1989_National_DRAM_Management_Handbook 1989 National DRAM Management Handbook
User Manual: 1989_National_DRAM_Management_Handbook
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~ National D Semiconductor 400017 A Corporate Dedication to Quality and Reliability National Semiconductor is an industry leader in the manufacture of high quality, high reliability integrated circuits. We have been the leading proponent of driving down IC defects and extending product lifetimes. From raw material through product design, manufacturing and shipping, our quality and reliability is second to none. We are proud of our success ... it sets a standard for others to achieve. Yet, our quest for perfection is ongoing so that you, our customer, can continue to rely on National Semiconductor Corporation to produce high quality products for your design systems. Charles E. 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Sporck President, Chief Executive Officer National Semiconductor Corporation DRAM MANAGEMENT 1989 Edition Dynamic Memory Control Error Detection and Correction Microprocessor Applications for the DP8408A/09A/17/18/19/28/29 Microprocessor Applications for the DP8420A/21A/22A Microprocessor Application for the NS32CG821 Physical Dimensionsl Appendices iii •• •II• TRADEMARKS Following is the most current list of National Semiconductor Corporation's trademarks and registered trademarks. Abuseable™ AnadigTM ANS-R-TRANTM APPSTM ASPECTTM Auto-Chem Defiasher™ BCPTM BI-FETTM BI-FET IITM BI-UNETM BIPLANTM BLCTM BLXTM Brite-LiteTM BTLTM CheckTrackTM CIMTM CIMBUSTM CLASICTM Clociu-'ChekTM COMBOTM COMBO ITM COMBO IITM COPSTM microcontrollers Datacheckerlll> DENSPAKTM DIBTM Digitalkerlll> DISCERNTM DISTILLTM DNRIII> DPVMTM ELSTARTM Embedded System Processor™ E-Z-UNKTM FACTTM FAIRCADTM FairtechTM FASTIII> 5-Star ServiceTM GENIXTM GNXTM HAMRTM HandiScan™ HEX3000TM HPCTM 13LIII> ICMTM INFOCHEXTM IntegrallSETM IntelisplayTM ISETM ISE/OSTM ISE/08TM ISE/1STM ISE32TM ISOPLANARTM ISOPLANAR-ZTM KeyScan™ LMCMOSTM M2CMOSTM Macrobus™ Macrocomponent™ MAXI-ROMIII> Meab'Chek™ MenuMaster™ Microbus™ data bus MICRO-DACTM ",talker™ Microtalker™ MICROWIRETM MICROWIRE/PLUSTM MOLETM MSTTM Naked-8™ Nationallll> National Semiconductorlll> National Semiconductor Corp. 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LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITIEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. NationalSemiconductorCorporatlon 2900 Semiconductor Drive, P.O. Box 58090, Santa Clara, Califomia 95052-8090 (408) 721-5000 TWX (910) 339-9240 National does not assume any responsibility for use of any circuitry described. no clrcuH patent Hcenses are Implied. and National reserves the right. at any time without notice, to change said circuitry or specifications. iv ~National ~ Semiconductor DRAM Management Introduction Today's large Dynamic Random Access Memory (DRAM) arrays require sophisticated high performance devices to provide timing access arbitration on board drive and control. National Semiconductor offers the broadest range of DRAM controllers with the highest "No-waitstate" performance available on the market. Controllers are available in Junction Isolated LS, Oxide Isolated ALS, and double metal CMOS for DRAMs from 64k bit through 4M bit devices, supporting memory arrays up to 64 Mbyte in size with only one LSIIVLSI device. For critical applications, National Semiconductor has developed several 16- and 32-bit Error Checking and Correction (ECG) devices to provide maximum data integrity. The DRAM Management Handbook contains complete product information. This includes the largest number and most complete set of DRAM control and ECC products, peripheral support devices and application notes detailing complete DRAM memory system design. v ~National ~ Semiconductor Introduction to VLSI Products E/homst/FDO! DRAM Ihnagem.nt Local Ante Network Communi- Graphics Display csBons Control ,.." TL/XX/0058-1 National Semiconductor VLSI products include complex peripheral circuits designed to serve a variety of applications. The VLSI products are especially well suited for microcomputer and microprocessor systems such as graphics workstations, personal computers, and many others. National Semiconductor VLSI devices are fully described in a series of databooks and handbooks. . Ethernet LANs. National Semiconductor offers a completely integrated solution for the IBM 370 class mainframes, System 3X and AS/400 systems for physical layer front end and processing of the IBM 3270/3299 "coaxial" and 5250 "twinaxial" protocols. National's family of UARTs provides high performance, low power serial data input/output interface. Among the books are the following titles: INTERFACE MASS STORAGE To drive the communications lines, National Semiconductor has drivers and receivers designed to meet all the major standards such as RS-232, RS-422, and RS-485. The National Semiconductor family of mass storage interface products offers the industry's highest performance and broadest range of products for Winchester hard disks, high performance ESDI and SCSI hard disks and floppy disks. Combined with CLASICTM, analog and high performance microcontroller devices, these products offer unparalleled solutions for integration. GRAPHICS The graphics chip set is designed to provide the highest level of performance with minimum demands and loading on the system CPU. The graphics system may be expanded to any number of color planes with virtually unlimited resolution. DRAM MANAGEMENT National Semiconductor offers the broadest range of DRAM controllers with the highest "No-waitstate" performance available on the market. For critical applications, National Semiconductor has developed several 16- and 32-bit Error Checking and Correction (ECC) devices to provide maximum data integrity. REAL TIME CLOCKS The RTC family provides a simple ,""P bus compatible interface to any system requiring accurate, reliable, on-going real time and calender functions. EMBEDDED SYSTEMS PROCESSORS National's Embedded System Processor™ family offers the most complete solution to 32-bit embedded processor needs via CPUs, slave processors, system peripherals, evaluation/development tools and software. Our total product system solution approach includes the hardware, software, and development support products necessary for your design. Evaluation board, in-system emulator, software development tools, and third party software are available now. MICROCONTROLLER As one of the broadest cost/performance product offerings in the industry today, National's microcontrollers provide the intelligence required for high performance applications such as laser printers, ISDN terminal adapters, floppy disks and SCSI hard disks. Complete support tools are available, including applications specific software, Designer's Kits, emulators, simulators, and development systems. Whether the application demands 4-, 8- or 16-bit performance, National has the right embedded control solution. LOCAL AREA NETWORKS, DATA COMMUNICATIONS, UARTS National Semiconductor provides a complete three-chip solution for an entire IEEE 802.3 standard for Ethernet/Thin vi ~Natlonal ~ Semiconductor Product Status Definitions Definition of Terms This data sheet contains the design specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. National Semiconductor Corporation reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. National Semiconductor Corporation reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. National Semiconductor Corporation reserves the right to make changes without further notice to any products herein to improve reliability, function or design. National does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. vii Table of Contents Alphanumeric Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Section 1 Dynamic Memory Control DRAM Controller Master Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DP8408A Dynamic RAM Controller/Driver....................................... DP8409A Multi-Mode Dynamic RAM Controller/Driver. . . . . .. . . . .. . . . . . . . . . . ... . .. . DP8417/NS32817/DP8418/NS32818/DP8419/NS32819/DP8419X/NS32819X 64k, 256k Dynamic RAM Controller/Drivers.................................... DP8428/NS32828/DP8429INS32829 1 Megabit High Speed Dynamic RAM Controller/Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DP8420AlDP8421A/DP8422A microCMOS Programmable 256k/1 M/4M Dynamic RAM Controller/Drivers. . . . . . . . . . . . . .. . ... . . .. . . . . . . . . . . .. . . . . . . . .. . . . . . . . . . NS32CG821 microCMOS Programmable 1M Dynamic RAM Controller/Driver........ DP8520A/DP8521A/DP8522A microCMOS Programmable 256k/1M/4M Video RAM Controller/Drivers (see Graphics Databook) ................................... 29F68 Dynamic RAM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54F /7 4F968 1 Mbit Dynamic RAM Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AN-305 Precautions to Take When Driving Memories. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AB-1 DP8408A/DP8409A1DP8417 /DP8418/DP8419/DP8428/DP8429 Application Hints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AB-9 DP8408A/DP8409A Fastest DRAM Access Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . Section 2 Error Detection and Correction 54F/74F420 Parallel Check Bit/Syndrome Bit Generator. .. . . . . . .. . . . . . .. . . . . . . . . . DP8400-2 E2C2 Expandable Error Checker/Corrector . . . . .. . . . . . .. . .. . . . . . .. . . . . . . DP8402A/DP8403/DP8404/DP8405 32-Bit Parallel Error Detection and Correction Circuits (EDAC's) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54F/74F632 32-Bit Parallel Error Detection and Correction Circuit. . . . . . . . . . . . . . . . . . AN-306 Expanding the Versatility of the DP8400 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AN-308 DP8400s in 64-Bit Expansion ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Section 3 Microprocessor Applications for the DP8408A/09A117/18/19/28/29 Microprocessor to DP8409A/17 118/19/28/29 Interface Selection Guide. . . . . . . . . . . . DP84300 Programmable Refresh Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DP84322 Dynamic RAM Controller Interface Circuit for the 68000 CPU ............. , DP84412 Dynamic RAM Controller Interface Series Circuit for the SeriGs 32000 CPU. . DP84422 Dynamic RAM Controller Interface Circuit for the 68000/008/010 CPUs .... DP84432 Dynamic RAM Controller Interface Circuit for the 8086/8088/80186/80188 CPUs .. . .. . . . . . .. .. . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . .. . DP84512 Dynamic RAM Controller Interface Circuit for the NS32332 . . . . . . . . . . . . . . . . DP84522 Dynamic RAM Controller Interface Circuit for the 68020 CPU . . . . . . . . . . . . . . DP84532 Dynamic RAM Controller Interface Circuit for the iAPX 286 CPU. . .. . . . . . . . . AN-309 InterfaCing the DP8408A1DP8409A to Various Microprocessors. . . . . . . . . . . . . AN-387 DP8400/DP8419 Error Correcting Dynamic RAM Memory System for the Series 32000 .............................................................. AN-411 Determining the Speed of the Dynamic RAM Needed When Interfacing the DP8419-80 to Most Major Microprocessors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AN-436 Dual Port Interface for the DP8417 /DP8418/DP8419/DP8428/DP8429 DRAM Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Section 4 Microprocessor Applications for the DP8420Al21A/22A AB-36 Exp!anation of National Semiconductor "PLAN" Software for Programming PALs..................................................................... AN-542 Interfacing the DP8420AlDP8421A/DP8422A to the NS320081NS32016/NS32C016/NS32032 and NS32132. . . . . . . . . . . . . . . . . . . . . . . . viii x 1-3 1-4 1-22 1-44 1-69 1-92 1-164 1-200 1-201 1-202 1-203 1-207 1-208 2-3 2-4 2-38 2-55 2-56 2-68 3-3 3-4 3-9 3-24 3-37 3-51 3-64 3-65 3-81 3-93 3-107 3-122 3-129 4-3 4-4 Table of Contents (Continued) Section 4 Microprocessor Applications for the DP8420Al21A122A (Continued) AN-543 Interfacing the DP8420AlDP8421A/DP8422A to the NS32332. . . . . . . . . . . .. . AN-541 Interfacing the DP8420AlDP8421 A/DP8422A to the NS32532 . . . . . . . . . . . . . . AN-540 A Dual Access NS32532 Error Detecting and Correcting Memory System. . . . . AN-538 Interfacing the DP8420AlDP8421 A/DP8422A to the 680001008/010 . . . . . . . . AN-615 Interfacing the DP8422A to the 68000-16 (Zero Wait State Burst Mode Access) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AN-539 Interfacing the DP8420AlDP8421 A/DP8422A to the 68020 ................ AN-616 Interfacing the DP8422A to the 68020 (Zero Wait State Burst Mode Access) . . AN-617 Interfacing the DP8422A to an Asynchronous Port B in a Dual 68020 System. . AN-537 Interfacing the DP8420AlDP8421A1DP8422A to the 68030 Microprocessor.. AN-535 A Dual Access DP8422A/68030/74F632 Error Detecting and Correcting Memory System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AN-544 Interfacing the DP8420A/DP8421 A/DP8422A to the 8086/186/88/188 Microprocessor ...... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AN-545 Interfacing the DP8420AlDP8421 A/DP8422A to the 80286 ................ AN-618 Interfacing the DP8420A/DP8421A/DP8422A to the 80286 Above 25 MHz, Including No Wait States in Burst Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AN-536 Interfacing the DP8420A/DP8421A/DP8422A to the 80386 ................ AN-619 Interfacing the DP8420A/DP8421 A/DP8422A to the 80386 (Zero Wait State Burst Mode Access) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AN-602 Interfacing the DP8420A/DP8421 A/DP8422A to the 29000 Utilizing the Burst Mode Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AN-546 Interfacing the DP8420A/DP8421A/DP8422A to the Z280/Z80000/Z8000 Microprocessor ...... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AN-642 Interfacing the Dual Port DP8422A to the TMS320C30 and the VM E Bus ..... Section 5 Microprocessor Application for the NS32CG821 AN-576 Interfacing the NS32CG821 to the NS32CG16 . . . . . . . . . .. . . . . . . . . . . . . . . . . . Section 6 Physical Dimensions! Appendices Physical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bookshelf Distributors ix 4-11 4-24 4-34 4-40 4-56 4-61 4-82 4-86 4-90 4-98 4-113 4-117 4-129 4-138 4-154 4-170 4-183 4-187 5-3 6-3 Alpha-Numeric Index 29F68 Dynamic RAM Controller ........................................................... 1-201 54F420 Parallel Check Bit/Syndrome Bit Generator ............................................ 2-3 54F632 32-Bit Parallel Error Detection and Correction Circuit ................................... 2-55 54F968 1 Mbit Dynamic RAM Controller .................................................... 1-202 74F420 Parallel Check Bit/Syndrome Bit Generator ............................................ 2-3 74F632 32-Bit Parallel Error Detection and Correction Circuit ................................... 2-55 74F9681 Mbit Dynamic RAM Controller .................................................... 1-202 AB-1 DP8408A1DP8409A1DP8417/DP8418/DP8419/DP8428/DP8429 Application Hints ........ 1-207 AB-9 DP8408A/DP8409A Fastest DRAM Access Mode ...................................... 1-208 AB-36 Explanation of National Semiconductor "PLAN" Software for Programming PALs ............ 4-3 AN-305 Precautions to Take When Driving Memories ........................................ 1-203 AN-306 Expanding the Versatility of the DP8400 .............................................. 2-56 AN-308 DP8400s in 64-Bit Expansion ....................................................... 2-68 AN-309 Interfacing the DP8408A/DP8409A to Various Microprocessors ......................... 3-93 AN-387 DP8400/DP8419 Error Correcting Dynamic RAM Memory System for the Series 32000 ... 3-107 AN-411 Determining the Speed of the Dynamic RAM Needed When Interfacing the DP8419-80 to Most Major Microprocessors ............................................... 3-122 AN-436 Dual Port Interface for the DP8417/DP8418/DP8419/DP8428/DP8429 DRAM Controller. 3-129 AN-535 A Dual Access DP8422A168030174F632 Error Detecting and Correcting Memory System .. 4-98 AN-536 Interfacing the DP8420A/DP8421A1DP8422A to the 80386 ........................... 4-138 AN-537 Interfacing the DP8420AlDP8421A1DP8422A to the 68030 Microprocessor .............. 4-90 AN-538 Interfacing the DP8420AlDP8421A1DP8422A to the 68000/008/010 .................... 4-40 AN-539 Interfacing the DP8420A/DP8421A1DP8422A to the 68020 ............................ 4-61 AN-540 A Dual Access NS32532 Error Detecting and Correcting Memory System ................. 4-34 AN-541 Interfacing the DP8420AlDP8421 AI DP8422A to the NS32532 .......................... 4-24 AN-542 Interfacing the DP8420AlDP8421A1DP8422A to the NS32008/NS320161NS32C0161NS32032 and NS32132 ..................................... 4-4 AN-543 Interfacing the DP8420AlDP8421A/DP8422A to the NS32332 .......................... 4-11 AN-544 Interfacing the DP8420AlDP8421 AI DP8422A to the 8086/186/88/188 Microprocessor .. 4-113 AN-545 Interfacing the DP8420AlDP8421A/DP8422A to the 80286 ........................... 4-117 AN-546 Interfacing the DP8420A/DP8421A1DP8422A to the Z280/Z80000/Z8000 Microprocessor ....................................................................... 4-183 AN-576 Interfacing the NS32CG821 to the NS32CG16 ......................................... 5-3 AN-602lnterfacing the DP8420AlDP8421 AI DP8422A to the 29000 Utilizing the Burst Mode Access .............................................................................. 4-170 AN-615 Interfacing the DP8422A to the 68000-16 (Zero Wait State Burst Mode Access) ........... 4-56 AN-616 Interfacing the DP8422A to the 68020 (Zero Wait State Burst Mode Access) .............. 4-82 AN-617 Interfacing the DP8422A to an Asynchronous Port B in a Dual 68020 System ............. 4-86 AN-618 Interfacing the DP8420AlDP8421 AlDP8422A to the 80286 Above 25 MHz, Including No Wait States in Burst Mode ........................................................... 4-129 AN-619 Interfacing the DP8420AlDP8421 A/DP8422A to the 80386 (Zero Wait State Burst Mode Access) .............................................................................. 4-154 AN-642 Interfacing the Dual Port DP8422A to the TMS320C30 and the VME Bus ................ 4-187 DP8400-2 E2C2 Expandable Error Checker/Corrector .......................................... 2-4 DP8402A 32-Bit Parallel Error Detection and Correction Circuits (EDAC's) ....................... 2-38 DP8403 32-Bit Parallel Error Detection and Correction Circuits (EDAC's) ......................... 2-38 DP8404 32-Bit Parallel Error Detection and Correction Circuits (EDAC's) ......................... 2-38 DP8405 32-Bit Parallel Error Detection and Correction Circuits (EDAC's) ......................... 2-38 DP8408A Dynamic RAM Controller/Driver .................................................... 1-4 DP8409A Multi-Mode Dynamic RAM Controller/Driver ......................................... 1-22 DP8417 64k Dynamic RAM Controller/Driver ................................................. 1-44 x Alpha-Numeric Index (Continued) DP8418 64k Dynamic RAM Controller/Driver ................................................. 1·44 DP8419 256k Dynamic RAM Controller/Driver ............................................... 1·44 DP8419X 256k Dynamic RAM Controller/Driver .............................................. 1·44 DP8420A microCMOS Programmable 256k Dynamic RAM Controller/Driver ..................... 1·92 DP8421 A microCMOS Programmable 1M Dynamic RAM Controller/Driver ....................... 1·92 DP8422A microCMOS Programmable 4M Dynamic RAM Controller/Driver ....................... 1·92 DP84281 Megabit High Speed Dynamic RAM Controller/Driver ................................ 1·69 DP84291 Megabit High Speed Dynamic RAM Controller/Driver ................................ 1·69 DP8520A microCMOS Programmable 256k Video RAM Controller/Driver (see Graphics Databook) ............................................................................ 1·200 DP8521A microCMOS Programmable 1M Video RAM Controller/Driver (see Graphics Databook) .. 1·200 DP8522A microCMOS Programmable 4M Video RAM Controller/Driver (see Graphics Databook) .. 1·200 DP84300 Programmable Refresh Timer ...................................................... 3·4 DP84322 Dynamic RAM Controller Interface Circuit for the 68000 CPU ........................... 3·9 DP84412 Dynamic RAM Controller Interface Series Circuit for the Series 32000 CPU .............. 3·24 DP84422 Dynamic RAM Controller Interface Circuit for the 68000/008/010 CPUs ................ 3·37 DP84432 Dynamic RAM Controller Interface Circuit for the 8086/8088/80186/80188 CPUs ........ 3·51 DP84512 Dynamic RAM Controller Interface Circuit for the NS32332 ............................ 3·64 DP84522 Dynamic RAM Controller Interface Circuit for the 68020 CPU .......................... 3·65 DP84532 Dynamic RAM Controller Interface Circuit for the iAPX 286 CPU ........................ 3·81 NS32CG821 microCMOS Programmable 1M Dynamic RAM Controller/Driver ................... 1·164 NS32817 64k Dynamic RAM Controller/Driver ............................................... 1·44 NS32818 64k Dynamic RAM Controller/Driver ............................................... 1·44 NS32819 256k Dynamic RAM Controller/Driver .............................................. 1·44 NS32819X 256k Dynamic RAM Controller/Driver ............................................. 1·44 NS328281 Megabit High Speed Dynamic RAM Controller/Driver ............................... 1·69 NS328291 Megabit High Speed Dynamic RAM Controller/Driver ............................... 1·69 xi Section 1 Dynamic Memory Control Section 1 Contents DRAM Controller Master Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DP8408A Dynamic RAM Controller/Driver............................................. DP8409A Multi-Mode Dynamic RAM Controller/Driver.................................. DP8417INS32817 /DP8418/NS32818/DP8419/NS32819/DP8419XINS32819X 64k, 256k Dynamic RAM Controller/Drivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DP8428INS32828/DP8429/NS32829 1 Megabit High Speed Dynamic RAM Controller/Drivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DP8420AlDP8421A/DP8422A microCMOS Programmable 256k/1 M/4M Dynamic RAM Controller/Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NS32CG821 microCMOS Programmable 1M Dynamic RAM Controller/Driver. .. . . . . .. .. . .. DP8520AlDP8521 AlDP8522A microCMOS Programmable 256k/1 M/4M Video RAM Controller/Drivers (see Graphics Databook) ......................................... 29F68 Dynamic RAM Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 54F174F9681 MbitDynamic RAM Controller.......................................... AN-305 Precautions to Take When Driving Memories ................................... AB-1 DP8408A/DP8409A1DP8417 /DP8418/DP8419/DP8428/DP8429 Application Hints. . . AB-9 DP8408A1DP8409A Fastest DRAM Access Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-2 1-3 1-4 1-22 1-44 1-69 1-92 1-164 1-200 1-201 1-202 1-203 1-207 1-208 DRAM Controller Master Selection Guide The data below is intended to highlight the key differentiable features of each DRAM ControllerIDriver offered by National Semiconductor. All NSC DRAM controllers integrate onboard delay line timing. high capacitive drive. row/column muxing logic. refresh counter. row and column input latches. memory bank select logic. As a result of the family feature commonality. most devices offer pin for pin up/downward compatiblity. Beyond this however. the process and design differences between the devices result in a broad selection of feature and performance options for the best system fit. Device # & Speed Options '" DRAMS Supported Process Typ Icc DP8408A A-2 A-3 16.64k DP8409A A-2 A-3 16. 64. 256k DP8417-80 -70 16.64. 256k DP8418-80 -70 16. 64. 256k DP8419-80 -70 16. 64. 256k DP8420A. DP8421A 16. 64. 256k. 1 Mega Bit. 4 MegaBit 2,... CMOS 16. 64. 256k Oxide Isolated (ALS) 150mA Oxide Isolated (ALS) 150mA & DP8422A DP8428-80 -70 & 1 MegaBit DP8429-80 -70 & 1 MegaBit 16. 64. 256k Junction Isolated (S) 210mA Junction Isolated (S) 210mA Oxide Isolated (ALS) 150mA Oxide Isolated (ALS) 150mA Oxide Isolated (ALS) 150mA 5mA A.C. Specified Word Width MaxRAS to CAS Out > Fast I Slow Mode Mode Guaranteed Row Address Hold > Fast I Slow Mode Mode 4 Banks of 16 Bit Data wi 6 Bit ECCea. 105 ns/125 ns 85 ns/100 ns 120 ns/145 ns 20 ns/30 ns 12 ns/20 ns 20 ns/30 ns +5V ±5% 4 Banks of 16 Bit Data wi 6 Bit ECCea. 105 ns/125 ns 85 ns/100 ns 120 ns/145 ns 20 ns/30 ns 12 ns/20 ns 20 ns/30 ns +5V ±5% 4 Banks of 16 Bit Data wi 6 Bit ECCea. 63 ns/80 ns 50 ns/72 ns 15 ns/25 ns 15 ns/25 ns +5V ±10% 2 Banks of 32 Bit Data wi 7 Bit ECCea. 63 ns/80 ns 50 ns172 ns 15 ns/25 ns 15 ns/25 ns +5V ±10% 4 Banks of 16 Bit Data wi 6 Bit ECCea. 63 ns/80 ns 50 ns172 ns 15 ns/25 ns 15 ns/25 ns +5V ±10% 53 ns/63 ns 15 ns/25 ns 2 Banks of 32 Bit Data wi 7 Bit ECC ea. 63 ns/80 ns 50 ns172 ns 15 ns/25 ns 15 ns/25 ns +5V ±10% 4 Banks of 16 Bit Data w/ 6 Bit ECC ea. 63 ns/80 ns 50 ns172 ns 15 ns/25 ns 15 ns/25 ns +5V ±10% 2 Banks of 32 Bit Data w/ 7 Bit ECCea. Operating Temp Range Vcc +5V ±10% Package Page No. [ 48N ] 48D 1-4 [ 48N ] 48D 68V 1-22 0°-70°C ] -400-+85°C -55°- + 125°C [ 48 N ] 48D 68V 1-44 0°-70°C ] -400-+85°C -55°-+ 125°C [ 48 N ] 48D 68V 1·44 0°-70°C ] -400-+85°C -55°-+ 125°C [ 48 N ] 48D 68V 1·44 0°-70°C ] -40°_+ 85°C -55°_+ 125°C [ 68V ] 0°-70°C ] -40°- + 85°C -55°- + 125°C [ 52D ] 68V 1-69 0°-70°C ] -400-+85°C -55°- + 125°C [ 52D ] 68V 1-69 [ 0"-70°C 0°-85°C [ 0°-70°C 0°-85°C [ [ [ [ [ [ ] ] 1-92 *All AC valves shown factor in worst case loading (including all ouputs switching simultaneously), operating temperature, and Vee supply variables. All delays assume the use of National's on-board automatic timing and delay line logic aHhough external delay line control timing is allowed and supported. ap!n~ UO!I:>alas JalSew JaIlOJIUO:) WVI:IO ~ ~ ~National ~ ~ Semiconductor DP8408A Dynamic RAM Controller IDriver General Description Operational Features Dynamic memory system designs, which formerly required several support chips to drive the memory array, can now be implemented with a Single IC ... the DPB40BA Dynamic RAM Controller/Driver. The DPB40BA is capable of driving all 16k and 64k Dynamic RAMs (DRAMs). Since the DPB40BA is a one-chip solution (including capacitive-load drivers), it minimizes propagation delay skews, the major performance disadvantage of multiple-chip memory drive and control. • All DRAM drive functions on one chip-minimizes skew on outputs, maximizes AC performance • On-chip capacitive-load drives (specified to drive up to BB DRAMs) • Drive directly all 16k and 64k DRAMs • Capable of addressing 64k and 256k words • Propagation delays of 25 ns typical at 500 pF load • CAS goes low automatically after column addresses are valid if desired • Auto Access mode provides RAS, Row to Column, select, then CAS automatically and fast • WE follows WIN unconditionally-offering READ, WRITE or READ-MODIFY-WRITE cycles • On-chip 8-bit refresh counter with selectable End-ofCount (127 or 255) • End-of-Count indicated by RF I/O pin going low at 127 or 255 • Low input on RF I/O resets 8-bit refresh counter • CAS inhibited during refresh cycle • Fall-through latches on address inputs controlled by ADS • TRI-STATE outputs allow multi-controller addressing of memory • Control output signals go high-impedance logic "1" when disabled for memory sharing • Power-up: counter reset, control Signals high, address outputs TRI-STATE, and End-of-Count set to 127 The DP840BA's 6 modes of operation offer a wide selection of DRAM control capabilities. Memory access may be controlled externally or on-chip automatically; an on-chip refresh counter makes refreshing less complicated. The DP840BA is a 48-pin DRAM Controller/Driver with 8 multiplexed address outputs and control signals. It consists of two B-bit address latches, an 8-bit refresh counter, and control logic. All output drivers are capable of driving 500 pF loads with propagation delays of 25 ns. The DPB408A timing parameters are specified driving the typical load capacitance of 88 DRAMs, including trace capacitance. The DP8408A has 3 mode-control pins: M2, Ml, and MO, where M2 is in general REFRESH. These 3 pins select 6 modes of operation. Inputs Bl and BO in the memory access modes (M2 = 1), are select inputs which select one of four RAS outputs. During normal access, the 8 address outputs can be selected from the Row Address Latch or the Column Address Latch. During refresh, the 8-bit on-Chip refresh counter is enabled onto the address bus and in this mode all RAS outputs are selected, while CAS is inhibited. The DP8408A can drive up to 4 banks of DRAMs, with each bank comprised of 16k's, or 64k·s. Control signal outputs RAS, CAS, and WE are provided with the same drive capability. Each RAS output drives one bank of DRAMs 50 that the four RAS outputs are used to select the banks, while CAS, WE, and the multiplexed addresses can be connected to all of the banks of DRAMs. This leaves the non-selected banks in the standby mode (less than one tenth of the operating power) with the data outputs in TRI-STATE®. Only the bank with its associated RAS low will be written to or read from. Mode Features • 6 modes of operation: 3 access, 1 refresh, and 2 set-up • 2 externally controlled modes: 1 access (Mode 4) and 1 refresh (Modes 0, 1 , 2) • 2 auto-access modes RAS ~ R/C ~ CAS automatic, with tRAH = 20 or 30 ns minimum (Modes 5, 6) • Externally controlled AII-RAS Access modes for memory initialization (Mode 3) • End-of-Count value of Refresh Counter set by Bl and BO (Mode 7) DP8408A Interface Between System & DRAM Banks ~6~i~~L ~ RAM CONTROL 6 10 SYSTEM . '1 DP84DBA DYNAMIC RAM CDNTROLLERI DRIVER 50DpF DRIVE RAM ADDRESS SYSTEM ADDRESS MEMORY 8 I 16k DR 64k DYNAMIC RAM BANKS TLlF/B40B-1 1-4 Block Diagram II ROW ADDRESS INPUT LATCH RO-7 ADS 1 CO-7 \ • COLUMN ADDR. INPUT LATCH I I H I I I I l 8·BIT REFRESH COUNTER HIGH CAPACITIVE DRIVE CAPABILITY OUTPUTS WHEN ENABLED ;1~ .... l I ' I I I I I t- I I 00-7 ~ • INDICATES THAT THERE IS A 3kQ PULL·UP RESISTOR ON THESE OUTPUTS WHEN THEY ARE DISABLED I ~ REFRESH r-- ~RAS3 ~RAS2 I-- ~RASI I-- RAS DECODER t 81_ BANK SELECT 8 0 _ INPUT LATCH cs_ t ~- ff- I- - I- r--;:z. +RASIN t CONTROL LOGIC + WIN RFtO + L M2(RFSH) ..... .. iIASIN _ R/C_ CAIiN_ ...... + I + I Ml MO ..... RAS 0 CAS OUTPUT ENABLE iNE TLlF/B40B-2 TABLE I. DP8408A Mode Select Options Mode (RFSH) M2 M1 MO 0 0 0 0 1 0 0 1 2 0 1 0 Mode of Operation Conditions Externally Controlled Refresh RFI/O AII-RAS Active = EOC 3 0 1 1 Externally Controlled AII-RAS Write 4 1 0 0 Externally Controlled Access Active RAS defined by Table II 5 1 0 1 Auto Access, Slow tRAH Active RAS defined by Table II 6 1 1 0 Auto Access, Fast tRAH Active RAS defined by Table II 7 1 1 1 Set End of Count See Table III for Mode 7 1·5 • ! Q Pin Definitions Vee, GND, GNo-Vee = 5V ±5%. The three supply pins have been assigned to the center of the package to reduce voltage drops, both DC and AC. There are also two ground pins to reduce the low level noise. The second ground pin is located two pins from Vee, so that decoupling capacitors can be inserted directly next to these pins. It is important to adequately decouple this device, due to the high switching currents that will occur when all 8 address bits change in the same direction simultaneously. A recommended solution would be a 1 ,..F multilayer ceramic capacitor in parallel with a low-voltage tantalum capaCitor, both connected as close as possible to pins 36 and 38 to reduce lead inductance. See Figure below. WIN: Write Enable Input. WE: Write Enable Output-Buffered output from WIN.' CAS: Column Address Strobe Output-In Modes 5 and 6, CAS goes low following valid column address. In Modes 3 and 4, it transitions low after RIC goes low, or follows CASIN going low if RIC is already low. CAS is high during refresh.' RAS 0-3: Row Address Strobe Outputs-Selects a memory bank decoded from Bl and BO (see Table II), if RFSH is high. If RFSH is low, all banks are selected" BO, B1: Bank Select Inputs-Strobed by ADS. Decoded to enable one of the RAS outputs when RASIN goes low. Also used to define End-of·Count in Mode 7 (Table III). ...-----.., 1''These outputs may need damping resistors to prevent overshoot, undershoot. See AN·aDS "Precautions to Take When Driving Memories." Vee (PIN 36) O-------~ 'MULTILAYER CERAMIC GND (PINS 38, 13) I 'TANTALUM _ T...L TABLE II. Memory Bank Decode Bank Select (Strobed by ADS) 0 TLlF/B40B-3 "Capacitor values should be chosen depending on the particular application. RO-R7: Row Address Inputs. CO-C7: Column Address Inputs. QO-Q7: Multiplexed Address Outputs-Selected from the Row Address Input Latch, the Column Address Input Latch, or the Refresh Counter.' RASIN: Row Address Strobe Input-Enables selected RAS n output when M2 (RFSH) is high, or all RAS n outputs when RFSH is low. Enabled RAS n Bl 80 0 0 1 1 0 1 0 1 RASa RAS1 RAS2 RAS3 Connection Diagram Dual In-Line Package :! ~SIN Ric: Row/Column Select Input-Selects either the row or column address input latch onto the output bus. CASIN: Column Address Strobe Input-Inhibits CAS out· put when high in Modes 4 and 3. In Mode 6 it can be used to prolong CAS output. ~: 46 110 45 WIN 44 WE 43 DO 42 Dl ADS: Address (Latch) Strobe Input-Row Address, Col· umn Address, and Bank Select Latches are fall·through with ADS high; Latches on high·to·low transition. CS: Chip Select Input-TRI·STATE the Address Outputs and puts the control signal into a high·impedance logic" 1" state when high (except in Mode 0); enables all outputs when low. 41 02 DP8408A 40 03 39 04 38 GND 37 05 36 VCC 35 06 34 07 33 NC MO, M1, M2: Mode Control Inputs-These 3 control pins determine the 6 major modes of operation of the DP8408A as depicted in Table I. 32 31 30 29 RF lIo-The 1/0 pin functions as a Reset Counter Input when set low from an external open·collector gate, or as a flag output. The flag goes active·low when M2 = 0 and the End·of-Count output is at 127 or 255 (see Table III). 26 Bl CAS RAS3 RAS2 RASI 28 RASo 27 BD 25 NC NC = No Connection TLlF/B40B-4 Top View Order Number DP8408AD, DP8408AN or DP8408AN·3 See NS Package Number D48A or N48A 1-6 Conditions for all Modes DP8408A DRIVING ANY 16K OR 64K DRAMS INPUT ADDRESSING The address block consists of a row-address latch, a columnaddress latch, and a resettable refresh counter. The address latches are fall-through when ADS is high and latch when ADS goes low. If the address bus contains valid addresses until after the valid address time, ADS can be permanently high. Otherwise ADS must go low while the addresses are still valid. The DP8408A can drive any 16k or 64k DRAMs. All 16k DRAMs are basically the same configuration, including the newer 5V-only version. Hence, in most applications, different manufacturers' DRAMs are interchangeable (for the same supply-rail chips), and the DP8408A can drive all 16k DRAMS (see Figure la). There are three basic configurations for the 5V-only 64k DRAMs: a 128-row by 512-column array with an on-RAM refresh counter, a 128-row by 512-column array with no onRAM refresh counter, and a 256-row by 256-column array with no on-RAM refresh counter. The DP8408A can drive all three configurations, and at the same time allows them all to be interchangeable (as shown in Figure lb and Ie), providing maximum flexibility in the choice of DRAMs. Since the 8-bit on-chip refresh counter can be used as a 7-bit refresh counter for the 128-row configuration, or as an 8-bit refresh counter for the 256-row configuration, the on-RAM refresh counter (if present) is never used. As long as 128 rows are refreshed every 2 ms (i.e. 256 rows in 4 ms) all DRAM types are correctly refreshed. When the DP8408A is in a refresh mode, the RF I/O pin indicates that the on-chip refresh counter has reached its end-of-count. This end-of-count is selectable as 127 or 255 to accommodate 16k or 64k DRAMs, respectively. Although the end-of-count may be chosen to be either of these values, the counter is not reset and always counts to 255 before rolling over to zero. In normal memory access operation, RASIN and R/C are initially high. When the address inputs are enabled into the address latches, the row addresses appear on the Q outputs. The address strobe also inputs the bank-select address, (BO and Bl). If CS is low, all outputs are enabled. When CS is transitioned high, the address outputs go TRISTATE and the control outputs first go high through a low impedance, and then are held by an on-chip high impedance. This allows output paralleling with other DP8408As for multi-addressing. All outputs go active about 50 ns after the chip is selected again. If CS is high, and a refresh cycle begins, all the outputs become active until the end of the refresh cycle. DRIVE CAPABILITY The DP8408A has timing parameters that are specified with up to 600 pF loads. In a typical memory system this is equivalent to about 88, 5V-only DRAMs, with trace lengths kept to a minimum. Therefore, the chip can drive four banks each of 16 or 22 bits, or two banks of 32 or 39 bits, or one bank of 64 or 72 bits. READ, WRITE AND READ-MODIFY-WRITE CYCLES Less loading will slightly reduce the timing parameters, and more loading will increase the timing parameters, according to the graph of Figure 6. The AC performance parameters are specified with the typical load capacitance of 88 DRAMs. This graph can be used to extrapolate the variations expected with other loading. The output signal, WE, determines what type of memory access cycle the memory will perform. If WE is kept high while CAS goes low, a read cycle occurs. If WE goes low before CAS goes low, a write cycle occurs and data at DI (DRAM input data) is written into the DRAM as CAS goes low. If WE goes low later than tewD after CAS goes low, first a read occurs and DO (DRAM output data) becomes valid; then data DI is written into the same address in the DRAM when WE goes low. In this read-modify-write case, DI and DO cannot be linked together. The type of cycle is therefore controlled by WE, which follows WIN. Because of distributed trace capacitance and inductance and DRAM input capacitance, current spikes can be created, causing overshoots and undershoots at the DRAM inputs that can change the contents of the DRAMs or even destroy them. To remove these spikes, a damping resistor (low inductance, carbon) can be inserted between the DP8408A driver outputs and the DRAMs, as close as possible to the DP8408A. The values of the damping resistors may differ between the different control outputs; RAS's CAS, Q's and WE. The damping resistors should be determined by the first prototypes (not wire-wrapped due to larger distributed capacitance and inductance). The best values for the damping resistors are the critical values giving a critically damped transition on the control outputs. Typical values for the damping resistors will be between 150 and 1000, the lower the loading the higher the value. (For more information, see AN-305 "Precautions to Take When Driving Memories.") POWER-UP INITIALIZE When Vee is first applied to the DP8408A, an initialize pulse clears the refresh counter, the internal control flip-flops, and sets the End-of-Count of the refresh counter to 127 (which may be changed via Mode 7). As Vee increases to about 2.3V, it holds the output control signals at a level of one Schottky diode-drop below Vee, and the output address to TRI-STATE. As Vee increases above 2.3V, control of these outputs is granted to the system. 1-7 II I :i o ..,. CO a. Q DP8408A Driving any 16k or 64k Dynamic RAMs , .. IJ CAS ~ ~ 1m ROWS I COLUMNS -t REFRESH COUNTER ~I COL. OECODE 7 ADDRESS ORIVERS R 128 0 W 128 16K 0 ARRAY E C 7 7 ADDRESS BUS 7 +12Vor +5V 16K OYNAMIC RAMS DP8408A TLlF/8408-S FIGURE 1a. DP8408A with any 16k DRAMS [~AS LATCHES 8 COLUMN ADDRESSE A LATCHES 7 ROW+1 COLUMN ADDRESS- CAS ~~ I r+1 f-t - ROWS lIAS COLUMNS REFRESH COUNTER 8 B ADDRESS DRIVERS -- I COL!CODE1J R 512 0 W 128 64 K ARRAY 0 E C 8 ADDRESS BUS 7 IF, DN·CHIP REFRESH COUNTER, NOT USED +5 V 64 K DYNAMIC RAMS DP8408A ONLY LS 7 BITS OF REFRESH COUNTER USED FOR THE 7 ROW ADDRESSES. MSB NOT USED BUT CAN TOGGLE TL/F/8408-6 FIGURE 1b. DP8408A with 128 Row X 512 Column 64k DRAM CAS ~ I ROWS COLUMNS 12B ROWS lOR 25~NR~re~ - . ~REFRESH ~I ~ 1m 8 ADDRESS ORIVERS B ..... + B ADDRESS BUS R 0 W 0 256 E B COUNTER C 1 COLUMN DECODE 256 - 64K ARRAY +5V 64K DYNAMIC RAMS 0 IN 4MSI I OP8408A ALL 8 BITS OF REFRESH COUNTER USED I~ I I I TL/F/8408-7 FIGURE 1c. DP8408A with 256 X 256 Column 64k DRAM 1-8 Functional Mode Descriptions Note: All delay parameters stated in text refer to the DPB40BA. Substitute the respective delay numbers for the DPB40B-2 or DPB40B-3 when using these devices. dress and RAS lines. For the load specified in the switching characteristics of this data sheet, 10 ns is sufficient. Refer to Figure 2. MODES 0, 1, 2 - EXTERNALLY CONTROLLED REFRESH To perform externally controlled burst refresh, RASIN is toggled while RFSH is held low. The refresh counter increments with RASIN going low to high, so that the DRAM rows are refreshed in succession by RASIN going high to low. In this mode, the input address latches are disabled from the address outputs and the refresh counter is enabled. When RAS occurs, the enabled row in the DRAM is refreshed. In the Externally Controlled Refresh mode, all RAS outputs are enabled following RASIN, and CAS is inhibited. This refreshes the same row in all four banks. The refresh counter increments when either RASIN or RFSH goes lowto-high after a refresh. RF I/O goes low when the count is 127 or 255, as set by End-of-Count (see Table III), with RASIN and RFSH low. To reset the counter to all zeros, RF I/O is set low through an external open-collector driver. MODE 3 - EXTERNALLY CONTROLLED ALL·RAS WRITE This mode is useful at system initialization. The memory address is provided by the processor, which also performs the incrementing. All four RAS outputs follow RASIN (supplied by the processor), strobing the row address into the DRAMs. R/C can now go low, while CASIN may be used to control CAS (as in the Externally Controlled Access mode), so that CAS strobes the column address contents into the DRAMs. At this time WE should be low, causing the data to be written into all four banks of DRAMs. At the end of the write cycle, the input address is incremented and latched by the DP8408A for the next write cycle. During refresh, RASIN and RFSH must be skewed transitioning low such that the refresh address is valid on the address outputs of the controller before the RAS outputs go low. The amount of time that RFSH should go low before RASIN does depends on the capacitive loading of the ad- ° INDICATES DYNAMIC RAM PARAMETERS 1-·-----IRCo-----~·1 INPUTS RASIN ~ li-.----IRASINL----i-I-------------- I -"':"-'1 1-IlIASINH-1 ~I--~I---------+I~ miN AND R/~ OUTPUTS I I RAS 0 I ALLm'sLOW ---+1 I -I tRDHNC OLD COLUMNS .+1 -------JI COUNTER RESET • REFRESH COUNT. I---IIRFLCT RFIIO II IRASO---_-_~IIIIIIr-_-IRF-Pd-H-i------------ FIRFPdL REFRESH COUNT. REFRESH CTR 00-7 1- - - - - - - -tRFpdH 1 1-IRPo-1 HAS 1,2, 3 11---7 -I I 1 L ___ • _____________ I i-IRLEOC I -I ~ I r-IRHEOC END OF COUNT LOW IF •• 127, 255 COUNTER RESET INPUT FROM OPEN COLLECTOR TL/F/8408-8 FIGURE 2_ External Control Refresh Cycle (MODES 0,1,2) 1-9TL/F /8408-10 FIGURE 4a. Read Cycle Timing (Mode 4) INPUTS "INDICATES DYNAMIC RAM PARAMETERS ADS (ALEI RIC DRAM DATA IN OUTPUTS liAS 0.1.2.3 00·7 -~-+--J.----_4--.[_;;;;;'::;t-r--;....;--r_----....!..--"-----l ===~ TLiF/8408-11 FIGURE 4b. Write Cycle Timing (Mode 4) 1·11 Functional Mode Descriptions (Continued) plexed address bus. After the row address has been held for tRAH, (the Row-Address hold-time of the DRAM), the column address is set up and then CAS occurs. This is all performed automatically by the DP8408A in this mode. MODE 5-AUTOMATIC ACCESS The Auto Access mode has two advantages over the Externally Controlled Access mode, due to the fact that all outputs except WE are initiated from RASIN. First, inputs RIC and CASIN are unnecessary. Secondly, because the output control signals are derived internally from one input signal (RASiN), timing-skew problems are reduced, thereby reducing memory access time substantially or allowing use of slower DRAMs. The automatic access features of Mode 5 (and Mode 6) of the DP8408A make DRAM accessing appear essentially "static". AUTOMATIC ACCESS CONTROL Provided the input address is valid as ADS goes low, RASIN can go low any time after ADS. This is because the selected RAS occurs typically 27 ns later, by which time the row address is already valid on the address output of the DP8408A. The Address Setup-Up time (tASA), is 0 ns on most DRAMs. The DP8408A in this mode (with ADS and RASIN edges simultaneously applied) produces a minimum tASR of 0 ns. This is true provided the input address was valid tASA before ADS went low (see Figure Sa). The major disadvantage of DRAMs compared to static RAMs is the complex timing involved. First, a RAS must occur with the row address previously set up on the multi- Next, the row address is disabled after tRAH (30 ns minimum); in most DRAMs, tRAH minimum is less than 30 ns. The column address is then set up and tAse later, CAS Timing Diagram l-tADS----I ... ·-----tRICL------<~1 ADS ADDRE~~WUTS/---< >---+------..l---READ----I---++---- COLUMNS VALID tASC I t=-- - -WRITE-- tCAC· DATA OUTPUT----------~------------< 1------tRAC·------1 TL/F/8408-12 >II Indicates Dynamic RAM Parameters FIGURE 5a. Modes 5, 6 Timing (CAS IN) High in Mode 6 1-12 Functional Mode Descriptions (Continued) occurs. The only other control input required is WIN. When a write cycle is required, WIN must go low at least 30 ns before CAS is output low. fast 16k or 64k DRAMs (which have a tRAH of IOns to 15 ns) in applications requiring fast access times; RASIN to CAS is typically 105 ns. This gives a total typical delay from: input address valid to RASIN (15 ns); to RAS (27 ns); to rows held (50 ns); to columns valid (25 ns); to CAS (23 ns) = 140 ns (that is, 125 ns from RASIN. All of these typical figures are for heavy capacitive loading, of approximately 88 DRAMs. This mode is therefore extremely fast. The external timing is greatly simplified for the memory system designer: the only system signal required is RASIN. In this mode, the RIC pin is not used, but CASIN is used to allow an extended CAS after RAS has already terminated. Refer to Figure 5b. This is desirable with fast cycle-times where RAS has to be terminated as soon as possible before the next RAS begins (to meet the precharge time, or tRP, requirements of the DRAM). CAS may then be held low by CASIN to extend the data output valid time from the DRAM to allow the system to read the data. CASIN subsequently going high ends CAS. If this extended CAS is not required, CASIN should be set high in Mode 6. MODE 6-FAST AUTOMATIC ACCESS The Fast Access mode is similar to Mode 5, but has a faster tRAH of 20 ns, minimum. It therefore can only be used with Timing Diagram l-tAOS-I·,~~~~~-tRICl-~~~~-1 INPUTS ADS ___ J tCRS OUTPUTS 00-7 - - WRITE - - -tOFF' tCAC' DATA DUTPUT---------------------r----------------------< VALID (READI 1------tRAC'-----_1 "'Indicates Dynamic RAM Parameters TL/F/8408-13 FIGURE 5b_ Mode 6 Timing, Extended CAS 1-13 I Functional Mode Descriptions (Continued) MODE 7-SET END·OF·COUNT 10 The End-of-Count can be externally selected In Mode 7, using ADS to strobe In the respective value of Bl and BO (see Table III). With Bl and BO the same EOC Is 127; with Bl =0 and BO= 1, EOC is 255; and with Bl = 1 and BO=O, EOC Is 127. This selected value of EOC will be used until the next Mode 7 selection. At power-up the EOC is automatically set to 127 (Bl and BO set to 11). 5 • -5 TABLE III. Mode 7 Bank Select (Strobed by ADS) End of Count Selected Bl BO 0 0 127 0 1 255 1 0 127 1 1 127 V / 0 V -10 0 V zoo / /' 400 600 800 1000 CpF TL/F/8408-14 FIGURE 6. Change in Propagation Delay vs. Loading Capacitance Relative to a 500 pF Load Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. 7.0V Supply Voltage, Vee Storage Temperature Range -65'C to + 150'C Input Voltage 5.5V Output Current 150mA lead Temperature (Soldering, 10 sec) 300'C Maximum Power Dissipation" at 25'C Cavity Package Molded Package 3542mW 2633mW Operating Conditions Supply Voltage Ambient Temperature Vee TA Min 4.75 0 Max 5.25 +70 Units V 'C 'Derate cavity package 23.6 mWre above 25'e; derate molded package 22.7 mW I'e above 25'e. Electrical Characteristics Vee = Symbol 5.0V ± 5%, O'C ,;; TA ,;; 70'C (unless otherwise noted) (Notes 2, 6) Parameter Conditions Ve Input Clamp Voltage Vee = Min., Ie IIHI Input High Current for ADS, RIC only VIN IIH2 Input High Current for All Other Inputs' VIN IIRSI Output load Current for RF 1/0 VIN IICTl Output load Current for RAS, CAS, WE VIN 11L1 Input low Current for ADS, RIC only VIN VIN = Min -12 mA = 2.5V = 2.5V = 0.5V, Output High = 0.5V, Chip Deselect = 0.5V = 0.5V 11L2 Input low Current for All Other Inputs" VIL Input low Threshold VIH Input High Threshold VOLI Output low Voltage" VOL2 Output low Voltage for RF 1/0 = 20 mA IOL = 10mA VOH1 Output High Voltage' IOH = -1 mA 2.4 VOH2 Output High Voltage for RF 110 IOH = - 100 /LA 2.4 110 Output High Drive Current' VOUT = 0.6V (Note 3) 100 Output low Drive Current" VOUT I~- 'UL TRI-STATE Output CUii6iit (Address Outputs) CAY'; YOUT s: 2.7V, CS = 2.0V, Mode 4 Icc Supply Current Vee = Max. Typ Max -0.6 -1.2 V 2.0 100 /LA 1.0 50 /LA -1.5 -2.5 mA -1.5 -2.5 mA -0.1 -1.0 mA -0.05 -0.5 mA 0.6 V 2.0 IOL = 'Except RF 1/0 Output. 1-14 2.7V (Note 3) -50 Units V 0.3 0.5 0.3 0.5 V V V 3.5 3.5 V -200 mA 200 mA 1.0 50 /LA 210 265 mA Switching Characteristic DP8408A/DP8408·3 VCC = 5.0V ± 5%, O°C :;:;: T A :;:;: 70°C unless otherwise noted (Notes 2,4, 5). The output load capacitance is typical for 4 banks of 22 DRAMs each of 88 DRAMs including trace capacitance. These values are: 00-07, CL = 500 pF; RASO-RAS3, CL = 150 pF; WE, CL = 500 pF; CAS, CL = 600 pF, unless otherwise noted. See Figure 7for test load. Switches S1 and S2 are closed unless otherwise noted, and R1 and R2 are 4.7 kO unless otherwise noted. Maximum propagation delays are specified with all outputs switching. Symbol Access Parameter 8408-3 8408A Conditions Units Min Typ Max Min Typ Max tRICL RASIN to CAS Output Delay (Mode 5) Figure5a 95 125 160 95 125 185 ns tRICL RASIN to CAS Output Delay (Mode 6) Figures 5a, 5b 80 105 140 80 105 160 ns tRICH RASIN to CAS Output Delay (Mode 5) Figure5a 40 48 60 40 48 70 ns tRICH RASIN to CAS Output Delay (Mode 6) Figures 5a, 5b 50 63 80 50 63 95 ns tRCDL RAS to CAS Output Delay (Mode 5) Figure5a 98 125 98 145 ns tRCDL RAS to CAS Output Delay (Mode 6) Figures 5a, 5b 78 105 78 120 ns tRCDH RAS to CAS Output Delay (Mode 5) Figure5a 27 40 27 40 ns tRCDH RAS to CAS Output Delay (Mode 6) Figure5a 40 65 40 65 ns tCCDH CASIN to CAS Output Delay (Mode 6) Figure5b 40 54 70 54 80 ns Row Address Hold Time (Mode 5) Figure5a 30 30 ns ns tRAH 40 tRAH Row Address Hold Time (Mode 6) Figures 5a, 5b 20 20 IASC Column Address Setup Time (Mode 5) Figure5a 8 8 ns tASC Column Address Setup Time (Mode 6) Figures 5a, 5b 6 6 ns tRCV RASIN to Column Address Valid (Mode 5) Figure5a 90 120 90 140 ns tRCV RASIN to Column Address Valid (Mode 6) Figures 5a, 5b 75 105 75 120 ns tRPDL RASIN to RAS Delay Figures 4a, 4b, 5a, 5b 20 27 35 20 27 40 ns tRPDH RASIN to RAS Delay Figures 4a, 4b, 5a, 5b 15 23 32 15 23 37 ns tAPDL Address Input to Output Low Delay Figures4~4b,5a,5b 25 40 25 46 ns tAPDH Address Input to Output High Delay Figures4~4~ 25 40 25 46 ns tSPDL Address Strobe to Address Output Low Figures 4a, 4b, 40 60 40 70 ns tSPDH Address Strobe to Address Output High Figures 4a, 4b, 40 60 40 70 tASA Address Setup Time to ADS Figures 4a, 4b, 5a, 5b 15 15 tAHA Address Hold Time from ADS Figures 4a, 4b, 5a, 5b 15 15 ns tAOS Address Strobe Pulse Width Figures 4a, 4b, 5a, 5b 30 30 ns IWPDL WIN to WE Output Delay Figure4b 15 25 30 15 25 35 ns tWPDH WIN to WE Output Delay Figure4b 15 30 60 15 30 70 ns tCRS CASIN Setup Time to RASIN High (Mode 6) Figure5b 35 tCPDL CASIN to CAS Delay Figure4b 32 41 68 32 41 77 tCPDH CASIN to CAS Delay Figure4b 25 39 50 25 39 60 ns tRCC Column Select to Column Address Valid Figure 4a 40 58 40 67 ns tRCR Row Select to Row Address Valid Figures 4a, 4b 40 58 40 67 ns tRHA Row Address Held from Column Select Figure4a tCCAS RIC Low to CAS Low (Mode 4 Auto CAS) Figure7a 65 90 (RIC low in Mode 4) 1-15 5a,5b 35 10 10 ns ns ns ns ns ns Switching Characteristics DP8408A/DP8408-3 (Continued) VCC = 5.0V ± 5%, O·C s T A S 70·C unless otherwise noted (Notes 2, 4, 5). The output load capacitance is typical for 4 banks of 22 DRAMs each of 88 DRAMs including trace capacitance. These values are: 00-07, CL = 500 pF; RASO-RAS3, CL = 150 pF; WE, CL = 500 pF; CAS, CL = 600 pF, unless otherwise noted. See Figure 710r test load. Switches S1 and S2 are closed unless otherwise noted, and R1 and R2 are 4.7 kO unless otherwise noted. Maximum propagation delays are specified with all outputs switching. Access Parameter Symbol 8408-3 8408A Conditions Min Typ Max Min Typ Units Max tOIFt Maximum (tRPOL - tRHA) See Mode 4 description 13 18 ns tOlF2 Maximum (tRCC - tcpod See Mode 4 description 13 18 ns Refresh Parameter tRC Refresh Cycle Period Figure 2 100 100 ns tRASINL, H Pulse Width of RASIN during Refresh Figure 2 50 50 ns tRFPOL RASIN to RAS Delay during Refresh Figure 2 35 50 70 35 50 80 ns tRFPOH RASIN to RAS Delay during Refresh Figure 2 30 40 55 30 40 65 ns tRFLCT RFSH Low to Counter Address Valid CS 47 60 47 70 ns tRFHRV RFSH High to Row Address Valid Figure 2 45 60 45 70 ns tROHNC RAS High to New Count Valid Figure 2 30 55 30 55 ns tRLEOC RASIN Low to End-of-Count Low CL = 50 pF, Figure 2 80 80 ns tRHEOC RASIN High to End-of-Count High CL = 50 pF, Figure 2 80 80 ns tRST Counter Reset Pulse Width Figure 2 tcTL RF 110 Low to Counter Outputs All Low Figure 2 = X, Figure 2 70 70 ns 100 100 ns TRI-STATE Parameter tZH CS Low to Address Output High from Hi-Z Figure 8 R1 = 3.5k, R2 = = tHZ CS High to Address Output Hi-Z from High CL R2 tZL CS Low to Address Output Low from Hi-Z Figure 8 R1 = 3.5k, R2 = = = 1.5k 15 pF, Figure 8 1k, S1 open = 1.5k 35 60 35 60 ns 20 40 20 40 ns 35 60 35 60 ns tLZ CS High to Address Output Hi-Z from Low CL R1 15 pF, Figure 8 1k, S2 open 25 50 25 50 ns tHZH CS Low to Control Output High from Hi-Z High Figure 8 R2 = 7500, S1 open 50 80 50 80 ns tHHZ CS High to Control Output Hi-Z High from High CL R2 = 15 pF, Figure 8 = 7500, S1 open 40 75 40 75 ns tHZL CS Low to Control Output Low from Hi-Z High Figure 8 S1, S2 open 45 75 45 75 ns tLHZ CS High to Control Output Hi-Z High from Low CL R2 50 80 50 80 ns = 15pF,Figure8, = 7500, S1 open 1-16 Switching Characteristics DP8408-2 VCC = 5.0V ±5%, O°C :s:; TA :s:; 70°C unless otherwise noted (Notes 2, 4, 5, 7). The output load capacitance is typical for 4 banks of 22 DRAMs each or 88 DRAMS including trace capacitance. These values are: 00-07, CL = 500 pF; RASO-RAS3, CL = 150 pF, WE, CL = 500 pF; CAS, CL = 600 pF, unless otherwise noted. See Figure 7for test load. Switches Sl and S2 are closed unless otherwise noted, and Rl and R2 are 4.7 k!1 unless otherwise noted. Maximum propagation delays are specified with all outputs switching. Symbol Access Parameter 8408-2 Conditions Units Min Typ Max tRICL RASIN to CAS Output Delay (Mode 5) Figure5a 75 100 130 ns tRICL RASIN to CAS Output Delay (Mode 6) Figures 5a, 5b 65 90 115 ns tRICH RASIN to CAS Output Delay (Mode 5) Figure5a 40 48 60 ns tRICH RASIN to CAS Output Delay (Mode 6) Figures 5a, 8b 50 63 80 ns tRCDL RAS to CAS Output Delay (Mode 5) Figure5a 75 100 ns tRCDL RAS to CAS Output Delay (Mode 6) Figures 5a, 5b 65 85 ns tRCDH RAS to CAS Output Delay (Mode 5) Figure5a 27 40 ns tRCDH RAS to CAS Output Delay (Mode 6) Figure5a 40 65 ns tCCDH CASIN to CAS Output Delay (Mode 6) Figure5b 40 54 70 ns tRAH Row Address Hold Time (Mode 5) (Note 7) Figure5a 20 ns tRAH Row Address Hold Time (Mode 6) (Note 7) Figures 5a, 5b 12 ns tASC Column Address Setup Time (Mode 5) Figure5a 3 ns tASC Column Address Setup Time (Mode 6) Figures 5a, 8b 3 ns tRCV RASIN to Column Address Valid (Mode 5) Figure5a tRCV RASIN to Column Address Valid (Mode 6) Figures 5a, 5b 70 90 ns tRPDL RASIN to RAS Delay Figures 4a, 4b, 5a, 5b 20 27 35 ns tRPDH RASIN to RAS Delay Figures 4a, 4b, 5a, 5b 15 23 32 ns tAPDL Address Input to Output Low Delay Figures 4a, 4b, 5a, 5b 25 40 ns 80 105 ns tAPDH Address Input to Output High Delay Figures 4a, 4b, 5a, 5b 25 40 ns tSPDL Address Strobe to Address Output Low Figures 4a, 4b 40 60 ns tSPDH Address Strobe to Address Output High Figures 4a, 4b 40 60 ns tASA Address Set-up Time to ADS Figures 4a, 4b, 5a, 5b tAHA Address Hold Time from ADS tADS Address Strobe Pulse Width tWPDL 15 ns Figures 4a, 4b, 5a, 5b 15 ns Figures 4a, 4b, 5a, 5b 30 WIN to WE Output Delay Figure4b 15 25 30 tWPDH WIN to WE Output Delay Figure4b 15 30 60 teRS CASIN Set-up Time to RASIN High (Mode 6) Figure5b 35 tCPDL CASIN to CAS Delay (RIC low in Mode 4) Figure4b 32 41 58 tCPDH CASIN to CAS Delay (RIC low in Mode 4) Figure4b 25 39 50 ns tRCC Column Select to Column Address Valid Figure4a 40 58 ns tRCR Row Select to Row Address Valid Figures 4a, 4b 40 58 ns tRHA Row Address Held from Column Select Figure4a tCCAS RIC Low to CAS Low (Mode 4 Auto CAS) Figure 7a 55 75 ns 1-17 ns ns ns ns 10 ns ns Switching Characteristics DP8408-2 (Continued) VCC = 5.0V ±5%, O°C ,;; TA ,;; 70°C unless otherwise noted (Notes 2, 4, 5, 7). The output load capacitance is typical for 4 banks of 22 DRAMs each or 88 DRAMS including trace capacitance. These values are: 00-07, CL = 500 pF; RASO-RAS3, CL = 150 pF, WE, CL = 500 pF; CAS, CL = 600 pF, unless otherwise noted. See Figure 7for test load. Switches S1 and S2 are closed unless otherwise noted, and R1 and R2 are 4.7 kO unless otherwise noted. Maximum propagation delays are specified with all outputs switching. Symbol Access Parameter 8408-2 Conditions Min Typ Units Max tOlF1 Maximum (tRPOL - tRHA) See Mode 4 description 13 ns tOlF2 Maximum (tRCC - tcpoLl See Mode 4 description 13 ns Refresh Parameter tRC Refresh Cycle Period Figure 2 100 tRASINl. H Pulse Width of RASIN during Refresh Figure 2 50 tRFPOL RASIN to RAS Delay during Refresh Figure 2 35 50 70 ns tRFPOH RASIN to RAS Delay during Refresh Figure 2 30 40 55 ns ns = ns tRFlCT RFSH Low to Counter Address Valid CS 47 60 tRFHRV RFSH High to Row Address Valid Figure 2 45 60 ns tROHNC RAS High to New Count Valid Figure 2 30 55 ns tRlEOC RASIN Low to End-of-Count Low CL 80 ns tRHEOC RASIN High to End-of-Count High Cl 80 ns tRST Counter Reset Pulse Width Figure 2 tCTL RF I/O Low to Counter Outputs All Low Figure 2 = = X, Figure 2 ns 50 pF, Figure 2 50 pF, Figure 2 70 ns 100 ns 35 60 ns 20 40 ns 35 60 ns 25 50 ns 50 80 ns 40 75 ns 45 75 ns 50 80 ns TRI-STATE Parameter tZH CS Low to Address Output High from Hi-Z Figures g, 12 R1 = 3.5k, R2 = = tHZ CS High to Address Output Hi-Z from High CL R2 tZl CS Low to Address Output Low from Hi-Z Figures 9, 12 R1 = 3.5k, R2 = = = 1.5k 15 pF, Figures 9, 12 1k,S1 open = 1.5k 15 pF, Figures 9, 12 1k,S20pen tLZ CS High to Address Output Hi-Z from Low CL R1 tHZH CS Low to Control Output High from Hi-ZHigh Figures 9, 12 R2 = 7500, S1 open tHHZ CS High to Control Output Hi-Z High from High CL R2 tHZL CS Low to Control Output Low from Hi-Z High Figure 12, S1, S20pen tLHZ CS High to Control Output Hi-Z High from Low CL R2 = = = = 1-18 15 pF, Figures 9, 12 7500, S1 open 15 pF, Figure 12, 7500, S1 open Input Capacitance TA = Symbol 25'C (Notes 2, 6) Parameter Conditione Min Typ Max Units CIN Input Capacitance ADS, R/r; 8 pF CIN Input Capacitance All Other Inputs 5 pF Not. 1: "Absolute Maximum Ratings" are the values beyond which the safety of the device cannot be guaranteed. They are not meant to Imply that the device should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation. Note 2: All typical values are for TA = 25'C and Vcc = 5.0V. Note 3: This test is provided as a monitor of Driver output source and sink current capability. Caution should be exercised in testing this parameter. In testing these parameters. a 150 resistor should be placed in series with each output under test. One output should be tested at a time and test time should not exceed 1 second. Note 4: Input pulse OV to 3.0V, tR for High and O.BV for Low. = tF = 2.5 ns, f = 2.5 MHz, tpw = 200 ns. Input reference pOint on AC measurements is 1.5V. Output reference pOints are 2.7V Note 5: The load capacitance on RF 110 should not exceed 50 pF. Note 6: Applies to all DP640BA versions unless otherwise specified. Note 7: The DP8408-2 device can only be used with memory devices that meet the tRAH specification indicated. ~. S1 - / I f ---o TEST POINT OUTPUT UNDER o--"tN...........- -..... TEST 15\2 S2 ~ "U" TL/F/8408-15 FIGURE 7. Output Load Circuit Timing Waveform INPUT OV 3.OV_--------___.. 1.5V J I ----.I \,.5V tHZ VOH -tHHZ=-.l OUTPUT VOL I ,,-: ,.;;;,,;-~~±:==O.5V -tHZH!-- -1 HIGH Z: _ _ _':"'-~ 2.7V ------O.5V -!ILHZ I tlZ :=-T VOH tZH 11""__- - VOL 'k'~O:::.8V:...._..;,,; IHZL I-- III TL/F/B408-16 FIGURES Applications included for systems using byte-writing. The refresh clock RFCK may be divided down from either RGCK using an IC counter such as the DM74LS393 or better still, the DP84300 Programmable Refresh Timer. The DP84300 can provide RFCK periods ranging from 15.4 !,-S to 15.6 !'-S based on the input clock of 2 to 10 MHz. Figure 9b shows the general timing diagram for interfacing the DP8408A to different microprocessors using the interface controller DP843X2. If external control is preferred, the DP8408A may be used in Modes 0 or 4, as in Figure 3. If basic auto access and refresh are required, then in cases where the user requires the minimum of external complexity, Modes 0 and 5 are ideal, as shown in Figure 9a. The DP843X2 is used to provide proper arbitration between memory access and refresh. This chip supplies all the nec· essary control signals to the processor as well as the DP8408A. Furthermore, two separate CAS outputs are also 1-19 I Applications • (Continued) .r 16·BIT MICROPROCESSOR DATA BUS MICROPROCESSOR ADDRESS BUS AOOR ~ ST~~~: t-.... ~ CO·6,7 ' - - - - Bl I - ADDRESS DECODER I I I --r-------... :: lSELECT W~Tt ~~~7~:E~CE~~~~' FOR VERY FAST MICRO· PROCESSORS ~:- ~ CAS - t II *-----~H AO-6,7 I om U ~~.~.~!-I~·I~~,~.~I~I:..,~·... I:aWER liAS_ + +J. -:J.. _ ,------- . II I I I ~ mL WI: rt"---t'1!W~E_J:~ RF 110 M2 Ml MO e- V W£ - L..--++--tmm .. AD-6,7 AO·6,7 I tTHE SELECT WAITINPUT TO THE OPB43X2 CHIP INSERTS A WAIT STATE I ...c::::;- p L 1-1--0 ~w n _ 1,.... '...... _t........................'.....,_ OP84XX1 ~ASL ,••• ~ ~ ~~ II _" : R/WW'~±:==:::;-+-t-1~@==t+t1W11l r- r---. I -:: ~ IADS MICROPROCEs:~:CKt-t----++-r+~e- r-- AO·6,7 L---J~CASU t-_ _ _ _r--_-t~ - - - +.... UPPER BYTE LOWER BYTE ...&....--,1+------ . RAMS MAY BE 16k OR 64k I ..__... ..__-._-+!RO-6,7 ...-------,RAM ADDRESS BUS 1-___ IIIP r---O-lA~JA--;;;; ----=m U" uASL- u:m BYTE L-._ _....!-_ _....J "0""1" -------.J OM t-=====t"i-r 748244 INECESSARY IF INSTRUCTIONS INCLUDE ""W:;;,;;,,;;.L..;:S::.EL:,:EC;;,;T..;:L::.OW::.:E::.;R.::B,;,;YT.:.E_ _ _ _ _ _ _ _~ t-======~..J m -",W=U::...;S::,EL:,:E::;CT'-.:U::.PP:.:E:::,R,:,BY:.:,T:.E BYTE·WRITING, OTHERWISE USE DIRECTLY FROM THE DPB408A TO THE RAMS. I- NECESSARY IF MORE THAN ONE BANK __ ' - - - t - - - - - - - - - - - ' TL/F/B40B-17 FIGURE 9a. Connecting the DP8408A between the 16·Blt Microprocessor and Memory 1-20 Applications (Continued) 1-= HIDDEN REFRESH-- I I I-MEMORY CYCLE - CYCLE I ---- MEMORY CYCLE ~ DP84300 MINIMIZES lOW TIME TO 20 CLOCKS MAXIMIZING CHANCE OF HIDDEN REFRESH RFCK ~IT _ _ FORCED ---- REFRESH - ACCESS I.MEMORY CYClE- __ ElSEWHERE_ n ~ ~ ______ _ _ ~ ~~ __ n ~ ~ ______ *T IS MICROPRO'~ESSOR'S CLOCK ~L - ~I PERIO~ TL/F 18408-18 FIGURE 9b. DP8408A Auto Refresh 1-21 I ~Nat1onal Semiconductor ~ ~ DP8409A Multi-Mode Dynamic RAM ControllerIDriver General Description Operational Features Dynamic memory system designs, which formerly required several support chips to drive the memory array, can now be implemented with a single IC ... the DP8409A MultiMode Dynamic RAM Controller/Driver. The DP8409A is capable of driving all 16k and 64k Dynamic RAMs (DRAMs) as well as 256k DRAMs. Since the DP8409A is a one-chip solution (including capacitive-load drivers), It minimizes propagation delay skews, the major performance disadvantage of multiple-chip memory drive and control. • All DRAM drive functions on one chip-minimizes skew on outputs, maximizes AC peformance • On-chip capacitive-load drives (specified to drive up to 88 DRAMs) • Drives directly all 16k, 64k, and 256k DRAMs • Capable of addressing 64k, 256k, or 1M words • Propagation delays of 25 ns typical at 500 pF load • CAS goes low automatically aiter column addresses are valid If desired • Auto Access mode provides RAS, row to column select, then CAS automatically and fast • WE follows WJiiI unconditionally-offering READ, WRITE or READ-MODIFY-WRITE cycles • On-chip 9-bit refresh counter with selectable End-ofCount (127, 255 or 511) • End-of-Count indicated by RF I/O pin going low at 127, 255 or 511 • Low input on RF I/O resets 9-bit refresh counter • CAS inhibited during refresh cycle • Fall-through latches on address inputs controlled by ADS • TRI-STATE outputs allow multi-controller addressing of memory • Control output signals go high-impedance logic "1" when disabled for memory sharing • Power-up: counter reset, control signals high, address outputs TRI-STATE, and End-of-Count set to 127 The DP8409A's 8 modes of operation offer a wide selection of DRAM control capabilities. Memory access may be controlled externally or on-chip automatically; an on-chip refresh counter makes refreshing (either externally or automatically controlled) less complicated; and automatic memory initialization is both simple and fast. The DP8409A is a 48-pin DRAM Controller/Driver with 9 multiplexed address outputs and 6 control signals. It consists of two 9-bit address latches, a 9-bit refresh counter, and control logic. All output drivers are capable of driving 500 pF loads with propagation delays of 25 ns. The DP8409A timing parameters are specified driving the typical load capacitance of 88 DRAMs, including trace capacitance. The DP8409A has 3 mode-control pins: M2, Ml, and MO, where M2 is in general REFRESH. These 3 pins select 8 modes of operation. Inputs B1 and BO in the memory access modes (M2 = 1), are select inputs which select one of four RAS outputs. During normal access, the 9 address outputs can be selected from the Row Address Latch or the Column Address Latch. During refresh, the 9-bit on-Chip refresh counter is enabled onto the address bus and in this mode all RAS outputs are selected, while CAS is inhibited. The DP8409A can drive up to 4 banks of DRAMs, with each bank comprised of 16k's, 64k's, or 256k's. Control signal outputs RAS, ~, and WE are provided with the same drive capability. Each RAS output drives one bank of DRAMs so that the four RAS outputs are used to select the banks, while ~, WE, and the multiplexed addresses can be connected to all of the banks of DRAMs. This leaves the non-selected banks in the standby mode (less than one tenth of the operating power) with the data outputs in TRISTATE®. Only the bank with its associated RAS low will be written to or read from. SYSTEM RAM CONTROL CONTROL ~ 10 SYSTEM 20 SYSTEM ADDRESS 6 0P8409A DYNAMIC RAM CONTROLLERI DRIVER 500pF DRIVE MEMORY 9 ... RAm ADDRESS Mode Features • 8 modes of operation: 3 access, 3 refresh, and 2 set-up • 2 externally controlled modes: 1 access and 1 refresh (Modes 0, 4) • 2 auto-access modes RAS - R/-e - ~ automatic, with tRAH = 20 or 30 ns minimum (Modes 5, 6) • Auto-access mode allows Hidden Refreshing (Mode 5) • Forced Refresh requested on RF I/O if no Hidden Refresh (Mode 5) • Forced Refresh performed after system acknowledge of request (Mode 1) • Automatic Burst Refresh mode stops at End-of-Count of 127, 255, or 511 (Mode 2) • 2 AII-RAS Acces modes externally or automatically controlled for memory initialization (Modes 3a, 3b) • Automatic AII·RAS mode with external 8-bit counter frees system for other set-up routines (Mode 3a) • End-of-Count value of Refresh Counter set by B 1 and BO (Mode 7) 16k. 64k. OR 256k DYNAMIC RAM BANKS TL/F/8409-1 1-22 Block and Connection Diagrams 68 Pin PCC I~ RO-8 ... ---~ '" i 9 8 1--+1>-••'-8 CD-8 10 6 5 • 3 2 1 68 67 66 65 64 63 62 61 60 ADS 11 59 RO 12 58 Ql CO 13 57 Q2 Rl 14 56 Q3 Cl 55 Q. 15 R2 16 5. GND C2 17 53 GHD GND 18 52 Q5 GHO 19 51 Yee R3 20 50 Yee m, C3 21 .9 Q6 1101 R. 22 C. 23 .7 Q8 R5 24 .6 C5 25 45 RA53 110, 81 80 7 1100 .a Q7 CAs ~ ~ v~~~~n~~~M~M~~~~~ CS-. CAl mIII_ RIC IRFeK) ---... emil (ROCK) _ TL/F/8409-3 II/Iii 'Ill! RFI/D M2(iIFiiIl M1 Dual-In-Llne Package .0 TL/F/8409-2 Order Number DP84D9AD, DP84D9AN, DP84D9AN-3 or DP84D9AV-2 See NS Package Number D48A, N48A or V68A DP84D9A Pin Definitions Vee, GND, GN~Vcc = 5V ±5%. The three supply pins have been assigned to the center of the package to reduce voltage drops, both DC and AC. There are also two ground pins to reduce the low level noise. The second ground pin is located two pins from Vee, so that decoupling capacitors can be inserted directly next to these pins. It is important to adequately decouple this device, due to the high switching currents that will occur when all 9 address bits change in the same direction simultaneously. A recommended solution would be a 1 ,.,.F multilayer ceramic capaCitor in parallel with a low-voltage tantalum capaCitor, both connected as close as possible to pins 36 and 38 to reduce lead inductance. See figure below. VCC(PIN 36) Top View RD-R8: Row Address Inputs. CD-C8: Column Address Inputs. QD-Q8: Multiplexed Address Outputs--Selected from the Row Address Input Latch, the Column Address Input Latch, or the Refresh Counter.· RASIN: Row Address Strobe Input-Enables selected RASn output when M2 (RFSH) is high, or all RASn outputs when RFSH is low. o------.. ....----., T.L I _ ~ 'MULTILAYER 'TANTALUM CERAM(C GND (PINS 38. 13) TL/F/8409-5 0 RIC (RFCK)-In Auto-Refresh Mode this pin is the external Refresh Clock Input: one refresh cycle has to be performed each clock period. In all other modes it is Row/Column Select Input: selects either the row or column address input latch onto the output bus. TL/F/8409-4 'Capacitor values should be chosen depending on the particular application. 1-23 • Pin Definitions (Continued) TABLE I. DP8409A Mode Select Options Mode (RFSH) M2 M1 MO 0 0 0 0 Externally Controlled Refresh RFIIO = 1 0 0 1 Auto Refresh-Forced RF 1/0 = Refresh Request (RFRO) 2 0 1 0 Internal Auto Burst Refresh RFIIO = Mode of Operation Conditions EOC EOC 3a 0 1 1 All RAS Auto Write RF I/O = EOC; All RAS Active 3b 0 1 1 Externally Controlled All RAS Access All RAS Active 4 1 0 0 Externally Controlled Access Active RAS Defined by Table II 5 1 0 1 Auto Access, Slow tRAH, Hidden Refresh Active RAS Defined by Table II 6 1 1 0 Auto Access, Fast tRAH Active RAS Defined by Table II 7 1 1 1 Set End of Count See Table III for Mode 7 manently high. Otherwise ADS must go low while the addresses are still valid. CASIN (RGCK)-In Auto-Refresh Mode, Auto Burst Mode, and AII-RAS Auto-Write Mode, this pin is the RAS Generator Clock input. In all other modes it is CASilii (Column Address Strobe Input), which inhibits CAS output when high in Modes 4 and 3b. In Mode 6 it can be used to prolong (;AS output. In normal memory access operation, RASIN and RIC; are initially high. When the address inputs are enabled into the address latches, the row addresses appear on the 0 outputs. The address strobe also inputs the bank-select address, (BO and Bl). If C;S is low, all outputs are enabled. When C;S is transitioned high, the address outputs go TRISTATE and the control outputs first go high through a low impedance, and then are held by an on-chip high impedance. This allows output paralleling with other DP8409As for multi-addressing. All outputs go active about 50 ns after the chip is selected again. If C;S is high, and a refresh cycle begins, all the outputs become active until the end of the refresh cycle. ADS: Address (Latch) Strobe Input-flow Address, Column Address, and Bank Select Latches are fall-through with ADS high; Latches on high-to-Iow transition. CS: Chip Select Input-The TRI-STATE mode will Address Outputs and puts the control signal into a high-impedance logic "1" state when high (unless refreshing in one of the Refresh Modes). Enables all outputs when low. MO, M1, M2: Mode Control Input_These 3 control pins determine the 8 major modes of operation of the DP8409A as depicted in Table I. DRIVE CAPABILITY RF I/O-The 110 pin functions as a Reset Counter Input when set low from an external open-collector gate, or as a flag output. The flag goes active-low in Modes 0 and 2 when the End-of-Count output is at 127, 255, or 511 (see Table III). In Auto-Refresh Mode it is the Refresh Request output. The DP8409A has timing parameters that are specified with up to 600 pF loads. In a typical memory system this is equivalent to about 88, 5V-only DRAMs, with trace lengths kept to a minimum. Therefore, the chip can drive four banks each of 16 or 22 bits, or two banks of 32 or 39 bits, or one bank of 64 or 72 bits. WIN: Write Enable Input. Less loading will slightly reduce the timing parameters, and more loading will increase the timing parameters, according to the graph of Figure 10. The AC performance parameters are specified with the typical load capaCitance of 88 DRAMs. This graph can be used to extrapolate the variations expected with other loading. WE: Write Enable Output-8uffered output from WIN.· CAS: Column Address Strobe Output-In Modes 3a, 5, and 6, c:AS transitions low following valid column address. In Modes 3b and 4, it goes low alterRte goes low, or follows CASIN going low if RIC is already low. CAS is high duing refresh.· Because of distributed trace capaCitance and inductance and DRAM input capacitance, current spikes can be created, causing overshoots and undershoots at the DRAM inputs that can change the contents of the DRAMs or even destroy them. To remove these spikes, a damping resistor (low inductance, carbon) can be inserted between the DP8409A driver outputs and the DRAMs, as close as possible to the DP8409A. The values of the damping resistors may differ between the different control outputs; RASs, c:AS, O's, and WE. The damping resistors should be determined by the first prototypes (not wire-wrapped due to the larger distributed capacitance and inductance). The best values for the damping resistors are the critical values giving a critically damped transition on the control outputs. Typical values for the damping resistors will be between 150 and 1000, the lower the loading the higher the value. (For more information, see AN-305 "Precautions to Take When Driving Memories.") RAS 0-3: Row Address Strobe Output-Selects a memory bank decoded from Bl and BO (see Table II), if RFSR is high. If RFSH is low, all banks are selected.· BO, B1: Bank Select Input-Strobed by ADS. Decoded to enable one of the RAS outputs when RASIN goes low. Also used to define End-of-Count in Mode 7 (Table III). Conditions for All Modes INPUT ADDRESSING The address block consists of a row-address latch, a column-address latch, and a resettable refresh counter. The address latches are fall-through when ADS is high and latch when ADS goes low. If the address bus contains valid addresses until after the valid address time, ADS can be per- 1-24 Conditions for All Modes (Continued) with no on-RAM refresh counter. The DP8409A can drive all three configurations, and at the same time allows them all to be interchangeable (as shown in Figures lb and Ie), providing maximum flexibility in the choice of DRAMs. Since the 9-bit on-chip refresh counter can be used as a 7-bit refresh counter for the 128-row configuration, or as an 8-bit refresh counter for the 256-row configuration, the on-RAM refresh counter (if present) is never used. As long as 128 rows are refreshed every 2 rns (i.e. 256 rows in 4 rns) all DRAM types are correctly refreshed. DP8409A DRIVING ANY 16k OR 64k DRAMs The DP8409A can drive any 16k or 64k DRAMs. All 16k DRAMs are basically the same configuration, including the newer 5V-only version. Hence, in most applications, different manufacturers' DRAMs are interchangeable (for the same supply-rail chips), and the DP8409A can drive all 16k DRAMs (see Figure la). There are three basic configurations for the 5V-only 64k DRAMs: a 128-row by 512-column array with an on-RAM refresh counter, a 128-row by 512-column array with no onRAM refresh counter, and a 256-row by 256-column array DP8409A Interface between System and DRAM Banks I~ r;.1 ROWS COLUMNS r-t CAS WE m AODRESS DRIVERS ...., 7 7 COL.!CODE R 128 W 128 16K ARRAY 0 0 7 ADDRESS 8US E C IJ 7 REFRESH COUNTER +12Vor +5V 16K DYNAMIC RAMS DP8409A TLiF/B409-6 FIGURE 1a. DP8409A with any 16k DRAMs [~ LATCHES 8 COLUMN ADDRESSES HE 7 DW+1 COLUMN ADDRESSlIAS LATCSR W ~. - ROWS I~'''HI''': rt REFRESH COUNTER 8 8 DRIVERS. 8 ADORES?' 8US ICOL!CDDEJ R 512 0 W 128 64K ARRAY 0 E C ~ IF. ON·CHIP REFRESH COUNTER, NOT USED +5V 64K DYNAMIC RAMS DP8409A ONLY LS 7 81TS OF REFRESH COUNTER USED FOR THE 7 ROW ADDRESSES. MSB NOT USED BUT CAN TOGGLE TLiF/8409-7 FIGURE 1b. DP8409A with 128 Row x 512 Column 64k DRAM • CAS ~~ ROWS I ""... 128 ROWS (OR 25~NR~:~ - ~ ~ _.7 ,• DRIVERS B B AODRESS BUS -. 8 1 COLUMN DECODE R -t~EFRESH COUNTER ~ 256 0 W 0 256 E C I j. 64K ARRAY +5V 64K DYNAMIC RAMS 0 IN 4MS) D E DP8409A ALL 8 BITS DF REFRESH CDUNTER USED TL/F /8409-8 FIGURE 1c. DP8409A with 256 x 256 Column 64k DRAM 1-25 DP8409A Functional Mode Descriptions Conditions for All Modes (Continued) When the DP8409A is in a refresh mode, the RF I/O pin indicates that the on-chip refresh counter has reached its end-of-count. This end-of-count is selectable as 127, 255 or 512 to accommodate 16k, 64k or 256k DRAMs. Although the end-of-count may be chosen to be any of these, the counter always counts to 511 before rolling over to zero. Note: All delay parameters slated in text refer to the DP8409A. Substitute the respective delay numbers for the DP8409·2 or DP8409·3 when using these devices. MODE O-EXTERNALLY CONTROLLED REFRESH Figure 2 is the Externally Controlled Refresh Timing. In this mode, the input address latches are disabled from the address outputs and the refresh counter is enabled. When RAS occurs, the enabled row in the DRAM is refreshed. In the Externally Controlled Refresh mode, all RAS outputs are enabled following RASIN, and CAS is inhibited. This refreshes the same row in all four banks. The refresh counter increments when either RASIN or RFSH goes low-to-high after a refresh. RF 1/0 goes low when the count is 127, 255, or 511, as set by End-of-Count (see Table III), with RASIN and RFSH low. To reset the counter to all zeros, RF I/O is set low through an external open-collector driver. READ, WRITE, AND READ-MODIFY-WRITE CYCLES The output signal, WE, determines what type of memory access cycle the memory will perform. If WE is kept high while CAS goes low, a read cycle occurs. If WE goes low before CAS goes low, a write cycle occurs and data at 01 (DRAM input data) is written into the DRAM as CAS goes low. If WE goes low later than tewD after CAS goes low, first a read occurs and DO (DRAM output data) becomes valid; then data 01 is written into the same address in the DRAM when WE goes low. In this read-modify-write case, 01 and DO cannot be linked together. The type of cycle is therefore controlled by WE, which follows WIN. During refresh, RASIN and RFSH must be skewed transitioning low such that the refresh address is valid on the address outputs of the controller before the RAS outputs go low. The amount of time that RFSH should go low before RASIN does depends on the capacitive loading of the address and RAS lines. For the load specified in the switching characteristics of this data sheet, IOns is sufficient. Refer to Figure 2. To perform externally controlled burst refresh, RASIN is toggled while RFSH is held low. The refresh counter increments with RASIN going low to high, so that the DRAM rows are refreshed in succession by RASIN going high to low. POWER-UP INITIALIZE When Vee is first applied to the DP8409A, an initialize pulse clears the refresh counter, the internal control flip-flops, and set the End-of-Count of the refresh counter to 127 (which may be changed via Mode 7). As Vee increases to about 2.3V, it holds the output control signals at a level of one Schottky diode-drop below Vee, and the output address to TRI-STATE. As Vee increases above 2.3V, control of these outputs is granted to the system. INPUTS RASiN CASiN AND Rtf OUTPUTS RASD RAS 1. 2. 3 tROHNC REFRESH CTR COUNTER RESET 00·8 ~!=!!O REFRESH COUNT n ,L _________________ I-IRLEOC • INDICATES DYNAMIC RAM PARAMETERS / -\ ~ \- tRHEOC END OF COUNT LOW IF 0=127, 255, 511 FIGURE 2. External Control Refresh Cycle (Mode 0) 1-26 COUNTER RESET INPUT FROM OPEN COLLECTOR TL/F/8409-9 DP8409A Functional Mode Descriptions (Continued) DRAMs. An external RiiJl Generator Clock (RGCK) is required for this function. It is fed to the CASIN (RGCK) pin, and may be up to 10 MHz. Whenever M2 goes low (inducing a forced refresh), RiiJl remains high for one to two periods of RGCK, depending on when M2 goes low relative to the high-to-Iow triggering edge of RGCK; RiiJl then goes low for two periods, performing a refresh on all banks. In order to obtain the minimum delay from M2 going low to RAS going low, M2 should go low tRFSRG before the next falling edge of RGCK. The Refresh Request on RF 1/0 is terminated as RiiJl begins, so that by the time the system has acknowledged the removal of the request and disabled its Acknowledge, (I.e., M2 goes high), Refresh AAS will have ended, and normal operations can begin again in the Automatic Access mode (Mode 5). If It Is desired that Refresh mend in less than 2 periods of RGCK from the time m went low, then M2 may be high earlier than tRQHRF after RGCK goes low and AAS will go high tRFRH after M2, if is low. If is high, the AAS will go high after 25 ns after M2 goes high. To allow the forced refresh, the system will have been inactive for about 4 periods of RGCK, which can be as fast as 400 ns every RFCK cycle. To guarantee a refresh of 128 rows every 2 ms, a period of up to 16 /Ls is required for RFCK. In other words, the system may be down for as little as 400 ns every 16 /Ls, or 2.5% of the time. Although this is not excessive, it may be preferable to perform a Hidden Refresh each RFCK cycle, which is allowed while still in the Auto-Access mode, (Mode 5). MODE 1-AUTOMATIC FORCED REFRESH In Mode 1, the R/~ (RFCK) pin becomes RFCK (refresh cycle clock), instead of R/~, and CAS remains high. If RFCK is kept permanently high, then whenever M2 (RFSH) goes low, an externally controlled refresh will occur and all RiiJl outputs will follow ~, strobing the refresh counter contents to the DRAMs. The RF 1/0 pin will always output high, but when set low externally through an open-collector driver, the refresh counter resets as normal. This externally controlled method may be preferred when operating in the Automatic Access mode (Mode 5), where hidden or forced refreshing is undesirable, but refreshing is still necessary. If RFCK Is an Input clock signal, one (and only one) refresh cycle must take place every RFCK cycle. Refer to Figure 9. If a hidden refresh does not occur while RFCK Is high, In Mode 5, then RF 1/0 (Refresh Request) goes low Immedlately after RFCK goes low, Indicating to the system that a forced refresh Is requested. The system must allow a forced refresh to take place while RFCK is low (refer to Figure 9). The Refresh Request signal on RF I/O may be connected to a Hoid or Bus Request input to the system. The system acknowledges the Hoid or Bus Request when ready, and outputs Hold Acknowledge or Bus Request Acknowledge. If this Is connected to the M2 (RFSH) pin, a forced-refresh cycle will be initiated by the DP8409A, and RiiJl will be internally generated on all four RiiJl outputs, to strobe the refresh counter contents on the address outputs into all the es c ~ ~ _ es RFCK r-- 'RBCKl I --l r-IRBCKH RGCK 80861'6832 REMOVE ACKNOWLEDGE 88OB0 REMOVES BRANT (MODE 5) M2(H) RF 110 (H) mo.,.2.al \ j \.. QO·8 f--'FRQl I ~p ACCESS J TO SELECTED BANK \ I I \ ~"'--C-Ol-S--'>B<--C-OLS--':" ,-_R_EF_RE_SH_C_O_UN_TER __ ~p ACCESS TO SELECTED BANKS >E)00C f-- 'RFLCT LS - TLIF/8409-10 FIGURE 3. DP8409A Performing a Forced Refresh (Mode 5 -+ 1 -+ 5) with Various Microprocessors 1-27 • I oct ~ DP8409A Functional Mode Descriptions (Continued) ex> Il. C DRAMS t Tns PROCESSOR ACTS AFTER INTERRUPT MODE MODE 2 : RGCK RAS 0-3 RF 110 (EOC) TLlF/8409-11 FIGURE 4. Auto-Burst Mode, Mode 2 corresponding check bits for error detection and correction). This requires writing the same data to each location of memory (every row of each column of each bank). All RAS outputs are activated, as in refresh, and so are CAS and WE. To write to all four banks simultaneously, every row is strobed in each column, in sequence, until data has been written to all locations. To select this mode, Bl and BO must have previously been set to 00, 01, or lOin Mode 7, depending on the DRAM size. For example, for 16k DRAMs, 81 and 80 are 00. For 64k DRAMs, 81 and 80 are 01, so that for the configuration of Figure 1b, the 8 refresh counter bits are strobed by RAS into the 7 row addresses and the ninth column address. After this Automatic-Write process, Bland 80 must be set again in Mode 7 to 00 to set End-of-Count to 127. For the configuration of Figure 1e, 81 and 80 set to 01 will work for Automatic-Write and End-of-Count equals 255. In this mode, R/C is disabled, WE is permanently enabled low, and CASIN (RGCK) becomes RGCK. RF I/O goes low whenever the refresh counter is 127, 255, or 511 (as set by End-ot-Count in Mode 7), and the RAS outputs are active. MODE 2-AUTOMATIC BURST REFRESH This mode is normally used before and/or after a DMA operation to ensure that all rows remain refreshed, provided the DMA transfer takes less than 2 ms (see Figure 4). When the DP8409A enters this mode, CASIN (RGCK) becomes the RAS Generator Clock (RGCK), and RASIN is disabled. CAS remains high, and RF I/O goes low when the refresh counter has reached the selected End-of-Count and the last RAS has ended. RF I/O then remains low until the AutoBurst Refresh mode is terminated. RF I/O can therefore be used as an interrupt to indicate the End-of-Burst conditions. The signal on all four RAS outputs is just a divide-by-four of RGCK; in other words, if RGCK has a 100 ns period, RAS is high and low for 200 ns each cycle. The refresh counter increments at the end of each RAS, starting from the count it contained when the mode was entered. If this was zero, then for a RGCK with a 100 ns period with End-of-Count set to 127, RF I/O will go low after 128 x 0.4 I'-s, or 51.2 I'-s. During this time, the system may be performing operations that do not involve DRAM. If all rows need to be burst refreshed, the refresh counter may be cleared by setting RF 110 low externally before the burst begins. Referring to Figure Sa, an external 8-bit counter (for 64k DRAMs) with TRI-STATE outputs is required and must be connected to the column address inputs. It is enabled only during this mode, and is clocked from RF I/O. The DP8409A refresh counter is used to address the rows, and the column address is supplied by the external counter. Every row for each column address is written to in all four banks. At the End-of-Count RF I/O goes low, which clocks the external counter. Therefore, for each column address, the refresh counter first outputs row-O to the address bus and all four RAS outputs strobe this row address into the DRAMs (see Figure 5b). A minimum of 30 ns after RAS goes low (tRAH = 30 ns), the refresh counter is disabled and the column ad- Burst-mode refreshing is also useful when powering down systems for long periods of time, but with data retention still required while the DRAMs are in standby. To maintain valid refreshing, power can be applied to the DP8409A (set to Mode 2), causing it to perform a complete burst refresh. When end-of-burst occurs (after 26 I'-s), power can then be removed from the DP8409A for 2 ms, consuming an average power of 1.3% of normal operating power. No control signal giiiches occur when switching power to the DP8409A. MODE 3a-ALL-RAS AUTOMATIC WRITE Mode 3a is useful at system initialization, when the memory is being cleared (i.e., with all-zeros in the data field and the 1-28 C DP8409A Functional Mode Descriptions (Continued) "'tJ dress input latch is enabled onto the address bus. About 14 ns after the column address is valid, CAS goes low, (tAse = + 14 ns), strobing the column address into the DRAMs. When RAS and CAS go high the refresh counter increments to the next row and the cycle repeats. Since WE is kept low in this mode, the data at DI (input data) of the DRAMs is written into each row of the latched column. During each cycle RAS is high for two periods of RGCK and low for two periods, giving a total write-cycle time of 400 ns minimum, which is adequate for most 16k and 64k DRAMs. On the last row of a column, RF I/O increments the external counter to the next column address. o (1) ./:>0 At the end of the last column address, an interrupt is generated from the external counter to let the system know that initialization has been completed. During the entire initialization time, the system can be performing other initialization functions. This approach to memory initialization is both automatic and fast. For instance, if four banks of 64k DRAMs are used, and RGCK is 100 ns, a write cycle to the same location in all four banks takes 400 ns, so the total time taken in initializing the 64k DRAMs is 65k X 400 ns or 26 ms. When the system receives the interrupt, the external counter must be permanently disabled. ADS and CS are interfaced by the system, and the DP8409A mode is changed. The interrupt must then be disabled. REQUIRED IF SYSTEMSTIU OPERATING WHilE DP8409A IN MDOE3A ~ PROCESSOR ADDRESS BUS RAS 0-3 DRAMS RASlN--r-----r---------~----_r~1 WiN WRITE PROCESSOR ADS CASIN M1 Ml .0 IRGCK) --H---- . The PAL has two functions. One as an address comparator, so that when the desired port address occurs (programmed in the PAL), the comparator gates the data into a latcli, where it is connected to the mode pins of the DP8409A. Hence the mode of the DP8409A can be changed as desired with one PAL chip merely by addressing the PAL location, and then outputting data to the mode-control pins. In this manner, all the automatic modes may be selected, assigning RIC as RFCK always, and CASIN as RGCK always. The output from RF I/O may be used as End-of-Count to an interrupt, or Refresh Request to HOLD or BUS REQUEST. A complex system may use Modes 5 and 1 for automatic access and refresh, Modes 3a and 7 for system initialization, and Mode 2 (autoburst refresh) before and after DMA. If basic auto access and refresh are required, then in cases where the user requires the minimum of external complexity, Modes 1 and 5 are ideal, as shown in Figure 13a. The DP843X2 is used to provide proper arbitration between memory access and refresh. This chip supplies all the necessary control signals to the processor as well as the DP8409A. Furthermore, two separate CAS outputs are also included for systems using byte-writing. The refresh clock RFCK may be divided down from either RGCK using 'an IC counter such as the DM74LS393 or better still, the DP84300 Programmable Refresh Timer. The DP84300 can provide RFCK periods ranging from 15.4 I£s to 15.6 I£s based on the input clock of 2 to 10 MHz. Figure 13b shows the general timing diagram for interfacing the DP8409A to different microprocessors using the interface controller DP843X2. OUTPUT UNDER TEST RD -I. . 0-1".,.,,"' .,. . . 1&Q !"' s,~ -~~-...,O INPUT 1.5V 1ttZH- TEST POINT t~" YoH 'ZHI,...--";::: >-.....__oIIl'Gtt z----:.....t .::::..-...:..~F=::;:=.D,5V J 2.7V VUL ~O.8:::V_.....;;;; l,:!L TUF/8409-22 TUF/8409-21 FIGURE 12. Waveform FIGURE 11. Output Load Circuit 16·811 MICROPROCESSOR DATA 8US ~_..%_......,MICROPROCESSOR DATA ADO.~ ADDRESS 8US _ _""'I_ _... ...-+I _~ MICROPROCESSOR L=.;;;;;;~~llnr~~~lmm tnlE SELECT WAIT INPUT w~--~ TO THE OPl43X2 CHIP INSERTS AWAIT STATE DURING ACCESSING. THIS IS NEtESSARY FOR VERY FAST MICRO- PROCESSORS NEaSSARY IF INSTRUCTIONS INCLUDE ,!:=:.::..====!------_I 74S244 mu DM SELECT UPPER BYTE ~~~L~S~EL~EC~T~~~W~E.~B~"~E _ _ _ _ _ _~I BYTE·WRmNG.DTHERWISE USE ~ DIRECTLY FROM THE DP8409A TO THE RAMS. I~~~~~~~~ NECESSARY IF MORE THAN ONE BANK ... TUF/8409-23 FIGURE 13a. Connecting the DP8409A Between the 16-Blt Microprocessor and Memory 1-42 o Applications I (Continued) ~ MEMORY CYCLE I HIDDEN ----' -REFRESH ACCESS-l -ELSEWHERE CYCLE 1 1 1- - MEMORY CYCLE-I- MEMORY CYCLE-! 0"4300 MINIMIZES LOW TIME TO 20 CLOCKS MAXIMIZINB CHANCE OF HIDDEN REFRESH RFCK SELECTING ELSEWHERE I IFORCED REFRESH ......- - - L____,~------~---------- ~~AO~ lIIR1I ----~~----------t_--------~.--------------~ RnOUTPUTS QO-8 ROW °T IS MICROPROCESSOR'S CLOCK PERIO~ TL/F/B409-24 FIGURE 13b_ DP8409A Auto Refresh II 1-43 >< 0) iij ~ 0) ,... -.:I' co ...... 0) '?A National ~ Semiconductor PRELIMINARY DP8417/NS32817, 8418/32818, 8419/32819, 8419X/ ,... 32819X 64k, 256k Dynamic RAM Controller/Drivers co C\I C') ...... 0) ,... -.:I' co ;0 ,... co C\I C') ...... co ,... -.:I' co ...... ..... ,... co C\I C') en z...... ..... ,... -.:I' co c.. C General Description Operational Features The DP8417/8418/8419/8419X represent a family of 256k DRAM Controller/Drivers which are designed to provide "No-Waitstate" CPU interface to Dynamic RAM arrays of up to 2 Mbytes and larger. Each device offers slight functional variations of the DP8419 design which are tailored for different system requirements. All family members are fabricated using National's new oxide isolated Advanced Low power Schottky (ALS) process and use design techniques which enable them to significantly out-perform all other LSI or discrete alternatives in speed, level of integration, and power consumption. Each device integrates the following critical 256k DRAM controller functions on a single monolithic device: ultra precise delay line; 9-bit refresh counter; fall-through row, column, and bank select input latches; Row/Column address muxing logic; on-board high capacitive-load RAS, CAS, and Write Enable & Address output drivers; and, precise control signal timing for all the above. There are four device options of the basic DP8419 Controller. The DP8417 is pin and function compatible with the DP8419 except that its outputs are TRI-STATE®. The DP8418 changes one pin and is specifically designed to offer an optimum interface to 32 bit microprocessors. The DP8419X is functionally identical to the DP8419, but is available in a 52-pin DIP package which is upward pin compatible with National's new DP8429D 1 Mbit DRAM Controller/ Driver. • Makes DRAM Interface and refresh tasks appear virtually transparent to the CPU, making DRAMs as easy to use as static RAMs • Specifically designed to eliminate CPU wait states up to 10 MHz or beyond • Eliminates 15 to 20 SSI/MSI components for significant board real estate reduction, system power savings and the elimination of chip-to-chip AC skewing • On-board ultra precise delay line • On-board high capacitive RAS, CAS, WE, and address drivers (specified driving 88 DRAMs directly) • AC specified for directly addressing up to 8 Megabytes • Low power/high speed bipolar oxide isolated process • Upward pin and function compatible with new DP8428/ DP8429 1 Mbit DRAM controller drivers • Downward pin and function compatible with DP8408A1 DP8409A 64k/256k DRAM controller/drivers • 4 user selectable modes of operation for Access and Refresh (2 automatic, 2 external) Each device is available in plastic DIP, Ceramic DIP, and Plastic Chip Carrier (PCC) packaging. (Continued) Contents • • • • System and Device Block Diagrams Recommended Companion Components Device Connection Diagrams and Pin Definitions Family Device Differences (DP841 9 vs DP8409A, 8417, 8418, 8419X) • Mode of Operation (Descriptions and Timing Diagrams) • Application Description and Diagrams • DC/ AC Electrical Specifications, Timing Diagrams and Test Conditions System Diagram CPU 32-BIT 16-BIT 8- BIT DP8417 DP8418. OR DP8419 MULTIPLEXED ADDRESS BUS 00-8(500 pF DRIVERS) 2S6K DRAM mO-3 (lS0pF DRIVERS) 1----.===----'\1 CO~~~~~iiR/ CAS (600pF DRIVER) WE (500 pF DRIVER) 4 BANKS DF 256K DYNAMIC RAMS UPTO 2 MEGABYTES PLUS ERROR CORRECTION. CHECK BITS ~~~~~C~==;;;;;:====~DATA IN DATA OUT DP84XX2 CPU SPECIFIC REFRESH/ACCESS ARBITRATION ERRCR CORRECIIOII 1'....- - - 1 CHECK BITS OUT TL/F/8396-25 1-44 r--------------------------------------------------------------------,c General Description "'0 0) (Continued) an access, leaving the three non-selected banks in the standby mode (less than one tenth of the operating power) with data outputs in TRI-STATE. The DP8419 has two mode-select pins, allowing for two refresh modes and two access modes. Refresh and access timing may be controlled either externally or automatically. The automatic modes require a minimum of input control signals. A refresh counter is on-chip and is multiplexed with the row and column inputs. Its contents appear at the address outputs of the DP8419 during any refresh, and are incremented at the completion of the refresh. Row/Column and bank address latches are also on-chip. However, if the address inputs to the DP8419 are valid throughout the duration of the access, these latches may be operated in the fallthrough mode. In order to specify each device for "true" worst case operating conditions, all timing parameters are guaranteed while the chip is driving the capacitive load of 88 DRAMs including trace capacitance. The chip's delay timing logic makes use of a patented new delay line technique which keeps A.C. skew to ± 3 ns over the full Vee range of ± 10% and temperature range of - 55'C to + 125'C. The DP8417, DP8418, DP8419, and DP8419X guarantee a maximum RASIN to CASOUT delay of 80 ns or 70 ns even while driving a 2 Mbyte memory array with error correction check bits included. Speed selected options of these devices are shown in the switching characteristics section of this document. With its four independent RAS outputs and nine multiplexed address outputs, the DP8419 can support up to four banks of 16k, 64k or 256k DRAMs. Two bank select pins, B1 and BO, are decoded to activate one of the RAS signals during ..... "" ....... ...... z CJ) (0) N 0) ..... ....... ...... 0) ..... "" 0) ...... (0) N 0) ..... 0) ...... 0) ..... "" CD ...... (0) N 0) ..... System Companion Components Device # Function DP84300 DP84412 DP84512 DP84322 DP84422 DP84522 DP84432 DP84532 DP8400-2 DP8400-4 DP8402A Programmable Refresh Timer for DP84xx DRAM Controller NS32008/16/32 to DP8409A117 118/19128129 Interface NS32332 to DP8417/18/19/28/29 Interface 68000108110 to DP8409A/17 118/19/28/29 Interface (up to 8 MHz) 68000108110 to DP8409A/17 118/19128/29 Interface (up to 12.5 MHz) 68020 to DP8417/18/19/28/29 Interface 8086/88/186/188 to DP8409A/17/18/19/28/29 Interface 80286 to DP8409AI 17 I 181 191 28/29 Interface 16-bit Expandable Error Checker/Corrector 16-bit Expandable Error Checker/Corrector 32-bit Error Detector and Corrector (EDAC) 1-45 CD ...... 0) ..... ""CD >< ...... (0) N 0) ..... >< CD ~ .... !...... Block Diagrams DP8417, 8419 and 8419X ~ .... RO-9 :C;; ADS - .... ~.... \ .....--""1 HIGH CAPACITIVE DRIVE CAPABILITY OUTPUTS YI~j'" "'~Do-. 1---'1/I CO-g I ' I I ~.... I I I ~.... IrQ! ~.... IrQ! IrQ Ir:: DECODER Iml Bl_ Imo .... i Q OO-g I I cs_ ro- nmIi_ CONTROL LOGIC RI~IRFCKI_ cmlf (RGCKI _ Will l RF 110 [>--wr t t t M21mlil RAHS MO TLIF18396-26 DP8418 RD-S \ ADS J~ CD-S I I I I I I HIGH CAPACITIVE DRIVE CAPABILITY OUTPUTS OD-9 ! I I I ffl3 RAS 2 RAS 1 RAS 0 _I CAS nmIi_ RiC CONTROL LOGIC (RFCKI CASiN (RGCKI _ WIN t t t RF 110 M2(RFSHI RAHS 1-46 f MO [>--iVE TllF18396-27 c"'CI Connection Diagrams (Dual-In-Line Package) CD ..... ...... .j:Oo RASiN R!C(RFCK) R!C(RFCK) 48 CASIN (RGCK) 47 cs MO 46 RF RAHS 45 M2(RFSH) 44 WiN WE ADS 43 00 ADS RO 42 01 RO CO 41 02 CO Rl 40 03 Rl 39 04 Cl 38 GNO R2 37 05 C2 36 VCC GND CASIN (RGCK) I/o MO RAHS M2(RFSH) Cl 10 R2 II C2 12 GNO 13 R3 14 35 06 R3 C3 IS 34 07 C3 R4 16 33 OB R4 C4 17 32 CiS C4 R5 18 31 RAS3 R5 C5 19 30 RAS2 C5 R6 20 29 RASI NC C6 21 28 RASO NC R7 22 27 BO R6 OP8417 OR OP8419 C7 23 26 Bl C6 R8 24 25 C8 R7 C7 TLiF/8396-28 R8 10 II 12 13 14 OPB419X IS 16 17 18 19 20 21 22 23 24 25 26 ....... Z 52_ RASIN 51_ CS 50 RF I/o 49 WIN 48 WE 47 00 46 NC 45 01 44 02 43 03 42 04 41 GNO 40 GNO 39 3B 05 VCC 37 06 36 07 35 OB 34_ CAS 33_ RAS3 32_ RAS2 31_ RASI 30_ RASO 29 BO 28 Bl 27 C8 (/) W II.) CD ..... ...... ....... CD ..... CD .j:Oo ....... W II.) CD ..... CD ....... CD ..... CD .j:Oo ....... W II.) CD ..... CD ....... CD .j:Oo ..... CD >< ....... W II.) ..... CD >< CD TLiF/8396-29 R!C(RFCK) 48 RASIN CASIN (RGCK) 47 cs I/o MO 46 RF RAHS 45 M2 (RFSH) 44 WiN WE ADS 43 00 RO 42 01 CO 41 02 Rl 40 03 Cl 10 39 04 R2 II 38 GNO C2 12 37 05 GND 13 36 vce R3 14 35 06 OP8418 C3 IS 34 07 R4 16 33 08 C4 17 32 CiS R5 18 31 RAS3 C5 19 30 RAS2 R6 20 29 RASI C6 21 28 RASO R7 22 27 NC C7 23 26 Bl R8 24 25 C8 TLiF/8396-30 Order Number DP8417D-70, DP8417D-80, DP8417N-70, DP8417N-80, DP8418D-70, DP8418D-80, DP8418N-70, DP8418N-80, DP8419D-70, DP8419D-80, DP8419N-70, DP8419N-80, DP8419XD-70 or DP8419XD-80. See NS Package Number D48A, D52A, or N48A 1-47 >< Q) ,.. CO C'I Connection Diagrams (Continued) C') Plastic Chip Carrier Package ...... >< Q) ,.. '< ...... W N CCI ..... >< U) Pin Definitions (Continued) Because of distributed trace capacitance and inductance and DRAM input capacitance, current spikes can be created, causing overshoots. and undershoots at the DRAM inputs that can change the contents of the DRAMs or even destroy them. To reduce these spikes, a damping resistor (low inductance, carbon) should be inserted between the DP8419 outputs and the DRAMs, as close as possible to the DP8419. The damping resistor values may differ depending on how heavily an output is loaded. These resistors should be determined by the first prototypes (not wirewrapped due to the larger distributed capacitance and inductance). Resistors should be chosen such that the transition on the control outputs is critically damped. Typical values will be from 150 to 1000, with the lower values being used with the larger memory arrays. Note that AC parameters are specified with 150 damping resistors. For more information see AN-305 "Precautions to Take When Driving Memories". indicating that no hidden refresh was performed while RFCK was high. When this pin is set low by an external gate the on-chip refresh counter is reset to all zeroes. WIN: Write Enable Input. WE: Write Enable Output - WE follows WIN unconditionally. RAHS: Row Address Hold Time Select - Selects the tRAH to be generated by the DP8419 delay line to allow use with fast or slow DRAMs. CAS: Column Address Strobe Output - In mode 5 and in mode 4 with CASIN low before RIC goes low, CAS goes low automatically after the column address is valid on the address outputs. In mode 4 CAS follows CASIN directly after RIC goes low, allowing for nibble accessing. CAS is always high during refresh. RAS 0-3: Row Address Strobe Outputs - The enabled RAS output (see Table II) follows RASIN directly during an access. During refresh, all RAS outputs are enabled. DP8419 DRIVING ANY 16k, 64k or 256k DRAMs BO, B1: Bank Select Inputs· These pins are decoded to enable one of the four RAS outputs during an access (see Table I and Table II). The DP8419 can drive any 16k, 64k or 256k DRAMs. All 16k DRAMs use basically the same configuration, including the 5V-only version. Hence, in most applications, different manufacturers' DRAMs are interchangeable (for the same supply-rail chips), and the DP8419 can drive them all (see Figure 1a). There are three basic configurations for the 5V-only 64k DRAMs: a 128-row by 512-column array with an on-RAM refresh counter, a 128-row by 512-column array with no onRAM refresh counter, and a 256·row by 256-column array with no on-RAM refresh counter. The DP8419 can drive all three configurations, and allows them all to be interchangeable (as shown in Figures 1b and 1e), providing maximum flexibility in the choice of DRAMs. Since the 9-bit on-chip refresh counter can be used as a 7-bit refresh counter for the 128-row configuration, or as an 8-bit refresh counter for the 256-row configuration, the on-RAM refresh counter, if present, is never used. TABLE I. DP8417, DP8419, DP8419X Memory Bank Decode Bank Select (Strobed by ADS) B1 BO 0 0 1 1 0 1 0 1 Enabled RAS n RASo RAS1 RAS2 RAS3 TABLE" DP8418 Memory Bank Decode Bank Select (Strobed by ADS) B1 NC 0 1 X X Enabled RASn RASo and RAS1 RAS2 and RAS3 256k DRAMs require all 18 of the DP8419's address inputs to select one memory location within the DRAM. RAS-only refreshing with the nine-bit refresh-counter on the DP8419 makes CAS before RAS refreshing, available on 256k DRAMs, unnecessary. Conditions for All Modes INPUT ADDRESSING READ, WRITE AND READ·MODIFY·WRITE CYCLES The address block consists of a row-address latch, a column-address latch, and a resettable refresh counter. The address latches are fall-through when ADS is high and latch when ADS goes low. If the address bus contains valid addresses until after CAS goes low at the end of the memory cycle, ADS can be permanently high. Otherwise ADS must go low while the addresses are still valid. The output signal, WE, determines what type of memory access cycle the memory will perform. If WE is kept high while CAS goes low, a read cycle occurs. If WE goes low before CAS goes low, a write cycle occurs and data at DI (DRAM input data) is written into the DRAM as CAS goes low. If WE goes low later than tewD after CAS goes low, first a read occurs and DO (DRAM output data) becomes valid, then data DI is written into the same address in the DRAM as WE goes low. In this read-modify-write case, DI and DO cannot be linked together. WE always follows WIN directly to determine the type of access to be performed. DRIVE CAPABILITY The DP8419 has timing parameters that are specified driving the typical capacitance (including traces) of 88, 5V-only DRAMs. Since there are 4 RAS outputs, each is specified driving one-fourth of the total memory. CAS, WE and the address outputs are specified driving all 88 DRAMs. POWER·UP INITIALIZE When Vee is first applied to the DP8419, an initialize pulse clears the refresh counter and the internal control flip-flops. The graph in Figure 10 may be used to determine the slight variations in timing panJJneters due to loading conditions other than 88 DRAMs. j 1-50 C Mode Features Summary .,..".... ....... 01) • 4 modes of operation: 2 access and 2 refresh • Automatic or external control selected by the user • Auto access mode provides RAS, row to column change, and then CAS automatically • Choice between two different values of tRAH in auto-access mode • CAS controlled independently in external control mode, allowing for nibble mode accessing • Automatic refreshing can make refreshes transparent to the system • ~ is inhibited during refresh cycles A burst refresh may be performed by holding RFSH low and toggling RASIN until all rows are refreshed. It may be useful in this case to reset the refresh counter just prior to beginning the refresh. The refresh counter resets to all zeroes when RFI/O is pulled low by an external gate. The refresh counter always counts to 511 before rolling over to zero. If there are 128 or 256 rows being refreshed then 07 or 08, respectively, going high may be used as an end-of-burst indicator. In order that the refresh address is valid on the address outputs prior to the RAS lines going low, RFSH must go low before i1Am. The setup time required is given by tRFLRL in the Switching Characteristics. This parameter may be adjusted using Figure 10 for loading conditions other than those specified. DP8419 Mode Descriptions MODE O-EXTERNALLY CONTROLLED REFRESH Figure 2 shows the Externally Controlled Refresh timing. In this mode the refresh counter contents are multiplexed to the address outputs. All RAS outputs are enabled to follow i1Am so that the row address indicated by the refresh counter is refreshed in all DRAM banks when i1Am goes low. The refresh counter increments when RASIN goes high. RFSH should be held low at least until RASIN goes high (they may go high simultaneously) so that the refresh address remains valid and all RAS outputs remain enabled throughout the refresh. TABLE III. DP8419 Mode Select Option. Mode 0 1 4 5 (llfF!Fl) M2 MO 0 0 0 1 1 0 1 1 Mode of Operation Externally Controlled Refresh Auto Refresh-Forced Externally Controlled Access Auto Access (Hidden Refresh) ...... Z (f) Co) N .... 01) ....... ...... 01) .,..... 01) ...... Co) ~ 01) ...... 01) .... .,..... ~ ~ .... .,.....~ 01) ~ .... CD Co) N 01) >< 1-51 >< en «; DP8419 Mode Descriptions (Continued) C\I C') >< DP8419 Interface Between System & DRAM Banks ~ r---------------i~iS~-- ·~::::::::::::::~~----------l en .,... ~ .,... __ ~ CIO --, C') R en .,... .., Iil'AD·D·RE·SS+~-"''+1 ~ C\I COL. DECODE 128 o ....... 128 A~~~ Y ~ 8US CIO ....... CIO .,... CIO +12Vor +5V 16K DYNAMIC RAMS C\I DP8419 C') ....... TLiF/8396-5 ..,.,... CIO CIO ....... ..... .,... CIO C\I FIGURE 1a. DP8419 with any 16k DRAMS ~AS LATCHES 7 ROW. 1 COLUMN ADDRESS CAS LATCHES 8 COLUMN AODRESSES CA~ I-I-"'~I-----------. C') ~ (J) Z ....... IIASH~"'+-- CIO ADDRESS BUS ..... .,... .., 128 Il. C 64K ARRAY IF. ON·CHIP REFRESH COUNTER. NOT USED .5V 64K DYNAMIC RAMS DPB419 TLiF/8396-6 Only LS 7 Bits of Refresh Counter used for the 7 Row Addresses. MSB not used but can toggle. FIGURE 1b. DP8419 with 128 Row x 512 Column 64k DRAM CAS WE -t--. liAS I---... """l r-=='==....., R o ADDRESS BUS +5V 64K W 256 64K ARRAY DYNAMIC RAMS DPB419 TLiF/8396-7 8 Bits of Refresh Counter Used FIGURE 1c. DP8419 with 256 Row x 256 Column 64k DRAM o E C 512 256K ARRAY .5V 256K DYNAMIC RAMS o I~ I DP84191 TLiF /8396-8 All 9 Bits of Refresh Counter Used FIGURE 1d. DP8419 with 256k DRAMs 1-52 C -a OCI DP8419 Mode Descriptions (Continued) ,j::o. ..... -... ....... Z CJ) INPUTS RASIN Co) N OCI ..... -... ....... OCI ,j::o. ..... OCI ....... Co) N OCI CASilI AND ..... R/f OCI ....... OCI ,j::o. ..... CQ OUTPUTS ....... RAS 0 Co) N OCI ..... CQ ....... RAS 1,2,3 00 ,j::o. ..... >< ....... CQ tROHNC REFRESH CTR COUNTER RESET n+l Co) N OCI ..... >< CQ 00·8 REFRESH COUNT n tRFLCT ~tRST~ RFI/O --------------------------~I -- ~I COUNTER RESET INPUT TLlF/B396-9 ·Indicates Dynamic RAM Parameters FIGURE 2a. External Control Refresh Cycle (Mode 0) MODE 1iIE M_OO_EO --1r-tRFPDH RAS 0·3 tRFLCT.... 00·8 r- . . 1 III LJ U 1 \..... tROHNC ~;---'"'\X! n+l TL/F/B396-10 FIGURE 2b. Burst Refresh Mode 0 1·53 ~r------------------------------------------------------------------ i DP8419 Mode Descriptions (Continued) ~ MODE 1-AUTOMATIC FORCED REFRESH ~ ... In Mode 1 the RIC (RFCK) pin becomes RFCK (refresh cycle clock) and the CASiN (RGCK) pin becomes RGCK (RAS generator clock). If RFCK is high and Mode 1 is entered then the chip operates as if in MODE 0 (externally controlled refresh), with all RAS outputs following RASTf\l. This feature of Mode 1 may be useful for those who want to use Mode 5 (automatic access) with externally controlled refresh. By holding RFCK permanently high one need only toggle M2 (i'i'FSR) to switch from Mode 5 to external refresh. As with Mode 0, RFIIO may be pulled low by an external gate to reset the refresh counter. .. ~ :;; ... ~ ~ .. ~ ;: ~ (") ~ :; CCI j::: co be used to reset the counter in this case since RFIIO is forced low internally for a request). After receiving the refresh request the system must allow a forced refresh to take place while RFCK is low. External logic can monitor ~ (RFIIO) so that when ~ goes low this logic will wait for the access currently In progress to be completed before pulling M2 ('FiFSFi) low to put the DP8419 in mode 1. If no access is taking place when ~ occurs, then M2 may immediately go low. Once M2 is low, the refresh counter contents appear at the address outputs and RAS is generated to perform the refresh. An external clock on RGCK is required to derive the refresh RAS signals. On the second falling edge of RGCK after M2 When using Mode 1 as automatic refresh, RFCK must be an input clock Signal. One refresh should occur each period of RFCK. If no refresh is performed while RFCK is high, then when RFCK goes low RFIIO immediately goes low to indicate that a refresh is requested. (RFIIO may still be used to reset the refresh counter even though it is also used as a refresh request pin, however, an open-collector gate should is low, all RAS lines go low. They remain low until two more falling edges of RGCK. Thus RAS remains high for one to two periods of RGCK after M2 goes low, and stays low for two periods. In order to obtain the minimum delay from M2 going low to RAS going low, M2 should go low tRFSRG before the falling edge of RGCK. N (") (/) ..... Z ..... ..... CCI a... Q (j) RFCK -I r-IRGCKL , -I r-IRGCKH RGCK r-1_IROHRFf=~IR~~RL~_ _ 8088/32016 ACKNOWLEDGES HOLD 68000 GRANTS BUS (MODE 5) M2 (RFSH) @) I1 I® RF 110 (RFRO), (MODE 1) r-IFROH 8086/32016 REMOVES ACKNOWLEDGE 68000 REMOVES GRANT (MODE 5) I r-tRFHRV-j R~OUEST REMOVED J rl--,--rI---r"J-.::!!!~""I......!..I-"'!'®""';I ~~LR==J~I ----:1-,.--'-.1. REFRESH '------....;.,----:..I_I@-li-'RGRHI I-IFROL ® I I-IRBRL 1 i- RAS 0, 1,-2,-3 \: 00-8 CAS 7 TO SELECTED BANK ~P ACCES 1 I J-j" >IRP---' ~--C-OLS--~,......-CO-L-S-..;.X I . ___ \ I -I REFRESH COUNTER ~ ACCESS TO SELECTED BANKS ~ i--IRFLCT LS .J TLiF /8396-11 (j) RFCK goes low @ Forced refresh RAS starts after> T Cl> RFRQ goes low if no hidden refresh (> tRP) occurred while RFCK was high (j) Forced refresh RAS ends RFRQ ® Next RASIN starts nexl access ~p acknowledges refresh request cr> ,..p removes refresh acknowledge FIGURE 3. DP8419 Performing a Forced Refresh (Mode 5 - 1-54 1- 5) with Various Microprocessors C "'a DP8419 Mode Descriptions (Continued) OCI this is 400 ns. To refresh 128 rows every 2 ms an average of about one refresh per 16 is required. With a RFCK period of 16 and RGCK period of 100 ns, DRAM accesses are delayed due to refresh only 2.5% of the time. If using the Hidden Refresh available in mode 5 (refreshing with RFCK high) this percentage will be even lower. The Refresh Request on RFI/O is terminated as RAS goes low. This signal may be used to end the refresh earlier than it normally would as described above. If M2 is pulled high while the RAS lines are low, then the RASs go high tRFRH later. The designer must be careful, however, not to violate the minimum RAS low time of the DRAMs. He must also guarantee that the minimum RAS precharge time is not violated during a transition from mode 1 to mode 5 when an access is desired immediately following a refresh. If the processor tries to access memory while the DP8419 is in mode 1, WAIT states should be inserted into the processor cycles until the DP8419 is back in mode 5 and the desired access has been accomplished (see Figure 9). MODE 4 - EXTERNALLY CONTROLLED ACCESS In this mode all control signal outputs can be controlled directly by the corresponding control input. The enabled RAS output follows RASIN, CAS follows CASIN (with RIC low), WE follows WIN and RIC determines whether the row or the column inputs are enabled to the address outputs (see Figure 4). Instead of using WAIT states to delay accesses when refreshing, HOLD states could be used as follows. RFRQ could be connected to a HOLD or Bus Request input to the system. When convenient, the system acknowledges the HOLD or Bus Request by pulling M2 low. Using this scheme, HOLD will end as the RAS lines go low (RFI/O goes high). Thus, there must be sufficient delay from the time HOLD goes high to the DP8419 returning to mode 5, so that the RAS low time of the DRAMs isn't violated as described earlier (see Figure 3 for mode 1 refresh with Hold states). To perform a forced refresh the system will be inactive for about four periods of RGCK. For a frequency of 10 MHz, ·Resistors required DRAM load. depends '"'S '"'S With RIC high, the row address latch contents are enabled onto the address bus. FiJiJi going low strobes the row address into the DRAMs. After waiting to allow for sufficient row-address hold time (tRAH) after RAS goes low, RIC can go low to enable the column address latch contents onto the address bus. When the column address is valid, CAS gOing low will strobe it into the DRAMs. WIN determines whether the cycle is a read, write or read-modify-write access. Refer to Figures 58 and 5b for typical Read and Write timing using mode 4. -~ + 6 Check B"s for ECC. For 2 Banks, can drive 32 data bits r- + 7 Check Bits for ECC. ~ For 1 Bank, can drive 64 data bits + 8 Check Bits for ECC. I I I I AO-15. 17. 19 INPUT iiAl ROW/ClIUiMii SEL Wlil'fE REFRESH ~ I I DATA RAS 3 ; : . RAS 2 ~1~ RAS 0 ....- ./ m CAS WE BANK 3 J ./ ./ RAS CAS WE SANK 2 ~ AO-6.7.S - ./ iiAS CAS DP8418 CAS WE ..• l- iiAS CAS WE A. BANK 1 CS DND t 00·6,7.B MO ~ V ./ BANK 0 W//~ AO-6. 7. B r .A~ -V /' ~ M2 'f -V ./ ....- Bl mtIf A. ~~ /' ~$ AO·6. 7.B C0-6. 7. S WIN • ~ A. AO·6.7.S WE R/e I I I • ----! BOADS ~ ~ RO·6. 7. S ....~ ::::! OCI •.... OCI ....... Co) I\) .... OCI OCI co •.... CD ....... Co) I\) .... OCI CD ....... OCI •.... CD >< ....... Co) N OCI >< on WiN z en Co) .... For 4 Banks, can drive 16 data bits I ....... CD DRAM • Maybe 16k, 64k or 256k INPUT CAS ALE •.......... A J ~~ 16Ks. 64Ks, 256Ks t ~ 00".-00/~ " TLlF/B396-12 FIGURE 4. Typical Application of DP8419 Using External Control Access and Refresh In Modes 0 and 4 1-55 >< CD ,.. CO N CO) ...... >< CD ,.. ~ CO ...... ,.. CD DP8419 Mode Descriptions (Continued) INPUTS 'INDICATES DYNAMIC RAM PARAMETERS ADS (AlEI SYSTEM ADDRESS BUS CO N CO) ...... ,.. CD :...... -4__ ____-+__________ CASIN __ ~ ~ ________________ ________ ~ ~~ ________ ,.. CO CO N Ric CO) ...... CO ,.. OUTPUTS ~ CO ,... ,.. ...... HAS 0,1,2,3 CO N CO) QIJ.8 U) Z ,... ,.. ...... ... - fCCAS --. ~ CO 11. o DRAM DATA DUT ~------4----------~ -----------------------(1 TL/F/8396-13 FIGURE 5a. Read Cycle Timing (Mode 4) INPIITS 'INDICATES DYNAMIC RAM PARAMETERS ADS (AlEI SYSTEM ADDRESS BUS RIC DRAM DATA IN ---;--i----;-------;---(i 1'---...,---'\ DUTPIITS HAS D,1,2,3 --i---.:-----; QD-8 TL/F/8396-14 FIGURE 5b. Write Cycle Timing (Mode 4) 1-56 o"0 DP8419 Mode Descriptions (Continued) co With Auto-CAS generation, the maximum delay from RIC to CAS (loaded with 600 pF) is 46 ns. Thus the maximum RASIN to CAS time is 71 ns, under the given conditions. With a maximum RASIN to RAS time (tRPoLl of 20 ns, the maximum RAS to CAS time is about 51 ns. Most DRAMs with a 15 ns minimum tRAH have a maximum tRCO of about 60 ns. Thus, memory accesses are likely to be RAS limited instead of CAS limited. In other words, memory access time is limited by DRAM performance, not controller performance. AUTOMATIC CAS GENERATION CAS is held high when RIC is high even if CASIN is low. If CASIN is low when RIC goes low, CAS goes low automatically, tASC after the column address is valid. This feature eliminates the need for an externally derived CASIN signal to control CAS when performing a simple access (Figure 5a demonstrates Auto-CAS generation in mode 4). Page or nibble accessing may be performed as shown in Figure 5c even if CAS is generated automatically for the initial access. REFRESHING IN CONJUNCTION WITH MODE 4 If using mode 4 to access memory, mode FASTEST MEMORY ACCESS The fastest mode 4 access is achieved by using the automatic CAS feature and external delay line to generate the required delay between RASIN and RIC. The amount of delay required depends on the minimum tRAH of the DRAMs being used. The DP8419 parameter tOlF1 has been specified in order that the delay between RASIN and RIC may be minimized. + a (externally con- ..... Z (f) Co) N ......... co ..... co .... .". co ..... Co) N .... co co ..... co .... .". CD ..... Co) trolled refresh) must be used for all refreshing. N MODE 5 - AUTOMATIC ACCESS WITH HIDDEN REFRESHING CAPABILITY CD ..... co Automatic-Access has two advantages over the externally controlled access (mode 4). First, RAS, CAS and the row to column change are all derived internally from one input signal, RASIN. Thus the need for an external delay line (see mode 4) is eliminated. Secondly, since RIC and CASIN are not needed to generate the row to column change and CAS, these pins can be used for the automatic refreshing function. tOlF1 = MAXIMUM (tRPDL - tRHA) where tRPOL = RASIN to RAS delay and tRHA = row address held from RIC going low. The delay between RASIN and RIC that guarantees the specified DRAM tRAH is given by MINIMUM RASIN to RIC = tOlF1 Example ......... .". With tOlF1 (from Switching Characteristics) = 7 ns, RASIN to RIC delay = 7 ns + 15 ns = 22 ns. A delay line of 25 ns will be sufficient. Page or Nibble mode may be performed by toggling CASIN once the initial access has been completed. In the case of page mode the column address must be changed before CASIN goes low to access a new memory location (see Figure 5c). Parameter tCPdif has been specified in order that users may easily determine minimum CAS pulse widths when CASIN is toggling. .... co .... .". CD >< ..... Co) N .... co CD >< AUTOMATIC ACCESS CONTROL Mode 5 of the DP8419 makes accessing Dynamic RAM nearly as easy as accessing static RAM. Once row and column addresses are valid (latched on the DP8419 if necessary), RASIN going low is all that is required to perform the memory access. tRAH. In an application using DRAMs that require a minimum tRAH of 15 ns, the following demonstrates how the maximum RASIN to CAS time is determined. II I TL/F/8396-15 FIGURE 5c. Page or Nibble Access in Mode 4 1-57 >< Q) ,.. co DP8419 Mode Descriptions (Continued) N C') ...... ~ ,.. '<:I' co ...... Q) ,.. co N C') 0; ,.. ADDRESS INPUTS 1 DATA '<:I' co ...... co ,.. co N C') ;;0 ,.. '<:I' co ...... 00-11 ,.. "'" co N C') (J) Z ...... ,.. "'" '<:I' ~ C tCAC' DATA D U 1 · P U 1 · - - - - - - - - - - + - - - - - - - - - - - < >I< Indicates Dynamic RAM Parameters VALID (READ) TLlF/8396-17 FIGURE 6. Mode 5 Timing (b) by a combination of mode 5 (hidden refresh) and mode 1 (auto-refresh) or (c) by a combination of mode 5 and mode 0 (a) Externally Controlled Refreshing in Mode 0 or Mode 1 All refreshing may be accomplished using external refreshes in either mode 0 or mode 1 with RIC (RFCK) tied high (see mode 0 and mode 1 descriptions). If this is desired, the system determines when a refresh will be performed, puts the DPB419 in the appropriate mode, and controls the RAS signals directly with RASIN. The on-chip refresh counter is enabled to the address outputs of the DPB419 when the refresh mode is entered, and increments when RASIN goes high at the completion of the refresh. (Refer to Figure 6) In mode 5 the selected RAS follows RASIN immediately, as in mode 4, to strobe the row address into the DRAMs. The row address remains valid on the DPB419 address outputs long enough to meet the tRAH requirement of the DRAMs (pin 4, RAHS, of the DP8419 allows the user two choices of tRAH)' Next, the column address replaces the row address on the address outputs and CAS goes low to strobe the columns into the DRAMs. WIN determines whether a read, write or read-modify-write is done. The diagram below illustrates mode 5 automatic control signal generation. (b) Mode 5 Refreshing (hidden) with Mode 1 refreshing (auto) (Refer to Figure 7a) If RFCK is tied to a clock (see mode 1 description), RFIIO becomes a refresh request output and goes low following RFCK going low if no refresh occurred while RFCK was high. Refreshes may be performed in mode 5 when the DPB419 is not selected for access (CS is high) and RFCK is high. If these conditions exist the refresh counter contents appear on the DPB419 address outputs and all RAS lines follow RASIN so that if RASIN goes low (an ~_ccess other than through the DP8419 OCCUfSj, aii RAS lines go low to perform the refresh. The DPB419 allows only one refresh of this type for each period of RFCK, since RFCK should be fast enough such that one refresh per period is sufficient to meet the DRAM refresh requirement. TL/F 18396-16 REFRESHING IN CONJUNCTION WITH MODE 5 When using mode 5 to perform memory accesses, refreshing may be accomplished: (a) externally (in mode 0 or mode 1) 1-58 ~----------------------------------------------------------~C ." DP8419 Mode Descriptions (Continued) co .... ~ Once it is started, a hidden refresh will continue even if RFCK goes low. However, CS must be high throughout the refresh (until RASIN goes high). System Characteristics: 1) DRAM used has min tRAH requirement of 15 ns and min tASR of 0 ns 2) DRAM address is valid from time Tv to the end of the memory cycle 3) four banks of twenty-two 256K memory chips each are being driven Using the DP8419 (see Figure 7b): These hidden refreshes are valuable in that they do not delay accesses. When determining the duty cycle of RFCK, the high time should be maximized in order to maximize the probability of hidden refreshes. If a hidden refresh doesn't happen, then a refresh request will occur on RFIIO when RFCK goes low. After receiving the request, the system must perform a refresh while RFCK is low. This may be done by going to mode 1 and allowing an automatic refresh (see mode 1 description). This refresh must be completed while RFCK is low, thus the RFCK low time is determined by the worst-case time required by the system to respond to a refresh request. 1) Tie pin 4 (RAHS) high to guarantee a 15 ns minimum tRAH which is sufficient for the DRAMs being used 2) Generate RASIN no earlier than time Tv + tASRL (see switching characteristics), so that the row address is valid on the DRAM address inputs before RAS occurs 3) Tie ADS high since latching the DRAM address on the (c) Mode 5 Refresh (Hidden Refresh) with mode 0 Refresh (External Refresh) DPB41 9 is not necessary 4) Connect the first 18 system address bits to RO-RB and CO-C8, and bits 19 and 20 to 80 and 81 5) Connect each RAS output of the DPB419 to the RAS inputs of the DRAMs of one bank of the memory array; connect OO-OB of the DPB419 to AO-AB of all DRAMs; connect CAS of the DPB419 to CAS of all the DRAMs This refresh scheme is identical to that in (b) except that after receiving a refresh request, mode 0 is entered to do the refresh (see mode 0 description). The refresh request is terminated (RFI/O goes high) as soon as mode 0 is entered. This method requires more control than using mode 1 (auto-refresh), however, it may be desirable if the mode 1 refresh time is considered to be excessive. Example Figure 7c illustrates a similar example using the DPB41B to drive two 32-bit banks. ::::! z ~ ~ CO .... ~ .... ~ ~ ~ .... CO ~ CO .... ~ CD ...... Co) ~ CO .... CD ...... CO .... ~ CD >< ...... Co) ~ .... CO CD >< Figure 7b demonstrates how a system designer would use the DPB419 in mode 5 based on certain characteristics of his system. II•• I --------IRFCK:--------'I ,••- - - - - I R F C K H - - - - - t · 1 ~----IRFCKL i FDRCES REFRES~ I N~c~~~~~D r- ~~ HIDDEN REFRESH ALLOWED , . . - - - - . . , . - - PRDCESSDR ACCESSING ELSEWHERE fS .......,L,~ ; ~ ; I~__________ -I 1 r,---------1 ----+---------------, RASlN JI 1-1 I I ~'~~----------~I----------I PROCESSDR CYCLE TIME 1- ICSHR=J II -I iifiiQ (RFI/O) RAS 0-3 ~ HIDDEN REFRESH ALREADY PERFORMED, NO- SUBSEQUENT REFRESH ALLOWED IN THIS CYCLE II ~------TIR-FPD-L5T~~I~~I--I-RFP-DH5------------I ONERAS 2Tn. -I DD.8~ ~"""""""""~ RFCTRn I SELECTED ROWS ~....._ _ _ _R_OW_S_ _ _ __ u FIGURE 7a. Hidden Refreshing (Mode 5) and Forced Refreshing (Mode 1) Timing 1-59 TL/F18396-18 DP8419 Mode Descriptions (Continued) L ./ 1m us ~ WE f$ .J- BANK 3 -y AO-. ./ L ./ RAS -. CAS WE $ I SYSTEM CLOCK I RGCK I \~ I iiAS INPUT WRifE REFRESH cs 1m, "'''_ ADS BO ~~ REFRESH CLOCK RAS3 I I HAS t RASO RD~8 ~ ./ ./ ./ -. us WE .J- , BANK ~ AD-' CD-8 --y AO-' RAS I- 1\ , BANK -y ./ DP8419 ~B' RAS RlSffi I RFCK ~ I ill CAS WE WE .A BANK 0 r WiN .. M2 I I AD-8 aO-8 CS Mo RAHS J ·T· ·t· DATA ./ 256Ks TL/F/8S96-19 FIGURE 7b_ Typical Application of DP8419 Using Modes 5 and 1 I SYSTEM CLOCK I I I I I AO-18 INPUT HAS REFRESH CLOCK WRITE REFRESH I I I I I I I I I I I I DATA HAS 2 HAS, ~ l~ I RAS3 ROCK " 1 " _ ADS • HAS 0 RO-8 t l RAS2 RAS3 AD-8 WE r+ CAS ~ CO-B 81 RASIN RFCK CAS WIN WE M2 00-8 cs t MO . AO-8 BANK 1 OP8418 OATAO-1S BANKl WE CAS ~ RASO RASl , -- RAHS JJ AO-8 1 AO-8 BANKO CAS WE 32'81T DATA 8US DATA 16,31 ~ BANKO CAS OATAO-1S & WE DATA 16-31 .0- I ... TL/F/8S96-SS FIGURE 7c. Typical Application of DP8418 Using MOd'!s 5 and 1 1-60 C "'D OCI Applications microprocessors and the DP84XX family of DRAM controller/drivers. These PALs interface to all the necessary control signals of the particular processor and the DP8419. The PAL controls the operation of the DP8419 in modes 5 and 1, while meeting all the critical timing considerations discussed above. The refresh clock, RFCK, may be divided down from the processor clock using an IC counter such as the DM74LS393 or the DP84300 programmable refresh timer. The DP84300 can provide RFCK periods ranging from 15.4 fLs to 15.6 fLs based on an input clock of 2 to 10 MHz. Figure 8 shows a general block diagram for a system using the DP8419 in modes 1 and 5. Figure 9 shows possible timing diagrams for such a system (using WAIT to prohibit access when refreshing). Although the DP84XX2 PALs are offered as standard peripheral devices for the DP84XX DRAM controller/drivers, the programming equations for these devices are provided so the user may make minor modification, for unique system requirements. If one desires a memory interface containing the DP8419 that minimizes the number of external components required, modes 5 and 1 should be used. These two modes provide: 1) Automatic access to memory (in mode 5 only one signal, RASIN, is required in order to access memory) 2) Hidden refresh capability (refreshes are performed automatically while in mode 5 when non-local accesses are taking place, as determined by CS) 3) Refresh request capability (if no hidden refresh took place while RFCK was high, a refresh request is generated at the RFIIO pin when RFCK goes high) 4) Automatic forced refresh (If a refresh request is generated while in mode 5, as described above, external logic should switch the DP8419 into mode 1 to do an automatic forced refresh. No other external control signals need be issued. WAIT states can be inserted into the processor machine cycles if the system tries to access memory while the DP8419 is in mode 1 doing a forced refresh). Some items to be considered when integrating the DP8419 into a system design are: ADVANTAGES OF DP8419 OVER A DISCRETE DYNAMIC RAM CONTROLLER 1) The DP8419 system solution takes up much less board space because everything is on one chip (latches, refresh counter, control logic, multiplexers, drivers, and internal delay lines). 1) The system designer should ensure that a DRAM access not be in progress when a refresh mode is entered. Similarly, one should not attempt to start an access while a refresh is in progress. The parameter tRFHRL specifies the minimum time from RFSH high to RASIN going low to initiate an access. 2) Less effort is needed to design a memory system. The DP8419 has automatic modes (1 and 5) which require a minimum of external control logic. Also programmable array logic devices (PALs) have been designed which allow an easy interface to most popular microprocessors (Motorola 68000 family, National Semiconductor 32032 family, Intel 8086 family, and the Zilog Z8000 family). 3) Less skew in memory timing parameters because all critical components are on one chip (many discrete drivers specify a minimum on-chip skew under worst-case conditions, but this cannot be used if more then one driver is needed, such as would be the case in driving a large dynamic RAM array). 4) Our switching characteristics give the designer the critical timing specifications based on TTL output levels (low = 0.8V, high = 2.4V) at a specified load capacitance. All timing parameters are specified on the DP8419: 2) One should always guarantee that the DP8419 is enabled for access prior to initiating the access (see tcSRL1). 3) One should bring RASIN low even during non-local access cycles when in mode 5 in order to maximize the chance of a hidden refresh occurring. 4) At lower frequencies (under 10 Mhz), it becomes increasingly important to differentiate between READ and WRITE cycles. RASIN generation during READ cycles can take place as soon as one knows that a processor READ access cycle has started. WRITE cycles, on the other hand, cannot start until one knows that the data to be written at the DRAM inputs will be valid a setup time before CAS (column address strobe) goes true at the DRAM inputs. Therefore, in general, READ cycles can be initiated earlier than WRITE cycles. ..... "" ..... Z tJ) W N -"" OCI ..... ..... OCI ..... OCI W N OCI ..... OCI OCI ..... "" CD W N OCI ..... CD OCI ..... ""CD >< W N OCI ..... >< CD A) driving 88 DRAM's over a temperature range of 0-70 degrees centigrade (no extra drivers are needed). 5) Many times it is possible to only add WAIT states during READ cycles and have no WAIT states during WRITE cycles. This is because it generally takes less time to write data into memory than to read data from memory. 8) under worst-case driving conditions with all outputs switching simultaneously (most discrete drivers on the market specify worst-case conditions with only one output switching at a time; this is not a true worst-case condition!). The DP84XX2 family of inexpensive preprogrammed medium Programmable Array Logic devices (PALs) have been developed to provide an easy interface between various III I 1-61 Applications (Continued) 16-BIT MICROPROCESSOR DATA BUS r-_.....;z;...._.,MICRoPIIoCESSOR ADDRESS BUS DATA AODR ~_ _. .~_"'_ _. . _+I ilQ3 MICROPllDCESSDR DPM1B R/W CLOCK UPPER BYTE LOWER BYTE ~:t:~~~111i;m.!f==1 WIll RGCK ilQ2 ilQ1 ilQD NECESSARY IF MORE THAN ONE BANK TL/F/8398-20 FIGURE 8. Connecting the DP8419 Between the 16·blt Microprocessor and Memory I ---1 -----.l FORCED L ,REFRESHI HIDDEN -REFRESH, ACCESS MEMORY CYCLE ELSEWHERE CYCLE r +- -1 !-MEMoRY CYCLE-!--MEMoRY CYCLE-I DPI43DD MINIMIZES LOW TIME TO 2D CLOCKS MQIMIZINB CHANCE OF RFCK HIDDEN REFRESH SELECTING ELSEWHERE L ----.If-------E~~i_-------- '1-1 III IIIIIlR IIPIl! _18 oUTFUTS IIFIIa (RFlIol RDOUTPUTI 00-1 ROW r~ L08IC HOLDS --------------------------------~~. 'T 18 mlcroprocesao,'s clock period ~------TL/F/8398-21 FIOURE 9. DP8419 Auto Refresh, Aceese with WAiT States 1·62 c ;g Switching Characteristics ~ The additional 1 ns is due to the fact that the RAS line is driving less (switching faster) than the load to which the 15 ns spec applies. The row address will remain valid for about the same time irregardless of address loading since it is considered to be not valid at the beginning of its transition. All AC parameters are specified with the equivalent load capacitances, including traces, of 88 DRAMs organized as 4 banks of 22 DRAMs each. Maximums are based on worstcase conditions including all outputs switching simultaneously. This, in many cases, results in the AC values shown in the DP84XX DRAM controller data sheet being much looser than true worst case (maximum) AC delays. The system designer should estimate the DP8419 load in his/her application, and modify the appropriate AC parameters using the graph in Figure 10. Two example calculations are provided below. OUTPUT UNDER TEST ~ Ro TEST POINT ~ : :CL - V/ .,F TLlF/B396-23 .... tZl -----hi .... tZH TL/F/B396-22 luI- r___... ~-- ~ ____ O•3V 3.5V - - - - - - l - VOL t. . . 'tar:-____ ______.,.7- 1.3V FIGURE 10. Change in Propagation Delay Relative to "True" (Application) Load Minus AC Specified Data Sheet Load 2 Examples >< ...... Co) ...~ ~ -t-VOH ",-- - - - - L O.3V OV TLlF/B396-34 FIGURE 11b. DP8417 TRI-STATE Waveforms # 1) A mode 4 user driving 2 16-bit banks of DRAM has the following approximate "true" loading conditions: Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply voltage, VCC 7.0V -65'C to + 150'C Storage Temperature Range - 300 pF max tRPDL = 20 ns - 0 ns = 20 ns (since F!AS loading is the same as that which is spec'ed) max tCPDL = 32 ns - 7 ns = 25 ns max tccAS = 46 ns - 7 ns = 39 ns Input Voltage 5.5V 150mA Output Current Lead Temp. (Soldering, 10 seconds) max tRCC = 41 ns - 6 ns = 35 ns min tRHA is not significantly effected since it does not involve an output transition Other parameters are adjusted in a similar manner. 300'C Operating Conditions #2) A mode 5 user driving one 16-bit bank of DRAM has the following approximate "true" loading conditions: VCC TA CAS -120 pF 00-08 - 100 pF RAS -120 pF A. C. parameters should be adjusted as follows: with RAHS = "1", max !RICL = 70 ns - 11 ns = 59 ns maxtRCDL = 55 ns + 1 ns - 11 ns = 45 ns (the + 1 ns is due to lighter RAS loading; the - 11 ns is due to lighter CAS loading) + 1 ns 1.5V \'1.3V CpF = 15 ns .... ~ ..... CD ..... CO ..... CD ~ .r__- - - - 3V OV-I---'I min tRAH ...... FIGURE 11a. Output Load Circuit -15.0 L-_.L.-_...L-....L.....L.._~_--' -500 -300 -100 0 + 100 + 300 + 500 - 250 pF ..... CD RL -7.5/ - 150 pF ~ ..... co ..... co 500n 15s::! 0 1--+---+-,.",,'-+--1---1 00-08 ~ ..... ..... ..... co ...... Co) ~ +7.5 I--l--l-+-+~/-T:.....-~ RAS Z tn Co) ~ V CAS ...... ..... co SI + 15.0 ....--,---r-T-,---....----, Ii! ..... ..... = 16 ns 1-63 Supply Voltage Ambient Temperature Min 4.50 Max 5.50 Units V 0 +70 'C II >< Q) ..... re ('I) ....... Electrical Characteristics VCC = 5.0V ±10%,O'C:;: TA:;: 70'C unless otherwise noted (Note 2) ~ ..... o::r Vc Input Clamp Voltage VCC ....... co IIH Input High Current for all Inputs VIN Q) ..... II RSI Output Load Current for RFIIO VIN N IlL Input Low Current for allinputs** VIN IIL2 ADS, RIC, CS, M2, RASIN VIN VIL Input Low Threshold VIH Input High Threshold VOL1 Output Low Voltage* ('I) VOL2 Output Low Voltage for RFI/O co ..... VOHl Output High Voltage' VOH2 Output High Voltage for RFIIO 110 Output High Drive Current* 100 Output Low Drive Current* en Icc Supply Current r-. ..... "Except RFIIO, ADS, RIC, CS, M2, RASIN co Switching Characteristics: DP8417, DP8418, DP8419, DP8419X C Vcc = 5.0V ± 10%, O'C :;: TA :;: 70'C unless otherwise noted (Notes 2, 4, 5), the output load capacitance is typical for 4 banks of 22 DRAMs each or 88 DRAMs, including trace capacitance. co ('I) ....... Q) ..... o::r co co ..... co ....... N ....... o::r co ....... r-. ..... re ('I) z ....... o::r a.. Symbol Parameter Conditions Min = Min, Ic = - 12mA = 2.5V = 0.5V, Output high = 0.5V = 0.5V Typ Max - O.B - 1.2 V 2.0 100 pA -0.7 -1.5 mA -0.02 -0.25 mA -0.05 -0.5 mA O.B V 2.0 = 20 mA IOL = BmA IOH = - 1 mA IOH = - 100 /LA VOUT = O.BV (Note 3) VOUT = 2.4V (Note 3) Vcc = Max IOL 2.4 Units V 0.3 0.5 0.3 0.5 V V V 3.5 2.4 3.5 V -50 - 200 mA 50 200 mA 150 240 mA 'Except RFI/O soon * These values are 00-08, CL = 500 pF; RASO-RAS3, CL = 150 pF; WE, CL = 500 pF; CAS, CL = 600 pF; RL = unless otherwise noted. See Figure 11a for test load. Sl is open unless otherwise noted. Maximum propagation delays are specified with all outputs switching. * * Preliminary Symbol Parameter *CL Condition '*AII CL = 50 pF Min Max Min Max Units ACCESS tRICLO RASIN to CAS Low Delay (RAHS = 0) Figure 6 DP8417, lB, 19-80 57 97 42 B5 ns tRICLO RASIN to CAS Low Delay (RAHS = 0) Figure 6 DP8417, lB, 19-70 57 87 42 75 ns tRICL1 RASIN to CAS Low Delay (RAHS = 1) Figure 6 DPB417, 18, 19-80 48 BO 35 68 ns tRICL1 RASIN to CAS Low Delay (RAHS = 1) Figure 6 DPB417, lB, 19-70 48 70 35 58 ns tRICH RASIN to CAS High Delay Figure 6 tRCOLO RAS to CAS Low Delay (RAHS = 0) Figure 6 DP8417, 18, 19-BO tRCOLO RAS to CAS Low Delay (RAHS = 0) tRCOL1 37 ns 43 BO ns Figure 6 DP8417, 18, 19-70 43 72 ns RAS to CAS Low Delay (RAHS = 1) Figure 6 DPB417, lB, 19-80 34 63 ns tRCOL1 RAS to CAS Low Delay (RAHS = 1) Figure 6 DP8417, 18, 19-70 34 55 ns tRCOH RAS to CAS High Delay Figure 6 tRAHO Row Address Hold Time (RAHS = 0, Mode 5) Figure 6 tRAHl Row Address Ho!d Time (RAHS = 1, Mode 5) Figure 6 tASC Column Address Set-up Time (Mode 5) Figure 6 22 1-64 ns 25 25 ns 15 15 ns 0 0 ns Switching Characteristics: DP8417, DP8418, DP8419, DP8419X c~ .......... QC) (Continued) VCC = 5.0V ± 10%, O'C S TA S 70'C unless otherwise noted (Notes 2, 4, 5). The output load capacitance is typical for 4 banks of 22 DRAMs each or 88 DRAMs, including trace capacitance. ..... ...... * These values are QO-Q8, CL = 500 pF; RASO-RASa, CL = 150 pF; WE, CL = 500 pF; CAS, CL = 600 pF; RL = soon unless otherwise noted. See Figure 11a for test load. S1 is open unless otherwise specified. Maximum propagation delays are specified with all outputs switching. (J) * * Preliminary Z Co) N QC) ...... ..... ...... .......... QC) Symbol Parameter *CL Condition Min **AII CL Max Min = 50 pF Units Max QC) ...... Co) ACCESS (Continued) N QC) ...... tRCVO RASIN to Column Address Valid (RAHS = 0, Mode 5) Figure 6 DP8417, 18, 19·80 94 ns QC) ...... QC) tRCVO RASIN to Column Address Valid (RAHS = 0, Mode 5) Figure 6 DP8417, 18, 19-70 85 ns tRCVI RASIN to Column Address Valid (RAHS = 1, Mode 5) Figure 6 DP8417, 18, 19-80 76 ns ...... (Q ...... Co) tRCVI RASIN to Column Address Valid (RAHS = 1, Mode 5) Figure 6 DP8417. 18, 19-70 68 tRPOL RASIN to RAS Low Delay Figures 5a, 5b. 6 21 18 ns tRPOH RASIN to RAS High Delay Figures 5a, 5b, 6 20 17 ns tASRL Address Set-up to RASIN low Figures 5a, 5b, 6 tAPO Address Input to Output Delay Figures 5a, 5b, 6 tspo Address Strobe High to Address Output Valid Figures 5a, 5b tASA Address Set-up Time to ADS Figures 5a, 5b, 6 5 ns tAHA Address Hold Time from ADS Figures 5a, 5b, 6 10 ns tAOS Address Strobe Pulse Width Figures 5a, 5b, 6 26 twpo WIN to WE Output Delay Figure5b tCPOL CASIN to CAS Low Delay (RIC low, Mode 4) Figure5b CASIN to CAS High Delay Figure5b tCPOH (RIC low, Mode 4) ...... ns 13 ns 25 ns ns ns 28 ns 17 33 ns 13 33 ns 13 ns 41 ns 45 ns Column Select to Column Address Valid Figure5a tRCR Row Select to Row Address Valid Figures 5a, 5b tRHA Row Address Held from Column Select Figure5a \cCAS RIC Low to CAS Low Delay (CASIN Low, Mode 4) Figure5a DP8417, 18, 19-80 50 ns t RIC Low to CAS Low Delay (CASIN Low, Mode 4) Figure5a DP8417, 18, 19-70 46 ns tOIFI Maximum (tRPOL - tRHA) See Mode 4 Description 7 ns tOlF2 Maximum (tRCC - tcpoLl 13 ns ns 7 REFRESH tRASINL,H Figure2a tRFPOLO RASIN to RAS Low Delay during Refresh (Mode 0) Figure2a 100 ns 50 ns 28 1-65 >< ...... Co) N ...... (Q >< 48 tRCC Figure2a .... ...... QC) 36 See Mode 4 Description Pulse Width of RASIN during Refresh (Q ...... QC) (Q tCPOL - \cPOH Refresh Cycle Period N QC) tCPdif tRC .... ns >< .... Switching Characteristics: DP8417, DP8418, DP8419, DP8419X ...... VCC = 5.0V ± 10%, O·C :;; T A :;; 70·C unless otherwise noted (Notes 2, 4, 5). The output load capacitance is typical for 4 banks of 22 DRAMs each or 88 DRAMs, including trace capacitance. Q) ~ ('I) >< ....'0:1' Q) co ...... Q) .... co '" 0; • These values are QO-Q8, CL = 500 pF; RASO-RASa, CL = 150 pF; WE, CL = 500 pF; CAS, CL = 600 pF; RL = 500n unless otherwise noted. See Figure 11a for test load. S1 is open unless otherwise specified. Maximum propagation delays are specified with all outputs switching . Symbol Parameter 'CL Condition Min ('I) ....'0:1' co ...... co co .... '" ....«;'0:1' z ...... '0:1' a.. C = 50 pF Units Max RASIN to RAS Low Delay during Hidden Refresh Figure? tRFPDHO RASIN to RAS High Delay during Refresh (Mode 0) Figure2a tRFPDH5 RASIN to RAS High Delay during Hidden Refresh Figure? tRFLCT RFSH Low to Counter Address Valid Figures 2a, 3 CS = X tRFLRL RFSH Low Set·up to RASIN Low (Mode 0), to get Minimum tASR = 0 Figure2a tRFHRL RFSH High Setup to Access RASIN Low Figure 3 tRFHRV RFSH High to Row Address Valid Figure 3 tROHNC RAS High to New Count Valid Figure2a tRST Counter Reset Pulse Width Figure2a tCTL RFI/O Low to Counter Outputs All Low Figure2a tRFCKL,H Minimum Pulse Width ofRFCK Figure? T Period of RAS Generator Clock Figure 3 tRGCKL Minimum Pulse Width Low ofRGCK Figure 3 tRGCKH Minimum Pulse Width High ofRGCK Figure 3 tFRQL RFCK Low to Forced RFRO (RFI/O) Low Figure 3 CL = 50 pF RL = 35k 66 ns RGCK Low to Forced RFRO High Figure 3 CL = 50pF RL = 35k 55 ns tRGRL RGCK Low to RAS Low Figure 3 20 41 ns tRGRH RGCK Low to RAS High Figure 3 20 48 ns ..... .... co Min tRFPDL5 co ...... P.I U) AIICL Max REFRESH (Continued) ('I) ....co..... (Continued) tFRQH 38 ns 35 ns 44 ns 38 ns 12 ns 25 ns 43 ns 42 ns 60 ns 100 1·66 ns 100 ns 30 ns 15 ns 15 ns Switching Characteristics: DP8417, DP8418, DP8419, DP8419X (Continued) Vee = 5.0V ± 10%, O"C ,,;: TA ,,;: 70"C unless otherwise noted (Notes 2, 4, 5). The output load capacitance is typical for 4 banks of 22 DRAMs each or BB DRAMs, including trace capacitance. • These values are 00-08, CL = 500 pF; RASO-RAS3, CL = 150 pF; WE, CL = 500 pF; CAS, CL = 600 pF; RL = 5000. unless otherwise noted. See Figure 118 for test load. S1 is open unless otherwise specified. Maximum propagation delays are specified with all outputs switching. Symbol Parameter ·CL Condition Min AIICL Max Min = 50pF Units Max REFRESH (Continued) tRQHRF RFSH Hold Time from RGCK Figure 3 tRFRH RFSH High to RAS High (Ending Forced Refresh early) (See Mode 1 Description) Fii=SH Low Set·up to (See Mode 1 Description) Figure 3 tRFSRG RGCK Low (Mode 1) tcSHR ~ High to RASiN Low for Hidden Refresh tRKRL RFCK High to RASIN low for hidden Refresh 2T ns 42 Figure 7 ns 12 ns 10 ns 50 ns 34 ns 5 ns 5 ns 5 ns 34 ns 34 ns DP8419, DP8419X ONLY tCSRL1 tCSRLO CS Low to Access RASIN Low (Using Mode 5 with Auto Refresh Mode) Figure 3 CS Low to Access RASIN (See Mode 5 Description) Low (Using Modes 4 or 5 with externally controlled Refresh) DP8418 ONLY tcSRL1 CS Low to Access RASIN Figure 3 Low (Using Mode 5 with Auto Refresh Mode) tcSRLO ~ Low to Access RASiN Low (Using Modes 4 or 5 with externally controlled Refresh) (See Mode 5 Description) DP8417 ONLY - PRELIMINARY tcSRL1 tcsRLO ~ Low to Access RASiliI Low (Using Mode 5 with Auto Refresh Mode) Figure 3 ~ Low to Access RASiliI Low (Using Modes 4 or 5 with externally controlled Refresh) (See Mode 5 Description) TRI·STATE (DP8417 ONLy) tZH ~ Low to Output High from Hi·Z 51 Open Flgure11b tHZ CS High to Output 51 Open, Q, WE Figure11b 50 ns S1 Open, RASO·3 0AS0·3 Figure11b 95 ns HI·Z from High tHZ es High to Output Hi·Z from High tZL CS Low to Output Low from Hi·Z tLZ CS High to Output Hi·Z from Low ns 50 51 Closed Figure11b ns 50 51 Closed Figure 11b 50 1·67 ns Input Capacitance TA = Symbol 25°C(Note2) Parameter Condition Min Typ Max Units Input Capacitance ADS, RIC, CS, M2, RASIN 8 pF Input Capacitance All Other Inputs 5 pF Note 1: "Absolute Maximum Rallngs" are lhe values beyond which the safety of the device cannot be guaranteed. They are not meant to Imply that the device should be operated at Ihesa nmlts. The table of "Electrical Characteristics" provides conditions for actual device operation. Note 2; All typical values are for TA = 25'C and Vcc= 5.0V. Note 3: This test Is provided as a mon~or of Driver output source and sink current capability. Csution should be exercised in testing this parameter. In testing these parameters, a 150 resistor should be placed In series with each output under test One output should be tested at a time and test time should not exceed 1 second. Note 4: Input pulse OV to a.ov, tR = iF = 2.5 ns, f= 2.5 MHz, Ipw = 200 ns. Input reference point on AC measurements Is 1.5V Output reference pOints are 2.4V for High and O.SV for Low. Note 5: The load capacltsnce on RF 1/0 should not exceed 50 pF. 1-68 ~National ~ Semiconductor DP8428/NS32828,DP8429/NS32829 1 Megabit High Speed Dynamic RAM ControllerIDrivers General Description Features The DP8428 and DP84291M DRAM Controller/Drivers are designed to provide "No-Waitstate" CPU interface to Dynamic RAM arrays of up to 8 Mbytes and larger. The DP8428 and DP8429 are tailored for 32-bit and 16-bit system requirements, respectively. Both devices are fabricated using National's new oxide isolated Advanced Low power Schottky (ALS) process and use design techniques which enable them to significantly out-perform all other LSI or discrete alternatives in speed, level of integration, and power consumption. Each device integrates the following critical 1M DRAM controller functions on a single monolithic device: ultra precise delay line; 9 bit refresh counter; fall-through row, column, and bank select input latches; Row/Column address muxing logic; on-board high capacitive-load RAS, CAS, Write Enable and Address output drivers; and, preCise control signal timing for all the above. In order to specify each device for "true" worst case operating conditions, all timing parameters are guaranteed while the chip is driving the capacitive load of 88 DRAMs including trace capacitance. The chip's delay timing logic makes use of a patented new delay line technique which keeps AC skew to ±3 ns over the full Vee range of ±10% and temperature range of - 55°C to + 125°C. The DP8428 and DP8429 guarantee a maximum RASIN to CASOUT delay of 80 ns or 70 ns even while driving an 8 Mbyte memory array with error correction check bits included. Two speed selected options of these devices are shown in the switching characteristics section of this document. (Continued) • Makes DRAM interface and refresh tasks appear virtually transparent to the CPU making DRAMs as easy to use as static RAMs • Specifically designed to eliminate CPU wait states up to 10 MHz or beyond • Eliminates 20 discrete components for significant board real estate reduction, system power savings and the elimination of chip-to-chip AC skewing • On-board ultra precise delay line • On-board high capacitive RAS, CAS, WE and Address drivers (specified driving 88 DRAMs directly) • AC specified for directly addressing up to 8 Mbytes • Low power/high speed bipolar oxide isolated process • Downward pin and function compatible with 256k DRAM Controller/Drivers DP8409A, DP8417, DP8418, and DP8419 Contents • • • • • System and Device Block Diagrams Recommended Companion Components Device Connection Diagrams and Pin Definitions Device Differences-DP8428 vs DP8429 Mode of Operation (Descriptions and Timing Diagrams) • Application Description and Diagrams • DC/ AC Electrical Specifications, Timing Diagrams and Test Conditions System Diagram CPU 32-BIT 16-BIT 8-BIT I 'I :1 DP84300 PROGRAMMABLE REFRESH TIMER ~ ADDRESS BUS tI DP842B OR DP8429 1 MEGABIT DRAM OONTROLLER/ DRIVERS MULTIPLEXED ADDRESS BUS . \ 00-9(500 pF DRIVERS) ,/ y iiAS 0-3 (150 pF DRIVERS) ~ y ~ (600 pF DRIVER) y r" ..-- INTERRUPT ! ~ A WAIT/DTACK ~ ."- y I READ/WRITE I ENABLE DP84XX2 CPU SPECIFIC REFRESH/ACCESS ARBITRATION ERROR CORRECOON TRANS- CEIVERS WE (SOD pF DRIVER) -" l,-L ['r 4 BANKS OF 1 MEGABIT DYNAMIC RAMS UPTO 8 MEGABYTES PLUS ERROR OORRECTION, CHECK BITS .. r---v I DATA IN MEMORY DATA BUS - . A DP8428129 OONlROl. " DP84OO-21B402A CONTROL " y LtcA~ 7' DP8400-2 OR DPB40ZA 16 BIT OR 32 BIT ERROR DETECTION AND OORRECTION ENABLE BUFFERS Ar-" . l~< ~ DATA OUT CHECK BITS IN r CHECK BITS OUT TL/F/8649-1 1-69 General Description (Continued) With its four independent RAS outputs and ten multiplexed address outputs, the DP8429 can support up to four banks of 64k, 256k or 1M DRAMs. Two bank select pins, B1 and 80, are decoded to activate one of the RAS signals during an access, leaving the three non-selected banks in the standby mode (less than one tenth of the operating power) with data outputs in TRI-STATE". The DP8428's one Bank Select pin, B1, enables 2 banks automatically during an access in order to provide an optimum interface for 32-bit microprocessors. The DP8428 and DP8429 each have two mode-select pins, allowing for two refresh modes and two access modes. Refresh and access timing may be controlled either externally or automatically. The automatic modes require a minimum of input control signals. A refresh counter is on-chip and is multiplexed with the row and column inputs. Its contents appear at the address outputs of the DP8428 or DP8429 during any refresh, and are incremented at the completion of the refresh. Row, Column and bank address latches are also on-chip. However, if the address inputs to the DP8428 or DP8429 are valid throughout the duration of the access, these latches may be operated in the fall-through mode. Each device is available in either the 52 pin Ceramic DIP, or the low cost JEDEC standard 68 pin Plastic Chip Carrier (PCC) package. Functional Block Diagrams DP8429 RO·9 -+ \ ADS _ ...._ _ CO·9 y~ -~_ _-.t/i HIGH CAPACITIVE DRIVE CAPABILITY OUTPUTS i"' ...-tlD--. r--........ I QO·8 I I ' I I I I I liD a 1---t:>--1iD2 Bl_ BO_ r---,.,--- fI_ RmIl_ liD 0 r---,.,---D! CONTROL LOGIC R/f(RFCKI_ cmIf(RGCKI _ ~~--~--~~--r-~ wm-----~~--+_--~---T-------L~RF 1/0 M2 (limil RAHS 1-70 MO TL/F/8849-2 Functional Block Diagrams (Continued) DP8428 RO·9 \ HIGH CAPACITIVE DRIVE CAPABILITY OUTPUTS y~ I---~/iI i"'I--+l~-. I I 00·9 ' I I I I I iiAS DECODER - , .....-_RASO RASIN fI_ ifAJlII_ 1---1>--.00 CONTROL LOGIC Rif(RFCK)_ rnlII (RGCK) _ WiN l RF 110 t t t M2 (iimf) RAHS MO TLlF/8649-3 System Companion Components Device # Function DP84300 DP84412 DP84512 DP84322 DP84422 DP84522 DP84432 DP84532 Programmable Refresh Timer for DP84xx DRAM Controller NS32008/16/32 to DP8409A117/18/19/28/29 Interface NS32332 to DP8417/18/19/28/29 Interface 68000/08110 to DP8409A117118/19/28/29 Interface (up to 8 MHz) 68000/08/10 to DP8409A117/18/19/28/29 Interface (up to 12.5 MHz) 68020 to DP8417/18/19/28/29 Interface 8086/881186/188 to DP8409A/17/18/19/28/29 Interface 80286 to DP8409A/17/18/19/28/29 Interface DP8400·2 16·61t Expandable Error Checker/Corrector (E2C2) DP8402A 32·6it Error Detector And Corrector (EDAC) 1·71 Connection Diagrams Dual-In-Llne Package Dual-In-Line Package RiC (RFCK) miN (RGCK) RIC (RFCK) 52 iiASiN CASIN (RGCK) 51 CS MO RAHS 4 RAHS M2 (n) 5 M2 (n) 50 Rf I/O 49 WiN MO ADS 4 48Wf 47 QO ADS RO RO CO co 46 Q9 45 01 Rl ClIO Rl ClIO 4402 43 03 R2'1 12 R2" C2 12 GND 13 42 Q4 C2 GND R3 C3 13 14 15 DP8428 41 GND DP8429 R3 14 C3 15 40 GND 39 OS R4 '6 C4 '7 R5 18 C5 19 R4 16 C4 '7 38 VCC 37 06 36 07 R5 '8 C5 19 35 08 34 R9 20 C9 21 R9 20 C9 21 33 R6 22 R6 22 C6 23 R724 C6 23 R724 C7 25 C7 25 R8 26 m RAS3 32 RAS2 31 RASl 3ORASO 29 eo 28 81 27 C8 R8 26 TL/F 18649-4 TL/F/8649-5 Order Number DP8428D-70, DP8428D-80 or DP8429D-70, DP8429D-80 See NS Package Number D52A Plastic Chip Carrier Package Plastic Chip Carrier Package 9 8 7 6 5 4 3 2 1 6867666564636261 10 60 ADS 11 59 RO 12 58 co 13 57 Rl 14 56 Cl 15 55 R2 16 54 G~~ : ~ GND R3 C3 R4 C4 R5 C5 R9 19 20 21 22 23 24 25 26 DP8428 ;; 51 50 49 48 47 46 45 44 98765432168~6868~~~~ ADS RO CO Rl Cl R2 C2 GND GND R3 C3 R4 C4 R5 C5 R9 09 01 02 03 04 GND GND 05 Vee Vee 06 07 08 CAS RAS3 VU~3031~~343538D383840M~43 eo 10 11 12 13 14 15 16 :~ 19 W 21 U ~ ~ ~ U DP8~9 59 09 ~ 01 ~ 02 56 Q3 55 04 ~ GND GND 05 51 Vee ~ Vee 48 06 48 07 Q 08 ;i 48 CAS ~ RAS3 44 27 2829 303132~34 353637 383940 414243 TUF/8649-6 TUF/8649-7 Order Number DP8428V-70, DP8428V-80 or DP8429V-70, DP8429V-80 See NS Package Number V68A 1-72 RO-R9: Row Address Inputs. CO-C9: Column Address Inputs. QO-Q9: Multiplexed Address Outputs - This address is selected from the Row Address Input Latch, the Column Address Input Latch or the Refresh Counter. DP8428 vs DP8429 The DP8428 DYNAMIC RAM CONTROLLER/DRIVER is identical to the DP8429 with the exception of two functional differences incorporated to improve performance with 32-bit microprocessors. RASIN: Row Address Strobe Input - RASIN directly controls the selected RAS output when in an access mode and all RAS outputs during hidden or external refresh. Ric (RFCK) - In the auto-modes this pin is the external refresh clock input; one refresh cycle should be performed each clock period. In the external access mode it is Row/ Column Select Input which enables either the row or column address input latch onto the output bus. 1) Pin 28 (B1) is used to enable/disable a pair of RAS outputs, and pin 29 (BO on the DP8429) is a no connect. When B1 is low, RASO and RAS1 are enabled sLlch that they both go low during an access. When B1 is high, RAS2 and RAS3 are enabled. This feature is useful when driving words of 32 bits or more since each RAS would be driving only one half of the word. By distributing the load on each RAS line in this way, the DP8428 will meet the same AC specifications driving 2 banks of 32 DRAMs each as the DP8429 does driving 4 banks of 16 bits each. CASIN (RGCK) - In the auto-modes this pin is the RAS Generator Clock input. In external access mode it is the Column Address Strobe input which controls CAS directly once columns are enabled on the address outputs. ADS: Address (Latch) Strobe Input - Row Address, Column Address, and Bank Select Latches are fall-through with ADS high; latching occurs on high-to-Iow transition of ADS. CS: Chip Select Input - When high, CS disables all accesses. Refreshing, however, in both modes 0 and 1 is not affected by this pin. MO, M2 (RFSH): Mode Control Inputs - These pins select one of the four available operational modes of the DP8429 (see Table III). RFI/O: Refresh Input/Output - In the auto-modes this pin is the Refresh Request Output. It goes low following RFCK indicating that no hidden refresh was performed while RFCK was high. When this pin is set low by an external gate the on-chip refresh counter is reset to all zeroes. WIN: Write Enable Input. WE: Write Enable Output - WE follows WIN unconditionally. 2) The hidden refresh function available on the DP8429 has been disabled on the DP8428 in order to reduce the amount of setup time necessary from CS going low to RASIN going low during an access of DRAM. This parameter, called tesRL1, is 5 ns for the DP8428 whereas it is 34 ns for the DP8429. The hidden refresh function allowed only a very small increase in system performance, at microprocessor frequencies of 10 MHz and above. Pin Definitions Vee, GND, GND - Vee = 5V ± 10%. The three supply pins have been assigned to the center of the package to reduce voltage drops, both DC and AC. There are two ground pins to reduce the low level noise. The second ground pin is located two pins from Vee, so that decoupling capacitors can be inserted directly next to these pins. It is important to adequately decouple this device, due to the high switching currents that will occur when all 10 address bits change in the same direction simultaneously. A recommended solution would be a 1 ",F multilayer ceramic capacitor in parallel with a low-voltage tantalum capacitor, both connected as close as possible to GND and Vee to reduce lead inductance. See Figure below. VCC RAHS: Row Address Hold Time Select - Selects the tRAH to be guaranteed by the DP8428 or DP8429 delay line to allow for the use of fast or slow DRAMs. CAS: Column Address Strobe Output - In mode 5 and in mode 4 with CASIN low before R/C goes low, CAS goes low automatically after the column address is valid on the address outputs. In mode 4 CAS follows CASIN directly after RIC goes low, allowing for nibble accessing. CAS is always high during refresh. O------I ...----....,J.I T "MULTILAYER CERAMIC "TANTALUM GND 0 RAS 0-3: Row Address Strobe Outputs - The enabled RAS output (see Table II) follows RASIN directly during an access. During refresh, all RAS outputs are enabled. TL/F/8649-8 *Capacitor values should be chosen depending on the particular application. 1-73 C "tJ co ~ I\) co C "tJ CO ~ I\) CD z en Co) I\) CO I\) CO z en Co) I\) CO I\) CD the DP8429. The damping resistor values may differ depending on how heavily an output is loaded. These resistors should be determined by the first prototypes (not wirewrapped due to the larger distributed capacitance and inductance). Resistors should be chosen such that the transition on the control outputs is critically damped. Typical values will be from 150 to 1000, with the lower values being used with the larger memory arrays. Note that AC parameters are specified with 150 damping resistors. For more information see AN-305 "Precautions to Take When Driving Memories". Pin Definitions (Continued) BO, B1: Bank Select Inputs - These pins are decoded to enable one or two of the four ~ outputs during an access (see Table I and Table II). TABLE I. DP8429 Memory Bank Decode Bank Select (Strobed by ADS) B1 BO 0 0 1 1 0 1 0 1 Enabled RASn RASo RAS1 ~2 DP8429 DRIVING ANY 256k or 1M DRAMS The DP8429 can drive any 256k or 1M DRAMs. 256k DRAMs require 18 of the DP8429's address inputs to select one memory location within the DRAM. "FiJlS.only refreshing with the nine-bit refresh-counter on the DP8429 makes CAS before RAS refreshing, available on 256k DRAMs, unnecessary (see Figure 1a). 1 Mbit DRAMs require the use of all 10 of the DP8429 Address Outputs (see Figure 1b). ~a TABLE II. DP8428 Memory Bank Decode Bank Select (Strobed by ADS) B1 NC 0 1 X X Enabled RASn RASo&RAS1 RAS2&RASa READ, WRITE AND READ-MODIFY-WRITE CYCLES The output signal, WE, determines what type of memory access cycle the memory will perform. If WE is kept high while CAS goes low, a read cycle occurs. If WE goes low before CAS goes low, a write cycle occurs and data at DI (DRAM input data) is written into the DRAM as CAS goes low. If WE goes low later than tewD after CAS goes low, first a read occurs and DO (DRAM output data) becomes valid, then data DI is written into the same address in the DRAM as WE goes low. In this read-modify-write case, DI and DO cannot be linked together. WE always follows WIN directly to determine the type of access to be performed. Conditions for All Modes INPUT ADDRESSING The address block consists of a row-address latch, a column-address latch, and a resettable refresh counter. The address latches are fall-through when ADS is high and latch when ADS goes low. If the address bus contains valid addresses until after CAS goes low at the end of the memory cycle, ADS can be permanently high. Otherwise ADS must go low while the addresses are still valid. POWER-UP INITIALIZE When Vee is first applied to the DP8429, an initialize pulse clears the refresh counter and the internal control flip-flops. DRIVE CAPABILITY The DP8429 has timing parameters that are specified driving the typical capacitance (including traces) of 88, 5V-only DRAMs. Since there are 4 ~ outputs, each is specified driving one-fourth of the total memory. CAS, WE and the address outputs are specified driving all 88 DRAMs. Mode Features Summary • 4 modes of operation: 2 access and 2 refresh • Automatic or external selected by the user • Auto access mode provides RAS, row to column change, and then CAS automatically. • Choice between two different values of tRAH in auto-access mode • CAS controlled independently in external control mode, allowing for nibble mode accessing • AutomatiC refreshing can make refreshes transparent to the system • CAS is inhibited during refresh cycles The graph in Figure 10 may be used to determine the slight variations in timing parameters, due to loading conditions other than 88 DRAMs. Because of distributed trace capacitance and inductance and DRAM input capacitance, current spikes can be created, causing overshoots and undershoots at the DRAM inputs that can change the contEints of the DRAMs or even destroy them. To reduce these spikes, a damping resistor (low inductance, carbon) should be inserted between the DP8429 outputs and the DRAMs, as close as possible to 1-74 C "U DP8428/DP8429 Mode Descriptions 00 ~ In order that the refresh address is valid on the address outputs prior to the RAS lines going low, RFSH must go low before RASIN. The setup time required is given by tRFLRL in the Switching Characteristics. This parameter may be adjusted using Figure 10 for loading conditions other than those specified. MODE O-EXTERNALLY CONTROLLED REFRESH Figure 2 shows the Externally Controlled Refresh timing. In this mode the refresh counter contents are multiplexed to the address outputs. All RAS outputs are enabled to follow RASIN so that the row address indicated by the refresh counter is refreshed in all DRAM banks when RASIN goes low. The refresh counter increments when RASIN goes high. RFSH should be held low at least until RASIN goes high (they may go high simultaneously) so that the refresh address remains valid and all RAS outputs remain enabled throughout the refresh. A burst refresh may be performed by holding RFSH low and toggling RASIN until all rows are refreshed. It may be useful in this case to reset the refresh counter just prior to beginning the refresh. The refresh counter resets to all zeroes when RFI/O is pulled low by an external gate. The refresh counter always counts to 511 before rolling over to zero. If there are 12B or 256 rows being refreshed then 07 or OB, respectively, going high may be used as an end-of-burst indicator. TABLE III. DP8428/DP8429 Mode Select Options Mode (RFSH) M2 MO Mode of Operation 0 0 0 Externally Controlled Refresh Auto Refresh-Forced Externally Controlled Access Auto Access (Hidden Refresh) 1 0 1 4 1 0 5 1 1 CAS ~~ '"",,: WE I,,,"'", r REFRESH COUNTER 9 9 l ~ COLUMN OECODE 512 R DRIVERS 0 9 ADDRESS BUS W D E C 9 512 - 256K ARRAY +5V 256K DYNAMIC RAMS 0 D E DPB429 TL/F/8649-12 All 9 Bits of Refresh Counter Used 1a. DP8428/DP8429 with 256k DRAMs FIGURE m I I ~ ROWS ~ WE 1m 10 COLUMNS REFRESH COUNTER ~~ ADDRESS DRIVERS 10 00 ....... C "U 00 ~ N CD ....... Z en Co) DP8428/DP8429 Interface Between System and DRAM Banks ROWS N ... ADDRESS ... BUS 10 ... ... '" R 0 W 0 E 512 C 0 D E ~ DP8429 l COLUMN DECODE 2048 11.1- BIT ARRAY .. +5V 1M DRAMS TL/F/8649-25 All 9 Bi1s of Refresh Counler Used FIGURE 1b. DP8428/DP8429 with 1M DRAMs 1-75 N 00 N 00 ....... Z en Co) N 00 N CD DP8428/DP8429 Mode Descriptions (Continued) INPUTS HASIN cmJj AND RII: OUTPUTS RAS 0 RAS 1,2,3 REFRESH CTR COUNTER RESET 00-9 REFRESH COUNT" tRFlCT RFIIO COUNTER RESET INPUT TUFf8649-13 'Indicates Dynamic RAM Parameters FIGURE 2a. External Control Refresh Cycle (Mode 0) MODE 1II T ® RFRO goes low if no hidden refresh (> tRP) occurred while RFCK was high ® Forced refresh RAS ends RFRO ® Next RASIN starts next access @) (i) j.t-P removes refresh acknowledge I-LP acknowledges refresh request FIGURE 3. DP8428/DP8429 Performing a Forced Refresh (Mode 5 ---+ 1 ---+ 5) with Various Microprocessors 1-77 I z I i Q DP8428/DP8429 Mode Descriptions (Continued) while the RAS lines are low, then the RASs go high tRFRH later. The designer must be careful, however, not to violate the minimum ~ low time of the DRAMs. He must also guarantee that the minimum RAS precharge time is not violated during a transition from mode 1 to mode 5 when an access is desired immediately following a refresh. If the processor tries to access memory whil~ the DP8429 is in mode 1, WAIT states should be Inserted Into the processor cycles until the DP8429 is ~ack in mode. 5 and the desired access has been accomplished (see Figure 9). Instead of using WAIT states to delay accesses when refreshing, HOLD states could be used as follows. RFRO could be connected to a HOLD or Bus Request input to the system. When convenient, the system acknowled~es th.e HOLD or Bus Request by pulling M2 low. USing this scheme, HOLD will end as the RAS lines go low (RFIIO goes high). Thus, there must be sufficien.t delay from the time HOLD goes high to the DP8429 returning to mode 5, so that the RAS low time of the DRAMs isn't violated as described earlier (see Figure 3 for mode 1 refresh with Hold states). To perform a forced refresh the system will be inactive for about four periods of RGCK. For a frequency of 10 MHz, this is 400 ns. To refresh 128 rows every 2 ms an average of *Resistors required about one refresh per 16. fJ-s is required. With a RFCK period of 16 fJ-s and RGCK period of 1~o ns, DR~M acces~es are delayed due to refr~sh O~ly 2.5 Yo of the tl~e. If ~slng the Hidden Refresh available In mode 5 (refreshing with RFCK high) this percentage will be even lower. MODE 4 _EXTERNALLY CONTROLLED ACCESS In this mode all control signal outputs can be controlled directly by the corresponding control Input. The enabled RAS output follows RASIN, eAS follows CASiN (with RIC low), WE follows WIN and RIC determines whether the row or the column inputs are enabled to the address outputs (see Figure 4). With RIC high, the row address latch contents are enabled onto the address bus. RAS gOing low strobes the row address into the DRAMs. After waiting to allow for sufficient row-address hold time (tRAH) after RAS goes low, RIC can go low to enable the column address latch contents onto the address bus. When the column address is valid, CAS going low will strobe it into the DRAMs. WIN determines whether the cycle is a read, write or read-modify-write access. Refer to Figures 5a and 5b for typical Read and Write timing using mode 4. Page or Nibble mode may be performed by toggling CASIN once the initial access has been completed. In the case of page mode the column address must be changed before depends on DRAM load. DRAMs Maybe 16k, 64k, 256k, 1 M For 4 Banks, can drive 16 data bits + 6 Gheck Bits for EGG. For 2 Banks, can drive .32 data bits + 7 Gheck Bits for EGG. For 1 Bank, can drive 64 data bits + 8 Gheck Bits for EGG. 18«s. B4Ks. 268K•• 1M. TL/F/8649-16 FIGURE 4. Typical Application of DP8429 Using External Control Access and Refresh in Modes 0 and 4 1-78 C DP8428/DP8429 Mode Descriptions -a co (Continued) -'" I\) INPUTS co ..... "INDICATES DYNAMIC RAM PARAMETERS ADS (ALE) C -a co -'" I\) co ..... z en Co) IASRL I\) -I I I 1 1 co I\) co ..... I z en Co) I Ric I OUTPUTS ill 0,1,2,3 I_IRPDL -tISPD- ·1 I ~l 1-IRcc·l IRHA~! J -tAPD- tAsR·I-tRAHr---1 ~~~::::~;%:::: ;~ QO-g ~ RDWS VALID co co I\) I ~I tRCRI_ ROWS COLUMNS VALID ~,tASC"I-tcAC·--1 I I I\) - teeAS -I tRAC·---~ DRAM DATA OUT \. DATA OUT VALID TL/F/8649-17 FIGURE Sa. Read Cycle Timing (Mode 4) INPUTS "INDICATES DYNAMIC RAM PARAMETERS ADS (ALEI SYSTEM ADDRESS BUS RiC DRAM DATA IN ---+--;----;------.:-----(1 OUTPUTS ill D,1,2,3 OO-g' ====~ TL/F/8649-18 FIGURE 5b. Write Cycle Timing (Mode 4) 1-79 m .--------------------------------------------------------------------------r N 00 N C') DP8428/DP8429 Mode Descriptions (Continued) re CASIN goes low to access a new memory location (see Figure 5c). Parameter tCPdif has been specified in order that users may easily determine minimum CAS pulse widths when CASIN is toggling. C') AUTOMATIC CAS GENERATION U) Z ...... 00 N U) Z ...... m N '0:1' ~ C re '0:1' ~ C With tOIFt (from Switching Characteristics) = 7 ns, RASIN to RIC delay = 7 ns + 15 ns = 22 ns. A delay line of 25 ns will be sufficient. With Auto-CAS generation, the maximum delay from RIC to CAS (loaded with 600 pF) is 46 ns. Thus the maximum RASIN to CAS time is 71 ns, under the given conditions. CAS is held high when RIC is high even if CASIN is low. If CASIN is low when RIC goes low, CAS goes low automatically, tASC after the column address is valid. This feature eliminates the need for an externally derived CASIN Signal to control CAS when performing a simple access (Figure 5a demonstrates Auto-CAS generation in mode 4). Page or nibble accessing may be performed as shown in Figure 5c even if CAS is generated automatically for the initial access. With a maximum RASIN to RAS time (tRPoLl of 20 ns, the maximum RAS to CAS time is about 51 ns. Most DRAMs with a 15 ns minimum tRAH have a maximum tRCO of about 60 ns. Thus memory accesses are likely to be RAS limited instead of CAS limited. In other words, memory access time is limited by DRAM performance, not controller performance. FASTEST MEMORY ACCESS REFRESHING IN CONJUNCTION WITH MODE 4 The fastest Mode 4 access is achieved by using the automatic CAS feature and external delay line to generate the required delay between RASIN and RIC. The amount of delay required depends on the minimum tRAH of the DRAMs being used. The DPB429 parameter tOlFt has been specified in order that the delay between RASIN and RIC may be minimized. If using mode 4 to access memory, mode 0 (externally controlled refresh) must be used for all refreshing. MODE 5 - AUTOMATIC ACCESS WITH HIDDEN REFRESHING CAPABILITY Automatic-Access has two advantages over the externally controlled access (mode 4). First, RAS, CAS and the row to column change are all derived internally from one input signal, RASIN. Thus the need for an external delay line (see mode 4) is eliminated. Secondly, since RIC and CASIN are not needed to generate the row to column change and CAS, these pins can be used for the automatic refreshing function. tOIFt = MAXIMUM (tRPOL - tRHA) where tRPOL = RASIN to RAS delay and tRHA = row address held from RIC going low. The delay between RASIN and RIC that guarantees the specified DRAM tRAH is given by MINIMUM RASIN to RIC = tOIFt + tRAH. AUTOMATIC ACCESS CONTROL Example Mode 5 of the DPB429 makes accessing Dynamic RAM nearly as easy as accessing static RAM. Once row and column addresses are valid (latched on the DPB429 if necessary), RASIN going low is all that is required to perform the memory access. In an application using DRAMs that require a minimum tRAH of 15 ns, the following demonstrates how the maximum RASIN to CAS time is determined. RiC ADS 4-----4-----------~ co·g QO·9 TL/F/8649-19 FIGURE 5c. Page or Nibble Access in Mode 4 1-BO c " DP8428/DP8429 Mode Descriptions (Continued) 00 -" 01:1N 00 i-1ADS-i ~_ _ _ _ _ __ C ADSJI 00 01:1N co 1----1..'., -t----<-I.--IRICL---~I Z en Co) N 00 N ADDRESS INPUTS/ DATA 00 Z en Co) N 00 N co QD-9~~ I--I[IS"---, ~--~~ - - W A I T E - i~--Iwcs·-~ ---- teAC· i DATA D U T P U T - - - - - - - - - - - t - - - - - - - - - - - - < ; -----IRAC·----~I *Indicates Dynamic RAM Parameters TLlF/8649-20 FIGURE 6. Mode 5 Timing (Refer to Figure 6) In mode 5 the selected RAS follows RASIN immediately, as in mode 4, to strobe the row address into the DRAMs. The row address remains valid on the DP8429 address outputs long enough to meet the tRAH requirement of the DRAMs (pin 4, RAHS, of the DP8429 allows the user two choices of tRAH). Next, the column address replaces the row address on the address outputs and CAS goes low to strobe the columns into the DRAMs. WIN determines whether a read, write or read-modify-write is done. The diagram below illustrates mode 5 automatic control signal generation. (b) by a combination of mode 5 (hidden refresh) and mode 1 (auto-refresh) (c) by a combination of mode 5 and mode 0 or (a) Externally Controlled Refreshing in Mode 0 or Mode 1 All refreshing may be accomplished using external refreshes in either mode 0 or mode 1 with RIC (RFCK) tied high (see mode 0 and mode 1 descriptions). If this is desired, the system determines when a refresh will be performed, puts the DP8429 in the appropriate mode, and controls the RAS signals directly with RASI N. The on-chip refresh counter is enabled to the address outputs of the DP8429 when the refresh mode is entered, and increments when RASIN goes high at the completion of the refresh. (b) Mode 5 Refreshing (hidden) with Mode 1 refreshing (auto) (Refer to Figure 7a) If RFCK is tied to a clock (see mode 1 description), RFI/O becomes a refresh request output and goes low following RFCK going low if no refresh occurred while RFCK was high. Refreshes may be performed in mode 5 when the DP8429 is not selected for access (CS is high) and RFCK is high. If these conditions exist the refresh counter contents appear on the DP8429 address outputs and all RAS lines follow RASIN so that if RASIN goes low (an access other than through the DP8429 occurs), all RAS lines go low to perform the refresh. The DP8429 allows only one refresh of this type for each period of RFCK, since RFCK should be fast enough such that one refresh per period is sufficient to meet the DRAM refresh requirement. TLiF/8649-21 REFRESHING IN CONJUNCTION WITH MODE 5 When using mode 5 to perform memory accesses, refreshing may be accomplished: (a) externally (in mode 0 or mode 1) 1-81 en C'I CO C'I DP8428/DP8429 Mode Descriptions (Continued) en z...... Once it is started, a hidden refresh will continue even if RFCK goes low. However, CS must be high throughout the refresh (until RASIN goes high). ('I) CO C'I CO C'I ('I) en z .. .. ~ f c ...... CO C'I CO Il. C System Characteristics: 1) DRAM used has min tRAH requirement of 15 ns and min tASR of 0 ns 2) DRAM address is valid from time Tv to the end of the memory cycle 3) four banks of twenty-two 256k memory chips each are being driven These hidden refreshes are valuable in that they do not delay accesses. When determining the duty cycle of RFCK, the high time should be maximized in order to maximize the probability of hidden refreshes. If a hidden refresh doesn't happen, then a refresh request will occur on RFI/O when RFCK goes low. After receiving the request, the system must perform a refresh while RFCK is low. This may be done by gOing to mode 1 and allowing an automatic refresh (see mode 1 description). This refresh must be completed while RFCK is low, thus the RFCK low time is determined by the worst-case time required by the system to respond to a refresh request. (c) Using the DP8429 (see Figure 7b): 1) Tie pin 4 (RAHS) high to guarantee a 15 ns minimum tRAH which is sufficient for the DRAMs being used 2) Generate RASI N no earlier than time Tv + tASRL (see switching characteristics), so that the row address is valid on the DRAM address inputs before RAS occurs 3) Tie ADS high since latching the DRAM address on the DP8429 is not necessary 4) Connect the first 20 system address bits to RO-R9 and CO-C9, and bits 21 and 22 to BO and B1 5) Connect each RAS output of the DP8429 to the RAS inputs of the DRAMs of one bank of the memory array; connect QO-Q9 of the DP8429 to AO-A9 of all DRAMs; connect CAS of the DP8429 to CAS of all the DRAMs Figure 7c illustrates a similar example using the DP8428 to drive two 32-bit banks. Mode 5 Refresh (Hidden Refresh) with mode 0 Refresh (External Refresh) This refresh scheme is identical to that in (b) except that after receiving a refresh request, mode 0 is entered to do the refresh (see mode 0 description). The refresh request is terminated (RFI/O goes high) as soon as mode 0 is entered. This method requires more control than using mode 1 (auto-refresh), however, it may be desirable if the mode 1 refresh time is considered to be excessive. Example Figure 7b demonstrates how a system designer would use the DP8429 in mode 5 based on certain characteristics of his system. i------tRFCKL ·1:::::::::::::::::::::::::::::=-tR-FC-K-HI=-_tR_F_CK~====~·I----·I I i FORCES REFRES~ r- I~~ N2<~~~~~D HIDDEN REFRESH ALLOWED r - - - - - - r - - PROCESSOR ACCESSING ELSEWHERE cs ~~+---------~~-------- ~ RFRO (RFI/D) HIDDEN REFRESH ALREADY PERFORMEO, NO SUBSEQUENT REFRESH ALLOWED IN THIS CYCLE RAS 0-3 ---.1 00·9 ~_ _ RO_W_S_ _ 2Tns ROWS u FIGURE 7a_ Hidden Refreshing (Mode 5) and Forced Refreshing (Mode 1) Timing 1-82 TL/F/B649-22 C "0 CD DP8428/DP8429 Mode Descriptions (Continued) ~ N ~ c I z ~ ~z en Co) N CD N CQ SYSTEM CLOCK ~----+I RGCK I I AI).21 "l"_:~S AG·9 r .......O'~,.,.,.,~1 CO·9 OP8429 81 INPUT RAS REFRESHCLDCK r - - - - - + I RASIN IRFCK r - I- - - - -• • WRiTE r------+I WIR REFRESH 1M2 r - I- - - - -• • '----;,;..;;;;;.,;.;;.;~....J csl-I----_ OATA~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ TLlF/8649-23 FIGURE 7b. Typical Application of DP8429 Using Modes 5 and 1 Applications larly, one should not attempt to start an access while a refresh is in progress. The parameter tRFHRl specifies the minimum time from RFSH high to RASIN gOing low to initiate an access. 2) One should always guarantee that the DP8429 is enabled for access prior to initiating the access (see tesRll). 3) One should bring RASIN low even during non·local access cycles when in mode 5 in order to maximize the chance of a hidden refresh occurring. If one desires a memory interface containing the DP8429 that minimizes the number of external components required, modes 5 and 1 should be used. These two modes provide: 1) Automatic access to memory (in mode 5 only one signal, RASIN, is required in order to access memory) 2) Hidden refresh capability (refreshes are performed automatically while in mode 5 when non-local accesses are taking place, as determined by CS) 3) Refresh request capability (if no hidden refresh took place while RFCK was high, a refresh request is generated at the RFI/O pin when RFCK goes high) 4) Automatic forced refresh (If a refresh request is generated while in mode 5, as described above, external logic should switch the DP8429 into mode 1 to do an automatic forced refresh. No other external control signals need be issued. WAIT states can be inserted into the processor machine cycles if the system tries to access memory while the DP8429 is in mode 1 doing a forced refresh). 4) At lower frequencies (under 10 Mhz), it becomes increasingly important to differentiate between READ and WRITE cycles. RASIN generation during READ cycles can take place as soon as one knows that a processor READ access cycle has started. WRITE cycles, on the other hand, cannot start until one knows that the data to be written at the DRAM inputs will be valid a setup time before CAS (column address strobe) goes true at the DRAM inputs. Therefore, in general, READ cycles can be initiated earlier than WRITE cycles. 5) Many times it is possible to only add WAIT states during READ cycles and have no WAIT states during WRITE cycles. This is because it generally takes less time to write data into memory than to read data from memory. Some items to be considered when integrating the DP8429 into a system design are: 1) The system designer should ensure that a DRAM access not be in progress when a refresh mode is entered. Simi- 1-83 Applications (Continued) , SYSTEM CLOCK I I RAS2 " 1 " _ ADS RAS1 I I AO-2Q INPUTRAS REFRESH CLOCK WififE REFRESH ~ l~ I ~ I BANK 1 WE _CAS RAS3 ~ WE AD-9 AO-9 DATA 0-15 r--- CAS f---- ~ B1 BANK 1 DATA 16.,31 ""' .. RASIN CAS RFCK r-- WEr M2 Mo 1 t Qo-g J J, I I ,.... Co-g I I I I f-w.r- OP8428 Cs I l RASi RO-9 I I DATA RASo WIN I , RASa RGCK I RAS1 RASO RAHS J AD-S AO-9 BANKO CAS WE 32-BIT DATA BUS DATA 0-15 BANKO ~ CAS WE r-- ~ DATA 16-31 ~ I TL/F/8649-24 FIGURE 7c. Typical Application of DP8428 Using Modes 5 and 1 2) Less effort is needed to design a memory system. The DP8429 has automatic modes (1 and 5) which require a minimum of external control logic. Also programmable array logiC devices (PALs) have been designed which allow an easy interface to most popular microprocessors (Motorola 68000 family, National Semiconductor 32032 family, Intel 8086 family, and the Zilog Z8000 family). The DP84XX2 family of inexpensive preprogrammed medium Programmable Array Logic devices (PALs) have been developed to provide an easy interface between various microprocessors and the DP84XX family of DRAM controller/ drivers. These PALs interface to all the necessary control signals of the particular processor and the DP8429. The PAL controls the operation of the DP8429 in modes 5 and 1, while meeting all the critical timing considerations discussed above. The refresh clock, RFCK, may be divided down from the processor clock using an IC counter such as the DM74LS393 or the DP84300 programmable refresh timer. The DP84300 can provide RFCK periods ranging from 15.4 !,-S to 15.6 !,-S based on an input clock of 2 to 10 MHz. Figure 8 shows a general block diagram for a system using the DP8429 in modes 1 and 5. Figure 9 shows possible timing diagrams for such a system (using WAIT to prohibit access when refreshing). Although the DP84XX2 PALs are offered as standard peripheral devices for the DP84XX DRAM controller/drivers, the programming equations for these devices are provided so the user may make minor modifications for unique system requirements. 3) Less skew in memory timing parameters because all critical components are on one chip (many discrete drivers specify a minimum on-chip skew under worst-case conditions, but this cannot be used if more then one driver is needed, such as would be the case in driving a large dynamic RAM array). 4) Our switching characteristics give the deSigner the critical timing specifications based on TTL output levels (low = 0.8V, high = 2.4V) at a specified load capacitance. All timing parameters are specified on the DP8429: A) driving 88 DRAM's over a temperature range of 0-70 degrees centigrade (no extra drivers are needed). 8) under worst-case driving conditions with all outputs switching simultaneously (most discrete drivers on the market specify worst-case conditions with only one output switching at a time; this is not a true worst-case conditionl). ADVANTAGES OF DP8429 OVER A DISCRETE DYNAMIC RAM CONTROLLER 1) The DP8429 system solution takes up much less board space because everything is on one chip (latches, refresh counter, control logic, multiplexers, drivers, and internal delay lines). 1-84 » ""2-n" I» 0" ::1 16-BIT MICROPROCESSOR DATA BUS * .. rl MICROPROCESSOR AOORESS BUS DATA AOOR 1". RO·6, 7, 8, 9 H !---o- DECODER .,0 .." ~ I I I DP84300 a, r WAIT BO 1 ~r~ ~I wr :: r-- RFCK RGCK ""' hl RASO WiN r-- SELECT WAITt ~ ~ 1IRASIN RF lID M2 LJ NECESSARY IF INSTRUCTIONS INCLUDE BYTE-WRITING, OTHERWISE USE CAS OIRECTlY FROM THE DP8429 TO THE RAMS. V ~ GAS I-- J /- S- c '" S If.J" CAS U ~ 7,8, 9 "" I~ 'CASL\ ' - - - 'CASUI DPB4XX2 tTHE SELECT WAIT INPUT TO THE OP84XX2 CHIP INSERTS A WAIT STATE DURING ACCESSING, THIS MAY BE NECESSARY FOR VERY FAST MICRO· PROCESSORS ~ I" CASL ' - - !.t. 1--RJiS ~WE + L-t> ISTATU~ ~ I ..... '-··CASU ~~. OP8429 4- 2-10MHz t ~ -0 o r., "" ~ -'" '-" ADS .--- MICROPROCESSOR '" RAMS MAY BE 16k, 64~ o,256k • RAM ADDRESS BUS AD, 6, 00·6, 7,8,9 CS AD OR STROBE CLOCK R/W UPPER BYTE LOWER BYTE CO-6, 7, 8, 9 Bl til t WE MO + I m~ ),8,9 RAS WE - 0- , ~ ~U- I I I I I I .. LOWER UPPER BYTE BYTE WL- , 1" CAS U SELECT UPPER BYTE OM 748244 CAS L SELECT LOWER BYTE NECESSARY IF MORE THAN ONE BANK . . . '--TL/F/8649-26 FIGURE 8. Connecting the DP8429 Between the 16-bit Microprocessor and Memory 6l8l&SN/8l8l&SN/6lt8dO/8lt8dO ~. DP8428/DP8429/NS32828/NS32829 » '0 -I~~~I- "2. c;" DJ /-MEilDaY CYl:l.E--I------IIE_rCYClE-/ _ _ _ IMIZES UIW TIllE TD 21 CUltllS 1lAX1M1ZI1IG CHAlICE OF ..IIIEN REFlESH RFtK I---L ELSEWHERE I 0" :::J (I) '§ SELECTING CS r--- .• { ~ 3- 5" c: ~ AS HASIN RFSH 0, '" 01'8429 OUTPUTS RFRO (RFI/OJ mOUTPUTS 0IJ.8 lOW CAS WAif TUF/8649-27 *T is microprocessor"s clock period FIGURE 9. DP8429 Auto Refresh, Access with WAIT States .-----------------------------------------------------------------------,0 'V co Switching Characteristics oIiIo All A. C. parameters are specified with the equivalent load capacitances, including traces, of 88 DRAMs organized as 4 banks of 22 DRAMs each. Maximums are based on worstcase conditions including all outputs switching simultaneously. This, in many cases, results in the AC valves shown in the DP84XX DRAM controller data sheet being much looser than true worst case maximum AC delays. The system designer should estimate the DP8429 load in his/ her application, and mOdify the appropriate A. C. parameters using the graph in Figure 10. Two example calculations are provided below. + 16.0 ,.--.,---r--r-,.-.....,..-..., +7.6 I Other parameters are adjusted in a similar manner. 2) A mode 5 user driving one bank of DRAM has the following loading conditions: CAS - 120 pF 00-09 - 100 pF RAS -120 pF A. C. parameters should be adjusted as follows: with RAHS = "1", /V -76 'V V -15.0 '---'_--'......1.......1._-'-_-' -500 -300 -100 0 + 100 +300 +600 D~~&~~ o-.....,,,RD,..,..-._-._ _-o TEST POINT CpF TEST TL/F/8649-28 FIGURE 10. Change in Propagation Delay relative to "true" (application) load minus AC specified data sheet load 15g t I RL ~ Examples 1) A mode 4 user driving 2 banks of DRAM has the following loading conditions: CAS - 300 pF TL/F 18649-29 FIGURE 11. Output Load Circuit 00-09 - 250 pF RAS - 150 pF A.C. parameters should be adjusted in accordance with Figure 10 and the specifications given for the 88 DRAM load as follows: max tRPDl = 20 ns - 0 ns = 20 ns (since RAS loading is the same as that which is spec'ed) max tePDl = 32 ns - 7 ns = 25 ns max tecAS = 46 ns - 7 ns = 39 ns max tRce = 41 ns - 6 ns = 35 ns min tRHA is not significantly effected since it does not involve an output transition 1-87 !~ (0) min tRAH = 15 ns + 1 ns = 16 ns The additional 1 ns is due to the fact that the RAS line is driving less (switching faster) than the load to which the 15 ns spec applies. The row address will remain valid for about the same time irregardless of address loading since it is considered to be not valid at the beginning of its transition. O~-+--+V~+--4--~ o '" z en max tRICl = 70 ns - 11 ns = 59 ns max tRCDl = 55 ns + 1 ns - 11 ns = 45 ns (the + 1 ns is due to lighter RAS loading; the - 11 ns is due to lighter CAS loading) f--I--1'--i-+-'7I'V"----i ~ ..... ~ ~ ..... z en (0) N co N CD en N co N CO) en z ....... co N ~ CO) en z ....... en N ~ ~ o....... ~ ~ co a. o Absolute Maximum Ratings Operating Conditions (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage, Vcc 7.0V Storage Temperature Range Input Voltage Output Current Lead Temp. (Soldering, 10 seconds) Min 4.50 Max 5.50 Units V 0 +70 'C - 65'C to + 150'C 5.5V 150mA 300'C Electrical Characteristics Vcc = Symbol Supply Voltage Ambient Temperature VCC TA 5.0V ± 10%, O'C Parameter Vc Input Clamp Voltage Vcc IIH Input High Current for all Inputs VIN II RSI Output Load Current for RFI/O VIN IIl1 Input Low Current for all Inputs" VIN IIl2 ADS, RIC, CS, M2, RASIN VIN Vil Input Low Threshold VIH Input High Threshold VOl1 Output Low Voltage' VOl2 Output Low Voltage for RFI/O VOH1 Output High Voltage' VOH2 Output High Voltage for RFI/O 110 Output High Drive Current' 100 Output Low Drive Current' Icc Supply Current S; TA S; 70'C unless otherwise noted (Note 2) Min Conditions = Min,lc = - 12 mA = 2.5V = 0.5V, Output high = 0.5V = 0.5V Typ Max - 0.8 - 1.2 V 2.0 100 p.A -0.7 -1.5 mA -0.02 -0.25 mA -0.05 -0.5 mA 0.8 2.0 = 20 mA = 8mA IOH = - 1 mA IOH = - 100 p.A VOUT = 0.8V (Note 3) VOUT = 2.4V (Note 3) Vcc = Max Units V V IOl 0.3 0.5 V IOl 0.3 0.5 V 2.4 3.5 2.4 3.5 V -50 - 200 mA 50 200 150 V mA 240 mA 'Except RFI/O "Except RFI/O, ADS, RIC, CS, M2, RASIN Switching Characteristics: DP8428 and DP8429 Vcc = 5.0V ± 10%, O'C S; TA S; 70'C unless otherwise noted (Notes 2, 4, 5), the output load capacitance is typical for 4 banks of 22 DRAMs each or 88 DRAMs, including trace capacitance. * These values are QO-Q9, C( = 500 pF; RASO-RAS3, CL = 150 pF; WE, CL = 500 pF; CAS, CL = 600 pF; RL = 5000. unless otherwise noted. See Figure 11 for test load. Maximum propagation delays are specified with all outputs switching • •• Preliminary Symbol Access Parameter 'CL Condition "All CL = 50 pF Min Max Min Max Units tRIClO RASIN to CAS Low Delay (RAHS = 0) Figure 6 DP8428-80/29-80 57 97 42 85 ns tRIClO RASIN to CAS Low Delay (RAHS = 0) Figure 6 DP8428-70/29-70 57 87 42 75 ns tRICl1 RASIN to CAS Low Delay (RAHS = 1) Rgure6 DP8428-80/29-80 48 80 35 68 ns tRICl1 RASIN to CAS Low Delay (RAHS = 1) Figure 6 DP8428-70/29-70 48 70 35 58 ns tRICH RASIN to CAS High Delay Figure 6 37 ns tRCOlO RAS to CAS Low Delay (RAHS = 0) Figure 6 DP8428-80/29-80 43 80 ns tRCDLO RAS to CAS Low Deiay (RAHS = 0) t-igure 6 DP8428-70/29-70 43 72 ns 1-88 Switching Characteristics: DP8428 and DP8429 o"V 01) (Continued) ~ VCC = 5.0V ± 10%, O'C :S: TA :S: 70'C unless otherwise noted (Notes 2, 4, 5), the output load capacitance is typical for 4 banks of 22 DRAMs each or BB DRAMs, including trace capacitance. ....... • These values are 00-09, CL = 500 pF; RASO-RAS3, CL = 150 pF; WE, CL = 500 pF; CAS, CL = 600 pF; RL = soon unless otherwise noted. See Figure 11 for test load. Maximum propagation delays are specified with all outputs switching. •• Preliminary "'co" ....... Symbol Access Parameter *CL Condition "All CL Units Min Max tRCDLl RAS to CAS Low Delay (RAHS = 1) Figure 6 DPB428·80/29·80 34 63 ns tRGDLl ~ to CAS Low Delay Figure 6 DPB428·70/29·70 34 55 ns (RAHS = 1) Min = 50 pF Max o"V 01) N Z en c.,) N 01) N 01) ....... Z en c.,) N 01) tRCDH ~ to CAS High Delay Figure 6 tRAHO Row Address Hold Time (RAHS = 0, Mode 5) Figure 6 25 25 ns tRAHl Row Address Hold Time (RAHS = 1, Mode 5) Figure 6 15 15 ns tASG Column Address Set·up Time (Mode 5) Figure 6 0 0 ns tRCVO RASIN to Column Address Valid (RAHS = 0, Mode 5) Figure 6 DP8428·BO/29·80 94 ns tRCVO RASIN to Column Address Valid (RAHS = 0, Mode 5) Figure 6 DP8428·70/29·70 85 ns tRCVl RASIN to Column Address Valid (RAHS = 1, Mode 5) Figure 6 DP8428·80/29·80 76 ns tRCVl RASIN to Column Address Valid (RAHS = 1, Mode 5) Figure 6 DP842B·70/29·70 6B ns 22 ns tRPDL RASIN to RAS Low Delay Figures 5a, 5b, 6 21 18 tRPDH RASIN to RAS High Delay Figures 5a, 5b, 6 20 17 tASRL Address Set·up to RASIN low Figures 5a, 5b, 6 tAPD Address Input to Output Delay Figures 5a, 5b, 6 36 tSPD Address Strobe High to Address Output Valid Figures 5a, 5b 48 tASA Address Set·up Time to ADS Figures 5a, 5b, 6 5 tAHA Address Hold Time from ADS Figures 5a, 5b, 6 10 ns tADS Address Strobe Pulse Width Figures 5a, 5b, 6 26 ns tWPD WIN to WE Output Delay Figure5b 28 ns tCPDL CASIN to CAS Low Delay (RIC low, Mode 4) Figure5b 17 33 ns tCPDH CASIN to CAS High Delay (RIC low, Mode 4) Figure5b 13 33 ns tCPdif tCPDL . tCPDH See Mode 4 Description 13 ns tRCG Column Select to Column Address Valid Figure5a 41 ns tRCR Row Select to Row Address Valid Figures 5a, 5b 45 ns tRHA Row Address Held from Column Select Figure5a tGGAS RIC Low to CAS Low Delay (CASIN Low, Mode 4) Figure5a DP8428·80/29·80 50 ns tCCAS RIC Low to CAS Low Delay (CASIN Low, Mode 4) Figure5a DP8428·70/29·70 46 ns tDIFl Maximum (tRPDL • tRHN See Mode 4 Description 7 ns tDIF2 Maximum (tRCC . tCPDLl 13 ns 13 N co ns ns ns 25 ns ns ns 7 1·89 01) ns • Switching Characteristics: DP8428 and DP8429 (Continued) VCC = 5.0V ± 10%, O'C os; TA OS; 70'C unless otherwise noted (Notes 2, 4, 5). The output load capacitance is typical for 4 banks of 22 DRAMs each or 88 DRAMs, including trace capacitance. , These values are QO-Q9, CL = 500 pF; RASO-RAS3, CL = 150 pF; WE, CL = 500 pF; CAS, CL = 600 pF; RL = soon unless otherwise noted. See Figure 11 for test load. Maximum propagation delays are specified with all outputs switching. * 'Preliminary Symbol Refresh Parameter "All CL = 50 pF 'CL Condition Min Max Min Units Max tRC Refresh Cycle Period Figure2a 100 ns tRASINL,H Pulse Width of RASIN during Refresh Figure2a 50 ns tRFPDLO RASIN to RAS Low Delay during Refresh (Mode 0) Figure2a 28 ns tRFPDL5 RASIN to RAS Low Delay during Hidden Refresh Figure 7 38 ns tRFPDHO RASIN to RAS High Delay during Refresh (Mode 0) Figure2a 35 ns tRFPDH5 RASIN to RAS High Delay during Hidden Refresh Figure 7 44 ns tRFLCT RFSH Low to Counter Address Valid Figures 2a, 3 38 ns tRFLRL RFSH Low Set-up to RASIN Low (Mode 0), to get Minimum tASR = 0 Figure2a 12 ns tRFHRL RFSH High Setup to Access RASIN Low Figure 3 25 ns tRFHRV RFSH High to Row Address Valid Figure 3 43 ns tROHNC RAS High to New Count Valid Figure2a 42 ns tRST Counter Reset Pulse Width Figure2a tCTl RFIIO Low to Counter Outputs All Low Figure2a tRFCKl,H Minimum Pulse Width of RFCK Figure 7 100 ns T Period of RAS Generator Clock Figure 3 30 ns tRGCKL Minimum Pulse Width Low ofRGCK Figure 3 15 ns tRGCKH Minimum Pulse Width High of RGCK Figure 3 15 ns tFRQL RFCK Low to Forced RFRQ (RFIIO) Low tFRQH RGCK Low to Forced RFRQ High CS = X 60 ns 100 Figure 3 ns 66 ns 55 ns CL = 50pF RL = 35k Figure 3 CL = 50pF RL = 35k 1-90 Switching Characteristics: DP8428 and DP8429 (Continued) Vee = 5.0V ± 10%, O'C s: TA s: 70'C unless otherwise noted (Notes 2, 4, 5). The output load capacitance is typical for 4 banks of 22 DRAMs each or 88 DRAMs, including trace capacitance . • These values are QO-Q9, CL = 500 pFj RASO-RAS3, CL = 150 pFj WE, CL = 500 pFj CAS, CL = 600 pFj RL = 500n unless otherwise noted. See Figure 11 tor test load. Maximum propagation delays are specified with all outputs switching • • ·Prellmlnary Symbol Refresh Parameter ·CL Condition ··AIICL Min Max Min = 50pF Units Max tRGRL RGCK Low to FiAS Low Figure 3 20 41 tRGRH RGCK Low to RAS High Figure 3 20 48 tRQHRF RFSH Hold Time from RGCK Figure 3 2T tRFRH RFSH High to RAS High (Ending Forced Refresh early) (See Mode 1 Description) tRFSRG RFSH Low Set-up to RGCK Low (Mode 1) (See Mode 1 Description) Figure 3 12 ns tesHR ~ High to ~ Low for Figure 7 10 ns Figure 3 34 ns Figure 3 5 ns (See Mode 5 Description) 5 ns 50 ns ns ns ns 42 ns Hidden Refresh tesRLl for DP8429 ~ Low to Access RASIN tesRLl for DP8428 ~ Low to Access ~ tesRLO CS Low to Access RASIN Low (Using Modes 4 or 5 with externally controlled Refresh) tRKRL RFCK High to RASIN low for hidden Refresh Low (Using Mode 5 with Auto Refresh Mode) Low (Using Mode 5 with Auto Refresh Mode) Input Capacitance TA = Symbol CIN 25'C (Note 2) Parameter Condition Input Capacitance ADS, RIC, ~, M2, RASIN Min 'ryp 8 Max Units pF Input Capacitance All Other Inputs 5 pF CIN Not. 1: "Absolute Maximum Ratings" are the values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation. Not. 2: All typical values are for TA - 25'C and Vee - 5.0V. Note 3: This test is provided as a monitor of Driver output source and sink current capability. Caution should be exercised in testing this parameter. In testing these parameters, a 1511 resistor should be placed in series with each output under test. One output should be tested at a time and test time should not exceed 1 second . Note 4: Input pulse OV to 3.0V, tR - tF - 2.5 ns, f- 2.5 MHz, tpw - 200 ns. Input reference point on AC measurements Is 1.5V Output reference points are 2.4V for High and O.BV for Low. Note 5: The load capacitance on RF 1/0 should not exceed 50 pF. 1-91 • ~NatiOnal Semiconductor DP8420A/21A/22A microCMOS Programmable 256k/1 M/4M Dynamic RAM ControllerIDrivers General Description Features The DP8420Al21A122A dynamic RAM controllers provide a low cost, single chip interface between dynamic RAM and all 8-, 16- and 32-bit systems. The DP8420Al21A122A generate all the required access control signal timing for DRAMs. An on-chip refresh request clock is used to automatically refresh the DRAM array. Refreshes and accesses are arbitrated on chip. If necessary, a WAIT or DTACK output inserts wait states into system access cycles, including burst mode accesses. RAS low time during refreshes and RAS pre charge time after refreshes and back to back accesses are guaranteed through the insertion of wait states. Separate on-chip precharge counters for each RAS output can be used for memory interleaving to avoid delayed back to back accesses because of precharge. An additional feature of the DP8422A is two access ports to simplify dual accessing. Arbitration among these ports and refresh is done on chip. • On chip high precision delay line to guarantee critical DRAM access timing parameters • microCMOS process for low power • High capacitance drivers for RAS, CAS, WE and DRAM address on chip • On chip support for nibble, page and static column DRAMs • Byte enable signals on chip allow byte writing in a word size up to 32 bits with no external logic • Selection of controller speeds: 20 MHz and 25 MHz • On board Port AlPort B (DP8422A only)/refresh arbitration logic • Direct interface to all major microprocessors (application notes available) • 4 RAS and 4 CAS drivers (the RAS and CAS configuration is programmable) # of Pins # of Address (PLCC) Outputs 68 9 DP8421A 68 10 DP8422A 84 11 Control DP8420A Largest DRAM Possible Direct Drive Memory Capacity Access Ports Available 256 kbit 4 Mbytes Single Access Port 1 Mbit 16 Mbytes Single Access Port 4 Mbit 64 Mbytes Dual Access Ports (A and B) Block Diagram F DP8420A/21A122A DRAM Controller BANK ADORESS IN ROW ADDRESS IN 2 roo- 0 R 11,10,9 11,10,9 .I 11,ID 11,10 J ADDRESS LATCH (ROW, COLUMN" BANK) 11,10,9 MUX ~ ~ADIlRESS OUT E R COLUMN ADDRESS IN JL MODE LOAD CONTROL INPUTS _ I .. PROGRAMMING REGISTERS JC 1 t~:crrr:o~~~~. PORT B AND REFRESH SYSTEM CLOCK - ~ 11.10.9 SCRUBBING COLUMN COUNTER 11.10.9 IIt REFRESH ROW COUNTER WAIT I ATACKB (8<422A) I ~ t.-~ GRANTB (8422A) 2 SCRUBBING BANK MEMORY CYCLE :!~AZr~~: BANK SELECT LOGIC I 1-+[ --+1 _ RAS GENERATOR CAS GENERATOR ~ iilSo _ j--. ~~ --4 J-.. 4 3 G CASO - 3 S_Wr L.J TL/F/8588-5 FIGURE 1 1-92 C Table of Contents 1.0 INTRODUCTION 6.0 ADDITIONAL ACCESS SUPPORT FEATURES 6.1 Address Latches and Column Increment 2.0 SIGNAL DESCRIPTIONS 2.1 Address, R/W and Programming Signals 6.2 Address Pipelining 2.2 DRAM Control Signals 6.3 Delay CAS During Write Accesses 2.3 Refresh Signals 7.0 RAS AND CAS CONFIGURATION MODES 2.4 Port A Access Signals 7.1 Byte Writing 2.5 Port B Access Signals (DP8422A) 7.2 Memory Interleaving 2.6 Common Dual Port Signals (DP8422A) 7.3 Address Pipelining 2.7 Power Signals and Capacitor Input 7.4 Error Scrubbing 2.8 Clock Inputs 7.5 Page/Burst Mode 3.0 PORT A ACCESS MODES 8.0 PROGRAMMING AND RESETTING 3.1 Access Mode 0 8.1 External Reset 3.2 Access Mode 1 8.2 Programming Methods 3.3 Read-Modify·Write Access Cycles 8.2.1 Mode Load Only Programming 8.2.2 Chip Selected Access Programming 4.0 REFRESH OPTIONS 8.3 Definition of Programming Bits 4.1 Refresh Control Modes 4.1.1 Automatic Internal Refresh 9.0 TEST MODE 4.1.2 Externally Controlled/Burst Refresh 10.0 DRAM CRITICAL TIMING OPTIONS 4.1.3 Refresh Request/Acknowledge 10.1 Programming Values of tRAH and tAse 4.2 Refresh Cycle Types 10.2 Calculation of tRAH and tAse 4.2.1 Conventional Refresh 11.0 DUAL ACCESSING (DP8422A) 4.2.2 Staggered RefreshTM 4.2.3 Error Scrubbing Refresh 11.1 Port B Access Mode 4.3 Extending Refresh 11.2 Port B Wait State Support 4.4 Clearing the Refresh Address Counter 11.3 Common Port A and Port B Dual Port Functions 4.5 Clearing the Refresh Request Clock 11.3.1 GRANTB Output 11.3.2 LOCK Input 5.0 PORT A WAIT STATE SUPPORT 12.0 ABSOLUTE MAXIMUM RATINGS 5.1 WAIT Type Output 5.1.1 WAIT During Single Accesses 13.0 DC ELECTRICAL CHARACTERISTICS 5.1.2 WAIT During Page/Burst Accesses 14.0 AC TIMING PARAMETERS 5.2 DTACK Type Output 15.0 FUNCTIONAL DIFFERENCES BETWEEN THE DP8420A/21A/22A AND THE DP8420/21/22 5.2.1 DTACK During Single Accesses 5.2.2 DTACK During Page/Burst Accesses 16.0 DP8420Al21A122A USER HINTS 5.3 Dynamically Increasing the Number of Wait States 5.4 Guaranteeing RAS Low Time and RAS Precharge Time 1·93 "tI OCI ~ -... ~ C "tI OCI ~ N ~ C "tI OCI ~ N N » 1.0 Introduction The DP8420Al21A122A are CMOS Dynamic RAM controllers that incorporate many advanced features including the capabilities of address latches, refresh counter, refresh clock, row, column and refresh address multiplexor, delay line, refresh/access arbitration logic and high capacitive drivers. The programmable system interface allows any manufacturer's microprocessor or bus to directly interface via the DP8420A/21A122A to DRAM arrays up to 64 Mbytes in size. of these modes can be used together or separately to achieve the desired results. When using internal automatic refreshing, the DP8420A/ 21A122A will generate an internal refresh request from the refresh request clock. The DP8420Al21A122A will arbitrate between the refresh requests and accesses. Assuming an access is not currently in progress, the DP8420Al21A122A will assert the signal RFIP. On the next positive clock edge, refreshing will begin. If an access had been in progress, the refresh will begin after the access has terminated. To use externally controlled/burst refresh, the user disables the internal refresh request by asserting the input DISRFRSH. A refresh can now be externally requested by asserting the input RFSH. The DP8420Al21A122A will arbitrate between the external refresh request and accesses. Assuming an access is not currently in progress, the DP8420Al21A122A will assert the output RFIP. On the next positive clock edge, refreshing will begin. If an access had been in progress, the refresh would take place after the access has terminated. With refresh request/acknowledge mode, the DP8420Al 21A/22A broadcasts the internal refresh request to the system through the RFRQ output pin. External circuitry can determine when to refresh the DRAM through the RFSH input. After power up, the DP8420Al21A122A must first be programmed before accessing the DRAM. The chip is programmed through the address bus. There are two methods of programming the chip. The first method, mode load only, is accomplished by asserting the signal mode load, ML. A valid programming selection is presented on the row, column, bank and ECAS inputs, then ML is negated. When ML is negated, the chip is programmed with the valid programming bits on the address bus. The second method, chip selected access, is accomplished by asserting ML and performing a chip selected access. When CS and AREQ are asserted for the access, the chip is programmed. During this programming access, the programming bits affecting the wait logic become effective immediately, allowing the access to terminate. After the access, ML is negated and the rest of the programming bits take effect. The controllers have three types of refreshing available: conventional, staggered and error scrubbing. Any refresh control mode can be used with any type of refresh. In a conventional refresh, all of the RAS outputs will be asserted and negated at once. In a staggered refresh, the RAS outputs will be asserted one positive clock edge apart. Error scrubbing is the same as conventional refresh except that a CAS will be asserted during a refresh allowing the system to run that data through an EDAC chip and write it back to memory, if a single bit error has occurred. The refreshes can be extended with the EXTEND REFRESH input, EXTNDRF. Once the DP8420Al21A122A has been programmed, a 60 ms initialization period is entered. During this time, the DP8420Al21A122A controllers perform refreshes to the DRAM array so further DRAM warm up cycles are unnecessary. The DP8420Al21A122A can now be used to access the DRAM. There are two modes of accessing with the controller. The two modes are Mode 0, which initiates RAS synchronously, and Mode 1, which initiates RAS asynchronously. The DP8420Al21A/22A have wait support available as DTACK or WAIT. Both are programmable. DTACK, Data Transfer ACKnowledge, is useful for processors whose wait signal is active high. WAIT is useful for processors whose wait signal is active low. The user can choose either at programming. These signals are used by the on-chip arbitor to insert wait states to guarantee the arbitration between accesses and refreshes or precharge. Both signals are independent of the access mode chosen. DTACK will assert a programmed number of clock edges from the event that starts the access RAS. DTACK will be negated, when the access is terminated, by AREQ being negated. DTACK can also be programmed to toggle with the ECAS inputs during burst/page mode accesses. To access the DRAM using Mode 0, the signal ALE is asserted along with CS to ensure a valid VRAM access. ALE asserting sets an internal latch and only needs to be pulsed and not held throughout the entire access. On the next rising clock edge, RAS will be asserted for that access. The DP8420Al21A122A will place the row address on the DRAM address bus, guarantee the programmed value of row address hold time of the DRAM, place the column address on the DRAM address bus, guarantee the programmed value of column address setup time and assert CAS. AREQ can be asserted any1ime after the clock edge which starts the access RAS. RAS and CAS will extend until AREQ is negated. The other access mode, Mode 1, is asynchronous to the clock. When ADS is asserted, RAS is asserted. The DP8420Al21A122A will place the row address on the DRAM address bus, guarantee the programmed value of row address hold time, place the column address on the DRAM address bus, guarantee the programmed value of column address setup time and assert CAS. AREQ can be tied to ADS or can be asserted after ADS is asserted. ~ negated will terminate the access. The DP8420Al21A122A have grell.tty expanded refresh capabilities compared to other DRAM controllers. There are three modes of refreshing available. These modes are internal automatic refreshing, externally controlled/burst refreshing, and refresh request/acknowledge refreshing. Any WAIT is asserted during the start of the access (ALE and CS, or ADS and CS) and will negate a number of clock edges from the event that starts the access l'iAS. After WAIT is negated, it will stay negated until the next access. WAIT can also be programmed to toggle with ECAS inputs during a burst/page mode access. Both signals can be dynamically delayed further through the WATfff\j signal to the DP8420Al21A122A. The DP8420Ai2iAi22A have address latches, used to latch the bank, row and column address inputs. Once the address is latched, a column increment feature can be used to increment the column address. The address latches can also be programmed to be fall through. 1-94 1.0 Introduction (Continued) The RAS and CAS drivers can be configured to drive a one, two or four bank memory array up to 32 bits in width. The ECAS signals can then be used to select one of four CAS drivers for byte writing with no external logic. this purpose since it is asserted when Port B has access to the DRAM array and negated when Port A has access to the DRAM array. Once a port has access to the array, the other port can be "locked out" by asserting the input LOCK. AREQB, when asserted, is used by Port B to request an access. ATACKB, when asserted, signifies that access RAS has been asserted for the requested Port B access. By using AT ACKB, the user can generate an appropriate WAIT or DTACK like signal for the Port B CPU. The following explains the terminology used in this data sheet. The terms negated and asserted are used. Asserted refers to a "true" signal. Thus, "ECASO asserted" means the ECASO input is at a logic o. The term "COLINC asserted" means the COLINC input is at a logic 1. The term negated refers to a "false" signal. Thus, "ECASO negated" means the ECASO input is at a logic 1. The term "COLINC negated" means the input COLINC is at a logic o. The table shown below clarifies this terminology. When configuring the DP8420A/21A/22A for more than one bank, memory interleaving can be used. By tying the low order address bits to the bank select lines, BO and B1, sequential back to back accesses will not be delayed since the DP8420Al21A122A have separate precharge counters per bank. The DP8420A/21A122A are capable of performing address pipelining. In address pipelining, the DP8420Al 21A122A guarantee the column address hold time and switch the internal multiplexor to place the row address on the address bus. At this time, another memory access to another bank can be initiated. The DP8422A has all the features previously mentioned. Unlike the DP8420Al21A, the DP8422A has a second port to allow a second CPU to access the memory array. This port, Port B, has two control signals to allow a CPU to access the DRAM array. These signals are access request for Port B, AREQB, and Advanced Transfer ACKnowledge for Port B, ATACKB. Two other signals are used by both Port A and Port B for dual accessing purposes. The signals are lock, LOCK and grant Port B, GRANTB. All arbitration for the two ports and refresh is done on-chip by the DP8422A through the insertion of wait states. Since the DP8422A has only one input address bus, the address lines have to be multiplexed externally. The signal GRANTB can be used for Signal Action Logic Level Active High Asserted High Active High Negated Low Active Low Asserted Low Active Low Negated High Connection Diagrams 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 Rl 10 60 WAmN Cl 11 59 RFSH R2 12 58 DISRFSH C2 13 57 DElClK R3 14 56 ClK C3 15 55 R4 16 54 COllNC C4 17 R5 18 Vee 53 GND DP8420A 52 1M: C5 19 51 GND R6 20 50 CAP C6 21 49 Vee R7 22 48 C7 23 47 AREQ R8 24 46 WIN C8 25 45 CAS3 R9 26 44 CAS2 CS TLiF/8588-4 Top View FIGURE 2 Order Number DP8420AV·20 or DP8420AV·25 See NS Package Number V68A 1-95 Connection Diagrams (Continued) 9 8 7 6 5 4 3 21M ~ " ~ M ~ ~ ~ 60 WArnN Rl 10 Cl 11 59 RFSH R2 12 58 DlSRFSH C2 13 R3 14 57 DEl.CI.K C3 15 55 Vee R4 16 54 COLINC 56 CLK C4 17 53 GND R5 18 C5 DP8421A 52 iii: 19 51 GND R6 20 50 CAP C6 21 49 Vee R7 22 48CS C7 23 47 AREQ WiN R8 24 46 C825 45 CAS3 R9 26 44 CAS2 TUF/8588-3 Top View FIGURE 3 Order Number DP8421AV-20 or DP8421AV-25 See NS Package Number V68A 11 10 9 co 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 12 74 13 73 Rl 14 72 RAP Cl 15 71 WAmN R2 16 70 RFSH C2 17 69 IlISRFSH R3 18 68 DELCLK C3 19 67 CLK R4 20 66 Vee C4 21 R5 22 ~ DP8422A COUNC M GND C523 63 GND R6 24 62 C6 25 61 GND R7 26 80 CAP iii: C7 27 59 Vee R8 28 56CS C8 57 LQCK 29 R9 30 56 AREQ8 C9 31 55 AREQ 32 54 WiN TL/F/8568-2 Top View FIGURE 4 Order Number DP8422AV-20 or DP8422AV-25 See NS Package Number V84A 1·96 2.0 Signal Descriptions Pin Name Device (If not Applicable to All) Inputl Output Description 2.1 ADDRESS, R/W AND PROGRAMMING SIGNALS RO-1O RO-9 DP8422A DP8420A/21A I I ROW ADDRESS: These inputs are used to specify the row address during an access to the DRAM. They are also used to program the chip when Ml is asserted (except R10). CO-1O CO-9 DP8422A DP8420A/21A I I COLUMN ADDRESS: These inputs are used to specify the column address during an access to the DRAM. They are also used to program the chip when Ml is asserted (except C1 0). BO,B1 I BANK SELECT: Depending on programming, these inputs are used to select a group of RAS and CAS outputs to assert during an access. They are also used to program the chip when Ml is asserted. ECASO-3 I ENABLE CAS: These inputs are used to enable a single or group of CAS outputs when asserted. In combination with the BO, B1 and the programming bits, these inputs select which CAS output or CAS outputs will assert during an access. The ECAS signals can also be used to toggle a group of CAS outputs for page/nibble mode accesses. They also can be used for byte write operations. If ECASO is negated during programming, continuing to assert the ECASO while negating AREO or AREOB during an access, will cause the CAS outputs to be extended while the RAS outputs are negated (the ECASn inputs have no effect during scrubbing refreshes). WIN I WRITE ENABLE IN: This input is used to signify a write operation to the DRAM. If ECASO is asserted during programming, the WE output will follow this input. This input asserted will also cause CASto delay to the next positive clock edge if address bit C9 is asserted during programming. COLINC (EXTNDRF) I I COLUMN INCREMENT: When the address latches are used, and RFIP is negated, this input functions as COLINC. Asserting this signal causes the column address to be incremented by one. When RFIP is asserted, this signal is used to extend the refresh cycle by any number of periods of ClK until it is negated. Ml I MODE LOAD: This input signal, when low, enables the internal programming register that stores the programming information. 2.2 DRAM CONTROL SIGNALS 0 0 0 DRAM ADDRESS: These outputs are the multiplexed output of the RO-9, 10 and CO-9, 10 and form the DRAM address bus. These outputs contain the refresh address whenever RFIP is asserted. They contain high capacitive drivers with 2011 series damping resistors. RASO-3 0 ROW ADDRESS STROBES: These outputs are asserted to latch the row address contained on the outputs 00-8, 9, 10 into the DRAM. When HFIP is asserted, the RAS outputs are used to latch the refresh row address contained on the 00-8, 9, 10 outputs in the DRAM. These outputs contain high capacitive drivers with 2011 series damping resistors. CASO-3 0 COLUMN ADDRESS STROBES: These outputs are asserted to latch the column address contained on the outputs 00-8, 9, 10 into the DRAM. These outputs have high capacitive drivers with 2011 series damping resistors. WE (RFRO) 0 0 WRITE ENABLE or REFRESH REQUEST: This output asserted specifies a write operation to the DRAM. When negated, this output specifies a read operation to the DRAM. When the DP8420A/21 A/22A is programmed in interleave mode or when ECASO is negated during programming, this output will function as RFRO. When asserted, this pin specifies that 13 I-'s or 15 I-'s have passed. If DISRFSH is negated, the DP8420A/21A122A will perform an internal refresh as soon as possible. If DISRFRSH is asserted, RFRO can be used to externally request a refresh through the input RFSH. This output has a high capacitive driver and a 2011 series damping resistor. 00-10 00-9 00-8 DP8422A DP8421A DP8421A 1-97 2.0 Signal Descriptions (Continued) Pin Name Device (If not Applicable to All) Input! Output Description 2.3 REFRESH SIGNALS RFIP 0 REFRESH IN PROGRESS: This output is asserted prior to a refresh cycle and is negated when all the RAS outputs are negated for that refresh. RFSH I REFRESH: This input asserted with DISRFRSH already asserted will request a refresh. If this input is continually asserted, the DP8420Al21 Al22A will perform refresh cycles in a burst refresh fashion until the input is negated. If RFSH is asserted with DISRFSH negated, the internal refresh address counter is cleared (useful for burst refreshes). ~ I DISABLE REFRESH: This input is used to disable internal refreshes and must be asserted when using RFSH for externally requested refreshes. (ALE) I I ADDRESS STROBE or ADDRESS LATCH ENABLE: Depending on programming, this input can function as ADS or ALE. In mode 0, the Input functions as ALE and when asserted along with ~ causes an internal latch to be set. Once this latch is set an access will start from the positive clock edge of ClK as soon as possible. In Mode 1, the input functions as ADS and when asserted along with ~, causes the access RAS to assert if no other event is taking place. If an event is taking place, RAS will be asserted from the positive edge of ClK as soon as possible. In both cases, the low going edge of this Signal latches the bank, row and column address if programmed to do so. ~ I CHIP SELECT: This input signal must be asserted to enable a Port A access. AREQ I ACCESS REQUEST: This input Signal in Mode 0 must be asserted some time after the first positive clock edge after ALE has been asserted. When this signal is negated, RAS is negated for the access. In Mode 1, this Signal must be asserted before ADS can be negated. When this signal is negated, RAS is negated for the access. WAIT (DTACK) 0 0 WAIT or DTACK: This output can be programmed to insert wait states into a CPU access cycle. With R7 negated during programming, the output will function as a WAIT type output. In this case, the output will be active low to signal a wait condition. With R7 asserted during programming, the output will function as DTACK. In this case, the output will be negated to signify a wait condition and will be asserted to signify the access has taken place. Each of these signals can be delayed by a number of positive clock edges or negative clock levels of ClK to increase the microprocessor's access cycle through the insertion of wait states. WAITIN I 2.4 PORT A ACCESS Am WAIT INCREASE: This input can be used to dynamically increase the number of positive clock edges of ClK until DTACK will be asserted or WAIT will be negated during a DRAM access. 1-98 2.0 Signal Descriptions (Continued) Pin Name Device (If not Applicable to All) Inputl Output Description 2.5 PORT B ACCESS SIGNALS AREaS DPB422A only I PORT B ACCESS REQUEST: This input asserted will latch the row, column and bank address if programmed, and requests an access to take place for Port B. If the access can take place, RAS will assert immediately. If the access has to be delayed, RAS will assert as soon as possible from a positive edge of CLK. ~ DPB422A only 0 ADVANCED TRANSFER ACKNOWLEDGE PORT B: This output is asserted when the access RAS is asserted for a Port B access. This signal can be used to generate the appropriate DTACK or WAIT type signal for Port B's CPU or bus. 2.6 COMMON DUAL PORT SIGNALS GRANTB DPB422A only 0 GRANT B: This output indicates which port is currently granted access to the DRAM array. When GRANTB is asserted, Port B has access to the array. When GRANTB is negated, Port A has access to the DRAM array. This Signal is used to multiplex the Signals RO-B, 9, 10; CO-B, 9, 10; BO-1; WlliI; ~ andECASO-3 to the DPB422A when using dual accessing. LOCK DPB422A only I LOCK: This input can be used by the currently granted port to "lock out" the other port from the DRAM array by inserting wait states into the locked out port's access cycle until [(X;i( is negated. 2.7 POWER SIGNALS AND CAPACITOR INPUT Vee I POWER: Supply Voltage. GND I GROUND: Supply Voltage Reference. CAP I CAPACITOR: This input is used by the internal PLL for stabilization. The value of the ceramic capaCitor should be 0.1 /LF and should be connected between this input and ground. 2.8 CLOCK INPUTS There are two clock inputs to the DPB420Al21A122A, CLK and DELCLK. These two clocks may both be tied to the same clock input, or they may be two separate clocks, running at different frequencies, asynchronous to each other. CLK I SYSTEM CLOCK: This input may be in the range of 0 Hz up to 25 MHz. This input is generally a constant frequency but it may be controlled externally to change frequencies or perhaps be stopped for some arbitrary period of time. This input provides the clock to the internal state machine that arbitrates between accesses and refreshes. This clock's positive edges and negative levels are used to extend the WAIT (DTACK) Signals. Ths clock is also used as the reference for the RAS precharge time and RAS low time during refresh. All Port A and Port B accesses are assumed to be synchronous to the system clock CLK. DELCLK I DELAY LINE CLOCK: The clock input DELCLK, may be in the range of 6 MHz to 20 MHz and should be a multiple of 2 (i.e., 6, B, 10, 12, 14, 16, 1B, 20 MHz) to have the DP8420Al21A122A switching characteristics hold. If DELCLK is not one of the above frequencies the accuracy of the internal delay line will suffer. This is because the phase locked loop that generates the delay line assumes an input clock frequency of a multiple of 2 MHz. For example, if the DELCLK input is at 7 MHz and we choose a divide by 3 (program bits CO-2) this will produce 2.333 MHz which is 16.667% off of 2 MHz. Therefore, the DP8420Al21 Al22A delay line would produce delays that are shorter (faster delays) than what is intended. If divide by 4 was chosen the delay line would be longer (slower delays) than intended (1.75 MHz instead of 2 MHz). (See Section 10 for more information.) This clock is also divided to create the internal refresh clock. 1·99 3.0 Port A Access Modes The DP8420Al21A122A have two general purpose access modes. With one of these modes, any microprocessor can be inter/aced to DRAM. A Port A access to DRAM is initiated by two input signals: ADS (ALE) and CS. The access is always terminated by one signal: AREO. These input signals should be synchronous to the input clock, ClK. One of these access modes is selected at programming through the B 1 input signal. In both modes, once an access has been requested by CS and ADS (ALE), the DP8422A will guarantee the following: 3.1 ACCESS MODE 0 Access Mode 0, shown in Figure Sa, is selected by negating the input B1 during programming. This access mode allows accesses to DRAM to always be initiated from the positive edge of the system input clock, ClK. To initiate a Mode 0 access, ALE is pulsed high and CS is asserted. Pulsing ALE high and asserting CS, sets an internal latch which requests an access. If the precharge time from the last access or DRAM refresh had been met and a refresh of DRAM or a Port B access was not in progress, the RAS or group of RASs would be initiated from the first positive edge of ClK. If a DRAM refresh is in progress or precharge time is required, the controller will wait until these events have taken place and assert RAS on the next positive edge of ClK. Sometime after the first positive edge of ClK after ALE and CS have been asserted, the input AREQ must be asserted. In single port applications, once AREO has been asserted, CS can be negated. Once AREQ is negated, RAS and DTACK, if programmed, will be negated. If ECASO is asserted during programming, CAS will be negated with AREQ. If ECASO was negated during programming, a Single CAS or group of CASs will continue to be asserted after RAS has been negated given that the appropriate ECASs inputs were The DP8420Al21A122A will have the row address valid to the DRAMs' address bus, 00-8, 9, 10 given that the row address setup time to the DP8420Al21A122A was met; The DP8420Al21A122A will bring the appropriate RAS or RASs low; The DP8420A/21A/22A will guarantee the minimum row address hold time, before switching the internal multiplexor to place the column address on the DRAM address bus, 00-8,9, 10; The DP8420A/21A122A will guarantee the minimum column address setup time before asserting the appropriate CAS or CASs; The DP8420A/21A122A will hold the column address valid the minimum specified column address hold time in address pipelining mode and will hold the column address valid the remainder of the access in non-pipelining mode. 00-8,9,10 COLUMN TL/F/8588-60 FIGURE Sa. Access Mode 0 1-100 3.0 Port A Access Modes (Continued) asserted as shown in Figure 5b. This allows the DRAM to have data present on the data out bus while gaining RAS precharge time. ALE can stay asserted several periods of ClK. However, ALE must be negated before or during the period of ClK in which AREQ is negated. es, which are not delayed by precharge, Port 8 access or refresh, to start immediately from the access request input, ADS. To initiate a Mode 1 access, ~ is asserted followed by ADS asserted. If the programmed precharge time from the last access or DRAM refresh had been met and a refresh of the DRAM or Port 8 access to the DRAM was not in progress, the RAS or group of 'RASs selected by programming and the bank select inputs would be asserted from ADS being asserted. If a DRAM refresh or Port 8 access is in progress or precharge time is required, the controller will wait until these events have taken place and assert FiAS or the group of FiASs from the next positive edge of ClK. When performing address pipelining, the ALE input cannot be asserted to start another access until AREQ has been asserted for at least one clock period of ClK for the present access. 3.2 ACCESS MODE 1 Access Mode 1, shown in Figure 68, is selected by asserting the input 81 during programming. This mode allows access- ClK ALE 00-8,9,10 _ _ _", ...._ _ _R~OW_ _...f'I-._ _ _ _ _ CO..;l;.;,UM;.;,N_ _ _ _ _' .......;.;;...F"-_______ Tl/F/8588-61 FIGURE 5b. Access Mode 0 Extending CAS ClK 00-8,9,10 COLUMN ROW TLlF/8588-62 FIGURE 6a. Access Mode 1 1-101 ~~------------------------------------------------------------~ ~ ~ C ;c N .., ~ C ~ N .., f C 3.0 Port A Access Modes (Continued) When ADS is asserted or sometime after, AREQ must be asserted. At this time, ADS can be negated and AREQ will continue the access. Once AREQ is negated, RAS and DTACK, if programmed,will be negated. If ECASO was asserted during programming, CAS will be negated with AREQ. If ECASO was negated during programming, a single CAS or group of CASs will continue to be asserted after RAS has been negated given that the appropriate ECAS inputs were asserted as shown in Figure 6b. This allows a ~RAM to have data present on the data out bus while gainIng RAS precharge time. ADS can continue to be asserted after AREQ has been asserted and negated, however a new access would not be started until ADS is negated and asserted again. ADS and AREQ can be tied together in applications not using address pipelining. 3.3 READ-MODIFY-WRITE CYCLES WITH EITHER ACCESS MODE There are 2 methods by which this chip can be used to do read-modify·write access cycles. The first method involves doing a late write access where the WIN input is asserted some delay after CAS is asserted. The second method involves doing a page mode read access followed by a page mode write access with RAS held low (see Figure 5). CASn must be toggled using the ECASn inputs and WIN has to be changed from negated to asserted (read to write) while CAS is negated. This method is better than changing WiN from negated to asserted in a late write access because here a problem may arise with DATA IN and DATA OUT being valid at the same time. This may result in a data line trying to drive two different levels simultaneously. The page mode method of a read-modify-write access allows the user to have transceivers in the system because the data in (read data) is guaranteed to be high impedance duro ing the time the data out (write data) is valid. If address pipe lining is programmed, it is possible for ADS to be negated after AREQ is asserted. Once AREQ is asserted, ADS can be asserted again to initiate a new access. ClK QO-8,9,10 ROW COLUMN Tl/F 18588-63 FIGURE 6b. Access Mode 1 Extending CAS 1-102 3.0 Port A Access Modes (Continued) 11K (d:-!~ --------< WRITE DATA READ CYCLE WlIITECYCLE TL/F IB5BB-G2 'There may be idle states Inserted here by the CPU. FIGURE Bc. Read·Modlfy·Wrlte Access Cycle 4.0 Refresh Options The DP8420Al21A/22A support a wide variety of refresh control mode options including automatic internally controlled refresh, externally controlled/burst refresh, refresh request/ acknowledge and any combination of the above. With each of the control modes above, different types of refreshes can be performed. These different types include all RAS refresh, staggered refresh and error scrubbing during all RAS refresh. There are three inputs, EXTNDRF, RFSH and DISRFSH, and two outputs, RFIP and RFRO, associated with refresh. There are also ten programming bits; RO-1, R9, CO-6 and ECASO used to program the various types of refreshing. The two inputs, RFSH and DISRFSH, are used in the externally controlled/burst refresh mode and the refresh request/acknowledge mode. The output RFRO is used in the refresh requset/acknowledge mode. The input EXTNDRF and the output RFIP are used in all refresh modes. Asserting the input EXTNDRF, extends the refresh cycle single or multiple integral clock periods of CLK. The output RFIP is asserted one period of CLK before the first refresh RAS is asserted. If an access is currently in progress, RFIP will be asserted up to one period of CLK before the first refresh RAS, once AREO or AREOB is negated for the access (see Figure 7a). 4.1.1. Automatic Internal Refresh The DP8420Al21A122A have an internal refresh clock. The period of the refresh clock is generated from the program· ming bits CO-3. Every period of the refresh clock, an internal refresh request is generated. As long as a DRAM access is not currently in progress and precharge time has been met, the internal refresh request will generate an automatic internal refresh. If a DRAM access is in progress, the DP8420Al21A122A on-chip arbitration logic will wait until the access is finished before performing the refresh. The refresh/ access arbitration logic can insert a refresh cycle between two address pipelined accesses. However, the refresh arbitration logic can not interrupt an access cycle to perform a refresh. To enable automatic internally controlled refreshes, the input DISRFSH must be negated. RfRQoRffijojffip AClpoRFRQ TL/F/B5BB-FB Explanation of Terms The DP8420A/21A/22A will increment the refresh address counter automatically, independent of the refresh mode used. The refresh address counter will be incremented once all the refresh RASs have been negated. In every combination of refresh control mode and refresh type, the DP8420A/21A/22A is programmed to keep RAS asserted a number of CLK periods. The values of RAS low time during refresh are programmed with the programming bits RO and R1. RFIP = ACIP = 4.1 REFRESH CONTROL MODES There are three different modes of refresh control. Any of these modes can be used in combination or singularly to produce the desired refresh results. The three different modes of control are: automatic internal refresh, external/ burst refresh and refresh request/acknowledge. 4.1.2 Externally Controlled/Burst Refresh To use externally controlled/burst refresh, the user must disable the automatic internally controlled refreshes by asserting the input DISRFSH. The user is responsible for generating the refresh request by asserting the input RFSH. Pulsing RFSH low, sets an internal latch, that is used to RFRO = RFSH = ReFresh ReOuest Internal to the DP8420Al21A/22A. RFRO has the ability to hold off a pending access. Extemally requested ReFreSH ReFresh In Progress Port A or Port B (DP8422A only) ACoess In Progress. This means that either RAS is low for an aeoess or is in the prooess of transltioning low for an access. FIGURE 7a. DP8420A/21A122A Access/Refresh Arbitration State Program 1-103 ~ N o::t co a. Q ....... ..... eLK C "U CO .".. ... II) l> ..... C "U CO .".. II) II) l> RASn TLlF/B5BB-BO FIGURE 17d. Mode 1 Delayed Access with WAIT OT (WAIT is Sampled at the End of the "T2" Clock State) T1 T2 T3 T4 elK ALE cs AREQ RASn WAIT TLlF/B5BB-B1 FIGURE 18a. Mode 0 Non-Delayed Access with WAIT OT (WAIT is Sampled at the "Ta" Failing Clock Edge) T1 T2 T3 lW T4 elK ALE cs AREQ RASn I il WAIT TL/F/B5BB-B2 FIGURE 18b. Mode 0 Delayed Access with WAIT Y.T (WAIT is Sampled at the "Ta" Falling Clock Edge) OT during non·delayed accesses and Y.T during delayed accesses: WAIT will stay negated during a non-delayed access as shown in Figures 18a and 18c. During an access that is delayed, WAIT will assert at the start of the access CS and ALE or ADS) and negate on the negative level of ClK after the positive edge of ClK that asserted RAS for that access as shown in Figures 18b and 18d. 1-111 5.0 Port A Wait State Support (Continued) Tl T2 T3 T4 CLK RASn WAIT TUF/8588-83 FIGURE 18c. Mode 1 Non-Delayed Access with WAIT OT (WAIT Is Sampled at the "T3" Falling Clock Edge) T1 T3 T2 TW T4 CLK I ~I TL/F/8588-84 FIGURE 18d. Mode 1 Delayed Access with WAIT %T (WAIT is Sampled at the "T3" Falling Clock Edge) 1-112 5.0 Port A Wait State Support C co "'D (Continued) 'loT during non-delayed and delayed accesses: if mode 0 is used, WAIT will assert when ALE is asserted and CS is asserted. WAIT will then negate on the negative level of ClK after the positive edge of ClK that asserts RAS for the access as shown in Figure 19a. In Mode 1, WAIT will assert from CS asserted and ADS asserted. WAIT will then negate on the negative level of ClK after RAS has been asserted for the access as shown in Figure 1ge. During delayed accesses in both modes, WAIT will assert at the start of the access and negate on the negative level of ClK after the positive edge of ClK that started RAS for that access as shown in Figures 19b and 19d. N """ o ~ C "'D co ....""" N ~ T1 TW T2 T3 C "'D co ClK """ N N ~ ALE RASn WAIT TL/F/8588-85 FIGURE 19a. Mode 0 Non-Delayed Access with WAIT 'loT (WAIT is Sampled at the "T2" Falling Clock Edge) T1 T2 TW TW 13 ClK ALE RASn WAIT TLiF/8588-86 FIGURE 19b. Mode 0 Delayed Access with WAIT 'loT (WAIT is Sampled at the "T2" Falling Clock Edge) 1-113 5.0 Port A Wait State Support (Continued) Tl T2 TW T3 CLK RASn TLIF/8588-87 FIGURE 19c. MODE 1 Non-Delayed Accesl with WAIT VaT (WAIT II Sampled at the "T2" Failing Clock Edge) Tl T2 TW TW T3 elK RASn TLIF/8588-88 FIGURE 19d. Mode 1 Delayed Accels with WAIT VaT (WAIT is Sampled at the "T2" Failing Clock Edge) 1-114 5.0 Port A Walt State Support (Continued) CS have been asserted as shown in Figure 20c. During de- 1T during non-delayed and delayed accesses. In Mode 0, WAIT will assert from ALE asserted and CS asserted. WAiT will negate from the next positive edge of CLK that asserts for the access as shown in Figure 2013. In Mode 1, WAiT will assert from ADS asserted and CS asserted. WAIT will negate from the first positive edge of CLK after ADS and layed accesses in both modes, WAif will assert at the beginning of the access and will negate on the first positive edge of CLK after the positive edge of CLK that starts RAS for the access as shown in Figures 20b and 20d. m T1 T2 TW T3 ClK ALE RASn TL/F/B5BB-B9 FIGURE 20a. Mode 0 Non-Delayed Acce•• with Wlf'i' 1T (WAiT I. Sampled at the End of the "T2" Clock State) T1 T2 TW TW T3 ClK ALE cs AREQ RASn WAiT TL/F/B5BB-90 FIGURE 20b. Mode 0 Delayed Acce•• with WAIT 1T (WAIT I. Sampled at the End of the "12" Clock State) 1-115 5.0 Port A Walt State Support (Continued) eLK RASn TUF/8588-91 FIGURE 20c. Mode 1 Non·Delayed Access with WAIT 1T (WAIT Is Sampled at the End of the "T2" Clock State) T1 12 TW 13 CLK RASn TLlF/8588-92 FIGURE 2Od. Mode 1 Delayed Access with WAIT 1T (WAIT Is Sampled at the End of the "T2" Clock State) When ending WAIT from a negative level of ClK; if RAS is asserted while ClK is high then WAiT will negate from the negative edge of ClK; if ~ is asserted while ClK is low then WAIT will negate from RAS asserting. When ending WAiT from a positive edge of ClK in Mode 0, the user can think of the positive edge of ClK that starts RAS as OT and the next positive edge of ClK as 1T. When ending WAIT from a positive edge of ClK in Mode 1, the positive edge of ClK that AIlS is setup to can be thought of as 1T in a non· delayed access. In a delayed access, the positive edge of ClK that starts l'iAS can be thought of as OT and the next positive edge as 1T. 5.1.2 Walt during Page Burst Accesses WAIT can be programmed to function differently during page/burst types of accesses. During a page/burst access, the ECAS inputs will be asserted then negated while AREQ is asserted. Through address bits R4 and R5, WAIT can be programmed to assert and negate during this type of access. The user is given four programming options described below. No Wait States: In this case, WAiT will remain negated even if the ~ inputs are toggled as shown in FigurB 21. 1·116 5.0 Port A Wait State Support (Continued) ClK BEGINNING AREQ ACg~S ~! ~-!-, A Hi ___oJ t I._!--__...J ~...I.., A:~- _ _ _...J t I t Tl/F/B5B8-93 FIGURE 21. No Wait States during Burst (WAIT is Sampled at the End of the "TS" Clock State) 1 T3 .1 1 T4 ~ ClK BEGINNING OF AREQ ACCESS RASn ECAS CAS WAIT TL/F/8588-94 FIGURE 22. OT during Burst (WAIT is Sampled at the End of the "TS" Clock State) T3 TW T4 T3 TW T4 T3 TW T4 CLK AREQ BEGINNING OF ACCESS RASn ECAS CAS WAIT TLlF/B588-95 FIGURE 2S. Y2T during Burst Access (WAIT is Sampled at the "TS" Falling Clock Edge) OT: WAIT will be asserted when the ECAS inputs are negated with AREQ remaining asserted. When a single or group of ECAS inputs are asserted, WAIT will be negated as shown in Figure 22. %T: WAIT will be asserted when the ECAS inputs are negated with AREQ remaining asserted. When a single or group of ECAS inputs are asserted again, WAIT will be negated from the first negative level of ClK after a single ECAS or group of ECASs are asserted as shown in Figure 23. 1-117 5.0 Port A Wait State Support (Continued) 1T: WAIT will be asserted when the ~ inputs are negated with AREQ remaining asserted. When a single or group of J:CAS inputs are asserted again, WAIT will be negated from the first positive edge of ClK after a single ECAS or group of ECASs are asserted as shown In Figure 24. ative levels from the event that starts ~ for the access. DTACK can also be programmed to function during pagel burst mode accesses. Once DTACK is asserted and the ~ inputs are negated with AR'EO asserted, DTACK can be programmed to negate and assert from the 'ECAS inputs toggling to perform a page/burst mode operation. Once AR'EO is negated, ending the access, I5TACK will be negated and stays negated until the next chip selected access. When ending WAI'i' from a negative level of ClK; if the ECASs are asserted while ClK Is high then WAIT will negate from the negative edge of ClK, if the ~s are asserted while ClK is low then WAIT will negate from the ECASs asserting. When ending WAIT from a positive edge of ClK, the positive edge of ClK that ECAS Is setup to can be thought of as 1T. 5.2.1 DTACK during Singi. Ace..... be programmed to delay a number of positive edges and/or negative levels of ClK. These options are programmed through address bits R2 and R3 at programming time. The user is given four options described by the following. OT during non-delayed accesses and delayed accesses: in Mode 0, 'I:i'f.lmK will ass.rt from the positive edge of ClK which starts FiAS as shown In Figure 268. In Mode 1, 'I:i'f.lmK will assert from AOS and OS as shown In Figure 26c. During delayed accesses In both modes, 'DTACK will assert from the positive edge 01 ClK which starts 'AAS for the access as shown In Figure 26b and 26d. 'DTACK can 5.2 DTACK TYPE OUTPUT With the R7 address bit asserted during programming, the user selects the DTACK type output. As long as DTACK is sampled negated by the CPU, wait states are inserted Into the current access cycle as shown In Figure 25. Once DTACK Is sampled asserted; the access cycle is completed by the CPU. 'I:i'f.lmK, which Is normally negated, Is programmed to assert a number of positive edges and/or neg- eLK o 0 0 BEGINNING Am A~~ IiASn Tl/F/85SB-1HI FIGURE 24. 1T during Bur.t Ace••• (WAIT I. sampl.d at the End of the "T3" Clock Stat.) I ClK Til T21TWI T31 ~ HIGH INSERTS A WAITSTATE IN THE ACCESS CVCU: DTACK SAMPLm LOW ALLOWS THE CPU TO TERMINATE THE ACCESS CYCLE FIGURE 25. DTACK Typ. Output 1-118 TUF/8588-97 ----------------------'0 ." 5.0 Port A Wait State Support c» .j:o. (Continued) T1 T2 14 ~ o 1 » ...... -.r\ elK o ." c» .j:o. ~ .... » ...... o ." c» .j:o. ~ RASn ~ TL/F/B588-96 FIGURE 26a. Mode a Non·Delayed Access with DTACK aT (DTACK is Sampled at the End of the "T2" Clock State) T1 TW T2 13 14 elK ALE RASn PRECHARGE TL/F/8588-99 FIGURE 26b. Mode a Delayed Access with DTACK aT (2T Clock Periods Are Programmed for RAS Precharge, DTACK is Sampled at the End of the "T2" Clock State) elK TL/F/B5B8-AO FIGURE 26c. Mode 1 Non-Delayed Access with DTACK aT (DTACK is Sampled at the End of the "T2" Clock State) T1 T2 ,I TW 13 1 14 1 .J'J\ elK PRECHARGE TL/F/8588-A1 FIGURE 26d. Mode 1 Delayed Access with DTACK OT (DTACK is Sampled at the End of the "T2" Clock State) 1-119 5.0 Port A Wait State Support (Continued) asserted as shown in Figures 27c and 27d. During delayed accesses in both modes, DTACK will assert from the negative level of ClK after the positive edge of ClK which starts RAS for the access as shown in Figures 27b and 27e. Y.T during non-delayed and delayed accesses: In Mode 0, DTACK will assert on the negative level of ClK after the positive edge of ClK which starts RAS as shown in Figure 27a. In Mode 1, DTACK will assert from the negative level of ClK after ADS has been asserted given that RAS is T1 T2 T3 T4 CLK AlE TLlF/8588-A2 FIGURE 27a. Mode 0 Non-Delayed Access with DTACK of Y.T (DTACK Is Sampled at the "T3" Failing Clock Edge) T2 T1 T3 T4 1W ClK ALE cs AREQ RASn PRECHARGE DTACK TL/F/8588-A3 FIGURE 27b. Mode 0 Delayed Access with DTACK of Y.T (DTACK Is Sampled at the "T3" Failing Clock Edge) T1 T2 T3 T4 CLK ADS cs AREQ RASn DTACK TL/F/8588-A4 FIGURE 27c. Mode 1 Non-Delayed Access with DTACK of Y.T (DTACK Is Sampled at the "T2" Failing Clock Edge) 1-120 C ." 5.0 Port A Wait State Support (Continued) I I T1 I T2 CD ~ I\) TW T3 0 T4 » ...... c ." CD ~ I\) ..... » ...... c ." CD ~ I\) I\) » Tl/F/8588-A5 FIGURE 27d. Mode 1 Non-Delayed Access with DTACK of %T (DTACK is Sampled at the "T2" Falling Clock Edge) Tl T2 TW TW T3 T4 ClK ADS cs AREQ RASn PRECHARGE I DTACK Tl/F/8588-A6 FIGURE 27e. Mode 1 Delayed Access with DTACK of %T (DTACK is Sampled at the "T2" Falling Clock Edge) 1T during delayed and non-delayed accesses: In Mode 0, DTACK will assert from the first positive edge of ClK after the positive edge of ClK which starts RAS for the access as shown in Figure 28a. In Mode 1, DTACK will assert from the T1 positive edge ClK after ADS and CS are asserted as shown in Figures 28c and 28d. During delayed accesses in both modes, DTACK will assert from the first positive edge of ClK after the positive edge of ClK which starts RAS for the access as shown in Figures 28b and 28e. T2 T3 ~ ClK I ALE RASn Tl/F/8588-A7 FIGURE 28a. Mode 0 Non-Delayed Access with DTACK of 1T (DTACK is Sampled at the End of the "T2" Clock State) 1-121 5.0 Port A Wait State Support (Continued) I I T1 T2 I I T3 TW elK ALE RASn PRECHARGE TL/F/8588-A8 FIGURE 28b. Mode 0 Delayed Access with DTACK of 1T (DTACK is Sampled at the End of the "T2" Clock State) T1 A9 T2 T3 T4 elK ADS cs AREQ RASn DTACK TLiF/8588-A9 FIGURE 28c. Mode 1 Non-Delayed Access with DTACK of 1T (DTACK is Sampled at the End of the "T2" Clock State) 80 I T1 T2 T3 T4 elK RASn '------'-___-.ly FIGURE 28d. Mode 1 Late Non-Delayed Access with DTACK of 1T (DTACK is Sampled at the End of the "T2" Clock State) 1·122 TLiF/8588-8D C ." .... m 5.0 Port A Wait State Support (Continued) I T1 I 12 1W 1W T3 N Q 1W ~ ...... eLK C ." ............. m N ~ C ." ....N m N ~ PRECHARGE TL/F/B5B8-Bl FIGURE 28e. Mode 1 Delayed Acceaa with DTACK of 1T (DTACK la Sampled at the End of the "T2" Clock State) 1%T during delayed and non-delayed accesses; In Mode 0, l5'i'AeK will assert from the negative level after the first posi- tive edge of elK after ADS and ~ are asserted as shown in Figures 29c and 29ft. During delayed accesses in both modes, ~ will assert from the negative level after the first positive edge of elK after the positive edge of elK which starts m for the access as shown in Figures 29b and 296. tive edge of elK after the positive edge of elK which starts for the access as shown in Figure 29B. In Mode 1, ~ will assert from the negative level after the first posl- m T1 12 1W 1W CLK ALE TL/F/B5B8-B2 FIGURE 29a. Mode 0 Non-Delayed Access with DTACK of 1%T (DTACK Is Sampled at the "T2" Falling Clock Edge) TLlF/B5BB-B3 FIGURE 29b. Mode 0 Delayed Accell with DTACK of 1% T (DTACK Is Sampled at the "T2" Failing Clock Edge) 1-123 5.0 Port A Wait State Support (Continued) 12 T1 T3 1W ClK TL/F/8588-B4 FIGURE 29c. Mode 1 Non-Delayed Access with DTACK of 1V.T (DTACK is Sampled at the "T2" Falling Clock Edge) 12 Tl T3 1W 1W ClK ADS cs AREQ RASn DTACK TL/F/B58B-B5 FIGURE 29d. Mode 1 Non-Delayed Access with DTACK of 1V.T (DTACK is Sampled at the "T2" Failing Clock Edge) 12 T1 T3 1W 1W T3 ClK PRECHARGE, TL/F/858B-B6 FIGURE 2ge. Mode 1 Delayed Access with DTACK of 1V.T (DTACK is Sampled at the "12" Failing Clock Edge) 1-124 C ." 5.0 Port A Wait State Support (Continued) co .j:Oo When starting DTACK from a negative level of ClK; if RAS is asserted while ClK is high then DTACK will assert from the negative edge of ClK, if RAS is asserted while ClK is low, then DTACK will assert from RAS asserting. When starting DT ACK from a positive edge of ClK in Mode 0, the positive edge of ClK that starts RAS can be thought of as aT. In Mode 1 during non-delayed accesses, the positive edge of ClK that ADS is setup to can be thought of as n. During delayed accesses, the positive edge of ClK that starts RAS can be thought of as aT and the next positive edge of ClK as n. the ECAS inputs will be asserted then negated while AREQ remains asserted. Through address bits R4 and R5, DTACK can be programmed to negate and assert during this type of access. The user is given four programming options described below. No Wait States: In this case, DTACK wll remain asserted even if the ECAS inputs are negated with AREQ asserted as shown in Figure 30. aT: DTACK will be negated when the ECAS inputs are negated with AREQ asserted. When a single or group of ECAS inputs are asserted again, DTACK will be asserted as shown in Figure 31. 5.2_2 DTACK during Page/Burst Accesses DT ACK can be programmed to function differently during page/burst types of accesses. During a page/burst access, T3 ,I T4 T3 , I T4 T3 ,I T4 T3 ,I T4 ClK BEGINNING or AREQ ACCESS RASn ECAS CAS DTACK TLiF/8588-B7 FIGURE 30. No Wait States during Burst Access (DTACK is Sampled at the End of the "T3" Clock State) T3 T4 T3 T4 T3 T4 T3 T4 ClK BEGINNING AREQ ACg~SS TLiF/8588-B8 FIGURE 31. OT during Burst Access (DTACK is Sampled at the End of the "T3" Clock State) 1-125 N o » ....... c ." co .j:Oo N ...... » ....... c ." co .j:Oo N N » 5.0 Port A Wait State Support (Continued) %T: DTACK will be negated when the ECAS inputs are negated with AREO asserted. When a single or group of ECAS inputs are asserted again, DTACK will be asserted from the first negative level of ClK after the single or group of ECASs are asserted as shown in Figure 32. 1T: DTACK will be negated when the ECAS inputs are negated with AREO asserted. When a single or group of ECAS inputs are asserted again, DTACK will be asserted from the first positive edge of ClK after the single or group of ECASs are asserted as shown in Figure 33. ClK BEGINNING AREQ ACg~SS TLiF/BSB8-B9 FIGURE 32. %T during Burst Access (DTACK is Sampled at the "T3" Falling Clock Edge) ClK BEGINNING AREQ or ACCESS m ECAS CAS DTACK Tl/F/8S88-CO FIGURE 33. 1T during Burst Access (DTACK Is Sampled at the "T3" Failing Clock Edge) 1-126 C 'tI 5.0 Port A Wait State Support (Continued) CO When starting DTACK from a negative level of ClK; if the ECASs are asserted while ClK is high then DTACK will assert from the negative edge of ClK, if the ECASs are asserted while ClK is low then DTACK will assert from the ECASs asserting. When starting DTACK from a positive edge of ClK, the positive edge of ClK that ECAS is setup to can be thought of as n. 5.4 GUARANTEEING RAS LOW TIME AND RAS PRECHARGE TIME The DP8420A/21A/22A will guarantee RAS precharge time between accesses; between refreshes; and between access and refreshes. The programming bits RO and R 1 are used to program combinations of RAS precharge time and RAS low time referenced by positive edges of ClK. RAS low time is programmed for refreshes only. During an access, the system designer guarantees the time RAS is asserted through the DP8420Al21 Al22A wait logic. Since inserting wait states into an access increases the length of the CPU signals which are used to create ADS or ALE and AREQ, the time that RAS is asserted can be guaranteed. 5_3 DYNAMICALLY INCREASING THE NUMBER OF WAIT STATES The user can increase the number of positive edges of ClK before DTACK is asserted or WAIT is negated. With the input WAITIN asserted, the user can delay DTACK asserting or WAIT negating either one or two more positive edges of ClK. The number of edges is programmed through address bit R6. If the user is increasing the number of positive edges in a delay that contains a negative level, the positive edges will be met before the negative level. For example if the user programmed DTACK of Y.T, asserting WAITIN, programmed as 2T, would increase the number of positive edges resulting in DTACK of 2Y.T as shown in Figure 34a. Similarly, WAITIN can increase the number of positive edges in a page/burst access. WAITIN can be permanently asserted in systems requiring an increased number of wait states. WAITIN can also be asserted and negated, depending on the type of access. As an example, a user could invert the WRITE line from the CPU and connect the output to WAITIN. This could be used to perform write accesses with 1 wait state and read accesses with 2 wait states as shown in Figure 34b. '" N o » ....... c 'tI CO '"..... N » ....... c'tI CO ..j:Oo N N » Precharge time is also guaranteed by the DP8420Al21A1 22A. Each RAS output has a separate positive edge of ClK counter. AREQ is negated setup to a positive edge of ClK to terminate the access. That positive edge is n. The next positive edge is 2T. RAS will not be asserted until the programmed number of positive edges of ClK have passed as shown in Figures 35, 37a, and 37b. Once the programmed precharge time has been met, RAS will be asserted from the positive edge of ClK. However, since there is a precharge counter per RAS, an access using another RAS will not be delayed. Precharge time before a refresh is always referenced from the access RAS negating before RASO for the refresh asserting. After a refresh, precharge time is referenced from RAS3 negating, for the refresh, to the access RAS asserting. --- ----------------------------~\I~!------~ WAITIN ,'-_ _ _ _ _ _- - . . . , . . - - - - -....; - - ACCESS WITH DTACK OF ~T ACCESS WITH DTACK OF ~T WITH WAITIN ASSERTED PROGRAMMED AS 2T WITH WAITIN NEGATED Tl/F/8588-C1 • FIGURE 34a. WAITIN Example (DTACK is Sampled at the "T3" Falling Clock Edge) Tl T2 ,I TW ,I T1 13 T2 TW TW T3 ClK ALE R/W ---------1:~ L- ,~~ WAITIN ACCESS WITH WAIT OF IT WITH WAITIN NEGATED ACC'-E-SS--W-ITH""""""'W--AIT--OF--IT-W-IT-H-W-A-IT-IN.../ ASSERTED PROGRAMMED AS IT FIGURE 34b. WAITIN Example (WAIT is Sampled at the End of "T2") t-127 TLlF/8588-C2 5.0 Port A Wait State Support (Continued) T1 T3 T1 T3 T2 T3 ClK ADS ----,..~_i_+-_:_---I ARro---~ r-~----~~~_~_~J----~~_-+~~_~_~ RASO----~~~~~~,-~----Jril--r_i\--~----r_~r_t__r--t_---RAS1--------~~--~~~~~----~~~--~~j--~-----+--~~~~--~J WACK----~~_ _1__y_-~---~~_~__\J'~--~---L--~j MODE 1 ACCESS TO BANK a WITH DTACK OF ~ T PROGRAMMED MODE 1 ACCESS TO BANK 1 WITH DTACK OF ~ T PROGRAMMED MODE 1 ACCESS TO~BA-N-K-l'--WI-TH""'DT~ACK OF ~ T, HELD OFF BECAUSE OF PRECHARGE (Programmed as 3T precharge) TL/F/8588-C3 FIGURE 35. Guaranteeing RAS Precharge (DTACK Is Sampled at the "T2" Falling Clock Edge) 6.0 Additional Access Support Features To support the different modes of accessing, the DP8420Al 21A122A have multiple access features. These features allow the user to take advantage of CPU or DRAM functions. These additional features include: address latches and column increment for page/burst mode support; address pipelining to allow a new access to start to a different bank of DRAM after CAS has been asserted and the column address hold time has been met; and delay CAS, to allow the user with a multiplexed bus to ensure valid data is present before CAS is asserted. the column address is incremented. If COLINC is asserted with all of the bits of the column address asserted, the column address will return to zero. COLiNC can be used for sequential accesses of static column DRAMs. COLINC can also be used with the ECAS inputs to support sequential accesses to page mode DRAMs as shown in Figure 36. COLINC should only be asserted when the signal RFiP is negated during an access since this input functions as extend refresh when RFIP is asserted. COLINC must be low (negated) when the address is being latched (A15S falling edge in Mode 1). The address latches function differently with the DP8422A. The DP8422A will latch the address of the currently granted port. If Port A is currently granted, the address will be latched as described in Section 6.1. If Port A is not granted, and requests an access, the address will be latched on the first or second positive edge of ClK after GRANTB has been negated depending on the programming bits RO, Rl. For Port B, if GRANTB is asserted, the address will be latched with AREQB asserted. If GRANTB is negated, the address will latch on the first or second positive edge of ClK after GRANTB is asserted depending on the programming bits RO, Rl. 6.1 ADDRESS LATCHES AND COLUMN INCREMENT The address latches can be programmed, through programming bit BO, to either latch the address or remain permanently in fall-through mode. If the address latches are used to latch the address, the rising edge of ALE in Mode 0 places the latches in fall-through. Once ALE is negated, the address present on the row, column and bank inputs is latched. In Mode 1, the address latches are in fall-through mode until AOO is asserted. ADS asserted latches the address. Once the address is latched, the column address can be incremented with the input COLINC. With COLINC asserted, 1-128 6.0 Additional Access Support Features 6.2 ADDRESS PIPELINING Address pipelining is the overlapping of accesses to differ· ent banks of DRAM. If the majority of successive accesses are to a different bank, the accesses can be overlapped. Because of this overlapping, the cycle time of the DRAM accesses are greatly reduced. The DP8420A/21 A/22A can be programmed to allow a new row address to be placed on the DRAM address bus after the column address hold time has been met. At this time, a new access can be initiated with ADS or ALE, depending on the access mode, while AREa is used to sustain the current access. The DP8422A supports address pipelining for Port A only. This mode can not be used with page, static column or nibble modes of operations because the DRAM column address is switched back to the row address after CAS is asserted. This mode is programmed through address bit R8 (see Figures 37a and 37b). In this mode, the output WE always functions as RFRa. C co "tI (Continued) During address pipelining in Mode 0, shown in Figure 37c, ALE cannot be pulsed high to start another access until AREa has been asserted for the previous access for at least one period of ClK. DTACK, if programmed, will be negated once AREa is negated. WAIT, if programmed to insert wait states, will be asserted once ALE and CS are asserted. In Mode 1, shown in Figure 37d, ADS can be negated once AREa is asserted. After meeting the minimum negated pulse width for ADS, ADS can again be asserted to start a new access. DT ACK, if programmed, will be negated once AREa is negated. WAIT, if programmed, will be asserted once ADS is asserted. .,.. N CI » c .,.."tI co N ..... » c "tI .,.. co N N » In either mode with either type of wait programmed, the DP8420A/21 A/22A will still delay the access for precharge if sequential accesses are to the same bank or if a refresh takes place. COLINC o aO-8,9,10 2 TLlF/8588-C4 FIGURE 36. Column Increment RASO CASO ADDRESS :L~ _____.;.;,;;.;;,;;;;.~ ____..Jx NEXT ROW COLUMN TL/F/8588-GO FIGURE 37a. Non·Address Pipelined Mode II TLlF/8588-G1 FIGURE 37b. Address Pipelined Mode 1·129 DP8420A/DP8421A/DP8422A T1 I T2 ClK L,T3 ._1_T1 _1- T2 L, T3 ._1_Tl I T2 I T3 --' _I_~3W I !» o TI T3W -' » D. ALE D. ;:::; AREO O· RASO !!. :::I » CASO () 00-8,9,10 X ROW X COLUMN "X j ROW X COLUMN CD Precha~e en en rJ) c 'v "- CAS 1 WAIT \ "( RASI () ;X • ROW j " WAITO WAITO ACCESS #1 TO BANK 0 BEGINNING: ACCESS #1 TO BANK 0 ENDING : ACCESS #2 TO BANK 1 BEGINNING DEl.AYEDA~ .A' COLUMN iA. ROW '0 '0 ~ ACCESS #2 TO BANK 1 ENDING ACCESS #3 TO BANK 1 DELAYED BECAUSE OF PRECHARGE (2T) TUF/8588-C5 FIGURE 37c. Mode 0 Address Pipelining (WAIT of 0, %T has Been Programmed. WAIT is Sampled at the "T3" Falling Clock Edge) o wArr~T ." CD !. c ~ CD ~ en Co> 0 I T1 T2 T2 T3 ClK &> ~ lii'" .s ADS AREO RASO CASO RASI CASI 00-8,9,10 DTACK 1~ RFIP TUF/8588-.C6 FIGURE 37d. Mode 1 Address Pipelining (DTACK 1%T Programmed, DTACK is Sampled at the "T3" Falling Clock Edge) o"'0 6.0 Additional Access Support Features (Continued) Address bit C9 asserted during programming will cause CAS to be delayed until the first positive edge of ClK after RAS is asserted when the input WIN is asserted. Delaying CAS during write accesses ensures that the data to be written to T2 ~ DRAM will be setup to CAS asserting as shown in Figures 388 and 38b. If the possibility exists that data still may not be present after the first positive edge of ClK, CAS can be delayed further with the ECAS inputs. If address bit C9 is negated during programming, read and write accesses will be treated the same (with regard to CAS). 6.3 DELAY CAS DURING WRITE ACCESSES T1 CD T1 T3 T2 N o ~ o"'0 CD ~ N ..... » ...... o"'0 T3 CD ClK ~ N N » ALE AREQ RAS CAS \~------------------- WIN MODE 0 WRITE ACCESS CAS CAN ASSERT ONLY AFTER FIRST POSITIVE CLOCK EDGE AFTER RAS IS ASSERTED MODE 0 READ ACCESS NORMAL CAS ASSERTION TL/F/8588-C7 FIGURE 38a. Mode 0 Delay CAS T1 T2 T2 T1 T3 T3 elK ADS AREQ RAS CAS \~---------------------------- WiN MODE 1 READ ACCESS NORMAL CAS ASSERTION MODE 1 WRITE ACCESS CAS CAN ASSERT ONLY AFTER FIRST POSITIVE CLOCK EDGE AFTER RAS IS ASSERTED TL/F/8588-C8 FIGURE 38b. Mode 1 Delay CAS 1-131 II ~ ~ 7.0 RAS and CAS Configuration Modes a. Q ...... ----...... ECASl [CAS2 ECAS3 TLlF/8588-D2 FIGURE 39d. 8 Bank DRAM Array for 16·Bit System (C6, C5, C4 1·133 = 1,1,0 during Programming) 7.0 RAS and CAS Configuration Modes (Continued) 7.2 MEMORY INTERLEAVING 7.3 ADDRESS PIPELINING Memory interleaving allows the cycle time of DRAMs to be reduced by having sequential acces_ to different memory banks. Since the DP8420Al21A122A /lave separate precharge counters per bank, sequential accesses will not be delayed if the accessed banks use different RAS outputs. To ensure different RAS outputs will be used, a mode is selected where either one or two RAS outputs will be asserted during an access. The bank select or selects, BO and B 1, are then tied to the least significant address bits, causing a different group of RASs to assert during each sequential access as shown in Agure 40. In this figure there should be at least one clock period of all RAS's negated between different RAS's being asserted to avoid the condition of a CAS before RAS refresh cycle. Address pipelining allows several access RASs to be asserted at once. Because RASs can overlap, each bank reo quires either a mode where one RAS and one CAS are used per bank as shown in Figure 418 or where two "RASs and two CASs are used per bank as shown in Figure 41b. Byte writing can be accomplished in a 16-bit word system if two RASs and two CASs are used per bank. In other systems, WEs (or external gating on the CAS outputs) must be used to perform byte writing. If WEs are used separate data in and data out buffers must be used. If the array is not layed out this way, a CAS to a bank can be low before RAS, which will cause a refresh of the DRAM, not an access. To take full advantage of address pipelining, memory interleaving is used. To memory interleave, the least significant address bits should be tied to the bank select inputs to ensure that all "back to back" sequential accesses are not delayed, since different memory banks are accessed. DP8420A/21 A/22A LOWER LOWER BYTE LOWER MIDDLE BYTE UPPER MIDDLE BYTE UPPER UPPER BYTE ECASO ECASl ECAS2 ECAS3 TL/F/8588-D3 FIGURE 40. Memory Interleaving (Ce, C5, C4 = 1,1,0 during Programming) 1·134 7.0 RAS and CAS Configuration Modes (Continued) DP8420A/21 A/22A may b. tied to ground In this case TL/F/8588-D4 FIGURE 41a. DRAM Array Setup for 4 Banks Using Address Plpellnlng (C6, C5, C4 = 1,1,1 or C6, C5, C4 = 0, 1, (Also Allowing Error Scrubbing) during Programming) ° DP8420A/21A/22A TL/F/858B-D5 FIGURE 41b. DRAM Array Setup for Address Plpellnlng with 2 Banks (C6, C5, C4 = 1,0,1 or C6, C5, C4 = 0, 0, 1 (Also Allowing Error Scrubbing) during Programming) 7.4 ERROR SCRUBBING In error scrubbing during refresh, the user selects one, two or four RAS and ~ outputs per bank. When performing error detection and correction, memory is always accessed I lOW ORDER ADR BIT ,OW ORDER ADR BIT + I eo as words. Since the eAS signals are not used to select individual bytes, the ECAS inputs can be tied low as shown in Figures 42a and 42b. DP8420A/21 A/22A BI iiASi Ro-S.9,IO CO-S,9,IO ADDRESS ------- MAY BE TIED TO GROUND IN TH1S CASE RASa CASO CASI RAS2 EWO CAS2 ECASI ECAS2 ECAS3 RAS3 CAS3 :I BANKO .I BANKI :I BANK2 .I BANK3 U FIGURE 42a. DRAM Array Setup for 4 Banks Using Error Scrubbing (C6, C5, C4 = 0, 1, -:!:- - I lOW ADR B1T DRESS MAY BE TIED TO GROUND IN TH1S CASE ------- BD BI DPS420A/21 A/22A RO-S,9,IO Co-S,9,IO RASO RASI CASO CASI ECASO RAS2 EClS1 Rill ECAS2 ECAS3 CAS2 CAS3 ° I I I I Tl/F/BSBB-D6 during Programming) BANKO BANKI U TL/F/65B6-D7 FIGURE 42b. DRAM Array Setup for Error Scrubbing with 2 Banks (C6, C5, C4 = 0, 0, 1 during Programming) 1·135 ~,-----------------------------------------------------------------~ N N ~ 7.0 RAS and CAS Configuration Modes (Continued) D- 7.5 PAGE/BURST MODE :( ,.. In a static column, page or burst mode system, the least significant bits must be tied to the column address in order to ensure that the page/burst accesses are to sequential memory addresses, as shown in Rgure 43. In a nibble mode system, the least significant bits must be tied to the highest column and row address bits in order to ensure that sequential address bits are the "nibble" bits for nibble mode accesses (Figure 43). The ECAS inputs may then be tog- co C N ~ co D- C ~ N gled with the DP8420A/21 Al22A's address latches in fallthrough mode, while AREQ is asserted. The ECAS inputs can also be used to select individual bytes. When using nibble mode DRAMS, the third and fourth address bits can be tied to the bank select inputs to perform memory interleaving. In page or static column modes, the two address bits after the page size can be .tied 10 the bank select inputs to select a new bank if the page size is exceeded. ~ co D- LOW ORDER { ADDRESS BITS AFTER COLUMN • C BO RASO Bl LADDRESS AFTER BANK RASI DP8420A/21 A/22A RAS2 RO-8,9,10 1 SEE BYTE WRITE SECTION FOR CONNECTION RAS3 I CO-8,9,10 LOW ORDER BITS m~! WRITE SECTION FOR CONNECTION ECASO ECASI ECAS2 I~ I~ I~~ Ie;; ~ () ~ ECAS3 . , SEE BYTE WRITE SECTION FOR CONNECTION TL/F/8588-D8 *See table below for row, column & bank address bit map. AO,A1 are used for byte addressing in this example Addresses Page Mode/Static Column Mode Page Size Nibble Mode' 256 Bits/Page 512 Bits/Page 1024 Bits/Page 2048 Bits/Page Column Address C9,R9 ~ A2,A3 CO-8 ~ X CO-7 ~ A2-9 C8-10 ~ X CO-8 ~ A2-10 C9.10 ~ X CO-9 ~ A2-11 Cl0 ~ X CO-l0 Row Address X X X X X BO Bl A4 AS Al0 Al1 Al1 A12 A12 A13 A13 A14 ~ A2-12 Assume that the least significant address bits are used for byte addressing. Given a 32~bit system AO,A 1 would be used for byte addressing. X ~ DON'T CARE. the user can do as he pleases. *Nibble mode values for A and C assume a system using 1 Mbit DRAMs. FIGURE 43. Page, Static Column, Nibble Mode System 1-136 r---------------------------------------------------------~c ~ 8.0 Programming and Resetting The DP8420Al21A122A must be programmed by one of two possible programming sequences before it can be used. At power up, the DP8420A/21A122A programming bits are in an undefined state. All internal latches and flip-flops are cleared. After programming, the DP8420Al21A122A enters a 50 ms initialization period. During this initialization period, the DP8420Al21A/22A performs refreshes about every 15 ,...s; this makes further DRAM warmup cycles unnecessary. The chip can be programmed as many times as the user wishes. After the first programming, the 50 ms initialization period will not be entered into unless the chip is reset. During the 50 ms initialization period, RFIP is asserted. The actual initialization time period is given by the following formula: T = 409S·(Clock Divisor Select) ·(Refresh Clock Fine Tune) I(DELCK Frequency) \f.i[ 8.1 EXTERNAL RESET At power up, all internal latches and flip-flops are cleared. The power up state can again be entered by asserting ML and DISRFSH for 16 positive edges of CLK. After resetting if the user negates DISRFSH before negating ML as shown in Figure 44a, ML negated will program the chip. If ML is negated before or at the same time as DISRFSH as shown in Figure 44b, the chip will not be programmed. After the chip is programmed, the 60 ms initialization period will be entered into if this is the first programming after power up or reset. It is recommended that the user perform a hardware reset of the DP8420Al21A122A before programming and using the chip. 16 CLOCKS "" ~ ):0 ..... C "tI 01) ..."" N ~ C "tI 01) ""~ N '1 I \ , DISRFSH ~ \ TLlF/8588-E2 FIGURE 44a. Chip Reset and Programmed r--- 16 POSITIVE EDGES OF ClK oo~ -~~ ---I t""7"Z7"7V"'-jr--TLlF/8588-E1 FIGURE 44b. Chip Reset but Not Programmed • 1-137 8.0 Programming and Resetting (Continued) 8.2 PROGRAMMING METHODS 8.2.1 MODE LOAD ONLY PROGRAMMING Using this method, a set of transceivers on the address bus can be put at TRI-STATE® by the system reset signal. A combination of pull-up and pull-down resistors can be used on the address inputs of the OP8420Al21 Al22A to select the programming values, as shown in FIgure 45b. MODE LOAD, ML, asserted enables an internal 23·bit programmable register. To use this method, the user asserts ML, enabling the internal programming register. After ML is asserted, a valid programming selection is placed on the address bus (and ECASO), then ML is negated. When ML is negated, the value on the address bus (and ECASO) is latched into the internal programming register and the DP8420A/21A/22A is programmed, as shown in Figure 45a. After ML is negated, the DP8420Al21A122A will enter the 60 ms initialization period only if this is the first program· ming after power up or reset. 8.2.2 CHIP SELECTED ACCESS PROGRAMMING The chip can aillo be programmed by asserting ML and performing a chip selected access. ADS (or ALE) is disabled internally until after programming. To program the chip using this method, ML is asserted. After ML is asserted, CS is asserted and a valid programming selection is placed on the address bus. When AREQ is asserted, the chip is programmed with the programming selection on the address bus. After AREQ is negated, ML can be negated as shown in Figure 46a. The DP8420Al21A122A must be programmed by one of two possible programming sequences before it can be used. \ ______...,1 MI ECASO BO,Bl - - - - - - - -..... RO-9 CO-9 _ _ _ _ _ _ _ _ _..J X X PROGRAMMING ........J 1-_ _ _ _ __ \--"B~ITiil.S,;;:.VQlAL;il;ID TlIF/8588-D9 FIGURE 45a. Mode Load Only Programming ADDRESS LATCHES AND DRIVERS CPU SYSTEM POWER UP RESET -...1.....--1 ~>O---....J TlIF/8588-10 'Pull-Up or Pull-Down Resislors on Each Address Input FIGURE 45b. Programming during System Reset / ADS OR ALE :XXXXXXXXXXXX x XXl(XXXXXX /XXXXXXXXXXXXxXXXXXXX xxxxxx~"\ / ADDRESS AND ECASO X VALID PROGRAMMING SELEcnON DPB420A/21 A/22A PROGRAMMED TL/F/8588-EO FIGURE 46a. CS Access Programming 1-138 8.0 Programming and Resetting (Continued) Using this method, various programming schemes can be used. For example if extra upper address bils are available, an unused high order address bit can be tied to the signal ML. Using this method, one need only write to a page of memory, thus asserting the high order bit and in turn programming the chip as shown in Figure 46b. DATA ~l CONTROL l~ RO-9, CO-9, BO, Bl and ECASO ADDRESS t.l[ 1 "" i~0-9, CO-9 +A23 t.AL CPU I/o PORT CPU Dl'842DA/21 A/22A and ECASO ADDRESS DP8420A/21 A/22A TL/F/8588-12 FIGURE 46c. Programming the DP8420Al21A122A through the Address Bus and an I/O Port Another simple way the chip can be programmed is the first write after system reset. This method requires only a flipflop and an OR gate as shown in Figure 46d. At reset, the flip-flop is preset, which pulls the Q output low. Since WR is negated, ML is not enabled. The first write access is used to program the chip. When WR is asserted, ML is asserted. WR negated clocks the flip-flop, negates ML, and programs the DPB420Al21A/22A with the address and ECASO available at that time. CS does not need to be asserted using this method. TL/FIB5BB-11 FIGURE 46b. Programming the DP8420A121A122A through the Address Bus Only An 1/0 port can also be used to assert ML. After ML is asserted, a chip selected access can be performed to program the chip. After the chip selected access, ML can be negated through the 1/0 port as shown in Figure 46c. SYSTEt.A RESET: RST_----, o PR CPU WRITE: RST Q DP8420A/21 A/22A iYR_.--I> ----' / TLiF/B5BB-14 FIGURE 46d. Programming the DP8420A/21A/22A on the Firat CPU Write after Power Up 1-139 ..... N "'" ..... > ..... C "'C (X) "'" N N > 8.0 Programming and Resetting (Continued) 8.3 PROGRAMMING BIT DEFINITIONS (Continued) Description Symbol R5,R4 WAIT/DTACK during Burst (See Section 5.1.2 or 5.2.2) 0,0 NO WAIT STATES; If R7 = 0 during programming, WAIT will remain negated during burst portion of access. If R7 = 1 programming, DTACK will remain asserted during burst portion of access. 0, 1 H; If R7 = 0 during programming, WAIT will assert when the ECAS inputs are negated with AREa asserted. WAIT will negate from the positive edge of CLK after the ECASs have been asserted. If R7 = 1 during programming, DTACK will negate when the ECAS inputs are negated with AREa asserted. DTACK will assert from the positive edge of CLK after the ECASs have been asserted. 1,0 %T; If R7 = 0 during programming, WAIT will assert when the ECAS inputs are negated with AREa asserted. WAIT will negate on the negative level of CLK after the ECASs have been asserted. If R7 = 1 during programming, DTACK will negate when the ECAS inputs are negated with AREQ asserted. DTACK will assert from the negative level of CLK after the ECASs have been asserted. 1, 1 OT; If R7 = 0 during programming, WAIT will assert when the ECAS inputs are negated. WAiT will negate when the ECAS inputs are asserted. If R7 = 1 during programming, DTACK will negate when the ECAS inputs are negated. DTACK will assert when the ECAS inputs are asserted. R3,R2 WAIT/DTACK Delay Times (See Section 5.1.1 or 5.2.1) 0,0 NO WAIT STATES; If R7 = 0 during programming, WAIT will remain high during non·delayed accesses. WAIT will negate when 'f'iAS is negated during delayed accesses. NO WAIT STATES; If R7 = 1 during programming, DTACK will be asserted when 'f'iAS is asserted. 0, 1 %T; If R7 = 0 during programming, WAiT will negate on the negative level of CLK, after the access 'f'iAS. 1T; If R7 = 1 during programming,l5i'ACK will be asserted on the positive edge of CLK after the access 'f'iAS. 1,0 NO WAIT STATES, %T; If R7 = 0 during programming, WAIT will remain high during non·delayed accesses. WAIT will negate on the negative level of CLK, after the access 'f'iAS, during delayed accesses. %T; If R7 = 1 during programming, DTACK will be asserted on the negative level of CLK after the access 'FiAS. 1, 1 1T; If R7 = 0 during programming, WAiT will negate on the positive edge of CLK after the access ~. 1%T; If R7 = 1 during programming, DTACK will be asserted on the negative level of CLK after the positive edge of CLK after the access 'f'iAS. 1·142 .-----------------------------------------------------------------------------'10 8.0 Programming and Resetting "tI 0) (Continued) .jlo. N 8.3 PROGRAMMING BIT DEFINITIONS (Continued) Symbol C » ...... Description o"tI R1, RO RAS Low and RAS Precharge Time 0,0 RAS asserted during refresh = 2 positive edges of CLK. RAS precharge time = 1 positive edge of CLK. RAS will start from the first positive edge of ClK after GRANTS transitions (DP8422A). 0,1 RAS asserted during refresh = 3 positive edges of ClK. RAS precharge time = 2 positive edges of ClK. RAS will start from the second positive edge of ClK after GRANTS transitions (DP8422A). 0) .jlo. 1,0 RAS asserted during refresh = 2 positive edges of ClK. RAS precharge time = 2 positive edges of ClK. RAS will start from the first positive edge of ClK after GRANTS transitions (DP8422A). 1, 1 RAS asserted during refresh = 4 positive edges of ClK. RAS precharge time = 3 positive edges of ClK. RAS will start from the second positive edge of ClK after GRANTS transitions (DP8422A). 10.2 CALCULATION OF tRAH AND tASC 9.0 Test Mode There are two clock inputs to the DP8420Al21 Al22A. These two clocks, DElClK and ClK can either be tied together to the same clock or be tied to different clocks running asynchronously at different frequencies. The clock input, DElClK, controls the internal delay line and refresh request clock. DElClK should be a multiple of 2 MHz. If DElClK is not a multiple of 2 MHz, tRAH and tASC will change. The new values of tRAH and tASC can be calculated by the following formulas: Staggered refresh in combination with the error scrubbing mode places the DP8420A/21A122A in test mode. In this mode, the 24·bit refresh counter is divided into a 13·bit and 11-bit counter. During refreshes both counters are incremented to reduce test time. 10.0 DRAM Critical Timing Parameters The two critical timing parameters, 3hown in Figure 47, that must be met when controlling the access timing to a DRAM are the row address hold time, tRAH, and the column address setup time, tASC. Since the DP8420Al21 Al22A contain a precise internal delay line, the values of these parameters can be selected at programming time. These values will also increase and decrease if DElClK varies from 2 MHz. If tRAH was programmed to equal 15 ns then tRAH = 30*«(DElClK Divisor)* 2 MHz/(DElClK Frequency»-1) + 15 ns. 10.1 PROGRAMMABLE VALUES OF tRAH AND tASC If tASC was programmed to equal 10 ns then tASC = 25 * «DElClK Divisor)* 2 MHz/(DElClK Frequency» - 15 ns. If tRAH was programmed to equal 25 ns then tRAH = 30*«(DElClK Divisor)* 2 MHz/(DElClK Frequency»-1) + 25 ns. If tASC was programmed to equal 0 ns then tASC = 15* «DElClK Divisor)* 2 MHz/(DElClK Frequency» - 15 ns. The DP8420A/21 A/22A allow the values of tRAH and tASC to be selected at programming time. For each parameter, two choices can be selected. tRAH, the row address hold time, is measured from RAS asserted to the row address starting to change to the column address. The two choices for tRAH are 15 ns and 25 ns, programmable through address bit C8. Since the values of tRAH and tASC are increased or decreased, the time to CAS asserted will also increase or decrease. These parameters can be adjusted by the following formula: Delay to CAS = Actual Spec. + Actual tRAH Programmed tRAH + Actual tASC - Programmed tASC. tASC, the column address setup time, is measured from the column address valid to CAS asserted. The two choices for tASC are 0 ns and 10 ns, programmable through address bit C7. OOUT ROW TLiF/8588-E3 FIGURE 47. tRAH and tASC 1-143 N ..... » ...... o"tI 0) .jlo. N N » suming that Port A is not accessing the DRAM «(;S, ADS/ ALE and AREQ) and RAS precharge for the particular bank has completed. It is important to note that for GRANTS to transition to Port S, Port A must not be requesting an access at a rising clock edge (or locked) and Port S must be requesting an access at that riSing clock edge. Port A can request an access through CS and ADS/ALE or CS and AREQ. Therefore during an interleaved access where CS and ~/ ALE become asserted before ~ from the previous access is negated, Port A will retain GRANTS = 0 whether AREQS is asserted or not. 11.0 Dual Accessing Functions (DP8422A) The DP8422A has all the functions previously described. In addition to those features, the DP8422A also has the capabilities to arbitrate among refresh, Port A and a second port, Port S. This allows two CPUs to access a common DRAM array. DRAM refresh has the highest priority followed by the currently granted port. The ungranted port has the lowest priority. The last granted port will continue to stay granted even after the access has terminated, until an access request is received from the ungranted port (see Figure 48a ). The dual access configuration assumes that both Port A and Port S are synchronous to the system clock. If they are not synchronous to the system clock they should be externally synchronized (Ex. Sy running the access requests through several Flip-Flops, see Figure 50a). Since there is no chip select for Port S, AREQS must incorporate this signal. This mode of accessing is similar to Mode 1 accessing for Port A. AREQAoARfQBo[OCj( 11.1 PORT B ACCESS MODES (DP8422A) Port S accesses are initiated from a single input, AREQS. When AREQS is asserted, an access request is generated. If G RANTS is asserted and a refresh is not taking place or precharge time is not required, RAS will be asserted when AREQS is asserted. Once AREQS is asserted, it must stay asserted until the access is over. AREQS negated, negates RAS as shown in Figure 48b. Note that if ECASO = 1 during programming the CAS outputs may be held asserted (beyond RASn negating) by continuing to assert the appropriate ECASn inputs (the same as Port A accesses). If Port S is not granted, the access will begin on the first or second positive edge of ClK after GRANTS is asserted (See RO, R1 programming bit definitions) as shown in Agure 48c, as- T1 TUF/8588-F9 Explanation of Terms ARECA ~ AREC8 ~ lOCK ~ Chip Selected access request from Port A Chip Selected access request from Port 8 Externally controlled lOCKing of the Port that is currently GRANTed. FIGURE 48a. DP8422A PORT A/PORT B ARBITRATION STATE DIAGRAM. This arbitration may take place during the "ACCESS" or "REFRESH" state (see Figure 7a ). T3 12 T4 elK TUF/B588-E4 FIGURE 48b. Access Request for Port B elK GRANTS _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- ' TL/F/8588-E5 FIGURE 48c. Delayed Port B Access 1-144 C 11.0 Dual Accessing Functions (DP8422A) "tI co (Continued) 11.2 PORT B WAIT STATE SUPPORT (DP8422A) ~ATACKB ~ro,~, Advanced transfer acknowledge for Port B, ATACKB, is used for wait state support for Port B. This output will be asserted when RAS for the Port B access is asserted, as shown in Figures 49a and 49b. Once asserted, this output will stay asserted until AREOB is negated. With external logic, ATACKB can be made to interface to any CPU's wait input as shown in Figure 49c. » ...... c"tI co "'" N L __________ CPU B CLOCK ATACKB TO CPU B C) Synchronize ATACKB to CPU B Clock. This is useful if CPU B runs asyn- "tI 11.3 COMMON PORT A AND PORT B DUAL PORT FUNCTIONS An input, LOCK, and an output, GRANTB, add additional functionality to the dual port arbitration logic. LOCK allows Port A or Port B to lock out the other port from the DRAM. When a Port is locked out of the DRAM, wait states will be inserted into its access cycle until it is allowed to access memory. GRANTB is used to multiplex the input control signals and addresses to the DP8422A. TLlF/8588-30 A) Extend ATACK to %T (% Clock) after RAS goes low. "~~"~' mo.", o 11.3.1 GRANTB Output Q The output GRANTB determines which port has current access to the DRAM array. GRANTB asserted signifies Port B has access. GRANTB negated signifies Port A has access to the DRAM array. ClK TL/F/8588-31 B) Extend AT ACK to 1T after RAS goes low. ClK -~ TL/F/8588-E6 FIGURE 49a. Non-Delayed Port B Access ClK GRANTB _ _ _ _ _ _ _ _ _- 1 TLlF/8588-E7 FIGURE 49b. Delayed Port B Access 1-145 c co FIGURE 49c. Modifying Wait Logic for Port B ClK-----I ~ TLiF 18588-32 » ...... chronous to the DP8422. MACKB~~--------------~ "'o" N "'" N N » 11.0 Dual Accessing Functions (DP8422A) (Continued) Since the DP8422A has only one set of address inputs. the signal is used. with the addition of buffers. to allow the cur· rently granted port's addresses to reach the DP8422A. The signals which need to be bufferred are RO-10. CO-1O. BO-1. ECASO-3. WE. and LOCK. All other inputs are not common and do not have to be buffered as shown in Figure 50a. If a Port. which is not currently granted. tries to access the DRAM array. the GRANTB output will transition from a rising clock edge from AREO or AREOB negating and will preceed the RAS for the access by one or two clock peri· ods. GRANTB will then stay in this state until the other port requests an access and the currently granted port is not accessing the DRAM as shown in Figure 50b. PORT A (SYNCHRONOUS) PORT B (SYNCHRONOUS or ASYNCHRONOUS) ClK. DElClK .c;:..:::::!..J ~="""'l'" CPU A rR::;D.:..;'if;;:R_...... ADDRESS 110-8.9.10 RASO - 3. CASO-3 ADDRESS. WE. COCK and ECASO-3 74.4S244 TRI-STATE ...---.... BUFFERS WE 74AS244 -t-----+-------='----1 TR1-STATE BUFFERS ADDRESS. WE. COCK and fCASo-3 DRAM CSB DATAENB ENB TA DATA TL/F/8588-55 ·If Port B is synchronous the Request Synchronizing logic will not be required. FIGURE 50a. Dual Accessing with the DP8422A (System Block Diagram) 1-146 C ." 11.0 Dual Accessing Functions (DP8422A) (Continued) co ~ N o ClK » ........ c V-t\ 1;-1\ ." co ~ .... N ~ C ." co I\, 1/ GRANTB ~ N N » i/ R/W PORT B DATA iUSn ECASO- 3 CASD- 3 VALID PORT A I ~ Ir\. 1/ ~ r\. 1/ - /I--~ ~ / 1/ PORT B ~ / "\.'::!!!, ADDRESS IN Tl/F/6568-29 FIGURE SOb. Walt States during a Port B Access 11.3.2 LOCK Input refreshes, it only keeps GRANTB in the same state even if the other port requests an access, as shown in Figure 51 s. [QCl< can be used by either port. When the IOCR input is asserted, the currently granted port can "lock out" the other port through the insertion of wait states to that port's access cycle. [QCl< does not disable ClK ADS AREQ lOCK \ \~____________________________-JI \ GRANTB AREQB \~--------------------------------------------------------------- ATACKB TLlF/8588-E8 FIGURE 51. LOCK Function 1-147 12.0 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. All Input or Output Voltage with Respect to GND ................... -0.5V to + 7V Power Dissipation @ 20 MHz ....................... 0.5W Temperature under Bias ................... O'C to + 70'C ESD Rating to be determined. Storage Temperature ................. - 65'C to + 150'C 13.0 DC Electrical Characteristics TA = Symbol Parameter O'Cto +70'C, Vce = 5V ±10%, GND = OV Conditions Min VIH logical 1 Input Voltage Tested with a Limited Functional Pattern VIL logical 0 Input Voltage Tested with a Limited Functional Pattern VOH1 a and WE Outputs IOH = -10 mA VOl1 a and WE Outputs IOL = 10 mA VOH2 All Outputs except as, WE IOH = -3 mA VOL2 All Outputs except as, WE IOL = 3mA liN Input leakage Current VIN = VCC or GND IlL ML Ml Input Current (low) VIN = GND lec1 Standby Current ClK at 8 MHz (VIN = Vce or GND) Typ Max Units 2.0 Vec + 0.5 V -0.5 0.8 V 0.5 V 0.5 V 10 /LA Vec - 1.0 V Vce - 1.0 -10 6 200 /LA 15 mA lec1 Standby Current ClK at 20 MHz (VIN = Vcc or GND) 8 17 mA Ice1 Standby Current ClK at 25 MHz (VIN = Vcc or GND) 10 20 mA lec2 Supply Current ClK at 8 MHz (Inputs Active) (lLOAD = 0) (VIN = Vcc or GND) 20 40 mA ICC2 Supply Current ClK at 20 MHz (Inputs Active) (I LOAD = 0) (VIN = Vcc or GND) 40 75 mA leC2 Supply Current ClK at 25 MHz (Inputs Active) (ILOAD = 0) (VIN = Vcc or GND) 50 95 mA 10 pF Input Capacitance CIN' 'Note: CIN Is not 100% tested. fiN at 1 MHz 14.0 AC Timing Parameters: DP8420A/DP8421A/DP8422A Two speed selections are given, the DP8420A/21A/22A-20 and the DP8420Al21 Al22A-25. The differences between the two parts are the maximum operating frequencies of the input ClKs and the maximum delay specifications. low frequency applications may use the "- 25" part to gain improved timing. 300-315 Mode 0 access parameters used in both single and dual access applications 400-416 Mode 1 access parameters used in both single and dual access applications 450-455 Special Mode 1 access parameters which supersede the 400-416 parameters when dual accessing The AC timing parameters are grouped into sectional numbers as shown below. These numbers also refer to the timing diagrams. 1-36 50-56 100-121 500-506 Programming parameters Unless otherwise stated Vec = 5.0V ±10%,O < TA < 70'C, the output load capacitance is typical for 4 banks of 18 DRAMs per bank, including trace capacitance (see Note 2). Common parameters to all modes of operation Difference parameters used to calculate; RAS low time, RAS precharge time, CAS high time and CAS low time Two different loads are specified: CL = 50 pF loads on all outputs except CL = 150 pF loads on 00-8, 9, 10 and WE; or Common dual access parameters used for Port B accesses and inputs and outputs used only in dual accessing CH = 50 pF loads on all outputs except CH = i25 pF ioads on RASO-3 and CASO-3 and CH = 380 pF loads on 00-8, 9, 10 and WE. 200-212 Refresh parameters 1-148 14.0 AC Timing Parameters: DP8420A/DP8421A/DP8422A (Continued) 8420A/21A/22A-20 Number Symbol Common Parameter Description CL 8420A/21A122A-25 CH CL CH Min Max Min Max Min Max Min Max 20 0 20 0 25 0 25 1 fClK ClK Frequency 0 2 tClKP ClK Period 50 50 40 40 3,4 tClKPW ClK Pulse Width 15 15 12 12 5 fDClK DElClK Frequency 5 20 5 20 5 20 5 20 6 tDClKP DElClK Period 50 200 50 200 50 200 50 200 7,8 tDClKPW DElClK Pulse Width 15 15 12 12 9a tPRASCASO RAS Asserted to CAS Asserted (tRAH = 15 ns, lASC = 0 ns) 30 30 30 30 9b tPRASCAS1 RAS Asserted to CAS Asserted (tRAH = 15 ns, tASC = 10 ns) 40 40 40 40 9c tPRASCAS2 (RAS Asserted to CAS Asserted (tRAH = 25 ns, tASC = 0 ns) 40 40 40 40 9d tPRASCAS3 (RAS Asserted to CAS Asserted (tRAH = 25 ns, tASC = 10 ns) 50 50 50 50 10a tRAH Row Address Hold Time (tRAH 10b tRAH Row Address Hold Time (tRAH 11a tASC Column Address Setup Time (lASC = 11b tASC Column Address Setup Time (tASC = 12 tPCKRAS ClK High to RAS Asserted following Precharge 27 32 22 26 13 tPARQRAS AREQ Negated to RAS Negated 38 43 31 35 27 = = 15) 15 15 15 15 25) 25 25 25 25 0) 0 0 0 0 10) 10 10 10 10 14 tPENCl ECASO-3 Asserted to CAS Asserted 23 31 20 15 tPENCH ECASO-3 Negated to CAS Negated 25 33 20 27 16 tPARQCAS AREQ Negated to CAS Negated 60 68 47 54 17 tPClKWH ClK to WAIT Negated 39 39 31 31 18 tPClKDlO ClK to DTACK Asserted (Programmed as DTACKof 1/2,1,1% or if WAITIN is Asserted) 33 33 28 28 44 44 36 36 19 tPEWl ECAS Negated to WAIT Asserted during a Burst Access 20 tSECK ECAS Asserted Setup to ClK High to Recognize the Rising Edge of ClK during a Burst Access 24 24 19 19 • I 1-149 14.0 AC Timing Parameters: DP8420A/DP8421A/DP8422A (Continued) Unless otherwise stated Vee = 5.0V ± 10%, O"C < TA per bank, Including trace capacitance (see Note 2). Two different loads are specified: CL - 50 pF loads on all outputs except CL = 150 pF loads on QO-8, 9, 10 and WEi or < 70'C, the output load capacitance Is typical for 4 banks of 18 DRAMs CH = 50 pF loads on all outputs except CH .. 125 pF loads on mO-3 and ~-3 and CH - 380 pF loads on QO-8, 9, 10 and WE. 8420Al21A/22A·20 Number Symbol Common Parameter Delcrlptlon CL Min 21 tPEDL tPEDH CH Min Max CL Min CH Max Min MIX ~ AS8erted to t:5TAC"R Asserted during a Burst Accese (Programmed ae t:5TAC"RO) 22 Max 8420A/21A122A·a5 ~ Negated to t:5TAC"R Negated during a Buret Access 48 48 38 38 49 49 38 38 24 WAITIfiI Asserted Setup to CLK tPWINWEH WiN Asserted to WE Asserted 34 44 27 37 25 tPWINWEL WiN Negated to WE Negated 34 44 27 37 26 tPAQ Row, Column Address Valid to QO-8, 9, 10 Valid 29 38 26 35 27 tPCINCQ COLINC Asserted to QO-6, 9, 10 Incremented 34 43 30 39 28 tSCINEN COLINC Aaserted Setup to E'CAS Asserted to Ensure tASC = 0 ns 29a tSARQCK1 AREC:i, AI1EQB Negated Setup to ClK 23 tSWCK 5 5 High with 1 Period of Precharge AREQ, AREQS Negated Setup to ClK High with> 1 Period of Precharge Programmed 5 5 18 19 17 19 46 46 37 37 19 19 15 15 29b tSARQCK2 30 tPAREQDH AREQ Negated to DTACk Negated 31 tPCKCAS ClK High to CAS Asserted when Delayed by WiN 32 tSCADEN Column Address Setup to ECAS Asserted to Guarantee tASC = 0 14 15 14 16 33 tWCINC COLINC Pulse Width 20 20 20 20 34a tPCKClO ClK High to CAS Asserted following Precharge (tRAH = 15 ns, tASC = 0 ns) 81 89 72 79 34b tPCKCl1 ClK High to CAS Asserted following Precharge (tRAH = 15 ns, tASC = 10 ns) 91 99 82 89 34c tPCKCl2 ClK High to CAS Asserted following Precharge (tRAH = 25 ns, tASC = 0 ns) 91 99 82 89 34d tPCKCl3 ClK High to CAS Asserted following Precharge (tRAH = 25 ns, tASC = 10 ns) 101 109 92 99 35 tCAH Column Address Hold Time (Interleave Mode Only) 36 tPCQR CAS Asserted to Row Address 34 34 27 27 31 39 25 32 32 32 90 Valid (Interleave Mode Only) 1-150 32 32 90 90 90 14.0 AC Timing Parameters: DP8420A/DP8421A/DP8422A (Continued) Unless otherwise stated Vee = 5.0V ± 10%, O'C < T A per bank, including trace capacitance (see Note 2). Two different loads are specified: CL = 50 pF loads on all outputs except CL = 150 pF loads on QO-8, 9,10 and WE; or < 70'C, the output load capacitance is typical for 4 banks of 18 DRAMs CH = 50 pF loads on all outputs except CH = 125 pF loads on RASO-3 and c.as0-3 and CH = 380 pF loads on QO-8, 9, 10 and WE. 8420A/21A122A·25 8420A/21A122A·20 Number Symbol Difference Parameter Description Min 50 tD1 CH CL Max Min CH CL Max Min Max Min Max (AREa or AREQS Negated to RAS Negated) Minus (CLK High to RAS Asserted) 16 16 14 14 51 tD2 (CLK High to Refresh ~ Negated) Minus (CLK High to ~ Asserted) 13 13 11 11 52 tD3a (ADS Asserted to RAS Asserted (Mode 1» Minus (AREQ Negated to RAS Negated) 4 4 4 4 4 4 4 4 53 tD3b (CLK High to ~ Asserted (Mode 0» Minus (AREa Negated to RAS Negated) 54 tD4 (ECAS Asserted to CAS Asserted) Minus (ECAS Negated to CAS Negated) 55 tD5 (CLK to Refresh RAS Asserted) Minus (CLK to Refresh RAS Negated) 6 6 6 6 56 tD6 (AREa Negated to RAS Negated) Minus (ADS Asserted to RAS Asserted ((Mode 1» 12 12 10 10 -7 1·151 7 -7 7 -7 7 -7 7 14.0 AC Timing Parameters: DP8420A/DP8421A/DP8422A (Continued) Unless otherwise stated Vee = 5.0V ± 10%, O°C < TA per bank, including trace capacitance (see Note 2). Two different loads are specified: CL = 50 pF loads on all outputs except CL = 150 pF loads on 00-8, 9, 10 and WE; or < 70"C, the output load capacitance is typical for 4 banks of 18 DRAMs CH CH CH = = = 50 pF loads on all outputs except 125 pF loads on RASO-3 and CASO-3 and 380 pF loads on QO-8, 9, 10 and WE. 8420Al21A122A-20 Number Common Dual Access Parameter Description Symbol Min 8420Al21A122A-25 CH CL Max Min CL Max Min CH Max Min Max 100 tHCKARQS AREQS Negated Held from ClK High 3 101 tSARQSCK AREQS Asserted Setup to ClK High 8 102 tPAQSRASl AREQS Asserted to RAS Asserted 43 48 37 41 103 tPAQSRASH AREQS Negated to RAS Negated 41 46 32 36 105 tPCKRASG ClK High to RAS Asserted for Pending Port S Access 55 60 44 48 106 tPAQSATKSl AREQS Asserted to ATACKS Asserted 57 57 45 45 107 tPCKATKS ClK High to ATACKS Asserted for Pending Access 67 67 51 51 108 tPCKGH ClK High to GRANTS Asserted 40 40 32 32 109 tPCKGl ClK High to GRANTS Negated 35 35 29 29 110 tSADDCKG Row Address Setup to ClK High That Asserts RAS following a GRANTS Change to Ensure lASR = 0 ns for Port S 11 15 11 16 lOCK Asserted Setup to ClK low to lock Current Port 5 5 5 5 111 tSlOCKCK 3 3 8 3 7 7 112 tPAQATKSH AREQ Negated to ATACKS Negated 26 26 21 21 113 tPAQSCASH AREQS Negated to CAS Negated 59 67 47 54 114 tSADAQS Address Valid Setup to AREQS Asserted 7 11 7 12 116 tHCKARQG AREQ Negated Held from ClK High 5 5 5 5 117 tWAQS AREQS High Pulse Width to Guarantee tASR = 0 ns 31 35 26 31 118a tPAQSCASO AREQS Asserted to CAS Asserted (tRAH = 15 ns, tASC = 0 ns) 103 111 87 94 118b tPAQSCAS1 AREQS Asserted to CAS Asserted (tRAH = 15 ns, tASC = 10 ns) 113 121 97 104 118c tPAQSCAS2 AREQS Asserted to CAS Asserted (tRAH = 25 ns, lASC = 0 ns) 113 121 97 104 118d tPAQSCAS3 AREQS Asserted to CAS Asserted (tRAH = 25 ns, tASC = 10 ns) 123 131 107 114 120a tPCKCASGO ClK High to CAS Asserted for Pending Port S Access (tRAH = 15 ns, tASC = 0 ns) 113 121 96 103 ClK High to CAS Asserted for Pending Port S Access (tRAH = 15 ns, tASC = 10 ns) 123 131 106 113 ClK High to CAS Asserted for Pending Port S Access (tRAH = 25 ns, tASC = 0 ns) 123 131 106 113 133 141 116 123 120b 120c 120d tPCKCASG1 tPCKCASG2 tPCKCASG3 ClK High to CAS Asserted for Pending Port B Access (tRAH 121 tSSADDCKG = 25 ns, tASC = 10 ns) Sank Address Valid Setup to ClK High That Starts RAS for Pending Port S Access 10 1-152 10 10 10 14.0 AC Timing Parameters: DP8420A/DP8421 A/DP8422A Unless otherwise stated Vee = 5.0V ± 10%, O·C < TA per bank, including trace capacitance (see Note 2). (Continued) < 70·C, the output load capacitance is typical for 4 banks of 18 DRAMs Two different loads are specified: CL = 50 pF loads on all outputs except CL = 150 pF loads on 00-8, 9, 10 and WE; or CH CH CH = 50 pF loads on all outputs except = 125 pF loads on RASO-3 and CASO-3 and = 380 pF loads on 00-8, 9, 10 and WE. 8420Al21A/22A-20 Number Symbol Refresh Parameter Description CL Min 200 tSRFCK 201 202 8420A/21A/22A-25 CH Max Min CL Max Min CH Max Min Max RFSH Asserted Setup to ClK High 27 27 22 22 tSDRFCK DISRFSH Asserted Setup to ClK High 28 28 22 22 tSXRFCK EXTENDRF Setup to ClK High 15 15 12 12 204 tPCKRFl ClK High to RFIP Asserted 39 39 31 31 205 tPARORF AREO Negated to RFIP Asserted 62 62 50 50 206 tPCKRFH ClK High to RFIP Negated 65 65 51 51 207 tPCKRFRASH ClK High to Refresh RAS Negated 35 40 29 33 208 tPCKRFRASl ClK High to Refresh RAS Asserted 28 33 23 27 209a tPCKClO ClK High to CAS Asserted during Error Scrubbing (tRAH = 15 ns, tASC = 0 ns) 82 90 73 80 ClK High to CAS Asserted during Error Scrubbing (tRAH = 15 ns, tASC = 10 ns) 92 100 83 90 ClK High to CAS Asserted during Error Scrubbing (tRAH = 25 ns, tASC = 0 ns) 92 100 83 90 ClK High to CAS Asserted during Error Scrubbing (tRAH = 25 ns, tASC = 10 ns) 102 110 83 100 209b 209c 209d tPCKCl1 tPCKCl2 tPCKCl3 210 tWRFSH RFSH Pulse Width 211 tPCKROl ClK High to RFRQ Asserted 46 46 40 40 212 tPCKROH ClK High to RFRO Negated 50 50 40 40 15 1-153 15 15 15 14.0 AC Timing Parameters: DP8420A/DP8421A/DP8422A (Continued) Unless otherwise stated Vee = 5.0V ± 10%, O'C < TA per bank, including trace capacitance (see Note 2). Two different loads are specified: CL = 50 pF loads on all outputs except CL = 150 pF loads on 00-8, 9, 10 and < 70'C, the output load capacitance is typical for 4 banks of 18 DRAMs CH = 50 pF loads on all outputs except CH = 125 pF loads on ~-3 and ~0-3 and CH = 380 pF loads on 00-8, 9, 10 and WE. WE; or 8420Al21A/22A-20 Number Symbol Mode 0 Access Parameter Description CL Min 8420A/21A122A-25 CH Max Min CH CL Max Min Max Min 300 tSCSCK OS Asserted to ClK High 14 14 13 13 301a tSAlECKNl ALE Asserted Setup to ClK High Not Using On-Chip latches or if Using On-Chip latches and BO, Bl, Are Constant, Only 1 Bank 16 16 15 15 ALE Asserted Setup to ClK High, if Using On-Chip latches if BO, B1 Can Change, More Than One Bank 29 29 29 29 301b tSAlECKl 302 tWAlE ALE Pulse Width 16 18 13 13 303 tSBADDCK Bank Address Valid Setup to ClK High 20 20 18 18 304 tSADDCK Row, Column Valid Setup to ClK High to Guarantee tASR = 0 ns 11 15 11 16 Row, Column, Bank Address Held from ALE Negated (Using On-Chip latches) 10 10 8 8 Row, Column, Bank Address Setup to ALE Negated (Using On-Chip latches) 3 3 2 2 305 306 tHASRCB tSRCBAS Max 307 tPCKRl ClK High to RAS Asserted 27 32 22 26 308a tPCKClO ClK High to ~ Asserted (tRAH = 15 ns, tASC = 0 ns) 81 89 72 79 308b tPCKCl1 ClK High to CAS Asserted (tRAH = 15 ns, tASC = 10 ns) 91 99 82 89 308c tPCKCl2 ClK High to CAS Asserted (tRAH = 25 ns, tASC = 0 ns) 91 99 82 89 308d tPCKCl3 ClK High to ~ Asserted (tRAH = 25 ns, IASC = 10 ns) 101 109 92 99 309 tHCKAlE ALE Negated Hold from ClK High 0 0 0 0 310 tSWINCK WIN Asserted Setup to ClK High to Guarantee CAS is Delayed -21 -21 -16 -16 311 tPCSWl CS Asserted to WAIT Asserted 26 26 22 22 312 tPCSWH CS Negated to WAIT Negated 30 30 25 25 313 tPClKDll ClK High to DTACK Asserted (Programmed as DTACKO) 40 40 32 32 314 tPAlEWl ALE Asserted to WAIT Asserted (CS is Already Asserted) 35 35 29 29 315 316 AREa Negated to ClK High That Starts Access RAS to Guarantee tASR = 0 ns (Non-Interleaved Mode Only) tpCKCVO ClK High to Column Address Valid (tRAH = 15 ns, IASC = 0 nsi 41 45 78 1-154 34 87 39 66 75 14.0 AC Timing Parameters: OP8420A/OP8421A/OP8422A (Continued) Unless otherwise stated Vee = 5.0V ± 10%, O'C < TA < 70'C, the output load capacitance is typical for 4 banks of 18 DRAMs per bank, including trace capacitance (see Note 2). Two different loads are specified: CH = 50 pF loads on ali outputs except CL = 50 pF loads on ali outputs except CH = 125 pF loads on ~0-3 and 0AS0-3 and CH = 380 pF loads on 00-8, 9, 10 and WE. CL = 150 pF loads on 00-8, 9, 10 and WE; or 8420A/21A122A·20 Number Symbol Model Acce•• Parameter Description CL Min 400a 400b AOS Asserted Setup to elK High tSADSCKW AOS Asserted Setup to ClK (to Guarantee Correct WAf"r tSADSCK1 8420Al21A/22A·25 CH Max Min CL Max Min CH Max Min 15 15 13 13 31 31 25 25 Max or riTAOR Output; Doesn't Apply for riTAORO) 401 tSCSADS 402 tPADSRl 403a tPADSCLO 403b tPADSCL 1 403c ~ Setup to Al5S Asserted A!5S Asserted to ~ Asserted A!5S Asserted to OAS Asserted (tRAH = 15 ns, tASC = 0 ns) 6 5 6 5 30 35 25 29 86 94 75 82 ADS Asserted to CAS Asserted (tRAH = 15 ns, tASC = 10 ns) 96 104 85 92 tPADSCL2 ADS Asserted to CAS Asserted (tRAH = 25 ns, tASC = 0 ns) 96 104 85 92 403d tPADSCL3 ADS Asserted to CAS Asserted (tRAH = 25 ns, tASC = 10 ns) 106 114 95 102 404 tSADDADS Row Address Valid Setup to ADS Asserted to Guarantee tASR = 0 ns 9 13 9 14 405 tHCKADS ADS Negated Held from CLK High 0 0 0 0 406 tSWADS WAITIN Asserted Setup to ADS Asserted to Guarantee DTACKO Is Delayed 0 0 0 0 407 tSBADAS Bank Address Setup to ADS Asserted 11 11 11 11 408 tHASRCB Row, Column, Bank Address Held from ADS Asserted (Using On-Chip Latches) 10 10 10 10 409 tSRCBAS Row, Column, Bank Address Setup to ADS Asserted (Using On-Chip Latches) 3 3 2 2 410 tWADSH ADS Negated Pulse Width 12 16 12 17 411 tPADSD ADS Asserted to DTACK Asserted (Programmed as DTACKO) 412 tSWINADS WIN Asserted Setup to ADS Asserted (to Guarantee CAS Delayed during Writes Accesses) 413 tPADSWLO 43 43 -10 35 -10 -10 35 -10 ADS Asserted to WAIT Asserted (Programmed as WAITO, Delayed Access) 35 35 29 29 414 tPADSWL1 ADS Asserted to WAIT Asserted (Programmed WAIT 112 or 1) 35 35 29 29 415 tPCLKDL1 CLK High to DTACK Asserted (Programmed as DTACKO, Delayed Access) 40 40 32 32 416 417 AREa Negated to ADS Asserted to Guarantee tASR = 0 ns (Non Interleaved Mode Only) tPADSCVO 42 38 ADS Asserted to Column Address Valid (tRAH = 15 ns, tAse = 0 ns) 83 1-155 31 92 36 69 78 III I 14.0 AC Timing Parameters: DP8420A/DP8421A/DP8422A (Continued) Unless otherwise stated Vee = 5.0V ± 10%, O'C < T A per bank, including trace capacitance (see Note 2). < 70'C, the output load capacitance is typical for 4 banks of 18 DRAMs Two different loads are specified: CL = 50 pF loads on all outputs except CL = 150 pF loads on 00-8, 9,10 and WE; or CH = 50 pF loads on all outputs except CH = 125 pF loads on RASO-3 and CASO-3 and CH = 380 pF loads on 00-8, 9, 10 and WE. 8420Al21A122A-20 Number Symbol Mode 1 Dual Access Parameter Description CL Min 450 tSADDCKG Row Address Setup to CLK High That Asserts RAS following a GRANTB Port Change to Ensure tASR = 0 ns 8420Al21A122A-25 CH Max 11 Min CL Max 15 Min CH Max 11 Min Max 16 451 tPCKRASG CLK High to RAS Asserted for Pending Access 48 53 38 42 452 tPCLKDL2 CLK to DTACK Asserted for Delayed Accesses (Programmed as DTACKO) 53 53 43 43 453a tPCKCASGO CLK High to CAS Asserted for Pending Access (tRAH = 15 ns, tASC = 0 ns) 101 109 86 93 CLK High to CAS Asserted for Pending Access (tRAH = 15 ns, IASC = 10 ns) 111 119 96 103 CLK High to CAS Asserted for Pending Access (tRAH = 25 ns, tASC = 0 ns) 111 119 96 103 CLK High to CAS Asserted for Pending Access (tRAH = 25 ns, tASC = 10 ns) 121 129 106 113 453b 453c 453d tPCKCASG1 tPCKCASG2 tPCKCASG3 454 tSBADDCKG Bank Address Valid Setp to CLK High That Asserts RAS for Pending Access 5 5 4 4 455 tSADSCKO ADS Asserted Setup to CLK High 12 12 11 11 8420Al21A122A-20 Number Symbol Programming Parameter Description CL Min 8 8420A/21A122A-25 CH Max Min 8 CH CL Max Min 7 Max Min 500 tHMLADD Mode Address Held from ML Negated 501 tSADDML Mode Address Setup to ML Negated 6 6 6 6 502 tWML ML Pulse Width 15 15 15 15 503 tSADAOML Mode Address Setup to AREO Asserted 0 0 0 0 504 tHADAOML Mode Address Held from AREO Asserted 51 51 38 38 505 tSCSARO CS Asserted Setup to AREO Asserted 6 6 6 6 506 tSMLARO ML Asserted Setup to AREO Asserted 10 10 10 10 Max 7 Note 1: "Absolute Maximum Ratings" are the values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation. Note 2: Input pulse ov to 3V; tR = tF = 2.5 ns. Input reference point on AC measurements is 1.5V. Output reference points are 2.4V for High and a.BV for Low. Note 3: AC Production testing is done at 50 pF. 1-156 C "tJ OCI 14.0 AC Timing Parameters: OP8420A/OP8421A/OP8422A (Continued) ~ N ~ ...... 71HB.~ M \ C 6 DElClK "tJ OCI ~ ~ ....» N ...... c "tJ OCI ~ ClK N N » TL/F/BSBB-ES FIGURE 52. Clock, DELCLK Timing ClK GRANTS RAsn RO-B,9,10 ............................. }--+-+-----+...... CO-BB~:k~ .t::.I.~~~'l,C,J"_-_+--+--.,;,;,::....--+....J~~(Y~_+----.,;,;,::....----J\,~~~~ CASn ECASn TL/F/BS88-FO FIGURE 53. 100: Dual Access Port B 1-157 DP8420A/DP8421A/DP8422A .... 0l:Io ClK b AREQB l> o ATACKB -I 3" 103 RAS 5" 109 eQ 400 '"': 0 AREQ I " S» 29 Dl 1 3 «030, CD CD DTACK 19 !i! RAS TLlF/8588-Fl c " FIGURE 54. 100: Port A and Port B Dual Access Q) 0l:Io N o CLK l> ....... C 01 0> " AREQ Q) 0l:Io N .... RF1P l> QlHl.9.1O IYYYYY' I u_ n . . n __ . . n_n ....... C I ___NV'fYYY'/Y" " Q) 0l:Io N N RASn l> '0 o IlIS1IfSH :::J g. C (!) S RFSH EXlENIlRF TLlF/8588-F2 FIGURE 55. 200: Refresh Timing o ." 14.0 AC Timing Parameters: DP8420A/DP8421A/DP8422A ClK ALE ~ 300 m BO,BI -- ~ ru\...J ru\...J ~ ~ ~ 302 ~ ...... o ." (1) _-:::1 I\XXXXXt 300 Y.'ll!lb. -........... o ." (1) ".. N N » VAllO 304 ............... ~ 3071:=-, 9- t I---- 308 CASn 29 L-.J _18 - 12 ~ -15f: -\ - I f_ \ 18 ~ 30r- t t -- H It -f - VALID 161- ~ 311 ~ XXXXXX -........... VALID r-- I-- 303 f-- ~ » ...... ~ VAllO r-- n.-rv- ..... ,.- i03 I-- 364 ".. N ".. N )IDe _ RO-8,9,10 CO-8,9,10 (1) (Continued) I~ --1 f 17 171-- f \ 1f f It _19 ~ H 17 + t I t I-- --\241-- t - I---- 261--00-8,9,10 XxXXxx. \ 316 f 1 ROW 25 r - I .------. COlU~N AX.X.XJ<.XXXXXX - I ROW COLUMN 20 _ \ ~ Tl/F/8588-F3 FIGURE 56. 300: Mode 0 Timing 1·159 • I ~ ~ co 14.0 AC Timing Parameters: DP8420A/DP8421A/DP8422A (Continued) a. c :c.,.. N 00:1' co a. a.K ALE c...... ~ AREQ 00:1' f c RASa CASO 316 35 00-8.9.10 RASI CASI RAS2 CAS2 80 81 CS TL/F/8588-F4 (Programmed as C4 ~ 1. C5 ~ 1. C6 ~ 1) FIGURE 57. 300: Mode 0 Interleaving 1·160 .-----------------------------------------------------------------------,0 "0 14.0 AC Timing Parameters: DP8420A/DP8421A/DP8422A (Continued) (II) "'" N ~ ..... elK o "0 (II) "'" N ...... » ..... o "0 (II) "'" N N » + __"'"t_---'y--------_I.A0£:~~~~~ QO-B,9,10.D/,,~~~_~-.-Jr_ _ _ CASn RO-B,9,10 ~""J!"'l~J:----------""\ CO-B,9,10 BO,Bl ~------------------~I FIGURE 58. 400: Mode 1 Timing 1-161 TLIF/8588-F5 ~ ~ 14.0 AC Timing Parameters: DP8420A/DP8421A/DP8422A (Continued) CO Q. C :( ,... ClK N -:t CO ADS Q. C 29 ...... '"CJ c oC') '" c c...5 ., CJ '" 1$ ~!~ CO ll ... z: o ;:; CJ ~ 0 > CJ C> 1 68 67 66 65 64 63 62 61 Rl 10 I\) ..... 60 WAlliN Cl 11 59 ClRF 58 DISRFSH 57 DElClK 56 ClK 55 Vee 54 COLINC 53 GND NS32CGB21 52 tiC 51 GND 50 CAP 49 Vee 48 CS 47 lSO 46 WIN 45 CAS3 44 CAS2 32 33 34 35 36 37 38 39 40 41 42 43 c o '" '" ~ ?I~ 15 I~!~ 1~ 1~ 1~ 1-~ 0 TLlFll0126-2 Top View FIGURE 2 Order Number NS32CG821V-20 or NS32CG821V-25 See NS Package Number V68A Cnl~--------------------------~~ ClK DElClK WAIT ~O~----------------------------~ TSO ~~----------------------------~ WIN 00-9 RASO-3 CASO-3 CS,tiC NS32CG16 RO-9 WE ~-----. . .~ CO-9 BO,Bl AI6-231-. .- - - - -. . . HBE~--------------.-------------~ ECAS1,3 -"'M AO ECASO,2 ADO-15~. . DRAM ARRAY (up \0 5MB) NS32CG821 ~~--------------------~AlE data bus TLlFll0126-48 "'Standard components in any NS32CG16 design FIGURE 3. NS32CG16-NS32CG821 Connection Diagram (Note 1) Note 1: This is only one possible way to connect the NS32CG821. See Sections 7 and 8 for additional options and configurations for hookup. 1·167 2.0 Signal Descriptions Pin Name I Output Input! I Description 2.1 ADDRESS, R/W AND PROGRAMMING SIGNALS RO-9 I ROW ADDRESS: These inputs are used to specify the row address during an access to the DRAM. They are also used to program the chip when M l is asserted (except R 10). CO-9 I COLUMN ADDRESS: These inputs are used to specify the column address during an access to the DRAM. They are also used to program the chip when Ml is asserted (except C1 0). BO,B1 I BANK SELECT: Depending on programming, these inputs are used to select a group of RAS and CAS outputs to assert during an access. They are also used to program the chip when Ml is asserted. ECASO-3 I ENABLE CAS: These inputs are used to enable a single or group of CAS outputs when asserted. In combination with the BO, B1 and the programming bits, these inputs select which CAS output or CAS outputs will assert during an access. The ECAS signals can also be used to toggle a group of CAS outputs for page mode accesses. They also can be used for byte write operations. WIN I WRITE ENABLE IN: This input is used to signify a write operation to the DRAM. The WE output follows this input. This input asserted will also cause CAS to delay to the next positive clock edge if address bit C9 is asserted during programming. COLINC I COLUMN INCREMENT: When the address latches are used, this input functions as COLINC. Asserting this signal causes the column address to be incremented by one. ML I MODE LOAD: This input signal, when low, enables the internal programming register that stores the programming information. 2.2 DRAM CONTROL SIGNALS 00-9 0 DRAM ADDRESS: These outputs are the multiplexed output of the RO-9 and CO-9 and form the DRAM address bus. These outputs contain the refresh address whenever refreshing is taking place. They contain high capacitive drivers with 200 series damping resistors. RASO-3 0 ROW ADDRESS STROBES: For an access, these outputs are asserted to latch the row address contained on the outputs 00-9 into the DRAM. For refreshing, the RAS outputs are used to latch the refresh row address contained on the 00-9 outputs in the DRAM. These outputs contain high capacitive drivers with 200 series damping resistors. CASO-3 0 COLUMN ADDRESS STROBES: These outputs are asserted to latch the column address contained on the outputs 00-9 into the DRAM. These outputs have high capacitive drivers with 200 series damping resistors. WE 0 WRITE ENABLE: This output asserted specifies a write operation to the DRAM. When negated, this output specifies a read operation to the DRAM. This output has a high capacitive driver and a 200 series damping resistor. 2.3 REFRESH SIGNALS CLRF I CLEAR REFRESH: This pin, in conjunction with DISRFSH is used to clear the internal refresh counter. DISRFSH I DISABLE REFRESH: When asserted with M L asserted for 16 positive edges of clock, the entire chip is reset and when negated with CLRF asserted clears the internal refresh address counter. 2.4 MEMORY ACCESS ALE I ADDRESS LATCH ENABLE: When ALE asserted along with CS causes an internal latch to be set. Once this latch is set and precharge time has been met an access will start from the positive clock edge of ClK as soon as possible. If Address latch (Bo = 0) is programmed, the low going edge of this signal latches the bank, row, and column address. CS I CHIP SELECT: This input signal must be asserted to enable an access. TSO I TIMING STATE OUTPUT: This input signal must be asserted some time after the first positive clock edge after ALE has been asserted. When this signal is negated, RAS is negated for the access. 1·168 z en w N o 2.0 Signal Descriptions (Continued) Pin Name Iinputl I Output Description ...... 2.4 MEMORY ACCESS (Continued) WAIT WAITIN G> QO N 0 WAIT: This output can be programmed to insert wait states into a CPU access cycle. This signal can be delayed by a number of positive clock edges or negative clock levels of ClK, depending on how it is programmed, to increase the microprocessor's access cycle through the insertion of wait states. I WAIT INCREASE: This input can be used to dynamically increase the number of positive clock edges of ClK until WAIT will be negated during a DRAM access. 2.5 POWER SIGNALS AND CAPACITOR INPUT Vee I POWER: Supply Voltage. GND I GROUND: Supply Voltage Reference. CAP I CAPACITOR: This input is used by the internal Pll for stabilization. The value of the ceramic capacitor should be 0.1 /LF and should be connected between this input and ground. 2.6 CLOCK INPUTS There are two clock inputs to the NS32CG821, ClK and DElClK. These two clocks may both be tied to the same clock input, or they may be two separate clocks, running at different frequencies, asynchronous to each other. ClK I SYSTEM CLOCK: This input may be in the range of 0 Hz up to 25 MHz. This input is generally a constant frequency but it may be controlled externally to change frequencies or perhaps be stopped for some arbitrary period of time. This input provides the clock to the internal state machine that arbitrates between accesses and refreshes. This clock's positive edges and negative levels are used to extend the WAIT signal. This clock is also used as the reference for the RAS precharge time and RAS low time during refresh. All memory accesses are assumed to be synchronous to the system clock ClK. DElCLK I DELAY LINE CLOCK: The clock input DElCLK, may be in the range of 6 MHz to 20 MHz and should be a multiple of 2 (i.e., 6, 8, 10, 12, 14, 16, 18, 20 MHz) to have the NS32CG821 switching characteristics hold. If DElClK is not one of the above frequencies the accuracy of the internal delay line will suffer. This is because the phase locked loop that generates the delay line assumes an input clock frequency of a multiple of 2 MHz. For example, if the DElCLK input is at 7 MHz and we choose a divide by 3 (program bits CO-2) this will produce 2.333 MHz which is 16.667% off of 2 MHz. Therefore, the NS32CG821 delay line would produce delays that are shorter (faster delays) than what is intended. If divide by 4 was chosen the delay line would be longer (slower delays) than intended (1.75 MHz instead of 2 MHz). (See Section 10 for more information.) This clock is also divided to create the internal refresh clock. 3.0 Memory Access An access to DRAM is initiated by two input signals: ALE and CS. The access is always terminated by one signal: TSO. These input signals should be synchronous to the in· put clock, ClK. Once an access has been requested by CS and ALE, the NS32CG821 will guarantee the following: The NS32CG821 will guarantee the minimum row address hold time, before switching the internal multiplexer to place the column address on the DRAM address bus, 00-9; The NS32CG821 will guarantee the minimum column ad· dress setup time before asserting the appropriate CAS or CASs; The NS32CG821 will have the row address valid to the DRAMs' address bus, 00-9 given that the row address setup time to the NS32CG821 was met; The NS32CG821 will hold the column address valid the minimum specified column address hold time. The NS32CG821 will bring the appropriate RAS or RASs low; The memory access shown in Figure 4 is selected by negating the input B 1 during programming. This access mode al- 1-169 • I ~ ~ z~ r------------------------------------------------------------------------------------------, 3.0 Memory Access (Continued) elK ALE 00-9 ________ ,~ __ ~ ____I ,____OO __ lU_M_N__________________ ~,~ ______ TLlF/l0126-3 FIGURE 4. Memory Access Sometime after the first positive edge of ClK after ALE and lows accesses to DRAM to always be initiated from the positive edge of the system input clock, ClK. To initiate an access, ALE is pulsed high and CS is asserted. Pulsing ALE high and asserting CS, sets an internal latch which requests an access. If the precharge time from the last access or DRAM refresh had been met and a refresh of DRAM was not in progress, the RAS or group of RASs would be initiated from the first positive edge of ClK. If a DRAM refresh is in progress or precharge time is required, the controller will wait until these events have taken place and assert RAS on the next positive edge of ClK. CS have been asserted, the input TSO must be asserted. Once TSO has been asserted, CS can be negated. Once TSO is negated, RAS and CAS will be negated. ALE can stay asserted several periods of ClK. However, ALE must be negated before or during the period of ClK in which TSO is negated. There are 2 methods by which this chip can be used to do read-modify-write access cycles. The first method involves doing a late write access where the WIN input is asserted some delay after CAS is asserted. The second method involves dOing a page mode read access followed by a page mode write access with RAS held low (see Figure 5). Once ALE and CS are both asserted, WAIT is asserted, unless WAIT is programmed as OT and a non-delayed access occurs, and follows CS until the rising clock edge. This is not a problem since the 32CG16 will not process the WAIT signal until the end of state T2. WAIT only has to guarantee that it meets the setup time to this edge of ClK on which it is sampled. READ MTA WRITE MTA M~_----------------~~~~~----~c:~~~:>-------- (dram) WRITE CYCLE READ CYCLE *There may be idle states inserted here by the CPU. TL/F/l0126-5 FIGURE 5. Read-Modify-Write Access Cycle 1-170 r---------------------------------------------------------~z en 3.0 Memory Access Co) (Continued) CASn must be toggled using the ECASn inputs and WiN has to be changed from negated to asserted (read to write) while CAS is negated. This method is better than changing WIN from negated to asserted in a late write access because here a problem may arise with DATA IN and DATA OUT being valid at the same time. This may result in a data line trying to drive two different levels simultaneously. The page mode method of a read-modify-write access allows the user to have transceivers in the system because the data in (read data) is guaranteed to be high impedance during the time the data out (write data) is valid. ~ N .... AClpOIRFRQ TL/F/l0126-6 Explanation of Terms IRFRO IRFIP = Internal ReFresh ReQuest of the NS32CG821. IRFRO has the ability to hold off a pending access. = Internal ReFresh In Progress ACIP = ACcess In Progress. This means that e~her RAS is low for an access or is in the process of transitioning low for an access. 4.0 Refresh Options FIGURE 6. NS32CG821 Acce88!Refresh Arbitration State Program The NS32CG821 supports automatic internally controlled refresh. Different types of refreshes can be performed. These different types include all RAS refresh and staggered refresh. 4.2 REFRESH CYCLE TYPES Two different types of refresh cycles are available for use. The two different types are mutually exclusive and can be used with the internal refresh control. The two different refresh cycle types are: all RAS refresh and staggered RAS refresh. In all refresh cycle types, the RAS precharge time is guaranteed: between the previous access RAS ending and the refresh RASo starting; between refresh RAS3 ending and access RAS beginning; between burst refresh RASs. There are two inputs, DISRFSH and ClRF, associated with refresh. There are also ten programming bits; RO-1, R9, CO-6 and ECASO used to program the various types of refreshing. The NS32CG821 will increment the refresh address counter automatically. The refresh address counter will be incremented once all the refresh RASs have been negated. In every combination of internal refresh and refresh type, the NS32CG821 is programmed to keep RAS asserted a number of ClK periods. The values of RAS low time during refresh are programmed with the programming bits RO and R1. 4.2.1 Conventional RAS Refresh A conventional refresh cycle causes RASO-3 to all assert from the first positive edge of ClK after refresh begins as shown in Figure 8. RASO-3 will stay asserted until the number of positive edges of ClK programmed have passed. On the last positive edge, RASO-3 will be negated and the refresh cycle will end. This type of refresh cycle is programmed by negating address bit R9 during programming. 4.1 AUTOMATIC INTERNAL REFRESH The NS32CG821 has an internal refresh clock. The period of the refresh clock is generated from the programming bits CO-3. Every period of the refresh clock, an internal refresh request is generated. As long as a DRAM access is not currently in progress and precharge time has been met, the internal refresh request will generate an automatic internal refresh. If a DRAM access is in progress, the NS32CG821 on-chip arbitration logic will wait until the access is finished before performing the refresh. The refresh! access arbitration logic can insert a refresh cycle between two accesses. If the two accesses are back to back, the arbitration logiC can insert a refresh cycle into the beginning of the next access. The CPU will wait to complete that access until the refresh cycle is completed. However, the refresh arbitration logic can not interrupt an access cycle in progress to perform a refresh. To enable automatic internally controlled refreshes, the input i5i'SRFSR must be negated. 4.2.2 Staggered RAS Refresh A staggered refresh staggers each RAS or group of RASs by a positive edge of ClK as shown in Figure 9. The number of RASs, which will be asserted on each positive edge of ClK, is determined by the RAS, CAS configuration mode programming bits C4-CS. If single RAS outputs are selected during programming, then each RAS will assert on successive positive edges of ClK. If two RAS outputs are selected during programming then RASO and RAS1 will assert on the first positive edge of ClK after refresh cycle begins. RAS2 and RAS3 will assert on the second positive edge of ClK after refresh cycle begins. If all RAS outputs were selected during programming, all 'FiA§ outputs would assert on the first positive edge of ClK after refresh cycle begins. Each RAS or group of ms will meet the programmed m low time and then negate. 1-171 .. NS32CG821 CLK (:) ::rJ • IRFRO CD CiJ en :r DISRFSH o RASo-3 TUF110126-7 FIGURE 7. Automatic Internal Refresh with Internal Refresh Request (3T of RAS low during refresh prognunmed) '0 O· ::l en ClK i" • IRFIP c: ~ RASO RASl !:I RAS2 -.J I\) RAS3 TUF/l0126-8 FIGURE 8. Conventional RAS Refresh CLK • IRFlP RASO RASI RAS2 RAS3 TUFI10126-9 FIGURE 9. Staggered RAS Refresh *IRFRQ and IRFIP are internal variables, they are only shown in the timing diagrams to make the diagrams easier to understand. z signer must ensure that the data from the DRAMs will be present for the CPU to sample or that the data has been written to the DRAM before allowing the CPU access cycle to terminate. The insertion of wait states also allows a CPU's access cycle to be extended until the DRAM access has taken place. The NS32CG821 inserts wait states into CPU access cycles due to; guaranteeing precharge time, refresh currently in progress, user programmed wait states, and the WAITIN signal being asserted. If one of these events is taking place and the CPU starts an access, the NS32CG821 will insert wait states into the access cycle, thereby increasing the length of the CPU's access. Once the event has been completed, the NS32CG821 will allow the access to take place and stop inserting wait states. 4.0 Refresh Options (Continued) 4.3 CLEARING THE REFRESH ADDRESS COUNTER The refresh address counter can be cleared by asserting ClRF while DISRFSH is negated as shown in Figure 10. This can be used prior to a burst refresh of the entire memory array. An end-of-count signal can be generated from the Q DRAM address outputs of the NS32CG821 and used to negate ClRF. elK ''-_-.Jf There are six programming bits, R2-R7; an input, WAITIN; and an output that functions as WAIT. TLlF/10126-10 FIGURE 10. Clearing the Refresh Address Counter 5.1 WAIT OUTPUT If WAIT is sampled asserted by the CPU, wait states (extra clock periods) are inserted into the current access cycle as shown in Figure 11. Once WAIT is sampled negated, the access cycle is completed by the CPU. WAIT is asserted at the beginning of a chip selected access and is programmed to negate a number of positive edges and/or negative levels of ClK from the event that starts the access. WAIT can also be programmed to function in page/burst mode applications. Once WAIT is negated during an access, and the ECAS inputs are negated with TSO asserted, WAIT can be programmed to toggle, following the ECAS inputs. Once TSO is negated, ending the access, WAIT will stay negated until the next chip selected access. 5.0 Wait State Support Wait states allow a CPU's access cycle to be increased by one or multiple CPU clock periods. By increasing the CPU's access cycle, all signals associated with that access cycle are extended. The CPU samples a wait line to determine if another clock period should be inserted into the access cycle. If another clock period is inserted, the CPU will continue to sample the input every CPU clock period until the input signal changes polarity, allowing the CPU access cycle to terminate. The user determines which value to select for WAIT depending upon the CPU speed used and where the user wants the CPU to sample its wait input during an access cycle. The decision to terminate the CPU access cycle is directly affected by the speed of the DRAMs used. The system de- Q'~ WAIT~ WAIT SAMPLED LOW INSERTS A WAITSTATE IN THE ACCESS CYCLE HIGH ALLOWS THE CPU TO TERMINATE THE ACCESS CYCLE FIGURE 11. WAIT Type Output 1-173 TL/F/10126-11 U) W N o Q CO N ..... ~ i r--------------------------------------------------------------------------5.0 Walt State Support (Continued) 5.1.1 Walt during Single Accesses can be programmed to delay a number of positive edges and/or negative levels of CLK. These options are programmed through address bits R2 and R3 at programming time. The user Is given four options described below. OT during non delayed and delayed acceses: WAIT will stay negated during a non-delayed access as shown in FIgure 12. During an access that is delayed, WAli will assert at the start of the access (OS and ALE) and negate from the positive edge of OD< that starts J!iAS for that access as shown In FIgure 13. WAlT eLK ALE Tl/F/10126-12 FIGURE 12. Non-Delayed Access with WAIT OT (WAIT is Sampled at the End of the "T2" Clock State) Tl T2 TW T3 T4 elK ALE cs TSO RASn WAIT Tl/F/10126-13 FIGURE 13. Delayed Access with WAIT OT ("2T" RAS Precharge, WAIT is Sampled at the End of the "T2" Clock State) 1-174 z (J) 5.0 Wait State Support (Continued) Co) II.) OT during non-delayed accesses and YoT during delayed accesses: WAIT will stay negated during a non-delayed access as shown in Figure 14. During an access that is delayed, WAIT will assert at the start of the access (CS and Tl ALE) and negate on the negative level of ClK after the positive edge of elK that asserted RAS for that access as shown in Figure 15. T2 T3 T4 TLlF/10126-14 FIGURE 14. Non-Delayed Access with WAIT OT (WAIT is Sampled at the "T3" Falling Clock Edge) Tl T2 T3 TW T4 elK ALE ./ I I TLlF/10126-15 FIGURE 15. Delayed Access with WAIT YoT (WAIT is Sampled at the "T3" Falling Clock Edge) 1-175 oG) 01) II.) ...... .,... N co c;, o N ('I) tJ) Z 5.0 Wait State Support (Continued) %T during non-delayed and delayed accesses: WAIT will assert when ALE is asserted and CS is asserted. WAIT will then negate on the negative level of ClK after the positive edge of ClK that asserts RAS for the access as shown in Figure 16. During delayed accesses in both modes, WAIT will assert at the start of the access and negate on the negative level of ClK after the positive edge of ClK that started RAS for that access as shown in Figure 17. TLlF/10126-16 FIGURE 16. Non-Delayed Access with WAIT %T (WAIT is Sampled at the "T2" Falling Clock Edge) T1 T2 TW TW T3 TLlF/10126-17 FIGURE 17. Delayed Access with WAIT %T (WAIT is Sampled at the "T2" Falling Clock Edge) 1-176 z en w 5.0 Wait State Support (Continued) N 1T during non-delayed and delayed accesses. WAIT will assert from ALE asserted and CS asserted. WAIT will negate from the next positive edge of ClK that asserts RAS for the access as shown in Figure 18. During delayed accesses, T1 WAIT will assert at the beginning of the access and will negate on the first positive edge of ClK after the positive edge of ClK that starts RAS for the access as shown in Figure 19. TW T2 13 I ~ ClK ALE Cs TSO RASn WAIT TL/F/10126-18 FIGURE 18. Non-Delayed Access with WAIT 1T (WAIT is Sampled at the End of the "T2" Clock State) T1 T2 TW TW T3 ClK ALE Cs TSO RASn WAIT TlIF/10126-19 FIGURE 19. Delayed Access with WAIT 1T (WAIT is Sampled at the End of the "T2" Clock State) 1-177 oC) (X) N 5.0 Wait State Support (Continued) When ending WAIT from a negative level of ClK; if RAS is asserted while ClK is high then WAIT will negate from the negative edge of ClK; if RAS is asserted while ClK is low then WAIT will negate from RAS asserting. When ending WAIT from a positive edge of ClK, the user can think of the positive edge of ClK that starts RAS as OT and the next positive edge of ClK as H. In a delayed access, the positive edge of ClK that starts RAS can be thought of as OT and the next positive edge as 1T. OT: WAIT will be asserted when the ECAS inputs are negated with TSO remaining asserted. When a single or group of ECAS inputs are asserted, WAIT will be negated as shown in Figure 21. %T: WAIT will be asserted when the ECAS inputs are negated with TSO remaining asserted. When a single or group of ECAS inputs are asserted again, WAIT will be negated from the first negative level of ClK after a single ECAS or group of ECASs are asserted as shown in Figure 22. H: WAIT will be asserted when the ECAS inputs are negated with TSO remaining asserted. When a single or group of ECAS inputs are asserted again, WAIT will be negated from the first positive edge of ClK after a single ECAS or group of ECASs are asserted as shown in Figure 23. 5.1.2 Walt during Page Burst Accesses WAIT can be programmed to function differently during page/burst types of accesses. During a page/burst access, the ECAS inputs will be asserted then negated while 'fSO is asserted. Through address bits R4 and RS, WAIT can be programmed to assert and negate during this type of access. The user is given four programming options described below. When ending WAIT from a negative level of ClK; if the ECASs are asserted while ClK is high then WAIT will negate from the negative edge of ClK, if the ECASs are asserted while ClK is low then WAIT will negate from the ECASs asserting. When ending WAIT from a positive edge of ClK, the positive edge of ClK that ECAS is setup to can be thought of as H. No Wait States: In this case, WAIT will remain negated even if the ECAS inputs are toggled as shown in Figure 20. T3 T4 T3 ,I T4 T3 T4 BEGINNING i'SO 1 T3 , OF :, ~ ECAS CAs T4 1 :~ ACCESS RASn ,I ~ , ClK , , , H H' AlJ= : I I WAIT TLlF/10126-20 FIGURE 20. No Wait States during Burst (WAIT is Sampled at the End of the "T3" Clock State) T3 .1 T4 T3 ,I T4 ClK BEGINNING i'SO T3 .1 T4 1 T3 ,I T4 1 ~ AC~~SS TL/F/10126-21 FIGURE 21. OT during Burst (WAIT is Sampled at the End of the "T3" Clock State) 1-178 z CJ) 5.0 Wait State Support (Continued) 1 13 1 TW 1 W N 13 14 TW 14 13 TW 0 14 C) CO ... C'K N BEGINNING or m ACCESS Wn Em rn iW! Tl/F/10126-22 FIGURE 22. YIT during Burat Acceaa (WAIT 18 Sampled at the uTS" Failing Clock Edge) C.K BEGINNING m or ACCESS RASn ECAS CAS WAIT Tl/F/10126-23 FIGURE 2S. 1T during Burst Access (WAIT is Sampled at the End of the "TS" Clock State) 5.2 DVNAMICALLV INCREASING THE NUMBER OF WAIT STATES WAITIN can increase the number of positive edges in a page/burst access. WAITIN can be permanently asserted in systems requiring an increased number of wait states. WAITIN can also be asserted and negated. depending on the type of access. As an example. a user could connect the ODIN output from the NS32CG16 to the WAITIN input. This could be used to perform write accesses with 1 wait state and read accesses with 2 wait states as shown in Figure 24. The user can increase the number of positive edges of ClK before WAIT is negated. With the input WAITIN asserted. the user can delay WAIT negating either one or two more positive edges of ClK. The number of edges is programmed through address bit R6. If the user is increasing the number of positive edges in a delay that contains a negative level. the positive edges will be met before the negative level. T1 T2 .1 TW .1 T1 T3 T2 TW TW T3 elK ALE RASn R~ ------------------------~:~ ~----~~\:--r------~! ....____ WAITIN ACCESS WITH WAIT OF 1T WITH WAITIN NEGATED ACCESS WITH WAIT OF 1T WITH WAITIN ASSERTED PROGRAMMED AS 1T Tl/F/10126-24 FIGURE 24. WAITIN Example (WAIT is Sampled at the End of "T2") 1·179 ~ N r-----------------------------------------------------------------------------------------------~ co 5.0 Wait State Support (Continued) N M 5.3 GUARANTEEING RAS LOW TIME AND RAS PRECHARGE TIME Z The NS32CG821 will guarantee RAS precharge time between accesses; between refreshes; and between access and refreshes. The programming bits RO and R1 are used to program combinations of RAS precharge time and RAS low time referenced by positive edges of ClK. RAS low time is programmed for refreshes only. During an access, the system designer guarantees the time RAS is asserted through the NS32CG821 wait logic. Since inserting wait states into an access increases the length of the CPU signals which are used to create ALE and TSO, the time that RAS is asserted can be guaranteed. "o CI) 6.0 Additional Access Support Features To support the different modes of accessing, the NS32CG821 have multiple access features. These features allow the user to take advantage of CPU or DRAM functions. These additional features include: address latches and column increment for page/burst mode support; and delay CAS, to allow the user with a multiplexed bus to ensure valid data is present before CAS is asserted. 6.1 ADDRESS LATCHES AND COLUMN INCREMENT The address latches can be programmed, through programming bit BO, to either latch the address or remain permanently in fall-through mode. If the address latches are used to latch the address, the rising edge of ALE places the latches in fall-through. Once ALE is negated, the address present on the row, column and bank inputs is latched. Precharge time is also guaranteed by the NS32CG821. Each RAS output has a separate positive edge of ClK counter. TSO is negated setup to a positive edge of ClK to terminate the access. That positive edge is n. The next positive edge is 2T. RAS will not be asserted until the programmed number of positive edges of ClK have passed. Once the programmed precharge time has been met, RAS will be asserted from the positive edge of ClK. However, since there is a precharge counter per RAS, an access using another RAS will not be delayed. Precharge time before a refresh is always referenced from the access RAS negating before RASa for the refresh asserting. After a refresh, precharge time is referenced from RAS3 negating, for the refresh, to the access RAS asserting. Once the address is latched, the column address can be incremented with the input COLINC. With COLINC asserted, the column address is incremented. If COLINC is asserted with all of the bits of the column address asserted, the column address will return to zero. COlINC can be used for sequential accesses of static column DRAMs. COLINC can also be used with the ECAS inputs to support sequential accesses to page mode DRAMs as shown in Figure 25. COLINC should only be asserted during an access. COLINC o 00-8,9,10 TL/F/l0126-25 FIGURE 25. Column Increment T1 T2 T1 T3 T2 T3 CLK ALE TSO RAS CAS WIN READ ACCESS NORMAL CAS ASSERTION \~------------------WRIT! ACCESS ASSERT ONLY AFTER FIRST POSITIVE CLOCK EDGE AFTER ill IS ASSERTED CAS CAN FIGURE 26. Delay CAS 1-180 TL/F/l0126-26 r-----------------------------------------------------------------------.z DRAM with 16-bit words and 2 parity bits. The NS32CG821 can drive more than 72 DRAMs, but the AC timing must be increased. Since the RAS and CAS outputs are configurable, all RAS and CAS outputs should be used for the maximum amount of drive. 6.0 Additional Access Support Features (Continued) 6.2 DELAY CAS DURING WRITE ACCESSES Address bit C9 asserted during programming will cause CAS to be delayed until the first positive edge of ClK after RAS is asserted when the input WIN is asserted. Delaying CAS during write accesses ensures that the data to be written to DRAM will be setup to CAS asserting as shown in Figure 26. If the possibility exists that data still may not be present after the first positive edge of ClK, CAS can be delayed further with the ECAS inputs. If address bit C9 is negated during programming, read and write accesses will be treated the same (with regard to CAS). ~ N (') C) c» .... N 7.1 BYTE WRITING By selecting a configuration in which all CAS outputs are selected during an access, the ECAS inputs enable a single or group of CAS outputs to select a byte (or bytes) in a word. In this case, the RAS outputs are used to select which of up to 4 banks is to be used as shown in Figure 29. In systems with a word size of 16 bits, the byte enables can be gated with a high order address bit to produce four byte enables which gives an equivalent to 8 banks of 16-bit words as shown in Figure 30. If less memory is required, each CAS should be used to drive each nibble in the 16-bit word as shown in Figures 27 and 28. 7.0 RAS and CAS Configuration Modes 7.2 MEMORY INTERLEAVING Memory interleaving allows the cycle time of DRAMs to be reduced by having sequential accesses to different memory banks. Since the NS32CG821 have separate precharge counters per bank, sequential accesses will not be delayed if the accessed banks use different RAS outputs. To ensure different RAS outputs will be used, a mode is selected where either one or two RAS outputs will be asserted during an access. The bank select or selects, BO and Bl, are then tied to the least significant address bits, causing a different The NS32CG821 allow the user to configure the DRAM array to contain one, two, four or eight banks of DRAM. Depending on the functions used, certain considerations must be used when determining how to set up the DRAM array. Programming address bits C4, C5 and C6 along with bank selects, BO-1, and CAS enables, ECASO-3, determine which RAS or group of RASs and which CAS or group of CASs will be asserted during an access. Different memory schemes are described. The NS32CG821 is specified driving a heavy load of 72 DRAMs, representing four banks of NS32CG821 TL/F/10126-27 FIGURE 27. 1 Bank DRAM Array Setup for 16-Blt System (Ca. C5. C4 = 011 during Programming) RASO RASI ~ CASO NS32CG821 CASI ECASo RAS2 ECAS2 ECASI ECAS3 RAS3 CAS2 CAS3 TL/F/10126-28 FIGURE 28. 2 Banks DRAM Array Setup tor 16-Blt System (Ca. C5. C4 = 101 during Programming) 1-181 7.0 RAS and CAS Configuration Modes (Continued) BO,B1 RO-9 CO-9 NS32CG821 ECASO ECAS2 ECASl ECAS3 TL/F/10126-29 FIGURE 29. 4 Banks Array Setup for 16-Blt System (Cs. Cs. C4 = 110 during Programming) NS32CG621 ECASO ) - - - -.... ECAS1 ECAS2 ECAS3 TLlF/10126-30 FIGURE 30. 8 Bank DRAM Array for 16·Blt System (Cs. Cs. C4 1-182 = 1. 1.0 during Programming) z (/) 7.0 RAS and CAS Configuration Modes (Continued) group of RASs to assert during each sequential access as shown in Figure 31. In this figure there should be at least one clock period of all RAS's negated between different RAS's being asserted to avoid the condition of a CAS before RAS refresh cycle. Co) N to ensure that the page/burst accesses are to sequential memory addresses, as shown in Figure 32. The ECAS inputs may then be toggled with the NS32CG821 's address latches in fall-through mode, while TSO is asserted. The ECAS inputs can also be used to select individual bytes. In page or static column modes, the two address bits after the page size can be tied to the bank select inputs to select a new bank if the page size is exceeded. 7.3 PAGE/BURST MODE In a static column, page or burst mode system, the least significant bits must be tied to the column address in order RASO NS32CG821 RASl RAS2 RAS3 CASO CASl CAS2 CAS3 TL/F110126-31 FIGURE 31_ Memory Interleaving (C6, C5, C4 = 1,1,0 during Programming) LOW ORDER { ADDRESS BITS AFTER COLUMN· BO RASO B1 ADDRESS AFTER BANK RO-9 LOW ORDER BITS CO-9 NS32CGB21 RAS1 RAS2 1 SEE BYTE WRITE SECTION FOR CONNECTION RAS3 '"~ 1 ECASO ECAS1 WRITE SECTiON FOR CONNECTION ECAS2 I~ 1~ !~!~ ECAS3 SEE BYTE WRITE SECTION FOR CONNECTION TL/F/10126-32 "See table below for row, column & bank address bit map. AO is used for byte addressing in this example. Page Mode/Static Column Mode Page Size Addresses Column Address Row Address BO Bl 256 Bits/Page 512 Bits/Page 1024 Bits/Page CO-7 ~ Al-8 C8-9 ~ X CO-8 ~ Al-9 C9 ~ X CO-9 X X X A9 A1D Al0 All All A12 x ~ DON'T CARE. the user can do as he pleases. FIGURE 32. Page, Static Column, Mode System 1-183 ~ Al-l0 oG) co .... N .N co c" oN Cf) (f) Z r-----------------------------------------------------------------------------------------------~ 8.0 Programming and Resetting ML, enabling the internal programming register. After ML is asserted, a valid programming selection is placed on the address bus (and ECASO), then ML is negated. When ML is negated, the value on the address bus (and ECASO) is latched into the internal programming register and the NS32CG821 is programmed, as shown in Figure 33. After ML is negated, the NS32CG821 will enter the 60 ms initialization period only if this is the first programming after power up or reset. Using this method, a set of transceivers on the address bus can be put at TRI-STATE® by the system reset signal. A combination of pull-up and pull-down resistors can be used on the address inputs of the NS32CG821 to select the programming values, as shown in FIgure 34. The NS32CG821 must be programmed by one of two possible programming sequences before it can be used. Once the chip is programmed, the bits effecting the wait logic become effective immediately, thus allowing the programming bus cycle to end. At power up, the NS32CG821 programming bits are in an undefined state. All internal latches and flip-flops are cleared. After programming, the NS32CG821 enters a 60 ms initialization period. During this initialization period, the NS32CG821 performs refreshes about every 15 p,s; this makes further DRAM warmup cycles unnecessary. The chip can be programmed as many times as the user wishes. After the first programming, the 60 ms initialization period will not be entered into unless the chip is reset. During the 60 ms initialization period, internal refreshes are taking place and the CPU is not allowed to enter into a memory access cycle. If a memory access is attempted, the NS32CG821 will send out wait states into the processor until initialization is complete. The actual initialization time period is given by the following formula: T = 4096'(Clock Divisor Select) "(Refresh Clock Fine Tune) I(DELCK Frequency) 8.2 CHIP SELECTED ACCESS PROGRAMMING The chip can also be programmed by asserting ML and performing a chip selected access. ALE is disabled internally until after programming. To program the chip using this method, ML is asserted. After ML is asserted, CS is assert· ed and a valid programming selection is placed on the ad· dress bus. When TSO is asserted, the chip is programmed with the programming selection on the address bus. After TSO is negated, ML can be negated as shown in Figure 35. 8.1 MODE LOAD ONLV PROGRAMMING MODE LOAD, ML, asserted enables an internal 23-bit programmable register. To use this method, the user asserts \ ....___----'1 ii[ ECASO ~~~~ CO-9 ---------"""XI.._ _~ROGRAMMING XI.._ _ _ _ __ • B:::.ITS~V.:iAL;ilID:.......J. TLlF/l0126-33 FIGURE 33. Mode Load Only Programming ADDRESS LATCHES AND DRIVERS CPU ADDRESS'f. NS32CG821 ENABLE I :- I SYSTEM POWER UP RESET --'---C>O-----I TL/F/l0126-34 ·Pull·Up or Pull·Down Resistors on Each Address Input FIGURE 34. Programming during System Reset / ADDRESS AND ECASO x VALID PROGRAMMING SELECTION x NS32CG821 PROGRAMMED TLlF/l0126-35 FIGURE 35. CS Access Programming 1·184 8.0 Programming and Resetting (Continued) Using this method, various programming schemes can be used. For example if extra upper address bits are available, an unused high order address bit can be tied to the signal ML. Using this method, one need only write to a page of memory, thus asserting the high order bit and in turn programming the chip as shown in Figure 36. DATA ",1 CONTROL I~ CPU CPU TLlF/l0126-37 FIGURE 37. Programming the NS32CG821 through the Address Bus and an 1/0 Port TLlF/l0126-36 Another simple way the chip can be programmed is the first write after system reset. This method requires only a flipflop and an OR gate as shown in Figure 38. At reset, the flipflop is preset. which pulls the Q output low. Since WR is negated, ML is not enabled. The first write access is used to program the chip. When WR is asserte~L is asserted. WR negated clocks the flip-flop, negates ML, and programs the NS32CG821 with the address and ECASO available at that time. CS does not need to be asserted using this method. An 1/0 port can also be used to assert ML. After ML is asserted, a chip selected access can be performed to pro· gram the chip. After the chip selected access, ML can be negated through the 1/0 port as shown in Figure 37. D RST NS32CG821 and ECASO ADDRESS NS32CG821 FIGURE 36. Programming the NS32CG821 through the Address Bus Only CPU WRITt: X j ~O-9 CO-9 ~A23 ML RO-9 CO-9 80 81 and ECASO ADORESS M[ 1 I/O PORT PR Q NS32CG821 Wii_....-o --/ :_~__I?1__~ __ ~ ~ TL/F/l0126-38 FIGURE 38. Programming the NS32CG821 on the First CPU Write after Power Up 1-185 ,..N co 8 r-------------------------------------------------------------------------------------~ 8.0 Programming and Resetting (Continued) N 8.3 EXTERNAL RESET tJ) At power up, all internal latches and flip-flops are cleared. The power up state can again be entered by asserting Ml and DISRFSH for 16 positive edges of ClK. After resetting if the user negates DISRFSH before negating Ml as shown in C") z I· ML \ DISRFSH \ Figure 39, Ml negated will program the chip. If Ml is negated before or at the same time as DISRFSH as shown in Figure 40, the chip will not be programmed. After the chip is programmed, the 60 ms initialization period will be entered into if this is the first programming after power up or reset. 16 CLOCKS "I I V TL/F/l0126-39 FIGURE 39. Chip Reset and Programmed r------- 16 POSITIVE EDGES OF ClK ~ ---~ t~V~7~/--- FIGURE 40. Chip Reset but Not Programmed 1-186 TLlF/l0126-40 8.0 Programming and Resetting (Continued) 8.4 PROGRAMMING BIT DEFINITIONS (Notes 1 and 2) Symbol Description BO Address Latch Mode 0 1 ALE asserted latches the input row, column and bank address. The row, column and bank latches are fall through. C9 Delay CAS during WRITE Accesses 0 1 CAS is treated the same for both READ and WRITE accesses. During WRITE accesses, CAS will be asserted by the event that occurs last: CAS asserted by the internal delay line or CAS asserted on the positive edge of ClK after RAS is asserted. C8 Row Address Hold Time 0 1 Row Address Hold Time Row Address Hold Time = = 25 ns minimum 15 ns minimum C7 Column Address Setup Time 0 1 Column Address Setup Time Column Address Setup Time C6,C5,C4 RAS and CAS Configuration Modes 0, 1, 1 RASO-3 and CASO-3 are all selected during an access. ECASn must be asserted for CASn to be asserted. 81, 80 are not used during an access. 1,0, 1 RAS and CAS pairs are selected by 81. ECASn must be asserted for CASn to be asserted. 81 = 0 during an access selects RASO-1 and CASO-1. 81 = 1 during an access selects RAS2-3 and CAS2-3. 80 is not used during an access. 1, 1,0 RAS singles are selected by 80-1. CASO-3 are all selected. ECASn must be asserted for CASn to be asserted. 81 = 0, 80 = 0 during an access selects RASO and CASO-3. 81 = 0, 80 = 1 during an access selects RAS1 and CASO-3. 81 = 1,80 = 0 during an access selects RAS2 and CASO-3. 81 = 1,80 = 1 during an access selects RAS3 and CASO-3. C3 Refresh Clock Fine Tune Divisor 0 Divide delay line/refresh clock further by 30 (If DElClK/Refresh Clock Clock Divisor = 2 MHz = 15 /Ls refresh period). Divide delay line/refresh clock further by 26 (If DElClK/Refresh Clock Clock Divisor = 2 MHz = 13 /Ls refresh period). 1 = 10 ns minimum = 0 ns minimum C2, C1, CO Delay Line/Refresh Clock Divisor Select 0,0,0 0,0,1 0,1,0 0,1, 1 1,0,0 1,0, 1 1,1,0 1, 1, 1 Divide DElClK by 10 to get as close to 2 MHz as possible. Divide DElClK by 9 to get as close to 2 MHz as possible. Divide DElClK by 8 to get as close to 2 MHz as possible. Divide DElClK by 7 to get as close to 2 MHz as possible. Divide DElClK by 6 to get as close to 2 MHz as possible. Divide DElClK by 5 to get as close to 2 MHz as possible. Divide DElClK by 4 to get as close to 2 MHz as possible. Divide DElClK by 3 to get as close to 2 MHz as possible. R9 Refresh Mode Select 0 1 RASO-3 will all assert and negate at the same time during a refresh. Staggered Refresh. RAS outputs during refresh are separated by one positive clock edge. Depending on the configuration mode. R6 Add Wait States to the Current Access if WAITIN is Low. 0 1 WAIT will be delayed by one additional positive edge of ClK. WAIT will be delayed by two additional positive edges of ClK. 1-187 8.0 Programming and Resetting (Continued) 8.4 PROGRAMMING BIT DEFINITIONS (Continued) Description Symbol R5,R4 WAIT during Burst (See Section 5.1.2) 0,0 NO WAIT STATES; WAIT will remain negated during burst portion of access. 0,1 H; WAIT will assert when the ECAS inputs are negated with TSO asserted. WAIT will negate from the positive edge of ClK after the ECASs have been asserted. 1,0 %T; WAIT will assert when the ECAS inputs are negated with TSO asserted. WAIT will negate on the negative level of ClK after the ECASs have been asserted. 1, 1 OT; WAIT will assert when the ECAS inputs are negated. WAIT will negate when the ECAS inputs are asserted. R3,R2 WAIT Delay Times (See Section 5.1.1) 0,0 NO WAIT STATES; WAIT will remain high during non-delayed accesses. WAIT will negate when RAS is negated during delayed accesses. 0,1 %T; WAIT will negate on the negative level of ClK, after the access RAS. 1,0 NO WAIT STATES, % T; WAIT will remain high during non-delayed accesses. WAIT will negate on the negative level of ClK, after the access RAS, during delayed accesses. 1, 1 1T; WAIT will negate on the positive edge of ClK after the access RAS. R1,RO RAS Low and RAS Precharge Time 0,0 RAS asserted during refresh = 2 positive edges of ClK. RAS precharge time = 1 positive edge of ClK. 0, 1 RAS asserted during refresh = 3 positive edges of ClK. RAS precharge time = 2 positive edges of ClK. 1,0 RAS asserted during refresh = 2 positive edges of ClK. RAS precharge time = 2 positive edges of ClK. 1, 1 RAS asserted during refresh = 4 positive edges of ClK. RAS precharge time = 3 positive edges of ClK. Note 1: During programming ECASo, 8" R7 have to be set to low, and Rs has to be set high. Nole 2: RAS and CAS configuration modes C6, C5, C4 = 000,001,010,100 and 111 1-188 are reserved. 9.0 DRAM Critical Timing Parameters The clock input, DELCLK, controls the internal delay line and refresh request clock. DELCLK should be a multiple of 2 MHz. If DELCLK is not a multiple of 2 MHz, tRAH and tASC will change. The new values of tRAH and tASC can be calculated by the following formulas: The two critical timing parameters, shown in Figure 41, that must be met when controlling the access timing to a DRAM are the row address hold time, tRAH, and the column address setup time, tASC. Since the NS32CG821 contain a precise internal delay line, the values of these parameters can be selected at programming time. These values will also increase and decrease if DELCLK varies from 2 MHz. If tRAH was programmed to equal 15 ns then tRAH = 30*«(DELCLK Divisor)' 2 MHz/(DELCLK Frequency»-1) + 15 ns. If tRAH was programmed to equal 25 ns then tRAH = 30*«(DELCLK Divisor)· 2 MHz/(DELCLK Frequency»-1) + 25 ns. If tASC was programmed to equal 0 ns then tASC = 15' «DELCLK Divisor)" 2 MHz/(DELCLK Frequency» - 15 ns. 9.1 PROGRAMMABLE VALUES OF tRAH AND tASC The NS32CG821 allow the values of tRAH and tASC to be selected at programming time. For each parameter, two choices can be selected. tRAH, the row address hold time, is measured from ~ asserted to the row address starting to change to the column address. The two choices for tRAH are 15 ns and 25 ns, programmable through address bit C8. tASC, the column address setup time, is measured from the column address valid to ~ asserted. The two choices for tASC are 0 ns and 10 ns, programmable through address bit If tASC was programmed to equal 10 ns then tASC = 25" «DELCLK Divisor)" 2 MHz/(DELCLK Frequency» - 15 ns. Since the values of tRAH and tASC are increased or decreased, the time to ~ asserted will also increase or decrease. These parameters can be adjusted by the following formula: C7. 9.2 CALCULATION OF tRAH AND tASC There are two clock inputs to the NS32CG821. These two clocks, DELCLK and CLK can either be tied together to the same clock or be tied to different clocks running asynchronously at different frequencies. Delay to ~ = Actual Spec. + Actual tRAH Programmed tRAH + Actual tASC - Programmed tASC. \ I-- tASC_ I--tRAH - QOUl ROW X TLlF/10126-41 FIGURE 41. tRAH and tASC 1-189 10.0 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Temperature under Bias ................... O'C to + 70'C All Input or Output Voltage with Respect to GND ................... -0.5Vto +7V Power Dissipation @ 20 MHz ....................... 0.5W ESD Rating to be determined. Storage Temperature ................. -65'C to + 150'C 11.0 DC Electrical Characteristics TA = O'Cto +70'C, Vcc = 5V ±10%, GND = OV Symbol Parameter Conditions VIH logical 1 Input Voltage Tested with a Limited Functional Pattern VIL logical 0 Input Voltage Tested with a Limited Functional Pattern VOHl a and WE Outputs VOL1 a and WE Outputs VOH2 All Outputs except as, WE VOL2 All Outputs except as, WE liN Input leakage Current = -10 mA = 10mA IOH = -3 mA IOL = 3 mA VIN = Vcc or GND VIN = GND Min IOH Typ Max Units 2.0 Vcc + 0.5 V -0.5 0.8 V 0.5 V Vcc - 1.0 IOL IILML Ml Input Current (low) ICCl Standby Current ClK at 8 MHz (VIN ICCl Standby Current ClK at 20 MHz (VIN ICCl Standby Current ICC2 Supply Current ICC2 V Vcc - 1.0 -10 = Vcc or GND) = Vcc or GND) ClK at 25 MHz (VIN = Vcc or GND) 6 0.5 V 10 p.A 200 p.A 15 mA 8 17 mA 10 20 mA ClK at 8 MHz (Inputs Active) (ILOAD = 0) (VIN = VCC or GND) 20 40 mA Supply Current ClK at 20 MHz (Inputs Active) (I LOAD = 0) (VIN = Vcc or GND) 40 75 mA ICC2 Supply Current ClK at 25 MHz (Inputs Active) (lLOAD = 0) (VIN = Vcc or GND) 50 95 mA CIN" Input Capacitance fiN at 1 MHz 10 pF 'Nole: CIN 18 "01100% lesled. 12.0 AC Timing Parameters: NS32CG821 Two speed selections are given, the NS32CG821-20 and the NS32CG821·25. The differences between the two parts are the maximum operating frequencies of the input ClKs and the maximum delay specifications. low frequency applications may use the" - 25" part to gain improved timing. The AC timing parameters are grouped into sectional numbers as shown below. These numbers also refer to the timing diagrams. 1-36 Common parameters to all modes of operation 50-56 Difference parameters used to calculate; RAS low time, RAS precharge time, CAS high time and C7:S low time 300-315 Memory access parameters used in both single and dual access applications 500-506 Programming parameters Unless otherwise stated Vcc = 5.0V ± 10%, 0 < TA < 70'C, the output load capacitance is typical for 4 banks of 18 DRAMs per bank, including trace capacitance (see Note 2). Two different loads are specified: 200-212 Refresh parameters 1-190 CL CL = CH CH CH = 50 pF loads on all outputs except = 125 pF loads on RASo-3 and C7:S0-3 and 50 pF loads on all outputs except = 150 pF loads on aO-9 and WE; or = 380 pF loads on aO-9 and WE. z (J) 12.0 AC Timing Parameters: NS32CG821 Unless otherwise stated Vee = 5.0V ± 10%, O°C < TA per bank, including trace capacitance (see Note 2). Two different loads are specified: CL = 50 pF loads on all outputs except CL = 150 pF loads on 00-9 and WE; or < (Continued) 70°C, the output load capacitance is typical for 4 banks of 18 DRAMs C) CH CH CH Symbol Common Parameter Description CL Min 1 fClK 2 3,4 Q) .... = 50 pF loads on all outputs except = 125 pF loads on RASO-3 and CASO-3 and = 380 pF loads on 00-9 and WE. NS32CG821-20 Number Co) ~ NS32CG821-25 CH Max Min N CL Max CH Min Max Min Max 0 25 0 25 ClK Frequency 0 tClKP ClKPeriod 50 50 40 tClKPW ClK Pulse Width 15 15 12 5 fDClK DElClK Frequency 5 20 5 20 5 20 5 20 6 tDClKP DElClK Period 50 200 50 200 50 200 50 200 7,8 tDClKPW DElClK Pulse Width 15 15 12 12 9a tPRASCASO RAS Asserted to CAS Asserted (tRAH = 15 ns, tASC = 0 ns) 30 30 30 30 9b tPRASCAS1 RAS Asserted to CAS Asserted (tRAH = 15 ns, tASC = 10 ns) 40 40 40 40 9c tPRASCAS2 (RAS Asserted to CAS Asserted (tRAH = 25 ns, tASC = 0 ns) 40 40 40 40 9d tPRASCAS3 (RAS Asserted to CAS Asserted (tRAH = 25 ns, tASC = 10 ns) 50 50 50 50 17 15 17 15 25 27 25 20 10a tRAH Row Address Hold Time (tRAH = 15) 10b tRAH Row Address Hold Time (tRAH 11a tASC Column Address Setup Time (tASC 11b tASC Column Address Setup Time (lASC = 10) 12 tPCKRAS ClK High to RAS Asserted following Precharge 27 = 25) = 0) 27 0 20 40 12 2 0 2 0 12 10 12 10 32 22 26 13 tPARORAS TSO Negated to RAS Negated 38 43 31 35 14 tPENCl ECASO-3 Asserted to CAS Asserted 23 31 20 27 15 tPENCH ECASO-3 Negated to CAS Negated 25 33 20 27 16 tPAROCAS TSO Negated to CAS Negated 60 68 47 54 17 tPClKWH ClK to WAIT Negated 39 39 31 31 19 tPEWl ECAS Negated to WAIT Asserted during a Burst Access 42 42 34 34 20 tSECK ECAS Asserted Setup to ClK High to Recognize the Rising Edge of ClK during a Burst Access 24 24 19 19 5 5 5 5 23 tSWCK 24 tPWINWEH WIN Asserted to WE Asserted 39 49 31 41 25 tPWINWEl WIN Negated to WE Negated 39 49 31 41 26 tPAO Row, Column Address Valid to 00-9 Valid 29 38 26 35 27 tPCINCO COLINC Asserted to 00-9 Incremented 34 43 30 39 28 tSCINEN COLINC Asserted Setup to ECAS Asserted to Ensure tASC = 0 ns WAITIN Asserted Setup to ClK 16 1-191 17 15 17 ...co N ~ (f) tI) Z 12.0 AC Timing Parameters: NS32CG821 (Continued) Two different loads are specified: CL = 50 pF loads on all outputs except CL = 150 pF loads on QO-9 and WE; or CH CH CH Unless otherwise stated Vee = 5.0V ± 10%, O°C < T A per bank, including trace capacitance (see Note 2). < 70°C, the output load capacitance is typical for 4 banks of 18 DRAMs = 50 pF loads on all outputs except = 125 pF loads on RASO-3 and CASO-3 and = 380 pF loads on QO-9 and WE. NS32CG821-20 Number Symbol Common Parameter Description CL Min NS32CG821-25 CH Max Min CL Max Min CH Max Min Max 29a tSARQCK1 TSO Negated Setup to ClK High with 1 Period of Precharge 43 43 34 34 29b tSARQCK2 TSO Negated Setup to ClK High with > 1 Period of Precharge Programmed 19 19 15 15 31 tPCKCAS ClK High to CAS Asserted when Delayed by WIN 32 tSCADEN Column Address Setup to ECAS Asserted to Guarantee tASC = 0 14 15 14 16 33 tWCINC COLINC Pulse Width 20 20 20 20 34a tPCKClO ClK High to CAS Asserted following Precharge (tRAH = 15 ns, tASC = 0 ns) 81 89 72 79 34b tPCKCl1 ClK High to CAS Asserted following Precharge (tRAH = 15 ns, tASC = 10 ns) 91 99 82 89 34c tPCKCl2 ClK High to CAS Asserted following Precharge (tRAH = 25 ns, lASC = 0 ns) 91 99 82 89 34d tPCKCl3 ClK High to CAS Asserted following Precharge (tRAH = 25 ns, tASC = 10 ns) 101 109 92 99 35 tCAH Column Address Hold Time (Interleave Mode Only) 36 tPCQR CAS Asserted to Row Address Valid (Interleave Mode Only) 31 32 32 90 1-192 39 25 32 90 32 32 90 90 z (J) 12.0 AC Timing Parameters: NS32CG821 Unless otherwise stated Vee = 5.0V ± 10%, O'C < TA per bank, including trace capacitance (see Note 2). < (Continued) 70'C, the output load capacitance is typical for 4 banks of 18 DRAMs NS32CG821-20 Number Difference Parameter Description Symbol CL Min 50 101 Max ...... NS32CG821-25 CH Min CH CL Max Min Max Min Max (TSO Negated to RAS Negated) Minus (ClK High to RAS Asserted) 16 16 14 14 51 102 (ClK High to Refresh RAS Negated) Minus (ClK High to RAS Asserted) 13 13 11 11 53 tD3b (ClK High to RAS Asserted Minus (TSO Negated to RAS Negated) 4 4 4 4 54 104 (ECAS Asserted to CAS Asserted) Minus (ECAS Negated to CAS Negated) 55 105 (ClK to Refresh RAS Asserted) Minus (ClK to Refresh RAS Negated) Unless otherwise stated Vee = 5.0V ± 10%, O'C < TA per bank, including trace capacitance (see Note 2). -7 7 -7 7 5 -7 5 7 5 5 CH = 50 pF loads on all outputs except CH = 125 pF loads on RASO-3 and CASO-3 and CH = 380 pF loads on 00-9 and WE. NS32CG821-25 NS32CG821-20 Symbol -7 < 70'C, the output load capacitance is typical for 4 banks of 18 DRAMs Two different loads are specified: CL = 50 pF loads on all outputs except CL = 150 pF loads on 00-9 and WE; or Number 7 Refresh Parameter Description CL Min CH Max Min CL Max Min CH Max Min Max 207 tPCKRFRASH ClK High to Refresh RAS Negated 35 40 29 33 208 tPCKRFRASl ClK High to Refresh RAS Asserted 28 33 23 27 1-193 N oCi) 00 N CH = 50 pF loads on all outputs except CH = 125 pF loads on RASO-3 and CASO-3 and CH = 380 pF loads on 00-9 and WE. Two different loads are specified: CL = 50 pF loads on all outputs except CL = 150 pF loads on 00-9 and WE; or Co) 12.0 AC Timing Parameters: NS32CG821 Unless otherwise stated VCC = 5.0V ± 10%, O°C < TA per bank, including trace capacitance (see Note 2). (Continued) < 70'C, the output load capacitance is typical for 4 banks of 18 DRAMs Two different loads are specified: CL = 50 pF loads on all outputs except CL = 150 pF loads on 00-9 and WE; or CH CH CH = 50 pF loads on all outputs except = 125 pF loads on RASO-3 and CASO-3 and = 380 pF loads on 00-9 and WE. NS32CG821·20 Number Symbol Memory Access Parameter Description CL Min NS32CG821-25 CH Max Min CL Max Min CH Max Min 300 tSCSCK CS Asserted to ClK High 14 14 13 13 301a tSAlECKNl ALE Asserted Setup to ClK High Not Using On-Chip latches or if Using On-Chip latches and BO, Bl, Are Constant, Only 1 Bank 16 16 15 15 ALE Asserted Setup to ClK High, if Using On-Chip latches if BO, Bl Can Change, More Than One Bank 29 29 29 29 301b tSAlECKl 302 tWAlE ALE Pulse Width 18 18 13 13 303 tSBADDCK Bank Address Valid Setup to ClK High 20 20 18 18 304 tSADDCK Row, Column Valid Setup to ClK High to Guarantee tASR = 0 ns 11 15 11 16 Row, Column, Bank Address Held from ALE Negated (Using On-Chip latches) 10 10 8 8 Row, Column, Bank Address Setup to ALE Negated (Using On-Chip latches) 3 3 2 2 305 306 tHASRCB tSRCBAS Max 307 tPCKRl ClK High to RAS Asserted 27 32 22 26 308a tPCKClO ClK High to CAS Asserted (tRAH = 15 ns, IASC = 0 ns) 81 89 72 79 308b tPCKCll ClK High to CAS Asserted (tRAH = 15 ns, tASC = 10 ns) 91 99 82 89 308c tPCKCl2 ClK High to CAS Asserted (tRAH = 25 ns, tASC = 0 ns) 91 99 82 89 308d tPCKCl3 ClK High to CAS Asserted (tRAH = 25 ns, tASC = 10 ns) 101 109 92 99 309 tHCKAlE ALE Negated Hold from ClK High 310 tSWINCK WIN Asserted Setup to ClK High that starts access RAS to Guarantee CAS is Delayed 0 0 0 0 -21 -21 -16 -16 311 tPCSWl CS Asserted to WAIT Asserted 26 26 22 22 312 tPCSWH CS Negated to WAIT Negated 26 26 22 22 314 tPAlEWl ALE Asserted to WAIT Asserted (CS is Already Asserted) 48 48 39 39 TSO Negated to ClK High That Starts Access RAS to Guarantee tASR = 0 ns 315 41 34 45 39 -~-~ 316 ttPCKCVO ClK to Column Addr. Valid (tRAH = 15 ns, tASC = 0 ns) 78 1-194 87 66 75 z 12.0 AC Timing Parameters: NS32CG821 Unless otherwise stated Vee = 5.0V ± 10%, O'C < T A < per bank, including trace capacitance (see Note 2). (Continued) 70'C, the output load capacitance is typical for 4 banks of 18 DRAMs Two different loads are specified: CL = 50 pF loads on all outputs except CL = 150 pF loads on QO-9 and WE; or CH CH CH = = = Symbol Programming Parameter Description Q) CL Min 8 .... N 50 pF loads on all outputs except 125 pF loads on RASO-3 and CASO-3 and 380 pF loads on QO-9 and ii'\iE. NS32CG821·20 Number ~ NS32CG821·25 CH Max Min CL Max Min CH Max Min 500 tHMLADD Mode Address Held from ML Negated 6 6 5 501 tSADDML Mode Address Setup to ML Negated 6 6 6 6 502 tWML ML Pulse Width 15 15 15 15 503 tSADAQML Mode Address Setup to 'i'SO Asserted 0 0 0 0 504 tHADAQML Mode Address Held from 'i'SO Asserted 39 39 29 29 505 tSCSARQ ~ Asserted Setup to 'i'SCi Asserted 6 6 6 6 506 tSMLARQ Ii.K Asserted Setup to iSO Asserted 10 10 10 10 Max 5 Note 1: "Absolute Maximum Ratings" are the values beyond which the safety of the device cannot be guaranteed. They are not meant to Imply that the davlce should be operated at the.. limits. The teble of "Electrical Characteristics" provides conditions for actual davlce operation. Note 2: Input pulse OV to 3V; tR = tF = 2.5 ns. Input reference point on AC measurements is 1.5V. Output reference pOints are 2.4V for High and O.BV for Low. Note 3: AC Production testing is done at 50 pF. OELCLK fi-J=th 2- ClK ," 2 ~ 4 rurvv TLlF/IDI28·42 FIGURE 42. Clock, DELCLK Timing ClK~ 150 ~ ru r- f- I IRFlP II f \ ! 0D-8,9,10 XXXXXX REFRESH ROW -t 2~ !Win ~ - 20~ f DlSRFSH -;.;,..... TL/FI1DI26-43 FIGURE 43, 200: Rafrash Timing 1-195 _ N I z r-----------------------------------------------------------------------------~ 12.0 AC Timing Parameters: NS32CG821 CLK ALE ~ ~ ~ ~ ~ n...J'w FL.f\-l Bs ~- 302 --j300 I(xxxJQa - ~03 BO.Bl RO-9 CO-9 (Continued) -~- )0(: I-- ---. - VALID XXXXX VALID xxxxx ..........., ---. ~ 3071:=- ~9- t RASn 1-- 308 r-- CASn -+ ~ VAUD ~ VALID - H 1+ t I-- 29 -J::::'[ ~ -\ I I-- \ -+ 17 17r- 311 12 161- L-.J - - \ 1;- _19 t I - -J- 17 r - --1241-- t -25j- + I 26- 316 aD-9 xxxx J-.. - Xlfl-ROW~ COLUMN - xxxxxxxxxxx ROW COLUMN ~ ECASn 20 I-- TLlF/l012B-44 FIGURE 44. 300: Memory Access Timing 1-196 r--------------------------------------------------------------------------.z en 12.0 AC Timing Parameters: NS32CG821 Co) (Continued) i.... eLK AlE ~-------i----------~~~~~~ BO TLlF/10126-45 (Programmed as C4 = 1,C5 = 1,C6 = 1) FIGURE 45. 300: Access Interleaving 1-197 ,.. ~ ~ z ~------------------------------------------------------------------------------------~ 12.0 AC Timing Parameters: NS32CG821 (Continued) eLK ALE as 4-~~4-------+-----~----------+-~~~ COLINe 00-9 Ro-9 eD-9 TL/FI10128-48 FIGURE 46. 400: COLINC Page/Static Column Ace••• Timing TLlF/lDl26-47 FIGURE 47. 500: Programming 1·198 13.0 NS32CG821 User Hints 1. All inputs to the NS32CG821 should be tied high, low or the output of some other device. 7. PARAMETER CHANGES DUE TO LOADING Not.: One signal is active high. COLINe should be tied low to disable. 2. Each ground on the NS32CG821 must be decoupled to the closest on-chip supply (Vecl with 0.1 ,..F ceramic capacitor. This is necessary because these grounds are kept separate inside the NS32CG821. The decoupling capacitors should be placed as close as possible with short leads to the ground and supply pins of the NS32CG821. 3. The output called "CAP" should have a 0.1 ,..F capaCitor to ground. 4. The NS32CG821 has 200 series damping resistors built into the output drivers of RAS, CAS, address and WE. Space should be provided for external damping resistors on the printed circuit board (or wire-wrap board) because they may be needed. The value of these damping resistors (if needed) will vary depending upon the output, the capacitance of the load, and the characteristics of the trace as well as the routing of the trace. The value of the damping resistor also may vary between the wire-wrap board and the printed circuit board. To determine the value of the series damping resistor it is recommended to use an oscilloscope and look at the furthest DRAM from the NS32CG821. The undershoot of RAS, CAS, WE and the addresses should be kept to less than 0.5V below ground by varying the value of the damping resistor. The damping resistors should be placed as close as possible with short leads to the driver outputs of the NS32CG821. 5. The circuit board must have a good Vee and ground plane connection. If the board is wire-wrapped, the Vee and ground pins of the NS32CG821, the DRAM associated logic and buffer circuitry must be soldered to the Vee and ground planes. 6. The traces from the NS32CG821 to the DRAM should be as short as possible. 1-199 All A.C. parameters are specified with the equivalent load capacitances, including traces, of 64 DRAMs organized as 4 banks of 18 DRAMs each. Maximums are based on worst-case conditions. If an output load changes then the A.C. timing parameters associated with that particular output must be changed. For example, if we changed our output load to C = 250 pF loads on RASO-3 and CASO-3 C = 760 pF loads on 00-9 and WE we would have to modify some parameters (not all calculated here) $308a Clock to CAS asserted (tRAH = 15 ns, tASC = 0 ns) A ratio can be used to figure out the timing change per change in capacitance for a particular parameter by using the specifications and capaCitances from heavy and light load timing. R . _ $308a wI heavy load - $308a w/light load CH(CAS) - CL(CAS) atlo 79 ns - 72 ns 125 pF - 50 pF 7 ns =-75 pF $308a (actual) = (capacitance difference x ratio) + $308a (specified) 7ns 75pF = ( 250pF -125pF ) - - = 11.7ns + 79ns = 90.7 ns @ 250 pF load + 79ns ~ N it) co a. C ...... cr: ,... N it) co a. C ...... ~ N it) co a. C ~National PRELIMINARY ~ Semiconductor DP8520A/DP8521A/DP8522A microCMOS Programmable 256k/1 M/4M Video RAM ControllerIDrivers General Description Features The DP8520Al21A/22A video RAM controllers provide a low cost, single chip interface between video RAM and all 8-, 16- and 32-bit systems. The DP8520Al21 Al22A generate all the required access control signal timing for VRAMs. An on-chip refresh request clock is used· to automatically refresh the VRAM array. Refreshes and accesses are arbitrated on Chip. If necessary, a WAIT or DTACK output inserts wait states into system access cycles, including burst mode accesses. RAS low time during refreshes and RAS precharge time after refreshes and back to back accesses are guaranteed through the insertion of wait states. Separate on-chip precharge counters for each RAS output can be used for memory interleaving to avoid delayed back to back accesses because of precharge. An additional feature of the DP8522A is two access ports to simplify dual accessing. Arbitration among these ports and refresh is done on Chip. • On chip high precision delay line to guarantee critical VRAM access timing parameters • microCMOS process for low power • High capacitance drivers for RAS, CAS, DT/OE and VRAM address on chip • On chip support for nibble, page and static column VRAMs • Byte enable signals on chip allow byte writing in a word size up to 16 bits with no external logic • Selection of controller speeds: 20 MHz and 25 MHz • On board Port AlPort B (DP8522A only)/refresh arbitration logic • Direct interface to all major microprocessors (application notes available) • 4 RAS and 4 CAS drivers (the RAS and CAS configuration is programmable) Control # of Pins # of Address (PLCC) Outputs Largest VRAM Possible Direct Drive Memory Capacity Access Ports Available DP8520A 68 9 256 kbit 4 Mbytes Single Access Port DP8521A 68 10 1 Mbit 16 Mbytes Single Access Port DP8522A 84 11 4 Mbit 64 Mbytes Dual Access Ports (A and B) Block Diagram DP8520Al21A/22A VRAM Controller BANK ADDRESS IN ROW ADDRESS IN I------, -....~'-. . -+....:.;:;:.:....1 COLUMN ADDRESS IN -t-+-+I__...,.,...__J MODE LOAD -f__..,--"";OO....--l CONTROL INPUTS ADDRESS OUT J--~I--::~~::::-.,..-W~--I-------~WAIT H-+--I------.... ATACKB(8522A) .. L:;:~:;==:.JTt_--t~==-:-::=- GRANTB(8522A) SYSTEM CLOCK iiASo- 3 CASO- 3 TLlF/933B-5 FIGURE 1 1-200 r-----------------------------------------------------------------------------, ~National N CD "TI en ()C) ~ Semiconductor 29F68 Dynamic RAM Controller General Description Features The 29F68 is a high-performance memory controller, replacing many SSI and MSI devices by grouping several unique functions. It provides two 9-bit address latches and two 9-bit counters for row and column address generation during refresh. A 2-bit bank select latch for row and column address generation during refresh, and a 2-bit bank select latch for the two high order address bits are provided to select one of the four RAS and CAS outputs. • High-performance memory controller • Replaces many SSI and MSI devices by grouping several unique functions • Functionally equivalent to AMD's Am2968 and Motorola's MC74F2968 • Provides control for 16K, 64K, or 256K dynamic RAM systems • Outputs directly drive up to 88 DRAMs • Highest order two address bits select one of four banks of RAMs • Chip Select for easy expansion • Provides memory refresh with error correction mode The 29F68 is functionally equivalent to AMD's Am2968 and Motorola's MC74F2968. Logic Symbol Connection Diagram Pin Assignment for Lee and pee AR7AC6AR6ACsARs LE GND AC4AR4A~AR3A~AR2 ~1lID1lID[j]1l§l1l]1HI1l][j][j][j]J[]][]] AC7 1lll ARa~ mNC []] AC 1 ACa~ ill AR1 SELo~ mACo rn ARo rn MSEL SEL1~ MC11m TL/F/9608-1 MColll! rues RASI~ ~CASI CAS3 1i!1 RAS3 lW lID] RASo ~ CASo ~ RAS o CAS2~ ~CAS1 NC~ RAS2~ I£J 0 0 ~'rw~.,rw~.,rw~.,r/ 1BJ~~Im~~~Illl~~IBI~~ Oa 0 7 06 05 Vee Vee BE GND 04 03 02 01 He TL/F/9608-2 1-201 • = ~ r---------------------------------------------------------------------------~ ~National ~ Semiconductor 54F/74F968 1 Mbit Dynamic RAM Controller General Description Features The 'F968 is a high performance memory controller, replacing many SSI and MSI devices by grouping several unique functions. It provides two 1O-bit address latches and two 10bit counters for row and column address generation during refresh. A 2-bit bank select latch for row and column address generation during refresh and a 2-bit bank select latch for the two high order address bits are provided to select one of the four RAS and CAS outputs. • Provides control for 16K, 64K, 256K or 1 Mbit DRAM systems • Outputs directly drive up to 88 DRAMs • Chip select for easy expansion • Provides memory refresh with error correction mode • 52-pin plastic leaded chip carrier Logic Symbol TL/F/9604-1 1-202 rJ; r----------------------------------------------------------------, Precautions to Take When Driving Memories National Semiconductor Application Note 305 Mike Evans As memory prices continue their relentless reduction of cost per bit, more and more systems designers are incorporating memories into their designs. In general these memories comprise a number of dynamic RAMs, such as the 64k x 1. In this x 1 configuration, the number of RAMs required is a multiple of the bus width. Most new system designs use 16bit microprocessors, so that a typical memory will comprise from 16 to 64 DRAMs, thus providing from 64k to 256k addressing capability. This means the memory drivers have to drive upwards of 16 RAMs. The drivers may be part of an integrated circuit dynamic RAM controller such as the DP8408A1DP8409A, or they may be on a separate chip such as the DP84240/DP84244 octal memory drivers. The recommendations in this article are valid for any type of memory driver. The purpose of the article is to forewarn new designers using memories of problems they will encounter if adequate precautions are not taken. A typical configuration of a 16-bit wide memory is shown in Figure 1. Each driver address output goes to every dynamic RAM, as does WE. ~ outputs go to half the number of RAMs assuming byte writing is required. RAS outputs each go only to one bank. Note that these loads are not true for the data inputs and outputs. Each data I/O only connects to its respective bit, so the loading is only one RAM per bank for data. In general, this is why buffers are not required on the data bus when interfacing to memory. Data In of the RAMs can be linked directly to Data Out for anyone bit, and also to the corresponding bit on the data bus. This is true for normal read and write operations, but If read-modlfy-write cycles are employed, the Data Out signals must be buffered from the data bus. Using this typical memory configuration may not be as simple as it seems. Without care and attention, problems can arise for the unprepared, and there are two areas in particular which may cause memory errors or memory damage: one is voltage overshoot caused by inductive traces and high capacitive loads, the other is switching spikes caused by switching high capacitive loads. manufacturers' RAMs, so a more typical maximum Input capacitance would be 3 pF for RAS and 3.5 pF for CAS. RAM input currents are so small as to be negligible. The input current is quoted as 10 p.A maximum, but again most RAMs are much less than this in a typical memory. Driving DRAMs, therefore, is not a problem of DC drive capability, but rather a problem of capacitance drive capability. Driving DRAM input capacitance is further compounded by printed circuit traces, and even more so by wire-wrapping. Both can be represented by a transmission line with distributed capacitance and inductance. Thus, the total load is equivalent to a complex impedance comprising the distributed trace inductance, and a capaCitance comprising distributed trace capacitance and RAM Input capacitance as shown in Figure 28. The effect Is an overshoot or undershoot at the dynamic RAM inputs that occurs each time a memory driver changes state, as shown in Figure 2b. As the driver output changes state, the load capacitance cannot be instantaneously charged or discharged because the current available is limited both by the driver transistor Impedance, and the equivalent series resistance from the supply rail through the chip to the trace resistance. This current will be similar in value to the quoted short circuit current of the driver stage; therefore there is a spike of current that lasts as long as it takes to change the voltage of all the capaCitances. For the driver stages of the DP8408A/DP8409A, or the DP84240/ DP84244, the typical short circuit current is 100 mA per stage. This Is true for either direction, so that the hlgh-to-Iow transition takes roughly the same time as the low-to-high tranSition, minimizing skew times on all the driver outputs, as they transition in either direction. Assuming the ou1put low voltage, VOL, Is 0.2V and the output high voltage, VOH, is 3.2V, and that the charge/discharge current Is constant at Isc, then the current spike will exist for a time, T, where, T = CIL X (VOH - Voullsc = 500 pF x 3.0V/l00 mA = 15 ns CL (500 pF) Is the load capaCitance of typically 84 to 88 dynamic RAMs, in other words, four banks comprising 16 data bits and possibly six check bits if error correction is required. In fact, due to the trace inductance, the rate of change of current will not be a step function, so that the current waveform looks like a spike. Even so, the rapid rate of change of current, di/dt, into the trace inductance L, will create a potentially excessive voltage "e" across this Inductance. As an example, if the current changes from 0 to 100 mA in 6 ns, and the composite trace inductance Is 0.3 p.H, then the voltage across this inductance is "e,"where, e = Ldi/dt = 0.3 p.H x 100 mAl6 ns = 5V In other words, at this rate of change In current, even a small Inductance can be dangerous for two reasons. First, the dynamic RAMs at the far end of the trace could be destroyed, unless they have clamping diodes to Vce and GND (most do not), or second, the returning voltage may exceed the threshold it has Just passed causing a second OVERSHOOT AND UNDERSHOOT (Undershoot is Negative Overshoot) When a system requires a number of dynamic RAMs, the result is high capacitance loads, caused by a combination of RAM input capacitance and trace capacitance. Each dynamic RAM has a specified input capacitance of 10 pF maximum, but most dynamic RAMs are closer to 2 to 3 pF. Very few actually get close to 10 pF, even under worst case conditions of high temperature and Vce. It is safe, therefore, to assume a much lower average input capacitance when using 16 or more RAMs. In fact, the input capacitance of most inputs is due more to the package than the Input gating, because the silicon gate inputs of the transistors In today's market have such high Impedance. A typical maximum would be 2.5 pF. Control inputs such as RAS and ~ connect to more than one transistor input. For example, on the National Semiconductor 64k x 1 dynamic RAM, the NMC4184, RAS goes to two transistors and CAS to four. In general, this is true for most 1-203 ~ • ! .and then third change of state. If this sudden glitch occurs on a control signal input such as RAS. the memory contents may be inadvertently changed. Some Ie manufacturers offer octal memory drivers with onchip series resistors fixed at ::::: 250. Unless this is the critical value required for all the lines. problems will arise. The DP8400 family has been deSigned with equivalent internal values of approximately 100. allowing for any external value of damping resistor. It is therefore necessary to remove the spike. The most common approach is to insert a damping resistor in the path between the driver and the RAMs. fairly close to the driver. as shown by RD in Figure 2a. The best value for the resistor is the critical value giving a critically damped transition. Too high a value will cause overdamping which results in a slow transition. This slow edge may create excessive skew problems and slow down the memory cycle; or even worse. the edge may be slow enough that the RAM cycle never begins internally. If the damping resistor value is too low. the undershoot or overshoot may not be removed. It is therefore recommended that the resistor be determined on the first prototypes (not wire-wrapped prototypes because the value will be different due to the larger distributed inductance and capacitance). Also. the values may be different for the control lines. particularly ~. If there are a number of banks. and a RAS is used to select each bank. then the damping resistor in this line will be higher. SWITCHING CURRENT SPIKES Another major undesirable effect of the fast current spikes is the effect on the Vee and GND pins. The worst case is when all eight or nine address outputs switch in the same direction at the same time. as shown in Figure 3a. If each driver can source or sink 100 mAo then a current of approximately 1A could enter or exit the driver chip in a period of 20 ns. The resistance and inductance of the Vee and GND lines to the chip can cause excessive drops during this switching time (see waveforms in Agure 3a). which may. in turn. upset latches either in the DP8408A1DP8409A. or externally. A ceramic capacitor connected across Vee and GND pins will largely remove the spike. A 1 /JoF multilayer ceramic is recommended. This should be fitted as close as possible to the pins in order to reduce lead inductance. The DP8408A1DP8409A pin configuration facilitates this with Typical values for the damping resistors will be between 150 and 1000. the lower the loading. the higher the values. Ii-BIT MICROPROCESSOR DATA BUS RAMS MAY BE 16k OR 64k RAM ADDRESS BUS QO-7 Rn3 !lUr !lUI tmo DM SELECT UPPER BYTE 74S244 1-----..... BELECT LOWER BYTE NECESSARY IF MORE THAN ONE BANK TL/F/5031-1 FIGURE 1. Typical 16-Blt Memory with Byte Write Address 1-204 r---------------------------------------------------------~~ Z ~ UI VCC Tt-D "'' .oo~". . . l ~RIVER ~ ~ 1.--1.....-----rrrn-~~l-~_c.,l L-n J.cs'J. CIN' , J.CSnJCINn C=I(CS+CIN), L=IL ,= lOll FOR OP8408A/09A OV Of 0P84240/244 -: TL/F/5031-2 FIGURE 2a. Complex Load Impedance Caused by Distributed Trace Inductance L and Capacitance Cs, and RAM Input Capacitance CIN I A'-_ ~DRIVERI CURRENT I ~ NO RO OR RD TOO LOW ~ ~U::l: ~C OVERDAMPED RD (RO TOO HIGH) 0 1 ____ ~- I II IF RETURNING OSCILLATOR IS TOO HIGH, A GLITCH MAY OCCUR r. OV _._I_\-+~..- -,-- _____--J _FA_S_T_ED_G_E_WI_TH_N_O_O_V_ER_SH_O_OT--If I"~/ EDGE TOO SLOW /" ,/ , TLlF/5031-3 FIGURE 2b. Timing Waveforms Showing the Effect of Variations of RD on Signals Appearing at the RAM GND and Vee pins 0.2" apart so that the ceramic capacitor can be fitted as close to the chip as possible. The second GND pin should also be decoupled. These GND and Vee pins are located in the center of the package to reduce bonding lead lengths. In fact, the lead resistance is five times lower than if the supply pins were in the corners. An example of how this spike can be reduced would be the previous example of a 1A change in supply current switching in 20 ns with a 1 ,...F ceramic capaCitor decoupling GND and Vee. The voltage drop "v" is 1AX20 ns/1 ,...F, or 20 mV. ommended. As a further recommendation, the dynamic RAMs should be similarly decoupled with approximately a 0.1 ,...F ceramic capaCitor on each RAM. Wire-wrapped boards, in particular, need speCial attention. There are some other precautions that may be considered when driving memories. First, be aware that IC sockets increase load capacitance and inductance, so it becomes a matter of the importance of removability of chips, and maintainability. Also, shorter, thicker trace lengths will reduce the load, and good GND and Vee connections will help reduce the voltage spikes around the memory board. For wirewrapped deSigns, GND and Vee should be multiwired. If the decoupling capaCitor was 0.01 ,...F, the drop would be 2V. Tantalum or other types of capacitors are lower frequency capaCitors and have only a small effect in reducing the voltage spike. Ceramic capaCitors are high frequency, and multilayer capacitors with lower inductance have a greater effect in reducing the voltage spike and are therefore rec- With proper decoupling and correct selection of damping resistors, integrated circuit dynamic RAM controllers will function as expected to ease the burden of the system designer. 1-205 • I EXTERNAL INTERNAL BONOING RESISTANCE ... V'CC SUPPLY RAIL RESISTANCE VCC VCC icC0 r OORIYER t- RD I I OORIVER r GNO' CDiCL) ::!: CL 0* : : CDECDUPLE BDNDING RESISTANCE ONO ~CL SUPPLY RAIL RESISTANCE ICC .G), - GNO TL/F/S031-4 FIGURE 38. Effect of Switching All Outputs Simultaneously In the Same Direction ~.m ~ CD ~_~_~I___r 1 -V\\-+ISC I IC OA-----J, -I V'CC-GNO AT \ -ISC-\L - ~WITH GOOD OECOUPLING ~ - WITH INADEQUATE OECOUPLING FIGURE 3b. Timing Waveforms Showing Internal Supply Rail Drops During Output Switching 1·206 TLlF/5031-5 DP8408A/09A/17/18/191 28/29 Application Hints National Semiconductor Application Brief # 1 Tim Garverick Webster Meier The DPB40BA, DPB409A dynamic RAM controllers have been well received by dynamic memory users because they perform functions formerly requiring multiple integrated circuit chips. These controllers are designed to be suitable for a variety of DRAM control methods. As a result of the many combinations of ways in which inputs to these chips may be varied, it was inevitable that certain conditions exist that would cause the DPB40BA, DPB409A to respond in an undesirable way. Feedback from customers using these chips has resulted in thorough investigations of such conditions. The following are constraints on the use of the DRAM controllers which are not addressed in their data sheets. The majority of customers will find that most of the items on this list are not pertinent to their particular application, and those that are impose minimal restrictions. B) 1) The on-chip refresh counter resets when the RFI/O pin goes low for a refresh request in mode 5 if this pin is excessively loaded with capaCitance. The data sheet suggests that this pin not be loaded with greater than 50 pF. Since RFI/O, in most cases, needs only to drive a low capacitance in a refresh control circuit, this limit is not unreasonable. 2) When the DPB40BA, DPB409A is in a refresh mode, the RFI/O pin indicates that the on-Chip refresh counter has reached its end-of-count. This end-of-count is selectable as 127, 255 or 511 (511 is available only on the DPB409A) to accommodate 16k, 64k or 256k DRAMS, respectively. Although the end-of-count may be chosen to be any of these, the counter always counts to 511 (255 for the DPB40BA) before rolling over to zero. 3) When going from mode 0, 1 or 2 (refresh) to mode 5 of the DPB40BA, if CASIN and RIC are both low, a glitch occurs on the CAS output. Since neither of these inputs is used in these modes, one or both should be held high. 4) Most DRAMs specify 0 ns row address set-up time to RAS. In order to guarantee this, the row address to the DPB40BA, DPB409A must be valid 10 ns before RASIN transitions low to initiate an access. In terms of the data sheet parameters, maximum (tAPD-tRPDLl = 10 ns. 5) When changing modes from refresh to access, again sufficient time must be allowed for the row address to be valid before RAS occurs. In this case, the address outputs of the DPB40BA, DPB409A are changing from the refresh counter to the row address inputs. In order for the row address to be set up a minimum of 0 ns before RAS goes low, RASIN should not go low until 30 ns after the change from refresh to access mode. 6) Both the low and high pulse widths of RAS have minimum requirements during refresh. When in mode 0, the RASIN to RAS low delay is longer than the RASIN to RAS high delay. In terms of the data sheet parameters, maximum (IRFPDL -tRFPDH) = 25 ns. Thus, the minimum low pulse width of RAS in mode 0 equals the RASIN low pulse width minus 25 ns. The minimum high pulse width of RAS in mode 0 equals the RASIN high pulse width. 7) The fastest memory access may be accomplished using mode 4 and external delay lines (see App. Brief #9). 9) In the data sheet, it is specified that CS should go low 30 ns (tCSLR) before RASIN goes low to initiate an access in mode 5. This is to prevent the possibility of a glitch on the RAS outputs, resulting from the DPB409A interpreting the RASIN as a hidden refresh. For the same reason, CS should be held low for a minimum of 15 ns after RASIN returns high, ending the access in mode 5. If the DPB409A is being used in mode 5 and CS = 1, and if RASIN goes low within 15 ns before RFCK (RIC) goes low, up to a 15 ns glitch may occur on the refresh request pin, RFI/O. However, since CS is high, a hidden refresh will occur as it normally would with RFCK high. If the glitch on RFI/O were detected and interpreted as a forced refresh request, no forced refresh would be allowed by the DPB409A since a hidden refresh was allowed. This would not cause any problem, however, since the hidden refresh has taken care of the refresh requirement for that period of RFCK. Also, this forced refresh request could not be detected if the system does not check RFI/O for a low state while RASIN is low (i.e., an access is taking place). 10) At CPU clock frequencies of 10 MHz and above it is suggested that the hidden refresh capability of the DRAM controller (DPB409/17/19/29) be disabled. The main reason for this suggestion is to satiSfy the parameter "tRKRL" (RFCK high to RASIN low for hidden refresh) which is given as a minimum of 50 ns in the DP8417/19/29 data sheets. Disabling hidden refresh also eliminates the need of meeting the parameter of "tcSRL1" (CS low to access RASIN low using Mode 5 with hidden refresh capability) which is given as a minimum of 34 ns in the DP8417/19/29 data sheets. In order to eliminate hidden refresh the "CS" pin of the DRAM controller should be permanently grounded on the DRAM controller, and the "CS" that previously went to the DRAM controller should be "ORed" with "RASIN" (the "OR" gate's output becoming the new "RASIN" input to the DRAM controller). 11) If the user desires to improve the DRAM controller "RASIN to RAS out" time ("tRPDL") external logic may be used to create multiple "RASs". The circuit shown below requires only several 74XX oxide isolated type IC's (74AS27 and 74AS04) to accomplish this aim. To use this circuit RASIN should transition low during refreshes. 1-207 74AS27 80...,---r.... 74AS04 81 RASIN RAS2 TLlF/5033-1 • d; National Semiconductor Application Brief Tim Garverick Rusty Meier « DP8408A/9A Fastest DRAM Access Mode If one desires the fastest possible operation of the DP8408A19A multi-mode dynamic RAM controllerldriver in accessing DRAMs, mode 4, externally controlled access mode should be considered. In using mode 4 there are three input signals which must be considered: 1) RASIN-generates RAS 2) RIC-switches between rows and columns on the address outputs 3) CASIN-generates CAS The equation for the delay between RIC and CASIN that guarantees the specified DRAM tASC is: min delay required = tOlF2 = 13ns where tASC = DRAM minimum column address set-up time to CAS To produce the above-mentioned delays between signals, a ± 2 ns resolution delay line can be used as follows: (assuming tRAH = 20 ns, tASC = 0 ns) RASIN to RIC delay = 13 ns + 20 ns = 33 ns In producing these signals a delay will be needed between RASIN and RIC and between RIC and CASIN. (Note: In mode 4 external generation of CASIN can produce CAS faster than automatic generation of CAS.) Two important parameters have been added to the DP8408A19A data sheets that help one compute the minimum acceptable delays between the above-mentioned signals. These parameters are: 1) tOlF1 = MAXIMUM (tRPOl - tRHA) = 13 ns where tRPOl = RASIN to RAS delay tRHA = row address held from column select + tRAH + tRAH where tRAH = DRAM minimum row address hold time from RAS = 13 ns = 13 ns Thus, RIC must follow RASIN by a minimum of 33 ns and CASIN must follow RIC by a minimum of 13 ns. With a delay line of ± 2 ns resolution, the RASIN to RIC and RIC to CASIN delays can be typicals of 35 ns and 15 ns, respectively. (See Figures 1 and 2.) This scheme will provide a maximum RASIN to CAS delay of: + 15 ns + 2 ns (resolution uncertainty) + MAXIMUM (tcpoLl tCPOl = CASIN to CAS delay These parameters are specified as being less than what would be calculated using the minImax values given for tRCC, tCPOl, tRPOl and tRHA in the DP8408A19A specification sheets, because on-chip delays track over temperature and supply variations. The equation for the delay between RASIN and RIC that guarantees the specified DRAM tRAH is: min delay required = tOlF1 RIC to CASIN delay = 13 ns + 0 ns 35 ns 2) tOlF2 = MAXIMUM (tRCC - tcpoLl = 13 ns where tRCC = column select to column address valid + tASC + tASC = 52 ns + MAXIMUM (tcpoLl For the DP8408/9-2, MAXIMUM (tcpoLl = 58 ns. For the DP8408A19A (no dash), MAXIMUM (tcpoLl = 68 ns (not 58 ns as indicated in data sheets up to November 1982). The fastest mode 4 accesses (with the assumed delay line and DRAM parameters) are therefore, 110 ns and 120 ns, respectively, for the -2 and non-dash parts. The maximum RASIN to CAS delay (tRICLl in mode 5 (auto mode) for the DP8408/9-2 (which guarantees a min tRAH of 20 ns) is 130 ns. The maximum tRICl in mode 5 for the DP8408A19A (no dash) is 160 ns. Thus, it is shown that if the features offered by the DP8408A/9A automatic modes can be sacrificed, mode 4 (externally controlled access) may be used to obtain the fastest memory access. 1-208 » III . CD RIC a's COLUMN ADDRESS DATA - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ( FIGURE 1. Mode 4 Timing Relationships RIC TLiF/8403-2 FIGURE 2. Mode 4 Externally Generated Signals 1-209 TL/F/8403-1 Section 2 Error Detection and Correction Section 2 Contents 54F174F420 Parallel Check Bit/Syndrome Bit Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DP8400-2 E2C2 Expandable Error Checker/Corrector. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . DP8402A/DP8403/DP8404/DP8405 32-Bit Parallel Error Detection and Correction Circuits (EDAC's) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54F174F632 32-Bit Parallel Error Detection and Correction Circuit .... . . . . . . . . . . . . . . . . . . . . AN-306 Expanding the Versatility of the DP8400 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AN-308 DP8400s in 64-Bit Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2-3 2-4 2-38 2-55 2-56 2-68 .-----------------------------------------------------------------------------, ~National ~ Semiconductor 54F/74F420 Parallel Check Bit/Syndrome Bit Generator General Description The 'F420 is a parallel check bit/syndrome bit generator. The 'F420 utilizes a modified hamming code to generate 7 check bits from a 32-bit dataword, in 15 ns, when operated in the check bit generate mode. When operated in the syndrome generate mode, the check bits and data bits read from memory are utilized in a parity summer to generate syndrome bits upon error detection. The maximum error count detectable is 2. A single error detect can occur in 18 ns; a double error detect in 22 ns. The syndrome bit generation can be output in 15 ns (maximum). Logic Diagram Connection Diagrams Pin Assignment for Lee and pee De -so SEF- -S, DEF- -CB I I II I II TLIF19542-' t7 Pin Assignment for DIP and Flatpak Os Os D4GND NCVCCD3 02 0,00 Cs \IQ1U!lIOOIlll[!}irn~flll!i1l!TIl[QIOOII1 ~-, ~~ 0,0 illI rn~ [!) c4 0" ~ ~~ mel ~~ ~~ rns ~~ rn~ ~~ D,6 1!i1 ~% rn.n 5, ~~ ~- rn~ rn~ ~~ ~~ ~~ ~w ~~ ~~ \llI1I£~1llI~~~I!iI~illIlMIl!ID@ o"o"o"""."""NC",."",."""o,, TLIF19542-2 c,- 2 c,- , c,- • c.- s cs- 6 c,- 7 \.J 48\-5, '7\-5, .6\-SEF 45 OEF 44 CB 43 NC .2 0" 0,- 8 41 030 9 0, 0,- ,0 40 39 029 028 0, 11 38 027 Vet. 12 37 0" eND 13 ,. 36 GNO 35 025 3. \-0" 0, 15 ,6 0, ,7 08 18 32\-0" 3' \-0" .. ,9 20 30 t-D20 21 22 23 2. 28 t-D18 0. Os 0" 0" 0" 0" 0,. 33 023 29 t-D19 27 t-D17 26 t-D16 25 rD'5 TLlF19542-3 Unit Loading/Fan Out: See Section 1 for U.L. definitions 54F174F Pin Names Co-Ce 00- 0 31 CB DEF SEF SO,S1 ~ ~ CI Description U.L. HIGH/LOW Check Bit/Syndrome Bus Inputs/ Outputs Data Bit Bus Check Bit Control Double Error Flag Single Error Flag Mode Control 3.5/1.083 150/40 (33.3) 1.011.0 1.0/1.0 50/33.3 50/33.3 1.011.0 2-3 Input IIHIIIL Output IOH/IOL 70 }J-A/ - 0.65 mA -3 mA/24 mA (20 mAl 20 }J-AI -0.6 mA 20 }J-A/ -0.6 mA -1 mA/20mA -1 mA120mA 20 }J-A/ -0.6 mA t?'A National ~ Semiconductor DP8400-2-E2C2 Expandable Error Checker/Corrector General Description The DP8400-2 Expandable Error Checker and Corrector (E2C2) aids system reliability and integrity by detecting errors in memory data and correcting single or double-bit errors. The E2C2 data 110 port sits across the processormemory data bus as shown, and the check bit 110 port connects to the memory check bits. Error flags are provided, and a syndrome 110 port is available. Fabricated using high speed Schottky technology in a 48-pin dual-in-line package, the DP8400-2 has been designed such that its internal delay times are minimal, maintaining maximum memory performance. OATA BUS I SYSTEM CONTROL PROCESSOR I I~ t E'C' J SYNOROME BUS IMEMORY CHECK 81T BUS I The DP8400-2 has a separate syndrome I/O bus which can be used for error logging or error management. In addition, the DP8400-2 can be used in BYTE-WRITE applications (for up to 72 data bits) because it has separate byte controls for the data buffers. In 16 or 32-bit systems, the DP8400-2 will generate and check system byte parity, if required, for integrity of the data supplied from or to the processor. There are three latch controls to enable latching of data in various modes and configurations. Operational Features 16/32148/64 6171J!8 61718/8 memory check bits or DP8400-2s than the single-error correct configurations. I ERROR FLAGS TLiF 16899-1 For a l6-bit word, the DP8400-2 monitors data between the processor and memory, with its 16-bit bidirectional data bus connected to the memory data bus. The DP8400-2 uses an encoding matrix to generate 6 check bits from the 16 bits of data. In a WRITE cycle, the data word and the corresponding check bits are written into memory. When the same location of memory is subsequently read, the E2C2 generates 6 new check bits from the memory data and compares them with the 6 check bits read from memory to create 6 syndrome bits. If there is a difference (causing some syndrome bits to go high), then that memory location contains an error and the DP8400-2 indicates the type of error with 3 error flags. If the error is a single data-bit error, the DP8400-2 will automatically correct it. The DP8400-2 is easily expandable to other data configurations. For a 32-bit data bus with 7 check bits, two DP8400-2s can be used in cascade with no other ICs. Three DP8400-2s can be used for 48 bits, and four DP8400-2s for 64 data bits, both with 8 check bits. In all these configurations, single and double-error detection and single-error correction are easy to implement. When the memory is more unreliable, or better system integrity is preferred, then in any of these configurations, double-error correction can be performed. One approach requires a further memory WRITE-READ cycle using complemented data and check bits from the DP8400-2. If at least one of the two errors is a hard error, the DP8400-2 will correct both errors. This implementation requires no more • Fast single and double-error detection • Fast single-error correction • Double-error correction after catastrophic failure with no additional ICs or check bits • Functionally expandable to 100% double-error correct capability • Functionally expandable to triple-error detect • Directly expandable to 32 bits using 2 DP8400-2s only • Directly expandable to 48 bits using 3 DP8400-2s only • Directly expandable to 64 bits using 4 DP8400-2s only • Expandable to and beyond 64 bits in fast configuration with extra ICs • 3 error flags for complete error recording • 3 latch enable inputs for versatile control • Byte parity generating and checking • Separate byte controls for outputting data in BYTEWRITE operation • Separate syndrome I/O port accessible for error logging and management • On-chip input and output latches for data bus, check bit bus and syndrome bus • Diagnostic capability for simulating check bits • Memory check bit bus, syndrome bus, error flags and internally generated syndromes available on the data bus • Self-test of E2C2 on the memory card under processor control • Full diagnostic check of memory with the E2C2 • Complete memory failure detectable • Power-on clears data and syndrome input latches Timing Features l6-BIT CONFIGURATION WRITE Time: 29 ns from data-in to check bits valid DETECT Time: 21 ns from data-in to Any Error (AE) flag set CORRECT Time: 44 ns from data-in to correct data cut 2-4 c Timing Features (Continued) Pin # 1 2 3 4 5 6 7 13 14 15 16 17 18 19 20 21 22 23 28 29 30 31 34 35 36 37 38 39 40 41 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 62 63 64 65 66 68 32-BIT CONFIGURATION WRITE Time: 49 ns from data-in to check bits valid DETECT Time: 46 ns from data-in to Any Error (A E) flag set CORRECT Time: 84 ns from data-in to correct data out DP8400-2 Connection Diagram Dual-In-Line Package 48 004 47 003 005 006 007 008 009 0010 002 0011 0012 OP8400 Cl C2 16 32 31 30 29 28 27 26 25 C3 17 C4 18 C5 19 C6 20 BPO (C7) 21 DES 22 C5lE 23 BPI (57) 24 Top View Ml MO 80 81 52 53 54 85 56 Tl/F/6899-2 Order Number DP8400V-2, DP8400N-2, or DP8400D-2 See NS Package V68, N48A or D48A Chip Carrier Package NW NW 0011 0010009008 D07 D06 NW NW NW D012 D013 D014 0015 OBi GND GND CO Cl C2 C3 NW NW NW D04 NW D03 D02 DOl DOD OBO NW 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 ." Pin Descriptions NW NW 5IT Dlf EO AE GND GND XP Vee Vee El M2 Ml MO 50 51 00 .1:>0 Description D05 D06 D07 D08 D09 D010 D011 D012 D013 D014 D015 OBI GND GND CO C1 C2 C3 C4 C5 C6 BPO (C7) OE8 C8LE BPI (87) 86 85 84 83 82 81 80 MO M1 M2 E1 Vee Vee XP GND GND AE EO DLF OLE aBO DOO D01 D02 D03 D04 Note: Pins 8, 9, 10, ", 12, 24, 25, 26, 27, 32, 33, 42, 43, 59, 60, 61, and 67 are all NW. NW C4 C5 C6 BPO NW NW OE5 (C7) BPI 56 55 54 53 52 NW NW (57) C5lE TL/F/6899-36 Top View 2-5 Q Q I N • , Pin Definitions See Figure 1 for abbreviations OBO, OB 1: Output byte-O and output byte-1 enables. These inputs, when low, enable DOLO and DOL 1 through OOBO and DOB1 onto the data bus pins DOO-D07 and D08D015. When OBO and OB1 are high the DOBO, DOB1 outputs are TRI-STATE®. Vee, GNO, GNO: 5.0V ±5%. The 3 supply pins have been assigned to the center of the package to reduce voltage drops, both DC and AC. Also there are two ground pins to reduce the low-level noise. The second ground pin is located two pins from Vee, so that decoupling capacitors can be inserted directly next to these pins. It is important to adequately decouple this device, due to the high switching currents that will occur when all 16 data bits change in the same direction simultaneously. A recommended solution would be a 1 /LF multilayer ceramic capacitor in parallel with a low-voltage tantalum capacitor, both connected close to pins 36 and 38 to reduce lead inductance. OES: Output enables syndromes. I/O control of the syndrome latches. When high, SOB is TRI-STATE and external syndromes pass through the syndrome input latch with CSlE high. When OES is low, SOB is enabled and the generated syndromes appear on the syndrome bus, also CSlE is inhibited internally to SIL. MO, M 1, M2: Mode control inputs. These three controls define the eight major operational modes of the DP8400-2. Table III depicts the modes. 000-0015: Data I/O port. 16-bit bidirectional data bus which is connected to the input of OllO and 0111 and the output of OOBO and 00B1, with 008-0015 also to CIL. System Write (Figure 2a) CO-C6: Check-bit 110 port. 7-bit bidirectional bus which is connected to the input of the Cil and the output of the COB. COB is enabled whenever M2 is low. The Normal WRITE mode is mode 0 of Table III. Referring to the block diagram in Figure 9a and the timing diagram of Figure 9b, the 16 bits of data from the processor are enabled into the data input latches, OllO and Dll1, when the input data latch enable (DlE) is high. When this goes low, the input data is latched. The check bit generator (CG) then produces 6 parity bits, called check bits. Each parity bit monitors different combinations of the input data-bits. In the 16-bit configuration, assuming no syndrome bits are being fed in from the syndrome bus into the syndrome input latch, the 6 check bits enter the check bit output latch (COL), when the output latch enable OLE is low, and are latched in when OLE goes high. Whenever M2 (READ/WRITE) is low, the check bit output buffer COB always enables the COL contents onto the external check bit bus. Also the data error decoder (DED) is inhibited during WRITE so no correction can take place. Data output latches DOLO and DOL 1, when enabled with OLE, will therefore see the contents of DllO and Dill. If valid system data is still on the data bus, a memory WRITE will write to memory the data on the data bus and the check bits output from COB. If the system has vacated the data bus, output enables (OBO and OB1) must be set low so that the original data word with its 6 check bits can be written to memory. SO-S6: Syndrome I/O port. 7-bit bidirectional bus which is connected to the input of the Sil and the output of the SOB. OLE: Input data latch enable. When high, OllO and 0111 outputs follow the input data bus. When low, OllO and 0111 latch the input data. CSLE: Input check bit and syndrome latch enable. When high, Cil and Sil follow the input check and syndrome bits. When low, Cil and Sil latch the input check and syndrome bits. If OES is low, Sil remains latched. OLE: Output latch enable. OLE enables the internally generated data to DOLO, and DOL 1, COL and SOL when low, and latches when high. XP: Multi-expansion, which feeds into a three-level comparator. With XP at OV, only 6 or 7 check bits are available for expansion up to 40 bits, allowing byte parity capability. With XP open or at Vee, expansion beyond 40 bits is possible, but byte parity capability is no longer available. When XP is at Vee, CG6 and CG7, the internally generated upper two check bits, are set low. When XP is open, CG6 and CG7 are set to word parity. BPO (C7): When XP is at OV, this pin is byte-O parity I/O. In the Normal WRITE mode, BPO receives system byte-O parity, and in the Normal READ mode outputs system byte-O parity. When XP is open or at Vee, this pin becomes C7 I/O, the eighth check bit for the memory check bits, for 48-bit expansion and beyond. System Read There are two methods of reading data: the error monitoring method (Figure 2b), and the always correct method (Figure 2c). Both require fast error detection, and the second, fast correction. With the first method, the memory data is only monitored by the E2C2, and is assumed to be correct. If there is an error, the Any Error flag (AE) goes high, requiring further action from the system to correct the data. With the always correct method, the memory data is assumed to be possibly in error. Memory data is removed and the corrected, or already correct, data is output from the E2C2 by enabling OB1 and OBO. To detect an error (referring to Figures 10a and 10b) first OLE and CSlE go high to enter data bits and check bits from memory into DllO, DOL 1 and CIL. The 6 check bits generated in CG from DllO and DOL 1 are then compared with Cil to generate syndromes on the internal syndrome bus (SG). Any bit or bits of SG that go high indicate an error to the error encoder (EE). BP1 (S7): When XP is at OV, this pin is byte-1 parity I/O. In the Normal WRITE mode, BP1 receives system byte-! parity, and in the Normal READ mode outputs system byte-1 parity. When XP is open or at Vee, this pin becomes S7 I/O, the eight syndrome bit for 48-bit expansion and beyond. AE: Any error. In the Normal READ mode, when low, AE indicates no error and when high, indicates that an error has occurred. In any WRITE mode, AE is permanently low. EO: In the Normal READ mode, EO is high for a single-data error, and low for other conditions. In the Normal WRITE mode, EO becomes PEO and is low if a parity error exists in byte-O as transmitted from the processor. E1: In the Normal READ mode, E1 is high for a Single-data error or a single check bit error, and low for no error and doubie-error. In the Normal WRITE mode, E1 becomes PE1 and is low if a parity error exists in byte-1 as transmitted from the processor. 2-6 , -~ -- XP ; .... BPO ) , , OLE B 5~ L)E>- ") 01, D~ BYTE PARITY GENERATOR 2 ---- ..;t. DATA INPUT LATCH 0 CHECK BIT GENERATOR 0-5 B, B - ---- J,4 "--- CG6.7 .I BYTE PARITY ERROR DETECTOR CG \ s: ~ ... ~~ r? .... B SG I ~: B, CLR , ~ ' ....[}] ..... PE ":» . . . .,.. [!] B 7 1D:t ;:J, INH DATA BIT ERROR DETECTOR DATA OUTPUT LATCH 1 r+ DATA OUTPUT BUFFER 1 W- OCO DATA OUTPUT LATCH 0 ~ OATA OUTPUT BUFFER 0 ..!r" OED CHECK BIT OUTPUT LATCH B 0 ... 7 1 - - CHECK BIT OUTPUT BUFFER ~ ~ 7. B MODE DECODER ERROR ENCODER ~D B OLE" 6 ~ EDT 0 SYNDROME INPUT LATCH B, DCl V'll8j ~Il m-Bt, I V f--+ Jry,t. DE1'- / CC SI 7. B '--.. .... , INH ,,,80-6.7 ,,, .... f- - - - .... I ~ CSLE 0-3 I B ...." '" III ALL ZERO SYNDROMES 1.5 ,, . JIBij ooB- 15 DQJ CHECK BIT INPUT LAX H '--- I}> I I 2 ~t I""""'=" 'f ¥DOD.7 DATA BUS .--DATA INPUT LATCH 1 BPI PSG ~ +-@I SYNDROME OUTPUT LATCH r--- CO-6. '\J SYNDROME OUTPUT -fl..B BUFFER DES SYNDROME BUS CHECK BIT BUS , .. AE Dil CG Cil CC Sil PSG Data Input Latch Check Bit Generator Check Bit Input Latch Check Bit Complementor Syndrome Input Latch Partial Syndrome Generator SG DED DEO,I PE DOLO, 1 COL Syndrome Generator Data Error Detector Data Error Bytes 0, 1 Parity Error Data Output Latch Bytes 0, t Check B~ Output Latch , ., SOL DOBO,I COB SOB EE DCO,I ~ .. ED Mo-2 Syndrome Output latch Data Output Buffer Bytes 0, t Check Bit Output Buffer Syndrome Output Buffer Error Encoder Data Corrector Bytes 0, 1 ~ mode of operation signifies active signal 6899-3 FIGURE 1. DP8400-2 Block Diagram ~·OOt8da II N 6 ~ System Diagrams-Modes of Operation ~ Q ~ A DATA 'l#ffi I PROCESSOR BYTE PARITY I I DATA II' "1 i"- WRITE DATA ~L p. E/po,1 DQ E1 ANY ERROR EICI MEMORY ----J BYTE PARITY ERROR { I LOW : LOW C M2 M1 MD fll '=' 0:1 ~ CHECK BITS WRITE CHECK BITS TLlF/6899-4 FIGURE 2a. Normal WRITE Mode with E2C2 DATA PROCESSOR INTERRUPT READ TL/F/6899-5 FIGURE 2b. Normal READ Mode, Error Monitoring Method with E2C2 DATA PROCESSOR DATA ERROR·PRONE MEMORY DATA DATA BYTE PARITY MEMORY INTERRUPT READ AE EICI CHECK BITS HIGH TLlF/6899-6 FIGURE 2c. Normal READ Mode, Always Correct Method with E2C2 2-8 System Read one or two check bit errors) are the two sets of syndromes for each individual error bit, XOR-ed together. By performing a parity check on the syndrome bits, flag E1 will indicate even/odd parity. If there is still an error, but it is not one of these errors, then it is a detectable triple-bit error. Some triple-bit errors are not detectable as such and may be interpreted as single-bit errors and falsely corrected as singledata errors. This is true for all standard ECC circuits using a Modified Hamming-code matrix. The DP6400-2 is capable, with its Rotational Syndrome Word Generator matrix, of determining all triple-bit errors using twice as many DP8400-2s and twice as many check bits. (Continued) If data correction is required OBO and 0Eff must be set low (after memory data has been disabled) to enable data output buffers DOBO and DOB1. The location of any data bit error Is determined by the data error decoder (DED), from the syndrome bits. The bit in error Is complemented in the DOL for correction. The other 15 bits from DED pass the DIL contents directly to the DOL, so that DOL now contains corrected data. Error Determination The three error flags, for a 16-bit example, are decoded from the internally generated syndromes as shown in Figure 3. First, if any error has occurred, the generated check bits will be different from the memory check bits, causing some of the syndrome bits to go high. By OR-ing the syndrome bits, the output will be an indication of any error. Error Flags Three error flags are provided to allow full error determination. Table I shows the error flag outputs for the different error types in Normal READ mode. If there is an error, then ANY ERROR will go high, at a time tOEV (Figure tOb) after data and check bits are presented to the DP8400-2. The other two error flags EO and E1 become valid tOEO and tOE1 later. If there is a single-data error, then (from the matrix in Table IV) it can be seen that any data error causes either 3 or 5 syndrome bits to go high. 16 AND gates decode which bit is in error and the bit in error is XOR-ed with the corresponding bit of the DIL to correct it, whereas the other 15 decoder outputs are low, causing the corresponding 15 bits in DIL to transfer to DOL directly. DOL now contains corrected data. The 16 AND gate outputs are OR-ed together causing EO to go high, so that EO is the single-data-error indication. If the error is a double-error, then either 2, 4 or 6 of the syndrome bits will be high. The syndromes for two errors (including The error flags differentiate between no error, single check bit error, single data-bit error, double-bit error. Because the DP8400-2 can correct double errors, it is important to know that two errors have occurred, and not just a multiple-error indication. The error flags will remain valid as long as DLE and CSLE are low, or if DLE is high, and data and check bits remain valid. Byte Parity Support SG. II! Some systems require extra integrity for transmission of data between the different cards. To achieve this, individual byte parity bits are transmitted with the data bits in both directions. The DP8400-2 offers byte parity support for up to 40 data bits. If the processor generates byte parity when transferring Information to the memory, during the WRITE cycle, then each byte parity bit can be connected to the corresponding byte parity I/O pin on the DP8400-2, either BPO or BP1. The DP8400-2 develops its own internal byte parity bits from the two bytes of data from the processor, and compares them with BPO and BP1 using an exclusiveOR for both parities. The output of each exclusive-OR is fed to the error flags EO and E1 as PEO and PE1, so that a byte parity error forces its respective error flag low, as in Table II. These flags are only valid for the Normal WRITE (mode 0) and XP at OV. The DP8400-2 checks and generates even byte parity. ANY SYNDROME BIT ANY ERROR DETECT 3 OR 5 SYNDROME BITS SINGLE DATA ERROR ED When transferring information from the memory to the processor, the DP8400-2 receives the memory data, and outputs the corresponding byte parity bits on BPO and BP1 to the processor. The processor block can then check data integrity with its own byte parity generator. If in fact memory data was in error, the DP8400-2 derives BPO and BP1 from the corrected data, so when corrected data is output from the DP8400-2, the processor will not detect a byte parity error. E1 During the read mode, DP8400-2 corrects single data bit error and also its parity. INTERNAL SYNDROME BUS TL/F 16899-7 FIGURE 3. Error Encoder 2-9 • ! TABLE I. Error Flags After Normal Read (Mode 4) TABLE II. Error Flags after Normal Write (Mode 0) AE E1 (PE1) EO (PEJ) Error Type 1 1 No parity error 1 0 Parity error, byte 0 0 1 Parity error, byte 1 0 Parity error, bytes 0, 1 AE E1 EO Error Type 0 0 0 No error 0 1 1 0 Single check bit error 0 1 1 1 Single·data error 0 1 0 0 Double·bit error 0 0 All Others Invalid conditions TABLE III. DP8400-2 Modes of Operation M2 M1 MO Mode (R/W) OES Operation 0 0 0 0 X Normal WRITE Oil DOL, CG - COL - COB 1 0 0 1 X Complement WRITE Oil DOL, Cil - COL - COB 2 0 1 0 X Diagnostic WRITE, OLE inhibited D08-D015e CG SOL SOB D08-D015 Cil COL COB 3 0 1 1 X Complement data-only WRITE Oil DOL, (CGO, 1,4, 5, CG2, CG3) COL - 4 1 0 0 X Normal READ Oil e DE _ DOL, Cil - COL COL COB 5 1 0 1 X Complement READ Oil e DE _ DOL, GiL 6A 1 1 0 0 READ generated syndromes, check bit OOO-OQ6, bus, error flags, SGO-SG6 CllO-Cll6 008-0014, E1 007, EO 0015 6B 1 1 0 1 READ syndrome bus, check bit bus, error 000-006, flags, SllO-Sll6 CllO-Cll6 008-0014, E1 007, EO 0015 7A 1 1 1 0 Generated syndromes replace with zero Sil SG, Cil COL, Oil e DE DOL - o,7B 1 1 1 1 Generated syndromes replace Sil SG, Cil COL, Oil e DE - DOL TABLE IV. Data-In To Check Bit Generate, Or Data Bit Error To Syndrome-Generate Matrix (16-Bit Configuration) o o GENERATED SYNDROMES 2 3 4 5 2 3 GENERATE CHECK 0 0 1 1 0 0 0 1 1 0 1 0 0 1 1 0 1 1 0 0 1 1 1 0 4 8 9 3 3 2 \. 'C2, C3 generate odd parity 7 0 4 5 BITS 1 1 0 1 0 0 1 0 0 0 1 1 5 2 3 1 1 1 1 1 6 7 8 9 o 2 3 4 5 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 0 0 1 1 1 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 1 B 0 D 0 3 } • 0 0 0 1 1 1 0 3 9 0 0 2 E 3 . 0 HEXADECIMAL EQUIVALENT OF SYNDROME BITS 2-10 o 1 1 0 1 1 1 1 1 1 0 4 5 C 7 0 3 F 2 F 2 0 000-15 2' 3' GENERATED CHECK BITS I TUF/6899-8 Modes of Operation There are three mode-control pins, M2, M1 and MO, offering 8 major modes of operation, according to Table III. M2 is the READ/WRITE control. In normal operation, mode o is Normal WRITE and mode 4 is Normal READ. By clamping MO and M1 low, and setting M2 low during WRITE and high during READ, the DP8400-2 is very easy to use for normal operation. The other modes will be covered in later sections. sented to the DP8400-2, where it is fed through DILO and DIL1 to the check bit generator. This generates 6 parity bits from different combinations of data bits, according to Table IV. The numbers in the row below the table are the hexadecimal equivalent of the column bits (with bits 6, 7 low). A "1" in any row indicates that the data bit in that column is connected to the parity generator for that row. For example, check bit 1 generates parity from data bits 3, 6, 8, 9, 11, 13, 14, and 15. Check bits 0, 1, 4, 5, and 6 generate even parity, and check bits 2 and 3 generate odd parity. This is done to insure that a total memory failure is detected. If all check bits were even parity, then all zeroes in the data word would generate all check bits zero and a total memory failure would not be detected when a memory READ was performed. Now allzero-data bits produce C2 and C3 high and a total memory failure will be detected. When reading back from the same location, the memory data bits (possibly in error) are fed to the same check bit generator, where they are compared to the memory check bits (also possibly in error) using 6 exclusive-OR gates. The outputs of the XORs are the syndrome bits, and these can be determined according to Table IV for one data bit error. For example, an error in bit 2 will produce the syndrome word 101001 (for S5 to SO respectively). The syndrome word is decoded by the error encoder to the error flags, and the data-error decoder to correct a single data bit error. Assuming the memory data has been latched in the DIL, by making DLE go low, memory data can be disabled. Then by setting OBO and OB1 low, corrected data will appear on the data bus. The syndromes are available as outputs on pins SO-5 when DES is low. It is also possible to feed in syndromes to SIL when DES is high and CSLE goes high. This can be useful when using the Error Management Unit shown in Figure 4. C6 and S6 are not used for 16 bits. It is safe therefore to make C6 appear low, through a 2.7 kO resistor to ground. The same applies for S6 if syndromes are input to the DP8400-2. If DES is permanently low, S6 may be left open. Any 16-bit memory correct system using the DP8400-2 without syndrome inputs must keep the DES pin grounded, then all the syndrome I/O pins may be left open. The reason for this is that the DP8400-2 resets the syndrome input latch at power up. If the DES pin is grounded, the syndrome input latch will remain reset for normal operations. 16-BIT CONFIGURATION The first two rows on top of the check bit generate matrix (Table IV) indicate the data position of DOO to D015. The left side of the matrix, listed 0 to 5, corresponds to syndromes SO to S5. SO is the least significant syndrome bit. There are two rows of hexadecimal numbers below the matrix. They are the hex equivalent of the syndrome patterns. For example, syndrome pattern in the first column of the matrix is 001011. Its least significant four bits (0010) equal hexadecimal 4, and the remaining two bits (11) equal hexadecimal 3. Check bit generation is done by selecting different combinations of data bits and generating parities from them. Each row of the check bit generate matrix corresponds to the generation of a check bit numbered on the right hand side of the matrix, and the ones in that row indicate the selection of data bits. The following are the check bit generate equations for 16-bit wide data words: CGO = D02 e D03 e D04 e D05 e D06 e D07 e D09 e D010 e D011 e D013 e D014 e D015 CG1 = D03 e D06 e D08 e D09 e D011 e D013 e D014 e D015 'CG2 = DOO e D03 e 004 e D08 e D010 e D012 e D013 e D014 e D015 e 1 'CG3 = D01 e D02 e D07 e D08 e D09 e D010 e D012 e D014 e D015 e 1 CG4 = DOO e D01 e D05 e D07 e D08 e D011 e D013 e D015 CG5 = DOO e D01 e D02 e D04 e D05 e D06 e D08 e D012 e D013 e D014 'CG2 and CG3 are odd parities. The following error map (Table V) depicts the relationship between all possible error conditions and their associated syndrome patterns. For example, if a syndrome pattern is SO-5 = 111101, data bit 14 is in error. The parameter tNMR (see Figure 10b), new mode recognized time, is measured from M2 (changing from READ to WRITE) to the valid check bits appearing on the check bit bus, provided the OLE was held low. Figure 4 shows how to connect one DP8400-2 in a 16-bit configuration, in order to detect and correct single or double-bit errors. For a Normal WRITE, processor data is pre- The parameter tMCR (see Figure 10b), mode change recognized time, is measured from M2 (changing from WRITE to TABLE V. Syndrome Decode To Bit In Error For 16-Bit Data Word SO Syndrome Bits S1 S2 S3 0 0 0 0 1 0 0 0 0 1 0 0 1 1 0 0 0 0 1 0 1 0 1 0 0 1 1 0 1 1 1 0 0 0 0 1 1 0 0 1 0 1 0 1 1 1 0 1 0 0 1 1 1 0 1 1 0 1 1 1 1 1 1 1 S5 S4 0 0 NE CO C1 D C2 D D 3 C3 D D 9 D 10 T D 0 1 C4 D D 11 D T T D D 7 T D T D D 15 1 0 C5 D D 6 D 4 T 0 D 2 T D 12 D D 14 1 1 D 5 T D 0 D D 13 1 D D T D T 8 D NE~no error Cn ~ check bit n in error T ~ three errors detected Number~ single 2-11 data bit in error D = two bits in error ~ I SYSTEM { BPI BYTE PARITY (IF REQUIRED) BPO MEMORY m BPI DP8400 ERROR MANAGEMENT 1---+--t~1 UNIT (IF REQUIRED) EO El M2 Ml R 2.7 kn ~ Necessary only when incorporating double complemenl correct. Otherwise connect C6 to GND Ihrough R. • Necessary when inputting syndromes, otherwise leave open. . t Refer-Io-discussion in "Olher Modes of Operation" under Clearing 51 L. . ERROR "20 ns max tpd1, 0 MODE CONTROL FLAGS TL/F/6899-9 FIGURE 4. 16·Bit Configuration Using One DP8400·2 ., ~ DATA BUS ~ PARITY ... DQO·15 BUS PI PO 000-31 !'- OQ16-31 P2 P3 ID BYTE { ABLES rn I!! MEMDRY OBO LATCH { CONTROLS ~ ($ ~ - ... BPO '--+ SVNDRO ME BUS ~.... OBO ~ DQO·7 p... ... 008·15 081 BPI OLE OLE CLSE 'P EXPANDED LOWE. WORD IL) so.st CO-6 DP8400 J L '::' ... BPO NC~ NC~ EO M' MI 00 I EO M' ~ CO-6~CBO.fi ., MO t I i ,P EXPANDED ., t--- BPI HIGHER WORD (HI 0"400 SO.6 A. I FLAOS 1 081 iill 4 cm ~ ERRO. { .... ! ! ERni;;\~":e:~::~f uNI7 008-15 ~ OLE ,--. lIES EI iIr" 100"'" 000-7 ~.-y lIES AE OBO . t Refer to discussion in "0ther .,!,., Modes of Operation" under C!earlng S!L. MO!)~ ~QMT~lJl! n Connection sequence must be done according 10 Table VIII. FIGURE 5. 32·Blt Error Detection and Correction 2-12 cHEcK_ BIT BUS TL/F/6899-10 o Modes of Operation TABLE VI. Error Flags After Normal READ (32-Bit Configuration) (Continued) READ) when both E1 and E2 become invalid. This is required when a memory correcting system employs the DP8400-2 with byte parity checking. The E1 and E2 pins flag the byte parity error in a memory WRITE cycle. When the DP8400-2 switches to a subsequent memory READ cycle, it requires tMCR for E 1 and E2 to be switched to flag any READ error(s). AE (H) E1 (H) EO (H) Expanded Operation 32-BIT CONFIGURATION EO (L)' 0 0 0 0 No error 1 1 0 0 Single-check bit error 1 1 1 0 Single-data bit error (H) 1 1 0 1 Single-data bit error (L) 1 0 0 0 Double-bit error All Others Figure 5 shows how to connect two DP8400-2s in cascade to detect single and double-bit errors, and to correct singledata errors. The same circuit will also correct double-bit errors once a double-error has been detected, provided at least one error is a hard error. The lower chip L is in effect a slave to the higher chip H, which controls the memory check bits and error reporting. The check bit bus of L is reordered and connected to the syndrome bus of H, as shown in Figure 5. ~EO Error Type Invalid conditions (L) is valid after transfer of partial syndromes from higher to lower tDCB32 = tDCB16 + tSCB16 tDEV32 = tDCB16 + tSEV16 = tDCB16 + tSCD16 tDCD32 (Low Chip) = tDCB16 + tBR' + tCCD16 tDCD32 (High Chip) *tBA: Bus reversing time (25 ns) 32-BIT MATRIX Table VII shows a 32-bit matrix using two DP8400-2s in cascade as in Figure 5. This is one of 12 matrices that work for 32 bits. The matrix for bits 0 to 15 (lower chip) is the matrix of Table IV for 16-bit configuration, with row 6 always "0". The matrix for bits 16 to 31 (higher chip) uses the same row combinations but interchanged, for example, the 3rd row (row 2) of L matrix is the same as the 6th row (row 5) of the H matrix. This means row 5 of H is in fact check bit 2 of H. Thus, the 6th row (row 5) combines generated check bit 5 (CG5) of L and generated check bit 2 of H. Check bit 5 of L therefore connects to the syndrome bit 2 (CG2) of H, and the composite generated check bit is written to check bit 2 of memory. Thus C2 performs a parity check on bits 0, 1, 2, 4, 5, 6, 8, 12, 13, 14, of L, and bits 16, 19, 20, 24, 26, 28, 29, 30, 31, of H. CG2 and CG3 generate odd parity, so that CG5 of L generates even parity which combines with CG2 of H generating odd parity. CG3 of Land CG3 of H both generate odd parity causing C3 to memory to represent even parity. Only 6 check bits are generated in each chip, the 7th (CG6) is always zero with XP grounded. Thus CG6 of L combines with CGO of H so that CO to memory is the parity of bits 18, 19, 20, 21, 22, 23, 25, 26, 27, 29, 30, 31. Similarly C6 to memory is only CG2 of L. The 7 composite generated check bits of H can now be written to memory. A READ cycle may consist of DETECT ONLY or DETECT THEN CORRECT, depending on the system approach. In both approaches, L writes its partial check bits, CGL, to H as in WRITE mode. H develops the syndrome bits from CGL, CGH and the 7 check bits read from memory in CIL. H then outputs from its error encoder (EE) if there is an error. If corrected data is required, H already knows if it has a single-data error from its syndrome bits, but if not, it must transfer partial syndromes back to L. These partial syndromes PSH, (CGH XOR-ed with CIL), are stored in SOL of H. L must therefore change modes from WRITE to READ, while H outputs the partial syndromes from its SOB by setting OES low. The partial syndromes are fed into CI L of L and XOR-ed with CGL to produce syndrome bits at SGL. The data error decoder, DED, then corrects the error in L. The DED of H will already have corrected an error in the higher 16 bits. Only one error in 32 bits can be corrected as a single-data error, the chip with no error does not change the contents of its DI L when it is enabled in DOL. Table VI shows the 3 error flags of H, which become valid during the DETECT cycle. EO of L becomes valid during the CORRECT cycle, so that the 4 flags provide complete error reporting. When reading data and check bits from memory, CG6-CGO of L are combined with CG6-CGO of H in the same combination as WRITE. Memory check bits are fed into C6-CO of H and compared with the 7 combined parity bits in H, to II TABLE VII. Data Bit Error To Syndrome-Generate Matrix (32-Bit Configuration) o o SYNDROMES L -----°1 . 1 1 2 3 4 5 6 7 890 1 0 0 1 1 0 0 o "2 1 0 0 "3 o 1 1 1 1 0 1 1 1 1 1 0 1 o 0 1 o 1 1 1 0 0 o 1 0 0 0 0 1 1 0 o 1 0 1 1 "'" o 9 N Equations for 32-bit expansion: In a Normal WRITE mode, referring to Figures 13a, 13b, and 13c, the 7 check bits generated from the lower 16 bits (CGL) are transferred via the COL to the COB of L, provided OLE is high and M2 (RtIN) of L is low. These partial check bits from L then appear at SIL of H, so that with CSLE high, they combine with the 6 check bits generated in H with an overlap of one bit, to produce 7 check bits. With M2 (RtIN) of H low, these 7 check bits are output from COB to memory. I· ." CO H -----°1 11111112 2222 345 6 7 890 1 234 5 6 1 1 1 0 1 1 1 1 0 1 o 1 1 1 o 1 0 1 1 1 1 1 1 0 1 0 1 1 0 0 1 o 1 0 1 5 1 1 1 0 1 1 1 0 1 0 0 0 1 1 1 0 6 0 0 0 0 o 0 o 0 0 0 0 0 0 0 0 0 4 9 7 5 C 7 F F 3 9 E B D 3 o 2 2130012321 2 2 3 3 }::;,~" I 8 9 0 1 1 0 0 1 BITS 1 4 1 o 0 1 1 0 o 0 1 o 1 o 1 1 1 1 2 0 o 1 1 1 1 1 1 O' 1 1 1 0 1 1 1 o AA122 88 81A B 0 HEX 1466545346527671 o 0 1 1 0 0 o 1 1 1 "'CG2, CG3 generate odd parity 2-13 0 1 0 0 1 0 1 1 1 0 1 1 1 0 1 0 000 0 000 0 1 000 o 1 1 1 0 o 0 1 o 1 1 0 0 1 0 1 1 0 0 1 1 1 0 0 0 0 0 1 o 1 o 1 o 1 o 1 0 TL/F/6899-11 r---------------------------------------------------------------------------------, ~ Expanded Operation (Continued) ~ co TABLE VIII. Check Bit Port To Syndrome Port Interconnections For Expansion To 32 Bits Q. o Syndrome I/O to Management SO S1 S2 S3 S4 S5 S6 L S L C H S H C 0 1 2 3 4 5 6 0 1 2 3 4 1 5 6 3 4 2 0 1 5 6 3 4 2 0 5 6 CO C1 C2 C3 Check Bit 11O to Memory C4 C5 C6 TABLE IX. Syndrome Decode To Bit In Error For 32-Bit Data Word S5 So S1 S2 S3 S4 0 0 0 NE CO C1 D C2 D D 3 C3 D D 9 D 10 T D 0 0 1 C4 0 0 11 D T T D D 7 17 D T D D 15 0 1 0 C5 D D 6 D 4 T D D 2 28 0 12 D D 14 0 1 1 D 5 16 D 0 D D 13 1 D D 24 D T 8 D 1 0 0 C6 D D 22 D T T D D 25 18 D T D D T 1 0 1 D 27 21 D T D D T 23 D D T D T T D 1 1 0 D 19 20 0 T D D T 26 D D 30 D T T D 1 1 1 T D 0 29 D T T D D 31 T D T D D T Syndrome Bits S6 0 0 0 0 NE=no error Number=single data bit in error 1 0 0 0 1 0 0 a 1 1 0 0 0 0 1 0 1 0 1 0 0 1 1 0 Cn=check bit n in error D=two bits in error 1 1 1 0 0 0 0 1 1 0 0 1 0 1 0 1 1 1 0 1 0 0 1 1 1 0 1 1 0 1 1 1 1 1 1 1 T=three errors detected produce 7 syndrome bits S6-S0. H can now determine if there is any error, and if it has a single·data error, it can locate it and correct it without transferring partial syndromes to L. As an example of a DETECT cycle, CG5 of L combines with CG2 of H and is compared in H with memory check bit Table VIII depicts the exact connection for 32.bit expansion. LS equals syndrome bits of L. LC equals check bits of L. HS equals syndrome bits of H. HC equals check bits of H. Syn· drome bits SO to S6 of L are connected to system syndrome bits SO to S6. LC and HS columns are lined together show· ing the check bit port of L connected to the syndrome port of H in the exact sequence as shown in Table VIII. For ex· ample, check bit CO of L is connected to the syndrome bit S1 of H, and check bit C6 of L is connected to the syndrome bit SO of H. Check bits of H are connected to the system check bits in the order shown. Check bit C1 of H is connect· ed to the system check bit CO. 2. If L is now set to mode 4, Normal READ, and OES of H is set low, the partial syndromes of H (CG6-CGO of H XOR·ed with C6-CO of H) are transferred and shifted to L. L re· ceives these partial syndromes (S6-S0 of H) as check bit inputs C2, C1, C4, C3, C5, CO, C6 respectively, and com· pares them with CG6-CGO respectively, to produce syn· drome bits S6-S0. L now decodes these syndromes to cor· rect any single·data error in data bits 0 to 15. For example, partial syndrome bit 2 of H combines with generated check bit 5 of L to produce syndrome bit 5 in L. An error in data bit 10 will create syndrome bits in Las 0001101 from S6-S0, and these will appear on S6-S0 of L with OES low. An error in H will appear as per the H matrix. For example, an error in bit 16 will cause S6-S0 of L to be 0110010. EXPANSIOM FOR DATA WORDS REQUIRING S CHECK BITS For 16·bit and 32·bit configurations, XP is set permanently low. In 48·bit or 64·bit configurations, XP is either set perma· nently to Vee or left open, according to Table X, to provide 8 check bits and syndrome bits. TABLE X. XP: Expansion Status If OES of L is set low, this syndrome combination appears on pins S6 to SO. For errors in bits 0 to 15, the syndrome outputs will be according to Table VII. For errors in bits 16 to 31, the syndrome outputs from L will still be according to Table VII due to the shifting of partial syndrome bits from H to L. The syndrome outputs from L are unique for each of the possible 32 bits in error. If there is a check bit error, only one syndrome bit will be high. For example, if C5 is in error, then S1 of L will be high. For double·errors, an even number of syndrome bits will be high, derived from XOR.ing the two single·bit error syn· dromes. As mentioned previously, this is only one of the 12 approaches to connecting two chips for 32 bits, 6 of which are mirror images. XP Status Data Bus OV BPO and BP1 are byte parity I/O CG6=0 < 40 Bits Open No byte parity 11O, CG6 and CG7 = word parity :<: 40 Bits Vee No byte parity 11O, CG6andCG7=0 :<: 40 Bits , I 4S-BIT EXPANSION Three DP8400·2s are required for 48 bits, with the higher chip using all 8 of its check bits to the memory. No byte parity is available for 48 to 64 bits. XP of all three chips must be at Vee. The three chips are connected in cascade as in 2·14 Expanded Operation o~ CD (Continued) TABLE XI. Check Bit Port To Syndrome Port Interconnections For Expansion To 48 Bits LL S SO S1 S2 Syndrome I/O S3 to S4 Management S5 S6 S7 LL LH C S 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 LH HL C S 1 5 6 3 4 2 0 7 1 5 6 3 4 2 0 7 . "" o o r-l HL C 6 1 4 7 2 3 5 0 6 1 4 7 2 3 5 0 CO C1 C2 Check Bit I/O C3 to C4 Memory C5 C6 C7 For example: SO of LL is connected to system syndrome SO. CO of LL is connected to 81 of LH. C1 of LH is connected to 86 of HL C6 of HL is connected to system check bit CO. TABLE XII. Syndrome Decode To Bit In Error For 48-Bit Data Word 0 0 0 0 1 0 0 0 0 1 0 0 1 1 0 0 0 0 1 0 1 0 1 0 0 1 1 0 1 1 1 0 0 0 0 1 1 0 0 1 0 1 0 1 1 1 0 1 0 0 1 1 1 0 1 1 0 1 1 1 1 1 1 1 S7 S6 S5 SO S1 S2 S3 S4 0 0 0 0 NE CO C1 0 C2 0 0 3 C3 0 0 9 0 10 T 0 0 0 0 1 C4 0 0 11 0 T T 0 0 7 17 0 T 0 0 15 0 0 1 0 C5 0 0 6 0 4 T 0 0 2 28 0 12 0 0 14 0 0 1 1 0 5 16 0 0 0 0 13 1 0 0 24 0 T 8 0 0 1 0 0 C6 0 0 22 0 T T 0 0 25 18 0 T 0 0 T 0 1 0 1 0 27 21 0 32 0 T 23 0 0 T 0 T T 0 0 1 1 0 0 19 20 0 33 0 0 0 T 26 0 0 30 0 T T 0 0 1 1 1 44 40 31 T T T 43 0 T T T 0 0 0 C7 0 0 T 0 0 0 0 0 0 0 T 0 0 0 29 1 0 0 0 T 1 0 0 1 0 T 35 0 T 0 0 T T 0 0 T 0 T T 0 1 0 1 0 0 T 41 0 39 0 0 T T 0 0 T 0 T T 0 1 0 1 1 42 0 0 T 0 T 47 0 0 T T 0 T 0 0 T 1 1 0 0 0 T 38 0 37 0 0 T T 0 0 T 0 T T 0 1 1 0 1 36 0 0 T 45 0 T T 34 0 0 T T T T T 0 T 0 0 0 0 0 0 T 1 0 0 T 1 0 0 T 1 0 T 1 1 1 1 0 T 46 0 T 0 0 T T 0 0 T 0 T T 0 Syndrome Bits NE = no error Number = single data bit in error T Cn = check bit n in error = two bits in error o T = three errors detected Figure 6. but with the HH chip removed. The error flags are as Table XV. but with AE (HH) and E1 (HH) becoming AE (HL) and E1 (HL), and EO (HH) removed. and syndrome bus for each of the chip pairs are shown in Table XIII. The error flags of HH are valid during the DETECT cycle as in Table XV, and the other error flags are valid during the CORRECT cycle. 48-BIT MATRIX The matrix for 48 bits is that for 64 bits shown (in Table XVI) but only using bits 0 to 47. This is one of many matrices for 48-bit expansion using the basic 16-bit matrix. The matrix shown uses 2 zeroes for CG6 and CG7, for all three chips, with XP set to Vee. Other matrices may use CG6 and CG7 as word parity with XP open. A faster method of 64-bit expansion shown in Figure 7 requires a few extra ICs, but can WRITE in 50 ns, DETECT in 42 ns or DETECT THEN CORRECT in 90 ns. In the WRITE mode, all four sets of check bits are combined externally in the 8 74S280 parity generators. These generate 8 composite check bits from the system data, which are then enabled to memory. In the DETECT mode, again 8 composite check bits are generated, from the memory data this time, and compared with the memory check bits to produce 8 external syndrome bits. These syndrome bits may be OR-ed to determine if there is any error. By making the 74S280 outputs SYNDROMES, then any bit low causes the 74S30 NAND gate to go high, giving any error indication. To correct the error, these syndrome bits are fed re-ordered into SIL of each OP8400-2 now set to mode 7B. This enables the syndromes directly to SG and then OED of each chip. One chip 64-BIT EXPANSION There are two basic methods of expansion to 64 bits, both requiring 8 check bits to memory, and four OP8400-2s. One is the cascade method of Figure 6, requiring no extra ICs. With this method partial check bits have to be transferred through three chips in the WRITE or DETECT mode, and partial syndrome bits transferred back through three chips in CORRECT mode. This method is similar to Figure 5, 32-bit approach. The connections between the check bit bus 2-15 • I Expanded Operation (Continued) will output corrected data, while the other three output nonmodified data (but still correct). 64-BIT MATRIX With the 64-bit matrix shown in Table XVI, it is necessary to set at least one chip with CG6, CG7 non-zero. The highest chip, connected to data bits 48 to 63, has XP set open, so that its CG6 and CG7 are word parity. The syndrome word of the highest chip will now have either 5 or 7 syndrome bits high, but inside the chip CG6 and CG7 remove two of these in a READ so that the chip sees the normal 3 or 5 syndrome bits. Equations for fast 64-bit expansion: tOCB64 tOEV64 tOCB64 = = = tOCB16 tOCB16 tOCB16 + tpd (74S280) + ipd (74S240) + tpd (74S280) + tpd (74S30) + tpd (74S280) + tpd (74ALS533) + tSC016 TABLE XIII. Ch.eck Bit Port To Syndrome Port Interconnections For Expansion To 64 Bits SO S1 S2 Syndrome I/O S3 to S4 Management S5 S6 S7 Ll S LL LH C 5 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 LH Hl C 5 1 5 6 3 4 2 0 7 1 5 6 3 4 2 0 7 Hl HH S C 6 1 4 7 2 3 5 0 6 1 4 7 2 3 5 0 HH C 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 CO C1 C2 Check Bit I/O C3 to C4 Memory C5 C6 C7 For example: 80 of LL is connected to system syndrome 80. CO of LL is connected to 81 of LH. Cl of LH is connected to 86 of HL. C6 of HL is connected to 87 of HH. C7 of HH is connected to system check bit CO. TABLE XIV. Syndrome Decode To Bit In Error For 64-Bit Data Word S7 S6 S5 50 51 52 S3 54 0 0 0 0 NE CO C1 D C2 D D 3 C3 D D 9 D 10 T D 0 0 0 1 C4 D D 11 D T T D D 7 17 D T D D 15 0 0 1 0 C5 D D 6 D 4 T D D 2 28 D 12 D D 14 0 0 1 1 D 5 16 D 0 D D 13 1 D D 24 D T 8 D 0 1 0 0 C6 D D 22 D T T D D 25 18 D T D D T 0 1 0 1 D 27 21 D 32 D D T 23 D D T D T T D 0 1 1 0 D 19 20 D 33 D D T 26 D D 30 D T T D 0 1 1 1 44 D D 29 D T 40 D D 31 T D T D D T 1 0 0 0 C7 D D T D T 43 D D T T D T D D 51 1 0 0 1 D T 35 D T D D 57 T D D 58 D T T D 1 0 1 0 D T 41 D 39 D D 59 T D D T D T T D 1 0 1 1 42 D D 55 D T 47 D D T T D T D D 63 Syndrome Bits 0 0 0 0 1 0 0 0 0 1 0 0 1 1 0 0 0 0 1 0 1 0 1 0 0 1 1 0 1 1 1 0 0 0 0 1 1 0 0 1 0 1 0 1 1 1 0 1 0 0 1 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 0 0 D T 38 D 37 D D 54 T D D 52 D T T D 1 1 0 1 36 D D 50 D T 45 D D 60 T D T D D 62 1 1 1 0 34 D D 53 D T T D D 48 T D T D D 61 1 1 1 1 D 49 46 D T D D T T D D T D 56 T D NE = no error Number = single data bit in error = check bit n in error en D = two Ms In T = three errors detected error TABLE XV. Error Flags After Normal READ (Any 64·Blt Configuration) AE(HH) E1 (HH) EO (HH) EO (Hl) EO (lH) EO (ll) 0 0 0 0 0 0 No error Error Type 1 1 0 0 0 0 Single-check bit errOr 1 1 1 0 0 0 Single-data bit error in HH 1 1 0 1 0 0 Single-data bit error in HL 1 1 0 0 1 0 Single-data bit error in LH 1 1 0 0 0 1 Single-data bit error in LL 1 0 0 0 0 0 Double-error 2-16 O:J~~~ffff&W?JY&?~~$W4Wffff$~$~IIQO-63 000-15 0016-31 ~ 00.48-63 D032-47 MEIIORY ----CIIII-1 ~ "" MODE CONTROLS TUF/6899-12 FIGURE 6. Cascade Expansion Using No Extra ICs (64-Bit Configuration) TABLE XVI. Data Bit Error To Syndrome-Generate Matrix (64-Bit Configuration) I• SYNDROMES LL .. I• LH .. I. HL .. I. HH ·1 1 1 1 1 1 1 0123456789012345 1111222222222233 6789012345678901 3333333344444444 2345678901234567 4455555555556666 8901234567890123 00011111101110111 100010010110101 210011000101011 30110000111101011 41100010110010101 5 1110111010001110 60000000000000000 7 0000000000000000 0001001011010111 1110111010001110 0000000000000000 0110000111101011 1100010110010101 1001100010101111 0011111101110111 0000000000000000 0000000000000000 0001001011010111 1100010110010101 0000000000000000 1001100010101111 0110000111101011 1110111010001110 0011111101110111 111111111111 7 001111101110 0 00010010 010 1 1001100010101 2 01100001111010113 1000101 0010 014 11101110100011105 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 6 48975139EBD3C7FF 3320232130012321 2AA12238B981 A3B9 3146654534652767 4402042462060626 56E9DCCA7AB87DFB 9 1 3 F B 3 7 3 D 7 B 7 9 F F F 0 HEX EFD8CECBF99ADEDB } DOO-63 GENERATED CHECK BITS J TUF/6899-13 ~-OO"8da iii DP8400-2 ~n ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~)f'~;:;---l BUS _= lATCH[=~~=$=:t1J=~I=$===:;::::::;~=$=t*=Ij*=$==~~~==*~[t:::l*=*===:;:::;=r--r--mf--:ru-t---..., CONTRDl MEMORY ~ ~ <~ (X) ~ .... CSW, ee2, tfI.Z .... L...l:=1ER.O. FLAGS . , I" CORRECT ~ ... ~ 1----- '''''273 I: ~,------,C8'_T 0, &fI, eR CW, CfI,CR FOR SEQUENCE: WRITE, DETECT, CORRECT CORiifCf 748244 ~VRIT_El_IlfTE=C,-T__- omCT I I e2c2 SYSTEM CONTROL TlIF/6899-14 FIGURE 7_ Parallel Expansion (Fast 64-Bit Configuration) C "'C Other Modes Of Operation (XI ",.. the error to repeat itself. For example, if cell N of a particular location is jammed permanently high, and a low is written to it, a high will be read. However, when the data is complemented a low is again written, so that a high is read back for the second time. After a second READ (this second READ is a COMPLEMENT READ) of the location, data and check bits from the memory are recomplemented, so that bit N now contains a low. In other words, the error in bit N has corrected itself, while the other bits are true again. If there are two hard errors in a location, both are automatically corrected and the DP8400-2 detects no error on COMPLEMENT READ, as in Figure 8a. Figure 8b also shows that if one error is soft, the hard error will disappear on the second READ and the DP8400-2 corrects the soft error as a singleerror. Therefore, in both cases, the DOL contains corrected data, ready to be enabled by OBO and OBI. A WRITE to memory at this stage removes the complemented data written at the start of the sequence. DOUBLE ERROR CORRECTION, USING THE DOUBLECOMPLEMENT APPROACH The DP8400-2 can be made to correct two errors, using no extra ICs or check bits, if at least one of the two errors detected is a hard error. This does require an extra memory WRITE and READ. Nevertheless, if a permanent failure exists, and an additional error occurs (creating two errors), both errors can be corrected, thereby saving a system crash. Once a double error has been detected, the system puts the DP8400-2 in COMPLEMENT mode by setting MO high. First a WRITE cycle is required and M2 is set low, putting the chip in mode 1, Table III, (COMPLEMENT WRITE), so that the contents of Dil are complemented into DOL, and the contents of Cil complemented into COL. OBO and OBI are set low so that complemented data and check bits can be written back to the same location of memory. Writing back complemented data to a location with a hard error forces DATA I/O I GENERATED CBs I HARD ERRORS ORIGINAL DATA/CBs WRITTEN TO MEMORY 2 DATA ERRORS INSERTED DATA/CBs READ FROM MEMORY I MEMORY CBs I ---+-~--I--~ I I [ I I NO CHECK BIT I I ERRORS 1 0 D 1.--1-1[ill] I ~ 101 ~ ~ ___________ COMPLEMENT DATA/CBs IN OP8400 INPUT LATCHES. WRITE BACK TO SAME LOCATION IN MEMORY READ BACK FROM SAME LOCATION IN MEMORY ~ _ _ _2~R~S~ECTE~ _ I II I I DA:AA~RER~RS I H I I I CGW I I I I NO ;::g:sBIT I [QJJJJ [ITDJ II SAME AS ORIGINAL COMPLEMENT DATA/CBs I CBs GENERATED [IITII--r-~ IN DP84DO INPUT LATCHE/S -~ ~W~~~ I I ~ I I I I I I +- __ I I I I I II ~ I}I J... DATA. SO SAME I / I MODE I I I ~ 1/ ~I 1 5 I I I I SAME CHECK BITS. -NO ERROR OETECTEOINDICATING BOTH HARD ERRORS HAVE BEEN REMOVED NUMBER OF COMPLEMENTS 2 BY DPB400 2 BY MEMORY EVEN 2 BY OP840D DBY MEMORY EVEN EVEN NUMBER OF COMPLEMENTS CREATES SAME DATA AS ORIGINAL TLiF/6899-15 FIGURE 8a. Double Error Correct Complement Hard Error Method - 2 Hard Errors In Data Bits 2-19 o o I N I Other Modes of Operation (Conti'"odl DATA 110 , GENERATED CII , 11 11 MEMDRY CII 'MDDE NARD ERROR 11---1 ORIGINAL DATA/CII WRlnEN TD MEMORY [ITTI]--J--D!LI-I-O!D I II I1 I1 1Iill--L-~CGR I I'COW I HARD II.DFT ERROR ERROR DATA/CBI READ FRDM MEMORY 1, ND CHECK BIT ERRORS '4 -------------~--~~~~~--~-!!II!] I I ~ COMPLEMENT DATA/CBa 1 ::I:::C~~~TS~~HES, SAME HARD ERROR COMPLEMENT DATA/CBa IN DP8400 INPUT LATCHES, AND CDMPARE CBI I I I I NO CHECK BIT ERRORS I I I I OM[] I LOCATION IN MEMORY READ BACK FROM SAME LOCATION I 111 0 I I [ll]J]-+-O!DI~ I D~~ITS' SINGLE ERROR DETECTED CORRECT SINGLE ERROR USING NORMAL DP8400 PROCEDURE OF XDR-ING DIWITH DE _____l!II!I DATA ERROR WORD [ITTI] TLlF/6899-16 FIGURE ab. Double Error Correct Complement Hard Error Method -1 Hard Error, The examples shown in Figures 8a and 8b are for 4 data bits. This approach will work for any number of data bits, but for simplicity these examples show how complementing twice corrects two errors in the data bits. The double COMPLEMENT approach also works for any two errors providing at least one is hard. In other words, one data-bit error and one check bit error, or two check bit errors are also corrected if one or both are hard. At the end of the COMPLEMENT READ cycle, the error flags indicate whether the data was correctable or not, as shown in Table XVII. If both the errors were soft, then the data was not correctable and the error flags indicate this. Soft Error In Data Bits configuration. In the 16·bit configuration, modes 1 and 5 of Table III are used. In the 32·bit expanded configuration, modes 1, 5 and 5 are used for the highest chip, and modes 3,3 and 4 for the lower chip for WRITE, DETECT, and COR· RECT. With the lower chip it is necessary to wrap around DOL (after latching its contents in mode 3), back to OIL and perform a Normal READ in mode 4 in the lower Chip. TABLE XVII. ERROR FLAGS AFTER COMPLEMENT READ (MODE 5) This approach is ideal where double errors are rare but may occur. To avoid a system crash, a double-error detect now causes the system to enter a subroutine to set the DP8400-2 in COMPLEMENT mode. This method is also useful in bulk-memory applications, where RAMs are used with known cell failures, and is applicable in 16, 32, 48 or 64-bit 2-20 Error Type AE E1 EO 0 0 0 1 1 0 One hard error, one soft check bit error 1 1 1 One hard error, one soft data bit error 1 0 0 Two soft errors, not corrected Two hard errors C Other Modes of Operation ." 0) (Continued) DOUBLE-ERROR CORRECT WITH ERROR LOGGING MONITORING GENERATED SYNDROMES AND MEMORY CHECK BITS Figures 4 and 5 show the E2C2 syndrome port connected to an error management unit (EMU). This scheme stores syndromes and the address of locations that fail, thereby logging the errors. Subsequent errors in a memory location that has already stored syndromes in the EMU, can then be removed by injecting the stored syndromes of the first error. To save the addresses and syndromes when power to the EMU is removed, it is necessary to be able to transfer information via the E2C2 syndrome port to the processor data bus. This is also useful for logging the errors in the processor. Transfer in the opposite direction is also necessary. Mode 6A enables SGO-SG6 onto DOO-D06, and CllOCIl6 onto D08-D014, provided OLE, OBO and OB1 are low. Also the two error flags, E1 and EO (latched from the previous READ mode), appear on DO? and D015. This may be used for checking the internal syndromes, for reading the memory check bits, or for diagnostiCS by checking the latched error flags. CLEARING SIL In the 16-bit only configuration, or the lower chip of expanded configurations, and in various modes of operation in the higher expanded chips, it is required that SI l be maintained at zero. At power-up initialization, both Sil and Dil are reset to all low. If OES is kept low, Sil will remain reset because CSlE is inhibited to SI L. Another method is to keep OES always high and the syndrome bus externally set low, or set low whenever CSlE can be used to clear SIL. Mode? A also forces the Sil to be cleared whenever CSlE occurs, and also these zero syndromes go to the internal syndrome bus SG. This puts the DP8400-2 in a PASSTHROUGH mode where the Dil contents pass to DOL and Cil contents to COL, if OLE is low. DATA BUS TO SYNDROME BUS TRANSFER This is necessary when transferring syndrome information to the error management unit, which is connected to the external syndrome bus. First, data to make CG = 0 (all data bits high) must be latched in DI L. Then in mode 2, data is fed to Cll, XOR-ed with 0, and output via SOL with OES low to the syndrome bus. Data is therefore fed directly from the system to the syndrome bus, and this cycle may be repeated as long as DlE is kept low, forCing CG to remain zero. SYNDROME BUS TO DATA BUS TRANSFER This is important when information in the error logger or error management unit has to be read. The DP8400-2 is set to mode 6B with OES high, and with OBO, OB1 and OLE low. If CSlE is high, the syndrome bus and check bit bus data appear on the lower and upper bytes of the data bus to be read by the system. Also E1 and EO values that were valid when mode 6 was entered, appear on DO? and D015. POWER-UP INITIALIZATION OF MEMORY Both Sil and Dil are reset low at power-up initialization. This facilitates writing all zeroes to the memory data bits to set up the memory. The check bits corresponding to all-zero data will appear on the check bit bus if the DP8400-2 is set to mode 0 and OLE is set low. All-zero data appears on the data bus when OBO and OB1 are also set low. The system can now write zero-data and corresponding check bits to every memory location. FULL DIAGNOSTIC CHECK OF MEMORY Using mode 2, it is possible to transfer the upper byte of the data bus directly to the Cll, with CSlE high, without affecting DIL. These simulated check bits then appear on the check bit bus with OLE low, which also causes the previously latched contents of Dil to transfer to DOL. By enabling OBO and OB1 data can be written to memory with the simulated check bits. A Normal READ cycle can then aid the system in determining that the memory bits are functioning correctly, since the processor knows the check bits and data it sent to the E2C2. Another solution is to put the E2C2 in mode 6 and read the memory check bits directly back to the processor. BYTE WRITING Figure 14a shows the block diagram of a 16-bit memory correction system consisting of a DP8400-2 error correction chip and a DP8409A DRAM controller chip. There are 12 control signals aSSOCiated with the interface. Six of the signals are standard DP8400-2 input signals, three are standard DP8409A input signals, and three are buffer control signals. The buffer control signals, PBUFO and PBUF1, control when data words or bytes from the DP8400-21 memory data bus are gated to the processor bus and when data words or bytes from the processor are gated to the DP84002/memory data bus. SELF-TEST OF THE E2C2 ON-CARD Again using mode 2, data written from the processor data bus upper byte to Cil may be stored in Cll, by taking CSlE low. Next, a mode 0 WRITE can be performed and the user generated data can be latched in the DP8400-2 input latches (DlE held low). Now the user may perform a normal mode 4 READ. This will in effect be a Diagnostic READ of the user generated data and check bits without using the external memory. Thus by reading corrected data in mode 4, and by reading the generated syndromes, and error flags EO and E1, the DP8400-2 can be tested completely on-card without involving memory. When the processor is reading or writing bytes to memory, words will always be read or written by the DP8400-2 and DP8409A error correction and DRAM controller section. The High Byte Enable and Address Data Bit Zero Signals from the processor should control the byte transfers via the ocal bus transceiver signals PBUFO and PBUF1. The buffer control signal, DOUTB, controls when data from memory is gated onto the DP8400-21 memory data bus. Figure 14b shows the timing relationships of the 12 control signals, along with the DP8400-2/memory data bus and some of the DRAM control signals (RAS and CAS). RGCK is the RAS generator clock of the DP8409A which is used in Mode 1 (Auto Refresh mode), along with being the system clock. 2-21 "'oo." N i co a.. o Other Modes of Operation (Continued) Having two separate byte enable pins, OBO and OB1, it is easy to implement byte writing using the DP8400-2. First it is necessary to read from the location to which the byte is to be written. To do this the DP8400-2 is put in normal Read mode (Mode 4), which will detect and correct a single bit error. WIN is kept high and RASIN is pulled low, causing the DP8409A, now in Mode 5 (Auto Access mode), to start a read memory cycle. The data word and check bits from memory are then enabled onto the DP8400-2/memory data bus by pulling DOUTB low. The data and check bits are valid on the bus after the RASIN to CAS time (tRAel plus the column access time (tCAel of the particular memories used. DLE, CSLE can then be pulled low in order to latch the memory data into the input latches of the DP8400-2. OLE can be pulled low to enable the corrected memory word, or the original memory word if no error was present, into the data output latches. Following this, DOUTB can be pulled high to disable the memory data from the DP8400-2/memory data bus. The corrected memory word will be available at the data output latches "tDcD16" after the memory word was available at the data input latches. Once the corrected data is available at the output latches OLE can be pulled high to latch the corrected data. Also DLE and CSLE can be pulled high in order to enable the input data latches again. Also a READ-MODIFY-WRITE cycle wa$~~. taking approximately 40% longer than a normal M.mory WRITE cycle. A READ and then a WRITE me11lQl'Y ~'Could have been used in the above example buUt '!I/O!,IkI have taken longer. ' ,',,:. ' ,to, Buffers are used in this system (74A~ keep the Data Out and Data In of the memory It's. frpr)i' conflicting with each other during Read-Modify-Wr~ ~les. A byte READ from memory is no differl\lllt from a normal READ. This approach may be used for ,.1~~pit processor using byte writing, or an 8-bit processQrllSirnJ -. i6-llit memory to reduce the memory percentage of ~Qt(, bits, or with memory word sizes greater than two byteS:' An APP NOTE (App Note 387) has b~ w!'ittendetailing an Error Correcting Memory System U$iogthe'QP8409A or DP8419 (Dynamic RAM Controller) and the 011'8400-2 interfaced to a National Semiconductor $!ilries 32OQO- CPU. See this App Note for further system details ~,~onsiderations. BEYOND SINGLE·ERROR CORRECT With the advent of larger semiconductor memories, the frequency of the soft errors will increase. Also some memory system designers may prefer to buy less expansive memories with known cell, row or column failures,-t/lus, more hard errors. All this means that double-error C91Teo\, triple-error detect capability, and beyond will become increasingly important. The DP8400-2 can correct two errors. provided one or both are hard errors, with no extra components, using the double complement approach. There are .two other approaches to enhance reliability and integrity. One is to use the error management unit to log errQ.rll using the syndrome bus, and then to output these syndromes; when required, back to the DP8400-2. Now the DP8400-2 can be put into a write cycle (Mode 0 = M2 = Low). At this time the byte to be written to memory and the other byte from memory can be enabled onto the DP8400-2/memory data bus (OBO, PBUF1 or OB1, PBUFO go low). DLE, CSLE can now transition low to latch the new memory word into the data input latch. OLE is pulled low to enable the output latches. When the new checkbits are valid, tOCB16 after the data word is valid on the DP8400-21 memory data bus, OLE and DLE can be pulled high to latch the new memory word into the output latches, and then WIN can be pulled low to write the data into memory. RASIN should be held low long enough to cause the new data and check bits to be stored into memory (WIN data hold time). DOUBLE SYNDROME DECODING The other approach takes advantage of 'the Rotational Syndrome Word Generator matrix. This matrix is an improvement of the Modified Hamming-code, so that\f,on a second DP8400-2, the data bus is shifted or rotated ~y one bit, and 2 errors occur, the syndromes for this ,Sgeopd chip will be different from the first for any 2 bits io ern)r. Both chips together output a unique set of syndromesJor any 2 bits in error. This can be decoded to correct any 2-bit error. This is not possible with other Modified Hamming:code matrices. ',";, .: -, ..; ..'. . t 2-22 I C Absolute Maximum Ratings Storage Temperature Range - 65°C to + 150°C Supply Voltage, Vee 7V Input Voltage CI) ,j:o, Min 4.75 0 Vee, Supply Voltage T A, Ambient Temperature 5.5V Output Sink Current "Q Operating Conditions (Note 1) Max 5.25 70 Units V °C Max Units 0.8 V 50mA Maximum Power Dissipation at 25°C Molded Package 3269 mW Lead Temperature (Soldering, 10 seconds) 300°C *Derate molded package 26.2 mW rc above 25°C. Electrical Characteristics Symbol (Note 2) Vee Parameter = 5V ± 5%, T A = O°C to 70°C unless otherwise noted Conditions VIL Input Low Threshold VIH Input High Threshold Ve Input Clamp Voltage Vee IIH Input High Current VIN IIH (XP) Input High Current Vee = Max, XP = 5.25V IlL (XP) Input Low Current Vee = Max, XP = OV IlL (BPO/C7) Input Low Current Vee = Max, VIN = 0.5V IlL (BP1/S7) Input Low Current Vee = Max, VIN = 0.5V ilL (CSLE) Input Low Current Vee IlL (DLE) Input Low Current IlL Min Typ V 2.0 = Min, Ie = -18mA -0.8 -1.5 1 160 fLA 2.5 4.5 mA -2.5 -4.5 mA -100.0 -500 fLA -100.0 -500 fLA = Max, VIN = 0.5V -150.0 -750 fLA Vee = Max, VIN = 0.5V -200.0 -1000 fLA Input Low Current Vee = Max, VIN = O.5V -50.0 -250 fLA II Input High Current (Max) VIN = 5.5V (Except XP Pin) 1.0 mA VOL Output Low Voltage 10L 10L = 8 mA (Except BPO, BP1) = 4 mA (BPO, BP1 Only) 0.5 0.5 V V VOH Output High Voltage 10H 10H = -100 /-,A = -1 mA los Output Short Current (Note 3) Vee = Max -150 -250 mA = Max 220 300 mA = 2.7V 0.3 0.3 2.7 2.4 3.2 3.0 V V V lee Supply Current Vee CIN (I/O) Input Capacitance All Bidirectional Pins Note 4 8.0 pF CIN Input Capacitance All Unidirectional Input Pins Note 4 5.0 pF Note 1: "Absolute Maximum Ratings" are the values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation. Note 2: All typical values are for TA ~ 25'C and Vcc~ 5.0V Note 3: Only one output at a time should be shorted. Note 4: Input capacitance is guaranteed by periodic testing. F te5t= 10kHz at 300 mV, T A= 25°G. Note 5: All switching parameters measured from 1.5V of input to 1.5V of output. Input pulse amplitude OV to 3V, t r =tf=2.5 ns. 2-23 o oI N DP8400-2 Switching Characteristics (Note 5) Vcc = 5.0V ±5%, TA = O·C to 70·C, Cl = 50 pF Symbol Parameter Typ Max Units Figure9b 29 40 ns Data Input to Any Error Valid Figures 10b, 11b (Note 1) 21 31 ns tOC016 Data Input Valid to Corrected Data Valid Figure 10b, OBO, OB1 Low 44 61 ns tOSI Data Input Set-Up Time Before OLE, CSLE H to L Figures fOb, 13d 10 5 ns tOHI Data Input Hold Time After OLE, CSLE H to L Figures 10b, 13d 10 5 ns toso Data Input Set-Up Time Before OLE L to H Figure 10b 10 5 ns tOHO Data Input Hold Time After OLE L to H Figure 10b 10 5 ns tOEO Data in Valid to EO Valid Figures9b, 10b, 13d 36 55 ns tOE1 Data in Valid to E1 Valid Figures9b, 10b, 13d 43 55 ns tlEV OLE, CSLE High to Any Error Flag Valid (Input Data Previously Valid) Figure 10b 28 45 ns tlEX OLE, CSLE High to Any Error Flag Invalid Figures 9b, 10b 38 60 ns tilE OLE, CSLE High Width to Guarantee Valid Data Latched Figures 10b, 13d 20 ns tOLE OLE Low Width to Guarantee Valid Data Latched Figure 13d 20 ns tZH High Impedance to Logic 1 from OBO, OB1, M2 Hto L Figures9b, 10b, 13d 22 36 ns tHZ Logic 1 to High Impedance from OBO, OB1, DES, M2 L to H Figures 9b, 10b, 13d, 38 55 ns tZl ofrom OBO, OB1, m:s Figures 9b, 10b, 13d 19 35 ns tOCB16 Data Input Valid to Check Bit Valid tOEV16 m:s Conditions Min High Impedance to Logic M2 Hto L tlZ Logic 0 to High Impedance from OBO, OB1, DES, M2 H to L Figures 9b, 10b, 13d 15 25 ns tpPE Byte Parity Input Valid to Parity Error Flags Valid Figure9b 16 27 ns tOPE Data In Valid to Parity Error Flags Valid Figures 9b, 13d 27 55 ns Figure9b .... 61 ns tocp Data in Valid to Corrected Byte Parity Output Valid AA Note 1: This parameter value holds given that an error occurred. In the case of no error. tOEV'6 will be max of 80 ns. 2-24 DP8400-2 Switching Characteristics (Continued) (Note 5) Vcc = 5.0V ± 5%, T A = O'C to 70'C, CL = 50 pF Typ Max Units Figure10b 22 35 ns Mode Valid to Complement Data Valid Figure 11b 34 50 ns tccv Mode Valid to Complement Check Bit Valid Figure 11b 30 45 ns tSCB Syndrome Input Valid to Check Bit Valid Figure 13d 20 35 ns tSEV Syndrome Input Valid (CGL) to Any Error Valid Figure 13d 17 27 ns tsco Syndrome Inputs Valid to Corrected Data Valid Figure 13d 35 50 ns tOSB Data Input Valid to Syndrome Bus Valid Figure 13d, OES Low 28 46 ns tCSB Check Bit Inputs Valid to Syndrome Bus Valid Figure 13d, C5ES Low 19 32 ns tCEV Check Bit Inputs Valid (PSH) to Any Error Valid Figure13d 17 30 ns tcco Check Bit Input Valid (PSH) to Corrected Data Valid Figure13d 30 45 ns tOCB32 Data Input Valid to Check Bit Valid Figure 13d 49 75 ns tOEV32 Data Input Valid to Any Error Valid Figure 13d 46 67 ns tOC032 Data Input Valid to Corrected Data Out Figure 13d, aBO, OB1 Low 84 110 ns Symbol Conditions Parameter tNMR New Mode Recognize Time tcov Min Note 1: "Absolute Maximum Ratings" are the values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation. Note 2: All typical values are for TA~25'C and Vcc~5.0V. Note 3: Only one output at a time should be shorted. Note 4: Input capacitance is guaranteed by periodic testing. F te5t=10 kHz at 300 mY, TA=25°C. Note 5: All switching parameters measured from 1.5V of input to 1.5V of output. Input pulse amplitude OV to 3V, tr = tf = 2.5 ns. 2-25 Typical Applications ,.., 00- ~ I CWO-6 , ~ ___ El ffi ~ ffi __ ~~~ ______________ ! WODE 0 TL/F/6899-17 FIGURE 9a. DP8400·2 16·Blt Configuration, Normal WRITE with Byte Parity Error Detect If Required INPUTS MODE ;NAlLE SYSTEM OATA OLE CSLE INPUTS/OUTPUTS BPO/BP1 DATA BUS CHECk8~~ --t--t~...::~t~~~~~~t)---\~...:.~~~ --+---'(i---+-~~~---+-l---t~:::::7\~-~~~~-...J -@/,\ ___ Olill!ill EO, E1 TLiF/6899-18 FIGURE 9b. DP8400·2 16·Bit Configuration, Normal WRITE and Normal READ Timing Diagram 2-26 Typical Applications (Continued) .......,, SYNDROYEIUS ~[--- [.!._---TL/F/6899-19 FIGURE 10a. DP8400-2 16-81t Configuration, Normal READ - Detect Error (And Correct If Required-) • , TL/F/6899-20 Note 1: If rewriting correct data and CBs to same location and single data error was detected. Note 2: If rewriting correct data and CBs to same location and single check bH was detected. FIGURE 10b. DP8400-2 16-81t Configuration, DETECT THEN CORRECT Timing Diagram 2-27 i Typical Applications (Continued) ==:;;;;;;;;;;;;;;;;;;;;;J:=======C====*D. t~ t ""~====================:'~"'~£*' 1)Ooo 7 ,nEO ~ ______________________________ ~ DO-7 ___ AE=L El ;;r, [0 M1!;2. _ _ _ _ _ _ _ _ _ _ _ _ _ _ • pio - - "~DE I TL/F/8899-21 FIGURE 11a. DP8400-2 16-Blt Configuration, COMPLEMENT WRITE READ l1li, CMPllGM IAMELllCATIDN _UllIEAD _ - - , INULEMEIIORY . . .11 I ENABt.ECOMPl. IATAMICI EIIIUI DU _DATA GlLE .lMOIIYca DATA lUi CHECK liT lUI I ~ EIIIUI ---< ---< MEMDRY DATA : MI_C, ==""",,",,=i-,.,.;iHYII"""1 ElIOR ~~_ _ _ _ _ __ TL/F/8899-22 Note 3: II ......vrlting corrected data and CBs back to same location and 1 soft data bR error was detected, Note 4: If rewriting corrected data and CBs back to same location and 2 hard errors or 1 soft check bH was detected. FIGURE 11b. DP8400-2 16-Blt Configuration, Detect 2 Errors, COMPLEMENT WRITE, COMPLEMENT READ, Output Corrected Data Timing Diagram 2·28 Typical Applications (Continued) 1+ 1100-1 ,"========::;:~=========::;;;;==jiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiif============loa,.,S , 'co At II [2, __ "!:,2. _ _ _ _ _ _ _ _ _ _ _ _ _ _ ~ TLlF/6899-23 FIGURE 11c. DP8400·2 16-81t Configuration, COMPLEMENT READ and Output Corrected It One or Two Hard Errors 2·29 i Typical Applications (Continued) ~ Q o o OI£ I , ~E_ _ _ ~ EI Pfi __ :DQ8-U 0 o ~t~ ______________ ! iiEo TLlF/6899-24 FIGURE 12a. DP8400-2 16-Bit Configuration, Diagnostic WRITE, READ. Data Bus to Check Bit Bus or Syndrome Bus (Providing 01 = HIGH In Previous Cycle to Set CG = All Zero For Transfer to S) 1)80-15 00-7 ~;"';"::::====~~m::::::::::::::::::::::::::::'~";';O::::~~~~~~1F::::::::::::::::::::::==1 08-15 00-7 SO•• 6.... 66 o ~~~~~'~OE~S--~==~::::::::::::::~~~t:::::::t:::::~::::::~;:=l::::::::::::~::~ $~::~J:owt BU;: CIIECKBITBliS ~E _ _ _ E1 _ _ _ _ _ E! ___U~2_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ! 11100£6 TLlF/6899-25 FIGURE 12b. DP8400-2 16-Blt Configuration, Monitor on Data Bus 2-30 Memory Check Bits Typical Applications (Continued) TL/F 16899-26 2-31 . ~ N ,--------------------------------------------------------------------------, Typical Applications (Continued) co a.. C g ~ ~ co a. 0 ~ c 0 . g w ti .!!II> 0 0 < W II: C- o e :::J 01 0;: C 0 0 i5 eli C') '" Q 0 .... co a. 0 .a C') W II: :::) C!' ii: d: ~ ....0co a. 0 TL/F/6899-27 2-32 Typical Applications (Continued) g c:' Q ~ CD D- C f! 8 1) ~ u0 cc( w a:: C 0 ! = ~ c 8 iii N Of) i CD D- C ~ W a:: :::l CI ii: ~ ~ !c• TLiF/6899-2B 2·33 i Typical Applications INPUTS D. C (Continued) >D(\.-------_::=x- WRITE DATA AND lEND CI. Wj( MOOEIH) READ-DETECT ERRORS CORRECT EMOII 4 lOR OIFNOTES 5, I) >a : MODE IL) ENABLf SYSTEM lilfA ENABLE MEMORY DATAANDCB. MEMWRITE ENABLE CD~REClm D~TAI 010,1 (H,L) dEs (H) DATA IUS (H, L) CHECK liT IUS (H) ---t/,IWhVIX ~-r1X SYNDROME CHECK liT IUS IUS (H) (L) _ _ >-I----<~~~~~~c.-4,..--~~~SH ~_ _ _- I I .ED'El(L)~~fYlll{llllllilll'" Note 5: If rewriting corrected data and CBs back to same location and single data error was detected. Nota 6: If rewriting corrected data and CBs back to same location and Single check bit error was detected. FIGURE 13d. DP8400-2 32-Blt Configuration, WRITE, DETECT and CORRECT Timing Diagram 2-34 TL/F/B899-29 :J 'a NS32016, DP8400-2, DP8409A or DP8419 Error Correcting Memory System OAMPING RESISTORS l J DP84300 PROGRAMMABLE DIVIDER I cnL ADDRESS/OATA BUS ADO-A015 16 J I I 15.6"' CLOCK • SYSTEM CLOCK J I DECODER ! 74ALS373 LATCHES .• I ~- 24 BIT :3~RESS AOO-7 74F245 OIR ~ I!DIIl fPilllfj FCLK 'y CAS ADS wr DP8409A DR OP8419 - 0- -- All C)" :::l en '§ ~ CS ::J C 00-7 1. 8 S 010-7 018-15 OD-7 D8~ y 1. , 8 000-7 OOUTB 74ALS244 8 008-15 CSLE OLE P.I.C. 3 PAL" &SHIFT REGISTER (74LS164) INTERFACE CONTROLLER 0P8400 EO ~ r f!!!.o SYSTEM RE!fi. DOUBLE R 0118-21 CHECK BITS 1, AE E1 ADS 6 CO-5 MOOECC fSlj ill C'6~.~ 74ALS244 6 0018-21 CHECK BITS -:¥.2k DOUTB CWAIT IF system contains NS32 )82 MMU PAV should be used in place of ADS n" OLE RFI/O HBE "2. MEMORY UP TO 4 BANKS OF 22 256k DRAMS 2 M BYTES PLUS CHECK BITS 0 - - mIN WiN RISK CS iIiiiN RASO-3 CAS WE 08-15 2--viiBii . ilB1 e!. » 'a D) 74ALS244 PSUFI PBUFO n" ADDRESS RFI/O og: n CTIJ. 1 RASO-3 r- NS32016. NS32201 NS32082" • RGCK RCO-7,8 74F245 I}' iN'! FROM/TO 1• OIR AD8-15 "'CWlff AO 00-7,8 .A PAL INTERFACE 0 - - mR(M2) CONTROLLER A16-A23 '"01 V"O-- RFCK A A !mrr IROM I/O PORT 10 OIUes. 10 1llA10, 10 FROM I/O PORT Ml MO TLiF/6899-30 FIGURE 14a. DP8400-2/8409A System Interface Block Diagram (See Figure 14b for Byte Write Control Timing) (';-OOt8dO II i Typical Applications (Coollo"'" Q CPU CLOCK IRGCKI L!l-1l-~ ~r- II ~ \ rIf OP8400/MEMORY DATA BUS 1 \ "READ" MEMDRY DATA K "WRITE" CORRECTED AND NEW DATA ~ / ~ VI CSLE OLE. on CHECK BITS ,--- \ \ J 1"READ" MEMDRY CHECK BITS \ \ READ "WRITE" NEW CHECK BITS ·1 \ \ M2 J JRITE r r- DATA TftANSMIT lml'IE TL/F/6899-31 FIGURE 14b. DP8400·2 16·Blt Configuration, Byte Write Timing 2-36 Typical Applications (Continued) r OLE 1-- VALID DATA ----~-'S-l:- DLE/CSLE - - - - - - - 'H =1 ---- TL/F/6899-32 FIGURE 15. Timing Waveform for Set-Up and Hold Time 437.0. 50pF TLiF/6899-34 237k.o. TL/F/6899-33 (a) TRI-STATE LOAD (b) TEST LOAD FIGURE 16. Loading Circuit OES SO-~-.... _--lo9V ~+--'-l---lo4V ~+-"",\:,----1.4V SO-~-"'I 1'---lo9V TL/F/6899-35 FIGURE 17. TRI-STATE Measurement 2-37 PI ~ ~ CC) D.. '?A National PRELIMINARY ;;: ~ Semiconductor C ~ CC) D.. C DP8402A/DP8403/DP8404/DP8405 32-Bit Parallel ..... Error Detection and Correction Circuits (EDAC's) C') <:) ~ CC) D.. General Description ..... The DP8402A, DP8403, DP8404 and DP8405 devices are 32-bit parallel error detection and correction circuits (EDACs) in 52-pin DP8402A and DP8403 or 48-pin DP8404 and DP8405 600-mil packages. The EDACs use a modified Hamming code to generate a 7-bit check word from a 32-bit data word. This check word is stored along with the data word during the memory write cycle. During the memory read cycle, the 39-bit words from memory are processed by the EDACs to determine if errors have occurred in memory. Single-bit errors in the 32-bit data word are flagged and corrected. C ~ <:) ~ CC) D.. C Single-bit errors in the 7-bit check word are flagged, and the CPU sends the EDAC through the correction cycle even though the 32-bit data word is not in error. The correction cycle will simply pass along the original 32-bit data word in this case and produce error syndrome bits to pinpoint the error-generating location. Double bit errors are flagged but not corrected. These errors may occur in any two bits of the 39-bit word from memory (two errors in the 32-bit data word, two errors in the 7-bit check word, or one error in each word). The gross-error condition of all lows or all highs from memory will be detected. Otherwise, errors in three or more bits of the 39-bit word are beyond the capabilities of these devices to detect. Read-modify-write (byte-control) operations can be performed with the DP8402A and DP8403 EDACs by using output latch enable, LEDBO, and the individual DEBO thru OEB3 byte control pins. Diagnostics are performed on the EDACs by controls and internal paths that allow the user to read the contents of the DB and CB input latches. These will determine if the failure occurred in memory or in the EDAC. Features • • • • • • Detects and corrects single-bit errors Detects and flags double-bit errors Built-in diagnostic capability Fast write and read cycle processing times Byte-write capability ... DP8402A and DP8403 Fully pin and function compatible with TI's SN74ALS632A thru SN74ALS635 series System Environment 8 I PROCESSOR CONTROL EDAC CHECK BITS & SYNDROME :1+;'~2~(~~I__DP_84_02~I~J'7 • !: ERROR' FlAGS 7,. MEMORY _ TLiF 18535-1 2-38 o"0 co .1:>0 o Simplified Functional Block and Connection Diagrams 4 32,; DATA WORD • S 7, 4 DATA BIT I/O • 32, ; LATCH CONTROL & OUTPUT ENABLE CHECK BIT GENERATOR ~ 32 CHECK BIT I/O & MUX 7 ; N » ~ ....... o"0 CHECK BITS & SYNDROME co .1:>0 o 1, ; 4 W ....... OUTPUT ENABLE 7 o"0 7 co .1:>0 o .1:>0 ....... ERROR DETECTION & CORRECTION • CONTROL DECODER o"0 co .1:>0 o 2, ; MODE SIGNALS U1 2 ERROR FLAG TL/F/8535-2 Device Package Byte-Write Output DPB402A DPB403 DPB404 DPB405 52-pin 52-pin 4B-pin 4B-pin yes yes no no TRI-STATE® Open-Collector TRI-STATE Open-Collector Dual-In-Line Packages Plastic Chip Carrier (.) U MERR MERR ERR ERR OBO so OBI OB31 081 NC DB3 DB4 DBS OEBO DB6 DB7 GND GND DB8 DB9 OEBl DB10 DBll 0812 DB13 DB14 OB30 082 OB3 0829 OB28 085 0827 OE08 0826 OB6 OB25 DB7 OB24 GND GND OB8 OB23 089 OB9 OB22 OEBI OBIO OB21 DBII OB20 OEBO GNO DB8 0823 DBII DB20 OBI2 OBI9 DBI9 DBI3 OBI8 OBI8 OB14 OBI7 OBIS OBI 6 OBH OBIS OBI6 CB6 CBO CBI CB6 CBO CBS CBI CB2 TL/F/8535-10 ~ _ _ 0 en 0 ~~ ~u c.J 9 8 7 6 5 4 3 2 1 6867666564636261 10 60 11 59 12 58 13 57 14 56 15 55 16 54 17 53 18 52 19 51 20 50 21 49 22 48 23 47 24 46 25 45 26 44 2728293031323334353637383940414243 NC NC 0828 OB27 OB26 OEB3 OB25 OB24 GND GNO OB23 OB22 OEB2 OB21 OB20 0819 OB18 TL/F/8535-11 Top View CB2 CB3 CB3 Top View I",\g &: iii ~I~ elS 8 ZZQOQ~~~»~~QQQZZ TLlF/8535-3 Top View Order Number DP8402AD, DP8403D, DP8404D or DP8405D See NS Package Number D48A or D52A 2-39 Order Number DP8402AV See NS Package Number V68A Mode Definitions PCC Pin Definitions DP8402A MODE PIN NAME DESCRIPTION S1 SO MODE OPERATION o L L WRITE Input dataword and output checkword 1 L H DIAGNOSTICS Input various data words against latched checkword/output valid error flags. 2 H L READ & FLAG Input dataword and output error flags 3 H H CORRECT Latched input data and checkword/output corrected data and syndrome code pin 1 LEDBO 4 5 6 EFffi' 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Pin Definitions so, 51 Control of EDAC mode, see preceding Mode Definitions DBO thru DB31 1/0 port for 32 bit dataword. CBO thru CB6 1/0 port for 7 bit checkword. Also output port for the syndrome error code during error correction mode. Dataword output buffer enable. When high, OEBOthru OEB3 output buffers are at TRI-STATE. Each pin (DP8402A, controls 8 1/0 ports. OEBO controls DBO DP8403) thru DB7, OEBl controls DB8 thru DB15, OEB2 controls DB 16 thru DB23 and OEB3 controls DB24 thru DB31. Data word output Latch enable. When high LEDBO (DP8402A, it inhibits input to the Latch. Operates on all DP8403) 32 bits of the dataword. OEDB TRI-STATE control for the data 1/0 port. (DP8404, When high output buffers are at DP8405) TRI-STATE. OECB Checkword output buffer enable. When high the output buffers are in TRI-STATE mode. Single error output flag, a low indicates at least a single bit error. Multiple error output flag, a low indicates two or more errors present. Vee 2 3 22 23 24 25 26 27 28 29 30 31 32 33 34 MERR DBO DBl DB2 NC NC NC DB3 DB4 DB5 OEBO DB6 DB7 GND GND DB8 DB9 OEBl DB10 DB11 DB12 DB13 DB14 NC NC NC DB15 NC CB6 CB5 CB4 pin 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 OECB CB3 CB2 CBl CBO DB16 DB17 NC NC DB18 DB19 DB20 DB21 OEB2 DB22 DB23 GND GND DB24 DB25 OEB3 DB26 DB27 DB28 NC NC NC NC DB29 DB30 DB31 SO 51 Vee TABLE I. Write Control Function Memory Cycle EDAC Function Write Generate check word Control S1 SO L Data 1/0 DB Control OEBn or OEDB DB Output Latch DP8402A, DP8403 LEDBO Check 1/0 CB Control OECB Input H x Output check bitst L L Error Flags ERR MERR H H fSee Table" for details on check bit generation. Memory Write Cycle Details During a memory write cycle, the check bits (CBO thru CB6) are generated internally in the EDAC by seven 16-input parity generators using the 32-bit data word as defined in Table 2. These seven check bits are stored in memory along with the original 32-bit data word. This 32-bit word will later be used in the memory read cycle for error detection and correction. 2-40 TABLE II. Parity Algorithm Check Word 32-Blt Data Word Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CBO X X X X X X X X X X X X X X X CB1 X X X X X X X X X X X X X X CB2 X X X X X X X X X X X X X X X X CB3 X X X X X X X X X X X X X X X CB4 X X X X X X X X X X X X X X X X CB5 X X X X X X X X X X X X X X X X CB6 X X X X X X X X X X X X X X X The seven check bits are parity bits derived from the matrix of data bits as indicated by "X" for each bit. Check bits 0, 1, 2 are odd parity or the exclusive NORing of the "X"ed bits for the particular check bit. Check bits 3, 4, 5, 6 are even parity or the exclusive ORing of the "X"ed bits for the particular check bit X X X X X Memory Read Cycle (Error Detection & Correction Details) During a memory read cycle, the 7 -bit check word is retrieved along with the actual data. In order to be able to determine whether the data from the memory is acceptable to use as presented on the bus, the error flags must be tested to determine if they are at the high level. next two cases of single-bit errors give a high on MERR and a low on ERR, which is the Signal for a correctable error, and the EDAC should be sent through the correction cycle. The last three cases of double-bit errors will cause the EDAC to Signal lows on both ERR and MERR, which is the interrupt indication for the CPU. The first case in Table III represents the normal, no-error conditions. The EDAC presents highs on both flags. The TABLE III. Error Function Total Number of Errors 32-Blt Data Word 7-Blt Check Word 0 1 0 1 2 0 0 0 1 1 0 2 Error Flags ERR MERR H L L L L L The DP8402 check bit syndrome matrix can be seen in TABLE II. The horizontal rows of this matrix generate the check bits by selecting different combinations of data bits, indicated by "X"s in the matrix, and generating parity from them. For instance, parity check bit "0" is generated by EXCLUSIVE NORing the following data bits together; 31, 29, 28, 26, 21, 19, 18, 17, 14, 11, 9, 8, 7, 6, 4, and O. For example, the data word "00000001 H" would generate the check bits CB6-0 = 48H (Check bits 0, 1, 2 are odd parity and check bits 3, 4, 5, 6 are even parity). During a WRITE operation (mode 0) the data enters the DP8402 and check bits are generated at the check bit input! output port. Both the data word and the check bits are then written to memory. H H H L L L Data Correction Not applicable Correction Correction Interrupt Interrupt Interrupt During a READ operation (mode 2, error detection) the data and check bits that were stored in memory, now possibly in error, are input through the data and check bit 1/0 ports. New check bits are internally generated from the data word. These new check bits are then compared, by an EXCLUSIVE NOR operation, with the original check bits that were stored in memory. The EXCLUSIVE NOR of the original check bits, that were stored in memory, with the new check bits is called the syndrome word. If the original check bits are the same as the new check bits, a no error condition, then a syndrome word of all ones is produced and both error flags (ERR and MERR) will be high. The DP8402 matrix encodes errors as follows: TABLE IV. Read, Flag, and Correct Function Memory Cycle EDAC Function Read Read & flag Read Latch input data and check bits H H Output corrected data H & syndrome bits 'rSee Table III for error description. Read Data I/O DB Control OEBn or OEDB DB Output Latch DP8402A, DP8403 LEDBO Check 1/0 L Input H X Input H Enabledt H Input data latched H L Input check word latched H Enabledt H Output corrected data word L X Output syndrome bits+ L Enabledt Control 81 80 :!:See Table V for error location. 2-41 CB Control 0Eai Error Flags ERR MERR Memory Read Cycle (Error Detection & Correction Details) (Continued) 2) A single check bit error will cause that particular check bit to go low in the syndrome word. 3) A double bit error will cause an even number of bits in the syndrome word to go low. The syndrome word will then be the EXCLUSIVE NOR of the two individual syndrome words corresponding to the 2 bits in error. The two-bit error is not correctable since the parity tree can only identify single bit errors. If any of the bits in the syndrome word are low the "ERR" flag goes low. The "MERR" (dual error) flag goes low during any double bit error conditions. (See Table III). Three or more simultaneous bit errors can cause the EOAC to believe that no error, a correctable error, or an uncorrectable error has occurred and will produce erroneous results in all three cases. It should be noted that the gross-error conditions of all lows and all highs will be detected. 1) Single data bit errors cause 3 or 5 bits in the syndrome word to go low. The columns of the check bit syndrome matrix (TABLE II) are the syndrome words for all single bit data errors in the 32 bit word (also see TABLE V). The data bit in error corresponds to the column in the check bit syndrome matrix that matches the syndrome word. For instance, the syndrome word indicating that data bit 31 is in error would be (CBS-CBO) = "0001010", see the column for data bit 31 in TABLE II, or see TABLE V. During mode 3 (SO = S1 = 1) the syndrome word is decoded, during single data bit errors, and used to invert the bit in error thus correcting the data word. The corrected word is made available on the data I/O port (OBO thru OB31), the check word I/O port (CBO thru CB6) presents the 7-bit syndrome error code. This syndrome error code can be used to locate the bad memory chip. TABLE V. Syndrome Decoding Syndrome Bits Syndrome Bits Error Syndrome Bits Error Syndrome Bits Error Error 6543210 6 5 432 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 L L L L L L L L L L L L L L L L L L L L L L H H L unc H 2-bit L 2-bit H unc L L L L H H H H L L L L L L L L L L L L L L H H L 2-bit H unc L OB7 H 2-bit H H H H L L L L L L L L L L L L L L L L L L H H L 2-bit H unc L unc H 2-bit H H H H H H H H L L L L L L L L L L L L L L H H L unc H 2-bit L 2-bit H OB23 L L L L L L L L L L L L L L L L H H H H L L H H L 2-bit H unc L unc H 2-bit L L L L H H H H L L L L L L L L H H H H L L H H L H L H DB6 2-bit 2-bit DB5 H H H H L L L L L L L L L L L L H H H H L L H H L unc H 2-bit L 2-bit H unc H H H H H H H H L L L L L L L L H H H H L L H H L H L H 2-bit OB22 OB21 2-bit L L L L L L L L L L L L H H H H L L L L L L H H L 2-bit H unc L OB31 H 2-bit L L L L H H H H L L L L H H H H L L L L L L H H L H L H OB4 2-bit 2-bit OB3 H H H H L L L L L L L L H H H H L L L L L L H H L unc H 2-bit L 2-bit H OB15 H H H H H H H H L L L L H H H H L L L L L L H H L H L H 2-bit OB20 OB19 2-bit L L L L L L L L L L L L H H H H H H. H H L L H H L unc H 2-bit L 2-bit H OB30 L L L L H H H H L L L L H H H H H H H H L L H H L 2-bit H OB2 L unc H 2-bit H H H H L L L L L L L L H H H H H H H H L L H H L 2-bit H unc L DB14 H 2-bit H H H H H H H H L L L L H H H H H H H H L L H H L H L H OB18 2-bit 2-bit CB4 L L L L L L L L H H H H L L L L L L L L L L H H L 2-bit H unc L OB29 H 2-bit L L L L H H H H H H H H L L L L L L L L L L H H L OBO H 2-bit L 2-bit H unc H H H H L L L L H H H H L L L L L L L L L L H H L unc H 2-bit L 2-bit H OB13 H H H H H H H H H H H H L L L L L L L L L L H H L 2-bit H OB16 L unc H 2-bit L L L L L L L L H H H H L L L L H H H H L L H H L H L H OB28 2-bit 2-bit OB27 L L L L H H H H H H H H L L L L H H H H L L H H L 2-bit H OB1 L unc H 2-bit H H H H L L L L H H H H L L L L H H H H L L H H L H L H 2-bit OB12 OB11 2-bit H H H H H H H H H H H H L L L L H H H H L L H H L H L H L L L L L L L L H H H H H H H H L L L L L L H H L H L H OB26 2-bit 2-bit OB25 L L L L H H H H H H H H H H H H L L L L L L H H L 2-bit H unc L unc H 2-bit H H H H L L L L H H H H H H H H L L L L L L H H L H L H 2-bit OB10 OB9 2-bit H H H H H H H H H H H H H H H H L L L L L L H H L unc H 2-bit L 2-bit H CB2 L L L L L L L L H H H H H H H H H H H H L L H H L 2-bit H OB24 L unc H 2-bit L L L L H H H H H H H H H H H H H H H H L L H H L H L H, unc 2-bit 2-bit CB6 H H H H L H H H L L OB8 L H H H L H 2-bit L H H H H L 2-bit L H H H H H CBS I CB X = error in check bit X DB Y = error In data bit Y 2-bit = double-bit error unc = uncorrectable muHlbit error 2-42 OB17 2-bit 2-bit CB3 H H H H H L L 2-bit H H H H H L H CB1 H H H H H H L CSO U II II n n n n n H H none C "'0 TABLE VI. Read-Modify-Write Function MEMORY EDAC FUNCTION CYCLE CONTROL 51 SO BYTEnt co DB OUTPUT CB LATCH CHECK 1/0 OEBnt LEDBO CONTROL "" ERROR FLAG ERRMERR Read Read & Fiag H L input H X input H Enabled Read Latch input data & check bits H H Input data latched H L Input check word latched H Enabled Hi-Z H Output Syndrome bits L Read Modify /write Latch corrected data word into output latch Modify appropriate byte or bytes & generate new check word H L H L Output data word latched H Input modified BYTEO H Ouput unchanged BYTEO L H "'0 "" -"" "" C (0) C "'0 co c Enabled C "'0 co "" Output check word L H H Diagnostic Operations The OP8402A thru DP8405 are capable of diagnostics that allow the user to determine whether the EOAC or the memory is failing. The diagnostic function tables will help the user to see the possibilities for diagnostic control. In the diagnostic mode (S1 = L, SO = H), the checkword is latched into the input latch while the data input remains transparent. This lets the user apply various data words against a fixed known checkword. If the user applies a diagnostic data word with an error in any bit location, the ERR flag should be low. If a diagnostic data word with two errors in any bit location is applied, the MERR flag should be low. After the checkword is latched into the input latch, it can be verified by taking OECB low. This outputs the latched checkword. With the DP8402A and DP8403, the diagnostic data word can be latched into the output data latch and verified. It should be noted that the DP8404 and OP8405 do not have this pass-through capability because they do not contain an output data latch. By changing from the diagnostiC mode (S1 = L, SO = H) to the correction mode (S1 = H, SO = H), the user can verify that the EDAC will correct the diagnostic data word. Also, the syndrome bits can be produced to verify that the EDAC pinpoints the error location. Table VII DP8402A and OP8403 and Table VIII DP8404 and DP8405 list the diagnostic functions. 2-43 C co tOEBO controls DBo-DB7 (BYTEO). 0EB1 controls DBa-DB15 (BYTE1). OEB2 controls DB16-DB23 (BYTE2). 0EB3 controls DB24-DB31 (BYTE3). The DP8402A and DP8403 devices are capable of bytewrite operations. The 39-bit word from memory must first be latched into the DB and CB input latches. This is easily accomplished by switching from the read and flag mode (S1 = H, SO = L) to the latch input mode (S1 = H, SO = H). The EDAC will then make any corrections, if necessary, to the data word and place it at the input of the output data latch. This data word must then be latched into the output data latch by taking LEOBO from a low to a high. Byte control can now be employed on the data word through the OEBO through OEB3 controls. OEBO controls DBO-DB? (byte 0), OEB1 controls DB8-DB15 (byte 1), OEB2 controls DB16-DB23 (byte 2), and OEB3 controls OB24-DB31 (byte 3). Placing a high on the byte control will disable the output and the user can modify the byte. If a low is placed on the byte control, then the original byte is allowed to pass onto the data bus unchanged. If the original data word is altered through byte control, a new check word must be generated before it is written back into memory. This is easily accomplished by taking control S1 and SO low. Table VI lists the read-modify-write functions. » C U1 H Read-Modify-Write (Byte Control) Operations C N TABLE VII. OP8402A, OP8403 Olagnostlc Function CONTROL EOAC FUNCTION Read & flag OATAI/O S1 SO H L Input correct data word H L H H Latch input check word while data input latch remains transparent L H Input diagnostic data wordt Latch diagnostic data word into output latch L H Input diagnostic datawordt Latch diagnostic data word into input latch Output diagnostic data word & syndrome bits Output corrected diagnostic data word & output syndrome bits OBBYTE OBOUTPUT CONTROL LATCH 'OEBn LEOBO H H H H Input diagnostic data word latched H Output diagnostic data word H Output corrected diagnostic data word H H L 0ECIi H Input check bits latched H L CB CONTROL Input correct check bits X H CHECK 1/0 L ERROR FLAGS ERR MERR H Enabled H Output latched check bits L Hi-Z H Output syndrome bits L Hi-Z H Output syndrome bits L H Enabled Enabled Enabled Hi-Z H Output syndrome bits L Hi-Z H Enabled tDlagnostic data Is a data word with an error In one bH location except when testing the ~ error flag. In this caee, the diagnostic data word will contain errors In two bit Iccatlons. TABLE VIII. OP8404, OP8405 Oiagnostic Function OBCONTROL OEOB CHECK 1/0 Input correct data word H H Input diagnostic datawordt H Input diagnostic data wordt H Input diagnostic data word latched H Output corrected diagnostic data word L EOAC FUNCTION CONTROL S1 SO Read & flag H L Latch input check bits while data input latch remains transparent L Output input check bits L Latch diagnostic data into input latch H Output corrected diagnostic data word H H OATAIIO OBCONTROL ERROR FLAGS OEC! Elm Mm'I Input correct check bits H H H H Input check bits latched H Enabled H Output input check bits L Enabled Output syndrome bits L Hi-Z H Output syndrome bits L HI-Z H Enabled Enabled tDiagnoatic data la a data word with an error In one b~ location ClXCapt when t6itin~ the liilElm error iiag. in this case, the dlagnoatic data word will contain errors In two bit locationa. 2-44 DP8402A, DP8403 Logic Diagram (Positive Logic) DECODER I X/y 0 1, 0 so - 1 SYNDROME GENERATOR I 7 3 ~1 ~ r---;;- h 1 SI - - 3 2 h 2 CHECK-BIT GENERATOR r-+- h h h h LATCHES 7 CBO-CB6 -- r--Cl --- h 7 lD MUX u..-:r BUFFERS ECB lD 8 ERROR DETECTOR "'- EN ERROR 0 - - ERR MULTIERROR 0 - - MERR 7 lD 32 BUFFERS -* - lD 8 EN """---" 7 ~ lD 8 8 8 8 32. 0 8 8 7 LATCHES DB24- DB31 EB3 Gl (7 X-OR) 11,.. ' - - - Cl 088-DB15 EB2 '-- 7 - 0816- DB23 EBI GO EN DBO- 087 EBO ~ W/i!rMgfq'@ffi ;-tpd-: WI#//$~%WWIM//;Xr-----V-ALID...,M""'ER"..RfLA-G------..... )0i///aMkw//k TLlF/8535-8 FIGURE 1. Read, Flag, and Correct Mode ~th(8)--': so i j ;:'=:!R~EA~D=:"~,.====~CO~RR~ECT:!.:===:::_;_--WRITE S1..J : ---<~=t::, WO~ m»<::)( ---< WO~ m»<::)( ---< WO~D m»<::)( ----< WO~D m»<::)( OUTPUT CORRECTED DATA WORD ---- ' ~,.~-NP-UT-N-OD-If-IED-BYT--E-0"'>$-~ DBO THRU DB7 INPUT DATA 088 THRU 0815 INPUT DATA OUTPUT CORREcrf DATA WORD ~ DB16 THRU DB23 INPUT DATA OUTPUT CORRE~D DATA WORD >$- 0824 THRU 0831 OEBO OEBl DEB2 CBO THRU CB6 ERR INPUT DATA ' , OUTPUT CORRECT~ DATA WORD I --~""------I , I~------------~------~ OUTPUT SYNDROME CO~E INPUT CHECK WORD - , ---------------P-------~~-------~-------------\'-_____V_AL_~_E~RR~fLA~G~__~1 NERR--------------~\~~~~-~-_~~~~-~-~-_-_-~-/~------------_ VAUD NERR fLAG . TL/F18535-7 FIGURE 2. Read, Correct Modify Mode 2·51 I I Switching Waveforms (Co",,,,,,, ..... I so L :-""(5)-1 ~----~'--~I~------------------ SI : INPUT DIAGNOSTIC : / DATA WORD Q ----,~'''---»»O< i OUTPUT DIAGNOSTIC OUTPUT CORRECTED / DATA WORD / DATA WORD X; ' "'_th(lD)"": ' --~------~--~:--~ Q ;-.. .~I.=:::l.:~t!.U~(4~)_+-_ _ _ _-!1-- tpd-: ___.;-.______- ...1 ; I $t.tl'~ 1- -, r-- I ~th12)-.: 1 -, , :.-- ~d CBO THRU CB6 llU(6) -+i : OUTPUT VALID CHECK WORD :. "": ,-------------------~~ OUTPUT SYNDROME CODE ~(11) .. I: - - Ipd --I~I----~:-~-~:--------------r---__ ipd - : _ .. ,. ------i----.... ---"""""--------- - - _. ERR, \ : ores ------------_ .. VERIFY PROPER OPERATION OF ERR FLAG, FLAG SHOULD BE LOW WITH A DIAGNOSTIC DATA WORD WITH A SINGLE ERROR VERIFY pp( ROPER OPERATION OF ~R FLAG FLAG SHOULD BE HIGH) MERR : - - Ipd ---l ----------jP\ r-- Ipd --I :,--------------------------- .. ------~-----. VERIFY PROPER OPERATION OF /(ERR FLAG (FLAG SHOULD BE HIGH) ~·------f~f:~--------- VERIFY PROPER OPERATON OF MERR FLAG, FLAG SHOULD BE LOW WITH A DIAGNOSTIC DATA WORD WITH A DOUBLE ERROR TL/F/B636-B FIGURE 3. Diagno8tlc Mode 2·52 C '1J 0) v, :c I DP84300 --. PROGRAM lIABLE DMDER CPU CLOCK ADORESS/DATA BUS ADO-31 1/ . I'r- I DECODER . ~ " --y 1 ~ 74AS245 TRANSCEIVERS (4) WAIT INTERRUPT I\) RFCK I I LATCHES I 32 BIT PROCESSOR y I CHIP SELECT 7<4ALS373~ " ADO-31 I/' .. ~ l.-...-. TRANCEIVER ENABLES (4) DP8409/19 CONTROL CHIP SELECT c I RC0-7.8.9 RFRO RASO.l.~ CAS RFSH 8 / .. v 2 WE o ~ » 5' S- irn -CD Co o :::J' CD C '1J WIN 0) . vi 010-31 0I:loo .... ...... .... CO 0) ...... ~ 0) DATA I/O 0-31 '-~ MODE. LATCH. BUFFER CONTROL 74ALS244 BUFFERS (4) ...... ERROR FLAGS Jl-'I L ~ II 000-31 'I t CHECK BIT I/O 0-6 ENABLE DATA AND CHECKBITS OUT RASO.l.2.3 CAS .& WE RASIN DP8402A INTERFACE CONTROLLER LOGIC WAIT DIAGNOSTIC INPUTS I/O PORT INPUTS 2 BANKS OF 39 (256K DRAM'S) (1M DRAM'S) ~J I INTERRUPT ..., ROCK - DP840BA/09A. CS DP8418/19. OR DP8428/29 DO-31 'I '~ SYSTEIot CLOCK. Y BYTE ENABLES. ADDRESS STROBE. AND READ / WRITE ADS 00-7.8.9 A -' 4 4 0I:loo MEMORY 2 TO 8M BYTES ...J. PLUS CHECK BITS .,. 00-7.8.9 . --y 74ALS244 BUFFER A 'I ENABLE DATA AND CHECKBITS OUT CHECK BITS IN 0-6 CHECK BITS OUT 0-6 CD ~ i 3 c i" co ; 3 SOl'8dO Il'Ol'8dO ItOl'8dO 1"~Ol'8dO ~ o ~ CIO ,----------------------------------------------------------------------------, DP8402A Interfaced to the DP8420A/21A/22A System Diagram D. C ...... CLK, DELCLK ~ o D. C CLK ...... ('I) ~ 7~~~~3is3 ~ J~B1Bl;-R"'C:;;'0---::-9""""1"'0-1:-!1'1 DP8420t~2~ A/22A ADD/DATA BUSADO-31 - ~ ADS, AREQ C INTERRUPT... 32 BIT CPU ...... SYSTEM CLK, :; BYTE ~ o D. C ,.. ~~~:~~ ~E~ORY RASO-3, CASo-3 QO-8, 9, 10, WE UP TO 64 ~ BYTES UP TO 4 BANKS OF 39 DRA~S PER BANK (UP TO 4 M BIT DRAMS) CONTROLLER WAIT CIO D. CS .r:~=,~ ~ CIO WAITIN, EXTENDRFSH, 74AS245 TRANSCEIVERS IJIL-,..JIl..-_ _ _W_IN_ _ _ _ _ _ _ _ _ _-"I r r b: 010-31 LIA _ _ _ _,/\f";~~ ~~:J 74ALS2441 r.-JDlR EN STROBE, WRITE/READ [ us ~~'----.,r~~;_;,-~~~~D~~~ 1 ~ ERROR CORRECTION t"i;iODE LATCH BUFFER CONTROL INTERFACE LOGIC BUS CYCLE RETRY ERROR FLAGS ENABLE DATA AND CHECK BITS OUT DAOT: 3/1 0 DP8402A CHECK BITSO - 6 VI I...E;ioN~_., 000-31 y J b: r - - - - - v i CHECK I . '-j74ALS244 VI I EN BITS IN 0-6 ...C_H_EC_K_B_ITS_O_UT_0_-_6.....1 Y I TIIF18535-12 2-54 r-------------------------------------------------------------------------------------, CD Co) N ~National ~ Semiconductor 54F/74F632 32-Bit Parallel Error Detection and Correction Circuit General Description check word, or one error in each word). The gross-error condition of all LOWs or all HIGHs from memory will be detected. Otherwise, errors in three or more bits of the 39bit word are beyond the capabilities of these devices to detect. Read-modify-write (byte-control) operations can be performed by using output latch enable, LEDBO, and the individual OEBo through OEB3 byte control pins. Diagnostics are performed on the EDACs by controls and internal paths that allow the user to read the contents of the Data Bit and Check Bit input latches. These will determine if the failure occurred in memory or in the EDAC. The 'F632 device is a 32-bit parallel error detection and correction circuit (EDAC) in a 52-pin or 68-pin package. The EDAC uses a modified Hamming code to generate a 7-bit check word from a 32-bit data word. This check word is stored along with the data word during the memory write cycle. During the memory read cycle, the 39-bit words from memory are processed by the EDAC to determine if errors have occurred in memory. Single-bit errors in the 32-bit data word are flagged and corrected. Single-bit errors in the 7 -bit check word are flagged, and the CPU sends the EDAC through the correction cycle even though the 32-bit data word is not in error. The correction cycle will simply pass along the original 32-bit data word in this case and produce error syndrome bits to pinpoint the error-generating location. Dual-bit errors are flagged but not corrected. These errors may occur in any two bits of the 39-bit word from memory (two errors in the 32-bit data word, two errors in the 7 -bit Features • • • • • Detects and corrects single-bit errors Detects and flags dual-bit errors Built-in diagnostic capability Fast write and read cycle processing times Byte-write capability Logic Symbol -132 DBo- DB31 -so MERR ERR -51 - -+I_t~1L-1~_+~-1'sf I J) lSI ~ CORRECTED OATA .;-+.....-----------------1-4-----\"---... TO DOL AND DDB ANY ERROR ~CGrDtlrt~rt_rtt_;'~1~~~IJ_-l--!_~--~I,J _________ I ~ ____ r-IH-+++,L-I L I____________ JI ~ ERROR ENCODER SO Cll IT[ II . BIT rCK} INPUT LATCH I-- f-- t----- t READ "----_ _ _ _---1'I II TL/F/5032··2 FIGURE la_ Error Correction 4·Blt Functional Diagram 2-56 s Y MEMORY DATA BUS S T E SYSTEM DATA M '\ - I HIGH ~ ~ OLE HIGH X I INTERNAL DATA BUS DATA INPUT LATCH J J 1 t I 1 CHECK BIT GENERATOR IJ SYN~~~ME. J -1 .J SYNDROME BIT GEN CHECK BIT INPUT LATCH ~ INTERNAL t CSLE HIGH m 0Bii ~ J J DATA BIT CORRECTOR r-+ DATA OUTPUT LATCH BUFFER tI DATA ERROR LOCATOR ~ M I-- E M o t ill R Y LOW ERROR TYPE DECOOER • I INTERNAL CHECK BIT BUS --'- DP840D CHECK BIT OUTPUT LATCH BUFFER ~ GENERATED CHECK BITS CHECK·BIT 110 PORT • M2 ERROR FLAGS MEMORY CHECK BIT BUS MIl Mol LOW LOW LOW TLiF/S032-3 FIGURE 2a. DP8400 Write To Memory Cycle S Y MEMORY DATA BUS S T E SET LOW TO ENABLE AFTER MEMORY DATA IS DISABLED MEMORY DATA M ( J ~ ~ HIGH HIGH OLE t J J I 1 CHECK BIT GENERATOR ~ .J SYNDROME BIT GEN t CSLE C~W J l~~~~ J r INTERNAL SYNDROME BUS J J OBI ,I '" 16·BIT INTERNAL DATA BUS DATA INPUT LATCH OBO 'J I " DP8400 ERROR FLAGS VALID ~ M E M t-- o HIGH (READ) - MEMORY CHECK BITS I6·CHECK·BIT 110 PORT • M2 R Y LOW OLE + CHECK BIT OUTPUT LATCH BUFFER FIGURE 2b. DP8400 Read From Memory Cycle 2·57 DATA OUTPUT LATCH BUFFER I I I ERROR TYPE DECODER • ~ r---l + DATA ERROR LOCATOR Y 6·BIT INTERNAL CHECK BIT BUS DATA BIT CORRECTOR MIl Mol LOW LOW MEMORY CHECK BIT BUS TL/F/S032-4 In the case of the DP8400 with 16 data bits and 6 check bits, there are 16 AND-gates to decode the 6 syndrome bits to determine the data bit in error. Table I shows the DP8400 matrix, called a Nelson Code, which has some unique features concerned with double soft error correction. For the purposes of this description, the matrix may be considered to be a form of Modified Hamming Code. The matrix has two functions: horizontally it tells us the value of the generated check bits for any data word when writing to memory, and vertically it tells us the syndrome word for any data bit in error. In a write cycle to memory, a '1' in any row indicates that the data bit in that column helps generate the parity bit in that row. For example, check bit 1 checks the parity of data bits 3, 6, 8, 9, 11, 13, 14 and 15, and generates even parity for those data bits. In a read cycle from memory, three or five of the six syndrome bits will go high for a single data bit error, and the columns represent the syndrome word, so the data bit in error is the number at the top of the column for that syndrome word. The 16 AND-gates each decode one of the 16 syndrome words shown in the col.umns of Table I, to locate the error. If there is a data bit error, one of the outputs of the 16 AND-gates will go high, to complement the data bit in error. syndrome input latches (CIL and SIL), respectively. These are latched in as CSLE goes low. (In 16-bit operation, DES, Output Enable Syndromes, will be set low permanently, inhibiting CSLE to SIL, which remains in the power-up reset condition so that it does not affect the simplified block diagram.) OLE, when set low, allows internal information into the data and check bit output latches (and the syndrome output latch, not shown). As rn:E goes high, this Information becomes latched. For some less complex designs, DLE, CSLE and OLE may be linked together. Providing OLE was low to allow corrected data into DOL, then C5'BO and <:581, when set low, enable the two data output buffers to present corrected data to the system. Data is enabled or disabled within 15 ns of these inputs going low or high, respectively. The DP8400 has three mode pins, M2, Ml and MO, which offer eight major modes of operation, deSignated 0 to 7. The most important two are Normal Write and Normal Read, and for these Ml and MO are set low. M2 is READ/WRITE so Normal Write is mode 0 and Normal Read is mode 4. Other modes are used for the Double Complement Correct approach (Modes 1, 3 and 5) and for diagnostics (Modes 2 and 6). Mode 7 used when expanded to more than 16 data bits and fast correction times are required. If two errors have occurred, the syndrome word is simply the Exclusive-OR of the syndrome words of the two individual bits in error, whether data or check bits, and is always even parity. First, if two check bits are in error, the corresponding two syndrome bits will go high. Second, for one data bit and one check bit error, then either two, four or six syndrome bits will go high. Finally, if two data bits are in error, again two, four or six syndrome bits go high. Thus a parity on the syndromes will indicate any two errors. This is important because if we know there are two errors, the DP8400 can attempt to correct them. The third error flag, El, is the parity of the syndrome bus and check bit error. The DP8400 provides three error flags AE (Any error), EO and El, as shown in Table II, so that the exact nature of the error can be determined. NORMAL OPERATION WITH A 16 DATA BIT MEMORY The basic requirements for normal operation of the DP8400 are that it generates check bits, detect errors and correct them with minimum delays, and that it be easy to use. In normal operation Ml and MO are set low. Figure 28 shows how the DP8400 generates check bits when writing data to memory. DLE may be kept high, ME: low, CSLE low, and M2 low so that the DP8400 is in Mode O. System data is presented to the data 1/0 port on pins DO-15, and enters DIL, where it connects to the check bit generator CG. The six generated check bits pass through COL and are enabled (with M2 low) onto the check bit 1/0 port. The six generated check bits will appear 30 ns after the 16 data bits are presented to the data 1/0 port. A write to memory will now store the 16 data bits and 6 corresponding check bits in the selected location of memory. The write cycle is therefore slowed down by 30 ns, which in most memory systems is not significant. CONFIGURATION AND CONTROL OF THE DP8400 The DP8400 has a 16-bit data 1/0 port and an 8-bit check bit 1/0 port (6 bits used with 16 data bits) for applications with memories used with 16-bit microprocessors. The 16-bit data 1/0 port sits on the memory data bus, and the 6 check bit 1/0 port connects directly to the check bit section of memory. In other words, each memory location now contains 16 data bits with 6 check bits. The DP8400 is expandable to beyond 80 data bits, each additional 16 data bits requiring an additional DP8400 without the need for extra logic circuitry. 32-bit wide memory busses are also a popular width for minicomputers. In addition, 16-bit microprocessor systems may use 32-bit memory, because this larger memory data width requires only 7 check bits, a lower percentage overhead of check bits to data bits. Figure 2b shows the paths when reading from memory, with DLE set high to enter the memory data bits into DIL, and CSLE also set high to enter memory check bits into CIL. M2 is set high so that the DP8400 is in Mode 4. The Any Error flag, AE, becomes valid 35 ns after memory data and check bits are valid. Error flags El and EO become valid approximately 15 ns later. Thus, if AE is low, no further operations are necessary. For fast 16-bit microprocessor systems, it may be necessary to introduce a wait state every read cycle to first determine if an error exists. If no error is detected the wait state is removed and the read cycle continues. If an error is detected, then the error flags El and EO must be examined to determine the required action. If the error is a single data bit error, DOL will by now contain corrected data. If there is no check bit error, then COL, which follows CIL when in Mode 4, now contains the original check bits. By taking rn:E high, corrected data bits are latched in DOL, and correct check bits in COL. The memory is now disabled, so that OBO and OBl can be set low to enable corrected data onto ihe data bus, and M2 set low to enable the contents of COL onto the check bit bus. A write to the same location of memory will therefore remove the data bit error if Figures 28 and 2b show a simplified block diagram of the DP8400 with its control signals. The numerous control signals provide ease of use in the many varied applications of this chip. There are three latch enable signals DLE, CSLE and OLE. Whenever DLE is high, data on the data I/O port DO-15 is entered into the data input latch DIL, and is latched in as DLE goes low. This allows either processor or memory data to be present on the data bus for only 3 ns prior to, and held over for 10 ns after DLE goes low. The data can then be removed if desired. Similarly, CSLE, when high, allows check bits on the check bit 1/0 port and external data on the syndrome 1/0 port to enter the check bit and 2-58 it was a soft error. The microprocessor can read the corrected data once the wait signal is removed. OP8400 has been designed to function in all of these applications, making it the most versatile and comprehensive error correction chip available. If the error is a single check bit error, OLE should be set low. DOL contains the contents of OIL, still correct data. Memory can now be disabled so that OBO and OB1, when set low, output correct data, and M2 when set low, allows the generated check bits from OIL to be output on the check bit I/O port. A write to the same location of memory will remove the check bit error if it was a soft error. The microprocessor now reads this correct data when the wait signal is removed. If a double bit error is detected, then other approaches may be taken, as described in the data sheet and later in this application note. The primary features of the OP8400 are discussed in the data sheet; there are, however, a number of other features that become very useful once a designer becomes acquainted with error correcting techniques. ERROR CHECKING AND CORRECTING FOR WIDERTHAN-16-BITS DATA WIDTHS At present, most 16-bit microprocessor systems use a 16-bit wide main memory, partly for simplicity, and also because main memories, in general, have not become large enough in size to justify otherwise. The data sheet shows how to accomplish this with one OP8400, utilizing the matrix of Table I. It is fairly easy to use a memory of twice the microprocessor data width to reduce total chip count when incorporating error correction capability. One example would be a complex 8-bit microprocessor using large main memory. If the memory data width is kept at eight bits, then five check bits are required for error correction for each byte of data. If four banks of memory are required, each bank comprising 13 chips, then 52 total memory chips are required and only 62% of the memory is used for system data. If the memory data width is increased to 16 bits for the same microprocessor-based system, then six check bits are required. These include: expansion beyond 16 data bits, diagnostic routines, error logging (allowing some double error correction), and a novel approach offering fast correction of any double error. This application note discusses how the . :--- ~ DATA 000·31 BUS ~ PARITY BUS 000-15 ~ PO P2 " 0B3 r 0016-31 ~ P3 BYTE { aB2 EMABLES ~ MEMORY 1~>- OBO LATCH { CONTROLS - ... BPO L......o $YNDR OME BUS ~ r ,.. !oo- ... DOO-7 OBO ~ 008·15 OBI B~IJ XP rJ-. OLE OLE elSE EXPANDED LOWER WOIIO (L) So•• t CO-6 DP840D OLE ~ CSLE OBO ,.. !oo- ... DOB-,S DQ()"7 OBI HIGHER WORD (Hl 0PB400 80-6 AE E1 NC~ NC~ EO M2 Ml MO AE M2 EO J Ml MO ~ CRO.. CHiCK ' - - BIT BUS I 11r ERROR LOOGER UNIT (IF REQUIRED) CO•• E1 r--- B" ImlXPr1. EXPANDED ~ DES OES FLAGS I t-+ 1""-;'--" ERROR { ... !o- ... BPO --,-, MODE CONTROLS I TL/F/5032-5 tRefer to discussion in "Other Modes of Operation" under Clearing SIL. >I< '" FIGURE 3. 32-Bit Error Detection and Correction 2-59 Connection sequence must be done according to Table VIII. » z I Co) oQ) The memory now comprises two banks each of 22 chips, totaling 44 memory chlps-a savings of eight memory chips. This saving is offset somewhat by the need to incorporate byte-writing capability, which does require extra components and slows down the memory write cycle. One DP8400 Is still needed, using all 18 bits, and two bidirectional buffers are also required. As a second example, using a 16-bit microprocessor with a memory of eight banks, each comprising 16 bits of data and six check bits, the total is 8 X 22 or 176 memory chips. Once the memory Is widened to 32 data bits with seven check bits, only four banks are required, and the total number of memorY chips reduces to 4 X 39, or 156-a savings of 20 memory chips. This is offset a little by the fact that an extra DP8400 is required, and slightly slower memory write and read cycles are necessary. In some cases, therefore, widening the memory data bus becomes more practical for large memories. Saving memory chips is just one reason why there is a need to be able to expand the DP8400 beyond 16 data bits. Most minicomputers now use 32-bit wide data busses, and soon there will be some 32-bit microprocessors. Other systems use 24 bits, 48 bits, 52 bits, 64 bits or a variety of other data widths. The DP8400 has been configured to be expandable to any data width, even beyond 80 bits, merely by inserting an additional DP8400 for each 16-bit increment in memory data. A section of the chip shown in the data sheet Block Diagram comprises the syndrome input and output latches, SIL andSOL, and a dedicated syndrome 1/0 port. This port has a number of uses not normally needed in simple 16-bit single error correction applications. One use of this syndrome port Is for data widths wider than 16 bits. Only one DP8400 Is required with 16 data bits or less, but if a system uses more than 16 memory data bits, additional DP8400s are required. For example, two DP8400s, one with its 16-bit data port connected to the lower word, and the other to the higher word, can be configured to generate check bits, and detect and correct errors for a 32-bit memory as shown in Figure 3. For writing to memory, both chips will still generate six check bits from the two words of 16 bits. But with more than 26 total data bits, seven check bits are required. Therefore, it is necessary to combine the two sets of check bits to produce seven compOSite check bits to be written to memory as shown In the flow path depicted in Fl{lure 48. This is achieved by outputting the six generated check bits from the lower word DP8400 (deSignated L), and Inputting them to H, the higher word DP8400. The syndrome port of H is available to receive these check bits from L, to be loaded into SIL of H, provided CSLE is high. The six outputs from SIL combine with the six check bits generated in H to create seven compOSite check bits, and this 7-bit combination is output on the check bit port to the memory check bits. Table II shows one of twelve possible ways to combine the two sets of check bits. Note that the lower word matrix for bits 0 and 15 is identical to Table I with the addition of all "O"s for the seventh check bit. The higher word matrix for bits 16 to 31 uses the same rows but in a different order, implying that the check bits from L must be cross-connected to H. For example, memory check bit 5 is generated from check bit 1 of L and check bit 5 of H. Both chips are therefore set to normal write mode when generating check bits. t-_ _ _ _--.;m;;;;L~H ® TL/F/5032-6 FIGURE 4a. E2C2 32-Blt Configuration, Error-Correct Flow Path 2-60 When reading from memory, the two chips first need to detect for an error. Figure 4b shows the flow path through the chips. L is set to normal write mode and H to normal read mode. Memory data is supplied to both chips so that L generates six check bits from the lower word data bits, and feeds them to SIL of H, the same as for writing. H also generates its own check bits which combine with those from L, and these seven composite check bits are compared with the seven memory check bits fed into CIL of H. This combining, plus comparison of check bits, is equivalent to seven 3input Exclusive-OR gates. The output of these Exclusive-OR gates are the seven syndrome bits, and these can be decoded to determine the type of error. First, if there is no error, error flag AE of H will remain inactive because memory data is correct, provided OLE is kept low, and DOL of both Land H will contain correct data. Second, if there is a memory check bit error, only one of the seven syndromes will go high and the three error flags of H will indicate a check bit error as in Table III. Note that memory data is still correct, and with OLE low, DOL of both Land H contain correct data. Third, if there is a single data error in bits 1631, the syndromes of H are such that the data error locator will locate the error and correct it, so again DOL of both L and H contain correct data. This is because the seventh syndrome bit is low for an error in the higher word, so that we have a six syndrome bit word as in Table I, to be decoded as normal to correct the error. In each of these three cases, DOL of both Land H contained correct data, and the common condition for these is either that AE(H) is "0", or E1(H) is "1". data error in bits 0-15, AE(H) is a "1", E1(H) a "1", and EO (H) a "0", but L does not have sufficient information to locate the error. It is first necessary to feed back the partially generated syndromes of H back to L, and this is achieved by reversing the direction of the common bus. First L is placed in normal read mode so that L's generated check bits become disabled. Next, the partial syndromes in Hare enabled onto the bus by setting OES of H low, so that its syndrome I/O port outputs the combined Exclusive-OR of CG(H) and CIL(H), which is transferred to CIL of L. These partial syndromes then combine with CG(L) to generate valid syndrome bits in L, demonstrated by the flow path of Figure 4c. If there is, in fact, a data bit error in bits 0-15, the seventh syndrome bit will go low, allowing the remaining six bits to be decoded to locate the error as per the columns of Table II. This switching around of the common bus, therefore, takes more time to correct the error in L, equivalent to a total time of approximately 100 ns. The fifth kind of error is identified as a double error. In this case, the error flags indicate the double error and the system can take the necessary action. A logical approach when using two DP8400s would be to first see if there is any need to reverse the common bus by monitoring AE(H), and when it is low, to output directly from DOL of both chips by setting 0B5 and 081 of each low. The System Data Valid flag should be set active at this time. If the AE(H) output is high and the error flags do not indicate a double error, then the common bus should be switched around and the System Data Valid signal set true. If the error is a double error, the user may utilize a number of alternatives, including the Double Complement Correct method. The fourth case is more complex. In the previous three cases, correct data has been available in both DOL about 50 ns after memory data became valid. Now with a single ® DC CORRECTED DATA (HIGHER WORD) DATA BIT IN ERROR CGL SIL PARTIAL SYNDROMES 3 ERR FLAGS TL/F/5032-7 FIGURE 4b. E2C2 32-81t Configuration, Detect Flow Path 2-61 TABLE I. Data In to Check Bit Generate, or Data Bit Error to Syndrome-Generate Matrix (16-Blt Configuration) 0 1 2 3 4 5 6 GENERATE CHECK BITS GENERATED SYNDROMES 0 1 2 3 4 5 0 0 1 0 0 0 0 4 3 8 3 1 0 0 1 0 9 2 1 0 1 0 0 0 0 0 7 0 5 2 1 0 0 0 7 8 9 1 0 1 0 0 1 0 1 0 0 1 0 0 0 0 0 0 1 5 DQO-15 o o 0 1 0 0 0 1 1 234 0 3 9 E B D 3 3 2 1 3 0 0 1 HEXADECIMAL EQUIVALENT OF SYNDROME BITS o 0 1 1 0 2" 3· 4 5 F 2 F 0 0 0 1 C 2 7 3 GENERATED CHECK BITS 'C2, C3 generate odd parity. o 0 "2 SYNDROMES '3 4 5 6 TABLE II. Data Bit Error to Syndrome-Generate Matrix (32-Bit Configuration) L H 1 1 1 1 1 1 1 1 122 2 2 2 222 2 233 1 2345678 9 0 2 345 6 7 8 901 2 3 4 567 8 901 DQO-31 00111111011 0 000 1 001 0 1 0 1 0 100 1 1 000 1 0 1 0 1 o1 1 0 0 0 0 1 1 1 1 0 1 0 0001001011011011 1110111010001110 0000000000000000 0 100001 110101 5 6 3 1 1 000 1 0 1 0 o 1 0 1 0 1 1 101 1 101 000 1 1 1 0 00000000000000 o 0 1000101 00101 0 1 0011000 o10 1 1 1 1 001 111 1 101 1 1 0 1 1 1 4 2 0 48975139EBD3C7FF 3320232130012321 2AA12238B981A3B9 3146654534652767 0 GENERATED CHECK BITS HEX 'CG2, CG3 generate odd parity. PROCESSOR OATA C0 H OLE WRITE OATA ® OLE M E M 0 OLE R Y PARTIAL CBs (CGl) Sil CW CW 0 WRITE CHECK BITS X DES TL/F/5032-8 FIGURE 4c. E2C2 32-Blt Configuration, Write Flow Path 2-62 TABLE III. Error Flags After Normal Read (32-Bit Configuration) »z I Co) o en EO(L)* Error Type AE(H) E1 (H) EO(H) 0 0 0 0 No Error 0 0 Single check bit error 0 Single data bit error (H) 0 0 0 Single data bit error (L) 0 Double bit error Invalid conditions All Others *EO (L) is valid after transfer of partial syndromes from higher to lower. This approach to wider data width error detection and cor· rection is termed the cascade configuration, and it requires only the one additional DP8400. The cascade approach can be used with up to five DP8400s controlling 80 data bits. The advantage is that only one additional DP8400 is required per 16 data bits, although write and read times become progressively slower as the number of DP8400s is increased. This is because of the time taken for the generated check bits to ripple through from the lowest to highest chips when writing and detecting, and then ripple back the other way for correcting. In many memory systems, speed is of utmost importance and for faster systems, it is possible to connect the DP8400s in a parallel configuration using additional IGs. Application Note AN-308 describes this approach in detail. the DP8400 will perform a normal read operation as if it were reading memory check bits. The results of this simulated read may be checked by enabling DOL to see if an error (if inserted) was corrected. Or as a further check, by entering mode 6, the predicted generated syndromes and error flags may be checked. Second, also while in mode 2, the simulated check bits appear at the cheCk bit port (from the data bus higher byte) available to be written to the check bit portion of memory as shown in Figure 4c. OLE is set high before the original simulated check bits are removed and then memory data is subsequently placed on the data bus. A write to memory will now write known data and simulated check bits to the selected location. By writing known data to the memory check bits in mode 2, and then reading the memory check bits in mode 6, each check bit in each location can be validated. Third, it is possible in mode 2 with DES low to transfer data from the higher byte to the syndrome 110 port, also shown in Figure 5c. But first the generated check bits must be all low. This is attained by previously loading all "1 "s into OIL in an earlier cycle. This is useful when using an error logger in conjunction with the DP8400 to feed the syndrome word into the logger whenever an error occurs. The user may, therefore, select one of these approaches (or a combination of both) for systems using memory data widths of more than 16 bits. DIAGNOSTIC CAPABILITIES OF THE DP8400 The DP8400 has been designed with system fault diagnois in mind. In fact, it is possible under microprocessor control with the DP8400 in site on the memory board to fully test every gate inside the DP8400 activated in normal operation, and also to diagnose all memory check bits. The DP8400 has two main diagnostic modes-modes 2 and 6. In other words, with M1 set high and MO set low, information can be written to or read from the chip. ERROR LOGGING WITH SYNDROME INJECTION CAPABILITY An important application of the dedicated syndrome 110 port is for error logging. This is because the internally generated syndromes derived during reading are available on this port, provided DES is set low. These syndromes indicate the exact location of a single error, whether it is in the data bits or check bits; they are therefore useful to be stored for error logging. Every time an error occurs when indicated by error flag AE, the syndromes corresponding to this error can be logged. Mode 6 allows the memory check bits to be read onto the higher byte bits 8-14, and syndromes to be read on the lower byte bits 0-6, as shown in Figure 5a. The remaining two bits, 7 and 15, are the error flags E1 and EO that were valid when mode 6 was entered. The syndrome bits will be the internally generated syndromes if DES is low (mode 6A), or external syndromes input on the syndrome 110 port if DES is high (mode 6B). The external syndromes could be obtained from an error loggerlsyndrome injector unit-this is an error logger with the capability of injecting syndromes back to the DP8400. Therefore, by being able to read the externally stored syndromes, the microprocessor can monitor or store the syndromes whenever needed. The syndrome word can be fed from SOL via the Syndrome Output Buffer onto the external syndrome bus. An Error Logger connected to this bus, as shown in Figure 6, will store the syndrome word in the same location as the corresponding address of each error that ocurs. An intelligent error logger will differentiate between new errors and ones that have occurred previously, by logging only new errors and ignoring ones that have already occurred. An easy way to determine this would be to compare the incoming memory address with the address of errors contained in the logger. If a match is not found and an error occurs, the new address and corresponding syndromes are logged. If a match is found, then whether an error occurs or not, Mode 2 transfers system data from the higher byte into GIL, instead of OIL, to simulate check bits. This can be used in three ways. First, as shown in Figure 5b, the simulated check bits can be latched in GIL by taking GSLE low. If the DP8400 is now set to normal read, mode 4, and new data is presented then, provided OLE is high and GSLE is kept low, 2-63 ! I Z cc no further action is necessary. Tag bits may be provided to indicate whether the error is hard or soft. Now that the error logger contains error information, it is necessary for the microprocessor to retrieve it. The OP8400 makes this easy, because the external syndrome bus data can be transferred to the data bus as described for operation in mode 6. If the error logger is made capable of outputting stored syndromes, and subsequently outputting the corresponding address one byte at a time, then all the relevant information can be retrieved by the microprocessor. The user may choose to store this in nonvolatile memory in the event of a power failure. When power returns, it will be desirable to restore this information back to the error logger, and this can be achieved by first loading OIL with all "1 "s to create all generated check bits low. Now the addresses and syndromes can be loaded from the higher byte of the microprocessor through the syndrome I/O port one byte at a time, with DP8400 in mode 2, to the error logger. For example, if an error has already been logged at a particular address and that address is re·written to, then if the error repeats subsequently, it is a hard error, and if not, it is a soft error. So, if a tag bit is set when a write occurs to a previously logged address and a subsequent error is detected at that address, a second tag bit is set indicating a hard error. A better approach would be to have the OP8400 correct and rewrite to the same location all in the same cycle, as soon as a single error is detected. The first error detected in a location is classified as a soft error until it recurs, and if an error does recur, a tag bit is set to indicate a hard error. It is assumed here that multiple soft errors will not occur in the same location. SYSTEM ~ [ MEMORY 7,8 OP8400 TL/F/5032-9 FIGURE Sa. Read Internal Generated Syndromes and Check Bit Port (Mode 6A) or Read Syndrome Port and Check Bit Port (Mode 6B) HIGHER BYTE DATA SIMULATED CHECK BITS SYSTEM MONITOR ERROR FLAGS TL/F/S032-10 FIGURE 5b. Diagnostic Read - Compare Simulated Check Bits with Check Bits Generated from Data Stored In Previous Cycle 2-64 HIBHER BYTE DATA ~ SYSTEM 7,Bf B-15 DQ ~!?l' MEMDRY ALL'D' U----, CB "-.Ir C~ DPB4DO TL/F/5032-11 1) DIAGNOSTIC WRITE: WRITE HIGHER DATA BYTE TO CHECK BIT BUS (MODE 2) 2) TRANSFER HIGHER DATA BYTE TO SYNDROME BUS (MODE 2, PREVIOUS CYCLE LATCHED ALL '1'. IN DIL TO MAKE CG = 0) FIGURE 5c. DP8400: Mode 2 ADDRESS BUS DATA BUS DATA 16.32, 64 S Y S T E M ADDRESS TAB T SYM SYNDROMES 16 1 6,7, B E'C' DPB4DD CHECK BITS M E M D R Y 6,7, B 1 -20 --+I"2~-B-1 ERROR LOGBER TL/F/5032-12 FIGURE 6. Error Logger Connected to DP8400 Syndrome Port CORRECTING DOUBLE ERRORS USING THE ERROR LOGGER ANY DOUBLE ERROR CORRECTION USING THE DOUBLE SYNDROME DECODE APPROACH It is possible to take the error logging function one stage further. As described so far, the error logger has been storing single errors (data bit or check bit). What if a double error is detected? If it is detected without any previous history at that address. one solution would be to perform a Double Complement to attempt to correct both errors. If this is not done, no useful information can be obtained. If both errors are corrected, the error logger records the syndromes of both, and tags whether they were both hard, or one hard and one soft. But, if there is a previous history at this address of a single error, then it is fair to assume that the second error has subsequently occurred. In this case, if the error logger could be made to inject the syndromes of the first error into the DP8400, the DP8400 would correct this error so that its DOL would then contain data with one error (if both errors are data bit errors). It is necessary at this point to wrap-around DOL back to DIL and allow the DP8400 to correct the second error. This approach is much faster than the Double Complement approach and at the same time offers full error logging capability. The data sheet shows how the DP8400 can perform double error correction using the Double Complement Approach, provided at least one of the errors was hard. For very large memories, this may not be adequate, as some systems will require total double error correction capability-quickly, without having to wait two additional memory cycles. Some of these systems will also require triple error detect capability. Fortunately, the matrix of the DP8400 has been configured to allow both of these capabilities. Most modern error detection/ correction matrices use a modified version of Hamming's original code. The Hamming code allows single errors to be corrected, however, two errors may not be detected as such. For 16 data bits, five check bits are required. Modified Hamming codes allow double error detect capability, as well, by arranging that the Exclusive-OR of the syndrome words of any two bits in error produces an even parity syndrome word. A parity check on the syndrome bus will, therefore, indicate two errors (or no error, but in this case, the Any Error flag will be inactive). For 16 data bits, six check bits are required for single/double error detect and single error correction capabilities. 2-65 !Z• :::J a. IIEMORYCIIECII MEMORY CIIECII BITS BIT CLEAR 8 't - I ,1>0 .ICIN0-7 74S2AO ......m o... o o... ... CD o·a :::J '§ FIGURE 3. E2C2 Simplified Block Diagram64-Bit Parallel Expansion, Error Determination and Correction .... a TLlF/5039-3 :::J 1 Mel 1 ~ .Cl2 II li MCl3 ..... 1 ~ 2 74Al.S273 IIEIIOIIY CHEal lIT ClEII IJ 3 • ea. .ea 5 M£IIOIIYCHBII:mour Y CHE.. Bn OUTPUT BUS ClOUT ...1 ~ • =0:f:) • CD 1 ."1 ~ ....CD I» COMPOSITE CHECK lIT IUS ~I .0 ~ 141210 ra~~~ rara74$288 I\) .:.. '" ~ 141210 = CCOM.3 I I I I- 0 2 I :s • ClII"'1 IIYEIMII 14S30 14$280 CST DO~15 D16-31 SYSTEII DArA IUS 832-41 ~ -- ... IIIUT ..... ~ ~ 141m ~ - ~~ ....... 1JU..&3 l. DO 8-15 r-t $0-1 r+ mlIP ocd 0..... 0 M2 M1 C0-7 "" NO It!::: - JJ_f DD 8-15 ~ SB-7 DGIM5 DPIMOII DES XP CO-l 1 1112 M1" ocefttt r-t 50-1 ~m n~ ...... DGD-15 CO·l 2 lIP 1112 ., t t tl --1. 1110 •• ~:3 - ~m 3 1112 . , III. Nct J Lt 10-1 lIP - COMPOSITE S.,....E BUS (ca-1) &0-1 -- .... 0 .... -o-· C () I .~ 5 m .... CD CD :: ~~ ~ WWIE_1EfEtT ~~~~~~~#2" ~ f---i I CCOM.' I 1 . . . . COMIUIIEIITBI ~ CHRIC BIT IUS 0 ~ CCOM , • ~ I CCOM"5"~"~'~2LtJ·,~~0~~ CCOM.l ~ CD () aI 5 Mel' 0 CUE 111£ ~ » ~ Q. ........m ....0 0 au ........0 CD DI1 () o· ----., ~ '0 0 •• •• :::> g: c CD .s ~ liB PARTiAL CHECK BIT BUS TUF/5039-4 FIGURE 4. E2C2 64-Bit Parallel Expansion, Detailed Block Diagram SOt-NY II !. Z CC Check Bit Generation, Error Detection And Error Correction CS2 CS7 CS7 CS6 CS' CS3 CS1 CS2 C(3)0 C(3)1 C(3)2 C(3)3 C(3)4 C(3)5 C(3)6 e(3)7 C(2)0 C(2)1 C(2)2 C(2)3 e(2)' e(2)5 e(2)6 e(2)7 eS2 CSO 12 CCOMP 0 74S280 C(0)1C(1)5C(2)3C(3)5 13 12 11 10 9 eCOMP' 74S280 C(1)0 C(l)l C(1)2 C(1)3 e(l)' C(1)5 C(1)6 C(1)7 CS6 CSO C(O)O C(O)l C(0)2 C(0)3 C(O)' C(0)5 C(0)6 C(0)7 13 12 11 10 (Continued) CCOMP 1 74S280 13 12 11 10 9 CCOMP2 74S280 748280 12 11 10 CCOMP 3 74S280 13 CCOMP 5 13 12 11 10 eeOMP 5 74S280 13 12 11 10 CCOMP7 74S280 TL/F/5039-5 FIGURE 5. E2C2 64-Bit Parallel Expansion 2-74 Check Bit Generation, Error Detection And Error Correction (Continued) OB1 of all four DP8400s go low. Devices 0, 1, and 3 all output the same data they received from memory. Only device 2 changes its (erroneous) data. Refer to Figure 6 below for the timing diagrams of a memory write and memory read cycle (detect then correct). The composite syndrome 11010000 is that of the error location 35. Since the syndrome is unique and fed reordered to each DP8400, only device 2 will recognize this syndrome pattern and complement its data bit 3. Then the corrected data can be output to the system data bus when OBO and MODE SVSTEM DATA ENABLE -~ -I - ~I II (NORMAL WRITE) I II (NOIIMALWRITEl 1B »z • w c OCI I - i>--- 'i L I I I I I I I I 080,081 DLE ~ Ii-- I CSLE I -C I DATA BUS - '- _. "( - ~ COMPOSlTE CB BUS COMPOSITE SYNIIRDMEBUS " IIP840Il'S'AE,ECI,El ~. -\ -J.. 2 I - ~ I I I I ~I I -t I I -~ I I I I I I MEMORY CHECK 81T OUT MEMORY CHECK BIT CLEAR I ! I I II II I I l'\ SYSTEM DATA I II ~ • \. COMPOSITE CBTOMEMOAY I I , ? '? ~m• • • • • • • • • • • • • 1 • FIGURE 6A. E2C2 64-Bit Parallel Expansion Memory Write Cycle ... - ~ I ) CPU Clock Frequency r< PtlOGRAM 1 DP8430D f-+RFCK tI:::;l< : A DM74lS168 fl.>--'" D CE -,[~ - CLOCK~)-~--------------------b -...... ~- TL/F/5001-4 TL/F/5001-3 Period of RFCK 2 = program A X program B FfI'eR Is low for 20x program 1 clocks Period of RFCK - 2x program Input FIGURE 2a. Expansion of Clock Divisor by 2x Maximum period of RFCK is 4096 clocks F!GURE 2b. Typical ExpansIon for ihe DP84300 3-6 Functional Description (Continued) DATA MEMORY CPU CLOCK >---...- - - - -..... TLlF/5001-S FIGURE 3a. Dynamic Memory System Using DP84300 DATA ADDRESS 1 t ~ 8D8ti CPU DP84300 A /\ I I ~ DP84432 ~ CLOCK , ...... --- --+ DP8408A MEMORY TL/F/5001-6 FIGURE 3b. 8086 System Using Dynamic RAMs DP8408A, DP84300, and DP84432 CE RFCK OM74LS74 OP84300 CLOCK OP84300 r .... J -"1r----t----I~CL;!!OCS!lK___ CLOCK >-...--t----t----I~CL;!!O£!CK~_.J TL/F/S001-8 TL/F/S001-7 FIGURE 4b. Circuit for Extending RFCK High by 2x FIGURE 4a. Circuit for Extending RFCK Low to 40 Clocks 3·7 • ~ "IiI' f Q Timing Diagrams Refresh Timer Outputs - - - - - - 20CLOCKS-----_·I_N-20CLOCKS_\ JlJ1I1. 1.....__- RFCK QG \ OF \ iff \ \ iili \ '---____---1 \ \.--_s-L -u-L I DC asJ QA J n Io.....--'--_ _ TL/F/5001-9 REFRESH REQUEST (RFRQ) Output Timing RFCK REFRESH RESETS IWIill \"'_ _ _ _ __ 7 ~ TL/F/5001-10 3-8 ,-------------------------------------------------------------------,0 "tJ ..,. ~National (II) Co) ~ Semiconductor N N DP84322 Dynamic RAM Controller Interface Circuit for the 68000 CPU General Description Features The DP84322 dynamic RAM controller interface is a Programmable Array Logic (PAL ®) device which allows for easy interface between the DP8409A, 17, 18, 19, 28, 29 dynamic RAM Controllers and the 68000/008/010 microprocessors. • Provides 3-chip solution for the 68000 CPU and dynamic RAM interface (DP84300, DP84322, & DP8409A) • Works with all 68000 speed versions • Possibility of operation at 8 MHz with no wait states • Performs hidden refresh • DTACK is automatically inserted for both memory access and memory refresh • Performs forced refresh using typically 4 CPU clocks • Standard National Semiconductor PAL part (DMPAL 16R4) • PAL logic equations can be modified by the user for his specific application and programmed into any of the PAL in the National Semiconductor PAL family, including the new high speed PALs. The DP84322 supplies all the control signals needed to perform memory read, write and refresh. Logic is included for inserting a wait state when using fast CPUs. Connection and Block Diagrams Dual-In-Line Package CLOCK- 1 U 20 t-Vcc AS- 2 19 t-RASIN UDS- 3 18 t - DTACK LDS- 4 17 t - iiFSif R/W- 5 16 t-NC RFRQ- 6 15 t-NC CAS- 7 14t-NC CS- 8 13t-CASU WAIT- 9 121-- CASL 111-iiE GND- 10 TL/F/S003-1 Top View Order Number DP84322J or DP84322N See NS Package Number J20A or N20A A-s-_P---.... RASIN GENERATOR RASIN ill --1H--.....~1 CAS iiiiS _.Hf-....-+.... GENERATOR CASL --...... CAS-HH.......-+.... CASU CS __~_+_T~-----__, R/W _.Hf----+I WAIT -1---1----.... DTACK GENERATOR ~>--.DTACK REFRESH I ACCESS 1-_ _ _-+ M2 (RFSH) ' - - - - - - - 1 ARBITRATION LOGIC RFRQ-----+I TL/F/S003-2 3-9 • Recommended Operating Conditions (Commercial) If Military/Aerospace specified devices are required, please contact the National SemiConductor Sales Office/Distributors for availability and specifications. Min Typ Max Units 4.75 5.00 5.25 V Vee, Supply Voltage -3.2 mA 10H, High Level Output Current 24 mA 10L' Low Level Output Current (Note 2) Min TA, Operating Free Air Temperature Typ 0 Max Units 75 ·C Electrical Characteristics over recommended operating temperature range Symbol Parameter Conditions Min VIH High Level Input Voltage VIL Low Level Input Voltage Vie Input Clamp Voltage Vee = Min, II = -18 mA VOH High Level Output Voltage Vee = Min, VIH = 2V, VIL = 0.8V, 10H = Max VOL Low Level Output Voltage Vee = Min. VIH = 2V, VIL = 0.8V, IOL = Max 10ZH Off-State Output Current High Level Voltage Applied Vee = Max, VIH = 2V, Va = 2.4V, VIL = 0.8V 10ZL Off-State Output Current Low Level Voltage Applied Vee = Max, VIH = 2V, Va = 0.4V, VIL = 0.8V II Input Current at Maximum Input Voltage Vee = Max, VI = 5.5V IIH High Level Input Current IlL Low Level Input Current los Short Circuit Output Current Vee = Max lee Supply Current Vee = Max Typ Max 2 Units V 0.8 V -1.5 V V 2.4 0.5 V 100 IJA -100 /LA 1.0 mA Vee = Max, VI = 2.4V 25 Vee = Max, VI = 0.4V -250 IJA IJA -130 mA 225(1) mA -30 150 Switching Characteristics over recommended ranges of temperature and Vee (Note 3) Symbol Commercial TA = OOCto +75"C Vee = 5.0V ±5% Test Conditions RL = 6670 Parameter Typ Max 15 25 ns 10 15 ns 10 20 ns CL = 5pF 11 20 ns CL = 50pF 10 25 ns CL=5pF 13 25 ns Min tpD Input to Output tpD Clock to Output tpzx Pin 11 to Output Enable tpxz Pin 11 to Output Disable tpzx Input to Output Enable CL = 50pF tpxz Input to Output Disable tw Width of Clock tsu Set-UpTime th Hold Time Note 1: Icc Note 2: Nole 3: I I Units High 15 ns Low 15 ns 25 0 = max at minimum temperature. One output at a time; otherwise 16 rnA. "a PAL 16R4B PAL is used. the Switching Characteristics will improve ccrrespondingly. 3-10 ns -10 ns C "V System Block Diagram CD ~ DP84322 and DP8409A for 68000 CPU .... ADDRESS BUS '" 1 I ::! - ADDRESS DECDDER L- AS ,....-- DM74LS393 DTACK ... OD-6. 7. 8 WE t-- 10 MHz MAX CLK '" we r+ -* RAS1 DP8409A DoUT WE DoUT * RAS2* r+ ~ AS ~ R/W ifIlS LDS 00-D15 t UOS - LOS I : M2(RFSH) 0 - M1 1 - MO 0P84322 RFRO OTACK _WAIT CASU 4 r-+ DoUT r-+ ~. +- DoUT ~ AD-6. 7. 8 RAS CASU CASL r--- CAS f""DE * RAS3* I+- liAS CASU CASL RASIN r-+ ~.~ AO-6. 7. 8 WE RASIN RFSH 0,. AO-S. 7. 8 RAS CASU CASL RFCK WIN cs ~.~ AO-S. 7. 8 CASU CASL ADS RGCK R/W N N RAS CD-So 7. 8 BO B1 cs r+ ... * -* RASD RO-6. 7. 8 Vce A1-A23 68000 Co) RFRO WE CAS :I CASL DP84244 DRAMs 8UFFER NECESSARY IF MORE THAN ONE BANK -These outputs may need resistors. DATA BUS .,. TL/F/S003-3 Mnemonic Description INPUT SIGNALS OUTPUT SIGNALS The clock signal determines the timing of the outputs and should be connected directly to the 68000 clock input. Address Strobe from the 68000 CPU. This input is used to generate RASIN to the DP8409A. UDS, LDS Upper and lower data strobe from the 68000 CPU. These inputs, together with AS, R/W, provide DTACK to the 68000. R/W Read/write from the 68000 CPU, when WAIT = O. Selects processor speed when WAIT = 1 ("1" = 4 to 6 MHz, "0" = 8 MHz). Column Address Strobe from the DP8409A. This input, together with LDS and UDS, provides two separate CAS outputs for accessing upper and lower memory data bytes. Chip Select. This input enables DTACK output. CS = 0, DTACK output is enabled; CS = 1, DTACK output is TRI-STATE®. Refresh Request. This input requests the DP84322 for a forced refresh. This input allows the necessary wait state to be WAIT inserted for memory access cycles. CLOCK CASU, CASL DTACK 3-11 This output provides a memory cycle start signal to the DP8409A and provides RAS timing during hidden refresh. These signals are the separate CAS outputs needed for byte writing. This output is used to insert wait states into the 68000 memory cycles when selected and during a forced refresh cycle where the CPU attempts to access the memory. This output is enabled when CS input is low and at TRISTATE when CS is high. This output controls the mode of the DP8409A. It always goes low for 4 CPU clock periods when AS is inactive and a forced refresh is requested through RFRQ input. This allows the DP8409A to perform an automatic forced refresh. II Functional Description WAIT input should be set low for 6 MHz or less allowing full speed of operation with no wait states. Data Transfer Acknowledge input (~ of the 68000 at these speeds is automatically inserted during S2 for every memory transaction cycle and is then negated at the end of that cycle when iJDS and/or 05S go high. For the 8 MHz 68000 however, a wait state is required for every memory transaction cycle. At these speeds, the WAIT input is set high, selecting the DP8409A's CAS output to generate DTACK and again DTACK is negated at the end of the cycle when UDS or LOS goes high. Note that DTACK output is enabled only when the DP8409A's CS is low. Therefore when the 68000 is accessing I/O or ROM (in other words, when the DP8409A is not selected), the DP84322's l5'fACK output goes high impedance logic '1' through the external pull-up resistor and it is now up to the designer to supply DTACK for a proper bus cycle. The following table indicates the maximum memory speed in terms of the DRAM timing parameters: !cAC (access-time from CAS) and tRP (RAS precharge time) required by different 68000 speed versions: MEMORY ACCESS As a 68000 bus cycle begins, a valid address is output on the address bus A 1-A23. This address is decoded to provide Chip Select (CS) to the DP8409A. After the address becomes valid, AS goes low and it is used to set RASIN low from the DP84322 interface circuit. Note that CS must go low for a minimum of 10 ns before the assertion of RASIN for a proper memory access. As an example, with a 8 MHz 68000, the address is valid for at least 30 ns before AS goes active. AS then has to ripple through the DP84322 to produce RASIN. This means the address is valid for a minimum of 40 ns before RASIN goes low, and the decoding of ~ should take less than 30 ns. At this speed the DM74LS138 or DM74LS139 decoders can be selected to guarantee the 10 ns minimum required by ~ set-up time gOing low before the access RASIN goes low (tcsRl of the DP8409A). This is important because a false hidden refresh may take place when the minimum tCSRl is not met. Typically ~ occurs at the end of S2. Subsequently, selected RAS output, row to column select and then CAS will automatically follow RASIN as determined by mode 5 of the DP8409A. Mode 5 guarantees a 30 ns minimum for row address hold time (tRAH) and a minimum of 8 ns column address set-up time (tASel. If the system requires instructions that use byte writing, then CASU and CASL are needed for accessing upper and lower memory data bytes, and they are provided by the DP84322. In the DP84322, [jjS and UDS are gated with CAS from the DP8409A to provide CASL and CASU, therefore designers need not be concerned about delaying CAS during write cycles to assure valid data being written into memory. The 8 MHz 68000 specifies during a write cycle that data output is valid for a minimum of 30 ns before OS goes active. Thus, CASL and CASU will not go low for at least 40 ns after the output data becomes stable, guaranteeing the 68000 valid data is written to memory. Microprocessor Clock 8MHz 6MHz 4MHz Maximum tCAC 125 ns 90 ns 270ns Minimum tRP 140 ns 170ns 280ns Minimum tRAS 220ns 290ns 450ns Pin 5 (R/W input to the DP84322) is not used as R/W when the WAIT input is high. Therefore, when WAIT is high and pin 5 is low, this is configured for the 8 MHz 68000. The dynamic RAM controller in this configuration operates in mode 5 and mode 1. When both WAIT and pin 5 are high, this is configured for 4 MHz and 6 MHz 68000, allowing only two microprocessor clocks for memory refresh. Furthermore, the designer can use the DP8408A because the dynamic RAM controller now operates in mode 0 and mode 5 or mode 6. In addition, the programmable refresh timer, DP84300, should be used to determine the refresh rate (RFCK) and to provide the refresh request (AFRO) input to the DP84322. The refresh timer can provide over two hundred different divisors. RFRO is given at the beginning of every RFCK cycle and remains active until M2 goes low for memory refresh. The DP84322 samples RFRQ when AS is high, then sets M2 low for two microprocessor clocks, taking the DP8408A or DP8409A to the external control refresh mode. RASiN for this refresh is also issued by the DP84322. If a memory access is pending, RASIN for this access will not be given until it is delayed for approximately one microprocessor clock, allowing RAS precharge time for the dynamic RAMs. The following table indicates different memory speeds in terms of the DRAM parameters required by 4 MHz and 6 MHz 68000: Furthermore, the gating of UDS, [jjS and CAS allows the DP84322 interface controller to support the test and set instruction (TAS). The 68000 utilizes the read-modify-write cycle to execute this instruction. The TAS instruction provides a method of communication between processors in a multiple processor system. Because of the nature of this instruction, in the 68000, this cycle is indivisible and the Address Strobe AS is asserted throughout the entire cycle, however OS is asserted twice for two accesses: a read then a write. The dynamic RAM controller and the DP84322 respond to this read-modily-write instruction as follows (refer to the TAS instruction timing diagram for clarification). First, the selected RAS goes low as a result of AS going low, and this RAS output will remain low throughout the entire cycle. Then the DP84322's selected CAS output (CASL or CASU) goes low to read the specified data byte. After this read, OS goes high causing the selected CAS to go high. A few clocks later R/W goes low and then OS is reasserted. As OS goes low, the selected CAS goes low strobing the CPU's modified data into memory, after which the cycle is ended when AS goes high. The two CAS outputs from the DP84322, however, can only drive one memory bank. For additional driving capability, a memory driver such as the DP84244 should be added to drive loads of up to 500 pF. Microprocessor Maximum Minimum Minimum Minimum Clock tCAC tRAS tRP tRAH 4 MHz 290 ns 200 ns 225 ns 20 ns 6MHz HOns 125ns 140ns 20ns DP8408A, DP8409A operate in mode 6 and mode O. Since this DP84322 interface circuit is designed to operate with all of the 68000 speed versions, a status input called WAIT is used to distinguish the 8 MHz from the others. The 3-12 Functional Description (Continued) When WAIT = 1, pin 5 = 0 (8 MHz), the PAL controller supports read and write cycles with one inserted wait state, forced refresh with five wait states inserted if CS is valid, an:] hidden refresh. This PAL mode does not support the T AS instruction. When WAIT = pin 5 = 1 (4-6 MHz), the PAL controller supports read and write cycles with no wait states inserted, and forced refresh with two wait states inserted if CS is valid. This PAL mode does not support the TAS instruction and only supports hidden refresh when used in mode 5 with the DP8409A controller. chip select is inactive because the microprocessor is accessing elsewhere, all four RAS outputs follow RASIN, strobing the contents of the on-Chip refresh counter to every memory bank. RASIN going high terminates the hidden refresh and also increments the refresh counter, preparing it for the next refresh cycle. Once a hidden refresh has taken place, a forced refresh will not be requested by the DP8409A for the current RFCK cycle. However, if the microprocessor continuously accessed the DP8409A and memory while RFCK was high, a hidden refresh could not have taken place and now the system must force a refresh. Immediately after RFCK goes low, the Refresh Request signal (RFRO) from the DP8409A goes low, indicating a forced refresh is necessary. First, when RFRO goes low any time during S2 to S7, the controller interface circuit waits until the end of the current memory access cycle and then sets M2 (RFSH) low. This refresh takes four microprocessor clocks to complete. If the current cycle is another memory cycle, the 68000 will automatically be put in four wait states. Alternately, when RFRO goes low while AS is high during SO to S1, M2 is now set low at S2. Therefore, it requires an additional microprocessor clock for this refresh. Once the DP8409A is in mode 1 forced refresh, all the RAS outputs remain high until two RGCK trailing edges after M2 goes low, when all RAS outputs go low. This allows a minimum of one and a half clock periods of RGCK for RAS precharge time. As specified in the DP8409A data sheet, the RAS outputs remain low for two clock periods of RGCK. The refresh counter is incremented as the RAS outputs go high. Once the forced refresh has ended, M2 is brought high, the DP8409A back to mode 5 auto access. Note that RASIN for the pending access is not given until it has been delayed for a full microprocessor clock, allowing R"AS precharge time for the coming access. The DP84322 can possibly be operated at 8 MHz with no wait states (WAIT = "0") given the following conditions: FAST PAL (PAL16R4A) S2 + S3 + S4 + S5 = 250 ns RASIN delay = 60 ns (AS low max.) + 25 ns (Fast PAL delay) = 85 ns max. RASIN to CAS delay DP8409-2 = 130 ns max. External CASH,L generation using 74S02 and 74S240 7.5 ns (74S02) + 10 ns (74S240) - 7.5 ns (less load on 8409 CAS line) = 10 ns max. Transceiver delay (74LS245) = 12 ns max. 68000 data setup into S6 = 40 ns min. :. Minimum !cAe = 53 ns = 250 - 85 - 130 - 10 - 12 + 40 Minimum tRAS = 240 ns Minimum tRP = 150 ns Minimum tRAH = 20 ns REFRESH CYCLE Since the access sequence timing is automatically derived from MSiliI in mode 5, Rie and CASTN are not used and now become Refresh Clock (RFCK) and R"AS-generator clock (RGCK) respectively. The Refresh Clock RFCK may be divided down from RGCK, which is the microprocessor clock, using the DM74LS393 or DM74LS390. RFCK provides the refresh time interval and RGCK the fast clock for all-R"AS refresh if forced refreshing is necessary. The DP8409A offers both hidden refresh in mode 5 and forced refresh in mode 1 with priority placed on hidden refreshing. Assume 128 rows are to be refreshed, then a 16 IJ-s maximum clock period is needed for RFCK to distribute refreshing of all the rows over the 2 ms period. If the 68000 bus is inactive (i.e., the 68000's instruction queue is full, or the 68000 is executing internal operations such as a multiply instruction, or the 68000 is in halt state ... ) and a refresh has been requested, a refresh will also take place because R'F'RO is continuously sampled while AS is high. Therefore, refreshing under these conditions will be transparent to the microprocessor. Consequently, the system throughput is increased because the DP84322 allows refreshing while the 68000 bus is inactive. The 84322 is a standard National Semiconductor PAL part (DMPAL16R4). The user can modify the PAL equations to support his particular application. The 84322 logic equations function table (functional test), and logic diagram can be seen at the end of this data sheet. The DP8409A provides hidden refreshing in mode 5 when the refresh clock (RFCK) is high and the microprocessor is not accessing RAM. In other words, when the DP8409A's II 3-13 ~ ~ ~ System Timing Diagrams o 68000 Memory Read Cycle (Wait = 0, Pin 5 = R/W) CLOCK Al-A23 OUTPUTS FROM 68000 H ~_______________V_A_Ll_D_AO_OR_E_SS________________J)~-------- AS illiS, LOS R/W iiASiN Iiml OUTPUTS FROM OP84322 mCK CASU, CASL OUTPUTS FROM DP8409A RJiSij-RAS3 SELECTED lIAS OUTPUT 00-08 COLUMN ADDRESS CAS WE IiFiiQ tcAC-,.I____.:..._to_ffj""'___ DRAM OUTPUT ----------------------------------c( , MEMORY DATA "',YTLiF/S003-4 3-14 System Timing Diagrams (Continued) 68000 Memory Read Cycle and Forced Refresh (Wait = 0, Pin 5 (4 Wait Clock Periods Inserted for Forced Refresh) f . - - CYC~:~~~21~~~~~~T:E~~~~ ~CLE = R/W) ---+- M~~~4:;~~g~:~N~:~LE ~ CLOCK A1-A23 AS OUTPUTS FROM 68000 UOS, LOS R/W RASIN RFSH OUTPUTS FROM DP84322 OTACK CASU, CASL RASO-RAS3 00-08 OUTPUTS FROM OP8409A CAS &I WE RFRO -teAC, DRAM OUTPUT 10FF lr --------------------------'«MEMORYDAT~ TLlF/5003-5 3-15 i System Timing Diagrams (Cooti_ TAB Inltructlon Cycle (Wilt = 0, Pin 6 = RIW) CLOCK AI·A23 :::>-<. . _________ >- .AO_DR.ES••_ _ _ _ _ _ _ _ _ _ _ OUTPUTS FROM llOOD on, III R/W OUTPUTS FROM DP84322 ClIu, ClIL tuFF SELECTED lin OUTPUT . GD-QI OUTPUTS FROM DP8408A D.rr~---------< TLIFI5003-6 3-16 System Timing Diagrams (Continued) Memory Read Cycle (Walt = 1, Pin 5 = 0) CLOCK A1-A23 »)---- ~,,_ _ _ _ _ _ _ _ _ _AO_O_R_ES_S_ _ _ _ _ _ _ _ _ _ OUTPUTS FROM 68000 OUTPUTS FROM OP84322 mU,mL SELECTED RAS OUTPUT RASD-RAS3 QD-QB COLUMN ADDRESS OUTPUTS FROM OP8408A &I DRAM OUTPUT -----------------------< MEMORY DATA TL/F/5003-7 3-17 System Timing Diagrams (Continued) Memory Read Cycle and Forced Refresh (Wait = 1, Pin 5 = 0) I DP64322 DETECTS START OF - - - - - CYCLE, SO INSERTS REFRESH CYCLE - - - - - . - DP84322 CONTINUES MEMORY ACCESS CYCLE - I CLOCK AO-A15 AS OUTPUTS FROM 68000 UOS, IDs R/W RASIN 4 "p CLOCK PERIODS RFSH OUTPUTS FROM DP64322 DTACK CASU, CASL RASO-RAS3 QO-Q8 CAS OUTPUTS FROM DP8409A WE RFRQ l DRAM OUTPUT ------------------------------c< MEMORY DATA'j.TL/F/5003-8 3-18 System Timing Diagrams (Continued) 68000 Memory Read Cycle (Wait and Pin 5 ~ 1) CLOCK AO-A23 H >--C ADDRESS '------- lIS OUTPUTS FROM 68000 UliS/m R/W 1!mIi (M2)RFSH OUTPUTS FROM OP84322 llfACK CASU, CASL mO-RAS3 00-08 OUTPUTS FROM DP8408A/9A eli! WE "'~{ RFRO FROM DP84300 DATA OUT -----------------------« MEMORY DATA »----TL/F/5003-10 3-19 • System Timing Diagrams (Continued) 68000 Memory Read Cycle and Memory Refresh (Walt and Pin 5 = 1) I I 1 _ DP84322 DETECTS START OF OP84322 CONTINUES , -CYCLE, SO INSERTS REFRESH CYCLE--'~""---MEMORY ACCESS CYCLE---j· OUTPUTS FROM 68000 lltiS/tlif R/W 1ImII M2(11F1Rj OUTPUTS FROM DP84322 "DmIf WU,WL !lBO-W3 00-08 OUTPUTS FROM DP8408A/9A CAS WE" -I FROM DP84300 lIFIIlI , DATA OUT MEMORV DATA TL/F/5003-11 3-20 :s:: o n. :::;; (i" DP8408A, DP8409A and 68000 Interface AUUHt~S BUS ,. ! I ADDRESS DECODER I I I Al-A23 H r----. RO-6, 7, B 00-6,7, B ~vv " -* RASO -vv CO-6, 7, B '*. BO '----t AS . '!'A ~ WE r'" Bl ~ * r ~ 68000 DTACK ). CLI( * * HAS2 ~ AU-6, 7, 8 DiN r'" CASU CASL DoUT WE ~ CS AS HASIN RFSH .. I" ..... R/Vi UOS UDS LOS LOS OP84322 HASIN M2(RFSH) MDD;t_ Ml 50R6 -+ MO t * *'A 4 AU-6, 7, 8 DiN RAS CASU CASL CAS 00-015 RAS3 CAS ~ RFRO DTACK " 1 " _ WAIT CASU -f""OE CASL I- DoUT WE ~I 3 m 0" n H ~ ~ C iii" CO ""I I» H 3 ~ H ~ H DRAMs DP84244 BUFFER NECESSARY IF MORE THAN ONE BANK DATA BUS '< (I) RAS WIN R/Vi Dour M2 RIC r-+ Dour AD-6, 7, 8 DiN WE DP840BAI9A - ~ CD RAS CASU CASL RASI r"'Y " I , · t CASIN c.> HAS WE 'Y RFRO DP84300 AD-6, 7, B DiN CASU CASL ADS cs n. o . TIlF/5000-9 'These oulpuls may need resisIors. ~~&t8da _ iii PAL Boolean Equations PAL 16R4 DP84322 Dynamic RAM Controller Interface for the MC68000-DP8409A Memory System CK I AS IUDS ILDS R IRFRQ ICAS ICS WAIT GND IOE ICL ICU IC 18 I A IRFSH IDTACK IRASIN VCC IF (VCC) RASIN = AS. IRFSH • I A + RFSH. R • A. WAIT IF (CS) DTACK = IR. CAS. WAIT + UDS. IA. 18. IWAIT + LOS. IA. 18. IWAIT + AS. IR. IA. 18. IWAIT • IRFSH • R • I A • 18 • WAIT RFSH: = I AS. RFRQ + RFSH. IR • IC. WAIT + RFSH. R • I A. WAIT + RFSH. IC. IWAIT + AS = RFSH =A C: = 8 A: 8: IF (VCC) CU = UDS. CDS IF (VCC) CL = LOS. CAS Function Table CK C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C AS UOS LOS R RFRQ CAS CS WAIT OE CL CU C B A RFSH OTACK RASIN H H H H H L L L L L H H H L L L L L L L L L H H L L H H L H H H H H H H H H H H H L L L L L H H H H L L L H H L L H L H H H H H H H H H L L L L L L H H H L L L L L H H H H H H H H H H H H H H H H H L L L L L L L L L L L L L L L L L L L L L H H H H H H H H H H H H H H H H H H L L H H H H H H H L L H H H H H H H L L H H H H H H L L L H H L L L L H H H H H H H L L L H H H H H H L L H H H H H L L H H H H H H L L L L L L L L L L L L L L L L L L L L L L L H L L L L L L L L L L L L L L L L L L L L L L L L L L L H H H H H L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L H H L H L H H H H H H H H H H H H H L L H L L H H H L H H L H H H H H H H H H X X X X X X X X X X X X X X X X X X X X H H H H H H H H H H L L L L H H H H H L L L L H H H H H L H H H H H H H H H L L L L H H H H H L L L L H H H H H L L H H Z H H H H H H H H L L L L H H H H H L L L L H H H H H H H L L L L H H H H H L L L L H H H H H L L H H H H Z Z L L H L L H H H H H H H L L H H H H H H H L L Z H H H H L H H H H H H H L L L L L H H H H H H L L L H H H H H H L L L L L H H H H L L L H H H H H H H H H H H H H 3-22 H H H H H H H H L H H H H H H H H H H H H L H H H H H H L H H H H H L H Z H H H H H L L H H H Z H H H L L H H H L H L L H H DP84322 Logic Diagram PAL 16R4 - INPUTS (0 31) LOCK 1 0123 UI7 111011 12131415 11171811 20212223 24252127 2U93C131 0 1 2 3 >--J •• I 7 ~ 2 RASIN 19 , 8 9 10 11 12 13 :>--J " 15 OTACK 18 ..., UOS .... a---t 16 17 18 19 20 21 22 23 "" ,/ IDS ... 2 4 -"" 2' 25 21 27 28 29 ... ~ tg] ~ , ~ ~C ... tp; '" 3D 31 ... ... R/iii .... 5 Pl~ 16 32 33 34 "' 35 36 37 38 39 RFRQ ... 6 4D "4243 x •• """. / .5 .6 .7 CAS .... .... 15 r.J. NC rv'14 7 .8 '9 50 51 52 53 x 5' >-d CAsU 13 55 CS .... 8 ~r-- .... .. 56 57 58 59 60 61 62 13 >--tl WAIT ... --I 9 o1 2 3 . , t-4 5 II 7 891011 12131415 16171819 20212223 242&2627 28293031 em 12 ~ 11 TL/F/5003-12 3-23 N.-----------------------------------------------------------i ,.. :: ~National ~ ~ Semiconductor DP84412 Dynamic RAM Controller Interface Series Circuit for the Series 32000® CPU • Works with all Series 32000 family speed versions up to 10 MHz. • Operation of Series 32000 processor at 10 MHz with no WAIT states. • Controls DP8409A or DP8419 Mode 5 accesses, hidden refreshes and Mode 1 Forced Refreshes automatically. • Inserts WAIT states in READ or WRITE cycles automatically depending on whether WAITRD or WAITWR are low, or if CS becomes active during a forced Refresh cycle. • Uses a standard National Semiconductor PAL part (DMPAL 16R6A). • The PAL logiC equations can be modified by the user for his specific application and programmed into any of the PALs in the National Semiconductor family, including the new very high speed PALs ("8" PAL parts). General Description The DP84412 is a new Programmable Array Logic (PAL®) device, that replaces the DP84312, designed to allow an easy interface between the National Semiconductor Series 32000 family of processors and the National Semiconductor DP8409A, DP8429, or DP8419 DRAM controller. The new DP84412 supplies all the control signals needed to perform memory read, write and refresh and work with the National Semiconductor Series 32000 family of processors up to 10 MHz. Logic is also included to insert WAIT states, if wanted, into the microprocessor READ or WRITE cycles when using fast CPUs. Features • Provides a 3-chip solution for the Series 32000 family, dynamic RAM interface (DP8409A or DP8419, DP84412, and clock divider). Connection Diagram FCLK m RF 110 ADS DDIN WAITWR cm cs WAfflIii lIE 1m FCLK m 20 CYCLED RF 110 lIIW mrnr iimR ADS iiA'SiN iiMli! MliDE 16 2il 15 3D 14 13 4D 12 CWAff 11 DDIN WAITWR cm lIE cs 2il 3D 4D 'Ci'IAlT IlICV CYCLED iimR MliiiE 2il 3D 4D CWAii WAITRD -= lIE -= TL/F/8397-1 Order Number DP84412J or DP84412N See NS Package Number N20A or J20A 3-24 Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Operating Programming 7V 12V Supply Voltage, Vee Input Voltage 5.5V 12V Off·State Output Voltage Storage Temperature Range Operating Programming 5.5V 12V -65·C to + 150·C Recommended Operating Conditions Symbol Commercial Parameter Min Vee Supply Voltage I Max 5.25 4.75 5 Low 15 10 High 15 10 tw Width of Clock tsu Setup Time from Input or Feedback to Clock 25 16 I Units Typ V ns ns th Hold Time 0 -10 TA Operating Free·Air Temperature 0 25 Te Operating Case Temperature ns ·C 75 ·c Electrical Characteristics Over Recommended Operating Temperature Range Symbol Parameter Test Conditions Min VIH High Level Input Voltage Vil Low Level Input Voltage Vie Input Clamp Voltage Vee = Min, II = -1B mA VOH High Level Output Voltage Vee = Min Vil = O.BV VIH = 2V 10H = -3.2mA VOL Low Level Output Voltage Vee = Min Vil = O.BV VIH = 2V 10l = 24 mA COM Off·State Output Current Vee = Max Vil = O.BV VIH = 2V 10ZH 10Zl Typ Max 2 V -O.B COM 2.4 Units O.B V -1.5 V 2.B 0.5 V Vo = 2.4V 100 p.A Vo = 0.4V -100 p.A 1 mA II Maximum Input Current Vee = Max, VI = 5.5V IIH High Level Input Current Vee = Max, VI = 2.4V III Low Level Input Current Vee = Max, VI = O.4V los Output Short·Circuit Current Vee = 5V lee Supply Current Vee = Max Vo = OV 3·25 0.3 V -30 25 p.A -0.02 -0.25 mA -70 -130 mA 120 1BO mA Switching Characteristics Over Recommended Ranges of Temperature and Vee Vee = 5V ±10%. Commercial: TA = O"C to 75"C, Vee = 5V ±5% Symbol Test Conditions R1,R2 Parameter tpo Input or Feedback to Output tcLK Clock to Output or Feedback tpzx Pin 11 to Output Enable tpxz Pin 11 to Output Disable tpzx tpxz Units Typ Max 15 25 ns 10 15 ns CL=50pF 10 20 ns CL = 5pF 11 20 ns Input to Output Enable CL = 50pF 10 25 ns Input to Output Disable CL = 5pF 13 25 ns Maximum Frequency fMAX vee ~ Commercial Min 25 30 ns Max at minimum temperature. PAL For Series 32000 Family Systems ADDRESS/OATA A"- r--- 023 U ENABLE 74AS373 AD·An .f""1ll! All1l A16An 01 - (32032 OR 32018 OR 32D011 AND 32201 8 jjjjjij eTTl e\Wf FCLIC i--' .... r:: RFIIO DPM412 ~ em: M1iDE iImi Frn ilEh- Is:: .... .... 32018 \ ., DIR 'I""" 11m m ~r- CO-7, a 80.1 DilDO II'IlI! 140 0...... D ~ 11m -vn;: lIAS! 11m mm iiiiE 32018 AD 14F245 TRANSCEIVER lOW BYTE CAS RFC_ 00-7.8 Will wero HC ......... ........ MEMORY OIIDO LO 00-7.8 '-w """ om IIWE RGCK HI BANKt I~ I _.M2 CLOCK MOREISIDATA 00-7.8 - HI 01100 LO 00-7.8 ' - - ;;m '-- W IIWE IfiiE IlIlE 1 BAHK2 MEMORY I~ I IIASiN DP843DO RFCK III!IIi I~ I T RFRO *"Ml DDIR twm MEMORY ClII RWE RO·7.8 ..aVO-- W !IE.llll.: ~ e)r-- TSD C.71et! LO HI BANKO LO __ cs - ~:~~ ..... DRAMe) -"'" AD~ 1!R" m 00·7.8 ~ , .,f"" !IIml! Hl!p - .."1-21 0 748139 I I 020 A ADDRESS/DATA 8US AlL IC'S DECOUPLED • SERIES DAMPING RESISTERS ·1 TIE UNUSED ADDRESS LINES TO Vee 1 HI BANK 3 MEMORY IlIlE 01100 1- DATAIN/OUT TL/F/8397-2 3-26 r-----------------------------------------------------------------------.c Mnemonic Description Functional Description INPUTS SIGNALS The following description applies to both the DP8409A and the DP8419 dynamic RAM controllers. 1) 2) 3) 4) 5) 6) 7) 8) 9) 10) "FCLK" Fast clock from the NS32201 TCU clock chip, this signal runs at twice the speed of the system clock. From the NS32201 TCU clock chip, "TSO" this signal indicates the start of the "T2" state and goes high at the beginning of the "T4" state. RFRO (refresh request) in mode 5. "RFI/O" From 8409A, an active low signal. "ADS" From the Series 32000 CPU, address strobe. If the system includes the MMU (NS32082) then PAY should be connected to this input. "DDIN" Used to differentiate between READ and WRITE cycles, and to allow CS READ cycles to start early. "WAITWRITE" This signal is used to add a WAIT state into a CS WRITE access cycle, and delay RASIN until the end of the "T2" clock period. From the NS32201 TCU clock chip, "CTTL" this signal runs at the system clock frequency. lies" From decoder chip (chip select) (active low). "WAITREAD" Used to insert 1 wait state into the Series 32000 READ bus cycle. The wait state allows the use of memory with longer access times (leAcl. An active low Signal. This input enables the outputs of the "D-Flip Flop" outputs of the PAL. A memory cycle starts when chip select (CS) and address strobe (ADS) are true. RASIN is supplied from the DP84412 to the DP8409A dynamic RAM controller, which then supplies a RAS Signal to the selected dynamic RAM bank. After the necessary row address hold time, the DP8409A switches the address outputs to the column address. The DP8409A then supplies the required CAS signal to the DRAM. In order to do byte operations it is suggested that the user provide external logic, as shown in the system block diagram, to produce a HIGH WRITE ENABLE and/or a LOW WRITE ENABLE. To differentiate between a READ and a WRITE, the DDIN signal from the CPU is used. DDIN is also supplied to the external WRITE ENABLE logic. A refresh cycle is started by one of two conditions. The refresh cycle caused by the first condition is called a hidden refresh. This occurs when refresh clock (RFCK) is high, CS is not true, and RASIN goes true. Here the CPU is accessing something else in the system and the DRAM can be refreshed at that time, thereby being transparent to the CPU. The second type of refresh is called forced refresh. This occurs if no hidden refresh was performed while RFCK was high. When RFCK transitions Iowa refresh request (RFRO) is generated. If there is not a DRAM access in progress the DP84412 will force a refresh by putting the DP8409A into mode 1 (automatic forced refresh mode). If the CPU tries to access the DRAM during a forced refresh cycle WAIT states will be inserted into its cycles until the forced refresh is over and the DRAM RAS precharge time has been met. Then the pending DRAM access will be allowed to take place. The DP84412 also allows forced refreshes to take place during long accesses of other devices. For instance, if EEPROM takes several microseconds to write to, the DRAM will still be refreshed while that access is in progress. OUTPUTS SIGNALS 1) 2) 3) 4) "MODE" 5) "2DLY" "3DLY" "4DLY" "RASIN" 6) "CYCLED" 7) "CWAlr' 8) "INCYCLE" This pin goes to M2 on the DP8409A to change from mode 5 to mode 1 (only used for forced refresh). Delay used internal to the PAL. Delay used internal to the PAL. Delay used internal to the PAL. To the 8409A (creates RASs). Goes low earlier for READ cycles than WRITE cycles. Goes active low once a hidden refresh (non CS cycle) or DRAM access has been performed. CYCLED always goes low at the beginning of the "T3" processor state. This Signal goes high (reset) by the end of the processor bus cycle as indicated by TSO being high. This output inserts "WAIT" or "HOLD" states into the NS32016 machine cycles (only WAIT states are used in this application). This output is in "not enabled" condition when CS is high (not chip selected). This signal goes active from the CPU ADS Signal. This signal indicates that the processor is doing an access somewhere in the system. This Signal stays low for several T states of the access cycle. In a standard memory cycle, the access can be slowed down by one clock cycle to accommodate slower memories or allow time to generate parity. This is accomplished by inserting a WAIT state into the processor access cycle. The DP84412 can insert WAIT states into either READ or WRITE cycles, or both. The extra WAIT state will not appear during the hidden refresh cycle, so faster devices on the CPU bus will not be affected. System Interface Description All members of the Series 32000 family of processors are able to use the DP84412. The DP84412 differentiates between READ and WRITE cycles, allowing the RASIN signal to start earlier during a READ cycle compared to a WRITE cycle. RASIN during a READ cycle will always start at the beginning of the "T2" processor cycle. The user must also guarantee that CS is valid a minimum of 30 ns before RASIN becomes valid. The worst case would be at 10 MHz where FCLK preceeds PHI1 by a maximum of 10 ns. RASIN can occur a minimum of approximately 8 ns after FCLK. Therefore CS must occur a minimum of 32 ns (30 ns+2 ns) before the rising edge of PHI1 at 10 MHz. The user may want to tie CS low on the DP8409A119 (disable HIDDEN REFRESH) and use the system transceivers to select the DRAM. In this case one only needs to concern himself with the 10 ns address setup time to RASIN. 3-27 ;g .0- .0..... I\) .... ~ .-----------------------------------------------------------------------------~ i Q The smallest pulse widths are generated during WRITE cycles since AASiN during WRITE cycles starts later than FfASlN during READ cycles. If one inserted a WAIT state in READ cycles the DRAM column access times and the RAS pulse width would be increased by one clock period (125 ns in this case). A WAIT state in WRITE cycles would just increase the ~ pulse width by one clock period. System Interface Description (Continued) The DP84412 can be used in a system with the MMU (NS32082) but the signal PAY would be connected to the ADS input instead of AI5S. Several other critical parameters in this application that involve the input signals i5i5fiiJ', ~, is(j, and FCLK. These parameters become most critical at 10 MHz where it is suggested that they are directly connected to the corresponding pins of the Series 32000 family ICs. This section of the data sheet goes through the calculation of the "tRAC" (~ access time) and "!cAC" (CAS access time) required by the DRAM for the Series 32000 family CPUs to operate at a particular clock frequency without introducing wait states into the processor access cycles. 80th "tRAC" and "!cAC" must be considered in determining what speed DRAM can be used in a particular system design. The DRAM chosen must meet both the "tRAC" and "tCAC" parameters calculated. In order to determine the "tRAC" and "tCAC" needed the DP8419 and fast PALs ("8" type PALs) timing parameters were used. If the user is using the DP8408A109A or a slower PAL device he should substitute their respective delays into the equations below. Most all of the calculations contained in this note use "RAHS" = 1 (15 ns guaranteed minimum row address hold time). Calculations only used "RAHS" = 0 (25 ns guaranteed minimum row address hold time) when the calculated access time from RAS exceeded 200 ns. This is because DRAMs can be found with row access times up to 150 ns that require only 15 ns row address hold times. B) 10 MHz Series 32000, No Walt States #1) RASTIillow = Tl - 2 ns (FCLK - PHil skew) + 12 ns ("8" PAL clocked output) = 100 - 2 + 12 = 110 ns maximum # 2) RASIN to RAS low = 20 ns maximum #3) RASIN to CAS low = 80 ns maximum (DP8419 RASTIiI - CAS low) - 3 ns (load of 72 DRAMs instead of 88 DRAMs speced in data sheet) = 77 ns #4) 74F245 transceiver delay = 7 ns maximum #5) CPU data setup time to "T4" = data setup to PHI2 T.E. + maximum PHI2 F.E. to PHil R.E. = 15 + 5 = 15 ns minimum "tRAC"=Tl +T2+T3- #1-#2-#4- #5 = 100+ 100+ 100-110-20-7-15= 148 ns "!cAC"=Tl +T2+T3-#1- #3-#4-#5 = 100+ 100+ 100-110-77-7-15=91 ns Therefore the DRAM chosen should have a "tRAC" less then or equal to 148 ns and a "!cAC" less than or equal to 91 ns. Standard 120 ns DRAMs meet this criteria. The minimum RAS PRECHARGE TIME will be approximately one and one half clock periods = 100 + 50 = 150 ns. The minimum CAS PRECHARGE TIME will be approximately one and one half clock periods plus 35 ns (minimum tRICl -tRICH for the DP8409-2) = 100 + 50 + 35 = 185 ns. The minimum RAS PULSE WIDTH will be approximately two clock periods - 5 ns (maximum tRPDl -tRPDH for the DP8409-2) = 200 - 5 = 195 ns. EXAMPLE DRAM TIMING CALCULATIONS A) 8 MHz Series 32000 CPU, No Walt states #1) RASIN = Tl - 2ns (FCLK to PHil skew) + 12 ns ("8" PAL clocked output) = 125 - 2 + 12 = 135 ns maximum # 2) RASIN to RAS low = 20 ns maximum (DP8419) #3) RASIN to CAS low = 80 ns (DP8419 RASIN - CAS low) - 3 ns (load of 72 DRAMs instead of 88 DRAMs , speced in data sheet) = 77 ns #4) 74F245 transceiver delay = 7 ns maximum #5) CPU data setup time to "T4" = data setup to PHI2 T.E. + maximum PHI2 F.E. to PHil R.E. = 15 + 5 = 20 ns minimum "tRAC"=Tl +T2+T3-#1- #2-#4-#5 = 125+ 125+ 125-135-20-7-20= 193 ns "!cAC"=T1 +T2+T3- #1- #3-#4-#5 = 125+ 125+ 125-135-77-7-20= 136 ns Therefore the DRAM chosen should have a "tRAC" less then or equal to 193 ns and a "!cAC" less than or equal to 136 ns. Standard 150 ns DRAMs meet this criteria. The minimum RAS PRECHARGE TIME will be approximately one and one half clock periods = 125 + 62 = 187 ns. The minimum CAS PRECHARGE TIME will be approximately one and one half clock periods plus 35 ns (minimum tRICl -tRICH for the DP8409-2) = 125 + 62 + 35 = 222 ns. The minimum RAS PULSE WIDTH will be approximately two clock periods - 5 ns (maximum tRPDL -tRPDH for the DP8409-2) = 250 - 5 = 245 ns. The minimum CAS PULSE WIDTH will be approximately two clock periods - 70 ns (maximum tRICl -tRICH for the DP8409-2) = 200 - 70 = 130 ns. The smallest pulse widths are generated during WRITE cycles since RASIN during WRITE cycles starts later than RASIN during READ cycles. If one Inserted a WAIT state in READ cycles the DRAM column access times and the RAS pulse width would be increased by one clock period (100 ns in this case). A WAIT state in WRITE cycles would Just increase the RAS pulse width by one clock period. SUGGESTIONS It is suggested that the DP8409A could be used up to 8 MHz. Above 8 MHz one should use the DP8409-2 or the DP8419. Also, fast PALs ("A" or "8" parts) should be used at 8 MHz and above. INTERPRETING THE DP84412 PAL EQUATIONS The boolean equations for the DP84412 were written using the standard PALASMTM format. In other words the equation: "IF (Vecl RASIN=INCY·MODE*4DoDDIN" will mean; The output "RASIN" (see pin list for DP84412) will be active low (inverted RASIN) when the output "INey" is low (making INCY high) AND the output "MODE" is high AND the output "4D" is low (making 4D high) AND the input ODIN is low (making DDIN high). The minimum CAS PULSE WIDTH will be approximately two clock periods - 70 ns (maximum tRICl -tRICH for the DP8409-2) = 250 - 70 = 180 ns. 3-28 c : PAL Boolean Equations PAL1SRSA :t .... ;FAST PAL NEW PAL FOR THE NATIONAL SEMICONDUCTOR NS3201S, 32008, 32032 NATIONAL SEMICONDUCTOR (WORKS UP 10 MHz) FCLK TSO RFIO ADS DDIN WAITWR CTTL CS WAITRD GND OE CWAIT 4DLY 3DLY 2DLY MODE RASIN CYCLED INCY VCC INCY·MODE·2DLY"WAITWR+ CseINcyeMODEe2DLY + CSeINCyeMODE-2DLY-WAITWReCTTL+ RASINeINCyeMODEe2DLY ;Start RASIN fast during "READ" cyole "WRITE" oycle without WAIT states Hidden Refresh RASIN "WRITE" cycle with WAIT states oontinue RASIN CYCLED : = MODE·2DLY·WAITWR·DDIN·CTTL+ MODE·2DLY·WAITRD·DDIN·CTTL+ MODE·2DLY· 4DLY·WAI TRD·DDIN· CTTL + MODE·2DLY·4DLY·WAITWR·DDIN·CTTL+ ;No WAITS inserted ;No WAITS inserted ;WAIT in READ cycle ;WAIT in WRITE cycle CYCLED·TSO·MODE+ CYCLED·MODE·CTTL MODE : = RFIO· INCY"2DLY· CTTL + MODE·3DLY+ ;forced refresh during idle ;states, in long cycles, ;or at the end of a cycle MODE·4DLY+ MODE·CTTL 2DLY : = MODE·4DLY·CTTL+ 2DLY"CTTL+ INCY·CYCLED·MODE·3DLY·4DLY·CTTL+ CS·DDIN·WAITRD· INCY·MODE·2DLY· 3DLY·4DLY + CS·DDIN·WAITWR·INCY·MODE·2DLY·3DLY·4DLY ;extend 2DLY if WAIT states are wanted 3DLY : = 2DLY·4DLY"CTTL+ 3DLY·CTTL 4DLY 3DLY·CTTL+ 4DLY·CTTL+ INCY·MODE·CTTL+ INCY·MODE·2DLY·CTTL IF (VCC) INCY = ADS·MODE+ CS·TSO·CYCLED·MODE·2DLY·4DLY+ ;Start INCY for CS INCY·CYCLED+ ;access after forced INCY·2DLY ;refresh IF (CS) CWAIT=CS·TSO·CYCLED·MODE·2DLY·4DLY+ CS·TSO·MODE+ ;for Access during ;forced refresh ;during forced refresh CS· INCY" CYCLED·DDIN·WAITRD·MODE·2DLY· 3DLY·4DLY + ; CS READ cycle with ; WAIT states CS·INCY·CYCLED·DDIN·WAITWR·MODE·2DLY·3DLY·4DLY CS WRITE cycle with ; WAIT states FIGURE 1. Equations for the Series 32000 Family Interface PAL 3·29 N N ,.. : fQ System Timing Diagrams 10 MHz SERIES 32000 READ CYCLE (NO WAIT STATESI T2 T1 FCLK CTTL HIDDEN REFRESH CYCLE (WRITEI T4 T3 T1 T3 T4 nruruu lfUn.ru lJ1J lJ1J lJ1J UU L ILrL rL rL rL ILrL n I nJ ADDRESS/DATA T2 , -E~ " I READ DATA }K - ) WRITE DATA -~ I n i.oo- ADDRESS r L I I L J I I RF 110 • • TL/F/8397-3 3-30 System Timing Diagrams (Continued) 10 MHz SERIES 32000 READ CYCLE (W/1 WAIT STATEI 10MHz SERIES 32000 WRIn CYCLE (NO WAIT STATES) T2 T1 FCLK CTTL T3 Tl il T' TW T3 T' ruuruuIU1Jruu nmIU1JIU1J nmruu rLrLrLrL rLrL rL rL rL n ru )K WRITE DATA ADDRESS/DATA : E E S S II READ DATA } II I I I I " II I r--, I ADDRESS) r I Rf I/O , I CWAIT J I I TL/F/8397-4 3-31 .... ~~------------------------------~ :: ~ System Timing Diagrams (Continued) Q 10MH, SERIES 32000 iwmwJ! =0) HIDDEN RFSH WRITE CYCLE T2 11 FCLK CTlL WRITE CYCLE (WITH 1WAIT STATE) T3 11 T4 T2 TW T3 T4 ruuruu rtrurtru nmMJ1JlJMJru-u n-n- rL n-rL rL rLrLrL ru K-K I ADS ADDRESS/DATA , ) WRITE DATA ADDRESS ADDRESS I II I J I I READ DATA } ;1 I r I RFI/D I, J n ~ 3-32 System Timing Diagrams (Continued) 10 MHz SERIES 32000 FORCED REFRESH WITH NDN-fS ACCESS AT THE END Ti FCLK cm Ti Ti 11 T2 T3 U1J 11lJlJlJru-u lJ1J lfU ~ T4 nm n-n- ILILrL rL I WRITEOATA ~SS ADDRESS/DATA ) Ii I L RFI/D II I , TLiF /8397-6 3-33 ... ,---------------------------------------------------------------------------------, System Timing Diagrams ~ ~ (Continued) ~ o 10 MHz SERIES 32000 FORCED REFRESH WITH WRITE ACCESS T2 T1 ,CLK em TW1 TW2 TW3 TW4 TW5 T3 T4 ru-uiUlJ1JlJiUlJruuruunruruuill.! rL n-n-n- ILn-n- ILrL lJ ADDRESS/DATA K- - } WRITE DATA ADDRESS r- I r I I I L RFI/D I~ J 1 J t J + TL/F /8397 - 7 3-34 System Timing Diagrams (Continued) 10MHz SERIES 32000 FORCED REFRESH WITH READ ACCESS AT THE END TI 11 FCLK CTTL Ti Ti T2 11 T3 TW T4 ruuruuUUlJlJUUnruruu UUUU rL ILrL rL rL ILrL rLrtf ADDRESS/DATA I ADDRESS ' \ " " I READ DATA } II II r I It I L RF I/O I I , t I TL/F/8397-8 3-35 ~ .,... "'=" "'=" co r----------------------------------------------------------------------------, System Timing Diagrams (Continued) a.. C lDMHz SERIES 32000 FORCED REFRESH WITH NDN-CS ACCESS THEN CS ACCESS T1 FCLK CTn T2 T3 Ti T4 T1 T2 T3 T4 rtru UlJ 111Jruuruuruuruuruuruu rL n- n-rLrLrLrLrL rL I ru ADDRESS/DATA K ADDRESS l I '\ WRITE DATA ADDRESS J } WRITE DATA r I I I I I r RF I/O II 1 t TL/F/8397-9 3-36 .---------------------------------------------~c ~National PRELIMINARY ~ Semiconductor !... I\) I\) DP84422 Dynamic RAM Controller Interface Circuit for the 68000/008/010 CPU(s) General Description The DP84422 is a new Programmable Array Logic (PAL®) device, that replaces the DP84322, designed to allow an easy interface between the Motorola 68000 family of processors and the National Semiconductor DP8409A, DP8429, or DP8419 DRAM controller. The new DP84422 supplies all the control signals needed to perform memory read, write, read modify write (as in the Test and Set, "TAS", instruction), and refresh and work with the 68000 family of processors up to 12.5 MHz. Logic is also included to insert WAIT states, if wanted, into the microprocessor READ or WRITE cycles when using fast CPUs. Features • Provides a 3-chip solution for the 68000 family, dynamic RAM interface (DP8409A or DP8419, DP84422, and clock divider). • Works with all 68000 family speed versions up to 12.5 MHz.-(68008; 68000; and 68010). • Operation of 68000 processor at 10 MHz with no WAIT states. • Controls DP8409A or DP8419 Mode 5 accesses, hidden refreshes and Mode 1 Forced Refreshes automatically. • Inserts WAIT states in READ or WRITE cycles automatically depending on when WAIT is low, or if chip select becomes active during a forced Refresh cycle. • Uses a standard National Semiconductor PAL part (DMPAL16R4A). • The PAL logic equations can be modified by the user for his specific application and programmed into any of the PAls in the National Semiconductor family, including the new very high speed PALs ("8" PAL parts). Connection Diagram CK AI CK iimN AI 1ffiiCii RF 110 RFI/O IIiiItii! UDSLDS RIW !iii CLK cs m lIE RIW CK AI RF 110 iiASiN IITACK rml( 2li 311 lIIImiI R !iii ill! CLK CLK CI MOllE 4Ii CYCLED 15 14 13 iffi\Ci( MliliE 2li 2ij !D !D iii iii Im'lIF 12 tvmli DE IRC'IlIl' cs RASiII 11 CYCIEii IIICYlIl' YOOf lIE TUF/8398-1 Order Number DP84422J or DP84422N See NS Package J20A or N20A 3-37 • Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Operating Programming Supply Voltage, Vee 7V 12V Input Voltage 12V 5.5V Off·State Output Voltage Storage Temperature Range Operating Programming 5.5V 12V -65'C to + 150'C Recommended Operating Conditions Symbol Commercial Parameter Min Supply Voltage Vee tsu Max 5.25 4.75 5 I Low 15 10 I High 15 10 Setup Time from Input or Feedback to Clock 25 16 Width of Clock tw Units Typ V ns ns th Hold Time 0 -10 TA Operating Free·Air Temperature 0 25 Te Operating Case Temperature ns 75 'C 'C Electrical Characteristics Over Recommended Operating Temperature Range Symbol Parameter High Level Input Voltage Vil Low Level Input Voltage VIC Input Clamp Voltage Vee = Min, 11= -18 rnA VOH High Level Output Voltage Vee = Min Vil =0.8V VIH=2V IOH=-3.2mA COM Val Low Level Output Voltage Vee=Min Vil =0.8V VIH=2V IOL =24mA Off-State Output Current Vee = Max Vil =0.8V VIH=2V IOZH 10Zl Typ Min Test Conditions VIH Max Units 0.8 V -1.5 V 2 V -0.8 2.4 2.8 COM V 0.3 0.5 V Vo=2.4V 100 /LA Vo=O.4V -100 /LA II Maximum Input Current Vee=Max, VI=5.5V 1 mA IIH High Level Input Current Vee = Max, VI = 2.4V 25 III Low Level Input Current Vee = Max, VI=O.4V los Output Short-Circuit Current Vee=5V Icc Supply Current Vee = Max -30 Vo=OV -0.02 -0.25 /LA mA -70 -130 mA 120 180 mA Switching Characteristics Over Recommended Ranges of Temperature and Vee Vee=5V ± 10% Symbol Commercial: TA=O to 75'C, Vee=5V ± 5% Parameter Test Conditions R1,R2 Commercial Min CL=50pF Units Typ Max tpo Input or Feedback to Output 15 25 ns telK Clock to Output of Feedback 10 15 ns tpzx Pin 11 to Output Enable 10 20 ns tpxz Pin 11 to Output Disable CL =5 pF 11 20 ns tpzx Input to Output Enable Cl =50pF 10 25 ns tpxz Input to Output Disable Cl =5 pF 13 25 fMAX Maximum Frequency 25 Vcc= Max. at minimum temperature 3-38 30 ns ns U) ~ S' 3 c ALlle'S DECOUPlED .. SERIES DAMPING RESISTERS *1 TIE UNUSED ADDRESS lINES TO Vee i' This circuit provides direct s.port at the 81000 Test MIl Set Insbutti.. - . PAGE MODE DRAMs. CC ..) AO·A23 'r r A B C 74ALS138 ADDRESS 1-23 r AS ~ ENABLE VCC 2.2k I.- lOS '" iiiiS RtW +500--::- LOS '--- AS ~UDS DlACK DR I-- _ C .~ Rfl/O OPB4422 ~ UOSLDS OAlABUS CLK MODE RASIN R/W t If>o.I I CLOCK CK CLK I DEI;!. - RFCK i:ASii 01/00 lir ~ 80-7.8 cs CO-7.8 BO.1 RAS> _ WE M1 ~ M2=RFSH RASIN RGCK RFCK ~ 0-15 raW J T WE • QO·6. 1. B • CAS I] ~ 6BOOO OilS LO ::.1.I_K2HI MEMOIIY I- WE CASH WiN 68000 [jjS- ENABLE 12) 74F245 TRANSCEIVERS (IF REQUIRED) 1 ~ 01/00 LO 1.1 y: i--- ao~.l.B BAIII3 HI RAS3 I...- WE OIR I CASH 01/00 RFRQ=RF 110 RASO 0PB4'9 RAS. OR RAS2' OP8409A RAS3 • BANK 1 HI MEMORT 08-&.1.1 ADS Mii 3 SANKO HI MEMORY 00·&.1.1 I- 0PB4311O DATA BUS ? "= OlACK c.> _ifoSii WE raW! Ff .. ~ MC68000 c" A1-A18 1010- RAMCS iii .I_KO LO W\:. CASH • MEMORY ~ ~ ouoo~ I DATA IN/DATA DUl TUF/8398-2 ~~""8da II Mnemonic Description Functional Description INPUT SIGNALS The following description applies to both the DP8409A, DP8429, and the DP8419 dynamic RAM controllers. A memory cycle starts when chip select (CS) and address strobe (1i$) are true. RASIN is supplied from the DP84422 to the DP8409A dynamic RAM controller, which then supplies a RAS signal to the selected dynamic RAM bank. After the necessary row address hold time, the DP8409A switches the address outputs to the column address. The DP8409A then supplies the required CAS Signal to the DRAM. In order to do byte operations it is suggested that the user provide external logic, as shown in the system block diagram, to produce a HIGH CAS and a LOW CAS. To differentiate between a READ and a WRITE, the R/W signal from the CPU is used. A refresh cycle is started by one of two conditions. The refresh cycle caused by the first condition is called a hidden refresh. This occurs when refresh clock (RFCK) is high, CS is not true, and RASIN goes low. Here the CPU is accessing something else in the system and the DRAM can be refreshed at that time, thereby being transparent to the CPU. The second type of refresh is called forced refresh. This occurs if no hidden refresh was performed while RFCK was high. When RFCK transitions Iowa refresh request (RFRQ) is generated. If there is not a DRAM access in progress the DP84422 will force a refresh by putting the DP8409A into mode 1 (automatic forced refresh mode). If the CPU tries to access the DRAM during a forced refresh cycle WAIT states will be inserted into its cycles until the forced refresh is over and the DRAM RAS precharge time has been met. Then the pending DRAM access will be allowed to take place. 1) 2) "CLK", "CK" "1i$" 3) "CS" 4) "R" 5) "RFIO" 6) "WAIT" 7) "UDSLDS" 8) "DH" 9) "OE" This is the 68000 CPU clock. This is the 68000 address strobe pin. This signal also tells when the 68000 is in a cycle. This is the chip select signal for the DP8409A. This is the READ/WRITE pin from the 68000. This is the RFIO, used as refresh request, from the DP8409A. This pin allows the insertion of 1 WAIT state in a CS Access cycle if low. As an example; if the user wants 1 WAIT state in READ accesses but 0 WAIT states in WRITE accesses he can invert the "R/W" input to this input. This input was produced by inverting the two terms UDS and LDS and then logically "NOR"ing them together. This input is low whenever one or both lJi5S or LDS are low. This pin is used in order to support the 88000 "TAS" instruction. This Signal is used in the "DTACK" PAL output. This input allows the user to disable the DP8409A119 hidden refresh, when low, provided he also ties "~" low on the DP8409A119. When this input is low "RASIN" is only brought low when a "CS" access ("CS" input to PAL low) is in progress Must be tied low to enable DP84422 outputs. The DP84422 also allows forced refreshes to take place during long accesses of other devices. For instance, if EEPROM takes several microseconds to write to, the DRAM will still be refreshed while that access is in progress. OUTPUT SIGNALS 1) "CYCLED" 2) "RASIN" 3) "DTACK" 5) "~,, 6) 7) 8) "2DLY'·' "3DLY" "4DLY" In a standard memory cycle, the access can be slowed down by one clock cycle to accommodate slower memories or allow time to generate parity. This is accomplished by inserting a WAIT state into the processor access cycle. The DP84422 can insert WAIT states into either READ cycles, WRITE cycles, READ MODIFY WRITE cycles, or both READ and WRITE cycles or the READ and WRITE portion of a READ MODIFY WRITE cycle. The extra WAIT state will not appear during the hidden refresh cycle, so faster devices on the CPU bus will not be affected. During a Test and Set instruction CAS is generated twice while FiAS is low. In order for this instruction to execute properly Page Mode DRAMs must be used. This signal goes low once a hidden refresh or an access has been done as indicated by 2DLY and 3DLY being low. This signal goes high once the cycle is over as indicated by AS going high. See also "DH input This Signal goes low following 1i$ during an access or hidden refresh. See also "DH" input. This signal causes WAIT states to be inserted into the 68000 processor cycles if it is not Iowa setup time before S4 falling clock edge. This signal indicates that an access has been requested during a forced refresh cycle. This Signal is used to insert WAIT states during the forementioned condition or to prevent a "nonCS" access cycle from automatically starting. This signal is used to pull the DP8409A pin M2 low in order to go to mode 1 to do a forced refresh. This signal is an internal delay. System Interface Description All members of the Motorola 68000 family of processors are able to use the DP84422. RASIN during a READ cycle will always start at the beginning of the "S3" processor cycle. The user must guarantee that CS is valid a minimum of 34 ns before RASIN becomes valid, unless the PAL "l5R" input is low and the DP8409A1 19 "CS" input is tied low (hidden refresh disabled). This Signa! is an internal delay. This signal is an internal delay. 3-40 System Interface Description (Continued) Several critical parameters in this application involve the input system CLOCK and the ADDRESS STR08E, AS. These parameters become most critical at higher frequencies (10 MHz and above) where it is suggested that they are directly connected to the corresponding pins of the Motorola 68000 family ICs. This section of the data sheet goes through the calculation of the "tRAC" (RAS access time) and "tCAC" (CAS access time) required by the DRAM for the 68000 family CPUs to operate at a particular clock frequency without introducing wait states into the processor access cycles. 80th "tRAC" and "teAC" must be considered in determining what speed DRAM can be used in a particular system design. The DRAM chosen must meet both the "tRAC" and "teAC" parameters calculated. In order to determine the "tRAC" and "tCAC" needed the DP8419 and fast PALs ("8" type PALs) timing parameters were used. If the user is using the DP8408A/09A or a slower PAL device he should substitute their respective delays into the equation below. Most all of the calculations contained in this note use "RAHS" = 1 (15 ns guaranteed minimum row address hold time). Calculations only used "RAHS" = 0 (25 ns guaranteed minimum row address hold time) when the calculated access time from RAH exceeded 200 ns. This is because DRAMs can be found with row access times up to 150 ns that require only 15 ns row address hold times. The calculated "tRAC" and "tCAC" may differ from the actual system values depending upon the external circuitry used to produce "CASH" and "CASL". The DP8409A/19 "RASIN-CAS" low will be approximately 10-15 ns less than the value given in the data sheet because of the small loading on the DP8409A/19 "CAS" output. The external circuitry needed to produce "CASH, L" should be loaded such that the column address (from DP8409A119 is valid when "CASH, L" goes low. For this reason "RASINCASH, L" may be longer than the value used in the "tRAC, tCAC" calculations, and therefore may give a smaller "tRAC, tCAC" then was calculated. EXAMPLE DRAM TIMING CALCULATIONS A) 8 MHz 68000, No WAIT States #1) RASIN low = SO + Sl + AS low (maximum) + "8" PAL combinational output delay maximum = 125 + 60 + 15 = 220 ns maximum #2) RASIN to RAS low = 20 ns maximum #3) RASIN to CAS low = 80 ns (DP8419 RASIN - CAS low) - 3 ns (load of 72 DRAMs instead of 88 DRAMs speced in data sheet) = 77 ns #4) 74F245 transceiver delay = 7 ns maximum # 5) CPU data setup time = 15 ns minimum "tRAC" = (SO + Sl) + (S2 + S3) + (S4 + S5) + S6 (min) - #1 - #2- #4 - #5 = 125 + 125 + 125 + 55 - 200 - 20 - 7 - 15 = 188 ns "tCAC" = (SO + Sl) + (S2 + S3) + (S4 + S5) + S6 (min) - #1 - #3 - #4 - #5 The minimum RAS PRECHARGE TIME will be approximately one and one half clock periods = 125 + 55 = 180 ns. The minimum CAS PRECHARGE TIME will be approximately one and one half clock periods plus 35 ns (minimum tRICl -tRICH for the DP8409-2)=125+55+35=215 ns. The minimum RAS PULSE WIDTH will be approximately two clock periods-5 ns (maximum tRPDl -tRPDH for the DP8409-2) = 250 - 5 = 245 ns. The minimum CAS PULSE WIDTH will be approximately two clock periods -70 ns (maximum tRICl -tRICH for the DP8409-2) = 250 - 70 = 180 ns. The smallest pulse widths are generated during WRITE cycles since RASIN during WRITE cycles starts later than RASIN during READ cycles. If one inserted a WAIT state in READ cycles the DRAM column access times, the CAS pulse width, and the RAS pulse width would be increased by one clock period (125 ns in this case). A WAIT state in WRITE cycles would just increase the RAS and CAS precharge by one clock period. B) 10 MHz 68000, No WAIT states #1) RASIN low = SO + S1 + AS low (maximum) + "8" PAL combinational output delay maximum = 100 + 55 + 15 = 170 ns maximum #2) RASIN to RAS low = 20 ns maximum #3) RASIN to CAS low = 80 ns (DP8419 RASIN - CAS low) - 3 ns (load of 72 DRAMs instead of 88 DRAMs speced in data sheet) = 77 ns #4) 74F245 transceiver delay = 7 ns maximum #5) CPU data setup time = 10 ns minimum "tRAC" = (SO + Sl) + (S2 + S3) + (S4 + S5) + S6 (min) - #1 - #2 - #4 - #5 = 100 + 100 + 100 + 45 - 170 - 20 - 7 - 10 = 138 ns "tCAC" = (SO + Sl) + (S2 + S3) + (S4 + S5) - S6 (min) - #1 - #3 - #4 - #5 = 100 + 100 + 100 + 45 - 170 - 77 - 7 - 10 = 81 ns Therefore the DRAM chosen should have a "tRAC" less than or equal to 138 ns and a "teAC" less than or equal to 81 ns. Standard 120 ns DRAMs meet this criteria. The minimum RAS PRECHARGE TIME will be approximately one and one half clock periods = 100 + 45 = 145 ns. The minimum CAS PRECHARGE TIME will be approximately one and one half clock periods plus 35 ns (minimum tRICl -tRICH for the DP8419) = 100 + 45 + 35 = 180 ns. The minimum RAS PULSE WIDTH will be approximately two clock periods-5 ns (maximum tRPDl -tRPDH for the DP8419)=200-5=195 ns. The minimum CAS PULSE WIDTH will be approximately two clock periods-50 ns (maximum tRICl -tRICH for the DP8419)= 200-50= 150 ns. The smallest pulse widths are generated during WRITE cycles since RASIN during WRITE cycles starts later than RASIN during READ cycles. If one inserted a WAIT state in READ cycles the DRAM column access times, the CAS pulse width, and the RAS pulse width would be increased by one clock period (100 ns in this case). A WAIT state in WRITE cycles would just increase the RAS and CAS precharge by one clock period. = 125 + 125 + 125 + 55 - 200 - 77 - 7 - 15 = 131 ns Therefore the DRAM chosen should have a "tRAC" less than or equal to 188 ns and a "tCAC" less than or equal to 131 ns. Standard 150 ns DRAMs meet this criteria. 3-41 • ~ ~ 3 ~ c ,---------------------------------------------------------------------------------, Interpreting the DP84422 PAL Equations The boolean equations for the DP84422 were written using the standard PALASMTM format. In other words the equation: "IF (VCC) RASIN=INCY .MODE*4D*R" will mean; The output "RASIN" (see pin list for DP84422) will be active low (inverted FiANN) when the output "INC)'" is low (making INCY high) AND the output "MODE" is high AND the output "4D" is low (makirig 4D high) and the input R/W is low (making R high). PAL16R4A ; FAST PAL NEW PAL FOR THE MOTOROLA 68000 PROCESSOR (WORKS UP TO 12.5MHZ) CK /AS RFIO /UDSLDS R /DH CLK /CS /WAIT GND /OE /INCYRF /CYCLED /4DLY /3DLY /2DLY /MODE /DTACK /RASIN VCC IF (VCC) RASIN = CS./INCYRF.AS·/MODE*4DLY./CYCLED*/CLK+ ;Start RASIN /CS./INCYRF.AS./MODE*2DLY./CYCLED./DH+ ;RASIN for Hidden RFSH CS.INCYRF*AS./MODE.4DLY./CYCLED./CLK+ ;Start RASIN after RFSH CS.RASIN./MODE*AS+ ;Hold RASIN valid ;Hold RASIN valid RASIN./MODE*2DLY IF (VCC) CYCLED =/MODE*2DLY*3DLY*/4DLY+ CYCLED.AS+ /MODE.CYCLED./CLK+ /CS*AS./MODE*/2DLY*/3DLY./4DLY ;Start ·CYCLED", does not allow ; glitch after refresh ;End on rising edge of CLK ;Start during long accesses of other ; devices IF (VCC) INCYRF =MODE*AS+ INCYRF.4DLY.AS ;Set Acoess during Refresh ;Hold it while 4DLY is low IF (CS) DTACK = AS*/WAIT*/R./MODE./CLK+ AS*WAIT./R*/MODE*2DLY*/CLK+ UDSLDS*/WAIT*R*/MODE./CLK+ UDSLDS*WAIT*R./MODE.2DLY./CLK+ DTACK.2DLY*/MODE+ DTACK*AS*RASIN*/MODE*/CYCLED+ DTACK*AS*/R*/MODE ;0 WAIT's for WRITE ;1 WAIT for WRITE ;0 WAIT's for READ ;1 WAIT for READ ;Continue. DTACK ;Continue DTACK ;Continue DTACK in RMW ; cycle ;For IDLE states or beginning ; states of 68000 cycle ;For RFSH during long cycles ; of other devices MODE = /RFIO./AS*/CYCLED./RASIN+ /CS*/RFIO.AS*CYCLED*/2DLY*/3DLY*/RASIN+ 2DLY 3DLY 4DLY MODE./3DLY+ MODE./4DLY = MODE*/4DLY+ /INCYRF.AS./CYCLED./MODE./3DLY.4DLY+ CS*INCYRF*AS·/CYCLED./MODE./3DLY.4DLY+ /MODE.2DLY./3DLY+ CS·WAIT.AS·/MODE.2DLY.3DLY./4DLY+ CS.AS./R*CYCLED./MODE*/2DLY*/3DLY./4DLY ;Start 2DLY ;Start 2DLY after RFSH ;Make 2DLY longer ;Start second 2DLY for ;the TAS instruction = 2DLY./4DLY = 3DLY+ /AS*/MODE+ /CS./RFIO.AS.CYCLED./2DLY./3DLY*/RASIN./MODE ;Need for beginning of forced refresh to ; inhibit "2DLY" FIGURE 1. Equations for New 68000 PAL That Supports the 68000 "TAS" Instruction 3·42 System Timing Diagrams 6B00010MHz HIDDEN REFRESH CYCLE 6800010 MHz READ CYCLE SO CK S1 S2 S3 rL L S4 S5 S6 S2 I k S3 S5 S6 S7 rurL r ) , \. f 1\ I S4 I )H DATA R/W S1 n-rLrL L I ADDRESS SO S7 ) '" I --1 r I L RFI/D I I ~ I I I I I n I I I I l l I L I • L TLlF/B39B-3 3-43 N~----------------------------~ N :: CO a. Q System Timing Diagrams (Continued) ~ READ CYCLE WITH ONE WAIT STATE 68000 WRITE CYCLE SO CK Sl S2 S4 S5 S6 S7 SO Sl S2 S3 S4 SW SW S5 S6 iL.Jn-n- rL rL ru rL n- L I I AS ADDRESS S3 -< I '\. DATA r I -< } } , f '\. I I I } r I I RIW , Rf 110 I OTACK J II n W I I I U , I I I I I L I I I I S7 I I 3·44 II I L I .. c-a System Timing Diagrams (Continued) CO N N 68000 In 10 MHz TEST AND SET INSTRUCTION SO CK Sl S3 S2 S5 S4 S6 S7 88 89 810 811 S12 813 814 S15 S16 S17 S18 S19 rLrLrL r-L tL rLrL rLrL rL r I ADDRESS -< }- , DATA , ~ I " I ~ " I I r I I R/W RF 110 , I U U I I I I I L I I I U , I I J 1 I I 1 TLlF/B39B-5 3·45 ~~------------------------------~ ~ :; ~ System Timing Diagrams (Continued) Q 68000 FORCED REFRESH THEN NON·CS ACCESS Ti CK Ti Ti SO Sl S2 S3 S4 S5 S6 S7 rL rL rL rL rL rL rL CS J l AS J ADDRESS } " 1 DATA )- " 1 I R/W , RFI/D ~ ~ L r I ,- I J I U I l l F oW , m I I I I I TL/F/8398-6 3·46 ,-----------------------------------------------------------------------, c ~ System Timing Diagrams (Continued) 01:00 p.) p.) 68000 FORCED REFRESH WITH C"!WRITE ACCESS SO CK L S1 S2 S3 S4 SM SM SW2 SW2 SW3 SW3 SW4 SW4 S6 S7 rL rL rLrL rL rL rtf l ADDRESS S5 K ) J DATA J " r l L R/W , ,, RFI/O 1 1 I L ~ ~ It ~ It II IL- II II Il l II I L. TL/F/8398-7 3-47 i System Timing Diagrams (Co"~'d) 68000 FORCED REFRESH WITH Cf ACCES8 AT THE END TI CK TI TI TI SO S1 82 S3 84 86 rL rLrL rLrL n- rL 86 n1 I J ADDRESS S7 1 '\. , J DATA '\. 1 I J R/iV RFIIO l • l [ ~ I ~ Il U I L J ~ Il J L ~I I I I TUF/8398-8 3-48 System Timing Diagrams (Continued) 68000 FORCED REFRESH CYCLE WITH NON·CS ACCESS THEN CS ACCESS SO CK Sl S2 S3 S4 S5 S6 TI SO Sl S2 S3 S4 S5 S6 S7 L rl-rL rL rL rLrLrL rL I ADDRESS S7 J , K r I ) "- L ,- DATA I- I I J I R/iN RF I/O n I l 1 I II I I I I U J I I I II I I LII I • L TL/F/8398-9 3-49 .. ~ r---------------------------------------------------------------------------------~ ~ ~ System Timing Diagrams (Continued) Q FORCED REFRESH DURING LONG NON-CS ACCESS CK ~~~~~~~~~~~~~~~~~~~ CS I I UDSLDS R I RASIN I -, I I I I I I I I I I II I I I L J I I I II I r- I DH TLIF/8396-10 3-50 .---------------------------------------------------~c ~National PRELIMINARY ~ Semiconductor DP84432 Dynamic RAM Controller Interface Circuit for the 8086/8088/80186/80188 CPU's General Description The DP84432 is a new Programmable Array Logic (PAL®) device, that replaces the DP84332, designed to allow an easy interface between the Intel 8088, 8086, 80188, 80186 CPU's and the National Semiconductor DP8409A, DP8429, or DP8419 DRAM controller. The new DP84432 supplies all the control signals needed to perform memory read, write and refresh and work with the Intel processors up to 10 MHz. Logic is also included to insert WAIT states, if wanted, into the microprocessor READ or WRITE cycles when using fast CPU's. Features • Provides a 3-chip solution for the 8086 family, dynamic RAM interface (DP8409A or DP8419, DP84432, and clock divider) • Works with all 8086 family speed versions up to 10 MHz • Operation of 8086, 8088, 80186, 80188 at 10 MHz with no WAIT states • Controls DP8409A or DP8419 Mode 5 accesses, hidden refreshes and Mode 1 Forced Refreshes automatically • Inserts WAIT states in READ or WRITE cycles automatically depending on whether WAITRD or WAITWR are low, or if CS becomes active during a forced Refresh cycle • Uses a standard National Semiconductor PAL part (DMPAL16R4A) • The PAL logic equations can be modified by the user for his specific application and programmed into any of the PALs in the National Semiconductor family, including the new very high speed PALs ("S" PAL parts) Connection Diagram ROY I1"mN RF 110 ALE MODE C::>--"'""""""---, C>--...:.:;;;;-,____.!.I 2ii CLK C>---:::~------'7t OLYRO WAITWR r",>-..1!lM-J-===:::ij 2ii 3D ,jjj ,jjj INCY OT~:>--~----~ MODE 3D INCYRF L.>----------' ROY RASfN INCYRF INCY TL/F/B399-1 Order Number DP84432N or DP84432J See NS Package Number N20A or J20A 3-51 " co .j:o. .j:o. Co) ~ Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Operating Programming 7V 12V 5.5V 12V 5.5V 12V -65·C to + 150·C Supply Voltage, Vee Input Voltage Off·State Output Voltage Storage Temperature Range DP84432 Recommended Operating Conditions Symbol Commercial Parameter Min Vee tw Supply Voltage I Width of Clock I Units Typ Max 5.25 4.75 5 Low 15 10 High 15 10 V ns tsu Setup Time from Input or Feedback to Clock 25 16 th Hold Time 0 -10 TA Operating Free-Air Temperature 0 25 Te Operating Case Temperature ns ns ·C 75 ·c Electrical Characteristics Over Recommended Operating Temperature Range Symbol Parameter Test Conditions VIH High Level Input Voltage VIL Low Level Input Voltage Vie Input Clamp Voltage Vee = Min., II = -18 mA VOH High Level Output Voltage Vee = Min. VIL = 0.8V VIH = 2V VOL Low Level Output Voltage Vee = Min. VIL = 0.8V VIH = 2V Off-State Output Current Vee = Max VIL = 0.8V VIH = 2V 10ZH 10ZL Min Typ Max Units 0.8 V -1.5 V 2 V -0.8 10H = - 3.2 mA COM 204 2.8 V 0.3 0.5 V Va = 2AV 100 /LA Va = OAV -100 /LA 1 mA 10L = -24mACOM II Maximum Input Current Vee = Max., VI = 5.5V IIH High Level Input Current Vee = Max., VI = 2.4V IlL Low Level Input Current Vee = Max., VI = 0.4V los Output Short-Circuit Current Vee = 5V lee Supply Currentt Vee = Max. -30 Vo = OV 25 /LA -0.02 -0.25 mA -70 -130 mA 120 180 mA Switching Characteristics Over Recommended Ranges of Temperature and Vee Vee=5V±10%. Commercial: TA=O to 75·C, Vee=5V±5% Symbol Parameter Test Conditions Rl,R2 tpD Input or Feedback to Output teLK Clock to Output or Feedback tpzx Pin 11 to Output Enable tpxz Pin 11 to Output Disable CL = 5 pF tpzx Input to Output Enable CL = 50 pF tpxz Input to Output Disable CL = 5 pF fMAX Maximum Frequency Commercial Min CL = 50 pF 25 vee = Max. at minimum temperature. 3-52 Units Typ Max 15 25 ns 10 15 ns 10 20 ns 11 20 ns 10 25 ns 13 25 ns 30 ns C ...... "tI Block Diagram co 8086 System Block Diagram Co) ADDRESS/DATA N All IC's Decoupled "'r-- "'Series damping resistors "'1 Tie unused address lines to Vee ENABLE 14AS373 OR 74F373 FIfC AO-A19 I r- aO-7.B 11m In HI SANKO MEMORY I- m Algi 'us ALE 8086,8088 tB284A& 82887) " 80188,B0188 ml OTiA VCC +8- mm: DRAMa _00-7,8 AO~"" - .... """"f'S r:: fS- AlE ROYI ....... ClnCK DP84300 MlmE ;mm Jr= 01,* fI( I RFCK .... 8086 DTIA ADDRESS/DATA MO DIR mE !lImE .DBS AD 74F246 TRANSCEIVER MEMORY DIlDO In DP8409AI 841918429 iim m; RASi 11m ~ '"""IW- 0- aO-7. B HI BANK2 ifIi!1i r- CAS MEMORY HWE MlmE=M' Will RGCK CAl RFCK aO w 7,8 WiN HI BANK 1 I~ I RFRO WE f-oNC "- I-- 00-7,8 RAS3 ' - - CAS AWE ....... 1 1 HI BANK 3 MEMORY [WE 01100 AWE ........ lOW BYTE 01100 I~I! OTiI! .... AWE BD.' OP84432 ROYI CLK m IIElLl!= .,f"" ., OTIR r- RO-7. B CD-7,B .5Va-- ADS RFI/O eLDeK -11m ... - 'I '--- 01100 In ~ ,.,f"" mm 4.7kQ ~ AENI 0 745139 ~fD - j I~ 1 A1-A19 A18 • A ADDRESS/DATA AWE 1l/IE 1- DATAIN/OUT TLIFIB399-2 Mnemonic Description INPUT SIGNALS 1) "CLOCK" 2) 3) 4) 5) 6) Inverted clock from 8284A or 8288. "CLOCK" should be delayed from CLOCK (pin 5). "CS" From decoder chip (chip select) (active low), "ALE" From 8086 (active high). "RFI/O" RFRO (refresh request) in mode 5, From 8409A, an active low Signal. "CLOCK" The non-inverted clock directly from the 8284A. This Signal should be unbuffered to this input so as not to incur any extra delay in the RASIN generation time. "DELAYREAD" This input signal allows the user to delay when the RASIN signal becomes valid to the DP8409A during a READ cycle of the 8086. This input should be low when using the DP8409A unless an external delay line is used to guarantee a 30 ns CS to RASIN delay (for DP8409A or 15 ns for DP8419) or if the user can afford to disable the hidden refresh by permanently tying CS low on the DP8409A. 3-53 7) "WAITWRITE" 8) "DT/R" or "S1" This signal is used to delay when RASIN becomes valid during an 8086 WRITE cycle and also adds a WAIT state into a CS WRITE access cycle. One may want to delay when RASIN becomes valid during a WRITE cycle when generating a parity bit for each byte, This would allow time to generate parity and be assured that the data and parity bit were both written to memory. Used to differentiate between READ and WRITE cycles, and to allow CS READ cycles to start early. If the system is not a minimum mode 8086 or 8088 system then the status signal "S1" should be used instead of "DT /R" so that the DP84432 knows immediately whether the CPU is doing a READ or a WRITE access cycle. • ~ r-------------------------------------------------------------------------~ ~ ~ c Mnemonic Description 9) 10) "WAITREAD" "OE" (Continued) Used to insert 1 wait state into the 8086 READ bus cycle. The wait state following bus cycle "T3" allows the use of memory with longer access times (tCAel. An active low signal. This input enables the outputs of the "D-Flip Flop" outputs of the PAL. occurs if no hidden refresh was performed while RFCK was high. When RFCK transitions Iowa refresh request (RFRQ) is generated. If there is not a DRAM access in progress the DP84432 will force a refresh by putting the DP8409A into mode 1 (automatic forced refresh mode). If the CPU tries to access the DRAM during a forced refresh cycle WAIT states will be inserted into its cycles until the forced refresh is over and the DRAM RAS precharge time has been met. Then the pending DRAM access will be allowed to take place. The DP84432 also allows forced refreshes to take place during long accesses of other devices. For instance, if EEPROM takes several microseconds to write to, the DRAM will still be refreshed while that access is in progress. OUTPUTS SIGNALS 1) "MODE" 2) 3) 4) 5) 6) "2DLY" "3DLY" "4DLY" "RASIN" "RDY1" 7) "INCYCLE REFRESH" This pin goes to M2 on the DP8409A to change from mode 5 to mode 1 (only used for forced refresh). Delay used internal to the PAL. Delay used internal to the PAL. Delay used internal to the PAL. To the 8409A (creates RAS's). To the 8284A or 8288 to insert wait states into the 8086 bus cycles (active low). This signal is used in the Figure 1 PAL to detect that an access cycle was started during a DRAM refresh cycle. This allows the PAL to determine, later in the cycle, whether to restart the "INCYCLE" signal or not. If the CPU is not accessing the DRAM, as determined by "CS" being low, then "INCYCLE" is not restarted. This signal goes active from the CPU ALE signal. This signal indicates that the processor is dOing an access somewhere in the system. This signal stays low for several T states of the access cycle. In a standard memory cycle, the access can be slowed down by one clock cycle to accommodate slower memories or allow time to generate parity. This is accomplished by inserting a WAIT state into the processor access cycle. The DP84432 can insert WAIT states into either READ or WRITE cycles, or both. The extra WAIT state will not appear during the hidden refresh cycle, so faster devices on the CPU bus will not be affected. SYSTEM INTERFACE DESCRIPTION The 80186 or 80188 will be able to use the DP84432 but it will be necessary to invert "ALE" of the 80186 or 80188 and logically NOR it with the "CLOCK" signal. This fix makes the 80186 or 80188 "ALE" signal appear to be similar to the 8086 or 8088 "ALE" signal. The 8088 will be able to use this PAL, but the 8088 will not need the logic necessary to produce LWE, HWE. The 80286 can not use this PAL because it's WAIT state logic is different. (See DP84532 data sheet). The DP84432 differentiates between READ and WRITE cycles, allowing the RASIN signal to start earlier during a READ cycle compared to a WRITE cycle. RASIN during a READ cycle can start during T1 or T2 of a processor cycle depending on whether the DELAYREAD input is set low or high. If DELAYREAD is false the user will need to use an external delay line to guarantee that CS will be valid a minimum of 30 ns before RASIN becomes true. If the user is willing to give up hidden refreshes (CS tied permanently low on DP8409A) he must only guarantee that the addresses are valid at the inputs of the DP8409A by a minimum of 10 ns before RASIN becomes valid. Functional Description The following description applies to both the DP8409A and the DP8419 dynamic RAM controllers. A memory cycle starts when chip select (CS) and address latch enable (ALE) are true. RASIN is supplied from the DP84432 to the DP8409A dynamic RAM controller, which then supplies a RAS signal to the selected dynamic RAM bank. After the necessary row address hold time, the DP8409A switches the address outputs to the column address. The DP8409A then supplies the required CAS signal to the DRAM. In order to do by1e operations it is suggested that the user provide external logic, as shown in the system block diagram, to produce a HIGH WRITE ENABLE or a LOW WRITE ENABLE. To differentiate between a READ and a WRITE, the DT /R (or status signal "S1" in a maximum mode 8086 or 8088 system or in a 80186,8188 system) signal from the CPU is inverted and also supplied to the external WRITE ENABLE logic. This section of the data sheet goes through the calculation of the "tRAC" (RAS access time) and "tCAC" (CAS access time) required by the DRAM for the iAPX 86/88/186/188 family CPUs to operate at a particular clock frequency without introducing wait states into the processor access cycles. Both "tRAC" and "tCAC" must be considered in determining what speed DRAM can be used in a particular system design. The DRAM chosen must meet both the "tRAC" and "tCAC" parameters calculated. In order to determine the "tRAC" and "tCAC" needed the DP8419 and fast PALs ("B" type PALs) timing parameters were used. If the user is using the DP8408A109A or a slower PAL device he should substitute their respective delays into the equations below. A refresh cycle is started by one of two conditions. The refresh cycle caused by the first condition is called a hidden refresh. This occurs when refresh clock (RFCK) is hiQh, CS is not true, and RASIN goes true. Here the CPU is accessing something else in the system and the DRAM can be refreshed at that time, thereby being transparent to the CPU. The second type of refresh is called forced refresh. This Most all of the calculations contained in this note use "RAHS" = 1 (15 ns guaranteed minimum row address hold time). Calculations only used "RAHS" = 0 (25 ns guaranteed minimum row address hold time) when the calculated access time from RAS exceeded 200 ns. This is because DRAMs can be found with row access times up to 150 ns that require only 15 ns row address hold times. 3-54 Functional Description (Continued) EXAMPLE ORAM TIMING CALCULATIONS The minimum RAS PRECHARGE TIME will be approximately one clock period+55 ns (minimum clock low)-15 ns (maximum DP84432 clocked output delay for ending RASIN)=125+55-15=165 ns. The minimum CAS PRECHARGE TIME will be approximately one clock period + 55 ns (minimum clock low) -15 ns (maximum clocked output delay for ending RASIN) + 35 ns (minimum tRICL-tRICH for the DP8409-2) = 125 +55-15+35=200 ns. The minimum RAS PULSE WIDTH will be approximately two clock periods-5 ns (tRPDL-tRPDH for the DP8409-2) =125+125-5=245 ns. The minimum CAS PULSE WIDTH will be approximately two clock periods-70 ns (maximum tRICL-tRICH for the DP8409-2) = 125+125-70= 180 ns. A) IAPX 86/88 8 MHz, No WAIT states, "/OLYRO" = low #1) RASIN low=1 system clock period + 15 ns ("8" PAL combinational output delay) = 125 + 15 = 140 ns maximum #2) RASIN to RAS low = 20 ns maximum #3) RASIN to CAS low=80 ns (DP8419 RASIN-CAS low)-3 ns (load of 72 DRAMs instead of 88 DRAMs speced in data sheet) = 77 ns maximum (using 15 ns minimum row address hold time) #4) 74F245 transceiver delay = 7 ns maximum #5) CPU data setup time to "T4"=20 ns minimum "tRAC" =T1+T2+T3-#1-#2-#4-#5 = 125+125+ 125-140-20-7-20= 1B8 ns "tcAC" =T1+T2+T3-#1-#3-#4-#5 =125+125+125-140-77-7-20=131 ns Therefore the DRAM chosen should have a "tRAC" less then or equal to 1BB ns and a "tcAC" less then or equal to 131 ns. Standard 150 ns DRAMs meet this criteria. The minimum RAS PRECHARGE TIME will be approximately two clock periods = 125 + 125 = 250 ns. The minimum CAS PRECHARGE TIME will be approximately two clock periods plus 50 ns (minimum tRICL-tRICH for the DPB409-2) = 125 + 125 + 50 = 300 ns. The minimum RAS PULSE WIDTH will be approximately two clock periods-5 ns (tRPDL-tRPDH for the DP8409-2) =125+125-5=245 ns. The minimum CAS PULSE WIDTH will be approximately two clock periods - 70 ns (maximum tRICL-tRICH for the DP8409-2) = 125 + 125 -70 = 1BO ns. The above times are assuming the use of the DPB409-2 and a fast ("A" part) PAL. The smallest pulse widths are generated during WRITE cycles since RASiN during WRITE cycles starts later than RASIN during READ eycles. C) 8086, 8 MHz, CS Tied Low (no hidden refresh), OLYRO = HIGH, No Delay Line Needed, No Walt States Minimum RASIN=69 ns (min clk low)+13 ns (min PAL delay)=82 ns Maximum Address Valid=60 ns (ADD valid max)+8 ns (74F373) = 68 ns The address must be valid a minimum of 10 ns before RASIN goes valid at the inputs of the DP8409A or DP8419, which it will be given the ICs used in this example. #1) RASiN 10w=Maximum clock high+15 ns ("8" PAL combinational output delay) = 82 + 15 = 97 ns maximum #2) RASIN to RAS low = 20 ns maximum #3) RASIN to CAS low=97 ns (DP8419 RASIN - CAS low)-3 ns (load of 72 DRAMs instead of 88 DRAMs speced in data sheet) = 94 ns maximum (using 25 ns minimum row address hold time) #4) 74F245 Transceiver delay = 7 ns maximum #5) CPU data setup time to "T4"=20 ns minimum "tRAC" =T1+T2+T3-#1-#2-#4-#5 =125+125+125-97-20-7-20=231 ns "tcAC" =T1+T2+T3-#1-#3-#4-#5 = 125+125+125-97-94-7-20= 157 ns Therefore the DRAM chosen should have a "tRAC" less then or equal to 231 ns and a "tCAC" less then or equal to 157 ns. Standard 200 ns DRAMs meet this criteria. The minimum RAS PRECHARGE TIME will be approximately one clock period + 69 ns (minimum clock low) + 15 ns (maximum DP84432 clocked output delay for ending RASIN)=125+69-15=179 ns. B) 80186, 8 MHz, "OLYRO" = HIGH, No Hidden Refresh (CS = Low), No Walt States Minimum RASIN=55 ns (min clk low)+1 ns (min PAL delay) = 6B ns Maximum Address Valid=44 ns (ADD valid max)+B ns (74F373) = 52 ns #1) RASIN 10w=Maximum clock high+15 ns ("8" PAL combinational output delay) = 70 + 15 = 85 ns maximum #2) RASIN to RAS low=20 ns maximum #3) RASiN to CAS low=97 ns (DP8419 RASIN-CAS low)-3 ns (load of 72 DRAMs instead of BB DRAMs speced in data sheet) = 94 ns maximum (using 25 ns minimum row address hold time) #4) 74F245 Transceiver delay = 7 ns maximum #5) CPU data setup time to "T4"=20 ns minimum "tRAC" =T1 +T2+T3- #1- #2- #4- #5 = 125+ 125+ 125-B5-20-7-20=243 ns "tCAC" =T1+T2+T3-#1-#3-#4-#5 =125+ 125+ 125-85-94-7-20= 169 ns Therefore the DRAM chosen should have a "tRAC" less then or equal to 243 ns and a "tcAC" less then or equal to 169 ns. Standard 200 ns DRAMs meet this criteria. The minimum CAS PRECHARGE TIME will be approximately one clock period+69 ns (minimum clock low)-15 ns (maximum clocked output delay for ending RASIN) + 35 ns tRICL-tRICH for the DPB409-2) = 125 (minimum +89-15+35=214 ns. The minimum RAS PULSE WIDTH will be approximately two clock periods-5 ns (tRPDL-tRPDH for the DP8409-2) = 125+ 125-5=245 ns. The minimum CAS PULSE WIDTH will be approximately two clock periods-70 ns (maximum lRICL-tRICH for the DP8409-2) = 125 + 125 -70 = 180 ns. 3-55 Functional Description (Continued) D) 8088, 10 MHz, mI Tied Low (no hidden refre.h), J5J:VIm = HIGH, No Delay Line Needed, No Walt State. MINIMUM fiASi1\j = 52 ns (min clk low) + 13 ns (min PAL delay) = 65 ns 3) CAS PRECHARGE TIME-minimum amount of time from CAS high until CAS transitions low again. 4) AAS PULSE WIDTH-minimum RAS valid time during an· access, this usually occurs during a WRITE operation since RASlfii Is generated later then in a READ operation. 5) CAS PULSE WIDTH-minimum CAS valid time during an access. 6) DATA IN SETUP TIME-the data, during a DRAM WRITE access cycle, must be valid at the DRAM inputs when WRITE ENABLE or CAS transitions low, whichever occurrs last. For instance, during a WRITE operation, one does not want CAS to go valid until the data to be written is setup at the inputs to the dynamic RAM. Therefore an 8086 running at 5 MHz should use a DP8409A and a slower DP84432 PAL. EXAMPLE: 8086, 5 MHz, DP8409A, DP84432 (fast PAL "A" part) MINIMUM RASIN = 3 ns (min clk inversion) + 7 ns (min fast PAL clocked output) + 13 ns (min combinational fast PAL output) = 23 ns into the T2 CPU cycle. MAXIMUM ADDRESS VALID = 50 ns (ADD valid max) + 8 ns (74F373) = 58 ns The address must be valid a minimum of 10 ns before RASIN goes valid at the inputs of the DP8409A or DP8419. As an example use two 74ALS04 inverters to guarantee a minimum delay of 4 ns, therefore MINIMUM RASIN = 69 ns #1) fiASi1\j low = Maximum clock high + 15 ns ("B" PAL combinational output delay) = 61 + 15 = 76 ns maximum #2) fiASi1\j to RAS low = 20 ns maximum #3) fiASi1\j to CAS low = 80 ns (DP8419 RASIN - CAS low) - 3 ns (load of 72 DRAMs instead of 88 DRAMs speced in data sheet) = 77 ns maximum (using 15 ns minimum row address hold time) #4) 74F245 Transceiver delay = 7 ns maximum #5) CPU data setup time to "T4" = 5 ris minimum MINIMUM CAS = MINIMUM RASIN + MINIMUM RASIN TO CAS TIME = 23 + 95 = 118ns MINIMUM DATA VALID during an 8086 WRITE at 5 MHz = 110 ns MINIMUM DATA VALID at DRAM input = MINIMUM DATA VALID + MINIMUM TRANSCEIVER DELAY (74F245) = 110 + 7 = 117ns "tRAC" =T1+T2+T3-#1-#2-#4-#5 = 100+ 100+ 100-76-20-7-5= 192 ns "!cAC" =T1+T2+T3-#1-#3-#4-#5 = 100+ 100+ 100-76-77-7-5= 135 ns Therefore the DRAM chosen should have a "tRAC" less then or equal to 192 ns and a "tCAe" less then or equal to 135 ns. Standard 150 ns DRAMs meet this criteria. Therefore, worst case, the data could be valid 1 ns before CAS becomes valid at the DRAM inputs. Most DRAMs specify 0 ns setup time so this is OK, but if the DP8409A is driving less then the full load specified in the data sheet CAS could become valid before the data was availabl$ at the DRAM inputs. Therefore the user may want to use a slower PAL or adjust the PAL equations to start the WRITE later in the access cycle. For example, the second equation in the 'RA§N term could be adjusted as follows to accomplish a later RASIN during WRITE cycles: change "C;S.iNCY.MQi5E.2D.WAi'i'WF!" to "C;S.INCY.MODE.2D.WAITWR.CLK" The minimum RAS PRECHARGE TIME will be approximately one clock period + 69 ns (minimum clock low) - 15 ns (maximum DP84432 clocked output delay for ending RASIN) = 125 + 69 - 15 = 179 ns. The minimum CAS PRECHARGE TIME will be approximately one clock period + 69 ns (minimum clock low) - 15 ns (maximum clocked output delay for ending RASIN) + 35 ns (minimum tRICL-tRICH for the DP8409-2) = 125 + 69 - 15 + 35 = 214 ns. The minimum RAS PULSE WIDTH will be approximately two ciock periods - 5 ns (tRPDL-tRPDH for the DP8409-2) = 125 + 125 - 5 = 245 ns. At higher frequencies one generally wants to generate WRITE as the DP84432 does in order to guarantee that the CAS pulse width is great enough. The minimum CAS PULSE WIDTH will be approximately two clock periods - 70 ns (maximum tRICL-tRICH for the DP8409-2) = 125 + 125 - 70 = 180 ns. INTERPRETING THE DP84432 PAL EQUATIONS SUGGESTIONS The boolean equations for the DP84432 were written using the standard PALASMTM format. In other words the equation: "IF (VCC) RASIN = INCY.MODE.4D.DT" will mean; It is suggested that the DP8409A is to be used up to 8 MHz. Above 8 MHz one should use the DP8409-2 or the DP8419. Also fast PALs ("A" parts) should be used at 8 MHz and above. If very fast PALs are used ("B" parts) the access will be 10 ns faster than calculated in the above sections. These suggestions occur because of DRAM parameters that must be met, such as: The output "RASIN" (see pin list for DP84432) will be active low (inverted RASIN) when the output "INCY" is low (making INCY high) AND the output "MODE" is high AND the output "40" is low (making 40 high) AND the input DT/R is low (making DT/R high). 1) CAS ACCESS TIME-time from CAS valid until data is available at the DRAM outputs. 2) RAS PRECHARGE TIME-minimum amount of time from RAS high until RAS transitions low again. 3-56 PAL Boolean Equations PAL16R4A ;FAST PAL NEW PAL FOR INTEL PROCESSORS 8086, 8088, 80186, 80188 NATIONAL SEMICONDUCTOR (WORKS UP TO 10 MHz) CK CS RF10 ALE CLK DLYRD WAITWR DT WAITRD GND OE INCY INCYRF 4D 3D 2D MODE RASIN RDY VCC IF (VCC) RASIN = INCY*MODE*4D"DT*DLYRD*CLK+ CS*INCY"MODE"2DOWAITWR+ CS"INCyoINCYRFoALE"MODE03D"DT"CLK+ CS*INCY"MODE"2D"DT"WAITWR"CLK+ CS*INCY"MODE"2D+ RASIN"INCY*ALEoMODE"3D"4D+ RASIN*MODE"2D ;Start RASIN, early READ ;Start RASIN, early WRITE ;Start READ ;Late WRITE ;Hidden RFSH ;Continue RASIN ;Continue RASIN IF (VCC) INCYRF = ALE"MODE+ INCYRFoMODE+ INCYRF*4D*CLK ;Start INCYCLE in REFRESH ;Ccntinue INCY in REFRESH ;Continue INCY in REFRESH MODE"3D+ MODE*4D 2D := MODEo4D+ INCyoMODE"4D+ CS*DToWAITRD*INCY"MODE"2D*3D*4D+ CS'DT'WAITWR"INCY"MODE'2D"3D'4D ;Forced RFSH at beginning ot a cycle, during IDLE states, or during long accesses ot other devices ;Extend tor "CS READ" cycle ;Extend tor "CS WRITE" cycle 3D := 2D*4D 4D := 3D+ INCY*MODE+ INCY"MODE"2D IF (VCC) INCY = ALE"MODE+ INCY*INCYRF*MODE"3D*4D+ INCY"MODE*2D+ CS"INCYRF"MODE*2D"3D*4D+ CS*INCY"MODE"3D*4D"RDY ;Start INCY tor access ;Continue INCY during access ;End INCY during access ;Start INCY atter REFRESH ;Continue INCY atter REFRESH IF (CS) RDY = CS*INCYRF"2D*3Do4D+ ;Access at end ot RFSH cycle CS*RDY*MODE"2D"3D*4D+ ;Continue RDY atter RFSH CS"MODE+ ;Continue RDY atter RFSH CS*DT"WAITRD"INCY"MODE"2D"3D"4D+ ;WAIT tor "CS READ" CS"DT"WAITWR*INCY"MODE*2D*3Do4D ;WAIT tor 'CS WRITE" FIGURE 1. Equations for the DP84432 Standard Interface PAL (Works In Minimum or Maximum Mode) 3·57 w ('I) i r--------------------------------------------------------------------------, System Timing Diagrams 888610MHz Q R~CESS ( 0=1) n WRITE ACCESS HIDDEN REFRESH T3 T2 n T4 T2 T4 T3 n..n.. n- n-n.. rLn..n.. n ALE ADD/DATA I m K ~. ADDRESS) DATA IN } -- K ADDRESS }- DATA OUT RFI/O CLCK J LS U- J LS U- LS J DT/If ROY n J ~ IL n r I II IL- ~ II n I II II J U I r TUF/8399-3 3-58 System Timing Diagrams (Continued) WRITE CYCLE (WITH DELAYED WRITE & 1WAIT STATE) IIIMIWII=D T1 T2 READ ACCESS (DELAYED READ W/DNE WAIT STATE) TW T3 T1 T4 rL ~ll-L ru :-, L cs ALE ADD/DATA Ul k=s TW T3 T2 ll-L lLlL } k=~ DATA OUT T4 { DATAIN }- L RFI/O CLCK J UlLJU-U-Lr Lr U-U-U- DT/ii I J L ROY I I n I I II I U n I I I I Ii I I I I I I L- r L TLIF/8399-5 3·59 I System Timing Diagrams (Continued) Q FORCED REFRESH W/WRITE ACCESS n T2 T3 TW1 n..rLrL rL n..rL rL rL rL ALE ADD/DATA TW2 TW4 TW3 TW5 T4 UL K ADDRESS } DATA OUT L RFI/O CLCK U- U-U- U-U-U-U-U-U- OT/R ROY n I r I n I Il I IL I II I Ii II II II I I I I I 3-60 r TUF/8399-6 System Timing Diagrams (Continued) FDRCED REFRESH W/READ ACCESS AT END TI T3 T4 n-rLn-ILrLn-n-ILn.. TI TI TI T1 T2 TW n ALE 1 ADD/DATA ADDRESS " I \. ) DATA IN L RF I/D CLCK }- U-LrU- U U-U-U-.sU- DTin RDY n I I I n II II l n ~ I U II r I L~ I I I I r TL/F/8399-7 3-61 System Timing Diagrams (Continued) FORCED REFRESH Ti NDN-CS WRITE ACCESS TI 11 TI T3 12 T4 n-rI- lL lLn-ILrIJ ALE J ADD/DATA - ... ADDRESS DATA OUT L RFIID CLCK } U- U-U-U- U-LfU- DT/ft ROY 1 J n 'I 1 1 It W n 1 1 1 I I I 3·62 I I TlIF/8399-8 System Timing Diagrams (Continued) CS·WRITE ACCESS fORCED REfRESH WINON·CS WRITE ACCESS 11 ~ T2 T3 T4 Ti T1 T2 T3 T4 ruILrL rL rLn..rL rL l ALE ADD/DATA -< , \.. DATA OUT ADDRESS }- DATA OUT -{ ADDRESS Rf I/O CLCK J LSlSlS LrLr LSU- U- DT/R ROY I I n J I I I I I II I L- I J n I I • I TLiF/8399-9 3-63 .,... r-------------------------------------------------------------------------- ~ i Q ~National PRELIMINARY ~ Semiconductor DP84512 Dynamic RAM Controller Interface Circuit for the NS32332 General Description This is a PAL (Programmable Array Logic) device designed to allow an easy interface between the National Semiconductor NS32332 microprocessor and the National Semiconductor DP8417/18/19/28/29 dynamic RAM controller. This PAL supplies all the control signals needed to perform memory read, burst read, write, and refresh operations up to a frequency of 15 MHz. Features • Provides a 3-chip solution for the NS32332/DP8418 (or DP8428) dynamic RAM interface (1 PAL, DP8418 and clock divider) • Works with all speed versions of the NS32332 up to 15 MHz • Allows operation of NS32332 at 12 MHz with no WAIT states with standard 120 ns 256k or 1M DRAMs • Controls DP8417/18/19/28/29 mode 5 accesses and mode 0 forced refreshes automatically • Allows READ accesses in burst mode • CPU WAIT states are automatically inserted during contention between DRAM accesses and DRAM refreshes • Uses standard National Semiconductor PALs (Le., DMPAL16R4A, the user may want to use faster versions of these PALs at higher CPU operating frequencies) • The PAL programming equations are provided with comments for easy user modification to his specific requirements 3-64 C ~National PRELIMINARY "tI co "" (II ~ Semiconductor N N DP84522 Dynamic RAM Controller Interface Circuit for the 68020 CPU General Description This is a Programmable Array Logic (PAL®) device designed to allow an easy interface between the 68020 microprocessor and the National Semiconductor DP8417, DP8418, DP8419, DP8428 or DP8429 dynamic memory controllers. This PAL supplies all the control Signals needed to perform memory read, write, and refresh operations up to a frequency of 16.7 MHz. Features • Provides a 3 or 4 chip solution for the 68020/DP8418 (or DP8428) dynamic RAM interface (1 or 2 PALs, DP8418, and clock divider) • Works with all speed versions of the 68020 up to 16.7 MHz • Allows operation of 68020 at 12.5 MHz with 1 WAIT state with standard 120 ns 256k DRAMs • Controls DP8418/28 mode 5 accesses and mode 1 or o forced refreshes automatically • Allows memory interleaving if desired • CPU WAIT states are automatically inserted during contention between memory interleaving/DRAM accesses/ DRAM refreshes • Uses standard National Semiconductor PALs (i.e., DMPAL16R4A; the user may want to use faster versions of these PALs at higher CPU operating frequencies) • The PAL programming equations are provided with comments for easy user modification to his specific requirements Functional Description The following description applies only to the DP8418 or DP8428 since "RFIIO" going low initiates a mode 0 externally controlled forced refresh. This forced refresh resets the internal refresh request logic on the DP8418 or DP8428, but will not reset the internal logic on the DP8409A. A memory cycle starts when chip select (CS) and the address strobe (AS) become true. RASIN is supplied from the PALs to the DP8418 DRAM controller, which then supplies RAS to the selected RAS bank. After the necessary row address hold time, the DP8418 switches the address outputs to the column address. The DP8418 then supplies the required CAS Signal to the DRAM. The first PAL (PAL # 1) supports byte operations by producing four WRITE enables, one for each possible byte of the 32 bit word (upper, upper middle, lower middle, and lower write enable). These WRITE enables are produced externally from the 68020 "DATA STROBE" and "READ/WRITE" outputs. Since it is possible that all WRITE cycles may be LATE WRITE cycles ("WRITE ENABLE" occurring after "COLUMN ADDRESS STROBE") memory buffers should be used instead of transceivers to separate the data in from the data out of the DRAMs. The second PAL (PAL #2) supports byte operations by producing four COLUMN ADDRESS STROBES, one for each of the possible bytes of the 32-bit word. This PAL terminates the DP8418 "RASIN" input early but holds the DRAM data valid by latching the byte "CAS's" externally. This method of supporting byte writes allows transceivers to be used, or to directly connect the DRAM data in and data out pins to the 68020 data bus 110 pins. Hidden REFRESH cycles are not allowed in this set of PALs because of the need for adequate RAS precharge times in all circumstances and the desire not to be inserting WAIT states into access cycles of other system elements. These PALs perform externally controlled forced refreshes automatically (mode 0). A refresh cycle occurs when the DP8418 input RFCK transitions low and the RFIO signal goes low requesting a refresh cycle. The PAL responds by pulling RFSH low (M2 and MOl if there are no current DRAM accesses in progress. If a DRAM access is in progress the PAL waits until the current access is completed before performing the forced refresh cycle. If an access is requested during the forced refresh cycle WAIT states are automatically inserted into the access cycle until the refresh cycle is completed and adequate RAS precharge has been completed. The pending DRAM access cycle is then performed. The input signal "NOWAIT" allows one to vary the amount of time required to do a refresh (see the description of the "NOWAIT" input in the pin description section). In one of the timing diagrams the "RFSH" output was tied to the "NOWAIT" input to decrease the length of the refresh cycle but still insert one wait state in normal DRAM access cycles (see Figure 5). The first PAL (PAL #1) supports memory interleaving to guarantee adequate RAS precharge time during two consecutive accesses to the same DRAM bank. This is performed by looking at the lower address bit or bits, A2 and/or A3. If the processor is sequentially accessing the DRAM each RAS output will have plenty of precharge time. But if the system tries to access the same bank twice in a row the access will be delayed until adequate RAS precharge time has been met. During this time WAIT states will automatically be inserted into the pending access cycle. The second PAL (PAL #2) guarantees adequate RAS precharge time (one and one half system clock periods) by ending the DP8418 "RASIN" input early. The DRAM data is held valid by externally latching the DRAM "CAS" input as explained earlier. This has the additional benefit of sim- 3-65 Functional Description (Continued) The required DRAM "tRAC" (row access time) can be calculated from plifying the memory interface of the 68020 by eliminating the external components needed for interleaving, though as one approaches 16.7 MHz the interleaving circuitry may again become necessary to guarantee adequate "RAS" precharge time. For PAL # 1 an external "0 type" flip-flop or another PAL could be used for the support of memory interleaving. If one is not using memory interleaving (10 MHz or below) the "PREVO" input can be used for some other function and the equations of "RASIN" that employ "PREVO" can be adjusted. SO + S1 + S2 + S3 + SW1 + SW2 + S4 (minimum 1/2 period) - #1 - #2 - #4 - #5 = 40 + 40 + 40 + 40 + 40 + 40 + 35 - 95 - 20 - 7 - 10 = 143 ns The required DRAM "tCAC" (column access time) can be calculated from SO + S1 + S2 + S3 + SW1 + SW2 + S4 (minimum 1/2 period) - #1 - #3 - #4 - #5 = 40 + 40 +40 + 40 + 40 + 40 + 35 - 95 - 77 - 7 - 10 = 86 ns The PAL equations for this interface are written in the National Semiconductor PLANTM format, which differs from the standard PALASMTM format. The DRAMs selected for this system must satisfy both the "tRAC and tCAC" requirements. Therefore the DRAMs must have a "tRAC" (row access time) less then or equal to 143 ns and a "tCAC" (column access time) less than or equal to 86 ns to be used in this system, under worst case conditions, for a 1 WAIT state 12.5 MHz 68020 system. Common 120 ns 64k or 256k DRAMs meet this specification. If one is using PAL #2, producing external "CAS's" and not using any external transceivers he could possibly use 150 ns DRAMs in the above example. EXAMPLE: PLAN FORMAT lRASIN : = RFSH* 12D* lAS This translates as, "RASIN" is low after the rising edge of the input clock given that "RFSH" was high and "20" was low and "AS" was Iowa setup time before the clock transitions high (here RASIN, 20, and RFSH are outputs of the PAL and AS is an input). EXAMPLE: PALASM FORMAT RASIN : = If one is using PAL #2, the calculated "tRAC" and "tCAC" may differ from the actual system values, depending upon the external circuitry used to produce the byte "CAS's". The DP8418 "RASIN-CAS" low will be approximately 10-15 ns less than the value given in the data sheet because of the small loading on the DP8418 "CAS" output. The external circuitry needed to produce the byte "CAS's" should be loaded such that the column address (from DP8418) is valid when "CAS" goes low. For this reason "RASIN-byte CAS" may be longer than the value used in the "tRAC, tCAC" calculations, and therefore may give a smaller "tRAC, tCAC" than was calculated. IRFSH*2D* AS The above expression means the same as the PLAN format expression except it is written in PALASM format. In other words; "RASIN" will go low after the rising edge of the clock given that "RFSH" was high, "20" was low, and "AS" was low a setup time before the clock transitions high (here RASIN, 20, and RFSH are outputs of the PAL and AS is an input). Depending on the specific type of PALs and logic used the user can calculate the speed requirements for the DRAM at the specified processor frequency as follows: CALCULATION OF DRAM "tRAC" RAS ACCESS TIME AND "tCAC" CAS ACCESS TIME REQUIRED FOR A 12.5 MHz 68020, 1 WAIT STATE, MICROPROCESSOR SYSTEM #1) RASINgenerationtime = "SO" + "S1" + 1 combinational output delay of the PAL generating the "RASIN" output (assume DMPAL 16R49) = 80 ns + 15 ns = 95 ns maximum # 2) RASIN to RAS out delay of the DP8418 = 20 ns maximum (used to determine "tRAC") #3) RASIN to CAS out delay of the DP8418 DRAM contoller driving a load of 2 banks of 256k DRAMs, each bank containing 36 (32 DRAMs plus byte parity) = 72 DRAMs Since this is under the specified load in the data sheet (approximately 88 DRAMs) approximately 3 ns can be subtracted from the data sheet number, giving 80 ns 3 ns = 77 ns maximum (used to determine "tCAC") #4) 74AS244 buffer delay = 7 ns maximum 68020 PAL Inputs and Outputs (Pin number of the PAL on the left) PAL # 1 Inputs 1) "CK" This is the system clock. 2) "AS" 3) "RFRQ" 5) "R" Address strobe from 68020. This is the refresh request from the DP8418. This is the chip select (see system block diagram). READIWRITE output pin from the 68020. 6) "CLK" The system clock. 7) "PREVO" This output holds the previously accessed DRAM "RAS" bank. This input is the address bit "A2" and is used to determine which "RAS" bank the system is accessing. 4) "CS" 8) "90" 9) "NOWAIT" #5) Data setup time required from the falling edge of "S4" clock = 10 ns maximum A normal 12.5 MHz 68020 access cycle (with 1 WAIT state inserted) contains 4 clock periods of 80 ns per period. 3-66 This PAL always inserts one WAIT state into every 68020 access cycle. This input, 68020 PAL Inputs and Outputs (Continued) if low, allows the DRAM to be accessed with no wait states inserted into the access cycle. This input also, if low during a refresh, shortens the length of the refresh cycle by one clock period. This causes the RAS pulse width (during a refresh) and the RAS precharge time (after a refresh) to be shorter. 11)"OE" PAL # 1 Outputs 19) "XDlY" 18) "RASIN" 17) "RFSH" 16) "1DlY" This signal initiates a DRAM Refresh. A delay that is used internally. 15) "2DlY" 14) "RFREQ" A delay that is used internally. Refresh request (from the DP8418) synchronized to the system cloCk. This input synchronizes "RFREQ" to the falling edge of the input system clock "ClK" and is used in arbitrating between refreshes and accesses (see "RASIN" equations). This output goes to the 68020 "DSACKO, 1" data acknowledge input. This output allows WAIT states to be inserted into DRAM access cycles during access/refresh/RAS precharge contention. 13) "RFREQCK" This input enables the PAL outputs. This signal is used to guarantee one period of "RFSH" high to "RASIN" low time and to guarantee two periods of RAS precharge time in consecutive accesses to the same DRAM bank. This signal causes RAS (or RASs) to go low during a DRAM access or refresh. • 3-67 N N ~ f Q Interface PAL # 1 Boolean Equations This PAL will work up to 16.7 MHz with the 68020. This PAL uses mode 0 (MO = M1 = M2 = low) for doing externally controlled forced refreshes, guaranteeing more than 2.5 periods of RGCK RAS pulse width ("NOWAIT" = high). If "NOWAIT" is low the refresh is shortened by one clock period. This PAL will only work with the DP8417 /18/19/28/29 since it uses mode 0 to reset the RFSH request (RFIO) signal. DMPAL16R4A CK AS RFRQ CS R CLK JOE /DSACK /RFREQCK /RFREQ PREVO BO /2DLY /lDLY IF (VCC) /XDLY = RFSH*/2DLY*RASIN*PREVO*BO +RFSH*/2DLY*RASIN*/PREVO*/BO +/RFSH*lDLY*/2DLY*/RASIN*NOWAIT*/CLK +/RFSH*lDLY*2DLY*RASIN*RFREQ*/NOWAIT +/XDLY*/RFSH*RFREQ +/XDLY*RASIN*/AS*CLK /NOWAIT GND /RFSH /RASIN /XDLY VCC ;Same bank interleave ;Same bank interleave ;"/XDLY" low during RFSH ;"/XDLY" low during RFSH ;Hold "/XDLY" low ;Hold "/XDLY" low IF (VCC) /RASIN = /RFSH*RFREQ*/lDLY +/RASIN*/RFSH*/2DLY*XDLY +RFSH*RFREQCK*/AS*/CS*PREVO*/BO*CLK +RFSH*RFREQCK*/AS*/CS*/PREVO*BO*CLK +RFSH*RFREQCK*/AS*/CS*2DLY*XDLY*CLK +/RASIN*RFSH*/AS*/CS +/RASIN*/CLK ;RFSH "/RASIN" ;Hold "/RASIN" low ;Start "/RASIN" ;Start "/RASIN" ;After idle states ;Hold "/RASIN" low ;Hold "/RASIN" low IF (VCC) /RFREQCK = /RFREQ*/CLK +/RFREQCK*/RFREQ ;Start from falling clock edge IF (/CS) /DSACK = /CS*RFSH*/RASIN*NOWAIT*/CLK +/DSACK*/CS*RFSH*/RASIN*/AS +/CS*RFSH*/AS*/NOWAIT*XDLY /RFSH := /RFREQ*RASIN*/lDLY*/2DLY +/RFREQ*RASIN*lDLY +/RFSH*/RFREQ +/RFSH*/RASIN +/RFSH* /lDLY ;One WAIT state ;Hold "/DSACK" low ;No WAIT state in access ;Start RFSH ;Start RFSH ;Hold RFSH low ;Hold RFSH low ;Hold RFSH low /lDLY := /RFSH*2DLY*/RFREQ +/RFSH*/lDLY*2DLY*XDLY +RFSH*/RASIN ;Start "/lDLY" during RFSH ;Continue "/lDLY" during RFSH ;Start "/lDLY" during /RASIN /2DLY := /RFSH*/lDLY +/RFSH*2DLY*/RFREQ*/NOWAIT +RFSH*/RASIN*/lDLY +RFSH*/RASIN*/NOWAIT ;Start "/2DLY" during RFSH ;Shorten RFSH ;Start "/2DLY" during /RASIN ;Shorten access /RFREQ := /RFRQ ;Synchronize to system clock 3-68 --+ CD 0 ~D CHIP SELECT DECODE r • 10- FLIP FLOP CLK 0 - .... ADDRESS 0-31 68020 SIZO SIZI UUD,UMD, It.tD,UD OS VCC - PREY 0 RASIN BO RFSH I-- NOWAIT RFRO M2, MO = RFSH +--.J .c+ vee DSACK AS DSACKO <0 DSACKI AS h R ~ CK R/W t DATA 0-31 OS CAS 00-7,8,9 RASIN - CS ""m RG-7, 8, 9 CO-7, 8,9 BO,Bl Vr .... 68020 PAL CONTROLLER ~ CLK V" """ L. SYSTEt.t ClK OS 1 'II:: ..... DRAM MEMORY 8M BYTES 2- BANKS EACH BANK USING 32-36 DRAMS OJ CD :IE CD CD :l 36 IF USING BYTE PARITY m CD o N o WIN RGCK RFCK II) :l WRITE UUD DRIVERS (74AS240) AND SELECT LOGIC Q. WRITE UMD C -a WRITE LMD CD .1=>0 ..... WRITE LLD DATA IN CD DATA OUT ........ N CD R/W _ ~ RFCK CLOCK DIVIDER -a » r RFI/O ~ CLK CD CS ADS BYTE DATA SElEer GENERATOR LOGIC GATED WITH OS I I) () Ml_ RASO, 1 DP8409A/ 18/28 RAS2,3 Gro k. L.24 --... :l ~ CS~ .../ L ~ r-1 Q "" 15.6 !,S a ::::J c: WRITE BUFFERS 74AS244 L I READ BUFFERS 74AS244 I. . J' ENABLE ENABLE (I) e TLIF/8589-1 FIGURE 1. 68020 System Diagram for PAL # 1 (';(';!it8dO II C'I C'I It) 00:1' f c Interface PAL # 1 Between 68020 and DP8418/28 (Continued) vcc ClK XDlY AS ClK RFRQ CS AS 2 18 RASIN 3 17 RFSH cs 4 16 1DlY 5 OS PAL 68020 RASIN RFSH 1DlY 2DlY 15 2DlY ClK 6 14 RFREQ PREVO 7 13 RFREQCK BO 8 12 DSACK RFREQCK 11 DE DSACK NOWAIT NOWAIT XDlY RFRQ R BO 19 RFREQ OS ADDRESS ADDRESS(31 :0) DATA DATA(31 :0) « OE D -.............._ .. - TL/F/6569-2 FIGURE 2. PAL # 1 Simulation Diagram 3-70 C "'CI Interface PAL # 1 System Timing Diagram OCI ~ N N READ ADRESS Tl CLK INPUT Cs T2 TW T1 T3 T2 :L n.. n..r-L r-L n.. INPUT h As INPUT OS INPUT ADDRESS (31:0) DATA (31:0) WRITE ACCESS TO DIFFERENT BANK READ ACCESS (SAME BANK) nTWI TW2 T3 Tl n r 11 r 11 h rh I ....X - J. Tl I TW3 TW4 X 00001002 I X DATA XvvvvX DATA X vvvv X DATA I I I I - , II II I II IDLY r II I 2DLY I 1 I I I I rh I u PREVO INPUT I r IL- ~ rh I XDLY L ---1 r- - r L ~ I BO INPUT I I WIN ~ DSACK TW2 I RFREQ RASIN TWI r 11 RFRQ INPUT RFSH n- T2 n.. rt- n.. rt- n.. rL X00050000 -- R INPUT T3 J. X vvvv XDATA uuuu nTW I X 00000104 00000100 T2 ~ n.. rt. n.. ACCESS DURING REFRESH l I + I t I I 1 J I + II NOWAIT INPUT I + I -, '- x j I TLlF/B5B9-3 FIGURE 3 3-71 I Interface PAL #= 1 System Timing Diagram (Continued) Q REFRESH W/ 11 ClK INPUT cs 12 TW rt. r--Ln.. TW2 CS TW3 WRITE ACCESS TW4 TW5 rL rt-rt-rt- REFRESH W/ NON ru TW6 T3 TW7 T1 TI rL rL rL run.. AS OS INPUT ADDRESS (31:0) DATA (31:0) CS ACCESS T3 THEN TI h I I I J L~ X I X00123456 X DATA ~uuuu X 00000108 X T IuuuuI DATA ]luuuu R I INPUT RFRQ INPUT RFREQ WIN 1DlY 2DLY XDlY PREVO INPUT TW2 I I X 00001002 TW1 T2 rL rL rL rL rt- It I r-.l. CS ACCESS T1 I INPUT INPUT T2 ,- I ...J -, I J I I II I -r I 1 ~~ II II II I I I :r1 I II rt. w I I II I L I L~ I - L I I I BO INPUT ,, , , , , I WIN DSACK ~ I I NOWAIT INPUT '--____----..J' l,....J t L t I ,, L~ ACCESS WAIT STATE 6 WAIT STATES MAX DURING REFRESH (WITH NOWAIT HIGH) TLIF/BSB9-4 FIGURE 4 3·72 Interface PAL # 1 System Timing Diagram REFRESH PAL #1 ClK INPUT T2 T1 TW WI CS WRITE ACCESS TW3 TW5 TW2 TW4 REFRESH WINON TW6 As OS INPUT ADDRESS (31:0) DATA (31:0) T3 rL rt. rt-rt- rt. rt-rt-rt- CS INPUT INPUT (Continued) TI n- n... TI T1 T2 n- rt. L CS ACCESS THEN CS ACCESS TI T2 TW1 T3 T1 I II I I I I I I X I X 00123456 X 00000108 X T I X DATA Xuuuu ~ I L~ -- X 00001002 .....XuuuuX -L. DATA Xuuuu R INPUT I RFRQ INPUT I - - ~ RASIN J 1DlY - XDlY I , h RFSH r--h RFREQ 2DlY TW2 rt. rt. rt. rt- ~ n.. I I ., I I I I II I ""L ~ I L~ L L I I I r~ I II II r LJ II I ~ I I I f-J I I PREVO INPUT BO INPUT WIN I ~ DSACK NOWAIT INPUT ~ ~ ~ ~ J - h ~ , L---I I ~ J I ~ L ..L I ' - - _ _ _ _ _- _ - J I t'--__ ACCESS WAIT STATE 5 WAIT STATES MAX DURING REFRESH (WITH NOWAIl lOW) TLlF/8589-5 FIGURE 5 • 3-73 N N ..,. II) ,--------------------------------------------------------------------------, Interface PAL # 1 System Timing Diagram f c REFRESH W/ NON CS ACCESS THEN CS READ ACCESS T1 ClK INPUT CS INPUT AS INPUT OS INPUT ADDRESS (31 :0) T2 T3 TI T1 • T3 T1 L~ - X 00001002 X 00123456 I T1 T2 T3 uuuuX DATA Xuuuu X DATA r. I q. . .J X 00050000 X 00060000 I I X uuuu X DATA XuuuuX DATA . - - ..... - - - I I X uvuuuuuu I Xuuuu I f-J r--~ I I r I I I L I XDlY I h rl r, I J I I I L ~ U PREVO INPUT I BO INPUT DSACK T3 r. r. I X h r-- h RASIN r-- h 1DlY WIN T2 I I RFSH 2DlY TW2 NON CS WRITE ACCESS I -.J R INPUT RFREQ TW1 READ ACCESS NO WAIT STATES ILh-n... n...h-n... n... n...h-n... n... n...h-h-rL ru n... rL DATA (31:0) RFRQ INPUT T2 (Continued) I L~ J L . .J t I r t t NOWAIT INPUT TL/F/8589-6 FIGURES 3-74 Interface PAL #2 Boolean Equations This PAL is similar to PAL # 1 but ends "RASIN" one half period earlier than PAL # 1 and relies on the external generation of byte "CAS's" to hold the data valid during 68020 READ access cycles. DMPAL16R4A CK /AS /RFRQ /CS R CLK NCl NC2 /NOWAIT GND /OE /DSACK /RFREQCK /RFREQ /2DLY /lDLY /RFSH /RASIN = IF (VCC) /XDLY RFSH'/2DLY'/AS +/RFSH*lDLY'/2DLY*/RASIN'NOWAIT*/CLK +/RFSH*lDLY*2DLY*RASIN*RFREQ'/NOWAIT +/RFSH'/XDLY*RFREQ +/XDLY*RASIN*/AS'CLK IF (VCC) /RASIN = /RFSH*RFREQ*/lDLY +/RFSH'/RASIN'/2DLY'XDLY +/RFSH'/RASIN*/CLK +RFSH'RFREQCK'/AS'/CS'XDLY*CLK +RFSH'RFREQCK'/AS'/CS*2DLY*XDLY*CLK +RFSH*/RASIN*/AS*/CS*XDLY +RFSH'/RASIN'CLK = IF (VCC) /RFREQCK /RFREQ*/CLK +/RFREQCK*/RFREQ VCC ;"/XDLY" during access ;"/XDLY" during RFSH ;"/XDLY" during RFSH ;Hold "/XDLY" low ;Hold "/XDLY" low ;RFSH "/RASIN" ;Hold in RFSH ;Hold in RFSH ;Start "/RASIN" ;After idle states ;Hold "/RASIN" low ;Hold "/RASIN" low ;Start from falling clock edge IF (VCC) /DSACK = /CS*RFSH*/RASIN*NOWAIT*/CLK +/DSACK* /CS*RFSH* /RASIN* /AS +/CS'RFSH*/AS*/NOWAIT'XDLY /RFSH := /RFREQ'RASIN'/lDLY*/2DLY +/RFREQ'RASIN*lDLY +/RFSH*/RFREQ +/RFSH'/RASIN +/RFSH'/lDLY /XDLY ;One WAIT state ;Hold "/DSACK" low ;No WAIT state in access ;Start RFSH ;Start RFSH ;Hold RFSH low ;Hold RFSH low ;Hold RFSH low /lDLY := /RFSH'2DLY'/RFREQ +/RFSH'/lDLY*2DLY*XDLY +RFSH*/RASIN ;Start "/lDLY" during RFSH ;Continue "/lDLY" during RFSH ;Start "/lDLY" during /RASIN /2DLY := /RFSH*/lDLY +/RFSH'2DLY'/RFREQ*/NOWAIT +RFSH*/RASIN'/lDLY +RFSH*/RASIN*/NOWAIT ;Start "/2DLY" during RFSH ;Shorten RFSH ;Start "/2DLY" during /RASIN ;Shorten access /RFREQ := /RFRQ ;Synchronize to system clock • 3-75 DP84522 ~D ~ DPB409A/ rTr::r~~~~~i---1r-----------------..:sj ~B/2B RASO, 1 CS ~ .~ 1----.1 "'; = ~ As DSACKO c.:> '" DATA 0-31 OS RASIN t---. UUD, Ut.!D, LMD,LLD r .:., WE ______-1 WIN SIZI I VCC~NOWAIT , cs II ~r RfSH QO-7,B,9 tJ 1 ·1 ~~~:O = RfSH I - :::. ~ ClK ~ D DS::......___ L..._ _ _ _ _ _ _ _ _ _ _ _ _..:: » r- DRAt.! MEMORY BM BYTES 2- BANKS EACH BANK USING 32-36 DRAMS 36 If USING BYTE PARITY 'II::: I\) C» CI) oI\) o ~ ~ CD RfCK -+_-+-_---J,::=j R/W cs CAS RGCK CAS DRIVERS, (74AS1036A) ~_ _ SELEer LOGIC • " AND t----+---1I--~ LATCHES 68020 -..,.........,.. CLOCK DIVIDER CD 3 oji)" CAS DSACK R I J; AS I I--'WIr-+I I--'WIr-+I .1 RASIN RFRQ () ." RAS2 3 VCC 6B020 I» ~ ' RO-7,B,9 CO-7,B,9 SIZ0r--+l ::::l Ml- CHIP SELECT DECODE r-:;)RESS 0-31 ::s CD ; OIR I ENABLE CAS UUo co CAS UMO il CAS LMD 3 CAS LLD DATA IN • DATA OUT I DATA OUT TRANSCEIVERS 74AS2~A DATA IN I ~ I TLIF/8589-7 FIGURE 7 Interface PAL #2 CAS Driver, Select Logic, and Latches TL/F/8589-8 FIGURE 8 • 3·77 I Interface PAL #268020 System Timing Diagram Q READ ACCESS T1 ClK INPUT T2 TW READ ACCESS(SAWE BANK) Tl T3 T2 TW WRITE ACCESS (DIFFERENT BANK) T3 T2 T1 TI TW REFRESH(SEE NEXT PAGE) T3 T1 INPUT AS r II r II h os h INPUT ADDRESS (31:0) DATA (31:0) - X 00000100 I I X 00000104 I X 00001002 DATAI uuuu .L I DATA Iuuuu X DATA I I I RFREQ II RFSH ~ , II I I lDlY II 2DlY IL~ L XDlY ~ HOWAIT INPUT TW4 I T .1 XDATA X uuuu I RFRQ INPUT DSACK TW3 .., X 00050000 X .1 uuuu r I R INPUT RASIH TW2 n... rLrt-rt. rt. rL rL rL rL rt. rLrt-rt. L..rw rL rL rL rL cs h INPUT TWl T2 I • I I I I I I • I + t r0- II L I r I LJ L Ir I I L J ~ I I I + • • .L T TL/F/8589-9 FIGURE 9 3-78 C ." Interface PAL #2 Between 68020 and DP8418 (Continued) T1 ClK INPUT T2 TWl TW2 ~ rL rL rL CS INPUT AS INPUT OS INPUT ADDRESS (31:0) DATA (31:0) TW3 TW4 TW5 TW6 TW7 T3 ~ REF RES H WI NON CS ACCESS THEN CS ACCESS TI REFRESH W/CS WRITE ACCESS 00 TI T2 T1 T3 RFSH h I I I I L~ I I I "lc 00001002 X 00123456 X I DATA X DATA Xuuuu X 00000108 X J( uuuu I ,- I --I I I II -n ~ .I lDlY ~ II 2DlY ~ II t t I I I II t LJ t t I J I I I t I I XDlY ~ I II RASIN DSACK TW2 I INPUT RFREO TWl ILrLru rlJ rL IL ILruIL ILIL IL ru rlJ n. R RFRO INPUT T2 T1 TI I r:....LJluuuuJl .. Q) M2 1.11 RASO DP8409A/19/29_ RASI CS RAS2 VCC ill4 N 11-=- Lo[) "- DEN_ CS '- I DT/R - ~ I ENABLE WRITE BUFFERS 74AS244 ENABLE I ·Drivers may not be needed depending on the load being driven. READ BUFFERS 74AS244 I J L.. r" TLlF/8590-1 FIGURE 1 ~£St8da 80286 System Diagram (Continued) 74AS04 ..- ,;.;;;.;. CLK ~ CS 802 84 ClOCK OUTPUT ~EQ VCC !!!:!'" =-~EQ 20 --= = =RASIN ~ ~Q !::"" -ClK 1 19 CYREQ ;2.. CS 2 18 RFREQ ~ RFRQ 3 17 RASIN SO 4 16 RFSH 51 5 15 IDLY ALE -51 ~ - II PAL 80286 #1 6 14 2DlY __--2.. 13 SYNRDY PRECH 8 12 WRITE 9 11 OE - RFSH !E!;.Y I =2DlY -V SYNRD ~E - 10 - VCC --H ~C 20 DDAO - - ~ ADDRESS ADDRESS(23:0) DATA DATA(15:0) D ALE 1 eo 2 81 3 19 PREVI 15 PREV2 6 14 PREV3 7 13 WINLOW AO 8 12 WINHIGH BHE 9 11 OE 4 IDLY 5 RFSH WRITE » =~ 18 ---17 PREVO 16 RASIN = o ~ PRECH PAL 80286 #2 - I, = --2 !!,EV = PREV3 WINlOW ~HI GH - 10 1 - ~ - FIGURE 2. 80286 PALs 3·88 TL/F/8590-2 System Timing Diagram READ ACCESS (BANK 0) -ur TC TS ALE DATA (15:0) SO·SI I CYREQ ( RFSH ~ RASIN I I ---, r X ~0108 I I I I / ~ I I I I I I I J rh I ". ! 0110 I _\ 'I X uuuuuu X0010020 L ( I I ----r / ( I (I I \1 PREYI PRECH rutr-u-t. ru-u-u-u-t. I) I 2DLY TC TS X001000C Xuu uuu I I IDLY PREYO XOO0102 / RFREQ ~ru-L -Je z Co) o CO Ds--~~r-------f1~-r====~31~ S04 (41 CASH (BANK 0) (7) CAsH (BANK1) "'"--'-~ (9) CAsL (BANKO) AD (12) CASL (BANK1) B/\ii---------+-., . . ...,-~I ·~ ..... CAS----------~~--~ TLiF/5040-3 FIGURE 2b. CASH and CASL Decoder When the processor is in either halt state (by executing the privileged HALT instruction) or single-stepping mode (when STOP) input is low), it introduces memory refresh cycles. However, care should be taken when the CPU is in either a WAIT state or a Bus Acknowledge cycle, that the dynamic RAM refresh will not take place. If these conditions occur over a long period of time, a burst refresh is recommended. This can be done by toggling RASIN while keeping M2 low, until all the rows of the dynamic RAM have been refreshed, then the CPU can resume its operations. Row to Column Select and then CAS output will automatically follow RASIN as determined by the Auto Access modes of the DP8408A. The RD line also goes active to indicate a memory read cycle is in progress. After tCAC (access time from CAS), read data becomes valid. This data is sampled on the rising edge of T3, then both MREQ and RD go inactive. Immediately following this, RFSH goes low, putting the DP8408A in the Externally Controlled Refresh mode. The MREQ goes active causing all four RAS outputs to go active to perform a refresh to all the banks of the dynamic RAMs. Note that during memory refresh cycles, the refresh address from the CPU is output on the address bus. However, the contents of the DP8408A on-chip refresh counter are used instead to provide the row address to the dynamic memory array. Since the Z80 provides only a 7-bit refresh address, it is an advantage to use the DP8408A 8-bit refresh counter to support 64k dynamic RAMs directly. The DP8408A refresh counter is incremented as MREQ returns high, ending the memory refresh. The RFSH goes inactive returning the DP8408A back to the Auto Access mode, preparing it for the next access cycle. The DP8408A and Z80A® Interface INSTRUCTION FETCH CYCLE Figure 5 shows the detailed interconnections between the DP8408A, the Z80 and the Dynamic RAMs. Figure 6 shows the timing during an M1 cycle (op code fetch). The program counter is output on the address bus at the beginning of the M1 cycle. One-half clock later MREQ goes active. This input is used to provide RASIN to the DP8408A to access the dynamic memory. Subsequently, the selected RAS output, II 3-95 T2 T3 I I DATA OUT COLUMN ADDRESS ~ _ _--i-_+-I 4 - - t C A C ·1 TL/F/5040-4 FIGURE 3. Memory Transaction Cycies 3-96 T2 T1 TJ -.J CLOCK I n I ~ I OP8408A REFRESH COUNTER INCREMENTS MRED I I Ii! SAME AS PREVIOUS CYCLE RIW STJ(RFSH) RASO·3 DP8408A REFRESH COUNTER 00·7 CAS mDi TLiF15040-5 FIGURE 4. Memory Refresh Cycle ADDRESS BUS I '" AO-15 '" r--- r- RO·B,7 00-6,7 CO-6,7 AO-6,7 r--- CS ADDRESS DECODER '--- 4 BO B1 VCc-y: RIC ZBOA SEE TABLE BELOW I:: RFSH ~ MRE1I ~ mO·3 - OP8408A miN CAS MO M1 -. ~ m CAS MEMORY M2 ADS RASIN WIN I I WE III WE SOD WAIT 00·7 iili Wii L. -. 00-7 DATA BUS 1" Soil I MO M1 I MODE 5 1 0 I MODE 6 I 0 1 TLiF15040-6 FIGURE 5. DP8408A and Z80A Interface 3·97 I- -.J AO-15 ==xI I ~ ~ co i!! Ml CYCLE Tl T2 I I laO PROGRAM COUNTER "I- T3 REFRESH PERFORMED EVERY OPCOOE FETCH I I I X I Mimi I T4 I -I I I I >C DP840aA REFRESH ADDRESS INCREMENTS I I lIIJ I I I I I NO WAIT STATE IS NECESSARY mil WAIT 00-7 I I I I RASO-3 I 00-7 CAS (74500) TL/F/5040-7 FIGURE 6. Z80A Op Code Fetch Cycle Showing Memory Refresh 3-98 l> MEMORY ACCESS CYCLE gram mer can move any block of data from the location pointed to by the D and E registers. This operation is repeated until the byte counter (B and C registers) reaches zero. Thus, this single instruction can move any block of data from one location to any other. Due to the fact that this instruction is refetched after each data byte transfer, the memory refresh cycle always takes place even though a transfer of up to 64k bytes of data may be performed. Furthermore, when the CPU has executed the software HALT instruction and is waiting for an interrupt before normal CPU operations can resume, the CPU executes Nap instructions to maintain memory refresh activity. Figure 7 shows the timing of the memory read and memory write cycle other than for the M1 op code fetch cycle. Similar to the op code fetch cycle, MREQ is used to provide RASIN. MREQ goes active aiter the address to the memory has had time to stabilize. Again, RAS output, Row to Column Select and then CAS output will automatically follow RASIN to access the specified memory location. For a memory read cycle, both MREQ and RD go active, and as a result, WIN remains high (refer to Figure 6), which allows a memory read operation to occur. On the other hand, only MREQ goes active during a write cycle, which forces WIN low, indicating an early write cycle. It should be noted that the CAS output to the memory array will not go low until WR goes low during memory write cycles as this guarantees the valid CPU data will be written into memory. However, care should be taken when the CPU is in either WAIT state or a Bus Acknowledge cycle, the dynamic RAM refresh will not take place. If these conditions occur long enough, a burst refresh is recommended, and it can be done by toggling RASIN while keeping M2 low until all the rows of the dynamic RAM have been refreshed before the CPU can resume its operation. zao It is worth mentioning that the CPU provides powerful block transfer instructions. An example is the LDIR (load, increment and repeat); using only this instruction, the proT1 T3 12 12 T1 T3 CLOCK I I =========:====M=EM=O'=Y=AO=O'=ES=S:===========:)(~ ________~___M_EM_O_RY_AO_O'_ES_S~__________~><=== I 1 M.m I 11i \VIi 1iIl mil WilT I I I I I I 00-7 I m I QO-7 \W (MR) - tRICl tCASOlY - tS4>(D) min. tRP: tw(MRH)=tw(cpH) + tf - 20 min. tRAS: tw(MRl) - 20=tc - 50 Dynamic RAM Parameters: tCAC: access time from CAS To perform automatic forced refresh, the DP8409A must receive two clock signals: the refresh period clock, RFCK, and RGCK, the RAS-generator clock; RGCK can be the microprocessor clock. It takes approximately four RGCK clock periods to perform this automatic forced refresh. The DP8409A gives preference to hidden refresh using RFCK as a level reference. The refresh time slot commences as RFCK goes high. If CS goes high while RFCK is high, the refresh counter is enabled in the address outputs. All four RAS outputs follow RASIN; so to perform a hidden refresh, RASIN must be set low and the refresh counter gets incremented as RASIN goes high. The DP8409A allows only one such hidden refresh to occur with a clock cycle of RFCK to minimize power consumption. tRP: RAS precharge time tRAS: RAS pulse width Z80 Parameters: tc: clock period tw(cpH): clock pulse width, clock high tf: clock fall time tOl4>(MR): MREQ delay from falling edge of clock, MREQ low tS4>(D): Data set up time to rising edge of clock during M1 cycle DP8408A and 74S00 Parameters: tRICl: RASIN to CAS output delay If a hidden refresh does not occur the DP8409A must force a refresh before RFCK begins a new cycle on a low-to-high transition. Therefore, as RFCK goes low (and a hidden refresh has not occurred), RF I/O (Refresh Request) goes low, requesting that a refresh be performed. When the system acknowledges the request, it sets M2 low, and prevents further access to the DP8409A. Then two RGCK negative edges after M2 has gone low, all four RAS outputs go low and remain low for two RGCK clock periods. After all four RAS outputs have gone low, M2 can go high any time to end the Automatic Forced Refresh. The DP8409A allows only one automatic refresh to occur within a clock cycle of RFCK. tCASOlY: propagation delay of the two 74S00 NAND gates For example, if the Z80A (4 MHz) and the DP8408A are used, then: max. tCAC: 1.5(250) - 85 - 132 - 13 - 50 = 95 ns min. tRP: 110 + 20 - 20 = 110 ns min. tRAS: tc - 50 = 200 ns tRIClmax. (mode 6): 132 ns at 15 pF load tCASDlY max.: 13 ns at 50 pF load Therefore, in this case, the designer should choose a dynamic memory which has maximum tCAC of 95 ns, minimum tRP of 110 ns and minimum tRAS of 200 ns. MEMORY ACCESS The MC68B09E starts a memory access cycle when E goes low, then the memory address becomes valid on the Address Bus AO-15. This address is decoded to provide Chip Select (CS) to the DP8409A. Then Q goes high and sets RASIN low from the PAl® Control logic as shown in Figure 12. Note that CS must go low for a minimum of 10 ns before the assertion of RASIN for a proper memory access. This is important because a false hidden refresh may take place when this 10 ns minimum setup time is not met. RASIN goes low initiating the auto access sequence as shown in Figure 1. Mode 5 guarantees a 30 ns minimum for row address hold time and a minimum of 8 ns column address set up time. RASIN remains low until E goes low at the end of the current access cycle. Using the 16R6A Programmable Array logic (25 ns PAL), the maximum access time from CAS of the selected dynamic RAM is determined as follows: DP8409A and MC68B09E Interface DP8409A OVERVIEW The DP8409A Dynamic RAM Controller/Driver is designed to control all multiplexed-address dynamic RAMs. It consists of two 9-bit address latches and a 9-bit refresh counter, thus allowing control of all 16k, 64k, and the coming generation 256k dynamic RAMs. More important, all the DP8409A outputs are capable of driving 500 pF loads. The DP8409A basically has eight modes of operation: Externally Controlled Refresh, Automatic Forced Refresh, Internal Auto Burst Refresh, All RAS Auto Write, Externally Controlled Access, Auto Access (slow tRAH and with hidden refresh), Fast Auto Access (fast tRAH) and Set End of Count. Of all these modes, Auto Access (mode 5) and Auto Forced Refresh (mode 1) are the most popular and will be used throughout this application. Mode 5 requires only RASIN to initiate a memory access cycle, because all the Max. tCAC: 3X125-25-160-40=150 ns 8409A tCAC: 3x125-25-130-40=180 ns 8409A-2 Q high to E low: 3 x 125 ns (8 MHz clock) = 375 ns 3-100 Q high to However, if no hidden refresh occurs while RFCK was high, RF 110 goes low immediately after the RFCK high-to-Iow transition requests a forced refresh. The PAL Control Logic samples RF 110, when E and Q are high and low respectively, to set M2 (RFSH) low, as shown in Figure 13. Once M2 has gone low, a forced refresh automatically occurs (as described in the DP8409A Overview). M2 remains low for four system clock periods to allow for this forced refresh. If the current microprocessor cycle is a nondynamic memory cycle (CS is high), this refresh is transparent to the microprocessor and STRETCH remains high (E and Q are not stretched). Nevertheless, if the current cycle is a dynamiC memory access cycle, STRETCH goes low stretching E and Q for a maximum of four system Clocks. RASI N for the pending access will be issued a full system clock after M2 has gone high; this is to allow some RAS precharge time for the dynamic RAM. After this, memory will be accessed in the manner as described in the Memory Access Cycle. RASIN low: 25 ns (16R6 A PAL Parameter) RASIN to CAS Output low: 160 ns (DP8409A's tRICl, Mode 5, at 500 pF load) 130 ns (DP8409A-2's tRICd Read data setup time (before E going low): 40 ns MEMORY REFRESH As described above, RASIN goes active when Q andlor E are high. This scheme, therefore, maximizes chances for hidden refresh because CS is high during nondynamic memory cycle. For example, when the CPU is executing internal operation or the CPU is accessing ROM or 110, CS is high during these times. The DP8409A therefore performs a hidden refresh as RASIN goes low, assuming that RFCK is high. I MODE 5 1 MO [ Ml ... WAIT RFSH 0 I MODE 6 1 1.- r- 01-- D lS74 ClK t- r.-I> NSC800 ClR -- MO Ml M2 ~ iiD r r--ADDRESS DECODER RASIN WiN CS l t CO-7 BO Bl ADS CAS CAS mO-3 ALE ADO-7 lSD4 DP84D8A ~ A8-1S ~ VCCL: CASIN RIC Q~ VCC Wii 0 1 WE 00-7 4 RAS MEMORY WE AO-7 ..,.. RO-7 DIN AND DOUT t TL/F/5040-9 FIGURE S. NSCSOO and DPS40SA Interface 3-101 • ClK -tJ1 1 AU AS-15 TI T2 1 I I 1 I + I I II I 14 T3 11--1+-1-~I---+-'1 ADDRESS VALID 1 ! . .,--+-1----' A~~~~:S)--I M TW ! h I) ~I I D "-----I) 1I 1I ~'----!-lb+--REfR-E~~c.m-RESS+ . - - --+-" 1".",.1,...-0~+-I _--++-_ ---+---<1 WD I 1 1 I~ I I Tl/F/5040-10 FIGURE 9. NSC800 Op Code Fetch Cycle Showing Memory Refresh 3-102 T1 TW " » z T3 , Co) leLK ALE o lr--l \ 1 CD I~I----~----~--~---- NB-15 MO-7 ADDRESS VALID DATAOUT VAllO -,----' iii! I I \ \ ~ I I I I I I J I I 1 1 I I 1 1 /)1 I~ I ·l I I I I (,I i ~II I "I I COLUMN ADDRESS "'+-' ( I tl I It I I I. 1 ROW ADDRESS ~ I I II i / I TL/F/5040-11 FIGURE 10. NSC800 Memory Write Cycle I ADDRESS BUS AO-15 DECODER 680Q a &8B09E I r- - lSD' ..... CS ilE E M2 I : STRETCH * VCC- F 80 81 RFI/O RO-7 ADS RAS1N M2 M1 MO DPM09A 8 WiN 00-1 RGCK BMHz SYSTEM CLOCK L....c - ~ J ClR 0 --A- lS16 ClK lS16 ClK --c ..,K PRE RASO-3 ~ J PRE 0 '- I> i:3 ~ CAS WE fo++ AO-l ::::: RAS - MEMORY CAS WE RFCK iir-- KCLR ii - '-r J CO-7 lSO'..... lSO.... l"'lso, 8 PAL 1686 I .... 1 RASIN '·1 R/iii 00-1 5V 0 .A E ... -k~ L= 5V fS '--Vcc DIN AND OOUT 1 8 O'TABUS TL/F/SD40-12 FIGURE 11. MC68B09E and DP8409A Interface 3-103 8MHz CLOCK I - I I I I 1 ,.., I I I I II '+ I I ~~ I I I I I I I I I Q I) R/W +- I X AO-15 ·cs I I I I DO-7 :::::> I I I I I I I "r SELECTED iiAS I )( I I I -~ I ADDRESS VALID I I QO-7 I II I RASO-3 I I I COLUMN ADDRESS ROW ADDRESS I + ,-+"1 I I I I I I I L___________________________________ I.. ICAC-I-.·I I toFF"I~ MEMORY (",_..:O::;:At.::.,A¥::::AU:::D_-J) TLIF/5040-13 'If OS 18 high Ihroughoullhls cycte (RFOK 18 also high), hidden refresh occurs Inslead of a memory access. FIGURE 12. MeSSSD;E Memory Read Cycle 3-104 IMHz CLOC'~~ 1., L.I RIW "0-15 I! ~ !-/ - cs 'I I ,/Ii .- ADDRESS VAUD RASIN M2tliffiil ~ a 1\ ~ I Hiif 2DLY 01 ') Sl1iEffiI '" m~ ....., , ALL W'I , SELECTED AAS t 00-7 REFRESH ADDRESS COLUMN ADDRESS CAS ..... WE II; RFIIO (RFRO) 00-7 - ~ IOFf-1 i----ICAC .1- I I- MEMORY DATA VALID I TLlF/5040-14 FIGURE 13. MC68B09E Forced Refresh and Memory Read Cycle 60t-NY iii PAL16R6A User Part '" 6809/8409A Interface PAL National Semiconductor CK E Q RFIO /CS /WAIT RW A B GND /OE CD/STRETCH /3DLY /2DLY /lDLY /M2 /RASIN VCC I f (VCC) RASIN= CS'E*/M2*/lDLY + CS*Q*/M2 M2: = E*/RFIO*/Q + M2*/3DLY lDLY:=M2 2DLY:=lDLY 3DLY:= 2DLY STRETCH: = CS*2DLY'E + CS'WAIT*E*Q*RW ;DESCRIPTION: ;The above equations are written in standard PALASMrM format. ;Also included in the logic is a nn/WAIT"" (active low) input. This ;input will allow the insertion of one WAIT state in a READ ;access cycle if it is tied low. If WAIT states are wanted in ;both READ and WRITE access cycles the ··Rwn. input in the STRETCH ;equation should be deleted. ;The user should make sure that CS is valid at the DP8409A input a ;minimum of 30 ns before RASIN is valid. If the user does not ;care about the HIDDEN REFRESH feature of the DP8409A, CS can be ;tied permanently low. In this configuration the RASIN term can ;transition whenever is convenient. Dual-In-Line Package CK- 1 ......, E- 2 Q- 3 RnO - 4 CS-S WAIT - 6 RW - 7 6809 PAL® r- 19 f- 16 ~2iiLY ~ 3DLY f- STRETCH 13 12 - 10 Vee WIN 18 ~i.i2 17 f- IDlY INTERFACE 15 14 NC 8 Ne- 9 GND - 20 11 Ne Ne -iiE TUF/5040-15 TopV1ew 3-106 DP8400/8419 Error Correcting Dynamic RAM Memory System for the Series 32000® National Semiconductor Application Note 387 Webster (Rusty) Meier INTRODUCTION Three PAL's® (Programmable Array Logic devices) were used in this application in order to interface between the NS32016, DP8419 and the DP8400 to produce an error correcting memory system for the Series 32000 microprocessor family. The PAL Interface Controller (hereafter referred to as P.LC.) takes care of all interfacing logic, no extra control logic is needed. • FEATURES • The P.LC. controls the following types of cycles: A) READ cycles with no errors detected, ALWAYS CORRECT MODE (1 WAIT state inserted). B) READ cycles with single error detected, the correct data will be written back to memory and given to the CPU. One WAIT state is inserted into the READ cycle and one WAIT state is inserted into the next access cycle (and the access is delayed) if it immediately follows the READ cycle. C) READ cycles with more then one error detected. In this case the processor is interrupted and appropriate action can be taken. D) WRITE cycles (no WAIT states). E) BYTE WRITE cycles, or READ MODIFY WRITE cycles (3 WAIT states inserted). If more then one error is detected in the READ portion of this cycle the processor will be interrupted so appropriate action can be taken. F) DRAM REFRESH cycles (may cause a maximum of 5 WAIT states to be inserted into an access cycle if the access occurs while the refresh is taking place). • All single bit errors are automatically corrected and rewritten back to memory. • All double bit errors are detected and cause a system interrupt. • Can directly drive up to 2M bytes of Dynamic RAM (4 banks of 22 256k DRAMS, each bank being 16 data bits plus 6 check bits). • The P.LC. allows full use of the DP8400 and all its modes of operation, including: A) The DIAGNOSTIC modes (can do a diagnostic test of the DP8400 without needing to use external memory). B) The COMPLEMENT modes (useful for doing the DOUBLE COMPLEMENT METHOD to try to correct 2 errors). • The P.I.C. interfaces between the DP8409A or DP8419 Dynamic RAM controller, the DP8400 Expandable Error Checker and Corrector, the NS32016 processor, the NS32201 Timing Control Unit, and the NS32082 Memory Management Unit (if used in the system). • Provides outputs to interrupt the CPU and to insert WAIT states if needed. • » z I W CD ...... This interface uses PAL's whose equations and timing are given, allowing the user to customize the interface to his own requirements (even a different processor family) if he so desires. Can work at 10 MHz (using the new DP8419, DP8400-2, and common 120 ns 64k DRAMs). Operation at higher frequencies is possible. DESCRIPTION The P.LC. consists of 3 PAL's and one 74LS164 parallel output serial shift register (see P.LC. logic diagram). If greater speed is needed for the shift register (CPU clock speed is over 6 MHz) one could use some similar type of shift register in a faster type of logiC ("AS, ALS, F"), or could make one out of D flip-flops (74AS174). If one is using a CPU other then the Series 32000 and does not have a fast clock (FCLK, twice system clock frequency) he could substitute a 5 or 10 tap delay line for the shift register. The P.I.C. uses a shift register as an aid in determining the state of the CPU and where it is in an access cycle. When either of the two outputs, "RASIN" or "RFSH", go true the shift register is enabled and begins producing a series of delays. These delays, along with specific signals from the CPU, are used in the interface to determine the state of the CPU and create the appropriate control signals for the DP8400, the DP8409A1DP8419, and the processor. Other CPUs should be able to customize this interface to their requirements by adjusting the appropriate equations. The logic in the upper right hand corner of the P.I.C. logiC diagram may not be needed (74LS374's, 74LS244, 74LS240's LED's and several SSI gates). The logic allows the latching of the DRAM bank (BA 17, BA 18), the syndrome (SO-S7), and the error flags (AE, EO, E1) during an error condition. The latched data will be displayed on the LED's (until the I/O RESET signal is applied) and can be read from the data bus by the CPU. The address in error could also be latched by this same logic, if desired. The 2 input AND gate (U5) in the upper left of the P.LC.logic diagram holds CS low until after RASIN goes high on the DP8409A/19. This is particularly useful for READ cycles with one ERROR where RASIN is extended beyond the end of the current cycle, perhaps into another access cycle. In this application double bit errors, in the dynamic RAM, generate an interrupt to the CPU. All single bit errors are automatically corrected and rewritten back to memory. During a SYSTEM RESET the internal flip-flops of PAL #1 are set to a refresh state by making the RESET input look like a refresh request (External logic was used to "NOR" the DP8409A/19 RFI/O input with a system RESET input to produce the PAL # 1 RFI/O input). The P.LC. performs HIDDEN REFRESHES (CPU not accessing the Dynamic RAM controlled by the DP8409A, indicated by "/CS" being high) assuming a 4 "T" state processor access cycle. 3-107 • The P.I.C. allows the full use of the DP8400 and all its modes of operation. For example, the DP8400 has excellent diagnostic capabilities included in modes "2" and "6". These modes allow one to perform a complete diagnostic test of the DP6400 without using the external memory. This is possible using an I/O port to control "M1 and MO" of the DP8400, along with the diagnostic control signals "DIAGCS and DIAGD" as follows: 1) The user can set the I/O signals "M1" and "DIAGCS" both high and perform a mode 2 DIAGNOSTIC WRITE to the DP6400 with user generated CHECK bits on the high byte of the data bus. The CHECK bits will be latched into the DP8400 (CSLE held low) until the user sets the I/O signal "DIAGCS" low. 2) The user can then set the I/O signals "M1" low and "DIAGD" high and perform a mode 0 WRITE, latching the user generated data in the DP6400 input latches (OLE held low). was high a setup time before the clock transitions high (here RASIN, RFSH, and QO[E are outputs and 20 is an input). Depending on the SpecifiC type of PAL's and logic used the user can calculate the speed requirements for the DRAM at the specified processor frequency as follows: Here both "tRAC" and "tCAC" must be calculated and con· sidered in determining what speed DRAM can be used in a particular system deSign. The DRAM chosen must meet both the "tRAC" and "tCAC" parameters calculated. EXAMPLE SYSTEM, 10 MHz, DP8400·2, DP8419, FAST "A" PART PALs #1) RASIN low = T1-2 ns (FCLK-PHI1 skew) + 15 ns ("A" PAL clocked output) = 100-2+ 15 = 113 ns maximum #2) RASIN to RAS low = 20 ns maximum (DP8419) #3) AASiN to CAS low = 80 ns (DP8419 FiAS'iN-"CAS low maximum) #4) 74F244 transceiver delay = 7 ns maximum #5) DP8400·2 data setup time to "CSLE, OLE" = 10 ns maximum #6) Minimum "CSLE, OLE" delay into "T3" = Minimum "A" PAL delay - minimum FCLK to PHI1 skew = 8 - 2 = 6 ns minimum 3) Next, the user can perform a normal mode 4 READ. This will in effect be a diagnostic READ of the user generated data and check bits without using the external memory. In this way the DP8400 can be completely checked out duro ing system initialization. 4) The syndromes, check bits, and error flags can also be read, provided ODLE, 080, and 0Bf are low, using mode 6A or by reading the latches. 5) When the diagnostics are completed the user can reo turn the DP8400 to normal functioning by resetting the 110 port outputs to the original DP8400 operating mode values ("MO, M1, DIAGCS, DIAGD" all low, and "I/o RESET" high). "tRAC" = T1 + T2 + TW - #1 - #2 - #4 - #5 + #6 Using the I/O port signal "MO" the user could perform the DOUBLE COMPLEMENT METHOD to try to correct a DOU· BLE bit error in the DRAM (see DP8400 data sheet for fur· ther Information on the DOUBLE COMPLEMENT METH· 00). Therefore the DRAM chosen should have a "tRAC" less than or equal to 156 ns and a "teAe" less than or equal to 96 ns. Standard 150 ns DRAMs meet this criteria. Approximately 150 ns minimum RAS precharge time. Another I/O port output, "I/O RESET", allows the outputs "DOUBLERROR" and "~,, in PAL #3 to be reset. The Signal "~" is used in this interface to latch the SYNDROME, DRAM bank, and ERROR flags during a CPU READ access with a single, double, or triple bit error. The CPU can READ these latched error signals by performing a memory READ from a specific memory location. (An OFF BOARD CHIP SELECT, "CS-CFFB".) This READ will gate the latched error condition to the CPU data bus via the 74LS244 buffer and the signal SYNDROME·DATA (see the upper right hand corner of the P.I.C. controller logic dia· gram). Approximately 200 ns minimum CAS precharge time. Approximately 230 ns minimum RAS pulse width. = 100 + 100 + 100 - 113 - 20 - 7 - 10 + 6 = 156 ns "tCAC" = T1 + T2 + TW - #1 - #3 - #4 - #5 + #6 = 100 + 100 + 100 - 113 - 80 - 7 - 10 + 6 = 96ns Approximately 180 ns minimum CAS pulse width. One must also consider the WRITE command to RAS and "CAS lead times when choosing DRAMs for this system. Our· ing a READ access cycle, with a single bit error, a READ· MODIFY·WRITE access is performed. Here, the WRITE command to RAS and ~ lead times are one half period in length. This may present a problem to systems operating at frequencies of 10 MHz or greater. One can alleviate this problem by Inserting an extra WAIT state into READ access cycles (see Use of P.I.C. at higher operating frequencies, #3) or by using external drivers from the PAL "WE" output to the DRAM "WE" Input (thereby speeding up the WIN to WE delay and guaranteeing a greater WE to 'RAS and CAS lead time). The PAL equations that fonow are in the National Semicon· ductor PLANTM format, which differs from the standard PALASMTM format. EXAMPLE: PLAN FORMAT "~ : = RFSH .215 .ODLE" USE OF THE P.I.C. AT HIGHER FREQUENCIES This translates as, "AASiN" is low after the rising edge of the input clock given that "RFSH" was high and "20" was low and "OOU:" was high a setup time before the clock transitions high (here RASIN, RFSH, and ~ are outputs of the PAL and 20 is an input). EXAMPLE: PALASM FORMAT 1) If one is using this interface above 4-6 MHz he should consider using the fast PAL's· (example "PAL 16R8A" in· stead of "PAL16R8"), a fast shift register (example 74F164), external fast logic (such as "AS, ALS, or F" type 74XX series) or the faster "B" type PAls to produce outputs "~, 080, 0Bf" to the DP8400, and the new DP8400·2 error correction chip. The fast PAL's· have an input to output maximum time of 25 ns, and 15 ns if it is a registered output. The slow PAL's· have an input to output maximum time of 35 ns, and 25 ns if it is a registered output. "RASIN : = RFSH • 20 • ODLE" The above expression means the same as the PLAN format expression except it is written in PALASM format. In other words "AASiN" will go low after the rising edge of the clock given that "RFSH" was high, "20" was low and "COLE" 3·108 One needs to produce "DOUTB, OBO, OB1" faster at higher CPU speeds to guarantee that the CPU reads valid data during a READ access cycle. To do this he could use external fast logic as shown in the following figure. Using the above example we can calculate (assuming a 10 MHz 32000 series processor) the time required to have valid data at the CPU data input pins. If WAIT states are also wanted in WRITE access cycles the "CWAIT" equations must include the following term: + RFSH • INCY • TSO • DDIN • 2D HIDDEN REFRESH and WRITE cycles as follows: + RFSH • RASIN • INCY • 2D ~~lOo- F?:--_-----: 3) Another possibility for this interface at higher frequencies would be to adjust READ access cycles by adding another WAIT state to them, as well as adjusting BYTE WRITE cycles. ... Using this method one would need another stage for the shift register or use a 74F164 and use CTTL as its clock instead of FCLK. If one looks at the above figure, using the 74F164, for reference the extra stage "10D" would be used. This would allow one to make the READ access cycle one "T" state longer by adjusting the READ and READ with error "RASIN" equations. To make the READ access cycle one "T" state longer another WAIT state would have to be added to READ cycles (making a total of 2 WAIT states) and the latch signals "ODLE" and "CSLE" must be adjusted by delaying them back % "T" state (allowing a % cycle longer access time). This also has the advantage of allowing the other % cycle of time to get the data valid at the inputs of the Series 32000 CPU. The BYTE WRITE access cycle could also be adjusted by delaying the signals "ODLE" and "CSLE" by % cycle. No other equations need to be touched. This would allow an extra % cycle for access time during BYTE WRITE access cycles. This would allow a standard 150 ns to possibly 200 ns DRAM in a 10 MHz system [80.5 ns + % "T" state (50 ns) = 130.5 ns column access time (tcAcH but would sacrifice by having 2 WAIT states in READ access cycles. 4) One also must be careful to make sure that CS is low, during an access, a minimum of 30 ns (DP8409A, 15 ns DP8419) before RASIN transitions low. If this is a problem one could tie CS permanently low (disabling hidden REFRESH) and use the system transceivers to select the memory system. CSLE-----.....J TLlF/B400-1 @OB1 would have the same configuration as OBO 13 ns (maximum time of CSLE into state T3 assuming fast "A" PAL) + 9 ns (maximum 74ALSOO propagation delay) + 9 ns (max 74ALSOO prop delay) +36 ns (maximum DP8400-2 "OBO, OB 1" to output valid delay) + 7 ns (maximum 74F245 propagation delay) + 20 ns (data setup time required for the series 32000 with respect to the CTTLclock) = 94 ns '* 'This value must not exceed 100 ns for a 10M Hz processor. The delay of "DOUTB" is to allow the DP8400 data, check bit and syndrome latches "DLE, and CSLE" to latch the data and check bits before turning off the DRAM output buffers. The delay of "OBO and OB1" allow the DRAM output buffers to turn off before the DP8400 starts driving the DP8400 memory data bus. In general the DRAM output buffers should turn off much faster then the DP8400 output buffers can turn on, so the user may want to allow "OBO, OB1" to become valid at the same time as "DOUTB" transitions high. 2) In order to allow the use of slower DRAMs at higher CPU speeds one may want to slow down access cycles by adding an extra WAIT state. To do this one could replace the 74LS164 IC with the following circuit: OA DB mil 3 EXTRA DELAY NC OTHER OPTIONS 20 40 60 If one is using the NS32082 Memory Management unit in a Series 32000 system he should connect the output "PAV" (Physical Address Valid) to the P.I.C. instead of the address strobe output "ADS". 74F164 m::m 80 cm NC NC . w 00 ...... If one wants to keep WRITE cycles without WAIT states inserted then the "RASIN" equations must be modified for 'm~ IIi\Sifl » z 100 An output for the BUS PARITY ERROR in a data transfer from the CPU to memory could also be detected, from the error flags and "AE" of the DP8400, and used to interrupt the CPU. However, the P.I.C. does not make use of that feature of the DP8400, though it would be very easy to add. If one does not want to WRITE corrected data to memory in case of a DOUBLE BIT error, in READ access cycle, he could disable the WRITE signal, "WIN", during a DOUBLE BIT error as follows: TLlF/B400-2 Here "CTTL" was used instead of "FCLK" with a 74F164. The "~" PAL equation must be adjusted to keep "~" 5 clock periods long, as follows: RFSH: = RFIO.INCY.2D +RFSH.RFIO +RFSH.6D +RFSH.CTTL WIN~ WIN WIN DOUBLERiiifIi TLiF/B400-3 3-109 • ~ r-------------------------------------------------------------------------~ ~ z, PAL NUMBER 3 Co) Q) PAL16R6A FCLK CTTL DIAGCS DIAGD /RESET CSRASIN AE EOl /DOUTB GND /OE /AOHBE /ERROR /ERRLAT /DOUBLERR /MODECC /CSLE /ODLE /DDIN VCC /ODLE : = CSRASIN./DDIN*/DOUTB./CTTL ;Read ;Read with error ;Byte Write ;Continue during Byte Write ;Byte Write ;Word Write ;Hold "/ODLE" ;Hold "/ODLE" for diagnostios + CSRASIN./DDIN./MODECC.CSLE.ODLE + CSRASIN.DDIN,/AOHBE./DOUTB./CTTL + /ODLE.CSRASIN.DDIN./AOHBE.CTTL + CSRASIN'DDIN'/AOHBE' /MODECC'CSLE'ODLE + CSRASIN'DDIN' AOHBE'/CTTL + /ODLE.CSRASIN.CTTL + /ODLE.DIAGD /CSLE = CSRASIN,/DDIN,/DOUTB,/CTTL ;Read ;Read with error ;Byte Write ;Byte Write ;Word WRITE ;Hold "/CSLE" ;Hold n/CSLE" for diagnostios + CSRASIN. /DDIN. /MODECC + CSRASIN.DDIN./ AOHBE./DOUTB./CTTL + CSRASIN.DDIN./ AOHBE./MODECC + CSRASIN.DDIN.AOHBE./CTTL + /CSLE.CSRASIN.CTTL + /CSLE.DIAGCS /MODECC := CSRASIN./ODLE./DDIN./CTTL + CSRASIN,/ODLE.DDIN./AOHBE./CTTL + CSRASIN.DDIN.AOHBE + /MODECC.CSRASIN ;READ ;BYTE ;WORD ;Hold ...... or Write w/error WRITE WRITE "/MODECC" /DOUBLERR := /DIAGCS./DIAGD.RESET.CSRASIN./ODLE./CTTL.AE.EOl ;Double bit error during READs or BYTE WRITEs + /DOUBLERR.RESET ;Hold "/DOUBLERR" /ERRLAT := /DIAGCS./DIAGD.CSRASIN./ODLE,/CTTL,AE + /ERRLAT'CSRASIN /ERROR := ;Any Error during ; READ or BYTE WRITE ;Continue n/ERRLAT" during READ or during BYTE WRITE /DIAGD./DIAGCS.RESET.CSRASIN./ERRLAT ;Store error syndrome and RAS bank and error flags + /ERROR,RESET ;Hold until RESET ;The output, n/CSLE", is shown inverted so the PAL will be ;programmed correctly, in other words, n/CSLE" goes low after the ;rising edge of FCLK given that one of its input equations was ;low a setup time before FCLK transitioned high. The output, ;n/CSLEn, should go straight to the pin "CSLEn of the DP8400. 3-113 • DP8400, DP8409A, NS32016 Error Correcting Dynamic RAM Computer System TERMINAL RS·232 c U~ -:> RDM STATIC RAM NMC2764(2) MONITOR NMC2116(21 r-- r- ~L C r -- ~ CPU & CLOCK CHIP PARALLEL PORr INS8255 SERIAL 110 lNS8251 NS32016 NS32201 .!J. ADDRESS BUS 7 - DATA BUS ~.L ,n· r-r-- r-'",""\ 1681TS } CONTROL BUS D CONTROL CORRECTION OP8400-4 OR DPB400-2 r CONTROL B419 ADDRESS DRAM CONTROLLER OPB409A. OP8419 OR OPB429 ERROR CHECKER/ 3-PAl INTERFACE CONTROLLER CONTROL l' - MEMORY (DRAM I (256k DRAMSI 4 BANKS DF 22 2M BYTES PLUS CHECK BITS ... DATA CHECK BITS TLiF 18400-4 3-114 NS32016, DP8400, DP8409A or DP8418 Error Correcting Memory System DAMPING RESISTORS .1 I I 0P84300 PftOGRAMMABlE DIVIDER rI 15.6"' CLOCK SYSTEM CLOCK I DECODER CTn 16 ADDRESSIDATA -, BUS ADO-ADI5 -[ 1 74AlS373 lATCHES 1 1 Vcco-- ~- --. 24 BIT :3~RESS AD ,~ FROM ITO PAL INTERFACE CONTROllER 74F245 OIR PBUfO DDiN 'J' 00-7.8 RGCK RASO-3 CAS , ADS WE -". RF 110 DP8409A. DP8419 OR DP8429 11 00-7 8 8 .Y RfSM FClK CS DDiN AD HBE OLE 3 PAL" & SHIFT REGISTER (74lS164) INTERFACE CONTROllER - ~ 74AlS244 8 008-15 ~ EO I ~ ~ OOUBlERR 0116-21 CHECK BITS AE ~ SYSTEM RESET 6 OP8400 El ADS • OOUTB CO-5 MOOECC TSO . . CWAIT 000-7 CSlE P.I.C. RF 110 ... DB~ 8 OLE CTTl ... 00-7 r-;--uOBO. iiB1 D10-7 DlB-15 PBUfl lIff MEMORY UP TO 4 BANKS Of 22 256k DR 1M DRAMS BM BYTES PLUS CHECK BITS 74AlS244 PBUFI CAS WE DB-IS NS32016. NS32201 NS32082' P8UfO . ~ WIN 0-. cs I- 01 AOORESS RASO-3 Rml(M2) 74F245 ~ . RCO-7.8 OIR AD8-15 I+ 0 . . - RASIN A16-A2l ADO-7 RFCK CWAIT OES C'6~.L~ 6 74AlS244 0016-21 CHECK BITS 2.2k OOUTB ! ! t fROM 110 PORT 10 OIAGCS. 10 OIAGO. 10 RESET FROM 110 PORT Ml MO TLiF 18400-5 'IF system contains NS32082 MMU PAY should be used in place of ADS LeE-NY iii AN-387 PJ.C. 3 PAL and Shift Register Interface Controller ~ FeLl( I Ci I iIiiili C>""---I- - I . --~ ....... " C>-- 1 .... r C>-- iffiO Z 5 ~ m O'l D--" ~ _ ---= .. IN il CL74lS''',,~ '" ~_ ::r : .. I. , , Jg.... " .. QH L-..;;J 13 1~13 11 ",1111 54 S1 3D 17• 6D 3Q • 60 15 • .. .. I ~ --," _ .. L 80 +' .~ ..., . I!I.... "" ~ 1 11 In~ "'. ~ :: " "UIIlSIII ..... .. ~ - I 111~ II I"" - ... , .' :: -,," ~ .' : : - LEOs 1", "} ",.. { , .. r- m 17 [1L LO 15 ZA ERROR 00" , • 3 5 'li " "" oo,;9 ..... FlAGS DOl 119 -..01 " .. tV - " DO (8:11) - -- ... - - - - . ~• .!!!.....-c:>.., - . -~ ..... ... ~JIIiiiF1 EImT ,,- ... . .. III 14 ~ ~ OtSPlAl PMM BANK. SYNDROME AND EllROaFlAGS DURING EAAORS. LSD '. r .----.,! - ; ; CO< L--..J.I I .... c ". . iilm. lill!!!!!L.! 6D ~18· ~ lS3 ... "1 - 1 " I LElh ~"STAH7 ,~-' • 1" ~ , } {~: =: .0- on : .... "'. I i----' _.o'~ L " ' " -' . -11 ~ ~ ~" " -.-----.,'"..~ .. -,;; 3 - ,,5 "" r.~::r: 1""7 ' Ie I II , .. -, _S " 11 • .: • : ,~' _ 1 I BA18." S5 72D .-0..... '-'~ ~ ~. _ : -+ ." +---, • us ~ I BA17' ,,___ _ • I-- . 5 - -. 1 ., 1 CK" -. .: --"Ii ' ~~ , .".E-" ggtI: "WIIi P'LI' '" • I II::.:.~. .- 1. '" ~ - ..... O .. -J iffiEi 5 .. 17 ..... IIRR 16 1- ' • ID 18 -,;;,. -- J ~ .=-- ~ ":j' _ ...' ~ • • ... r1IIIiir"7 I ~ ~~ __ 1." I"~ ""'" ~'::: I~ iIiOY - D-- ,. RflO ""'___.... - _ I c>--i--J .1 'DI',5 _ rI . ,- em, .,. -', _""1 IF 110 ~ feLl( L C:>=---... IIII -, I iiiIijjj CS" ~mwB -c:: =ti !L....c:>WIIi ~bOU'1!!!!!.c> IRiiiii1Rii ITO CPU INTERRUPT PIN) TL/F/8400-6 r--------------------------------------------------------------------, WRITE ACCESS CYCLE T1 CTTL T2 • Co) CD ..... READ ACCESS CYCLE (WITH NO ERRORS) T3 T1 T4 TW T2 T4 T3 ~ z rL rL rL n- n- rL n-n- rL h I u II II II ru I DPB400 MEMORY DATA BUS r::. WRITE DATA ,..........,. DRAM .J ECC DATA} -r-- I CHECK BIT S DRAM GENERATED .J ~ '-~ J I 20 In 40 L L II L r ~ n. 0 0 P--CSLE P--- n I J I i lJ T I II nr r r I J In n- • II> • L I io--- r - L TLiF/8400-7 3·117 ~ co r--------------------------------------------------------------------------, C? WRITE ACCESS CYClE, EXTENDED FROM PREVIOUS READ (WITH ERROR) ACCESS CYCLE ROO ACCESS CYClE (WITH SINGLE BIT ERROR) z --L 0 AIT }- r--- 0 OR GENERATED r-- 0 { T4 L ~ J • r r IN / \ p. LATCH ERROR CONDITION (PRESENT ONLY IF ERROR) TLIF18400-9 3-119 ..... co CO) I Z cc FORCED REFRESH FOLLOWED BY READ ACCESS WITH ERROR T1 CTTL TWI T2 TW2 TW3 TW4 TW5 TW6 T4 T3 rL rt- rL rL n- ILn- rL n-rI- CSDRAM iiDiN mADS II r--n II ru ~"'~".' DP84DD MEMORY DATA BUS EO ~RAM ~A CHECK BITS TED RF 110 iiFSil iiASiN 20 I r--~ I I 40 II II 60 :1 II I r- 1 80 am r-- CSlE r-- I Im'/ 'DIO,l n. r ..I r-- ru 1 1 , , , II J 11 II \ IL~ \\ I ;1--- \ CYCLED rL /--TL/F16400-10 3-120 r---------------------------------------------------__________ T2 T1 CTTL TWl rLn-n- TW2 TW4 TW3 TW5 --,~ ZI FORCED REFRESH WITH WRITE ACCESS AT THE SAME TIME IWRITE EXTENDED FROM PREVIOUS READ WITH ERROR) Co) 00 TW6 ..... T4 T3 n-n-n-rLrLn- rL w RF 110 r- """-1 ru OPB400 MEMORY DATA BUS CHECK BITS , """ECC CORRECT WRITE DATA ~ J ~ GENERATED 1-----1' J J W f-- oil 011 011 on II ~ L l n I H I lJn CSLE f--- J L W LJ T j 1 1 l l II J L l f-- I 0 "- • L L FROM PREVIOUS READ ACCESS CYCLE WITH ERROR 3-121 TLlF/8400-11 ,..- r--------------------------------------------------------------------------------, Determining the Speed of .- National Semiconductor Application Note 411 z ZI #4) 74F245 transceiver delay = 7 ns maximum #5) CPU data setup time to "T4" = 5 ns minimum "tRAC" = T1 + T2 + T3 - #1 - #2 - #4 - #5 = 100 + 100 + 100 - 76 - 20 - 7 - 5 iAPX 86/88 8 MHz No Wait State Calculations #1) RA81N low = Maximum clock high + 15 ns ("B" PAL combinational output delay) = 82 + 15 = 97 ns maximum #2) RA81N to RAS low = 20 ns maximum = = "tCAC" = = RASIN to CAS low = 80 ns (DP8419-80 RASIN CAS low) - 3 ns (load of 72 DRAMs instead of 88 DRAMs speced in data sheet) = 77 ns maximum (using 15 ns minimum row address hold time) Therefore the DRAM chosen should have a "tRAC" less than or equal to 186 ns and a "tCAC" less than or equal to 129 ns. Standard 150 ns DRAMs meet this criteria. 7 MHz iAPX 286, 14 MHz Clock, No Wait State Calculations #1) RA81N low = T1 + 74A804 gate delay + "8" PAL clocked output delay = 71.4 + 4.5 + 12 = 88 ns maximum 125 - 85 - 20 - 7 - 20 #2) #3) = 243 ns "tCAC" = T1 + T2 + T3 - #1 - #3 - #4 - #5 = 125 + 125 + 125 - 85 - 94 - 7 - 20 = 169 ns Therefore the DRAM chosen should have a "tRAC" less than or equal to 243 ns and a "tCAC" less than or equal to 169 ns. Standard 200 ns DRAMs meet this criteria. RASIN to RAS low = 20 ns maximum RASIN to CAS low = 80 ns (DP8419-80 RASIN CAS low) - 3 ns (load of 72 DRAMs instead of 88 DRAMs speced in data sheet) = 77 ns maximum (using 15 ns minimum row address hold time) #4) 74F244 transceiver delay = 7 ns maximum iAPX 86/88 10 MHz No Wait State Calculations #1) RASIN low = Maximum clock high + 15 ns ("B" PAL combinational output delay) = 61 + 15 = 76 ns maximum #2) RASIN to RAS low = 20 ns maximum #5) CPU data setup time to "T4" = 10 ns minimum "tRAC" = Tl + T2 + T3 + T4 - #1 - #2 - #4 - #5 = 71.4 + 71.4 + 71.4 10 = 160 ns 3-127 + 71.4 - 88 - 20 - 7 - • + + + ....... r------------------------------------------------------------------------------------------, + + + ~ ~ "tCAC" = T1 T2 T3 T4 - #1 - #3 - #4 - #5 = 71.4 71.4 71.4 71.4 - 88 - 77 - 7 10=103ns Therefore the DRAM chosen should have a "tRAC" less than or equal to 160 ns and a "tCAC" less than or equal to 103 ns. Standard 150 ns DRAMs meet this criteria. #4) 74F244 transceiver delay = 7 ns maximum #5) CPU data setup time to "T4" = 10 ns minimum "tRAC" = T1 + T2 + T3 + T4 - #1 - #2 - #4 - #5 = 62.5 + 62.5 + 62.5 + 62.5 - 79 - 20 - 7 10 = 134 ns "tCAC" = T1 + T2 + T3 + T4 - #1 - #3 - #4 - #5 = 62.5 + 62.5 + 62.5 + 62.5 - 79 - 77 - 7 10 = 77 ns Therefore the DRAM chosen should have a "tRAC" less than or equal to 134 ns and a "tCAC" less than or equal to 77 ns. Standard 120 ns DRAMs meet this criteria. 8 MHz IAPX 286, 16 MHz Clock, No Walt State Calculations #1) #2) #3) low = T1 + 74AS04 gate delay + "8" PAL clocked output delay = 62.5 + 4.5 + 12 = 79 ns maximum RASIN to RAS low = 20 ns maximum RASIN to CAS low = 80 ns (DP8419-80 RASIN CAS low) - 3 ns (load of 72 DRAMs instead of 88 DRAMs speced in data sheet) = 77 ns maximum (using 15 ns minimum row address hold time) RASIN 16MHz+-----------------------------, 14MHz+---------------------------~ II lOOns DRAM (256Kx1) (50ns tCAC) D 150ns DRAM (256Kx1) (75ns tCAC) 12MHz 10MHz 8MHz~~__~----~__~---- 6MHz rrrrm 4MHz Wllll SERIES 32000 68000 rAMILY 68020 68020 (1 WAIT STATE INSERTION) 8086 8088 80286 80188 80286 200ns DRAM (256Kx1) (lOOns tCAC) • FOR THE 150n. AND 200ns (256Kxl) DRAMS THE ACCESS TIME IS RAS LIMITED TL/F/8595-3 FIGURE 3 Note 1: The data presented in this figure is based on typical examples. Faster "no wait state" CPU performance is possible with several of the microprocessors shown above via the use of the DP8419·70 Instead of the DP8419·80; the elimination of Data Bus Transceivers; a more tailored PAL (Refresh Access Arbitrator) approach; faster support logic; lower than the 15n damping resistor specified in the DP8419·80 data sheet; or, less than the specified capacitive load driven directly by the DP8419 (88 DRAMs). 3-128 National Semiconductor Application Note 436 Webster (Rusty) B. Meier Dual Port Interface for the DP8417/18/19/28/29 DRAM Controller Refresh always has the highest priority and will always occur immediately upon a refresh request (i'fFRCi) given that an access by Port A or B is not currently in progress. Port A has a higher priority than Port B though the scheme used attempts to give both ports a more equal priority. The arbiter does this by leaving Port A or Port B granted, after an access by that particular port, as long as no other ports are currently trying to access the DRAM. This scheme is used because data tends to be transferred In bursts from a particular port. Once a port is granted, subsequent requests by that port immediately access the DRAM, until another port gains access to the DRAM (see Figure 11 of the timing waveforms for Port A). This arbiter guarantees one and one half system clock periods of RAS precharge between accesses of different ports. It is up to the user to guarantee the precharge time between consecutive accesses from the same port. This arbiter assumes a minimum of one period high time between access requests from a particular port. Hidden Refresh is not supported in any of the following dual port schemes for several reasons: 1) I! "CS", of the DP8419, is not permanently tied low the user must guarantee a "CS-RASIN" minimum time of 34 ns for the DP8419. This could slow down the access time of several of the dual port schemes presented. 2) In order to do hidden refresh a port must be granted during a non-CS access cycle. When the port is granted during a non-CS access cycle the other port may be requesting the dual ported memory also and have to wait for it. A possible problem is that the non-CS access may not even be causing a hidden refresh at that time so in essence the other port is being slowed down for no reason (i.e. a hidden or forced refresh may have already been done during that period of the refresh clock). I! either Port A or B tries to access the DRAM during a refresh WAIT states will automatically be inserted into that port's access cycle. Also if one of the ports tries to access the DRAM while the other port is, WAIT states will automatically be inserted into the appropriate port's access cycle. The user may want to change the "WAIT" state equations depending upon the processor or bus being interfaced to. The DUAL PORT ARBITER gives access to the refresh cycle via the M2 (RFSH) pin of the DP8419. The GRNTB output of the DUAL PORT CONTROLLER acts as a multiplexor Signal to enable either PORT A or PORT B. Once enabled the Port selected will enable its addresses, write enable, [QOj( control Signal, and data to the DP8419 and its controlled memory. The user must be careful to assure that a particular port will not be locked ("LOCK" low while "GRNTA or B" Is low) for more than 15.6 ,""S (RFCK period) or the system may miss a refresh. The Dual Port scheme presented assumes that all "PORT REQUEST" inputs are synchronous to the system clock input to the PAL (i.e. "PORT REQUESTs" occur following a rising edge of the system clock). I! a specific "PORT REQUEST" is asynchronous to the system clock it has to be synchronized to the system clock by running it through two flip-flops (see "AREQB" and "ARFRQ" in the system block diagram). The two "RFRQ" synchronizing flip-flops are needed for the PAL refresh logic to work correctly. The term "WliiIA" (write enable for Port A) is used to cause "RASIN" to be generated later for a WRITE access than a READ access. This may be necessary to guarantee that valid data is written to the DRAM during WRITE accesses. If Port B is asynchronous this Input Is not needed because Port B requests are delayed through the external synchronization circuitry. If Port B is synchronous both ports should mux to the "WIN" input, and use this input in generating the "RASIN" output of the PAL. The Dual Port scheme presented does not assume the use of any specific processor. Therefore, the user may require some external logic to interface the Dual Port PAL to a specific microprocessor or bus. Figures 1-5 show several suggestions for circuits used to generate "REQA" for different CPU's. The PAL equations were deSigned assuming a National Semiconductor Series 32000® CPU on Port A. In the "RASIN" equations for Port A WRITE cycles were started one hal! period later than READ INTRODUCTION This application note describes a general purpose dual port interface to the DP8417118/19/28/29 DRAM controller. A PAL® (Programmable Array Logic) device is used to implement this interface. The PAL contains the logic necessary to arbitrate between the three ports (Refresh, Port A, and Port B), provide WAIT states to Port A or B when necessary, and an output to multiplex the Port A or B addresses to the DRAM controller. FEATURES • Provides a versatile dual port interface to the DP84171 18/19/28/29 DRAM controller • Provides arbitration circuitry between DRAM refresh cycles, Port A accesses, and Port B accesses • Allows for Port A and Port B to be synchronous or asynchronous to the input system clock • Guarantees a minimum of one and one half system clock periods of RAS precharge time between grants to any two ports • Provides WAIT state logic to both PORT A and Port B to handle contention problems between ports • Differentiates between READ and WRITE accesses for Port A allowing Port A WRITE accesses to begin later than READ accesses DESCRIPTION This hardware arbitrates access to the dynamic RAM controlled by the DP8419 (or any of the related family members: DP8417/18/19/28/29) to either: 1) A Refresh cycle, "GRNTRF" 2) Port A, "GRNTA" 3) Port B, "G11NiB"" 3-129 cycles and both READ and WRITE accesses were ended one half period after "REOA" went high (this is to make up for WRITE accesses starting one half period after "REOA"). The user may wish to modify these equations (and possibly the "WAlTA" equations) depending upon the specific CPU being used. EXAMPLE: DETERMINING THE REOUIRED MEMORY SPEED ("tRAC" AND "tCAC") FOR A SERIES 32000 TO RUN AT 10 MHz WITHOUT WAIT STATES This reads, the active low flip-flop output "GRNTRF" is low following the rising edge of the input clock given that, the active low input "RFRO" is low AND the active low output "GRNTA" is high AND the active low output "GRNTB" is high a setup time before the input clock transitions high. (Notice that RFRO is interpreted as being low.) POSSIBLE MODIFICATIONS TO THIS APPLICATION In this application "REOB" is synchronized to the falling edge of the system clock input of the PAL. Generating "REQB" from the falling clock edge allows minimum delay from the asynchronous request to the synchronized request producing "GRNTB" and or "RASIN". Producing "REOB" in this way also delays "RASIN" during a port B access because of the effect of the "GTOA" term. In order to calculate the tRAC and tCAC of the DRAM (see Series 32000 example above) the delay to "RASIN" low would be: "AREOB" low (asynchronous request B) + SYNCHRONIZATION delay (2 flip-flops) + 3 input NAND gate delay of "GTOA" + PAL delay for "RASIN". If "REOB" is synchronized to the rising edge of the system clock there is a potential danger of getting glitches on the "RASIN" output of the PAL as a result of the "GTOA,B" terms. The glitches are possible under the condition of both "REOA" and "REOB" going low during a single clock period. For example, if Port B is currently granted ("GRNTB" low) and "REOA" goes low more than one inverter gate delay before "REOB" goes low the "GTOA" term will initially be high, then go low, then back high. This could cause a small glitch at the beginning of "RASIN". This glitch can be avoided by guaranteeing that either the requests are separated by at least a three input NAND gate delay (as is the case in this application note) or that when two requests happen within one clock period they happen within one inverter gate delay of each other. The circuits shown below, in Figure 1, could be used to guarantee that when two requests happen within one clock they occur within one gate delay of each other. Assume the Series 32000 is synchronously interfaced to Port A. #1) RASIN low = T1 + 6 ns (PHI1 to CTTL Rising edge maximum) + 12 ns ("B" PAL clocked output) + 15 ns ("B" PAL combinational output) = 100 + 6 + 12 + 15 = 133 ns maximum #2) RASIN to RAS low = 20 ns maximum #3) RASIN to CAS low = 70 ns (DPB419-70) - 3 ns (72 DRAMs instead of 88 DRAMs spec'd in data sheet) = 67 ns maximum #4) 74F245 transceiver delay = 7 ns maximum # 5) CPU data setup time to "T4" clock cycle = 15 ns maximum "tRAC"=T1 +T2+T3- #1- #2-#4-#5 =100+100+100-133 ns-20-7-15=125 ns "lcAC"=T1 +T2+T3-#1-#3-#4-#5 =100+100+100-133 ns-67-7-15=78 ns Therefore the DRAM chosen should have a "tRAC" less than or equal to 125 ns and a "tCAe" less than or equal to 78 ns. Standard 120 ns DRAMs meet this criteria. The following is an example of how to interpret the PAL equations correctly. These equations are presented in the format specified by the National Semiconductor PLAN format. CAUTION, this format differs from the much used PALASM format. EXAMPLE: GRNTRF:= RFRO*GRNTA*GRNTB TSO rROM SERIES 32000 CLOCK 0------------1 fSCi FIGURE 1_ Alternative Request Generating Circuits 3-130 TL/F/8678-1 IDEAS ON GENERATING "REQA" FOR SEVERAL DIFFERENT MICROPROCESSORS. *REQA, REQB, RFRQ should have a minimum setup time of approximately 20 ns before the rising edge of the system clock. o I SERIES 32000 1) "CLOCK" System clock. 2) "REQA·' A synchronous access request from Port A. "WINA" WRITE ENABLE from Port A. This input is used to delay "RASIN" during WRITE accesses. 4) "REQB" A synchronous chip selected access request form Port B. "AREQB" is run through two flip· flops to get "REOB". Chip Select for Port B is assumed to be included within this input. TL/F/8678-2 FIGURE 2. Series 32000 "REQA" Minimum of 2 periods RAS precharge between successive accesses. AS n.......Jr-..... )0""";,--\ AS "---_r-_ CLK ~-,--_ Xl-.....- O . 5) "RFRQ" A synchronous refresh request. 6) "LOCK" The "LOCK" input is an active low signal that is driven by either Port A or Port B. This input, when low, causes the arbiter to keep the currently granted Port granted until the "LOCK" input goes high. This input is useful in implementing atomic operations such as sema· phores that are useful in multiuser/multitasking operat· ing systems. 7) "GTOA" This input is generated externally using the three signals REQA, REOB, and LOCK with some discrete logic. This input indicates that the arbiter will switch to Port A, given that Port B is currently granted. This input is needed to guarantee that when the arbiter switches control of the DRAM from Port B to Port A that GRNTB goes invalid before REQB is able to start another access (see the RASIN output term "PORTB RASIN" in PAL equations). AREa TL/F/8678-3 FIGURE 3. 68000 "REQA" Minimum of 1% periods of RAS precharge. ~ 3) NTSO 0 - - - - - 0 REO A CLK » z DUAL PORT PAL # 1 INPUTS W aI TL/F/8678-4 FIGURE 4. 8086 "REQA" Method # 1 Minimum of 2 periods of RAS precharge. oI 8086 METHOD #2 ALE I 0------4 TLiF/8678-5 FIGURE 5. 8086 "REQA" Method #2 (For faster speed, minimum of 1 period of RAS precharge.) • 3-131 8) "GTOB" This input is generated externally using the three signals REQA, REQB, and lOCK with some discrete logic. This input indicates that the arbiter will switch to Port B given that Port A is currently granted. This input is needed to guarantee that when the arbiter switches control of the DRAM from Port A to Port B that GRNTA goes invalid before REQA is able to start another access (see the RASIN output term "PORTA RASIN" in PAL equations). 4) "GRNTRF" Goes to DP8419 M2 (RFSH) input. This causes an automatic forced refresh cycle. 5) "GRNT1D" Goes low one period after "GRNTA", "GRNTB", or "GRNTRF" go low. This output is used to guarantee that one period is allowed after arbitration before a "RASIN" is generated during a port access. This allows the particular port's address, write enable signal, and lock input to become valid before an access is started. This output also allows the PAL to determine when a particular port has been granted for several system clock periods. This information allows the arbiter to immediately generate "RASIN" for any subsequent memory accesses since the address is already muxed to the DRAM controller (see Figure 11 for the timing waveforms for Port A). 9) "ClK" This is the system clock input that may be used in the PAL equations (Le. "WAIT"). 10) "CSA" This input is the chip select input for Port A. It is used, along with "REQA", to request and cause an access to the DRAM. DUAL PORT PAL # 1, OUTPUTS 6) "WAlTA" This output functions as a WAIT input for Port NOTE: All outputs are active low. A. 1) "RASIN" This is the RASIN input to the DP8419 for Port A, Port B, and refresh. 2) "GRNTA" This output is the grant output for Port A. 7) "GTORFSH" This input is generated internally and indicates that the arbiter will give access control over to the refresh Port at the next rising clock edge. 3) "GRNTB" This output functions as the grant output for both Port A (high) and Port B (low). 8) "XACKB" This output is generated external to the PAL and functions as a transfer acknowledge for Port B. DUAL PORT PAL #1 PAL16R4B CLOCK /REQA /WlNA /REQB tOE /CSA /WAlTA /GRNT1D /GRNTA /GRNTB /RFRQ /LOCK /GTOA /GTOB CLK /GRNTRF /GRNTB /GRNTA /RASlN := /CSA*/REQA*GRNTRF*RFRQ"GRNTB GND /GTORFSH + /LOCK" /GRNTA + /CSA */REQA "RFRQ* /GRNTRF*GRNTlD + /CSA" /GTOA" /*GRNTB"RFRQ*RASlN + /CSA */REQA" /GRNTA + /GRNTA *REQB"RFRQ ;Start GRNTA ;Continue GRNTA ;RFSH_TO_PORTA ;PORTB_TO_PORTA ;Ho1d GRNTA ;Ho1d GRNTA REQA*GRNTA*RFRQ*GRNTRF"/REQB + /LOCK" /GRNTB + /GTOB" /GRNTA "RFRQ"RASlN + REQA "RFRQ" /GRNTRF" /REQB"GRNTlD + /REQB" /GRNTB + /GRNTB*REQA*RFRQ + /GRNTB*CSA"RFRQ ;Start GRNTB ;Continue GRNTB ;PORTA_TO_PORTB ;RFSH_TO_PORTB ;Ho1d GRNTB ;Ho1d GRNTB ;Ho1d GRNTB /GRNTRF := GRNTA*GRNTB*/RFRQ + /GRNTRF* /RFRQ + REQA */GRNTA "LOCK" /RFRQ + REQB* /GRNTB"LOCK" /RFRQ + /GRNTRF* /GRNTlD ;Start GRNTRF ;Continue GRNTRF ;PORTA_TO_RFSH ;PORTB_TO_RFSH ;Ho1d GRNTRF /GRNTlD := /GRNTA*GTOB*GTORFSH + /GRNTB*GTOA*GTORFSH + /GRNTRF* /RFRQ ;GRNTlD for PORTA ;GRNTlD for PORTB ;GRNTlD for RFSH IF (VCC) /GTORFSH = REQA*/GRNTA*LOCK*/RFRQ + REQB* /GRNTB*LOCK* /RFRQ ;PORTA_TO_RFSH ;PORTB_TO_RFSH 3-132 VCC DUAL PORT PAL #1. PAL16R4B (Continued) IF (VCC) /RASIN = /CSA*/REQA*/GRNTA*/GRNT1D*GTOB*GTORFSH*WINA + /CSA'/REQA'/GRNTA'/GRNTlD'GTOB*GTORFSH'/WINA*/CLK +/CSA'/REQA'/GRNTA'/GRNT1D'GTOB'GTORFSH'/WINA*/RASIN + /GRNTA */GRNTlD'/RASIN'CLK + /REQB'/GRNTB'/GRNTlD*GTOA'GTORFSH + /GRNTRF*/GRNTlD'GTORFSH IF (VCC) /WAlTA = /CSA'/REQA'GRNTA + /CSA*/REQA'/WAlTA'CLK ;PORTA READ RASIN ;PORTA WRITE RASIN ;PORTA WRITE RASIN ;Hold PORTA RASIN ;PORTB RASIN ;RFSH RASIN ;Start WAlTA ;WAIT until one half period after GRNTA "CSA • REQA • GTOA REQ8 • RFRQ + CSA. REQA TL/F/8678-6 FIGURE 6. Dual Port State Diagram ! &I 'Refresh hes the highest priority "Port A hes the second highest priority "'Port B has the lowest priority 3·133 q z PORT B ASYNCHRONOUS (COULD BE SYNCHRONOUS) PORT A SYNCHRONOUS c( SYSTEW CLOCK ADDRESS. WE. LOCK D A T D A T A A 0I>BEA =DATA BUFFER ENABLE FOR PORT A TL/F/8678-7 FIGURE 7. Dual Port Interface 3·134 -- ARFRQ - r-- ARFRQ D ~ r- Q-D RFRQ Q >CKQ i- >CKQ - - -- -A~D -- r- Qr-- D >CKQ i- CLOCK CLOCK - ~A REQA - ~A WINA ~QB - AREQB ~K LOCK - ---- ,c >CKQ r- - REQB WINA )0 GTOA 74LS10 L REQB ~N - 19 3 17 GRNTA DUAL PORT PAL #1 RFRQ 5 14 GRNT1D 13 WAlTA GTOB 8 9 - GRNTB 15 GRNTRF GTOA 7 ' - GTOB - I 16 GRNTB LOCK 6 ~LS10 ~TA 18 RASIN REQB 4 -LOCK REQA GTORFSH fCC 28 REQA 2 ~ ... REQA? - GTORFSH CLOCK 1 LOCK ~ Q~B ~SA I LO TRF -~T1D rJ.L - ,!!!TA 1~ ~ - - liE- -- CSA liE rDB - XACKB ~J )- RASIN - TUF/BB7B-B FIGURE 8. Dual Port PAL Controller Diagram mRII (PAL OUTPUT) 0 - - - - - - - 1 AREQB >C)--o SCWAITB .....----------0() L----------------o PORT B SYSTEM CLOCK ASYNCHRONOUS REQ8 TL/F/B67B-9 FIGURE 9. Asynchronous Port B transfer acknowledge ("XACKB") synchronizes circuit to produce "CWAITB" synchronous with the Port B clock "CTTL" ("SCWAITB") 3-135 ,. U) C') z cr:: REfRESH WITH PORT B READ ACCESS PORT B REQUEST PENDING WITH PORT A REQUEST PENDING PORT A READ ADDRESS CLOCK ARfRQ TWI T3 TW2 T4 I I RfRQ L ~ GTORF'SH ~ GRNTRf REQA I J -1 ~ I II/ I WINA WAITA PORT A WRITE ACCESS "'1.. rt.. rt. n.. rt.. rt. rt. n.. n.. "'1.. "'1..n.. n.. n.. n- iL n- n.. n. ..., T2 T1 ~ ~ l.i ..LI I ~ I GTOA ~ ~ ~ ~ ~ r-- I II :I> GRNTA + ~ I I AREQ8 REQ8 I I I I \ XACKB I I \ GTOB \ GRNTB I~~ GRNT1D I \ \ '-I PORT A RASIN _I I (~ ~~ I \. ... REfRESH I ~ I r~ ~ r-t PO ~B I PORTA LOCK ADDRESS (31:1) I 00000800 I I I I I 00000008 I I I I X 40000802 I 04426220 I I I I I I I I I I TLlF/8678-10 FIGURE 10. Dual Port Timing 3·136 PORT B READ ACCESS WITH PORT A REQUEST PENDING TW CLOCK PORT A READ ACCESS (NO WAIT STATES) PORT A WRITE ACCESS TW T3 T4 Tl T2 T3 T4 IL h- n... rL rL rL h- n... rL "'l.J ruru rL ;1..fU"L ARFRQ GTORFSH GRNTRF REQA J 1 p I WINA WAlTA , t t t t t ~ GRNTA I AREQB XACKB - ., GTOB J GRNTB ~ GRNTID RASIN I J \ h~ ~ !:J II> I LOCK ADDRESS (31:1) I I GTOA REQB 1/ + t I I I I I 1'-1 !X X 04426220 \ \ X 60000806 40000802 I~ I I.J I ! I I I J NOTICE RASIN STARTS ONE HALF PERIOD LATER DURING WRITE ACCESSES TLIF18678-11 FIGURE 11. Dual Port TImIng • 3-137 Section 4 Microprocessor Applications for the DP8420A/21A/22A Section 4 Contents AB-36 Explanation of National Semiconductor "PLAN" Software for Programming PALs. . . . . AN-542 Interfacing the DP8420AlDP8421A1DP8422A to the NS320081NS320161NS32C016/NS32032 and NS32132 ............................. AN-543 Interfacing the DP8420AlDP8421 AlDP8422A to the NS32332 . . . . . . . . . . . . • . . . . . . . AN-541 Interfacing the DP8420AlDP8421 AlDP8422A to the NS32532. . . . . . . . . . . . . . . . . . . . AN-540 A Dual Access NS32532 Error Detecting and Correcting Memory System. . . . . . . . . . . AN-538 Interfacing the DP8420AlDP8421A1DP8422A to the 68000/008/010. . . . . . . •.. . . . . AN-615 Interfacing the DP8422A to the 68000-16 (Zero Wait State Burst Mode Access) . . . . . AN-539 Interfacing the DP8420AlDP8421A1DP8422A to the 68020 ............•...•..... AN-616 Interfacing the DP8422A to the 68020 (Zero Wait State Burst Mode Access) •.....•. AN-617 Interfacing the DP8422A to an Asynchronous Port B in a Dual 68020 System ....... AN-537 Interfacing the DP8420AlDP8421A1DP8422A to the 68030 Microprocessor.... ... . AN-535 A Dual Access DP8422A168030174F632 Error Detecting and Correcting Memory System .......................•...•.•.•.......•...•.•...•.........•...........•. AN-544 Interfacing the DP8420A/DP8421A1DP8422A to the 8086/186/88/188 Microprocessor..... .•.••.• .. .•.•..•.....•........ .......•....... .... ....••.....• AN-545 Interfacing the DP8420A/DP8421 AI DP8422A to the 80286 ...............•.•.... AN-618 Interfacing the DP8420AlDP8421 A/DP8422A to the 80286 Above 25 MHz, Including No Wait States in Burst Mode. . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . • . . • . . . . • . . . . • . . . . . .• AN-536 Interfacing the DP8420AlDP8421 AlDP8422A to the 80386 ...•..•.•........•.•.. AN-619 Interfacing the DP8420AlDP8421 AlDP8422A to the 80386 (Zero Wait State Burst Mode Access) •.....•.•.....•.•..•.••...•.....................•.....•....•...•..• AN-602 Interfacing the DP8420AlDP8421 AlDP8422A to the 29000 Utilizing the Burst Mode Access ...............•.......•.....•....•...•...•.•...•.•.....•..•..•.•........ AN-546 Interfacing the DP8420AlDP8421 AI DP8422A to the Z280/Z80000/Z8000 Microprocessor . . . . . . . . • . . . • . . • . . • . . • . • . • . • . . . • . . • . . . . . . • . • . • . • . . • . • . . • . • . . . . . • .. AN-642 Interfacing the Dual Port DP8422A to the TMS320C30 and the VME Bus. .•..•.•.•• 4·2 4-3 4-4 4-11 4-24 4-34 4-40 4-56 4-61 4-82 4-86 4-90 4-98 4-113 4·117 4·129 4-138 4·154 4-170 4-183 4·187 r----------------------------------------------------------------.~ National Semiconductor Application Brief 36 Webster (Rusty) Meier Jr. and Joe Tate Explanation of National Semiconductor "PLANTM" Software for Programming PAL®s ~ 'l' INTRODUCTION This example reads: the output "I DC" will transition low given that one of the following conditions are valid; 1. the input "lAS" is low AND the input "/CS" is low AND the output "IDS" is low and the input "ClK" is low, OR 2. the input "lAS" is low AND the input "/CS" is low AND the output" IDC" is low and the input "ClK" is high PLAN equations can be converted to PALASMTM format very easily. First, the outputs of the boolean equations should be complemented. Second, any symbols in the boolean equations that are complemented (have" I" preceding the symbol) in the pin list should be complemented in the boolean equations. As an example the above mentioned sample equation has been converted to PAlASM below; The National Semiconductor PLAN software provides interactive design and development tools for system designers who use programmable logic devices (PAls). The PLAN software package permits a designer to create, with the use of an architecture specific language, an easily read and understood text file to describe a circuit design, select the appropriate device to accommodate the described logic, assign a pin-list to the device, document the design, generate test vectors for the selected devices, and format data to facilitate device programming and functional testing. PLAN allows the user to assign the device type (type of PAL), generate a pin list to accommodate the equations, and enter the boolean equations that define the PAls operation. The boolean equations are written in the sum-of-products form with architecture defining commands as required. The sum-of-products formatted boolean equations begin with a symbol representing a device output followed by either the equality (" = ") or clock (": = ") operator. The sign of the output symbol defines the state of the device output when the equation is satisfied. If the output symbol is preceded by a complement sign ("/") the equation output will be low when the input states defining one of the product terms (of that particular output) are true. IF (VCC) DC = AS'CS'DS'/ClK + AS'CS'DC'ClK Notice that "ClK" does not have a complement sign preceding it in the pIn list and therefore has the same representation in both the PLAN and the PAlASM equations. EXAMPLE NATIONAL SEMICONDUCTOR PLAN FORMAT PAL EQUATIONS PAl16R4D SClK ICS lAS NC1 IDTACK IEXST IADDW ClK NC2 GND IOE ISTERM IDC NC3 IDS IDA NC4 IENCAS I AREQ VCC IF (VCC) I AREQ = I AS' ICS'ClK + I AREQ' ICS' IClK IF (VCC) IENCAS = IAREQ'/CS'DC + I AREQ' ICS' IClK The sum-of-products boolean equations define an output to be true, given that one of the product terms in that output's equations is true. The symbols that make up the sum-ofproducts refer to the state of the input (or output). If a complement sign precedes the input (or output) symbol, in the equation, it means that the input (or output) must be low to be true (logic one). Notice that it does not matter whether the input (or output) pin has a complement sign preceding it or not, anytime a complement sign precedes an input (or output) symbol In an equation that symbol must be low to be true (logic one). IF (VCC) IDC = IAS'/CS'/DS'/ClK + I AS' ICS' IDC'ClK IF (VCC) ISTERM = IAS'/CS'/DA'DS'/ClK'/ADDW + I AS' ICS' IDTACK'DS'ClK' ADDW + I EXST* IClK + ISTERM'CLK Consider the following example (use the PAL pinout and equations listed below to identify the input and output pin names); IDA:= IAREQ'/CS'/DTACK'DS'/ADDW IDS:= IAREQ'/CS'/DTACK'/DA'DS'/ADDW + I AREQ' ICS' IDTACK*DS' I ADDW EXAMPLE EQUATIONS: IF (VCC) IDC = IAS'/CS'/DS'/ClK + I AS' ICS' IDC'ClK 4-3 ~ Interfacing the DP8420A/21A/22Atothe NS32008/016/C0161 032/132 National Semiconductor Application Note 542 Joe Tate and Rusty Meier INTRODUCTION $301 b: application note explains interfacing the This DP8420Al21 Al22A to the National Semiconductor 32C016. Two different designs are shown and explained. It is assumed the reader is familiar with the NS32C016 access cycles and the DP8420Al21A122A modes of operation. This application note is written for the NS32C016, but is also valid for the NS32008/016/032/132. = 55 ns @ 10 MHz = 66 ns - 5 ns - 26 ns - 2 ns = 33 ns @ 15 MHz DESIGN DESCRIPTION This design is a simple circuit to interface the DP8420Al21A122A to the NS32C016 and up to 32 Mbytes of DRAM. The DP8420Al21A122A is operated in mode O. An access cycle begins when the 32C016 asserts the ADS signal and places a valid address on the bus. The ADS signal places a group of 74AS373 fall-through latches in fallthrough mode and ADS negated latches the address to guarantee the address is valid throughout the entire access. The ADS signal is inverted to produce the signal ALE to the DP8420Al21A/22A. On the next rising clock edge, after the ALE signal is asserted,the DP8420Al21A122A will assert RAS. After guaranteeing the row address hold time, tRAH, the DP8420Al21 Al22A will place the column address on the DRAM address bus, guarantee the column address setup time and assert CAS. The transceivers are enabled by CS and AS. After tCAC, the DRAM will place the data on the bus. The DP8420Al21A122A will also take care of refresh access arbitration and will hold off the access by asserting the CWAIT Signal to the NS32C201 TCU. Timing parameters are referenced to the numbers shown in the DP8420A/21A/22A data sheet. Times beginning with a "$" refer to the DP8420Al21A122A data sheet. Times beginning with a "#" refer to the NS32C016 data sheet. Times beginning with a "!" refer to the NS32C201 data sheet in the 1986 Series 32000® data book. Equations given allow the user the calculation timing based on his frequency and application. The clock to the DELCLK has been chosen to be a multiple of 2MHz. If you do not have a clock, which is a multiple of 2 MHz, the ADS to CAS time must be recalculated. $302: $300: = Tcp10 = 100 ns @ ALE Pulse Width = T1 - Inverter Max - PHI1 to - CTTL to PHI1 = #tADSw = 25 ns @ 15 MHz $303 & $304: Address Setup to CLK = T1 - PHI1 to Address + AS373 in to out + CTTL to PHI1 Max) = Tcp - #tADSa - tphl - !tPCr = 100 ns - 50 ns - 6 ns - 2 ns = 42 ns @ 10 MHz = 66 ns - 35 ns - 6 ns - 2 ns = 23 ns @ 15 MHz $309: ALE Negated Held from CLK High = Min CLK to ADS + Min Inverter - CTTL to PHI1 Max = Min CLK to ADS + 1 ns - 2 ns = Min ClK to ADS - 1 ns @ 10 MHz = Min ClK to ADS - 1 ns @ 15 MHz • no time is specified for ClK to i\DS min.' $310: 10 MHz WIN Setup to CLK High to Guarantee CAS is Delayed = T1 + T2 - PHI1 to CTTL R.E. - DDIN Signal Valid - 74AS04 = 2Tcp - ltPCr - #tDDINv - tphl = 200 ns - 2 ns - 45 ns - 5 ns = Tcp15 = 66 ns @ 15 MHz = 148 @ 10 MHz CS asserted to CLK High = T1 - (PHI1 to address + AS373 in to Out + AS138 Decoder + CTTL to PHI1 Max + Inverter) = Tcp - #tALV - tphl - tphl - ltPCr = 100 ns - 50 ns - 6 ns - 9 ns - 2 ns = 66 ns ns - 35 = 14 ns @ flS - + 66 ns - 2 ns - 38 ns - 5 ns = 87 ns @ 15 MHz = 33 ns @ 10 MHz = 66 ADS = 30 ns @ 10 MHz DESIGN TIMING PARAMETERS Clock Period ALE Setup to CLK High = T1 - Inverter Max - PHI1 to ADS - CTTL to PHI1 = Tcp - tplh - #tADSa - ltPCr = 100 ns - 5 ns - 35 ns - 2 ns 6 ns - 9 ns - 2 ns 15 MHz 4-4 $315: 1 Wait State tRAC AREA Negated to ClK High that Starts Access RAS = T4 + T1 - PHI1 to CTTl R.E. - PHI1 to TSO High = 2Tcp - ItPCr - ItTr = 200 ns - 2 ns - 18 ns = = 180 ns 66 ns = 120 ns = = = 246 ns = 198 ns - 2 ns - 26 ns - 7 ns - 10 ns = 153 ns 15 MHz @ I = 23 ns @ 10 MHz = 27 ns + 0 ns - 6 ns - 5 ns = 16 ns @ 15 MHz = 58 ns = 66 ns - 2 ns - 31 ns - 5 ns = 28 ns 1 Wait States tCAC 10 MHz @ = 132 ns - 2 ns - 79 ns - 7 ns - 10 ns = 34 ns @ 15 MHz T2 + T3 - Max Clock Skew - ClK to CAS - Transceiver Delay - Data Setup = 3Tcp - !tPCr - $308a - tphl - #tDls = 300 ns - 6 ns - 79 ns - 7 ns - 15 ns = = 10 MHz 193 ns @ 10 MHz I = 100 ns @ 15 MHz RAS Precharge Parameters $29b: AREQ Negated Setup to ClK = Clock Period - Clock Skew PHI1 to CTTl - PHI1 to TSO = TCP - !tPCr - !tTr = 100 ns - 2 ns - 18 ns = 80 ns o Wait States = T2 + T3 - Max Clock Skew - ClK to RAS - Transceiver Delay - Data Setup = 2TCP - !tPCr - $307 - tphl - #lOls = 200 ns - 6 ns - 26 ns - 7 ns - 15 ns 146 ns @ 10 MHz tRP I = 2Tcp - !tPCr - $307 - tphl - #lOls 10 MHz @ 15 MHz Programmed Clocks - Clock Skew PHI1 to CTTl - PHI1 to TSO - [(AREQ to RAS Negated) - (ClK to RAS Asserted)] = 2TCP - ItPCr - ItTr - $50 = 200 ns - 2 ns - 18 ns - 16 ns = = 164 ns = 132 ns - 2 ns - 26 ns - 7 ns - 10 ns @ @ 66 ns - 2 ns - 10 ns = 54 ns = 87 ns I = 198 ns - 2 ns - 79 ns - 7 ns - 10 ns = = I + T3 - Max Clock Skew - ClK to RAS - Transceiver Delay - Data Setup 2Tcp - !tPCr - $308a tphl - #lOls 200 ns - 6 ns - 79 ns - 7 ns - 15 ns = 93 ns CWAIT Setup for Termination of Access = Clock Period - Max to PHI to CTTl - ClK to Wait High - 74AS32 = !TCP - !tTCr - $17 - tphl = 100 ns - 6 ns - 31 ns - 5 ns = 15 MHz @ N = T2 = tRAC AND tCAC TIMING FOR DRAMs Timing diagrams are supplied on page 8. Since systems and DRAM times vary, the user is encouraged to change the following equations to match his system requirements. Timing has been supplied for systems with 0 or 1 wait states. If DELClK is not a multiple of 2 MHz the ClK to CAS delay must be recalculated. tRAC 10 MHz @ ~ oWait States tCAC 'parameters $311 & 312 & 314 ensure WAIT will already be asserted @ + 66 ns - 2 ns - 10 ns CWAITTIMING ItCWs(W): CWAIT Setup for WAIT STATES = Min PHI1 Pulse Width + Min Clock Overlap - PHI1 to TSO - 74AS32 = !Tclw(1) + !tnOVl - !tTf - tphl = 40 ns + 0 ns - 12 ns - 5 ns ItCWs(W): I TW + T3 - Max Clock Skew - ClK to RAS - Transceiver Delay - Data Setup 3Tcp - !tPCr - $307 - tphl - #lOls 300 ns - 6 ns - 26 ns - 7 ns - 15 ns = T2 I 10 MHz @ + » z U1 @ 10 MHz 15 MHz II 4-5 ~ LI) !.... RAS low During Refresh tRAS = Programmed Clocks - [(ClK High to Refresh RAS Asserted) - (ClK High to Refresh RAS Negated)] = 2TCP - $55 =200ns-6ns - 194 ns @ 10 MHz = 132ns - 6ns =126ns@15MHz ADS ADDRESS DATA N' ...-- ODIN AO CASO- 3 RASO- 3 ADS MEMORY ENABLE " r" ~ 00-8,9,10 DP8420A/21A/22A WE Cs I- 74AS138 HBE ClK, DElClK AREO 32C016 WIN WAIT CTTL .-- TSO DBE ECASD,l ECAS2,3 HBE AO 32C201 CWAIT (f- - ~ let: EN DIRj+DIR!r"t- ~ 74AS245 " f'!- DATAI/O 'LATCHES ARE NOT NEEDED IF DP8420A/21A/22A INTERNAL lATCHES ARE USED. TL/F/9736-1 'Latches are not needed if DP8420A/21A/22A internal latches are used. 32C016 Up to 15 MHz 4·6 Design Programming Bits Bits Description Value RAS Precharge Time = RAS Low During Refresh = 2T 2T RD R1 = = 0 1 R2, R3 WAIT Generation Mode during Non-Burst Access R2 R3 u u R4, RS WAIT During Burst R4 RS = = = = 0 0 R6 ADD Wait States with WAITIN R6 = x R7 WAIT Mode Selected R7 Non-Interleaved Mode RB = = 0 RB R9 Staggered or all RAS Refresh R9 CO,C1, C2 Divisior for DELCLK ·Use a Multiple of 2 MHz External Clock CO C1 C2 RO, R1 1 = u = • = • = • =' = •• = •• = •• C3 +30 REFRESH C3 C4, CS, C6 RAS, CAS Configuration Mode • ·Choose an all CAS Mode, Tie a CAS to Each Nibble C4 C5 C6 C7 Select 0 ns Column Address Setup C7 CB Select 15 ns Row Address Hold CB = = C9 CAS is Delayed During Writes C9 = 1 1 1 BO Latches are Fall-Through BO = 1 B1 Access Mode 0 81 = 0 ECASO Non-Extend CAS Mode ECASO = 0 x = don't care u = user defined R2 R2 R9 R9 = = = = 0 1 0 1 R3 R3 = 1 = 0 for 0 WAIT STATES for 1 WAIT STATE all RAS refresh staggered refresh II 4-7 AN-S42 Design Timing # 1 T1 ,..---.. PHI1 T2 '''---'' T3 '''---'' T4 ''''--'' T1 ,...--. T2 '''---'' T3 TW T4 '''---'' I (TCU) CTTL (TCU) CLK (8420A) , ADS (cpu) ALE (8420A) TSO TCU I AREO (8420A) , ADDRESS (CPU) (8420A) .... .;, I I VALID : VALID WAIT (8420A) , CS, (8420A) , CWAIT (TCU) RAS (8420A) , CAS (8420A) 00-8,9,10 (8420A) COLUMN ACCESS #1 o WAIT STATES COLUMN ACCESS #2 1 WAIT STATE ·1 TL/F/9736-2 Design Timing #2 TI TI T1 T2 TW TW TW TW T4 T3 (:C~) ), CTIl I (TCU) , (842~~) ~ --r---v-- ADS (cpu) ALE (8420A) ____~__~r_\~__~--~--~--~--~------~ ~~~ +-------~------~------~ AREQ (8420A) (8i;~~l ADDRESS I , :---~-hr+-......;---...;..-~-~-~-.:.-----i j X i VALID i / ~,------------------~----~, ~ f' 1 (8420A) , <0 cst (8420A) , CWAIT (TCU) , RAS 2T RAS LOW (8420A) 2T PRECHARGE ' ~S (8420A) QO-(:4~O~) RFIP \ I l.---..A I (8420A) : ' : REFRESH ROW A VALID ROW: I COLUMN ~ I: ,l~-.; __ :/ :\ , ' I· ACCESS DURING DRAM REFRESH J l TL/F/9736-3 Access # 3 Access/Refresh Arbitration ltS-NV II N "It DRAM Speed Versus Processor Speed (DRAM Speed References the RAS Access Time, tRAC, of the DRAM Using DP8422A·25 Timing Specifications) 1.1) z• (.) z "" ...'""">< IIsono DRAM 13.4 (.) 0 ...J em 13MHz ::> 0 12MHz 11 MHz (.) 10 MHz DRAM KEY: l1.S m lOOn. DRAM 111120 n. DRAM 9.S~ D 150no DRAM 9 MHz S MHz NS32032 o WAIT STATES, 4 CLOCKS PER ACCESS NS32032 1 WAIT STATE, 5 CLOCKS PER ACCESS 4-10 TL/F/9736-4 National Semiconductor Application Note 543 Webster (Rusty) Meier Jr. and Joe Tate Interfacing the DP8420A/21A/22Atothe National Semiconductor NS32332 I INTRODUCTION This application note describes how to interface the National Semiconductor NS32332 microprocessor to the DP8422A DRAM controller (also applicable to DP8420Al21 A). There are four designs shown in this application note. The differences between these designs are as follows: 1. Design # 1 can be used up to 14 M Hz, has no wait states in normal accesses and no wait states in burst accesses, does not contain an MMU unit, is programmed with DTACKO out of the DP8422A, and has the 1W input of the PAL tied high, 2. Design # 2 can be used up to 15 MHz, has one wait state in normal accesses and no wait states in burst accesses, does not contain an MMU unit, is programmed with DTACK1 out of the DP8422A, and has the 1W input of the PAL tied high, 3. Design #3 can be used up to 14 MHz, has one wait state in normal accesses and no wait states in burst accesses, does contain an MMU unit, is programmed with DTACKO out of the DP8422A, and has the 1W input of the PAL tied high, 4. Design #4 can be used up to 15 MHz, has two wait states in normal accesses and no wait states in burst accesses, does contain an MMU unit, is programmed with DTACK1 out of the DP8422A, and has the 1W input of the PAL tied high, An extra wait state can also be added to any of the four above designs by tying the 1W input low. It is assumed that the reader is already familiar with NS32332 and the DP8422A modes of operation. II DESCRIPTION OF FOUR DESIGNS, ALLOWING UP TO 15 MHz OPERATION WITH 0, 1, OR 2 WAIT STATES IN NORMAL ACCESSES, NO WAIT STATES IN BURST ACCESSES AND AN OPTIONAL MMU (MEMORY MANAGEMENT UNIT, NS32382) These four designs are all similar. Taken together they allow the user to design a 32332 DRAM system with 0, 1, or 2 wait states during an access. This system can be designed with or without the NS32382 MMU. These designs are shown driving two banks of DRAM, each bank being 32 bits in width, giving a maximum memory capacity of 32 Mbytes (using 4 Mbit x 1 DRAMs). By choosing a different RAS and CAS configuration mode (see programming mode bits section of DP8422A data sheet), this application could support 4 banks of DRAM, giving a memory capacity of 64 Mbytes (using 4 Mbit x 1 DRAMs). The memory banks are interleaved on every four word (32bit word) boundary. This means that the address bit (A4) is tied to the bank select input of the DP8422A (B1). If the majority of accesses made by the NS32332 are sequential, the NS32332 can be doing burst accesses most of the time. Each burst of four words can alternate memory banks, allowing one memory bank to be precharging (RAS precharge) while the other bank is being accessed. This is a higher performance memory system than a non-interleaved memory system (bank select on the higher address bits). Each back to back memory access to the same memory bank will generally require extra wait states to be inserted into the CPU access cycles to guarantee the RAS precharge time. The logic shown in this application note forms a complete NS32332 memory sub-system, no other logic is needed. This sub-system automatically takes care of: A. arbitration between Port A, Port B, and refreshing the DRAM; B. the isertion of wait states to the processor (Port A and Port B) when needed (I.e., if RAS precharge is needed, refresh is happening during a memory access, the other Port is currently doing an access ... etc.); C. performing byte writes and reads to the 32-bit words in memory. By making use of the enable input on the 74AS373 latch, this application can easily be used in a dual access application. The addresses and chip select are TRI-STATEIil through this latch, the write input (WIN), lock input (LOCK), and ECASO-3 inputs must also be able to be TRI-STATE (a 74AS244 could be used for this purpose). By multiplexing the above inputs (through the use of the above parts and similar parts for Port B), the DP8422A can be used in a dual access applications. All the timing (see TIMING section of this application note) will remain the same whether single or dual accessing is implemented. If an MMU (NS32382) is used the signal "PAV" should be input to the PAL "ADS" input instead of the NS32332 ADS input. If wanted the user could input the MADS signal to the PAL (using the "NC1" input), allowing the access cycle to be started one clock earlier. When the PAL senses the MADS input transitioning low it can insert one less wait state into that particular access. The PAL output term D1 and the input term 1W can be deleted from the PAL if the user is not interested in adding an extra wait state to any of the four deSigns. Note: When driving 64 Mbytes, the timing calculations will have to be adjusted to the greater capacitive load. 4-11 III ~ "=" II) Z• ----+----+-C]Di6iA~A=>--1"""-C:::::iDiAAT~:>--t----1H=mDA~TAC:>--+----+----1 cs ADS ALE ADSL AREQ It-I IL-J ~ I h - DTACK 1 ~--~-----+-'Dl I,;,;.,-+_ _+--_-+-.....I I Dl I iii (PAL) ii2 (PAL) ROY - I BOUT WEN 1 WRITLEN RFIP RAS (1:0) RAS (3:2) I CASG (3:0) I B(I:0) ECAS (3:0) EN_TRAN I I i----READ ACCESS BANK 1 I READ ACCESS BANK 0 - - - - 1 TLlF19737-4 4-17 AN-543 CTR ADDRESS/DATil [jJ-LrL ~ ~ K-tL ~rL ~ rLrLr:-t-ili--rL I ADD DATA - DATA f!; PAl' ALI: ADSl: AREO It-- (PAL) D2 (PAL) ~ h DATA L J I I r- II Dl I 1..- t t ,-- Dl I I , ROY ~I ADD _ L-J DTACK 1 D1 _ .r- L - • BOUT • • • • • IL-- ~ I CASEN WRITLEN RAS (1:0) REFRESH I RFlP I \ RAS (3:2) \ CASG (3:0) \ II I I \ r- \ I I _II B(I:0) ECAS (3:0) ElLmAN I I BURST READ ACCESS I ACCESS DURING DRAM REFRESH TUF/9737-5 Design # 2: 32332 with One Wait State per Access (Non-Burst. DTACK1 Programmed). No MMU. PAL Input 1W Tied High cm I ADDRESS/DATA VIR I PH1 DATA I I VIR ~ rL}L rL DATA PHY CS PAV .L-..J L-..J I ALE I I ADSL AREO r- DO 100 DTACK 0 D1 (PAL) 52 (PAL) J • ROY BOUT CASEN L..-.~ • I • II • ,r- 1 I WRITE-EN RFIP RAS (1:0) RAS (3:2) CASG (3:0) B(1:0) r \ \.-- ~ """'\ 2 ECAS (3:0) EN_TRAN I II I WRITE ACCESS BANK 0 READ ACCESS BANK 1 . TLlF/9737-6 Design # 3: 32332 with MMU and One Wait State per Access (Non-Burst), PAL Input 1W Tied High 4-19 AN-543 r-LrL rL rL- rLrLrL rL rLr--Lf--t~ r-L ~ ~ "A- rL em I ADDRESS/DATA VIR PHY I DATA TA I)j _ VIR II """ DATA PHY _ CS PAY L-J ALE I II II ADSL II II II IL.1.---- :.---- AREQ 1 00 DTACK 0 iii (PAL) D2 (PAL) I ROY ~I , I ~ I t t I BOUT I Dl , , , , , , , r - It--- .--- I I CASEN ,-- r-~ WRITLEN \ RflP I \ RAS (1:0) REfRESH I I \ \ , I RAS (3:2) 1'-- I r - CASG (3:0) I 8(1:0) - \ 1,-- ECAS (3:0) EtLlRAN r- \ . BURST READ ACCESS ACCESS DURING DRAM REFRESH , TL/F/9737-7 Design # 3: 32332 with MMU and One Wait State per Access (Non-Burst), PAL Input 1W Tied High CTTL ADDRESS/DATA ~rL.~~r-L-rLt-t- r-i...J VIR PHY DATA CS - _ VIR l..-J PAV I PHY DATA L-..J ALE II ADSL LJ .J r- AREa Dl DTACK 1 I r- tDl iii (PAL) in (PAL) J ~ RDY ~I ~ t Ii ~ II-t- L- BOUT CASEN ~ WRITLEN RFIP RAS (1:0) \ RAS (3:2) \ r I CASG (3:0) B(l:O) I2 2\ ECAS (3:0) EN_TRAN I READ ACCESS BANK 1 . I READ ACCESS BANK 0 TLfF/9737-8 Design #4: 32332 with MMU and Two Wait States per Access (Non-Burst, DTACK1 Programmed), PAL Input 1WTied High &tS-NY II AN-543 ~ A~SftM~t:K:~~:J~:J~-r------1-~:m~:>-1~<:~~~-r~:i~C:~~>--1-------t-------r------1-------t-----1~:Ji$c:J '~~I-----+-----+----~----~----~~----~----~----+-----+-----~----~----~----~-----+-----+-----+----~----~----~ PAY I~ • ALE AiiSl '---I r---- L L -' ~ I AREO , I I I I ~DI DTACK 1 1'01 iii (PAL) I I Ir;:: D2 (PAL) ~ RDY ~I BOuf CASEN h Ir---1----IJ II WRITLEN iifip REfRESH I , HAS (1:0) \ -+-----+---+--+---+--+-~ r-, , '---~-+--~-+-,I~ \ HAS (3:2) CASG (3:0) I I I I ~ I I~ I I I I I I I ~ I I' I I 8(1:0) ECAS (3:0) II EN_TlWi I• I BURS\" READ ACCESS LJ -1• ACCESS DURING DRAM REfRESH -I lLIF/9737-9 Design #4: 32332 with MMU and Two Walt States per Access (Non-Burst, DTACK1 Programmed), PAL Input 1WTled High ..:r: .---------------------------------------------------------------~~ Dram Speed Vs. Proceasor Speed, (Dram Speed References the RAS Acceas Time, tRAC, of the Dram, using DP8422A-25 Timing Specifications) en Co) 1611Hz >u z '"::> ...'",.."" 1511Hz 15 14MHz 14.1 1311Hz 12.3 a ...uu 0 1211Hz II e DRAII KEY: SOns DRAII 111100 nl DRAII 111120 nl DRAM 1111Hz 10.4R 10MHz D 150nl DRAM 911Hz SIIHz HS32332 o WAIT STATES. " CLOCKS PER ACCESS TL/F/9737-10 II 4·23 .- .-------------------------------------------------------------------------------------, ;1; Interfacl"ng'the Z c:( DP8420AI 21 AI 22A to the National Semiconductor NS32532 1.0 INTRODUCTION This application note describes how to interface the Nation· al Semiconductor NS32532 microprocessor to the DP8422A DRAM controller (also applicable to DP8420Al21 A). It is assumed that the reader is already fa· miliar with NS32532 and the DP8422A modes of operation. 2.0 DESCRIPTION OF DESIGN, ALLOWING UP TO 25 MHz OPERATION WITH 2 OR 3 WAIT STATES IN NORMAL ACCESSES AND 1 WAIT STATE DURING BURST ACCESSES This design drives two banks of DRAM, each bank being 32 bits in width, giving a maximum memory capacity of 32 Mbytes (using 4 Mbit x 1 DRAMs). By choosing a differ· ent RAS and CAS configuration mode (see programming mode bits section of DP8422A data sheet) this application could support 4 banks of DRAM, giving a memory capacity of 64 Mbytes (using 4 Mbit x 1 DRAMs, NOTE that when driving 64 Mbytes the timing calculations will have to be adjusted to the greater capacitive load). The memory banks are interleaved on every four word (32· bit word) boundary. This means that the address bit (A4) is tied to the bank select input of the DP8422A (B 1). If the majority of accesses made by the NS32532 are sequential, the NS32532 can be dOing burst accesses most of the time. Each burst of four words can alternate memory banks, al· lowing one memory bank to be precharging (RAS pre· charge) while the other bank is being accessed. This is a higher performance memory system than a non·interleaved memory system (bank select on the higher address bits). Each separate memory access to the same memory bank will generally require extra wait states to be inserted into the CPU access cycles to allow for the RAS precharge time. This design supports the NS32532 burst access operations. To support these operations it is assumed that nibble mode DRAMs will be used. (See the timing calculations, Section IV). National Semiconductor Application Note 541 Webster (Rusty) Meier Jr. and Joe Tate ~ The logic shown in this application note forms a complete NS32532 memory sub·system, no other logic is needed. This sub·system automatically takes care of: A arbitration between Port A, Port B, and refreshing the DRAM; B the insertion of wait states to the processor (Port A and Port B) when needed (i.e., if RAS precharge is needed, refresh is happening during a memory access, the other Port is currently doing an access ... etc); C performing byte writes and reads to the 32·bit words in memory. The Confirm Bus Cycle (CON F) signal is input to the DP8422A Chip Select (CS) input. Therefore the CONF sig· nal disables the current access, from the DP8422A, if the NS32532 has cancelled it (CONF high setup to ADS tran· sitioning low). The PAL starts an access via the DP8422A by pulling the ADS, AREQ inputs low. These inputs are brought low given that CS and Begin Memory Transaction (BMT) are both low. By making use of the enable input on the 74AS244 buffer, this application can easily be used in a dual access applica· tion. The addresses and chip select are TRI·STATE® through this buffer, the write input (WIN), lock input (LOCK), and ECASO-3 inputs must also be able to be TRI·STATE (another 74AS244 could be used for this purpose). By multi· plexing the above inputs (through the use of the above parts and similar parts for Port B) the DP8422A can be used in a dual access application. If this design is used in a dual ac· cess application at 25 MHz the tRAc and tCAC (required RAS and CAS access time required by the DRAM) will have to be recalculated since the time to RAS and CAS is longer for the dual access application (see TIMING section of this application note). 4·24 r--------------------------------------------------------------------,~ 2b Minimum address setup time to ADS low (DP8422A-25 needs 14 ns): 3.0 NS32532 DESIGN, UP TO 25 MHz WITH 2 OR 3 WAIT STATES DURING NORMAL ACCESSES AND 1 WAIT STATE DURING BURST ACCESSES, PROGRAMMING MODE BITS Programming Bits RO Rl R2 R3 = = = = R4 R5 R6 =0 =0 =0 R7 R8 R9 CO Cl C2 = = = = = = 1 1 X X X X = = = = C7 C8 C9 = 1 = 1 = 1 3a Minimum CS setup time to ClK high (PAL 16R4D needs 10 ns): 40 ns (one clock period) - 8 ns (maximum time to address valid from SClK high) - 6.2 ns (74AS244 buffer delay maximum) - 9 ns (max 74AS138 decoder) = 16.8 ns 3b Minimum CS setup time to ADS low (DP8422A-25 needs 5 ns): a Minimum time to ADS low (see #2a from above) = 42 ns b Maximum time to CONF (CONF is tied to CS of the DP8422A) = 20 ns (one half clock period) + 9 ns (CONF low from falling clock edge) = 29 ns maximum Therefore: 42 ns (minimum time to ADS low) - 29 ns (maximum time to CONF low) = 13 ns Select based upon the input "DElClK" frequency. Example: if the input clock frequency is 20 MHz then choose CO,l ,2 = 0,0,0 (divide by ten, this will give a frequency of 2 MHz). If using the DP8422A over 20 MHz do an initial divide by two externally and then run that output into the DElClK input and choose the correct divider. X 0 0 1 SO = 1 Sl = 1 ECASO = 0 o= Description RAS low four clocks, RAS precharge of three clocks. DTACKl is chosen. DTACK low first rising ClK edge after access RAS is low. No Wait states during burst accesses. If WAITIN = 0, add one clock to DTACK. Since we are not using the WAITIN input it should be tied high on the DP8422A. Select DTACK Non-Interleaved Mode 1 1 1 0 C3 C4 C5 C6 42 ns (#2a above) - 8 ns (max time to address valid from SlCK high) - 6.2 ns (74AS244 buffer delay max) = 27.8 ns 4 Determining tRAG during a normal access (RAS access time needed by the DRAM): 160 ns (four clock periods to do the access) - 8 ns (PAL 16R4D clocked output) - 29 ns (ADS to RAS low) - 10 ns (NS32532 data setup time) - 7 ns (74F245) = 106 ns Therefore the tRAG of the DRAM must be 106 ns or less. 5 Determining tGAG during a normal access (CAS access time) and column address access time needed by the DRAM: 160 ns - 8 ns - 10 ns - 7 ns - 75 ns (ADS to CAS low on DP8422A-25, 50 pF spec) - 12 ns [74AS32, 6 ns, plus 6 ns extra, taken from lab data on the 74AS32, for drYing a 220 damping resistor and 150 pF of capacitance associated with driving 16 DRAM CAS inputs (per CAS output)) = 48 ns RAS groups selected by "S 1". This mode allows two RAS outputs to go low during an access, and allows byte writing 32-bit words. Column address setup time of 0 ns. Row address hold time of 15 ns. Delay CAS during write accesses to one clock after RAS transitions low. Fall-thru latches Access Mode 1 CAS not extended beyond RAS. Therefore the tGAG of the DRAM must be 48 ns or less. 6 Determining the nibble mode access time needed during a burst access: 80 ns (two clock periods to do the burst) - 20 ns (one half clock period during which CAS is high from the previous access) - 10 ns (PAL16R4D combinational output from ClK input falling edge, ENCAS) - 12 ns (74AS32 delay to produce CAS from the ENCAS input, see description from # 5) - 10 ns (NS32532 data setup time) - 7 ns (74F245) = 21 ns program with low voltage level 1 ~ X = program program with high voltage level Therefore the nibble mode access time of the DRAM must be 21 ns or less. with either high or low voltage level (don't care condition) NS32532 TIMING CALCULATIONS FOR DESIGN AT 25 MHz WITH 3 WAIT STATES DURING THE NORMAL ACCESSES AND 1 WAIT STATE DURING BURST ACCESSES 7 Maximum time to DTACKl low (PAl16R6D needs 10 ns setup to SClK): 40 ns (one clock) - 28 ns (DTACKl low from ClK high on DP8422A-25) = 12 ns Minimum ADS low setup time to CLOCK high for DTACK logic to work correctly (DP8422A-25 needs 25 ns): 8 Minimum RDY setup time to SClK (19 ns to SClK rising edge is needed by the NS32532): 40 ns (one clock period) - 8 ns (PAL 16R4D clocked output maximum) = 32 ns 40 ns (one clock period) output maximum) = 32 ns 2a Minimum time to ADS low = 40 ns (one clock period) + 2 ns (minimum clocked output delay of PAL 16R4D PAL) = 42 ns minimum 8 ns (PAL 16R4D clocked Note: Calculations can be performed for different frequencies by substituting the appropriate values into the above equations. 4-25 ZI (II ~ ..... ..... i .---------------------------------------------------------------------------------~ 5.0 NS32532 DESIGN, PAL EQUATIONS WRITTEN IN NATIONAL SEMICONDUCTOR PLAN FORMAT PAL16R40 BCLK ICS lADS IBOUT 10TACK IEXROY 13W CLK IBMT GNO IOE NC1 lOB NC2 IROY IDA I AREa IENCAS I AOSL VCC IF (VCC) IAOSL = lADS +/AOSL"/CLK + I AOSL "/BOUP ICS +/AOSL"ROY"/CS IF (VCC) IENCAS = IAREa"/CS"OB + I AREa· ICLK· ICS IF (VCC) lOB = IAREa"/BOUP/ROY·/CLK + I AREa· IBOUP10B'CLK IAREa:= IAOSL·/BMP/CS + I AOSL· I AREa· ICS 10A:= IAOSL·/AREa·/OTACK·OA·/3W·/CS IROY:= IAREa·/OTACK·/AOSL·/OA·/CS·/3W + I AREa· 10TACK' I AOSL ·ROY· ICS·3W +/EXROY Key: Reading PAL equations written In PLAN EXAMPLE EaUATIONS: IF (VCC) lOB = IAREa·/BOUP/ROY·/CLK + I AREa· IBOUP10B·CLK This example reads: the output "lOB" will transition low given that one of the following conditions are valid; 1) the output "/AREa" is low AND the input "/BOUT" is low AND the output "/ROY" is low and the input "CLK" is low, OR 2) the output "/AREa" is low AND the input "I BOUT" is low AND the output "lOB" is low and the input "CLK" is high. 4·26 NS32532 D••lgn, up to 25 MHz, with 2 or 3 Walt Stat•• In Normal Ace..... and 1 Walt Stat. In Bur.t Ace..... n .... 74AS244 BUFFERS I I ~ I RO-l0 CO-I 0 BO,I 74AS138 DECODER I ~ 7 WIN WRITLEN BEO-3 NS32532 ... ADDRESS BUS 0 .1 DRAW CS (TO PAL) ~ ECASO-3 4 BCLK DELCLK, CLK CONF CS DP8422A RASO 1 2 00-10 11 RAS2 3 2 WE 2 BANKS OF 32 BITS OF DRAW DTACKI cs ADS 32532 PAL ADS AREQ BOUT 1 AREQ CASGO-3 BWT ENCAS ROY .. 1"- SRW~""'-' AREQ FROW PAL WRITE....EN~ OATAO-31 "v '1 DIR 0 TRANCEIVERS 74F245 t,4 ' 4 -CASO-3DENCAS J .. :.. 74AS32 DATAO-31 'I TL/F/9735-1 • 4·27 AN-541 NS32532 with 2 Wait States per Access (One Wait State during Burst Accesses), 3W Input of PAL is Tied High Tl BCLK ADDRESS DATA T2 WI r-L rL. rL. - W2 n-n-rL LJ BtotT ',~J CONF 1---, ADSL -, WI W2 Tl r-L rL. rL. JI. lI. ADS Tl JI. T1 T2 WI W2 n-r-L r-Ln-~ r-!L.. rL. - JI. ~ rt-J IL-J L.....J T/ r!i:.rtlI. .r-- - L...J I I I I AREO DTACKI I I iiA(PAL) ~I iii (PAL) l- ROY I --.rn 1- I '.-- BOUT ENCAS I r- h , I ~ h Ir\ 1\ WRITLEN RFIP RAS(I:0) RAS(3:2) CASG(3:D) , B(1:0) I '-- , I 1 2'\ 12 ECAS(3:0) ...- - - WRITE ACCESS BANK 0 READ ACCESS BANK 1 -I"'A"M~ MI! BURST ACCESS BANK 0 TL/F/9735-2 NS32532 with 2 Wait States per Access (One Wait State during Burst Accesses), 3W Input of PAL is Tied High Tl BCLK T2 rL rL ADDRESS WI W2 W3 W4 W6 WS W7 W8 W9 Wl0 Wll - I DATA ADS LJ BMT ~~ ADSL , AREO J CDNF TI r----r----r---- ~ r L r Lr---- ~ r Lr----r-t- r--L r-- Jl r-- I DTACKI ~ iiA(PAL) iiii(PAL) ful ROY J L-J r-- BOUT ENCAS I -' WRITCEN RFlP RAS(I:0) h f-I RAS(3:2) CASG(3:0) B(I:0) REFRESH 3T PRECHARGE \ f \ f 3T PRECHARGE '\ ~ f2 2 I ECAS(3:0) ACCESS DURING DRAM REFRESH TUF/9735-3 ~tS-N" -iii _ ~ r---------------------------------------------------------------------------------~ NS32532 with 3 Walt States per Access (One Walt State during Burst Accesses), 3W Input of PAL Is Tied Low Z CC n-n-rt- r L n-n-rt- r L n-n-nTl BCLK ADDRESS T2 Wl W2 T1 W3 T2 Wl W2 W3 TI DATA ADS I--.J BMT ~~ CONF ADSL ~ L...~ -., r---. , I r-- I I AREQ II DTACKl I rr- fiA(PAL) - ilii(PAL) ROY L-~ BOUT ENCAS I I ,--- 1- WRITLEN RFIP RAS(1:0) RAS(3:2) CASG(3:0) B(1:0) I " r- " r-- I 2 " 2 ECAS(3:0) READ ACCESS BANK 1 READ ACCESS BANK 0 TL/F/9735-4 4-30 ,----------------------------------------------------------------, NS32532 with 3 Walt States per Access (One Walt State during Burst Accesses), 3W Input of PAL is Tied Low ~ ZI U1 BCLK ADDRESS WI W2 W3 T2B BMT 11r--t ADSL ~ TI "'" ~ CONF T2BW - - I DATA ADS ..... "" r-L r--Lrt-rur--L r--LIL-rtT2 ~ Ir-II Ir-- AREQ DTACKI r-- I DA(PAL) iiB(PAL) L ROY f-l Ir-- ~V- BOUT ENCAS II WRITE-EN RFIP RAS(I:0) , ~ RAS(3:2) II\. CASG(3:0) r-- B(I:0) ECAS(3:0) BURST ACCESS BANK 0 TL/F/9735-5 4-31 AN·541 NS32532 with 3 Wait States per Access. 3W Input of PAL is Tied Low T1 BCLK ADDRESS DATA ADS BMT CONF ADSL AREQ DTACK1 ~I rL T2 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 TI TI TI TI r-t-r-t-r-t-n.- r L r L r-t-r-t-r-t- r L r L r L r-t-r-t- r--L. r L ~ ,- X JI. .....,. 'L- L-.J ~~ IlL 11 L IJ I....J I iiA (PAL) L......... DB (PAL) ROY ~J I BOUT ENCAS lJ I I WRITLEN RFIP RAS(1:0) '--' ...J RAS(3:2) CASG(3:0) REFRESH PRECHARGE '\ '\ I 4T REFRESH I 3T PRECHARGE f '\ I J '\ B(1:0) ECAS(3:0) , ACCESS DURING DRAM REFRESH IDLE CACHE HIT • liT TLIF19735-6 » z DRAM Speed Vs. Processor Speed, (DRAM Speed References the RAS Access Time, tRAC, of the DRAM, using DP8422A-25 Timing Specificatons) 25 MHz I U'I ~ ..... 25 24MHz 23 MHz 23 22 MHz 21 MHz 20MHz >(.) :z :::> '" 0 '" .... '" '"0 (.) 20 DRAM KEY: 19 MHz 18MHz 1180ns DRAM 17MHz m 16MHz lOOns DRAM 15MHz ..J (.) 14MHz 11120 ns DRAM 13MHz 12 MHz D 11 MHz 10 MHz 150ns DRAM 9 MHz BMHz NS32532 3 WAIT STATES, 5 CLOCKS PER ACCESS TL/F/9735-7 • 4·33 ~ A Dual Access NS32532 Error Detecting and Correcting Memory System National Semiconductor Application Note 540 Webster (Rusty) Meier, Jr. and Joe Tate I. INTRODUCTION During read accesses the data is always processed through the 74F632 EDAC chip (i.e., the EDAC data buffers are enabled to provide the data to the CPU). The 74F632 is always put into latch and correct mode during read accesses, even though the data from the memory may be correct. This allows CAS to be toggled early (before the CPU has sampled the data), during burst mode accesses, to start accessing the next word of the burst access. This design drives two banks of DRAM, each bank being 39 bits in width (32 data bits plus 7 check bits) giving a maximum memory capacity of 32 Mbytes of error corrected memory (using 4 Mbit x 1 DRAMs). By choosing a different RAS and CAS configuration mode (see programming mode bits section of DP8422A data sheet) this application can support 4 banks of DRAM, giving a memory capacity of 64 Mbytes (using 4 Mbit x 1 DRAMs, NOTE that when driving 64 Mbytes the timing calculations will have to be adjusted to the greater capacitive load). The memory banks are interleaved on every four word (32bit word) boundary. This means that the address bit (A4) is tied to the bank select input of the DP8422A (B 1). Address bits A3,2 are tied to the least significant column address inputs (Cl,O) to support burst accesses using nibble mode DRAMs. Address bits A 1,0 are used to produce the four byte select data strobes, used in byte reads and writes. If the majority of accesses made by the NS32532 are sequential, the NS32532 can be doing burst accesses most of the time. Each burst of four words can alternate memory banks (address bit A4 tied to DP8422A pin Bl), allowing one memory bank to be precharging (RAS precharge) while the other bank is being accessed. This is a higher performance memory system than a non-interleaved memory system (bank select on the higher address bits). Each separate memory access to the same memory bank will generally require extra wait states to be inserted into the CPU access cycles to allow for the RAS precharge time. This appendix describes how to interface two NS32532 microprocessors, both synchronous to the same system clock, to a DP8422A DRAM controller and a 74F632 EDAC chip. It is assumed that the reader is already familiar with NS32532, the DP8422A, and the 74F632 modes of operation. The National Semiconductor DP8420A can be used in place of the 74F632, though its timing is slower. This application note supports the following types of memory accesses: 1. Read accesses with 6 wait states inserted (8 clock periods total in the synchronous mode read access), any single bit errors are automatically corrected before sending the data to the CPU (EDAC unit in always correct mode); 2. Write accesses with 3 wait states inserted (5 clock periods total in the synchronous mode write access); 3. Byte write accesses with 7 wait states inserted (9 clock periods total in the synchronous mode byte write access); 4. Burst read accesses with 3 wait states in the burst portion of the access (4 clock periods total per synchronous mode burst read memory access); 5. Scrubbing during DRAM refreshes (6 clock periods total during the refresh if no errors, 8 clock periods total during the refresh if any errors), any single bit errors are corrected. The corrected word is then written back to the DRAM. II. DESCRIPTION OF 25 MHz DUAL ACCESS NS32532 SYSTEM INTERFACED TO THE DP8422A AND THE 74F632 This design allows two NS32532 microprocessors to access a common error corrected dynamic memory system. The error corrected memory system is implemented using the 74F632 EDAC chip in the always correct mode. Whichever NS32532 accessed the memory last has a higher priority. Both NS32532s are interfaced to the DRAM and allow the DRAM system to support burst mode accesses. This design is very similar to the 68030 dual access EDAC design and the PALs will be very similar. The reader can refer to that design to see the timing waveforms, block diagrams, and simulations. The only necessary changes to the 68030 design are that the STERMA,B PAL outputs will have to be modified to support the NS32532 RDY inputs, and the AREQ, AREQB outputs of the PALs will have to take ADS, CS, and CONF into consideration (not just ADS, CS as in the 68030 design). The user should also be careful not to violate the DP8422A parameter #416 (AREQ negated to ADS asserted to guarantee tASR = 0 ns) when generating the AREQ, AREQB PAL outputs. During read accesses the data is always processed through the EDAC chip (always correct type of system). If a single bit error occurs during a read access this design guarantees correct data to the CPU, but does not write the corrected data back to Ine DRAM. Singie bit soft errors in memory are only corrected (written back to memory) during scrubbing type refreshes. The memory is scrubbed often enough that the probability of accumulating two soft errors in memory is very unlikely. The logic shown in this application note forms a complete NS32532 memory SUb-system, no other logic is needed. This sub-system automatically takes care of: A. arbitration between Port A, Port B, and refreshing the DRAM; B. the insertion of wait states to the processor (Port A and Port B) when needed (i.e., if RAS precharge is needed, refresh is happening during a memory access, the other Port is currently doing an access ... etc.); C. performing bytes write and reads to the 32-bit words in memory; D. normal and burst access operations. By making use of the enable input on the 74AS244 buffer, this application allows dual access applications. The addresses and chip select are TRI-STATE through this buffer, the write input (\"-IIN), lock input (LOCK) ana ECASO-3 inputs must also be able to be TRI-STATE (another 74AS244 could be used for this purpose). By multiplexing the above inputs (through the use of the above parts and similar parts for Port B) the DP8422A allows dual accessing to be performed. 4-34 III. NS32532 25 MHz DUAL ACCESS EDAC DESIGN: THE EDAC ERROR MONITORING METHOD IN CONJUNCTION WITH THE NS32532 BUS RETRY FEATURE The NS32532 dual access EDAC system design can use the error monitoring method in conjunction with the NS32532 bus retry feature, instead of the always correct method (design shown in the NS32532 application note). The error monitoring method can yield a slight improvement in system performance. IV. NS32532 25 MHz DUAL ACCESS DESIGN, PRO· GRAMMING MODE BITS Programming Bits By using the error monitoring method of error correction single read accesses or the first read access during a burst access can be shortened by one clock period, allowing a synchronous read access to have only 5 wait states inserted, 7 clock periods total (compared to 6 wait states, 8 clock periods total when dOing the always correct method). All other types of accesses (burst reads, bytes writes, word writes, refresh scrubbing) will execute in the same number of clock cycles, and in the same manner as described in this application note. Read accesses can save one wait state because the data from the DRAM memory is assumed to be correct in the error monitoring system deSign. Therefore the DRAM data is given directly to the CPU instead of running it through the EDAC chip as was done in the always correct method. RAS low four clocks, RAS precharge of three R2 = 1 R3 = 0 'i5'fAOO is chosen. i5iAOR low first rising R4 = 0 R5 = 0 No WAIT states during burst accesses R6 = 0 If WAITIN = 0, add one clock to DTACK. WAITIN may be tied high or low in this application depending upon the number of wait states the user desires to insert into the access. Select DTACK R7 = 1 clocks ClK edge after access RAS is low. R8 = 1 R9 = X Non-interleaved Mode CO = 1 C1 = X C2 = X Selected based upon the input "DElClK" frequency. Example: if the input clock frequency is 20 MHz, then choose CO,1 ,2 = 0,0,0 (divide by ten, this will give a frequency of 2 MHz). If DElClK of the DP8422A is over 20 MHz do an initial divide by two externally and then run that output into the DElClK input and choose the correct divider. In order to do this design it is required that the bus retry feature of the NS32532 and registered transceivers be employed. The bus retry feature of the NS32532 involves pulling the NS32532 input signal "BRT" low before the end of state T2 or T2B. Given that this is done the NS32532 will complete the bus cycle normally, but will ignore the data read in the case of a read cycle. The CPU will then wait for BRT to transition high before repeating the bus cycle (unless that access is not currently needed by the CPU). This feature is useful for the case where an error is detected in the DRAM data. In this case BRT is brought low until the data from the DRAM is corrected (by the EDAC chip) and written back to the DRAM. BRT is then brought high to continue CPU processing. Registered transceivers are necessary (in place of the 74F245's shown in the block diagram) during burst mode read accesses because CAS transitions high before the CPU has sampled the DRAM data. The registered transceivers hold the data valid until the CPU samples it during these cases. A read, read with a single bit error, and burst read access timing are shown at the end of this appendix implementing the error monitoring method. The user can see how these access cycles differ from the always correct method access cycles shown in the 68030 dual access EDAC application note. Description RO = 1 R1 = 1 C3 C4 C5 C6 = X = 0 = 0 = 1 C7 = 1 C8 = 1 C9 = 1 BO = 1 B1 = 1 ECASO = 0 o~ 1 X ~ ~ RAS groups select by "B1 ". This mode allows two RAS outputs to go low during an access, and allows byte writing in 32-bit words. Column address setup time of 0 ns Row address hold time of 15 ns Delay CAS during write accesses to one clock after RAS transitions low Fall-thru latches Access mode 1 Non-extend CAS mode Program with low voltage level Program with high voltage level Program with either high or low voltage level (don't care condition) II 4-35 C. Worst case time to DRAM data valid: 144 ns (from "S" above, maximum time to~) +50 ns ("CAS access time "tCAC"for a typical 100 ns DRAM) = 194 ns O. Worst case time to data valid on the EOAC data bus: 194 ns (from "c" above) + 7 ns (74AS244 maximum delay) = 201 ns E. Worst case time until the error flags are valid from the 74F632: 201 ns (from "0" above) + 31 ns (74F632 maximum time to error flags valid) = 232 ns F. Worst case time until corrected data is valid from the 74F632: 201 ns (from "0" above) + 28 ns (74F632 maximum time from data in to correct data out) = 229 ns G. Worst case time until corrected data is available at the CPU: 229 ns (from "F" above) + 7 ns (74F245 maximum delay) = 236 ns v. NS32532 25 MHz WORST CASE TIMING CALCULATIONS The worst case access is an access from Po"rt B. This occurs because the time to RAS and CAS low is longer for the Port B access than a Port A access, a refresh with scrubbing access, or an access which has been delayed from starting (due to refresh, RAS precharge time, or the other Port accessing memory). A. Worst case time to RAS low from the beginning of an access cycle: 40 ns (T1 clock period of NS32532) + 10 ns (PAL 16R40 maximum combinational output delay to produce AREaB) + 41 ns (OP8422A-25 parameter # 102, AREa to RAS delay maximum) = 91 ns B. Worst case time to CAS low from the beginning of an access cycle: 40 ns + 10 ns + 94 ns (OP8422A-25 parameter # 118a, AREaB to CAS delay maximum) = 144 ns 4-36 » z . EDAC Memory-Control Logic in this System Needs the Following: 3 PALS and Some Logic Gates (II .Il1o o CLOCK GENERATOR + 2 2 NS32532 + ADS CS ODIN BOUT CONF RDY,BIN 3 J 'I ADS, CS, ODIN I. CONTROL LOGIC BRT 4 ~ AREQ, PORT A ENABLE ~ ENCAS I~ II 1 I + 3 2 2 BOUT, CONF ROY, BIN BRT NS32532 PORT B ENABLE DATA STROBES GRANTB, ATACKB.LDTACK,RFIP 4 4 CLK DELCLK DATA 4 STROBES 4 ILO ..::; ::"1 ADDRESS 2-25 DATA STROBES 4 l .1\ BUFFERS 74AS244 V LOCK PORTA ROW,COLUMN BANK ADDRESS / I 1'\ V I FROM CONTROL LOGIC IWE I L I TRANSCEIVER ENABLES FROM CONTROL LOGIC 4 I BIDIRECTIONAL -'\ DATA FROM CPU V '" EN 39 BITS OF DATA+ CHECKBITS 1\ 11 5 BUFFERS 74AS244 0 A T A 32 DRAM BUFFERS B I T S I DATA + CHECK BITS ED~~Eg~~~T & l"l BUS '7 EDAC MODE, LATCH AND BUFFER CONTROL ERROR FLAGS 'I ! ~ DATA 0-31 I 81 FROM 'l CONTROL LOGIC I 2.- I _KEN ~ DATA + CHECKBITS INTO MEMORY 111 74F632 i LJ\ '-----V BUFFER ENABLE FROM CONTROL LOGIC V DIR ;::.. 1'<: ADDRESS 2-25 \I EDAC UNIT PORTA EN DIR Ill4 74F245 N"' = A 74AS244 " = B I T S PORTB ROW,COLUMN BANK ADDRESS MULTIPLEXED ADDRESS 00-10 11 DRAM MEMORY UP TO 4 BANKS OF 39 BITS (DATA + CHECK BITS 39) USING 41.1 X 1 DRAMS 641.1 BYTES OF ERROR CORRECTED DRAM ILO BUFFERS A 1~~4Ii~4 0 A T A 32 4 LOCK DP8422A TO CONTROL LOGIC PORT B RjW 4 74F245 ~ "'~ Zz I >Vl "'n r-", rnfSi 4,/ '" ENt=TLlF/9734-1 FIGURE 1.NS32532 Dual Access EDAC Memory System Using the Always Correct Method (see Section III for how Block Diagram Changes for Error Monitoring Method) II 4-37 ~ I Z READ ACCESS (NO ERROR) c:r: Tl T2 WI W2 W3 READ ACCESS W4 W5 T1 T2 WI SINGLE BIT ERROR W2 W3 W4 W5 WRITE BACK Al A2 n BCLK WE to DRAWs ROY RASn CASn DATA ON EDAC BUS OECB E 0 A C U N I T ERR FLAG OEBO-3 50,51 LEDBO = DRAW BUFF_EN TRAN_EN BRT TLIF 19734-2 FIGURE 2. NS32532 Dual Access EDAC System Timing @ 25 MHz (DP8422A-25 74F632) Error Monitoring Method Using the Bus Retry Input of the NS32532 and Registered Transceivers 4-38 READ WITH BURST BURST » z I BURST (II 0l:Io- o T1 T2 W1 W2 W3 W4 W5 B1 WB1 WB2 WB3 B1 WB1 WB2 WB3 TI BCLK ADS,AREO CONF WE to ORAt.4s ROY RASn CASn DATA ON EOAC BUS OECB E 0 A C U N I T ERR FLAG OEBO-3 SO,Sl LEOBO = ORAt.4BUFF_EN TRAN_EN BRT TL/F/9734-3 FIGURE 3. NS32532 Dual Access EDAC System Timing @ 25 MHz (DP8422A-25, 74F632) Error Monitoring Method Using the Bus Retry Input of the NS32532 and Registered Transceivers • 4-39 Interfacing the DP8420A/21A/22A to the 68000/008/010 National Semiconductor Application Note 538 Joe Tate and Rusty Meier INTRODUCTION This application note explains interfacing the DP8420Al21A122A DRAM controller to the 68000. Three different designs are shown and explained. It is assumed that the reader is familiar with the 68000 access cycles and the DP8420Al21A122A modes of operation. This application note also applies to the 68010. $401: DESIGN # 1 DESCRIPTION Design # 1 is a simple circuit to interface the 68000 to the DP8420Al21A122A and up to 32 Mbytes of DRAM. The DP8420Al21 Al22A is operated in Mode 1. An access cycle begins when the 68000 places a valid address on the address bus and asserts the address strobe (AS). Chip select (CS) is generated by a 74AS138 decoder. If a refresh or Port B access (DP8422A only) is not in progress, the DP8420Al21A122A will assert the proper RAS depending on the bank select inputs (BO, B1). After guaranteeing the programmed value of row address hold time the DP8420Al21A122A will switch the DRAM address (QO-8, 9, 10) to the column address and assert CAS. By this time, the 74AS245's have been enabled and the DRAMs place their data on the data bus. The DP8420Al21A122A also asserts DTACK which is used to generate DTACK to the 68000 to complete the access. If a refresh or Port B access had been in progress, the DP8420Al21A122A would have delayed the 68000's access by inserting wait states into the access cycle until the refresh or Port B access was complete and the programmed amount of precharge time was met. This circuit can run up to 10 MHz with 0 wait states, with two or more banks. For 10 MHz, zero wait states with one bank, see design #2. Timing parameters are referenced to the numbers shown in the DP8420Al21 Al22A data sheet timing parameters. Numbered times starting with a "$" refer to the DP8420Al21A122A timing parameters. Numbered times starting with "#" refer to the 68000 data sheet. Equations have been given to allow the user to calculate timing based on his frequency and application. The clock is at 10 MHz, a multiple of 2 MHz, allowing it to be tied directly to DElClK. If DElClK is not a multiple of 2 MHz, ADS to CAS must be recalculated. DESIGN # 1 TIMING AT 10 MHz AND 8 MHz Clock Period = Tcp10 = 100 ns @ 10 MHz = Tcp8 = 125 ns @ 8 ns $400b: ADS Asserted Setup to ClK High = Clock Period - ClK High to AS Asserted = Tcp10 - #9 = 100 ns - 55 ns = 45 ns @ CS Setup to ADS Asserted = 68000 Address to AS Max - 74AS138 Decoder = #11 - Tphl Max =20ns-9ns = 11ns@10MHz = #11 - Tphl =30ns-9ns = 21 ns @ 8 MHz $407 & $404: Address Valid Setup to ADS Asserted = 68000 Address to AS Max = #11 Max = 20 ns @ 10 MHz = #11 Max = 30 ns@8MHz $405: ADS Negated Held from ClK High = 68000 ClK High to AS Asserted Min = #10 Min = 0 ns @ 10 MHz = #10 Min = 0 ns@ 8 MHz #47: DTACK Setup Time = y. Clock Period - Clock to DTACK Asserted = y. Tcpl0 - $18 =50ns-28ns = 22 ns @ 10 MHz ··Using 8420-25 = Y. Tcp8 - $18 = 62.5 ns - 33 ns ··Using 8420-25 = 29.5 ns @8 MHz RAS LOW DURING REFRESH = Programmed Clock tRAS - [(ClK High to Refresh RAS Asserted) - (ClK High to Refresh RAS Negated)] = Tcp10 + Tcp10 - $55 = 100 ns + 100 ns - 6 ns = 194 ns @ 10 MHz I = Tcp8 + Tcp8 - $55 = 125 ns + 125 ns - 6 ns = 244 ns @ 8 MHz 10 MHz = TcpS - #9 = 125 ns - 60 ns = 65 ns @ 8 MHz 4-40 RAS PRECHARGE PARAMETERS" tRP = (Programmed Clocks - 1) - [(AREa to RAS Negated) - (ClK to RAS Asserted)] = Tcp10 - $50 = 100 ns - 16 ns = 84 ns @ »z 1 Wait State tRAG I s2 + s3 + s4 + sw + sw + s5 + s6 - ClK to AS Asserted Max - ADS Asserted to RAS Asserted - 74AS245 Delay Max - 68000 Data Setup Min = 3'10 Tcp10 - #9 - $402 - Tphl Max - #27 = 350 ns - 55 ns - 35 ns - 7 ns - 10 ns = 10 MHz = Tcp8 - $50 = 125 ns - 16 ns = 109 ns @ 243 ns = 3'10 Tcp8 - #9 - $402 - Tphl Max - #27 437.5 ns - 60 ns - 35 ns - 7 ns - 15 ns """To gain more precharge program 3t or use design #2. tRAC AND tCAC FOR DRAMs = Timing is supplied for the system shown in Figure 1. (see Figures 2, 3 and 4). Since systems and DRAM times vary, the user is encouraged to change the following equations to match his system requirements. Timing has been supplied for systems with 0 or 1 wait state. If DElGlK is not a multi· pie of 2 MHz, the timing for tRAH and tASC will increase or decrease according to the equations given in the data sheet. The ADS to RAS and ADS to GAS will also have to be changed depending on the capacitance of the DRAM array. = 143 ns @ 10 MHz tGAC I w/Heavy Using 8420·20 load = s2 + s3 + s4 + s5 + s6 - GlK to AS Asserted Max - ADS Asserted to CAS Asserted - 74AS245 Delay Max - 68000 Data Setup Min 2'10 Tcp10 - #9 - $403a - Tphl Max - #27 = 250 ns - 55 ns - 94 ns - 7 ns - 10 ns = 84 ns = @ 10 MHz I w/Heavy USing 8420·20 load 136 ns @ 8 MHz I wI Using 8420·20 Heavy load 1 Wait State tGAC = - 7 ns - 15 ns 8 MHz Using 8420·20 w/Heavy load = = 312.5 ns - 60 ns - 35 ns @ I '---:.=:...:..:.:"-=--=--==----' #9 - $402 - Tphl Max - #27 195 ns 8 MHz = 2'10 Tcp8 - #9 - $403a - Tphl Max - #27 = 312.5 ns - 60 ns - 94 ns - 7 ns - 15 ns = 2'10 Tcp8 - = @ o Wait States = s2 + s3 + s4 + s5 + s6 - ClK to AS Asserted Max - ADS Asserted to RAS Asserted - 74AS245 Delay Max - 68000 Data Setup Min = 2'10 Tcp10 - #9 - $402 - Tphl Max - #27 = 250 ns - 55 ns - 35 ns - 7 ns - 10 ns = 320 ns '----'=:....:.:;::....;::....::...:.::..:.=---' oWait States tRAG @ 10 MHz I w/Heavy USing 8420·20 load = 8 MHz Using 8420·20 w/Heavy load = s2 + s3 r s4 + sw + sw + s6 - ClK to AS Asserted Max - ADS Asserted to CAS Asserted - 74AS245 Delay Max - 68000 Data Setup Min 3'10 Tcp10 - #9 - $403a - Tphl Max - #27 = 350 ns - 55 ns - 94 ns - 7 ns - 10 ns = 184 ns @ 10 MHz I w/Heavy Using 8420·20 load = 3'10 Tcp8 - #9 - $403a - Tphl Max - #27 437.5 ns - 60 ns - 94 ns - 7 ns - 15 ns Using 8420·20 = 261 ns @ 8 MHz w/Heavy load = 4·41 UI Co) (1) :g Design # 1 Programming Bits It) I Z Bits c( Value Description RO,R1 RAS low Time During REFRESH = 2T RAS Precharge Time = 2T RO = 0 R1 = 1 R2,R3 DTACK Generation Modes for Non-Burst Accesses R2 = s R3 = s R4,R5 DTACK Generation Modes for Burst Accesses R4 = s R5 = s R6 Add Wait States with WAITIN R6 = s R7 DTACK Mode Select R7 = 1 R8 Non Interleaved Mode R8 = 1 R9 Staggered or All RAS REFRESH R9 = u CO, Cl, C2 Divisor for DElClK CO = s Cl = s C2 = s C3 +30 REFRESH C3 C4,C5, C6 RAS, CAS Configuration Mode ·Choose All CAS Mode C4 = u C5 = u C6 = u = 0 C7 Select 0 ns Column Address Setup C7= 1 C8 Select 15 ns Row Address Setup C8 C9 CAS is Delayed to the Next Rising ClK Edge During Writes C9 = 1 BO The Row/Column Bank latches Are Fall Through Mode BO = 1 B1 Access Mode 1 Bl = 1 ECASO CAS Not Extended Beyond RAS ECASO = 0 u = user defined R2 = 1 R3 = R2 = 1 R3 = CO = 1 Cl = CO = 0 C1 = R4 = 0 R5 = R4 = 1 R5 = s 0 0 0 0 0 1 = system dependent R6 = 0 C2 = 1 C2 = 1 for 0 WAIT STATES for 1 WAIT STATE for 10MHz for8 MHz for 0 WAIT STATES during write portion of test and set for 1 WAIT STATE during write portion of test and set 4-42 = 1 l> z I I~ ~ 68000 U1 Co) c» ~ CLK, DELCLK CS " RCO-9,10 ADDRESS BUS II Al v A2 AS BO RASO- 3 RASO- 3 CASO-l CASO - 1 • LOW BYTE CAS2- 3 CAS2 - 3 • HIGH BYTE ~ ~420A/21A/22A ADS,AREQ LDS ECASO,I UDS ECAS2,3 R/W WIN DTACK WAIT (DTACK) WE STATIC COLUMN OR PAGE MODE DRAMS REQUIRED FOR TEST; SET INSTRUCTION DATA IN DATA OUT DATAO-15 " WE ~ CS:::i)-, AS -Tii-I Ir1 EN EN DIR '--- DIR I IA ~ Ii 74F245 ~ TL/F/9732-1 FIGURE 1.68000 Design # 1 4-43 co CO) It) I Z c( CLK (68000) (8420A) AODRESS (68000) BO,Bl RCO-8,9,10 (8420A) AS (68000) ADS (8420A) RAS (8420A) ill (DRAM) CAS (8420A) CAS (DRAM) 00-8,9,10 (8420A) AO-8,9,10 (DRAM) UDS, LOS (68000) ms (8420A) R/'ii (68000) RFiP (8420A) DTACK (8420A) DTACK (68000) OATA (DRAM) ACCESS #1 READ ACCESc.;.S~_ _ _ _ _ ACCESS #2 TEST AND SET ACCESS _ _ _ _ _-I WITH 0 WAIT STATES WITH 0 WAIT STATES TL/F/9732-2 FIGURE 2. 68000 Design IF 1 Timing 444 CLK (68000) (8420A) ADDRESS (68000) r-"'\I+....-!-....,....r-+-+--!-,""...."\~........+-++--!-....,,.....~....-'-....-!-....--'r-....+-......-:--!--!-......,. BO,81 ...~----...--~------------...----------------+------'~ RCO(:4~O~)~-"~------~----+---~_"~~r'----AS (68000) ADS (8420A) RAS (M20A) RAS (DRAM) CAS (8420A) CAS (DRAM) QO(:4~O~r-"\r~""""~/--~~--""+',A-"",J~""""~/~-!-~""~~+""__""""-'-""-!-""""+-+-!-~""~\,..~ AO-~~A~)~J\ ______ .J~ ____ ~ __ ~-'I~J' ______-" ______+-__ ____________...__________-+____...__ ~ -'1~ UDS, COS (68000) ECAS (8420A) R!W (68000) RFlP (8420A) DTACK (8420A) r-.........................."'" CTACK (68000) (D~:~~ I-...................................-{' VALID , VALID VALID ACCESS #3 READ ACCESS --r~----- ACCESS #4 TEST AND SET ACCESS _ _ _ _ _ _--I WITH 1 WAITSTATE WITH 1 WAITSTATE TL/F/9732-3 FIGURE 3, 68000 Design # 1 Timing 4·45 ~ L9 Z c( ClK (68000) (8420A) ADDRESS ' (68000) 80,B1 RCO-8,9,10 (8420A) , VALiD AS (68000) ADS (8420A) RAS (8420A) , RAS (DRAM) , REFRESH PRECHARGE CAS (8420A) , CAS (DRAM) QO-8,9,10 (8420A) , AO-8,9,10 ' (DRAM) , cros, LOS , REFRESH ROW : COLUMN ' (68000) ECAS ' (8420A) , R/W , (6BOOO) , RFIP (B420A) REFRqH iii'ACK ' (B420A) DTACK (68000) DATA (DRAM) , , i--------ACCESS #5 DELAYEO BY REFRESH - - - - - - - 1 TLlF/9732-4 FIGURE 4. 68000 Design # 1 Timing 4-46 $407 & $404: DESIGN #2 DESCRIPTION Design # 2 differs from Design # 1 in that the 68000 can be run up to 12.5 MHz. This design can also run with no wait states at 10 MHz if only one bank of DRAM is being used. A latch must be used with the 68000 address strobe to guarantee the address setup to ADS asserted requirement of the DP8420Al21A/22A. Again, the DP8420A/21A122A is operated in Mode 1. An access cycle begins when the 68000 places a valid address on the address bus at the beginning of processor state s1. At processor state s2, the 68000 asserts the address strobe, AS. This signal is qualified with ClK low to set a latch. The output of this latch produces the signal ADS to the DP8420Al21 Al22A. When the signal ADS is asserted on the DP8420Al21 Al22A, the chip will assert RAS. After time, the guaranteeing the row address hold 8420Al21 A/22A will place the column address to the DRAM address bus. After guaranteeing the column address setup time, the DP8420Al21A122A will assert CAS. After time tCAC has passed, the DRAM will place its data on the data bus. The 8420A/21A122A will assert the DTACK output allowing the bus cycle to end. If a refresh of a Port B access had been in progress, the access would have been delayed by inserting wait states in the Port A access cycle. = Tcp12 + Tphl + Tphl + Tphl + Tphl - #6 - Tphl + 1 ns + 1 ns - 55 ns - 1 ns = 80 ns = 28 ns @ 12.5 MHz $405: #47: = 3 ns @ 12.5 MHz Tphl 1 ns I Tphl - Tphl 1 ns - 1 ns I DTACK Setup Time = 1 Clock Period - CLOCK skew (74AS04) - Max Clock to DTACK I = Tcp12 + Tcp12 - $50 80 ns + 80 ns - 16 ns = Clock Period + 74AS04 Delay Min + 74AS04 Delay Min + 74AS02 Delay Min + 74AS02 Delay Min - 74AS04 Delay Min - Clock to ADR Max - 74AS138 Delay Max = Tcp12 + Tphl Min + Tphl Min + Tphl Min + Tphl Min - Tphl Min - #6 - Tphl Max = + + + RAS PRECHARGE PARAMETERS = Programmed Clocks - Clock to AS Negated - [(AREQ to RAS Negated) - (ClK to RAS Asserted)] CS Setup to ADS Asserted 12.5 MHz + + tRP - 1 ns - 4.5 ns - 4.5 ns @ Tphl 1 ns Min = 154 ns @ 12.5 MHz = 80 ns + 40 ns + 1 ns + 1 ns - 55 ns 19 ns + + Tphl + RAS lOW DURING REFRESH tRAS = Programmed Clock - [(ClK High to Refresh RAS Asserted) - (ClK High to Refresh RAS Negated)] = Tcp12 + Tcp12 - $55 = 80 ns + 80 ns - 6 ns Tphl Min - #9 - Tphl Min - Tphl Max - Tphl Max = = 1 ns = 47 ns @ 12.5 MHz + 80 ns + 1 ns + 1 ns + 1 ns - 1 ns - 55 ns - 9 ns I = 80 ns - 5 ns - 28 ns = Tcp12 + % Tcp12 + Tphl Min = 1 ns = Tcp12 - Tphl Max - $18 + 74AS04 Delay Min + 74AS04 Delay Min - Clock to AS Asserted Max - 74AS04 Delay Min - 74AS02 Delay Max - 74AS02 Delay Max $401: + ADS Negated Held from ClK High = + % Clock Period = 57 ns @ 12_5 MHz 1 ns + Min 74AS02 74AS02 + Min 74AS04 - Min 74AS04 ADS Asserted Setup to ClK High = Clock Period + = Min 74AS04 DESIGN #2 TIMING AT 12.5 MHz Clock Period = Tcp12 80 ns @ 12.5 MHz $400b: Address Valid to ADS Asserted = Clock Period + 74AS04 Delay Min + 74AS04 Delay Min + 74AS02 Delay Min + 74AS02 Delay Min - Clock to ADR Max - 74AS04 Min = 144 ns $29b: @ 12.5 MHz AREQ Negated Setup to ClK = Clock Period + Min CLOCK Skew 74AS04 - Max 74AS02 - Max 74AS02 = Tcp12 + Tphl + Tphl - Tphl = 80 ns + 1 ns - 4.5 ns - 4.5 ns 1 ns = 72 ns @ 12.5 MHz I 4-47 I 1 wait state • uses transceivers • tRAC AND tCAC FOR DRAMs Timing is supplied for the system shown in Agure 5. (See Figures 6). Since systems and DRAM times vary, the user is encouraged to change the following equations to match his system. Timing has been suppiled for systems with 0 wait states and 1 bank of DRAM and 1 wait state and 4 banks of DRAM. If DELCLK is not a multiple of 2 MHz, the times of tRAH and tASC will increase or decrease according to the equations given in the data sheet. The ADS to RAS and ADS to ~ will also have to be changed depending on the capacitance of the DRAM array. tCAC = 124 ns tRAC = s2 + s3 + s4 + s5 + s6 - 74AS02 Max - 74AS02 Max - Clock to AS Max - ADS to RAS - Data Setup = 2% Tcp12 - Tphl - Tphl - #9 - $402 - #27 = 200 - 4.5 ns - 4.5 ns - 55 ns - 25 ns - 10 ns = 101 ns I wi ··U~ing 8420-25 Light Load 12.5 MHz @ 1 wait state • uses transceivers • ffi~ =~+~+~+~+~+~+~ - 74AS02 Max - 7AS02 Max - Clock to AS Max - ADS to RAS - 74AS245 Delay - Data Setup = 3% Tcp12 - Tphl - Tphl - #9 - $402 - Tphl - #27 = 280 ns - 4.5 ns - 4.5 ns - 55 ns - 29 ns - 7 ns - 10 ns = 170 ns @ 12.5 MHz RASLowTime tRP = Max AS Low - % Clock Period - 74AS02 Delay - 74AS02 Delay + 74AS02 Delay + 74AS02 Delay - [(ADS Asserted to RAS) - (AREQ Negated to RAS Negated)] = #14 - % Tcp12 - Tphl - Tphl + Tphl + Tphl - $52 = 160 ns - 40 ns - 0 ns I tCAC o wait states • does not use transceivers • !CAC = s2 + s3 + ~ + s5 + s6 - 74AS02 Max - 74AS02 Max - Clock to AS Max - ADS Asserted to CAS - Data Setup = 2% Tcp12 - Tphl - Tphl - #9 - $403a - #27 = 200 ns - 4.5 ns - 4.5 ns - 55 ns - 75 ns - 10 ns = 51 ns @ 12.5 MHz I 12.5 MHz @ DESIGN #2,0 WAIT STATES DURING WRITE ACCESS Design #2 can be modified to allow 0 wait states during writes. To accomplish this, the chip must be programmed with the same value except that bits R2, R3 and R6 are changed to: R2 = 0 DTACK of OT from RAS R3 = 0 R6 = 0 Hold off DTACK 1 extra clock period The hardware must be modifed. The signal R/W from the 68000 is inverted and tied to the 8420 signal WAITIN. This ensures that a wait state will only be asserted during read accesses (see Figure 6). o waits during write access timing o wait states • does not use transceivers • tRAC =s2+s3+s4+sw+sw+s5+s6 - 74AS02 Max Delay - 74AS02 Max Delay - Clock to AS Max - ADS Asserted to CAS - 74AS245 Data Setup = 3% Tcp12 - Tphl - Tphl - #9 - $403a - Tphl - #27 = 280 ns - 4.5 ns - 4.5 ns - 55 ns - 75 ns - 7 ns - 10 ns = 120 ns @ I 12.5 MHz CAS Low Time tCP = s2 + s3 + s4 + s5 + 56 - Max CLK to AS - 74AS02 - 74AS02 - Max AS to ~ + Min CLK to DS + Min ECAS to CAS = 2% Tcp12 - #9 - Tphl - Tphl - $403a + #12 + $14 = 200 ns - 55 ns - 4.5 ns - 4.5 ns -82ns+Ons+Ons I wi ·Using 8420-25 Light Load = 54 ns 4-48 @ 12.5 MHz I . l> z Design # 2 Programming Bits U1 Bits u Description Value RO,R1 RAS low Time = 2T RAS Precharge Time = 2T RO = 0 R1 = 1 R2, R3 DTACK Generation Modes for Non-Burst Accesses R2 = 0 R3 = 1 R4, R5 DTACK Generation Modes for Burst Accesses R4 = 0 R5 = 1 R6 Add Wait States with WAITIN R6 = 0 R7 DT ACK Mode Select R7 = 1 R8 Non Interleaved Mode R8 = 1 R9 Staggered or All RAS REFRESH R9 = u CO, C1, C2 Divisor for DElClK CO = u C1 = u C2 = u C3 +30 REFRESH C3 = 0 C4, C5, C6 RAS, CAS Configuration Mode 'Choose All CAS Mode C4 = u C5 = u C6 = u C7 Select 15 ns Column Address Setup C7 = 1 C8 Select 15 ns Row Address Setup C8 = 1 C9 CAS is Delayed to the Next Rising ClK Edge During Writes C9 = 1 BO The Row/Column Bank latches Are Fall Through Mode BO = 1 B1 Access Mode 1 B1 = 1 ECASO CAS Not Extended Beyond RAS ECASO = 0 = user defined 'see previous page for 0 WAIT STATES during writes 4-49 W 0) RASO RASI MEMORY (UP TO 32M bytes) CASO lJ===~=~=-+t DP8420A/21A/22A t-~--'-,,-,-,""""'';'''';';'~,A QO-9,10,AND WE 68000 ECAS2,3 ECASO,l CASI R cs--r-... AS--L.-" EN 74F245 DATAO-15 DATAO-15 TL/F/9732-5 FIGURE 5. 68000 Design # 2 up to 12.5 MHz 4·50 )to ZI UI ClK (68000) ClK (8420A) ADDRESS (68000) BO,B1 RCO-8,9,10 (8420A) AS (68000) ADS (8420A) RAS(8420A) RAS(DRAM) CAS (8420A) CAS (DRAM) 00-8,9,10 (8420A) AO-8.9 1 l0 (DRAM) UDS, lOS (68000) ECAS (8420A) R/'ii (68000) RflP (8420A) DTACK (8420A) DTACK (68000) (0) OCI ~~rJ\.FurLr\AnJVL - X - "\ I I I I I I I I I I I I I I I I I I I I I I I I I I ,, ,, ,,, ,, ,, , , ,, ,,, ,, ,, , , ,,, , ,,, ,, , ,, ,, ,,, ,, , ,, ,, , , ,,, ,, ,, ,, ,,, , , ,,, ,, , ,, , , , ,, , , ,, ,, , , ,, :, ,, ,, , ,, ,, ,, , ,, ,, :\,, , ,, ,, \ , , ,,, , x: ROW ,, :\ , , ,, ,, , , ,,, ,, ,, ,, ,, , DATA VALID , ,,, ,, , , ,, ,, ,, ,, ,, , ,, , , ,, ,, , ,,, , ,,, \ COLUMN ,, ,,, , ,, ,,, ,, , ,, , , ,, ,,, ,, , ,,, ,,, , ,, ,, ,,, ,, , I I I I , :1 , i, ,, ,, X \ . ,, ,, , ,, ,, , , , X, , , ,,, ,, ,, I ,,, ,, ,, ,, 1:,, DATA , , , ,, ,, , , , ,,, ,, , , 1 ,, I I 1 VALID ,, , \:, I , ~ ,, , J :\ , , ,, 1:, ROW ,, , ,, ,,, ,, ,,, ~ ,,, , ,,, , 1 ,, , , ,, , , ,, ,, ,, ,, , , , DATA ,, , ,,, ACCESS , , , , ,, , ,,, ,, , ,, , ,, :/, \ \1, I ,, , , ,, ,, , ,,, ,,, ,, , ,, ,, ,, , COLU¥N ,, , ,, ,,, , ,, ,, I I ,, Wi, ,, , , ,, ,, ,, ,, , , ,, ,, , I ,, ,, I-- WRITE ~READ ACCESS------ I ' I I , , , , ,, ,, , ,, ,, J 1:, , , , ,, , ,, , , , ,, ,,, ,, ,, , ,, ,,, , , ,, , ~ TLlF/9732-6 FIGURE 6. Design # 2 Timing with Zero Wait States during Writes • 4-51 I co ,---------------------------------------------------------------------------------, C") z~ c( tRP DESIGN #3 DESCRIPTION Design # 3 is a simple circuit to interface the 68000 running @ 16 MHz to the DP8420Al21A122A and up to 32 Mbytes of DRAM. The DP8420Al21A122A is operated in Mode 1. An access cycle begins when the 68000 places a valid address . on the address bus and asserts AS. AS is then clocked with a 74AS74 flip-flop. The output of the flip-flop is used to produce ADS to the DP8420Al21A122A. Chip Select (CS) is generated by a 74AS138 decoder. If a refresh or Port B access had been in progress, the 8420Al21A122A would hold off the access by inserting wait states in the access cycle. The DP8420Al21A/22A will place the row address on the DRAM's address bus and assert RAS. After guaranteeing the row address hold time, tRAH, the DP8420Al21A122A will place the column address on the DRAM's address bus and assert CAS. = = 104 ns @ 16.667 MHz $401: tRAC AND tCAC FOR DRAMs Timing is supplied for the system shown in Figure 7. Since system and DRAM times vary, the user is encouraged to change the following equations to match his system requirements. Timing has been supplied for systems with 2 wait states. If DElClK is not a multiple of 2 MHz, the timing for tRAH and tASC will increase or decrease according to the times given in the data sheet. The ADS to RAS and ADS to CAS will also have to be changed depending on the capacitance of the DRAM array. 1 wait state tRAC 51 ns @ 16.667 MHz CS Asserted Setup to ADS Asserted = 1% Clock Periods + Min 74AS74 Delay - Max Clock to Address - 74AS138 Delay = 1% Tcp16 + Tphl $407 & $404: Delay - ADS to RAS - Data Setup = 150 ns -9 ns - 25 ns - 10 ns 2 wait states * uses 4 banks with tranceivers * tRAC = s4 + sw + sw + sw + sw + s5 - 74AS74 Delay - ADS to RAS - Data Setup - Transceivers = 3% Tcp16 - Tphl - $402 - #27 - Tphl 35.5 ns@ 16.667 MHzl + Min 74AS74 Delay - Max Clock to Address = 1% Clock Periods = 1%Tcp16 + Tphl - #6 90 ns + 4.5 ns - 50 ns = 44.5 ns @ 16.667 MHz ADS Negated Held from ClK High = Min 74AS74 Delay #47: DTACK Setup Time = Clock Period - 74AS74 Delay Max = Tcp16 - Tphl = 4.5 ns @ 16.667 MHz = I $405: I = 51 ns @ 16.667 MHz RAS LOW DURING REFRESH = Programmed Clocks - [(ClK High to Refresh RAS Asserted) - (ClK High to Refresh RAS Negated)] Tcp16 + Tcp16 + Tcp16 - $55 = 240 ns - 6 ns = + 210 ns - 9 ns - 29 ns -10ns-7ns = 155 ns @ 16.667 MHz = 60 ns - 9 ns tRAS I ~~~~h~4C~~~5 = 106 ns @ 16.667 MHz - #6 - Tphl Address Valid Setup to ADS Asserted = * using 1 BANK with no transceivers = s4 + sw + sw + s5 + s6 - 74AS74 = 2% Tcp16 - Tphl - $402 - #27 = 90 ns + 4.5 ns + 50 ns - 9 ns = I RAS PRECHARGE PARAMETERS = Programmed Clocks - Clock to AS tRP Negated - [(AREO to RAS Negated) - (ClK to RAS Asserted)] ADS Asserted Setup to ClK High = Clock Period - 74AS74 Delay Max = Tcp16 - Tphl = 60 ns - 9 ns = 1) [(AREO to RAS Negated) (ClK to RAS Asserted)] Tcp16 + Tcp16 - $50 = 120 ns - 16 ns DESIGN #3 TIMING AT 16.667 MHz Clock Period = Tcp16 = 60 ns @ 16.667 MHz $400b: = (Programmed Clocks - Tcp16 = 234 ns @ 16.667 MHz 4-52 I + s6 1 wait state' using 1 BANK with no transceivers tCAC =s4+sw+sw+s5+s6 - 74AS74 Delay - ADS to CAS - Data Setup = 2% Tcp16 - Tphl - $403a - #27 2 wait states • using 4 banks with transceivers • » z tCAC U'1 eN = s4 + sw + sw + sw + sw + s5 + s6 - 74AS74 Delay - ADS to CAS - Data Setup - Transceiver = 3% Tcp16 - Tphl - $403a - #27 - Tphl = 150 ns - 9 ns - 75 ns - 10 ns I = 56 ns @ 16 MHz I co = 210 ns - 9 ns - 82 ns - 10 ns - 7 ns I I = 102 ns @ 16 MHz I Design # 3 Programming Bits Bits Description Value RO,R1 RAS low Time = 2T RAS Precharge Time = 2T RO = 0 R1 = 1 R2,R3 DTACK Generation Modes for Non-Burst Accesses R2 = 1 R3 = 0 R4,R5 DTACK Generation Modes for Burst Accesses R4 = u R5 = u R6 Add Wait States with WAITIN R6 = u R7 DTACK Mode Select R7 = 1 R8 Non Interleaved Mode R8 = 1 R9 Staggered or All RAS REFRESH R9 = u CO, C1, C2 Divisor for DElClK (+8 for 16 MHz) CO = 0 C1 = 1 C2 = 0 C3 +30 REFRESH C3 = 0 C4, C5, C6 RAS, CAS Configuration Mode 'Choose All CAS Mode C4 = u C5 = u C6 = u C7 Select 15 ns Column Address Setup C7 = 1 C8 Select 15 ns Row Address Setup C8 = 1 C9 CAS is Delayed to the Next Rising ClK Edge During Writes C9 = 1 BO The Row/Column Bank latches Are Fall Through Mode BO = 1 B1 Access Mode 1 B1 = 1 ECASO CAS Not Extended Beyond RAS ECASO = 0 u = user defined 'see previous page for 0 WAIT STATES during writes • 4-53 I CLOCK I rf)_l r---~--~A~S~J -~~~~A~D~S1-~1AD~S:-----~CL~K-------' ~ 4 QO-8.9.10~::::::~:JDRAM 1+-----1rRl t-------~ 11!!J' _ __ •• AREQ iiTACK 68000 DlACK RASO - 3 RAS ~ DP8420A/21A/22A t-_ _ _ _ _..;L;;;oDS;o...,_.. ECASO. 1 CASO - 3 t-------~ CAS t-_ _ _ _~~U:.::DS~-.. ECAS2.3 WE t-------.. WE r---t---t-vi ADDRESS I 17tsry:}t-~--II-+UC~S I ~~~ R/W- DIR EN ____ ~~~ DAlAO-15 v 74AS245 ______________ ~ I ~~ J rIAIu-__~~~____________________~ I!J DATAO-15 TL/F/9732-7 FIGURE 7. 68000 Design #3, Works up to 16 MHz Additional Circuitry tor Design # 1 Using the 68450 DMA Controller DP8420A/21A/22A 68450 D~CK.~---------------~ TL/F/9732-8 4·54 Because the 68450 samples DTACK on a positive edge of ClK and the 68000 samples DTACK on the negative edge, additional circuitry must be added to produce the two DTACK signals. The DTACKs must be produced different to ensure RAS low time after an access delayed by a refresh. The programming bits must also be changed as follows: $47: DTACK Setup Time = % CLOCK Period - 74AS74 CLOCK to Q - 74AS32 = % Tcp10 - Tphl - Tphl = 50 ns - 9 ns - 6 ns = 35 ns For 0 WAITSTATES R2 0 R3 1 FOR /DTACK OF 1/2 = = For 1 WAITSTATE R2 0 R3 1 R6 = = 10 MHz @ = % Tcp8 - Tphl - Tphl = 62.5 ns - 9 ns - 6 ns =0 FOR = 47 ns /DTACK OF 1 1/2 Tie the DP8420 signal WAITIN low for 1 waitstate and high for 0 waitstates. All timing except for the following should still apply. Times with a "#" refer to the 68000 data sheet. Times with a "I" refer to the 68450 data sheet and times with a "$" refer to the DPB420A/21 A/22A data sheet. 16: 8 MHz @ DTACK Setup Time (68450) = % CLOCK Period - CLOCK to DTACK = % Tcp10 - $18 = 50 ns - 28 ns = 22 ns @ 10 MHz = % Tcp8 - $18 = 62.5 ns - 33 ns = 29 ns @ 8 MHz All other 68450 times are the same as the 6BOOO. DRAM Speed Versus Processor Speed, (DRAM Speed References the RAS Access Time, tRAC, of the DRAM. Using DP8422A-25 Timing Specifications) 171.lHz ORAM KEY, 16MHz 15MHz • 80ns DRAW 14NH% mm 100 ns DRAM 13MHz 12t.tHz . 1 2 0 ns DRAM 11 MHz D 10lAHz 150nsDRAM 9 MHz 8 MHz - - ' ' - - _......_ ........_ ........__- ' - - - 68000 68000 4 CLOCKS PER ACCESS 1 WAIT STATI:. 5 CLOCKS PER ACCESS o WAIT STATES. TLlF19732-9 • 4·55 I .... LI) ~ z Interfacing the DP8420A/21A/22A to the 68020 National Semiconductor Application Note 539 Joe Tate and Rusty Meier INTRODUCTION This application note explains interfacing the DP8420Al21A/22A DRAM controller to the 68020 microprocessor. Three different designs are shown and explained. It is assumed that the reader is already familiar with the 68020 access cycles and the DP8420A/21A122A modes of operation. DESIGN # 1 TIMING AT 16 MHz AND 12 MHz Clock Period = Tcp16 = 62.5 ns @ 16 MHz = Tcp12 = 83 ns @ 12 MHz DESIGN # 1 DESCRIPTION Design # 1 is a simple circuit to interface the 68020 to the DP8420Al21A/22A and up to 64 Mbytes of DRAM. The DP8420Al21 A/22A is operated in Mode 1. An access cycle begins when the 68020 places a valid address on the address bus and asserts the address strobe (AS). Chip select (CS) is generated by a 74AS138 decoder. If a refresh or Port 8 access (DP8422A only) is not in progress, the DP8420Al21A122A will assert the proper RAS depending on the bank select inputs (80, 81). After guaranteeing the programmed value of row address hold time, the DP8420Al21A122A will switch the DRAM address (00-8, 9, 10) to the column address and assert CAS. By this time, the 74AS245s have been enabled and the DRAMs place their data on the data bus. The DP8420A/21A122A also asserts DTACK which is used to generate DSACKO,1 to the 68020. If a refresh had been in progress, the DP8420A/21 Al22A would have delayed the 68020's access by inserting wait states into the access cycle until the refresh was complete and the programmed amount of precharge time was met. This circuit can run up to 16 MHz with one wait state. However, the timing parameters become close to the minimums for the DP8420Al21A122A parameters. ADS asserted to ClK high ($400b), ~ setup to ADS asserted ($401) and ADS negated held from ClK ($405). Problems can also occur if the loading on the clocks generated from the 74AS74 cause too much skew between ClK and CLK. The clock must be inverted to guarantee timing parameters. A solution to this problem is to invert the CLOCK to the 68020 with a 74AS04. Since the 68020 address strobe can end late in the access, a problem with RAS precharge can occur in back-to-back accesses. In these accesses, the DP8420Al21A122A will guarantee the precharge time by inserting wait states. To reduce this problem, memory interleaving should be used by tying the low order address bits to the bank selects. Timing parameters are referenced to the numbers shown in the DP8420Al21A/22A data sheet. Numbered times starting with a "$" refer to the DP8420Al21 A/22A timing parameters. Numbered times starting with" #" refer to the Motorola 68020 data sheet. Equations have been given to allow the user to calculate timing based on his frequency and application. The clock has been chosen at a multiple of 2 MHz only to allow the user to hook the system clock to the Pll delay line clock (DElClK). If you are running at a frequency that is not a multiple of 2 MHz, it is recommended that you use a clock which is a multiple of 2 MHz for DElClK. If DElClK is not a multiple of 2 MHz, ADS to CAS must be recalculated. $400b: z I U1 Co) co ADS Asserted Setup to ClK High = Clock Period - 68020 Clock to AS Low Max = Tcp16 - #9 Max = 62.5 ns - 30 ns = 32 ns @ 16 MHz = Tcp12 - #9 Max = 83 ns -40 ns = 43 ns @ 12 MHz $401: CS Setup to ADS Asserted = 68020 Address to AS Maximum - 74AS138 Decoder Maximum = #11 Max - Tphl Max = 15 ns - 9 ns = 6 ns @ 16 MHz = #11 Max - Tphl Max = 20 ns - 9 ns =11ns@12MHz $407 & 404: 4-61 Address Valid Setup to ADS Asserted = 68020 Address to AS Maximum = #11 Max = 15 ns @ 16 MHz = #11 Max = 20 ns @ 12 MHz $405: ADS Negated Held from ClK High = 68020 Minimum Clock to AS = #9 Min = 3 ns @ 16 MHz = #9 Min = 3 ns @ 12 MHz # 47 A: DSACKO, 1 Setup Time = '12 Clock Period - Max 74AS74 Delay - Max 74AS32 Delay = 31 ns - 9 ns - 5 ns = 17 ns @ 16 MHz = '12 Tcp12 - Tphl Max - Tphl Max = 41 ns - 9 ns - 5 ns = 27 ns @ 12 MHz II #478: o Walt Statea = s1 + s2 + s3 + s4 - 68020 CLK to AS tRAC Max - 74AS245 Delay Max - 68020 Data Setup Min - ADS Asserted to RAS Asserted = Tcp16 + Tcp16 - #9 Max - Tphl Max - #27 Min - $402 Max = 62.5 ns + 62.5 ns - 30ns - 7 ns - 5 ns -35 ns w/8420A-20 = 48 na @ 16 MHz Heavy load w/8420A-25 = 58 na @ 16 MHz Light load = Tcp12 + Tcp12 - #9 Max - Tphl Max - #27 Min - $402 Max =83ns+83ns-40ns - 7 ns - 10 ns - 35 ns = 74 n @ 12 MHz w/8420A-20 a Heavy load w/8420A-25 = 84 na @ 12 MHz Light Load DSACKO, 1 Hold Time = Yo Clock Period + Min 74AS74 Delay + Min 74AS32 Delay = Yo Tcp16 + Tphl Min + Tphl Min = 31 ns + 5 ns + 1 ns = 37 na @ 16 MHz I = Yo Tcp12 + Tphl Min + Tphl Min = 41 ns - 9ns - 5 ns = 47 na @ 12 MHz I RAS Low during REFRESH tRAS = Programmed Clocks - [(ClK High to Refresh RAS Asserted) - (ClK High to Refresh RAS Negated)] = Tcp16 + Tcp16 - $55 = 62.5 ns + 62.5 ns -6 ns = 119 na @ 16 MHz I = Tcp12 + Tcp12 - $55 = 83.3 ns + 83.3 ns - 6 ns = 160 na @ 12 MHz I 1 Walt Stat. tRAC = Tcp12 - #12 =83ns-40ns = s1 + s2 + sw + sw +s3 + s4 - 68020 ClK to AS Max - 74AS245 Delay Max - 68020 Data Setup Min - ADS Asserted to RAS As.serted = Tcp18 + Tcp16 + Tcp16 - #9 Max - Tphl Max - #27 Min - $402 Max = 62.5 ns + 62.5 ns + 62.5 ns - 30 ns - 7 ns - 5 ns -35 ns = 110 @ 16 MHz w/8420A-20 na Heavy load = 43 na = 120 na @ 16 MHz = 157 a n @ 12 MHz w/8420A-20 Heavy load = 167 na @ 12 MHz w/8420A-25 Light load AD Precharge Parametera·· $29b: ~ Negated Setup to ClK High = CLOCK Period - CLOCK Low to 68020 AS Negated = Tcp18 - #12 = 62.5 ns - 30 ns = 32 na tRP @ @ 16 MHz w/8420A-25 Light load = Tcp12 + Tcp12 + Tcp12 - #9 Max - Tphl Max - # 27 Min - $402 Max = 83 ns + 83 ns + 83 ns -40 ns - 7 ns - 10 ns - 35 ns 12 MHz = s5 + sO + s1 + s2 - 68020 ClK low to AS Negated - [(AREa to RAS Negated) - (ClK to RAS Asserted») = 2 Tcp16 - #12 - $50 = 125 ns - 30 ns - 18 ns w/8420Al21AI = 79 na @ 18 MHz 22A w/8420Al21AI = 81 na @ 16 MHz 22A = 2 Tcp12 - #12 - $50 = 186 ns - 40 ns - 16 ns = 120 na @ 12 MHz 2 Walt Stat.a tRAC = s1 + s2 + sw + sw + SW + sw + s3 + s4 - 68020 ClK to AS Max - 74AS245 Delay Max - 68020 Data Setup Min - ~ Asserted to Asserted Tcp16 + Tcp18 + Tcp18 + Tcp16 - 9 Max - Tphl Max - #27 Min - $402 Max = 82.5 ns + 62.5 ns + 82.6 ns + 62.6 ns - 30 ns - 7 ns -6 ns -36 ns I "Note: To galn more precharge program 3T. = tRAC AND tCAC TIMING FOR DRAMa Timing Is supplied for the system shown In Figuftl 1 (See Figures 2, 3). Since systems and DRAM times vary, the user Is encouraged to change the following equations to match his system requirements. Timing has been supplied for systems with 0, 1 or 2 walt states. If the DELCLK Is not a multiple of 2 MHz, the timing for tRAH and IASC will Increase. Because tRAH and IASC will Increase, ~ to ~ and ~ to 'CAS will also Increase and must be changed according to the equations given in the data sheet. The ADS to and ~ to 'CAS will also have to be changed depending on the capacitance of the DRAM array. m 4-62 m - 173 na @ 18 MHz I w/8420A-20 Heavy Load = 183 na @ 18 MHz w/8420A-26 light Load r--------------------------------------------------------------------, z ~ = Tcp12 + Tcp12 + Tcp12 + Tcp12 -9 = 51 ns @ 16 MHz Max - Tphl Max - #27 Min - $402 Max = 83 ns + 83 ns + 83 ns + 83 ns -40 ns -7 ns - 10 ns -35 ns = 240 ns @ 12 MHz w/8420A-20 Heavy load = 250 ns @ 12 MHz w/8420A-25 Light load = 70.5 ns @ 16 MHz = sl + s2 + s3 + s4 - 68020 ClK to AS Max - 74AS245 Delay Max - 88020 Data Setup Min - ADS Asserted to ~ Asserted = Tcp16 + Tcp16 - #9 Max - Tphl Max - #27 Min - $403a Max = 62.5 ns + 62.5 ns - 30 ns - 7 ns -5 ns - 94 ns w/8420A-20 = -11 ns @ 16 MHz Heavy load w/8420A-25 = 6 ns @ 16 MHz Light load = 134 ns = Tcp12 + Tcp12 - #9 Max - Tphl Max - #27 Min - $403a Max = 83 ns + 83 ns -40 ns - 7 ns - 10 ns - 94 ns w/8420A-20 = 15 ns @ 12 MHz Heavy load 12 MHz w/8420A-25 light load = sl + - + s2 + sw + sw + sw + sw + s3 s4 - 68020 ClK to AS Max 74AS245 Delay Max 68020 Data Setup Min - Ai5'S Asserted to eAS Asserted = Tcp16 + Tcp16 + Tcp16 + Tcp16 - #9 Max - Tphl Max - #27 Min - $403a Max = 62.5 ns + 62.5 ns + 62.5 ns +62.5 ns - 30 ns - 7 ns -5ns-94ns = 114 ns @ 16 MHz = 133 ns @ 16 MHz ~~:~~~:~ w/8420A-25 Light load = Tcp12 + Tcp12 + Tcp12 + Tcp12 w/8420A-25 Light load - #9 Max - Tphl Max - #27 Min - $403a Max = 83 ns + 83 ns + 83 ns + 83 ns - 40 ns - 7 ns - 10 ns - 74 ns 1 Walt Stat. tCAC @ 2WaltStat.s tCAC I = 34 ns @ 12 MHz I w/8420A-25 Light load = Tcp12 + Tcp12 + Tcp12 - #9 Max - Tphl Max - #27 Min - $403a Max = 83 ns + 83 ns + 83 ns - 40 ns - 7 ns - 10 ns - 94 ns w/8420A-20 = 98 ns @ 12 MHz Heavy load oWalt Stat. tCAC w/8420A-20 Heavy load = sl + s2 + sw + sw + s3 + s4 - 68020 ClK to AS Max - 74AS245 Delay Max - 68020 Data Setup Min - Al5S Asserted to eAS Asserted = Tcp16 + Tcp16 + Tcp16 - #9 Max - Tphl Max - # 27 Min - $403a Max = 62.5 ns + 62.5 ns + 62.5 ns - 30 ns -7ns-5ns-94ns 4-63 = 181 ns @ 12 MHz w/8420A-20 Heavy load = 200 ns @ 12 MHz w/8420A-25 Light load • U1 ~ Design # 1 Programming Bits Bits x u s Description Value RO, R1 RAS Low during REFRESH = 2T FiJi$ Precharge Time = 2T RO = 0 R1 = 1 R2,R3 DTACK Generation Modes for Non-Burst Accesses (YzT after RAS) R2 = 0 R3 = 1 R4,R5 DTACK during Burst Mode R4 = x R5 = x RS Add Wait States with WAITIN RS = x R7 DTACK Mode Selected R7 = 1 R8 = 1 R8 Non-Interleaved Mode R9 Staggered or All REFRESH R9 = u CO, C1, C2 Divisor for DELCLK CO = s C1 = s C2 = s C3 +30 REFRESH C3 = 0 C4,C5,CS RAS, CAS Configuration Mode 'Choose An All CAS Mode C4 = u C5 = u CS = u C7 Select 0 ns Column Address Setup C7= 1 C8 Select 15 ns Row Address Hold C8 = 1 C9 CAS is Delayed to Next Rising CLOCK during Writes C9 = 1 BO The Row/Column Bank Latches Are in Fall Through Mode BO = 1 B1 Access Mode 1 B1 = 1 ECASO CAS not extended beyond FiJi$ ECASo = = don't care = user defined = system dependent s@ 16MHz s@ 12 MHz CO = 0 C1 = 1 C2 = 0 CO = 0 C1 = 0 C2 = 1 4-S4 0 32 MHz » z . c>--, CLK U'I ::g RASO - 3 ~---1~ RAS CASO- 3 CAS ~~-------------.-------+~ AOR ~_ _"fIIII_ _ _" '_ _ _+--I~RCO - WE 8, 9,10 BO, B1' ri--------I---.... CS 68020 ...----+-~WIN WE Q(0-10) _ _~A 8420A/21A/22A R/W ....--------1-'1-1 ...----11-_-1 OTACK OSACK DATA -.J UUO [>-Ht:j;---:..:=:=:......1..!E~CA~S~0~-23~_ _ _ _ UMO LMO LLO DATAI/O 74AS245 TL/F/9733-1 'Tie least significant ADR bits (A2, A3) to BO, Bl. FIGURE 1. Design #1,68020 up to 16 MHz with 1 Wait State 4-65 AN-S39 CLK (68020) CLK (842OA) A2-A31 (68020) RO-l0(842OA) CIl-l0(842OA) 80.81 (842OA) VALID VALID: AS (68020) ADS (842OA) AREO (8420A) RAS (8420A) RAS (DRAM) PRECHARGE ' CAS (8420A) CAS (DRAM) ~I 00-10 (8420A) Ao-l0 I I ROW ,'COLUMN ' ROW' COLUMN (DRAM) 00-31 (68020) VALID DTACK (8420A) DSACK (68020) RFlP (8420A) \. ACCESS #1 (READ) .,. ACCESS #2 (READ DELAYED BY PRECHARGE) TUF/9733-2 FIGURE 2. Design # 1 Timing a.K(68020) a.K (842OA) A2-A31 (68020) 1I&-10(842OA) , ROW ,'COLUMN' , , :COLUMN: 00-31 (68020) OTACK (8420A) OSACK (68020) RFIP (8420A) j. ACCESS #1 (READ) -I' ACCESS #2 (READ DELAYED BY PRECHARGE) TLlF/9733-5 FIGURE 5. 68020 Design # 2 Timing 6eS-NV II AN-S39 ClK I (68000) ) (8420A) I AS-A31 (68020) RO-l0 (8420A) CO-l0(8420A) BO,91 (8420A) I VALID AS (68020) I ADS (8420A) AREO (8420A) I RAS (8420A) RAS (DRAM) I CAS (8420A) CAS (DRAM) ~I I 00-10 (8420A) Ao-l0 (DRAM) I R~FRES!"i PRECHARGE I I I I I REFRESH, ROW: ~CCES? RO\V i I ACCESS COLUMN , I I I 00-31 (68020) DTACK (8420A) I DSACK (68020) I RflP (8420A) I REFRESH I I' ACCESS #3 DELAYEO BY REFRESH ·1 TUF/9733-6 FIGURE 6. 68020 Design #2 Tuning DESIGN #3 DESCRIPTION Design #3 uses two 68020s sharing a common DRAM array. Port A's interface is the same as design # 1. The two processors share the same ClK. By using the same ClK, the request from Port B do not have to be synchronized to the system ClK. $404 & 407: »z I (II Co) CD = # 11 Max + Tphl Min + Tphl Max = 15 ns + 2 ns - 6 ns = 11ns@16MHz In this design, an access begins from Port A when the 68020 asserts AS. Assuming the DP8422 has granted access to Port A through GRANTB negated, AS will assert RAS. After guaranteeing the programmed value of tRAH, the DP8422 will switch the a outputs to the column address tASC before asserting CAS. By this time the 74AS245s have been enabled and the DRAM places its data on the data bus. The cycle is terminated by the DP8422 asserting DTACK. The 68020 will then sample the data from the data bus and negate AREa. AREa negated will cause RAS to be negated. If at any time during Port A's access Port B had requested an access by asserting AREOB, Port B's 68020 would have been delayed by keeping AT ACKB negated. This would have Inserted wait states into Port B's access. After Port A's access terminates, GRANTB is asserted to allow Port B's address through the mux. On the next rising CLOCK edge, RAS will be asserted. Again, after guaranteeing the necessary address parameters, CAS will be asserted. Refresh will happen after the current access is completed and precharge time has been met. During this refresh, all accesses will be held off. = # 11 Max + Tphl Min - Tphl Max = 20 ns + 2 ns - 6 ns = 16 ns @ 12 MHz $405: ADS Negated Held from ClK = 68020 Min CLOCK to AS = #9 Min = 3 ns = 3 ns @ 16 MHz = #9 Min + Tphl Min =3ns+2ns = 3 ns #47A: @ 12 MHz DSACKO,l Setup Time = % CLOCK Period - 74AS74 Delay Max - 74AS32 Delay Max = % Tcp16 - Tphl Max - Tphl Max = 31 ns - 9 ns - 5 ns = 18 ns @ 16 MHz Since back-to-back accesses can cause precharge delays, it is recommended that the low order address bits be tied to the bank select inputs. • Requires External Flip-Flop and OR Gate. = % CLOCK Period - ClK to DTACK Asserted = % Tcp - $18 Max = 41 ns - 33 ns DESIGN #3 TIMING DESCRIPTION Clock Period = Tcp16 = 65 ns@ 16 MHz = Tcp12 = 83 ns @ 12 MHz = 8 ns @ 12 MHz Port A Timing $400b: Address Valid Setup to ADS Asserted = 68020 Address to AS + Min 74AS244 - Max 74AS244 'Program as DTACK of 1% No External Flip-Flop Required. ADS Asserted Setup to ClK High = Clock Period - 68020 Clock to AS low Max = Tcp16 - #9 Max #47B: = 62.5 ns - 30 ns = 32_5 ns @ 16 MHz I DSACKO,l Hold Time = % Clock Period + Min 74AS74 + Min 74AS32 = % Tcp16 + Tphl Min + Tphl Min = 31 ns + 5 ns + 1 ns = Tcp12 - #9 Max = 37 ns @ 16 MHz = 83 ns - 40 ns "'Requires External Flip Flop and OR Gate. = 43 ns @ 12 MHz $401: = CS Setup to ADS Asserted % CLOCK Period + Min ClK to DTACK Asserted = 41 ns + 0 ns = 68020 AS Address to AS Max + 74AS244 Min - 74AS138 Decoder Max = # 11 Max + Tphl Min + Tphl Max = 41 ns @ 12 MHz >10 Program as DTACK of 1%. = 15 ns + 2 ns - 9 ns • = 8 ns @ 16 MHz = # 11 Max + Tphl Min + Tphl Max =20ns+2ns-9ns = 13 ns @ 12 MHz 4-75 ~ II) I Z c:r: = # 11 - Tphl Max + Tphl Min + Tphl Min #450 & $454: Address Setup to ClK High = CLOCK Period - ClK High to GRANTB Negated - 74AS04 Delay Max - 74ASOO Delay Max - 74ASOO Delay Max - 74AS244 Delay = Tcp16 - $109 Max - Tplh - Tphl - Tphl - Tzh = 62.5 ns - 26 ns - 5 ns - 4.5 ns - 4.5 ns - 9 ns C==13.5 ns = = 16 MHz @ = $117: @ 12 MHz I = #47a I 5 ns = #9 Min + Tphl Min @ = 5 ns @ = #47B 12 MHz $110: 83 ns - 40 ns - 6 ns = 37 ns @ 12 MHz @ @ 16 MHz 41 ns - 9 ns - 5 ns @ 12 MHz DSACKO,1 Hold Time = V. CLOCK Period + Min 74AS74 + Min 74AS32 = V. Tcp16 + Min Tphl + Min Tphl = 31 ns + 5 ns + 1 ns @ = V. Tcp12 = 47 ns 16 MHz 12 MHz Row Address Setup to ClK High = CLOCK Period - ClK High to GRANTB Asserted - 74AS04 Delay Max - 74ASOO Delay Max - 74AS244 Delay = Tcp16 - $108 - Tplh - Tphl - Tzh = 60 ns - 30 ns - 5 ns - 4.5 ns - 9 ns @ 12 MHz Programmed CLOCKs - [(ClK High to Refresh RAS Asserted) (ClK High to Refresh RAS Negated)) = Tcp16 + Tcp16 - $55 = 62.5 ns + 62.5 ns -6 ns = = 119 ns 16 MHz @ I = Tcp12 + Tcp12 - $55 = 83.3 ns +83.3 ns - 6 ns = 160 ns @ 12 MHz = 11.5 ns @ 16 MHz RAS Precharge Parameters = Tcp12 - $108 - Tplh - Tphl - Tzh = 80 ns - 30 ns - 5 ns - 4.5 ns - 9 ns $29b: 20 MHz I RAS low during REFRESH tRAS #9 Max - Tphl Max @ I + Min Tphl + Min Tphl = 41 ns + 5 ns + 1 ns I = = 31.5 ns $114: 16 MHz @ Tcp12 - 17 ns = 37 ns AREaB Asserted Setup to ClK High = Clock Period - ClK to AS Max - 74AS32 Max = Tcp16 - #9 Max - Tphl Max = 62.5 ns - 30 ns - 6 ns = 26.5 ns 50 ns = 27 ns 16 MHz = 16 MHz @ DSACKO,1 Setup Time = V. CLOCK Period - Max 74AS74 - Max 74AS32 = V. Tcp16 + Min Tphl + Min Tphl = 31 ns - 9 ns - 5 ns = = 40 ns = V. Tcp12 - Tphl Max - Tphl Max AREaB Held Negated from ClK High = ClK to AS Min + 74AS32 Min = #9 Min + Tphl Min = 3 ns + 2 ns = 3 ns + 2 ns $101: AREa Negated Pulse Width = AS Negated Width = #15 Min = Port B Timing $100: I = #15 Min tcp12 - $109 Max - Tplh - Tphl - Tphl - Tzh 83 ns - 32 ns - 5 ns - 4.5 ns - 4.5 ns - 9 ns = 34 ns 20 ns - 6 ns + 2 ns + 2 ns = 18 ns @ 12 MHz I Address Valid Setup to AREaS Asserted = Min Address to AS - 74AS244 Max + 74AS244 Min + 74AS32 Min = # 11 - Tphl Max + Tphl Min + Tphl Min = 15 ns - 6 ns + 2 ns + 2 ns AREa Negated Setup to ClK High = CLOCK Period - CLOCK low to AS Negated = 62.5 ns - 30 ns = 32 ns @ 16 MHz = Tcp12 - #12 =83ns-40ns = 43 ns @ 12 MHz = 13 ns @ 16 MHz 4·76 I tRP + sO + s1 + s2 - 68020 ClK low to AS Asserted - [(AREa to RAS Negated) - (ClK to RAS Asserted)) = ss = 2 Tcp16 = = Tcp12 + Tcp12 + Tcp12 + Tcp12 - #9 Max - Tphl - Tphl - #27 Min - $402 Max # 12 - $50 = 83.3 ns + 83.3 ns + 83.3 ns 125 ns - 30 ns - 16 ns = 79 ns @ 16 MHz = 81 ns 16 MHz @ + 83.3 ns - 40 ns - 6.2 ns -7 ns - 10 ns -35 ns w/8420A-20 w/8420A-25 = 240 ns = 2 Tcp12 = #12 - $50 166 ns - 30 ns - 16 ns = 120 ns @ 12 MHz tRAC + s2 + sw + SW + 53 + s4 - 68020 ClK to AS Max - 74AS32 Delay Max - 74AS244 Delay Max - 74AS245 Delay Max - 68020 Data Setup Min - AREaS Asserted to RAS Asserted = s1 + Tcp16 + Tcp16 - #9 Max - Tphl Max - Tphl Max - Tphl Max - #27 Min - $102 Max = Tcp16 + 62.5 ns + 62.5 ns - 30 ns - 6.2 ns - 5 ns - 7 ns - 5 ns - 34 ns = 62.5 ns = 110 ns @ 16 MHz PortA 1 Wait State + Tcp12 + Tcp12 - #9 Max - Tphl Max - Tphl Max - Tphl Max - #27 Min - $102 Max + 83.3 ns + 83.3 ns - 40 ns - 6.2 ns - 5 ns - 7 ns - 10 ns - 42 ns = 83.3 ns + Tcp16 + Tcp16 - #9 Max - Tphl - Tphl - #27 Min - $402 Max = Tcp16 + = 110 ns @ = 139 ns @ 12 MHz 62.5 ns + 62.5 ns - 30 ns - 6.2 ns - 7 ns - 5 ns - 29 ns + 16 MHz + = Tcp12 #9 Max - Tphl - Tphl - #27 Min - $402 Max Tcp12 tRAC = s1 + s2 + sw + sw + sw + sw Tcp12 + 83.3 ns + 83.3 ns - 40 ns - 6.2 ns - 7 ns - 10 ns -35 ns = 83.3 ns = 163 ns @ 12 MHz I w/8420A-20 Heavy load 2 Wait States I w/8420A-25 Heavy load = I w/8420A-25 Heavy load = Tcp12 + s2 + sw + sw + s3 + s4 - 68020 ClK to AS Max - 74AS244 Delay Max - 74AS245 Delay Max - 68020 Data Setup Min - ADS Asserted to RAS Asserted = s1 = 62.5 ns I w/8420A-20 Heavy load 1 Walt State I tRAC AND 1CAC TIMING FOR DRAMs = I w/8420A-20 Heavy load - 68020 ClK to AS Max - 74AS32 Delay Max - 74AS244 Delay Max - 74AS245 Delay Max - 68020 Data Setup Min - AREaS Asserted to RAS Aserted Tcp16 + Tcp16 + Tcp16 + Tcp16 - #9 Max - Tphl Max - Tphl Max - Tphl Max - #27 Min - $102 Max + 62.5 ns + 62.5 ns + 62.5 ns - 30 ns - 6.2 ns - 5 ns - 7 ns -5ns-34ns = 62.5 ns 2 Walt States tRAC 12 MHz PortB Timing is supplied for the system shown in Figure 7 (See Figure 8). Since systems and DRAM times vary, the user is encouraged to change the following equations to match his system requirements. Timing has been supplied for systems with 1 or 2 wait states. If DElClK is not a multiple of 2 MHz, the timing for tRAH and tASC will change and must be calculated and changed according to the equations in the DP8420A/21A122A data sheet. tRAC @ s2 + sw + sw + s3 + s4 - 68020 ClK to AS Max - 74AS244 Delay Max - 74AS245 Delay Max - 68020 Data Setup Min - ADS Asserted to RAS Asserted = Tcp16 + Tcp16 + Tcp16 + Tcp16 - #9 Max - Tphl - Tphl # 27 Min - $402 Max = s1 + = 167 ns @ = Tcp12 + 16 MHz I w/8420A-25 Heavy load Tcp12 + Tcp12 + Tcp12 - #9 Max - Tphl Max - Tphl Max - Tphl Max - #27 Min - $102 Max = 83.3 ns + 83.3 ns + 83.3 ns + 83.3 ns -40 ns - 6.2 ns - 5 ns - 7 ns - 10 ns -42 ns w/8420A-20 = 223 ns @ 12 MHz Heavy load + 62.5 ns + 62.5 ns + 62.5 ns - 30 ns - 6.2 ns - 7 ns - 5 ns - 29 ns = 62.5 ns = 172.8 nS@16MHzlwH/8420lA-2d5 eavy oa 4-77 PortA 1 Walt State tCAC PortB 1 Walt State s2 + sw + sw + s3 + s4 - 68020 ClK to AS Max - 74AS244 Delay Max - 74AS245 Delay Max - 68020 Data Setup Min - ADS Asserted to CAS Asserted = Tep16 + Tep16 + Tep16 - #9 Max - Tphl - Tphl - # 27 Min - $403a Max = s1 + tCAC = + 62.5 ns + 62.5 ns - 30 ns - 6.2 ns - 7 ns -5 ns - 82 ns = 62.5 ns = 57 ns @ 16 MHz = = 62.5 ns + 62.5 ns + 62.5 ns - 30 ns - 5 ns - 6.2 ns - 7 ns -5 ns - 88 ns I w/8420A-25 Heavy load Tep12 + Tep12 + Tep12 = #9 Max - Tphl - Tphl - #27 Min - $403a Max = 46 ns = = 83.3 ns + 83.3 ns + 83.3 ns -40 ns - 6.2 ns - 7 ns - 10 ns - 94 ns w/8420A-20 = 92 ns @ 12 MHz Heavy load + Tep12 + Tep12 - #27 Min - $118a - 5 ns - 6.2 ns - 7 ns - 10 ns - 103 ns = 78 ns @ 12 MHz + S2 + sw + sw + sw + sw + s3 s4 - 68020 ClK to AS Max - 74AS244 Delay Max - 74AS245 Delay Max - 68020 Data Setup Min - ADS Asserted to CAS Asserted = Tep16 + Tep16 + Tep16 + Tep16 - #9 Max - Tphl - Tphl - # 27 Min - $403a Max = 62.5 ns + 62.5 ns + 62.5 ns + 62.5 ns - 30 ns - 6.2 ns - 7 ns -5ns-82ns = s1 + I w/8420A-20 Heavy load 2 Wait States tCAC = s1 + s2 + sw + sw + sw + sw + s3 s4 - 68020 ClK to AS Max - 74AS32 Delay Max - 74AS244 Delay Max - 74AS245 Delay Max - 68020 Data Setup Min - AREQB Asserted to CAS Asserted Tep16 + Tep16 + Tep16 + Tep16 - #9 Max - Tphl - Tphl - Tphl - #27 Min - $118a Max + = I w/8420A-25 Heavy load + 62.5 ns + 62.5 ns - 30 ns - 5 ns - 6.2 ns - 5 ns - 7 ns - 5 ns - 84 ns = 62.5 ns = Tep12 + Tep12 + Tep12 + Tep12 - #9 Max - Tphl - Tphl - # 27 Min - $403a Max = 83.3 ns + 83.3 ns + 83.3 ns + 83.3 ns - 40 ns - 6.2 ns - 5 ns - 7 ns - 10 ns - 94 ns = 171 ns @ 12 MHz Tep12 I w/8420A-25 Heavy load 16 MHz = 83.3 ns + 83.3 ns + 83.3 ns -40 ns 2 Walt States = 119 ns @ 16 MHz @ = #9 Max - Tphl - Tphl - Tphl I tCAC + s2 + sw + sw + s3 + s4 - 68020 ClK to AS Max - 74AS32 Delay Max - 74AS244 Delay Max - 74AS245 Delay Max - 68020 Data Setup Min - AREQB Asserted to CAS Asserted Tep16 + Tep16 + Tep16 - #9 Max - Tphl - Tphl - Tphl - #27 Min - $118 = s1 = 109 ns @ 16 MHz I w/8420A-25 Heavy load = Tep12 + Tep12 + Tep12 + Tep12 - # 9 Max - Tphl - Tphl - Tphl - #27 Min - $118 Max I w/8420A-20 Heavy load + 83.3 ns + 83.3 ns + 83.3 ns - 40 ns - 5 ns - 6.2 ns - 7 ns - 10 ns - 103 ns = 83.3 ns = 162 ns @ 12 MHz 4-78 I w/8420A-20 Heavy load . ClK ADS 68020 DSACK a ... BYTE ..... ENABLES - D ADS 11 ~l ~I ~I ~ p E(/)~~ - DTACK ! r I DSACK DATA GRANTB a D ClK D a '-- ~ '"c m~' ENA 1~1~1~,g C « r- C .oil .. 74AS244 r I .... 74AS244 . ~ BYTE ENABLES ~ EN .. 74AS245 ~ ADDRESS ClK 8422A J 68020 74AS138 I ATACKB fa ECASO - 3 I ~I VI ~ ClK Tcs J:t Lj ADDRESS I 74AS244 CLOCK r- U1 .... ~ DATA , n 32MHz ::: 4 » z EN DATA I/O DRAM ARRAY DATA I/O A . 74AS245 TLIF 19733-7 FIGURE 7. 68020 Dual Port System up to 16 MHz 4·79 ~ PORTS 51 51 51 I 51 50 I 51 52 I SW SW. 5W 5W I SW 5W ,5W SW I 53 54 I 55 51 I $I CLOCK PORTA ClK (8420A) AS (PORTA) AS PORTS ADDRESS (8420A) PORT A ADDRESS: PORT A ADDRESS : --!',.....-o!---!---+-J\,.....-,,--!----!---!',.....-!-',.......-!---o!--.....---!----!J\,--!-- DTACK (8420A) iiSACi( (PORTA) GRANTS DSACK (PORTS) RAS (8420A) ORTA ACCESS PORT B ACCESS PORT A ACCESS: CAS (8420A) DATA - - - - - - - . . . . . ( TUF/9733-8 FIGURE 8. 68020 Design #3 Timing. Delayed Dual Port Accesses 4-80 ~ ZI DRAM Speed Versus Processor Speed. (DRAM Speed References the RAS Access Time, tRAC, of the DRAM, Using DP8422A-25 Timing Specifications.) 25 25 MHz U1 Co) (Q 25 24MHz 23 MHz 22.7 22 MHz 22 21 MHz 20.1 20MHz >z w <.) ::> 8 ...'" >< <.) 0 DRAM KEY: 19MHz 18MHz _ 80ns DRAM mm 100 ns DRAM 17.1 17MHz 16MHz 15MHz ...J <.) 14MHz R D 13MHz 12MHz 11 104Hz 10MHz 120 ns DRAM 150 ns DRAM 9MHz 8MHz 68020 1 WAIT STATE, 4 CLOCKS PER ACCESS DESIGN #1 68020 2 WAIT STATES, 5 CLOCKS PER ACCESS DESIGN #2 68020 3 WAIT STATES, 6 CLOCKS PER ACCESS DESIGN #2 TLiF/9733-9 4-81 Interfacing the DP8422A to the 68020 (Zero Wait State Burst Mode Access) National Semiconductor Application Note 616 Lawson H. C. Chang INTRODUCTION DP6422A is operated in Mode 1. An access cycle begins when the 66020 places a valid address on the address bus and asserts the Address Strobe (AS) if a refresh or Port B access (DP6422A only) is not in progress. The proper ~ and CAS will be asserted respectively, depending upon programming bits C6, C5, and C4 for RAS and CAS configuration after guaranteeing the programmed value of row address hold time and the column address setup time. This application note describes interfacing the DP6422A DRAM controller (also applicable to DP6420Al21A) to the 66020 with slower memories. This design is based upon burst mode access by holding RAS low and toggling CAS. It is assumed that the user is familiar with the DP6422A and 66020 mode operations. DESIGN DESCRIPTION The High Speed Access (HSA) output signal of page detector indicates whether the current access is in the same page as previous access or not. AEiS (AREQ) is kept low if the current access is in the page, otherwise ADS (AREQ) will be forced to go high to terminate the burst access. Internal refresh logic automatically generates refresh request every 15 !'-S. The timing diagrams are shown in Figure 2 and Figure3. This design consists of the DP6422A DRAM controller, two PALs (16R4D and 16L6D), and a page detector (ALS6311). This design accommodates two banks of DRAM, each bank being 32 bits in width, giving maximum memory capacity of either 6 Mbytes (using 1M x 1 DRAMs) or 32 Mbytes (using 4M x 1 DRAMs). This design is based on 1M x 1 DRAM running at 16 MHz clock. The schematic diagram of interfacing DP6422A to the 66020 is shown in Figure 1. The CLOCK GENTR I ClK 68020 PALl SilO (3) Sill (4) FCO FCI (5) FC2 AD AI A24 A25 os (19)~<> (6) (7) (8) DSACK I AS DATA ~ ~ (2) '!" '!" ClK2 (I) CS RFRQ (3) DTACK ClK (5) (6) (7) ECASO PAL2 PFRQ Vee PAGE DETECTOR ALS63ll F (9) (8) (4) ECAS I (18)~ (17)~ ADDRESS <> ECAS2 (12) llD (2) DP6422A DEClK ECAS3 (13) l~D (1) ClK cs (16) CS (15) UUD (14) UWD (11) R!W b ClK ~K26 ~ Q A13-A22 ~ (12)_ (19) ADS Bl A2-Al1 CASO-3 ~ BO CONC9 L.:; (18) CSD (17) DTACKD DTACKDl (16) DTACKD2 (15) WE (14) ASD (13) ... ... RASO-3 RONR9 AI2 I ~ f--<> ADS AREQ DTACK 1 ~ X1 DRAM .. ~ f-<> WAITIN I ~ EN D TRANSCEIVER TL/F/l0440-1 FIGURE 1. Schematic Diagram of Interfacing DP8422A/68020 Burst Access 4-62 DP8422A PROGRAMMING BITS tRAC (Nonburst Access): 3 tcp - PAL tCLK Max. - PAL tp Max. - $402 ADS Low to RAS Low - # 27 Data Setup F245 Transceiver tp Max. = 187.5 ns - 8 ns - 10 ns - 29 ns - 5 ns - 6 ns (·25 Part) = 129.5 ns = 187.5 ns - 8 ns - 10 ns - 35 ns - 5 ns - 6 ns (·20 Part) = 123.5 ns tCAC (Nonburst Access): 3 tcp - PAL tcLK Max. - PAL tp Max. - $403a ADS Low to CAS Low - # 27 Data Setup F245 Transceiver tp Max. = 187.5 ns - 8 ns - 10 ns - 82 ns - 5 ns - 6 ns = 76.5 ns (·25 Part) = 187.5 ns - 8 ns - 10 ns - 94 ns - 5 ns - 6 ns (·20 Part) = 64.5 ns (Nonburst Access): 3 tcp - PAL tCLK Max. - PAL tp Max. - $417 ADS Low to Column Address Valid - #27 Data Setup - F245 Transceiver tp Max. = 187.5 ns - 8 ns - 10 ns - 78 ns - 5 ns - 6 ns = 80.5 ns (·25 Part) = 187.5 ns - 8 ns - 10 ns - 92 ns - 5 ns - 6 ns = 66.5ns (·20 Part) (Burst Access): 2 tcp - #9 CLK High to OS Low Max. - PAL tp Max. - $14 ECAS Low to CAS Low Max. - #27 Data Setup - F245 Transceiver tp Max. = 125 ns - 30 ns - 10 ns - 27 ns - 5 ns - 6 ns = 47 ns (·25 Part) = 125 ns - 30 ns - 10 ns - 31 ns - 5 ns - 6 ns u = User Defined Programming Bits RO, R1 = 0,1 R2,R3 = 0,0 R4,R5 R6 R7 R8 R9 CO,C1,C2 C3 C4,C5, C6 C7 C8 C9 BO B1 ECASO Description RAS High and Low Times DTACK Generation Mode for Nonburst Access = 0,0 DTACK Generation Mode for Burst Access =0 Add Wait States if WAITIN is Low = 1 DTACK Mode Select = 1 Noninterleave Mode =u All RAS's or Staggered Refresh Select = 0,1,0 Refresh Clock Divisor Select =0 Refresh Clock Divider Select = 0,0,1 RAS and CAS Configuration Mode = 1 tASC Mode Select = 1 tRAH Mode Select =u Delay CAS during Write Access Mode Select = 1 Fall through Mode = 1 Mode 1 Access = 1 Extend CAS and Refresh Request tAA DESIGN TIMING PARAMETERS Timing parameters are referenced to the numbers shown in the DP8422A data sheet timing parameters. Numbered times starting with a "$" refer to DP8422A timing parame· ters. Numbered times starting with a "#" refer to 68020 timing parameters. 16 MHz $400: tCAC tcp = 62.5 ns ADS Asserted Setup to CLK Yz tcp - PAL tCLK Max. = 31.25ns - 8ns = 23.25 ns $401: $416: #47: CS Setup to ADS Asserted 2 tcp + PAL tCLK Min. - #6 CO< to Address Valid - PAL tp Max. = 125 ns + 5.5 ns - 30 ns - 10 ns = 90.5 ns AREQ Negated to ADS Asserted tcp - (PAL tCLK Max. - PAL tCLK Min.) = 62.5 ns - 2.5 ns = 60 ns =GM ~~~ (Burst Access): 3.5 tcp - #6 CLK Low to Address Valid Max. $26 Address Valid to Q Max. - #27 Data Setup - F245 Transceiver tp Max. = 218.75 ns - 30 ns - 35 ns - 5 ns - 6 ns (·25 Part) = 142.75 ns = 218.75 ns - 30 ns - 38 ns - 5 ns - 6 ns = 139.75 ns (·20 Part) DTACK (68020) Low Setup to CLK Low Yz tcp - PAL tCLK Max. - PAL tp Max. = 31.25 ns - 8 ns - 10 ns = 13.5 ns 4·83 :J> Z ~ .... en U) ..- ~ cc r---------------------------------------------------------------------------------~ 68020PAL EQUATIONS The Boolean entry operators are listed as ": = " Replaced by (After Clock) "=" Equality Cj*" Outputs: IIACK- = ICS- = AND U+" OR "I" Complement Active low The brief explanation of PAL output signals CS This combinational output signal is Chip Select. CSDThis sequential output signal is Chip Select Delayed by one clock. ADSThis sequential output signal is Address Strobe (also used as an Access Request, I AREQ, to DP8422A). DTACKD- This sequential output signal is Data Transfer Delayed by one clock. DTACKD1- This sequential output signal is Data Transfer Delayed by two clocks. DTACKD2- This sequential output signal is Data Transfer Delayed by three clocks. WEThis sequential output signal is Write Enable to DRAM. DSACKThis combinational output signal is Data Transfer and Size Acknowledge. UUDThis combinational output signal is to select upper upper by1e. UMDThis combinational output signal is to select upper middle byte. lMDThis combinational output signal is to select lower middle byte. llDThis combinational output signal is to select lower lower by1e. IACKThis combinational output signal is interrupt acknowledge. IUUDIUMD- IlMD- IllD- IFC2 + IFC1 + IFCO IA23' IA24 • IA25 • IFC2 • IFC1 • FCO + IA23' IA24 • IA25 • IFC2 • FC1 • IFCO + IA23' IA24' IA25 • FC2 • IFC1 • FCO + IA23' IA24 • I A25 • FC2 • FC1 • IFCO = lAO' IA1 • IDS- • IAS= IS120' IA1 • IDS- • IAS- + AO' IA1 • IDS- • IAS- + SI21 • IA1 • IDS- • IAS= lAO' IA1 • IDS- • IAS- + IA1 • ISI20 • ISI21 • IDS- • IAS- + SI21 • SI20 IA1 • IDS- • IAS- + IS120'/A1 • AO • IDS- • IAS= AO • SI20 • SI21 * IDS- • IAS- + IS120' ISI21 * IDS- • IAS- + AO • A1 • IDS- • IAS- + A1 • SI21 • IDS- • IAS- (1/) PAL2 (PAL 16R6D) EQUATIONS Inputs: ClK2, CS-, HSA-, AS-, RFRQ-, DTACK-, ClK, RWIADS= IHSA- • IASDIDSACK= IDTACK- • IDTACKDIDTACKD- := IDTACK- • IClK + IDTACKD- • ClK IDTACKD1- := IDTACKD- • IClK + IDTACKD1• ClK IDTACKD2- := IDTACKD1- • IClK + IDTACKD2- • ClK IASD:= ICSD- • ClK IAS- + ICSD- • IHSA- • IAS- + ICSD- • IRFRQ- • IAS- + IRFRQ- • CSD- • IAS- + IRFRQ- • ClK' IAS- + IRFRQ- • IHSA- • IAS- + ICSD- • ClK' RFRQ- + ICSD- • IHSA- • RFRQ:= IRW- • AS- • ClK + IWE- • IWEIClK := ICS- • IClK + ICSD- • ClK ICSD- (I) PAL 1 (PAL 16L8D) EQUATIONS Inputs: AO, A 1, A23, A24, A25, FC2, FC1, FCO, S120, S121, DS-, AS- Note: PAL 1 address inputs, such as A23, A24 and A25, are system memory size dependent. 4-84 r - - - - NON BURST ACCESS - - - - - - BURST ACCESS -----+;- NON BURST ACCESS , ClK2 ADs AREQ ~~-----'- ________________-i______________-i__~~PRmEC~H~AR~G[E- ~r---------~ ______ ROW COL ffiffilrnm~--~::::l- 0:0,a.m ! ~--'C~__Ji------ROW COL ______________~----\:::~____~----1:::~ ______ ____________ -l______ ~~r---------------~~ ~~Kr-------~--~~~-L ~ ~~----~ __ ~r-~~-- TLlF/10440-2 FIGURE 2. Timing Diagram of Burst and Nonburst Access ClK2 ClK ~,~r---~::::~--~1_--~::::~---------------------------- ADS AREQ \---------------'1 ~~--------------+___(fP~REOCCH,HA~~GEE:\---------Jr-p,PRmre~H~AR~G[E:\-------REFRESH ROW COL ROW mm.rnro~--~::::l____1_--~::::~----------------------------[jJj,[\iOi ~ D~CK~-------l------+_--r---~----L---~-----L----~--~L---- RF~r---------'-____+_--------------~----------------------~r---------------t_~ _________________'------------------- FIGURE 3. Timing Diagram of Refresh, Burst and Nonburst Access. 4-85 TL/F/10440-3 ... ~ ~----------------------------------------------------------------------~ National Semiconductor Application Note 617 Chris Koehle ~ Interfacing the DP8422A ~ to an Asynchronous Port B in a Dual 68020 System INTRODUCTION This application note explains interfacing the DP8422A DRAM controller to two 68020 microprocessors that are running at the same frequency, but asynchronously to each other. This application note is a supplement to AN-539 (interfacing the DP8420Al21 A/22A to the 68020) and is intended to show synchronization logic and timing requirements for a Port B CPU that is running asynchronous to the DP8422A. It is assumed that the reader is already familiar with the 68020 access cycles and the DP8422A modes of operation. DESIGN DESCRIPTION This design shows all of the logic necessary to interface an asynchronous 20 MHz 68020 to the DP8422A Port B control inputs. This design is a worst case example and includes some logic that would not be needed in slower systems (i.e., 68000 @ 10 MHz). In our example, a Port B access begins when the asynchronous 68020 places a valid address on the address bus and asserts the address strobe, AS. In order to synchronize this signal to the DP8422A, it is run through two DO flip-flops, which are clocked by Port A's input clock. The first DO is run by an inverted clock in order to reduce the synchronization delay time by %T. Once AREOB is asserted, the access request is latched on the DP8422A and an access will start. If GRANTB is asserted, signaling Port B control of the access port, and a refresh is not in progress, the DP8422A will assert an access RAS. The transfer acknowledge signal, ATACKB is also asserted from AREOB asserting (or from the same edge of clock that starts RAS for a delayed access). AREaS also runs through two DO flip-flops before being input as DSACK to the 68020B. These two flip-flops serve a dual purpose, one being to synchronize the ATACKB signal to the 68020B clock, and the other is to provide 1T of delay for the ATACKS signal. Once DSACK is sampled as asserted by the 68020, AS is negated, signifying an end to the present access. AS negating is used to negate the DSACK input by presetting the two flip-flops connected to this input. This is done to guarantee that the 68020B DSACk signal is negated prior to the next access request being valid. The "a" output that is connected to the DSACK input on the 68020 is also run through 1%T of delay (2DO's) before it is used to preset the flip-flop that drives AREOB. The preset is used to negate the AREOB signal and to hold it negated for the required AREOB negated pulse width as specified by the DP8422A. AS is also used to preset this signal so A"FiEQB does not get asserted in instances where there are not back-to-back accesses. The 1%T delay is used so that the AREOS signal is negated after data is sampled by the 88020. In addition to the parameters calculated in AN-539, these additional parameters are included to show how the synchronizing logic still meets the necessary setup times required by the system (the "$" symbol refers to a DP8422A parameter, and the" #" symbol refers to a 68020 parameter). $101 AREOB Asserted Setup to ClK High (The DP8422A-25 needs 7 ns) = 1 Tcp - tpHL (74F74 DO Flip-Flop) =50ns-8ns = 42 ns #47a iSSA(;k Asserted Setup Time (68020 needs 5 ns) % Tcp - tpHL (74F74) 25 ns - 8 ns 17 ns AS negated pulse width guarantees the DP8422A meets AREOB negated pulse width ($117) through the preset of DO flip-flop which is connected to AREOB input. 4-86 » z PORT B (ASYNCHRONOUS) PORT A (SYNCHRONOUS) ~ + ClK,DlY ClK " ADDRESS PORT A 74AS244 lOCKA V WEA TRI-STATE BUFFERS CSA DATAENA ! ENA DIR EN "v 8422A "A ACCESS CONTROL TRANSCEIVER WE " J t-- " It lO~ EN - + "v A ACCESS CONTROL 68020 ClKA A v ADDRESS PORTB ++ REQUEST AND SYNCHRONIZING lOGIC CONTROL 68020 ~ 0 ADDRESS RASO-3 CASO-3 - L....- 74AS244 lOCKB DRAM J " ~ + ClKB TRI-STATE BUFFERS WEB A ADDRESS WE LOCK " CSB WE "'D~ A T AL-...I\ DATA ENB 6 DIR ENB EN V " TRANSCEIVER A TLlF/l0441-1 FIGURE 1. Dual Porting with the DP8422A with an Asynchronous Port B Synchronizing Logic for a Dual 68020 Asynchronous System ....-I (ASYNCHRONOUS) CLOCK A 1-----1~-------ClK t-t.....- . - ; AS AREQB 1-----1 DP8422A 68020 ""'-+---1 DSACK TL/F/l0441-2 4·87 0, ..... ...... 68020 Asynchronous Port B-Single Access CLKA CLKB AREQB (Q#2) QII6 TLlF/l0441-3 Back to Back Accesses where DQ Catches AS Negated Pulse in between Accesses CLKA CLKS Q#l % is2b! ~ ~ rt;;. ~ fSOl:l ~ ~ ~ ~ ~ ~ ~ rL \ Ah A - ~ I V :-\ \ I \ DSACK ~ \ ~ t. 1\ NOR ~RESET~ \ "'- I \ I \ \ I~ 'rI ~ ~ I I~ 1\ ~ ~ .t. r- \ output I I \ 0#5 --J / 0#3 ~ II r- L .~ II- r\ 1) \ ~ \ pRESET PQ#2 TLlF/l0441-4 4-88 z» . Back-to-Back Accesses where OQ# 1 Ooes Not Catch AS Negated Pulse in between Accesses Q) ...... ..... ClKA ClKB , rsow~~~rs%:.~rsOI±.rsi~~~~~rL rL 0#1 I I I I I I I I I \ I I I '~ I I ~,/.. ~ I \ / I \ J \ I \ I • • • (0#4) If 0#6 NOR output L.!!::EJ 00#2 ~ • • • IJ \H~ 0#5 J \ \ DSACK I I \~ J J 1/ r """"\ \ PRESET pO#2 TLlF/10441-5 4-89 ~ C") It) Z - ZI rl (II 74AS244 BUFFERS RO-l0 CO-l0 BO.l .4:.G . . ~1i (TO PAL) I 74AS138 DECODER Cs WIN R/W 68030 ~ ADDRESS BUS I ECASO-3 UUD.UWD.LWD.LLD RASO. 1 2 00-10 11 RAS2 3 2 2 BANKS OF 32 BITS OF DRAW WE DP8422A DELCLK. CLK CLK L~ CS ....... ADDvi~ STERW DATAO-31 ADS AREO AS ~ - DTACK 68030 PAL 1 CA~ AREO ENCAS '--- AREO FROW R;w~PALl " ] VI _ ENCAS ~ '" ;:- 4 000-3 ~2 I. DIR G TRANCEIVERS 74F245 [ DATAO-31 TL/F /9731-1 FIGURE 1.68030 Design, up to 25 MHz, with 2, 3 or 4 Walt States In Normal Accesses and 1 or 2 Wait State in Burst Accesses CLK ADDRESS rL rLrL r:LrLrLrt- rL rL. rLrL- DATA AS rr--, r---L r Il1.-- r-h AREO r- DTACK 2 DA 00 L...-fJ DC L-- L-fJ STERW L- f--I ENCAS L.. .--- , L.. f-J r--- r 1..-- Vi RFIP RAS (1:0) I RAS (3:2) ,-- CASG (3:0) B(I:0) \ 2 ECAS (3:0) ADOW EXST READ ACCESS BANK 1 WRITE ACCESS BANK 0 , FIGURE 2. 68030 Timing, 3 Walt States during Synchronous Accesses (ADDW = High) 4-93 TL/F/9731-2 elK AOORESS DATA AS AREQ OTACK 2 DA rL ~ rLrL -L rL -L rL rL rt-- ..... ~ r--"1 1---, r-r-- f-J jjjj r DC J STERM L..; i-I ENCAS -=;:t;:k: ..rr--- '--- L.; In ....r ~ ~ r- Vi RFIP 1,-- iiAS (1:0) iiAS (3:2) ~ CASG (3:0) ~ B(1:0) 1'\ 1'\ 1,- ~(3:0) ADDW EXST BANK 0 BURST ACCESS Tl/F/9731-3 FIGURE 3. 68030 Timing, 3 Walt States during Synchronous Accesses and 1 Walt State during Burst Accesses (ADDW = High) CLJ( ADDRESS DATA AS AREQ DTACK 2 r-L rLr-L rL ~r-L rL 2LrL rL ri:..rL rL -Lr-L I--- ~ r---h 1......- r- .I DA iii 1"'"- DC J L.. STERM L.. ~ ~ ENCAS r- rr--- Vi RFIP r--"1 HAS (1:0)1-' REF ESH 3T PRECH ~E iiAS (3:2) r- 3T PRECH RGE ,.-- CASG (3:0)11 8{1:O) ECAS (3:0) ADDW EXST I 1 I 1 I REFRESH DURING BANK 1 ACCESS TL/F/9731-4 FIGURE 4. 68030 Timing, 3 Walt States during Synchronous Accesses (ADDW 4·94 = High) :J> z T1 ClK W1 r L r-L ADDRESS lI. ri- rL ri- rLrLrL rLri- rLrL rL DATA AS r- r---, h DTACK 2 1..-- Ir-h I I iiA ....... - lI. AREQ I U1 c;,.) r- I II 1.- I DB r- IL..-- DC L- ~ STERM L I I ENCAS r- I 1.- J Vi RFIP r- RAS (1:0) RAS (3:2) II ,-- CASG (3:0) B(1:0) 2 \ ECAS (3:0) ADDW EXST BANK 1 READ ACCESS . BANK 0 READ ACCESS TLiF/9731-5 FIGURE 5. 68030 Timing, 4 Wait States during Synchronous Accesses (ADDW = Low) • 4-95 ~ C') r------------------------------------------------------------------------------------------. '9 ~ ClK ADDRESS rL rL rL rL rL rL rL. ~ r-1- rL DATA ... - AS h .- AREQ ~, DTACK 2 r- DA DB I--fJ DC L.t---J STER~ ENCAS L- :...-I -h I....., , r-- roo-- IL-- ..-L.. L. :...-l .r- Ir- Vi RriP Q(10:0) RAS r- (1:0) RAS (3:2) r-\ CASG (3:0) 1.- B(1:0) ECAS (3:0) ADDW EXST BANK 0 BURST ACCESS Tl/F/9731-6 FIGURE 6. 68030 Timing, 4 Wait States during Synchronous Accesses and 2 Wait States during Burst Accesses (ADDW = Low) ClK ADDRESS DATA AS AREQ DTACK 2 rL rL rL ru ~ru rL rL rL rL rL rL rL 2L.rL rL -==. ... :..-- ~ 1.- r- fJ .- DA DB ""-- DC L- STER~ ENCAS L.... 1..--- f---J ~ ,r- Vi RRP RAS ---, (1:0 ).J RE RESH 3T PRECH RGE PRECHAR E ACCES r- RAS (3:2) Ir-- CASG (3:0) 8(1:0) ECAS (3:0) ADDW EXST --- BANI< 0 ACCESS DURiNG DRAM REFRESH TLlF/9731-7 FIGURE 7. 68030 Timing, 4 Wait States during Synchronous Accesses (ADDW = Low) 4-96 l> z DRAM Speed Versus Processor Speed (DRAM Speed References the RAS Access Time, tRAC, of the DRAM Using DP8422A-25 Timing Specifications) 25MHz 25 • U'I W ~ 25m 24 MHz 23 MHz 22.4~ 23.2 22 MHz 2114Hz 2014Hz >- u ..,z :> ..,a ...'" '"uo .... u 1914Hz 18MHz 17MHz 20.5_ DRAM KEY: 17.4~ 1180ns DRAM ~ 16MHz 15MHz lOOns DRAM 14MHz 11120 ns DRAM 13MHz 12MHz D 1114Hz 10MHz 150"s DRAM 9MHz 8MHz--~----~--~~--~----~-- 68030 68030 3 WAIT STATES, 5 CLOCKS PER ACCESS 4 WAIT STATES, 6 CLOCKS PER ACCESS TUF/9731-8 II 4-97 It) ~ National Semiconductor Application Note 535 Webster (Rusty) Meier Jr. and Joe Tate A Dual Access DP8422AI cc 68030/74F632 Error Detecting and Correcting Memory System z• I INTRODUCTION This application note describes how to interface two 68030 microprocessors, both synchronous to the same system clock, to a DP8422A DRAM controller and a 74F632 EDAC chip. It is assumed that the reader is already familiar with 68030, the DP8422A, and the 74F632 modes of operation. The National Semiconductor DP8402A can be used in place of the 74F632 though its timing is slower. This design drives two banks of DRAM, each bank being 39 bits in width (32 data bits plus 7 check bits) giving a maximum memory capacity of 32 Mbytes of error corrected memory (using 4 M-bit x 1 DRAMs). By choosing a different RAS and CAS configuration mode (see programming mode bits section of DP8422A data sheet) this application can support 4 banks of DRAM, giving a memory capacity of 64 Mbytes (using 4M-bit x 1 DRAMs, NOTE that when driving 64 Mbytes the timing calculations will have to be adjusted to the greater capacitive load). This application note supports the following types of memory accesses: 1. Read accesses with 6 wait states inserted (8 clock periods total in the synchronous mode read access), any single bit errors are automatically corrected before sending the data to the CPU (EDAC unit in always correct model error monitoring mode is also described); The memory banks are interleaved on every four word (32bit word) boundary. This means that the address bit (A4) is tied to the bank select input of the DP8422A (Bl). Address bits A3,2 are tied to the highest row and column address inputs (R9, C9 for 1 Mbit DRAMs) to support burst accesses using nibble mode DRAMs. Nibble mode DRAMs must be usedl The reason for this is that nibble mode DRAMs support address wrap-around during a burst access. Address wrap-around is needed during an internal cache miSS where the 68030 starts a burst memory access on a non-page boundary (i.e., the first of a 4 word burst may have the least significant address bits, "A3,A2" = 10). Given this condition, the CPU expects word 2, word 3, word 0, word 1. On incrementing from word 3 to word 0 the address bit A4 must not change (the nibble page must remain the same). Nibble mode DRAMs support the address wraparound feature. 2. Write accesses with 3 wait states inserted (5 clock periods total in the synchronous mode write access); 3. Byte write accesses with 7 wait states inserted (9 clock periods total in the synchronous mode byte write access); 4. Burst read accesses with 3 wait states in the burst portion of the access (4 clock periods total per synchronous mode burst read memory access); 5. Scrubbing during DRAM refreshes (6 clock periods total during the refresh if no errors, 8 clock periods total during the refresh if any errors), any single bit errors are corrected. The corrected word is then written back to the DRAM. II DESCRIPTION OF 25 MHz DUAL ACCESS 68030 SYSTEM INTERFACED TO THE DP8422A AND THE 74F632 This design allows two 68030 microprocessors to access a common error corrected dynamic memory system. The error corrected memory system is implemented using the 74F632 EDAC chip in the always correct mode. Whichever 68030 accessed the memory last has a higher priority. Both 68030s are interfaced to the DRAM in the synchronous mode of operation (the accesses are terminated with the 68030 STERM input). This allows the DRAM system to support burst mode accesses. During read accesses the data is always processed through the EDAC chip (always correct type of system). If a single bit error occurs during a read access this design guarantees correct data to the CPU, but does not write the corrected data back to the DRAM. Single bit soft errors in memory are only corrected (written back to memory) during scrubbing type refreshes. The memory is scrubbed often enough that the probability of accumulating two soft errors in memory is very unlikely. During read accesses the data is always processed through the 74F632 EDAC chip (i.e., the EDAC data buffers are enabled to provide the data to the CPU). The 74F632 is always put into latch and correct mode during read accesses, even though the data from the memory may be correct. This al10...."8 "CAS to be toggled early (before the CPU has sampled the data), during burst mode accesses, to start accessing the next word of the burst access. Address bits A 1, AO are used to produce the four byte select data strobes, used in byte reads and writes. If the majority of accesses made by the 68030 are sequential, the 68030 can be doing burst accesses most of the time. Each burst of four words can alternate memory banks (address bit A4 tied to DP8422A pin Bl), allowing one memory bank to be precharging (RAS precharge) while the other bank is being accessed. This is a higher performance memory system than a non-interleaved memory system (bank select on the higher address bits). Each separate memory access to the same memory bank will generally require extra wait states to be inserted into the CPU access cycles to allow for the RAS precharge time. The logiC shown in this application note forms a complete 68030 memory sub-system, no other logic is needed. This SUb-system automatically takes care of: A. arbitration between Port A, Port B, and refreshing the DRAM; B. the insertion of wait states to the processor (Port A and Port B) when needed (i.e., if RAS precharge is needed, refresh is happening during a memory access, the other Port is currently dOing an access ... etc.); C. performing byte writes and reads to the 32-bit words in memory; D. normal and burst access operations. 4-98 A read, read with a single bit error, and burst read access timing are shown at the end of this application note implementing the error monitoring method. The user can see how these access cycles differ from the always correct method access cycles. By making use of the enable input on the 74AS244 buffer, this application allows dual access applications. The addresses and chip select are TRI-STATE~ through this buffer, the write input (WIN), lock input (LOCK), and ECASO-3 inputs must also be able to be TRI-STATE (another 74AS244 could be used for this purpose). By multiplexing the above inputs (through the use of the above parts and similar parts for Port B) the DP8422A allows dual accessing to be performed. IV 68030 25 MHz DUAL ACCESS DESIGN, PROGRAMMING MODE BITS Programming Description Bits III ANOTHER OPTION FOR A 68030 25 MHz DUAL ACCESS EDAC DESIGN: THE EDAC ERROR MONITORING METHOD IN CONJUNCTION WITH THE 68030 ASYNCHRONOUS LATE RETRY FEATURE RO = 1 R1 = 1 RAS low four clocks, RAS precharge of three clocks = 1 = 0 DTACK 1 is chosen. DTACK low first riSing CLK edge after access RAS is low. R2 R3 The 68030 dual access EDAC system design could use the error monitoring method in conjunction with the 68030 asynchronous late retry feature, instead of the always correct method (design shown in this application note). The error monitoring method can yield a slight improvement in system performance. By using the error monitoring method of error correction single read accesses or the first read access during a burst access can be shortened by one clock period, allowing a synchronous read access to have only 5 wait states inserted, 7 clock periods total (compared to 6 wait states, 8 clock periods total when doing the always correct method). All other types of accesses (burst reads, byte writes, word writes, refresh scrubbing) will execute in the same number of clock cycles, and in the same manner as described in this application note. Read accesses can save one wait state because the data from the DRAM memory is assumed to be correct in the error monitoring system design. Therefore the DRAM data is given directly to the CPU instead of running it through the EDAC chip as was done in the always correct method. R4 = 0 R5 = 0 No WAIT states during burst accesses R6 = 0 If WAITIN = 0, add one clock to DTACK. WAITIN may be tied high or low in this application depending upon the number of wait states the user desires to insert into the access. R7 = 1 Select DTACK R8 = 1 R9 = X Non-interleaved mode CO = X C1 = X C2 = X Select based upon the input "DELCLK" frequency. Example: if the input clock frequency is 20 MHz then choose CO,1,2 = 0,0,0 (divide by ten, this will give a frequency of 2 MHz). If DELCLK of the DP8422A is over 20 MHz do an initial divide by two ex1ernally and then run that output into the DELCLK input and choose the correct divider. C3 = X C4 = 0 C5 = 0 C6 = 1 In order to do this deSign it is required that the asynchronous late retry feature of the 68030 and registered transceivers (74F646) be employed. The asynchronous late retry feature of the 68030 involves pulling the 68030 input signals "BERR and HALT" both low before the falling clock edge of the last clock cycle of the access. Given that this is done the 68030 will suspend all bus activity until HALT is brought high and then will retry the aborted bus cycle (unless that access is not currently needed by the CPU). This feature is useful for the case where an error is detected in the DRAM data. In this case BERR and HALT are brought low until the data from the DRAM is corrected (by the EDAC chip) and written back to the DRAM. BERR and HALT are then brough high to continue CPU processing. RAS groups selected by "B1". This mode allows two RAS outputs to go low during an access, and allows byte writing in 32-bit words. C7 = 1 Column address setup time of 0 ns C8 = 1 Row address hold time of 15 ns C9 = 1 Delay CAS during write accesses to one clock after RAS transitions low = 1 Fall-thru latches B1 = 1 Access mode 1 ECASO = 0 Non-ex1end CAS BO o~ 1 ~ Program with low voltage level Program with high voltage level X ~ Program with either high or low voltage level (don't care condition) Registered transceivers (74F646) are necessary during burst mode read accesses because CAS transitions high before the CPU has sampled the DRAM data. The registered transceivers hold the data valid until the CPU samples it during these cases. II I 4-99 U) C") U) z• « r---------------------------------------------------------------------------------, 2b. Minimum address setup time to ClK high (used in #38 calculation below): 40 ns (one clock period) - 20 ns (assumed 68030 max time to address valid from ClK high) - 6.2 ns (74AS244 buffer delay max) = 13.8 ns V 68030 25 MHz WORST CASE TIMING CALCULATIONS The worst case access is an access from Port 8. This oc· curs because the time to RAS and CAS low is longer for the Port 8 access than; a Port A access, a refresh with scrub· bing access, or an access which has been delayed from starting (due to refresh, RAS precharge time, or the other Port accessing memory). 3a. Minimum CS setup time to ADS low (DP8422A·25 needs 5 ns, parameter # 401): A. Worst case time to RAS low from the beginning of an 16.3 ns (#2a) - 9 ns (max 74AS138 decoder) = 7.3 ns 3b. Minimum CS setup time to ClK high (PAL equations need 0 ns): 13.8 ns (#2b) - 9 ns (max 74AS138 decoder) = 4.8 ns 4. Determining tRAC during a normal access (RAS access time needed by the DRAM): 200 ns (five and one·half clock periods to get data from the DRAM to the 74F632 data inputs) - 3 ns (74F632 data setup time to mode input SO high) + 2.5 ns (mini· mum PAL 16R4D combinational output delay for "SO") - 84 ns (from "A" of worst case times, from the begin. ning of the access to RAS low) - 6.2 ns (74F244 DRAM buffer delay maximum) = 129.3 ns access cycle: 40 ns (T1 clock period of 68030) + 10 ns (PAL 16R4D maximum combinational output delay to produce AREQ8) + 41 ns (DP8422A·25 parameter #102, AREQ to RAS delay maximum) = 91 ns 8. Worst case time to CAS low from the beginning of an access cycle: 40 ns + 10 ns + 94 ns (DP8422A·25 parameter # 118a, AREQ8 to CAS delay maximum) = 144 ns C. Worst case time to DRAM data valid: 144 ns (from "8" above, maximum time to CAS) + 50 ns (CAS access time "tCAe" for a typical 100 ns DRAM) = 194 ns D. Worst case time to data valid on the EDAC data bus: 194 ns (from "c" above) delay) = 201 ns + Therefore the tRAC of the DRAM must be 129.3 ns or less. 7 ns (74AS244 maximum 5. E. Worst case time until the error flags are valid from the 74F632: 201 ns (from "0" above) + 31 ns (74F632 maximum time to error flags valid) = 232 ns F. Worst case time until corrected data is valid from the 74F632: 220 ns (five and one· half clock periods to get data from the DRAM to the 74F632 data inputs) - 3 ns (74F632 data setup time to mode input SO high) + 2.5 ns (mini· mum PAL16R4D combinational output delay for "SO") - 138 ns (from "8" of worst case times, from the be· ginning of the access to CAS low) - 6.2 ns (74F244 DRAM buffer delay maximum) = 75.3 ns 201 ns (from "0" above) + 28 ns (74F632 maximum time from data in to corrected data out) = 229 ns G. Worst case time until corrected data is available at the CPU: 229 ns (from "F" above) lay) = 236 ns + 7 ns (74F245 maximum de· 6. VI 68030 25 MHz DUAL ACCESS DESIGN, TIMING CAL· CULATIONS 1. Determining tCAC during a normal access (CAS access time) and column address access time needed by the DRAM: Minimum ADS low setup time to CLOCK high for DTACK logic to work correctly (DP8422A·25 needs 25 ns, parameter #400b): 40 ns (one clock period) - 10 ns (PAL 16R4D combina· tional output maximum that produces AREQ, ADS) = 30 ns 2a. Minimum address setup time to ADS low (DP8422A·25 needs 14 ns, parameter #404): 40 ns (one clock period) - 20 ns (assumed 68030 max time to address valid from ClK high) - 6.2 ns (74AS244 buffer delay max) + 2.5 ns (minimum PAL 16R4D combinational output delay that produces AREQ, ADS) = 16.3 ns 7. 8. Therefore the tCAC of the DRAM must be 75.3 ns or less. Determining the nibble mode access time needed dur· ing a burst access: 100 ns (two and one·half clock periods to do the burst) - 8 ns (PAL 16R4D clocked output delay maximum for ENCAS output) - 27 ns (DP8422A·25 ECASn to CASn asserted maximum, parameter #14) - 3 ns (74F632 data setup time to mode input SO high) + 2.5 ns (mini· mum PAL 16R4D combinational output delay for "SO") - 6.2 ns (74F244 DRAM buffer delay maximum) = 58.3 ns Therefore the nibble mode access time of the DRAM must be 58.3 ns or less Maximum time to DTACK1 low (PAL16R4D needs 10 ns setup to ClK): 40 ns (One clock) - 28 ns (DTACK2 low from ClK high on DP8422A·25, parameter # 18) = 12 ns Minimum STERM setup time to ClK (0 ns to ClK rising edge is needed by the 68030): 20 ns (one·half clock period) - 10 ns (PAL 16R4D com· binational output maximum) = 10 ns "''''Note: That calculations can be performed for different frequencies andlor different combinations of wait states by substituting the appropriate values into the above equations. 4·100 + OEB * RFIP • 06 * SERR + R * WORO • 05 • BClK + OEB • R * WORO * 05 + OEB • R * WORO * 06 IF (VCC) OECB = R * WORO * RFIP • S1 + RFIP • 05 • BClK • SERR + OECB • RFIP * 05 • SERR + OECB * RFIP • 06 • SERR + R * WORO * 05 • BClK + OECB * R * WORO * 05 + OECB * R * WORO * 06 IF (VCC) STERMA = R * RFIP * 05 * 06 • GRANTB * BClK + STERMA * R • RFIP • 05 • GRANTB * BClK + R * WORO * RFIP * 02 • 06 * GRANTB * BClK + STERMA * R * WORO * RFIP * 02 • 06 • GRANTB * BClK + R * WORO • RFIP * 05 * 06 * GRANTB * BClK + STERMA * R * WORO • RFIP * 06 * GRANTB * BClK VII 68030 25 MHz DUAL ACCESS EDAC SYSTEM DESIGN, PAL EQUATIONS WRITTEN IN NATIONAL SEMICONDUCTOR PlANTM FORMAT OP1 PAl16R40 BClK ClK CSASA CSB ASB OTACK ATACKB WCBREQ RFIP GNO OE RASa COUNT ENCAS 03 02 01 AREQB AREQVCC IF (VCC) AREQ = CSASA • ClK + AREQ • CSASA + AREQ' ClK IF (VCC) AREQB = CSB • ASB • ClK + AREQB • CSB • ASB + AREQB' ClK IF (VCC) COUNT = AREQ' OTACK • CSASA + AREQB • ATACKB * ASB + RFIP' RASa 01 := AREQ • OTACK + ATACKB * AREQB + RFIP * RASa 02:= 01 • 03 • COUNT + 03 • AREQ • OTACK • RFIP 03 : = 02 • COiJNf IF (VCC) STERMB = R * RFIP * 05 * 06 * GRANTB * BClK + STERMB * R * RFIP * 05 * GRANTB • BClK + R * WORO • RFIP * 02 * 06 * GRANTB * BClK + STERMB * R * WORO * RFIP • 02 • 06 • GRANTB * BClK + R * WORO • RFIP * 05 • 06 • GRANTB * BClK + STERMB * R * WORO * RFIP • 06 * GRANTB * BClK OP3 PAl16R40 BClK ClK so S1 ERR MERR COUNT 02 03 GNO OE OECB BERR 06 05 04 WE SERR lEDBO VCC IF (VCC) lEOBO = 02 * so * S1 * ClK + lEOBO * 03 • so + lEOBO' ClK IF (VCC) SERR = 04 * So • S1 * COUNT * ERR * ClK + SERR * COUNT IF (VCC) BERR = 04 * So * S1 * COUNT * MERR * ClK + BERR * COUNT WE := S1 • 02 • 03 * COUNT * OECB ENCAS: = WCBREQ + 01 + 02 + 03 + RFIP OP2 PAl16l80 BClK R WORO GRANTB RFIP SEAR 52 55 06 GNO OE STERMB STERMA OECB OEB TRAN_EN S1 so EXRF VCC IF (VCC) EXRF = RFIP • S1 • 02 • 05 • 06 • SERR + EXRF • RFIP • S1 • 05 * 06 + RFIP • 05 • SERR IF (VCC) so = R • WORO • RFIP + 02' 05 + so· BClK + 05' BClK + so· 05 + SO' 06 + S1 • SERR • RFIP IF (VCC) S1 = R • WORO • RFIP + 05' BClK + S1 • 05 + S1 • 06 • R * WORO + S1 • 06 • RFIP + S1 • SERR • RFIP IF (VCC) ""T"RA.-N"'"_----..E=N = R • 55 • BCD< • RFIP + TRAN_EN * R • 05 • 06' RFIP + R * 05 * STERMA * RFIP + R • 05 * STERMB • RFIP + R * WORO • S1 • RFIP + R * WORO * 05 • BClK • RFIP + TRAN_EN * R * WORO * 55 • RFIP + TRAN_EN * R • WORO * 06 * RFIP IF (VCC) OEB = R • 05 * BClK + OEB * R * 05 + RFIP * 05 * BClK * SERR + OEB * RFIP • 05 • SERR 04 := 03 * COUNT 05 := 04 * COUNT 06:= 05 * COUNT Key: Reading PAL equations written in PLAN EXAMPLE EQUATIONS: IF (VCC) AREQ = CSASA * ClK + AREQ * CSASA + AREQ * ClK This example reads: the output "AREQ" will transition low given that one of the following conditions are valid; 1. the input "CSASA" is low ANO the input "ClK" is high, OR 2. the output "AREQ" is low ANO the input "CSASA" is low, OR 3. the output "AREQ" is low ANO the input "ClK" is low. 4-101 . » z U1 to) U1 CLOCK GENERATOR 3 '" AS CS RIW CBRro STREM CBACK' 2 68030 .I:I I CONTROL LOGIC "I BERR -l 4 RiTc 1'1. ADDRESS 2-25 BUFFERS 7<1AS244 V LOCK V 1'\ PORTA '\ ROW,COLUMN BANK ADDRESS'; v I FROM COIilllOL WE I WE I B 1 T S I 4 BIDIRECTIONAL DATA FROM CPU I -l\ V " EN Ii 4 BUFFERS PORTA ROW,COLUMN BANK ADDRESS 7<1AS2<14 39 BITS or DATA+ CHECKBITS 1\ r- " EDAC MODE, LATCH AND BurFER CONTROL II 8 EDAC UNIT P~TA 74r632 2 ERROR FLAGS "I V 4 7<1F24S IlL-- rROM CONTROL LOGIC TO CONTROL LOGIC 1'1. ] DATA 0-31 v ~ s I .1pOBJ R/W B --1\ B I T DRAM BUFFERS I ::.. D A T A 32 5 BurFERS 7<1AS24<1 DATA + CHECK BITS IJ! I !'EN V 7' ADDRESS 2-25 BurFER ENABLE FROM CONTROL LOGIC DATA + CHECKBITS INTO MEMORY A EDAC DATA Be CHECKBIT BUS A 'I MULTIPLEXED ADDRESS 00-10 11 DRAM MEMORY UP TO 4 BANKS OF 39 BITS (DATA + CHECK BITS =39) USING 4M X 1 DRAMS = 64M BYTES OF ERROR CORRECTED DRAM .:;... TRANSCEIVER ENABLES FROM CONTROL LOGIC 4 4 LOCK DP8422A I~~ D A T A 32 DATA STROBES Vl ~ v{;l~ E~k=TlIF/9729-1 Control logic In this system needs the following: 3 PAL~s and some logic gates 'OIDiOl< is tied low back to 68030 FIGURE " Block Diagram of Dual Access 68030 Error Detecting and Correcting (74F632) Memory System 4·102 . »z fee - 20 "'"'- FROM 74F632 =:: ERR ~ MERR X 1 2 3 4 5 6 7 8 9 ClK ClK SO Sl ERR MERR COUNT 02 03 PAL #3 FOR 68030 EDAC SYSTEM 19 lEDBO 18 SERR 17 WE 16 04 15 05 14 06 13 BERR 12 OECB 11 OE ~ U1 Co) U1 TO 74F632 ~- TO DRAMs "'A A- TO GRANTED 68030 -& ..J!..O t~cc 20 -=::. R WORD" f-¢ FROM DP8422A A -=- - ClK R WORD GRANTB RFIP SERR 02 05 06 1 2 3 4 5 6 7 8 9 PAL #2 FOR 68030 EDAC SYSTEM ..J!..O 19 18 17 16 15 14 13 12 11 EXRF SO Sl A TRAN EN ;:. OEB OECB STERMA STERMB OE =- -... ...,E:XRF (COLINC of DP8422A). TO PORT DECODER THEN TRANSCEIVERS TO BYTE DECODER THEN 74F632 TO 74F632 PORT A 68030 PORT B 68030 -& ~~~il.----c> TO DP8422A t-;.;'-,!;~'------<:J FROM DP8422A TL/F/9729-2 'If WORD is low then 32 bits are being accessed from the memory system. If WORD is high then less than 32 bits are being accessed from the memory system. FIGURE 2. Control Logic for 68030 Dual Access EDAC Memory System 4·103 LI) ('I) LI) z• cc rL rL ~ rtW2 ClK W3 ASA ~ AREQ W4 W5 W6 ~~~ T2 TI ru IL TI ~ I DTACK I Ir1.-- ii1 52 I r-- D3 54 I I 55 II 56 1.- I STERMA I I WE RFIP RAS (1:0) RAS (3:2) CAS (3:0) ENCAS I " , 3 " ERR OEB,OECB , " SO,Sl lEDBO, TRAN_EN CPU ADDRESS EDAC DATABUS VALID I I I I J I 1 I '" I '" J ,"2 I READ READ ACCESS I CORRECT I 1 I TL/F/9729-3 FIGURE 3. 68030 EDAC Read Access Timing 4·104 rL r-L r-L rLr-L r-L- IL- r---L r L r L IL-IL-IL-11- r L r L IL-IL ---, r-L r-L BWI BW2 BW3 T3 BWI BW2 BW3 T4 BWI BW2 BW3 T5 I Iii r-h D-'- : ---.J i ; I irt--~ 'L-.. I .r- )4 , I ; L-- STEIiA L. :...-.J L. ~ L. :...-.J L. f--I iF !o iii 01 RAS ( 11 RAS ( 'I f-J CAS ( Jl f..--.J '\ C '\C C I '\ C I '\ C I.-n 1'-1 r-1 ~ CAS ERR OEB,O ECB L-----J SI ,SI 1 LEDBO, TRAN. ~I CPU ADDR ESS EDAC DATAl IUS Previous '\1 '-J I 1 ~ Read Access '\2 I ,\1 I 1 1 'T' '\1 I 1 '\1 '\ 2 I 1 I 1 '\1 I 2 I '\1 X CORRECT 3 )-( I ~ VAUD I I I READ 1 CCRRECT 1 1--( READ 2 X CORRECT 2 ) - ( READ 3 READ 4 X CORRECT 4 BURST READ ACCESS TL/F/9729-4 FIGURE 4. 68030 EDAC Burst Read Access Timing seS-NV II Ln (II) r---------------------------------------------------------------------------------~ ~ z cc T2 ClK ASA rL- r-L ----I AREQ II rt.. rt.. rLr-LriI I DTACK 0; 52 r- I , II I II L .... .... ii3 54 ~ '-- J .... OS 56 STERMA :, r- ~ ~ WE RFIP RAS (1 :0) 1 RAS (3:2) CAS (3:0) C 1 J~ " " 3 ENCAS 2 1 1 1 I ri\ SO,S 1 lEDBO, TRAN_EN 2 12 1 CPU ADDRESS I EDAC DATABUS CORRECT PREVIOUS READ ACCESS _I I - 1 VALID WRITE WORD WRITE ~ J TL/F/9729-5 FIGURE 5, 68030 EDAC Word Write Access Timing 4-106 T1 n- rL rL r---LrL ASA ---, ClK rurL rL r-1- r-L I AREa r- ~ DTACK 51 ..J II 52 II Ir I II 03 ..J D4 ~ Ir Ir I II ~ 55 os I STERMA I I WE RFIP RAS (1:0) r '\ RAS (3:2) II CAS (3:0) ~ 1(; li ENCAS ERR OEB,OECB ~ 50,51 ~ lEDBO, TRAN_EN ~ CPU ADDRESS EDAC DATABUS r- '\ I1T '\ '\ 1 VALID I ~ r- ,\1,\ I ,\1 I I READ I BYTE WRITE ACCESS - - I 2 CORRECTED - .TLlF/9729-6 FIGURE 6. 68030 EDAC Byte Write Access Timing II 4·107 TI ClK TI RF1 RF2 RF3 RF4 RFS RF6 rL.- r-t-r-t- rL.- rL.- r-t-r-t- r--L- rL.- r-t- AREQ DTACK iij .-- ..J 52 I l...-- ~ II 03 ..J ii4 I I ~ 55 r- I D6 L..- r- STERMA WE RFIP h RAS (1:0) V RAS (3:2) CAS (3:0) ~ , , REFRESH NO ERRORS I I C ENCAS EXTENDIREFRESH EXRF I ERR ", OEB,OECB SO,S 1 lEDBO, TRAN_EN , I ", , I r I CPU ADDRESS EDAC DATABUS READ _ CORRECT DRAM REFRESH WITH SCRUBBING TLiF/9729-7 FIGURE 7. 68030 EDAC DRAM Refresh with Scrubbing 4·108 n W2 WI W3 W4 W5 W6 W8 W7 WID W9 TI T2 Wll ClK AREQ I I DTA: I I I I I I 52 I J J J I I I I II I r-I Ir-- ii3 I ~ L--Ir-- I os ii6 S~RMA .J L s WE §I " , . 1 1 I I I s RFIP REFRESH WITH SINGLE BIT ERROR RAS(I:0)P J RAS (3:2) ' l i n ,- I CAS (3:0) , J 3 ENCAS 1 I EXRF I EXTEND REFRESH ERR '1 SO,51 'I ''+I--+---+----l--+-+--t---+--+--+--tI' I'~2_...,..._-..,.__.,...._...,...__~_...,...._.....,._ '1, lEDBO, TRAILEN CPU ADDRESS , '2' OEB,OECB VAlID EDAC DATABU5 READ I. )-( I CORRECT )..1..(-----SCRUB~'NG . I . WRITE ACCESS DURING DRAM REFRESH WITH SINGLE BIT ERROR WliltEAccrssDIfA -,-- - - ~ I TL/F/9729-8 FIGURE 8. 68030 EDAC Write Access during Refresh Timing StS-NV II AN-535 T2A CLK AREQB WBI WB2 rt- r L r L ~ ATACKB iii ii2 OJ WB5 WBB WB7 WB6 WB9 WBl0 , , , , , iii L-- , WE L ~I I I L-- ~ , OS STERIotB TI T2B , , , ii4 WB4 , , , WB3 ra- ~rt- r L r Lra-rt-rt- r, L ru , i R -, GRANTB RAS (1:0) RAS (3:2) CAS (3:0) I 3 " I 3 ENCAS EXRF ERR OEB,OECB I SO,SI I LEDBO, TRANJ:N OPIU22A ADDRESS mAC OATABUS 2 , I PI WRIJ[ A 1 I , I POR ][ I I I I I I I I ROO PORTB PORT B ACESS DURING PORT A ACCESS FIGURE 9.6B030 EDAC Port B Access during Port A Access '1 I ", n7 I '2 - CORR B J-TUF/9729-9 :I> Z Tl WI W2 W3 WI, W5 T2 T1 W1 W2 W3 WI, W5 T2 .1.1 .1.2 TI BCLK ADS,AREQ WE to DRAMs STERht RASn CASn TRAN_EN (CLOCK OF) CPBA 74F646 CPAB E D A C U N 1 T OECB ERR FLAG OEBO-3 SO,SI READ READ --0= DRAhtBUFLEN DATA ON EDAC BUS BERR,HALT READ ACCESS (NO ERRORS) WRITE BACK TL/F/9729-10 FIGURE 10.68030 EDAC Error Monitoring Method Using the Asynchronous Late Retry Feature of the 68030 4-111 • UI W UI Lt) (f) Lt) I Z T1 c:( WI W2 W3 W4 W5 T2 BWI BW2 BW3 T3 BWI BW2 BW3 T4 TI TI BCLK ADS,AREQ WE to DRAMs STERt.1 RASn CASn TRAN_EN (CLOCK OF) CPBA 74F646 CPAB E D A C U N I T OECB ERR FLAG OEBO-3 SO,SI = LEDBO DRAt.1BUFF_EN DATA ON EDAC BUS BERR, HALT READ WITH BURST BURST BURST TLIF/9729-11 FIGURE 11.68030 EDAC Error Monitoring Method Using the Asynchronous Late Retry Feature of the 68030 4-112 National Semiconductor Application Note 544 Webster (Rusty) Meier Jr. Interfacing the DP8420AI 21A/22A to the 8086/1861 88/188 Microprocessor I INTRODUCTION This application note describes how to interface the 80186 microprocessor to the DP8422A DRAM controller (also applicable to DP8420A/21A). It is assumed that the reader is already familiar with 80186 and the DP8422A modes of operation. This application note will also allow the 8086/88/ 188 to interface to the DP8420Al21A122A. II DESCRIPTION OF DESIGN, 8086/88/186/188 OPERATING AT UP TO 16 MHz (UP TO 12.5 MHz WITH 0 WAIT STATES) cess application the tRAC and tCAC (required RAS and CAS access time required by the DRAM) will have to be recalculated since the time to RAS and CAS is longer for the dual access application (see TIMING section of this application note). 1118086/186/88/188 DESIGN, 10 MHz WITH 0 WAIT STATES DURING NORMAL ACCESSES, PROGRAM MODE BITS Programming Bits The block diagram of this design is shown driving four banks of DRAM, each bank being 16 bits in width, giving a maximum memory capacity of up to 32 Mbytes (using 4 M-bit X 1 DRAMs). The memory banks are interleaved on word (16-bit word) boundries. This means that the address bits (A 1,2) is tied to the bank select inputs of the DP8422A (BO,l). Address bit AO is used, along with Bus High Enable (BHE), to produce the two by1e select data strobes. These byte selects (AO, BHE) are used in byte reads and writes as well as selects for the transceivers. This application allows 0 or more wait states to be inserted in normal accesses of the 8086/186/88/188. The number of wait states can be adjusted through the WAITIN input of the DP8422A. The logic shown in this application note forms a complete ~ R2 R3 R4 R5 R6 ~ ~ ~ ~ ~ ~ 0 1 0 0 0 0 0 R7 ~ 0 R8 = 1 R9 = X CO = X Cl ~ X C2 ~ X 8086/186/88/188 memory sub-system, no other logic is needed. This sub-system automatically takes care of: A. arbitration between Port A, Port B and refreshing the DRAM; B. the insertion of wait states to the processor (Port A and Port B) when needed (i.e., if RAS precharge is needed, refresh is happening during a memory access, the other Port is currently doing an access ... etc); C. performing by1e writes and reads to the 16-bit words in memory. C3 C4 C5 C6 If the system uses the 8086/88 the "ALE" output can be directly input to the DP8420Al21A122A, the 74AS08 "AND" gate and the two 74AS04 inverters on the "ALE" output are not needed. By using the "output control" pins of some external latches (74AS373's), this application can easily be used in a dual access application. The addresses could be tri-stated through these latches, the write input (WIN), lock input (LOCK), and ECASO-3 inputs must also be able to be tristated (a 74AS244 could be used for this purpose). By multiplexing the above inputs (through the use of the above parts and similar parts for Port B) the DP8422A can be used in a dual access application. If this design is used in a dual ac- RO Rl ~ ~ ~ ~ X 0 1 1 C7 = 1 C8 = 1 C9 ~ 1 BO = 1 Bl = 0 ECASO = 0 o= Description RAS low two clocks, RAS precharge of two clocks. If more RAS precharge is desired the user should program three periods of RAS precharge. WAIT zero is chosen. WAIT follows the access RAS low. No WAIT states during burst accesses If WAIT = 0, add one clock to WAIT. WAITIN may be tied high or low in this application depending upon the number of wait states the user desires to insert into the access Select WAIT Non-interleaved Mode Select based upon the input "DELCLK" frequency. Example: if the input clock frequency is 10 MHz then choose CO,l ,2 = 1,0,1 (divide by five, this will give a frequency of 2 MHz). RAS banks selected by "BO,l". This mode allows one RAS output to go low during an access, and allows byte writing in 16-bit words. Column address setup time of 0 ns. Row address hold time of 15 ns Delay CAS during write accesses to one clock after RAS transitions low Fall through latches. Access mode 0 CAS not extended beyond RAS Program with low voltage level 1 = Program with high voltage level X = Program with either high or low voltage level (don't care condition) 4-113 V 8086/186/88/188 TIMING CALCULATIONS FOR IV 8086/186/88/188 TIMING CALCULATIONS FOR DESIGN AT 10 MHz WITH NO WAIT STATES DURING NORMAL ACCESSES DESIGN AT 16 MHz WITH ONE WAIT STATE DURING NORMAL ACCESSES (THE WAITIN INPUT OF THE DP8422A SHOULD BE TIED LOW) 1. Minimum ALE high setup time to CLOCK high (DP8422A20 needs 16 ns, #301a): 100 ns (one clock period) - 9 ns (maximum delay through two 74AS04S) - 6 ns (74AS08 max delay) = 85 ns 2. Minimum address setup time to ClK high (DP8422A-20 needs 20 ns, #303): 100 ns (one clock period) - 50 ns (min address valid delay, TClAV parameter in 80C186 data sheet) - 6 ns (74AS373 max delay) + 1 ns (74AlS04B min delay) = 45 ns 3. Minimum CS setup time to clock high (DP8422-20 needs 14 ns, # 300): 45 ns (#2 above) - 10 ns (max 74AlS138 decoder) = 35 ns 4. Determining tRAG during a normal access (RAS access time needed by the DRAM): 200 ns (two clock periods to do the access) - 32 ns (ClK to RAS low max, DP8422-20 # 307) - 15 ns (8086/ 186/88/188 data setup time, TDVCl) - 8 ns (74AS245A max delay) - 5 ns (74AS04 max delay, clock skew) = 140 ns Therefore the tRAG of the DRAM must be 140 ns or less. 5. Determining tGAG during a normal access (CAS access time) and column address access time needed by the DRAM: 200 ns - 89 ns (ClK to CAS low on DP8422A-20, #308a) - 15 ns - 8 ns - 5 ns = 83 ns Therefore the tGAG of the DRAM must be 83 ns or less. 6. Minimum SRDY (Synchronous ReaDY) setup time to SYSClK low (ClK to DP8422A is inverted from SYSClK), 8086/186/88/188 SRDY input needs 15 ns, TSRYCl: 100 ns (one clock period) - 39 ns (DP8422A-20 max delay to WAIT 0 high after arbitration, parameter # 17) = 61 ns 1. Minimum ALE high setup time to CLOCK high (DP8422A20 needs 16 ns, #301a): 62.5 ns (one clock period) - 9 ns (maximum delay through two 74AS04s) - 6 ns (74AS08 max delay) = 47.5 ns 2. Minimum address setup time to ClK high (DP8422A-20 needs 20 ns, # 303): 62.5 ns (one clock period) - 33 ns (min address valid delay, TClAV parameter in 80C186 data sheet) - 6 ns (74AS373 max delay) + 1 ns (74AlS04B min delay) = 24.5 ns 3. Minimum CS setup time to clock high (DP8422A-20 needs 14 ns, #300): 24.5 ns (#2 above) - 10 ns (max 74AlS138 decoder) = 14.5 ns 4. Determining tRAG during a normal access (RAS access time needed by the DRAM): 182.5 ns (three clock periods to do the access) - 32 ns (ClK to RAS low max, DP8422A-20 # 307) - 15 ns (8086/186/88/188 data setup time, TDVCl) - 8 ns (74S245A max delay) - 5 ns (74AS04 max delay, clock skew) = 122.5 ns Therefore the tRAG of the DRAM must be 122.5 ns or less. 5. Determining tGAG during a normal access (CAS access time) and column address access time needed by the DRAM: 182.5 ns - 89 ns (ClK to CAS low on DP8422A-20, #308a) - 15 ns - 8 ns - 5 ns = 65.6 ns Therefore the tGAG of the DRAM must be 65.5 ns or less. 6. Minimum SRDY (Synchronous ReaDY) setup time to SYSClK low (ClK to DP8422A is inverted from SYSClK), 8086/186/88/188 SRDY input needs 15 ns, TSRYCl: 62.5 ns (one clock period) - 39 ns (DP8422A-20 max delay to WAIT 1 high, parameter #17) = 23.5 ns Note: Calculations can be performed for different frequencies, different logic (ALS or CMOS ... etc), or the DP8422A-25, and/or different combinations of wait states by substatuting the appropriate values into the above equations. Note: Calculations can be performed for different frequencies, different logic (ALS or CMOS ... etc), the DP8422A-25 and/or different combinations of wait states by substatuting the appropriate values into the above equations. 4-114 ALE ClKOUT ClK, DElClK ALE ALE 1 - - - - - 1 DT/R WIN RASO- 3 I----.. RAs CASO- 3 t----I~CAS AREQ CS OP8420A/21 A/22A IotEIotORY BO 80186 • WE I----I~WE ADDRESS Bl RCO- 9,10 ECASO, 1 ECAS2,3 SRDY A WAIT DATA I/O BHE r---<...J;:::'...J BHE TL/F/973B-1 @May not be needed in all memory applications 'If using the SOS6/88 the two inverters (74AS04) and the "AND" gate (74AS08) are not needed, ALE from the 8086/88 can be directly connected to the DP8420A/21A/22A ALE input. FIGURE 1.80186 Block Diagram SYSClK ClK (DP8422A) ALE (80186) ADDRESS/ DATA !Q--+o-" WR 80186 ADS (B422A) RFIP (B422A) --+--+--O+--+--I'\. '-i~"""-I" RAS--+--i.. (B422A) '--I-....Jf SRDY (B422A) (WAiT) --+--+--+--+-ool '--+--+--f--+-~ READ CYClE--r-----RE~~~TrRtr18~SS----+I TL/F/973B-2 FIGURE 2. 80186 Timing 4·115 ~ r----------------------------------------------------------------------------, ~ DRAM Speed Vs. Processor Speed, (DRAM Speed References the RAS Access Time, tRAC, of the DRAM, using DP8422A-25 Timing Specifications) ~ z cc 17WHz 16.7 16WHz 15WHz DRAW KEY: 14.5 >- ...z ...... 14WHz 0 => 0 '" "".... 0 1180ns DRAW 13.6 13WHz 12.7 ~ 11.3 111120 ns DRAW lOOns DRAW 12WHz 0 0 11 WHz D 10WHz 9.6 150ns DRAW 9WHz 8WHz 8086/186 o WAIT STATES, 4 CLOCKS PER ACCESS 8086/186 1 WAIT STATE, 5 CLOCKS PER ACCESS 4-116 TL/F/9738-3 .----------------------------------------------------------------,~ ~ =F Interfacing the DP8420A/21A/22Atothe 80286 National Semiconductor Application Note 545 Webster (Rusty) Meier Jr. and Joe Tate INTRODUCTION B. The insertion of wait states to the processor (Port A and Port B) when needed (i.e., if RAS precharge is needed, refresh is occurring during a memory access, the other Port is currently doing an access ... etc.); This application note describes how to interface the 80286 microprocessor to the DP8422A DRAM controller (also applicable to DP8420A/21 A). There are three designs contained within this application note. The designs differ in terms of the maximum allowable frequency of operation. Design #1 can be used up to 16 MHz (80286-8) with one wait state. Design #2 can be used up to 20 MHz (80286-10) with one wait state. Design #3 can be used up to 25 MHz (80286-12) with one wait state. It is assumed that the reader is already familiar with 80286 access cycles and the DP8422A modes of operation. DESCRIPTION OF DESIGN # 1, ALLOWS UP TO 16 MHz OPERATION (CLOCK OUTPUT OF THE 82284) WITH NO WAIT STATES USING THE 80286-8 Design # 1 (see Figures 1 and 2) consists of the DP8422A DRAM controller and several logic gates. These parts interface to the 80286 as shown in the block diagram. It accommodates two banks of DRAM, each bank being 16 bits in width, giving a maximum memory capacity of 16 Mbytes (using 4M-bit X 1 DRAMs). By choosing a different RAS and CAS configuration mode (see programming mode bits section of 8422A data sheet) this application could support 4 banks of DRAM, giving a memory capacity of 32 Mbytes (using 4M-bit X 1 DRAMs). The memory banks are interleaved. This means that the least significant address bit (A 1) is tied to the bank select input of the DP8422A (B1). Because the majority of accesses made by the 80286 will be sequential in nature, one memory bank can be precharging (RAS precharge) while the other bank is being accessed. The interleaved memory system has higher system performance than a non-interleaved memory system. In a non-interleaved memory system, each sequential access will generally be to the same memory bank thereby requiring extra wait states to be inserted into the CPU access cycles to allow for the RAS precharge time. The user can choose non-address pipe lined mode for this design as long as the parameter "AREQ negated to ClK high minimum to guarantee tASR = 0 ns" is guaranteed (45 ns minimum for the 8422A-20, 39 ns for the 8422A-25). At 16 MHz, the user must choose address pipe lined mode since it is not possible to meet the above parameter (62.5 ns one clock - 25 ns MRDC,MWRC max valid 5.5 ns 74AS08 max delay + 1 ns min 74ASOO CLOCK delay = 33.5 ns which is less than the 39 ns the DP8422A-25 needs). When using the DP8422A in address pipelined mode, the DRAMs chosen should need a minimum column address hold time of 32 ns or less. The logic shown in this application note forms a complete 80286 memory sub-system, no other logic is needed. This sub-system automatically takes care of: A. Arbitration between Port A, Port B, and refreshing the DRAM; ~ U'I C. Performing byte writes and reads to the 16-bit words in memory. Since the WE output of the DP8422A becomes refresh request (RFRQ) if the chip is programmed in address pipelining mode, the WIN signal was buffered to provide WE to the DRAMs. The gates labeled "U1" should both be in the same package (74ASOO) so that their delays cancel, see the TIMING section for how these delays cancel. The ready logiC can be made faster by programming DTACKO into the DP8422A and running this through a fast bipolar flip-flop clocked by CLOCK. By making use of the enable input on the 74AS373 latch, this application can easily be used in a dual access application. The addresses and chip select are TRI-STATE® through this latch, the write input (WIN), lock input (LOCK), and ECASO-3 inputs must also be able to be TRI-STATE (a 74AS244 could be used for this purpose). By multiplexing the above inputs, (through the use of the above parts and similar parts for Port B) the DP8422A can be used in a dual access application. All the timing (see TIMING section of this application note) will remain the same whether single or dual accessing is implemented. DESCRIPTION OF DESIGN #2, ALLOWS UP TO 20 MHz OPERATION (CLOCK OUTPUT OF THE 82284) WITH NO WAIT STATES USING THE 80286-10 DeSign # 2 (see Figures 3, 4, 5) is basically the same as Design # 1 except for the following changes: A. The circuit that produces SRDY, the gate signal for the 74AS373 transparent latches, and AREQ has been changed to using DTACKO, several 74AS374 flip-flops, and some logic gates. This was needed for speed in producing the gating signal of the 74AS373 (so as to get adequate address and chip select setup time), B. The output "D1" which is used to produce the AREQ input was gated with CS. This was done to guarantee that the DTAcK2 output becomes defined after power up, C. This deSign will work at 20 MHz, D. This design has zero wait states inserted in normal sequential accesses, multiple wait states may be inserted on multiple accesses to the same memory bank, during DRAM refreshing, or during accesses from Port B if dual accessing is used (DP8422A only). In the 80286 READY lOGIC, the 74AS374 flip-flop that produces the D2 output has some gating at its inputs. This gating is used to synchronize the D2 output to the 80286 PClK so as to end the access at the correct time. The user can choose non-address pipelined mode for this design as long as the parameter "AREQ negated to CLK high minimum to guarantee tASR = 0 ns" is guaranteed 4-117 • ~ ~--------------------------------------------------------------------------------, ;;z cC (45 ns minimum for the 8422A-20, 39 ns for the 8422A-25). At 20 MHz, the user should choose address pipelined mode since it is not possible to meet the above parameter (50 ns one clock - 8 ns 74AS374 max delay - 4.5 ns 74ASOO max delay + 1 ns min 74ASOO CLOCK delay = 38.5 ns which is less than the 39 ns the DP8422A-25 needs). The user should also keep in mind that when using the DP8422A in address pipelined mode the DRAMs chosen need a minimum column address hold time of 32 ns. 80286 DESIGN # 1, UP TO 16 MHz WITH NO WAIT STATES, PROGRAMMING MODE BITS Programming RO=O R1=1 DESCRIPTION OF DESIGN #3, ALLOWS UP TO 25 MHz OPERATION (CLOCK OUTPUT OF THE 82284) WITH ONE WAIT STATE USING THE 80286-12 R2=1 R3=0 R4=0 R5=0 R6=1 R7=1 R8=X Design # 3 (see Figures 6, 7, 8) is very similar to Design #2 except for the following changes: A. The circuit that produces SRDY, the gate signal for the 74AS373 transparent latches, and AREa has been changed to use DTACK2, a 74AS175 flip-flop, and some logic gates. This was needed because the 8428812 was not known to be available, and also for speed in producing the gating signal of the 74AS373, 8. The AREa input was gated with CS using gate "U2". This was done to guarantee that the DTACK2 output becomes defined after power up, C. Description Bits R9=X CO=X C1=X C2=X This design will work at 25 MHz and possibly beyond, if the 80286 is ever produced at faster speeds (see the TIMING section for Design #3), D. This design has one wait state inserted in normal sequential accesses, multiple wait states may be inserted on multiple accesses to the same memory bank, during DRAM refreshing, or during accesses from Port 8 if dual accessing is used (DP8422A only). C3=X C4=1 C5=1 C6=1 The user can choose non-address pipelined mode for this design as long as the parameter "AREa negated to ClK high minimum to guarantee tASR = 0 ns" is guaranteed (45 ns minimum for the 8422A-20, 39 ns for the 8422A-25). At 25 MHz, the user must choose address pipelined mode since it is not possible to meet the above parameter (40 ns one clock - 7.5 ns 74AS175 max delay - 1 ns min 74ASOO CLOCK delay = 33.5 ns which is less than the 39 ns the DP8422A-25 needs). The user should also keep in mind that when using the DP8422A in address pipelined mode the DRAMs chosen need a minimum column address hold time of 32 ns. C7=1 C8=1 C9=1 80=1 81 =0 ECASO=O In the 80286 READY lOGIC, the 74AS175 flip-flop that produces the D4 output has some gating at its inputs. This gating is used to synchronize the D4 output to the 80286 PCLK so as to end the access at the correct time. o RAS low two clocks, RAS precharge of two clocks. It should be noted that the user should choose RO,1 = 11 when operating above 16 MHz to allow enough RAS precharge time DTACK low one clock from RAS low No WAIT states during burst accesses If WAITIN=O, add two clocks to DTACK Select DTACK The user may choose address pipe lined mode (R8 = 0) remember to choose DRAMs with column address hold times of 32 ns or less, or non-address pipelined mode (R8 = 1), at clock frequencies below 16 MHz. Select based upon the input clock frequency. Example: if the input clock frequency is 12 MHz then choose CO,1 ,2 = 0,0,1 (divide by six, this will give a frequency of 2 MHz). RAS and CAS groups selected by "81 ". This mode allows two RAS and two CAS outputs to go low during an access, and allows byte writing in 16-bit words. Column address setup time of 0 ns. Row address hold time of 15 ns. Delay CAS during write accesses to one clock after RAS transitions low Fall-thru latches Access mode 0 Non-extend CAS mode = Program wnh low voltage level 1 = Program wi1h high voltage level X = Program with either high or low voltage level (don't care condition) 4-118 ):00 80286 DESIGN # 2, UP TO 20 MHz WITH NO WAIT STATES, PROGRAMMING MODE BITS 80286 DESIGN #3, UP TO 25 MHz WITH ONE WAIT STATE, PROGRAMMING MODE BITS Programming Bits Programming Bits RO=1 R1=1 R2=0 R3=0 R4=0 R5=0 R6=0 R7=1 RS=X R9=X CO=X C1=X C2=X C3=X C4=1 C5=1 C6=1 C7=1 CS=1 C9=1 80=1 81 =0 ECASO=O o= Description RO=1 RAS low four clocks, RAS precharge of three clocks R1=1 R2=1 R3=0 R4=0 R5=0 R6=0 DTACK low from RAS low No WAIT states during burst accesses If WAITIN = 0, add one clock to DTACK. Since we are not using the WAITIN input it should be tied high on the DP8422A. Select DTACK The user may choose address pipelined mode (RS = 0), remember to choose DRAMs with column address hold times of 32 ns or less or non-address pipelined mode (RS = 1), at clock frequencies below 20 MHz R7=1 RS=X Select based upon the input clock frequency. Example: if the input clock frequency is 16 MHz then choose CO,1,2 = 0,1,0 (divide by eight, this will give a frequency of 2 MHz). R9=X CO=X C1 =X C2=X RAS and CAS groups selected by "81". This mode allows two RAS and CAS outputs to go low during an access, and allows byte writing in 16-bit words. Column address setup time of 0 ns. Row address hold time of 15 ns. Delay CAS during write accesses to one clock after RAS transitions low Fall-thru latches Access mode 0 Non-extend CAS mode C3=X C4=1 C5=0 C6=1 C7=1 CS=1 C9=1 Program with low voltage level 1 = Program with high voltage level x= Program with either high or low voltage level (don't care condition) 60=1 61=0 ECASO=O o= 1 ~ ZI U1 ~ U1 Description RAS low four clocks, RAS precharge of three clocks DTACK low one clock from RAS low No WAIT states during burst accesses If WAITIN = 0, add one clock to DTACK. Since we are using DTACK2 the WAITIN input should be tied low on the DP8422A. Select DTACK The user must choose address pipelined mode (RS = 0), at clock frequencies above 20 MHz. Also remember to choose DRAMs with column address hold times of 32 ns or less or non-address pipelined mode (RS = 1), at clock frequencies below 20 MHz Select based upon the input clock frequency. Example: if the input clock frequency is 12 MHz then choose CO,1,2 = 0,0,1 (divide by six, this will give a frequency of 2 MHz). For a CPU frequency of 24 MHz the clock could be divided by two initially to give a 12 MHz input to the DELCLK input of the DPS422A. RAS and CAS groups selected by "81". This mode allows two RAS and two CAS outputs to go low during an access, and allows byte writing in 16-bit words. Column address setup time of 0 ns. Row address hold time of 15 ns. Delay CAS during write accesses to one clock after RAS transitions low Fall-thru latches Access mode 0 Non-extend CAS mode Program with low voltage level Program with high voltage level X = Program with either high or low voltage level (don't care condition) • 4-119 ..,. U) , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - , U) z• DTACKI = SRDY RAsa, 1 CASO,I RAS2,3 CAS2,3 DATA RFlP WRITE DATA REFRESH TL/F/9739-2 FIGURE 2. 80286 Design # 1 Timing, up to 16 MHz (80286-8), No Wait States StS-NV II Lt) ;Z r---------------------------------------------------------------------------------~ Vee J - M/io BHE,AO ,,2 , WRITE 0 r S-- SRDY PCLK - .. ... II. QO-8910 OPB420A/21A/22A CAS23 ECASO,2 ECAS1,3 AREQ -AREQ 80286 LCS-+ READY ~CLOCK LOGIC I+--ALE ~ LCS v DTACKO II. ::.. '" .. - DIR DATA MEMORY WE WIN DT/R v RAS2,3 ALE Ul 51 80286 82284 Bl I LATCH ADDRESS Be Mlfo 74AS373 I ADDRESS V I So 1 LCS IDECODERJ-l 74ALS138 EN TRANSCEIVERS 74AS245 IA DATA TLlF/9739-4 FIGURE 3. 80286 Block Diagram of Design # 2, Mode 0, up to 20 MHz DTACKO 02 0 Q 74AS374 01 CLOCK LCS PCLK JO-...._ _ _~AR.::E:::l.Q (TO READY, G, ~)------~~ ANOARro) PCLK 02 CLOCK TL/F/9739-5 FIGURE 4. 80286 Ready Logic for Design #2 4-124 WRITE ACCESS TS TC READ ACCESS TS TC READ ACCESS (SA~E BANK) TS TC TC READ ACCESS DURING REfRESH TS TC TC TC TC CLOCK SO·S; ALE AREO= SRDY=G WIN LATCHED ADDRESS 00 ! D1 '"U1 D2 RASO, 1 CASO,1 CD RAS2,3 CAS2,3 DATA ( WRITE 1 RFIP REFRESH TLlF/9739-6 FIGURE 5. 80286 Design #2 Timing, up to 20 MHz (80286-10), No Wait States StS-NV II "t..rim ClOCK I Ji ADDRESS & t.l1iO LATCHED CHIP SELECT LATCH 74AS373 J I ADDRESS .6 I Bl & t.l/io READ=O BHE,AO -=c>.J 80286 READY LOGIC ~ RASO, 1 ... CASO,I ~ "v RAS2,3 DP8420A/21 A/22A CAS23 , ~2 t.lEt.lORY WE ECASO, 2 ECAS1,3 U2~ LCS D3 PCLK 1\ WIN ~f SRDY 0-89 10 ALE Ul WRITE=O ~ Al 'tG Sl 80286 82284 - ., SO 1 LCS I:DECODER 74ALS138 _11 ~ r r CLK,DLYCLK CLOCK DTACK2 SYSTEt.l RESET ~CLOCK ~ +--ALE ~ WIN-1) H LCS DT/R - " DIR TRANSCEIVERS 74AS245 DATA v "-EN A DATA .. TL/F/9739-8 FIGURE 6. 80286 System Block Diagram of Design #3, Mode 0, up to 25 MHz PClK-----------------------~---_i D a mACK2---------~~>C~D=2---------~ D 04----1 03----1 74AS175 Q F-PCLK a 03 Q D3 a 04 (TO READY, G, AND AREa) Q a ALE Q ClOCK------------------------------~~ CLOCK SYSTEt.l RESET ---------------------------------------1 FIGURE 7. 80286 Ready Logic for Design #3 4·126 TUF/9739-9 WRITE ACCESS 15 TC READ ACCESS TC 15 TC READ ACCESS (SAME BANK) TC 15 TC TC READ ACCESS DURING REFRESH 15 TC Te TC TC TC TC CLOCK SO-51 ALE AREQ WIN LATCHED ADDRESS !I '" 02 .." 03 D3=G= SRDY I I I I I PCLK SYNCHRONIZES 04 IN THESE TWO ACCESSES I 04 I I I RASO, 1 RAS2,3 I I I DATA I WRITE READ READ RFIP TLlF/9739-10 FIGURE 8.80286 Design #3 Timing, up to 25 MHz (80286-12), with One Wait State per Access StS-NV -11-- ..., Ion Ion Z• 32 MHz) the WIN - input may need to be sampled by a flip-flop (clocked by 8420CLK -) before being input to the PAL to meet the setup requirements of the PAL inputs. This would have the effect of delaying ECAS - 0, t becoming valid by one clock period (CLK -) during read accesses, this would not affect the performance of this interface. II 4·135 AN-618 80286/DP8421A Page Mode Timing (Design #2) IN-PAGE ACCESSING 1- Ts Te Te TS , Te TS ~ DIFfERENT PAGE (SAME BANK) ~ I ~ I ~ I ~ I ~ I " ~ I ~ I ~ CLK ~ ,.iJ4-th+8~$f::q= 8420ClJ(~ CPU SOl AOSo- l , " I.R£Q.. , \.l, WIN- ADDRESS !c.> 0> ~, }, , " NEW PAGE SAME PAGE HSA~ RFRODYACK~ (DTI2~) SRDY~ N~ ECAS..Q.l RAs--o.l ~2.3 00-.0-3 DATA , [' :' A# }: READ lJ ~~ ~------~---~------~--< TL/FI10442-4 80286/DP8421A Page Mode Timing (Design #2) rTS TC TC I ~ I IN-PAGEl DIFFERENT PAGE (OTHER BANK) ~ I ~ I ~ REFRESH WITH PENDING ACCESS ACCESS ~ I ~ I Tc Ts Tc TS TC TC TC I I I I I I I I I I I I 1\ TC ClK 842DCLKN CSN CPU 501 ~ AOSN IJ, LREQN WINN ADORESS ! '".... HSAN ~ I XI XINON-CS ACCESS XI I ~l: :01 XI I I, I II RFRQN OTACKN (DT12N) SRDYN NOA~ -;\ I ECASNO, 1 RASNO, 1 RASN2, 3 CA$NQ-3 DATA I I I If I I I I I I I I I I 1 I I I I I I I " I ,'-- I I I I I I I -V I I I I I I I -:\ I I I I I I I I I I I I I I -:\ I I I I I I I I I I I I I I 1 I I I I I I I I I I I I I '\ 'i/ I I '\ I I I : I I I : I I I I I ~~ " READ If / ~'" '- READ If I I '/ I I I + PRE.\:HARGE I I r- RE~RESH I I 1/ I I I I '\ I I I 1 _'" I I I I I \ I /' I I I I t I I : I I I I I I I I ~~' I I I I READ ---.I I TLlF/10442-5 8~9-N\f II (g , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - , z~ Interfacing the c:c National Semiconductor Application Note 536 Webster (Rusty) Meier Jr. and Joe Tate DP8420A/21 A/22A to the 80386 ~ INTRODUCTION This application note describes how to interface the 80386 microprocessor to the DP8422A DRAM controller (also applicable to DP8420Al21A). The 80386 is interfaced with the DP8422A in both address pipelined (Design # 1) and nonaddress pipelined (Design #2) mode up to 50 MHz (8038625). It is assumed that the reader is already familiar with 80386 access cycles and the DP8422A modes of operation. I. DESCRIPTION OF DESIGN # lA and lB, THE 80386 IN ADDRESS PIPELINED MODE, ALLOWING OPERATION UP TO 50 MHZ (80386-25) WITH ONE WAIT STATE PER ACCESS. (40 MHZ, TWO WAIT STATES PER ACCESS AT 50 MHZ) The # 1 Designs (80386 in address pipelined mode) consist of the DP8422A DRAM controller, a single PAL® (PAL 16R8D), and several logic gates. These parts interface to the 80386 as shown in the block diagrams. This design accommodates two banks of DRAM, each bank being 32 bits in width, giving a maximum memory capacity of 32 Mbytes (using 4 Mbit x 1 DRAMs). See Figures 1-5. Design # 1A differs from # 1 8 in terms of the maximum operating frequency. Design # 1A can operate up to 40 MHz, Design # 18 can operate up to 50 MHz. Designs # 1A and 8 allow 1 wait state per access for read cycles and 2 wait states per access for write cycles in address pipelined mode. The memory banks are two way interleaved. This means that the least significant address bit (A2) is tied to the bank select input of the DP8422A (81). 8ecause the majority of accesses made by the 80386 will be sequential, one memory bank can be precharging (RAS precharge) while the other bank is being accessed. This allows the memory system to be much higher performance than a non-interleaved memory system. In a non-interleaved memory system, each successive access will generally be to the same memory bank thereby requiring extra wait states to be inserted into the CPU access cycles to allow for the RAS precharge time. In Designs 1A and 18, the PAL (PAL 16R8D) is used primarily to support the address pipelining capability of the 80386 (next address input, NA#). Since the NA# input is only allowed to drop low at the end of the current access no address latches are needed in the system. If address buffers were desired they could be used, but the DP8422A-25 would have to be used in order to meet the bank address and chip select setup times (see "80386 32 MHz Timing Calculations" section). An input is provided (EXT_NA) on the PAL for other system peripherals to have their NA inputs synchronized to the system clock (up to 50 MHz). Designs 1A and 18 have one wait state during successive address pipelined accesses to alternating memory banks. During accesses to the same memory bank multiple wait states will be inserted to guarantee RAS precharge. If the user desires two wait states during successive address pipelined accesses (an extra wait state per access), this can be accomplished by running RASO and RAS2 through a flip-flop (clocked by CLKA) before allowing them to be input to the PAL in Design # 18. This will delay NA and READY by one CLKA clock period. In Design # 1A the WAITIN input could be tied low and programmed to add 1 clock to the DTACK output. If the user wants to do dual accessing with the DP8422A DRAM controller, address buffers (74AS244s) must be added to the address, ECASO-3, LOCK, and WIN inputs. For the 32 MHz system (80386-16), the system diagram will remain unchanged, but the user will need to use the faster DP8422A-25 part. For higher frequency dual access memory systems (above 32 MHz), these designs will have to be modified as above. Also, CLKA should be inverted (use 1Q output from 74AS175). This will cause RAS to be started one half CLKA clock period later, allowing extra address and chip select setup time to the DP8422A. II. DESCRIPTION OF DESIGN #2, THE 80386 IN NON· ADDRESS PIPELINED MODE, ALLOWING OPERATION UP TO 40 MHZ (80386·20) WITH TWO WAIT STATES PER ACCESS (50 MHZ WITH THREE WAIT STATES) DeSign # 2 (80386 not using address pipelined mode) consists of the DP8422A DRAM controller, several flip-flops (74AS175), and several logic gates. These parts interface to the 80386 as shown in the block diagrams. This design accommodates two banks of DRAM, each bank being 32 bits in width, giving a maximum memory capacity of 32 Mbytes (using 4 Mbit x 1 DRAMs). See Figures 6-10. The memory banks are two way interleaved. This means that the least significant address bit (A2) is tied to the bank select input of the DP8422A (81). 8ecause the majority of accesses made by the 80386 will be sequential, one memory bank can be precharging (RAS precharge) while the other bank is being accessed. This allows the memory system to be much higher performance than a non-interleaved memory system. In a non-interleaved memory system, each successive access will generally be to the same memory bank thereby requiring extra wait states to be inserted into the CPU access cycles to allow for the RAS precharge time. Design # 2 has two wait states during successive accesses to alternating memory banks. During accesses to the same memory bank multiple wait states will be inserted to guarantee RAS precharge. If the user desires three wait states during successive accesses (an extra wait state per access), this can be accomplished by pulling WAITIN low during accesses. WAITIN should be programmed to add one clock period (CLKA) to the DTACK output. This will delay READY by one CLKA clock period. 4-138 The timing calculations for two designs (Designs # 1 and # 2) are included in this application note with the DP8422A interfaced to the 80386-16 running at 32 MHz and the 80386-20 running at 40 MHz. Since the DP8420A/21A/22A has a column address hold time of 32 ns the minimum time between two accesses (to guarantee 0 ns row address setup time) is 150 ns (equivalent to three clock periods at 20 MHz, 150 ns). When using the DP8420Al21A/22A at 20 MHz the user should program three clock periods of precharge. This is because two clock periods of precharge at 20 MHz will only guarantee 81 ns of RAS precharge (2 x 50 ns - t01, (parameter #50 "14 ns") - clock (20 MHz) to AREa high, (approximately 5 ns for both design # 1 and # 2)). In DeSign #2 the four gates "A1, A2, B, C" are not necessary if the system designer already has some means of correctly enabling the data transceivers. Also, in Design # 2 the NOR gate that produces READY will not be needed in many systems, the 3a output of the 74AS175 could be used instead (READY2.5). Though, this output would not allow quite as much READY setup time as the output of the NOR gate. Because of the way ALE is generated to the DP8422A, two pulses of ALE may be generated during each access (see timing diagrams 3,4,5,8,9 and 10). This is not detailed in the DP8420Al21 A/22A data sheet but this is permissible as long as no glitches happen after AREa transitions low for that access. Therefore, this is a valid way of providing ALE to the DP8422A. If the user wants to do dual accessing with the DP8422A DRAM controller address buffers (74AS244s) must be added to the address, ~0-3, TI5CK and WIN inputs. For the 32 MHz system (80386-16), the system diagram will remain unchanged, but the user will need to use the faster DP8422A-25 part. For higher frequency dual access memory systems (above 32 MHz), design # 2 will have to be modified as above. Also, CLKA should be inverted (use 10 output from 74AS175). This will cause RAS to be started one half CLKA clock period later, allowing extra address and chip select setup time to the DP8422A. III. COMMON DESIGN FEATURES The logic shown in these applications form a complete 80386 memory sub-system, no other logic is needed. This sub-system automatically takes care of: a. arbitration between Port A, Port B, and refreshing the DRAM; b. the insertion of wait states to the processor (Port A) when needed (I.e., one wait state during address pipelined accesses (# 1 Designs), two wait states during non-address pipelined accesses (Design # 2), multiple wait states if an access takes place during a refresh operation or if RAS precharge is needed ... etc.); c. enabling address pipelining on the 80386 through the NA# input (#1 Designs only), and d. performing byte writes and reads to the 32-bit words in memory. 4-139 U) , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - , CO') ~ ~ IV. 80386 DESIGN # 1 AND #2, PROGRAMMING MODE BITS Programming Bits RO = 1 R1 = 1 Description RAS low four clocks, RAS precharge of three clocks R2 = X R3 = X R4 RS R6 R7 R8 R9 CO C1 C2 = 0 No WAIT states during burst accesses = 0 = X = X = 0 = = X = Interleaved Mode (requires DRAMs with a column address hold time of 32 ns or less) X X Select based upon the input clock frequency. Example: if the input clock frequency is 16 MHz then choose CO, 1,2 = 0, 1,0 (divide by eight, this will give a frequency of 2 MHz). = X C3 = X C4 = 1 CS = 0 C6 = 1 RAS and CAS groups selected by "81". This mode allows two RAS and two CAS outputs to go low during an access. C7 = 1 C8 = 1 Column address setup time of 0 ns. Row address hold time of 15 ns. C9 = 1 Delay CAS during write accesses to one clock after RAS transitions low 80 = 1 81 = 0 Fall-thru latches Access mode 0 ECASO=O Non-extend CAS o= Program with low voltage level 1 = Program with high voltage level X = Program with either high or low voltage level (don't care condition) delay)-2 ns ("0" speed PAL minimum clock delay, for skew between 32 MHz and 16 MHz clock) = 37.S ns V.80386 # 1 DESIGNS (AND # 2 DESIGN), 32 MHZ TIMING CALCULATIONS, WITH ONE WAIT STATE PER ACCESS IN ADDRESS PIPELINED MODE, TWO WAIT STATES PER ACCESS IN NON-ADDRESS PIPELINED MODE (DP8422A-20 USES THE 16 MHZ CLOCK) The CLKA delay to ALE through 74AS02 is similar: 31 ns (one half clock period, 16 MHz) +4.S ns (74AS02 maximum delay) + 1.S ns (PAL estimated skew between low to high and high to low clock to output delay) = 37 ns Note: Design # 2 timing calculations are the same as Design # 1 except for those calculations involving "CLKA", Timing calculations involving the minimum or maximum delay or skew of CLKA with respect to CLK2 should be recalculated substituting the 74AS175 parameters for the PAL parameters. 3. Minimum ALE high setup time to CLKA high (OP8422A20 needs 16 ns): 62.5 ns (one clock period, 16 MHz)-37.5 ns (#2) = 25 ns 4. Minimum address setup time to CLKA high (DP8422-20 needs 20 ns): 1. Maximum time to address valid (with respect to 16 MHz clock): 62.5 ns (Once clock period, 16 MHz)-38 ns (#1) = 24.5 ns 40 ns (maximum time to address valid) - 2 ns ("D" speed PAL minimum delay, because 16 MHz clock is from PAL with minimum delay as skew from 32 MHz CPU clock) = 5. Minimum CS setup time to CLKA high (DP8422-20 needs ;4 ns): S8 ns 24.S ns (#4)-9 ns (74AS138 decoder) = 15.S ns 2. Maximum time to ALE high (with respect to 16 MHz clock): 35 ns (maximum ADS valid) + 4.5 ns (74AS02 maximum 4-140 . r--------------------------------------------------------------------.~ 2. Maximum time to ALE high (with respect to 20 MHz clock): 30 ns (maximum ADS valid) +4.5 ns (74AS02 maximum delay) - 2 ns (PAL minimum clock delay, for skew between 40 MHz and 20 MHz clock) = 32.5 ns The ClKA delay to ALE through 74AS02 is: 25 ns (one half clock period, 20 MHz) +4.5 ns (74AS02 maximum delay) + 1.5 ns (PAL skew between low to high and high to low clock to output delay) = 31 ns 3. Minimum ALE high setup time to ClKA high (DP8422A25 needs 15 ns): 50 ns (one clock period, 20 MHz) -32.5 ns (#2) = 17.5 ns 4. Minimum address setup time to ClKA high (DP8422A-25 needs 18 ns): 50 ns (one clock period, 20 MHz) - 30 ns (# 1) = 20 ns 5. Minimum CS setup time to ClKA high (DP8422A-25 needs 13 ns): 20 ns (#4) -6 ns (74AS139 two to four decoder) = 14 ns 6. Determining tRAG (RAS access time needed by the DRAM): 200 ns (four clock periods at 20 MHz) - 50 ns (one clock period) -8 ns (PAL maximum delay low to high from ClK2 clock, clock skew) -10 ns (data setup time) -7 ns (74AS245) - 26 ns( ClK to RAS low) = 99 ns Therefore the tRAG of the DRAM must be 99 ns or less. 7. Determining !cAG (CAS access time needed by the DRAM): 200 ns -50 ns -8 ns -10 ns -7 ns -79 ns (ClK to CAS low) = 46 ns Therefore the tGAG of the DRAM must be 46 ns or less. 8. Minimum setup of DTACKO to the PAl16R8D, DESIGN # 1 ONLY, (need 8 ns): 50 ns (one clock period) -8 ns (PAL maximum delay low to high from clock, clock skew 20 MHz vs 40 MHz) -33 ns (clock to DTACKO valid from DP8422A-25) = 9 ns 9A. Minimum READY setup time to READY being sampled (11 ns is needed by the 80386) DESIGN # 1: 25 ns (one half clock period) -8 ns (maximum "D" PAL clocked output delay) = 17 ns 9B. Minimum READY setup time to READY being sampled (11 ns is needed by the 80386) DESIGN # 2: IF 74AS02 IS USED TO PRODUCE READY: 25 ns (last one half clock period of T2) + 5.5 ns [10 ns (see in note below) -4.5 ns (max 74AS02 delay)] = 30.5 ns IF 30 OUTPUT OF 74AS175 IS USED FOR READY: 25 ns (last one half clock period of T2) -10 ns (max delay of 74AS175) = 15 ns 6. Determining tRAG (RAS access time needed by the DRAM): 250 ns (four clock periods at 16 MHz) - 62.5 ns (one clock period) -8 ns (PAlmaximum delay low to high from ClK2 clock, clock skew) -1 0 ns (data setup time) - 7 ns (74AS245)-32 ns (ClK to RAS low) = 130.5 ns Therefore the tRAG of the DRAM must be 130.5 ns or less. 7. Determining tGAG (CAS access time needed by the DRAM): 250 ns -62.5 ns -8 ns -10 ns -7 ns -89 ns (ClK to CAS low) = 73.5 ns Therefore the tGAG of the DRAM must be 73.5 ns or less. COMMON 120 ns DRAMS Will MEET THIS tRAG AND tGAG PARAMETER. 8. Minimum setup of DTACKO to the PAl16R8D, DESIGN # 1 ONLY, (need 10 ns): 62.5 ns (one clock period) -8 ns (PAL maximum delay low to high from clock, clock skew 32 MHz vs 16 MHz) -41 ns (clock to DTACKO valid from DP8422A-20) = 13.5 ns 9A. Minimum READY setup time to READY being sampled (20 ns is needed by the 80386) DESIGN # 1A and # 1B: 31.25 ns (one half clock period) -8 ns (maximum "0" PAL clocked output delay) = 23.25 ns 9B. Minimum READY setup time to READY being sampled (20 ns is needed by the 80386) DESIGN #2: IF 74AS02 IS USED TO PRODUCE READY: 31.25 ns (last one half clock period of T2) + 13 ns [17.5 ns (see in note below) -4.5 ns (max 74AS02 Delay)] = 44.25 ns IF 3Q OUTPUT OF 74AS175 IS USED FOR READY: 31.25 ns (last one half clock period of T2) -10 ns (max delay of 74AS175) = 21.25 ns Note: DTACK1.5 setup to 74AS175 input, used to generate l5'i'ACR2.5 (74AS175 needs 3 ns): 62.5 ns (one clock period at 16 MHz) -45 ns [7.5 ns (ClKA max delay) + 33 ns (DP8422A-20 DTACK1.5 max delay) + 4.5 ns (74AS02 max delay)] = 17.5 ns setup to mid T2 of last access clock period. 10. Minimum NA setup time to NA being sampled, Design # 1 only (10 ns is needed by the 80386): 31 ns (one clock period at 32 MHz) -8 ns (maximum "0" PAL clocked output delay) = 23 ns VI. 80386 # 1 DESIGNS (AND # 2 DESIGN), 40 MHZ TIMING CALCULATIONS, WITH ONE WAIT STATE PER ACCESS IN ADDRESS PIPEllNED MODE, TWO WAIT STATES PER ACCESS IN NON·ADDRESS PIPEllNED MODE (DP8422A-25 USES THE 20 MHZ CLOCK) .... "'Note: Design #2 timing calculations are the same as Design#1 except for those calculations involving "CLKA", CLKA is produced by a 74AS175In Design #2 instead of a "D" speed PAL (Design #1). Therefore the timing calculations involving the minimum or maxi~ mum delay or skew of CLKA with respect to CLK2 should be recalculated substituting the 74AS175 parameters for the PAL parame- Note: DTACK 1.5 setup to 74AS175 input. used to generate DTACK2.5 (74AS175 needs 3 ns): 50 ns (one clock period of 20 MHz) -40 ns [7.5 ns (ClKA max delay) + 28 ns (DP8422-25 DTACK1.5 max delay) +4.5 ns (74AS02 max delay)] = 10 ns setup to mid T2 of last access clock period. 10. Minimum NA setup time to NA being sampled, Design # 1 only (8 ns is needed by the 80386): 25 ns (one clock period at 40 MHz) -8 ns (maximum "D" PAL clocked output delay) = 17 ns ters. 1. Maximum time to address valid (with respect to 20 MHz clock): 32 ns (maximum time to address valid) - 2 ns ("D" speed PAL minimum delay, because 20 MHz clock is from PAL with minimum delay as skew from 40 MHz CPU clock) = 30 ns 4-141 Z U1 Co) en VII. 80388 DESIGN'" 1, PAL EQUATIONS WRITTEN IN NATIONAL SEMICONDUCTOR PLANTM FORMAT DESIGN #1A UP ro 40 MHz (80386-20) PAL16R8D CLK2 82384CLK ADS CS DrACKO EXr_NA W Bl RESEr GND OE BOWE ADS1D CLKA READ READY NA ADS3D B1WE VCC B1WE:=ADS3D*ADS1D*READ*DrACKO*Bl +B1WE*CLKA*READ*RESEr BOWE:=ADS3D*ADS1D*READ*DrACKO*Bl +BOWE*CLKA*READ*RESEr ADS3D:=ADS1D*CLKA*RESEr +ADS3D*CLKA*RESEr NA:=DrACKO*ADS1D*CLKA*RESEr*w +DrACKO*ADS1D*ADS3D*BOWE*CLKA*RESEr +DrACKO*ADS1D*ADS3D*B1WE*CLKA*RESEr +Exr_NA*CLKA*RESEr +NA*CLKA*RESEr READY:=NA*ADS3D*ADS1D*DrACKO*CLKA*RESEr +READY*ADS3D*DrACKO*RESEr ADS1D:=ADS*CLKA*CS +ADS1D*NA*RESEr +ADS1D*CLKA*RESEr READ:=CS*W*ADS1D*CLKA*RESEr +READ*ADS1D*RESET +READ*CLKA*RESEr CLKA:_82384CLK DESIGN #lB UP TO 50 MHz (80386-25) PAL16R8D CLK2 82384CLK ADS CS RASO RAS2 WNO_NA RESET GND OE BOWE ADS1D CLKA READ READY NA ADS3D B1WE VCC B1WE:=ADS3D*ADS1D*READ*RAS2*NO_NA +B1WE*CLKA*READ*RESEr BOWE:=ADS3D*ADS1D*READ*RASO*NO_NA +BOWE*CLKA*READ*RESET ADS3D:=ADS1D*CLKA*RESET +ADS3D*CLKA*RESEr NA:=RASO*ADS1D*CLKA*RESEr*NO_NA*W +RASO*ADS1D*ADS3D*BOWE*CLKA*RESET +RASO*ADSlD*ADS3D*B1WE*CLKA*RESEr +RAS2*ADS1D*CLKA*RESET*NO_NA*W +RAS2*ADS1D*ADS3D*BOWE*CLKA*RESEr +RAS2*ADS1D*ADS3D*B1WE*CLKA*RESET +NA*CLKA*RESET Logic Needed for "NO_NA" Term in Design #1 B READY:=NA*ADS3D*ADS1D*RASO*CLKA*RESET*NO_NA +READY*ADS3D*RASO*RESEr*NO_NA +NA*ADS3D*ADS1D*RAS2*CLKA*RESEr*NO_NA +READY*ADS3D*RAS2*RESEr*NO_NA ADS1D:=ADS*CLKA*CS +ADS1D*NA*RESEr +ADS1D*CLKA*RESEr _~ RFIP RFIP GRANTB e-----.. . )o--c:> [ -~- NO_NA TL/F/97S0-12 READ:=CS*W*ADS1D*CLKA*RESEr +RL4~*ADS1D·RESET +READ*CLKA*RESEr CLKA:=82384CLK 4·142 ~-------------------------------------------------------------------.~ =F Key: Reading PAL Equations Written In PLAN EXAMPLE EQUATIONS: READ: = CS_RD·ADSlD·CLKA +READ·ADS1D +REAO·CLKA (II ~ This example reads: the output "READ" will transition low on the next rising "CLK2" clock edge (given that one of the following conditions are valid, a setup time before "CLK2" transitions high); 1. the input "CS_RD" is high AND the input "ADS1D" is high AND the input "CLKA" is low, OR 2. the output "READ" is low AND the input "ADS1 D" is low, OR 3. the output "READ" is low AND the input "CLKA" is high CLOCK CLK2, ~ ADDRESS MilO CLK2, CLK ~DECODERI cs~ L.!L. ADS W/R 80386 BEO-3 READY .. NA 4 J cs ROWO-9 UOLUMNO-9 Bl I CLKA CLK,DLYCLK I J II L RASO-l DTACK (or RASO,2) NEXT ADDRESS REQUEST, READY, CLOCK GENERATOR, DP8422A CONTROL, AND READ/WRITE CONTROL LOGIC QO-l0 CASO-l ALE ALE ADS3D AREQ W/R~ DP8422A MEMORY TWO 32 BIT BANKS INTERLEAVED BANKO WEO-3 RAS2-3 CAS2-3 BANKI WEO-3 ECASO-3 4 :L~I§;>, ,... ;;! ; "--;J ENABLEO-3 c--" DIR J 74F245 DATA BUSO-31 TL/F/9730-1 FIGURE 1. 80386 Design 41 1 (A and B), System Block Diagram for Address Pipelined Mode Operation at up to 50 MHz (DP8422A Uses Half Speed Clock, CLKA) 4·143 AN·S36 ALE 110386 HIGH SPEED CLOCK - = 8,0386 HALF SPEED CLOCK ::80386 ADS OUTPUT '" 'I BIWE "'1.''0..&. - , 82384CLK ADS 2 18 ADSJD 3 17 MA DRAM CHIP SELECT : - CS 4 DP8422A DTACKO :::. DTACKO 5 EXT NA 6 EXTERNAL MA's _ (FROM OTHER PERIPHERALS) 80386 WRITE OUTPUT 80386 ADDRESS BIT FOR DP8422A BANK SELECT TO DP8422A ALE INPUT W 7 -- " TO DP8422A AREO INPUT TO 80386 16 80386 PAL TO 80386 15 ADSID TO DP8422A CLK,DELCLK INPUTS TO EHABLE's OF BYTE DATA TRANSCEIVERS ! ECASO, I C> TO DP8422A ECASO, ECASI 1 ECAS2, 3 C> TO DP8422A 1 1 .j>. .j>. : 1 -I ECAS2, ECAS3 ~IDIR BIWE 1 UI • ____ • TO DIRECTION OF TRANSCEIVERS BIWE W_B13 DRAM BANK1 BYTE WRITES BIWE BE3 B1WE BIWE ~ BE2 ~ • BIWE BEl ~ BEO BOWE BE(3:0) BOWE~ DRAM BANKO BYTE WRITES BOWE~O BEO TL/F/9730-2 FIGURE 2. 80386/DP8422A Interface Control Logic for Design # 1A ~ ZI TI CLKA T2 T2 T2P L- n- n- h-h- CS ADS n ~ ALE T2 T2 ADS3D T2 T2P W- L. ---I L. ---l L. r lJl r Ln r ~ ""--- r--- L1 :-J 1.J..........J READY TIP T2P r-u n-I Lh-h- n-I Lh-J .-,---, ADS1D W TIP U1 + I RFRQ RFIP READ RAS 0,1 READ WRITE RAS 2,3 I CAS 0,1 CAS 2,3 BANK 0 Bl t t NA BANK 0 BANK 1 t + r-, + r--- + ECASOl ECAS23 - I W_BO 0 W_Bl 0 READ DIR ADDRESS DATA ADD N X I I READ ACCESS N ADDN+1 I READ N I WRITE N+1 )-( I I ADD N+2 I WRITE ACCESS N+l I I X I READ ACCESS N+2 ADD N+3 READ N+2 )0- ~ TL/F/9730-3 FIGURE 3. 80386 Design # 1 (A and B) Address Pipelined Timing 4-145 Co) Q) ~ Ion I Z cc CS ADS ALE ADS1D ADS3D READY rL. rL rL rL rL rLrr... rL rL rL rLrr... ru ~ --' --11 -11 '- --I r fL r- .r-'----, ~ L- --J r- ut U 1.1.....J ---.I -.r- W REFRESH REQUEST RFRQ REFRESH RFIP RAS 0,1 WRITE PRECHARGE READ PRECHARGE RAS 2,3 CAS 0,1 I CAS 2,3 Bl NA • • - • BANK 0 • BANK 0 • + f.--l- t ECASOI ----....I ECAS23 ----....I W_BO 0 W_Bl0 READ ----....I DIR ADDRESS DATA I I ~ T I I I WRITE I I I I I I WRITE BANK 0 I I I READ BANK D READ I -, TL/F/9730-4 FIGURE 4. 80386 Design # 1 Address Pipelined Timing 4·146 rL rL. rL rL rL rL rL rL rL ~rL. TI CLKA CS ADS L... ~ r- WI. ALE ADSID ADS3D READY :I:t~ r- L I W REFRESH REQUEST RFRQ REFRESH RFIP RAS 0,1 I RFSH I r- READ PRECHARGE RAS 2,3 r- CAS 0,1 CAS 2,3 Bl • NA • • • • • BANK 0 • L ECASOI ECAS23 W_BO 0 W_Bl0 READ DIR ADDRESS DATA lI. READ I I I I I I I I READ ACCESS DURING DRAt.! REFRESH READ J"- I I TUF/9730-5 FIGURE 5. 80386 Design # 1 Address Pipellned Timing 4·147 CLOCK CLK2, ~ Jl ROWO-9 COLUMNO-9 Bl ADDRESS 101/10 CLK2, CLK ADS W/R RASO 80386 BEO-3 RAS2 4 ~DECODERI CS.1. 80386/DP8422A INTERFACE CONTROL LOGIC READY, CLOCK GENERATOR, DP8422A CONTROL, AND READ/WRITE CONTROL LOGIC CS CLK,DLYCLK RFRO RASO-l GRANTB 000-1 RFIP ALE ALE ~VCC DP8422A AREO RAS2-3 WRITLEN WIN CAS2-3 AREO J I I CLKA l MEMORY lWO 32 BIT BANKS INTERLEAVED WE READY 6 00-10 EOOO-3 4 WRITLEN ~ > WRITE-EN EN_TRAN -! EN DIR TRANSCEIVERS 1 DATA BUS 0-31 r TL/F/9730-8 FIGURE 6. 80386 Design #2, System Block Diagram tor Non-Address Plpellned Mode Operation at up to 50 MHz (DP8422A Uses One Half Speed Clock) 4-148 RDY2 rROht DP8422A CLKA TL/F/9730-7 FIGURE 7. 80386/DP8422 Interface Control Logic for Design #2 9CS-NV II CD C') It) I Z cr: T2 T1 T2 T2 T2 T1 T2 T2 T2 T1 T2 T2 rt-rt- rl.-rt-rt-rt- rl.-rt- rl.-rl.-rt- r--u n... CS CLKA ADS h ALE ~ Wt L- .....J I RDY3 ~ h + L...l READY r-1 LJ 11 11 ,r--- I rLJ I--- I-- I r- RDYLS WRITE_EN I... I... DTACKLS ALE1D r- ~ r LI1 AREQ L-.l. I - - L-.l. I ...J RFRQ RFIP RAS (1:0) REAO '\ I BANK 0 CAS (1:0) READ '\ BANK 0 I RAS (3:2) WRITE CAS (3:2) "\ B(I:0) BANK 1 I '\ ECAS (3:0) EN_TRAN I--- ADDRESS DATA r--ADD I I I I READ BANK 0 READ - 1 I ADO ADD WRITE 1 WRITE BANK 1 I 1 I I READ BANK 0 READ ? 1 I TLiF /9730-8 FIGURE 8. 80386 Design # 2 Non-Address Plpelined Timing 4-150 r--------------------------------------------------------------------, T2 T1 CLKA f,[ ru ru T2 T2 T2 Tl T2 T2 r L r L IL- r L r L r L T2 T2 ru w Tl G) rLrL CS ADS ALE ~~ L- --I --11 ~ AREQ DTACKL5 L-~ ..J r- 1""1 ~ IL..J --I II r-1 ALEID READY .. LI RDYL5 RDY3 L.. r r- Ut 1-1 1-1 J WRITE-EN REFRE H REQUEST RrRQ ~~H RrlP RAS (1:0) CAS (1:0) ~ WRITE '\ I READ '\ PRECHARGE BANKO BANK 0 ~ rr- RAS (3:2) CAS (3:2) B(I:0) ECAS (3:0) EN_TRAN ~h ADDRESS DATA JI. JI. ~ r I WRITE l I I WRITE ACCESS BANK 0 I I I I I READ I I READ ACCESS BANK 0 TL/F /9730-9 FIGURE 9. 80386 Design # 2 Non-Address Plpellned Timing 4-151 ~ :iF UI ~ .." Z• cC CLKA rL f,[ rL.. rL rL r-LrL rL rL rL rL r--tr CS ADS L.. .......J ALE r- Ln AREQ L- r- I r- --r~ RDY3 IU ALEID READY r ~~ DTACKL5 RDYL5 L- -L.l~ L....r h • • • • • WR1TE-EN REFRESH REQUEST RfRO RflP I REFRESH I RAS (1:0) , I CAS (1:0) W I I , RAS (3:2) , PRECHARGE READ ,-- BANK 0 r- I CAS (3:2) 8(1 :0) ECAS (3:0) EN_TRAN ADDRESS DATA I READ I I I I I I I I I I I I I READ ACCESS DURING DRAW REfRESH READ I -, I TL/F/9730-10 FIGURE 10.80386 Design #2 Non-Address Plpellned Timing 4·152 2214Hz - r - -I- 21 -I1914Hz -I- 20 2114Hz 2014Hz 1814Hz -r- 1714Hz -I- 82384 1614Hz "elK" 1514Hz OUTPUT 1414Hz FREQUENCY 1314Hz -r-r- -I-I1214Hz -I1114Hz -I1014Hz -I-I-I7104Hz -I9104Hz 80no DRAMo 21 20 100no DRAMo 17.7 80no DRAMo 100no DRAMs -AI8ume- 17.7 120ns DRAMs 15 120ns DRAMs 15 150no DRAMs 12 A.200 ns DRAMs "tRAc" have 100 ns tcAC 8.150 ns DRAMs "tRAC" have 75 ns lCAC C.120 ns DRAMs "tRAC" have 60 ns tcAC 150no DRAMs D.100 ns DRAMs "tRAC" have 50 ns tcAC E. 80 ns DRAMs "tRAC" have 40 ns tCAC 12 200ns DRAMs 200ns DRAMs DESIGN #1 ONE WAIT STATE DURING SEQUENTIAL ADDRESS PIPELINED ACCESSES DESIGN #2 TWO WAIT STATES DURING SEQUENTIAL NON-ADDRESS PIPELINED ACCESSES 8104Hz 6MHz TLlF/9730-11 FIGURE 11.80386 Design # 1 and # 2, DRAM Speed Verses Processor Speed (The Processor Speed is Referencing the 82384 "ClK" Output, The DRAM Speed is Referencing the RAS Access Time "tRAC" of the DRAM) 4·153 .... ~ r-----------------------------------------------------------------------~ ~ z ~ ~~' cso .... NA .... ..JiL ... WAIl AT""," DELa.K ~3.1l1 ~ ... ... mfJd>S «,0<1) «,0<1) CA$(! II) I ECAS / I IREOH ENDACC DOACC I I I RFRO RFIP 0(10:0) RAS(1:0) '\ ~ \ 001 \. I I \.\. , "~':l 001 I '\ I I RAS (3:2) \. CASG(3:0) I '\ ~ DATA READ ACCESS BANK 0 -- ~ r-\. ..... ~ r- BURST READ ACCESS BANK 1 ~ BURST READ ----.. TL/F/l0394-3 ~09-N" II AN-602 Design # 1 Timing (Continued) OW2 CLK B2 BWI BW2 IDLE IDLE fL- fL- r L fL- fL- r L ADDRESS rL r-L rL rLr-L rL r L rt- ILWI W2 W3 W4 VAlID IREO AREOI I r-1 ADS, AREO IBREO I L L ---l IBACK DTACK2 IRDYI ~ COllNC, IRDY ~I IRDY3 ECASI ECAS I . I II -----. / I . II JI) 11 I 11 / ENDACC RFIP o(10:0) ~ .....rh I OOACC RFRO I JI) / IREOH , \ \ 001 \ \ 002 \ I \ REFRESH REOUEST l I 003 I ~ REFRESH 004 RAS(I:0} \. , RAS(3:2} PRECHARGE r-\ CASG(3:0} DATA .- -muD I-.. ~ r-\ - "'VALiii I-.. ~ READ BURST ACCESS BANK 1 USING COliNC - - \. I J\. --.J I -vAriii ~ READ ACCESS DURING REFRESH ,I TLlF/10394-4 Design ClK ADDRESS *' 1 Timing (Continued) n-n.... r1.... rL. n-r1....rL rL.. n-r-t- ~ n-r-L rL rL W4 W5 W8 W12 W13 Bl OWl VAUD IREO AREOI ADS, AREO IBREO I IBACK DTACK2 II IRDYI I I COLlNC, IROY ~I IRDY3 r-- II ECASI L" ECAS II> I Irl IREOH I 1 lrL 7 ENDACC DOACC RFRO RF1P ~ \ REFRESH , 1 [I 0(10:0) RAS(I:0) 1 RAS(3:2) 1 PRECHARGE \ \ 001 ~ .. 002 , CASG(3:0) ,-, ..... ~ DATA r-- - r--\. ..... ~ ~ READ BURST ACCESS DURING REFRESH TL/F/10394-5 ~09-NV II AN·602 Design # 2 Timing TI ClK WI r-L- ~ h- IREO W3 W4 TI WI W2 W3 W4 W5 rL ~ ~ h- rL.. rL.. ~ ~ rL.. rL r-Lr--L IJ J AREOI I .-- AREO IBREO I I IBACK I I OTACK2 IROY1 L...- ~ IROY ~I t'1 I I ~r--"~ II IRDY3 I'--~ ECASI ECAS !I I IREOH I \ OOACC J RFRO 1\ RFIP RAS(I:O) m....J '\ \ ~ \ --rOOI '\ II U \ RAS(3:2) CASG(3:0) / / II I ENOACC 0(10:0) ~ JI) "- \ 1"-... Y DOl '" I 002 \ I TL/F/l0394-9 Design # 2 Timing (Continued) --L n- rL rL rL r-L rL rL r--L r-L rL. rL r-LI L~ BWI ClK IREO W5 AREOI I W6 I AREO IBREO ---1 L ......J IBACK DTACK2 ~I IRDYI L-~ IRDY iJ ,. IL- IRDY3 ECASI ill / ECAS DOACC RrRO RrlP 0(10:0) / I II I \ IREOH ENDACC ill 'I I I I \ \ II \ \ L RErR ~H REOUE T ~ 1"-X 003 it JI. 002 ~ RErRESH n J[004 RAS(I:0) RAS(3:2) CASG(3:0) J r\_ L-. _ _ LJ " I " " TL/F/10394-10 C;09-NV II AN·602 Design #2 Timing (Continued) W6 CLK W8 W7 W9 W10 Wll W12 W13 81 L-- ~ ~ r L r L ~ rt- r L ~ fREQ BWI I f f f f rwr L ~rur L r L I AREQI AREQ I fBREQ L fBACK I OTACK2 I fROYl fRDY ~I r- h L.........I fROY3 ECASI ECAS fREQH ENOACC DDACC RFRQ RFlP I Q(10:0) I RAS(I:0) I RAS(3:2) I CASG(3:0) '\ lI. 002 1001 '\'\ '\ I TUF/10394-11 » z . High Performance 2900 System Block Diagram Using 2 DRAM Banks, This System Could Be of Stili Higher Performance by Extending It to 4 DRAM Banks DRA~~l1 (TO PAL) 74AS138 DECODER I . RASO.1 2 00-10 11 01 WIN '-I DP8422A DElClK. ClK ClK L...C~ IREO.IBREO 29000 CONTROL LOGIC IBACK 4 COllNC DTACK R!W AREO B1 CASO-3 ~ BOECAS ~ RESET---+ ....... DO WE WE ~ BANK 1 OF 32 BITS OF DRAM 11 RFRO -AREO ~ I- 2 RAS2 3 T ECASD-3 IRDY BANK 0 OF 32 BITS OF DRA~ BOCASO-3 29000 N ~ CS RjW o B1 = Addr... bR 11 } Assuming RO-10=Address bits 14-24 4~-b" CO-10=Addres. bit. 2-10,12, 13 DRA~S ADDRESS BUS !!! en f.r '¥""~r SELECT - B1 ECAS 4 ~ BOECAS B1 ECAS i-- 4 r--~ CASO-3D- 32 - ~ 74F244 32 7 INSTRUCTION BUS 0-31 2-1 MUXES BUFFERS (MAY NOT BE NEEDED) TLlF/10394-8 4·181 AN-602 29000 Mode 1,2 Bank System High Performance (Start Access in Bank 0) ClOCK 40 ADDRESS ADS, AREQ IREQ IBREQ 80 120 160 200 240 320 360 400 440 480 520 560 600 640 680 7 VALID ~ h V .,-- r ~ ~~ IROY iiASQ-3 BANKOECAS 280 VALID .r-f\ l~ ~ \.........: ~ ~ ~ '- 1'\ IrIr- 1'\ 'r- 79 r---\ 11'\ 1'\ 11'\ BANKO CASQ-3 BANKI ECAS 1'\ 1'\ 132 DATA 182 1'\ r-- r--f\ 1 0 1 0 295 ~~ 1'\ 11'\ r-- COLlNC= IROY·BANKI 11'\ 11'\ 1'\ BANKI CASO-3 11'\ Stay low 1 0 1 0 TlIF/l0394-6 !ex> I\) 2900 Mode 1 2 Bank System High Performance (Start Access in Bank 1) (Interleaving Ability Not as Good) CLOCK 40 ADS, AREQ IREQ IBREQ 80 120 COLINC = IROY·BANKI DATA 280 320 360 400 440 480 ~ 520 560 600 640 681 Ir-- "'\ h4\ '----.: r- BANKO CASO-3 BANK I CX-SO-3 240 h iiASO-3 BANKI ECAS 200 VALID IROY BANKOECAS 160 VALID ADDRESS r ~~ r ~ --J !\----:r - '---.,;tt 79 r"'\ r"'\ 11'\ 132 I--- ' - -h r--- ,....,. 182- lr\ IT"\ iT"\ r---\ r"'\ T"\ 132 r-- r"'\ r"'\ 0 1 r--- r- 11'\ 0 1 TlIF/l0394-7 » National Semiconductor Application Note 546 Webster (Rusty) Meier, Jr. and Joe Tate Interfacing the DP8420A/21A/22A to the z ~ U1 Z280/Z80000/Z8000 Microprocessor I INTRODUCTION This application note describes how to interface the Z280 microprocessor to the DP8422A DRAM controller (also applicable to DP8420A/21 A). It is assumed that the reader is already familiar with Z280 and the DP8422A modes of operation. The interface to the Z80000 and Z8000 is similar to the interface described in this application note. n DESCRIPTION OF DESIGN, ALLOWING OPERATION AT 10 MHz (AND ABOVE) WITH 1 WAIT STATE IN NORMAL ACCESSES AND 1 WAIT STATE DURING BURST ACCESSES The block diagram of this design is shown driving two banks of DRAM, each bank being 16 bits in width, giving a maximum memory capacity of up to 16 Mbytes (using 4 M-bit X 1 DRAMs). By choosing a different RAS and CAS configuration mode (see programming mode bits section of DP8422A data sheet) this application can support 4 banks of DRAM, giving a memory capacity of up to 32 Mbytes (using 4 M-bit X 1 DRAMs). The memory banks are interleaved on every four word (16bit word) boundry. This means that the address bit (A3) is tied to the bank select input of the DP8422A (B1). Address bits A2,1 are tied to the most significant row and column address inputs (R9,C9 for 1 Mbit DRAMs) to support burst accesses using static column mode DRAMs. Since this application assumes the use of static column DRAMs the column address strobe (CAS) is left low throughout the entire burst access. If the user desires to use nibble mode or page mode DRAMs the CAS outputs must be toggled, the ECAS inputs the DP8422A can be used for this purpose (OS of the Z280 could be "OR"ed with the current ECAS inputs). If nibble mode DRAMs are used the COLINC input of the DP8422A need not be driven. Address bit AO is used to produce the two byte select data strobes along with the by1e/word signal (B/W). These byte selects (By1e 0 ECAS and By1e 1 ECAS) are used in byte reads and writes as well as selects for the transceivers. If the majority of accesses made by the Z280 are sequential, the Z280 can be doing burst accesses most of the time. Each burst of four words can alternate memory banks, allowing one memory bank to be precharging (RAS precharge) while the other bank is being accessed (Bank select, B 1, tied to address A3). This is a higher performance memory system then a non-interleaved memory system (bank select on the higher address bits). Each separate memory access to the same memory bank may require extra wait states to be inserted into the CPU access cycles to allow for the RAS precharge time, if two periods or more of RAS precharge were programmed. This application allows 1 or more wait states to be inserted in normal accesses and 1 or more wait states to be inserted during burst accesses of the Z280. The number of wait states can be adjusted through the WAIT IN input of the DP8422A. The logic shown in this application note forms a complete Z280 memory sub-system, no other logic is needed. This sub-system automatically takes care of: A. arbitration between Port A, Port B, and refreshing the DRAM; B. the insertion of wait states to the processor (Port A and Port B) when needed (i.e., if RAS precharge is needed, refresh is happening during a memory access, the other Port is currently doing an access ... etc); C. performing byte writes and reads to the 16-bit words in memory; D. normal and burst access operations. The external wait logic (U1, U2, U3, U4; see Figure 1) is needed to support burst accesses of the Z280. During burst accesses the Z280 WAIT input is sampled every falling clock edge. What is worse is that the WAIT input needs one half clock period setup time and the OS signal (used to toggle ECASO-3 and thereby toggle the DP8422A WAIT output) takes close to one half of a clock period to transition high. This leaves no time for the DP8422A WAIT output to transition between states. The external flip-flop is used to provide extra fast response time for normal access wait states and to toggle when doing a burst mode access. If the user is not going to do burst accesses the WAIT output can be tied directly to the WAIT input of the Z280 (U 1, U2, U3, U4 would not be needed). Also all this logic could easily be put into a PAL® if desired. By using the "output control" pins of some external latches (74ALS373's), this application can easily be used in a dual access application. The addresses could be TRI-STATE® through these latches, the write input (WIN), lock input (LOCK), and ECASO-3 inputs must also be able to be TRISTATE (a 74AS244 could be used for this purpose). By mUltiplexing the above inputs (through the use of the above parts and similar parts for Port B) the DP8422A can be used in a dual access application. If this design is used in a dual access application the tRAG and tGAG (required RAS and CAS access time required by the DRAM) will have to be recalculated since the time to RAS and CAS is longer for the dual access application (see TIMING section of this application note). 4-183 I .co. en III Z280 DESIGN, 10 MHz WITH 1 WAIT STATE DURING NORMAL ACCESSES AND 1 WAIT STATE DURING BURST ACCESSES, PROGRAMMING MODE BITS Programming Bits RO = 0 R1 = 1 R2 = 0 R3 = 1 R4 = 0 R5 = 0 R6 = 0 R7 = 1 R8 = 1 R9 = X CO= X C1 = X C2 = X C3 =' X C4 = 0 C5 = 0 Description 2B. Minimum address hold time to ALE low (DP8422A-20 needs 10 ns, #305): RAS low two clocks, RAS precharge of two clocks, this setup will only guarantee 93.5 ns RAS precharge (at 10 MHz) from refresh RAS high to access RAS low. If more RAS precharge is desired the user should program three periods of RAS precharge. DTACK one half is chosen. DTACK low first rising ClK edge after access RAS is low. No WAIT states during burst accesses 20 ns (address hold from AS high, #22 of Z280 data sheet) + 1 ns (74ALS04B min delay) = 21 ns 2C. Minimum address setup to CLOCK high (DP8422A-20 needs bank address setup to CLOCK of 20 ns, #303): 3. 4. If WAITIN = 0, add one clock to DTACK. WAITIN may be tied high or low in this application depending upon the number of wait states the user desires to insert into the access. Select DTACK Non-interleaved Mode Select based upon the input "DELClK" frequency. Example: if the input clock frequency is 10 MHz then choose CO,1,2 = 1,0,1 (divide by five, this will give a frequency of 2 MHz). C7 = 1 C8 = 1 C9 = 1 Column address setup time of 0 ns Row address hold time of 15 ns Delay ~ during write accesses to one clock after RAS transitions low latches latch on ALE input low Access mode 0 CASn not extended beyond RASn Determining tRAC during a normal access (RAS access time needed by the DRAM): 250 ns (two and one half clock periods to do the access) - 32 ns (ClK to RAS low max, DP8422A-20 #307) - 30 ns (Z280 data setup time, #9) - 10 ns (74AlS245A max delay) = 178 ns Determining tCAC during a normal access (CAS access time) and column address access time needed by the DRAM: 250 ns - 89 ns (ClK to CAS low on DP8422A-20, #308a) - 30 ns - 10 ns = 121 ns Therefore the tCAC of the DRAM must be 1.21 ns or less. 6. Determining the column address access time needed during a static column mode burst access: 20 ns (two clocks to do the access, Ex. mid T3 to mid TBW to mid T4) - 35 ns (DS high, Z280 parameter #8) - 43 ns (COLINC asserted to address outputs of DP8420A-20 incremented, #27) - 30 ns (Z280 data setup time, # 9) - 10 ns (74AlS245A max delay) = 82 ns Therefore the column address access time of the DRAM must be 82 ns or less. (One can see that if zero wait states would have been programmed the column address access time would have been less then 0 ns (82 - 100 (one clock))). 7. Maximum time to DTACK one half low (74AlS374 0 type flip-flop needs 10 ns setup to ClK): 100 ns (One clock, mid T2 in mid TW) - 33 ns (DTACK one half low from ClK high on DP8422A-20, # 18) - 12 ns (max delay on 74AlS02 = 55 ns RAS groups selected by "B 1". This mode allows two RAS outputs to go low during an access, and allows byte writing in 16- or 32-bit words. 100 ns (one clock period) - 20 ns (max clock to address valid, Z280 data sheet #2) = 80 ns Minimum CS setup time to clock high (DP8422A-20 needs 14 ns, #300): 80 ns (#2C above) - 22 ns (max 74AlS138 decoder) = 58 ns Therefore the tRAC of the DRAM must be 178 ns or less. (One can see that if zero wait states would have been programmed the tRAC would have been 84 ns (using DP8422A-25, has faster ClK to RAS low of 26 ns) 184-100 (one clock». 5. C6 = 1 BO = 0 B1 = 0 ECASO = 0 2A. Minimum address setup time to ALE low (DP8422A-20 needs 3 ns, #306): 25 ns (address setup to AS high, #20 Z280 data sheet) + 1 ns (74AlS04B min delay) = 26 ns o 7" Program with low voltage level 1 = Program with high voltage level X = Program with either high or low voltage level (don't care condition) IV Z280 TIMING CALCULATIONS FOR DESIGN AT 10 MHz WITH 1 WAIT STATE DURING NORMAL ACCESSES AND 1 WAIT STATE DURING BURST ACCESSES 8. Minimum WAIT setup time to ClK low (Z280 WAIT input needs 50 ns, #14): 100 ns (one clock period) - 16 ns (74AlS374 max delay) - 14 ns (74AlS08 max delay) = 70 ns 1. Minimum ALE high setup time to CLOCK high if using the on-Chip latches and more then one RAS bank (OP8422A20 needs 29 ns, #301b): 100 ilS (one ciock period) - 20 ns (AS valid maximum delay, #3 of Z280 data sheet) - 11 ns (74AlS04B max delay) = 69 ns 9. Minimum RAS precharge (DP8422A programmed with 2 clock periods of RAS precharge): Since the AREO input of the OP8422A will go high from OS and IE both being high the AREO high setup to clock rising edge (OP8422A parameter #29b, 19 ns) parameter is violated. This means that the rising clock edge following AREQ high mayor may not be counted. 4-184 Therefore, the user should guarantee that the DRAM he is using needs a RAS precharge time of 93.5 ns or less. If more RAS precharge time is needed the user should program the DP8422A with 3 periods of RAS precharge (RO, R1) during programming. Since that first rising clock edge could be counted, and would give less RAS precharge time, we must assume this condition in the calculation of the minimum RAS precharge. Therefore: 200 ns (2 clock periods) - 50 ns (half clock period before both iE and OS transition high) - 35 ns (iE and OS high, Z280 parameters #8 and #19) - 5.5 ns (74AS08 max delay) - 16 ns (DP8422A RAS high to RAS low difference parameter #50) = 93.5 ns Note: Calculations can be performed for different frequencies and/or different combinations of wait states by 5ubstatuting the appropriate values into the above equations. .1 n A16-23 II A16llAI7 vI R CO- ~ADlt AS 'V OS JL I B/W • (Bmo) rCASO, 3 LATCHED AO ~E~ORY QO-8 CASO - 1 (BmO) CAS2. 3 BYTEI WIN WAIT 11/2 Vce ~TACKI/21 tOISRfSHtRFsRT WAIT's from other 3"'" U4 system peripherals U3 1 DATA 0-15 :1 r-R/W 2 BANKS 1lP842OA/21A/22A ~(Bml)ECAS2,3 R/W RASO.I (BANKO) RAS2. 3 BANK I WE AREa IE Z280 ~ CS Bl ALE ClK DElClK COLINC ~" ClK 74AlS138 DECODER 'iE...,§4 eLK 'BmOECAS or Bm I ECAS EN DIR 74AlS245 DATA 0-15 TL/F/9740-1 OE to the DRAMs and EN to the transceivers FIGURE 1. 10 MHz Z280 Design (Z-bus Interface), 1 Walt State In Normal Accesses, 1 Wait State in Burst Accesses 'The user may want to gate CS ("OR" Gate) with the signals that produce TLiF/9740-2 FIGURE 2. Z280 Access Cycles and Refresh (1 Wait State during Normal Access Cycles) 4-185 ..,. CD It) I Z ex> lRAso : I I :~ \ • \ I \ • / y--- I V- \ r I I lCASo T"" \ I x::: : I / \ I IRAS 1 ; - \ / I I ICAS 1 ;- o /DTACK (fRDY) \ :/ I ::::x ROW X !! COL \ ! : X :/ ROW !! X \ COL ! :/ X ROW !! X \ Cal ! '.{ TUF/10558-2 FIGURE 2. Timing Diagram for Interleave Access between Bank 0 and Bank 1 I' (CLK)H3 BANK I I a ACCESS I I I I 'I' I I I I I I Hd I I I I L 'I' REFRESH" I I I I I I I j I I I I I I I I I j I I a ACCESS I I I I I I I I I I I I I I I I I I '/ I I I I I I I I ISTRB PENDING BANK I I '\ I I '\ IRFRO : ·· ~ :-· ··· ·· · /RAS : · I I lCAS o ~ I I I I \ I . I '\ '/ '\ I I I \ I ',/ I I I I I ~ \ I '\ I \ I fp,ADS • (f EO) I I I I I ICS : U> :i....,..r~.,,) I ADDR !CJI I I '\ I I I PRECHARGE I I I I I I I I I './ I I I I I I I I I IDTACK I (/ROY) • X ROW I ... . COL ... I REFRESH ROW .... I I J. '\ :/ -""- I IRFIP : ! J. I J. COL ROW I J. I I . I X ROW I · \. I '\ \; I . I I 0 TL/F/10558-3 "During _ aD IRAS's will go low and high altha same time if All IRAS Refresh Mode is selected. FIGURE 3. nming Diagram for Refresh after an Access - - - - - - - -- - ---------------------- ~t9-NY II Section 5 Microprocessor Application for the NS32CG821 II Section 5 Contents AN-576 Interfacing the NS32CG821 to the NS32CG16 ..... .... ...... ...............•... 5·2 5-3 National Semiconductor Application Note 576 Chris Koehle Rich Levin Interfacing the NS32CG821 to the NS32CG 16 INTRODUCTION This application note explains how to interface the NS32CG821 to the NS32CG16 microprocessor. It is assumed that the reader is familiar with the NS32CG16 access cycles and operation of the NS32CG821. The N32CG821 will also take complete care of the DRAM's refresh needs. There is an internal 15 microsecond timer, and a refresh address counter. Refresh access arbitration will be controlled by an internal state machine. It will allow current cycles to complete before starting the refresh cycle. If a refresh cycle is in progress the NS32CG16 will be held off completing the access by asserting the CWAIT signal to the NS32CG16. During programming of the chip, it is recommended that the user gate ML (Mode Load) and (TSO) (Timing State Output) for the connection onto the ML pin of the NS32CG821. This is to ensure that the chip will be programmed while a valid access address is present. Timing parameters are referenced to the numbers shown in the NS32CG821 data sheet, and are included in each equation in italics to indicate the target specifications that need to be satisfied. Times that begin with a "$" refer to the NS32CG821 data sheet unless otherwise stated times use "NS32CG821-20" part's parameters with heavy loading; these times are generally worse than the "NS32CG821-25" part. Times that begin with a "#" refer to the NS32CG16 data sheet. Equations are provided so that the user can calculate timing based on their frequency and application. DESIGN DESCRIPTION This design is a simple circuit to interface the NS32CG821 to the NS32CG16 and up to 8 Mbytes of DRAM. An access cycle begins when the NS32CG16 asserts the ADS signal and places a valid address on the bus. The ADS places a pair of 74F373 fall-through latches in fall-through mode and on the negating edge of ADS latches the address to guarantee that the address is valid throughout the entire access. The ADS signal is inverted to produce the signal ALE to the NS32CG821. On the next rising clock edge, after the ALE signal is asserted, the NS32CG821 will assert RAS. After guaranteeing the row address hold time, tRAH, the NS32CG821 will place the column address on the DRAM address bus, guarantee the column address setup time and assert ~. During read cycles, the DRAM will place valid data on the bus after the DRAM, tcAC, timing has been met. During write cycles, ~ will be delayed until after T3re, to ensure that the CPU's write data is valid before CAS is asserted. NS32CG 16-NS32CG821 Connection Diagram ClK ~~----------------------~~ DElClK TSO~------------------------------------------~ TSO Ym~------------------------------------------~ WIN 00-9 RASO-3 ..._ .... CASo-3 cs,M[ NS32CG16 RO-9 CO-9 BO,Bl AO WE ECAS1,3 DRAM ARRAY ECASO, 2 (up to 8MB) NS32CG821 >:-::..!----------+iAlE data bus TL/F/10130-1 'Standard components In any NS32CG16 design. II 5-3 Timing parameter to guarantee ftll$ Precharge with 2 Clock Precharge DESIGN TIMING PARAMETERS Timing diagrams are supplied further on in this document. Clock Period $300: = Tep10 = 100 ns $29b: 10 MHz @ = T1 - (CTTl to address valid + = T4 - CITl to = Tep - 1= 88 ns @ 10 MHz = Tep - #tAHv - tSpal = 100 ns - 40 ns - 15 ns 45 ns = 66 ns - 30 ns - 1= $301a: 21 ns CWAIT: 15 ns 1 15 MHz @ = 66 ns -10 ns 1= 56 ns @ 15 MHz 1 10 MHz @ cs 16 ns Min @ NS32CG821-20, 15 ns Min @ NS32CG821-25 = T1 - Inverter Max - CITl to ADS 1= = T ep - tplh - #tADSa = 100 ns - 5 ns - 35 ns 60 ns 1= = 66ns - 5ns - 26ns 1= $302: 35 ns CWAIT: 1 15 MHz @ ALE Pulse Width 18 ns Min 13 ns Min @ @ 66 ns @ 1 10 MHz 15 MHz + 15 ns + 22 ns) 1 Hold, after T3re #tCWh, 5 ns Min @ 10 MHz & 15 MHz for NS32CG16 = T3re to WAIT Negated = $17 Min NS32CG821-20, NS32CG821-25 @ 119 ns = 133 ns - (30 ns 1 10 MHz @ Setup for Wait States, before T3re #tCWs, 20 ns Min @ 10 MHz & 15 MHz for NS32CG 16 = T1 + T2 - (Time in T1 until Asserted + CS to WAIT Asserted) = 2Tep - (#TAHv + tSpal + $311) = 200 ns - (40 ns + 15 ns + 26 ns) ALE Setup to ClK High 1= fSO Inactive #TSOia = 100 ns -12 ns B·PAl de· lay) 1= fSO negated Setup to ClK High with > 1 Period of Precharge 19 ns Min @ NS32CG821-20, 15 ns Min @ NS32CG821-25 = Tep15 = 66 ns @ 15 MHz CS Asserted to ClK High (only A20-A23 are used for decode) 14 ns Min @ NS32CG821-20, 13 ns Min @ NS32CG821-25 = 7 ns @ NS32CG821-20 = 7 ns @ NS32CG821-25 = #tADSw = 30 ns @ 10 MHz = 25 ns CWAIT: 15 MHz @ $303 & $304: Address Setup to ClK 20 ns Min 18 ns Min @ @ NS32CG821-20, NS32CG821-25 = T3 - ClK to WAIT Negated = T1 - CITl to Address - F373 In to Out = = Tep - tAHv - tphl = 100 ns - 39 ns = 100 ns - 40 ns - 6 ns 1= 54 ns 10 MHz @ 1= 1 1= 30 ns 15 MHz @ 1= 1 RAS (to guarantee CAS is delayed) @ @ + tWRa = 100 ns - (100 ns 1= -20 ns @ -15 ns @ 20 ns) 10 MHzl = 66 ns - (66 ns 1= + + @ 10 MHz 1NS32CG821-20 Part 27 ns @ 15 MHz 1NS32CG821-20 Part Since systems and DRAM times vary, the user is encour· aged to change the following equations to match their sys· tem requirements. Timing has been supplied for systems with 0 or 1 wait states. The times assume worst case load. As such, the time will improve with lower circuit loads. NS32CG821-20 & NS32CG821-25 = T1 - (time until WR active) = Tep - (Tep 61 ns DRAM SPECIFIC TIMING WHEN USING THE NS32CG16 @ 10 MHz WIN Setup to ClK High that starts the access -21 ns Min -16 ns Min Tep - $17 Max = 66 ns - 39 ns = 66 ns - 30 ns - 6 ns $310: Setup for Termination of Access #tCWs, 20 ns Min @ 10 MHz & 15 MHz for NS32CG16 15 ns) 15 MHz 1 5-4 r--------------------------------------------------------------------.~ Zero Wait States Analysis for a 10 MHz NS32CG16 tRAC = T2 + T3 - ClK to RAS Delay - Data Setup - DRAM SPECIFIC TIMING WHEN USING THE NS32CG16 @ 15MHz Transceiver The input DElClK controls the internal delay line and should be a multiple of 2 MHz. Since DElClK is 15 MHz (when directly connected to CTTl) and is not a multiple of 2 MHz, tRAH and tASC will vary from the programmed times according to the equations listed below. In addition, please note the following pertaining to the timing equations: = 2Tep - $307 - tphl - #tDls = 200 ns - 32 ns - 7 ns - 18 ns 1= 143 ns @ I 10 MHz NS32CG821·20 Part = T2 + T3 - ClK to Column Address Valid - Transceiver Delay - Data Setup 1. Times for tRAH and tASC at light loads are specified 2 ns longer than for normal-heavy loads. (See data sheet specifications.) = 2Tep - $316act - tphl - #tDls = 200 ns - 87 ns - 7 ns - 18 ns 1= 88 ns tCAC 10 MHz @ INS32CG821·20 Part 2. Light load is defined as 4 banks of four x 4 DRAMs 3. When using normal-heavy loads at 15 MHz a DELCLK divisor of 8 is used and when using light loads at 15 MHz a DElClK divisor of 7 is used. = T2 + T3 - ClK to CAS - Transceiver Delay - Data Setup = 2Tep - $308act - tphl - #tDls = 200 ns - 89 ns - 7 ns - 18 ns 1= 86 ns tRAHae\ 10 MHz 1NS32CG821·20 Part @ = 30 * [(DELCLK divisor * 2 MHz/DELClK freq) - 1] ns + 15 ns ( + 2 ns for lightload only) = 30' [(8 * 2 MHz/15 MHz) - l]ns + 15 ns One Wait State Analysis for a 10 MHz NS32CG16 tRAC = T2 + Tw + T3 - ClK to RAS Transceiver Delay - Data Setup = 17 ns = 3Tep - $307 - tphl - #tDls = SOO ns - 32 ns - 7 ns - 18 ns = SO' [(7' 2 MHz/15 MHz) - l]ns + 2ns 1= 243 ns tAA @ I = 15 ns 10 MHz NS32CG821·20 Part tASCaet = STep - $S16act - tphl - #tDls = 300 ns - 87 ns - 7 ns - 18 ns !cAC @ I = 1 ns @ 15 MHz I Light Loads PARAMETER ADJUSTMENTS FOR 15 MHz DELCLK DUE TO CHANGED tRAH and tAse ClK High to CAS = Data Sheet Spec + $308act (Actual tRAH - Spec tRAH) + (Actual tASC Spec tASel = 79 ns + (17 ns - 15 ns) + (1 ns - 0 ns) RAS Precharge Time < 100 ns) = T 4 + Tl - CTTl to TSO inactive + [(ClK high to RAS asserted) - (TSO negated to RAS negated)] @ RAS low During Refresh tRAS = 82 ns @ 15 MHz + $53 + 4 ns I = 89 ns 10 MHz for NS32CG16 + (17 ns - 15 ns) = 92 ns @ 15 MHz (for both zero and one wait state) + (1 ns - 0 ns) NS32CG821·20 Part Heavy Load = 72 ns + (15 ns - 17 ns) = 69 ns @ 15 MHz = 2Tep - $55 =200ns-5ns @ NS32CG821·25 Part Heavy Load = Programmed Clocks - [(ClK High to Refresh RAS asserted) - (ClK High to Refresh RAS negated)) 1= 195 ns +2 ns see DRAM data sheet (usually 1= 192 ns 15 MHz = 15' [(7 • 2 MHz/15 MHz) ns - 15 ns 10 MHz NS32CG821·20 Part = 2Tep - #trsOia = 200 ns - 12 ns @ Normal-Heavy Loads RAS Precharge Parameter (for both zero and one wait state) tRP 15 MHz = 15' [DELCLK Divisor' 2 MHz/DELCLK Freq] ns - 15 ns ( + 2 ns for light load only) = 1 ns 10 MHz NS32CG821·20 Part = STep - $308act - tphl - #tDls = SOO ns - 89 ns - 7 ns - 18 ns @ @ + 15 ns = 15' [8 • 2 MHz/15 MHz)ns - 15 ns = T2 + Tw + T3 - ClKto~Transceiver Delay - Data Setup 1= 186 ns 15 MHz Light Loads = T2 + Tw + TS - ClK to ColumnAddress Valid - Transceiver Delay - Data Setup 1= 188 ns @ Normal-Heavy loads + (1 ns - 2 ns) NS32CG821·25 Part Light Load I 10 MHz for NS32CG16 = 81 ns + (15ns -17ns) = 78 ns @ 15 MHz Light Load 5·5 + (1 ns - 2ns) NS32CG821·20 Part Z ~ $316act ONE WAIT STATE ANALYSIS FOR A 15 MHz NS32CG18 ClK High to Column Address Valid = Data sheet Spec + (Actual tRAH Specified tRAH) = 75 ns + (17 ns - 15 ns) = 77 ns @ 15 MHz tRAC = 3Tep - $307 - !Phi - #tOl s = 200 ns - 26 ns - 7 ns - 15 ns NS32CG821-20 Part = 152 ns Normal-Heavy load = 87 ns + (17 ns - 15 ns) = 89 ns @ 15 MHz + = 200 ns - 22 ns - 7 ns - 15 ns NS32CG821-20 Part = 158 ns + Tw + T3 - ClK to Column Address Valid - Transceiver Delay - Data Setup = T2 NS32CG821-25 Part = 78 ns + (15 ns - 17 ns) = 3Tep - $316act - tphl - #tOl s = 200 ns - 77 ns - 7 ns - 15 ns = 78 ns @ 15 MHz = 101 ns NS32CG821-2Q Part Light Load = T2 = 200 ns - 64 ns - 7 ns - 15 ns = 114 ns, + T3 - ClK to RAS - Transceiver Delay - Data Setup n. tcAC NS32CG821-25 Part Normal-Heavy Load = T2 + Tw + T3 - ClK to CAS Transceiver Delay - Data Setup 3Tep $308act - tphl - #t01 8 = 200 ns - 82 ns - 7 ns - 15 ns = 133 ns - 22 ns - 7 ns - 15 ns = 98ns Normal-Heavy Load = 89 = 200 ns - 69 ns - 7 ns - 15 ns n. NS32CG821-25 Part Light Load = T2 = 109 ns + T3 - ClK to Column Address Valid - Transceiver Delay - Data Setup = 34 n. NS32CG821-25 Part see DRAM data sheet (usually < 100 ns) = T4 + T1 - CTTLtoTSOlnactive + [(ClK High to ~ Asserted) - ('i'SC5 Negated to RAS Negated)) = 133 ns - 64 ns - 7 ns - 15 ns NS32CG821-25 Part = 2Tep - tTSOia + = 133 ns - 10 ns = T2 + T3 - ClK to CAS - Transceiver Delay - Data Setup for NS32CG18 #tOl s = 133 ns - 82 ns - 7 ns - 15 ns = 29 ns $53 4 ns + = 127 ns @ 15 MHz = 2Tep - $308act - !Phi - RAS LOW DURING REFRESH NS32CG821-25 Part Normal-Heavy Load = 133 ns - 69 ns - 7 ns - 15 ns = 42 ns NS32CG821-25 Part RAS PRECHARGE PARAMETER (FOR BOTH ZERO AND ONE WAIT STATE) RAS Precharge Time Normal-Heavy Load = 47ns Light Load NS32CG821-25 Part Light Load = 2Tep - $316act - tphl - #tOl s = 133 ns - 77 ns - 7 ns - 15 ns tCAC NS32CG821-25 Part Light Load = 2Tep - $307 - !Phi - #t0l8 = 133 ns - 26 ns - 7 ns - 15 ns = 85 NS32CG821-25 Part Normal-Heavy Load ZERO WAIT STATES ANALYSIS FOR A 15 MHz NS32CG18 iRAC NS32CG821-25 Part Ught Load (15 ns - 17 ns) = 84 ns @ 15 MHz Light Load NS32CG821-25 Part Normal-Heavy Load Normal-Heavy Load = 66 ns = T2 + Tw + T3 - ClKto~Transceiver Delay - Delay Setup (FOR BOTH ZERO AND ONE WAIT STATE) tRAS = Programmed Clocks - [(ClK High to Refresh ~ Asserted) - (CKl High to Refresh RAS Negated)] = 2Tep - $55 = 133 ns - 6 ns NS32C0821-25 Part Light Load ., 127 liS @ 15 MHz for NS32C018 5-8 . l> Programming Bits* Bit Value Description R1, RO 1,0 RAS Low during Refresh = 2T RAS Precharge Time = 2T R3, R2 0,0 1,1 No Wait States during Non-Delayed Access One Wait State during Non-Delayed Access R5,R4 0,0 User Defined Add Wait States with WAITIN R9 User Defined .. Staggered or all RAS Refresh ... C3 C6, C5, C4 en No Wait States during Burst R6 CO, C1, C2 z ...... U"I Divisor for DELCLK Time between Refreshes User Defined Depends on User's DRAM Configurations = 0 ns = 15 ns C7 1 Choose tASC C8 1 Choose tRAH C9 1 Delay CAS for Write Accesses BO 1 Address Latches are Fall Through • ECASO, B1, and R7 must be programmed low and R8 must be programmed high for operation of chip. "Choose C2, C1, CO = 1,0,1 for NS32CG16 @ 10 MHz 0,1,0 for NS32CG16 @ 15 MHz, w/Heavy Load 0,1,1 for NS32CG16 @ 15 MHz, wI Light Load ... Choose C3 = o for NS32CGG16 @ 10 MHz 1 for NS32CG16 @ 15 MHz Normal-Heavy Load o for NS32CG16 @ 15 MHz Light Load II 5-7 ~ ~ NS32CG16-NS32CG821 Dram Timing for 0 Wait States II( READ CYCLE T1 CPU STATES eG16 WRITE CYCLE 13 T2 T4 T1 T2 T3 T4 NS32CG821 cm ADS ALE as \J --.r\ \...J n T\ 1\ :::x ADDRESS X VALID ;so VALID / \ J WiN \ m ,- \ \ CAS QO-8.9.10 V :::x ROW r- \ X COLUWN X ROW X COLUWN \ WAIT (connect to CWAI!) DATA (DRAW) J. J. ~ ~ READ DATA WRITE DATA }--TLIFll0130-2 5·8 NS32CG16-NS32CG821 DRAM TImIng wIth One Walt State WRITE CYCLE READ CYCLE ~ COli T2 TI TW TW T2 TI T4 T3 T3 T4 NS32CGB21 em rv ADS \.J ALE J' n CS T\ 1\ -X ADDRESS X VALID t TSO ,r'"' \ m \ / \ CAS U QD-a.9.ID II \ ',..J WiN VALID ROW \ / X rl- \ X COlUWN ROW X COlUWN \ J. WAiT J. '---.1.11 (,onnoel to 00ii) \_J.t TL/F/l0130-3 Access Requeat durIng an Internal Refresh Cycle (for One Walt State durIng Access) ClK 110-9 INTERNAL REFRESH IN PROGRESS (NOT A PIN BUT INCLUDED FOR DIAGftAII CLARITY. M:TIVE LOW) I ?:~ .2:;;~ I I I VALID ROW REFRESH ROW \ )( ~ W/~ VALID COL / 2T m LOW / 2T PRECHARGE \ 1\ ALE t '0Wm ~ z:x-n Y l l l l l II 1\ TLlF/l0130-4 5-9 Section 6 Physical Dimensionsl Appendices Section 6 Contents Physical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . Bookshelf Distributors 6·2 6-3 ." i ~National ~ Semiconductor All dimensions are in inches (millimeters) ~ c 3' CD ~ (II 48 Lead Hermetic Dual-In-Line Package (D) NS Package Number D48A I. . 4J '" 41 44 43 41 41 41 • 11 :rr 31 31 31 :t1 3D II 0' ~ (II II U ZJ II ~~~I~~I~~~Tf L',D. ····,'···r I • fl. to 11 11 IS M 11 I. U I' II II Z1 II 13 Z4 ::=:~!:I TY' LEADS VEATtCAL TO 11° MAX OUTWARD 0.110-1.120 iMiHUii ryp REF 52 Lead Sidebraze Hermetic Dual-In-Llne Package (D) NS Package Number D52A ~-------------------------~--------------------------~ U MHO I aiD iT.ilii ; I'HI-a' ll -I.' I· j 4 Q U • Q " g , • • W " " ~ MAl Q n A D " '1 ,. ,. " • " " u n ~ U 17 ,. U H ~ n n " .~~ii.~::::::::::::::::::::::::tl::::::::::::1J.ll!.:!.I!!!. i--- • n u • ____~--______~~____~ IWIII ..... "0 MAX Al,LIIWMIU 6·3 U ) 'w!'i ~(::I H 20 Lead Ceramic Dual-In-Llne Package (J) NS Package Number J20A 0.985 ~-----(25.019) -----~ MAX 0.005-0.020 (0.127-0.508) HADTYP 0.IS0 i4.572i GLASS SEALANT MAX 0.200 (5.080) MAX 0.150 (3.810) MIN D.OOS-0.012 (0.203 - 0.305) I-- 0.310-0.410 O.01S±o.OO3 ~II_ (D.457±0.076)11 (7.S74-10.41) t 0.125-0.200 (3.175-5.080) t J20A ~REV M) 20 Lead Molded Dual-In-Line Package (N) NS Package Number N20A 1.013-1.040 (25.73-26.42) 0.092 X0.030 (2.337 x0.782) MAXDP :=:1 0'032±0'005~O 19 ~====~1~8==17===1==1=6==14===13==1=2==11~---r 0.260 <0.005 (6.604 to.127) PIN NO. IIDENT ~ (~:~~:)~ (0.SI3tO.I27) RAD PIN NO.IIDENT~ ~~~~~~~~ MIN 1 OPTION 2 0.300-0.320 C"""I 0.065 (1.8&1) ~~~++~~~~~~~ :!J 0.009-0.01& (0.229-0.381) TVP 0.08000.005 +0040. 1 (1.524>0.127) 0.32& -DllI& f I t- 0.01"0.003 (0.4&7> 0.078) ~~ 0.12&-0.140 (3.17&-3.556) 0.020 (0.508) MIN 11.2&5 +1.018 ~ -0.381 N20A (REV 0) 6-4 24 Lead Skinny Dual-In-Line Package (0.300" Centers Molded) (N) NS Package Number N24C 0,092 (2,337) (2 PLS) PIN NO, 1 IDENT 0,260±0.005 (6,604±0,127) I 0,300-0,320 :"~~'" I 0,009-0,015 (0,229-0,381) 0.325 ~~:~~~ 1 ,016) (8 ,255 + -0,381 -+-~"':::::':---I N24C (REV F) 48 Lead Molded Dual-In-Line Package (N) NS Package Number N48A r-----------~(:D~-:1~)------------I1 ~ I O.550±O,Q05 (13.97±O.127) ~ ~ ~ ~ ~ 0.062 (1.574) ,AD 0,030 r:;= (D.762) -I=t= MAX 0.600-0,620 '\""±\'Bt (15,24-15,741 ~ --(14.73) M I N - - '.500 0.009-0.015 ~ 0.625 ~:::~~ (11i.88 ~~:~;~ 6-5 ~ ~ W 3 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ 2 U ~ ~ en c o '~ CD 68 Lead Plastic Chip Carrier (V) NS Package Number V68A E i:S 0.020 (0.508) MIN 0.104 -0.118 ~ '!!. f. ~ rQ "l 0.828 0.950 (24.13) REFSQ 0.050=0.800 (~l': 0.915-0.998 ,;~~ .D (8.382) DIANOM PEDESTAL (25.02-25.U) SQUARE Rf --L 44•...........,..n.n.n.r;.n..n..r,....,..,.",n.n.n.r;.n.r-r· 26 ~ U 0.826 -----I~~I ~..o----- (20.91) NOM V66A (ReV G) 84 Lead Plastic Chip Carrier (V) NS Package Number V84A ~ 12.M2-2.9971 J 1.nOtO,010 II.... ±O.2M) 80 CONTACT DIMENSION "L ~-J (1.193-1.348) REF 20 SPACES AT REF'O 11.124) t .L...-O-.O-30-_-0.0-4S---...tb,"""I.-' 0.1611-0180 0,004 (O.78Z-1.143) HAD TYP :~~ 0.186-0.180 (4.111-4.1572) ~ (O.lo2) TOTAL o/Ioj'lo/'o./\oOlOlll 11.087-1.118) ~ I 1ll.LLULLLU~ ~"--Oo-"--J--i
Source Exif Data:File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.6 Linearized : No Create Date : 2016:08:10 20:01:32-08:00 Modify Date : 2016:08:10 20:49:46-07:00 XMP Toolkit : Adobe XMP Core 4.2.1-c041 52.342996, 2008/05/07-21:37:19 Metadata Date : 2016:08:10 20:49:46-07:00 Producer : Adobe Acrobat 9.0 Paper Capture Plug-in Format : application/pdf Document ID : uuid:4ba2c9b0-6352-ed45-8bd2-12a884f6e134 Instance ID : uuid:43451cbe-5809-9241-a4c8-58fba7ac2228 Page Layout : SinglePage Page Mode : UseNone Page Count : 648EXIF Metadata provided by EXIF.tools