1989_National_DRAM_Management_Handbook 1989 National DRAM Management Handbook

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DRAM MANAGEMENT
1989 Edition

Dynamic Memory Control
Error Detection and Correction
Microprocessor Applications for
the DP8408A/09A/17/18/19/28/29
Microprocessor Applications for
the DP8420A/21A/22A
Microprocessor Application for
the NS32CG821
Physical Dimensionsl Appendices
iii

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DRAM Management Introduction
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Introduction to VLSI Products
E/homst/FDO!

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Ihnagem.nt

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csBons

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TL/XX/0058-1

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vii

Table of Contents
Alphanumeric Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Section 1 Dynamic Memory Control
DRAM Controller Master Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DP8408A Dynamic RAM Controller/Driver.......................................
DP8409A Multi-Mode Dynamic RAM Controller/Driver. . . . . .. . . . .. . . . . . . . . . . ... . .. .
DP8417/NS32817/DP8418/NS32818/DP8419/NS32819/DP8419X/NS32819X
64k, 256k Dynamic RAM Controller/Drivers....................................
DP8428/NS32828/DP8429INS32829 1 Megabit High Speed Dynamic RAM
Controller/Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DP8420AlDP8421A/DP8422A microCMOS Programmable 256k/1 M/4M Dynamic
RAM Controller/Drivers. . . . . . . . . . . . . .. . ... . . .. . . . . . . . . . . .. . . . . . . . .. . . . . . . . . .
NS32CG821 microCMOS Programmable 1M Dynamic RAM Controller/Driver........
DP8520A/DP8521A/DP8522A microCMOS Programmable 256k/1M/4M Video RAM
Controller/Drivers (see Graphics Databook) ...................................
29F68 Dynamic RAM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
54F /7 4F968 1 Mbit Dynamic RAM Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-305 Precautions to Take When Driving Memories. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AB-1 DP8408A/DP8409A1DP8417 /DP8418/DP8419/DP8428/DP8429 Application
Hints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AB-9 DP8408A/DP8409A Fastest DRAM Access Mode. . . . . . . . . . . . . . . . . . . . . . . . . . .
Section 2 Error Detection and Correction
54F/74F420 Parallel Check Bit/Syndrome Bit Generator. .. . . . . . .. . . . . . .. . . . . . . . . .
DP8400-2 E2C2 Expandable Error Checker/Corrector . . . . .. . . . . . .. . .. . . . . . .. . . . . . .
DP8402A/DP8403/DP8404/DP8405 32-Bit Parallel Error Detection and Correction
Circuits (EDAC's) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
54F/74F632 32-Bit Parallel Error Detection and Correction Circuit. . . . . . . . . . . . . . . . . .
AN-306 Expanding the Versatility of the DP8400 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-308 DP8400s in 64-Bit Expansion ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Section 3 Microprocessor Applications for the DP8408A/09A117/18/19/28/29
Microprocessor to DP8409A/17 118/19/28/29 Interface Selection Guide. . . . . . . . . . . .
DP84300 Programmable Refresh Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DP84322 Dynamic RAM Controller Interface Circuit for the 68000 CPU ............. ,
DP84412 Dynamic RAM Controller Interface Series Circuit for the SeriGs 32000 CPU. .
DP84422 Dynamic RAM Controller Interface Circuit for the 68000/008/010 CPUs ....
DP84432 Dynamic RAM Controller Interface Circuit for the 8086/8088/80186/80188
CPUs .. . .. . . . . . .. .. . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . .. .
DP84512 Dynamic RAM Controller Interface Circuit for the NS32332 . . . . . . . . . . . . . . . .
DP84522 Dynamic RAM Controller Interface Circuit for the 68020 CPU . . . . . . . . . . . . . .
DP84532 Dynamic RAM Controller Interface Circuit for the iAPX 286 CPU. . .. . . . . . . . .
AN-309 InterfaCing the DP8408A1DP8409A to Various Microprocessors. . . . . . . . . . . . .
AN-387 DP8400/DP8419 Error Correcting Dynamic RAM Memory System for the
Series 32000 ..............................................................
AN-411 Determining the Speed of the Dynamic RAM Needed When Interfacing the
DP8419-80 to Most Major Microprocessors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-436 Dual Port Interface for the DP8417 /DP8418/DP8419/DP8428/DP8429
DRAM Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Section 4 Microprocessor Applications for the DP8420Al21A/22A
AB-36 Exp!anation of National Semiconductor "PLAN" Software for Programming
PALs.....................................................................
AN-542 Interfacing the DP8420AlDP8421A/DP8422A to the
NS320081NS32016/NS32C016/NS32032 and NS32132. . . . . . . . . . . . . . . . . . . . . . . .
viii

x
1-3
1-4
1-22
1-44
1-69
1-92
1-164
1-200
1-201
1-202
1-203
1-207
1-208
2-3
2-4
2-38
2-55
2-56
2-68
3-3
3-4
3-9
3-24
3-37
3-51
3-64
3-65
3-81
3-93
3-107
3-122
3-129

4-3
4-4

Table of Contents (Continued)
Section 4 Microprocessor Applications for the DP8420Al21A122A (Continued)
AN-543 Interfacing the DP8420AlDP8421A/DP8422A to the NS32332. . . . . . . . . . . .. .
AN-541 Interfacing the DP8420AlDP8421 A/DP8422A to the NS32532 . . . . . . . . . . . . . .
AN-540 A Dual Access NS32532 Error Detecting and Correcting Memory System. . . . .
AN-538 Interfacing the DP8420AlDP8421 A/DP8422A to the 680001008/010 . . . . . . . .
AN-615 Interfacing the DP8422A to the 68000-16 (Zero Wait State Burst Mode
Access) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-539 Interfacing the DP8420AlDP8421 A/DP8422A to the 68020 ................
AN-616 Interfacing the DP8422A to the 68020 (Zero Wait State Burst Mode Access) . .
AN-617 Interfacing the DP8422A to an Asynchronous Port B in a Dual 68020 System. .
AN-537 Interfacing the DP8420AlDP8421A1DP8422A to the 68030 Microprocessor..
AN-535 A Dual Access DP8422A/68030/74F632 Error Detecting and Correcting
Memory System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-544 Interfacing the DP8420A/DP8421 A/DP8422A to the 8086/186/88/188
Microprocessor ...... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-545 Interfacing the DP8420AlDP8421 A/DP8422A to the 80286 ................
AN-618 Interfacing the DP8420A/DP8421A/DP8422A to the 80286 Above 25 MHz,
Including No Wait States in Burst Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-536 Interfacing the DP8420A/DP8421A/DP8422A to the 80386 ................
AN-619 Interfacing the DP8420A/DP8421 A/DP8422A to the 80386 (Zero Wait State
Burst Mode Access) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-602 Interfacing the DP8420A/DP8421 A/DP8422A to the 29000 Utilizing the Burst
Mode Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-546 Interfacing the DP8420A/DP8421A/DP8422A to the Z280/Z80000/Z8000
Microprocessor ...... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-642 Interfacing the Dual Port DP8422A to the TMS320C30 and the VM E Bus .....
Section 5 Microprocessor Application for the NS32CG821
AN-576 Interfacing the NS32CG821 to the NS32CG16 . . . . . . . . . .. . . . . . . . . . . . . . . . . .
Section 6 Physical Dimensions! Appendices
Physical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bookshelf
Distributors

ix

4-11
4-24
4-34
4-40
4-56
4-61
4-82
4-86
4-90
4-98
4-113
4-117
4-129
4-138
4-154
4-170
4-183
4-187
5-3
6-3

Alpha-Numeric Index
29F68 Dynamic RAM Controller ........................................................... 1-201
54F420 Parallel Check Bit/Syndrome Bit Generator ............................................ 2-3
54F632 32-Bit Parallel Error Detection and Correction Circuit ................................... 2-55
54F968 1 Mbit Dynamic RAM Controller .................................................... 1-202
74F420 Parallel Check Bit/Syndrome Bit Generator ............................................ 2-3
74F632 32-Bit Parallel Error Detection and Correction Circuit ................................... 2-55
74F9681 Mbit Dynamic RAM Controller .................................................... 1-202
AB-1 DP8408A1DP8409A1DP8417/DP8418/DP8419/DP8428/DP8429 Application Hints ........ 1-207
AB-9 DP8408A/DP8409A Fastest DRAM Access Mode ...................................... 1-208
AB-36 Explanation of National Semiconductor "PLAN" Software for Programming PALs ............ 4-3
AN-305 Precautions to Take When Driving Memories ........................................ 1-203
AN-306 Expanding the Versatility of the DP8400 .............................................. 2-56
AN-308 DP8400s in 64-Bit Expansion ....................................................... 2-68
AN-309 Interfacing the DP8408A/DP8409A to Various Microprocessors ......................... 3-93
AN-387 DP8400/DP8419 Error Correcting Dynamic RAM Memory System for the Series 32000 ... 3-107
AN-411 Determining the Speed of the Dynamic RAM Needed When Interfacing the
DP8419-80 to Most Major Microprocessors ............................................... 3-122
AN-436 Dual Port Interface for the DP8417/DP8418/DP8419/DP8428/DP8429 DRAM Controller. 3-129
AN-535 A Dual Access DP8422A168030174F632 Error Detecting and Correcting Memory System .. 4-98
AN-536 Interfacing the DP8420A/DP8421A1DP8422A to the 80386 ........................... 4-138
AN-537 Interfacing the DP8420AlDP8421A1DP8422A to the 68030 Microprocessor .............. 4-90
AN-538 Interfacing the DP8420AlDP8421A1DP8422A to the 68000/008/010 .................... 4-40
AN-539 Interfacing the DP8420A/DP8421A1DP8422A to the 68020 ............................ 4-61
AN-540 A Dual Access NS32532 Error Detecting and Correcting Memory System ................. 4-34
AN-541 Interfacing the DP8420AlDP8421 AI DP8422A to the NS32532 .......................... 4-24
AN-542 Interfacing the DP8420AlDP8421A1DP8422A to the
NS32008/NS320161NS32C0161NS32032 and NS32132 ..................................... 4-4
AN-543 Interfacing the DP8420AlDP8421A/DP8422A to the NS32332 .......................... 4-11
AN-544 Interfacing the DP8420AlDP8421 AI DP8422A to the 8086/186/88/188 Microprocessor .. 4-113
AN-545 Interfacing the DP8420AlDP8421A/DP8422A to the 80286 ........................... 4-117
AN-546 Interfacing the DP8420A/DP8421A1DP8422A to the Z280/Z80000/Z8000
Microprocessor ....................................................................... 4-183
AN-576 Interfacing the NS32CG821 to the NS32CG16 ......................................... 5-3
AN-602lnterfacing the DP8420AlDP8421 AI DP8422A to the 29000 Utilizing the Burst Mode
Access .............................................................................. 4-170
AN-615 Interfacing the DP8422A to the 68000-16 (Zero Wait State Burst Mode Access) ........... 4-56
AN-616 Interfacing the DP8422A to the 68020 (Zero Wait State Burst Mode Access) .............. 4-82
AN-617 Interfacing the DP8422A to an Asynchronous Port B in a Dual 68020 System ............. 4-86
AN-618 Interfacing the DP8420AlDP8421 AlDP8422A to the 80286 Above 25 MHz, Including
No Wait States in Burst Mode ........................................................... 4-129
AN-619 Interfacing the DP8420AlDP8421 A/DP8422A to the 80386 (Zero Wait State Burst Mode
Access) .............................................................................. 4-154
AN-642 Interfacing the Dual Port DP8422A to the TMS320C30 and the VME Bus ................ 4-187
DP8400-2 E2C2 Expandable Error Checker/Corrector .......................................... 2-4
DP8402A 32-Bit Parallel Error Detection and Correction Circuits (EDAC's) ....................... 2-38
DP8403 32-Bit Parallel Error Detection and Correction Circuits (EDAC's) ......................... 2-38
DP8404 32-Bit Parallel Error Detection and Correction Circuits (EDAC's) ......................... 2-38
DP8405 32-Bit Parallel Error Detection and Correction Circuits (EDAC's) ......................... 2-38
DP8408A Dynamic RAM Controller/Driver .................................................... 1-4
DP8409A Multi-Mode Dynamic RAM Controller/Driver ......................................... 1-22
DP8417 64k Dynamic RAM Controller/Driver ................................................. 1-44

x

Alpha-Numeric Index (Continued)
DP8418 64k Dynamic RAM Controller/Driver ................................................. 1·44
DP8419 256k Dynamic RAM Controller/Driver ............................................... 1·44
DP8419X 256k Dynamic RAM Controller/Driver .............................................. 1·44
DP8420A microCMOS Programmable 256k Dynamic RAM Controller/Driver ..................... 1·92
DP8421 A microCMOS Programmable 1M Dynamic RAM Controller/Driver ....................... 1·92
DP8422A microCMOS Programmable 4M Dynamic RAM Controller/Driver ....................... 1·92
DP84281 Megabit High Speed Dynamic RAM Controller/Driver ................................ 1·69
DP84291 Megabit High Speed Dynamic RAM Controller/Driver ................................ 1·69
DP8520A microCMOS Programmable 256k Video RAM Controller/Driver (see Graphics
Databook) ............................................................................ 1·200
DP8521A microCMOS Programmable 1M Video RAM Controller/Driver (see Graphics Databook) .. 1·200
DP8522A microCMOS Programmable 4M Video RAM Controller/Driver (see Graphics Databook) .. 1·200
DP84300 Programmable Refresh Timer ...................................................... 3·4
DP84322 Dynamic RAM Controller Interface Circuit for the 68000 CPU ........................... 3·9
DP84412 Dynamic RAM Controller Interface Series Circuit for the Series 32000 CPU .............. 3·24
DP84422 Dynamic RAM Controller Interface Circuit for the 68000/008/010 CPUs ................ 3·37
DP84432 Dynamic RAM Controller Interface Circuit for the 8086/8088/80186/80188 CPUs ........ 3·51
DP84512 Dynamic RAM Controller Interface Circuit for the NS32332 ............................ 3·64
DP84522 Dynamic RAM Controller Interface Circuit for the 68020 CPU .......................... 3·65
DP84532 Dynamic RAM Controller Interface Circuit for the iAPX 286 CPU ........................ 3·81
NS32CG821 microCMOS Programmable 1M Dynamic RAM Controller/Driver ................... 1·164
NS32817 64k Dynamic RAM Controller/Driver ............................................... 1·44
NS32818 64k Dynamic RAM Controller/Driver ............................................... 1·44
NS32819 256k Dynamic RAM Controller/Driver .............................................. 1·44
NS32819X 256k Dynamic RAM Controller/Driver ............................................. 1·44
NS328281 Megabit High Speed Dynamic RAM Controller/Driver ............................... 1·69
NS328291 Megabit High Speed Dynamic RAM Controller/Driver ............................... 1·69

xi

Section 1
Dynamic Memory Control

Section 1 Contents
DRAM Controller Master Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DP8408A Dynamic RAM Controller/Driver.............................................
DP8409A Multi-Mode Dynamic RAM Controller/Driver..................................
DP8417INS32817 /DP8418/NS32818/DP8419/NS32819/DP8419XINS32819X 64k, 256k
Dynamic RAM Controller/Drivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DP8428INS32828/DP8429/NS32829 1 Megabit High Speed Dynamic RAM
Controller/Drivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DP8420AlDP8421A/DP8422A microCMOS Programmable 256k/1 M/4M Dynamic RAM
Controller/Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS32CG821 microCMOS Programmable 1M Dynamic RAM Controller/Driver. .. . . . . .. .. . ..
DP8520AlDP8521 AlDP8522A microCMOS Programmable 256k/1 M/4M Video RAM
Controller/Drivers (see Graphics Databook) .........................................
29F68 Dynamic RAM Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
54F174F9681 MbitDynamic RAM Controller..........................................
AN-305 Precautions to Take When Driving Memories ...................................
AB-1 DP8408A/DP8409A1DP8417 /DP8418/DP8419/DP8428/DP8429 Application Hints. . .
AB-9 DP8408A1DP8409A Fastest DRAM Access Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

1-2

1-3
1-4
1-22
1-44
1-69
1-92
1-164
1-200
1-201
1-202
1-203
1-207
1-208

DRAM Controller Master Selection Guide
The data below is intended to highlight the key differentiable features of each DRAM ControllerIDriver offered by National Semiconductor. All NSC DRAM controllers integrate
onboard delay line timing. high capacitive drive. row/column muxing logic. refresh counter. row and column input latches. memory bank select logic. As a result of the family
feature commonality. most devices offer pin for pin up/downward compatiblity. Beyond this however. the process and design differences between the devices result in a broad
selection of feature and performance options for the best system fit.

Device # &
Speed Options

'"

DRAMS
Supported

Process

Typ

Icc

DP8408A
A-2
A-3

16.64k

DP8409A
A-2
A-3

16. 64. 256k

DP8417-80
-70

16.64. 256k

DP8418-80
-70

16. 64. 256k

DP8419-80
-70

16. 64. 256k

DP8420A. DP8421A

16. 64. 256k.
1 Mega Bit.
4 MegaBit

2,... CMOS

16. 64. 256k

Oxide
Isolated
(ALS)

150mA

Oxide
Isolated
(ALS)

150mA

& DP8422A
DP8428-80
-70

& 1 MegaBit

DP8429-80
-70

& 1 MegaBit

16. 64. 256k

Junction
Isolated
(S)

210mA

Junction
Isolated
(S)

210mA

Oxide
Isolated
(ALS)

150mA

Oxide
Isolated
(ALS)

150mA

Oxide
Isolated
(ALS)

150mA

5mA

A.C. Specified
Word Width

MaxRAS
to CAS Out
> Fast I Slow
Mode Mode

Guaranteed Row
Address Hold
> Fast I Slow
Mode Mode

4 Banks of
16 Bit Data wi
6 Bit ECCea.

105 ns/125 ns
85 ns/100 ns
120 ns/145 ns

20 ns/30 ns
12 ns/20 ns
20 ns/30 ns

+5V ±5%

4 Banks of
16 Bit Data wi
6 Bit ECCea.

105 ns/125 ns
85 ns/100 ns
120 ns/145 ns

20 ns/30 ns
12 ns/20 ns
20 ns/30 ns

+5V ±5%

4 Banks of
16 Bit Data wi
6 Bit ECCea.

63 ns/80 ns
50 ns/72 ns

15 ns/25 ns
15 ns/25 ns

+5V ±10%

2 Banks of
32 Bit Data wi
7 Bit ECCea.

63 ns/80 ns
50 ns172 ns

15 ns/25 ns
15 ns/25 ns

+5V ±10%

4 Banks of
16 Bit Data wi
6 Bit ECCea.

63 ns/80 ns
50 ns172 ns

15 ns/25 ns
15 ns/25 ns

+5V ±10%

53 ns/63 ns

15 ns/25 ns

2 Banks of
32 Bit Data wi
7 Bit ECC ea.

63 ns/80 ns
50 ns172 ns

15 ns/25 ns
15 ns/25 ns

+5V ±10%

4 Banks of
16 Bit Data w/
6 Bit ECC ea.

63 ns/80 ns
50 ns172 ns

15 ns/25 ns
15 ns/25 ns

+5V ±10%

2 Banks of
32 Bit Data w/
7 Bit ECCea.

Operating
Temp Range

Vcc

+5V ±10%

Package

Page
No.

[ 48N ]
48D

1-4

[ 48N ]
48D
68V

1-22

0°-70°C
]
-400-+85°C
-55°- + 125°C

[ 48 N ]
48D
68V

1-44

0°-70°C
]
-400-+85°C
-55°-+ 125°C

[ 48 N ]
48D
68V

1·44

0°-70°C
]
-400-+85°C
-55°-+ 125°C

[ 48 N ]
48D
68V

1·44

0°-70°C
]
-40°_+ 85°C
-55°_+ 125°C

[ 68V ]

0°-70°C
]
-40°- + 85°C
-55°- + 125°C

[ 52D ]
68V

1-69

0°-70°C
]
-400-+85°C
-55°- + 125°C

[ 52D ]
68V

1-69

[

0"-70°C
0°-85°C

[

0°-70°C
0°-85°C

[

[

[

[

[

[

]
]

1-92

*All AC valves shown factor in worst case loading (including all ouputs switching simultaneously), operating temperature, and Vee supply variables. All delays assume the use of National's on-board automatic timing and
delay line logic aHhough external delay line control timing is allowed and supported.

ap!n~

UO!I:>alas JalSew JaIlOJIUO:) WVI:IO

~

~ ~National

~ ~ Semiconductor
DP8408A Dynamic RAM Controller IDriver
General Description

Operational Features

Dynamic memory system designs, which formerly required
several support chips to drive the memory array, can now
be implemented with a Single IC ... the DPB40BA Dynamic
RAM Controller/Driver. The DPB40BA is capable of driving
all 16k and 64k Dynamic RAMs (DRAMs). Since the
DPB40BA is a one-chip solution (including capacitive-load
drivers), it minimizes propagation delay skews, the major
performance disadvantage of multiple-chip memory drive
and control.

• All DRAM drive functions on one chip-minimizes skew
on outputs, maximizes AC performance
• On-chip capacitive-load drives (specified to drive up to
BB DRAMs)
• Drive directly all 16k and 64k DRAMs
• Capable of addressing 64k and 256k words
• Propagation delays of 25 ns typical at 500 pF load
• CAS goes low automatically after column addresses are
valid if desired
• Auto Access mode provides RAS, Row to Column,
select, then CAS automatically and fast
• WE follows WIN unconditionally-offering READ,
WRITE or READ-MODIFY-WRITE cycles
• On-chip 8-bit refresh counter with selectable End-ofCount (127 or 255)
• End-of-Count indicated by RF I/O pin going low at 127
or 255
• Low input on RF I/O resets 8-bit refresh counter
• CAS inhibited during refresh cycle
• Fall-through latches on address inputs controlled by ADS
• TRI-STATE outputs allow multi-controller addressing of
memory
• Control output signals go high-impedance logic "1"
when disabled for memory sharing
• Power-up: counter reset, control Signals high, address
outputs TRI-STATE, and End-of-Count set to 127

The DP840BA's 6 modes of operation offer a wide selection
of DRAM control capabilities. Memory access may be controlled externally or on-chip automatically; an on-chip refresh counter makes refreshing less complicated.
The DP840BA is a 48-pin DRAM Controller/Driver with 8
multiplexed address outputs and control signals. It consists
of two B-bit address latches, an 8-bit refresh counter, and
control logic. All output drivers are capable of driving 500 pF
loads with propagation delays of 25 ns. The DPB408A timing parameters are specified driving the typical load capacitance of 88 DRAMs, including trace capacitance.
The DP8408A has 3 mode-control pins: M2, Ml, and MO,
where M2 is in general REFRESH. These 3 pins select 6
modes of operation. Inputs Bl and BO in the memory access modes (M2 = 1), are select inputs which select one of
four RAS outputs. During normal access, the 8 address outputs can be selected from the Row Address Latch or the
Column Address Latch. During refresh, the 8-bit on-Chip refresh counter is enabled onto the address bus and in this
mode all RAS outputs are selected, while CAS is inhibited.
The DP8408A can drive up to 4 banks of DRAMs, with each
bank comprised of 16k's, or 64k·s. Control signal outputs
RAS, CAS, and WE are provided with the same drive capability. Each RAS output drives one bank of DRAMs 50 that
the four RAS outputs are used to select the banks, while
CAS, WE, and the multiplexed addresses can be connected
to all of the banks of DRAMs. This leaves the non-selected
banks in the standby mode (less than one tenth of the operating power) with the data outputs in TRI-STATE®. Only the
bank with its associated RAS low will be written to or read
from.

Mode Features
• 6 modes of operation: 3 access, 1 refresh, and 2 set-up
• 2 externally controlled modes: 1 access (Mode 4) and
1 refresh (Modes 0, 1 , 2)
• 2 auto-access modes RAS ~ R/C ~ CAS automatic,
with tRAH = 20 or 30 ns minimum (Modes 5, 6)
• Externally controlled AII-RAS Access modes for memory initialization (Mode 3)
• End-of-Count value of Refresh Counter set by Bl and
BO (Mode 7)

DP8408A Interface Between System & DRAM Banks

~6~i~~L

~

RAM
CONTROL
6

10

SYSTEM

.

'1

DP84DBA
DYNAMIC RAM
CDNTROLLERI
DRIVER

50DpF DRIVE

RAM
ADDRESS

SYSTEM
ADDRESS

MEMORY

8
I

16k DR 64k
DYNAMIC
RAM BANKS
TLlF/B40B-1

1-4

Block Diagram

II

ROW ADDRESS
INPUT LATCH

RO-7

ADS

1

CO-7

\

•

COLUMN ADDR.
INPUT LATCH

I
I

H
I
I
I
I

l

8·BIT
REFRESH
COUNTER

HIGH CAPACITIVE DRIVE
CAPABILITY OUTPUTS
WHEN ENABLED

;1~ ....

l

I
'
I
I
I
I

I

t-

I
I

00-7

~

• INDICATES THAT THERE
IS A 3kQ PULL·UP
RESISTOR ON THESE
OUTPUTS WHEN THEY
ARE DISABLED

I

~

REFRESH

r--

~RAS3

~RAS2
I-- ~RASI
I--

RAS
DECODER

t
81_

BANK SELECT
8 0 _ INPUT LATCH

cs_

t

~-

ff-

I-

- I-

r--;:z.

+RASIN

t
CONTROL LOGIC

+

WIN

RFtO

+

L

M2(RFSH)

.....

..

iIASIN _

R/C_
CAIiN_

......

+
I

+
I

Ml

MO

.....

RAS 0

CAS

OUTPUT
ENABLE

iNE

TLlF/B40B-2

TABLE I. DP8408A Mode Select Options
Mode

(RFSH)
M2

M1

MO

0

0

0

0

1

0

0

1

2

0

1

0

Mode of Operation

Conditions

Externally Controlled Refresh

RFI/O

AII-RAS Active

=

EOC

3

0

1

1

Externally Controlled AII-RAS Write

4

1

0

0

Externally Controlled Access

Active RAS defined by Table II

5

1

0

1

Auto Access, Slow tRAH

Active RAS defined by Table II

6

1

1

0

Auto Access, Fast tRAH

Active RAS defined by Table II

7

1

1

1

Set End of Count

See Table III for Mode 7

1·5

•

!
Q

Pin Definitions
Vee, GND, GNo-Vee = 5V ±5%. The three supply pins
have been assigned to the center of the package to reduce
voltage drops, both DC and AC. There are also two ground
pins to reduce the low level noise. The second ground pin is
located two pins from Vee, so that decoupling capacitors
can be inserted directly next to these pins. It is important to
adequately decouple this device, due to the high switching
currents that will occur when all 8 address bits change in the
same direction simultaneously. A recommended solution
would be a 1 ,..F multilayer ceramic capacitor in parallel with
a low-voltage tantalum capaCitor, both connected as close
as possible to pins 36 and 38 to reduce lead inductance.
See Figure below.

WIN: Write Enable Input.
WE: Write Enable Output-Buffered output from WIN.'
CAS: Column Address Strobe Output-In Modes 5 and 6,
CAS goes low following valid column address. In Modes 3
and 4, it transitions low after RIC goes low, or follows
CASIN going low if RIC is already low. CAS is high during
refresh.'
RAS 0-3: Row Address Strobe Outputs-Selects a memory bank decoded from Bl and BO (see Table II), if RFSH is
high. If RFSH is low, all banks are selected"
BO, B1: Bank Select Inputs-Strobed by ADS. Decoded to
enable one of the RAS outputs when RASIN goes low. Also
used to define End-of·Count in Mode 7 (Table III).

...-----..,

1''These outputs may need damping resistors to prevent overshoot, undershoot. See AN·aDS "Precautions to Take When Driving Memories."

Vee (PIN 36) O-------~
'MULTILAYER
CERAMIC
GND (PINS 38, 13)

I

'TANTALUM

_

T...L

TABLE II. Memory Bank Decode
Bank Select
(Strobed by ADS)

0
TLlF/B40B-3

"Capacitor values should be chosen depending on the particular application.

RO-R7: Row Address Inputs.
CO-C7: Column Address Inputs.
QO-Q7: Multiplexed Address Outputs-Selected from
the Row Address Input Latch, the Column Address Input
Latch, or the Refresh Counter.'
RASIN: Row Address Strobe Input-Enables selected
RAS n output when M2 (RFSH) is high, or all RAS n outputs
when RFSH is low.

Enabled RAS n

Bl

80

0
0
1
1

0
1
0
1

RASa
RAS1
RAS2
RAS3

Connection Diagram
Dual In-Line Package

:! ~SIN

Ric: Row/Column Select Input-Selects either the row or
column address input latch onto the output bus.
CASIN: Column Address Strobe Input-Inhibits CAS out·
put when high in Modes 4 and 3. In Mode 6 it can be used to
prolong CAS output.

~:

46
110
45 WIN
44 WE
43 DO

42 Dl

ADS: Address (Latch) Strobe Input-Row Address, Col·
umn Address, and Bank Select Latches are fall·through with
ADS high; Latches on high·to·low transition.
CS: Chip Select Input-TRI·STATE the Address Outputs
and puts the control signal into a high·impedance logic" 1"
state when high (except in Mode 0); enables all outputs
when low.

41 02

DP8408A

40 03
39 04
38 GND
37 05
36 VCC
35 06
34 07
33 NC

MO, M1, M2: Mode Control Inputs-These 3 control pins
determine the 6 major modes of operation of the DP8408A
as depicted in Table I.

32
31
30
29

RF lIo-The 1/0 pin functions as a Reset Counter Input
when set low from an external open·collector gate, or as a
flag output. The flag goes active·low when M2 = 0 and the
End·of-Count output is at 127 or 255 (see Table III).

26 Bl

CAS
RAS3
RAS2
RASI
28 RASo
27 BD
25 NC

NC = No Connection

TLlF/B40B-4

Top View
Order Number DP8408AD, DP8408AN or DP8408AN·3
See NS Package Number D48A or N48A

1-6

Conditions for all Modes
DP8408A DRIVING ANY 16K OR 64K DRAMS

INPUT ADDRESSING
The address block consists of a row-address latch, a columnaddress latch, and a resettable refresh counter. The address latches are fall-through when ADS is high and latch
when ADS goes low. If the address bus contains valid addresses until after the valid address time, ADS can be permanently high. Otherwise ADS must go low while the addresses are still valid.

The DP8408A can drive any 16k or 64k DRAMs. All 16k
DRAMs are basically the same configuration, including the
newer 5V-only version. Hence, in most applications, different manufacturers' DRAMs are interchangeable (for the
same supply-rail chips), and the DP8408A can drive all 16k
DRAMS (see Figure la).
There are three basic configurations for the 5V-only 64k
DRAMs: a 128-row by 512-column array with an on-RAM
refresh counter, a 128-row by 512-column array with no onRAM refresh counter, and a 256-row by 256-column array
with no on-RAM refresh counter. The DP8408A can drive all
three configurations, and at the same time allows them all to
be interchangeable (as shown in Figure lb and Ie), providing maximum flexibility in the choice of DRAMs. Since the
8-bit on-chip refresh counter can be used as a 7-bit refresh
counter for the 128-row configuration, or as an 8-bit refresh
counter for the 256-row configuration, the on-RAM refresh
counter (if present) is never used. As long as 128 rows are
refreshed every 2 ms (i.e. 256 rows in 4 ms) all DRAM types
are correctly refreshed.
When the DP8408A is in a refresh mode, the RF I/O pin
indicates that the on-chip refresh counter has reached its
end-of-count. This end-of-count is selectable as 127 or 255
to accommodate 16k or 64k DRAMs, respectively. Although
the end-of-count may be chosen to be either of these values, the counter is not reset and always counts to 255 before rolling over to zero.

In normal memory access operation, RASIN and R/C are
initially high. When the address inputs are enabled into the
address latches, the row addresses appear on the Q outputs. The address strobe also inputs the bank-select address, (BO and Bl). If CS is low, all outputs are enabled.
When CS is transitioned high, the address outputs go TRISTATE and the control outputs first go high through a low
impedance, and then are held by an on-chip high impedance. This allows output paralleling with other DP8408As for
multi-addressing. All outputs go active about 50 ns after the
chip is selected again. If CS is high, and a refresh cycle
begins, all the outputs become active until the end of the
refresh cycle.
DRIVE CAPABILITY
The DP8408A has timing parameters that are specified with
up to 600 pF loads. In a typical memory system this is equivalent to about 88, 5V-only DRAMs, with trace lengths kept
to a minimum. Therefore, the chip can drive four banks each
of 16 or 22 bits, or two banks of 32 or 39 bits, or one bank of
64 or 72 bits.

READ, WRITE AND READ-MODIFY-WRITE CYCLES

Less loading will slightly reduce the timing parameters, and
more loading will increase the timing parameters, according
to the graph of Figure 6. The AC performance parameters
are specified with the typical load capacitance of 88
DRAMs. This graph can be used to extrapolate the variations expected with other loading.

The output signal, WE, determines what type of memory
access cycle the memory will perform. If WE is kept high
while CAS goes low, a read cycle occurs. If WE goes low
before CAS goes low, a write cycle occurs and data at DI
(DRAM input data) is written into the DRAM as CAS goes
low. If WE goes low later than tewD after CAS goes low, first
a read occurs and DO (DRAM output data) becomes valid;
then data DI is written into the same address in the DRAM
when WE goes low. In this read-modify-write case, DI and
DO cannot be linked together. The type of cycle is therefore
controlled by WE, which follows WIN.

Because of distributed trace capacitance and inductance
and DRAM input capacitance, current spikes can be created, causing overshoots and undershoots at the DRAM inputs that can change the contents of the DRAMs or even
destroy them. To remove these spikes, a damping resistor
(low inductance, carbon) can be inserted between the
DP8408A driver outputs and the DRAMs, as close as possible to the DP8408A. The values of the damping resistors
may differ between the different control outputs; RAS's
CAS, Q's and WE. The damping resistors should be determined by the first prototypes (not wire-wrapped due to larger distributed capacitance and inductance). The best values
for the damping resistors are the critical values giving a critically damped transition on the control outputs. Typical values for the damping resistors will be between 150 and
1000, the lower the loading the higher the value. (For more
information, see AN-305 "Precautions to Take When Driving Memories.")

POWER-UP INITIALIZE
When Vee is first applied to the DP8408A, an initialize pulse
clears the refresh counter, the internal control flip-flops, and
sets the End-of-Count of the refresh counter to 127 (which
may be changed via Mode 7). As Vee increases to about
2.3V, it holds the output control signals at a level of one
Schottky diode-drop below Vee, and the output address to
TRI-STATE. As Vee increases above 2.3V, control of these
outputs is granted to the system.

1-7

II
I

:i
o
..,.
CO

a.
Q

DP8408A Driving any 16k or 64k Dynamic RAMs

, .. IJ

CAS

~

~

1m

ROWS

I

COLUMNS

-t

REFRESH
COUNTER

~I

COL. OECODE

7
ADDRESS
ORIVERS

R
128
0
W 128 16K
0
ARRAY
E
C

7
7

ADDRESS
BUS

7
+12Vor +5V 16K OYNAMIC RAMS
DP8408A
TLlF/8408-S

FIGURE 1a. DP8408A with any 16k DRAMS

[~AS LATCHES 8 COLUMN ADDRESSE

A LATCHES 7 ROW+1 COLUMN ADDRESS-

CAS

~~
I r+1
f-t
-

ROWS

lIAS

COLUMNS

REFRESH
COUNTER

8

B

ADDRESS
DRIVERS

--

I COL!CODE1J
R
512
0
W
128
64 K ARRAY
0
E
C

8

ADDRESS
BUS

7

IF, DN·CHIP REFRESH COUNTER, NOT USED
+5 V 64 K DYNAMIC RAMS

DP8408A
ONLY LS 7 BITS OF REFRESH COUNTER USED FOR THE 7 ROW ADDRESSES.
MSB NOT USED BUT CAN TOGGLE
TL/F/8408-6

FIGURE 1b. DP8408A with 128 Row X 512 Column 64k DRAM

CAS

~
I
ROWS

COLUMNS

12B ROWS
lOR

25~NR~re~ - .

~REFRESH

~I

~

1m
8
ADDRESS
ORIVERS

B

.....

+
B

ADDRESS
BUS

R
0
W
0 256
E

B

COUNTER

C

1

COLUMN DECODE
256

-

64K
ARRAY

+5V 64K
DYNAMIC
RAMS

0

IN 4MSI

I

OP8408A
ALL 8 BITS OF REFRESH COUNTER USED

I~ I

I

I
TL/F/8408-7

FIGURE 1c. DP8408A with 256 X 256 Column 64k DRAM

1-8

Functional Mode Descriptions
Note: All delay parameters stated in text refer to the DPB40BA. Substitute
the respective delay numbers for the DPB40B-2 or DPB40B-3 when
using these devices.

dress and RAS lines. For the load specified in the switching
characteristics of this data sheet, 10 ns is sufficient. Refer
to Figure 2.

MODES 0, 1, 2 - EXTERNALLY CONTROLLED
REFRESH

To perform externally controlled burst refresh, RASIN is toggled while RFSH is held low. The refresh counter increments with RASIN going low to high, so that the DRAM rows
are refreshed in succession by RASIN going high to low.

In this mode, the input address latches are disabled from
the address outputs and the refresh counter is enabled.
When RAS occurs, the enabled row in the DRAM is refreshed. In the Externally Controlled Refresh mode, all RAS
outputs are enabled following RASIN, and CAS is inhibited.
This refreshes the same row in all four banks. The refresh
counter increments when either RASIN or RFSH goes lowto-high after a refresh. RF I/O goes low when the count is
127 or 255, as set by End-of-Count (see Table III), with
RASIN and RFSH low. To reset the counter to all zeros, RF
I/O is set low through an external open-collector driver.

MODE 3 - EXTERNALLY CONTROLLED
ALL·RAS WRITE
This mode is useful at system initialization. The memory address is provided by the processor, which also performs the
incrementing. All four RAS outputs follow RASIN (supplied
by the processor), strobing the row address into the
DRAMs. R/C can now go low, while CASIN may be used to
control CAS (as in the Externally Controlled Access mode),
so that CAS strobes the column address contents into the
DRAMs. At this time WE should be low, causing the data to
be written into all four banks of DRAMs. At the end of the
write cycle, the input address is incremented and latched by
the DP8408A for the next write cycle.

During refresh, RASIN and RFSH must be skewed transitioning low such that the refresh address is valid on the
address outputs of the controller before the RAS outputs go
low. The amount of time that RFSH should go low before
RASIN does depends on the capacitive loading of the ad-

° INDICATES DYNAMIC RAM PARAMETERS

1-·-----IRCo-----~·1
INPUTS
RASIN

~

li-.----IRASINL----i-I--------------

I

-"':"-'1

1-IlIASINH-1

~I--~I---------+I~

miN AND R/~
OUTPUTS

I

I

RAS 0

I

ALLm'sLOW

---+1

I -I

tRDHNC

OLD COLUMNS

.+1

-------JI

COUNTER RESET

•

REFRESH COUNT.

I---IIRFLCT

RFIIO

II

IRASO---_-_~IIIIIIr-_-IRF-Pd-H-i------------

FIRFPdL

REFRESH COUNT.

REFRESH CTR

00-7

1- - - - - - -

-tRFpdH 1

1-IRPo-1
HAS 1,2, 3

11---7
-I

I
1
L ___ • _____________

I

i-IRLEOC

I

-I

~
I

r-IRHEOC

END OF COUNT
LOW IF •• 127, 255

COUNTER RESET
INPUT FROM
OPEN COLLECTOR
TL/F/8408-8

FIGURE 2_ External Control Refresh Cycle (MODES 0,1,2)

1-9


TL/F /8408-10

FIGURE 4a. Read Cycle Timing (Mode 4)

INPUTS

"INDICATES DYNAMIC RAM
PARAMETERS

ADS (ALEI

RIC

DRAM DATA IN
OUTPUTS

liAS 0.1.2.3

00·7

-~-+--J.----_4--.[_;;;;;'::;t-r--;....;--r_----....!..--"-----l

===~

TLiF/8408-11

FIGURE 4b. Write Cycle Timing (Mode 4)

1·11

Functional Mode Descriptions (Continued)
plexed address bus. After the row address has been held
for tRAH, (the Row-Address hold-time of the DRAM), the
column address is set up and then CAS occurs. This is all
performed automatically by the DP8408A in this mode.

MODE 5-AUTOMATIC ACCESS
The Auto Access mode has two advantages over the Externally Controlled Access mode, due to the fact that all outputs except WE are initiated from RASIN. First, inputs RIC
and CASIN are unnecessary. Secondly, because the output
control signals are derived internally from one input signal
(RASiN), timing-skew problems are reduced, thereby reducing memory access time substantially or allowing use of
slower DRAMs. The automatic access features of Mode 5
(and Mode 6) of the DP8408A make DRAM accessing appear essentially "static".
AUTOMATIC ACCESS CONTROL

Provided the input address is valid as ADS goes low, RASIN
can go low any time after ADS. This is because the selected
RAS occurs typically 27 ns later, by which time the row address is already valid on the address output of the
DP8408A. The Address Setup-Up time (tASA), is 0 ns on
most DRAMs. The DP8408A in this mode (with ADS and
RASIN edges simultaneously applied) produces a minimum
tASR of 0 ns. This is true provided the input address was
valid tASA before ADS went low (see Figure Sa).

The major disadvantage of DRAMs compared to static
RAMs is the complex timing involved. First, a RAS must
occur with the row address previously set up on the multi-

Next, the row address is disabled after tRAH (30 ns minimum); in most DRAMs, tRAH minimum is less than 30 ns.
The column address is then set up and tAse later, CAS

Timing Diagram
l-tADS----I ...
·-----tRICL------<~1
ADS

ADDRE~~WUTS/---<

>---+------..l---READ----I---++----

COLUMNS VALID
tASC

I

t=--

-

-WRITE--

tCAC·
DATA OUTPUT----------~------------<
1------tRAC·------1
TL/F/8408-12
>II

Indicates Dynamic RAM Parameters

FIGURE 5a. Modes 5, 6 Timing (CAS IN) High in Mode 6

1-12

Functional Mode Descriptions (Continued)
occurs. The only other control input required is WIN. When
a write cycle is required, WIN must go low at least 30 ns
before CAS is output low.

fast 16k or 64k DRAMs (which have a tRAH of IOns to 15
ns) in applications requiring fast access times; RASIN to
CAS is typically 105 ns.

This gives a total typical delay from: input address valid to
RASIN (15 ns); to RAS (27 ns); to rows held (50 ns); to
columns valid (25 ns); to CAS (23 ns) = 140 ns (that is, 125
ns from RASIN. All of these typical figures are for heavy
capacitive loading, of approximately 88 DRAMs. This mode
is therefore extremely fast. The external timing is greatly
simplified for the memory system designer: the only system
signal required is RASIN.

In this mode, the RIC pin is not used, but CASIN is used to
allow an extended CAS after RAS has already terminated.
Refer to Figure 5b. This is desirable with fast cycle-times
where RAS has to be terminated as soon as possible before
the next RAS begins (to meet the precharge time, or tRP,
requirements of the DRAM). CAS may then be held low by
CASIN to extend the data output valid time from the DRAM
to allow the system to read the data. CASIN subsequently
going high ends CAS. If this extended CAS is not required,
CASIN should be set high in Mode 6.

MODE 6-FAST AUTOMATIC ACCESS
The Fast Access mode is similar to Mode 5, but has a faster
tRAH of 20 ns, minimum. It therefore can only be used with

Timing Diagram
l-tAOS-I·,~~~~~-tRICl-~~~~-1

INPUTS
ADS

___ J
tCRS

OUTPUTS

00-7

-

-

WRITE -

-

-tOFF'

tCAC'

DATA DUTPUT---------------------r----------------------<

VALID (READI

1------tRAC'-----_1
"'Indicates Dynamic RAM Parameters

TL/F/8408-13

FIGURE 5b_ Mode 6 Timing, Extended CAS
1-13

I

Functional Mode Descriptions (Continued)
MODE 7-SET END·OF·COUNT

10

The End-of-Count can be externally selected In Mode 7,
using ADS to strobe In the respective value of Bl and BO
(see Table III). With Bl and BO the same EOC Is 127; with
Bl =0 and BO= 1, EOC is 255; and with Bl = 1 and BO=O,
EOC Is 127. This selected value of EOC will be used until
the next Mode 7 selection. At power-up the EOC is automatically set to 127 (Bl and BO set to 11).

5

•

-5

TABLE III. Mode 7
Bank Select
(Strobed by ADS)

End of Count
Selected

Bl

BO

0

0

127

0

1

255

1

0

127

1

1

127

V

/

0

V

-10

0

V
zoo

/

/'

400

600

800

1000

CpF
TL/F/8408-14

FIGURE 6. Change in Propagation Delay vs. Loading
Capacitance Relative to a 500 pF Load

Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
7.0V
Supply Voltage, Vee
Storage Temperature Range
-65'C to + 150'C
Input Voltage
5.5V
Output Current
150mA
lead Temperature (Soldering, 10 sec)
300'C

Maximum Power Dissipation" at 25'C
Cavity Package
Molded Package

3542mW
2633mW

Operating Conditions
Supply Voltage
Ambient Temperature

Vee
TA

Min
4.75
0

Max
5.25
+70

Units
V
'C

'Derate cavity package 23.6 mWre above 25'e; derate molded package
22.7 mW I'e above 25'e.

Electrical Characteristics Vee =
Symbol

5.0V ± 5%, O'C ,;; TA ,;; 70'C (unless otherwise noted) (Notes 2, 6)

Parameter

Conditions

Ve

Input Clamp Voltage

Vee = Min., Ie

IIHI

Input High Current for ADS, RIC only

VIN

IIH2

Input High Current for All Other Inputs'

VIN

IIRSI

Output load Current for RF 1/0

VIN

IICTl

Output load Current for RAS, CAS, WE

VIN

11L1

Input low Current for ADS, RIC only

VIN
VIN

=

Min

-12 mA

= 2.5V
= 2.5V
= 0.5V, Output High
= 0.5V, Chip Deselect
= 0.5V
= 0.5V

11L2

Input low Current for All Other Inputs"

VIL

Input low Threshold

VIH

Input High Threshold

VOLI

Output low Voltage"

VOL2

Output low Voltage for RF 1/0

= 20 mA
IOL = 10mA

VOH1

Output High Voltage'

IOH = -1 mA

2.4

VOH2

Output High Voltage for RF 110

IOH = - 100 /LA

2.4

110

Output High Drive Current'

VOUT = 0.6V (Note 3)

100

Output low Drive Current"

VOUT

I~-

'UL

TRI-STATE Output CUii6iit
(Address Outputs)

CAY'; YOUT s: 2.7V,
CS = 2.0V, Mode 4

Icc

Supply Current

Vee = Max.

Typ

Max

-0.6

-1.2

V

2.0

100

/LA

1.0

50

/LA

-1.5

-2.5

mA

-1.5

-2.5

mA

-0.1

-1.0

mA

-0.05

-0.5

mA

0.6

V

2.0
IOL

=

'Except RF 1/0 Output.

1-14

2.7V (Note 3)
-50

Units

V
0.3

0.5

0.3

0.5

V
V
V

3.5
3.5

V

-200

mA

200

mA

1.0

50

/LA

210

265

mA

Switching Characteristic DP8408A/DP8408·3
VCC = 5.0V ± 5%, O°C :;:;: T A :;:;: 70°C unless otherwise noted (Notes 2,4, 5). The output load capacitance is typical for 4 banks
of 22 DRAMs each of 88 DRAMs including trace capacitance. These values are: 00-07, CL = 500 pF; RASO-RAS3, CL = 150 pF;
WE, CL = 500 pF; CAS, CL = 600 pF, unless otherwise noted. See Figure 7for test load. Switches S1 and S2 are closed unless
otherwise noted, and R1 and R2 are 4.7 kO unless otherwise noted. Maximum propagation delays are specified with all outputs
switching.

Symbol

Access Parameter

8408-3

8408A

Conditions

Units

Min

Typ

Max

Min

Typ

Max

tRICL

RASIN to CAS Output Delay (Mode 5)

Figure5a

95

125

160

95

125

185

ns

tRICL

RASIN to CAS Output Delay (Mode 6)

Figures 5a, 5b

80

105

140

80

105

160

ns

tRICH

RASIN to CAS Output Delay (Mode 5)

Figure5a

40

48

60

40

48

70

ns

tRICH

RASIN to CAS Output Delay (Mode 6)

Figures 5a, 5b

50

63

80

50

63

95

ns

tRCDL

RAS to CAS Output Delay (Mode 5)

Figure5a

98

125

98

145

ns

tRCDL

RAS to CAS Output Delay (Mode 6)

Figures 5a, 5b

78

105

78

120

ns

tRCDH

RAS to CAS Output Delay (Mode 5)

Figure5a

27

40

27

40

ns

tRCDH

RAS to CAS Output Delay (Mode 6)

Figure5a

40

65

40

65

ns

tCCDH

CASIN to CAS Output Delay (Mode 6)

Figure5b

40

54

70

54

80

ns

Row Address Hold Time (Mode 5)

Figure5a

30

30

ns
ns

tRAH

40

tRAH

Row Address Hold Time (Mode 6)

Figures 5a, 5b

20

20

IASC

Column Address Setup Time (Mode 5)

Figure5a

8

8

ns

tASC

Column Address Setup Time (Mode 6)

Figures 5a, 5b

6

6

ns

tRCV

RASIN to Column Address Valid (Mode 5)

Figure5a

90

120

90

140

ns

tRCV

RASIN to Column Address Valid (Mode 6)

Figures 5a, 5b

75

105

75

120

ns

tRPDL

RASIN to RAS Delay

Figures 4a, 4b, 5a, 5b

20

27

35

20

27

40

ns

tRPDH

RASIN to RAS Delay

Figures 4a, 4b, 5a, 5b

15

23

32

15

23

37

ns

tAPDL

Address Input to Output Low Delay

Figures4~4b,5a,5b

25

40

25

46

ns

tAPDH

Address Input to Output High Delay

Figures4~4~

25

40

25

46

ns

tSPDL

Address Strobe to Address Output Low

Figures 4a, 4b,

40

60

40

70

ns

tSPDH

Address Strobe to Address Output High

Figures 4a, 4b,

40

60

40

70

tASA

Address Setup Time to ADS

Figures 4a, 4b, 5a, 5b

15

15

tAHA

Address Hold Time from ADS

Figures 4a, 4b, 5a, 5b

15

15

ns

tAOS

Address Strobe Pulse Width

Figures 4a, 4b, 5a, 5b

30

30

ns

IWPDL

WIN to WE Output Delay

Figure4b

15

25

30

15

25

35

ns

tWPDH

WIN to WE Output Delay

Figure4b

15

30

60

15

30

70

ns

tCRS

CASIN Setup Time to RASIN High (Mode 6)

Figure5b

35

tCPDL

CASIN to CAS Delay

Figure4b

32

41

68

32

41

77

tCPDH

CASIN to CAS Delay

Figure4b

25

39

50

25

39

60

ns

tRCC

Column Select to Column Address Valid

Figure 4a

40

58

40

67

ns

tRCR

Row Select to Row Address Valid

Figures 4a, 4b

40

58

40

67

ns

tRHA

Row Address Held from Column Select

Figure4a

tCCAS

RIC Low to CAS Low (Mode 4 Auto CAS)

Figure7a

65

90

(RIC low in Mode 4)

1-15

5a,5b

35

10

10

ns
ns

ns
ns

ns
ns

Switching Characteristics DP8408A/DP8408-3 (Continued)
VCC = 5.0V ± 5%, O·C s T A S 70·C unless otherwise noted (Notes 2, 4, 5). The output load capacitance is typical for 4 banks
of 22 DRAMs each of 88 DRAMs including trace capacitance. These values are: 00-07, CL = 500 pF; RASO-RAS3, CL = 150 pF;
WE, CL = 500 pF; CAS, CL = 600 pF, unless otherwise noted. See Figure 710r test load. Switches S1 and S2 are closed unless
otherwise noted, and R1 and R2 are 4.7 kO unless otherwise noted. Maximum propagation delays are specified with all outputs
switching.

Access Parameter

Symbol

8408-3

8408A

Conditions
Min

Typ

Max

Min

Typ

Units
Max

tOIFt

Maximum (tRPOL - tRHA)

See Mode 4 description

13

18

ns

tOlF2

Maximum (tRCC - tcpod

See Mode 4 description

13

18

ns

Refresh Parameter
tRC

Refresh Cycle Period

Figure 2

100

100

ns

tRASINL, H

Pulse Width of RASIN during Refresh

Figure 2

50

50

ns

tRFPOL

RASIN to RAS Delay during Refresh

Figure 2

35

50

70

35

50

80

ns

tRFPOH

RASIN to RAS Delay during Refresh

Figure 2

30

40

55

30

40

65

ns

tRFLCT

RFSH Low to Counter Address Valid

CS

47

60

47

70

ns

tRFHRV

RFSH High to Row Address Valid

Figure 2

45

60

45

70

ns

tROHNC

RAS High to New Count Valid

Figure 2

30

55

30

55

ns

tRLEOC

RASIN Low to End-of-Count Low

CL

=

50 pF, Figure 2

80

80

ns

tRHEOC

RASIN High to End-of-Count High

CL

=

50 pF, Figure 2

80

80

ns

tRST

Counter Reset Pulse Width

Figure 2

tcTL

RF 110 Low to Counter Outputs All Low

Figure 2

=

X, Figure 2

70

70

ns

100

100

ns

TRI-STATE Parameter
tZH

CS Low to Address Output High from Hi-Z

Figure 8
R1 = 3.5k, R2

=
=

tHZ

CS High to Address Output Hi-Z from High

CL
R2

tZL

CS Low to Address Output Low from Hi-Z

Figure 8
R1 = 3.5k, R2

=
=

=

1.5k

15 pF, Figure 8
1k, S1 open

=

1.5k

35

60

35

60

ns

20

40

20

40

ns

35

60

35

60

ns

tLZ

CS High to Address Output Hi-Z from Low

CL
R1

15 pF, Figure 8
1k, S2 open

25

50

25

50

ns

tHZH

CS Low to Control Output High from
Hi-Z High

Figure 8
R2 = 7500, S1 open

50

80

50

80

ns

tHHZ

CS High to Control Output Hi-Z High
from High

CL
R2

= 15 pF, Figure 8
= 7500, S1 open

40

75

40

75

ns

tHZL

CS Low to Control Output Low from
Hi-Z High

Figure 8
S1, S2 open

45

75

45

75

ns

tLHZ

CS High to Control Output Hi-Z High
from Low

CL
R2

50

80

50

80

ns

= 15pF,Figure8,
= 7500, S1 open

1-16

Switching Characteristics DP8408-2
VCC = 5.0V ±5%, O°C :s:; TA :s:; 70°C unless otherwise noted (Notes 2, 4, 5, 7). The output load capacitance is typical for 4
banks of 22 DRAMs each or 88 DRAMS including trace capacitance. These values are: 00-07, CL = 500 pF; RASO-RAS3, CL
= 150 pF, WE, CL = 500 pF; CAS, CL = 600 pF, unless otherwise noted. See Figure 7for test load. Switches Sl and S2 are
closed unless otherwise noted, and Rl and R2 are 4.7 k!1 unless otherwise noted. Maximum propagation delays are specified
with all outputs switching.
Symbol

Access Parameter

8408-2

Conditions

Units

Min

Typ

Max

tRICL

RASIN to CAS Output Delay (Mode 5)

Figure5a

75

100

130

ns

tRICL

RASIN to CAS Output Delay (Mode 6)

Figures 5a, 5b

65

90

115

ns

tRICH

RASIN to CAS Output Delay (Mode 5)

Figure5a

40

48

60

ns

tRICH

RASIN to CAS Output Delay (Mode 6)

Figures 5a, 8b

50

63

80

ns

tRCDL

RAS to CAS Output Delay (Mode 5)

Figure5a

75

100

ns

tRCDL

RAS to CAS Output Delay (Mode 6)

Figures 5a, 5b

65

85

ns

tRCDH

RAS to CAS Output Delay (Mode 5)

Figure5a

27

40

ns

tRCDH

RAS to CAS Output Delay (Mode 6)

Figure5a

40

65

ns

tCCDH

CASIN to CAS Output Delay (Mode 6)

Figure5b

40

54

70

ns

tRAH

Row Address Hold Time (Mode 5) (Note 7)

Figure5a

20

ns

tRAH

Row Address Hold Time (Mode 6) (Note 7)

Figures 5a, 5b

12

ns

tASC

Column Address Setup Time (Mode 5)

Figure5a

3

ns

tASC

Column Address Setup Time (Mode 6)

Figures 5a, 8b

3

ns

tRCV

RASIN to Column Address Valid (Mode 5)

Figure5a

tRCV

RASIN to Column Address Valid (Mode 6)

Figures 5a, 5b

70

90

ns

tRPDL

RASIN to RAS Delay

Figures 4a, 4b, 5a, 5b

20

27

35

ns

tRPDH

RASIN to RAS Delay

Figures 4a, 4b, 5a, 5b

15

23

32

ns

tAPDL

Address Input to Output Low Delay

Figures 4a, 4b, 5a, 5b

25

40

ns

80

105

ns

tAPDH

Address Input to Output High Delay

Figures 4a, 4b, 5a, 5b

25

40

ns

tSPDL

Address Strobe to Address Output Low

Figures 4a, 4b

40

60

ns

tSPDH

Address Strobe to Address Output High

Figures 4a, 4b

40

60

ns

tASA

Address Set-up Time to ADS

Figures 4a, 4b, 5a, 5b

tAHA

Address Hold Time from ADS

tADS

Address Strobe Pulse Width

tWPDL

15

ns

Figures 4a, 4b, 5a, 5b

15

ns

Figures 4a, 4b, 5a, 5b

30

WIN to WE Output Delay

Figure4b

15

25

30

tWPDH

WIN to WE Output Delay

Figure4b

15

30

60

teRS

CASIN Set-up Time to RASIN High (Mode 6)

Figure5b

35

tCPDL

CASIN to CAS Delay (RIC low in Mode 4)

Figure4b

32

41

58

tCPDH

CASIN to CAS Delay (RIC low in Mode 4)

Figure4b

25

39

50

ns

tRCC

Column Select to Column Address Valid

Figure4a

40

58

ns

tRCR

Row Select to Row Address Valid

Figures 4a, 4b

40

58

ns

tRHA

Row Address Held from Column Select

Figure4a

tCCAS

RIC Low to CAS Low (Mode 4 Auto CAS)

Figure 7a

55

75

ns

1-17

ns
ns
ns
ns

10

ns

ns

Switching Characteristics DP8408-2

(Continued)

VCC = 5.0V ±5%, O°C ,;; TA ,;; 70°C unless otherwise noted (Notes 2, 4, 5, 7). The output load capacitance is typical for 4
banks of 22 DRAMs each or 88 DRAMS including trace capacitance. These values are: 00-07, CL = 500 pF; RASO-RAS3, CL
= 150 pF, WE, CL = 500 pF; CAS, CL = 600 pF, unless otherwise noted. See Figure 7for test load. Switches S1 and S2 are
closed unless otherwise noted, and R1 and R2 are 4.7 kO unless otherwise noted. Maximum propagation delays are specified
with all outputs switching.
Symbol

Access Parameter

8408-2

Conditions
Min

Typ

Units
Max

tOlF1

Maximum (tRPOL - tRHA)

See Mode 4 description

13

ns

tOlF2

Maximum (tRCC - tcpoLl

See Mode 4 description

13

ns

Refresh Parameter
tRC

Refresh Cycle Period

Figure 2

100

tRASINl. H

Pulse Width of RASIN during Refresh

Figure 2

50

tRFPOL

RASIN to RAS Delay during Refresh

Figure 2

35

50

70

ns

tRFPOH

RASIN to RAS Delay during Refresh

Figure 2

30

40

55

ns
ns

=

ns

tRFlCT

RFSH Low to Counter Address Valid

CS

47

60

tRFHRV

RFSH High to Row Address Valid

Figure 2

45

60

ns

tROHNC

RAS High to New Count Valid

Figure 2

30

55

ns

tRlEOC

RASIN Low to End-of-Count Low

CL

80

ns

tRHEOC

RASIN High to End-of-Count High

Cl

80

ns

tRST

Counter Reset Pulse Width

Figure 2

tCTL

RF I/O Low to Counter Outputs All Low

Figure 2

=
=

X, Figure 2

ns

50 pF, Figure 2
50 pF, Figure 2
70

ns
100

ns

35

60

ns

20

40

ns

35

60

ns

25

50

ns

50

80

ns

40

75

ns

45

75

ns

50

80

ns

TRI-STATE Parameter
tZH

CS Low to Address Output High from Hi-Z

Figures g, 12
R1 = 3.5k, R2

=
=

tHZ

CS High to Address Output Hi-Z from High

CL
R2

tZl

CS Low to Address Output Low from Hi-Z

Figures 9, 12
R1 = 3.5k, R2

=
=

=

1.5k

15 pF, Figures 9, 12
1k,S1 open

=

1.5k

15 pF, Figures 9, 12
1k,S20pen

tLZ

CS High to Address Output Hi-Z from Low

CL
R1

tHZH

CS Low to Control Output High from
Hi-ZHigh

Figures 9, 12
R2 = 7500, S1 open

tHHZ

CS High to Control Output Hi-Z High
from High

CL
R2

tHZL

CS Low to Control Output Low from
Hi-Z High

Figure 12,
S1, S20pen

tLHZ

CS High to Control Output Hi-Z High
from Low

CL
R2

=
=

=
=

1-18

15 pF, Figures 9, 12
7500, S1 open

15 pF, Figure 12,
7500, S1 open

Input Capacitance TA =
Symbol

25'C (Notes 2, 6)

Parameter

Conditione

Min

Typ

Max

Units

CIN

Input Capacitance ADS, R/r;

8

pF

CIN

Input Capacitance All Other Inputs

5

pF

Not. 1: "Absolute Maximum Ratings" are the values beyond which the safety of the device cannot be guaranteed. They are not meant to Imply that the device
should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: All typical values are for TA = 25'C and Vcc = 5.0V.
Note 3: This test is provided as a monitor of Driver output source and sink current capability. Caution should be exercised in testing this parameter. In testing these
parameters. a 150 resistor should be placed in series with each output under test. One output should be tested at a time and test time should not exceed 1 second.

Note 4: Input pulse OV to 3.0V, tR
for High and O.BV for Low.

= tF = 2.5 ns, f = 2.5 MHz, tpw = 200 ns. Input reference pOint on AC measurements is 1.5V. Output reference pOints are 2.7V

Note 5: The load capacitance on RF 110 should not exceed 50 pF.
Note 6: Applies to all DP640BA versions unless otherwise specified.
Note 7: The DP8408-2 device can only be used with memory devices that meet the tRAH specification indicated.

~.
S1 - /

I

f ---o TEST POINT

OUTPUT
UNDER o--"tN...........- -.....
TEST

15\2

S2

~

"U"

TL/F/8408-15

FIGURE 7. Output Load Circuit

Timing Waveform

INPUT

OV

3.OV_--------___..

1.5V J I

----.I

\,.5V
tHZ

VOH

-tHHZ=-.l

OUTPUT VOL

I ,,-:

,.;;;,,;-~~±:==O.5V

-tHZH!--

-1

HIGH Z: _ _ _':"'-~ 2.7V

------O.5V
-!ILHZ

I tlZ

:=-T

VOH

tZH 11""__- - VOL

'k'~O:::.8V:...._..;,,;

IHZL

I--

III
TL/F/B408-16

FIGURES

Applications
included for systems using byte-writing. The refresh clock
RFCK may be divided down from either RGCK using an IC
counter such as the DM74LS393 or better still, the
DP84300 Programmable Refresh Timer. The DP84300 can
provide RFCK periods ranging from 15.4 !,-S to 15.6 !'-S
based on the input clock of 2 to 10 MHz. Figure 9b shows
the general timing diagram for interfacing the DP8408A to
different microprocessors using the interface controller
DP843X2.

If external control is preferred, the DP8408A may be used in
Modes 0 or 4, as in Figure 3.
If basic auto access and refresh are required, then in cases
where the user requires the minimum of external complexity,
Modes 0 and 5 are ideal, as shown in Figure 9a. The
DP843X2 is used to provide proper arbitration between
memory access and refresh. This chip supplies all the nec·
essary control signals to the processor as well as the
DP8408A. Furthermore, two separate CAS outputs are also

1-19

I

Applications
•

(Continued)

.r

16·BIT MICROPROCESSOR DATA BUS

MICROPROCESSOR ADDRESS BUS

AOOR

~

ST~~~: t-....

~

CO·6,7
' - - - - Bl
I
-

ADDRESS
DECODER

I I I

--r-------...

::

lSELECT
W~Tt

~~~7~:E~CE~~~~'

FOR VERY FAST MICRO·
PROCESSORS

~:-

~

CAS -

t

II

*-----~H

AO-6,7

I

om U

~~.~.~!-I~·I~~,~.~I~I:..,~·...

I:aWER

liAS_

+ +J.

-:J..

_
,-------

.

II I
I
I

~
mL

WI: rt"---t'1!W~E_J:~

RF 110 M2 Ml MO

e- V

W£

-

L..--++--tmm

..

AD-6,7

AO·6,7

I

tTHE SELECT WAITINPUT
TO THE OPB43X2 CHIP
INSERTS A WAIT STATE

I

...c::::;-

p L 1-1--0
~w
n
_

1,.... '......
_t........................'.....,_
OP84XX1

~ASL

,•••

~ ~ ~~ II

_" :

R/WW'~±:==:::;-+-t-1~@==t+t1W11l
r- r---. I

-::

~

IADS

MICROPROCEs:~:CKt-t----++-r+~e-

r--

AO·6,7

L---J~CASU

t-_ _ _ _r--_-t~

- - - +....

UPPER BYTE
LOWER BYTE

...&....--,1+------ .

RAMS MAY BE 16k OR 64k

I ..__...
..__-._-+!RO-6,7
...-------,RAM ADDRESS BUS
1-___
IIIP

r---O-lA~JA--;;;;

----=m U"
uASL-

u:m

BYTE

L-._ _....!-_ _....J "0""1"

-------.J

OM

t-=====t"i-r
748244 INECESSARY IF INSTRUCTIONS INCLUDE ""W:;;,;;,,;;.L..;:S::.EL:,:EC;;,;T..;:L::.OW::.:E::.;R.::B,;,;YT.:.E_ _ _ _ _ _ _ _~
t-======~..J

m

-",W=U::...;S::,EL:,:E::;CT'-.:U::.PP:.:E:::,R,:,BY:.:,T:.E

BYTE·WRITING, OTHERWISE USE
DIRECTLY
FROM THE DPB408A TO THE RAMS.

I-

NECESSARY IF MORE THAN ONE BANK __ ' - - - t - - - - - - - - - - - '
TL/F/B40B-17

FIGURE 9a. Connecting the DP8408A between the 16·Blt Microprocessor and Memory

1-20

Applications

(Continued)

1-=

HIDDEN
REFRESH--

I

I

I-MEMORY CYCLE -

CYCLE

I

---- MEMORY CYCLE

~

DP84300 MINIMIZES lOW TIME TO

20 CLOCKS MAXIMIZING CHANCE OF
HIDDEN REFRESH

RFCK

~IT _ _

FORCED

---- REFRESH -

ACCESS
I.MEMORY CYClE- __ ElSEWHERE_

n

~

~

______ _ _
~

~~

__

n

~

~

______

*T IS

MICROPRO'~ESSOR'S

CLOCK

~L -

~I

PERIO~

TL/F 18408-18

FIGURE 9b. DP8408A Auto Refresh

1-21

I ~Nat1onal
Semiconductor
~ ~

DP8409A Multi-Mode Dynamic RAM ControllerIDriver
General Description

Operational Features

Dynamic memory system designs, which formerly required
several support chips to drive the memory array, can now
be implemented with a single IC ... the DP8409A MultiMode Dynamic RAM Controller/Driver. The DP8409A is capable of driving all 16k and 64k Dynamic RAMs (DRAMs) as
well as 256k DRAMs. Since the DP8409A is a one-chip solution (including capacitive-load drivers), It minimizes propagation delay skews, the major performance disadvantage of
multiple-chip memory drive and control.

• All DRAM drive functions on one chip-minimizes skew
on outputs, maximizes AC peformance
• On-chip capacitive-load drives (specified to drive up to
88 DRAMs)
• Drives directly all 16k, 64k, and 256k DRAMs
• Capable of addressing 64k, 256k, or 1M words
• Propagation delays of 25 ns typical at 500 pF load
• CAS goes low automatically aiter column addresses are
valid If desired
• Auto Access mode provides RAS, row to column select, then CAS automatically and fast
• WE follows WJiiI unconditionally-offering READ,
WRITE or READ-MODIFY-WRITE cycles
• On-chip 9-bit refresh counter with selectable End-ofCount (127, 255 or 511)
• End-of-Count indicated by RF I/O pin going low at 127,
255 or 511
• Low input on RF I/O resets 9-bit refresh counter
• CAS inhibited during refresh cycle
• Fall-through latches on address inputs controlled by
ADS
• TRI-STATE outputs allow multi-controller addressing of
memory
• Control output signals go high-impedance logic "1"
when disabled for memory sharing
• Power-up: counter reset, control signals high, address
outputs TRI-STATE, and End-of-Count set to 127

The DP8409A's 8 modes of operation offer a wide selection
of DRAM control capabilities. Memory access may be controlled externally or on-chip automatically; an on-chip refresh counter makes refreshing (either externally or automatically controlled) less complicated; and automatic memory initialization is both simple and fast.
The DP8409A is a 48-pin DRAM Controller/Driver with 9
multiplexed address outputs and 6 control signals. It consists of two 9-bit address latches, a 9-bit refresh counter,
and control logic. All output drivers are capable of driving
500 pF loads with propagation delays of 25 ns. The
DP8409A timing parameters are specified driving the typical
load capacitance of 88 DRAMs, including trace capacitance.
The DP8409A has 3 mode-control pins: M2, Ml, and MO,
where M2 is in general REFRESH. These 3 pins select 8
modes of operation. Inputs B1 and BO in the memory access modes (M2 = 1), are select inputs which select one of
four RAS outputs. During normal access, the 9 address outputs can be selected from the Row Address Latch or the
Column Address Latch. During refresh, the 9-bit on-Chip refresh counter is enabled onto the address bus and in this
mode all RAS outputs are selected, while CAS is inhibited.
The DP8409A can drive up to 4 banks of DRAMs, with each
bank comprised of 16k's, 64k's, or 256k's. Control signal
outputs RAS, ~, and WE are provided with the same
drive capability. Each RAS output drives one bank of
DRAMs so that the four RAS outputs are used to select the
banks, while ~, WE, and the multiplexed addresses can
be connected to all of the banks of DRAMs. This leaves the
non-selected banks in the standby mode (less than one
tenth of the operating power) with the data outputs in TRISTATE®. Only the bank with its associated RAS low will be
written to or read from.
SYSTEM

RAM
CONTROL

CONTROL

~
10

SYSTEM

20

SYSTEM
ADDRESS

6

0P8409A
DYNAMIC RAM
CONTROLLERI
DRIVER

500pF DRIVE

MEMORY

9

...
RAm

ADDRESS

Mode Features
• 8 modes of operation: 3 access, 3 refresh, and 2
set-up
• 2 externally controlled modes: 1 access and 1 refresh
(Modes 0, 4)
• 2 auto-access modes RAS - R/-e - ~ automatic,
with tRAH = 20 or 30 ns minimum (Modes 5, 6)
• Auto-access mode allows Hidden Refreshing (Mode 5)
• Forced Refresh requested on RF I/O if no Hidden Refresh (Mode 5)
• Forced Refresh performed after system acknowledge of
request (Mode 1)
• Automatic Burst Refresh mode stops at End-of-Count
of 127, 255, or 511 (Mode 2)
• 2 AII-RAS Acces modes externally or automatically controlled for memory initialization (Modes 3a, 3b)
• Automatic AII·RAS mode with external 8-bit counter
frees system for other set-up routines (Mode 3a)
• End-of-Count value of Refresh Counter set by B 1 and
BO (Mode 7)

16k. 64k. OR
256k DYNAMIC
RAM BANKS
TL/F/8409-1

1-22

Block and Connection Diagrams

68 Pin PCC

I~

RO-8

...

---~

'" i
9 8

1--+1>-••'-8

CD-8

10

6

5

•

3

2

1 68 67 66 65 64 63 62 61
60

ADS 11

59

RO 12

58 Ql

CO 13

57 Q2

Rl 14

56 Q3

Cl

55 Q.

15

R2 16

5. GND

C2 17

53 GHD

GND 18

52 Q5

GHO 19

51 Yee

R3 20

50 Yee

m,

C3 21

.9 Q6

1101

R. 22
C. 23

.7 Q8

R5 24

.6

C5 25

45 RA53

110,

81
80

7

1100

.a

Q7

CAs

~
~
v~~~~n~~~M~M~~~~~

CS-.

CAl

mIII_
RIC IRFeK) ---...

emil (ROCK)

_

TL/F/8409-3

II/Iii

'Ill!
RFI/D

M2(iIFiiIl

M1

Dual-In-Llne Package

.0
TL/F/8409-2

Order Number DP84D9AD, DP84D9AN,
DP84D9AN-3 or DP84D9AV-2
See NS Package Number D48A, N48A or V68A

DP84D9A

Pin Definitions
Vee, GND, GN~Vcc = 5V ±5%. The three supply pins
have been assigned to the center of the package to reduce
voltage drops, both DC and AC. There are also two ground
pins to reduce the low level noise. The second ground pin is
located two pins from Vee, so that decoupling capacitors
can be inserted directly next to these pins. It is important to
adequately decouple this device, due to the high switching
currents that will occur when all 9 address bits change in the
same direction simultaneously. A recommended solution
would be a 1 ,.,.F multilayer ceramic capaCitor in parallel with
a low-voltage tantalum capaCitor, both connected as close
as possible to pins 36 and 38 to reduce lead inductance.
See figure below.
VCC(PIN 36)

Top View
RD-R8: Row Address Inputs.
CD-C8: Column Address Inputs.

QD-Q8: Multiplexed Address Outputs--Selected from
the Row Address Input Latch, the Column Address Input
Latch, or the Refresh Counter.·
RASIN: Row Address Strobe Input-Enables selected
RASn output when M2 (RFSH) is high, or all RASn outputs
when RFSH is low.

o------.. ....----.,
T.L
I
_
~

'MULTILAYER

'TANTALUM

CERAM(C

GND (PINS 38. 13)

TL/F/8409-5

0

RIC (RFCK)-In Auto-Refresh Mode this pin is the external Refresh Clock Input: one refresh cycle has to be performed each clock period. In all other modes it is Row/Column Select Input: selects either the row or column address
input latch onto the output bus.

TL/F/8409-4

'Capacitor values should be chosen depending on the particular application.

1-23

•

Pin Definitions (Continued)
TABLE I. DP8409A Mode Select Options
Mode

(RFSH)
M2

M1

MO

0

0

0

0

Externally Controlled Refresh

RFIIO =

1

0

0

1

Auto Refresh-Forced

RF 1/0 = Refresh Request (RFRO)

2

0

1

0

Internal Auto Burst Refresh

RFIIO =

Mode of Operation

Conditions

EOC
EOC

3a

0

1

1

All RAS Auto Write

RF I/O = EOC; All RAS Active

3b

0

1

1

Externally Controlled All RAS Access

All RAS Active

4

1

0

0

Externally Controlled Access

Active RAS Defined by Table II

5

1

0

1

Auto Access, Slow tRAH, Hidden Refresh

Active RAS Defined by Table II

6

1

1

0

Auto Access, Fast tRAH

Active RAS Defined by Table II

7

1

1

1

Set End of Count

See Table III for Mode 7
manently high. Otherwise ADS must go low while the addresses are still valid.

CASIN (RGCK)-In Auto-Refresh Mode, Auto Burst Mode,
and AII-RAS Auto-Write Mode, this pin is the RAS Generator
Clock input. In all other modes it is CASilii (Column Address
Strobe Input), which inhibits CAS output when high in
Modes 4 and 3b. In Mode 6 it can be used to prolong (;AS
output.

In normal memory access operation, RASIN and RIC; are
initially high. When the address inputs are enabled into the
address latches, the row addresses appear on the 0 outputs. The address strobe also inputs the bank-select address, (BO and Bl). If C;S is low, all outputs are enabled.
When C;S is transitioned high, the address outputs go TRISTATE and the control outputs first go high through a low
impedance, and then are held by an on-chip high impedance. This allows output paralleling with other DP8409As for
multi-addressing. All outputs go active about 50 ns after the
chip is selected again. If C;S is high, and a refresh cycle
begins, all the outputs become active until the end of the
refresh cycle.

ADS: Address (Latch) Strobe Input-flow Address, Column Address, and Bank Select Latches are fall-through with
ADS high; Latches on high-to-Iow transition.
CS: Chip Select Input-The TRI-STATE mode will Address
Outputs and puts the control signal into a high-impedance
logic "1" state when high (unless refreshing in one of the
Refresh Modes). Enables all outputs when low.
MO, M1, M2: Mode Control Input_These 3 control pins
determine the 8 major modes of operation of the DP8409A
as depicted in Table I.

DRIVE CAPABILITY

RF I/O-The 110 pin functions as a Reset Counter Input
when set low from an external open-collector gate, or as a
flag output. The flag goes active-low in Modes 0 and 2 when
the End-of-Count output is at 127, 255, or 511 (see
Table III). In Auto-Refresh Mode it is the Refresh Request
output.

The DP8409A has timing parameters that are specified with
up to 600 pF loads. In a typical memory system this is equivalent to about 88, 5V-only DRAMs, with trace lengths kept
to a minimum. Therefore, the chip can drive four banks each
of 16 or 22 bits, or two banks of 32 or 39 bits, or one bank of
64 or 72 bits.

WIN: Write Enable Input.

Less loading will slightly reduce the timing parameters, and
more loading will increase the timing parameters, according
to the graph of Figure 10. The AC performance parameters
are specified with the typical load capaCitance of 88
DRAMs. This graph can be used to extrapolate the variations expected with other loading.

WE: Write Enable Output-8uffered output from WIN.·
CAS: Column Address Strobe Output-In Modes 3a, 5,
and 6, c:AS transitions low following valid column address.
In Modes 3b and 4, it goes low alterRte goes low, or follows CASIN going low if RIC is already low. CAS is high
duing refresh.·

Because of distributed trace capaCitance and inductance
and DRAM input capacitance, current spikes can be created, causing overshoots and undershoots at the DRAM inputs that can change the contents of the DRAMs or even
destroy them. To remove these spikes, a damping resistor
(low inductance, carbon) can be inserted between the
DP8409A driver outputs and the DRAMs, as close as possible to the DP8409A. The values of the damping resistors
may differ between the different control outputs; RASs,
c:AS, O's, and WE. The damping resistors should be determined by the first prototypes (not wire-wrapped due to the
larger distributed capacitance and inductance). The best
values for the damping resistors are the critical values giving
a critically damped transition on the control outputs. Typical
values for the damping resistors will be between 150 and
1000, the lower the loading the higher the value. (For more
information, see AN-305 "Precautions to Take When Driving Memories.")

RAS 0-3: Row Address Strobe Output-Selects a memory bank decoded from Bl and BO (see Table II), if RFSR is
high. If RFSH is low, all banks are selected.·
BO, B1: Bank Select Input-Strobed by ADS. Decoded to
enable one of the RAS outputs when RASIN goes low. Also
used to define End-of-Count in Mode 7 (Table III).

Conditions for All Modes
INPUT ADDRESSING
The address block consists of a row-address latch, a column-address latch, and a resettable refresh counter. The
address latches are fall-through when ADS is high and latch
when ADS goes low. If the address bus contains valid addresses until after the valid address time, ADS can be per-

1-24

Conditions for All Modes (Continued)
with no on-RAM refresh counter. The DP8409A can drive all
three configurations, and at the same time allows them all to
be interchangeable (as shown in Figures lb and Ie), providing maximum flexibility in the choice of DRAMs. Since the
9-bit on-chip refresh counter can be used as a 7-bit refresh
counter for the 128-row configuration, or as an 8-bit refresh
counter for the 256-row configuration, the on-RAM refresh
counter (if present) is never used. As long as 128 rows are
refreshed every 2 rns (i.e. 256 rows in 4 rns) all DRAM types
are correctly refreshed.

DP8409A DRIVING ANY 16k OR 64k DRAMs
The DP8409A can drive any 16k or 64k DRAMs. All 16k
DRAMs are basically the same configuration, including the
newer 5V-only version. Hence, in most applications, different manufacturers' DRAMs are interchangeable (for the
same supply-rail chips), and the DP8409A can drive all 16k
DRAMs (see Figure la).
There are three basic configurations for the 5V-only 64k
DRAMs: a 128-row by 512-column array with an on-RAM
refresh counter, a 128-row by 512-column array with no onRAM refresh counter, and a 256-row by 256-column array

DP8409A Interface between System and DRAM Banks

I~
r;.1
ROWS

COLUMNS

r-t

CAS
WE

m
AODRESS
DRIVERS

....,

7

7

COL.!CODE

R

128

W 128

16K
ARRAY

0

0

7

ADDRESS
8US

E
C

IJ

7

REFRESH
COUNTER

+12Vor +5V 16K DYNAMIC RAMS
DP8409A
TLiF/B409-6

FIGURE 1a. DP8409A with any 16k DRAMs
[~ LATCHES 8 COLUMN ADDRESSES

HE 7 DW+1 COLUMN ADDRESSlIAS LATCSR

W

~.

-

ROWS

I~'''HI''':

rt

REFRESH
COUNTER

8

8

DRIVERS.

8

ADORES?'
8US

ICOL!CDDEJ
R
512
0
W
128
64K ARRAY
0
E
C

~
IF. ON·CHIP REFRESH COUNTER, NOT USED
+5V 64K DYNAMIC RAMS

DP8409A

ONLY LS 7 81TS OF REFRESH COUNTER USED FOR THE 7 ROW ADDRESSES.
MSB NOT USED BUT CAN TOGGLE
TLiF/8409-7

FIGURE 1b. DP8409A with 128 Row x 512 Column 64k DRAM

•

CAS

~~
ROWS

I ""...
128 ROWS
(OR

25~NR~:~ -

~ ~ _.7
,•

DRIVERS

B

B
AODRESS
BUS

-.
8

1
COLUMN DECODE

R

-t~EFRESH
COUNTER ~

256

0

W

0 256
E
C

I

j.

64K
ARRAY

+5V 64K
DYNAMIC
RAMS

0

IN 4MS)

D
E

DP8409A
ALL 8 BITS DF REFRESH CDUNTER USED

TL/F /8409-8

FIGURE 1c. DP8409A with 256 x 256 Column 64k DRAM

1-25

DP8409A Functional Mode
Descriptions

Conditions for All Modes (Continued)
When the DP8409A is in a refresh mode, the RF I/O pin
indicates that the on-chip refresh counter has reached its
end-of-count. This end-of-count is selectable as 127, 255 or
512 to accommodate 16k, 64k or 256k DRAMs. Although
the end-of-count may be chosen to be any of these, the
counter always counts to 511 before rolling over to zero.

Note: All delay parameters slated in text refer to the DP8409A. Substitute
the respective delay numbers for the DP8409·2 or DP8409·3 when
using these devices.

MODE O-EXTERNALLY CONTROLLED REFRESH

Figure 2 is the Externally Controlled Refresh Timing. In this
mode, the input address latches are disabled from the address outputs and the refresh counter is enabled. When
RAS occurs, the enabled row in the DRAM is refreshed. In
the Externally Controlled Refresh mode, all RAS outputs are
enabled following RASIN, and CAS is inhibited. This refreshes the same row in all four banks. The refresh counter increments when either RASIN or RFSH goes low-to-high after a
refresh. RF 1/0 goes low when the count is 127, 255, or
511, as set by End-of-Count (see Table III), with RASIN and
RFSH low. To reset the counter to all zeros, RF I/O is set
low through an external open-collector driver.

READ, WRITE, AND READ-MODIFY-WRITE CYCLES

The output signal, WE, determines what type of memory
access cycle the memory will perform. If WE is kept high
while CAS goes low, a read cycle occurs. If WE goes low
before CAS goes low, a write cycle occurs and data at 01
(DRAM input data) is written into the DRAM as CAS goes
low. If WE goes low later than tewD after CAS goes low, first
a read occurs and DO (DRAM output data) becomes valid;
then data 01 is written into the same address in the DRAM
when WE goes low. In this read-modify-write case, 01 and
DO cannot be linked together. The type of cycle is therefore
controlled by WE, which follows WIN.

During refresh, RASIN and RFSH must be skewed transitioning low such that the refresh address is valid on the
address outputs of the controller before the RAS outputs go
low. The amount of time that RFSH should go low before
RASIN does depends on the capacitive loading of the address and RAS lines. For the load specified in the switching
characteristics of this data sheet, IOns is sufficient. Refer
to Figure 2.
To perform externally controlled burst refresh, RASIN is toggled while RFSH is held low. The refresh counter increments with RASIN going low to high, so that the DRAM rows
are refreshed in succession by RASIN going high to low.

POWER-UP INITIALIZE

When Vee is first applied to the DP8409A, an initialize pulse
clears the refresh counter, the internal control flip-flops, and
set the End-of-Count of the refresh counter to 127 (which
may be changed via Mode 7). As Vee increases to about
2.3V, it holds the output control signals at a level of one
Schottky diode-drop below Vee, and the output address to
TRI-STATE. As Vee increases above 2.3V, control of these
outputs is granted to the system.

INPUTS

RASiN

CASiN AND Rtf
OUTPUTS

RASD

RAS

1. 2. 3

tROHNC
REFRESH CTR

COUNTER RESET

00·8

~!=!!O

REFRESH COUNT n

,L

_________________

I-IRLEOC
• INDICATES DYNAMIC RAM PARAMETERS

/

-\

~

\- tRHEOC

END OF COUNT
LOW IF 0=127, 255, 511

FIGURE 2. External Control Refresh Cycle (Mode 0)

1-26

COUNTER RESET
INPUT FROM

OPEN COLLECTOR

TL/F/8409-9

DP8409A Functional Mode Descriptions (Continued)
DRAMs. An external RiiJl Generator Clock (RGCK) is required for this function. It is fed to the CASIN (RGCK) pin,
and may be up to 10 MHz. Whenever M2 goes low (inducing
a forced refresh), RiiJl remains high for one to two periods
of RGCK, depending on when M2 goes low relative to the
high-to-Iow triggering edge of RGCK; RiiJl then goes low for
two periods, performing a refresh on all banks. In order to
obtain the minimum delay from M2 going low to RAS going
low, M2 should go low tRFSRG before the next falling edge
of RGCK. The Refresh Request on RF 1/0 is terminated as
RiiJl begins, so that by the time the system has acknowledged the removal of the request and disabled its Acknowledge, (I.e., M2 goes high), Refresh AAS will have ended,
and normal operations can begin again in the Automatic
Access mode (Mode 5). If It Is desired that Refresh mend
in less than 2 periods of RGCK from the time m went low,
then M2 may be high earlier than tRQHRF after RGCK goes
low and AAS will go high tRFRH after M2, if
is low. If
is high, the AAS will go high after 25 ns after M2 goes high.
To allow the forced refresh, the system will have been inactive for about 4 periods of RGCK, which can be as fast as
400 ns every RFCK cycle. To guarantee a refresh of 128
rows every 2 ms, a period of up to 16 /Ls is required for
RFCK. In other words, the system may be down for as little
as 400 ns every 16 /Ls, or 2.5% of the time. Although this is
not excessive, it may be preferable to perform a Hidden
Refresh each RFCK cycle, which is allowed while still in the
Auto-Access mode, (Mode 5).

MODE 1-AUTOMATIC FORCED REFRESH
In Mode 1, the R/~ (RFCK) pin becomes RFCK (refresh
cycle clock), instead of R/~, and CAS remains high. If
RFCK is kept permanently high, then whenever M2 (RFSH)
goes low, an externally controlled refresh will occur and all
RiiJl outputs will follow ~, strobing the refresh counter
contents to the DRAMs. The RF 1/0 pin will always output
high, but when set low externally through an open-collector
driver, the refresh counter resets as normal. This externally
controlled method may be preferred when operating in the
Automatic Access mode (Mode 5), where hidden or forced
refreshing is undesirable, but refreshing is still necessary.
If RFCK Is an Input clock signal, one (and only one) refresh
cycle must take place every RFCK cycle. Refer to Figure 9.
If a hidden refresh does not occur while RFCK Is high, In
Mode 5, then RF 1/0 (Refresh Request) goes low Immedlately after RFCK goes low, Indicating to the system that a
forced refresh Is requested. The system must allow a forced
refresh to take place while RFCK is low (refer to Figure 9).
The Refresh Request signal on RF I/O may be connected
to a Hoid or Bus Request input to the system. The system
acknowledges the Hoid or Bus Request when ready, and
outputs Hold Acknowledge or Bus Request Acknowledge. If
this Is connected to the M2 (RFSH) pin, a forced-refresh
cycle will be initiated by the DP8409A, and RiiJl will be internally generated on all four RiiJl outputs, to strobe the refresh counter contents on the address outputs into all the

es

c
~
~
_

es

RFCK

r--

'RBCKl

I --l

r-IRBCKH

RGCK

80861'6832 REMOVE ACKNOWLEDGE
88OB0 REMOVES BRANT (MODE 5)

M2(H)

RF 110 (H)

mo.,.2.al

\

j

\..

QO·8

f--'FRQl

I

~p ACCESS
J
TO SELECTED BANK

\ I

I

\

~"'--C-Ol-S--'>B<--C-OLS--':"

,-_R_EF_RE_SH_C_O_UN_TER
__

~p ACCESS TO
SELECTED BANKS

>E)00C

f-- 'RFLCT

LS
-

TLIF/8409-10

FIGURE 3. DP8409A Performing a Forced Refresh (Mode 5 -+ 1 -+ 5) with Various Microprocessors

1-27

•
I

oct
~

DP8409A Functional Mode Descriptions (Continued)

ex>
Il.

C

DRAMS

t

Tns

PROCESSOR ACTS
AFTER INTERRUPT
MODE

MODE 2 :

RGCK

RAS 0-3

RF 110 (EOC)
TLlF/8409-11

FIGURE 4. Auto-Burst Mode, Mode 2
corresponding check bits for error detection and correction).
This requires writing the same data to each location of
memory (every row of each column of each bank). All RAS
outputs are activated, as in refresh, and so are CAS and
WE. To write to all four banks simultaneously, every row is
strobed in each column, in sequence, until data has been
written to all locations.
To select this mode, Bl and BO must have previously been
set to 00, 01, or lOin Mode 7, depending on the DRAM size.
For example, for 16k DRAMs, 81 and 80 are 00. For 64k
DRAMs, 81 and 80 are 01, so that for the configuration of
Figure 1b, the 8 refresh counter bits are strobed by RAS into
the 7 row addresses and the ninth column address. After
this Automatic-Write process, Bland 80 must be set again
in Mode 7 to 00 to set End-of-Count to 127. For the configuration of Figure 1e, 81 and 80 set to 01 will work for Automatic-Write and End-of-Count equals 255.
In this mode, R/C is disabled, WE is permanently enabled
low, and CASIN (RGCK) becomes RGCK. RF I/O goes low
whenever the refresh counter is 127, 255, or 511 (as set by
End-ot-Count in Mode 7), and the RAS outputs are active.

MODE 2-AUTOMATIC BURST REFRESH
This mode is normally used before and/or after a DMA operation to ensure that all rows remain refreshed, provided
the DMA transfer takes less than 2 ms (see Figure 4). When
the DP8409A enters this mode, CASIN (RGCK) becomes
the RAS Generator Clock (RGCK), and RASIN is disabled.
CAS remains high, and RF I/O goes low when the refresh
counter has reached the selected End-of-Count and the last
RAS has ended. RF I/O then remains low until the AutoBurst Refresh mode is terminated. RF I/O can therefore be
used as an interrupt to indicate the End-of-Burst conditions.
The signal on all four RAS outputs is just a divide-by-four of
RGCK; in other words, if RGCK has a 100 ns period, RAS is
high and low for 200 ns each cycle. The refresh counter
increments at the end of each RAS, starting from the count
it contained when the mode was entered. If this was zero,
then for a RGCK with a 100 ns period with End-of-Count set
to 127, RF I/O will go low after 128 x 0.4 I'-s, or 51.2 I'-s.
During this time, the system may be performing operations
that do not involve DRAM. If all rows need to be burst refreshed, the refresh counter may be cleared by setting RF
110 low externally before the burst begins.

Referring to Figure Sa, an external 8-bit counter (for 64k
DRAMs) with TRI-STATE outputs is required and must be
connected to the column address inputs. It is enabled only
during this mode, and is clocked from RF I/O. The
DP8409A refresh counter is used to address the rows, and
the column address is supplied by the external counter. Every row for each column address is written to in all four
banks. At the End-of-Count RF I/O goes low, which clocks
the external counter.
Therefore, for each column address, the refresh counter
first outputs row-O to the address bus and all four RAS outputs strobe this row address into the DRAMs (see Figure
5b). A minimum of 30 ns after RAS goes low (tRAH =
30 ns), the refresh counter is disabled and the column ad-

Burst-mode refreshing is also useful when powering down
systems for long periods of time, but with data retention still
required while the DRAMs are in standby. To maintain valid
refreshing, power can be applied to the DP8409A (set to
Mode 2), causing it to perform a complete burst refresh.
When end-of-burst occurs (after 26 I'-s), power can then be
removed from the DP8409A for 2 ms, consuming an average power of 1.3% of normal operating power. No control
signal giiiches occur when switching power to the
DP8409A.
MODE 3a-ALL-RAS AUTOMATIC WRITE
Mode 3a is useful at system initialization, when the memory
is being cleared (i.e., with all-zeros in the data field and the
1-28

C

DP8409A Functional Mode Descriptions (Continued)

"'tJ

dress input latch is enabled onto the address bus. About
14 ns after the column address is valid, CAS goes low, (tAse
= + 14 ns), strobing the column address into the DRAMs.
When RAS and CAS go high the refresh counter increments
to the next row and the cycle repeats. Since WE is kept low
in this mode, the data at DI (input data) of the DRAMs is
written into each row of the latched column. During each
cycle RAS is high for two periods of RGCK and low for two
periods, giving a total write-cycle time of 400 ns minimum,
which is adequate for most 16k and 64k DRAMs. On the last
row of a column, RF I/O increments the external counter to
the next column address.

o

(1)

./:>0

At the end of the last column address, an interrupt is generated from the external counter to let the system know that
initialization has been completed. During the entire initialization time, the system can be performing other initialization
functions. This approach to memory initialization is both automatic and fast. For instance, if four banks of 64k DRAMs
are used, and RGCK is 100 ns, a write cycle to the same
location in all four banks takes 400 ns, so the total time
taken in initializing the 64k DRAMs is 65k X 400 ns or
26 ms. When the system receives the interrupt, the external
counter must be permanently disabled. ADS and CS are
interfaced by the system, and the DP8409A mode is
changed. The interrupt must then be disabled.

REQUIRED IF
SYSTEMSTIU

OPERATING

WHilE DP8409A
IN MDOE3A

~

PROCESSOR
ADDRESS
BUS

RAS

0-3

DRAMS

RASlN--r-----r---------~----_r~1

WiN

WRITE
PROCESSOR ADS

CASIN
M1 Ml .0 IRGCK)

--H----

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