1989_National_Data_Acquisition_Linear_Devices_Databook 1989 National Data Acquisition Linear Devices Databook
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~ National
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Semiconductor
400015
Data Acquisition
Linear Devices
Databook
1989 Edition
General Information
Alphanumeric
Available Hybrid Products
Additional Available Linear Devices
Industry Cross Reference Guide by Part Number
Package Cross Reference Guide
Active Filters
•
Analog Switches/Multiplexers
•
Analog-to-Digital Converters
Digital-to-Analog Converters
Sample and Hold
Temperature Sensors
II
II
II
til
Surface Mount
fI
II
Appendices/Physical Dimensions
•
Voltage References
iii
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied, and National reserves the right, at any time
without notice, to change said circuitry or specifications.
iv
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Linear Products
Introduction
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National Semiconductor Corporation first established itself
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~National
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Product Status Definitions
1:)
~
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Definition of Terms
Definition
Product Status
Formative or
In Design
This data sheet contains the design specifications for product
development. Specifications may change in any manner without notice.
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or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others.
vi
Table of Contents
Alphanumeric Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Available Hybrid Products .....................................................
Additional Available Linear Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cross Reference by Part Number. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Cross Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Section 1 Active Filters
Active Filters Definition of Terms ...............................................
Active Filters Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AF100 Universal Active Filter ..................................................
AF150 Universal Wideband Active Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AF151 Dual Universal Active Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LMF90 4th-Order LMCMOSTM Programmable Elliptic Notch Filter...................
LMF100 High Performance Dual Switched Capacitor Filter. . . . . . . . . . . . . . . . . . . . . . . ..
LMF120 Mask Programmable Switched Capacitor Filter ...........................
MF4 4th Order Switched Capacitor Butterworth Lowpass Filter . . . . . . . . . . . . . . . . . . . . .
MF5 Universal Monolithic Switched Capacitor Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MF6 6th Order Switched Capacitor Butterworth Lowpass Filter . . . . . . . . . . . . . . . . . . . . .
MF8 4th Order Switched Capacitor Bandpass Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MF10 Universal Monolithic Dual Switched Capacitor Filter.........................
Section 2 Analog Switches/Multiplexers
Analog Switches/Multiplexers Definition of Terms ................................
Analog Switches/Multiplexers Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AH0014/ AH0014C DPDT, AH0015/ AH0015C Quad SPST, AH0019/ AH0019C Dual
DPST-TTL/DTL Compatible MOS Analog Switches.. . .. .. .. .. . . . ... . . .. . . .... ..
AH5009/ AH501 0/ AH5011 / AH5012 Monolithic Analog Current Switch ..............
AH5020C Monolithic Analog Current Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CD4016BM/CD4016BC Quad Bilateral Switch...................................
CD4051 BM/CD4051 BC Single 8-Channel Analog Multiplexer/Demultiplexer. . . . . . . . .
CD4052BM/CD4052BC Dual4-Channel Analog Multiplexer/Demultiplexer. .. . . .. . ..
CD4053BM/CD4053BC Triple 2-Channel Analog Multiplexer/Demultiplexer. . . . . . . . . .
CD4066BM/CD4066BC Quad Bilateral Switch ...................................
CD4529BC Dual4-Channel or 8-Channel Analog Data Selector.. . .. .. .. . .. .. . .. .. ..
LF11331/LF13331/LF11332/LF13332/LF11333/LF13333,LF11201/LF13201/
LF11202/LF13202 Quad SPST JFET Analog Switches. . . . . . . . . . . . . . . . . . . . . . . . . .
LF13508 8-Channel Analog Multiplexer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LF13509 4-Channel Analog Multiplexer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HC4016/MM74HC4016 Quad Analog Switch...............................
MM54HC4051/MM74HC4051 8-Channel Analog Multiplexer. . . . . . . . . . . . . . . . . . . . . . .
MM54HC4052/MM74HC4052 Dual4-Channel Analog Multiplexer. .. .. . .. .. ... . ....
MM54HC4053/MM74HC4053 Triple 2-Channel Analog Multiplexer.. .. . .. .. ... . ... .
MM54HC4066/MM74HC4066 Quad Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM54HC4316/MM74HC4316 Quad Analog Switch with Level Translator. . . . . . . . . . . .
Section 3 Analog-to-Digital Converters
Analog-to-Digital Converters Definition of Terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog-to-Digital Converters Selection Guide. . .. .. ... .. .. . . .. . . . .. .. . . . . ... . . ....
ADC0800 8-Bit A/D Converter. .. . . .. . . . . .. . . .. .. .... ... . . . . . .. . .. . . . . .. . . .. .. .
ADC0801 / ADC0802/ ADC0803/ ADC0804/ ADC0805 8-Bit p.P Compatible A/D
Converters ................................................................
ADC0808/ ADC0809 8-Bit /-LP Compatible AID Converters with 8-Channel Multiplexer.
ADC0811 8-Bit Serial 110 A/D Converter with 11-Channel Multiplexer. . . . . . . . . . . . . . .
vii
x
xiv
xvi
xxv
xxx
1-3
1-4
1-5
1-23
1-42
1-51
1-71
1-93
1-106
1-119
1-134
1-152
1-174
2-3
2-4
2-5
2-9
2-20
2-28
2-29
2-29
2-29
2-30
2-31
2-32
2-43
2-43
2-57
2-58
2-58
2-58
2-59
2-60
3-3
3-4
3-7
3-16
3-48
3-59
Table of Contents (Continued)
Section 3 Analog-to-Digital Converters (Continued)
ADC08161 ADC0817 8-Bit p.P Compatible AID Converters with 16-Channel
Multiplexer ................................................................ .
ADC0819 8-Bit Serial 1/0 AID Converter with 19-Channel Multiplexer .............. .
ADC0820 8-Bit High Speed p.P Compatible AID Converter with Track/Hold Function ..
ADC0829 p.P Compatible 8-Bit AID with 11-Channel MUX/Digitallnput ............. .
ADC0831 I ADC08321 ADC0834 and ADC0838 8-Bit Serial 1/0 AID Converters with
Multiplexer Options ........................................................ .
ADC0833 8-Bit Serial 1/0 AID Converter with 4-Channel Multiplexer ............... .
ADC0841 8-Bit p.P Compatible AID Converter ........................ , .......... .
ADC08441 ADC0848 8-Bit p.P Compatible AID Converters with Multiplexer Options .. .
ADC08521 ADC0854 Multiplexed Comparators with 8-Bit Reference Divider ......... .
ADC1 001 I ADC1 021 1O-Bit p.P Compatible AID Converters ....................... .
ADC1 0051 ADC1 025 1O-Bit p.P Compatible AID Converters ....................... .
ADC12051 ADC1225 12-Bit Plus Sign p.P Compatible AID Converters .............. .
ADC121 01 ADC1211 12-Bit CMOS AID Converters .............................. .
ADC3511 3%-Digit Microprocessor Compatible AID Converter .................... .
ADC3711 3%-Digit Microprocessor Compatible AID Converter .................... .
ADD3501 3%-Digit DVM with Multiplexed 7-Segment Output ...................... .
ADD3701 3%-Digit DVM with Multiplexed 7-Segment Output ...................... .
DM2502/DM2503/DM2504 Successive Approximation Registers .................. .
LM 131 AI LM 131, LM231 AI LM231, LM331 AI LM331 Precision Voltage-to-Frequency
Converters ............................................................... .
MM54C905/MM74C905 12-Bit Successive Approximation Register ................ .
* p.A9708 6-ChanneI8-Bit p.P Compatible AID Converter .......................... .
3-70
3-81
3-91
3-107
3-115
3-140
3-158
3-170
3-187
3-204
3-211
3-222
3-239
3-250
3-250
3-259
3-268
3-278
3-279
3-290
3-291
Section 4 Digital-to-Analog Converters
Digital-to-Analog Converters Definition of Terms ................................. .
Digital-to-Analog Converters Selection Guide .................................... .
* DAC0630/DAC0631 Triple 6-Bit Video DAC with Color Pallette .................... .
DAC0800/DAC0801 IDAC0802 8-Bit DI A Converters ............................ .
DAC0808/DAC0807/DAC0806 8-Bit DI A Converters ............................ .
DAC0830/DAC0831 IDAC0832 8-Bit p.P Compatible Double-Buffered DI A
Converters ............................................................... .
DAC1 000/DAC1 001 IDAC1 002/DAC1 006/DAC1 007 IDAC1 008 p.P Compatible,
Double-Buffered DI A Converters ............................................ .
DAC1 020/DAC1 021 IDAC1 022 1O-Bit Binary Multiplying DI A Converters ........... .
DAC1220/DAC1221 IDAC1222 12-Bit Binary Multiplying DI A Converters ........... .
DAC1208/DAC1209/DAC121 0/DAC1230/DAC1231 IDAC1232 12-Bit p.P Compatible
Double-Buffered DI A Converters ............................................ .
DAC1218/DAC121912-Bit Multiplying D/A Converters ........................... .
DAC1265A/DAC1265 Hi-Speed 12-Bit DI A Converters with Reference ............. .
DAC1266A/DAC1266 Hi-Speed 12-Bit DI A Converters ........................... .
4-3
4-4
4-6
4-21
4-30
4-38
4-56
4-79
4-79
4-89
4-104
4-115
4-124
Section 5 Sample and Hold
Sample and Hold Definition of Terms ........................................... .
Sample and Hold Selection Guide ............................................. .
LF198/LF298/LF198A1LF398A Monolithic Sample and Hold Circuits .............. .
LF13006/LF13007 Digital Gain Set ............................................ .
LH0023/LH0023C/LH0043/LH0043C Sample and Hold Circuits .................. .
LH0053/LH0053C High Speed Sample and Hold Amplifier ........................ .
• LH4860 Super Fast 12-BitTrack-Hold Amplifier .................................. .
'Devices Not Covered In Last Publication
viii
5-3
5-4
5-5
5-15
5-22
5-31
5-37
Table of Contents (Continued)
Section 6 Temperature Sensors
Temperature Sensors Selection Guide ..........................................
LM34/LM34A/LM34C/LM34CAlLM34D Precision Fahrenheit Temperature Sensors. .
LM3S/LM3SA/LM3SC/LM3SCA/LM3SD Precision Centigrade Temperature Sensors.
LM13S/LM23S/LM33S/LM13SA/LM23SA/LM33SA Precision Temperature Sensors..
LM3911 Temperature Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Section 7 Voltage Reference
Voltage Reference Selection Guide. . . . .. . .... .. ... .. ... .. . . .. .. .. .. . .. . . . ... . ..
LH0070 Series BCD Buffered Reference. .. .. .. .... . . . . . . . . .. .. .. .. . . . .. . . .. . . ..
LH0071 Series Precision Buffered Reference ....................................
• LH7070 Series Precision BCD Buffered Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
• LH7071 Series Precision Binary Buffered Reference ..............................
LM113/LM313 Reference Diode. .. . .. .. .. .... . ... . ... .. . ... .. .. .. .. ... .. ... . ..
LM129/LM329 Precision Reference............................................
LM134/LM234/LM334 3-Terminal Adjustable Current Sources. . . . . . . . . . . . . . . . . . . . .
LM136-2.S/LM236-2.S/LM336-2.SV Reference Diodes. . .... . . .. .. .... . .. .. .... . ..
LM136-S.0/LM236-S.0/LM336-S.0V Reference Diodes.. ... .. . . . .. .. .. . .. .. . . .. . ..
LM168/LM268/LM368 Precision Voltage References. . .. ... .. .. . . . .... . .. . . ... . ..
LM169/LM369 Precision Voltage References.. .. . ... . . .... . . .. . . . ... . . . . . .... . ..
LM18S-1.2/LM28S-1.2/LM38S-1.2 MicropowerVoltage Reference Diodes...........
LM18S-2.S/LM28S-2.S/LM38S-2.S MicropowerVoltage Reference Diodes...........
LM1 8S/LM28S/LM38S Adjustable Micropower Voltage References. . . . . . . . . . . . . . . . .
LM199/LM299/LM399/LM3999 Precision References... .... . . .. .. .. . . ... . . .. . . ..
LM368-2.S Precision Voltage Reference... .. . .. . ... .. .. ... .. . .. .. .... . .. . . ... ...
Section 8 Surface Mount
Surface Mount .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-4S0 Small Outline (SO) Package Surface Mounting Methods-Parameters and Their
Effect on Product Reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Section 9 Appendices/Physical Dimensions
Appendix A General Product Marking and Code Explanation .......................
Appendix B Application Note Referenced by Part Number. . . . . . . . . . . . . . . . . . . . . . . . . .
Appendix C Summary of Commercial Reliability Programs. . . . . . . . . . . . . . . . . . . . . . . . . .
Appendix D Military Aerospace Programs from National Semiconductor. . . . . . . . . . . . . .
Appendix E Understanding Integrated Circuit Package Power Capabilities. . .. . . .... . .
Appendix F How to Get the Right Information from a Datasheet . . . . . . . . . . . . . . . . . . . . .
Appendix G Obsolete Product Replacement Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Physical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bookshelf
Distributors
*Devlces Not Covered In Last Publication
ix
6-3
6-4
6-12
6-21
6-30
7-3
7-7
7-7
7-11
7-11
7-16
7-19
7-24
7-32
7-39
7-46
7-S2
7-62
7-69
7-7S
7-82
7-91
8-3
8-13
9-3
9-4
9-10
9-11
9-18
9-23
9-27
9-28
Alpha-Numeric Index
ADC0800 8-Bit AID Converter .............................................................. 3-7
ADC0801 8-Bit p.P Compatible AID Converter ................................................ 3-16
ADC0802 8-Bit p.P Compatible A/D Converter ................................................ 3-16
ADC0803 8-Bit p.P Compatible AID Converter ..................... '" ........................ 3-16
ADC0804 8-Bit p.P Compatible A/D Converter ................................................ 3-16
ADC0805 8-Bit p.P Compatible AI D Converter ................................................ 3-16
ADC0808 8-Bit p.P Compatible AID Converter with 8-Channel Multiplexer ........................ 3-48
ADC0809 8-Bit p.P Compatible AID Converter with 8-Channel Multiplexer ........................ 3-48
ADC0811 8-Bit Serial 1/0 AID Converter with 11-Channel Multiplexer ........................... 3-59
ADC0816 8-Bit p.P Compatible AID Converter with 16-Channel Multiplexer ....................... 3-70
ADC0817 8-Bit p.P Compatible AID Converter with 16-Channel Multiplexer ... " .................. 3-70
ADC0819 8-Bit Serial 1/0 AID Converter with 19-Channel Multiplexer ........................... 3-81
ADC0820 8-Bit High Speed p.P Compatible AID Converter with Track/Hold Function .............. 3-91
ADC0829 p.P Compatible 8-Bit AID with 11-Channel MUX/Digitallnput ......................... 3-107
ADC0831 8-Bit Serial 1/0 AID Converter with Multiplexer Options ............................. 3-115
ADC0832 8-Bit Serial 1/0 AID Converter with Multiplexer Options ............................. 3-115
ADC0833 8-Bit Serial 1/0 AID Converter with 4-Channel Multiplexer ........................... 3-140
ADC0834 8-Bit Serial 1/0 AID Converter with Multiplexer Options ............................. 3-115
ADC0838 8-Bit Serial 1/0 AID Converter with Multiplexer Options ............................. 3-115
ADC0841 8-Bit p.P Compatible AID Converter. .............................................. 3-158
ADC0844 8-Bit p.P Compatible AID Converter with Multiplexer Options ......................... 3-170
ADC0848 8-Bit p.P Compatible AID Converter with Multiplexer Options ......................... 3-170
ADC0852 Multiplexed Comparator with 8-Bit Reference Divider ................................. 3-187
ADC0854 Multiplexed Comparator with 8-Bit Reference Divider ................................ 3-187
ADC1001 1O-Bit p.P Compatible AID Converter ............................................. 3-204
ADC1005 1O-Bit p.P Compatible AID Converter ............................................. 3-211
ADC1021 10-Bit p.P Compatible AID Converter ............................................. 3-204
ADC1025 10-Bit p.P Compatible AID Converter ......................•...................... 3-211
ADC1205 12-Bit Plus Sign p.P Compatible AID Converter ..................................... 3-222
ADC1210 12-Bit CMOS AID Converter ..................................................... 3-239
ADC1211 12-Bit CMOS AID Converter ..................................................... 3-239
ADC1225 12-Bit Plus Sign p.P Compatible AID Converter ..................................... 3-222
ADC3511 3%-Digit Microprocessor Compatible AID Converter ................................ 3-250
ADC3711 3%-Digit Microprocessor Compatible AID Converter ................................ 3-250
ADD3501 3%-Digit DVM with Multiplexed 7-Segment Output .................................. 3-259
ADD3701 3%-Digit DVM with Multiplexed 7-Segment Output .................................. 3-268
AF100 Universal Active Filter ................................................................ 1-5
AF150 Universal Wideband Active Filter ..................................................... 1-23
AF151 Dual Universal Active Filter .......................................................... 1-42
AH0014 Dual DPST-TTL/DTL Compatible MOS Analog Switch .................................. 2-5
AH0015 Quad SPST Dual DPST-TTL/DTL Compatible MOS Analog Switch ....................... 2-5
AH0019 Dual DPST-TTL/DTL Compatible MOS Analog Switch .................................. 2-5
AH5009 Monolithic Analog Current Switch .................................................... 2-9
AH5010 Monolithic Analog Current Switch .................................................... 2-9
AH5011 Monolithic Analog Current Switch .................................................... 2-9
AH50 12 Monolithic Analog Current Switch .................................................... 2-9
AH5020C Monolithic Analog Current Switch .................................................. 2-20
CD4016BM Quad Bilateral Switch .......................................................... 2-28
CD4051 BM Single 8-Channel Analog Multiplexer/Demultiplexer ................................ 2-29
CD4052BM Dual4-Channel Analog Multiplexer/Demultiplexer ............ '" .................. 2-29
CD4053BM Triple 2-Channe: Analog MultiplexerIDemultiplexer ................................. 2-29
x
Alpha-Numeric Index (Continued)
CD4066BM Quad Bilateral Switch .......................................................... 2-30
CD4529BC Dual4-Channel or 8-Channel Analog Data Selector ....... " ........................ 2-31
DAC0630 Triple 6-Bit Video DAC with Color Pallette ............................................ 4-6
DAC0631 Triple 6-Bit Video DAC with Color Pallette ............................................ 4-6
DAC0800 8-Bit Df A Converter ............................................................. 4-21
DAC0801 8-Bit Df A Converter ............................................................. 4-21
DAC0802 8-Bit Df A Converter ............................................................. 4-21
DAC0806 8-Bit Df A Converter ............................................................. 4-30
DAC0807 8-Bit Df A Converter ............................................................. 4-30
DAC0808 8-Bit Df A Converter ............................................................. 4-30
DAC0830 8-Bit p.P Compatible Double-Buffered Df A Converter . ................................ 4-38
DAC0831 8-Bit p.P Compatible Double-Buffered Df A Converter . ................................ 4-38
DAC0832 8-Bit p.P Compatible Double-Buffered Df A Converter . ................................ 4-38
DAC1 000 p.P Compatible, Double-Buffered Df A Converter . .................................... 4-56
DAC1001 p.P Compatible, Double-Buffered Df A Converter . .................................... 4-56
DAC1002 p.P Compatible, Double-Buffered Df A Converter . .................................... 4-56
DAC1006 p.P Compatible, Double-Buffered Df A Converter . .................................... 4-56
DAC1007 p.P Compatible, Double-Buffered Df A Converter . .................................... 4-56
DAC1008 p.P Compatible, Double-Buffered Df A Converter . .................................... 4-56
DAC1020 10-Bit Binary Multiplying DfA Converter ............................................ 4-79
DAC1021 10-Bit Binary Multiplying Df A Converter . ........................................... 4-79
DAC1022 10-Bit Binary Multiplying Df A Converter . ........................................... 4-79
DAC1208 12-Bit p.P Compatible Double-Buffered Df A Converter ............................... 4-89
DAC1209 12-Bit p.P Compatible Double-Buffered Df A Converter ............................... 4-89
DAC1210 12-Bit p.P Compatible Double-Buffered Df A Converter ............................... 4-89
DAC1218 12-Bit Multiplying Df A Converter . ................................................ 4-104
DAC1219 12-Bit Multiplying Df A Converter . ................................................ 4-104
DAC1220 12-Bit Binary Multiplying Df A Converter . ........................................... 4-79
DAC1221 12-Bit Binary Multiplying Df A Converter . ........................................... 4-79
DAC1222 12-Bit Binary Multiplying Df A Converter ............................................ 4-79
DAC1230 12-Bit p.P Compatible Double-Buffered Df A Converter ............................... 4-89
DAC1231 12-Bit p.P Compatible Double-Buffered Df A Converter ............................... 4-89
DAC1232 12-Bit p.P Compatible Double-Buffered Df A Converter ............................... 4-89
DAC1265 Hi-Speed 12-Bit Df A Converter with Reference .................................... 4-115
DAC1266 Hi-Speed 12-BitDf A Converter .................................................. 4-124
DM2502 Successive Approximation Register ................................................ 3-278
DM2503 Successive Approximation Register ................................................ 3-278
DM2504 Successive Approximation Register ................................................ 3-278
LF198 Monolithic Sample and Hold Circuit .................................................... 5-5
LF298 Monolithic Sample and Hold Circuit .................................................... 5-5
LF398A Monolithic Sample and Hold Circuit ................................................... 5-5
LF11201 Quad SPST JFET Analog Switch ................................................... 2-32
LF11202 Quad SPST JFET Analog Switch ................................................... 2-32
LF11331 Quad SPST JFET Analog Switch ................................................... 2-32
LF11332 Quad SPST J FET Analog Switch ................................................... 2-32
LF11333 Quad SPST J FET Analog Switch ................................................... 2-32
LF13006 Digital Gain Set .................................................................. 5-15
LF13007 Digital Gain Set .................................................................. 5-15
LF13201 Quad SPST JFET Analog Switch ................................................... 2-32
LF13202 Quad SPST JFET Analog Switch ................................................... 2-32
LF13331 Quad SPST JFET Analog Switch ................................................... 2-32
xi
Alpha-Numeric
Index(continUed)
LF13332 Quad SPST JFET Analog Switch ...........................................•....... 2-32
LF13333 Quad SPST JFET Analog Switch ................................................... 2-32
LF13508 8-Channel Analog Multiplexer ...................................................... 2-43
LF13509 4-Channel Analog Multiplexer ...................................................... 2-43
LH0023 Sample and Hold Circuit ........................................................... 5-22
LH0043 Sample and Hold Circuit ........................................................... 5-22
LH0053 High Speed Sample and Hold Amplifier .............................................. 5-31
LH0070 Series BCD Buffered Reference ...................................................... 7-7
LH0071 Series Precision Buffered Reference ................................................. 7-7
LH4860 Super Fast 12-Bit Track-Hold Amplifier ............................................... 5-37
LH7070 Series Precision BCD Buffered Reference ............................................ 7-11
LH7071 Series Precision Binary Buffered Reference .......................................... 7-11
LM34 Precision Fahrenheit Temperature Sensor ............................................... 6-4
LM35 Precision Centigrade Temperature Sensor ............................................. 6-12
LM113 Reference Diode .................................................................. 7-16
LM129 Precision Reference ............................................................... 7-19
LM131 Precision Voltage-to-Frequency Converter ........................................... 3-279
LM134 3-Terminal Adjustable Current Source ................................................ 7-24
LM135 Precision Temperature Sensor. ...................................................... 6-21
LM136-2.5V Reference Diode .............................................................. 7-32
LM136-5.0V Reference Diode .............................................................. 7-39
LM168 Precision Voltage Reference ........................................................ 7-46
LM169 Precision Voltage Reference ........................................................ 7-52
LM185 Adjustable Micropower Voltage Reference ............................................ 7-75
LM185-1.2 Micropower Voltage Reference Diode ............................................. 7-62
LM185-2.5 MicropowerVoltage Reference Diode ............................................. 7-69
LM199 Precision Reference ............................................................... 7-82
LM231 Precision Voltage-to-Frequency Converter ........................................... 3-279
LM234 3-Terminal Adjustable Current Source ................................................ 7-24
LM235 Precision Temperature Sensor ....................................................... 6-21
LM236-2.5V Reference Diode .............................................................. 7-32
LM236-5.0V Reference Diode .............................................................. 7-39
LM268 Precision Voltage Reference ........................................................ 7-46
LM285 Adjustable Micropower Voltage Reference ............................................. 7-75
LM285-1.2 Micropower Voltage Reference Diode ............................................. 7-62
LM285-2.5 MicropowerVoltage Reference Diode ............................................. 7-69
LM299 Precision Reference ............................................................... 7-82
LM313 Reference Diode .................................................................. 7-16
LM329 Precision Reference ............................................................... 7-19
LM331 Precision Voltage-to-Frequency Converter ........................................... 3-279
LM334 3-Terminal Adjustable Current Source ................................................ 7-24
LM335 Precision Temperature Sensor ....................................................... 6-21
LM336-2.5V Reference Diode .............................................................. 7-32
LM336-5.0V Reference Diode .............................................................. 7-39
LM368 Precision Voltage Reference ........................................................ 7-46
LM368-2.5 Precision Voltage Reference ..................................................... 7-91
LM369 Precision Voltage Reference ........................................................ 7-52
LM385 Adjustable Micropower Voltage Reference ............................................ 7-75
LM385-1.2 Micropower Voltage Reference Diode ............................................. 7-62
LM385-2.5 Micropower Voltage Reference Diode ............................................. 7-69
LM399 Precision Reference ............................................................... 7-82
xii
Alpha-Numeric Index (Continued)
LM3911 Temperature Controller ............................................................ 6-30
LM3999 Precision Reference .............................................................. 7-82
LMF90 4th-Order LMCMOSTM Programmable Elliptic Notch Filter ............................... 1-51
LMF100 High Performance Dual Switched Capacitor Filter ..................................... 1-71
LMF120 Mask Programmable Switched Capacitor Filter ....................................... 1-93
M F4 4th Order Switched Capacitor Butterworth Lowpass Filter ................................ 1-106
MF5 Universal Monolithic Switched Capacitor Filter .......................................... 1-119
MF6 6th Order Switched Capacitor Butterworth Lowpass Filter ................................ 1-134
MF8 4th Order Switched Capacitor Bandpass Filter .......................................... 1-152
MF10 Universal Monolithic Dual Switched Capacitor Filter .................................... 1-174
MM54C905 12-Bit Successive Approximation Register ....................................... 3-290
MM54HC4016 Quad Analog Switch ......................................................... 2-57
MM54HC4051 8-Channel Analog Multiplexer ................................................. 2-58
MM54HC4052 Dual 4-Channel Analog Multiplexer ............................................ 2-58
MM54HC4053 Triple 2-Channel Analog Multiplexer ........................................... 2-58
MM54HC4066 Quad Analog Switch ......................................................... 2-59
MM54HC4316 Quad Analog Switch with Level Translator ...................................... 2-60
MM74C905 12-Bit Successive Approximation Register ....................................... 3-290
MM74HC4016 Quad Analog Switch ......................................................... 2-57
MM74HC4051 8-Channel Analog Multiplexer ................................................. 2-58
MM74HC4052 Dual4-Channel Analog Multiplexer ............................................ 2-58
MM74HC4053 Triple 2-Channel Analog Multiplexer ........................................... 2-58
MM74HC4066 Quad Analog Switch ......................................................... 2-59
MM74HC4316 Quad Analog Switch with Level Translator ...................................... 2-60
]LA9708 6-Channel 8-Bit ]LP Compatible AID Converter ...................................... 3-291
xiii
~National
~ Semiconductor
Available Hybrid Products
Device Number
Databook
ADC1210/ADC1211
AF100
AF150
AF151
AH00141 AH00151 AHOO19
DHOOO6
DHOOO8
DHOO11
DHOO34
DHOO35
DH3467
DH3725
LHOOO2
LHOOO3
LHOOO4
LHOO20
LHOO21/LHOO41
LHOO22/LHOO42/LHOO52
LHOO23/LHOO43
LHOO24
LHOO32
LHOO33/LHOO63
LHOO36
LHOO38
LHOO44
LHOO45
LHOO53
LHOO61
LHOO62
LHOO70/LHOO71
LHOO75
LHOO76
LHOO82
LHOO84
LHOO86
LHOO91
LHOO94
LH0101
Data Acquisition Linear Devices
Data Acquisition Linear Devices
Data Acquisition Linear Devices
Data Acquisition Linear Devices
Data Acquisition Linear Devices
Individual Datasheet
Individual Datasheet
Individual Datasheet
Individual Datasheet
Individual Datasheet
Individual Datasheet
Individual Datasheet
General Purpose Linear Devices
General Purpose Linear Devices
General Purpose Linear Devices
General Purpose Linear Devices
General Purpose Linear Devices
General Purpose Linear Devices
Data Acquisition Linear Devices
General Purpose Linear Devices
General. Purpose Linear Devices
General Purpose Linear Devices
General Purpose Linear Devices
General Purpose Linear Devices
General Purpose Linear Devices
General Purpose Linear Devices
Data Acquisition Linear Devices
General Purpose Linear Devices
General Purpose Linear Devices
Data Acquisition Linear Devices
General Purpose Linear Devices
General Purpose Linear Devices
General Purpose Linear Devices
General Purpose Linear Devices
General Purpose Linear Devices
Special Purpose Linear Devices
Special Purpose Linear Devices
General Purpose Linear Devices
xiv
Device Number
Databook
LH1605
LH2101
LH2108/LH2308
LH2110/LH2210/LH2310
LH2111/LH2211/LH2311
LH2422
LH4001
LH4002
LH4003
LH4004
LH4006
LH4008
LH4009
LH4010
LH4011
LH4012
LH4033/LH4063
LH4101
LH4104
LH4105
LH41 06
LH4117
LH4118
LH4124
LH4141
LH4161
LH4162
LH4200
LH4266
LH4860
LH7001
LH7070/LH7071
HS7067
HS7107
MHOO07
General Purpose Linear Devices
General Purpose Linear Devices
General Purpose Linear Devices
General Purpose Linear Devices
General Purpose Linear Devices
Special Purpose Linear Devices
General Purpose Linear Devices
General Purpose Linear Devices
General Purpose Linear Devices
General Purpose Linear Devices
General Purpose Linear Devices
General Purpose Linear Devices
General Purpose Linear Devices
General Purpose Linear Devices
General Purpose Linear Devices
General Purpose Linear Devices
General Purpose Linear Devices
General Purpose Linear Devices
General Purpose Linear Devices
General Purpose Linear Devices
General Purpose Linear Devices
General Purpose Linear Devices
General Purpose Linear Devices
General Purpose Linear Devices
General Purpose Linear Devices
General Purpose Linear Devices
General Purpose Linear Devices
General Purpose Linear Devices
Special Purpose Linear Devices
Data Acquisition Linear Devices
General Purpose Linear Devices
Data Acquisition Linear Devices
General Purpose Linear Devices
General Purpose Linear Devices
Individual Datasheet
xv
~National
~ Semiconductor
Additional Available Linear Devices
Device
Databook
HS7067 7 Amp, Multimode, High Efficiency Switching Regulator ........ General Purpose Linear Devices
HS71 07 7 Amp, Multimode, High Efficiency Switching Regulator ........ General Purpose Linear Devices
LF111 Voltage Comparator ........................................ General Purpose Linear Devices
LF147 Wide Bandwidth Quad JFET Input Operational Amplifiers ........ General Purpose Linear Devices
LF155 Series Monolithic JFET Input Operational Amplifiers ............ General Purpose Linear Devices
LF156 Series Monolithic JFET Input Operational Amplifiers ............ General Purpose Linear Devices
LF157 Series Monolithic JFET Input Operational Amplifiers ............ General Purpose Linear Devices
LF211 Voltage Comparator ........................................ General Purpose Linear Devices
LF255 Series Monolithic JFET Input Operational Amplifiers ............ General Purpose Linear Devices
LF256 Series Monolithic JFET Input Operational Amplifiers ............ General Purpose Linear Devices
LF257 Series Monolithic JFET Input Operational Amplifiers ............ General Purpose Linear Devices
LF311 Voltage Comparator ........................................ General Purpose Linear Devices
LF347 Wide Bandwidth Quad JFET Input Operational Amplifiers ........ General Purpose Linear Devices
LF347B Wide Bandwidth Quad JFET Input Operational Amplifiers ...... General Purpose Linear Devices
LF351 Wide Bandwidth JFET Input Operational Amplifier .............. General Purpose Linear Devices
LF353 Wide Bandwidth Dual JFET Input Operational Amplifier ......... General Purpose Linear Devices
LF355 Series Monolithic JFET Input Operational Amplifiers ............ General Purpose Linear Devices
LF356 Series Monolithic JFET Input Operational Amplifiers ............ General Purpose Linear Devices
LF357 Series Monolithic JFET Input Operational Amplifiers ............ General Purpose Linear Devices
LF400 Fast Settling JFET Input Operational Amplifier ................. General Purpose Linear Devices
LF401 Precision Fast Settling JFET Input Operational Amplifier ......... General Purpose Linear Devices
LF411 Low Offset, Low Drift JFET Input Operational Amplifier .......... General Purpose Linear Devices
LF412 Low Offset, Low Drift Dual JFET Operational Amplifier .......... General Purpose Linear Devices
LF441 Low Power JFET Input Operational Amplifier ................... General Purpose Linear Devices
LF442 Dual Low Power JFET Input Operational Amplifier .............. General Purpose Linear Devices
LF444 Quad Low Power JFET Input Operational Amplifier ............. General Purpose Linear Devices
LF451 Wide-Bandwidth JFET Input Operational Amplifier .............. General Purpose Linear Devices
LF453 Wide-Bandwidth Dual JFET Input Operational Amplifier ......... General Purpose Linear Devices
LF13741 Monolithic JFET Input Operational Amplifier ................. General Purpose Linear Devices
LH0002 Current Amplifier .......................................... General Purpose Linear Devices
LH0003 Wide Bandwidth Operational Amplifier ....................... General Purpose Linear Devices
LH0004 High Voltage Operational Amplifier .......................... General Purpose Linear Devices
LH0020 High Gain Operational Amplifier ............................. General Purpose Linear Devices
LH0021 1.0-Amp Power Operational Amplifier ........................ General Purpose Linear Devices
LH0022 High Performance FET Operational Amplifier ................. General Purpose Linear Devices
LH0024 High Slew Rate Operational Amplifier ........................ General Purpose Linear Devices
LH0032 Ultra Fast FET-Input Operational Amplifier ................... General Purpose Linear Devices
LH0033 Fast Buffer Amplifier ...................................... General Purpose Linear Devices
LH0036 Instrumentation Amplifier .................................. General Purpose Linear Devices
LH0038 True Instrumentation Amplifier .............................. General Purpose Linear Devices
LH0041 0.2-Amp Power Operational Amplifier ........................ General Purpose Linear Devices
LH0042 Low Cost FET Operational Amplifier ......................... General Purpose Linear Devices
LH0044 Series Precision Low Noise Operational Amplifiers ............ General Purpose Linear Devices
LH0045 Two Wire Transmitter ..................................... General Purpose Linear Devices
xvi
r-------------------------------------------------------------------~~
C.
C.
Additional Available Linear Devices (Continued)
Device
;::;:
Databook
LH0052 Precision FET Operational Amplifier ......................... General Purpose Linear Devices
LH0061 0.5 Amp Wide Band Operational Amplifier .................... General Purpose Linear Devices
LH0062 High Speed FET Operational Amplifier ....................... General Purpose Linear Devices
LH0063 Fast Buffer Amplifier ...................................... General Purpose Linear Devices
LH0075 Positive Precision Programmable Regulator .................. General Purpose Linear Devices
LH0076 Negative Precision Programmable Regulator ................. General Purpose Linear Devices
LH0082 Optical Communication Receiver/Amplifier ................... General Purpose Linear Devices
LH0084 Digitally-Programmable-Gain Instrumentation Amplifier ........ General Purpose Linear Devices
LH0086 Digitally-Programmable-Gain Amplifier ....................... General Purpose Linear Devices
LH0091 True RMS to DC Converter ................................. Speciai Purpose Linear Devices
LH0094 Multifunction Converter .................................... Special Purpose Linear Devices
LH0101 Power Operational Amplifier ................................ General Purpose Linear Devices
LH 1605 5 Amp, High Efficiency Switching Regulator .................. General Purpose Linear Devices
LH21 01 A Dual High Performance Operational Amplifier ............... General Purpose Linear Devices
LH2108 Dual Super Beta Operational Amplifier ....................... General Purpose Linear Devices
LH2110 Dual Voltage Follower ..................................... General Purpose Linear Devices
LH2111 Dual Voltage Comparator .................................. General Purpose Linear Devices
LH2201 A Dual High Performance Operational Amplifier ............... General Purpose Linear Devices
LH2210 Dual Voltage Follower ..................................... General Purpose Linear Devices
LH2211 Dual Voltage Comparator .................................. General Purpose Linear Devices
LH2301A Dual High Performance Operational Amplifier ............... General Purpose Linear Devices
LH2308 Dual Super Beta Operational Amplifier ....................... General Purpose Linear Devices
LH2310 Dual Voltage Follower ..................................... General Purpose Linear Devices
LH2311 Dual Voltage Comparator .................................. General Purpose Linear Devices
LH2422 CRT Video Driver Amplifier ................................. Special Purpose Linear Devices
LH4001 Wideband Current Buffer .................................. General Purpose Linear Devices
LH4002 Wideband Video Buffer .................................... General Purpose Linear Devices
LH4003 Precision RF Closed Loop Buffer ........................... General Purpose Linear Devices
LH4004 Wideband FET Input Buffer/Amplifier ........................ General Purpose Linear Devices
LH4006 Precision RF Closed Loop Buffer ........................... General Purpose Linear Devices
LH4008 Fast Buffer ............................................... General Purpose Linear Devices
LH4009 Fast Buffer ................................................ General Purpose Linear Devices
LH4010 Fast FET Buffer .......................................... General Purpose Linear Devices
LH4011 Fast Open Loop Buffer .................................... General Purpose Linear Devices
LH4012 Wideband Buffer .......................................... General Purpose Linear Devices
LH4033C Fast and Ultra Fast Buffer Amplifiers ....................... General Purpose Linear Devices
LH4063C Fast and Ultra Fast Buffer Amplifiers ....................... General Purpose Linear Devices
LH4101 Wideband High Current Operational Amplifier ................. General Purpose Linear Devices
LH4104 Fast Settling High Current Operational Amplifier .............. General Purpose Linear Devices
LH4105 Precision Fast Settling High Current Operational Amplifier ...... General Purpose Linear Devices
LH4106 ± 5V High Speed Operational Amplifier ...................... General Purpose Linear Devices
LH4117 Precision RF Amplifier ..................................... General Purpose Linear Devices
LH4118 Low Gain Wide Band RF Amplifier .......................... General Purpose Linear Devices
LH4124C High Slew Rate Operational Amplifier ...................... General Purpose Linear Devices
LH4141 C 0.2 Amp Power Operational Amplifier ...................... General Purpose Linear Devices
LH4161 High Speed Operational Amplifier ........................... General Purpose Linear Devices
LH4162 Dual High Speed Operational Amplifier ...................... General Purpose Linear Devices
LH4200 General Purpose GaAs FET Amplifier ....................... General Purpose Linear Devices
LH4266 SPDT RF Switch .......................................... Special Purpose Linear Devices
LH7001 Positive/Negative Adjustable Regulator ...................... General Purpose Linear Devices
LM10 Operational Amplifier and Voltage Reference ................... General Purpose Linear Devices
LM11 Operational Amplifier ........................................ General Purpose Linear Devices
xvii
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,---------------------------------------------------------------------------------,
Additional Available Linear Devices
(Continued)
Q)
c
Device
Databook
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Q)
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Q)
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'CiS
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"CiS
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LM 12(L) 150W Operational Amplifier ................................ General Purpose Linear Devices
LM78G 4-Terminal Adjustable Regulator ............................ General Purpose Linear Devices
LM78LOO Series 3-Terminal Positive Regulators ...................... General Purpose Linear Devices
LM78LXX Series 3-Terminal Positive Regulators ..................... General Purpose Linear Devices
LM78MG 4-Terminal Positive Regulator ............................. General Purpose Linear Devices
LM78MXX Series 3-Terminal Positive Regulators ..................... General Purpose Linear Devices
LM78S40 Universal Switching Regulator Subsystem .................. General Purpose Linear Devices
LM78XX Series Voltage Regulators ................................. General Purpose Linear Devices
LM79G 4-Terminal Adjustable Regulator ............................ General Purpose Linear Devices
LM79LXXAC Series 3-Terminal Adjustable Negative Regulators ........ General Purpose Linear Devices
LM79MOO Series 3-Terminal Negative Regulators .................... General Purpose Linear Devices
LM79MG 4-Terminal Positive Regulator ............................. General Purpose Linear Devices
LM79XX Series 3-Terminal Negative Regulators ...................... General Purpose Linear Devices
LM1 01 A Operational Amplifier ..................................... General Purpose Linear Devices
LM102 Voltage Follower .......................................... General Purpose Linear Devices
LM 104 Negative Regulator ........................................ General Purpose Linear Devices
LM1 05 Voltage Regulator ......................................... General Purpose Linear Devices
LM 106 Voltage Comparator ....................................... General Purpose Linear Devices
LM107 Operational Amplifier ....................................... General Purpose Linear Devices
LM108 Operational Amplifier ....................................... General Purpose Linear Devices
LM108A Operational Amplifier ..................................... General Purpose Linear Devices
LM1 09 5-Volt Regulator ........................................ ; .. General Purpose Linear Devices
LM110 Voltage Follower .......................................... General Purpose Linear Devices
LM111 Voltage Comparator ....................................... General Purpose Linear Devices
LM 112 Operational Amplifiers ...................................... General Purpose Linear Devices
LM 117 3-Terminal Adjustable Regulator ............................. General Purpose Linear Devices
LM117HV 3-Terminal Adjustable Regulator .......................... General Purpose Linear Devices
LM118 Operational Amplifiers ...................................... General Purpose Linear Devices
LM119 High Speed Dual Comparator ............................... General Purpose Linear Devices
LM120 Series 3-Terminal Negative Regulator ........................ General Purpose Linear Devices
LM 122 Precision Timer ............................................ Special Purpose Linear Devices
LM123 3-Amp, 5-Volt Positive Regulator ............................. General Purpose Linear Devices
LM 124 Low Power Quad Operational Amplifiers ...................... General Purpose Linear Devices
LM125 Voltage Regulator ......................................... General Purpose Linear Devices
LM126 Voltage Regulator ......................................... General Purpose Linear Devices
LM133 3-Amp Adjustable Negative Voltage Regulator ................. General Purpose Linear Devices
LM137 3-Terminal Adjustable Negative Regulator .................... General Purpose Linear Devices
LM137HV 3-Terminal Adjustable Negative Regulator (High Voltage) .... General Purpose Linear Devices
LM 138 3-Amp Adjustable Power Regulator .......................... General Purpose Linear Devices
LM139 Low Power Low Offset Voltage Quad Comparator .............. General Purpose Linear Devices
LM 140 Series 3-Terminal Positive Regulators ........................ General Purpose Linear Devices
LM 140L Series 3-Terminal Positive Regulators ....................... General Purpose Linear Devices
LM143 High Voltage Operational Amplifier ........................... General Purpose Linear Devices
LM144 High Voltage, High Slew Rate Operational Amplifier ............ General Purpose Linear Devices
LM145 Negative 3-Amp Regulator .................................. General Purpose Linear Devices
LM146 Programmable Quad Operational Amplifier .................... General Purpose Linear Devices
LM148 Quad 741 Operational Amplifiers ............................ General Purpose Linear Devices
LM 149 Wide Band Decompensated (Av(M IN) = 5) ................... General Purpose Linear Devices
LM150 3-Amp Adjustable Power Regulator .......................... General Purpose Linear Devices
LM158 Low Power Dual Operational Amplifier ........................ General Purpose Linear Devices
LM160 High Speed Differential Comparator .......................... General Purpose Linear Devices
LM161 High Speed Differential Comparator .......................... General Purpose Linear Devices
xviii
Additional Available Linear Devices (Continued)
Device
Databook
LM 193 Low Power Low Offset Voltage Dual Comparator .............. General Purpose Linear Devices
LM194 SuperMatch Pair ........................................... Special Purpose Linear Devices
LM195 Ultra Reliable Power Transistor .............................. Special Purpose Linear Devices
LM196 10 Amp Adjustable Voltage Regulator ........................ General Purpose Linear Devices
LM201 A Operational Amplifier ..................................... General Purpose Linear Devices
LM204 Negative Regulator ........................................ General Purpose Linear Devices
LM205 Voltage Regulator ......................................... General Purpose Linear Devices
LM206 Voltage Comparator ....................................... General Purpose Linear Devices
LM207 Operational Amplifier ....................................... General Purpose Linear Devices
LM208 Operational Amplifier ....................................... General Purpose Linear Devices
LM208A Operational Amplifier ..................................... General Purpose Linear Devices
LM210 Voltage Follower .......................................... General Purpose Linear Devices
LM211 Voltage Comparator ....................................... General Purpose Linear Devices
LM212 Operational Amplifiers ...................................... General Purpose Linear Devices
LM218 Operational Amplifiers ............................ , ......... General Purpose Linear Devices
LM219 High Speed Dual Comparator ............................... General Purpose Linear Devices
LM221 Precision Preamplifier ...................................... General Purpose Linear Devices
LM224 Low Power Quad Operational Amplifiers ...................... General Purpose Linear Devices
LM239 Low Power Low Offset Voltage Quad Comparator .............. General Purpose Linear Devices
LM246 Programmable Quad Operational Amplifier .................... General Purpose Linear Devices
LM248 Quad 741 Operational Amplifiers ............................ General Purpose Linear Devices
LM249 Wide Band Decompensated (Av(MIN) = 5) ................... General Purpose Linear Devices
LM258 Low Power Dual Operational Amplifier ........................ General Purpose Linear Devices
LM260 High Speed Differential Comparator .......................... General Purpose Linear Devices
LM261 High Speed Differential Comparator .......................... General Purpose Linear Devices
LM293 Low Power Low Offset Voltage Dual Comparator .............. General Purpose Lin.ear Devices
LM295 Ultra Reliable Power Transistor .............................. Special Purpose Linear Devices
LM301 A Operational Amplifier ..................................... General Purpose Linear Devices
LM302 Voltage Follower .......................................... General Purpose Linear Devices
LM304 Negative Regulator ........................................ General Purpose Linear Devices
LM305 Voltage Regulator ......................................... General Purpose Linear Devices
LM306 Voltage Comparator ....................................... General Purpose Linear Devices
LM307 Operational Amplifier ....................................... General Purpose Linear Devices
LM308 Operational Amplifier ....................................... General Purpose Linear Devices
LM308A Operational Amplifier ..................................... General Purpose Linear Devices
LM309 5-Volt Regulator ........................................... General Purpose Linear Devices
LM310 Voltage Follower .......................................... General Purpose Linear Devices
LM311 Voltage Comparator ....................................... General Purpose Linear Devices
LM312 Operational Amplifiers ...................................... General Purpose Linear Devices
LM317 3-Terminal Adjustable Regulator ............................. General Purpose Linear Devices
LM317HV 3-Terminal Adjustable Regulator .......................... General Purpose Linear Devices
LM317L 3-Terminal Adjustable Regulator ............................ General Purpose Linear Devices
LM318 Operational Amplifiers ...................................... General Purpose Linear Devices
LM319 High Speed Dual Comparator ............................... General Purpose Linear Devices
LM320 Series 3-Terminal Negative Regulator ........................ General Purpose Linear Devices
LM320L 3-Terminal Negative Regulator ............................. General Purpose Linear Devices
LM321 Precision Preamplifier ...................................... General Purpose Linear Devices
LM322 Precision Timer ............................................ Special Purpose Linear Devices
LM323 3-Amp, 5-Volt Positive Regulator ............................. General Purpose Linear Devices
LM324 Low Power Quad Operational Amplifiers ...................... General Purpose Linear Devices
LM325 Voltage Regulator ......................................... General Purpose Linear Devices
LM326 Voltage Regulator ......................................... General Purpose Linear Devices
xix
Additional Available Linear Devices (Continued)
Databook
Device
LM330 3-Terminal Positive Regulator ............................... General Purpose Linear Devices
LM333 3-Amp Adjustable Negative Voltage Regulator ................. General Purpose Linear Devices
LM337 3-Terminal Adjustable Negative Regulator .................... General Purpose Linear Devices
LM337HV 3-Terminal Adjustable Negative Regulator (High Voltage) .... General Purpose Linear Devices
LM337L 3-Terminal Adjustable Regulator ............................ General Purpose Linear Devices
LM338 3-Amp Adjustable Power Regulator .......................... General Purpose Linear Devices
LM339 Low Power Low Offset Voltage Quad Comparator .............. General Purpose Linear Devices
LM340 Series 3-Terminal Positive Regulators ........................ General Purpose Linear Devices
LM340L Series 3-Terminal Positive Regulators ....................... General Purpose Linear Devices
LM341 Series 3-Terminal Positive Regulators ........................ General Purpose Linear Devices
LM342 Series 3-Terminal Positive Regulators ........................ General Purpose Linear Devices
LM343 High Voltage Operational Amplifier ........................... General Purpose Linear Devices
LM344 High Voltage, High Slew Rate Operational Amplifier ............ General Purpose Linear Devices
LM345 Negative 3-Amp Regulator .................................. General Purpose Linear Devices
LM346 Programmable Quad Operational Amplifier .................... General Purpose Linear Devices
LM348 Quad 741 Operational Amplifiers ............................ General Purpose Linear Devices
LM349 Wide Band Decompensated (Av(MIN) = 5) ................... General Purpose Linear Devices
LM350 3-Amp Adjustable Power Regulator .......................... General Purpose Linear Devices
LM358 Low Power Dual Operational Amplifier ........................ General Purpose Linear Devices
LM359 Dual, High Speed, Programmable Current Mode (Norton)
Amplifier ...................................................... General Purpose Linear Devices
LM360 High Speed Differential Comparator .......................... General Purpose Linear Devices
LM361 High Speed Differential Comparator .......................... General Purpose Linear Devices
LM363 Precision Instrumentation Amplifier .......................... General Purpose Linear Devices
LM376 Voltage Regulator ......................................... General Purpose Linear Devices
LM380 Audio Power Amplifier ...................................... Special Purpose Linear Devices
LM381 Low Noise Dual Preamplifier ................................. Special Purpose Linear Devices
LM382 Low Noise Dual Preamplifier ................................. Special Purpose Linear Devices
LM383 7 Watt Audio Power Amplifier ................................ Special Purpose Linear Devices
LM384 5 Watt Audio Power Amplifier ................................ Special Purpose Linear Devices
LM386 Low Voltage Audio Power Amplifier ........................... Special Purpose Linear Devices
LM387 Low Noise Dual Preamplifier ................................. Special Purpose Linear Devices
LM388 1.5-Watt Audio Power Amplifier .............................. Special Purpose Linear Devices
LM389 Low Voltage Audio Power Amplifier with NPN Transistor Array ... Special Purpose Linear Devices
LM390 1 Watt Battery Operated Audio Power Amplifier ................ Special Purpose Linear Devices
LM391 Audio Power Driver .... ; .................................... Special Purpose Linear Devices
LM392 Low Power Operational Amplifier /voltage Comparator ......... General Purpose Linear Devices
LM393 Low Power Low Offset Voltage Dual Comparator .............. General Purpose Linear Devices
LM394 SuperMatch Pair ........................................... Special Purpose Linear Devices
LM395 Ultra Reliable Power Transistor .............................. Special Purpose Linear Devices
LM396 10 Amp Adjustable Voltage Regulator ........................ General Purpose Linear Devices
LM431A Adjustable Precision Zener Shunt Regulator ................. General Purpose Linear Devices
LM494 Pulse Width Modulated Control Circuit ........................ General Purpose Linear Devices
LM555 Timer ..................................................... Special Purpose Linear Devices
LM555C Timer ................................................... Special Purpose Linear Devices
LM556 Dual Timer ................................................ Special Purpose Linear Devices
LM556C Dual Timer ............................................... Special Purpose Linear Devices
LM565 Phase Locked Loop ........................................ Special Purpose Linear Devices
LM565C Phase Locked Loop ....................................... Special Purpose Linear Devices
LM566C Voltage Controlled Oscillator ............................... Special Purpose Linear Devices
LM567 Tone Decoder ............................................. Special Purpose Linear Devices
LM567C Tone Decoder ............................................ Special Purpose Linear Devices
xx
»
D.
Additional Available Linear Devices (Continued)
Device
D.
;:;:
Databook
LM592 Differential Video Amplifier .................................. Special Purpose Linear Devices
LM604 4-Channel MUX-Amp ....................................... General Purpose Linear Devices
LM607 Precision Operational Amplifier .............................. General Purpose Linear Devices
LM611 Adjustable Micropower Floating Voltage Reference and
Single-Supply Operational Amplifier ............................... General Purpose Linear Devices
LM613 Dual Operational Amplifiers, Dual Comparators, and Adjustable
Reference ..................................................... General Purpose Linear Devices
LM614 Quad Operational Amplifier and Adjustable Reference .......... General Purpose Linear Devices
LM621 Brushless Motor Commutator ................................ Special Purpose Linear Devices
LM627 Precision Operational Amplifiers ............................. General Purpose Linear Devices
LM628 Precision Motion Controller .................................. Special Purpose Linear Devices
LM629 Precision Motion Controller .................................. Special Purpose Linear Devices
LM637 Precision Operational Amplifiers ............................. General Purpose Linear Devices
LM675 Power Operational Amplifier ................................. General Purpose Linear Devices
LM710 Voltage Comparator ....................................... General Purpose Linear Devices
LM723 Voltage Regulator ......................................... General Purpose Linear Devices
LM725 Operational Amplifier ....................................... General Purpose Linear Devices
LM733 Differential Video Amplifier .................................. Special Purpose Linear Devices
LM733C Differential Video Amplifier ................................. Special Purpose Linear Devices
LM741 Operational Amplifier ....................................... General Purpose Linear Devices
LM759 Power Operational Amplifier ................................. General Purpose Linear Devices
LM776 Multi-Purpose Programmable Operational Amplifier ............ General Purpose Linear Devices
LM831 Low Voltage Audio Power Amplifier ........................... Special Purpose Linear Devices
LM832 Dynamic Noise Reduction System DNR ....................... Special Purpose Linear Devices
LM833 Dual Audio Operational Amplifier ............................. General Purpose Linear Devices
LM837 Low Noise Quad Operational Amplifier ....................... General Purpose Linear Devices
LM903 Fluid Level Detector ........................................ Special Purpose Linear Devices
LM1035 Dual DC Operated TonelVolume/Balance Circuit ............. Special Purpose Linear Devices
LM1036 Dual DC Operated TonelVolume/Balance Circuit ............. Special Purpose Linear Devices
LM1037 Dual Four-Channel Analog Switch .............. , ......... , .. Special Purpose Linear Devices
LM1038 Dual Four-Channel Analog Switch .... , ...................... Special Purpose Linear Devices
LM1040 Dual DC Operated TonelVolume/Balance Circuit with Stereo
Enhancement Facility ........................................... Special Purpose Linear Devices
LM1042 Fluid Level Detector ....................................... Special Purpose Linear Devices
LM 1044 Analog Video Switch ....................................... Special Purpose Linear Devices
LM1112A Dolby B-Type Noise Reduction Processor ................... Special Purpose Linear Devices
LM 1112B Dolby B-Type Noise Reduction Processor ................... Special Purpose Linear Devices
LM1112C Dolby B-Type Noise Reduction Processor ................... Special Purpose Linear Devices
LM1131 A Dual Dolby B-Type Noise Reduction Processor .............. Special Purpose Linear Devices
LM1201 Video Amplifier System .................................... SpeCial Purpose Linear Devices
LM1203 RGB Video Amplifier System ............................... Special Purpose Linear Devices
LM1211 Broadband Demodulator System ............................ Special Purpose Linear Devices
LM1391 Phase-Locked Loop ....................................... Special Purpose Linear Devices
LM1414 Dual Differential Voltage Comparator ........................ General Purpose Linear Devices
LM1458 Dual Operational Amplifier ................................. General Purpose Linear Devices
LM1496 Balanced Modulator-Demodulator ........................... Special Purpose Linear Devices
LM1514 Dual Differential Voltage Comparator ........................ General Purpose Linear Devices
LM1524D Regulating Pulse Width Modulator ......................... General Purpose Linear Devices
LM1525A Pulse Width Modulator ................................... General Purpose Linear Devices
LM1527A Pulse Width Modulator ................................... General Purpose Linear Devices
LM1558 Dual Operational Amplifier ................................. General Purpose Linear Devices
LM1575-5.0 Simple Switcher Step-Down Voltage Regulator ............ General Purpose Linear Devices
xxi
o·
:::J
!!!..
~
iii"
eCD
r-
:5'
CD
m
.....
C
CD
<
c;.
CD
til
Additional Available Linear Devices (Continued)
Device
Databook
LM1578A Switching Regulator ..................................... General Purpose Linear Devices
LM1596 Balanced Modulator-Demodulator ........................... Special Purpose Linear Devices
LM1800 Phase-Locked Loop FM Stereo Demodulator ................. Special Purpose Linear Devices
LM 180 1 Battery Operated Power Comparator ........................ Special Purpose Linear Devices
LM1812 Ultrasonic Transceiver ..................................... Special Purpose Linear Devices
LM 1815 Adaptive Sense Amplifier ................................... Special Purpose Linear Devices
LM 1818 Electronically Switched Audio Tape System .................. Special Purpose Linear Devices
LM1819 Air-Core Meter Driver ...................................... Special Purpose Linear Devices
LM1823 Video IF Amplifier/PLL Detection System .................... Special Purpose Linear Devices
LM 1830 Fluid Detector ............................................ Special Purpose Linear Devices
LM1837 Low Noise Preamplifier for Autoreversing Tape Playback
System ........................................................ Special Purpose Linear Devices
LM1851 Ground Fault Interrupter ................................... Special Purpose Linear Devices
LM1863 AM Radio System for Electronically Tuned Radio .............. Special Purpose Linear Devices
LM1865 Advanced FM IF System ................................... Special Purpose Linear Devices
LM 1866 Low Voltage AM/FM Receiver .............................. Special Purpose Linear Devices
LM1868 AM/FM Radio System ..................................... Special Purpose Linear Devices
LM1870 Stereo Demodulator with Blend ............................. Special Purpose Linear Devices
LM1871 HC Encoder/Transmitter ................................... Special Purpose Linear Devices
LM1872 Radio Control Receiver/Decoder ............................ Special Purpose Linear Devices
LM1875 20 Watt Power Audio Amplifier .............................. Special Purpose Linear Devices
LM1877 Dual Power Audio Amplifier ................................. Special Purpose Linear Devices
LM1880 No-Holds Vertical/Horizontal ............................... Special Purpose Linear Devices
LM1881 Video Sync Separator ..................................... Special Purpose Linear Devices
LM1884 TV Stereo Decoder ........................................ Special Purpose Linear Devices
LM1 886 TV Video Matrix D to A ..................................... Special Purpose Linear Devices
LM1889 TV Video Modulator ....................................... Special Purpose Linear Devices
LM1893 Carrier Current Transceiver ................................. Special Purpose Linear Devices
LM1894 Dynamic Noise Reduction System DNR ...................... Special Purpose Linear Devices
LM1895 Audio Power Amplifier ..................................... Special Purpose Linear Devices
LM1896 Dual Power Audio Amplifier ................................. Special Purpose Linear Devices
LM1897 Low Noise Preamplifier for Tape Playback System ............. Special Purpose Linear Devices
LM1921 1 Amp Industrial Switch .................................... Special Purpose Linear Devices
LM1946 Over/Under Current Limit Diagnostic Circuit .................. Special Purpose Linear Devices
LM1949 Injector Drive Controller .................................... Special Purpose Linear Devices
LM1951 Solid State 1 Amp Switch .................................. Special Purpose Linear Devices
LM1964 Sensor Interface Amplifier .................................. Special Purpose Linear Devices
LM1965 Advanced FM IF System ................................... Special Purpose Linear Devices
LM2002 8 Watt Audio Power Amplifier ............................... Special Purpose Linear Devices
LM2005 20 Watt Automotive Power Amplifier ......................... Special Purpose Linear Devices
LM2065 Advanced FM IF Sys~em ................................... Special Purpose Linear Devices
LM2524D Regulating Pulse Width Modulator ......................... General Purpose Linear Devices
LM2575-5.0 Simple Switcher Step-Down Voltage Regulator ............ General Purpose Linear Devices
LM2578A Switching Regulator ..................................... General Purpose Linear Devices
LM2579 Switching Regulator ...................................... General Purpose Linear Devices
LM2877 Dual 4 Watt Power Audio Amplifier .......................... Special Purpose Linear Devices
LM2878 Dual 5 Watt Power Audio Amplifier .......................... Special Purpose Linear Devices
LM2879 Dual 8 Watt Audio Amplifier ................................. Special Purpose Linear Devices
LM2889 TV Video Modulator ....................................... Special Purpose Linear Devices
LM2893 Carrier Current Transceiver ................................. Special Purpose Linear Devices
LM2896 Dual Power Audio Amplifier ................................. Special Purpose Linear Devices
LM2900 Quad Amplifier ........................................... General Purpose Linear Devices
xxii
Additional Available Linear Devices (Continued)
Device
Databook
LM2901 Low Power Low Offset Voltage Quad Comparator ............. General Purpose Linear Devices
LM2902 Low Power Quad Operational Amplifiers ..................... General Purpose Linear Devices
LM2903 Low Power Low Offset Voltage Dual Comparator ............. General Purpose Linear Devices
LM2904 Low Power Dual Operational Amplifier ....................... General Purpose Linear Devices
LM2905 Precision Timer ........................................... Special Purpose Linear Devices
LM2907 Frequency to Voltage Converter ............................ Special Purpose Linear Devices
LM2917 Frequency to Voltage Converter ............................ Special Purpose Linear Devices
LM2924 Low Power Operational AmplifierlVoltage Comparator ........ General Purpose Linear Devices
LM2925 Low Dropout Regulator with Delayed Reset .................. General Purpose Linear Devices
LM2930 3-Terminal Positive Regulator .............................. General Purpose Linear Devices
LM2931 Series Low Drop-Out Regulators ............................ General Purpose Linear Devices
LM2935 Low Dropout Dual Regulator ............................... General Purpose Linear Devices
LM2936 Ultra-Low Quiescent Current 5V Regulator ................... General Purpose Linear Devices
LM2940 1A Low Dropout Regulator ................................. General Purpose Linear Devices
LM2940C 1A Low Dropout Regulator ............................... General Purpose Linear Devices
LM2941 1A Low Dropout Adjustable Regulator ....................... General Purpose Linear Devices
LM2941 C 1A Low Dropout Adjustable Regulator ..................... General Purpose Linear Devices
LM2984C Microprocessor Power Supply System ..................... General Purpose Linear Devices
LM3045 Transistor Array ........................................... Special Purpose Linear Devices
LM3046 Transistor Array ........................................... Special Purpose Linear Devices
LM3080 Operational Transconductance Amplifier .................... General Purpose Linear Devices
LM3086 Transistor Array ........................................... Special Purpose Linear Devices
LM3089 FM Receiver IF System .................................... Special Purpose Linear Devices
LM3146 High Voltage Transistor Array ............................... Special Purpose Linear Devices
LM3189 FM IF System ............................................ Special Purpose Linear Devices
LM3301 Quad Amplifier ........................................... General Purpose Linear Devices
LM3302 Low Power Low Offset Voltage Quad Comparator ............. General Purpose Linear Devices
LM3303 Quad Operational Amplifier ................................ General Purpose Linear Devices
LM3361 A Low Voltage/Power Narrow Band FM IF System ............. Special Purpose Linear Devices
LM3401 Quad Amplifier ........................................... General Purpose Linear Devices
LM3403 Quad Operational Amplifier ................................ General Purpose Linear Devices
LM3503 Quad Operational Amplifier ................................ General Purpose Linear Devices
LM3524D Regulating Pulse Width Modulator ......................... General Purpose Linear Devices
LM3525A Pulse Width Modulator ................................... General Purpose Linear Devices
LM3527 A Pulse Width Modulator ................................... General Purpose Linear Devices
LM3578A Switching Regulator ..................................... General Purpose Linear Devices
LM3820 AM Radio System ......................................... Special Purpose Linear Devices
LM3900 Quad Amplifier ........................................... General Purpose Linear Devices
LM3905 Precision Timer ........................................... Special Purpose Linear Devices
LM3909 LED Flasher/Oscillator .................................... Special Purpose Linear Devices
LM3914 Dot/Bar Display Driver ..................................... Special Purpose Linear Devices
LM3915 Dot/Bar Display Driver ..................................... Special Purpose Linear Devices
LM3916 Dot/Bar Display Driver ..................................... Special Purpose Linear Devices
LM4136 Quad Operational Amplifier ................................ General Purpose Linear Devices
LM4250 Programmable Operational Amplifier ........................ General Purpose Linear Devices
LM4500A High Fidelity FM Stereo Demodulator with Blend ............. Special Purpose Linear Devices
LM6118 Fast Settling Dual Operational Amplifier ..................... General Purpose Linear Devices
LM6121 High Speed Buffer ........................................ General Purpose Linear Devices
LM6125 High Speed Buffer ........................................ General Purpose Linear Devices
LM6161 High Speed Operational Amplifier ........................... General Purpose Linear Devices
LM6164 High Speed Operational Amplifier ........................... General Purpose Linear Devices
LM6165 High Speed Operational Amplifier ........................... General Purpose Linear Devices
xxiii
Additional Available Linear Devices (Continued)
Device
Databook
LM6218 Fast Settling Dual Operational Amplifier ..................... General Purpose Linear Devices
LM6221 High Speed Buffer ........................................ General Purpose Linear Devices
LM6225 High Speed Buffer ........................................ General Purpose Linear Devices
LM6261 High Speed Operational Amplifier ........................... General Purpose Linear Devices
LM6264 High Speed Operational Amplifier ........................... General Purpose Linear Devices
LM6265 High Speed Operational Amplifier ........................... General Purpose Linear Devices
LM6313 High Speed, High Power Operational Amplifier ............... General Purpose Linear Devices
LM6321 High Speed Buffer ........................................ General Purpose Linear Devices
LM6325 High Speed Buffer ........................................ General Purpose Linear Devices
LM6361 High Speed Operational Amplifier ........................... General Purpose Linear Devices
LM6364 High Speed Operational Amplifier ........................... General Purpose Linear Devices
LM6365 High Speed Operational Amplifier ........................... General Purpose Linear Devices
LM7800 Series Voltage Regulators ................................. General Purpose Linear Devices
LM7900 Series 3-Terminal Negative Regulators ...................... General Purpose Linear Devices
LM13080 Programmable Power Operational Amplifier ................. General Purpose Linear Devices
LM13600 Dual Operational Transconductance Amplifier with
Linearizing Diodes and Buffers ................................... General Purpose Linear Devices
LM13700 Dual Operational Transconductance Amplifier with
Linearizing Diodes and Buffers ................................... General Purpose Linear Devices
LM18293 Four Channel Push Pull Driver ............................. Special Purpose Linear Devices
LM77000 Power Operational Amplifier .............................. General Purpose Linear Devices
LMC555 CMOS Timer ............................................. Special Purpose Linear Devices
LMC567 Low Power Tone Decoder ................................. Special Purpose Linear Devices
LMC568 Low Power Phase-Locked Loop ............................ Special Purpose Linear Devices
LMC660 CMOS Quad Operational Amplifier .......................... General Purpose Linear Devices
LMC662 CMOS Dual Operational Amplifier .......................... General Purpose Linear Devices
LMC669 Auto Zero ............................................... General Purpose Linear Devices
LMC835 Digital Controlled Graphic Equalizer ......................... Special Purpose Linear Devices
LMC7660 Switched Capacitor Voltage Converter ..................... General Purpose Linear Devices
LP124 Micropower Quad Operational Amplifier ....................... General Purpose Linear Devices
LP265 Micropower Programmable Quad Comparator ................. General Purpose Linear Devices
LP311 Voltage Comparator ........................................ General Purpose Linear Devices
LP324 Micropower Quad Operational Amplifier ....................... General Purpose Linear Devices
LP339 Ultra-Low Power Quad Comparator ........................... General Purpose Linear Devices
LP365 Micropower Programmable Quad Comparator ................. General Purpose Linear Devices
LP395 Ultra Reliable Power Transistor ............................... Special Purpose Linear Devices
LP2902 Micropower Quad Operational Amplifier ...................... General Purpose Linear Devices
LP2950 5V Adjustable Micropower Voltage Regulator ................. General Purpose Linear Devices
LP2951 Adjustable Micropower Voltage Regulator .................... General Purpose Linear Devices
LPC660 CMOS Quad Operational Amplifier .......................... General Purpose Linear Devices
LPC662 CMOS Dual Operational Amplifier ........................... General Purpose Linear Devices
OP-07 Low Offset, Low Drift Operational Amplifier .................... General Purpose Linear Devices
TL081CP Wide Bandwidth JFET Input Operational Amplifier ........... General Purpose Linear Devices
TL082CP Wide Bandwidth Dual JFET Input Operational Amplifier ....... General Purpose Linear Devices
xxiv
...
0
0
~NatiOnal
III
III
::u
(D
Semiconductor
...
(D
(D
::s
(')
CROSS REFERENCE BY PART NUMBER
(D
0"
'<
"U
-...
A complete interchangeability list of Linear IC's offered by most Integrated Circuit
Manufacturers are listed in this section and reference the nearest National Semiconductor Corp. direct replacement or recommended replacement with either an
improved or functional replacement. The following notations are appended to assist you in finding the best option.
I\)
Z
c
3
0"
...
(D
No reference note ...... "DIRECT REPLACEMENT"
Note (1) ............... "IMPROVED REPLACEMENT" Pinfor-Pin replacement with "SUPERIOR" Electrical Specifications.
Note (2) ............... "FUNCTIONAL
REPLACEMENT"
Similar device. Consult datasheet to
determine the suitability for specific
application.
Note (3) ............... "SIMILAR DEVICE" with superior
performance. Consult datasheet to
determine suitability of the replacement for specific application.
ANALOG
DEVICES
AD0042
AD101A
AD201A
AD301A
AD3542
AD5035
AD506
AD509
AD521
AD521
AD524
AD537
AD562
AD563
AD565A
AD566A
AD567
AD573
AD581
AD581
AD582
AD583
AD588
AD589M
AD589U
AD590
AD590
AD590
AD590
AD611J
AD611K
AD614
AD624
AD650
AD651
AD654
NATIONAL
LH0042
LM101A
LM210A
LM301A
LH0042
LH0042
LH0022
LHOO03
LH0036
LM363
LH0038
LM331
DAC1266
DAC1265
DAC1265
DAC1266
DAC1230
ADC1005
LH0070
LM581
LF398
LF198
LM369
LM385
LM185
LM134
LM135
LM34
LM35
LF411C
LF411AC
LH0086
LH0038
LM331
LM331
LM331
(2)
(1)
(1)
(1)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(3)
(3)
(2)
(2)
(1)
(2)
(3)
(2)
(1)
(1)
(2)
(2)
(3)
(3)
(1)
(1)
(2)
(2)
(2)
(2)
(2)
AD673
AD741
AD7502
AD7516
AD7523
AD7523
AD7523
AD7524
AD7524
AD7524
AD7533
AD7533
AD7533
AD7541
AD7541
AD7541A
AD7541A
AD7542
AD7542
AD7542
AD7545
AD7545
AD7545
AD7548
AD7548
AD7548
AD7552
AD7552
AD7571
AD7571
AD7575
AD7576
AD7578
AD7578
AD7820
ADDAC-08
ADDAC-08
ADC0841
LM741
LF13509
CD4066B
DAC0830
DAC0831
DAC0832
DAC0830
DAC0831
DAC0832
DAC1020
DAC1021
DAC1022
DAC1218
DAC1219
DAC1218
DAC1219
DAC1208
DAC1209
DAC1210
DAC1208
DAC1209
DAC1210
DAC1230
DAC1231
DAC1232
ADC1220
ADC1225
ADC1005
ADC1025
ADC0820
ADC0820
ADC1205
ADC1225
ADC0820
DAC0800
DAC0801
xxv
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(1)
(1)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
ADDAC-08
ADDAC80
ADDAC85
ADLH0032
ADLH0033
ADOP07
DAC0802
DAC1280+
DAC2180+
LH0032
LH0033
LM607
(1)
(1)
(2)
(2)
(1)
APEX
PAOl
PAOl
PA07
PAOlO
PAOlO
PAOll
PA51
PA73
NATIONAL
LH010l
LM12
LM12
LH010l
LM12
LM12
LM12
LM12
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
BURR-BROWN
3507
3533
3542
3550
3551
3553
3554
3571
3572
3573
3626
3629
3606A6
3606A6
HOS-l00
INA102
SHC298A
SHC80
SHC85
NATIONAL
LM6361
LH0033
LH0042
LM6361
LM6361
LH0063
LH0032
LM675
LH0021
LM675
LH0036
LH0038
LH0084
LH0086
LH0033
LH0038
LF398A
LF398
LF398
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(1)
(2)
(2)
...
Q)
.Q
E
-...
::J
Z
ra
a..
>-
.Q
Q)
(.)
s::::
...
Q)
Q)
Q)
a:
III
III
...
0
(..)
CTS
CTSOOO2
CTSOO04
CTS0021
CTS0024
CTS0032
CTS0033
CTS0041
CTS0042
CTS2101A
CTS2111
NATIONAL
LH002
LHOO04
LH0021
LH0024
LH0032
LH0033
LH0041
LH0042
LH2101A
LH2111
ELANTEC
EHA2500
EHA2502
EHA2505
EHA2510
EHA2512
EHA2515
EHA2520
EHA2522
EHA2525
EHA2600
EHA2602
EHA2605
EHA2620
EHA2622
EHA2625
EL2006
EL2006C
ELHOO02
ELH0021
ELH0032
ELH0033
ELH0041
ELH0101
NATIONAL
LM6161
LM6161
LM6361
LM6161
LM6161
LM6361
LM6164
LM6164
LM6364
LM6161
LM6161
LM6361
LM6164
LM6164
LM6364
LM6161
LM6261
LHOO02
LH0021
LH0032
LH0033
LH0041
LH0101
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(1 )
(1 )
(1 )
(1 )
(1 )
(1 )
EXAR
XR-1001
XR-1002
XR084
XR084M
XR1458
XR146
XR246
XR346
NATIONAL
MF4C-100
MF4C-50
LF347
LF147
LM1458
LF146
LF246
LF346
(1 )
(1 )
(1 )
(1 )
(1 )
(1)
(1 )
(1 )
HARRIS (Incl.
GE/RCAI
INTERSIL)
AD7520
AD7520
AD7521
AD7521
AD7521
AD7530
AD7530
AD7530
AD7531
AD7531
AD7531
AD7533
AD7533
AD7533
AD7541
AD7541
ADC0801
ADC0802
ADC0803
ADC0804
CA081
NATIONAL
DAC1021
DAC1022
DAC1220
DAC1221
DAC1222
DAC1020
DAC1021
DAC1022
DAC1220
DAC1221
DAC1222
DAC1020
DAC1021
DAC1022
DAC1218
DAC1219
ADC0801
ADC0802
ADC0803
ADC0804
LF411M
(3)
(3)
(3)
(2)
CA081A
CA081B
CA081C
CA082
CA082A
CA082B
CA082C
CA084
CA084B
CA084C
CA124
CA139
CA139A
CA1458
CA1558
CA158
CA158A
CA224
CA239
CA239A
CA258
CA258A
CA301A
CA307
CA31 05
CA311
CA324
CA3290
CA339
CA339A
CA3401
CA358
CA358A
CA741
CA747
CA748
DG201
DG211
DG212
HA-OP07
HA2400
HA2404
HA2405
HA2406
HA2500
HA2502
HA2505
HA2510
HA2512
HA2515
HA2520
HA2520
HA2522
HA2522
HA2525
HA2525
HA2530
HA2535
HA2540
HA2541-2
HA2541-5
HA2542
HA2542-2
HA2542-5
HA2600
HA2602
HA2605
HA2620
HA2622
HA2625
HA2640
LF411C
LF411C
TL081C
LF412M
LF412C
LF412C
TL082C
LF147
LF347B
LF347
LM124
LM139
LM139A
LM1458
LM1558
LM158
LM158A
LM224
LM239
LM239A
LM258
LM258A
LM301A
LM307
LM675
LM311
LM324
LM393
LM339
LM339A
LM3401
LM358
LM358A
LM741
LM747
LM748
LF11201
LF13201
LF13202
LM607
LM604AM
LM604AM
LM604C
LM604C
LM6161
LM6161
LM6361
LM6161
LM6161
LM6361
LHOO03
LM6164
LHOO03
LM6164
LHOO03
LH6364
LH0024
LH0024
LH0032
LM6161
LM6361
LH0032
LM6164
LM6164
LM6161
LM6161
LM6361
LM6164
LM6164
LM6364
LHOO04
xxvi
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(1 )
(1 )
(1 )
(1 )
(1 )
(1 )
(1)
(1 )
(1 )
(1 )
(1 )
(1 )
(1 )
(1 )
(2)
(1 )
(1 )
(2)
(1 )
(1 )
(1 )
(1 )
(1 )
(1 )
(1 )
(1)
(1 )
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(1)
(2)
(1)
(2)
(1)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(1 )
HA5033
HA5162
HA5180
HF-10
HI-201
HI-300
ICH8530
ICL7114
ICL7114
ICL7660
ICL8069
ICL8069
IH5009
IH5010
IH5011
IH5012
IH61 08
IH6208
LM741
J.LA748
LH0033
LH0062
LH0052
MF10
LF13201
AH5020
LH0101
ADC1205
ADC1225
LMC7660
LM313
LM385-1.2
AH5009
AH5010
AH5011
AH5012
LF13508
LF13509
LM741
LM748
HEWLETT·
PACKARD
HCTL-100
NATIONAL
LM628
(3)
HITACHI
HA13421A
HA17082
HA17082A
HA17084
HA17084A
HA17094
HA17301
HA17324
HA17339
HA17358
HA17393
HA17458
HA17741
HA17747
HA17901
HA17902
HA17903
NATIONAL
LM18293
LF353
LF412
LF347
LF347B
LM2904
LM3301
LM324
LM339
LM358
LM393
LM1458
LM741
LM747
LM2901
LM2902
LM2903
(3)
(1 )
(1 )
(1 )
(1 )
(1 )
(1 )
(1 )
(1 )
(1 )
(1 )
(1 )
(1 )
(1 )
(1 )
(1 )
(1 )
LINEAR
TECHNOLOGY
AD581
AD581
LM1009M
LM129
LM134
LM185
LM199
LM234
LM329
LM334
LM385
LM399
LT1001
LT1004C
LT1004M
LT1009C
LT1019C
LT1019M
LT1020
LT1021C
LT1021 M
LT1029C
LT1029M
LT1031
LT117A
NATIONAL
LH0070
LM581
LM136-2.5
LM129
LM134
LM185
LM199
LM234
LM329
LM334
LM385
LM399
LM607A
LM385
LM185
LM336-2.5
LM368
LM168
LP2951
LM369
LM169
LM336-5.0
LM136-5.0
LH0070
LM117A
(1 )
(2)
(1 )
(2)
(2)
(2)
(2)
(1 )
(1 )
(2)
(2)
(3)
(1 )
(1 )
LT123A
LT138A
LT150A
LT317A
LT323A
LT338A
LT350A
REF-01
REF-01
SG1524
SG1525A
SG1527A
SG3524
SG3525A
SG3527A
LM123A
LM138A
LM150A
LM317A
LM323A
LM338A
LM350A
LM168
LM368
LM1524D
LM1525A
LM1527A
LM3524D
LM3525A
LM3527A
(1)
(1)
(1)
(2)
(2)
(1)
(2)
(2)
LSI
COMPUTER
LS7261
LS7263
NATIONAL
LM621
LM621
MICRA
MCOOO2
MCOOO3
MCOOO4
MCOO32
MCOO33
MCOO41
MCOO63
NATIONAL
LHOOO2
LHOOO3
LHOOO4
LHOO32
LHOO33
LHOO41
LHOO63
MICRO POWER
MP108
MP108A
MP155
MP155A
MP156
MP156A
MP157
MP157A
MP208
MP20CA
MP210JA
MP308
MP308A
MP355A
MP356A
MP357A
MP5010G
MP5010G
MP5010H
MP5010H
MP5010L
MP5010L
MPOP07
NATIONAL
LM108
LM108A
LF155
LF155A
LF156
LF156A
LF157
LF157A
LM208
LM208A
LH2108A
LM308
LM308A
LF355A
LF356A
LF357A
LM185
LM385
LM185
LM385
LM185
LM385
LM607
MOTOROLA
AD562A
AD563A
DAC-08
DAC-08
DAC-08
LM109H
LM109K
LM117K
LM123K
LM137K
LM150K
LM2931
LM309K
LM317K
NATIONAL
DAC1266
(2)
(2)
DAC1265
DAC0800
DAC0801
DAC0802
LM109H
LM109KSTEEL
LM117KSTEEL
LM123K STEEL
LM137K STEEL
LM150K STEEL
LM2931
LM309K STEEL
LM317K STEEL
(3)
(3)
(1)
LM323K
LM337K
LM350K
MC1408
MC1408
MC1408
MC1414
LM1436
MC14442
MC14444
MC145040
MC145041
MC1458
MC1496
MC1508
MC1514
MC1536
MC1558
MC1596
MC1709
MC1710
MC1723
MC1723C
MC1741
MC1747
MC1748
MC3301
MC3302
MC3361
MC34001
MC34001A
MC34001B
MC34002
MC34002A
MC34002B
MC34004
MC34004
MC34004B
MC34004B
MC3401
MC3410
MC3412
MC35001
MC35001A
MC35001B
MC35002
MC35002A
MC35002B
MC3510
MC4741
MC78LXXACG
MC78LXXACP
MC78LXXCG
MC78LXXCP
MC78MXXCT
MC78MXXCT
MC78MXXCT
MC78XXACT
MC78XXCK
MC78XXCT
MC79LXXACG
MC79LXXACP
MC79LXXCP
MC79LXXCP
MC79MXXAKC
MC79XXACT
MC79XXAKC
MC79XXCK
MC79XXCK
MC79XXCT
LM323K STEEL
LM337K STEEL
LM350K STEEL
DAC0806
DAC0807
DAC0808
LM1414
LM343
ADC0829
ADC0830
ADC0811
ADC0811
LM1458
LM1496
DAC0808
LM1514
LM143
LM1558
LM1596
LM709
LM710
LM723
LM723C
LM741
LM747
LM748
LM3301
LM3302
LM3361A
LF351
LF411C
LF411C
LF353
LF412A
LF412C
LF147
LF347
LF147
LF347B
LM3401
DAC1020
DAC1265
LF411M
LF411M
LF411M
LF412M
LF412AM
LF412M
DAC1020
LM348
LM78LXXACH
LM78LXXACZ
LM78LXXCH
LM78LXXSACZ
LM341P-XX
LM342P-XX
LM78MXXCT
LM340AT-XX
LM78XXCK
LM78XXCT
LM320H-XX
LM320LZ-XX
LM79LXXCZ
LM79LXXCZ
LM320MP-XX
LM320T-XX
LM320K-XX
LM320K-XX
LM79XXCK
LM79XXCT
xxvii
(1)
(2)
(2)
(2)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(2)
(1)
(1)
(1)
(1)
(1)
(1)
(2)
PRECISION
MONOLITHIC
INC.
ADC-910
ADC-910
AMP-01
BUF-03
DAC-02
DAC-02
DAC-02
DAC-03
DAC-03
DAC-03
DAC-05
DAC-05
DAC-05
DAC-08
DAC-08
DAC-08
DAC-100
DAC-100
DAC-100
DAC-1408
DAC-1408
DAC-1408
DAC-312
DAC-8012
DAC-8012
DAC-8012
DAC-888
DAC-888
DAC-888
MUX-08E
MUX-24E
OP-05
OP-07
OP-15
OP-215
OP-77
PM-108
PM-10BA
PM-139
PM-139A
PM-155
PM-155A
PM-156
PM-156A
PM-15?
PM-157A
PM-208
PM-208A
PM-2108A
PM-308
PM-30BA
PM-339A
PM-355
PM-355A
PM-356
PM-357
PM-357A
PM-725
PM-741
PM-747
PM-7533
PM-7533
PM-7533
PM-7541
PM-7541
PM356A
PM420
0.,
0
NATIONAL
ADC1005
ADC1025
LHOO38
LHOO33
DAC1020
DAC1021
DAC1022
DAC1020
DAC1021
DAC1022
DAC1020
DAC1021
DAC1022
DACOBOO
DAC0801
DAC0802
DAC1020
DAC1021
DAC1022
DAC0806
DACOB07
DAC080B
DAC1266
DAC1208
DAC1209
DAC1210
DAC-0830
DAC0831
DAC0832
LF13508
LF13509
LM607
LM607
LF411
LF412
LM607
LM108
LM108A
LM139
LM139A
LF155
LF155A
LF156
LF156A
LF157
LF157A
LM208
LM208A
LH2108A
LM308
LM308A
LM339A
LF355
LF355A
LF356
LF357
LF357A
LM725
LM741
LM747
DAC1020
DAC1021
DAC1022
DAC1218
DAC1219
LF356A
LM124
III
III
(2)
(2)
(2)
(1)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(1)
(1)
(1)
(1)
(1)
:0
CD
.,CD
CD
:::I
0
CD
e-
'<
"tJ
-
II)
.,
Z
r::
3
e-
.,CD
...
Q)
.Q
E
::s
Z
-...
C'CI
Q.
>-
.Q
Q)
(,)
s::::
...
Q)
Q)
00-
Q)
a:
II>
II>
...
0
0
REF-01GJ
REF-02
REF-43
REF-01
SW-06B
SW-06F
SW-06G
SW-201B
SW-201F
SW-201G
SW-202B
SW-202F
SW-202G
LM368-1.0
LM368-5.0
LM368-2.5
LM369
LFl1333
LF13333
LF13333
LFl1201
LF13201
LF13201
LFl1202
LF13202
LF13202
RAYTHEON
LP365
RG1458
RG1558
RG714
RG741
RG747
REF-Ol
REF-On
REF-02
REF-03
NATIONAL
LP365
LM1458
LM1558
LM607
LM741
LM747
LM369
LM368
LM368-5.0
LM368-5.0
SAMSUNG
KA3524
KA431
KA78S40
LM741
MG78LXX
MG78MXX
MG78XX
MG79MXX
MG79XX
NATIONAL
LM3524D
LM431
LM78S40
LM741
LM78LXX
LM78MXX
LM78XX
LM79MXX
LM79XX
SGSTHOMSON
L123GB
L293
L4940
L4941
L4960
L4962
L78MXXGV
L78S05GV
L78XXAGV
L78XXGT
L78XXGV
L790XXAGV
L79XXGT
L79XXGV
LF198
LF298
LF398
LM105H
LM109K
LMl17H
LMl17K
LMl17K
LM123K
LM134
LM135
LM137H
LM137K
LM138K
LM234
LM235
LM2930A
LM2931A
NATIONAL
LM723GN
LM18293
LM2940T-5.0
LM2940T-5.0
LM2579
LM2579
LM341P-XX
LM323K-5.0
LM340AT-XX
LM78XXGK
LM78XXGT
LM320T-XX
LM79XXGK
LM79XXGT
LF198A
LF298
LF398A
LM105H
LM109K STEEL
LM117H
LFl17K
LFl17K STEEL
LF123K STEEL
LM134
LM135
LM137H
LM137K STEEL
LM138KSTEEL
LM234
LM235
LM2930T-5.0
LM2931AT-5.0
(1)
(3)
(1)
(1)
(1)
(1)
(1)
(3)
(1)
(1)
(2)
(2)
(2)
(2)
(2)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
LM2935
LM305H
LM309H
LM309K
LM317H
LM317K
LM317K
LM317T
LM323K
LM334
LM335
LM335A
LM337H
LM337K
LM338K
LM748
LM7805MK
SG1524
SG1525A
SG1527A
SG2524
SG3524
SG3525A
SG3527A
TBG0136
TGA3089
TDA2310
,..,A741
,..,A748
,..,A7805GK
,..,A7812GK
,..,A7812MK
,..,A7815GK
,..,A7815MK
,..,A7905GK
,..,A7905MK
,..,A7912GK
,..,A7912MK
,..,A7915GK
I-'A7915MK
LM2935
LM305H
LM309H
LM309K STEEL
LM317H
LM317K
LM317K STEEL
LM317T
LM323K STEEL
LM334
LM335
LM335A
LM337H
LM337K STEEL
LM338K STEEL
LM748
LM140K-5.0
LM1524D
LM1525A
LM1527A
LM2524D
LM3524D
LM3525A
LM3527A
LM336
LM3089
LM381
LM741
LM748
LM7805KG
LM7812KG
LM140K-12
LM7815KG
LM140K-15
LM7905KG
LM120K-5.0
LM7912KG
LM120K-12
LM7915KG
LM120K-15
SIEMENS
TGA365
NATIONAL
LH0101
SIGNETICS
78LXXAGS
78LXXADB
78LXXGDB
78LXXGS
78XXGU
78XXDA
79XXGU
79XXDA
ADG0801
ADG0802
ADG0803
ADG0804
ADG0805
DAG-08
DAG-08
DAG-08
LF198
LF298
LF398
LM109DB
LM309DA
LM309DB
LM340XXDA
LM340XXLL
MG1408
MG1408
MG1408
NATIONAL
LM78LXXAGZ
LM78XXAGH
LM78LXXGH
LM78LXXAGZ
LM78XXGT
LM78XXGK
LM79XXGT
LM79XXGK
ADG0801
ADG0802
ADG0803
ADG0804
ADG0805
DAG0800
DAG0801
DAG0802
LF198
LF298
LF398
LM109H
LM309K
LM309H
LM340KXX
LM340T-XX
DAG0806
DAG0807
DAG0808
xxviii
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
MG1496N
MG1508
MG1596K
NE4558
NE4558D
NE4558N
NE5034
NE5118
NE529
NE532
NE5410
NE5532
NE5532N
NE5532P
NE555N
SA532
SA534
SE5118
SE529
SE532
SE5410
SE567
,..,A723GF
,..,A723GL
,..,A723GN
,..,A723F
,..,A723L
,..,A741
,..,A747
LM1496N
DAG0808
LM1596H
LM833
LM833GM
LM833GN
ADG0841
DAG0830
LM361
LM358
DAG1020
LM833
LM833GN
LM833GN
LM555GN
LM2904
LM2902
DAG0830
LM161
LM158
DAG1020
LM567
LM723GJ
LM723GH
LM723GN
LM723J
LM723H
LM741
LM747
SILICON
GENERAL
SG10l
SG101A
SG104
SG105
SG107
SG109
SGl17
SGl173
SGl17A
SG117MV
SG120-XX
SG123
SG123A
SG124
SG137
SG138
SG138A
SG140-XX
SG1436
SG150
SG150A
SG1524
SG1524B
SG1525A
SG1527A
SG1536
SG201
SG201A
SG204
SG205
SG207
SG224
SG2524
SG2524B
SG301A
SG304
SG305
SG307
SG309
SG317
NATIONAL
LM101A
LM101A
LM104
LM105
LM107
LM109
LMl17
LM675
LMl17A
LMl17HV
LM120-XX
LM123
LM123A
LM124
LM137
LM138
LM138A
LM140-XX
LM343
LM150
LM150A
LM1524D
LM1524D
LM1525A
LM1527A
LM143
LM201A
LM201A
LM204
LM205
LM207
LM224
LM2524D
LM2524D
LM301A
LM304
LM305
LM307
LM309
LM317
(2)
(2)
(2)
(2)
(2)
(1)
(1)
(2)
(2)
(2)
(1)
(1)
(2)
(1)
(1)
(2)
(2)
(1)
(1)
(1)
(1)
(1)
(2)
(1)
(1)
(1)
(1)
(1)
(1)
...
0
SG3173
SG317A
SG317MV
SG320-XX
SG323
SG323A
SG324
SG337
SG338
SG338A
SG340-XX
SG350
SG350A
SG3524
SG3524B
SG3525A
SG3527A
SG723
SG723C
SG741
SG78XX
SG78XXA
SG78XXAC
SG78XXC
SG79XX
SG79XXA
SG79XXAC
SG79XXC
LM675
LM317A
LM317HV
LM320-XX
LM323
LM323A
LM324
LM337
LM338
LM338A
LM340-XX
LM350
LM350A
LM3524D
LM3524D
LM3525A
LM3527A
LM723
LM723C
LM741
LM140-XX
LM140A-XX
LM340A-XX
LM78XXC
LM120-XX
LM120-XX
LM320-XX
LM79XXC
SILICONIX
DG201
DG202
DG211
DG212
DG508
DG509
NATIONAL
LF13201
LF13202
LF13201
LF13202
LF13508
LF13509
SPRAGUE
SG3525A
SG3527A
UDN2993B
NATIONAL
LM3525A
LM3527A
LM18293
TELEDYNE
TPOO32
TPOO33
NATIONAL
LHOO32
LHOO33
TEXAS
INSTRUMENTS
ADC0801
ADC0802
ADC0803
ADC0804
ADC0805
ADC0808
ADC0809
ADC0831
ADC0832
NATIONAL
ADC0801
ADC0802
ADC0803
ADC0804
ADC0805
ADC0808
ADC0809
ADC0831
ADC0832
(2)
(1)
(1)
(1)
(2)
(2)
(2)
(2)
(3)
ADC0834
ADC0838
LM317KC
RC4558
RC4588D
RV4558D
TL071
TL071A
TL071B
TL072
TL072A
TL072B
TL074
TL074A
TL081
TL081A
TL081B
TL082
TL082A
TL082B
TL084
TL084A
TL087
TL088
TL288
TL487N
TL489N
TL490N
TL491N
TL520
TL521
TL522
TL530
TL531
TL532
TLC532A
TL533
TLC533A
TLC274AC
TLC274AI
TLC274AM
TLC274BC
TLC274BI
TLC274BM
TLC274C
TLC2741
TLC274M
TLC540
TLC541
TLC549
TL061
TL061A
TL061B
TL062
TL062A
TL062B
TL064
ADC0834
ADC0838
LM317T
LM833
LM833CM
LM833CM
LF351
LF411
LF411
LF353
LF412
LF412
LF347
LF347B
TL081
LF411
LF411
TL082
LF412
LF412
LF347
LF347B
LF411A
LF411A
LF412A
LM3915N
LM3914N
LM3914N
LM3914N
ADC0848
ADC0848
ADC0848
ADC0830B
ADC0830C
ADC0829B
ADC0829B
ADC0829C
ADC0829C
LMC660AI
LMC660AI
LMC660AM
LMC660AI
LMC660AI
LMC660AM
LMC660C
LMC660AI
LMC660AM
ADC0811
ADC0811
ADC0831
LF441
LF441
LF441A
LF442
LF442A
LF442
LF444
xxix
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
TL064A
/LA709
/LA723CJ
/LA723CN
/LA723MJ
/LA733CN
/L A741
/L A747
/LA78LXXACL
/LA78MXXCKD
/LA78XXCKC
/LA79MXXCKD
/LA79XXCKC
LF444A
LM709
LM723CJ
LM723CN
LM723J
LM733CN
LM741
LM747
LM78LXXACZ
LM78MXXCP
LM78XXCT
LM79MXXCP
LM79XXCT
TOSHIBA
TA7504
TA75339
TA75358
TA75393
TA75902
NATIONAL
LM741
LM2901
LM2904
LM2903
LM2902
UNITRODE
L293
UC117
UC137
UC150
UC1524
UC1524A
UC1525A
UC1527A
UC2524
UC2524A
UC317
UC337
UC350
UC3524
UC3524A
UC3525A
UC3527A
UC494
UC78XXACK
UC78XXAK
UC78XXCK
UC78XXCK
UC78XXK
UC79XXACK
UC79XXAK
UC79XXCK
UC79XXK
NATIONAL
LM18293
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LM150
LM1524D
LM1524D
LM1525A
LM1527A
LM2524D
LM2524D
LM317
LM337
LM350
LM3524D
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LM494
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II~~~~~~~II
xxxii
LTC
Section 1
Active Filters
II
Section 1 Contents
Active Filters Definition ofTerms .....................................................
Active Filters Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AF100 Universal Active Filter ........................................................
AF150 Universal Wideband Active Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AF151 Dual Universal Active Filter... ..... .......... ..... ........... .. .... ........ .. ..
LMF90 4th-Order LMCMOSTM Programmable Elliptic Notch Filter... ... ...... . .. . ...... . ..
LMF100 High Performance Dual Switched Capacitor Filter... ..... ...... ... .. ........ . ...
LMF120 Mask Programmable Switched Capacitor Filter......... ............ .. ........ ..
MF4 4th Order Switched Capacitor Butterworth Lowpass Filter . . . . . . . . . . . . . . . . . . . . . . . . . . .
MF5 Universal Monolithic Switched Capacitor Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MF6 6th Order Switched Capacitor Butterworth Lowpass Filter . . . . . . . . . . . . • . . . . . . . . . . . . . .
MF8 4th Order Switched Capacitor Bandpass Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MF10 Universal Monolithic Dual Switched Capacitor Filter...............................
1-2
1-3
1-4
1-5
1-23
1-42
1-51
1-71
1-93
1-106
1-119
1-134
1-152
1-174
~
~.
~National
~ Semiconductor
::!!
::;:
CD
T
c
Active Filters
Definition of Terms
!1
S·
::;:
o·
::l
%
'elK: the switched capacitor filter external clock frequency.
'0: center of frequency of the second order function com-
HOHP: the gain in (V IV) of the highpass output of each
MF10 as f -+- fCLK/2.
plex pole pair. fo is measured at the bandpass output of
each % MFl 0, and it is the frequency of the bandpass peak
occurrence.
Q: quality factor of the 2nd order function complex pole pair.
Q is also measured at the bandpass output of each % MFl 0
and it is the ratio of fo over the -3 dB bandwidth of the 2nd
order bandpass filter. The value of Q is not measured at the
lowpass or highpass outputs of the filter, but its value relates to the possible amplitude peaking at the above outputs.
Qz: the quality factor of the 2nd order function complex zero
pair, if any. (Qz is a parameter used when an allpass output
is sought and unlike Q it cannot be directly measured).
9.
....~
3en
'z: the center frequency of the 2nd order function complex
zero pair, if any. If fz is different from fo, and if the Qz is
quite high it can be observed as a notch frequency at the
allpass output.
'notch: the notch frequency observed at the notch output(s)
of the MF10.
HONt: the notch output gain as f -+- 0 Hz.
Hosp: the gain in (V IV) of the bandpass output at f = fo.
HOlP: the gain in (V IV) of the lowpass output of each %
MF10 at f -+- 0 Hz.
HON2: the notch output gain as f -+- fCLK/2.
II
1-3
~NatiOnal
Semiconductor
Active Filter Selection Guide
Device #
Type
Function
Max
Order
Max Freq
Accuracy
Freq
Range
Typ.Q
Accuracy
Max
FxQ
AF100
Universal
Universal
2nd
±1.0%
0.1-10 kHz
±7.5%
50kHz
AF150
Wideband
Universal
Universal
2nd
±1.0%
0.1-100 kHz
±7.5%
200 kHz
AF151
Dual
Universal
Universal
4th
±1.0%
0.1-10kHz
±7.5%
50 kHz
MF10(S, n
Universal
Universal
4th
±0.6%
0.1-30 kHz
±2%
200 kHz
MF8
....g
."
~National
~ Semiconductor
AF100 Universal Active Filter
General Description
Features
The AF100 state variable active filter is a general second
order lumped RC network. Only four external resistors program the AF100 for specific second order functions. Lowpass, highpass, and bandpass functions are available simultaneously at separate outputs. Notch and all pass functions
are available by summing the outputs in the uncommitted
output summing amplifier. Higher order systems are realized
by cascading AF100 active filters with appropriate programming resistors.
•
•
•
•
•
•
•
•
Any of the classical filter configurations, such as Butterworth, Bessel, Cauer, and Chebyshev can be formed.
•
•
•
Military or commercial specifications
Independent Q, frequency, gain adjustments
Low sensitivity to external component variation
Separate lowpass, highpass, bandpass outputs
Inputs may be differential, inverting, or non-inverting
Allpass and notch outputs may be formed using uncommitted amplifier
Operates to 10kHz
Q range to 500
Power supply range
± 5V to ± 18V
Frequency accuracy
± 1 % unadjusted
Q frequency product :;;;50,000
Connection Diagrams
Ceramic Dual-In-Line Package
NO
PIN
NO
PIN
INT I
BANDPASS
OUTPUT
-Y
AMP
OUTPUT
Plastic Dual-In-Line Package
AMP
-INPUT
GND
INT I
BANDPASS HIGHPASS
OUTPUT OUTPUT
INPUT
INPUT
lOOk
INPUT
INPUT
HIGHPASS
OUTPUT
.Y
LOWPASS AMP
OUTPUT .,NPUT
INT 2
-Y
NO
PIN
AMP
.,NPUT
AMP
-INPUT
GND
AMP
OUTPUT
.Y
INT 2
LOWPASS
OUTPUT
TLIKI'011'-2
TLIKI'O"'-'
Top View
*Note: Internally connected. Do not use.
Top View
Order Number AF100-1CJ or AF100-2CJ
See NS Package Number HY13A
Order Number AF100-1CN or AF100-2CN
See NS Package Number N16A
Metal Can Package
Order Number AF100-1CJ, AF100-1G, AF100-2CG or
AF100-2G
See NS Package Number H12B
TLlKI'011'-3
Top View
1-5
II
CI
CI
....
LL.
011(
Absolute Maximum Ratings
Operating Temperature
AF100-1CJ, AF100-2CJ,
AF100-1CG, AF100-2CG,
AF1 00-1 CN, AF100-2CN
AF100-1G, AF100-2G
Storage Temperature
AF100-1G, AF100-2G
AF100-1CG, AF100-2CG,
AF100-1CJ, AF100-2CJ,
AF1 00-1 CN, AF1 00-2CN
If MIlitary/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications..
Supply Voltage
±18V
Power Dissipation
900 mW/Package
(500 mW/Amp)
Differential Input Voltage
Output Short Circuit Duration (Note 1)
Lead Temperature (Soldering, 10 sec.)
±36V
Infinite
300'C
- 25'C to + 85'C
- 55'C to + 125'C
-65'Cto
+ 125'C
-25'C to
+ 100'C
Electrical Characteristics (Complete Active Filter) (Note 2)
Parameter
Min
Conditions
Typ
Max
Units
Frequency Range
fc x Q
~
50,000
10k
Hz
QRange
fc x Q
~
50,000
500
Hz/Hz
fa Accuracy
AF100-1, AF100-1C
AF100-2, AF100-2C
fc X Q ,;; 10,000, TA
fc x Q,;; 10,000, TA
= 25'C
= 25'C
±2.5
±1.0
%
±150
ppml'C
fc x Q,;; 10,000TA
= 25'C
fa Temperature Coefficient
QAccuracy
±50
Q Temperature Coefficient
Power Supply Current
Vs
±7.5
%
±300
±750
ppml'C
2.5
4.5
mA
= ±15V
Electrical Characteristics (Internal Op Amp) (Note 3)
Typ
Max
Units
1.0
6.0
mV
4
50
nA
Input Bias Current
30
200
Input Resistance
2.5
MO
Parameter
Input Offset Voltage
Conditions
Min
Rs~10kO
Input Offset Current
nA
Large Signal Voltage Gain
RL;;' 2k
VOUT = ±10V
25
160
V/mV
Output Voltage Swing
RL
RL
= 10kO
= 2kO
±12
±10
±14
±13
V
Input Voltage Range
±12
~
V
Common Mode Rejection Ratio
Rs
10kO
70
90
Supply Voltage Rejection Ratio
Rs,;;10kO
77
96
dB
dB
Output Short Circuit Current
25
mA
Slew Rate (Unity Gain)
0.6
V/",s
Small Signal Bandwidth
1
MHz
Phase Margin
Degrees
60
Note 1: Arry of the amplifiers can be shorted 10 ground indefinHely, however more than one should nol be simultaneously shorted as the maximum junction
temperature will be exceeded.
Note 2: Speciflcations apply for Vs ~ ±15V, over -25'C 10 + 85'C for the AF100-IC and AF100·2C and over -55'C to + 125'C for the AF100·l andAF100·2,
unless otherwise specified.
Nota 3: Specifications apply forVs ~ ±15V, TA ~ 25'C.
1-6
»
.....
g
."
Application Information
BANDPASS
HIGHPASS
LDWPASS AMP IN-
,-------lOOk
IN2o-~~~~~~--r_------r_--_+------_+
AMPOUT
IN lO-~_-----"''''''--------.......
AMPIN+
TLlK/10111-4
FIGURE 1. AF100 Schematic
CIRCUIT DESCRIPTION AND OPERATION
If the output is taken from the output of A3, numerator coef·
ficients
and a2 equal zero and the transfer function be·
comes:
as
A schematic of the AF1 00 is shown in Figure 1. Amplifier A 1
is a summing amplifier with inputs from integrator A2 to the
non·inverting input and integrator A3 to the inverting input.
Amplifier A4 is an uncommitted amplifier.
T(s) = _ _ _a-=-1_ _
s2+wOs+w02
Q
By adding external resistors the circuit can be used to generate the second order system
Using proper input and output connections the circuit can
also be used to generate the transfer functions for a notch
and all pass filter.
T(s) = a3 s2 + a2s + a1
s2+b2S+ b 1
In the transfer function for a notch function a2 becomes
zero, a1 equals 1, and
equals wz 2 . The transfer function
becomes:
The denominator coefficients determine the complex pole
pair location and the quality of the poles where
000 =
.Jb1 =
as
the radian center frequency
T(s) =
Q = : ; = the quality of the complex pole pair
S2 + wz
----'=--2
s2 + WOs + 0002
Q
If the output is taken from the output of A 1, numerator coef·
ficients a1 and a2 equal zero, and the transfer function be·
comes:
a3 s2
T(s) = - - - " " " - ' - - s2+wOs+w02
Q
(notch)
In the allpass transfer function al = 1, a2 = -Wo/Q and
= 000 2 . The transfer function becomes:
as
s2 - WOs +'0002
(highpass)
Q
T(s)=----s2+WOs+W02
(all pass)
Q
If the output is taken from the output of A2, numerator coefficients al and
equal zero and the transfer function becomes:
as
COMMON CONFIGURATIONS
The specific transfer functions for some of the most useful
circuit configurations using the AF100 are illustrated in Figures 2 through 8. Also included are the gain equations for
each transfer function in the frequency band of interest, the
Q equation, center frequency equation and the Q determining resistor equation.
(bandpass)
lOOk
lOOk
(Iowpass)
-=
eh
HIGHPASS
eb
BANDPASS
e,
LOWPASS
"External components
FIGURE 2. Non-Inverting Input (Q
1-7
>
QMIN. see Q Tuning Section)
TLlK/10111-5
III
C)
C)
....
u..
cc
r-------------------------------------------------------------------------------------,
Applications Information (Continued)
a) Non-inverting input (Figure 2) transfer equations are:
s2 [1 +
~1+
~]
5
10
eh =
RQ
(highpass)
A.
-=-__
eb = ____
[1
1.1
RQ
(Iowpass)
"'1"'2 [
!L =
where
el
elN
I
+ ~]
1 + RIN
~ = ____-=____1_0_5-=
A.
el = "'1"'2----------elN
A.
109
"'1 =-RF-l
1~~1
105 ] "'1 +0.1 "'1"'2
1+-+RQ
1.1
(1. + 10
RIN
5
R
1 +....!t:!.
___=-____
10_5-=
A.
1.1
+ RIN)
A. = s2 +
S "'1
1
104
=1.1+FiQ
~I
elN
01
00
= 010
+ RIN
105
104
1
+-
1
+ RIN
=-~
105
~:
"'0 = ~0.1 "'1"'2
Q=[1+~] 'i~
104
lOOk
1.1
°h
HIGHPASS
1
°b
BANOPASS
0,
LOWPASS
TUK/l0111-6
'Externa' components
FIGURE 3. Non-Inverting Input
(0 < 0MIN. see a Tuning Section)
1-8
+ RQ
1~5
+-
RQ
elN 8 -+
-1-
104]
+0
104
1.1 +FiQ
~I
(~~:::)
[
RQ
+ RIN + RIN)
105
(Iowpass)
where
RIN
11
(1
(bandpass)
+~]
11
8""':0=
RQ -
(highpass)
1.1
+ RIN + RIN
A. = s2 + s[
105
A.
-s"'l [
]
105
S2[',':;]
(bandpass)
A.
elN
~=
elN
R1.1 R ]
[
1 +....!t:!. +....!t:!.
5 __R_Q=
,-1_0_
-S"'l
b) Non-inverting input (Figure 3) transfer equations are:
v .,;:;-
RIN
.
+0.1 "'1"'2
J:-
Applications Information
."
.....
(Continued)
o
lOOk
o
lOOk
lOOk
R,j'
-=
RQ'
°b
°h
HIGHPASS
BANDPASS
°1
°1
°b
°h
HIGHPASS
LOWPASS
TL/KI101"-7
BANDPASS
LOWPASS
TLlK/'O"'-B
·External components
·External components
FIGURE 4. Inverting Input
FIGURE 5. Differential Input
c) Inverting input (Figure 4) transfer function equations are:
d) Differential input (Figure 5) transfer function equations
are:
-s2 104
~=~
(highpass)
I!.
elN
~=
.!!t=~
I!.
104
- CLll CLl2 !L =
RIN
elN
I!.
~=
(Iowpass)
where
1.1
+104]
-
I!. = s2+SCLll [
1
I
eb
elN
I
01
=
010
1
5
+10 ]
RQ
1.1 + 104
RIN
RQ = _ Q (10
~0.1 :~
+ 0.1 CLllCLl2
+-+-Ra
RINI
CLlo = ~0.1 CLllCLl2
(highpass)
Q = [1
+
~~ + -~-~5-,] ~0.1
104
1.1 +-R
CLl2
CLll
IN2
(bandpass)
RQ = _-:-_--:-_ _1.:..;0:....5_:--_ _ __
+RIN
5
0:
1
(Iowpass)
~0.1
1.: -~-~4-~05]
I!. = s2 + S CLll [
Q
~0.1 :~
CLlo = ~0.1 CLllCLl2
Q= [
(Iowpass)
Ra
RIN
4(
10
105)
- 1+RIN
RQ
104
1.1
(bandpass)
+ 0.1 CLllCLl2
+-
105
RIN
104
et
elN S'-O
00
RIN
105
(highpass)
104
- sCLll - RIN2
elN
I!.
104
- CLll CLl2 - !L =
RIN2
elN
I!.
109
CLll=RFI
where
(bandpass)
elN
I
RIN2
I!.
elN
104
SCLll-
eh
elN s'-
S2~
CLl2
CLll
104 ) _ 1
1.1 + RIN
1-9
(
104 )
105
1.1 + -R-IN-2 - 1 - -R-IN-'
III
Applications Information (Continued)
100k
100k
-=
·Extemal components
FIGURE 6. Output Notch Using All Four Amplifiers
f) Input notch (Figure 7) transfer function equations are:
C
10 : 9 [S2
+ WZ2]
en = -----;:-.::...,,--:-:::-::::-7-elN
[ 1.1 RO ]
s2 + S w1 105 + RO + w02
109
w1 = RF1
109
W2 =
"Fi;;;
_
/RF2 X 10 9
Wz - wo-y
RzCZ
I
en I
elN 01-
Wo = 40.1 W1 W 2
RF2
Rz
en
elN 01-0
Cz
00
= -10- 9
g) Allpass (Figure 8) transfer function equations are:
~
I
en
elN 01
=
OIZ
-0
= _ [S2 - sW1
s2
elN
+ s W1
[~] +
[_1_.1_]
2 + RIN
RO
100k
105
2+-
0=~~0.1W2
1.1
109
W1 = RF1
w1
109
w2 = RF2
Wo = 40.1 W1W2
Time delay at W = 20 seconds
Wo
'Extemal components
TL/K/l0lll-l0
FIGURE 7. Input Notch Using Three Amplifiers
1-10
W02]
+ w02
r-------------------------------------------------------------------,~
Applications Information
."
.....
(Continued)
o
o
lOOk
lOOk'
lOOk
hR'
> .....-0·0
RD'
tExtemal components
TUK/l0lll-ll
FIGURE 8. Allpass
FREQUENCY TUNING
To tune the AF100 two resistors are required for frequencies between 200 Hz and 10kHz. For lower frequencies "T"
tuning or addition of external capacitors is required. Using
external capacitors allows the user to go as low in frequen·
cy as he desires. "T" tuning and external capacitors can be
used together.
Two resistor tuning for 200 Hz to 10 kHz
Rf=
"T" resistive tuning for fo
< 200 Hz
R12
Rs=--Rf - 2Rt
RF
Rl<2
50.33 x 106
fo
n
AFlOO
AFlOO
113
RT
TUK/l0111-12
FIGURE 9. Resistive Tuning
TL/K/l0111-14
FIGURE 10. T Tuning
GRAPH B. "T" Tuning
GRAPH A. Resistive Tuning
1000
lOOk
S...
lDk
'"z~
en
...in
.
'"I
'"
10".
lk
lDk
lOOk
fe-FREQUENCY (Hz)
lk
10 1 10 10
lk
FREQUENCY (Hz)
TUK/l0111-13
TUK/l0111-15
1-11
o
o
.,...
u..
QMIN.
Non-Inverting Input
0.05033
Rf = fo(C + 1 x 10-9)
sa
lOOkem
ma
R1Na
-l00k
r-RIN=lMEG~~
RI~'hl0k
10k,,_
CJ
'"
=J=C
Rf
3
13
14
15
7
lkllll_"IIIfII.
l00L-LLUllill-~~~-LLU~
moo
0.1
1.0
100
10
Q
TL/K/l0111-19
TLlK/l0111-16
For Q
FIGURE 11. Low Frequency RC Tuning
< QMIN in non-inverting mode:
104
QTUNING
RO
To tune the Q of an AF1 00 requires one resistor from pins 1
or 2 to ground. The value of the Q tuning resistor depends
on the input connection and input resistance as well as the
value of the Q. The Q of the unit is inversely proportional to
resistance to ground at pin 1 and directly proportional to
resistance to ground from pin 2.
=
--""""'-(--10""'
5"")-+1
03162
.
0 RIN
-
- 11
.
R
o-_VVINI,,--'-Il +
6 GRAPH C. QMIN. Non-Inverting Input
10
1+ 105
AF100
2
r-- -
105 _ _
TL/K/l0111-20
"'
FIGURE 13. Q Tuning for Q < QMIN.
Non-Inverting Input
1.0
10
GRAPH E. Q < QMIN.
Non-Inverting Input
100
l00k~~!lII~~iI~~~1I
Q
11111
TL/K/l0111-17
For Q
> OMIN in non-inverting mode:
RO
-
5 _ ---=5
= _ _ _1_0_
l +
o-....R"'IN,..,.......-'-I
RIN = lOOk
10k
I
CJ
'"
10
3.480 - 1 - RIN
RIN = 10k
lk
100
l...-.l....!..L.U.WJ......!...J....l..Wlll......!....l...LJ.J.J.llJ
0.01
AF100
0.1
1.0
10
Q
TL/K/l0111-21
TLlK/l0111-18
FIGURE 12. Q Tuning for Q > QMIN.
Non-Inverting Input
1-12
»
."
.....
Applications Information (Continued)
o
For any 0 in inverting mode:
105
RO =
o
GRAPH G. Input RC Notch
3.160 (1.1
l0r!ll!_
+ ~~:) -
1
~N
2
o---'WIr---t-
0::
AF100
0.1 _ _
OD1LV~~~~~~~~~
0.1
10
1.0
100
fe/fz
TL/K/l0111-22
TLlK/l0111-25
FIGURE 14. Q Tuning Inverting Input
For output notch tuning:
GRAPH F. Q Tuning
Inverting Input
It.t _ _
RHP- CzyRLP
fa
10
RHP
b
l00k _ _
HP
IXI N =lOOk
a
0::
10k
~OUTPUT
AF100
~R,IN,=!I~Oklr-...:~II~111
LP
15
'.
RLP
TLlK/l0111-26
Q
FIGURE 16. Output Notch
TL/K/l0111-23
NOTCH TUNING
Two methods to generate notches are the RC input and
lowpass/highpass summing. The RC input method requires
adding a capacitor and resistor connected to the two inte·
grator inputs. The capacitor connects to "Int 1" and the
resistor connects to "Int 2". The output summing requires
two resistors connected to the lowpass and highpass output.
GRAPH H. Output Notch
II
10
1
D..
....I
0::
~
::
0::
For input RC notch tuning:
0.1
/
RZ = RF X 10- 9 (!Q)2
Cz
fz
AFlOO
0.01
0.1
.!.Lo OUTPUT
1.0
10
100
fz/fo
TL/K/l0111-27
.t~
INPUT
fCz
0--+--------'
7
RZ
TLlK/l0111-24
FIGURE 15. Input RC Notch
1-13
g
...
II..
cc
Applications Information (Continued)
TUNING TIPS
Notch Tuning
If a circuit has a jw axis zero pair the notch can be tuned by
adjusting the ratio of the summing resistors (Iowpass/highpass summing) or the input resistance (input RC).
In either case the signal is connected to the input and the
proper resistor is adjusted for a null at the output.
In applications where 2% to 3% accuracy is not sufficient to
provide the required filter response, the AF100 stages can
be tuned by adding trim pots or trim resistors in series or
parallel with one of the frequency determining resistors and
the 0 determining resistor.
When tuning a filter section, no matter what output configuration is to be used in the circuit, measurements are made
between the input and the bandpass (pin 13) output.
Before any tuning is attempted the lowpass (pin 7) output
should be checked to see that the output is not clipping. At
the center frequency of the section the lowpass output is
10 dB higher than the bandpass output and 20 dB higher
than the highpass. This should be kept in mind because if
clipping occurs the results obtained when tuning will be incorrect.
Special Cases
When using the input RC notch the unit cannot be tuned
through the normal input so an additional 100k resistor can
be added at pin 1 and the unit can be tuned normally. Then
the 100k input resistor should be grounded and the notch
tuned through the normal RC input.
An alternative way of tuning is to tune using the 0 resistor
as the input. This requires the 0 resistor be lifted from
ground and connecting the Signal source to the normally
grounded end of the 0 resistor. This has the problem that
when the 0 resistor is grounded after tuning, its value is
decreased by the output impedance of the source. This
technique has the advantage of not requiring an additional
resistor.
Frequency Tuning
By adlusting the resistance between pins 7 and 13 the center frequency of a section can be adjusted. If the input is
through pin 1 the phase shift at center frequency will be
180· and if the input is through pin 2 the phase shift at
center frequency will be 0·. Adjusting center frequency by
phase is the most accurate but tuning for maximum gain is
also correct.
TUNING PROCEDURE (See Figure 17)
Center Frequency Tuning
Set oscillator to center frequency desired for the filter section, adjust amplitude and check that Clipping does not occur at the lowpass output pin 5 (AF100J).
"Q"Tuning
The "0" is tuned by adjusting the resistance between pin 1
or 2 and ground. Low 0 tuning resistors will be from pin 2 to
ground (0 < 0.6). High 0 tuning resistors will be from pin 1
to ground. To tune the 0 correctly the signal source must
have an output impedance very much lower than the input
resistance of the filter since the input resistance affects the
Q. The input must be driven through the same resistance
the circuit will see to obtain precise adjustment.
Adjust the resistance between pins 13 and 7 until the phase
shift between input and bandpass output is 180·.
QTunlng
Set oscillator to upper or lower 45· frequency (see tuning
tips) and tune the 0 reSistor until the phase shift is 135·
(upper 45· frequency) or 225· (lower 45· frequency).
Zero Tuning
Set the oscillator output to the zero frequency and tune the
zero resistor for a null at the ouput of the summing amplifier.
The lower 3 dB (45·) frequency, fl' and the upper 3 dB (45·)
frequency, fH' can be calculated by the following equations:
fH =
C~ + ~L~r + 1) x (fo)
Gain AdJust
Set the oscillator to any desired frequency and the gain can
be adjusted by measuring the output of the summing amplifier and adjusting the feedback resistance.
where fo = center frequency
fl =
(~L~r + 1 - 2~) x (fo)
When adjusting the 0, set the signal source to either fH or fl
and adjust for 45· phase change or a 3 dB gain change.
Q
TLlK/10111-28
FIGURE 17. Filter Tuning Setup
1-14
l:-
Applications Information
....o
."
(Continued)
V+
V+
o
V+
lOOk
lOOk
ArIOO
ArlOO
RQ
2RQ
lOOk
12
V/2 (PSEUDO GROUND)
TUK/IOIII-30
TUK/IOIII-29
FIGURE 19. Single Power Supply
Connection Using Resistive Dividers
FIGURE 18. Single Power Supply Connection Using
Uncommitted Amplifier to Split Supply
v+
V+
lOOk
II
lOOk
II
lOOk
lOOk
I.045k
I.045k
v-
V-
TL/K/l0111-31
Performance
0.1 dB ripple passband
0.1 dB notch width
= 100 Hz
40 dB notch width = 6.25 Hz
4th Order 1010 Hz Notch
o
STAGE 1
Fe
= 1031.1
e=
FZ
=
Hz
28.34
1012.2 Hz
-10
!
-20
~
-30
~
V
'\
V
"
-40
-50
STAGE 2
Fe
I
= 989.3 Hz
e = 28.34
FZ
=
1007.8 Hz
-60
960
980
1000
1020
1040
FREQUENCY (Hz)
TUK/l0111-32
FIGURE 20. 1010 Hz Notch-Telephone Holding Tone Reject Filter
FILTER DESIGN
found, it is transformed to obtain the transfer function for the
actual filter desired. Graph I shows the lowpass amplitude
response which can be defined by four quantities.
Since most filter tables are in terms of a normalized lowpass
prototype. the filter to be designed is usually reduced to a
lowpass prototype. After the lowpass transfer function is
1-15
•
CI
CI
....u..
Applications Information (Continued)
CC
To obtain the lowpass prototype for the notch filter (Graph
L) AMAX and AMIN are the same as for the lowpass case
and
GRAPH I. Lowpass Prototype Response
.L
f
fc = 1
AlIA)(
CD'
where fa
~
= .Jf1f5 = .Jf2I4
~
GRAPH L. Notch Response
-L
T
AtotIN
Ie
AwAX
Is
LOG FREQUENCY
TL/K/l0111-33
AMAX = the maximum peak to peak ripple in the passband.
AWIN
AMIN = the minimum attenuation in the stopband.
fc
= the passband cuttoff frequency.
fs
= the stopband start frequency.
By defining these four quantities for the lowpass prototype
the normalized pole and zero locations and the Q (quality)
of the poles can be determined from tables or by computer
programs.
~ I
YIYl
TUK/l0111-36
Normalized Lowpass Transformed to
Un-Normalized Lowpass
To obtain the lowpass prototype for the highpass filter
(Graph J) AMAX and AMIN are the same as for the lowpass
case but fc = 1/f2 and fs = 1/f1.
The normalized lowpass filter has the passband edge normalized to unity. The un-normalized lowpass filter instead
has the passband edge at fc. The normalized and un-normalized lowpass filters are related by the transformation s
= SCllC. This transforms the normalized passband edge s =
j to the un-normalized passband edge s = jCllC.
GRAPH J. Highpass Response
Normalized Lowpass Transformed to
Un-Normalized Highpass
The transformation that can be used for lowpass to highpass is S = Cllc/s. Since S is inversely proportional to s, the
low frequency and high frequency responses are interchanged. The normalized lowpass 1/(82 + S/Q + 1) transforms to the un-normalized highpass
s2
S2+ CllC S + CllC2
TL/K/l0111-34
Q
To obtain the lowpass prototype for a bandpass filter (Graph
K) AMAX and AMIN are the same as for the lowpass case but
fc
where f3
=1
= .Jf1f5 =.Jf214
fs
Normalized Lowpass Transformed to Un-Normalized
Bandpass
= f5 -
f1
f4 - f2
i.e., geometric symmetry
The transformation that can be used for lowpass to bandpass is S = (s2 + Cl102)/BWs where Cl102 is the center frequency of the desired bandpass filter and BW is the ripple
bandwidth.
f5 - f1 = AMIN bandwidth
f4 - f2 = Ripple bandwidth
Normalized Lowpass Transformed to Un-Normalized
Bandstop (or Notch)
GRAPH K. Bandpass Response
The bandstop filter has a reciprocal response to a bandpass
filter. Therefore a bandstop filter can be obtained by first
transforming the lowpass prototype to a highpass and then
performing the bandpass transformation.
JLr---~~~~----
T
AlIA)(
SELECTION OF TRANSFER FUNCTION
The selection of a function which approximates the shape of
the response desired is a complicated process. Except in
the simplest cases it requires the use of tables or computer
programs. The form of the transfer function desired is in
terms of the pole and zero locations. The most common
approximations found in tables are Butterworth, Tschebycheff, Elliptic, and Bessel. The decision as to which approximation to use is usually a function of the requirements and
TUK/l0111-35
1-16
l>
."
.....
CI
Applications Information
(Continued)
system objectives. Butterworth filters are the simplest but
have the disadvantage of requiring high order transfer functions to obtain sharp roll-offs.
The Tschebycheff function is a min/max approximation in
the passband. This approximation has the property that it is
equiripple which means that the error oscillates between
maximums and minimums of equal amplitude in the passband. the Tschebycheff approximation, because of its equiripple nature, has a much steeper transition region than the
Butterworth approximation.
The elliptic filter, also known as Cauer or Zolotarev filters,
are equiripple in the passband and stopband and have a
steeper transition region than the Butterworth or the Tschebycheff.
For a specific lowpass filter three quantities can be used to
determine the degree of the transfer function: the maximum
passband ripple, the minimum stopband attenuation, and
the transition ratio (tr = ros/ roc). Decreasing AMAX, increasing AM IN, or decreasing tr will increase the degree of
the transfer function. But for the same requirements the elliptic filter will require the lowest order transfer function. Tables and graphs are available in reference books such as
"Reference Data for Radio Engineers", Howard W. Sams &
Co., Inc., 5th Edition, 1970 and Erich Christian and Egon
Eisenmann, "Filter Design Tables and Graphs", John Wiley
and Sons, 1966.
For specific transfer functions and their pole locations such
text as louis Weinberg, "Network Analysis and Synthesis",
McGraw Hill Book Company, 1962 and Richard W. Daniels,
"Approximation Methods for Electronic Filter Design",
McGraw-Hili Book Company, 1974, are available.
Maximum output noise
Power consumption
Power supply voltage
Dynamic range
Maximum output level
The second step is to find the pole and zero location for the
transfer function which meet the above requirements. This
can be done by using tables and graphs or network synthesis. The form of the transfer function which is easiest to
convert to a cascaded filter is a product of first and second
order terms in these forms:
First Order
K
Second Order
K
Ks
KS2
Ks
(Iowpass)
(highpass)
(bandpass)
S2+ "'Os + "'02
Q
K(s2
+ "'Z2)
(notch)
S2+ "'Os + "'02
Q
DESIGN OF CASCADED MULTISECTION FILTERS
The first step in designing is to define the response required
and define the performance specifications:
1. Type of filter:
lowpass, highpass, bandpass, notch, allpass
2. Attenuation and frequency response
3. Performance
Center frequency/corner frequency plus tolerance and
stability
Insertion loss/gain plus tolerance and stability
Source impedance
load impedance
(allpass)
Each of the second order functions is realizable by tuning
an AF100 stage. By cascading these stages the desired
transfer function is realized.
CASCADING SECOND ORDER STAGES
The primary concern in cascading second order stages is to
minimize the maximum difference in amplitude from input to
output over the frequencies of interest. A computer program
is probably required in very complicated cases but some
. general rules that can be used that will usually give satisfactory results are:
f,_Hz f3 f5
fo_Hz
f6f4 f2_Hz
TL/K/l0111-37
GRAPH M. Generalized Model Response
1-17
CI
Q
.,..
Q
LL.
c(
r--------------------------------------------------------------------------------,
Applications Information (Continued)
1. The highest "0" pole pair should be paired with the zero
pair closest in frequency.
3. In cascaded filters of more than two sections the first
section should be the section with "0" closest to 0.707
and then additional stages should be added in order of
least difference between first stage 0 and their O.
2. If highpass and lowpass stages are cascaded the lowpass sections should be the higher frequency and highpass sections the lower frequency.
RF3
Rn
77.6k
RF2
48.3k
16.3k
2
lOOk
3.93k
lOOk
2
lOOk
AF100
405k
33.0k
54.9k
lOOk
ArlOO
5
13
AFIOO
5
11
13
10.8k
50.8k
Rn
RF2
RF3
48.3k
54.9k
77.6k
TLlK/lOlll-38
Lowpass Elliptic Filter
Fe = 1
Fs = 1.3
AMAX = 0.1 dB
AMIN = 40 dB
N=6
fOl
= 1.0415
01
= 7.88
fZl
= 1.329
fz/fo
= 1.28
(~r = 1.63
f02
= 0.9165
02
= 1.79
fZ2
= 1.664
fz/fo
= 1.82
(~r = 3.30
f03
= 0.649
03
= 0.625
fZ3
= 4.1285
fz/fO
= 6.36
(~r = 40.5
(503.3)
RFI = - - - - - X 105 .
fOl X fe
at 1000 Hz = fe
RFI
= 48.3k
RF2
5
RF2 = -(503.3)
- - - - X 10
f02 X fe
= 54.9k
(503.3)
RF3 = - - - - f03 X fe
RF3 = 77.6k
6th Order Elliptic Filter
0
-6
-12
Iii'
.!!..
~
-18
-24
-30
-36
-42
-48
-54
0.01
III
0.1
10
FREQUENCY (kHz)
TL/K/lOlll-39
FIGURE 21. Lowpass Elliptic Filter Example
1-18
l>
Applications Information
....
."
(Continued)
Y+
500/1000 Hz Switchable
Butterworth Lowpass Filter
lOOk
+6
INPUTo-W'"""1r-'i
OUTPUT
ArIOO
217k
.,.
Fe
Q
~
~
~
1000/500 Hz
~
0.707
25.17k
0
-6
-12
",
-18
-24
-30
-36
"\
'"
-42
-48
-54
100
Gain at de
~
Gain at 1 kH/500 Hz
~
10,000
1000
+13 dB
FREQUENCY (Hz)
10 dB
TL/K/l0111-41
TL/K/l0111-40
FIGURE 22. Switchable Filter Example: 500 Hz/1000 Hz Butterworth Lowpass
Y+
Y+
lOOk
II
lOOk
10
II
10
lOOk
ArlOO
lOOk
AFIOO
242.9k
8.813k
13 12 14
14
-=
150k
150k
150k
150k
150k
Y-
TLIK/10111-42
+6
STAGE 1
Fe
~
3.328 Hz
Q
~
3.84
Fz
~
4.218 Hz
!
~
-6
-12
-18
-24
-30
-36
STAGE 2
/
Fe
~
2.975 Hz
-42
Q
~
0.693
-48
-54
Fz
~
8.865 Hz
I
10
100
1000
FREQUENCY (Hz)
TL/K/l0111-43
FIGURE 23. EEG Delta Filter-3 Hz Lowpass
1-19
CI
CI
o
o
u:::
....
."
~National
UI
o
~ Semiconductor
AF150
Universal Wideband Active Filter
General Description
Features
The AF150 wideband active filter is a general second order
lumped RC network. Only four exfernal resistors are required to program the AF150 for specific second order functions. Low pass, high pass and band pass functions are
available simultaneously at separate outputs. Notch and all
pass functions can be formed by summing the outputs with
an exfernal amplifier. Higher order filters are realized by cascading AF150 active filters with appropriate programming
resistors.
•
•
•
•
•
•
Any of the classical filter configurations, such as Butterworth, Bessel, Cauer and Chebyshev can be formed.
•
•
•
•
Independent Q, frequency, gain adjustments
Low sensitivity to external component variation
Separate low pass, high pass, band pass outputs
Inputs may be differential, inverting or non-inverting
All pass and notch outputs may be formed
Operates to 100 kHz
Q range to 500
±5V to ±IBV
Power supply range
± 1% unadjusted
High accuracy
2 X 105
Q frequency product
Connection Diagram
NO
PIN
NO
PIN
INT 1
BANDPASS
OUTPUT
-v
GND
10
2
INPUT
-Nole: Internally connected. 00 Not use.
INPUT
3
HIGHPASS
OUTPUT
+V
LOWPASS
OUTPUT
INT2
Top View
Ceramic Dual-In-Line Package
Order Number AFI50-1CJ or AFI50-2CJ
See NS Package Number HY13A
1-23
NO
PIN
TL/K/l0112-1
C)
II)
....u..
cc
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
Differential Input Voltage
Infinite
Operating Temperature
±18V
Power Dissipation
(Note 1)
±36V
Output Short·Circuit Duration (Note 1)
-25'Cto +85'C
Storage Temperature
-25'Cto +100'C
Lead Temperature
(Soldering, 10 Seconds)
900 mW/Package (500 mW/Amp)
300'C
Electrical Characteristics
Specifications apply for Vs = ±15V, over -25'C to +85'C unless otherwise specified.
Symbol
Parameter
Conditions
Frequency Range
fe
Min
Typ
x a s: 2 X 105
Max
Hz
500
Hz/Hz
±2.5
±1.0
%
±50
±150
ppml'C
±7.5
%
±300
±750
ppml'C
ORange
foAccuracy
AF150-1J
AF150-2J
bofo/aT
fe
= 25'C
fo Temperature Coefficient
a Accuracy
boa/aT
x a s: 5 X 104, TA
fe X a
s:
5 X 104, TA = 25'C
a Temperature Coefficient
PSRR
Power Supply Rejection Ratio
80
100
CMRR
Common Mode Rejection
80
100
lOS
Input Offset Current
Tj = 25'C
3
50
Is
Input Bias Current
Tj = 25'C
30
200
VCM
Input Common·Mode Voltage Range
Vs = ±15V
Is
Power Supply Current
Vs = ±15V, TA = 25'C
±11
Units
100k
dB
±12
15
pA
V
30
mA
1: Any of the amplifier's outputs can be shorted to ground indefinitely; however, more than one should not be simultaneously shorted es the maximum
package power dissipation will be exceeded.
Note
Applications Information
CIRCUIT DESCRIPTION AND OPERATION
If the output is taken from the output of A2, numerator coef·
ficients a1 and a3 equal zero and the transfer function be·
comes:
A schematic of the AF150 is shown in Figure 1. Amplifier A 1
is a summing amplifier with inputs from integrator A2 to the
non·inverting input and integrator A3 to the inverting input.
T{s) =
By adding external resistors the circuit can be used to gen·
erate the second order transfer function:
aa
s2 + a2 s + a1
T{s) =
s2+b2S + b1
The denominator coefficients determine the complex pole
pair location and the quality of the poles where
Wo =
.Jiii =
T{s) =
{low pass)
Using an external op amp and the proper input and output
connections, the circuit can also be used to generate the
transfer functions for a notch and all pass filter.
If the output is taken from the output of A 1, numerator coef·
ficients a1 and a2 equal zero, and the transfer function be·
comes:
In the transfer function for a notch function a2 becomes
zero, a1 equals w/- and as equals 1. The transfer function
becomes:
aas2
a
a1
s2 + wos + w02
a
a = : : = the quality of the complex pole pair
s2+~+w02
(band pass)
If the output is taken from the output of A3, numerator coef·
ficients as and a2 equal zero and the transfer function be·
comes:
the radian center frequency
T{s) =
a2s
s2 + wos + w02
a
(high pass)
T{s) =
s2 + w/-
s2+~+w02
a
1-24
(notch)
»
...
."
Applications Information
(Continued)
UI
Q
HIGH PASS
3
LOW PASS
BAND PASS
14
13
5
7
20k
2o----1~~~-+------~----~~----~----__t
2k
10k
TL/K/10112-2
FIGURE 1. AF150 Schematic
aa
In the all pass transfer function
= 1, a2 = - wo/O and
a1 = w02. The transfer function becomes:
s2 - wOs
Q
Two resistor tuning for 1 kHz to 100 kHz:
228.8 x 106
R,=
+ w02
T(s) = -----='-----s2 + wOs + w02
fo
n
(1)
(all pass)
o
The relationships between the generalized coefficients and
the external resistors will be found in the appendix. It is not,
however, necessary to use these theoretical, if not
"messy", equations to solve for the proper external resistor
values. In general, it is assumed that the user has knowledge of the frequency and Q of the specific filter he is designing. For higher order filters of various types, the reader
is directed to any of the available texts on filters (see bibliography) for information and tables concerning the location
of the poles and zeros. Once the specifics of the filter are
found from the tables, it is simply a matter of cascading the
sections with proper attention to some general guidelines
which are included later in the application section.
Af150
Rf
TL/K/10112-3
FIGURE 2. Resistive Tuning
looomn_
Graph A. Resistive Tuning
The following discussion gives a step-by-step procedure for
designing filters with several examples given for clarity.
II
FREQUENCY TUNING
Two equal value frequency setting resistors are required for
frequencies above 1 kHz. For lower frequencies, T tuning or
the addition of external capacitors is required. Using external capacitors allows the user to go as low in frequency as
he desires. T tuning and external capacitors can be used
together.
10 _ _
'e-FREQUENCY (Hz)
TLlK/10112-4
T resistive tuning for fa
<
1 kHz:
Rl2
R,- 2Rl
Rs = =-~-=-
Rf from equation 1.
1-25
(2)
C) , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,
Lt)
~
Applications Information (Continued)
a
If the required in the circuit is greater than OMIN, use the
circuit configuration shown in Figure 5 and equation 4 to
resistor. If the
of the circuit is less
calculate Ro, the
than OM IN, use the circuit configuration shown in Figure 6
and equation 5.
a
ArlSO
a
Graph C. QMIN
105 Non-Inverting Input
TLlK/l0112-5
FIGURE 3. T Tuning
Graph B. T Tuning
lOOk
10
102 L.....I...J..J..LJ.llIl.--L..J..J.J.J.J.lIJ..--,""u.u.WI
:§:
0.1
1.0
10
10k
~
~
TL/K/l0112-8
~
For
Ik
a > OMIN in non-inverting mode:
104
RO = --------1-0-,4 n
~
'"
10
10
Ik
(4)
3.480 - 1
looL...1..J.J.;LJ.llIl.-+J..I..CWll.....L.l..L
RIN
10k
FREQUENCY (Hz)
TL/K/IOI12-6
If external capacitors are used for fo
3 should be used.
R
f = fo (C
AFISO
< 1 kHz, then equation
0.05033
x 10- 12) n
+ 220
(3)
TL/K/l0112-9
FIGURE 5.
a Tuning for a > QMIN. Non-Inverting Input
Graph D. RQ for a > aMIN.
Non-Inverting Input
10k
AFISO
III
Ik
TL/K/l0112-7
FIGURE 4. Low Frequency RC Tuning
100".
a DETERMINATION
Setting the a requires one resistor from either pin 1 or pin 2
to ground. The value of the a setting resistor depends on
the input connection and input resistance as well as the
value of the O. The a will be inversely proportional to the
Q
TL/K/l0112-10
resistance from pin 1 to ground and directly proportional to
resistance from pin 2 to ground.
For
<
OMIN in non-inverting mode:
2 x 103
Ro = ----(-:---1-0-:
4:-)---- n
1 +0.3162
ORIN - 1.1
NON-INVERTING CONNECTION·
a
To determine the
resistor, choose a value of input resistor, RIN (Figures 5 and 6) and calculate OMIN (Graph C).
1
a
+ 104
RIN
OMIN=~
*Note: The discussion of "non-inverting" and "inverting" has to do with the
phase relationship between the input port and the low pass output
port. Refer to F/{Jure 1 for other output port phase relationships.
1-26
(5)
Applications Information
»
"11
......
(Continued)
U1
o
DESIGN EXAMPLE
Non-Inverting Band Pass Filter
Amo
Center frequency 38 kHz
= fa, 10 Hz/Hz = Q, 10k = RIN.
2
-L..-_ _ _ _ _- - '
'f
6020
Input
'IN
O~'0~k__~r--~~--~----~l
AF150
TL/K/l0112-11
FIGURE 6. Q Tuning for Q < QMIN,
Non-Inverting Input
13
'Q
OUTPUT
250
Graph E. Ra for Q < QMIN,
Non-Inverting Input
TL/K/l0112-15
lOOk
Using Equation 1
228.8 X 106
Rt =
10k
Rt
=
fa
228.8 X 106
38 X 103
=
n
6020n
Using Equation 6
104
0.1
1.0
RQ =
10
(
3.16Q
TLlK/l0112-12
(
104
2 x 103 )
+ ---
-1
n
(6)
RIN
Notches can be generated by two simple methods: using
RC input (Figure 8) or low pass/high pass summing (Figure
9). The RC input method requires adding a capacitor to pin
14 and a resistor connects to pin 7. The summing method
requires two resistors connected to the low pass and high
pass output.
ArlS0
The difference between the two possible methods of generating a notch is that the capacitor connection requires a
high quality precision capacitor and the gain of the circuit is
difficult to adjust because the gain and zero location are
both dependent on Cz and Rz. The amplifier summing
method requires 3 precision resistors and an external operational amplifier. However, the gain can be adjusted independent of the notch frequency.
TLlK/l0112-13
FIGURE 7. Q Tuning, Inverting Input
Graph F. Q Tuning Inverting
Input
For input RC notch tuning:
Rz =
fZ
10
n
NOTCH FILTERS
--2..
L..-_ _ _ _ _- - '
0.1
1
From equation 33, the center frequency gain is found to be
6.3 VIV (16 dB). If the center frequency gain is to be adjust·
ed, equation 33 can be solved for RQ in terms of RIN and
this substituted into equation 6 to find the required RIN and
RQ.
For any Q in inverting mode:
3.16Q 1.1
2 X 10 3)
+~ -
RQ = 250n
INVERTING CONNECTION'
RQ =
1.1
100
TLlK/l0112-14
"Note: The discussion of "non-inverting" and "inverting" has to do with the
phase relationship between the input port and the low pass output
port. Refer to Rgure 1 for other output port phase relationships.
1·27
X 12 (fo)2
n
10
Cz Rt
220
fz
= frequency of notch (zero location)
(7)
•
C) , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,
\l)
....u..
cc
Applications Information (Continued)
DESIGN EXAMPLE
19 kHz notch using RC input.
14
19 kHz
19 kHz
20
Center frequency
Zero frequency
f!Lo OUTPUT
Af150
fa
fZ
Q
7
~Cz
RZ
INPUT
TL/K110112-16
FIGURE 8. Input RC Notch
AF150
Graph G. Input RC Notch
RQ
10
146
14
13
+-~~~----OOUTP~
I c~~~'
lit
RI
12.04k
Cz
12.04k
220pr
INPUT O---.....--.JVI,,.,...--.J
RZ
12.04k
0.1
TL/K/l0112-20
FIGURE 10. RC Notch, 19 kHz
I
Using equation 1:
0.01
0.1
10
Rf= 228.8
100
TUK/l0112-17
For the low pass/high pass summing technique,
Rh =
(~)2RL
fa
0
Using equation 4 with R'N = 00:
104
(8)
10
X 106
fa
Rf = 12,0400
IO/IZ
RO =
1040
3.48Q-l - R'N
RO = 1460
Using equation 7:
R=
Af150
(Cz
RF X1012 ) (!2)20
220
Z
fz
RZ = 12,0400
DESIGN EXAMPLE
19 kHz notch using low pass/high pass summing
19 kHz
19 kHz
20
Center frequency
Zero frequency
TUK/l0112-1B
FIGURE 9. Output Notch
fa
fz
Q
Using equation 1:
Graph H. Output Notch
10
Rf=
0.,,,.
228.8 X 106
fa
0
Rf = 12,0400
Using equation 4, choose R'N = 10 kO:
104
RO=
1040
3.48Q-l-R'N
RO = 1480
Using equation 8:
0.01 L...JC.LL.illlJl.-L....LJ.illlJl.-L..LJ.lilJ.II
0.1
10
100
Rh =
IZ/IO
(~)2 RL
fa
Choose RL = 20k, then Rh = 2k
TUK/l0112-19
1·28
10
Applications Information
»
"11
.......
(Continued)
U1
TRIALS, TRIBULATIONS AND TRICKS
When adjusting the Q, set the signal source to either fH or fl
and adjust for 45' phase change or a 3 dB gain change.
Certainly, there is no substitute for experience when applying active filters, working with op amps or riding a bicycle.
However, the following section will discuss some of the finer
points in more detail, and hopefully alleviate some of the
fears and problems that might be encountered.
Notch Tuning
If a circuit has a jw axis zero pair the notch can be tuned by
adjusting the ratio of the summing resistors (low pass/high
pass summing) or the input resistance (input RC).
TUNING TIPS
In either case the signal is connected to the input and the
proper resistor is adjusted for a null at the output.
In applications where 2 to 3% accuracy is not sufficient to
provide the required filter response, the AF150 stages can
be tuned by adding trim pots or trim resistors in series or
parallel with one of the frequency determining resistors and
the Q determining resistor.
Special Cases
When using the input RC notch the unit cannot be tuned
through the normal input so an additional 100k resistor can
be added at pin 1 and the unit can be tuned normally. Then
the 100k input resistor should be grounded and the notch
tuned through the normal RC input.
When tuning a filter section, no matter what output configuration is to be used in the circuit, measurements are made
between the input and the band pass (pin 13) output.
An alternative way of tuning is to tune using the Q resistor
as the input. This requires the Q resistor be lifted from
ground and connecting the signal source to the normally
grounded end of the Q resistor. This has the problem that
when the Q resistor is grounded after tuning, its value is
decreased by the output impedance of the source. This
technique has the advantage of not requiring an additional
resistor.
Before any tuning is attempted the low pass (pin 5) output
should be checked to see that the output is not clipping. At
the center frequency of the section the low pass output is
10 dB higher than the band pass output and 20 dB higher
than the high pass. This should be kept in mind because if
clipping occurs the results obtained when tuning will be incorrect.
Frequency Tuning
TUNING PROCEDURE
By adjusting the resistance between pins 7 and 13 the center frequency of a section can be adjusted. If the input is
through pin 1 the phase shift at center frequency will be
180' and if the input is through pin 2 the phase shift at
center frequency will be 0'. Adjusting center frequency by
phase is the most accurate but tuning for maximum gain is
also correct.
Center Frequency Tuning
Set oscillator to center frequency desired for the filter section, adjust amplitude and check that clipping does not occur at the low pass output pin 5.
Adjust the resistance between pins 13 and 7 until the phase
shift between input and band pass output is 180'.
QTuning
QTuning
The Q is tuned by adjusting the resistance between pin 1 or
pin 2 and ground. Low Q tuning resistors will be from pin 2
to ground (Q < 0.6). High Q tuning resistors will be from pin
1 to ground. To tune the Q correctly, the signal source must
have an output impedance very much lower than the input
resistance of the filter since the input resistance affects the
Q. The input must be driven through the same resistance
the circuit will see to obtain precise adjustment.
Set oscillator to upper or lower 45' frequency (see tuning
tips) and tune the Q resistor until the phase shift is 135'
(upper 45' frequency) or 225' (lower 45' frequency).
The lower 3 dB (45') frequency, fl' and the upper 3 dB (45')
frequency, fH' can be calculated by the following equations:
FILTER DESIGN
fH
=
fl =
where fo
C~ + ~(-iar + 1
)
Zero Tuning
Set the oscillator output to the zero frequency and tune the
zero resistor for a null at the output of the summing amplifier.
Since most filter tables are in terms of a normalized low
pass prototype, the filter to be designed is usually reduced
to a low pass prototype. After the low pass transfer function
is found, it is transformed to obtain the transfer function for
the actual filter desired. The low pass amplitude response
which can be defined by four quantities, defined below:
x (fo)
(~C~r + 1 - 2~) x (fo)
= center frequency
v+
Rf
12,040
GAIN
10k
RH
2k
3
v+
RIM
10k
INPUT
S
AF1S0
6
RL
20k
RQ
148
OUTPUT
VV-
Rf
12,040
1-29
TUK/10112-21
o
o
....
Ln
LL
Applications Information
Applications Information
."
.....
(Continued)
en
programs. The form of the transfer function desired is in
terms of the pole and zero locations. The most common
approximations found in tables are Butterworth, Chebychev,
Elliptic and Bessel. The decision as to which approximation
to use is usually a function of the requirements and system
objectives. Butterworth filters are the simplest but have the
disadvantage of requiring high order transfer functions to
obtain sharp roll-offs.
The Chebychev function is a minImax approximation in the
pass band. This approximation has the property that it is
equiripple which means that the error oscillates between
maximums and minimums of equal amplitude in the pass
band. The Chebychev approximation, because of its equirippie nature, has a much steeper transition region than the
Butterworth approximation.
First Order
K
s+
o
Second Order
K
(low pass)
Wr
~
s + Wr
(high pass)
(band pass)
S2+WOS+W02
o
K(s2
+
wZ2)
(notch)
s2+wOs+w02
o
The elliptic filter, also known as Cauer or Zolotarev filters,
are equiripple in the pass band and stop band and have a
steeper transition region than the Butterworth or the Chebychev.
For a specific low pass filter three quantities can be used to
determine the degree of the transfer function: the maximum
pass band ripple, the minimum stop band attenuation, and
the transition ratio (tr = wsl we!. Decreasing AMAX, increasing AMIN, or decreasing tr will increase the degree of the
transfer function. But for the same requirements the elliptic
filter will require the lowest order transfer function. Tables
and graphs are available in reference books such as "Reference Data for Radio Engineers", Howard W. Sams & Co.,
Inc., 5th Edition, 1970 and Erich Christian and Egon Eisenmann, "Filter Design Tables and Graphs"; John Wiley and
Sons, 1966.
o + W0 2
S2 - wos
(all pass)
S2+WOS+W02
o
Each of the second order functions is realizable by using an
AF150 stage. By cascading these stages the desired transfer function is realized.
CASCADING SECOND ORDER STAGES
The primary concern in cascading second order stages is to
minimize the difference in amplitude from input to output
over the frequencies of interest. A computer program is
probably required in very complicated cases but some general rules that can be used that will usually give satisfactory
results are:
1. The highest 0 pole pair should be paired with the zero
pair closest in frequency.
2. If high pass and low pass stages are cascaded, the low
pass sections should be the higher frequency and high
pass sections the lower frequency.
3. In cascaded filters of more than two sections, the first
section should be the section with 0 closest to 0.707 and
then additional stages should be added in order of least
difference between first stage 0 and their O.
For specific transfer functions and their pole locations such
texts as Louis Weinberg, "Network Analysis and Synthesis",
McGraw Hill Book Company, 1962 and Richard W. Daniels,
"Approximation Methods for Electronic Filter Design",
McGraw-Hili Book Company, 1974, are available.
DESIGN OF CASCADED MULTISECTION FILTERS
The first step in designing is to define the response required
and define the performance specifications:
1. Type of filter:
DESIGN EXAMPLES OF CASCADE CONNECTIONS
Low pass, high pass, band pass, notch, all pass
2. Attenuation and frequency response
Example 1:
Consider a 4th order Butterworth low pass filter with a
10 kHz cutoff (-3 dB) frequency and input impedance
~30 kn.
From tables, the normalized filter parameters are:
3. Performance
Center frequency I corner frequency plus tolerance and
stability
Insertion lossl gain plus tolerance and stability
Source impedance
F1
=
1.0
01
=
0.541
F2 = 1.0
02 = 1.306
Thus, relative to the design required
F1 = (1.0)(10 kHz) = 10kHz
Load impedance
Maximum output noise
Power consumption
F2
Power supply voltage
Dynamic range
= (1.0)(10 kHz) = 10 kHz
Section 1
F = 10 kHz,
Maximum output level
The second step is to find the pole and zero location for the
transfer function which meet the above requirements. This
can be done by using tables and graphs or network synthesis. The form of the transfer function which is easiest to
convert to a cascaded filter is a product of first and second
order terms in these forms:
Rt=
228.8
fo
Rt = 22,880n
1-31
0 = 1.306
x 106
n
(Using equation 1)
III
Applications Information (Continued)
Select input resistor 31.6 kO
Complete Filter, Example 1
104
INPUT
1+-
22.BBk
RIN
OMIN=~
13
31.6k
OMIN = 0.378
Thus, 0 > OMIN
Therefore:
AF1S0
SECllON I
104
Ra =
3097
31.6k
14
1040
3.480 - 1 - -R (Using equation 4)
IN
Ra = 30970
First Stage
13
22.88k
Anso
OUTPUT
SECTION 2
RIM
31.6k
ArISO
INPUT
LP
OUT
17.66k
14
RQ
3097
13
-
.22.88k
TL/K/IOI12-27
22.BBk
TUK/IOI12-26
Section 2
Example 2.
Consider the design of a low pass filter with the following
peiformance:
fo = 10k, 0 = 0.541
fc=10kHz
Since fo is the same as for the first section:
fs = 11 kHz
RI = 22.88kO
Select RIN = 31.6 kO
104
Ra=
1040
(Using equation 4)
IN
Ra = 17,6610
3.480 - 1 -
R
AMAX = 1 dB
AMIN = 40 dB
It is found that a 6th order elliptic filter will satisfy the above
requirements. The parameters of the design are:
STAGE
1
2
3
fo (kHz)
5.16
8.83
10.0
Q
0.82
3.72
20.89
fz(kHz)
29.71
13.09
11.15
Applications Information
(Continued)
Stage 1
Stage 2
The second stage design follows exactly the same procedure as the first stage design. The results are:
a) From equation 1, RF is found to be 44.34k
b) From equation 4, RQ is found to be 11.72k assuming RIN
(arbitrary) is 10 k.o..
a) From equation 1, Rf = 25.91 k
To create the transmission zero fz, at 29.71 kHz, use equation8.
R
h
= (~)2 RL
fo
or R
10'
h
b) From equation 4, RQ = 913.6.0., again assuming RIN is
arbitrarily 10k.
13.09)2 RL
c) Rh = ( 8.83
10 or
= (29.71)2 RL
5.16
10
Thus,
Selecting RL = 10k, then Rh = 2.2k, the second stage
design is shown below.
Rh = 3.315 RL
If RL is arbitrarily chosen as 10 k.o., Rh = 33.15k.
Thus, the design of the first stage is:
Stage 3
The third stage design, again, is identical to the first 2
stages and the results are (for RIN = 10k):
First Stage
~""
...
.
..
.......
Rf
RQ
1•
AF150
Rh
11.72k
13
-=-
= 228.8 X
=
.
....'"
= 2288k
.
104
104
3.480 - 1 - RIN
= 141.4.0.
= (~)2 RL = (~)2 RL
fo
10
10
Let RL = 20k, Rh = 2.48k
RL
'.k
106
fo
33.15k
10k
..
Rh = 0.22 RL
10
TO SECOND
STAGE
TL/K/l0112-28
where the feedback resistor, R, around the external op amp
may be used to adjust the gain.
Second Stage
R
(10k)
Rf
25.91k
INPUT FROM
1ST STAGE
R'N
10k
AnsO
913.6
-=
II
TO 3RD
RL
10k
Ro
STAGE
-=
lit
25.9,.
1-33
TLlK/l0112-29
C)
.."
u:CC
r---------------------------------------------------------------------------------,
Applications Information (Continued)
Filter for Example 2
.....34k
INPUT
Rl
(2.6k)
33.15k
25.91k
R2
(11.17k)
2.2k
10k
Ar150
10k
ArI50
10k
10k
11.72k
913.6
44.34k
-=
25.91k
22.88k
R3
(132.2k)
2.4Bk
10k
Arl50
20k
141.4
22.88k
TL/K/l0112-30
Note 1: Select Rl, R2, R3 for desired gain.
Note 2: All amplifiers LF356.
From equation 13, the DC gain of the first section is
Similarly, the DC gain of the second and third sections are:
11
AV1=
AVI =
104
1
AV2 = 0.850
AV3 = 0.151
Therefore, the overall DC gain is 0.495 and can be adjusted
by selecting R1 with respect to 10k, R2 with respect to 10k
or R3 with respect to 20k.
R
R
1 +...lli +...lli
104
RQ
11
104
= 3.86 VIV
+ 104 + 11.72
X
103
1-34
l>
Applications Information
'TI
.....
(Continued)
C1I
Q
For convenience, a standard resistor value table is given below.
Standard Resistance Values are obtained from the Decade Table by multiplying by multiples of 10. As an example, 1.33 can
represent 1.330,1330,1.33 kO, 13.3 kO, 133 kO, 1.33 MO.
Standard 5% and 2% Resistance Values
Ohms
Ohms
Ohms
Ohms
Ohms
Ohms
Ohms
Ohms
Ohms
Ohms
Ohms
10
11
12
13
15
16
18
20
22
24
27
30
33
36
39
43
47
51
56
62
68
75
82
91
100
110
120
130
150
160
180
200
220
240
270
300
330
360
390
430
470
510
560
620
680
750
820
1,200
1,300
1,500
1,600
1,800
2,000
2,200
2,400
2,700
3,000
3,300
3,600
3,900
4,300
4,700
5,100
5,600
6,200
6,800
7,500
8,200
9,100
10,000
11,000
12,000
13,000
15,000
16,000
18,000
20,000
22,000
24,000
27,000
30,000
33,000
36,000
39,000
43,000
47,000
51,000
56,000
62,000
68,000
75,000
82,000
91,000
100,000
110,000
120,000
130,000
150,000
160,000
180,000
200,000
220,000
1.00
1.02
1.05
1.07
1.10
1.13
1.15
1.18
1.21
1.24
1.27
1.30
1.33
1.37
1.40
1.43
910
1,000
1,100
Megohms
0.24
0.27
0.30
0.33
0.36
0.39
0.43
0.47
0.51
0.56
0.62
0.68
0.75
0.82
0.91
1.0
1.1
1.2
1.3
1.5
Decade Table Determining %% and 1% Standard Resistance Values
Appendix
1.47
1.50
1.54
1.58
1.62
1.65
1.69
1.74
2.15
2.21
2.26
2.32
2.37
2.43
2.49
2.55
1.78
1.82
1.87
1.91
1.96
2.00
2.05
2.10
3.16
3.24
3.32
3.40
3.48
3.57
3.65
3.74
2.61
2.67
2.74
2.80
2.87
2.94
3.01
3.09
4.64
4.75
4.87
4.99
5.11
5.23
5.36
5.49
3.83
3.92
4.02
4.12
4.22
4.32
4.42
4.53
6.81
6.98
7.15
7.32
7.50
7.68
7.87
8.06
5.62
5.76
5.90
6.04
6.19
6.34
6.49
6.65
8.25
8.45
8.66
8.87
9.09
9.31
9.53
9.76
(See Footnote)
The specific transfer functions for some of the most useful
circuit configurations using the AF150 are illustrated in Figures 11-17. Also included are the gain equations for each
transfer function in the frequency band of interest, the Q
equation, center frequency equation and the Q determining
resistor equation. QMIN is a function of R'N (see Graph C).
:L 1
=
11
(DC Gain)
(1 + R'N + RIN)
104
RQ
e'N s->o
~1
= (
e'N s ->
R1.1
1
00
104
a. Non-Inverting Input (Figure 10)
Transfer Equations are:
S2[1
+~1+!:!ill]
104
,
..
eh
=
e'N
RQ
(high pass)
1.1
]
1 + R'N + R'N
104 --=:0...::.
RQ
-eb = _ _-=-__,__
(band pass)
e'N
..
-St.ll1
(9)
R
1
1.1
R
= -
RQ
104
4
10 )
+---+--RQ
where
"'0 = ~0.1 "'1 "'2, (see Footnote)
(10)
Q=
]
C+~1+~)~0.1 (:~)
+.J!:!. +.J!:!.
et
104
RQ
= ---=--""C,---"'-=- (low pass)
..
e'N
) (High Freq. Gainl(14)
R'N
(Center
(15)
e'N ., = "0
(1 + !:!ill + !:!ill) Freq. Gain)
104
RQ
1012
1012
"'1 = Rf1 X 220
"'2 = Rf2 X 220
[
t.ll1 t.ll2 [
(1
..:2.1
R
+ .J!:!. + .J!:!.
(13)
104
(11)
(16)
(17)
where
a
= s2 + s [
1~
1
104 ] t.ll1 + 0.1 "'1 t.ll2
1 + ---+ --(12)
Ra
R'N
Note: It should be noted that in the text of this paper, "1 and "'2 have been assumed equal, and hence Rft
facilitates the design. However, for completeness, the equations given are exact.
1-35
=
Rf2. No generality is lost in this assumption and it
II
or----------------------------------------------------------------------,
.... Appendix (Continued)
II)
!;lc
7
14
20k
10k
-=
3
eh
HIGH PASS
5
13
eb
BAND PASS
eL
LOW PASS
TLlK110112-31
'External Components
FIGURE 11. Non-Inverting Input (Q > QM1N)
b) Non-inverting input (Figure 12) transfer equations are:
1.1
3
2 x 10 ]
+ -A--
s2 [
1 + AIN
104
A
1.1
- SCll l
,
Q
[
(22)
(high pass)
+~]
(23)
1 + AIN
4 _::.
eb = _ _-=-_:--_1_0_
elN
A
(band pass)
1.1
CIIl C112 [
(18)
(19)
~I
+~]
'A
1
A
elN .,
+ -lli
104
1
(low pass)
=
"0
=-~
(24)
1 + RIN
104
1012
CIIl = All _ 220'
(20)
104
+--
1012
C112 = - - - - A12- 220
where
11 = 52
+ S CIIl
[
2 x 103 ]
1.1 +-A-1 o~
1 +-AIN
+ 0.1
WI C112
=
(21)
Q
[
1
104]
+--
AIN
2x103
1.1+~
2 X 107
RQ= (
1-36
104 ) (
1 +AIN
01
~
W2
¥~) -1.1
(25)
(26)
.-------------------------------------------------------------------~
Appendix
~
....
."
(Continued)
U'I
<:)
2
7
14
20k
2k
Rn·
10k ':'
3
8h
HIGH PASS
13
8b
BAND PASS
5
8L
LOW PASS
TUK/l0112-32
·Extemal Components
FIGURE 12. Non-Inverting Input (Q < QMIN)
c) Inverting input (Figure 13) transfer function equations are:
SCl.ll
eb =
2 x 103 )
(-l!.RIN
(band pass)
(28)
elN
3
2 x 10 )
-CI.llC1.l2 ( - - eI =
l!. RIN
(low pass)
(29)
elN
10 12
CI.ll = Rf1 • 220'
10 12
CI.l2=--R12. 220
•
where
1.1
l!. = s2
+
2 x 103 ]
+--RIN
S CI.ll [
104
1
+ 0.1
CI.ll CI.l2
(30)
+-RQ
1·37
~
u::
Appendix (Continued)
CC
I
e,
2 X 104
= - R - - (low pass) (DC gain)
elN 9-+0
IN
-
I
eh
elN 9 -+
d) Differential input (Figure 14) transfer function equations
are:
(31)
s2
00
__
-
2 X 103 (high pass)
RIN (high freq. gain)
3
2X10
-- ( 1
RIN
(32)
x 103
+---
~
(band pass)
(center freq. gain)(33)
1
1.1
+104]
RQ
104
+_
~0.1
(1)2
Q
1.1
a
(37)
(38)
1012
(1)2 =
Rf2 X 220
1
where
1'.1
(35)
a=
2 x 103)
(
(36)
2 x 103 )
-s(l)1 ( - - =
RIN2
(band pass)
1012
'(1)1 = Rll X 220'
(34)
(I)
104
~0.1 :~
(high pass)
a
2 x 103 )
(1)1(1)2 ( - R - e, =
IN2
(low pass)
elN
a
RIN
RQ =
10
RIN2
elN
RIN
Q = [
(2 x 3)
=
elN
4
+10-)
RQ
2
1.1
~
+ R;;-
-
s2
+ s(l)l
[
1
1
2 x 103 ]
+ -'-R-IN~04 + 0.1
104
(1)1 (1)2 (39)
+-+-RQ
RINI
(40)
104
104]
1+-+Q = [
1.1
2
RQ
RINI
2 X 103
+---
~0.1
(1)2
(1)1
RIN2
7
14
20k
eb
BAND PASS
eh
HIGH PASS
'External Components
FIGURE 13. Inverting Input, Any Q
1-38
eL
LOW PASS
TLlK/10112-33
(41)
»
"TI
....
Appendix (Continued)
CII
C
14
2
7
20k
Rn·
2k
220pF
RINZ•
elN {
RIN1 •
10k
Ro·
-=-
3
13
eh
HIGH PASS
'External Components
5
eb
BAND PASS
ef
LOW PASS
TL/K/10112-34
FIGURE 14. Differential Input
104
RQ =
~
Q
(
)
1.1
w2
0.1 WI
+2
X 103
RIN2
~
- 1 _
(42)
RINI
(46)
e) Notch filter (Figure 15) transfer function equations are:
(52
+
1.1
wz2) [
1
+ RIN + RIN
] Rg
Rh
en
I
91N s--+
00
1.1
Rg
A) -Ah
(high freq. gain)
(1 + AIN + -ill
104
~I
elN
10 12
WI = Atl X 220'
(47)
AQ
=0
(48)
01 = OIz
10 12
w2 = Rf2 X 220'
14
7
III
20k
Rn·
2k
220pF
220 pF
.>.....--.;;;50
10k
LOW PASS
13
3
HIGH PASS
TL/K/10112-35
FIGURE 15. Notch Filter Using an External Amplifier
1-39
C)
II)
LL.
cc
r-------------------------------------------------------------------------------------,
Appendix (Continued)
12
f) Input notch filter (Rgure 16) transfer function equations
are:
•
!In.1
= -RF2
RZ
(51)
Cz
= 220 X 10-12
(52)
elN ",-0
(49)
I
en
elN '" _
00
ClIO = ~0.1 CII1 C112 (50)
1012
C112 = -----Rf2. 220
3
7
14
20k
2
5
10k
13
TUK110112-36
'Ex1ernal Components
FIGURE 16. Input Notch Filter Using 3 Amplifiers
g) All pass (Rgum 17) transfer function equations are:
eo = _ [S2_
elN
s2
SCll1
[~]
0=
+ CII02]
+ s CII1 [
__1_.1_
] + CII02
2 + RIN
Ra
[
104]
2+-
~ ~0.1C112
1.1
1012
CII1 = Rf1 • 220'
(53)
(54)
CII1
1012
"'2 = -----Rf2· 220
ClIO = ~0.1 CII1 C112
Time delay at "'0 is 20 seconds
ClIO
3
13
14
7
20k
2k
5
2R*
10k
2R·
i>....-080
RQO
TL/KI10t t2-37
'External Components
FIGURE 17. All Pass
1-40
:J>
Definition of Terms
Bibliography
AMAX Maximum pass band peak-to-peak ripple
R.W. Daniels: "ApproJdmation Methods for Electronic Filter
McGraw-Hili Book Co., New York, 1974
G.S. Moschytz: "Linear Integrated Networks Design", Van
Norstrand Reinhold Co., New York, 1975
E. Christian and E. Eisenmann, "Filter Design Tables and
Graphs", John Wiley & Sons, New York, 1966
AMIN
Minimum stop band loss
Frequency of jw axis pole pair
A.I. Zverev, "Handbook of Filter Synthesis", John Wiley &
Sons, New York, 1967
Stop band edge
Pole frequency determining resistance
fL
Q
Design'~
Frequency of complex pole pair
Quality of pole
Pass band edge
Rz
Ra
fH
'TI
....
en
Zero Frequency determining resistance
Pole quality determining resistance
Frequency above center frequency at which the gain
decreases by 3 dB for a band pass filter
Frequency below center frequency at which the gain
decreases by 3 dB for a band pass filter
•
1-41
.,...
.,...
It)
u..
c(
J?)I National
~ Semiconductor
AF151 Dual Universal Active Filter
General Description
Features
The AF151 consists of 2 general purpose state variable active filters in a single package. By uSing only 4 external resistors for each section, various second order functions may
be formed. Low pass, high pass and band pass functions
are available simultaneously at separate outputs. In addition, there are 2 uncommitted operational amplifiers which
are available for buffering or for forming all pass and notch
functions. Any of the classical filter configurations, such as
Butterworth, Bessel, Cauer and Chebyshev can be easily
formed.
•
•
•
•
•
•
•
•
Independent Q, frequency and gain adjustment
Very low sensitivity to external component variation
Separate low pass, high pass and band pass outputs
Operation to 10kHz
Q range to 500
Wide power supply range-±5V to ±18V
Accuracy- ± 1%
Fourth order functions in one package
Circuit Diagrams
lOOk
10k
1000 pF
1000 pF
6~5
7~
8
24
12
20
~
-= III
y+ v+ y-
TLlK/10113-1
lOOk
18:b:r
15
19
17
+
TL/K/10113-2
Order Number AF151·1CJ or AF151·2CJ
See NS Package Number HY24A
1-42
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
±18V
Supply Voltage
Power Dissipation
Differential Input Voltage
Output Short-Circuit Duration (Note 1)
Infinite
Operating Temperature
+ 85°C
+ 100°C
- 25°C to
Storage Temperature
Lead Temperature (Soldering, 10 sec.)
-25°C to
300°C
900 mW /Package
±36V
Electrical Characteristics (Complete Active Filter)
Specifications apply for Vs = ± 15V and over - 25°C to + 85°C unless otherwise specified.
(Specifications apply for each section.)
Parameter
Conditions
Min
Typ
Max
Units
Frequency Range
fe x 0 ,;; 50,000
10k
Hz
ORange
fe x 0 ,;; 50,000
500
Hz/Hz
foAccuracy
AF151-1C
AF151-2C
fe x 0 ,;; 10,000, TA
fe x 0,;; 10,000, TA
=
=
25°C
25°C
±2.5
±1.0
%
±150
ppml"C
o Accuracy
o Temperature Coefficient
fe x 0 ,;; 10,000, TA
=
25°C
Power Supply Current
Vs
fo Temperature Coefficient
±50
±7.5
%
±300
±750
ppm/oC
2.5
4.5
mA
Typ
Max
Units
1.0
6.0
mV
4
50
nA
Input Bias Current
30
200
Input Resistance
2.5
Mn
V/mV
=
±15V
Electrical Characteristics (Internal Op Amp) (Note 2)
Parameter
Conditions
Input Offset Voltage
Min
RS';;10kn
Input Offset Current
Large Signal Voltage Gain
RL
RL
=
=
=
25
160
10kn
±12
±14
2 kn
±10
±13
RL;;' 2k, VOUT
Output Voltage Swing
±10V
Input Voltage Range
±12
nA
V
V
Common-Mode Rejection Ratio
Rs';; 10kn
70
90
dB
Supply Voltage Rejection Ratio
Rs';; 10kn
77
96
dB
Output Short-Circuit Current
25
mA
Slew Rate (Unity Gain)
0.6
V//kS
Small Signal Bandwidth
Phase Margin
1
MHz
60
Degrees
Note 1: Any of the amplifiers can be shorted to ground indefinitely; however, more than one should not be simultaneously shorted as the maximum junction
temperature will be exceeded.
Note 2: Specifications apply lor Vs
~
±15V, TA
~
:r:.....
U1
.....
."
Absolute Maximum Ratings
25'C.
1-43
~
an
~
u.
c(
r-----------------------------------------------------------------------------------------,
Applications Information
The AF151 consists of 2 identical filter sections and 2 uncommitted op amps. The op amps may be used for buffering
inputs and outputs, summing amplifiers (for notch filter generation), adjusting gain through the filter sections, additional
passive networks to create higher order filters, or simply
used elsewhere in the user's system.
If the output is taken from the output of A 1, numerator coefficients al and a2 equal zero, and the transfer function becomes:
saS2
T(s) = - - - - - " - -
The design equations given apply to both sections; however, for clarity, only the pin designations for Section 1 will be
shown in the examples and discussion.
If the output is taken from the output of A2, numerator coefficients al and sa equal zero and the transfer function becomes:
See the AF100 datasheet for additional information on this
type of filter.
T(s) = _ _--'a2=-s_ _
The design equations assume that the user has knowledge
of the frequency and Q values for the particular design to be
synthesized. If this is not the case, various references and
texts are available to help the user in determining these
parameters. A bibliography of recommended texts can also
be found in the AF100 datasheet.
If the output is taken from the output of A3, numerator coefficients a3 and a2 equal zero and the transfer function becomes:
T(s) = _ _ _a....
l __
Q
Using proper input and output connections the circuit can
also be used to generate the transfer functions for a notch
and all pass filter.
By adding external resistors the circuit can be used to generate the second order system.
In the transfer function for a notch function a2 becomes
zero, al equals CIIz2 and a3 equals 1. The transfer function
becomes:
saS2 + a2s + al
T(s) = -'::----':.--..!.
s2 + b2S + bl
The denominator coefficients determine the complex pole
pair location and the quality of the poles .where
.Jb1 =
(Notch)
the radian center frequency
In the all pass transfer function al = CII02, a2 = -CIIo/Q
and sa = 1. The transfer function becomes:
Q = :0 = the quality of the complex pole pair
2
(Low Pass)
s2 + CIIoS + CII02
A schematic of one section of the AF151 is shown in Figure
1. Amplifier A 1 is a summing amplifier with inputs from integrator A2 to the non-inverting input and integrator A3 to the
inverting input. Amplifier A4 is an uncommitted amplifier.
=
(Band Pass)
s2+Cllos+Cll02
Q
CIRCUIT DESCRIPTION AND OPERATION
ClIO
(High Pass)
s2 + ~ + CII02
,
s2-CIIos+Cll02
Q
T(s)=----s2+Cllos+Cll02
(All Pass)
Q
HIGH PASS
BANDPASS
LOW PASS AMP IN-
--------
3
lOOk,
IN 2o-+-1~..J\IVv--f--f----+--+-----t
10k
lOOk ':"
21
IN lO-~~---'lM------'
~-------------------------------------
7
-------
AMPIN+
TUK/l0113-3
FIGURE 1_ AF151 SchematiC (Section 1)
1-44
r-------------------------------------------------------------------~~
....CI'I
....
."
Applications Information (Continued)
To determine which connection is required for a particular
a, arbitrarily select a value of RIN (Figure 4) and calculate
aMIN according to Equation 3.
105
1 +RIN
aMIN =
(3)
FREQUENCY CALCULATIONS
For operation above 200 Hz, the frequency of each section
of the AF151 is set by 2 equal valued resistors. These resistors couple the output of the first op amp (pin 2) to the input
of the second op amp (pin 1) and the output of the second
op amp (pin 23) to the input of the third op amp (pin 22).
"""""3.4iI
The value for Rf is given by:
50.33 X 106
(1)
Rf=
n
fo
For operation below 200 Hz, "T" tuning should be used as
shown in Figure 3.
For this configuration,
If the a required for the circuit is greater than OMIN, use
Equation 4 to calculate the value of RO and the connection
shown in Figure 4.
105
Ro =
105
(4)
3.4Ba-l-RIN
If the a required for the circuit is less than aMIN, use Equation 5 to calculate the value of Ro and the connection
shown in Figure 5.
R-r2
Rs=--(2)
Rf - 2RT
where RT or Rs can be chosen arbitrarily, once Rf is found
from Equation 1.
104
~=
~
0.3162 (1 + 105 ) - 1.1
a
RIN
Both connections shown in Figures 4 and 5 are "non-inverting" relative to the phase relationship between the input
signal and the low pass output.
For any a, Equation 6 may be used with the "inverting"
connection shown in Figure 6.
105
(6)
RO =
(
104)
3.160 1.1 + RIN - 1
Q CALCULATIONS
a
To set the
of each section of the AF151, one resistor is
required. The value of the a setting resistor depends on the
input connection (inverting or non-inverting) and the input
resistance. Because the input resistance does affect the a,
it is often desirable to use one of the uncommitted op amps
to provide a buffer between the signal source impedance
and the input resistor used to set the a.
AF151
AF151
ILl22_ _-w.__...J123
II
TUK/l0113-4
FIGURE 2. Frequency Tuning
TL/K/l0113-5
FIGURE 3. "T" Tuning for Low Frequency
RIN
0-..1\1\,....._;;.21'"1+
AF151
AF151
TL/K/l0113-7
-"-
FIGURE 5. Connection for Q
TLlK/l0113-6
FIGURE 4. Connection for Q
> QMIN
3
AF151
RQ
21
+
TL/K/l0113-8
FIGURE 6. Connection for Any Q, Inverting
1-45
< QMIN
~ r-----------------------------------------------------------------------------------------~
an
~
II.
f z• the gain to the output of the
(~p)
Again. it is advantageous to use one of the uncommitted op
amps to perform this summing function to prevent loading of
this stage or the resistors RLP and RHP from effecting the Q
of subsequent stages. Resistor R can be used to set the
gain of the filter section.
At the notch, ideally the gain is zero (0).
GAIN CALCULATIONS
TUNING TIPS
The following list of equations will be helpful in calculating
the relationship between the external components and various important parameters. The following definitions are
used:
In applications where 2% to 3% accuracy is not sufficient to
provide the required filter response. the AF151 stages can
be tuned by adding trim pots or trim resistors in series or
parallel with one of the frequency determining reSistors and
the Q determining resistor.
AL -
Gain from input to low pass output at DC
AH -
Gain from input to high pass output at high frequency
As -
Gain from input to band pass output at center frequency
AH = (1
105
Before any tuning is attempted; the low pass output should
be checked to see that the output is not clipping. At the
center frequency of the section. the low pass output is
10 dB higher than the band pass output and 20 dB higher
than the high pass. This should be kept in mind because if
Clipping occurs. the results obtained when tuning will be incorrect.
11
AL=~
AH=~
a
5
105
10 )
- ( 1 +-+As =
Ra
+ RIN
a
+ RIN
105
Ra
Frequency Tuning
RIN
By adjusting resistor RI. center frequency of a section can
be adjusted. Adjusting center frequency by phase is the
most accurate but tuning for maximum gain is also correct.
QTuning
For Figure 5:
11
The Q is tuned by adjusting the Ra resistor. To tune the Q
correctly, the signal source must have an output impedance
very much lower than the input resistance of the filter since
the input resistance affects the Q. The input must be driven
through the same resistance the circuit will "see" to obtain
precise adjustment.
105
+-
Ra
AL=--a-
1.1
AH=
104
+-
a
-(1
AB =
a = 1
Ra
+ 105 )
a
+
Ra
When tuning a filter section. no matter what output configuration is to be used in the circuit, measurements are made
between the input and the band pass output.
For Figure 4:
a = 1
+ RIN + RIN)
RIN
RIN
105
1-46
»
Applications Information
."
(Continued)
The lower 3 dB (45°) frequency, fl' and the upper 3 dB (45°)
frequency, fH' can be calculated by the following equations:
fH =
C
1
0 +
~c~r + 1 )
x
(fa)
(c) From Equation 4, RQ is found to be
105
105
105
RQ =
105
3.48a - 1 - R'N
(3.48)(40) - 1 - 3 X 105
where fa = center frequency
fL
=
.....
.....
U1
Since the a required for the design (a = 40), is greater
than aMIN, the circuit of Figure 4 or Figure 6 may be used.
Arbitrarily we shall select the circuit of Figure 4.
(~C~r + 1- 2~) X(fa)
When adjusting the a, set the signal source to either fH or fL
and adjust for 45°C phase change or a 3 dB gain change.
or
Notch Tuning
RQ
=
7250
I
(d) Calculate the center frequency gain for Figure 4.
105
105 )
- ( 1 +-+As =
RQ
R'N = _--.:(,-1_+_1_3_7_.9_+_0._3_33..:-)
If a circuit has a jw axis zero pair, the notch can be tuned by
adjusting the ratio of the summing resistors (low pass/high
pass summing).
( 1 + R'N + RIN)
RQ
105
In either case, the signal is connected to the input and the
proper resistor is adjusted for a null at the output.
(1 + 3.0 + 414)
As = 0.333 VIV
Since the gain at fa is 0.333 VIV, a gain of 10 VIV can be
obtained by using the uncommitted operational amplifier
with a gain of 30.03 as shown in Figure 8.
TUNING PROCEDURE
Center Frequency Tuning
Set oscillator to center frequency desired for the filter section, adjust amplitude and check that clipping does not occur at the low pass output.
+v
Adjust the Rt resistor until the phase shift between input and
band pass output is 180° or 0°, depending upon the connection.
r-&'::"'_...I.:=~::....J=_-L:.jll
OUTPUT
17
10k
10k
298k
QTuning
Set oscillator to upper or lower 45° frequency (see tuning
tips) and tune the a resistor until the phase shift is 135°
(upper 45° frequency) or 225° (lower 45° frequency).
Zero Tuning (Notch Tuning)
INPUT
INPUT
Set the oscillator output to the zero frequency and tune one
of the summing resistors for a null at the output of the summing amplifier.
300k
300k
579.Q
Gain Adjust
TL/K/l0113-10
Set the oscillator to any desired frequency and the gain can
be adjusted by measuring the output of the summing amplifier and adjusting the feedback resistance.
FIGURE 8. Dual Band Pass Filter
DESIGN EXAMPLE
Assume 2 band pass filters are required to separate FSK
data.
f1 = 800 Hz, a = 40
f2
=
1000 Hz, a
=
III
OUTPUT
20k
50
The gain through each filter is to be 10 VIV (20 dB).
Since the design is similar for both sections, only the first
section design will be shown for the example.
(a) From Equation 1
Rt
=
50.33 x 10 6
fa
50.33 X 106
800
TL/K/l0113-11
Rt
=
FIGURE 9. Telephone Multifrequency (MF)
Band Pass Filter
62.9k
(b) Checking aMIN from Equation 3, arbitrarily let
R'N
300k.
105
105
1+- 1+--R'N
3 X 105
3.48
= 0.383
aM IN = ~ =
=
1-47
,.. r---------------------------------------------------------------------------------,
II)
,..
~
Applications Information (Continued)
FREQ
BW
fe
f1
Q1" Q2
f2
RF1
RF2
RQ
700
900
1100
1300
1500
1700
75
75
75
75
75
75
698.4
898.7
1098.8
1298.9
1499.0
1699.1
665.6
865.8
1065.7
1265.8
1465.8
1665.9
17
21.8
26.7
31.6
36.4
41.3
732.8
932.9
1132.9
1332.9
1532.9
1733.0
75.62k
58.13k
47.23k
39.76k
34.34k
30.21k
68.68k
53.95k
44.43k
37.76k
32.83k
29.04k
1.749k
1.354k
1.100k
926.20
802.10
705.60
700Hz
900Hz
1100Hz
1300 Hz
1500 Hz
1700Hz
I
I
I
I
I
I
AF110
AFll0
Afll0
I
I
I
I
I
I
AF151
700Hz
A=6dB
AFl51
900Hz
A=6dB
AF151
1100Hz
A=6dB
AF151
1300Hz
A=6dB
AF151
1500Hz
A=6dB
AFlSl
1700Hz
A=6dB
I
1
1
o-jf-
I
1
1
I
AFl04
AGe
TUK/10113-12
FIGURE 10. MF Tone Receiver
1-48
.---------------------------------------------------------------~~
Applications Information
U'I
40.11k
57.43k
22
12
INPUT 301k
....."
....
(Continued)
21
An51
21.02k
17
4
31.6k
Cutoff 1270 Hz
Stop Band Edge 2025 Hz
Band Pass Ripple 1.5 dB
Rejection 59 dB
lei 876.3 Hz
le2 1254.8 Hz
01 1.75
02 8.21
IZI 3201.7 Hz
1z2 2113.3 Hz
IA 356.9 Hz
57.43k
OUTPUT
42.22k
TUK/l0113-13
FIGURE 11. Low Pass Low Speed Asynchronous FSK Modem Filter
17.15k
24.56k
10
22
17
0.01 J.&F
301 k
21
o-Jl-+-''INv-~
104k
AF151
18
2209.0.
4 6
Cutoff 2025 Hz
Stop Band Edge 1270 Hz
Band Pass Ripple 1.5 dB
Rejection 59 dB
lei 2049.6 Hz
1c2 2934.8 Hz
01 8.21
02 1.75
Izi 1216.9 Hz
IZ2 803.3 Hz
IA 7206Hz
5
301k
10.61k
9 13
17.15k
lOOk
14
16
301k
lOOk
2255.0.
24.45k
TUK/l0113-14
FIGURE 12. High Pass Low Speed Asynchronous FSK Modem Filter
1-49
.,...
.,...
It)
u..
c(
Applications Information
(Continued)
Standard Resistance Values are obtained from the Decade Table by multiplying by multiples of 10. As an example, 1.33 can
represent 1.330, 1330, 1.33 kO, 13.3 kO, 133 kO, 1.33 MO.
Standard 50/0 and 20/0 Resistance Values
0
0
0
0
0
0
0
0
0
0
0
10
11
12
13
15
16
18
20
22
24
27
30
33
36
39
43
47
51
56
62
68
75
82
91
100
110
120
130
150
160
180
200
220
240
270
300
330
360
390
430
470
510
560
620
680
750
820
910
1,000
1,100
1,200
1,300
1,500
1,600
1,800
2,000
2,200
2,400
2,700
3,000
3,300
3,600
3,900
4,300
4,700
5,100
5,600
6,200
6,800
7,500
8,200
9,100
10,000
11,000
12,000
13,000
15,000
16,000
18,000
20,000
22,000
24,000
27,000
30,000
33,000
36,000
39,000
43,000
47,000
51,000
56,000
62,000
68,000
75,000
82,000
91,000
100,000
110,000
120,000
130,000
150,000
160,000
180,000
200,000
220,000
MO
0.24
0.27
0.30
0.33
0.36
0.39
0.43
0.47
0.51
0.56
0.62
0.68
0.75
0.82
0.91
1.0
1.1
1.2
1.3
1.5
Decade Table Determining Yo % and 1 % Standard Resistance Values
0
0
0
0
0
0
0
0
0
0
0
MO
1.00
1.02
1.05
1.07
1.10
1.13
1.15
1.18
1.21
1.24
1.27
1.30
1.33
1.37
1.40
1.43
1.47
1.50
1.54
1.58
1.62
1.65
1.69
1.74
1.78
1.82
1.87
1.91
1.96
2.00
2.05
2.10
2.15
2.21
2.26
2.32
2.37
2.43
2.49
2.55
2.61
2.67
2.74
2.80
2.87
2.94
3.01
3.09
3.16
3.24
3.32
3.40
3.48
3.57
3.65
3.74
3.83
3.92
4.02
4.12
4.22
4.32
4.42
4.53
4.64
4.75
4.87.
4.99
5.11
5.23
5.36
5.49
5.62
5.76
5.90
6.04
6.19
6.34
6.49
6.65
6.81
6.98
7.15
7.32
7.50
7.68
7.87
8.06
8.25
8.45
8.66
8.87
9.09
9.31
9.53
9.76
1-50
~National
~ Semiconductor
LMF90
4th-Order Elliptic Notch Filter
III
General Description
The LMF90 is a fourth-order elliptic notch (band-reject) filter
based on switched-capacitor techniques. No external components are needed to define the response function. The
depth of the notch is set using a two-level logic input, and
the width is programmed using a three-level logic input. Two
different notch depths and three different ratios of notch
width to center frequency may be programmed by connecting these pins to Y+, ground, or Y-. Another three-level
logic pin sets the ratio of clock frequency to notch frequency.
An internal crystal oscillator is provided. Used in conjunction
with a low-cost color TY crystal and the internal clock frequency divider, a notch filter can be built with center frequency at 50 Hz, 60 Hz, 100 Hz, 120 Hz, 150 Hz, or 180 Hz
for rejection of power line interference. Several LMF90s can
be operated from a single crystal. An additional input is provided for an externally-generated clock signal.
II
II
No external components needed to set response characteristics
Notch width, attenuation, and clock-to-center-frequency
ratio independently programmable
14 pin 0.3" wide package
Key Specifications
.. fa Range
0.1 Hz to 30 kHz
.. fa accuracy over full temperature range (max)
1.5%
II Supply voltage range
± 2Y to ± 7.5V or 4V to 15V
II Passband Ripple (typ)
0.25 dB
II Attenuation at fa (typ)
39 dB or 48 dB (selectable)
[I fCLK: fa
100:1,50:1, or 33.3:1
III Notch Bandwidth (typ)
0.127 fa, 0.26 fa, or 0.55 fa
Cl Output offset voltage (max)
120 mY
Applications
Automatic test equipment
Communications
ID Power line interference rejection
III
Features
II
III
Center frequency set by external clock or on-board
clock oscillator
Typical Connection
Connection
Diagram
60 Hz Notch Filter
+5V
VIN
.Dual-In-Line Package
W
1
14
y+
R
2
13
GND
12
11
VIN1
VIN2
0
lD
lMF90
xrAl2
LMF90
xrAll
5
10
elK
6
9
Your
XL5
7
8
v-
TlfHfl0354-2
Top View
elK
Order Number LMF90CCN,
LMF90CCWM, LMF90CIJ
orLMF90CMJ
See NS Package Number
J14A, M14B or N14A
XL5
+5V
TLfHfl0354-1
1-51
LMF90
Absolute Maximum Ratings
(Notes 1 & 3)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Yoltage (Ys = y+ - Y-)
-0.3Yto +16Y
Y- -0.3YtoY+ +0.3Y
Yoltage at any Input or Output
5mA
Input Current at any Pin (Note 10)
20mA
Package Input Current (Note 10)
500mW
Power Dissipation (Note 5)
ESD Susceptability (Note 6)
Pin9
All Other Pins
1800Y
2000Y
Soldering Information (Note 4)
N Package (Soldering, 10 sec.)
J Package (Soldering, 10 sec.)
260'C
300'C
Storage Temperature Range
- 65'C to + 150'C
Junction Temperature
150'C
Operating Ratings (Notes 2 & 3)
Temperature Range
LMF90CCN, LMF90CCWM
LMF90CIJ
LMF90CMJ
TMIN <:; TA <:; TMAX
O'C <:; TA <:; +70'C
-40'C <:; TA <:; +85'C
-55'C <:; TA <:; + 125'C
4.0Y to 15.0Y
Supply Yoltage Range
AC Electrical Characteristics
The following specifications apply for y+ = + 5Y and Y- = -5Y unless otherwise specified. Boldface limits apply for
TA = TMIN to TMAXi all other limits TA = TJ = 25'C.
LMF90CCN,
LMF90CCWM
Symbol
'"
Conditions
Parameter
Typ
(Note 7)
LMF90CIJ,
LMF90CMJ
Tested
Limit
(Note 8)
Design
Limit
(Note 9)
30
30
1.5
4.0
I\)
fa
fClK
fClK/f01
Pin 6
Pin 6
Pins4 and 5
Clock Frequency
Range
Clock-to-CenterFrequency Ratio
fClK/f02
fClK/f03
Hz (Min)
kHz (Max)
1.5
4.0
1.5
4.0
Hz (Min)
MHz (Max)
MHz (Max)
33.5 ±1%
33.5 ±1.5%
33.5 ±1.5%
(Max)
50.25 ±1%
50.25 ±1.5%
50.25 ± 1.5%
(Max)
100.5 ±1%
100.5 ±1_5%
100.5 ±1.5%
(Max)
Passband Gain
0
±0.2
±0.2
0
±0.2
dB (Max)
0
±0.2
±0.2
0
±0.2
dB (Max)
0
±0.2
±0.2
0
±0.2
= 167 kHz
D = R = GND,
= 250 kHz
y+, D = GND, R = Y-,
DC and 20 kHz, W = D = Y-, R = Y+,
fClK = 167 kHz
W = D = R = GND,
fClK = 250 kHz
W = y+ , D = GND, R = Y-,
fClK = 500 kHz
.-
--
10
10
fClK = 500 kHz
HaN
Units
(Limit)
Design
Limit
(Note 9)
30
W=D=Y-,R=Y+,
fClK
W=
fClK
W =
Tested
Limit
(Note 8)
0.1
0.1
Center Frequency
Range
Typ
(Note 7)
dB (Max)
~--
'---
AC Electrical Characteristics The following specifications apply for V+ =
TA = TMIN to TMAX; all other limits TA = TJ = 25°C. (Continued)
+ 5V and V-
= -5V unless otherwise specified. Boldface limits apply for
LMF90CCN,
LMF90CCWM
Symbol
...
Conditions
Ratio of Passband W =
Width to Center
fCLK
Frequency
W=
fCLK
W=
fCLK
0 = V-, R = V+,
= 167 kHz
0 = R = GND,
= 250 kHz
V+, 0 = GND, R = V-,
= 500 kHz
W=
AMinl@fOI Gain at
Center Frequency fCLK
W=
AMin2@f02
fCLK
W=
AMin3@f03
fCLK
0 = V-, R = V+,
= 167 kHz
0 = R = GND,
= 250 kHz
V+, 0 = GND, R = V-,
= 500 kHz
PBW
~
Parameter
Additional Center
Frequency Gain
TestsatfOI
Typ
(Note 7)
Tested
Limit
(Note 8)
LMF90CIJ,
LMF90CMJ
Design
Limit
(Note 9)
Typ
(Note 7)
0.1275 ±0.0175 0.1275 ±0.0175
W = GND, 0 = V-, R = V+,
fCLK = 167 kHz
W=V+,D=V-,R=V+,
fCLK = 167 kHz
W = V-, 0 = GND, R = V+,
fCLK = 167 kHz
W = 0 = GND, R = v+,
fCLK = 167 kHz
W = V+,D = GND,R = V+,
fCLK = 167 kHz
Tested
Limit
(Note 8)
Design
Limit
(Note 9)
Units
(Limit)
0.1275 ±0.O175
(Max)
0.265 ±0.025
0.265 ± 0.025
0.265 ± 0.025
(Max)
0.550 ±0.05
0.550 ±0.05
0.550 ±0.05
(Max)
-39
-30
-30
-39
-30
dB (Max)
-48
-36.5
-36.5
-48
-36.5
dB (Max)
-48
-36.5
-36.5
-48
-36.5
dB (Max)
-36
-30
-30
-36
-30
dB (Max)
-36
-30
-30
-36
-30
dB (Max)
-42
-30
-30
-42
-30
dB (Max)
-48
-35
-35
-48
-35
dB (Max)
-48
-35
-35
-48
-35
dB (Max)
--
--
06:1W1
II
LMF90
AC Electrical Characteristics The following specifications apply for V+ =
TA = TMIN to TMAX; all other limits TA = TJ = 25'C. (Continued)
+ 5V and V-
= -5V unless otherwise specified. Boldface limits apply for
LMF90CCN,
LMF90CCWM
Symbol
Additional Center
Frequency Gain
Testsatf02
Additional Center
Frequency Gain
Testsatf03
0,
Conditions
Parameter
.j>.
W=
fCLK
W=
fCLK
W=
fCLK
W=
fCLK
W=
fCLK
V-, D = V-, R = GND,
= 250 kHz
GND, D = V-, R = GND,
= 250 kHz
V+, D = V-, R = GND,
= 250 kHz
V-, D = R = GND,
= 250 kHz
V+, D = R = GND,
= 250 kHz
W=D=R=V-,
fCLK = 500 kHz
W = GND, D = V-, R = V-,
fCLK = 500 kHz
W = V+, D = V-, R = V-,
fCLK = 500 kHz
W = V-, D = GND, R = V-,
fCLK = 500 kHz
W = D = GND, R = V-,
fCLK = 500 kHz
LMF90CIJ,
LMF90CMJ
Design
Limit
(Note 9)
Units
(Limit)
Typ
(Note 7)
Tested
Limit
(Note 8)
Design
Limit
(Note 9)
Typ
(Note 7)
Tested
Limit
(Note 8)
-36
-30
-30
-36
-30
dB (Max)
-36
-30
-30
-36
-30
dB (Max)
-36
-30
-30
-36
-30
dB (Max)
-42
-30
-30
-42
-30
dB (Max)
-48
-35
-35
-48
-35
dB (Max)
-36
-30
-30
-36
-30
dB (Max)
-36
-30
-30
-36
-30
dB (Max)
-36
-30
-30
-36
-30
dB (Max)
-42
-30
-30
-42
-30
dB (Max)
-48
-35
-35
-48
-35
dB (Max)
Gain at fs = 0.995 fOl
Gain at f4 = 1.005 fOl
W = D = V-, R = V+ ,
fCLK = 167 kHz
-41
-41
-30
-30
-30
-30
-41
-41
-30
-30
dB (Max)
dB (Max)
Gain atfs = 0.992 f02
Gain atf4 = 1.008 f02
W = D = R. = GND, fCLK = 250 kHz
-40
-40
-35
-35
-35
-35
-40
-40
-35
-35
dB (Max)
dB (Max)
~
Gain at fs = 0.982 foa
Gainatf4 = 1.018 fos
W = V+, D = GND, R = VfCLK = 500 kHz
-41
-41
-35
-35
-35
-35
-41
-41
-35
-35
dB (Max)
dB (Max)
Amaxl
Passband Ripple
W = D = V-, R = V+ ,
fCLK = 167 kHz
f5 = 0.914 fOl
0.25
0.25
0.9
0
0.9
0
0.25
0.25
0.9
0
dB (Max)
dB (Min)
fa = 1.094 fOl
0.25
0.25
0.9
0
0.9
0
0.25
0.25
0.9
0
dB (Max)
dB (Min)
A3a
%
Asb
~b
ASc
----
AC Electrical Characteristics The following specifications apply for V+
TA
=
= + 5V and V- = -5V unless otherwise specified. Boldface limits apply for
TMIN to TMAX; all other limits TA = TJ = 25°C. (Continued)
LMF90CCN,
LMF90CCWM
Symbol
AMax2
AMax3
En
Parameter
Passband Ripple
Passband Ripple
Output Noise
&.
01
Conditions
W = D = R = GND,
fClK = 250 kHz
W = V+, D = GND, R = VfClK = 500 kHz
Design
Limit
(Note 9)
Units
(Limit)
Typ
(Note 7)
Tested
Limit
(Note 8)
Design
Limit
(Note 9)
Typ
(Note 7)
Tested
Limit
(Note 8)
f5 = 0.830 f02
0.25
0.25
0.9
0
0.9
0
0.26
0.25
0.9
0
dB (Max)
dB (Min)
f6 = 1.205 f02
0.25
0.25
0.9
0
0.9
0
0.25
0.25
0.9
0
dB (Max)
dB (Min)
f5 = 0.700103
0.25
0.25
0.9
0
0.9
0
0.25
0.25
0.9
0
dB (Max)
dB (Min)
16 = 1.428 f03
0.25
0.25
0.9
0
0.9
0
0.25
0.25
0.9
0
dB (Max)
dB (Min)
20 kHz Bandwidth
W = D = V-,R = V+,fClK = 167kHz
W = D = R = GND, fClK = 250 kHz
W = V+, D = GND, R = V-,
fClK = 500 kHz
Clock Feedthrough
LMF90CIJ,
LMF90CMJ
670
370
670
370
fLVrms
fLVrms
250
250
fLVrms
50
50
mVp-p
GBW
Output Buffer
Gain Bandwidth
1
1
MHz
SR
Output Buffer
Slew Rate
3
3
V/fLs
Cl
Maximum Capacitive
Load
200
200
pF
06:1Wl
II
LMF90
DC Electrical Characteristics The following specifications apply for V+ = + 5V and V- = - 5V unless otherwise specified. Boldface Limits Apply for
TA = TMIN to TMAX; all other limits TA = TJ = 25"C.
LMF90CCN,
LMF90CCWM
Symbol
a.en
Parameter
Conditions
Typ
(Note 7)
Tested
Limit
(Note 8)
LMF90CIJ,
LMF90CMJ
Design
Limit
(Note 9)
Typ
(Note 7)
Tested
Limit
(Note 8)
Design
Limit
(Note 9)
Units
(Limit)
Is
Power Supply Current
fCLK = 500 kHz, VIN1 = VIN2 = GND
2.35
5.0
5.0
2.35
5.0
rnA (Max)
Vas
Output Offset Voltage
W=
W=
W=
fCLK
±50
±60
±80
±120
±140
±170
±120
±140
±170
±50
±60
±80
±120
±140
±170
mV(Max)
mV(Max)
mV(Max)
Your
Output Voltage Swing
RL = 5 kfl
+4.2, -4.7
±4.0
±4.0
+4.2, -4.7
±4.0
V (Min)
VI1
Logical "Low"
Input Voltage
Pins 1, 2, 3, 7, and 10
-4.0
-4.0
-4.0
V (Max)
VI2
Logical "GND"
Input Voltage
Pins 1, 2, 3, 7, and 10
+1.0
-1.0
+ 1.0
-1.0
+1.0
-1.0
V (Max)
V (Min)
VI3
Logical "High"
Input Voltage
Pins 1, 2, 3, and 7
+4.0
+4.0
+4.0
V (Min)
liN
Input Current
Pins 1, 2, 3, 7, and 10
±10
±10
±10
",A (Max)
VIL
Logical "0" Input
Voltage, Pins 5 and 6
Pin 5, XLS = V+
or Pin 6, XLS = GND
-4.0
-4.0
-4.0
V (Max)
VIH
Logical "1" Input
Voltage, Pins 5 and 6
+4.0
+4.0
+4.0
V(Min)
VIL
Logical "0" Input
Voltage, Pin 6
+0.8
+0.8
+0.8
V (Max)
VIH
Logical "1" Input
Voltage, Pin 6
+2.0
+2.0
+2.0
V (Min)
VOL
Logical "0" Output
Voltage, Pin 6
-4.0
-4.0
-4.0
V (Max)
VOH
Logical "1 " Output
Voltage, Pin 6
+4.0
+4.0
+4.0
V (Min)
D = V-, R = V+, fCLK = 167 kHz
D = R = GND, fCLK = 250 kHz
v+, D = GND, R = V-,
= 500 kHz
V+ - V- = 10V, XLS = V- or
V+ = +5V, V- = OV, XLS = +2.5V
XLS = V+ ,llourl = 4 rnA
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Note 2: Operating Ratings indicate conditions for which the device is intended to be functional. These ratings do not guarantee specific performance limits,
however. For guaranteed specifications and test conditions. see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions
listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 3: All voltages are measured w~h respect to GND unless otherwise specified.
Note 4: See AN450 "Surface Mounting Methods and Their Effect on Product Reliability" or Ihe section titled "Surface Mount" found in any current Linear Data
Book for other methods of soldering surface mount devices.
Note 5: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, 0JA and the ambient temperature, TA. The maximum
allowable power dissipation at any temperature is Po = (TJMAX - TpJ/8JA or the number given in the Absolute Maximum Ratings, whichever is lower. For this
device, TJMAX ~ 150"C, and the typical thermal resistance (0JAl when board mounted is 61"C/W for the LMF90CCN, 134"C/W for the LMF90CCWM, and 59"C/W
for the LMF90CIJ and CMJ.
Note 6: Human body model, 100 pF discharged through a 1.5 kfl resistor.
Note 7: Typicals are at TJ
~
2S"C and represent the most likely parametric norm.
Note 8: Tested Limits are guaranteed and 100% tested.
Note 9: Design Limits are guaranteed, but not 100% tested.
Note 10: When the input voltage (VIN) at any pin exceeds the power supplies (VIN < V- or VIN > V +), the current at that pin should be limited to 5 mAo The 20 mA
maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5 rnA to four.
II
1-57
Typical Performance Characteristics
Notch Depth vs
Clock Frequency
Notch Depth vs
Supply Voltage
20
Iii'
~
J
!
...~
40
Notch Depth
vs Temperature
20
20 rT1"TT"""'"TTTTTT"ru:=",
30
301-+++++++++++++++++1
40
J
50
6OL..L..J...J....L..J...~.u..~~..L-I....L...W
-55 -35 -15 5 25 45 65 85 105 125
CLOCK FREQUENCY (kHz)
SUPPLY VOLTAGE (:tV)
Power Supply Current
vs Power Supply Voltage
TEMPERATURE (OC)
Offset Voltage vs
Clock Frequency
Power Supply Current
vs Temperature
i-"
I
I I
TA= 250C I I
fax= 500 kHz
!
180 TA =25OC
160 Vs -:t5V
r-
140
W=;':D=GIID,~'~'V"
uHrHH~~++++trHHH
2.01-h~++++++++++++++1
2.0
lB~~~~~~~~~
1
2
3
4
5
6
7
POWER SUPPLY VOLTAGE (:tV)
120rT~W~=~V'~D~=~G~ND~R~=~V"=-~
Il1Ort~fraxT=,5_00rtkH,Z--n~-r~
90
60
VS=:t5V
0.5
50
11111 II
TA =25OC
Vs=:t5V
W=D=R=GND~f~~2~k~H
W=D=R-GND
~-H-)~
...101'"
111111
D.2
~
W=D=V",R=V'
0.1
40
-55 -35 -15 5 25 45 65 85 105 125
SUPPLY VOLTAGE (:tV)
1
AMBIENT TEMPERATURE (OC)
Passband Width vs
Supply Voltage
D.6 rT1rn"TT"TTTTTTrrrn..,
~
~
::;
-55 -35 -15 5 25 45 65 B5 105 125
AMBIENT TEMPERATURE (OC)
1Il00
100lI0
Stopband Width vs
Clock Frequency
~
Effrn:mmlIEfJJJ
100
CLOCK FREQUENCY (kHz)
Passband Width vs
Temperature
0.1
100lI0
11111
II
W=V',D=GND,R=V"III'I I
W=V',D=GND,
R=V",lnK=5OOkHz
I"r
1Il00
Passband Width vs
Clock Frequency
D.6
80
70
SUPPLY VOLTAGE (:tV)
100
CLOCK FREQUENCY (kHz)
Offset Voltage vs
Temperature
1110
2O!+y9-t-t-1H--+-++++-I
10
AMBIENT TEMPERATURE (OC)
Offset Voltage vs
Supply Voltage
80 W=D=R=GN
eLK= 0 z
20
-55 -35 -15 5 25 45 65 85 105 125
I
D.06r-..."mm-'Trrmr,..,~m
D.05I-H1fH1!!I-~~~++~
W= v+, D=GNQ, R=V;iHlII,.-+++I-IIHI
D.04 l-H1fH1!!I-++H'dT",=,.;25",OC
m-l-IIHI
v =:t5V
ODI
HH-ttIWlf-t++
000 L.....J'-'-'.wJ.LL-.L..J...L.U.UJI-.u..J..U.UII
1
1110
1Il00
100lI0
CLOCK FREQUENCY (kHz)
TUH/l0354-3
1-58
r
Typical Performance Characteristics
is:
."
CD
(Continued)
Q
Stopband Width
vs Supply Voltage
1;
is
S
e:
I
IUI6 T,=25"1:
Stopband Width
vs Temperature
1;
I I
I I I I
I I
IUJW=V+,D=GND,R=V"
fCLK =500kHz I I I
~
r..t
o.os
11.04
8
e:
I I
II I I
II
W= 0 - R= GND,fClJ( -250 kHz
I ILL
D.03
c
~
!~
~
Oll6
o.os
!11111
IIIII I
lli
w=v+, D_GND,R =V",fClK -500kHz
11.04
D.03
W=D=V",R=v+, fCL'= 167 kHz
0.01
1
2
3
4
5
6
7
B
~
0.D2
ODI
1;
1M
II
0.2
1;
is
aE
e:z
0.0
~;j
~-0.2
tlc
-0..4
3
4
5
6
7
B
«
~
~
;:l
4.2
!lI
1111
5
1=
I
0.01
~
-4
"
-oD4
!lI
0.00
0
~
~
3.9
1
10
100
l00D
I
-3.8
1
4
3
5
6
7
B
Positive Output Swing
vs Temperature
4.6
E
!lI
1111
T =25
Vs=t5V
fClJ(= 500 kHz
-«
2
SUPPLY VOLTAGE (tV)
jill
jill
jill
-.jJ)
;:l
0
>
RL =5klll I I
vs=t5~HI
4.5 fClJ(=500kHz
II
4.4
5
5
~
~
4.2
0
-4.5
~
-4.6
-3.9
~1
1
LOAD RESISTANCE (kll)
NEGA1lVE SWING
-8
-10
5 25 45 65 851OS125
!lI _4.21~
I
.jJ)
smVE SWING-
-6
Negative Output Voltage
Swing vs Load Resistance
I
RL =5 kll
4
5
§!
10000
6 fCll(= 500kHz
~
;:l
l00D
B T.=25"1:
5
'"
~
~1
=>
0
E
-o.oz
-om
E
II
R=GND
100
Output Swing
vs Supply Voltage
AMBIENT TEMPERATURE ("1:)
IIII II
T, =25"1:
Vs=t5V
fClJ(=500 kHz
§!
10
10
0.D2
Positive Output Voltage
Swing vs Load Resistance
III
III
....
CLOCK FREQUENCY (kHz)
Vs=t5V
-ss -35 -IS
III
R=~
R=V- or GND
-0.1
5 25 45 65 B5 1115 125
D.03
SUPPLY VOLTAGE (tv)
E
t-- RIJ~
~~--o.o1
9
-o.s
2
0.0
;:l
"
c
I
I
1
~c
2
0
-2
"'8
10
"
V
III
11.04
~
R=V;
iili
0.1
~
III
III
To=25OC
r-vs
[ll"
iS~
YI~=V;-'IRlr'~~~7116HHf
0.2
Clock-to-Center-Frequency
Ratio Deviation
vs Temperature
0
I
To =25"1:
=>~
~9
~i
~~
O~ffI
IDtPERATURE ("1:)
is
~~
Vs=t5V
W= 0= R=GND, fClJ(=250 kHz
-ss -35 -15
Clock-to-Center-Frequency
Ratio Deviation
vs Supply Voltage
~
1;
c
0.D2
~
o
l1'"tt
II
SUPPLY VOLTAGE (tV)
0
Clock-to-Center-Frequency
Ratio Deviation
vs Clock Frequency
10
100
l00D
LOAD RESISTANCE (kII)
-ss -35 -15
5 25 45 65 B5 lOS 125
AMBIENT TEMPERUURE (OC)
Negative Output Swing
vs Temperature
E
'"z
~
-4.5
I
RL =sklill
Vs=:t5V
-4.6 fCLK =500kHz
!lI
;!
~
~
0
~
z
-4.7
-4.B
-4!1
-ss -35 -IS
5 25 45 65 85 lOS 125
AMBIENT IDtPERATURE ("1:)
TLlH/l0354-4
1-59
O'-------------------------------------------------------------~
G)
u.
...
:IE
Pin Descriptions
W (Pin 1)
R (Pin 2)
This 1hree-level logic input sets the width of
the notch. Notch width is fc2-fc1 (see Figure
1). When W is tied to V+ (pin 14), GND (pin
13), orV- (pin 8), the notch width is 0.55 fo,
0.26 fo, or 0.127 fo, respectively.
This three-level logic input sets the ratio of
the clock frequency (fCLI V+) the absolute value 01 current at that pin should be limited
to 5 mA'or less. The sum 01 the currents at all pins that are driven beyond the power supply voltages should not exceed 20 mAo
Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, 9JA, and the ambient temperature, TA. The maximum
allowable power dissipation at any temperature is Po ~ (TJMAX - TAJ/ 9JA or the number given in the Absolute Maximum Ratings, whichever is lower. For this
device, TJMAX ~ 125"C, and the typical junction-to-ambient thermal resistance 01 the LMFIOOACN/CCN when board mounted is 55"C/W. For the LMFIOOAJ/
CCJ, this number increases to 95"C/W and lor the LMFIOOCCWM this number is 66·C/W.
Note 4: The accuracy 01 the Q value is a function 01 the center lrequency (10)' This is illustrated in the curves under the heading "Typical Pelormance Characteristics",
Note 5: VO." Vo.2, and Vosa refer to the internal offsets as discussed in the Applications Information section 3.4.
Note 6: Crosstalk between the internal filter sections is measured by applying a I VRMS 10 kHz signal to one bandpass filter section input and grounding the input
of the other bandpass fitter section. The crosstalk is the ratio between the output of the grounded filter section and the I VRMS input signal of the other section.
Nota 7: The short circuit source current is measured by forcing the output that is being tested to its maximum positive voltage swing and then shorting that output to
the negative supply. The short circun sink current is measured by forcing the output that is being tested to rts maximum negative voltage swing and then shorting
that output to the posHive suPPly. These are the worst case conditions.
Note 8: Typicals are at 25"C and represent most likely parametric norm.
Note 9: Tested limits are guaranteed to National's AOOL (Average Outgoing Qualrty Level).
Note 10: Design limits are guaranteed to National's AOQL (Average OutgOing Quality Level) but are not 100% tested.
Note 11: Human body model, 100 pF discharged through a 1.5 kn resistor.
Note 12: In 50:1 mode the output noise is 3 dB higher.
Note 13: In 50:1 mode the clock feedthrough is.6 dB higher.
1-74
Typical Performance Characteristics
Power Supply Current vs
Power Supply Voltage
12
!"E
10
a
9
9.0
11
~
J
J
/
,
8
as
a
s.o
J
T.=25OC
'elk= 250 kHz -
./
!"E
I
7
5
10
IS
Power Supply Voltago (V)
20
~
en
.I;
V.=U.5V
'"
75
Positive Output Swing
vs Temperature
5
..
·i
E
v =t5V" I"--
.......
'e.= 250 kHz
.....
7.0
-55 -35 -IS 5 25 <45 65 85 105 125
Tomporalure (OC)
6
0
V
~
/
/
./
Output Swing vs
Supply Voltage
Power Supply Current vs
Temperature
~
E
.~
6
2
RLOAD=5kll_ T.=25OC
-2
~
-6
f
1..--' ....
0
-4
............
..... j'-....
2
I
3 4 5 6 7
Supply Voltage (tV)
f
4
E
.e
f
RLOAD =5k11
3
~
-3
I
1
2f- r- V,-:t2.5V
4
.
!
E
RLOAD=5~
-
/
3 1
-
2
V,=t5V
I
-55 -35-15 5 25 <45 65 85 105 125
Tlmporalure (OC)
Tlmporalure (OC)
fCLK/fo Ratio vs Q
101l.4
V,=U.5V
i
i
-3
0
/
100.0
rr
:;_o99B
'"jim
-4
\
-5, 0"
'\...
-
1005
10'
102
Load R.oIstane. (kill
~
....0
)
V,=:t5V
T.=25OC
Vp1n12=OV
I
49.8
)49.6
-
99.4
49.4
99.2
49.2
0
103
uno
I
I
.., 1J
1
/
995
20
40
60
80
100
0
40
1005
i
I III
I
II
i
Q=IOO/
_olm.o
~
-"
99.0
~
0
100
80
-"
V,=U.5V
T.=25OC
VPlnI2=+2.5i /
r
51
Q=IOO/
JQ=IVJ
50
995
99.D
500 1000 1500 2000 2500 3000 3500
60
fCLKIfO Ratio vs fCLK
52
Q=IOII
/I
V,=U.5V
f- TA=25OC
Vpln12=OV
Q=y
Idk (kHz)
20
Q
fCLKIfO Ratio vs fCLK
101.0
I
Q=2
0
Idk =1 11Hz
T.=25OC- r-- VPln12=t- I - -
Q
Q=IOJ
Q=IOO
:l!
V.=:t2.5V-
V
V.=t5V
fCLK/fo Ratio vs fCLK
101.0
i
103
V.=t~
_0
'dk = I YH.'--TA =25OC
' - - I--VpIn12=OV- -
10'
102
Load R..lstance (kll)
/
so.o
V.=:t2.5V-
V.=U.5V
,L'i"'"
fCLK/fo Ratio vs Q
50.2
V.=:t5V
10D.2
E
I
10"
-5
-55 -35 -15 5 25 <45 65 85 105 125
Negative Output Voltage
Swing vs Load Resistance
-21'-..
V.=t5V
~
.e
-4
8
Positive Output Voltage
Swing vs Load Resistance
V.=t5V
E
....
-8
5
V.=U.5V
".,
"..
4
J\
Negative Output Swing
vs Temperature
-2
8
r - I-- QJ2_
/
49
1000
2000
Ielk (kHz)
3000
0
500
1000
1500
2000
2500
Ie. (kHz)
TUH/5645-8
1-75
CI
CI
u::
Typical Performance Characteristics (Continued)
::E
....I
fCLK/fo Ratio vs Temperature
fCLKIfO Ratio vs fCLK
52
~
~
r-- . TV,~t5~
A=25CC
"-
Jl.1Y
~
Q=I00
'
-4
J
20
10
50:1 modo 1
100:1 modo 1
1
o!¢l:I~!~
Q
511
Rallo OovIallon < III
"",
""
\.
\.
.\
........... '\.\
uP
"
\.\.
Q
TL/H/5645-9
1-76
riii:
LMF100 System Block Diagram
....
."
o
o
AGND
CLKA
5DI1DD
L Sh
CUla
TOAGND
+-----+------0\
INVa
Vii
Vi N/AP/HPa Sla
BPa
LPa
TUH/5645-1
Pin Descriptions
This pin activates a switch that connects one of the inputs of each filter's second summer either to AGND
(SAIB tied to V-) or to the lowpass
(LP) output (SAIB tied to V+). This
offers the flexibility needed for configuring the filter in its various modes
of operation.
This is both the analog and digital
positive supply.
This pin needs to be tied to V+ except when the device is to operate
on a single 5V supply and a TTL level clock is applied. For 5V, TTL operation, VD + should be tied to ground
(OV).
Analog and digital negative supplies.
VA - and VD - should be derived
from the same source. They have
been brought out separately so they
can be bypassed by separate capacitors, if desired. They can also be tied
together externally and bypassed
with a single capacitor.
LP(1,20), BP(2,19), The second order lowpass, bandN/AP/HP(3,18)
pass and notchl allpass/highpass
outputs. These outputs can typically
swing to within 1V of each supply
when driving a 5 kO load. For optimum performance, capacitive loading on these outputs should be minimized. For signal frequencies above
15 kHz the capacitance loading
should be kept below 30 pF.
INV(4,17)
The inverting input of the summing
opamp of each filter. These are high
impedance inputs. The non-inverting
input is internally tied to AGND so
the opamp can be used only as an
inverting amplifier.
S1(5,16)
S1 is a Signal input pin used in
modes 1b, 4, and 5. The input impedance is 1lfCLK X 1 pF. The pin
should be driven with a source impedance of less than 1 kO. If S 1 is
not driven with a signal it should be
tied to AGND (mid-supply).
1-77
II
C) r-----------------------------------------------------------------------------------------~
C)
....L&.
:!i
Pin Descriptions (Continued)
LSh(9)
CLK(10,11)
50/100(12)*
AGND(15)
1.0 Definitions of Terms
Level shift pin. This is used to accommodate various clock levels with
dual or single supply operation. With
dual ± 5V supplies and CMOS (± 5V)
or TTL (OV-5V) clock levels, LSh
should be tied to system ground.
For OV-10V single supply operation
the AGND pin should be biased at
+ 5V and the LSh pin should be tied
to the system ground for TTL clock
levels. LSh should be biased at + 5V
for ± 5V CMOS clock levels.
The LSh pin is tied to system ground
for ± 2.5V operation. For single 5V
operation the LSh and Vo+ pins are
tied to system ground for TTL clock
levels.
Clock inputs for the two switched capacitor filter sections. Unipolar or bipolar clock levels may be applied to
the CLK inputs according to the programming voltage applied to the LSh
pin. The duty cycle of the clock
should be close to 50%, especially
when clock frequencies above
200 kHz are used. This allows the
maximum time for the internal
opamps to settle, which yields optimum filter performance.
By tying this pin to V+ a 50:1 clock
to filter center frequency ratio is obtained. Tying this pin at mid-supply
(i.e., system ground with dual supplies) or to V- allows the filter to operate at a 100: 1 clock to center frequency ratio.
This is the analog ground pin. This
pin should be connected to the system ground for dual supply operation
or biased to mid-supply for single
supply operation. For a further discussion of mid-supply biasing techniques see the Applications Information (Section 3.2). For optimum filter
performance a "clean" ground must
be provided.
feu<: the frequency of the external clock signal applied to
pin 10 or 11.
fo: center frequency of the second order function complex
pole pair. fo is measured at the bandpass outputs of the
LMF100, and is the frequency of maximum bandpass gain.
(Figure 1).
fnotch: the frequency of minimum (ideally zero) gain at the
notch outputs.
fz: the center frequency of the second order complex zero
pair, if any. If fz is different from fo and if Qz is high, it can be
observed as the frequency of a notch at the allpass output.
(Figure 13).
Q: "quality factor" of the 2nd order filter. Q is measured at
the bandpass outputs of the LMF100 and is equal to fo divided by the -3 dB bandwidth of the 2nd order bandpass
filter (Agure 1). The value of Q determines the shape of the
2nd order filter responses as shown in Figure 6.
Qz: the quality factor of the second order complex zero pair,
if any. Qz is related to the allpass characteristic, which is
written:
where Qz = Q for an all-pass response.
HOBP: the gain (in VIV) of the bandpass output at f = fo.
HOLP: the gain (in VIV) of the lowpass output as f -+ 0 Hz
(Figure 2).
HOHP: the gain (in V /V) of the highpass output as f -+
fCLK/2 (Figure 3).
HON: the gain (in V IV) of the notch output as f -+ 0 Hz
and as f -+ fCLK/2, when the notch filter has equal gain
above and below the center frequency (Figure 4). When the
low-frequency gain differs from the high-frequency gain, as
in modes 2 and 3il (Agures 10 and 12), the two quantities
below are used in place of HON.
HON1: the gain (in VIV) of the notch output as f -+ 0 Hz.
HON2: the gain (in VIV) of the notch output as f -+ fCLK/2.
'This device is pln-for-pin compatible with the MFIO except for the following
changes:
I. Unlike the MFIO, the LMFIOO has a single positive supply pin rotA+)'
2. On the LMFloo Vo + is a control pin and Is not the digital positive supply
as on the MF10.
3. Unlike tihe MF10, the LMFloo does not support the current limiting mode.
When the 50/100 pin Is tied to V- the LMF100 will remain in the 100:1
mode.
1-78
r-
s:::
....
1.0 Definitions of Terms (Continued)
."
HSp(s) =
;;-
a
S2
~_ 90
1-----.....
HOBP
0.707 HOBP I----I--I-\.
=
if:
o
o
HOSps
--='---
+ SWo + Wo2
Q
451----"10..
0 I----+~
-45 I----I-+"......
-90
i
1---++-+-"""fL 10 IH
I (LOG SCALE)
IL I, IH
I (LOG SCALE)
TLlH/5645-20
TUH/5645-19
(b)
(a)
FIGURE 1. 2nd-Order Bandpass Response
>
~
..
Hop ..
f-;:::;;::;;....."
HoLP
0
~
llJ -90 I - - - - " l .
"
~
HOp
HOHP
0.707 HOHP
r""'===i~~--
~
llJ -90 I - - - - - f
~
~
-180
10
I (LOG SCALE)
Ie
Ip
I (LOG SCALE)
TL/H/5645-24
TLlH/5645-23
(b)
(a)
fp = fo X
[~1 - 2~2]-1
HOp = HOHP X 1
1
rT
'Q\}1 - 4Q2
FIGURE 3. 2nd-Order High-Pass Response
1-79
III
g
.,..
II.
1.0 Definitions of Terms (Continued)
::E
..J
90
>
;;:
~ 45
HON
;; 0.707 HON
g
III 0
c
iE -45
-H
I---~--f----
I---~
~
____~~____~
It fa IN
IL 10 IN
I (LOG SCALE)
I (LOG SCAlE)
TUH/5645-25
TUH/5645-26
(a)
(b)
FIGURE 4. 2nd-Order Notch Response
>
ez
HAP
I-----"T""--
~
!!i-ISO I----~
:ii
IE
t:::==±==::::
-360
fa
fa
I (lOG SCAlE)
I (lOG SCALE)
TL/H/5645-27
TL1H/5645-28
(a)
(b)
FIGURE 5. 2nd-Order All-Pass Response
(b) Low Pass
(a) Bandpass
20
20
10
10
0-1
:"'10..
~
-20
-30
-40
...... "
IJ
,"-
t7 ~1-2i
0.1
0.5 1
2
FREQUENCY (Hz)
..... ~~~.707-
z -10
g
o-~
""
0-0.5
~
0.1
0.2
0.5 1.0 2.0
FREQUENCY (Hz)
(d) Notch
I
-20
I.
"'
I--
~
., .,.
100<
0-0.5
'Q=~.L
V
~
"
-40
0.1 0.2
10
,
0-10_
0.5 1.0 2
FREQUENCY (Hz)
5
10
(e) All-Pass
-60
ffi -120
i
!e
;; -10 f-+--+-"~pt.,;;
~
5.0
~
-30
"-
-40
10
0.707
~
'-,
-30
r-o
'"
.
r-t-0=~ct-~0-2--"
a i...,
;; -10
;;:
....... "-
1
-20 -0 0.2
l.......
10
L !!-.~~!±=
i
"-
"" .......
."~ o'!,o ~ ,
.....
l"
'I'll \"
(c) High-Pass
20
-- 1-- 0 =10 ~0=5+-
-20~+-1-~~~;i_
Q-5
'-
-180
l"'o.. 0=0.2
f""IoL
... -240
. \y'=1
-30
1-+--+-+-+--1--1
-300
-40
__~~__~~
0.1 0.2 0.5
1.0 2
10
-360
L-~~
'\c IX
0.1 0.2
FREQUENCY (Hz)
0.5
1
2
5
10
FREOUENCY (Hz)
TUH/5645-29
FIGURE 6. Response of various 2nd-order filters as a function of Q. Gains
and center frequencies are normalized to unity.
1-80
,-----------------------------------------------------------------------------, r
3:
2.0 Modes of Operation
The LMF100 is a switched capacitor (sampled data) lilter.
To fully describe its transfer functions, a time domain analysis is appropriate. Since this is cumbersome, and since the
LMF100 closely approximates continuous lilters, the following discussion is based on the well-known frequency domain. Each LMF100 can produce two full 2nd order functions. See Table I lor a summary 01 the characteristics 01 the
various modes.
a
BW
..!!L
BW
= quality lactor of the complex pole pair
= the -3 dB bandwidth of the bandpass
output.
HOLP
fnotch = fo (See Figure 7)
=
=
center frequency of the complex pole pair
HOlP
= Lowpass gain (as I
HOSp
= Bandpass gain (at I = (0) =
HON
=
0)
Notch output gain as I ~
Hosp
Q
or Hosp
=
HOLP X
a
HOlP(peak) "" a x HOlP (for high a's)
MODE 1a: Non-Inverting BP, LP (See Figure 8)
10
center frequency of the imaginary zero pair = 10.
~
=
= HON X O.
fCLK IClK
= --or-100
50
Inotch
o
Circuit dynamics:
MODE 1: Notch 1, Bandpass, Lowpass Outputs:
fa
..."o
R3
R2
=
a
l~fCLK/2
R2
R1
R3
R1
}=
-
100
50
a
R3
HOlP
-1; HOLP(peak) "" a x HOLP (for high a's)
R3
HOSPl
R2
Rl
= fCLK or fClK
HOSP2
R2
R2
= 1 (non-inverting)
Circuit dynamics: HOSPl = a
Note: VIN should be driven from a low impedance
«1
kO) source.
TL/H/5645-11
FIGURE 7. MODE 1
V,N
TLlH/5645-4
FIGURE 8. MODE 1a
1-81
o ,--------------------------------------------------------------------------,
o
.,...
u..
:::iii
...I
2.0 Modes of Operation
(Continued)
MODE 1b: Notch 1, Bandpass, Lowpass Outputs:
MODE 2: Notch 2, Bandpass, Lowpass: fnotch
fO
= center frequency of the complex pole pair
= fClK X
100
fnotch
fO
50
= center frequency of the imaginary zero pair = fo.
R2
0) = - 2Rl
= Lowpass gain (as f -
HOSp
R3
= Bandpass gain (at f = fo) = - Rl
HON
= Notch output gain as f _ 0
} = - R2
f - fClK/2
R!
=..!2.-=R3
BW R2
x
+
1
Q
= quality factor of the complex pole pair
50
+
1
R2/R3
HOlP
= Lowpass output gain (as f -
0)
R2/Rl
.J2
R2/R4
+
1
Hosp
= Bandpass output gain (at f = fo) = - R3/Rl
HON!
= Notch output gain (as f -
= the -3 dB bandwidth of the bandpass output.
=
1 or fClK ~ R2
50
R4
fClK :fClK
= 100 or
0)
R2/Rl
Circuit dynamics:
HOlP
+
fnotch
~R2/R4
= quality factor of the complex pole pair
BW
fo
= center frequency
= fClK ~ R2
100
R4
.J2 or fClK X .J2
HOlP
Q
<
(See Figure 10)
fnotch = fo (See Figure 9)
R2/R4
Hosp
In
.J2 Q or Hosp = HOlP X Q X .2
HON2
+
1
= Notch output gain (asf _
fC~K)
= -R2/Rl
Filter dynamics: Hosp = Q ~ HOlP HON2 = ~ HON! HON2
HOSp
HOlP(peak) "" Q X HOlP (for high Q's)
R3
TUH/5645-14
FIGURE 9. MODE 1b
R4
TL/H/5645-36
FIGURE 10. MODE 2
1-82
2.0 Modes of Operation
r3:
(Continued)
MODE 3a: HP, BP, LP and Notch with External Op Amp
MODE 3: Highpass, Bandpass, Lowpass Outputs
(See Figure 11)
10
a
= IClK X
100
(See Figure 12)
fR2 r IClK x fR2
VFi4 0 50 VFi4
10
100
a
= quality lactor 01 the complex pole pair
=
fR2 X R3
VFi4 R2
HOHP
. (
IClK)
R2
HOHP = H·Ig hpass gain
at! --+"2 = - Rl
= Bandpass gain (at I = 10) = _
HOlP
= Lowpass gain (as I --+ 0) = _ R4
=
fR2 or ICLK x fR2
VFi4 50 VFi4
fR2 x R3
VFi4 R2
R2
Rl
R3
HOBP
HOBP
R3
Rl
R4
Rl
HOlP
Rl
Circuit dynamics: RR2 = HOHP; HOBP =
4 HOlP
= IClK X
Rl
fRh or IClK fRh
= notch Irequency = IClK
VRj
100
~HOHP X HOlP X a
HON
HOlP(peak) "" a X HOlP (for high a's)
50
vRj
= gain 01 notch at
I = fa =
II a(:~ HOlP -
:~ HOHP) II
HOHP(peak) "" a X HOHP (lor high a's)
Hnt
= gain 01 notch (as I --+ 0) =
Hn2
= gain 01 notch ( as I --+
R
R~
X HOlP
IC~K)
Rg
= - - X HOHP
Rh
H4
'In Mode 3, the feedback loop is closed
around the input summing amplifier, the
finite GBW product of this op amp caus·
es a slight Q enhancement. If this is a
problem, connect a small capacitor
(to pF-tOO pF) across R4 to provide
some phase lead.
TL/H/5645-5
FIGURE 11. MODE 3
H4
H,
NOTCH
OUT
TLlH/5645-10
FIGURE 12. MODE 3a
1-83
'"TI
.....
o
o
o
o
....
u..
:!i
2.0 Modes of Operation (Continued)
MODE 4: Allpass, Bandpass, Lowpass Outputs
(See Figure 13)
fo
MODE 5: Numerator Complex Zeros, BP, LP
(See Figure 14)
= center frequency
= fClK or fClK.
100
50 '
fo
=
fz
=
fo
R3
=BW=R2;
Qz = quality factor of complex zero pair =
:~
Q
Qz
=41
fClK)
R2
HOAP' = Affpassgain ( atO < f < 2
= - R1 = - 1
(:~ + 1) =
-
R3
R1/R4 X R1
R1(R2 + R4)
= Lowpass gain (as f -+ 0)
= -
~1
= gain at C.Z. output (as f -+ 0 Hz)
-R2(R4 - R1)
For AP output make R1 = R2
HOlP
+ R2 X fClKor~1 + R2 X fClK
R4
100
R4
50
- R1 X fClKor~1 _ R1 X fClK
R4
100
R4
50
R3
= 41 + R2/R4 x R2
fz' = center frequency of the complex zero :::: fo
Q
~1
= gain at C.Z. output ( as f -+
2
HOSp
=_(R2+1)xR3
R1
R2
HOlP
=_(R2+R1)xR4
R2 + R4
R1
Hosp = Bandpass gain (at f = fo)
= _ R3 (1 + R2) = -2 (R3)
R2
R1
R2
fC~K)
Circuit dynamics: Hosp = (HOlP) x Q = (HOAP + 1)Q
'Due to the sampled data nature of the fllter, a slight mismatch 01 Iz and fo
occurs causing a 0.4 dB peaking around '0 of the allpass filter amplitude
response (which theoretically should be a straight line). If this is unacceptable, Mode 5 is recommended.
TL/H/5645-6
FIGURE 13. MODE 4
R4
TLlH/5645-15
FIGURE 14. MODE 5
1-84
=
-R~2
r-
2.0 Modes of Operation
=
MODE 6b: Single Pole LP Filler (Inverting and Non·
Inverting) (See Figure 16)
cutoff frequency of LP or HP output
=
= R2 fClK or R2 fClK
R3 100
HOlP
HOHP
....o==
'TI
(Continued)
MODE 6a: Single Pole, HP, LP Filter (See Figure 15)
R3 50
cutoff frequency of LP outputs
'" R2 fClK or R2 fClK
R3100
R3 50
R3
Rl
R2
Rl
=
1 (non-inverting)
R3
R2
HI
VIN -"tN~-I
VTLlH/5645-16
FIGURE 15. MODE 6a
LPA (N.INV.) VIN
LPA (INV)
TL/H/5645-7
FIGURE 16. MODE 6b
1-85
o
C)
C)
....
LL
:!!
...J
r----------------------------------------------------------------------------------,
2.0 Modes of Operation (Continued)
MODE 6c: Single Pole, AP, LP Filter (See Figure 17)
fCLK
MODE 7: Summing Integrator (See Figure 18)
= integrator time constant
T
fCLK
= 5Qor"1OO
1 (asf
~
=
HOAP
= -1 (as f ~ fCLK/2)
HOLP
= -2
R1
=
R2
=
16
8
fCLK
fCLK
=-or-
0)
HOAP
R3
R3
TLlH/5645-17
FIGURE 17. MODE 6c
IN2
OUl2
OUll
1(20)
Rl
IN 1>--'V'iIIr.....
TL/H/5B45-37
Equivalent Circuit
OUll
INl >----t
QUl2
.~-....,
IN2>-------I
TL/H/5645-38
K ~.':!g
R1
OUT1
~
OUT2
~ !IOUT1 dt
-
~ IIN1
T
dt - !IIN2dt
T
T
FIGURE 18. MODE 7
1·86
r-
s::
2.0 Modes of Operation (Continued)
TABLE I. Summary of Modes. Realizable filter types (e.g. low-pass) denoted by asterisks.
Unless otherwise noted, gains of various filter outputs are inverting and adjustable by resistor ratios.
Mode
1
BP
LP
·
*
HP
1a
HOlP=+1
1b
*
*
2
·
·
·
·
·
3a
*
4
·
S
*
Adjustable
felK/fo
3
No
2
No
May need input buffer. Poor dynamics
for highQ.
·
3
No
Useful for high
frequency applications.
*
3
Yes (above
fClK/SO or
fClK/100)
4
Yes
Universal StateVariable Filter. Best
general-purpose mode.
7
Yes
As above, but also
includes resistortuneable notch.
*
3
No
Gives Allpass response with HOAP = - 1
and HOlP = - 2.
.
4
Yes
Gives flatter all pass
response than above
if R1 = R2 = O.02R4'
3
Yes
Single pole.
2
Yes
Single pole.
3
No
Single pole.
2
Yes
Summing integrator with
adjustable time constant.
AP
·
(2)
HOBP1 = -Q
HOBP2 = + 1
3
Number of
Resistors
N
.
*
·
·
·
.
Sa
*
Sb
(2)
HOlP1 = + 1
-R3
HOlP2 =
Notes
R2
Sc
·
*
7
3.0 Applications Information
The LMF100 is a general purpose dual second-order state
variable filter whose center frequency is proportional to the
frequency of the square wave applied to the clock input
(fClK)' The various clocking options are summarized in the
following table.
Clocking Options
Clock Levels
LSh
Vo+
-SVand +SV
-SVand +SV
TTL (OV to + SV)
CMOS (-SVto +SV)
OV
OV
+SV
+SV
OVand 10V
OVand 10V
TTL (OV to SV)
CMOS (OV to + 10V)
OV
+SV
+10V
+10V
OV
+2.SV
OV
+2.SV
OV
+SV
Power Supply
- 2.SV and + 2.SV CMOS
( - 2.SV to + 2.SV)
OVandSV
TTL (OV to + SV)
OVandSV
CMOS (OV to + SV)
By connecting pin 12 to the appropriate dc voltage, the filter
center frequency. fo. can be made equal to either fClK/100
or fClK/SO. fo can be very accurately set (within ±O.S%) by
using a crystal clock oscillator, or can be easily varied over
a wide frequency range by adjusting the clock frequency. If
desired, the fClK/fo ratio can be altered by external resistors as in Figures 10, 11, 12, 13, 14, 15 and 16. This is
useful when high-order filters (greater than two) are to be
realized by cascading the second-order sections. This al·
lows each stage to be stagger tuned while using only one
clock. The filter Q and gain are set by external resistor ratios.
All of the five second·order filter types can be built using
either section of the LMF100. These are illustrated in Figures 1 through 5 along with their transfer functions and
some related equations. Figure 6 shows the effect of Q on
the shapes of these curves.
1-87
'"n
......
o
o
r-------------------------------------------------------------------3.0 Applications Information (Continued)
u..
o
o
.,...
:::!5
..J
3.1 DESIGN EXAMPLE
In order to design a filter using the LMF100, we must define
the necessary values of three parameters for each secondorder section: fo, the filter section's center frequency; Ho,
the passband gain; and the filter's Q. These are determined
by the characteristics required of the filter being designed.
In most filter designs involving multiple second·order
stages, it is best to place the stages with lower Q values
ahead of stages with higher Q, especially when the higher Q
is greater than 0.707. This is due to the higher relative gain
at the center frequency of a higher-Q stage. Placing a stage
with lower Q ahead of a higher-Q stage will provide some
attenuation at the center frequency and thus help avoid clipping of signals near this frequency. For this example, stage
A has the lower Q (0.785) so it will be placed ahead of the
other stage.
As an example, let's assume that a system requires a
fourth-order Chebyshev low·pass filter with 1 dB ripple, unity
gain at dc, and 1000 Hz cutoff frequency. As the system
order is four, it is realizable using both second-order sections of an LMF100. Many filter design texts (and National's
Switched Capacitor Filter Handbook) include tables that list
the characteristics (fa and Q) of each of the second-order
filter sections needed to synthesize a given higher-order fil·
ter. For the Chebyshev filter defined above, such a table
yields the following characteristics:
For the first section, we begin the design by choosing a
convenient value for the input resistance: R1A = 20k. The
absolute value of the passband gain HOlPA is made equal
to 1 by choosing R4A such that: R4A = -HOLPAR1A = R1A
= 20k. If the 50/100/CL pin is connected to mid·supply for
nominal 100:1 clock-to-center-frequency ratio, we find R2A
by:
faA = 529 Hz
QA = 0.785
fOB = 993 Hz
QB = 3.559
For unity gain at dc, we also specify:
=
R2A
fOA2
=
4
(529)2_
R4A(fClK/l00)2
2 X 10 X (1000)2 - 5.6kand
R3A = QA ~R2AR4A = O. 785~5.6 x 103 x 2 x 104 = 8.3k
The resistors for the second section are found in a similar
fashion:
HOA = 1
HOB = 1
The desired clock-to-cutoff-frequency ratio for the overall
filter of this example is 100 and a 100 kHz clock signal is
available. Note that the required center frequencies for the
two second-order sections will not be obtainable with clockto-center-frequency ratios of 50 or 100. It will be necessary
.
fClK
to adjust - - externally. From Table I, we see that Mode 3
fa
R1B = 20k
R4B
R1B = 20k
R = R
fOB2
_
(993)2 _
2B
4B(fCLK/l00)2 - 20k(1OOo)2 - 19.7k
R3B = QB~R2BR4B =3.559~1.97 X 104 x 2 x 104 = 70.6k
The complete circuit is shown in Figure 19 for split ±5V
power supplies. Supply bypass capacitors are highly recommended.
can be used to produce a low· pass filter with resistor-adjust·
able center frequency.
RIB
20k
, . . . . - - - Your
~----~~------4---~
LP s
BPs
....Wlr-..::..t N/ AP/HP A
N/ AP/HP s
INVA
20k
5
INVs
Sl A
20
R4B
20k
19
R3B
70.6 k
18
R2B
19.7 k
17
Sls
lMF100
-5V
7
+5V
0.1
JlJL.
VA+
VA-
Vo+
Vo-
l Sh.
14
-5V
0.1
50/100/Cl
11
-l--=======--J
10
CLOCK IN
feLK = 100 kHz
AGND
SA/s
CLKA
ClKs
TL/H/5645-30
FIGURE 19. Fourth-order Chebyshev low-pass filter from example in 3.1.
± 5V power supply. OV-5V TTL or ± 5V CMOS logic levels.
1-88
.-----------------------------------------------------------------------------, r
!i:
3.0 Applications Information (Continued)
-n
....
C)
C)
R1B
20k
VOUT
LPA
LP B
SPA
SPB
N/ AP/HP A
N/ AP/HP B
INVA
VIN
Sl A
INVe
LMFlOO
20
R4B
20k
19
R3B
70.6k
18
R2S
19.7k
17
Sle
AGND
SAle
VA+
VA-
Vo+
VoSO/100/CL
-= 10
.JUL
CLKA
CLKB
11
CLOCK IN
fCLK= 100kHz
TLlH/5645-31
FIGURE 20. Fourth-order Chebyshev low-pass filter from example in 3.1. Single + 10V power supply. OV-5V TTL logic
levels. Input signals should be referred to half-supply or applied through a coupling capacitor.
, ,~"'. .
hE
y+
"::"
T
"::"
y+
y+
"2
2k,;R ,;100k
0.1I'F';C'; 470 I'F
TL/H/5645-33
TL/H/5645-32
TLlH/5645-34
(a) Resistive Divider with
Decoupling Capacitor
(b) Voltage Regulator
(c) Operational Amplifier
with Divider
FIGURE 21. Three Ways of Generating V2+ for Single-Supply Operation
1-89
C)
C)
,...
II.
:E
....I
r---------------------------------------------------------------------------------,
3.0 Applications Information (Continued)
Typical values for these offsets with 5A1B tied to V + are:
3.2 SINGLE SUPPLY OPERATION
The LMF100 can also operate with a single·ended power
supply. Figure 20 shows the example filter with a single·end·
ed power supply. VA + and VD + are again connected to the
positive power supply (4 to 15 volts), and VA - and VD - are
connected to ground. The AGND pin must be tied to V+ 12
for single supply operation. This half·supply point should be
very "clean", as any noise appearing on it will be treated as
an input to the filter. It can be derived from the supply volt·
age with a pair of resistors and a bypass capacitor (Figure .
21a), or a low·impedance half·supply voltage can be made
using a three-terminal voltage regulator or an operational
amplifier (Figures 21b and 21c). The passive resistor divider
with a bypass capacitor is sufficient for many applications,
provided that the time constant is long enough to reject any
power supply noise. It is also important that the half-supply
reference present a low impedance to the clock frequency,
so at very low clock frequencies the regulator or op-amp
approaches may be preferable because they will require
smaller capacitors to filter the clock frequency. The main
power supply voltage should be clean (preferably regulated)
and bypassed with 0.1 ",F.
VOS1 = opamp offset = ±5 mV
VOS2 = ±SO mVat 50:1 or 100:1
VOS3 = ±15 mV at 50:1 or 100:1
When 5A1B is tied to V-, VOS2 will approximately halve.
The dc offset at the BP output is equal to the input offset of
the lowpass integrator (VOS3). The offsets at the other outputs depend on the mode of operation and the resistor ratios, as described in the following expressions.
Mode 1 and Mode 4
(6 +
1
+
VOS(N)
= VOS1
VOS(BP)
= VOS3
VOS(lP)
= VOS(N) - VOS2
IIHolPI!) -
V~S3
Mode 1a
Vos(N.INV.BP) = ( 1
3.3 DYNAMIC CONSIDERATIONS
1)
+Q
VOS1
VOS3
- Q
Vos(lNV.BP)
= VOS3
Vos(LP)
= Vos(N.INV.BP) - VOS2
Mode 1b
The maximum signal handling capability of the LMF100, like
that of any active filter, is limited by the power supply voltages used. The amplifiers in the LMF100 are able to swing
to within about 1 volt of the supplies, so the input signals
must be kept small enough that none of the outputs will
exceed these limits. If the LMF100 is operating on ± 5 volts,
for example, the outputs will clip at about 8Vp-p. The maximum input voltage multiplied by the filter gain should therefore be less than 8Vp.p.
VOS(N)
VOS(BP)
VOS(lP)
= VOS1 ( 1
+ -A2
+ -A2)
- -A2
VOS3
AS
A1
AS
= VOS3
= VOS(N) _ VOS2
2
2
Mode 2 and Mode 5
Note that if the filter Q is high, the gain at the lowpass or
highpass outputs will be much greater than the nominal filter
gain (Rgure 6). As an example, a lowpass filter with a Q of
10 will have a 20 dB peak in its amplitude response at fa. If
the nominal gain of the filter (HOlP) is equal to 1, the gain at
fa will be 10. The maximum input signal at fa must therefore
be less than 800 mV p_p when the circuit is operated on ±5
volt supplies.
VOS(N)
Also note that one output can have a reasonable small voltage on it while another is saturated. This is most likely for a
circuit such as the notch in Mode 1 (Figure 7). The notch
output will be very small at fa, so it might appear safe to
apply a large signal to the input. However, the bandpass will
have its maximum gain at fa and can clip if overdriven. If one
output clips, the performance at the other outputs will be
degraded, so avoid overdriving any filter section, even ones
whose outputs are not being directly used. Accompanying
Figures 7 through 17 are equations labeled "circuit dynamics", which relate the Q and the gains at the various outputs.
These should be consulted to determine peak circuit gains
and maximum allowable signals for a given application.
Mode 3
2)
1
(A
Ap + 1 VOS1 X 1 + A2/A4
+
V
1
OS2 1 + A4/A2
VOS3
aJ1 +A2/A4:
Ap = A111ASIIA4
VOS(BP)
= VOS3
VOS(lP)
= VOS(N) - VOS2
VOS(HP)
=VOS2
VOS(BP)
=VOS3
VOS(lP)
= VOS1 [1 + :;] - VOS2(::)
- VOS3(::)
Ap = A111A211AS
Mode 6a and 6c
3.4 OFFSET VOLTAGE
The LMF1 OO's switched capacitor integrators have a slightly
higher input offset voltage than found in a typical continuous
time active filter integrator. Because of National's new
LMCM05 process and new design techniques the internal
offsets have been minimized, compared to the industry
standard MF10. Figure 22 shows an equivalent circuit of the
LMF1 00 from which the output dc offsets can be calculated.
VOS(HP)
= VOS2
VOS(lP)
A3)
A3
A3
= VOS1 ( 1 + - + - - VOS2
A2
A1
A2
Mode6b
1-90
VOS(lP (N.INV))
= VOS2
VOS(lP (INV»
A3)
A3
= VOS1 ( 1 + - - VOS2
A2
A2
r-
s:::
....o'TI
3.0 Applications Information (Continued)
o
LP
TLlH/5645-12
FIGURE 22. Offset Voltage Sources
the unused side B opamp. The Q is 10 and the gain is 1 VIV
in the passband. However, fClK/fo = 1000 to allow for a
wide input spectrum. This means that for pin 12 tied to
ground (100:1 mode), R4/R2 = 100. The offset voltage at
the lowpass output (LP) will be about 3V. However, this is an
extreme case and the resistor ratio is usually much smaller.
Where necessary, the offset voltage can be adjusted by using the circuit of Figure 24. This allows adjustment of VOS1,
which will have varying effects on the different outputs as
described in the above equations. Some outputs cannot be
adjusted this way in some modes, however (VOS(BP) in
modes la and 3, for example).
In many applications, the outputs are ac coupled and dc
offsets are not bothersome unless large signals are applied
to the filter input. However, larger offset voltages will cause
clipping to occur at lower ac signal levels, and clipping at
any of the outputs will cause gain nonlinearities and will
change fo and Q. When operating in Mode 3, offsets can
become excessively large if R2 and R4 are used to make
fClK/fo significantly higher than the nominal value, especially if Q is also high.
For example, Figure 23 shows a second-order 60 Hz notch
filter. This circuit yields a notch with about 40 dB of attenuation at 60 Hz. A notch is formed by subtracting the bandpass output of a mode 3 configuration from the input using
R4
R3
R2
Rl
VIN
3
4
VOUT
SPA
N/AP/HPA
RI
INVA
51 A
-5V
20
lPA
2
Rh
Rl
R2
R3
R4
Rg
RI
Rh
= 100 kll
= 1 kll
= 100 kll
= 100 kll
= 10 kll
= 10 kll
= 10 kll
lMF100
5A/B
VA-
+5V
ClK IN...nn..
fclk= 60 kHz
~-+------t--5V
Vol5h.
ClKA
elKs
TL/H/5645-39
FIGURE 23. Second-Order Notch Filter
1-91
•
o
o
....
u..
3.0 Applications Information (Continued)
::l
5V SUPPLY
-=
R3
TLlH/5645-13
FIGURE 24. Method for Trimming Vos
3.5 SAMPLED DATA SYSTEM CONSIDERATIONS
Another characteristic of sampled-data circuits is that the
output signal changes amplitude once every sampling period, resulting in "steps" in the output voltage which occur at
the clock rate (Figure 25). If necessary, these can be
"smoothed" with a simple R-C low-pass filter at the LMF100
output.
The LMF100 is a sampled data filter, and as such, differs in
many ways from conventional continuous-time filters. An important characteristic of sampled-data systems is their effect on signals at frequencies greater than one-half the
sampling frequency. (The LMF100's sampling frequency is
the same as its clock frequency.) If a signal with a frequency
greater than one-half the sampling frequency is applied to
the input of a sampled data system, it will be "reflected" to
a frequency less than one-half the sampling frequency.
Thus, an input signal whose frequency is f5/2 + 100 Hz will
cause the system to respond as though the input frequency
was f5/2 - 100 Hz. This phenomenon is known as "aliasing", and can be reduced or eliminated by limiting the input
signal spectrum to less than f5/2. This may in some cases
require the use of a bandwidth-limiting filter ahead of the
LMF100 to limit the input spectrum. However, since the
clock frequency is much higher than the center frequency,
this will often not be necessary.
The ratio of fCLK to fe (normally either 50:1 or 100:1) will
also affect performance. A ratio of 100:1 will reduce any
aliasing problems and is usually recommended for wideband input signals. In noise-sensitive applications, a ratio of
100: 1 will result in 3 dB lower output noise for the same filter
configuration.
The accuracy of the fCLK/fo ratio is dependent on the value
of Q. This is illustrated in the curves under the heading
"Typical Performance Characteristics". As Q is changed,
the true value of the ratio changes as well. Unless the Q is
low, the error in fCLK/fo will be small. If the error is too large
for a specific application, use a mode that allows adjustment
of the ratio with external resistors.
100:1
50:1
TLlH/5645-35
FIGURE 25. The Sampled-Data Output Waveform
1-92
,------------------------------------------------------------------------, r
iii:
~National
"T1
-.
I\)
o
~ Semiconductor
LMF120 Mask-Programmable
Switched-Capacitor Active Filter System
General Description
The LMF120 is a mask-programmable switched-capacitor
filter capable of realizing virtually any filter response up to
twelve poles using six independent biquad blocks. It is customized to meet specific application requirements through
the use of automated design techniques. Circuit realization
occurs during the final metal-mask stage of the manufacturing process.
Three sample-and-hold inputs and three buffered outputs
allow one, two, or three independent filters on a single chip.
Each of the filters may be any type: high-pass, low-pass, allpass, bandpass, or notch.
The center or cutoff frequency of each filter is determined
by the clock frequency. The clock signal can be supplied by
an external source, or it can be generated by the internal
oscillator, using an external crystal and two capaCitors. An
on-board programmable divider chain can divide the clock
input frequency by up to 256 so that each on-chip filter can
have a different cutoff/center frequency. Accuracy is enhanced by close matching of the internal components: the
ratio of the clock frequency to the center/corner frequency
is typically accurate to ±0.5%, and is guaranteed to ± 1.5%
over the full temperature range.
The customization process is initiated by submitting transfer
functions, pole and zero locations, or band diagrams to National Semiconductor. A worksheet is included in this datasheet, which can be returned to National Semiconductor for
an initial evaluation. Each filter is computer-optimized to
best meet the requested specifications, and computer simulations are produced for approval before prototyping begins.
Features
• Mask-programmable for virtually any filter response
• All filter types (low-pass, high-pass, bandpass, notch,
all-pass)
• All filter approximations (Butterworth, Chebyshev, Elliptic, Bessel, etc.)
• Up to 12 poles and right-half-plane zeros in one 16-pin
package
• One, two, or three filters per package
• Wide Q range: up to 100 per biquad
• Choice of internal or external clock
• No external components other than clock or crystal and
two capacitors
• Programmable clock divider: + 2 to + 256
• Center frequency accuracy: ±1.5% over temperature
• Supply voltage range: ±2V to ±7.5Vor +4V to +14V
Applications
•
•
•
•
Anti-alias filters
Real-time audio analyzers
Biomedical instrumentation
Cellular telephones
Simplified Block Diagram
IN 1 11
IN 2 12
IN 3
14
y+
16
v-
8
GND
8
I
I
S/H
BIQUAD 1
6
XTAL 1
7 XTAL 2
BIQUAD 2
10 eLK OUT
BIQUAD 3
5 OUT 1
21
S/H 3
BIQUAD 4
4 OUT2
1
BIQUAD 5
3 OUT3
BIQUAD 6
TL/H/10353-1
1-93
Absolute Maximum Ratings
(Notes 1 & 3)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Total Supply Voltage (V+ - V-)
-0.3Vto +16V
V- - 0.3V to V+ + 0.3V
Voltage at Any Pin
Input Current per Pin (Note 10)
Total Input Current (Note 10)
Power Dissipation (Note 5)
Storage Temperature Range
150'C
-65'C to + 150'C
ESD Susceptibility (Note 6)
2000V
Operating Ratings (Notes 2 & 3)
±5mA
±20mA
Lead Temp. (Soldering 10 sec.)
Dual-In-Line Package (Plastic)
Surlace Mount Pkg. (Note 4)
Vapor Phase (60 sec.)
Infrared (15 sec.)
500mW
Maximum Junction Temperature
Temperature Range
LMF120CCN, LMF120CCV
LMF120CIJ
LMF120CMJ
SupplyVoltage(V+ -\r)
300·C
215'C
220'C
TMIN S; TA S; TMAX
O'C S; TA S; +70'C
-40'C S; TA S; +85'C
- 55'Cs; T A S; + 125'C
4.0Vto 14V
Filter Electrical Characteristics
Because the LMF120's perlormance characteristics vary depending on the programming mask configuration, many of the
speCifications listed in this section are given only as typical values. These are intended to serve as guidelines for assessing the
capabilities of the IC and the feasibility of a desired filter response. Specific filter perlormance data (obtained by computer
simulation) will be supplied by National Semiconductor after the desired characteristics for the particular filter implementation
have been defined. Test frequencies and attenuation values appropriate to the application can then be chosen. The following
specifications apply for V+ = + 5V and V- = -5V unless otherwise specified. Boldface limits apply for TMln to TMa,,;
all other limits apply for T A = TJ = 25·C.
Symbol
Parameter
Conditions
Typical
(Note 7)
Tested
Limit
(Note 8)
Design
Limit
(Note 9)
Units
(Limit)
10
1.5
Hz (Min)
MHz (Max)
4
MHz (Max)
Center or Cutoff
Frequency
0.1
100
Hz (Min)
kHz (Max)
ICLK/fo
Filter Clock-to-Center-Frequency
Ratio Range (Each Biquad)
10
500
Hz/Hz(Min)
Hz/Hz(Max)
afCLK/fo
Filter Clock-to-Center-Frequency
Accuracy (Each Biquad)
±0.5
% (Max)
Ho
Passband Gain Error
±0.2
dB (Max)
Q
Filter "Q" (Each Biquad)
100
(Max)
±2
%
100
1
MHz
(Note 11)
80
dB
fCLK
Filter Clock Frequency
fCLKIN
Clock Input Frequency
(Logic Circuitry Only)
10
aQ
Q
fo x Q
Pin 60r7
Q Accuracy (Each Biquad)
0.5
Center Frequency-Q
Product
Q
Dynamic Range
(Each Biquad)
S;
S;
Q
S;
30
Clock Feedthrough
10
mVrms
VOS
Offset Voltage
(Each Biquad)
70
mV
ISBQ
Supply Current
(Each Biquad)
0.4
mA
ISSH
Supply Current (Each Input
Sample-and-Hold)
0.3
mA
Is
Total Supply Current (All
Circuit Blocks Connected)
. 10
mA
1-94
r
s:::
Output Buffer Electrical Characteristics
The following specifications apply for V+ = + 5V and VTMin to TMax; all other limits apply for TA = TJ = 25°C.
Symbol
Parameter
= -
5V unless otherwise specified. Boldface limits apply for
Q
=
Design
Limit
(Note 9)
Tested
Limit
(Note 8)
Typical
(Note 7)
Conditions
V+ - 1.0
V- +1.0
Units
(Limit)
V (Min)
V (Max)
Vo
Output Voltage Swing
SR
Slew Rate
1.0
CL
Maximum Capacitive Load
200
pF
GBW
Gain-Bandwidth Product
1.0
MHz
IS
Supply Current per Buffer
0.8
mA
RL
5k!1.
Vlp..s
Logic Input and Output Electrical Characteristics
The following specifications apply for V+ = +5V and V- = -5V unless otherwise specified. Boldface limits apply for
TMin to TMax; all other limits apply for TA = TJ = + 25°C.
Symbol
Parameter
V+
=
5V, V-
Logical "1"
Logical "0"
V+
=
10V, V
=
VIH
VIL
Logical "1"
Logical "0"
V+
=
2.5V, V
=
VIH
V,L
Logical "1"
Logical "0"
V+
=
5V, V-
=
Logical "1"
Logical "0"
V+
=
5V, V-
=
Logical "1"
Logical "0"
V+
=
10V, V-
Logical "1"
Logical "0"
V+
=
5V, V
VIH
V,L
VIH
V,L
V,H
VIL
Pin 7 CMOS
Clock Input
Voltage
(Notes 12
and 13)
Pin B TTL
Clock
Input Voltage
(Notes 12
and 13)
VIH
VIL
Typical
(Note 7)
Conditions
Logical "1"
Logical "0"
VIH
VIL
VOH
Clock Output
Logical "1"
lOUT
VOL
Clock Output
Logical "0"
lOUT
liN
Input Current
XTAL1,XTAL2
=
=
"TI
.....
I\)
=
Design
Limit
(Note 9)
Units
(Limit)
-5V
+3.0
-3.0
V (Min)
V (Max)
OV
+8.0
+2.0
V (Min)
V (Max)
+1.5
-1.5
V (Min)
V (Max)
OV
+4.0
+1.0
V (Min)
V (Max)
-5V
+2.0
+0.8
V (Min)
V (Max)
+2.0
+0.8
V (Min)
V (Max)
+2.0
+0.8
V (Min)
V (Max)
=
=
Tested
Limit
(Note 8)
-2.5V
OV
OV
-1 mA
v+ - 1.0
V (Min)
+1 mA
V- + 1.0
V (Max)
±10
p..A(Max)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Note 2: Operating Ratings indicate conditions for which the device is intended to be functional. These ratings do not guarantee specific performance limits,
however. For guaranteed specifications and tast conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions
listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 3: All voltages are measured with respect to GND unless otherwise specified.
Note 4: See AN450 "'Surface Mounting Methods and Their Effect on Product Reliability"' or the section titled "'Surface Mount"' found in any current Linear Data
Book for other methods of soldering surface mount devices.
Note 5: The maximum power dissipation must be derated at elevated temperatures and is a function of TJrnax' 0JA, and the ambient temperature, TA. The
maximum allowable power dissipation at any temperature is ~D = (TJmax - TA)/9JA or the number given in the Absolute Maximum Ratings, whichever is lower.
For guaranteed operation, TJmax ~ 125°C. The typical thermal resistance (ElJAl of the LMFI20N when board·mounted is 51°C/W. ElJA is typically 5Z'C/W for the
LMFI20J, and 86°C/W for the LMFI20V.
Note 6: Human body model, 100 pF discharged through a 1.5 kn resistor.
Note 7: Typicals are at TJ ~ 25°C and represent the most likely parametric norm.
Note 8: Tested Limits are guaranteed and 100% tested.
Note 9: Design Limits are guaranteed, but not 100% tested.
Note 10: When the input voltage (VIN) at any pin exceeds the power supplies (YIN < V- or VIN > V+), the current at that pin should be limited to 5 mAo The 20 mA
maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5 rnA to four.
Note 11: Dynamic range is defined as the ratio of the tested minimum output voltage swing to the wideband noise over a 20 kHz bandwidth.
Note 12: Each custom version of !he LMF120 will be tested at only one power supply voltage, which will be chosen to correspond to the application for which it is
intended.
Note 13: Only one clock input will be active for any given version of the LMF120. Therefore, a device wi! be tested for either TTL or CMOS clock input threshold,
whichever is appropriate.
1-95
Connection Diagrams
Dual-In-Line Package
GND- 1
\..../
16
Plastic Chip Carrier Package
-yo
~
q
~
3
2
1 20 19
+
q
L L 'i i 'i
N.C.- 2
15 -N.C.
ooT3- 3
14 rlN3
OUT3- 4
OUT2- 4
13 rN.C.
OUT2- 5
17 -N.C.
OUT1- 5
12 !-IN 2
N.C.- 6
16 -IN2
XTAL 1- 6
11 !-IN 1
OUT1- 7
15,....N.C.
XTAL2- 7
10 !-CLKOUT
N.C.- 8
Y-- 8
18 -IN3
14 i-INI
9 10 11 12 13
9 !-N.C.
1. ~ ~ ! q'.
..,....~ z
ee
-J
TL/H/l0353-2
Order Number LMF120CIJ, LMF120CMJ, LMF120CCN
See NS Package Number J16A or N16E
~
TUH/l0353-3
Order Number LMF120CCV
See NS Package Number V20A
Typical Performance Characteristics
Biquad Clock-to-Center
Frequency Ratio Deviation
vs Clock Frequency
+1
Q.3
t;
is
=>
~,..
Q.2
O~~
U
Q=10 II
r-,,~ i 0=30
0
0=30
0.1
IA"
!IOO
=1dd1
0=10
-1
g
Sl
1\
~ ~-Q.2
1\
-3
Vs=t2.5V
-CI.3 TA=25"C
Z!O
500
Vs=U.5V
TA=25CC
-4
750 1000 lZ!O 1500
0
250
CLOCK F1ItQUENCY (kHz)
vs=t5V
TA=25CC
2
0=10
0
g
Sl
=
-2
-4
-a
t;
is
250
500
750 1000 1250 1500
CLOCK FREOUEHCY(kHz)
0=10
0=30
0=1
S~-o.1
~
~ ~-Q.2
I
-CI.3
0
750 1000 1250 1500
r
zOO
500
750 1000 lZ!O 1500
Blquad Q Deviation
vs Temperature
!CLK = 320 kHz
~
Z!O
CLOCK FREOUEHCY(kHz)
1111
2 !CLK = 320 kHz
0=10
1
Q.2 0=10
S
I
0
0.1
0=100
= 2
Vs=i5V
~ -0.1
g
Sl
0
-1
Q
1:10
-6
e:,..
Biquad Clock-to-CenterFrequency Ratio Deviation
vs Temperature
Q.3
-l--l-
0=100
S
Q.2
a.OCK FREQUENCY(kHz)
Biquad Q Deviation
vs Clock Frequency
4
500
T =25CC
ls=t5V
Q.3
t;
is
§Ioo
-2
U-o.l
0
Blquad Clock-ta-Center
Frequency Ratio Deviation
vs Clock Frequency
Biquad Q Deviation
vs Clock Frequency
~ ~-Q.2
-2
-CI.3
-3
II I
II I
VS=t5V
rNJl'
Vs~iI2.~
I
I
I
-55 -35-15 5 25 45 65 85 105 125
-55 -35-15 5 25 45 65 85 105 125
AMBIENT TEMPERATURE (CC)
AMBIENT TEMPERATURE (CC)
TUH/l0353-4
1·96
.3:
Pin Description
"T1
......
GND (Pin 1)
This is the analog ground reference for the
LMFI20. In split supply applications, GND
should be connected to the system
ground. When operating the LMF120 from
a single positive power supply voltage, pin
1 should be connected to a "clean" reference voltage midway between V+ and
N.C. (Pins 2, 9,
13,& 15)
These pins are not connected to the internal circuitry.
OUT3 (Pin 3),
OUT2 (Pin 4),
OUTI (Pin 5)
These are the outputs of the buffer amplifiers. Depending on the filter configuration,
one, two, or all three of these outputs may
be used.
XTAL 1 (Pin 6)
This is the crystal oscillator input pin.
When using the internal oscillator, the
crystal should be tied between XTAL 1 and
XTAL2. XTALI can also be used as an input for an external TTL -level clock.
Note that by proper choice of coefficients and input connections, any type of filter response (low-pass, high-pass, bandpass, notch, or all-pass) can be obtained. For example, a
notch filter can be realized by connecting the input signal to
VHP and VLP. An all-pass filter can be realized by connecting the input signal to VHP, VLP, and VBP2. Coefficients are
controlled by the metal mask, which determines the values
of the internal capacitors and the interconnections between
the filter stages, sample-holds, and output buffers. By appropriate design of the metal mask, the biquad sections can
be cascaded to form high-order filters.
V-.
XTAL2 Pin 7)
This is the output of the internal crystal oscillator. When using the internal oscillator,
the crystal should be tied between XTAL1
and XT AL2. XTAL2 can also be used as
an input for an external CMOS logic-compatible clock swinging from V+ to V-.
V- (PinS)
This is the negative power supply pin. It
should be bypassed with at least a 0.1 ,..,F
ceramic capacitor. For single-supply operation, connect this pin to system ground.
CLOCK OUT
(Pin 10)
This is the clock output pin. It can drive the
clock inputs of additional filters or other
components. The clock output signal
swings from V+ to V-. This pin can be
mask-programmed to supply an output at
the same frequency as the internal oscillator or external clock input, or at any output
frequency available from the internal divider chain.
C)L2
TL/h,10353-5
FIGURE 1. Single Biquad Structure. There are six
of these second-order blocks within the LMFI20.
Any of the biquad blocks can realize a low-pass,
high-pass, bandpass, notch, or all-pass response.
The LMF120 contains three input sample-and-hold circuits.
These are used only when necessary-in a notch filter, for
example, where a sampled signal is summed with a continuous signal within the biquad. The result of such a summation
would contain a residual signal equal to the difference between the sampled waveform and its continuous version.
This residual would place a limit on the notch filter's effectiveness. The sample-and-hold ensures that the "continuous" signal path in the biquad (from VHP to VOUT) carries a
sampled signal, thus improving the notch's performance.
This is the positive power supply pin. It
should be bypassed with at least a 0.1 J.LF
ceramic capacitor.
Functional Description
Each of the six internal biquad switched-capacitor filter sections (shown in detail in Figure 1 ) can have a characteristic
equation of the form:
V
OUT
(s) - S2VHP - VBP2 b 1s + VLpbO
s2 + a1 s + ao
o
The center or cutoff frequency is proportional to the filter
clock frequency. The ratio of the clock frequency to the center frequency (fCLK:fO) is programmable with virtually infinite
resolution over a range of 10:1 to 500:1, although clock-tocenter-frequency ratios in the 50:1 to 100:1 range usually
give the best performance.
INPUTI (Pin 11),These are the inputs to the filter. When
INPUT2 (Pin 12), necessary (in notch filters, for example),
INPUT3 (Pin 14) the input pins are connected to the internal sample-hold circuits.
V+ (Pin 16)
N
In addition to three input pins, the LMF120 has three output
buffer amplifiers, allowing one package to contain up to
three independent filters. The total number of poles can be
any number up to twelve, so, for example, a single LMF120
could perform the function of a 6th-order low-pass, a 2ndorder bandpass, and a 4th-order high-pass filter simultaneously.
(1)
or:
(2)
1-97
II
or--------------------------------------------------------------r
~
Functional Description
(Continued)
SAMPLED·DATA SYSTEM CONSIDERATIONS
!irE
...I
Output Steps
Because the LMF120 uses switched-capacitor techniques,
its performance differs in several ways from non-sampled
(continuous) circuits. The analog signal at any input is sampled during each filter clock cycle, and since the output voltage can change only once every clock cycle, the result is a
discontinuous output signal. The output signal takes the
form of a series of voltage "steps", as shown in Figure 2.
The steps are smaller when the ratio of clock frequency to
signal frequency is larger.
Clock Circuitry
The LMF120's clock input circuitry can be mask-programmed to accept an external TTL or CMOS-level clock, or
to serve as a self-contained oscillator with the addition of an
external crystal and two capacitors (see Figure 6). The
clock signal can directly drive the biquad sections (if the
frequency is appropriate), or its frequency can be divided by
2n, where n is an integer between 1 and 8 ( + 2, + 4, + 8, . . .
+ 256). If necessary, each biquad section can obtain its
clock signal from a different divider tap.
The Clock Output pin can be programmed to supply additional LMF120s or other circuits with a clock signal whose
frequency is equal to either the clock input frequency, or the
frequency at any of the divider taps.
Aliasing
Another important characteristic of sampled-data systems is
their effect on signals at frequencies greater than one-half
the sampling frequency, fs. (The LMF120's sampling frequency is the same as the filter clock frequency). If a signal
with a frequency greater than one-half the sampling frequency is applied to the input of a sampled-data system, it
will be "reflected" to a frequency less than one-half the
sampling frequency. Thus, an input signal whose frequency
is f8/ 2 + 10Hz will cause the system to respond as though
the input frequency was 18/ 2 - 10Hz. This phenomenon is
known as "aliasing". Aliasing can be reduced or eliminated
by limiting the input signal spectrum to less than f8/2. In
some cases, it may be necessary to use a bandwidth-limiting filter (often a simple passive RC low-pass) between the
signal source and the switched-capacitor filter's input.
Power Consumption
Because the LMF120 is a CMOS integrated circuit, its power consumption is low. To further reduce power consumption, any unused sample-and-holds and buffer amplifiers are
shut down when fewer than three filters are required. (For
example, a single 12th-order notch filter would need only
one sample-and-hold and one buffer.) Unused biquad sections (if any) are shut down as well. For low-frequency applications, the internal current drain can be reduced by about
30% for further power savings.
Applications Information
Clock Frequency Limitations
Power Supplies
The performance characteristics of a switched-capacitor filter depend on the switching (clock) frequency. At very low
clock frequencies (below 10Hz), the time between clock
cycles is relatively long, and small paraSitic leakage currents
cause the internal capacitors to discharge sufficiently to affect the filter's offset voltage and gain. This effect becomes
more pronounced at elevated operating temperatures.
The LMF120 can operate from supply voltages (V+ - V-)
ranging from 4.0V up to 14V, but the choice of supply voltage can affect circuit performance. The IC depends on MaS
switches for its operation. All such switches have inherent
"ON" resistances, which can cause small delays in charging internal capaCitances. IncreaSing the supply voltage reduces this "ON" resistance, which improves the accuracy of
the filter in high-frequency applications. The maximum practical center frequency improves by roughly 10% to 20%
when the supply voltage increases from 5V to 10V.
At higher clock frequencies, performance deviations are primarily due to the reduced time available for the internal operational amplifiers to settle. For this reason, when the filter
clock is externally generated (clock divider unused), the
clock waveform'S duty cycle should be as close to 50% as
pOSSible, especially at high clock frequencies.
Dynamic range is also affected by supply voltage. Both the
noise level and the maximum signal voltage increase as
supply voltage increases, but the maximum signal voltage
increases more rapidly with supply voltage. Thus, the dynamic range is greater with higher supply voltages. It is
therefore recommended that the supply voltage be kept
near the maximum operating voltage when dynamic range
and/or high-frequency performance are important.
Offset Voltage
SWitched-capacitor filters often have higher offset voltages
than non-sampling filters with similar topologies. This is due
to charge injection from the MaS switches into the sampling
and integrating capacitors. The LMF120 is built using National's LMCMOSTM process for linear CMOS circuits, and
has far lower input offset voltage than most other switchedcapacitor filters. Typical offset voltage for an LMF120 filter
will be in the 20 mV'to 400 mV range, with the actual value
being strongly dependent on the type of filter response being realized and the number of cascaded biquad stages
needed to achieve that particular response.
As with all switched-capacitor filters, each of the LMF120's
power supply pins should be bypassed with a minimum of
0.1 /LF located close to the chip.
100:1
Noise
Switched-capacitor filters have two kinds of noise at their
outputs. There is a random, "thermal" noise component
whose level is typically on the order of 250 /LV. The actual
value depends on the specific filter being implemented. The
other kind of noise is digital clock feedthrough. This will
have an amplitude in the vicinity of 10 mV rms. In some
applications, the clock noise frequency is so high compared
to the signal frequency that it is unimportant. In other cases,
5D:1
TUH/10353-6
FIGURE 2. SWitched·Capacltor Filter Output
Waveform. Note the sampling "steps".
1-98
rAt the maximum clock frequency of 1.5 MHz, the lowest
typical value for the effective RIN the VIN1 input is therefore
1.33 Mfi. Note that RIN increases as fClK decreases, so the
input impedance will always be greater than or equal to this
value. In addition to this "resistive" input impedance, the
input protection diodes and the package contribute a total of
about 5 pF of capacitance from the input pin to ground.
When the input pins are connected directly to a biquad section, the input impedance can be either a "pure" capaCitance to ground, or a "resistive" switched-capacitor network
with characteristics similar to these of the sample-and-hold
circuits. As Figure 1 shows, the capacitors at the inputs of
the biquads do not have fixed values. They are typically
around 1 pF to 2 pF, but can be as large as 8 pF in some
designs.
Applications Information
(Continued)
clock noise may have to be removed from the output signal
with, for example, a passive low-pass filter at the LMF120's
output.
Input Impedance
The LMF120's input pins may be connected to the sampleand-hold circuits or directly to biquad filter sections, depending on system requirements. The sample-and-hold input circuits, shown in the block diagram, are normally used only in
filter implementations that require input signals (which are
normally continuous) to be combined with sampled signals,
as in notch and high-pass designs. Sampling the input before combining it with a sampled filter output makes the
overall filter response more accurate.
During the first half of a clock cycle, the 61 switch closes,
charging CIN to the input voltage VIN. During the second
half-cycle, the 62 switch closes, and the charge on GIN is
transferred to the feedback capaCitor. At frequencies well
below the clock frequency, the input impedance approximates a resistor whose value is
5:
....
."
~
Q
Typical Applications
Third-Octave Analyzer Filter
Figure 4 is a block diagram of one version of the LMF120.
The LMF120-TPQ contains three fourth-order Chebyshev
bandpass filters. The center frequencies are spaced Yo octave apart. This circuit is intended to be used in "real time"
audio spectrum analysis applications. Figure 5 shows the
computer-simulated magnitude versus frequency curves for
the LMF120-TPQ. These curves meet ANSI specifications
for Type E, Class II, Third-Octave filters. The center frequencies of the LMF120-TPQ's three filters are located at
fClK/50, fClK/62.5, and fClK/BO, so that by using several
LMF120-TPQs with clock frequencies separated by a factor
1
RIN=---'
CINfClK
At any sample/hold input, CIN is nominally 0.5 pF. For a
worst-case calculation of effective RIN, assume CIN =
0.5 pF and fClK = 1.5 MHz. Thus,
Rin(min) = 0.75 : 10- 6 = 1.33 Mfi.
Tl/F/l0353-7
FIGURE 3. The inputs to the sample-and-hold circuits
consist of diodes, switches, and capacitors. The input
impedance has a "resistive" component that depends
on the clock frequency, and a capacitive component
from the protection diodes.
II
y+
VGND
Tl/H/l0353-8
FIGURE 4. Block Diagram of LMF120-TPQ showing internal connections. Note that the input sample-and-holds are not
used in this version of the LMF120. The clock output frequency is one-half of the clock input frequency.
1-99
Typical Applications (Continued)
30pF 111Hz 30pF
of 2n, a complex audio program can be analyzed for frequency content over a range of several octaves. To facilitate this, the CLK OUT pin of the LMF120-TPQ supplies an
output clock signal whose frequency is % that of the incoming clock frequency. Therefore, a single internal or external
clock oscillator can provide the clock reference for all of the
30 filters in a complete audio real time analyzer.
The circuit shown in Figure 6 uses the LMF120-TPQ to implement a Va-octave filter set for use in "real time" audio
program analyzers. Ten LMF120-TPQs can provide all of
the filtering for the full audio frequency range.
The upper LMF120 handles the highest octave, with center
frequencies of 20 kHz, 16 kHz, and 12.6 kHz. It also contains the 1 MHz master clock oscillator for the entire system. Its Clock Out pin provides a 500 kHz clock for the
second LMF120, which supplies 250 kHz to the third
LMF120, and so on.
..r1
~
-= 0 7-=
11
5
12
4
20 kHz BAND OUT
16kHz BAND OUT
12.5 kHz BAND OUT
10kHz BAND OUT
8 kHz BAND OUT
6.25 kHz BANO OUT
5 kHz BAND OUT
4 kHz BAND OUT
3.13 kHz BAND OUT
10
j
'Gi"
j
-10
-20
I
I
I
I I,I
-30
rn "1
2.5 kHz BAND OUT
2 kHz BAND OUT
I III
I II
1.56 kHz BAND OUT
,
I 1\ 1\
1.25 kHz BAND OUT
1 kHz BAND OUT
781 Hz BAND OUT
-40
1000
10000
FREQUENCY (Hz)
TUH/10353-9
625 Hz BAND OUT
FIGURE 5. Response curves for the three filters in the
LMF120-TPQ. The clock frequency Is 250 kHz.
If the audio input Signal were applied to all of the LMF120TPQ input pins, aliasing might occur in the lower frequency
filters due to audio components near their clock frequencies
(e.g., an input Signal component near 1.B kHz will produce
an output from one of the filters in the LMF120 that handles
the lowest octave). This problem is solved by using two
LMF60-100 6th-order Butterworth low-pass filters as antialiasing filters. One LMF60-100 is placed ahead of the three
lowest-frequency LMF120TPQs and is clocked with the
31.25 kHz clock signal. The other LMF60-100 is ahead of
the next four LMF120-TPQs and the first LMF60-100. Its
clock frequency is 500 kHz.
The internal sample-and-hold circuits are not connected to
the LMF120-TPQ's input pins; instead, the inputs are connected directly to C6 of three of the biquads (see Figure 4 ).
C6 is 1.2 pF in the LMF120-TPQ, so the input impedance at
each input of the chip handling the highest octave will be
B33 ko.. The input impedances of the filters in the next octave will be twice this, or 1.667 Mo., and so on. Each filter
will also have 5 pF of additional capacitance to ground.
500 Hz BAND OUT
391 Hz BAND OUT
. 313Hz BAND OUT
250 Hz BAND OUT
195 Hz BAND OUT
156 Hz BAND OUT
125 Hz BAND OUT
97.7 Hz BAND OUT
L_cr.:l:1i:1_ 78•1 Hz BAND OUT
62.5 Hz BAND OUT
1-......f--IClJ-+.,.... 46.8 Hz BAND OUT
12th-Order Elliptic Low-Pass
With the internal biquads connected as shown in Figure 7,
the LMF120 functions as a 12th-order elliptic low-pass filter
with 0.4 dB passband ripple. The filter's extremely rapid cutoff slope is useful in applications such as anti-aliasing filters,
where unwanted signals may exist at frequencies just above
those of the desired signals. Two curves of gain vs frequency are included-Figure 8 shows the filter's overall response, and Figure 9 shows the passband response with
much higher resolution.
r-....,.,r-L!...U--.-.-39.1 Hz BAND OUT
r-"'OO'r-L!...U-OA-31.3Hz BAND OUT
L....-:1741-1lr\3}-;-;- 24.4 Hz BAND OUT
LMF120-TPQ
TUH/l0353-10
FIGURE 6. Audio "Real-Time" analyzer filter
set using LMF120-TPQ one-third octave filters.
The LMF60s provide anti-alias filtering.
Power supplies (not shown) are ± 5V and
should be bypassed with 0.1 ,...F at each supply pin.
1-100
Typical Applications
(Continued)
'aJ(
BIQUAD 1
10= 1.001 50
IZ =5.750¥o
[ ~Q~=~6~8.5~8=~
BIQUAD 2 'a.K
10 =0.975 50
..j
DIVIDER CHAIN
t ..!..
I-:ll-
traCK IN
7 N.C.
ClK OUT
.. Q=19.195
N.C • ...:..::..I-
r:::l
~
N.C• ..1!.1-
I
12
S/H
'aJ(
BIQUAD 3
10 =0.910 50
IZ=1.447~
31
t
::;Q;;=:::8:::J.35 6=::::
C
16
'aJ(
BIQUAD 4
10 =0.784 50
IZ =1.225W-
I
V-
OSCllLATOR/
lEVEL SHIFTER
~
~ Ca.;IZ::=:2:i.0~86:':~:K~
VIN -
yo
-t
[ ::;Q;;=;;:3~.86t;;:6=~
'aJ(
-=8
~
BIQUAD 5
10 =0.569 50
GND~r-
IZ 1.136 '~~K
=
[ ::;Q;;=;1:;1.74r;:0=~
'aJ(
BIQUAD 6
10 = 0.293-:50
IZ=1.104'~
Q=0.684
TLlH/l0353-11
FIGURE 7. 12th-Order Elliptic Low-Pass Filter
50
0
'iD'
~
z
~
-so
o I--t-V~ftttt.b,-+
jj++++ttH
-100
./
I
'"
-150
100
1000
10000
1000
FREQUENCY (Hz)
10000
FREQUENCY (Hz)
TL/H/l0353-13
TL/H/l0353-12
FIGURE 8. Computer-simulated LMF120 12th-Order
Elliptic Low-Pass Response. The clock frequency for
the curve shown here is 100 kHz, and the clock-tocenter-frequency ratio Is 50:1.
FIGURE 9. Computer-simulated LMF120
12th-Order Elliptic Low-Pass Response. This
curve covers the same frequency range as
the one In Figure 8, but increased resolution
shows the passband ripple more clearly.
1-101
III
Semi-Custom Filter
Development Procedure
Note: Please contact the nearest National Semiconductor Sales Office for
information on LMFI20 seml-custom filter development costs.
As discussed earier in this data sheet, the LMF120's offset
voltage will generally be in the tens of millivolts, and will be
dependent 9n the kind of transfer function the filter is intended to realize. It is important to ensure that the application's requirements are compatible with the LMF120's offset
voltage characteristics.
Developing a new switched-capacitor filter using the
LMF120 is relatively simple. First, define the performance
requirements for the filter(s) in terms of pole and zero locations, transfer functions, or frequency/attenuation specifications, whichever is most convenient. The worksheet in the
back of this data sheet may be used for this purpose. National Semiconductor will determine whether the application's performance requirements can be met with a semicustom proprietary version of the LMFI20. If the required
filter is feasible, computer simulations of the filter's performance will be provided. If the performance is satisfactory, test
frequencies and performance limits will be chosen and the
custom metal mask will be produced and prototype devices
will be manufactured. The prototyping stage generally takes
from eight to twelve weeks. After prototypes have been
built, tested, and approved, production can begin. (See the
pre-production activity flow in Figure 10).
THE DESIGN AUTOMATION SYSTEM
National Semiconductor customizes the LMF120 to a specific application by generating a metal mask that provides
the interconnections between the internal circuit blocks and
programs them for the required characteristics. The mask is
generated using National's proprietary filter CAD software.
This software computes the optimum capaCitor values for
each of the six switched-capacitor biquad filter sections to
ensure close conformance to the target requirements. It
also optimizes the design for high signal-to-noise ratio, and
then analyzes the design, taking into account all second-order effects, such as parasitic capaCitances, switch "ON"
resistance, and the finite gain-bandwidth products of the operational amplifiers. The final design analysis is then returned for verification and approval.
Feasibility
The first step in developing a custom filter based on the
LMF120 is to determine whether an LMF120 can indeed
realize the desired filter response. To this end, it is helpful to
understand the limitations of the circuit.
Actual metal mask generation begins once the design and
the test frequencies and limits have been approved. National's· in-house CAD system is used to facilitate mask generation. The new metal mask is then used to complete the
fabrication of the final silicon. The design automation system ensures fast and accurate results on the first run.
The center or cutoff frequency (fo) of the filter is one limitation. As indicated in the table of Filter Electrical Characteristics, this can typically range from a low of 0.1 Hz to a high of
100 kHz. These numbers, however, are given as guidelines
only. The actual frequency limits will depend on the specific
characteristics of the filter being developed. For example, if
the desired filter must have a very fast attenuation slope
beyond the cutoff frequency, the maximum cutoff frequency
may be significantly less than 100 kHz. As a general rule,
filters with gentler slopes can have cutoff frequencies as
high as 100 kHz, while very fast rolloffs may be limited to
corner frequencies below 20 kHz.
The Test Procedure
When the IC is in production, its performance must be verified by automated testing. Some of the tests will be common to all versions of the LMFI20: logic levels and logic
input current for example. Other tests will be for parameters
that are specifiC to a particular metal mask. These consist of
total supply current, DC offset voltages, Signal swing, and
several frequency/gain (or attenuation) test points for each
filter. The frequencies and test limits will be tailored to the
speCific application requirements for the filter(s).
Filter Q is another parameter whose acceptable range is
strongly dependent on the desired characteristics. Higher
values of Q are more difficult to achieve with high center or
corner frequencies. A useful figure of merit is the product of
Q and Fo. If this product is less than 1 MHz and Q is less
than 100 for each biquad filter section, it should be achievable with the LMFI20.
National will provide information on the typical behavior of
the filter(s) for those parameters that are not tested or guaranteed by design, such as clock feedthrough and output
noise. This information will be returned with the prototype
parts.
Some special test reqUirements can be accommodated;
these will be evaluated on request.
Filter order is obviously an important specification. If the
desired filter response requires a 13th-order filter, it can't be
fully implemented by a single LMF120, which can provide up
to 12 poles of filtering.
1-102
r
2. Total Number of Filters:
The LMF120 may consist of one, two or three independent
filters. Specify the total number of filters for this LMF120
design.
Semi-Custom Filter Development
Procedure (Continued)
s:
....
."
N
o
3. Input Clock Frequency:
The maximum clock frequency is 4 MHz. Specify the crystal
frequency if you plan to use the internal crystal oscillator.
Two external capacitors and one crystal are required for the
crystal oscillator.
4. Filter Clock Frequency:
This is the frequency at which the filter will be clocked.
There are many factors to be considered in the choice of
this frequency. Operation at the highest possible clock frequency reduces aliasing in the signal band, and reduces the
need for pre- and/or post-filtering. However, there are certain factors that limit the maximum frequency. These include
finite gain-bandwidth of the op-amps and finite on-resistances of internal switches. On the other hand, using slow clock
frequencies enables the filter to operate at lower supply currents and to save power on applications requiring low-power
operation. The maximum clock frequency for the LMF120's
internal biquads is 1.5 MHz, so the internal clock frequency
divider must be used to reduce this frequency if the clock
frequency at the LMF120's clock input pin is greater than
1.5 MHz. Additionally, the filter clock frequency must also be
at least ten times higher (and preferably 50 to 100 times
higher) than the highest pole or zero in the filter structure.
Example: Determine the filter clock frequency for a BANDPASS filter with center at 1 kHz. The system clock (input
clock) is 3.5 MHz.
Solution: Since the input clock is higher than 1.5 MHz it
must be divided down internally. Dividing by 32 gives a filter
clock frequency of 109.38 kHz. Therefore, the clock-to-center frequency ratio is 109380/1000 = 109.38. This is close
to the 50:1 to 100:1 range of clock-to-center-frequency ratios that generally gives the best results.
5. Clock Output Frequency:
This is an optional output that may be used to supply a clock
frequency anywhere else in the application system. This
output is subject to the following constraints:
fCLKOUT = fCLKIN/2 n for n = 0, 1, ... 8. Specify N/ A if this
output is not to be used.
6. Input Clock Level:
CMOS or TTL input levels may be specified for OV-5V,
± 5V or OV -1 OV power supplies. For non-standard supplies,
only CMOS input levels may be specified.
TL/H/l0353-14
FIGURE 10. Pre-Production Activity Flow
7. Filter Descriptions:
LMF120 Filter Worksheet
Instructions
Use this space to describe the filter(s) by transfer functions,
band diagrams, pole-zero locations, or fo and Q values for
the individual biquads. Pole-zero locations or fo and Q values are preferred, but the filters may be described in any of
the ways mentioned above. Examples of appropriate band
diagrams are shown in Figures 11 and 12. fc is the cutoff
frequency of the passband and fs is the frequency that defines the beginning of the stopband. AMAX is the maximum
acceptable passband gain variation. AMIN is the minimum
acceptable stopband attenuation.
Use the following instructions for completing the attached
Filter Worksheet. Return one completed worksheet for each
LMF120 device (maximum of three filters per LMF120) to
your local National Semiconductor sales office. If you require more worksheets you may photocopy this one.
1. Supply Voltage:
Specify your system supply voltage requirements. The total
supply voltage (V+ - V-) can be anywhere from 4V to
14V. Higher voltages are advantageous when dynamic
range and maximum operating frequency are critical concerns.
1-103
•
Q
....
U.
N
r---------------------------------------------------------------------------~
LMF120 Filter Worksheet Instructions (Continued)
::::i
Test frequencies for each filter should be specified with the
following in mind:
..I
A. Test frequencies between 100 Hz and 8 kHz: Digital Signal Processing techniques are used in the test procedure.
This produces the best accuracy and allows the measurement of both amplitude and phase response at the test frequencies. The customer may choose between the following
alternatives:
1. 7 test frequencies; each frequency is a multiple of 10Hz
with a minimum difference of 10Hz.
2. 15 test frequencies; each frequency is a multiple of 10Hz
with a minimum difference of 20 Hz.
FREQUENCY
In the DSP test procedure, all of the test frequencies are
applied to the filter simultaneously. The output energy available at any given frequency will be less with 15 test frequencies than with 7 test frequencies; therefore the test will be
more accurate with 7 test frequencies than with 15 test frequencies.
TUH/l0353-15
FIGURE 11. Format of a band diagram for a low-pass
filter. The amplitude response requirements are
specified by AMAX, AMIN, fc and fs·
B. Test frequencies above 8 kHz will require a voltmeter test
method, which can measure only the amplitude response.
The only constraint on the voltmeter method is that the test
frequencies must be above 1 kHz. 7 frequencies can be
tested.
Any special requirements will be considered separately, and
may be included with the Worksheet.
8. APPLICATION INFORMATION:
Describe the application, the end product, and the most important performance characteristics for the filter in this application.
Tl/H/l0353-16
FIGURE 12. Format of a band diagram for a bandpass
filter. The filter's amplitude response requirements are
specified by AMIN. AMAX, fC1' fC2' fS1 and fS2.
1-104
r-----------------------------------------------------------------------------, r
lii:
."
LMF120 Filter Worksheet
....
Engineering Contact _ _ _ _ _ _ _ _ _ _ _ __
N
Filter #2
Phone __________________________________
FilterOrder _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Company Name ________________________
Address _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Use the space below to write the transfer function or pole!
zero locations, or plot a detailed band diagram. Use a separate page if more space is needed.
1) Supply Voltage _ _ _ _ _ _ _ _ _ _ __
2) Total Number of Filters _ _ _ _ _ _ _ _ _ __
3) Input Clock Frequency (4 MHz Maximum) _ _ __
4) Filter Clock (1.5 MHz Maximum) _ _ _ _ _ _ _ __
5) Clock Output Frequency _ _ _ _ _ _ _ _ __
6) Input Clock Logic Levels (TTL or CMOS) ______
7) Filter Descriptions:
Please use the space below to define your filter(s). Note
that the total sum of the poles or zeros for all three filters
must not exceed twelve.
Filter #2 Test Frequencies _ _ _ _ _ _ _ _ _ __
Filter #1
Filter Order _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___
Use the space below to write the transfer function or pole!
zero locations, or plot a detailed band diagram. Use a sepa·
rate page if more space is needed.
Filter #3
FilterOrder _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___
Use the space below to write the transfer function or pole!
zero locations, or plot a detailed band diagram. Use a sepa·
rate page if more space is needed.
Filter #1 Test Frequencies _ _ _ _ _ _ _ _ _ __
Filter #3 Test Frequencies _ _ _ _ _ _ _ _ _ __
8) Application Information: Please describe in detail the
application for the LMF120 filters in your system.
a) End Product: _ _ _ _ _ _ _ _ _ _ _ _ ___
b) Projected Volume per Year: _ _ _ _ _ _ _ _ __
c) List the most important performance requirements for the
filters in your application (i.e., Dynamic Range> 50 dB, etc.)
1-105
o
~National
~ Semiconductor
MF4 4th Order Switched Capacitor Butterworth
Lowpass Filter
General Description
Features
The MF4 is a versatile, easy to use, precision 4th order
Butterworth low-pass filter. Switched-capacitor techniques
eliminate external component requirements and allow a
clock-tunable cutoff frequency. The ratio of the clock frequency to the low-pass cutoff frequency is internally set to
50 to 1 (MF4-50) or 100 to 1 (MF4-100). A Schmitt trigger
clock input stage allows two clocking options, either selfclocking (via an external resistor and capacitor) for standalone applications, or for tighter cutoff frequency control an
external TTL or CMOS logic compatible clock can be applied. The maximally flat passband frequency response together with a DC gain of 1 VIV allows cascading MF4 sections together for higher order filtering.
•
•
•
•
•
•
•
•
•
Low Cost
Easy to use
B-pin mini-DIP or 14-pin wide-body S.O.
No external components
5V to 14V supply voltage
Cutoff frequency range of 0.1 Hz to 20 kHz
Cutoff frequency accuracy of ± 0.3 % typical
Cutoff frequency set by external clock
Separate TTL and CMOS/Schmitt-trigger clock inputs
Block and Connection Diagrams
Dual-In-Line Package
ALTER
OUT
ClK IN
FILTER
IN
CLKR
y+
l. Sh
AGNO
v-
ALTER
OUT
y+
FilTER
IN
TUH/5064-2
4TH ORDER
BUTTERWORTH
LOWPASS ALTER
y-
Order Number MF4CN-50
or MF4CN-100
See NS Package Number N08E
AGNO
Small-Outline
Wide-Body Package
C~u~-+--t
CLKIN
ClKR
l. Sh
TL/H/5064-1
14
FILTER IN
NC
2
13
HC
CLKR
3
12
y+
HC
4
11
NC
L.SH
5
10
AGND
HC
6
9
He
v-
7
8
FILTER OUT
TLlH/5064-25
Top View
Order Number MF4CWM-50
or MF4CWM-100
.see NS Package Number M14B
1-106
Soldering Information:
• N Package: 10 sec.
260'C
• SO Package: Vapor Phase (60 sec.)
215'C
220'C
Infrared (15 sec.)
See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" for other methods of soldering surface mount devices.
Absolute Maximum Ratings
(Notes 1.2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V+ - V-)
14V
Voltage At Any Pin
V+ + 0.2V
V- - 0.2V
Input Current at Any Pin (Note 14)
5mA
Package Input Current (Note 14)
20mA
Power Dissipation (Note 15)
500mW
Storage Temperature
150'C
ESD Susceptibility (Note 13)
800V
Operating Ratings
(Note 2)
Temperature Range
MF4CN-50. MF4CN-l00
MF4CWM-50, MF4CWM-l00
Supply Voltage (V+ - V-)
Tmin
O'C
O'C
,,;: TA
,,;: TA
,,;: TA
,,;: Tmax
,,;: 70'C
,,;: 70'C
5Vto 14V
Filter Electrical Characteristics The following specifications apply for felK ,,;: 250 kHz (see Note 5) unless
otherwise specified. Boldface limits apply for T MIN to T MAX; all other limits TA = TJ = 25'C.
MF4-50
Parameter
Conditions
Typical
(Note 10)
MF4-100
Tested
Design
Tested
Design
Typical
Limit
Limit
Limit
Limit
(Note 10)
(Note 11) (Note 12)
(Note 11) (Note 12)
Unit
V+ = +5V, V- = -5V
fe• Cutoff Frequency
Range (Note 3)
Min
Max
I
Supply Current
Maximum Clock
Feedthrough
(Peak-to-Peak)
0.1
20k
felk = 250 kHz
Filter Output
3.5
25
Ho. DC Gain
Rsource ,,;: 2 kO
felk/fe Temperature
Coefficient
at2fe
DC Offset Voltage
3.5
3.5
mA
Rl=10kO
I
0.0
±0.15
±0.15
0.0
±0.15
±0.15
49.96
±0.8%
49.96
±0.6%
99.09
±0.3%
99.09
±1.0%
99.09
±0.6%
-25.0
±30
-24.0
-24.0
+4.0
-4.5
Dynamic Range (Note 4)
-25.0
+3.5
-4.0
+3.5
-4.0
80
f = 6000Hz
-7.57
±0.27
-7.57
±0.27
f = 4500Hz
-1.44
±0.12
-1.44
±0.12
+4.0
-4.5
-24.0
-24.0
dB
mV
+3.5
-4.0
+3.5
-4.0
V
V
50
1.5
mA
mA
82
dB
dB
f = 3000Hz
-7.21
±0.2
-7.21
±0.2
f = 2250Hz
-1.39
±0.1
-1.39
±O.1
1-107
dB
ppml'C
-400
50
1.5
Source
Sink
mV
49.96
±0.3%
-200
Minimum Output Swing
2.5
25
±15
Stopband Attenuation (Min)
Additional Magnitude
Response Test Points
(Note 6)
felk = 250 kHz
3.5
Hz
Yin = OV
felk/fe. Clock to Cutoff
Frequency Ratio
Output Short Circuit
Current (Note 8)
2.5
0.1
10k
dB
III
Filter Electrical Characteristics The following specifications apply for fCLK :5: 250kHz (see Note 5) unless
otherwise specified. Boldface limits apply for TMIN to TMAX; all other limits TA = TJ = 25°C. (Continued) .
MF4-100
MF4-50
Parameter
Y+
Conditions
Tested
Typical
Limit
(Note 10)
(Note 11)
Design
Tested
Design
Typical
Limit
Limit
Limit
(Note 10)
(~~ote 12)
(Note 11) (Note 12)
Unit
= +2.5Y, Y- = -2.5Y
fc Cutoff Frequency
Range (Note 3)
I
0.1
10k
min
max
= 250 kHz
Supply Current
fclk
Maximum Clock
Feedthrough
Filter Output
(Peak-to-Peak)
Yin = OV
Ho• DC Gain
Rsource :5: 2 kO
1.5
2.25
2.25
1.5
2.25
0.1
5k
Hz
2_25
rnA
15
15
mV
0.0
±0.15
±0.15
0.0
±0.15
±0.15
fClk/fc. Clock to Cutoff
Frequency Ratio
50.07
±0.3%
50.07
±1.0%
50.07
±0_6%
99.16
±0.3%
99.16
±1.0%
99.16
±0.6%
fCLK/fc Temperature
Coefficient
±25
Stopband Attenuation (Min)
-25.0
at2fc
DC Offset Voltage
-24.0
-24.0
+1.0
-1.7
+1.0
-1.7
-150
Minimum Output Swing
Output Short Circuit
Current (Note 8)
±60
RL=10kO
+1.5
-2.2
I
Source
Sink
Dynamic Range (Note 4)
Additional Magnitude
Response Test Points
(Note 6)
(fc = 5 kHz)
Magnitude at
fclk
f
ppml"C
-25.0
-24.0
+1.0
-1.7
+1.0
-1.7
dB
mV
+1.5
-2.2
V
V
28
0.5
28
0.5
rnA
rnA
78
78
dB
= 250 kHz
= 6000 Hz
f = 4500 Hz
f
-24.0
-300
-7.57
±0.27
-7.57
±0.27
dB
-1.46
±0.12
-1.46
±0.12
dB
f = 3000 Hz
(fc = 2.5 kHz)
Magnitude
dB
= 2250 Hz
-7.21
±0.2
-7.21
±0.2
-1.39
±0.1
-1.39
±0.1
dB
Logic Input-Output Characteristics The following specifications apply for V- = OV (see Note 7) unless
otherwise specified. Boldface limits apply for TMIN to TMAX; all other limits TA = TJ = 25°C.
Parameter
Conditions
Typical
(Note 10)
Tested
Limit
(Note 11)
Design
Limit
(Note 12)
Unit
6.1
6.1
8.9
V
3.1
4.4
3.1
4.4
V
J
SCHMITT TRIGGER
VT +. Positive Going Threshold
Voltage
= 10V
Min
Max
V+
Min
Max
V+ = 5V
7.0
3.5
1-108
Logic Input-Output Characteristics The following specifications apply for Votherwise specified. Boldface limits apply for T MIN to T MAX; all other limits T A
Parameter
=
tJ
=
Typical
Conditions
=
OV (see Note 7) unless
25'C. (Continued)
(Note 10)
Tested
Design
limit
limit
(Note 11)
(Note 12)
1.3
1.3
3.8
Unit
SCHMITT TRIGGER (Continued)
V T -, Negative Going Threshold
Voltage
Min
V+
=
10V
3.0
Max
Min
V+
=
5V
1.5
Max
Hysteresis (VT + -VT -)
Min
V+
=
10V
4.0
Max
Min
V+
=
5V
2.0
Max
Minimum logical "1 " Output Voltage
10 = -10p.A
(pin 2)
V+
V+
Maximum logical "0" Output Voltage
10 = 10p.A
(pin 2)
V+
V+
Minimum Output Source Current
ClK R Shorted
(pin 2)
to Ground
V+
V+
Maximum Output Sink Current
ClK R Shorted
(pin 2)
toV+
V+
V+
3.8
V
0.6
1.9
V
2.3
7.6
V
3.8
1.2
3.8
V
0.6
1.9
2.3
7.6
1.2
=
10V
9.0
9.0
V
=
5V
4.5
4.5
V
1.0
1.0
V
0.5
0.5
V
6.0
3.0
3.0
mA
1.5
0.75
0.75
mA
= 10V
= 5V
= 10V
= 5V
= 10V
= 5V
5.0
2.5
2.5
mA
1.3
0.65
0.65
mA
TTL CLOCK INPUT, ClK R PIN (Note 9)
Maximum VIL, logical "0" Input Voltage
0.8
Minimum VIH, logical "1 " Input Voltage
2.0
V
2.0
p.A
Maximum leakage Current at ClK R Pin
L. Sh Pin at Mid-Supply
V
Note 1: Absolule Maximum Ratings indicale limils beyond which damage 10 Ihe device may occur. AC and DC electncal specifications do not apply when operating
Ihe device beyond ils specified operating conditions.
Note 2: All voltages are wilh respecllo GND.
Note 3: The cutoff frequency of the filter is defined as the frequency where the magnitude response is 3.01 dB less than the DC gain of the filter.
Note 4: For ±5V supplies Ihe dynamic range is referenced 10 2.82 Vrms (4V peak) where Ihe wideband noise over a 20 kHz bandwidlh is typically 280 fLVrms for
Ihe MF4-50 and 230 fLVrms forthe MF4·100. For ±2.5V supplies Ihe dynamic range is referenced 101.06 Vrms (1.5V peak) where Ihe wideband noise over a 20
kHz bandwidlh is typically 130 fLVrms for bolh Ihe MF4·50 and Ihe MF4-100.
Note 5: The specifications for Ihe MF4 have been given for a clock frequency (felKl of 2S0 kHz or less. Above Ihs clock frequency Ihe culoff frequency begins 10
devlale from the specified error band of ±0.6% bullhe filter still mainlains its magnilude charactenslics. See Application Hints.
Note 6: Besides checking Ihe culoff frequency (fe) and Ihe slopband attenualion al2 fe, two addilional frequencies are used 10 check Ihe magnilude response of
Ihe filler. The magniludes are referenced to a DC gain of 0.0 dB.
Note 7: For simplicity all Ihe logic levels have been referenced 10 Vand ± 2.SV supplies.
= OV (excepl for Ihe TTL inpullogic levels). The logic levels will scale accordingly for ±SV
Note 8: The short circuil source currenl is measured by forcing Ihe oulpullhal is being lesled 10 ils maximum posilive voltage swing and Ihen shorting Ihal output to
the negalive supply. The short circuil sink currenl is measured by forcing the oulpullhal is being lesled 10 ils maximum negative vollage and then shorting Ihal
output to the positive supply. These are worst case conditions.
Note 9: The MF4 is operaling wilh symmetrtcal splil supplies and L. Sh is lied to ground.
Note 10: Typicals are at 25°C and represent most likely parametric norm.
Note 11: Guaranleed 10 Nalional's Average Dulgoing Quality Level (ADOL).
Note 12: Guaranleed. bul noll00% production lesled. These Iimils are nol used 10 delermine oulgoing quality levels.
Note 13: Human body model; 100 pF discharged Ihrough a 1.5 kG resislor.
Note 14: When Ihe input voltage (VIN) at any pin exceeds the power supply rails (VIN < V- orVIN> V+) the absolute value of current at that pin should be limited
10 S mA or less. The 20 mA package input current limits the number of pins Ihal can exceed Ihe power supply boundaries with a S mA current limit 10 four.
Note 15: Thermal Resistance
8JA (Junction to Ambient) N Package ..•........ 10S"C/W.
8JA M Package ..................•.•........•. 95"C/W.
1-109
II
~
:E
Typical Performance Characteristics
Power Supply Current
vs Power Supply Voltage
4J)
-0.5
llL.0.1
f-
'fI-
f-
10
NOMINAL 0
"
3.8
3.6
100
-55
" .....
-
~os kWI~G
'" ......
II!
L.-
L.-
1.0
co:
I-
1 1
f- V±=±5V
RL=3.5 kll
~
"
c
-1.0
1.0
~
0.0 -leLK 100.04
-10
l-
f-
0.1
4.6
1111111
~2
~
OPAMP Output Voltage
Swing vs Temperature
I"'"
~EGISWlrG
~-
I"
J
1
-15
25
85
TEMPERATURE I'CI
125
TLlH/5066-3
1-122
is:
observed as the frequency of a notch at the allpass output.
(Figure 10).
Typical Performance
Characteristics (Continued)
the bandpass output of the MF5 and is equal to fo divided by
the - 3dS bandwidth of the 2nd order bandpass filter (Figure 1). The value of Q determines the shape of the 2nd
order filter responses as shown in Figure 6.
VJ=-~5J
6.0
,....
'[.
j
5.2
leU( =250 kHz
Qz: the quality factor of the second order complex zero pair,
if any. Qz is related to the allpass characteristic, which is
written:
Hf!'oo.dI"'40i0d- 100:1 f-f-I-
i:l 4.8 1-1~
iil
50:~i-""Iod-"'-""'od---1---1
.....
10....
HOAP ( s2 - s;o
..........1"...
I"'"
4.4
CI'I
Q: "quality factor" of the 2nd order filter. Q is measured at
Supply Current vs Temperature
56....
."
s2
4.0 L-L.......J'-l.---L.....I..--L....L...L..J
-55 -15
25
85
125
TEMPERATURE ('C)
+ (J)02 )
z
HAP(S) =
+ s(J)o + (J)02
Q
where Qz = Q for an all-pass response.
HOBP: the gain (in VIV) of the bandpass output at f = f o.
HOlP: the gain (in V IV) of the lowpass output as f --+ 0 Hz
(Figure 2).
TL/H/S066-4
1.0 Definitions of Terms
HOHP: the gain (in VIV) of the highpass output as
f --+ fclk/2 (FigureS).
HON: the gain (in V IV) of the notch output as f --+ 0 Hz and
as f --+ fclk/2, when the notch filter has equal gain above
and below the center frequency (Figure 4). When the low-
felK: the frequency of the external clock signal applied to
pin B.
f o: center frequency of the second order function complex
pole pair. fo is measured at the bandpass output of the MF5,
and is the frequency of maximum bandpass gain. (Figure 1).
frequency gain differs from the high-frequency gain, as in
modes 2 and 3a (Figures 11 and 8), the two quantities below are used in place of HON.
fnotch: the frequency of minimum (ideally zero) gain at the
notch output.
fz: the center frequency of the second order complex zero
HON1: the gain (in VIV) of the notch output as f --+ 0 Hz.
pair, if any. If fz is different from fo and if Qz is high, it can be
HON2: the gain (in VIV) of the notch output as f --+ fClk/2.
HBP(S) =
_....:H"'O"'B~P.'--_
82 + S(l)o + Ctlo2
Q
>"
HOBP I----~JI"
,'-.
e 0.707 HoBP 1---/1~+~l\
~
../,
IL I, IH
(a)
I (LOG SCALE)
(b)
TUH/S066-S
It. 10 IH
I (LOG SCALE)
•
TL/H/S066-6
FIGURE 1. 2nd-Order Bandpass Response
~O~
f'.....
~-90
-180
(a)
Ip I,
I (LOG SCALE)
(b)
TL/H/S066-7
10
I (LOG SCALE)
TLlH/S066-8
FIGURE 2. 2nd-Order Low-Pass Response
>"
H~~~ I===;~~--
i,m"'t;1
::J-90
f
l-/l
-lBO 1--_ _.....1-_ __
&-_~~---~
(a)
I,
Ip
I (LOG SCALE)
10
TLlH/S066-9
(b)
I (LOG SCALE)
FIGURE 3. 2nd.order High-Pass Response
1-123
TL/H/S066-10
HOp=HOLPX 1 ~
1
I--
a
402
~
u..
:::a:
r-------------------------------------------------------------------------,
1.0 Definition of Terms (Continued)
.
HN(S) ~ HON(S2
90
;-
~
HON
;;;
;; 0.107 HON f----~r__--f-=------
s2 +
45
Q
0>02}
+ 0102
Q~_'o_; 10~M
~0.-45
~
+
Srdo
IH - IL
I---~
-90
~__~~~____•
IL 10 IN
IL 10 IH
I (LOG SCALE)
IL~ (;~ +~ (2bJ" + 1)
IH ~ 1 (2b + ~ (2b)' + 1)
10
0
I (LOG SCALE)
TLlH/5066-11
TL/H/S066-12
(a)
(b)
FIGURE 4. 2nd-Order Notch Response
:> HAl'
~
I----'"'T"---
...~~-180
z
~
-3.60
1:::::==±==::
10
10
I (LOG SCALE)
I (LOG SCALE)
TL/H/5066-14
TL/H/5066-13
(b)
(a)
FIGURE 5. 2nd-Order All-Pass Response
(a) Bandpass
20
20
10
10
(b) Low-Pass
'"
;; -10
~
-20
".
~
l'o.
......
lI'-,
'
......
O-~
~ {!'o
-3~
yo
~r-~
-40 t5
0.1
~=0.707-
'"~
~ ~ .,
"- .....
z -10
~
-20
0
o.s'""'"
1- 0 0.2
~~
10
~
"- I '
"-,
~
0.1
0.2
0.5 1.0 2.0
FREOUENCY (Hz)
(d) Notch
5.0
~O
"'
,. -'/II""
0.707
-10
K
1 IL
-20
I~
-30
I'IIIto.
-40
0.5 1
2
FREOUENCY (Hz)
!z
~
-30
=±O~~ ..... 0-10_ t.l.
=±.O-~-,
0-1
:::'!!
10
J..~9-!r
~0=1
0-1
~
."
20 (c) Hlgh·Pass
-- 1 -0 - 1OJ pO=5T
~
-40
U
"
0.1 0.2
10
'0-~.5_
bO=Y· L
0.5 1.0
2
5
10
FREOUENCY (Hz)
(e) All-Pass
10 f--+--r--+--r--t-~
-60
0-5
"-
6" -120
~
'"
."
;; -10 I-+--+~
~
-20
~
...... 0-0.2
......
-180
~
0. -240
I-+--+--D---'t-<
\~.
1
'-IX
-300
-40
L -............._
1.0 0.2 0.5
........- - L . _........- - '
0.1
2
-360
10
0.1 0.2
FREOUENCY (Hz)
0.5
1
10
FREOUENCY (Hz)
TUH/S066-15
FIGURE 6. Responses of various 2nd-order filters
as a function of Q. Gains and center frequencies
are normalized to unity.
1-124
iii:
."
2.0 Modes of Operation
CJ1
The MF5 is a switched capacitor (sampled data) filter. To
fully describe its transfer functions, a time domain approach
is appropriate. Since this is cumbersome, and since the
MF5 closely approximates continuous filters, the following
discussion is based on the well known frequency domain.
Each MF5 can produce a full 2nd order function. See Table
1 for a summary of the characteristics of the various modes.
a
BW
=~=R3
BW
R2
= the -3 dB bandwidth of the bandpass output.
Circuit dynamics:
Hosp
HOlP = aorHosp = HOlP
MODE 1: Notch 1, Bandpass, Lowpass Outputs:
fo
HOlP(peak) "" a
fnotch = fo (See Figure 7)
= center frequency of the complex pole pair
x HOlP (for high a's)
MODE 1a: Non-Inverting BP, LP (See Figure 8)
= fClK or fClK
100
50
a
fnotch = center frequency of the imaginary zero pair = fo.
R2
HOlP = Lowpass gain (as f 0) = - R1
Hosp = Bandpass gain (at f = fo) = -
x a = HON x O.
HOlP
:~
= fClK or fClK
100
50
R3
R2
-1; HOlP(peak) '" a
R3
R2
x HOlP (for high a's)
HOSP2 = 1 (non-inverting)
= Notch output gain as f _
f -
0
}
Circuit dynamics: HOSPI = a
Note: VIN should be driven from a low impedance
= -R2
Rl
fClK/2
TL/H/S066-16
FIGURE 7. MODE 1
TUH/S066-17
FIGURE 8. MODE 1a
1-125
« 1 kG)
Ln , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,
LL.
(Continued)
:i
2.0 Modes of Operation
MODE 2: Notch 2, Bandpass, Lowpass: fnOlch-....J\I\I'tt--rl---1
~5
V+
TL/H/5066-21
FIGURE 12. MODE 4
1-127
U) , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,
II.
:&
2.0 Modes of Operation (Continued)
MODE 6a: Single Pole, HP, LP Filter (See Figure 14)
= cutoff frequency of LP or HP output
MODE 5: Numerator Complex Zeros, BP, LP
(See Figure 13)
fo
=
~1
fz
=
~1
Q
=
,/1
=
./1 -
>
+ R2 x fClKor~1 + R2 X fClK
R4
100
R4
50
R2 fClK R2 fClK
= R3 100 or R3
50
- R1 x fClKor~1 _ R1 X fClK
R4
100
R4
50
R3
+ R2/R4 X R2
HOlP
HOHP
R1/R4 X R3
R1
H0z1
-R2(R4-R1)
= gain at C.Z. output (as f--+ 0 Hz)= R1 (R4+R2)
HOz2
= gain at C.z. output ( as f --+
fC~K)
=
MODE 6b: Single Pole LP Filter (Inverting and NonInverting) (See Figure 15)
fe
-R~2
= cutoff frequency of LP outputs
'" R2 fClK or R2 fClK
R3100
R3 50
HOBP =_(=R2 + 1) x R3
R1
R2
HOlP
R3
R1
R2
R1
HOlP1 = 1 (non-inverting)
R3
HOlP2 = - R2
= _ (R2 + R1) x R4
R1
R2 + R4
R4
TLlH/5066-22
FIGURE 13. MODE 5
HP
51
LP
R1
V,N
-.Jw.......n---I
TL/H/5066-23
FIGURE 14_ MODE 6a
LP,
(NON INVI V,N
TL/H/5066-24
FIGURE 15. MODE 6b
1-128
2.0 Modes of Operation
3:
en
."
(Continued)
TABLE I. Summary of Modes. Realizable filter types (e.g.low·pass) denoted by asterisks. Unless otherwise noted,
gains of various filter outputs are inverting and adjustable by resistor ratios.
Mode
1
2
3
3a
4
S
Adjustable
felK/fo
3
No
HOlP=+1
2
No
*
3
Yes (above
fClK/SO or
fClK/100)
*
4
Yes
Universal StateVariable Filter. Best
general·purpose mode.
*
7
Yes
As above, but also
includes resistortuneable notch.
*
3
No
Gives Allpass response with HOAP = -1
and HOlP= -2.
*
4
Gives flatter allpass
response than above
if R1 = R2 = 0.02R4'
3
Single pole.
2
Single pole
LP
*
*
HOBP1=-Q
HOBP2= +1
(2)
1a
Number of
resistors
BP
*
*
*
*
*
6a
6b
HP
*
*
N
*
*
*
*
*
*
(2)
AP
*
HOlP= +1
-R3
HOlP2=Fi2
Notes
May need input buffer. Poor dynamics
forhighQ.
3.0 Applications Information
From the specifications, the filter parameters are:
fo=200 Hz, HOlP= -2, and, for Butterworth response,
Q=0.707.
The MF5 is a general-purpose second-order state variable
filter whose center frequency is proportional to the frequency of the square wave applied to the clock input (fcuO. By
connecting pin 9 to the appropriate DC voltage, the filter
center frequency fa can be made equal to either fClK/100
or felK/SO. fa can be very accurately set (within ±0.6%) by
using a crystal clock oscillator, or can be easily varied over
a wide frequency range by adjusting the clock frequency. If
desired, the fClK/fa ratio can be altered by external resistors as in Figures 9, 10, ", 13, 14, and 15. The filter Q and
gain are determined by external resistors.
All of the five second-order filter types can be built using the
MFS. These are illustrated in Figures 1 through 5 along with
their transfer functions and some related equations. Figure
6 shows the effect of Q on the shapes of these curves.
When filter orders greater than two are desired, two or more
MFSs can be cascaded. The MFS also includes an uncommitted CMOS operational amplifier for additional Signal processing applications.
In section 2.0 are several modes of operation for the MFS,
each having different characteristics. Some allow adjustment of fClK/fo, others produce different combinations of
filter types, some are inverting while others are non-inverting, etc. These characteristics are summarized in Table I. To
keep the example simple, we will use mode 1, which has
notch, bandpass, and lowpass outputs, and inverts the signal polarity. Three external resistors determine the filter's Q
and gain. From the equations accompanying Figure 7,
Q = Ra/R2 and the passband gain HOlP = - R2/R1. Since
the input signal is driving a summing junction through R1,
the input impedance will be equal to R1. Start by choosing a
value for R1. 10k is convenient and gives a reasonable input
impedance. For HOlP = - 2, we have:
R2 = -R1HOlP = 10k x 2 = 20k.
For Q = 0.707 we have:
Ra = R2Q = 20k x 0.707 = 14.14k. Use 1Sk.
For operation on ±SV supplies, V+ is connected to +SV,
V- to -SV, and AGND to ground. The power supplies
should be "clean" (regulated supplies are preferred) and
0.1 /LF bypass capacitors are recommended.
3.1 DESIGN EXAMPLE
An example will help illustrate the MFS design procedure.
For the example, we will design a 2nd order Butterworth
low-pass filter with a cutoff frequency of 200 Hz, and a passband gain of - 2. The circuit will operate from a ± SV power
supply, and the clock amplitude will be ± Sv (CMOS) levels).
1-129
If
::E
3.0 Applications Information
(Continued)
+5V
Rl
T
10k R3
15k
Ol
•
R2,20k
LSb
... _____ J
SI
INVI
BP
I
I
I
I
I
I
I
I
I
L
CLK
LP
14
Your
-5V
J1IU"L
20 kHz
±5V OR OV TO 5V
TL/H/5066-25
FIGURE 16. 2nd-Order Butterworth Low-Pass Filter of Design
Example. For feLK = 50, Connect Pin 9 to
fo
+ 5V, and
Change Clock Frequency to 10 kHz.
lOV
Rl
10k R3
15k
T o.
l
'::"
H2,20k
v+
LSh
INVI
SA
... _____ J
BP
I
I
I
I
I
I
I
I
I
L
CLK
LP
14
Your
20kHz,
OVTO 5V OR
OVTO 10V
TL/H/5066-26
FIGURE 17. Butterworth Low-Pass Circuit of Example~ but Designed (or Single-5upply Operation
1-130
s::
."
3.0 Applications Information (Continued)
U1
y+
y+
V+
y+
T
--....--. -'2
"-~-,.~ =5Y
TYPICAL VALUES:
2ksRsl00k
4.7 pFsCs470 pF
TLlH/5066-27
(a) Resistive Divider with
Deeoupling Capaeiter
TLlH/5066-28
(b) Voltage Regulator
TLlH/5066-29
(e) Operational Amplifier
with Divider
FIGURE 18. Three Ways of Generating V2+ for Single-supply Operation
For a cutoff frequency of 200 Hz, the external clock can be
either 10kHz with pin 9 connected to V+ (50:1) or 20 kHz
with pin 9 tied to AGND or V- (100:1). The voltage on the
LogiC Level Shift pin (7) determines the logic threshold for
the clock input. The threshold is approximately 2V higher
than the voltage applied to pin 7. Therefore, when pin 7 is
grounded, the clock logic threshold will be 2V, making it
compatible with 0-5 volt TTL logic levels and ± 5 volt
CMOS levels. Pin 7 should be connected to a clean, low-impedance (less than 10000) voltage source.
these limits. If the MF5 is operating on ±5 volts, for example, the outputs will clip at about 8Vp_p. The maximum input
voltage multiplied by the filter gain should therefore be less
than BVp•p.
Note that if the filter has high Q, the gain at the lowpass or
highpass outputs will be much greater than the nominal filter
gain (Figure 6). As an example, a lowpass filter with a Q of
10 will have a 20 dB peak in its amplitude response at fo. If
the nominal gain of the filter HOlP is equal to 1, the gain at
fo will be 10. The maximum input signal at fo must therefore
be less than 800 mVp•p when the circuit is operated on ± 5
volt supplies.
Also note that one output can have a reasonable small voltage on it while another is saturated. This is most likely for a
circuit such as the notch in Mode 1 (Figure 7). The notch
output will be very small at fo, so it might appear safe to
apply a large signal to the input. However, the bandpass will
have its maximum gain at fo and can clip if overdriven. If one
output clips, the performance at the other outputs will be
degraded, so avoid overdriving any filter section, even ones
whose outputs are not being directly used. Accompanying
Figures 7 through 15 are equations labeled "circuit dynamics", which relate the Q and the gains at the various outputs.
These should be consulted to determine peak circuit gains
and maximum allowable signals for a given application.
The complete circuit of the deSign example is shown for a
100:1 clock ratio in Figure 16.
3.2 SINGLE SUPPLY OPERATION
The MF5 can also operate with a single·ended power supply. Figure 17 shows the example filter with a single-ended
power supply. V+ is again connected to the positive power
supply (8 to 14 volts), and V- is connected to ground. The
AGND pin must be tied to V+ 12 for single supply operation.
This half-supply point should be very "clean", as any noise
appearing on it will be treated as an input to the filter. It can
be derived from the supply voltage with a pair of resistors
and a bypass capacitor (Figure 18a), or a low-impedance
half-supply voltage can be made using a three-terminal voltage regulator or an operational amplifier (Figures 18b and
18c). The passive resistor divider with a bypass capacitor is
sufficient for many applications, provided that the time constant is long enough to reject any power supply noise. It is
also important that the half-supply reference present a low
impedance to the clock frequency, so at very low clock frequencies the regulator or op-amp approaches may be preferable because they will require smaller capacitors to filter
the clock frequency. The main power supply voltage should
be clean (preferably regulated) and bypassed with 0.1 ftF.
3.4 OFFSET VOLTAGE
The MF5's switched capacitor integrators have a higher
equivalent input offset voltage than would be found in a
typical continuous-time active filter integrator. Figure 19
shows an equivalent circuit of the MF5 from which the output dc offsets can be calculated. Typical values for these
offsets are:
3.3 DYNAMIC CONSIDERATIONS
The maximum signal handling capability of the MF5, like
that of any active filter, is limited by the power supply voltages used. The amplifiers in the MF5 are able to swing to
within about 1 volt of the supplies, so the input signals must
be kept small enough that none of the outputs will exceed
Vos1 = opamp offset = ±5mV
Vos2 = -185mV @ 50:1
-310mV @ 100:1
VosS = +115mV@50:1
+240mV@100:1
The dc offset at the BP output is equal to the input offset of
the lowpass integrator (VosS). The offsets at the other outputs depend on the mode of operation and the resistor ratios, as described in the following expressions.
1-131
II
If
:IE
3.0 Applications Information (Continued)
Mode 2 and Mode 5
Mode 1 and Mode 4
(6 +
1
+
VOS(N)
= VOS1
VOS(BP)
= VOS3
VOS(LP)
= VOS(N) - VOS2
IIHoLPII) -
V~S3
2)
1
(R
Rp + 1 VOS1 X 1 + R2/R4
VOS(N)
1
VOS3
+ VOS2 1 + R4/R2
Modela
a.J1 +R2/R4
Rp = R111R211R4
Vos(N.lNV.BP) = ( 1
1)
+Q
VOS1
-
VOS3
Q
VOS(INV.BP)
= VOS3
Vos(LP)
= Vos(N.lNV.BP) - VOS2
VOS(BP)
= VOS3
VOS(LP)
= VOS(N) - VOS2
Mode 3
VOS(HP)
=VOS2
VOS(BP)
=VOS3
VOS(LP)
= _
R4 (R2 VOS3 + VOS2) +
R2 R3
- -R4 ( 1 + -R2) VOS1; Rp = R111R311R4
R2
Rp
TL/H/5066-30
FIGURE 19. Block Diagram Showing MF5
Offset Voltage Sources
5V SUPPLY
R
1M
R4
YIN )-'W.....-t
R3
TL/H/S066-31
FIGURE 20. Method for Trimming VOS,
See Text, Section 3.4
1-132
3.0 Applications Information
(Continued)
ing", and can be reduced or eliminated by limiting the input
signal spectrum to less than f s /2. This may in some cases
require the use of a bandwidth-limiting filter ahead of the
MF5 to limit the input spectrum. However, since the clock
frequency is much higher than the center frequency, this will
often not be necessary.
For most applications, the outputs are AC coupled and DC
offsets are not bothersome unless large signals are applied
to the filter input. However, larger offset voltages will cause
clipping to occur at lower ac signal levels, and clipping at
any of the outputs will cause gain nonlinearities and will
change fo and Q. When operating in Mode 3, offsets can
become excessively large if R2 and R4 are used to make
fCLKlfo significantly higher than the nominal value, especially if Q is also high. An extreme example is a bandpass filter
having unity gain, a Q of 20, and fCLKlfo = 250 with pin 9
tied to V- (100:1 nominal). R4/R2 will therefore be equal to
6.25 and the offset voltage at the lowpass output will be
about + 1.9V. Where necessary, the offset voltage can be
adjusted by using the circuit of Figure 20. This allows adjustment of Vosl, which will have varying effects on the different
outputs as described in the above equations. Some outputs
cannot be adjusted this way in some modes, however
(VOS(BP) in modes 1a and 3, for example).
Another characteristic of sampled-data circuits is that the
output signal changes amplitude once every sampling period, resulting in "steps" in the output voltage which occur at
the clock rate. (Figure 21) If necessary, these can be
"smoothed" with a simple R-C low-pass filter at the MF5
output.
The ratio of fCLK to fe (normally either 50:1 or 100:1) will
also affect performance. A ratio of 100:1 will reduce any
aliasing problems and is usually recommended for wideband input Signals. In noise sensitive applications, however,
a ratio of 50: 1 may be better as it will result in 3 dB lower
output noise. The 50:1 ratio also results in lower DC offset
voltages, as discussed in 3.4.
3.5 SAMPLED DATA SYSTEM CONSIDERATIONS
The accuracy of the fCLKlfo ratio is dependent on the value
of Q. This is illustrated in the curves under the heading
"Typical Performance Characteristics". As Q is changed,
the true value of the ratio changes as well. Unless the Q is
low, the error in fCLKlfo will be small. If the error is too large
for a specific application, use a mode that allows adjustment
of the ratio with external resistors.
The MF5 is a sampled data filter, and as such, differs in
many ways from conventional continuous-time filters. An important characteristic of sampled-data systems is their effect on signals at Ii ,.quencies greater than one-half the
sampling frequency. (The MF5's sampling frequency is the
same as its clock frequency). If a signal with a frequency
greater than one-half the sampling frequency is applied to
the input of a sampled data system, it will be "reflected" to
a frequency less than one-half the sampling frequency.
Thus, an input signal whose frequency is fs/2 + 100 Hz will
cause the system to respond as though the input frequency
was fs/2 - 100 Hz. This phenomenon is known as "alias-
It should also be noted that the product of Q and fo should
be limited to 300 kHz when fo < 5 kHz, and to 200 kHz for
fo > 5 kHz.
100:1
50:1
TLiH/5066-32
FIGURE 21. The Sampled-Data Output Waveform
1-133
~National
~ Semiconductor
MF6 6th Order Switched Capacitor
Butterworth Lowpass Filter
General Description
Features
The MF6 is a versatile easy to use, precision 6th order Butterworth lowpass active filter. Switched capacitor techniques eliminate external component requirements and alIowa clock tunable cutoff frequency. The ratio of the clock
frequency to the lowpass cutoff frequency is internally set to
50 to 1 (MF6-50) or 100 to 1 (MF6-100). A Schmitt trigger
clock input stage allows two clocking options, either selfclocking (via an external resistor and capacitor) for standalone applications, or an external TTL or CMOS logic compatible clock can be used for tighter cutoff frequency control. The maximally flat passband frequency response together with a DC gain of 1 V IV allows cascading MF6 sections for higher order filtering. In addition to the filter, two
independent CMOS op amps are included on the die and
are useful for any general signal conditioning applications.
•
•
•
•
•
•
•
No external components
14-pin DIP or 14-pin wide-body S.O. package
Cutoff frequency accuracy of ±0.3% typical
Cutoff frequency range of 0.1 Hz to 20 kHz
Two uncommitted op amps available
5V to 14V total supply voltage
Cutoff frequency set by external or internal clock
Block and Connection Diagrams
fiLTER
OUT
All Packages
INVI
N.INY!
14
INVI
FILTER
La.
OUT
CUlR
Yt1
ABIIO
INYZ
Vuz
V-
AlND
CLK
IN
V·
FILTER
Vol ADJ
IN
INY!
TL/H/5065-2
Top View
N.lNn
L.III
y.
yTL/H/5065-1
Order Number MF6CWM-50
or MF6CWM-100
See NS Package Number M14B
Order Number MF6CN-50
or MF6CN-100
See NS Package Number N14A
Order Number MF6CJ-50
or MF6CJ-100
See NS Package Number J 14A
1-134
Absolute Maximum Ratings
(Note 11)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
See AN-4S0 "Surface Mounting Methods and Their Effect
on Product Reliability" (Appendix D) for other methods of
soldering surface mount devices.
14V
Voltage at Any Pin
Operating Ratings
V- - 0.2V. V+ + 0.2V
Input Current at Any Pin (Note 13)
SmA
Package Input Current (Note 13)
20mA
Power Dissipation (Note 14)
-40·C
MF6CJ-SO. MF6CJ-l00
:0:;
SupplyVoltage(Vs = V+-V-)
800V
:0:;
+70·C
TA:O:; +8S·C
SV to 14V
260·C
300·C
21S·C
220·C
Filter Electrical Characteristics The following specifications apply for felK
otherwise specified. Boldface limits apply for T MIN to T MAX; all other limits T A = TJ ,;, 2S·C.
MF6CWM-50, MF6CWM-l00,
MF6CN-50, MF6CN-l00
Parameter
O·C:o:; TA
MF6CWM-SO. MF6CWM-l00
-6S·C to + 150·C
ESD Susceptibility (Note 12)
Soldering Information
N Package (10 sec.)
J Package (10 sec.)
SO Package
Vapor Phase (60 sec.)
Infrared (IS sec.)
TMIN :0:; TA:O:; TMAX
O·C:o:; TA :0:; +70·C
MF6CN-SO. MF6CN-l00
SOOmW
Storage Temperature
(Note 11)
Temperature Range
Conditions
Typical
(Note 8)
Tested
Limit
(Note 9)
Design
Limit
(Note 10)
:0:;
2S0 kHz (see Note 3) unless
MF6CJ-50, MF6CJ-l00
Typicai
(Note 8)
Tested
Limit
(Note 9)
DesIgn
Limit
(Note 10)
Units
V+ = +5V, V- = -5V
Ie. Cutoff
Frequency
Range
(Note 1)
MF6-S0
MF6-100
Min
Max
Min
Max
Total Supply Current
Maximum Clock
Feedthrough
ICLK = 2S0 kHz
Filter Output
OpAmp lOut
OpAmp 2 Out
He.
DC Gain
MF6-50
MF6-100
DC
Offset Voltage
MF6-50
MF6-100
Minimum Output
Voltage Swing
Dynamic Range
(Note 2)
Additional
Magnitude
Response Test
Points (Note 4)
4.0
6.0
8.5
30
2S
20
Rseurce
:0:; 2k!l
fCLK/le.
Clock to Cutoff
Frequency Ratio
Maximum Output
Short Circuit
Current (Note 6)
0.1
20k
0.1
10k
0.0
0.1
20k
0.1
10k
4.0
8.5
±0.30
0.0
mA
mV
(peak-topeak)
30
25
20
±0.30
Hz
±0.30
dB
49.27±0.3% 49.27±1% 49.27±1% 49.27±0.3% 49.27±1%
98.97±0.3% 98.97±1% 98.97±1% 98.97±0.3% 98.97±1%
-200
-400
RL=10k!l
-200
-400
mV
+4.0
-4.1
+3.5
-3.8
+3.5
-3.5
+4.0
-4.1
+3.5
-3.5
V
Source
Sink
50
1.5
60
2.0
80
3.0
50
1.5
80
3.0
mA
MF6-50
MF6-100
83
81
83
81
dB
MF6-50 ICLK=250 kHz
1=6000 Hz
1=4500 Hz
-9.47
-0.92
-9.47±0.5 -9.47±0.65
-0.92±0.2 -0.92±0.3
-9.47
-0.92
-9.47±0.65
-0.92±0.3
dB
MF6-100 ICLK = 250 kHz
1=3000 Hz
1=2250 Hz
-9.48
-0.97
-9.48±0.5 -9.48 ± 0.65
-0.97±0.2 -0.97±0.3
-9.48
-0.97
-9.48±0.65
-0.97±0.3
dB
1-13S
Filter Electrical Characteristics (Continued) The following specifications apply for fCLK ,;; 250 kHz (see
Note 3) unless otherwise specified. Boldface limits apply for TMIN to TMAX; all other limits T A
MF6CWM·SO, MF6CWM·l00
MF6CN·SO, MF6CN·l00
Parameter
Conditions
Typical
(Note 8)
Y+
=
, Tested
Limit
(Note 9)
Design
Limit
(Note 10)
=
TJ
=
25°C.
MF6CJ·SO, MF6CJ·l00
Typical
(Note 8)
Tested
Limit
(Note 9)
Design
limit
(Note 10)
Units
+ 5Y, Y- = -SY (Continued)
Attenuation Rate
MFS-50 ICLK=250 kHz
11 =SOOO Hz
12=8000 Hz
-3S
-36
-36
dB/
'octave
MFS-100 ICLK = 250 kHz
11 =3000 Hz
12=4000 Hz
-3S
-36
-36
dB/
octave
Y+ = +2.5Y, Y- = -2.SY
Ie, Cutoff
Frequency
Range
(Note 1)
MFS-50
0.1
10k
0.1
5k
Min
Max
Min
Max
MFS·l00
Total Supply Current
ICLK = 250 kHz
Maximum Clock
Filter Output
Feedthrough
OpAmp lOut
Op Amp 2 Out
Ha.DCGain
MFS-50
MFS-l00
DC
Offset Voltage
MF6·50
MF6-100
Minimum Output
Voltage Swing
Attenuation
Rate
0.0
2.5
4.0
±0.30
±0.30
0.0
mA
mY
(peak·topeak)
20
15
10
-200
-400
Source
Sink
Dynamic Range (Note 2)
Additional
Magnitude
Response Test
Points (Note 4)
4.0
Hz
±0.30
dB
49.10±0.3% 49.10±2% 49.10±3% 49.10±0.3% 49.10±3%
98.65±0.3% 98.65±2% 98.65 ± 2.25% 98.65±0.3% 98.65 ± 2.25%
RL =10 ktl
Maximum Output
Short Circuit
Current (Note S)
4.0
20
15
10
Rsauree,;2 ktl
ICLK!le• Clock to
Cutoff Frequency
Ratio
2.5
0.1
10k
0.1
5k
-200
-400
mV
+1.5
-2.2
+1.0
-1.7
+1.0
-1.5
+1.5
-2.2
+1.0
-1.5
V
28
0.5
40
1.0
50
1.5
28
0.5
50
1.5
mA
77
77
dB
MFS·50 ICLK=250 kHz
1=6000 Hz
1=4500 Hz
-9.54
-0.9S
-9:54±0.5 -9.54±0.65
-0.9S±0.2 -0.96±0.3
-9.54
-0.96
-9.54±0.65
-0.96±0.3
dB
MF6-100 ICLK=250kHz
1=3000 Hz
1=2250 Hz
-9.S7
-1.01
-9.S7±0.5 -9.67±0.65
-1.01 ±0.2 -1.01±0.3
-9.67
-1.01
-9.67±0.65
-1.01±0.3
dB
MFS·50 ICLK = 250 kHz
11 =6000 Hz
12=8000 Hz
-36
-36
-36
dB!
octave
MF6-100 ICLK= 250 kHz
11 =3000 Hz
12=4000 Hz
-36
-36
-36
dB!
octave
1-136
Op Amp Electrical Characteristics
Boldface limits apply for TMIN to TMAX; all other limits TA = TJ = 25°C.
MFSCN-SO, MFSCN-100,
MFSCWM-SO, MFSCWM-100
Parameter
Conditions
MFSCJ-SO, MFSCJ-100
Typical
(Note 8)
Tested
Limit
(Note 9)
Design
Limit
(Note 10)
Typical
(Note 8)
Tested
Limit
(Note 9)
±8.0
±20
±20
±8.0
±20
Design
Limit
(Note 10)
Units
V+ = +SV, V- = -SV
Input Offset Voltage
Input Bias Current
CMRR (Op Amp # 2 Only)
VCM1 = 1.8V,
VCM2 = -2.2V
Output Voltage Swing
RL=10kn
mV
pA
10
10
SO
55
dB
+3.6
-4.0
+4.0
-4.5
+3.6
-4.0
V
80
6.0
54
2.0
80
6.0
mA
SO
55
+4.0
-4.5
+3.8
-4.0
Maximum Output Short Source
Sink
Circuit Current (Note 6)
54
2.0
65
4.0
Slew Rate
7.0
7.0
V/!'-s
DC Open Loop Gain
72
72
dB
Gain Bandwidth Product
1.2
1.2
MHz
V+ = +2.SV, V- = -2.SV
Input Offset Voltage
±8.0
Input Bias Current
±20
±20
10
CMRR (Op-Amp #2 Only)
VCM1 = + 0.5V,
VCM2 = -0.9V
Output Voltage Swing
RL = 10kn
±8.0
±20
mV
pA
10
60
55
+1.5
-2.2
+1.3
-1.7
Maximum Output Short Source
Circuit Current (Note 6)
Sink
24
1.0
35
2.0
Slew Rate
6.0
6.0
DC Open Loop Gain
67
67
dB
Gain Bandwidth Product
1.2
1.2
MHz
1-137
60
55
dB
+1.1
-1.7
+1.5
-2.2
+1.1
-1.7
V
50
4.0
24
1.0
50
4.0
mA
V/!'-s
Logic Input-Output Electrical Characteristics
The following specifications apply forV(see Note S) unless otherwise specified. Boldface limits apply for T MIN to T MAX; all other limits T A = T J = 2S·C.
MF6CN-50, MF6CN-100
MF6CWM-50, MF6CWM-100
Parameter
Conditions
Typical
(Note 8)
Tested
limit
(Note 9)
=
OV
MF6CJ-50, MF6CJ-100
Design
Typical
limit
(Note 8)
(Note 10)
Tested
limit
(Note 9)
Design
limit
(Note 10)
Units
TTL CLOCK INPUT, ClK R PIN (Note 7)
Maximum VIL, Logical "0"
Input Voltage
0.8
0.8
0.8
V
Minimum VIH, Logical "1"
Input Voltage
2.0
2.0
2.0
V
2.0
2.0
2.0
",A
Maximum Leakage Current
atCLKR Pin
LSh Pin at
Mid· Supply
SCHMITT TRIGGER
VT +, Positive Going
Threshold Voltage
VT-, Negative Going
Threshold Voltage
Hysteresis (VT + - VT -)
Min V+
Max
=
10V
7.0
6.1
8.9
6.1
8.9
7.0
6.1
8.9
V
Min V+
Max
=
SV
3.S
3.1
4.4
3.1
4.4
3.S
3.1
4.4
V
Min V+
Max
=
10V
3.0
1.3
3.8
1.3
3.8
3.0
1.3
3.8
V
Min V+
Max
=
SV
1.S
0.6
1.9
0.6
1.9
1.S
0.6
1.9
V
Min
Max
V+
=
10V
4.0
2.3
7.6
2.3
7.6
4.0
2.3
7.6
V
Min
Max
V+
=
SV
2.0
1.2
3.8
1.2
3.8
2.0
1.2
3.8
V
10V
SV
9.0
4.S
9.0
4.5
9.0
4.5
V
10V
SV
1.0
O.S
1.0
0.5
1.0
0.5
V
Minimum Logical "1" Output
Voltage (Pin 11)
10
=
-10]JA
V+
V+
Maximum Logical "0" Output
Voltage (Pin 11)
10
=
10",A
V+
V+
Minimum Output Source
Current (Pin 11)
CLKRTied
to Ground
V+
V+
Maximum Output Sink
Current (Pin 11)
CLKRTied
toV+
V+
V+
=
=
=
=
=
=
=
=
10V
SV
6.0
1.S
3.0
0.7S
3.0
0.75
6.0
1.S
3.0
0.75
rnA
10V
SV
s.o
2.5
0.65
2.5
0.65
S.O
1.3
2.5
0.65
rnA
1.3
Note 1: The cutoff frequency of the filter is defined as the frequency where the magnitude response is 3.01 dB less than the DC gain of the filter.
Note 2: For ±5V supplies the dynamic range is referenced to 2.82 Vrms (4V peak) where the wideband noise over a 20 kHz bandwidth is typically 200 /LVrms for
the MF6-50 and 250 /LVrms for the MF6-100. For ±2.5V supplies the dynamic range is referenced to 1.06 Vrms (I.SV peak) where the wideband noise over a 20
kHz bandwidth is typically 140 /LVrms for both the MF6-S0 and the MF6-100.
Nole 3: The specifications for the MF6 have been given for a clock frequency (fcu V+) the absolute value of current althat pin should be limited
to S rnA or less. The 20 mA package input current limits the number of pins that can exceed the power supply boundaries with a S mA current limit to four.
Nole 14: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX. 8JA, and the ambient temperature, TA. The
maximum allowable power dissipation at any temperature is Po = (TJMAX - TAJ/6JA or the number given in the Absolute Maximum Ratings, whichever is lower.
For this device, TJMAX ~ 12S'C, and the typical junction-to-ambient thermal resistance of the MF6CN when board mounted is 67"C/W. For the MF6CJ this number
decreases to 6Z'C/W. For MF6CWM, 8JA ~ 78·C/W.
1·138
Typical Performance Characteristics
Schmitt Trigger Threshold Voltage
vs Power Supply Voltage
13
V- -ov
12 T =25"C
II A
10
Crosstalk from Either Op-Amp
to Filter Output (MF6-50)
-20 r1"TTTTmr-rn;mnr"TT'--~rITm1
9
8
7
6
5
4
3 ~
b--2
Crosstalk from Filter
to Op-Amps (MF6-100)
IL
V
v
v
-40 rTTT11l1lT""1""TT71TJJr"1TT'~~,""
v
VI"
~r-
I
o
5
-90
6
7
8
9 10 II 12 13 14
V+ POWER SUPPLY VOLTAGE (V)
IK
Ill(
-20 r1"TITrmrTT11T1T11-rrr-rrM"""
L..J..J..JJjJjJL.-llJ.llllll...LUWllL.LUJWlIJ
10
lOll<
FREQUENcY (Hz)
Crosstalk from Filter
to Op-Amps (MF6-50)
OP-A~P2
100
100
Crosstalk from Either Op-Amp
to Filter Output (MF6-100)
-40 rrmmrr-rmmrr-rTT"'-r-T,.,."",
100
IK
~
700
~
600
FREQUENCY (Hz)
lOll<
100
IK
Ill(
FREQUENCY (Hz)
lOll<
VS=IOV
TA=25OC
fclk ,,250kflz
Ill(
Ill(
Equivalent Input Noise
Voltage of Op-Amps
-
-90'-'-J.J..iJJJL.L.l..WUl-..J...:;:..ulL.J..lllilll
10
IK
FREQUENCY (Hz)
lOll<
100
I
t--
IK
Ill(
lOll<
FREQUENCY (Hz)
TL/H/S06S-9
1-139
ff!
:il
Typical Performance Characteristics (Continued)
Positive Voltage Swing vs
Power Supply Voltage
5B (Op Amp Output)
5.4
5.0
Positive Voltage Swing vs
Power Supply Voltage
(Filter Output)
A=25-.;
1\=10kA
",
> fn' the signal at the output of the
filter is greatly attenuated thus only the input Signal will appear at the output of the Op-Amp. With R3 = R1 = 1.014
R2 the overall gain is 0.986 or -0.12 dB at frequencies
above the notch.
f.=2k
FREQUENCY (Hz)
TL/H/5065-24
FIGURE 8. Design Example Magnitude Response
Specification Where the Response of the Filter Design
Must Fall Within the Shaded Area of the Specification
Since the MF6's cutoff frequency fe, which corresponds to a
gain attenuation of -3.01 dB, was not specified in this example it needs to be calculated. Solving equation 2 where f
= fe as follows:
fe = fb
[
(100.1(3.01 dB) - 1)]11(2n)
(100.1 Amax _ 1)
= 1 kHz
=
[
100.301 - 1 ]1/12
100.1 _ 1
1.119kHz
where fe = fClK!50 or fClK!100.
1-147
U) , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,
u.
:e
Designing with the MF6 (Continued)
MF6
Mr6
-
-41----n!-
o-!FILTER
~r4J
FILTER
FILTER FILTER
IN
OUT
VOSADJ AGND
7
5
LSh
IN
OUT
y+
12
If"
6
CLKR
10
11
-=
y+=+5Vo---------~~--~~~------------~--_+-------J
1f"=-5Vo-------------------~---_r------------------------~~------------~
feLK
m
>-------------------....-----------------------------------'"
LOGIC LEVELS
TLlH/5065-25
FIGURE 9. Cascading Two MF6s
10
0
-10
~
~
....
Q
5
...
":2
~
Va;:....r-If"= lOY
f c1k =50kHz
1\\
-20
-30
\\~!~
\
\ 1\
-.40
-so
-m
\
1\
-70
lWO MF6s-
-Ill
II 1111
-90
1\
0.1
5
10
TL/H/5065-27
FREQUENCY (kHz)
TLlH/5065-26
FIGURE 10a. One MF6-50 vs. Two MF6-50s Cascaded
FIGURE 10b. Phase Response of
Two Cascaded MF6-50s
1-148
Designing with the MF6 (Continued)
VOSADJ
7
IAF6
1----1-(
R3
5Vs
OV
fCLK
R2
Rl
SIGNAL
INPUT
~""'_ _ _ _ _ _--I-~~~
____....J
.. NOTCH ..
FILTER OUTPUT
TUH/S06S-28
FIGURE lla. "Notch" Filter
+10
•
0
~
~
-10
""
::>
5
-20
c
Q.
""...
-30
-40
-00
10
50
100
500
lK
FREQUENCY (Hz)
TL/H/S06S-29
FIGURE 11 b. MF6·50 "Notch" Filter Amplitude Response
1·149
~
:E
Designing with the MF6 (Continued)
2.4 CHANGING CLOCK FREQUENCY
INSTANTANEOUSLY
The MF6 will respond favorably to a sudden change in clock
frequency. Distortion in the output signal occurs at the transition of the clock frequency and lasts approximately three
cutoff frequency (fd cycles. As shown in Figure 12, if the
control signal is low the MF6·50 has a 100 kHz clock making fe = 2 kHz; when this signal goes high the clock frequency changes to 50 kHz yielding 1 kHz fe.
The transient response of the MF6 seen in Figure 13 is also
dependent on the fe and thus the fClK applied to the filter.
The MF6 responds as a classical sixth order Butterworth
lowpass filter.
TLIH/5065-31
FIGURE 13. MF6-50Step Input Response, Vertical =
2VIdiv., Horizontal = 1 ms/div., fClK = 100 kHz
the input signal contains a component at a frequency higher
than half the clock frequency, as in Figure 148, that component will be "reflected" about fClK/2 into the frequency
range be/ow fClK/2 as in Figure 14b. If this component is
within the passband of the filter and of large enough amplitude it can cause problems. Therefore if frequency components in the input signal exceed fClK/2 they must be attenuated before being applied to the MF6 input. The necessary
amount of attenuation will vary depending on system requirements. In critical applications the signal components
above fClK/2 will have to be attenuated at least to the filter's residual noise level. An example circuit is shown in
Figure 15 using one of the uncommitted Op-Amps available
in the MF6.
TLiH/S065-30
fiN
~
1.5 kHz (scope time base
~
2 ms/div)
FIGURE 12. MF6-50 Abrupt Clock Frequency Change
2.5 ALIASING CONSIDERATIONS
Aliasing effects have to be taken into consideration when
input signal frequencies exceed half the sampling rate. For
the MF6 this equals half the clock frequency (fClI<). When
Is
.!!.. -I
IS
2
2
Is
2
.!!.. +1
IS
2
FREQUENCY
FREQUENCY
TLlH/506S-38
TLlH/5065-37
(a) Input Signal Spectrum
(b) Output Signal Spectrum. Note that the input signal at
fs/2 + f causes an output signal to appear at fs/2 - f.
Figure 14. The phenomenon of aliasing in sampled-data systems. An input signal whose frequency is greater than onehalf the sampling frequency will cause an output to appear at a frequency lower than one-half the sampling frequency.
In the MF6, fs = fClK.
1-150
Designing with the MF6 (Continued)
VOSADJ
7
t.lF6
VOUT
FILTER 8
IN
C2
R4
R1
R2
R3
INV1
TUH/S06S-34
10
~
1
21T,JA1 A2C1C2
~
Ho
A4/Rs (Ho
~
1 when Rs and R4 are omitted and V02 is directly tied to INV2).
Design Procedure:
pick Cl
R2
~
1
2QCl'''0
lor a 2nd Order Butterworth Q
R2 ~
~
0.707
0.113
c:;;;;-
make Rl ~ A2
and
C2
~
1
(21TloAl)2Cl
Note: The parallel combination 01 R4 (il used), Al and A2 should be;, 10 kn in order not to load Op·Amp #2.
FIGURE 15. Second Order Butterworth Anti-Aliasing Filter Using Uncommitted Op-Amp #2
1-151
II
~National
~ Semiconductor
MF8 4th-Order Switched Capacitor Bandpass Filter
General Description
Features
The MF8 consists of two second-order bandpass filter
stages and an inverting operational amplifier. The two filter
stages are identical and may be used as two tracking second-order bandpass filters, or cascaded to form a single
fourth-order bandpass filter. The center frequency is controlled by an external clock for optimal accuracy, and may
be set anywhere between 0.1 Hz and 20 kHz. The ratio of
clock frequency to center frequency is programmable to
100:1 or 50:1. Two inputs are available for TTL or CMOS
clock signals. The TTL input will accept logic levels referenced to either the negative power supply pin or the ground
pin, allowing operation on single or split power supplies. The
CMOS input is a Schmitt inverter which can be made to selfoscillate using an external resistor and capacitor.
By using the uncommitted amplifier and resistors for negative feedback, any all-pole (Butterworth, Chebyshev, etc.)
filter can be formed. This requires only three resistors for a
fourth-order bandpass filter. 0 of the second-order stages
may be programmed to any of 31 different values by the five
"0 logiC" pins. The available 0 values span a range from
0.5 through 90. Overall filter bandwidth is programmed by
connecting the appropriate 0 logic pins to either V+ or V-.
Filters with order higher than four can be built by cascading
MF8s.
• Center frequency set by external clock
• 0 set by five-bit digital word
• Uncommitted inverting op amp
• 4th-order all-pole filters using only three external
resistors
• Cascadable for higher-order filters
• Bandwidth, response characteristic, and center
frequency independently programmable
• Separate TTL and CMOS clock inputs
• 18 pin 0.3" wide package
Key Specifications
• Center frequency range 0.1 Hz to 20 kHz
• 0 range 0.5 to 90
• Supply voltage range 9V to 14V (±4.5V to ±7V)
• Center frequency accuracy 1 % over full temperature
range
Typical Application & Connection Diagrams
Dual-In-Line Package
120 kJl
VOUT
30 kJl
C
30 kJl
+5V
+5V
...IUl.J
1
18
D
2
17
E
A
3
16
F1 IN
AGND
4
15
FlOUT
F21N
14
A OUT
F2 OUT
13
A IN
12
V+
11
V-
10
50/100
TTL ClK
7
CMOS ClK
8
RC
TUH/B694-2
-5V
CLOCK IN
-5V
+5V
Order Number MF8CCJ
orMF8CCN
See NS Package Number
J18Aor N18A
-5V
TUH/B694-1
Fourth-Order Butterworth Bandpass Filter
1-152
Top View
Absolute Maximum Ratings (Note 1)
See AN·450 "Surface Mounting Methods and Their Effect
on Product Reliability" for other methods of soldering sur·
face mount devices.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
SupplyVoltage(Vs = V+ - V-)
-0.3V to + 15V
Voltage at any Input (Note 2)
V- -0.3VtoV+ +0.3V
Input Current at any Input Pin (Note 2)
±1 rnA
Output Short·Circuit Current (Note 7)
±1 rnA
Power Dissipation (Note 3)
500mW
Storage Temperature
-65'C to + 150'C
Soldering Information:
10 sec.
J Package:
260'C
N Package:
10 sec.
300'C
SO Package:
Vapor Phase (60 sec.)
215'C
Infrared (15 sec.)
220'C
ESD rating is to be determined.
Operating Ratings (Note 1)
Temperature Range
TMIN ,;;; TA';;; TMAX
O'C,;;; TA ,;;; +70'C
MF8CCN
-40'C';;; TA';;; +85'C
MF8CCJ
Supply Voltage (Vs = V+ - V-)
+9Vto +14V
fClK x a Range
for 10 Hz,;;; fClK ,;;; 250 kHz
for 250 kHz';;; fClK ,;;; 1 MHz
any a
fClK x a,;: 5MHz
Filter Electrical Characteristics The following specifications apply for V+ = + 5V, V- = -5V, ClOAD =
50 pF and RLOAD = 50 kO on filter output unless otherwise specified. Boldface limits apply for TMIN to T MAX; all other limits
TA = TJ = 25'C.
MF8CCN
Parameter
(Notes 4, 5)
Symbol
Ho
a
R
Ho
a
R
Ho
a
R
Gain atfo
a
fClK/fo
Gain atfo
a
fClK/fo
Gain atfo
a
fClK/fo
Gain atfo
Conditions
fClK = 250 kHz
1QO:1
ABCDE = 11100
fClK = 250 kHz
100:1
ABCDE = 10011
fClK = 250 kHz
50:1
ABCDE = 00001
Typical
(Note 9)
Tested
Limit
(Note 10)
aR/RTH fClK/fo Deviation Vs = ±5V ±5%
from Theoretical fClK ,;;; 250 kHz
(See Table I)
a
a
fClK = 250 kHz, 50:1
ABCDE = 00110
Dynamic Range ABCDE = 11100
(Note 6)
ABCDE = 10011
ABCDE = 00001
Clock
Feedthrough
Filter and Op Amp
fClK ,;: 250 kHz
a,;: 1
a> 1
Is
Maximum Supply fClK = 250 kHz, no
Current
loads on outputs
Vos
Maximum Filter
Output Offset
Voltage
fClK = 250 kHz, a = 4
50:1
100:1
Minimum Filter
Output Swing
RLOAD = 5kO
(Note 6)
VOUT
Typical
(Note 9)
Tested
Limit
(Note 10)
6.02 ±.05 6.02 ±0.2
6.02 ±0.05 6.02 ±0.2
3.92 ±2% 3.92 ±6%
3.92 ±2%
99.2 ±0.3% 99.2 ±1%
dB
99.2 ±0.3% 99.2 ±1%
6.02 ±0.2
6.02 ±0.5
15.5 ±3% 15.5 ±8%
15.5 ±3%
15.5 ±8%
dB
99.7 ±0.3% 99.7±1%
99.7 ±0.3% 99.7 ±1%
5.85 ±0.4
5.85 ±1
5.85 ±0.4
5.85 ±1
55 ±5%
55 ±10%
55 ±5%
55 ±10%
dB
49.9 ±0.2% 49.9 ±1%
49.9 ±0.2% 49.9 ±1%
6.02 ±1.5 6.02 ±0.5
±0.3%
Design Units
Limit
(Note 11)
3.92 ±6%
6.02 ±0.2 6.02 ±0.5
Vs = ±5V ±5%
6.02 ±0.5
fClK ,;: 250 kHz
aa/aTH a Deviation from Vs = ±5V ±5%
Theoretical
±5%
fClK ,;: 250 kHz, a > 1
(See Table I)
fClK ,;: 100 kHz,
1 < a < 57
±2%
Ho
MF8CCJ
Design
Limit
(Note 11)
6.02 ±1.5 dB
±15%
±5%
±15%
±6%
±2%
±6%
±1%
±0.3%
±1%
10.6 ±2%
10.6 ±6% 10.6 ±2% 10.6 ±8%
86
80
75
86
80
75
dB
dB
dB
80
40
80
40
mV
mV
9
12
±40
±80
±120
±240
±4.1
±3.8
1·153
12
±3.8
9
13
rnA
±40
±80
±120
±240
mV
mV
±4.1
±3.6
V
II
Op Amp Electrical Characteristics The following specifications apply for V+
= +5V, V- = -5Vandno
load on the Op Amp output unless otherwise specified. Boldface limits apply for T MIN to T MAX; all other limits TA = TJ = 25'C.
MF8CCN
Symbol
Parameter
Conditions
MF8CCJ
Typical
Tested
Design Typical Tested
Design Units
Limit
Limit
Limit
Limit
(Note 9) (Note 10) (Note 11) (Note 9) (Note 10) (Note 11)
Vos
Maximum Input Offset Voltage
±B
18 '
Maximum Input Bias Current
10
±20
±B
±20
VOUT
Minimum Output Voltage Swing RLOAD = 5 kO
AVOL
Open Loop Gain
BO
BO
dB
GBW
Gain Bandwidth
Product
I.B
I.B
MHz
SR
Slew Rate
10
10
V//Ls
mV
10
±3.B
±3.5
±3.4
pA
±3.B
±3.1
Logic Input and Output Characteristics The following specifications apply for V+
V
= ,+10VandV-
= OV unless otherwise specified. Boldface limits apply for T MIN to T MAX; all other limits TA = TJ = 25'C.
MF8CCN
Symbol
VT+
Parameter
Positive Threshold
Negative Threshold
Voltage on pin B
Min Vs = V+ - V- referred
to V- = OV (Note B)
Max
0.7Vs
0.5BVs
0.7Vs
Min Vs = V+ - V-: referred
to V- = OV (Note B)
Max
0.35Vs
0.35Vs
~ Output Voltage on
Min High
10 = -10/LA
VOL'
Max Low,
10 = +10 /LA
pin 9
(Note 12)
Typical Tested Design Typical Tested Design Units
Limit
Limit
Limit
Limit
(Note 9) (Note 10 (Note 11) (Note 9) (Note 10) (Note 11)
Conditions
-
Voltage on pin B
VT-
~ Output Current on Min Source Pin 9 tied to Vpin 9
Pin 9 tied to V+
Min Sink
10L
~
VIL
liN
MF8CCJ
Input Voltage on Min High
pins: 1, 2, 3, 10,
Max Low
17, & lB (Note 12)
Input Current on pins: 1, 2,
3,7, B, 10, 17, & lB
0.7Vs
0.5BVs
V
'0.B9Vs
0.7Vs'
0.B9Vs
V
O.I1Vs
0.35Vs
O.I1Vs'
V
0.47Vs
0.35Vs
0.47Vs
V
9.0
V
9.0
9.0
1.0
1.0
6.0
3.0
5.0
2.5
6.0
1.0
V
3.0
mA
5.0
2.5
mA
7.0
9.0
7.0
9.0
V
3.0
1.0
3.0
1.0
V
10
/LA
10
10
,~ Input Voltage on
V
2.0
Min High
2.0
2,.0
V+ "" +10V, V- = OVor
V+ = +5V, V- = -5V
pin 7
0.8
V
O.B
0.8
Max Low
VIL
Note 1: Absolute Maximum Raings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: When the applied voltage at any pin falls outside the power supply voltages (VIN < V- or VIN > V+), the absolute value of current atthal'pin should be
limited to 1 rnA or less.
Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX. E>JA. and the ambient temperature, TA. The maximum
allowable power dissipation at any temperature is Po = (TJMAX - TA>/9JA or the number given in the Absolute Maximum Ratings, whichever is !o"Yer. For this
device, TJMAX
=
125'C, and the typical junction-to·ambientlhermal resistance of the MFBCCN when board mounted is 50"C/W. For the MFBCCJ, this number
increases to 65°C/W.
Note 4: The center frequency of each 2nd·order filter section is defined as Ihe frequency where the phase shift through the filter is zero.
Note 5: Q is defined as the measured center frequency dMded by the measured b~ndwidth. where the bandwidth is the difference between 'the two frequencies
where the gain is 3 dB less than the, gain measured at the center fr~uency.
Note 6: Dynamic range is defined as the ratio of the tesled minimum output swing of 2.69 Vrms (± 3.BV peak·to·peak) to the wideband noise over a 20 kHz
bandwidth, For as of 1 or less the dynamic range and output swing will degrade because Ihe gain at an internal node is 2/0. Keeping the input signal level below
1.23xQ Vrms will avoid distortion in this case.
1-154
Note 7: If it is possible for a signal output (pin 6,14, or 15) to be shorted to V+, V- or ground, add a series resistor to limit output current.
Note 8: If V- is anything other than OY then the value of Y- should be added to the values given in the table. For example for Y+ = +5Y and Y- = -5Y the
typical VT+ ~ 0.7 (10V) + (-5V) ~ +2V.
Note 9: Typicals are at 25°C and represent the most likely parametric norm.
Note 10: Tested Limits are guaranteed to National's AOQL (Average Outgoing Quality Level).
Note 11: Design Limits are guaranteed but not 100% tested. These limits are not used to calculate outgoing quality levels.
Note 12: These logic levels have been referenced to V-. The logic levels will shift accordingly for split supplies.
Pin Descriptions
Q Logic Inputs
A,B,C,D,E
(3,2,1, 18, 17):
These inputs program the Os of the two
2nd-order bandpass filter stages. Logic
"1" is V+ and logic "0" is V-.
AGND(4):
This is the analog and digital ground pin
and should be connected to the system
ground for split supply operation or biased to mid-supply for Single supply operation. For best filter performance, the
ground line should be "clean".
v+
These are the positive and negative
power supply inputs. Oecoupling the
power supply pins with 0.1 p.F or larger
capacitors is highly recommended.
(12),
V- (11):
F11N (16),
F2!N (5):
These are the inputs to the bandpass filter stages. To minimize gain error the
source impedance should be less than 2
k!1. Input signals should be referenced
to AGNO.
F10UT(15),
F20UT(6):
These are the outputs of the bandpass
filter stages.
A IN (13):
This is the inverting input to the uncommitted operational amplifier. The non-inverting input is internally connected to
AGND.
AOUT(14):
This is the output of the uncommitted
operational amplifier.
50/100 (10):
This pin sets the ratio of the clock frequency to the bandpass center frequency. Connecting this pin to V + sets the
ratio to 100:1. Connecting it to V- sets
the ratio to 50:1.
TTL CLK (7):
This is the TIL-level clock input pin.
There are two logic threshold levels, so
the MF8 can be operated on either single-ended or split supplies with the logic
input referred to either V- or AGND.
When this pin is not used (or when
CMOS logic levels are used), it should
be connected to either V+ or V-.
CMOS CLK (8):
This pin is the input to a CMOS Schmitt
inverter. Clock signals with CMOS logic
levels may be applied to this input. If the
TTL input is used this pin should be connected to V-.
RC(9):
This pin allows the MF8 to generate its
own clock signal. To do this, connect an
external resistor between the RC pin and
the CMOS Clock input, and an external
capacitor from the CMOS Clock input to
AGND. The TIL Clock input should be
connected to V- or V+. When the MF8
is driven from an external clock, the RC
pin should be left open.
1.0 Application Information
1.1 INTRODUCTION
A simplified block diagram for the MF8 is shown in Figure 1.
The analog signal path components are two identical 2ndorder bandpass filters and an operational amplifier. Each
filter has a fixed voltage gain of 2. The filters' cutoff frequency is proportional to the clock frequency, which may be applied to the chip from an external source or generated internally with the aid of an external resistor and capacitor. The
proportionality constant fCLK/fo can be set to either 50 or
100 depending on the logic level on pin 10. The "0" of the
two filters can have any of 31 values ranging from 0.5 to 90
and is set by the logic levels on pins 1, 2, 3, 17, and 18.
Table I shows the available values of 0 and the logic levels
required to obtain them. The operational amplifier's non-inverting input is internally grounded, so it may be used only
for inverting applications.
The components in the analog signal path can be interconnected in several ways, three of which are illustrated in Figures 2a, 2b and 2c. The two second-order filter sections can
be used as separate filters whose center frequencies track
very closely as in Figure 2a. Each filter section has a high
input impedance and low output impedance. The op amp
may be used for gain scaling or other inverting functions. If
sharper cutoff slopes are desired, the two filter sections
may be cascaded as in Figure 2b. Again, the op amp is
uncommitted. The circuit in Figure 2c uses both filter sections with the op amp and three resistors to build a "multiple
feedback loop" filter. This configuration offers the greatest
flexibility for fourth-order bandpass designs. Virtually any
fourth-order all pole response shape (Butterworth, Chebyshev) can be obtained with a wide range of bandwidths,
simply by proper choice of resistor values and O. The three
connection schemes in Figure 2 will be discussed in more
detail in Sections 1.4 and 1.5.
1-155
s:
"TI
CD
~
::a!
Typical Performance Characteristics
fCLKIfO Ratio vs Supply
fCLKlfo Ratio vs Clock
fCLKIfO Ratio vs Clock
Frequency-S0:1 Mode
Frequency-100:1 Mode
50
100
Q=90
Q=IS.8~
r-
fL~~DI
f47
~
f-
'"="
~
-
III
97
III
96
tS
g
'~I25krZ
VS=tsv
RL=so kll
0.15
~
.t!..-
tc
'CLK=I25,tVS=tsv
RL= 50 kll---c
'1.=50pF
J
0.10
~
"
~
I 25
50
75
100
~ -o.os-so
TEMPERATURE (OC)
Q vs Supply Voltage-
50:1 and 100:1
'~I25kHz
I-TA=25OC
I- RL=50kll
'1.=SOpF
o.s
!C
L.
1--'
CI
"~
r- V
~ -o.s /
z
Q=S7
.......-r
/'
Q~'5.8
-r"Q=4
g
IS
ii
10
'"'"
~
~
tS
t6
~
~
~
~
.......
50
TA_~
NO LOAD
30
10
"
1\
102
103 104
z
0
~
10
o
~
iii
'\..
20
2
,as
FREQUENCY (Hz)
~
Vs=tsVnL
I---RL=SOkll
'1.=SOpF-
Q:!5~
~
"
-0.2
-OA
~I5.8
I'
'\.1
-0.6
~ -o.s
\.
CI
Q=S7\
-1.0
-so
100
-25
0
25
50
75
100
Q vs Clock Frequency-
50:1 and 100:1
25 r""TTI'TTmr-T"T'T1mTTT""TT
IllmTlllllII
l rn
20 H-+tttlttt-+t+tltttt--t-I7tH1tl
!C
-5
-10
r-
-IS
f-
-20 f-
~
~
Q=4
TA=+2Sj
VS=tSV
RL=SOkll
~
:.:
~
f~Mrp~
H-+tttlttt-+++tItttt--t-IIII\-I'HtttlIIIIII
H-++ItHtI-++++ttttI--+l11ftffi11I111ftI111
SH-++ItHtI-++++ttttI--+l~1ftI
O~~~~t#~~~~
-s
r-
T~~~2SOC H++1ItII-+l-IHI1ftI
-10
-IS
ff-
Vs= tsV I-tlftttlH+lHtttI
RL=50kll+++llllI-+f-Ift~
-20 r-25
-30 f-40 r-
~
n~iir P~-+++ItItt--H-1ffittl
,'-,03"uJ.WllL,g4:-'-.J...l.J.JWJ,as":-l....LJ.WW,g6
CLOCK FREQUENCY (Hz)
Negative Power
Supply Rejection
20
!.
Vs=tSV.
10 '~250kHz
Q=IS.8
TA= 2SOC
-10
I
-20
100:1
-50
'eLK" 12S kHz
Q=4
Positive Power
Supply Rejection
§
,
'\.
40
75
'\f
CLOCK FREQUENCY (Hz)
Vs~
"-,
50
Q.2
I
Q vs Clock Frequency50:1 and 100:1
20
60
25
z
0
!!l
t7
100
90
~
0
"~
OA
IS
10
Op Amp-Open Loop
Frequency Response
2
-25
!C
D.6
TEMPERATURE (OC)
SUPPLY VOLTAGE (V)
80
70
-
~
DB
TEMPERATURE (OC)
-1.0
t4
.....
1.0
g
CI
...
!C
z
~
Q vs Temperature50:1 and 100:1
~
0
CI
~
IL
Q=I
o
~
/
o.os
t7
is
SUPPLY VOLTAGE (V)
fCLKlfo Ratio vs
Temperature-50:1 Mode
Q=57
Q=4
1:;
IIII
II
/'
V
V
CLOCK FREQUENCY (Hz)
Q=4~ ~=S::7
O,:!. I-" r-
..
~1
IIII
/'
103
Temperature-100:1 Mode
g
III
I~,O LOAD
It
fCLKlfo Ratio vs
1.0
I1
vs=tSV
T.=25OC
/'
i-'1.=50pF
IQ 2
-
98
/'
i- RL=50kll
~
99
CLOCK FREQUENCY (Hz)
~=S7
'CLK= I 2S kHz
TA=25OC
Q=IS.8tw
~
Qli~
vs=tSV
T.=2SOC
Voltage-50:1 and
100:1 Mode
2
~
.....
~ 50:1
II
II
106 107
vs=tSV.I.
10 '~250kHz
Q=IS.8
T.=25OC
-10 f-
~
-20
~
-30
iii
~
-40
-so
/
V
~
-60
102
FREQUENCY (Hz)
FREQUENCY (Hz)
TLlH/8694-24
1-156
3:
."
Typical Performance Characteristics (Continued)
Positive Swing vs
Load Resistance
Negative Swing vs
Load Resistance
Negative Swing vs
Supply Voltage
I
JJlllj
VS=i5V
T.=250(:
CII)
OP-A~P
-3
flLTJ:R
/
~
'"
~
Negative Swing vs Temperature
(Filter and Op Amp)
TA=250(:
RL=5kll
VS=t5V
RL=5kll
,/
..-oP-A~P
V
/
~
is
i7
i6
'"~
Supply Current vs
Temperature
"- \.
I\.
'\.
-2
-4
a~
e:
z
0
!'"
I"-
....
/
-1
-10
25
-50-25
TJ:~PERATUR[
so
25
75
100
V
/
so
75
100
/'
-0.05
-0.10
~
V
-50 -25
60
TA=250(: .1.
50 fcu<= 250 kHz
40
NO LOAD
30 -Q=4
1/
20
12.5
tQ
10.0
10
8
\
V"
""'"
-1
-7!J
-2
-6
It
-3
ffi
~
'"
10'
104
105
CLOCK fREQUENCY (Hz)
i7
i6
VS=i5V
fCLK= 250 kHz
f- NO LOAD
V,N=OV
r--Q=4
t:; -10.0
o
V
Filter Offset Voltage vs
Temperature-50:1 and 100:1
-4
102
100,1
is
-2
-12.5
,/
/. , /
SUPPLY VOLTAGE (V)
T.=25O(:
VS=i5V
7!J
NO LOAD
5.0 I-Q=4
2!J
0.0
-5.0
100
./
i7
Filter Offset Voltage vs Clock
Frequency-50:1 and 100:1
'"~
75
1::r50,1
10
SUPPLY VOLTAGE (V)
14
12
50
(OC)
Filter Offset Voltage
vs Supply Voltage
/
i6
25
TJ:~PERATURE
/
is
/
/
.4
t4
(0(:)
Filter Offset Voltage vs
Q-50:1 and 100:1
llil
V
,/
ill
TA=25O(:
fCLK= 250 kHz
NO LOAD
_V,N=OV
I\..
\.
-6
-8
0.05
Supply Current vs
Supply Voltage
Vs=t5v
feu<= 250 kHz
NO LOADV,N=OV -
\.
'"z
VS=t5V
RL=5kll
TJ:MPERATURE (0(:)
SUPPLY VOLTAGE (V)
8
0.10
~
/
-0.3
-50 -25
~
~
1/
V
1/
~
u
/
i7
Positive Swing vs Temperature
(Filter and Op Amp)
~
,/ ,/
t6
is
SUPPLY VOLTAGE (V)
Positive Swing vs
Supply Voltage
fILTER/:
~
i'-..
LOAD RESISTANCE (II)
,/
OP-AMP
i'......... ,
........
105
LOAO RESISTANCE (II)
~
fiLTER
-5
11111
10'
10
~
-6
T'=m
1111
-100
-4
T.=250(:
RL=5kll
OP-AMP
Vs=t5V
1111
r:z
\
FILTER
I'
t-
'"
~
~
.....
-
-so -25
1/
/
/
/
25
50
75
100
TEMPERATURE (0(:)
TL/H/8694-25
1-157
~
:E
1.0 Application Information
(Continued)
AGND
50/100
m
ClK
CMOS
ClK
TLlH/8694-3
FIGURE 1. Simplified Block Diagram of the MF8
TLlH/8694-4
FIGURE 2a. Separate Second-Order "Tracking" Filters
VOUT
TL/H/8694-5
FIGURE 2b. Fourth-Order Bandpass Made by Cascading Two Second-Order Stages
1-158
1.0 Application Information
(Continued)
R2
r---~~------------------------------~-VOUT
TL/H/8694-6
FIGURE 2c. Multiple Feedback Loop Connection
1.2 CLOCKS
Clock signals derived from a crystal-controlled oscillator are
recommended when maximum center frequency accuracy
is desired, but in less critical applications the MFa can generate its own clock signal as in Figures 3c and 4c. An external resistor and capacitor determine the oscillation frequency. Tolerance of these components and part-to-part variations in Schmitt-trigger logic thresholds limit the accuracy of
the RC clock frequency. In the self-clocked mode the TTL
Clock input should be connected to either pin 11 or pin 12.
The MFa has two clock input pins, one for CMOS logic levels and the other for TTL levels. The TTL (pin 7) input automatically adjusts its switching threshold to enable operation
on either single or split power supplies. When this input is
used, the CMOS logic input should be connected to pin
11 (V-). The CMOS Schmitt trigger input at pin a accepts
CMOS logic levels. When it is used, the TTL input should be
connected to either pin 11 (V-) or pin 12 (V+). The basic
clock hookups for single and split supply operation are
shown in Figures 3 and 4.
10
18
2
17
16
AGND
F2 IN
F2 OUT
5V
-5V
JlIL
.
-5V
15
MF8
14
13
m ClK
12
CMOS CLK
11
RC
10
10
Fl IN
18
17
A
FlOUT
AGND
A OUT
F2 IN
A IN
5VJlJL
OV
+5V
V-
-5V
MFB
50/100
A OUT
14
A IN
13
mClK
V+
12
CMOS' ClK
-5V
FlOUT
15
F2 OUT
V+
Fl IN
16
RC
TL/H/8694-8
(b) MFa Driven with TTL Logic Level Clock
C
B
A
AGND
f2 IN
f2 OUT
TTL CLK
CMOS CLK
RC
C-v
-5V
50/100
10
TLlH/8694-7
(a) MFa Driven with CMOS Logic Level Clock
-5V
+5V
v-
II
1
18
2
16
4
15
Mf8
14
13
7
12
8
II
9
10
1
fClK ~
RC
17
3
5
D
fl IN
Typically for Vs' ~ 10V
1
fClK ~ 1.69 RC
f1 OUT
A OUT
A IN
V+
v-
Inl (VS
- VT - )
Vs -VT+
'Vs
~
V+ - V-
+5V
-5V
50/100
TL/H/B694-9
(c) MFa Driven with Schmitt Trigger OSCillator
FIGURE 3. Dual Supply Operation
1-159
r
T+ )
VL
1
•
fe
::::is
1.0 Application Information (Continued)
pled to the filter input or biased to V+ /2. It is strongly recommended that each power supply pin be bypassed to
ground with at least a 0.1 ",F ceramic capacitor. In single
supply applications, with V- connected to ground, V+ and
AGND should be bypassed to system ground.
1.3 POWER SUPPLIES AND ANALOG GROUND
The MFa can be operated from single or dual-polarity power
supplies. For dual-supply operation, the analog ground (pin
4) should be connected to system ground. When single supplies are used, pin 4 should be biased to V+ /2 as in Figures
3 and 4. The input signal should either be capacitively cou-
18
D
17
E
3
16
Fl IN
AGND
4
15
FlOUT
14
A OUT
C
10V
10k
B
2
A
•
-%-
F2 IN
5
F2 OUT
6
13
A IN
TTL ClK
7
12
V+
CMOS ClK
8
11
V-
RC
9
10
50/100
10k
J1IIl0V
MF8
5V DC
+10V
OV
TLIH/8694-10
(a) MF8 Driven with CMOS Logic Level Clock
18
D
17
E
3
16
F1 IN
AGND
4
15
F1 OUT
F2 IN
5
14
A OUT
F2 OUT
6
13
A IN
TTL ClK
7
12
V+
CMOS ClK
8
11
V-
RC
9
10
50/100
C
10V
-V
0•1 J.LF
10k
J1II+5V
OV
B
2
A
•
MF8
+10V
TL/H/8694-11
(b) MF8 Driven with TTL Logic Clock
10V
C
18
D
17
E
3
16
F1 IN
AGND
4
15
F1 OUT
F2 IN
5
14
A OUT
13
A IN
B
2
A
•
MF8
F2 OUT
fClK
RCIN
I Cs
=vT- )
Vs VT+
Typically for Vs
= 10V
1
fClK
TTL CLK
7
12
V+
CMOS ClK
8
11
V-
10
50/100
RC
1
=
= 1.69 RC
+10V
TLIHI8694-12
(c) MF8 Driven with the Schmitt Trigger OSCillator
FIGURE 4. Single supply operation. The AGND pin must be biased to mid-supply.
The input signal should be dc biased to mid-supply or capacitor-coupled to the input pin.
1-160
r
T+ )
VT-
I
1.0 Application Information
(Continued)
1.4 MULTIPLE FEEDBACK LOOP CONFIGURATION
The multi·loop approach to building bandpass filters is high·
Iy flexible and stable, yet uses few external components.
Figure 5 shows the MFS's internal operational amplifier and
two second·order filter stages with three external resistors
in a fourth·order multiple feedback configuration. Higher·or·
der filters may be built by adding more second-order sections and feedback resistors as in Figure 6. The filter's response is determined by the clock frequency, the clock-tocenter-frequency ratio, the ratios of the feedback resistor
values, and the as of the second-order filter sections. The
design procedure for multiple feedback filters can be broken
down into a few simple steps:
HDBP
1..
AMAX
T
T. .:. .:. . . . . . .:..........::. .:. T
1 V+) the absolute value of current at that pin should be limited
to 5 rnA or less. The 20 rnA package input current limits the number of pins that can exceed the power supply boundaries with a 5 rnA current limit to four.
Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, 9JA, and the ambient temperature, TA. The maximum
= (TJMAX - TAl/6JA or the number given in the Absolute Maximum Ratings, whichever is lower. For this
device, TJMAX ~ 125°C, and the typical junction·to·ambient thermal resistance of the MFI OACN/CCN when board mounted is 55°C/W. For the MF10AJ/CCJ, this
number increases to 95°C/Wand for the MF10CCWM this number is 66°C/W.
allowable power dissipation at any temperature is PD
Note 4: The accuracy of the Q value is a function of the center frequency (fo). This is illustrated in the curves under the heading "Typical Performance
Characteristics".
Note 5: YOSt, V0S2, and VOS3 refer to the internal offsets as discussed in the Applications Information Section 3.4.
Note 6: For ±5V supplies the dynamic range is referenced to 2.82V rms (4V peak) where the wideband noise over a 20 kHz bandwidth is typically 200 ",V rms for
the MF10 wijh a 50:1 CLK ratio and 280 ",V rms for the MF10 with a 100:1 CLK ratio.
Note 7: The short circuit source current is measured by forcing the output that is being tested to its maximum positive voltage swing and then shorting that output to
the negative supply. The short circuit sink current is measured by forcing the output that is being tested to its maximum negative voltage swing and then shorting
that output to the positive supply. These are the worst case conditions.
Note 8: Typicals are at 25°C and represent most likely parametriC norm.
Note 9: Tested IimHs are guaranteed to National's AOQL (Average Outgoing Quality Level).
Note 10: Oesign limits are guaranteed but not 100% tested. These limits are not used to calculate outgoing quality levels.
Note 11: Human body model, 100 pF discharged through a 1.5 kO resistor.
1-176
;:
...."11
Typical Performance Characteristics
101.0
!
!
i
i
i
9.0
8.0
-3JI
-3,9
~
-4.D
1=
g
-4.2
~
-.u
5
z
-4.1
-4.5
5
5.0
o 4.8 1--::1o.Io1#lli!-+++ttI!F=J-HtttlJl
... 4.6
; !:~ ~~fj!~ff~i+ml
;:~ k.b,;t~4i-1.5~V~0~LT~S=iU~PP~L1iiiES~~fl-!llll
10.0
9.D
11.0
12D
13D
LOAD RESISTANCE(ll.)
Negative Output
Swing vs Temperature
Positive Output Swing
vs Temperature
Vs~ t~V
I I
I I
-Nobl I
,
(RL= 3.5 k %
,
,,
4.50
,~
-55
i
-15
~r+
1=
430
~
~
4k.O.
25
;;
ol2O
01.10
125
85
'"
-55
l!l
1.5
.
1.0
~
0.5
~
.......
0.0
k-J.-.
I......
r--.
-1.0
-55
-15
!.
<.J
-0.5
-01.5
+/-5.5 VOLT SUPPLIES
-5.0
+ -6.0 VOLT SUPPLIES
-5.5
+/-6.5 VOLT SUPPLIES
-6.0
lk
25
10k
VS=t5V
TA =25OC
MODE 1
NOMINAL =11.0
NOTC~~,(RL-3.6 kll.)
Q Deviation vs
Clock Frequency
"
85
5.5
5.0
~OD£ 1
01.5
fCLK
'10=50:1
......
0.00
-15
25
85
TEMPERATURE (OC)
Q Deviation vs
Clock Frequency
fCLKlfO Deviation
vs Temperature
!.
,
I
01.0
2D
0.0
I'.
-2.0
lDO 2DO 3DO «Xl 5DO 1m 7DO lID 9DO lDOD
,. ,
CLOCK FREQUENCY (kHz)
D.06
0.05
D.04
D.03
2.5
125
D.02
'CLK
I-, =100:110_1--1--
.. -0.03
-0.1)4
-o.os
-o.os
-om
-o.os
-15
25
TEMPERATURE(OC)
II
f~~=I,OO~'
D.06
0.D5
VS=t5V I
NOMINAL Q= 10.0
MODE 1 I
D.03 fCLK=2~0 kHz
D.04
III
D.02
.
0.01
~<.J
f~~=50:1
ODD
-2.01
-oD2
-0.03 ~
-0.1)4
-o.og
-55
9= 10.0
fCLKlfO Deviation
vs Temperature
fCLK~~~
~~
_ -om
TA=25OC
~~~~~
CLOCK FREQUENCY (kHz)
VS=t5V~+
NOMIN1~
MODE 1
0.01
V~=t'5V
2D
1.5
1.0
0.5
I'.
0.0
......
-0.5
1'.-'
-1.0
100 2DO 3DO «Xl 5DO 1m 7DO lID 9DO lDOD
-
-0.10
-55
-
~
I.......
-0.15
125
01.0
3.5
3D
fCLK =25? kHz_
TEMPERATURE(OC)
7Il.O
-V's=i5V I.
18.0
-TA=25OC
,I
16.0 -NOMINAL Q=10.0
101.0 -MODE 1
12D -'CLK
10.0 -'10=50:1
8.0
6.0
NONINA~tr
0.05
1000
CLOCK FREQUENCY (kHz)
~s=t5V~±
0.10
~
100:1
500
100
0.20
1\
\
l.I
-70
125
85
5J;!;
/
V
...,.
~
25
1M
Crosstalk vs Clock
Frequency
0.25
0.15
lOOk
LOAD RESISTANCE(ll.)
~
-0.05
/
22D
6.0
+/-5.0 VOLT SUPPLIES
Temperature
fCLK=±
fCLK
'10=100:1
,
!
III
+ -4.5 VOLT SUPPLIES
-01.0
,~
0.30
NOMI~t.E
MODE 1
\
0
-3.5
Q Deviation vs
V~=~5V
2D
5
III
-3.0
TEMPERATURE (OC)
Q Deviation vs
Temperature
2.5
,,.
-15
TEMPERATURE(OC)
3D
5
TAN~
-
-2D
-2.5
8A~DP1ss
iND ILoJp+~c-;
_
(R L=5.0kll.)
, ~
0
f-+6PASS AND
I(RL 5
.~
£
Vs~t~V- I-
"
A'I
I
~
0\.40
5
lA'"
t7. ~
£
Negative Output Voltage
Swing vs Load
Resistance (NI AP/HP Output)
-1.5
3.6'~k:.J..J.J.J.ll,!1:0k:-"..u.ll'~0':::Ok-'-J.J.J.~,M
101.0
POWER SUPPLY VOLTAGE (V)
-.c.J
-4.6
-4:l
5 5.21.
V
/
8.0
~ ~:: F;~ilfij§fj~j1rnl
V
,I
6.4 r-rnrmrrr-rrmTI:rr-i-rTTITTTI
6.2 l-t+tttttll--H-tHtttrTA= 250C
;:~
U.5 VOLT SUPPLIES
£
I
10.0
7.0
£
1/
11.0
-3:/
Positive Output Voltage Swing
vs Load Resistance
(N/AP/HP Output)
Power Supply Current
vs Power Supply Voltage
A=25OC
13D -NODE
1
_
f
o =5kHz
12D
o
85
125
-55
,
,
......
I
II
V
/
-15
25
85
125
TEN PERATURE (OC)
TL/H110399-2
1-177
C)
.,...
LL
:2
r-----------------------------------------------------------------------------------------~
Typical Performance Characteristics
felK/fo Deviation
vs Clock Frequency
o..co
Q.3O
f
I
~~=100r
o
-o.os
-0.10
-0.15
I
I
1.4 I- Vs=t5V
T.=25"C
12 I-
NO~IN:L±O~
NODE 1
Q.2O
0.15
0.10
o.os
1.6
T.=25"C
0.25
Deviation of felK
vs Nominal Q fo
felK/fo Deviation
vs Clock Frequency
VS=t5~i=h
!lJ5
(Continued)
\1
5
"
NO~IN'L Q
1.0 I- MODE 1
0.8 I- fCLK=~O:1
I
II
1/
= 10.0
0.6 I- rfo
0.4
z
!
o
-1J)
I
;1_
I
02
0
-2.0
-Q.2O
-D.25
I-
r-
-0.30
-02
100 200 300 400 500 600 700 600 900 1000
100 200 300 400 500 600 700 600 900 1000
CLOCK FREQUENCY (kHz)
-3.0
0.1
1.0
NO~INAL
CLOCK FREQUENCY (kHz)
10
100
Q
Deviation of felK
vs Nominal Q fo
z
i
di....
-0.5'1161
-I.oE
0.1
1.0
10
100
NOMINAL Q
TL/H/l0399-3
Pin Descriptions
LP(1,20), BP(2,19), The second order lowpass, bandpass
N/ AP/HP(3,18)
and notch/allpass/highpass outputs.
These outputs can typically sink 1.5 mA
and source 3 rnA. Each output typically
swings to within 1V of each supply.
INV(4,17)
The inverting input of the summing opamp of each filter. These are high impedance inputs, but the non-inverting input is internally tied to AGND, making
INVA and INVs behave like summing
junctions (low impedance, current inputs).
S1(5,16)
S1 is a signal input pin used in the allpass filter configurations (see modes 4
and 5). The pin should be driven with a
source impedance of less than 1 k!1. If
S1 is not driven with a signal it should be
tied to AGND (mid-supply).
SAlS(6)
VA + (7),Vo + (8)
This pin activates a switch that connects
one of the inputs of each filter's second
summer to either AGND (SAIS tied to
V-) or to the lowpass (LP) output (SAIS
tied to V +). This offers the flexibility
needed for configuring the filter in its
various modes of operation.
Analog positive supply and digital positive supply. These pins are internally
connected through the Ie substrate and
therefore VA + and Vo + should be derived from the same power supply
source. They have been brought out
separately so they can be bypassed by
separate capacitors, if desired. They
can be externally tied together and bypassed by a single capacitor.
VA-(14), Vo-(13) Analog and digital negative supplies.
The same comments as for VA + and
Vo + apply here.
1-178
is:
Pin Descriptions (Continued)
1.0 Definition of Terms
LSh(9)
fClK: the frequency of the external clock signal applied to
pin 10 or 11.
CLKA(10),
CLKB(11)
50/100/CL(12)
AGND(15)
Level shift pin; it accommodates various
clock levels with dual or single supply
operation. With dual ±5V supplies, the
MF10 can be driven with CMOS clock
levels (± 5V) and the LSh pin should be
tied to the system ground. If the same
supplies as above are used but only TTL
clock levels, derived from OV to + 5V
supply, are available, the LSh pin should
be tied io the system ground. For single
supply operation (OV and + 1OV) the
VA -, VD - pins should be connected to
the system ground, the AGND pin
should be biased at + 5V and the LSh
pin should also be tied to the system
ground for TTL clock levels. LSh should
be biased at + 5V for CMOS clock levels in 10V single-supply applications.
Clock inputs for each switched capacitor filter building block. They should both
be of the same level (TTL or CMOS).
The level shift (LSh) pin description discusses how to accommodate their levels. The duty cycle of the clock should
be close to 50% especially when clock
frequencies above 200 kHz are used.
This allows the maximum time for the
internal op-amps to settle, which yields
optimum filter operation.
fO: center frequency of the second order function complex
pole pair. fO is measured at the bandpass outputs of the
MF10, and is the frequency of maximum bandpass gain.
(Figure 1)
fno1ch: the frequency of minimum (ideally zero) gain at the
notch outputs.
fz: the center frequency of the second order complex zero
pair, if any. If fz is different from fo and if Qz is high, it can be
observed as the frequency of a notch at the all pass output.
(Figure 10)
Q: "quality factor" of the 2nd order filter. Q is measured at
the bandpass outputs of the MF10 and is equal to fo divided
by the -3 dB bandwidth of the 2nd order bandpass filter
(Figure 1). The value of Q determines the shape of the 2nd
order lilter responses as shown in Figure 6.
Qz: the quality factor of the second order complex zero pair,
if any. Qz is related to the all pass characteristic, which is
written:
where Qz = Q for an all-pass response.
HOBP: the gain (in VIV) of the bandpass output at f = fo.
HOlP: the gain (in VIV) of the lowpass output as f -+ 0 Hz
(Figure 2).
HOHP: the gain (in VIV) 01 the highpass output as 1 -+
ICLK/2 (Figure 3).
HON: the gain (in VIV) of the notch output as 1 -+ 0 Hz
and as f -+ fCLK/2, when the notch lilter has equal gain
above and below the center frequency (Figure 4). When the
low-frequency gain differs from the high-frequency gain, as
in modes 2 and 3a (Figures 11 and 8), the two quantities
below are used in place of HON.
By tying this pin high a 50:1 clock-to-filter-center-frequency ratio is obtained.
Tying this pin at mid-supplies (i.e, analog
ground with dual supplies) allows the filter to operate at a 100:1 clock-to-center-frequency ratio. When the pin is tied
low (i.e., negative supply with dual supplies), a simple current limiting circuit is
triggered to limit the overall supply current down to about 2.5 mA. The filtering
action is then aborted.
This is the analog ground pin. This pin
should be connected to the system
ground for dual supply operation or biased to mid-supply for single supply operation. For a further discussion of midsupply biasing techniques see the Applications Information (Section 3.2). For
optimum filter performance a "clean"
ground must be provided.
HON1: the gain (in VIV) 01 the notch output as f -+ 0 Hz.
HON2: the gain (in VIV) of the notch output as f -+ fCLK/2.
1-179
....
o
."
o
.,...
LI..
::!5
1.0 Definition of Terms
(Continued)
HBP(S) ~ _-"H",OB",P:.=S_ _
'>
a
i-
HOB. 1 - - - -.....
0.707 HOB. 1----,j~4
S2
90
:1
0 I----f-''Io...
iE -45 I----t-l-.."......
~
+
swO
Q
+
W02
451---~~
-90
Q
I----t-l-~~~
Il I, IH
fL 10 IH
I (LOG SCALE)
I (LOG SCALE)
TLlH/10399-6
TL/H/10399-5
~ -.!9....;
IH - Il
10
~ JfiJH
IL~fo(;~+~(~r+1
)
fH~fo(~+~(~r +1
)
(b)
(a)
wo
=
27TfO
FIGURE 1. 2nd-Order Bandpass Response
HLP(S)
= __
H",O",LP...;.W-"O,-2_
52
;;-
Hop
;;;
HOlP
i" 0.707 HOl.
~
1-;;;;;;;;;;;;;;;;-"
t-
SWO
.~
'"
I-----+-"~
Q
+
W02
::l -90 I-----'lilt.
iE
r
I.
+
-1801-----j----':=!!I-
Ie
10
I (LOG SCALE)
I (LOG SCALE)
TLlH/10399-7
TL/H/10399-8
(a)
(b)
FIGURE 2. 2nd-Order Low-Pass Response
'>
~
H~~: I===~~---
~
.
~ -90
0.707 HOHP
~
iE
-180
Ie
10
I.
I (LOG SCALE)
I (LOG SCALE)
TL/H/10399-10
TLlH/10399-9
(b)
(a)
HOp~ HOHpX 1 ~
1-Q
4Q2
FIGURE 3. 2nd-Order High-Pass Response
1-180
1.0 Definitions of Terms
(Continued)
90
;;-
~ 45
HON
;;:
;; 0.707 HON I---~r---f-'-----
w
~...
iil
-45 I-----~
-90'--_ _...L...:....J'--_ _•
ILio IN
IL=IO(;~ +~(-do? + 1
IL 10 IN
I (LOG SCALE)
I (LOG SCALE)
TUH/l0399-11
TL/H/l0399-12
(a)
(-do + ~(-dor + 1 )
IH = 10
(b)
)
FIGURE 4. 2nd-Order Notch Response
;;- HAP
~
1----..,.---
~
~-180
z
~
t::==::::t==~:
-360
10
10
I (LOG SCALE)
I (LOG SCALE)
TL/H/l0399-14
TL1H/10399-13
(b)
(a)
FIGURE 5. 2nd-Order All-Pass Response
(a) Bandpass
(b) Low Pass
20
20
10
.
10
!t
Q-l
~
;; -10
~
-20 I/"
t--30
-40
"
j'jn.\.
,
~![~O ~ l"-.....
~J'/I\~ Q-~ I.......
0.5 1
2
FREQUENCY (Hz)
""""
-30
-40
0.1
10
0.2
0.5 1.0 2.0
FREQUENCY (Hz)
(d) Notch
10
/
:!!.
z -10
~
-20
~
-20
,
A
-40
10
Kr:::Q=~.5_
,~
-30
I'IIIt.
~
5.0
I 1/
Q=~.L
'V
0.1 0.2
0.5 1.0 2
FREQUENCY (Hz)
5
10
(e) All-Pass
20
.
,. "' ......
~
;; -10
~
~I '
-20 '-Q=0.2
..
t7 ~Q=r "".....,"
0.1
~
Q 0.5
-
=ToQ 2 _I.l..
Q=i....,
-Q 0.707
.
~=0.707-
"-......
-+Q=~=;;;;j I Q- 1O -
10
£.L~Q
i,-Q=l
..,.......
~
(c) High-Pass
20
I-- I--Q-l0 pM+-
''\1~
-60
1=10' t--
,
Q-5
~-120
.
't~-
~
"""''- :~~.-
-180
N
... -240
'Q=11.5-
-30
-300
-40
-360
0.1 0.2 0.5
1.0 2
FREQUENCY (Hz)
r-.. Q-0.2
:c
10
\:=1
I'\.I~
0.1
0.2
0.5
1
10
FREQUENCY (Hz)
TL/H/l0399-15
FIGURE 6. Response of various 2nd-order filters as a function of Q.
Gains and center frequencies are normalized to unity.
1-161
o.....
u..
:::E
2.0 Modes of Operation
The MF10 is a switched capacitor (sampled data) filter. To
fully describe its transfer functions, a time domain approach
is appropriate. Since this is cumbersome, and since the
MF10 closely approximates continuous filters, the following
discussion is based on the well know frequency domain.
Each MF10 can produce a full 2nd order function. See Table I for a summary of the characteristics of the various
modes.
felK
=~=R3
BW
= quality factor of the complex pole pair
= the - 3 dB bandwidth of the bandpass output.
BW
HOlP =
HOlP(peak) "" a
fO
fClK
=
fnotch = center frequency of the imaginary zero pair = fo.
a
R2
0) = - R1
.
f _
HON = Notch output gain as f _
HOlP X a
x HOlP (for high a's)
MODE 1a: Non-Inverting BP, LP (See Figure 8)
fClK
HOBP = Bandpass gain (atf = fo) = -
HOBP
Q
or Hosp =
= HON X O.
1OO 0r 50
.
HOlP = Lowpass gain (as f -
R2
Circuit dynamics:
MODE 1: Notch 1, Bandpass, Lowpass Outputs:
'notch = fo (See Figure 7)
fo
= center frequency of the complex pole pair
=
a
felK
100 or 50
R3
R2
HOlP = -1; HOlP(peak) "" a
R3
HOBP1= -R2
:~
0
}
-R2
f
12 =-R
elK
1
x HOlP (for high a's)
HOBP~ 1 (Non-Inverting)
Circuit Dynamics: HOBP1 = a
Note: VIN should be driven from a low impedance «1
kll)
source.
TL/H/10399-16
FIGURE 7. MODE 1
TUH/10399-17
FIGURE 8. MODE 1a
1-182
2.0 Modes of Operation
MODE 2: Notch 2, Bandpass, Lowpass: fnotch
(See Figure 9)
fo
......
< fo
MODE 3: Highpass, Bandpass, Lowpass Outputs
(See Figure 10)
= center frequency
= fClK ~R2
100
f
:s::
"T1
(Continued)
+ 1 or
R4
= fClK X
fClK
50
~R2 + 1
R4
a
- fClK or fClK
notch - 100
50
a
R2/R3
..
.
R2
Circuit dynamics: - =
R4
Hosp
R2/R1
R2/R4 + 1
HOlP(peak) ~ a
Filter dynamics: Hosp
=
~)
a ~HOlP HON2
= -
HOHP(peak) ~ a
R2/R1
= ~HON1
R2
R1
=
HOlP = Lowpass Gain ( as f ---'" 0 ) = -
HON1 = Notch output gain (as f ---'" 0)
Notch output gain ( as f ---'"
fC~K)
Hosp = Lowpass Gain ( at f = fo) = -
R2/R1
R2/R4 + 1
Hosp = Bandpass output gain (at f = fo) = -R3/R1
=
fR2 x R3
V"R4 R2
HOHP = Highpass Gain ( as f ---'"
+1
HOlP = Lowpass output gain (as f ---'" 0)
HON2
fR2 or fClK x fR2
V"R4 50 V"R4
= quality factor of the complex pole pair
=
= quality factor of the complex pole pair
~R2/R4
100
fO
o
:~
:~
HOHP
--;
HOlP
= ~"'H-O-HP-:-:X'H'O-L-P X a
x HOlP (for high a's)
x HOHP (for high a's)
HON2
H4
HI
SAIB
~6
v+
TLlH110399-18
FIGURE 9. MODE 2
r
ce•
,~
-,
H4
TLlHI1 0399-19
-In Mode 3, the feedback loop is closed around the input summing amplifier; the finite GBW product of this op amp causes a slight Q enhancement. If this is a
problem. connect a small capacitor (10 pF - 100 pF) across R4 to provide some phase lead.
FIGURE 10. MODE 3
1-183
II
o ,-----------------------------------------------------------------------------,
....
u.
:Ii
2.0 Modes of Operation (Continued)
MODE 3a: HP, BP, LP and Notch with External Op Amp
(See Figure 11)
10
o
= IClK X
100
=
MODE 4: Allpass, Bandpass, Lowpass Outputs
(See Figure 12)
= center Irequency
10
fR2 or IClK x fR2
VRA 50 VRA
= IClK or IClK.
fR2 x R3
VRA R2
100
R2
HOHP = -R1
o
Oz = quality lactor 01 complex zero pair =
R4
HOLP = -R1
10
:~
For AP output make R1 = R2
= notch Irequency = IClK
100
fRh
VA;
or IClK
50
. ( atO
HOAp·= Allpass gain
fRh
VA;
1= 10 = \\0
=-
(~HOlP - ~HOHP )\\
Hn1
= gain 01 notch (as I -+ 0) =
Hn2
= gain 01 notch ( as I -+
IClK)
5 kHz.
100:1
50:1
TUH/l0399-32
FIGURE 21. The Sampled-Data Output Waveform
1-190
Section 2
Analog Switchesl
Multiplexers
•
Section 2 Contents
Analog Switches/Multiplexers Definition of Terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog Switches/Multiplexers Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AH00141 AH0014C DPDT, AH001S1 AH001SC Quad SPST, AH00191 AH0019C Dual
DPST-TTL/DTL Compatible MOS Analog Switches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AHS0091 AHS01 0/ AHS011/ AHS012 Monolithic Analog Current Switch. . . . . . . . . . . . . . . . . . . .
AHS020C Monolithic Analog Current Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CD4016BM/CD4016BC Quad Bilateral Switch .........................................
CD40S1 BM/CD40S1 BC Single 8-Channel Analog Multiplexer/Demultiplexer. . . . . . . . . . . . . . .
CD40S2BM/CD40S2BC Dual4-Channel Analog Multiplexer/Demultiplexer ................
CD40S3BM/CD40S3BC Triple 2-Channel Analog Multiplexer/Demultiplexer ...............
CD4066BM/CD4066BC Quad Bilateral Switch .........................................
CD4S29BC Dual 4-Channel or 8-Channel Analog Data Selector ..........................
LF11331/LF13331/LF11332/LF13332/LF11333/LF13333,LF11201/LF13201/LF11202/
LF13202 Quad SPST JFET Analog Switches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LF13S08 8-Channel Analog Multiplexer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LF13S09 4-Channel Analog Multiplexer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MMS4HC4016/MM74HC4016 Quad Analog Switch.....................................
MMS4HC40S1/MM74HC40S1 8-Channel Analog Multiplexer.............................
MMS4HC40S2/MM74HC40S2 Dual4-Channel Analog Multiplexer... . .. .. ... . . .. .... ... ..
MMS4HC40S3/MM74HC40S3 Triple 2-Channel Analog Multiplexer.......................
MMS4HC4066/MM74HC4066 Quad Analog Switch. .. ... . .... . . . . . . ... .. ... .. ..... .... .
MMS4HC4316/MM74HC4316 Quad Analog Switch with Level Translator..................
2-2
2-3
2-4
2-S
2-9
2-20
2-28
2-29
2-29
2-29
2-30
2-31
2-32
2-43
2-43
2-S7
2-S8
2-S8
2-S8
2-S9
2-60
~National
~ Semiconductor
Analog Switch
Definition of Terms
RON: Resistance between the output and the input of an
addressed channel.
Is: Current at any switch input. This is leakage current when
the switch is ON.
10: Current at any switch input going into the switch. This is
leakage current when the switch is OFF.
10-IS: Leakage current that flows from the closed switch
into the body. This leakage is the difference between the
current ID going into the switch and the current Is going out
of the switch.
tRAN: Delay time when switching from one address state to
another.
tON: Delay time between the 50% points of an enable input
and the switch ON condition.
es:
Capacitance between any open terminal "S" and
ground.
tOFF: Delay time between the 50% points of the enable
input and the switch OFF condition.
eo:
Capacitance between any open terminal "D" and
ground.
•
2-3
CP
"CI
"5
CJ
c
o
~
_NatiOnal
Semiconductor
CP
Ci)
en
...
Analog Switch/Multiplexer Selection Guide
CP
=
"ii
:;=
"3
:::!!i
.....
-
.c
u
~
Q
o
c
(ii
c(
Vs
Part Number
Function
Logic Input
AH0014
AH0015
AH0019
AH5011
AH5012
CD4016
CD4066
LF11201/LF13201
LF11202/LF13202
LF11331/LF13331
LF11332/LF13332
LF11333/LF13333
MM74HC4016
DPDT
QUADSPST
DUAL DPST
QUADSPST
TTL,DTL
TTL,DTL
TTL,DTL
TTL,CMOS
TTL,CMOS
CMOS
CMOS
TTL
TTL
TTL
TTL
TTL
CMOS
+10/-22
AH5020
DUALSPDT
TTL,CMOS
-
TRIPLESPDT
CMOS
CMOS
CD4053
MM74HC4053
AH5009
AH5010
(Typ)
+10/-22
+10/-22
±7.5
±7.5
±15
±15
±15
±15
±15
±12
±7.5
±6.0
-
TON/TOFF
ns(Typ)
RON
350/600
100/600
100/600
150/300
150/300
20/40
25/50
90/500
90/500
90/500
90/500
90/500
5/8
75
75
75
100
150
850
280
200
200
200
200
200
40
150/300
150
160175
15/16
300
40
150/300
150/300
100
150
160175
n
4-CHANNEL
TTL,CMOS
TTL,CMOS
CD4052
CD4529B
LF13509
MM74HC4052
4-CHANNEL
DIFFERENTIAL
CMOS
CMOS
TTL,CMOS
CMOS
±7.5
±7.5
±18
±6.0
50
1600/200
15/16
300
350
350
40
CD4051
CD4529B
LF13508
MM74HC4051
8-CHANNEL
CMOS
CMOS
TTL,CMOS
CMOS
±7.5
±7.5
±18
±6.0
160/75
50
1600/200
15/16
300
350
350
40
2-4
~
:x:
o
o.....
~National
~ Semiconductor
.j:>.
.......
~
:x:
o
o
.....
.j:>.
AH0014/AH0014C* DPDT, AH0015/AH0015C Quad
SPST, AH0019/AH0019C* Dual DPST-TTL/DTL
Compatible MOS Analog Switches
o
.......
~
:x:
o
o
.....
General Description
This series of TIL/DTL compatible MaS analog switches
feature high speed with internal level shifting and driving.
The package contains two monolithic integrated circuit
chips: the MaS analog chip is similar to the MM450 type
which consists of four MaS analog switch transistors; the
second chip is a bipolar I.C. gate and level shifter. The series is available in hermetic dual-in-line package.
.......
Features
o.......
•
•
•
•
•
•
•
•
These switches are particularly suited for use in both military
and industrial applications such as commutators in data acquisition systems, multiplexers, AID and D/ A converters,
long time constant integrators, sample and hold circuits,
modulators/demodulators, and other analog signal switching applications.
U1
The AH0014, AH0015 and AH0019 are specified for operation over the - 55°C to + 125°C military temperature range.
The AH0014C, AH0015C and AH0019C are specified for
operation over the - 25°C to + 85°C temperature range.
~
:x:
o
o
.....
U1
± 10V
500 ns
Large analog voltage switching
Fast switching speed
Operation over wide range of power supplies
Low ON resistance
High OFF resistance
Analog signals in excess of
Fully compatible with DTL or TIL logic
Includes gating and level shifting
200{1
1011 {1
25 MHz
~
:x:
o
o
.....
CD
.......
~
:x:
o
o.....
CD
o
Block and Connection Diagrams
QuadSPST
,.-------------- ..
ANALOG B:
:
IN At.
~
ANALOG,_9"':!-_ _.....
IN 81- I
'10 ANALOG
ANALOG 7:
I
:O>---.. .
A~~L~~
6:
IN 92'
I
ot.:.a
•
I
:
5
,I ,lOUT 1
,
IN 1
I
ANAI~O~~~~~L~G
~~~L~G
AN~~O~
I
l: ~' ~~
.----- ------:TVee
~~il~
~ANALOG
ANALOG 11:
'-"'-OUT 1
I
7:
•
I
~:
I
I
I: 8
:
i
I
I
~~~LfG
AN~~O~!~i ~: ~: ~: ~?-~L~G
t_ ___ __ ___ _!L~Wo
...-GND
2
1
16
15
LOGIC LOGIC LOGIC LOGIC
4
3
2
1
LOGIC
B
Note: All logic inputs shown at logiC "1",
Note: All logic inputs shown at logic "1".
TL/K/10125-1
Dual DPST
6.--------------.,
ANALOG
INA1~
ANALOG
~
.L.!..L ANALOG
OUT 1
'_
IN 81.
I
~;
ANALOG 9.
•
I
I
INA2~'
•
ANALOGy!:":
INB2.
•
~
:10
ANALOG
~OUT2
l:•- -'1~'~'
~~
:TVee
-1312 - - - -
Note: All logic inputs shown at logic "1".
TLlK/10125-2
Order Number AH0015D or AH0015CD
See NS Package Number D16C
Order Number AH0014D or AH0014CD
See NS Package Number 0140
2
.-GND
LOGIC
LOGIC
AI
A2
LOGIC
LOGIC
Bl
B2
Order Number AH0019D or AH0019CD
See NS Package Number 0140
'Previously called NH0014/NH0014C and NH0019/NH0019C
2-5
TLlK/10125-3
fJI
-~
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
V- Supply Voltage
-30V
X
en
o
o
.
CD
i>
X
AH50091 AH50 101 AH50 111 AH50 12 Monolithic
Analog Current Switches
•
•
•
•
•
•
•
•
General Description
A versatile family of monolithic JFET analog switches economically fulfills a wide variety of multiplexing and analog
switching applications.
Even numbered switches may be driven directly from standard 5V logic, whereas the odd numbered switches are intended for applications utilizing 10V or 15V logic. The monolithic construction guarantees tight resistance match and
track.
.......
l>
X
Active filters
Signal multiplexers/demultiplexers
Multiple channel AGC
Quad compressors/expanders
Choppers/demodulators
Programmable gain amplifiers
High impedance voltage buffer
Sample and hold
en
o
....
....
.......
l>
X
en
o
....
N
Features
For voltage switching applications see LF13331, LF13332,
and LF13333 Analog Switch Family, or the CMOS Analog
Switch Family.
•
•
•
•
•
•
•
Applications
•
•
..
•
•
en
....o
o
AID and Df A converters
Micropower converters
Industrial controllers
Position controllers
Data acquisition
Interfaces with standard TTL and CMOS
"ON" resistance match
Low "ON" resistance
Very low leakage
Large analog signal range
High switching speed
Excellent isolation between
channels
20
1000
50 pA
± 10V peak
150 ns
80 dB
at 1 kHz
Connection and Schematic Diagrams (All switches shown are for logical "1" input)
Dual-In-Line Package
Dual-In-Line Package
14
"
"12
15
LOGIC DRIVE
\I
5VLOGIC
15V LOGIC
10
4 CHANNEL
MUX
4SPST
SWITCHES
AH5010C
AH5009C
AH5012C
AH5011C
"
13
12
\I
10
TOP VIEW
AH5009C and AH5010C MUX Switches
(4-Channel Version Shown)
Order Number AH5009CM,
AH5009CN, AH5010CM or AH5010CN
See NS Package Number M14A or N14A
TO' VIEW
AH5011C and AH5012C SPST Switches
(Quad Version Shown)
Order Number AH5011CM,
AH5011CN, AH5012CM or AH5012CN
See NS Package Number M16A or N16A
100--+----'
120---+-----'
120-.....----1
130-.....-----'
"
"
"
COMMON DRAINS
UNCOMMlnED DRAINS TL/H/5659-1
Nole: All diode cathodes are internally connected to the substrate.
2-9
....o
N
it)
Absolute Maximum Ratings
~
....
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications•
::r:
....
o
it)
::r:
~....
o
it)
::r:
~o
oit)
::r:
c:c
(Note t)
Input Voltage
AH50091 AH501 01 AH5011 1AH5012
30V
Positive Analog Signal Voltage
30V
Drain Current
30mA
Soldering Information:
N Package 10 sec
SO Package Vapor Phase (60 sec.)
Infrared (15 sec.)
300'C
215'C
220'C
Power Dissipation
500mW
Negative Analog Signal Voltage
-15V
Operating Temperature Range
Diode Current
10mA
Storage Temperature Range
- 25'C to + 85'C
- 65'C to + 150'C
Electrical Characteristics AH5010 and AH5012 (Notes 2 and 3)
Symbol
Conditions
Typ
Max
Units
IGSX
Input Current "OFF"
4.5VS:VGoS:11V, Vso=0.7V
TA=85'C
0.01
0.2
10
nA
nA
10(OFF)
Leakage Current "OFF"
Vso=0.7V, VGs=3.8V
TA=85'C
0.02
0.2
10
nA
nA
IG(ON)
Leakage Current "ON"
VGo=OV,ls=1 rnA
TA=85'C
0.08
1
200
nA
nA
IG(ON)
Leakage Current "ON"
VGo=OV,ls= 2 rnA
TA=85'C
0.13
5
10
nA
poA
IG(ON)
Leakage Current "ON"
VGo=OV,ls= -2 rnA
TA=85'C
0.1
10
20
nA
poA
roS(ON)
Drain-Source Resistance
VGs=0.35V,ls=2 rnA
TA=+85'C
90
150
240
n
n
VolOoE
Forward Diode Drop
10=0.5 rnA
roS(ON)
Match
VGS=OV, 10=1 rnA
TON
Turn "ON" Time
See AC Test Circuit
TOFF
Turn "OFF" Time
See AC Test Circuit
CT
CrossTalk
See AC Test Circuit
120
Parameter
0.8
V
20
n
150
500
ns
300
500
4
ns
dB
Electrical Characteristics AH5009 and AH5011 (Notes 2 and 3)
Typ
Max
Units
IGSX
Input Current "OFF"
11VS:VGoS:15V, Vso=0.7V
TA=85'C
0.01
0.2
10
nA
nA
10(OFF)
Leakage Current "OFF"
Vso=0.7V, VGS= 10.3V
TA=85'C
0.D1
0.2
10
nA
nA
IG(ON)
Leakage Current "ON"
VGo=OV,ls= 1 rnA
TA=85'C
0.04
0.5
100
nA
nA
IG(ON)
Leakage Current "ON"
VGo=OV,ls=2 rnA
TA=85'C
2
1
nA
poA
IG(ON)
Leakage Current "ON"
VGo=OV,ls= -2 rnA
TA=85'C
5
2
p.A
100
160
n
n
Symbol
Parameter
Conditions
roS(ON)
Drain-Source Resistance
VolOoE
Forward Diode Drop
10=0.5 rnA
roS(ON)
Match
VGs=OV,10=1 rnA
TON
Turn "ON" Time
See AC Test Circuit
TOFF
Turn "OFF" Time
See AC Test Circuit
VGs=1.5V,ls=2 rnA
TA=85'C
CT
60
nA
0.8
V
10
n
150
50
ns
300
500
ns
2
CrossTalk
See AC Test Circuitf = 100 Hz.
120
dB
Note I: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating cond~ions.
Note 2: Test conditions 25'C unless otherwise noted.
Note 3: "OFF" and "ON" notation refers to the conduction state of the FET switch.
Note 4: Thermal Resistance:
8JA
NI4A, NI6A
MI4A,MI6A
9Z'C/W
115'C/W
2-10
)I-
::r:
Test Circuits and Switching Time Waveforms
UI
o
o
CD
.....
)I-
Cross Talk Test Circuit
~~-~+~15~V--------'
::r:
UI
o
....
o
10k
) I-
::r:
UI
....o
....
.....
)I-
.-o VOUT
~6_ _ _
::r:
UI
10k
o
....
N
10k
-15V
Time Waveforms
+5V D,+15V
AC Test Circuit
VA =±10V
_--"--0
VOUT
(C L S 10 pF)
TLiH/5659-2
2-11
Typical Performance Characteristics
Leakage Current, IO(OFF)
vs Temperature
Parameter Interaction
1000
ros it1o'" -1 mAo Ves =OV
~c
hI! Vas = -15V. Vos = OV PULSED
:i.!
-~
t;!;; 200
....
..
2i~
iE~
..
YGSIOFF.@Vos·-1SV,tD=-1 nA
§
ig
loss
""";,..
100
....
10
,.!l
..
!
~
p~
!!! ..
",,,
'os
20
/
10
10k
l
Ii:
9
,..:
,g
lk
..
..~
100
10
~
./
25
35
125
J
\~'fIl ..k::::: ::::;;;..-
100
po - ttl'\D'~~
\~C1II'" oS
..
ri
75
i.
50
iE
-
I-- $
zs
p
35
55
45
65
-
I
'VA - ~iov'
r--
-3~
-20
-1.
85
lDo
lk
TEMPERATURE I'C)
1000
100
..'"
~
I
!..'" IO~1III
=
ID=-2ni~
8
:=1=
~
10
5
1.0
ly--lmA
mID-fj~
I I I I
5.0
D
10
z
-(..=
I
8
~
I
15
TA = 25'C
Voo --5V
''''1 kHz
100
~
~ VOSIaFF)
1
-G.1
20
~
5V
-1.0
-10
DRAIN CURRENT (mA)
Normalized Drain
Resistance vs Bias Voltage
-2D
\
\
VQSIOFF'.-1OV.-'OP~A~I=~~~
'DSb = __'DS
__
-15
\
.!
z
V.SIOFF' •
~~!OFF'=7.5vlll
Drain Current vs Bias
Voltage
-25
I
2V
YfJ.omoi
oRAIN·GATE VOLTAGE IV)
C
1M
Transconductance vs
Drain Current
TA=25°C
ill
IIOk
10k
FREQUENCY 1Hz)
Leakage Current vs
Drain-Gate Voltage
i...
85
Cross Talk, CT vs Frequency
-
15
75
65
-120
-110
-100
i i -110
:!!
t; -80
~ -10
~ -60
-50
-40
o
25
55
45
TEMPERATURE I'C)
"ON" Resistance, rOS(ON)
vs Temperature
§
./
10
100
10=-1 mA
I
~
V••. GATE SOURCE CUTOFF VOLTAGE IV)
1&0
I
ill
8
1.0
1.0
I
-10
-5
Vas '" -10V
,., kHz
TA = 25°C
\
1-~
VGIIDFF)
+-t-t-H
\ \
\
, I'.. r-....
\. \.. "\..
"
1.0
I--.
2.0
3.0
0.2
GATE-IlOURCE VOLTAGE IV)
0.4
OJ
D.'
1.0
IVGSIVGSIOFFII- NORMALIZED GATE·
To-5oURCE VOLTAGE (V)
2-12
TLlH/5659-3
):0
:::J:
Applications Information
UI
C)
C)
Theory of Operation
The AH series of analog switches are primarily intended for
operation in current mode switch applications; i.e., the
drains of the FET switch are held at or near ground by oper·
ating into the summing junction of an operational amplifier.
Limiting the drain voltage to under a few hundred millivolts
eliminates the need for a special gate driver, allowing the
switches to be driven directly by standard TIL (AH5010),
5V·l0V CMOS (AH5010), open collector 15V TIL/CMOS
(AH5009).
"OFF" state. With VIN=15V and the VA=10V, the source
of 01 is clamped to about 0.7V by the diode (VGS= 14.3V)
ensuring that ac signals imposed on the 10V input will not
gate the FET "ON."
Selection of Gain Setting Resistors
Since the AH series of analog switches are operated in current mode, it is generally advisable to make the signal current as large as possible. However, current through the FET
switch tends to forward bias the source to gate junction and
the signal shunting diode resulting in leakage through these
junctions. As shown in Figure 2, IG(ON) represents a finite
error in the current reaching the summing junction of the op
amp.
Two basic switch configurations are available: 4 indepen·
dent switches (SPST) and 4 pole switches used for multi·
plexing (4 PST-MUX). The MUX versions such as the
AH5009 offer common drains and include a series FET operated at VGs= OV. The additional FET is placed in the
feedback path in order to compensate for the "ON" resistance of the switch FET as shown in Figure 1.
Secondly, the rOS(ON) of the FET begins to "round" as IS
approaches loss. A practical rule of thumb is to maintain Is
at less than 11'0 of lOSS.
Combining the criteria from the above discussion yields:
The closed-loop gain of Figure 1 is:
A
vel =
R2
Rl
+ rOS(ON)02
+ rOS(ON)01
R 1 . ~ VA(MAX) AD
min
IG(ON)
For Rl = R2, gain accuracy is determined by the rOS(ON)
match between 01 and 02. Typical match between 01 and
02 is 4 ohms resulting in a gain accuracy of 0.05% (for Rl
= R2 = 10 k!l).
(2a)
or:
~ VA(MAX)
loss/10
whichever is larger.
Noise Immunity
(2b)
The switches with the source diodes grounded exhibit improved noise immunity for positive analog signals in the
!ANAlOG V
INPUT A
Rl
10k
R2
10k
ANALOG
OUTPUT
-
-
FIGURE 1. Use of Compensation FET
--
VA
Is'"
Rl
VA =+IDV
iii
ID = Is - IGIDNI
-.
R2
TUH/5659-4
FIGURE 2. On Leakage Current, IG(ON)
2-13
~
):0
:::J:
UI
....
C)
.....
):0
C)
:::J:
UI
........
......
C)
):0
:::J:
UI
....
N
C)
....
~.-----------------------------------------------------------~
~
Applications Information
~
....
Where: VA(MAXl
::I:
....o
..,
AD
~
IG(ON)
loss
::I:
..,....::I:
o
o
~
~
::I:
cc
(Continued)
= Peak amplitude of the analog
input signal
= Desired accuracy
Accordingly:
= Leakage at a given Is
= Saturation current of the FET
switch
Where: VA(MIN)
Rl MA ,;;; VA(MIN) AD
( Xl (N) IO(OFF)
"'20mA
In a typical application, VA might = ±10V, Ao=O.l%,
O'C,;;;TA,;;;8S'C. The criterion of equation (2b) predicts:
(10V)
Rl(MIN): ....10-.0 OUTPUT
ANALOG
TO
10k)
LOGIC
INPUT
I
(V IN)
I
I
I
I
:::J:
_JI
-
~~~----...:.
FIGURE 4. Interfacing with
+5V OR +15V
ANALOG
INPUT (VA)
r------ I
I
I
I
I
I
+ 5V TTL
I
I
I
I
I
10k
.+15V
>""""'0 ANALOG
OUTPUT
RexT
(2kTO
10k)
LOGIC
INPUT
(V;n)
TL/H/5659-6
FIGURE 5. Interfacing with
+ 15V Open Collector TTL
2-15
•
....oCN
II)
~
r-------------------------------------------------~----------------------------__,
Applications Information
(Continued)
-4--0 OUT
TUH/5659-7
2·16
Typical Applications
»
::I:
(Continued)
(II
o
o
CD
......
a·Channel Multiplexer with Sample and Hold
»
::I:
(II
o
.....
o
i;
::I:
(II
o.....
.....
i;
10k
::I:
II
(II
I
10k
ANALOG
INPUTS
o.....
I\)
I
10k
I
L__ •
4
I
_ _ _ _ _ ...1I
12
CHARACTERISTICS, TYPICAL OUTPUT
VOLTAGE DRIFT
I '. . . CHANNEL
I
SAMPLE/HOLD
SELECT
14
~----'
-............,
E1N13
EIN14
E1N15
E1N16
I
I
I
I
61
I
I
111
I8
I
I
19
I
I
I
CHARACTERISTICS:
I
I
141
ERROR~O.4"V
TYPICAL@ 2S'C
10"V TYPICAL @ 70'C
116
Note: The analog switch between the op amp and the 16 input
I
IL.....:.
- ____
15 JI
switches reduces the errors due to leakage.
13
All resistors are 10k.
2-18
TL/H/5659-9
r-------------------------------------------------------------------~~
Typical Applications
:::E:
U1
(Continued)
o
o
CD
.....
Gain Programmable Amplifier
~
:::E:
U1
....
~:::E:
o
....
....
o
lilk
U1
"
»
lile
:::E:
U1
....
o
I\)
&
lOOk
9
1M
13
10M
I
-1 CHARACTERISTICS: GAIN' -EoI
UT.
IN
R'B
IZ
GAIN SELECT
TUH/5659-10
fII
2-19
o
Q
~ ~National
~ ~ Semiconductor
AH5020C Monolithic Analog Current Switch
General Description
Applications
This versatile dual monolithic JFET analog switch economically fulfills a wide variety of multiplexing and analog switching applications.
• AID and D/ A converters
• Micropower converters
• Industrial controllers
• Position controllers
• Data acquisition
• Active filters
• Signal multiplexers/demultiplexers
• Multiple channel AGC
• Quad compressors/expanders
• Choppers/demodulators
• Programmable gain amplifiers
• High impedance voltage buffer
• Sample and hold
For voltage switching applications see LF13201, LF13202,
LF13331, LF13332, and LF13333 Analog Switch Family, or
the CMOS Analog Switch Family.
These switches may be driven directly from standard 5V
logic.
The monolithic construction guarantees tight resistance
match and track.
Features
•
•
•
•
•
•
•
Interfaces with standard TTL
"ON" resistance match
Low "ON" resistance
Very low leakage
Large analog signal range
High switching speed
Excellent isolation between
channels
2n
150n
50 pA
±10V peak
150 ns
80 dB
at 1 kHz
Connection and Schematic Diagrams (All switches shown are for logical "1 ")
Dual-In-Llne Package
TLlH/5166-1
Top View
Order Number AH5020CJ
See NS Package Number J08A
3
TLlH/5166-2
Note: All diode cathodes are intemally connected to the substrate.
2-20
Absolute Maximum Ratings
(Note 1)
Drain Current
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Positive Analog Signal Voltage
-15V
Diode Current
10mA
- 25·C to + 85·C
-65·Cto + 150·C
Storage Temperature Range
30V
Negative Analog Signal Voltage
500mW
Operating Temp. Range
30V
Input Voltage
30 rnA
Power Dissipation
Lead Temp. (Soldering, 10 seconds)
300·C
Electrical Characteristics (Notes 2 and 3)
Symbols
Parameter
Typ
Max
Units
0.01
0.Q1
0.1
0.2
10
nA
nA
nA
0.Q1
0.2
10
nA
nA
1 rnA
0.08
1
200
nA
nA
=
2 rnA
0.13
5
10
nA
p.A
=
-2mA
0.1
10
20
nA
p.A
90
150
240
.n
.n
Conditions
IGSX
Input Current "OFF"
VGO = 4.5V, VSO = 0.7V
VGO = 11V, VSD = 0.7V
TA = 85·C, VGO = 11V, VSO
10(OFF)
Leakage Current "OFF"
VSD = 0.7V, VGS
TA = 85·C
IG(ON)
Leakage Current "ON"
VGO = OV, Is
TA = 85·C
=
IG(ON)
Leakage Current "ON"
VGO = OV, Is
TA = 85·C
IG(ON)
Leakage Current "ON"
VGO = OV,ls
TA = 85·C
rOS(ON)
Drain-Source Resistance
VGS = 0.5V, is
TA = +85·C
VOIOOE
Forward Diode Drop
10
rOS(ON)
Match
VGS
TON
Turn "ON" Time
=
=
=
3.8V
2 rnA
=
0.7V
0.8
V
2
20
.n
See ac Test Circuit
150
500
ns
500
0.5 rnA
=
0, 10
=
1 rnA
TOFF
Turn "OFF" Time
See ac Test Circuit
300
CT
CrossTalk
See ac Test Circuit
120
ns
dB
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: Test conditions 25'C unless otherwise noted.
Note 3:
"OFF" and "ON"
notation refers to the conduction state of the
FET switch.
Note 4: Thermal Resistance:
6JA (Junction to Ambient) .......... Nt A
6Jc(Junction to Case) ............. Nt A
2-21
g
S
Test Circuits
1.1)
:::E:
cc
AC Test Circuit
Cross Talk Test CIrcuIt
10k
, . - -.....-.0 vour
(CLsl0 pF)
>---"'-Vour
10k
O.lF
10k
-15V
TUH/5166-4
~
TL/H/5166-3
Switching Time Waveforms
VIN
.. = If'; 0.1,..
OV
D.8V --+--~~--+_
Vour
VA = +lOV
OV
OV
Vour
VA= -lOV--jr--f'o---+-_J
TL/H/5166-5
2-22
»
::E:
Typical Performance Characteristics
U1
Parameter Interaction
l000~--~~--~~~~
c;,;ffi
....
~
s:
...eo...
...c::
;:
:z:
200
t--t::W+I1itt'lloss-t-HttttI
:Z::z:
~:5
leo
20
!z
w
~
10
:!l!l:!l°o~.ml
a
a:
a:
lk
I
100
./
::0
00
iii
m
....
a-
./
1
t
t-+fi-ttHtt--t-t+tH-Hl
o
10k
100
e
woo""
~~
o
N
o
Leakage Current, IO(OFF)
vs Temperature
J
10
1.0
1.0
5 10
100
VGS-GATE-SOURCE CUTOFF VOLTAGE (V)'
10
,
25
35
,
I
45 55 65 75
TEMPERATURE rC)
85
TLlH/5166-6
TLlH/5166-7
"ON" Resistance, rOS(ON)
vs Temperature
150
S'
;;; 125
~
100
a:
75
III
50
oJ
25
5V~
F"
Cross Talk, CT vs Frequency
--
5VTTL
-120 E'T'''''T''"T''T'Tn-rr~~:rrt
-110 H"Oi/:I-H--'H-tlt--HrVjA - ± 10V
~-100 1-t~~~~-r-ttij-H-tH
:!!. -90
o
25
35
45 55 65 75
TEMPERATURE rC}
1-+-H-H-N"Ht-l--++I+-H-fH
~ -SO
ti
-70 I-I-~+~~+~~~~~~~~t+:
....... ~
5! -60 1-++++l-H+II-++R'II::-I-I-fH
~ ;;-m/l0~-15V CMOS
Z
5"
.L
ID--l mA
'f -50 H-+ttt-HtIt++HIH"'P'tt1
!; -40 1+++H-H+!t+++IIH-ritl
-30 H-++IH-HfHl-HrH-HtH
-20 H-++IH-HfHf+rH-HtH
-10 ............................u....;.....w................
100
lk
10k
lOOk
1M
FREQUENCY (Hz)
85
TLlH/5166-B
TLlH/5166-9
Leakage Current vs
Drain-Gate Voltage
Transconductance vs
Drain Current
:; l000;w.~
8
l:!
100
TA-2S"C
Voo--5V
1=1 kHz
100
II
::0
00
;
=VCIS(OFFj=2V
10
w
~i:lI
~VCIS(OFFj=5V
li
~~
5.0
10
15
20
ORAIN-GATE VOLTAGE (V)
1
-0.1
25
VCIS(OFFj,!,7.'5J
III
-10
-1.0
DRAlN CURRENT (mA)
TLlH/5166-11
TL/H/5166-10
Drain Current vs Bias
Voltage
-25
!-20
~
Normalized Drain Resistance
vs Bias Voltage
g
Vos= -10V
1=1 kHz
TA=25"C
\
\
.l
w
~
~
1- \,\ "\
15
3! -10
!l
1.
-5
o
o
1-~
20
~
10
VGS(OFF
:::
~~
=
J
:E
5.0
z
1 2.0
~
~ ~ ~
~
@ -10V. -10 pA
IDS
50 IDSb=---
~
co
::0
00
100 VGS(OFFI
'" "- ......
~
1'000.
1.0
2.0
3.0
GATE-sGURCE VOLTAGE (V)
............ -"
0.2
0.4
0.6
0.8
1.0
'Vas IVGS(OFFI!-NORMAUZ£D
GATE-TD-SDURCE VDlJAGE (V)
TLlH/5166-12
TLlH/5166-13
2-23
Applications Information
THEORY OF OPERATION
NOISE IMMUNITY
The AH5020 analog switches are primarily intended for operation in current mode switch applications; i.e., the drains
of the FET switch are held at or near ground by operating
into the summing junction of an operational amplifier. Limiting the drain voltage to under a few hundred millivolts eliminates the need for a special gate driver, allowing the
switches to be driven directly by standard TTL.
The switches with the source diodes grounded exhibit improved noise immunity for positive analog signals in the
"OFF" state. With VIN = 15V and the VA = 10V, the
source of 01 is clamped to about 0.7V by the diode (VGS =
14.3V) ensuring that ac signals imposed on the 10V input
will not gate the FET "ON".
SELECTION OF GAIN SETTING RESISTORS
If only one of the two switches in each package is used to
apply an input signal to the input of an op amp, the other
switch FET can be placed in the feedback path in order to
compensate for the "ON" resistance of the switch FET as
shown in Figure 1.
Since the AH5020 analog switches are operated in current
mode, it is generally advisable to make the. signal current as
large as possible. However, current through the FET switch
tends to forward bias the source to gate junction and the
signal shunting diode resulting in leakage through these
junctions. As shown in Figure 2, IG(ON) represents a finite
error in the current reaching the summing junction of the op
amp.
The closed-loop gain of Figure 1 is:
AVCL = _
=R=.2....:+....:.=ro""s'""(O"'N"')Q~2
R1 + rOS(ON)Ql
For R1 = R2, gain accuracy is determined by the rOS(ON)
match between 01 and 02. Typical match between 01 and
02 is 20 resulting in a gain accuracy of 0.02% (for R1 = R2
= 10 kO).
Secondly, the rOS(ON) of the FET begins to "round" as Is
approaches loss. A practical rule of thumb is to maintain Is
at less than '/,0 of loss.
Combining the criteria from the above discussion yields:
R1 MIN :;, VA(MAX)AO
()
IG(ON)
(2a)
or:
:;, VA(MAX)
(2b)
loss/10
whichever is larger.
Rl
-=
10k
HZ
10k
> - -....
TL/H/5166-14
FIGURE 1. Use of Compensation FET
ISE!~
Rl-
R2
TL/H/5166-15
FIGURE 2. On Leakage Current, IG(ON)
2-24
.-----------------------------------------------------------------,~
Applications Information
::I:
(J1
(Continued)
o
N
Accordingly:
= Peak amplitude of the analog input
signal
= Desired accuracy
AO
= Leakage at a given IS
IG(ON)
= Saturation current of the FET switch
loss
= 20 mA
In a typical application, VA might = ±10V, Ao =0.1%, O·C
s TA S 8S·C. The criterion of equation (2b) predicts:
Where VA(MAX)
o
R1 MAX S VA(MIN) Ao
(
) (N) IO(OFF)
Where VA(MIN) = Minimum value for the analog input signal
Ao
Desired accuracy
N
= Number of channels
IO(OFF)
= "OFF" leakage of a given FET switch
As an example, if N=10, Ao=0.1%, and IO(OFF) S 10 nA
at 8S·C for the AHS020. R1(MAX) is:
10V
R1(MIN) :2: 20 mA =S kO
10
For R1 = Sk, Is'" 10V/Sk or 2 mAo The electrical characteristics guarantee an IG(ON) s 1p.A at 8S·C for the
AHS020. Per the criterion of equation (2a):
(10V)(10- 3)
R1(MIN):2: 1 X 10- 6 :2: 10 kO
(1V)(10- 3 )
R1(MAX) S (10)(10 X 10-9)
o
10k
Selection of R2, of course, depends on the gain desired and
for unity gain R1 = R2.
Lastly, the foregoing discussion has ignored resistor tolerances, input bias current and offset voltage of the op
amp - all of which should be considered in setting the
overall gain accuracy of the circuit.
Since equation (2a) predicts a higher value, the 10k resistor
should be used.
The "OFF" condition of the FET also affects gain accuracy.
As shown in Figure 3, the leakage across Q2, IO(OFF) represents a finite error in the current arriving at the summing
junction of the op amp.
IS"'~
81-
R2
•
H1
TL/H/5166-16
FIGURE 3. Off Leakage Current, IO(OFF)
2-2S
Applications Information (Continued)
TTL COMPATIBILITY
DEFINITION OF TERMS
Standard TTL gates pull-up to about 3.5V (no load). In order
to ensure turn-off of the AH5020, a pull-up resistor, REXT of
at least 10 kG should be placed between the 5V Vee and the
gate output as shown in Figure 4.
The terms referred to in the electrical characteristics tables
are as defined in Figure 5.
AIIALOtI
INPUT (VAl
r------'5V
10k
RElIT
(2k
ANALOG
TO
OUTPUT
10k)
LOGIC
I
I
I
INPUT (VIII)
m
'='
'=' J
&.::_----• 5V
BATE
TL/H/5166-17
FIGURE 4. Interfacing with
+ 5V TTL
VA .....W~....- - : : " t
a:,:TL/H/5166-16
FIGURE 5. Definition of Terms
2-26
Typical Applications
Deglitched Switch for Noiseless Audio Switching
Off
ftC TYPICALLY
1 ms-l0 ms
rON
AUDIO
SIGNAL -~M..-"'-:-:-:!
INPUT
>-+-OUT
TLlH/5166-19
Gain Programmable Amplifier
10k
>;....-....-EoUT
r
10k
l
I
I
I
I
I
I
I
lOOk
Characteristics: Gain
L __ _
2
.
__:"J
~
- EIOUT
IN
~
RFS
7
GAIN SELECT
TL/H/5166-20
2-27
o
m
CD
.,...
~National
C
"'lI'
C
o
.....
~ Semiconductor
:::i!l
m CD4016BM/CD4016BC Quad Bilateral Switch
.,...
C
"'lI'
General Description
C
o The CD4016BM/CD4016BC is a quad bilateral switch in- • Extremely high control input impedance
CD
tended for the transmission or multiplexing of analog or digital signalso It is pin-for-pin compatible with CD4066BM/
CD4066BCo
• Low crosstalk between switches
1012n (typo)
- 50 dB (typo)
@ flS = 009 MHz, RL = 1 kn
• Frequency response, switch "ON"
40 MHz (typo)
Features
Applications
3V to 15V
Wide supply voltage range
Wide range of digital and analog switching ±705 VpEAK
400n (typo)
"ON" resistance for 15V operation
Matched "ON" resistance over 15V
signal input
aRON = 1on (typo)
0.4 % distortion (typo)
• High degree of linearity
@flS = 1 kHz, Vls=5 Vp_p,
•
•
•
•
• Analog signal switching/multiplexing
• Signal gating
• Squelch control
• Chopper
• Modulator/Demodulator
• Commutating switch
• Digital signal switching/multiplexing
• CMOS logic implementation
• Analog-to-digital/digital-to-analog conversion
• Digital control of frequency, impedance, phase, and analog-signal gain
Voo-Vss=10V, RL = 10 kn
• Extremely low "OFF" switch leakage
001 nA (typo)
@Voo - VSS= 10V
TA=25°C
Schematic and Connection Diagrams
Dual-In-Llne Package
14
IN lOUT
IN lOUT
:::==::::;113~ CONTROL A
OUTIIN -=-If-_...1
CONTROL---t----{>c_--...,
---IIt-
OUTIIN
Voo
OUTIIN -=-11---,
CONTROL D
INIOUT
INIOUT
CDNTROL B
OUTIIN
CONTROL C"'""":1----.,
r---+'-DUT/IN
Vss
INIOUT
TDP VIEW
TLlF/5661-1
Order Number CD4016B'
'Please look into Section B, Appendix 0 for availability of various package typeso
See the CMOS Logic Databook for Complete Specifications
2-28
o
c
~National
"'oCJ1"
....
~ Semiconductor
III
s::
o
........
c
CD4051BM/CD4051BC Single 8-Channel Analog
MultiplexerIDemultiplexer
CD4052BM/CD4052BC Dual 4-Channel Analog
MultiplexerIDemultiplexer
CD4053BM/CD4053BC Triple 2-Channel Analog
MultiplexerIDemultiplexer
...."'"
o
CJ1
III
o........
o
c
"'o"
CJ1
N
III
s::
o
........
c
General Description
These analog multiplexers/demultiplexers are digitally controlled analog switches having low "ON" impedance and
very low "OFF" leakage currents. Control of analog signals
up to 15Vp_p can be achieved by digital signal amplitudes of
3-15V. For example, if Voo = 5V, Vss = OV and VEE = - 5V,
analog signals from - 5V to + 5V can be controlled by digital inputs of 0-5V. The multiplexer circuits dissipate extremely low quiescent power over the full Voo-Vss and
VOO-VEE supply voltage ranges, independent of the logic
state of the control signals. When a logical "1" is present at
the inhibit input terminal all channels are "OFF".
CD4051BM/CD4051BC is a single 8-channel multiplexer
having three binary control inputs. A, B, and C, and an inhibit
input. The three binary signals select 1 of 8 channels to be
turned "ON" and connect the input to the output.
CD4052BM/CD4052BC is a differential4-channel multiplexer having two binary control inputs, A and B, and an inhibit
input. The two binary input signals select 1 or 4 pairs of
channels to be turned on and connect the differential analog inputs to the differential outputs.
CD4053BM/CD4053BC is a triple 2-channel multiplexer
having three separate digital control inputs, A, B, and C, and
an inhibit input. Each control input selects one of a pair of
channels which are connected in a single-pole double-throw
configuration.
Features
• Wide range of digital and analog signal levels: digital
3-15V, analog to 15Vp_p
B Low "ON" resistance: 80.0. (typ.) over entire 15Vp_p signal-input range for VOO-VEE= 15V
• High "OFF" resistance: channel leakage of ± 10 pA
(typ.) at VOO-VEE= 10V
iii Logic level conversion for digital addressing signals of
3-15V (Voo-Vss=3-15V) to switch analog signals to
15 Vp_p (Voo-VEE= 15V)
• Matched switch characteristics: 6.RON = 50. (typ.) for
VOO-VEE= 15V
• Very low quiescent power dissipation under all digitalcontrol input and supply conditions: 1 ",W (typ.) at
Voo-Vss=Voo-VEE= 10V
• Binary address decoding on chip
Dual·in·Line Packages
CD4052BM/CD4052BC
CD4053BM/CD4053BC
IN/OUT
5
~DUT/IN~
IN/OUT
IN/OUT
TOP VIEW
Oy
2v
y
Jv
ty
INiiiiiT DUTIIN IiiiOiiT
INH
VEE
Vss
TOP VIEW
TOP VIEW
Order Number CD4051 B', CD4052B', or CD4053B"
'Please look into Section B. Appendix D for availability of various package types.
See the CMOS Logic Databook for Complete Specifications
2-29
CJ1
N
III
o
o
c
........
Connection Diagrams
CD4051BM/CD4051BC
"'o"
TL/F/5662-1
"'o"
CJ1
Co)
III
s::
o
........
c
"'"
o
CJ1
Co)
III
o
•
o
m
~
o
...,
Q
o
......
II?'A National
~ Semiconductor
:::E
m
CD4066BM/CD4066BC Quad Bilateral Switch
CD
...,oCDQ
o
General Description
• Extremely low "OFF"
0.1 nA (typ.)
switch leakage
@ Voo-Vss=10V, TA=25°C
• Extremely high control input impedance
10120(typ.)
• Low crosstalk
-50 dB (typ.)
between switches
@ fis=0.9 MHz, RL =1 kO
• Frequency response, switch "ON"
40 MHz (typ.)
The CD4066BM/CD4066BC is a quad bilateral switch intended for the transmission or multiplexing of analog or digital signals. It is pin-for-pin compatible with CD4016BM/
CD4016BC, but has a much lower "ON" resistance, and
"ON" resistance is relatively constant over the input-signal
range.
Features
Applications
3V to 15V
• Wide supply voltage range
0.45 Voo (typ.)
• High noise immunity
• Wide range of digital and
±7.5 VPEAK
analog switching
800
• "ON" resistance for 15V operation
~RON=50 (typ.)
• Matched "ON" resistance
over 15V signal input
• "ON" resistance flat over peak-to-peak signal range
• High "ON"/"OFF"
65 dB (typ.)
output voltage ratio
@ fis = 10kHz, RL = 10 kO
• High degree linearity
0.1 % distortion (typ.)
High degree linearity
@ fis=1 kHz, Vis=5Vp_p ,
High degree linearity
Voo-Vss=10V, RL =10 kO
• Analog signal switching/multiplexing
• Signal gating
• Squelch control
• Chopper
• Modulator/Demodulator
• Commutating switch
• Digital signal switching/multiplexing
• CMOS logic implementation
.
• Analog-to-digital/digital-to-analog conversion
• Digital control of frequency, impedance, phase, and analog-signal-gain
Schematic and Connection Diagrams
IN/OUT
CONTROL
Order Number CD4066B*
'Please look into Section 8, Appendix D
for availability of various package types.
Dual-In-Line Package
See the CMOS Logic
Databook for Complete
Specifications
INIOUT 1
,--_+=-'3 CONTROL A
12 CONTROL 0
DUYflN
INIDUT
"
IN{OUT
10 OUT/IN
CONTROL B 5
CONTROL C ~-----,
vss
BIN/OUT
TL/F/5665-1
Top View
2-30
o
C
~National
0l:Io
U1
N
~ Semiconductor
co
m
s:::
"o
CD4529BM/CD4529BC Dual 4-Channel or Single
a-Channel Analog Data Selector
C
0l:Io
U1
N
co
m
General Description
Features
The CD4529B is a dual 4-channel or a single 8-channel
analog data selector, implemented with complementary
MOS (CMOS) circuits constructed with N- and P-channel
enhancement mode transistors. Dual 4-channel or 8-channel mode operation is selected by proper input coding, with
outputs Z and W tied together lor the single 8-bit mode. The
device is suitable lor digital as well as analog applications,
including various 1-01-4 and 1-01-8 data selector lunctions.
Since the device is analog and bidirectional, it can also be
used lor dual binary to 1-01-4 or single 1-01-8 decoder applications.
3.0V to 15V
• Wide supply voltage range
0.45 Voo (typ.)
• High noise immunity
0.005/JoW/package
• Low quiescent
power dissipation
(typ.)@5.0 Voc
• 10 MHz Irequency operation (typ.)
• Data paths are bidirectional
• Linear ON resistance [1200 (typ.)@15V]
• TRI-STATE® outputs (high impedance disable strobe)
a Plug-in replacement lor MC14529B
Connection Diagram
Logic Diagram
o
Dual-In-Line Package
Voa
STy
YO
VI
yz
Yl
W
z
X'
STx
XG
XI
lZ
v"
Xl
X,
l
TD'VIEW
Order Number CD4529B'
'Please look into Section 8, Appendix D
XZ
•
for availability of various package types.
STx STy B A
fII
,
Truth Table
Xl
Z
W
XO
Xl
X2
X3
VO
VI
V2
V3
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
XO
Xl
X2
X3
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
VO
VI
V2
V3
0
0
X X
}
Dual
4-Channel
Mode
2 Outputs
YO
"
"
Ylo-+--+++----+--'iC::::t--.
Single
8-Channel Mode
1 Output
(ZandW
tied together)
YlO"-I---1I--f-----I---+OH
YJO"----------I---+O......
High
Impedance
(TRI-STATE)
TL/F/5999-1
See the CMOS Logic Databook
for Complete Specifications
x = Don't care
2-31
~
c
,----------------------------------------------------------------------------,
~
,.. ~National
C')
U.
....I
~ Semiconductor
,..
,.. Quad SPST JFET Analog Switches
......
~
c
BI.FET II ™ Technology
~
U.
....I
......
,..
c
~
C')
,..
U.
....I
LF11331, LF13331 4 Normally Open Switches with Disable
LF11332, LF13332 4 Normally Closed Switches with Disable
LF11333, LF13333 2 Normally Closed Switches and 2 Normally Open Switches with Disable
LF11201, LF13201 4 Normally Closed Switches
LF11202, LF13202 4 Normally Open Switches
......
,.. General Description
c
,..
,..
~
U.
....I
......
C')
C')
C')
C')
,..
U.
....I
......
C')
C')
C')
,..
,..
Features
• Analog signals are not loaded
• Constant "ON" resistance for signals up to ± 10V and
100 kHz
• Pin compatible with CMOS switches with the advantage
of blowout free handling
• Small signal analog signals to 50 MHz
• Break-before·make action
tOFF < tON
-50 dB
• High open switch isolation at 1.0 MHz
<1.0 nA
• Low leakage in "OFF" state
• TTL, DTL, RTL compatibility
• Single disable pin opens all switches in package on
LF11331, LF11332, LF11333
• LF11201 is pin compatible with DG201
These devices are a monolithic combination of bipolar and
JFET technology producing the industry's first one chip
quad JFET switch. A unique circuit technique is employed to
maintain a constant resistance over the analog voltage
range of ± 10V. The input is designed to operate from mini·
mum TTL levels, and switch operation also ensures a break·
before-make action.
These devices operate from ± 15V supplies and swing a
± 10V analog signal. The JFET switches are designed for
applications where a dc to medium frequency analog signal
needs to be controlled.
U.
....I
(;;j
C')
C')
C')
,.. Test Circuit and Schematic Diagram
U.
....I
......
~
,..
,..
C')
INPUTfVAl
U.
....I
,..
U.
....I
o
IS
a......
INPUT V
IN
(LOGIC "0" < O.8VI
(LOGIC "I" > 2.0VI
v.l
I
r:l
.J ~ -::-
I
I
. L. -
......
,..
C')
I
C')
,..
,..
DI _ .~~
~
~I-::-
I
..!!.... I
lOGIC
......
,..
C')
C')
C')
r-------,
IA
ANAlOG-
EE
fV!!,. ti :!c,:-
I
I
__
I
R
.J
1_15v Icct +15V
TLlH/5667-2
FIGURE 1. Typical Circuit for One Switch
U.
....I
LOGIC
IN
VA
-VEE
FIGURE 2. Schematic Diagram (Normally Open)
2·32
TL1H/5667-12
r
"..........
Absolute Maximum Ratings
Supply Voltage (Vcc - VEE)
36V
Reference Voltage
VEE,;;VR';;VCC
Logic Input Voltage
VR -4.0V,;;VIN,;;VR + 6.0V
Analog Voltage
IiAI<20mA
Electrical Characteristics
Symbol
500mW
900mW
"ON" Resistance
- 65"C to + 150"C
.....
......
300"C
"..........
215"C
220"C
RON Match "ON" Resistance Matching
Analog Range
VA
Leakage Current in "ON" Condition
IS(ON) +
IDrON)
Source Current in "OFF" Condition
IS(OFF)
LF11331/2/3
LF11201/2
TA~25"C
mA
TA~25°C
Switch "ON,"
VS~VD~
±10V
Switch "OFF," Vs~ +10V,
VD~ -10V
Switch "OFF," Vs~ +10V,
VO~ -10V
TA~25"C
LF13331/2/3
LF13201/2 Units
150 250
150 200
200 350
200 300
5
20
10 50
±10 ±11
±10 ±11
0.3
5
0.3 10
3
30
3 100
TA~25°C
10(OFF)
Drain Current in "OFF" Condition
VINH
VINL
IINH
Logical "1" Input Voltage
Logical "0" Input Voltage
Logical "1" Input Current
VIN~5V
TA~25°C
IINL
Logical "0" Input Current
VIN~O.S
TA~25"C
tON
tOFF
tON-tOFF
CS(OFF)
CD(OFF)
CS(ON) +
CDION)
Delay Time "ON"
Delay Time "OFF"
Break-Belore-Make
Source Capacitance
Drain Capacitance
Active Source and Drain Capacitance
Vs~
± 10V, (Figure 3)
Vs ~ ± 1OV, (Figure 3)
Vs~ ±10V, (Figure 3)
Switch "OFF," Vs~ ±10V
Switch "OFF," VD~ ± 10V
Switch "ON," VS~VD~OV
TA~25"C
TA~25"C
ISO (OFF)
CT
SR
lOIS
"OFF" Isolation
Crosstalk
Analog Slew Rate
Disable Current
(Figure 4), (Note 4)
(Figure 4), (Note 4)
(Note 5)
(Figure 5), (Note 6)
TA~25°C
lEE
Negative Supply Current
All Switches "OFF,"
IR
Reference Supply Current
AIISwitches"OFF,"Vs~
±10V TA~25°C
Icc
Positive Supply Current
AIiSwitches"OFF,"Vs~
±10V
0.4
3
0.1
3
TA~25°C
5
100
5
100
2.0
TA~25"C
TA~25°C
TA~25°C
TA~25°C
TA~25°C
TA~25°C
TA~25°C
Vs~
± 10V
TA~25"C
TA~25"C
0.4
3
0.1
3
r
W
W
N
......
r
".....
3.6
3.6
2-33
r
......
O.S
40
100
0.1
1
V
V
/k A
J-'A
/k A
J-'A
ns
ns
ns
pF
pF
pF
-50
-65
50
0.4 1.0
0.6 1.5
-50
dB
-65
dB
50
V//ks
0.6 1.5 mA
0.9 2.3 mA
3.0
4.2
2.0
2.S
4.5
6.3
4.3 7.0 mA
6.0 10.5 mA
2.7 5.0 mA
3.S 7.5 mA
7.0 9.0 mA
9.S 13.5 mA
Note 5: This is the analog signal slew rate above which the signal is distorted as a result of finite internal slew rates.
Note 6: All sWitches in the deVice are turned "OFF" by saturating a transistor at the disable node as shown in Figure 5. The delay time will be approximately equal
to the tON or tOFF plus the delay introduced by the external transistor.
85'C/W
100'C/W
105'C/W
W
W
......
nA
nA
nA
nA
Note 4: These parameters are limited by the pin to pin capacitance of the package.
Note 8: 9JA (Typical) Thermal Resistance
r
"W..........
10
30
10
30
500
90
SO
4.0
3.0
5.0
Note 7: This graph indicates the analog current at which 1 % of the analog current is lost when the drain is positive with respect to the source.
......
".....
500
90
SO
4.0
3.0
5.0
5.0
7.5
4.0
6.0
6.0
9.0
W
W
N
V
nA
nA
2.0
O.S
10
25
0.1
1
.n
.n
.n
Note 1: Refer to RETSFI1201X, RETSFI1331X, RETSF11332X and RETSF11333X for military specifications.
Note 2: For operating at high temperature the molded DIP products must be derated based on a + 1ao°c maximum junction temperature and a thermal resistance
of + 150°C/W, devices in the cavity DIP are based on a + 150°C maximum junction temperature and are derated at ± 10QoC/W.
Note 3: Unless otherwise specified, vcc~ + 15V. VEE~ -15V. VR ~OV, and limits apply for -55'C"TA" + 125'C for the LFI1331/2/3 and the LF11201 /2.
-25'C~TA~ + 85'C for the LF13331 /2/3 and the LF13201 /2.
Molded DIP (N)
Cavity DIP (D)
Small Outline (M)
W
W
W
W
Conditions
VA~O, ID~1
".....
Storage Temperature
Min Typ Max Min Typ Max
RON
r
- 55"C to + 125"C
O"Cto +70"C
(Note 3)
Parameter
.....
......
Operating Temperature Range
LF11201, 2 and LF11331, 2, 3
LF13201, 2 and LF13331, 2, 3
Soldering Information
Nand D Package (10 sec.)
SO Package
Vapor Phase (60 sec.)
Infrared (15 sec.)
VEE,;;VA,;;VCC+ 6V;
VA,;;VEE+36V
Analog Current
W
W
Power Dissipation (Note 2)
Molded DIP (N Suffix)
Cavity DIP (D Suffix)
If Military/ Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
(Note 1)
W
W
W
W
r
"..........
N
o
.....
......
r
".....
W
N
o
.....
......
r
"..........
N
o
N
......
r
".....
~.
~
o
~
C")
....
r---------------------------------------------------------------------------------,
Connection Diagrams (Top View for SO and Dual-In-Line Packages) (All Switches Shown are For Logical "0")
I&.
....I
.....
~
o
LF11331/LF13331
IN.
04
IN,
Dl
LF11332/LF13332
53
IN.
D4
IN,
01
53
D3
52
02
........
....I
.....
....o
....
....I
.....
....
o
........
~
I&.
~
C")
I&.
~
I&.
....I
~
C")
51
VA
-VEE
52
D2
IN,
51
VA
-VEE
C")
C")
....
I&.
IN.
TUHf5667-13
TLfHf5667 -1
LF11333/LF13333
LF11201lLF13201
....I
.....
04
54
+Vee
01
51
-VEE
Ne
53
D3
52
02
C")
C")
C")
....
....
I&.
....I
.....
~
C")
C")
....
I&.
....I
.....
~
C")
C")
....
....
I&.
....I
.....
....
~
....
I&.
....I
.....
....
........
I&.
'IN,
Dl
51
VR
-VEE
52
D2
IN,
IN,
LF11202/LF13202
IN.
D4
54
IN,
TLfHf5667-15
TLfHf5667-14
C")
VA
Order Number LF13201D, LF11201D, LF13202D,
LF11202D,LF13331D,LF11331D,LF13332D,LF11332D,
LF13333D or LF11333D
See NS Package Number D16C
+Vee
Order Number LF13201M, LF13202M, LF13331M,
LF13332M or LF13333M
See NS Package Number M16A
C")
C")
....I
Order Number LF13201N, LF13202N, LF13331N,
LF13332N or LF13333N
See NS Package Number N16A
IN,
01
51
-VEE
VR
,IN.
TLfHf5667-16
2-34
Test Circuit and Typical Performance Curves
Delay Time, Rise Time, Settling Time, and Switching Transients
-1SV
+15V
v! ••~V
v.I •• ,'ov
vo
1\
\
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TLlH/5667-3
Additional Test Circuits
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TEMPERATURE ( CI
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ALL SWITCHES OFF
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!!!
lOD
ANALOG CURRENT (rnA)
z
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OUT'UT'UlSE
~
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Crosstalk and "OFF"
Isolation vs Frequency
Using Test Circuit
01 Figure 5
Switching Times
1200
10.
+Vcc" 15V. -VEE;; -15V
TIME MEASURED FROM
50% INPUT PULSE TO 90%
r--i"" It--,~
I
400
vee = 15V
I-- I - 1--.
TEMPERATURE f'C1
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"ON" Resistance
"ON" Resistance
"ON" Resistance
N
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2.'
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25
50
SUPPl Y VOLTAGE f' VI
50
TEMPERATURE ( C)
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20
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Current
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- -+---
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VEE" 15V
VIN =+50V
VR = OV
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TEMPERATURE
FREQUENCY 1Hz)
:/
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10
4" -16
-3
1M
r-.
VA (VOLTS)
lNOTE
Z
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~
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Maximum Accurate
Analog Current
vs Temperature
0
40
6.'
VA (VOLTS)
CL =3pF
!VI
ATTENUATION = 20 LOG f l
(SEE FIGURE 4)
A
;;
u
•.• 1-----'_----'_----'_----'_-'
150
-2'
60
,
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Small Signal Response
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5
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10
0.4
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10.
~'"
~-,~--~-~-.....,
TEMPERATURE ( C)
FREOUENCY IHd
Switch Capacitances
Switch Leakage CUrrent
Switch Leakage Currents
Supply Current
5'
~
~
100
r C)
4.' I-- I--
z
1'--
.........
I--- I-
2.'
ISO
-100
50
50
100
150
TEMPERATURE (' C)
TLlH/5667-5
2-36
r-
Application Hints
GENERAL INFORMATION
LEAKAGE CURRENTS
These devices are monolithic quad JFET analog switches
with "ON" resistances which are essentially independent of
analog voltage or analog current. The leakage currents are
typically less than 1 nA at 25'C in both the "OFF"and "ON"
switch states and introduce negligible errors in most applications. Each switch is controlled by minimum TTL logic
levels at its input and is designed to turn "OFF" faster than
it will turn "ON." This prevents two analog sources from
being transiently connected together during switching. The
switches were designed for applications which require
break-before-make action, no analog current loss, medium
speed switching times and moderate analog currents.
The drain and source leakage currents, in both the ON and
the OFF states of each switch, are typically less than 1 nA
at 25'C and less than 100 nA at 125'C. As shown in the
typical curves, these leakage currents are Dependent on
power supply voltages, analog voltage, analog current and
the source to drain voltage.
DELAY TIMES
The delay time OFF (tOFF) is essentially independent of
both the analog voltage and temperature. The delay time
ON (tON) will decrease as either (Vee-VA) decreases or
the temperature decreases.
Because these analog switches are JFET rather than
CMOS, they do not require special handling.
POWER SUPPLIES
The voltage between the positive supply (Veel and either
the negative supply (VEE) or the reference supply (VR) can
be as much as 36V. To accommodate variations in input
logiC reference voltages, VR can range from VEE to
(Vee~4.5V). Care should be taken to ensure that the power
supply leads for the device never become reversed in polarity or that the device is never inadvertantly installed backwards in a test socket. If one of these conditions occurs, the
supplies would zener an internal diode to an unlimited current; and result in a destroyed device.
LOGIC INPUTS
The logic input (IN), of each switch, is referenced to two
forward diode drops (1.4V at 25'C) from the reference supply (VR) which makes it compatible with DTL, RTL, and TTL
logic families. For normal operation, the logic "0" voltage
can range from O.BV to -4.0V with respect to VR and the
logic "1" voltage can range from 2.0V to 6.0V with respect
to VR, provided VIN is not greater than (Vee-2.5V). If the
input voltage is greater than (Vee -2.5V), the input current
will increase. If the input voltage exceeds 6.0V or -4.0V
with respect to VR, a resistor in series with the input should
be used to limit the input current to less than 100ILA.
When a switch is turned OFF or ON, transients will appear
at the load due to the internal transient voltage at the gate
of the switch JFET being coupled to the drain and source by
the junction capacitances of the JFET. The magnitude of
these transients is dependent on the load. A lower value RL
produces a lower transient voltage. A negative transient occurs during the delay time ON, while a positive transient
occurs during the delay time OFF. These transients are relatively small when compared to faster switch families.
Analog Voltage
Each switch has a constant "ON" resistance (RON) for analog voltages from (VEE+5V) to (Vee-5V). For analog voltages greater than (Vee-5V), the switch will remain ON independent of the logiC input voltage. For analog voltages
less than (VEE+5V), the ON resistance of the switch will
increase. Although the switch will not operate normally
when the analog voltage is out of the previously mentioned
range, the source voltage can go to either (VEE+36V) or
(Vee+6V), whichever is more positive, and can go as negative as VEE without destruction. The drain (D) voltage can
also go to either (VEE+36V) or (Vee+6V), whichever is
more positive, and can go as negative as (Vee-36V) without destruction.
DISABLE NODE
This node can be used, as shown in Figure 5, to turn all the
switches in the unit off independent of logic inputs. Normally, the node floats freely at an internal diode drop (::::0.7V)
above VR. When the external transistor in Figure 5 is saturated, the node is pulled very close to VR and the unit is
disabled. Typically, the current from the node will be less
than 1 mAo This feature is not available on the LF11201 or
LF11202 series.
Analog Current
5 mAl when the FET enters the saturation region. However, if the drain is positive with respect to
the source and a small analog current loss at high analog
currents (Note 6) is tolerable, a low RON can be maintained
for analog currents greater than 5 mA at 25'C.
r----I
I
} VDISA8Li: 'IV
TLlH/5667-6
FIGURE 5. Disable Function
2-37
W
W
W
w
W
N
.......
r-
...."TI
W
W
W
N
.......
r-
........"TI
w
w
w
.......
r-
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W
W
W
W
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r-
SWITCHING TRANSIENTS
ANALOG VOLTAGE AND CURRENT
........"TI
w
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.......
r"TI
....
....
.......
r........"TI
........
o....
.......
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N
W
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,---------------------------------------------------------------------------------,
Typical Applications
Sample and Hold with Reset
U.
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Programmable Inverting Non-Inverting Operational Amplifier
......
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Programmable Gain Operational Amplifier
U.
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r~---;;;;;;----l
"
10k
y--+","IIN...-,
1M
v,.
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r .......
-oVOUT
500k
GAIN SELECT
TL/H/5667-7
2-38
r-
"T1
......
Typical Applications
......
w
w
......
.......
(Continued)
Demultiplexer
r-
lOOk
"T1
......
W
W
W
Multiplexer/Mixer
......
.......
5,.
r-
"T1
......
......
w
W
N
.......
r-
"T1
......
W
W
W
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.......
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"T1
......
......
W
W
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.......
r-
"T1
......
W
W
W
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.......
r"T1
......
N
o
......
.......
r-
"T1
......
W
N
o......
.......
r-
8-Channel Analog Commutator with 6-Channel Select Logic
"T1
......
......
Ir--------,
N
o
N
.......
r-
Lf113Jl
0
ANALOG
INPUTS
o
(
o
o
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6CHANNH
SELECT lOGIC
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I
1-_ _ _ _ _ _ _ _+--+_.
,I
_
ANAlO~
INPUTS
"
(:
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11
o......:.:.tl-----<
tL...---_ _ _ _ _ _ _ --l
14
o--:.;
lF1IJ31
TL/H/5667 -8
2-39
N
~
(W)
.....
u..
r-----------------------------------------------------------------------------,
Typical Applications
(Continued)
..J
.......
N
o
N
.....
.....
u..
..J
.......
.....
o
N
(W)
.....
u..
..J
.......
.....
o
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.....
.....
u..
..J
.......
(W)
(W)
(W)
(W)
.....
u..
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.......
(W)
(W)
(W)
.....
.....
u..
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~
(W)
(W)
(W)
.....
Self-Zeroing Operational Amplifier
u..
D.41... f
..J
.......
N
(W)
(W)
.....
.....
u..
..J
.......
.....
(W)
(W)
(W)
.....
u..
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.......
.....
.....
.....
(W)
(W)
u..
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A..f---+:.......oo Vour
ZERO
INPUTS
JL ____~
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r---,,----l
TUH/5667-9
2-40
r-
Typical Applications
."
.....
.....
W
W
.....
.......
(Continued)
Programmable Integrator with Reset and Hold
n
n
r-
."
.....
W
W
W
v"o---"I",,"--,
.....
r--
SELECT
.......
r-
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o-l!f--[>--
N
.......
.....
.....
W
SELECT~
RESET
INTEGRATE _
W
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......
."
L~3~
W
W
W
N
11
.....
ANDHOLD~
14
.......
11
r-
."
.....
.....
~-_~--~VOUT
W
W
W
.......
r-
."
.....
Staircase Transfer Function Operational Amplifier
W
W
W
W
.......
r-
."
.....
.....
N
C
.....
.......
r-
."
.....
W
N
C
Av
.....
=-"-'+
RIr~
.......
RON
r-
."
.....
.....
N
C
N
v"
.......
r-
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~.
TLlH/5667-10
2-41
N ,-----------------------------------------------------------------------------,
o
N
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.....
Typical Applications
U.
...I
.....
N
(Continued)
DSB Modulator-Demodulator
o
C'I
.....
.....
.....
.....
U.
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o
fi'ft"
.....
r-
.....
.....
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C')
C')
MODULATOR
DEMODULATOR
TLlH/5667-11
.....
U.
...I
.....
N
C')
C')
.....
.....
U.
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.....
.....
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2-42
r-
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.....
Co)
~National
CJ'I
o
~ Semiconductor
BI·FET II ™ Technology
LF13508 8-Channel Analog Multiplexer
LF13509 4-Channel Differential Analog Multiplexer
co
......
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.....
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CJ'I
o
CD
General Description
The LF13508 is an 8-channel analog multiplexer which connects the output to 1 of the 8 analog inputs depending on
the state of a 3-bit binary address. An enable control allows
disconnecting the output, thereby providing a package select function.
This device is fabricated with National's BI-FET technology
which provides ion-implanted JFETs for the analog switch
on the same chip as the bipolar decode and switch drive
circuitry. This technology makes possible low constant
"ON" resistance with analog input voltage variations. This'
device does not suffer from latch-up problems or static
charge blow-out problems associated with similar CMOS
parts. The digital inputs are designed to operate from both
TTL and CM08 levels while always providing a definite
break-before-make action.
The LF13509 is a 4-channel differential analog multiplexer.
A 2-bit binary address will connect a pair of independent
analog inputs to one of any 4 pairs of independent analog
outputs. The device has all the features of the LF13508
series and should be used whenever differential analog inputs are required.
Features
•
•
•
•
•
•
•
•
•
•
JFET switches rather than CM08
No static discharge blow-out problem
No SCR latch-up problems
Analog Signal range 11V, -15V
Constant "ON" resistance for analog Signals between
-11V and 11V
"ON" resistance 380 n typ
Digital inputs compatible with TTL and CM08
Output enable control
Break-before-make action: toFF = 0.2 p.s; tON = 2 p.s typ
Lower leakage devices available
Functional Diagrams and Truth Tables
LF13508
A2
EN
AI
AD
-VEE
GND
Vee
sa
S7
S6
S4
S5
S3
S2
SI
EN
A2
A1
AO
SWITCH
ON
H
H
H
H
H
H
H
H
L
L
L
L
L
H
H
H
H
X
L
L
H
H
L
L
H
H
X
L
H
L
H
L
H
L
H
X
81
S2
S3
84
85
86
87
S8
NONE
LF13509
EN
AI
-VEE
GND
DB
S4B
S3B
S2B
SIB
S4A
S3A
SZA
SIA
DA
TL/H/5668-1
2-43
EN
A1
AO
L
H
H
H
H
X
X
L
L
H
H
L
H
L
H
SWITCH
PAIR ON
None
81
82
83
84
II
G)
o
II)
C")
Absolute Maximum Ratings
LL.
If MIlitary/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
36V
Positive Supply - Negative Supply (VCC-VEE)
..-
..J
.....
CO
oII)
C")
..-
LL.
..J
Positive Analog Input Voltage (Note 1)
Negative Analog Input Voltage (Note 1)
Vee
-VEE
Positive Digital Input Voltage
Negative Digital Input Voltage
Analog Switch Current
Power Dissipation (PD at 25'C)
(Notes 2 & 7)
Molded DIP (N)
500mW
PD
900mW
Cavity DIP (D)
PD
100'C
Maximum Junction Temperature (TjMAXl
Operating Temperature Range
O'C:S:TA:S: +70'C
Storage Temperature Range
-65'Cto + 150'C
Lead Temperature (Soldering, 10 sec.)
300'C
VCC
-5V
Ilsl<10 mA
Electrical Characteristics (Note 3)
Symbol
Parameter
LF13508
LF13509
Conditions
Min
RON
"ON" Resistance
VOUT=OV, Is=100 ",A
TA=25'C
aRON
aRON with Analog Voltage
Swing
-10V:S:VOUT:S: + 10V, Is= 100 ",A
TA=25'C
RON Match
RON Match Between Switches
VOUT=OV, Is=100 ",A
TA=25'C
IS(OFF)
Source Current in "OFF"
Condition
Switch "OFF", Vs=11, VD= -11,
(Note 4)
TA=25'C
ID(OFF)
Drain Current in "OFF"
Condition
Switch "OFF", Vs= 11, VD= -11,
(Note 4)
TA=25'C
Leakage Current in "ON"
Condition
Switch "ON" VD= 11V, (Note 4)
TA=25'C
ID(ON)
Typ
380
650
500
850
n
n
0.01
1
%
20
150
n
5
nA
50
nA
20
nA
500
nA
20
nA
500
nA
0.09
0.6
1
VINH
Digital "1" Input Voltage
VINL
Digital "0" Input Voltage
IINL
Digital "0" Input Current
VIN=O.7V
TA=25'C
IINL(EN)
Digital "0" Enable Current
VEN=0.7V
TA=25'C
Units
Max
2.0
V
0.7
V
1.5
30
",A
40
",A
1.2
30
",A
40
",A
tTRAN
Switching Time 01 Multiplexer
(Figure 1), (Note 5)
TA=25'C
1.8
",s
tOPEN
Break-Belore-Make
(FigureS)
TA=25'C
1.6
",s
tON(EN)
Enable Delay "ON"
(Figure 2)
TA=25'C
1.6
",s
tOFF(EN)
Enable Delay "OFF"
(Figure 2)
TA=25'C
0.2
",s
ISO(OFF)
CT
"OFF" Isolation
(Note 6)
TA=25'C
-66
dB
Crosstalk
LF13509 Series, (Note 6)
TA=25'C
-66
dB
CS(OFF)
Source Capacitance ("OFF")
Switch "OFF", VOUT=OV,
Vs=OV
TA=25'C
2.2
pF
CD(OFF)
Drain Capacitance ("OFF")
Switch "OFF", VOUT=OV,
Vs=OV
TA=25'C
Icc
Positive Supply Current
All Digital Inputs Grounded
TA=25'C
lEE
Negative Supply Current
All Digital Inputs Grounded
TA=25'C
11.4
pF
7.4
12
mA
7.9
15
mA
2.7
5
mA
2.8
6
mA
Note 1: II the analog input voltage exceeds this Iimi~ the input current should be limited to less than 10 rnA.
Note 2: The maximum power dissipation lor these devices must be derated at elevated temperatures and is dictated by TjMA)(, 8jA. and the ambient temperature,
TA. The maximum available power dissipation at any temperature is Po ~ (TIMAX - TAl/8jA or the 2S'C POMAX, whichever is less.
Note 3: These specifications apply lor VS= ± ISV and over the absolute maximum operating temperature range (TL,;:TA,;:TH) unless otherwise noted.
Note 4: Conditions applied to leakage tests insure worse case leakages. Exceeding II V on the analog input may cause an "OFF" channel to turn "ON".
Note 5: Lots are sample tested to this parameter. The measurement conditions of Figure 1 insure worse case transition time.
Note 6: "OFF" isolation is measured with all switches "OFF" and driving a source. Crosstalk is measured with a pair 01 swHches "ON", driving channel A and
measuring channel B. RL =200. CL =7 pF, Vs~3 Vrms, '~SOO kHz.
Note 7: Thermal Resistance 6jA (Junction to Ambient)
Molded DIP (N)
ISO'C/W
Cavity DIP (D)
100'C/W
2-44
r-
....
c.:I
-n
Connection Diagrams
CJ1
Q
LF13508
Dual·ln·Llne Package
T
Al
GND
AZ
16
15
vee
14
55
Il
S6
SI
11
lZ
Al
58
10
9
GND
116
Vee
14
15
SIB
SZ8
lZ
13
SlB
548
11
Z
1
EN
1
-VEE
4
SI
5
I8
1
6
SZ
Sl
S4
AD
9
c.:I
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LF13509
Dual·ln·Line Package
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TOP VIEW
1
4
5
6
1
-VEE
SIA
SZA
5lA
S4A
r
DA
TOP VIEW
TLlH/56eS-2
Order Number LF13508D
See NS Package Number D16C
Order Number LF13508N
See NS Package Number N16A
Order Number LF13509D
See NS Package Number D16C
Order Number LF13509N
See NS Package Number N16A
AC Test Circuits and Switching Time Waveforms
Vee
2Vo- EN
?-
A2
51
52-S1
LF13508
58
f-o 10V
f-o -10V -::!:-
. ~ &-::I.-:b=-i':'r=----r:-.~.'"
Dt-C>-.........,
~::~~ n
':'
GND
~
-l
-VEE
50
-15V
10M
0.8 VS8
l-ITRAN
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TLlH/566S-3
FIGURE 1. Transition Time
2·45
til
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AC Test Circuit and Switching Time Waveforms (Continued)
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VOUT
lOGIC
INPUT
INPUT
DRIVE
3V~
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'-TL/H/5666-4
FIGURE 3. Break-Before-Make
Transition Times and Transients
VA=10V
VA=5V
V,N
V,N
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GNO
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Vo
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TL/H/566B-7
TLlH/566B-B
Test Circuit
ISV
GND
VCC
SI
LF135D8
SB~:>-...,
-ISV
lpS/DIV
TLiH/BB6B-l0
TLlH/566B-9
2-46
.-
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Typical Performance Characteristics
U1
"ON" Resistance
"ON" Resistance
800
400
E
Ez
3&0
..
VCC" 15V
VEE' -15V
IA'O
TA"25'C
320
300
6
100
-55 -35 -IS 5 25 45 &5 85 IDS 125
1
~
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IO(OrFI
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ill
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z
f::
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f-
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l-
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f::
f::f-
f-
35
85
95
125
-55
-25
35
f-
Bias Currents
Vcc ·15V
VEE"-15V VLOGIC -OV
\
......
~~PLY
........
lEN
~
w
z"
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I ' ...... .......... .......
!::
...... ......
-ISUPPLY
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-25
35
65
TEMPERATURE ('CI
95
125
10M
~
:l
24
22
20
18
18
14
12
10
8
COlON I
COIOFFI
CS(OFFI
2
o
-S5
1M
Switch Capacitances
I
.... ~
lOOk
FREOUENCY (H.I
Supply Currents
10
t\.
lD1t
125
TEMPERATURE I'CI
3
1\ \
is
65
Ell
~
-100
-110
TEMPERATURE ('CI
125
-50
'OFFEN-
-55 -25
95
-40
'ONEV
0.5
65
-30
l/
;;;
~V
35
"OFF" Isolation and
Crosstalk
"'5~
vJc
I-YEE --15V
-25
TEMPERATURE rCI
Enable Delay Times
(Figure 2)
- 'TRA~ "'/
'OPEN
:l
w
10
-5
ANALOG VOLTAGE (VI
SW.itching Times
(Figures 1 and 3)
-VEE'-1SV
I
~
0.1
0.01
-IS -10
ANALOG VOLTAGE (VI
3.5
n
-IO(OFFI '"h'.
'"
IS OFFI
10
10
-5
10(ONI
w
1:
-0.1
H
10
.=~
10(ONI
_-IO(OFFI
100
Switch Leakage
Currents
100
10:ONI
~
-I
ANALOG INPUT CURRENT (mAl
-I
~
-2
Switch Leakage
Currents
1000
ISIOFFI
-10
+~-
200
TEMPERATURE I'CI
0.1
-IS
CD
a:~ 300
100
8 10
Switch Leakage
Currents
VCC'15V
I-vEE ·-1SV
TA • 25'C
8
o
200
ANALOG INPUT VOLTAGE IVI
.~
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400
0
300
-10 -8 -8 -4 -2 0 2 4
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600 I-VEE' -15V
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1
100
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100
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"ON" Resistance
o
-55 -25
35
85
TEMPERATURE rCI
95
125
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ANALOG VOLTAGE (VI
TLlH/566B-l I
2-47
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Application Hints
The LF11508 series is an 8-channel analog multiplexer
which allows the connection of a single load to 1 of 8 different analog inputs. These multiplexers incorporate JFETs in
a switch configuration which insures a constant "ON" resistance over the analog voltage range of the device. Four TTL
compatible inputs are provided; a 3-bit binary decode to select a particular channel and an enable input used as a
package select. The switches operate with a break-beforemake action preventing the temporary connection of ,2 analog inputs during switching. Because these multiplexers are
fabricated with the BI-FET process rather than CMOS, they
do not require special handling.
LEAKAGE CURRENTS
Leakage currents will remain within the specified value as
long as the drain and source remain within the specified
analog voltage range. As the switch terminals exceed the
positive analog voltage range "ON" and "OFF" leakage
currents increase. The "ON" leakage increases due to an
internal clamp required by the switch structure. The "OFF"
leakage increases because the gate to source reverse bias
has been decreased to the point where the switch becomes
active. Leakage currents vary slightly with analog voltage
and will approximately double for every 10°C rise in temperature.
The LF11509 series is a 4-channel differential multiplexer
which allows two loads to be connected to 1 of 4 different
pairs of analog inputs. The LF11509 series also has all the
features of the LF11508.
SWITCHING TIMES AND TRANSIENTS
These multiplexers operate with a break-before-make
switch action. The turn off time is much faster than the turn
on time to guarantee this feature over the full range of analog input voltage and temperature. Switching transients are
introduced when a switch is turned "OFF". The amplitude of
these transients may be reduced by increasing the load capacitance or decreasing the load resistance. The actual
charge transfer in the transient may be reduced by operating on reduced power supplies. Examples of switching times
and transients are shown in the typical characteristic
curves. The enable function switching times are specified
separately from switch-to-switch transition times and may
be thought of as package-to-package transition times.
ANALOG VOLTAGE AND CURRENT
The "ON" resistance, RON, of the analog switches is constant over a wide input range from positive (Veel supply to
negative (- VEE) supply.
The analog input should not exceed either positive or negative supply without limiting the, current to less than 10 mA;
otherwise the multiplexer may get damaged. For proper oP7
eration, however, the positive analog voltage should be kept
equal to or less than Vee - 4V as this will increase the
switch leakage in both "ON" and "OFF" state and it may
also cause a false turn "ON" of a normally "OFF" switch.
This limit applies over the full temperature range.
The maximum allowable switch "ON" voltage (the drop
across the switch in the "ON" condition) is ± O.4V over temperature. If this number is to exceed the input current should
be limited to 10 mA.
LOGIC INPUTS AND ENABLE INPUT
Switch selection in the LF11508 series is accomplished by
using a 3-bit binary decode while the LF11509 series uses a
2-bit decode. These binary logic inputs are compatible with
both TTL and CMOS logic voltage levels. The maximum
positive voltage applied to these inputs may exceed Vee but
should not exceed -VEE+36V. The maximum negative
voltage should not be less than 4V below ground as this will
cause an internal device to zener and all the switches will
turn "ON".
As shown in the schematic diagram, the logic low bias current will flow until the PNP input is raised above the 3 diode
reference (::::: 2.1 V). Above this voltage the input device becomes reverse biased and the input current drops to the
leakage of the reverse biased junction « 0.1 /LA).
The "ON" resistance of the multiplexing switches varies
slightly with analog current because they are JFETs running
at OV gate to source. The JFET characteristics shown in
Figure 4 indicates how'RON tends to vary with current. A
lower RON is possible when the source voltage is negative
with respect to the drain voltage because the JFET becomes enhanced. Caution should be used when operating
in this mode as this may forward-bias an internal transistor
and cause high currents to flow in the switches. Thus, the
drain voltage should never be greater than O.4V positive
with respect to the source voltage without limiting the drain
current to less than 10 mA.
p
s
1.6
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cc
1.2
3.6
1.8
C
.!
0
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Vso
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0.8
-
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-2
II"
L
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I
-3.6
-1
-2
Vso (V)
J..oo'
II'
-1
Vso (VI
TL/H/5668-12
FIGURE 4. JFET Characteristics
2-48
r-
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Typical Applications
U1
o
DATA ACQUISITION SYSTEM
A SIMPLIFIED SYSTEM DISCUSSION
Analog multiplexers (MUX) are usually used for multi-channel Data Acquisition Units (DAU). Figure 5 shows a system
in which 8 different analog inputs are sampled and converted into digital words for further processing. The sample and
hold circuit is optional, depending on input speed requirements and on AID converter speed.
Accuracy: The conversion accuracy of each individual sample with the system operating at the throughput rate.
A. ACCURACY CONSIDERATIONS
1. Multiplexer's Influence on System Accuracy (Figure 6).
a. The error, (E), caused by the finite "ON" resistance, RON, of the multiplexing switches is given
by:
100
Rs
+
where:
aRON)
aRON = "ON" resistance modulation which is
negligible for JFET switches like the LF11508
Example: Let RON = 450 .n, aRON = 0, Rs = 0, TA
= 25'C and allowable E = 0.01 % which is equivalent
to 1/2 LSB in a 12-bit system:
I
min
BITS
0.2
0.05
0.01
0.0008
8
10
12
16
6.2t
7.6t
9t
11.8t
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......
Co)
U1
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CD
+ Rs) II RIN
The sample and hold, if used, also introduces errors into
the system accuracy due to:
• Offset voltage of sample and hold
• Droop rate in the Hold mode
• T A: Aperture time or time delay between the time of a
digital Hold command and the actual Hold occurance
• Taq: Acquisition time or time it takes to acquire an
analog input and settle within a predetermined error
band
• Hold step: Error created during the Sample to Hold
mode caused by an undesirable charge injected into
the Hold capaCitor Ch.
For more details on sample and hold errors, see the
LF198/LF298/LF398 data sheet.
3. AID Converter Influence on System Accuracy
RIN = following stage input impedance
RIN
ERROR %
ts(OFF): is the time it takes to discharge Cs within
a tolerable error. The "OFF" settling time should
be taken into account for bipolar inputs where its
effects will appear as a worse case of doubling
of the ts(ON).
2. Sample and Hold Influence on System Accuracy
For a discussion on system structure, addressing mode and
processor interfacing, see application note AN-159.
+ RIN/(RON +
r-
ts(ON)
TO 1I2LSB
t = Cs (RON
Speed or Throughput Rate: Number of samples/secondl
channel the system can handle.
1
......
TABLE!.
Parameters characterizing the system are:
System Channels: The number of multiplexer channels.
E(%) =
CD
The "accuracy" of the AID converter is the best possible
system accuracy. In most data acquisition systems, the
AID converter is the most expensive single component,
so its error will often dominate system error. Care should
be taken that MUX, S/H and input source errors do not
exceed system error requirements when added to AID
errors. For instance, if an 8-bit accuracy system is desired
and an 8-bit AID converter is used, the accuracy of the
MUX and 8/H should be far better than 8 bits.
For details on AID converter specifications, see AN-156.
= RON(100 - E) = 4.5 M.n
E
Note that if temperature effects are included, some
gain (or full scale) drift will occur; but effects on linearity
are small.
b. Multiplexer settling time (ts):
ts(ON): is the time required for the MUX output to
settle within a predetermined accuracy, as
shown in Table I.
Cs (Figure 6): MUX output capacitance + following stage input capacitance + any stray capacitance at this node.
} ,BlTSWDRD
CONVERSION COMPLETE
TUH/566B-13
FIGURE 5. Random-Addressed, Multiplexed DAU
FIGURE 6. a-Channel MUX
2-49
•
Typical Applications (Continued)
where TA is the aperture time of the S/H. This represents an input slew rate improvement by a factor: Tc/
TA. Here again, the slew rate error is not affected by
the acquisition time of the Sample and Hold since conversion will start after the S/H has settled. An important thing to notice is that the sample and hold errors
will add to the total system error budget; therefore, the
inequality of the .0. V,NI'.o.t expression should become
more stringent.
B. SPEED CONSIDERATIONS
In the system of Figure 5 with ttie S/H omitted, if n-bit accuracy is desired, the change of the analog input voltage
should be less than ± 1 /2 LSB over the AID conversion
time Tc. In other words, the analog input slew rate, (rate of
change of input voltage), will cause a slew-induced error
and its magnitude, with respect to the total system error, will
depend on the particular application.
I
b.VIN
b.t max
<
Example: TC = 40 /Ls, TA = 0.5 /Ls, n = 8: Tc/TA = 80
So the use of a S/H allows a speed improvement by
nearly two orders of magnitude.
The maximum throughput rate can be calculated by:
±1/2 LSB = ~
TC
2n X TC
where VFS is the full scale voltage of the AID. Note that
slew induced errors are not affected by the MUX switch time
since we can let the unit settle before starting conversion.
Th. R
=
8.
I
b.VIN
b.t max
< 1mV
,...S
C. SYSTEM EXAMPLE (Figure 7)
The LF398 S/H with a 1000 pF hold capacitor, has an acquisition time of 4 /Ls to 0.1 % (1/4 LSB error for 8 bits) and
an aperture time of less than 200 ,...S. On the other hand,
after the hold command, the output will settle to ±0.05 mV
in 1 ,...S. This, together with the acquisition time, introduces
approximately a ± 1/4 LSB error. Allowing another 1/4 LSB
error for hold step and gain non-linearity, the maximum slew
error (.0.VIN/ .o.t) should not exceed 1/4 LSB or:
which is a very small number. A 10 Vp-p sine wave of a
frequency greater than 32 Hz will have higher slew rate
than this. The maximum throughput rate of the above 8channel system would be calculated using both the AID
conversion time and the sum of MUX switch "ON" time
and settling time, i.e.:
Th. R
,
I
max
=
TMUX = TON
8(T 1 T
)
C + MUX
=
3k samples/sec/
channel
b.VIN 1
- s: - X - 1
1
X ""5mV/",s
b.t
4 256 TA
(which is the maximum slew rate of a 5 V peak sine wave.
Also notice that, due to the above input slew restrictions,
the analog delay caused by the finite BW of the S/H and the
digital delay caused by the response time of the controller
will be negligible. The maximum throughput rate of the system is:
+ TS(ON)
Also notice that Nyquist sampling criteria would allow
each channel to have a signal bandwidth of 1.5 kHz max,
while the slew limit dictates a maximum frequency of 32
Hz. If the input signal has a peak-to-peak voltage less
than 10V, the allowable maximum input frequency can be
calculated by:
f
Th. R Imax
_ (Slew Rate)max
MAX 7TVp-p
1. Improving System Speed with a Sample and Hold
The system speed can be improved by using the
S/H shown in Figure 5. This allows a much greater
rate of change of VIN.
b.VIN
I
8(5
+ ~0)10-6 =
2800 samples/sec/ch.
If the system speed requirements are relaxed, but the AID
converter is still too slow, then an inexpensive S/H can be
built by using just a capaCitor and a low cost FET input op
amp as shown in Figure 8.
On the other hand, if the input voltage is not band-limited a
low pass filter with an attenuation of 30 dB or better at 1.5
kHz, should be connected in front of the MUX.
Tt
Imax =
1
8(TA + Taq + Tel
Notice that TMUX does not affect the .0.VIN/.o.t expression
nor the throughput rate of the system since it may be
switched and settled while the Sample and Hold is in the
Hold mode. This is true, provided that: T MUX < TA + TC.
Example: Let T C = 40 ,...s (MM4357), VFS = 10V and n
VFS
max <2 n XTA
2-50
r-
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.....
Typical Applications (Continued)
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15V
1&
15
AI
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EOC: End of Conversion
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LF1350B
2.4k
SC: Start Conversion
-12V
1"'1-4_ _ _"'O~~~~!NPUT
~~~~~~~~~~
II
FIGURE 7a. Sequentially Multiplexed DAU with Sample and Hold
ruuUUUUUUUlIlIUllUlnnnn.n1UlJlruUWU't11l1IlIlMf .
"0"
--,L...______II~L...__---Ir'1L...__---Ir'1. . .______IrL
L...-_-I,J
S/H--1
se _ _ _ _ _.....~~~,
nee
L-J
---I11
eLKEN _ _ _ _
r'
Ao _ _ _ _ _ _ _....
AI _ _ _ _ _ _ _ _
A2 _ _ _ _ _ _ _ _
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'----__11
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L...,-,'"--___. . . . .r.
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ll
1I
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~L-_
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•
TL/H/5668-14
FIGURE 7b. Timing Diagram
2-51
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It)
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CO)
LA.
....I
Typical Applications
(Continued)
An alternate way to increase the system channel is shown
in Figure 10, where the enable pins are used to disable one
MUX while the other is sampling. With this method, many 8channel multiplexers can be connected, but the parasitic
capacitance at the common output node will keep increasing and will eventually degrade the settling time, ts(ON)'
Also, the MUX speed will now affect the system throughput.
If, for instance, this method was used instead of second
level multiplexing, the system of Figure 9 will lose half of its
speed. If, however, speed is not the prime system requirement, the approach of Figure 10 is more cost effective.
D. DOUBLING THE SYSTEM CHANNEL CAPABILITY
This is done in two different ways. First, we can use second
level multiplexing with speed benefits, as shown in Figure 9.
A fast 2-channel multiplexer, made by the dual analog
switch AM182, accepts the outputs of each 8-channel MUX,
LF13508, and then feeds them sequentially into an 8-bit
successive approximation AID converter. With this technique, the throughput rate of the system can again be made
independent of the LF13508 speed. Looking at the timing
diagram, when the AID converter converts the analog value
of an upper multiplexer channel, we switch channels in the
lower multiplexer for the next conversion. This can be done
provided that:
E. DIFFERENTIAL INPUT SYSTEMS
Systems operating in industrial environments may require
an instrumentation amplifier to separate the desired analog
signal from any common-mode signal present. The
LF11509 was deSigned to provide 4 pairs of differential input signals to the input of an instrumentation amplifier for
further process. A 4-channel preconditioning circuit is
shown in Figure 11 and a complete system is shown in Figure 12.
TMUX ,;; Tc + 1 CP
The LF356 connected as unity gain buffers are used because of the low input impedance of the AID; they are connected between multiplexers for speed optimization. With a
maximum clock frequency of 4.5 MHz:
Th. R
=
106
16 x 2
=
31.25ksamples/sec/channel
and
Il.VIN I
10
1
Tt
max < 256 X 2,...s =
19.5 mV/,...s for 10VFS
15V
-15V
-
-
"'TDA/D
LF1350B
SAMPLE--,
i
EN
HDLD--W
AD
At
A2
CHANNEL SELECT
TUH/566B-15
• The acquisition time, TA, of the Sample and Hold depends upon: RON, loss of swttches. ZOUT of switches
• loss '" 1.5 mA, ZOUT ~ 40 kG
.VIN~IOV, Ch~IOOO
pF,
TA~20
"s to 0.1%
• Error created by charge iniection during Hold mode: IlVE'" 10 pF (14.5V-VIWICh
FIGURE 8. Inexpensive Sample and Hold
2-52
r-
Typical Applications
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(Continued)
(J1
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r------~-----------l
15V
I
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-15V
5V
I
15V
-15V
Co)
(J1
oU)
I
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52
_ ___
~~~~
------,
r-------DCO
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DM2502
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MS.O:-==::.:...jf----.
15V
5V
3.9M
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D.01/.lF":"
.".
-15V
I
______
_
_
_
_
_
_
_
_
_
_
_
_
_
_
15V
-15V
B.8IT S.A. AID
~
FIGURE 9a. A Fast 16-Channel DAU with Second Level Multiplexing
..J1JUlnIUUUlfUlfln.Il.flJUUUlnIUtnnmUWUl
CLK
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AO
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3.
U
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IL
TLlH/5668-16
FIGURE 9b. Timing Diagram
2·53
en ,---------------------------------------------------------------------------------,
o
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....
U.
...I
........
Typical Applications
(Continued)
l!iV
-15V
CO
o
Ln
....U.
C")
...I
....~O-<....OTO S/" OR AID
10
'5
":'"
MM74C193
,5V
-15V
TL/H/5668-17
FIGURE 10. A 16-Channel Multiplexer with Sequential Multiplexing
2-54
· Schematic Diagrams
LF13508
------~-.----_+--t_----+_~--------~~~
2·55
en
c
In
,...
C')
Schematic Diagrams (Continued)
LF13509
LL.
...I
.......
CX)
C
In
,...
C')
LL.
...I
Q
Z
I.
---------------f--t-----t--r----------~~
2-56
.-------------------------------------------------------------,~
~
~National
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MM54HC40 16/MM74HC40 16
Quad Analog Switch
~
~
....,
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General Description
Features
These devices are digitally controlled analog switches implemented in advanced silicon-gate CMOS technology.
These switches have low "on" resistance and low "off"
leakages. They are bidirectional switches, thus any analog
input may be used as an output and vice-versa. The '4016
devices allow control of up to 12V (peak) analog signals
with digital control signals of the same range. Each switch
has its own control input which disables each switch when
low. All analog inputs and outputs and digital inputs are protected from electrostatic damage by diodes to Vee and
ground.
•
•
•
•
•
•
Connection Diagram
Truth Table
o
~
Typical switch enable time: 15 ns
Wide analog input voltage range: 0-12V
Low "on" resistance: son typo
Low quiescent current: 80 /LA maximum (74HC)
Matched switch characteristics
Individual switch controls
...
Q
0)
Dual-In-Line Package
Vee
1CTL
4CTL
41/0
40/1
30/1
31/0
8
10/1
20/1
21/02CTL
3CTL
Switch
CTL
1/0-0/1
L
H
"OFF"
liON"
See the CMOS Logic Databook
for complete specifications
7
11/0
Input
GNo
TL/F/5350-1
II
Top View
Order Number MM54HC4016* or MM74HC4016*
·Please look into Section 8, Appendix D
for availability of various package types.
Schematic Diagram
TLlF/5350-2
2-57
~
11)
o
o:t
o
:::E:
~
::E
::E
.....
,----------------------------------------------------------------------------,
J?'A National
~ Semiconductor
MM54HC4051/MM74HC4051
8-Channel Analog Multiplexer
o
o:t
o MM54HC4052/MM74HC4052
:::E:
o:t
Dual 4-Channel Analog Multiplexer
::E
::E
MM54HC4053/MM74HC4053
.....
C'\I
o Triple 2-Channel Analog Multiplexer
o:t
~
11)
11)
11)
o
:::E:
o:t
.....
::E
::E
.....
C'\I
11)
o
o:t
o
:::E:
o:t
11)
::E
::E
......
....
11)
o
o:t
o
:::E:
o:t
.....
::E
::E
.....
....
11)
o
o:t
o
:::E:
o:t
11)
::E
::E
General Description
a pair of 4-channel multiplexers. The binary code placed on
the A, and B select lines determine which switch in each 4
channel section is "on", connecting one of the four inputs in
each section to its common output. This enables the implementation of a 4-channel differential multiplexer.
These multiplexers are digitally controlled analog switches
implemented in advanced silicon-gate CMOS technology.
These switches have low "on" resistance and low "off"
leakages. They are bidirectional switches, thus any analog
input may be used as an output and vice-versa. Also these
switches contain linearization circuitry which lowers the on
resistance and increases switch linearity. These devices allow control of up to ± 6V (peak) analog signals with digital
control signals of 0 to 6V. Three supply pins are provided for
Vee, ground, and VEE. This enables the connection of 0-5V
logic signals when Vee = 5V and an analog input range of
± 5V when VEE = 5V. All three devices also have an inhibit
control which when high will disable all switches to their off
state. All analog inputs and outputs and digital inputs are
protected from electrostatic damage by diodes to Vee and
ground.
MM54HC4051/MM74HC4051: This device connects together the outputs of 8 switches, thus achieving an 8 channel Multiplexer. The binary code placed on the A, B, and C
select lines determines which one of the eight switches is
"on", and connects one of the eight inputs to the common
output.
MM54HC4052/MM74HC4052: This device connects together the outputs of 4 switches in two sets, thus achieving
MM54HC4053/MM74HC4053: This device contains 6
switches whose outputs are connected together in pairs,
thus implementing a triple 2 channel multiplexer, or the
equivalent of 3 single-pole-double throw configurations.
Each of the A, B, or C select lines independently controls
one pair of switches, selecting one of the two switches to be
lion".
Features
• Wide analog input voltage range: ± 6V
• Low "on" resistance: 50 typo (Vec-VEE=4.5V)
30 typo (Vee-VEE=9V)
• Logic level translation to enable 5V logic with ± 5V
analog signals
• Low quiescent current: 80 /LA maximum (74HC)
• Matched Switch characteristic
Connection Diagrams
Dual-In-Line Packages
IN/OUT
Vee
Y2
Yl
YO
V3
~OUTIIN~
vcczx
A
IX
1
4
Y6 OUTIIN Y1
INiOuT
Y5
INiOuT
ox
INH
VEE
OT
2T
T
3T
5
lY
INiiiiiT OUTIIN INiiiiiT
TLiF/5353-1
Top View
3X
IN/OUT
A
Vee
'AT
AX
INH
I.
VEE
TL/F/5353-2
Top View
TLlF/5353-3
Top View
Order Number MM54HC4051* , MM74HC4051*, MM54HC4052',
MM74HC4052*, MM54HC4053' or MM74HC4053*
'Please look Into Section 8, Appendix 0 for availability of various package types.
See the CMOS Logic Oatabook for Complete Specifications
2-58
A
'HC4053
'HC4052
'HC4051
Y4
X
~National
~ Semiconductor
MM54HC4066/MM74HC4066
Quad Analog Switch
General Description
Features
These devices are digitally controlled analog switches utilizing advanced silicon-gate CMOS technology. These
switches have low "on" resistance and low "off" leakages.
They are bidirectional switches, thus any analog input may
be used as an output and visa-versa. Also the '4066
switches contain linearization circuitry which lowers the
"on" resistance and increases switch linearity. The '4066
devices allow control of up to 12V (peak) analog signals
with digital control signals of the same range. Each switch
has its own control input which disables each switch when
low. All analog inputs and outputs and digital inputs are protected from electrostatic damage by diodes to Vee and
ground.
•
•
•
•
•
•
Connection Diagram
Truth Table
Typical switch enable time: 15 ns
Wide analog input voltage range: 0-12V
Low "on" resistance: 30 typo (,4066)
Low quiescent current: 80 ,.,A maximum (74HC)
Matched switch characteristics
Individual switch controls
Dual-In-Line Package
Vee
11/0
lCTL
10/1
4Cn
20/1
41/0
21/0
40/1
2CTL
30/1
3CTL
31/0
Input
Switch
CTL
1/0-0/1
L
H
"OFF"
"ON"
See the CMOS Logic Databook
for Complete Specifications
GND
TL/F/5355-1
Top View
Order Number MM54HC4066* or MM74HC4066*
'" Please look into Section 8, Appendix D
for availability of various package types.
Schematic Diagram
0/1
CONTROL
TL/F/S355-2
2-59
~National
~ Semiconductor
MM54HC4316/MM74HC4316
Quad Analog Switch with Level Translator
General Description
Features
These devices are digitally controlled analog switches implemented in advanced silicon-gate CMOS technology.
These switches have low "on" resistance and low "off"
leakages. They are bidirectional switches, thus any analog
input may be used as an output and vice-versa. Three supply pins are provided on the '4316 to implement a level
translator which enables this circuit to operate with 0-6V
logic levels and up to ±6V analog switch levels. The '4316
also has a common enable input in addition to each switch's
control which when low will disable all switches to their off
state. All analog inputs and outputs and digital inputs are
protected from electrostatic damage by diodes to Vee and
ground.
• Typical switch enable time: 20 ns
• Wide analog input voltage range: ±6V
• Low "on" resistance: 50 typo (VCC-VEE=4.5V)
30 typo (VCC-VEE=9V)
• Low quiescent current: 80 /LA maximum (74HC)
• Matched switch characteristics
• Individual switch controls plus a common enable
Connection and Logic Diagrams
Truth Table
Dual-In-Line Package
tClL 4ClL 41fo 40fl 30fl
2CTL 3CTL
Inputs
31fO
En
Switch
En
CTL
1/0-0/1
H
L
L
X
"OFF"
"OFF"
"ON"
L
H
See the CMOS Logic Databook
for Complete Specifications
UNO
Tl/F /5369-1
Top View
Order Number MM54HC4316* or MM74HC4316*
'Please look into Section e, Appendix 0
for availability of various package types.
.....-......-OOfl
ClL
......._~J
o------II~"'_
Iii 0--1 :».......
TliF/5369-2
2-60
Section 3
Analog-to-Digital
Converters
&I
Section 3 Contents
Analog-to-Digital Converters Definition of Terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .
Analog-to-Digital Converters Selection Guide ..........................................
ADC0800 8-Bit AID Converter.......... ...... .... . . . ....... .. ... ....... ... . ...... . . .
ADC0801 I ADC08021 ADC08031 ADC08041 ADC0805 8-Bit /LP Compatible AID Converters . .
ADC08081 ADC0809 8-Bit /LP Compatible AID Converters with 8-Channel Multiplexer. . . . . . .
ADC0811 8-Bit Serial 1/0 AID Converter with 11-Channel Multiplexer. . . . . . . . . . . . . . . . . . . . .
ADC0816/ADC0817 8-Bit /LP Compatible AID Converters with 16-Channel Multiplexer......
ADC0819 8-Bit Serial 1/0 AID Converter with 19-Channel Multiplexer. . . . . . . . . . . . . . . . . . . . .
ADC0820 8-Bit High Speed /LP Compatible AID Converter with Track/Hold Function. . . . . . . .
ADC0829 /LP Compatible 8-Bit AID with 11-Channel MUX/Digitallnput. . . . . . . . . . . . . . . . . . . .
ADC0831 I ADC08321 ADC0834 and ADC0838 8-Bit Serial 1/0 AID Converters with
Multiplexer Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC0833 8-Bit Serial 1/0 AID Converter with 4-Channel Multiplexer. . . . . . . . . . . . . . . . . . . . . .
ADC0841 8-Bit /LP Compatible AID Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC08441 ADC0848 8-Bit /LP Compatible AID Converters with Multiplexer Options . . . . . . . . .
ADC08521 ADC0854 Multiplexed Comparators with 8-Bit Reference Divider. . . . . . . . . . . . . . . .
ADC1 001 I ADC1 021 1O-Bit /LP Compatible AID Converters. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ADC1 0051 ADC1 025 1O-Bit /LP Compatible AID Converters. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ADC12051 ADC1225 12-Bit Plus Sign /LP Compatible AID Converters . . . . . . . . . . . . . . . . . . . ..
ADC121 01 ADC1211 12-Bit CMOS AID Converters .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC3511 3%-Digit Microprocessor Compatible AID Converter. . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC3711 3%-Digit Microprocessor Compatible AID Converter. . . . . . . . . . . . . . . . . . . . . . . . . . .
ADD3501 3%-Digit DVM with Multiplexed 7-Segment Output. .. . .. .. .. .... .. ... .. .. ... ...
ADD3701 3%-Digit DVM with Multiplexed 7-Segment Output. .. . .. .... .... .. ... .. ... .. ...
DM2502/DM2503/DM2504 Successive Approximation Registers ........................
LM131A1LM131, LM231A1LM231, LM331A1LM331 Precision Voltage-to-Frequency
Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM54C905/MM74C905 12-Bit Successive Approximation Register. . . . . . . . . . . . . . . . . . . . . . .
/LA9708 6-Channel 8-Bit /LP Compatible AID Converter .................................
3-2
3-3
3-4
3-7
3-16
3-48
3-59
3-70
3-81
3-91
3-107
3-115
3-140
3-158
3-170
3-187
3-204
3-211
3-222
3-239
3-250
3-250
3-259
3-268
3-278
3-279
3-290
3-291
~National
~ Semiconductor
Definition Of Terms
AID Converters
Conversion Time: The time required for a complete measurement by an analog-to-digital converter.
Multiplying DAC: In a sense, every DAC is a multiplying
DAC since the output voltage (or current) is equal to the
reference voltage times a constant determined by the digital
input code divided by 2n (n is the number of bits of resolution). In a two quadrant multiplying DAC the reference voltage or the digital input code can change the output voltage
polarity. If both the reference voltage and the digital code
change the output voltage polarity four quadrant multiplication exists.
DC Common-Mode Error: This specification applies to
ADCs with differential inputs. it is the change in the output
code that occurs when the analog voltages on the two inputs are changed by an equal amount. It is expressed in
LSBs.
Differential Nonlinearity: Ideally, any two adjacent digital
codes correspond to measured analog voltages that are exactly one LSB apart. Differential non-linearity is a measure
of the worst case deviation from the ideal 1 LSB step. For
example, a DAC with a 1.5 LSB output change for a 1 LSB
digital code change exhibits % LSB differential non-linearity.
Differential non-linearity may be expressed in fractional bits
or as a percentage of full scale. A differential non-linearity
greater than 1 LSB will lead to a non-monotonic transfer
function in a DAC and missing codes in an ADC.
Offset Error (Zero Error): In a DAC, this is the output voltage that exists when the input digital code is set to give an
ideal output of zero volts. In the case of an ADC, this is the
difference between the ideal input voltage (% LSB) and the
actual input voltage that is needed to make the transition
from zero to 1 LSB. All the digital codes in the transfer curve
are offset by the same value. Many converters allow nulling
of offset with an external potentiometer. Offset error is usually expressed in LSBs.
Gain Error (Full Scale Error): For an ADC, the difference
(usually expressed in LSBs) between the input voltage that
should ideally produce a full scale output code and the actual input voltage that produces that code. For DACs, it is the
difference between the output voltage (or current) with full
scale input code and the ideal voltage (or current) that
should exist with a full scale input code.
Power Supply Rejection (Power Supply Sensitivity): The
sensitivity of a converter to changes in the dc power supply
voltages.
Quantizing Error: The error inherent in all AID conversions. Since even an "ideal" converter has finite resolution,
any analog voltage that falls between two adjacent output
codes will result in an output code that is inaccurate by up to
% LSB.
Gain Temperature Coefficient (Full Scale Temperature
Coefficient): Change in gain error divided by change in
temperature. Usually expressed in parts per million per degree Celsius (ppml'C).
Ratiometric Operation: Many AID applications require a
stable and accurate reference voltage against which the input voltage is compared. This approach results in an absolute conversion. Some applications, however, use transducers or other signal sources whose output voltages are
proportional to some external reference. In these ratiometric applications, the reference for the signal source should
be connected to the reference input of the converter. Thus,
any variations in the source reference voltage will also
change the converter reference voltage and produce an accurate conversion.
Integral Nonlinearity (Linearity Error): Worst case deviation from the line between the endpoints (zero and full
scale). Can be expressed as a percentage of full scale or in
fractions of an LSB.
LSB (Least-Significant Bit): In a binary coded system this
is the bit that carries the smallest value or weight. Its value
is the full scale voltage (or current) divided by 2n, where n is
the resolution of the converter.
Missing Codes: When an incremental increase or decrease
in input voltage causes the converter to increment or decrement its numeric output by more than one LSB the converter is said to exhibit "missing codes". If there are missing
codes, there is a numeric value on the output on the converter which cannot be reached by any input voltage value.
Resolution: The smallest analog increment corresponding
to a 1 LSB converter code change. For converters, resolution is normally expressed in bits, where the number of analog levels is equal to 2n. As an example, a 12-bit converter
divides the analog signal into 212 = 4096 discrete voltage
(or current) levels.
Monotonicity: A monotonic function has a slope whose
sign does not change. A monotonic DAC has an output that
changes in the same direction (or remains constant) for
each increase in the input code. The converse is true for
decreasing codes.
Settling Time: The time from a change in input code until a
DAC's output Signal remains within ± % LSB (or some other
specified tolerance) of the final value.
MSB (Most Significant Bit): In a binary coded system this
is the bit that has the largest value or weight. Its value is one
half of full scale.
3-3
•
CI)
'C
·s
c:J
c
~NatiOnal
Semiconductor
o
:g
CI)
..
Ci)
AID Converter Selection Guide
(J)
~
CI)
c>
o
o
c
:(
Part
No.
Input
Resolution Accuracy Conversion
Voltage
(Bits)
(Max)
Time
Range
Output
Logic
Levels
Supplies
(V)
Temperature
RangeM
I
Package
Comments
C
AID CONVERTER
TTL,
+5, -12
TRI-STATE
•
5V
TTL,
TRI-STATE
+5
•
•
110 ",S
5V
TTL,
TRI-STATE
+5
•
•
•
20-PinDIP
20-PinSO Differential Input
20-PinPCC
±%LSB
110 ",S
5V
TTL,
TRI-STATE
+5
·
•
•
20-PinDIP
20-PinSO Differential Input
20-Pin PCC
8
±1 LSB
110 ",S
5V
TTL,
TRI-STATE
+5
•
•
20-Pin DIP
20-PinSO Differential Input
20-Pin PCC
tADC0805
8
±1 LSB
110 ",S
5V
TTL,
TRI-STATE
+5
•
20-PinDIP
tADC0808
8
±%LSB
100 ",S
5V
TTL,
TRI-STATE
+5
•
28-Pin DIP
8-Channel MUX
28-PinPCC
tADC0809
8
±1 LSB
fOO
5V
TTL,
TRI-STATE
+5
•
28-PinDIP
8-Channel MUX
28-PinPCC
tADC0811B
8
±%LSB
32",s
5V
TTL
+5
•
•
20-PinDIP II-Channel
20-Pin PCC Serial 1/0
tADC0811C
8
±1 LSB
32",s
5V
TTL
+5
•
•
20-PinDIP II-Channel
20-Pin PCC Serial 1/0
tADC0816
8
±%LSB
100 "'S
5V
TTL,
TRI-STATE
+5
tADC0817
8
±1 LSB
100 "'S
5V
TTL,
TRI-STATE
tADC0819B
8
±%LSB
16 ",S
5V
tADC0819C
8
±1 LSB
16",s
tADC0820B
8
±%LSB
tADC0820C
8
±1 LSB
tADC0800
8
±2LSB
50 ",S
±5V
tADC0801
8
±v..LSB
110 ",S
tADC0802
8
±Y2 LSB
tADC0803
8
tADC0804
"'S
•
•
•
18-Pin DIP
20-PinDIP Differential Input
Ratiometric
Operation
•
40-Pin DIP 16-Channel MUX
+5
•
40-PinDIP 16-Channel MUX
TTL
+5
•
•
28-Pin DIP 19-Channel
28-Pin PCC Serial 1/0
5V
TTL
+5
•
•
28-Pin DIP 19-Channel
28-PinPCC Serial 1/0
1.2 "'S
5V
TTL,
TRI-STATE
+5
•
•
•
20-Pin DIP
Built-In Track and
20-PinSO
Hold Function
20-Pin PCC
1.2 ",S
5V
TTL,
TRI-STATE
+5
•
•
•
20-PinDIP
Built-In Track and
20-PinSO
Hold Function
20-Pin PCC
3-4
»
.......
AID Converter Selection Guide (Continued)
Part
No.
Input
Resolution Accuracy Conversion
Voltage
(Bits)
(Max)
Time
Range
C
Output
Logic
Levels
Supplies
(V)
Temperature
Range'
M
I
oo
Package
Comments
:::J
<
CD
~
C
...CD
en
AID CONVERTER (Continued)
CD
tADC0829B
8
±%LSB
100,.s
5V
TTL,
TRI-STATE
+5
•
28-Pin DIP
Additional Digital
Input Capability
(j)
tADC0829C
8
±1 LSB
100,.s
5V
TTL,
TRI-STATE
+5
0
28-Pin DIP
Additional Digitai
Input Capability
:::J
C)
tADC0831B
8
±%LSB
32,.s
5V
TTL
+5
0
0
8-Pin DIP
Serial 1/0
tADC0831C
8
±1 LSB
32,.s
5V
TTL
+5
0
•
8-Pin DIP
Serial 1/0
tADC0832B
8
±%LSB
32,.s
5V
TTL
+5
•
0
8-Pin DIP
2-Channel
Serial 1/0
tADC0832C
8
±1 LSB
32,.s
5V
TTL
+5
0
•
8-Pin DIP
2-Channel
Serial 1/0
tADC0833B
8
±%LSB
32,.s
5V
TTL
+5
0
0
14-Pin DIP
4-Channel
Serial 1/0
tADC0833C
8
±1 LSB
32,.s
5V
TTL
+5
0
•
14-Pin DIP
4-Channel
Serial 1/0
tADC0834B
8
±%LSB
32,.s
5V
TTL
+5
·
0
14-Pin DIP
4-Channel
Serial 1/0
tADC0834C
8
±1 LSB
32,.s
5V
TTL
+5
0
0
14-Pin DIP
4-Channel
Serial 1/0
tADC0838B
8
±%LSB
32,.s
5V
TTL
+5
0
0
20-Pin DIP 8-Channel
20-Pin PCC Serial 1/0
tADC0838C
8
±1 LSB
32,.s
5V
TTL
+5
•
0
20-Pin DIP 8-Channel
20-Pin PCC Serial 1/0
tADC0841B
8
±%LSB
40,.s
5V
TTL,
TRI-STATE
+5
0
•
20-Pin DIP Differential Input,
20-Pin PCC Internal Clock
tADC0841C
8
±1 LSB
40,.s
5V
TTL,
TRI-STATE
+5
·
0
20-Pin DIP Differential Input,
20-Pin PCC Internal Clock
tADC0844B
8
±%LSB
40,.s
5V
TTL,
TRI-STATE
+5
•
•
20-Pin DIP
4-Channel MUX,
Internal Clock
tADC0844C
8
±1 LSB
40,.s
5V
TTL,
TRI-STATE
+5
•
0
20-Pin DIP
4-Channel MUX,
Internal Clock
tADC0848B
8
±%LSB
40,.s
5V
TTL,
TRI-STATE
+5
•
•
24-PinDIP 8-Channel MUX,
28-PinPCC Internal Clock
tADC0848C
8
±1 LSB
40,.s
5V
TTL,
TRI-STATE
+5
•
•
24-Pin DIP 8-Channel MUX,
28-Pin PCC Internal Clock
ADC1001C
10
±1 LSB
200,.s
5V
TTL,
TRI-STATE
+5
•
•
8-Bit Bus
20-Pin DIP Compatible,
Differential Input
ADC1005B
10
±%LSB
50,.s
5V
TTL,
TRI-STATE
+5
•
•
8-Bit Bus
20-Pin DIP
Compatible,
20-Pin PCC
Differential Input
3-5
0
g,
O·
C
c.:
CD
CI)
't:J
·5
~
c
o
:;:;
u
CI)
AID Converter Selection Guide (Continued)
Part
No.
Input
Resolution Accuracy Conversion
Voltage
(Bits)
(Max)
Time
Range
Output
Logie
Levels
Supplies
(V)
Cii
...
(I)
~
CI)
c>
o
o
c
......
Temperature
Range·
Package
Comments
M
I
C
•
•
•
8·Bit Bus
20·Pin DIP
Compatible,
20-Pin PCC
Differential Input
•
•
24-Pin DIP Differential Input
AID CONVERTER (Continued)
ADC1005C
10
±1 LSB
50/Ls
5V
TTL,
TRI·STATE
+5
ADC1021C
10
±1 LSB
200/Ls
5V
TTL,
TRI-STATE
+5
ADC1025B
10
±%LSB
50/Ls
5V
TTL,
TRI-STATE
+5
•
•
•
24-Pin DIP
Differential Input
28-Pin PCC
ADC1025C
10
±1 LSB
50/Ls
5V
TTL,
TRI-STATE
+5
•
•
•
24-Pin DIP
Differential Input
28-Pin PCC
ADC1205B
12+sign
±%LSB
100/Ls
±5V
TTL,
TRI-STATE
+5, ±5
•
•
8-Bit Bus
24-Pin DIP Compatible,
Differential Input
ADC1205C
12+sign
±1 LSB
100/Ls
±5V
TTL,
TRI-STATE
+5, ±5
•
•
ADC1210
12
±%LSB
200/Ls
10.2V
CMOS
+5to ±15
·
8-Bit Bus
24-Pin DIP Compatible,
Differential Input
•
24-Pin DIP Bipolar or
Unipolar Input
ADC1211
12
±2LSB
200/Ls
10.2V
CMOS
+5to ±5
•
•
24-Pin DIP Bipolar or
Unipolar Input
ADC1225B
12+sign
±%LSB
100/Ls
±5V
TTL,
TRI-STATE
+5, ±5
•
•
28-Pin DIP
Differential
Input
ADC1225C
12+sign
±1 LSB
100/Ls
±5V
TTL,
TRI-STATE
+5, ±5
•
•
28-Pin DIP
Differential
Input
ADC3511
3%-Digit
0.05%
200ms
2V
TTL,
TRI-STATE
+5
•
24-Pin DIP
Integrating
/LP Compatible
ADC3711
3%-Digit
0.05%
400ms
2V
TTL,
TRI-STATE
+5
•
24-Pin DIP
Integrating
/LP Compatible
V-F
0.Q1%
N/A
•
Voltage-to8-Pin DIP or Frequency
TO-99 Can Converter
100 kHz Max
c(
LM131
Open
Vee - 2V
Collector
+5to +40
•
•
DIGITAL VOLTMETER
ADD3501
3%-Digit
0.05%
200 ms
2V
7-Segment
LED Drive
+5
•
28-Pin DIP
3%-Digit
LED DVM
ADD3701
3%-Digit
0.05%
400ms
2V
7-Segment
LED Drive
+5
•
28-Pin DIP
3%-Digit
LED DVM
"Temperature ranges: "M" is -55°C to +125°C ambient; "I" is -40°C to +8SoC or -25°C to
tAccuracy specified is absolute accuracy and includes total unadjusted errOT.
3-6
+ 85°G; "G"
is O"C to +700C.
»
c
n
o
~National
CO
~ Semiconductor
o
o
ADC0800 8-Bit AID Converter
General Description
Features
The ADC0800 is an 8-bit monolithic AID converter using Pchannel ion-implanted MOS technology. It contains a high
input impedance comparator, 256 series resistors and analog switches, control logic and output latches. Conversion is
performed using a successive approximation technique
where the unknown analog voltage is compared to the resistor tie points using analog switches. When the appropriate tie point voltage matches the unknown voltage, conversion is complete and the digital outputs contain an 8-bit
complementary binary word corresponding to the unknown.
The binary output is TRI-STATE® to permit bussing on common data lines.
•
•
•
•
•
Low cost
±5V, 10V input ranges
No missing codes
Ratiometric conversion
TRI-STATE outputs
•
•
•
•
•
•
•
•
Fast
Contains output latches
TTL compatible
Supply voltages
Resolution
Linearity
Conversion speed
Clock range
The ADC0800PD is specified over - 55'C to + 125'C and
the ADC0800PCD is specified over O'C to 70'C.
TC=50 JLs
5 VDC and -12 VDC
8 bits
±1 LSB
40 clock periods
50 to 800 kHz
Block Diagram
Vss
(PMOS
BODY)
R·NETWORK
TOP
15
10
r - ...__:::_-_-=-:_-_-..:;:~~-~-': ':.-~:::-------:::..--
I
P.RESISTOR
N·BODY
I
: : :~. . :::1dI
I
I
I
I
ANALOG
SWITCH+
-..--_-_-__
+I;.;,I-oCLOCK
16
I
SELECTION
AND
CONTROL
LOGIC
.-J _
t--+--__I 300
L
_...J
IB
END OF
CONVERSION
(EOC)
O-VGG
17
I
B·BIT
LATCH
I
L
I
t
150
I
I
START
CONVERSION
-- ----
5
R·NETWORK
BOTTOM
-.J OIGITA~ROUNO
12
13
MSB
VIN
ANALOG
INPUT
LSB
COMPLEMENTARY
DIGITAL OUTPUT
TLlH/5670-1
(OOOOOOOO~
+ full·scale)
3-7
g
Q)
o
(.)
C
V+) the absolute value of current at that pin should be limited
to 5 rnA or less. The 20 rnA package input current limits the,number of pins that can exceed the power supply boundaries w~h a 5 rnA current limit to four.
Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX. 6JA. and the ambient temperature. TA. The maximum
allowable power dissipation at any temparature is Po ~ (TJMAX - TA)/8JA or the number given in the Absolute Maximum Ratings, whichever is lower. For this
device, TJMAX ~ 125'C, and the typical iunction·lo·ambient thermal resistance of the ADC0800PO and ADC0800PCD when board mounted is 66·C/W.
Note 4: Human body model, 100 pF discharged through a 1.5 kG resistor.
Note 5: Typicals are at 2S'C and represent most likely parametriC norm.
Note 6: Tested limits are guaranteed to National's AOQL (Average OutgOing Quality Level).
Note 7: Oesign limits are guaranteed but not 100% tested. These limits are not used to calculate outgoing quality levels.
Note 8: Non.linearity specifications are based on best straight line.
Note 9: Guaranteed by deSign only.
Note 10: Start conversion pulse duration greater than 3% clock periods will cause conversion errors.
3·8
l>
C
oQ
Timing Diagram
co
Q
Q
CLOCK
INPUT
+SV-n
START
CONVERSION
ov--l
~~I
1----1
+SV,
EOC
_____________________________
\--.- - - 4 0 X I 1 /1
\~________I~______--J.
OV
+SV
OUTPUT
ENABLE
I'\. SO%
"SO%
OV
!
+sv
DATA
-
-
-
-
"'1i-RTsTATEi -
-
-
-
-I
OV
ENABLE
OELAY-
-190%
F9D'!.
-
\'10%
lOll
1-
DISABLE
DELAY-
TUH/5670-2
Dala is complementary binary (full scale is all "O's" output).
Application Hints
R-network (pin 15). The analog input voltage and the voltage that is applied to the bottom of the R-network (pin 5)
must be at least 7V above the -VGG supply voltage to
ensure adequate voltage drive to the analog switches.
OPERATION
The ADCOBOO contains a network with 256-3000 resistors
in series. Analog switch taps are made at the junction of
each resistor and at each end of the network. In operation,
a reference (10.00V) is applied across this network of 256
resistors. An analog input (VIN) is first compared to the center point of the ladder via the appropriate switch. If VIN is
larger than VREF/2, the internal logic changes the switch
pOints and now compares VIN and % VREF. This process,
known as successive approximation, continues until the
best match of VIN and VREF/N is made. N now defines a
specific tap on the resistor network. When the conversion is
complete, the logic loads a binary word corresponding to
this tap into the output latch and an end of conversion
(EOC) logic level appears. The output latches hold this data
valid until a new conversion is completed and new data is
loaded into the latches. The data transfer occurs in about
200 ns so that valid data is present virtually all the time in
the latches. The data outputs are activated when the Output
Enable is high, and in TRI-STATE when Output Enable is
low. The Enable Delay time is approximately 200 ns. Each
conversion requires 40 clock periods. The device may be
operated in the free running mode by connectiRg the Start
Conversion line to the End of Conversion line. However, to
ensure start-up under all possible conditions, an external
Start Conversion pulse is required during power up conditions.
Other reference voltages may be used (such as 10.24V). If a
5V reference is used, the analog range will be 5V and accuracy will be reduced by a factor of 2. Thus, for maximum
accuracy, it is desirable to operate with at least a 10V reference. For TTL logic levels, this requires 5V and - 5V for the
R-network. CMOS can operate at the 10 VDC Vss level and
a single 10 VDC reference can be used. All digital voltage
levels for both inputs and outputs will be from ground to
VSS·
ANALOG INPUT AND SOURCE RESISTANCE
CONSIDERATIONS
The lead to the analog input (pin 12) should be kept as short
as possible. Both noise and digital clock coupling to this
input can cause conversion errors. To minimize any input
errors, the following source resistance considerations
should be noted:
For RsS;5k
No analog input bypass capacitor required, although a 0.1 JoLF input bypass
capaCitor will prevent pickup due to unavoidable series lead inductance.
For 5k 20k
Input buffering is necessary.
The reference applied across the 256 resistor network determines the analog input range. VREF= 10.00V with the top
of the R-network connected to 5V and the bottom connected to - 5V gives a ± 5V range. The reference can be level
shifted between Vss and VGG. However, the voltage, applied to the top of the R-network (pin 15), must not exceed
VSS, to prevent forward biasing the on-chip parasitic silicon
diodes that exist between the P-diffused resistors (pin 15)
and the N-type body (pin 10, Vss). Use of a standard logic
power supply for Vss can cause problems, both due to initial
voltage tolerance and changes over temperature. A solution
is to power the Vss line (15 mA max drain) from the output
of the op amp that is used to bias the top of the
If the overall converter system requires lowpass filtering of
the analog input Signal, use a 20 kO or less series resistor
for a passive RC section or add an op amp RC active lowpass filter (with its inherent low output resistance) to ensure
accurate conversions.
CLOCK COUPLING
The clock lead should be kept away from the analog input
line to reduce coupling.
LOGIC INPUTS
The logical "1" input voltage swing for the Clock, Start Conversion and Output Enable should be (Vss-1.0V).
3-9
C) , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,
C)
CI)
(Continued)
C)
Application Hints
(.)
C
Typical Applications
C
o
(Continued)
C)
zero adjust potentiometer should be set to provide a flicker
on the LSB LED readout with all the other display LEOs
OFF.
To adjust the full-scale adjust potentiometer, an analog input that is 1% LSB less than the reference (10.240-0.060
or 10.180 VDcl should be applied to the analog input and
the full-scale adjusted for a flicker on the LSB LED, but this
time with all the other LEOs ON.
TESTING THE AID CONVERTER
There are many degrees of complexity associated with testing an AID converter. One of the simplest tests is to apply a
known analog input voltage to the converter and use LEOs
to display the resulting digital output code as shown in Figure 3. Note that the LED drivers invert the digital output of
the AID converter to provide a binary display. A lab DVM
can be used if a precision voltage source is not available.
After adjusting the zero and full-scale, any number of pOints
can be checked, as desired.
co
C)
C)
A complete circuit for a simple AID tester is shown in Figure
4. Note that the clock input voltage swing and the digital
output voltage swings are from OV to 10.24V. The
MM74C901 provides a voltage translation to 5V operation
and also the logic inversion so the readout LEOs are in binary.
For ease of testing, a 10.24 VDC reference is recommended
for the AID converter. This provides an LSB of 40 mV
(10.240/256). To adjust the zero of the AID, an analog input
voltage of % LSB or 20 mV should be applied and the
START
AiD
UNDER TEST
I
I
V
~
OUTPUT
ENABLE
BINARY DISPLAY
TL/H/5670-15
FIGURE 3. Basic AID Tester
(POWE~·~tDp~e~) 0 - - -.....- - -....- - -....--.+
1'1D"F
Ik
FUll-SCALE
ADJUST
SVOC
10
roo
lD.24V-.,
DV....J L..J
I- BOD kHz
OUT EN
Vss
MSB
ClK
ADCDBDO
UNDER TEST
•
ANALOG
INPUT
2EA MM74C9Dl
(CMDSTDTILI
TLlH/5670-7
FIGURE 4. Complete Basic Tester Circuit
3·13
Typical Applications
(Continued)
The digital output LED display can be decoded by dividing
the 8 bits into the 4 most significant bits and 4 least significant bits. Table I shows the fractional binary equivalent of
these two 8-bit groups. By adding the decoded voltages
which are obtained from the column: "Input Voltage Value
with a 10.240 VREF" of both the MS and LS groups, the
value of the digital display can be determined. For example,
for an output LED display of "1011 0110" or "B6" (in hex)
the voltage values from the table are 7.04 + 0.24 or
7.280 Voc. These voltage values represent the center values of a perfect AID converter. The input voltage has to
change by ± % LSB (± 20 mV), the "quantization uncertainty" of an AID, to obtain an output digital code change. The
effects of this quantization error have to be accounted for in
the interpretation of the test results. A plot of this natural
error source is shown in Figure 5 where, for clarity, both the
analog input voltage and the error voltage are normalized to
LSBs.
TABLE I. DECODING THE DIGITAL OUTPUT LEDs
INPUT VOLTAGE
VALUE WITH
10,24 VREF
FRACTIONAL BINARY VALUE FOR
HEX
BINARY
MSGROUP
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
LSGROUP
15/16
15/256
7/8
7/128
13/16
13/256
3/4
3/64
11/16
11/256
5/8
5/128
9/256
9/16
1/2
1/32
7/16
7/256
3/8
3/128
5/16
5/256
1/64
1/4
3/16
3/256
1/8
11128
1/16
!z
1/256
MSGROUP
LSGROUP
9.600
8.960
8.320
7.680
7.040
6.400
5.760
5.120
4.480
3.840
3.200
2.560
1.920
1.280
0.640
0
0.600
0.560
0.520
0.480
0.440
0.400
0.360
0.320
0.280
0.240
0.200
0.160
0.120
0.080
0.040
0
1
-- .---.---.---=
co
..:;
w
0
112
0
>
'"
'"ffi
0
..
e
-1/2
-1
~ ~ ~3
Gc-_~~_'~~_
ANALOG INPUT VOLTAGE (IN LSBs)
Tl/H/5670-8
FIGURE 5. Error Plot of a Perfect AID Showing Effects of Quantization Error
3-14
):0
Typical Applications
c
(Continued)
A low speed ramp generator can also be used to sweep the
analog input voltage and the LED outputs will provide a binary counting sequence from zero to full-scale.
For operation with a microprocessor or a computer-based
test system, it is more convenient to present the errors digitally. This can be done with the circuit of Figure 7 where the
output code transitions can be detected as the 1O-bit DAC is
incremented. This provides % LSS steps for the 8-bit AID
under test. If the results of this test are automatically plotted
with the analog input on the X axis and the error (in LSS's)
as the Y axis, a useful transfer function of the AID under
test results. For acceptance testing, the plot is not necessary and the testing speed can be increased by establishing
internal limits on the allowed error for each code.
The techniques described so far are suitable for an engineering evaluation or a quick check on performance. For a
higher speed test system, or to obtain plotted data, a digitalto-analog converter is needed for the test set-up. An accurate 10-bit DAC can serve as the precision voltage source
for the AID. Errors of the AID under test can be provided as
either analog voltages or differences in two digital words.
A basic AID tester which uses a DAC and provides the error
as an analog output voltage is shown in Figure 6. The 2 op
amps can be eliminated if a lab DVM with a numerical subtraction feature is available to directly readout the difference
voltage, "A-C".
n
o
co
o
o
ANALOG INPUT
VOLTAGE
"A"
1D1XANAlOG
ERROR VOL lAGE
":'
All
R's~O.05%
tolerance
Tl/H/5670-16
FIGURE 6. AID Tester with Analog Error Output
DIGITAL
INPUT
DIGITAL
OUTPUT
TlIH/5670-17
FIGURE 7. BasiC "Digital" AID Tester
Connection Diagram
Dual-In-Llne Package
R·
N£T·
WORK
Voo
"
2-5
17
2-8
"
TOP
15
.
2-1
•
LSI
2-8
Il
VIN
12
CLOCK
Vss
11
ID
-
'--
.-1
Z
,-4
,-3
3
,-,
•
,-I
lIS.
, ,
1
•
R·
IIIET·
•
EO.
WOR'
lonuM
Top View
Order Number ADC0800PD
or ADC0800PCD
See NS Package Number D18A
3-15
Tl1H/5670-9
_NatiOnal
Semiconductor
ADC08011 ADC08021 ADC08031 ADC08041 ADC0805
8-Bit p,P Compatible AID Converters
General Description
The ADC0801, ADC0802, ADC0803, ADC0804 and
ADC0805 are CMOS 8-bit successive approximation AID
converters that use a differential potentiometric laddersimilar to the 256R products. These converters are designed to allow operation with the NSC800 and INS8080A
derivative control bus with TRI-STATE® output latches directly driving the data bus. These AIDs appear like memory
locations or I/O ports to the microprocessor and no interfacing logic is needed.
Differential analog voltage inputs allow increasing the common-mode rejection and offsetting the analog zero input
voltage value. In addition, the voltage reference input. can
be adjusted to allow encoding any smaller analog voltage
span to the full 8 bits of resolution.
• Differential analog voltage inputs
• Logic inputs and outputs meet both MOS and TTL voltage level specifications
• Works with 2.5V (LM336) voltage' reference
• On-chip clock generator
• OV to 5V analog input voltage range with single 5V
supply
• No zero adjust required
• 0.3" standard width 20-pin DIP package
• 20-pin molded chip carrier or small outline package
• Operates ratiometrically or with 5 VDC, 2.5 VDC, or analog span adjusted voltage reference
Features
• Resolution
• Total error
• Conversion time
Key Specifications
• Compatible with 8080 ",p derivatives-no interfacing
logic needed - access time - 135 ns
• Easy interface to all microprocessors, or operates
"stand alone"
8 bits
±% LSB, ±y. LSB and ±1 LSB
100 J.ts
Typical Applications
,.,.
,
, ff
, I'IR
,
~~
JI'RDCESSDR
12
13
;
elK R
10k
DB6
DB'
DB4
"
DB'
17
11
y
T~o~
r--
~,.SDUCER
8·81T RESOLUTION
OYER ANY DESIRED
ANALOG INPUT
VOLTAGE RANGE
DB7
14
"
19
elKIN 4
tNTR
t1
20
Vee
RD
DB'
DB'
DBO
AID
6
YIN(+I
7 >DIFF INPUTS
V'NH
AGND
VREFI2
L-
8
.!.....o ~~~~:C~ION ~
-
SEE SECTION U.1
'::'
2A.1
10
o GND
'--
":;}.,
If.
TUH/5671-1
8080 Interface
Error Specification (Includes Full-Scale,
Zero Error, and Non-Linearity)
i:I
iii
NSC.DO,
101••
lID,
8048.
ETC,
WI!
AID
Full·
VREF/2=2.500 Voc VREF/2 = No Connection
Scale
(No Adjustments)
(No Adjustments)
Adjusted
ADC0801
±%LSB
±y. LSB
ADC0802
I1ITII
A
.,
Part
Number
ADC0803
±Y.LSB
DATA
ADC0804
ADC0805
TL/H/5671-31
3-16
±1 LSB
±1 LSB
Absolute Maximum Ratings
(Notes 1 & 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Package Dissipation at TA = 25·C
875mW
ESD Susceptibility (Note 10)
Supply Voltage (Vce> (Note 3)
6.5V
Voltage
Logic Control Inputs
-0.3Vto +18V
At Other Input and Outputs
-0.3V to (VCC+ 0.3V)
Lead Temp. (Soldering. 10 seconds)
Dual-In-Line Package (plastic)
260·C
300·C
Dual-In-Line Package (ceramic)
Surface Mount Package
Vapor Phase (60 second,s)
Infrared (15 seconds)
-65·C to + 150·C
Storage Temperature Range
800V
Operating Ratings
215"C
220·C
Min
Typ
»
c
o
N
.....
c»
o
o
(X)
o
~
»
c
oo
(X)
The following specifications apply for Vcc=5 Voc. TMINS;TAS;TMAX and fCLK=640 kHz unless otherwise specified.
Conditions
o
(X)
TMINS;TAS;TMAX
-55·CS;TAS;+125·C
-40·CS;TAS; + 85·C
-40·CS;TAS; + 85·C
0·CS;TAS;+70·C
0·CS;TAS;+70"C
0·CS;TAS;+70"C
4.5 VOC to 6.3 voc
Electrical Characteristics
Parameter
(X)
....
.....
oo
(Notes 1 & 2)
Temperature Range
ADC0801/02LJ
ADC0801/02/03/04LCJ
ADC0801/02/03/05LCN
ADC0804LCN
ADC0802/03/04LCV
ADC0802/03/04LCWM
RangeofVCC
»
c
oo
o
Max
Units
.....
~
ADC0801: Total Adjusted Error (Note 8)
With Full-Scale Adj.
(See Section 2.5.2)
±%
LSB
»
c
ADC0802: Total Unadjusted Error (Note 8)
VREF/2=2.500 VOC
±%
LSB
(X)
ADC0803: Total Adjusted Error (Note 8)
With Full-Scale Adj.
(See Section 2.5.2)
±%
LSB
ADC0804: Total Unadjusted Error (Note 8)
VREF/2=2.500 VOC
±1
LSB
ADG0805: Total Unadjusted Error (Note 8)
VREF/2-No Connection
±1
LSB
VREF/2 Input Resistance (Pin 9)
ADC0801/02/03/05
ADC0804 (Note 9)
2.5
0.75
8.0
1.1
oo
o
C1I
kO
kO
Analog Input Voltage Range
(Note 4) V( +) or V( -)
DC Common-Mode Error
Over Analog Input Voltage
Range
Gnd-0.05
±'A6
±Va
VOC
LSB
Power Supply Sensitivity
Vcc=5 VOC ± 10% Over
Allowed VIN( +) and VIN( -)
Voltage Range (Note 4)
±'A6
±Va
LSB
VCC+0.05
AC Electrical Characteristics
The following specifications apply for Vcc= 5 VOC and TA = 25·C unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Tc
Conversion Time
fClK = 640 kHz (Note 6)
103
114
p.s
Tc
Conversion Time
(Note 5. 6)
66
73
l/fclK
fClK
Clock Frequency
Clock Duty Cycle
VCc=5V. (Note 5)
(Note 5)
100
40
1460
60
kHz
%
CR
Conversion Rate in Free-Running
Mode
INTR tied to WR with
CS=O VOC. fClK=640 kHz
9708
conv/s
tW(WR)L
Width of WR Input (Start Pulse Width)
CS=O VOC (Note 7)
tACC
Access Time (Delay from Falling
Edge of RD to Output Data Valid)
Cl =100 pF
135
200
ns
tlH. tOH
TRI-STATE Control (Delay
from Rising Edge of RD to
Hi-ZState)
Cl =10 pF. Rl =10k
(See TRI-STATE Test
Circuits)
125
200
ns
tWI.tRI
Delay from Falling Edge _ _
of WR or RD to Reset of INTR
300
450
ns
GIN
Input Capacitance of Logic
Control Inputs
5
7.5
pF
COUT
TRI-STATE Output
Capacitance (Data Buffers)
5
7.5
pF
640
8770
100
ns
CONTROL INPUTS [Note: CLK IN (Pin 4) is the input of a.Schmitt trigger circuit and is therefore specified separately]
VIN(1)
Logical "1" Input Voltage
(Except Pin 4 CLK IN)
Vcc=5.25Voc
3-17
2.0
15
VOC
•
It)
CI
co
CI
AC Electrical Characteristics (Continued)
C
The following specifications apply for Vee = 5Voe and T MIN';; TA ,;; T MAX, unless otherwise specified.
o
c(
"..,.
CI
Symbol
I
Parameter
I
Conditions
I
Min
I
Typ
I
Max
co
CONTROL INPUTS [Note: ClK IN (Pin 4) is the input of a Schmitt trigger circuit and is therefore specified separately]
o
VIN(O)
~
liN (1)
CI
C
('I)
CI
CI
liN (0)
C
c(
"NCI
co
Vr+
CI
Vr-
co
VH
CI
C
0.005
1
/LAoe
-1
-0.005
2.7
3.1
3.5
Voe
ClK IN (Pin 4) Negative
Going Threshold Voltage
1.5
1.8
2.1
Voe
ClK IN (Pin 4) Hysteresis
0.6
1.3
2.0
Voe
0.4
Voe
logical "0" Input Current
(All Inputs)
VIN=OVoe
/LAoe
ClK IN (Pin 4) Positive Going
(VT+ )-(Vr)
o
c(
VIN=5 Voe
Voe
Threshold Voltage
c(
".,...
CI
logical "1" Input Current
0.8
CLOCK IN AND CLOCK R
o
C
Vee = 4.75 Voe
Units
(All Inputs)
co
o
logical "0" Input Voltage
(Except Pin 4 ClK IN)
I
Your (0)
logical "0" ClK R Output
Voltage
VOUT(1)
logical "1" ClK R Output
Voltage
10= 36O /LA
Vee = 4.75 Voe
10=-360/LA
2.4
Voe
Vee = 4.75 Voe
DATA OUTPUTS AND INTR
Vour(O)
logical "0" Output Voltage
Data Outputs
INTR Output
lour=1.6 rnA, Vee = 4.75 Voe
0.4
0.4
Vour (1)
logical "1" Output Voltage
10= -360 /LA, Vee =4.75 Voc
2.4
Vour(1)
logical "1" Output Voltage
10= -10 /LA, Vcc=4.75 VOC
4.5
VOC
lour
TRI-STATE Disabled Output
Vour=O VOC
-3
leakage (All Data Buffers)
Vour=5 VOC
/LAOC
/LAoe
lour=1.0 rnA, Vee = 4.75 Voe
VDe
Voe
VDC
3
ISOURCE
Vour Short to Gnd, T A = 25°C
4.5
ISINK
VOUT Short to Vcc, T A = 25°C
9.0
6
mAoc
16
mAoc
POWER SUPPLY
Icc
Supply Current (Includes
ladder Current)
fCLK=640 kHz,
VREF/2=NC, TA=25°C
andCS=5V
ADC0801/02/03/04lCJ/05
1.1
1.9
ADC0804lCN/lCVIlCWM
1.8
2.5
rnA
mA
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to Gnd, unless otherwise specnied. The separate A Gnd point should always be wired to the D Gnd.
Note 3: A zener diode exists. internally, from Vee to Gnd and has a typical breakdown voltage of 7 VDe.
Note 4: For VIN(-);" VIN(+) the digital output code will be 0000 OpOO. Two on-chip diodes are tied to each analog Input (see block diagram) which will forward
conduct for analog input voltages one diode drop below ground or one diode drop greater than the Vee supply. Be careful, during testing at low Vee levels (4.5V),
as high level analog inputs (5V) can cause this input diode to conduct-especially at elevated temperatures, and cause errors for analog inputs near tul1~scale. The
spec allows 50 mV forward bias of either diode. This means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV, the output
code will be correct. To achieve an absolute 0 Voc to 5 Voc input voltage range will therefore require a minimum supply voltage of 4.950 Voe over temperature
variations, initial tolerance and loading.
Note ,5: Accuracy is guaranteed at fClK
~
640 kHz. At higher clock frequencies accuracy can degrade. For lower clock frequencies, the duty cycle limits can be
extended so long as the minimum clock high time interval or minimum clock low time interval is no less than 275 ns.
Note 6: With an asynchronous start pulse, up to 8 clock periods may be required bafore the internal clock phases are proper to start the conversion process. The
start request is internally latched, see Figure 2 and section 2.0.
Note 7: The cg input is assumed to bracket the WR strobe input and therefore timing is dependent on the WR pulse width. An arbitrarily wide pulse width will hold
the converter in a reset mode 81;1d the start of conversion is initiated by the low to high transition of the WR pulse (see timing diagrams).
Note 8: None of these AIDs requires a zero adjust (see section 2.5.1). To obtain zero code at other analog input voltages see section 2.5 and Figure 5.
Note 9: The VREF/2 pin is the center point of a two-resistor divider connected from Vce to ground. In all versions of the ADC080t, ADc0802, ADC0803, and
ADC0805, and in the ADC0804LCJ, each resistor is typically 16 kll. In all versions of the ADC0804 except the ADC0804LCJ, each reSistor is typically 2.2 kll.
Note 10: Human body model, tOO pF discharged through a 1.5 kll resistor.
3-18
»
c
oo
Typical Performance Characteristics
0)
o.....
);;
C
Delay From Falling Edge of
RD to Output Data Valid
vs. load Capacitance
logic Input Threshold Voltage
vs. Supply Voltage
ClK IN Schmitt Trip levels
vs. Supply Voltage
oo
0)
o
~
1.8 n--'-r~-5:O:50:::C~S;:'!T:-A~S;:-+~'2:l50::-C"
500
~
1.7
H-++-t--t-H-+-+:>I"-+--l
400
~
3.1
I
H7.v++++1:;;iH"'f++t-I
......
»
c
"g
1.6
2.1 H-++++-:I::::!-±+-I.::±:-l
0)
300
!~"!i1
~
2.3
L
H-+++-i-H--t-1H-+-l
1.9
vr_
H-+++-+-bl..-ot-,F'I=-+-l
.
co
co
~
H-++,.~H-++-t-+--l
H-+--J.-"l--t-H-+++-+--l
...
1.5
~
1.4 1"1-++++-H-+++t-I
::
~
~-
3.5 1"'"T-r-r
I -r-'T""1-r"'T""'T""1-r..,
~
~
~
_
-55°C~TA~+125°C
i!:
200
:!;
~
1.3 L-'-L...L...l.....JL..J.....L..J.....L....JL..J....J
4.50
4.15
5.00
5.25
5.50
100
o
200
VCC - SUPPLY VOLTAGE IVoel
400
600
100
I
1.5 L.l-L...L...l....L-I.--L...I-.1....J-L-'
5.25
5.50
5.00
4.15
4.50
1000
LOAD CAPACITANCE IpFI
VCC - SUPPLY VOLTAGE IVocl
N
oo
o
to)
......
»
c
oo
0)
o
-'="
......
»
c
oo
0)
o(1'f
Full-Scale Error vs
Conversion Time
fCLK vs. Clock Capacitor
1000
I
Effect of Unadjusted Offset Error
vs. VREF/2 Voltage
16
TC=73/fCLK
1
\
'1 k
:li
R- Ok
~
~
=2
\
100
10
5
ill
4
~
3
>
I"'
~
:::;
2
I
1000
40
&0
lA,,-t-+-t+-rI-++-l.,-I.,+-+--i
H-'kH-+-f-0ATA OUTPUT....
6 H-+-N++-iBi"U'!'FF-tE",RSl-t_HI-j
I
~OUT"2AVOC
4
H--A....r-+-t-t-t-1'oH....,H-I
3
H-+-+-t--~V~+~~~~.~~0.4~V-~0f-c~,~t1j
2~~~~~~~~~
0
25
50
15
B
6
:£co
4
2
120
100
0
0.01
140
0.1
100 125
TA - AMBIENTTEMPERATURE lOCI
'"f'.j
!"ili
1.6
~
~
1.2
d!..CC'"S. V
0.1
~
0.4
0
• ,VCF
=t5V
0
25
~
I
I
0:
co
_
~
50
"ILSB' 2IVREFIZI IZERO
AN::~LL' -
SCALE AOJUSTEO)-
It.±-
1-+- , ',Sa VALUE ImVI
0.5
1.22 t
4.88
I
~
19.53
~ M'1r~r~
-+-l 'CLK = 840 kHz
-H cr"I' I I
-50 -25
l-~oC~a01-
~
VCC'"5V
ill
~
:ggolo~~
o803ANOADC08ti~SiJ-f;;
5
linearity Error at low
VREF/2 Voltages
1.0 r-1r-I--r--r-r--r....,...-,--,-..,
ZA =::-rT"'1J"'T-r-,-,-,--,-rT-'-'
l~N-A~
... Z.O f.4.
Vcc~
1.0
VREF12IVOCI
Power Supply Current
vs Temperature (Note 9)
I rr.".,.;-r'-"'v"-cc:'!=75"VoCc:' "
-50 -25
ffi
V'NI+I = V'NI-I = OV.
ASSUMES VOS = 2 mV.
THIS SHOWSiHE NEED
FOR A ZERO A~J. IF
THE SPAN IS REDUCED.
TC. CONVERSION TIME ,"sl
Output Current vs
Temperature
5
10
;-
i;;
N::::b..
CLOCK CAPACITOR IpFI
I-+++-Pid-I-ils~u~c~
10
0:
1\ VCC·5.oV
VN
0
100
12 -
;;:
~
\
-1
:li
co
VCC- 4.5V
0:
\
J,'
&
0:
co
1\
~
;;
~
14
I
o~L-WW~~~~~~~
75
100 125
TA - AMBIENT TEMPERATURE rc)
o
1
Z
Z.5
VREFI2 VOLTAGE IVOCI
TLlH/5671-2
3-19
~ r-----------------------------------------------------------------------------------------~
C)
co
C)
o
c
TRI-STATE Test Circuits and Waveforms
~
co
C)
toH. CL = 10 pF
tOH
~
C)
VCC
Vce
Vec
g
Vcc ---I"':'~::=----
iii!
~
i
10k
DATA :::
8c
GND
~~IH
~
C")
OUTPUTS
DATA
OUTPUT
OH
vcc
DATA
OUTPUTS
GND------=
lr =20 ns
('I
-10%
VOL
c(
.....
~
TL/H/5671-3
1,=20 ns
i
C)
o
c
c(
.....
.....
C)
co
Timing Diagrams (All timing is measured from the 50% voltage points)
START
CDNVERS1DN _ _ _ _---.
\'----IIi~---II
C)
o
cc(
WI!
~f--1--'
twl-
-
I-I--
twlWiiIL
"BUSY"
ACTUAL INTERNAL
STATUS OF THE
CONVERTER
DATA IS VALID IN
OUTPUT LATCHES
"NOT BUSY"
INTERNAL T C -
-ITOBxllfCLK
,
ILAST DATA WAS READI
V
__
_ WAS
__
___
ILAST
DATA
NOT_
READI
INT ASSERTED
wJ
-
I-- lIZTCLK
Output Enable and Reset INTR
iIi'fii RESET
~
~
~
'R.
-
NOTE
DATA
OUTPUTS
--------
-
'ACC
- ----
TRI-STATE@
~----
-~
-
-
'IH.'OH
I--
Note: Read strobe must occur 8 clock periods (8/fcLlQ after assertion of Interrupt to guarantee reset of fiiI'i'R.
3-20
TUH/5671-4
»
c
oo
Typical Applications (Continued)
0)
6800 Interface
o
......
Ratiometric with Full·Scale Adjust
.......
»
c
Vee
15VOCI
o
o
0)
oI\)
,...----,
I
Vee
VINI+)
0
0
.. ,...
-:"..
&100.
seoz,
AID
85GZ,
ETC.
'='
);;
C
oo
n
+
~1GI'F
~
0)
o
AID
CAl
.......
'"
»
c
.
vREfn
VINI-I
'='
0
0
0
o
0l:00o
.......
OPTIONAL
FSADJUST
•• op ••
~
Nole: before using caps al VIN or VREF/2,
0)
L ____
•• .a. ••
'='
o
o
»
c
oo
see section 2.3.2 Input Bypass Capacitors.
0)
o
U'I
Absolute with a 2.S00V Reference
Absolute with a SV Reference
Vee
Vee·VREF
(SYnc)
(IVac)
['"----.,
vecl-~--...,
Vee 1-"",---1--"1
V".I+I
I
+
.
I
Tla~FI
..
AID
.".
AID
I
r---LI-I·~I"
..
I
I
VR"IZI----~~=;.:;
I
I
,,.
.".
L ____ J
FS
OPTIONAL
AD.
fSAD.lUST
'For low power, see also LM385-2.5
Zero·Shift and Span Adjust: 2V::5: VIN::5: SV
Span Adjust: OV::5:VIN::5:3V
Vee
liVoc)
Vee
ISVoc)
veel-~--------....,
r--(>--IVIOI'I
V,.
Vee
1-""'--------,
Voo
.
AID
AID
,,.
fS
+
SETS2ERD
lM336
AD'
~IIAF
--=-+....:;;===''-II-_t-.....J
CODEVDlTA·,,"JtJIiIr_ _-'\"'''',.,._ _
,.
ZJk
ZVac
ZERO ADJ
TUH/5671-5
3-21
Typical Applications
(Continued)
Directly Converting a Low-Level Signal
A p.P Interfaced Comparator
Vee
Vee
15Vocl
15YDCl
+
~1D"'F
"
AI.
'"
LM33&
"
FS
AD.I
For: V,N(+»V,N(-)
Outpul~ FFHEX
For. V,N(+)---------IVINI+1
1--+---------......,
+
~10~f
"
AI'
r-""',.,......
9.1k
I·IITDAC
2.5IOVDC
V."" 1-...,_....-<:'
OSVOAC<2.5V
'.5UOV.e
LM338
":"
Digitizing a Current Flow
..,
I2A FULL·SCALEI
--.I1OAO
Vee
'00
15Voc'
Vee
VINH
,...
+
1""
AID
":"
ZE~og ~.I------1 VIN(t)
'.J
"
":"
I.1k
VREfI2
UDk
TL/H/5671-6
3·22
»
c
Typical Applications (Continued)
oo
Self-Clocking Multiple AIDs
"CO--
o
......
.....
~! UiLftf---'C~~
----- ..'VO'"'
elKR
>
eLKR
CO
External Clocking
'V
eLKIN
-- --
-.--
,
AID #1
»
c
-- ----1.5VMAXO
oo
,------,
CO
o
.....
'"
»
c
51k-
AID
'CLlC~CLKIN
oo
AID
CO
o
w
.....
f--
eLKIN
"0--
--3D"
»
c
oo
ClKn
I
100 kHz,; fClK';; 1460 kHz
CO
o
AfD#2
--
.....
"""
»
c
t
oo
+
(Jt
·Use a large A value
to reduce loading
eLKIN
CO
I
at eLK R oul ut.
o
IF MORE THAN 5 ADDITIONAL
AIDs, USE A CMOS BUFFER (NOT TZl)
",p Interface for Free-Running AID
Self-Clocking in Free-Running Mode
YIN'''')
ClIR
10k
;:J; 0000',."_'_-:-:;::-_.,
CLKIN
AID
RUH
l.sTAGE
;J;15DPF
AID
ClK R 1--"'--1.~CLK
B~ND-:;4~~R
V07·
. . .--------.. .-0"1
eLKIN
STAnT"
;:J;
150,F
READY
ITO~PI
-I
·After power-up, a momentary grounding
of the WR input is needed to guarantee operation.
·VOl
n
I
1-III.lfCLKJ
11 PREVENTIRD
L - - - - - J LOURINGAID
I
I
~T,----
RESET
171.,lfClK)
DATA UPDATE
RESET
Operating with "Automotive" Ratiometric Transducers
Vee
(SVoC)
Ratiometric with VREF/2 Forced
Vee
(Syoc)
'Ok
VXDR
Vee
YINI+)
Ik
ZERO
+
Vee
VIN'''''
~'hF
VINI-'·
+
~'DPf
AD.
AID
3k
":"
AUCOlO5
-=-
'6k
ID.
AID
":"
VREFIZ
"
FS
AOJ
VINI-)
-=·VIN(-)~0.15
VCC
15% of VCC,;;VXDR,;;85% of VCC
VREFIZ
I'"'
ID'
-=Tl/H/5671-7
3-23
•
an
o
CO
8
c
A/D
c
oo
00
oCo)
AID
i>
CI~
c
oo
.. ---;.
.j:>.
00
r--
o
DATA I S / ' - - - J "-....STARTSHEW
OUTPUT
CONVERSION
TL/H/5671-33
TL/H/5671-34
"Beckman Instruments # 694-3-R1 OK resistor array
p.P Interfaced Comparator with Hysteresis
oo
Protecting the Input
00
o
c.n
Vee
(5 Vocl
VINI.)
MSI (08JII-----.
OBI
OUTPUT
AID
.:r:'+D,.,
-15 VDC
VINf-!
AID
VOE'"
'::'
Diodes are lN914
.,.
+VREF
CI
e
TLlH/5671-9
ii
A Low-Cost, 3-Decade Logarithmic Converter
OF.
TLlH/5671-35
'DO
Analog Self-Test for a System
v.
AID
SYSTEM
DeTEST
POINTS
8
CHANNEL
ANALOG
.ux
> ..............',.,.--!V,.H
"
AID
CD'15t
TL/H/5671-36
"LM389 transistors
A, B, C, D
3-25
~
LM324A quad op amp
......
»
c
Lt)
o
!
o
Typical Applications (Continued)
c
3·Decade Logarithmic AID Converter
c(
.....
..,.
A, B, C, D = lM324A
o
CO
o
o
cc(
'DO
'>-4.....-¥.I\,----IVINI+)
.....
C')
o
CO
o
o
c
AID
~
C'i
o
CO
o
lM'"
g
~
.....
o
o.1J1fT.".
ZAfl43t
CO
o
-sv
o
cc(
.
111
ID'
'"
AOJ
Noise Filtering the Analog Input
Multiplexing Differential Inputs
."
•
CHANNEL
DIFFERENTIAL
MUX
CD4D5Z
AID
AID
fC-20 Hz
Uses Chebyshev implementation for steeper roll-oll
unity-gain, 2nd order, low-pass filter
Adding a separate filter for each channel increases
B CHANNEL
:::..._~_~ SELECT
fROM OUTPUT
system response time if an analog multiplexer
PORT OR",
is used
Output Buffers with AID Data Enabled
Increasing Bus Drive andlor Reducing Time on Bus
Cf
TO",
AID
i'Iii_T""~_
AID
TOj.l'
DATA IUS
DATA*
Cf ........dr'-...
Cf
TRI-sTAUo!I
i'Iii
BUfFERS
DATA BUS
DATA OUT
~~
Viii
AID
TRI..sTATE@
BUFFERS
_______________________________________..J
TL/H/5671-10
'AID output data is updated 1 elK period
prior to assertion of IN'i'R
'Allows output data to set-up at falling edge of CS
3·26
J>
C
oo
Typical Applications (Continued)
...
CD
o
......
Sampling an AC Input Signal
J>
C
oo
OdB
co
o
SAMPLE
AND
HOLD
N
......
J>
LFJ91
C
AID
l/H
LOW-PASS, MUl Jl.PDLE
FILTER
o
o
CDNrRDL~Ch
CD
o
c.:I
......
J>
C
oo
-lrcl.JLJ
-I I', 1- ~--"'-------....I
co
o
0l:Io
i;
C
oo
Note 1: Oversample whenever possible [keep fs > 2f(-60)] to eliminate input frequency folding
(aliasing) and to allow for the skirt response of the filter.
CD
Note 2: Consider the amplitude errors which are introdUI...:!d within the passband of the filter.
o
UI
700/0 Power Savings by Clock Gating
laA/o
(Complete shutdown takes ::; 30 seconds.)
•
Power Savings by AID and VREF Shutdown
'V~DN
0-
r------.......~---.....,>------o~C~DC)
Off
vcc/-.,.,.--+
jJPCONTRDL
BUS
---,,_ ....
...
CMOS
AID"
BUFFER
TO DATA
BUS
VREF/21---.....
TL/H/5671-11
'Use ADC0801, 02, 03 or 05 for lowest power consumption.
Note: Logic inputs can be driven to Vee with AID supply at zero volts.
Buffer prevents data bus from overdriving output of AID when in shutdown mode.
3-27
Ln
o
CO
o
o
c
~
o
Functional Description
o
CO
o
A perfect AID transfer characteristic (staircase waveform) is
shown in Figure 1a. The horizontal scale is analog input
voltage and the particular points labeled are in steps of 1
LSB (19.53 mV with 2.5V tied to the VREF/2 pin). The digital
output codes that correspond to these inputs are shown as
D-1, D, and D+ 1. For the perfect AID, not only will centervalue (A -1, A, A + 1, . . . . ) analog inputs produce the correct output ditigal codes, but also each riser (the transitions
between adjacent output codes) will be located ± % LSB
away from each center-value. As shown, the risers are ideal
and have no width. Correct digital output codes will be provided for a range of analog input voltages that extend ± %
LSB from the ideal center-values. Each tread (the range of
analog input voltage that provides the same digital output
code) is therefore 1 LSB wide.
Figure 1b shows a worst case error plot for the ADCOB01.
All center-valued inputs are guaranteed to produce the correct output codes and the adjacent risers are guaranteed to
be no closer to the center-value points than ± % LSB. In
C
Transfer Function
CO
o
o
c
~
C')
CI
co
o
o
C
I
DE~~~ER 1+-++-HH-----1
INTR F/F
OAC
VIOUTI
AGND
-II-II. '#elKi
=+-
DIGITAL OUTPUTS
.)-_______
..
-.;.,
CSINOTE1iOt:::::=::_-_....<~f_-,_
TRI-sTATE@CONTROL
---"rfDlW. CDMJiC
--I 1-. -;;;-n:
x '"elK
..;=O:.;U;.::TP,::UT;.,E;;;N;;;AB:;:lE+_ _ _ _ _ _ _ _
ROO
RESET
TLlH/5671-13
Note 1: CS shown twice for clarity.
Nole 2: SAR = Successive Approximation Register.
FIGURE 2. Block Diagram
3-29
Ln
o
~
o
cc(
;;r
io
o
cc(
....
CO)
o
CO
o
o
cc(
....
('II
o
CO
o
o
c
c(
....
....
o
CO
o
o
cc(
r---------------------------------------------------------------------------------,
Functional Description (Continued)
After the "1" is clocked through the 8-bit shift register
(which completes the SAR search) it appears as the input to
the D-type latch, LATCH 1. As soon as this "1" is output
from the shift register, the AND gate, G2, causes the new
digital word to transfer to the TRI-STATE output latches.
When LATCH 1 is subsequently enabled, the Q output
makes a high-to-Iow transition which causes the INTR F/F
to set. An inverting buffer then supplies the INTR input signal.
Note that this SET control of the INTR F/F remains low for
8 of the external clock periods (as the internal clocks run at
'Is of the frequency of the external clock). If the data output
is continuously enabled (CS and RD both held low), the
INTR output will still signal the end of conversion (by a highto-low transition), because the SET input can control the Q
output of the INTR F/F even though the RESET input is
constantly at a "1" level in this operating mode. This INTR
output will therefore stay low for the duration of the SET
signal, which is 8 periods of the external clock frequency
(assuming the AID is not started during this interval).
slight time difference between the input voltage samples is
given by:
4.5 )
aVe(MAX) = (Vp) (21Tfem) ( fCLK '
where:
aVe is the error voltage due to sampling delay
Vp is the peak value of the common-mode voltage
fern is the common-mode frequency
As an example, to keep this error to % LSB (- 5 mY) when
operating with a 60 Hz common-mode frequency, fern, and
using a 640 kHz AID clock, fCLK, would allow a peak value
of the common-mode voltage, Vp, which is given by:
Vp = [aVe(MAXl (fCLK)1
(21Tfem) (4.5)
or
V _ (5 X 1O- 3 )(640X10 3)
p(6.28) (60) (4.5)
which gives
When operating in the free-running or continuous conversion mode (INTR pin tied to WR and CS wired low-see
also section 2.8), the START F/F is SET by the high-to-Iow
transition of the INTR signal. This resets the SHIFT REGISTER which causes the input to the D-type latch, LATCH 1,
to go low. As the latch enable input is still present, the Q
output will go high, which then allows the INTR F/F to be
RESET. This reduces the width of the resulting INTR output
pulse to only a few propagation delays (approximately 300
ns).
Vp""1.9V.
The allowed range of analog input voltages usually places
more severe restrictions on input common-mode noise levels.
An analog input voltage with a reduced span and a relatively
large zero offset can be handled easily by making use of the
differential input (see section 2.4 Reference Voltage).
2.3 Analog Inputs
When data is to be read, the combination of both CS and
RD being low will cause the INTR F/F to be reset and the
TRI-STATE output latches will be enabled to provide the 8bit digital outputs.
2.3.1 Input Current
Normal Mode
Due to the internal switching action, displacement currents
will flow at the analog inputs. This is due to on-chip stray
capacitance to ground as shown in Figure 3.
2.1 Digital Control Inputs
The digital control inputs (CS, RD, and WR) meet standard
T2L logic voltage levels. These signals have been renamed
when compared to the standard AID Start and Output Enable labels. In addition, these inputs are active low to allow
an easy interface to microprocessor control busses. For
non-microprocessor based applications, the CS input (pin 1)
can be grounded and the standard AI D Start function is
obtained by an active low pulse applied at the WR input (pin
3) and the Output Enable function is caused by an active
low pulse at the RD input (pin 2).
r----------------,
I
I
'ON'RS
.!:'I
I
I
I
RS
IpEAK'~
jt
~:&
'ON
SWI
2.2 Analog Differential Voltage Inputs and
Common-Mode Rejection
This AID has additional applications flexibility due to the
analog differential voltage input. The VIN( -) input (pin 7)
can be used to automatically subtract a fixed voltage value
from the input reading (tare correction). This is also useful in
4 mA-20 mA current loop conversion. In addition, commonmode noise can be reduced by use of the differential input.
eSTRAY
TU2PFI
TL/H/5671-14
'ON of SW 1 and SW 2 '" 5 kn
The time interval between sampling VIN( + ) and VIN( -) is 4'Iz clock periods. The maximum error voltage due to this
'~'ON
eSTRAY
e<
5 kn x 12 pF ~ 60 n.
FIGURE 3. Analog Input Impedance
3-30
,--------------------------------------------------------------------,>
c
Functional Description (Continued)
oo
The voltage on this capacitance is switched and will result in
currents entering the VIN( +) input pin and leaving the
VIN( -) input which will depend on the analog differential
input voltage levels. These current transients occur at the
leading edge of the internal clocks. They rapidly decay and
do not cause errors as the on-chip comparator is strobed at
the end of the clock period.
Fault Mode
If the voltage source applied to the VIN( +) or VIN( -) pin
exceeds the allowed operating range of Vee + 50 mV, large
input currents can flow through a parasitic diode to the Vce
pin. If these currents can exceed the 1 mA max allowed
spec, an external diode (1 N914) should be added to bypass
this current to the Vee pin (with the current bypassed with
this diode, the voltage at the VIN( +) pin can exceed the
Vee voltage by the forward voltage of this diode).
...
resistance and the use of an input bypass capacitor. This
error can be eliminated by doing a full-scale adjustment of
the AID (adjust VREF/2 for a proper full·scale reading-see
section 2.5.2 on Full-Scale Adjustment) with the source resistance and input bypass capacitor in place.
"-
2.4 Reference Voltage
oI\)
2.4.1 Span Adjust
For maximum applications flexibility, these AIDs have been
designed to accommodate a 5 Voe, 2.5 Voe or an adjusted
voltage reference. This has been achieved in the design of
the IC as shown in Figure 4.
"-
CXI
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>
C
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CXI
>
C
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CXI
o
W
"-
>
C
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20
CXI
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2.3.2 Input Bypass Capacitors
""
>
C
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"-
Bypass capacitors at the inputs will average these charges
and cause a DC current to flow through the output resistances of the analog signal sources. This charge pumping
action is worse for continuous conversions with the VIN( +)
input voltage at full-scale. For continuous conversions with
a 640 kHz clock frequency with the VIN( +) input at 5V, this
DC current is at a maximum of approximately 5 J.LA. Therefore, bypass capacitors should not be used at the analog
inputs or the VREFI2 pin for high resistance sources (> 1
kn). If input bypass capacitors are necessary for noise filtering and high source resistance is desirable to minimize capacitor size, the detrimental effects of the voltage drop
across this input resistance, which is due to the average
value of the input current, can be eliminated with a full-scale
adjustment while the given source resistor and input bypass
capacitor are both in place. This is possible because the
average value of the input current is a precise linear function of the differential input voltage.
R
I I
9
VREf/Z
DIGITAL
CIRCUITS
R
~}- H I
II DECODE
ANALOG
CIRCUITS
't-}~
A GNo
2.3.3 Input Source Resistance
Large values of source resistance where an input bypass
capacitor is not used, will not cause errors as the input currents settle out prior to the comparison time. If a low pass
filter is required in the system, use a low valued series resistor (:0: 1 kn) for a passive RC section or add an op amp RC
active low pass filter. For low source resistance applications, (:0: 1 kn), a 0.1 J.LF bypass capacitor at the inputs will
prevent noise pickup due to series lead inductance of a long
wire. A loon series resistor can be used to isolate this capacitor-both the Rand C are placed outside the feedback
loop-from the output of an op amp, if used.
8
-
o GND
10
r.7
TL/H/5671-15
FIGURE 4. The VREFERENCE Design on the IC
Notice that the reference voltage for the IC is either % of
the voltage applied to the Vee supply pin, or is equal to the
voltage that is externally forced at the VREF/2 pin. This allows for a ratiometric voltage reference using the Vee supply, a 5 Voe reference voltage can be used for the Vee
supply or a voltage less than 2.5 Voe can be applied to the
VREF/2 input for increased application flexibility. The internal gain to the VREF/2 input is 2, making the full-scale differential input voltage twice the voltage at pin 9.
An example of the use of an adjusted reference voltage is to
accommodate a reduced span-or dynamic voltage range
of the analog input voltage. If the analog input voltage were
to range from 0.5 Voc to 3.5 Voe, instead of OV to 5 Voc,
the span would be 3V as shown in Figure 5. With 0.5 Voe
applied to the VIN( -) pin to absorb the offset, the reference
voltage can be made equal to % of the 3V span or 1.5 Voe.
The AID now will encode the VIN( +) signal from 0.5V to 3.5
V with the 0.5V input corresponding to zero and the 3.5 Voe
input corresponding to full-scale. The full 8 bits of resolution
are therefore applied over this reduced analog input voltage
range.
2.3.4 Noise
The leads to the analog inputs (pin 6 and 7) should be kept
as short as possible to minimize input noise coupling. Both
noise and undesired digital clock coupling to these inputs
can cause system errors. The source resistance for these
inputs should, in general, be kept below 5 kn. Larger values
of source resistance can cause undesired system noise
pickup. Input bypass capacitors, placed from the analog inputs to ground, will eliminate system noise pickup but can
create analog scale errors as these capacitors will average
the transient input switching currents of the AID (see section 2.3.1.). This scale error depends on both a large source
3-31
CXI
o
en
~~--------------------------------------------------------~
o
CIO
8c
Functional Description
(Continued)
~
'
4
3
2
I
VIN(+)MAX
(3.5V)
4
+VREF
I
VI?J~JV~IN
SPAN =3V
I
0
-
0.5~:
ZERD-SHIFT
ADJ
U
C
Ql~ T
1.5 VDC
SPAN
ADJ
':"
c(
, ; LM358
SPAN12
(1.5VDC)
~.;t
.
':"
A'
IpF
~
TLlH/5671-16
a) Analog Input Signal Example
b) Accommodating an Analog Input from
O.5V (Digital Out = = OOHEX) to 3.5V
(Digital Out = FFHEXl
FIGURE 5. Adapting the AID Analog Input Voltages to Match an Arbitrary Input Signal Range
2.5 Errors and Reference Voltage Adjustments
2.4.2 Reference Accuracy Requirements
The converter can be operated in a ratiometric mode or an
absolute mode. In ratiometric converter applications, the
magnitude of the reference voltage is a factor in both the
output of the source transducer and the output of the AID
converter and therefore cancels out in the final digital output
code. The ADCOB05 is specified particularly for use in ratio·
metric applications with no adjustments required. In absolute conversion applications, both the initial value and the
temperature stability of the reference voltage are important
factors in the accuracy of the AID converter. For VREF/2
voltages of 2.4 Voc nominal value, initial errors of ± 10
mVoc will cause conversion errors of ± 1 LSB due to the
gain of 2 of the VREF/2 input. In reduced span applications,
the initial value and the stability of the VREF/2 input voltage
become even more important. For example, if the span is
reduced to 2.5V, the analog input LSB voltage value is correspondingly reduced from 20 mV (5V span) to 10 mV and
1 LSB at the VREF/2 input becomes 5 mY. As can be seen,
this reduces the allowed initial tolerance of the reference
voltage and requires correspondingly less absolute change
with temperature variations. Note that spans smaller than
2.5V place even tighter requirements on the initial accuracy
and stability of the reference source.
2.5.1 Zero Error
The zero of the AID does not require adjustment. If the
minimum analog input voltage value, V)N(MIN), is not ground,
a zero offset can be done. The converter can be made to
output 0000 0000 digital code for this minimum input voltage
by biasing the AID VIN( -) input at this VIN(MIN) value (see
Applications section). This utilizes the differential mode operation of the AID.
The zero error of the AI D converter relates to the location
of the first riser of the transfer function and can be measured by grounding the VIN (:-) input and applying a small
magnitude positive voltage to the VIN (+) input. Zero error
is the difference between the actual DC input voltage that is
necessary to just cause an output digital code transition
from 0000 0000 to 0000 0001 and the ideal '12 LSB value
('12 LSB = 9.B mV for VREF/2=2.500 Vocl.
2.5.2 Full-Scale
The full-scale adjustment can be made by applying a differential input voltage that is 1'12 LSB less than the desired
analog full-scale voltage range and then adjusting the magnitude of the VREF/2 input (pin 9 or the Vee supply if pin 9 is
not used) for a digital output code that is just changing from
11111110to 11111111.
In general, the magnitude of the reference voltage will require an initial adjustment. Errors due to an improper value
of reference voltage appear as full-scale errors in the AID
transfer function. IC voltage regulators may be used for references if the ambient temperature changes are not excessive. The LM336B 2.5V IC reference diode (from National
Semiconductor) has a temperature stability of 1.B mV typ
(6 mV max) over O'C,;;TA';; + 70'C. Other temperature
range parts are also available.
3-32
.-------------------------------------------------------------------~~
Functional Description
(Continued)
conversion in process is not allowed to be completed, therefore the data of the previous conversion remains in this
latch. The INTR output simply remains at the "1" level.
2.5.3 Adjusting for an Arbitrary Analog Input Voltage
Range
If the analog zero voltage of the AID is shifted away from
ground (for example, to accommodate an analog input sig·
nal that does not go to ground) this new zero reference
should be properly adjusted first. A V,N( +) voltage that
equals this desired zero reference plus y. lSB (where the
lSB is calculated for the desired analog span, 1 lSB = ana·
log span/256) is applied to pin 6 and the zero reference
voltage at pin 7 should then be adjusted to just obtain the
OOHEX to 01 HEX code transition.
The full-scale adjustment should then be made (with the
proper V,N( -) voltage applied) by forCing a voltage to the
V,N( +) input which is given by:
2.8 Continuous Conversions
For operation in the free-running mode.an initializing pulse
should be used, following power-up, to ensure circuit operation. In this application, the CS input is grounded and the
WR input is tied to the INTR output. This WR and INTR
node should be momentarily forced to logiC low following a
power-up cycle to guarantee operation.
2.9 Driving the Data Bus
This MaS AID, like MaS microprocessors and memories,
will require a bus driver when the total capacitance of the
data bus gets large. Other circuitry, which is tied to the data
bus, will add to the total capacitive loading, even in TRISTATE (high impedance mode). Backplane bussing also
greatly adds to the stray capacitance of the data bus.
There are some alternatives available to the designer to
handle this problem. Basically, the capacitive loading of the
data bus slows down the response time, even though DC
specifications are still met. For systems operating with a
relatively slow CPU clock frequency, more time is available
in which to establish proper logiC levels on the bus and
therefore higher capacitive loads can be driven (see typical
characteristics curves).
At higher CPU clock frequencies time can be extended for
I/O reads (and/or writes) by inserting wait states (8080) or
using clock extending circuits (6800).
.
[ (VMAX - VMIN)]
VIN (+) fs adJ = VMAX-1.5
256
'
where:
VMAX=The high end of the analog input range
and
VMIN = the low end (the offset zero) of the analog range.
(Both are ground referenced.)
The VREF/2 (or Vee> voltage is then adjusted to provide a
code change from FEHEX to FFHEX. This completes the adjustment procedure.
2.6 Clocking Option
The clock for the AID can be derived from the CPU clock or
an external RC can be added to provide self-clocking. The
ClK IN (pin 4) makes use of a Schmitt trigger as shown in
Figure 6.
ClKR
CD
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.....
......
~
c
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CD
o
N
......
~
C
oo
CD
o
CAl
i;
C
oo
CD
o·
~
......
~
c
oo
CD
o
U1
Finally, if time is short and capacitive loading is high, external bus drivers must be used. These can be TRI-STATE
buffers (low power Schottky such as the DM74lS240 series
is recommended) or special higher drive current products
which are designed as bus drivers. High current bipolar bus
drivers with PNP inputs are recommended.
v
19
1
feLK"'1.1 RC
2.10 Power Supplies
FIGURE 6. Self-Clocking the AID
Noise spikes on the Vee supply line can cause conversion
errors as the comparator will respond to this noise. A low
inductance tantalum filter capaCitor should be used close to
the converter Vee pin and values of 1 ).LF or greater are
recommended. If an unregulated voltage is available in the
system, a separate lM340LAZ-5.0, TO-92, 5V voltage regulator for the converter (and other analog circuitry) will greatly
reduce digital noise on the Vee supply.
Heavy capacitive or DC loading of the clock R pin should be
avoided as this will disturb normal converter operation.
loads less than 50 pF, such as driving up to 7 AID converter clock inputs from a single clock R pin of 1 converter, are
allowed. For larger clock line loading, a CMOS or low power
TTL buffer or PNP input logic should be used to minimize
the loading on the clock R pin (do not use a standard TTL
buffer).
Standard digital wire wrap sockets are not satisfactory for
breadboarding this AID converter. Sockets on PC boards
can be used and all logic Signal wires and leads should be
grouped and kept as far away as possible from the analog
signal leads. Exposed leads to the analog inputs can cause
undesired digital noise and hum pickup, therefore shielded
leads may be necessary in many applications.
FCl:::.K;;;I::r>-_--1~.'>o_..... ClK
c
oo
R"'10 k!l.
AID
TL/H/5671-17
2.11 Wiring and Hook-Up Precautions
2.7 Restart During a Conversion
If the AID is restarted (CS and WR go low and return high)
during a conversion, the converter is reset and a new conversion is started. The output data latch is not updated if the
3-33
II
Lr) , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,
Q
co
8c
--
»
c
n
Q
01)
VANALOG OUTPUT
Q
N
.....
»
c
R
ANAL~g~~=~~ 0 -
"B"
1
R
1
R
01)
%
100R +
R
~.
A
n
Q
:....
1"
~
"CO
Q
.....
»
c
Co)
':'
n
Q
1
01)
Q
100X ANALOG
ERROR VOLTAGE
~C
n
Q
01)
FIGURE 8. AID Tester with Analog Error Output
OIGITA~~~
INPUT
-y
OAC1000
10·BIT
DAC
r
Q
U1
AID UNDER
TEST
~DIGITAL
OUTPUT
TUH/S671-19
FIGURE 9. Basic "Digital" AID Tester
TABLE I. DECODING THE DIGITAL OUTPUT LEDs
HEX
FRACTIONAL BINARY VALUE FOR
BINARY
MSGROUP
C
1
1
1
1
1
1
1
1
1
1
0
0
1
0
1
0
B
A
9
8
1
1
1
1
0
0
0
0
1
1
0
0
1
0
1
0
7
6
5
4
0
0
0
0
1
1
1
1
1
1
0
0
1
0
1
0
3
2
1
0
0
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
F
E
0
OUTPUT VOLTAGE
CENTER VALUES
WITH
VREF/2=2.560 VOC
'Display Outpul= VMS Group
LSGROUP
15/16
15/256
7/8
71128
13/16
13/256
3/4
3/64
11/256
11/16
5/8
5/128
9/256
9/16
1/2
1/32
7/16
7/256
3/8
3/128
5/16
2/256
1/4
1/64
3/256
3/16
1/8
1/128
1/16
+
1/256
VLS Group
3·35
VMS GROUP'
VLSGROUP'
4.800
4.480
4.160
3.840
0.300
0.280
0.260
0.240
3.520
3.200
2/880
2/560
0.220
0.200
0.180
0.160
2.240
1.920
1.600
1/280
0.140
0.120
0.100
0.080
0.960
0.640
0.320
0
0.060
0.040
0.020
0
•
It)
o
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o
(.)
Functional Description (Continued)
C
INTI141
V
------- 011'1 (341 1'1
cs
iii!
Wii
elKIN
INTH
ANALOG
INPUTS
AID
VINI+I
VINH
1"'----_
J!!-----.
&---_
1"'-----.
1=------.
E-----.
J.!!...---_
VREFI2
13
DB'
OBI 12
DGND
DB1'1
AGND
I~::J
D, Ill! 1311
Dl Ilil
011311
D3 1301
D' ~II
D5 ~II
DB ~71
11'1
1"1
IHI
1311
1301
I[]
J!!-----. D7 ~'I 1'1
J-!------4 All {2I1
1341
~----"" A" 12'1 IMI
A" 1251 1331
~----"" VMAI" 1'1
Notet: Numbers in parentheses refer to MC6BOO CPU pin oUl
Note 2: Number or leiters in brackets refer to standard M6BOO system common bus code.
m
FIGURE 14. ADC0801·MC6800 CPU Interface
3-38
?GND
1111 lin
414243
I
TLlH/5671-24
»
C
Functional Description (Continued)
0
0
CD
SAMPLE PROGRAM FOR FIGURE 14 ADC0801-MC6800 CPU INTERFACE
DATAIN
TEMP2
DF36
STX
; Save contents of X
CE002C
LDX
; Upon IRQ low CPU
#$002C
FFFFF8
STX
$FFF8
; jumps to 002C
B7 50 00
STAA
; Start ADC0801
$5000
OE
CLI
3E
CONVRT
; Wai t for interrupt
WAI
DE 34
LDX
TEMPl
8C 02 OF
; Is final data stored?
CPX
#$020F
2714
ENDP
BEQ
B7 50 00
STAA
; Restarts ADC0801
$5000
08
INX
DF34
TEMPl
STX
20FO
BRA
CONVRT
DE 34
INTRPT
LDX
TEMPl
B6 50 00
LDAA
; Read data
$5000
A700
STAA
X
; Store i t at X
3B
RTI
TEMPl
; Starting address for
0200
FDB
$0200
; data storage
TEMP2
0000
FDB
$0000
; Reini tial1ze TEMPl
CE 02 00
ENDP
LDX
#$0200
DF34
TEMPl
STX
LDX
DE 36
TEMP2
RTS
; Return from subroutine
39
; To user's program
0010
0012
0015
0018
OOlB
OOlC
OOlD
OOlF
0022
0024
0027
0028
002A
002C
002E
0031
0033
0034
0036
0038
003B
003D
003F
Note 1: In order for the microprocessor to service subroutines and interrupts, the stack pointer must be dimensioned in the user's program.
18
19
CBl
CB2
10k
1
1
2
J.,
~
4
5
6
ANALOG
INPUTS
7
,_ .... -!....
150 PF
T
tb~
CS
V
VCC ~5V
19
CLKR
DBO 18
iili
\Vii
11
VIN(»
DB3 15
13
VIN(-)
AGND
DB414
14
DB5 13
15
DB6 12
16
DB7 11
17
INTH
AID
~ VREFi2
10
10
DBI 17
DB2 16
eLK IN
D GND
12
PBO
PIA
PBI
PB2
PB3
PB4
PB5
PB6
PB7
TL/H/5671-25
FIGURE 15. ADC0801-MC6820 PIA Interface
3-39
....0
.......
»
C
0
0
CD
0
N
.......
»
C
0
0
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0
Co)
.......
»
C
0
0
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C)
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c
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RX
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17"
o
4Jk
-12V
.....
if
V"
01:100
»
c
5VOC
lOOk
if
5W'
oo
2DOk
ii4 FRnMOUTPUl
"Ok
V"
if
PORT BlUfFER
IFIGURE111
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1IIlk
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if
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FRD. DUTPUT
PORTC
'fiGURE lSI
.".
!U
SW4
ff'-~----------------------------------------------~----"
Note 1: R2
~
49.5 R1
Note 2: Switches are LMC13334 CMOS analog switches.
Note 3: The 9 resistors used in the auto-zero section can be ±5% tolerance.
FIGURE 17. Gain of 100 Differential Transducer Preamp
Ali B5
T5
itf ..
8010AADOilESSBUS
INVERTING
ADDRESS
BUFFERS
{ j B3
~B2
T4
OMB131
TZ
At Bl
iIr"
OUTPUT
T1
TO
•
'V
CS
AURD AO
AID OUTPUT DATA
ADRI AI
D7
D;
'"
RIC
f-;J;
150 P
D}
•
~
TO "SAAN
RESISTORS
Ei TO SWI
ClTO SW2
TUH/5671-27
FIGURE 18. Microprocessor Interface Circuitry for Differential Preamp
3-43
io
(.)
C
~
o
CO
o
A flow chart for the zeroing subroutine is shown in Figure
19. It must be noted that the ADC0801 series will output an
all zero code when it converts a negative input [V IN( -) <:
VIN( + )1. Also, a logic inversion exists as all of the I/O ports
are buffered with inverting gates.
C
Basically, if the data read is zero, the differential output voltage is negative, so a bit in Port B is cleared to pull Vx more
negative which will make the output more positive for the
next conversion. If the data read is not zero, the output voltage is positive so a bit in Port B is set to make Vx more
positive and the output more negative. This continues for 8
approximations and the differential output eventually converges to within 5 mV of zero.
co
The actual program is given in Figure 20. All addresses
used are compatible with the BLC 80/10 microcomputer
system. In particular:
o
c
~
acoo
(.)
~
o
o
(.)
Port A and the ADC0801 are at port address E4
C
Port B is at port address E5
3DOO
3D02
3D04
3D06
3D07
3D09
3DOB
3DOD
3DOE
3DlO
3D13
3D15
3D16
3D17
3D1A
3D1B
3D1D
3D20
3D21
3D23
3D24
3D26
3D29
3D2A
3D2D
3D2E
3D2F
3D30
3D33
3D34
3D37
3D38
3D39
3D3B
3E90
D3E7
2601
7C
D3E6
0680
3E7F
4F
D3E5
31AA3D
D3E4
FB
00
C3163D
7A
C600
CA2D3D
78
F600
IF
FEOO
CA373D
47
C3333D
79
BO
4F
C3203D
A9
C30D3D
47
7C
EE03
D3E6
MVI90
Out Control Port
MVI H 01
MOVA,H
OUT C
MVI B 80
MVI A 7F
MOV C,A
OUT B
LXI SP 3DAA
OUTA
IE
NOP
JMP Loop
MOV A,D
ADIOO
JZ Set C
MOVA,B
ORIOO
RAR
CPIOO
JZDone
MOV B,A
JMPNewC
MOVA,C
ORAB
MOV C,A
JMP Shift B
XRAC
JMPReturn
MOVB,A
MOV A,H
XRI03
OUT C
3D3D
C
; Program PPI
Auto-Zero Subroutine
; Close SWl open SW2
; Ini tialize SAR bi t pointer
; Ini tialize SAR code
Return
; Port B = SAR code
; Dimension stack pointer
; Start AID
Start
Loop
; Loop until INT asserted
0
0
00
0
.....
.......
l>
C
0
0
00
0
I\)
.......
l>
C
0
0
00
0
W
.......
l>
Auto-Zero
; Test AID output data for zero
Shift B
;
;
;
;
Clear carry
Shi ft "1" in B right one place
Is B zero? I f yes last
approximation has been made
C
0
0
00
0
,j:o,
.......
l>
C
0
0
00
0
U1
Set C
; Set bi t in C that is in same
; position as "1" inB
NewC
;
;
;
;
;
;
Done
Clear bi t in C that is in
same posi tion as "1" in B
then output new SAR code.
Open SW1, close SW2 then
proceed wi th program. Preamp
is now zeroed.
Normal
0
3C3D
3C3F
3C41
3C42
3C43
3C45
3C48
DBE4
EEFF
57
78
E6FF
C21A3D
C33D3D
Program for processing
proper data values
INA
XRI FF
MOVD,A
MOV A,B
ANI FF
JNZ Auto-Zero
JMPNormal
Read AID Subroutine
; Read AID data
; Invert data
; Is B Reg = O? I f not stay
; in auto zero subroutine
Note: All numerical values are hexadecimal representations.
FIGURE 20. Software for Auto-Zeroed Differential AID
5.3 Multiple AID Converters in a Z-80® Interrupt Driven
Mode (Continued)
The following notes apply:
5) The peripherals of concern are mapped into 1/0 space
with the following port assignments:
1) It is assumed that the CPU automatically performs a RST
7 instruction when a valid interrupt is acknowledged (CPU
is in interrupt mode 1). Hence, the subroutine starting address of X0038.
HEX PORT ADDRESS
00
01
2) The address bus from the Z-80 and the data bus to the Z80 are assumed to be inverted by bus drivers.
02
03
04
05
06
07
3) AID data and identifying words will be stored in sequential memory locations starting at the arbitrarily chosen address X 3EOO.
4) The stack pointer must be dimensioned in the main program as the RST 7 instruction automatically pushes the
PC onto the stack and the subroutine uses an additional
6 stack addresses.
PERIPHERAL
MM74C374 8-bit flip-flop
AID 1
AID 2
AID 3
A/D4
A/D5
AID 6
A/D7
This port address also serves as the AID identifying word in
the program.
3-45
•
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C)
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IV
.1
IITtI
'- ~"·~n
OM1'"
c:c
.....
"1:1'
C)
~
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c:c
.....
DB7
~
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IliTli
II
JiIi AI1I •
lift
.. r-D'
Oil
: MM7ee37"
OJ
D.
D.
OUT,DJ
CLiI.
OIS.DI
eLKIN
r--
IITtI
~IV
JiIi AI1I'
II
-Ak;
~
~
'"
C)
co
C)
o
c
~
.....
-
IlII
o
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•
c:c
•
,
.
DI
,
D.
D'
IITtI
II
1m AiDe
IlII
I-
D:I
D'
elKIN
IIITlI
II
l1li AlDi
IiI\
va
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.,
cue IN
"J
C)
II
JiIi AI1Il
lift
CU,IN
:~
t-DA,;m-: .,
C")
C)
r--
YO
DO
;,1-
eLKIN
IIM14LS131
GI
]
)0- G"
]
10--
."
"
1m
y,
II
l1li AID I
lift
rI-
Y2
0:0
D'
CLKIIil
Yl
1m
II
IRi AID 7
IiII
YO
DO
;,-
f::ClKR
;J;JlPF
r-
elKIN
TLlH/5671-29
FIGURE 21. Multiple AIDs with z·ao Type Microprocessor
INTERRUPT SERVICING SUBROUTINE
SOURCE
LOC
OBJCODE
STATEMENT
COMMENT
0038
0039
003A
003B
003E
0040
0042
0044
0045
0046
0048
004B
004C
004D
004E
0051
005'2
0055
0057
0059
005A
005B
005C
005D
0060
0061
0062
0063
E5
C5
F5
2l003E
OEOl
D300
DBOO
47
79
FE 08
CA6000
78
IF
47
DA5500
OC
C34500
ED 78
EEFF
77
2C
71
2C
C3 51 00
Fl
Cl
El
C9
TEST
PUSHHL
PUSHBC
PUSHAF
LD (HL) ,X3EOO
LD C, XOl
OUTXOO, A
INA, XOO
LDB,A
LDA,C
CP, X08
JPZ, DONE
LDA,B
RRA
NEXT
LOAD
DONE
LDB,A
JPC, LOAD
INC C
JP,TEST
INA, (C)
XORFF
LD (HL) ,A
INCL
; Save contents of all registers affected by
; this subroutine.
; Assumed INT mode 1 earlier set.
; Initialize memory pointer where data will be stored.
; C register will be port ADDR of AID converters.
; Load peripheral status word into 8-bi t latch.
; Load status word into accumulator.
; Save the status word.
; Test to see i f the status of all AID I shave
; been cheeked. If so , exit subroutine
; Test a single bi t in status word by looking for
; a "1ft to be rotated into the CARRY (an INT
; is loaded as a "1"). I f CARRY is set then load
; contents of AID at port ADDR in C register.
; If CARRY is not set, increment C register to point
; to next AID, then test next bit in status word.
; Read data from interrupting AID and invert
; the data.
; Store the data
LD (HL) ,C
; Store AID identifier (AID port ADDR) •
INCL
JP,NEXT
POPAF
POPBC
POPHL
; Test next bit in status word.
; Re-establish all registers as they were
; before the interrupt.
RET
; Return to original program
3·46
:J>
c
Ordering Information
o
C)
TEMP RANGE
ERROR
O'CTO 70'C
±%Bit
Adjusted
±%Bit
Unadjusted
±%Bit
Adjusted
±1Bit
Unadjusted
O'CT070'C
+ 85'C
0)
ADC0801LCN
....
......
- 40'C TO
O'CTO 70'C
C)
:J>
ADC0802LCWM
ADC0802LCV
ADC0802LCN
c
oC)
ADC0803LCWM
ADC0803LCV
ADC0803LCN
N
ADC0804LCWM
ADC0804LCV
M20B-Small Outline
V20A-Chip Carrier
0)
C)
ADCOB04LCN
ADCOB05LCN
......
:J>
c
oC)
0)
PACKAGE OUTLINE
TEMP RANGE
ERROR
- 40'C TO
± % Bit Adjusted
± % Bit Unadjusted
± % Bit Adjusted
± 1Bit Unadjusted
+ 85'C
N20A-Molded DIP
-55'CTO
C)
Co)
......
:J>
c
oC)
+ 125'C
0)
C)
01:00
......
ADC0801LCJ
ADC0802LCJ
ADC0803LCJ
ADC0804LCJ
ADC0801LJ
ADC0802LJ
J20A-Cavily DIP
J20A-Cavity DIP
:J>
C
oC)
0)
C)
PACKAGE OUTLINE
en
Connection Diagrams
ADC080X
Dual·ln·Line and Small Outline (SO) Packages
CS-l
\..../
Rii-2
20 f- Vee (OR VREF)
19 f-ClKR
WR-3
18 rDBO (lSB)
CLKIN- 4
17 r-DBI
INTR- 5
16 r-DB2
V1N(+)- 6
15 -DB3
V1k)-7
AGND- 8
14 -DB4
VREF/2- 9
DGND- 10
12 -DB6
ADC080X
Molded Chip Carrier (PCC) Package
ClKR- 19
Vee (OR VREF) -
CS-
18 17 16 15 14
13 -DB5
20
12 - DB6
1
11
-DB7(t.lSB)
10 -DGND
9 - VREF/2
5
13 -DB5
6
7
8
11 -DB7 (t.lSB)
TLlH/5671-32
TLlH/5671-30
See Ordering Information
3-47
•
CD ,----------------------------------------------------------------------------,
Q
8
~National
~ ~ Semiconductor
CIO
~
.
8 ADC08081 ADC0809 8-Bit JLP Compatible AID Converters
5i! with 8-Channel Multiplexer
General Description
Features
The ADC0808, ADC0809 data acquisition component is a
monolithic CMOS device with an 8-bit analog-to-digital converter, 8-channel multiplexer and microprocessor compatible control logic. The 8-bit A/D converter uses successive
approximation as the conversion technique. The converter
features a high impedance chopper stabilized comparator, a
256R voltage divider with analog switch tree and a successive approximation register. The 8-channel multiplexer can
directly access any of 8-single-ended analog signals.
• Easy interface to all microprocessors
• Operates ratiometrically or with 5 VOC or analog span
adjusted voltage reference
• No zero or full-scale adjust required
• 8-channel multiplexer with address logic
• OV to 5V input range with Single 5V power supply
• Outputs meet TTL voltage level specifications
• Standard hermetic or molded 28-pin DIP package
• 28-pin molded chip carrier package
• ADC0808 equivalent to MM74C949
• ADC0809 equjvalent to MM74C949-1
The device eliminates the need for external zero and fullscale adjustments. Easy interfacing to microprocessors is
provided by the latched and decoded multiplexer address
inputs and latched TTL TRI-STATE® outputs.
The design of the ADC0808, ADC0809 has been optimized
by incorporating the most desirable aspects of several AID
conversion techniques. The ADC0808, ADC0809 offers high
speed, high accuracy, minimal temperature dependence,
excellent long-term accuracy and repeatability, and consumes minimal power. These features make this device
ideally suited to applications from process and machine
control to consumer and automotive applications. For 16channel multiplexer with common output (sample/hold port)
see ADC0816 data sheet. (See AN-247 for more information.)
Key Specifications
•
•
•
•
•
Block Diagram
Resolution
Total Unadjusted Error
Single Supply
Low Power
Conversion Time
START
r..~.Vo
I
8 Bits
± Yo LSB and .± 1 LSB
5 Voc
15 mW
100 JLs
CLDCK
- - -.....- _ . 1 - _ - - 1 _.......
I
I
I
I
I
• ANALOG INPUTS
ADDRESS
LATCH ENABLE
ADDRESS
LATCH
AND
DECODER
See Ordering
Information
11
VCC
GND
TUH/5672-1
3-48
Absolute Maximum Ratings (Notes 1 & 2)
Operating Conditions (Notes 1 & 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Temperature Range (Note 1)
Supply Voltage (Vee! (Note 3)
Voltage at Any Pin
Except Control Inputs
TMIN,;;;TA,;;;TMAX
-55'C,;;;TA';; + 125'C
ADC0808CJ
ADC0808CCJ, ADC0808CCN,
ADC0809CCN
ADC0808CCV, ADC0809CCV
6.5V
-0.3V to (Vee+0.3V)
Range of Vee (Note 1)
4.5 Voe to 6.0 Voe
Voltage at Control Inputs
-0.3V to + 15V
(START, OE, CLOCK, ALE, ADD A, ADD B, ADD C)
Storage Temperature Range
-40'C,;;TA';; +85'C
-40'C,;;; TA';;; +85'C
- 65'C to + 150'C
Package Dissipation at TA = 25'C
Lead Temp. (Soldering, 10 seconds)
Dual-In-Line Package (plastic)
Dual-In-Line Package (ceramic)
Molded Chip Carrier Package
Vapor Phase (60 seconds)
Infrared (15 seconds)
ESD Susceptibility (Note 11)
875mW
260'C
300'C
215'C
220'C
400V
Electrical Characteristics
Converter Specifications: Vee=5 Voe=VREF+, VREF(-)=GND, TMIN,;;TA,;;TMAX and feLK=640 kHz unless otherwise
stated.
Max
Units
25'C
TMINtoTMAX
±y.
±%
LSB
LSB
ADC0809
Total Unadjusted Error
(Note 5)
O'Ct070'C
TMINtoTMAX
±1
±1%
LSB
LSB
Vcc+ 0.1O
Voe
Vee
Vee+ 0.1
V
Vee /2
Vcc/2 + O.1
V
2
",A
Symbol
Parameter
ADC0808
Total Unadjusted Error
(Note 5)
Conditions
Min
Typ
Input Resistance
From Ref( + ) to Ref( -)
1.0
Analog Input Voltage Range
(Note 4) V( + ) or V( - )
GND-0.10
VREF(+)
Voltage, Top of Ladder
Measured at Ref( + )
VREFI+I+VREFI-1
2
Voltage, Center of Ladder
VREF(-)
Voltage, Bottom of Ladder
Measured at Ref( -)
-0.1
0
liN
Comparator Input Current
fc = 640 kHz, (Note 6)
-2
±0.5
Vee/2-0.1
kO
2.5
V
Electrical Characteristics
Digital Levels and DC Specifications: ADC0808CJ 4.5V';; Vee';; 5.5V, -55'C,;;TA';;;+125'C unless otherwise noted
ADC0808CCJ, ADC0808CCN, ADCOS08CCV, ADCOS09CCN and ADCOS09CCV, 4.75,;;Vee,;;5.25V, -40'C';;TA';; +S5'C unless otherwise noted
.
Symbol
Parameter
Conditions
OFF Channel Leakage Current
Vee=5V, VIN=5V,
TA=25'C
TMINto TMAX
Min
Typ
Max
Units
10
200
1.0
nA
",A
ANALOG MULTIPLEXER
IOFF(+)
IOFF(-)
OFF Channel Leakage Current
Vee=5V, VIN=O,
TA=25'C
TMINto TMAX
3-49
-200
-1.0
-10
nA
",A
»
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CO
o
o
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CO
o
o
C
:
....... '"
...... g
0",
j5 S~ '"
en
z
0
0
~
0
I-
::>
C1.
I-
::>
0
TL/H/5672-11
Order Number ADC0808CCN, ADC0809CCN,
ADC0808CCJ or ADC0808CJ
See NS Package J28A or N28A
TUH/5672-12
Order Number ADC0808CCV or ADC0809CCV
See NS Package V28A
Timing Diagram
r-'N-j
CLDCK
.
,
START
r--\
,
50.
1-""
'''~H_I
ALE
I
----J -twALE
ADDRESS
...
1--
STABLE ..DRESS
I
.
sa•
..
I
'
ANALOG
INPUT
;
STABLE
~~f.COMPARATOR
'0-
DunUT
/
I
ENABLE
EDC
x. . . __
:
IN'UT
(INTERNAL NODE)
'--
X
---tro .t
e
I
tc
"'1
OUTPUTS _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 2.R!!'~E_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _{'__ _ _ _ ___'}-
TL/H/5672-4
FIGURE 5
3-53
0) , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,
o
CO
o
o
cc(
Typical Performance Characteristics
......
co
o
CO
o
o
cc(
j
1.5
,---,----,r--,....--,.
0.5
f---+---ji--.F-f-::.,.4!'-j
g
Z
Q
II:
....
....
'"'"a::
~ -0.5
'"'"a::
i--:V'''f--P--i--+--j
>
I-
-1
1.25
2.5
o "--_-'-_--'-_ _"--_....1
o
1.25
2.5
3.75
3.75
VIN(V)
VIN (VI
TLlH15672-5
FIGURE 6. Comparator liN vs VIN
(Vee = VREF= 5V)
FIGURE 7. Multiplexer RON vs VIN
(Vee=VREF=5V)
TRI-STATE Test Circuits and Timing Diagrams
Vee
OUTPUT
ENABLE
GNO --.!'~1'-----OUTPUT
ENABLE
VOH~~IH
~
OUTPUT
------Jf-so%-
GNO - - - - - - - - - - - "
tOH. tHO
Vee
Vee
Vee
10k
OUTPUT
ENABLE
GNO
OUTPUT
ENABLE
OH
eL
':"
r
Vee
OUTPUT
~
--
VOL
10%
TLlH15672-6
FIGURES
3·54
Applications Information
Ratiometric transducers such as potentiometers, strain
gauges, thermistor bridges, pressure transducers, etc., are
suitable for measuring proportional relationships; however,
many types of measurements must be referred to an absolute standard such as voltage or current. This means a system reference must be used which relates the full··scale
voltage to the standard volt. For example, if
VCC=VREF=5.12V, then the full-scale range is divided into
256 standard steps. The smallest standard step is 1 LSB
which is then 20 mY.
OPERATION
1.0 RATIOMETRIC CONVERSION
The ADC0808, ADC0809 is designed as a complete Data
Acquisition System (DAS) for ratio metric conversion sys·
tems. In ratiometric systems, the physical variable being
measured is expressed as a percentage of full-scale which
is not necessarily related to an absolute standard. The voltage input to the ADC0808 is expressed by the equation
VIN
Dx
VIs-VZ DMAX-DMIN
VIN = Input voltage into the ADC0808
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......
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ID
2.0 RESISTOR LADDER LIMITATIONS
The voltages from the resistor ladder are compared to the
selected into 8 times in a conversion. These voltages are
coupled to the comparator via an analog switch tree which
is referenced to the supply. The voltages at the top, center
and bottom of the ladder must be controlled to maintain
proper operation.
The top of the ladder, Ref( +), should not be more positive
than the supply, and the bottom of the ladder, Ref( -),
should not be more negative than ground. The center of the
ladder voltage must also be near the center of the supply
because the analog switch tree changes from N-channel
switches to P-channel switches. These limitations are automatically satisfied in ratiometric systems and can be easily
met in ground referenced systems.
Figure 10 shows a ground referenced system with a separate supply and reference. In this system, the supply must
be trimmed to match the reference voltage. For instance, if
a 5.12V is used, the supply should be adjusted to the same
voltage within 0.1V.
(1)
Vis = Full-scale voltage
Vz = Zero voltage
DX = Data point being measured
DMAX=Maximum data limit
DMIN = Minimum data limit
A good example of a ratio metric transducer is a potentiometer used as a position sensor. The position of the wiper is
directly proportional to the output voltage which is a ratio of
the full-scale voltage across it. Since the data is represented as a proportion of full-scale, reference requirements are
greatly reduced, eliminating a large source of error and cost
for many applications. A major advantage of the ADC0808,
ADC0809 is that the input voltage range is equal to the supply range so the transducers can be connected directly
across the supply and their outputs connected directly into
the multiplexer inputs, (Figure 9).
r---~P---~,""""--""--1Vcc
REFI_)
MSB
.
~"'---+---"""I------Iln1
•
DIGITAL
OUTPUT
PROPORTIONAL
TO ANALOG
INPUT
DOUT
Q
-~-~
OUT- VREF - Vce
4.75V"Vce=VREF,,5.25V
ADCOBOB
* Ratlometrlc transducers
FIGURE 9. Ratiometric Conversion System
3-55
TL/H/5672-7
G)
c
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CD
C
CD
C
o
cc(
Applications Information
(Continued)
The ADC0606 needs less than a milliamp of supply current
so develop.ing the supply from the reference is readily. accomplished. In Figure 11 a ground referenced system is
shown which generates the supply from the reference. The
buffer shown can be an op amp of sufficient drive to supply
the milliamp of supply current and the desired bus drive, or if
a capacitive bus is driven by the outputs a large capacitor
will supply the transient supply current as seen in Figure 12.
The LM301 is overcompensated to insure stability when
loaded by the 10 ",F output capacitor.
The top and bottom ladder voltages cannot exceed Vee
and ground, respectively, but they can be symmetrically less
than Vee and greater than ground. The center of the ladder
voltage should always be near the center of the supply. The
sensitivity of the converter can be increased, (i.e., size of
the LSB steps decreased) by using a symmetrical reference
system. In Figure 13, a 2.5V reference is symmetrically centered about Vee/2 since the same current flows in identical
resistors. This system with a 2.5V reference allows the LSB
bit to be half the size of a 5V reference system.
I---------ivcc
1------1 REF(+)
DIGITAL
OUTPUT
REFERENCED
TO
GROUND
··•
In7
InO
REFf-)
QOUT~~
~--~t---~-~~~GNO
ADCOIHIB
.
4.7SV
VREF
';vc~ ~
VREF ,; S.2SV
FIGURE 10. Ground Referenced
Conversion System Using Trimmed Supply
>-....--I~cc
1---. .-----------1 REF (+)
DIGITAL OUTPUT
REFERENCED TO
GROUND
··
In7
InO
REFH
~--------------------~~~GND
QOUT~~
VREF
4.7SV ,;
vee
~
VREF ,; S.2SV
ADCOBOB
TUH/5672-8
FIGURE 11: Ground Referenced Conversion System with
Reference Generating Vee Supply
3-56
:J>
Applications Information
o
oo
(Continued)
10-15 Voe
CD
o
CD
lk
l>
o
oo
1000 pF
Rl
CD
o
co
LMl29B
Vee
RZ
>.....fj_...
lOT
-~REF(+)
Rl
DIGITAL OUTPUT
PROPORTIONAL TO
ANALOG INPUT
I.ZSV $ VIN $ l.7SV
RA~R8
*Ratiometric transducers
TUH/5672-9
FIGURE 13. Symmetrically Centered Reference
3.0 CONVERTER EQUATIONS
4.0 ANALOG COMPARATOR INPUTS
The transition between adjacent codes Nand N + 1 is given
by:
The dynamic comparator input current is caused by the periodic switching of on-chip stray capacitances. These are
connected alternately to the output of the resistor ladder/
switch tree network and to the comparator input as part of
the operation of the chopper stabilized comparator.
VIN~ { (VAEF(+)-VAEF(-)[2~6 +
s:J
±VTUE } +VAEF(-)
(2)
The center of an output code N is given by:
VIN{
(VAEF(+)-VAEF(-)[2~6] ±VTUE} +VAEF(-)
The average value of the comparator input current varies
directly with clock frequency and with VIN as shown in Figure6.
(3)
The output code N for an arbitrary input are the integers
within the range:
N
VIN-VAEF(-I x256±AbsoluteAccuracy
VAEF(+)-VAEF(-)
If no filter capacitors are used at the analog inputs and the
signal source impedances are low, the comparator input
current should not introduce converter errors, as the transient created by the capacitance discharge will die out before the comparator output is strobed.
(4)
where: VIN=Voltage at comparator input
VREF(+) = Voltage at Ref(+)
VREF(-) = Voltage at Ref(-)
If input filter capacitors are desired for noise reduction and
signal conditioning they will tend to average out the dynamic
comparator input current. It will then take on the characteristics of a DC bias current whose effect can be predicted
conventionally.
VrUE=Total unadjusted error voltage (typically
VREF(+) + 512)
3-57
•
G)
g
8c
Typical Application
2 eR/W
MEMW
WR
WR
NWDS
VMA-<1>eR/W
INTR (Thru RST Circuit)
INTR (Thru RST Circuit)
INT (Thru RST Circuit, Mode 0)
SA (Thru Sense A)
IRQA or IRQB (Thru PIA)
Ordering Information
TEMPERATURE RANGE
E
rror
I
I
-40'Cto +85"C
± Yz LSB Unadjusted
ADC0808CCN
± 1 LSB Unadjusted
ADC0809CCN
ADC0809CCV
N28A Molded DIP
V28A Molded Chip Carrier
Package Outline
ADC0808CCV
3-58
-55'C to + 125'C
ADC0808CCJ
ADC0808CJ
J28A Ceramic DIP
J28A Ceramic DIP
r---------------------------------------------------------------,~
C
oo
00
.....
.....
~National
~ Semiconductor
ADC0811 8-Bit Serial 1/0 AID Converter
With 11-Channel Multiplexer
General Description
The ADC0811 is an 8-Bit successive approximation AID
converter with simultaneous serial 110. The serial input controls an analog multiplexer which selects from 11 input
channels or an internal half scale test voltage.
An input sample-and-hold is implemented by a capacitive
reference ladder and sampled data comparator. This allows
the input signal to vary during the conversion cycle.
Separate serial 110 and conversion clock inputs are provided to facilitate the interface to various microprocessors.
Features
II Separate asynchronous converter clock and serial data
110 clock.
III 11-Channel multiplexer with 4-Bit serial address logic.
III Built-in sample and hold function.
Connection Diagrams
II Ratiometric or absolute voltage referencing.
II No zero or full-scale adjust required.
II Internally addressable test voltage.
II OV to 5V input range with single 5V power supply.
II TTL/MaS input/output compatible.
II 0.3" standard width 20-pin dip or 20-pin molded chip
carrier
Key Specifications
20
VCC
CHI
19
q,'CLK
± 'l2LSB and ± 1LSB
5VDC
15 mW
32 ",S
Functional Diagram
Dual-In-Line Package
CHO
8-Bits
II Resolution
II Total unadjusted error
II Single supply
II Low Power
II Conversion Time
VCC
120
01'
CH2
18
SCLK
CH3
17
01
CH4
16
DO
CH5
cs
CH6
VREF
CH7
AGND
CH8
GND
ADDRESS
LATCH AND
DECODElI
1+_-+___.....;.;;.15 cs
CONTROL
AND
TIMING
1+_-1_...._-=18 SCLK
CHO
CHID
10
ANALOG
INPUT
MUX
CH9
Top View
TL1H/5587 -1
L.._ _ _ _ _ _ _1;,;;,9 q,'CLK
Molded Chip Carrier (PCC) Package
SCLK 01
DO
cs
VREF
14
. - - - - - - - - ' " " VREF
q,'CLK
AGND
VCC
12
CHID
CHo
CH9
CHI
GNo
CH2
CH8
!lrEST
110
GND
1
13
AGND
TL/H/55B7-3
CH3 CH4 CH5 CH6 CH7
Top View
TL1H/55B7-2
Order Number ADC0811J,N,V
See NS Packages J20A, N20A, V20A
Use Ordering Information
3-59
•
....CC)
8
c
6.5V
Voltage
Inputs and Outputs
-0.3Vto Vcc +0.3V
±5mA
Input Current Per Pin (Note 3)
Total Package Input Current (Note 3)
±20mA
Storage Temperature
-65·Cto + 150·C
Package Dissipation at T A = 25·C
875mW
2600C
3000C
215·C
220·C
ESD Susceptibility (Note 11)
2000V
Operating Ratings (Notes 1 & 2)
Supply Voltage (Vee>
Temperature Range
ADC0811 BCN, ADC0811CCN
ADCOB11 BCJ, ADCOB11 BCV
ADCOB11 CCJ, ADCOB11 CCV
ADCOB11 BJ, ADCOB11CJ
4.5 Voe to 6.0 Voe
TMINS:TAS:TMAX
0·CS:TAs:70·C
-400CS:TAS:B5·C
-40·CS:TAS:B5·C
-55·CS:TAS:125·C
Electrical Characteristics
The following specifications apply for Vee = 4.75V to 5.25V, VREF = +4.6V to (Vee + 0.1V), 2 eLK = 2.097 MHz unless
otherwise specified. Boldface limits apply from TMIN to TMAX; all other limits TA = TJ = 25·C.
ADC0811BCJ, ADC0811 BJ
ADC0811CCJ, ADC0811CJ
Parameter
Conditions
Typical
(Note 6)
Tested
Limit
(Note 7)
ADC0811BCN, ADC0811BCV
ADC0811CCN, ADC0811CCV
Design
Typical
Limit
(Note 6)
(Note 8)
Tested
Limit
(Note 7)
Design
Limit
(Note 8)
Units
±y.
±y,.
±1
±1
LSB
LSB
LSB
LSB
CONVERTER AND MULTIPLEXER CHARACTERISTICS
Maximum Total
VREF= 5.00 Voe
Unadjusted Error
(Note 4)
ADC0811 BCN, ADC0811 BCV
ADC0811 BCJ, ADC0811 BJ
ADC0811 CCN, ADC0811 CCV
ADCOB11CCJ,ADCOB11CJ
±y,.
±1
Minimum Reference
Input Resistance
8
Maximum Reference
Input Resistance
8
Maximum Analog Input Range
(Note 5)
Minimum Analog Input Range
On Channel Leakage Current
ADCOB11 BCJ, CCJ, BCN, CCN, On Channel = 5V
BCV,CCV Off Channel = OV
ADC0811CJ, BJ
ADCOB11 BCJ, CCJ. BCN. CCN. On Channel = OV
BCV,CCV Off Channel = 5V
ADC0811 BJ, CJ
(Note 9)
Off Channel Leakage Current
ADC0811 BCJ, CCJ, BCN, CCN, On Channel = 5V
BCV,CCV Off Channel = OV
ADC0811CJ, BJ
ADC0811 BCJ, CCJ, BCN, CCN, On Channel = OV
BCV,CCV Off Channel = 5V
ADCOB11BJ, CJ
(Note 9)
5
11
B
B
11
5
kO
11
kO
Vee + 0.05
Vcc+ O.05 Vee + 0.05
V
GND-0.05
GND-0.05 GND-0.05
V
1000
400
1000
1000
-1000
nA
-400
-1000
-1000
-1000
nA
nA
-400
1000
-1000
1000
nA
nA
nA
400
1000
nA
1000
nA
Minimum VTEST
Internal Test Voltage
VREF=Vee,
CH 11 Selected
125
125
125
(Note 10)
Counts
Maximum VTEST
Internal Test Voltage
VREF = Vee,
CH 11 Selected
130
130 .
130
(Note 10)
Counts
3-60
»
Electrical Characteristics
The following specifications apply for VCC = 4.75V to 5.25V. VREF = +4.6V to (VCC + O.W). 2 ClK = 2.097 MHz unless
otherwise specified. Boldface limits apply from TMIN to TMAX; all other limits TA = TJ = 25'C. (Continued)
ADC0811 BCJ, ADC0811 BJ
ADC0811CCJ, ADC0811CJ
Parameter
Conditions
Typical
(Note S)
Tested
Limit
(Note 7)
ADC0811BCN,ADC0811BCV
ADC0811CCN, ADC0811CCV
Design
Limit
(Note 8)
Typical
(NoteS)
Tested
Limit
(Note 7)
Design
Limit
(Note 8)
Units
DIGITAL AND DC CHARACTERISTICS
VIN(1). Logical "1" Input
Voltage (Min)
Vcc=5.25V
2.0
2.0
2.0
V
VIN(O). Logical "0" Input
Voltage (Max)
VCC= 4.75V
0.8
0.8
0.8
V
IIN(1). Logical "1" Input
Current (Max)
VIN=5.0V
IIN(O). Logical "0" Input
Current (Max)
VIN=OV
VOUT(1). Logical "1"
Output Voltage (Min)
Vcc=4.75V
IOUT= -360 p.A
IOUT= -10 /J-A
VOUT(O). Logical "0"
Output Voltage (Max)
Vcc=5.25V
IOUT=1.6mA
lOUT. TRI-STATE Output
Current (Max)
VOUT=OV
VOUT=5V
-0.01
0.01
ISOURCE. Output Source
Current (Min)
VOUT=OV
0.005
2.5
0.005
2.5
2.5
p.A
-0.005
-2.5
-0.005
2.5
-2.5
p.A
2.4
4.5
2.4
4.5
0.4
V
V
p.A
p.A
mA
2.4
4.5
0.4
0.4
-0.01
0.01
-3
3
-12
-3
3
-6.5
-14
-6.5
-3
3
-6.5
V
ISINK. Output Sink Current (Min)
VOUT=VCC
18
8.0
16
8.0
8.0
mA
Icc. Supply Current (Max)
CS = 1. VREF Open
1
2.5
1
2.5
mA
IREF(Max)
VREF=5V
0.7
1
0.7
1
2.5
1
mA
AC CHARACTERISTICS
Parameter
2 ClK. 2 Clock Frequency
SClK. Serial Data Clock
Frequency
T C. Conversion Process Time
tACC. Access Time Delay From CS
Falling Edge to DO Data Valid
Conditions
Typical
(Note 6)
0.70
3.0
2.0
2.1
MAX
700
525
525
MIN
48
48
64
64
MHz
5.0
MIN
I-Not Including MUX
Addressing and
r - - Analog Input
MAX
Sampling Times
MIN
1
MAX
3
r--
KHz
2 cycles
2 cycles
1
412CLK+~
sec
0
ns
CLK
~
MAX
tHDO. Minimum DO Hold Time from SClK
Falling Edge
Units
1.0
MIN
tHCS. CS Hold Time After the Falling
Edge of SClK
tHDI. Minimum 01 Hold Time from
SClK Rising Edge
Design
Limit
(Note 8)
MAX
r--
tSET-UP. Minimum Set-up Time of CS Falling
Edge to SClK Rising Edge
t CS. Total CS Low Time
Tested
Limit
(Note 7)
0
Rl =30k.
Cl =100 pF
3-S1
tset.up + 8/SCLK
sec
tcs(min) + 48/2CLK
sec
0
ns
10
ns
c
oo
co
.....
.....
........
co
8
c
cC
Electrical Characteristics
The following specifications apply for Vee = 4.75V to 5.25V. VREF = +4.6V to (Vcc + 0.1V). 2 CLK = 2.097 MHz unless
otherwise specified. Boldface limits apply from T MIN to T MAX; all other limits T A = TJ = 25°C. (Continued)
Parameter
Tested
Limit
(Note 7)
Typical
(Note 6)
Conditions
Design
Limit
(Note 8)
Units
400
ns
AC CHARACTERISTICS (Continued)
tSDI. Minimum 01 Set-up Time to SCLK
Rising Edge
tODD. Maximum Delay From SCLK
Falling Edge to DO Data Valid
200
RL =30k.
CL=100pF
180
400
400
ns
90
150
150
ns
4/SCLK+1,.,.5
sec
tTRI. Maximum DO Hold Time.
(CS Rising edge to DO
TRI-STATE)
RL =3k.
CL =100pF
teA. Analog
Sampling Time
After Address Is Latched
CS=Low
tROD. Maximum DO
RL =30 kn.
"TRI-STATE" to "HIGH": State
75
150
150
Rise Time
CL=100pf
"LOW" to "HIGH" State
150
300
300
tFDO. Maximum DO
RL =30 kn.
"TRI-STATE" to "LOW" State
75
150
150
Fall Time
CL=100pf
"HIGH" to "LOW" State
150
300
300
CIN. Maximum Input
Analog Inputs. ANO-AN10 and VREF
11
55
Capacitance
All Others
5
15
ns
ns
pF
Note 1: Absolute Maximum Ratings indicate limtls beyond which damage to the device may occur. DC and AC electrical specHications do not apply when operating
the device beyond its specHied operating conditions.
Nole 2: All voltages are measured with respect to ground.
Note 3: Under over voltage conditions (VINVccl the maximum input current at anyone pin is ±5 rnA. If the voltage at more than one pin exceeds
Vee
+ .3V the total package current must be limited to 20 rnA. For example the maximum number of pins that can be over driven at the maximum current level of
±5 rnA is four.
Note 4: Total unadjusted efror includes offset, full-scale, linearity, multiplexer, and hold step errors.
Note 5: Two on-Chip diodes are tied to each analog input, which will forwardwconduct for analog input voltages one diode drop below ground or one diode drop
greater than Vee supply. Be careful during testing at low Vee levels (4.5V). as high level analog inputs (5V) can cause this input diode to conduct. especially at
elevated temperatures, and cause errors for analog inputs near fullwscale. The spec allows 50 mV forward bias of either diode. This means that as long as the
analog VIN does not exceed the supply voltage by more than 50 mV. the output code will be correct. To achieve an absolute 0 Voc to 5 Voc input voltage range will
therefore require a minimum supply voltage of 4.950 Voc over temperature variations, initial tolerance and loading.
Note 6: Typicals are at 25'C and represent most likely parametric norm.
Note 7: Guaranteed and 100% production tested under worst case condition.
Note 8: Guaranteed. but not 100% production tested. These limits are not used to calculate outgoing quality levels.
Note 9: Channel leakage current Is measured after the channel selection.
Note 10: I count = VREF/256.
Note 11: Human body model. 100 pF discharged through a 1.5 kn resistor.
Test Circuits
DO Except "TRI-STATE"
Leakage Current
5V
5.0V
TEST POINT
~----0- CHO (ON)
F..--r!.
I
I
CH NNEL
SELECT
CHI (OFF)
:
•
1. ~, ,r
.....
RL
CH2 (OFF)
2.2k
MMO 6150
OR EOUIVALENT
AOCOSlt 00
r;
,. MMD 7000
OR EQUIVALENT
,.
~
~ CH10 (OFF)
TLfHf5587-17
3-62
TL/Hf5587-6
»
c
Test Circuits (Continued)
oo
tTRI "TRI-STATE"
TEST
POINT
01)
.......
.......
5.0V
b
Rl
AOCOS11 DO
P
Cl
TL/H/5587 -22
Typical Performance Characteristics
Unadjusted Offset Error vs
VREF Voltage
16
~x
1.5
'~~+2;~~
14
1.Z5 _
i'"'"
I'" 12
....tI~ 10
~
~
'"co
'"
'"w
til
~
8
6
4
0.75
t:
:ilz
0.5
5
0
., 0.4
~
co
'" 0.3
0.5
Sell( = 525 kHz
<1>2=2.1 MHz
Vee = VREF = 5V
'"~
:s
iii>-
'"ffi
t:
:ilz
::l
0.2
S.
....
ill 15
ill
B
1
~~
2
3
VREF (V)
4
::l
0.1
~
ill
'"
~I
.ll
125°C
. .."
~1
25°C
.;.-
4
2
3
<1>, ClK (MHz)
1
:< 0.7
s.
I
w
'"
ill
I
4
-
125
ill
r--.
~
I""'-
i"""
Ii!
~
5
Vee -5.25V I
Vee =5.0V
I.....
I' :11 .....
....
....
"'" ,7-~
....
verrsi
Vee =4.SV
0.5
105
65
-55 -15
25
TEMPERATURE (OC)
Resistive Ladder Reference
Current vs Temperature
O.S
..,..
2
3
2(MHz)
"
I I I
VREF = Vee
_I. . ~ !v+: 4>, =2.1 MHz
\Vee =5.5V
SelK =525 kHz
II: 1.0
Vee = VREF = 5V
SelK =525 kHz
T.=25°C
0
1.5
I'"
SS°i:-
0
, ./
~
Power Supply Current
vs Temperature
1....
Power Supply Current vs
4>2 Clock Frequency
II:
IsouReE YoUT =2.4V
~
-
~
~CE YoUT -IOV
0
-100 -50
50
100
0
TEMP£RATURE (OC)
5
,-
IB
5
.l
Vee-5Voc
ISIMK YoUT = 5'1
ISIMK1UT =Oi 4V
0.3
i
-25
25
75
125
TEMPERATURE ("C)
1....
10
co
~
SelK = 525 kHz
Vee =VREF=5V
0.4
0.2
:z
0.1
1.5
1.4
1.3
1.Z
1.1
1_0
0.9
O.S
0.7
0.6
0.5
....
Linearity vs 4>2 Clock
Frequency
Linearity vs Temperature
0.5
"
0.25
"
:< 20
\
0
0.1
1.0
VREF (Voe)
25
<1>,-2.1 MH,
~ClK = 525 kHz
Vee=5V
T.=25'C
1.0
En
::l
2
0
0.01
Output Current vs
Temperature
Linearity Error vs VREF
Voltage
2=OV
SelK =OV
0.6
r--.
0.5
0.4
0.3
-55
5
vee=V~F=5V
-15
65
25
TEMPERATURE (OC)
105
TL/H/5587-16
3-63
EI
.,...
.,...
co
8
c
E~
DO
TLlH/5587-11
·Strobing CS High and Low will abort the present conversion and initiate a new serial 110 exchange.
Timing with a gated SCLK and CS Continuously Low
SCLK
Ci(LOW)
----------.-----+--------+--
OO ____D7_____~~---~-~-~~-"',~D-7-TLlH/5587-9
Using CS To TRI-8TATE DO
CONVERSION PROCESSSCLIC
~c(SEE NOTE)
TL/H/5587-10
Note: Strobing CS Low during this time interval will abort the conversion in process.
3-64
l>
c
oo
Timing Diagrams (Continued)
........
CO
CS High During Conversion
!.o-----
tCA
CHANNEL
--+-ACQUISITION-.....
(MIN)
+I. . - - - 6 4 <1>2 CLDCKS;---....
Seu<
~-,~
_______________r
_______________.J~
01
DO
TLlH/5587 -4
CS Low During Conversion
Seu<
~,~
______________________.__
------------------~r
,.--
48 <1>2 CLOCKS--I
DO
TLlH/5587-5
Note: DO and 01 lines share the S·bit 1/0 shift register(see Functional Block Diagram). Since the MUX address bits are shifted in on SCLK rising edges while SCLK
falling edges shift out conversion data on DO, the eighth falling edge of SCLK will shift out the MSB MUX address bit (A7) on DO. Thus, if addressing channels
CHS-CH10, a high DO will occur momentarily (one <1>2 clock period) until the S·bit I/O shift register is cleared by the internal EOC signal.
Channel Addressing Table
TABLE I. ADC 0811 Channel Addressing
MUXADDRESS
ANALOG CHANNEL
SELECTED
A7 A6 A5 A4 As A2 At AO
0
CHO
0
0
0
X X X X
0
0
0
1 X X X X
CH1
0
0
1
0
X X X X
CH2
1
CH3
0
0
1 X X X X
0
1 0
0
X X X X
CH4
0
1 0
1 X X X X
CH5
0
1
1 0
X X X X
CH6
0
1
1
1 X X X X
CH7
0
0
0
X X X X
CH8
1
0
0
1 X X X X
CH9
1
0
1 0
X X X X
CH10
1
1
0
1
1 X X X X
VTEST
1
1 X X X X X X LOGIC TEST MODE"
• Analog channel inputs CHO thru CH3 are logic outputs
3-65
•
ADC0811
."
C
:::s
n
0"
:::s
e!-
m
tP2
T.
TR
TS
0"
n
ICOMP
~
CONVERSION
TIMING GENERATORS
SAR
C
i"
i-+SAR
CC
iii
3
cc
SCU( 118]
-I
c.>
J
8l
tttttttFi
5~BIT BINARY
•
I
lEI
Va
01117
I ,
IiBJGNO
F--::t ,. I- I
illIAGNO
18100
TLiH/5587 -8
.----------------------------------------------------------------------.>
c
Functional Description
oo
CIQ
1.0 DIGITAL INTERFACE
.....
.....
this mux address/sample cycle, data from the last conversion is also clocked out on ~O. Since 07 was clocked out
on the falling edge of CS only data bits 06-00 remain to be
received. The following seven falling edges 01 SCLK shift out
this data on ~O.
The AOC0811 uses five input/output pins to implement the
serial interface. Taking chip select (CS) low enables the I/O
data lines (DO and 01) and the serial clock input (SCLK)' The
result of the last conversion is transmitted by the AID on the
DO line, while simultaneously the 01 line receives the address data that selects the mux channel for the next conversion. The mux address is shifted in on the rising edge of
SCLK and the conversion data is shifted out on the falling
edge. It takes eight SCLK cycles to complete the serial I/O.
A second clock (4)2) controls the SAR during the conversion
process and must be continuously enabled.
The 8th SCLK falling edge initiates the beginning of the AID's
actual conversion process which takes between 48 to 64 4>2
cycles (Tel. During this time CS can go high to TRI-STATE
DO and disable the SCLK input or it can remain low. If CS is
held Iowa new I/O exchange will not start until the conversion sequence has been completed, however once the conversion ends serial I/O will immediately begin. Since there is
an ambiguity in the conversion time (Tel synchronizing the
data exchange is impOSSible. Therefore CS should go high
before the 48th 4>2 clock has elasped and return low after
the 64th 4>2 to synchronize serial communication.
1.1 CONTINUOUS SCLK
With a continuous SCLK input CS must be used to synchronize the serial data exchange (see Figure 1). The AOC0811
recognizes a valid CS one to three 4>2 clock periods after
the actual falling edge of CS. This is implemented to ensure
noise immunity of the CS Signal. Any spikes on CS less than
one 4>2 clock period will be ignored. CS must remain low
during the complete I/O exchange which takes eight SCLK
cycles. Although CS is not immediately acknowledged for
the purpose of starting a new conversion, the falling edge of
CS immediately enables DO to output the MSB (07) of the
previous conversion.
A conversion or I/O operation can be aborted at any time by
strobing CS. If CS is high or low less than one 4>2 clock it will
be ignored by the AID. If the CS is strobed high or low
between 1 to 3 4>2 clocks the AID mayor may not respond.
Therefore CS must be strobed high or low greater than 3 4>2
clocks to ensure recognition. If a conversion or I/O exchange is aborted while in process the consequent data
output will be erroneous until a complete conversion sequence has been implemented.
The first SCLK rising edge will be acknowledged after a setup time (tset.up) has elapsed from the falling edge of CS.
This and the following seven SCLK rising edges will shift in
the channel address forthe analog multiplexer. Since there are
12 channels only four address bits are utilized. The first four
SCLK cycles clock in the mux address, during the next four
SCLK cycles the analog input is selected and sampled. During
SERIAL DATA
INPUT
4 MSB OUTPUT
1.2 DISCONTINUOUS SCLK
Another way to accomplish synchronous serial communication is to tie CS low continuously and disable SCLK after its
8th falling edge (see Figure 2). SCLK must remain low for
ANALOG VOLTAGE
ACQUISITION WINDOW
4 LSB OATA OUTPUT
CONVERSION PROCESS
SClK
TL/H/5587-18
FIGURE 1
CONVERSION PROCESS
SERIAL DATA
INPUT
4 MSB OUTPUT
ANALOG VOLTAGE
ACQUISITION WINOOW
4 LSB DATA OUTPUT
CS (LOW)
----~------~---------+------~~-+---Sm
----!
DO
TLIH/5587 -19
FIGURE 2
3-67
•
..CIO
r-----------------------------------------------------------------------------------------,
o
Functional Description (Continued)
Q
at least 64 640 kHz, the minimum start pulse width is 8 clock periods plus 2 p.s. For synchronous operation
at fe ,; 640 kHz take start high within 100 ns of clock going low.
Note 8: The outputs of the data register are updated one clock cycle before the rising edge of EOe.
Note 9: Human body model, 100 pF discharged through a 1.5 kG resistor.
3-72
»
c
oI:)
Functional Description
Multiplexer: The device contains a 1S-channel single-ended analog signal multiplexer. A particular input channel is
selected by using the address decoder. Table 1 shows the
input states for the address line and the expansion control
line to select any channel. The address is latched into the
decoder on the low-to-high transition of the address latch
enable signal.
TABLE 1
Selected
Analog Channel
INa
IN1
IN2
IN3
IN4
IN5
INS
IN7
IN8
IN9
IN10
IN11
IN12
IN13
IN14
IN15
All Channels OFF
Address Line
D
C
B
A
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
X
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
X
X
X
Additional single-ended analog signals can be multiplexed
to the AID converter by disabling all the multiplexer inputs
using the expansion control. The additional external Signals
are connected to the comparator input and the device
ground. Additional signal conditioning (Le., prescaling, sample and hold, instrumentation amplification, etc.) may also
be added between the analog input Signal and the comparator input.
Expansion
Control
CONVERTER CHARACTERISTICS
The Converter
The heart of this single chip data acquisition system is its 8bit analog-to-digital converter. The converter is designed to
give fast, accurate, and repeatable conversions over a wide
range of temperatures. The converter is partitioned into 3
major sections: the 25SR ladder network, the successive
approximation register, and the comparator. The converter's
digital outputs are positive true.
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
The 25SR ladder network approach (Figure 1) was chosen
over the conventional R/2R ladder because of its inherent
monotonicity, which guarantees no missing digital codes.
Monotonicity is particularly important in closed loop feedback control systems. A non-monotonic relationship can
cause oscillations that will be catastrophic for the system.
Additionally, the 25SR network does not cause load variations on the reference voltage.
The bottom resistor and the top resistor of the ladder network in Figure 1 are not the same value as the remainder of
the network. The difference in these resistors causes the
output characteristic to be symmetrical with the zero and
full-scale points of the transfer curve. The first output transition occurs when the analog signal has reached + % LSB
and succeeding output transitions occur every 1 LSB later
up to full-scale.
X=don't care
CONTROLS FROM S.A.R.
I
REF('i
C--
.
:
256R
R
R
REFI-)
·
·
·
·
·
·
·
·
·
·
..• 'J•
TO
.... COMPARATOR
INPUT
C-TL/H/5277-2
FIGURE 1. Resistor Ladder and Switch Tree
3-73
co
.....
en
......
»
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o
I:)
co
.....
~
.....,...
co
o
(.)
C
C
Applications Information
oo
CD
.....
OPERATION
Ratiometric transducers such as potentiometers, strain
gauges, thermistor bridges, pressure transducers, etc., are
suitable for measuring proportional relationships; however,
many types of measurements must be referred to an abso·
lute standard such as voltage or current. This means a system reference must be used which relates the full-scale
voltage to the standard volt. For example, if Vee = VREF =
5.12V, then the full-scale range is divided into 256 standard
steps. The smallest standard step is 1 LSB which is then 20
mV.
1.0 RATIOMETRIC CONVERSION
The ADC0816, ADC0817 is designed as a complete Data
Acquisition System (DAS) for ratio metric conversion sys·
tems. In ratiometric systems, the physical variable being
measured is expressed as a percentage of full·scale which
is not necessarily related to an absolute standard. The volt·
age input to the ADC0816 is expressed by the equation
VIN
Dx
Vls-VZ
DMAX-DMIN
(1)
VIN = Input voltage into the ADC0816
2.0 RESISTOR LADDER LIMITATIONS
Vis = Full·scale voltage
The voltages from the resistor ladder are compared to the
selected input 8 times in a conversion. These voltages are
coupled to the comparator via an analog switch tree which
is referenced to the supply. The voltages at the top, center
and bottom of the ladder must be controlled to maintain
proper operation.
Vz = Zero voltage
Dx = Data point being measured
DMAX = Maximum data limit
DMIN = Minimum data limit
en
......
l>
C
oo
CD
.....
......
The top of the ladder, Ref( +), should not be more positive
than the supply, and the bottom of the ladder, Ref( -),
should not be more negative than ground. The center of the
ladder voltage must also be near the center of the supply
because the analog switch tree changes from N-channel
switches to P·channel switches These limitations are automaticaly satisfied in ra,tiometric systems and can be easily
met in ground referenced systems.
A good example of a ratiometric transducer is a potentiome·
ter used as a position sensor. The position of the wiper is
directly proportional to the output voltage which is a ratio of
the full·scale voltage across it. Since the data is represent·
ed as a proportion of full'scale, reference requirements are
greatly reduced, eliminating a large source of error and cost
for many applications. A major advantage of the ADC0816,
ADC0817 is that the input voltage range is equal to the sup·
ply range so the transducers can be connected directly
across the supply and their outputs connected directly into
the multiplexer inputs, (Figure 9).
Figure 10 shows a ground referenced system with a separate supply and reference. In this system, the supply must
be trimmed to match the reference voltage. For instance, if
a 5.12V reference is used, the supply should be adjusted to
the same voltage within 0.1V.
Vee
REF(+)
MSB
.•
Inl5
DIGITAL
OUTPUT
PROPORTIONAL
TO ANALOG
INPUT
nOUT
InO
REFH
QOUT=
LSB
~=~
VREF
vcc
4.75V "vee = vAEF"S.2SV
GNO
• Ratiometric transducers
'::"
AoeoBI6,17
FIGURE g, Ratiometric Conversion System
3-77
TL/H/5277 -11
II
....r-. ,---------------------------------------------------------------------------------,
Applications Information (Continued)
~
The top and bottom ladder voltages cannot exceed Vee
g The ADC0816 needs less than a milliamp of supply current
and ground, respectively, but they can be symmetrically less
so developing the supply from the reference is readily ac~
complished. In Figure 11 a ground references system is
Vee and greater than ground. The center of the ladder
CD
.... shown which generates the supply from the reference. The than
voltage should always be near the center of the supply. The
8
c
-....--IVcc
DIGITAL OUTPUT
REFERENCED TO
GROUND
••
•
InO
REFH
L-----------------~--iGND
aOUT-_..!!!'!.
VREF
4.7SV"VCC=VREF"S.25V
ADCOBI6,17
TL/H/5277-13
FIGURE 11. Ground Referenced Conversion System with
Reference Generating Vee Supply
3-78
.----------------------------------------------------------------------.~
Applications Information
c
o
(Continued)
...
C)
00
10-IS VOC
01
i;:
C
o
Ik
Rl
...
C)
1000 pF
00
.......
LMlZ9B
VCC
RZ
lOT
>-1-"'-~REF(+)
Rl
REFH
TLlH/5277-14
FIGURE 12. Typical Reference and Supply Circuit
SV
....."",..,....--4 VCC
"'_-.1___. :
r-_ _"'_ _"'___
l::.:.7.::,:SV:.j REF(+)
MSB
~I---f--+-----II.,S
DOUT
DIGITAL OUTPUT
P~OPORTIONAL TO
ANALOG INPUT
I.ZSV " Y,N $ l.7SV
1----11.0
"'_-.1___. :
L-_ _" '_ _" '_ _ _
1,;:.Z:,:SV:.jREFH
Z.SV
REFERENCE
LSB
RA=RB
* Ratlometric transducers
TL/H/5277 -15
FIGURE 13. Symmetrically Centered Reference
3.0 CONVERTER EQUATIONS
The transition between adjacent codes Nand N + 1 is
given by:
V'N=
{(VREF(+)-VREF(-))[2~6 + 5:2] ±VTUE} +VREF(-)
The output code N for an arbitrary input are the integers
within the range:
N=
VIN-VREF(-) x256±Absolute Accuracy
VREF(+)-VREF(-)
where: VIN = Voltage at comparator input
VREF = Voltage at Ref( + )
VREF = Voltage at Ref(-)
VTUE = Total unadjusted error voltage (typically
(2)
The center of an output code N is given by:
V'N= {
(VREF(+)-VREF(-)[2~6] ±VTUE] +VREF(-)
(3)
VREF(+) +512)
3·79
(4)
~
.....
co
.------------------------------------------------------------------------------------------,
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Applications Information (Continued)
c
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4.0 ANALOG COMPARATOR INPUTS
o
.....
CD
.....
CO
o
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cc(
If no filter capacitors are used at the analog or comparator
inputs and the signal source impedances are low. the comparator input current should not introduce converter errors.
as the transient created by the capacitance discharge will
die out before the comparator output is strobed.
The dynamic comparator input current is caused by the peri·
odic switching of on-chip stray capacitances These are connected alternately to the output of the resistor ladder/switch
tree network and to the comparator input as part of the
operation of the chopper stabilized comparator.
If input filter capacitors are desired for noise reduction and
signal conditioning they will tend to average out the dynamic
comparator input current. It will then take on the characteristics of a DC bias current whose effect can be predicted
conventionally. See AN-258 for further discussion.
The average value of the comparator input current varies
directly with clock frequency and with VIN as shown in Fig-
ure6.
Typical Application
READ----~~)o
________________________
ADDRESS
DECODE
(AD4-ADI5)'
~
.....- -. .------.INTERRUPT
Msa
WRITE
---'L-_
Lsa
VIN1B]
0-5V
ANALOG
INPUT RANGE
VINI
TUH/5277-16
'Address latches needed lor 8085 and SC/MP interfacing the ADC0816. 17 to a microprocessor
Microprocessor Interface Table
PROCESSOR
8080
8085
Z-80
SC/MP
6800
READ
WRITE
INTERRUPT (COMMENn
MEMR
RD
RD
NRDS
VMAe2 eR/W
MEMW
WR
WR
NWDS
VMAe02eR/W
INTR (Thru RST Circuit)
INTR (Thru RST Circuit)
INT (Thru RST Circuit. Mode 0)
SA (Thru Sense A)
IROA or IROB (Thru PIA)
Ordering Information
TEMPERATURE RANGE
Error
-40'Cto +85'C
± % Bit Unadjusted
ADC0816CCN
± 1 Bit Unadjusted
ADC0817CCN
Package Outline
N40A Molded DIP
3-80
- 55'C to + 125'C
ADC0816CCJ
ADC0816CJ
J40A Hermetic DIP
J40A Hermetic DIP
~----------------------------------------------------------,~
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CD
.....
J?JI National
~ Semiconductor
CD
ADC0819 8-Bit Serial 1/0 AID Converter
with 19-Channel Multiplexer
General Description
The ADC0819 is an 8-Bit successive approximation AID
converter with simultaneous serial 110. The serial input controls an analog multiplexer which selects from 19 input
channels or an internal half scale test voltage.
An input sample-and-hold is implemented by a capacitive
reference ladder and sampled data comparator. This allows
the input Signal to vary during the conversion cycle.
Separate serial I/O and conversion clock inputs are provided to facilitate the interface to various microprocessors.
Features
• Separate asynchronous converter clock and serial data
I/O clock.
• 19-Channel multiplexer with 5-Bit serial address logic.
• Built-in sample and hold function.
Connection Diagrams
•
•
•
•
•
•
Ratiometric or absolute voltage referencing.
No zero or full-scale adjust required.
Internally addressable test voltage.
OV to 5V input range with single 5V power supply.
TTL/MOS input/output compatible.
28-pin molded chip carrier or 28-pin molded DIP
Key Specifications
•
•
•
•
•
8-Bits
Resolution
Total unadjusted error
Single supply
Low Power
Conversion Time
± '!aLSB and ± 1 LSB
5VDC
15 mW
16
).I.s
Functional Diagram
Molded Chip Carrier (PCC) Package
25
2(
13 22 21 20 19
Sa.. 2.
18
0i16
27
26
17
CHIS
I.
au
I
2
15
I.
CHI.
CHI3
CH2
3
13
.,""
Vee
CHO
CH3
•
•
5
12
7 8
01'
ADDRESS
LATCHANO
IlECllDER
GNO
CONTROL
AND
CH12
CHl1
nlllNG
23 9
.+-_+-..------'2;;.8 Sa.,
9 10 11
CHO I
2
au
CH2 3
TL/H/9287 -1
Top View
Order Number ADC0819BCV, CCV
See NS Package Number V28A
Dual-In-Llne Package
CHO
CHI
CH2
CH3
CH'
3
•
CH5
4
5
8
7
CHID ~~
CHll 13
CH12 1&
CH13 '8
Vee
Xl
.2CLK
26
25
01
CH15 '8
24
DO
CHla 19
SCU<
cs
7
23
22
CH7
CHe
CH9
8
9
10
21
20
19
II
18
17
1&
CHIS
CHI5
eHU
12
13
GNO
I.
15
CHI3
v..,<+)
v..,<-)
•
CH7 :
: : 10
26
CHS
CHIO
CHl1
CH3
CH4
CH5
CH8
ANALOD
INPUT
NUX
...-_ _ _ _.....;;22
v..,+
CH14 17
CHI7 20
CHI8
CHI8
CHI7
1'4
SNO
TL/H/92B7 -2
CH1~
TL/H/92B7 -20
Top View
Order Number ADC0819BCN, CCN
See NS Package Number N28B
3-81
....
Q)
~
Absolute Maximum Ratings (Notes 1 & 2)
c(
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
oQ
Supply Voltage (Vcc)
Voltage
Inputs and Outputs
Input Current Per Pin (Note 3)
6.5V
215°C
220°C
2000V
Operating Ratings (Notes 1 & 2)
±20mA
Supply Voltage (Vee)
-65°C to + 150°C
Package Dissipation at TA = 25°C
260°C
ESD Susceptibility (Note 11)
-0.3V to Vee +0.3V
±5mA
Total Package Input Current (Note 3)
Storage Temperature
Lead Temperature (Soldering, 10 sec.)
Dual-In-Line Package (Plastic)
Surface Mount Package
Vapor Phase (60 sec.)
Infrared (15 sec.)
4.5 Voe to 6.0 Voe
Temperature Range
875mW
TMIN S; TA S; TMAX
-40°C S; TA S; +85°C
ADC0819BCV, ADC0819CCV
ADC0819BCN, ADC0819CCN
O°C
S;
TA
S;
+70°C
Electrical Characteristics
The following specifications apply for Vee = 5V, VREF = 5V, 2 elK = 2.097 MHz unless otherwise specified. Boldface limits
apply from TMIN to TMAX; all other limits TA = TJ = 25°C.
ADC0819BCV, ADC0819BCN
ADC0819CCV, ADC0819CCN
Parameter
Conditions
Typical
(Note 6)
Tested
Limit
(Note 7)
Design
Limit
(Note 8)
Units
±%
±1
±%
±1
LSB
LSB
5
k!1
CONVERTER AND MULTIPLEXER CHARACTERISTICS
Maximum Total
Unadjusted Error
ADC0819BCV, BCN
ADC0819CCV, CCN
VREF= 5.00 Voe
(Note 4)
Minimum Reference
Input Resistance
8
Maximum Reference
Input Resistance
Maximum Analog Input Range
8
(Note 5)
Minimum Analog input Range
On Channel Leakage Current
ADC0819BCV,CCV,BCN,CCN
ADC0819BCV,CCV, BCN,CCN
Off Channel Leakage Current
ADC0819BCV,CGV,BCN,CCN
On Channel=5V
Off Channel = OV
On Channel = OV
Off Channel = 5V
(Note 9)
11
11
k!1
Vee + 0.05
Vee + 0.05
V
GND-0.05
GND-0.05
V
400
1000
nA
-400
-1000
nA
-400
-1000
nA
400
1000
nA
ADC0819BCV,CCV, BCN,CCN
On Channel=5V
Off Channel = OV
On Channel=OV
Off Channel = 5V
(Note 9)
Minimum VTEST
Internal Test Voltage
VREF=Vee,
CH 19 Selected
125
125
(Note 10)
Counts
Maximum VTEST
Internal Test Voltage
VREF=Vee,
CH 19 Selected
130
130
(Note 10)
Counts
2.0
2.0
V
0.8
0.8
V
2.5
2.5
",A
-2.5
-2.5
",A
DIGITAL AND DC CHARACTERISTICS
VIN(1), Logical "1" Input
Voltage (Min)
Vee=5.25V
VIN(O), Logical "0" Input
Voltage (Max)
Vee=4.75V
IIN(1), Logical "1" Input
Current (Max)
VIN=5.0V
IIN(O), Logical "0" Input
Current (Max)
VIN=OV
0.005
-0.005
3-82
Electrical Characteristics (Continued)
The following specifications apply for VCC = 5V. VREF = 5V. 2 CLK = 2.097 MHz unless otherwise specified. Boldface limits
apply from T MIN to T MAX; all other limits T A = T J = 25°C.
ADC0819BCV, ADC0819BCN
ADC0819CCV, ADC0819CCN
Parameter
Conditions
Typical
(Note 6)
Tested
Limit
(Note 7)
Design
Limit
(Note 8)
Units
2.4
4.5
2.4
4.5
V
V
0.4
0.4
V
-3
3
-3
3
/LA
/LA
-6.5
-6.5
mA
mA
DIGITAL AND DC CHARACTERISTICS (Continued)
VOUT(1). Logical "1"
Output Voltage (Min)
Vcc=4.75V
IOUT= -360 /LA
IOUT= -10 /LA
VOUT(ot Logical "a"
Output oltage (Max)
Vcc=5.25V
IOUT=1.6mA
lOUT. TRI-STATEOutput
Current (Max)
VOUT=OV
VOUT=5V
-0.01
0.01
ISOURCE. Output Source
Current (Min)
VOUT=OV
-14
ISINK. Output Sink Current (Min)
VOUT=VCC
16
8.0
B.O
Icc. Supply Current (Max)
CS= 1. VREF Open
1
2.5
2.5
mA
IREF(Max)
VREF=5V
0.7
1
1
mA
AC CHARACTERISTICS
Parameter
2 CLK. 2 Clock Frequency
Conditions
-MIN
4.0
2.0
2.1
MAX
1000
525
525
MIN
26
26
32
32
5.0
-MIN
T C. Conversion Process Time
Not Including MUX
Addressing and
Analog Input
MAX
Sampling Times
tACC. Access Time Delay From CS
Falling Edge to DO Data Valid
-
MIN
1
MAX
3
tSET-UP. Minimum Set-up Time of CS Falling
Edge to SCLK Rising Edge
IHCS. CS Hold Time After Ihe Falling
Edge of SCLK
I CS. Total CS Low Time
~
MAX
tHOI. Minimum 01 Hold Time from
SCLK Rising Edge
tHOO. Minimum DO Hold Time from SCLK
Falling Edge
Design
Limit
(Note 8)
1.0
0.70
MAX
SCLK. Serial Dala Clock
Frequency
Tested
Typical
Limit
(Note 6) (Note 7)
a
RL =30k.
CL =100pF
IsOI. Minimum 01 Set-up Time to SCLK
Rising Edge
200
Units
MHz
KHz
2 cycles
2 cycles
1
412CLK+~
CLK
sec
0
ns
tset-up + B/SCLK
sec
t cs(min) + 2612CLK
sec
0
ns
10
ns
400
ns
1000. Maximum Delay From SCLK
Falling Edge to DO Data Valid
RL =30k.
CL =100 pF
180
200
250
ns
ITRI. Maximum DO Hold Time.
(CS Rising edge to DO TRI-STATE)
RL =3k.
CL =100pF
90
150
150
ns
»
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01)
-'"
CD
Electrical Characteristics The following specifications apply for Vee =
5V, tr=tf= 20 ns, VREF = 5V, unless
otherwise specified. Boldface limits apply from T MIN to TMAX; all other limits T A = T J = 25°C.
Parameter
Typical
Conditions
(Note
6)
Tested
Design
Limit
Limit
(Note 7)
(Note 8)
Units
AC CHARACTERISTICS (Continued)
teA,Analog
After Address Is Latched
Sampling Time
CS=Low
tRCO, Maximum DO
RL=30kO,
"TRI-STATE" to "HIGH" State
Rise Time
CL =100 pf
"LOW" to "HIGH" State
tFDD, Maximum DO
RL =30 k~,
"TRI-STATE" to "LOW" State
75
150
150
Fall TIme
CL=100pf
"HIGH" to "LOW" State
150
300
300
CIN, Maximum Input
Analog Inputs, ANO-AN10 and VREF
Capacitance
All Others
3/SCLK+1/A-s
75
150
150
150
300
300
11
55
5
15
sec
ns
ns
pF
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Nole 2: All voltages are measurad with respect to ground.
Nole 3: Under over voltage conditions (VIN Vccl the maximum input current at eny one pin is ± 5 mAo "the voltage at more than one pin exceeds
Vee + .3V the total package current must be limited to 20 rnA. For example the maximum number of pins that can be over driven at the maximum current level of
±5 rnA is four.
Nole 4: Total unadiusted error includes offset, full-scale, linearity, multiplexer, and hold step errors.
Nole 5: Two on-chip diodes are tied 10 each analog input, which will forward·conduct for analog input voltages one diode drop below ground or one diode drop
greater than Vee supply. Be careful during testing at low Vee levals (4.5V). as high level analog Inputs (5V) can cause this Input diode to conduct, especlally at
elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows 50 mV forward bias of either diode. This means that as long as Ihe
analog VIN does not exceed the supply voltage by more Ihan 50 mV, the output code will be correct. To achieve an absolute 0 Vee to 5 VOC input voltage range will
Iherefore require a minimum supply voltage of 4.950 Voc over temperature variations, initial tolerance end loading.
Nole 6: Typical. are at 25'C and represent most likely parametric norm.
Nole 7: Tested LimHs are guaranteed to National'. AOQL (Average OutgOing Quality Level).
Note 8: Design Umits are guaranteed, but not 100% production tested. These limits are not used to calculate outgOing quality levels.
Note 9: Channel leakage current is measured after the channel selection.
Nole 10: 1 count
= VREF/256.
Note 11: Humen body model; 100 pF discharged lhrough a 1.5 kG resistor.
Test Circuits
DO Except "TRI-STATE"
Leakage Current
5.0V
5V
.J.
.0-
R~.
~:
I
I
I
I
CHANNEL
SELECT
A
I
I
I
•
•
TEST POINT
Uk
MMO 6150
OR EQUI~~NT
CHO (ON)
1,·. . ~ rr
ADC0819 00
CHI (OFF)
T
Rl
Cl
CH2 (OFF)
.
;
~
~RM~~~~LENT
~
•
a.....:....- CHI8 (OFF)
TUH/9287-4
TL/H/9287 -3
Timing Diagrams
ITRI "TRI-STATE"
TEST
POINT
1-'·1 10
P
DO "TRI-STATE" Rise
5.DV
-/
DO 1.2V-TRI-lITATE
~
TUH/9287-5
3-84
& Fall Times
[-tROO
2.4V
1oo!l.4V
[-tRlO
TL/H/9287 -6
»
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oo
Timing Diagrams (Continued)
DD
DO Low to High State
DO High to Low State
_~IRDD
=tIFDD
2.4-Y---_ _....... D.4Y
DD
3.5Y
CD
......
(Q
D.4Y
TLlH/9267-7
TL/H/9267 -6
Data Input and Output Timing
SCLI(
DI
DD
----In-TL/H/9267-9
Timing with a continuous SCLK
TL/H/9267 -10
·Strobing CS High and Low will abort the present conversion and initiate a new serial 1/0 exchange.
Timing with a gated SCLK and CS Continuously Low
ATAI/D EXCHANGE CYCLE-
SCLI(
~
D
16
7
1"---'--+-
CS(LDW)
--------~---+--.--~00
D1
D1
TL/H/9267 -11
Using CS To TRI-STATE DO
CONYERSION PRDCESSSeLl(
EK:!::t-:--__
TRI-8TATE-(!
TLlH/9267-12
Note: Strobing CS Low during this time interval will abort the conversion in process.
3-85
•
....CO r------------------------------------------------------------------------------------------,
CD
8
c
Timing Diagrams (Continued)
CS High During Conversion
2) controls the SAR during the conversion
process and must be continuously enabled.
this mux addresslsample cycle, data from the last conversion is also clocked out on DO. Since 07 was clocked out
on the falling edge of es only data bits 06-00 remain to be
received. The following seven falling edges of SCLK shift out
this data on DO.
The 8th SCLK falling edge initiates the beginning of the AID's
actual conversion process which takes between 26 and 32
<1>2 cycles (Td. During this time es can go high to TRISTATE DO and disable the SCLK input or it can remain low.
If es is held Iowa new 110 exchange will not start until the
conversion sequence has been completed, however once
the conversion ends serial I/O will immediately begin. Since
there is an ambiguity in the conversion time (Td synchronizing the data exchange is impossible. Therefore es should
go high before the 26th <1>2 clock has elasped and return low
after the 32nd <1>2 to synchronize serial communication.
1.1 CONTINUOUS SCLK
With a continuous SCLK input es must be used to synchronize the serial data exchange (see Figure 1). The ADe0819
recognizes a valid es one to three <1>2 clock periods after
the actual falling edge of es. This is implemented to ensure
nOise immunity of the es signal. Any spikes on es less than
one <1>2 clock period will be ignored. es must remain low
during the complete 110 exchange which takes eight SCLK
cycles. Although es is not immediately acknowledged for
the purpose of starting a new conversion, the falling edge of
es immediately enables DO to output the MSB (07) of the
previous conversion.
A conversion or 110 operation can be aborted at any time by
strobing es. If es is high or low less than one <1>2 clock it will
be ignored by the AID. If the es is strobed high or low
between 1 to 3 <1>2 clocks the AID mayor may not respond.
Therefore es must be strobed high or low greater than 3 <1>2
clocks to ensure recognition. If a conversion or 110 exchange is aborted while in process the consequent data
output will be erroneous until a complete conversion sequence has been implemented.
The first SCLK rising edge will be acknowledged after a setup time (tset-up) has elapsed from the falling edge of es.
This and the following seven SCLK rising edges will shift in
the channel addressfortheanalog multiplexer. Since there are
19 channels only five address bits are utilized. The first five
SCLK cycles clock in the mux address, during the next three
SCLK cycles the analog input is selected and sampled. During
1.2 DISCONTINUOUS SCLK
Another way to accomplish synchronous serial communication is to tie es low continuously and disable SCLK after its
8th falling edge (see Figure 2). SCLK must remain low for
ANALOG VOLTAGE
ACOUISITION WINDOW
3 LSD DATA OUTPUT
SERIAL DATA
INPUT
5 MSD OUTPUT
I CONVERSIDN PROCESS
TL/H/92B7 -16
FIGURE 1
SERIAL OATA
INPIIT
cs ILOW)
TcIMAX ) _
~4~0~:2
5 MSB OUTPUT
------~--------+-----~----------~----SCLK
00
----!
07
03
02
01
00
~''-
________
-J~
__
07 _
TLlH/9287 -17
FIGURE 2
3-88
r--------------------------------------------------------------------,~
Functional Description
C
(Continued)
at least 32 <1>2 clocks to ensure that the AID has completed
its conversion. If SCLK is enabled sooner, synchronizing to
the data output on DO is not possible since an end of conversion signal from the AID is not available and the actual
conversion time is not known. With CS low during the conversion time (32 <1>2 max) DO will go high or low after the
eighth falling edge of SCLK until the conversion is completed. Once the conversion is through DO will transmit the
MSB. The rest of the data will be shifted out once SCLK is
enabled as discussed previously.
If CS goes high during the conversion sequence DO is tristated, and the result is not affected so long as CS remains
high until the end of the conversion.
eighth SCLK falling edge. The hold mode is initiated with the
start of the conversion process. An acquisition window of
3tSCLK + 1 ,,"sec is therefore available to allow the ladder
capaCitance to settle to the analog input voltage. Any
change in the analog voltage before or after the acquisition
window will not effect the AID conversion result.
oo
CO
....
CD
In the most simple case, the ladder's acquisition time is determined by the Ron (3K) of the multiplexer switches and the
total ladder capaCitance (90pf). These values yield an acquisition time of about 2 ,,"sec for a full scale reading. Therefore the analog input must be stable for at least 2 ,,"sec
before and 1 ,.sec after the eighth SCLK falling edge to
ensure a proper conversion. External input source resistance and capaCitance will lengthen the acquisition time and
should be accounted for.
Other conventional sample and hold error specifications are
included in the error and timing specs of the AID. The hold
step and gain error sample/hold specs are taken into account in the ADC0819's total unadjusted error, while the
hold settling time is included in the AID's max conversion
time of 32 <1>2 clock periods. The hold droop rate can be
thought of as being zero since an unlimited amount of time
can pass between a conversion and the reading of data.
However, once the data is read it is lost and another conversion is started.
1.2 MULTIPLEXER ADDRESSING
The five bit mux address is shifted, MSB first, into DI. Input
data corresponds to the channel selected as shown in table
1. Care should be taken not to send an address greater than
or equal to twenty four (11 XXX) as this puts the AID in a
digital testing mode. In this mode the analog inputs CHO
thru CH4 become digital outputs, for our use in production
testing.
2.0 ANALOG INPUT
2.1 THE INPUT SAMPLE AND HOLD
The ADC0819's sample/hold capacitor is implemented in its
capacitive ladder structure. After the channel address is received, the ladder is switched to sample the proper analog
input. This sampling mode is maintained for 1 ,,"sec after the
Typical Applications
ADC0819-INS8048 INTERFACE
INS8048
~~ t----I~;LKADC081::~
P12
-
00
<1>2
;:} NINmEN ANALOG
:
INPUTS
•
CHI8-
TUH/9287 -18
3-89
•
....co
G)
ADC0819 FUNCTIONAL CIRCUIT
0
5V
0
C
0:(
MSB
5Y
CHO
CHI
14 Vee
01
1
CH2
CH3
~
CH4
CH5
2CLK
CH6
CH7
CH8
ScLl(
26
CH9
~
CHID
5V
CHll
23
CH12
':'
CH13
SHiRl LOAD
CH14
74C165
DO
CH15
DH
CH16
DA
6
14
13
12
11
CH17
CHIS
5V
14
INA 74LS93 DD 11
':'
MSB
':'
LSB
CHANNEL SELECT
':'
2CLK
TL/H/9287 -19
Ordering Information
Temperature Range
Total Unadjusted
Error
O'Cto +70'C
- 40'C to + 85'C
I
±1jzLSB
ADC0819BCN
ADC0819BCV
I
±1 LSB
ADC0819CCN
ADC0819CCV
N28B
V28A
Package Outline
3-90
l>
C
""---,
oo
\'--_.-J)
N
~National
~ Semiconductor
ADC0820 8-Bit High Speed p.P Compatible
A/D Converter with Track/Hold Function
General Description
Features
By using a half-flash conversion technique, the 8-bit
ADC0820 CMOS AID offers a 1.5 JLs conversion time and
dissipates only 75 mW of power. The half-flash technique
consists of 32 comparators, a most significant 4-bit ADC
and a least significant 4-bit ADC.
..
II
..
..
..
The input to the ADC0820 is tracked and held by the input
sampling circuitry eliminating the need for an external sample-and-hold for signals moving at less than 100 mV I JLs.
For ease of interface to microprocessors, the ADC0820 has
been designed to appear as a memory location or 1/0 port
without the need for external interfacing logic.
..
III
Key Specifications
B Bits
2.5 JLs Max (RD Mode)
1.5 JLs Max (WR-RD Mode)
1:1 Input signals with slew rate of 100 mV I JLs converted
without external sample-and-hold to B bits
III Low Power
75 mW Max
II Total Unadjusted Error
± Yo LSB and ± 1 LSB
II Resolution
III
..
II
Conversion Time
CI
III
•
III
[J
microCMOS
Q)
o
Built-in track-and-hold function
No missing codes
No external clocking
Single supply-5 VDC
Easy interface to all microprocessors, or operates
stand-alone
Latched TRI-STATE® output
Logic inputs and outputs meet both MOS and T2L voltage level specifications
Operates ratiometrically or with any reference value
equal to or less than Vee
OV to 5V analog input voltage range with single 5V
supply
No zero or full-scale adjust required
Overflow output available for cascading
0.3" standard width 20-pin DIP
20-pin molded chip carrier package
20-pin small outline package
Connection and Functional Diagrams
Dual-In-Line and Small
Outline Packages
V,N
20
Vrx
DBO
19
18
NC
Of[
DB2
17
DB7
DB3
16
DB6
DB1
3
ViR/RDY
6
15
OB5
MODE
7
14
DB4
iiii
8
13
cs
iNi'
9
12
VA,,(-)
GND
10
11
vA"H
VREFt+1
Of[
OFL
4·SlT
DB1
DB6
DBS
FLASH
ADC
(4 MSBI)
0..
VREF(-)
OUTPUT
HIT
OAC
TLiH/5501-1
LATCH
AND
TRI·STATE
BUFFERS
Top View
VWt+}
Molded Chip Carrier
Package
083
4·81T
OB2
FLASH
ADC
(4 LSBs,
OBI
OBO
VREF(-)
cs
NC
Vrx
20
VIN
DBO
DB1
3
12
11
VA,,(-)
VR,,(-)
10
GND
1Nf
Rii"
TUH/5501-2
FIGURE 1
iNi'
TL/H/5501-33
3-91
See Ordering Information
•
o
C\I
CO
o
Absolute Maximum Ratings (Notes 1 &2)
cc(
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
o
Supply Voltage (Vee>
Logic Control Inputs
Voltage at Other Inputs and Output
Lead Temp. (Soldering, 10 sec.)
Dual-In-Line Package (plastic)
Dual-In-Line Package (ceramic)
Surface Mount Package
Vapor Phase (60 sec.)
Infrared (15 sec.)
10V
-0.2V to Vee +0.2V
-0.2V to Vee +0.2V
Storage Temperature Range
Operating Ratings
- 65·C to + 150·C
Package Dissipation at TA = 25·C
B75mW
Input Current at Any Pin (Note 5)
215·C
220·C
(Notes 1 & 2)
Temperature Range
TMINS:TAS:TMAX
-55·CS:TAS: + 125·C
1 mA
ADCOB20BD, ADCOB20CJ
4mA
ADCOB20BCD, ADCOB20CCJ
-40·CS:TAS: +B5·C
1200V
ADCOB20BCN, ADCOB20CCN
ADCOB20BCV, ADCOB20CCV
0·CS:TAS:700C
0·CS:TAS:70·C
ADCOB20BCWM, ADCOB20CCWM
0·CS:TAS:70·C
Package Input Current (Note 5)
ESD Susceptability (Note 9)
260·C
300·C
4.5VtoBV
Vee Range
Converter Characteristics The following specifications apply for RD mode (pin 7= 0), Vcc= 5V,
VREF( +) = 5V, and VREF( -) = GND unless otherwise specified. Boldface limits apply from TMIN to TMAX; all other limits
TA=Tj=25·C.
ADC0820BD, ADC0820CJ
ADC0820BCD, ADC0820CCJ
Parameter
Conditions
Typ
(Note 6)
Resolution
Total Unadjusted Error
(Note 3)
Tested
Limit
(Note 7)
Design
Limit
(Note 8)
ADC0820BCN, ADC0820CCN
ADC0820BCV, ADC0820CCV
ADC0820BCWM, ADC0820CCWM
Typ
(Note 6)
8
ADCOB20BD, BCD
ADCOB20BCN
ADCOB20CD, CCD
ADC0820CCN
Tested
Limit
(Note 7)
Design
Limit
(Note 8)
8
8
±%
±Yz
±1
±1
±Yz
±1
Limit
Units
. Bits
LSB
LSB
LSB
LSB
Minimum Reference
Resistance
2.3
1.00
2.3
1.2
kfl
Maximum Reference·
Resistance
2.3
6
2.3
5.3
6
kfl
Maximum VREF( +)
Input Voltage
Vee
Vee
Vee
V
Minimum VREF( -)
Input Voltage
GND
GND
GND
V
Minimum VREF( +)
Input Voltage
VREF(-)
VREF(-)
VREA-)
V
Maximum VREF( -)
Input Voltage
VREA+)
VREF(+)
VREF(+)
V
Maximum VIN Input
Voltage
Vcc+ 0•1
VCC+ 0.1
Vee + 0.1
V
Minimum VIN Input
GND-0.1
GND-0.1
GND-O.1
V
3
-3
0.3
-0.3
3
-3
/LA
/LA
±%
±%
LSB
Voltage
Maximum Analog
Input Leakage Current
CS = Vee
VIN=Vee
VIN=GND
Power Supply
Sensitivity
Vcc=5V±50/0
±V,s
±%
3-92
±V,6
J>
C
oo
DC Electrical Characteristics
The following specifications apply for Vcc= SV, unless otherwise specified.
Boldface limits apply from T MIN to T MAX; all other limits T A = T J = 2SoC.
ADC0820BD, ADC0820CJ
ADC0820BCD, ADC0820CCJ
Parameter
Conditions
Tested
Limit
(Note 7)
Typ
(Note 6)
Design
Limit
(Note 8)
ADC0820BCN, ADC0820CCN
ADC0820BCV, ADC0820CCV
ADC0820BCWM, ADC0820CCWM
Typ
(Note 6)
Tested
Limit
(Note 7)
Design
Limit
(Note 8)
CD
N
o
Limit
Units
V
CS,WR,RD
2.0
2.0
2.0
Mode
3.5
3.S
3.5
V
CS, WR, RD
0.8
0.8
0.8
V
1.S
1.5
V
0.3
170
1
3
200
,..A
,..A
,..A
-1
,..A
VIN(1), Logical "1"
Input Voltage
Vcc=S.2SV
VIN(O), Logical "0"
Input Voltage
Vcc=4.7SV
IIN(1), Logical "1"
Input Current
VIN(1) = SV; CS, RD
VIN(1)=SV; WR
VIN(1)=SV; Mode
IIN(O), Logical "0"
Input Current
VIN(O)=OV; CS, RD, WR,
Mode
Mode
1.5
O.OOS
0.1
SO
1
3
200
O.OOS
0.1
SO
-O.OOS
-1
-O.OOS
VOUT(1), Logical "1" Vcc=4.7SV, IOUT= -360 ,..A;
Output Voltage
DBO-DB7, OFL, INT
Vec=4.7SV, IOUT= -10 ,..A;
DBO-DB7, OFL, INT
2.4
2.8
2.4
V
4.5
4.6
4.5
V
VOUT(O), Logical "0" Vcc=4.7SV, IOUT= 1.6 rnA;
Output Voltage
DBO-DB7, OFL, INT, RDY
0.4
0.34
0.4
V
lOUT, TRI·STATE
Output Current
VOUT=SV; DBO-DB7, RDY
VOUT=OV; DBO-DB7, RDY
0.1
-0.1
3
-3
0.1
-0.1
0.3
-0.3
3
-3
,..A
JLA
ISOURCE, Output
Source Current
VOUT=OV; DBO-DB7, OFL
INT
-12
-6
-4.0
-12
-9
-9
-7.2
-S.3
-6
-4.0
rnA
rnA
ISINK, Output Sink
Current
VOUT=SV; DBO-DB7, OFL,
INT, RDY
14
7
14
8.4
7
mA
Icc, Supply Current
CS=WR=RD=O
7.S
15
7.S
13
15
mA
AC Electrical Characteristics The following specifications apply for Vce= SV, tr= tf = 20 ns, VREF( +) = SV,
VREF( -) = OV and T A = 2SoC unless otherwise specified.
Parameter
Conditions
Typ
(Note 6)
Tested
Limit
(Note 7)
Design
Limit
(Note 8)
Units
leRD, Conversion Time for RD Mode
Pin 7 = 0, (Figure 2)
1.6
2.S
JLs
tACCO, Access Time (Delay from
Falling Edge of RD to Output Valid)
Pin 7 = 0, (Figure 2)
tCRD+20
tCRD+SO
ns
leWR.RD, Conversion Time for
WR·RDMode
Pin 7 = Vce; tWR = 600 ns,
tRD = 600 ns; (Figures 3a and 3b)
1.S2
JLs
tWR, Write Time
I
I
tRD, Read Time
Min
Max
(Note 4) See Graph
Min
Pin 7 = Vec; (Figures 3a and 3b)
(Note 4) See Graph
tAee1, Access Time (Delay from
Falling Edge of RD to Output Valid)
tACC2, Access Time (Delay from
Falling Edge of RD to Output Valid)
600
Pin 7 = Vec; (Figures 3a and 3b)
ns
SO
JLs
. 600
ns
Pin 7 = Vcc, tADtl; (Figure3b)
CL =1SpF
70
120
ns
CL =100 pF
90
1S0
ns
3·93
•
AC Electrical Characteristics (Continued) The following specifications apply for VCC= 5V. t,.=tj= 20 ns.
VREF( + ) = 5V. VREF( -) = OV and TA = 25°C unless otherwise specified.
Parameter
Conditions
Tested
Limit
(Note 7)
Typ
(Note 6)
Design
Limit
(Note 8)
Units
tl> Internal Comparison Time
Pin 7=Vcc; (Figures3b and 4)
CL =50pF
800
1300
ns
tiH. tOH. TRI-STATE Control
(Delay from Rising Edge of RD to
Hi-ZState)
RL =1k. CL =10 pF
100
200
ns
Iiiii'fL. Delay from Rising Edge of
WR to Falling Edge of INT
Pin 7 = Vee. CL = 50 pF
tRO>tl; (Figure3b)
tRO V+) the absolute value of current at that pin should be limited
to 1 mA or less. The 4 mA peckage input current limHs the number of pins that can exceed the power supply boundaries with almA current limit to four..
Nota 6: Typlcals are at 25°C and represent most likely parametriC norm.
Note 7: Tested limits are guaranteed to National's AOQL (Average OutgOing Quality Level).
Note 8: DeSign limits are guaranteed but not 100% tested. These limits are not used to calculate outgoing quality levels.
Nota 9: Human body model. 100 pF discharaged through a 1.5 kG resistor.
TRI-STATE Test Circuits and Waveforms
lIlI
t'H. c. =10 pF
tlH
Vee
1,1--
Vee
DATA
CI
-=- -=-
"J
OUTPUT
DATA VOH
OUTPUTS
-=-
GND
TL/H/5501-3
tr =20ns
tOH
vee
-=
90%
TVH/5501-4
DATA
Vee
OUTPUTS
1r~ 20 ns VOL
TL/H/5501-5
3-94
1,190%
50%
GND
eLI
"="":"
~
Vee - lIlI
DATA
OUTPUT
CI
10%
tOH' C. =10 pF
Vee
M
IIIi
50%
GND
Ik
tOH
90%
IIIi
10%
~
-1
0%
TL/H/5501-6
»
c
Timing Diagrams
oo
(X)
\
N
o
~-----
r.. . __
----1
tP
RDY
TL/H/5501-7
Note: On power-up the state of tNT can be high or low.
FIGURE 2. RD Mode (Pin 7 is Low)
,__
__----J/ ____ _
~D
-11m'l
OBO-OB7 -
-
-
-
-
-
TLIH/5501-8
FIGURE 3a. WR-RD Mode (Pin 7 is High and tROtl)
3-95
o
C'I
CO
o
o
Typical Performance Characteristics
C
in
ffi
~
>
z
8
II:
:::>
§
~
U)
I
5.0
5.25
5.5
Vee-SUPPLY VOLTAGE (V)
I
lL-~--~--~~--~
5'---'-_-'---'_-'---'
-100 -50
50
100 150
TA-AMBIENT TEMPERATURE ('C)
-100 -50
50
100 150
TA-AMBIENT TEMPERATURE ('C)
Accuracy vs tWR
2.0
~
1.5
\
g
ffi 1.0
~
15z
~
2.0
1.5
ffi 1.0
~
15z
o
500
600 700
tWl! (n.)
BOD
2.0
1\
OM
~ 1.5
Vcc l=5V
TA=25'C
\
IC
lil
f5 1.0
_ 0.5
ii!j
Ii!
.;5
z
~
0.5
1
\,
\.
500 600 700 800 900
tRD (ns)
tj, Internal Time Delay vs
Temperature
'"
1.5 I----II--+--+--+--j
1
2.0 .------,r--r---,---r--,
...
300 400 500 600 700 800 900
Ip (ns)
Output Current vs
Temperature
ISDURCE Vour = 2.4V
~
~ 1.0 I----If--+-~.PF=----j
"-
i
1.5
>-
-
;::
z
~
Ie
C
VCC=5V
VREF=5V
TA=25'C
tWR=600 ns
tRD=600 ns
o
300 400
:il
i
ffi 1.0
\
0.5
2.0
IC
o
900
Accuracy vs VREF
[VREF=VREF(+)-VREF (-)1
o
\
Ie
c
~
400
Vec=5V
VREF=5V
TA=25'C
tp=500 ns
twR =600 ns
! 1
Ie
\
0.5
Accuracy vs tp
Accuracy vs tRD
Vec=5V
VREF=5V
TA =25'C
!P=500 ns
fRD =600 ns
\
10 1--1~-+--+-+--l
ffi
..,
;::
10'
Power Supply Current vs
Temperature (not Including
reference ladder)
Conversion Time (RD Mode)
vs Temperature
o
.
Ii;
-I"'--
~
~ 0'---'-_-'---'_-'---'
T
a
VREF (V)
0.5
-100 -50
50
100 150
TA-AMBIENT TEMPERATURE ('C)
0'---'---'---'--'---'
-100 -50
0
50 100 150
TA-AMBIENT TEMPERATURE ('C)
TUH/5501-11
'I LSS= VREF
256
3-96
r----------------------------------------------------------------------.~
C
Description of Pin Functions
Pin Name
1
2
3
4
5
6
VIN
DBO
DB1
DB2
DB3
WR/RDY
7
Mode
8
RD
Function
Pin Name
Function
WR·RDMode
INT going low indicates that the conversion is completed and the data result is in
the output latch.INT will go low, -800 ns
(the preset internal time out, tl) after the
rising edge of WR (see Figure 3b); or INT
will go low after the falling edge of RD, if
RD goes low prior to the 800 ns time out
(see Figure 3a). INT is reset by the rising
edge of RD or CS (see Figures 3a and
3b).
RDMode
INT going low indicates that the conversion is completed and the data result is in
the output latch. INT is reset by the rising
edge of RD or CS (see Figure 2).
10 GND
Ground
11 VREF(-) The bottom of resistor ladder, voltage
range: GND,;;VREF(-),;;VREF(+) (Note
Analog input; range =GND,;;VIN,;;Vee
TRI-STATE data output-bit 0 (LSB)
TRI-STATE data output-bit 1
TRI-STATE data output-bit 2
TRI-STATE data output-bit 3
WR-RD Mode
WR: With CS low, the conversion is started on the falling edge of WR. Approximately 800 ns (the preset internal time
out, tl) after the WR rising edge, the result
of the conversion will be strobed into the
output latch, provided that RD does not
occur prior to this time out (see Figures
3a and 3b).
RDMode
RDY: This is an open drain output (no internal pull-up device). RDY will go low after the falling edge of CS; RDY will go
TRI-STATE when the result of the conversion is strobed into the output latch. It is
used to simplify the interface to a microprocessor system (see Figure 2).
Mode: Mode selection input-it is internally tied to GND through a 50 ,.,.A current
source.
RD Mode: When mode is low
WR·RD Mode: When mode is high
WR·RDMode
With CS low, the TRI-STATE data outputs
(DBO-DB7) will be activated when RD
goes low (see Figure 4). RD can also be
used to increase the speed of the converter by reading data prior to the preset
internal time out (tl' - 800 ns). If this is
done, the data result transferred to output
latch is latched after the falling edge of
the RD (see Figures 3a and 3b).
RDMode
With CS low, the conversion will start with
RD going low, also RD will enable the
TRI-STATE data outputs at the completion of the conversion. RDY going TRISTATE and INT going low indicates the
completion of the conversion (see Figure
9
INT
5)
12 VREF(+) The top of resistor ladder, voltage range:
VREF(-),;;VREF(+),;;Vec (Note 5)
CS must be low in order for the RD or WR
13 CS
to be recognized by the converter.
TRI-STATE data output-bit 4
14 DB4
TRI-STATE data output-bit 5
15 DB5
16 DB6
TRI-STATE data output--bit 6
TRI-STATE data output-bit 7 (MSB)
17 DB7
Overflow output-If the analog input is
18 OFL
higher than the VREF( + ), OFL will be low
at the end of conversion. It can be used to
cascade 2 or more devices to have more
resolution (9, 10-bit). This output is always
active and does not go into TRI-STATE
as DBO-DB7 do.
19 NC
No connection
Power supply voltage
20 Vee
2).
1.0 Functional Description
1.1 GENERAL OPERATION
The ADC0820 uses two 4-bit flash AID converters to make
an 8-bit measurement (Figure 1). Each flash ADC is made
up of 15 comparators which compare the unknown input to
a reference ladder to get a 4-bit result. To take a full 8-bit
reading, one flash conversion is done to provide the 4 most
significant data bits (via the MS flash ADC). Driven by the 4
MSBs, an internal DAC recreates an analog approximation
of the input voltage. This analog signal is then subtracted
from the input, and the difference voltage is converted by a
second 4-bit flash ADC (the LS ADC), providing the 4 least
significant bits of the output data word.
The internal DAC is actually a subsection of the MS flash
converter. This is accomplished by using the same resistor
ladder for the AID as well as for generating the DAC signal.
The DAC output is actually the tap on the resistor ladder
which most closely approximates the analog input. In addition, the "sampled-data" comparators used in the ADC0820
provide the ability to compare the magnitudes of several
analog signals simultaneously, without using input summing
amplifiers. This is especially useful in the LS flash ADC,
where the Signal to be converted is an analog difference.
3-97
oc
co
N
C
o ,---------------------------------------------------------------------
N
CD
o
o
cc:(
1.0 Functional Description
(Continued)
1.2 THE SAMPLED-DATA COMPARATOR
The actual Circuitry used in the ADC0820 is a simple but
important expansion of the basic comparator described
above. By adding a second capacitor and another set of
switches to the input (Figure 6), the scheme can be expanded to make dual differential comparisons. In this circuit, the
feedback switch and one input switch on each capacitor (Z
switches) are closed in the zeroing cycle. A comparison is
then made by connecting the second input on each capacitor and opening all of the other switches (5 switches). The
change in voltage at the inverter's input, as a result of the
change in charge on each input capacitor, will now depend
on both input signal differences.
Each comparator in the ADC0820 consists of a CMOS inverter with a capacitively coupled input (Figure 5). Analog
switches connect the two comparator inputs to the input
capacitor (C) and also connect the inverter's input and output. This device in effect now has one differential input pair.
A comparison requires two cycles, one for zeroing the comparator, and another for making the comparison.
In the first cycle, one input switch and the inverter's feedback switch (Figure 5a) are closed. In this interval, C is
charged to the connected input (V1) less the inverter's bias
voltage (VB, approximately 1.2V). In the second cycle (Figure 5b), these two switches are opened and the other (V2)
input's switch is closed. The input capacitor now subtracts
its stored voltage from the second input and the difference
is amplified by the inverter's open loop gain. The inverter's
input (VB') becomes
1.3 ARCHITECTURE
In the ADC0820, one bank of 15 comparators is used in
each 4-bit flash AID converter (Figure 7). The MS (most
significant) flash ADC also has one additional comparator to
detect input overrange. These two sets of comparators operate alternately, with one group in its zeroing cycle while
the other is comparing.
C
VB-(V1-V2)-C+Cs
and the output will go high or low depending on the sign of
VB'-VB·
TLlH/5501-13
TLlH/5501-12
.VB'-VB
• Vo ~ VB
·VonC ~ VI-VB
~
(V2-Vl)-C-
c+cs
.vo' ~ ~
[CV2-CVlj
C+C8
• Cs = stray input
node capacitor
aVo' is dependent on V2-Vl
• Va = inverter input
bias voltage
FIGURE 5b. Compare Phase
FIGURE Sa. Zeroing Phase
FIGURE 5. Sampled-Data Comparator
Z
RLADDER
(VI)
/}
Ci-
-o""s
-A
Vo ~ Cl +C2+C8 [Cl(V2-Vl)+C2(V4-V3)]
VIN,./
(V2)
(V3)~}n_
ANA GND
Z
1I2LSB./
(V4)
-0""
I
-A
_L
I
-
A
Cs
'
TL/H/5501-14
FIGURE 6. ADC0820 Comparator (from MS Flash ADC)
3-98
»
c
Detailed Block Diagram
oo
CI)
I'.)
4 BIT lS
4MSB
4BlTMS
FLASH CONY
o
FLASH CONY
r---------~-----------'~r.------------~----------~
R/3;?
1/2lSB VOLTAGE
IJIN VAEF(+)
VREF(-l
OACSWITCHES
R/3;!
caMP
OUTPUT
H/16
RIl6
A/16
eM
CL
OUTPUTS
OUTPUTS
A SWITCH CONTROL
LINES
•
DBO-DB7
1..J
1/'
1/2lSB VOLTAGE.:.....cr
GAOUNO~0'~
3
/8
VIN~
1..J
i..J
1/'
OAC OUTPUT
A
~
B
V"!..o/'0'~
MS COMPARATORS
CM1-CM16
lI1LS. VOLTAGE
!../~
REFlAODER~0'
REFLADDER~0'
FIGURE 7
3-99
lS COMPARATORS
el1-eus
TL/H/5501-15
0.-------------------------------------------------1
C'II
8
c
----TL/H/5501-17
RDMode
FIGURE A. WR-RD Mode (Pin 71s High and tRDtl)
RDY~,-_ _...../
Stand-Alone
For stand-alone operation in WR-RD mode, CS and RD can
be tied low and a conversion can be started with WR. Data
will be valid approximately 800 ns following WR's rising
edge.
' ......_...J/
.J)--------
DBD-DB7 - - - - - - - - - - - - - - ( \ , , _ _
WR-RD Mode (Pin 71s High) Stand-Alone Operation
TLlH/5501-16
a~W
When in RD mode, the comparator phases are internally
triggered. At the falling edge of RD, the MS flash converter
goes from zero to compare mode and the LS ADC's comparators enter their zero cycle. After 800 ns, data from the
MS flash is latched and the LS flash ADC enters compare
mode. Following another 800 ns, the lower 4 bits are recovered.
__________________________
~ LOW - - - - - - - - - - - - - - - - - - - - - - - - - -
.....I}----c:=>--
DBD-DB7 - -_ _
TLlH/5501-19
3-100
1.0 Functional Description
l>
C
oc
(Continued)
QC)
N
o
0
o
MS COMPARATORS ZERO
TO REFERENCE LADDER.
LS COMPARATORS FLOAT.
0
o
'
o
MS COMPARATORS COMPARE
VIN TO THEIR REFERENCE
LADDER TAP. THE COMPARATOR
OUTPUTS DIGITALLY TRACK
VIN-VLADDER TAP
\
0
~~NC~~:~~:~:A~~:?STO
MS COMPARATOR OUTPUTS
ARE LATCHED. THE MS
OAC IS SET. THE MS
COMPARATOR FLOATS.
LS COMPARATORS COMPARE
LSB SECTION OF REFERENCE
0
\
o
LS COMPARATOR OUTPUTS
ARE LATCHED AND CAN
BE READ.
MS COMPARATORS RETURN
TO ZERO MODE.
'--L::.A;:;OO::E:;;;R.'--_ _ _----'
INPUT CAPACITORS TRACK VIN.
TL/H/5501-20
Note: MS means most significant
LS means least significant
FIGURE 8_ Operating Sequence (WR-RD Mode)
OTHER INTERFACE CONSIDERATIONS
2.2 INPUT CURRENT
In order to maintain conversion accuracy, WR has a maximum width spec of 50 !,-s_ When the MS flash ADC's sampled-data comparators (Section 1.2) are in comparison
mode (WR is low), the input capacitors (C, Figure 6) must
hold their charge_ Switch leakage and inverter bias current
can cause errors if the comparator is left in this phase for
too long.
Since the MS flash ADC enters its zeroing phase at the end
of a conversion (Section 1.3), a new conversion cannot be
started until this phase is complete. The minimum spec for
this time (tp, Figures 2, 8a, 8b, and 4) is 500 ns.
Due to the unique conversion techniques employed by the
ADC0820, the analog input behaves somewhat differently
than in conventional devices. The AID's sampled-data comparators take varying amounts of input current depending
on which cycle the conversion is in.
The equivalent input circuit of the ADC0820 is shown in
Figure lOa. When a conversion starts (WR low, WR-RD
mode), all input switches close, connecting VIN to thirty-one
1 pF capacitors. Although the two 4-bit flash circuits are not
both in their compare cycle at the same time, VIN still sees
all input capacitors at once. This is because the MS flash
converter is connected to the input during its compare interval and the LS flash is connected to the input during its
zeroing phase (Section 1.3). In other words, the LS ADC
uses VIN as its zero-phase input.
2.0 Analog Considerations
2_1 REFERENCE AND INPUT
The two VREF inputs of the ADC0820 are fully differential
and define the zero to full-scale input range of the A to D
converter. This allows the designer to easily vary the span
of the analog input since this range will be equivalent to the
voltage difference between VIN( +) and VIN( -). By reducing
VREF(VREF=VREF(+)-VREF(-)) to less than 5V, the sensitivity of the converter can be increased (Le., if VREF=2V
then 1 LSB=7.8 mY). The input/reference arrangement
also facilitates ratiometric operation and in many cases the
chip power supply can be used for transducer power as well
as the VREF source.
This reference flexibility lets the input span not only be varied but also offset from zero. The voltage at VREF( -) sets
the input level which produces a digital output of all zeroes.
Though VIN is not itself differential, the reference design
affords nearly differential-input capability for most measurement applications. Figure 9 shows some of the configurations that are possible.
The input capacitors must charge to the input voltage
through the on resistance of the analog switches (about 5
kO to 10 kO). In addition, about 12 pF of input stray capacitance must also be charged. For large source resistances,
the analog input can be modeled as an RC network as
shown in Figure lab. As Rs increases, it will take longer for
the input capacitance to charge.
In RD mode, the input switches are closed for approximately
800 ns at the start of the conversion. In'WR-RD mode, the
time that the switches are closed to allow this charging is
the time that WR is low. Since other factors force this time
to be at least 600 ns, input time constants of 100 ns can be
accommodated without special consideration. Typical total
input capacitance values of 45 pF allow Rs to be 1;5 kO
without lengthening WR to give VIN more time to settle.
3-101
2.0 Analog Considerations (Continued)
External Reference 2.5V Full-Scale
Power Supply as Reference
V,N 1+1
IN+
V,N 1+1
V,N I-I
GND
V,N I-I
V,N 1+1
IN+
-"""IIt-......
5V
--fREFI + I
IN+
GNO
GND
':'
Uk
5V
Input Not Referred to GND
1.2k
REFI+J
5V -""',..,..._~ REFI + I
REFI-I
VIN I - I - - -.....--f REFI-I
LM385-2.5
REFI-I
.~
':'
TL1H/5501-21
* .'
oj
TLlH/5501-22
-t
* Current path must
still exist from VIN(-I
to ground
TLlH/5501-23
FIGURE 9. Analog Input Options
~ l
VI'_J\I\Rs~~_"R,..DN"""'- .....--~~~~v
-15V
I.B2k
1%
3-104
TLlH/5501-31
Co)
b
-.of
'<
C:;'
Digital Waveform Recorder
ATDa
CONVERTERS
MEMORY
AOC0820
2KxBRAM
"C
ADDRESS
COUNTERS
AS
AD
ANALOG
INPUT
1.
OV TO 5V
10
A TO 0 CONTROL LOGIC
et
»
"C
DM74LS393
"2-
CLR1~
C:;'
CLR2
I»
':'
0'
:s
en
elx
AOC0820
5V
--I
VIN
MODE
080
eI
20
DM74LS393
AID
':'
all
I ;::::::J~
Wii,
021
I I
WI!,
CLOCK
o
t:
8
RDI
DM74LS164 04
lili, WII,
IWl!2 Efiii,
(71
'g."
III
EWIi,
03
~
lWiI.
'0
0
Eiiih
RDz
Eiiii,
elx
STORED
OIGlnZfO
OUTPUT
OVID -5V
':'
5V
lM311
':'
':'
TRIG LEVEL
5V~
5V.....J¥'A
•
• 1.3M samples/sec
• 4k memory
':'
T1IIGGER
TL/H/5501-32
O~800av
Ii
C)
C'I
~
CJ
o011(
r----------------------------------------------------------------------------,
Ordering Information
Part Number
ADC0820BD
ADC0820BCD
ADC0820BCV
Total
Unadjusted Error
±%LSB
ADC0820BCM
ADC0820BCN
ADC0820CJ
ADC0820CCJ
ADC0820CCV
ADC0820CCM
ADC0820CCN
±1 LSB
Package
D20A-Cavity DIP
D20A-Cavity DIP
V20A-Molded Chip
Carrier
M20B-Wide Body Small
Outline
N20A-Molded DIP
J20A-Cerdip
J20A-Cerdip.
V20A-Molded Chip
Carrier
MJ20B-Wide Body Small
Outline
N20A-Molded DIP
3-106
Temperature
Range
-55·C to + 125·C
- 40·C to + 80·C
O·Cto +70·C
O·Cto +70·C
O·Cto +70·C
- 55·C to + 125·C
-40·C to + 85·C
O·Cto +70·C
O·Cto +70·C
O·Cto +70·C
~National
~ Semiconductor
ADC0829 fLP Compatible 8-Bit AID
with 11-Channel MUX/Digitallnput
General Description
Features
The ADC0829 is an 8-bit successive approximation AID
converter with an II-channel multiplexer of which six can
be used as digital inputs, as well as, analog inputs.
II
This AID is designed to operate from the /-,P data bus using
a single 5V supply.
Channel selection, conversion control, software configuration and bus interface logic are all contained on this monolithic CMOS device.
This device contains three 16-bit registers which are accessed via double byte instructions. The control register is a
write only register which controls the start of a new conversion, selects the channel to be converted, configures the 8bit 1/0 port as input or output, and provides information for
the 8-bit output register.
The conversion results register is a read only register which
contains the current status and most recent conversion results. The discrete input register is also a read only register
which contains the four address bits of the selected channel, and the six discrete inputs which are connected to the
analog multiplexer.
II
II
II
II
II
II
III
III
Easy interface to all microprocessors or operates
"stand alone"
Operates ratiometrically or with analog span adjusted
voltage reference
II-Channel multiplexer with latched control logic of
which six can be used as digital inputs
0 to 5V analog input range with single 5V supply
TTL/MOS input/output compatible
No zero or full scale adjusts required
Standard 28-pin DIP
Temperature range -40'C to +85'C
ADC0829 equivalent to MM74C934
Key Specification
8 Bits
±% LSB and ±1 LSB
256/-,s
5VDC
50 mW
.. Resolution
III Total Unadjusted Error
II Conversion Time
III Single Supply
.. Low Power
Connection and Block Diagrams
VAEF
AGND
1
28
VREF (CH1)
GND
2
27
Vee
DB7
3
26
CHO
DB6
4
25
CH2
DB5
5
24
CH3
DB4
6
23
CH4
DB3
7
22
CH5
DB2
8
OBI
CHO, 11
CH2-CH11
PO-P5
11
6-BIT AID
SUCCESSIVE
APPROXIMATION
EOC
21
PO (CHIO)
20
PI (CH11)
P2(CH8)
DBO
10
19
R/W
11
18
P3 (CH9)
4>2 CLOCK
12
17
P4(CH6)
RSI
13
16
P5(CH7)
CS
14
15
RESET
ANALOG
DATA
REGISTER
(READ ONLY)
DIGITAL
DATA
REGISTER
(REAO ONLY)
AO-A3
CONTROL
REGISTER
(WRITE ONLY)
TL/H/5508-1
DBO-OB7
R/W
Top View
BUS
CONTROL
LOGIC
Ordering Information
Error
± 112 Bit Unadjusted
ADC0829BCN
± 1 Bit Unadjusted
ADC0829CCN
Package Outline
cs
RSI
RESET
"'2
TL/H/5508-2
N28B
3-107
~
co
8c
c(
Absolute Maximum Ratings (Notes 1 and 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Package Dissipation
at TA = 25·C (Board Mount)
Supply Voltage, Vee (Note 3)
ESD Susceptability (Note 8)
Voltage
Logic Inputs
Analog Inputs
Storage Temperature
875mW
260·C
Lead Temp. (Soldering, 10 seconds)
6.5V
2000V
±5mA
+20mA
Input Current Per Pin
Package
-0.3VtoVcc + 0.3V
-0.3Vto Vcc + 0.3V
- 65·C to + 150·C
Operating Conditions (Notes 1 and 2)
Supply Voltage, Vee
4.75 Voe to 5.5 Voe
-40·Cto + 85·C
Temperature Range
Converter and Multiplexer Electrical Characteristics Vee=5Voe=VREF(+), VREF(-)=GND,
SCLK <1>2=1.048 MHz, -40·C s; TA + 85·C unless otherwise noted.
Parameter
Total Unadjusted Error; (Note 3)
ADC0829BCN
ADC0829CCN
Typ
(Notes)
Min
Conditions
VREF Forced to 5.000 Voe
VREF Forced to 5.000 Voe
Reference Input Resistance
(Note 4) V( + ) or V( -)
VREF( +) Voltage, Top of Ladder
Measured at REF( + )
±1f2
±1
LSB
LSB
kO
GND-0.10
VREF(+) + VREF(-)Voltage
2
'
Center of Ladder
Units
4.5
1.0
Analog Input Voltage Range
Max
Vee+ 0.1O
V
Vee
Vee + 0.01
V
Vee/2- 0.1
Vee/2
Vee/2+ 0.01
V
-0.1
0
VREF( -) Voltage,
Bottom of Ladder
Measured at REF( -)
IOFF, Off Channel
ON Channel = 5V
ADC0829BCN
±400
nA
Leakage Current (Note 6)
OFF Channel = OV
ADC0829CCN
±1
/LA
ION,On Channel
ON Channel=OV
ADC0829BCN
±400
nA
Leakage Current (Note 6)
OFF Channel = 5V
ADC0829CCN
±1
/LA
V
AC Characteristics Vee=VREF(+)=5V, tr =tf=20 ns and TA=25·C (Note 7) unless otherwise noted.
Parameter
Conditions
Min
teyC(2), <1>2 Clock Cycle Time (1 Ifcj>2)
0.943
PWH(2), <1>2 Clock Pulse Width, High
440
PWd2), <1>2 Clock Pulse Width, Low
410
Typ
Max
Units
10.0
/Ls
ns
ns
25
tr(2), <1>2 Rise Time
30
tf(2), <1>2 Fall Time
145
ns
ns
tAS, Address Set Up Time
RS1, R/W,CS
ns
tOOR, Data Delay (Read)
DBO-DB7
tosw, Data Delay Setup (Write)
DBO-DB7
185
ns
tAH, Address Hold Time
RS1, R/W,CE
20
ns
tOHW, Input Data Hold Time
DBO-DB7
20
ns
tOHR, Output Data Hold Time
DBO-DB7
10
ns
Analog Channel Settling Time
32
Clocks
Ie, Conversion Time
256
Clocks
335
3-108
ns
»
c
Digital and DC Characteristics Vee=4.5V to 5.5V and -40'C';;TA';;B5'C unless otherwise noted.
Conditions
Parameter
Min
Q
Units
Max
Typ
0
Bus Control Inputs (R/W, ENABLE RESET, RS1, CS) and Peripheral Inputs (PO-P5)
VIN(1), Logical "1" Input Voltage
2.0
V
VIN(O), Logical "0" Input Voltage
O.B
V
liN, Input Leakage Current
±1
p.A
V+) the absolute value of current at that pin should be limited
to 5 mA or less. The 20 mA package input current limits the number of pins that can exceed the power supply boundaries with a 5 mA currentlimH to four.
Note 5: Human body model, 100 pF discharged through a 1.5 kU resistor.
Note 6: Total unadjusted error includes offset, full·scale, linearity. and multiplexer errors.
Note 7: Cannot be tested for ADCOB32.
Note 8: For VIN(-):>VIN(+) the digital output code will be 0000 0000. Two on.chip diodes are tied to each analog input (see Block Diagram) which will forward
conduct for analog input voltages one diode drop below ground or one diode drop greater then the Vee supply. Be careful, during testing at low Vee levels (4.5V),
as high level analog inputs (5V) can cause this input diode to conduct-especially at elevated temperatures. and cause errors for analog inputs near full-scale. The
spec allows 50 mV forward bias of either diode. This means that as long as the analog VIN or VREF does not exceed the supply voltage by more than 50 mY, the
output code will be correct. To achieve an absolute 0 Voc to 5 Voc input voltage range will therefore require a minimum supply voltage of 4.950 Voe over
temperature variations. initial tolerance and loading.
Note 9: Leakage current is measured with the clock not switching.
Note 10: A 40% to 60% clock duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of
these limits, the minimum, time the clock is high or the minimum time the clock is low must be at least 1 p.s. The maximum time the clock can be high is 60 p.s. The
clock can be stopped when low so long as the analog input voltage remains stable.
Note 11: Since data, MSB first, is the output of the comparator used in the successive approximation loop, an addHional delay is built In (see Block Diagram) to
allow for comparator response time.
Note 12: Typicals are at 25'C and represent most likely parametric norm.
Note 13: Tested limits are guaranteed to National's AOOL (Average Outgoing OualHy Level).
Note 14: Guaranteed but not 100% production tested. These limits are not used to calculate outgoing quality levels.
3-118
»
c
Typical Performance Characteristics
n
o
...
.....
OC)
Co)
Unadjusted Offset Error
vs VREF Voltage
16
Sx
-I[!!
II
ol!
~.;=2.mv.
A 2S'C
12
10
..
1.5
VIN(+I=VIN(-I=OV
14
.. 1.25
~
i
1.0
~
0.01
o
0.1
1.0
VREF (Voci
r-'"""1-.,--..,....-.,----,
N
.....
'"
~ 0.25 1---1f---f--+--=F~-I
~
VREF=5.0V
!eLK=250 kHz
z
::;
OC)
Co)
....
.....
OL-~--~~--~~
o
-100 -50
VREF (VI
0
50
100
150
TEMPERATURE ('CI
TLlH/5583-2
Output Current vs
Temperature
Linearity Error vs fClK
25 r--::I--,.--r---,---,
3.0
!
VREF=5V
Vcc=5V
2.5
l....
125'C
iI
B
;; 2.0
~w
~
1.5
I
~ 1.0
~ 0.5
~
-5S'C
o
l
1.0
!!j
B
.
10 100 200 300 400 SOD
!eLK (kHzl
~
'"
'"
~
lL
5
~
600
1_~C:=4~~~~--J
10 I'SOURCE Voe = 2.4V
....
::0
25'C
20
!Z 15
E 0.5
OL-L.-L.-L.-L.-L.-L.-~
O'-----'---'---'--.L---I
-75-50-25 0 25 50 75 100125
-100 -50
50 10.0
TEMPERATURE ('CI
TEMP£RATURE ('CI
Note: For ADC0832 add 'REF.
125
TL/H/5583-40
Power Supply Current
VSfCLK
15.--.--,--,-,---,
Vcc 15V
Leakage Current Test Circuit
@~5"C
5V
ADCOB3X
CH A (ON CHANNEL)
100
400
500
CHANNEL
VOLTAGE
SELECT
TLlH/5583-29
....------------1::: }
._________
.:
OFF
CHANNELS
.. --------I
TLlH/5583-3
3-119
»
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»
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!!!
~
~ 0.5
z
::; 0.25
0.50
~
.-- I---JCC=5J
(250 kHzl
i5 0.75 I-- r-- TA=25'C
o
Linearity Error vs
Temperature
Linearity Error vs VREF
Voltage
»
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8
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r---------------------------------------------------------------------------------,
TRI-STATE Test Circuits and Waveforms
c(
"..,.
C")
Vee
co
o
Vee --I-'-~=----
o
cc(
fS
~J-----'
t--1--....-o~:~:UT
DDAN~ ~:'H
'~
"N
C")
:::
co
o
SARSDUTPUTS
o
GND------'"
c
~
.,...
tOH
C")
co
o
o
cc(
Vee
Vee
GND
DATA
OUTPUT
tOH
DO AND Vee
~
SARS OUTPUTS
---10%
VOL
TLlH/5583-23
TLlH/5583-4
Timing Diagrams
Data Output Timing
Data Input Timing
elK
eLK
fS
~~
DATA
DATA
R
~~
TL/H/5583-24
TLIH/5583-25
ADC0831 Start Conversion Timing
CLK
START CONVERSION
00-----'\1
BIT 6
TLlH/5583-26
3-120
Timing Diagrams (Continued)
ADCOB31 Timing
10
11
TL/H/5583-27
• LSB first output not available on ADC0831.
ADCOB32 Timing
CLOCKICLKI
CHIP SELfCT ICSI
DATA OUT (001--::==--1
TRI-STATE
TUH/5583-28
ADCOB34 Timing
CUICK ICLKI
CHIP SELECT 11:11
DATA IN 1011
SAR STATUS IBARSI
DATA OUT I D O I - - - - - - - - i
MUX
TL/H/5583-5
3-121
ADC0831 / ADC0832/ ADC0834/ ADC0838
::!
3
S"
CC
c
ADC0838 Timing
10
11
12
13
14
iii"
15
16
17
18
19
20
21
22
23
24
25
...
CC
26
I\)
3
CLOCK (CLK)
til
~
:J
g.
CHIP SELECT (~)
C
CD
,e,
OATA IN (01)
SAR STATUS (SARS)
~
I\J
I\J
R="D"
DATA OUT (~O) - - - - - = = : : - - - - - 1
USINGSE[SE
TO CONTROL
LSB FIRST
OUTPUT
00----------------1
7
1
(MSB)
I~.
MUX SETTLING
TLlH/5583-6
'" Make sure clock edge # 18 clocks in the LSB before
SE is taken low
oz
Og,
1;'"
~~
01
cii
Gl"T1 0
Z 0~ 3
•
CD
m~
11
cs~
I
1
lIt
-
l>
t
C
oo
(XI
9.
w
~ i; i
~g !fl
0)
~! §
0''0 g.
n ..... g
~(ii' ~
START CONV AND ENABLE TSL DUTPUT BUFFER
16
VCC
"c: '"
~
g
!e.
1
CH 0*
0'
:l
!..
l
OJ
en- "<
mOl!!.
Co
'<
~~ ~
~~
i
_." :::r
~~ ~
2Co m
m ~
0
o In -g
,,~
~:-"
~
N
c.>
-en
m
~
o
g
0'
...
CH 1*
n
CH 2*
C
iii'
CH J*
ea
ANALOG
MUX
(EOUIVALENTI
CH4
iiJ
3
!fJ
CH 5
CH6*
cs
.r
I
S-
"-'
;r
CH 7*
I
·"':----;R:-1j
COM*
VREI
VCC
~
»
~
.r
i
0--,
T , ., TO ~~~E~~:~
SAR
LOGIC
ANO
LATCH
IV ZENER
19
v. .- 0
':'
!"
9
13
18
17
10
DGN°l
':'
.:mf
.
TO
INTERNAL
CIRCUITS
...
I
l'
B7
I
86
B5
~
~
~
~
~
~
9·B1T
SHIFT
REGISTER
"
CDMP
18
Co
J
n
ClK
o~' ~.
qi
."
C
:l
11
INPUT PROTECTION - All LOGIC INPUTS
AGND
Sg.
':'
CD
9
TL/H/55B3-7
~.
50.
a
9£90::>OV/f7£90::>OV/t:£90::>OV/ ~ £90::>0'1
iii
co
('I)
co
0
0
Connection Diagrams
C
ADC0838 8-Channel MUX
ADC0834 4-Channel MUX
<0:1'
Dual-In-Line Package
Dual-In-Line Package
Functional Description
(Continued)
Since the input configuration is under software control, it
can be modified, as required, at each conversion. A channel
can be treated as a single-ended, ground referenced input
for one conversion; then it can be reconfigured as part of a
differential channel for another conversion. Figure 1 illustrates the input flexibility which can be achieved.
The analog input voltages for each channel can range from
50 mV below ground to 50 mV above Vee (typically 5V)
without degrading conversion accuracy.
To understand the operation of these converters it is best to
refer to the Timing Diagrams and Functional Block Diagram
and to follow a complete conversion sequence. For clarity a
separate diagram is shown of each device.
2.0 THE DIGITAL INTERFACE
A most important characteristic of these converters is their
serial data link with the controlling processor. Using a serial
communication format offers two very significant system improvements; it allows more function to be included in the
converter package with no increase in package size and it
can eliminate the transmission of low level analog signals by
locating the converter right at the analog sensor; transmitting highly noise immune digital data back to the host processor.
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....
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:r>
c
oo
1. A conversion is initiated by first pulling the CS (chip select) line low. This line must be held low for the entire conversion. The converter is now waiting for a start bit and its
MUX assignment word.
"-
2. A clock is then generated by the processor (if not provided continuously) and output to the AID clock input.
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3. On each rising edge of the clock the status of the data in
(01) line is clocked into the MUX address shift register. The
start bit is the first logic "1" that appears on this line (all
leading zeros are ignored). Following the start bit the converter expects the next 2 to 4 bits to be the MUX assignmentword.
CD
Co)
N
:r>
CD
Co)
oIloo
"-
:r>
c
oo
CD
Co)
CD
8 Single-Ended
8 Pseudo-Differential
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
CDM(-I
+
CDM(-I
VSIAS-=-
J
Mixed Mode
4 Differential
0.1
•
+
D.lj
2.3
+
2.3
+
4.5
+
6.7
+
+
+
COM (-I
VSIAS-=-'
~
FIGURE 1. Analog Input Multiplexer Options for the ADC0838
3-127
TL/H/55B3-9
= .--------------------------------------------------------------------,
=
o
C')
(.)
C
-
··
CHO
>-
CSI+- GO
·•
···
ClK I+- SK
0
AOCOB3B
•
•
•
>-
COP420
Of
CH7
DO
f4-- so
CHO
c
oo
CSI+- P13
CO
(0)
N
......
~
CLK I+- P12
AOC083B
C
o
o
INS8048
CO
Oil+- Pl1
(0)
~
......
•
r--+ SI
>-
~
CH7
C
O0r-+ Plo
o
o
CO
(0)
TL/H/5583-13
COP CODING EXAMPLE
Mnemonic
LEI
SC
OGI
CLRA
AISCl
XAS
LDD
NOP
XAS
Instruction
;SELECT AID (CS=O)
;BIT COUNTER - 5
;A - MUX ADDRESS
;CY - ADDRESS BIT
;TESTBIT
;BIT=O
ZERO:
ANL
Pl, #OFEH ;DI-O
;CONTINUE
JMP CONT
;BIT=l
ONE:
ORL Pl, #1
;DI-l
CONT:
CALL PULSE
;PULSE SK 0 -+ 1 -+ 0
DJNZ B, LOOP 1 ;CONTINUE UNTIL DONE
;EXTRA CLOCK FOR SYNC
CALL PULSE
MOV B, #8
;BIT COUNTER - 8
;PULSE SK 0 -+ 1 -+ 0
LOOP 2: CALL PULSE
IN
A,Pl
;CY-DO
RRC A
RRC A
MOV A,C
;A-RESULT
RLC A
;A(O) - BIT AND SHIFT
MOV C,A
;C-RESULT
DJNZ B, LOOP 2 ;CONTINUE UNTIL DONE
RETR
;PULSE SUBROUTINE
PULSE: ORL Pl, #04
;SK-l
NOP
;DELAY
ANL
Pl, #OFBH ;SK-O
RET
Mnemonic
Pl, #OF7H
ANL
MOV B,#5
MOV A, #ADDR
LOOP 1: RRC A
JC
ONE
Instruction
ENABLES SIO's INPUT AND OUTPUT
C=l
GO=O(CS=O)
CLEARS ACCUMULATOR
LOADS ACCUMULATOR WITH 1
EXCHANGES SIO WITH ACCUMULATOR
AND STARTS SK CLOCK
LOADS MUX ADDRESS FROM RAM
INTO ACCUMULATOR
START:
LOADS MUX ADDRESS FROM
ACCUMULATOR TO SIO REGISTER
i
8 INSTRUCTIONS
.,j.
XAS
XIS
CLR A
RC
XAS
XIS
OGI
LEI
CO
8048 CODING EXAMPLE
READS HIGH ORDER NIBBLE (4 BITS)
INTO ACCUMULATOR
PUTS HIGH ORDER NIBBLE INTO RAM
CLEARS ACCUMULATOR
C= 0
READS LOW ORDER NIBBLE INTO
ACCUMULATOR AND STOPS SK
PUTS LOW ORDER NIBBLE INTO RAM
GO=l (CS=l)
DISABLES SIO's INPUT AND OUTPUT
3-131
•
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o
(,)
Applications (Continued)
C
--f VIN!+)
+
1"D"F
Uk
-----,
ADC0831
r--:-:-:=:-+--'
I
I
I
I
SETS ZERO
CODE VOLTAGE
Uk
LM336
330
I
I
_J
1k
2 VUC
ZERO AOJ
TL/H/5583-16
3-134
»
Applications
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oo
(Continued)
ClO
....
Obtaining Higher Resolution
Co)
.......
»
c
Vcc-1~---1~----------'------------------,
Vee
V,N
'-
+
-
>Z.5V
,;Z.5V
-
+
:}
:}
:}
:}
R
VREF
ADCDB3Z
oo
~
R
ClO
Co)
3R
N
.......
»
c
oo
ClO
Co)
01:00
.......
»
c
oo
ClO
Co)
1
ClO
TL/H/5583-17
Controller performs a routine to determine which input polarity (9-bit example) or which channel pair (10-bit example) provides a non-zero output code.
This information provides the extra bits.
a) 9-Bit AID
b)10-Bit AID
Protecting the Input
Vee
(5V oc)
-15 Voc
AOC0832
Diodes are 1N914
TLlH/5583-18
3-135
ICD
CI
(J
Applications (Continued)
..
C
High Accuracy Comparators
~
5Y
C')
CD
CI
(J
Vet
C
+
CC
.....
C'OI
:}
C')
CD
CI
g
~
....
SYSTEM
TEST
POINTS
}
>-----I~
TO
CONTROLLER
jAOC0838
C')
~
g
CC
¥TN 3
COM
DO
~
allis if +VIN > -VIN
DO
~
all Os If +VIN < -VIN
TUH/5583-36
Digital Load Cell
330
TUH/5583-19
• Uses one more wire than load cell itself
• Two mini-DIPs could be mounted Inside load cell for digital output transducer
• Electronic offset and gain trims relax mechanical specs for gauge factor and offset
• Low level cell output is converted Immediately lor high noise Immunity
3-136
Applications (Continued)
4 mA-20 mA Current Loop Converter
lOOk
INP
24k
6.2k
200k .....--~vc~e---.
+
+IN
10k~--Ir--+--I-IN
lM3B5-2.5V
Vee
CD4024
CLK
CS~---~-'lJV\r_
ADCOS31
6N139
om COUPLER
10k
DO I-~HI4I-t"""''V\;'''""- Vee
5k ~_I--IVREF
lM385-2.5V
47k
3.9k
""-----V+
300k
......- - - - V o
! ~-+-----'
......- - - - - - - 6 N O
• All power supplied by loop
. • 1500V isolation at output
Tl/H/5583-20
Isolated Data Converter
lN4148
~-~~I*-t-----------~VceO~
10k
CLK-W\r-ooj
6V
ClK
470
cs
lOOk
Vee
ADC083B
10k
CS-W\r--I
DI
lfl-
CHANNELS
Vee
00
6.8k
10k
":'
• No power required remotely
• 1500V isolation
TUH/5583-39
3-137
ADC0831 I ADC08321ADC08341ADC0838
»
1:1
Two Wire Interface for 8 Channels
'2.
(i'
S»
6'
0.1 pF
:::I
en
11
a.
IDV
Ik
~...."
18k
,
'~II.'"
10k ~ lOOk
IDV
LM393
'::"
68k
1
LM393
DUAL COMPo
t
Vee
IN4148
16k
DUAL CDMP.
::::I
'::"
•
Ik
18k
• "'r-VC
=-r-lJ r
1-
18k
ooW
CLK
lOOk
~
Ve
~
lOOk
AOCOB3B
+
IN4148
V· ~ Ve
+
'i'OOPF
Co>
CD
lOOk
10k
DI
veehvee
'::"
rO.
-,
"J"0"pF
33k
'::"
• No additional connections
• Cs derived from extended high on ClK line> 100 pS n.n.r----t.I1It
• Timing arranged for 40 kHz. could be changed up or down by component change
• 10% ClK frequency change without component change OK
~
:I:
i~
,pF
l>
C
o
Applications (Continued)
«:)
CD
....W
......
Two Wire 1-Channellnterface
~~
lZV
CLK
E.
ivL
Uk
lBk
lBk
C S - 'ZV
AND
10k
00-
lk
C
~~
47k
V
loo~
....
lIZLM393
'i~
l>
o
«:)
"';ZNZZZZ
CD
W
N
......
l>
....
lOOk
C
o
«:)
II
10k
*r"":"
~ r lN414B
DO
~ ~lN414B
lOOk
CD
W
Vee
~
10k
~
16k
~
":"
47k
....
:f;}
lBk
Vee
V
C1
+
LM393
.... DUAL COMIIIRATDR
~
• Simpler version 0' Iklhannel
• Cs derived 'rom long elK pulse
...
~
zoo
ADCOB31
l>
C
o
«:)
CD
W
CD
lOOk
~
- '-560 pF
1'~'
eLK
......
""
Vee
-
.,; k
~ ~5.1V
....
,.,.
~
TUH/5583-22
Ordering Information
Total
Unadjusted Error
Package
Temperature
Range
±%
Hermetic (J)
Hermetic (J)
Molded(N)
-55'Cto + 125'C
-40'Cto +85'C
O'Cto +70'C
ADC0831CCJ
ADC0831CCN
±1
Hermetic (J)
Molded(N)
-40'Cto +85'C
O'Cto +70'C
ADC0832BJ
ADC0832BCJ
ADC0832BCN
±%
Hermetic (J)
Hermetic (J)
Molded(N)
-55'Cto + 125'C
- 40'C to + 85'C
O'Cto +70·C
ADC0832CCJ
ADC0832CCN
±1
Hermetic(J)
Molded (N)
- 40·C to + 85·C
O'Cto +70'C
ADC0834BJ
ADC0834BCJ
ADC0834BCN
±%
Hermetic(J)
Hermetic (J)
Molded(N)
-55·C to + 125·C
-40'Cto +85'C
O'Cto +70·C
±1
Hermetic (J)
Molded(N)
-40·Cto +85·C
O"Cto +70·C
±%
Hermetic (J)
Hermetic (J)
PCC(V)
Molded (N)
- 55'C to + 125'C
- 40·C to + 85·C
O'Cto +70'C
O"Cto +70·C
±1
Hermetic (J)
PCC(V)
Molded (N)
- 40·C to + 85·C
O'Cto +70'C
O·Cto +70·C
Part Number
ADC0831BJ
ADC0831BCJ
ADC0831BCN
Analog Input
Channels
1
2
4
ADC0834CCJ
ADC0834CCN
ADC0838BJ
ADC0838BCJ
ADC0838BCV
ADC0838BCN
ADC0838CCJ
ADC0838CCV
ADC0838CCN
8
See NS Package Number JOBA, J14A, J20A, NOBE, N14A, N20A or V20A
3-139
•
C')
C')
~ ~National
~ ~ Semiconductor
ADC0833 8-Bit Serial 1/0 AID Converter
with 4-Channel Multiplexer
General Description
Features
The ADCOa33 series is an a-bit successive approximation
AID converter with a serial I/O and configurable input multiplexer with 4 channels. The serial I/O is configured to comply with the NSC MICROWIRETM serial data exchange standard for easy interface to the COPSTM family of processors,
as well as with standard shift registers or ,..,Ps.
• NSC MICROWIRE compatible-direct interface to COPS
family processors
• Easy interface to all microprocessors, or operates
"stand alone"
• Works with 2.5V (LM336) voltage reference
• No full-scale or zero adjust required
• Differential analog voltage inputs
• 4-channel analog multiplexer
• Shunt regulator allows operation with high voltage
supplies
• OV to 5V input range with Single 5V power supply
• Remote operation with serial digital data link
• TTL/MOS input/output compatible
• 0.3" standard width 14-pin DIP package
The 4-channel multiplexer is software configured for singleended or differential inputs when channel aSSigned by a 4bit serial word.
The differential analog voltage input allows increasing the
common-mode rejection and offsetting the analog zero input voltage value. In addition, the voltage reference input
can be adjusted to allow encoding any smaller analog .voltage span to the full a bits of resolution.
Key Specifications
•
•
•
•
•
a Bits
Resolution
Total Unadjusted Error
Single Supply
Low Power
Conversion Time
± Yz LSB and ± 1 LSB
5Voc
23mW
32,..,s
Connection and Functional Diagrams
Dual-In-Une Package
y+
CS.
CHO
1
14
2
Vee
01
3
ClK
CHI
4
CH2
5
l:S
CLK
DI
SARS
AOC0833
00
CH3· 6
DGNO
SARS
ADDRESS
LATCH
AND
DECODER
9
8
7
VRFI/2
AGNO
DO
('cHANNEl. S.E.
OR
2.cHANNEL
DlFF.
MUIliPUER
TLlH/5607-14
Top View
Order Number ADC0833BCJ,
ADC0833BJ, ADC0833CJ,
ADC0833CCJ, ADC0833BCN or
ADC0833CCN
See NS Package Number
J14AorN14A
CH3
V+
(SHUNT
REII)
Vee
VREF/2
AlNO
(5V)
TL/H/S607-1
3-140
:J>
C
Absolute Maximum Ratings (Notes 1 & 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Current into V
+ (Note 3)
15mA
Supply Voltage, Vee (Note 3)
Voltage
Logic Inputs
Analog Inputs
6.5V
-0.3V to Vee + 0.3V
-0.3V to Vee + 0.3V
Input Current per Pin (Note 4)
±5mA
Package Input Current (Note 4)
Storage Temperature
oo
Package Dissipation at
T A = 25'C (Board Mount)
Lead Temperature (Soldering, 10 sec.)
Dual-In-Line Package (Plastic)
Dual-In-Line Package (Ceramic)
260'C
300'C
ESD Susceptibility (Note 5)
2000V
00
O.BW
Operating Conditions (Notes 1 & 2)
Supply Voltage, Vee
4.5 Voe to 6.3 Voe
Temperature Range
ADCOB33BJ, ADCOB33CJ
ADCOB33BCJ, ADCOB33CCJ
ADCOB33BCN, ADCOB33CCN
±20mA
-65'Cto + 150'C
Electrical Characteristics
TMIN:O::TA:O::TMAX
-55'C:O::TA:O::125'C
-40'C:O::TA:O::B5'C
O'C:O::TA:O::70'C
v+
The following specifications apply for Vee =
= 5V, feLK = 250 kHz and
VREF/2 :0:: (Vee + 0.1 V) unless otherwise specified. Boldface limits apply from TMIN to TMAX; all other limits
TA = Tj = 25'C.
Parameter
Typ
(Note 6)
Conditions
Tested
Limit
(Note 7)
Design
Limit
(NoteS)
±'h
±%
±1
±1
±%
Units
CONVERTER AND MULTIPLEXER CHARACTERISTICS
Total Unadjusted Error
ADC0833BCN
ADCOBB3BJ, BCJ
ADCOB33CCN
ADCOB33CJ, CCJ
VREF/2 Forced to 2.500 Voe
±1
LSB
LSB
LSB
LSB
Minimum Total Ladder
Resistance (Note 9)
ADCOB33BCJ/CCJ/BJ/CJ
ADC0833BCN/CCN
7.0
7.0
2.6
2.6
2.6
k!l
k!l
Maximum Total Ladder
Resistance (Note 9)
ADC0833BCJ/CCJ/BJ/CJ
ADC0833BCN/CCN
7.0
7.0
11.8
10.B
11.8
k!l
k!l
GND-0.05
GND-0.05
GND-0.05
V
V
Vee + 0.05
Vee + 0.05
Vee+ 0 •05
V
V
±y..
±%
±y..
LSB
LSB
1
1
1
LSB
LSB
Minimum Common-Mode
Input Range (Note 10)
ADCOB33BCJ/CCJ/BJ/CJ
ADC0833BCN/CCN
All MUX Inputs and COM Input
Maximum Common-Mode
Input Range (Note 10)
ADC0833BCJ/CCJ/BJ/CJ
ADCOB33BCN/CCN
All MUX Inputs and COM Input
DC Common-Mode Error
ADCOB33BCJ/CCJ/BJ/CJ
ADC0833BCN/CCN
Change In Zero
Error From Vee = 5V
To Internal Zener
Operation (Note 3)
ADCOB33BCJ/CCJ/BJ/CJ
ADC0833BCN/CCN
±v,.
±v,.
15mAlntoV+
Vee = N.C.
VREF/2 = 2.500V
3-141
Co)
Co)
C")
C")
co
o
g
V+) the absolute value of current at that pin should be limited
to 5 rnA or less. The 20 rnA package input current limits the number of pins that can exceed the power supply boundaries with a 5 rnA current limit to four.
Nole 5: Human body model, tOO pF discharged through a t.5 kn resistor.
Nole 6: Typicals are at 25'C and represent most likely parametric norm.
Note 7: Tested lim"s are guaranteed to National's AOQL (Average Outgoing Quality Level).
Nole 8: Design limits are guaranteed but not 100% tested. These limits are not used to calculate outgoing quality levels.
Note 9: See Applications, section 3.0.
Nole 10: For VIN( -):> VIN( +) the digitsl output code will be 0000 0000. Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward
conduct for analog Input voltages one diode drop below ground or one diode drop graater than Ihe Vee supply. Be careful. during testing at low Vee levels (4.5V).
as high level analog inputs (5V) can cause this input diode to conduct-especially at elevated temperatures, and cause errors for analog inputs near full-scale. The
spec allows 50 mV forward bias of either diode. This maans that as long as the analog VIN or VREF doss not exceed the supply voltage by more than 50 mV, the
output code will be correct To achieve an absolute 0 Vee to 5 Vae Input voltage range will therefore require a minimum supply voltage of 4.950 Vae over
temperature variations, InHial tolerance and loading.
Nole 11: Leakage currant is measured with the clock not switching.
Nola 12: A 40% to 60% clock duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of
these limits, the minimum time the clock is high or the minimum time the clock is low must be at least 1/,-s. The maximum time the clock can be high is 60 /,-s. The
clocked can be stopped when low so long as the analog input voltage remains stable.
Nate 13: Since data, MSB firs~ is the output of the comparator used in the successive apprOximation loop, an additional delay is buiH in (see Block Diagram) to
allow for comparator response time.
3-144
r--------------------------------------------------------------------.~
C
Timing Diagrams
o
o
co
Co)
Co)
Data Output Timing
Data Input Timing
CLK
OATA
OUT (00)
TRI-STATE Test Circuits and Waveforms
--!--'-h::::---
VCC
~~IH
ODANO : : :
~
SARS OUTPUTS
GNO------=
1,=20 ns
tOH
Vcc
Vcc
GND
OOANDVCC~~
SARSOUTPUTS VOL
~
•
1,=20 ns
Leakage Current Test Circuit
5V
~
ADC0833
CH A (ON CHANNEL)
CHANNEL
VOLTAGE
SELECT
t-----I
L_________ :::}
CH 0
:~:NNELS
TL/H/5607 -2
3-145
~
~
CD
o
g
,---------------------------------------------------------------------------------,
Typical Performance Characteristics
cc
Effect of Unadjusted Offset
Error vs VREF/2 Voltage
Linearity Error vs
VREF Voltage
14 :::\
12~
10-
O~ r----.:-=-,---r-~--,
~'"
VIN(+)=VIN(-)=OV'"
~U~~~i~~
7ii'
~
FOR A ZERO ADJ. IF
THE SPAN IS REDUCED.
~
1.2S
15 0.75
6
!:
4
!i
a
2
o
~
Vcc=SV
(2S0KHz) _
TA=25"C
1.0
8
u
I
0.1
1"'-----
Vcc=5V
VRfF/2=2SV
z
::i
fcuci2S0KHr
OL-~
__
-100 -50
0
1.0
0.2S
~
"-
0.25
0
0.01
Linearity Error
vs Temperature
1~r=~--~--r-~--,
16
~
0
__
L-~
50
__
100
~
150
TEMPERATURE ("C)
Output Current
vs Temperature
Power Supply Current
vs Temperature
Linearity Error vs fCLK
25r-~--'---r-~--,
3.0
~
~
15
!:
a~
2.S
VREF!2=2.5V
vcc=sv
12S"C
2.0
lS
1.0
U
I
-55"C
I
L.
25"C
o
0
10 100
200
300
400
500
-100 -50
600
TEMPERATURE ("C)
fcue (KHz)
50
100
125
TEMPERATURE ("C)
Power Supply
Current vs fCLK
2.S
,..---,----,----r---r--,
Vcc 15v@is"C
2.01---1---+---+--+--1
1~
I-"""
l.oL-~--~--L-~--~
o
100
200
300
400
500
IcLK
."
C
~ .'._'M"U.'m.~_.'
ClK _12
..~____ .
:J
!l-
0'
:J
MUX
ADDRESS
~
.".
r-1::r®
·1
I
• __ I
o
T ..... , ..... T
'
~
/
-+-
Rr
TO
ANALOG
MUX
(EOUIVAlENTI
,',_1 1 ,
_
-II
·1·'
I ,
,
cl~
~TO~~R~U~~:~
,
~
1
r-
L
17
I
R I
cc
Dl
3
.!!
~
R
EOC
C
!!
B5
Vtc
~
'"iii'C
~CI
cs
I
13 INPUT
18
START
~
SAR
lOGIC
AND
lATCH
i'lVZENER
"::"
TIME
0'
n
~~
,
CDMP
1qJ
S~y
!!.
m
TO
INTERNAL
CIRCUITS
.
~
!!
!!.
I·IIT
SHIFT
REGISTER
IR
CS .....
F1
n
~
-y--v00
III
18
INPUT PROTECTION - All lOOIC INPUTS
-+TUH/5607-4
&&8000"
II
~
~
co
o
o
cc(
r-------------------------------------------------------------------------------~
Timing Diagram
CLOCK
(eLK)
CHIP SELECT
lal
ULE~~~==~~~L:::::::::~~~~~~~~~~IT[::::::::~::==~==~~
DAlAIN,,, ,
(011 ' "
DON'T
CARE
SGUI!IJ
,:::::~=~B'T~'~__,
1--+--
(SARS) TRI.
MUX
STATE
SElTlIHG-l----I---
TIME
TRI·
STATE
I
DATA ~~~ ----TRI-STATE:-----....j
TRI.
t-________~n~A~TE
UR~AruS~~~M~UX~C~ON~FI~GU~RA~T~IO~NW~O~RO~--t_----------------------1L____________________
TL/H/S607-5
acquisition systems is significantly simplified with this type
of input flexibility. One converter package can now handle
ground referenced inputs and true differential inputs.
A particular input configuration is assigned during the MUX
addressing sequence, prior to the start of a conversion. The
MUX address selects which of the analog inputs are to be
enabled and whether this input is single-ended or differential. In the differential case, it also assigns the polarity of the
channels. Differential inputs are restricted to adjacent channel pairs. For example channel 0 and channel 1 may be
selected as a differential pair. Channel 0 or 1 cannot act
differentially with any other channel. In addition to selecting
differential mode the sign may also be selected. Channel 0
may be selected as the positive input and channel 1 as the
negative input or 'vice versa . .This programmability is best
illustrated by the MUX addressing codes shown in the following table. The MUX address is shifted into the converter
through the 01 line.
Functional Description
1.0 MULTIPLEXER ADDRESSING
The design of the ADC0833 utilizes a sample-data comparator structure which provides for a differential analog input
to be converted by a successive approximation routine.
The actual voltage converted is always the difference between an assigned "+" input terminal and a "-" input terminal. The polarity of each input terminal of the pair being
converted indicates which line the converter expects to be
the most positive. If the assigned" +" input is less than the
"-" input the converter responds with an all zeros output
code.
A unique input multiplexing scheme has been utilized to provide multiple analog channels with software-configurable
single-ended (ground referred) or differential inputs. The analog Signal conditioning required in transducer-based data
TABLE I. MUX Addressing
Single-Ended MUX Mode
Channel #
Address
SGLI
0001
DIF
SIGN
1
0
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
1
SELECT
0
1
2
3
+
+
+
+
COM is internally ties to a GND
Differential MUX Mode
Channel #
Address
SGLI
0001
DIF
SIGN
1
0
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
SELECT
3-148
0
1
+
-
-
2
3
+
-
-
+
+
»
c
Functional Description (Continued)
(")
(;)
Since the input configuration is under software control, it
can be modified, as required, at each conversion. A channel
can be treated as a single-ended, ground referenced input
for one conversion; then it can be reconfigured as part of a
differential channel for another conversion. Figure 1 illustrates the input flexibility which can be achieved.
ting highly noise immune digital data back to the host processor.
Co)
Co)
To understand the operation of these converters it is best to
refer to the Timing Diagram and Functional Block Diagram
and to follow a complete conversion sequence.
1. A conversion is initiated by first pulling the CS (chip select) line low. This line must be held low for the entire conversion. The converter is now waiting for a start bit and its
MUX assignment word.
The analog input voltages for each channel can range from
50 mV below ground to 50mV above VcC(typically 5V) without degrading conversion accuracy.
2. A clock is then generated by the processor (if not provided continuously) and output to the AID clock input.
2.0 THE DIGITAL INTERFACE
A most important characteristic of these converters is their
serial data link with the controlling processor. Using a serial
communication format offers two very significant system improvements; it allows more function to be included in the
converter package with no increase in package size and it
can eliminate the transmission of low level analog signals by
locating the converter right at the analog sensor; transmit-
3. On each rising edge of the clock the status of the data in
(01) line is clocked into the MUX address shift register. The
start bit is the first logic "1" that appears on this line (all
leading zeros are ignored). Following the start bit the converter expects the next 4 bits to be the MUX assignment
word.
4 Single-Ended
D
00
2 Differential
+
+
2
+
3
+
D'1{
2'3{
+(-)
-(+)
+(-)
-(+)
UND
Mixed Mode
•
TlIH/5607-6
FIGURE 1. Analog Input Multiplexer Options for the ADC0833
3-149
~.-------------------------------------------------------------~
~
co
o
o
c
Applications
C
(Continued)
(')
o
00
Co)
Co)
Digitizing a Current Flow
Vcc
0.1
_
ILOAO
(2A FULL·SCALE)
(5VOC)o-~~~~~~--------~~~----~~~~~--------~-----------,
Vee
(5 VOC)
Vce~----------~-------------,
+
J
AOCOB33
100
ZERO
ADJ
>....----------1 CHI
10llF
9.1.
+<
VREFI2I-+--...
30
120k
r
1.
FS
ADJ
11lF
Operating with Automotive Ratiometric Transducers
VCC
(5VDC)
•
ADC0833
16.
lk
..... '......_ ..... FS
ADJ
8.2.
·VIN(-)~O.15
vee
15% of VCC"VXDR"B5% of Vee
TUH/5607-12
3·155
Applications (Continued)
Span Adjust: OV~VIN~3V
I&I(F~el
veet--1~-------'
r--<>--fVIN(+1
+
~"'F
2'
A0CDl33
1.11336
TL/H/5607 -1 B
Zero-Shift and Span Adjust: 2V ~VIN ~ 5V
Vee
(OVDel
veel-~"'"""--------...
r--<>--fVIN(+1
+
~'D'F
ADCl133
r-- ------,
I
I
SHIZERD
eDDEYDLrADE
Uk
330
.,..
.,..
1k
ZVoe
ZERO AD"
.,..
I
I
I
I
I
I
_J
TUH/5607-19
Protecting the Input
High Accuracy Comparators
Vee
IV
Vee
(5 Voc)
~['
-$
: }a"
NlC0833
2
Vnt2
TO
C\JfITRDLLER
:}2,3
-15 Voc
ADC0833
DO
= aliI. W+
VIN
>
-VIN
+
V,N
<
-VIN
DO = allOsil
Diodes are 1 N914
TUH/5607-20
For additional application ideas, refer to the data shee1 for lhe ADC0831 lamily of serial data converters,
3-156
TL/H/5607-13
l>
C
Ordering Information
o
«:)
Q)
Part Number
Temperature
Range
ADC0833BCJ
-40·C to + 85·C
ADC0833BCN
O·Cto +70·C
ADC0833BJ
-55·Cto + 125·C
ADC0833CCJ
-40·C to + 85·C
ADC0833CCN
ADC0833CJ
O·Cto +70·C
Total
Unadjusted
Error
w
w
±1/2 LSB
±1 LSB
-55·Cto + 125·C
•
3-157
,-'OS' r--------------------------------------------------------------------------------,
8
~National
!i ~ Semiconductor
ADC0841
8-Bit ILP Compatible AID Converter
General Description
Features
The ADC0841 is a CMOS 8-bit successive approximation
AID converter. Differential inputs provide low frequency input common mode rejection and allow offsetting the analog
range of the converter. In addition, the reference input can
be adjusted enabling the conversion of reduced analog
ranges with 8-bit resolution.
The AID is designed to operate with the control bus of a
variety of microprocessors. TRI-STATE@ output latches that
directly drive the data bus permit the AID to be configured
as a memory location or I/O device to the microprocessor
with no interface logic necessary.
• Easy interface to all microprocessors
• Operates ratiometrically or with 5 Voe
voltage reference
• No zero or full-scale adjust required
• Internal clock
• OV to 5V input range with single 5V power supply
• 0.3" standard width 20-pin package
• 20 Pin Molded Chip Carrier Package
Key Specifications
•
•
•
..
Resolution
Total Unadjusted Error
Single Supply
Low Power
±% LSB and ±
• Conversion Time
8 Bits
1 LSB
5 Voe
15 mW
40,..s
Block and Connection Diagrams
INTR
(5)
8-BIT
S.A.R.
080(18)-DB7(11)
AID
._-----------------------------_.
Molded Chip Carrier Package
Dual-In-Llne Package
cs
20
Vee
N.C.
Rii
WR
3
18
DBO
N.C.
4
17
DBl
INTR
5
16
DB2
V1N(+)
V1N(-)
6
15
DB3
7
14
DB4
AGND
8
13
085
VREr
DGND
9
12
DB6
10
11
087
2
19
TUH/8557-1
DBO
DBl
DB2
DB3
DB4
18
17
16
15
14
N.C.
19
13
DB5
Vee
20
12
DB6
11
DB7
cs
RD
2
10
DGND
WR
3
9
VREr
TUH/8557-2
Top View
N.C.
(N.C.-No Connection)
INTR V1N(+) V1N(-) AGND
TLlH/8557-3
Top View
3-158
Absolute Maximum Ratings (Notes 1 & 2)
Lead Temp. (Soldering, 10 seconds)
Dual-In-Line Package (Plastic)
Dual-In-Line Package (Ceramic)
Molded Chip Carrier Package
Vapor Phase (60 seconds)
Infrared (15 seconds)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
6.5V
Supply Voltage (Vee>
Voltage
Logic Control Inputs
At Other Inputs and Outputs
-0.3V to Vee+0.3V
-0.3V to Vee+0.3V
- 65·C to + 150·C
Storage Temperature
Package Dissipation at T A = 25·C
BOOV
Operating Conditions (Notes 1 and 2)
±20mA
Input Current Per Package (Note 3)
215·C
220"C
ESD Susceptibility (Note 10)
±5mA
Input Current Per Pin (Note 3)
260·C
300"C
B75mW
Supply Voltage (Vee>
4.5 Voe to 6.0 Voe
Temperature Range
ADCOB41 BCN, ADCOB41 CCN
ADCOB41 BCJ, ADCOB41 CCJ,
ADCOB41 BCV, ADCOB41 CCV
ADCOB41 BJ, ADCOB41 CJ
TMINS;TAS;TMAX
O·C S; T AS; 70"C
- 40·C S; TAS; B5·C
-55·CS;TAS; 125·C
Electrical Characteristics
The following specifications apply for Vee = 5 Voe unless otherwise specified.
Boldface limits apply from T MIN to T MAX; all other limits T A = Tj = 25·C.
ADC0841 BJ, ADC0841 BCJ
ADC0841CJ, ADC0841CCJ
Parameter
Conditions
Typ
(Note 6)
Tested
Limit
(Note 7)
Design
Limit
(Note 8)
ADC0841BCN, ADC0841CCN
ADC0841BCV, ADC0841CCV
Typ
(Note 6)
Tested
Limit
(Note 7)
Design
Limit
(Note 8)
±%
±%
±1
±1
Units
CONVERTER AND MULTIPLEXER CHARACTERISTICS
Maximum Total
Unadjusted Error
ADCOB41 BCN, BCV
ADCOB41BJ, BCJ
ADCOB41CCN, CCV
ADCOB41 CJ, CCJ
VREF=5.00Voe
(Note 4)
±%
±1
LSB
LSB
LSB
LSB
Minimum Reference
Input Resistance
2.4
1.1
2.4
1.2
1.1
k!l
Maximum Reference
Input Resistance
2.4
5.9
2.4
5.4
5.9
k!l
Maximum Common-Mode
Input Voltage
(Note 5)
Vee+ O•05
Vee + 0.05
Vee + O.OS
V
Minimum Common-Mode
Input Voltage
(Note 5)
GND-O.OS
GND-O.05
GND-O.OS
V
DC Common-Mode Error
Differential Mode
± 1f1s
±y..
±1f1s
±'/4
±y..
LSB
Power Supply Sensitivity
Vee=5V±5%
± 1f1s
±%
±1f1a
±'Ia
±%
LSB
3-159
•
.,...
..,.
co
o
g
Electrical Characteristics The following specifications apply for Vcc= 5 VOC unless otherwise specified.
Boldface limits apply from TMIN to TMAX; all other limits TA=Tj=25'C. (Continued)
Vee) the maximum input current at anyone pin is ±5 rnA. If the current is limited to ±5 rnA at all the
pins no more than four pins can be in this condhion in order to meet the Input Current Per Package (±20 rnA) specification.
Note 4: Total undajusted error includes offset, full·scale, and linearity.
Note 5: For VIN (-) ;" VIN (+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input, which will forward·conduct for analog
input voltages one diode drop below ground or one diode drop greater than Vee supply. Be careful during testing at low Vee levels (4.5V), as high level analog
inputs (5V) can cause this input diode to conduct, especially at elevated temperatures, and cause errors for analog inputs near full·scale. The spec allows 50 mV
forward bias of either diode. This means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV, the output code will be correct. To
achieve an absolute 0 Voe to 5 Voe Input voltage range will therefore require a minimum supply voltage of 4.950 Voe over temperature variations, initial tolerance
and loading.
Note 6: Typicals are at 25"C and represent most likely parametric norm.
Note 7: Tested limits are guaranteed to National's AOQl (Average OutgOing Quality level).
Note 8: Design limits are guaranteed but not 100% production tested. These limits are not used to calculate outgoing qualhy levels.
Note 9: The temperature coefficient is 0.3%I'C.
Note 10: Human body model, 100 pF discharged through 1.5 kG resistor.
Timing Diagram
cs\
Wi
-
H
I
r
\
&I
~~
\
II
iiii
)
- -!WI
INTH _____J
DBD-DB7 - - - - - -
l
tc
---
{~
II
.
tH11+-
'l
NOTE I
tIH,tOH+
--------------..,r-!!!I:!!~------ H
tACC-
OBD-OB7
)--
I-TUH/8557-9
Note I: Read strobe must occur at least 600 ns after the assertion of interrupt to guarantee reset of INTR.
3-161
....
'0:1'
co
8c
Typical Performance Characteristics
c(
Logic Input Threshold
, , Voltage vs Supply Voltage
~
1.1
-H"C ::>TA~ .121"C
w
!!:
1.1
;
1.1
i
I
-
Ycc,:,5Y
1 1.5
'"
:=
=
1.•
IB
~
ii1
'"
1.4
1.3
UI
4.n
I..
1.21
oL-L-L-JL......L.....JL.....JL......L.....I
-15 -50 -25 0 25 50 75 IUD 125
UO
TEMPEllATURE ("CI
Vcc - sumY VOLTAGE 1Vocl
Linearity Error vs VREF
1.0
!
i
Power S~pply Current vs
Temperature
Output Current vs
Temperature
10
...J
Vcc~1V
TA=2rC
(ZERO AIIO FULL-SCAU-
AllJUS1ED1
I
-
o
30
Iez
20
8
•
Z
3
40
i!z
~
\..
0.5
r-- r--
-75-50-25 0 25 50 75 IUD 125
TEMPEllATURE ("CI
Conversion Time vs
Temperature
U
¥lIEF (VI
Vcc=5
,,"
,
i'
",
~
r-
10
o
.4
-
-
o
50
TA=25"C
50
....
~
Conversion Time vs VSUPPLY
I
0.5
i"""
4.75
5
5.25
SUPPlY VOLTAGE IVI
5.1
o
-75-50 -25 0 25 50 75 IUD 125
TEMPERATURE ("CI
TUH/8557-4
Unadjusted Offset Error vs
VREF Voltage
14
!
i
i
TRI-STATE Test Circuits and Waveforms
"""TTTTmr-r-nnlm
12
Vce
10
8
4
I-H~H-++
o
0.01
0.1
1.0
VIEF (VI
TL/H/8557 -5
TL/H/8557 -22
tOH. CL = 10 pF
tOH
Vee
Vee
Vee
DATA : : :
OUTPUTS
GND
~~lH
~
OH
Vee
DATA
.
~
---
OUTPUTS
GND _ _ _ _ _ _ _c:=
10%
VOL
TUH/8557-6
TL/H/8557 -8
I, = 20n8
TL/H/8557 -7
3-162
1,= 20 no
."
C
~
VREF AGND
90
Vee
()
08
0'
~
e!.
m
0'
()
START
LADDER AND DECODER
FIF
DAC
'"c
6
V1N(+) O~'--+---.
iii'
ce
~
9-BIT
SHIFT REGISTER
7
V1N(-) 0
D)
3
•
~
ONE SHOT
m
'"
!
TRI-STATE
OUTPUT LATCHES
XFER 141--------4
....
TRI H!4---,
i i i "1 "=OUTPUT
ENABLE
1-
600nS
DELAY
LSB
MSB
11 12 13 14 15 16 17 18
DB7 DB6 DB5 DB4 DB3 DB2 OBI DBO
DIGITAL OUTPUTS
~t800av
II
..8
~
~
r------------------------------------------------------------------------------------------,
Functional Description
For a 60 Hz common-mode Signal to generate a % LSB
error (::::: 5 mV) with the converter running at 40 ,...S, its peak
value would have to be 5.43V. This large a common-mode
signal is much greater than that generally found in a well
designed data acquisition system.
A conversion is initiated via the CS and WR lines. If the data
from a previous conversion is not read, the INTR line will be
low. The falling edge of WR will reset the INTR line high and
ready the AID for a conversion cycle. The rising edge of WR
starts a conversion. After the conversion cycle (tc ~ 60
,...sec), which is set by the internal clock frequency, the digital data is transferred to the output latch and the INTR is
asserted low. Taking CS and RD low resets INTR output
high and transfers the conversion result on the output data
lines (DBO-DB7).
2.2 Input Current
Due to the sampling nature of the analog inputs, short duration spikes of current enter the U +" input and exit the U - "
input at the clock edges during the actual conversion. These
currents decay rapidly and do not cause errors as the internal comparator is strobed at the end of a clock period. Bypass capaCitors at the inputs will average these currents
and cause an effective DC current to flow through the output resistance of the analog signal source. Bypass capacitors should not be used if the source resistance is greater
than 1 kG. An op amp RC active low pass filter can provide
both impedance buffering and noise filtering should a high
impedance Signal source be required.
Applications Information
1.0 REFERENCE CONSIDERATIONS
The voltage applied to the reference input of this converter
defines the voltage span of the analog input (the difference
between VIf~(MAX) and VIN(MIN» over which the 256 possible output codes apply. The device can be used in either
ratiometric applications or in systems requiring absolute accuracy. The reference pin must be connected to a voltage
source capable of driving the minimum reference input resistance of 1.1 kG. This pin is the top of a resistor divider
string used for the successive approximation conversion.
3.0 OPTIONAL ADJUSTMENTS
3.1 Zero Error
The zero of the AID does not require adjustment. If the
minimum analog input voltage value, VIN(MIN), is not ground,
a zero offset can be done. The converter can be made to
output 0000 0000 digital code for this minimum input voltage
by biasing the VIN· (-) input at this VIN(MIN) value.
The zero error of the AID converter relates to the location
of the first riser of the transfer function and can be measured by grounding the V- input and applying a small magnitude positive voltage to the V+ input. Zero error is the
difference between actual DC input voltage which is necessary to just cause an output digital code transition from 0000
0000 to 0000 0001 and the ideal Yz LSB value (Yz LSB = 9.8
mV for VREF= 5.000 VDcl.
In a ratiometric system (Figure 1a), the analog input voltage
is proportional to the voltage used for the AID reference.
This voltage is typically the system power supply, so the
VREF pin can be tied to Vee. This technique relaxes the
stability requirements of the system reference as the analog
input and AID reference move together maintaining the
same output code for a given input condition.
For absolute accuracy (Figure 1b), where the analog input
varies between very specific voltage limits, the reference pin
can be biased with a time and temperature stable voltage
source. The LM385 and LM336 reference diodes are good
low current devices to use with this converter.
The maximum value of the reference is limited to the Vcc
supply voltage. The minimum value, however, can be quite
small (see Typical Performance Characteristics) to allow direct conversions of transducer outputs providing less than a
5V output span. Particular care must be taken with regard to
noise pickup, circuit layout and system error voltage sources when operating with a reduced span due to the increased sensitivity of the converter (1 LSB equals
VREF/256).
3.2 Full-Scale
The full-scale adjustment can be made by applying a differential input voltage which is 1 Yz LSB down from the desired
analog full-scale voltage range and then adjusting the magnitude of the VREF input for a digital output code changing
from 11111110 to 11111111.
3.3 Adjusting for an Arbitrary Analog Input Voltage
Range
If the analog zero voltage of the AID is shifted away from
ground (for example, to accommodate an analog input signal which does not go to ground), this new zero reference
should be properly adjusted first. A voltage which equals
this desired zero reference plus Yz LSB (where the LSB is
calculated for the desired analog span, 1 LSB = analog
span/256) is applied to the U +" input (VIN( +» and the zero
reference voltage at the U_" input (VIN(-»should then be
adjusted to just obtain the OOHEX to 01 HEX code transition.
2.0 THE ANALOG INPUTS
2.1 Analog Differential Voltage Inputs and CommonMode Rejection
The differential inputs of this converter actually reduce the
effects of common-mode input noise, a Signal common to
both selected +" and
inputs for a conversion (60 Hz
is most typical). The time interval between sampling the
U +" input and then the U - " input is Yz of a clock period.
The change in the common-mode voltage during this short
time interval can cause conversion errors. For a sinusoidal
common-mode signal this error is:
U
U -"
VERROR(MAX) = Vpeak (21T fCM) X 0.5 X
(~)
where fCM is the frequency of the common·mode signal,
Vpeak is its peak voltage value and tc is the conversion
time.
3-164
Applications Information
»
c
oc
(Continued)
CD
5V
....
~
5V
?
Vee
AOCOB41
AOCOB41
AGNO
AGNO
1
...L
TLlH/8557 -11
TL/H/8557-12
a) Ratiometric
b) Absolute with a Reduced Span
FIGURE 1. Referencing Examples
The full-scale adjustment should be made [with the proper
VIN (-) voltage applied] by forcing a voltage to the VIN( +)
input which is given by:
VMIN=the low end (the offset zero) of the analog range.
(Both are ground referenced.)
The VREF (or Vecl voltage is then adjusted to provide a
code change from FEHEX to FFHEX. This completes the adjustment procedure.
For an example see the Zero-Shift and Span Adjust circuit
below.
V (+) fs adJ·=V
-1.5 [(VMAX-VMIN)]
IN
MAX
256
where VMAX=the high end of the analog input range and
Zero-Shift and Span Adjust (2V S; VIN S; 5V)
vee
(5 voel
V,N(+I
Vee
+
VIN
~'0"F
'="SETS
•
----,
["""""""7=:-+---'
V'N(-)
1.2k
VOLTAGE
SPAN
Aoe0841
VREF
1
1
........._ _-+-...1
I
LM336·l.5
SETS ZERO
CODE VOLTAGE
(lV)
330
I
_J
lk
'="
ZVoe
ZERO AOJ
l.lk
1
'="
TLlH/8557-13
3-165
,...
oo:r
~
Applications Information
(Continued)
g
c(
Span Adjust OV"V,N,,3V
Vee
15Voe}
V,N!+}
vee
+
v,N
1'10"
ADC0841
lk
V,NH
VRE'
+
1'1,'
-=
lM336·2.5
TL/H/B557 -14
Protecting the Input
High Accuracy Comparator
5V
VCC
(&Voci
Vee
TEST
POINT
Ycc
V1N (+)
ADC0841
vlNH
-15VDC
AOC0841
TL/H/8557-16
DO~allls
TLlH/B557 -15
DO~all
Diodes are 1N914
3-166
if VIN(+»V,N(-)
Os if VIN(+)
6.5V
Voltage
Logic Control Inputs
At Other Inputs and Outputs
-0.3Vto +15V
-0.3V to Vee+0.3V
Input Current at Any Pin (Note 3)
5mA
Package Input Current (Note 3)
20mA
Storage Temperature
CD
260'C
300'C
215'C
220'C
Supply Voltage (VeC>
Temperature Range
ADC0844BCN, ADC0844CCN,
ADC0848BCN, ADC0848CCN
ADC0844BCJ, ADC0844CCJ,
ADC0848BCJ, ADC0848CCJ
ADC0848BCV, ADC0848CCV
ADC0844BJ, ADC0844CJ,
ADC084BBJ, ADC0848CJ
875mW
BOOV
4.5 Voe to 6.0 Voe
TMIN,;;:TA,;;:TMAX
0'C,;;:TA';;:70'C
-40'C';;:TA';;:85'C
-55'C,;;:TA,;;:125'C
Parameter
Conditions
Tested
Limit
(Note 6)
Typ
(Note 5)
ADC0844BCN, ADC0844CCN
ADC0848BCN, ADC0848CCN
ADC0848BCV, ADC0848CCV
Design
Typ
Limit
(Note 5)
(Note 7)
Tested
Limit
(Note 6)
Design
Limit
(Note 7)
±%
±%
±1
±1
Limit
Units
CONVERTER AND MULTIPLEXER CHARACTERISTICS
Maximum Total
VREF=5.00 Voe
Unadjusted Error
(Note 8)
ADC0844BCN, ADC0848BCN, BCV
ADC0844BJ, BCJ, ADCOB48BJ, BCJ
ADC0844CCN, ADC084BCCN, CCV
ADCOB44CJ, CCJ, ADCOB48CJ, CCJ
±%
±1
LSB
LSB
LSB
LSB
Minimum Reference
Input Resistance
2.4
1.1
2.4
1.2
1.1
kO
Maximum Reference
Input Resistance
2.4
5.9
2.4
5.4
5.9
kO
Maximum Common-Mode
Input Voltage
(Note 9)
Vee + 0.05
Vee+ 0.05 Vee+ 0 •05
V
Minimum Common-Mode
Input Voltage
(Note 9)
GND-0.05
GND-0.05 GND-0.05
V
DC Common-Mode Error
Differential Mode
±'116
±%
±'116
±%
±%
LSB
Power Supply Sensitivity
Vee=5V±5%
± '116
±%
± '116
±'Ia
±%
LSB
Off Channel Leakage
Current
(Note 10)
On Channel = 5V,
Off Channel = OV
-1
-0.1
-1
)J-A
1
0.1
1
)J-A
On Channel = OV,
Off Channel = 5V
DIGITAL AND DC CHARACTERISTICS
VIN(l), Logical "1" Input
Voltage (Min)
Vee=5.25V
2.0
2.0
2.0
V
VIN(O), Logical "0" Input
Voltage (Max)
Vee=4.75V
0.8
O.B
0.8
V
IIN(l), Logical "1" Input
Current (Max)
VIN=5.0V
1
)J-A
0.005
3-171
1
0.005
c
o
i
CD
Electrical Characteristics The following specifications apply for Vee = 5 Voe unless otherwise specified.
Boldface limits apply from TMIN to TMAX; all other limits TA = Tj = 25'C.
ADC0844BJ, ADC0844BCJ
ADC0844CJ, ADC0844CCJ
ADC0848BJ, ADC0848BCJ
ADC0848CJ, ADC0848CCJ
"'"'""
»
......
"'"
Operating Conditions (Notes 1 & 2)
- 65'C to + 150'C
Package Dissipation at TA = 25'C
ESD Susceptibility (Note 4)
oo
Lead Temperature (Soldering, 10 seconds)
Dual-In-Line Package (Plastic)
Dual-In-Line Package (Ceramic)
Molded Chip Carrier Package
Vapor Phase (60 seconds)
Infrared (15 seconds)
co
-.:r
!
o
C
Electrical Characteristics The following specifications apply for Vcc = 5 Voc unless otherwise specified.
Boldface limits apply from TMIN to TMAX; all other limits TA = Tj = 25°C. (Continued)
tRI. Maximum Delay from Falling Edge of WR or RD to
Reset of INTR
(Note 11)
200
400
ns
tos. Minimum Data Set·Up Time
(Note 11)
50
100
ns
tOH. Minimum Data Hold Time
(Note 11)
0
50
CIN. Capacitance of Logic Inputs
5
ns
ns
pF
COUTo Capacitance of Logic Outputs
5
pF
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. OC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to the ground pins.
Note 3: When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < V- or VIN >
V+) the absolute value of the current at that pin should be
limited to 5 rnA or less. The 20 rnA package input current limits the number of pins that can exceed the power s~pply boundaries with a 5 rnA current limit to four.
Note 4: Human body model, 100 pF discharged through a 1.5 kO resistor.
Note 5: Typicals are at 2S'C and represent most likely parametric norm.
Note 6: Tested limits are guaranteed to National's AOQL (Average OutgOing Quality Level).
Note 7: Oesign limits are guaranteed by not 100% tested. These limits are not used to calculate outgoing quality levels.
Note 8: Total unadiuSted error includes offset, full·scale, linearity. and mu~iplexer error.
3·172
Note 9: For Y,N (-) ;, Y,N (+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input. which will forward-conduct for analog
input voltages one diode drop below ground or one diode drop greater than Vee supply. Be careful during testing at low Vee levels (4.5V). as high level analog
inputs (5V) can cause this input diode to conduct, especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows 50 mV
forward bias of either diode_ This means that as long as the analog Y,N does not exceed the supply voltage by more than 50 mV. the output code will be correct. To
achieve an absolute 0 Voc to 5 Voe input voltage range will therefore require a minimum supply voltage of 4.950 Voc over temperature variations, initial tolerance
and loading.
Note 10: Off channel leakage current is measured after the channel selection.
>
C
oo
CD
.j:o,
.j:o,
......
>
C
o
o
Note 11: The temperature coefficient is O.30/0/ C.
D
CD
.j:o,
Typical Performance Characteristics
Logic Input Threshold
Voltage vs Supply Voltage
E
'"~
1.1
..
..
m
..
.~
25
1.1
1
i'"
>
9 1.&
00-
.......
.~
,;'
1.4
I I
~De=5v-
.....
~OVJ
10
4.50
4.15
5.25
5.Da
'"
'"
15
3w
Vee~5V
D.5
~
i!!z
:Ii
40
-
z 30
~
..
15
>
z
::l
D
TA-25'C
r- r--
1
2
3
4
5
4.5
~ 20
..
~
z
,
5.25
5.5
Unadjusted Offset Error vs
VREF Voltage
1..0'"
",-'
5
SUPPLY VOLTAGE (V)
Vee=5V
30
4.75
14
40
z
r-
lD
Conversion Time vs
Temperature
;::
'"""
20
¥REF (VI
:Ii
0
-75 -50-25 0 25 50 75 100 125
TEMPERATURE ('C)
0
0
3w
'"
r-
5D
;::
\.
50
......... ....
Conversion Time vs VSUPPLV
6D
TA=25'C
(ZERO AND FULL-SCALEADJUSTEOI
r- ....100.
1
::0
Linearity Error vs VREF
i
15
'"g;
..
~
E 0.5
5
1.0
.
1.5
0
-75-50-250 25 50 75 100 125
TEMPERATURE ('C)
5!0
Vee - SUPPLY VOLTAGE IVuel
~
1
~RCE Voe-2.41v
IS+Vof=fvt
1.3
Vee ",5V
JCC=5 Voc
'"
15
ii
9
2
~
20
::0
1.5
Power Supply Current vs
Temperature
Output Current vs
Temperature
-5Soc ~TA 'S+125°C
~
CD
~N~~:~~IN1~1~~1
12
!.'"
1..0"'''
".
'"
15
..
IU
'"
It
lD
D
-75-50-25 0 25 50 75 10D 125
TEMPERATURE ('CI
Vos=2 mV
TA=25'C
10
--
8
6
4
,
:-
-
2
0
O.Dl
!!
0.1
1.0
5
VREF (V)
TL/H/S016-3
3-173
TRI-STATE Test Circuits and Waveforms
Vee
Vee
DATA : : :
TL/H/501S-4
OUTPUTS
GND
---ir-:-z::::::----
~~IH
~
--------=
TUH/501S-5
,,= 20 ns
toH
vee
tOH. CL = 10 pF
vee
10k
GND
OH
iiIi
Vee
DATA
OUTPUTS
~
-10%
VOL
TL/Ht501S-7
,,=20ns
TL/H/501S-S
Leakage Current Test Circuit
5V
AOC0848
1'-----+-1 CH2 (ON/OFFI
CH3 (ONtOFFI
eH4 (ON tOFFI
eH5 (ONtOFFI'
CH6 (ONtOFFI'
CH7 (ONtOFFI'
CH810NtOFFI'
CHANNEL
VOL1l\GE
SELEC7
'NOT INeWDEO ON AOCD844
3·174
TUH/501S-8
Timing Diagrams
Programming New Channel Configuration and Starting a Conversion
cs\___--JI
,-,
------\~
______J;-
iiii
~----------IC:----------~
D80-D87 _ _ _ _ _ _
MAO-MA4
TLiH/SOI6-9
Note 1: Read strobe must occur at least 600 ns after the assertion of interrupt to guarantee reset of INTR.
Note 2: MA stands for MUX address.
Using the Previously Selected Channel Configuration and Starting a Conversion
''--_--II
Wii
iiii
I+---tc:-:::j--t
1,...--.++----·
\ __
'----'I
-----11
------------{
DBo-DB7
READING THE RESULT
OF THE lAST
CONVERSION
3-175
)--
TLlH/5016-10
ADC0844/ ADC0848
~
CII1
CH2
CH3
CH4
"'C
Vr
"
C
__]C
1D
1--
'IIi
It
LADDER AND DECODER
'IIi
DAC
"
~
oo
~~
CD
01::00
START
CLK
F/F
CD
."
C
f-
::J
a
0'
CHS
CH6
SIGN
SELECT
~ +(-)
CH7
CH8
r--
T
AGND
~
.....
m
::J
L...-
+(-)
A"
~
G
!!.
4
SAR LATCH
, II.L
~
c
MUX
DECDDER
TRI·STATE"
OUTPUT LATCHES
S'
~
CQ
DNE SHOT
3
~
~
m
0'
()
9·81T
SHIFT REGISTER
c;
xmr
-I
'fill
"I" = DUTPUT
ENABLE
.t
r
600n•
DELAY
INTR
MAD
MUX
ADDRESS
LATCH
MAl
MA2
MA3
MA4
MSB,
,LSB
DIGITAL OUTPUTS
~
"
~
TUH/5016-11
:t:O
Functional Description
The ADCOB44 and ADCOB4B contain a 4-channel and Bchannel analog input multiplexer (MUX) respectively. Each
MUX can be configured into one of three modes of operation differential, pseudo-differential, and single ended.
These modes are discussed in the Applications Information
Section. The specific mode is selected by loading the MUX
address latch with the proper address (see Table I and Table II). Inputs to the MUX address latch (MAO-MA4) are
common with data bus lines (DBO-DB4) and are enabled
when the RD line is high. A conversion is initiated via the CS
and WR lines. If the data from a previous conversion is not
read, the INTR line will be low. The falling edge of WR will
reset the INTR line high and ready the AID for a conversion
cycle. The rising edge of WR, with RD high, strobes the data
on the MAO/DBO-MA4/DB4 inputs into the MUX address
latch to select a new input configuration and start a conversion. If the RD line is held low during the entire low period of
WR the previous MUX configuration is retained, and the
data of the previous conversion is the output on lines DBODB7. After the conversion cycle (te ,; 40 }-,s), which is set
by the internal clock frequency, the digital data is trans-
oo
ferred to the output latch and the INTR is asserted low.
Taking CS and RD low resets INTR output high and outputs
the conversion result on the data lines (DBO-DB7).
.......
Applications Information
oo
(XI
~
~
:t:O
1.0 MULTIPLEXER CONFIGURATION
The design of these converters utilizes a sampled-data
comparator structure which allows a differential analog input
to be converted by a successive approximation routine.
(XI
~
(XI
The actual voltage converted is always the difference between an assigned" +" input terminal and a "-" input terminal. The polarity of each input terminal of the pair being
converted indicates which line the converter expects to be
the most positive. If the assigned" +" input is less than the
"-" input the converter responds with an all zeros output
code.
A unique input multiplexing scheme has been utilized to provide multiple analog channels. The input channels can be
software configured into three modes: differential, single-
TABLE I. ADC0844 MUX ADDRESSING
MUXAddress
CS
MA3
MA2
MA1
MAO
X
X
X
X
L
L
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
H
H
H
H
H
H
X
X
X
CH1
CH2
+
-
-
+
+
U
H
H
H
H
U
H
H
H
+
L
L
L
L
X
L
U
L
L
L
L
L
L
L
L
L
L
L
H
L
L
Channel#
RD
H
H
H
H
L
H
H
WR
L
H
U
CH3
CH4
+
+
-
AGND
Differential
-
+
+
-
PseudoDifferential
-
+
L
Single-Ended
-
+
+
MUX
Mode
-
Previous Channel Configuration
X=don't care
4 Single-Ended
CH1CH2CH3CH4 ...,.--
r
(+1
(+1
(+1
(+)
2 Differential
CHI, CH2 {
ADCD844
CH3,CH4{
AGND(-)
=
=
ADC0844
+(-)
-(+1
TLiH/SOI6-12
TL/H/S016-13
3 Pseudo-Differential
CH1- (+1
CH2- 1+1
CH3- (+1
•
+(-1
-(+1
Combined
--
ADC0844
CH1,CH2{-
+
CH3 CH4-
+
r
CH4- (-I
ADC0844
+
AGND(-I
TL/H/S016-14
TL/H/SOI6-1S
FIGURE 1. Analog Input Multiplexer Options
3-177
co
'<:I'
co
o
Applications Information
C
ended, or pseudo-differential. Figure 1 shows the three
modes using the 4-channel MUX ADC0844. The eight inputs
of the ADC0848 can also be configured in any of the three
modes. In the differential mode, the ADC0844 channel inputs are grouped in pairs, CHI with CH2 and CH3 with CH4.
The polarity assignment of each channel in the pair is interchangeable. The single-ended mode has CH1-CH4 assigned as the positive input with the negative input being the
analog ground (AGND) of the device. Finally, in the pseudodifferential mode CH1-CH3 are positive inputs referenced
to CH4 which is now a pseudo-ground. This pseudo-ground
input can be set to any potential within the input commonmode range of the converter. The analog signal conditioning
required in transducer-based data acquisition systems is
significantly simplified with this type of input flexibility. One
converter package can now handle ground referenced inputs and true differential inputs as well as signals with some
arbitrary reference voltage.
o
--I VIN!+)
Vee t-.....--------------.,
VIN
ADC0848
lk
VREFt--4~(
-..tl----+
LM336-2.5
Tl/H/5016-20
Protecting the Input
Vee
(5 VDe>
II
TUH/5016-21
Diodes are lN914
3-181
G)
'0:1'
G)
8
c
r------------------------------------------------------------------------------------------,
Applications Information (Continued)
cr:
High Accuracy Comparators
~
5V
g
Vee
G)
C)
cr:
SYSTEM
TEST
POINTS
TL/H/5016-22
00=8111. HV,N(+»V,N(-)
00=8110. HV,N(+)7.:
~
~
~
?
-~
CH2
OB6
CH3
OB5
CH4
CH5
CH6
MA4/0B4
D.U.T.
MA3/DB3
CH7
CHS
MA2/0S2
AGNO
MA1/0Bl
MAO/OBO
OGNO
____r)
fSWii
~
23
11
(9)13
(11114
4
(12)15
7
(13116
S
(14)17
13
(1511S
14
(16)19
17
(17) 20
IS
iiii IHTR
(19)
22
to
.fll
OUT
3 DIS
01
VREF
OB7
""
i;
C
oo
5V
01
02
02
03
03
04
04
MM74C374
D5
05
06
06
07
07
OS
OS
(1)~e14
1
21
"'U..
2
NSL5027
(S Pli
CO
t
""
CO
6
~
[:1
.:.:
9
.:.~
5
f
12
J!
~
15
16
~'
.:.:..
19
""n 7
A
1/6
1/6
1.2k
(S Pl)
Vee
11
"'U..
,,'7
5V
11 9 7 5 3
25k
~I,~' n
DlS2
IN5
IN4
5.1k
5.1k
5.1k
12
MA4_
10
M!.,.
u0-
MM80C95
1/6
MM74C14 ""
5.1k
05 04 03 02 01
r
=r200PF
5.1k
IN3
7
1
0151
IN2
INI
MAl
6
u-
4
M!!.,.
2
MA!,.
0V'"
,,'7
TUH/5016-25
Note: OUT pin numbers in parentheses are for AOC0844, others are for AOC0848.
Start a Conversion without Updating the Channel Configuration
•
~>-----------------~~
~>-----------,-~
~
AOC084S
~----I-----t-IRU
TLlH/5016-26
CS:.WR will update the channel configuration and start a conversion.
CS:eRD will read the conversion data and start a new conversion without updating the channel configuration.
Waiting for the end of this conversion is not necessary. A CS.WR can immediately follow the CSoRO.
3-183
CD
~
CD
0
0
Applications Information (Continued)
Q
ADC0844-INS8039 Interface
CC
.....
5V
~
~
5V
CD
0
0
40
Q
20
Vee
CC
Vee
OBO
DBI
DB2
DB3
DB4
INSBD39
DB5
DB6
, DB7
iiiii
iiii
12
17
13
16
14
15
15
14
16
13
17
12
18
11
19
10
27
DB1/MAl
DB2IMAZ
DB3/MA3
OB4
DB5
ADC0844
DB6
DB7
19
PIO
Pll
DBO/MAO
18
iiiii
iiii
cs
iiifii
(+)CH3
(-)CH4
TUH/5016-27
0000
0410
0010
B9FF
0012
0014
0016
B820
89FF
2300
0018
001A
1450
2302
001C
001D
18
1450
SAMPLE PROGRAM FOR ADC0844-INS8039 INTERFACE
CONVERTING TWO RATIOMETRIC, DIFFERENTIAL SIGNALS
ORG
OH
JMP
BEGIN
;START PROGRAM AT ADDR 10
;MAIN PROGRAM
ORG
10H
Rl,#OFFH
BEGIN:
MOV
;LOAD Rl WITH A UNUSED ADDR
;LOCATION
MOV
RO,#20H
;A/D DATA ADDRESS
Pl,#OFFH
;SET PORT 1 OUTPUTS HIGH
ORL
MOV
A,OOH
;LOAD THE ACC WITH AID MUX DATA
;CHl AND CH2 DIFFERENTIAL
CALL
CONY
;CALL THE CONVERSION SUBROUTINE
A,#02H
MOV
;LOAD THE ACC WITH AID MUX DATA
;CH3 AND CH4 DIFFERENTIAL
RO
;INCREMENTTHE AID DATA ADDRESS
INC
CALL
CONY
;CALL THE CONVERSION SUBROUTINE
;CONTINUE MAIN PROGRAM
;CONVERSION SUBROUTINE
;ENTRY:ACC-AID MUX DATA
;EXIT: ACC-CONVERTED DATA
0050
0052
0053
0054
0056
0057
0059
005A
99 FE
91
09
3253
81
8901
AO
83
CONY:
LOOP:
ORG
ANL
MOVX
IN
JBl
MOVX
ORL
MOV
RET
50H
Pl,#OFEH
@Rl,A
A,Pl
LOOP
A,@Rl
Pl,&OlH
@RO,A
3-184
;CHIP SELECT THE AID
;LOAD AID MUX & START CONVERSION
;INPUT INTR STATE
;IF INTR = 1 GOTO LOOP
;IF INTR = 0 INPUT AID DATA
;CLEAR THE AID CHIP SELECT
;STORE THE AID DATA
;RETURN TO MAIN PROGRAM
----------------,~
Applications Information
c
(")
(Continued)
o
CD
.,..
.,..
......
I/O Interface to NSC800
Vcc
5V
5V
VREF
5V
~
ADCD848
c(")
~
AO/D8D
::~:8:~
~ADO
::
MA4/g::
CH4( +)
DB6
...------tCH51+)
DB7
:g;
AD6
AD7
CHI( +)
L----ICH2(+) MA3/D83
o
.,..
CD
CD
AD3
t_~~~~::::::~CH3(+)
r----ICH61+)
CH71+)
AD11
AD12
AD13
ADI4
AD15
!DIM
TUH/5016-28
SAMPLE PROGRAM FOR ADC0848-NSC800 INTERFACE
0008
OOOF
001F
SCOO
OOOA'
OOOC'
OOOF'
0012'
OS090AOB
OCODOEOF
OE1F
0616
210000'
1100SC
EDAS
0014'
EB
0015'
0017'
001S'
001B'
SEOF
3D
C2001S'
EDA2
001D'
001E'
EB
C2000E'
DODO'
0004'
O~~S'
NCONV
DEL
CS
ADDTA
EQU
EQU
EQU
EQU
16
15
1FH
DOSCH
MUXDTA:
DB
DB
LD
LD
LD
LD
OUTI
OSH,09H,OAH,OBH
OCH,ODH,OEH,OFH
C,CS
B,NCONV
HL,MUXDTA
DE,ADDTA
EX
DE,HL
LD
DEC
JP
INI
A,DEL
A
NZ,WAIT
EX
JP
DE,HL
NZ,STCONV
START:
STCONV:
WAIT:
;DELAY 50 ",sec CONVERSION
;THE BOARD ADDRESS
;START OF RAM FOR AID
;DATA
;MUXDATA
;LOAD AID'S MUX DATA
;AND START A CONVERSION
;HL= RAM ADDRESS FOR THE
;AlDDATA
;WAIT 50 ",sec FOR THE
;CONVERSION TO FINISH
;STORE THE AID'S DATA
;CONVERTED ALL INPUTS?
;IF NOT GOTO STCONV
END
Note: This routine sequentially programs the MUX data latch in the signal-ended mode. For CHI-CHB a conversion is started, then a 50 p.s wait for the AID to
completa a conversion and the data is stored at address ADDTA for CHI. ADDTA + I for CH2, etc.
3-185
8~
c
...CD~
8c
Ordering Information
Temperature
Range
Total Unadjusted Error
±% LSB
±1 LSB
ADC0844BCN
ADC0844CCN
O·Cto +70·C
C
n
o
~National
CD
U1
~ Semiconductor
N
.......
:J>
ADC0852! ADC0854
Multiplexed Comparator with 8-Bit Reference Divider
C
n
o
CD
U1
.j::Io
General Description
The ADC0852 and ADC0854 are CMOS devices that combine a versatile analog input multiplexer, voltage comparator, and an 8-bit DAC which provides the comparator's
threshold voltage (VTH). The comparator provides a "1-bit"
output as a result of a comparison between the analog input
and the DAC's output. This allows for easy implementation
of set-point, on-off or "bang-bang" control systems with
several advantages over previous devices.
once each clock cycle up to a maximum clock rate of
400 kHz.
Features
•
•
•
•
•
II
The ADC0854 has a 4 input multiplexer that can be software
configured for single ended, pseudo-differential, and full-differential modes of operation. In addition the DAC's reference input is brought out to allow for reduction of the span.
The ADC0852 has a two input multiplexer that can be configured as 2 single-ended or 1 differential input pair. The
DAC reference input is internally tied to Vee.
The multiplexer and 8-bit DAC are programmed via a serial
data input word. Once programmed the output is updated
2 or 4 channel multiplexer
Differential or Single-ended input, software controlled
Serial digital data interface
256 programmable reference voltage levels
Continuous comparison after programming
Fixed, ratiometric, or reduced span reference capability
(ADC 0854)
Key Specifications
• Accuracy, ± % LSB or ± 1 LSB of Reference (0.2%)
• Single 5V power supply
• Low Power, 15 mW
ClK
VREF-----I
>-----00
AGNO-----...1
-V+
0 1 - -.....- -..........
-Vee
cs-
-OGNO
CHO
CHI
CH2
CH3
COM
TL/H/5521-1
FIGURE 1. ADC0854 Simplified Block Diagram (ADC0852 has 2 input channels,
COM tied to GND, VREF tied to Vee, V + omitted, and one GND connection)
•
2 Channel and 4 Channel Pin Out
ADC0852 2-CHANNEL MUX
Dual-In-Line Package
C§
CHO
2
CHI
3
GND (COM)
4
AOC0852
ADC0854 4-CHANNEL MUX
Dual-In-Line Package
8
Vee (VREF)
C§
1
14
7
CLK
CHO
2
13
v+
DO
CHI
3
12
01
01
CH2
4
11
CLK
CH3
5
10
DO
COM
6
DGNO
7
5
TL/H/5521-10
Top View
AOC0854
8
Vee
VREF
AGNO
AGND and COM internally connected to GND
VREF internally connected to Vee
TL/H/5521-11
Top View
Order Number ADC0852
See NS Package Number J08A or N08E
Order Number ADC0854
See NS Package Number J14A or N14A
3-187
'0:1'
it)
co
c
Absolute Maximum Ratings (Notes 1 and 2)
C
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Current into V+ (Note 3)
15mA
(,)
.
Note 13: See text, section 1.2.
Note 14: Human body model, 100 pF discharged through a 1.5 kG resistor.
Note 15: Because the reference ladder of the ADC0852 is internally connected to Vee. ladder resistance cannot be directly tested for the ADC0852. Ladder
current is included in the ADC0852's supply current specification.
3-190
~
C
g
Typical Performance Characteristics
00
CII
Internal DAC Linearity
Error vs VREF Voltage
1.5
0.50
Vcc =5V
(CLK = 250 kH,
TA=25'C
1.25
...iii"~ 1.0
Internal DAC Linearity
Error vs Temperature
"
'"
'"
'"~
'"
~
'" 0.75
!5
>-
0.25
I-
;;:
~ 0.5
z
:::; 0.25
::5
z
"-
60 Comparator Error vs fCLK
t'-...
-
!
.
'"
'"
ffi
VREF=5.0V
:::;
VRE~=5V
50
~
~
co
N
o
Vec=5V
00
125'C
CII
.a:o.
40
30
20
-25'C
10
(CLKf50 kr
V
~
25'C
0
0
25
1
2
3
VREF (Vue)
4
C
§.
t-
i
t-
~
6
15
Output Current vs
Temperature
~VDC=iV
!Ii;
4
It
3
......
...
'"
'"
If
Ii
ISOURCE Vue = 2.4V
IE
5
(SINK Vue = 0.4V
0
-100 -50
0
50
100
TEMPERATURE I'C)
1.5
l-
.I!!
.
'"
:::0
1.0 Vee=5V
I
1""'-,
.... r--~_
~
G:
:::0
_t~;:~,
reCi4.5V
0.5
leLK = J50
~='r
0
150
JH'
I
0
-75-50-25 0 25 50 75 100 125
TEMPERATURE ('C)
:::0
1.5
-
r-- ....
~
~
it
"~
-50-25 0
600
vlJ.ote
I!!
\
'"
1.0
25 50 75 100 125
-50 -25 0 25 50 75 100 125
TEMPERATURE ('C)
TEMPERATURE ('C)
Icc. Power Supply
Current vs. fCLK. ADC0854*
1.5
------
...
'"'"
1\
150
2.0
So
Iill
\,
1
100 200 300 400 500
ICLK (kH,)
IREF. Reference
Current vs. Temp. ADC0854
c
2
ICC. Power Supply Current
vs. Temperature. ADC0854*
C
oS
100
5_~
ISOURCEVUC~
ID
50
Comparator Offset vs
Temperature
j
"
0
TEMPERATURE ('C)
Vcc=5V
20
0
0
-100 -50
5
C
oS
vee=15v
@2~C
I-
ill 1.0
.
'"
'"
~~
:::0
~
...G:
:::0
0.5
'"
II:
~
0
0
100
200
300
400
500
IeLK(kH,)
TL/H/5521-2
'For ADCOB52 add 'REF
3·191
~o
Timing Diagrams
..
Data Input Timing
Data Output Timing
ClK
DATA OUT (DO)
TlIH/5521-3
. and Waveforms
TRI-STATE Test Circuits
.
Vee
I
...
CI
~.....-
.....-
DATA
OUTPUT
00
~
'.,.
DATA
OUTPUT
CL
Vee
T
90%
50%
10%
GND~OH
.
vee
00
10
VOL
.
Leakag e Test Circuit
TlIH/5521-6
3-192
%
Tl/H/5521-5
CS..!
CLK"'il
DI...!!
NOTE 1
MUX
ADDRESS
Vee
l
CHO 2
CHl 3
NOTE 1
~I
JCH2
cs
4
• CH3 5
~.
EDCI
CD
.,.
'"
Jl
PARALLEL
XFRTD
COM
Vee
NOTE1{
MUX
ANALOG
"S I-f-'"
~ ''''Fr:~~L
(MUX CODE 0, 0, 0)
TO INTERNAL
7V ZENER
V+ 13
-
LATCH
I
",·'1
6
I
~I
111
BV=30V
12
':'
7
DGND].,
VREF
9,.'Woo
LADDER AND DECODER
,
':' AGND
Note 1: For ADC0852; 01 is input directly to the 0 input of
ODD/SIGN, select: is forced to a "1", AGNOand COM are internally tied to DGND. only Vee is brought out, VREF is internally
lied to Vee, only CH2 and CH3 are brought out.
INPUT PROTECTION-ALL LOGIC INPUTS
TL/H/5521-7
FIGURE 2. Detailed Block Diagram
11S8000"I~S8000"
iii
ADC0852! ADC0854
»
c
o
Functional Description
In the first cycle (Figure 4a), one input switch and the inverter's feedback switch are closed. In this interval, the input
capacitor (C) is charged to the connected input (V1) less the
inverter's bias voltage (Va, approx. 1.2 volts). In the second
cycle (Figure 4b) these two switches are opened and the
other (V2) input's switch is closed. The input capacitor now
subtracts its stored voltage from the second input and the
difference is amplified by the inverter's open loop gain. The
1. 1 The Sampled-data Comparator
The ADCOB52 and ADCOB54 utilize a sampled-data comparator structure to compare the analog difference between
a selected "+" and "-" input to an B-bit programmable
threshold.
This comparator consists of a CMOS inverter with a capacltively coupled input (Figure 4). Analog switches connect the
two comparator inputs to the input capacitor and also connect the inverter's input and output. This device in effect
now has one differential input pair. A comparison requires
two cycles, one for zeroing the comparator and another for
making the comparison.
C
inverter input (Va') becomes Va - (V1 - V2) C + Cs and
the output will go high or low depending on the sign of Va'Va·
FIGURE 4. Sampled-Data Comparator
Vl-oJ'~.
V2-o
•
•
•
•
JCS
Vo = Va
Von C = VI-Va
Cs = Stray Input Node Cap.
Va = Inverter Input Bias Voltage
TLlH/5521-B
FIGURE 4a. Zeroing Phase
Vl--P)C~~
~o-Lva'
V2-o
C
• Va,-Va = (V2- V l) C+Cs
va'
ICS
-A
• Vo = - - [CV2- CV1]
C+ Cs
• VOisdependentonV2-VI
TL/H/5521-9
FIGURE 4b. Compare Phase
A
VtNI+)Vl~Cl
A
VtNI-)V2~J1
V3::)C2
Vo ""
Va
• Comp,;..alor Reads VTH from Internal DAC Differentially
B'
*Vnt(+)
ICI (V2 - VI) + C2 (V4 - Vs)]
-A
[aQCl + a QC2]
Cl+ C2+ CS
A
*Vntl-)
-A
Cl+ C2+ CS
V4~
TLlH/5521-14
FIGURE 4c. Multiple Differential Inputs
3-195
:i
U1
~C
oo
CO
U1
.j;Io
~
II)
IX)
r---------------------------------------------------------------------------------,
o
g
c(
......
N
~.
g
c(
Functional Description (Continued)
In actual practice, the devices used in the AOC0852/4 are a
Simple but important expansion of the basic comparator described above. As shown in Figure 4c, multiple differential
comparisons can be made. In this circuit, the feedback
switch and one input switch on each capacitor (A switches)
are closed in the first cycle. Then the other input on each
capacitor is connected while all of the first switches are
opened. The change in voltage at the inverter's input, as a
result of the change in charge on each input capacitor (C1,
C2), will now depend on both input signal differences.
vide multiple analog channels with software-configurable
single-ended, differential, or pseudo-differential operation.
The analog signal conditioning required in transducer-input
and other types of data acquisition systems is significantly
simplified with this type of input flexibility. One device package can now handle ground referenced inputs as well as
signals with some arbitrary reference Voltage.
On the AOC0854, the "common" pin (pin 6) is used as the
"-" input for all channels in single-ended mode. Since this
input need not be at analog ground, it can be used as the
common line for pseudo-differential operation. It may be tied
to a reference potential that is common to all inputs and
within the input range of the comparator. This feature is
especially useful in single-supply applications where the analog circuitry is biased to a potential other than ground.
1.2 Input Sampling and Response TIme
The input phases of the comparator relate to the device
clock (ClK) as shown in Figure 5. Because the comparator
is a sampling device, its response characteristics are somewhat different from those of linear comparators. The VIN( + )
input is sampled first (elK high) followed by VIN( -) (ClK
low). The output responds to those inputs, one half cycle
later, on ClK's falling edge.
The comparator's response time to an input step is dependent on the step's phase relation to the ClK signal. If an
input step occurs too late to influence the most imminent
comparator deCision, one more ClK cycle will pass before
the output is correct. In effect, the response time for the
VIN( +) input has a minimum of 1 ClK cycle + 1 ,.,.S and a
maximum of 2 ClK cycles + 1 ,.,.S. The VIN( -) input's delay
will range from 1/2 ClK cycle + 1 ,.,.S to 1.5 ClK cycles +
1 ,.,.S since it is sampled after VIN( + ).
A particular input configuration is assigned during the MUX
addressing sequence which occurs prior to the start of a
comparison. The MUX address selects which of the analog
channels is to be enabled, what the input mode will be, and
the input channel polarity. One limitation is that differential
inputs are restricted to adjacent channel pairs. For example,
channel 0 and 1 may be selected as a differential pair but
they cannot act differentially with any other channel.
The channel and polarity selection is done serially via the 01
input. A complete listing of the input configurations and corresponding MUX addresses for the AOC0852 and AOC0854
is shown in tables I and II. Figure 6 illustrates the analog
connections for the various input options.
The sampled inputs also affect the device's response to
pulsed signals. As shown in the shaded areas in Figure 5,
pulses that rise and/ or fall near the latter part of a ClK halfcycle may be ignored.
The analog input voltage for each channel can range from
50 mV below ground to 50 mV above Vee (typically 5V)
without degrading accuracy.
1.3 Input Multiplexer
A unique input multiplexing scheme has been utilized to pro·
A VIHI+)ANOVrHI_) SAMPLED (ZEROING)
B VINI_I AND VrH( + I SAMPLED
VINI + I AND VrHI-1 FOR
NEXT COMPARISON
o
OUTPUT UPDATED
BASED ON A AND B
E VIN(_I AND Vnt(+1 FOR
NEXT COMPARISON
F OUTPUT BASED
ONCANDE
CLK
SAMPLING UNCERTAINTY FOR TRANSIENTST
ON VINI +) INPUT DURING THIS TIME
L
SAMPLING UNCERTAINTY FOR TRANSIENTS
ON VIN\-I INPUT DURING THIS TIME
TL/H/5521-13
FIGURE 5. Analog Input Timing
3-196
Functional Description
(Continued)
TABLE I. MUX Addressing: ADC0854
Single·Ended MUX Mode
MUXAddress
TABLE II. MUX Addressing: ADC0852
Single Ended MUX Mode
Channel
SGLI
DIF
0001
SIGN
SELECT
0
1
0
0
+
1
0
1
1
1
0
1
1
1
1
2
MUXAddress
3
COM
+
-
+
+
Channel
SGLI
DIF
0001
SIGN
0
1
0
+
1
1
+
COM is internally tied to A GND
Differential MUX Mode
MUXAddress
Differential MUX Mode
MUXAddress
Channel
SGLI
DIF
0001
SIGN
SELECT
0
1
0
+
-
0
O·
0
0
1
0
1
0
0
1
1
-
2
3
+
-
-
+
Channel
SGLI
DIF
0001
SIGN
0
0
0
1
0
1
+
-
+
+
4 Single-Ended
4 Pseudo-Differential
0-+
0- +
1- +
1-+
2-+
2- +
3- +
3- +
~
1
COM(-}
VBIAS
.J:
-=-
.J:
2 Differential
COM(-}
•
Mixed Mode
{- +
O.ll_
-
+(-}
O.I{=
2.3{=
2-+
-(+}
+(-}
-(+}
3-+
.J!""
VBIAS
-=-
COM (-}
~
FIGURE 6. Analog Input Multiplexer Options for the ADC0854
3·197
TL/H/5521-15
~ r-------------------------------------------------------------~
It)
co
C)
(.)
C
window
Two low outputs --+ input < window
One low and Dna high
--+-
input is within window
3·200
»
c
Typical Applications (Continued)
oo
CO
UI
110V,I,C
5V
N
.....
»
c
HI
oo
CO
UI
4.7k
00 10
~
4.7k
5V 14 Yee
1
CHO
CH1
2
3
COM
5V
2.73V+10rrNI C
Q
lk
2.13V
lMJ35
TEMP
SENSOR
2k
OFFSET
4k
2k
FULL·
SCALE
LM103
3.3V
2k
4k
TLlH/5521-23
FIGURE 14. Serial Input Temperature Controller
Note 1: ADC0854 does not require constant service from computer. Self controlled after one write to 01 if CS remains low.
Note 2: Ul: Solid State Relay, Potter Brumfield #EOM10B22
Note 3: Set Temp via. 01. Range: 0 to 125"C
10V""1---.JtJIIIr-----,
&.8k
DO 10
20k
TLlH/5521-24
FIGURE 15. Load Cell Limit Comparator
• Differential Input elliminates need for instrumentation amplifier
• A total of 4 load cells can be monitored by AOC0854
3-201
~
II)
co
CI
r-----------------------------------------------------------------------------------------,
Typical Applications
(Continued)
(.).
C
Absolute Maximum Ratings (Notes 1 & 2)
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Temperature Range
Supply Voltage (Vccl (Note 3)
ADC1 001 CCJ-1
Range of VCC
-65'C to + 150'C
Package Dissipation at T A = 25'C
O'C,;;TA';; +70'C
ADC1 021 CCJ-1
Voltage at Other Inputs and Outputs -0.3V to (Vcc+0.3V)
4.5 VOC to 6.3 VOC
875mW
Lead Temp. (Soldering. 10 seconds)
300'C
ESD Susceptibility (Note 10)
800V
Converter Characteristics
Converter Specifications: VCC= 5 VOC. VREF/2 = 2.500 VOC. T MIN,;;TA,;;T MAX and fCLK= 410kHz unless otherwise specified.
Parameter
Conditions
Min
Typ
ADC1001C. ADC1021C:
Linearity Error
Zero Error
FUll-Scale Error
Total Ladder Resistance (Note 9)
Input Resistance at Pin 9
Analog Input Voltage Range
(Note 4) V(+) orV(-)
DC Common-Mode Error
Over Analog Input Voltage Range
Power Supply Sensitivity
Vcc=5 Voc±5% Over
Allowed VIN( +) and VIN( -)
Voltage Range (Note 4)
2.2
Max
Units
±1
±2
±2
LSB
LSB
LSB
Vcc+O.05
VOC
KO
4.8
GND-0.05
±%
±%
LSB
LSB
AC Electrical Characteristics
Timing Specifications: Vcc=5 VOC and TA=25'C unless otherwise specified.
Symbol
Tc
fCLK
Parameter
Max
Units
Conversion Time
(Note 5)
fCLK=410 kHz
80
196
90
219
1/fCLK
,...S
Clock Frequency
(Note 8)
100
1260
kHz
40
60
%
4600
conv/s
Conditions
Clock Duty Cycle
Min
Typ
CR
Conversion Rate In Free-Running
Mode
INTR tied to WR with
CS=O Voc. fCLK=410 kHz
tW(WR)L
Width of WR Input (Start Pulse
Width)
CS=O VOC (Note 6)
tACC
Access Time (Delay from
Falling Edge of RD to Output
Data Valid)
CL=100pF
170
300
ns
t1H. tOH
TRI-STATE® Control (Delay
from Rising Edge of RD to
Hi-ZState)
CL =10 pF. RL =10k
(See TRI-STATE Test
Circuits)
125
200
ns
tWI.tRI
Delay from Falling Edge
of WR or RD to Reset of INTR
300
450
ns
t1rs
INTR to 1st Read Set-Up Time
CIN
Input Capacitance of Logic
Control Inputs
5
7.5
pF
COUT
TRI-STATE Output
Capacitance (Data Buffers)
5
7.5
pF
150
550
3-205
o
....
c
c
......
....
l>
ADC1021CCJ
-0.3Vto +18V
Storage Temperature Range
TMIN ,;;TA';;TMAX
-40'C';;TA';; +85'C
ADC1001CCJ
6.5V
Logic Control Inputs
C
(Notes 1 &2)
ns
400
ns
C
o
....
cI\)
....
.,..
C'II
....o
DC Electrical Characteristics
c
The following specifications apply for Vee=5 VDe and TMINS:TAS: TMAX, unless otherwise specified.
Co)
ct
..........o
....o
Co)
c
Symbol
Parameter
Conditions
Min
Typ
Max
Units
15
VDe
0.8
VDe
1
/LADe
CONTROL INPUTS [Note: ClK IN is the input of a Schmitt trigger circuit and is therefore specified separately]
VIN (1)
ct
logical "1" Input Voltage
Vee = 5.25 VDe
2.0
(Except ClK IN)
VIN(O)
logical "0" Input Voltage
Vee = 4.75 VDe
(Except ClK IN)
liN (1)
logical "1" Input Current
0.005
VIN=5VDe
(All Inputs)
liN (0)
logical "0" input Current
VIN=OVDe
-1
-0.005
2.7
3.1
3.5
VDe
1.5
1.8
2.1
VDe
0.6
1.3
2.0
VDe
0.4·
VDe
/LADe
(All Inputs)
CLOCK IN
VT+
ClK IN Positive Going
Threshold Voltage
VT-
ClK IN Negative Going
Threshold Voltage
VH
ClK IN Hysteresis
(VT+)-(Vr-"l
OUTPUTS AND INTR
VOUT(O)
logical "0" Output Voltage
10UT= 1.6 mA, Vee = 4.75 Vbe
VOUT(I)
logical "1" Output Voltage
10= -360 /LA, Vee = 4.75 VDe
2.4
VDe
10= -10 /lA, Vee=4.75 VDe
4.5
VDe
lOUT
TRI-STATE Disabled Output
VOUT=O.4 VDe
0.1
-100
/lADe
leakage (All Data Buffers)
VOUT=5 VDe
0.1
3
/lADe
ISOUReE
VOUT Short to GND, T A = 25°C
4.5
6
mADe
ISINK
VOUT Short to Vee, T A = 25°C
9.0
16
mADe
POWER SUPPLY
Icc
Supply Current (Includes
Ladder Current)
feLK=410 kHz,
VREF/2=NC, TA=25°C
andCS=1
2.5
5.0
mA
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specmed. The separate A GND point should always be wired to the D GND.
Note 3: A zener diode exists, internally, from Vee to GND and has a typical breakdown voltage of 7 Voc.
Note 4: For VIN( -) <: VIN( +) the dig~al output code will be all zeros. Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward
conduct for analog input voltages one diode drop below ground or one diode drop greater than the VCC supply. Be careful, during testing at low Vee levels (4.5V),
as high level analog inputs (5V) can cause this input diode to conduct-especially at elevated temperatures, and cause errors for analog inputs near fullseale. The
spec allows 50 mV forward bias of either diode. This means that as long as the analog VIN does not exceed the supply voltage by mpre than 50 mV, the output
code will be correct. To achieve an absolute a Voc to 5 VDC input voltage range will therefore require a minimum supply voltage of 4.950 Voc over temperature
variations, initial tolerance and loading.
Note 5: With an asynchronous start pulse, up to 8 clock periods may be required before the internal clock phases are proper to start the conversion process. The
start request is internally latched. see Figure 1.
Note 6: The CS input is assumed to bracket the WR strobe input and therefore timing is dependent on the WR pulse width. An arbitrarily wide pulse width will hold
the converter in a reset mode and the start of conversion is initiated by the low to high transition of the WR pulse (see Timing Diagrams).
Note 7: All typical values are for TA ~ 25°C.
Note 8: Accuracy is guaranteed at fCLK~410 kHz. At higher clock frequencies accuracy can degrade.
Note 9: The VREF/2 pin is the center point of a two resistor divider (each resistor is 2.4kll) connected from Vee to ground. Total ladder input resistance is the sum
of \hese two equal resistors.
Note 10: Human body model, 100 pF discharged through a 1.5 kll resistor.
3-206
l>
c
o....
Typical Performance Characteristics
logic Input Threshold
Voltage vs Supply Voltage
~
1.8
r--I-,---.f-_I.-5~ocldA ~+125!c
~
1.7
H-+-+-+--I-t--"H-+7!"+-1
~
1.6
H-t-t-++-i7'fi;'++-HH
1.5
H-+i;'--1.o4-1-+-H-+-++-I
=
>
o
Delay From Falling Edge of
RD to Output Data Valid
vs load Capacitance
7'
500
ClK IN Schmitt Trip levels
vs Supply Voltage
EEEEEEEEEE
~
~
~
=
>
=
~
a:
....
~
~
1.4
9
1.3 L...J'-l....J......J......J.....J-L.....J'-l....J.....J-J
;;;
4.50
4.75
5.00
5.25
....o
o
....
N
2.3 H-+-+-+-+-+-H-+-++-!
i:
I£-I-t-t-++--!-H-t-t--+--l
.,
3.1 H""V,l-T+-t-...J~H::;;;I.--i"q:...+-HH
l>
c
~
:z:
::l
~
I
3.5
....o
......
100
~Ettt:t:t:t:tE
o
5.50
§
200
400
600
BOO
.,
1.9
1.5 L.....J-L.-L..J.....I-J--L....J......J.....J-L.....J
1000
4.50
LOAD CAPACITANCE (pF)
Vcc -SUPPLY VOLTAGE (Voc)
v~ _IH-+-++_-iI--t::;;;l......'1""t-H
4.75
5.00
5.25
5.50
VCC - SUPPLY VOLTAGE (VOC)
Output Current vs
Temperature
Vcc- 5Voc
<'
.§
....
I-+*+-+-+-j-DATA DUTPUTfBUFFERS
I
::'a:i
a:
B
....
":=
I
i'- .I
"
=
ISINK
H++-il- VOUT =0.4 VDC
zL..J......L...J....J..""'::;:":""_":;'::'.J......L-=
-50 -25
0
25
50
75
100 125
TA - AMBIENT TEMPERATURE (OC)
TL/H/5675-2
TRI-STATE Test Circuits and Waveforms
tlH
t1H. CL ~ 10 pF
VCC
VCC
ifii
DATA
OUTPUT
CL.-L
ifii
10k
I
DATA :::
TLlH/5675-4
tOH. CL = 10 pF
--f
-',I':"'"
VCC
10k
vcc
GND ----'
•
~
90%
50%
10%
OH
DATA
OUTPUT
Vcc
DATA
OUTPUTS
CL-":'
-------==
TL/H/5675-3
1!li
iiii
~~IH
"'-
GND
tOH
Vcc
{s90%
'11:0%
OUTPUTS
~
-',f--
~
--10%
VOL
TL/H/5675-6
t,~20
TLlH/5675-5
3-207
ns
•
,...
N
,...
(J
cc(
",...
0
0
,...
0
(J
Timing Diagrams
START
CONVERSION
C
c(
CI
\
I
foI
"BUSY"
+-____+-__-
C
Functional Description
The ADC1001, ADC1021 use an advanced potentiometric
resistive ladder network. The analog inputs, as well as the
taps of this ladder network, are switched into a weighted
capacitor array. The output of this capacitor array is the input to a sampled data comparator. This comparator allows
the successive approximation logic to match the analog difference input voltage [VIN(+)-VIN(-)j to taps on the R
network. The most significant bit is tested first and after 10
comparisons (80 clock cycles) a digital 10-bit binary code
(all "1 "s = full-scale) is transferred to an output latch and
then an interrupt is asserted (INTR makes a high-to-Iow
transition). The device may be operated in the free-running
mode by connecting INTR to the WR inut with CS=O. To
ensure start-up under all possible conditions, an external
WR pulse is required during the first power-up cycle. A conversion in process can be interrupted by issuing a second
start command.
clocked in, which allows the conversion process to continue. If the set signal were to still be present, this reset pulse
would have no effect and the 10-bit shift register would continue to be held in the reset mode. This logic therefore al·
lows for wide CS and WR signals and the converter will start
after at least one of these signals returns high and the internal clocks again provide a reset signal for the start F/F.
o
.....
o
o
.....
......
J>
C
o.....
o
N
.....
After the "1" is clocked through the 1O-bit shift register
(which completes the SAR search) it causes the new digital
word to transfer to the TRI-STATE output latches. When
this XFER signal makes a high-to-Iow transition the one
shot fires, setting the INTR F/F. An inverting buffer then
supplies the INTR output signal.
Note that this SET control of the INTR F/F remains low for
aproximately 400 ns. If the data output is continuously enabled (CS and RD both held low), the INTR output will still
signal the end of the conversion (by a high-to·low transition), because the SET input can control the Q output of
the INTR F/F even though the RESET input is constantly at
a "1" level. This INTR output will therefore stay low for the
duration of the SET signal.
When data is to be read, the combination of both CS and
RD being low will cause the INTR F/F to be reset and the
TRI·STATE output latches will be enabled.
On the high-to-Iow transition of the WR input the internal
SAR latches and the shift register stages are reset. As long
as the CS input and WR input remain low, the AID will remain in a reset state. Conversion will start from 1 to 8 clock
periods after at least one of these inputs makes a low-tohigh transition.
A functional diagram of the AID converter is shown in Figure 1. All of the inputs and outputs are shown and the major
logic control paths are drawn in heavier weight lines.
Zero and Full-Scale Adjustment
Zero error can be adjusted as shown in Figure 2. VIN( +) is
forced to + 2.5 mV (+ '12 LSB) and the potentiometer is
adjusted until the digital output code changes from 00 0000
0000 to 00 0000 0001.
The conversion is initialized by taking CS and WR simultaneously low. This sets the start flip-flop (F IF) and the resulting "1" level resets the 8-bit shift register, resets the Interrupt (INTR) F/F and inputs a "1" to the D flop, F/F1, which
is at the input end of the 10-bit shift register. Internal clock
signals then transfer this "1" to the Q output of F/F1. The
AND gate, Gl, combines this "1" output with a clock signal
to provide a reset signal to the start F/F. If the set signal is
no longer present (either WR or CS is a "1 ") the start F/F is
reset and the 10-bit shift register then can have the "1"
Full-scale is adjusted as shown in Figure 3, with the VREF/2
input. With VIN (+) forced to the desired full-scale voltage
less 1'12 LSBs (VFS -1 '12 LSBs), VREF/2 is adjusted until
the digital output code changes from 11 1111 1110 to 11
11111111.
(Vee) 5V
~
5V
~lk
ADC1001, ADC1021
ADC1001, ADC1021
VREF/2
1.0M
10k :>I!_.....W\r-....-.....jVIN(-)
~
10k
~
~
~
100
'""
~LM336
-
-5V
TL/H/5675-10
TL/H/5675-9
NOTE: VIN( -) should be biased so
that VIN(-)~ -O.05V when potentiometer
wiper is sat at most negative
voltage position.
FIGURE 3. Full-Scale Adjust
FIGURE 2. Zero Adjust Circuit
3-209
•
....
....
o
N
o
Typical Application
5V
C
---....
LADDER
AND
DECODER
START CONVERSION
IF RESET' ''0''
SAR
LATCH
INDTEZ)
VREFl2o---~~--"",*-"
INTR F/F
DAC
VIOUTI
AGND
':"
VCC
V'NI>I o-"-I-.c.2;J-~
~
-11-400ns
AOCIOZI24·PIN
nINOTE~~:::::::::::::~[=:')-____________-;,~~~;,;:-"________________-;;r,~
ft" C
TRI.STATE CONTROL
"I'" OUTPUT ENABLE
Note I: CS shown twice for clarity.
Note 2: SAR ~ Successive Approximation Register.
RESET
TLlH/5675-13
FIGURE 1
3-210
»
c
....o
~National
c
c
~ Semiconductor
U\
........
»
c
ADC10051 ADC1025 10-Bit ILP Compatible AID Converters ....
o
C
N
General Description
U\
The ADC1005 and ADC1025 are CMOS 10-bit successive
approximation AID converters. The 20-pin ADC1005 outputs 10-bit data in a two-byte format for interface with B-bit
microprocessors.
The 24-pin ADC1025 outputs 10 bits in parallel and is intended for 16-bit data buses or stand-alone applications.
Both A-to-Ds have differential inputs to permit rejection of
common-mode signals, allow the analog input range to be
offset, and also to permit the conversion of signals not referred to ground. In addition, the reference voltage can be
adjusted, allowing smaller voltage spans to be measured
with 10-bit resolution.
II Operates ratiometrically or with 5 Voc voltage refer-
ence or analog span adjusted voltage reference
II OV to 5V analog input voltage range with single
5V supply
II On-chip clock generator
II TLLlMOS input/output compatible
II 0.3" standard width 20-pin DIP or 24-pin DIP with 10-
bit parallel output
II Available in 20-pin or 2B-pin molded chip carrier
package
Key Specifications
II Resolution
Features
10 bits
±% LSB and ±1 LSB
50,...s
.. Linearity Error
II Conversion Time
Easy interface to all microprocessors
II Differential analog voltage inputs
II
Connection Diagrams
ADC1005 (for an a-bit data bus)
ADC1025 (10-bit parallel outputs)
Dual-In-Line Package
Dual-In-Line Package
CS-I
20I- Vee
CS-l
24
iW- 2
19 f-ClKR
iW-2
23 -CLKR
22 -0'
Vee
iYR-3
18 f-
BIT2 0
iYR-3
ClKIN- 4
171-
BIT3 0
ClKIN- 4
INTR- S
ISC-
BIT4 0
INTR- 5
20 -BIT2
V~C+)- 6
ISf-
BITS 0
VINC+)- 6
19 -BIT3
VINC-)- 7
141-
BIT6 0
VINC-)- 7
18 -BIT4
AGND- 8
131-
BIT7 0
AGND- 8
17 -BIT5
VREF - 9
12 f-
BIT8 BITO(lSB)
VREF- 9
16 -BiT6
DGND- 10
llf-(USB)BIT9 BIT 1
ISTBYTE 2NDBYTE
21-0'
BITI- 10
15~BIT7
(lSB)BITO- 11
14 f-BIT8
DGNO- 12
TLlH/5261-1
13,...BIT9(USB)
TLlH/5261-2
Top View
Top View
ADC1005 Molded Chip Carrier Package
ADC1025 Molded Chip Carrier Package
s~s.~~
~
!::
!::
!::
•
iii i i
25 24 23 22 21 20 19
18 17 16 15 14
CLKR- 19
Vee -
0'-26
13I-BIT7/0
20
12I-BIT8/BITO(LSB)
CS- 1
111-(USB)BIT9/BITI
iW-2
IOI-DGND
91- VREF
iYR- 3
4
5
~
·I.!.!!'
6
7
N t<') ~ II') co
O!:: t:: !:: t:: t:
'I 'I iii i i
!::
8
16 -BIT8
CS-l
15 -BIT9
iW- 2
14 -DGND
iYR-3
13 -BITO
'5I~~~~~~}
4
6
d~}}~
Tl/H/5261-19
Top View
'TRI·STATE® output buffers which output 0 during
17f-BIT7
Vee - 28
ClKIN -
~ ~~
18f-NC
ClKR-27
7
>
8
>
Top View
AD
See Ordering Information
3-211
12 -BITI
9 10 11
TLlH/S261-20
II)
'"
....c
Absolute Maximum Ratings
cr:
.....
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications•
g
II)
....og
5i!
Supply Voltage (Vee)
Logic Control Inputs
Voltage at Other Inputs and Outputs
Input Current Per Pin
Input Current Per Package
Operating Ratings (Notes 1 & 2)
(Notes 1 & 2)
6.5V
Package Dissipation at TA = 25'C
Lead Temperature
(Soldering, 10 seconds)
Dual-In-Line Package (Plastic)
Dual-In-Line Package (Ceramic)
Surface Mount Package
Vapor Phase (60 seconds)
Infrared (15 seconds)
ESD Susceptibility (Note 8)
TMN,;;TA,;;TMAX
-55'C,;;TA';; + 125'C
ADG1025BJ, ADC1025CJ
ADCl 005BCJ, ADCl 005CCJ
ADC1025BCJ, ADC1025CCJ
-0.3Vto +15V
-0.3V to Vee +0.3V
±5mA
-40'C';;TA';; + 85'C
O'C,;;TA,;;70'C
ADCl 005BCJ-l, ADC1005CCJ-l
ADC1025BCJ-l, ADC1025CCJ-l
±20mA
Storage Temperature Range
4.5Vt06.0V
Supply Voltage (Vecl
Temperature Range
ADCl 005BJ, ADC1005CJ
- 65'C to + 150'C
875mW
ADC1005BCN, ADC1005CCN
ADC1025BCN, ADC1025CCN
ADC1005BCV,ADC1005CCV
ADC1025BCV, ADC1025CCV
260'C
300'C
215'C
220'C
800V
Electrical Characteristics The following specifications apply for Vee = 5V, VREF = 5V, felK = I.B MHz
unless otherwise specified. Boldface limits apply from T MIN to T MAX; All other limits TA = Tj = 25'C.
ADC10X5BCJ·l, ADC10X5CCJ·l
ADC10X5BCN, ADC10X5CCN
ADC10X5BCV, ADC10X5CCV
Limit
Units
Design
Design
Tested
Typ
Limit
Limit
Limit
(Note 5)
(Note 6)
(Note 7)
(Note 7)
ADC10X5BJ, ADC10X5BCJ
ADC10X5CJ, ADC10X5CCJ
Parameter
Conditions
Typ
(Note 5)
Tested
Limit
(Note 6)
I
I
Converter Characteristics
Linearity Error (Note 3)
ADCl OX5BJ, ADCl OX5BCJ
ADCl OX5BCJ-l, BCN, BCV
ADCl OX5CJ, ADCl OX5CCJ
ADClOX5CCJ-l, GCN, CCV
±O.S
±0.5
±O.S
±1
±1
±0.5
±O.S
±1
±1
±0.5
±O.S
±1
Zero Error
ADCl OX5BJ, ADCl OX5BCJ
ADC10X5BCJ-l, BCN; BCV
ADCl OX5CJ, ADCl OX5CCJ
ADClOX5CCJ-l, CCN, CCV
±O.S
±1
Fullscale Error
ADCl OX5BJ, ADCl OX5BCJ
ADC10X5BCJ-l, BCN, BCV
ADC10X5CJ, ADCl OX5CCJ
ADCl OX5CCJ-l, CCN, CCV
±O.S
MIN
MAx
Common-Mode
Input (Note 4)
MIN
MAX
2.2
8.3
4.B
4.B
4.8
4.8
±1
±1
2.4
7.6
2.2
8.3
kO
kO
Vee + 0.05 Vcc+ O•OS
GND-0.05 GND-O.OS
Vcc+ O•OS
GND-O.OS
VIN(+) orVIN(-)
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
±1
Reference
Input
Resistance
LSB
LSB
LSB
LSB
V
V
DC Common-Mode
Error
Over Common-Mode
Input Range
±Ys
±%
±Ys
±%
±%
LSB
Power Supply Sensitivity
Vcc=5 Voe±5%
VREF = 4.75V
±Ys
±%
±Ys
±%
±%
LSB
3-212
»
c
o-"
Electrical Characteristics (Continued) The following specifications apply for Vee =
SV. VREF = SV. felK =
1.8 MHz unless otherwise specified. Boldface limits apply from T MIN to T MAX; All other limits TA = Tj = 2SoC.
ADC10X5BJ, ADC10X5BCJ
ADC10X5CJ, ADC10X5CCJ
Parameter
Conditions
Typ
(Note 5)
Tested
Limit
(Note 6)
Design
Limit
(Note 7)
ADC10X5BCJ-1, ADC10X5CCJ-1
ADC10X5BCN, ADC10X5CCN
ADC10X5BCV, ADC10X5CCV
Typ
(Note 5)
Tested
Limit
(Note 6)
Design
Limit
(Note 7)
o
o
U1
.......
Limit
Units
»
c
o-"
o
N
U1
DC Characteristics
VIN(1) Logical "1" Input
Voltage MIN
Vee=S.2SV
(except CLKIN )
2.0
2.0
2_0
V
VIN(O). Logical "0" Input
Voltage MAX
VCC=4.7SV
(Except CLKIN )
O.S
0.8
O.S
V
liN. Logical "1" Input
Current MAX
VIN=S,OV
1
p.A
liN. Logical "0" Input
Current MAX
VIN=OV
1
O.OOS
1
O.OOS
-O.OOS
-1
-O.OOS
-1
-1
p.A
VT+(MIN). Minimum CLKIN
Positive going Threshold
Voltage
3.1
2.7
3.1
2.7
2_7
V
VT(MAX). Maximum CLKIN
Positive going Threshold
Voltage
3.1
3_5
3.1
3.S
3.5
V
VT - (MIN). Minimum CLKIN
Negative going Threshold
Voltage
1.8
1.5
1.8
I.S
1.5
V
VT - (MAX). Maximum CLKIN
Negative going Threshold
Voltage
1.8
2_1
1.8
2.1
2_1
V
VH(MIN). Minimum ClKIN
Hysteresis (VT + -VT -)
1.3
0.6
1.3
0.6
0.6
V
VH(MAX). Maximum CLKIN
Hysteresis (VT + -VT -)
1.3
2_0
1.3
2.0
2.0
V
2.4
4.5
2.8
4.6
2.4
4_5
V
V
0_4
0.34
0.4
V
VOUT(1). logical "1"
Output Voltage
MIN
Vce=4.7SV
IOUT= -360 p.A
IOUT= -10 p.A
VOUT(O). Logical "0"
Output Voltage
MAX
Vce=4.7SV
IOUT=I.6mA
lOUT. TRI-STATEOutput
Current
MAX
VOUT = OV
VOUT = SV
ISOURCE. Output Source
Current
MIN
ISINK. Output Sink
Current
MIN
VOUT=OV
VOUT=SV
Icc. Supply Current
MAX
fClK = 1.8 MHz
CS="I"
-0.01
0.01
-3
3
-0.01
0.01
-0.3
0.3
-3
3
p.A
p.A
-14
-6.5
-14
-7.S
-6_5
mA
16
8_0
16
9.0
8_0
mA
I.S
3
I.S
2.S
3
mA
AC Electrical Characteristics The following specifications apply for VCC =
SV. VREF = SV. tr = tl = 20 ns
unless otherwise specified. Boldface limits apply from TMIN to TMAX; All other limits T A = Tj = 2SoC.
Tested
Limit
(Note 6)
Design
Limit
(Note 7)
Limit
Units
fClK. Clock FrequencyMIN
MAX
0.2
2.6
0.2
2.6
MHz
MHz
Clock Duty Cycle
40
60
40
60
%
%
Parameter
Conditions
Typ
(Note 5)
MIN
MAX
3-213
•
II)
C'I
o
o
Q
VIN(+) the digital output code will be 00 0000 0000. Two on·chip diodes are lied to each analog input which will forward conduct for analog
input voltages one diode drop below ground or one diode drop greater than Vee supply. Be careful. during testing at low. Vee levels (4.5V). as high level analog
inputs (5V) can cause this input diode to conduct, especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows 50 mV
forward bias of e~her diode. This means that as long as the analog VIN does not exceed the supply voltage by more than 50 mY. the output code will be correct. To
achieve an absolute 0 VDC to 5 Voc input voltage range will therefore require a minimum supply voltage of 4.950 VDC over temperature va~iations, initial tolerance
and loading.
Note 5: Typicals are at 2S'C and represent most likely parametric norm.
Nole 6: Tested and guaranteed to National's AOQL (Average Outgoing
Qual~
Level).
Note 7: Guaranteed. but not 100% production tested. These limits are not used to calculate outgoing quality levels.
Note 8: Human body model. 100 pF discharged through a 1.5 kn resistor.
Functional Diagram
r----cs
CLKR
cr 1.=: .
L
b>
I
CONTROL
AND
TIMING
~INTR
1
+
SAR
I\NI-I
I
........
,
~
BYTE
SEQUENCER
AND
TRI·SllITE"
OUTPUT
lATCH
lADDER
AND
DECODER
AL
1
3-214
--
~}-~
~
r-
ADCtD05
ONLY
~
~
I
DGND
I
Vee
(5VI
TL/H/5261-3
~
Typical Performance Characteristics
1.8
~
1.1
1.6
~
~
">
300
1.4
1.3
4.50
2.7
4.75
5.00
5.25
5.50
o
200
2.3
;;
1.9
400
GOD
BOD
Output Current vs
Temperature
B
'"~ 0.8
DATA OUTPUT
BUFFERS
-\sriu~c~
V1,.
1.5
4.50
1000
4.75
0.41--"':"·-+-*'--+----1
g
0.2
0
ffi -0.2
~
1-v~~~K. 0.4 VOC i'"
75
5.50
f---t---+
~
~
50
5.25
r---,---r-::--::::o
0.6
!
25
5.00
1
I
VCC - SUPPLY VOLTAGE (VOC)
w
~
I
....,'!.OUT ~ 2.4 VOC
0
U1
Typical linearity Error
vs Clock Frequency
1
VCC~5VOC
2
-50 -25
oII.)
1--'1-
LOAD CAPACITANCE (pF)
VCC - SUPPLY VOLTAGE (V DC)
~
C
-5SoCSTA -::;;+125°C
"
"::J'"
~
100
U1
......
o
.....
..
~
....
200
'"0;
~
v+
~
"
V
3.1
~
L
~
1.5
E
w
"'"
,-
'"
::J
~
3.5
400
">
~
o
o
ClK IN Schmitt Trip levels
vs Supply Voltage
500
-.!-5~'CldA ~+125Ic i7'
w
o
.....
Delay from Falling Edge of
RD to Output Data Valid vs
load Capacitance
logic Input Threshold
Voltage vs Supply Voltage
~
C
-0.4 1---+----+----1
-0.6 1---+----/-----1
-0.8 1---+----+----1
-1
L-_~
0.2
100 125
TA - AMBIENT TEMPERATURE ('C)
____
~
__
1.0
1.8
CLOCK FREQUENCY (MHz)
~
2.6
TL/H/5261-4
Timing Diagrams
Start Conversion
\
I
~jJ_1w_(W_R)_L_____
(LAST DATA WAS READ)
(LAST DATA WAS NOT READ)
TLlH/5261-5
Output Enable and Reset INTR
INTR RESET
-'tAl
-
1ST RO'
2NORO\
/
' - - .~
"RS
DATA
OUTPUTS- -
__
-
~R!!TA~® _ _ _
By_L~_E_J}- _ _
-{.._ _
'ACC
'The 24-pin ADC1025 Qulpul. all 10 bits on each RD
TLlH/5261-6
Note: All timing is measured from the 50% voltage points.
3-215
•
Il')
('II
o
.,...
o
Timing Diagrams (Continued)
C
1 kn). If input bypass capacitors are necessary for
noise filtering and high source resistance is desirable to
minimize capaCitor size, the detrimental effects of the voltage drop across this input resistance, which is due to the
average value of the input current, can be eliminated with a
full-scale adjustment while the given source resistor and input bypass capaCitor are both in place. This is possible because the average value of the input current is a linear function of the differential input voltage.
3.1 Analog Differential Voltage Inputs and
Common-Mode Rejection
The differential inputs of these converters reduce the effects of common-mode input noise, which is defined as
noise common to both selected" + " and" -" inputs (60 Hz
is most typical). The time interval between sampling the
"+" input and the "-" input is half of an internal clock
period. The change in the common-mode voltage during this
short time interval can cause conversion errors. For a sinusoidal common-mode signal, this error is:
4
VERROR(MAX) = VPEAK (21T fCM) X fCLK
3.4 Input Source Resistance
large values of source resistance where an input bypass
capacitor is not used, will not cause effors if the input currents settle out prior to the comparison time. If a low pass
filter is required in the system, use a low valued series resistor (s; 1 kfi) for a passive RC section or add an op amp RC
active low pass filter. For low source resistance applications
(S;0.1 kn) a 4700 pF bypass capacitor at the inputs will
prevent pickup due to series lead induction of a long wire. A
1000, series resistor can be used to isolate this capaCitor both the R and the C are placed outside the feedback loop
- from the output of an op amp, if used.
where fCM is the frequency of the common-mode signal,
VPEAK is its peak voltage value and fCLK is the clock frequencyat the ClK IN pin.
For a 60 Hz common-mode signal to generate a 1/4 lSB
error (1.2 mY) with the converter running at 1.8 MHz, its
peak value would have to be 1.46V. A common-mode signal
this large is much greater than that generally found in data
aquisition systems.
3.2 Input Current
Due to the sampling nature of the analog inputs, short duration spikes of current enter the" +" input and exit the" -"
input at the clock rising edges during the conversion. These
currents decay rapidly and do not cause errors as the internal comparator is strobed at the end of a clock period.
3.5 Noise
The leads to the analog inputs (pins 6 and 7) should be kept
as short as possible to minimize input noise coupling. Both
noise and undesired digital clock coupling to these inputs
can cause system errors. The source resistance for these
inputs should, in general, be kept below 1 kn. larger values
of source resistance can cause undesired system noise
pickup. Input bypass capacitors, placed from the analog inputs to ground, can reduce system noise pickup but can
create analog scale errors. See section 3.2, 3.3, and 3.4 if
input filtering is to be used.
3.3 Input Bypass Capacitors
Bypass capacitors at the inputs will average the current
spikes noted in 3.2 and cause a DC current to flow through
the output resistances of the analog signal sources. This
charge pumping action is worse for continuous conversions
with the VIN(+) input voltage at full scale. For continuous
conversions with a 1.8 MHz clock frequency with the VIN( + )
3-218
Functional Description
»
c
....oo
(Continued)
4.0 OFFSET AND REFERENCE ADJUSTMENT
o
en
.....
4.1 Zero Offset
The zero error of the AID converter relates to the location
of the first riser of the transfer function and can be measured by grounding the V( -) input and applying a small
magnitude positive voltage to the V( +) input. Zero error is
the difference between the actual DC input voltage that is
necessary to just cause an output digital code transition
from 00 0000 0000 to 00 0000 0001 and the ideal 112 LSB
value (1/2 LSB = 2.45 mV for VREF = 5.0 Vocl.
The zero of the AID normally does not require adjustment.
However, for cases where VIN(MIN) is not ground and in
reduced span applications (VREF < 5V), an offset adjustment may be desired. The converter can be made to output
an all zero digital code for an arbitrary input by biasing the
AID's VIN( -) input at that voltage. This utilizes the differential input operation of the AID.
zero reference voltage at the corresponding "-" input
should then be adjusted to just obtain the OOOHEX 001 HEX
code transition.
The full-scale adjustment should be made [with the proper
VIN( -) voltage applied) by forcing a voltage to the VIN( + )
input given by:
.
[(VMAX - VMIN)]
VIN(+) FS ad] = VMAX - 1.5
1024
where VMAX = the high end of the analog input range and
VMIN = the low end (the offset zero) of the analog range.
(Both are ground referenced).
The VREF (or Vecl voltage is then adjusted to provide a
code change from 3FFHEX to 3FEHEX. This completes the
adjustment procedure.
For an example see the Zero-Shift and Span-Adjust circuit
below.
4.2 Full Scale
The full-scale adjustment can be made by applying a differential input voltage that is 1% LSB down from the desired
analog full-scale voltage range and then adjusting the magnitude of the VREF input for a digital output code that is just
changing from 1111111110 to 11 11111111.
5.0 POWER SUPPLIES
Noise spikes on the Vee supply line can cause conversion
errors as the comparator will respond to this noise. A low
inductance tantalum filter capaCitor should be used close to
the converter Vee pin and values of 1 p.F or greater are
recommended. If an unregulated voltage is available in the
system, a separate LM340LAZ-5.0, TO-92, 5V voltage regulator for the converter (and the other analog cirCUitry) will
greatly reduce digital noise on the Vee supply.
A single point analog ground that is separate from the logic
ground points should be used. The power supply bypass
capaCitor and the self-clocking capacitor (if used) should
both be returned to the digital ground. Any VREF bypass
capaCitors, analog input filters capaCitors, or input Signal
shielding should be returned to the analog ground point.
4.3 Adjusting for an Arbitrary Analog
Input Voltage Range
If the analog zero voltage of the AID is shifted away from
ground (for example, to accommodate an analog input signal that does not go to ground), this new zero reference
should be properly adjusted first. A VIN( +) voltage that
equals this desired zero reference plus 112 LSB (where the
LSB is calculated for the desired analog span, 1 LSB =
analog span/1 024) is applied to selected" +" input and the
vccl-~I----------....
AOC1005
AOC10Z5
f
+
10
"F
3.9k
~~
*'
AOJ
r- - - - - - - -..,
,I lk AJr-,
lIZ LM35B
3V
I,:::
~ l"F
,~
SETS ZERO
CODE VOLTAGE
Z.lk
330
Uk
+
""I
,I
,
SETS VOLTAGE SPAN
_..,'
LM336.Z.5·~ ~
I
,
,
L _________ J
1k
Z VOC
ZERO AOJ
TLlH15261-16
Figure 4. Zero-Shift and Span-Adjust (2V :5: VIN :5: 5V)
3-219
»
c
o....
o
en
N
II)
N
(;)
.....
0
Typical Applications
sv
ec(
......
20
es
II)
(;)
(;)
Vee
iili
Wii
.....
e
c(
0
eLK R
10k
eLK IN
INTR
11
12
13
14
1S
16
17
18
150~
19
TRANSDUCER
10·BIT RESOLUTION
OVER
ANALOG INPUT,
VOLTAGE RANGE
087
OB6
OBS
Aoel005
VINI')
OIFf INPUTS
OB4
VINI-)
OB3
AGNO
OB2
VREF
DBl
OBO
o GNO
10
TL/H/5261-13
Operating with Ratlometric Transducers
Handling ± 5V Analog Inputs
Vee (5 Voe)
Vee (5 Vue)
2k
Vee
Vee
1---1~-f IIINI+)
3.3k
20k
0.7 Vee
1k
VREF
±5V
10 TURN
TRIM POT
I1~F
VREF
7.5k
VIN(_I
AGND
VIN(-)
= 0.15 Vee
TL/H/5261-14
TLlH/5261-15
15% of Vee s VXDR S 85% of Vee
TRI-STATE Test Circuits and Waveforms
Vee
---i-j,=---
iili
DATA :::
OUTPUTS
GND
~~IH
~
-------'==
TLlH/5261-9
1,=20 ns
OH
DATA
OUTPUT
DATA
OUTPUTS
Vee
~
-10%
VOL
1,=20 ns
TL/H/5261-B
3-220
TLlH/5261-10
,----------------------------------------------------------------------,
Ordering Information
Part Number
ADC1005BCN
Package
Outline
Temperature
Range
Linearity
Error
Part Number
N20A
Package
Outline
ADC1005CCN
N20A
ADC1025BCN
N24C
ADC1025CCN
N24C
ADC1005BCV
V20A
ADC1005CCV
V20A
ADC1025BCV
V28A
ADC1025CCV
V28A
ADC1005BCJ-1
J20A
ADC1025BCJ-1
J24F
ADC1005BCJ
J20A
ADC1025BCJ
J24F
ADC1005BJ
J20A
ADC1025BJ
J24F
O°Cto +70°C
±%LSB
-40°C to + 85°C
- 55°C to + 125°C
ADC1005CCJ-1
J20A
ADC1025CCJ-1
J24F
ADC1005CCJ
J20A
ADC1025CCJ
J24F
ADC1005CJ
J20A
ADC1025CJ
J24F
Temperature
Range
Linearity
Error
~
c
o
......
o
o
c.n
.......
~
c
o......
o
1\3
c.n
O°Cto +70°C
±1 LSB
-40°C to +85°C
- 55°C to + 125°C
•
3-221
U)
N
N
r----------------------------------------------------------------------------,
.....
o ~National
C
I
ADC1tz&
IiII
DB5
Ci
10
lm
11
11
DB3
DIGITAL GIlD
12
17
"2
IlEADYIIU'I
"
"
11
1181
"
DID
iii!
I
DaG
eLKIN
Top View
I
I
BVTE
SEQUENCEft
AND
TRI-8TATE"
OUTPUT
LATCH
TWOBVTE
1
ADe12D5
ONLY
LADDER
AND
DECODER
I
~------ 'iREF -----~--~
AGND
18
~-------------9lmr
I
I
I
'-1+1
I
I
SUCCESSIVE
APPROXIMATION
REGISTER
v-
DIGITAL
Vee
-I.
STATUS
I
I
I
~NI-I
ANALOGO_D
READY
OUT
I
Dual-In-Line Package
'11111-1
iiii Viii
I
TLlH/5676-1
Top View
cs
CONTROL
AND
TIMING
I
ADC1205
ClK
IN
ANALOG
lice
TLlH/5676-3
See Ordering Information
Tl/H/5676-2
3-222
Absolute Maximum Ratings
»
c
o
Operating Conditions (Notes 1 & 2)
(Notes 1 & 2)
Temperature Range
ADC1205BCJ, ADC1205CCJ
ADC1225BCJ, ADC1225CCJ
ADC1205BCJ-l, ADC1205CCJ-l
ADC1225BCJ-l, ADC1225CCJ-l
Supply Voltage (DVcc and AVcc)
Negative Supply Voltage (V-)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (DVcc and AVcC>
6.5V
Negative Supply Voltage (V-)
-15VtoGND
Logic Control Inputs
-0.3V to + 15V
Voltage at Analog Inputs
(V-)-0.3Vto Vcc+0.3V
[VIN(+), VIN(-)l
-0.3Vto (Vcc+0.3)V
Voltage at All Outputs, VREF, Vas
Input Current per Pin
±5mA
Input Current per Package
±20mA
Storage Temperature Range
- 65'C to + 150'C
Package DiSSipation at T A = 25'C
875mW
Lead Temp. (Soldering, 10 seconds)
300'C
ESD Susceptibility (Note 12)
800V
TMIN,;;TA,;;TMAX
0'C,;;TA,;;70'C
4.5 Voc to 6.0 Voc
-15VtoGND
Electrical Characteristics
Parameter
Conditions
Typ
(Note 8)
Tested
Design
Limit
Limit
(Note 9) (Note 10)
ADC120SBCJ·1, ADC120SCCJ·1
ADC122SBCJ·1, ADC122SCCJ·1
Design
Tested
Typ
Limit
Limit
(Note 8)
(Note 10)
(Note 9)
Limit
Units
CONVERTER CHARACTERISTICS
Linearity Error
Unipolar Input
ADC1205BCJ, ADC1225BCJ
Range
ADC1205BCJ-l, ADC1225BCJ-l (Note 11)
ADC1205CCJ, ADC1225CCJ
ADCI205CCJ-l, ADCI225CCJ-l
±1
±1
LSB
LSB
LSB
LSB
Unadjusted Zero Error
Unipolar Input
Range
±2
±2
±2
LSB
Unadjusted Positive and Negative
Full-Scale Error
Unipolar Input
Range
±30
±30
±30
LSB
Negative Full-Scale Error
Unipolar Input
Range, Full
Scale Adj. to
Zero
±Yz
LSB
±Yz
±Y2
±Yz
±1
±Yz
Linearity Error
Bipolar Input
Range
ADCI205BCJ, ADC1225BCJ
ADCI205BCJ-l, ADCI225BCJ-l (Note 11)
ADC1205CCJ, ADC1225CCJ
ADC1205CCJ-l, ADC1225CCJ-l
±1.S
±2
±2
LSB
LSB
LSB
LSB
Unadjusted Zero Error
Bipolar Input
Range
±2
±2
±2
LSB
Unadjusted Positive and Negative
Full-Scale Error
Bipolar Input
Range
±30
±30
±30
LSB
Negative Full-Scale Error
Bipolar Input
Range, Full
Scale Adj. to
Zero
±2
±2
±2
LSB
±1.5
±1.S
±2
6
1S
6
1S
ppml'C
Maximum Offset Temperature
Coefficient
0.5
1.S
0.5
1.S
ppml'C
Minimum VREF Input Resistance
4.0
2
4.0
2
2
kO
Maximum VREF Input Resistance
4.0
8
4.0
8
8
kO
Maximum Gain Temperature
Coefficient
3-223
o
UI
-40'C,;;TA';; + 85'C
The following specifications apply for DVcc = AVcc = 5V, VREF = 5V, fCLK = 1.0 MHz, V- = -5V for bipolar input range, or
V- = GND for unipolar input range unless otherwise specified. Bipolar input range is defined as -5.05V ,;; VIN(+) ,;; 5.05V;
-5.05V ,;; VIN(-) ,;; 5.05V and IVIN(+) - vIN(-)1 ,;; 5.05V. Unipolar input range is defined as -0.05V ,;; VIN(+) ,;; 5.05V;
-0.05V,;; VIN(-) ,;; 5.05V and IVIN(+) - vIN(-)1 ,;; 5.05V. Boldface limits apply from TMIN to TMAX; all other limits TA = TJ
= 25'C (Notes 3, 4, 5, 6, 7).
ADC120SBCJ, ADC120SCCJ
ADC122SBCJ, ADC122SCCJ
-r.
N
»
c
o-r.
N
N
UI
\I)
C'I
C'I
....
(.)
c
~
....
o
C'I
Electrical Characteristics (Continued)
The following specifications apply for DVcc = AVcc = 5V, VREF = 5V, fClK = 1.0 MHz, V- = -5V for bipolar input range, or
V- = GND for unipolar input range unless otherwise specified. Bipolar input range is defined as -5.05V ,;;: VIN(+) ,;;: 5.05V;
-5.05V ,;;: VIN(-) ,;;: 5.05V and IViN(+) - vIN(-)1 ,;;: 5.05V. Unipolar input range is defined as -0.05V ,;;: VIN(+) ,;;: 5.05V;
-0.05V';;: VIN(-) ,;;: 5.05Vand IVIN(+) - vIN(-)1 ,;;: 5.05V. Boldface limits apply from TMIN to TMAX;all other IimitsTA = TJ
= 25'C (Notes 3, 4, 5, 6, 7) .
(.)
cc(
ADC120SBCJ, ADC120SCCJ
ADC122SBCJ, ADC122SCCJ
Parameter
Conditions
Typ
(NoteS)
Tested
Limit
(Note 9)
Design
Limit
(Note 10)
ADC120SBCJ-1, ADC120SCCJ-1
ADC122SBCJ-1, ADC122SCCJ-1
Typ
(Note S)
Tested
Limit
(Note 9)
Design
Limit
(Note 10)
GND-D.05
GND-O.OS
Limit
Units
CONVERTER CHARACTERISTICS (Continued)
Minimum Analog Input
Voltage
Maximum Analog Input
Voltage
Unipolar Input
Range
Bipolar Input
Range
Unipolar Input
Range
Bipolar.lnput
Range
DC Common-Mode Error
Power Supply Sensitivity
GND-O.OS
-Vc- 0.05 -Vee- O•OS
V
Vcc+ 0.05
Vee + 0.05
V
Vcc+ 0.05
Vee + 0.05
V
±%
±%
LSB
±%
±%
±%
±%
±%
±%
lSB
lSB
±%
±%
±%
lSB
-Vee- O•OS
Vee + 0.05
Vee + 0.05
±Ya
V
±%
±Ya
AVcc=:DVcc=
5V±5%,
V-=-5V±5%
Zero Error
Positive and Negative
Full-Scale Error
Linearity Error
DIGITAL AND DC CHARACTERISTICS
VIN(l), logical "1" Input
Voltage (Min)
Vcc=5.25V,
All Inputs except
ClKIN
2.0
2.0
2.0
V
VIN(O), logical "0" Input
Voltage (Max)
Vcc=4.75V,
All Inputs except
ClKIN
O.S
0.8
0.8
V
IIN(l), logical "1" Input
Current (Max)
VIN=5V
0.005
1
0.005
1
p.A
IIN(O), logical "0" Input
Current (Max)
VIN=OV
-0.005
-1
-0.005
-1
p.A
Vr+ (Minj, Minimum PositiveGoing Threshold Voltage
ClKIN
3.1
2.7
3.1
2.7
2.7
V
Vr+ (Max), Maximum Positive- ClKIN
GOing Threshold Voltage
3.1
3.5
3.1
3.5
3.5
V
Vr- (Min), Minimum NegativeGoing Threshold Voltage
elKIN
1.8
1.4
1.8
1.4
1.4
V
Vr- (Max), Maximum Negative- ClKIN
Going Threshold Voltage
1.8
2.1
1.8
2.1
2.1
V
VH(Minj, Minimum Hysteresis
[Vr+(Minj-VT-(Max))
ClKIN
1.3
0.6
1.3
0.6
0.6
V
VH(Max), Maximum Hysteresis
[Vr+(Maxj-Vr-(Min)1
ClKIN
1.3
2.1
1.3
2.1
2.1
V
3-224
»
c
Electrical Characteristics (Continued)
The following specifications apply for DVcc = AVcc = 5V, VREF = 5V, fCLK = 1.0 MHz. V- = -5V for bipolar input range, or
V- = GND for unipolar input range unless otherwise specified. Bipolar input range is defined as -5.05V ,;; VIN(+) ,;; 5.05V;
-5.05V ,;; VIN(-) ,;; 5.05V and IVIN(+) - vIN(-)1 ,;; 5.05V. Unipolar input range is defined as -0.05V ,;; VIN(+) ,;; 5.05V;
-0.05V,;; VIN(-) ,;; 5.05Vand IVIN(+) - vIN(-)1 ,;; 5.05V. Boldface limits apply from TMIN to TMAX; all other limits TA = TJ
= 25°C (Notes 3, 4, 5, 6, 7).
ADC1205BCJ, ADC1205CCJ
ADC1225BCJ, ADC1225CCJ
Parameter
Conditions
Typ
(Note 8)
en
Limit
Units
Design
Limit
(Note 10)
2.4
4.5
2.4
4.5
2.4
4.5
V
V
0.4
0.4
0.4
V
Typ
(Note 8)
DIGITAL AND DC CHARACTERISTICS (Continued)
VOUT(l), Logical "1" Output
Voltage (Min)
Vcc=4.75V
IOUT= -360 p.A
IOUT= -10 p.A
VOUT(O), Logical "0" Output
Voltage (Max)
Vcc=4.75V
IOUT=1.6mA
lOUT. TRI-STATE Output Leakage VOUT=OV
Current (Max)
VOUT=5V
-0.Q1
0.01
-3
3
-0.Q1
0.01
-0.3
0.3
-3
3
p.A
p.A
-7.0
-6.0
mA
ISOURCE, Output Source Current
(Min)
VOUT=OV
-12
-6.0
-12
ISINK, Output Sink Current (Min)
VOUT=5V
16
8.0
16
9.0
8.0
mA
1
3
1
2.5
3
mA
DICC, DVCC Supply Current (Max) fCLK=l MHz,CS=l
AICC, AVCC Supply Current (Max) fCLK=l MHz,CS=l
1
3
1
2.5
3
mA
1-, V - Supply Current (Max)
10
100
10
100
100
p.A
fCLK= 1 MHz, CS= 1
AC Electrical Characteristics
The following specifications apply for DVCC = AVCC = 5.0V, tr= tf = 20 ns and T A = 25°C unless otherwise specified.
Parameter
Conditions
Typ
(Note 8)
Tested
Limit
(Note 9)
1.0
1.0
0.3
1.5
Design
Limit
(Note 10)
Limit
Units
fCLK. Clock Frequency
MIN
MAX
Clock Duty Cycle
MIN
MAX
40
60
%
%
T C, Conversion Time
MIN
MAX
MIN
MAX
108
109
108
109
l/fCLK
l/fCLK
fCLK = 1.0 MHz
fCLK=1.0MHz
MAX
MHz
MHz
,",S
p's
220
350
ns
tACC, Access Time (Delay from
Falling Edge of RD to
Output Data Valid) (Max)
CL =100 pF
210
340
ns
tlH, ioH, TRI-STATE Control (Delay
from Rising Edge of RD to
Hi-Z State) (Max)
RL =2k, CL = 100 pF
170
290
ns
tpD(READYOUT), RD or WR to
READYOUT Delay (Max)
250
400
ns
tpD(INT),RD or WR to Reset of INT
(Max)
250
400
ns
tW(WR)L, WR Pulse Width
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating ratings.
Note 2: All voltages are measured with respect to ground. unless otherwise specified.
Note 3: A parasitic zener diode exists internally from AVec and DVcc to ground. This parasitic zener has a typical breakdown voltage of 7 VDC.
3-225
»
c
o......
N
N
ADC1205BCJ-1, ADC1205CCJ-1
ADC1225BCJ-1, ADC1225CCJ-1
Tested
Limit
(Note 9)
Tested Design
Limit
Limit
(Note 9) (Note 10)
o
......
N
o
en
.....
Ln
<"I
<"I
.....
U
C
AC Electrical Characteristics (Continued)
Note 4: Two on-chip diodes are tied to each analog input as shown below.
cc
;:n
DIGITAL Vee
CI
<"I
.....
U
C
CC
VJNI+1
ORVJNH
t-r-t--+ TO INTERNAL CIRCUITRY
VTl/H/5676-4
Errors in the AID conversion can occur if these diodes are forward biased more than 50 mY. This means that if AVec and DVec are minimum (4.75 Vecl and V- is
minimum (-4.7SVecl, full-scale must be';: 4.8Vec.
Note 5: A diode exists between analog Vec and digHal Vc.
m--tT
I
I
AVee
DVcc
~
TO INTERNAL CIRCUITRY
TO INTERNAL CIRCUITRY
I
I
Tl/H/5676-20
To guarantee accuracy, it is required that the AVec and DVec be connected together to a power supply with separate bypass filters at each Vcc pin.
Note 6: A diode exists between analog ground and digital ground.
ANALOG GROUND
DIGITAL GROUND
~ TO INTERNAL CIRCUITRY
o-----L
TO INTERNAL CIRCUITRY
Tl/H/5676-21
To guarantee accuracy, it is required that the analog ground and digital ground be connected together externally:
Note 7: Accuracy is guaranteed at fClK = 1.0 MHz. At higher clock frequencies accuracy may degrade.
Note 8: Typicals are at 2S'C and represent most likely parametric norm.
Note 9: Tested and guaranteed to National's AOOL (Average Outgoing QualHy Level).
Note 10: Guaranteed, but not 100% production tested. These limits are not used 10 calculate oulgoing quality levels.
Note 11: Linearity error is defined as Ihe deviation of the analog value, expressed in LSBs, from the slraighlline which passes through posHive full scale and zero,
after adjusting zero error. (See Figures Ib and Ie).
Note 12: Human body model; 100 pF discharged through a 1.5 kn resistor.
14095) 0,1111,1111,1111
(4094) 0,1111,1111,1110
POSITIVE
FULL·SCALE
TRANSITION
+VREF
I,ODDD,DODO,DODI (-4095)
I,DODO,DOOO,DDDD (-4096)
ANALOG INPUT VOLTAGE IVINI +1- VINI-' I
FIGURE
1a. Transfer Characteristic
3-226
TLlH/5676-8
»
c
o....
N
o
U1
......
»
c
o....
N
~
-3 LSD
OUTPUT CODE
+ 40951
{fHDM - 4096 TO
TUH/5676-22
FIGURE 1b. Simplified Error Curve vs. Output Code Without Zero and Fullscale Adjustment
~
III
+3 LSB
+2 LSD
NEGATIVE
FULLSCAI£
ERROR
I
+1 LSD
UNWITY ERROR
-1 LSD
-2 LSB
-3 LSD
OUTPUT CODE
(FROM - 4096 TO +40951
TL/H/5676-23
FIGURE 1c. Simplified Error Curve vs. Output Code after Zero/Fuliscale Adjustment
•
Vee
DATA
OUl1'UT
iiD
Vee
iiii
GND
Rl
":"
YoH
DATA OUTPUT
":"
GNO
#":" T
Vee
Vee
l
Ii
R
Vee ---t:J~::-
DATA
OUTPUT
iiii
OND
CL
Vee
-
toHR,-
DATA OUTPUT
YoL _ _ _ _.;II 1011
TLlH/5676-7
FIGURE 2. TRI·STATE Test Circuits and Waveforms
3·227
U)
N
N
r---------------------------------------------------------------------------------,
.-
Timing Diagrams
C
Transfer Characteristic for ADC1205 and ADC1225 Unipolar Input Range and Bipolar Input Range (digital output codes vs the
difference of the analog inputs [ VIN! +) - VIN( _) ])
o
C
Functional Description (Continued)
o
.....
CS
~
C)
U1
......
ViR
I t,
I t,
,
,
,I
,
,
,I
,
,
I.
Rii
INTR
,.,
Tc
~
U1
,
,,
,
L.J
DATA
(OBO-OBI2)
~
,
,,
,
REAOYOUT
l>
C
o
.....
L.J
X
X
OLD OATA
NEW DATA
TUH/5676-28
ADC1225
cs
1
-b>_
crt> -
!6 74
Rii
INTR
ViR
READY OUT
+5Vo- STATUS
~~ATA
(OBo-OBI2)
TUH/5676-29
FIGURE 13
When using this method of conversion only one strobe is
necessary and the rising edge of WR/RD can be used to
read the current conversion results. These methods reduce
the throughput time of the conversion since the RD and WR
cycles are combined.
2. With the standard timing WR pulse width longer than the
conversion time a conversion is completed but the INTR will
never go low to signal the end of a conversion. The output
latches will be updated and valid information will be available when the RD cycle is accomplished.
CS
I
ViR
L-.J
L-.J
,
LJ,
LJ
,
,
,
,
I,,
,,,
Rii
INTR
READY OUT
DATA
(D80-0B7)
I
3. Tying CS and RD low continuously and strobing WR to
initiate a conversion will also yield valid data. The INTR will
never go low to signal the end of a conversion and the
digital outputs will always be enabled, so using INTR to
strobe the WR line for a continuous conversion cannot be
done with this part.
A simple stand-alone circuit can be accomplished by driving
WR with the inverse of the READY OUT signal using a simpie inverter as shown below.
I
,
,
,I
,
,
,
11
<
I
)
MOST
SIGNIFICANT
BYTE
I
.11
I
,
,
,
I,
Tc
"
11
(
)
LEAST
SIGNIFICANT
BYTE
FIGURE 14
3-233
TUH/5876-30
~ r-------------------------------------------------------------------------~
...
CIoI
CIoI
(J
C
~
...g
o
CIoI
c(
Functional Description (Continued)
through the output resistance of the analog Signal source.
This charge pumping action is worse for continuous conversions with the VIN( +) input voltage at full-scale. For continuous conversions with a 1 MHz clock frequency and the
VIN( +) input at 5V, the average input current is approximately 5 p.A. For this reason bypass capacitors should not be
used at the analog inputs for high resistance sources
(RSOURCE 100 0).
If input bypass capaCitors are necessary for noise filtering
and high source resistance is desirable to minimize capacitor
size, the detrimental effects of the voltage drop across this
input resistance, due to the average value of the input current, can be minimized with a full-scale adjustment while the
given source resistance and input bypass capacitor are both
in place. This is effective because the average value of the
input current is a linear function of the differential input voltage.
ADC1205
Case 1 would be the only one that would appy to the
ADC1205 since two RD strobes are necessary to retrieve
the 13 bits of information on the B bit data bus. Simultaneously strobing WR and RD low will enable the most significant byte on DBO-DB7 and start a conversion. Pulsing
WR/RD low before the end of this conversion will enable
the least significant byte of data on the outputs and restart a
conversion.
4_0 REFERENCE VOLTAGE
The voltage applied to the reference input of the converter
defines the voltage span of the analog inputs (the difference
between VIN(+) and VIN(-), over which 4096 positive output codes and 4096 negative output codes exist. The
A-to-D can be used in either ratiometric or absolute reference applications. VREF must be connected to a voltage
source capable of driving the reference input resistance
(typically 4 kO).
5.4 INPUT SOURCE RESISTANCE
Large values of source resistance where an input bypass
capaCitor is not used, will not cause errors as the input currents settle out prior to the comparison time. If a low pass
filter is required in the system, use a low valued series resistor (R,;; 100 0) for a passive RC section or add an op amp
RC active low pass filter. For low source resistance applica·
tions, (RSOURCE';;100 0) a 0.001 p.F bypass capaCitor at
the inputs will prevent pickup due to series lead inductance
of a long wire. A 100 0 series resistor can be used to isolate
this capacitor - both the Rand C are placed outside the
feedback loop - from the output of an op amp, if used.
In a ratiometric system, the analog input voltage is proportional to the voltage used for the AID reference. When this
voltage is the system power supply, the VREF pin can be
tied to Vee. This technique relaxes the stability requirement
of the system reference as the analog input and AID reference move together maintaining the same output code for a
given input condition.
For absolute accuracy, where the analog input varies between very specific voltage limits, the reference pin can be
biased with a time and temperature stable voltage source.
In general, the magnitude of the reference voltage will require an initial adjustment to null out full-scale errors.
5.5 NOISE
The leads to the analog inputs should be kept as short as
possible to minimize input noise coupling. Both noise and
undesired digital clock coupling to these inputs can cause
errors. Input filtering can be used to reduce the effects of
these sources, but careful note should be taken of sections
5.3 and 5.4 if this route is taken.
5.0 THE ANALOG INPUTS
5.1 DIFFERENTIAL VOLTAGE INPUTS AND COMMON
MODE REJECTION
The differential inputs of the ADC1225 and ADC1205 actually reduce the effects of common-mode input noise, i.e.,
signals common to both VIN(+) and VIN(-) inputs (60 Hz is
most typical). The time interval between sampling the" + "
and" -" input is 4 clock periods. Therefore, a change in the
common-mode voltage during this short time interval may
cause conversion errors. For a sinusoidal common-mode
Signal the error would be:
"
6.0 POWER SUPPLIES
Noise spikes on the Vee supply line can cause conversion
errors as the comparator will respond to this noise. Low
inductance tantalum capacitors of 1 p.F or greater are recommended for supply bypassing. Separate bypass caps
should be placed close to the DVcc and AVcc pins. If an
unregulatecj voltage source is available in the system, a separate LM340LAZ-5.0 voltage regulator for the A-to-D's Vee
(and other analog circuitry) will greatly reduce digital noise
on the supply "line.
4
VERROR(MAX) = VPEAK (2'IT fCM)fClK
where fCM is the frequency of the common-mode Signal,
VpEAK is its peak voltage value and fClK is the converter's
clock frequency. In most cases VERROR will not be significant. For a 60 Hz common-mode signal to generate a 'i4
LSB error (300 p.V) with the converter running at 1 MHz its
peak value would have to be 200mV.
7.0 ERRORS AND REFERENCE VOLTAGE
ADJUSTMENTS
7.1 ZERO ADJUST
The zero error of the AI D converter relates to the location
of the first riser of the transfer function and can be measured by grounding the VIN(-) input and applying a small
magnitude positive voltage to the VIN( +) input. Zero error is
the difference between the actual DC input voltage necessary to just cause an output digital code transition from all
zeroes to 0,0000,0000,0001 and the ideal % LSB value (%
LSB=0.61 mV for VREF=5 Vocl. Zero error can be adjusted as shown in Figure 15. VIN(+) is forced to 0.61 mV, and
VIN(-) is forced to OV. The potentiometer is adjusted until
the digital output code changes from all zeroes to
0,000,0000,0001.
5.2 INPUT CURRENT
Due to the sampling nature of the analog inputs, short duration spikes of current enter the" +" input and exit the" -"
input at the leading clock edges during the actual conversion. These currents decay rapidly and do not cause errors
as the internal comparator is strobed at the end of a clock
period.
5.3 INPUT BYPASS CAPACITORS
Bypass capaCitors at the inputs will average the current
spikes mentioned in 5.2 and cause a DC current to flow
3-234
.-------------------------------------------------------------------~~
C
Functional Description (Continued)
tude of the VREF input so that the output code is just changing from 0,1111,1111,1110 to 0,1111,1111,1111.
A simpler, although slightly less accurate, approach is to
ground VIN(+I and VIN(-I' and adjust for all zeros at the
output. Error will be well under % LSB if the adjustment is
done so that the potentiometer is "centered" within the
0,000,000 range. A positive voltage at the Vas input will
reduce the output code. The adjustment range is + 4 to
-30 LSB.
39K
Bipolar Inputs
Do the same procedure outlined above for the unipolar case
and then change the differential input voltage so that the
digital output code is Just changing from 1,0000,0000,0001
to 1,0000,0000,0000. Record the differential input voltage,
Vx. the ideal differential input voltage for that transition
should be;
0.61 mV
( -VF
+5V
+
YL)
8192
Calculate the difference between Vx and the ideal voltage;
d = Vx - (-VF
+
VF )
8192
Then apply a differential input voltage of;
TLIHI5676-11
(Vx -
FIGURE 15. Zero Adjust Circuit
%)
and adjust the magnitude of VREF so the digital output
code is just changing from 1,0000,0000,0001 to
1,0000,0000,0000. That will obtain the positive and negative
full-scale transition with symmetrical minimum error.
7.2 POSITIVE AND NEGATIVE FULL-SCALE
ADJUSTMENT
Unipolar Inputs
Apply a differential input voltage which is 1.5 LSB below the
desired analog full-scale voltage (VF) and adjust the magni-
Typical Applications
·Input must have some
current return path to
.-------4 YiNI+1
DVCC ~=:::::----,
signal ground
.
::.
.:.
'*
YiNI-1
AVec
V-
*"'*'"~~
T o.
1pF
CI
Wii
liIi
IRl'
READYDUT
OBI
TLlH/5676-12
3-235
o
....
N
o
U1
......
~
C
o
....
N
N
U1
~
....
(.)
Typical Applications (Continued)
Q
Protecting the Input
~
....~
Vec
(5 Voc)
(.)
Q
~Hf--"'---"'VREF OVcc
AVec
AOC1205
AOC1225
TLIH15676-19
Nole: II' resislors are 1 % metal film types
2) LF412 power
+ 10V and ground
3-237
Ordering Information
Temperature Range
Non-Linearity
I
I
- 40"C to
O"Cto 70"C
+ 85"C
0.012%
ADC1205BCJ-1
ADC1225BCJ-1
ADC1205BCJ
ADC1225BCJ
0.024%
ADC1205CCJ-1
ADC1225CCJ-1
ADC1205CCJ
ADC1225CCJ
J24A
J28A
J24A
J28A
Package Outline
3-238
r----------------------------------------------------------------,~
C
~National
(')
.....
I\)
.....
o
......
~ Semiconductor
~
c(')
.....
.....
.....
ADC12101 ADC1211 12-Bit CMOS AID Converters
I\)
General Description
The ADC1210, ADC1211 are low power, medium speed, 12bit successive approximation, analog-to-digital converters.
The devices are complete converters requiring only the application of a reference voltage and a clock for operation.
Included within the device are the successive approximation
logic, CMOS analog switches, precision laser trimmed thin
film R-2R ladder network and FET input comparator.
Both devices are available in military and industrial temperature ranges.
Features
• 12-bit resolution
• ± % LSB or ± 2 LSB nonlinearity
• Single + 5V to ± 15V supply range
• 100 JLs 12-bit, 30 JLs 10-bit conversion rate
• CMOS compatible outputs
• Bipolar or unipolar analog inputs
• 200 kO analog input impedance
The ADC121 a offers 12-bit resolution and 12-bit accuracy,
and the ADC1211 offers 12-bit resolution with 1a-bit accuracy. The inverted binary outputs are directly compatible with
CMOS logic. The ADC121 0, ADC1211 will operate over a
wide supply range, convert both bipolar and unipolar analog
inputs, and operate in either a continuous conversion mode
or logic-controlled START-STOP conversion mode. The devices are capable of making a 12-bit conversion in 100 JLs
typ, and can be connected to convert 10 bits in 30 JLs.
Block Diagram
22
CLOCK
START
CONVERSION
COMPLETE
COMPARATOR
OUTPUT
R26
200k
R25
200k
il28
R27
20k
20k
DIGITAL OUTPUTS
20
19
18
17
16
15
v-
TLlH/5677-1
Connection Diagram
Dual·ln·Line Package
ILSB'
2-12
'-""-';---'"
CLOCK
n COMPARATOR
Z-II
OUTPUT
n
.YIVREF)
,,,
21 GND
,-I
,-1
19 Rza
,-I
II HZS
20
"
Order Number ADC1210HD,
ADC1210HCD, ADC1211HD,
ADC1211HCD
See NS Package 0240
v-
"N
16 RZI
2_3'D
15 AZl
2- 2 11
14
~~:~::~OI~1
2 1 12
13 START (lei
IMS.)
'--_ _ _ _ _..J
TOP VIEW
TLlH/5677-2
3-239
•
.....
.....
.....
('II
g
c(
.....
Q
.....
.....
('II
o
~
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Maximum Reference Supply Voltage (V+)
16V
Maximum Negative Supply Voltage (V-)
-20V
V++0.3V
Voltage At Any Logic Pin
Analog Input Voltage
±15V
Maximum Digital Output Current
±10mA
Maximum Comparator Output Current
50 rnA
Comparator Output Short-Circuit Duration
5 Seconds
Power Dissipation
See Curves
Operating Temperature Range
ADC121 OHD, ADC1211 HD
- 55°C to + 125°C
ADC1210HCD, ADC1211 HCD
-25°C to +85°C
Storage Temperature Range
- 65°C to + 150"C
Lead Temperature (Soldering, 10 seconds)
300°C
ESD Susceptibility (Note 4)
TBDV
DC Electrical Characteristics (Notes 1 and 2)
Parameter
ADC1210
Conditions
Min
Resolution
Typ
ADC1211
Max
12
Full Scale Error
(Note 3)
fCLK=65 kHz, TA=25°C
fCLK=65 kHz
TA= 25°C, Unadjusted
Zero Scale Error
TA= 25°C, Unadjusted
Linearity Error
Min
Bits
±0.0183
±0.0366
±0.0488
%FS
%FS
0.20
0.50
%FS
0.20
0.50
%FS
±1/2
±1i2
LSB
Input Resistor Values
R27, R28
20
20
Input Resistor Values
R25, R26
200
200
Input Resistor Ratios
R25/R26, R27/R28
Logic "0" Input Current
VIN=OV
IOUT,;;-1 ",A
Logic "1" Output Voltage
LogiC "0" Output Voltage
Positive Supply Current
Negative Supply Current
kO
0.8
V
2
2
V
1
-1
1
-1
",A
9.2
9.2
",A
V
0.5
V
5
8
5
8
rnA
4
6
4
6
rnA
0.5
IOUT,;;1 ",A
V+ = 15V, fCLK=65 kHz,
TA=25°C
V- = -15V, TA=25°C
%
8
Logic "0" Input Voltage
VIN=10.24V
kO
0.8
8
Logic "1" Input Current
Max
12
Quantization Error
Logic "1" Input Voltage
Units
Typ
AC Electrical Characteristics TA = 25°C, (Notes 1 and 2)
Typ
Max
Conversion Time
Parameter
Conditions
100
200
Maximum Clock Frequency
130
65
Clock Pulse Width
Propagation Delay From Clock to Data Output
Min
100
Units
"'S
kHz
ns
50
t,,;;t,,;;10 ns
60
150
ns
t,,;;t,,;; 10 ns
60
150
ns
5
"'pFS
(QOtoQ11)
Propagation Delay from Clock to Conversion
Complete
Clock Rise and Fall Time
Input CapaCitance
10
Start Conversion Set-Up Time
30
ns
Note 1: Unless otherwise noted. these specifications apply for V+ =10.240V. V-= -15V. over the temperature range -S5'C to + 125"C for the ADCI210HD.
ADC1211 HD, and - 25'C to + 85'C for the ADC121 OHCD, ADC1211 HCD.
Nota 2: All typical values are for TA = 2S'C.
Nota 3: Unless otherwise noted, this specification applies over the temperature range - 25"C to + 85'C. Provision is made to adjust zero scale error to OV and fullscale to 10.237SV during testing. Standard linearity test circuit is shown in Figure Sa.
Note 4: Human body model, 100 pF discharged through a 1.5 kll resistor.
3-240
:t:O
Schematic Diagram
o
.....
.,.
y-
"
....o
I\)
,.
17
19
HZ5
ZODt
15
RZI
ZOOt
RZ7
ZOIl
);;
AZI
ZOIl
o
o
....
.........
I\)
COMPARATOR _'
. '~~"
.
OUTPUT
HI
1I0k
"24
"Ok
+ ___-..-....__+_
Vt"IVREF'·O:;"+-----
10
11
12
13
c
o.....
14
....
N
o
......
:r>
c
o.....
N
.....
.....
Oil
O'
OB
01
0'
05
O'
03
02
01
00
L--
cc---.J
~I--------CONVERSIONTIME'-----------Il
TUH/5677-B
FIGURE 1c. Timing Diagram for VIN = Zero Scale
11
Cp
PIN 2l
Oil
OlD
09
08
01
06
05
O'
03
02
01
00----1r-------------~
cc----l,L
, f..- - - - - - - -
CONVERSIONTlME---------I.
TL/H/5677-9
FIGURE 1d. Timing Diagram for VIN= -3.412SV (010101010101)
3·243
..-
TABLE 1. Pin Assignments and Explanations
C'I
.-
0
C
CC
......
Pin Number
Mnemonic
1-12
011-00
Digital (data) output pins. This information is a parallel 12-bit complemented binary representation of the converted analog signal. All data is valid when "Conversion Complete"
goes low. Logic levels are ground and V+.
0
C
CC
13
SC
Start Conversion is a logic input which causes synchronous reset of the successive
approximation register and initiates conversion. Logic levels are ground and V+.
14
CC
"Conversion Complete" is a digital output signal which indicates the status of the converter. When CC is high, conversion is taking place, when low conversion is completed.
Logic levels are ground and V+ .
15,16
R27, R2B
R27 and R2B are two application resistors connected to the comparator non-inverting
input. The resistors may be used in various modes of operation. Their nominal values are
20 kO each. See Applications section.
17
+IN
Non-inverting input of the analog comparator. This node is used in various configurations
and for compensation of the loop. See Applications section.
1B,19
R25, R26
R25 and R26 are two application resistors that are tied internally to the inverting input of
the comparator. Their nominal values are 200 kO each. See Applications section. The R2R ladder network will have the same temperature coefficient as these resistors.
20
V-
Negative supply voltage for bias of the analog comparator. Optionally may be grounded
or operated with voltages to -20V.
21
22
GND
V+(VREF)
Ground for both digital and analog signals.
V+ sets both maximum full scale and input and output logic levels.
23
CO
Comparator output.
24
Cp
Clock is an input which causes the successive approximation (shift) register to advance
through the conversion sequence. Logic levels are ground and V + .
CI
.C'I
.-
Function
10-bit conversion accuracy is taking place. The 02 output
should be "OR'd" with CONVERSION COMPLETE (CC) in
order to ensure that the register does not lock-up upon power turn-on.
2.0 APPLICATIONS
2.1
Power Supply Considerations and
Decoupllng
?"?"?"?l1y..y"Y,.y"?,,y,.I,~
Pin 22 is both the positive supply and voltage reference
input to the ADC1210, ADC1211. The magnitude of V+ determines the input logiC "1" threshold and the output voltage from the CMOS SAR. The device will operate over a
range of V+ from 5V to 15V. However, in order to preserve
12-bit accuracy, V+ should be well regulated (0.01%) and
isolated from external switching transients. It is therefore
recommended that pin 22 be decoupled with a 4.7 I£F tantalum capaCitor in parallel with a 0.1 I£F ceramic disc capacitor.
The V- supply (pin 20) provides negative bias for the FET
comparator. Although pin 20 may be grounded in some applications, it must be at least 2V more negative than the
most negative analog input signal. When a negative supply
is used, pin 20 should also be bypassed with 4.71£F in parallel with 0.1 I£F.
Grounding and circuit layout are extremely important in preserving 12-bit accuracy. The user is advised to employ separate digital and analog returns, and to make these PC
board traces as "heavy" as practical.
2.2
I
~II: I'"' ' ' '
ADe12n
00 01 OZ 03 04 05 01 Q7
oa
Q9 010 0:11
!' '.A' A'A' ATl' iA"A"(
NC
DIGITAL OUTPUTS
TL/H/5677-10
FIGURE 2. Short Cycling the ADC1211 to Improve
10-Bit Conversion Time (Continuous Conversion)
2.3 Logic Compatibility
The ADC1210, ADC1211 is intended to interface with
CMOS logiC levels: I.e., the logiC inputs and outputs are directly compatible with series 54C174C and CD4000 family
of logic components. The outputs of the ADC1210,
ADC1211 will not drive LPTTL, TTL or PMOS logic directly
without degrading accuracy. Various recommended interface techniques are shown in Figures 3 and 4.
2.4
Short Cycle for Improved Conversion
Time (Figure 2)
Operating Configurations
Several recommended operating configurations are shown
in Figure 5.
The ADC1210, ADC1211 counting sequence may be truncated to decrease conversion time. For example, when using the ADC1211, 2 clock intervals may be "saved" if
3-244
l>
C
Applications Information (Continued)
Y+I1OTD 15VI
o
....
....
o
VCC I5V}
1'1)
......
l>
C
o....
........
1'1)
DIGITAL OUTPUTS
nlOR5VCMoS
CDMPATIBLE
1/&MM14C901
ORMM74C902
TUH/5677-11
FIGURE 3. Interfacing an ADC1210, ADC1211 Running on V+
> Vee. Example: V+
= 10.24V, System Vee = 5V
VCC z '5V
y
15VJUl
DV
SYSTEM
CLOCK 0 -
--.k
011 ~
010 11
-[>-- f....l! 'p
09 10
o. •
01 •
O• .!.
MU74C8D1
on
MM74C9D2
on
-[>- f-ll.
I:
OK.
MM74C9DB
-¥
,
Sf
r
1I2RA1Z-1
1
'::"
I2RAU-
.JMS.
L.
:~~
ADCI21D.
ADe121!
MU74Cl14
0-
.
,........l.!L.
,
r
I
V+ 5V
----"
..
IOKN
DIGITAL
OUTPUTS
1
L.
_.J
o,~
o.~
" ce
o,i!...D2 .l..-
MM74C9D&
01.l..-
-
no .l.-
~
Vee
".
LSI
•:J~D.v'nSiD
COMPLETE
'Ii
1/8!;;;'4C9DB
TL/H/5677-12
FIGURE 4. Interfacing an ADC1210, ADC1211 Running on V+
< Vee. Example: V+
= 5V, Vee = 15V
puts must be stable logic "0"). Offset Null is accomplished
by then applying an analog input voltage equal to % LSB at
pins 18 and 19. R2 is adjusted until the LSB output flickers
equally between logic "I" and logic "0" (all other bits are
stable). In the circuit of Figure 6, the ADC1210, ADC1211 is
configured for Complementary Binary logic and the values
shown are for V+ = 10.240V, VFS = 10.2375V,
LSB = 2.5 mY.
2.5 Offset and Full Scale Adjust
A variety of techniques may be employed to adjust Offset
and Full Scale on the ADC1210, ADC1211. A straight·for·
ward Full Scale Adjust is to incrementally vary V+ (VREF) to
match the analog input voltage. A recommended technique
is shown in Figure 6. An LM199 and low drift op amp(e.g.,
the LH0044) are used to provide the precision reference.
The ADC1210, ADC1211 is put in the continuous convert
mode by shorting pins 13 and 14. An analog voltage equal
to VREF minus 1% LSB (10.23625V) is applied to pins 18
and 19, and Rl is adjusted until the LSB flickers equally
between logic "1" and logic "0" (all other out-
An alternate technique is shown in Figure 7. In this instance,
an LH0071 is used to provide the reference voltage. An
analog input voltage equal to VREF minus 1% LSB
(10.23625V) is applied to pins 18 and 19.
3-245
•
........
....
g
~
....
....
o
C'I
Applications Information (Continued)
CI
Ir -AOCIZtIl,ADC1Z11
----------,
C'I
'Ok
cc(
CLOCK PULSE
e,
srART
R
CONVERSION
COMPLETE
I
I
O/A AND SAR LOGIC
cc
lLs."~-r""""""T"...,r-r""""""T""'S.FI
141
~l"fo
RZ6
2A
2112
, • • • , •,
825
2R
lUl112
A28
"
II
.
A27
'
""
"
II
~;_~,,~~~~~~~~-J
DIGITAL
,-,
OUTPUTS
-::"
ANALOG
-::"
V'
tVREFI
INPUT
5VS:V+S:15V
OVS:VINS:V+
Logical "1"S:0.5V
Logical "0" "'V+
FIGURE 5a. Single Supply Configuration, Complementary Logic
I7nC;;;;'-A07,;;'; -
-
-
"
4=
~
-
-
----------,
I
CLOCk PUlSE
START
CONVERSION
COMPLETE
I
m
I
I
"
"
"
"I
D
Ie
13
DIAAN05ARlOGIC
2112
2- 12
V+=15.000V
V-=-15V
0s:VINS:1OV
Logical "1" ;"14V
Logical "0" s: 0.5V
,••
,
7
,
.
DIGITAL
OUTPUTS
'"~
RZS
'" '"
" "
lOll
1 ; ; " - - - 19-'1
i i - 16-'5
Ne
2-'
V
I
-- "
R.
""
R,
':"':-
-15V
ANALOG
INPUT
COMPA RATon
DUTPU
__ .J
~
-::"
,
I"
COMPARATOR
+
MS'
LS'
~J
II
t'--
"
" 'J.
II
-::"
TL/H/5677-14
FIGURE 5b. High Voltage CMOS Compatible, OV to 10V Input
V+=ID24I1V
r°C;;;O:AOcmI-------------- --l
22
I
I
CLOCK PULSE
START
CONVERSION
COMPLETE
"sc
«LSI
II
D
.
Z-IZ
,
R
D/A AND SAR LOGIC
.
+
7
2R
1011 1 2 - - -
R2I
COMPARATOR
OUTPUT
V
R27
20
...........-DIGITAL
OUTPUTS
"
"
-::"11
~1
,"',
ANALOG
INPUT
V+ =10.24V
-5.12VS:VINS: +5.12V
Logical "1"S:0.5V
Logical "0" "'10V
I"
T
I ,"...
__
J
;r- ia l;;- I;;- 1;;-"'.
"'0
2R
I
I
I
COMPARATOR
.sa
", , , •, , •
m
V·,".24V
t
'"
IO.
A,
"
. TUH/5677-15
FIGURE !ie. Bipolar Input, Complementary Logic
3-246
l:o
C
Applications Information (Continued)
....
....
(')
N
C)
.......
l:o
C
(')
....
N
........
CLOCK
I5V
.2
'-"NV_< ;:;k
-15V
-lSV
TLlH/5677-16
FIGURE 6. Offset and Full Scale Adjustment for Complementary Binary
Rl is adjusted until the LSB output flickers equally between
logic "1" and logic "0" (all other outputs must be a stable
logic "0"). For Offset Null, an analog voltage equal to 1/2
LSB (1.25 mV) is then applied to pins 18 and 19, and R2, is
adjusted until the LSB output flickers equally between logic
"1" and "0".
The circuit insures that in no case can the ADC121 0 make
an error in the Most Significant Bit (MSB) decision. Without
the circuit, it is possible for energy from the trailing edge of
an asynchronous START pulse to be coupled into the
ADC1210's comparator. If the analog input is near halfscale, the charge injected can force an error in the MSB
decision. The circuit allows one clock period for this energy
to dissipate before the decision is recorded.
INPUT VOLTAGE
IDVTD1D.2J75V)
I5V
2.7 ADC1210 CONVERSION AT 26 p's
-ISV
The ADC121 0 can run at 500 kHz clock frequency, or 12-bit
conversion time of 26 P.s (Figure 9). The comparator output
is clamped low until the successive approximation register
(SAR) is ready to strobe in the data at the rising edge of the
conversion clock. Comparator oscillation is suppressed and
kept from influencing the conversion decisions, eliminating
the need for the AC hysteresis circuit above clock frequency
of 65 kHz that is recommended.
CLOCK
VRlf
-I5V
TL/H/5677-17
" a"
CLOCK . . , - - - - -_ _ _ _..!:j
FIGURE 7. Offset and Full-Scale Adjustment
Technique Using LH0071
'v
In both techniques shown, adjusting the Full-Scale first and
then Offset minimizes adjustment interaction. At least one
iteration is recommended as a se/f-check.
V
""
MS,
ADCIZ1D
DIGITAL
• OUTPUT
COUT
2.6 START PULSE CONSIDERATIONS
21
To assure reliable conversion accuracy, the START (SC)
pulse applied to pin 13 of the ADC121 0 should be synchronized to the conversion clock. One simple way to do that is
the circuit shown in Figure 8. Note that once a conversion
cycle is initiated, the START signal cannot effect the conversion operation until it is completed.
.
,sa
TL/H/5677-18
FIGURE 9. Conversion at 26 p's
A complementary phased clock is required. The positive
phase is used to clock the converter SAR as is normally the
case. The same signal is buffered and inverted by the transistor. The open collector is wire·ORed to the output of the
comparator. During the first half of the clock cycle (50%
duty cycle), the comparator output is clamped and disabled,
though its internal operation is still in normal working order.
The last half cycle of the clock unci amps the comparator
output. Thus, the output is permitted to slew to the final logic
state just before the decision is logged into the SAR. The
MM74C906 buffer (or with two inverting buffers) provides
adequate propogation delay such that the comparator output data is held long enough to resolve any internal logic
setup time requirements.
C:1Dtll.-I~~=+...!!j:;--""""--""""'"
TLlH/5677-19
FIGURE 8. Synchronizing the START Pulse
3-247
~
r----------------------------------------------------------------------------------------------,
~
N
~
U
c
c
o
.....
N
.....
.....
•
3-249
~
,------------------------------------------------------------------------------------.
~
5
~National
~ ~ Semiconductor
.....
PRELIMINARY
~
~ ADC3511 3%-Digit Microprocessor Compatible AID
~
Converter
ADC3711 3314-Digit Microprocessor Compatible AID
Converter
General Description
The ADC3511 and ADC3711 (MM74C937, MM74C938-1)
monolithic AID converter circuits are manufactured using
standard complementary MOS (CMOS) technology. A pulse
modulation analog-to-digital conversion technique is used
and requires no external precision components. In addition,
this technique allows the use of a reference voltage that is
the same polarity as the input voltage.
One 5V (TTL) power supply is required. Operating with an
isolated supply allows the conversion of positive as well as
negative voltages. The sign of the input voltage is automatically determined and indicated on the sign pin. If the power
supply is not isolated, only one polarity of voltage may be
converted.
The conversion rate is set by an internal oscillator. The frequency of the oscillator can be set by an external RC network or the oscillator can be driven from an external frequency source. When using the external RC network, a
square wave output is available.
The ADC3511 and ADC3711 have been designed to provide addressed BCD data and are intended for use with
microprocessors and other digital systems. BCD digits are
selected on demand via 2 Digit Select (00,01) inputs. Digit
Select inputs are latched by a low-to-high transition on the
Digit Latch Enable (DLE) input and will remain latched as
long as OLE remains high. A start conversion input and a
conversion complete output are included on both the
ADC3511 and the ADC3711.
Features
•
•
•
•
•
•
•
•
•
•
•
•
Operates from single 5V supply
ADC3511 converts 0 to ±1999 counts
ADC3711 converts 0 to ± 3999 counts
Addressed BCD outputs
No external precision components necessary
Easily interfaced to microprocessors or other digital
systems
Medium speed-200 mslconversion
TTL compatible
Internal clock set with RC network or driven externally
Overflow indicated by hex "EEEE" output reading as
well as an overflow output
ADC3511 equivalent to MM74C937
ADC3711 equivalent to MM74C938-1
Applications
• Low cost analog-to-digital converter
• Eliminate analog multiplexing by using remote
AID converters
• Convert analog transducers (temperature, pressure, displacement, etc.) to digital transducers
Connection Diagram
Dual-In-Line Package
Vee
....!
U
~21
B.zG
ANALOG Vee ...l
a
22.2
vss
....!.
.!!.. 01
OVERFLOW....!.
!!.. 00
23
CONVERSION COMPLETE ...!
START CONVERSION
.!!. OLE
..1
.!!. fOUT
;l!- fiN
SIGN...!
.!!. VR"
VFlLTER...!
VINH.1!!.
.!.!... $WI
VIN!"...!.!
,am
Order Number ADC3511CCN
or ADC3711CCN
NS Package N24A
.!!. ANALOG GND
vn..!!
TOP VIEW
3-250
TL/H/5678-1
»
c
Absolute Maximum Ratings (Note 1)
o
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Voltage at Any Pin
Absolute Maximum Vee
Storage Temperature Range
-0.3VtoVee +0.3V
Operating Temperature Range (TA)
6.5V
-65'C to + 150'C
Lead Temp. (Soldering, 10 seconds)
260'C
ESD Susceptibility (Note 5)
TBDV
-40'Cto +85'C
Package Dissipation at T A = 25'C
Operating Vee Range
CAl
U1
....
....
......
»
c
oCAl
...............
500mW
4.5Vto 6.0V
DC Electrical Characteristics ADC3511CC,ADC3711CC
4.75V:>: Vee:>: 5.25V, -40'C:>:TA:>: + 85'C, unless otherwise specified.
Symbol
Parameter
VIN(l)
Logical "1" Input Voltage
(Except fiN)
VIN(O)
Logical "0" Input Voltage
(Except fiN)
VIN(l)
Conditions
Typ
(Note 2)
Min
Max
Units
V
Vee- 1.5
1.5
Logical "1" Input Voltage
V
V
Vee- 0.6
(fiN)
VIN(O)
Logical "0" Input Voltage
(fiN)
VOUT(l)
Logical "1" Output Voltage
(Except 20, 21, 22, 23)
10= 36O /LA
Vee- O.4
V
VOUT(l)
Logical "1 " Output Voltage
(20,21, 22, 23)
10= 36O /LA
Vee-1.0
V
VOUT(O)
Logical "0" Output Voltage
10=1.6mA
IIN(l)
Logical "1" Input Current
(SC, DLE, DO, D1)
VIN=Vee
IIN(O)
Logical "0" Input Current
(SC, DLE, DO, D1)
VIN=OV
Icc
Supply Current
All Outputs Open
0.6
0.005
-1.0
V
0.4
V
1.0
/LA
-0.005
/LA
5.0
0.5
mA
AC Electrical Characteristics ADC3511CC,ADC3711CC
Vee=5V; TA=25'C, CL =50 pF; tr =tl=20 ns; unless otherwise specified.
Symbol
Parameter
fose
Oscillator Frequency
fiN
Clock Frequency
feONv
Conversion Rate
tsepw
Start Conversion Pulse Width
tpdo, tpdl
Propagation Delay
DO, D1, to 20, 21, 22, 23
tpdO, tpdl
Propagation Delay
DLE to 20, 21, 22, 23
IsET.UP
Set-UpTime
DO, D1, to DLE
tPWDLE
Minimum Pulse Width
Digit Latch Enable (Low)
Conditions
Min
Typ
(Note 2)
Max
Units
640
kHz
0.6!RC
100
ADC3511CC
ADC3711CC
tHOLD=O ns
3-251
conversions! sec
conversions! sec
fIN/64,512
fIN!129,024
200
DLE=OV
Hz
DC
ns
2.0
5.0
/Ls
2.0
5.0
/Ls
100
200
ns
100
200
ns
•
~
~
.....
('I)
(.)
c
~
~
~
r-----------------------------------------------------------------------------------------------,
Converter Characteristics ADC3511CC, ADC3711CC 4.75 S:VccS: 5.25V; -40"CS:TAS: + 85'C,
fc=5 conv.lsec (ADC3511CC); 2.5 conv.lsec (ADC3711CC); unless otherwise specified.
Symbol
Conditions
Min'
Typ
(Note 2)
Max
Units
VIN=0-2V Full Scale
VIN = 0-200 mV Full Scale
-0.05
±0.025
+0.05
-1
-0.5
+1.0
+0
+3.0
-0
-5
±1
+0
+5
% of Full-Scale
(Note 3)
Counts
mV
(Note 4)
Counts
nA
Parameter
It)
('I)
Non-Linearity
(.)
cc(
Quantization Error
Offset Error
VIN=OV
Rollover Error
Analog Input Current
TA=25'C
Note 1: Absolute Maximum Ratings Indicate lim~s beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating condHions.
Note 2: All typical. are given for TA = 25'C.
Nole 3: For the ADC3511CC: full·scale=1999 counts; therefore 0.025% of full·scale='h count and 0.05% of full·scale=l count. For the ADC3711CC: full·
scale = 3999 counts; therefore 0.025% of full-scale= 1 count and 0.05% of full-scale = 2 count
Nole 4: For full-scale=2.000V: 1 mV=l count for the ADC3511CC; 1 mV=2 counts for the ADC3711CC.
Nole 5: Human body model. 100 pF discharged through a 1.50 resistor.
Block Diagram
AOC3511 3 %-Olglt AlO (0 AOC3711 3 %-Olglt A/O)
31121JlJ41·DIGIT
LATCH
"f-..
~
r--
-
STARTCONV
FREDIN
FREDOUT
Dlf-..I--"f-..
-
-
'" ..... 1 - - -
., .....
".....
B4--t1
DIGITAL TIMING
AND CONTROL
~.....
-
16:4
ROMBtO
MUX
DECODER
~
I-
102
I
-
~
---
_vss
"'-
.J:-
y
"
V
=== 1:4
DECOIIER
I
I
I
10'
COMPARATOR
TIMING
--/)0---+ "
rIr
'-- IJ"
MSD
101
lO.
"
--/)0---+ ,I
"".....
.....
....... 1 - - -
+
GNO
--
" .....
" .....
"-
V
>L
CZ z::&
1-0 OCt
0U
uu
...~
;J
-'
...>
"0
II:
it
~.
23 zZ ZI 20 Dl DO DlE
co
»
"0
'2.
5V
(;'
!.
1-'-IO I'F
1+r-1OVDC
..... I-~
ANALDG VCC
2°1--
Z3
ADC3511CC
(ADC3711 CCI
Vss
Dl
OVERFLOW
DO
DlE
c.:l
CDNVERSION
CDMPLETE
START
CONVERSION
01
0>
SIGN
'"
-,,1'\D!
'WC
~r
250pF
VIN(-)
SWI
VIN(+)
SW2
,..........
~
=y=0.471'F
NOTE 3
'!D!
-';.;0"
"'~'.J I~
1/
if
> 680
•
g>
I
I
I
a
:::I
1
I
~ I r" I- DmETI
I I ADJUST I
lOki
I : lOOk
I
I I
lN914 ~
~ I ~ >50k I
lN914~
: Z32 ±1%.
20'
I,'000 ±1%.
I..--
::::I
til
I
I
ANALOG
VFB
I
I
I
I
I
I
VREF
RJ
NOTE3-.-
GND
7.5k
'DUT
liN
VFlLTER ,
~~:I'~1-
2V REFERENCE, _
211-
22
0'
r.--- 1---,
VCC
L.
,_
}G ~
~}"'
1--,'-
f - - - f-.J
~
\\
~
,
L. ...... _.J
i> 22M
Note l:fl II resistors % watt. and
±5%. un 'ess otherwise specified.
Note 2: fl I capacitors± 10%.
Note 3: L.ow leakage capacitor.
Note 4: F:3
RIR2
= RI + R2 ±2SU.
GND
TLlH/S678-8
FIGURE 4. 3 %-Digit AID; + 1999 Counts, + 2.000 Volts Full Scale
(3 %-Diglt AID; + 3999 Counts, + 2.000 Volts Full Scale)
zz
II;~
a: &II
-I
~
II:
'<
....
~III "'....
'a
...
lI:~ii~ z ffi
~ ...... !! >
Cl)uuc.»
'"
0'
!!.
23 22 2' 20 01 DO OLE
0
»
tl
'a
r
1+
I- ~ Vcc
...... ANALOG VCC
23
AOC3511CC
(AOC3711CC)
OVERFLOW
~
UI
-..a
SIGN
2'~
j---
20 I---
I
I
I
Vss
DI
'OUT
...
.. 7..;.5~
OA~~ VFILTER
~~
250 pF
VREF
VIN(+)
'
VINH
SWI
VIN(+)
sm
r-- VFB
-~
T~·47"F
NOTE 3
... ~3
~Oo"
~
~
lOOk
II
Ij
- , T'OVDC
D)
1;5
:
~.
:::I
c:
~
I
I
I 232>1%.
II
0'
:l
o
- r - '5V DC
I
I
'> 680
lN914~
:}"G ~
·
20,
~},,'
.•
I1'000 "%:
"""JI' ~
ANALOG
~ -
I
I
51k
VINHr
0'
+ IOOQ,.F'
+ I,.F
I
DLE
'IN
NOTE 3
....
-""~~
.
2V REFERENCE. _
00
CONVERSION
COMPLETE
START
CONVERSION
C.:>
-
l~~
LM340·5
I-L-IO,.F
r- lOV oc
22
'2.
l' 11'. .
LM309
DR
.. --
L. __
IN914 ~
t
I
I
I
>- lOki
r- ~ omETI
I ADJUST I
I >'00k I
I I >
~50k
t I rt+:
L..
~-- ~.J
I
Note 1: All resistors % watt, and
±5%. unlE 55 otherwise specified.
Note 2: All capacitors±10%.
Note 3: LcIW leakage capacitor.
Note 4:
R~
R1R2
~ Rl + R2 ±2511.
I
f---'
22M
\\
~
TLlH/567B-6
FIGURE 5. 3 Y2-Diglt AID; ± 1999 Counts, ± 2.000 Volts Full Scale
(3 %-DigitA/D; ±3999 Counts, ±2.000 Volts Full Scale)
Ul&:>O"IU 9&:>0"
II
ADC3511/ ADC3711
....
.-'" ...
.- .... .
......
~
ZZ
i!~
",> >
CZ Z
Z
In
"e!.5'
Z3 ZZ Zl ZO 01 DO OLE
tl
l>
l'
lM3D9
DR
I
l.....a....l0pF
EE
w
VCC
-
2'
ANAlOGVCC
20
22
23
ADC3&I1CC
(AOC3711CCI
OVERFLOW
CONVERSION
COMPLETE
START
CONVERSION
Co)
ro
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CD
fllH-
NOTE
DA 3
51k
VINH
SIGN
ff---
VFllTER
I
I
I
Vss
01
00
OLE
7.5k
fOUT
~f-
2&8pF
fiN
VINH
j---
I
VIN(+I
SW2
VIN(+I
~
VF8
10:'"
./
=r~
NOTE 3
NOTE 5
200 _
II
Ij
IN914~
232 " "
50
~
L __
RI
~G
R2
~
IN914 ~
~ I
I
I
I
I I
t--- t--- t-.J
~
IE
0'
en
::l
g
a
:::l
<::
CD
.e
V. walt. and
± 5%, unless otherwi e specl·
Note I: All resistors
j.
lOki
~ I
'2.
~
I
1'020 '1"
'Y' '1 ~ ~
ANALOG
-r- I5VDC,
I
I
,
R3
180
I
SWI
+ IODD.F'
- , T'OVDC
I
VREF
SIk
-
I
I
I
I
lM~U Jl'~
+ I.F
2V REFERENCE, _
"
....
I
+.
t-OmETI
ADJUST
lOOk
I
I
I
&Ok
I
L. t - - . J
fled.
Note 2: All capacitors
Note 3: Low leakage
10%
c pacHor.
AIA2
Note 4: A3 - RI + F
±50n
Note 5: R4-900k ±I % for the
ADG3511ee. 200.0 mV Full·
Scale.
A4-400k±I'
for the
ADG3711 ee. 400.0 mV Full·
22M
Scale .
\\
~
TL/H/5678-7
FIGURE 6. 3 %-Digit AID; ± 1999 Counts, ± 200.0 mV Full Scale
(3 %-Digit AID; ± 3999 Counts, ± 400.0 mV Full-Scale)
r------------------------------------------------------------------.~
C
C
~National
Co)
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o.....
ADD3501 3% Digit DVM with
Multiplexed 7-Segment Output
General Description
Features
The ADD3501 monolithic DVM circuit is manufactured using
standard complementary MOS (CMOS) technology. A pulse
modulation analog-to-digital conversion technique is used
and requires no external precision components. In addition,
this technique allows the use of a reference voltage that is
the same polarity as the input voltage.
III Operates from single 5V supply
One 5V (TTL) power supply is required. Operating with an
isolated supply allows the conversion of positive as well as
negative voltages. The sign of the input voltage is automatically determined and output on the sign pin. If the power
supply is not isolated, only one polarity of voltage may be
converted.
The conversion rate is set by an internal oscillator. The frequency of the oscillator can be set by an external RC network or the oscillator can be driven from an external frequency source. When using the external RC network, a
square wave output is available. It is important to note that
great care has been taken to synchronize digit multiplexing
with the AID conversion timing to eliminate noise due to
power supply transients.
The ADD3501 has been deSigned to drive 7-segment multiplexed LED displays directly with the aid of external digit
buffers and segment resistors. Under condition of overrange, the overflow output will go high and the display will
read + OFL or - OFL, depending on whether the input voltage is positive or negative. In addition to this, the most significant digit is blanked when zero.
ID Converts OV to ± 1.999V
III Multiplexed 7-segment
III Drives segments directly
1\ No external preCision component necessary
III Accuracy specified over temperature
III Medium speed - 200ms/conversion
III Internal clock set with RC network or driven externally
III Overrange Indicated by +OFL or -OFL display read-
ing and OFLO output
III Analog inputs in applications shown can withstand
±200 Volts
II ADD3501 equivalent to MM74C935
Applications
III Low cost digital power supply readouts
IIiI Low cost digital multi meters
IJ
Low cost digital panel meters
iii Eliminate analog multiplexing by using remote AID con[J
verters
Convert analog transducers (temperature, pressure, displacement, etc.) to digital transducers
A start conversion input and a conversion complete output
are included on all 4 versions of this product.
Connection Diagram
Vee -
1
281- S,
ANALOG Vee -
2
271-
Sd- 3
Sf
261-S,
S,- 4
2SI-GNO
Sb -
5
241- DIGIT 1 IMSDI
S, -
6
OFLO -
7
231- DIGIT2
CONVERSION COMPLETE -
8
21
START CONVERSION _
9
20 t-- lOUT
ADD35Dl
221-- DIGIT 3
I-- DIGIT 41LSDI
SIGN -
10
19 roo liN
VFlLTER -
11
18 -
VINI-J -
12
17'- SWI
VINI+I_ IJ
161-- SW2
VFB -
VREF
'------_......
14
IS roo ANALOG GNO
Order Number ADD350tCCN
See NS Package Number N28B
3-259
TL/H/5681-1
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Voltage at Any Pin
-0.3VtoVcc +0.3V
Operating Temperature Range (TA)
-40'Cto +8S'C
ESD Susceptibility (Note 3)
TBDV
Package Dissipation at T A= 2S'C
derate at 8JA(MA)<)= 12S'C/Watt
above TA= 2S'C
Operating Vee Range
Absolute Maximum Vcc
Lead Temp. (Soldering, 10 seconds)
Storage Temperature Range
800mW
4.SVto 6.0V
6.5V
260"C
-6S'C to + 150'C
Electrical Characteristics ADD3S01
4.7SV ;;; Vee ;;; S.2SV, -40"C ;;; TA ;;; +8S'C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ(2)
Max
Units
1.5
V
0.4
V
0.4
V
V
VIN(l)
Logical "1" Input Voltage
VIN(O)
Logical "0" Input Voltage
VOUT(O)
Logical "0" Output Voltage
(All Digital Outputs except
Digit Outputs)
10=1.1 mA
VOUT(O)
Logical "0" Output Voltage
(Digit Outputs)
10=0.7mA
VOUT(l)
Logical "1" Output Voltage
(All Segment Outputs)
10=50 mA@TJ=2S'CVee=SV
10=30 mA@TJ=100'C
Vee- 1.6
Vee- 1.6
VOUT(l)
Logical "1" Output Voltage
(All Digital Outputs except
Segment Outputs)
10 = SOOIlA (Digit Outputs)
10= 360",A (Conv. Complete,
+ 1-, Oflo Outputs)
Vcc- 0.4
V
ISOURCE
Output Source Current
(Digit Outputs)
VOUT=1.0V
2.0
mA
IIN(l)
Logical "1" Input Current
(Start Conversion)
VIN=1.SV
IIN(O)
Logical "0" Input Current
(Start Conversion)
VIN=OV
Icc
Supply Current
Segments and Digits Open
fose
Oscillator Frequency
fiN
Clock Frequency
fc
Conversion Rate
fMUX
Digit Mux Rate
tBLANK
Inter Digit Blanking Time
Vcc- 1.5
V
V
Vcc- 1•3
Vcc- 1•3
1.0
-1.0
",A
",A
0.5
10
kHz
0.6/RC
100
rnA
640
kHz
f1N/64,S12
conv.lsec
flN/2S6
Hz
1/(32fMUX>
sec
Start Conversion Pulse Width
200
DC
ns
tscpw
Nate 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specHications do not apply when operating
the device beyond its specified operating condijions.
Nate 2: All typicals given for TA = 2S'C.
Nale 3: Human body model. 100 pF discharged through a 1.S kll resistor.
3·260
l>
Electrical Characteristics ADD3S01
C
C
tc=S conversions/second, 0·C';;TA,;;70·C, unless otherwise specified.
U1
Conditions
Min
Typ
Max
Units
VIN=0-2V Full Scale
VIN = 0 - 200mV Full Scale
-O.OS
-O.OS
±0.02S
±0.02S
+O.OS
+O.OS
%of
full scale
+0
counts
Parameter
Non-Linearity
w
o
......
-1
Quantization Error
-O.S
Offset Error, VIN = OV
+1.S
-0
Rollover Error
Analog Input Current
(VIN+, VIN-)
-S
TA=2S·C
±0.5
+3
mV
+0
counts
+S
nA
Block Diagram
ADD3501 3Y.-Digit DVM Block Diagram
3%·OIGI1
LATCH
AI~
•,rClrDlrA2r• 2~
,.--
r-LSD
-
--
.,.,C2 - D2-
..
DIGITAL TIMING
FREOIN_
co .......
AND CONTROL
--t>o--- ..
ROM
16;4
MUX
1
SEGMENT
DECODER
--[>0---."
--[>o-.s,
....
.....
f
101
"'-:::: ....
=f.
102
FREOOUT_
=f
::!'
10'
10.
DIGIT BLANK
r-COMPARATOR
TIMING
~
-
+
r--
i---
"'7
GNO ......... VSS
S,
.........
f--
'---
S,
r-t>---Sb
;---
c--c--r--r--r--C'c--0'_
r--r---- I
A'_
-....... MSO r--
STARTCDNV~
.....
.....
--'--
OVERFLOW
ROM
-
-
::::
"
DIGIT 1 (MSDI
DIGITZ
::::
:::.....
0lGI13
DiGIT 4 (LSDI
-OVERflOW
DIGITAL Yee
CONY COMPLETE
SIGN
'DO
..--C
0
ANALOG Vee
YFILTER
+V'N
~VREF
r --~
+
1
!WI
+ ....
~ rt-~
IES:
I .- I
I
-VIN
I
+
L_":..J
:LOG GNO
v..
TUH/5681-2
3-261
•
..C)
r.n
C")
C
C
.
In this mode the analog input is continuously converted and
the display is updated at a rate equal to 64,512 x 1/f1N.
The rising edge of the Conversion Complete output indicates that new information has been transferred from the
internal counter to the display latch. This information will
remain in the display latch until the next low-to-high transition of the Conversion Complete output. A logic "1" will be
maintained on the Conversion Complete output for a time
equal to 64X1/f1N.
Figure 3 gives the operation using the Start Conversion input. It is important to note that the Start Conversion input
and Conversion Complete output do not influence the actual
analog-to-digital conversion in any way.
Internally the ADD3501 is always continuously converting
the analog voltage present at its inputs. The Start Conversion input is used to control the transfer of information from
the internal counter to the display latch.
Co)
U1
o
.....
An RS latch on the Start Conversion input allows a broad
range of input pulse widths to be used on this signal. As
shown in Figure 3, the Conversion Complete output goes to
a logic "0" on the riSing edge of the Start Conversion pulse
and goes to a logic "1" some time later when the new conversion is transferred from the internal counter to the display latch. Since the Start Conversion pulse can occur at
any time during the conversion cycle, the amount of time
from Start Conversion to Conversion Complete will vary.
The maximum time is 64,512X1/flN and the minimum time
is 256 X 1/f1N.
Timing Waveforms
fIN
lUlI----------
r:
1".-1----------
64,512 x 1/f1N
..
~I
64,DDDx 1/f1N - - - - - - - - ;..
r--
CONVERSION CYCLE - - - - - - - - - - - - - - - - - - - - . ; .
(INTERNAL SIGNAL)
L.-..J
-1---------- 64,256 x 1/f1N ---------+~I-.\
CONVERSION
COMPLETE
1
r
1
NEW
CONVERSION
STArTS
I
r- 64/f1N
n____
CONVERSION
ENOS
I
TLlH/5681-4
Figure 2. Conversion Cycle Timing Diagram for Free Running Operation
----------"IU
CONVERSION CYCLE
(INTERNAL SIGNAill
r-,! _ _
START CONVERSION,:.·_..
n
..I
i
u
II
.-~
I._ _ _ _
!_..
! ________________
...1"_-_-_-_-_-_-_. . __-'
CONVERSION
COMPLETE - - - - - - - -
TL/H/5681-5
Figure 3. Conversion Cycle Timing Diagram Operating with Start Conversion Input
3-263
-o .-----------------------------------------------------------------------------1
II)
C")
c
c
cc
Applications
SYSTEM DESIGN CONSIDERATIONS
Perhaps the most important thing to consider when designing a system using the ADD3501 is. power supply noise on
the Vee and ground lines. Because Ii single power supply is
used and currents in the 300 rnA range are being switched,
good circuit layout techniques cannot be overemphasized.
Great care has been exercised in the design of the
ADD3501 to minimize these problems but poor printed circuit layout can negate these features.
Figures 4, 5, and 6 show schematics of DVM systems. An
attempt has been made to show, on these schematics, the
proper distribution for ground and Vee. To help isolate digital and analog portions of the circuit, the analog Vee and
ground have been separated from the digital Vee and
ground. Care must be taken to eliminate high current from
flowing in the analog Vee and ground wires. The most effective method of accomplishing this is to use a single ground
point and a single Vee point where all wires are brought
together. In addition to this the conductors must be of sufficient size to prevent significant voltage drops.
To prevent switching noise from causing jitter problems, a
voltage regulator with good high frequency response is necessary. The LM309 and the LM340-5 voltage regulators
both function well and are shown in Figures 4, 5, and 6.
Adding more filtering than is shown will in general increase
the jitter rather than decrease it. The most important characteristic of transients on the Vee line is the duration of the
transient and not its amplitude.
Figure 4 shows a DPM system which converts OV to 1.999V
operating from a non-isolated power supply. In this configuration the sign output could be + (logic "I ") or - (logic
"0") and it should be ignored. Higher voltages could be converted by placing a fixed divider on the input; lower voltages
could be converted by placing a fixed divider on the feedback, as shown in Figure 6.
Figures 5 and 6 show systems operating with an isolated
supply that will convert positive and negative inputs. 60 Hz
common mode input becomes a problem in this configuration and a transformer with an electrostatic shield between
primary and secondary windings is shown. The necessity for
using a shielded transformer depends on the performance
requirements and the actual application.
The filter capacitors connected to VFB (pin 14) and VFLT
(pin 11) should be low leakage. In the application examples
shown every 1.0nA of leakage current will cause 0.1 mV error (1.0Xl0- 9 AX100kO=0.1mVj.lf the leakage current in
both capacitors is exactly the same no error will result since
the source impedances driving them are matched.
3-264
Q,,-, '=1
NSB5388
Jrio~X)
,
8-45n
r--
f::/~
--;:j:jJ, 0 Lll LlO I F
I
IlM309
LM~O.5
Ir I
I
POWERGND,----------------------JL---~L-Jl~1-~~~~~~~~
~~~=!
~
I
!
L_____ J
'"~
I
U1
1
22M "
I
r--+---,:200n~R'
15
~S;
O~
fl617
~
~
N
-
II
I
100k
ADD3501
OFFSET
ADJUST (5)
SIGNAL
~
!
n
c
:>:>----------------+---l----L--~J
Jij
II.'
O.41
131
<
~
<
2
1:
<
Z
I
~
~
1i4J13J12rf'o:,.I,"
L----------J.!-T....J
n~
c,"
"
~n
c
§~
< ...
""
I' 10
0
"
131
~
16
5
n
14
'3
~
12
~
l'
.
lOOk
~
~)
~
Tl~
TLlH/5681-6
NOTES:
1. ALL RESISTORS
Y. WATT
± 5% UNLESS OTHERWISE
SPECIFIED.
2. ALL CAPACITORS ± 10%.
3. LOW LEAKAGE CAPACITOR REQUIRED.
4. R,R2 ~R3±25n
R,+R2
Figure 4. 3'J.-Digit DPM,
+ 1.999 Volts Full Scale
~oseaa'd
iii
ADD3501
n
NSB53BB
Ul
N
'"'"
ADD3501
GUARD
VI·'
OVT [)! 1.999Y
NOTES:
vI-I
1. ALL RESISTORS
_
'f. WAn +
5% UNLESS 0 THERWISE
SPECIFIED.
2. ALL CAPACITORS ± 10%.
3. LOW LEAKAGE CAPACITOR REQUIRED.
4. RR1R2
1+ R2
Figure 5. 31jz-Oigit OPM,
± 1.999 Volts Full Scale
~R3±25n
TL/H/5681-7
non
r
,-"..
31 ~
NSB5388
r--
::T IcgJll-II-II-/~
~/O/~!O.~
1I1I
lM309
DR
lMJ40-5
I,
.2500
-,'
TISVDC
r---
17
...
c.:>
'"
~
c
;Ok
150k
~
m
.. OFFSET
,...--J ADJUST
lOOk
GUARD
'Ok 01%
_!.
ADD3501
»____---l
l;
n
~
0
;;
c
z
~
c
C
I:
!::;
z
n~
~
0,.
z~
c~
I" I" I" pI 1'0 I'
"
~n
§~
~
Is
j,
c
n
[6
g
E I' 1 I' l'
3
O.41~F
)3)
VI')
~
d
...l! 10~F
0-
10VDC
NOTES:
1. ALL RESISTORS
10011. !...Ol%
V(-)
'14 WAn ± 5% UNLESS OTHERWISE
SPECIFIED.
2. ALL CAPACITORS ± 10%.
,
3. LOW LEAKAGE CAPACITOR REQUIRED.
4. R,R2 ~R3±25!l
R,+R2
TLlH/568'-8
Figure 6. 3'h-Digit DVM, Four Decade, ± O.2V, ± 2V, ± 20V and ± 200V Full Scale
~os£aa\f
iii
~
re
r------------------------------------------------------------------------------------,
E ~National
5i! ~ Semiconductor
ADD3701 3% Digit DVM with Multiplexed 7-Segment
Output
General Description
Features
The ADD3701 (MM74C936-1) monolithic DVM circuit is
manufactured using standard complementary MOS (CMOS)
technology. A pulse modulation analog-to-digital conversion
technique is used and requires no external precision components. In addition, this technique allows the use of a reference voltage that is the same polarity as the input voltage.
•
•
•
•
•
•
•
•
•
One 5V (TTL) power supply is required. Operating with an
isolated supply allows the conversion of positive as well as
negative voltages. The sign of the input voltage is automatically determined and output on the sign pin. If the power
supply is not isolated, only one polarity of voltage may be
converted.
The conversion rate is set by an internal oscillator. The frequency of the oscillator can be set by an external RC network or the oscillator can be driven from an external frequency source. When using the external RC network, a
square wave output is available. It is important to note that
great care has been taken to synchronize digit multiplexing
with the AID conversion timing to eliminate noise due to
power supply transients.
The ADD3701 has been deSigned to drive 7-segment multiplexed LED displays directly with the aid of external digit
buffers and segment resistors. Under condition of overrange, the overflow output will go high and the display will
read + OFL or -OFL, depending on whether the input voltage is positive or negative. In addition to this, the most significant digit is blanked when zero.
Operates from single 5V supply
Converts 0 to ±3999 counts
Multiplexed 7-segment
Drives segments directly
No external precision components necessary
Accuracy specified over temperature
Medium speed - 400 ms/conversion
Internal clock set with RC network or driven externally
Overrange indicated by +OFL or -OFL display reading and OFLO output
• Analog inputs in applications shown can withstand
±200 Volts
• ADD3701 equivalent to MM74C936-1
Applications
•
•
•
•
Low cost digital power supply readouts
Low cost digital multi meters
Low cost digital panel meters
Eliminate analog multiplexing by using remote AID converters
• Convert analog transducers (temperature, pressure, displacement, etc.) to digital transducers
• Indicators and displays requiring readout up to 3999
counts
A start conversion input and a conversion complete output
are included.
Connection Diagram
VCC- I
ANALOG VCC -
28~S.
2
27I--St
Sd- 3
261--Sg
s,,-
4
25 t--GND
Sb- 5
s.,-
241--01GIT I (MSO)
6
23 t--DIGITZ
OFLO- 7
CONVERSION COMPLETE -
8
START CONVERSION -
8
22 t--0IGIT 3
ADD3701
21 -
OIGIT4 (LSD)
20 -fOUT
SIGN- 10
IS-fiN
VFILTER- II
18 -VREF
17 -SWI
18 -swz
VIN(-)- 12
VIN(+)- 13
VFB- 14
15 -ANALOG GNO
TUH/5682-1
Order Number ADD3701CCN
See NS Package Number N28B
3-268
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Voltage at Any Pin except
Start Conversion
-0.3Vto Vcc+0.3V
Voltage at Start Conversion
-0.3Vto + 15.0V
ESD Susceptibility (Note 5)
TBDV
Operating Temperature Range (TA)
Package Dissipation at TA = 25·C
Operating Vcc Range
Absolute Maximum Vcc
Lead Temp. (Soldering, 10 seconds)
Storage Temperature Range
- 40·C to + 85·C
800mW
4.5Vt06.0V
6.5V
260·C
-65·C to + 150·C
Electrical Characteristics
4.75V,,;Vcc,,;5.25V, -40·C,,;TA"; + 85·C, unless otherwise specified.
Parameter
VIN(1)
Logical "1" Input Voltage
VIN(O)
Logical "0" Input Voltage
VOUT(O)
Logical "0" Output Voltage
(Ali Digital Outputs Except
Digital Outputs)
VOUT(O)
Conditions
Min
Typ2
Max
Units
V
VCC- 1.5
1.5
V
10=1.1 mA
0.4
V
Logical "0" Output Voltage
(Digit Outputs)
10=0.7mA
0.4
V
VOUT(1)
Logical "1 " Output Voltage
(Ali Segment Outputs)
10=50 mA@TJ=25·CVcc=5V
10=30 mA@TJ=100·C
Vcc- 1.6
Vcc- 1.6
VOUT(1)
Logical "1" Output Voltage
(Ali Digital Outputs Except
Segment Outputs)
10 = 500 p.A (Digit Outputs)
10=360 p.A (Conv. Complete,
+ /-, OFLO Outputs)
Vcc- 0.4
V
ISOURCE
Output Source Current
(Digital Outputs)
VOUT=1.0V
2.0
mA
IIN(1)
Logical "1" Input Current
(Start Conversion)
VIN=15V
IIN(O)
Logical "0" Input Current
(Start Conversion)
VIN=OV
Icc
Supply Current
Segments and Digits Open
fosc
Oscillator Frequency
fiN
Clock Frequency
fc
Conversion Rate
fMUX
Digit Mux Rate
tSLANK
Inter Digit Blanking Time
V
V
Vcc- 1.3
Vcc- 1.3
1.0
-1.0
p.A
p.A
0.5
10
0.6/RC
100
640
f1N/129,024
rnA
kHz
kHz
conv.lsec
flN/512
Hz
1/(32fMUxl
seconds
ns
Start Conversion Pulse Width
200
DC
tscPW
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All typicals given for TA = 25'C.
Note 3: Full scaie=4000 counts; therefore 0.025% of full scale = 1 count and 0.05% of full scale = 2 counts.
Note 4: For 2.000 Volts full scale, 1 mV = 2 counts.
Note 5: Human body model, 100 pF discharged through a 1.5 kG resistor.
3-269
•
.....
~
CO)
Q
Q
-~
-"
....
-r
ID4
FREDDUT_
4>-1,
........
---
-
.or.0 f.-
DIGITAL TIMING
FREOIN_
LSD
r---
---
......
I,
Sf
It
DIGIT' eMSDI
0lOlT2
DIGlTl
DIGIT 4 (LSDI
ovERFLOW
DIGITAL Vee
CONY COMPLETE
'00
ANALOG Vee
YFILTER
+YIN
-VIN
.e
-:-1
lJ..iii
I ::: 1
JIgT
1
1
SIGN
~VREF
D
sw,
i'...........
.....
CD"ARATO~
0
-~ ~
1£:l06&NO
L_:....J
VfB
TL/H/5682-2
3-270
»
c
Theory of Operation
A schematic for the analog loop is shown in Figure 1. The
output of SW1 is either at VREF or zero volts, depending on
the state of the D flip-flop. If Q is at a high level,
VOUT=VREF and if Q is at a low level VOUT=OV. This voltage is then applied to the low pass filter comprised of R1
and C1. The output of this filter, VFB, is connected to the
negative input of the comparator, where it is compared to
the analog input voltage, VIN. The output of the comparator
is connected to the D input of the D flip-flop. Information is
then transferred from the D input to the Q and Q outputs on
the positive edge of clock. This loop forms an oscillator
whose duty cycle is precisely related to the analog input
voltage, VIN.
An example will demonstrate this relationship. Assume the
input voltage is equal to 0.500 V. If the Q output of the D flipflop is high then VOUT will equal VREF (2.000 V) and VFB will
charge toward 2 V with a time constant equal to R1Cl. At
some time VFB will exceed 0.500 V and the comparator
output will switch to OV. At the next clock rising edge the Q
output of the D flip-flop will switch to ground, causing VOUT
to switch to OV. At this time VFB will start discharging toward
OV with a time constant R1Cj. When VFB is less than 0.5 V
the comparator output will switch high. On the rising edge of
the next clock the Q output of the D flip-flop will switch high
and the process will repeat. There exists at the output of
SW1 a square wave pulse train with positive amplitude VREF
and negative amplitude OV.
The lowpass filter will pass the DC value and then:
VFB = VREF (duty cycle)
Since the closed loop system will always force VFB to equal
VIN, we can then say that:
c
.....
Q
Co)
.....
VIN=VFB=VREF (duty cycle)
or
VVIN = (duty cycle)
REF
The duty cycle is logically ANDed with the input frequency
fiN. The resultant frequency f equals:
f= (duty cycle) x (clock)
Frequency f is accumulated by counter no. 1 for a time determined by counter no. 2. The count contained in counter
no. 1 is then:
f
(duty cycle) x (clock)
(clock)/N
(count) (clock)1N
= VIN xN
VREF
For the ADD3701 N = 4000.
The DC value of this pulse train is:
VOUT=VREF
tON
toN+tOFF
VREF (duty cycle)
Schematic Diagram
•
liN 0--""_01
RESET
TUH/56B2-3
VIN~VFB~VREFX(duly
cycle)
I ~ (duty cycle) X liN
Count in Counter No.1
I
liNIN
(duly cycle) XIIN
liNIN
VIN
VREF XN
FIGURE 1. Analog Loop Schematic Pulse Modulation AID Converter
3-271
General Information
The timing diagram, shown in Figure 2, gives operation for
the free running mode. Free running operation is obtained
by connecting the Start Conversion input to logic "1" (Vee).
In this mode the analog input is continuously converted and
the display is updated at a rate equal to 129,024 X 1/f1N.
Internally the ADD3701 is always continuously converting
the analog voltage present at its input. The Start Conversion
input is used to control the transfer of information from the
internal counter to the display latch.
An RS latch on the Start Conversion input allows a broad
range of input pulse widths to be used on this signal. As
shown in Figure 3, the Conversion Complete output goes to
a logic "0" on the rising edge of the Start Conversion pulse
and goes to a logic "1" some time later when the new conversion is transferred from the internal counter to the display latch. Since the Start Conversion pulse can occur at
any time during the conversion cycle, the amount of time
from Start Conversion to Conversion Complete will vary.
The maximum time is 129,024 x 1IfIN and the minimum time
is 512X1/f1N.
The rising edge of the Conversion Complete output indicates that new information has been transferred from the
internal counter to the display latch. This information will
remain in the display latch until the next low-to-high transition of the Conversion Complete output. A logic "1" will be
maintained on the Conversion Complete output for a time
equal to 128 x 1/f1N.
Figure 3 gives the operation using the Start Conversion input. It is important to note that the Start Conversion input
and Conversion Complete output do not influence the actual
analog-to-digital conversion in any way.
Timing Waveforms
fiN
.nn.
r:
>---------129.024. 1I11N
I
100·->---------128.000. lIf I N - - - - - - "
WL~l~~~r~,~~~~,
-------------------iur
L4>---------128.512.
l/IIN-------'~1-I I
r-128/IIN
CONVERSION
COMPLETE
t
1
NEW
CONVERSION
STARTS
CONVERSION
ENDS
TL/H/5682-4
FIGURE 2. Conversion Cycle Timing Diagram for Free Running Operation
r--------...,U
CONVERSION CYCLE
(INTERNAL SIGNAill
,.-,
n
i
J..r_-_-_-_-_-_-..~ __...
START CONVERSION,.'_'___-,
u
.-,
L _ _.....i,I.....i,I_ _ _ _ _ _ _ _ _ _ _ _ _ __
CONVERSION
COMPLETE --------
FIGURE 3. Conversion Cycle Timing
TL/H/5882-5
Dlagr~m
3-272
Operating with Start Conversion Input
:s:O
Applications
o
Co)
......
SYSTEM DESIGN CONSIDERATIONS
Perhaps the most important thing to consider when designing a system using the ADD3701 is power supply noise on
the Vee and ground lines. Because a single power supply is
used and currents in the 300 mA range are being switched,
good circuit layout techniques cannot be overemphasized.
Great care has been exercised in the design of the
ADD3701 to minimize these problems but poor printed circuit layout can negate these features.
Figures 4, 5, and 6 show schematics of DVM systems. An
attempt has been made to show, on these schematics, the
proper distribution for ground and Vee. To help isolate digital and analog portions of the circuit, the analog Vee and
ground have been separated from the digital Vee and
ground. Care must be taken to eliminate high current from
flowing in the analog Vee and ground wires. The most effective method of accomplishing this is to use a single ground
point and a single Vee pOint where all wires are brought
together. In addition to this the conductors must be of sufficient size to prevent significant voltage drops.
To prevent switching noise from causing jitter problems, a
voltage regulator with good high frequency response is necessary. The LM309 and the LM340-5 voltage regulators all
function well and are shown in Figures 4, 5, and 6. Adding
more filtering than is shown will in general increase the jitter
rather than decrease it.
The most important characteristics of transients on the Vee
line is the duration of the transient and not its amplitude.
....o
Figure 4 shows a DPM system which converts 0 to + 3.999
counts operating from a non-isolated power supply. In this
configuration the sign output could be + (logic "1") or (logic "0") and it should be ignored. Higher voltages could
be converted by placing a fixed divider on the input; lower
voltages could be converted by placing a fixed divider on
the feedback, as shown in Figure 5.
Figures 5 and 6 show systems operating with an isolated
supply that will convert positive and negative inputs. 60 Hz
common mode input becomes a problem in this configuration and a transformer with an electrostatic shield between
primary and secondary windings is shown. The necessity for
using a shielded transformer depends on the performance
requirements and the actual application.
The filter capacitors connected to VFB (pin 14) and VFLT
(pin 11) should be low leakage. In the application examples
shown every 1.0 nA of leakage current will cause 0.1 mV
error (1.0X1O- 9A x 100 kO=0.1 mY). If the leakage current in both capacitors is exactly the same no error will result since the source impedances driving them are matched.
•
3-273
ADD3701
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TL/H/5682-6
NOTES.
+1 .... V
1. ALL RESISTORS
% WATT ± 5% UNLESS OTHERWISE SPECIFIED
2. ALL CAPACITORS ± 10%
3. LOW LEAKAGE CAPACITOR REQUIRED.
R,R2
4. R, + R2
Figure 4. 30/0-0igital OPM,
+ 3.999 Count Full Scale
~ R3 ±251l
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NOTES:
oV TO UIIV
1. ALL RESISTORS
(0·3.1•• CoUNTSI
Y. WATT
±5% UNLESS OTHERWISE SPECIFIED
2. ALL CAPACITORS ±10%.
TL/H/5682-7
3. LOW LEAKAGE CAPACITOR REQUIRED.
4. R,R2
R, +R2 ~R3±25n.
Figure 5. 3%-Oigit OPM, ± 3.999 Counts Full Scale
~Ol£aa\f
iii
ADD3701
B-45n
Co>
~
Ol
ADD3701
GUARD
IMai1%
V{+)
V!-I
2. ALL CAPACITORS ± 10%.
3. LOW LEAKAGE CAPACITOR REQUIRED.
R,R2
4. R,+ R2 ~R3±25!l.
Figure 6. 3%-Digit DVM, Four Decade,
± O.4V, ± 4V, ± 40V, and ± 400V Full Scale
TLlH/5662-6
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300k
DISPLAY 9.999 WHEN OVERFLOWED.
ALL DIGITS CAN ALSO BE BLANKED AT
OVERFLOW BY TYING OFL TO B1 ON THE
CD4543s.
Figure 7. ADD3701 Driving Liquid Crystal Display
3-277
TL/H/5682-9
~
oII)
N
~National
c ~ Semiconductor
.....
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II)
N
:iii
DM2502/DM2502C, DM2503/DM2503C, DM2504/DM2504C
c Successive Approximation Registers
.....
u
C")
o
General Description
Features
:iii
The DM2502, DM2503 and DM2504 are 8-bit and 12-bit
TTL registers designed for use in successive approximation
AID converters. These devices contain all the logic and
control circuits necessary (in combination with a Df A converter) to perform successive approximation analog-to-digital conversions.
U
N
The DM2502 has 8 bits with serial capability and is not expandable.
N
The DM2503 has 8 bits and is expandable without serial
capability.
• Complete logic for successive approximation AID converters
• 8-bit and 12-bit registers
• Capable of short cycle or expanded operation
• Continuous or start-stop operation
• Compatible with Df A converters using any logic code
• Active low or active high logiC outputs
• Use as general purpose serial-to-parallel converter or
ring counter
II)
N
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c
The DM2504 has 12 bits with serial capability and expandability.
All three devices are available in ceramic DIP and molded
Epoxy-B DIPs. The DM2502, DM2503 and DM2504 operate
over - 55'C to + 125'C; the DM2502C, DM2503C and
DM2504C operate over O'C to + 70'C.
Connection Diagrams
Dual-In-Llne Package
Q7
15
07
14
06
13
05
12
Dual-In-Line Package
11
vcc 011 NC all 010 09 OB
CP
04
10
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124
9
(DM2502) Occ
DO
(OM2503)
3
QO
4
01
5
02
6
03
22
21
20
19
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17
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5
15
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4
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01
6
02
7
8
9
03 04
05
10
Ne
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TLlF/6612-2
E
TUF/6612-1
Order Number DM2504J or DM2504CN
See NS Package Number J24A or N24A
Order Number DM2502J, DM2503J, DM2502CN or
DM2503CN
See NS Package Number J16A or N16A
See the LS/S/TTL Logic Databook for Complete Specifications
3-278
r
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.....
~National
(,,)
.....
»
.....
r
:s::
.....
.....
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~ Semiconductor
LM131A/LM131, LM231A/LM231, LM331A/LM331
Precision Voltage-to-Frequency Converters
(,,)
.....
(,,)
General Description
The LM131/LM231/LM331 family of voltage-to-frequency
converters are ideally suited for use in simple low-cost circuits for analog-to-digital conversion, precision frequencyto-voltage conversion, long-term integration, linear frequency modulation or demodulation, and many other functions.
The output when used as a voltage-to-frequency converter
is a pulse train at a frequency precisely proportional to the
appiied input voltage. Thus, it provides all the inherent advantages of the voltage-to-frequency conversion techniques, and is easy to apply in all standard voltage-to-frequency converter applications. Further, the LM131A1
LM231A1LM331A attains a new high level of accuracy versus temperature which could only be attained with expensive voltage-to-frequency modules. Additionally the LM131
is ideally suited for use in digital systems at low power supply voltages and can provide low-cost analog-to-digital conversion in microprocessor-controlled systems. And, the frequency from a battery powered voltage-to-frequency converter can be easily channeled through a simple photoisolator to provide isolation against high common mode levels.
The LM131/LM231/LM331 utilizes a new temperaturecompensated band-gap reference circuit, to provide excellent accuracy over the full operating temperature range, at
,power supplies as low as 4.0V. The precision timer circuit
has low bias currents without degrading the quick response
necessary for 100 kHz voltage-to-frequency conversion.
And the output is capable of driving 3 TIL loads, or a high
voltage output up to 40V, yet is short-circuit-proof against
Vee·
~
r
:s::
~
.....
.....
r
:s::
(,,)
Features
• Guaranteed linearity 0.01 % max
• Improved performance in existing voltage-to-frequency
conversion applications
• Split or single supply operation
• Operates on single 5V supply
• Pulse output compatible with all logic forms
• Excellent temperature stability, ± 50 ppml'C max
• Low power dissipation, 15 mW typical at 5V
• Wide dynamic range, 100 dB min at 10kHz full scale
frequency
• Wide range of full scale frequency, 1 Hz to 100 kHz
(,,)
.....
»
.....
r
:s::
(,,)
(,,)
.....
• Low cost
Typical Applications
•
12k±1%*
}.
-VS
(OPTIONAL)
OFFSET ADJUST
TL/H/5680-1
·Use stable components with low temperature coefficients. See Typical Applications section.
"O.I"F or lfLF, Saa "Principlas of Operation."
FIGURE 1. Simple Stand-Alone Voltage-to-Frequency Converter
with ± 0.03% Typical Linearity (f = 10 Hz to 11 kHz)
3-279
....
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C')
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==
.....
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C')
N
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==
.....
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
Output Short Circuit to Ground
Output Short Circuit to Vee
Input Voltage
LM131A1LM131
40V
Continuous
Continuous
-0.2Vto +Vs
TMIN
TMAX
O·Cto +70·C
670mW
1S0·C/W
S70mW
1S0·C/W
SOOmW
1SS·C/W
S70mW
1S0·C/W
SOOmW
1SS·C/W
260"C
260"C
TBDV
260·C
260·C
TBDV
260·C
260·C
TBDV
TMIN
TMAX
- SS·C to + 12S·C
C')
Operating Ambient Temperature Range
Power Dissipation (Po at 2S·C)
and Thermal Resistance (6jM
(H Package) Po
6jA
(N Package) Po
6jA
Lead Temperature (Soldering. 10 sec.)
Dual-In-Line Package (Plastic)
Metal Can Package (TO-S)
ESD Susceptibility (Note 4)
==
Electrical Characteristics TA = 2S·C unless otherwise specified (Note 2)
....
.
1.024
1.822
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1.81 8
1.914
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-25
TEMPERATURE. ·C
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5
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80
80
100
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Input Current (Pins 6, 7) vs
Temperature
~
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I-
12
-75
2.0
~
1.&
35
40
1
S
-25
+25
+75
+125 +150
TEMPERATURE,oC
Nonlinearity Error, PreCision
F·to·V Converter (Figure 6)
if J
-55'C~ I
2.4
0.8
VSUPPLY. V
!l
Output Saturation Voltage vs
lOUT (Pin 3)
>
18
J:i-r- '"
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5
10
1.2
25 30
t'-r--,
50
-50
2••
1'+125'C
20
V
3.2
.... ~ ~
JIll fIP' -"
10 15
"
~
100
FREQUENCY, kHz
D.4
5
....
ill
cc
1/
120
Power Drain vs VSUPPLY
-55!~
-
C
oS
-0.03
-0.04
p!SI
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VSUPPLY. V
:
FREOUENCY. kHz
+L
TYPICAL
150
=
5
"'~
+0,04
~
-0.04 t--I---+--t--t--+---l
20
40
10 15 20 25 30 35 40
TEMPERATURE. ·C
ol-d:::--+-I-+--+-I
35
o~(\ I.oiii~
1"1II1II
200
~
30
~~.~
-1.5
Nonlinearity Error, LM131
(Figure 1)
100 kHz Nonlinearity Error,
LM131 Family (Rgure 4)
~:~ r--+--t-~~~--~--f
25
-2.0
1.912
9.94 L...L....L....L....L....L....L....L....I....I
-55 -2&
+25
+15
+125
+2.0
~
~
.....
~ 1.91 8
~+OA3r--+--t-~~~--+-~
20
1.930
1.92&
t-+-t-+--t--If--f
15
Output Frequency vs
VSUPPLY
1.928
10.04
+0:114
10
PQWER SUPPLY VQLTAGE. Vs
VREF vs Temperature,
LM131A
''',...,....,...-r-r-r-r-,
~
r-
FREQUENCY. kHz
Frequency vs Temperature,
LM131A
10.0&
SPEC LIMIT
::::i 0.010
-0.03 UJ.WlLWlllLl.LIlIIL
10
0.020
~O.015
:3
~
-0.01
~-0.02
~ -0.13
.
....
+0.01
" J
i,/
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+0.04 r--t--+--~t--+--t---f
1.{25·C
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I--+--t--I,,!~,~--+---f
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+0.02 tt--~tt--~,~M~~=~I~M~UM~~~~~
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-0.04
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SPEC
f,f."
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10
20
30
'OUT.mA
40
10
50
12
FREQUENCY. kHz
TL/H/56BO-3
3-282
riii:
......
Typical Applications (Continued)
Co)
PRINCIPLES OF OPERATION OF A SIMPLIFIED
VOLTAGE-TO-FREQUENCY CONVERTER
DETAIL OF OPERATION, FUNCTIONAL BLOCK
DIAGRAM (FIGURE 1a)
The LM131 is a monolithic circuit designed for accuracy and
versatile operation when applied as a voltage-to-frequency
(V-to-F) converter or as a frequency-to-voltage (F-to-V) converter. A simplified block diagram of the LM131 is shown in
Figure 2 and consists of a switched current source, input
comparator, and 1-shottimer.
The block diagram shows a band gap reference which provides a stable 1.9 VDC output. This 1.9 VDC is well regulated
over a Vs range of 3.9V to 40V. It also has a flat, low temperature coefficient, and typically changes less than %%
over a 100·C temperature change.
The current pump circuit forces the voltage at pin 2 to be at
1.9V, and causes a current i = 1.90VlRs to flow. For
Rs = 14k, i = 135 p.A. The precision current reflector provides a current equal to i to the current switch. The current
switch switches the current to pin 1 or to ground depending
on the state of the Rs flip-flop.
The operation of these blocks is best understood by gOing
through the operating cycle of the basic V-to-F converter,
Figure 2, which consists of the simplified block diagram of
the LM131 and the various resistors and capacitors connected to it.
The voltage comparator compares a positive input voltage,
V1, at pin 7 to the voltage, Vx, at pin 6. If V1 is greater, the
comparator will trigger the 1-shot timer. The output of the
timer will turn ON both the frequency output transistor and
the switched current source for a period t= 1.1 RtCt. During
this period, the current i will flow out of the switched current
source and provide a fixed amount of charge, Q= i x t, into
the capacitor, CL. This will normally charge Vx up to a higher
level than V1. At the end of the timing period, the current i
will turn OFF, and the timer will reset itself.
The timing function consists of an Rs flip-flop, and a timer
comparator connected to the external RtCt network. When
the input comparator detects a voltage at pin 7 higher than
pin 6, it sets the Rs flip-flop which turns ON the current
switch and the output driver transistor. When the voltage at
pin 5 rises to % Vee, the timer comparator causes the Rs
flip-flop to reset. The reset transistor is then turned ON and
the current switch is turned OFF.
......
l>
.....
r-
iii:
......
Co)
......
.....
riii:
N
Co)
......
l>
.....
r-
iii:
~
......
.....
riii:
Co)
Co)
......
l>
.....
r-
iii:
Co)
Co)
......
However, if the input comparator still detects pin 7 higher
than pin 6 when pin 5 crosses % Vee, the flip-flop will not
be reset, and the current at pin 1 will continue to flow, in its
allemptto make the voltage at pin 6 higher than pin 7. This
condition will usually apply under start· up conditions or in
the case of an overload voltage at signal input. It should be
noted that during this sort of overload, the output frequency
will be 0; as soon as the signal is restored to the working
range, the output frequency will be resumed.
Now there is no current flowing from pin 1, and the capacitor CL will be gradually discharged by RL until Vx falls to the
level of V1. Then the comparator will trigger the timer and
start another cycle.
The currentflowing into CL is exactly lAVE = i x (1.1 x RtCtl
x f, and the current flowing out of CL is exactly Vx/RL ""
VIN/RL. If VIN is doubled, the frequency will double to maintain this balance. Even a simple V-to-F converter can provide a frequency precisely proportional to its input voltage
over a wide range of frequencies.
The output driver transistor acts to saturate pin 3 with an
ON resistance of about 500. In case of overvoltage, the
output current is actively limited to less than 50 rnA.
The voltage at pin 2 is regulated at 1.90 VOC for all values of
i between 10 p.A to 500 p.A. It can be used as a voltage
reference for other components, but care must be taken to
ensure that current is not taken from it which could reduce
the accuracy of the converter.
"L
",
"'-r--A/IIIr----.---i
q
PRINCIPLES OF OPERATION OF BASIC VOLTAGETO-FREQUENCY CONVERTER (FIGURE 1)
VLOGIC
The simple stand-alone V-to-F converter shown in Figure 1
includes all the basic circuitry of Figure 2 plus a few components for improved performance.
A resistor, RIN= 100 kO±10%, has been added in the path
to pin 7, so that the bias current at pin 7 (-80 nA typical)
will cancel the effect of the bias current at pin 6 and help
provide minimum frequency offset.
FREQUENCY
OUTPUT
The resistance Rs at pin 2 is made up of a 12 kO fixed
resistor plus a 5 kO (cermet, preferably) gain adjust rheostat. The function of this adjustment is to trim out the gain
tolerance of the LM131, and the tolerance of Rt, RL and Ct.
TUH/5680-4
FIGURE 2. Simplified Block Diagram of Stand-Alone
Voltage-to-Frequency Converter Showing LM131 and
External Components
3-283
•
.- r----------------------------------------------------------------------------------------------,
CO)
CO)
==
....I
;;c.CO)
CO)
==
.......
....I
.CO)
N
:l
;;C
.CO)
N
==
.......
....I
.CO)
.-
==
Typical Applications (Continued)
For best results, all the components should be stable lowtemperature-coefficient components, such as metal-film resistors. The capacitor should have low dielectric absorption;
depending ,on the temperature characteristics desired, NPO
ceramic, polystyrene, Teflon or polypropylene are best
suited.
A capacitor CIN is added from pin 7 to ground to act as a
filter for VIN. A value of 0.Q1 ",F to 0.1 ",F will be adequate in
most cases; however, in cases where better filtering is required, a 1 ",F capacitor can be used. When the RC time
constants are matched at pin 6 and pin 7, a voltage step at
VIN will cause a step change in fOUT. If CIN is much less
than CL, a step at VIN may cause fOUT to stop momentarily.
A 470 resistor, in series with the 1 ",F CL, is added to give
hysteresis effect which helps the input comparator provide
the excellent linearity (0.03% typical).
....I
DETAIL OF OPERATION OF PRECISION V-TO-F
CONVERTER (FIGURE 3)
CO)
.-
In this circuit, integration is performed by using a conventional operational amplifier and feedback capacitor, CF.
When the integrator's output crosses the nominal threshold
level at pin 6 of the LM131, the timing cycle is initiated.
;;C
.-
==
....I
The average current fed into the op amp's summing point
(pin 2) is i X (1.1 RtCtJ x f which is perfectly balanced with
- VIN/RIN. In this circuit, the voltage offset of the LM131
input comparator does not affect the offset or accuracy of
the V-to-F converter as it does in the stand-alone V-to-F
converter; nor does the LM131 bias current or offset current. 'Instead, the offset voltage and offset current of the
operational amplifier are the only limits on how small the
signal can be accurately converted. Since op amps with
voltage offset well below 1 mV and offset currents well below 2 nA are available at low cost, this circuit is recommended for best accuracy for small signals. This circuit also responds immediately to any change of input signal (which a
stand-alone circuit does not) so that the output frequency
will be an accurate representation of VIN, as quickly as 2
output pulses' spacing can be measured .
In the precision mode, excellent 'linearity is obtained because the current source (pin 1) is always at ground potential and that voltage does not vary with VIN or fOUT. (In the
stand-alone V-to-F converter, a major cause of non-linearity
is the output impedance at pin 1 which causes i to change
as a function of VIN).
The circuit of Figure 4 operates in the same way as Agure 3,
but with the necessary changes for high speed operation.
Vs
'Ok"D%
10k .t10%**
-"""I\,........
VLOGIC
1_
~-4_---:mz
FULL-SCALE
Uk
V,N
-IOV
FULL SCALE
-...JW\r-------+----I
IN400Z
vs+--Nw-+
I
TUH/5680-5
'Use stable compoMnts with low temperature coefficients. See Typical Applications section.
"This resistor can be 5 kn or 10 kn torVs~BV to 22V, but must be 10 kn tor VS~4.5V to
av.
'''Use low offset voltage and low offset current op amps tor A1: recommended types LM10B, LM30BA, LF411A
FIGURE 3. Standard Test Circuit and Applications Circuit, Precision Voltage-to-Frequency Converter
3-284
......
==
Typical Applications (Continued)
(0)
DETAILS OF OPERATION, FREQUENCY-TOVOLTAGE CONVERTERS (FIGURES 5 AND 6)
0.1 second time constant, and settling of 0.7 second to
0.1 % accuracy.
In these applications, a pulse input at fiN is differentiated by
a CoR network and the negative-going edge at pin 6 causes
the input comparator to trigger the timer circuit. Just as with
a V-to-F converter, the average current flowing out of pin 1
is IAVERAGE = i x (1.1 RICI) x f.
In the simple circuit of FIGURE 5, this current is filtered in
the network RL = 100 k!l. and 1 ".F. The ripple will be less
than 10 mV peak, but the response will be slow, with a
In the precision circuit, an operational amplifier provides a
buffered output and also acts as a 2-pole filter. The ripple
will be less than 5 mV peak for all frequencies above 1 kHz,
and the response time will be much quicker than in Figure 5.
However, for input frequencies below 200 Hz, this circuit will
have worse ripple than Figure 5. The engineering of the filter
time-constants to get adequate response and small enough
ripple simply requires a study of the compromises to be
made. Inherently, V-to-F converter response can be fast,
but F-to-V response can not.
.....
J>
......
.-
.....
==
(0)
.....
......
.==
N
(0)
.....
J>
......
.==
N
(0)
.....
......
.==
(0)
(0)
.....
J>
......
Ht
1011 :1:111%**
&.IkU"*
.==
.....
(0)
(0)
r-"'V\"""""VLOGIC
LM331
I-:-~~---o ~~:~Hl
FULL SCALE
,,-
GAIN
ADJUST
·Use stable components with low temperature coefficients.
u.
See Typical Applications section.
CF
"This resistor can be 5 kn or 10 kn for
470pF
V,N
FULLSCmO-.....W Y - - - - -....--f .....-
but must be 10 kn for
....
Vs~4.5V
Vs~BV
to 22V,
to BV.
**"Usa low offset voltage and low offset current op amps for A 1:
recommended types LF411A or LF356.
-V,
Vs
-V,
IN4DDZ
"
OPTIONAL
OFFSET ADJUST
ZlHOIM
TL/H/5680-6
FIGURE 4_ Precision Voltage-to-Frequency Converter,
100 kHz Full-Scale, ± 0.03% Non-Linearity
+VS=+4·SVTD+20V
+Vs= +15V
A,
Uk1m*
A,
&81.
410pF
--1 ......-----'-1
J1..JlI1..
t
1%.
C,
-!O,OTIlF*
Jl......J1..
I,. -I ......-=-___
lIN
AS
{
Af
lDDku*
lOUT
~.....- .....--VOUT
12"" ".
AL
1001ln*
""'"
~
Cl,41Dpf
AS
Sk-
{
,,-
TL/H/5680-7
vour
~ f,N X 2.09V x !'!h x
Rs
VOUT ~ -f,N X 2.09V
(RAJ
·Use stable components with low temperature coefficients.
RF
x As x (Rtc,)
-Vs
TL/H/56BO-8
SELECT Rx ~ (Vs - 2V)
0.2mA
FIGURE 5. Simple Frequency-to-Voltage Converter,
10 kHz Full-Scale, ±0_06% Non-Linearity
·Use stable components with low temperature coefficients.
FIGURE 6_ Precision Frequency-to-Voltage Converter,
10kHz Full-Scale with 2-Pole Filter, ± 0_01 %
Non-Linearity Maximum
3-285
.CO)
CO)
:;
•
Typical Applications (Continued)
Ught Intensity to Frequency Converter
.-
CO)
CO)
+5VTO+ISV
:::E
...I
......
.-
,...
CO)
N
F--f-"'-o~:::'::
FULL SCALE
:::E
•:s
...I
.CO)
N
......
.CO)
.-
TUH/5680-9
:::E
...I
'L14F-l, L14G-l or L14H-l, photo transistor (General Electric Co.) or similar
......
c:c
.CO)
.-
:s
Temperature to Frequency Converter
Vo
.
,
I-=--f.-..........~ fOUTa TEM.
U1II:t 1%R,
IIHlrK
.
D."/.IF
TUH/5680-10
Basic Analog-ta-Dlgltal Converter Using
Voltage-to-Frequency Converter
Long-Term Digital Integrator Using VFC
'Vo
'VI
VI.
VII
TL/H/568D-l1
TUH/568D-12
3-286
Typical Applications (Continued)
Analog-to-Digltal Converter with Microprocessor
,vs
TLlH/5680-13
Remote Voltage-to-Frequency Converter with 2-Wlre Transmitter and Receiver
FREQUENCY
OUTPUT
TLlH/5680-14
Voltage-to-Frequency Converter with Square-Wave Output Using + 2 Flip-Flop
'VS' +4.0VOC TO +15VOC
CLR PRE
'VS
47k
VFC
CIRCUIT
USING
LM331
fOUT-F/2
SQUARE
WAVE
TL/H/5680-15
Voltage-to-Frequency Converter with Isolators
'Vs
'VLOOIC
Ik
VFC
USING
LM331
'---r---'
/,
t--D.o---
\
'OUT
TO COMPUTER
OR
~~ COUNTER
TO F·TO·V
CONVERTER
USING LMI31
DPTDISOLATOR
4N210R
SIMILAR
TL/H/5680-16
3-287
..(f)
(f)
:::E
Typical Applications
(Continued)
....I
......
Voltage-to-Frequency Converter with Isolators
c:(
..-
-.........n~-fOUT
...........,,.---I fOUT
N
:::E
....I
COMPARATOR
WITH
HYSTERESIS
......
..-
TUH/5660-17
(f)
..:::E
Voltage-to-Frequency Converter with Isolators
....I
-------.....
ANALOG
INPUTS'
COMPARATOR
12:....:..::~-~HC>------.....
13;...:.:,..-+++11'>-----.....
14.....:.:.L--++++l1>----.....
15,~T---+-+-r-~H:>_----__.
16--=+---+-H~HH-I:>---~
DIGITAL AO
1-0F-B
ADDRESS A1
ADDRESS DECODER
(FROM MPU) A2-,-...__________-'
I
~-------r4---------8
6 -5
RREF
vee
VREF +Vee
---".I.------
CH (RAMP CAPACITOR)
TlIH/l0409-1
3-291
•
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vccl
Pin Temperature
Ceramic DIP (Soldering, 60 Sec.)
Molded DIP (Soldering, 10 Sec.)
1BV
300'C
260'C
Comparator Output (Ramp Stop)
-0.3Vto +1BV
Operating Ratings (Note 1)
Analog Input Range
-0.3Vto +30V
Operating Temperature Range
Digital Input Range
-0.3Vto +30V
Output Sink Current
~A970BPC,~A970BDC
10mA
Storage Temperature Range
-65'Cto +150'C
Continuous Total Dissipation
Ceramic DIP Package
Molded DIP Package
900mW
1000 mW
O'Cto +70'C
- 55'C to + 125'C
~A970BDM
Supply Voltage {Vccl
4.75Vto 15V
Reference Voltage
(VREF) (Note 2)
2.BV to 5.25V
300pF
Ramp Capacitor (CH)
12 ~At050 ~A
Reference Current (IR)
Analog Input Range
OVto VREF
Ramp Stop Output Current
1.6mA
Electrical Characteristics
Over recommended operating conditions, Vcc = 5.0V, -55'C ~ TA ~ + 125'C for ~A970BDM and O°C ~ TA ~ +70'C for
~A970BDC or ~A970BPC; unless otherwise specified.
Symbol
Typ
Max
Units
EA
Conversion Accuracy
Parameter
Over Entire Temperature
Range (Note 3)
Conditions
±0.2
±0.3
%
ER
Linearity
Applies to Any One
Channel (Note 4)
±O.OB
±0.2
%
VOSM
Multiplexer Input Offset Voltage
Channel ON
2.0
4.0
mV
tc
Conversion Time per Channel
Analog Input = OV to VREF
CH = 300 pF, IREF = 50 ~A
296
350
~s
tA
Acquisition Time
CH
20
40
IA
Acquisition Current
=
Min
1000pF
150
~s
IJ.A
to
Ramp Start Delay Time
100
ns
tM
Multiplexer Address Time
1.0
~s
VIH
Digital Input HIGH Voltage
AO, A 1, A2, Ramp Start
VIL
Digital Input LOW Voltage
AO, A 1, A2, Ramp Start
18
Analog Input Current
Channel ON or OFF
IlL
Input LOW Current
AO, A 1, A2, Ramp Start
IIH
Input HIGH Current
AO, A 1, A2, Ramp Start
los
Input Offset Current
10H
Comparator Logic "1"
Output Leakage Current
VOH
VOL
Comparator Logic "0" Output Voltage
10L
PSRR
Power Supply Rejection Ratio
(Note 5)
Cross Talk between
Any Two Channels
(Note 6)
Vee
2.0
V
0.8
=
=
O.4V
-3.0
-1.0
-15
-5
5.5V
1.0
=
=
15V
=
5Vto 15V,I0
IJ.A
1.0
IJ.A
3.0
~A
10
~A
0.4
1.6 mA
=
V
~A
V
40
dB
60
dB
Icc
Power Supply Current
CIN
Input Capacitance
0
7.5
3.0
15
mA
pF
COUT
Comparator Output Capacitance
5.0
pF
Note 1: Absoute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but do not guarantee specific performance limits.
Note 2: VREF should not exceed Vee - 2V.
Note 3: Conversion accuracy is defined as the deviations from a straight line drawn between the paints defined by channel address 000 (0 scale) and channel
address t t t (full scale) for all channels.
Note 4: Linearity is defined as the deviation from a straight line drawn between the 0 and full scale points for each channel.
Note 5: Power supply rejection ratio is defined as the conversion error contributed by power supply voltage variations while resolving mid scale on any channel.
Note 6: Cross Talk between channels ~ 20 log t.vCH.
AV,
3-292
r--------------------------------------------------------------------------.~
»
Timing Diagram and Test Circuits
CD
......
o
CO
r----s!
U
I-IA--j
-2V--;
RA~PSTART
1-10
O.BV
V1N +O.7V---
CAPACITOR
VOLTAGE
o.~~=~---t---L!""
______
At
I'A9708
RAMP
A2 START CH GND
Vee
RA~P
STOP
0.4V
TLIHII0409-7
FIGURE 1. Equivalent Timing Waveform for
Test Circuits and Applications
TLIHll0409-10
FIGURE 4. StatiC Measurements
Functional Description
ALL COMPONENTS
:t10%
This Analog to Digital Converter is a single-slope 8-bit, 6channel AID converter that provides all of the necessary
analog functions for a microprocessor·based data/control
system. The device uses the processor system to provide
the necessary addressing, timing and counting functions
and includes a 1-of·8 decoder, 8·channel analog multiplex·
er, sample and hold, precision current reference, ramp integrator and comparator on a single monolithic chip.
+5V
AI
RAMP
A2 START
2kJl
l.lkJl
Applications that require auto·zero or auto-calibration, (See
Figures 5-8) can use selection of address 000 and 111, for
input address lines AO-A2, in conjunction with the arithme·
tic capability of a microprocessor to provide ground and
scaling factors. Address 0, 0, 0 internally connects the input
of the ramp generator to ground and may be used for zero
offset correction in subsequent conversions. Address 1, 1,
1, internally connects the input of the ramp generator to the
voltage reference, VREF, and may be used for scale factor
correction in subsequent conversions. For the following, reo
fer to the Functional Block Diagram.
+5V
CONTROL I/O rRO~ MPU
(TIMING COMPATIBLE WITH FiGURE I)
Input Timing:
TLIHII0409-8
tA> 400 I's
VREF
=
)
( 2kll3.3kll
+ 3.3kll 5V
= 3.t
5 - 3.1
IR = 100kll = 191'A
tRlmax = full scale ramp time
Six separate external analog voltage inputs may come into
terminals 11 -16 and the specific analog input to be convert·
ed is selected via address terminals AO-A2. The analog
input voltage level is transferred to the external ramp capacitor connected to pin 4 when the input to the ramp start
terminal (pin 3) is at a logic 0 (See Figure 1). The time to
charge the capaCitor is the acquisition time which is a function of the output impedance of an amplifier internal to the
AID converter and the value of the capacitor. After charging
the external capaCitor the ramp start terminal is switched to
a logiC 1 which introduces a high impedance between the
analog input voltage and the external capacitor.
0.01 X 10-6
= 19 X 10 6 X 3.1 = 1.6ms
Note: For evaluation purposes,the ramp start timing generation can be implemented with an lM555 timer (astable operation) or MPU evaluation kit,
and a time interval meter for ramp time measurement. The TIM meter will
measure the time between to 0 to 1 transition of the ramp start and the 1 to
o transition of the ramp stop. The ramp stop is open collectof, and must
have an external pull-up resistor to Vce.
FIGURE 2. Slow Speed Evaluation Circuit
for Ratiometric Operation
The capaCitor begins to discharge at a controlled rate. The
controlled rate of discharge (ramp) is established by the ex·
ternal reference voltage, the external reference resistor, the
value of the external capacitor and the internal leakage of
the AID converter. Connected to the capacitor terminal is a
I'A970B
AI
RAMP
A2 START
TLIHll0409-9
FIGURE 3. Linearity!Acquisition Time!
Conversion Time Test Circuit
3·293
•
Functional Description (Continued)
Auto-Zero and Full-Scale Features
COUNT
COUNT
256t---------~
NF.S.f-----------""""'~
INPUT
INPUT
TL/H/10409-4
TLiH/10409-3
NF.S. '" 256
No Zero Offset
No Full-Scale Error
Nz '" 0
(N) has both full-scale and zero errors
Count (n) = VV 1N x 256
REF
FIGURE 6. Transfer Function with
Zero and Full-Scale Error
FIGURE 5. Ideal Transfer Function
comparator internal to the AID converter with its output going to the ramp stop terminal (pin 7). The comparator output
is a logic one when the capacitor is charged and switches to
a logic 0 when the capacitor is in a discharged state. The
ramp time is from the time when ramp start goes HIGH (logic "1 ") to when ramp stop goes LOW (logic "0"). The microprocessor must be programmed to determine this conversion time. The ideal (no undesirable internal source impedances, leakage paths, errors on levels where comparator
switches or delay time) conversion time is calculated as follows:
Where
Auto-Zero and Full-Scale Features (Continued)
COUNT
N'F.S.I------------:7'r
N'I-------::7f'~
Ramp Time = V1 CH
IR
V1 = Analog Input Voltage Being Measured
CH = External Ramp Capacitor
INPUT
=N
N'
- Nz
TL/H/10409-5
N' has Full-Scale Error
FIGURE 7. Transfer Functions with
Zero-Correction Added
IR = Vee - VREF
RREF
Where
Vee = Power Supply Voltage
VREF = Reference Voltage
RREF = Reference Resistor
In actual use the errors due to a nonideal AID converter can
be minimized by using a microprocessor to make the calculations. (See Figures 5 through 8.)
COUNT
N"F.S.f------------,;If'
Channel Selection
Input Address Line
A2
A1
AD
0
0
0
0
1
1
0
1
0
1
0
0
0
1
1
1
1
0
0
1
1
1
0
1
Selected
Analog Input
INPUT
Ground
11
12
13
14
15
16
VREF
N"
=
256
(N - Nz) x (NF.S.
Nz)
TL/H/10409-6
FIGURE 8. Transfer Function with both Zero and
Full-Scale Correction Added
3-294
r--------------------------------------------------------------------------,~
Application Suggestions and Formulas
1. The ramp time measurement may be implemented in
software using a register increment, followed by a branch
back depending on the status of the ramp stop.
1. The capacitor node impedance is approximately 30 ,...0.
and should have no parallel resistance for proper operation.
2. Alternately, the ramp stop may be tied into the interrupt
structure in systems containing a programmable binary
timer. This scheme has the following advantages:
2. tR when VIN = OV will be finite (i.e., the comparator will
always toggle for VIN :;0, OV).
a. The CPU is not committed during the ramp time interval.
Typical Applications
3. The ramp stop output is open collector, and an external
pull-up resistor is required.
b. It requires only 4 bits of an I/O port for control signals.
3. The auto-zero/auto-full-scale (See Figures 5-8) should
use double preCision, rounded (as opposed to truncated)
arithmatics. Several points are worth noting:
4. All digital inputs and outputs are TTL compatible.
5. For proper operation, timing commences on the 0 to 1
transition of ramp start and terminates on the 1 to 0 transition of ramp stop.
6. tA
:;0,
a. The subtractions are single op code instructions.
b. The full scale correction uses a multiply by 256 and
can be accomplished by a shift left S bits (usually one
instruction) or placing (N - Nz) in the MSB register
and setting the LSB register to zero, for the double
preCision divide.
CH
.
A I X VREF (See Figure 1 )
150,... - R
.
CH
CH
7. tR (ramp time) = - - - , tRlmax = - - X VREF
IR X VIN
IR
(See Figure 1)
C. The divisor (NF.S. -
Nz) of the MSB register will al-
ways be zero.
-Vc""C"::---_V:..!.R"'E"'F
S.IR =-'RREF
9. 2V ,;; VREF ,;; (Vcc - 2V)
These schemes have the following advantages:
a. No access to the data bus or address bus is required,
by the AID system.
10. Address lines AO, A 1, A2 must be stable throughout the
sampling interval, tAo
b. 4 I/O bits completely support the AID system.
C.
11. Pin 6 (RREF) should be bypassed to ground via a 0.02
,...F capacitor.
Since auto full scale/auto zero are implemented in
software and long term drift (aging) effects are eliminated.
Microprocessor Considerations
d. Software overhead is minimal (typically 30 bytes).
Several alternatives exist from a hardware/software standpOint in microprocessor based systems using the ,...A970S.
e. Where ratio metric operation is permissible, the 4 external components may be ±5% tolerance, including the
power supply.
~~~~--------------------~
roMP~--------------------~
A3~--------------------~
14 I'A9708 A21------------------------i
I/o
PORT
Al~---;IR-------------------I
Rl
CAPt---....;;....----,
R2
OUTPUT
Note: AVI
~
(Applied Force) and can be Linearized (if necessary) in Software.
FIGURE 9. Ratiometric Strain Gage Sensore/Controller
3-295
TL/H/l0409-11
~
......
o
CO
Typical Applications
(Continued)
SENSOR
VCC+
SOLUnON
!
NV+O
!
R3
Vcc+
Vcc+
~
RAMP
STARTt--------------1
PHOTO
RESISTOR
roMP~--------------------_i
~~--------------------_i
RX
J.'A9708
VCC+
AZi-------------t
I/O PORT
Al~--_:_----------------_i
IRCAPt-----..,
Rl
RZ
CONTROL
CIRCUITS
TUH/l0409-12
ApplicatiDns
Beverage Brewers/Dispensers
Chemical Solution Control
Automatic Liquid Mixing Control
Ramp Current
VI
~
~ IR ~ Vee (Rl ' ; RJ (i)
(RX :x RB) Vee+
FIGURE 10
3-296
Section 4
Digital-to-Analog
Converters
II
Section 4 Contents
Digital-to-Analog Converters Definition of Terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital-to-Analog Converters Selection Guide ..........................................
DAC0630/DAC0631 Triple 6-Bit Video DAC with Color Pallette . . . . . . . . . . . . . . . . . . . . . . . . . . .
DAC0800/DAC0801/DAC0802 8-Bit DI A Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DAC0808/DAC0807/DAC0806 8-Bit DI A Converters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DAC0830/DAC0831/DAC0832 8-Bit jl.P Compatible Double-Buffered DI A Converters .. . . . .
DAC1 000/DAC1 001/DAC1 002/DAC1 006/DAC1 007/DAC1 008 jl.P Compatible,
Double-Buffered DI A Converters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DAC1020/DAC1021/DAC102210-Bit Binary Multiplying D/A Converters..................
DAC1220/DAC1221/DAC122212-Bit Binary Multiplying D/A Converters..................
DAC1208/DAC1209/DAC121 0/DAC1230/DAC1231/DAC1232 12-Bit jl.P Compatible
Double-Buffered DI A Converters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DAC1218/DAC1219 12-Bit Multiplying DI A Converters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DAC1265A1DAC1265 Hi-Speed 12-Bit DI A Converters with Reference. . . . . . . . . . . . . . . . . . ..
DAC1266A1DAC1266 Hi-Speed 12-Bit DI A Converters .................................
4-2
4-3
4-4
4-6
4-21
4-30
4-38
4-56
4-79
4-79
4-89
4-104
4-115
4-124
~National
~ Semiconductor
Definition of Terms
DI A Converters
Conversion Time: The time required for a complete measurement by an analog-to-digital converter.
Multiplying DAC: In a sense, every DAC is a multiplying
DAC since the output voltage (or current) is equal to the
reference voltage times a constant determined by the digital
input code divided by 2" (n is the number of bits of resolution). In a two quadrant multiplying DAC the reference voltage or the digital input code can change the output voltage
polarity. if both the reference voltage and the digital code
change the output voltage polarity, four quadrant multiplication exists.
DC Common-Mode Error: This specification applies to
ADCs with differential inputs. It is the change in the output
code that occurs when the analog voltages on the two inputs are changed by an equal amount. It is expressed in
LSBs.
Differential Nonlinearity: Ideally, any two adjacent digital
codes correspond to measured analog voltages that are exactly one LSB apart. Differential non-linearity is a measure
of the worst case deviation from the ideal 1 LSB step. For
example, a DAC with a 1.5 LSB output change for a 1 LSB
digital code change exhibits % LSB differential non-linearity.
Differential non-linearity may be expressed in fractional bits
or as a percentage of full scale. A differential non-linearity
greater than 1 LSB will lead to a non-monotonic transfer
function in a DAC and missing codes in an ADC.
Offset Error (Zero Error): In a DAC, this is the output voltage that exists when the input digital code is set to give an
ideal output of zero volts. In the case of an ADC, this is the
difference between the ideal input voltage (% LSB) and the
actual input voltage that is needed to make the transition
from zero to 1 LSB. All the digital codes in the transfer curve
are offset by the same value. Many converters allow nulling
of offset with an external potentiometer. Offset error is usually expressed in LSBs.
Gain Error (Full Scale Error): For an ADC, the difference
(usually expressed in LSBs) between the input voltage that
should ideally produce a full scale output code and the actual input voltage that produces that code. For DACs, it is the
difference between the output voltage (or current) with full
scale input code and the ideal voltage (or current) that
should exist with a full scale input code.
Power Supply Rejection (Power Supply Sensitivity): The
sensitivity of a converter to changes in the dc power supply
voltages.
Quantizing Error: The error inherent in all AID conversions. Since even an "ideal" converter has finite resolution,
any analog voltage that falls between two adjacent output
codes will result in an output code that is inaccurate by up to
% LSB.
Gain Temperature Coefficient (Full Scale Temperature
Coefficient): Change in gain error divided by change in
temperature. Usually expressed in parts per million per degree Celsius (ppmI"C).
Ratiometric Operation: Many AID applications require a
stable and accurate reference voltage against which the input voltage is compared. This approach results in an absolute conversion. Some applications, however, use transducers or other Signal sources whose output voltages are
proportional to some external reference. In these ratiometric applications, the reference for the signal source should
be connected to the reference input of the converter. Thus,
any variations in the source reference voltage will also
change the converter reference voltage and produce an accurate conversion.
Integral Nonlinearity (Linearity Error): Worst case deviation from the line between the endpoints (zero and full
scale). Can be expressed as a percentage of full scale or in
fractions of an LSB.
LSB (Least-Significant Bit): In a binary coded system this
is the bit that carries the smallest value or weight. Its value
is the full scale voltage (or current) divided by 2", where n is
the resolution of the converter.
Monotonicity: A monotonic function has a slope whose
sign does not change. A monotonic DAC has an output that
changes in the same direction (or remains constant) for
each increase in the input code. The converse is true for
decreasing codes.
Resolution: The smallest analog increment corresponding
to a 1 LSB converter code change. For converters, resolution is normally expressed in bits, where the number of analog levels is equal to 2". As an example, a 12-bit converter
divides the analog signal into 212 = 4096 discrete voltage
(or current) levels.
MSB (Most Significant Bit): in a binary coded system this
is the bit that has the largest value or weight. Its value is one
half of full scale.
Settling Time: The time from a change in input code until a
DAC's output signal remains within ± % LSB (or some other
specified tolerance) of the final value.
4-3
II
~NatiOnal
Semiconductor
01 A Converter Selection Guide
Part
No.
Resolution
(Bits)
Linearity
% (Max)
Settling
Time
(+% LSB)
Supplies
(V)
@2S'C
Temperature
Range'
M
I
Package
Comments
C
DAC0631
6
0.78
28
5
•
28-Pin DIP
44-PinPCC
Triple 35 MHz
VideoDAC
DAC0631-40
6
0.78
25
5
•
28-Pin DIP
44-PinPCC
Triple 40 MHz
VideoDAC
DAC0630
6
0.78
20
5
•
28-Pin DIP
44-Pln PCC
Triple 50 MHz
VideoDAC
ADC0852
8
0.19
5
•
•
8-PinDIP
DAC, Comparator,
Serial Input
ADC0854
8
0.19
5
•
•
14-Pin DIP
DAC, Comparator,
Serial Input
DAC0800
8
0.19
100 ns
±5to ±15
•
•
16-PinDIP
16-PinS.O.
High-Speed
Multiplying
DAC0801
8
0.39
100 ns
±5to ±15
•
•
16-Pin DIP
16-PinS.O.
High-Speed
Multiplying
DAC0802
8
0.10
100 ns
±5to ±15
•
•
16-Pin DIP
16-PinS.O.
High-Speed
Multiplying
DAC0806
8
0.78
150 ns
±5to ±15
•
16-Pin DIP
16-PinS.O.
Multiplying
DAC0807
8
0.39
150 ns
±5to±15
•
16-Pin DIP
16-PinS.O.
Multiplying
DAC0808
8
0.19
150 ns
±5to ±15
•
•
16-PinDIP
16-PinS.O.
Multiplying
DAC0830
8
0.05
1 /Ls
5to 15
•
•
20-Pin DIP
20-PinS.O.
20-PinPCC
/LP Compatible
4-Quadrant
Multiplying
DAC0831
8
0.10
1 /Ls
5to 15
•
20-Pin DIP
/LP Compatible
4-Quadrant
Multiplying
DAC0832
8
0.20
1 /Ls
5to 15
•
•
20-Pin DIP
20-PinS.O.
20-PinPCC
/LP Compatible
4-Quadrant
Multiplying
DAC1000
10
0.05
500ns
5to 15
•
•
24-Pin DIP
/LP Compatible
Double Buffered
DAC1001
10
0.1
500ns
5to 15
•
24-PinDIP
/LP Compatible
Double Buffered
DAC1002
10
0.2
500ns
5to 15
•
•
•
24-Pin DIP
/LP Compatible
Double Buffered
DAC1006
10
0.05
500ns
5to 15
•
•
•
20·PinDIP
/LP Compatible
Double Buffered
DAC1007
10
0.1
500ns
5to 15
•
•
20-Pin DIP
/LP Compatible
Double Buffered
DAC1008
10
0.2
500 ns
5to 15
•
•
20-PinDIP
/LP Compatible
Double Buffered
4-4
•
•
•
~
01 A Converter Selection Guide (Continued)
Part
No.
DAC1020
DAC1021
DAC1022
Resolution
(Bits)
10
10
10
Linearity
@25'C
% (Max)
Settling
Time
(+% LSB)
Supplies
(V)
0.05
500 n5
5 to 15
0.1
0.2
500n5
500n5
5to 15
5to 15
(')
Temperature
Range'
M
I
C
•
•
•
•
•
•
•
•
•
Package
Comments
16·PinDIP
4·Quadrant
Multiplying
16·Pin DIP
4·Quadrant
Multiplying
16·PinDIP
4·Quadrant
Multiplying
DAC1208
12
0.012
1 p.s
5to 15
•
•
24-PinDIP
p.P Compatible
4-Quadrant
Multiplying
DAC1209
12
0.024
1 P.5
5to 15
•
•
24·Pin DIP
p.P Compatible
4-Quadrant
Multiplying
DAC1210
12
0.05
1 P.5
5to 15
•
•
24-Pin DIP
p.P Compatible
4-Quadrant
Multiplying
DAC1218
12
0.012
1 p.s
5to 15
•
•
18-Pin DIP
4-Quadrant
Multiplying
DAC1219
12
0.024
1 p.s
5to 15
0
•
18-Pin DIP
4-Quadrant
Multiplying
DAC1220
12
0.05
500n5
5to 15
•
•
18-Pin DIP
4-Quadrant
Multiplying
DAC1221
12
0.1
500n5
5 to 15
•
18-PinDIP
4-Quadrant
Multiplying
DAC1222
12
0.2
500n5
5 to 15
•
•
18-Pin DIP
4-Quadrant
Multiplying
DAC1230
12
0.012
1 p.5
5to 15
•
•
20-PinDIP
p.P Compatible
4-Quadrant
Multiplying
DAC1231
12
0.024
1 P.5
5to 15
•
•
20-Pin DIP
p.P Compatible
4-Quadrant
Multiplying
DAC1232
12
0.05
1 p.5
5to 15
•
•
20-Pin DIP
p.P Compatible
4-Quadrant
Multiplying
DAC1265A
12
0.006
200n5
±15
24·Pin DIP
High·Speed
12
0.012
200n5
±15
•
•
•
DAC1265
•
24·Pin DIP
High·Speed
DAC1266A
12
0.006
200ns
±12to ±15
•
•
24·Pin DIP
High·Speed
DAC1266
12
0.012
200n5
±12to ±15
•
•
24·Pin DIP
High·Speed
•
•
'AmbJent temperature range for "M" is -SS'C to + 12S'C, "J" is -2S'C to +8S'C or -40"C to +8S'C, "C" O"C to +70·C.
4·5
o
....~
....CD
en
CD
CD
2O·
::I
C)
C
a::
CD
,.. r--------------------------------------------------------------------------------,
CO)
:8 ~ National
~~ ~ Semiconductor
CO)
8
DAC0630/DAC0631
;:§ Triple 6-Bit Video DAC with Color Palette
General Description
Features
The DAC0630 and DAC0631 are monolithic triple 6-bit video
digital-to-analog converters with on-chip 256 x 18 bit color
palettes and are intended for graphics applications. The color palette makes possible the display of 256 colors selected
from a total of 256K possible colors through the internal
6-bit video DACs. The DACs are capable of driving 750 or
37.50 loads to normal video levels at pixel rates of 50 MHz
(DAC0630) and 35 MHz (DAC0631). The DAC0630 and
DAC0631 provide a bi-directional microprocessor interface
with TTL compatible inputs. The DAC0630 and DAC0631
are pin- and functionally-compatible with the Inmos IMS
G171-50 and IMS G171-35 and IMS G176-50 and IMS
G176-35.
• Pixel rates of 50 MHz (DAC0630) and 35 MHz
(DAC0631)
•
•
•
•
•
256 x18 bit color palette
256K possible colors
Color palette read-back
Three internal 6-bit DACs
Directly drives (75!l) video cable
•
•
•
•
RGB analog output
Composite blank
Single + 5V supply
Low power, high performance CMOS/bipolar
processing
• TTL compatible inputs
• Full asynchronous ",p interface
• 28-pin package
Block and Connection Diagrams
Dual-In-Line Package
PCLK
Timing
Generalor
y+
GND
Color Palette
256x18Bii
18
DO-~
WR
Rii
RSo
28
RED
GREEN
8-BII
Micro-
y+
RS,
BLUE
3
RSo
IREF
4
WR
Po
5
~
P,
6
P2
P3
7
P4
Ps
9
D3
10
D2
Ps
P7
11
12
17
PCLK
13
16
Do
BLANK
GND
14
15
Rii
8
Ds
Ds
DAC0630
DAC0631
D4
D,
RED
Processor
Interface
TL/H/9636-2
18-BII Data
RS,
GREEN
Top View
BLUE
Order Number
DAC0630CCD or DAC0631CCD
See NS Package Number D28D
BLANK
IREF--------'
TL/H/9636-1
4-6
Order Number DAC0631CCN
See NS Package Number N28B
Power Dissipation (Note 5)
ESD Susceptability (Note 6)
Absolute Maximum Ratings
(Notes 1 & 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Positive Supply Voltage (V +)
GND - 0.3V to 7V
Soldering Information
D Package (10 sec)
N Package (10 sec)
Voltage at Logic Inputs (Note 3)
Storage Temperature
GND V+
GND V+
Voltage at Analog Pins 1-4 (Note 3)
Analog Output Current, Pins 1-3
Reference Current, Pin 4
DC Digital Output Current (Note 4)
0.5Vto
+ 0.5V
0.5Vto
+ 0.5V
1.0W
2000V
300'C
260'C
-65'Cto 150'C
Temperature Range
TMIN S; TA S; TMAX
Positive Supply Voltage
15mA
25mA
O'C
S;
TA
S; + 70'C
4.5 to 5.5V
AC and DC Electrical Characteristics
DAC0630
DAC0631
IREF
Parameter
Reference Current
Conditions
Typical
(Note 7)
Tested
Limit
(NoteS)
Design
Limit
(Note 9)
Units
Minimum
-3
mA
Maximum
-10
mA
160
150
mA
mA
Y+ - 3
V
±10
p.A
±50
p.A
2.4
V
0.4
V
V
lAVE
Maximum Average
Supply Current
VREFmin
Minimum Reference Voltage at
IREFPin
V+ = 4.5V
IREF = 8.88 mA
liN
Maximum Digital Input Current
(Pins 5-13,15,16,25-27)
V+ = 5.5V
GND S; VIN
S;
V+
Maximum Tri-State Digital Output
Current (Pins 17-24)
V+ = 5.5V
GND S; VIN
S;
V+
VOH
Minimum Logic "1" Output
Voltage
V+ = 4.5V, 10 = -5 mA
VOL
Maximum Logic "0" Output
Voltage
V+ = 4.5V, 10 = +5 mA
VIH
Minimum Logic "1" Input Voltage
4.5V
S;
V+
S;
5.5V
2
VIL
Maximum Logic "0" Input Voltage
4.5V
S;
V+
S;
5.5V
0.8
V
6
Bits
1.5
V
loz
DAC0630
DAC0631
PCLK = 50 MHz
PCLK = 35 MHz
IREF = 10mA
Digital Outputs Unloaded
DAC Resolution
VOUT
Minimum Output Voltage
Compliance (Pins 1-3)
lOUT
S;
10mA
4-7
~
oo
Co)
.....
The following specifications apply for V + = +5V, unless otherwise specified. Boldface limits apply for TMIN to TMAX; all
other limits TA = 25'C.
Symbol
en
Co)
o
......
en
Operating Ratings (Notes 1 & 2)
45mA
~
oo
AC and DC Electrical Characteristics (Continued)
The following specifications apply for V+
other limits TA = 25D C.
=
+5V, unless otherwise specified. Boldface limits apply for TMIN to TMAX; all
DAC0630
DAC0631
Symbol
lOUT
Parameter
Conditions
Maximum Output Current
Compliance (Pins 1-3)
VOUT';; 1V
IREF s: lOrnA
Full-Scale Gain Error
(Note 10)
ZL = 75!l + 30pF
IREF = 4.44 mA
ZL = 37.5!l
30 pF
IREF = 8.88 mA
Tested
Limit
(Note 8)
Design
Limit
(Note 9)
Units
21
mA
-8, +2
%
-14, -4
%
ZL = 75!l + 30pF
IREF = 4.44 mA
(See Note 11)
±2
%
Integral Non-Linearity
(Note 12)
ZL ;, 75!l + 30 pF
IREF = 4.44 mA
±O.5
LSB
Rise Time
(Note 13)
ZL = 75!l + 30pF
IREF = 4.44 mA
+
DAC-to-DAC Mismatch
toN
Typical
(Note 7)
Maximum Full-Scale
Settling Time
DAC0630
DAC0631
Maximum Glitch Energy
ZL = 75!l + 30pF
IREF = 4.44 mA
(See Note 14)
ZL =.75!l + 30pF
IREF = 4.44 mA
(See Note 15)
±200
8
ns
20
28
ns
ns
±400
pV-sec
CIN
Digital Input Capacitance (Pins
5-13,15,16,25-27)
COUT
Digital Output Capacitance (Pins
17-24)
RD
CoUTA
Analog Output Capacitance
(Pins 1-3)
BLANK
VOUTBLANK
Maximum Blanking Output
Voltage
BLANK = Logic Low
ZL = 75!l + 30pF
IREF = 4.44 mA
±O.5
LSB
Unadjusted Output Offset Error
BLANK = Logic High
ZL = 75!l + 30pF
IREF = 4.44 mA
±O.&
LSB
Clock Feedthrough
(Note 16)
PSS
Power Supply Sensitivity
DAC0630D
DAC0631D
DAC0631N
=
Logic High
=
Logic Low
7
pF
7
pF
10
pF
PCLK = 50 MHz
PCLK = 35 MHz
PCLK = 35 MHz
ZL = 75!l + 30pF
IREF = 4.44 mA
4.5V ,;; V+ ,;; 5.5V
lOUT = Full Scale
ZL = 75!l + 30pF
IREF = 4.44 mA
4-8
-30
-35
-30
6
dB
dB
dB
%IV
AC Electrical Characteristics The following specifications apply for V+
g
= + 5V. Boldface limits apply for
(")
o
en
Co)
TMIN to TMAX; all other limits TA = 25°C. Design Limits apply for 4.5V :s; V + :s; 5.5V.
DAC0630
Symbol
Parameter
tcHCH
Minimum PCLK Period
Conditions
(Note 17)
Tested
Typical
Limit
(Note 7)
(Note 8)
~
DAC0631
Design
Limit
(Note 9)
Tested
Typical
Limit
(Note 7)
(Note 8)
Design
Limit
(Note 9)
Units
o
en
Co)
28
28
ns
6
9
9
ns
20
20
6
±2.5
±2.5
AtCHCH
Maximum PCLK Jitter
tCLCH
Minimum PCLK Width Low
tCHCL
Minimum PCLK Width High
6
6
7
7
ns
tPVCH
Minimum Pixel Word Setup Time
(Note 18)
4
4
4
4
ns
tCHPX
Minimum Pixel Word Hold Time
(Note 18)
4
4
4
4
ns
Minimum BLANK Setup Time
(Note 18)
4
4
4
4
ns
tCHBX
Minimum BLANK Hold Time
(Note 18)
4
4
4
4
ns
tcHAV
PCLK to Valid DAC
Output
(Note 19)
5
5
5
5
ns
30
30
30
30
AtCHAV
Maximum Differential Output
Delay
(Note 20)
tWLWH
Minimum WR Pulse Width Low
tRLRH
Minimum RD Pulse Width Low
tSVWL
Minimum Register Select Setup
TIme
(Write Cycle)
tsVRL
Minimum Register Select Setup
Time
(Read Cycle)
tWLSX
Minimum Register Select Hold
Time
(Write Cycle)
tRLSX
Minimum Register Select Hold
Time
(Read Cycle)
tOVWH
1
ns
1
50
50
50
50
ns
50
50
50
50
ns
10
10
15
15
ns
10
10
15
15
ns
10
10
15
15
ns
10
10
15
15
ns
Minimum WR Data Setup Time
10
10
15
15
ns
tWHOX
Minimum WR Data Hold Time
10
10
15
15
ns
tRLOX
Minimum Output Turn-On Delay
5
5
5
5
ns
tRLOV
Maximum RD Enable Access
Time
40
40
40
40
ns
tRHOX
Minimum Output Hold Time
5
5
5
5
ns
20
20
20
20
ns
tRHOZ
Maximum Output Turn-Off Delay
IwHWL1
Minimum Successive Write
Interval
3(tcHCH) 3(tcHCH)
3(tCHCH) 3(1CHCH)
tWHRL1
Minimum WR followed by Read
Interval
3(tCHCH) 3(1CHCH)
3(tcHCH) 3(tcHCH)
tRHRL1
Minimum Successive Read
Interval
3(tCHCH) 3(1CHCH)
3(tcHCH) 3<'cHCH)
tRHWL1
Minimum RD followed by Write
Interval
3(tcHCH) 3(tcHCH)
3(tcHCH) 3(1CHCH)
3(tcHCH) 3(tcHCH)
3(tCHCH) 3(tCHCH)
tWHWl2 Minimum WR after Color Write
(Note 21)
(Note 22)
4-9
....
%
tBVCH
IMinimum
IMaximum
g
(")
•
AC Electrical Characteristics (Continued) The following specifications apply for V+ =
limits apply for TMIN to TMAX; all other limits TA = 25°C. Design limits apply for 4.5V :s; V+ :s; 5.5V.
DAC0630
Symbol
Parameter
Tested
Conditions Typical
Limit
(Note 7)
(Note 8)
+5V. Boldface
DAC0631
Design
Limit
(Note 9)
Typical
(Note 7)
Tested
Limit
(Note 8)
Design
Limit
(Note 9)
tWHRL2
Minimum RD after Color Write
(Note 22)
3(tCHCH) 3ctcHCH)
3(tCHCH) 3ctcHCH)
tRHRL2
Minimum RD after Color Read
(Note 22)
6(tCHCH) 6ctcHCH)
6(tCHCH) 6ctcHCH)
tRHWL2
Minimum WR after Color Read
(Note 22)
6(tCHCH) 6(tcHCH)
6(tCHCH) 6(1:CHCH)
tWHRL3
Minimum RD after Read
Address Write
(Note 22)
6(tCHCH) 6(tCHCH)
6(tCHCH) 6(1:CHCH)
Maximum Write/Read Enable
Transition Time
50
50
Units
ns
Note t: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond Hs specHied operating ratings.
Note 2: All voltages are measured with respect to ground, unless otherwise specified.
Note 3: When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < GND or VIN > V+) the absolute value of current at that pin should be limited
to S mA or less. The sum of the currents at all pins that are driven beyond the power supply voltages should not exceed 20 mAo
Note 4: One output at any time. The maximum time for this output level is one second.
Note 5: The maximum power dissipation must be derated at elevated temperatures and Is dictated by TJMAX, OJA, and the ambient temperature, TA. The maximum
allowable power dissipation at any temperature is Po = (TJMAX-TAl/OJA or the number given in the Absolute Maximum Ratings, whichever is lower. For this
device, TJMAX = 12S'C, and the typical thermal resistance (OJAl of the DAC0630/0631 CCD when board mounted Is 40'C/W. The typical thermal resistance for the
DAC0630/631 CCN when board mounted is 8S'C/W.
Note 6: Human body model, 100 pF discharged through a I.S kll resistor.
Note 7: Typicals are at 2S'C and represent most likely parametric norm.
Note 8: Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level).
Note 9: Design limits are guaranteed to National's AOQL (Average Outgoing Quality Level) but not 100% tested.
Note 10: Full·Scale Gain Error is defined as !i(F.S. IOUT)RL-2.1(IREF)Rt.l/12.1(IREF)Rt.l)100%. VBLACK LEVEL = OV.
Note 11: The listed value is relative to the midpoint of the full-scale distribution of the internal three DACs.
Note 12: Zero and lull·scale adjusted linearity error = [Vou,-Voffse,-{D x VLSB)]IVLSB, VLSB = (Vlull scale-Voffset)/63.
Note 13: The rise time is measured from 10% to 90% of the full scale transition.
Note 14: The output signal's settling time is measured from a 2% change at the transition's initial value until it has settled to within 2% of the final value, excluding
clock feedthrough.
Note 15: This value is determined using triangle approximation: glitch energy = (area of positive transient)-(area of negative tranSient).
Note 16: The value shown is the ratio of the RMS value of any PCLK signal on the analog outputs to the lull·scale output voltage (700 mV).
Note 17: This parameter is the allowed variation in the pixel clock frequency. It does not permit the pixel clock period to vary below the minimum value for pixel
clock (!cHCW period specified above.
Note 18: It is necessary that the color palette's pixel address be a valid logic level with the appropriate setup and hold times at each rising edge of PCLK (thiS
requirement includes the blanking pariod).
Note 19: A valid analog output is defined as the SO% point between successive values. This parameter is stable with time but can vary between different devices
and may vary wHh different dc operating conditions.
Note 20: This applies to different analog outputs on the same device.
Note 21: Measured at ±200 mV from initial steady state output voltage.
Note 22: This parameter allows synchronization between operations on the microprocessor interface and the pixel stream being processed by the color palette.
4-10
c
»
o
AC Test Conditions Digital Output Load
1.4V
DAC0630's
and
DAC0631's
Pins 17-24
~
50PF
Input Pulse Levels ........................... GND to 3V
o
en
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Input Rise and Fall Times (10% to 90%) ............ 2.5 ns
.......
DigitallnputTiming Reference Level. ................ 1.5V
Digital Output Timing Reference Level ....... O.BV and 2.4V
I
en
Co)
.....
TLlH/9636-3
Timing Waveforms
PCLK
RED
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lXXXXXXXXXXXXXXX>--A~B--r-C\
"-F~G~
"'_"""'"",",<.K._~"""..¥.>'-¥."""'"",",.
<.K._".
'-BLANK-BLANK-'
GREEN D-A--r-B~C ___ BLANK_BLANK...r-F~G--r
BLUE[)(XXXXXXXxxXXXXXXXxrA'--B--r-C~BLANK_BLANK""-F---G-.r
TL/H/9636-4
FIGURE 1. System Timing Diagram
PCLK
RED _ _ A~B-4----t~--
- - - - BLANK--
GREEN--A~B
- - - - BLANK - BLUE -A~B-l___ Iir'--C~
~
BLANK - - - - BLANK - TL/H/9636-5
FIGURE 2. Expanded Timing Diagram Detailing Timing Specifications
4·11
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;
r-------------------------------------------------------------------------------------,
Timing Waveforms
(Continued)
.....
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TL/H/9636-6
FIGURE 3. Basic Write Cycle
~-~----------------------~~~::::::::~~t_-------TUH/9636-7
FIGURE 4. Basic Read Cycle
ViR
RD
\\,._____
....l
1$.'lllX__
~
'------------C){1
~U.i.....;...~~~~_.u,()()()()()(Xh~~~_.&.l&~X~X~~~.;...i......JXXXXXXX:::)O
~----(~..--~~r'iB;LLUiuE::).--~~
- - - - { ADDRESS
TLfHf9636-14
FIGURE 11. Color Value Write Followed by Any Read
RD
...."
'.~~____'
DO-~ - - - - {
ADDRESS
~---<~>----~(CJB~L~UEC
TLfHf9636-15
FIGURE 12. Color Value Write Followed by Any Write
4-14
,----------------------------------------------------------------------, C
Timing Waveforms
l:;
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(Continued)
Q)
Wii~tWHRL3
w
o
.....
C
l:;
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iffi
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Do-Iry
---<
ADDRESS
~---
ADDRESS
RED
GREEN
BLUE
TLlH/9636-17
FIGURE 14. Color Value Read Followed by Any Write
III
4-15
9-
C")
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r-----------------------------------------------------------------------------------------,
PCLK(13)
Connection Diagram
Plastic & Cavity
Dual·ln·Llne Package
C")
~
RED- 1.
\..../
28 ~v+
GREEN- 2
27 ~RS1
BLUE- 3
26 ~RSo
' REf Po -
25
4
5
GND (14)
Hvii
RD (15)
24 ~D7
23 ~D6
P1- 6
22 -Ds
P2 -
7
P3 P4 -
8
9
21 -D4
20 -D3
Ps-
10
19
P6-
11
18 -D1
P7 -
12
DAC0630
DAC0631
BLANK (16)
-Dz
17 -Do
PCLK- 13
00-07 (17-24)
16 -BLANK
GND- 14
15
-Rli
TUH/9636-18
TopYlew
Pin Descriptions
RED (1),
GREEN (2),
BLUE (3)
IREF (4)
PO-P7 (5-12)
These are the analog output pins of the
6-bit DACs. The output currents from
these pins flow through the terminating
resistors and develop the RGB (red,
green and blue) voltages that drive the
monitor. Each DAC is composed of 63
current sources. The output of each of
these current sources is summed together according to the applied 6-bit binary
value.
This is the Reference Current input. The
current forced out of this pin to ground
determines the current sourced by each
of the 63 current sources in each of the
three 6-bit DACs. Each current source
produces 1/30 of IREF when activated by
the 6-bit digital input code.
These are the high-speed Pixel Address
inputs. This byte-wide information is
latched and masked by the Pixel Mask
Register. The resulting value is used as
an address of a location in the Color Palette RAM.
WR(25)
RSO,RSI
(26,27)
Y+ (28)
4-16
The high-speed Pixel Clock signal is applied to this pin. The rising edge controls
the latching of the Pixel Address and
Blanking inputs. It also controls the progress of these values through the three
stage pipeline of the Color Palette and
through the DACs to the outputs.
This is the ground power supply connection.
This is the active low Read bus control
signal. When active, any information
present on the internal data bus is available on the Data I/O lines, Do-D7.
This is an active low signal that forces the
DAC's outputs to zero. When BLANK is
asserted a video monitor's screen becomes black and the DACs ignore any
output values from the Color Palette.
However, the Color Palette can still be
updated through Do-D7.
These are the bidirectional Data I/O lines
used by the host microprocessor to write
information (using the active low WR) into
and read information (using the active low
RD) from the DAC0630 and DAC0631 's
internal registers (Pixel Address register,
Color Value register, and Pixel Mask register).
During the write cycle, the rising edge of
WR latches the data into the selected
register.
The rising edge of RD determines the
end of the read cycle.
With RD and WR equal to a logic high,
the Data I/O lines will no longer contain
information from the selected register
and will go into a tristate mode.
This is the active low Write signal. It controls the timing of the write operations on
the microprocessor interface inputs, DoD7. When active, any information present
on the external data bus is available to
the Data I/O lines, Do-~.
These are the Register Select lines which
control the selection of one of the three
internal registers. These two lines are
sampled during the falling edges of the
enable signals (RD or WR). See Functional Description for more information regarding the internal registers.
This is the positive supply pin. It is normally connected to + 5 Vdc and bypassed with a 10 /loF tantalum capacitor
and a 0.1 /loF chip capacitor.
g
Functional Description
The DAC0630 (or DAC0631) forms the output stage for high
resolution raster scan RGB video systems. It contains a Color Palette with 256 memory locations that are 18 bits wide.
The color palette's output is connected to three high speed
current output 6-bit video DACs. The devices use on-board
registers to interface easily with microprocessors.
It is possible to read the color definitions stored in the
DAC's color palette. After setting RSo and RS1 equal to 1,
the desired color palette address is stored in the Pixel Address register. The color definition (18-bits) in the desired
color palette location is then automatically transferred to the
Color Value register and the Pixel Address is auto-incremented. With successive read cycles, the color definitions
pointed to by the incremented address are transferred to
the color value register. Refer to Figure 13.
The Pixel Mask register is a byte-wide latch. by setting
RSo = 0 and RS1 = 1, the Pixel Mask register can be
accessed by the microprocessor interface, Do-D7. This register is used to mask selected bits of the pixel address values applied to the Pixel Address inputs (PO-P7)' A "1" in
any location in the Pixel Mask register leaves the corresponding bit in the pixel address unchanged. A "0" will reset
the corresponding bit to zero. The operation of the Pixel
Mask register does not affect the address of the color definition when the microprocessor accesses the color palette.
The masking operation makes it possible to alter the displayed colors without altering the contents of external video
memory or the DAC0630/631's color palette.
MICROPROCESSOR INTERFACE
The DAC0630 and DAC0631 's microprocessor interface
consists of three internal registers; Pixel Address register,
Color Value register, and Pixel Mask register. These are individually accessed by register select signals, RSo and RS1.
The following table defines which of the three internal registers is selected by each of the four combinations of logic
states of RSo and RS1.
RSo
RS1
Register
0
1
1
0
0
1
0
1
Pixel Address (Write Mode)
Pixel Address (Read Mode)
Color Value
Pixel Mask
The contents of the color palette can be accessed through
the Color Value and Pixel Address registers.
WRITING TO THE COLOR PALETTE
A new color definition can be stored in the color palette by
first specifying the initial address while in write mode
(RSo = RS1 = WR = 0). This address is stored in the Pixel
Address register. The initial address is followed by the red,
green and blue color definition data (RSo = 1, RS1 =
WR = 0). These three six-bit values are collected together
in the Color Value register for a total of 18 bits. The internal
logic then transfers this new color definition to the location
pointed to by the address stored in the Pixel Address register. As soon as this transfer is completed, the Pixel Address
register is auto-incremented. This allows consecutive color
palette locations to be updated without the microprocessor
specifying each address. All that is necessary is to continue
supplying the red, green and blue data for each consecutive
address. Refer to Figures 11 and 12.
Attempting to update the color palette when BLANK is not
asserted results in the data from the Color Value register
taking precedence over the DAC0630 and DAC0631's bit
mapping operation. The output of the three 6-bit DACs will
be based on the color definition from the memory location
specified by the pixel address register and not the address
found on PO-P7. This conflict results in the DAC's generating unexpected output levels. This can last as long as two
PCLK periods.
All of the operations on the microprocessor interface can
take place asynchronously to the pixel information currently
being processed by the Color Palette.
The Pixel Address register is a byte-wide latch that receives and latches address information applied to pins 1724. It can be used in either the Read and Write mode depending on the logic state of RSo and RS1. With RSo =
RS1 = 0 (register select = 0,0), the Pixel address register
is in the write mode. Two events normally precede writing
one or more new color definitions to the color palette. The
first is the specification of a color palette address. Second,
the Color Value register must be loaded with a color definition. The sequence of data transfer is 1) the desired color
palette address (this address is stored in the Pixel Address
register) and 2) the color definitions: red, green and blue.
Refer to Figures 11 and 12.
When RSo = RS1 = 1 (register select = 1,1), the Pixel
Address register is in the read mode. Once again, two
events take place and normally precede reading one or
more color definitions in the color palette. The first action is
to specify an address within the color palette. the second is
to load the Color Value register with the contents of the
color palette location whose address is stored in the Pixel
Address Register. The color definition data transfer sequence is red, green and blue. Refer to Figures 10, 13 and
14.
READING FROM THE COLOR PALETTE
To read a location in the color palette an address is sent on
the Data 110 lines (Do-D7) while in read mode (RSo =
RS1 = 1, WR = 0) and stored in the Pixel Address register.
The color definition in the specified color palette location is
then transferred to the Color Value register and the Pixel
Address register is auto-incremented. The color definition
can now be retrieved with three sequential read operations
(RSo = 1, RS1 = RD = 0). The first byte placed on the
Data 110 lines contains the red value. The next is green,
and the last is blue. The two most significant bits are set to
zero in each case. Once again, the Pixel Address register is
auto-incremented, and consecutive color palette locations
can be read simply by specifying the beginning address and
reading the color palette one or more times. Refer to Figures 10, 13 and 14.
The Color Value register is an internal 18-bit wide register
used as a buffer between the microprocessor interface and
the color palette. It is accessed by setting RSo = 1 and
RS1 = O. A color definition can be read from or written to
this register by a sequence of three byte-wide transfers to
this register address. When a byte is written to this register,
only the least significant six bits (Do- Ds) contain color information. When a byte is read from this register address, only
the six least significant bits contain information-the most
significant two bits are set to zero. Refer to Figures 10-14.
After the write sequence is completed, the Color Value register's contents are written to the specified color palette address stored in the Pixel Address register. Finally, the Pixel
Address register is automatically incremented.
4-17
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Functional Description
ANALOG OUTPUT-LINE DRIVING
(Continued)
The connection between the DAC's outputs and the RGB
inputs of the video monitor it is driving should be viewed as
a transmission line. Impedance changes along this line will
result in the reflection of part of the video signal back to the
DAC's outputs. These reflections may result in a degradation of the picture quality displayed on the monitor.
If the Pixel address register is ever updated during a read or
write operation, the current data sequence is terminated
and a new read or write operation is initialized.
CO)
CD
VIDEO PATH
~
The video path consists of the Pixel Latch and Mask (inputs
PO-P7), color palette (256 x 1B-bit wide RAM), 1B-bit wide
bus, and an 1B-bit wide latch on the inputs of the three 6-bit
high-speed video DAQs. The video path uses a three clock
cycle (PCUQ pipeline for the pixel address and BLANK inputs. These signals are latched on the rising edge of PClK.
o
To ensure good signal fidelity, RF techniques should be observed. Any traces connecting the DAC0630 or DAC0631 to
an on-board connector should form a transmission line of
750 impedance. However, the need to ensure that the connecting traces form a transmission line can be eliminated by
placing the DAC's output termination resistors at the output
connector instead of the DAC's output pins.
At each rising edge of PClK, the Color Palette address applied to PO-P7 is stored in the Pixel Latch and defines a
location in the Color Palette. The color definition in that location is then transferred to the three 6-bit DAC input latches.
The coaxial cable that connects the DAC's outputs to a video monitor should have a characteristic impedance of 750.
Connectors on the coaxial line can cause impedance
change. Any connectors used with the coaxial cable should
match its characteristic impedance.
ANALOG OUTPUTS
The analog outputs are designed to drive 750 loads with
IREF set to 4.44 mA or 37.50 loads with IREF set to
B.BB mA. For both loads the peak-white amplitude is 0.7V.
There are four different methods of terminating the DAC
outputs:
1)
2)
3)
4)
The analog outputs can be set to zero by using the BLANK
input. This is an active low signal that forces the analog
outputs to ground by placing all zeros on the DACs' inputs.
The color definition selected by the pixel address is ignored.
Single termination at the DAC (750)
Single termination at the destination (750)
Double termination (37.50)
Buffered signal
1) Single termination at the source involves placing a single termination resistor at each DAC output of the DAC0630
and DAC0631 (or at the connector, as described above). No
other terminating load is present. Therefore, a high-input
impedance monitor should be used. The ac load driven by
the DAC's outputs is the transmission line impedance in parallel with the load resistor. The transmission line's impedance should match the impedance of the load resistor.
Thus, the DAC's output has an initial signal amplitude that is
half the dc value expected. This half-amplitude signal is
100% reflected by the open circuit presented by the monitor
input. This restores the signal amplitude to the expected
value. The reflections from the monitor propagate back
towards the DAC outputs. The load resistor at each DAC
output presents a correctly terminated transmission line so
no further reflections occur. This arrangement is relatively
tolerant to mismatches in the transmission line between the
DAC and the monitor because no reflections occur at the
DAC end of the transmission line. However, multiple monitors should not be connected in parallel despite each monitor's high input impedance.
2) Single termination at the destination has the termination impedance at the input of the monitor acting as both the
load resistor for the DAC and the termination impedance of
the cable (transmission line). If the connection between the
DAC0630/631 is correctly terminated there will be no reflections. However; if there are any line impedance variations
along the cable, reflections will occur and create "ghost images" on the display. This occurs because there is a reflection from the point where the mismatch occurs back to the
DAC's output. The signal then reflects off the DAC's output
back toward the monitor. It arrives with a significant time
delay following the original signal, and "ghosting" results.
The DAC0630/631's DACs use switched current sources
that are summed together, thus generating the output current. Each 6-bit DAC consists of 63 current sources, each of
which has a magnitude of IREF/30. The digital input code
determines the number of current sources that are active
and contributing to the total output current. This output current, in conjunction with a termination resistance connected
between each DAC output and ground, sets the full-scale
magnitude of the output voltage as determined by
VPEAKWHITE = 2.1(IREF)Rl
VBLACK lEVEL = OV
Application Hints
POWER SUPPLY
The DAC0630 and DAC0631 draw large transient currents
from the power supply. To ensure proper operation it is necessary to utilize standard high frequency board layout and
power supply distribution techniques.
The transient currents drawn by the DAC0630 and
DAC0631 dictate that the ac impedance at the supply pins
must be kept to a minimum. This is accomplished by using
the recommended decoupling capacitors, C1 and C2, as
shown in Figure 15. These capacitors must have leads that
are as short as possible. High frequency decoupling is accomplished with a 0.1 p.F chip capacitor, C1. A bead tantalum, between 10 p.F to 47 p.F, should be used for C2.
Differential ground noise can be created when a voltage
difference appears between pin 14 and the ground of the
digital devices driving the DAC0630 or DAC0631. This voltage difference is caused by series impedance in the ground
path and the current transients drawn by the DAC0630 or
DAC0631. The differential ground noise can be minimized
by using large, low inductance ground paths between the
digital devices that drive the DAC0630 or DAC0631 and pin
14. Therefore, a ground plane layout is recommended.
3) Double termination of the DAC outputs allow each end
of the transmission line to be correctly matched. This results
in the least amount of reflection and the highest signal and
display fidelity. This termination method also allows for the
4-18
c
»
Application Hints (Continued)
0
«:)
C»
c.:I
+5V
«:)
5
8
Pixel Address Input
18
19
20
21
22
23
24
D2
~~ " . "{
.....
4
I REF
GND
14
DO
Dl
PCLK
For IREF= 4. 44mA:
Rl = 22.1!l, R2 = 93111
For IREF=8.88mA:
Rl = 11.0., R2 = 464,(1
13
DAC0630
DAC0631
D3
To monitor's RED input.
RED
D4
75-
Pixel Clock
75-
DS
Os
2
To monitor's GREEN input.
RS O
75-
RS 1
15 ifIj
25
16
«:)
C»
c.:I
GREEN
27
C
»
0
0.1 J.'F
°7
26
........
28
PI
P2
P3
9
P4
10
Ps
11
Ps
12
P7
17
Data Input/Output
V+
Po
ViR
BLANK
To monitor's BLUE input.
BLUE
J1I1.fUl...r
75-
Note: Bead-style tantalum capacitors should be used for the 10 "F devices_
Thermally connect the NPN transistors together with a Wakefield 259 series Equalizing Link.
75- 1/4 Walt Carbon Film
TL/H/9636-19
FIGURE 15. Typical Connection Showing IREF Generator and Double Termination
fastest fall time. The DAC termination's RC time constant
sets the outputs' fall time. The greater the time constant,
the slower the fall time. Therefore, the fall time will be minimized since the impedance using this termination technique
is less than that achieved with single termination. With double-termination it is necessary to increase IREF to
8.88 mA to ensure a full-scale output voltage of 700 mY.
GENERATING IREF
An active current source for IREF is recommended to ensure
that the DACs have predictable and stable output currents.
There are numerous methods available to generate the reference current. The voltage drop from V+ to the IREF pin
increases with increasing IREF current. The circuit used to
generate IREF must be designed to operate at the minimum
voltage (VREFmin = V+ - 3V) expected from the IREF pin
to ground. For any application, VREFmin will be smallest
when IREF is maximum and supply voltage is minimum. For
IREF = 8.8 mA and V+ = 4.5V, the IREF generator will
have to operate with 1.5V or less across it. IREF generators
that require a voltage drop greater than 1 .5V may be used if
a negative supply is available.
4) By placing a buffer at the DAC's output, the DAC0630
and DAC0631 will be able to drive large capacitive loads
such as long lossy cables. The buffer requries a high input
impedance, a condition that is satisfied with LM1203 RGB
Video Amplifier System. A 75n load is placed at the buffer's
input. The buffer's low output impedance should be
matched to the interconnecting cable with a series resistor.
The cable should then be terminated with the same resistance at the monitor.
A simple IREF generator circuit is shown with the DAC0630/
DAC0631 in Figure 15. As shown, this IREF generator will
sink ;:,4.44 mA (single termination) with Rl = 22.1n and
R2 = 931 n. For applications that use double termination,
Rl = 11 nand R2 = 464n. The diode connected transistor, 01, across 02's base-emitter junction performs a firstorder compensation for thermal variations. It is important to
keep the lead lengths as short as possible. This will help
reduce stray capacitance and the amount of PCLK that is fed
into the IREF pin.
ANALOG OUTPUT-PROTECTION
The DAC0630 and DAC0631 have on-chip electrostatic discharge (ESD) protection on each pin. However, the same
precautions should be taken as with any other CMOS integrated circuit during manufacturing to reduce the possibility
of ESD damage.
4-19
Application Hints (Continued)
.5V
v.
5 P
6
28
0
P,
7 P
8
Pixel Add.." Input
2
P3
9 P
10
IRErl-'------t:::;-.....- -....
•
11 Ps
12 P6
P7
17
GNO ,.
Do
3604
18 0
19
20
Dolo InputlOutput
21
1
~
~
22 04
PClK 13
DAC063D
DAC0631 REDo.;l-t-..,..---_e) To monitor's RED
lnput•
•
..L
23 Os
24 06
0,
,
Control 51gnolo
{~~RSO
--+-r----e)
..LToInput.monitor'. GREEN
GREEll.
15 ~1
RO
25 ViR
16
BilNK
_ ) To monKer's BLUE
BLUE 3
..Llnput•
Plxol C l o c l c J U 1 I " L f l . f " - - - - - - - - - '
Note: Bead·style tantalum capacHors should be used for the 10 ".F devices.
-
'1/4 Wott Carbon FIlm
TLlH/9636-20
FIGURE 16. Single Termination with LM334 Current Source IREF Generator
Figure 16 shows an alternative method of generating IREF.
The LM334 precision current source i,s used in a temperature compensated configuration. The reference current is
set by a single resistor, R1, independent of V+. The current's value is
DECOUPLING IREF
The magnitude of the current flowing through the internal
current sources depends not only on IREF' but also on the
voltage at pin 4 relative to V+. Therefore, voltage variations
between V+ and the IREF input can result in variations in
the DAC's output current. These variations can be greatly
attenuated by using a high frequency capacitor in parallel
with a larger electrolytic capacitor to couple the IREF input
toV+.
IREF:::: 160 mV/R1
4-20
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(X)
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........
DAC0800/DAC080 1IDAC0802 8-Bit Digital-to-Analog
Converters
The DACOBOO, DACOB02, DACOBOOC, DACOB01 C and
DACOB02C are a direct replacement for the DAC-OB, DACOBA, DAC-OBC, DAC-OBE and DAC-OBH, respectively.
The DACOBOO series are monolithic B-bit high-speed current-output digital-to-analog converters (DAC) featuring typical settling times of 100 ns. When used as a multiplying
DAC, monotonic performance over a 40 to 1 reference current range is possible. The DACOBOO series also features
high compliance complementary current outputs to allow
differential output voltages of 20 Vp-p with simple resistor
loads as shown in Figure 1. The reference-to-full-scale current matching of better than ± 1 LSB eliminates the need for
full-scale trims in most applications while the nonlinearities
of better than ± 0.1 % over temperature minimizes system
error accumulations.
Features
II
II
..
II
I:lI
III
III
The noise immune inputs of the DACOBOO series will accept
TTL levels with the logic threshold pin, VLC, grounded.
Changing the VLC potential will allow direct interface to other logic families. The performance and characteristics of the
device are essentially unchanged over the full ± 4.5V to
± 1BV power supply range; power dissipation is only 33 mW
with ± 5V supplies and is independent of the logic input
states.
[lJ
J:I
III
III
Fast settling output current
100 ns
±1 LSB
Full scale error
±0.1%
Nonlinearity over temperature
Full scale current drift
±10 ppmrC
-10V to +1BV
High output compliance
Complementary current outputs
Interface directly with TTL, CMOS, PMOS and others
2 quadrant wide range multiplying capability
Wide power supply range
± 4.5V to ± 1BV
33 mW at ±5V
Low power consumption
Low cost
Typical Applications
tov
I
DIGITAL INPUTS
'MSB
LSB '
y¥¥yy¥¥¥
10k
10k
lOUT
V': _-tL:-l: !. . -6~', ~8_0_A:.;: !. : _"_'~,'jl.=:t: __. . .-o} ".""'"
......
-=1-
~'~e F~
',.
TLIH/S686-t
FIGURE 1. ±20 Vp_p Output Digital-to-Analog Converter (Note 4)
Ordering Information
Non-Linearity
±0.1% FS
±0.1% FS
±0.19% FS
±0.19% FS
±0.39% FS
(X)
o......
........
c
General Description
10V
c
»
oo
Temperature
Range
Order Numbers
J Package (J16A)*
-55°C:o; TA:O; + 125°C DACOB02LJ
O°C:o; TA:O; +70°C
DACOB02LCJ
-55°C:o; TA :0; + 125°C DACOBOOLJ
O°C:o; TA:O; +70°C
DACOBOOLCJ
O°C:O; TA:O; +70°C
DACOB01LCJ
DAC-OBAQ
DAC-OBHQ
DAC-OBQ
DAC-OBEQ
DAC-OBCQ
"'Devices may be ordered by using either order number.
4-21
N Package (N16A)*
SO Package (M16A)
DACOB02LCN
DAC-OBHP
DACOB02LCM
DAC0800LCN
DACOB01 LCN
DAC-OBEP
DAC-OBCP
DACOBOOLCM
DACOB01 LCM
»
o
o(X)
oI\)
('II
i
Absolute Maximum Ratings (Note 1)
~..........
Lead Temp. (Soldering, 10 seconds)
Dual-In-Line Package (plastic)
Dual-In-Line Package (ceramic)
Surface Mount Package
Vapor Phase (60 seconds)
Infrared (15 seconds)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications•
Supply Voltage (V+ - V-)
±18Vor36V
Power Dissipation (Note 2)
500mW
Reference Input Differential Voltage
V- toV+
(V14 to V15)
Reference Input Common-Mode Range
V- toV+
(V14, V15)
Reference Input Current
5mA
V- to V- plus 36V
Logic Inputs
Analog Current Outputs (Vs - = -15V)
4.25mA
ESD Susceptibility (Note 3)
TBDV
Storage Temperature
- 65'C to + 150'C
io
~
C
......
o
o
CO
o
g
260'C
300'C
215'C
220'C
Operating Conditions (Note 1)
Temperature (TAl
DAC0802L
DAC0800L
DAC0800LC
DAC0801LC
DAC0802LC
Min
Max
Units
-55
-55
0
0
0
+125
+125
+70
+70
+70
'C
'C
'C
'C
'C
Electrical Characteristics The following specifications apply for Vs = ± 15V, IREF = 2 mA and T MIN
T MAX unless otherwise specified. Output characteristics refer to both lOUT and lOUT.
Symbol
ts
tPLH,
tPHL
TCIFS
Vac
IFS4
IFSS
Izs
Parameter
Resolution
Monotonicity
Nonlinearity
Settling Time
IFSR
VIL
VIH
Logic Input Levels
Logic "0"
Logic "1"
IlL
IIH
Logic Input Current
Logic "0"
Logic "1"
115
dlldt
DACOB02LJ
DACOBOOLJ
DACOB01LC
DACOB02LC
DAC0800LC
Units
Min Typ Max Min Typ Max Min Typ
Max
8
8
8
8
8
8
8
8
8
Bits
8
8
8
8
8
8
8
8
8
Bits
±0.39 %FS
±0.1
±0.19
To ± 'h LSB, All Bits Switched
"ON" or "OFF", TA=25'C
DAC0800L
DAC0800LC
100
135
100
Propagation Delay
TA=25'C
Each Bit
35
60
All Bits Switched
35
60
Full Scale Tempco
±10 ±50
-10
Output Voltage Compliance Full Scale Current Change
18 -10
<'h LSB, RaUT>20 M!l. Typ
Full Scale Current
VREF=10.000V, R14=5.000 k!l. 1.984 1.992 2.000 1.94
R15=5.000 k!l., TA=25'C
Full Scale Symmetry
±0.5 ±4.0
IFS4- IFS2
Zero Scale Current
Output Current Range
VIS
VTHR
Conditions
Logic Input Swing
Logic Threshold Range
Reference Bias Current
V-=-5V
V-=-8Vto-18V
0
0
0.1
2.0
2.0
1.0
2.1
4.2
2.0
Vs= ±15V
Reference Input Slew Rate (Aguf912)
4.5V';;V+ ,;1BV
~ Power Supply Sensitivity
-4.5V';;V- ';;1BV
PSSIFSIREF=1mA
Power Supply Current
Vs= ±5V, IREF=1 mA
1+
1-
0
0
-10
-10
4.0
ns
135
150
35
35
±10
60
60
±50
18 -10
35
35
±10
60
ns
60
ns
±80 ppml'C
18
V
1.99
2.04 1.94
1.99
2.04
mA
ns
ns
±1
±8.0
±2
+16
jJoA
0.2
2.0
2.0
2.0
2.1
4.2
0.2
2.0
2.0
4.0
2.1
4.2
jJoA
mA
mA
0.8
V
V
-2.0
0.002
-10
10
18 -10
13.5 -10
-3.0
-1.0
18
13.5
-3.0
jJoA
",A
V
0
0
0.8
2.0
-2.0 -10
0.002 10
150
100
100
0.8
VLC=OV
VLC=OV
-10V,;;VIN';; +0.8V
2V,;;VIN';; + 18V
V-=-15V
s: T A s:
2.0
-2.0
0.002
18 -10
13.5 -10
-1.0 -3.0
-1.0
-10
10
V
0.0001
0.0001
0.Q1
0.01
0.0001
0.0001
0.01
0.01
",A
mAl",s
%1%
%1%
2.3
3.8
-4.3 -5.B
2.3
-4.3
3.B
-5.B
2.3
-4.3
3.B
-5.B
mA
mA
2.4
3.8
-6.4 -7.B
2.4
-6.4
3.8
-7.B
2.4
-6.4
3.8
-7.B
mA
mA
2.5
3.B
-6.5 -7.B
2.5
-6.5
3.8
-7.8
2.5
-6.5
3.B
-7.8
mA
mA
8.0
0.0001 0.01
0.0001 0.01
4.0
8.0
4.0
8.0
Vs=5V, -15V, IREF=2 mA
1+
1Vs= ±15V, IREF=2mA
1+
1-
4-22
g
Electrical Characteristics (Continued)
The following specifications apply for Vs =
characteristics refer to both lOUT and lOUT.
Symbol
PD
Parameter
Conditions
Power Dissipation
(')
± 15V, IREF
±5V,IREF=1 rnA
5V,-15V,IREF=2 rnA
±15V,IREF=2 rnA
= 2 rnA and T MIN';;
DAC0802L1
DAC0802LC
Min
Typ
Max
33
4B
lOB
136
135
174
T A ,;; T MAX unless otherwise specified. Output
DAC0800LI
DAC0800LC
Min
Typ
Max
33
4B
lOB
136
135
174
DAC0801LC
Typ
Min
33
lOB
135
Units
Max
4B
136
174
o
CD
o
~
g
(')
mW
mW
mW
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: The maximum junction temperature of the DACOBOO, DACOBOI and DACOB02 is 125'C. For operating at elevated temperatures, devices in the Dual-In-Line
J package must be derated based on a thennal resistance of 10fJ'C/W, junction-to-ambient, 175'C/W for the molded Dual-In-Line N package and 10fJ'C/W for the
Small Outline M package.
o
CD
o
.....
.......
g
(')
o
CD
o
I\)
Note 3: Human body model, 100 pF discharged through a 1.5 kll resistor.
Note 4: Pin-out numbers for the DACOBOX represent the Dual·ln-Line package. The Small Outline package pin-out differs from the Dual-ln·Line package.
Connection Diagrams
Dual-In-Line Package
THRESHOLD 1
CONTROL. VLC
Small Outline Package
y+
16 COMPENSATION
•
'OUT
15 VREFI-)
v-
14 VREFI.)
13
'OUT
BZ
11 Bl
B3
10 B6
B4
B5
B7
14
86
COMPENSATION
4
13
85
THRESHOLD CONTROL, VLC
5
12
B4
lOUT
6
11
83
V-
7
10
82
v+
12 BB LSB
MS881
B8 LSB
VREF(+)
VREF(-)
Bl MSB
lOUT
TUH/5686-14
Top View
TLlH/5686-13
Top View
See Ordering Information
Block Diagram (Note 4)
MSB
v'
"
B2
B3
.
.
LSI
B5
"
B1
II
-+---.,
VREF(+IO:;:'·+-o.....
QACOI
"
COMP
vTLlH/5686-2
4-23
C'II
o
CO
~.......,...
Typical Performance Characteristics
Full Scale Current
vs Reference Current
o
CO
o
LSB Propagation Delay Vs IFS
TA"TMINTO TMAX
ALL BITS HIGH
'LlMiTFOR f-Y'-15Y
~ 400 l -
i"< --
g
......
".
..~
IL
o
o
CO
o
§
I.....
1/
g
1/
r-
-Y·-5Y -
L;'
I
.e
o 1/
o
~
250
100
f
LlMITFOR- r-
RL :::;500
ALL BITS "ON"
YR15 - OV
'"....=>
3DO
200
150
R14- R15 -lk
;;;
350
~
'"
:l!
Reference Input
Frequency Response
12
lD
B
450 r-
I LSB-18nA
w
l-
>
;::
I LSB·7.B.A
50
1111
IJI 111111
o
1111
1llllI
0.01 0.2 0.050.1 0.02 0.5 1
2
$
,/
"-
-2
-4
-6
-B
-10
I\,
}-
1\
-12
-14
S 10
0.1
0.2
IFS - OUTPUT FULL SCALE CURRENT (mAl
'REF - REFERENCE CURRENT (mAl
2
~~
0.5
10
FREQUENCY (MH,I
Curve 1: Cc=15 pF, VIN=2 Vp-p
centered at 1V.
Curve 2: Cc = 15 pF, VIN = 50 mVp-p
centered at 200 mY.
Curve 3: Cc=O pF, VIN=100 mVp-p
at OV and applied through 50
n con-
nected to pin 14.2V applied to R14.
Reference Amp
Common-Mode Range
4
:<
3.6
TA' TMIN TO TMAX
AL} 81Tf ·ON"
oS 32
....
ill
co
co
1l
~
~
I
E
2.B
2.4
2
1.6
1.2
0.8
0.4
Logic Input Current
vs Input Voltage
:<
.3
....
~5
I
-y. -15V
I
+Y=15V
Y'-SY
'REf' 2 mA
II
lRE~ • limA
!lu
r-
IRE~'O~mA-
I
0
-14 -10 -6
-2
2
6
10
14
'"
;;
Il
0;
2.6
2.4
2.2
2
I.B
~ 1.6
u
~
> 1.4
I
1.2
9
I
" "
O.B
0.6
0.4
0.2
0
50
-50
-12-10-B-B-4-2024 68101214161B
lB
100
150
TA - TEMPERATURE (. CI
Yi - LOGIC INPUT YOLTAGE (VI
YIS - REFERENCE COMMOHOOE YOLTAGE IYI
VTH - VLC vs Temperature
Note. Positive common~mode range is
always (V+) - 1.5V
Output Current vs Output
Voltage (Output Voltage
Compliance)
u
:<
....
..~
=>
-Y~-IJy ~Y'~SV
I
I.B
I I
1.4
I
0.8
16
:<
~
12
....
Bit Transfer
Characteristics
..
ill
co
5
IRJFJmA
..
:. -4
IRE)-02 mA
2
6
10
14
Vo - OUTPUT VOLTAGE (VI
>
lB
IREF=2mA
BI,
~
O.B
..~
0.6
E
02
....
~
l
0.4
1.2
oS
>
I
-14 -10 -B -2
~
~
IREF-2mA
12
I
E
Output Voltage Compliance
vs Temperature
ALLIBITSI"ONi' TA - TMIN TO TMAX
2.4
oS
i
20
D.4'
I
-8
-12 L..-J......L......L--L-'--'--'--'--'----'
-SO
0
50
100
150
TA - TEMPERATURE rCI
-\{·-16V
t/r-V--SY
~2
B3
B4
f-'~
lit
-12-10-B-6-4-20 246 B 101214161B
YL - LOGIC INPUT YOLTAGE IVI
TL/H/5686-3
Note. Bl-BB have identical transfer characteristics. Bits are fully switched with less than V. LSB
error, at less than ± 100 mV from actual threshold. These switching points are guaranteed to lie
between O.B and 2V over the operating temperature range (VLC = OV).
4-24
Typical Performance Characteristics
(Continued)
I-- -1--'1- ~ITJ IR~F • ~ mA - r-
l-
-,---
o
2
4
a:
6 8 10 12 14 16 18 20
~
-
I--
I I I
I I I
~
- f - I- ~v; 1~~
.!.
I I I
I I I
a:
~
::
-~O
-4 -6 -11-10-12-14-16-18-20
50
f-
1+
100
1511
TA - TEMPERATURE ("CI
V - NEGATIVE POWER SUPPLY (VI
Vcc - POSITIVE POWER SUPPLY IVI
C-!vL!v
~
I
o -2
ALL BITS HIGH OR LOW
IREF=ZmA I I
-c-
~
I;
It
10
I-
~IJTJIR~FLi-
-r- I~ WitH I~EFI. 0.1 ml
o
".sill
ALL BITS MAY BE HIGH OR LOW
ALL BITS HIGH OR LOW
D
Power Supply Current
vs Temperature
Power Supply Current
vs -V
Power Supply Current
vs +V
TLlH/5666-4
Equivalent Circuit
..
MSD
v'
B1
"
,
BZ
•
..,
B4
•
7
..
.7
10
11
'SD
II
,
,-,
lOUT
-v
TL/H/5686-15
Typical Applications
FIGURE 2
(Continued)
DIGITAL INPUTS
MSI
+ VREF
IFS '"
Lsa'
RREF
BI B2 83 B4 85 BS 87 a8
10
RREf
IFS for all
For fixed reference, TTL operation,
IRI4,
AU
iO ~
+
logic states
'0
+vREF
X 255
256
typical values are:
-VREF
~r
-v
VREF
~
10.000V
RREF
~
5.000k
II
R15 '" RREF
Cc ~ 0,01 ".F
.
VLC
~
OV (Ground)
TL/H/5686-5
FIGURE 3. Basic Positive Reference Operation (Note 4)
DAClaDO
DACIiIDO
R15
-VREf 0--0-""'1""'-11&
TL/H/5686-16
_ -VREF 255
IFS---XRREF
256
TL/H/5686-21
FIGURE 4. Recommended Full Scale Adjustment Circuit
(Note 4)
Note. RREF sets IFS; R15 is
for bias current cancellation
FIGURE 5. Basic Negative Reference Operation (Note 4)
4·25
Typical Applications (Continued)
DIGITAL INPUTS
MSa
LSI'
B18ZB3B4ISB&B7B1
ED
IREF"ZIIIA
TLlH/568S-17
B1 B2 B3 B4 B5 B6 B7 B8 lomA
1 1 1
1 1
1
1 1 1.992
1 1 1 1
1
1
1 0 1.984
1 0
0
1 1.008
0 0
0 0
Full Scale
Full Scale-LSB
Half Scale + LSB
Half Scale
Half Scale- LSB
Zero Scale + LSB
Zero Scale
1
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
1
0
1.000
0.992
0.008
0.000
lomA
Eo
Eo
0.000 -9.960 0.000
0.008 -9.920 -0.040
0.984 -5.040 -4.920
0.992
1.000
1.984
1.992
-5.000
-4.960
-0.040
0.000
-4.960
-5.000
-9.920
-9.960
FIGURE 6. Basic Unipolar Negative Operation (Note 4)
r - - - - I o I•••~~~~~+10.000Y
"'REF-2m"
••
DACDBOD
Iii z
TLlH/S666-S
B1 B2 B3 B4 B5 B6 B7 B8
EO
Pos. Full Scale
1 1 1 1 1 1 1 1 -9.920
Pos. Full Scale-LSB 1 1 1 1 1 1 1 0 -9.840
Zero Scale + LSB
1 0 0 0 0 0 0 1 -0.080
Zero Scale
1 0 0 0 0 0 0 0
0.000
Zero Scale - LSB
0 1 1 1 1 1 1 1 +0.080
Neg. Full Scale + LSB 0 0 0 0 0 0 0 1 +9.920
Neg. Full Scale
0 0 0 0 0 0 0 0 +10.000
FIGURE 7. Basic Bipolar Output Operation (Note 4)
Eo
+10.000
+9.920
+0.160
+0.080
0.000
-9.840
-9.920
6k
"l
I• •
VREf",1DV
Eo .. Vw (-255
2X)
2ii'" + 'iii
DACDno
where X Is the Input code end
RL ~ f'lL = RREF
Iii z
TL/H/SSB6-'S
If Rl =
RL within ± 0.05%. output is symmetrical about ground
B1 B2 B3 B4 B5 B6 B7 B8
Pos. Full Scale
Pos. Full Scale-LSB
( + )Zero Scale
( - )Zero Scale
Neg. Full Scale + LSB
Neg. Full Scale
1
1
1
0
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
0
0
1
1
0
Eo
+9.960
+9.880
+0.040
-0.040
-9.880
-9.960
FIGURE 8. Symmetrical ,Offset Binary Operation (Note 4)
4·26
c
~
o
Typical Applications (Continued)
co
o
o
......
C
~
o
co
....
......
o
DAC0800
255
256 IREF
TL/H/5686-19
For complementary output (operation as negative logic DAe), connect inverting inpul of op amp 10
(pin 2). connect 10 (pin 4) 10 ground.
10
N
FIGURE 9. Positive Low Impedance Output Operation (Note 4)
255
IFS" 256 IREF
DACOlao
TLlH/5686-20
For complementary output (operation as a negative logic CAe) connect non-inverting inpul of op am 10
(pin 2); connect 10 (pin 4) 10 ground.
10
FIGURE 10. Negative Low Impedance Output Operation (Note 4)
VTH
~
VLC
+
I.4V
15V CMOS. HTL. HNIL
VTH
~
7.6V
PMOS
VTH"'QV
+v REF
9
RREF
RESISTOR
f~{OPTIONAL
FOR OFFSETINPUTS
R'N
r:-------4'~L_y,f'v_.,
o-.llJ\IY...~.~-t 14
Dyn
REa ~200
OAC080D
Rp
NO CAP
n
TL/H/5686-10
Typical values: RIN~5k.+V'N~10V
TLlH/5686-9
Note. Do not exceed negative logic input range of DAC.
FIGURE 11. Interfacing with Various Logic Families
FIGURE 12. Pulsed Reference Operation (Note 4)
4·27
~
o
co
o
~
o
GO
o
r------------------------------------------------------------------------------------,
g
......
.,...
Typical Applications
(a) IREF 2 peak negative swing of liN
o
GO
o
!
g
......
(b)
+ VREF must be above peak positive swing of VIN
IREF
g
~
(Continued)
VIN~
VIN~
R15
IDPTIONAL)
o--'IIV'v---i15
DACDBDD
HIGH INPUT------.
OACOBOD
IMPEDANCE
TL/H/5686-12
TUH/5686-11
FIGURE 13. Accommodating Bipolar References (Note 4)
FOR TURN "ON", VL = 2.7V
0.1
FORTURN"OFF",VL"O.7V VLo-,,-ot
LI 1..
50"~_
MINIMUM
5V
lk
CAPACITANCE"
HP5082·2BOO
SCHOTTKY DIODES
VCLo-. ._ _.....
O.7V
"'1: OV
0•4V
VOUT
1 X PROBE
r- OV
...J--OAV
RREF
RI5
......'VIo"""otI5
13
DACOBID
(D.U.T.1
lOUT
-15V
TO D.U.T .
-15V
TL/H/5686-7
FIGURE 14. Settling Time Measurement (Note 4)
4-28
Typical Applications
~
(Continued)
o
CO
o
o
......
r5V S70P
OV ....J
CDNVERSIDN
FREE
RUN
C
l;
oCO
...o
1&
5V
......
VCC
C
0M2502
SAR
l;
GNO
DO Dl QZ QJ D4 as DB D7
3
5 & 11 12 13 14
oCO
•
':"
LSB
o
I\)
t
15V
5V
8·BIT DIGITAL
WORD
15V
R4
3.BM
Msa
VREF
Rl
5k
R2
5k
R3
5k
lk
12 11 10 9 B 7 & 5
14 LSa B7 BB B5 B4 B3 B2 MSB
VR+
Iii
DACDBQO
1k
-15V
51
10""
Note. For 1 ,",,8 conversion time with a-bit resolution and 7-bit accuracy, an
-15V
FIGURE 15. A Complete 2
LM36t comparator replaces the LM3t9 and the reference current is doubled
by reducing Rt, R2 and R3 to 2.5 kO and R4 to 2 MO.
TLlH/5686-B
"'S Conversion Time, 8-Blt AID Converter (Note 4)
4-29
~National
~ Semiconductor
OAC0808/0AC0807/0AC0806 8-Bit 01 A Converters
General Description
The DACOBOB series is an B-bit monolithic digital-to-analog
converter (DAC) featuring a full scale output current settling
time of 150 ns while dissipating only 33 mW with ± 5V supplies. No reference current (IREF) trimming is required for
most applications since the full scale output current is typically ± 1 LSB of 255 IREFI 256. Relative accuracies of better than ± 0.19% assure 8-bit monotonicity and linearity
while zero level output current of less than 4 /LA provides
B-bit zero accuracy for IREF;;,2 mAo The power supply currents of the DAC080B series are independent of bit codes,
and exhibits essentially constant device characteristics over
the entire supply voltage range.
The DACOB08 will interface directly with popular TTL, DTL
or CMOS logic levels, and is a direct replacement for the
MC150B/MC140B. For higher speed applications, see
DAC0800 data sheet.
Features
•
•
•
•
•
Relative accuracy: ±0.19% error maximum (DACOB08)
Full scale current match: ± 1 LSB typ
7 and 6-bit accuracy available (DACOB07, DACOB06)
Fast settling time: 150 ns typ
Noninverting digital inputs are TTL and CMOS compatible
• High speed multiplying input slew rate: B mAl /Ls
• Power supply voltage range: ± 4.5V to ± lBV
• Low power consumption: 33 mW @ ± 5V
Block and Connection Diagrams
MS.
RANGE
Dual-In-Line Package
LSB
?Y
YY? YY ?
CURRENT SWITCHES
CONTROL
I
NCCNDTEl)..!.
~
II
Ro2R LADOER
Order Number
DAC0808, DAC0807,
orDAC0806
See NS Package
NumberJ16A,
M16AorN16A
10
GNO
BIAS CIRCUIT
'--_ _ _--.....1
VREfl+lo--H~;:::::=::::;J--"C:=::---'=:::;-.L-1-o vcc
t'
NPM CU~~!~:
........
VREFI_lo.....l-:V-t_..::SO""U":::CE"'PA"""'-I
l.!":!!!E;:':.':!!!,"!!!E.!!CE!!'~~~~~~'~~_---1--t"'\CDMPEN
CURRENT AMP
------,... •
V~E
TL1H/5687-1
u
~VREFI"I
VEE.2
lO-..!
MSI A1..!
tl!- COMPENSATI ON
~VREFH
GNU..!.
DACUl.S
SERIES
~v(C
~A'
.,..!
.,2
t1!-A&
.. ..!
r!-.,
LSB
j!!..,
TOP VIEW
TL/H/5687-2
Small-Outline Package
Vr:c
1
V,EF(-)
2
V'EF(-)
3
lie-AS LS8
15j-A7
14j-AI
COMPENSATION
4
13
AS
Ne
5
12
A4
A3
GND
I
11
VEE
7
10
10
8
9
A2
Al USB
TL/H/5687-13
Top View
Ordering Information
ACCURACY OPERATING TEMPERATURE f -_ _ _ _ _ _ _,.--'O:;..;R..:.:D:,;:E"'R:;..;N.o.;U:;,;;M:;;;:B:..:E"'R;:,::S_-.._ _ _ _ _ __
RANGE
J PACKAGE (J16A)*
N PACKAGE (N16A)*
SO PACKAGE (M16A)
8-bit
8-bit
7-bit
6-bit
-55·C,;;TAS: + 125·C
O·C,;;TAS: + 75·C
O·CS:TAS: + 75·C
O·CS:TAS: + 75·C
DACOBOBLJ
DACOBOBLCJ
DACOB07LCJ
DAC0806LCJ
MC150BLB
MC140BLB DAC080BLCN MC140BPB
MC140BL7 DACOB07LCN MC140BP7
MC140BL6 DACOB06LCN MC140BP6
"Note. Devices may be ordered by using either order number.
4-30
DACOBOBLCM
DAC0807LCM
DAC0806LCM
Absolute Maximum Ratings
g
o<:)
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Power Supply Voltage
Vcc
VEE
Digital Input Voltage, V5-V12
+ 1BVoc
- 1BVoc
-10Vocto + 1BVoc
Applied Output Voltage, Vo
-11 Vocto +1BVoc
Reference Current, 114
Storage Temperature Range
Lead Temp. (Soldering, 10 seconds)
Dual-In-Line Package (Plastic)
Dual-In-Line Package (Ceramic)
Surface Mount Package
Vapor Phase (60 seconds)
Infrared (15 seconds)
Power Dissipation (Note 3)
Vcc, VEE
1000mW
ESD Susceptibility (Note 4)
TBD
260'C
300'C
Temperature Range
DACOBOBL
DACOBOBLC Series
215'C
220'C
Electrical Characteristics
Symbol
Parameter
Conditions
TA = 25'C (Note 6),
(Figure 5)
TA = 25'C, (Figure 5)
tpLH, tpHL
Propagation Delay Time
TClo
Output Full'Scale Current Drift
MSB
VIH
VIL
Digilallnput Logic Levels
High Level, Logic "1 "
Low Level, Logic "0"
(FigureS)
MSB
Digital Input Current
High Level
Low Level
(FigureS)
VIH = 5V
VIL = O.BV
Reference Input Bias Current
(FigureS)
Output Current Range
(FigureS)
VEE = -5V
VEE = -15V, TA = 25'C
115
10
Output Current
Output Current, All Bits Low
Output Voltage Compliance (Note 2)
VEE=-5V,IREF=1 mA
VEE Below -1 OV
Min
Typ
Max
±0.19
%
±0.39
±O.7B
%
%
ns
150
30
100
±20
ns
ppml'C
2
VREF = 2.000V,
R14 = 10000.,
(FigureS)
(FigureS)
Units
%
(Figure 4)
Relative Accuracy (Error Relative
to Full Scale 10)
DACOBOBL (LM150B-B),
DACOBOBLC (LM140B-B)
DACOB07LC (LM140B-7), (Note 5)
DACOB06LC (LM140B-6), (Note 5)
Settling Time to Within 1f2 LSB
(Includes tpLH)
O.B
Voc
Voc
0
-0.003
0.040
-O.B
mA
mA
-1
-3
",A
0
0
2.0
2.0
2.1
4.2
mA
mA
1.9
1.99
0
2.1
4
mA
",A
-0.55, +0.4
-5.0, +0.4
Voc
Voc
E,"; 0.19%, TA = 25'C
4-31
<:)
g
o
CO
<:)
.....
......
g
TMIN ,,; TA"; TMAX
-55'C,,; TA"; + 125'C
o ,,;TA"; +75'C
(Vcc = 5V, VEE = -15 Voc, VREF/R14 = 2 mA, DACOBOB:TA = -55'Cto + 125'C, DACOBOBC, DACOB07C, DACOB06C, TA
= O'C to + 75'C, and all digital inputs at high logic level unless otherwise noted.)
E,
CO
CO
......
<:)
Operating Ratings
5mA
Reference Amplifier Inputs, V14, V15
-65'Cto + 150'C
o<:)
CO
<:)
en
U) , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,
o
CD
o
~
......
.....
o
~
Electrical Characteristics
(Continued)
(Vee = SV, VEE = -1S Voe, VREF/R14 = 2 mA, DACOBOB: TA = -SS·Cto
12S·C, DACOBOBC, DACOB07C, DACOB06C, TA
= O·C to
7S·C, and all digital inputs at high logic level unless otherwise noted.)
Symbol
Parameter
SRIREF
Reference Current Slew Rate
(Figure 6)
Output Current Power Supply
Conditions
-SV:s; VEE :s; -16.SV
Min
Typ
4
B
Max
Units
mA/p.s
O.OS
2.7
p.AIV
2.3
-4.3
22
-13
mA
S.O
-1S
S.S
Voe
-16.S
Voe
Sensitivity
......
CD
o
~
+
+
Power Supply Current (All Bits
(Figure 3)
Low)
(J
Icc
~
lEE
Power Supply Voltage Range
TA =
mA
2S·C, (Figure 3)
4.S
-4.S
Vee
VEE
Power Dissipation
All Bits Low
All Bits High
Vee = SV, VEE = -SV
33
170
mW
Vee = SV, VEE = -15V
106
305
mW
Vee = 1SV, VEE = -SV
90
mW
160
mW
Vee = 1SV, VEE = -1SV
Nole 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: Range control is not required.
Nole 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX' 8JA. and the ambient temperature, TA. The maximum
allowable power dissipation at any temperature is Po = (TJMAX - T,J18JA or the number given in the Absolute Maixmum Ratings, whichever is lower. For this
device, TJMAX = 125°C, and the typical Junction~to-ambiBnt thermal resistance of the dual-in-line J package when the board mounted Is 1OcrC/W. For the dual-inline N package,this number increases to 175'C/W and for the small outline M package this number is 100·C/W.
Nole 4: Human body model, 100 pF discharged through a 1.5 kO resistor.
Note 5: All current switches are tested to guarantee at least 50% of rated current.
Nole 6: All bits switched.
Note 7: Pin·out numbers for the DALOBOX represent the dual-in-line package. The small outline package pinout differs from the dual·in-line package.
Typical Application
Ycc· 5V
13
",""e>--."'....."""---o
lo.aOOY" VREF
DIGITAL
INPUTS
TUH/5687-3
FIGURE 1.
+ 10V Output Digital to Analog Converter (Note 7)
4-32
Typical Performance Characteristics
=
Vee
5V, VEE
=
=
-15V, TA
25'C, unless otherwise noted
Logic Input Current vs
Input Voltage
Bit Transfer Char;lcteristics
1.4
"...::;
11
=
~
0.8
:;;
..
0.6
~
AI THROUGH A8
I I I III
r
E
1J lLll
0.2
"...
= 1.6
I
VEE' -5V
I
I I
r
0.8
0.6
~
0.4
,
...... r--.
......
0.2
o
-55 -31-19 -1 11 35 53 11 89 101125
TA - TEMPERATURE ('C)
Typical Power Supply
Current vs Temperature
8.0
".
oS
I-
~
:;;
~-4fmRE
-8
o
1.0
6.0
lEE
5.0
4.0
5=
3.0
Ie
1.0
III
ALL BITS HIGH OR LOW
"4=2mA
2.0
f-r- -
"""
ICC
T
-12
-14 -10 -6 -Z
2
6
10
14
lB
-50
Typical Power Supply
Current vs VEE
ALL BITS HIGH OR LOW
J 1- I-
-,---rIEE\oI1T~ll~'ZrnA
50
100
150
IEIE W!TH ! ) 1 JA
--
lEE WITH 1,4' O.Z rnA
I
w
>
IfC
I
VEE - NEGATIVE POWER SUPPLY (VI
-
~
:;;""
~
.
ICC
o Z 4
6
B 10 12 14 16 18 ZO
VCC - POSITIVE POWER SUPPLY (V)
100
150
Reference Input
Frequency Response
ALL BITS HIGH OR LOW
1,4'ZrnA
r-r-
o -Z -4 -6 -8 -10-IZ-14-16-18-Z0
50
TEMPERATURE I"CI
Typical Power Supply
Current vs Vee
lEE
--
-50
TEMPERATURE f·CI
Vo - OUTPUT VOLTAGE (VI
o
1.2
~
I
!;
11~~0.lmA
E D.4
lZ I-~~~~~~~I-H
w
'"~
IJ4-tA
--
......
1.4
Output Voltage Compliance
vs Temperature
~
l:l
~.
A4
ZO~~rn
16~
114'2 rnA
1.2
--
VL -lOGIC INPUT VOLTAGE (VI
I I
ALL BITS "ON"
2.4
~
f-?:
-12-10-8-6-4-2024681012141618
Output Current vs Output
Voltage (Output Voltage
Compliance)
VEE' -15V
A3
-V'-5V
1.8
1.6
~ 0.;
?;
VL - LOGIC INPUT VOLTAGE (VI
oS
..
%
-12-10-8-6-4-2024681012141618
2.8
+/t
g
9
~Z
-V'-15V
0.4
'"~
~,
oS
Il
1:
~
1,4'ZrnA
Logic Threshold Voltage vs
Temperature
~
=
B
'A
-Z
-4
-6
-B
-10
-12
-14
-16
"-"\
0.1
C
0.3
10
f - FREQUENCY (MH.)
TUH/5687-5
Unless otherwise specified: A14 =
A15 = 1 kn, C = 15 pF, pin 16 to
VEE; AL = 500., pin 4 to ground.
Curve A: Large Signal Bandwidth
Method of Figure 7, VREF = 2 Vp-p
offset 1 V above ground.
Curve B: Small Signal Bandwidth
Method of Figure 7, AL = 2500., VREF
= 50 mVp-p offset 200 mV above
ground.
Curve C: Large and Small Signal
Bandwidth Method of Figure 9 (no op
amp, AL = 500.), As = 500., VREF =
2V, Vs = 100 mVp-p centered at OV.
4-33
III
DAC0808/DAC0807/DAC0806
Vee
MS.
GND
At
AI
AJ
A4
A5
At
Al
LS.
At
I
13
"
t1
11
~
•
+vREFO -.,
,
i
-VREFO)o!'!I'I---r-li
....,---1--'..
111
COMPO
Ir
VEE
TL/H/5687 -4
FIGURE 2. Equivalent Circuit of the DAC0808 Series (Note 7)
c
~
o
Test Circuits
Vee
I~
DIGITAL
INPUTS
co
o
VI and 11 apply to inputs A1-A8.
The resistor tied to pin 15 is to temperature compensate the
bias current and may not be necessary for all applications.
10 = K
A5
A7
A.
:i ' 'I
"2 + "4
A4
A5
+ 16 + 32
+
A6
64
A7
128
+
+
A8 )
256
~
o
co
o
C
~
o
AN = "0" if AN is at low level
VEE
C
.....
.....
and AN = "1" if AN is at high level
RL
',-
A2
where K "" VREF
R14
t'-o---....-o ~8TPUT
AI
( A1
co
.....
co
o
en
TUH/56B7-6
FIGURE 3. Notation Definitions Test Circuit (Note 7)
MSB
A'
88IT
COUNTER
TL/H/56B7-7
VEE
FIGURE 4. Relative Accuracy Test Circuit (Note 7)
UV--..,.------""""',
"N
D.4V
2Voc
"
I'HL "IPlHSlOns
D.7V
USE AL TO GND FOR TURN "OFF"
MEASUREMENT (SEE TEXT)
SEnLlNGTlME
~D.l,.F
'0IFIGURE5)
lk~
FOR SETTLING TIME
ts- 1&DnsTYP
~O---"",-""o()eo =~~~~~E:~~~L~,:':f
TO±l/ZLSB
~COS"Z5PF
TRANSIENT
RESPONSE
lN4454 (LOW CAPACITANCE,
FAST RECOVERY DIODE)
-----J! I
RL-50
PIN4TO GNn
-10DnV--W.....
VEE
TLiH/56B7-B
FIGURE 5. Transient Response and Settling Time (Note 7)
4-35
II
~
I
.-----------------------------------------------------------------------------.
Test Circuits (Continued)
Vee
vee
;:::
R14 .. RI5
g
o
AI
~
C
t-o-......""'M....O VRH
AZ
ZVo-n
-.I L-
A3
;;0
..r1..
I
A4
!
"'REF
RI4
RU
15
A5
ljj
"'LI'
AD
A7
c
SCOPE
zm:~
RL
AS
":"
SLEWING
TIME
dl
I
SEE TEXT FOR VALUES OF e
dV
iii = ilL iit
VeE
TUH/56B7-10
FIGURE 7. Positive VREF (Note 7)
TUH/56B7-9
FIGURE 6. Reference Current Slew Rate Measurement (Note 7)
Vee
Vs
RI4a
17Voc
Voltage at Any Digital Input
VeetoGND
±25V
Voltage at VREF Input
Package Dissipation
at T A = 25°C (Note 3)
Temperature Range
500mW
DC Voltage Applied to
IOUT1 or IOUT2 (Note 4)
ESD Susceptability (Note 14)
215°C
220°C
Part numbers with 'LCN' suffix
-100mVtoVee
800V
TMIN:O::TA:O::TMAX
O°Cto +70°C
Part numbers with 'LCWM' suffix
O°Cto +70°C
Part numbers with 'LCV' suffix
O°Cto +70°C
Part numbers with' LCJ' suffix
Part numbers with 'LJ' suffix
-40°C to +85°C
-55°C to + 125°C
Voltage at Any Digital Input
Vee to GND
Electrical Characteristics VREF= 10.000 Voe unless otherwise noted. Boldface limits apply over temperature, TMIN:O::TA:O::TMAX- For all other limits TA =25°C.
Parameter
See
Note
Conditions
Vee = 5 Vee ±5%
Vee = 4.75 Vee
Vee = 12 Vee ±5%
Vee = 15.75 Vee
to 15 Vee ± 5%
Tested
Typ
Limit
(Note 12)
(Note 5)
Limit
Units
Design Limit
(Note 6)
CONVERTER CHARACTERISTICS
Resolution
8
Zero and full scale adjusted
-10V:O::VREF:O:: + 10V
Linearity Error Max
Differential Nonlinearity
Max
DAC0830LJ & LCJ
DAC0832LJ & LCJ
DAC0830LCN, LCWM & LCV
DAC0831LCN
DAC0832LCN, LCWM & LCV
Zero and full scale adjusted
-10V:O::VREF:O:: + 10V
Monotonicity
-10V:O::VREF
:O::+10V
Using Internal RIb
-10V:O::VREF:O:: + 10V
Gain Error Tempco Max
Using internal RIb
Power Supply Rejection
All digital inputs latched high
Vce= 14.5V to 15.5V
11.5V to 12.5V
4.5Vto 5.5V
Reference Input
I
I
8
bits
0.05
0.2
0.05
0.1
0.2
0.05
0.2
0.05
0.1
0.2
%FSR
%FSR
%FSR
%FSR
%FSR
0.1
0.4
0.1
0.2
0.4
0.1
0.4
0.1
0.2
0.4
%FSR
%FSR
%FSR
%FSR
%FSR
8
8
8
8
bits
bits
±1
±1
%FS
0.0006
%
Fsrc
4,8
LJ & LCJ
LCN, LCWM & LCV
Gain Error Max
8
4,8
DAC0830LJ & LCJ
DAC0832LJ & LCJ
DAC0830LCN, LCWM & LCV
DAC0831LCN
DAC0832LCN, LCWM & LCV
4
7
±0.2
0.0002
%
FSRIV
0.0002
0.0006
0.013
0.0025
Max
15
20
20
k!1
Min
15
10
10
k!1
Output Feedthrough Error
VREF=20 Vp-p, f= 100 kHz
All data inputs latched low
3
4-39
co
t.)
o
.......
c
»
o
o
co
t.)
.....
c
»
oo
.......
Operating Conditions
- 65°C to + 150°C
Storage Temperature Range
260°C
300°C
0.015
mVp-p
co
t.)
N
('II
C')
co
o
o
«
c.......
.,...
Electrical Characteristics
VREF= 10.000 VDC unless otherwise noted. Boldface limits apply over temperature, TMIN"TA"TMAX' For all other limits TA = 25"C. (Continued)
C')
co
o
o
«
c.......
Parameter
See
Note
Conditions
Typ
(Note 12)
oC')
CO
o
o
~
Vee = 4.75 Voe
Vee = 15.75 Voe
Tested
Limit
(Note 5)
Vee = 5 Voe ±5%
Vee = 12Voe ±5%
to 15Voe ±5%
Limit
Units
Design limit .
(Note 6)
CONVERTER CHARACTERISTICS (Continued)
Output Leakage
Current Max
Output
Capacitance
10
100
50
100
100
nA
100
50
100
100
nA
IOUT1
All data inputs
latched low
LJ & LCJ
LCN, LCWM & LCV
IOUT2
All data inputs
latched high
LJ & LCJ
LCN, LCWM & LCV
IOUT1
IOUT2
All data inputs
latched low
45
115
pF
IOUT1
IOUT2
All data inputs
latched high
130
30
pF
DIGITAL AND DC CHARACTERISTICS
Digital Input
Voltages
Digital Input
Currents
Supply Current
Drain
Max
Logic Low
LJ
4.75V
LJ
15.75V
LCJ
4.75V
LCJ
15.75V
LCN, LCWM, LCV
0.6
0.8
0.7
0.8
0.95
0.8
LJ & LCJ
LCN, LCWM, LCV
2.0
1.9
2.0
2.0
VDC
VDC
Min
Logic High
Max
Digital inputs <0.8V
LJ & LCJ
LCN, LCWM, LCV
-50
-200
-160
-200
-200
)J-A
)J-A
Digital inputs> 2.0V
LJ & LCJ
LCN, LCWM, LCV
0.1
+10
+8
+10
+10
)J-A
1.2
3.5
3.5
1.7
2.0
Max
LJ & LCJ
LCN, LCWM, LCV
4·40
mA
Electrical Characteristics VREF= 10.000 Voc unless otherwise noted. Boldface limits apply over temperature, TMIN S:TAS:TMAX' For all other limits TA = 25°C. (Continued)
Vcc= 15.75 VOC
Symbol
Parameter
Conditions
See
Note
Typ
(Note 12)
VCC= 12 Voc±50/0
Vcc=4.75Voc
to 15 Voc ±50/0
Tested
Design
Limit
Limit
(Note 5)
(Note 6)
Typ
(Note 12)
Tested
Vcc= 5Voc
±50/0
Design
Limit
Limit
(Note 5)
(Note 6)
Limit
Units
AC CHARACTERISTICS
Current Setting
ts
VIL =OV, VIH=5V
Write and XFER
tw
VIL =OV, VIH=5V
Pulse Width Min
tos
Data Setup Time
Min
tOH
Data Hold Time
VIL =OV. VIH=5V
Min
tcs
Control Setup Time VIL=OV. VIH=5V
Min
tCH
Control Hold Time
11
100
VIL =OV. VIH=5V
Min
9
100
9
110
".S
600
900
375
900
320
30
50
50
600
250
a
0
10
a
900
ns
900
1100
320
900
600
30
320
a
375
320
250
320
9
9
250
320
9
VIL =OV, VIH=5V
1.0
1.0
Time
1100
a
0
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Nole 2: All voltages are measured with respect to GNO, unless otherwise specified.
Nole 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, OJA, and the ambient temperatura, TA. The maximum
allowable power dissipation at any temperature is Po ~ (TJMAX - TA)/OJA or the number given in the Absolute Maximum Ratings, whichever is lower. For this
device, TJMAX ~ 125'C (plastic) or t50'C (ceramic), and the typical junction·to·ambient thermal resistance of the J package when board mounted is BO·C/W. For
the N package, this number increases to 100'C/W and for the V package this number is 120·C/W.
Nole 4: For current switching applications, both IOUT1 and IOUT2 must go to ground or the "Virtual Ground" of an operational amplifier. The linearity error is
degraded by approximately Ves ... VREF. For example, if VREF ~ 1OV then a 1 mV offset, VOS, on IOUT1 or IOUT2 will introduce an additional 0.01 % linearity error.
Nole 5: Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level).
NDte 6: Guaranteed, but not 100% production tested. These limits are not used to calculate outgoing quality levels.
Note 7: Guaranteed at VREF~ ± 10 Voc and VREF~ ± 1 Voc.
Nole 8: The unit "FSR" stands for "Full Scale Range." "Linearity Error" and "Power Supply Rejection" specs are based on this unit to eliminate dependence on a
particular VREF value and to indicate the true performance 01 the part. The "Linearity Error" specification 01 the OACOB30 is "0.05% of FSR (MAX)". This
guarantees that alter performing a zero and lull scale adjustment (see Sections 2.5 and 2.6), the plot of the 256 analog voltage outputs will each be within
0.05% XVREF of a straight line which passes through zero and lull scale.
Nole 9: Boldlace tested limits apply to the LJ and LCJ suflix parts only.
Note 10: A 100nA leakage current wHh Rfb~20k and VREF~ 10V corresponds to a zero error of (100X 10-9 X20X 103)X 100/10 which is 0.02% 01 FS.
Nole 11: The entire write pulse must occur within the valid data interval for the specified tw,
Note 12: Typicals are at 25'C and represent most likely parametric norm.
Nole 13: Human body model, 100 pF discharged through a 1.5 kO resistor.
4-41
los, IoH, and Is to apply.
N
C")
co
0
0
I"-
VIL
IOUT1 IOUT2
VALID DAC DATA
ir
tS
-
-" .....50%
F
rSmLEOTO
±'/,LSB
TL/H/560B-2
Definition of Package Pinouts
Control Signals (All control signals level actuated)
CS:
Chip Select (active low). The CS in combination with ILE will enable WR1.
ILE:
Input Latch Enable (active high). The ILE in
combination with CS enables WR1.
Write 1. The active low WR1 is used to load the
WR1:
digital input data bits (DI) into the input latch.
The data in the input latch is latched when WR1
is high. To update the input latch-CS and WR1
must be low while ILE is high.
Write 2 (active low). This Signal, in combination
WR2:
with XFER, causes the 8-bit data which is available in the input latch to transfer to the DAC
register.
Transfer control signal (active low). The
XFER:
XFER will enable WR2.
Vee:
GND:
Other Pin Functions
010.017: Digital Inputs. Dlo is the least significant bit
(LSB) and DI7 is the most significant bit (MSB).
loun:
DAC Current Output 1. IOUT1 is a maximum
for a digital code of all 1's in the DAC register,
and is zero for all O's in DAC register.
IOUT2:
DAC Current Output 2. IOUT2 is a constant
minus IOUT1' or IOUT1 + IOUT2 = constant (I full
scale for a fixed reference voltage).
Rib:
Feedback Resistor. The feedback resistor is
provided on the IC chip for use as the shunt
feedback resistor for the external op amp which is
used to provide an output voltage for the DAC.
This on-chip resistor should always be used (not
an external resistor) since it matches the resistors
which are used in the on-chip R-2R ladder and
tracks these resistors over temperature.
Reference Voltage Input_ This input connects an
external precision voltage source to the internal R2R ladder. VREF can be selected over the range of
+ 10 to -10V. This is also the analog voltage input for a 4-quadrant multiplying DAC application.
Digital Supply Voltage. This is the power supply
pin for the part. Vcc can be from + 5 to + 15VDC.
Operation is optimum for +15VDC.
The pin 10 voltage must be at the same ground
potential as IOUT1 and IOUT2 for current switching
applications. Any difference of potential (Vos pin
10) will result in a linearity change of
Vospin 10
3VREF
For example, if VREF = 10V and pin 10 is 9mV
offset from IOUT1 and IOUT2 the linearity change
will be 0.03%.
Pin 3 can be offset ± 100mV with no linearity
change, but the logic input threshold will shift.
4-42
c
l;
Linearity Error
o
CD
w
o
......
C
l;
o
...w
......
CD
C
l;
DIGITAL INPUT
o
OIGiTALINPUT
OIGITALINPUT
TLlH/5608-3
a) End point test after
zero and fs adj.
b) Best straight line
c) Shifting fs adj. to pass
best straight line test
Definition of Terms
Resolution: Resolution is directly related to the number of
switches or bits within the DAC. For example, the DACOB30
has 28 or 256 steps and therefore has B-bit resolution.
Settling Time: Settling time is the time required from a code
transition until the DAC output reaches within ± 'lzLSB of
the final output value. Full-scale settling time requires a zero
to full-scale or full-scale to zero output change.
Linearity Error: Linearity Error is the maximum deviation
from a straight line passing through the endpoints of the
DAC transfer characteristic. It is measured after adjusting
for zero and full-scale. Linearity error is a parameter intrinsic
to the device and cannot be externally adjusted.
Full-Scale Error: Full scale error is a measure of the output
error between an ideal DAC and the actual device output.
Ideally, for the DACOB30 series, full-scale is VREF -1LSB.
For VREF= 1OV and unipolar operation, VFULL-5CALE=
10.0000V-39mV=9.961V. Full-scale error is adjustable to
zero.
National's linearity "end point test" (a) and the "best
straight line" test (b,c) used by other suppliers are illustrated
above. The "end point test" greatly simplifies the adjustment procedure by eliminating the need for multiple iterations of checking the linearity and then adjusting full scale
until the linearity is met. The "end pOint test" guarantees
that linearity is met after a single full scale adjust. (One adjustment vs. multiple iterations of the adjustment.) The "end
point test" uses a standard zero and F.S. adjustment procedure and is a much more stringent test for DAC linearity.
Differential Nonlinearity: The difference between any two
consecutive codes in the transfer curve from the theoretical
1 LSB is differential nonlinearity.
Monotonic: If the output of a DAC increases for increasing
digital input code, then the DAC is monotonic. An B-bit DAC
which is monotonic to B bits simply means that increasing
digital input codes will produce an increasing analog output.
Power Supply Sensitivity: Power supply sensitivity is a
measure of the effect of power supply changes on the DAC
full-scale output.
r--------------------l
IMSBIOI,
13 1
18
VREF
14
Ol,o-....;.;.t---I
Ol.o-":':'t---I
16
Ol,o-..:.:.t---I
112
loun
B·BIT
MULTIPLYING
O/A
CONVERTER
4
0130-""';:'+--1
loun
01,0--"----1
01,0--"----1
Rib
1
ILSBIOIoo-""':'_-I
1
ILE
I
I
191
U*
I
h
t---()GNO
I
I
I
11
I
I
21
II
120
cs~~
~;;:::~J
r-o Vcc
18 1
~'O:~~:::::::[~
mRO 17
I
1I 10
·NOTE: WHEN 11"="1", Q OUTPUTS FOLLOW 0 INPUTS:
I-!!-oGNO
L ______~E~~~·::..o~A~ ~I~~~:... __ J
TL/H/5608-4
FIGURE 1. DAC0830 Functional Diagram
4-43
CD
W
N
Typical Performance Characteristics
Digital Input Threshold
vs. Temperature
2.4
2.0
2.0
r--.
'":c 1.6 t--. r--r-r--!~15VDe
r--. t- r-..
>
~
c
iii
i!:
1.2
r--I:"-~
Vee ~ 5VDe r - t:--
~
i! O.B
~
iii
i!:
1.6
1.2
i! O.B
w
-0.075
!;
l-
...
..
c
:s
!i
400
300
ii
TA~25'e-
-0.125
"I 1
0
5
10
15
Vee. SUPPLY VOLTAGE (VDCI
0
~
~
100
........ :::..
.. , .,
~ -0,025
-0.05
t-
I--'"
J.l
W
VceB5V
Data Hold Time
V-
VIH~V
V
--
Vie~15Vje-
-0.1
-55-35-15 5 25 45 65 B5 105 125
TA. AMBIENT TEMPERATURE ('CI
5
10
15
Vee. SUPPLY VOLTAGE (VI
!i 200
-0.100
0.025
ffi
Write Pulse Width
i
LINEARITY ERROR
••• GAIN ERROR
0.05
-0.075
500
i'
f-.t ~ERJOR
z
~
TA~125·C
~
~
0
... ~INEARITY ERROR
0.000
.
~25'C
i..--
I - ~1--
~
Gain and Unearity Error
Variation VB. Supply Voltage
-0.05
TLlc
0.4
+0.025
~
-
>
0
-55-35-15 5 25 45 65 B5 105 125
TA. AMBIENT TEMPERATURE ('C)
#
0.1
0.075
<5
0.4
;;;: -0.025
Gain and Linearity Error
Variation vs. Temperature
a
a
<5
Digital Input Threshold
vs. Vee
2.4
V
vi-'"
!
I .....
~C=5V
VIHI=3~
VCC=12V~
l-
VIH=5V
IveC-12V, VIH=3V
VCC=15V, VIH=3V or 5V
-55-35-15 5 25 45 65 B5 105.125
TA. AMBIENT TEMPERATURE ('CI
~
;::
21:c
250
200
~
150
ej
100
.
~
~~;:;:'-r_
.Vce:15V,
II VIH=3V
50
VCC=12V,
VIH=3V Vc~tv:"
12V,15V
VIH =5V
r- "\
/
\/
-55-35-15 5 25 45 65 B5 105125
TA. AMBIENT TEMPERATURE ('C)
TL/H/5608-5
DAC0830 Series Application Hints
These DAC's are the industry's first microprocessor compatible, double-buffered 8-bit multiplying D to A converters.
Double-buffering allows the utmost application flexibility
from a digital control pOint of view. This 20-pin device is also
pin for pin compatible (with one exception) with the
DAC1230, a 12-bit MICRO-DAC. In the event that a system's analog output resolution and accuracy must be upgraded, substituting the DAC1230 can be easily accomplished. By tying address bit Ao to the ILE pin, a two-byte JLP
write instruction (double preCision) which automatically increments the address for the second byte write (starting
with Ao = "1 ") can be used. This allows either an 8-bit or the
12-bit part to be used with no hardware or software changes. For the simplest 8-bit application, this pin should be tied
to Vee (also see other uses in section 1.1).
system to be updated to their new analog output levels
simultaneously via a common strobe signal.
The timing requirements and logic level convention of the
register control Signals have been designed to minimize or
eliminate external interfacing logic when applied to most
popular microprocessors and development systems. It is
easy to think of these converters as 8-bit "write-only" memory locations that provide an analog output quantity. All inputs to these DAC's meet TTL voltage level specs and can
also be driven directly with high voltage CMOS logic in nonmicroprocessor based systems. To prevent damage to the
chip from static discharge, all unused digital inputs should
be tied to Vee or ground. If any of the digital inputs are
inadvertantly left floating, the DAC interprets the pin as a
logic "1".
Analog signal control versatility is provided by a precision R2R ladder network which allows full 4-quadrant multiplica·
tion of a wide range bipolar reference voltage by an applied
digital word.
1.1 Double-Buffered Operation
Updating the analog output of these DAC's in a double-buff·
ered manner is basically a two step or double write operation. In a microprocessor system two unique system ad·
dresses must be decoded, one for the input latch controlled
by the CS pin and a second for the DAC latch which is
controlled by the XFER line. If more than one DAC is being
driven, Figure 2, the CS line of each DAC would typically be
decoded individually, but all of the converters could share a
common XFER address to allow simultaneous updating of
any number of DAC's. The timing for this operation is
shown, Figure 3.
1.0 DIGITAL CONSIDERATIONS
A most unique characteristic of these DAC's is that the 8-bit
digital input byte is double·buffered. This means that the
data must transfer through two independently controlled 8bit latching registers before being applied to the R-2R lad·
der network to change the analog output. The addition of a
second register allows two useful control features. First, any
DAC in a system can simultaneously hold the current DAC
data in one register (DAC register) and the next data word in
the second register (input register) to allow fast updating of
the DAC output on demand. Second, and probably more
important, double·buffering allows any number of DAC's in a
It is important to note that the analog outputs that will
change after a simultaneous transfer are those from the
DAC's whose input register had been modified prior to the
XFER command.
4-44
g
oo
DAC0830 Series Application Hints (Continued)
CC)
w
o
.....
~o
ANALOG
OUTPUT 1
~
....
.....
c
»
o
oCC)
w
I\)
ANALOG
OUTPUT 2
"---L~ANALOG
OUTPUT n
SYSTEM"'
DAC DISABLE
"TIE TO LOGIC 1 IF NOT NEEDED (SEE SEC. 1.1).
FIGURE 2. Controlling Mutiple DACs
DATA BUS
~V~?--;_ _ __
cs
WRI & WIi2
\
\
n
/
II
(INPUT LATCH
UPDATED
mli
ILE
\ ~------,CTER
ANALOG OUTPUT - "
UPDATED
?I
\
=LOGIC "1"
LATCHED
TUH/5608-6
FIGURE 3
one controlling the DAC's to take over control of the data
bus and control lines. If this second system were to use the
same addresses as those decoded for DAC control (but for
a different purpose) the ILE function would prevent the
DAC's from being erroneously altered.
The ILE pin is an active high chip select which can be de·
coded from the address bus as a qualifier for the normal CS
signal generated during a write operation. This can be used
to provide a higher degree of decoding unique control sig·
nals for a particular DAC, and thereby create a more efficient addressing scheme.
In a "Stand-Alone" system the control signals are generated by discrete logic. In this case double-buffering can be
controlled by simply taking CS and XFER to a logic "0", ILE
to a logic "1" and pulling WRI low to load data to the input
latch. Pulling WR2 low will then update the analog output. A
logic "1" on either of these lines will prevent the changing
of the analog output.
Another useful application of the ILE pin of each DAC in a
multiple DAC system is to tie these inputs together and use
this as a control line that can effectively "freeze" the outputs of all the DAC's at their present value. Pulling this line
low latches the input register and prevents new data from
being written to the DAC. This can be particularly useful in
multiprocessing systems to allow a processor other than the
4-45
DAC0830 Series Application Hints (Continued)
~----~\~----~/
ANALOG
OUTPUT UPDATED
DATA
LATCHED
TL/H/560B-7
ILE~LOGIC "1"; WR2 and XFER GROUNDED
FIGURE 4
1.2 Slngle·Buffered Operation
In a microprocessor controlled system where maximum
data throughput to the DAC is of primary concern, or when
only one DAC of several needs to be updated at a time, a
single-buffered configuration can be used. One of the two
internal registers allows the data to flow through and the
other register will serve as the data latch.
Digital signal feedthrough (see Section 1.5) is minimized if
the input register is used as the data latch. Timing for this
mode is shown in Figure 4.
be met or erroneous data can be latched. This hold time is
defined as the length of time data must be held valid on the
digital inputs after a qualified (via CS) WR strobe makes a
low to high transition to latch the applied data.
If the controlling device or system does not inherently meet
these timing specs the DAC can be treated as a slow memory or peripheral and utilize a technique to extend the write
strobe. A simple extension of the write time, by adding a
wait state, can simultaneously hold the write strobe active
and data valid on the bus to satisfy the minimum WR pulsewidth. If this does not provide a sufficient data hold time at
the end of the write cycle, a negative edge triggered oneshot can be included between the system write strobe and
the WR pin of the DAC. This is illustrated in Figure 5 for an
exemplary system which provides a 250ns WR strobe time
with a data hold time of less than IOns.
The proper data set-up time prior to the latching edge (LO to
HI transition) of the WR strobe, is insured if the WR pulsewidth is within spec and the data is valid on the bus for the
duration of the DAC WR strobe.
Single-buffering in a "stand-alone" system is achieved by
strobing WRl low to update the DAC with CS, WR2 and
XFER grounded and ILE tied high.
1.3 Flow·Through Operation
Though primarily designed to provide microprocessor interface compatibility, the MICRO-DAC's can easily be configured to allow the analog output to continuously reflect the
state of an applied digital input. This is most useful in applications where the DAC is used in a continuous feedback
control loop and is driven by a binary up-down counter, or in
function generation circuits where a ROM is continuously
providing DAC data.
1.5 Digital Signal Feedthrough
When data is latched in the internal registers, but the digital
inputs are changing state, a narrow spike of current may
flow out of the current output terminals. This spike is caused
by the rapid switching of internal logic gates that are responding to the input changes.
Simply grounding CS, WR1, WR2, and XFER and tying ILE
high allows both internal registers to follow the applied digital inputs (flow-through) and directly affect the DAC analog
output.
1.4 Control Signal Timing
There are several recommendations to minimize this effect.
When latching data in the DAC, always use the input register as the latch. Second, reducing the Vee supply for the
DAC from + 15V to + 5V offers a factor of 5 improvement in
the magnitude of the feedthrough, but at the expense of
internal logic switching speed. Finally, increasing Cc (Figure
8) to a value consistent with the actual circuit bandwidth
requirements can provide a substantial damping effect on
any output spikes:
When interfacing these MICRO-DAC to any microprocessor,
there are two important time relationships that must be considered to insure proper operation. The first is the minimum
WR strobe pulse width which is specified as 900 ns for all
valid operating conditions of supply voltage and ambient
temperature, but typically a pulse width of only 180ns is
adequate if Vcc= 15VoC. A second consideration is that
the guaranteed minimum data hold time of 50ns should
4-46
g
oo
DAC0830 Series Application Hints (Continued)
OC)
Co)
DATA BUS
o
......
g
oo
OC)
Co)
....
......
DNE
SHDT
C
r.;
o
OC)
Co)
I\)
~J~ ~~_________D_M_A_~_L_ID___________~
WRITE
~\~~~~ - - - - ,
-l I-
I
SYSTEM DATA HOLD TIME « IDns)
NORMAL
ONE WAIT
-WRITE STRDBE~"- STATE (25Dn,)
Wii
(250n,)
(OUTPUT OF -----..,
DNE·SHDT)
1_
DACWR
_I
r--PULSE WIOTH~
(350n,)
_I
OAC
DATA HOLD TIME
(160n,)
1-TLiH/5608-8
FIGURE 5. Accommodating a High Speed System
2.0 ANALOG CONSIDERATIONS
The fundamental purpose of any D to A converter is to pro·
vide an accurate analog output quantity which is representa'
tive of the applied digital word. In the case of the DACOB30,
the output, IOUll, is a current directly proportional to the
product of the applied reference voltage and the digital input
word. For application versatility, a second output, IOUT2, is
provided as a current directly proportional to the complement of the digital input Basically:
Figure 6. The MOS switches operate in the current mode
with a small voltage drop across them and can therefore
switch currents of either polarity. This is the basis for the 4quadrant multiplying feature of this DAC.
2.2 Basic Unipolar Output Voltage
To maintain linearity of output current with changes in the
applied digital code, it is important that the voltages at both
of the current output pins be as near ground potential
(OVoc) as possible. With VREF= +10V every millivolt ap·
pearing at either IOUll or IOUT2 will cause a 0.01 % linearity
error. In most applications this output current is converted to
a voltage by using an op amp as shown in Figure 7.
I
- VREF x Digital Input.
256'
OUT1- 15kfl
I
VREF 255-Digitallnput
OUT2= 15 kfl x
256
The inverting input of the op amp is a "virtual ground" created by the feedback from its output through the internal 15
kfl resistor, Rib. All of the output current (determined by the
digital input and the reference voltage) will flow through RIb
to the output of the amplifier. Two-quadrant operation can
be obtained by reversing the polarity of VREF thus causing
IOUT1 to flow into the DAC and be sourced from the output
of the amplifier. The output voltage, in either case, is always
equal to IOUT1 X Rib and is the opposite polarity of the reference voltage.
The reference can be either a stable DC voltage source or
an AC Signal anywhere in the range from -10V to +10V.
The DAC can be thought of as a digitally controlled a\tenuator: the output voltage is always less than or equal to the
applied reference voltage. The VREF terminal of the device
presents a nominal impedance of 15 kfl to ground to external circuitry.
Always use the internal Rib resistor to create an output voltage since this resistor matches (and tracks with temperature) the value of the resistors used to generate the output
current (IOUT1).
where the digital input is the decimal (base 10) equivalent of
the applied a·bit binary word (0 to 255), VREF is the voltage
at pin a and 15 kfl is the nominal value of the internal resistance, R, of the R-2R ladder network (discussed in Section
2.1).
Several factors external to the DAC itself must be considered to maintain analog accuracy and are covered in subse·
quent sections.
2.1 The Current Switching R-2R Ladder
The analog circuitry, Figure 6, consists of a silicon-chromium (SiCr or Si-chrome) thin film R-2R ladder which is deposited on the surface oxide of the monolithic chip. As a result,
there are no parasitic diode problems with the ladder (as
there may be with diffused resistors) so the reference voltage, VREF, can range -10V to +10V even if VCC for the
device is 5Voc.
The digital input code to the DAC simply controls the position of the SPDT current switches and steers the available
ladder current to either IOUT1 or IOUT2 as determined by the
logic input level ("1" or "0") respectively, as shown in
4-47
~~------------------------------------------------------------~
CO)
CD
CI
g
......
....
DAC0830 Series Application Hints (Continued)
VREF o-_-~"",,,,,"",,,i\A._
••••••• r-.A,/\tv-_----.
CO)
CD
CI
g
......
Rib
"1"
CI
L-+-....-t--"--t---~~+-..!.~f...----.l.-o
---"-----~~--..!.----__o
CO)
~
I - - -....
IOUT1
IOUT2
FIGURE 6
DIGITAL
INPUT
'>~~o Your
=-(lOUT! x Rib)
VREF (DlGll~~ INPUTho
\
FIGURE 7
Vos ADJUST
Yee
TLlHI5608-9
2.3 Op Amp Considerations
This configuration features several improvements over existing circuits for bipolar outputs with other multiplying
DACs. Only the offset voltage of amplifier 1 has to be nulled
to preserve linearity of the DAC. The offset voltage error of
the second op amp (although a constant output voltage error) has no effect on linearity. It should be nulled only if
absolute output accuracy is required. Finally, the values of
the resistors around the second amplifier do not have to
match the internal DAC resistors, they need only to match
and temperature track each other. A thin film 4-resistor network available from Beckman Instruments, Inc. (part no.
694-3-R10K-D) is ideally suited for this application. These
resistors are matched to 0.1 % and exhibit only 5 ppml'C
resistance tracking temperature coefficient. Two of the four
available 10 kO resistors can be paralleled to form R in
Figure 9 and the other two can be used independently as
the resistances labeled 2R.
The op amp used in Figure 7 should have offset voltage
nulling capability (See Section 2.5).
The selected op amp should have as Iowa value of input
bias current as possible. The product of the bias current
times the feedback resistance creates an output voltage er·
ror which can be significant in low reference voltage appli·
cations. BI-FET op amps are highly recommended for use
with these DACs because of their very low input current.
Transient response and settling time of the op amp are im·
portant in fast data throughput applications. The largest stability problem is the feedback pole created by the feedback
resistance, Rib, and the output capacitance of the DAC.
This appears from the op amp output to the (-) input and
includes the stray capacitance at this node. Addition of a
lead capacitance, Cc in Figure 8, greatly reduces overshoot
and ringing at the output for a step change in DAC output
current.
2.5 Zero Adjustment
Finally, the output voltage swing of the amplifier must be
greater than VREF to allow reaching the full scale output
voltage. Depending on the loading on the output of the amplifier and the available op amp supply voltages (only ± 12
volts in many development systems), a reference voltage
less than 10 volts may be necessary to obtain the full analog output voltage range.
For accurate conversions, the input offset voltage of the
output amplifier must always be nulled. Amplifier offset errors create an overall degradation of DAC linearity.
The fundamental purpose of zeroing is to make the voltage
appearing at the DAC outputs as near OVoc as possible.
This is accomplished for the typical DAC - op amp connection (Figure 7) by shorting out Rib, the amplifier feedback
resistor, and adjusting the Vos nulling potentiometer of the
op amp until the output reads zero volts. This is done, of
course, with an applied digital code of all zeros if IOUll is
driving the op amp (all one's for IOUT2). The short around
Rib is then removed and the converter is zero adjusted.
2.4 Bipolar Output Voltage with a Fixed Reference
The addition of a second op amp to the previous circuitry
can be used to generate a bipolar output voltage from a
fixed reference voltage. This, in effect, gives sign significance to the MSB of the digital input word and allows twoquadrant multiplication of the reference voltage. The polarity
of the reference can also be reversed to realize full 4-quadrant multiplication: ±VREFX ±Digital Code= ±VOUT. This
circuit is shown in Figure 9.
4-48
c
~
o
DAC0830 Series Application Hints (Continued)
QC)
Cc
IOUT1~:--""'---;
DACD83D
IOUT2,......~_+-
__
ts
(0 to Full Scale)
OPAmp
Cc
LF356
LF351
LF357'
22pF
22pF
10 pF
Co)
o
........
C
~
n
o
QC)
Co)
......
~
........
'2.4 kfl RESISTOR ADDED FROM-INPUT TO
GROUND TO INSURE STABILITY
C
~
FIGURE 8
oQC)
Co)
I\)
0
VREF
r
DAC083D
VOUT=VREF
I
AI>
(DIGITAL CODE -128)
128
J
TLlH/560B-l0
1 LSB='VREFI
128
Input Code
MSB .......... LSB
'THESE RESISTORS ARE AVAILABLE FROM
BECKMAN INSTRUMENTS, INC. AS THEIR
PART NO. 694-3-R1DK-D
1 1 1 1
1 1 0 0
1 0 0 0
0 1 1 1
1
0
0
1
1 1 1
0 0 0
0 0 0
1 1 1
IDEALVOUT
+VREF
-VREF
VREF-1 LSB
VREF/2
-IVREFI + 1 LSB
-IVREFI/2
0
0
-1 LSB
+1 LSB
0 0 1 1 1 1 1 1 JVREFI_ 1 LSB
2
0 0 0 0 0 0 0 0
-IVREFI
IVREFI + 1 LSB
2
+IVREFI
FIGURE 9
2_6 Full-Scale Adjustment
In the case where the matching of RIb to the R value of the
R-2R ladder (typically ±0.2%) is insufficient for full-scale
accuracy in a particular application, the VREF voltage can be
adjusted or an external resistor and potentiometer can be
added as shown in Figure 10 to provide a full-scale adjustment.
manner from the standard current switching configuration.
The reference voltage is connected to one of the current
output terminals (IOUTl for true binary digital control, IOUT2
is for complementary binary) and the output voltage is taken
from the normal VREF pin. The converter output is now a
voltage in the range from OV to 255/256 VREF as a function
of the applied digital code as shown in Figure ".
The temperature coefficients of the resistors used for this
adjustment are an important concern. To prevent degradation of the gain error temperature coefficient by the external
resistors, their temperature coefficients ideally would have
to match that of the internal DAC resistors, which is a highly
impractical constraint. For the values shown in Figure 10, if
the resistor and the potentiometer each had a temperature
coefficient of ± 100 ppml'C maximum, the overall gain error
temperature coefficent would be degraded a maximum of
0.0025%I'C for an adjustment pot setting of less than 3%
of RIb.
Your
\
2_7 Using the DAC0830 in a Voltage Switching
Vee
TLlH/560B-ll
Configuration
FIGURE 10. Adding Full-Scale Adjustment
The R-2R ladder can also be operated as a voltage switching network. In this mode the ladder is used in an inverted
4-49
N
r-------------------------------------------------------------------------------~
C")
CIO
<:)
o
DAC0830 Series Application Hints (Continued)
(Y'E')
C!i
.......
0-:8......_A/lt'.-......_"",..,..__ • • • • • _ _NoII.._ _"",2R,.,._
....
DY " \loUT"
C")
~~: YREF
CIO
2R
<:)
~
C
2R
2R
2R
(~1~8) TL-t-l-+I--...+I-III-°-O_.·-1I-+-t--Lf(~-~:)......:.(I=OUT1.:...;.;..,)
.......
<:)
C")
11
- '-----.......-_~-----4-~--+-.-~~~_2_'55YOC
""1..
CIO
<:)
o
«
c
-
-
-
(Ioun) 12
REFERENCE
TLIH/5608-12
FIGURE 11. Voltage Mode Switching
gain error on the voltage difference between Vee and the
voltage applied to the normal current output terminals. This
is a result of the voltage drive requirements of the ladder
switches. To ensure that all 8 switches turn on sufficiently
(so as not to add significant resistance to any leg of the
ladder and thereby introduce additional linearity and gain
errors) it is recommended that the applied reference voltage
be kept less than +5Voe and Vee be at least 9V more
positive than VREF. These restrictions ensure less than
0.1 % linearity and gain error change. Figures 16, 17 and 18
characterize the effects of bringing VREF and Vee closer
together as well as typical temperature performance of this
voltage switching configuration.
This configuration offers several useful application advan·
tages. Since the output is a voltage, an external op amp is
not necessarily required but the output impedance of the
DAC is fairly high (equal to the specified reference input
resistance of 10 kn to 20 kn) so an op amp may be used
for buffering purposes. Some of the advantages of this
mode are illustrated in Figures 12, 13, 14 and 15.
There are two important things to keep in mind when using
this DAC in the voltage switching mode. The applied refer·
ence voltage must be positive since there are internal para·
sitic diodes from ground to the IOUTl and IOUT2 terminals
which would turn on if the applied reference went negative.
There is also a dependence of conversion linearity and
. . . _--0()
+15V Vee
....._--o+15V
r......;::..:;-~~~~~-_~_+~2.5V REFERENCE
LM336
8 YREF
8 V'E'
LM336
10
R10k
+15Y
>.:...-.--o\loU1
=+2.5Yoc6 +~X~)
-2.5VOC" \loUT"
2.5Yoe(~~)
2k
-15
30k
TLlH/560B-13
• Voltage switching mode eliminates output signal inversion and therefore a
need for a negative power supply.
• VOUT~2.5V (..E...-1)
128
• Zero code output voltage is limited by the low level output saturation voltage of the op amp. The 2 kO pull-down resistor helps to reduce this voltage.
• Slewing and settling time for a full scale output change is ;::::: 1.8 jJ.s
• Vos of the op amp has no effect on DAC linearity.
FIGURE 13. Obtaining a Bipolar Output from a Fixed
Reference with a Single Op Amp
FIGURE 12. Single Supply DAC
4·50
DAC0830 Series Application Hints (Continued)
+10V(~::)
-10V .. YoUT ..
-15
o .. Yue ..
t
~: (2.5Y)
AY=+8
FIGURE 14. Bipolar Output with Increased Output Voltage Swing
+15Y
1:~
DAC0830
loun
8 YREF
GNO
10 3
12
120k
1---t
+15Y~=YMA"1.YoL::=UT
Ok
=VMIN
CODE (D)
o
o
255
TLlH/560B-14
Only a single + 15V supply required
• Non-interactive full-scale and zero code output adjustments
o
VMAX and VMIN must be :s; +5VDC and
~OV.
1
o
Incremental Output 5tep= 256 (VMAX- VMIN).
OVOUT=.E...(VMAX-VMIN)+ 255VM1N
256
256
FIGURE 15. Single Supply DAC with Level Shift and SpanAdjustable Output
Gain and Linearity Error
Variation vs. Supply Voltage
0.4
l
I
35
0.2
VREF;"5Y
\
o
I~ -0.2
0.4
YOLTAGE MODE OPE':J~If.. ERhoR
YREF= 2.5Y
- ,HEF
T
0.2 4LINEARITY
ERROR
Yt:e=~
35
I
YREF=5Y
iiERjOR,
TA=25"C
VOLTAGE MOD
,-OPERATION
I
ffi
~
2 5Y
.
l
'"
:Ii!
r- ~
t--
~ -0.2
o
2
4
6
8
10 12 14
Vee. SUPPLY VOLTAGE (Voe)
16
I
I
I
J
..,... V
~ee = 12f\ I"'\.
I'
0.100
0.075
Ve~=15Y
I
Vee = 15V
0.050
0.025
...35
~
-0.050
-0.075
TA=25"C
°
l
'"
'"ffi
~ -0.025
AGAIN ERROR
-0.4
-0.4
Gain and Linearity Error
Variation vs. Temperature
Gain and Linearity Error
Variation VS. Reference Voltage
~:E MODE OPERATION
I
ALiNEARITY ERROR ..::::::
Vee=15Y. VREf=5V
Yt:e= 12V. VREF=2.5V- i;;>-<
-
.;::;
I~ i-"'""
""
y
"..
-I I"
""'" AGAIN
ERROR
Vee = 15Y. VREF = 5V DR
Vee=12Y. VREF=2.5V
1 1
10
VREF. REFERENCE VOLTAGE (Voe)
-0.100
-55 -35 -15 5 25 45 65 85 105 125
TA. AMBIENT TEMPERATURE (OC)
TL/H/560B-15
FIGURE 16
FIGURE 17
Note: For these curves. VREF is the voltage ap,
plied to pin 11 (Ioun) with pin 12 (loUT2I
grounded.
4-51
FIGURE 18
CN
CO)
r---------------------------------------------------------------------------------,
co
o
g
.....
....
CO)
CO
o
g
~
CO
o
g
DAC0830 Series Application Hints (Continued)
2.8 Miscellaneous Application Hints
These converters are CMOS products and reasonable care
should be exercised in handling them to prevent catastrophic failures due to static discharge.
Overall noise reduction and reference stability is of particular concern when using the higher accuracy versions, the
DAC0830 and DAC0831, or their advantages are wasted.
Conversion accuracy is only as good as the applied reference voltage so providing a stable source over time and
temperature changes is an important factor to consider.
A "good" ground is most desirable. A single point ground
distribution technique for analog signals and supply returns
keeps other devices in a system from affecting the output of
the DACs.
During power-up supply voltage sequencing, the -15V (or
-12V) supply of the op amp may appear first. This will
cause the output of the op amp to bias near the negative
supply potential. No harm is done to the DAC, however, as
the on-chip 15 k!l feedback resistor sufficiently limits the
current flow from loun when this lead is internally clamped
to one diode drop below ground.
Careful circuit construction with minimization of lead lengths
around the analog circuitry, is a primary concern. Good high
frequency supply decoupling will aid in preventing inadvertant noise from appearing on the analog output.
3.0 GENERAL APPLICATION IDEAS
The connections for the control pins of the digital input registers are purposely omitted. Any of the control formats discussed in Section 1 of the accompanying text will work with
any of the circuits shown. The method used depends on the
overall system provisions and requirements.
The digital input code is referred to as D and represents the
decimal equivalent value of the 8-bit binary input, for example:
Binary Input
Pin 13
MSB
1
1
0
0
0
1
0
0
0
0
Pin 7
LSB
1
0
0
0
0
1
0
1
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
1
0
D
Decimal Equivalent
1
0
0
0
0
255
128
16
2
0
Applications
DAC Controlled Amplifier (Volume Control)
Capacitance Multiplier
V,N
20
+15V
IOUT2
Vee
OAC0830
loun
VREF
20
+15V
8
10
&2
-=-
>----_-0 VOUT
&,
~&EOUlY
I
o VOUT= -V'N (256)
TL/H/560B-16
oCeOUlV=Cl
o
o When'D=O, the amplifier will go open loop and the output will salurate.
(1+ 2:)
• Maximum voltage across the equivalent capacitance is
o Feedback impedance from the - input to lhe output varies from 15 kll to
00 as the input code changes from full-scale to zero.
limited to Vo MAX (op amp)
1+ 256
o
• C2 is used to improve settling time of op amp.
4-52
g
Applications (Continued)
oo
CO
Variable fa. Variable Qo. Constant BW Bandpass Filter
Ct.)
o
.......
R.
g
oo
0
.,.
CO
....
g
Ct.)
.......
10Ul1
DACD83D
R,
oo
CO
'::-
Ct.)
N
15k
'::-
TL/H/560B-17
o
fo
~
{Kf5
"256.
00
~ {Kf5 (2A a
"256
21TA,C'
where C,
~
C2
~
C; K
~
+ All. 3dbBW
Aa(K + 1)'
A6
As
and A,
~
~
Aa(K + 1)
21TA,C(2Aa + R')
A of DAC
~
15k
o Ho ~ 1 for A'N ~ A4 ~ A,
• Aange of fo and 0 is '" 16 to 1 for circuit shown. The
range can be extended to 255 to 1 by replacing A, with a
second DAC0830 driven by the same digital input word.
o Maximum fo
x 0 product should be ,;:200 kHz.
DAC Controlled Function Generator
+15V
I
+15V
75k
SYMMETRY;;
TRIM
-15V
WAVESHAPE/
TRIM
2k
+15V 2Qr---....;:O""-..................;.;..........;;.a
OAC0830
., r- +15
L.J
-15
SQUARE WAVE
OUTPUT
TUH/560B-1B
• DAC controls the frequency of sine, square, and triangle outputs.
o
o f ~ 256(20k)C for VOMAX ~ VOMIN of square wave output and A, ~ 3 A2.
o 255 to 1 linear frequency range; osciliator stops with 0
~
0
• Trim symmetry and wave·shape for minimum sine wave distortion.
4·53
Applications (Continued)
Two Terminal Floating 4 to 20 mA Current Loop Controller
INPUT
IN4DDI
LM334
6D1IQ
TLlH/5608-'9
lOUT = VREF
[.!..A, + _0_]
[1 + &]
256AIb
A3
• OAC0830 linearly controls the current flow from the input terminal to the
output terminal to be 4 rnA (for 0=0) to 19.94 mA (lor 0=255).
• CircuH operates with a !erminal voltage differential of 16V to 55V.
• P2 adjusts the magnitude of the output current and P, adjusts the zero
to full scale range of output current.
• Oignal inputs can be supplied from a processor using opto isolators on
each input or the OAC latches can flow-through (connect control lines to
pins 3 and 10 of the OAC) and the Input data can be set by SPST toggle
switches to ground (pins 3 and 10).
DAC Controlled Exponential Time Response
r
VINITIAL
VflNAL
....J
\\)UT
A
VINITIAL ~
VFINAL
\
... YODANDC
TLlH/56OS-20
• output responds exponentially to input chenges and automatically stops
when VOUT=VIN
• Output time constant is directiy proporticnal to the OAC input code and
capacHorC
• Input voltage must be positive (See section 2.7)
4-54
Ordering Information
Temperature Range
Non
Unearity
DAC0830LCN
0.1% FSR
DAC0831LCN
0.2% FSR
DAC0832LCN
Package Outline
-40"Cto + 85'C
- 55'C to + 125'C
DAC0830LCM
DAC0830LCV
DAC0830LCJ
DAC0830LJ
DAC0832LCM
DAC0832LCV
DAC0832LCJ
DAC0832LJ
O"Cto +70'
0.05% FSR
N20A-Molded DIP
M20B Small Outline
4·55
V20A Chip Carrier
J20A-Ceramic DIP
co
o
o
....
~
c
r----------------------------------------------------------------------------,
~National
~ Semiconductor
..........o
o.... DAC1 OOO/DAC 1001/DAC1 002/DAC1 006/DAC1 0071
o
i§ DAC1008p.P Compatible,
...... Double-Buffered 0 to A Converters
co
o
o
.....
General Description
o The DAC10001112 and DAC10061718
i§
......
C'I
o
....o
o
i§
......
,..
o
o
....
o
i§
......
o
o
o
....
o
i§
Features
• Uses easy to adjust END POINT specs, NOT BEST
STRAIGHT LINE FIT
• Low power consumption
• Direct interface to all popular microprocessors.
• Integrated thin film on CMOS structure
• Double-buffered, single-buffered or flow through digital
data inputs.
• Loads two 8-bit bytes or a single 10-bit word.
• Logic inputs which meet TTL voltage level specs (1.4V
logiC threshold).
• Works with ± 10V reference-full 4-quadrant multiplication .
• Operates STAND ALONE (without !,-P) if desired.
• Available in 0.3" standard 20-pin and 0.6" 24-pin package.
• Differential non-linearity selection available as special
order.
are advanced
CMOS/Si-Cr 10-, 9- and 8-bit accurate multiplying DACs
which are designed to interface directly with the 8080, 8048,
8085, l-80 and other popular microprocessors. These
DACs appear as a memory location or an 110 port to the !,-P
and no interfacing logic is needed.
These devices, combined with an external amplifier and
voltage reference, can be used as standard 01 A converters;
and they are very attractive for multiplying applications
(such as digitally controlled gain blocks) since their linearity
error is essentially independent of the voltage reference.
They become equally attractive in audio Signal processing
equipment as audio gain controls or as programmable attenuators which marry high quality audio signal processing
to digitally based systems under microprocessor control .
All of these DACs are double buffered. They can load all 10
bits or two 8-bit bytes and the data format can be either right
justified or left justified. The analog section of these DACs is
essentially the same as that of the DAC1020.
Key Specifications
The DAC1000 series are the 10-bit members of a family of
microprocessor-compatible DAC's (MICRO-DACTM's). For
applications requiring other resolutions, the DAC0830 series
(8 bits) and the DAC1208 and DAC1230 (12 bits) are available alternatives.
Part #
Accuracy
(bits)
DAC1000
10
DAC1001
9
DAC1002
8
DAC1006
10
DAC1007
9
DAC1008
8
Pin
Description
24
Has all
logiC
features
20
For leftjustified
data
• Output Current Settling Time
• Resolution
• Linearity
• Gain Tempco
• Low Power DiSSipation
(including ladder)
• Single Power Supply
500 ns
10 bits
10, 9, and 8 bits
(guaranteed over temp.)
-0.0003% of FSI'C
20mW
5 to 15 VDC
Typical Application
r=
DAC1006/100711008
CONT~L BUS
WR
Bytll1/Byte 2
rl--:;;';:::"---'1
XFER
~
~
,===DB:;,J7"'"'DATA BUS="
S
b-
DBD
LSB
lOBO BUS
•
1
3
2
CI
+VCfl':F:
1
20 14
MICRO·DAC'·
20 PIN 10
13
.".
~L
_
12 .............
11
~
lOUT 1
/!o
IOU12
1·
.".
0"
Your
+
NOTE: FOR DETAILS OF BUS
CONNECTION SEe SECTION 6.0
TUH/56BB-l
4-56
Absolute Maximum Ratings
(Notes 1 & 2)
ESD Susceptibility (Note 11)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vee)
Voltage at Any Digital Input
17Voe
VcctoGND
±25V
-65·C to + 150·C
Voltage at VREF Input
Storage Temperature Range
Package Dissipation at TA = 25·C (Note 3)
DC Voltage Applied to IOUT1 or IOUT2
(Note 4)
aoov
Lead Temp. (Soldering, 10 seconds)
Dual-In-Line Package (plastic)
Dual-In-Line Package (ceramic)
Operating Ratings
-100 mV to Vee
VeetoGND
Conditions
See
Note
Min.
Typ.
Resolution
Linearity Error
Differential
Nonlinearity
Monotonicity
Vcc= 5Voc±5%
Min.
Typ.
Endpoint adjust only
TMIN 2.0V
6
VIL =OV, VIH=5V
Write and XFER
Pulse Width
tw
VIL =OV, VIH=5V,
TA=25°C
8
TMIN,;:;TA,;:;TMAX
9
VIL =OV, VIH=5V,
TA=25°C
tOH
VIL =OV, VIH=5V
TA=25°C
tcs
VIL =OV, VIL =5V,
TA=25°C
tCH
VIL =OV, VIH=5V,
TA=25°C
nA
200
200
nA
0.8
0.8,0.8
0.6
0.7,0.8
Voc
Voc
Voc
-150
+10
p.Aoc
p.Aoc
2.0
-40
-150
-40
1.0
+10
1.0
500
ns
60
100
320
500
200
250
ns
ns
9
150
320
80
120
320
500
170
250
ns
ns
9
200
250
100
120
320
500
220
320
ns
ns
9
150
320
60
100
320
500
180
260
ns
ns
9
10
10
0
0
10
10
0
0
ns
ns
TMIN,;:;TA,;:;TMAX
Control Hold Time
Units
Max.
150
320
TMIN,;:;TA,;:;TMAX
Control Set Up
Time
Typ.
200
500
TMIN,;:;TA,;:;TMAX
Data Hold Time
Min.
200
2.0
ts
tos
Max.
6
Current Settling
Time
Data Set Up Time
Typ.
Vcc= 5Voc±5%
TMIN,;:;TA,;:;TMAX
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond
~s
specified operating conditions.
Note 2: All voltages are measured with respect to GNO, unless otherwise specified.
Note 3: This SOO mW specification applies for all packages. The low intrinsic power dissipation of this part (and the fact that there is no way to Significantly modify
the power dissipation) removes concern for heat sinking.
Note 4: For current ~ching applications, both loun and IOUT2 must go to ground or the "Virtual Ground" of an operational amplifier. The linearity error is
degraded by approximateIyVOS+VREF. For example, if VREF=10V then a 1 mVoffset, VOS, on loun or IOUT2 will Introduce an addHional 0.01% linear~ error.
Note 5: Guaranteed at VREF= ±10 VDe and VREF= ±1 Voc.
Note 6: TMIN=O"C and TMAX=70'C for "LCN" suffix parts.
TMIN= -40"C and TMAX=8S'C for "LCJ" suffix parts.
TMIN=SS'C and TMAX=125"C for "U" suffix parts.
Note 7: The unit "FSR" stands for "Full Scale Range." "Linearity Error" and "Power Supply Rejection" specs are based on this unit to eliminate dependence on a
particular VREF value and to indicate the true partorrnance of the part. The "Linearity Error" specification of the OAC1000 is "O.OS% of FSR (MAX)." This
guarantees that after performing a zero and full scale adjustment (See Sections 2.S and 2.6), the plot of the 1024 analog voltage outputs will each be within
0.05% XVREF of a straight line which passes through zero and full scale.
Note 8: This specification implies that all parts are guaranteed to operate with a write pulse or transfer pulse width (tv;) of 320 ns. A typical part will operate with tv;
of only 100 ns. The entire write pulse must occur within the valid data interval for the specified tw, los, toH, and Is to apply.
Note 9: Guaranteed by design but not tested.
Note 10! A 200 nA leakage current with Rfb=20K and VREF=10V corresponds to a zero error of (200Xl0- 9 X20Xl03)Xl00+l0 which is 0.04% of FS.
Note 11: Human body model, 100 pF discharged through a I.S kn resistor.
4-58
g
...oo
Switching Waveforms
VIH
CS, BYTEIIBYTE2
rlcs-llcH
5~
o
~
I;::
F
g
...
o
::~~r-t.v---1
~%
VIL
o
o
r--
...o~
~IDS==4IDHI-
I
VIH~
DATA BITS
...
......
~%
h
VIL
o
~
IS-
"~----FS
IDUT1,IDUT2
...~
' " SETTLED TO
±'h LSB
TL/H/5688-2
o
o
~
Typical Performance Characteristics
Errors vs. Supply Voltage
0.000
~
-.025
"'c
"'"'
-.050
'"
L:NEA~ITY E~ftOft
I I
0.075
I I
~ 0.050
g"' 0.025 I- - '" lIN~RIJ ER~OR r-'j ''j'
III
"
0.000
'
"
""
r 1"""
~ -0.025
V
-.075
I
~
-.100
'" GAIN ERROR
~
Control Setup Time, tcs
.
.....
ui
500
i-~!NL~OVI
I
~
~
400
5
~
~
8
300
200
100
o
VCC=15V
100
r--
500
)NL~OVI
400
~
300
-
~
8
100
o
-55 -35 -15 5 25 45 65 85 105 125
vJc=~v
I
'"
:
I
VCC=10V VCC=15V-
-P-
1\
i-""
_I-"
2.0
'"
::l 1.2
~
~
:!
~
0.8
0.4
0.0
I I
5
.....1-1,..l.
~~
300
Iii-'
200
)NL~OVI
I
jH 3V TOjV
i
1
VCC=15V
.J
LvJc=ll0V
VCC=5V
-
~ I-"K"
f.--
l-
-55 -35 -15
5 25 45 65 85 105 125
TA. AMBIENT TEMPERATURE ('C)
Digital Input Threshold
vs. Temperature
2.0
TAI=2~~ I--
T+25~
- -
VC~ = Jv VCC = 10V
VCC=15V-
2.4
II
1
g;
o
TA. AMBIENT TEMPERATURE ('C)
1.6 TA=L55 c
400
3 100
i--
Digital Threshold
vs, Supply Voltage
~
500
.
~
-55 -35-15 5 25 45 65 85 105125
AM81ENT TEMPERATURE ('C)
......
......
-V\NHt ITO jV
Data Hold Time, tOH
;::
200
o
I
-55-35-15525456585105125
AMBIENT TEMPERATURE ('CI
VINHtlTOr
~
lil
!i
~ I-"
~
...o
o
o
;::
..!. I. VCC=10V
l)...- I-"
VCC=5V
\
2.4
200
Data Setup Time, tos
V\NHtyO jV
;::
~
I~
-O.I!55_35_15 5 25 45 65 85 105125
AMBIENT TEMPERATURE ('C)
10
15
SUPPLY VOLTAGE Vcc (Voc)
:=
~
£ 300
I I
I I
-0.015
vlNLlov I
~ 400
'" GAIN ERROR
-0.050
-.125
!:
500
f-
"
~
g
Write Width, tw
I
V
~
z
Errors vs. Temperature
0.100
~
I--
~
I-- I-""
i
I-- I--
1.2
~
:! 0.8
~
10
1.8
......
--r--. ............
...... r--.
0.4
0.0
-55-35-15 5 25 45 65 85 105125
TEMPERATURE ('C)
15
SUPPLY VOLTAGE Vcc (V)
4·59
TLiH/5688-3
c
»
o
...o
o
=
co ,---------------------------------------------------------------------------------,
o
o
Block and Connection Diagrams
..-
g
DAC1000/100111002 (24-Pin Parts)
j:::
o
o
..-
DAC1000/100111002
(24-Pin Parts)
Dual-In-Line Package
15
1--+, 3'" ± VSEF
g
.....
1--+-t~IOUT2
LJ/RJ
24
23
CD
WRI
Byte IIByte 2
21
..-
WR2
CS
1-p-t-'..4~ lOUT I
g
g
,.,
2nd
BYTE BYTE
STROBE STROBE
g
..-
XFER
STROBE
VCC
CONTROL LOGIC
~
c
.....
..cs
g
g
015
016
DID (LSB)
6
Wii2
Wlii
iFEii BYTE II
WI
BYTE 2
iiJ
RFB
11
lOUT,
GND
12
IOUT2
10
TLlH/5688-4
HC
017
016
015
014
013
5
•
'8
01,
(LIB) DID
'5
DAC1006/1007/1008
(20-Pin Parts)
Dual-In-Llne Package
± VREF
I---r:'.:..'~ IOUT2
1--_r:'.=.2~ lOUT,
'0 BIT
'9
17
16
012
1--_+':.::3..
9
B
7
6
VREF
TOP VIEW
DAC1006/1007/1008 (20-Pin Parts)
(MSB) 019
OIB
OAC 1000,
1001,1002
017
OIB
(MSB) Dig
23
o
o
..-
§..-
GNO
MULTIPLYING
O/A CONVERTER
~
Wli
'9
'B
17
Byt. IIIryitf
00
015
5
015
017
6
DACloo6
DAC1D07
DAClODB
018
(MSB) 019
, II
2nd
BYTE
BYTE
STROBE STROBE
014
013
012
01,
im
C\i
VCC
NC
NC
XFER STROBE
GND
013
'6
012
01,
'5
14
RFB
13
'0
VCC
014
DID (LSB)
12
VREF
lOUT,
11
IDUT2
CONTROL LOGIC
TLlH/5688-28
Top View
See Ordering Information
cs
Wii
XFiii
Bm 1/
8m2
USE DAC1006/1007/'008
FOR LEFT JUSTIFIED DATA
·TLlH/5668-5
4-60
g
o
....
o
DAC1000/1001/1002-Simple Hookup for a "Quick Look"
o
~
+15VOC
+15VOC
~....
o
>.l........OOVOUT
••
•
lK
"::"
LSB
....o
.....
....o~
VOUT 0 TO VREF (~)
17
o
'A TOTAL OF 10
INPUT SWITCHES
& 1 K RESISTORS
-15VOC
TL/H/5688-6
Notes:
1. ForVREF~ -10.240 Voc the output voltage steps are approximately 10 mV each.
en
.....
3. Single point ground is strongly recommended.
~....
DAC1006/1007l100a-Simple Hookup for a "Quick Look"
o
o
.....
.....
g
o
....
o
+~'\o-~------------,
+15VDC
tK
~....
o
o
2. Operation is set up for flow through-no latching of digital input data.
SWI
N
.....
+15VDC
i
VOS
25K
lK
.>--_-G+ VOUT
o
_
• 15L--,r---....,.--'
LSB
'A TOTAL OF 10
INPUT SWITCHES
& 1K RESISTORS
oVOC .. VOUT .. + VREF G~m
4
-15VOC
TUH/5688-7
Notes:
1. For VREF~ -to.240 Vae the output voltage steps are approximately 10 mV each.
2. SWt is a normally closed switCh. While SWI is closed, the DAC register is latched and new data
can be loaded into the input latch via the 10 SW2 switches.
When SWI is momentarily opened the new data is transferred from the input latch to the DAC register and is latched when SWt again closes.
4-61
:g
....o
g
j::::
o
o
....
g
......
CD
o
....
o
~
c
......
N
o
o
....
g
......
....
....
o
o
g
C;
o
o
....
g
1.0 DEFINITION OF PACKAGE PINOUTS
1.1 Control Signals (All control signals are level actuated.)
RFB: Feedback Resistor - This is provided on the IC chip
for use as the shunt feedback resistor when an external op
amp is used to provide an output voltage for the DAC. This
on-chip resistor should always be used (not an external resistor) because it matches the resistors used in the on-chip
R-2R ladder and tracks these resistors over temperature.
VREF: Reference Voltage Input - This is the connection for
the external precision voltage source which drives the R-2R
ladder. VREF can range from -10 to + 10 volts. This is also
the analog voltage input for a 4-quadrant multiplying DAC
application.
CS: Chip Select - active low, it will enable WR (DAC10031008) or WR1 (DAC1000-1002).
WR or WR1: Write - The active low WR (or WR1 DAC1 000-1 002) is used to load the digital data bits (DI) into
the input latch. The data in the input latch is latched when
WR (or WR1) is high. The 10-bit input latch is split into two
latches; one holds 8 bits and the other holds 2 bits. The
Byte1/Byte2 control pin is used to select both input latches
when Byte1/Byte2 = 1 or to overwrite the 2-bit input latch
when in the low state.
Vee: Digital Supply Voltage - This is the power supply pin
for the part. Vee can be from + 5 to + 15 VDe. Operation is
optimum for + 15V. The input threshold voltages are nearly
independent of Vee. (See Typical Performance Characteristics and Description in Section 3.0, T2l compatible logic
inputs.)
GND: Ground - the ground pin for the part.
WRz: Extra Write (DAC1000-1002) - The active low WR2
is used to load the data from the input latch to the DAC
register while XFER is low. The data in the DAC register is
latched when WR2 is high.
BytellByte2: Byte Sequence Control - When this control
is high, all ten locations of the input latch are enabled. When
low, only two locations of the input latch are enabled and
these two locations are overwritten on the second byte
write. On the DAC1006, 1007, and 1008, the Byte1/Byte2
must be low to transfer the 10-bit data in the input latch to
the DAC register.
1.2 Other Pin Functions
DJ; (i=O to 9): Digital Inputs- Dlo is the least significant bit
(lSB) and Dig is the most significant bit (MSB).
1.3 Definition of Terms
Resolution: Resolution is directly related to the number of
switches or bits within the DAC. For example, the DAC1000
has 2 10 or 1024 steps and therefore has 10-bit resolution.
Linearity Error: Linearity error is the maximum deviation
from a straight line passing through the endpoints of the
DAC transfer characteristic. It is measured after adjusting
for zero and full-scale. Linearity error is a parameter intrinsic
to the device and cannot be externally adjusted.
National's linearity test (a) and the "best straight line" test
(b) used by other suppliers are illustrated below. The "best
straight line" requires a special zero and FS adjustment for
each part, which is almost impossible for user to determine.
The "end point test" uses a standard zero and FS adjustment procedure and is a much more stringent test for DAC
linearity.
IOUT1: DAC Current Output 1 - IOUT1 is a maximum for a
digital input code of all 1s and is zero for a digital input code
of all Os.
Power Supply Sensitivity: Power supply sensitivity is a
measure of the effect of power supply changes on the DAC
full-scale output (which is the worst case).
XFER: Transfer Control Signal, active low - This Signal, in
combination with others, is used to transfer the 10-bit data
which is available in the input latch to the DAC register see timing diagrams.
lJ/RJ: left Justify/Right Justify (DAC1000-1002) - When
LJ/RJ is high the part is set up for left justified (fractional)
data format. (DAC1006-1008 have this done internally.)
When W/RJ is low, the part is set up for right justified (integer) data.
IOUT2: DAC Current Output 2 IOUT1' or
I
I
OUT1 + OUT2
IOUT2 is a constant minus
1023 VREF
1024 R
where R "" 15 kO.
a. End Point Test After Zero and FS Adj.
b. Best Straight Line
DIGITAL INPUT
DIGITAL INPUT
TL/H/5688-8
4-62
Settling Time: Settling time is the time required from a code
transition until the DAC output reaches within ± % LSB of
the final output value. Full-scale settling time requires a zero
to full-scale or full-scale to zero output change.
Full-Scale Error: Full scale error is a measure of the output
error between an ideal DAC and the actual device output.
Ideally, for the DAC1000 series, full-scale is VREF-1 LSB.
For VREF= -10V and unipolar operation, VFULLSCALE = 10.0000V -9.BmV=9.9902V. Full-scale error is
adjustable to zero.
3.0 TTL COMPATIBLE LOGIC INPUTS
To guarantee TTL voltage compatibility of the logic inputs, a
novel bipolar (NPN) regulator circuit is used. This makes the
input logic thresholds equal to the forward drop of two diodes (and also matches the temperature variation) as occurs naturally in TTL. The basic circuit is shown in Figure 1.
A curve of digital input threshold as a function of power
supply voltage is shown in the Typical Performance Characteristics section.
4.0 APPLICATION HINTS
Monotonicity: If the output of a DAC increases for increasing digital input code, then the DAC is monotonic. A 10-bit
DAC with 10-bit monotonicity will produce an increasing analog output when all 10 digital inputs are exercised. A 10-bit
DAC with 9-bit monotonicity will be monotonic when only
the most significant 9 bits are exercised. Similarly, B-bit
monotonicity is guaranteed when only the most significant B
bits are exercised.
The DC stability of the VREF source is the most important
factor to maintain accuracy of the DAC over time and temperature changes. A good single point ground for the analog
Signals is next in importance.
These MICRO-DAC converters are CMOS products and
reasonable care should be exercised in handling them prior
to final mounting on a PC board. The digital inputs are protected, but permanent damage may occur if the part is subjected to high electrostatic fields. Store unused parts in conductive foam or anti-static rails.
2_0 DOUBLE BUFFERING
These DACs are double-buffered, microprocessor compatible versions of the DAC1020 10-bit multiplying DAC. The
addition of the buffers for the digital input data not only allows for storage of this data, but also provides a way to
assemble the 10-bit input data word from two write cycles
when using an B-bit data bus. Thus, the next data update for
the DAC output can be made with the complete new set of
1O-bit data. Further, the double buffering allows many DACs
in a system to store current data and also the next data. The
updating of the new data for each DAC is also not time
critical. When all DACs are updated, a common strobe signal can then be used to cause all DACs to switch to their
new analog output levels.
4.1 Power Supply Sequencing & Decoupling
Some IC amplifiers draw excessive current from the Analog
inputs to V- when the supplies are first turned on. To prevent damage to the DAC - an external Schottky diode connected from IOUTl or IOUT2 to ground may be required to
prevent destructive currents in IOUTl or IOUT2. If an LM741
or LF356 is used - these diodes are not required.
The standard power supply decoupling capacitors which are
used for the op amp are adequate for the DAC.
~
....
o
o
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.......
~....
o
....
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o
....
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.......
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.......
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oQ)
.......
~
....
o
o
.....
......
~....
o
o
co
+Vcc
(3++YTHN)
/'
VSIAS
(TO OTHER INPUTS)
o
S·
.VTHRESHOLD
FIGURE 1. BasiC Logic Threshold Loop
4-63
II
=20
TLiH/56B8-9
co
o
r-----------------------------------------------------------------------------------------,
o
.,...
4.2 Op Amp Bias Current & Input Leads
~...........
The op amp bias current (IB) CAN CAUSE DC ERRORS. 81FETTM op amps have very low bias current, and therefore
the error introduced is negligible. BI-FET op amps are
strongly recommended for these DACs.
o
o
.,...
o
~
......
able ladder current to the IOUT1 output pin. These MOS
switches operate in the current mode with a small voltage
drop across them and can therefore switch currents of either polarity. This is the basis for the 4-quadrant multiplying
feature of this DAC.
The distance from the IOUTl pin of the DAC to the inverting
input of the op amp should be kept as short as possible to
prevent inadvertent noise pickup.
CD
5.0 ANALOG APPLICATIONS
o
The analog section of these DACs uses an R-2R ladder
which can be operated both in the current switching mode
and in the voltage switching mode.
o
o
.,...
~
~
o
o
.,...
~.......,...
o
o.,...
~
Q
......
o
o
o
.,...
o
~
5.1.1 Providing a Unipolar Output Voltage with the
DAC !11 the Current Switching Mode
A voltage output is provided by making use of an external
op amp as a current-to-voltage converter. The idea is to use
the internal feedback resistor. RFB, from the output of the
op amp to the inverting (-) input. Now, when current is
entered at this inverting input. the feedback action of the op
amp keeps that input at ground potential. This causes the
applied input current to be diverted to the feedback resistor.
The output voltage of the op amp is forced to a voltage
given by:
The major product changes (compared with the DAC1020)
have been made in the digital functioning of the DAC. The
analog functioning is reviewed here for completeness. For
additional analog applications, such as multipliers. aUenuators, digitally controlled amplifiers and low frequency sine
wave oscillators. refer to the DAC1020 data sheet. Some
basic circuit ideas are presented in this section in addition to
complete applications circuits.
VOUT = -(IOUTI XRFB)
Notice that the sign of the output voltage depends on the
direction of current flow through the feedback resistor.
In current switching mode applications. both current output
pins (IOUTl and IOUT2) should be operated at 0 Voc. This is
accomplished as shown in Figure 3. The capacitor. Ce. is
used to compensate for the output capaCitance of the DAC
and the input capacitance of the op amp. The required feedback resistor. RFB. is available on the chip (one end is internally tied to IOUT1) and must be used since an external
resistor will not provide the needed matching and temperature tracking. This circuit can therefore be simplified as
5.1 Operation in Current Switching Mode
The analog circuitry. Figure 2. consists of a silicon-chromium (Si-Cr) thin film R-2R ladder which is deposited on the
surface oxide of the monolithic chip. As a result. there is no
parasitic diode connected to the VREF pin as would exist if
diffused resistors were used. The reference voltage input
(VREF) can therefore range from -10V to +10V.
The digital input code to the DAC simply controls the position of the SPOT current switches, SWO to SW9. A logical 1
digital input causes the current switch to steer the avail-
DIGITAL INPUT CODE
(MSBI
019
0
018
1
R
±VREF
017.· • • •
0
R
011
010 (LSBI
1
TERMINATION
R
-----
-=-
2R
2R
2R
2R
RIB
R
' - - I - - - t -.....---t---f---r.--o 10UTl
' - - - - - -.....- - - -.....- -....-----oIOUT2
R"'15kQ
FIGURE 2. Current Mode Switching
VCC
(INTERNALI RFB
lOUT 1
( +15VDCI
+VREF
>-........--0 VOUT = -(IOUTI x RIBI
MICRO-DAC
-=-
OP AMP Cc pF
RI
ts }JoS TLlH/568B-l0
FIGURE 3. Converting lOUT to VOUT LF356
22
LF351
24
00
4
LF357
10
2.4k
1.5
4-64
00
3
shown in Figure 4, where the sign of the reference voltage
has been changed to provide a positive output voltage. Note
that the output current, IOUT1' now flows through the RFB
pin.
where VREF can be positive or negative and 0 is the signed
decimal equivalent of the 2's complement processor data.
(-512,;;D,;;+511orl000000000:5:D:5:0111111111).lfthe
applied digital input is interpreted as the decimal equivalent
of a true binary word, VOUT can be found by:
5.1.2 Providing a Bipolar Output Voltage with the
DAC in the Current Switching Mode
2'sComp.
(Decimal)
+511
+256
0
-1
-256
-512
0:5:D:5:1023
With this configuration, only the offset voltage of amplifier 1
need be nulled to preserve linearity of the DAC. The offset
voltage error of the second op amp has no effect on linearity. It presents a constant output voltage error and should be
nulled only if absolute accuracy is needed. Another advantage of this configuration is that the values of the external
resistors required do not have to match the value of the
internal DAC resistors; they need only to match and temperature track each other.
A thin film 4 resistor network available from Beckman Instruments, Inc. (part no. 694-3-Rl0K-D) is ideally suited for this
application. Two of the four available 10 k!l resistor can be
paralleled to form R in Figure 5 and the other two can be
used separately as the resistors labeled 2R.
Operation is summarized in the table below:
D
VO=VREFX 512
2'sComp.
(Binary)
Applied
Digital Input
Applied
True Binary
(Decimal)
+VREF
-VREF
0111111111
0100000000
0000000000
1111111111
1100000000
1000000000
1111111111
1100000000
1000000000
0111111111
0100000000
0000000000
1023
768
512
511
256
0
VREF-l LSB
VREF/2
0
-1 LSB
-VREF/2
-VREF
-IVREFI+l LSB
-IVREFI/2
0
+1 LSB
+IVREFI/2
+IVREFI
with: 1 LSB='VREFI
512
vcc
o
o
o
......
C
l>
D-512)
VO=VREF ( ~
The addition of a second op amp to the circuit of Figure 4
can be used to generate a bipolar output voltage from a
fixed reference voltage Figure 5. This, in effect, gives sign
significance to the MSB of the digital input word to allow two
quadrant multiplication of the reference voltage. The polarity
of the reference can also be reversed to realize the full fourquadrant multiplication.
The applied digital word is offset binary which includes a
code to output zero volts without the need of a large valued
resistor common to existing bipolar multiplying DAC circuits.
Offset binary code can be derived from 2's complement
data (most common for signed processor arithmetic) by inverting the state of the MSB in either software or hardware.
After doing this the output then responds in accordance to
the following expression:
c
~
.....
VOUT
o
.....
o
o.....
......
C
~
.....
o
o
N
......
C
~
.....
o
o
Q)
......
~
......
o
o
......
......
~
o
.....
o
o
co
IOUTl
I +15VOC)
RIB
-VREF
MICRO·OAC
YOUT
-::-
-::-
oVOC .. YOUT .. + VREF G~
FIGURE 4. Providing a Unipolar Output Voltage
II
Vcc
±VaEF
MICRO·OAC
L-________~GTND~IO~UTr~~---1~
VOUT
TL/H/5688-11
FIGURE 5. Providing a Bipolar Output Voltage with the DAC in the Current Switching Mode
4-65
m
r-----------------------~------------------------------------------------------~
g
g
g
o
o
......
.....
o
o
U;
o
o
~
-.....
g
g
-o
o
g
C;
-g
o
o
5.2 Analog Operation in the Voltage Switching Mode
Some useful application circuits result if the R·2R ladder Is
operated in the voltage switching mode. There are two very
important things to remember when using the DAC in the
voltage mode. The reference voltage (+ V) must always be
positive since there are parasitic diodes to ground on the
IOUTl pin which would turn on if the reference voltage went
negative. To maintain a degradation of linearity less than
±O.005%, keep +V S; 3 Voe and Vee at least 10V more
positive than + V. Agures 6 and 7 show these errors for the
voltage switching mode. This operation appears unusual,
since a reference voltage (+ V) is applied to the IOUT1 pin
and the voltage output is the VREF pin. This basic idea is
.
shown in Agure 8.
Notice that this is unipolar operation since ali voltages are
positive. A bipolar output voltage can be obtained by using a
single op amp as shown in Figure 10. For a digital input
code of ali zeros, the output voltage from the VREF pin is
zero volts. The external op amp now has a single input of
+V and is operating with a gain of -1 to this input. The
output of the op amp therefore will be at - V for a digital
input of ali zeros. As the digital code increases, the output
voltage at the VREF pin increases.
Notice that the gain of the op amp to voltages which are
applied to the (+) input is + 2 and the gain to voltages
which are applied to the input resistor, R, is -1. The output
voltage of the op amp depends on both of these inputs and
is given by:
This VOUT range can be scaled by use of a non·inverting
gain stage as shown in Figure 9.
VOUT=(+V} (-1)+VREF(+2)
+.1
~
+.1
b. LINEARITY ERROR
+.05
a:
co
a:
b. GAIN EftROR
a:
co
!!!
..
I
-.05
-.1
o
b. GAIN ERROR
:!l
Z
f-1
, "-
!5
........
CD
c
:z:
,
, b. LINEARITY ERROR
~ +.05
~
15
...!!!
.
I
'I
-.06
C=,5V
-jV=fV
1 234 567
RERRENCE VOLTAGE. +V (Yocl
-.1 0
2
4
&
8
10 12 14
16
SUPPLY YOLTASE, vcc (Vocl
FIGURE 7
FIGURE 6
DIGITAL INPUT CODE
(MSII
Olg
018
017 • • • • •
0
(YREFI
0
011
DID (LSII
1
0
R
YOUT
2R
2R
0" VOUT" 2.5YOC
VCC
Om)
2R
2R
":"
2R
R" 15kg
( +15Vocl
MICRO·OAC
VOUT
R2
OVOC " YOUT" +2.5VOC (1 + ~)(Ii)
TL/H/566B-12
FIGURE 9. Amplifying the Voltage Mode Output (Single Supply Operation)
4·66
g
(")
......
o
o
~
Vcc
-2.5VOC" VOUT" 2.5VUC (::})
"VREF"
~
VOUT
......
oo
......
....
+V
(+2.500 VOC)
~
(LM336)
......
o
o
FIGURE 10. Providing a Bipolar Output Voltage with a Single Op Amp
~
~
+V
(+ 2.500 VOC)
......
o
o
~
~
:>-......-oVOUT
"VREF"
......
o
o
~
o .. VOAC .. +2.5 VUc
(lgm
TUH/56BB-13
FIGURE 11. Increasing the Output Voltage Swing
The output voltage swing can be expanded by adding 2
resistors to Figure 10 as shown in Figure ". These added
resistors are used to attenuate the + V voltage. The overall
gain, Av( -), from the + V terminal to the output of the op
amp determines the most negative output voltage, -4(+ V)
(when the VREF voltage at the + input of the op amp is
zero) with the component values shown. The complete dynamic range of VaUT is provided by the gain from the (+)
input of the op amp. As the voltage at the VREF pin ranges
from OV to +V(1023/1024) the output of the op amp will
range from -10 Vee to +10V (1023/1024) when using a
+ V voltage of + 2.500 Vee. The 2.5 Vee reference voltage
can be easily developed by using the LM336 zener which
can be biased through the RFB internal resistor, connected
to Vee.
~......
o
oQ)
If the Vas is to be adjusted there are a few pOints to consider. Note that no "de balancing" resistance should be used
in the grounded positive input lead of the op amp. This resistance and the input current of the op amp can also create
errors. The low input biasing current of the BI-FET op amps
makes them ideal for use in DAC current to voltage applications. The Vos of the op amp should be adjusted with a
digital input of all zeros to force IOUT= 0 mAo A 1 kO resistor
can be temporarily connected from the inverting input to
ground to provide a dc gain of approximately 15 to the VOS
of the op amp and make the zeroing easier to sense.
5.4 Full-Scale Adjust
The full-scale adjust procedure depends on the application
circuit and whether the DAC is operated in the current
switching mode or in the voltage switching mode. Techniques are given below for all of the possible application
circuits.
5.3 Op Amp Vos Adjust (Zero Adjust) for Current
Switching Mode
Proper operation of the ladder requires that all of the 2R
legs always go to exactly 0 Voc (ground). Therefore offset
voltage, Vos, of the external op amp cannot be tolerated as
every millivolt of Vos will introduce 0.01 % of added linearity
error. At first this seems unusually sensitive, until it becomes
clear the 1 mV is 0.01 % of the 10V reference! High resolution converters of high accuracy require attention to every
detail in an application to achieve the available performance
which is inherent in the part. To prevent this source of error,
the Vas of the op amp has to be initially zeroed. This is the
"zero adjust" of the DAC calibration sequence and should
be done first.
5.4.1 Current Switching with Unipolar Output Voltage
After doing a "zero adjust," set all of the digital input levels
HIGH and adjust the magnitude of VREF for
.
1023
VauT= -(Ideal VREF) 1024
This completes the DAC calibration.
4-67
II
co
CI
CI
r---------------------------------------------------------------------------------,
....
~
§....
~......
U)
CI
CI
....
o
a
~
CI
CI
....
5.4.2 Current Switching with Bipolar Output Voltage
The circuit of Figure 12 shows the 3 adjustments needed.
The first step is to set all of the digital inputs LOW (to force
IOUTl to 0) and then trim "zero adj." for zero volts at the
inverting input (pin 2) of OA1. Next, with a·code of all zeros
still applied, adjust "- FS adj.", the reference voltage, for
VOUT= ±i(ideal VREF)i. The sign of the output voltage will
be opposite that of the applied reference.
5.4.3 Voltage Switching with.a Unipolar Output Voltage
Refer to the circuit of Figure 13 and set all digital inputs
LOW. Trim the "zero adj." for VOUT= 0 Voc± 1 mY. Then
set all digital inputs HIGH and trim the "FS Adj." for:
Rl)1023
VOUT=(+V) ( 1 + - - - R2 1024
5.4.4 Voltage Switching with a Bipolar Output Voltage
Finally, set all of the digital inputs HIGH and adjust "+ FS
adj." for VOUT=VREF (511/512). The sign of the output at
this time will be the same as that of the reference voltage.
The addition of the 2000 resistor in series with the VREF pin
of the DAC is to force the circuit gain error from the DAC to
be negative. This insures that adding resistance to Rib, with
the 500n pot, will always compensate the gain error of the
DAC.
Refer to Figure 14 and set all digital inputs LOW. Trim the
"-FS Adj." for VOUT= -2.5 Voc. Then set all digital inputs
HIGH and trim the "+FS Adj." for VOUT= +2.5 (511/512)
Voc. Test the zero by setting the MS digital input HIGH and
all the rest LOW. Adjust Vos of amp #3, if necessary, and
recheck the full-scale values.
o
a..........
CI
CI
....
o
a
(+FS AOJ)
500
(-FS AOJ)
±VREF
200
§....
YoUT
~
511 )
-VAEF<:VOUT<: +VAEF ( 512
FIGURE 12. Full Scale Adjust - Current Switching with Bipolar Output Voltage
VCC
( +15VOC)
"VREF"
MICRO·OAC
~:"",,-,,_VOUT
OVoc < YOUT < 2.5YoC (1 + ~WdH)
FS ADJ.
TL/H/5688-14
FIGURE 13. Full Scale Adjust - Voltage Switching with a Unipolar Output Voltage
4-68
g
(")
+Y
+FS
......
c
c
~
12.56YOC)
A~J.
-FS ADJ.
,...
MICRO-OAC
~I
100~
1
g
R" MATCH TO 0.01%
/r-:pOO!l~_~
R"
R"
15K
15K
(")
......
c
c......
2
rV
~n ~r
J
......
g
1.78K
'-
-==-
b>~~'
(")
......
c
C
N
......
g
(ill)
-2.5Y" YOUT" 2.5 512 Y
TL/H/56BB·15
FIGURE 14_ Voltage Switching with a Bipolar Output Voltage
6_0 DIGITAL CONTROL DESCRIPTION
The DAC1000 series of products can be used in a wide
variety of operating modes. Most of the options are shown
in Table 1. Also shown in this table are the section numbers
of this data sheet where each of the operating modes is
discussed. For example, if your main interest in interfacing
to a ,...p with an B-bit data bus you will be directed to Section
6.1.0.
transfer, or updating, of more than one DAC.
For operating without a ,...p in the stand alone mode, three
options are provided: 1) using only a single digital data buffer, 2) using both digital data buffers - "double buffered," or
3) allowing the input digital data to "flow through" to provide
the analog output without the use of any data latches.
To reduce the required reading, only the applicable sections
of 6.1 through 6.4 need be considered.
The first consideration is "will the DAC be interfaced to a ,...p
with an B-bit or a 16-bit data bus or used in the stand-alone
mode?" For the B-bit data bus, a second selection is made
on how the 2nd digital data buffer (the DAC Latch) is updated by a transfer from the 1st digital data buffer (the Input
Latch). Three options are provided: 1) an automatic transfer
when the 2nd data byte is written to the DAC, 2) a transfer
which is under the control of the ,...p and can include more
than one DAC in a simultaneous transfer, or 3) a transfer
which is under the control of external logic. Further, the data
format can be either left justified or right justified.
When interfacing to a ,...p with a 16-bit data bus only two
selections are available: 1) operating the DAC with a single
digital data buffer (the transfer of one DAC does not have to
be synchronized with any other DACs in the system), or 2)
operating with a double digital data buffer for simultaneous
(")
......
c
c
~
~
......
c
c
.....
......
g
(")
......
c
c
C»
6.1 Interfacing to an 8-Blt Data Bus
Transferring 10 bits of data over an 8-bit bus requires two
write cycles and provides four possible combinations which
depend upon two basic data format and protocol decisions:
1. Is the data to be left justified (considered as fractional
binary data with the binary pOint to the left) or right justified (considered as binary weighted data with the binary
point to the right)?
2. Which byte will be transferred first, the most significant
byte (MS byte) or the least significant byte (LS byte)?
Table 1
Operating Mode
Data Bus
8-Bit Data Bus (6.1.0)
Right Justified (6.1.1)
Left Justified (6.1.2)
Automatic Transfer
Section
6.2.1
6.2.1
,...p Control Transfer
Figure No.
(24-Pin)
(20-Pln)
16
17
1B
Section
6.2.2
6.2.2
Single Buffered
16-Bit Data Bus (6.3.0)
6.3.1
19
6.4.1
19
16
17
18
Section
6.2.3
6.2.3
Double Buffered
20
6.3.2
Single Buffered
Stand Alone (6.4.0)
Figure No.
(24-Pin)
(20-Pin)
External Transfer
19
6.4.2
4-69
19
16
17
1B
Flow Through
20
Not Applicable
Flow Through
Double Buffered
20
Figure No.
(20-Pln)
(24-Pln)
20
6.4.3
19
NA
II
6.1.2 For Left Justified Data
For applications which require left justified data, DAC10061008 (20-pin parts) can be used. A simplified logic diagram
which shows the external connections to the data bus and
the internal functions of both of the data buffer registers
(Input Latch and DAC Register) is shown in Rgure 18.
These parts require the MS or Hi Byte data group to be
transferred on the 1st write cycle.
These data possibilities are shown in Figure 15. Note that
the justification of data depends on how the 10-bit data
word is located within the 16-bit data source (CPU) register.
In either case, there is a surplus of 6 bits and these are
shown as "don't care" terms (" x ") in this figure.
All of these DACs load 10 bits on the 1st write cycle. A
particular set of 2 bits is then overwritten on the 2nd write
cycle, depending on the justification of the data. This requires the 1st write cycle to contain the LS or LO Byte data
group for all right justified data options. For all left justified
data options, the 1st write cycle must contain the MS or Hi
Byte data group.
6.2 ContrOlling Data Transfer for an 8-Blt Data Bus
Three operating modes are possible for controlling the
transfer of data from the Input Latch to the DAC Register,
where it will update the analog output voltage. The simplest
is the automatic transfer mode, which causes the data
transfer to occur at the time of the 2nd write cycle. This is
recommended when the exact timing of the changes of the
DAC analog output are not critical. This typically happens
where each DAC is' operating individually in a system and
the analog updating of one DAC is not required to be synchronized to any other DAC. For synchronized DAC updating, two options are provided: ,.p control via a common
XFER strobe or external update timing control via an external strobe. The details of these options are now shown.
6.1.1 Providing for Optional Data Format
The DAC1000/1/2 (24-pin parts) can be used for either
data formatting by tying the LJ/RJ pin either high or low,
respectively. A simplified logiC diagram which shows the external connections to the data bus and the internal functions
of both of the data buffer registers (Input Latch and DAC
Register) is shown in Figure 16 for the right justified data
operation. Figure 17 is for left justified data.
I-----I.IITIYT£----!-----I.IITIVTE---..j
LO
1
!MsaEHU+++AEHLSI! xIxIxIxIxIxI
1
.,
1
LO
'1
! x! x! x! x! xIx!MsaEF++usl'FIEo:oATH+sa!
1
I.
HI BYTE
BYTE
1m
BYTE
FIGURE 15. Fitting a 10-Blt Data Word into 16 Available Bit Locations
DAC1000/100111002 (24-Pin Parts)
ElItJ
~
"I
DIg IMSl)
10
I.IIT
DATA
IUS
I ~
I
,I
..lIT
TO
CURRENT
SWITCHES
:
~:l!~
l
----------------~
a
a
~Ul
WIlEN:
ll'm! !IIDll =1,Q
~s FOLLOW DINPUTS.
AT
0 IS~ED.O'
DATA
TUH/5688-16
FIGURE 16. Input Connections and Controls for DAC1000-1002 Right Justified Data Option
4-70
~
......
o
o
o
........
C
~
......
o
o
......
.......
DAC1000/100111002 (24-Pin Parts)
:~DaiT~llI1~!DI9~~(!MS~a!)~j(~~:l~~~~~~
~
10
I~~~~
8.BIT:
2!
DATA BUS
Da~
o
o
N
........
LATCH
20
19
......
I
DI~
(LSB)
TO
CURRENT
SWITCHES
10·81T
DAC
LATCH
g
o
......
I
o
o
17
Q)
.......
I
.1
~
......
o
o
rol:RERm:E=I.D
OUTPUTS FOLLOW 0 INPUTS.
rol:R ERm:E=o. DATA
AT 0 IS LATCHED.
~~~[:~~~----~
WiiiOo
(~)mmO:~~E:~------------------------J
W1120
......
........
C
I
21
v+~
W/iiJ
C
!ArnL
EHlm: WHEN:
ayt.l/B;iiZo--"t-----rl
(INTERNAL LOGIC IS SHOWN FOR
LF/RJ = I-LEFT JUSTIFIED)
~
......
o
o
co
FIGURE 17. Input Connections and Controls for DAC1000-1002 Left Justified Data Option
DAC1006/100711008 (20-Pin Parts for Left Justified Data)
I
OBT
I
9
Dig (MSa)
a
T
6
a·alT
DATA BUS
a·BIT
INPUT
LATCH
1
lB
1
DB~
I
TO
CURRENT
SWITCHES
01. (LSB)
16'
15
Byt.lIa;ti"f
CI
WHEN:
\VII
WCII ERm:E = 1.0
OUTPUTS FOLLOW 0 INPUTS.
mcJI ERm:E=o. DATA
AT 0 IS LATCHEO.
(CH)
mil
TLlH/5688-17
FIGURE 18. Input Connections and Controls for DAC1006/1007/1008 Left Justified Data
4-71
6.2.1 Automatic Transfer
This makes use of a double byte (double precision) write. The first byte (8 bits) is strobed into the input latch and the second
byte causes a simultaneous strobe of the two remaining bits into the input latch and also the transfer of the complete 1O-bit word
from the input latch to the DAC register. This is shown in the following timing diagrams; the point in time where the analog output
is updated is also indicated on these diagrams.
DAC1000/100111002 (24-Pin Parts)
'Wi
----\-·r~_
LATCH~T-C_
\J.JLOAD Byt. 1
'WIIl aim
DAC1006/1007/1008 (20-Pin Parts)
LOAD 8ytt 2
LATCH OAC
~.t;~1
)L1-r~~~TER
~\
Bvte 11 iiii2 •
xm!'
ANALOG
OUTPUT
UPDATED
LOAD Byte 1
.
a rna -----\-) -,.- ~_
LATCH
\J.J-~.:
Byte 1IByt. 2
'----TL/H/5688-18
'SIGNIFIES CONTROL INPUTS WHICH ARE DRIVEN IN PARALLEL
6,2.2 Transfer Using ",p Write Stroke
The input latch is loaded with the first two write strobes. The XFER signal is provided by external logic, as shown below, to cause
the transfer to be accomplished on a third write strobe. This is shown in the following diagrams:
DAC1000/1001/1002 (24-Pin Parts)
t\,----,t.LG
CI" \
~
LOAD Byte 1
OUTPUT
UPDATED
LOAD Byt. 2
DAC1006/100711008 (20-Pin Parts)
eJ
LATCH OAC
REGISTER
LOAD Byt. 1
2\l.r
rna
1~2-----
~\
LATCH OAC
REGISTER
LATCH Byte 2
LATCH Byt. 2
8ytt 1Iijiil
OUTPUT
UPDATED
LOAD Byte 2
Wi~B~tr
~alm~~V?2
\I...----I/\,_---II.LG
Byte1lByte 2
I
. ?(-----
~W
22
~\
I
r----
?~-----
WHERE THE XRR CONTROL CAN BE GENERATED BY USING A SECOND CHIP SElECT AS:
'-:g====QJO-----oOxm!
AND THE BYTE CON11l0L CAN BE DERIVED FllDM THE ADDRESS BUS SI&NALS.
TUH/5688-19
6.2.3 Transfer Using an External Strobe
This is similar to the previous operation except the XFER signal is not provided by the ",P. The timing diagram for this is:
DAC1000/1001/1002 (24-Pin Parts)
LOAD Byt. 1
m
LOAD Byte 2
DAC1006/1007/1008 (20-Pin Parts)
t-2_ _ __
~~ATCHByt'2
2~,--_ _~ /----
-
~~FER
I LATCH DAC
~~~~3~
~2'----ANALOG
UPDATED
2U
3~r:~lo -
t
XFER
Byt.1I
Iiiil
LATCH DAC
REGISTER
2~
REGISTER
,'-----
~2'_----TUH/5688-20
4-72
c
6.3 Interfacing to a 16-Bit Data Bus
The interface to a 1S-bit data bus is easily handled by connecting to 10 of the available bus lines. This allows a wiring selected
right justified or left justified data format. This is shown in the connection diagrams of Figures 19 and 20, where the use of DBS
to DB15 gives left justified data operation. Note that any part number can be used and the Byte1 IByte2 control should be wired
1.;
....
c
c
c
.....
C
Hi.
1.;
....
c
....
.....
c
....c~
c
JUSTIFIED
Rb\~T
.....
I\)
I
~:~
I"
DI9 IMS81
1.;
....
I===:l~
9
8
7
,6·BIT
DATA BUS
C
I------ID
'0
I - - - -.....-ID
lD·8IT
DATA
LATCH
21
20
19
18
I-~:::::::::~DD REGISTER
'~:JT
c
c
TD
CURRENT
SWITCHES
D
en
.....
~
....
c
D
D
D
17
~
By1I1/Bjii1 Plno-....:.......- - - - f
tl,d ta +VCC
WHEN:
CI ......--"'........--....
c
.....
.....
=mm=I.Q
OUTPUTS FOllOW 0 INPUTS.
g
=mm=o, DATA
AT 0 IS LATCHED.
m ..........,r-uli.-'
o....
iFEiiO::jt::[)-------------J
Iml Wii20
c
cQ)
I
UlRl=X21
IDDN'T CAREI---Y
I
FIGURE 19. Input Connections and Logic for DAC1000-1002 with 16-Bit Data Bus
LEFT
I
JUSTIFIED I
DAC1D0611DD7I10DB (2IJ.PlN PARTSI
~~:D:Bl:5:t:~ID:19:(:M:SB:I::::::I~--~:::::::::::f::---~~ MSB
7
0
6
,~
'6·BIT
DATA
::j.WJ
'~:Jl
0
TO
CURRENT
SWITCHES
0
B_UlS~~~j~~~~~~~~L~LA~T~CHj~~~~~~l~R~EG~IS~TE~Rjl
~
I__.-q-, =E
DB61 Dloll (LSBI
cs, ...
LSB
~
Wii2~1--t-~.....I
CD:J:
WHEN:
OL
LAffif EllAlItr = 1,Q
:
I
(ffiijIXFER4~-~~~~~-------~--~
I
31
+VCCo----:t (EQUIVALENT LDGIC SHDWN
Byte lIBy1' 2 I FOR THIS PIN HIGHI
OUTPUTS FOllOW D INPUTS.
mc!fmB[f=O,OATA
AT D IS LATCHED.
TL/H/5688-21
FIGURE 20. Input Connections and Logic for DAC1006/100711008 with 16-Blt Data Bus
4-73
8
~
§....
~
§....
~
.....
N
«:)
«:)
....
Three operating modes are possible: flow through, single buffered, or double buffered. The timing diagrams for these are shown
below:
6.3.1 Single Buffered
DAC1000/100111002 (24·Pln Parts)
,\......_----J!
~
Wifi & Wiii
ANALOG
OUTPUT
UPOATED-
aytJlIliiiil=1
9=0
t
~
iiIII
"
lATCHES DATA IN
DAC REGISTER
ANALOI
OUTPUT _
UPOATED
1m=0
L-J,
" INPUT DATA IS
\
lATCHED
LOAD INPUT lATCH
DAC1 0061 1007/1008 (20·Pln Parts)
\\......_--J!
u
INPUT DATA IS lATCHED
INPUT DATA IS lATCHED
WRi~2
....
XFER AND lATCH
"' DAC REGISTER
-
LOAD INPUT lATCH'
XFER TO DAC REGISTER
Ci
«:)
«:)
iii
'-.. LOAD INPUT lATCH
-
----~2~--------ayl. 11 iiii1
\
....
LOAD INPUT lATCH
ANALOO
'---------
«:)
«:)
~
\L____.....J/,
6.3.2 Double Buffered
DAC 1000/100111002 (24·Pln Parts)
.....
....
~
c:;
DAC1006/1007/1008 (20·Pln Parts)
....._ J
81lllT~t .......,~
XFER
~
..... DAC REGISTER
t
IS lATCHED
iF£ii OR WR2
ANALOG
OUTPUT -..,.,
UPOATE
XFER
TUH/5688-22
6.4 Stand Alone Operation
For applications for a DAC which are not under ,.:P control (stand alone) there are two basic operating modes, single buffered
and double buffered. The timing diagrams for these are shown below:
6.4.1 Single Buffered
DAC1000/1001/1002 (24·Pln Parts)
9/111
""""\
,
DAC1006/1007/1008 (20·Pln Parts)
XFER TO OAC REGISTER
,.-t.2
L--...J-- lATCH INPUT LATCH
lytJ 1I1ytJ 2
\/
~D INPUT
LATCH
1"-,-
I
ANALOG
LATCHES DATA IN DAC REGISTER
3~'¥10
LOAD INPUT LATCH
u=rn'\'mlAT:.uE~T REMAIN VAUD
6.4.2 Double Buffered
DAC1000/100111002 (24-Pln Parts)
IiIii
""""\
,
DAC1006/1007/1008 (20'Pin Parts)·
LOAD INPUT LATCHr-_ _ _ _ _ __
,.-t.2
L--...J- LATCH INPUT lATCH
Wi \
LOAD INPUT LATCH
wn
cs=XFEli=o
.ytJl/ijiiZ=1
/
/ _ LATCH INPUT LATCH
XFER
r~~
\ / r:::cH DAC
UPOATED-~--..J
REDISTER
2~XFER
ANALOD '
OUTPUT _
UPOATED
I
"
LATCH DAC
REGISTER
TUH/5688-23
'For a connection diagram of this operating mode use Fl{Juf8 18 for the Logic and Figuf8 20 for the Data Input connections.
4-74
~.....
6.4.3 Flow Through
This operating mode causes the 10·bit input word to directly create the DAC output without any latching involved.
c
c
~
g
DAC1000/l00l/1002 (24-Pin Parts)
o
.....
c
c
.....
......
WR1 ~WR2~CS~XFER~D
By191/By192~1
g
7.0 MICROPROCESSOR INTERFACE
The circuit will perform an automatic transfer of the 10 bits
of output data from the CPU to the DAC register as outlined
in Section 6.2.1, "Controlling Data Transfer for an 8-Bit Data
Bus."
Since a double byte write is necessary to control the DAC
with the INS8080A, a possible instruction to achieve this is a
PUSH of a register pair onto a "stack" in memory. The 16bit register pair word will contain the 10 bits of the eventual
DAC input data in the proper sequence to conform to both
The logic functions of the DAC1000 family have been oriented towards an ease of interface with all popular /LPs. The
following sections discuss in detail a few useful interface
schemes.
7.1 DAC1001/112 to INS8080A Interface
Figure 21 illustrates the simplicity of interfaCing the
DAC1000 to an INS8080A based microprocessor system.
o
.....
c
c
I\)
......
g
o.....
c
cQ)
......
~.....
c
c
......
......
~
.....
c
c
co
VOUT
TLlH/5688-24
NOTE: DOUBLE BYTE STORES CAN BE USED.
9.g. THE INSTRUCTION SHLD FDD1 STORES THE L
REG INTO B1 AND THE H REG INTO B2 AND
TRANSFERS THE RESULT TO THE DAC REGISTER.
THE OPERAND OF THE SHLD INSTRUCTION MUST
BE AN ODD ADDRESS FOR PROPER TRANSFER.
FIGURE 21. Interfacing the DAC1000 to the INS8080A CPU Group
4-75
co ,---------------------------------------------------------------------------------,
o
the requirements of the DAC (with regard to right or left
PIA, and the LOW byte is loaded into ORB. The 10-bit data
o
~r:::
o
o.,...
~
c
.....
CD
o
o
.,...
g
.....
N
o
o
.,...
g
.....
.,...
o
o
.,...
o
g
.....
o
o
o
.,...
g
justified data) and the implementation of the PUSH instruction which will output the higher order byte of the register
pair (i.e., register B of the BC pair) first. The DAC will actually appear as a twO-byte "stack" in memory to the CPU. The
autO-decrementing of the stack pointer during a PUSH allows using address bit 0 of the stack pOinter as the Bytell
Byte2 and XFER strobes if bit 0 of the stack pointer address
-1, (SP-l), is a "1" as presented to the DAC. Additional
address decoding by the DM8131 will generate a unique
DAC chip select (CS) and synchronize this CS to the two
memory write strobes of the PUSH instruction.
transfer to the DAC and the corresponding analog output
change occur simultaneously upon CB2 going LOW under
program control. The 10-bit data word in the DAC register
will be latched (and hence VOUT will be fixed) when CB2 is
brought back HIGH.
If both output ports of the PIA are not available, it is possible
to interface the DACI 000 through a Single port without
much effort. However, additional logic at the CB2(or CA2)
lines or access to some of the 6800 system control lines will
be required.
To reset the stack pOinter so new data may be output to the
same DAC, a POP instruction followed by instructions to
insure that proper data is in the DAC data register pair before it is "PUSHED" to the DAC should be executed, as the
POP instruction will arbitrarily alter the contents of a register
pair.
Another double byte write instruction is Store Hand L Direct
(SHLD), where the HL register pair would temporarily contain the DAC data and the two sequential addresses for the
DAC are specified by the instruction op code. The auto incrementing of the DAC address by the SHLD instruction
permits the same simple scheme of using address bit 0 to
generate the byte number and transfer strobes.
7.3 Noise Considerations
A typical digital/microprocessor bus environment is a tremendous potential source of high frequency noise which
can be coupled to sensitive analog circuitry. The fast edges
of the data and address bus Signals generate frequency
components of 10's of megahertz and can cause noise
spikes to appear at the DAC output. These noise spikes
occur when the data bus changes state or when data is
transferred between the latches of the device.
In low frequency or DC applications, low pass filtering can
reduce these noise spikes. This is accomplished by overcompensating the DAC output amplifier by increasing the
value of the feedback capaCitor (Cc in Figure 3) .
In applications requiring a fast transient response from the
DAC and op amp, filtering may not be feasible. Adding a
latch, DM74LS374, as shown in Agure 23 isolates the device from the data bus, thus eliminating noise spikes that
occur every time the data bus changes state. Another method for eliminating noise spikes is to add a sample and hold
after the DAC op amp. This also has the advantage of eliminating noise spikes when changing digital codes.
7.2 DAC1000 to MC6820/1 PIA Interface
In Figure 22 the DAC1000 is interfaced to an M6800 system
through an MC6820/1 Peripheral Interface Adapter (PIA). In
this case the CS pin of the DAC is grounded since the PIA is
already mapped in the 6800 system memory space and no
decoding is necessary. Furthermore, by using both Ports A
and B of the PIA the 10-bit data transfer, assumed right
justified again in two 8-bit bytes, is greatly simplified. The
HIGH byte is loaded into. Output Register A (ORA) of the
PAl 3
PlIO 2
PIA
CB2
PB7
PB6
PB5
PB4
PB3
PB2
17
1
15
14
13
12
PBl :0
PBO
VOUT
TUH/5688-25
FIGURE 22. DAC1000 to MC6820/1 PIA Interface
4-76
~
.....
o
o
o
.....
~.....
o
o
.....
.....
~
"'OUTPUT
LOG
.....
o
o
.....
~
""l..I"" CI FROM ' - - / - - - - - ,
~~:~~=>--t1r~~I:>-J
SYSTEM
C
NOTE: DATA HOLD TIME REDUCED TO THAT OF DM74LS374 ('" 10 ns)
ViR
l:;
.....
o
oQ)
A!lDRE::~1;~>_-..:::::jL')o-------I
.....
(LOW FOR BYTE 1
HIGH FOR BYTE 21
FIGURE 23. Isolating Data Bus from DAC Circuitry to Eliminate Digital NOise Coupling
~
o
.....
o
o
.....
.....
Msa
~
Lsa
.....
o
o
co
1SV
1Sk
MICRO·OAC
OAC1000 SERIES
Your
V-
V-
TUH/5688-26
FIGURE 24. Digitally Controlled Amplifierl Attenuator
7.4 Digitally Controlled Ampliflerl Attenuator
An unusual application of the DAC, Figure 24, applies the
input voltage via the on-chip feedback resistor. The lower
op amp automatically adjusts the VREF IN voltage such that
loun is equal to the input current (VIN/RfB). The magnitude
of this VREF IN voltage depends on the digital word which is
in the DAC register. IOUT2 then depends upon both the
magnitude of VIN and the digital word. The second op amp
converts IOUT2 to a voltage, VOUT, which is given by:
Note that N = 0 (or a digital code of all zeros) is not allowed
or this will cause the output amplifier to saturate at either
±VMAX' depending on the sign of VIN.
To provide a digitally controlled divider, the output op amp
can be eliminated. Ground the IOUT2 pin of the DAC and
VOUT is now taken from the lower op amp (which also drives
the VREF input of the DAC). The expression for VOUT is now
given by
1023-N)
VOUT=VIN ( - - N - ,where O
0.10
-r- ----1+
I
....
:!;
r- ~I!
~
_1!+~51!
CI
z
CC
0:
CC
0
a:
CI
a:
a:
:!;-O.05
::>
...
-'
::
m
0.05
i=
0.5
./
~
/
CC
'"
is
-0.10
0
0
20
40
60
80
5.0
TA - TEMPERATURE ('C)
10.0
15.0
V+ (VOLTS)
TLiH/5689-2
FIGURE 2_ Gain Error Variation vs V+
FIGURE 1. Digital Input Threshold vs
Ambient Temperature
4-81
•
w.-------------------------------------------------~
w
w
....
g
.....
....w
....w
~
.....
o
w
....w
~
.....
w
w
o
....
g
.....
....w
o
....
g
.....
~
o
....
~
c
Typical Applications
The following applications ani also valid for 12-bit systems
using the DAC1220 and 2 additional digital inputs.
Operational Amplifier Vos Adjust (Figure 3)
Connect all digital inputs, A 1-A10, to ground and adjust the
potentiometer to bring the op amp VOUT pin to within ± 1
mV from ground potential. If VREF is less than 10V, a finer
Vos adjustment is required. It is helpful to increase the resolution of the Vos adjust procedure by connecting a 1 kn
resistor between the inverting input of the op amp to
ground. After Vos has been adjusted, remove the 1 kn .
Operational Amplifier Bias Current (Figure 3)
The op amp bias current, Ib' flows through the 15k internal
feedback resistor. BI-FET op amps have low Ib and, therefore, the 15k x Ib error they introduce is negligible; they are
strongly recommended for the DAC1020 applications.
Vos Considerations
The output impedance, ROUT, of the DAC is modulated by
the digital input code which causes a modulation of the operational amplifier output offset. It is therefore recommended to adjust the op amp Vos. ROUT is - 15k if more than 4
digital inputs are high; ROUT is - 45k if a single digital input
is high, and ROUT approaches infinity if all inputs are low.
Full-Scale Adjust (Figure 4)
Switch high all the digital inputs, A1-A10, and measure the
op amp output voltage. Use a 500n potentiometer, as
shown, to bring IlvoUT11 to a voltage equal to VREF X
1023/1024.
SELECTING AND COMPENSATING THE OPERATIONAL AMPLIFIER
Op Amp Family
CF
RI
P
Vw
Circuit Settling
Time,ts
Circuit Small
SignalBW
LF357
LF356
LF351
LM741
10 pF
22pF
24pF
0
2.4k
25k
25k
10k
10k
V+
V+
VV-
1.5,...s
3,...s
4,...s
40,...s
1M
0.5M
0.5M
200 kHz
00
00
00
MSD
LSD
AI A2 A3 A4 AS A6 A7 AD A9 AID
TLIHI5689-3
AI
A2 A3
AIO )
VOUT= -VREF ( '2+'4+'8+ ···1024
-IOV ,;; VREF ,;; 10V
o ,;; VOUT ,;;
1023 V
- 1024 REF
where AN = I if the AN digital input is high
AN = 0 if the AN digital input Is low
FIGURE 3. BasiC Connection: Unipolar or 2..Quadrant Multiplying
Configuration (Digital Attenuator)
4-82
Typical Applications (Continued)
MSI
LSI
A1 A2 A3 A4 A5 AI A1 AI A9 AtD
15V
VREF
I.
15
VOUT
RfS 25DO
FULL-SCALE
DECREASE
FIGURE 4. Full-Scale Adjust
MSB
LSB
At A2 A3 A4 A5 A6 .7 A8 AS Ata
FIGURE 5. Alternate Full-Scale Adjust: (Allows Increasing or Decreasing the Gain)
DIGITAL WORD A
'MSI
LSI '
Al A2 A3 A. AS AI Al AI AI AID
DIGITAL WORD B
'MSI
LSI'
•
A1 A2 A3 A4 AS AI A1 A8 A9 AtD
TUH/5689-4
where VREF can be an AC signal
FIGURE 6. Precision Analog-to-Digital Multiplier
4-83
N
N
N
....
~....
Typical Applications (Continued)
COMPLEMENTARY OFFSET BINARY
(BIPOLAR) OPERATION
MIl
LSI
... , AI A3 A4 1105 AI 1.1 A' AI AID
"N
DIGITAL INPUT
....
000 o 0 0 0
000 o 0 0 0
0 1 1 1 1 1 1
100 000 0
1 0 0 0 0 0 0
1111111
N
~
YOUT
"oN
....
N
~
Note that:
N
• IOUT1
"o
....
o
VREF
x (1023)
-RLADDER
1024
• By doubling the output range we get half the
resolution
• The 10M resistor, adds a 1 LSB "thump", to
allow full offset binary operation where the out·
put reaches zero for the half·scale code. If
symmetrical output excursions are required,
omit the 10M resistor.
N
~
"o....
....
o
N
TL/H/5689-5
VOUT
=
AI
-VAEF (
A2
Al0
2'" +"4 + ••• + 1024 -
where: AN
AN
~
+ 1 if AN input is high
~
-1 if AN input is low
1)
1024
~
"o
o....
+ lOUT 2 =
---
FIGURE 7. Bipolar 4-Quadrant Multiplying Configuration
N
~
VOUT
000
+VREF
o 0 1 VREF X 1022/1024
1 1 1
VREF X 2/1024
0 o 0
0
001 -VREF X 2/1024
1 1 1 -VREF (1022/1024)
Operational Amplifiers Vos Adjust (Figure 7)
Gain Adjust (Full-Scale Adjust)
a)
Assuming that the external 1Ok resistors are matched to
better than 0.1 %, the gain adjust of the circuit is the same
with the one previously discussed.
Switch all the digital inputs high; adjust the Vos potentiometer of op amp B to bring its output to a value equal
to-(VREF/1024) (V).
b) Switch the MSB high and the remaining digital inputs
low. Adjust the Vos potentiometer of op amp A, to bring
its output value to within a 1 mV from ground potential.
For VREF < 10V, a finer adjust is necessary, as already
mentioned in the previous application.
MSI
MSB
LSI
lSI
AI AZ Al 1.4 AS Ai A1 AI A9 11010
AI AZ Al A4 AS Ai A7 AI AS A1D
15Y
TLlH/5689-6
TRUE OFFSET BINARY OPERATION
DIGITAL INPUT
1
1
0
ts
1
0
0
~
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
o
VOUT
1
0
0
1
0
0
1
0
0
R2
AvR4 ~ (2Av- -l)R'R1~ Av- -1'
R3 + Rl11R2
VREF X 1022/1024
0
-VREF
o
~
Example: VREF
~ VOUTIPEAKl. R ~ 20k
VREF
2V. VOUT (swing) .. ±10V: Av-
R; Av~
Then R4 ~ 9R. Rl
R3 ~ 0.64R
~
0.8 R2. If Rl
~
~
0.2R then R2
5V
~
0.25R.
1.8 p,s
FIGURE 9. Bipolar Configuration with
Increased Output Swing
use LM336 for a voltage reference
FIGURE 8. Bipolar Configuration with a Single Op Amp
4-84
Typical Applications
g
...
o
(Continued)
Q
MSB
LSB
A1 AZ A3 A4 AS A6 A1 AB AS A1D
N
.....
Q
~...
1SY
...
g
o
...
Q
N
.....
15
lour Z
Q
N
N
.....
g
Your 0-+----<
...
o
N
N
.....
Q
C
l:;
...
Y-
v
_
-VREF
...
g
o
...
OUT - (AI
A2 A3
Al0 )
-+-+-+
.2
4
8
.. 1024
N
N
.....
where: VREF can be an AC Signal
• By connecting the DAC in the feedback loop of an operational amplifier a linear digitally control gain block can be
realized
N
N
N
• Note that with all digital inputs low, the gain of the amplifier
is infinity, that is, the op amp will saturate. In other words, we
cannot divide the VREF by zero!
FIGURE 10. Analog-to-Dlgltal Divider (or Digitally Gain Controlled Amplifier)
MSB
LSB
A1 AZ A3 A4 AS A6 A1 AB AS A1D
Your
Y-
Y-
TLlH/5689-7
AI A2 ... +
Al0]
-+-+
2
4
1024
Your
~ VREF [ ~ + ~ + ... +~
2
4
~ VREF (--N-)
1023 - N
orVOUT
1024
where: 0 ,;: N ,;: 1023
N "'" 0 for AN = a\l zeros
N
~
1 forAl0
~
N
~
1023 for AN
I,Al-A9
~
~
alii's
FIGURE 11. Digitally controlled Amplifier-AHenuator
4-85
0
C'I
C'I
C'I
....
~..........
C'I
C'I
....
g
......
Typical Applications
(Continued)
O.lpf
"Vo-.....~M....-I
~
15V
10k
AAOI-4.1kN
" ",
"
B2
"
c
B4
C'I
C'I
16
15
15
5
•
14
14
•
7
13
13
7
I ". , "
....
" •,
B
~
11
B7
......
C'I
"
C'I
....
C
•
5
11
1010
11
1010
,
,
11
"
~
c
SINE WAVE OUT
......
....
C
....
C'I
~......
c
C'I
c
....
~
CLOCK
(FREQUENCY
CONTROL)
TLlH/5689-8
• Output frequency =
f~~~;
• Output voltage range
fMAX
~
2 kHz
= OV - 10V peak
• THO < 0.2%
• Excellent amplitude and frequency stability with temperature
• Low pass filter shown has a 1 kHz corner (for output frequencies below 10Hz.
filter corner should be reduced)
• Any periodic function can be implemented by modifying the contents of the look
up table ROM
• No start up problems
FIGURE 12. Precision Low Frequency Sine Wave Oscillator Using Sine Look-Up ROM
4-86
Typical Applications
(Continued)
LSS
11
ii
OVERFLOW
TO DAC1020
DIGITAL INPUTS
Il
15V
UP DWN
IIA ...........-o
MSS
MM74COO - NAND gates
MM74C32 - OR gates
MM74C74 - 0 flip-flop
MM74C193 - Binary upl
TLlH/5689-9
• Binary up/down counter digitally "ramps" the DAC
output
• Can stop counting at any desired 10-bit input code
• Senses up or down count overflow and automatically
reverses direction of count
FIGURE 13. A Useful Digital Input Code Generator for DAC Attenuator or Amplifier Circuits
4-87
N
N
N
r-------------------------------------------------------------------------~
.....
Definition of Terms
N
N
Resolution: Resolution is defined as the reciprocal of the
number of discrete steps in the Of A output. It is directly
related to the number of switches or bits within the Of A. For
example, the OAC1020 has 2 10 or 1024 steps while the
OAC1220 has 212 or 4096 steps. Therefore, the OAC1020
has 10-bit resolution, while the OAC1220 has 12-bit resolution.
SeHllng Time: Full-scale settling time requires a zero to fullscale or full-scale to zero output change. Settling time is the
time required from a code transition until the 01 A output
reaches within ± Y:z LSB of final output value.
Linearity Error: Linearity error is the maximum deviation
from a straight line passing through the endpoints of the
0/A transfer characteristic. It is measured after calibrating
for zero (see Vas adjust in typical applications) and fullscale. Linearity error is a design parameter intrinsic to the
device and cannot be externally adjusted.
Full-Scale Error: Full-scale error is a measure of the output
error between an ideal 01 A and the actual device output.
Ideally, for the OAC1020 full-scale is VREF-l LSB. For
VREF=10V
and
unipolar
operation,
VFULLSCALE=10.0000V-9.8 mV=9.9902V. Full-scale error is
adjustable to zero as shown in Figure 5.
~.....
......
.....
~
(:)
N
N
.....
~
......
N
Power Supply Sensitivity: Power supply sensitivity is a
measure of the effect of power supply changes on the 01 A
full-scale output.
N
Q
.....
~
C
......
.....
N
Q
.....
~......
Q
N
Q
.....
OAC FAILS END PDlNTTEST
LINEARITY ERROR ~ 1 LSB
~
IN
DIGITAL INPUT
IN
TL/H/5669-10
a
bl
(a) End pOint test after zero and full-scale adjust.
b2
(b) By shifting the full-scale calibration on of the OAC of
Figure (bt) we could pass the "best straight line" (b2)
test and meet the ± Y:z linearity error specification.
The OAC has 1 LSB linearity error.
Note. (a), (b1) and (b2) above illustrate the difference between "end point" National's linearity test (a) and "best straight line" test. Note that both devices in (a) and
(b2) meet the ± Yz LSB linearity error specification but the end point test is a more "real life" way of characterizing the DAC.
Connection Diagrams
DAC122X
Dual-In-Line Package
DAC102X
Dual-In-Llne Package
" "FEEDBACK
lOUT'
15 VREFIN
lOUT:!
....
UND 3
A2
11 AI
•
Ai •
1&
v.
.
A"
"
A'
AI
A"
A. •
" ..
"
A' '
AJ
.. J
AJ
VREFIN
15 Al1(L5Bi
Al(MS81
12 AI
ID
"FEEDBACK
17
13 Al0(lSB)
..
"
I. ..
TO' VIEW
TOP VIEW
4-88
TLlH/5669-11
g
....
~National
(")
I\)
<:)
~ Semiconductor
CD
......
g
....
MICRO-DACTM DAC1208/DAC 1209/DAC 121 O/DAC 12301
DAC1231/DAC1232 12-Bit, J.LP Compatible,
Double-Buffered D to A Converters
(")
I\)
<:)
CD
......
g
General Description
Features
The DAC1208 and the DAC1230 series are 12-bit multiplying D to A converters designed to interface directly with a
wide variety of microprocessors (8080, 8048, 8085, Z-80,
etc.). Double buffering input registers and associated controllines allow these DACs to appear as a two-byte "stack"
in the system's memory or I/O space with no additional interfacing logic required.
The DAC1208 series provides all 12 input lines to allow single buffering for maximum throughput when used with 16-bit
processors. These input lines can also be externally configured to permit an 8-bit data interface. The DAC1230 series
can be used with an 8-bit data bus directly as it internally
formulates the 12-bit DAC data from its 8 input lines. All of
these DACs accept left-justified data from the processor.
The analog section is a precision silicon-chromium (Si-Cr)
R-2R ladder network and twelve CMOS current switches.
An inverted R-2R ladder structure is used with the binary
weighted currents switched between the IOUT1 and IOUT2
maintaining a constant current in each ladder leg independent of the switch state. Special circuitry provides TTL logic
input voltage level compatibility.
The DAC1208 series and DAC1230 series are the 12-bit
members of a family of microprocessor compatible DACs
(MICRO-DACsTM). For applications requiring other resolutions, the DAC1000 series for 10-bit and DAC0830 series
for 8-bit are available alternatives.
• Linearity specified with zero and full-scale adjust only
• Direct interface to all popular microprocessors
• Double-buffered, single-buffered or flow through digital
data inputs
• Logic inputs which meet TTL voltage level specs (1.4V
logic threshold)
• Works with ± 1OV reference-full 4-quadrant
multiplication
• Operates stand-alone (without ,..P) if desired
• All parts guaranteed 12-bit monotonic
• DAC1230 series is pin compatible with the DAC0830
series 8-bit MICRO-DACs
....
....
(")
• Gain Tempco
• Low Power Dissipation
• Single Power Supply
<:)
......
....~
I\)
Co)
<:)
......
~....
I\)
Co)
....
......
g
....
(")
Key Specifications
• Current Settling Time
• Resolution
• Linearity (Guaranteed
over temperature)
I\)
,..s
1
12 Bits
I\)
Co)
I\)
10,11, or 12 Bits of FS
1.3 ppml"C
20 mW
5 VDC to 15 VDC
Typical Application
CONTROL BUS
fi
vce
511!l
FULL·SCALE
ADJUST
WRI
WRZ
15V
II
0
"m
'3.
DATA BUS
VDUT
+-Q15V
15k
ZERO
ADJUST
'::"
-15V
TUH/5690-1
4-89
Absolute Maximum Ratings
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
(Notes 1 and 2)
Supply Voltage (Vee)
Lead Temperature (Soldering, 10 seconds)
17Voc
VcctoGND
±25V
Voltage at Any Digital Input
Voltage at VREF Input
Storage Temperature Range
- 65°C to + 1500C
Package Dissipation at TA = 2SoC
(Note 3)
Range of Vcc
Voltage at Any Digital Input
SOOmW
DC Voltage Applied to loun or IOUT2
(Note 4)
ESD Susceptability
3000C
Temperature Range
TMIN:$; TA:$; TMAX
DAC1208LCJ, DAC1209LCJ,
DAC1210LCJ, DAC1230LCJ,
DAC1231 LCJ, DAC1232LCJ
-400C:$; TA:$; +85°C
DAC1208LCJ-1, DAC1209LCJ-1,
DAC121 OLCJ-1, DAC1230LCJ-1,
OOC:$; TA:$; +700C
DAC1231 LCJ-1, DAC1232LCJ-1
4.75 Voc to 16 Voc
VeetoGND
-100 mV to Vee
800V
Electrical Characteristics
VREF=10.000 Voc, Vcc=11.4 Voc to 15.75 Voc unless otherwise noted. Boldface limits apply from TMIN to TMAX (see
Note 13); all other limits TA = TJ = 25°C.
Parameter
Notes
Conditions
Resolution
Linearity Error
(End Point Linearity)
Differential Non-Linearity
Zero and Full-Scale
Adjusted
DAC1208, DAC1230
DAC1209, DAC1231
DAC1210, DAC1232
4,7,13
Zero and Full-Scale
Adjusted
DAC1208, DAC1230
DAC1209, DAC1231
DAC1210, DAC1232
4,7,13
Monotonicity
Gain Error (Min)
Gain Error (Max)
Using Internal RFb
Vrel = ±10V, ±1V
Gain Error Tempco
Power Supply Rejection
All Digital Inputs
Latched High
Reference Input Resistance (Min)
Reference Input ReSistance (Max)
Output Feedthrough Error
Output Capacitance
VREF=20 Vp-p, f= 100 kHz
All Data Inputs Latched
Low
IOUT2
Tested
Umlt
(Note 5)
Design
Limit
(Note 6)
Units
12
12
12
Bits
0.012
0.024
0.050
0.012
0.024
0.05
%ofFSR
%ofFSR
%ofFSR
0.018
0.024
0.050
0.018
0.024
0.05
%ofFSR
%ofFSR
%ofFSR
12
4
12
12
7
-0.1
0.0
7
-0.1
-0.2
7
±1.3
7
±3.0
±30
13
15
15
10
20
9
3.0
13
All Data Inputs Latched
Low
All Data Inputs Latched
High
Bits
% ofFSR
%ofFSR
±8.0
ppm of FS'oC
ppm of FSRIV
10
20
kO
mVp-p
200
70
70
200
pF
pF
pF
pF
2.0
2.5
rnA
All Data Inputs loun
Latched High
IOUT2
All Data Inputs loun
Latched Low
IOUT2
Supply Current Drain
Output Leakage Current
IOUTl
Typ
(Note 10)
11,13
0.1
15
15
nA
11,13
0.1
15
15
nA
Digital Input Threshold
Low Threshold
High Threshold
13
13
0.8
2.2
0.8
2.2
Voc
VOC
Digital Input Currents
Digital Inputs <0.8V
Digital Inputs > 2.2V
13
13
-200
10
-200
10
,...Aoc
,...Aoc
4-90
Electrical Characteristics (Continued)
VREF
=
10.000 VOC, Vcc
=
Note 13); all other limits TA
Symbol
11.4 VOC to 15.75 VOC unless otherwise noted. Boldface limits apply from TMIN to TMAX (see
=
TJ
=
25°C.
Parameter
Conditions
See
Typ
Note
(Note 10)
Tested
Design
Limit
Limit
(Note 5)
(Note 6)
Units
AC CHARACTERISTICS
ts
Current Setting Time
VIL
tw
Write and XFER
VIL
=
=
VIL
=
OV, VIH
=
=
OV, VIH
=
OV, VIH
5V
1.0
5V
50
Pulse Width Min.
tos
Data Setup Time Min.
6
p.s
320
320
70
5V
320
320
tOH
Data Hold Time Min.
VIL
=
OV, VIH
=
30
5V
90
90
tcs
Control Setup Time Min.
VIL
=
OV, VIH
=
60
5V
ns
320
320
tCH
Control Hold Time Min.
VIL
=
OV, VIH
=
10
0
5V
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: This SOO mW specification applies for all packages. The low intrinsic power dissipation of this part (and the faet that there is no way to signHicantly modify
the power dissipation) removes concern for heat sinking.
Note 4: Both IOUT1 and IOUT2 must go to ground or the virtual ground of an operational amplifier. The linearity error is degraded by approximately Vas'" VREF. For
example, if VREF= 10V then a 1 mV offset, Vas, on 10UT1 or IOUT2 will introduce an additional 0.01 % linearity error.
Note 5: Tested and guaranteed to National's AOOL (Average Outgoing Quailly Level).
Note 6: Design limits are guaranteed but not 100% tested. These limits are not used to calculate outgoing quality levels. Guaranteed for Vee = 11.4V to IS.7SV
and VREF = -10V to +10V.
Note 7: The unit FSR stands for full·scale range. Linearity Error and Power Supply Reiection specs are based on this unit to eliminate dependence on a particular
VREF value to indicate the true performance of the part The Linearity Error specification of the DAC120B is 0.012% of FSR(max). This guarantees that after
performing a zero and full·scale adjustment, the plot of the 4096 analog voltage outputs will each be within 0.012% x VREF of a straight line which passes through
zero and full·scale. The un~ ppm of FSR(parts per million of full-scale range) and ppm of FS(parts per million of full·scale) are used for convenience to define specs
of very small percentage values, typical of higher accuracy converters. In this Instance, 1 ppm of FSR=VREF/l06 is the conversion laetar to provide an actual
output voltage quantity. For example, the gain error tempco spec of ± 6 ppm of FSI'C represents a worst-case full·scale gain error change with temperature from
-40'C to + BS'C of ±(6)(VREF/l06)(125'C) or ±0.75 (10- 3) VREF which is ±0.075% of VREF.
Note 8: This spec implies that all parts are guaranteed to operate w~h a write pulse or transfer pulse width (tw) of 320 ns. A typical part will operate with tw of only
100 ns. The entire write pulse must occur wHhin the valid data interval for the specified tw, tos, tOH and Is to apply.
Note 9: To achieve this low feedthrough in the D package, the user must ground the metal lid. If the lid is left floating the feedthrough is typically 6 mV.
Note 10: Typicals are al' 25'C and represent the most likely parametriC norm.
Note 11: A 10 nA leakage current with RFb=20k and VREF=10V corresponds to a zero error of (10Xl0- 9 X20Xl03)Xl00% 10V or 0.002% of FS.
Note 12: Human body model, 100 pF discharged through a I.S kG resistor.
Note 13: Tested limH for -1 suffix parts applies only at 2S'C.
Connection Diagrams
Dual-In-Line Package
iii...!
Dual-In-Llne Package
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TOPYIEW
TL/H/5690-2
TO.YIEW
See Ordering Information
4-91
N
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Switching Waveforms
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TL/H/5690-3
Typical Performance Characteristics
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TLIH/5690-4
4·92
the DAC1230, DAC1231, and DAC1232 must be connected
to ground. It is important that lOUT1 and lOUT2 are at ground
potential for current switching applications. Any difference
of potential (Vos on these pins) will result in a linearity
change of
Definition of Package Pinouts
CONTROL SIGNALS (all control signals are level actuated)
CS: Chip Select (active low). The CS will enable WR1.
WR1: Write 1. The active low WR1 is used to load the digital
data bits (01) into the input latch. The data in the input latch
is latched when WR1 is high. The 12-bit input latch is split
into two latches. One holds the first 8 bits, while the other
holds 4 bits. The Byte 1/Byte 2 control pin is used to select
both latches when Byte 1I Byte 2 is high or to overwrite the
4-bit input latch when in the low state.
3VREF
For example, if VREF = 10V and these ground pins are 9
mV offset from lOUT1 and lOUT2' the linearity change will be
0.03%.
N
o
01)
......
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n
.....
N
o
CD
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C
)0-
Definition of Terms
Byte 1/Byte 2: Byte Sequence Control. When this control is
high, all 12 locations of the input latch are enabled. When
low, only the four least significant locations of the input latch
are enabled.
WR2: Write 2 (active low). The WR2 will enable XFER.
Resolution: Resolution is defined as the reciprocal of the
number of discrete steps in the DAC output. It is directly
related to the number of switches or bits within the DAC. For
example, the DAC1208 has 212 or 4096 steps and therefore
has 12-bit resolution.
Linearity Error: Linearity error is the maximum deviation
from a straight line passing through the endpoints of the
DAC transfer characteristic. It is measured after adjusting
for zero and full-scale. Linearity error is a parameter intrinsic
to the device and cannot be externally adjusted.
National's linearity test (a) and the best straight line test (b)
used by other suppliers are illustrated below. The best
straight line (b) requires a special zero and FS adjustment
for each part, which is almost impossible for the user to
determine. The end point test uses a standard zero FS adjustment procedure and is a much more stringent test for
DAC linearity.
XFER: Transfer Control Signal (active low). This signal, in
combination with WR2, causes the 12-bit data which is
available in the input latches to transfer to the DAC register.
DID to 0111: Digital Inputs. 010 is the least significant digital
input (LSB) and 0111 is the most significant digital input
(MSB).
loun: DAC Current Output 1. loun is a maximum for a
digital code of all 1s in the DAC register, and is zero for all
Os in the DAC register.
IOUT2: DAC Current Output 2. IOUT2 is a constant minus
IOUT1' or IOUTl + IOUT2 = constant (for a fixed reference
voltage). This constant current is
VREF X (1 -
~
n
.....
40~6)
Power Supply Sensitivity: Power supply sensitivity is a
measure of the effect of power supply changes on the DAC
full-scale output.
Settling Time: Full-scale current settling time requires zero
to full-scale or full-scale to zero output change. Settling time
is the time required from a code transition until the DAC
output reaches within ± % LSB of the final output value.
divided by the reference input resistance.
RFb: Feedback Resistor. The feedback resistor is provided
on the IC chip for use as the shunt feedback resistor for the
external op amp which is used to provide an output voltage
for the DAC. This on-chip resistor should always be used
(not an external resistor) since it matches the resistors in
the on-Chip R-2R ladder and tracks these resistors over
temperature.
Full-Scale Error: Full-scale error is a measure of the output
error between an ideal DAC and the actual device output.
Ideally, for the DAC1208 or DAC1230 series, full-scale is
VREF-1 LSB. For VREF= 10V and unipolar operation,
VFULL-SCALE = 1O.OOOOV - 2.44 mV = 9.9976V. Full-scale
error is adjustable to zero.
Differential Non-Linearity: The difference between any
two consecutive codes in the transfer curve from the theoretical 1 LSB is differential non-linearity.
Monotonic: If the output of a DAC increases for increasing
digital input code, then the DAC is monotonic. A 12-bit DAC
which is monotonic to 12 bits simply means that input increaSing digital input codes will produce an increasing analog output.
VREF: Reference Voltage Input. This input connects an external precision voltage source to the internal R-2R ladder.
VREF can be selected over the range of 10V to -10V. This
is also the analog voltage input for a 4-quadrant multiplying
DAC application.
Vee: Digital Supply Voltage. This is the power supply pin for
the part. Vcc can be from 5 Voc to 15 Voc. Operation is
optimum for 15 Voc.
GND: Pins 3 and 12 of the DAC1208, DAC1209, and
DAC1210 must be connected to ground. Pins 3 and 10 of
DIGITAL INPUT
TUH/5690-5
b) Shifting FS Adjust to Pass
Best Straight Line Test
a) End Point Test After Zero
and FS Adjust
4-93
n
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r------------------------------------------------------------------------------------------,
All of the digital inputs to these DACs contain a unique
.,... Application Hints
threshold regulator circuit to maintain TIL voltage level
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1.0 DIGITAL INTERFACE
These DACs are designed to provide all of the necessary
digital input circuitry to permit a direct interface to a wide
variety of microprocessor systems. The timing and logic level convention of the input control signals allow the DACs to
be treated as a typical memory device or 110 peripheral with
no external logic required in most systems. Essentially
these DACs can be mapped as a two-byte stack in memory
(or 110 space) to receive their 12 bits of input data in two
successive S-bit data writing sequences. The DAC1230 series is intended for use in systems with an S-bit data bus.
The DAC120S series provides all 12 digital input lines which
can be externally configured to be controlled from an S-bit
bus or can be driven directly from a 16-bit data bus.
compatibility independent of the applied Vee to the DAC.
Any input can also be driven from higher voltage CMOS
logic levels in non-microprocessor based systems. To prevent damage to the chip from static discharge, all unused
digital inputs should be tied to Vee or ground. As a troubleshooting aid, if any digital input is inadvertently left floating,
the DAC will interpret the pin as a logic "1".
Double buffered digital inputs allow the DAC to internally
format the 12-bit word used to set the current switching R2R ladder network (see section 2.0) from two S-bit data
write cycles. Figures 1 and 2 show the internal data registers and their controlling logic circuitry. The timing diagrams
for updating the DAC output are shown in sections 1.1, 1.2
and 1.3 for three possible control modes. The method used
depends strictly upon the particular application .
g
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0
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0
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0 1 - - - MS8
or-Dr--
0
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of--
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0
0
0
0
D
D
12·BIT
0
o
REGISTER
DAe
Of-Of-Q I---
12·81Y
MULTIPLVING
"A
CONVERTER
I--~
YREF
I--f!!
IOUT2
I-~r!!
loun
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LE
BYTE lIiYffi
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7
D 4-BIT
8
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33
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ru-
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GN'
GN'
LE
When
When
;:::
LE= I, Q oulputsfollow 0 Inputs
LE =0, Q outputs are latched
FIGURE 1. DAC1208, DAC1209, DAC1210 Functional Diagram
DI,,\MSII IDI31
DI,.IDI,I
DIIIDI,I
DIIIDI.I
DI7
DI6
DI.
DI,
'3
D
D
D
D
D
D
D
D
"
"
,
•
'6
I
7
8·BIT
INPUT
LATCH
D
0
0
0
0
•
•
0
0
0
o
0
~tll
01--01--01--12·81Y
DAe
'OUT'
12-8IT
01---
MULTIPLYING
I---
CONVERTER
REGISTER Q
VAEF
I--tll loun
Dr---
D
D
0
I--j!.
0 1 - - - MS8
01---
0
D/A
,-j!..
LE
D
o
or---- D
4·81T
01---
r-- •
D ~:~~~ 0 f - - - 0
BYTE 1/iYffi
•
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17
~I
'L~
r
fl!
f-
Dr--
Q
01---
Dr----
or---- O
LS8
jl!.
Vee
UNO
GNO
LE
E
When
When
::J
LE=I, Qoutputs follow 0 Inputs
LE =0, Q outputs are latched
TL/H/5690-6
FIGURE 2. DAC1230, DAC1231, DAC1232 Functional Diagram
4-94
g
Application Hints (Continued)
o
....
~
1.1 Automatic Transfer
The 12·bit DAC word is automatically transferred to the DAC register and the R·2R ladder when the second write (the 4 LSBs of
the data) occurs.
-':»-----------<<:,____V_A_Ll_D____J:>~--------------
DATABUS-------<:,_____V_A_LI_D____
o
CD
......
g
....o
....o
BYTEI/ffiIT--------------------------------......\
I\)
~__________~~~~~------
......
ANALOG OUTPUT
PDATED
/ }
iO:'=A::N::A":":LD:::G:":D:::U=Tp:::U::'T-\
._
LATCHED
\'--_..-Jf
Wiil AND IYR2
LOAD I·BIT INPUT
LATCH (4-8IT INPUT
LATCH ALSO CHANGED)
~....
I\)
OVERWRITE THE4·BIT
INPUT LATCH AND TRANSFER
ALL IZ BITS TO THE D/A
TLlH/5690-7
1.2 Independent Processor Transfer Control
In this case a separate address is decoded to provide the XFER signal. This allows the processor to load the next required DAC
word but not change the analog output until some time later, most useful for the simultaneous updating of several DACs in a
system where their XFER lines would be tied together.
DATABUS
-------<<:. .____
..J»---------<<:...___
V_A_Ll_D__
g
o
....
I\)
\I.... _ _----Jf
AND~
00
......
.....,>-_------------_____________
V_AL_'D__
w
o
......
C
l!;
....
I\)
....
......
w
~....
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w
I\)
BYTE I/iYffi
1...
\ ..._ _ _ _ _ _..1.
':.:..
===: ===: =
\'--_ _---=.f
Wiil ANDWRZ
ANALOO OUTPUT
UPDATED
ANALOO OUTPUT
LATCHED
.
LOAD 8·IIT INPUT
LATCH (4-BIT INPUT
LATCH ALSO CHANGED)
OVERWRITE 4-81T
INPUTLATCH
TRANSFER 12·8IT DAC
WORD TO THE D/A
TLiH/5690-8
1.3 Transfer via an External Strobe
This method is basically the same as the previous operation except the XFER signal is provided by a device other than the
processor. This allows the DAC to hold the code for a conditional analog output signal which will be required on demand from an
external monitoring device (an analog voltage comparator for instance).
DATA BUS
<
VALID
<
)
VALID
II
:>
Ci
""
Wiil
r-----------
\
'BYTE I/BYTE Z
'---I
LOAD 8·BIT INPUT
LATCH (4-BIT INPUT
LATCH ALSO CHANGED)
...J.------ ____
'---I
.
DVERWRITE 4·IIT
INPUTLATCH
WR2 tied to a logic low (OV)
.
ANALOG OUTPUT UPDATED
AND LATCHED
TLlH/5690-9
4·95
Application Hints (Continued)
1.4 Left-Justified Data Format
It is important to realize that the input registers of these
DACs are arranged to accept a left-justified data word from
the microprocessor with the most significant a bits coming
first (Byte 1) and the lower 4 bits second. Left justification
simply means that the binary point is assumed to be located
to the left of the most significant bit. Figure 3 shows how the
12 bits of DAC data should be arranged in 2 a-bit registers
of an a-bit processor before being written to the DAC.
1.5 16-Blt Data Bus Interface
The DAC120a series provides all 12 digital input lines to
permit a direct parallel interface to a 16-bit data bus. In this
instance, double buffering is not always necessary (unless a
simultaneous updating of several DACs or a data transfer
via an external strobe is desired) so the 12-bit DAC register
can be wired to flow-through whereby its Q outputs always
reflect the state of its D inputs. The external connections
required and the timing diagram for this single buffered application are shown in Figure 4. Note that either left or rightjustified data from the processor can be accommodated
with a 16-bit data bus.
J - H I BVTE-r-LO BVTE--I
'1.6 Flow-Through Operation
Through primarily designed to provide microprocessor interface compatibility, the MICRO-DACs can easily be configured to allow the analog output to continuously reflect the
state of an applied digital input. This is most useful in appli-
I MSB-OACOATAELSB xX xxl
~--~--~"~--~.----~
BYTE 2
BYTE I
x~
TL/H/5690·10
don" care
FIGURE 3. Left-Justified Data Format
Interface Timing
171
181
III
2DI
16·BIT
41
DATA BUS ~----o()-~--I
51
TO
CURRENT
SWITCHES
I
I
OBD
084
81
71
81
0
II
0
VCC
SYSTEM
Wii STROBE
16·BIT
DATA BUS
cs
Wiil
<
VAllO
~
)
I
ANALOG OUTPUT
UPDATED
ANALOG OUTPUT
LATCHED
TUH/5690·11
XFER and WR2 grounded; Byle I/Byle 2 lied 10 Vee.
FIGURE 4. 16-Bit Data Bus Interface for the DAC1208 Series
4-96
Application Hints (Continued)
cations where the DAC is used in a continuous feedback
control loop and is driven by a binary up/down counter, or in
function generation circuits where a ROM is continuously
providing DAC data.
incrementing the address for Byte 2) from propagating
through the address word and changing any of the bits de·
coded for CS or XFER. Figure 5 shows how to prevent this
effect.
Only the DAC120B, DAC1209, DAC1210 devices can have
all 12 inputs flow·through. Simply grounding CS, WR1, WR2
and XFER and tying Byte 1/Byte 2 high allows both internal
registers to follow the applied digital inputs (flow·through)
and directly affect the DAC analog output.
The same problem can occur from a borrow when an auto·
decremented address is used; but only if the processor's
address outputs are inverted before being decoded.
1.8 Control Signal Timing
When interfacing these MICRO·DACs to any microproces·
sor, there are two important time relationships that must be
considered to insure proper operation. The first is the mini·
mum WR strobe pulse width which is specified as 320 ns for
Vee = 11.4V to 15.75V and operation over temperature, but
typically a pulse width of only 250 ns is adequate. A second
consideration is that the guaranteed minimum data hold
time of 90 ns should be met or erroneous data can be
latched. This hold time is defined as the length of time data
must be held valid on the digital inputs after a qualified (via
CS) WR strobe makes a low to high transition to latch the
applied data.
If the controlling device or system does not inherently meet
these timing specs the DAC can be treated as a slow mem·
ory or peripheral and utilize a technique to extend the write
strobe. A simple extension of the write time, by adding a
wait state, can simultaneously hold the write strobe active
and data valid on the bus to satisfy the minimum WR pulse
1.7 Address Decoding Tips
It is possible to map the MICRO·DACs into system ROM
space to allow more efficient use of existing address decod·
ing hardware. The DAC in effect can share the same ad·
dresses of any number of ROM locations. The ROM outputs
will only be enabled by a READ of its address (gated by the
system READ strobe) and the DAC will only accept data
that is written to the same address (gated by the system
WRITE strobe).
The Byte 1/Byte 2 control function can easily be generated
by the processor's least significant address bit (AO) by plac·
ing the DAC at two consecutive address locations and utiliz·
ing double·byte WRITE instructions which automatically in·
crement or decrement the address. The CS and XFER sig.
nals can then be decoded from the remaining address bits.
Care must be taken in selecting the actual address used
for Byte 1 of the DAC to prevent a carry (as a result of
~
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.......
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.......
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o.....
I\)
.....
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.......
~
o
.....
I\)
W
o
.......
C
l:;
.....
I\)
W
.....
c
»
o
.....
.......
I\)
W
I\)
Write
Cycle
Address Bits
First
(Byte 1)
Second
(Byte 2)
15
2
\.
I
T
Decoded to
AddressDAC
l'
0·'
0
1
1
0
·Starting with a 0 prevents a carry on address incrementing.
"Used as Byte l/Byte2 Control.
FIGURE 5
DATA BUS
DNE·
SHOT
ANALOG
OUTPUT
DACI130
V
DATA
BUS---1\.
SYSTEM
WRITE STROBE
OATAVAUD
~
_NORMAL
WRITE STROBE
(250 os)
ONE WAIT
STATE
(250 ns)
_'---+__
SYSTEM OATA HOLD TIME (10 OI)
r
Wii
(OUTPUT OF
ONE.sHon
TL/H/5690·12
FIGURE 6. Accommodating a High Speed System
4·97
Application Hints (Continued)
width. If this does not provide a sufficient data hold time at
the end of the write cycle, a negative edge triggered oneshot can be included between the system write strobe and
the WR pin of the DAC. This is illustrated in Figure 6 for an
exemplary system which provides a 250 ns WR strobe time
with a data hold time of only IOns.
easily accomplished by over-compensating the DAC output
amplifier by increasing the value of its feedback capacitor.
In applications requiring a fast output response from the
DAC and op amp, filtering may not be feasible. In this event,
digital signals can be completely isolated from the DAC
circuitry, by the use of a DM74LS374 latch, until a valid
CS signal is applied to update the DAC. This is shown in
Figure 7.
A single TRI-STATE@ data buffer such as the DM81LS95
can be used to isolate any number of DACs in a system.
Figure 8 shows this isolating circuitry and decoding hardware for a multiple DAC analog output card. Pull-up resistors are used on the buffer outputs to limit the impedance at
the DAC digital inputs when the card is not selected. A
unique feature of this card is that the DAC XFER strobes are
controlled by the data bus. This allows a very flexible update
of any combination of analog outputs via a transfer word
which would contain a zero in the bit position assigned to
any of the DACs required to change to a new output value.
The proper data set-up time prior to the latching edge' (low
to high transition) of the WR strobe, is insured if the WR
pulse width is within spec and the data is valid on the bus for
the duration of the DAC WR strobe.
1.9 Digital Signal Feedthrough
A typical microprocessor is a tremendous potential source
of high frequency noise which can be coupled to sensitive
analog circuitry. The fast edges of the data and address bus
signals generate frequency components of 10's of megahertz and may cause fast transients to appear at the DAC
output, even when data is latched internally.
In low frequency or DC applications, low pass filtering can
reduce the magnitude of any fast transients. This is most
ANALOG
OUTPUT
;:~:::s
DECODER
....++-,. . . v".J....r_
\Vii ~~~~~ ....-+-+-..
Xffii FROM
ADDRESS ......-t--"JL../
DECODER
ADDRESS BIT 0
_-..,0---------..
-i.1-_-_-.J1.:-
H~~~ ~~: :~~~~ ....
TL/H/5690·13
FIGURE 7. Isolating Data Bus from DAC Circuitry to Eliminate Digital Noise Coupling
4-98
g
...
o
Application Hints (Continued)
I\)
o
co
.....
g
...
o
sv
I\)
o
co
.....
D~US
A13
AIZ
B6
BS
T6
84
T4
T3
AID
~G
07
AB
A7
DB
OS
04
AI
AS
03
OZ
Dl
DO
A4
A3
A2
Al
JAD
i
U"
rr+
...-0 GZ
"17
sv
°1
mr
m
2
CSZ
J
CS3
TRANSFER SELEcN
L:~~B~ER
OJ
02
01
Ai
DO
-
A2
Al
GND
5V
~
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p~
Gl
A4
V4
VJ
V2
VI
I
r
81~:1
...
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...~
...
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I DiODO
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101
WRZ
OAC1Z3D
I
I
I
I
g
...
10Z
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Co)
I\)
°too
{
S.lk
0
0
DAC
BUS
0
p4
ps
A
I
~ WAf
~
g
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CSi
XFliI
B1tH
C
8
I B~I: I
Wii
VB
VS
OAC1Z30
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5."
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AJ
A2
Al
XfRlf
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sv
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YB
06
Y7
os
YI
04
VS
03
Y4
OZ
Y3
01
V2
DO
VI
-0
~ Wiif
U"
10.I"F
11/3 OM70L97 BUFFER
AB
AS
o
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fS[
~
DM81LS9SS~
BUFFER
10Z
o
:;
v-
TZ
T1
Bl
~z
101
...........o
-
TS
83
BZ
An
g
BOARD
SELECT
S.,.
DMI131
BUS COMP
AIS
A14
sv
~
~
en
r---< XFR3
r-< WliT
S.1k
_
XFRJ
XFR2
XFRI
r-~""'OVDUT
12
TL/H/5690-15
VOUT ~ -(Ioun x RFt»
~ -VREF(D)
4096
forO:;: 0:;: 4095
FIGURE 9. Unipolar Output Configuration
4-100
c
»
o
Application Hints (Continued)
Transient response and settling time of the op amp are important in fast data throughput applications. The largest stability problem is the feedback pole created by the feedback
resistance, RFb, and the output capacitance of the DAC.
This appears from the op amp output to the (-) input and
includes the stray capacitance at this node. Addition of a
lead capacitance, Cc in Figure 9, greatly reduces overshoot
and ringing at the output for a step change in DAC output
current.
internal feedback resistor, RFb, matches the R-2R ladder
resistors. A negative gain error indicates that RFb is a smaller resistance value than it should be. To adjust this gain
error, some resistance must always be added in series with
RFb. The 50n potentiometer shown is sufficient to adjust
the worst-case gain error for these devices.
2.2 Bipolar Output Voltage from a Fixed Reference
The addition of a second op amp to the unipolar circuit can
generate a bipolar output voltage from a fixed reference
voltage. This, in effect, gives sign significance to the MSB of
the digital input word to allow two quadrant multiplication of
the reference voltage. The polarity of the reference can also
be reversed to realize full 4-quadrant multiplication. This circuit is shown in Figure 10.
2.1.1 Zero and Full-Scale Adjustments
For accurate conversions, the input offset voltage of the
output amplifier must always be nulled. Amplifier offset errors create an overall degradation of DAC linearity.
The fundamental purpose of zeroing is to make the voltage
appearing at the DAC outputs as near 0 VDC as possible.
This is accomplished by shorting out RFb, the amplifier feedback resistor, and adjusting the vas nulling potentiometer of
the op amp until the output reads zero volts. This is done, of
course, with an applied digital code of all zeros if IOUTl is
driving the op amp (all ones for IOUT2l. The short around
RFb is then removed and the converter is zero adjusted.
A unique feature of this series of DACs is that the full-scale
or gain error is guaranteed to be negative. The gain error
specification is a measure of how close the value of the
This configuration features several improvements over existing circuits for a bipolar output shown with other multiplying DACs. Only the offset voltage of amplifier 1 affects the
linearity of the DAC. The offset voltage error of the second
op amp (although a constant output error) has no effect on
linearity. In addition, this configuration offers a non-interactive positive and negative full-scale calibration procedure.
....
N
o
~
g
o
....
N
o
CD
.......
g
o....
....
N
~
....~
N
Co)
o
.......
g
....o
....
.......
N
Co)
g
o
....
N
Co)
N
(+FULL-SCALE
ADJUST)
2R
10k
15V
24
VCC
±VREF
(-FULL-SCALE
ADJUSTI
VOUT
v
-
OUT -
V
REF
(0 - 2048)TLlH/5690.16
2048
forO';; 0,;; 4095
1 LSB
~
IVREFI
2048
Input Code
MSB......LSB
IdealVOUT
+VREF
-VREF
111111111111
VREF -1 LSB
-IVREFI + 1 LSB
-IVREFI/2
110000000000
VREF/2
100000000000
0
0
011111111111
-1 LSB
- VREF _ 1 LSB
2
-VREF
+1 LSB
IVREFI + 1 LSB
2
+IVREFI
001111111111
000000000000
FIGURE 10. Bipolar Output Voltage Configuration
4-101
~
r-------------------------------------------------------------------------~
C")
~
.....
Application Hints (Continued)
......
.....
To calibrate the bipolar output circuit, three adjustments are
required. The first step is to set all of the digital inputs LOW
(to force IOUT1 to 0) then null the Vos of amplifier 1 by
setting the voltage at its inverting input (pin 2) to zero volts.
Next, with a code of all zeros still applied, adjust U -full·
scale adjust", the reference voltage, for VOUT= ±IVREF
ideall. The polarity of the output voltage at this time will be
opposite that of the applied reference. Finally, set all of the
digital inputs HIGH and adjust u+full·scale adjust" for
~
C")
~
.....
o
~
......
o
C")
~
.....
~
2~2.1 Zero and Full-Scale Adjustments
The polarity of the output will be the same as that of the
reference voltage.
3.0 APPLICATION IDEAS
In this section the digital input word is represented by the
letter D and is equal to the decimal equivalent of the 12·bit
binary input. Hence D can be any integer value between 0
and 4095.
2047
Your = VREF 2048·
......
o
.....
.....
~
g
.....
Composite Amplifier for Good DC Characteristics and Fast Output Response
o
15k
11
CD
~
.....
OACIZI1I
~
tlDV
REFERENCE
......
CO
o
lD
• Combines the low vos.
~
.....
':'
D.47.F
low Vos drift and low
o
"'_"""-
DECODER
SYSTEM
WASTHOIE
TL/H/5B90-20
Ordering Information
Part Number
DAC1208LCJ
Temperature
Range
Non-Linearity
Package
0.012%
J24ACerdip
-40"Cto +85·C
O·Cto +70·C
DAC1208LCJ-1
0.012%
J24ACerdip
DAC1209LCJ
0.024%
J24ACerdip
-40·Cto +85·C
DAC1209LCJ-1
0.024%
J24ACerdip
O·Cto +70·C
DAC1210LCJ
0.050%
J24ACerdip
-40·Cto +85·C
DAC1210LCJ-1
0.050%
J24ACerdip
O·Cto +70·C
DAC1230LCJ
0.012%
J20ACerdip
-40·Cto +85·C
DAC1230LCJ-1
0.012%
J20ACerdip
O·Cto +70"C
DAC1231LCJ
0.024%
J20ACerdip
-40·Cto +85·C
DAC1231 LCJ-1
0.024%
J20ACerdip
O·Cto +70·C
DAC1232LCJ
0.050%
J20ACerdip
-40·Cto +85·C
DAC1232LCJ-1
0.050%
J20ACerdip
O·Cto +70·C
4-103
•
.... r----------------------------------------------------------------------------,
.... ~National
CD
N
g ~ Semiconductor
~
....
....N OAC1218/0AC1219
g 12-Bit Binary Multiplying 01 A Converter
General Description
The DAC1218 and the DAC1219 are 12-bit binary, 4-quadrant multiplying D to A converters. The linearity, differential
non-linearity and monotonicity specifications for these converters are all guaranteed over temperature. In addition,
these parameters are specified with standard zero and fullscale adjustment procedures as opposed to the impractical
best fit straight line guarantee.
This level of precision is achieved though the use of an
advanced silicon-chromium (SiCr) R-2R resistor ladder network. This type of thin-film resistor eliminates the parasitic
diode problems associated with diffused resistors and allows the applied reference voltage to range from -25V to
25V, independent of the logic supply voltage.
CMOS current switches and drive circuitry are used to
achieve low power consumption (20 mW typical) and minimize output leakage current errors (10 nA maximum).
Unique digital input circuitry maintains TTL compatible input
threshold voltages over the full operating supply voltage
range.
The DAC1218 and DAC1219 are direct replacements for
the AD7541 series, AD7521 series, and AD7531 series with
a significant improvement in the linearity specification. In
applications where direct interface of the D to A converter to
a microprocessor bus is desirable, the DAC1208 and
DAC1230 series eliminate the need for additional interface
logic.
Features
• Linearity specified with zero and full-scale adjust only
• Logic inputs which meet TTL voltage level specs (1.4V
logic threshold)
• Works with ± 10V reference-full 4-quadrant
multiplication
• All parts guaranteed 12-bit monotonic
Key Specifications
1 ,...S
12 Bits
12 Bits (DAC1218)
11 Bits (DAC1219)
1.5 ppml'C
20mW
5 Voc to 15 Voc
• Current Settling Time
• Resolution
• Linearity (Guaranteed
over temperature)
• Gain Tempco
• Low Power Dissipation
• Single Power Supply
Typical Application
Connection Diagram
DIGITAL
INPUT
Dual-In-Line Package
loun
15V
•
loun
GND
±tOY
ANALDG
OUTPUT
VREF
A1IMSBI
A2
15V
A3
12
04
15V
TL/H/5691-1
VOUT~ -VREF
A9 .
11 AB
AS
lD
A6
01
AI
A2 t>:3
( -+-+-+
... -A12)
2484096
TL/H/5691-15
where: AN
~
I H digital input is high
AN
~
0 if digital input is low
Top View
Ordering Information
Temperature Range
O'Cto +70'C
-40'Cto + 85'C
1 0.012%
Linearity.1 0.024%
DAC1218LCJ-1
DAC1218LCJ
J18ACerdip
DAC1219LCJ-1
DAC1219LCJ
J18ACerdip
Non
4-104
Package Outline
Absolute Maximum Ratings (Notes 1 and 2)
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Temperature Range
DAC1218LCJ,DAC1219LCJ
DAC1218LCJ-1, DAC1219LCJ-1
Supply Voltage (Vee>
Voltage at Any Digital Input
Range of Vee
Voltage at Any Digital Input
17Voe
VeetoGND
±25V
Voltage at VREF Input
Storage Temperature Range
TMIN ,;;: TA';;: TMAX
-40'C';;: TA';;: +85'C
O'C,;;: TA';;: 70'C
5 Voe to 16 Voe
VeetoGND
-65'C to + 150'C
Package Dissipation at TA= 25'C (Note 3)
500mW
-100mVtoVee
DC Voltage Applied to IOUT1 or IOUT2
(Note 4)
Lead Temp. (Soldering. 10 seconds)
ESD Susceptibility (Note 11)
300'C
800V
Electrical Characteristics
VREF = 10.000 Voe, Vee = 11.4 Voe to 15.75 Voe unless otherwise noted. Boldface limits apply from TMIN to TMAX (see
Note 9); all other limits TA = TJ = 25'C.
Parameter
Conditions
Notes
Resolution
Linearity Error
(End Point Linearity)
Differential Non-Linearity
Zero and Full-Scale
Adjusted
DAC1218
DAC1219
4,5,9
Zero and Full-Scale
Adjusted
DAC1218
DAC1219
4,5,9
Monotonicity
Gain Error (Min)
Gain Error (Max)
Using Internal RFb,
VREF = ±10V, ±1V
Gain Error Tempco
Typ
(Note 10)
Tested
Limit
(Note 11)
Design
Limit
(Note 12)
Units
12
12
12
Bits
0.012
0.024
0.012
0.024
% of FSR
% of FSR
0.018
0.024
0.018
0.024
% of FSR
% of FSR
12
12
Bits
4
12
5
-0.1
0.0
5
-0.1
-0.2
5
±1.3
% of FSR
% ofFSR
±6.0
Power Supply Rejection
All Digital Inputs High
5
±3.0
±30
Reference Input Resistance
(Min)
9
15
10
10
(Max)
9
15
20
20
Output Feedthrough Error
VREF=120 Vp-p, f=100 kHz
All Data Inputs Low
6
3.0
Output Capacitance
All Data Inputs
High
All Data Inputs
Low
Output Leakage Current
IOUT1
IOUT2
9
ppm of FSRIV
kn
kn
mVp-p
200
70
70
200
pF
pF
pF
pF
2.0
2.5
mA
10
10
10
10
nA
nA
IOUT1
IOUT2
IOUT1
IOUT2
Supply Current Drain
ppm of FSI'C
7,9
All Data Inputs Low
All Data Inputs High
Digital Input Threshold
Low Threshold
High Threshold
9
0.8
2.2
0.8
2.2
Voe
Voe
Digital Input Currents
Digital Inputs <0.8V
Digital Inputs > 2.2V
9
-200
10
-200
10
,..Aoe
,..Aoe
Is Current Settling Time
RL = 100n, Output Settled
to 0.01 %, All Digital Inputs
Switched Simultaneously
1
4-105
,..s
en
.,...
N
o
~
......
co
.,...
N
.,...
o
'------......-0 VOUT
TlIH/5691-7
FIGURE 4. Composite Output Amplifier Connection
15V
PULSE GENERATOR
INPUT
{QH-....
OV-5V
±1GV
.50
SETTLE
SIGNAL
OUT
(TO SCOPE)
Diodes are 1N4148
...
-15V o---4~~_--
-15V
TlIH/5691-B
FIGURE 5. CAC Settling Time Test Circuit
Amplifier
Cc
Settling Time to 0.01 %
LM11
LF351
LF351
Composite
LM11-LF351
LF356
20pF
15 pF
30pF
30,",s
8,",s
5,",s
20pF
8,",s
15pF
6,",s
FIGURE 6. Some Measured Settling Times
4-110
Application Hints (Continued)
where D is the decimal equivalent of the true binary input
word. This configuration inherently accepts a code (halfscale or D = 2048) to provide OV out without requiring an
external % LSB offset as needed by other bipolar multiplying DAC circuits.
Only the offset voltage of amplifier A 1 need be nulled to
preserve linearity. The gain setting resistors around A2 must
match and track each other. A thin film, 4-resistor network
available from Beckman Instruments, Inc. (part no. 694-3R10K-D) is ideally suited for this application. Two of the four
resistors can be paralleled to form R and the other two can
be used separately as the resistors labeled 2R.
Operation is summarized in the table below:
3.0 OBTAINING A BIPOLAR OUTPUT VOLTAGE
FROM A FIXED REFERENCE
The addition of a second op amp to the circuit of Figure 2
can generate a bipolar output voltage from a fixed reference
voltage (Figure 7). This, in effect gives sign significance to
the MSB of the digital input word to allow two quadrant mul·
tiplication of the reference voltage. The polarity of the refer·
ence voltage can also be reversed to realize full 4-quadrant
multiplication.
The output responds in accordance to the following expression:
D - 2048)
Vo = VREF ( 2048
,0 ,;: D ,;: 4095
Applied
Digital Input
MSB
LSB
1
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
1
0
0
1
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
Decimal
Equivalent
+VREF
-VREF
4095
3072
2048
2047
1024
0
VREF-1 LSB
VREF/2
0
-1 LSB
-VREF/2
-VREF
- VREFI + 1 LSB
-IVREFI/2
0
+1 LSB
+IVREFI/2
+IVREFI
VOUT
Where 1 LSB = IVREFI
2048
-FULL-SCALE
ADJUST
R,Sk
2R'
ISV
16
2R'
10k
2R'
tVREF
-FULL-SCALE
ADJUST
21k
ZERO
ADJUST
lR'
10k
'0.1 % malching
TUH/5691-9
FIGURE 7. Obtaining a Bipolar Output from a Fixed Reference
4-111
~.....
I\)
.....
co
.....
~.....
.....
I\)
CD
.,..
G)
N
.,..
~
C
.....
co
.,..
.,..
N
~
C
Application Hints (Continued)
3.1 Zero and Full-Scale Adjustments
4.0 MISCELLANEOUS APPLICATION HINTS
The devices are CMOS products and reasonable care
should be exercised in handling them to prevent catastrophic failures due to electrostatic discharge.
During power-up supply voltage sequencing, the negative
supply of the output amplifier may appear first. This will typically cause the output of the op amp to bias near the negative supply potential. No harm is done to the DAC, however,
as the on-chip 15 kfi feedback resistor sufficiently limits the
current flow from IOUT1 when this lead is clamped to one
diode drop below ground.
As a general rule, any unused digital inputs should be tied
high or low as required by the application. As a troubleshooting aid, if any digital input is left floating, the DAC will
interpret that input as a logical 1 level.
The three adjustments needed for this circuit are shown in
Figure 7. The first step is to set all of the digital inputs LOW
(to force IOUT1 to 0) and then trim "zero adjust" for zero
volts at the inverting input (pin 2) of OA 1. Next, with a code
of all zeros still applied, adjust "- full-scale adjust", the reference voltage, for VOUT = ± I(ideal VREF)I. The sign of the
output voltage will be opposite that of the applied reference.
Finally, set all of the digital inputs HIGH and adjust" + fullscale adjust" for VOUT=VREF (511/512). The sign of the
output at this time will be the same as that of the reference
voltage. This + full-scale adjustment scheme takes into account the effects of the Vos of amplifier A2 (as long as this
offset is less than 0.1 % of VREF) and any gain errors due to
external resistor mismatch.
Additional Application Ideas
For the circuits shown, D represents the decimal equivalent of the binary digital input code. D ranges from 0 (for an all zeros
input code) to 4095 (for an all ones input code) and for any code can be determined from:
o=
2048(A1) + 1024(A2) + 512(A2) + ... 2(A11)
where AN = 1 if that input is high
AN = 0 if that input is low
+
1(A12)
DAC Controlled Amplifier
VIN
Vee
18
IIV
DAelZI8
VREF
GND
17
510
'::'
I&V
0.1 pF
>_....0
VOUT" -VIN(4098)
o
TL/H/5691-10
4-112
g
Additional Application Ideas (Continued)
(")
.....
I\)
.....
~
C
Offsetting the Zero Code Output Voltage
~
.....
.....
I\)
CD
15V
16 VCC
DAC1211
+VREF
17 VREF
">~-OVDUT
GND
R2
2VREFR2
VZoroShift = Rl + R2
TL/H/5691-11
High Current Controller
5V-+5DV
o
IDUT2;'i~--",~
16V
DAC121.
-=.t
IDUT1~::;"'_ _ _
-lV
REFERENCE
1.
I
I
~
I
I
I
L __ _
_ 1 Amp (D)
0-
4096
TLlH/5691-12
4-113
G)
.,...
C'I
.,...
g
.....
Additional Application Ideas (Continued)
CD
.,...
C'I
.,...
g
DAC Controlled Function Generator
15V
o Cl controls maximum frequency
• <0.5% sine wave THO over range
• Range 30 kHz maximum
o Llnearity-DAC limit
0
of=
I&V
4096 (4/3 RFb C)
~10VPK
r--""',..,.----'\I\i'll-........--...-o t7V
.sL
snUAAE OUT
IIV
DACU1'
TLIHI5691-13
Digitally Programmable Pulse-Width Generator
SV-r1
av
.....J L
10
11
INITIALIZING
STROBEo-....
INPUT
2.7•
-----'\oI\!\,-----.....,
u.
IIV
IB
o_elZll
TTL OUTPUT
PULSE
- llVoe
_1""1_
m-'-'-lii-'
-+--f u!..I n n ~ :
ttl
t~
MIN
MAX
TUH15691-14
pw .. C(7.5V) (4096) (RFbl
OIVREF
4-114
~
o
......
~National
~ Semiconductor
DAC1265A/DAC1265 Hi-Speed 12-Bit D/A Converter
with Reference
N
General Description
Features
Q)
(II
The DAC1265A and DAC1265 are fast 12-bit digital to analog converters with internal voltage reference. These DACs
use 12 precision high speed bipolar current steering
switches, control amplifier, thin film resistor network, and
buried zener voltage reference to obtain a high accuracy,
very fast analog output current. The DAC1265A and
DAC1265 have 10%-90% full-scale transition time under
35 ns and settle to less than % LSB in 200 ns. The buried
zener reference has long-term stability and temperature drift
characteristics comparable to the best discrete or separate
IC references.
These digital to analog converters are recommended for
applications in CRT displays, precision instruments and data
acquisition systems requiring throughput rates as high as 5
MHz for full range transitions.
II Bipolar current output DAC and voltage reference
.. Fully differential, non-saturating precision current switch
- ROUT and COUT do not change with digital input
code.
II Internal buried zener reference - 1OV ± 1 % max
II Precision thin film resistors for use with external op
amp for voltage out or as input resistors for a successive approximation AID converter
II Superior replacement for 12-bit DI A converters of this
type
Q)
(II
»
~
o
.......
......
N
Key Specifications
Resolution and Monotonicity
12 Bits
II Linearity
12 Bits
(Guaranteed over temperature)
.. Output Current Settling Time
400 ns max to 0.01 %
II Gain Tempco
± 15 ppml'C max
II Power Supply Sensitivity
± 10 ppm of FS/% VSUPPLY
II
Block and Connection Diagrams
... R
+Vs GND
REFERENCE 4
OUT
'1
IO.OV
IlEFERENCE
NC
NC
-Vs
Z
1
o
o
1
1D
. . - - - - - - 0 0 IOV RANGE
20V RANGE
-+-+. . 'V·SI/'5kIr"1p-_=~
REFE~~;~~ 6'_ _
ANA~~~ O'---4IO+-'I/'''l/'k'--I
9 CURRENT OUTPUT
(SUMMING JUNCTION)
t------7--O
+ _____+'
c
BIPOLAR 8..-_ _-+-'II.I\i.""'k_ _ _ _
OFFSET
24 23 22 21 20 19 18 17 16 15 14 13
(LSBI
Tl/H/5242-1
(MSlJi
Dual-In-Line Package
NC
1
24
(~SB)BIT 1
NC
2
23
BIT2
+Vs
3
22
BIT 3
10.0 Vm OUT
4
21
BIT 4
ANAlOGGND
5
20
BITS
REF INPUT
19
BIT 6
-Vs
18
BlTl
BIPOLAR OfFSET
17
BIT8
'OUT(-2mAFS)
16
BIT 9
10VRANGE
10
15
BIT 10
20VRANGE
11
14
BIT 11
POWERGND
12
13
(lSB) BIT 12
Order Number DAC1265AJ,
DAC1265ACJ, DAC1265LJ or
DAC1265LCJ
See NS Package Number J24A
Tl/H/5242-2
Top View
4-115
It)
CD
....
Absolute Maximum Ratings
: TA :>: T MAX. For all other limits TA = 25'C.
DAC1265
DAC1265A
Parameter
Current Output
Conditions
See
Note
Unipolar
Bipolar
Tested Design
Tested Design
Typ
Typ
Limit
Limit
Limit
Limit
(Note 11) (Note 2) (Note 3) (Note 11) (Note 2) (Note 3)
-2
-1.6to
-2.4
-2
-1.6 to
-2.4
±1.0
±0.8to
±1.2
±1.0
±0.8to
±1.2
Units
rnA
Output
Capacitance
25
25
pF
Output Noise (FS, 10Hz to 100 kHz with Internal
10V Range)
Reference
40
40
,...Vrms
TypOutput
Voltage Ranges
Using Internal Offset and Range Rs
±2.5, ±5, ±10,Ot05,Ot010
Reference Input
Resistance
20.8
15 to 25
Output
Compliance
Voltage
V
20.8
15t025
kO
-1.5 to
10
-1.5 to
10
V
REFERENCE OUTPUT CHARACTERISTICS
Reference
Voltage
Temperature
Coefficient
~
IREF=1.5mA
10.00
Max
10.00
±12
3.0
fo=1 kHz, 0.5 mA:>:IREF:>:3 rnA
0.05
V
9.90
10.10
±8
Reference
Output Current
Min
Output
Resistance Max
9.90
10.10
1.0
0.05
ppml"C
3.0
rnA
1.0
0
DIGITAL AND DC CHARACTERISTICS
Logic High
Bit ON
AJ and LJ Suffix
ACJ and LCJ Suffix
Low
IMax Logic
Bit OFF
AJ and LJ Suffix
ACJ and LCJ Suffix
Logic High
AJ and LJ Suffix
ACJ and LCJ Suffix
150
150
300
280
AJ and LJ Suffix
ACJ and LCJ Suffix
45
45
100
90
Logic Input
Voltage
Logic Input
Current Max
Logic Low
Power Supplyll +
Current Max
11_
Power
Dissipation Max
Power Supply
Sensitivity Max
2 to 5.5
1.9 to 5.5 2t05.5
0.8
1.0
V+ Supply=15V±10%
2t05.5
1.9 to 5.5 2to 5.5
0.8
1.0
0.8
300
150
150
300
280
300
100
45
45
100
90
100
0.8
V
,...A
3
5
3
5
V- Supply = -15V±10%
-12
-18
-12
-18
rnA
VSUPPLY= ± 15V
225
345
225
345
mW
V+Supply= 15V± 10%
10
±3
±10
±3
±10
ppmofFSI
V- Supply= -15V±10%
10
±15
±25
±15
±25
% VSUPPLY
4·117
Electrical Characteristics (Continued) VSUPPLY= ± 15V ± 5% unless otherwise noted. Boldface limits apply
over temperature, TMIN,;;TA,;;TMAX. For all other limits TA= 25°C.
DAC1265A
Units
200
400
ns
15
30
ns
90% to 10% Fall Time
30
50
30
Plus Delay Time
Nole 1: The typical 8JA of the 24-pin package is 80' C/W.
Nole 2: Tested and guaranteed to National's AOOL (Average Outgoing Quality Level).
Note 3: Guaranteed, but not 100% production tested. These IimHs are not used to calculate outgoing quality levels.
50
Conditions
Design
Limit
(Note 3)
Typ
(Note 11)
200
400
15
30
Typ
(Note 11)
Tested
Limit
(Note 2)
DAC1265
Design
Limit
(Note 3)
Parameter
See
Note
Tested
Limit
(Note 2)
AC CHARACTERISTICS
Settling
Time Max
FSRChange
Full-Scale
Transition Max
10% to 90% Rise Time
Plus Delay Time
Note 4: Unearity error VOUT-VOFFSET-(D x VLSel where VLSB VFS - VOFFSET and Dis the digital input (0 to 4095) which produced Your.
VLSB
4095
.
(VFS-VOFFSET)-(4095/4096)10V
Nole 5: Percent gain error for 10V range
10V
x 100.
Note 6: Unipolar offset error for 10V range~(VourI10V)x 100 in percent 01 full-scale.
Note 7: Bipolar offset error lor 10V range VOUTt~~-5V) x I 00 in percent 01 full-scale.
Note 8: Bipolar zero error for 10V range~(Vour/IOV)xIOO In percent of full-scale.
Note 9: Gain error tempco (VFS - VOFFSET)at (TMAX or TMIN) - (VFS - VOFFSET) at 25'C XI OS In ppml"C.
10V range x (TMAX or TMIN - 25'C)
Nole 10: Power supply sensitivity lor 10V range ~ 106 X (VFS - VOFFSET) al (16.5V or -I ~.~~: ~~~ - VOFFSET) at (13.5V or -16.5V) in ppm of FS/% Vs.
The opposite supply is held at -15V or + 15V respectively.
Nole 11: Typicals are at 25"C and represent most likely parametric norm.
Nole 12: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when
operating the device beyond its specified operating conditions.
Note 13: Human body model, 100 pF discharged through a 1.5 kll resistor.
Functional Description and
Applications
1.0 BUFFERED VOLTAGE OUTPUT CONNECTION
The standard current-to-voltage conversion connections using an operational amplifier are shown here with the preferred trimming techniques. If a low offset operational amplifier (LF401A) is used, excellent performance can be obtained in many situations without trimming (an op amp with
less than 0.5 mV maximum offset voltage should be used to
keep offset errors below % LSB). Unipolar zero will typically
be within ± % LSB (plus op amp offset), and if a 500. fixed
resistor is substituted for the 1000. trimmer (R2, Figure 1),
full-scale accuracy will be within 0.1 % (0.20% maximum).
Substituting a 500. resistor for the 1000. bipolar offset trimmer (R1, Figure 2) will give a bipolar zero error typically
within ±2 LSB (0.05%).
Step 2-Gain Adjust
Turn all bits ON and adjust 1000. gain trimmer, R2, until the
output is 9.9976V (full-scale adjusted to 1 LSB less than
nominal full-scale of 10.000V). If a 10.2375V full-scale is
desired (exactly 2.5 mV fbit), insert a 1200. resistor in series
with the gain resistor at pin 10 to the op amp output.
1.2 Bipolar Configuration (Figure 2)
This configuration will provide a bipolar output voltage from
- 5.000V to 4.9976V, with positive full-scale occurring with
all bits ON (aIl1s).
Step 1--offset Adjust
Turn OFF all bits. Adjust 1000. offset trimmer, R1, to give
- 5.000V output.
Step 2-Galn Adjust
Turn ON all bits. Adjust 1000. gain trimmer, R2, to give a
reading of 4.9976V.
Please note that it is not necessary to trim the op amp to
obtain full accuracy at room temperature. In most bipolar
situations, an op amp trim is unnecessary unless the untrimmed offset drift of the op amp is excessive. Bipolar zero
error (MSB bit ON) is not adjusted separately and is typically
< ±0.05% of FS after offset and gain adjust.
1.1 Unipolar Configuration (Figure 1)
This configuration will provide a unipolar OV to 9.9976V output range.
step 1-otfset Adjust (Zero)
Turn all bits OFF and adjust zero trimmer, R1, until the output reads O.OOOV (1 LSB = 2.44 mY). In most cases this trim
is not needed.
4-118
Functional Description and Applications (Continued)
ISV
100
ISV
-ISV
+Vs
r - - - - - Q R E F OUT
BIPOLAR OFF
4
20V RANGE
R2
100
OAe12&5A
OAe12&5
5k
1.9Sk
10
10V RANGE
10 pF
OUTPUT
IV TO 10V
·Power and analog ground must have a
common current return path. See section 4.0 for proper connections.
TUH/5242-3
FIGURE 1. OV to 10V Unipolar Voltage Output
15V
+Vs
Rl
IUD
BIPOLAR OFF
11
RZ
100
OAe1215A
OAelZ15
mv RANGE
5k
U5k
10
lU5k
5k
DAC
OUTPUT
-5VTO 5V
4----
10
Ik
-VS
-15V
M S B - - - - - - - - - - ; - LSB
·Power and analog ground must have a
common current return path. See section 4.0 for proper conneetions.
TUH/5242-5
FIGURE 2. ± 5V Bipolar Voltage Output
4-119
Functional Description and Applications (Continued)
1.3 Other Voltage Ranges (Figure 3)
3.0 DIGITAL INPUT
The DAC1265A and DAC1265 can also be easily configured
for a unipolar OV to 5V range or ± 2.5V and ± 1OV bipolar
ranges by using the additional 5k application resistor provided at the 20V range R terminal, pin 11. For a 5V range (OV
to 5V or ± 2.5V), the two 5k resistors are used in parallel by
shorting pin 11 to pin 9 and connecting pin 10 to the op amp
output and the bipolar offset either left open for unipolar or
connected through a 1000 pot to the REF OUT for the bipolar range. For the ± 10V range use the 5k resistors in series
by connecting only pin 11 to the op amp output and connecting the bipolar offset as shown. The ± 10V option is
shown in Figure 3.
The DAC1265A and DAC1265 use a standard positive true
straight binary code for unipolar outputs (all 1s give fullscale output), and an offset binary code for bipolar output
ranges. In the bipolar mode, with all Os on the inputs, the
output will go to negative full-scale; with 100... 00 (only the
MSB on), the output will be O.OOV; with all 1s, the output will
go to positive full-scale.
The threshold of the digital input circuitry is set at 1.4V and
does not vary with supply voltage. The input lines can interface with any type of 5V logie, TTL/DTL or CMOS, and have
sufficiently low input currents to interface easily with unbuffered CMOS logic. The configuration of the input circuit is
shown in Figure 4. The input line can be modeled as a 30
kO resistance connected to a -0.7V rail.
2.0 INTERNAL/EXTERNAL REFERENCE USE
The performance of the DAC1265A and DAC1265 is specified with the internal reference driving the DAC since all
trimming and testing (especially for full-scale error and bipolar operation) is done in this configuration.
DIGITAL
INPUTS
(PINS 13 TD 24)
T.
The internal reference has sufficient buffering to drive external circuitry in addition to the reference currents required for
the DAC (typically 0.5 rnA to REF IN and 1.0 rnA to BIPOLAR OFFSET, if used). A minimum of 1.5 rnA is available for
driving external circuits. The reference is typically trimmed
to ± 0.2%, then tested and guaranteed to ± 1.0% maximum
error. The temperature coefficient is comparable to that of
the full-scale TC for a particular grade.
_
-
5pF
PDWER
GRDUND
3Dk
a---.--UV
TD LDGIC
TUH/5242-6
FIGURE 4. Equivalent Digital Input Circuit
OAC
-
.t
ID
DUTPUT
-10V TO 10V
lOUT· 4 Jt IREf • CODE
CODE INPUT
PWRGND' 12
-VS
-l1V
24
13
MSI-------_
.. LSI
·Power and analog ground must have a
common cU,rrent return path. See sec-
tion 4.0 for proper connections.
TL/H/5242-4
FIGURE 3. ± 10V Voltage Output
4-120
o
Functional Description and Applications
4.0 APPLICATION OF ANALOG AND POWER GROUNDS
The DAC1265A and DAC1265 have separate analog and
power ground pins to allow optimum connections for low
noise and high speed performance. The two ground lines
can be separated by up to 200 mV without any loss in per·
formance. There may be some loss in linearity beyond that
level. If these DACs are to be used in a system in which the
two grounds will be ultimately connected at some distance
from the device, it is recommended that parallel back·to·
back diodes be connected between the ground lines near
the device to prevent a fault condition.
(Continued)
tion or breakdown which results in non·linear performance.
Compliance limits are not affected by the positive power
supply, but are a function of output current and negative
supply.
6.0 DIRECT UNBUFFERED VOLTAGE OUTPUT FOR CA·
BLEDRIVING
The wide compliance range allows direct current-to-voltage
conversion with just an output resistor. Figure 5 shows a
connection using the gain and bipolar output resistors to
give a ± 1.60V bipolar swing. In this situation, the digital
code is complementary binary. Other combinations of internal and external output resistors (Rx) can be used to scale
to alternate voltage ranges, simply by appropriately scaling
the 0 mA to -2 mA unipolar output current and using the
1O.OV reference voltage for bipolar offset. For example, set·
ting Rx = 2.67 kn gives a ± 1V range with a 1 kn equivalent
output impedance.
The analog ground at pin 5 is the ground reference point for
the internal reference and is thus the "high quality" ground;
it should be connected directly to the analog reference point
of the system. The power ground at pin 12 can be connect·
ed to the most convenient ground reference point; analog
power return is preferred, but digital ground is acceptable. If
power ground contains high frequency noise beyond 200
mY, this noise may feed through the converter, so that
some caution will be required in applying these grounds.
This connection is especially useful for directly driving a
long cable at high speed. Using a 50n resistor for Rx would
allow interface to a 50n cable with a ± 50 mV full·scale
swing.
5.0 OUTPUT VOLTAGE COMPLIANCE
7.0 HIGH SPEED 12·BIT AID CONVERTERS
The DAC1265A and DAC1265 have a typical output compli·
ance range from -2V to 10V. The current·steering output
stages will be unaffected by changes in the output terminal
voltage over that range. However, there is an equivalent
output impedance of 8k in parallel with 25 pF at the output
terminal which produces an equivalent error current if the
voltage deviates from power ground. This is a linear effect
that does not change with input code. Operation beyond the
compliance limits may cause either output stage satura-
The fast settling characteristics of the DAC1265A and
DAC1265 make them ideal for high speed successive ap·
proximation AID converters. The internal reference and
trimmed internal resistors allow a 12·bit converter system to
be constructed with a minimum parts count. Shown in Figure 6 is a configuration using standard components; this
system completes a full 12·bit conversion in 10 J.Ls unipolar
or bipolar. This converter will be accurate to ± % LSB of 12
bits and have a typical gain TC of 10 ppmrC.
50
+vs
BIPOLAR OFF
11
20V RANGE
100
OAC1265A
DAC1265
5k
9.95k
10
10V RANGE
19.95k
':"
5k
OAC
-
OAe OUT
'0
8k
RX
lOUT'" 4 x 'REF x CODE
CODE INPUT
12
24
PWR GNO
-Vs
M S B - - - - - - -....-
lS8
TL/H/5242-7
FIGURE 5. Unbuffered Bipolar Voltage Output
4·121
»o
.....
N
C»
U1
»
.......
o
»
o
.....
N
C»
U1
~
re
,...
,---------------------------------------------------------------,
g
~CD
N
,...
g
Functional Description and Applications (Continued)
In the unipolar mode, the system range is OV to 9.9976V,
with each bit having a value of 2.44 mV. For true conversion
accuracy, an AID converter should be trimmed so that a
given output code results from input levels from % LSB below to % LSB above the exact voltage represented by that
code. Therefore, the converter zero point should be
trimmed with an input voltage of 1.22 mV; trim R1 until the
LSB just begins to appear in the output code (all other bits
"0"). For full-scale, use an input voltage of 9.9963V (10V-1
LSB-% LSB); then trim R2 until the LSB just begins to appear (all other bits "1").
the pretrimmed internal resistors are sufficiently accurate
that external trimmers will be unnecessary, especially in situations requiring less than full 12-bit ± % LSB accuracy.
For fastest operation, the impedance at the comparator
summing node must be minimized. However, lowering the'
impedance will reduce the voltage signal to the comparator
(at an equivalent impedance at the summing node of 1 kG,
1 LSB = 0.5 mV), to the point that comparator performance
will be sacrificed. The contribution to this impedance from
the DAC will vary with the input configuration (Figure 6, Input
Ranges Table).
The bipolar signal range is -5.0V to 4.9976V. Bipolar offset
trimming is done by applying a -4.9988V input signal and
trimming R3 for the LSB transition (all other bits "0").
Full-scale is set by applying 4.9963V and trimming R2 for
the LSB transition (all other bits "1 "). In many applications,
To prevent dynamic errors, the input signal should have a
low dynamic source impedance, such as that ofthe LF411 A
op amp.
15V
1~~
BIPOLAR UNIPOLAR
~------~~~----~
lOOk
HI (UNIPOLAR)
500
100
-15V
BIPQlAROFF
....--f-::11ZOV:9=:RA::N'::GE:-----o: } ANALOG INPUTS
RZ
100
9,950
5V
DAC
lOUT· 4 x IREF x CODE
~-+-4~--4--+~~
CODE INPUT
'2
24
•
MSB
LSB
13
POWER OND
-VS
1!f1
DIG OUT 12
USB
_....:L;::SB:..+.:++-HH±:+-+-H....
21
II I
mlVmw--~OI
SERIAL OUT --~"1
11
DM25D4 SAR
14
DATA 1ft
mmT
CLOCK
TL/H/5242-8
INPUT RANGES
Equlv.
Unipolar
0105
Bipolar
±2.5
010 10
01020
±5
±IO
FIGURE 6. Fast Precision Analog to Digital Converter
4-122
Connect
Input 10 A
BIoDACOUT
Input 10 A
InpulloB
DACZoUT
1.60kO
2.35kO
3.D8kO
Definition of Terms
Digital Inputs: The OAC1265A and OAC1265 accept digital
input codes in binary format and may be user connected for
anyone of three binary codes: straight binary, two's complement, or offset binary.
Digital
Input
MSB LSB
Analog Output
Straight
Binary
Offset
Binary
000 .. 000
zero
- FS (Full-Scale)
011 ... 111 %FS-1LSB
zero-1 LSB
zero
100 .. 000
%FS
111 ... 111 + FS-1 LSB
+FS-1 LSB
Two's
Complement'
zero
+FS-1 LSB
-FS
zero-1 LSB
'Invert MSB with external inverter to obtain Two's Complement coding
Linearity Error: Linearity error of a 01 A converter is an
important measure of its accuracy. It describes the deviation
from an ideal straight line transfer curve drawn between
zero (all bits OFF) and full-scale (all bits ON).
Differential Non-Linearity: For a 01 A converter, it is the
difference between the actual output voltage change and
the ideal (1 LSB) voltage change for a one-bit change in
code. A differential non-linearity of ± 1 LSB or less guarantees monotonicity; i.e., the output always increases and never decreases for an increasing input. It is guaranteed by
testing the major carry transitions, i.e., 100...000 to
011 ... 111, etc.
Settling Time: Settling time is the time required for the output to settle to within the specified error band for any input
code transition. It is usually specified for a full-scale or major
carry transition.
Gain Tempco: The change in full-scale analog output over
the specified temperature range expressed in parts per million of full-scale per °C (ppm of FSI"C). Gain error is measured with respect to 25°C at high (TMAXI and low (TMIN)
temperatures. Gain tempco is calculated for both high
(TMAX - 25°C) and low (25·C - TMIN) ranges by dividing the
gain error by the respective change in temperature. The
specification is the larger of the two representing worstcase drift.
Offset Tempco: The change in analog output with all bits
OFF over the specified temperature range expressed in
parts per million of full-scale per ·C (ppm of FSI"C). Offset
error is measured with respect to 25°C at high (TMAXI and
low (TMIN) temperatures. Offset tempco is calculated for
both high (TMAX-25°C) and low (25·C-TMIN) ranges by
dividing the offset error by the respective change in temperature. The specification given is the larger of the two, representing worst-case drift.
Power Supply Sensitivity: Power supply sensitivity is a
measure of the change in gain and offset of the 01 A converter resulting from a change in -15V or + 15V supplies.
It is specified under OC conditions and expressed as parts
per million of full-scale per percent of change in power supply (ppm of FS/%).
Ordering Information
Temperature Range
Linearity Error
Over Temperature
DoC to 70"C
-55°C to + 125°C
±% Bit
OAC1265ACJ
OAC1265AJ
f--±-3:':Y4:""B-it--I--0-A-C-1-2-65-L-CJ--+--0-A-C-1-2-6-5-LJ---i
4-123
U)
U)
r----------------------------------------------------------------------------,
C'I
..-
g ~National
~ Semiconductor
~ DAC1266A/DAC1266 Hi-Speed 12-Bit D/A Converter
U)
C'I
General Description
..-
g
The DAC1266A and DAC1266 are fast 12-bit digital to analog converters. These DACs use 12 precision high speed
bipolar current steering switches, control amplifier, and a
thin film resistor network to obtain a high accuracy, very fast
analog output current. The DAC1266A and DAC1266 have
10%-90% full-scale transition time under 30 ns and settle
to less than 112 LSB in 200 ns.
These digital to analog converters are recommended for
applications in CRT displays, precision instruments and data
acquisition systems requiring throughput rates as high as 5
MHz for full range transitions.
Features
• Bipolar current output DAC
• Fully differential, non-saturating precision current switch
- ROUT and COUT do not change with digital input
code
• Precision thin film resistors for use with external op
amp for voltage out or as input resistors for a successive approximate AID converter
• Superior replacement for 12-bit DI A converters of this
type
Key Specifications
• Resolution and Monotonicity
12 Bits
• Linearity
12 Bits
(Guaranteed over temperature)
• Output Current Settling Time
400 ns max to 0.01 %
30 ns
• Full-Scale Transition Time (10%-90%)
• Power Supply Sensitivity ±15 ppm of FS/% VSUPPLY
Block and Connection Diagrams
O--~::::~--~--__~----------~r_------~l~O 10V RANGE
11
20V RANGE
CURRENT OUll'UT
...----------~-o9 (SUMMING
JUNCTION)
2423222120191817161413
(MSB)
(LSB)
TUH/506B-7
Dual-In-Llne Package
NC
1
24
NC
2
23
(MSB)BlTl
BIT 2
22
BIT3
BIT 4
ANALOG GROUND
AIIP SUMI.IING
JUNCTION
REFERENCE IN
4
21
5
20
BITS
-Vs
6
19
BIT6
BIPOLAR OFFSET
18
BIT1
NC
17
BITS
lour (-2 mA FS)
16
BIT9
10V RANGE
15
BIT 10
20V RANGE
14
BIT 11
POWER GROUND
13
(LSB) BIT 12
Order Number
DAC1266AJ, DAC1266ACJ,
DAC1266LJ or DAC1266LCJ
See NS Package Number J24A
TL/H/508B-l
Top View
4-124
Absolute Maximum Ratings
(Note11)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V-)
OVto -18V
Current Output (Pin 9) Voltage
Logic Input Voltage
-3V,12V
-1V,7V
Reference Input Voltage (Pin 5)
Analog GND to Power GND
±12V
±1V
Bipolar Offset
10VRange
±12V
±12V
V- to +24V
20VRange
Power Dissipation (Note 1)
1000 mW
Operating Temperature Range
DAC1266AJ, DAC1266LJ
TMINS:TAS:TMAX
-55'Cto + 125'C
DAC1266ACJ,DAC1266LCJ
Storage Temperature Range
Maximum Junction Temperature
O'Cto +70·C
- 65'C to + 150'C
150'C
300'C
Lead Temp. (Soldering, 10 sec.)
ESD Susceptibility (Note 12)
TBD
Electrical Characteristics VSUPPLY= -15V ± 5% and VREF= 1O.OOOV unless otherwise noted. Boldface limits apply over temperature, T MIN s: TA S:TMAX. For all other limits TA = 25'C.
DAC1266A
Parameter
Conditions
See
Note
Typ
DAC1266
Tested Design
Limit
Limit
(Note 2) (Note 3)
Typ
Tested Design
Limit
Limit
(Note 2) (Note 3)
Units
CONVERTER CHARACTERISTICS
Resolution
12
Linearity Error
Max
Zero and Full-Scale Adjusted
LSB
±Ys
±%
±Y:,
±%
±%
AJ and LJ Suffix Parts
ACJ and LCJ Suffix Parts
Differential
Non-Linearity
Max
Zero and Full-Scale Adjusted
Monotonicity
AJ and LJ Suffix Parts
ACJ and LCJ Suffix Parts
Full-Scale
(Gain) Error
Max
R2 = 500 in Figure 1
Offset Error Max
All Bits OFF,
Logic "0"
Bits
12
4
±%
±%
±%
±%
±%
±Y:,
±%
12
12
12
12
12
5
±0.1
±0.20
±0.1
±0.20
Unipolar (Figure 1 Pin 7 Open)
6
±0.01
±0.05
±0.01
±0.05
Bipolar (R1 and R2 = 500 in
Figure2j
7
±0.05
±0.1
±0.05
±0.15
Zero Error Max
MSBON
Bipolar (R1 and R2= 500 in
Figure2j
B
±0.05
±0.1
±0.05
±0.15
Gain
Adjustment
Range Min
R2=500±500 in Figure 1
±0.2
±0.2
Bipolar Offset
Adjustment
Range Min
R1 =500±500 and R2=500 in
Figure 2
±0.15
±0.15
Full-Scale (Gain)
Temperature
Coefficients Max
AJ and LJ Suffix
ACJ and LCJ Suffix
Unipolar Offset
Temperature
Coefficients Max
Bits
12
% FullScale
"--
1
1
3
AJ and LJ Suffix
ACJ and LCJ Suffix
1
1
2
Bipolar Zero
Temperature
Coefficients Max
AJ and LJ Suffix
ACJ and LCJ Suffix
5
5
10
Output
Resistance
Exclusive of Offset and Range Rs
7.5
Current Output
Unipolar
Bipolar
9
ppml'C
5
5
10
3
1
1
2
2
5
5
10
10
6to 10
7.5
6to 10
kO
-2
-1.6 to
-2.4
-2
-1.6to
-2.4
mA
±1.0
±O.Bto
±1.2
±1.0
±0.8to
±1.2
4-125
10
2
10
~....
N
CD
;
"C
....~
N
CD
CD
Electrical Characteristics (Continued) VSUPPLY= -15V ± 5% and VREF= 10.000V unless otherwise noted.
Boldface limits apply over temperature, TMIN,;;TA,;;TMAX. For all other limits TA = 25·C.
DAC1266A
Parameter
Conditions
See
Note Typ
Output
Capacitance
DAC1266
Tested Design
Tested Design
Limit Typ
Limit
Limit
Limit
(Note 2) (Note 3)
(Note 2) (Note 3)
25
Using Internal Offset and Range RS
TypOutput
Voltage Ranges
Reference Input
Resistance
Units
25
pF
±2.5, ±5, ± 10, 0 to 5, 0 to 10
V
20.8 15 to 25
kO
20.8 15t025
-1.510
10
-1.510
10
2105.5
2to5.5
1.9 to 5.5 2105.5
1.9to 5.5 2105.5
Output
Compliance
Voltage
V
DIGITAL AND DC CHARACTERISTICS
Logic Input
Voltage
I
Logic High
BitON
AJ and LJ Suffix
ACJ and LCJ Suffix
Logic Low
AJ and LJ Suffix
ACJ and LCJ Suffix
Max Bit OFF
Logic Input
Current Max
Logic High
Logic Low
0.8
1.0
AJ and LJ Suffix
ACJ and LCJ Sufix
150
150
300
AJ and LJ Suffix
ACJ and LCJ Suffix
45
45
100
280
90
V
0.8
0.8
1.0
150
150
300
300
45
45
100
100
280
90
0.8
/LA
300
100
Power Supply
Current Max
V- Supply= -15V±10%
-12
~18
-12
-18
mA
Power
Dissipation Max
V- Supply= -15V
180
270
180
270
mW
Power Supply
Sensitivity Max
V- Supply= -12V±5%
10
±15
±25
±15
±25
V- Supply= -15V±10%
10
±15
±25
±15
±25
ppm of FSI
% VSUPPLY
AC CHARACTERISTICS
Settling
Time Max
FSRChange
200
400
200
400
Full-scale
Transition Max
Delay Plus 10% to 90% Rise Time
15
30
15
30
Delay Plus 90% to 10% Fall Time
30
50
30
Note 1: The typical 8JA 01 the 24·pin package is 80" CfW.
Note 2: Tested and guaranteed to National's AOQL (Average Outgoing Quality Level).
Note 3: Guaranteed, but not 100% production tested. These IimHs are not used to calculate outgoing quality levels.
50
ns
ns
Note 4: Unearity error = VOUT - VOFF~ET - (0 x VLSBl where VLSB = VFS - VOFFSET and 0 is the digHsI input (0 to 4095) which produced VOUT.
LSB
4095
Note 5: Percent gain error for 10V range = (VFS - VOFFSET) - (4095f4096)VREF x 100.
VREF
Nole 6: Unipolar offset error lor 10V range = (VOUTfVREF) x 100 in percent of lull·scale.
Note 7: Bipolar offset error for 10V range = VOUT -V(-VREFf 2) x 100 in percent 01 lull·scale.
REF
.
Note 8: Bipolar zero error for 10V range = (VOUTfVREF) x 100 in percent of lull·scale.
Note 9: Gain error tempco = (VFS - VOFFSET) at (TMAX arTMIN) - (VFS - VOFFSET) at 25'C x 1()6 in ppmf'C.
10V range x (TMAX or TMIN 25'C)
Note 10: Power supply sensitivity for 10V range = 106 x (VFS - VOFFSET) al(-13.5V) - (VFS - VOFFSET) at (-16.5V) In ppm of FSf% Vs.
VREF X 20%
Note 11: Absolute Maximum Ratings indicate IimHs beyond which damage to the device may occur. DC and AC electrical specifications do not apply when
operating the device beyond its specified operating conditions.
Note 12: Human body model, 100 pF discharged through a 1.5 kO resistor.
4-126
Functional Description and
Applications
1.2 Bipolar Configuration (Figure 2)
1.0 BUFFERED VOLTAGE OUTPUT CONNECTION
The standard current·to·voltage conversion connections using an operational amplifier are shown here with the preferred trimming techniques. If a low offset operational amplifier (LF401A) is used, excellent performance can be obtained in many situations without trimming (an op amp with
less than O.S mV maximum offset voltage should be used to
keep offset errors below % LSB). Unipolar zero will typically
be within ± % LSB (plus op amp offset), and if a son fixed
resistor is substituted for the 100n trimmer (R2, Figure 1),
full-scale accuracy will be within 0.1 % (0.20% maximum).
Substituting a son resistor for the 100n bipolar offset trimmer (R1, Figure 2) will give a bipolar zero error typically
within ±2 LSB (O.OS%).
This configuration will provide a bipolar output voltage from
-S.OOOV to 4.9976V, with positive full-scale occurring with
all bits ON (all 1s).
Step 1-Qffset Adjust
Turn OFF all bits. Adjust 100n offset trimmer, R 1, to give
-S.OOOVoutput.
Step 2-Gain Adjust
Turn ON all bits. Adjust 100n gain trimmer, R2, to give a
reading of 4.9976V.
Please note that it is not necessary to trim the op amp to
obtain full accuracy at room temperature. In most bipolar
situations, an op amp trim is unnecessary unless the untrimmed offset drift of the op amp is excessive. Bipolar zero
error (MSB bit ON) is not adjusted separately and is typically
< ±O.OS% of FS after offset and gain adjust.
1.1 Unipolar Configuration (Figure 1)
This configuration will provide a unipolar OV to 9.9976V output range.
Step 1-Qffset Adjust (Zero)
1.3 Other Voltage Ranges (Figure 3)
Turn all bits OFF and adjust zero trimmer, R1, until the output reads O.OOOV (1 LSB = 2.44 mY). In most cases this trim
is not needed.
The DAC1266A and DAC1266 can also be easily configured
for a unipolar OV to SV range or ± 2.SV and ± 10V bipolar
ranges by using the additional Sk application resistor provided at the 20V range R terminal, pin 11. For a SV span (OV to
SV or ± 2.SV), the two Sk resistors are used in parallel by
shorting pin 11 to pin 9 and connecting pin 10 to the op amp
output and the bipolar offset either left open for unipolar or
connected through a 100n pot to the external
Step 2-Gain Adjust
Turn all bits ON and adjust 1000 gain trimmer, R2, until the
output is 9.9976V (full-scale adjusted to 1 LSB less than
nominal full-scale of 10.000V). If a 10.237SV full-scale is
desired (exactly 2.S mVlbit), insert a 1200 resistor in series
with the gain resistor at pin 10 to the op amp output or use
the LH0071 voltage reference.
-16V
BIPOLAR OFF
II
OAtl266A
OAtl266
9.95k
20V RANGE
5k
10
-
'REF
B.SmA
IOV RANGE
-
V+
OAt
IDUT" 4 It IREF
It
OUTPUT
OVTO 10V
OAt OUT
10
ANA
GNO
10pF
5k
B'
2.4k
CODE
-=
-Vs
PWR GNO
TL/H/5068-2
·Power and analog ground must have
FIGURE 1. OV to 10V Unipolar Voltage Output
4-127
a common current return path. See
section 3.0 for proper connections.
•
Functional Desc:ription and Applications (Continued)
RI
IDO
BIPOLAR OFF
11
DACIIIIA
DACIIII
5.
9,9511
-
!OVRANGE
IREF
a.SmA
DUTI'UT
-IV TO SV
5.
-
DAC
10
ANA
.ND
I.
IOUT·4 x IREF x CODE
CODE INPUT
13
-VS
LS.
TLlH/5068-6
·Power and analog ground must have
a common current return path. Sse
section 3.0 lor proper connections.
FIGURE 2. ± 5V Bipolar Voltage Output
81
lDO
BIPOLAR OFF
11
IOVRANGE
-
DACI21I1IA
DACI21I1I
SUMMING
9.9Sk
5'
10
-
IREF
JUNCTION
5
IU5Io
REF IN
v'
10V RANCE
O.5mA
-
DAC
1111<
ANA
GND
OUTPUT
-10VTO
10V
10
lOUT" 4 x IREF
I
I.
CODE
CODE INPUT
-VS
10"
Ok
':'
, - - - - - - - - _ . LSB
TLlH/5068-3
FIGURE 3. ± 10V Voltage Output
'Power and analog ground must have
a common cul1'8nt return path. See
section 3.0 lor proper connections.
4-128
Functional Description and
Applications (Continued)
reference for the bipolar range. For the ± 1OV range use the
5k resistors in series by connecting only pin 11 to the op
amp output and connecting the bipolar offset as shown. The
± 1OV option is shown in Figure 3.
The analog ground at pin 3 is the ground reference pOint for
the internal reference and is thus the "high quality" ground;
it should be connected directly to the analog reference point
of the system. The power ground at pin 12 can be connected to the most convenient ground reference point; analog
power return is preferred, but digital ground is acceptable. If
power ground contains high frequency noise beyond 200
mV, this noise may feed through the converter, so that
some caution will be required in applying these grounds.
2.0 DIGITAL INPUT
The DAC1266A and DAC1266 use a standard positive true
straight binary code for unipolar outputs (all 1s give fullscale output), and an offset binary code for bipolar output
ranges. In the bipolar mode, with all Os on the inputs, the
output will go to negative full-scale; with 100...00 (only the
MSB on), the output will be O.OOV; with all 1s, the output will
go to positive full-scale.
4.0 OUTPUT VOLTAGE COMPLIANCE
The DAC1266A and DAC1266 have a typical output compliance range from -2V to 10V. The current-steering output
stages will be unaffected by changes in the output terminal
voltage over that range. However, there is an equivalent
output impedance of 8k in parallel with 25 pF at the output
terminal which produces an equivalent error current if the
voltage deviates from power ground. This is a linear effect
that does not change with input code. Operation beyond the
compliance limits may cause either output stage saturation
or breakdown which results in non-linear performance.
Compliance limits are a function of output current and negative supply.
The threshold of the digital input circuitry is set at 1.4V and
does not vary with supply voltage. The input lines can interface with any type of 5V logic, TTLlDTL or CMOS, and have
sufficiently low input currents to interface easily with unbuffered CMOS logic. The configuration of the input circuit is
shown in Figure 4. The input line can be modelled as a 30
kO resistance connected to a -0.7V rail.
DIGITAL
INPUTS
(PINS 13 TO 241
..L
5.0 DIRECT UNBUFFERED VOLTAGE OUTPUT FOR
CABLE DRIVING
SPF
TPWR
The wide compliance range allows direct current-to-voltage
conversion with just an output resistor. Figure 5 shows a
connection using the gain and bipolar output resistors to
give a ± 1.60V bipolar swing. In this situation, the digital
code is complementary binary. Other combinations of internal and external output resistors (Rx) can be used to scale
to alternate voltage ranges, simply by appropriately scaling
the 0 rnA to - 2 rnA unipolar output current and using the
1O.OV reference voltage for bipolar offset. For example, setting Rx = 2.67 kO gives a ± 1V range with a 1 kO equivalent
output impedance.
30k
":" GND
-D.1V
.......-oTOLOGIC
TL/H/5068-4
FIGURE 4. Equivalent Digital Input Circuit
3.0 APPLICATION OF ANALOG AND POWER GROUND
The DAC1266A and DAC1266 have separate analog and
power ground pins to allow optimum connections for low
noise and high speed performance. The two ground lines
can be separated by up to 200 mV without any loss in performance. There may be some loss in linearity beyond that
level. If these DACs are to be used in a system in which the
two grounds will be ultimately connected at some distance
from the device, it is recommended that parallel back-toback diodes be connected between the ground lines near
the device to prevent a fault condition.
This connection is especially useful for directly driving a
long cable at high speed. Using a 500 resistor for Rx would
allow interface to a 500 cable with a ± 50 mV full-scale
swing.
6.0 HIGH SPEED 12-BIT AID CONVERTERS
The fast settling characteristics of the DAC1266A and
DAC1266 make them ideal for high speed successive approximation AID converters. Shown in Figure 6 is a configuration using standard components; this system completes a
full 12-bit conversion in 10 ,...s unipolar or bipolar. This converter will be accurate to ± % LSB of 12 bits and have a
typical gain TC of 10 ppml"C.
4-129
II
co
co
....C'II
g
....
Functional Description and Applications (Continued)
50
~O"PF
~
co
C'II
....
BIPOLAR OFF
5k
11
o
«c
20V RANGE
DACI2&6A
OAC126&
9.9Sk
5'
10
'REF
10V RANGE
~
19.95k
Sk
REF IN
V·
ANA
GND 3
OAe
'Ok
DACDUT
RX
8k
lOUT" 4 I( IREF
-Vs
II
CODE
-'------~
••
lSB
FIGURE 5. Unbuffered Bipolar Voltage Output
BIPOLAR UNIPOLAR
lOOk
10............."......._
R3
100
I
15V
~.IUNIPOlARI
100
-15V
BIPOLAR OFF
11
: ) ANALOG INPUTS
20Y RANGE
9.95k
OAC1266A
511
DACU66
AMP
SUMMING
JUNCTION
'9.95k
15V
10
'REF
~
5.
REF
v'
5V
10VRANGE
1k
IN
".
OAC
~
10
ANA
GNO
lOUT; 4 II 'REF J. CODE
..
CODE INPUT
LSU
13
-Vs
DIG DUl
E.LJ _...::LS::.'-t::+-+-t-t-I-::ir.i-t-+-+
...
""7""l
21
1& 9
11
"ClINVCliMi'---: and low (T MIN)
temperatures. Gain tempco is calculated for both high
(TMAX-2S'C) and low (2S'C-T MIN) ranges by dividing the
gain error by the respective change in temperature. The
specification is the larger of the two representing worstcase drift.
Offset Tempeo: The change in analog output with all bits
OFF over the specified temperature expressed in parts per
million of full-scale per 'C (ppm of FSI'C). Offset error is
measured with respect to 2S'C at high (TMAX) and low
(TMIN) temperatures. Offset tempco is calculated for both
high (TMAX-2S'C) and low (2S'C- TMIN) ranges by dividing
the offset error by the respective change in temperature.
The specification given is the larger of the two, representing
worst-case drift.
Power Supply Sensitivity: Power supply sensitivity is a
measure of the change in gain and offset of the 01 A converter resulting from a change in -1SV supply. It is specified under OC conditions and expressed as parts per million
of full-scale per percent of change in power supply (ppm of
FS/%).
Analog Output
Digital
Input
MSBLSB
000... 000
011 ... 111
100...000
111 ... 111
Straight
Binary
Offset
Binary
Two's
Complement"
zero
-FS (Full-Scale)
LSB
zero-1 LSB
zero
%FS
+FS-1 LSB
+FS-1 LSB
zero
+FS-1 LSB
-FS
zero-1 LSB
% FS-1
II
*Invert MSB with external inverter to obtain Two's Complement coding
Ordering Information
Temperature Range
Linearity Error
OverTemperature
I
I
O"C to 70'C
-55'C to + 125'C
± % Bit
DAC1266ACJ
DAC1266AJ
±% Bit
DAC1266LCJ
OAC1266LJ
r-~~--+------------r--------------~
4-131
Section 5
Sample and Hold
II
Section 5 Contents
Sample and Hold Definition ofTerms.................................. .. ............. .
Sample and Hold Selection Guide ....................................................
LF198/LF298/LF198A1LF398A Monolithic Sample and Hold Circuits. . . . . . . . . . . . . . . . . . . . .
LF13006/LF13007 Digital Gain Set...................................................
LH0023/LH0023C/LH0043/LH0043C Sample and Hold Circuits.........................
LH0053/LH0053C High Speed Sample and Hold Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LH4860 Super Fast 12-Bit Track-Hold Amplifier ........................................
5-2
5-3
5-4
5-5
5-15
5-22
5-31
5-37
r--------------------------------------------------------------------,0
DI
3
CD
~National
'1:1
~ Semiconductor
DI
;:,
Co
:::z::
Sample and Hold
Definition of Terms
o
fc
!!.
S"
::;:
Acquisition Time: The time required to acquire a new analog input voltage with an output step of 1av. Note that acquisition time is not just the time required for the output to
settle, but also includes the time required for all internal
nodes to settle so that the output assumes the proper value
when switched to the hold mode.
Gain Error: The ratio of output voltage swing to input voltage swing in the sample mode expressed as a percent difference.
Hold Settling Time: The time required for the output to
settle within 1 mV of final value aiter the "hold" logic command.
Hold Step: The voltage step at the output of the sample
and hold when switching from sample mode to hold mode
with a steady (~C) analog input voltage. Logic swing is 5V.
Aperture Time: The delay required between "Hold" command and an input analog transition, so that the transition
does not affect the held output.
Dynamic Sampling Error: The error introduced into the
held output due to a changing analog input at the time the
hold command is given. Error is expressed in mV with a
given hold capacitor value and input slew rate. Note that
this error term occurs even for long sample times.
5-3
cr
;:,
o
';;}
3
en
~NatiOnal
Semiconductor
Sample and Hold Selection Guide
LHOO23
LHOO43
LHOO53
LH4860
Units
0,01
0.1
0.2
0,01
% Max
20
40
7
5
mVMax
10
' 1
6
500
(Note 2)
mVlsec
1
Acquisition TIme (25·C)
Cs = 1000pF
Cs = 10000pF
N/A
50
10
30
4
0.15
(Note 2)
,...s
(Note 1)
Aperture TIme (25"C)
150
20
10
6
ns
Temperature Range
-55 to +125
-55 to +125
-55 to +125
-55 to +125
·C
High Speed
12-Bit
High Speed
Accuracy
Gain/Offset Error
Offset Voltage
Droop Rate (25·C)
Cs = 1000pF
Cs = 10000pF
Comment
Nola 1: Cs
Low Drift
Medium Speed
= 100 pF
Nota 2: Cs is internal
Accuracy
Gain/Offset Error
LF198A
LF398A
LF198
LF398
LF298
Units
0,01
0.01
0.02
0.02
0.02
% Max
Offset Voltage
2
3
5
10
5
mVMax
Droop Rate (25·C)
Cs = 1000pF
Cs = 10000pF
30
3
30
3
30
3
30
3
30
mV/sec
Acquisition TIme (25"C)
Cs = 1000pF
Cs = 10000pF
4
4
4
4
4
20
20
20
20
20
3
,...s
Aperture Time (25·C)
250
250
250
250
250
ns
Temperature Range
-55 to +125
Oto +70
-55to +125
Oto +70
-25 to +85
·C
Low Drift
Low Drift
General
Purpose
General
Purpose
Low Drift
Comment
5-4
r-
....
CD
."
~National
~
~ Semiconductor
."
LF198/LF298/LF398,LF198A/LF398A
........
Monolithic Sample and Hold Circuits
~
CD
co
r~
~
r-
General Description
Features
The LF198/LF298/LF398 are monolithic sample and hold
circuits which utilize BI-FET technology to obtain ultra-high
dc accuracy with fast acquisition of signal and low droop
rate. Operating as a unity gain follower, dc gain accuracy is
0.002% typical and acquisition time is as low as 6 p,s to
0.01 %. A bipolar input stage is used to achieve low offset
voltage and wide bandwidth. Input offset adjust is accomplished with a single pin, and does not degrade input offset
drift. The wide bandwidth allows the LF198 to be included
inside the feedback loop of 1 MHz op amps without having
stability problems. Input impedance of 10100 allows high
source impedances to be used without degrading accuracy.
P-channeljunction FET'sare combined with bipolar devices in
the output amplifier to give droop rates as low as 5 mVImin
with a 1 p,F hold capacitor. The JFET's have much lower
noise than MOS devices used in previous designs and do
not exhibit high temperature instabilities. The overall deSign
guarantees no feed-through from input to output in the hold
mode, even for input signals equal to the supply voltages.
• Operates from ±5V to ± 18V supplies
• Less than 10 p,s acquisition time
• TTL, PMOS, CMOS compatible logic input
• 0.5 mV typical hold step at Ch = 0,01 p,F
• Low input offset
• 0.002% gain accuracy
• Low output noise in hold mode
• Input characteristics do not change during hold mode
• High supply rejection ratio in sample or hold
• Wide bandwidth
LogiC inputs on the LF198 are fully differential with low input
current, allowing direct connection to TTL, PMOS, and
CMOS. Differential threshold is 1.4V. The LF198 will operate from ± 5V to ± 18V supplies. It is available in an 8-lead
TO-5 package.
An "An version is available with tightened electrical specifications.
Typical Connection and Performance Curve
OUTPUT
1000-0.01
0.001
0.1
HOLO CAPACITOR I.F)
TUH/5692-2
Connection Diagrams
Metal Can Package
LOGIC
Dual-In-Une Package
v·
1
OFFSET
ADJUST
2
LOGIC
1
INPUT
LOGIC
REFERENCE
OFFSET
ADJUST
Ch
V-
OUTPUT
V-
TOP VIEW
TDPVIEW
Order Number LF398N or LF398AN
See NS Package Number N08E
Order Number LF198H, LF298H,
LF398H, LF198AH or LF398AH
See NS Package Number H08e
5-5
TL/H/5692-11
'"
r."
....
;........
CD
r-
i
3kHz
o
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
U
~
I~
I~
"TI
IA I.
TIME (1"')
TLlH/5692-12
nWE (Ju)
M
~
Co)
CD
TL/H/5692-13
;
Logic Input Configurations
TTL & CMOS
3V os; VL (Hi State) os; 7V
Threshold = l.4V
'Select for 2.BV at pin B
v'
7V
OS;
CMOS
VL (HI State) os; 15V
v'
20.
30k
n
-1
Threshold = 0.6 (V+) + 1.4V
HOLO
20k
LSAMPLE
•
Threshold = 0.6 (V +) - 1.4V
OpAmpDrlve
'13VRAMPLE
- -
-13
Threshold'"
-
-""",.....
8.2k
"3VHOLO
':' 82k
--J\N\_....
HOLD
-'3V
SAMPLE
4.7k
+ 4V
Threshold
5-9
=
-4V
TLlH/5692-6
:i
G)
fZ
....I
~
....
LL
G)
....I
!
LL
....I
......
co
G)
~
......
co
G)
....I
....LL
....I
Application Hints
Hold Capacitor
tor on the chip. This means that at the moment the "hold"
command arrives, the hold capacitor voltage may be somewhat different than the actual analog input. The effect of
these delays is opposite to the effect created by delays in
the logic which switches the circuit from sample to hold. For
example, consider an analog input of 20 Vp-p at 10 kHz.
Maximum dV/dt is 0.6 V//Ls. With no analog phase delay
and 100 ns logic delay, one could expect up to (0.1 /Ls)
(0.6V I /Ls) = 60 mV error if the "hold" signal arrived near
maximum dV/dt of the input. A positive-going input would
give a + 60 mV error. Now assume a 1 MHz (3 dB) bandwidth for the overall analog loop. This generates a phase
delay of 160 ns. If the hold capacitor sees this exact delay,
then error due to analog delay will be (0.16 /Ls) (0.6 VI /Ls)
= -96 mV. Total output error is +60 mV (digital) -96 mV
(analog) for a total of -36 mV. To add to the confusion,
analog delay is proportioned to hold capacitor value while
digital delay remains constant. A family of curves (dynamic
sampling error) is included to help estimate errors.
A curve labeled Aperture Time has been included for sampling conditions where the input is steady during the sampling period, but may experience a sudden change nearly
coincident with the "hold" command. This curve is based on
a 1 mV error fed into the output.
Hold step, acquisition time, and droop rate are the major
trade-offs in the 'selection of a hold capacitor value. Size
and cost may also become important for larger values. Use
of the curves included with this data sheet should be helpful
in selecting a reasonable value of capacitance. Keep in
mind that for fast repetition rates or tracking fast signals, the
capacitor drive currents may cause a significant temperature rise in the LF198 .
A significant source of error in an accurate sample and hold
circuit is dielectric absorption in the hold capacitor. A mylar
cap, for instance, may,"sag back" up to 0.2% after a quick
change in voltage. A long sample time is required before the
circuit can be put back into the hold mode with this type of
capacitor. Dielectrics with very low hysteresis are polystyrene, polypropylene, and Teflon. Other types such as mica
and polycarbonate are not nearly as good. Ceramic is unusable with> 1% hysteresis. The advantage of polypropylene
over polystyrene is that it extends the maximum ambient
temperature from 85'C to 100'C. "NPO" or "COG" capacitors are now available for 125'C operation and also have
low dielectric absorption. For more exact data, see the
curve Dielectric Absorption EffOr. The hysteresis numbers
on the curve are final values, taken after full relaxation. The
hysteresis error can be significantly reduced if the output of
the LF198 is digitized quickly after the hold mode is initiated.
The hysteresis relaxation time constant in polypropylene, for
instance, is 10-50 ms. If A-to-D conversion can be made
within 1 ms, hysteresis error will be reduced by a factor of
ten.
A second curve, Hold Settling Time indicates the time required for the output to settle to 1 mV after the "hold" command.'
,
Digital Feedthrough
Fast rise time logic signals can cause hold errors by feeding
externally into the analog input at the same time the amplifier is put into the hold mode. To minimize this problem,
board layout should keep logic lines as far as possible from
the analog input. Grounded guarding traces may also be
used around the input line, especially if it is driven from a
high impedance source. Reducing high amplitude logic signals to 2.5V will also help.
DC and AC Zeroing
DC zeroing is accomplished by connecting the offset adjust
pin to the wiper of a 1 kO potentiometer which has one end
tied to V + and the other end tied through a resistor to
ground. The resistor should be selected to give :::: 0.6 mA
through the 1k potentiometer.
AC zeroing (hold step zeroing) can be obtained by addh1g
an inverter with the adjustment pot tied input to output. A
10 pF capacitor from the wiper to the hold capacitor will give
±4 mV hold step adjustment with a 0.Q1 /LF hold capacitor
and 5V logic supply. For larger logic swings, a smaller capacitor « 10 pF) may be used.
Guarding Technique
v'
Logic Rise Time
For proper operation, logic signals into the LF198 must have
a minimum dV/dt of 1.0 V//Ls. Slower signals will cause
excessive hold step. If a RIC network is used in front of the
logic input for signal delay, calculate the slope of the waveform at the threshold point to ensure that it is at least
1.0 V//Ls.
Sampling Dynamic Signals
Sample error to moving input signals probably causes more
confusion among sample-and-hold users than any other parameter. The primary reason for this is that many users
make the assumption that the sample and hold amplifier is
truly locked on to the input signal while in the sample mode.
In actuality, there are finite phase delays through the circuit
creating an input-output differential for fast moving signals.
In addition, although the output may have settled, the hold
capacitor has an additional lag due to the 3000 series resis-
BOnoMViEW
TL/H/5692-5
Use 10-pln layout. Guard around Ch Is tied to output.
5-10
r-
....
CD
."
Functional Diagram
CD
.....
r-
~
OFFSET
-------------"I
Z
CD
CD
.....
r-
~
I
I
I
INPUT
3
I
+
1/
LOGlcn>1
1
LOGIC
REFERENCE
CD
~
OUTPUT
r-
....
CD
I
."
I
I
;.....
r-
I
3DD
~
I
I
I
_ _ _ _ ....J
_/
11
L _________ _
;
6
HOLO
CAPACITOR
TL/H/5692-1
Typical Applications (Continued)
X1000 Sample & Hold
Sample and Difference Circuit
(Output Follows Input in Hold Mode)
VOUT
15V
RI
:~
OFF':; ~~"A""+""';'i
D.OlpF
AOJUST
V,N
VOUT
-15V
~ I-'W.....+--_......
n.
VOUT
VIN
":"
·For lower gains, the LM108 must be frequency compensated
100
Use:::: Av pF from camp 2 t~ ground
5-11
RESET
TRACK
= VB + aV,N(HOLD MODE)
TLlH/5692-7
Typical Applications (Continued)
Ramp Generator with Variable Reset Level
IIV
Integrator with Programmable Reset Level
v+
AI
Uk
-IIV
Dl
L.,13
1.2V
AESET
LEVEL
INPUT
AESET
LEVEL
INPUT
~:""'-I--4~ODUTPUT
RESET
IV-,..,
1V...J
R_
L" DIFFERENTIAL
INTEGRATING
INPUT
1
RI
1M
I"
o-JVII',~",-~
R3
1M
1%
I!.V
I.2V
'~e;' ~g~ ramp rate I!.T = (R2)(Ct.)
R4
200k
1%
Output Holds at Average of Sampled Input
Increased Slew Current
DUTPUT
INPUT
T
Select (Rill «4,)
>
Ch
1
2'1rlIN (Min)
Reset Stabilized Amplifier (Gain of 1000)
Fast Acquisition, Low Droop Sample & Hold
1M
1k
1%
15V
'"
DUTPUT
INPUT
DUTPUT
-15V
20ft
30k
IV:rL
IV
-l I- AESET PULSE
~2ml
Vos ,; 2O"V (No trim)
ZIN:::: 1 MO
I!.Vos :::: 30"Vlsec
I!.I
'"
':'
5V TO 15V
-j
r-
121111
r-
.s-L
Uk
4.1k
O.oI.F
I!.~~ :::: O.I"V/'C
T
':'
TLlH/5692-8
5·12
r-
....
CO
."
Typical Applications
(Continued)
Synchronous Correlator for Recovering
Signals Below Noise Level
CO
"."
r-
2-Channel Switch
15V
I\)
15V
CO
CO
"r-
OUTPUT FREOUENCY
SET BY SWEEP RATE
.A
" V
V
~
OOCV
.A. S~GNAL
>:--'\NIf--....
NPUT
CO
"A"'NPUT
CO
r"."
....CO
;
"A"SELECT
5V-n
Dv--I
L...
"B"SELECT
"r-
~
"B"INPUT
A
± 0.02%
Gain
10100.
Z'N
BW
"" 1 MHz
Crosstalk -90 dB
@ 1 kHz
";6mV
Offset
LM122H
TIMER
R6
4.1k
20k
4
Cl
41DpF
C2**
6
5 ID
,,; 75mV
NC
component of input noise
"Select C2
@ '"
5 X lo-elf,N
DC & AC Zeroing
Staircase Generator
15V
DC
ZERO
CO
;
'Select Cl to filter lowest frequency
TO SCOPE SWEEP
OUTPUT. SCALE R3
TO OBTAIN ~OTO 3V
AT PIN 6.
Vos
B
1 ± 0.2%
47ko.
"" 400kHz
-90dB
15V
RESET
5V-n
DV--I L...
>::""_",,--,,,-0 OUTPUT
RI
4.1k
Ol
LM11l
CLOCK
12V
5V-1I n
OV"'" L.J L...
R&*
SDk
R5
11k
R4
8.2k
II
R8
12k
...Y,fIt-_-o15V
02
IN914
TL/H/5692-9
'Select for step height
50k .... '" IV Step
5-13
~
en
C')
Typical Applications (Continued)
LA.
-I
.......
':"'--t-OOUTPUT
CX)
en
("i
LA.
-I
Ch
LOGIC
.......
CX)
Rl
200k
R2
200k
en
....
LA.
-I
"Select for time constant C1 = 1;Ok
·"Adjust for amplitude
TLIH15692-10
Definition of Terms
Hold Step: The voltage step at the output of the sample
and hold when switching from sample mode to hold mode
with a steady (de) analog input voltage. Logic swing is 5V.
Acquisition Time: The time required to acquire a new analog input voltage with an output step of 1av. Note that acquisition time is not just the time required for the output to
settle, but also includes the time required for all internal
nodes to settle so that the output assumes the proper value
when switched to the hold mode.
Gain Error: The ratio of output voltage swing to input voltage swing in the sample mode expressed as a per cent
difference.
Hold Settling Time: The time required for the output to
settle within 1 mV of final value after the "hold" logic command.
Dynamic Sampling Error: The error introduced into the
held output due to a changing analog input at the time the
hold command is given. Error is expressed in mV with a
given hold capacitor value and input slew rate. Note that
this error term occurs even for long sample times.
Aperture Time: The delay required between "Hold" command and an input analog transition, so that the transition
does not affect the held output.
5-14
.-"T1
~National
PRELIMINARY
~ Semiconductor
.....
Co)
o
oQ)
......
.-"T1
.....
LF13006/LF13007 Digital Gain Set
Co)
o
o
......
General Description
The LF13006 and LF13007 are precision digital gain sets
used for accurately setting non-inverting op amp gains.
Gains are set with a 3-bit digital word which can be latched
in with WR and CS pins. All digital inputs are TTL and CMOS
compatible.
The LF13006 shown below will set binary scaled gains of 1,
2,4,8,16,32,64, and 128. The LF13007 will set gains of 1,
2, 5, 10, 20, 50, and 100 (a common attenuator sequence).
In addition, both versions have several taps and two uncommitted matching resistors that allow customization of the
gain.
The gains are set with precision thin film resistors. The low
temperature coefficient of the thin film resistors and their
excellent tracking result in gain ratios which are virtually independent of temperature.
The LF13006, LF13007 used in conjunction with an amplifier not only satisfies the need for a digitally programmable
amplifier in microprocessor based systems, but is also useful for discrete applications, eliminating the need to find
0.5% resistors in the ratio of 100 to 1 which track each
other over temperature.
Features
II TTL and CMOS compatible logic levels
II Microprocessor compatible
Gain error 0.5% max
Binary or scope knob gains
II Wide supply range + 5V to ± 18V
II Packaged in 16-pin DIP
II
III
Block Diagram and Typical Application
(LF13006)
LFl3DD6
,.--------t-EXT
,.------t- 8 00l
2R
DIG IN
MSB3
DIG IN
2
AOUT
INPUT
DIG IN
LSB 1.
DAlABUS
CONTROL
UNES
TL/H/5114-1
Note: R'" 15 kfl
Order Number LF13006N or LF13007N
See NS Package Number N16A
5-15
Operating Ratings
Absolute Maximum Ratings
(Note 1)
Operating Temperature Range
Lead Temp. (Soldering, 10 seconds)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage, V+ to V36V
Supply Voltage, V+ to GND
25V
Voltage at Any Digital Input
V+ toGND
V+ to (V- + 2V)
Analog Voltage
-40"Cto +85·C
260·C
Electrical Characteristics (Note 2)
Parameter
Conditions
Typ
(Note 3)
Tested
Limit
(Note 4)
Design
Limit
(Note 5)
Units
0.5
0.5
'Yo(max)
Gain Error
AOUT= ±10V
ANAGND=OV
IINPUT<10 nA
0.3
Gain Temperature Coefficient
AoUT= ±10V
ANAGND=OV
0.001
Digital Input Voltage
Low
High
Digital Input Current
Low
High
'Yorc
1.4
1.6
0.8
2.0
0.8
2.0
V(max)
V(min)
-38
0.0001
-100
1
",A(max)
",A(max)
2
-1.7
5
-5
-100
1
5
-5
Positive Power Supply Current
VIL=OV
VIH=5V
All Logic Inputs Low
Negative Power Supply Current
All Logic Inputs Low
Write Pulse Width, tw
VIL = OV, VIH = 5V
150
ns(min)
Chip Select Set-Up Time, tcs
VIL =OV, VIH=5V
250
ns(min)
Chip Select Hold Time, tCH
VIL =OV, VIH=5V
0
ns(min)
DIG IN Set-Up Time, tDS
VIL =OV, VIH=5V
150
ns(min)
DIG iN Hold Time, tDH
VIL =OV, VIH=5V
(Note 4)
60
Switching Time for Gain Change
3
Unit Resistance, R
15
mA(max)
ns(min)
ns(max)
200
Switch On Resistance
mA(max)
kfl
kfl
R1 and R2 Mismatch
'Yo(max)
0.3
0.5
0.5
R1 IR2 Temperature Coefficient
'Yorc
0.001
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when oparating
the device beyond its specified operating conditions.
Note 2: Parameters are specified at V+ = lSV and V- = -lSV. Min V+ to ground voltage is SV. Min V+ to V- voltage is SV. Boldface numbera apply over full
operating temperature ranges. All other numbers apply at TA= Tj = 2S'C.
Note 3: Typicals are at 2SOC and represent most likely parametric norm.
Note 4: Guaranteed and 100% production tested.
Note 5: Guaranteed (but not 100% production tested) over the oparating temperatura. These limits are not used to calculate outgoing quality levels.
Note 6: Settling time for gain change is the switching time for gain change plus settling time (see section on Settling Time).
Note 7: WR minimum high threshold voltage Increases to 2.4V under the extreme condRions when all three digital Inputs are simultaneously taken from OV to SV at
a slew rate 01 greater than SOOVI ILS.
12-18
Connection Diagram
GAIN TABLE
Dual-In-Line Package
Gain
Digital Input
LF13006
DIGin3
DIGin2
DIG in 1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
AOUT
1
2
4
8
16
32
64
128
BOUT
1
1.25
2.5
5
10
20
40
80
DlBGNO- 1
LF13007
AoUT
1
1.25
2
5
10
20
50
100
BOUT
1
1
1.6
4
8
16
40
80
5-16
V
16 i-ANABNO
INPIIT- 2
15 i-R2
v--
3
14~R,
v+-
4
13~Rl
12 ~AOUT
00- 5
l1~Ci
BOUT- 6
Wii-7
10i-DlB1N3
01GIN1- 8
9i- 0lBIH2
TOP VIEW
TUH/SI14-2
.----------------------------------------------------------------------,r
."
....
Switching Waveforms
Co)
o
oQ)
......
r
....
."
les
cs
~
o
ViH
~
ViH
Wii
5011
VIL
ViH
DATA BITS
VIL
~
.~
los
----sii%
5011
TL/H/5114-3
Block Diagram and Typical Application
(Continued) (LF13007)
:-1- -=[- -i- -bj-j-
- -- -,
LFl3007
r-----------------~Drr
,...-------1- lOUT
DECODE
I
-1- - -l-
L
DIG IN
LSB 1
WII
ei
OIllAIUS
CONTROL
UNES
TL/H/5114-4
Note: R '" 15 kO
5-17
•
Typical Performance Characteristics
Positive Power Supply
Current vs Temperature
Negative Power Supply
5.0 H~-t-+-+-+-++-I
-1.0
!4.0
Ii! 3.0 """,,...:t.:.:..j--+--1!''''''"'~+-l
c"-2.0
!§.
Vs-±5V
~fl0VI.... ~ -Vs =±I5V
.... 1""'"
ffi-3.0
2.0
~
~-4.0
1.0
-5.0
a:
8
Digital Input Threshold vs
Temperature
o Current vs Temperature
)~
~ 2.5
..ax:
9
I
-15
25
55
105
TEMPERATURE ('CI
-55
Logical 0 Input Bias Current
~
0.5
70~-;-.-r-r-.-.'-,
50
a:
40
iii
a:
..
:::0
~
_ 2.0
.
!:!j!;
~
30
!!
!!i
-55'C
1.2 -i5'C
0.8 - l r
0.4
o
-15
25
65
105
TEMPERATURE ('CI
Write Width, tw
o
400
!
~
""" .... I-'"
I I"
C
20
..,..
--i--'
9 1.6
~300
~
Ii
Vs= ±5V
!i 200
5
10
15
SUPPLY VOLTAGE ,(VI
Data Set-Up Time, tos
~~
~
Vs= ±15V
vs'= ±2D1i,
100 -"v::tr
~
I
o
-55
20
-15
25
65
TEMPERATURE ('CI
105
'Chip Select Set-Up Time, les
500
500
!
»
~~~
-55
I
400
.... 1-"'
~300
........
Y$=±5V i-" ~
....
~ ....
o
,
-15
25
65
105
TEMPERATURE ('CI
500
::.
:z:
10
-55
-55
2.4
60
...~
o
-15
25
55
105
TEMPERATURE ('CI
Digital Input Threshold vs
Supply Voltage
VB Temperature
--
j$
~
o t:t:tt±±±±±:1
-55
Vs=±15V
~
j!; 1.5
....0
;::
-
Y$=±20V
Vs= ±5V
~
200
'"
I:J
100
o
-15
25
65
105
TEMPERATURE ('CI
~ov
-55
.........
"'"
Vsj ±15V
Vs= ±20V
-15
25
55
105
TEMPERATURE ('CI
TLlH/5114-5
5-18
r-
...."11
Application Information
Co:»
use of a lead capacitor from the inverting input to the output
of the amplifier. A lead capacitor is effective whenever the
feedback around an amplifier is resistive, whether with discrete resistors or with the LF1300617. It compensates for
the feedback pole created by the parallel resistance and
capacitance from the inverting input of the op amp to AC
ground.
FLOW-THROUGH OPERATION
THE LF13006, LF13007 can be operated with control lines
CS and WR grounded. In this mode new data on the digital
inputs will immediately set the new gain value. Input data
cannot be latched in this mode.
INPUT CURRENT
Settling Time Test Circuit
Current flowing through the input (pin 2) due to bias current
of the op amp will result in a gain error due to switch impedance. Normally this error is very small. For example, 10 nA
of bias current flowing through 3 kn of switch resistance will
result in an error of 30 IJ-V at the summing node. However,
applications that have significant current flowing through the
input must take this effect into account.
C)
C)
en
......
r-
...."11
Co:»
C)
C)
"'"
LFI3DD6
r---:-1
SETTLING TIME
ID/GAIN:r
D
Settling time is a function of the particular op amp used with
the LF1300617 and the gain that is selected. It can be optimized and stability problems can be prevented through the
OUT
IN
TL/H/5114-6
Typical Settling Time Curves
j;
,.~
Ik
;
100
:!
~
:l!
'Ii
1=
W
ll:i Ik
WITH LF351
~
co:
:;;
~
'"
'Ii
~
'Ii
co:
!: IDD
:;0
i
:l!
j;
Ik
'"
co
co
:l!
co
10
I-
w
:Ii!
:I!
ID
I-
;::
co
co
co
z
~
.
:::I
I
D
co
B 10 12
LEAD CAPACITOR IpF)
Iii
14
ID
w
:Ii!
;::
;::
IDD
z
.Iii
:::I
I
0
B ID 12
LEAD CAPACITOR IpF)
14
6 B ID 12
LEAD CAPACITOR IpF)
14
TL/H/5114-7
• Unstable at CL less than 2 pF
Typical Applications
Variable Time Constant Filter
Variable Capacitance Multiplier
Time constant ~
Ceffecllve ~ Cllgain set #)
Note: Output swing at input op amp
~ CI
N ~ setting of LFI3006
is multiplied by set gain. Signal
I
(range ~ 128 to I)
range may be limited.
IN
12
AOUT
12
AOUT
LFI3D06
LFI3D07
15
INPUT 2
LF13006
LFI3D07
DIGITAL
CONTRDL
14
II
15
2 INPUT
":"
14
13
CI
ANA
GNU
16
ANA
GND
16
DIOITAL
CONTROL
BUFFERED
FILTERED~~~~~
DUTPUT
1/2 LF412
DUAL Op·AMP
":"
TL/H/5114-Q
TUH/5114-B
5-19
rQ
Q
.....
~
.....
C")
r------------------------------------------------------------------------------------------,
Typical Applications
(Continued)
Switchable Gain of ± 1
Programmable Current Source
DIBITAL
IN
15V
8.....
C")
3Dk
u.
.....
15
12
LF13DD6
AOUT
LF13006
LF13007
LM385·1.2V
INPUT
ANA
GND
TL/H/5114-11
Nota: Digital code = 000, VOur=VIN;
DigHal code=OOl, Vour= -VIN
Programmable Differential Amp
TUH/5114-10
1.2V [
1
lOUT = 120fl gain set ...
DIGITAL
IN
1
Inverting Gains
-IN
LFI3DD6
LF13D07
ANA
16 GND
AOUT 12
DIGITAL
CONTROL
INPUT
+IN
LF13DD6
Lf13DG7
16
ANA
GND
14
LF13DD8
Lf13DG7
16
DIGITAL
IN
¥auT
TUH/Sl14-12
Inverting gain with high input im·
AOUT
pedance can be obtained with the
12
LFI3006, LF13007 by using the two
TUH/5114-13
on-board resistors and a dual op
amp as shown.
Nota 1: Actual gain=sei galn-l
since LF13006s are in
"inverting mode".
Nota 2: Set gain must be
same on both LFI3006s.
5-20
Typical Applications
Altered Gain Range
.."
.....
(Continued)
Co)
One Octave per Bit Function Generator
Q
Q
Variable Gains of Almost 1
en
."."
.....
OUT
Co)
Q
Q
16
ANA
GND
15
......
15
lf13006
12
lf13006
AOUT
'::"
2 INPUT
2 INPUT
lf13006
INPUT 2
13
DIGITAL
CONTROL
13
DIGITAL
CONTROL
ANA
GND
16
AOUT
12
ANA
GND
16
TL/H/5114-14
TLlH/5114-16
10k
10k
TRIANGLE
WAVE
OUTPUT
TL/H/5114-15
GAINS
GAINS
AOUT
BOUT
1
1.B
1
9
1.B
1.2
2
3
4
4.8
5.33
5.65
1.29
1.125
1.059
1.029
1.014
1.007
3
4.5
6
7.2
8
8.47
Attenuator (0 dB to -42 dB In 6 dB steps)
Programmable Instrumentation Amp
INPIIT
12
AuuI
10k
LFI3DD6
ANA
16 GND
lf13006
lfl3D07
AuuI 12
10k
DUTPIIT
10k
ANA
A-------4
GND
16
TL/H/5114-17
Note I: VOUT=N (A-B), N=set gain.
TL/H/5114-18
Note 2: All 10k resistors 0.1 % matched.
5·21
•
o
..,
C")
8 ~National
:s......
~ Semiconductor
o
LH0023/LH0023C/LH0043/LH0043C Sample
..,
o
C")
:J:
....
......
o and Hold Circuits
C")
C'II
o
o
:J:
....
......
C")
~
o
:J:
....
General Description
Features
The LH0023/LH0023C and LH0043/LH0043C are complete sample and hold circuits including input buffer amplifier, FET output amplifier, analog signal sampling gate, TTL
compatible logic circuitry and level shifting. They are designed to operate from standard ± 15V DC supplies, but
provision is made on the LH0023/LH0023C for connection
of a separate + 5V logic supply in minimum noise applications. The principal' difference between the LH0023/
LH0023C and the LH0043/LH0043C is a 10:1 trade-off in
performance between sample accuracy and sample acquisition time. Devices are pin compatible except for TTL logic
polarity.
LH0023/LH0023C
• Sample accuracy-0.01 % max
• Hold drift rate-0.5 mY/sec typ
• Sample acquisition time-100 P.s max for 20V
• Aperture time-150 ns typ
• Wide analog input range-±10V'min
• Logic input-TTLlDTL compatible
• Offset adjustable to zero with single 10k pot
• Output short circuit proof
The LH0023/LH0023C and LH0043/LH0043C are ideally
suited for a wide variety of sample and hold applications
including data acquisition, analog to digital conversion, synchronous demodulation, and automatic test setup. They offer significant cost and size reduction over equivalent module or discrete designs. Each device is available in a hermetic TO-6 package and is completely specified over both
full military and industrial temperature ranges.
The LH0023 and LH0043 are specified for operation over
the - 55'C to + 125'C military temperature range. The
LH0023C and LH0043C are specified for operation over the
-25'C to +65'C temperature range.
LH0043/LH0043C
• Sample acquisition time-15 P.s max for 20V
4 p.s typ for 5V
• Aperture time-20 ns typ
• Hold drift rate-1 mV /sec typ
• Sample accuracy-0.1 % max
• Wide analog input range- ± 10V min
• Logic input-TTLlDTL compatible
• Offset adjustable to zero with single 10k pot
• Output short circuit protection
Connection Diagrams
LH0023/LH0023C
LH0043/LH0043C
N.C.
ANALOG
INPUT
·Tie for operation •
with V+ = 15Vonly
OUTPUT
N.C.
TOPYIEW
Vee
TOP VIEW
TUK/5693-B
TUK/5693-1
Order N,umber LH0023G or
LH0023CG or LH0043G or
LH0043CG
See Package Number G12B
5-22
~--------------------------------------------------~~
c
Block Diagrams
C
N
Co:!
....
r-
LH0023/LH0023C
:c
c
OFFSET
ADJUST
-
~
Co:!
4
~
r-
S.
:c
c
c
RZ
0l:Io
Co:!
....r-
ANALOG Qiio_",ZO",KV-_...
INPUT
:c
~
>~""00Q OUTPUT
Co:!
o
STORAGE
L..-------o CAPACITOR
RI
LOGIC~
~V'
_ _ _ _""'1
INPUT
~TII.
one to pin 8 for operation without Vee supply.
•
- - - 0 ION 0
10
- - - 0 VTLlK/5693-9
LH0043/LH0043C
OFFSET ADJUST
II
>-4....0
I
LOGIC~_~
INPUT~
OUTPUT
STORAGE
L..-------oI CAPACITOR
IZ
~V·
ID
~V-
•
~GND
5-23
TL/K/5693-10
III
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vs)
±20V
Logic Supply Voltage (Vee> LH0023, LH0023C
Logie Input Voltage (Va)
Analog Input Voltage (V5)
Power Dissipation
See graph
Continuous
Output Short Circuit Duration
Operating Temperature Range
LH0023, LH0043
+7.0V
+5.5V
±15V
- 55·C to + 125·C
-25·Cto +85·C
-65·Cto -150·C
LH0023C, LH0043C
Storage Temperature Range
Lead Soldering (10 seconds)
300·C
Electrical Characteristics LH0023/LH0023C (Note 1)
Limits
Parameter
Conditions
LHOO23
Min
Typ
LHOO23C
Max
Min
Typ
Units
Max
Sample (Logic "1")
Input Voltage
Vee = 4.5V
Sample (Logic "1")
Input Current
Va = 2.4V, Vee = 5.5V
5.0
5.0
",A
Hold (Logic "0")
Input Voltage
Vee = 4.5V
0.8
0.8
V
Hold (Logic "0")
Input Current
Va = 0.4V, Vee = 5.5V
0.5
0.5
mA
2.0
±10
Analog Input
Voltage Range
2.0
± 11
±10
V
±11
V
Supply Current - 110
V5 = OV, Va = 2V,
V11=OV
4.5
6
4.5
6
mA
Supply Current -112
V5 = OV, va = 0.4V,
V11 = OV
4.5
6
4.5
6
mA
mA
Supply Current - Ie
Ve = 5.0V, V5 = 0
Sample Accuracy
VOUT = ±10V (Full Scale)
DC Input Resistance
Sample Mode
Hold Mode
Input Current - 15
Sample Mode
500
20
1.0
1.6
1.0
1.6
0.002
0.01
0.002
0.02
1000
25
0.2
Input Capacitance
1.0
V5 = ±10V;V11 = ±10V,
10.0
pin 1
-55·C:S:TA:S: 125·C
Vs = ±10V;V11 = ±10V
Drift Rate
VOUT = ±5V, Cs = 0,01 ",F,
TA = 25·C
0.5
Drift Rate
VOUT = ±10V,
Cs = 0,01 ",F, T A = 25·C
1.0
Drift Rate
VOUT = ±10V,
Cs = 0.01 ",F
200
20.0
2.0
150
50
1.5
Output Offset Voltage
(without null)
Rs :s: 10k, Vs = OV,
Va = 2.0V
Analog Voltage
RL;;;' 1k, TA = 25·C
50
1.5
3.0
±11
500
pA
pF
50
mV/s
0.2
mVims
ns
100
3.0
± 11
"'S
V/",s
±20
±10
nA
mV/s
150
100
±20
±10
",A
2.0
0.50
aVOUT = 20V,
Cs = 0,01 ",F
1.5
0.5
20
%
kO
kO
3.0
5.0
Aperture Time
Output Amplifier
Slew Rate
1000
25
0.3
3.0
Leakage Current -
Sample Acquisition
Time
300
20
mV
V
Output Range
±10
±12
±10
±12
RL;;;' 2k
V
Note 1: Unless otherwise noted, these specifications apply for Y+ = + 15Y, Yee = +5Y, Y = -15Y, pin 9 grounded, a 0.01 "F capacHor connected between
pin I and ground over the temperature range - 55'C to + I 25'C for the LH0023, and - 25'C to + 85'C for the LH0023C. All typical values are for TA = 25·C.
5-24
Electrical Characteristics LH0043/LH0043C: (Note 2)
Limits
Parameter
Conditions
LHOO43
Min
Hold (Logic "1 ")
Input Voltage
Hold (Logie "1 ")
Input Current
Typ
2.0
Va = 2.4V
Va = 0.4V
Analog Input
Voltage Range
Supply Current
±10
Vs = OV, Va = 2V, V11 = OV
Vs = OV, Va = O.4V,
VII = OV
Sample Accuracy
VOUT= ±10V(FuIiScale)
DC Input Resistance
Tc = 25°C
1010
Input Current - Is
Typ
Units
Max
V
5.0
5.0
p.A
0.8
0.8
V
1.5
1.5
rnA
±11
±10
20
14
22
18
0.02
0.1
1012
1.0
Input Capacitance
Min
2.0
Sample (Logic "0")
Input Voltage
Sample (Logic "0")
Input Current
LHOO43C
Max
1010
±11
20
14
22
18
rnA
0.02
0.3
%
10.0
nA
50
pA
1.5
1.5
rnA
n
1012
2.0
5.0
V
pF
Leakage Currentpin 1
Vs = ±10V;V11 = ±10,
Tc = 25°C
Vs = ±10V;VII = ±10V
10
25
10
25
2
5
nA
Drift Rate
VOUT = ± 10V, Cs = 0.001 p.F,
Tc = 25°C
10
25
20
50
mVls
Drift Rate
VOUT = ±10V,Cs = 0.001 p.F
10
25
2
5
mVlms
Drift Rate
VOUT = ±10V, Cs = 0.01 p.F,
Tc = 25°C
1
2.5
2
5
mVls
Drift Rate
VOUT = ±10V,Cs = 0.01 p.F
mVlms
Aperture Time
Sample Acquisition
Time
aVOUT = 20V, Cs = 0.001 P. F
aVOUT = 20V, Cs = 0.01 p.F
aVOUT = 5V, Cs = 0.001 p.F
Output Amplifier
Slew Rate
VOUT = 5V, Cs = 0.001 p.F
Output Offset Voltage
(without nUll)
Rs 5: 10k, Vs = OV, Va = OV
1.5
20
1
2.5
0.2
0.5
20
60
20
60
ns
10
30
4
15
50
10
30
4
15
50
p.s
p.s
p.s
3.0
1.5
±40
3.0
Vlp.s
±40
mV
Analog Voltage
±10
±11
±10
±11
V
RL2:1k, TA = 25°C
Output Range
±10
±12
±10
±12
RL 2: 2k
V
Note 2: Unless otherwise noted, these specifications apply for V+ = ±15V, V- = -15V, pin 9 grounded, a 5000 pF capacKor connected between pin I and
ground over the temperature range - 55'C to + 125'C for the LH0043, and - 25'C to + 85'C for the LH0043C. All typical values are for Tc = 25'C.
5·25
Typical Performance Characteristics
2.0
..
::
~.. us
i
~ST1LL AIR WITH CLlP·ON
-
1.J5
HEATSINK
1.&
I
.
"
O.S
D.ZS
2S
50
15
..
~
T. '2S'C
w
ffi
~
t;
"
100
S +lDV ___ LL
01\
,
I
ffi
::; ov
'\I. I I
INPUT"";
t;
1 : -- --1'1.. L
-0 1 2 3 4I 5 6 1 8 9 1 0
150
TEMPERATURE I"CI
I I ~"
I I I I\. ~OUTPUT
'-II
>
... OUTPUT
-r 1
-10
125
;!
I
.. ov
I- T. = 2S'C
w
~ +1GV - -
'\
STILL AIR
v. ·s.ov
~
~,
1.0
I-~s ~ ±1~V I
I-~" O.OI.F
v. ·o.ov
Vs = t15V
c,. =O.OOI.F
-
~ ~
;:: 1.25
Sample Acquisition
Tlm_LH0043
Sample Acquisition
Tim_LH0043
Power D!ssipation
II
INPUT-!
1 1
-10V
rs...
-
I I
I
SI01520253035404550
TIME ",.1
TIME
"'.1
TLIK/5693-2
.
...
~
w
Sample Acquisition
Tlm_LHOO23
100~~
INPUT
>
-S
i
-1'
~
w
+1'
+S
c
!:;
0
>
-s
.
-10
==
~
~
w
l"-
1/
\
~
!
OUll'UT
IJ
I
~
Co·I.Ol.F
TA "Z5°t
VSAMfLj .. 5 ov
1\
/
-4
-&
-I
-10
~VoUT=""0 .
-12
f--
-14
-18
-12V-l0-l-6-4 -2 0 2 4 • • 1012V
20 40 10 10 lID nl 140 110 21D
TIME 1101
lS.0
..
..
I=--
10.0
i..
==
1_
..... :-- Vs =±15V
'\ ""'\
10DO
T. '2S"C
20
2S
0
1.000
)..
o.DDI
100
r-
OUTPUT CURRENT I...AI
15
100
125
Vs" '15
T.' -125
1'\
VOUT
C"
,
I"
1'\
10
""1
.1
.0001
To' 25 C
NI
.001
= ·to
" , l"-
NIL
0.1
CAPACITANCE
'"
I"-
10
I I I
1\.1 I I
D.D!
50
IN
LHODZ3G TA =25·C
D.DODI
30
10.000
LIIIIII23G TA' 125'&
0.1
15
25
Drift vs Capacitance
(LH0043)
1\.1 I
I 1\.1
1 I 1\.
1
10
o
TEMPERATURE I CI
I I I I L
I I I I I
I I I I I
u
•o
'OI~M
Drift vs Capacitance
(LH0023)
0
TA ·,2SOC
//
OUTPUT VOLTAGE IVI
Output Current
. Limiting
~
Pin 1 Leakage Current
vs Temperature
1.
~
..
...
...
Pin 1 Leakage Current
vs Output Voltage
.01
CAPACITANCE
"
10
"'FI
(LH0023)
101M
V
IBM
1/
1M
'i
....
lD010
1Il10
1/
i ,.
g
~
1/
100
0
1
D.
/
1/
".
/
1/
:1/
0.0• .01 0.1 1 10 lDO 1k , •• lOOk 1M 10M 100M .
FREQUENCY IH"
TLlK/5693-3
5-26
r::J:
o
o
Typical Applications
N
(0)
........
How to Build a Sample and Hold Module
rI
I
--I
INPUT
SAMPLE/--'o....c:J
HOLD
lOGIC
INPUT
I
o
o
N
I
I
I
Rl
lDKn
10
LHDD23
OR
LH0043
(0)
o........
r-
::J:
o
o,j:o,
I
11
(0)
........
r-
H ........- -.....-OUTPUT
I
I
I
::J:
_ - - - - -. .---1II....- - - - - V - H5V)
I
ANALOG_+~
r-
::J:
I
I
12
o
o
,j:o,
(0)
o
.---II----+-- v· ("5V)
L-~-~---e~-~~--~---~--GROUND
IL ___________ ..JI
GUARD SHIELD
P.C. BOARD
TLlK/5693-4
Note I: CI is polystyrene.
Note 2: C2, C3, C4 are ceramic disc.
Note 3: Jumper 7-8 and C4 not required for LH0043.
Note 4: R1 optional if zero trim is required.
Forcing Function Setup for Automatic: Test Gear
DIGITAL {
INPUT
CODE
O/A
CONVERTER
CROSS
POINT
MATRIX
DEMULTIPLEXER
AHII015
DEVICE
} PINS
TLlK/5693-5
Data Acquisition System
UH
ANALOG SWITCH
MULTIPLEXUS
AHII015
lHII023
OR
LH0043
AID
CONVERTER
DIGITAL
} OUTPUTS
SlH LOGIC
CHANNEl SElECT
TL/K/5693-11
'See op amp selection guide for details. Most popular types include LH0052, LMI08, LM112, LH0044, LH0036, and LH0038.
5-27
o
C')
-.:I'
o
o
Typical Applications (Continued)
Single Pulse Sampler
:::E:
..J
~
-.:I'
o
o
:::E:
..J
.....
o
ANALOG -
~~~~~
-r--.....,I---.....;~
...- - - - - - - - - - -. .
DIGITAL
OUTPUTS
. .-
C')
N
o
o
:::E:
..J
.....
C')
N
o
o
:::E:
..J
MULTIPLEXER
I
L _ _AHao15
_ _ _ .J
CLOCK
TUK/5693-12
Two Channel Double Sideband Demodulator
1.flJ1..r.JUL r - - - - - - - - - - ,
COM~~~!~ 0-_ _ _ _.5..11:....-1
I
11
I
I
I
L~3_ _
SIGNAL ql OUTPUT
I
-oJ
1
~C'
sr----------l
~I--I.
111
I
I
I
SIGNAL =2 OUTPUT
TUK/5693-13
5-28
r--------------------------------------------------------------------------------,
1.0 DRIFT ERROR MINIMIZATION
In order to minimize drift error, care in selection of Cs and
layout of the printed circuit board is required. The capacitor
should be of high quality Teflon, polycarbonate, or polysty·
rene construction. Board cleaniness and layout are critical
particularly at elevated temperatures. See AN·63 for de·
tailed recommendations. A guard conductor connected to
the output surrounding the storage node (pin 1) will be help·
ful in meeting severe environmental conditions which would
otherwise cause leakage across the printed circuit board.
2.0 CAPACITOR SELECTION
The size of the capacitor is dictated by the required drift rate
and acquisition time. The drift is determined by the leakage
dV
IL
current at pin 1 and may be calculated by - = - , where IL
dt
Cs
is the total leakage current at pin 1 of the device, and Cs is
the value of the storage capacitor.
2.1 Capacitor Selection - LH0023
At room temperature leakage current for the LH0023 is ap·
proximately 100 pA. A drift rate of 10 mVlsec would require
a 0.01 IJ.F capacitor.
For values of Cs up to 0.01 IJ.F the acquisition time is limited
by the slew rate of the input buffer amplifier, A 1, typically 0.5
VI ".S. Beyond this point, current availability to charge Cs
also enters the picture. The acquisition time is given by:
tA""
r-
:::E:
c
Applications Information
2AeoRCs=2X10-3~Ae RC
0.5 x 106
0
S
amplifier, but it will not be available at the output). For larger
values of storage capaCitance, the limitation is the current
sinking capability of the input amplifier, typically 10 mAo With
Cs = 0.01 IJ.F, the slew rate can be estimated by
dV
dt
10-10-3
0.01 _ 10 6 = 1VI".s or a slewing time for a 5 volt
signal change of 5".s.
3.0 OFFSET NULL
Provision is made to null both the LH0023 and LH0043 by
use of a 10k pot between pins 3 and 4. Offset null should be
accomplished in the sample mode at one half the input volt·
age range for minimum average error.
4.0 SWITCHING SPIKE MINIMIZATION-LH0043
A capacitive divider is formed by the storage capaCitor and
the capacitance of the internal FET switch which causes a
small error current to be injected into the storage capacitor
at the termination of the sample interval. This can be con·
sidered a negative DC offset and nulled out as described in
(3.0), or the transient may be nulled by coupling an equal
but oppOSite signal to the storage capacitor. This may be
accomplished by connecting a capacitor of about 30 pF (or
a trimmer) between the logic input (pin 6) and the storage
capaCitor (pin 1). Note that this capaCitor must be chosen as
carefully as the storage capacitor itself with respect to leak·
age. The LH0023 has switch spike minimization circuitry
built into the device.
C
N
.....
rCIo)
:::E:
c
C
N
CIo)
n
.....
r-
:::E:
c
C
-Ilooo
.....
rCIo)
:::E:
c
C
-Ilooo
CIo)
n
5.0 ELIMINATION OF THE 5V LOGIC SUPPLY - LH0023
where: R = the internal resistance in series with Cs
Aeo = change in voltage sampled
An average value for R is approximately 600 ohms. The
expression for tA reduces to:
~AeoCs
tA""~
The 5V logic supply may be eliminated by shorting pin 7 to
pin 8 which connects a 10k dropping resistor between the
+15V and Ve. Decoupling pin 8 to ground through 0.1 ".F
disc capaCitor is recommended in order to minimize tran·
sients in the output.
6.0 HEAT SINKING
For a -10V to +10V change and Cs =.05 ".F, acquisition
time is typically 50 ".S.
2.2 CapaCitor Selection- LH0043
At 25'C case temperature, the leakage current for the
LH0043G is approximately 10 pA, so a drift rate of 5 mVls
would require a capacitor of Cs = 10-1012 /5-10 3 = 2000
pF or larger.
For values of Cs below about 5000 pF, the acquisition time
of the LH0043G will be limited by the slew rate of the output
amplifier (the signal will be acquired, in the sense that the
voltage will be stored on the capaCitor, in much less time as
dictated by the slew rate and current capacity of the input
The LH0023 and LH0043G may be operated without dam·
age throughout the military temperature range of - 55 to
+ 125'C ( - 25 to + 85'C for the LH0023CG and
LH0043CG) with no explicit heat sink, however power dissi·
pation will cause the internal temperature to rise above am·
bient. A simple clip·on heat sink such as Wakefield
#215-1.9 or equivalent will reduce the internal tempera·
ture about 20'C thereby cutting the leakage current and drift
rate by one fourth at max. ambient. There is no internal
electrical connection to the case, so it may be mounted
directly to a grounded heat sink.
7.0 THEORY OF OPERATION-LH0023
The LH0023/LH0023C is comprised of input buffer amplifi·
er, A 1, analog switches, S1 and 52, a TTL to M05 level
5·29
III
Applications Information
(Continued)
translator, and output buffer amplifier, A2. In the "sample"
mode, the logic input is raised to logic "1" (Vs :S: 2.0V)
which closes 81 and opens 82. 8torage capacitor, Cs , is
charged to the input voltage through 81 and the output
slews to the input voltage. In the "hold" mode, the logic
input is lowered to logic "0" (VS :S: 0.8V) opening 81 and
closing 82. Cs retains the sample voltage which is applied to
the output via A2. 8ince 81 is open, the input signal is overriden, and leakage across the M08 switch is therefore minimized. With 81 open, drift is primarily determined by input
bias current of A2, typically 100 pA at 25°C.
7.1 Theory of Operation-LH0043
The LH0043/LH0043C Is comprised of Input buffer amplifier
A1, FET switch 81 operated by a TTL compatible level
translator, and output buffer amplifier A2. To enter the
"sample" mode, the logic input is taken to the TTL logic "0"
state (Vs=0.8V) which commands the switch 81 closed
and allows A 1 to make the storage capacitor voltage equal
to the analog input voltage. in the "hold" mode (Vs=2.0V),
81 is opened isolating the storage capacitor from the input
and leaving it charged to a voltage equal to the last analog
input voltage before entering the hold mode. The storage
capaCitor voltage is brought to the output by low leakage
amplifier A2.
8.0 DEFINITIONS
V5: The voltage at pin 5, e.g., the analog input voltage.
Vs: The voltage at pin 6, e.g., the logic control input signal.
V11: The voltage at pin 11, e.g., the output signal.
TA: the temperature of the ambient air.
Tc: The temperature of the device case at the center of
the bottom of the header.
Acquisition Time:
The time required for the output (pin 11) to settle within the
rated accuracy after a specified input change is applied to
the input (pin 5) with the logic input (pin 6) in the low state.
ANALOG
I"'UT
Aperture Time:
The time indeterminacy when switching from sample mode
to hold including the delay from the time the mode control
signal (pin 6) passes through its threshold (1.4 volts) to the
time the circuit actually enters the hold mode.
LOGIC
IIIPUT
ANALOG
OUTPUT
TL/K/5693-7
Output Offset Voltage:
The voltage at the output terminal (pin 11) with the analog
input (pin 5) at ground and logic input (pin 6) in the "sample"
mode. This will always be adjustable to zero using a 10k pot
between pins 3 and 4 with the wiper arm returned to V-.
5-30
!I:
o
o
'?A National
U1
~ Semiconductor
Co)
.......
r-
::J:
o
o
LH0053/LH0053C High Speed
Sample and Hold Amplifier
U1
Co)
(")
General Description
Features
The LH0053/LH0053C is a high speed sample and hold
circuit capable of acquiring a 20V step signal in under
5.0,...s.
•
•
•
•
•
•
The device is ideally suited for a variety of high speed data
acquisition applications including analog buffer memories
for A to 0 conversion and synchronous demodulation.
Sample acquisition time 10 ,...s max. for 20V signal
FET switch for preset or reset function
Sample accuracy null
Offset adjust to OV
DTL/TTL compatible FET gate
Single storage capacitor
Schematic and Connection Diagrams
ANALOG
INPUT
4
Metal Can Package
STORAGE
CAPACITOR
FEEDBACK
OFFSET
ADJUST
FEEDBACK ;---...
Rl
STORAGE
CAPACITOR
10
OUTPUT
N.C.
GATE 1
TL/H/9251-2
GND
Top View
TL/H/9251-1
Order Number LH0053G or
LH0053CG
See NS Package Number G12B
AC Test Circuit
Acquisition Time Test Circuit
20k.o.
47k.o.
sro~ot----t----------r_-_~
______________________~--i
......-_ _-1 CF
p----- ----.----.------ --------1
3
47k.o.
IN
,
:
4' 10k.o.
II
10kn.
ot------!-,-1\1"""'--1
12'
,
+15V ()---t
10'
-15V ~~--r'I;.;.I.....-o OUTPUT
I
ILH0053
S/H
LOGIC
.. _--------------6
0------------::..1
9
TL/H/9251-6
Applications Information
SOURCE IMPEDANCE COMPENSATION
The drift is dictated by leakage current at pin 5 and is given
by:
The gain accuracy (linearity) of the LH0053/LH0053C is set
by two internal precision resistors. Circuit applications in
which the source impedance is non-zero will result in a
closed loop gain error, e.g. if Rs = 100, a gain error of
0.1 % results. Figures 1 and 2 show methods for accommodating non-zero source impedance.
~=.!b.
dt
CF
Where IL is the leakage current at pin 5 and CF is the value
of the capacitance. The room temperature leakage of the
LH0053 is typically 6.0 pA, and a 1000 pF capacitor will
yield a drift rate of 6.0 mV per second.
For values of CF below 1000 pF, acquisition for the LH0053
is primarily governed by the slew rate of the input amplifier
(20 VI ,,"s) and the setting time of the output amplifier
("" 1.0 ,,"s). For values above CF = 1000 pF, acquisition
time is given by:
DRIFT ERROR MINIMIZATION
In order to minimize drift error, care in selecting CF and
layout of the printed circuit board are required. The capacitor should be of high quality teflon, polycarbonate, or polystyrene construction. Board layout and clean lines are critical particularly at elevated temperature.
A ground guard (shield) surrounding pin 5 will minimize leakage currents to and from the summing junction, arising from
extraneous signals. See AN-63 for detailed recommendations.
Where:
CF = The value of the capacitor
t:. V = The magnitude of the input step, e.g. 20V
CAPACITOR SELECTION
The size of the capacitor is determined by the required drift
rate usually at the expense of acquisition time.
IDSS = The ON current of switch 01 "" 5.0 mA
tS2 = The setting time of output amplifier "" 1.0
.------1
Cr
3
.---- -----------------5 ---------R2
Rl
4
RS
11
._--------------------- --------_ ..
I
LH0053
TL/H/9251-7
FIGURE 1. Non-Zero Source Impedance Compensation
5-34
""S
r-
::J:
Applications Information (Continued)
CI
CI
U1
....-----1
3
.....
rCo)
CF
::J:
5
CI
CI
U1
Co)
o
11
.---------------------- ---------_.
9
TL/H/9251-B
FIGURE 2. Non-Zero Source Impedance Buffering
GATE INPUT CONSIDERATIONS
5.0V TTL Applications
Vee 5.0V TO 15V
The LH0053 Gate input (pin 6) will interface directly with
5.0V TTL. However, TTL gates typically pull up to 2.5V in
the logic "1" state. It is therefore advisable to use a 10 kO
pull-up resistor between the 5.0V, Vee, and the output of
the gate as shown in Figure 3.
To obtain the highest speed and fastest acquisition time, the
gate drive shown in Figure 6 is recommended.
A INPUT
+5.0V
10 kD.
6r----.
TL/H/9251-10
JO--+-~
FIGURE 4. CMOS Logic Compatibility
HEAT SINKING
LH0053
The LH0053 may be operated over the military temperature
range, - 55°C to + 125°C, without incurring damage to the
device. However, a clip on heat sink such as the Wakefield
215 Series or Thermalloy 2240 will reduce the internal temperature rise by about 20°C. The result is two-fold improvement in drift rate at an ambient temperature of 25°C.
TUH/9251-9
FIGURE 3_ TTL Logic Compatibility
CMOS APPLICATIONS
Since the case of the device is electrically isolated from the
circuit, the LH0053 may be mounted directly to a grounded
heat sink.
The LH0053 gate input may be interfaced directly with 74C,
CMOS operating off of Vee's from 5.0V to 15V. However,
transient currents of several milliamps can flow on the rising
and falling edges of the input signal. It is, therefore, advisable to parallel the outputs of two 54C/74C gates as shown
in Figure 4.
POWER SUPPLY DECOUPLING
Amplifiers A 1 and A2 within the LH0053 are very wide band
devices and are sensitive to power supply inductance. It is
advisable to bypass V+ (pin 12) and V- (pin 10) to ground
with 0.1 ",F disc capacitors in order to prevent oscillation.
It should be noted that leakage at pin 5 in the hold mode will
be increased by a factor of 2 to 3 when operating into 1 5V
logic levels.
5-35
•
Applications Information (Continued)
Should this procedure prove inadequate, the disc capacitors
should be paralleled with 4.7 p.F solid tantalum electrolytic
capacitors.
DC OFFSET ADJUST
Output offset error may be adjusted to zero using the circuit
shown in Figure 5. Offset null should be accomplished in the
sample mode rye ,;; 0.5V) and analog input (pin 4) equal to
zero volts.
,
4'
,,
Rl
,II
>-r-....
-o OUTPUT
,
'LH0053
• - - -101 - - - - - - - - -
+15V
6
-
TUH/9251-11
FIGURE 5. Offset Null Circuit
+5V
2kD.
....--TOPIN 6
1 kD.
TLlH/9251-12
FIGURE 6. High Speed Gate Drive Circuit
Definition of Terms
Voltage V4: The voltage at pin 4, i.e., the analog input voltage.
Aperture Time: The time indeterminacy when switching
from the "sample" mode to the HOLD mode measured from
the time the logic input passes through its threshold (2.0V)
to the time the device actually enters the HOLD mode.
Sample Accuracy: Difference between input voltage and
output voltage while in the sample mode, expressed as a
percent of the input voltage.
Voltage V6: The voltage at pin 6, i.e., the logic control signal. A logic "1" input, Ve ,;; 4.5V, places the LH0053 in the
HOLD mode; a logic "0" input (Ve ,;; 0.5V) places the device in sample mode.
Acquisition Time: The time required for the output (pin 11)
to settle within the rated accuracy after a specified input
change is applied to Analog Input 1 (pin 4) with logic input,
(pin 6) in the logic "0" state.
5-36
,------------------------------------------------------------------------, r
::J:
~
co
~National
en
~ Semiconductor
Q
LH4860
Super Fast 12-Bit Track-Hold Amplifier
General Description
Features
The LH4860 is an extremely fast high resolution SampleHold (track-and-hold) amplifier. It guarantees acquisition
time and sample-to·hold settling time to ± 0.01 %. The
LH4860 will acquire a full10V signal to ±0.01% full scale
(or ± 1 mY) in less than 200 ns. The bandwidth of the tracking amplifier is 16 MHz. In the track mode, offset error is
typically ±0.5 mV and gain error is typically ±0.05%. The
LH4860 is precisely laser trimmed for pedestal compensation. The "Hold" capacitor is internal for ease of use. Also,
the bypassing power supply capacitors are inside the package.
• 200 ns max acquisition time 10V step to ±0.01% FS
• 100 ns max sample-to-hold settling time
• ± 50 ps aperture jitter
• 74 dB feedthrough attenuation
• TTL compatible
• Direct replacement for HTC-0300, 4860, and HS9720
Applications
•
•
•
•
•
Transient recorders
Fast fourier analysis
High speed DAS's
High speed DDS's
Analog delay and storage
Block and Connection Diagrams
1 k4
GROUND
COM~2lig
GROUND
12
10~
TUK/9770-2
Analog Output
1
24
+15V Supply
Nle
Nle
Nle
Nle
Nle
Nle
Nle
2
3
4
5
23
Ground
22
-15V Supply
Ground
Nle
Nle
Nle
17 Nle
16 Nle
+5V Supply
Digital Ground
15
Hold Command
III
Ground
14
Nle
13
Analog Input
TL/K/9770-1
Top View
Dual-In-Llne Metal Package (D)
Order Number LH4860D or LH4860CD
See NS Package Number 0241
5-37
C)
...
CD
CIO
:::t:
....I
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor sales
Office/Distributors for availability and specifications.
Supply Voltage (Vs+ and Vs-)
±18V
Logic Supply Voltage (Vo)
Analog Input Voltage
Digital Input Voltage
Output Short Circuit Duration
+7V
±Vs
-0.5Vto +5.5V
Output Current (Note 1)
±65mA
DC Electrical Characteristics Vs "'=
Continuous
Operating Temperature Range
LH4860C
LH4860
- 25°C to + 85°C
- 55°C to + 125°C
Storage Temperature Range
- 65°C to + 150°C
Power Dissipation (Po)
(See Graph)
2.4W
ESD(Note6)
TBD
±15Vand +5V, TA = + 25°C. unl~ssotherwise noted (Note 1)
LH4860C/LH4860
Symbol
Paramet"r
Conditions
Input/Output
Voltage Range
Input Impedance
Output Current
Design
Limit
(Note 9)
Units
(Max Unless
Otherwise
Stated)
Typ
Tested
Limit
(Note 8)
±11.5
±10.25
V (Min)
40
rnA
1
(Note 1)
kO
Output Impedance
0.1
0
Maximum Capacitive
Load
150
pF
Logic High "1"
Logic Low "0"
(Note 2)
(Note 2)
2.0
V (Min)
5.0
V
0
V (Min)
0.8
Digital Input Loading
V
1
TTL Load
Gain
-1.00
Gain Accuracy
±0.05
±0.2
0/0
Gain Linearity
Error (Note 4)
±0.003
±0.01
O/OFS
mV
V/V
Offset Voltage
Sample Mode
±0.5
±5
Hold Step
Pedestal Figure 1
±2.5
±20
Gain Drift
(Note 7)
Offset Drift
Sample Mode
(Note 4)
5·38
mV
±0.5
±5
ppm of
FSR/oC
±3
±15
ppm of
FSRI"C
r
AC Electrical Characteristicsvs =
::I:
LH4860C/LH4860
Symbol
Parameter
Acquisition
Time (Notes 4, 5)
Settling Time Sample
to Hold (Note 4)
Tested
Limit
(Note 8)
1OV Step to ± 0.01 %
FS (±1 mY)
150
200
ns
10V Step to ±0.1 %
FS(±10 mY)
100
170
ns
1OV Step to ± 1%
FS (±100 mY)
90
ns
lVStepto ±1%
FS (±100 mY)
75
ns
to ± 0.01 % FS (1 mY)
60
to ±0.1% FS (10 mY)
40
ns
180
mVp_p
Aperture Delay Time
100
Design
Limit
(Note 9)
CO
Units
(Max Unless
Otherwise
Stated)
Typ
Conditions
Sample to Hold
Transient
ns
6
ns
Aperture Jitter
±50
ps
Output Slew Rate
300
V/).ts
16
MHz
Small Signal
Bandwidth (-3 dB)
±0.5
Droop Rate
Feedthrough
PSRR
.&:ao
±15Vand +5V, TA = + 25'C, unless olherwise noted (Note 1)
).tV/).ts
±55
).tV/).ts
+125'C
±1.2
mV/).ts
74
dB
±0.5
mVIV
2.5 MHz, 20 Vp_p
Input
Power Supply
Rejection Ratio
Quiescent Current
Drain
±5
+85'C
+15VSupply
21
25
mA
-15V Supply
-22
-25
mA
+5VSupply
Power Consumption
17
25
mA
730
875
mW
Note 1: The LH4860 output is current limited at approximately ±65 rnA and the unit can withstand a sustained short-ta-ground. For normal operation, load current
should not exceed ± 40 rnA.
Note 2: See Application Information for use of Hold and Hold inputs.
Note 3: The Hold Command inputs appear as one TTL load and are defined as sinking 40 p.A with logic "1" applied and sourcing 1.6 rnA with logic "0" applied.
Note 4: FS means "Full Scale" and is equivalent to 10V. FSR means "Full Scale Range" and is equivalent to 20V. For a l2·bit system, 1 LSB ~ 0.024% FS.
Note 5: Acquisition time is tested with no load.
Note 6: The test circuit used consists of the human body model of 100 pF in series with 1500f!.
Note 7: Boldface limits are guaranteed over full temperature range. Operating ambient temperature range of LH4860C is - 2S"C to + 8S"C, and LH4860 is - SS"C
to +12S"C.
Note 8: Tested limits are guaranteed and 100% production tested.
Note 9: Design limits are guaranteed (but not production tested) over the indicated temperature or temperature range. These limits are not used to calculate
outgoing quality level.
5-39
en
o
tRACK MODE
HOLD MODE
TUK/9770-5
FIGURE 1. Timing Diagram
Typical Performance Characteristics
Track Mode Gain
and Phase
Maximum Power Dissipation
Final Voltage Accuracy vs
Acquisition Time
3
l-
1.0
CASE
I
i'"
D.8
I -,.... ']c=..60C/N
1000
900
fl-
'~:~/N t'...
II
1
450
J
!
;f
1\ AV,N=10V-r-!
100
~
I
'iii
il!
D.2
o
o
~
"
10
1
0.1
50
100
150
10
0.1
Tempenllure (ac)
o
100
Frequency (MHz)
100
20D
TIm. (n...)
TL/K/9770-3
16
14
12
~
10
I
0
0.1
10
100
Input Signal Slew Ralo (V/1"')
1000
TL/K/9770-4
FIGURE 2. Accuracy Error Due to a ± 50 ps Aperture Jitter at 10V Full Scale
Application Information
logic supply needs to be well bypassed. Although both + 5V
and ± 15V are internally decoupled with 0.001 ",F, in critical
applications, additional bypass capaCitors are recommend·
ed (0.1 ",F-l ",F tantalum).
LAYOUT
The LH4860 is constructed in a way that with proper care in
the layout it will meet its specifications without additional
external components.
A large analog ground plane will provide uniform ground
potential to the four ground pins (Pin 10, 15, 21 and 23).
These pins should be connected to the ground plane with
minimum lead length. Any difference in ground potential,
due to ground current, will degrade the performance of the
device.
LOGIC COMMANDS
A TTL logic "0" on Pin 11 (or a logic "I" on Pin 12) will put
the LH4860 into the sample (track) mode. In this mode, the
device acts as an inverting unity gain amplifier, and its out·
put will track the input.
A logic "I" on Pin 11 and logic "0" on Pin 12 will put the
device into the hold mode, where the output will be held
constant at the level present when the command was given.
The analog and digital grounds of the LH4860 should be
connected together close to the device. The + 5V digital
5·40
~----------------------------------------------------------~r
Application Information
....
::J:
(Continued)
(X)
Unused logic pins need to be tied to a fixed logic level.
When Pin 11 is used, then Pin 12 must be tied to ground;
when Pin 12 is used as logic input, Pin 11 is to be tied to
+ 5V through 1 kn.
maximum allowable rate of change, the frequency that can
be converted accurately becomes:
Pin 12
(Hold)
State
0
0
1
1
0
1
0
1
Track
Track
Hold
Track
In the tracking mode, the Track-Hold Amplifier operates as
an inverting amplifier with unity gain. It is limited by its small
signal bandwidth, typically 16 MHz, and the power bandwidth, typically 4.8 MHz.
f _ 12.2V/",s_
21T5V - 338 kHz
The fact that the LH4860 can digitize the fastest part of a
338 kHz sine wave does not mean it can digitize that signal
for reconstruction purposes. Realistically a sample can only
be taken in the time it takes to acquire (200 ns for the
LH4860) plus the conversion time of the ADC.
LOADING
Some restrictions on the output load apply to avoid oscillations and performance variations over temperature .
. .. Recommended load resistance is 500n or above and
capacitance up to 50 pF; load resistance down to 250n can
be used without degrading the performance. Capacitive
loads up to 150 pF will be free of oscillations, but acquisition
and settling times will be extended due to slew rate limitations in the output.
Other Considerations for Using the
LH4860 with AID Converters
There are several considerations for good match between
track hold amplifier and AID. One is that the output resistance of the T IH should be low compared to the input resistance of the AID, up to frequencies 5 times the clockrate of
the AID. This is because of the digital nature of a successive approximation AID its internal DI A changes its output
momentarily and current transients occur at the AID input.
These should be sunk and settled before the next bit conversion. In the hold mode, the LH4860 has a typical output
resistance of 0.1 n; its output, typically, recovers to ±0.01 %
from 2 mA step in less than 100 ns.
APERTURE JITTER
In a typical DSP Application, an analog signal needs to be
digitized. This can be done with an AID Converter; which
has the limitation that the Signal needs to be fairly constant
throughout the conversion time, therefore, only low frequency signals can be converted without loss of accuracy. To
handle faster signals, a Track-Hold Amplifier can be used in
front of the AID.
Another consideration is the LH4860's track-to-hold transient settling time. Normally, the same timing pulse that initiates "hold" also starts the AID conversion. The decision for
the AID's MSB, normally, takes place one clock cycle after
the start signal, and at that time, the track-hold command
pin can be driven directly (or inverted) from the successive
approximation AID's conversion status output. During conversion the T IH is in hold.
In order not to lose accuracy, the standard rule of thumb is
that the input Signal should not change more than ± % LSB
during the conversion time. This determines the maximum
frequency for accurate conversion.
For example, take a 12-bit 10 "'S AID Converter. If it is
operated on a OV to 10V input range, 1 LSB is equivalent to:
10V
212
10V
= 4096 = 2.44 mV
Many sampling AID converter applications require that a
signal be sampled fast but held for a long time so that a
slow (inexpensive) AID converter may be used. Such conflicting requirements place stringent demands on a S/H amplifier. Fortunately, cascading two S/H amplifiers, as in Figure 3, solves the problem. The LH4860 acquires the signal
to within 0.01 % F.S. in under 200 ns and holds it until the
LH0023 acquires the sampled signal. The low droop rate of
LH0023 allows it to hold the sampled signal to within 0.Q1 %
for as long as the conversion time of ADC1210 (100 ",s).
Note that the start pulse for the AID converter should occur
at the end of LH0023's hold mode settling time. Figure 3'5
circuit accepts a OV to - 5V full scale input signal and produces a complementary binary output. A typical timing dia-
and % LSB is 1.22 mV. The maximum allowable rate of
change becomes:
dV
% LSB
dt
Conversion Time
-=
..
For a sinewave of vet)
of change vs. time.
1.22 mV
= - - - = 122 VIs
10 "'S
= A sine 21T ft, the derivative is a rate
dv(t)
dt
=
Q
122 VIs
f = - - - = 3.9 Hz
21T5V
If a track-hold amplifier is used in front of the AID, then
much faster signals can be accurately digitized. In this case,
the input waveform has to be repetitive, and the hold pulse
is shifted in phase every time a new conversion is made,
until the whole signal has been captured. The limitation for
accuracy is determined by the aperture jitter, which is the
uncertainty of the moment when the signal is frozen. In
this case, the maximum slew rate is 1.22 mV1100 ps = 12.2
VI "'S and the highest frequency at which accurate conversion occurs becomes:
Each Pin 11 or 12 represents one TTL load to the drive
circuit.
Pin 11
(Hold)
m
21Tf A Cos (21T ft)
The extreme value of this is at t = 0, and the maximum rate
of change becomes 21TfA.
If the sinewave is chosen for 10 Vp_p, or A = 5V, the maximum rate of change becomes 101Tf. If this is equated to the
5-41
•
Applications
+15V
+5V
-15V
!
ADC INPUT
11
24r---.....;...............................;................
CLOCK
CC
14
13
200k
-15V S/H2
S/Hl
TTL OUTPUTS
lk
START COMMAND
TL/K/9770-6
'Polystyrene Cap 0.Q1 I'F
FIGURE 3. Sampling AID Converter
SAMPLE
S/Hl
(LH4860)
----I~~HOL~Dl
Jt_\1
--11-\2
S/H2
(LH0025)
SAMPLE
---JI
3l~\3~n~HDLD
I
l\4
/-\5----1
0
1
11 12
t1 = S/H1 acquisition time = 200 ns
12 ~ S/HI hold mode settling lime ~ 100 ns
t3 = S/H2 acquisition time = 20 Ils
4 ~ S/H2 hold mode settling lime ~ lSI'S
ts = Conversion time of AOC1210 = 100,...5
Is ~ Clock period ~ 7.71's
t7 = Start pulse setup time = 30 ns
Ie ~ Slart pulse widlh ~ 1051's
t9 = Conversion complete time = 5 JLs
110 ~ Sampling period ~ 13 + 4 + Is + 17
~ 1351'S
1
Is ~ ~ ~ 7.4 kHz
CLOCK
START
COMMAND
CONVERTING
STATUS
\9
(cc)
i + - - - - T10 - - - - f >
CONVERSION
COMPLm
TL/K/9770-8
FIGURE 4. Typical Timing Diagram for the Sampling AID Converter
(Not Drawn to Scale)
gram for
sampling
the input
3.52 kHz
the sampling AID converter (Figure 4) shows a
frequency of 7.4 kHz, thus from Nyquist criteria,
signal's maximum frequency should be limited to
(Le., half the sampling frequency). This circuit is
well suited for capturing fast single shot events as well as
repetitive signals and for operation at elevated temperatures at which the increased droop rate of LH4860 is compensated for by the low droop rate of LH0023.
5-42
Applications (Continued)
+15V
ANALOG
INPUTS
DG187AA
11
(5ILICONIX)
10
1 Mil
5/H
CONTROL
-15V
TLlK/9770-7
FIGURE 5. Fast Data Acquisition Using Ping-Pong Switching
goes into hold mode and a new conversion can begin at the
end of 8tH2's hold mode settling time, 8tH1 now goes into
the sampling mode. This approach thus eliminates the
8tH's acquisition time from the system's overall cycle time.
Note that DG187AA's typical switch on and off times are
less than the 100 ns hold mode settling time of the LH4860.
Consequently, switching the 8tH's output to the output
channel at the instant the 8tH goes from sample to hold
mode eliminates the switch delay because the ADC's conversion does not begin until after the LH4860's hold mode
settling time of 100 ns. Neglecting the minimal delay
through LH0033G, a sampling interval of 1100 ns can be
achieved, this is only a 10% increase over the minimum
available sampling interval. It should be noted that since
LH0033 and LH4860 do not have preCisely unity gain, they
introduce gain error in addition to voltage offset. The gain
error and offset of the entire system can, however, be
trimmed out by the ADC's gain and offset trim circuits. The
circuit in Figure 5 accepts -5V to +5V input signals and
produces an inverted output. The circuit described is ideally
suited for interface with flash ADCs having sub-microsecond conversion times, and, taking advantage of the pingpong switching scheme allows significant improvement in
system throughput compared to a single 8tH and ADC
combination.
For ultrafast AID converters with conversion time in the microsecond region, the 8tH's acquisition and hold mode settling time can contribute significantly to the system's overall
cycle time thus reducing system throughput. For example,
ADC can add as
an LH4860 at the front end of a 12-bitl1
much as 300 ns to the converter's conversion time thus
increasing the sampling interval to 1300 ns; a 30% increase. However, by using two 8tH amplifiers in a pingpong switching configuration, the system's cycle time can
be decreased to very nearly that of the ADC. Figure 5 shows
an ultrafast multi-channel data acquisition system. The
AH0015 Mux allows the selection of 1 of 4 input signals in a
process monitor application. Note that a logic "1 " at
AH0015's logic control pin closes the corresponding switch.
8ince LH4860's input impedance is only 1 kl1, LH0033 buffers the input signal so as to prevent the 8tH from loading
the signal source, a 1 MI1 resistor at the buffer's input prevents the buffer's output from saturating when all Mux
switches are open. The ping-pong switching scheme involves the use of a fast 8PDT switch (DG187AA) to select
the output of each 8tH for half the sampling period. Thus,
8tH1 's output is selected when 8tH1 is in the hold mode,
the ADC meanwhile begins conversion. While the ADC is
converting, 8tH2 is acquiring a new sample of the input
signal. As soon as the ADC's conversion is complete, 8tH2
,..S
III
5-43
Section 6
Temperature Sensors
Section 6 Contents
Temperature Sensors Selection Guide. .... . ..... .... .. ........ . . .. . .... ... ........ ...
LM34/LM34A1LM34C/LM34CAlLM34D Precision Fahrenheit Temperature Sensors .......
LM35/LM35A1LM35C/LM35CAlLM35D Precision Centigrade Temperature Sensors. . . . . . .
LM135/LM235/LM335/LM135A1LM235A1LM335A Precision Temperature Sensors. . . . . . . .
LM3911 Temperature Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-2
6-3
6-4
6-12
6-21
6-30
';;j
3
~NatiOnal
't:J
CD
a
Semiconductor
c
~
en
CD
Temperature Sensor
Selection Guide
:J
fII
o
~
en
CD
CD
(')
O·
Part
Temp. Range
"Accuracy
Output Scale
LM34A
LM34
LM34CA
LM34C
LM34D
-50'Fto
-50'Fto
-40'Fto
-40'Fto
+32'Fto
+300'F
+300'F
+230'F
+230'F
+212'F
±2.0'F
±3.0'F
±2.0'F
±3.0'F
±4.0'F
10 mVI'F
10 mVI'F
10 mVI'F
10 mVI'F
10mV/'F
LM35A
LM35
LM35CA
LM35C
LM35D
-55'C to + 150'C
- 55'C to + 150'C
-40'Cto +110'C
-40'Cto +110'C
O'C to + 100'C
±1.0'C
±1.5'C
± 1.0'C
±1.5'C
±2.0'C
10 mVI'C
10mV/'C
10mVI'C
10 mVI'C
10mV/'C
LM134-3
LM134-6
LM234-3
LM234-6
- 55'C to
- 55'C to
- 25'C to
-25'Cto
+ 125'C
+ 125'C
+ 100'C
+100'C
±3.0'C
±6.0'C
±3.0'C
±6.0'C
ISET oc
LM135A
LM135
LM235A
LM235
LM335A
LM335
- 55'C to
- 55'C to
-40'Cto
-40'Cto
- 40'C to
-40'C to
+ 150'C
+ 150'C
+ 125'C
+ 125'C
+ 100'C
+ 100'C
±1.3'C
±2.0'C
±1.3'C
±2.0'C
±2.0'C
±4.0'C
10 mV/'k
10mVI'k
10 mVl'k
10 mV/'k
10mVI'k
10mV/'k
LM3911
-25'Cto +85'C
±10.0'C
10 mV/'k (or 'F)
:J
Ci)
C
a:
CD
'k
'k
oc 'k
oc 'k
ISET oc
ISET
(SET
·Note: Accuracy is measured over T(Min) to T(Max) uncalibrated
Nole: The LM134/234/334 3·Terminal Adjustable current sources Datasheet can be found in Linear 1, Section 1.
•
6-3
J?)I National
~ Semiconductor
LM34/LM34A/LM34C/LM34CA/LM34D
Precision Fahrenheit Temperature Sensors
General Description
The l.M34 series are precision integrated-circuit temperature sensors, whose output voltage is linearly proportional to
the Fahrenheit temperature. The LM34 thus has an advantage over linear temperature sensors calibrated in degrees
Kelvin, as the user is not required to subtract a large constant voltage from its output to obtain convenient Fahrenheit scaling. The LM34 does not require any external calibration or trimming to provide typical accuracies of ± V2F at
room temperature and ± 1%'F over a full - 50 to + 300'F
temperature range. Low cost is assured by trimming and
calibration at the wafer level. The LM34's low output impedance, linear output, and precise inherent calibration make
interfacing to readout or control circuitry especially easy. It
can be used with single power supplies or with plus and
minus supplies. As it draws only 70 p.A from its supply, it has
very low self-heating, less than 0.2'F in still air. The LM34 is
rated to operate over a -50' to +300'F temperature
range, while the LM34C is rated for a -40' to +230'F
range (O'F with improved accuracy). The LM34 series is
available packaged in hermetic TO-46 transistor packages,
Connection Diagrams
while the LM34C is also available in the' plastic TO-92 transistor package. The LM34 is a complement to the LM35
(Centigrade) temperature sensor.
Features
•
•
•
•
•
•
•
•
•
•
•
Calibrated directly in degrees Fahrenheit
Linear + 10.0 mV I'F scale factor
1.0'F accuracy guaranteed (at + 77'F)
Rated for full - 50' to + 300'F range
Suitable for remote applications
Low cost due to wafer-level trimming
Operates from 5 to 30 volts
Less than 70 p.A current drain
Low self-heating, 0.18'F in still air
Nonlinearity only ± 0.5'F typical
Low-impedance output, 0.4,(1 for 1 mA load
Typical Applications
TO-46
Metal Can Package'
+V,
IHVTO +20V)
$-.MQ'U.M
TL/H/6685-3
TLiH/6685-1
FIGURE 1. Basic Fahrenheit Temperature Sensor
( + 5' to + 300'F)
·Case is connected to negative pin.
Order Numbers LM34H, LM34AH,
LM34CH, LM34CAH or LM34DH
See NS Package Number H03H
+Vs
CHOOSE A, = (- Vs)/50 p.A
TO-92
Plastic Package
BOTTOM VIEW
VOUT
VOUT= +3,000 mVAT +300°F
= + 750 mV AT + 75°F
= -500 mV AT -50°F
TL/H/6685-4
TLiH/6685-2
FIGURE 2. Full-Range Fahrenheit Temperature Sensor
Order Number LM34CZ or LM34DZ
See NS Package Number Z03A
6-4
Absolute Maximum Ratings (Note 10)
Lead Temp. (Soldering, 10 seconds)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
+35Vto -0.2V
Output Voltage
+6Vto -1.0V
Output Current
10mA
-76'Fto +356'F
TO-92 Package
-76'Fto +300'F
+300'C
TO-92 Package
+ 260'C
Specified Operating Temp. Range (Note 2)
TMINtoTMAX
-50'Fto +300'F
LM34, LM34A
Storage Temperature,
TO-46 Package
TO-46 Package
LM34C, LM34CA
-40'Fto +230'F
LM34D
+32'Fto +212'F
DC Electrical Characteristics (Note 1, Note 6)
LM34CA
LM34A
Parameter
Accuracy (Note 7)
Conditions
TA
TA
TA
TA
=
=
=
=
+77'F
O'F
TMAX
TMIN
Typical
Tested
Limit
(Note 4)
±0.4
±0.6
±0.8
±0.8
±1.0
TMIN ~ TA ~ TMAX
±0.35
Sensor Gain
(Average Slope)
TMIN ~ TA ~ TMAX
+10.0
+9.9,
+10.1
Load Regulation
(Note 3)
TA
±0.4
±0.5
±1.0
Line Regulation (Note 3)
TA = +77'F
5V ~ Vs ~ 30V
±0.01
±0.02
±0.05
75
131
76
132
90
+0.5
2.0
=
+77'F
Typical
±0.4
±0.6
±0.8
±0.8
±2.0
±2.0
Nonlinearity (Note 8)
TMIN ~ TA ~ TMAX
~ IL ~ 1 mA
Design
Limit
(Note 5)
±0.7
Tested
Limit
(Note 4)
Design
Limit
(Note 5)
±1.0
±2.0
±2.0
±3.0
Units
(Max)
'F
'F
'F
'F
±0.30
±0.6
'F
+10.0
+9.9,
+10.1
mVI'F, min
mVI'F, max
±3.0
mV/mA
mV/mA
±O.1
mVIV
mVIV
139
/LA
/LA
142
/LA
/LA
3.0
/LA
/LA
±0.4
±1.0
±3.0
±0.5
±0.01
±0.02
±0.05
±O.1
90
163
75
116
76
117
+1.0
3.0
0.5
1.0
+0.30
+0.5
+0.30
+0.5
/LA/'F
+3.0
+5.0
+3.0
+5.0
'F
o
Quiescent Current
(Note 9)
Change of Quiescent
Current (Note 3)
Vs
Vs
Vs
Vs
=
=
=
=
+5V, +77'F
+5V
+30V, +77'F
+30V
4V ~ Vs ~ 30V, + 77'F
5V ~ Vs ~ 30V
Temperature Coefficient
of Quiescent Current
Minimum Temperature
for Rated Accuracy
In circuit of Figure 1,
Long-Term Stability
Tj
IL
=
=
0
T MAX for 1000 hours
160
92
±0.16
±0.16
92
2.0
'F
Note 1: Unless otherwise noted, these specifications apply: -SO"F ,;; Tj ,;; + 300'F lor the LM34 and LM34A; -40'F ,;; TI ,;; +230"F lor the LM34C and
LM34CA; and +S2"F ,;; Tj ,;; + 212"Florthe LMS4D. Vs ~ +S Vdc and ILOAD ~ SO p.A in the circuital Figure 2; +6 Vdclor LM34 and LMS4A lor 2SO"F ,;; TI ,;;
SOO·F. These specilications also apply Irom + S'F to TMAX in the circuit 01 Figure 1.
Note 2: Thermal resistance 01 the T0-46 packaga is 92"F/W junction to ambient and 4S'F/W iunction to case. Thermal rasistance 01 the TO·92 packaga is
324°F/W junction to ambient.
Note 3: Regulation is measured at constant junction temperature using pulse testing with a low duty cycle. Changes in output due to heating effects can be
computed by multiplying the internal dissipation by the thermal resistance.
Note 4: Tested limits are guaranteed and 100% tested in production.
Note 5: Design limits are guaranteed (but not I 00% production tested) over the indicated temperature and supply voltage ranges. These limits are not used to
calculate outgoing quality levels.
Note 6: Specilication in BOLDFACE TYPE apply over tha lull rated temperature range.
Note 7: Accuracy is defined as the error between the output voltage and 10 mVrF times the device's case temperature at specified conditions of voltage, current,
and temperature (expressed in 'F).
Note 8: Nonlinearity is defined as the deviation of the output·yoltage·yersus·temperature curve from the best·fit straight line over the device's rated temperature
range.
Note 9: Quiescent current is defined in the circuit of Figure 1.
Note 10: Absolute Maximum Ratings indicate limits bayond which damage to the device may occur. DC and AC electrical specilications do not apply when
operating the device beyond its rated operating conditions (see Note 1).
6-5
DC Electrical Characteristics (Note 1, Note 6) (Continued)
LM34
Parameter
Accuracy, LM34, LM34C
(Note 7)
Accuracy, LM34D
(Note 7)
Conditions
=
=
=
=
TA =
TA =
TA =
TA
TA
TA
TA
+77'F
O'F
TMAX
TMIN
Typical
±0.8
±1.0
±1.6
±1.6
Tested
Limit
(Note 4)
±2.0
±3.0
±3.0
+77'F
TMAX
TMIN
Nonlinearity (Note 8)
TMIN';; TA';; TMAX
±0.6
Sensor Gain
(Average Slope)
TMIN';; TA';; TMAX
+10.0
+9.8,
+10.2
Load Regulation
(Note 3)
TA = +77'F
TMIN ,;; TA';; +150'F
0,;; IL';; 1 mA
±0.4
±0.5
±2.5
Une Regulation (Note 3)
TA = +77'F
5V,;; VS';; 30V
±0.01
±0.02
±0.1
75
131
76
132
100
+0.5
+1.0
3.0
Quiescent Current
(Note 9)
Change of Quiescent
Current (Note 3)
Vs
Vs
Vs
Vs
=
=
=
=
+5V, +77'F
+5V
+30V, +77'F
+30V
4V ,;; Vs ,;; 30V, + 77'F
5V,;; VS';; 30V
Temperature Coefficient
of Quiescent Current
Minimum Temperature
for Rated Accuracy
In circuit of Figure 1,
IL = 0
Long-Term Stability
Tj
=
LM34C, LM34D
Design
Limit
(Note 5)
T MAX for 1000 hours
±1.0
Typical
Tested
Limit
(Note 4)
±0.8
±1.0
±1.6
±1.6
±2.0
±1.2
±1.8
±1.8
±3.0
±4.0
±4.0
'F
'F
OF
±1.0
of
mV/oF, min
mVI'F, max
±6.0
mV/mA
mV/mA
±0.2
mVIV
mVIV
±0.D1
±0.02
±0.1
±0.2
100
181
75
116
76
117
0.5
1.0
3.0
5.0
+0.30
+0.7
+3.0
+5.0
159
p.A
p.A
p.A
p.A
5.0
p.A
p.A
+0.30
+0.7
p.A!'F
+3.0
+5.0
'F
±0.16
6-6
'F
'F
'F
of
+9.8,
+10.2
±2.5
±0.16
±3.0
±3.0
±4.0
±0.4
±0.4
±0.5
103
Units
(Max)
+10.0
±6.0
176
Design
Limit
(Note 5)
154
103
'F
Typical Performance Characteristics
Thermal Resistance
Junction to Air
~rl
.
..
iii
w
.
8
";;;!
'"....
III
:z:
!Z
360
180
45
40
u
540
z
i5
i5
~~t
w
'"
;::
35
30
25
20
15
10
5
nTOr
400
800
1200 1600
o
2000
120
120
100
:I
80
..,..
..
w
-'
z
ii:
~
60
40
co
....
~
20
it!
I
,.
~
~'io.92
,.
E
...2i
.~
.--
>
V
-
,
\
400
~
co
80
:;
5.0
160
~
i
....
l:l:;
3.0 ~"""'''--I
I~
60
TEMPERATURE ('F)
......r.
120
100
[...0'
80
I""
60
•
40
~
20
-100
300
-4.0
-100
;:
--
r-- "
"'
co
"
III
~
:i'"~
'"
:!!
"""
100
200
TEMPERATURE ('F)
100
200
300
Accuracy vs. Temperature
(Guaranteed)
"-
LM34A
TYPICAL
L'r.;34
,
'"
TEMPERATURE ('F)
LM34
"'u
',UJIIIIIII"
1IIl,
I
200
140
Accuracy vs. Temperature
(Guaranteed)
t 2.0 ,
1IIl"
~ 1.0
w
"'" -1.0
m -2.0 r-~,
:!!
'" -3.0 I:.mm"
/
100
-20
Quiescent Current vs.
Temperature
(In Circuit of Figure 1)
ill
"
~
V
I
TIME IMIN)
I--t--t--+-+r--l
3.0
~
1
2000
....--r--r--....--...,...--,
4.0
140
-100
1200 1600
4.0 1----f--+---;jM'-_+_~
Quiescent Current vs. Temp·
erature (In Circuit of Figure 2;
-Vs = -5V, R1 = 100k)
100
800
40
20
10'
TEMPERATURE I'F)
180
120
....
~
TD·92
o
co
200
iB
~
....
.... ~6
TIME (SEC)
160
60
2.0 '---'--.1..--'---'----'
-100
100 200
300 400
o
~
....
-'
:§
;r:
co
w
-20
220
80
~
Minimum Supply Voltage
vs. Temperature
6.0
J
100
AIR VELOCITY (FPM)
Thermal Response in
Stirred Oil Bath
TO·4& f"
~
3
w
AIR VELOCITY (FPM)
l
Thermal Response in
Still Air
Thermal Time Constant
720
300
5.0
4.0
3.0
2.0
1.0
0
-1.0
-2.0
-3.0
-4.0
-5.0
-100
100
200
300
400
TEMPERATURE (OF)
TL/H/6685-5
6-7
Typical Applications
The LM34 can be applied easily in the same way as other
integrated-circuit temperature sensors. It can be glued or
cemented to a surface and its temperature will be within
about 0.02°F of the surface temperature. This presumes
that the ambient air temperature is almost the same as the
surface temperature; if the air temperature were much higher or lower than the surface temperature, the actual temperature of the LM34 die would be at an intermediate temperature between the surface temperature and the air temperature. This is expecially true for the TO-92 plastic package,
where the copper leads are the principal thermal path to
carry heat into the device, so its temperature might be closer to the air temperature than to the surface temperature.
To minimize this problem, be sure that the wiring to the
LM34, as it leaves the device, is held at the same temperature as the surface of interest. The easiest way to do this is
to cover up these wires with a bead of epoxy which will
insure that the leads and wires are all at the same temperature as the surface, and that the LM34 die's temperature will
not be affected by the air temperature.
The TO-46 metal package can also be soldered to a metal
surface or pipe without damage. Of course in that case, the
V _ terminal of the circuit will be grounded to that metal.
Alternatively, the LM34 can be mounted inside a sealed-end
metal tube, and can then be dipped into a bath or screwed
into a threaded hole in a tank. As with any IC, the LM34 and
accompanying wiring and circuits must be kept insulated
and dry, to avoid leakage and corrosion. This is especially
true Irthecfrcilitmay-6perate at cold temperatures where
condensation can occur. Printed-circuit coatings and varnishes such as Humiseal and epoxy paints or dips are often
used to insure that moisture cannot corrode the LM34 or its
connections.
These devices are sometimes soldered to a small, lightweight heat fin to decrease the thermal time constant and
speed up the response in slowly-moving air. On the other
hand, a small thermal mass may be added to the sensor to
give the steadiest reading despite small deviations in the air
temperature.
Capacitive Loads
Like most micro power circuits, the LM34 has a limited ability
to drive heavy capacitive loads. The LM34 by itself is able to
drive 50 pF without special precautions. If heavier loads are
anticipated, it is easy to isolate or decouple the load with a
resistor; see Figure 3. Or you can improve the tolerance of
capacitance with a series R-C damper from output to
ground; see Figure 4. When the LM34 is applied with a
4990 load resistor (as shown), it is relatively immune to
wiring capacitance because the capacitance forms a bypass
from ground to input, not on the output. However, as with
any linear circuit connected to wires in a hostile environment, its performance can be affected adversely by intense
electromagnetic sources such as relays, radio transmitters,
motors with arcing brushes, SCR's transients, etc., as its
wiring can act as a receiving antenna and its internal junctions can act as rectifiers. For best results in such cases, a
bypass capacitor from VIN to ground and a series R-C
... _ damper. such as 750 in series with 0.2 or 1 I1F from output
to ground are often useful. These are shown in the following
circuits.
Temperature Sensor,
Single Supply, -50" to + 300°F
+Vs
TLlH16685-7
1
L
FIGURE 3. LM34 with Decoupling from Capacitive Load
LM34 }
lN914 ~,
'""" :
r -- - ......- - - - - I
LM34 S
} Vou,
18k
10%
l.1. ILI~~==-""
~
~
160
I
I
1~~
L _ - - ........- ....--4~\-
TLIH16685-6
\
0.1 .F BYPASS
(OPTIONAL)
HEAVY CAPACITIVE LOAD, WIRING, ETC.
TLlHI6685-8
FIGURE 4. LM34 with R-C Damper
Temperature Rise of LM34 Due to Self-Heating (Thermal Resistance)
Conditions
Still air
Moving air
Still oil
Stirred oil
(Clamped to metal, infinite heat sink)
TO-46,
No Heat Sink
TO-46,
Small Heat Fin·
TO-92,
No Heat Sink
TO-92,
Small Heat Fin"
720"F/W
180"F/W
180°F/W
90°F/W
180°F/W
7Z'F/W
72°F/W
54°F/W
324°F/W
162°F/W
162°F/W
81°F/W
25Z'F/W
126°F/W
126°F/W
7Z'F/W
(43°F/W)
'Wakefield lype 201 or I" disc of 0.020" sheel brass, soldered 10 case, or similar.
"T0-92 package glued and leads soldered 10 I" square of 'I,." prinled circuil board w"h 2 OZ copper foil, or similar.
6-8
Typical Applications
(Continued)
Two-Wire Remote Temperature Sensor
(Grounded Sensor)
Two-Wire Remote Temperature Sensor
(Output Referred to Ground)
5V
5V
+
YOUT
= 10mYI'F (TA+3'F)
HEAT
FINS
HEAT
FINS
;;:---T"'"--'
TWISTED PAIR
~_,..._
4991l
1%
20k
5%
OR 50k RHEOSTAT
FOR GAIN ADJUST
TL/H/6685-10
TL/H/6685-9
4-to-20 mA Current Source
(0 to + 100'F)
Fahrenheit Thermometer
(Analog Meter)
+5V
r - -......" " ' " " - - - - -...Mt-+6VTD +30V
2N2907
....-..-"'4D2
1%
62.5
D.5%
TL/H/8685-12
TL/H/6685-11
Expanded Scale Thermometer
(50' to SO' Fahrenheit, for Example Shown)
Temperature-to-Dlgltal Converter
(Serial Output, + 12S'F Full Scale)
+9V
-
......-
_--------1----.--~--+~
... OUT
2k
2600
+
t-"""",,,,,,,,_.J\IV\r..,
SERIAL DATA
100 ,A. 60 mV
FUll SCALE
SND
OUTPUT
CLOCK
.....---ENABLE
10k
L..-....- -....- -....___...._____ OROUND
TUH/6685-14
TL/H/6685-13
6-9
Q
"=I'
C")
::::!E
...I
r----------------------------------------------------------------------,
Typical Applications (Continued)
~
LM34 with Voltage-to-Frequency Converter and Isolated Output
(3°F to + 300"F; 30 Hz to 3000 Hz)
"=I'
C")
::::!E
...I
+6V
~
C")
::::!E
...I
<
+
"=I'
C")
::::!E
...I
OUT
;;:
100k.ll
::::!E
...I
0.01 ~F
C")
100k.ll
1%
TLlH/66B5-15
Bar-Graph Temperature Display
(Dot Mode)
67
68
69
70
71
72
.. ,.
,r
73
74 75
+7V
~k
20.F;f
':'
~,
~
, .. ,.
18
I
---Jl
~
lM34
-
,~
13
~~ ~
, ,~ ~ ,.. , ,,. ,~ ~ ~
..
fo
11
12
lM3914
~
+~:
4
5
6
7
18
10
8
9
II
16
17
15
~~ ~
14
,. ,,. ,,.. .~~
..
fo
13
12
6
7
1~
lk'
X
4
5
ED•
10
~~
8
I
Ne
V.
Vc
1.0k*
/, ~
500!!
4021l'
4021l'
4021l'
-
o
(+2.25V)
I
1PF
11
lM3914
LOUT
+
I
""14
15
16
,.
VA
+
HEAT
FINS
17
,
lk'
2k'
ka
~lk
...
/,
/, lk
o:!:r
TLlH/6685-16
•
~
1% or 2% film resistor
-Trim RB for VB
~
3.525V
-Trim Rc for Vc
~
2.725V
-Trim RA for VA ~ 0.085V
-Example. VA
6-10
~
+
40 mVrF x T AMBIENT
3.285V at 80'F
,------------------------------------------------------------------------,
Typical Applications (Continued)
~
i:
w
~
......
~
i:
w
~
Temperature-to-Dlgltal Converter
(Parallel TRI-STATE@ Outputs for Standard Data Bus to fLP Interface, 128 of Full Scale)
~
~
i:
w
+5V
Q
+
OUT
PARALLEL DATA
OUTPUT
~
i:
w
GNO
~
iiiTii
150
lk
Cs
iiii
Wii
+
1,F
~
i:
w
~
o
GROUND
TLlH/6685-17
Temperature Controller
+15V
3k
TEMP. ADJUST
HEATER
INDICATOR
400"F
+15V
50k
6V
40 mA
27k
2k
\~
________________
~ JI
,
I
I
THERMALLY COUPLED
SETPOINT
(10 my/oF)
ACTUAL
TEMPERATURE
(10 my/oF)
TLiH/6685-1 B
Block Diagram
1.590VmT
(AT 77°F)
t----+-+-.,
Rl
VOUT= 10 mY/oF
Ve
0.865R2
nRl
R2
TL/H/6685-19
6-11
~National
~ Semiconductor
LM35/LM35A/LM35C/LM35CA/LM35D
Precision Centigrade Temperature Sensors
General Description
The LM35 series are precision integrated-circuit temperature sensors, whose output voltage is linearly proportional to
the Celsius (Centigrade) temperature. The LM35 thus has
an advantage over linear temperature sensors calibrated in·
Kelvin, as the user is not required to subtract a large constant voltage from its output to obtain convenient Centigrade scaling. The LM35 does not require any extemal calibration or trimming to provide typical accuracies of ± 1,4·C
at room temperature and ± %·C over a full - 55 to + 150·C
temperature range. Low cost is assured by trimming and
calibration at the wafer level. The LM35's low output impedance, linear output, and precise inherent calibration make
interfacing to readout or control circuitry especially easy. It
can be used with single power supplies, or with plus and
minus supplies. As it draws only 60 /LA from its supply, it has
very low self-heating, less than 0.1·C in still air. The LM35 is
rated to operate over a-55· to + 150·C temperature
range, while the LM35C is rated for a -40· to + 11 O·C
range (-10· with.improved accuracy). The LM35 series is
Connection Diagrams
available packaged in hermetic T0-46 transistor packages,
while the LM35C is also available in the plastic TO-92 transistor package.
Features
•
•
•
•
•
•
•
•
•
•
•
Calibrated dire"ctly in • Celsius (Centigrade)
Unear + 10.0 mVl·C scale factor
0.5°C accuracy guaranteeable (at + 25·C)
Rated for full - 55° to + 150"C range
Suitable for remote applications
Low cost due to wafer-level trimming
Operates from 4 to 30 volts
Less than 60 /LA current drain
Low self-heating,
in still air
Nonlinearity only ± 14°C typical
Low impedance output, 0.1 n for 1 mA load
o.oa·c
Typical Applications
TO-46
Metal Can Package·
(§)
t§l
+Vs
¥OUT
+vs
6
GNDO-
BDTTOMVIEW
*Case is connected
OUTPUT
~DmV+10.0mV/OC
TLlH/5516-1
to negative pin
TL/H/5516-3
FIGURE 1. Basic Centigrade Temperature
Sensor (+ 2°C to + 150"C)
Order Number LM35H, LM35AH,
LM35CH, LM35CAH or LM35DH
See NS Package Number H03H
TO-92
Plastic Package
~
--
:M:5'~T
BOTTOM VIEW
TL/H/5516-2
Order Number LM35CZ or LM35DZ
See NS Package Number Z03A
R1
-vs
VOUT=+1,500mVal +150'C
= +250 mVal +25"C
= -550 mVal -55'C
TLlH/5516-4
FIGURE 2. Full-Range Centigrade Temperature Sensor
6-12
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Absolute Maximum Ratings (Note 10)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
+35Vto -0.2V
Output Voltage
+6Vto -1.0V
Output Current
10mA
Storage Temp., TO·46 Package,
-60'C to + 180'C
TO·92 Package,
-60'Cto +150'C
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Specified Operating Temperature Range: TMIN to TMAX
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(Note 2)
LM35, LM35A
- 55'C to + 150'C
LM35C, LM35CA
-40'Cto +110'C
LM35D
O'C to + 100'C
300'C
TO·92 Package,
260'C
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Lead Temp. (Soldering, 10 seconds):
TO·46 Package,
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......
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Electrical Characteristics (Note 1) (Note 6)
LM35CA
LM35A
Parameter
Accuracy
(Note 7)
Conditions
TA= +25'C
TA=-10'C
TA=TMAX
TA=TMIN
Typical
±0.2
±0.3
±0.4
±0.4
Tested
Limit
(Note 4)
±0.5
TMIN:5:TA:5:TMAX
±0.18
Sensor Gain
(Average Slope)
TMIN:5:TA:5:TMAX
+10.0
+9.9,
+10.1
Load Regulation
(Note 3) 0:5: IL:5: 1 mA
TA= + 25'C
TMIN:5:TA:5:TMAX
±0.4
±0.5
±1.0
Line Regulation
(Note 3)
TA= + 25'C
4V:5:Vs:5:30V
±0.01
±0.02
±0.05
Quiescent Current
(Note 9)
Vs= +5V, +25'C
Vs=+5V
Vs= +30V, + 25'C
Vs=+30V
56
105
56.2
105.5
67
0.2
0.5
1.0
4V:5:Vs:5:30V, +25'C
4V:5:Vs:5:30V
Temperature
Coefficient of
Quiescent Current
Typical
±0.2
±0.3
±0.4
±0.4
±1.0
±1.0
Nonlinearity
(Note 8)
Change of
Quiescent Current
(Note 3)
Design
Limit
(Note 5)
±0.35
Tested
Limit
(Note 4)
±0.5
±1.5
±0.15
±0.3
'C
+10.0
+9.9,
+10.1
mV/'C
±1.0
±0.4
±0.5
±1.0
±0.01
±0.02
±0.05
±O.1
67
133
56
91
56.2
91.5
2.0
0.2
0.5
+0.39
+0.5
+2.0
Minimum Temperature
for Rated Accuracy
In circuit of
Figure 1, IL =0
+1.5
Long Term Stability
TJ=TMAX. for
1000 hours
±0.08
68
Uhits
. ·(Ma~.)
'C
'C
'C
'C
±1.0
±3.0
131
Design
Limit
(Note 5)
±3.0
mV/mA
mV/mA
±O.1
mVIV
mVIV
116
p.A
p.A
p.A
p.A
2.0
p.A
p.A
+0.39
+0.5
p.AI'C
+1.5
+2.0
'C
±0.08
114
68
1.0
'C
Note 1: Unless otherwise noted. these specifications apply: - 55'C"TJ" + 150'C for the LM35 and LM35A; - 4er" TJ" + 11 erc for the LM35C and LM35CA; and
er"TJ" +IDcrC for the LM35D. Vs= +5Vdc and ILOAD=50 /LA. in the circuit of Figure 2. These specifications also apply from +2'C to TMAX in the circuit of
F/{/ure 1. Specifications in boldface apply over the full rated temperature range.
Note 2: Thermal resistence of the T0-46 package is 440'C/W, iunclion to ambient. and 24'C/W junction to case. Thermal resistence of the TO·92 package is
ISerC/W junclion to ambient.
6·13
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Electrical Characteristics (Note 1) (Note 6)
(Continued)
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LM35
Parameter
Conditions
Typical
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Accuracy,
LM35D
(Note 7)
TA= + 25'C
TA=TMAX
TA=TMIN
Nonlinearity
(Note B)
TMIN:5:TA:5:TMAX
±0.3
Sensor Gain
(Average Slope)
TMIN:5:TA:5:TMAX
+10.0
+9.8,
+10.2
Load Regulation
(Note 3) 0:5: IL:5: 1 mA
TA=+25'C
TMIN:5:TA:5:TMAX
±0.4
±0.5
±2.0
Line Regulation
(Note 3)
TA= +25'C
4V:5:Vs:5:30V
±0.Q1
±0.02
±0.1
Quiescent Current
(Note 9)
Vs= +5V, +25'C
Vs=+5V
Vs= +30V, +25'C
Vs=+30V
56
105
56.2
-105.5
BO
Change of
Quiescent Current
(Note 3)
4V:5:Vs:5:30V, +25'C
4V:5:Vs:5:30V
Temperature
Coefficient of
Quiescent Current
LM35C, LM35D
Design
Limit
(Note 5)
±1.0
TA=+25'C
TA= -10'C
TA=TMAX
TA=TMIN
.....
:E
±0.4
±0.5
±O.B
±O.B
Accuracy,
LM35, LM35C
(Note 7)
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Tested
Limit
(Note 4)
±1.5
±1.5
±0.5
Typical
Tested
Limit
(Note 4)
±0.4
±0.5
±O.B
±O.B
±1.0
±0.6
±0.9
±0.9
±1.5
'C
'C
'C
'C
±2.0
±2.0
'C
'C
'C
±0.2
±0.5
'C
+10.0
+9.8,
+10.2
mV/'C
±0.4
±0.5
±2.0
±0.01
±0.02
±0.1
±0.2
BO
161
56
91
56.2
91.5
3.0
0.2
0.5
+0.39
+0.7
+2.0
B2
0.2
0.5
Minimum Temperature
for Rated Accuracy
In circuit of
Figure 1, IL =0
+1.5
Long Term Stability
TJ=TMAX,for
1000 hours
±O.OB
2.0
Units
(Max.)
±1.5
±1.5
±2.0
'±5.0
158
Design
Limit
(Note 5)
±5.0
mV/mA
mV/mA
±0.2
mVIV
mVIV
138
/k A
/k A
/k A
141
,.ok
3.0
/k A
/k A
+0.39
+0.7
/kAl'C
+1.5
+2.0
'C
±O.OB
B2
2.0
'C
Note 3: Regulation is measured at constant junction temperature, using pulse testing with a low duty cycle. Changes in output due to heating effects can be
computed by multiplying the intemal dissipation by the thermal resistance.
Note 4: Tested limits are guaranteed and 100% tested in production,
Note 5: Design Umits are guaranteed (but not 100% production tested) over the indicated temperature and supply voltage ranges. These limits are not used to
calculate outgoing quality levels.
Note 6: Specifications in boldface apply over the full rated temperature range,
Note 7: Accuracy is defined as the error between the output voltage and 1Omv/oC times the device's case temperature, at specified conditions of Yoitage. current,
and temperature (expressed in ·C).
Note 8: Nonlinearity is defined as the deviation of the output·voltage·versus-temperature curve from the best·fit straight line, over the device's rated temperature
range.
Note 9: Quiescent current Is defined in the circuit of Figure 1.
Note 10: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when
operating the device beyond its rated operating conditions. See Note 1.
6·14
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Typical Performance Characteristics
Thermal Resistance
Junction to Air
45
40
i"
E
...z 300 H-t-+-+-I-+++-+-I
u
ill
200 I-\I-t-+-+-I-+++-+-I
T1I-46
~ tl~;t:eS~~:t~
To·92
... 100
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o L....L-'--'-...I.....L...JL......L--'---'-..J
o
400
800 1200 1600
AIR VELOCITY (FPM)
Thermal Response
in Still Air
Thermal Time Constant
400 I"""'T-r-r-r-.--r--r-..,.....,....,
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!Z
~
~
~
~--I-t-+-+-I-+-+--H
35 H-l-+-+-+++++-l
30 H-l-t-+-+-++++-l
25 I\-IH-t--+-+-I-++--H
20
15
\
~-l-t-+-+-++++-l
J T~.46I-'H-t--+-+-I--l
~ lo~,~~~~-r+-~-+~
5~~
o~
2000
Co)
120
o
....
....
~ 100
~
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60
40
20
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.....
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0
400 800 1200 1600 2000
AIR VELOCITY (FPM)
g
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-20
0
2
4
6
TIME (MINUTES)
8
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Quiescent Current
vs. Temperature
(In Circuit of Figure t.)
Thermal Response in
Stirred Oil Bath
120
r-r-r-,--r-..,...-,--,--,
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C
160 r-,.-,r-r-r-r....,......,..-.-.,....,
140
~~H-t--+-+-+-I-+-l
1120
~H-t-+-+-I--I-+-t-:.iI.
l-
I...,
100
~
60
..
~
-20 L-L--L--l.-l.-l.-.l-.l-.J
80
40
20
0
-75 -25
o
TIME (SECONDS)
25
75
125
TEMPERATURE ('C)
175
TUH/5516-17
200
10
1 160
1
B
140
120
~
100
fa
80
~
Quiescent Current
vs. Temperature
(In Circuit of Figure 2.)
Accuracy vs. Temperature
(Guaranteed)
2.0
r-r-r-,-..,-r-,-r-r-r-,
~-t-+-I-++-+-+-~
~~+-~-+~+-~
H-t-+-+++-J.oo"f~'-t-l
Accuracy vs. Temperature
(Guaranteed)
2.5 "r-r-r-,-..,....,........,-"
2.0 Hf'Il!li.trl,l~ct-tllol"cliIItlf-L~3~D
u
1.5
LM35C
'" 1.0
"'~N. iii"
LMHCA
~
H-t-+-+-b.-li."'F-l-t-+-l
H-t-t-A"',++++-+--i
0.5
::!o.~
1"'Io~ 'frPICA~fF
..t.
L~, 3~,·CA
~ ..,0.5 ~•.,y.:++1off7lito..r+++--F-I
!!! -1.0
~boI"'~-+-I-+-+-+-~
Ioff
iIi-l.5
LM35C
IJf
I I
-2.0
L~3~D
- 2.5 I-J'--I......L-'--'--'--'--'-..L.......I
-75 -25
25
75 125
175
TEMPERATURE ('C)
I-
40 I-J'--"-'--'--'--'--'--'-.J......I
-75 -25 25
75
125 175
TEMPERATURE ('C)
_ 2.0 1-J--'-'--'--'--'-'L"'M;;;35'-'-........
-75 -25 25
75
125 175
TEMPERATURE ('C)
TL/H/5516-18
6-15
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II)
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:i!i
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......
II)
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Applications
The LM35 can be applied easily in the same way as other
integrated-circuit temperature sensors. It can be glued or
cemented to a surface and its temperature will be within
about 0.01·C of the surface temperature.
This presumes that the ambient air temperature is almost
the same as the surface temperature; if the air temperature
were much higher or lower than the surface temperature,
the actual temperature of the LM35 die would be at an intermediate temperature between the surface temperature and
the air temperature. This is expecially true for the TO-92
plastic package, where the copper leads are the principal
thermal path to carry heat into the device, so its temperature might be closer to the air temperature than to the surface temperature.
To minimize this problem, be sure that the wiring to the
LM35, as it leaves the device, is held at the same temperature as the surface of interest. The easiest way to do this is
to cover up these wires with a bead of epoxy which will
insure that the leads and wires are all at the same temperature as the surface, and that the LM35 die's temperature will
not be affected by the air temperature.
The T0-46 metal package can also be soldered to a metal
surface or pipe without damage. Of course, in that case the
V - terminal of the circuit will be grounded to that metal.
Alternatively, the LM35 can be mounted inside a sealed-end
metal tube, and can then be dipped into a bath or screwed
into a threaded hole in a tank. As with any IC, the LM35 and
accompanying wiring and circuits must be kept insulated
and dry, to avoid leakage and corrosion. This is especially
true if the circuit may operate at cold temperatures where
condensation can occur. Printed-circuit coatings and varnishes such as Humiseal and epoxy paints or dips are often
used to insure that moisture cannot corrode the LM35 or its
connections.
. These devices are sometimes soldered to a small lightweight heat fin, to decrease the thermal time constant and
speed up the response in slowly-moving air. On the other
hand, a small thermal mass may be added to the sensor, to
give the steadiest reading despite small deviations in the air
temperature.
Temperature Rise of LM35 Due To Self-heating (Thermal Resistance)
TO-46,
no heat sink
Still air
Moving air
Still oil
Stirred oil
(Clamped to metal,
Infinite heat sink)
TO-46,
small heat fin'
400·C/W
100·C/W
100·C/W
50·C/W
TO-92,
no heat sink
1000C/vV
400C/W
40·C/W.
30·C/W
TO-92,
small heat fin"
140·C/W
70·C/W
70·C/W
40·C/W
180·C/W
900C/W
900C/W
45·C/W
(24·C/W)
• Wakefield type 201, or 1" disc of 0.020" sheet brass, soldered to case, or similar.
.. T0-92 package glued and leads soldered to t' square of
'Ii.'
printed circuit board with 2 oz. foil or similar.
Typical Applications (Continued)
_+...
Ir----~~~~~~~~~
.........
HEAVY CAPACITIVE LOAD, WIRING. ETC.
+
HEAVY CAPACITIVE LOAD. WIRING. ETC.
I
:~OUTiiiT..J2~k,,"""~e:====~ TO A HIGH·IMPEDANCE LOAD
0.1,.F BYPASS..1....
I
OPTIONAL ..,....
I
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LM35
IL ____
TL/H/5516-19
FIGURE 3. LM35 with Decoupllng from Capacitive Load
llroUT~_~===~
75
;'~I,.F
~----~--~----
___
TUH/5516-20
FIGURE 4. LM35 with R-C Damper
capacitance because the capacitance forms a bypass from
ground to input, not on the output. However, as with any
linear circuit connected to wires in a hostile environment, its
performance can be affected adversely by intense electro·
magnetic sources such as relays, radio transmitters, motors
with arcing brushes, SCR transients, etc, as its wiring can
act as a receiving antenna and its internal junctions can act
as rectifiers. For best results in such cases, a bypass capacitor from VIN to ground and a series R-C damper such as
75n in series with 0.2 or 1 p.F from output to ground are
often useful. These are shown in Figures 13, 14, and 16.
CAPACITIVE LOADS
Like most micropower circuits, the LM35 has a limited ability
to drive heavy capacitive loads. The LM35 by itself is able to
drive 50 pf without special precautions. If heavier loads are
anticipated, it is easy to isolate or decouple the load with a
resistor; see Figure 3. Or you can improve the tolerance of
capacitance with a series R-C damper from output to
ground; see Figure 4.
When the LM35 is applied with a 200n load resistor as
shown in Figure 5, 6, or 8, it is relatively immune to wiring
6-16
r-----------------------------------------------------------------------------,~
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Typical Applications (Continued)
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FINS
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HEAT
FINS
~
lWlSTEOIWR
TLlH/5516-6
FIGURE 6. Two-Wire Remote Temperature Sensor
(Output Referred to Ground)
TL/H/5516-5
FIGURE 5. Two-Wire Remote Temperature Sensor
(Grounded Sensor)
+Vs
r----t~----~-I
I
O.lpf
.l...
BYPASS""T"" ~--....
OPrIONAL I
I
2k
I
111
I
TWISTED PAIR
200
111
L_--o1--~poooe:...._ ::M=~~~~~~~+10~C)
18k
1011
200
111
TLlH/5516-7
FIGURE 7. Temperature Sensor, Single Supply, -55' to
+ 150'C
TL/H/5516-6
FIGURE 8. Two-Wire Remote Temperature Sensor
(Output Referred to Ground)
, - - -....- - - - - -....-+11-
+Ys
(6YTO 2OV)
+SV TO +3DV
Uk
45.5k
111
10k
111
VoUT~
+1.0mY/'F
26.4k
111
TLlH/5516-9
FIGURE 9. 4-To-20 mA Current Source (O'C to
+ 100'C)
LM385-1.2
18k
TL/H/5516-10
FIGURE 10. Fahrenheit Thermometer
6-17
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Typical Applications (Continued)
5V
9V
100pA.
60mV
FULL-SCALE
TL/H/5516-11
FIGURE 11. Centigrade Thermometer (Analog Meter)
TLlH/5516-12
FIGURE 12. Expanded Scale Thermometer
(50" to BO' Fahrenheit, for Example Shown)
~------------'----------1~----~
IN
REF
1.28V
....,r-r""T...
SERIAL
DATA OUTPUT
CLOCK
.....- - - -... ENABLE
~~~--4-----~--------~--------&ND
TLlH/5516-13
FIGURE 13. Temperature To Digital Converter (Serial Output) (+ 12B'C Full Scale)
5V
16k
IN
1k
VREF
O.64V
PARALLEL
DATA
OUTPUT
INTR
'fS
iiii
Wi!
2k
GND
TL/H/5516-14
FIGURE 14. Temperature To Digital Converter (Parallel TRI-STATE® Outputs for
Standard Data Bus to ,...p Interface) (12B'C Full Scale)
6·18
Typical Applications
(Continued)
-------------------------'·F----------------------~
20 LEOs
HEAT
ANS
499·
499·
Uk·
Uk·
IkO
Re
RS
lk
lk
RA
lk
TLlH/5516-16
·=1% or 2% film resistor
-Trim AB for VB = 3.075V
-Trim Ac for VC=I.955V
-Trim RA for VA = O.075V + 1OOmVrc X Tambient
-Example, VA = 2.275V at 22"C
FIGURE 15. Bar-Graph Temperature Display (Dot Mode)
6Y
.,
fOUT
..
lOOk
LMl31
0.01,.f
lOOk
0.01
~F
LOWTEMPCO
47
TLlH/5516-15
FIGURE 16. LM35 With Voltage-To-Frequency Converter And Isolated Output
(TC to + 150"C; 20 Hz to 1500 Hz)
6-19
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Block Diagram
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TLlH/5516-21
6-20
J?'A National
~ Semiconductor
LM 135/LM235/LM335, LM 135A/LM235A/LM335A
Precision Temperature Sensors
General Description
The LM135 series are precision, easily-calibrated, integrated circuit temperature sensors. Operating as a 2-terminal
zener, the LM135 has a breakdown voltage directly proportional to absolute temperature at + 10 mVI"K. With less
than 1.n dynamic impedance the device operates over a
current range of 400 p.A to 5 mA with virtually no change in
performance. When calibrated at 25'C the LM135 has typically less than 1'C error over a 100'C temperature range.
Unlike other sensors the LM135 has a linear output.
Applications for the LM135 include almost any type of temperature sensing over a - 55'C to + 150'C temperature
range. The low impedance and linear output make interfacing to readout or control circuitry especially easy.
The LM135 operates over a - 55'C to + 150'C temperature
range while the LM235 operates over a -40'C to + 125'C
temperature range. The LM335 operates from -40'C to
+100'C. The LM135/LM235/LM335 are available packaged in hermetic TO-46 transistor packages while the
LM335 is also available in plastic TO-92 packages.
Features
• Directly calibrated in 'Kelvin
iii 1'C initial accuracy available
• Operates from 400 /LA to 5 mA
iii Less than 1.n dynamic impedance
III Easily calibrated
iii Wide operating temperature range
III 200'C overrange
a Low cost
Schematic Diagram
R.
60.
1--+--1~"""-ADJUSTMENT
RIO
13.811
TL/H/5698-1
Connection Diagrams
TO-92
PlastiC Package
TO-46
Metal Can Package"
BonOMVIEW
BonOMVIEW
TL/H/5698-8
·ease is connected to negative pin
Order Number LM335Z or LM335AZ
See NS Package Number Z03A
Order Number LM135H, LM235H,
LM335H, LM135AH, LM235AH or LM335AH
See NS Package Number H03H
6-21
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
(Note 4)
Reverse Current
15mA
Forward Current
10mA
Specified Operating Temp. Range
Continuous
- 55·C to + 150·C
LM135, LM135A
-40·Cto + 125·C
LM235, LM235A
-40·C to + 100·C
LM335, LM335A
Lead Temp. (Soldering, 10 seconds)
TO-92 Package:
T0-46 Package:
Storage Temperature
TO-46 Package
-60·C to + 160·C
TO-92 Package
- 60·C to + 150·C
Temperature Accuracy
Intermittent
(Note 2)
150"C to 200"C
125·C to 150·C
1OO·C to 125·C
260"C
300"C
LM135/LM235, LM135A1LM235A (Note 1)
Parameter
Operating Output Voltage
Tc = 25·C, IR = 1 mA
Uncalibrated Temperature Error
Tc = 25·C, IR = 1 mA
Uncalibrated Temperature Error
TMIN
:s: Tc:S: TMAX, IR
LM135/LM235
LM135A1LM235A
Conditions
Units
Min
Typ
Max
Min
Typ
Max
2.97
2.96
2.99
2.95
2.96
3.01
V
0.5
1
1
3
·C
= 1 mA
1.3
2.7
2
5
·C
Temperature Error with 25·C
Calibration
TMIN:S: Tc:S: TMAX, IR = 1 mA
0.3
1
0.5
1.5
·C
Calibrated Error at Extended
Temperatures
T c = T MAX (Intermittent)
Non-Linearity
IR = 1 mA
2
·C
2
0.3
0.5
0.3
1
·C
Temperature Accuracy LM335, LM335A (Note 1)
Parameter
Operating Output Voltage
Tc = 25·C, IR = 1 mA
Uncalibrated Temperature Error
Tc = 25·C, IR = 1 mA
Uncalibrated Temperature Error
LM335
LM335A
Conditions
Units
Min
Typ
Max
Min
Typ
Max
2.95
2.96
3.01
2.92
2.98
3.04
V
1
3
2
6
·C
TMIN:S: Tc:S: TMAX, IR = 1 mA
2
5
4
9
·C
Temperature Error with 25·C
Calibration
TMIN:S: Tc:S: TMAX, IR = 1 mA
0.5
1
1
2
·C
Calibrated Error at Extended
Temperatures
T c = T MAX (Intermittent)
Non-Linearity
IR = 1 mA
2
·C
2
0.3
1.5
0.3
1.5
·C
Electrical Characteristics (Note 1)
Parameter
LM135/LM235
LM135A1LM235A
Conditions
Min
Operating Output Voltage
Change with Current
400 ,...A:S:IR:S:5 mA
At Constant Temperature
Dynamic Impedance
IR=1 mA
Output Voltage Temperature
Coefficient
Typ
Max
2.5
10
LM335
LM335A
Min
Units
Typ
Max
3
14
mV
0.5
0.6
n
+10
+10
mVrC
Time Constant
Still Air
100 It/Min Air
Stirred Oil
60
10
1
60
10
1
sec
sec
sec
Time Stability
Tc=125·C
0.2
0.2
·C/khr
Note 1: Accuracy measurements are made in a well·stirred oil bath. For other conditions, self heating must be considered.
Note 2: Continuous operation at these temperatures for 10,000 hours for H package and 5,000 hours for Z package may decrease life expectancy of the devioe.
Note 3: Thermal. Resistance
TO·92 T0-46
ijunction to ambient)
20Z'C/W 400'C/W
ijunctlon to case)
17CY'C/W N/A
Note 4: Refer to RETS135H for milHary spacifications.
9JA
9JC
6-22
Typical Performance Characteristics
Reverse Voltage Change
Calibrated Error
Reverse Characteristics
10
I I
~.• 1-55!C
I
I
TI-25'C
P'~
:<
.§
...
4.V('
,/
I I
V
XJ..1"""
'I
t..IJiiII'
I
ffi
~
I
I
I
-4
-55 -15
10
25
.
.~
..,.
E
I-,N.Or
~
Iz"1mA
§
~
u
z
I
10
~
~
C:Tj=-55'C
.
iii
c
I
I
""'"
Tj'25'C--1
ZOO
10k
lk
100
lOOk
10
lk
100
10k
lOOk
FREQUENCY IHzI
Thermal Response
in Still Air
41
U
l!l...
~
l'\
"
~
!
TO·9Z
~ 100
35
~
">
10
5
BOO
1200
1600
~
1\
0
410
...""
e.
~
25
15
'"
~
=
30
z
zo
8
=
TD~
,,~
1111
"-
Thermal Time Constant
~
c
240
45
<- 310
210
z
r\.
FREQUENCY (Hz)
Thermal Resistance
Junction to Air
~
2S0
..'"
=Tj.,25'_.A
~
_IIN~UT
~
~
u
4110
..."
320
"
lil
10
..
Noise Voltage
Tj=25'C
1k
TlMEII
3>
L~ rJ.OURNS
---
4258-0007
•
15V
r-____+-~1~_*51-1~0.,~
2>
-15V
TL/H/5698-20
Simple Temperature Controller
lOY -3I1V-4_-----------------------.....-4_------.
HEATER
LM32BC
lM311S
TL/H/5698-5
Simple Temperature Control
LM335
SV-4UV
UI32ae
3>
,.
-10V
TLiH/5698-21
6-25
Typical Applications
(Continued)
Ground Referred Fahrenheit Thermometer
Centigrade Thermometer
..
15Y
.
..
.,'
LM335
15Y
15Y
'2k
lOUTPUT
1DrnYl°r.
8Z'
21'
'Ok
t----6~·~·'..~~-~~ll
Ilk
Uk
"
2"
-1,.
TUH/569B-22
.".
.".
'Adjust R2 lor 2.554V across LM336.
r"
Adjust Rt lor correct output.
100
.".
TLlH/569B-23
'AdJust lor 2.7315V at output 01 LM308
Fahrenheit Thermometer
15.
,..
,.
tM335
TLlH/569B-24
'To calibrate adjust R2 for 2.554V across LM336.
Adjust RI lor correct output.
THERMOCOUPLE COLD JUNCTION COMPENSATION
Compensation for Grounded Thermocouple
·Select R3 for proper thermocouple type
THERMOR3
COUPLE
(±1%)
15V
J
4.7k
200k
3770
3080
T
1"
R3*
1:~ 2'l1-"\j'Y\o............""',..,.-,
K
2930
S
45.80
SEEBECK
COEFFICIENT
52.3 ",VI"C
42.B ",VI"C
40.B",VI'C
6.4 ",V/'C
Alljustments: Compensates lor both sensor and resistor tolerances
1M
1%
I. Short LM329B
2. Adjust RI lor Seebeck Coefficient times ambient temperature (in degrees
K) across R3.
3. Short LM335 and adjust R210r voltage across R3 corresponding to thermocouple type
J
THERMOCOUPLE
T
12k
-15V
TL/H/569B-6
6-26
14.32 mV
11.79 mV
K
S
11.17mV
1.768 mV
Typical Applications
(Continued)
Single Power Supply Cold Junction Compensation
15V
10k
·Select R3 and R4 for thermocouple type
ZOOk
THERMOTHERMOCOUPLE
RI
10k
LM335
R3
COUPLE
+
':'
':'
R3
R4
SEEBECK
COEFFICIENT
J
T
1.05K
385n
52.3/LVrC
856n
315n
42.8/LVrC
K
816n
300n
40.8/LVrC
S
128n
46.3n
6.4/LV/'C
Adiustments:
I. Adjust RI for the voltage across R3 equal to the Seebeck Coefficient
15V
times ambient temperature in degrees Kelvin.
2. Adjust R2 for voltage across R4 corresponding to thermocouple
+
200k
R2
10k
LM3298
':'
J
T
OUTPUT
1M
14.32 mV
K
11.79 mV
11.17 mV
S
1.768mV
R4
':'
TLlH/5696-11
Centigrade Calibrated Thermocouple Thermometer
I02k
1%
294k
1%
4.7k
15V
10k
-15V
I~:
LM335
':'
422
1%
':'
698k
1%
lOOk
1%
Terminate thermocouple reference junction in
RZ
10k
':'
close proximity to LM335.
Adlustments:
I. Apply signal in place of thermocouple and ad·
just R3 for a gain of 245.7.
2. Short non· inverting input of LM308A and out·
put of LM329B to ground.
3. Adjust RI so that VOUT ~ 2.982V @ 25°C.
4. Remove short across LM329B and adiust R2
so Ihal VOUT ~ 246 mV @ 2SoC.
LM3298
':'
R3
5k
VOUT ~ 10 mvfc
5. Remove short across thermocouple.
TL/H/569B-12
Fast Charger for Nickel-Cadmium Batteries
Differential Temperature
Sensor
r-----_....
i;~------~~---------1~-----t--------~------------~~----,
~START
15V
10k
10k
_ _ _~2Ok
200
\
Dlt
LM335 ....---.4.....--....
10k
TLlH/569B-7
THERMALLYCDUPLE~ -
-
-
-
tAdjust 01 to 50 mV greater Vz than 02.
Charge terminates on SoC temperalure rise. Couple 02 to battery.
6·27
-
-
-
lav
':'
-12V
TLlH/569B-13
Typical Applications (Continued)
Differential Temperature Sensor
15V
zalite
OUTPUT
1DDrnVfC
TLlH/5698-14
Variable Offset Thermometer*
11V
15V
It
OUTPUT
100mV/'C
75k
t Adjust for zero wRh sensor al o-e and lOT pal sel al o-e
'Adjust for zero outpul wilh lOT pol sel all we and sensor
at l00'e
*Output reads difference between lemperature and dial setting
of lOT pol
It
-!5V
TLlH/569B-15
6·28
r------------------------------------------------------------------------,
Typical Applications (Continued)
r
....
==
w
Ground Referred Centigrade Thermometer
en
......
Air Flow Detector'
r
20k
==
w
I\)
en
......
~
12k
w
OUTPUT
IOmVfC
OUTPUT -HIGH
WITH AIR FLOW
-15V
w
wen
r
....==w
en
~
r
M.lk
±1"
==
w
I\)
50K
TRIP POINT >-.t-...:;.&.
ADJUST
en
~
......
r
2k
TL/H/5698-17
'Self heating is used to detect air flow
w
==
w
en
~
-15V
TL/H/5698-16
Definition of Terms
Operating Output Voltage: The voltage appearing across
the positive and negative terminals of the device at specified conditions of operating temperature and current.
Uncalibrated Temperature Error: The error between the
operating output voltage at 10 mV;oK and case temperature
at specified conditions of current and case temperature.
Calibrated Temperature Error: The error between operating output voltage and case temperature at 10 mV;oK over
a temperature range at a specified operating current with
the 25'C error adjusted to zero.
6-29
I?JI National
~ Semiconductor
LM3911 Temperature Controller
General Description
The LM3911 is a highly accurate temperature measurement
and! or control system for use over a - 25'C to + 85'C temperature range. Fabricated on a single monolithic chip, it
includes a temperature sensor, a stable voltage reference
and an operational amplifier.
The LM3911 uses the difference in emitter-base voltage of
transistors operating at different current densities as the basic temperature sensitive element. Since this output depends only on transistor matching the same reliability and
stability as present op amps can be expected.
The output voltage of the LM3911 is directly proportional to
temperature in degrees Kelvin at 10 mVI'K. Using the internal op amp with external resistors any temperature scale
factor is easily obtained. By connecting the op amp as a
comparator, the output will switch as the temperature transverses the set-point making the device useful as an on-off
temperature controller.
The LM3911 is available in two package styles, a metal can
TO-46 and an 8-lead epoxy mini-DIP. In the epoxy package
all electrical connections are made on one side of the device allowing the other 4 leads to be used for attaching the
LM3911 to the temperature souce. The LM3911 is rated for
operation over a - 25'C to + 85'C temperature range.
Features
An active shunt regulator is connected across the power
leads of the LM3911 to provide a stable 6.8V voltage reference for the sensing system. This allows the use of any
power supply voltage with suitable external resistors.
Uncalibrated accuracy ± 10'C
Internal op amp with frequency compensation
Linear output of 10 mVI'K (10 mVI'C)
Can be calibrated in degrees Kelvin, Celsius or
Fahrenheit
• Output can drive loads up to 35V
• Internal stable voltage reference
•
•
•
•
The input bias current is low and relatively constant with
temperature, ensuring high accuracy when high source impedance is used. Further, the output collector can be returned to a voltage higher than 6.8V allowing the LM3911 to
drive lamps and relays up to a 35V supply..
• Low cost
Block Diagram
~--------,---~------------~~~v'
uv
L.....~....nDUTPUT
Typical Applications
Proportioning Temperature
Controller
Ground Referred
Centigrade Thermometer
15V
v'
yO
(laTE 3)
...
V·
..
1.50
2J3k
OUTPUT
IDmVf'C
....f"
Uk!l
H1
H•
H,
Ilk
'"
po~:~
SET
TEMPERATURE
AT10mV".
U
L.....--~--.J.J..V'v-~~~: :~::1~:ING
15V
H•
H&
H'15
Basic Temperature Controller
yO
,,: ~JV"V"H_-tIN LM3I1~UT
H'
OUTPUT*
H3
V-
'"
5.Dt*
~ ::~~~~~y
• Trims out initial zener tolerance.
-
LEO HoR H•
HEAT "OFF"
1.& ...
HZ
Uk
V-11V
HII
(NOTE!)
V(MOTEl)
• output goes negative on
temperature increase
Rs~(V+
-a.8V) kO
HEATER
Tl/H/5701-1
Nota I: CI determines proportioning frequency f :::: 2R: CI
Set output 10 read C
Note 2: RIO ~
Iv+1 + Iv-I-7V
O.OOI5A
Note 3: Efther V- or V+ can be ground.
6-30
r
3:
Co)
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Current (Extemally Set)
10mA
Output Collector Voltage, V + +
36V
Feedback Input Voltage Range
OVto +7.0V
Output Short Circuit Duration
Indefinite
- 25°C to + 85°C
Operating Temperature Range
Storage Temperature Range
- 65°C to + 150°C
Lead Temperature (Soldering, 10 seconds)
260°C
Electrical Characteristics (Note 1)
Parameter
I
I
Conditions
SENSOR
Min
I
Typ
I
Max
I
Units
Output Voltage
TA= - 25°C, (Note 2)
2.36
2.48
2.60
V
Output Voltage
TA= + 25°C, (Note 2)
2.88
2.98
3.08
V
Output Voltage
TA= + 85°C, (Note 2)
3.46
3.58
3.70
V
Linearity
AT=100°C
0.5
2
%
Long-Term Stability
0.3
%
Repeatability
0.3
%
VOLTAGE REFERENCE
Reverse Breakdown Voltage
Reverse Breakdown Voltage
Change With Current
1 mA:<=:l z:<=:5mA
1 mA:<=:l z:<=:5 mA
6.55
Temperature Stability
6.85
7.25
V
10
35
mV
20
85
mV
3.0
n
RMS Noise Voltage
Iz=1 mA
10 Hz:<=:f:<=:10 kHz
30
Long Term Stability
TA=+85°C
6.0
/LV
mV
TA=+25°C
35
150
45
250
Dynamic Impedance
OPAMP
Input Bias Current
Input Bias Current
nA
nA
Voltage Gain
RL =36k, V+ + =36V
Output Leakage Current
TA= 25°C (Note 3)
0.2
2
/LA
Output Leakage Current
(Note 3)
1.0
8
/LA
Output Source Current
VOUT:<=:3.70
2500
15000
VIV
10
/LA
Output Sink Current
2.0
mA
1V:<=: VOUT:<=:36V
Nole I: These specHications apply for -2S'C';TA'; +85'C and 0.9 mA ,;ISUPPLY';1.1 mA unless otherwise specified; CL';SO pF.
Nole 2: The outpul voltage applies to the basic thermometer configuration with the output and input terminals shorted and a load resistance of ;, 1.0 Mil. This is
the feedback sense voltage and includes errors in both the sensor and op amp. This voltage is specified for the sensor in a rapidly stirred oil bath. The output is
referred to V+ .
Note 3: The output leakage current is specified with
~ 100 mV overdrive.
Since this voltage changes with temperature, the voltage drive for turn-off changes and is
defined as VOUT (wHh output and input shorted) -100 mV. This speCification applies for VOUT=36V.
Application Hints
Although the LM3911 is designed to be totally trouble-free,
certain precautions should be taken to insure the best possible performance.
As with any temperature sensor, internal power dissipation
will raise the sensor's temperature above ambient. Nominal
suggested operating current for the shunt regulator is 1.0
mA and causes 7.0 mW of power dissipation. In free, still, air
this raises the package temperature by about 1.2°K. AIthough the regulator will operate at higher reverse currents
and the output will drive loads up to 5.0 mA, these higher
currents will raise the sensor temperature to about 19°K
above ambient-degrading accuracy. Therefore, the sensor
should be operated at the lowest possible power level.
With moving air, liquid or surface temperature sensing, selfheating is not as great a problem since the measured
media will conduct the heat from the sensor. Also, there are
many small heat sinks designed for transistors which will
improve heat transfer to the sensor from the surrounding
medium. A small finned clip-on heat sink is quite effective in
free-air. It should be mentioned that the LM3911 die is on
the base of the package and therefore coupling to the base
is preferable.
The internal reference regulator provides a temperature stable voltage for offsetting the output or setting a comparison
point in temperature controllers. However, since this reference is at the same temperature as the sensor temperature,
changes will also cause reference drift. For application
where maximum accuracy is needed an external reference
should be used. Of course, for fixed temperature controllers
the internal reference is adequate.
6-31
CD
......
......
yy-
m
;....I
r-----------------------------------------------------------------------------------------------,
Typical Performance Characteristics
Temperature
Conversion
Op Amp Input Current
T CENTIGRADE = T C
~
40
~
i!!
!Iic
273.16
5
TC =
(40
+ TF) 9 -40
TF =
(40
+ Tel "5
9
45
0.6
~
;;
TKELVIN = TK
+
i...
ill
a:
T FAHRENHEIT = T F
TK = TC
.
...
i
12
ill
a:
~
;;
T.-2S'C_
8D
cz
60
~
~
~
/
.f.·
100
'">
80
14
oS
..
100
SHUNT REGULATOR CURRENT (mAl
Reference Regulation
40
2.0
10
2.0
50
S"
'"
"...ill
~
4.0
Ie
a:
4.0 5.0 1.0 1.0 2.0 3.0 4.0 5.0
~ '------or----'
SUPPLY
SUPPLY
VOLTAOE (V)
CURRENTlmA)
...
'"
c
!
/
o
is
...
.
~
::liB
Ie
1.0
Thermal Time Constant in
Still Air
Device Temperature Rise
16
j!:"
o
DEVICE VOLTAGE (V)
24
a:
it
~a
1/
TIME (SECONDS)
",
gB
o
1/
Ii
o
1:
... 8.0
",a:
4.0
V
0.1
::!
5.0
10
~=
Dl
- 2.0
Supply Sensitivity
.....
I
TO·5
40
/
T.· 25'C
0.3
>
/ ' i-"""
SATURATION VOLTAGE (V)
(REFFEREO TO V-I
.~
DA
~
Thermal Time Constant
in Stirred Oil Bath
'"
"...
1.0
.~i~5
illa:
TEMPERATURE ('C)
/
4.0
...
25
-55 -36 -16 6.0 25 46 65 85 105 125
-40
~
8.0
/
oS 0.5
~~ "
3D
is
...
1/
c
V
:!;
20
16
~
...... ~
35
Output Saturation
Voltage
1
...
Power Supply Current
0.1
50
V
i
/'
./
~
~
~
/'
o
2.0
4.0
>
6.0
8.0
SUPPLY CURRENT (mA)
10
12
t-l~~~ra.0;.~.6~kt$IW=:t:t!~
-1.0
-2.0 ,--3.0
~~. _mll-+++-i
I--Hklf-I~
'HI-fIHHHH
10
§
...~
1.0
0.1
100
2110
TIME (PS)
300
400
10
100
1.Dk
10k
101111
FREQUENCY (Hz)
TL/H/5701-2
6-32
Schematic Diagram
v'
02
INPUT
OUTPUT
Typical Applications
(Continued)
Basic Thermometer for Negative Supply
.-_L+:....-.,......__+
I~~!~~.
Basic Thermometer
for Positive Supply
15V
v'
v'
Rs
1.Sk
I
x 103n
RS
External Frequency Compensation
for Greater Stability when Driving
Capacitive Loads
=
(V- - 6.BY)
t-----,
Rs
Uk
7.5k
OUTPUT
,OmVrK
Note: Load current to GND
is supplied through Rs
RS = (V- - 6.BV)
Increasing Output Drive
15V
r-~+;;l-_t-~~_I~OU!~~K
x 103n
Operating With External Zener for
Lower Power Dissipation
Temperature Controller With Hysteresis
+15V
15V
3.5k
R,
15V
1,5k
Rs'
1100
I
OUTPUT
1DmvrK
1NI21
lOOk
t
R,
+
20k
OUTPUT
~4f
INPUT
LM3911
I.
~ DUTPUT*
22M
~
·Depends on Zener current.
6-33
"'Output goes positive on temperature increase
tSet temperature
TLiH/5701-3
Typical Applications
(Continued)
Meter The~mometer With Trimmed Output
Thermometer With Meter Output
RI' ~
(Vz)O.OIAT
I5V
lis
Select la ,;;
19>
+
OUTPUT
H,"
1M (VZ - 0.01 TO)
v'
R2 ~ 0.01 To - laRI
la
H,'
50>
U87k
~
~~- RI
R3
Vz
LM3II'
1M
31.n
TO
la
V' - .
H2"
INPUT
H3"
Shunt regulator voltage (use 6.85)
Meter temperature span rKJ
Meter full scale current (A)
Meter zero temperature rKJ
CUrrent through RI, R2, R3 at zero
meter current (10 p.A to 1.0 mAl (A)
AT
R3'
&.Dk
OUTPUTi-"~
- R2
2VI)
(Ia,;; _R
INPUT
H,"
50>
+
la
H2'
28.21.
LM3111
2V
Ai"
-:
500'
·Values shown for:
TO
1M
~
~
·Selected as for meter thermometer except To should
300"K, AT
~
100oK,
1.0 rnA,la
~
100l'A
be 5°K more than desired and 10 = 100 p,A
"The 0.01 in the above and following equations is in units of VloK or V
and is a result of the basic O.OW/oK sensitivity of the transducer
rc,
tCalibrates TO
Ground Referred Thermometer
.---_-----_.....;~sv
RI
~
(Vz)(IOmV)(AT)
0.01 To)
RL
Ground Referred Centigrade Thermometer
~ (Vz
H'
211>
1%
R2 ~ 0.01 To -la RI
la
H2
lM3tl1
INPUT
R3
t---Ir--I--"
~ ~- RI
10
Vz
AT
TO
Vo
la
H3
OUTPUT
- R2
tOmViC
Shunt regulator voltage
Temperature span (OK)
Temperature for zero output rK)
Full scale output voltage,;; I OV
Uk
-I5V-II/Ift"o-4_-_....I
Currentthrough RI, R2, R3
at zero output voltage
(typically 100 I'A to 1.0 rnA)
7.5.
OUTPUT
30pF
"'Setzero
R2(1l)
~
00
R~ ~3
[
TH(VZ - 0.01 Tu - TL(VZ - 0.01 TH)
1
Two Terminal Temperature to Current Transducer'
+
LMI13
I
H'
30k
INPUT
R4 ~ (Vz
12k
t--1,*"""-'"
R2
H2
1
_..!..
R2
R3
Temperature for IL< KJ
Temperature for IH ( K)
Zener voltage (V)
Low temperature output current (A)
High temperature output current (A)
H4
18i.2k
IUk
I)
'Oak
1-.....~--'-IH..-4.-t
8.110
( Vz - O.OITL
+ -,-_:.:R2=--:-_L.:...
..!.. + ..!..
+'2VTO +4DV
LM3911
OUTPUT
I
[ (R2)(0.01 Tu
O.OITu(R2)
RI
H3
200
'Values shown for
100JT~ I
mA to 10 mA for IO"F to 100"F
tSettemperature
TUH/5701-4
"The 0.01 in the above and following equations is in units of VrK or V
rc, and is a result of the basic 0.01 V1 K sensitivity of the transducer
6·34
0
Typical Applications (Continued)
Over Temperature Detectors With Common Output
I5V
V'1
..
R,
1.5k
7.Sk
..
R,
7.5k
7.511
R,
5.
OUTPUT
+
R.
R.
OU:'"T
OUTPUT
~ INPUT
~ INPUT
lM3911
R!
J
R.
OU:'"T
~ INPUT
OUTPUT
LM3911
R!
.l.
.1.
..
Rl
Trip Po.nt ~ Vz Rl + R2
~ INPUT
R'
R'
+
R.
LMl911
lM3911
.1.
J
.l.
Rs ~
(V
+ -6.BV)
0.001 A
+
6.BV
Rl + R2
TL/H/5701-5
Two-Wire Remote A.C. Electronic Thermostat (Gas or Oil Furnace Control)
lN451
~II
S.C.A.S.
Cl06A2
26VAC
CONTROL
TRANSFORMER
60Hl
OR
TRIM
IR[DBA2
SET t
T~~~~~~~~~~~-4
L..._,---'
J:~k
4W-WW
Uk
4.7M
lN451
lD.III
1%
12k
510
REMOTE
TL/H/5701-B
·Solenoid or 6-15W heater
tPot will provide about a 50c F to gO°F setting range. The trim resistor (1 OOk) is selected
to bring 70c F near the middle of the pot rotation.
seR heating, by proper positioning, can preheat the sensor giving control anticipation as is presently used in many home thermostats.
1---9-------O}LOAO
Electronic Thermostat
BLACK
1
tf~v
SENSITIVE GATE TRIAC
+
IGT~,;5
60 Hz
'10
!.ow
50k
mA
RCA T2300, 40529
LMJ911
OR SIMILAR
150t
Uk
·8et temperature
WHITE
5.111
6-35
tSCA turns on power to fan or
cooler when temperature in·
creases.
TL/H/5701-9
-_
~
~
r-----------------------------------------------~----------------------------------~
Typical Applications (Continued)
Three-Wire Electronic Thermostat
IN4004
Uk
LOAD (HEATER: 10 mA TO 3&A)
12k
181
ll2W
l&.1k
lK'
10k
lGM
>.....- ...----I--'w\/--..
2NS064
TO 120VAC
16.511
1%
1.5M
'Divider is set for a nominal O'C-125"C range.
Wire wound reststors will provide maximum
temperature stability.
"Almost any TRIAC rated 1 to 35 amperes
usable wHh appropriate load.
Differential Thermometer
+IIV
112
I&Ok
Kelvin Thermometer With .
Ground Referred Output
OUTPUT
R4
410
liV
v'
R.
3.011
~
v'
10k
r-----''-'+'----1
~:r
IN
D.l%
LM3811
INPUT
*L
1.00'
oUT~Lr~
NO.1
V-
IOmvrK
Rl
111,1"
el
v'
IN
LU3an
NO.2
OUT
v-
All
OUTPUT
RS
Uk
Uk
10k
D.l%
Rs
= Vs+
- 6.BV x l03n
2
2Il010
+ R2
f
+16V
-1 V
~~:O
) (T2 - T"" 1---+; TRIM
RI
Output can swing ± 3V at ± 50 p.A
with low output impedance
-ISV
"The 0.01 in the above equation is in units of W'K or VI'C, and is a result
of the basic 0.Q1 VrK sensttivity of the tranaducer .
= 0.01
VOUT
R,
Connection Diagrams
TQ-46 Package
Dual-tn-Line Package
OmuT~V-
Ie
INPUT~v'
Ie
Ne
TOP VIEW
Ne
Nob: Pin 4canalCtld to CUI.
TOP VIEW
Order Number LM3911N
See NS Package N08E
6-36
TLlH!5701-B
TLlH/5701-7
Order Number LM3911H-46
See NS Package H04A
Section 7
Voltage References
,.
Section 7 Contents
Voltage Reference Selection Guide. .. . .. .. .. .. . . . . .. . . . .. . . . . .. . . . .. ... .. . . . .. . . ... . .
LH0070 Series BCD Buffered Reference. . ... . . . . . . .. . . . .. . .. . .. . . ... ... .. . .. . . . . ... . .
LH0071 Series Precision Buffered Reference. . . .. . . . .. . .. . . . . . . .. . .... . .. ... . .. . . . . . . .
LH7070 Series Precision BCD Buffered Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LH7071 Series Precision Binary Buffered Reference. .. . . . .. . . .. .. . . ... ... .. . . . .. . . .. . ..
LM113/LM313 Reference Diode. .. ... .. . . .. . . . . . . .. . . . .. . . . . .. . . ... ... .. . . . . . . . ... . .
LM129/LM329 Precision Reference..................................................
LM134/LM234/LM334 3-Terminal Adjustable Current Sources. . . .. . . ... ... .. . . . . . . . . . . . .
LM136-2.5/LM236-2.5/LM336-2.5V Reference Diodes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM136-5.0/LM236-5.0/LM336-5.0V Reference Diodes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LM168/LM268/LM368 Precision Voltage References...................................
LM169/LM369 Precision Voltage References..........................................
LM185-1.2/LM285-1.2/LM385-1.2 Micropower Voltage Reference Diodes. . . . . . . . . . . . . . . . .
LM185-2.5/LM285-2.5/LM385-2.5 Micropower Voltage Reference Diodes. . . ... . .. . . . . . . . .
LM185/LM285/LM385 Adjustable Micropower Voltage References. . . . . . . . . . . . . . . . . . . . . . .
LM199/LM299/LM399/LM3999 Precision References..................................
LM368-2.5 Precision Voltage Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-2
7-3
7-7
7-7
7-11
7-11
7-16
7-19
7-24
7-32
7-39
7-46
7-52
7-62
7-69
7-75
7-82
7-91
~NatiOnal
Semiconductor
Voltage Reference Selection Guide
Shunt Type
Reverse Breakdown
Voltage (VR)
Device
Temperature
Operating
Voltage
Drift
Tolerance
Temp.
Over
Range- Max, TA = 25'C ppml'C
(Max)
Range
1.22
1.22
1.22
1.22
LMl13-2
LMl13-1
LMl13
LM313
M
M
M
C
±1%
±2%
±5%
±5%
50 (Typ) -55'Cto + 125'C
50 (Typ) -55'Cto + 125'C
100 (Typ) - 55'C to + 125'C
100 (Typ)
O'Cto +70'C
1.235
1.235
1.235
1.235
1.235
1.235
1.235
1.235
1.235
1.235
LM185BX-1.2
LM185BY-l.2
LM185-1.2
LM285BX-1.2
LM285BY-1.2
LM285-1.2
LM385BX-l.2
LM385BY-1.2
LM385B-l.2
LM385-1.2
M
M
M
I
I
I
C
C
C
C
±1%
±1%
±1%
±1%
±1%
±1%
±1%
±1%
±1%
+2%, -2.4%
30
50
150
30
50
150
30
50
150
150
1.24 to 5.3 (Adj.)
1.24 to 5.3 (Adj.)
1.24 to 5.3 (Adj.)
1.24 to 5.3 (Adj.)
1.24 to 5.3 (Adj.)
1.24 to 5.3 (Adj.)
1.24 to 5.3 (Adj.)
1.24 to 5.3 (Adj.)
1.24 to 5.3 (Adj.)
LM185B
LM185BX
LM185BY
LM285BX
LM285BY
LM285
LM385BX
LM385BY
LM385
M
M
M
I
I
I
C
C
C
±1%
±1%
±1%
±1%
±1%
±2%
±1%
±1%
±2%
1.24 to 6.3
1.24 to 6.3
1.24 to 6.3
1.24 to 6.3
(Adj.)
(Adj.)
(Adj.)
(Adj.)
tLM611M
LM611AI
LM6111
LM611C
M
I
I
C
1.24 to 6.3
1.24 to 6.3
1.24 to 6.3
1.24 to 6.3
(Adj.)
(Adj.)
(Adj.)
(Adj.)
ttLM613M
LM613AI
LM6131
LM613C
1.24 to 6.3 (Adj.)
1.24 to 6.3 (Adj.)
1.24 to 6.3 (Adj.)
1.24 to 6.3 (Adj.)
2.49
2.49
2.49
2.49
2.49
2.49
Output
Operating
Dynamic
Current Range, IR Impedance
(Typ)
500 ",A to 20 rnA
500 ",A to 20 rnA
500 ",A to 20 rnA
500 ",A to 20 rnA
0.8
0.8
0.8
0.8
-55'C to + 125'C
- 55'C to + 125'C
-55'Cto +125'C
- 40'C to + 85'C
-40'Cto + 85'C
-40'C to +85'C
O'Cto +70'C
O'Cto +70'C
O'Cto +70'C
O'Cto +70'C
10 ",A to 20 rnA
10 ",A to 20 rnA
10 ",A to 20 rnA
10 ",A to 20 rnA
10 ",A to 20 rnA
10 ",A to 20 rnA
15 ",A to 20 rnA
15 ",A to 20 rnA
15 ",A to 20 rnA
15 ",A to 20 rnA
1
1
1
1
1
1
1
1
1
1
150
30
50
30
50
150
30
50
150
- 55'C to + 125'C
- 55'C to + 125'C
- 55'C to + 125'C
-40'Cto +85'C
-40'Cto +85'C
-40'Cto +85'C
O'Cto +70'C
O'Cto +70'C
O'Cto +70'C
10 ",A to 20 rnA
10 ",A to 20 rnA
10 ",A to 20 rnA
10 ",A to 20 rnA
10 ",A to 20 rnA
10 ",A to 20 rnA
13 ",A to 20 rnA
13 ",A to 20 rnA
13 ",A to 20 rnA
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
±0.4%
±0.6%
±0.6%
±2.0%
20
20
80
150
-55'C to + 125'C
-40'C to + 85'C
-40'C to + 85'C
O'Cto +70'C
16 ",A to 10 rnA
16 ",A to 10 rnA
16 ",A to 10 rnA
16 ",A to 10 rnA
0.27
0.27
0.27
0.27
M
I
I
C
±0.4%
±0.6%
±0.6%
±2.0%
20
20
80
150
-55'Cto + 125'C
- 40'C to + 85'C
- 40'C to + 85'C
O'Cto +70'C
16 ",A to
16 ",A to
16 ",A to
16 ",A to
10 rnA
10 rnA
lOrnA
10 rnA
0.2
0.2
0.2
0.2
:j:LM614M
LM614AI
LM6141
LM614C
M
I
I
C
±0.4%
±0.6%
±0.6%
±2.0%
20
20
80
150
-55'Cto + 125'C
-40'Cto +85'C
-40'Cto +85'C
O'Cto +70'C
16 ",A to
16 ",A to
16 ",A to
16 ",A to
10 rnA
10 rnA
10 rnA
10 rnA
0.2
0.2,
0.2
0.2
LM136A
LM136
LM236A
LM236
LM336
LM336B
M
M
I
I
I
C
±1%
±2%
±1%
±2%
±4%
±2%
72
72
72
72
54
54
- 55'C to + 125'C
- 55'C to + 125'C
- 25'C to + 85'C
- 25'C to + 85'C
O'Cto +70'C
O'Cto +70'C
400 ",A to 10 rnA
400 ",A to 10 rnA
400 ",A to 10 rnA
400 ",A to 10 rnA
400 ",A to 10 rnA
400 ",A to 10 rnA
7-3
0.4
0.4
0.4
0.4
0.4
0.4
II
CI)
'tJ
·s
CJ
Shunt Type (Continued)
c
o
1;
CI)
Reverse Breakdown
Voltage (VR)
Device
iii
(/)
CI)
u
c
~
CI)
Q;
IX:
CI)
en
oS
~
Temperature
Operating
Voltage
Drift
Temp.
Tolerance
Over
ppml'C
Range' Max, TA = 2S·C
(Max)
Range
Output
Operating
Dynamic
Current Range, IR Impedance
(Typ)
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
LM185BX-2.5
LM185BY-2.5
LM185B-2.5
LM285BX-2.5
LM285BY-2.5
LM285-2.5
LM385BX-2.5
LM385BY-2.5
LM385B-2.5
LM385-2.5
M
M
M
I
I
I
C
C
C
C
±1.5%
±1.5%
±1.5%
±1.5%
±1.5%
±1.5%
±1.5%
±1.5%
±1.5%
±3%
30
50
150
30
50
150
30
50
150
150
-55·Cto +125·C
-55·Cto + 125·C
-55·Cto + 125·C
- 40·C to + 85·C
- 40·C to + 85·C
-40·Cto +85·C
O·Cto +70·C
O·Cto +70·C
O·Cto +70·C
O·Cto +70"C
20 /LA to 20 rnA
20 /LA to 20 mA
20 /LA to 20 rnA
20 /LA to 20 mA
20 /LA to 20 mA
20 /LA to 20 mA
20 /LA to 20 mA
20 /LA to 20 mA
20 /LA to 20 mA
20 /LA to 20 rnA
1
1
1
1
1
1
1
1
1
1
5.0
5.0
5.0
5.0
5.0
5.0
LM136A
LM136
LM236A
LM236
LM336B
LM336
M
M
I
I
C
C
±1%
±2%
±1%
±2%
±2%
±4%
72
72
72
72
54
54
-55·Cto + 125·C
-55·Cto + 125·C
- 25·C to + 85·C
-25·Cto + 85·C
O·Cto +70·C
O·Cto +70·C
400 /LA to 10 rnA
400 /LA to 10 rnA
400 /LA to 10 rnA
400 /LA to 10 rnA
400 /LA to 10 rnA
400 /LA to 10 mA
0.8
0.8
0.8
0.8
0.8
0.8
6.9
6.9
6.9
6.9
6.9
6.9
LM129A
LM129B
LM129C
LM329B
LM329C
LM329D
M
M
M
C
C
C
+3%,-2%
+3%,-2%
+3%,-2%
±5%
±5%
±5%
10
20
50
50
20
100
- 55·C to + 125·C 600 /LA to 15 rnA
- 55·C to + 125·C 600 /LA to 15 mA
- 55·C to + 125·C '600 /LA to 15 mA
O·Cto +70·C
600 /LA-to 15 mA
O·Cto +70"C
600 /LA to 15 mA
O·Cto +70·C
600 /LA to 15 rnA
6.95
6.95
6.95
6.95
6.95
6.95
6.95
6.95
6.95
6.95
LM199A
LM199A-20
LM199
LM299A
LM299A-20
LM299
LM399A'
LM399A-50
LM399
LM3999
M
M
M
I
I
I
C
C
C
C
'C (Commercial) ~ O'C to 7fY'C, I (Industrial)
M (Military) ~ - S5"C to + 12S'C
~
- 55·C to + 125·C 500 /LA to 10 rnA
±2%
0.5
Same as LM199A with 20 ppm guaranteed long term drift.
±2%
- 55·C to + 125·C 500 /LA to 10 mA
1.0
-25·Cto +85·C 500 /LA to 10 mA
±2%
0.5
Same as LM299A with 20 ppm guaranteed long term drift.
±2%
- 25·C to + 85·C 500 /LA to 10 rnA
1
±5%
1
O·Cto +70·C
500 /LA to 10 rnA
Same as LM399A with 50 ppm guaranteed long term drift.
±5%
O·Cto +70·C
2
500 /LA to 10 rnA
O·Cto +70·C
±5%
5
600 /LA to 10 mA
-25"C to +8S'C for the LM236 and LM299, I
~
0.6
0.6
0.6
0.8'-0.8
0.8
0.5
0.5
0.5
0.5
0.5
0.5
0.6
-4fY'C to +8S'C for all others.
tLM611 has on-board Op Amp.
ttLM613 has on-board Dual Op Amp and Dual Comparator.
*LM614 has on-board Quad Op Amp.
Current References
Output Current
Range
2/LAt010mA
2 /LA to 10 rnA
2/LAt010mA
2 /LA to 10 mA
2/LAt010rnA
2,..At010rnA
2,..At010rnA
Device
LM134
LM134-3
LM134-6
LM234
LM234-3
LM234-6
LM334
1 mAtoSmA
Operating
Voltage
Range
Set Current
Temperature
Dependence'
±5%
N/A
N/A
±5
N/A
N/A
±8%
Wt040V
1Vt040V
1V to 40V
1Vt040V
1Vt040V
1Vt040V
1V to 40V
0.96T to 0.1 04T
0.98T to 0.1 02T
0.971 to 0.1 03T
0.96T to 0.1 04T
0.98T to 0.1 02T
0.97T to 0.1 03T
0.96T to 0.1 04T
Set Current Error
Operating
Temperature
Range
2 /LA to 10 /LA
10 /LA to 1 mA
- 55·C to + 125·C
- 55·C to + 125·C
-55·C to + 125·C
~25·Cto +100·C
- 25·C to + 100·C
- 25·C to + 100·C
O·Cto +70·C
±8%
N/A
N/A
±8%
N/A
N/A
±12%
±3%
±1%
±2%
±3%
±1%
±2%
±6%
'Set current changes linearly with temperature at a rate of O.33%I·C,
7-4
o<
;:
Series Type (Buffered Output)
Output
Voltage
Device
ca
(I)
Temperature
Oper.
Voltage
Drift
Temp:
Tolerance
Over
Range" Max, TA = 25'C ppml'C
(Max)
Range
Load Reg.
ppm/mA
Operating
Current
Range
Quiescent
Current
(mA)
::D
!e.
(I)
C;;
::s
0.2 (Adj) tLM10
0.2 (Adj) tLM10B
0.2 (Adj) tLM10C
M
I
C
±2.5%
±2.5%
±5.0%
20typ
20typ
30typ
-55'Cto + 125'C
-25'Cto +85'C
O'Cto +70'C
100
100
100
OmAto +1 mA
OmAto +1 mA
OmAto +1 mA
0.27
0.27
0.30
2.5
2.5
LM368Y-2.5
LM368-2.5
C
C
±0.2%
±0.2%
20
30
O'Cto +70'C
O'Cto +70'C
25
25
OmAto+l0mA
OmAto+l0mA
0.55
0.55
5.0
5.0
5.0
5.0
LM168BY-5.0
LM268BY-5.0
LM368BY-5.0
LM368-5.0
M
I
C
C
±0.05%
±0.05%
±0.1%
±0.1%
10
15
20
30
- 55'C to + 125'C
- 40'C to + 85'C
O'Cto +70'C
O'Cto +70'C
10
10
10
10
-10mAto +10mA
-10mAto+l0mA
-10 mA to +10 mA
-10 mA to +10 mA
0.35
0.35
0.35
0.35
10
10
10
10
10
10
10
10
10
10
10
LM169B
LH0070-2
LM169
LH0070-0
LH0070-1
LM369C
LM369
LM369B
LM368Y-l0
LM368-10
LM369D
M
M
M
M
M
C
C
C
C
C
C
±0.05%
±0.05%
±0.05%
±0.1%
±0.1%
±0.05%
±0.05%
±0.05%
±0.1%
±0.1%
±0.1%
3
8
5
40
20
10
5
3
20
30
30
- 55'C to + 125'C
- 25'C to + 25'C
- 55'C to + 125'C
- 25'C to + 25'C
- 25'C to + 25'C
O'Cto +70'C
O'Cto +70'C
O'Cto +70'C
O'Cto +70'C
O'Cto +70'C
O'Cto +70'C
8
60
8
60
60
8
8
8
10
10
8
-10mAto+10mA
0~05 mA
-10mAto +10mA
OmAt05mA
OmAt05mA
-10mAto +10mA
-10mAto +10mA
-10 mA to +10 mA
-10mAto +10mA
-10 mA to +10 mA
-10mAto +10mA
1.8
5
1.8
5
5
1.8
1.8
1.8
0.35
0.35
2
10.24
10.24
10.24
LH0071-2
LH0071-1
LH0071-0
M
M
M
±0.05%
±0.1%
±0.1%
8
20
40
- 40'C to + 85'C
-40'Cto +85'C
-25'Cto +25'C
60
60
60
OmAt05mA
OmAt05mA
OrnAt05mA
5
5
5
n
(I)
en
(I)
CD
2-
O·
::s
Q
c
a:
(I)
'C (Commercial) = O'C to 7rrC.1 (Industrial) = -40'C to + 85'C, M (Military) = -55'C to +125'C
tAeference has on·board Op Amp.
Low Current Reference Diodes
Output
Voltage
Device
3.0
3.3
3.6
3.9
LM103-3.0
LM103-3.3
LM103-3.6
LM103-3.9
Operating
Temp.
Range'
Voltage
Tolerance
Max, T A = 25'C
M
M
M
M
±10%
±10%
±10%
±10%
Temperature
Drift
ppml'C
(Max)
-1700
-1500
-1400
-1300
Over
Range
- 55'C to
-55'Cto
-55'C to
- 55'C to
+ 125'C
+ 125'C
+ 125'C
+ 125'C
Operating
Current Range, IR
Output
Dynamic
Impedance
(Typ) .
10,..A to 10 rnA
10,..A to 10 rnA
1O,..A to 10 rnA
1O,..Atol0rnA
25
25
25
25
'M (Military) = -55'Cto + 125'C
£I
7-5
"Reference Grade" Voltage Regulators*
Output
Voltage
Device
Output
Voltage
Output
Variation
Load Reg. Line Reg.
Quiescent
Tolerance
Current
Current
Over Operating ppm/mA ppm/V
(Max)
Max, T A = 25·C
Range
Operating
Temperature
Range
- 55·C to + 150·C
LP2951
LP2951AC -40·Cto + 125·C
LP2951C -40·Cto + 125·C
±0.5%
±0.5%
±1%
±0.5%
±0.5%
±1%
100
100
200
42
42
83
100 rnA
100 rnA
100 rnA
120 p.A
120 p.A
120p.A
Programmable:
LH0075
5V,6V,10V, 12V,15V LH0075C
- 55·C to + 125·C
O·Cto +70·C
±0.5%
±1%
±0.3% (Typ)
±0.14% (Typ)
38
76
200
400
200 rnA
200 rnA
8mA
lOrnA
Programmable
-5V, -6V, -10V
-10V, -15V
LH0076
LH0076C
-55·Cto +125·C
O·Cto +70·C
±0.5%
±1%
±0.3% (Typ)
±0.14% (Typ)
38
38
200
400
200 rnA
200 rnA
15mA
15mA
5V
5V
LP2950AC - 40·C to + 125·C
LP2950C -40·C to + 125·C
±0.5%
±1%
±0.5%
±1%
100
200
42
83
100mA
100 rnA
120 p.A
120 p.A
Adjustable:
1.235V to 30V
·For more information on these circuits, refer to the Continuous Voltage Regulators section of the General Purpose Unear Devices Databook.
..
. ,.--
..
"
7-6
r::I:
o
o
......
o
......
r::I:
o
o
......
J?A National
~ Semiconductor
LH0070 Series Precision BCD Buffered Reference
LH0071 Series Precision Binary Buffered Reference
....
General Description
The LH0070 and LH0071 are precision, three terminal, voltage references consisting of a temperature compensated
zener diode driven by a current regulator and a buffer amplifier. The devices provide an accurate reference that is virtually independent of input voltage, load current, temperature
and time. The LH0070 has a 10.000V nominal output to
provide equal step sizes in BCD applications. The LH0071
has a 10.240V nominal output to provide equal step sizes in
binary applications.
them ideal choices as reference voltages in precision D to A
and A to D systems.
Features
III Accuracy output voltage
III
III
The output voltage is established by trimming ultra-stable,
low temperature drift, thin film resistors under actual operating circuit conditions. The devices are shortcircuit proof in
both the current sourcing and Sinking directions.
II
III
IJ
10V±0.02%
LH0070
10.24V ± 0.02%
LH0071
Single supply operation
11.4V to 40V
Low output impedance
0.20
Excellent line regulation
0.1 mVIV
20 p,Vp-p
Low zener noise
3-lead TO-S (pin compatible with the LM109)
Short circuit proof
Low standby current
3 mA
The LH0070 and LH0071 series combine excellent long
term stability, ease of application, and low cost, making
III
Equivalent Schematic
Connection Diagram
I:J
r-----oV'N
.J
TO-S Metal Can Package
".mi:f·~'
VDUT
Dl
.2
BOTTOM VIEW
TL/H/5550-7
Order Number LH0070-0H, LH0071-0H, LH0070-1H,
LH0071-1 H, LH0070-2H or LH0071·2H
See NS Package Number H03B
J
GND
(CASEI
TL/H/5550-1
Typical Applications
Statistical Voltage Standard
'Output Voltage Fine Adjustment
--_P-----....-----,
.15Vo-. . .
+ISV
100
!!------OVOUT
100
~_ _ _ _ _ _ _ _ _....~'~D°lf__.---O~~~T
OPTlO.AL
r-'Wlf_.....-JI/I/'v--.A,/l/'v-.....-o -15V
+
T
TL/H/5550-6
'Note: The oulpul of Ihe LH0070 and LH0071 may be adiusled 10 a precise voltage by using the above circuil since the supply currenl of Ihe devices is
relatively small and constant with temperature and input voltage. For the circuit shown. supply sensitivities are degraded slightly to 0.01 O/O/V change in VOUT
for changes in V,N and V-.
An addilionallemperalure drift of 0.0001 %I"C is added due 10 Ihe varialion of supply current wilh lemperalure of Ihe LH0070 and LH0071. Sensilivity 10 Ihe
value of R1, R2 and A3 is less than 0.001 %1%.
7-7
PI
.........
o
o
:z::
....I
......
~
o
o
:z::
....I
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
(Note 4)
Supply Voltage
40V
Power Dissipation (See Curve)
600mW
Short Circuit Duration
Output Current
Operating Temperature Range
Storage Temperature Range
Lead Temp. (Soldering, 10 seconds)
Continuous
±20mA
- 55·C to + 125·C
-65°C to ±150"C
300·C
Electrical Characteristics (Note 1)
Parameter
Conditions
Min
Output Voltage
LH0070
LH0071
TA=25·C
Output Accuracy
-0, -1
-2
TA=25·C
Output Accuracy
-0, -1
-2
TA= -55·C, 125·C
Output Voltage Change With
Temperature
-0
-1
-2
(Note 2)
Line Regulation
-0, -1
-2
13V,;;VIN,;;33V, Tc=25°C
Input Voltage Range
RL = 50kO
Load Regulation
omA,;;IOUT';;5 mA
Quiescent Current
13V,;;VIN,;;33V,IOUT=0 mA
Max
10.000
10.24
±0.03
±0.02
AVIN= 20V From 23VTo 33V
Output Noise Voltage
BW=0.1 Hz To 10 Hz, TA=25·C
Ripple Rejection
f= 120 Hz
Output Resistance
1
Units
V
V
±0.1
±0.05
%
%
±0.3
±0.2
%
%
±0.02
±0.01
±0.2
±0.1
±0.04
%
%
%
0.02
0.01
0.1
0.03
%
%
40
V
11.4
Change In Quiescent Current
Long Term Stability
-0, -1
-2
Typ
0.01
0.03
%
3
5
mA
0.75
1.5
mA
20
/LVp,p
0.01
%/Vp.p
0.2
0.6
0
±0.2
±0.05
%/yr.
%/yr.
TA= 25·C (Note 3)
Thermal Resistance
Tj = 150·C
·C/W
IIja (Junction to Ambient)
200
·C/W
lIie (Junction to Case)
100
Note 1: Unless otherwise specHied, these specifications apply for VIN= IS.0V, RL = 10 kll, and over the temperatuns range of -S5"CS:TAS: + 125·C.
Note 2: This specHication is the difference in output voltage measured at TA = B5"C and TA= 2S'C or TA= 2S'C and TA= - 25"C with nsadings taken after test
chamber and device-under-test stabilization at temperature using a suitable precision voltmeter.
Note 3: This parameter is guaranteed by design and not tested.
Note 4: Refer to the following RETS drawings for military specifications:
RETSOO70·0H for LH0070·0H
RETS0071·0H for LH0071·0H
RETSOO70·1H for LH0070·1H
RETS0071·1H for LH0071·1H
RETS0070·2H for LHOO70·2H
RETSO071·2H for LHOO71·2H
7·8
r
::J:
o
Typical Performance Characteristics
100
iz
co
~
BOD
Maximum Power Dissipation
Quiescent Current vs Input
Voltage
- 1\:.'
_!A"-55'C
TA' +25'C f'..,
-TA"+125'Cl "-
IDD'C
-W' TJI~AXI"'5D'C
9
2alrC
IA" -W
I\..
SOD
...... 1-'"
p- I"'""
400
iii
is lDD
i!'"
~
"-
200
100
n
~
~
"
100
us
--
.> .....
.-
500
0
it-
~ -SOD
1,/
~a
.
500
S -5110
~co
f-+-+-+-+-+-+--I
10
15
20
25
3D
-25
l5
::J:
o
o
...
........
sa
15
100 125
Output Short Circuit
Characteristics
1 1 1
1 1 1
I,..
25
CASE TEMPERATURE I'CI
INPUT VOLTAGE IVI
la r--+-~~r-Tt-+---I
LI
Cl'" lDpF
~
~
a.2
........
1.1
Step Load Response
~
a.l r---r---T:"'-"---r-~-"--'
.....
o
o
.......
r
I
AMBIENT TEMPERATURE I'CI
~
Normalized Output Voltage
vs Temperature
1 1J
1 1 1
CL" 0.01 #-IF
"""
DELTA CURRENT;; 5 m A t - t t
PULSE WIDTH" 2#011
10
TIME (PI)
IS
2a
25
3D
OUTPUT CURRENT ImAI
TLlHI5550-2
Noise Voltage
10.,V
VERT;~
HORIZ:~
DlV.
BW=O.1 Hz TO 10Hz
TUH/5550-6
Typical Applications (Continued)
Expanded Scale AC Voltmeter
IN4004
14D-180VPEAK
30k
47k
,W
NDMINAl
111Vrms
AC LINE
IDjJF
+
II
Ik
1"'-.........NIr-... <,DOV CAL
zoov
3Dk
3k
1/4W
TLIHI5550-4
7-9
....
l"'e
e
%:
..J
~
e
e
%:
..J
Typical Applications (Continued)
Dual Output Bench Power Supply
+~~-------,------~-----,------------,
27-3ZVDC
RAW INPUT
,.....'II\,.......___J>/'''''_ _ _-+__+-__
..:::.,O~~::~Tl
47'
Precision Process Control Interface
, - - - - - - - - - -......>--....- - - - + I 5 V
4-20m"0
INPUT ~
1m
.".
Vour IOV FOR 20 mA
fOOk
IIVFOR4mA
",---+---15V
BOlk
249k
'"
ZERO
.".
'"
Boosted Reference For
Low Input Voltages
Negative 10V Reference
Oo-....--'""1o--o+IZV
56011
1-=-......1--0 Your
~--OYour
-15Y
TLIHI5550-5
7-10
r--------------------------------------------------------------------------------,
r::I:
.......
o.......
~National
o
......
~ Semiconductor
r-
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.......
o.......
LH7070 Series Precision BCD Buffered Reference
LH7071 Series Precision Binary Buffered Reference
....
General Description
The LH7070 and LH7071 are precision, three terminal, voltage references consisting of a temperature compensated
zener diode driven by a current regulator and a buffer amplifier. The devices provide an accurate reference that is virtually independent of input voltage, load current, temperature
and time. The LH7070 has a 10.000V nominal output to
provide equal step sizes in BCD applications. The LH7071
has a 10.240V nominal output to provide equal step sizes in
binary applications.
The output voltage is established by trimming ultrastable,
low temperature drift, thin film resistors under actual operating circuit conditions. The devices are short-circuit proof in
both the current sourcing and sinking directions.
Equivalent Schematic
The LH7070 and LH7071 series combine excellent long
term stability, ease of application, and low cost, making
them ideal choices as reference voltages in precision D to A
and A to D systems.
Features
• Accurate output voltage
- LH7070
-LH7071
• Single supply operation
• Low output impedance
• Excellent line regulation
• Low zener noise
II Short circuit proof
II Low standby current
10V ±0.03%
10.24V ±0.03%
II.4V to 40V
0.20
0.2 mVIV
20,..Vp-p
3 mA
Connection Diagram
2
r----OVIN
R3
...----I~
6
Ne..! •
~NC
VIN.l
LNC
Nc.l
!..VOUT
loNc
GNO...!
_ A / > - + - O VOUT
r-;,r
TLlK/10032-2
Top View
Rl
Order Number LH7070CN or LH7071CN
See NS Package Number NOSE
R2
4
GNO
(CASE)
TL/K/10032-1
II
7-11
........
....:::co
..J
~
....:::co
..J
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
40V
Power Dissipation (See Curve)
800mW
Short Circuit Duration
Output Current
±20mA
- 25'C to + 85'C
-65'C to + 150'C
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 Sec.)
300'C
Continuous
Electrical Characteristics (Note 1)
Parameter
Output Voltage
Conditions
Min
TA = 25'C
LH7070
LH7071
Output Accuracy
TA = 25'C
LH7070, LH7071
Output Accuracy
TA = - 25'C to
Output Voltage Change
with Temperature
(Notes2,3)
Typ
Max
10.000
10.240
±0.03
+ 85'C (Note 3)
Line Regulation
13V ~ VIN ~ 33V, TA = 25'C
Input Voltage Range
Load Regulation
Quiescent Current
Change in Quiescent Current
Output Noise Voltage
Ripple Rejection
Output Resistance
RL = 50 kn
o rnA ~ lOUT ~ 5 rnA
13V ~ VIN ~ 33V,IOUT = 0 rnA
aVIN = 20Vfrom 13Vt033V
BW = 0.1 Hz to 10 Hz, TA = 25'C
f = 120Hz
Long Term Stability
TA = 25'C (Note 3)
Note 1: Unless otherwise specified, these specifications apply for VIN
~
0.02
11.4
1
0.01
2
0.75
20
0.01
0.2
Units
V
V
±0.1
%
±0.3
%
±0.14
%
0.1
0/0
40
0.03
3
1.5
V
%
rnA
rnA
,,"Vp_p
%lVp_p
0.6
n
±0.2
%/yr.
lS.0V, RL = 10 kil, and over the temperature range of -2S'C ,; TA ,; +8S'C.
Note 2: This specification is the difference in output voltage measured at TA ~ 8S'C and TA = 25'C or TA ~ 2S'C and TA = - 2S'C with readings taken after test
chamber and device-under-test stabilization at temperature using a suitable precision voltmeter.
Note 3: This parameter is guaranteed by design and not tested.
7-12
r-
::r:
Typical Performance Characteristics
.......
o
o
......
r-
.......
Maximum
Power Dissipation
Quiescent Current vs
Input Voltage
OS
0.8
TA=-25OC
l=+25OC ..... C"-.....
A=+85OC
\
0.7
>--..... r-: K
1\
0.6
'I.
05
0.4
\
= 1000cj\\ ~
\
0.3
0.2
,
20
40
60
60
r-
oV
o
~
L..I
~
0
-500
~
§!
500
0
5 -500
1=
::>
0
1
~.2I-+-+-I-+-+-I--1
10
15
20
25
30
-50 -25
35
__L-~~~
50 75 100 125
25
Output Short Circuit
Characteristics
12
1 1
3V:S VIN:S 30V
,...., -I111
II'"
0
CASE TEMPERATURE (OC)
INPUT VOLTAGE (V)
10
~
Q
>
DELTA CURRENT=5mA
PULSE WIDTH = 21'S
5
1 1
0
IJ
1 1
o
o
TIME (),.)
\
r\
~ -\
\\ \
\' \
5
c.. =101'F
"-
TA
TA =+25OC:---\
TA=-25~..........
~
1 1
1 1
,...
=1+85~-..\
£
c.. =O.OII'F
~
~
0.0
~.3L-~-L~
5
Load Transient
Response
z
0.1
i--O·
I
1
100 120 140
500
~
;:Z"
::>0
~~
~
.-
0.21-+-+-1-+-+-1--1
~'"
AMBIENT TEMPERATURE (OC)
!
---
~
::r:
QQ
I
I
O.1
o
o
I~
~
Normalized Output Voltage
vs Temperature
0.3,-..,--,--,---,-.-,--,
10
15
20
25
30
OUTPUT CURRENT (mA)
TL/K/l0032-5
Noise Voltage
VERT:
10;lV
DiY."
HORIZ:~
DIY.
TL/K/l0032-6
fI
7-13
..-
....
....
::I:
o
Typical Applications
...I
Statistical Voltage Standard
......
o
~
::I:
'Output Voltage Fine Adjustment
+15V
+15Vo--r---....- - - -.....- - - - - .
100
...I
P-------oVOUT
100
100
L----------'WIr-+--ob~~JT
I
OPTIONAL
+
TL/K/l0032-3
TUK/10032-4
'Note: The output of the LH7070 and LH7071 may be adjusted to
a precise voltage by using the above circuit since the sup·
ply current of the device is relatively small and constant
with temperature and input voltage. For the circuit shown,
supply sensitivilies are degraded slightly to 0.01 %IV
change in VOUT for changes in V,N and V-.
An additional lemperature drift of 0.0001 %I"C is added
due to the variation of supply current with temperature of
Ihe LH7070 and LH7071. SensRivily to the value of AI, A2
and AS is less than 0.001 %1%.
Expanded Scale AC Voltmeter
lN4004
14D-lI10VPEAI(
30k
41k
'W
+
NOMINAL
117V.ntS
AC lIIIE
10"F
20DV
F-....-'lN......... ('oov
" CAL
30'
3k
114W
TL/K/l0032-7
Dual Output Bench Power Supply
+--.---------1-------------~~------------_,
21-32 Vue
RAW INPUT
M.-....---~"",.,----+--+----""O ~~::~T I
r-......
47'
TUK/l0032-B
7-14
Typical Applications
(Continued)
Precision Process Control Interface
r--------------..--..- - - - . , 5 V
40-200 mV
FROM 2 WIRE TRANSMITTER
SIMILAR TO LH0045
4-20m0
INPUT
I
10
>--....-VOUT' 10V FOR 20 mA
lOOk
OV FOR 4 mA
",---+--15V
249k
24.lk
" '__-'\~'VM"""__",,,< ~~~N
192
TLlK/l0032-9
Negative 10V Reference
Current Boost for
Low Input Voltages
O--....- - -....-O+12V
56011
t--....-OVOUT
....---oVOUT
1.2kl1
TLlK/l0032-11
-15V
TL/K/l0032-10
,.
7-15
....
Mr-----------------------------------------------------------~
M
:E
...I
~National
........ ~ Semiconductor
~
:E
...I
LM113/LM313 Reference Diode
General Description
The LM113/LM313 are temperature compensated, low voltage reference diodes. They feature extremely-tight regulation over a wide range of operating currents in addition to an
unusually-low breakdown voltage and good temperature
stability.
• Dynamic impedance of 0.30 from 500 /LA to 20 mA
• Temperature stability typically 1 % over-55°C to 125"C
range (LM113), O°C to 70°C (LM313)
• Tight tolerance: ±5%, ±2% or ±1%
The characteristics of this reference recommend it for use in
bias-regulation circuitry, in low-voltage power supplies or in
battery powered equipment. The fact that the breakdown
voltage is equal to a physical property of silicon-the energy-band gap voltage-makes it useful for many temperature-compensation and temperature-measurement functions.
The diodes are synthesized using transistors and resistors
in a monolithic integrated circuit. As such, they have the
same low noise and long term stability as modern IC op
amps. Further, output voltage of the reference depends only
on highly-predictable properties of components in the IC; so
they can be manufactured and supplied to tight tolerances.
Features
• Low breakdown voltage: 1.220V
Schematic and Connection Diagrams
Metal Can Package
Note: Pin 2 CGftntcbd tel CISI.
TOP VIEW
Order Number LM113H or
LM113·1H or LM113-2H or LM313H
See NS Package Number H02A
TUH/5713-1
Typical Applications
Low Voltage Regulator
VIN >3V
Level Detector for Photodiode
....---1:
2105
TTL
OUTPUT
"
LM313
'"
...,.••.. ••..
. ,,'
__"",___-, ."
....vv.O+~:...--_.....Vov, "ZV
UK
L-_~"""
tSolidtantalum.
TL/H/5713-2
7-16
,-----------------------------------------------------------------------------, r
3:
.....
Absolute Maximum Ratings
.....
Co)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
(Note 3)
Power Dissipation (Note 1)
Reverse Current
Storage Temperature Range
Lead Temperature
(Soldering. 10 seconds)
Operating Temperature Range
LM113
LM313
100mW
50mA
50mA
Forward Current
-65"Cto + 150"C
300"C
......
r
3:
Co)
.....
Co)
-55"Cto+125"C
O"Cto +70"C
Electrical Characteristics (Note 2)
Parameter
Conditions
Reverse Breakdown Voltage
LMl13/LM313
LMl13·1
LM113·2
IR
Reverse Breakdown Voltage
Change
0.5mA";: IR";: 20mA
Reverse Dynamic Impedance
IR
IR
=
1 mA
Min
Typ
Max
Units
1.160
1.210
1.195
1.220
1.22
1.22
1.280
1.232
1.245
V
V
V
6.0
15
mV
0.2
0.25
1.0
0.8
n
n
0.67
1.0
V
= 1 mA
= 10mA
= 1.0mA
Forward Voltage Drop
IF
RMS Noise Voltage
10Hz";: f,,;: 10kHz
IR = 1 mA
Reverse Breakdown Voltage
Change with Current
0.5mA";: IR";: 10mA
TMIN ,,;: TA";: TMAX
Breakdown Voltage Temperature
Coefficient
1.0mA";: IR";: 10mA
TMIN ,,;: TA";: TMAX
5
",V
mV
15
0.01
%/"C
Note 1: For operating at elevated temperatures, the device must be derated based on a 1500C maximum junction and a thermal resistance of SOOC/W junction to
case or 44f1'C/W junclion to ambient.
Note 2: These speeHieations apply for TA ~ 2S'C, unless stated otherwise. At high currents, breakdown voltage should be measured with lead lengths less than %
inch. Kelvin contact sockets are also recommended. The diode should not be operated with shunt capacitances between 200 pF and 0.1 IlF, unless isolated by at
least a 100.0 resistor, as it may oscillate at some currents.
Note 3: Referto the following RETS drawings for military specifications: RETSI13·1X for LMI13·1, RETSI13·2X for LM113·2 or RETS113X for LM113.
Typical Performance Characteristics
Temperature Drift
Reverse Dynamic Impedance
Reverse Characteristics
10
;;
§ 1.230 I-I-I-t-t-t-t-+-+-l
~'"
~ 1.220
:::ffi
>
;0
6
..ri'"
I-t-::!;;o.i-+-+-+-+-+--:I
,,"
~
..'"'"
..!;
111111
25'C
jj
4
!:;
>
1-1-1-1-+-+-+-+-+-1
2
S
1.200 .':-:':-L-L-L-.L..-.L..-.1-..L......J
-55 ·35 ·15 5 25 45 65 85 105 12~
TEMPERATURE ('C)
B
~
~I-I-I-t-t-t-+-+-l
~ 1.210
..s
0
·2
0.3
REVERSE CURRENT (mA)
1
10
30
REVERSE CURRENT (mA)
TLlH/5713-3
7·17
,.
Typical Performance Characteristics (Continued)
Reverse Characteristics
Reverse Dynamic Impedance
lit'
Noise Voltage
90
100
I n =5mA
T.=2S'C
80
~
~
~
-
Xi I
2S'C
I
lit'
0.2
OA
0.&
oS 60
I
L..L.LWWL....L..I.J.....L......I.J.UI......J..LJWII.I
100
1.4
Ik
lDk
Forward Characteristics
I
1.5
;;
T. =-SS'C
~~
! O.S
~
0.5
~
k:;:::~
~
T.=2S'C
~
o
1M
100
10Dlc
3D
Maximum Shunt Capacitance
OUj'UT_
!-"'"'
I
INT
1
50
10
10k
IN'UI
I
I
liiill{C
"
FREQUENCY (HzI
Response Time
2.0
."
lOOk
FREQUENCY (Hz)
2.0
I11tmtl-mlHf+I:t.
4Dt-+ItltHHttIfIHI-HiIHll-t-ffiiflll
REVERSE VOLTAGE (VI
ii 1.5
~>1.0
.. 50
~
t.2
1.0
~
1 H-HIlIIlf-'H+lillllll'++
0.1
0.8
70
;;
~
J.
/ ~'CI
10 H-HIlIIlf-'H+lllli--++
:l
I
L
o
12
FORWARD CURRENT (mAl
TIME
1&
20
lOS
"'.1
10'
10'
CAPACITANCE (pFI
TL/H/5713-4
Typical Applications (Continued)
Amplifier Biasing for Constant Gain with Temperature
,,,.
1301e
"
+15Y
Constant Current Source
"
"K
OUTPUT
...---"v
~
Thermometer
.....
.
IK
• Adjusl for OV at O'C
tAdjust for 100 mVI'C
"'
-1iV
TL/H/5713-5
7-18
.--------------------------------------------------------------------------------, r5i:
....
~National
N
~
r5i:
(0)
~ Semiconductor
N
(Q
LM 129/LM329 Precision Reference
General Description
The LM129 and LM329 family are precision multi-current
temperature-compensated 6.9V zener references with dynamic impedances a factor of 10 to 100 less than discrete
diodes. Constructed in a single silicon chip, the LM129 uses
active circuitry to buffer the internal zener allowing the device to operate over a 0.5 rnA to 15 rnA range with virtually
no change in performance. The LM129 and LM329 are
available with selected temperature coefficients of 0.001,
0.002, 0.005 and 0.D1 %I"C. These new references also
have excellent long term stability and low noise.
A new subsurface breakdown zener used in the LM129
gives lower noise and better long-term stability than conventional IC zeners. Further the zener and temperature compensating transistor are made by a planar process so they
are immune to problems that plague ordinary zeners. For
example, there is virtually no voltage shift in zener voltage
due to temperature cycling and the device is insensitive to
stress on the leads.
The LM129 can be used in place of conventional zeners
with improved performance. The low dynamic impedance
simplifies biasing and the wide operating current allows the
replacement of many zener types.
The LM129 is packaged in a 2-lead TO-46 package and is
rated for operation over a - 55°C to + 125°C temperature
range. The LM329 for operation over O°C to 70°C is available in both a hermetic TO-46 package and a TO-92 epoxy
package.
Features
•
•
•
•
•
•
0.6 rnA to 15 rnA operating current
0.6.(1 dynamic impedance at any current
Available with temperature coefficients of 0.001 %I"C
7!'-V wideband noise
5% initial tolerance
0.002% long term stability
• Low cost
• Subsurface zener
Connection Diagrams
Metal Can Package
Plastic Package
TLlH/5714-4
Bottom View
Order Number LM329BZ,
LM329CZ or LM329DZ
See NS Package Z03A
TL/H/5714-6
Bottom View
Pin 2 is electrically connected to case
Order Number LM129AH, LM129BH, LM129CH,
LM329AH, LM329BH, LM329CH or LM329DH
See NS Package H02A
Typical Applications
Simple Reference
•
9V TO 40V
RS
TLlH/5714-1
7-19
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
(Note 2)
Reverse Breakdown Current
- 55·C to + 150·C
Storage Temperature Range
Soldering Information
TO·92 package: 10 sec.
T0-46 package: 10 sec.
260·C
SOO·C
SOmA
Forward Current
2mA
Operating Temperature Range
LM129
LMS29
-55·C to + 125·C
O·Cto +70"C
Electrical Characteristics (Note 1)
Parameter
Reverse Breakdown Voltage
LM129A,B,C
Conditions
TA = 25·C,
0.6 mA :$; IR :$; 15 mA
Reverse Breakdown Change
with Current (Note S)
TA = 25·C,
0.6 mA :$; IR :$; 15 mA
Reverse Dynamic Impedance
(NoteS)
TA
RMSNoise
LMS29A, B, C, D
Units
Min
Typ
Max
Min
Typ
Max
6.7
6.9
7.2
. 6.6
6.9
7.25
V
9
14
9
20
mV
0.6
1
0.8
2
n
TA = 25·C,
10Hz:$; F:$; 10kHz
7
20
7
100
Long Term Stability
(1000 hours)
TA = 45·C ± 0.1·C,
iR = 1 mA ± O.S%
20
Temperature Coefficient
LM129A, LMS29A
LM129B, LMS29B
LM129C, LMS29C
LMS29D
IR
Change In Reverse Breakdown
Temperature Coefficient
1 mA :$; IR :$; 15 mA
1
1
ppml"C
Reverse Breakdown Change
with Current
1 mA:$; IR :$; 15 mA
12
12
mV
Reverse Dynamic Impedance
1 mA :$; IR :$; 15 mA
0.8
1
n
=
=
25·C, iR
=
1 mA
...
./LV
ppm
20
1 mA
6
15
SO
10
20
50
6
15
SO
50
10
20
50
100
ppml"C
ppml"C
ppml"C
ppml"C
Note 1: These specifications apply for -SS'C ,; TA ,; + 12S'C for the LM129 and O'C ,; TA ,; +70'C for the LM329 unless olherwise specified. The maximum
Junction temperature for an LM129 is ISO'C and LM329 is 100'C. For operating at elevated temperalure, devices in TO·46 package must be derated based on a
Ihermal resistance of 440'C/W junction to ambient or 80'C/W junction to case. For Ihe TO-92 package, the derating is based on 1BO'C/W junction to ambient with
0.4" leads from a PC board and 160'C/W junction to ambient with 0.12S" lead length to a PC board.
Note 2: Refer
to RETS129H for LM129 family mil~ary specifications.
Note 3: These changes are leslOO on a pulsed basis wilh a low duty-cycle. For changes versus temperature. compute in terms of tempco.
7-20
.-----------------------------------------------------------------------------,r
....3:
Typical Applications (Continued)
N
co
......
Adjustable Bipolar Output Reference
Low Cost 0-25V Regulator
3:
(0)
SDk
ISV
!'-4P--- VOUT
r
N
co
+ISV
1.Sk
OUTPUT
>~""--6.9:5 VOUT :5 6.9
SDk>ol......--~
LM129
6.9V
-ISV
30 pF
TUH/5714-8
-IDV
TL/H/5714-7
OV to 20V Power Reference
25VT040V'---.~--
____________________
~---------------~
LM19Sk
2k
LM129
6.9V
,~--t--~-JV~~---t_-OVTD20V
lA
lk
-5V
TUH/5714-9
External Reference for Temperature Transducer
15V
lk
} OUTPUT
10mV/'K
•
LM1Z9
6.9V
TUH/5714-2
7·21
Typical Applications
(Continued)
Positive Current Source
lDVT04DV'-...- -....- - - - - -...- -_ _- - .
LM1Z9
6.9V
TL/HI5714-11
Buffered Reference with Single Supply
+15V-....- - - - - - - - ,
9k
>~1--1DV
LM1Z9
6.9V
TUH/5714-3
Schematic Diagram
OJ
6.JV
JD pF
10k
2k
.....- - -...- .....----.....04.......- - - - - -....--t 2
TL/H/5714-10
7-22
r-
...s::
Typical Performance Characteristics
Reverse Characteristics
III)
Forward Characteristics
Response Time
1.2 , - - - - - - . - - . . , . . - - - , - - - ,
OUTPUT
3:
10-2
1.SK
INPUT t::I. I ~h~T -
~
>Z
'"
z
'" 103
r-;:r.-: t:\::~
tl,
10- 5
6.45 6.55
6.65
~.-.-
'"
~
>
!A'=12S·C
6.15
/ I
~
Tj"2S"C
3
~
JTI"\S"C-
-
20
10
0.8
~~
0.6 1---+-----:::J.-~-1I-..,.."-l
~
0.4
0.2
I
6.85
6.95
7.05
100
REVERSE VOLTAGE (V)
200
JOo
0.01
Tj"'-5S·C
~
;l
I--
u
!
10
Zener Noise Voltage
Reverse Voltage Change
/.
10
:;;:
0.1
FORWARD CURRENT (mAl
150
~
z
loo--q--+--1I---1
400
100
u
Co)
III)
co
1---+----''-t;;_''''-1I-7'''--I
TIME (usJ
Dynamic Impedance
s::
1.01--+---t--r--:;>'i
w
~
INPUT- i - -
co
......
r-
Tj"m"C / .
1.0
,.-,
._-
I
0.1
10
I
100
Ik
FREQUENCY (Hz)
10k
~
100
~"2S'C
-
f"
o
lOOk
~
~
Tj'" SS"C
I-- Tj"2S"C
~
~25"CTj=125:;#
./
o
10
50
10
100
REVERSE CURRENT (mAl
1k
10k
lOOk
FREOUENCY (Hz)
TLlH/5714-12
Low Frequency Noise Voltage
0.01 Hz'$. I~ 1 Hz
10
TIME (MINUTES)
Tl/H/5714-5
•
7-23
~National
~ Semiconductor
LM 134/LM234/LM334
3-Terminal Adjustable Current Sources
General Description
The LM134/LM234/LM334 are 3-terminal adjustable current sources featuring 10,000:1 range in operating current,
excellent current regulation and a wide dynamic voltage
range of 1V to 40V. Current is established with one external
resistor and no other parts are required. Initial current accuracy is ±3%. The LM134/LM234/LM334 are true floating
current sources with no separate power supply connections.
In addition, reverse applied voltages of up to 20V will draw
only a few dozen microamperes of current, allowing the devices to act as both a rectifier and current source in AC
applications.
LM234-3 and LM134-6/LM234-6 are specified as true temperature sensors with guaranteed initial accuracy of ± 3°C
and ±6°C, respectively. These devices are ideal in remote
sense applications because series resistance in long wire
runs does not affect accuracy. In addition, only 2 wires are
required.
The LM 134 is guaranteed over a temperature range of
- 55°C to + 125°C, the LM234 from - 25°C to + 100"C and
the LM334 from O°C to + 70"C. These devices are available
in TO-46 hermetic, TO-92 and 80-8 plastic packages.
The sense voltage used to establish operating current in the
LM134 is 64 mV at 25°C and is directly proportional to absolute temperature ("K). The simplest one external resistor
connection, then, generates a current with :::: + 0.33%I"C
temperature dependence. Zero drift operation can be obtained by adding one extra resistor and a diode.
Applications for the new current sources include bias networks, surge protection, low power reference, ramp generation, LED driver, and temperature sensing. The LM134-31
•
•
•
•
•
•
Features
Operates from 1V to 40V
0.02%1V current regulation
Programmable from 1 /LA to 10 mA
True 2-terminal operation
Available as fully specified temperature sensor
±3% initial accuracy
Connection Diagrams
SO-8
Surface Mount Package
TO-46
Metal Can Package
TO-92
Plastic Package
y+ R
y+
-0--
Y-
8
TLlH/5697-10
Bottom View
TLlH/5697 -12
BoHomView
Pin 3 is electrically ccnnected to case.
TL/H/5697-24
Order Number LM334M
See NS Package Number MOBA
Order Number LM134H, LM134H-3,
LM134H-6, LM234H, LM234H-3,
LM234H-6, or LM334H
See NS Package Number H03H
Order Number LM334Z, LM234Z·3
orLM234Z-6
See NS Package Number Z03A
Typical Application
Basic 2-Terminal Current Source
+YIN
I.,.
RSfT
Y-
TLlH/5697 -1
7-24
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
V+ to V- Forward Voltage
LM134/LM234
LM334/LM134-3/LM134-6/LM234-3/LM234-6
40V
30V
V+ to V- Reverse Voltage
20V
R Pin to V- Voltage
Operating Temperature Range (Note 4)
- 55'C to + 125'C
LM134/LM134-3/LM134-6
LM234/LM234-3/LM234-6
-25'C to + 100'C
O'Cto +70'C
LM334
Soldering Information
TO-92 Package (10 sec.)
T0-46 Package (10 sec.)
SO Package
Vapor Phase (60 sec.)
Infrared (15 sec.)
5V
Set Current
10mA
Power Dissipation
400mW
260'C
300'C
215'C
220'C
See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" (Appendix D) for other methods of
soldering surface mount devices.
Electrical Characteristics (Note 1)
Parameter
Min
Typ
Set Current Error, V+ =2.5V,
(Note 2)
10 fLA,;;ISET';;1 rnA
1 mA
1/
14
10
/
lk
ill 100
&Z
&4
~
~
0-
86
58
1-5,.
1
INPUT
TIME (Nota scae changes at each current level)
88
8Z
;;
.!
1
-zoo,.
1
1
1-50,.
1
/
SO
4&
-SO -Z5
I"
0 Z5 50 15 100 lZ5
TEMPERATURE rC)
'"~
1'-0
10
1
10
ISET" SmA
l-i SET "lmA
-ISET"'00pA
='SET"IOpA
lk
10k
100
FREQUENCY (Hz)
ll1Dk
TL/H/5697 -2
7-26
r-----------------------------------------------------------------------------,
Typical Performance Characteristics (Continued)
....
Co)
Ratio of ISET to V- Current
Turn-On Voltage
r
lS:
,Joo
......
r
lS:
20
lmA
100 IiA
N
Co)
,Joo
......
18
1---1-r-l--+--RS~T = 68~n-
CI
~
16
a:
I---J~-+RSET ~ 6.8k - -
r
lS:
Co)
l/'
V
1,,\
,
Co)
,Joo
1\
14
10llA
If
12
I
IliA
0.4
0.6
0.8
1.0
1.2
10 IiA
1.4
100 IiA
V+TO V-VOLTAGE
lmA
10mA
ISET
TL/H/5697-3
Application Hints
The LM 134 has been designed for ease of application, but a
general discussion of design features is presented here to
familiarize the designer with device characteristics which
may not be immediately obvious. These include the effects
of slewing, power dissipation, capacitance, noise, and contact resistance.
will be increased by about 12 dB. In many cases, this is
acceptable and a single stage amplifier can be built with a
voltage gain exceeding 2000.
LEAD RESISTANCE
The sense voltage which determines operating current of
the LM134 is less than 100 mY. At this level, thermocouple
or lead resistance effects should be minimized by locating
the current setting resistor physically close to the device.
Sockets should be avoided if possible. It takes only 0.70
contact resistance to reduce output current by 1 % at the
1 mA level.
SLEW RATE
At slew rates above a given threshold (see curve), the
LM134 may exhibit non-linear current shifts. The slewing
rate at which this occurs is directly proportional to ISET. At
ISET=10 /LA, maximum dV/dt is O.Q1V1/Ls; at ISET= 1 mA,
the limit is lV//Ls. Slew rates above the limit do not harm
the LM134, or cause large currents to flow.
SENSING TEMPERATURE
The LM134 makes an ideal remote temperature sensor because its current mode operation does not lose accuracy
over long wire runs. Output current is directly proportional to
absolute temperature in degrees Kelvin, according to the
following formula:
THERMAL EFFECTS
Internal heating can have a significant effect on current regulation for ISET greater than 100 /LA. For example, each 1V
increase across the LM 134 at ISET = 1 mA will increase
junction temperature by :::: O.4°C in still air. Output current
(ISET) has a temperature coefficient of ::::0.33%rC, so the
change in current due to temperature rise will be (0.4)
(0.33) = 0.132%. This is a 10:1 degradation in regulation
compared to true electrical effects. Thermal effects, therefore, must be taken into account when DC regulation is critical and ISET exceeds 100 /LA. Heat sinking of the TO-46
package or the TO-92 leads can reduce this effect by more
than 3:1.
I
(227 /LVIOK)(T)
SET
RSET
Calibration of the LM134 is greatly simplified because of the
fact that most of the initial inaccuracy is due to a gain term
(slope error) and not an offset. This means that a calibration
consisting of a gain adjustment only will trim both slope and
zero at the same time. In addition, gain adjustment is a one
point trim because the output of the LM134 extrapolates to
zero at OOK, independent of RSET or any initial inaccuracy.
SHUNT CAPACITANCE
In certain applications, the 15 pF shunt capacitance of the
LM134 may have to be reduced, either because of loading
problems or because it limits the AC output impedance of
the current source. This can be easily accomplished by buffering the LM134 with an FET as shown in the applications.
This can reduce capacitance to less than 3 pF and improve
regulation by at least an order of magnitude. DC characteristics (with the exception of minimum input voltage), are not
affected.
INITIAL OUTPUT
ISET
t
DESIRED
OUTPUT
lb'
I
I
I
NOISE
O'K
Current noise generated by the LM134 is approximately 4
times the shot noise of a transistor. If the LM 134 is used as
an active load for a transistor amplifier, input referred noise
"
T1
I
I
I
I
1
I
12
T3
TL/H/5697 -4
This property of the LM134 is illustrated in the accompanying graph. Line abc is the sensor current before trimming.
7-27
•
Application Hints
(Continued)
Line a'b'c' is the desired output. A gain trim done at T2 will
move the output from b to b' and will simultaneously correct
the slope so that the output at T1 and T3 will be correct.
This gain trim can be done on RSET or on the load resistor
used to terminate the LM134. Slope error after trim will normally be less than ± 1%. To maintain this accuracy, however, a low temperature coefficient resistor must be used for
RSET·
A 33 ppml'C drift of RSET will give a 1% slope error because the resistor will normally see about the same temperature variations as the LM134. Separating RSET from the
LM 134 requires 3 wires and has lead resistance problems,
so is not normally recommended. Metal film resistors with
less than 20 ppml'C drift are readily available. Wire wound
resistors may also be used where best stability is required.
Typical Applications (Continued)
Zero Temperature Coefficient Current Source
Terminating Remote Sensor for Voltage Output
+V'N
RSET
RI*
~IO
RSET
(lSET)(RL)
10mVfK FOR
RSET= 230n
RL = 10 kn
TL/H/5697-13
*Select ratio of R1 to RSETto obtain zero drift. 1+ ;::::: 21SET
TLlH/5697-14
Ground Referred Fahrenheit Thermometer
Low Output Impedance Thermometer
R4
V'N<:4.8V
56k
r--'\f'IIlr--1......- - - - - - - - +V'N <: 3V
R3*
60..,0\t-_ VOUT = 10 mVfK
)c0(4_r.;_. .-lI.J
Rl
230
1%
Zour:> loon
R2
Cl
10k
1%
LM336Z
2.5V*
TL/H/5697-6
*Output impedance of the LM134 at the "R" pin is
-R n
approximately ~ where Ro is the equivalent
TLlH/5697-15
'Select R3 ~ VREF/5B31"A. VREF may be any stable positive voltage ~2V
external resistance connected to the V- pin. This
negative resistance can be reduced by a factor of 5
or more by inserting an equivalent resistor in series
with the output.
Trim R3 to calibrate
7-28
Typical Applications (Continued)
Low Output Impedance Thermometer
Higher Output Current
+VIN
+VIN - -...- - - - ,
Cl
0.002Z
>0*....;;...0004""'""- VOUT
=10 mVfK
ZOUTS;zn
TL/H/5697-5
'Select R1 and C1 for optimum stability
TLlH/5697-16
Mlcropower Bias
+VIN
Low Input Voltage Reference Driver
+VIN <:: vREF + 200 mV - -...- - - - - - - ,
VOUT = Vz + 84 mV" 2S"C
IOUTS;3mA
Dl
LM129
LM136
LMl13
ETt.
R2
120
-VIN
TL/H/5697-17
TL/H/5697 -18
Ramp Generator
+VIN
•
"'---+-VOUT
RESET...fL
TL/H/5697 -19
7-29
-=r ,---------------------------------------------------------------------------------,
C')
C')
::::!l
....I
......
-=r
C')
N
Typical Applications (Continued)
1.2V Reference Operates on 10 p.A and 2V
1.2V Regulator with 1.BV Minimum Input
+VIN~ZV
vIN~
I.BV
::::!l
....I
......
-=r
....
R3
3.6k
C')
::::!l
)CI<+-+.;.;...-1-....."J\jI'y--- VOUT = 1.2V
....I
lOUT:> I~A
RZ*
l-'V'-ilY-1-- Vour -1.2V
Uk
1%
IOUT:>ZDD~A
IN451
TL/H/5697-20
·Select ratio of R1 to R2 to obtain zero temperature drift
TL/H/5697 -7
·Select ratio of R1 to R2 for zero temperature drift
Buffer for Photoconductive Cell
Alternate Trimming Technique
Zener Biasing
R
R
1.5V
RSET
"'---"-VOUT
TUH/5697-8
"'For
± 10% adjustment, select RSET
10% high. and make RI '" 3 RSET
FET Cascoding for Low Capacitance and/or Ultra High Output Impedance
+vIN
R
RSET
V-
RSEr
-VIN
TL/H/5697-21
TLlH/5697-22
'Select 01 or 02 to ensure a1leaslIY across the LM134. Vp (1 - ISET/loss) :;, 1.2V.
7,30
Typical Applications
(Continued)
Generating Negative Output Impedance
In-Line Current Limiter
+VIN
RSET
R
y+
().
~ Rl*
.~
R
~l
RSET
V
TUH/5697 -23
'ZOUT:::: -16· R1 (R11V1N must not exceed ISETl
TL/H/5697 -9
·Use minimum value required to ensure stability of protected device. This
minimizes inrush current to a direct short.
Schematic Diagram
~-----e-------------v-
7-31
TL/H/5697 -11
U) r-----------------------------------------------------------------------~----------_,
~ ~National
:=i..... ~ Semiconductor
CO)
CO)
U)
N
cD
~
:=i
;A;
.
N
CD
....
:!!i
CO)
....I
LM 136-2.S/LM236-2.S/LM336-2.SV Reference Diode
General Description
The LM136-2.5/LM236-2.5 and LM336-2.5 integrated circuits are precision 2.5V shunt regulator diodes. These
monolithic IC voltage references operate as a low-temperature-coefficient 2.5V zener with 0.20 dynamic impedance. A
third terminal on the LM136-2.5 allows the reference voltage and temperature coefficient to be trimmed easily.
Both are packaged in a TO-46 package. The LM336-2.5 is
rated for operation over a O°C to + 700C temperature range
and is available in a TO-92 plastic package.
.Features
• Low temperature coefficient
• Wide operating current of 400 fJ.A to 10 mA
• 0.20 dynamic impedance
• ± 1% initial tolerance available
• Guaranteed temperature stability
• Easily trimmed for minimum temperature drift
• Fast tum-on
• Three lead transistor package
The LM136-2.5 series is useful as a precision 2.5V low voltage reference for digital voltmeters, power supplies or op
amp circuitry. The 2.5V make it convenient to obtain a stable reference from 5V logic supplies. Further, since the
LM136-2.5 operates as a shunt regulator, it can be used as
either a positive or negative voltage reference.
The LM 136-2.5 is rated for operation over - 55°C to
+ 125°C while the LM236-2.5 is rated over a - 25°C to
+ 85°C temperature range.
Connection Diagrams
TO-92
Plastic Package
SO Package
TO-46
.. Metal ciiii Package
+
Ne
ADJ
8
TUH/5715-8
Bottom View
TUH/5715-20
Order Number LM336Z-2.5
or LM336BZ-2.5
See NS Package Number Z03A
Bottom View
Ne
Order Number LM136H-2.5.
LM236H-2.5. LM336H-2.5.
LM136AH-2.5 or LM236AH-2.5
See NS Package Number H03H
Ne
3
Ne
4
TL/H/5715-12
Top View
Order Number LM336M-2.5
or LM336BM-2.5
See NS Package Number M08A
Typical Applications
2.5V Reference with Minimum
Temperature Coefficient
2.5V Reference
5V
Wide Input Range Reference
5V
vlN l.S - 4IIV
l.Sk
l.5k
Z.5V
IN457*
.....-+-- VOUT' Z.SV
LM1lS·2.5
LMl3S·2.5
A--.-c
TUH/5715-9
IN457*
t Adlust to 2.490V
'Any silicon signal diode
TLlH/5715-10
7-32
TL/H/5715-11
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Reverse Current
Soldering Information
TO-92 Package (10 sec.)
TO-46 Package (10 sec.)
SO Package
Vapor Phase (60 sec.)
Infrared (15 sec.)
15mA
10mA
Forward Current
Storage Temperature
- 60'C to + 150'C
Operating Temperature Range
LM136
LM236
LM336
-55'Cto +150'C
- 25'C to + 85'C
O'Cto +70'C
260'C
300'C
215'C
220'C
See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" (Appendix D) for other methods of
soldering surface mount devices.
Electrical Characteristics (Note 1)
Parameter
LM 136A-2.5/LM236A-2.5
LM136-2.5/LM236-2.5
Conditions
Reverse Breakdown Voltage
TA=25'C, IR=1 rnA
LM136/LM236/LM336
LMI36A1LM236A, LM336B
LM336B-2.5
LM336-2.5
Units
Min
Typ
Max
Min
Typ
Max
2.440
2.465
2.490
2.490
2.540
2.515
2.390
2.440
2.490
2.490
2.590
2.540
V
V
Reverse Breakdown Change
With Current
TA=25'C,
400 ,...A:5:IR:5:10 rnA
2.6
6
2.6
10
mV
Reverse Dynamic Impedance
TA=25'C, IR=1 rnA
0.2
0.6
0.2
1
0.
Temperature Stability
(Note 2)
VR Adjusted to 2.490V
IR = 1 mA, (Figure 2)
0'C:5:TA:5:70'C (LM336)
-25'C:5:TA:5: + 85'C (LM236)
-55'C:5:TA:5: + 125'C (LMI36)
1.8
6
3.5
12
9
18
mV
mV
mV
3
10
3
12
mV
0.4
1
0.4
1.4
0.
Reverse Breakdown Change
With Current
400 ,...A:5:IR:5:10 rnA
Reverse Dynamic Impedance
IR=1 mA
Long Term Stability
20
ppm
TA=25'C ±O.I'C, IR=1 mA
20
Note I: Unless otherwise specified, the LMI36·2.S is specified from - SS'C ,;; TA ,;; + 12S'C. the LM236·2.S from - 2S'C ,;; TA';; + BS'C and the LM336-2.S from
O'C ,;; TA ,;; +70'C.
Note 2: Temperature stability for the LM336 and LM236 family is guaranteed by design. Design limits are guaranteed (but not 100% production tested) over the
indicated temperature and supply voltage ranges. These limits are not used to calculate outgoing quality levels. Stability is defined as the maximum change in Vret
from 2S'C to TA (min) or TA (max).
Note 3: For elevated temperature operation. Tj max is:
LM136
LM236
LM336
lS0'C
125'C
100'C
Thermal Resistance
TO·92
TO-46
50-8
8ja (Junction to Ambient)
lBO'C/W (0.4" leads)
170'C/W (0.12S" lead)
440'C/W
16S'C/W
n/a
BO'C/W
n/a
81a (Junction to Case)
Typical Performance Characteristics
Reverse Voltage Change
Zener Noise Voltage
3.S
.
lOll
IR=1 mA
.! 3.0
Tj -IIS'C
~
;0
c
.~
3
~
">
I
rr:
Dynamic Impedance
ISO
:>
2.5
~
~ :;.-r
2
~
1.5
1.0
0.5
/
0
0
V-
~
200
~j=-S5'C
;l!
I
Tj-15'C_
I
"
u
\
150
;0
100
"c
4
6
8
REVERSE CURRENT (mAl
10
10
"
lOll
10
I
I
Tj'11S'C~
i
~
">"
so
2
~ IR ·\mA
g
~
\
~
!
Tj'IS'C'-
\
Ik
10k
FREQUENCY (H.)
I
I
Tj -
-ss'e
Tj-16'C-
I
0.1
lOOk
W
10
100
Ik
10k
lOOk
FREQUENCY (H.I
TUH/5715-2
7-33
,.
Typical Performance Characteristics
Response Time
.1
1..
z~
-
0_
OUTPUT
Forward Characteristics
Ti=25·C
I
a..
, ..
aurruT
-j
0
0
I
T
I
I
I IINPUT I I
I I I I I
z C
-
0.8
!:;
~"UT
-
1.2r--'T""-"--""---'
./
I.D
,. //
...
....
. / "/
.. ~ "
Ilf
I-
1---
5
Reverse Characteristics
I I I I I
3
(Continued)
>
D.&
;I
0.4
~
_
D.2
Tj--55'e
~IZ5'C- I - I
&
TIMEfps)
./
I
D
•
DJIOI
2.&
O.D!
'.1
1
10
FORWARD CURRENT (mAl
TUH/5715-3
Application Hints
The LM 136 series voltage references are much easier to
use than ordinary zener diodes. Their low impedance and
wide operating current range simplify biasing in almost any
circuit. Further, either the breakdown voltage or the temperature coefficient can be adjusted to optimize circuit performance.
If minimum temperature coefficient is desired, two diodes
can be added in series with the adjustment potentiometer
as shown in Figure 2. When the device is adjusted to 2.490V
the temperature coefficient is minimized. Almost any silicon
signal diode can be used for this purpose such as a 1N914,
1N4148 or a 1N457. For proper temperature compensation
the diodes should be in the same thermal environment as
the LM136. It is usually sufficient to mount the diodes near
the LM136 on the printed circuit board. The absolute resistance of R1 is not critical and any value from 2k to 20k will
work.
Figure 1 shows an LM136 with a 10k potentiometer for adjusting the reverse breakdown voltage. With the addition of
R1 the breakdown voltage can be adjusted without affecting
the temperature coefficient of the device. The adjustment
range is usually sufficient to adjust for both the initial device
tolerance and inaccuracies in buffer circuitry.
v+
RS
RS
~~IN914
~ ~IN914
TL/H/5715-4
FIGURE 1. LM136 With Pot for Adjustment
of Breakdown Voltage
(Trim Range = ± 120 mV typical)
FIGURE 2. Temperature CoeffiCient Adjustment
(Trim Range = ± 70 mV typical)
7-34
Typical Applications
(Continued)
Low Cost 2 Amp Switching Regulator t
6VTO~~--~--~------~~
';---~~~--------------e-~('~Ll~'-~----~-VOUT 5V
6UO",H
+
+
VARO
VS<330
4lJJF
TL/H/5715-5
'l1 60 turns #16 wire on Arnold Core A·254168·2
tEfficiency ::: 80%
Precision Power Regulator with Low Temperature Coefficient
~--~~----------~~-VOUT
VIN
Uk
Rl
315
LM33B·2.5 . .~--+.(
IN457
R2
2k
OUTPUT
ADJUST
":'"
TLlH/5715-13
'Adjust for 3.75V across RI
Trimmed 2.5V Reference with Temperature
Coefficient Independent of Breakdown Voltage
5VCrowbar
10V
V+-------1~----~e--------
5k
LM33B·2.5 ',6,....--+.(
100
~~L~BRATE
SENSITIVE GATE
seH
200
'Does not affect temperature coefficient
TL/H/5715-14
7·35
TL/H/5715-15
.
~
c.,j
CD
r-----------------------------------------------------------------------------------------~
Typical Applications
(Continued)
CO)
CO)
Adjustable Shunt Regulator
:::iE
....I
......
~
~
CD
RS
6VT040V--~~~__--------~--------------~___ ~~~U~V
CO)
N
:::iE
.....
....I
~
~
CD
....
CO)
:::iE
....I
TLlH/5715-6
Linear Ohmmeter
y+
35
Uk
1%
Z5k
1%
10k
CALIBRATE
IOkIV
lklV
>--+-VOUT
TLlH/5715-16
7·36
r-----------------------------------------------------------------------------,r
...3:
Typical Applications (Continued)
.
~
Op Amp with Output Clamped
en
Bipolar Output Reference
N
C,n
......
5V
RF
r
3:
5k
.
N
~
en
N
C,n
......
10k
2k
'2V
...J.W\r-...--I
r
3:
1%
M136·2.5
~
~
±1.25V
_-""",""-0 v'
tC,n
10k
1%
TUH/5715-17
5k
-5V
TL/H/5715-18
2.5V Square Wave Calibrator
5V
..._--~~--...- - OUTPUT
....--+OCCALIBRATE
TLlH/5715-19
fI
7-37
U)
~
CD
r---------------------------------------------------------------------------------,
Typical Applications (Continued)
(f)
(f)
5V Buffered Reference
:E
..J
.....
U)
~
Low Noise Buffered Reference
5V
7V $V,N$36V -
....- - - - - - - .
ZDk
'"
CD
(f)
C'II
2.2k
::iii
..J
......
U)
BV
~
Z.BV
CD
....
(f)
::iii
..J
10k
CAL
10k
CAL
LM33&
TL/H/5715-7
Schematic Diagram
r-----------------------------~~~----~--------------------~--._-------+
Rl
50k
R5
24k
R6
24k
R7
6.6k
Cl
30pF
R8
600
ADJ
R9
30k
RIO
6.6k
R2
2k
R3
Uk
TLlH/5715-1
7-38
~National
~ Semiconductor
LM 136-5.0/LM236-5.0/LM336-5.0, 5.0V Reference Diode
General Description
The LMI36-5.0/LM236-5.0/LM336-5.0 integrated circuits
are precision 5.0V shun! regulator diodes. These monolithic
IC voltage references operate as a low temperature coefficient 5.0V zener with 0.6n dynamic impedance. A third terminal on the LMI36-5.0 allows the reference voltage and
temperature coefficient to be trimmed easily.
The LMI36-5.0 series is useful as a precision 5.0V low voltage reference for digital voltmeters, power supplies or op
amp circuitry. The 5.0V makes it convenient to obtain a stable reference from low voltage supplies. Further, since the
LM 136-5.0 operates as a shunt regulator, it can be used as
either a positive or negative voltage reference.
The LMI36-5.0 is rated for operation over -55·C to
+ 125·C while the LM236-5.0 is rated over a - 25·C to
+ 85·C temperature range. Both are packaged in a TO-46
package. The LM336-5.0 is rated for operation over a O·C to
+ 70·C temperature range and is available in a TO-92 plastic package. For applications requiring 2.5V see LMI36-2.5.
Features
II Adjustable 4V to 6V
II Low temperature coefficient
III Wide operating current of 600 /J-A to 10 mA
11\ 0.6n dynamic impedance
m ± 1% initial tolerance available
II Guaranteed temperature stability
II Easily trimmed for minimum temperature drift
iii Fast turn-on
IlJ Three lead transistor package
Connection Diagrams
TO-92
Plastic Package
TO-46
Metal Can Package
SO Package
+
8
TLlHIS716-4
Bottom View
4
TLIHIS716-S
Order Number LM336Z-S.0 or
LM336BZ-S.O
See NS Package Number Z03A
NC
Bottom View
Order Number LM136H-S.O,
LM236H-S.O, LM136AH-S.O or
LM236AH-S.O
See NS Package Number H03H
NC
TLIHIS716-7
Order Number LM336M-S.O or
LM336BM-S.O
See NS Package Number M08A
Typical Applications
S.OV Reference with Minimum
Temperature Coefficient
S.OV Reference
IOV
lDV
Trimmed 4V to 6V Reference
with Temperature Coefficient
Independent of Breakdown Voltage
IOV
2.5k
IOk*
TLlHIS716-1
LM336·5.0 . - -....C CALIBRATE
LM1J6·5.01
lMJJ6·5.D
t Adjust to 5.00V
TLIHIS716-3
•Any silicon signal diode
• Does not affect temperature coefficient
-=-
TLlH/5716-15
7-39
•
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Reverse Current
Forward Current
Soldering Information
TO-92 Package (10 sec.)
260"C
TO-46 Package (10 sec.)
300"C
SO Package
215·C
Vapor Phase (60 sec.)
220·C
Infrared (15 sec.)
See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" (appendix D) for other methods of
soldering surface mount devices.
15mA
10mA
-60"Cto + 150·C
Storage Temperature
Operating Temperature Range
LM136-5.0
LM236-5.0
LM336-5.0
- 55·C to + 150·C
- 25·C to + 85·C
O·Cto +70·C
Electrical Characteristics (Note 1)
Parameter
Reverse Breakdown Voltage
LM136A-5.0/LM236A-5.0
LM136-5.0/LM236-5.0
Conditions
TA=2S·C, IR=1 mA
LM136-5.0/LM236-5.0/LM336-5.0
LM136A-5.0/LM236A-5.0, LM336B-5.0
LM336B-5.0
LM336-5.0
Units
Min
Typ
Max
Min
Typ
Max
4.9
4.95
5.00
5.00
5.1
5.05
4.8
4.90
5.00
5.00
5.2
5.1
V
V
Reverse Breakdown Change
With Current
TA=25·C,
600 f£A,:;;IR,:;;10 mA
6
12
6
20
mV
Reverse Dynamic Impedance
TA=25·C, IR=1 mA
0.6
1.2
0.6
2
.n
Temperature Stability
VR Adjusted 5.00V
IR = 1 mA, (Figure 2)
0·C,:;;TA':;;70·C (LM336'5.0)
- 25·C,:;; TA':;; + 85·C (LM236-5.0)
-S5·C,:;;TA':;; + 125·C (LM136-5.0)
4
12
7
20
18
36
mV
mV
mV
Reverse Breakdown Change
With Current
600 f£A':;;IR:<=;10 mA
6
17
6
24
mV
Adjustment Range
Circuit of Figure 1
±1
Reverse Dynamic Impedance
IR=1mA
0.8
1.6
0.8
2.5
.n
Long Term Stability
TA=25·C±0.1·C,IR=1 mA
20
±1
20
V
ppm
Note 1: Unless otherwise specified. the LM136-S.0 is specified from -S5"CS:TAS: + 12S'C, the LM236·S.0 from' -2S'Cs:TAS: +SS'C and the LM336·5.0 from
O"C5:TA5:+70'C.
Note 2: Temperature stability for the LM336 and LM236 family is guaranteed by design. Design limits are guaranteed (but not 100% percent production tested)
over the indicated temperature and supply voltage ranges. These limits are not used to calculate outgOing quality levels. Stability Is defined as the maximum charge
in VREF from 2S'C \0 TA(min) or TA(max).
Note 3: For elevated temperature operation. Tj max is;
LM136
150"C
LM236
12S'C
LM336
100"C
Thermal ReSistance
TQ-92
TQ-46
So-e
8jo (Junction to Ambient)
ISO"C/W (0.4' Leads)
170"C/W (0.125" Leads)
44O"C/W
165'C/W
9ja (Junction to Case)
N/A
SO'C/W
N/A
7-40
r-
....3:
Typical Performance Characteristics
c.:I
en
Reverse Voltage Change
Zener Noise Voltage
Dynamic Impedance
IR-' mA
='R"'mA
Tj=25°C
350
\
300
..s
".
w
0
250
200
Ti"125°C~
\
REVERSE CURRENT ImAI
~
U1
-Tj=25"C -?/I~'
Tj= -SS"C
~
10k
''''' FREOUENCY IHzl
Ik
10
lOOk
100
Reverse Characteristics
, , , II
Tj ~25~C
OUTPUT
~~!h
r-ir- _INPUT
-
10
5
~
51
-
10-1
r---'--Y--,--r-,
10-2
,
'---1--+--+-+......-1
~ 10-3
w
OUTPUT
if!
>
I I I I
, IINPUT , ,
II II ,
-I-j
~ 10-4
1.5
TIME ""I
Temperature Drift
~5.D411
co
~
i"
.
~
5.000
i-""
i-""
w
-r-.
--..... .....r-...--
.
.."iii
">
t-
4.920
4.880
.~
~
I-""
IR=1mA
'j ,
4.840
-55 -35 -15
4.5
5.5
Forward Characteristics
1.2
~ i'"""
4.9&0
3.5
REVERSE VOLTAGE (VI
5.120
5.080
2.5
~
5 25 45 65 85 105 125
r--,---r--,----,
1.0
u.s
0.6
0.4
0.2
0.01
0.1
10
FORWARD CURRENT (..AI
TEMPERATURE ("CI
TL/H/5716-8
Application Hints
The LM136-5.0 series voltage references are much easier
to use than ordinary zener diodes. Their low impedance and
wide operating current range simplify biasing in almost any
circuit. Further, either the breakdown voltage or the temperature coefficient can be adjusted to optimize circuit performance.
Figure 1 shows an LM136-5.0 with a 10k potentiometer for
adjusting the reverse breakdown voltage. With the addition
of R1 the breakdown voltage can be adjusted without affecting the temperature coefficient of the device. The adjustment range is usually sufficient to adjust for both the
initial device tolerance and inaccuracies in buffer Circuitry.
If minimum temperature coefficient is desired, four diodes
can be added in series with the adjustment potentiometer
as shown in Figure 2. When the device is adjusted to 5.00V
the temperature coefficient is minimized. Almost any silicon
signal diode can be used for this purpose such as a 1N914,
1N4148 or a 1N457. For proper temperature compensation
the diodes should be in the same thermal environment as
the LM136-5.0. It is usually sufficient to mount the diodes
near the LM136-5.0 on the printed circuit board. The absolute resistance of the network is not critical and any value
from 2k to 20k will work. Because of the wide adjustment
range, fixed resistors should be connected in series with the
pot to make pot setting less critical.
7-41
.
Co)
lOOk
TL/H/5716-2
.I
r-
en
10k
lk
FREOUENCY IHzl
Response Time
b
.....
3:
Co)
,
I
0.1
10
3:
N
Co)
10
150
10
b
.....
r-
100
400
~>
•
U1
U1
b
Application Hints (Continued)
LM136·5.0
Rl
A--+C. 10k
-
TL/H/5716-9
FIGURE 1. LM136-5.0 with Pot for Adjustment of
Breakdown Voltage (Trim Range = ± 1.0V Typical)
1 rnA.!.
RS
lN914
5k
Rl
LMI36-5.0 A--+'~ 2k
5k
lN914
_
TL/H/5716-10
FIGURE 2. Temperature Coefficient Adjustment
(Trim Range = ± O.5V Typical)
Typical Applications
(Continued)
Precision Power Regulator with Low Temperature Coefficient
lM317
INPUT
OUT~--~'-------------~--VOUT
Uk
'Adjust for 6.2SV across RI
7-42
TUH/5716-11
,-----------------------------------------------------------------------------, r
...s:w
Typical Applications (Continued)
.
5VCrowbar
0)
CTI
V+-------4~----~~------
b
.......
r
s:
N
W
LM336·5.0
cp
CTI
b
.......
r
SENSITIVE GATE
100
s:
w
seR
w
0)
•
CTI
200
b
TL/H/5716-12
Adjustable Shunt Regulator
RS
VIN > 2V + VOUT
-,..,.'IY-t---------...--------------...- ~~:~~~OV
TLlH/5716-13
Linear Ohmmeter
5k
1%
PI
>;.......-VOUT
TL/H/5716-14
7-43
C) r-----------------------------------------------------------------------------------------~
u;
I
CD
CO)
CO)
Typical Applications
(Continued)
:E
..J
....
Op Amp with Output Clamped
Bipolar Output Reference
C)
u?
CD
SV
CO)
('II
:E
St
..J
....
~
C)
2k
CO)
.....
±2.SV
:E
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5t
-SV
S.OV Square Wave Calibrator
10V Buffered Reference
12V'SVINS3&V-. . .- - - - -.....
10V
2Dk
1%
2k
oJI---....--....
--OUTPUT
10V
.--KCALIBRATE
lDk
CAL
Low Noise Buffered Reference
Wide Input Range Reference
7.SV
LM334
5V
.....-+-- VOUT =S.OV
10k
CAL
TLlH/5716-6
7·44
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24k
08
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6.6k
25k
CI
30pF
R8
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600
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6.6k
TUH/5716-16
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r----------------------------------------------------------------------------,
~National
PRELIMINARY
~ Semiconductor
LM168/LM268/LM368 Precision Voltage Reference
CD
.,...
~
General Description
Features
The LM16B/LM36B are precision, monolithic, temperaturecompensated voltage references. The LM16B makes use of
thin-film technology enhanced by the discrete laser trimming of resistors to achieve excellent Temperature coeffi·
cient (Tempco) of VOUT (as low as 5ppml"C), along with
tight initial tolerance, (as low as 0.02%). The trim scheme is
such that individual resistors are cut open rather than being
trimmed (partially cut), to avoid resistor drift caused by electromigration in the trimmed area. The LM16B also provides
excellent stability vs. changes in input voltage and output
current (both sourcing and sinking). This device is available
in output voltage options of 5.0V and 1O.OV and will operate
in both series or shunt mode. Also see the LM36B-2.5 data
sheet for a 2.5V output. The devices are short circuit proof
when sourcing current. A trim pin is made available for fine
trimming of VOUT or for obtaining intermediate values without greatly affecting the Tempco of the device.
•
•
•
•
•
•
•
•
•
300 p,A operating current
Low output impedance
Excellent line regulation (.0001 %N typical)
Single-supply operation
Externally trimmable
Low temperature coefficient
Operates in series or shunt mode
10.0V or 5.0V
Excellent initial accuracy (0.02% typical)
Connection Diagram
Dual-ln-LlnePackage (N)
or S.O. Package (M)
Metal Can Package
Ne
y+NCOs NC
NC
2
y.
7
3
6
OUTPUT
4
5
ADJ
TLlH/5522-19
Top View
Order Number LM368N-5.0
or LM268BYN-5.0
See NS Package Number N08E
yTL/H/5522-1
Top View
·case connected to V-
Order Number LM168BYH-10, LM168BYH-5.0,
LM268BYH-10, LM268BYH-5.0,
LM368YH-10, LM368YH-5.0, LM368H-10, LM368H-5.0
See NS Package Number H08C
Typical Applications
Series Regulator
Shunt Regulator
1 mA-l0 mA
!
2
5.000V
TLlH/5522-2
TLlH/5522-3
7-46
Absolute Maximum Ratings
(Note 8)
Input Voltage (Series Mode)
35V
Reverse Current (Shunt Mode)
Power Dissipation
Storage Temperature Range
Soldering Information
DIP (N) Package, 10 sec.
TO-5 (H) Package, 10 sec.
SO (M) Package, Vapor Phase (60 sec.)
Infrared (15 sec.)
50mA
600mW
-60'C to + 150'C
Operating Temperature Range
LM168
-55'Cto +125'C
LM268
-40'Cto +85'C
LM368
O'Cto +70'C
+ 260'C
+300'C
+215'C
+ 220'C
See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" (Appendix D) for other methods of
soldering surface mount devices.
Electrical Characteristics (Note 1)
LM168/LM268/LM368
Parameter
Conditions
VOUT Error: LM168B, LM268B
LM368
Typical
Tested
Limit
(Note 2)
±0.02
±0.02
±0.05
±0.1
Design
Limit
(Note 3)
Units
(Max. unless
noted)
%
%
Line Regulation
(VOUT +3V) ~ VIN ~ 30V
±0.0001
±0.0005
%N
Load Regulation
(Note 4)
o mA ~
ISOURCE ~ 10 mA
-10 mA ~ ISINK ~ 0 mA
±0.0003
±0.003
±0.001
±0.008
%/mA
%/mA
Thermal Regulation
T = 20 mS (Note 5)
±0.005
±0.01
%/100mW
250
350
/k A
3
5
/k AN
±5
±7.5
±11
±15
±10
±15
±20
±30
ppml'C
ppml'C
ppml'C
ppml'C
30
70
100
mA
Quiescent Current
Change of Quiescent Current vs. VIN
(VOUT +3V) ~ VIN ~ 30V
Temperature Coefficient
of VOUT (see graph): LM168BY
(Note 6)
LM2688Y
LM368Y
LM368
-55'C ~
-40'C ~
O'C ~ TA
O'C ~ TA
Short Circuit Current
VOUT
Noise:
=
TA ~ 125'C
TA ~ 85'C
~ 70'C
~ 70'C
0
10.0V: 0.1 -10Hz
100Hz -10 kHz
6.2V: 0.1 - 10Hz
100Hz -10 kHz
5.0V: 0.1 - 10Hz
100Hz-10kHz
VOUT Adjust Range: 10.000V
5.000V
30
1100
20
700
16
575
OV ~ VPIN5 ~ VOUT
Note 1: Unless otherwise noted, these specifications apply: TA = 2Sg C, VIN
=
4.5-17.0
4.4-7.0
15V, 'LOAD = D, 0
5;;
uVp-p
nV/,fHz
uVp·p
nV/,fHz
uVp·p
nV/,fHz
6.0-15.5
4.5·6.0
Vmin.
Vmin.
CL :::;: 200 pF, Circuit is operating in Series Mode. Or, circuit is
operating in Shunt Mode, VIN = + ISV or VIN = VOUT. TA = + 2S'C. ILOAD = -1.0 mAo 0 ,; CL ,; 200 pF.
Note 2: Tested Limits are guaranteed and 100% tested in production.
Note 3: DeSign Limits are guaranteed (but not 100% production tested) over the indicated temperature and supply voltage ranges. These limits are not used to
calculate outgoing quality levels.
Note 4: The LM168 has a Class B output, and will exhibit transients at the crossover point. This point occurs when the device is asked to sink approximately
120 p.A. In some applications it may be advantageous to preload the output to either VIN or Ground, to avoid this crossover point.
Note 5: Thermal Regulation is defined as the change in the output Voltage at a time T after a step change in power dissipation of 100 mW.
Nole 6: Temperature Coefficient of VOUT is defined as the worst case delta,Vour measured at Specified Temperatures divided by the total span of the Specified
Temperature Range (Sea graphs). There is no guarantee that the Specified Temperatures are exactly at the minimum or maximum deviation.
Nole 7: In metal can (H). 0J_C is 7S'C/W and 0J-A is ISO"c/W. In plastic DIP. 0J-A is 160'C/W. In 50-8. 0J-A is 180'C/W. in TO-92. 0J_A is 160'C/W.
Note 8: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its Rated Operating Conditions (see Note 1 and Conditions).
7-47
co
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Typical Performance Characteristics
..J
......
Quiescent Current vs. Input
Voltage and Temperature
co
CD
N
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..
"...
E
(Note 1)
Dropout Voltage vs. Output Current
(Series Mode Sourcing Current)
Output Change vs.
Output Current
3
'
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CD
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125"C
:!E
25"C"
..J
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1".000 ~
r-~J"CI
i""
-
25"C
~12p i""~
-55"C
I!!
.
.~
2
40
4
6
Ripple Rejection
100
§:
~
3\.
10
z
:l!i
~
...
.
~
'"
..!.
>'
~
~
iii
~
0.1
J'
.
~0.001
~
0.01
~
100
lk
10k
FREQUENCY (Hz)
lOOk
10
Temperature Coefficient:
LM368·10 (Curve A)
10
I
~10.DOOV
fJ
...
~
~ --, 1.
N 'jj
I
I
1.-70 -..,1
: '" I,
0
-10
-
1
1_-
-5
~
,
/
-'
10
I..
31-
~_
.! ...
lk
10k lOOk
FREQUENCY (Hz)
~
lS
!i!
...
E
~
-10
-55 -40
'"
~ 10.000Y
!j
I
I
0 25
10 85
TEMPERATURE ("C)
10k
lOOk
10
w
I
I
lk
Temperature CoeffiCient:
LM168·10 (Curve C)
ii1
III
I
125"- "'"i
i
100
FREQUENCY (Hz)
I
- --- ,.....
19.35 mY
I
-5
~
0.1
10
..
r'. ---
~
~10.000V
!j
v"
~
1M
!
iiiw
~
0.01
100
10
o 25 1085 125
TEMPERATURE ("C)
Typical Temperature Coefficient Calculations:
-55 -40
3 1
§
1/
Temperature CoeffiCient:
LM268·10 (Curve B)
j
~
Output Impedance VS. Frequency
(Sinking Current)
Frequency
I
0.0001
10
VS.
I.oIJI
0.01
10
OUTPUT CURRENT (mA)
100
0.1
z
~
!l
-3
-4
-10
I
~~
~4
SOURCING
-1
OUTPUT CURRENT (mA)
Output Impedance vs. Frequency
(Sourcing Current)
~
-2
ro
8
I'
SINKING
:l!
:z:
'"
10
20
30
INPUT VOLTAGE (V)
1"1..
>'
.s
...
125
5!
~
-5
..
-10
, -~
--- - _.- J
"
r
t-,, t-J ____ ~1A,
9.35 mY
'"
180"
-55 -40
0 25
10 85
TEMPERATURE ("C)
LM368-10 (see Curve A)
LM268·10 (see Curve B)
LM 168-1 0 (see CUrve C)
T.C.~7.7
T.C.~9.35
T.C.=9.35 mV/(180"Xl0V)
mV/(70"xl0V)
mV/(12S"Xl0V)
~7.5X 10E·6~7.5ppm/"C
=IIXl0E-6=llppm/"C
(3) with tOn in series with 10 ILl. VOUT to Gnd.
(4) with Both.
I
1&00
(2) with 0.Q1 ILl Mylar. Trim to Gnd.
11200
....... ....
1800
1400
"
I
I
i ' ~ov
5V I---
-
o
10
100
lk
FREQUENCY (Hz)
10k
TLlH/5522-5
7-48
TLlH/5522-4
= 5.2 x 1 OE·6 ~ S.2ppml"C
Output NOise VS. Frequency
(1) LM368 alone.
125
r
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en
Typical Applications
Narrow Range Trimmable Regulator (± 1% min.)
Wide Range Trimmable Regulator
Y+
CO
......
r
3!:
en
I\)
r---J.!----
-Your
R=
YTLlH/5522-11
y. LF444A or
% LF412A
Thin Film Resistor Network,
±O.05% Ma1ching and 5ppm Tracking
(Beckman 694-3-R-l0K·A),
(Caddock T-914-10K-l00·05)
or similar.
7·49
=
TL/H/5522-12
II
Typical Applications (Continued)
Multiple Output Voltages
y+
20Y
lOll
1:.a...-"!_~IOV
r ......-,!:......-+.--1OV
4.7k
TUH/5522-14
TUH/5522-13
y+
R-
Thin Film Resistor Network
0.05% Matching and Sppm Tracking
(Beckman 694-3·R-10K-AI.
(Caddock T-914·1 OK·1 OO-OSI
or similar.
TL/H/5522-15
Reference with Booster
100 mA Boosted Reference
Y+
Y+
1110-200
lW
~ (0PT11JNAl
r .........-,~--+---~~---
~ PRE-LOADI
------~
VOUT
*50!'F
TUH/5522-16
TL/H/5522-17
7-50
r---------~----------------------------------------------------------------__.
Typical Applications
r
....3:
(Continued)
0)
co
......
r
3:
N
0)
co
......
Buffered High-Current Reference with Filter
~
V+
Co)
0)
co
10k
10k
3.3
'-----:--;r----4----4...... VOUT
3.3k
TL/H/5522-18
Simplified Schematic Diagram
r-------------------t--~-v+
20
~------~--~-~~~--~-VOOT
50k
50k
t--t-'Wv- TRIM
55k FOR 5V
170k FOR lOV
'-----~-~--~-_t--_t-_t--~----V-
'Reg. U.S. Pat. Off.
7-51
TUH/5522-6
•
en
(Q
~ ~National
$,.. ~ Semiconductor
PRELIMINARY
== LM169/LM369 Precision Voltage Reference
....I
General Description
Features
The LM169/LM369 are precision monolithic temperaturecompensated voltage references. They are based on a buried zener reference as pioneered in the LM199 references,
but do not require any heater, as they rely on special temperature-compensation techniques (Patent Pending). The
LM169 makes use of thin-film technology enhanced by the
discrete laser trimming of resistors to achieve excellent
Temperature coefficient (Tempco) of Vaut (as low as 1
ppmrC), along with tight initial tolerances (as low as
0.01 %). The trim scheme is such that individual resistors
are cut open rather than being trimmed (partially cut), to
avoid resistor drift caused by electromigration in the
trimmed area. The LM169 also provides excellent stability
vs. changes in input voltage and output current (both sourcing and sinking). The devices have a 10.000V output and
will operate in either series or shunt mode; the output is
short-circuit-proof to ground. A trim pin is available which
permits fine-trimming of Vaut' and also permits filtering to
greatly decrease the output noise by adding a small capacitor (0.05 to 0.5 fLF).
•
•
•
•
•
Low Tempco of Vaut
Excellent initial accuracy (0.003%)
Excellent line regulation (2 ppm/V)
Excellent output impedance
Excellent thermal regulation
•
•
•
•
Low noise
Easy to filter output noise
Low dissipation - 20 mW
Operates in series or shunt mode
Connection Diagrams
Metal Can Package (H)
Dual-In-Line Package (N)
or S.O. Package (M)
'0
*
+VIN
2
7
8 '
•
GROUND
3
4
6
5
VOUT
•
FILTER AND
TRIM PIN
TLlH/9110-5
Top View
Order Number LM369DM, LM369N,
LM369BN, LM369CN or LM369DN
See NS Package Number MOSA or NOSE
GROUND
TLlH/9110-1
Top View
(Case is connected to ground.)
8
TO-92 Plastic Package (Z)
VOUT
,. Do not connect; internal connection for factory trims.
Order Number LM169H, LM169BH,
LM369H, LM369BH,
See NS Package Number HOSC
GROUND
+VIN
TL/H/9110-28
Bottom View
Order Number LM369DZ
See NS Package Number Z03A
7-52
Absolute Maximum Ratings
(Note B)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Input Voltage (Series Mode)
Soldering Information
+ 260·C
DIP (N) Package, 10 sec.
TO-5 (H) Package, 10 sec.
+300·C
SO (M) Package, Vapor Phase (60 sec.)
+215·C
+ 220·C
Infrared (15 sec.)
See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" (Appendix D) for other methods of
soldering surface mount devices.
35V
Reverse Current (Shunt Mode)
50mA
600mW
Power Dissipation (Note 7)
Storage Temperature Range
- 60·C to + 150·C
Operating Temperature Range
LM169
LM369
(Tj min to Tj max)
-55·C to + 125·C
O·Cto +70·C
ESD Tolerance
Czap = 100 pF, Rzap = 1.5k
Electrical Characteristics, LM169, LM369
Parameter
Conditions
Typical
(Note 1)
Tested
Limits
(Note 2)
Design
Limit
(Note 3)
Units
(Max
Unless
Noted)
V
+ 10.000
Vout Nominal
BOOV
Vout Error
(Note 11)
50
0.50
±500
±5
Vout Tempco
LMI69B, LM369B
LM169, LM369
LM369C
(Note 6) (Note 11)
Tmin < Tj < T max
Tmin < Tj < T max
Tmin
8
- 'f
II
+250(;
+250(;
+1250(;
I
I-
11
o
10
I
s:tl
10
!5
0. I
O
I'\.
_f- I- -+1250(;
1-
I
I
I
_ SINKING CURRENT
1 (Cl=O.II'F TANTALUM)
L.
I-
§
TANrALUM
I/SOURCING
CURRENT
0.0 I
0.00 I
10
100
lK
I
I
I
I
10K
lOOK
~z
ii!
~
_
~
Start-up Response
1.0
'E
10
~
0
0.1
j
C1,=1 0 I'F
10K
lOOK
10
100
lK
1M
20
,.
~
~z
5
0
CFlLTER=O
I'
100
o
10
-
!5
....... C"l1!R = 0.0331'F
.......,..,.1
cr<1!R = 0.331'F
100
103
~
-25OC +25OC
8 -55OC -5OC
FREQUENCY (Hz)
1.6mV
20
15
~ _2r-'L-_~_--+-~--r--~;t1!"
"- i'
10
0.0001 0.001
~ -4r-r--+--~--r-7-1
0.01
TL/H/9110-24
o
0.1
TL/H/9110-25
-6r-~-+--~--r-r-1
-8
-75
-50
180· - \ - +50
+100 +150
+125
TEMPERATURE (OC)
LM369 Temperature
Coefficient
-5OC +25CC
3
I
I
-2
-3
LM169 (see curve above):
T.C. ~ 1.6 mV/(IS0' x 10V)
~ 8.9 x 10- 7 ~ 0.89 ppml'C
b.5~V
). ~-- I
I
--
-- I - -
~
;:!
Typical Temperature Coefficient Calculations:
+700c
:1
I
I
~
TL/H/9110-26
:1
I
~
g
~
O
100
TLiH/9110-6
+700c +1250(;
25
FILTER CAPACITOR (PIN 5 TO GROUND) {J'F)
1
80
30
o
o
105
60
LM169 Temperature
Coefficient
Output Noise vs Filter
Capacitor
';;;
40
llME{J's)
40
~
~
!5
I
J
FREQUENCY (Hz)
400
200
;
0.001
35
~
VIN
10
0,01
Output Noise vs Frequency
300
I--
Cl=O
OR O.II'F ~-
1M
500
!:
+10
OUTPUT CURRENT (mA)
20
FREQUENCY (Hz)
@
r-
-
-10
Ripple Rejection
vs Frequency
//
V
SOURCING
I
-2
10
10
1/ Cl =IO I'F
Cl=O/I
SINKI~ "
OUTPUT CURRENT(mA)
Output Impedance
vs Frequency
100
s
,.-l-
o
o
30
20
INPUT VOLTAGE (V)
~a;
-5~OC
.... f- -r
1
1).4
0.0
3
I
r~55OC
DB
Output Change vs
Output Current
I
I
I
I
-,
-
LM369 (see curve alleft):
T.C. ~ 0.5 mV/(7S' x 10V)
~ 6.7 X 10- 7 ~ 0.67 ppm/'C
I
I
-75oc-l1
I
I
-4
-75 -50 -25 0 25 50 75 100125150
TEMPERATURE (OC)
7-55
TLiH/9110-27
•
en .---------------------------------------------------------------------------------,
CD
(W)
:::a:
-J
......
en
CD
.,...
:::a:
-J
Application Hints
the circuits shown, to provide an output trim range of ± 10
millivolts. Trimming to a wider range is pOSSible, but is not
recommended as it may degrade the Tempco and the
Tempco linearity at temperature extremes. For example, if
the output were trimmed up to 10.240V, the Tempco would
be degraded by 8 ppml"C. As a general rule, Tempco will
be degraded by 1 ppm/·C per 30 mV of output adjustment.
The LM169/LM369 can be applied in the same way as any
other voltage reference. The adjacent Typical Applications
Circuits suggest various uses for the LM169/LM369. The
LM169 is recommended for applications where the highest
stability and lowest noise is required over the full military
temperature range. The LM369 is suitable for limited-temperature operation. The curves showing the Noise vs. Capacitance in the Typical Performance Characteristics section show graphically that a modest capaCitance of 0.1 to
0.3 microfarads can cut the broadband noise down to a level of only a few microvolts, less than 1 ppm of the output
voltage. The capaCitor used should be a low-leakage type.
For the temperature range 0 to 50·C, polyester or Mylar®
will be suitable, but at higher temperatures, a premium film
capaCitor such as polypropylene is recommended. For operation at + 125·C, a Teflon® capaCitor would be required, to
ensure sufficiently low leakage. Ceramic capacitors may
seem to do the job, but are not recommended for production use, as the high-K ceramics cannot be guaranteed for
low leakage, and may exhibit piezo-electric effects, converting vibration or mechanical stress into excessive electrical
noise.
Additionally, the inherent superiority of the LM169/369's
buried Zener diode provides freedom from low-frequency
noise, wobble, and jitter, in the frequency range 0.01 to 10
Hertz, where capacitive filtering is not feasible.
The output can sink current as well as source it, but the
output impedance is much better for sourcing current. Also,
the LM169/369 requires a 0.1 ",F tantalum capaCitor (or,
0.1 ",F in series with 100) bypass from the output to ground,
for stable operation in shunt mode (output sinking current).
The output has a class-B stage, so if the load current changes from sourcing to sinking, an output transient will occur.
To avoid this transient, it may be advisable to preload the
output with a few milliamperes of load to ground. The
LM169/369 does have an excellent tolerance of load capacitance, and in cases of load transients, electrolytic or
tantalum capacitors in the range 1 to 500 microfarads have
been shown to improve the output impedance without degrading the dynamic stability of the device. The LM169/369
are rated to drive an output of ± 10 mA, but for best accuracy, any load current larger than 1 mA can cause thermal
errors (such as, 1 mA x 5V x 4 ppm/1 00 mW = 0.2 ppm
or 2 microvolts) and degrade the ultimate precision of the
output voltage.
The output is short-circuit-proof to ground. However, avoid
overloads at high ambient temperatures, as a prolonged
short-circuit may cause the junction temperature to exceed
the Absolute Maximum Temperature. The device does not
include a thermal shut-down circuit. If the output is pulled to
a positive voltage such as + 15 or + 20V, the output current
will be limited, but overheating may occur. Avoid such overloads for voltages higher than +20 V, for more than 5 seconds, or, at high ambient temperatures.
Pins 1, 3, 7, and 8 of the LM169/369 are connected to
internal trim circuits which are used to trim the device's output voltage and Tempco during final testing at the factory.
Do not connect anything to these pins, or improper operation may result. These pins would not be damaged by a
short to ground, or by Electrostatic Discharges; however,
keep them away from large transients or AC Signals, as
stray capacitance could couple noises into the output.
These pins may be cut off if desired. Alternatively, a shield
foil can be laid out on the printed circuit board, surrounding
these pins and pin 5, and this guard foil can be connected to
ground or to You!, effectively acting as a guard against AC
coupling and DC leakages.
The LM169/369 has an excellent long-term stability, and is
suitable for use in high-resolution Digital Voltmeters or Data
Acquisition systems. Its long-term stability is typically 3 to 10
ppm per 1000 hours when held near T max, and slightly better when operated at room temperature. Contact the factory
for availability of devices with proven long-term stability.
The trim pin (pin 5) should also be guarded away from noise
Signals and leakages, as it has a sensitivity of 15 millivolts of
~Vou! per microampere. The trim pin can also be used in
Typical Applications
Series Reference
Shunt Reference with Optional Trim
1=2mA
1:
"2.----+---.....-- ~~:.~OV
IN
V+
13V:SV :S30V
j2
IN
LM369
OUT":--
~~~~;OV
GND
IN
LM369
GND
-t
OUT
~
!
13V:S
2M
TRIM r--i-"M......~
'--';;1'r.4- - - '
TL/H/9110-2
Series Reference with
Optional Filter
for Reduced Noise
::=~Mr
;-----llRlt.t LM369
50 K
~
:S 30Y
O~r~T
(tl0mV)
:~"J.&F
LOW LEAKAGE
OUT":--~\':.~V
GND
14
±
-::t:-
TL/H/9110-4
TUH/9110-3
7-56
Typical Applications (Continued)
± 10V Reference
± 5V Reference
+15
V+
2
~O.IP.F
IN
LM369
I--
OUTPUT
+10.000V
OUT 6
2
IN
LM369
OUT
TRIM,
6
+5V
2M
5
50K
TRIM
GND
2
1OK
4
LM369
o. 1%
OUT 6
7K 2
6 """l'M60;
GND
'-____~4----- ~~~~~OV
~
0.01
'1r'~
p.~
--
-
1=2mA
I OK
O. 1 %
-5V
VTL/H/9110-7
-15
TLlH/9110-8
Multiple Output Voltages
23V :s VIN :s 35V
23V :s VIN :s 30V
1
2
T2
IN
IN
OUT
LM369
GND
.!... 20V
LM369
OUT~-""-
5
TRIM ~
20V
10K
4
2
IN
OUT~-""'-10V
OUT 6
LM369
GND
TRIM
~
LM369
10V
0.1 p.F
TANTALUM
4.7K
4
..L
TL/H/9110-10
TL/H/9110-9
24V :s VIN :s 30V
A
TL/H/9110-11
7-57
~
Thin Film Aesistor Network
0.05% Matching and 5 ppm Tracking
(Beckman 694·3·R·l OK·A).
(Caddock T·914·1 OK·l 00·05)
(Allen Bradley FOBB103A)
or similar.
,.
en ,---------------------------------------------------------------------------------,
CD
C')
~
Typical Applications
(Continued)
Precision Wide-Range Current Source
"enCD
-
+15
:::::i
....I
10K·
0.1 pr
TANTALUM
A,
10K·
= LF411A, LM607, LM308A
or similar
0,,02
= high {J PNP,
8.2K
(+12VO!::VOUT O!::-20V)
5%
PN4250, 2N3906,
or similar
I
• = Part of Precision Resistor Network,
±0.05% ~a1ching,
(Allen Bradley F08B103A)
(Caddock T·914-1 OK-1 00·05)
(Beckman 694-3-R-10K-A)
or similar
t
-15
IOUT=
2V
Rx
TL/H/9110-18
± 10V, ± 5V References
+15V
+5V
A =
'!4 LF444A or
Yo LF412A or
LM607
R
-5V
= Thin Film Resis10r Network
0.05% Matching and 5 ppm Tracking
(Beckman 694·3·R-10K·A),
(caddock T-914·10K-100-05)
(Allen Bradley F08B103A)
or similar.
-15V
Reference with Booster
TL/H/9110-12
100 mA Boosted Reference
V+
14V:SVIN :S31V
470
3.3
Ql
2N2907
100-200
2
IN
LM369
lW
OUTa-;6;....~~_--VOUT
5
I
I
I
~-+-"",--VOUT
<:(OPTlONAL
+ ~ PRE-LOAD)
(OPTlONAL
PRE-LOAD)
I
I
TL/H/9110-13
TUH/9110-14
7-58
Typical Applications
(Continued)
Precision Programmable Supply
+15V
+15V
21
DAC1655
18
PINS 1-16
DIGITAL
INPUTS----------'
A1, A2, A3 = LF411A, LM607, or similar
-15V
TLlH/9110-21
Current Source
-30V
2k,;; Ax,;; 10M
TL/H/9110-16
Precision Current Source
+15
~o1jr
LEAKAGE
Rx
GND
O.lpF
4
10.0.
22K
10K
5%
•
-15
lour=
01,02 = high P PNP,
PN4250, 2N3906
10V
Rx
or similar
A1
= LM607, LMll, LF411A
or similar
TL/H/9110-17
7-59
0)
CD
;
Typical Applications (Continued)
::::!
. Oscilloscope Calibrator
0)
.,..
CD
==
...I
12
224
TO
SCOPE
~
,
ir
1K
t----i
Ot------'
,
,-
1 WHz
[:>0 =
51
MM74HC04
FREQUENCY
SELECTOR
(1M Hz, 976Hz)
,,
49.9K
,,,
49.94
AWPLITUDE
SELECTOR
52
(10V, lDmV)
TL1H/9"O-22
Precision Wide-Range Current Sink
10V
lout
=
Ax
A, ~ LM1', LM607 or similar.
(V3 + 2V) s: VOU! s: +20V.
~ high Bela NPN, 2N3707, 2N3904 or similar.
aI, 02
-20V
TLiH/911 0-'9
Digitally Variable Supply
+15V
2
IN
Lt.l369
OUT
VOU! ~ -10V x (Digilally Sel Gain).
A, ~ LMllA, LM607, or similar.
MDAC ~ DAC1220, DAC1208, DAC1230, or similar.
TLiH/911 0-20
7-60
r
Typical Applications
s:
.....
(Continued)
0)
cg
.......
r
Ultra-Low-Noise Statistical Reference
s:
+15V
CJ,)
0)
REPEAT
cg
~-----1~----~------.------'-----AS
DESIRED
• __ .&. _.
I
I
: LI.l369:--.
I
I
..L
I-=
I
I
I
I
·--T-· :
I
.J..
SEE
NOTE
R
I
I.
::R
...---+----4---_...-.---..-1-0UTPUT
OPTIONAL OUTPUT BUFFER
10K
BUFFERED
OUTPUT
10K
1 )LF
X. POLYPROPYLENE
TLlH/9110-23
200n s; R s; lk
When N pieces of LM369 are used, the Vout noise is decreased by a factor of
TN1
If the output buffer is not used, for lowest noise add 0.1 I'F Mylar® from ground to pin 5 of each LM369.
LM 169 Block Diagram
+VS
VOUT
400.0.
OUTPUT
TRIMS
.....
..!.,
- - - ..
.....
•• ---"3,
10K
".
t"~r-I --~~-==t::t----+---f 5 TRIM
AND
FILTER
....
22K
L--.L--------=t:===t:==:::.r
•• PATENT PENDING
4
GROUND
TL/H/9110-15
.. Do not connect; internal connection for factory trim.
•
7-61
C'!
.....
•
II)
co
('I)
::a:
....I
......
J?JI National
~ Semiconductor
C'! LM185-1.2/LM285-1.2/LM385-1.2
.....
·
It)
co
C\I
::a:
....I
......
C'!
.....
·
It)
co
.....
::a:
....I
Micropower Voltage Reference Diode
General Description
The LM185-1.2/LM285-1.2/LM385-1.2 are micropower
2-terminal band-gap voltage regulator diodes. Operating
over a 10 )J-A to 20 rnA current range, they feature exceptionally low dynamic impedance and good temperature stability. On-chip trimming is used to provide tight voltage tolerance. Since the LM185-1.2 band-gap reference uses only
transistors and resistors, low noise and good long term stability result.
Careful design of the LM185-1.2 has made the device exceptionally tolerant of capacitive loading, making it easy to
use in almost any reference application. The wide dynamic
operating range allows its use with widely varying supplies
with excellent regulation.
The extremely low power drain of the LM185-1.2 makes it
useful for micropower circuitry. This voltage reference can
be used to make portable meters, regulators or general purpose analog circuitry with battery life approaching shelf life.
Further, the wide operating current allows it to replace older
references with a tighter tolerance part.
The LM185-1.2 is rated for operation over a - 55'C to
125'C temperature range while the LM285-1.2 is rated
- 40'C to 85'C and the LM385-1.2 O'C to 70'C. The LM 1851.2/LM285-1.2 are available in a hermetic TO-4S package
and the LM285-1.2/LM385-1.2 are also available in a lowcost TO-92 molded package, as well as S.O.
Features
• ±4 mV (±0.3%) max. initial tolerance (A grade)
• Operating current of 10 )J-A to 20 rnA
• o.sn max dynamic impedance (A grade)
• Low temperature coefficient
• Low voltage reference-1.235V
• 2.5V device and adjustable device also available
- LM185-2.5 series and LM185 series, respectively
Connection Diagrams
8
TO-92
Plastic Package (Zl
TO-46
Metal Can Package (Hl
~
8
SO Package
+
~
TL/H/551S-10
,
Bottom View
TL/H/551S-6
1
HC
HCHCHC
765
2
HC
3
HC
Bottom View
Order Number LM285Z-1.2,
LM285AZ-1.2, LM285AXZ-1.2,
LM285AYZ-1.2,
LM285BXZ-1.2, LM285BYZ-1.2,
LM385Z-1.2, LM385AZ-1.2,
LM385AXZ-1.2, LM385AYZ-1.2,
LM385BZ-1.2, LM385BXZ-1.2
or LM385BYZ-1.2
See NS Package Number Z03A
Order Number LM185H-1.2,
LM185AH-1.2, LM185AXH-1.2,
LM185AYH-1.2, LM185BXH-1.2,
LM185BYH-1.2, LM285H-1.2,
LM285AH-1.2, LM285AXH-1.2,
LM285AYH-1.2, LM285BXH-1.2
or LM285BYH-1.2
See NS Package Number H02A
4
TL1H/551S-9
Order Number LM285M-1.2,
LM285AM-1.2, LM285AXM-1.2,
LM285AYM-1.2, LM285BXM-1.2,
LM285BYM-1.2, LM385M-1.2,
LM385AM-1.2, LM385AXM-1.2,
LM385AYM-1.2, LM385BM-1.2,
LM385BXM-1.2 or LM385BYM-1.2
See NS Package Number M08A
Applications
Centigrade Thermometer
Wide Input Range
Reference
YIN" 2.3V TO JOV
Calibration
1. Adjust R1 so that Vt
1 mVl-K
1.5Vt
~
temp at
2, Adjust V2 to 273.2 mV
'110 for 1 ,3V to t .6V battery volt·
age ~ 50~At0150~
TL/H/551S-S
TL/H/5518-1
7·62
r-
3:
......
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
(Note 2)
Reverse Current
30mA
Forward Current
10mA
Soldering Information
TO·92 package: 10 sec.
TO·46 package: 10 sec.
SO package: Vapor phase (60 sec.)
Infrared (15 sec.)
Operating Temperature Range (Note 3)
-55·C to
LM185-1.2
LM285-1.2
+ 150·C
260·C
300·C
215·C
220·C
See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" for other methods of soldering surface mount devices.
+ 125·C
-40·Cto + 85·C
0·Ct070·C
LM385-1.2
-55·C to
Storage Temperature
CO
U1
......
N
.......
I
r-
3:
N
CO
U1
......
N
.......
I
r-
3:
Cr.)
CO
U1
......
I
Electrical Characteristics (Note 4)
Parameter
I
N
LM18SA-1.2
LM18SAX-1.2
LM18SAY-1.2
LM28SA-1.2
LM28SAX-1.2
LM28SAY-1.2
Conditions
Tested
Limit
(NoteS)
Typ
Reverse Breakdown
Voltage
IR = 100 ",A
1.235
Design
Limit
(Note 6)
1.231
1.239
1.230
Typ
1.235
1.220
1.245
1.235
8
10
7
IMIN ,;; IR ,;; 1 mA
1
1 mA ,;; IR ,;; 20 mA
10
Minimum Operating
Current
Reverse Breakdown
Voltage Change with
Current
LM38SA-1.2
LM38SAX-1.2
LM38SAY-1.2
7
Tested
Limit
(Note S)
Units
(Limit)
Design
Limit
(Note 6)
1.231
1.239
1.225
1.245
V(Min)
V(Max)
V(Min)
V(Max)
",A
(Max)
8
10
1.5
1
1.5
mV
(Max)
20
10
20
mV
(Max)
n
Reverse Dynamic
Impedance
IR = 100 ",A,f = 20Hz
Wideband Noise (rms)
IR = 100 ",A,
10Hz';; f,;; 10kHz
60
60
",V
Long Term Stability
IR = 100 ",A, T = 1000 Hr,
TA = 25·C ±0.1·C
20
20
ppm
Average Temperature
Coefficient (Note 7)
IMIN ,;; IR ,;; 20 mA
X Suffix
YSuffix
All Others
0.2
0.6
1.5
30
50
0.2
0.6
1.5
ppml"C
(Max)
30
50
150
(Max)
150
•
7-63
C'!
..-
·
In
co
Electrical Characteristics (Continued) (Note 4)
('I)
LM185-1.2
LM185BX-1.2
LM185BY-1.2
LM285-1.2
LM285BX-1.2
LM2858Y-1.2
:s
....I
.......
C'!
..-
·
In
co
Parameter
Conditions
Typ
C'\I
:s
....I
..-
·
In
:s
....I
LM385-1.2
Units
(Limit)
Tested Design Tested Design Tested Design
Limit
Limit
Limit
Limit
Limit
Limit
(Note 5) (Note 6) (Note 5) (Note 6) (Note 5) (Note 6)
.......
C'!
co
......
LM385B-1.2
LM385BX-1.2
LM385BY-1.2
TA = 25'C,
10 fLA s;; IR s;; 20 mA
Reverse Breakdown
Voltage
1.223
1.247
8
10
20
15
20
15
20
fLA
(Max)
10 fLA s;; IR s;; 1 mA
1
1.5
1
1.5
1
1.5
mV
(Max)
1 mA s;; IR s;; 20 mA
10
20
20
25
20
25
mV
(Max)
Minimum Operating
Current
Reverse Breakdown
Voltage Change with
Current
1.223
1.247
V(Min)
V(Max)
1.235
1.205
1.260
1
n
Wideband Noise (rms)
IR = 100fLA,
10 Hz S;; f S;; 10 kHz
60
fLV
Long Term Stability
IR = 100 fLA, T = 1000 Hr,
TA = 25'C ±0.1'C
20
ppm
Average Temperature
Coefficient (Note 7)
IR = 100 fLA
X Suffix
Y Suffix
All Others
Reverse Dynamic Impedance IR
= 100 fLA, f = 20Hz
30
50
30
50
150
150
150
ppml'C
ppml'C
ppml'C
(Max)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics.
The guaranteed specifications apply only for the test conditions listed.
Note 2: Refer to
RETS185H~1.2
for military specifications.
Note 3: For elevated temperature operation, Tj max is:
LM185
150"C
LM285
125"C
LM385
100"C
Thermal Resistance
TO·92
TO·46
SO·8
9JA Gunction to ambient)
180"C/W (004" leads)
170"C/W (0.125" leads)
440"C/W
165"C/W
N/A
80"C/W
N/A
()JC (junction to case)
Note 4: Parameters identified with boldface type apply at temperature extremes. All other numbers apply at TA = TJ = 25"C.
Note 5: Guaranteed and 100% production tested.
Note 6: Guaranteed, but not 100% production tested. These limits are not used to calculate average outgoing quality levels.
Note 7: The average temperature coefficient is defined as the maximum deviation of reference voltage at all measured temperatures between the operating T MAX
and TMIN, divided by TMAX - TMIN. The measured temperatures are -55"C, -40"C, O"C, 25"C, 70"C, 85"C, 125"C.
7·64
r-
:5:
.....
Typical Performance Characteristics
Reverse Characteristics
CXI
Reverse Characteristics
Forward Characteristics
r-
:5:
....,,.,,.mnr-rTTT1,,,,.....,.,.TTm1r1n
1.2
100 , , - - ' - - ' - - - ' - ' - 1 1 - - - ,
Cf1
.....
N
........
N
CXI
1.230
~
l'
1.220
u
10
~
"
z
~
0.1)1
TEMPERATURE I·CI
Noise Voltage
:5
~
g
10
~
1
10
0.1
~
"'"
300
100
lk
10k
FREOUENCY IHzl
lOOk
lk
10k
lk
10k
lOOk
1M
/ ~..~,UTPJT= II----
t:)
0.5
I---
~
40
CUTOFF FREQUENCY IHd
100
1.0
lOOk
f-'"""'=
~
0
10
/V
:>
1.5
50
~
~,
V
Response Time
~
100
/
V
10
2.0
Q
200
TA =25"C
'.= 100".
FREQUENCY (Hz)
~
'00
100
11--'
100
60
~
f'
0
z
100
Filtered Output Noise
600
::?
~
70
In'" 10DIJA
I~
lk
REVERSE CURRENT (mAl
700
500
s:
O.
-55-35-15 5 25 45 65 85105125
10
Reverse Dynamic Impedance
10k
~O!i
~
u
;;
,..
0.1
FORWARD CURRENT (rnA)
s
z
r- ,...
1,,1"'"
0.01
100
Reverse Dynamic Impedance
r-
10-'"
w
!:;
10
100 r-T-m'1Tllr-,-mrnrTTTT1T11r"nT""1I
Iri=lho"~
~ 1.250
0.1
REVERSE CURRENT (rnA)
REVERSE VOLTAGE (VI
f-I--
I'N 'UT I
I I
200
.00
600
TIME (,.lSl
TLlH/551B-3
fJI
7-65
C"!
.,...
•
II)
co
:iE
Applications (Continued)
C")
....I
Micropower Reference
from 9V Battery
Reference from
1.5V Battery
9V
1.5V
t,
C'.,...i
ab
~
k
~
SoOk
:iE
.....
....I
.
C"!
.,...
1.2V
':" LM38S-1.Z
1.2V
':" LM385-1.2
II)
co
.,...
TL/H/5518-2
:iE
....I
LM385 Applications
Micropower* 5V Regulator
Mlcropower* 10V Reference
~------",-------",_--V'N?5.2V
In
r----.·,;....-VIN-15V
1M
....-_... ,OV
>~
VO=5V
r--~""~"'IL'" 100mA
150 pF
3.5M
500k
LM385-1.2
10M
2k
·'0 '" 20 ILA slandby current
·'0 '" 30 p.A
Precision 1 ,...A to 1 mA Current Sources
LM385·1.Z
LM385-1.2
CI
150pF
1.5V TO 2 7 V - - - -...- - - - " " , . , .....
....
-1.5V TO -27V --....;;.-...---t-~""'
-30V
·'oUT~~
R2
7·66
TUH/5518-4
r-
LM385 Applications
s:
.....
(Continued)
(X)
U1
.....
I
N
.....
METER THERMOMETERS
O°C -100°C Thermometer
r-
s:
N
Lower Power Thermometer
(X)
U1
.....
I
ISO
N
.....
r-
s:
I.HO
1.6V'
(,.)
(X)
U1
Ok TO
I
mt
1.5V
(1.J-1.6Vl t
R4
220
* 2N3638 or 2N2907 select for inverse HFE
~
5
t Select for operation at 1.3V
t
10 '" 600 I'A to 900 I'A
Calibration
I. Short LM385-1.2, adjusl A3 for
10uT~temp
at I I'AI"K
2. Remove short, adjust R2 for correct reading in centigrade
tlo at 1.3V'" 500l'A
IQ all.6V '" 2.4 mA
Micropower Thermocouple Cold Junction Compensator
ISO
2k
1%
5.lk
1M
1%
MERCURY
CELL
V-
+
ZERO AOJ
TC AOJ
500
lOOk
1.345V
LM385-1.2
1.3-1.6V
RI
R2
+
R4
100
THERMOCOUPLE
+
METER
'_I
COLD JUNCTION
ISOTHERMAL
WITH lM334
Calibration
1. Short LM385-1.2, adjust A3 for
IOUT~
TL/H/5518-5
temp at 1.8 I'Af'K
2. Remove short, adjust R2 for correct reading in of
Adjustment Procedure
1. Adjust Te ADJ pot until voltage across R1 equals Kelvin temperature
multiplied by the thermocouple Seebeck coefficient.
2. Adjust zero ADJ pot until voltage across R2 equals the thermocouple
Seebeck coefficient multiplied by 273.2.
Thermocouple
Seebeck
At
R2
Voltage
Voltage
Type
Coefficient (0)
(0)
AcrossR1 AcrossR2
@2S'C
(I'VI"C)
(mV)
(mV)
523 1.24k
52.3
15.60
14.32
T
12.77
11.78
42.8
432
lk
12.17
11.17
K
412 9530
40.8
S
63.4 150n
1.908
1.766
6.4
Typical supply current 50 ].LA
7-67
II
...C'!
I
Ll)
co
CO)
:E
Schematic Diagram
..J
......
C'!
...
I
Ll)
co
N
:E
..J
......
...C'!
...co
:E
I
Ll)
..J
TL/H/551B-7
7-68
.....
....3:
~National
Q)
·
U1
N
~ Semiconductor
en
......
.....
3i:
LM 185-2.5/LM285-2.5/LM385-2.5 Micropower
Voltage Reference Diode
N
Q)
U1
N
•
en
......
.....
General Description
The LM185-2.5/LM285-2.5/LM385-2.5 are micropower 2terminal band-gap voltage regulator diodes. Operating over
a 20 ,..,A to 20 mA current range, they feature exceptionally
low dynamic impedance and good temperature stability. Onchip trimming is used to provide tight voltage tolerance.
Since the LM-185-2.5 band-gap reference uses only transistors and resistors, low noise and good long term stability
result.
Careful design of the LM185-2.5 has made the device exceptionally tolerant of capacitive loading, making it easy to
use in almost any reference application. The wide dynamic
operating range allows its use with widely varying supplies
with excellent regulation.
The extremely low power drain of the LM185-2.5 makes it
useful for micropower circuitry. This voltage reference can
be used to make portable meters, regulators or general purpose analog circuitry with battery life approaching shelf life.
Further, the wide operating current allows it to replace older
references with a tighter tolerance part. For applications requiring 1.2V see LM185-1.2.
The LM185-2.5 is rated for operation over a -55'C to
125'C temperature range while the LM285-2.5 is rated
- 40'C to 85'C and the LM385-2.5 O'C to 70'C. The LM 1852.5/LM285-2.5 are available in a hermetic TO-46 package
and the LM285-2.5/LM385-2.5 are also available in a lowcost TO-92 molded package, as well as S.O.
Features
•
•
•
•
•
•
±20 mV (±0.8%) max. initial tolerance (A grade)
Operating current of 20 p.A to 20 mA
0.6.0. dynamic impedance (A grade)
Low temperature coefficient
Low voltage reference-2.5V
1.2V device and adjustable device also availableLM185-1.2 series and LM185 series, respectively
Applications
f
Micropower Reference from 9V Battery
Wide Input Range Reference
VIN '" J.1V TO lOV
9Y 200k
lMJl4
Z.5Y
J.JIt
OUT
~~M38s.z.5
"'="
'::' LM385·2.5
2.5V
TL/H/5519-2
TLlH/5519-12
Connection Diagrams
TO-92
Plastic Package
TO-46
Metal Can Package
TL/H/5519-B
Bottom View
Order Number LM285Z-2.5,
LM285AZ-2.5, LM285AXZ-2.5,
LM285AYZ-2.5,
LM285BXZ-2.5, LM285BYZ-2.5,
LM385Z-2.5, LM385AZ-2.5,
LM385AXZ-2.5, LM385AYZ-2.5,
LM385BZ-2.5, LM385BXZ-2.5
or LM385BYZ-2.5
See NS Package Number Z03A
(3
SO Package
Y7 Ys
NICs
TLlH/5519-13
Bottom View
Order Number LM185H-2.5,
LM185AH-2.5, LM185AXH-2.5,
LM 185AYH-2.5, LM 185BXH-2.5,
LM185BYH-2.5, LM285H-2.5,
LM285AH-2.5, LM285AXH-2.5,
LM285AYH-2.5, LM285BXH-2.5
or LM285BYH-2.5
See NS Package Number H02A
7-69
TL/H/5519-11
Order Number LM285M-2.5,
LM285AM-2.5, LM285AXM-2.5,
LM285AYM-2.5, LM285BXM-2.5,
LM285BYM-2.5, LM385M-2.5,
LM385AM-2.5, LM385AXM-2.5,
LM385AYM-2.5, LM385BM-2.5,
LM385BXM-2.5 or LM385BYM-2.5
See NS Package Number M08A
3i:
w
Q)
·
U1
N
en
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
(Note 2)
- 55·C to
Storage Temperature
Soldering Information
TO·92 Package (10 sec.)
TO-46 Package (10 sec.)
SO Package
Vapor Phase (60 sec.)
Infrared (15 sec.)
Reverse Current
30mA
Forward Current
10mA
Operating Temperature Range (Note 3)
-55·Cto + 125·C
LM185·2.5
LM285·2.5
-40·C to + 85·C
O·Cto 70·C
LM385-2.5
+ 150·C
260·C
300·C
215·C
220·C
See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" for other methods of soldering surface mount devices.
Electrical Characteristics (Note 4)
Parameter
Conditions
LM185A-2.5
LM185AX-2.5
LM185AY-2.5
LM285A-2.5
LM285AX-2.5
LM285AY-2.5
Typ
Tested
Limit
(Note 5)
Reverse Breakdown
Voltage
IR
= 100 !LA
2.500
-
-
2.460
2.535
.. -
Minimum Operating
Current
Tested
Umit
(Note 5)
12
Units
(Limits)
Design
Umit
(Note 6)
2.480
2.520
2.480
2.520
2.500
.
Design
Limit
(Note 6)
LM385A-2.5
LM385AX-2.5
LM385AY-2.5
2.470
2.530
18
20
18
20
V(Min)
V(Max)
V(Min)
V(Max)
!LA
(Max)
Reverse Breakdown
Voltage Change with
Current
IMIN ,:: IR ,:: 1mA
1
1.5
1
1.5
mV
(Max)
1 mA ,:: IR ,:: 20 mA
10
20
10
20
mV
(Max)
Reverse Dynamic
Impedance
IR = 100 !LA.
f = 20 Hz
0.2
Wideband Noise (rms)
IR = 100 !LA
10 Hz':: f':: 10 kHz
120
!LV
Long Term Stability
IR = 100 !LA.
T = 1000 Hr.
TA = 25·C ±0.1·C
20
ppm
Average Temperature
Coefficient (Note 7)
IMIN ,:: IR ,:: 20 mA
X Suffix
Y Suffix
All Others
0.6
0.6
1.5
1.5
30
50
30
50
150
7-70
0.
ppml"C
(Max)
150
r
:s:
......
Electrical Characteristics (Continued) (Note 4)
(1)
U1
I
LM185-2.5
LM185BX-2.5
LM185BY-2.5
LM285-2.5
Parameter
Conditions
Typ
LM285BX-2.5
LM285BY-2.5
Tested
Limit
(Note 5)
Reverse Breakdown
Voltage
TA = 25·C.
20/LA ,,; IR ,,; 20 mA
2.5
N
......
LM385B-2.5
LM385BX-2.5
LM385BY-2.5
LM385-2.5
I
Tested
Limit
(Note 6)
Limit
(Note 5)
Design
Limit
(Note 6)
Tested
Limit
(Note 5)
2.462
2.536
Reverse Breakdown
r
s:
w
(1)
(Note 6)
V(Min)
V(Max)
2.425
2.575
20
30
20
30
/LA
(Max)
20/LA ,,; IR ,,; 1 mA
1
1.5
2.0
2.5
2.0
2.5
mV
(Max)
1 mA ,,; IR ,,; 20 mA
10
20
20
25
20
25
mV
(Max)
Reverse Dynamic
Impedance
IR = 100 /LA.
f=20Hz
Wideband Noise (rms)
Long Term Stability
Average Temperature
Coefficient (Note 7)
......
Design
Limit
30
13
1
.n
IR = 100/LA.
10Hz"; f,,; 10kHz
120
/LV
IR = 100 /LA.
T = 1000 Hr.
TA = 25'C ±0.1·C
20
ppm
IR = 100/LA
X Suffix
Y Suffix
30
50
30
50
150
All Others
ppmrC
150
150
ppmrC
ppmrC
(Max)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics.
The guaranteed speCifications apply only for the test conditions listed.
Nole 2: Refer to RETSI8SH-2.S for military specifications.
Note 3: For elevated temperature operation, TJ MAX is:
LM18S
LM28S
LM38S
ISO'C
12S'C
100'C
Thermal Resistance
OJ_ (Junction to Ambient)
OJ_ (Junction to Case)
TO-92
TO-46
SO-8
180'C/W (0.4" Leads) 440'C/W 16S'C/W
17O'C/W (0.12S" Leads)
N/A
80'C/W
N/A
Nole 4: Parameters identified with boldface type apply at temperature extremes. All other numbers apply at TA
Nole 5: Guaranteed and 100% production tested.
~
TJ
~
2S'C.
Note 6: Guaranteed, but not 100% production tested. These limits are not used to calculate average outgoing quality levels.
Note 7: The average temperature coefficient is defined as the maximum deviation of reference voltage at all measured temperatures between the operating TMAX
and TMIN, divided by TMAX-TMIN. The measured temperatures are -SS'C, -40'C, O'C, 2S'C, 70'C. 85'C, 12S'C.
7-71
(1)
U,
20
Minimum Operating
r
:s:
N
N
Current
Voltage Change with
Current
Units
(Limit)
U1
Design
2.462
2.536
U,
U1
I
N
U,
Typical Performance Characteristics
Reverse Characteristics
100
Reverse Characteristics
16
"-".
~
w
TA=-55°C
i
12
"'"~
..'"
'">
'"
0.5
1.0
1.5
2.0
2.5
:ltn i l
-4
0.01
1000
In'" 100pA
'"
2.410
~
2.460
10
100
100
~
Htttlfllll--ttttltllt---ttttffi!t-H-t-HlW
10
H'mdtlll--I:;
0.1
10
10
10
f-+t-ltt1Ilft-+
'"
~
BOO
100
lk
10k
FREQUENCY (Hz)
100k
1M
t-1.0
t--t--
OUTPUT
~f
t--
OUl1n
r-- r--~
~
A
>
1\
10
J
10
10k
~J
I
2.0
'"
I
lk
Response Time
2
i
100
3.0
120 r-TTTmmr--rrTTnm---rTTTTTT11
100
400
V
V
L
FREQUENCY (HI)
Filtered Output Noise
I:~ "'0~~l
~
V
L
100
~ 600
200
100
~
;;
REVERSE CURRENT (rnA)
1000
~
""c
0.1
0.01
Noise Voltage
~
lk
~
65 85 105 125
100
TA"25°C
'R::: 100pA
§
~
TEMPERATURE (CCl
1200
10
10k
0.1
1400
1
~
~
5 25 45
0.1
Reverse Dynamic
Impedance
n-rn1l1lr-rrmmr-nnm,,--rnmm
~
2.450
-55 -35 -15
0.01
FORWARD CURRENT 1m AI
;5
r-r-.
~2.480
~
0.1
f'" 25 Hz
~
2.490
O.4H+ttttlt--tI;lottIllf--t-tHtttH-tH1tttI
Reverse Dynamic
Impedance
~2,SI0
~
I
REVERSE CURRENT ImAI
2.530
V ....
H+ttffitT-+[lliil!-'fffl:lilf-Jititltll
5
Temperature Drift
~ 2.500
O.B
c
~
3.0
H+ttttlt-+H-ttlHII-+t1ftti11H-tHittit
'"
\
REVERSE VOLTAGE IVI
2.520
~
>
0.1
1.2
w
'"~
~
w
!
~
2
I~A;i~d~l~
'""
"
~
10
Forward Characteristics
1.6 rTTTT111Ir..,.,,,,,,,,rnmnrTTfln111
I~~"I,W~~~
;;
lOOk
100
!k
10k
CUTOFF FREQUENCY IHd
lOOk
J INPUT
J
200
TIME
400
600
(/ls)
TL/H/5519-3
7-72
r
3:
.....
LM385-2.5 Applications
.
CO
U'I
Micropower' 10V Reference
Micropower' 5V Regulator
-
N
U,
10
10
.......
r
3:
. - - - -......---VIN::: 15V
r:~-----~p---------"'---'VIN;;'5.ZV
.
N
CO
U'I
N
> .....t---1~10V
. -_ _..._
..._Vo = 5V
ISO pF
1.SM
U,
.......
r
3:
w
CO
IL" 100mA
U'I
N
u,
SOOk
LMJ85·Z.5
10M
lOOk
Zk
TLlH/5519-10
'10 '" 30 ~ standby currant
'10" 40 ~A
TL/H/5519-9
Precision 1 /LA to 1 mA Current Sources
LMJ85·Z.5
LM38S·2.S
Cl
150 pF
-l.SV TO -21V --....;--4~--__I-y.\III....I
l.SV TO 21V - - - - -...----...J\N'Ir-.....
-JOV
TL/H/5519-4
METER THERMOMETERS
O·C-1 OO·C Thermometer
O·F-50·F Thermometer
lk
lk
R4
R4
100
220
TL/H/5519-5
Calibration
Calibration
1. Short LM3B5-2.5. adju.l R3 for IOUT= lemp all ~AI'K
1. Short LM3B5-2.5. adjust R3 for IOUT=tamp at I.B ~I'K
2. Remove short, adjust R2 for correct reading in centigrade
2. Remove short, adjust R2 for correct reading in OF
7-73
•
.
~ .-------------------------------------------------------------------------------~
N
~
co
('I)
::!!
LM385-2.5 Applications (Continued)
Micropower Thermocouple Cold Junction Compensator
..J
....
~
~
~
~
::!!
....
..J
.
Adjustment Procedure
20
1%
Ilk
1. Adjust TC ADJ pot until voltage across Rl equals Kelvin temperature
multiplied by the thermocouple Seebeck coefficient
1M
1%
3V
2. Adjust zero ADJ pot until voltage across R2 equals the thermocouple
Seebeck coefficient multiplied by 273.2.
TCAOJ
500
+
LITHIUM
~
N
~
co
::!!
....
..J
+
THERMOCOUPLE
+
METER
\_,
COLD JUNCTION
ISOTHERMAL
WITH LMl14
TLlH15519-6
Thermocouple
Type
Seebeck
Co·
efficient
R1
(n)
R2
(n)
523
432
412
63.4
1.24k
1k
953n
150n
(p.vrc)
J
T
K
S
52.3
42.8
40.8
6.4
Voltage
Across R1
@25°C
(mV)
15.60
12.77
12.17
1.908
Voltage
AcrossR2
(my)
Improving Regulation of Adjustable
Regulators
14.32
11.78
11.17
1.766
Typical supply current 50 p.A
TLlH15519-7
Schematic Diagram
TLIH15519-1
7-74
,------------------------------------------------------------------------, r
s::
.....
OCt
~National
~ Semiconductor
c.n
.......
LM 185/LM285/LM385
Adjustable Micropower Voltage References
c.n
.......
r
s::
N
OCt
r
s::
Co)
OCt
c.n
General Description
alog circuitry with battery life approaching shelf life. Further,
the wide operating current allows it to replace older references with a tighter tolerance part.
The LM185 is rated for operation over a -55'C to 125'C
temperature range, while the LM285 is rated -40'C to 85'C
and the LM385 O'C to 70'C. The LM185 is available in a
hermetic TO-46 package and the LM285/LM385 are available in a low-cost TO-92 molded package, as well as S.O.
The LM185/LM285/LM385 are micropower 3·terminal adjustable band-gap voltage reference diodes. Operating from
1.24 to 5.3V and over a 10 /LA to 20 mA current range, they
feature exceptionally low dynamic impedance and good
temperature stability. On-chip trimming is used to provide
tight voltage tolerance. Since the LM185 band-gap reference uses only transistors and resistors, low noise and
good long-term stability result.
Careful design of the LM185 has made the device tolerant
of capacitive loading, making it easy to use in almost any
reference application. The wide dynamic operating range
allows its use with widely varying supplies with excellent
regulation.
Features
Adjustable from 1.24V to 5.30V
Operating current of 10 /LA to 20 mA
III 1% and 2% initial tolerance
III 1 n dynamic impedance
II Low temperature coefficient
III
III
The extremely low power drain of the LM185 makes it useful
for micropower circuitry. This voltage reference can be used
to make portable meters, regulators or general purpose an-
Connection Diagrams
TO-92
Plastic Package
TO-46
Metal Can Package
SO Package
+
NC
NC
ADJ
8
TLIH/5250-9
TL/H/5250-1
Bottom View
Order Number LM285BXZ,
LM285BYZ, LM285Z, LM385BXZ,
LM385BYZ or LM385Z
See NS Package Number Z03A
Bottom View
Order Number LM185BH,
LM185BXH or LM185BYH
See NS Package Number H03A
3
NC
4
TLiH/5250-10
Order Number LM285M or LM385M
See NS Package Number M08A
Block Diagram
Typical Applications
1.2V Reference
5.0V Reference
9V
9V
H1 VOUT= 1.24
50k
H1
500k
(~+ 1)
5V
+
.....--1.2V
H2
120k
H3
364k
Tl/H/5250-13
TLiH/5250-14
7-75
-=-
TLiH/5250-2
II
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
(Note 2)
Reverse Current
30mA
Forward Current
Operating Temperature Range (Note 3)
LM185 Series
LM285 Series
LM385 Series
Storage Temperature
Soldering Information
260·C
TO-92 Package (10 sec.)
TO-46 Package (10 sec.)
300·C
SO Package
215·C
Vapor Phase (60 sec.)
220·C
Infrared (15 sec.)
See An-450 "Surface Mounting Methods and Their Effect
on Product Reliability" for other methods of soldering surface mount devices.
10mA
- 55·C to 125·C
-40·C to 85·C
O·Cto 700C
- 55·C to 150·C
Electrical Characteristics (Note 4)
LM385
LM185, LM285
Parameter
Reference Voltage
Conditions
IR ~ 100,.A
Typ
1.240
LM185BX, LM185BV
LM185B, LM285BX,
LM28SBV
LM385BX,
LM385BV
LM285
LM385
Typ
Tested
Limit
(NoteS)
Design Tested Design
Limit
Limit
Limit
(NoteS) (Note 5) (NoteS)
1.252
1.265
1.270 1.240 1.252
1.255
1.265
1.270
Tested Design Tested Design
Limit
Limit
Limit
Limit
(Note 5) (NoteS) (NoteS) (NoteS)
1.215
1.205
1.228
1.215
1.215
1.205
1
10
1.5
20
1
15
1.5
25
1
15
1.5
25
1.255
1.228
1.215
Reference Voltage
IMIN < IR < 1 mA
Change with Current 1 mA < IR < 20 mA
0.2
4
Dynamic Output
Impedance
IR ~ 100 ,.A, f ~ 100 Hz
lAC ~ 0.1 IR VOUT ~ VREF
VOUT ~ 5.3V
Reference Voltage
Change with Output
Voltage
IR ~ 100,.A
Feedback Current
Minimum Operating
Current (see curve)
VOUT ~ VREF
VOUT ~ 5.3V
Output Wideband
Noise
IR ~ 100,.A,10Hz
VOUT ~ VREF
VOUT ~ 5.3V
1.5
20
0.3
0.7
0.2
5
V
(max)
V
(min)
mV
(max)
n
0.4
1
1
3
6
3
6
2
5
10
5
10
mV
(max)
13
20
25
20
25
16
30
35
30
35
nA(max)
6
30
9
10
50
9
10
50
7
35
11
55
13
60
11
55
13
60
,.A
(max)
45
45
< f < 10kHz
50
170
IR ~ 100 ,.A, T ~ 1000 Hr,
TA ~ 25·C ± O.I·C
p.Vrms
50
170
30
50
Average Temperature IR ~ 100,.A X Suffix
Coefficient (Note 7)
Y Suffix
All Others
Long Term Stability
1
10
Unlls
(Limit)
30
50
30
50
150
150
20
30
50
150
20
ppml"c
(max)
150
ppm
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions. see the Electrical Characteristics.
The guaranteed specifications apply only for the test conditions listed.
Note 2: Refer to RETSI B5H for military specHications.
Note 3: For elevated lemperature operation, Tj max is:
LM1B5
150"C
LM2B5
125"C
LM3B5
100"C
Thermal Resistance
OJ, (Junction to Ambient)
O·c (Junction to Case)
TO-92
TO-46
SO-8
1BO"C/W (0.4" leads) 440"C/W 165"C/W
170"C/W (0.125" leads)
N/A
BO"C/W
Note 4: Parameters identified with boldface type apply at temperature extremes. All other numbers apply at TA
parameters apply for VREF < VOUT < 5.3V.
~
TJ
~
N/A
25"C. Unless otherwise specified, all
Note 5: Guaranteed and 100% production tested.
Note 6: Guaranteed, but not 100% production tested. These limits are nol to be used to calculate average outgoing quality levels.
Note 7: The average temperature coefficient is defined as the maximum deviation of reference voltage at all measured temperatures from T min to T max. divided by
Tmax - Tmin. The measured temperatures are -55, -40,0,25, 70, 85, 125"C.
7-76
.---------------------------------------------------------------------------------, r:s:::
.....
Typical Performance Characteristics
QC)
en
.....
r-
Temperature Drift of 3
Representative Units
1.260
1~-lbopL
e: 1.250
!Ii! 1.240
~
Feedback Current
25
"'"
,,-
r-
i!l
Poi 1.230
....
~
1.220
....
5
=15
~ 10
I
L~:~;; .,.---
10
'"
B40
iii
10
-50 -25 0 25 50 75 100 125
TEMPERATURE (OC)
Reverse Characteristics
I
~OU~=~
~ 30
!!
z 20
I
o
N
QC)
l60
ffi 50
II
o
100
WORST
en
.....
r-
70
VOlT=lREF
-r
co
.....
:s:::
~
:::0
.....
·55·35·15 & 25 45 65 85105125
TEMPERATURE (OC)
l~
IR~IDDI,.A
1 20
Minimum Operating Current
aD
:s:::
(0)
QC)
en
I'".......WORST
fI"/ CASELMI85
lj
~
~~
--
1·
2
TYP@25°C
4
5
OUTPUT VOLTAGE (V)
Forward Characteristics
Reverse Characteristics
1.2
r-rmmnr-r"ITII1IM1'T
VOUT=VREF
10 ~~-+--t-~-+--flr~
...~
I
-2
0.2 0.4 0.6 0.8 1.0 1.2 1.4
REVERSE VOLTAGE (V)
0.01
Output Noise Voltage
1,.000
0.1
1
10
REVERSE CURRENT (mA)
0.1
1
10
FORWARD CURRENT (mA)
100
Response Time
Dynamic Output Impedance
100
IR-loo,.A
I
VOUT=VRE~
OUTPUT
~
'" 1.000
i....
i
I
I!'!"_+_.......;,;;~
I
§-
"* . OUTPUT
I
,...
LM
...
100
10
0.1
10~~~~~~m-~~
10
100
lk
10k
FREQUENCY (Hz)
L..1..~~J..LUIIIL...1~WL...JUJ.U1III
10
lOOk
100
It
10k
FREQUENCY (Hz)
100
'INPUT
o
lOOk
50
I-I--
t-I--
"-
I
100 150
TIME(",)
200
TL/H/5250-3
LM285
Temperature CoeffiCient Typical
LM185
Temperature Coefficient Typical
-&
o
..
E
..~-------,
LM385
Temperature Coefficient Typical
i
o~----~
(1.24)
-a. =e
o 0 c;;;;;o-..-;;;::---,
toy
-5
-5
II
5000 -0.5
7000
-10~~--~~--~~~
-55 -25
0.035
0.0028
I!J
0 +25
+70+85 +125
TEMPERATURE (OC)
mVI"C
-55-40
mV/oC
0 +25
+70+85 +125
TEMPERATURE (OC)
0.025
"It/°C ---i---..L.-%/oc _
0.002
ppm/DC
ppm/oC~ TEMPCO =
TOTA~i I~/pm
7000
QI_~-1° 0
+25
+70
~oC~O,032
"It/°C----O.0026
ppm/oc-IJ!] TEMPCO
j.Y
= toT
TUH/5250-4
7·77
Typical Applications (Continued)
Precision 10V Reference
Low AC Noise Reference
ISY
ISY
HI
SK
HI
lOOK
...-_"""1I....
~~~T
H2
301K
H2
120k
1%
+ C2
H3
68.1K
10pF
1%
R3
360 kU
25V Low Current Shunt Regulator
200 mA Shunt Regulator
Y+
H3
V+
H4
100pA-12V
LED DN
-5V
-5V
Fast Positive Clamp
2.4V + aV01
Bidirectional Clamp
±2.4V
AI
VOUT
A2
01
IN914
02
IN914
A3
24DK
A4
240K
Bidirectional Adjustable Clamp
±1.8Vto ±2.4V
Bidirectional Adjustable Clamp
±2.4Vto ±6V
AI
II
TL/H/5250-6
7-79
Typical Applications
-
(Continued)
Simple Floating Current Detector
Current Source
OT020mA
+15V
+5V
81
81
3900
±2%
lN4002
02
R2
470k
Dl'
N.C.
":"
I
1.24V
1 ".A < lOUT < 100 rnA
10UT=~
81
-..!I!L
THRESHOLO-Iit"'+ 4N28 GAIN
Precision Floating Current Detector
-
OT020mA
+5V
Rl
3320
±1%
02
1.4002
R3
lOOk
Dl'
N.C.
ITHRESHOLD= 1.::V =3.7mA±2%
TUH/5250-7
, 01 can be any LED, VF = I.SV to 2.2V at 3 rnA. 01 may acl as an
Indicator. 01 will be on If ITHRESHOLD falls below the threshold current,
except with 1=0.
7-80
Typical Applications (Continued)
Centigrade Thermometer, 10 mVI'C
Freezer Alarm
r-------....-9V
TEMP
SENSOR
Rl
R5
10k
50k
rL
4.5V .;;,
r-I
I
I
I
TEMP
L!~~R
TL/H/5250-11
BEEPS AT TEMPERATURES ABOVE THAT SET
BY Rl (RANGE IS - 3DoF to + 12DoFI
TL/H/5250-12
Schematic Diagram
R6
2DDk
REFERENCE
R7
5Dk
R8
3DDk
FEEDBACK
(FBI
TL/H/5250-B
II
7-81
en
en
en
C')
:E
..J
......
en
en
C')
:E
..J
......
en
en
N
:E
..J
......
en
en
.,...
:E
..J
~National
~ Semiconductor
LM 199/LM299/LM399/LM3999 Precision Reference
General Description
The LM199 series are precision, temperature-stabilized
monolithic zeners offering temperature coefficients a factor
of ten better than high quality reference zeners. Constructed on a single monolithic chip is a temperature stabilizer
circuit and an active reference zener. The active circuitry
reduces the dynamic impedance of the zener to about 0.5!l
and allows the zener to operate over 0.5 mA to 10 mA current range with essentially no change in voltage or temperature coefficient. Further, a new subsurface zener structure
gives low noise and excellent long term stability compared
to ordinary monolithic zeners. The package is supplied with
a thermal shield to minimize heater power and improve temperature regulation.
The LM199 series references are exceptionally easy to use
and free of the problems that are often experienced with
ordinary zeners. There is virtually no hysteresis in reference
voltage with temperature cycling. Also, the LM199 is free of
voltage shifts due to stress on the leads. Finally, since the
unit is temperature stabilized, warm up time is fast.
The LM199 can be used in almost any application in place
of ordinary zeners with improved performance. Some ideal
applications are analog to digital converters, calibration
standards, precision voltage or current sources or precision
power supplies. Further in many cases the LM199 can replace references in existing equipment with a minimum of
wiring changes.
Connection Diagrams
The LM199 series devices are packaged in a standard hermetic TO-46 package inside a thermal shield. The LM199 is
rated for operation from - 55°C to + 125°C while the LM299
is rated for operation from - 25°C to + B5°C and the LM399
is rated from O°C to + 70°C.
The LM3999 is packaged in a standard TO-92 package and
is rated from O°C to + 70°C
Features
•
•
•
•
•
•
•
•
•
•
rc
Guaranteed 0.0001 %
temperature coefficient
Low dynamic impedance - 0.5!l
Initial tolerance on breakdown voltage - 2%
Sharp breakdown at 400 /LA
Wide operating current - 500 /LA to 10 mA
Wide supply range for temperature stabilizer
Guaranteed low noise
Low power for stabilization - 300 mW at 25°C
Long term stability - 20 ppm
Proven reliability, low-stress packaging in TO-46 integrated-circuit hermetic package, for low hysteresis after
thermal cycling. 33 million hours MTBF at TA = + 25°C
(TJ = +86°C)
• Certified long term stability available
Functional Block Diagrams
LM 199/LM299/LM399
Metal Can Package
+
TLIH/S717-14
Top View
LM199/LM299/LM399 (See Table on fourth page)
NS Package Number H04D
TLlH/S717-1S
LM3999
Plastic Package TO-92
~
o
TL/H/S717-1D
Bottom View
LM3999 (See Table on fourth page)
NS Package Number Z03A
TLlH/S717 -11
7-82
Absolute Maximum Ratings
Specifications for MilitaryI Aerospace products are not
contained in this datasheet. Refer to the following Reliability Electrical Test Specifications documents:
RETS199X for LM199, RETS199AX for LMI99A.
Temperature Stabilizer Voltage
LM199/LM299/LM399
LM3999
40V
36V
Reverse Breakdown Current
20mA
Forward Current
LM199/LM299/LM399
LM3999
Parameter
-55'C to + 125'C
-25'Cto +85'C
-O'Cto +70'C
Storage Temperature Range
- 55'C to + 150'C
+ 260'C
+300'C
(Note 2)
0.5mA';; IR';; 10mA
Reverse Breakdown Voltage
Change with Current
0.5 mA ,;; IR ,;; 10 mA
Reverse Dynamic Impedance
IR = 1 mA
-55'C';;TA';;+85'C}
+ 85'C,;;TA';; + 125'C
-25'C';;TA';;85'C
O'C';;TA';;+70'C
LM399
LM199/LM299
Conditions
Reverse Breakdown Voltage
Reverse Breakdown
Temperature Coefficient
Operating Temperature Range
LM199
LM299
LM399/LM3999
Soldering Information
TO-92 package (10 sec.)
TO-46 package (10 sec.)
1 mA
-0.1 mA
Electrical Characteristics
40V
-0.1V
Reference to Substrate Voltage V(RS) (Note 1)
Typ
Max
Min
Typ
Max
6.8
6.95
7.1
6.6
6.95
7.3
V
6
9
6
12
mV
0.5
1
0.5
1.5
n
0.00003
0.0005
0.00003
0.0001
0.0015
0.0001
0.00003
0.0002
%rC
%rC
%rC
%rC
7
50
",V
LM199
LM299
LM399
RMS Noise
10Hz';; f ,;; 10kHz
7
Long Term Stability
Stabilized, 22'C,;; T A';; 28'C,
1000 Hours, IR = 1 mA ± 0.1 %
20
Temperature Stabilizer
Supply Current
TA=25'C, Still Air, Vs=30V
TA = - 55'C
8.5
22
Temperature Stabilizer
Supply Voltage
Vs = 30V, TA = 25'C
Initial Turn-on Current
9,;; VS';; 40, TA= + 25'C, (Note 3)
20
14
28
8.5
15
9
3
140
ppm
20
40
9
Warm-Up Time to 0.05%
Units
Min
40
3
V
sec.
140
200
mA
mA
200
Electrical Characteristics (Note 2)
Parameter
LM3999
Conditions
Reverse Breakdown Voltage
0.6 mA ,;; IR ,;; 10 mA
Reverse Breakdown Voltage
Change with Current
0.6 mA ,;; IR ,;; 10 mA
Reverse Dynamic Impedance
IR = 1 mA
Reverse Breakdown
Temperature Coefficient
O'C,;; TA';; 70'C
Units
Min
Typ
Max
6.6
6.95
7.3
V
6
20
mV
0.6
2.2
n
0.0002
0.0005
%rC
RMSNoise
10 Hz ,;; f ,;; 10 kHz
7
",V
Long Term Stability
Stabilized, 22'C ,;; T A ,;; 28'C,
1000 Hours, IR = 1 mA ±0.1 %
20
ppm
Temperature Stabilizer
T A = 25'C, Still Air, Vs = 30V
12
Temperature Stabilizer
Supply Voltage
Warm-Up Time to 0.05%
Vs = 30V, TA = 25'C
Initial Turn-On Current
9 ,;; Vs ,;; 40, T A = 25'C
18
mA
36
V
5
7-83
140
sec.
200
mA
Electrical Characteristics (Note 2)
Parameter
Reverse Breakdown Voltage
0.5 mA :5: IR :5: 10 mA
Reverse Breakdown Voltage
Change with Current
0.5mA:5: IR:5: 10mA
Reverse Dynamic Impedance
IR = 1 mA
Reverse Breakdown
Temperature Coefficient
LM199A, LM299A
Conditions
-55°C:5:TA:5:+85°C}
+85°C:5:TA:5:+125°C
-25°C:5:TA:5:85°C
0°C:5:TA:5:+70°C
Max
Min
Typ
Max
6.8
6.95
7.1
6.6
6.95
7.3
V
6
9
6
12
mV
0.5
1
0.5
1.5
LM299A
LM399A
0.00002
0.0005
0.00002
0.00005
0.0010
0.00005
20
RMSNoise
10Hz:5:f:5: 10kHz
7
Long Term Stability
Stabilized,22°C:5:TA:5:28°C,
1000 Hours,IR=1 mA±0.1%
20
Temperature Stabilizer
Supply Current
TA=25°C, Still Air, Vs=30V
TA =- 55°C
8.5
22
14
28
Vs = 30V, TA = 25°C
Initial Turn-on Current
9:5:Vs:5:40, TA= + 25°C, (Note 3)
0.00003
0.0001
%I"C
%I"C
%I"C
7
50
",V
8.5
40
ppm
15
3
200
Conditions
Reverse Breakdown Voltage
0.5 mA:5:IR:5:10 mA
Reverse Breakdown Voltage
Change With Current
0.5 mA:5:IR:5:10 mA
Reverse Dynamic Impedance
IR = 1 mA
Reverse Breakdown
Temperature Coefficient
-55°C:5:TA:5:85° }
85°C:5:TA:5:125°C
-25°C:5:TA:5:85°C
0°C:5:TA:5:70°C
V
sec.
140
200
Electrical Characteristics (Note 2)
Parameter
mA
40
9
3
140
11
%/oC
20
9
Warm-Up Time to 0.05%
Units
Typ
LM199A
Temperature Stabilizer
Supply Voltage
LM399A
Min
mA
-
LM199AH-20, LM299AH-20
LM399AH-50
Units
Min
Typ
Max
Min
Typ
Max
6.8
6.95
7.1
6.6
6.95
7.3
V
6
9
6
12
mV
0.5
1.5
11
0.5
1
0.00002
0.0005
0.00002
0.00005
0.0010
0.00005
0.00003
0.0001
%I"C
%I"C
%I"C
%I"C
RMS Noise
10 Hz:5:f:5:10 kHz
7
20
7
50
",V
Long Term Stability
Stabilized,22°C:5:TA:5:28°C,
1000 Hours, IR= 1 mA±0.1 %
8
20
9
50
ppm
Temperature Stabilizer
Supply Current
TA=25°C, Still Air, Vs=30V
TA=55°C
8.5
22
14
28
8.5
15
LM199A
LM299A
LM399A
Temperature Stabilizer
Supply Voltage
40
9
Warm-Up Time to 0.05%
Vs=30V, TA = 25°C
Initial Turn-on Current
9:5:Vs:5:40, TA = 25°C, (Note 3)
3
140
9
40
V
200
mA
3
200
140
mA
s
Nole 1: The substrate is electrically connected to the negative terminal of the temperature stabilizer. The voltage that can be applied to either terminal of the
reference is 40V more positive or 0.1 V more negative than the substrate.
Nole 2: These specHications apply for 30V applied to the temperature stabilizer and - 55'C';;TA';; + 125'C for the LM199; - 25'C';;TA';; + 85'C for the LM299 and
O'C,;;TA';; +70'C for the LM399 and LM3999.
Note 3: This initial current can be reduced by adding an appropriate resistor and capaCitor to the heater circuit. See the performance characteristic graphs to
detennine values.
Note 4: Do not wash the LM199 with its polysulfone thermal shield in TCE.
7-84
r-
3:
.....
Ordering Information
Initial
Tolerance
Q'Cto +7Q'C
CD
- 25"C to + 85'C
2%
5%
LM399H
LM399AH
5%
LM3999Z
Guaranteed Long
Term Stability
-55'C to + 125"C
NS
Package
LM299AH
LM199AH
H04D
LM299H
LM199H
H04D
CD
......
r3:
N
CD
~
~
Co)
Z03A
LM399AH-50
LM299AH-20
LM199AH-20
H04D
CD
CD
......
r3:
Co)
CD
CD
CD
Certified Long Term Drift
The National Semiconductor LM199AH-20, LM299AH-20,
and LM399AH-50 are ultra-stable Zener references specialIy selected from the production runs of LM199AH,
LM299AH, LM399AH and tested to confirm a long-term stability of 20, 20, or 50 ppm per 1000 hours, respectively. The
devices are measured every 168 hours and the voltage of
each device is logged and compared in such a way as to
show the deviation from its initial value. Each measurement
is taken with a probable-worst-case deviation of ± 2 ppm,
compared to the Reference Voltage, which is derived from
several groups of NBS-traceable references such as
LM199AH-20's, 1N827's, and saturated standard cells, so
that the deviation of anyone group will not cause false indications. Indeed, this comparison process has recently been
automated using a specially prepared computer program
which is custom-designed to reject noisy data (and require a
repeat reading) and to record the average of the best 5 of 7
readings, just as a sagacious standards engineer will reject
unbelievable readings.
The typical characteristic for the LM199AH-20 is shown below. This computerized print-out form of each reference's
stability is shipped with the unit.
Typical Characteristics
National Semiconductor
Certified Long Term Drift
Hrs
Drift
168
336
504
672
840
1008
-20
-24
-36
-34
-40
-36
LM199AH-20
Part #6849
Limits
LM199AH-20 140 p.V
LM299AH-20 140 p.V
LM399AH-20 350 p.V
Testing Conditions
Heater Voltage
30V
Zener Current
1 mA
Ambient Temp.
25'C
120
D
R
80
F
40
I
T
pV
----..
0
-40
F--
-813
-120
0
168
336
504 672
HOURS
8413 113138
TL/H/5717-12
•
7-85
Typical Performance Characteristics
Dynamic Impedance
Reverse Voltage Change
Reverse Characteristics
100
5....
Z
'"
~
'"z
u
10-4
~
'"
,..
~
H
~ :::::
u
>
/f
1.0
TJ=25"~
~
V·)1f.ABllI~EDI
IT, 090 C)
10"
6.25
6.65
6.05
1.05
10
10
REVERSE VOLTAGE IV)
Zener Noise Voltage
~
Heater Current
00
S
1\
.5
~
0
~
100
TJ=n c
-2
lk
10k
~
'"~
~
.
12
16
TA
140
200
...... 1"'-
;;-
120
....
100
.5
i
150
I"'- .......
100
~
~
50
20
-55 -35 -IS
-55 -35 -15 5
::
:--~,
25 C
S
800
'"
700
::i
600
;;
400
In
I I
'";:::2'"
VI
:::;
w
~'ttl~
Ir
60
40
o
25 45 65 85 105 125
2 4
65
05
105
'"
'"
500
300
;0
0
~
...
:E
x
I
TURN ON TEMPERATURE r'C)
45
Heater Surge Limit Resistor vs
Minimum Supply Voltage at
Various Minimum Temperatures
YV),0JVH '20V_
1----I,CVH '30V
00
25
TEMPERATURE I'C)
Q
20
..... -
o
20
'5V
160
VH 1, 4JV
;:::
i1
8
40
Heater Current (To Limit This
Surge, See Next Graph)
Initial Heater Current
'"
~
~
'"....w
~
HEATER ON TIME -ISEC)
250
w
i
VH
4
FREQUENCY (Hz)
....z
....
I
o
tOOk
60
.5
I
,,
-3
;;-
1~~,-J5C
-4
100
10
.5
I
I
;0
~
--
25 C
=1
I
-1
....
5Q
STAOILIZED IT, 090 C) _
50
;;-
100k
FREQUENCY 1Hz)
Stabilization Time
TA
150
10k
1k
100
REVERSE CURRENT (rnA)
200
~
I
0.1
6.45
/
STABllIZE~
IT, ~90'C)
~
w
10- 3
I
10
z
ti
ill
~
-w
.
10-2
6 8 10 12 14 16 18
200
100
10
TIME (SEC)
20
30
40
MINIMUM SUPPLY VOLTAGE (V)
TL1H/5717-2
'Heater must be bypassed with a 2
or larger tantalum capacitor if re-
p-F
sistors are used.
Response Time
Low Frequency Noise Voltage
OUTPUT
STABILIZED
IT, ', 90 CY-
i!
'"2
0.01
Hl~t$l
~
Hz
'"
~>
IT; ,9Il"C)
':h
".
,
20
10
OU1PUT
-
,--"---
-
INPUT- i - -
100
10
TIME IMINUTES)
l
w
STABILIZED
~T)5C- r--
200
300
400
TIME (1"$)
TLlH/5717-3
TLIH/5717-7
7-86
r-
....iii:
Typical Applications
Single Supply Operation
$......
Split Supply Operation
r-
+ 15V--....- - - - ,
9V '040V---il~---""
iii:
N
CD
'"
TEMPERATURE
STABILIZER
CD
......
r-
iii:
~
TEMPERATURE
STABILIZER
69!iV
CD
......
r-
695V
iii:
Co)
CD
$
-15V
Negative Heater Supply with
Positive Reference
Buffered Reference
With Single Supply
."V--....----....--------,
·"V-------,
'"
Ok
15k
TEMPERATURE
TEMPERATURE
STABILIZER
STABILIZER
695V
IOV
595V
9V TO
"V
Positive Current Source
10VT04DV-....- - - -....- -....- - - - - - - i l r - - - - - . . . ,
350
0.11.
TEMPERATURE
STABILIZER
6!1&V
LM199
4Jk
Standard Cell Replacement
,.
15VT02DV---.-----.--------------,
1% REGULATED
1.511
....--....---, ~~J~~:
"k
lOOk
121
0.1.
TEMPERATURE
STABILIZER
1.95Y
OUTPUT
'Ok
2k
0.'%
TLIH15717-4
7-87
CD
CD
CD
CO)
Typical Applications (Continued)
:is
...I
.....
CD
CD
Negative Current Source
('I)
:is
...I
.....
CD
CD
7.!ik
C'I
:is
...I
.....
CD
....
CD
:is
...I
300
-"v--..........---.....- -...---....----------'
Square Wave Voltage Reference
·l!iV
..
15k
..
SDk
....,N.,...~,...-""',.,..--
10F
~
..;+, . - OUTPUT
Portable Calibrator'
-L
[
Uk
1%
200k
12VTO _
I8V--
laOk
+
IN451
"k
TEMPERATURE
STABILIUR
\%
6.9SV
OTO lOY
INPUT
Jk
SQUARE WAVE
L...+_.....;L:;:M:.:;19;:9_--1I-.JTRIM
·Warm-up time 10 seconds: intermittent operation does not degrade long term stability.
14V Reference
Precision Clamp'
CLAMP
INPUT
R,
TEMPERATURE
STABILIZER
6.9SV
LM199
...- - - - - - + - - O U T P U T
.,SV--+----.,
IN914
\5k
+
+
TEMPERATURE
STABILIZER
TEMPERATURE
STABILIZER
&9!iV
B.9SV
lM19!
lMI99
INgle
'::" 'Clamp will sink 5 rnA when input goes more positive than reference
TLlH/5717-5
7-88
r-
....3:
Typical Applications (Continued)
CD
CD
......
r3:
I\)
OV to 20V Power Reference
>IV TO"V--~t-----4Ir---------------"'-------'
CD
CD
......
r3:
to)
"
TEMPERATURE
STABILIZER
CD
lM195K
CD
......
r-
20k ~.I-"'VVII""'-'V'o,....-t--t
3:
to)
695V
CD
CD
CD
LMI99
-5V
Bipolar Output Reference
50k
+15V---4II-----,
15k
TEMPERATURE
STABILIZER
G9SV
OUTPUT 69V
5"~"'---'
I~V
lMl99
Jhf
15V
TL/H/5717-6
Voltage Reference
TO;:~--""'---""--------------'
1.St
OUTPUT
I.OW
TUH/5717-9
,.
7-89
en
en
en
C")
:E
Schematic Diagrams
..J
Temperature Stabilizer
......
en
en
C')
:E
r-----~--------------_.------------
__----------~3
v·
..J
......
en
en
N
:E
..J
......
en
en
:E
....
..J
02
63V
2k
42
~----------~--~--~~--~~-----t----~----~4
V
TLfH/5717 -01
Reference
03
63V
30 pF
10k
2k
2.6k
30k
~------~--~--------~------------~--~2
7-90
-
TLfH/5717-13
r------------------------------------------------------------------------, r
~National
PRELIMINARY
~ Semiconductor
I
I\)
en
LM368-2.5 Precision Voltage Reference
General Description
Features
The LM368-2.5 is a precision, monolithic, temperature-compensated voltage reference. The LM368-2.5 makes use of
thin-film technology enhanced by the discrete laser trimming of resistors to achieve excellent Temperature coefficient (Tempco) of VOUT (as low as 11 ppmI'C), along with
tight initial tolerance, (as low as 0.02%). The trim scheme is
such that individual resistors are cut open rather than being
trimmed (partially cut), to avoid resistor drift caused by electromigration in the trimmed area. The LM368-2.5 also provides excellent stability vs. changes in input voltage and
output current. The output is short circuit proof. A trim pin is
made available for fine trimming of VOUT or for obtaining
intermediate values without greatly affecting the Tempco of
the device.
• 400 /J-A operating current
• Low output impedance
I!I Excellent line regulation (.0001 %IV typical)
III Single-supply operation
• Externally trimmable
• Low temperature coefficient
• Excellent initial accuracy (0.02% typical)
• Best reference available for low-voltage operation
(Vs = 5V, VREF = 2.500V)
Connection Diagrams
Dual-In-Line Package (N)
or 5.0. Package (M)
Metal Can Package
Ne
y+NCDs NC
NC
2
y-
7
3
6
OUTPUT
4
5
ADJ
3:
Co)
m
CI)
TLIH/6446-15
Top View
Order Number LM36BN-2.5
See NS Package Number NOBE
TL/H/6446-1
Top View
·case connected to VOrder Number LM368H-2.5 LM368YH-2.5
See NS Package Number H08C
Typical Applications
Low Voltage Reference
4.SV-30V
2
TUH/6446-2
7·91
Absolute Maximum Ratings (Note 7)
If Military/Aerospace specified devices are required,
please contact the Natiomil Semiconductor Sales
Office/Distributors for availability and specifications.
Input Voltage
35V
Power Dissipation
Storage Temperature Range
Soldering Information
DIP (N) Package (10 sec.)
TO-5 (H) Package (10 sec.)
+2BO'C
+300'C
See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" (Appendix D) for other methods of
soldering surface mount devices.
BOOmW
-BO'Cto + 150'C
Operating Temperature Range
O'Cto +70'C
Electrical Characteristics (Note 1)
LM368-2.5
Parameter
Conditions
Typical
Tested
Limit
(Note 2)
Design
Limit
(Note 3)
Units
(Max. unless
noted)
±0.02
±0.2
%
Line Regulation
5.0V :5: VIN :5: 30V
±0.0001
±0.0005
%N
Load Regulation (Note B)
o mA :5: ISOURCE :5: 10 mA
±0.0003
±0.0025
%/mA
Thermal Regulation
T
±0.005
±0.02
%/100 mW
VOUT Error: LM36B
= 20 mS (Note 4)
350
550
/LA
Change of Quiescent Current vs. VIN
5.0V :5: VIN :5: 30V
3
5
/LAN
Temperature Coefficient
of Your (see graph): LM3BBY-2.5
(Note 5)
LM3BB-2.5
O'C:5: TA:5: 70'C
O'C:5: TA:5: 70'C
±11
±15
±20
Short Circuit Current
VOUT
=0
30
70
Quiescent Current
Noise:
0.1-10Hz
100 Hz-l0 kHz
±30
ppml'C
ppml'C
100
12
420
1.9-5.2
VOUT Adjust Range
2.2-5.0
o :5: VPIN5 :5: VOUT
Note 1: Unless otherwise noted. these specifications apply: TA ~ 25·C. 4.9V 5: VIN 5: 10.5V, 0 5: ILOAD 5: 0.5 mA, 05: CL 5: 200 pF.
mA
uVp-p
nV/,JHz
Vmin.
Note 2: Tested Limits are guaranteed and 100% tested in production.
Note 3: Design Limits are guaranteed (but not 100% production tested) over the indicated temperature and supply voltage ranges. These limits are not used to
calculate outgoing quality levels.
Note 4: Thermal Regulation is defined as the change in the output Voltage at a time T after a step change in power dissipation of 100 mW.
Note 5: Temperature Coefficient of VOUT is defined as the worst case delta·VOUT measured at Specified Temperatures divided by the total span of the Specified
Temperature Range (See graphs). There is no guarantee that the Specified Temperatures are exactly at the minimum or maximum deviation.
Note 6: In metal can (H), 8J.C is 75·C/W and 8J.A is 150·C/W. In plastic DIP, 8J.A is 160"C/W. In 50·8, 8J.A is 180·C/W, in TO-92, 8J.A is 160·C/W.
Note 7: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its Rated Operating Conditions (see Note 1 and Conditions).
Note 8: Load regulation is measured on the output pin at a point Ya below the base of the package. Regulation is measured at constant junction temperature,
R
using pulse testing with a low duty cycle. Changes in output voltage due to heating effects are covered under the specification for thermal regulation.
7-92
Typical Performance Characteristics (Note 1)
Quiescent Current vs. Input
Voltage and Temperature
Dropout Voltage vs.
Output Current
0.4
0.3
5GG
.,.,.
~-
I
I~200
:::0
.. 300
100
.. .-"...
~ c::;.
125'C
25'C- 1",000
~ ""'"
r-~5!'CI
!
SOURCING
~ -0.1
6 -0.2
-0.3
-0.4
o
10
20
30
INPUT VOLTAGE (V)
40
o
10
4
OUTPUT CURRENT (mA)
Output Impedance vs.
Frequency
100
10
4
OUTPUT CURRENT (mA)
Ripple Rejection vs.
Frequency
I
3, ..!.
§: 10
;;~
~~
I
~
;!
!
0.2
0.1
~
125~ ... -~
i""
-55'C
~
...
~ 25'C
Output Change vs.
Output Current
&i
iil
~
0.1
0.1
.~ L 2
~
~ 4
0.01
~O.OOl
~
!~
i!
0.01
'I
0.0001
10
100
lk
10k
FREOUENCY (Hz)
lOOk
L
10
100
;,-
(1) LM368 as is.
(2) with 0.01 ,.1 Mylar, Trim to Gnd.
3
(3) with 10n in sertes with to ,.1,
VOUTto Gnd.
4 ...
(4) with Both.
'""
lk
10k lOOk
FREOUENCY (Hz)
1M
Output Noise vs.
Frequency
Temperature Coefficient:
LM368·2.5 (Curve A)
i:...
~
~
;"
2.500V
§!
...
~
co
~
I
1
1_-
-1
Nl~J
___ 1
;"-70
--+'I
;'
0
-2
I
-55 -40
0 25
-
70 85
TEMPERATURE ('C)
......
o
125
10
100
lk
FREOUENCY (Hz)
10k
TLlH/8446-3
Typical Temperature Coefficient Calculations:
LM388·2.5 (see Curve A)
T.C.=1.7 mv/(70"x2.5V)
=9.7 ppml"C
,.
7-93
an
c"j
cb
Typical Applications
(I)
C')
::!!
....I
Narrow Range Trimmable Regulator (± 1% min.)
Wide Range Trimmable Regulator
..,.!....-.. .
r ......
-VOUT
5
2M
L........J~II'\r-t~20k
Tl/H/B446-5
Tl/H/B446-6
Improved Noise Performance
r .....;;..."1.!.---....
VOUT
to ~F
TUH/B446-7
± 2.5V, ± 1.25V References
1.250V
-1.25OV
t>
R~
~
y.. LM324A or
% LM358A
Tl/H/B446-B
Thin Rim Resistor Network,
±0.05% Matching and 5 ppm Tracking
(Beckman 694-3-R-tOK-A),
(Caddock T-9t 4-1 OK-l 00-05)
or similar.
7-94
Typical Applications
(Continued)
Multiple Output Voltages
Y+
Y+
_---""I..!~ 5.000Y
5.000Y
r-&.;;.ij!.-~~--
r'-'--1!-J---I--~--
2.500V
Uk
2.500Y
TL/H/8446-9
TUH/8446-10
R = Thin Film Resistor Network
0.05% Matching and 5 ppm Tracking
(Beckman 694·3·R·10K·A).
(Caddock T·914·10K·l00-OS)
or similar.
Reference with Booster
100 mA Boosted Reference
Y+;;:5.OV
Y+;'5.5Y
100-200
lW
r ........il.!.-~~----....~ (OPIIONAL
~ PRE·LOAD)
------"
1.+
YOUT
~ 2.S00V
r---t!-~~----~ VOUT ~
50p.F
2.500V
TLlH/8446-11
TL/H/8446-12
,.
7-95
U)
~
co
r-------------------------------------------------------------------------------------,
Typical Applications (Continued)
CD
C")
:::iii
~
Buffered High-Current Reference with Filter
+5.0V
10k
10k
3.3
L---+-lI---~~--~~VDUT"2.500v
Uk
TL/H/B446-13
Simplified Schematic Diagram
r-----------------.--~-V+
zo
-t--4~VOUT
18k
1.5k
15k
50k
5pF
50k
I - -......W_TRIM
55k
~-----~--~-~--~--~---~---V'Reg. U.S. Pat. Off.
7-96
TL/H/B446-14
Section 8
Surface Mount
•
Section 8 Contents
Surface Mount . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-4S0 Small Outline (SO) Package Surface Mounting Methods-Parameters and Their Effect
on Product Reliability .............................................................
8-2
8-3
8-13
en
-...
c
~NatiOnal
I I)
n
Semiconductor
CD
ii!!i:
o
c
~
Surface Mount
Cost pressures today are forcing many electronics manufacturers to automate their production lines. Surface mount
technology plays a key role in this cost-savings trend because:
SURFACE MOUNT PACKAGING AT NATIONAL
To help our customers take advantage of this new technology, National has developed a line of surface mount packages. Ranging in lead counts from 3 to 360, the package
offerings are summarized in Table I.
1. The mounting of devices on the PC board surface eliminates the expense of drilling holes;
Lead center spacing keeps shrinking with each new generation of surface mount package. Traditional packages (e.g.,
OIPs) have a 100 mil lead center spacing. Surface mount
packages currently in production (e.g., SOT, SOIC, PCC,
LCC, LOCC) have a 50 mil lead center spacing. Surface
mount packages in production release (e.g., PQFP) have a
25 mil lead center spacing. Surface mount packages in development (e.g., TAPEPAK®) will have a lead center spacing of only 12-20 mils.
2. The use of pick-and-place machines to assemble the PC
boards greatly reduces labor costs;
3. The lighter and more compact assembled products resuiting from the smaller dimensions of surface mount
packages mean lower material costs.
Production processes now permit both surface mount and
insertion mount components to be assembled on the same
PC board.
TABLE I. Surface Mount Packages from National
Package
Type
Package
Material
Small Outline
Transistor
(SOT)
Small Outline
IC(SOIC)
'U: ~
Plastic Chip
Carrier (PCC)
~
~
Plastic Quad
Flat Pack
(PQFP)
Q
TAPEPAK®
(TP)
Leadless Chip Leaded Chip
Carrier (LCC) Carrier
(LOCC)
[tjJ 0
,l I!II1! !IIII!II !II III II 11HHHHHHHl I
~i]
Plastic
Plastic
Plastic
Plastic
Plastic
Ceramic
Ceramic
Gull Wing
Gull Wing
J-Bend
Gull Wing
Gull Wing
-
Gull Wing
Lead Center
Spacing
50 Mils
50 Mils
50 Mils
25 Mils
20,15,12 Mils
50 Mils
50 Mils
Tape & Reel
Option
Yes
Yes
Yes
tbd
tbd
No
No
Lead Bend
Lead Counts SOT-23
High Profile
SOT-23
Low Profile
SO-8(*)
SO-14(0)
PCC-20(*)
PCC-28(0)
SO-14 Wide(O)
SO-16(*)
SO-16Wide(0)
SO-20(*)
SO-24(0)
PCC-44(0)
PCC-68
PCC-84
PCC-124
PQFP-84
PQFP-100
PQFP-132
PQFP-196(*)
PQFP-244
'In production (or planned) for linear products.
8-3
TP-40 (0)
TP-68
TP-84
TP-132
TP-172
TP-220
TP-284
TP-360
LCC-18
LCC-20(*)
LOCC-44
LCC-28
LOCC-68
LCC-32
LCC-44 (0)
LOCC-84
LCC-48
LCC-52
LCC-68
LCC-84
LCC-124
LOCC-124
..C r----------------------------------------------------------------------------------------------,
::l
LINEAR PRODUCTS IN SURFACE MOUNT
::il
Linear functions available in surface mount include:
o
Q)
U
ftI
't:
::l
en
TABLE II: Surface Mount Package
Thermal Resistance Range"
• Op amps
• Comparators
Package
• Regulators
• References
• Data conversion
• Industrial
• Consumer
• Automotive
A complete list of linear part numbers in surface mount is
presented in Table III. Refer to the datasheet in the appropriate chapter of this databook for a complete description of
the device. In addition, National is continually expanding the
list of devices offered in surface mount. If the functions you
need do not appear in Table III, contact the sales office or
distributor branch nearest you for additional information.
Automated manufacturers can improve their cost savings by
using Tape-and-Reel for surface mount devices. Simplified
handling results because hundreds-to-thousands of semiconductors are carried on a single Tape-and-Reel pack (see
ordering and shipping information-printed later in this section-for a comparison of devices/reel vs. devices/rail for
those surface mount package types being used for linear
products). With this higher device count per reel (when compared with less than a 100 devices per rail), pick-and-place
machines have to be re-Ioaded less frequently and lower
labor costs result.
Thermal Resistance··
(OjA,·C/W)
SO-8
SO-14
SO-14 Wide
SO-16
SO-16 Wide
SO-20
SO-24
120-175
100-140
70-110
90-130
70-100
60-90
55-85
PCC-20
PCC-28
PCC-44
70-100
60-90
40-60
• Actual thermal resistance for a particular device depends on die size.
Re'er to the datasheet for the actual 9jA value.
"Test conditions: PCB mount (FR4 material), still air (room temperature),
copper traces (150 x 20 x 10 mils).
Given a max junction temperature of 150·C and a maximum
allowed ambient temperature, the surface mount device will
be able to dissipate less power than the DIP device. This
factor must be taken into account for new designs.
For board conversion, the DIP and surface mount devices
would have to dissipate the same power. This means the
surface mount circuit would have a lower maximum allowable ambient temperature than the DIP circuit. For DIP circuits where the maximum ambient temperature required is
substantially lower than the maximum ambient temperature
allowed, there may be enough margin for safe operation of
the surface mount circuit with its lower maximum allowable
ambient temperature. But where the maximum ambient temperature required of the DIP current is close to the maximum allowable ambient temperature, the lower maximum
ambient temperature allowed for the surface mount circuit
may fall below the maximum ambient temperature required.
The circuit designer must be aware of this potential pitfall so
that an appropriate work-around can be found to keep the
surface mount package from being thermally overstressed
in the application.
With Tape-and-Reel, manufacturers save twice-once from
using surface mount technology for automated PC board
assembly and again from less device handling during shipment and machine set-up.
BOARD CONVERSION
Besides new designs, many manufacturers are converting
existing printed circuit board designs to surface mount. The
. resulting PCB will be smaller, lighter and less expensive to
manufacture; but there is one caveat-be careful about the
thermal dissipation capability of the surface mount package.
Because the surface mount package is smaller than the traditional dual-in-line package, the surface mount package is
not capable of conducting as much heat away as the DIP
(i.e., the surface mount package has a higher thermal resistance-see Table II).
The silicon for most National devices can operate up to a
150·C junction temperature (check the datasheet for the
rare exception). Like the DIP, the surface mount package
can actually withstand an ambient temperature of up to
125·C (although a commercial temperature range device
will only be specified for a max ambient temperature of 70·C
and an industrial temperature range device will only be
specified for a max ambient temperature of 85·C). See
AN-336, "Understanding Integrated Circuit Package Power
Capabilities", (reprinted in the appendix of each linear databook volume) for more information.
SURFACE MOUNT LITERATURE
National has published extensive literature on the subject of
surface mount packaging. Engineers from packaging, quality, reliability, and surface mount applications have pooled
their experience to provide you with practical hands-on
knowledge about the construction and use of surface mount
packages.
The applications note AN-450 "Surface Mounting Methods
and their Effect on Product Reliability" is referenced on
each SMD datasheet. In addition, "Wave Soldering of Surface Mount Components" is reprinted in this section for your
information.
8-4
.--------------------------------------------------------------------------.0
C
TABLE III. Linear Surface Mount Current Device Listing
Amplifiers and Comparators
Part Number
LF347WM
LF351M
LF451CM
LF353M
LF355M
LF356M
LF357M
LF444CWM
LM10CWM
LM10CLWM
LM308M
LM308AM
LM310M
LM311M
LM318M
LM319M
LM324M
LM339M
LM346M
LM348M
LM358M
LM359M
Data Acquisition Circuits
Part Number
Part Number
ADC0802LCV
ADC0802LCWM
ADC0804LCV
ADC0804LCWM
ADC0808CCV
ADC0809CCV
LM392M
LM393M
LM741CM
LM1458M
LM2901M
LM2902M
LM2903M
LM2904M
LM2924M
LM3403M
ADC0811BCV
ADC0811CCV
ADC0819BCV
ADC0819CCV
ADC0820BCV
ADC0820CCV
LM4250M
LM324M
LM339M
LM365WM
LM607CM
LMC669BCWM
LMC669CCWM
LF441CM
DAC0808LCM
DAC0830LCWM
DAC0830LCV
DAC0832LCWM
DAC0832LCV
Industrial Functions
Part Number
Part Number
LM317LM
LF3334M
LM2931M·5.0
LM3524M
LM78L05ACM
LM78L12ACM
LM78L15ACM
LM385M
LM385M-1.2
ADC1025BCV
ADC1025CCV
DAC0800LCM
DAC0801LCM
DAC0802LCM
DAC0806LCM
DAC0807LCM
ADC0838BCV
ADC0838CCV
ADC0841BCV
ADC0841CCV
ADC0848BCV
ADC0848CCV
ADC1005BCV
ADC1005CCV
Regulators and References
LM336M·2.5
LF336BM·2.5
LM336M·5.0
LM336BM·5.0
LM337LM
Part Number
LM79L05ACM
LM79L12ACM
LM79L15ACM
LP2951ACM
LP2951CM
Part Number
Part Number
AH5012CM
LF13331M
LF13509M
LF13333M
LM555CM
LM13600M
LM13700M
LMC555CM
LM567CM
MF4CWM-50
LM556CM
LM567CM
LM1496M
LM2917M
MF4CWM-100
MF6CWM-50
MF10CCWM
MF6CWM-100
MF5CWM
LM3046M
LM3086M
LM3146M
LM385BM-1.2
LM385M-2.5
LM385BM-2.5
LM723CM
LM2931CM
Commercial and Automotive
8-5
Part Number
Part Number
LM386M-1
LM592M
LM831M
LM832M
LM833M
LM1837M
LM1851M
LM1863M
LM1865M
LM1870M
LM837M
LM838M
LM1131CM
LM1894M
LM1964V
LM2893M
LM3361AM
LM1881M
§
is:
oC
:::J
..C r------------------------------------------------------------------------------------------,
Package
5 Hybrids
Package
Max/Rail
Per Reel'
:e
~
::J
U)
Designator
Part Number
Part Number
LHOO02E
LH4002E
LH0032E
LH0033E
SO-8
SO-14
SO-14 Wide
SO-16
SO-16 Wide
SO-20
SO-24
A FINAL WORD
National is a world leader in the design and manufacture of
surface mount components.
Because of design innovations such as perforated copper
leadframes, our small outline package is as reliable as our
DIP-the laws of physics would have meant that a straight
"junior copy" of the DIP would have resulted in an "S.O."
package of lower reliability. You benefit from this equivalence of reliability. In addition, our ongoing vigilance at each
step of the production process assures that the reliability we
designed in stays in so that only devices of the highest quality and reliability are shipped to your factory.
Our surface mount applications lab at our headquarters site
in Santa Clara, California continues to research (and publish) methods to make it even easier for you to use surface
mount technology. Your problems are our problems.
When you think "Surface Mount"-think "National"!
M
M
WM
M
WM
M
M
100
50
50
50
50
40
30
2500
2500
1000
2500
1000
1000
1000
V
V
V
50
40
25
1000
1000
500
PQfP-196
Vf
TBD
TP-40
TP
100
TBD
E
E
50
25
-
PCL-20
PCL-28
PCL-44
LCC-20
LCC-44
-
·Incremental ordering quantities. (National Semiconductor reserves the right
to provide a smaller quantity of devices per Tape-and-Reel pack to preserve
lot or date code integrity. See example below.)
Example: You order 5,000 LM324M ICs shipped in Tapeand-Reel.
• Case 1: All 5,000 devices have the same date code
Ordering and Shipping Information
• You receive 2 SO-14 (Narrow) Tape-and-Reel
packs, each having 2500 LM324M ICs
• Case 2: 3,000 devices have date code A and 2,000 devices have date code B
• You receive 3 SO-14 (Narrow) Tape-and-Reel
packs as follows:
When you order a surface mount semiconductor, it will be in
one of the several available surface mount package types.
Specifying the Tape-and-Reel method of shipment means
that you will receive your devices in the foilowing quantfties
per Tape-and-Reel pack: SMD devices can also be supplied
in conventional conductive rails.
Pack # 1 has 2,500 LM324M ICs with date code A
Pack #2 has 500 LM324M ICs with date code A
Pack #3 has 2,000 LM324M ICs with date code B
Short-Form Procurement Specification
TAPE FORMAT
Trailer (Hub End)'
Carrier'
Leader (Start End)'
Empty Cavities,
min (Unsealed
Cover Tape)
Empty Cavities,
min (Sealed
Cover Tape)
Filled Cavities
(Sealed
Cover Tape)
Empty Cavities,
min (Sealed
Cover Tape)
Empty Cavities,
min (Unsealed
Cover Tape)
SO-8 (Narrow)
2
2
2500
5
5
SO-14 (Narrow)
2
2
2500
5
5
SO-14 (Wide)
2
2
1000
5
5
SO-16 (Narrow)
2
2
2500
5
5
SO-16 (Wide)
2
2
1000
5
5
SO-20 (Wide)
2
2
1000
5
5
SO-24 (Wide)
2
2
1000
5
5
PCC-20
2
2
1000
5
5
PCC-28
2
2
750
5
5
PCC-44
2
2
500
5
5
Small Outline IC
Plastic Chip Carrier IC
'The following diagram Identifies these sections of the tape and Pin (11 device orientation.
8-6
,--------------------------------------------------------------------------, w
c
Short-Form Procurement Specification
iit
n
(Continued)
DEVICE ORIENTATION
r-
CD
DIRECTION
OF FEED
TRAILER
SECTION
o==
•
----i·*r·t---------CARRIERSECTION--------_~t..---------I~~I
,-----...,
)000000000000000000000000000900~OOOOOOOOOOOOOOOOC
i
II
I
I
I
HUB
END
''---'-I-~''--~
• EMPTY
CAVITIES
• UNSEALED
COVER TAPE
• EMPTY
CAVITIES
• SEALED
COVER TAPE
:
I
I
I
:
i
I
~~i~3DCt:~~:iTAPE.-7-'·s-~ '. ~::.hES J' - .-~:-r~PT-r/-IES- '
• SEALED
~--------::o
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i
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r:-v-
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i
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0
• UNSEALED
PeC-IC
DEVICES
TLlXX/0026-8
• Reel:
MATERIALS
• Cavity Tape: Conductive PVC (less than 105 Ohms/Sq)
(1) Solid 80 pt fibreboard (standard)
(2) Conductive fibreboard available
• Cover Tape: Polyester
(3) Conductive plastic (PVC) available
(1) Conductive cover available
TAPE DIMENSIONS (24 Millimeter Tape or Less)
__ Po 10 PITCH CUMULATIVE
TAPE TOLERANCE ±0.2mm
DEVICE ORIENTATION
PIN
1
SO·IC
PCC-IC
TL/XX/OO28-9
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Short-Form Procurement Specification (Continued)
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Small Outline IC
80-8
12±.30 8.0±.10
(Narrow)
5.5±.05 1.75±.10 2.0±.05 4.0±.10 1.55±.05 .30±.10 6.4±.10
5.2±.10
2.1 ±.10 1.55±.05 30
80-14
16±.30 8.0±.10
(Narrow)
7.5±.10 1.75±.10 2.0±.05 4.0±.10 1.55±.05 .30±.10 6.5±.10
9.0±.10
2.1 ±.10 1.55±.05 40
9.5±.10
3.0±.10 1.55±.05 40
80-14
(Wide)
16±.30 12.0±.10 7.5±.10 1.75±.10 2.0±.05 4.0±.10 1.55±.05 .30±.10 10.9±.10
80-16
16±.30 8.0±.10
(Narrow)
80-16
(Wide)
80-20
(Wide)
80-24
(Wide)
7.5±.10 1.75±.10 2.0±.05 4.0±.10 1.55±.05 .30±.10 6.5±.10
10.3±.10 2.1 ±.10 1.55±.05 40
16±.30 12.0±.10 7.5±.10 1.75±.10 2.0±.05 4.0±.10 1.55±.05 .30±.10 10.9±.10 10.76±.10 3.0±.10 1.55±.05 40
24±.30 12.0±.10 11.5±.10 1.75±.10 2.0±.05 4.0±.10 1.55±.05 .30±.10 10.9±.10 13.3±.10 3.0±.10 2.05±.05 50
24±.30 12.0±.10 11.5±.10 1.75±.10 2.0±.05 4.0±.10 1.55±.05 .30±.10 10.9±.10 15.85±.10 3.0±.10 2.05±.05 50
Plastic Chip Carrier IC
PCC-20
16±.30 12.0±.10 7.5±.10 1.75±.10 2.0±.05 4.0±.10 1.55±.05 .30±.10 9.3±.10
PCC-28
24±.30 16.0±.10 11.5±.10 1.75±.10 2.0±.05 4.0±.10 1.55±.05 .30±.10 13.0±.10 13.0±.10 4.9±.10 2.05±.05 50
Note 1: 1\0. Bo and
9.3±.10
4.9±.10 1.55±.05 40
Ko dimensions are measured 0.3 mm above the inside wall of the cavity bottom.
Nota 2: Tape with components shall pass around a mandril radius R without damage.
Note 3: Cavity tape material shall be PVC conductive (less than 105 Ohms/Sq).
Note 4: Cover tape material shall be polyester (30-65 grams peel-back force).
Note 5: 0, Dimension is centered within cavity.
Note 6: All dimensions are in millimeters.
REEL DIMENSIONS
TMAX
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APPLICATION NOTE REFERENCED BY PART NUMBER
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National Semiconductor Linear Application notes are normally written to explain
the operation and use of a particular device or family of IC's, or to present alternative technical solutions. The following PART NUMBER index references the published application notes that would offer application assistance for those specific
IC's.
, The 1986 Linear Applications Handbook is a complete text for all current Application Notes for both Monolithic and Hybrid products. Specific Application Notes are
available upon request through National Semiconductor Sales Offices.
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DEVICE NUMBER
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APPLICATION NOTE
9-4
»
DEVICE NUMBER
APPLICATION NOTE
DAC1008 ...................................................... AN-271, AN-275, AN-277, AN-284
DAC1020 .............................................. AN-263, AN-269, AN-293, AN-294, AN-299
DAC1021 ............................................................................. AN-269
DAC1022 ............................................................................. AN-269
DAC1208 .....................................................................AN-271 , AN-284
DAC1209 .....................................................................AN-271 , AN-284
DAC1210 ..................................................................... AN-271 , AN-284
DAC1218 ............................................................................. AN-293
DAC1220 ..................................................................... AN-253, AN-269
DAC1221 .............................................................................AN-269
DAC1222 .............................................................................AN-269
DAC1230 .............................................................................AN-284
DAC1231 ..................................................................... AN-271, AN-284
DAC1232 ..................................................................... AN-271, AN-284
DAC1280 ..................................................................... AN-261, AN-263
DH0034 ...............................................................................AN-253
DH0035 ................................................................................ AN-49
D88606 ....................................................................... AN-381 , AN-382
D88608 ................................................. " ............................ AN-382
DT1058 ...............................................................................AN-287
DT1060 ...............................................................................AN-287
DT8W250E2 .......................................................................... AN-287
DT8W250GI ........................................................................... AN-287
IN88070 .............................................................................. AN-260
LF111 .................................................................................. LB-39
LF155 ........................................................................ AN-263, AN-447
LF198 ........................................................................ AN-245, AN-294
LF311 ................................................................................AN-301
LF347 ......................... AN-256, AN-262, AN-263, AN-265, AN-266, AN-301 , AN-344, AN-447
LF351 ...................... AN-242, AN-263, AN-266, AN-271, AN-275, AN-293, AN-447, Appendix C
LF351A ...............................................................................AN-240
LF351 B ........................................................................... Appendix D
LF353 ........ AN-256, AN-258, AN-263, AN-264, AN-271, AN-285, AN-293, AN-447, LB-44, Appendix D
LF356 ................................. AN-253, AN-258, AN-260, AN-263, AN-266, AN-271, AN-272,
AN-275, AN-293, AN-294, AN-295, AN-301, AN-447
LF357 .................................................................. AN-263, AN-447, LB-42
LF398 ........................................... AN-247, AN-258, AN-266, AN-294, AN-298, LB-45
LF400 ........................................................................ AN-428, AN-447
LF411 ......................................................... AN-294, AN-301, AN-344, AN-447
LF412 ................................................. AN-272, AN-299, AN-301, AN-344, AN-447
LF441 ........................................................................ AN-301, AN-447
LF13006 .............................................................................. AN-344
LF13007 .............................................................................. AN-344
LF13331 ...................................................................... AN-294, AN-447
LF13508 .............................................................. AN-289, AN-360, AN-447
LF13509 .............................................................. AN-289, AN-295, AN-447
LH0002 .................................. AN-13, AN-63, AN-227, AN-244, AN-263, AN-272, AN-301
LH0022 ......................................................................... AN-63, AN-75
LH0023 .......................................................................AN-245, AN-360
LH0024 ............................................................................... AN-253
LH0032 ............................................................... AN-242, AN-244, AN-253
LH0033 ........................................................ AN-48, AN-115, AN-227, AN-253
LH0042 .......................................................................... , ..... AN-63
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Typical A + Flow is:
General
• SEM
• Assembly and Seal
National Semiconductor Commercial Reliability Programs
provide a broad range of off-the-shelf enhanced semiconductor products that supply an extra measure of quality and
reliability needed in high-stress or difficult to service applications.
National's A + and B + programs allow each individual customer to:
• Four Hour 150'C Bake
• Five Temperature Cycles (O'C to + 100'C)
• High Temperature Electrical Test
• Electrical Test
• Burn-In (160 hours at a minimum junction temperature of
125'C)
• Minimize the need for incoming electrical inspection
• Eliminate the need and associated costs of using independent testing laboratories
• DC Parametric and Function Tests
• Tightened Quality Control Inspection Plans
• Reduction in infant mortality rate
• Reduction in reworked board costs
• Reduction in warranty and service costs
Note: Certain products may follow slightly different procass flows dictated
by specific capabilities and device characteristics, consult NSC.
P + Product Enhancement
A + Product Enhancement
The P + product enhancement program applies to regulator
devices and offers an added advantage. P+ involves a dynamic self-heating burn-in that tests the thermal shutdown
of the regulator. P + is proven more effective than the standard 125'C burn-in as an early screen for infant mortality
defects. It sharply reduces the cost of testing incoming components. Reliability Report L-140 further explains the P+
process. The following chart lists regulators which receive
P + prior to shipment and at no additional cost.
The A + Product Enhancement incorporates the benefits of
the Multiple-Pass and Elevated Temperature along with
"BURN-IN."
The A + Program provides:
• 100% Temperature Cycling
• 100% Electrical Testing at Room and High Temperature
• 100% Burn-In Testing Combining Increased Temperature with Applied Voltage
• Acceptable Quality Levels Greater than Industry Norm
Package Types
Device
TO-3
TO-39 H TO-220T TO-202P TO-92Z
KSTEEL
LM109/309
X
X
LM117/317
X
X
LM 117HV/317HV
X
X
LM120/320
X
LM123/323
X
X
X
X
X
X
X
X
X
X
LM137/337
X
X
LM137HV/337HV
X
X
LM13B/33B
X
LM140/340
X
LM145/345
X
LM150/250/350
X
LM196/396
X
X
LM2930/2935/2940/29B4
X
LM2931
X
LM7BXX
X
9-10
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Appendix 0
Military Aerospace Programs
from National Semiconductor
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This appendix is intended to provide a brief overview of military products available from National Semiconductor. For
further information, refer to our 1987 Reliability Handbook.
MIL-STD-883
Although originally intended to establish uniform test methods and procedures, MIL-STD-883 has also become the
general specification for non-JAN military product. Revision
C of this document defines the minimum requirements for a
device to be marked and advertised as 883-compliant. Included are design and construction criteria, documentation
controls, electrical and mechanical screening requirements,
and quality control procedures. Details can be found in paragraph 1.2.1 of MIL-STD-883.
IVIIL-M-38510
The MIL-M-38510 Program, which is sometimes called the
JAN IC Program, is administered by the Defense Electronics
Supply Center (DESC). The purpose of this program is to
provide the military community with standardized products
that have been manufactured and screened to governmentcontrolled specifications in government-certified facilities.
All 3851 0 manufacturers must be formally qualified and their
products listed on DESC's Qualified Products List (QPL) before devices can be marked and shipped as JAN product.
National offers both 883 Class Band 883 Class S product.
The screening requirements for both classes of product are
outlined in Table III.
As with DESC specifications, a manufacturer is allowed to
use his standard electrical tests provided that all critical parameters are tested. Also, the electrical test parameters,
test conditions, test limits, and test temperatures must be
clearly documented. At National Semiconductor, this information is available via our RETS (Reliability Electrical Test
Specification Program). The RETS document is a complete
description of the electrical tests performed and is controlled by our QA department. Individual copies are available
upon request.
There are two processing levels specified within MIL-M38510: Classes Sand B. Class S is typically specified for
space flight applications, while Class B is used for aircraft
and ground systems. National is a major supplier of both
classes of devices. Screening requirements are outlined in
Table III.
Tables I and II explain the JAN device marking system.
Copies of MIL-M-38510, the QPL, and other related documents may be obtained from:
Naval Publications and Forms Center
5801 Tabor Avenue
Philadelphia, PA 19120
(212) 697-2179
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Some of National's older products are not completely compliant with MIL-STD-883 but are still required for use in military systems. These devices are screened to the same
stringent requirements as 883 product but are marked
"-MIL".
DIESC Specifications
Military Screening Program (MSP)
DESC specifications are issued to provide standardized versions of devices which are not yet available as JAN product.
MIL-STD-883 Class B screening is coupled with tightly controlled electrical specifications which have been written to
allow a manufacturer to use his standard electrical tests. A
current listing of National's DESC specification offerings can
be obtained from our franchised distributors, sales offices,
or DESC. DESC is located in Dayton, Ohio.
National's Military Screening Program was developed to
make screened versions of advanced products such as gate
arrays and microprocessors available more quickly than is
possible for JAN and 883 devices. Through this program,
screened product is made available for prototypes and
breadboards prior to or during the JAN or 883 qualification
activities. MSP products receive the 100% screening of Table III but are not subjected to Group C and D quality conformance testing. Other criteria such as electrical testing
and temperature range will vary depending upon individual
device status and capability.
9-11
•
~ r-----------------------------------------------------------------------------------------~
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TABLE I. The MIL-M-38510 Part Marking
~~8~(X~~XYYY
8
Lead Finish
A= Solder Dipped
B=TIn
Plate
[
C= Gold Plate
X= Any lead finish above
Is acceptable
Device Package
(see Table II)
' - Screening Level
S, B, or C
Device Number on
Slash Sheet
' - - - Slash Sheet Number
' - - - - - For radiation hard devices
this slash Is replaced by the
Radiation Hardness Assurance
Designator (1.1, D, R, or H per
paragraph 3.4.1.3 of MIL-1.138510)
L-----MIL-M-38510
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(which may be applied only to
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paragraphs 3.6.2.1 and 3.6.7 of
MIL-1.1-38510)
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TABLE II. JAN Package Codes
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Package
Designation
A
B
C
D
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F
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M
N
P
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R
S
T
U
V
W
X
Y
Z
2
3
Microcircuit Industry ,
Description
14-Pin 1/4" X 1/4" (metal) flat pack
14-Pin 3/16" X 1/4" flat pack
14-Pin 1/4" X 3/4" dual-in-line
14-Pin 1/4" X3/8" (ceramic) flat pack
16-Pin 1/4" X3/8" dual-in-line
16-Pin 1/4" X 3/8" (metal or ceramic)
flat pack
8-pin TO-99 can or header
10-pin 1/4" x 1/4" (metal) flat pack
1O-pin TO-l 00 can or header
24-pin 1/2" x 1-1/4" dual-in-line
24-pin 3/8" x 5/8" flat pack
24-pin 1/4" x 1-1/4" dual-in-line
12-pin TO-l 01 can or header
(Note 1)
8-pin 1/4" x 3/8" dual-in-line
40-pin 3/16" x 2-1 /16" dual-in-line
20-pin 1/4" x 1-1/16" dual-in-line
20·pin 1/4" x 1/2" flat pack
(Note 1)
(Note 1)
18-pin 3/8" x 15/16" dual-in-line
22-pin 3/8" x 1-1/8" dual-in-line
(Note 1)
(Note 1)
(Note 1)
20-terminaI0.350" x 0.350" chip carrier
28-terminal 0.450" x 0.450" chip carrier
Note 1: These letters are assigned to packages by individual detail specifi·
cations and may be assigned to different packages in different specifications.
9-12
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TABLE III. 100% Screening Requirements
:I
Class B
ClassS
Co
Screen
Method
Reqmt
Method
Reqmt
1.
Wafer Lot Acceptance
5007
All Lots
-
2.
Nondestructive Bond Pull
2023
100%
-
3.
Internal Visual (Note 1)
2010, Condition A
100%
2010, Condition B
100%
4.
Stabilization Bake
1008, Condition C,
24 hrs. Min.
100%
1008, Condition C,
24 hrs. Min.
100%
5.
Temp. Cycling (Note 2)
1010, Condition C
100%
1010, Condition C
100%
6.
Constant Acceleration
2001, Condition E (Min.)
y 1 Orientation Only
100%
2001, Condition E, (Min.),
Y 1 Orientation Only
100%
7.
Visual Inspection (Note 3)
8.
Particle Impact Noise Detection (PIND)
2020, Condition A (Note 4)
100%
9.
Serialization
(Note 5)
100%
10.
Interim (Pre-Burn-In) Electrical
Parameters
Per Applicable Device
Specification (Note 13)
100%
11.
Burn-In Test
1015
240 Hrs. @ 125'C Min.
(Cond. F Not Allowed)
100%
100%
100%
Per Applicable Device
Specification (Note 13)
100%
13.
Reverse Bias Burn-In (Note 7)
1015; Test Condition A, C,
72 Hrs. @ 150'C Min.
(Cond. F Not Allowed)
100%
All Lots
5% Parametric (Note 14),
3% Functional -25'C
16.
Final Electrical Test
a) Static Tests
1) 25'C (Subgroup 1, Table I, 5005)
2) Max & Min Rated Operating Temp.
(Subgroups 2, 3, Table I, 5005)
b) Dynamic Tests & Switching Tests, 25'C
(Subgroups 4, 9, Table I, 5005)
c) Functional Test, 25'C
(Subgroup 7, Table I, 5005)
Per Applicable Device
Specification
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Interim (Post-Burn-In) Electrical
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PDA Calculation
1015
160 Hrs.
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15.
Per Applicable Device
Specification (Note 6)
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Specification
100%
100%
100%
100%
100%
100%
100%
100%
•
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TABLE III. 100% Screening Requirements (Continued)
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8
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Screen
Method
17.
Seal Fine, Gross
1014
ClassB
Reqmt
100%, (Note 8)
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18.
Radiographic (Note 10)
2012 Two Views
100%
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Qualification or Quality Conformance
Inspection Test Sample Selection
(Note 11)
Samp.
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20.
External Visual (Note 12)
2009
100%
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1014
Reqmt
100%, (Note 9)
(Note 11)
Samp.
100%
Note 1: Unless otherwise specified. at the manufaclurer'S option. test samples for Group B. bond strength (Method 5005) may be randomly selected prior to or
following internal visual (Method 5004). prior to sealing provided all other specification requirements are satisfied (e.g. bond strength requirements shall apply to
each inspection lot, bond failures shall be counted even if the bond would have failed internal visual).
E
Note 2: For Class B devices, this test may be replaced with thermal shock method 1011, test condition A, minimum.
CI
Note 3: At the manufacturer's option, visual inspection for catastrophic failures may be conducted after each of the thermal/mechanical screens, after the
sequence or after seal test. Catastrophic failures are defined as missing leads, broken packages, or lids off.
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Note 4: The PIND test may be performed in. any sequence after step 6 and prior to step 16. See MIL-M-38510. paragraph 4.6.3.
Note 5: Class S devices shall be serialized prior to interim electrical parameter measurements.
Note 6: When specified. all devices shall be tested for those parameters requiring delta calculations.
Note 7: Reverse bias bum-in is a requirement only when specified in the applicable device specification. The order of performing bum-in and reverse bias bum-in
may be inverted.
Note 8: For Class 5 devices. the seal test may be performed in any sequence between step 16 and step 19. but it shall be performed after all shearing and forming
operations on the terminals.
Note 9: For Class B devices, the fine and gross seal tests shall be performed separate or together in any sequence and order between step 6 and step 20 except
that they shall be performed after all shearing and forming operations on the terminals. When 100% seal screen cannot be performed after shearing and forming
(e_g. flatpacks and chip carriers) the seal screen shall be done 100% prior to these operations and a sample test (LTPD = 5) shall be performed on each
inspection lot following these operaUons. If the sample fails. 100% rescreening shall be required_
Note 10: The radiographic screen may be performed in any sequence after step 19.
-Nole-l1:-Samples-shall-be-selecled for testing in accordance with the specific device class and lot requirements of Method 5005
Nole 12: External Visual shall be performed on the lot any lime after step 19 and prior to shipment.
Note 13: Read and Record when past bum-in delta measurements are specified.
Note 14: PDA shall apply to all static, dynamiC, functional, and switching measurements at either 25°C or maximum rated operating temperature.
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Appendix E
Understanding Integrated Circuit
Package Power Capabilities
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INTRODUCTION
The short and long term reliability of National Semiconductor's interface circuits, like any integrated circuit, is very dependent on its environmental condition. Beyond the mechanical/environmental factors, nothing has a·greater influence on this reliability than the electrical and thermal stress
seen by the integrated circuit. Both of these stress issues
are specifically addressed on every interface circuit data
sheet, under the headings of Absolute Maximum Ratings
and Recommended Operating Conditions.
Failure rate is the number of devices that will be expected to
fail in a given period of time (such as, per million hours). The
mean time between failure (MTBF) is the average time (in
hours) that will be expected to elapse after a unit has failed
before the next unit failure will occur. These two primary
"units of measure" for device reliability are inversely relat·
ed:
MTBF =
However, through application calls, it has become clear that
electrical stress conditions are generally more understood
than the thermal stress conditions. Unde~standing the importance of electrical stress should never be reduced, but
clearly, a higher focus and understanding must be placed on .
thermal stress. Thermal stress and its application to interface circuits from National Semiconductor is the subject of
this application note.
Although the "bathtub" curve plots the overall failure rate
versus time, the useful failure rate can be defined as. the
percentage of devices that fail per-unit-time during the flat
portion of the curve. This area, called the useful life, extends
between t1 and t2 or from the end of infant mortality to the
onset of wearout. The useful life may be as short as several
years but usually extends for decades if adequate design
margins are used in the development of a system.
FACTORS AFFECTING DEVICE RELIABILITY
Figure 1 shows the well known "bathtub" curve plotting failure rate versus time. Similar to all system hardware (mechanical or electrical) the reliability of interface integrated
circuits conform to this curve: The key issues associated
with this curve are infant mortality, failure rate, and useful
life.
Many factors influence useful life including: pressure, mechanical stress, thermal cycling, and electrical stress. However, die temperature during the device's useful life plays an
equally important role in triggering the onset of wearout.
FAILURE RATES vs TIME AND TEMPERATURE
The relationship between integrated circuit failure rates and
time and temperature is a well established fact. The occurrence of these failures is' a function which can be represented by the Arrhenius Model. Well validated and predominantly used for accelerated life testing of integrated circuits, the
Arrhenius Model assumes the degradation of a performance
parameter is linear with time and that MTBF is a function of
temperature stress. The temperature dependence is an exponential function that defines the probability of occurrence.
This results in a formula for expressing the lifetime or MTBF
at a given temperature stress in relation to another MTBF at
a different temperature. The ratio of these two MTBFs is
called the acceleration factor F and is defined by the following equation:
INFANT
MORTALITY
(SHADED AREA)
m
EARLY UFE
"
USEFUL UFE
~
1
Failure Rate
WEARDUT TIME
TL/H/9312-1
FIGURE 1. Failure Rate vs Time
F =
Infant mortality, the high failure rate from time to to t1 (early
life), is greatly influenced by system stress conditions other
than temperature, and can vary widely from one application
to another. The main stress factors that contribute to infant
mortality are electrical transients and noise, mechanical
maltreatment and excessive temperatures. Most of these
failures are discovered in device test, burn-in, card assembly and handling, and initial system test and operation. Although important, much literature is available on the subject
of infant mortality in integrated circuits and is beyond the
scope of this application note.
~~ =
exp
[~( ;2 -
;1)]
Where: X1 = Failure rate at junction temperature T1
X2 = Failure rate at junction temperature T2
T
= JUnction temperature in degrees Kelvin
E = Thermal activation energy in electron volts
(ev)
K = Boltzman's constant
9-18
»
flows from the chip to the ultimate heat sink, the ambient
environment. There are two predominant paths. The first is
from the die to the die attach pad to the surrounding package material to the package lead frame to the printed circuit
board and then to the ambient. The second path is from the
package directly to the ambient air.
However, the dramatic acceleration effect of junction temperature (chip temperature) on failure rate is illustrated in a
plot of the above equation for three different activation energies in Figure 2. This graph clearly demonstrates the importance of the relationship of junction temperature to device failure rate. For example, using the 0.99 ev line, a 30'
rise in junction temperature, say from 130'C to 160'C, results in a 10 to 1 increase in failure rate.
Improving the thermal characteristics of any stage in the
flow chart of Figure 4 will result in an improvement in device
thermal characteristics. However, grouping all these characteristics into one equation determining the overall thermal
capability of an integrated circuit/package/environmental
condition is possible. The equation that expresses this relationship is:
~1000k
...
t--t--+---j--+-....,,~-l
C)
lOOk
~
10k
~
lk
1-+-+-,j'l---1;!~l--I
w
100
I-+---:;II'-""""'I--HI-l--I
~
~
::l
3
TJ = TA + Po (OJA)
Where: TJ = Die junction temperature
10 l-~tIC-+--!:I..-+t~!=--I
60
90
120 150 180 210
TLlH/9312-2
FIGURE 2_ Failure Rate as a Function
of Junction Temperature
DEVICE THERMAL CAPABILITIES
There are many factors which affect the thermal capability
of an integrated circuit. To understand these we need to
understand the predominant paths for heat to transfer out of
the integrated circuit package. This is illustrated by Figures
3and 4.
Figure 3 shows a cross-sectional view of an assembled integrated circuit mounted into a printed circuit board.
ic:
::s
c..
(I)
til
Dr
::s
c..
:i"
CC
-
CC
iiI
( I)
Thermal resistance junction-to-ambient
OJA, the thermal resistance from device junction-to-ambient
temperature, is measured and specified by the manufacturers of integrated circuits. National Semiconductor utilizes
special vehicles and methods to measure and monitor this
parameter. All circuit data sheets specify the thermal characteristics and capabilities of the packages available for a
given device under specific conditions-these package
power ratings directly relate to thermal resistance junctionto-ambient or 0JA.
Although National provides these thermal ratings, it is critical that the end user understand how to use these numbers
to improve thermal characteristics in the development of his
system using IC components.
JUNCTION TEMPERATURE ('CI
c..
>e-
( I)
Po = Total power dissipation (in watts)
oJA =
(I)
::s
5'
T A = Ambient temperature in the vicinity device
if
"C
"C
c..
o
:;n
c
;::;:
"tI
1\1
n
~
1\1
CC
(I)
"tI
o
...~
o
1\1
"C
1\1
g;
Figure 4 is a flow chart showing how the heat generated at
the power source, the junctions of the integrated circuit
;::;:
CD-
til
DEVICE LEAD
TLlH/9312-3
FIGURE 3_ Integrated Circuit Soldered into a Printed Circuit Board (Cross-Sectional View)
DIE
JUNCTION
(ENERGY
SOURCE)
f--+
DIE
r---+
DIE
ATTACH
PAD
r--+
PACKAGE
MATERIAL
r--.
LEAD
FRAME
f--+
PRINTED
CIRCUIT
BOARD
AIRFILM
AROUND
PACKAGE
f--+
AMBIENT
f--+
AMBIENT
TLlH/9312-4
FIGURE 4_ Thermal Flow (Predominant Paths)
9-19
II)
CI)
~
DETERMINING DEVICE OPERATING
JUNCTION TEMPERATURE
c.
From the above equation the method of determining actual
worst-case device operating junction temperature becomes
straightforward. Given a package thermal characteristic,
8JA, worst-case ambient operating temperature, TA(max),
the only unknown parameter is device power dissipation,
Po. In calculating this parameter, the dissipation of the integrated circuit due to its own supply has to be considered,
th(;l dissipation within the package due to the external load
must also be added. The power associated with the load in
a dynamic (switching) situation must also be considered.
For example, the power associated with an inductor or a
capacitor in a static versus dynamic (say, 1 MHz) condition
is significantly different.
:cco
co
o....
CI)
o==
D.
CI)
C)
CO
oX
U
CO
D.
-
":i
u
....
(3
.=
-C
CI)
....
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CO
CI)
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c
:ac
CO
~
CI)
-C
C
;:)
1-
LIJ
><
:ac
CI)
c.
c.
c:(
The slope of the straight line between these two points is
minus the inversion of the thermal resistance. This is referred to as the derating factor.
Derating Factor =
As mentioned, Figure 5 is a plot of.the safe thermal operating area for a device in a 16-pin molded DIP. As long as the
intersection of a vertical line defining the maximum ambient
temperature (70°C in our previous example) and maximum
device package power (600 mW) remains below the maximum package thermal capability line the junction temperature will remain below 150°C-the limit for a molded package. If the intersection of ambient temperature and package
power fails on this line, the maximum junction temperature
will be 150°C. Any intersection that occurs above this line
will result in a junction temperature in excess of 150°C and
is not an appropriate operating condition.
The junction temperature of a device with a total package
power of 600 mW at 70°C in a package with a thermal resistance of 63°C/W is 108°C.
TJ = 70°C
+ (63°C/W) x
(0.6W) = 108°C
2.4
The next obvious question is, "how safe is 108°C?"
~ 2.0
MAXIMUM ALLOWABLE JUNCTION TEMPERATURES
i5
~
What is an acceptable maximum operating junction temperature is in itself somewhat of a difficult question to answer.
Many companies have established their own standards
based on corporate policy. However, the semiconductor industry has developed some defacto standards based on the
device package type. These have been well accepted as
numbers that relate to reasonable (acceptable) device lifetimes, thus failure rates.
1.6
~ 1.2
~
3l 0.8
~
0.4
I
16-PIN
t------I-----I---t-Mo~OEO PACKAGE
",,-MAXIMUM PAckAGE
IY
OPERATING'
AREA
r~NEERMALCAPABILITY
..1
r------
r--
r------
1'\ SLOPE= -olA-
Po-600 mW
I"
~O-PE-RrM-IN~G~l--+~"-~--+-~
POINTJ TA = 70°C_-t~_rl_-j
O~~I~~I~I--~"-~~
25 50 75 100 125 150 175
National Semiconductor has adopted these industry-wide
standards. For devices fabricated in a molded package, the
maximum allowable junction temperature is 150°C. For
these devices assembled in ceramic or cavity DIP packages, the maximum allowable junction temperature is
175°C. The numbers are different because of the differences in package types. The thermal strain associated with the
die package interface in a cavity package is much less than
that exhibited in a molded package where the integrated
circuit chip is in direct contact with the package material.
Let us use this new information and our thermal equation to
construct a graph which displays the safe thermal (power)
operating area for a given package type. Figure 5 is an example of such a graph. The end points of this graph are
easily determined. For a 16-pin molded package, the maximum allowable temperature is 150°C; at this point no power
dissipation is allowable. The power capability at 25°C is
1.98W as given by the following calculation:
TEMPERATURE (Oe)
TLiH/9312-5
FIGURE 5. Package Power Capability
vs Temperature
The thermal capabilities of all integrated circuits are expressed as a power capability at 25°C still air environment
with a given derating factor. This simply states, for every
degree of ambient temperature rise above 25°C, reduce the
package power capability stated by the derating factor
which is expressed in mWrC. For our example-a 8JA of
63°C/W relates to a derating factor of 15.9 mW
rc.
FACTORS INFLUENCING PACKAGE
THERMAL RESISTANCE
As discussed earlier, improving any portion of the two primary thermal flow paths will result in an improvement in
overall thermal resistance junction-to-ambient. This section
discusses those components of thermal resistance that can
be influenced by the manufacturer of the integrated circuit. It
also discusses those factors in the overall thermal resistance that can be impacted by the end user of the integrated
circuit. Understanding these issues will go a long way in
understanding chip power capabilities and what can be
done to insure the best possible operating conditions and,
thus, best overall reliability.
P @250C= TJ(max)-TA= 150°C-25°C=1.98W
o
8JA
63°C/W
9-20
Die Size
-G"0
110
... -
Figure 6 shows a graph of our 16-pin DIP thermal resistance
as a function of integrated circuit die size. Clearly, as the
chip size increases the thermal resistance decreases-this
relates directly to having a larger area with which to dissipate a given power.
~i
!'liD
~~5l
"""'-t.........
80
:;!~~
:&Zu
0:
<>.
~Ei
I [is
~~
70
70
'"
3
130
m~5
<>.
i~
~~
90
ffi
1.0
0:
~ 0.9
:&
iii
j!: 0.8
I
DIP
0.7
{§ 0.6
z
I
~ 0.5
A~~
KpVAR
..........
•",
~~
MOLDED jCjjE
fllf
DIE
lk MIL2
11..c"1J2
.,....
500
1000
AIR FLOW (LINEAR FEET/MINUTE)
TLlH/9312-9
CO~
70
Other Factors
2
3
A number of other factors influence thermal resistance. The
most important of these is using thermal epoxy in mounting
ICs to the PC board and heat sinks. Generally these techniques are required only in the very highest of power applications.
Some confusion exists between the difference in thermal
resistance junction-to-ambient (8JtJ and thermal resistance
junction-to-case (8Jcl. The best measure of actual junction
temperature is the junction-to-ambient number since nearly.
all systems operate in an open air environment. The only
situation where thermal resistance junction-to-case is important is when the entire system is immersed in a thermal bath
and the environmental temperature is indeed the case temperature. This is only used in extreme cases and is the exception to the rule and, for this reason, is not addressed in
this application note.
4 5 6 7 8910
OlE SIZE (kMIL2)
TLlH/9312-7
FIGURE 7_ Thermal Resistance vs
Lead Frame Material
Board vs Socket Mount
One of the major paths of dissipating energy generated by
the integrated circuit is through the device leads. As a result
of this, the graph of Figure 8 comes as no surprise. This
compares the thermal resistance of our 16-pin package soldered into a printed circuit board (board mount) compared
to the same package placed in a socket (socket mount).
Adding a socket in the path between the PC board and the
device adds another stage in the thermal flow path, thus
increasing the overall thermal resistance. The thermal capabilities of National Semiconductor's interface circuits are
specified assuming board mount conditions. If the devices
are placed in a socket the thermal capabilities should be
reduced by approximately 5% to 10%.
9-21
S"
c;-
FIGURE 9_ Thermal Resistance vs Air Flow
50
CO
CO
III
o
::J
Co
S"
IIIIIUN
i$
~
a!~!: 110
~t;
~ 1.1
..
~BDARD ~:J:r~i:'~~ AIR
:&Zu
4 5 6 7 8 910
AirFlow
When a high power situation exists and the ambient temperature cannot be reduced, the next best thing is to provide air
flow in the vicinity of the package. The graph of Figure 9
illustrates the impact this has on thermal resistance. This
graph plots the relative reduction in thermal resistance normalized to the still air condition for our 16-pin molded DIP.
The thermal ratings on National Semiconductor's interface
circuits data sheets relate to the still air environment.
4 5 6 7 8 910
Lead Frame Material
jSffi
3
::J
Co
CD
FIGURE 8_ Thermal Resistance vs
Board or Socket Mount
Figure 7 shows the influence of lead frame material (both
die attach and device pins) on thermal resistance. This
graph compares our same 16-pin DIP with a copper lead
frame, a Kovar lead frame, and finally an Alloy 42 type lead
frame-these are lead frame materials commonly used in
the industry. Obviously the thermal conductivity of the lead
frame material has a significant impact in package power
capability. Molded interface circuits from National Semiconductor use the copper lead frame exclusively.
!!iii
"",i"o
TL/H/9312-8
TLlH/9312-6
150
"I"-
DIE SIZE (kMIL2)
FIGURE 6. Thermal Resistance vs Die Size
170
ic
~CKET
~
2
DIE SIZE (kMIL2)
w _
u
zl-
~
~ 10....
60
2
'"
.
""t--..
60
50
0:
80 I--BOAR"
C"
=~~
I [is
~~
~iii
~
90
~fi
w
100
m~ti
~~~
100
u_
CD
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a
8.
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c
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CP
r---------------------------------------------------------------------------------,
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ca
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(3
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en
CP
.E
en
c
=cc
NATIONAL SEMICONDUCTOR
PACKAGE CAPABILITIES
Figures 10 a(ld 11 show composite plots of the thermal
characteristics of the most common package types in the
National Semiconductor Linear Circuits product family. Figure 10 is a composite of the copper lead frame molded
package. Figure 11 is a composite of the ceramic (cavity)
DIP using poly die attach. These graphs represent board
mount still air thermal capabilities. Another, and final, thermal resistance trend will be noticed in these graphs. As the
number of device pins increase in a DIP the thermal resistance decreases. Referring back to the thermal flow chart,
this trend should, by now, be obvious.
RATINGS ON INTERFACE CIRCUITS DATA SHEETS
In conclusion, all National Semiconductor Linear Products
define power dissipation (thermal) capability. This information can be found in the Absolute Maximum Ratings section
of the data sheet. The thermal information shown in this
application note represents average data for characterization of the indicated package. Actual thermal resistance can
vary from ±10% to ± 15% due to fluctuations in assembly
quality, die shape, die thickness, distribution of heat sources
on the die, etc. The numbers quoted in the linear data
.!
CP
"'C
C
~
=cc
CP
D.
D.
CC
• Derate cavity package at 10 mWrC above 25"C; derate molded package
at 11.8 mW
above 25'C.
rc
If the molded package is used at a maximum ambient temperature of 70·C, the package power capability is 945 mW.
Po@ 70·C=1476 mW-(11.8 mWI"C)X (70·C-25·C)
= 945mW
Molded (N Package) DIP'
Copper Leadframe-HTP
Die Attach Board MountStill Air
~
at><
sheets reflect a 15% safety margin from the average numbers found in this application note. Insuring that total package power remains under a specified level will guarantee
that the maximum junction temperature will not exceed the
package maximum.
The package power ratings are specified as a maximum
power at 25·C ambient with an associated derating factor
for ambient temperatures above 25·C. It is easy to determine the power capability at an elevated temperature. The
power specified at 25·C should be reduced by the derating
factor for every degree of ambient temperature above 25·C.
For example, in a given product data sheet the following will
be found:
Maximum Power Dissipation' at 25·C
Cavity Package
1509 mW
Molded Package 1476 mW
.
...zt--
Cavity (J Package) DIP'
Poly Die Attach Board
Mount-Still Air
130
140 .----.--...-""T""T"""1r-r-r-n
110
i!ffi
~ii
"':E
~~5
a!~~
:EZ ..
90
70
~~o
50
"CI
"CI
~National
CD
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C.
;C'
b
g-
Appendix G
Obsolete Product Replacement Guide
O
!-a
Some device types, individual temperature grades and package options have been discontinued. This guide is provided to help
design engineers select and specify an appropriate alternative.
NSC Part Number
Replacement
Note
NSC Part Number
Replacement
Note
ADB1200
DAC1200/1201
LF352
LF13300
LHOOO1
LHOOO5/LHOOO5A
LHOO37
LH0132
LH2011
LH2201A
LH2208
LH2208A
LH24250
LM170/270/370
LM 171/271/371
LM172/272/372
LM173/273/373
LM174/274/374
LM175/275/375
LM216/316
LM388N·2/N·3
LM377N
LM378N
LM379
LM1014
LM1017
LM1019
LM1821S
ADC3711
DAC1265
LM3631
ADC3711
LM4250
LHOOO3
LHOO36
LHOO32
LM11
LM201A
LM208
LM208A
LM11
LM13600N
no replacement
no replacement
no replacement
no replacement
no replacement
LM11
LM388N·1
LM2877P
LM2878P
LM2879T
no replacement
no replacement
no replacement
LM1823
2
2
2
2
2
2
3
2
2
2
2
2
2
2
LM1822
LM1828
LM1848
LM1877N· 1/N·21N·3
LM2003
LM2808
LM2831
LM3011
LM3064
LM3075
TBA120V
TBA440C
TBA510
TBA530
TBA540
TBA560C
TBA920
TBA950·2
TBA970
TBA990
TDA440
TDA2522/23
TDA2530
TDA2530/31
TDA2540/41
TDA2560
TDA2590
TDA3500
LM1823
no replacement
no replacement
LM1877N·9
no replacement
no replacement
LM1851
no replacement
no replacement
no replacement
no replacement
LM1823
no replacement
no replacement
no replacement
no replacement
no replacement
no replacement
no replacement
no replacement
no replacement
no replacement
no replacement
no replacement
no replacement
no replacement
no replacement
no replacement
3
2
2
3
3
3
2
Nole 1: IMPROVED REPLACEMENT: Pin for Pin replacement with superior electrical specifications.
Nole 2: FUNCTIONAL REPLACEMENT: Consult datasheet to determine suitability of the replacement for specific application.
Nole 3: SIMILAR DEVICE with superior performance: Consult datasheet to determine suitability of the replacement for specific application.
9·27
(;
c.
c
n
:CD:c
"CI
~3
CD
2
::J
G)
C
2
2
c:
CD
~
.2
II)
c
CD
E
is
~National
~ Semiconductor
All dimensions are in inches (millimeters)
1ii
(,)
.~
f.
16 Lead Hermetic Dual-In-Line Package (D)
NS Package Number D16C
PIN NO. 1
IDENT
(6.858-7.747)
T.r~~~~~~~
il ~ r- 1
Fl-,::,.::;.:, :~~
JL
0.005
(0.127)
MIN~
I.
0.485
(12.319)
MAX
~:J
..I
0.290-0.320
0.015-0.023
(0.381-0.584)
(2.032)
(7.36&-8.128)
MAX TVP
0.050 ±D.DD5
0 180
(1.270 ±D.127) TVP _ . (4.572)
MAX
0.020-0.060
.Jl-----t----t
0.125-0.200
0.150
0.100 ±0.010
(2.540 ±0.254)
(0.100/(2.540) 8se
TVP REL TO LEADS
1 AND 16)
(3.175-5.080)
(3.810)
MIN
D16CtRE\lH)
18 Lead Hermetic Dual-In-Line Package (D)
NS Package Number D18A
PIN NO. 1
IDENT
0.054
ts:i=lI
...
~ +0.300
40"
0.020-0.060
(0.203-0.381)
0.015-0.023
\--(1.6201---1
(0.381-0.584)
REF
,II
~~
0.125 (0.508-1.524)
(3.115)
MIN
D18A(REV D)
9·28
20 Lead Hermetic Dual-In-Line Package (D)
NS Package Number D20A
(6.B5B-7.B74)
L,-,-,-,""""'-::\r-r:-r-r.'T'""T':"-'-'-'-+.r-o:-r-r.::rl
~
0.050±0.005
(1.270±0.127)
TYP
.
~
I p.290-0.320
--J ("'7.'"36'"6--;;--B.""12"'B)
0.020-0.060
(0.50B-l.524)
~
I
0.00B-0.015
-- (0.203-0.3Bl) •
I--
~-- ~
(0.127)
MIN
~
L
II
-00.015-0.023
(0.381 0.584)
..
0.100±0.010
O.OBO
0.125-0.200
(3.175 5.0BO)
TYP
(2.540±0.254)
(2.032)
MAX
D20AIRfVDI
24 Lead Sidebraze Hybrid Dual-In-line Package (D)
NS Package Number 0240
24
23
22
21
20
1.295
(32.89)
MAX
1.263
(32.081
MAX
19 18
...
17
16
15
14
13
.1
t',
0.060
(1.524)
-I
--7)
(15.36
MAX
../ "
RAD
OPTIONAL
9
10
11
12
~
0.005
(0.127)
MIN
H
----.-rl:=-0.010 +OO'DOOO~
1'0.254 +0.076)
(-0.058
-.l
l
0600+0.015~
~
(+D.381)
15.24 -0.254
SEATING-=>.J""'L.J""'LJ""'LJ""\".r-....r-...
PlANE
I
0.100±0.010
(2.540 ±0.254"·
TYP
PIN NO.1
IDENTIACATION
ON 8RAZE PAD
(OPTIONAL)
0240 (REV FI
9 ..29
•
o ,----------------------------------------------------------------------------------,
C
o
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c
CP
24 Lead (0.600" Wide) Dual-In-Line Metal Package (D)
NS Package Number 0241
E
is
1.360-1.380
(34.54 35.05)
lj
'~
24
.c
a.
23
22
21
20
19
18
17
16
15
14
13
()()()O()()O()()O()()
0.790-0.800
'·"l··' ,~: (-:-:) :c:):c:):(: : :):c:)=c:):c:):(: : :):c:)=c:)~
:c:):(-:_:)
I/'
1
PIN NO.
IOENT
L
0.590-0.610
(14.99 -15.49)
3
4
5
6
7
8
9
10
11
12
f
I
J
2
0.430
(10.92)
J
_I
L
--.-1 L
0.016 -0.019 DlA
(0.406 0.483)
D241{REVBl
28 Lead Hermetic Dual-In-Line Package (D)
NS Package Number 0280
Im n
1.430 MAX
•
II
136.32)
H
~
M
Hun
~
19
18
17
1&
15
!
I
-_--,---------JoLf!
r_---(:-5~~-0)-MA-X
0.605
(15.37)
L--------'_--------l'I--'-T T
PIN 1 IDENTIFICATION ~
~
1
0.485
(12.32)
2
3
"
5
8
7
8
9
10
11
12
13
14
l
~r------======'::~j
t
f:::':'
Jl
0.005 MIN
(0.127)
--I
OQO.Ol0 lYP
('.5AD±O.254}
!~0.023 (t~:}
....
lYP
(0.381-0 ....}
9-30
_I
L--.o.lM! MAIm
r--(1.1431
)
0
D28DtIIEVBl
24 Lead Ceramic Flatpack (F)
NS Package Number F24D
0.090
(2.286)
'--r::
0.010-0.040
(0.254-1.016)
,-
0.030
(0.762)
MIN
(1.143)
MIIX
t
0.250-0.350
(6.350-8.890)
..L--f·lf-II
242322212019181716151413
'~'C= ~::.:
0 t9=
J (: : : : :)
,-
(:~;)
0.003-0.006
(0.076-0.152)
---t
...II.-
1 2 3 4 5 6 789101112
L
0.005
-JdO.019
(0.381-0.483)
(0.127)
MIN
ALLEHOS
F24D(REVD)
12 Lead (0.400" Square Pattern) Metal Can Package (G)
NS Package Number G12B
-~~.O~)-
0545
55
(13.843
OIA
0.141 -0.181
-4.597)
~
- - - -
0.030
(0.762)
=f4
0.030
(0.762)
MIIX
UNCONTROLLED
LEAD DIA
o.500
(
12.70)
MIN
L
0.016-0.019
I"~i0.406 - 0.483)
DIA TYP
(:::) -+00---+1
TYP
Gl28 (REV ct
9-31
o ,-----------------------------------------------------------------------------,
a
Ui
c
~
2 Lead (0.100" Diameter P.C.) TO-46 Metal Can Package (H)
NS Package Number H02A
is
B
'is:
a.
I+---i*- 0.100
i2.iii
T.P.
..........
3 Lead (0.200" Diameter P.C.) Metal Can Package (H)
NS Package Number H03A
-
0.358-11.3 0
(1.-.u:I) DIA
~DIA
.!:!!!:!:!!!. ..... 11.001
.......'
(••191-4.811)
r4
1
.!.!!!..
(1.210)
I
SEATING PLANE
J
0.&00
~
r-
-
MAX
• .01 .....11.
'-ii,iii:iAiiJ
(12.10)
MIN
i
9·32
MAX
(~~)
UNCONTROLLED
_& LEAODIA
DI~ TVP
---
r-----------------------------------------------------------------------------.~
3 Lead (0.200" Diameter P.C.) TO-39 Metal Can Package (H)
NS Package Number H03B
.
~
0.240-0.260
(6.096-6.604)
0.350-0.370
(8.890-9.398)
DIA
0.315-0.335
1(8.00107A8.509)
~
o
0"
~
o
1
(0.889)
0'035Q
MLAX
SEATING
1
0.500
(T
PLANE
~ ~ ~
-II-- (0.406
0.016-0.019 DIA
-0.483)
0.100
(2.540) T.P.
HOJB\REV Ol
3 Lead (0.100" Diameter P.C.) TO-46 Metal Can Package (H)
NS Package Number H03H
8lit
0.Z09-0.Z19 DtA
(5.308-5.5&3)
0.178-0.195
SEATING
I(4.521-4.953)
~~=DIA
P L A N E l m f i 0.080-0.105
~MAX~
=r--
~~.~OU~-~2~.&&=7)
(0.&35)
UNCONTROLLED
LEAD DtA
0.016-0.019
II
(OA06-O.483) ---j !-DIATVP
000
0.500
(1210) MIN
.
o.D30
(0.162)
MAX
0.100
r----I----(2.540) TVP
H03HIREVC)
9·33
~
~
c
3"
CD
o
C
o
"iii
c
CD
E
is
r-------------------------------------------------------------------------~
4 Lead (0.100" Diameter P.C.) TO-46 Metal Can Package.(H)
NS Package Number H04A
B
"i.e
OIA 0.178-0.195
(4.521-4.953)
D.
ii
SEATING
PLANE
8
(:~: =:::~:)
~
~]}
- .
MAX 0.025 ----.l
UNCONTROLLED (0635)
LEAD DIA •
0.016-0.019
(0.406-0.483) --J
000
II--
~0.080-0.105
(2.032 - 2.667)
0.500 MI N
(12.700)
0.030
(0.762) MAX
H04A{REVB)
4 Lead (0.100" Diameter P.C.) Shielded Metal Can Package (H)
NS Package Number H04D
SEATING PLANE
~0.400 __~++
____~1
~~~
(10.16)
MIN
THERMAL SHIELD
(VALOX 420-94V-O)
9-34
H040lREV E}
"tI
=':i
~
8 Lead (0.200" Diameter P.C.) TO-99 Metal Can Package (H)
NS Package Number H08C
c
3CD
::s
~_ _ _--'I+ 0.315 -0.335 DlA
(8.001-8.509)
en
o·
::s
en
0.165-0.185
(4.191 - 4.699)
REFERENCE PLANE
-+-.--
0.100
(2.540) TYP
t
0.115-0.145
(2.921-3.683)
DIA
H08C(REV E)
13 Lead Dual-In-Line Hybrid Package (J)
NS Package Number HY13A
__- -
0.800 MAX _ __
(20.32)
0.140
(3.556) MAX
~L--"""'\...J"1....r"1....--.....r-1....=-~
f
_
1
0'050±0'01~
(1.270±0.254)
TYP
t
SEATING PLANE
0.010
I I 0.100±0.010 (0.254)
---J t-- (2.540±0.254) MIN
TYP
~ 0.018-0.022
(0.457 - 0.559)
HY13A(REV DI
9-35
o ,---------------------------------------------------------------------------------,
C
o
'iii
cC\)
E
24 Lead Dual-In-Line Hybrid Package (J)
NS Package Number HY24A
is
B
l.c
Il..
PIN NO.1 IDENT--H
I
D.D5DiO.01D
~ (1.270±0.254)
TYP
-
II
I
---j
I
D.l0D±0.010
~ (2.540±O.254)
TYP
0.018-0.022
-(0.457-0.5591
HY24AjREVO)
8 Narrow Lead Ceramic Dual-In-Line Package (J)
NS Package Number J08A
0.025
(0.635) HAD
0.220-0.291
(5.558-7.391)
'r.-r-'l"'::'T""'T....-r-r;;r{~
4 \
I
0.290-0.320
I
I~: :$.Ti'~\
0.008-0.012+
95°±5'
(0.203-0.305)" ....
TYP
....[
0.310-0.410
(7.874-10.41)
[..-
1..-
0.010
(0.254)
HAD TYP
0.200
(5.080)
0.015 MIN ....
(0.381)
MAX
G~SS,~~~~~~~.--------~I
SEA~NT "
90.~il.1
~;;jr~
0.055
(1.~~
I....j
BOTH ENDS
It
0.01B±0.003 0.125-0.200
--\ .... (0.457~~.07S) (3.175-5.080)
0.150
(3.810)
MIN
(0.508-1.524)
0.100±0.010
(2.540±0.254) TYP
JOBAIREVJI
9-36
14 Lead Ceramic Dual-In-Line Package (J)
NS Package Number J14A
0.785
1~------(19.939)------~-~11
MAX
t
0.025
(0.635)
RAD
0.220-0.310
(5.588-7.874)
1......r:-T-r::T'T";"'I"""r."T"""T7T"T~--I~
0.290-0.320
(7.366-8.128)
0.180
--MAX
(4.572)
0.060 ±0.005
-I
I,"
L
0.018 ±0.003
(0.457 fO.076)
0.100 ±0.010
(2.540 ±0.254)
-11-
0.125~.200
(3.175-5.080)
0.150
(3.81)
MIN
J14A (REV G)
16 Lead Ceramic Dual-In-Line Package (J)
NS Package Number J16A
0.025
(0.635)
RAD
0.005-0.020
(0.127 -0.508)
RAD TYP
r
~~!-(7.366
.--=!.
0.290-0.320
0.005
95°+5°
-
MAX
I
--l
0.310 _ 0.410
(7.874-10.41)
':)
M
(5
__
~ Bt~~~~~~~~~~!I~T-~~ -+__
8.128)
0.180
(4.572)
0.200
--l
0.008-0.012
(0.203-0.305)
I
I--
J
-L
0.080
(2.~~
BOTH
ENOS
J16A(REVK)
9-37
o
C
o
"iii
c
CP
r-----------------------------------------------------------------------------------------~
18 Lead Ceramic Dual-In-Line Package (J)
NS Package Number J18A
E
is
0.020
(0.508) HAD MAX
B
-t
ia.
0.310
(7.B74) MAX
"mT:;"M"';'T~~-r.T"1":~U
0.005 MIN-(0.127)
J!1!!!!..MAX
(5.080)
- I 0.290-0.320 t-I (1.366-B.128) I
0.020 - 0.060
(0.508-1.524)
0.125-0.200
(3.175-5.080)
r:~GlASSSEALANT
~tll
(~~)
j
.
95'±~
0.310 - 0.410
(7.874-10.41)
L
0.008-0.012
(0.203-0.305)
86'94'
TIP
L
0.100±0.010
(2.540±0.254)
JP
Lj
0.01B±0.003
(0.457±0.076) TIP
0.098
(2.489)
MAX
BOTH ENDS
J18A(REVLI
20 Lead Ceramic Dual-In-Line Package (J)
NS Package Number J20A
0.9B5
....-----------(25.019)
MAX
0.180
(4.572)
MAX
0.055± 0.005
(1.397±0.127)
0.290-0.320
(7.366-8.128)~
----------~
GLASS SEALANT
'J
0.200
(5.080)
MAX
86'9
--I\4-.,:0::;.0:;=08:...-.::0.~01:=:2
(0.203 - 0.305)
I.-(7.874-10.41)
0.310-0.410
0.060
(1.524)
MAX
BOTH ENDS
0.125-0.200
(3.175-5.080)
IL
II
t
0.01B±0.OO3 __
(0.457±0.076)
0.100±0.010
(2.540±0.254)
J20A(REVM)
9-38
.-----------------------------------------------------------------------------,
24 Lead Ceramic Dual-In-Line Package (J)
NS Package Number J24A
~
c;"
!!.
.
C
U90
(lZ.766) _ _ _ _ _ _ _ 1
~,
1'-T:'1-r: T"T-: T'"T":'T-r.~:-nr.T-r: -r_r:;'I" T:; rT: 'T" 'I": :r" ' "'-j""
0.005
95" '5"
I_
::s
o
0"
::s
o
P""n'.~.w .~. . ~.~~. "J ,
0.008-0.012
0.685 -0.060
r--(
CD
0.514-0.526
0.OlO-0.055
(0.762-1.l97)
RAD TVP
0.590-0.6Z0 ~
3"
0.600
i~!'
0.025
(0.6l5)
RAD
~
tG.6l5)
17.40 -1.524
_
I
.-.~
0.098
0.125-0.200
(l.175-5.080)
(2.489)
MAX
MIN
0.150
(l.810)
MIN
J<'4AIREVH)
24 Lead Ceramic Dual-in-Line Package (J)
NS Package Number J24F
1.290
1 - - - - - - - - ( 3 2 . n ) MAX------_~
~RAD
(0.835)
0.030-0.055
(0.76Z-I.397)
t
t
~
:r
0.080 ±D.DD5
(1.524 ±D.I21) TVP
I
0.020-0.070 RAD TVP
(0.508-1.718)
(~::::=::!::)
r
I
~~0.,~8°r---1H;~~~~~~~~~~;;~;;~~--~~~~~:) ~
-~~r-·~~~r~I~Ir_~'~I~~r~~~Ir_~,~I."r_~~=TM~AFx
J
f.
H - - -0-",1-25-
(3~1~)
.
95°±5"
.
~
1'"-' 0.310-0AIO I ~:p03-Q.305)
f: (J.814-IOAt)--I
J24F(RlVGI
9·39
(I)
c
o
";)
c
CD
E
28 Lead Ceramic Dual-In-Line Package (J)
NS Package Number J28A
is
1--------(3~~~1 MAX
B
"l
.c
a.
0.600
115.2401
--------\
'r-==~:U!:.L.=..L::U!:!J-=.J:~:U.::L=..J.:::&...I'~..;_ _-+MAXGLASS
D.D25
(0.6351
AAD
0.514-0.526
~-r.~or~~TT~r.T~rr.~or~~~~~~~' 1
113.06 13.381
0.030-0.055
(0.162-1.3911
RAD TVP
0.180
(4.5121
MAX
0225
(5.1151
~~~;;~9;~~SF~~~;;~~~~~~~
h
--I~
0.125
1~:~51
0.018 -O.ODZ
(0.451 -0.5081
0.060-0.100
11.524-2.5401
40 Lead Ceramic Dual-In-Line Package (J)
NS Package Number J40A
I--------;------I!~~:I------------I
MAX
0.025
(0.63'1 AAD
O.030-tJ.055
~I
RADTYP
022.
('.11&1
MAX
0.018 i 0.002 _ II _
(0.4'1' 0.0511 --11-TVP
~I
(2.540 ! a.2641
TVP
--j
0.098
(2.4881
MAX (80TH ENOSI
J«IA(REVIQ
9-40
r-----------------------------------------------------------------------------,
8 Lead (0.150" Wide) Molded Small Outline Package (M)
NS Package Number M08A
0.lB9-0.197
(4.BOO-5.004)
B
7
6
c
3'
I
CD
:::I
5
UI
0'
i~
0
:::I
UI
0.22B-0.244
q '- ..!!:!!!I! MAX
(5.791 -6.,98)
/ " (0.254)
LEAD NO. 1
10ENT
1r
1~:~~~=::~:)
J!J!1!!..=l!J!! x 45'-..
(0.254-0.50B)
1---
r
(~::=~::~)
\
ALL LEAO TIPS _
..
~-fT
4
3D'
TYP
0.004-0.010
(0.102-0.254)
0.050
(1.270)
0.016-0.050
~~~L ~~J
TYP ALL LEADS
3
L--~d t
t (~:~!)
t
L~'~TYP
t
-=fALL
LEADS
.r--..IJ
0.004, ,
T
(0.102)
2
0.053 - 0.069
(1.346-1.753)
,
B' MAX TYP
r
1
J
TYP
SEATING
PLANE
O.OOB TYP
(0.203)
(0.356-0.508)
_
_{REVH,
14 Lead (0.150" Wide) Molded Small Outline Package (M)
NS Package Number M14A
_ _ _ 0.335-0.344
~
-IA A 3"3'~ A &1
-t
0.228 -0.244 (
(5.791-6.1~B)
30'
TYP
f\
1':\
!,~V
LEADI~~N~ ~~ ~ ~ ~ ~ ~ ~_~_
t
1234567
.!!!!!!.MAX
(0.254)
1r
0.150-0.157
(3.Bl0 3.988) -
0.010-0.020 45'
(0.254 0.50B) x
B' MAX TYP
rr---I,
~J!:
111..
+
~j l-=:t--:
O.OOBe
(0.203-0.254)1·-~
TYP ALL LEADS
0.004
(0.102)
ALL LEAD TIPS
0.053 -0.069
(1.346 1.753)
t
ALL LEADS
SEATING
PLANE
,
t t
0.014
(0.356)
0.016-0.050
(0.406 1.270)
TYPALL LEAOS
~
~J I
(1.270)
TYP
-
- -
JL
0.004-0.010
(0.102-0.254)
- ---.-1
_11:J-0.020 TYP
(0.3li§-O.50B)
0.008 TYP
(0.203)
M14A\AEVI1I
9-41
~
:::r
~
0'
!!.
o
C
.i
i
r---------------------------------------------------------------------------------,
14 Lead (0.300" Wide) Molded Small Outline Package (M)
NS Package Number M14B
E
2i
'5
I
1
0.394-0.419
(10.01-10.641
.!!!!!..(0.6861
~H~~
0.009-0.013
r (~::::=~:::lt
1
mALL LEADS ~
.!!:!!!!.
x45'
r~m
*
(0.4321
t
ALL LEADS
~ . ~JjC±
(0.1021
ALL LEAD
0.093-0.104
(2.362 -2.6421
,
0.037 -0.044
(0.940-1.1181
Trl
~J
(1.2701
(0.762-1.2701
TYP ALL LEADS
~
SWING
PLANE
t
JL~m
.-
I
0.004-0.012
(0.102-0.3051
(0.356-0.4831
TYP
TIPS
M14BIAEVDi
16 Lead (0.150" Wide) Molded Small Outline Package (M)
NS Package Number M16A
--r
.
1
L
(::~:=::!:I
~X45'
(0.254 -0.5061
::1::
TYP ALL LEADS
o.lI53-o.t169
(1.346-1.7531
8' MAX TYP
ALL LEADS
TJ Lj~,
0.0114
1-.--
t
t
0014
_._
(0.3581
TVP ALL LEADS
'J$8L.t=1iAriiFiibiLJ
JL j' L
0.004-0.010
~
~
TYP
ii."i02i
.
(1.2701
9-42
t
PLANE
O.014-0.020TYP,
(0.356-0.5081
~TYP
(0.203)
ALL LEAD TIPS
SEATING
MI6AlReVHi
,-----------------------------------------------------------------------------,
20 Lead (0.300" Wide) Molded Small Outline Package (M)
NS Package Number M20B
~
:::r
U1
~
c
3'
CD
:;,
!e.
o:;,
UI
:m=;:;::;:;::;;;::::::;::;::;;:;:::;:;:::;:;:::::;:;::::;:;~
2
3
4
5
6
7
B
9
lo-r
~MAX
10.254)
0.093 -0.104
12.362 -2.642)
8 MAX TYP
0
0.00910.013
10.229-0.330)
TYP ALL LEADS
~~==0.OO=4=/==S;=~~"ll ~oL'6;0 'S050
ALLI~O:~IPS
-10.406-1.270)
TYP ALL LEADS
+
~ 0.004-0.012
10.102-0.305)
L ~=_~_~-~-~-=--==-==-=""===~
f I~!::) J I_~
_I [~2:.:N:yp
.
11.270)
TYP
JL
SEAnNG
10.356 -0.5OB)
..!!..!!!!!TYP
(0.203)
M20B (REV F)
8 Lead Molded Dual-In-Line Package (N)
NS Package Number N08E
~7
0.092 DIA
(2.337)
0.032±0.005
(0.813 ± 0.127)
RAD
PIN NO.lIDENT~
PIN NO.1 IDENT
1
DPTIDN 2
95'±5'
D.045±D.015
(1.143±0.381)
NOBE(REV F]
9-43
o ,---------------------------------------------------------------------------------,
C
.~
5i
14 Lead Molded Dual-In-Line Package (N)
NS Package Number N 14A
E
C
1j
.~
.c
a.
0.092 OIA ~ MAX
(2.337)
(0.762) IIfI'TH
OPTION 1
OPTION 02
0.135±0.OO5
(3.429 ±0.127)
0.3011-0.320
(7.620-8.128)
0065
(l'r
4'TYP
---1)
OPTIONAL
0.020
(0.508)
MIN 0.125-0.150
(3.1711-3.810)
~
. . l--
f
90'±4' TVP
II
I
I
0.014-0.023 TYP- _
(0.356 -0.584)
- ..
_
I
0.050±0.010 TYP
(1.270-0.254)
0.075±0.015
(1.905±0.3811
0.100±0.010 TVP
(2.540±0.254)
-,
L95'
~
Is.
~TYP
~tOO
(0.203-0.406)
I
.. ~~::.
0.280 __
(7.112)
MIN
0.325
+1.016)
(8255
. -0.381
N14AtREV fl
16 Lead Molded Dual-In-Line Package (N)
NS Package Number N16A
0.092
(2.337)
DIA NOM
(2X)
PIN NO.1 IDENT
~
••••
0.280
(7.112)
MIN
0.300-0.320
. 0.030
---
(7.620-8.128)
~
(~~:)
r~ 'J I-- J
","-W.
I.
0.325
(
--l-(0.229-0.3811
~:~~·1
+1 016)
8255 -O:aBl
0.075 to.015
(1.905 to.3811
0.100±0.010
(2.540 '0.254)
NI6A(REVE)
9·44
16 Lead Molded Dual-In-Line Package (N)
NS Package Number N16E
0.032±0.005 ~5
14
(0.813±0.127)
R
PIN NO.lI0ENT~
~
0'280~
(7.112)
1
MIN
0.030
0.300-0.320
---
(0.762)
MAX
t==JLi
~
1I~-
I
..
95"±5"
~~:~~~
•
I
0.009-'0.015
t
(0.229-0.381)
0.030+0.015
0.325
(,
+1016)
,8.255 -0:381
JI-- J
1--11
(0.762±0.381)
0.018+0.003
~ I-- (0.457±0.076)
0.125-0.140
(3.175 - 3.556)
MIN
0.100±0.010
(2.540 ±0.254)
TYP
N16E{REV E)
18 Lead Molded Dual-In-Line Package (N)
NS Package Number N 18A
0.843-0.870
(21.41-22.10)
0.092
- x0.030
-(2.336)
(0.762)
15
NOM
MAX
DEEP (2 PLCS)
14
13
-:-:-j
12
11
10
f0.250 .0.005
PIN NO. llDENT
(6.350 ±0.127)
~
~;:r=;:;;;:::;:;:;::;::;::;:::;;;:;:::;:::;:::;:;:;::r.;:I--1.
0'280~
(7.112)
MIN
'
0.300:"'0.320
Ir: I
0 1
-: ::
t.:"'
I·
2
OPTION 2
0.325
~:~~
·1
(8.255 +1.016)
~
-0.381
1J
0.025 ±0.015
I--
(0.635 ±0.3811
0.100 ±0.lIl0
(2.540 ±0.254)
TVP
90;':p4"f
0.120
(0.508)
0.125-0.140 I MIN
(3.175-3.556)
N18A(REVE)
9·45
o .---------------------------------------------------------------------------------,
C
o
'iij
C
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20 Lead Molded Dual-In-Line Package (N)
NS Package Number N20A
E
is
'fj
1.0Il-I.040
(25.7l-26.42)
0.092 X o.olO
(2.l37 X 0.762)
MAXDP
'~
0.ol2 ±0.005
(0.813±O'127)~D
19
RAD
\F====~~±I='~I~B=='5~=14~1~3~1=2~1~1~___r
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0.260 '0.005
(6.604 ±0.127)
PIN NO. I IDENT
~ (~:~~:)~
PIN NO.IIDENT~
~~mmT.n~~mm~~
MIN
OPTION 2
0.300-0.320
~
O.llO 0.005
0.065
(1.651)
~n.Tlrrrll.n+orn~~
0.009-O.01~J
I
+D.04o
0.l25 -0.015'
-90·.0.004'
(0.229-O.l81)
TYP
0.060 '0.005
(1.524.0.127)
I
t-
0.01B±0.003
(0.457> 0.076)
~~
L
0.125-0.140
(l.175-3.556)
f
I
0.020
(0.508)
MIN
(8.255 +1.016)
~
-0.381
N20A(REVGI
24 Lead Molded Dual-In-Line Package (N)
NS Package Number N24A
I
1.243-1.270
1--------(31.57-32.26)------o·~
13
0.062
(1.575)
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0
PIN NO. IIOENT
r:
I
0.540 '0.005
J~'"
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(~i~)
_0._03_0
(0.762)
MAX
!F(l5.24-15.748)
95"'5"
0.625
~::~:
I
2
DOTTED OUTLINES
REFLECT ALTERNATE
MOLDED BODY CONFIGURATION
0.580 ~
0.600-0.620
1_
11
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r - ( 1 5 875 +D.635)~
. -11.381
0.075
(1.905)
L~___+I-----"':":':""++--'T1--t-------'
0.009-0.015
~
(0.229-0.381)
0.075 ±0.015
(1.905 ±0.381)
6"94"
~
f--
TYP
0.015
_11_ 0.018.0.0 0.125-0.140 (0.381)
0.100 ±0.010l1 (0.457 .0.076) (3.175-3.556) MIN
(2.540 .0.254)
N24A (REV EI
9-46
24 Lead Skinny Dual-In-Line Package (0.300" Centers Molded) (N)
NS Package Number N24C
1.243-1.270
~------------·(=3~1.=57~-~32~.2=6)------------~
0.092
MAX
(2.337)
(2 PLS)
f
PIN NO.1
IDENT
D.260±0.OD5
(6.6D4±0.127)
I
OPTION 2
0.062
(1.575)
0.300-0.320
HAD
~'="'I
0.009-0.015
(0.229-0.381)
D.04D
(1.016)
TYP
0.065
(1.651)
-r--J
0.075±0.015
(1.9D5±0.381)
(8255+ 1.016)
~ .
-0.381
.
I
IN24C(REVF)
28 Lead Molded Dual-In-Line Package (N)
NS Package Number N28B
PiN NO.1 10ENT
1.------------ 1.393-1.420
___________-+1
(35.38-36.07)
0.145-0.210
___
'_~_5'334)
(0.229-0.381)
0.050±0.015
(1.270±0.381)
)
t--
0.125-0.145
(3.175-3.683)
N288(AEVEt
9·47
o
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r-----------------------------------------------------------------------------,
40 Lead Molded Dual-In-Line Package (N)
NS Package Number N40A
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is
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1
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(1.67SI
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PIN NO. llDENT
95"±5"
~ D.62S~::::
(16.175 ~:~::J
---I
0.075'0.015
(1.905 ±0.3811
N'DA(REYEI
20 Lead Plastic Chip Carrier (V)
NS Package Number V20A
(1.1431
D.04if5
x45'
I
18
D.080
(2.0321
~_-r-r'---t-L.. ~~~E~~:L
b~
~
15'
VIEWA·A
4 SPACES AT
0.050
(1.270)
0.31D -D.33O
(7.874-8.382)
.(CONTACT DIMENSION)
0.026-0.032
(0.660-0.8131
TVP
0.D05 -0.015
(0.127-0.3811
I1
.
0.013-0.018
(0.330-0.4571
TVP
"0.020
(0.5081
j~:~~~~~~~~~~~~
PIN NO.1
10ENT
0.032 _ 0.D4D
(0.813-1.016)
MIN
0.385 -0.395
4 - (9.719-10.031
SQUARE
V2OA,REV J)
9·48
,-----------------------------------------------------------------------------,
~
::T
28 Lead Plastic Chip Carrier (V)
NS Package Number V28A
"<
til
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c
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til
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til
0.165-0.180
(4.191-4.572)
~
.
t t
0.104-0.118
(2.642 -2.997)
V26A (REV G)
16 Lead Ceramic Package (W)
NS Package Number W16A
0.0.0 -0.080
(1.270-2.032)
--J roI I
0.004-0.006 TYP-t!
(0.lo2-0.152)
II
0.371 - 0.390
(9.423 - 9.906)
0.007-0.018
(0.178-0.457jTYP
I 1t
0.050±0.005 TYP
(1.270 ±0.127)
--r--I-o.ooo MIN TYP
00.370
(6.350-9.398)
I
~~~~~.---'
. - 16151413121110 9
f
0.300
(7.620)
MAX ~LASS
,
0.245 -0.275
(6.223 -6.985)
1
__ ,2345678
,
t
----1~I}JI
DETAIL A
PIN NO.1
10ENT
0.026 -0.040 TYP
(0.660 -1.016)
-
0.250-0.370
(6.350-9.398)
-Jl
-+
0.015-0.019
(0.381-0.482)
TYP
9-49
W16A(REV H)
lrI
-
DETAIL A
0.008-0.012
(0.203-0.305)
o ,---------------------------------------------------------------------------------,
C
o
"iii
c
CD
E
3 Lead TO-92 Molded Package (Z)
NS Package Number Z03A
is
EJECTION MARK
0.065xO.015
(1.651 xO.3811
li
DEEP MAX
£
Q.
· ~I
I----.,
L
i
0.175 -0.185
(4.445 -4.6991 I
SEATING PlANE
.
L
t
0.175-0.185
(4.445-4.6991
5'
i
I.L
L - - _.J
----L
~
O.SOO
0.025
(l~fl
nnnUNC~?!~~LED
L - - UUU
LEAD DIA
Jlit-- (:::~:=:::~:I -.11.~
0.045-0.055
(1.143-1.3971
2 PLCS
.l!:!!!!..
TIP
0.0145 -0.0155
(0.3683-0.39371
8EFORE LEAD
FINISH
O.045-D.D55
'B"~r
\ It I
0.135-0.145
(3.429 - 3.6831
\.# '"
10'
10'
Z03A (REV E)
9-50
~National
a
Semiconductor
Bookshelf of Technical Support Information
National Semiconductor Corporation recognizes the need to keep you informed about the availability of current technical
literature.
This bookshelf is a compilation of books that are currently available. The listing that follows shows the publication year and
section contents for each book.
Please contact your local National sales office for possible complimentary copies. A listing of sales offices follows this
bookshelf.
We are interested in your comments on our technical literature and your suggestions for improvement.
Please send them to:
Technical Communications Dept. M/S 16300
2900 Semiconductor Drive
P.O. Box 58090
Santa Clara, CA 95052-8090
AlS/AS lOGIC DATABOOK-1987
Introduction to Bipolar Logic • Advanced Low Power Schottky • Advanced Schottky
ASIC DESIGN MANUAL/GATE ARRAYS & STANDARD CEllS-1987
SSI/MSI Functions. Peripheral Functions 0 LSIIVLSI Functions. Design Guidelines. Packaging
CMOS lOGIC DATABOOK-1988
CMOS AC Switching Test Circuits and Timing Waveforms. CMOS Application Notes. MM54HC/MM74HC
MM54HCT/MM74HCTo CD4XXX. MM54CXXX/MM74CXXX. Surface Mount
DATA COMMUNICATION/lAN/UART DATABOOK-Rev. 1-1988
LAN IEEE 802.3 • High Speed Serial/IBM Data Communications. ISDN Components. UARTs
Modems. Transmission Line Drivers/Receivers
DISCRETE SEMICONDUCTOR PRODUCTS DATABOOK-1989
Selection Guide and Cross Reference Guides. Diodes. Bipolar NPN Transistors
Bipolar PNP Transistors 0 JFET Transistors. Surface Mount Products. Pro-Electron Series
Consumer Series. Power Components. Transistor Datasheets • Process Characteristics
DRAM MANAGEMENT HANDBOOK-1988
Dynamic Memory Control 0 Error Detection and Correction. Microprocessor Applications for the
DP8408A/09A117/18/19/28'/29· Microprocessor Applications for the DP8420Al21A122A
F100K DATABOOK-1989
Family Overview. F100K Datasheets • 11 C Datasheets • 10K and 100K Memory Datasheets
DeSign Guide. Circuit Basics'. Logic Design. Transmission Line Concepts. System Considerations
Power Distribution and Thermal Considerations. Testing Techniques. Quality Assurance and Reliability
FACTTM ADVANCED CMOS lOGIC DATABOOK-1989
Description and Family Characteristics. Ratings, Specifications 'and Waveforms
Design Considerations • 54AC174ACXXX • 54ACT174ACTXXX
FAST® ADVANCED SCHOTTKY TTL lOGIC DATABOOK-1988
Circuit Characteristics • Ratings, Specifications and Waveforms. DeSign Considerations. 54F/7 4FXXX
FAST® APPLICATIONS HANDBOOK-REPRINT
Reprint of 1987 Fairchild FAST Applications Handbook
Contains application information on the FAST family: Introduction. Multiplexers. Decoders. Encoders
Operators. FIFOs • Counters. TTL Small Scale Integration. Line Driving and System Design
FAST Characteristics and Testing • Packaging Characteristics • Index
GENERAL PURPOSE LINEAR DEVICES DATABOOK-1989
Continuous Voltage Regulators. Switching Voltage Regulators. Operational Amplifiers. Buffers • Voltage Comparators
Instrumentation Amplifiers. Surface Mount
GRAPHICS HANDBOOK-1989
Advanced Graphics Chipset. DP8500 Development Tools. Application Notes
INTERFACE DATABOOK-1988
Transmission Line Drivers/Receivers. Bus Transceivers. Peripheral Power Drivers. Display Drivers
Memory Support • Microprocessor Support. Level Translators and Buffers. Frequency Synthesis. Hi-Rei Interface
LINEAR APPLICATIONS HANDBOOK-1986
The purpose of this handbook is to provide a fully indexed and cross-referenced collection of linear integrated circuit
applications using both monolithic and hybrid circuits from National Semiconductor.
Individual application notes are normally written to explain the operation and use of one particular device or to detail various
methods of accomplishing a given function. The organization of this handbook takes advantage of this innate coherence by
keeping each application note intact, arranging them in numerical order, and providing a detailed Subject Index.
LS/S/TTL DATABOOK-1987
Introduction to Bipolar Logic • Low Power Schottky. Schottky. TTL. L()w power
MASS STORAGE HANDBOOK-1988
Winchester Disk Preamplifiers • Winchester Disk Servo Control. Winchester Disk Pulse Detectors
Winchester Disk Data Separators/Synchronizers and ENDECs. Winchester Disk Data Controller
SCSI Bus Interface Circuits • Floppy Disk Controllers
MEMORY DATABOOK-1988
PROMs, EPROMs, EEPROMs • Flash EPROMs and EEPROMs • TTL I/O SRAMs
ECL I/O SRAMs • ECL I/O Memory Modules
.
MICROCONTROLLER DATABOOK-1988
COP400 Family • COP800 Family. COPS Applications. HPC Family. HPC Applications
MICROWIRE and MICROWIRE/PLUS Peripherals • Display/Terminal Management Processor (TMP)
Micro(;ontroller Development Tools
PROGRAMMABLE LOGIC DATABOOK & DESIGN MANUAL-1989
Product Line Overview. Datasheets • Designing with PLDs. PLD Design Methodology. PLD DeSign Development Tools
Fabrication of Programmable Logic. Application Examples
REAL TIME CLOCK HANDBOOK-1989
Real Time Clocks and Timer Clock Peripherals. Application Notes
RELIABILITY HANDBOOK-1986
Reliability and the Die. Internal Construction. Finished Package. MIL-STD-883 • MIL-M-3851 0
The Specification Development Process. Reliability and the Hybrid Device. VLSIIVHSIC Devices
Radiation Environment. Electrostatic Discharge. Discrete Device. Standardization
Quality Assurance and Reliability Engineering. Reliability and Documentation. Commercial Grade Device
European Reliability Programs. Reliability aM the Cost of Semiconductor Ownership
Reliability Testing at National Semiconductor. The Total Military/ Aerospace Standardization Program
883B/RETSTM Products. MILS/RETSTM Products. 883/RETSTM Hybrids. MIL-M-38510 Class B Products
Radiation Hardened Technology. Wafer Fabrication. Semiconductor Assembly and Packaging
Semiconductor Packages. Glossary of Terms. Key Government Agencies. AN/ Numbers and Acronyms
Bibliography. MIL-M-3851 0 and DESC Drawing Cross Listing
SERIES 32000 MICROPROCESSORS DATABOOK-1988
Series 32000 Overview • Central Processing Units • Slave Processors. Peripherals. Board Level Products
Development Systems and Tools. Software Support. Application Notes. NSC800 Family
SPECIAL PURPOSE LINEAR DEVICES DATABOOK-1989
Audio Circuits • Radio Circuits • Video Circuits. Motion Control Circuits. Special Function Circuits
Surface Mount
TELECOMMUNICATIONS-1987
Line Card Components • Integrated Services Digital Network Components • Modems
Analog Telephone Components • Application Notes
~ National
~ Semiconductor
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(Continued)
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