1989_National_Embedded_System_Processor_Databook 1989 National Embedded System Processor Databook
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Embedded
System
Processor
Databook
1989 Edition
Embedded System Processor
Overview
II
CPU-Central Processing Units
•
Slave Processors
II
Peripherals
Development Systems and
Software Tools
Physical Dimensionsl Appendices
iii
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v
Table of Contents
Alphanumeric Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vii
Section 1 Embedded System Processor Overview
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Key Features of National's Embedded System Processors. . . . . . . . . . . . . . . . . . . . . . . . .
Component Descriptions ......................................................
Hardware Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Systems and Software Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Support Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-3
1-4
1-5
1-6
1-7
1-8
Section 2 CPU-Central Processing Units
NS32GX32-20, NS32GX32-25, NS32GX32-30 High-Performance 32-Bit Embedded
System Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS32CG 16-10, NS32CG 16-15 High-Performance Printer/Display Processors . . . . . . . .
2-3
2-96
Section 3 Slave Processors
NS32381-15, NS32381-20, NS32381-25, NS32381-30 Floating-Point Units..........
NS32081-10, NS32081-15 Floating-Point Units...................................
3-3
3-32
Section 4 Peripherals
NS32202-10 Interrupt Control Unit............................... ...............
NS32203-10 Direct Memory Access Controller .. .. . . .. .. .. .. . . . .. . .. .. .. . .. . .. . ..
NS32CG821 microCMOS Programmable 1M Dynamic RAM Controller/Driver........
HPC16083/HPC26083/HPC36083/HPC46083/HPC16003/HPC26003/HPC36003/
HPC46003 High-Performance Microcontrollers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DP8510 BITBLT Processing Unit ...............................................
DP8511 BITBLT Processing Unit (BPU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-3
4-28
4-57
4-58
4-59
4-60
Section 5 Development Systems and Software Tools
NS32CG16 ISE Development Tool. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SYS32/30 PC-Add-I n Development Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Series 32000 GENIX Native and Cross-Support (GNX) Development Tools (Version 3)
Series 32000 GNX-Version 3 C Optimizing Compiler ..............................
Series 32000 GNX-Version 3 Fortran 77 Optimizing Compiler. . . . . . . . . . . . . . . . . . . . . . .
Series 32000 GNX-Version 3 Pascal Optimizing Compiler. . . . . . . . . . . . . . . . . . . . . . . . . .
5-3
5-10
5-16
5-21
5-25
5-29
Section 6 Physical Dimensions/Appendices
Glossary of Terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bookshelf
Distributors
vi
6-3
6-1 0
Alpha-Numeric Index
DP8510 BITBLT Processing Unit ........................................................... 4-59
DP8511 BITBLT Processing Unit (BPU) ...........•.......................................... 4-60
HPC16003 High-Performance Microcontroller ....•.•...................................•..... 4-58
HPC16083 High-Performance Microcontroller ............................................•.•. 4-58
HPC26003 High-Performance Microcontroller ................................................ 4-58
HPC26083 High-Performance Microcontroller ........•........•..............•............... 4-58
HPC36003 High-Performance Microcontroller ................................................ 4-58
HPC36083 High-Performance Microcontroller ...........................•.....•......•....... 4-58
HPC46003 High-Performance Microcontroller ....•........................................... 4-58
HPC46083 High-Performance Microcontroller ................................................ 4-58
NS32CG161SE Development Tool ........................................................... 5-3
NS32CG16-10 High-Performance Printer/Display Processor ................................... 2-96
NS32CG16-15 High-Performance Printer/Display Processor .......•........................... 2-96
NS32CG821 microCMOS Programmable 1M Dynamic RAM Controller/Driver .................... 4-57
NS32GX32-20 High-Performance 32-Bit Embedded System Processor ........................... 2-3
NS32GX32-25 High-Performance 32-Bit Embedded System Processor ........................... 2-3
NS32GX32-30 High-Performance 32-Bit Embedded System Processor ........................... 2-3
NS32081-10 Floating-Point Unit ............................................................ 3-32
NS32081-15 Floating-Point Unit ............................................................ 3-32
NS32202-10 Interrupt Control Unit ........................................................... 4-3
NS32203-10 Direct Memory Access Controller ............................................... 4-28
NS32381-15 Floating-Point Unit ............................................................. 3-3
NS32381-20 Floating-Point Unit ................................•............................ 3-3
NS32381-25 Floating-Point Unit ..........................•......•.......•................... 3-3
NS32381-30 Floating-Point Unit .•...........•....................•.......................... 3-3
Series 32000 GENIX Native and Cross-Support (GNX) Development Tools (Version 3) ............ 5-16
Series 32000 GNX-Version 3 C Optimizing Compiler .......................................... 5-21
Series 32000 GNX-Version 3 Pascal Optimizing Compiler ...................................... 5-29
Series 32000 GNX-Version 3 Fortran 77 Optimizing Compiler ................................... 5-25
SYS32/30 PC-Add-In Development Package ................................................ 5-10
vii
Section 1
Embedded System
Processor Overview
II
Section 1 Contents
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Key Features of National's Embedded System Processors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Component Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Systems and Software Chart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Support Devices ...................................................................
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Introduction
National's Embedded System Processor™ family offers the
most complete solution to your 32-bit embedded processor
needs via CPUs, slave processors, system peripherals,
evaluation/development tools and software.
In short, the degree to which the processor can maximize
software utility directly affects the cost of a product, its reliability, and time to market. It also affects future software
modification for product enhancement or rapid advances in
hardware technology.
We at National Semiconductor firmly believe that it takes a
total family of Embedded System Processors to effectively
meet the needs of an embedded system designer.
Our approach has been to define an architecture addressing these software issues most effectively. National Semiconductor's Embedded System Processor family combines
32-bit performance with efficient management of a large address space. It facilitates high-level language program development and efficient instruction execution. Floating-point
is integrated into the architecture.
This Databook presents technical descriptions of our 32-bit
Embedded System Processors, slave processors, peripherals, software and development tools. It is designed to be
updated frequently so that our customers can have the latest technical information on the Embedded System Processor.
But we didn't stop there. Advanced architecture isn't
enough. Our total product system solution approach includes the hardware, software, and development support
products necessary for your design. The evaluation board,
in-system emulator, software development tools, and third
party software are available now for your evaluation and
development.
When we at National Semiconductor began designing the
Embedded System Processor family, we decided to support
an architecture that addressed the needs of embedded design. We chose to take the time to design it properly so that
optimal system cost/performance, high system integration,
and total system solutions were addressed. Working from
the top down, we analyzed the issues and anticipated the
embedded computing needs. The result is an advanced and
efficient family of Embedded System Processors.
The Embedded System Processor is a solid foundation from
which National Semiconductor can build solutions for your
future designs while satisfying your needs today.
Software productivity has become a major issue in embedded system product development. In embedded systems
this issue centers around the capability of the processor to
maximize the utility of software relative to shorter development cycles, under the constraints of lower cost and higher
performance.
For further information please contact your local sales office.
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accelerating customized CPU instructions that would otherwise be implemented in software. At the same time, software compatibility is maintained, i.e., it is always possible to
substitute lower-cost software modules in place of the slave
processor.
Some of the features that set the Embedded System Processor family apart as the best choice for 32-bit designs are
as follows:
FAMILY OF EMBEDDED SYSTEM PROCESSORS
Embedded System Processors are more than just a single
chip set, it is a family of chip sets. By mixing and matching
CPUs with compatible slave processors and support chips,
an embedded system designer has an unprecedented degree of flexibility in matching price/performance to the end
product.
FLOATING-POINT SUPPORT
National offers a complete set of floating-point solutions.
This includes the NS32081 Floating-Point Unit, and the
NS32381 Floating-Point Unit. The NS32081 provides highspeed arithmetic computation with high precision and accuracy at low cost. The NS32381 provides low power consumption and even greater performance than the NS32081
while maintaining high-precision and accuracy.
CLEANEST 32-BIT OPTIMIZED ARCHITECTURE
The Embedded System Processor was designed around a
32-bit architecture from the beginning. It has a fully symmetrical instruction set so that all addressing modes and all
data types can be operated on by all instructions. This
makes it easy to learn the architecture, easy to program in
assembly language, and easy to write code-efficient, highlevel language compilers.
HIGH-LEVEL LANGUAGE SUPPORT
National's Embedded System Processor has special features that support high-level languages, thus improving software productivity and reducing development costs. For example, there are special instructions that help the compiler
deal with structured data types such as Arrays, Strings, Records, and Stacks. Also, modular programming is supported
by special hardware registers, software instructions, an external addressing mode, and architecturally supported link
tables.
APPLICATION-SPECIFIC SLAVE PROCESSORS
Embedded System Processor architecture allows users to
design their own application-specific slave processors to
interface with the existing chip set. These processors can
be used to increase the overall system performance by
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CENTRAL PROCESSING UNITS (CPU's)
NS32GX32
High-Performance 32-Bit Embedded System Processor
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CPU-Central
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Section 2 Contents
NS32GX32-20, NS32GX32-25, NS32GX32-30 High-Performance 32-Bit Embedded System
Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS32CG16-10, NS32CG16-15 High-Performance Printer/Display Processors. . . . . . . . . . . . . .
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The NS32GX32 is a high-performance 32-bit embedded
system processor in the Series 32000® family. It is software
compatible with the previous microprocessors in the family
but with a greatly enhanced internal implementation.
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Software compatible with the Series 32000 family
32-bit architecture and implementation
4-GByte uniform addressing space
4-Stage instruction pipeline
512-Byte on-chip instruction cache
1024-Byte on-chip data cache
High-performance bus
- Separate 32-bit address and data lines
- Burst mode memory accessing
- Dynamic bus sizing
• Floating-point support via the NS32381
• 1.25 J.Lm double-metal CMOS technology
• 175-pin PGA package
The NS32GX32 integrates more than 320,000 transistors
fabricated in a 1.25 J.Lm double-metal CMOS technology.
The advanced technology and mainframe-like design of the
device enable it to achieve peak performance of 15 million
instructions per second.
The high-performance specifications are the result of a fourstage instruction pipeline, on-chip instruction and data
caches, and a significantly increased clock frequency. In addition, the system interface provides optimal support for applications spanning a wide range, from low-cost, real-time
controllers to highly sophisticated, embedded systems.
In addition to generally improved performance, the
NS32GX32 offers much faster interrupt service and task
switching for real-time applications.
Block Diagram
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1.0 PRODUCT INTRODUCTION
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2.0 ARCHITECTURAL DESCRIPTION
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3.0 FUNCTIONAL DESCRIPTION (Continued)
3.1.3 Instruction Pipeline
3.1.3.1 Branch Prediction
2.1 Register Set
3.1.3.2 Memory Mapped 1/0
2.1.1 General Purpose Registers
3.1.3.3 Serializing Operations
2.1.2 Address Registers
3.1.4 Slave Processor Instructions
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2.1.3 Processor Status Register
3.1.4.1 Slave Instruction Protocol
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2.1.4 Configuration Register
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3.1.4.2 Floating-Point Instructions
2.1.5 Debug Registers
3.1.4.3 Custom Slave Instructions
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2.2 Memory Organization
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2.2.1 Address Mapping
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2.3 Modular Software Support
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2.4 Instruction Set
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3.2 Exception Processing
3.2.1 Exception Acknowledge Sequence
3.2.2 Returning from an Exception Service Procedure
3.2.3 Maskable Interrupts
3.2.3.1 Non-Vectored Mode
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3.2.3.2 Vectored Mode: Non-Cascaded Case
2.4.1 General Instruction Format
3.2.3.3 Vectored Mode: Cascaded Case
2.4.2 Addressing Modes
3.2.4 Non-Maskable Interrupt
2.4.3 Instruction Set Summary
3.2.5 Traps
3.0 FUNCTIONAL DESCRIPTION
3.2.6 Bus Errors
3.1 Instruction Execution
3.2.7 Priority Among Exceptions
3.1.1 Operating States
3.2.8 Exception Acknowledge Sequences:
Detailed Flow
3.1.2 Instruction Endings
3.1.2.2 Suspended Instructions
3.2.8.1 MaskablelNon-Maskable Interrupt
Sequence
3.1.2.3 Terminated Instructions
3.2.8.2 Restartable Bus Error Sequence
3.1.2.4 Partially Completed Instructions
3.2.8.3 SLAVE/ILLlSVC/DVZ/FLG/BPT lUND
Trap Sequence
3.1.2.1 Completed Instructions
3.2.8.4 Trace Trap Sequence
2-4
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Table of Contents (Continued)
3.0 FUNCTIONAL DESCRIPTION (Continued)
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4.0 DEVICE SPECIFICATIONS (Continued)
3.2.8.5 Integer-Overflow Trap Sequence
4.4.1 Definitions
3.2.8.6 Debug Trap Sequence
4.4.2 Timing Tables
3.2.8.7 Non-Restartable Bus Error Sequence
4.4.2.1 Output Signals: Internal Propagation
Delays
3.3 Debugging Support
4.4.2.2 Input Signal Requirements
3.3.1 Instruction Tracing
4.4.3 Timing Diagrams
3.3.2 Debug Trap Capability
3.4 On-Chip Caches
APPENDIX A: INSTRUCTION FORMATS
3.4.1 Instruction Cache (IC)
B: COMPATIBILITY ISSUES
3.4.2 Data Cache (DC)
B.1 Restrictions on Compatibility
3.4.3 Cache Coherence Support
3.5 System Interface
3.5.1 Power and Grounding
3.5.4 Bus Cycles
C.2 Instruction Definitions
3.5.4.3 Burst Cycles
D: INSTRUCTION EXECUTION TIMES
3.5.4.4 Cycle Extension
3.5.4.5 Interlocked Bus Cycles
3.5.4.6 Interrupt Control Cycles
0.1 Internal Organization and Instruction
Execution
3.5.4.7 Slave Processor Bus Cycles
0.2 Basic Execution Times
3.5.5 Bus Exceptions
0.2.1 Loader Timing
3.5.6 Dynamic Bus Configuration
0.2.2 Address Unit Timing
3.5.6.1 Instruction Fetch Sequences
0.2.3 Execution Unit Timing
3.5.6.2 Data Read Sequences
0.3 Instruction Dependencies
3.5.6.3 Data Write Sequences
0.3.1 Data Dependencies
3.5.7 Bus Access Control
0.3.1.1 Register Interlocks
3.5.8 Interfacing Memory-Mapped I/O Devices
0.3.1.2 Memory Interlocks
3.5.9 Interrupt and Debug Trap Requests
0.3.2 Control Dependencies
3.5.10 Internal Status
0.4 Storage Delays
4.0 DEVICE SPECIFICATIONS
0.4.1 Instruction Cache Misses
4.1 Pin Descriptions
0.4.2 Data Cache Misses
4.1.1 Supplies
0.4.3 Instruction and Operand Alignment
4.1.2 Input Signals
0.5 Execution Time Calculations
4.1.3 Output Signals
0.5.1 Definitions
4.1.4 Input/Output Signals
0.5.2 Notes on Table Use
4.2 Absolute Maximum Ratings
0.5.3 Teft Evaluation
4.3 Electrical Characteristics
0.5.4 Instruction Timing Example
4.4 Switching Characteristics
0.5.5 Execution Timing Tables
0.5.5.1 Basic and Memory
Management Instructions
0.5.5.2 Floating-Point Instructions,
CPU Portion
2-5
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C.1 Processor Service Instructions
3.5.4.2 Basic Read and Write Cycles
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B.3 Integer-Overflow Trap
C: INSTRUCTION SET EXTENSIONS
3.5.4.1 Bus Status
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B.5 Memory-Mapped I/O
3.5.3 Resetting
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B.2 Architecture Extensions
B.4 Self-Modifying Code
3.5.2 Clocking
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List of Illustrations
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CPU Block Diagram ................................................................•.........................•.. 1
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NS32GX32 Internal Registers ..........................................................•................•....... 2-1
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Configuration Register (CFG) .... ' ........................•.............................................•.......• 2-3
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Debug Condition Register (OCR) .......................•........................................................ 2-4
2:
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Processor Status Register (PSR) ................................................................................ 2-2
Debug Status Register (DSR) ................................................................................... 2-5
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NS32GX32 Address Mapping ........................................................................•..•....... 2-6
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NS32GX32 Run-Time Environment ... " ............ '...........................•................................. 2-7
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General Instruction Format ...............................•..............................•..........•........... 2-8
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Index Byte Format ..........................................................•......................•.......... 2-9
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Displacement Encodings ...................................................................................... 2-10
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Operating States .......................................•..............................•....................... 3-1
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NS32GX32 Internal Instruction Pipeline .......................................................................... 3-2
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Memory References for Consecutive Instructions ........•........................•............................... 3-3
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Memory References after Serialization ............................................................ ~ .............. 3-4
Slave Instruction Protocol: CPU Actions ...............................................................•.......... 3-5
10 and Operation Word ................................................................................•....... 3-6
Slave Processor Status Word ................................................................................... 3-7
Interrupt Dispatch Table ....................................................................................... 3-8
Exception Acknowledge Sequence: Direct-Exception Mode Disabled ................................................ 3-9
Exception Acknowledge Sequence: Direct-Exception Mode Enabled ................................................ 3-10
Return From Trap (RETTn) Instruction Flow: Direct-Exception Mode Disabled ........................................ 3-11
Return From Interrupt (RETI) Instruction Flow: Direct-Exception Mode Disabled ...................................... 3-12
Exception Processing Flowchart .•............................................................................. 3-13
Service Sequence .......................................................................•................... 3-14
Instruction Cache Structure ........................................................................' ........... 3-15
Data Cache Structure ...................................................................... '................... 3-16
Power and Ground Connections ............................................................................... 3-17
Bus Clock Synchronization .................................................................................... 3-18
Power-On Reset Requirements ...........................•...............•.....•.............................. 3-19
General Reset Timing ............................................................. '.............•...•..•...... 3-20
Basic Read Cycle ............................................................................................ 3-21
Write Cycle ......................................................•.....................•..................... 3-22
Burst Read cycles .........................................................................'.. '................. 3-23
Cycle Extension of a Basic Read Cycle ....................•.................................................... 3-24
Slave Processor Write Cycle ................................................................................... 3-25
Slave Processor Read Cycle .................................................................................. 3-26
Bus Retry During a Basic Read Cycle ........................................................................... 3-27
Basic Interface for 32-Bit Memories .....................................................................•...... 3-28
Basic Interface for 16-Bit Memories .......................•..............................................•..... 3-29
Hold Acknowledge: (Bus Initially Idle) ......................•..............................................•..... 3-30
Typical 1/0 Device Interface .........................................•.................................'........ 3-31
2-6
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List of Illustrations (Continued)
NS32GX32 Interface Signals ................................................................................... 4-1
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175-Pin PGA Package ......................................................................................... 4-2
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Output Signals Specification Standard ....................•.......................................................4-3
Input Signals Specification Standard ............................................................................. .4-4
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Basic Read Cycle Timing ...•......................•.............................•.............................. 4-5
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Write Cycle Timing ........•....................................................•.............................. 4-6
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Interlocked Read and Write Cycles ...............•.............................................................. 4-7
Burst Read Cycles ............................................................................................ 4-8
External Termination of Burst Cycles ............................................................................ 4-9
Bus Error or Retry During Burst Cycles .......................................................................... 4-10
Extended Retry Timing ...............................................•....................................... 4-11
HOLD Timing (Bus Initially Idle) ................................................................................ 4-12
HOLD Acknowledge Timing (Bus Initially Not Idle) •.................................•............................. 4-13
Slave Processor Read Timing ..................................................................•.............. 4-14
Slave Processor Write Timing .................................................................................. 4-15
Slave Processor Done ..•.............................................•....................................... 4-16
FSSR Signal Timing .....•.................................................................................... 4-17
INT and NMI Signals Sampling .........................................•....................................... 4-18
Debug Trap Request ..•..............................................•....................................... 4-19
PFS Signal Timing ...................................................•....................................... 4-20
ISF Signal Timing ......•.............................................•....................................... 4-21
Break Point Signal Timing ..................................................................................... 4-22
Clock Waveforms ............................................................................................ 4-23
Bus Clock Synchronization .................................................................................... 4-24
Power-On Reset .......•..................................................................................... 4-25
Non-Power-On Reset ...•..................................................................................... 4-26
LPRi/SPRi Instruction Formats ................................................................................. C-1
CINV Instruction Format .......................................................................•............... C-2
List of Tables
Access Protection Levels ...................................................................................... 2-1
NS32GX32 Addressing Modes .................................................................................. 2-2
NS32GX32 Instruction Set Summary ............................................................................ 2-3
Floating-Point Instruction Protocol ...............•............................................................... 3-1
Custom Slave Instruction Protocols .............................................................................. 3-2
Summary of Exception Processing .............................................................................. 3-3
Interrupt Sequences ........................................................................................... 3-4
Cacheable/Non-Cacheable Instruction Fetches from a 32-Bit Bus ................................................... 3-5
Cacheable/Non-Cacheable Instruction Fetches from a 16-Bit Bus ..........•.....................•.................. 3-6
CacheablelNon-Cacheable Instruction Fetches from an 8-Bit Bus ................................................... 3-7
CacheablelNon-Cacheable Data Reads from a 32-Bit Bus ................•........................................ 3-8
Cacheable/Non-Cacheable Data Reads from a 16-Bit Bus ......................................................... 3-9
Cacheable/Non-Cacheable Data Reads from an 8-Bit Bus ........................................................ 3-10
Data Writes to a 32-Bit Bus .................................................................................... 3-11
Data Writes to a 16-Bit Bus .................................................................................... 3-12
Data Writes to an 8-Bit Bus ....•............................................................................... 3-13
LPRilSPRi New 'Short' Field Encodings ......................................................................... C-1
Additional Address Unit Processing Time for Complex Addressing Modes ............................................. D-1
2-7
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1.0 Product Introduction
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The NS32GX32 is an extremely sophisticated microprocessorin the Series 32000 family with a full 32-bit architecture
and implementation optimized for high-performance applications.
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Large, Uniform Addressing. The NS32GX32 has 32-bit
address pointers that can address up to 4 gigabytes without
requiring any segmentation.
Modular Software Support. Any software package for the
Series 32000 family can be developed independent of all
other packages, without regard to individual addressing. In
addition, ROM code is totally relocatable and easy to access, which allows a significant reduction in hardware and
software costs.
By employing a number of mainframe-like features, the device can deliver 15 MIPS peaks performance with no wait
states at a frequency of 30 MHz.
The NS32GX32 is fully software compatible will all the other
Series 32000 CPUs. The architectural features of the Series
32000 family and particularly the NS32GX32 CPU, are described briefly below.
Software Processor Concept. The Series 32000 architecture allows future expansions of the instruction set that can
be executed by special slave processors, acting as extensions to the CPU. This concept of slave processors is
unique to the Series 32000 family. It allows software compatibility even for future components because the slave
hardware is transparent to the software. With future advances in semiconductor technology, the slaves can be
physically integrated on the CPU chip itself.
Powerful Addressing Modes. Nine addressing modes
available to all instructions are included to access data
structures efficiently.
Data Types. The architecture provides for numerous data
types, such as byte, word, doubleword. and BCD, which may
be arranged into a wide variety of data structures.
SymmetriC Instruction Set. While avoiding special case
instructions that compilers can't use, the Series 32000 architecture incorporates powerful instructions for control operations, such as array indexing and external procedure
calls, which save considerable space and time for compiled
code.
To summarize, the architectural features cited above provide three primary performance advantages and characteristics:
• High-level language support
• Easy future growth path
Memory-to-Memory Operations. The Series 32000 CPUs
represent two-address machines. This means that each operand can be referenced by anyone of the addressing
modes provided.
• Application flexibility
2.0 Architectural Description
2.1 REGISTER SET
This powerful memory-to-memory architecture permits
memory locations to be treated as registers for all usefull
operations. This is important for temporary operands as well
as for context switching.
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Address
3281ts
PC
SPO
SP1
FP
SB
INTBASE
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The NS32GX32 CPU has 21 internal registers grouped according to functions as follows: 8 general purpose, 7 address, 1 processor status, 1 configuration, and 4 debug. All
registers are 32 bits wide except for the module and processor status, which are each 16 bits wide. Figure 2-1 shows
the NS32GX32 internal registers.
General Purpose
3281ts ~
RO
R1
R2
R3
R4
R5
R6
R7
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MOD
Processor Status
PSR
Debug
OCR
DSR
CAR
BPC
Configuration
CFG
FIGURE 2-1. NS32GX32 Internal Registers
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2.0 Architectural Description
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2.1.1 General Purpose Registers
INTBASE-Interrupt Base. The INTBASE register holds
the address of the dispatch table for interrupts and traps
(Section 3.2.1).
There are eight registers (RO-R7) used for satisfying the
high speed general storage requirements, such as holding
temporary variables and addresses. The general purpose
registers are free for any use by the programmer. They are
32 bits in length. If a general purpose register is specified for
an operand that is eight or 16 bits long, only the low part of
the register is used; the high part is not referenced or modified.
MOD-Module. The MOD register holds the address of the
module descriptor of the currently executing software module. The MOD register is 16 bits long, therefore the module
table must be contained within the first 64 kbytes of memory.
2.1.3 Processor Status Register
2.1.2 Address Registers
The seven address registers are used by the processor to
implement specific address functions. A description of them
follows.
PC-Program Counter. The PC register is a pointer to the
first byte of the instruction currently being executed. The PC
is used to reference memory in the program section.
When a reference is made to the selected Stack Pointer
(see PSR S-bit), the terms 'SP Register' or 'SP' are used.
SP refers to either SPO or SP1, depending on the setting of
the S bit in the PSR register. If the S bit in the PSR is 0, SP
refers to SPO. If the S bit in the PSR is 1 then SP refers to
SP1.
L
The L bit is altered by comparison instructions. In a
comparison instruction the L bit is set to "1" if the second operand is less than the first operand, when both
operands are interpreted as unsigned integers. Otherwise, it is set to "0". In Floating-Point comparisons, this
bit is always cleared.
The NS32GX32 also allows the SP1 register to be directly
loaded and stored using privileged forms of the LPRi and
SPRi instructions, regardless of the setting of the PSR S-bit.
When SP1 is accessed in this manner, it is referred to as
'USP Register' or simply 'USP'.
V
The V-bit enables generation of a trap (OVF) when an
integer arithmetic operation overflows.
F
The F bit is a general condition flag, which is altered by
many instructions (e.g., integer arithmetic instructions
use it to indicate overflow).
Stacks in the Series 32000 family grow downward in memory. A Push operation pre-decrements the Stack Pointer by
the operand length. A Pop operation post-increments the
Stack Pointer by the operand length.
Z
The Z bit is altered by comparison instructions. In a
comparison instruction the Z bit is set to "1" if the second operand is equal to the first operand; otherwise it is
set to "0".
FP-Frame Pointer. The FP regist~r is used by a procedure
to access parameters and local variables on the stack. The
FP register is set up on procedure entry with the ENTER
instruction and restored on procedure termination with the
EXIT instruction.
N
The N bit is altered by comparison instructions. In a
comparison instruction the N bit is set to "1" if the second operand is less than the first operand, when both
operands are interpreted as signed integers. Otherwise,
it is set to "0".
The frame pOinter holds the address in memory occupied by
the old contents of the frame pointer.
U
If the U bit is "1" no privileged instructions may be executed. If the U bit is "0" then all instructions may be
executed. When U = 0 the processor is said to be in
Supervisor Mode; when U = 1 the processor is said to
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FIGURE 2·2. Processor Status Register (PSR)
2-9
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The T bit causes program tracing. If this bit is set to 1, a
TRC trap is executed after every instruction (Section
3.3.1).
S
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The PSR is sixteen bits long, divided into two eight-bit
halves. The low order eight bits are accessible to all programs, but the high order eight bits are accessible only to
programs executing in Supervisor Mode.
T
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The C bit indicates that a carry or borrow occurred after
an addition or subtraction instruction. It can be used
with the AD DC and SU8C instructions to perform multiple-precision integer arithmetic calculations. It may
have a setting of 0 (no carry or borrow) or 1 (carry or
borrow).
SB-Statlc Base. The S8 register points to the global variables of a software module. This register is used to support
relocatable global variables for software modules. The S8
register holds the lowest address in memory occupied by
the global variables of a module.
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The Processor Status Register (PSR) holds status information for the microprocessor.
C
sPa, SP1-Stack Pointers. The SPO register points to the
lowest address of the last item stored on the INTERRUPT
STACK. This stack is normally used only by the operating
system. It is used primarily for storing temporary data, and
holding return information for operating system subroutines
and interrupt and trap service routines. The SP1 register
points to the lowest address of the last item stored on the
USER STACK. This stack is used by normal user programs
to hold temporary data and subroutine return information.
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2.0 Architectural Description
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S
The S bit specifies whether the SPO register or SP1
register is used as the Stack Pointer. The bit is automatically cleared on interrupts and traps. It may have a
setting of 0 (use the SPO register) or 1 (use the SP1
register).
P
The P bit prevents a TRC trap from occuring more than
once for an instruction (Section 3.3.1). It may have a
setting of 0 (no trace pending) or 1 (trace pending).
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be in User Mode. A User Mode program is restricted
from executing certain instructions and accessing certain registers which could interfere with the operating
system. For example, a User Mode program is prevented from changing the setting of the flag used to indicate
its own privilege mode. A Supervisor Mode program is
assumed to be a trusted part of the operating system,
hence it has no such restrictions.
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Interrupt vectoring. This bit controls whether maskable interrupts are handled in nonvectored (I = 0) or
vectored (I = 1) mode. Refer to Section 3.2.3 for more
information.
F
Floating-point instruction set. This bit indicates
whether a floating-point unit (FPU) is present to execute floating-point instructions. If this bit is 0 when the
CPU executes a floating-point instruction, a Trap
(UNO) occurs. If this bit is 1, then the CPU transfers
the instruction and any necessary operands to the
FPU using the slave-processor protocol described in
Section 3.1.4.1.
C
Custom instruction set. This bit indicates whether a
custom slave processor is present to execute custom
instructions. If this bit is 0 when the CPU executes a
custom instruction, a Trap (UNO) occurs. If this bit is
1, the CPU transfers the instruction and any necessary operands to the custom slave processor using
the slave-processor protocol described in Section
3.1.4.1.
DE
Direct-Exception mode enable. This bit enables the
Direct-Exception mode for processing exceptions.
When this mode is selected, the CPU response time
to interrupts and other exceptions is significantly improved. Refer to Section 3.2.1 for more information.
DC
Data Cache enable. This bit enables the on-chip Data
Cache to be accessed for data reads and writes. Refer to Section 3.4.2 for more information.
LDC
Lock Data Cache. This bit controls whether the contents of the on-chip Data Cache are locked to fixed
memory locations (LDC= 1), or updated when a data
read is missing from the cache (LDC = 0).
IC
Instruction Cache enable. This bit enables the onchip Instruction Cache to be accessed for instruction
fetches. Refer to Section 3.4.1 for more information.
LIC
Lock Instruction Cache. This bit controls whether the
contents of the on-chip Instruction Cache are locked
to fixed memory locations (L1C= 1), or updated when
an instruction fetch is missing from the cache
(L1C=O).
If I = 1, then all interrupts will be accepted. If I = 0,
only the NMI interrupt is accepted. Trap enables are not
affected by this bit.
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2.1.4 Configuration Register
The Configuration Register (CFG) is 32 bits wide, of which
ten bits are implemented. The implemented bits enable various operating modes for the CPU, including vectoring of
interrupts, execution of slave instructions, and control of the
on·chip caches. In the NS32332 bits 4 through 7 of the CFG
register selected between the 16-bit and 32-bit slave protocols and between 512-byte and 4-Kbyte page sizes. The
NS32GX32 supports only the 32-bit slave protocol and no
memory management: consequently these bits are forced
to 1.
When the CFG register is loaded using the LPRi instruction,
bit 2 and bits 13 through 31 should be set to O. Bits 4
through 7 are ignored during loading, and are always returned as 1's when CFG is stored via the SPRi instruction.
When the SETCFG instruction is executed, the contents of
the CFG register bits 0 through 3 are loaded from the instruction's short field, bits 4 through 7 are ignored and bits 8
through 12 are forced to o. Bit 2 must be set to O.
The format of the CFG register is shown in Figure 2-3. The
various control bits are described below.
I
Reserved
I
L1C
I
IC
I LDC I
DC
I
DE
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C
I
Res
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F
FIGURE 2·3. Configuration Register (CFG) Bits 13 to 31 are Reservedj Bits 4 to 7 are Forced to 1
2-10
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2.0 Architectural Description
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2.1.5 Debug Registers
The NS32GX32 contains 4 registers dedicated for debugging functions.
The following 2 bits control testing features that can be
used during initial system debugging. These features are
unique to the NS32GX32 implementation of the Series
32000 architecture; as such, they may not be supported in
future implementations. For normal operation these 2 bits
should be set to O.
SI
Single-Instruction mode enable. This bit, when set
to 1, inhibits the overlapping of instruction's execution.
These registers are accessed using privileged forms of the
LPRi and SPRi instructions.
OCR-Debug Condition Register. The DCR Register enables detection of debug conditions. The format of the DCR
is shown in Figure 2-4,' the various bits are described below.
A debug condition is enabled when the related bit is set to 1.
BCP
Branch Condition Prediction disable. When this bit is
1, the branch prediction mechanism is disabled. See
Section 3.1.3.1.
DSR-Debug Status Register. The DSR Register indicates
debug conditions that have been detected. When the CPU
detects an enabled debug condition, it sets the corresponding bit (BC, BEX, BCA) in the DSR to 1. When an addresscompare condition is detected, then the RD-bit is loaded to
indicate whether a read or write reference was performed.
Software must clear all the bits in the DSR when appropriate. The format of the DSR is shown in Figure 2-5,' the various fields are described below.
RD
Indicates whether the last address-compare condition was for a read (RD = 1) or write (RD = 0)
reference
BPC PC-match condition detected
BEX External condition detected
BCA Address-compare condition detected
CBEO Compare Byte Enable 0; when set, BYTEO of an
aligned double·word is included in the address com·
parison
CBE1 Compare Byte Enable 1; when set, BYTE1 of an
aligned double·word is included in the address com·
parison
CBE2 Compare Byte Enable 2; when set, BYTE2 of an
aligned double·word is included in the address comparison
CBE3 Compare Byte Enable 3; when set, BYTE3 of an
aligned double-word is included in the address com·
parison
CWR Address-compare enable for write references
CRD
CAE
TR
PCE
UD
SO
DEN
Address-compare enable for read references
Address-compare enable
Enable Trap (DBG) when a debug condition is de·
tected
PC-match enable
Enable debug conditions in User-Mode
Enable debug conditions in Supervisor Mode
Enable debug conditions
Note: If an address compare is detected for a read and write for the same
Instruction, the RD bit will remain clear.
CAR--Compare Address Register. The CAR Register
contains the address that is compared to operand reference
addresses to detect an address-compare condition. The address must be double-word aligned; that is, the two leastsignificant bits must be O. The CAR is 32 bits wide.
15
Reserved
31
24
Reserved
FIGURE 2·4. Debug Condition Register (OCR)
13~D
28 27
BPC
BEX
BCA
1
Reserved
FIGURE 2·5. Debug Status Register (DSR)
2-11
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2.0 Architectural Description (Continued)
BPC-Breakpolnt Program Counter. The BPC Register
contains the address that is compared with the PC contents
to detect a PC-match condition. The BPC Register is 32 bits
wide.
stored at the lowest address and the most significant word
of the double-word is stored at the address two higher. In
memory, the address of a double-word is the address of its
least significant byte, and a double-word may start at any
address.
2.2 MEMORY ORGANIZATION
The NS32GX32 implements full 32-bit addresses. This allows the CPU to access up to 4 Gbytes of memory. The
memory is a uniform linear address space. Memory locations are numbered sequentially starting at zero and ending
at 232 -1. The number specifying a memory location is
called an address. The contents of each memory location is
a byte consisting of eight bits. Unless otherwise noted, diagrams in this document show data stored in memory with
the lowest address on the right and the highest address on
the left. Also, when data is shown vertically, the lowest address is at the top of a diagram and the highest address at
the bottom of the diagram. When bits are numbered in a
diagram, the least significant bit is given the number zero,
and is shown at the right of the diagram. Bits are numbered
in increasing significance and toward the left.
A+3
24123
16 15
1
A+2
A+1
MSB
A
LSB
Double-Word at Address A
Although memory is addressed as bytes, it is actually organized as double-words. Note that access time to a word or a
double-word depends upon its address, e.g. double-words
that are aligned to start at addresses that are multiples of
four will be accessed more quickly than those not so
aligned. This also applies to words that cross a double-word
boundary.
2.2.1 Address Mapping
Figure 2-6 shows the NS32GX32 address mapping.
The NS32GX32 supports the use of memory-mapped peripheral devices and coprocessors. Such memory-mapped
devices can be located at arbitrary locations in the address
space except for the upper 8 Mbytes of memory (addresses
between FF800000 (hex) and FFFFFFFF (hex), inclusive),
which are reserved by National Semiconductor Corporation.
Nevertheless, it is recommended that high-performance peripheral devices and coprocessors be located in a specific 8
Mbyte region of memory (addresses between FFOOOOOO
(hex) and FF7FFFFF (hex), inclusive), that is dedicated for
memory-mapped I/O. This is because the NS32GX32 detects references to the dedicated locations and serializes
reads and writes. See Section 3.1.3.3. When making I/O
references to addresses outside the'dedicated region, external hardware must indicate to the NS32GX32 that special
handling is required.
A
Byte at Address A
Two contiguous bytes are called a word. Except where noted, the least significant byte of a word is stored at the lower
address, and the most significant byte of the word is stored
at the next higher address. In memory, the address of a
word is the address of its least significant byte, and a word
may start at any address.
A
A+1
MSB
LSB
In this case a small performance degradation will also result. Refer to Section 3.1.3.2 for more information on memory-mapped I/O.
Word at Address A
Two contiguous words are called a double-word. Except
where noted, the least significant word of a double-word is
Address (Hex)
00000000
Memory and I/O
FFOOOOOO
Memory-Mapped I/O
FF800000
Reserved by NSC
FFFFFEOO
Interrupt Control
FFFFFFFF
FIGURE 2-6. NS32GX32 Address Mapping
2-12
2.0 Architectural Description
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(Continued)
The Module Table is located within the first 64 kbytes of
memory. This table contains a Module Descriptor (also
called a Module Table Entry) for each module in the address space of the program. A Module Descriptor has four
32-bit entries corresponding to each component of a module:
2.3 MODULAR SOFTWARE SUPPORT
The NS32GX32 provides special support for software modules and modular programs.
Each module in a NS32GX32 software environment consists of three components:
1. Program Code Segment.
• The Static Base entry contains the address of the beginning of the module's static data segment.
This se~ment contains the module's code and constant
data.
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2. Static Data Segment.
• The Link Table Base points to the beginning of the module's Link Table.
Used to store variables and data that may be accessed
by all procedures within the module.
3. Link Table.
• The Program Base is the address of the beginning of the
code and constant data for the module.
.....
• A fourth entry is currently unused but reserved.
This component contains two types of entries: Absolute
Addresses and Procedure Descriptors.
The MOD Register in the CPU contains the address of the
Module Descriptor for the currently executing module.
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An Absolute Address is used in the external addressing
mode, in conjunction with a displacement and the current
MOD Register contents to compute the effective address
of an external variable belonging to another module.
The Static Base Register (SB) contains a copy of the Static
Base entry in the Module Descriptor of the currently executing module, i.e., it points to the beginning of the current
module's static data area.
The Procedure Descriptor is used in the call external procedure (CXP) instruction to compute the address of an
external procedure.
This register is implemented in the CPU for efficiency purposes. By having a copy of the static base entry or chip, the
CPU can avoid reading it from memory each time a data
item in the static data segment is accessed.
Normally, the linker program specifies the locations of the
three components. The Static Data and Link Table typically
reside in RAM; the code component can be either in RAM or
in ROM. The three components can be mapped into noncontiguous locations in memory, and each can be independently relocated. Since the Link Table contains the absolute
addresses of external variables, the linker need not assign
absolute memory addresses for these in the module itself;
they may be assigned at load time.
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In an NS32GX32 software environment modules need not
be linked together prior to loading. As modules are loaded,
a linking loader simply updates the Module Table and fills
the Link Table entries with the appropriate values. No modification of a module's code is required. Thus, modules may
be stored in read-only memory and may be added to a system independently of each other, without regard to their individual addressing. Figure 2-7 shows a typical NS32GX32
run-time environment.
To handle the transfer of control from one module to another, the NS32GX32 uses a module table in memory and two
registers in the CPU.
STATIC DATA
SEGMENT
SB REGISTER
DISP
31
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LINK TABLE
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PROGRAM CODE
SEGMENT
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DISP2
EXT. VARIABLE
TL/EE/l0253-2
Note: Dashed lines indicate information copied to registers during transfer of control between modules.
FIGURE 2-7. NS32GX32 Run-Time Environment
2-13
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DISP
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INDEX
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FIGURE 2-8. General Instruction Format
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TL/EE/10253-6
FIGURE 2-9. Index Byte Format
2.4 INSTRUCTION SET
Byte Displacement: Range - 64 to
+ 63
2.4.1 General Instruction Format
Figure 2-8 shows the general format of a Series 32000 instruction. The Basic Instruction is one to three bytes long
and contains the Opcode and up to two 5-bit General Addressing Mode (liGen") fields. Following the Basic Instruction field is a set of optional extensions, which may appear
depending on the instruction and the addressing modes selected.
D
SIGNED DISPLACEMENT
Word Displacement: Range -8192 to
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+ 8191
o
Index Bytes appear when either or both Gen fields specify
Scaled Index. In this case, the Gen field specifies only the
Scale Factor (1, 2, 4 or 8), and the Index Byte specifies
which General Purpose Register to use as the index, and
which addressing mode calculation to perform before indexing. See Figure 2-9.
Following Index Bytes come any displacements (addressing
constants) or immediate values associated with the selected addressing modes. Each Disp/lmm field may contain
one or two displacements, or one immediate value. The size
of a Displacement field is encoded with the top bits of that
field, as shown in Figure 2-10, with the remaining bits interpreted as a signed (two's complement) value. The size of an
immediate value is determined from the Opcode field. Both
Displacement and Immediate fields are stored most significant byte first. Note that this is different from the memory
representation of data (Section 2.2).
Double Word Displacement:
Range -(2 29 - 224)to + (2 29 - 1)*
0
7
1
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Some instructions require additional, 'implied" immediates
and/or displacements, apart from those associated with addressing modes. Any such extensions appear at the end of
the instruction, in the order that they appear within the list of
operands in the instruction definition (Section 2.4.3).
TL/EE/10253-7
FIGURE 2-10. Displacement Encodlngs
'Note: The pattern "11100000" for the most significant byte of the displace-
2.4.2 Addressing Modes
ment is reserved by National for future enhancements. Therefore. It
should never be used by the user program. This causes the lower
limit of the displacement range to be -(229 -2 24) instead of -229.
The CPU generally accesses an operand by calculating its
Effective Address based on information available when the
operand is to be accessed. The method to be used in performing this calculation is specified by the programmer as
an "addressing mode."
2-14
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2.0 Architectural Description
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CN
(Continued)
I\)
eral Purpose Register by 1, 2, 4 or B and adding it into the
total, yielding the final Effective Address of the operand.
Addressing modes are designed to optimally support hlghlevel language accesses to variables. In nearly all cases, a
variable access requires only one addressing mode, within
the instruction that acts upon that variable. Extraneous data
movement is therefore minimized.
Table 2-2 is a brief summary of the addressing modes. For a
complete description of their actions, see the Instruction Set
Reference Manual.
Addressing Modes fall into nine basic types:
Register: The operand is available in one of the eight General Purpose Registers. In certain Slave Processor instructions, an auxiliary set of eight registers may be referenced
instead.
Register Relative: A General Purpose Register contains an
address to which is added a displacement value from the
instruction, yielding the Effective Address of the operand in
memory.
2.4.3 Instruction Set Summary
Table 2-3 presents a brief description of the NS32GX32 instruction set. The Format column refers to the Instruction
Format tables (Appendix A). The Instruction column gives
the instruction as coded in assembly language, and the Description column provides a short description of the function
provided by that instruction. Further details of the exact operations performed by each instruction may be found in the
Instruction Set Reference Manual.
Memory Space: Identical to Register Relative above, except that the register used is one of the dedicated registers
PC, SP, SB or FP. These registers point to data areas generally needed by high-level languages.
Notations:
i = Integer length suffix: B = Byte
W = Word
Memory Relative: A pointer variable is found within the
memory space pointed to by the SP, SB or FP register. A
displacement is added to that pointer to generate the Effective Address of the operand.
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D = Double Word
f = Floating Point length suffix: F = Standard Floating
L = Long Floating
gen = General operand. Any addressing mode can be
specified.
short = A 4-bit value encoded within the Basic Instruction
(see Appendix A for encodings).
Immediate: The operand is encoded within the instruction.
This addressing mode is not allowed if the operand is to be
written.
Absolute: The address of the operand is specified by a
displacement field in the instruction.
imm = Implied immediate operand. An B-bit value appended after any addressing extensions.
disp = Displacement (addressing constant): 8, 16 or 32
bits. All three lengths legal.
External: A pointer value is read from a specified entry of
the current Link Table. To this pointer value is added a displacement, yielding the Effective Address of the operand.
reg = Any General Purpose Register: RO-R7.
areg = Any Processor Register: Address, Debug, Status,
Configuration.
creg = A Custom Slave Processor Register (Implementation Dependent).
Top of Stack: The currently-selected Stack Pointer (SPO or
SP1) specifies the location of the operand. The operand is
pushed or popped, depending on whether it is written or
read.
Scaled Index: Although encoded as an addressing mode,
Scaled Indexing is an option on any addressing mode except Immediate or another Scaled Index. It has the effect of
calculating an Effective Address, then multiplying any Gen-
cond = Any condition code, encoded as a 4-bit field within
the Basic Instruction (see Appendix A for encodings).
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2.0 Architectural Description (Continued)
TABLE 2-2. NS32GX32 Addressing Modes
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ENCODING
Register
00000
00001
00010
00011
00100
00101
00110
00111
MODE
ASSEMBLER SYNTAX
EFFECTIVE ADDRESS
Register 0
Register 1
Register 2
Register 3
Register 4
RegisterS
Register 6
Register 7
RO, FO, LO
R1,F1,L1
R2, F2, L2
R3, F3, L3
R4, F4, L4
RS, FS, LS
R6, F6, L6
R7, F7, L7
None: Operand is in the
specified register.
Register Relative
01000
01001
01010
01011
01100
01101
01110
01111
Register 0 relative
Register 1 relative
Register 2 relative
Register 3 relative
Register 4 relative
Register S relative
Register 6 relative
Register 7 relative
disp(RO)
disp(R1)
disp(R2)
disp(R3)
disp(R4)
disp(RS)
disp(R6)
disp(R7)
Disp + Register.
Memory Relative
10000
10001
10010
Frame memory relative
Stack memory relative
Static memory relative
disp2(disp1 (FP»
disp2(disp1 (SP»
disp2(disp1 (S8»
Disp2 + Pointer; Pointer found at
address Disp1 + Register. "SP" is either
SPO or SP1, as selected in PSR.
Reserved
10011
(Reserved for Future Use)
Immediate
10100
Immediate
value
None. Operand is input from
instruction queue.
Absolute
10101
Absolute
@disp
Disp.
EXT(disp1) + disp2
Disp2 + Pointer; Pointer Is found
at Link Table Entry number Disp1.
External
10110
. External
Top of Stack
10111
Top of stack
TOS
Top of current stack, using either
User or Interrupt Stack Pointer,
as selected in PSR. Automatic
Push/Pop included.
Memory Space
11000
11001
11010
11011
Frame memory
Stack memory
Static memory
Program memory
disp(FP)
disp(SP)
disp(S8)
·+disp
Disp + Register; "SP" is either
SPO or SP1, as selected in PSR.
Scaled Index
11100
11101
11110
11111
Index, bytes
Index, words
Index, double words
Index, quad words
mode[Rn:8]
mode[Rn:W]
mode[Rn:D]
mode[Rn:Q]
EA (mode) + Rn.
EA (mode) + 2 x Rn.
EA (mode) + 4 x Rn.
EA (mode) + 8 x Rn.
"Mode' and 'n' are contained
within the Index 8yte.
EA (mode) denotes the effective
address generated using mode.
2-16
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2.0 Architectural Description
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(Continued)
N
TABLE 2·3. NS32GX32 Instruction Set Summary
MOVES
Format
4
2
7
7
7
7
7
4
Operation
MOVi
MOVQi
MOVMi
MOVZBW
MOVZiD
MOVXBW
MOVXiD
ADDR
INTEGER ARITHMETIC
Format
Operation
4
ADDI
2
ADDQi
4
ADDCi
4
SUBi
4
SUBCi
6
NEGi
6
ABSi
7
MULi
7
QUOi
7
REMi
7
DIVi
7
MODi
7
MEIi
7
DEli
Operands
gen,gen
short,gen
gen,gen,disp
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
Description
Move a value.
Extend and move a signed 4-bit constant.
Move Multiple: disp bytes (1 to 16).
Move with zero extension.
Move with zero extension.
Move with sign extension.
Move with sign extension.
Move Effective Address.
Operands
gen,gen
short,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
Description
Add.
Add signed 4-bit constant.
Add with carry.
Subtract.
Subtract with carry (borrow).
Negate (2's complement).
Take absolute value.
Multiply.
Divide, rounding toward zero.
Remainder from QUO.
Divide, rounding down.
Remainder from DIV (Modulus).
Multiply to Extended Integer.
Divide Extended Integer.
PACKED DECIMAL (BCD) ARITHMETIC
Format
Operation
Operands
6
ADDPi
gen,gen
6
SUBPi
gen,gen
Description
Add Packed.
Subtract Packed.
INTEGER COMPARISON
Format
Operation
4
CMPi
2
CMPQi
7
CMPMi
Operands
gen,gen
short,gen
gen,gen,disp
Description
Compare.
Compare to signed 4-bit constant.
Compare Multiple: disp bytes (1 to 16).
LOGICAL AND BOOLEAN
Format
Operation
4
ANDi
4
ORi
4
BICi
4
XORi
6
COMi
6
NOTi
2
Scondi
Operands
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen
Description
Logical AND.
Logical OR.
Clear selected bits.
Logical Exclusive OR.
Complement all bits.
Boolean complement: LSB only.
Save condition code (cond) as a Boolean variable of size i.
SHIFTS
Format
6
6
6
Operands
gen,gen
gen,gen
gen,gen
Description
Logical Shift, left or right.
Arithmetic Shift, left or right.
Rotate, left or right.
Operation
LSHi
ASHi
ROTi
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2.0 Architectural Description (Continued)
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TABLE 2-3. NS32GX32 Instruction Set Summary (Continued)
BITS
Format
4
6
6
6
6
6
8
Operation
TBITi
SBITi
SBITIi
CBITi
CBITIi
IBITi
FFSi
Operands
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
Description
Test bit.
Test and set bit.
Test and set bit, interlocked.
Test and clear bit.
Test and clear bit, interlocked.
Test and invert bit.
Find first set bit.
BIT FIELDS
Bit fields are values in memory that are not aligned to byte boundaries. Examples are PACKED arrays and records used in
Pascal. "Extract" instructions read and align a bit field. "Insert" instructions write a bit field from an aligned source.
Format
Operation
Operands
Description
8
EXTi
reg,gen,gen,disp
Extract bit field (array oriented).
8
INSi
reg,gen,gen,disp
Insert bit field (array oriented).
7
EXTSi
gen,gen,imm,imm
Extract bit field (short form).
7
INSSi
gen,gen,imm,imm
Insert bit field (short form).
CVTP
reg,gen,gen
Convert to Bit Field Pointer.
8
ARRAYS
Format
8
8
Operation
CHECKi
INDEXi
Operands
reg,gen,gen
reg,gen,gen
STRINGS
String instructions assign specific functions to
the General Purpose Registers:
R4 - Comparison Value
R3 - Translation Table Pointer
R2 - String 2 Pointer
R1 - String 1 Pointer
RO - Limit Count
Format
5
5
5
Operation
MOVSi
MOVST
CMPSi
CMPST
SKPSi
SKPST
Operands
options
options
options
options
options
options
Description
Index bounds check.
Recursive indexing step for multiple-dimensional arrays.
Options on all string instructions are:
B (Backward):
Decrement string pointers after each step
rather than incrementing.
U (Until match):
End instruction if String 1 entry
matches R4.
W (While match):
End instruction if String 1 entry
does not match R4.
All string instructions end when RO decrements to zero.
Description
Move String 1 to String 2.
Move string, translating bytes.
Compare String 1 to String 2.
Compare translating, String 1 bytes.
Skip over String 1 entries.
Skip, translating bytes for Until/While.
2-18
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2.0 Architectural Description (Continued)
~
TABLE 2·3. NS32GX32 Instruction Set Summary (Continued)
JUMPS AND LINKAGE
Format
Operation
3
JUMP
0
BR
0
Bcond
3
CASEI
2
ACBI
3
JSR
BSR
CXP
3
CXPD
SVC
FLAG
BPT
ENTER
EXIT
RET
RXP
RETT
RETI
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Operands
gen
disp
disp
gen
short,gen,disp
gen
disp
dlsp
gen
[reg list),disp
[reg list)
disp
disp
disp
CPU REGISTER MANIPULATION
Format
Operation
Operands
[reg list]
1
SAVE
[reg list)
RESTORE
2
areg,gen
LPRi
Description
Jump.
Branch (PC Relative).
Conditional branch.
Multiway branch.
Add 4·bit constant and branch If non·zero.
Jump to subroutine.
Branch to subroutine.
Call external procedure.
Call external procedure using descriptor.
Supervisor Call.
Flag Trap.
Breakpoint Trap.
Save registers and allocate stack frame (Enter Procedure).
Restore registers and reclaim stack frame (Exit Procedure).
Return from subroutine.
Return from external procedure call.
Return from trap. (Privileged)
Return from Interrupt. (Privileged)
2
SPRi
areg,gen
3
3
3
5
ADJSPi
BISPSRi
BICPSRi
SETCFG
gen
gen
gen
[option list]
Description
Save General Purpose Registers.
Restore General Purpose Registers.
Load Processor Register. (Privileged if PSR, INTBASE, USP, CFG
or Debug Registers).
Store Processor Register. (Privileged if PSR, INTBASE, USP, CFG
or Debug Registers).
Adjust Stack Pointer.
Set selected bits in PSR. (Privileged if not Byte length)
Clear selected bits in PSR. (Privileged if not Byte length)
Set Configuration Register. (Privileged)
Operands
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen
gen
Description
Move a Floating Point value.
Move and shorten a Long value to Standard.
Move and lengthen a Standard value to Long.
Convert any integer to Standard or Long Floating.
Convert to integer by rounding.
Convert to integer by truncating, toward zero.
Convert to largest integer less than or equal to value.
Add.
Subtract.
Multiply.
Divide.
Compare.
Negate.
Take absolute value.
Polynomial Step.
Dot Product.
Binary Scale.
Binary Log.
Load FSR.
Store FSR.
FLOATING POINT
Format
Operation
11
MOVf
9
MOVLF
9
MOVFL
9
MOVif
9
ROUNDfi
9
TRUNCfi
9
FLOORfi
11
ADDf
11
SUBf
11
MULf
11
DIVf
11
CMPf
11
NEGf
11
ABSf
12
POLYf
12
DOTf
12
SCALBf
12
LOGBf
9
LFSR
9
SFSR
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(f')
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2.0 Architectural Description
MISCELLANEOUS
Format
Operation
Operands
1
•
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NOP
WAIT
DIA
14
(f')
8
CINV
MOVSUi
options,gen
gen,gen
8
MOVUSi
gen,gen
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(f')
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(Continued)
TABLE 2-3. NS32GX32 Instruction Set Summary (Continued)
CUSTOM SLAVE
Format
Operation
15.5
15.5
15.5
15.5
15.5
15.5
15.5
15.5
15.5
15.5
15.1
15.1
15.1
15.1
15.1
15.1
15.1
15.1
15.0
15.0
CCALOc
CCAL1c
CCAL2c
CCAL3c
CMOVOc
CMOV1c
CMOV2c
CMOV3c
CCMPOc
CCMP1c
CCVOci
CCV1ci
CCV2ci
CCV3ic
CCV4DQ
CCV5QD
LCSR
SCSR
LCR
SCR
Description
No Operation.
Wait for interrupt.
Diagnose. Single-byte "Branch to Self" for hardware
breakpointing. Not for use in programming.
Cache Invalidate. (Privileged)
Move a value from Supervisor
Space to User Space. (Privileged)
Move a value from User Space
to Supervisor Space. (Privileged)
Operands
Description
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen,gen
gen
gen
creg,gen
creg,gen
Custom Calculate.
Custom Move.
Custom Compare.
Custom Convert.
Load Custom Status Register.
Store Custom Status Register.
Load Custom Register. (Privileged)
Store Custom Register. (Privileged)
2-20
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3.0 Functional Description
This chapter provides details on the functional characteristics of the NS32GX32 microprocessor.
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The chapter is divided into five main sections:
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Instruction Execution, Exception Processing, Debugging,
On-Chip Caches and System Interface.
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3.1 INSTRUCTION EXECUTION
To execute an instruction, the NS32GX32 performs the following operations:
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• Fetch the instruction
• Read source operands, if any (1)
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• Calculate results
• Write result operands, if any
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• Modify flags, if necessary
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• Update the program counter
Under most circumstances, the CPU can be conceived to
execute instructions by completing the operations above in
strict sequence for one instruction and then beginning the
sequence of operations for the next instruction. However,
due to the internal instruction pipelining, as well as the occurrence of exceptions, the sequence of operations performed during the execution of an instruction may be altered. Furthermore, exceptions also break the sequentiality
of the instructions executed by the CPU.
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Details on the effects of the internal pipelining, as well as
the occurrence of exceptions on the instruction execution,
are provided in the following sections.
TL/EE/10253-8
FIGURE 3-1. Operating States
tion is detected, the CPU enters the Processing-An-Exception state.
Note: 1 In this and following sections, memory locations read by the CPU to
calculate effective addresses for Memory·Relative and External ad·
dressing modes are considered like source operands, even if the
effective address is being calculated for an operand with access
class of write.
The CPU enters the Halted state when a bus error is detected while the CPU is processing an exception, thereby preventing the transfer of control to an appropriate exception
service procedure. The CPU remains in the Halted state
until reset occurs. A special status identifying this state is
presented on the system interface.
3.1.1 Operating States
The CPU has five operating states regarding the execution
of instructions and the processing of exceptions: Reset, Executing Instructions, Processing An Exception, Waiting-ForAn-Interrupt, and Halted. The various states and transitions
between them are shown in Figure 3-1.
Whenever the RST signal is asserted, the CPU enters the
reset state. The CPU remains in the reset state until the
RST signal is driven inactive, at which time it enters the
Executing-Instructions state. In the Reset state the contents
of certain registers are initialized. Refer to Section 3.5.3 for
details.
In the Executing-Instructions state, the CPU executes instructions. It will exit this state when an exception is recognized or a WAIT instruction is encountered. At which time it
enters the Processing-An-Exception state or the WaitingFor-An-Interrupt state respectively.
Note: When the Direct·Exception mode is enabled, the CPU does not save
the MOD Register contents nor does it read the module linkage information for the exception service procedure. Refer to Section 3.2 for
details.
3.1.2 Instruction Endings
The NS32GX32 checks for exceptions at various points
while executing instructions. Certain exceptions, like interrupts, are in most cases recognized between instructions.
Other exceptions, like Divide-By-Zero Trap, are recognized
during execution of an instruction. When an exception is
recognized during execution of an instruction, the instruction
ends in one of four possible ways: completed, suspended,
terminated, or partially completed. Each type of exception
causes a particular ending, as specified in Section 3.2.
While in the Processing-An-Exception state, the CPU saves
the PC, PSR and MOD register contents on the stack and
reads the new PC and module linkage information to begin
execution of the exception service procedure (see note).
3.1.2.1 Completed Instructions
When an exception is recognized after an instruction is
completed, the CPU has performed all of the operations for
that instruction and for all other instructions executed since
the last exception occurred. Result operands have been
written, flags have been modified, and the PC saved on the
Interrupt Stack contains the address of the next instruction
to execute. The exception service procedure can, at its conclusion, execute the RETT instruction (or the RETI instruction for vectored interrupts), and the CPU will begin executing the instruction following the completed instruction.
Following the completion of all data references required to
process an exception, the CPU enters the Executing-Instructions state.
In the Waiting-For-An-Interrupt state, the CPU is idle. A special status identifying this state is presented on the system
interface (Section 3.5). When an interrupt or a debug condi-
2-21
3.0 Functional Description (Continued)
3.1.2.2 Suspended Instructions
An instruction is suspended when one of several trap conditions or a restartable bus error is detected during execution
of the instruction. A suspended instruction has not been
completed, but all other instructions executed since the last
exception occurred have been completed. Result operands
and flags due to be affected by the instruction may have
been modified, but only modifications that allow the instruction to be executed again and completed can occur. For
certain exceptions (Trap (UND), Trap (ILL), and bus errors)
the CPU clears the P-flag in the PSR before saving the copy
that is pushed on the Interrupt Stack. The PC saved on the
Interrupt Stack contains the address of the suspended instruction.
For example, the RESTORE Instruction pops up to 8 general-purpose registers from the stack. If an invalid page table
entry is detected on one of the references to the stack, then
the Instruction is suspended. The general-purpose registers
due to be loaded by the instruction may have been modified,
but the stack pointer still holds the same. value that it did
when the instruction began.
To complete a suspended instruction, the exception service
procedure takes either of two actions:
1. The service procedure can simulate the suspended instruction's execution. After calculating and writing the instruction's results, the flags in the PSR copy saved on the
Interrupt Stack should be modified, and the PC saved on
the Interrupt Stack should be updated to point to the next
instruction to execute. The service procedure can then
execute the RETT instruction, and the CPU begins executing the instruction following the suspended instruction.
This is the action taken when floating-point instructions
are simulated by software in systems without a hardware
floating-point unit.
2. The suspended instruction can be executed again after
the service procedure has eliminated the trap condition
that caused the instruction to be suspended. The service
procedure should execute the RETT instruction at its conclusion; then the CPU begins executing the suspended
instruction again. This is the action taken by a debugger
when it encounters a BPT instruction that was temporarily
placed in another instruction's location in order to set a
breakpoint.
is the contents of the PC. The result operands of other instructions executed since the last serializing operation may
not have been written to memory. A terminated instruction
cannot be completed.
3.1.2.4 Partially Completed Instructions
When a restartable bus error, interrupt, or debug condition is
recognized during execution of a string instruction, the instruction is said to be partially completed. A partially completed instruction has not completed, but all other instructions executed since the last exception occurred have been
completed. Result operands and flags due to be affected by
the instruction may have been modified, but the values
stored in the string pointers and other general-purpose registers used during the instruction's execution allow the instruction to be executed again and completed.
The CPU clears the P-flag in the PSR before saving the
copy that is pushed on the Interrupt Stack. The PC saved on
the Interrupt Stack contains the address of the partially
completed instruction. The exception service procedure
can, at its conclusion, simply execute the RETT instruction
(or the RETI instruction for vectored interrupts), and the
CPU will resume executing the partially completed instruction.
3.1.3 Instruction Pipeline
The NS32GX32 executes instructions in a heavily pipelined
fashion. This allows a significant performance enhancement
since the operations of several instructions are performed
simultaneously rather than in a strictly sequential manner.
The CPU provides a four-stage internal instruction pipeline.
As shown in Figure 3-2, a write buffer, that can hold up to
two operands, is also provided to allow write operations to
be performed off-line.
Stage 1
Buffer
Stage 2
Note 1: Although the NS32GX32 allows a suspended instruction to be exe·
cuted again and completed, the CPU may have read a source operand for the instruction from a memory-mapped peripheral port before the exception was recognized. In such a case, the characteristics of the peripheral device may prevent correct reexecution of the
Instruction.
Buffer
Stage 3
Note 2: It may be necessary for the exception service procedure to alter the
P-flag in the PSR copy saved on the Interrupt Stack: If the exception
service procedure simulates the suspended instruction and the Pflag was cleared by the CPU before saving the PSR copy, then the
saved T-flag must be copied to the saved P-flag (like the floatingpoint Instruction simulation described above). Or if the exception
service procedure executes the suspended instruction again and
the P-flag was not cleared by the CPU before saving the PSR copy,
then the saved P-flag must be cleared (like the breakpoint trap described above). Otherwise, no alteration to the saved P-f1ag is necessary.
Stage 4
p-------------.:
:
2 Memory Results
._-------------_.
Buffer
TL/EE/10253-9
FIGURE 3-2. NS32GX32 Internal Instruction Pipeline
Due to the pipelining, operations like fetching one instruction, reading the source operands of a second instruction,
calculating the results of a third instruction and storing the
results of a fourth instruction, can all occur in parallel.
3.1.2.3 Terminated Instructions
An instruction being executed is terminated when reset or a
nonrestartable bus error occurs. Any result operands and
flags due to be affected by the instruction are undefined, as
2-22
3.0 Functional Description
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(Continued)
The order of memory references performed by the CPU may
also differ from that related to a strictly sequential instruction execution. In fact, when an instruction is being executed, some of the source operands may be read from memory
before the instruction is completely fetched. For example,
the CPU may read the first source operand for an instruction
before it has fetched a displacement used in calculating the
address of the second source operand. The CPU, however,
always completes fetching an instruction and reading its
source operands before writing its results. When more than
one source operand must be read from memory to execute
an instruction, the operands may be read in any order. Similarly, when more than one result operand is written to memory to execute an instruction, the operands may be written
in any order.
DATA WRITE
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This occurs every time the sequentiality of the instructions is
broken, due to the execution of certain instructions or the
occurrence of exceptions.
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The result of a pipeline breakage is a performance degradation, due to the fact that a certain portion of the pipeline
must be flushed and new data must be brought in.
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More precisely, the prediction mechanism predicts backward branches as taken and forward branches as not taken,
except for the branch instructions BLE and BNE that are
always predicted as taken.
Thus, the resulting probability of correct prediction is fairly
high, especially for branch instructions placed at the end of
loops.
The sequence of operations performed by the loader and
execution units in the CPU is given below:
• Loader detects branches and calculates destination addresses
• Loader uses branch opcode and direction to select between sequential and non-sequential streams
• Loader saves address for alternate stream
• Execution unit resolves branch decision
Due to the branch predicition, some special care is required
when writing self-modifying code. Refer to the appropriate
section in Appendix B for more information on this subject.
INSTRUCTION N+ 1
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When a conditional branch instruction is decoded in the early stages of the pipeline, a prediction on the execution of the
instruction is performed.
INSTRUCTION rETCH ~UCTION fETCH
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3.1.3.1 Branch Prediction
The NS32GX32 provides a special mechanism, called
branch prediction, that helps minimize this performance
penalty.
The description above is summarized in Figure 3-3, which
shows the precedence of memory references for two consecutive instructions.
INSTRUCTION N
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One problem inherent to all pipelined machines is what is
called "Pipeline Breakage".
An instruction is fetched only after all previous instructions
have been completely fetched. However, the CPU may begin fetching an instruction before all of the source operands
have been read and results written for previous instructions.
The source operands for an instruction are read only after
all previous instructions have been fetched and their source
operands read. A source operand for an instruction may be
read before all results of previous instructions have been
written, except when the source operand's value depends
on a result not yet written. The CPU compares the address
and length of a source operand with those of any results not
yet written, and delays reading the source operand until after writing all results on which the source operand depends.
Also, the CPU ensures that the interlocked read and write
references to execute an SBITli or CBITIi instruction occur
after writing all results of previous instructions and before
reading any source operands for subsequent instructions.
The result operands for an instruction are written after all
results of previous instructions have been written.
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It is also to be noted that the CPU does not check for dependencies between the fetching of an instruction and the
writing of previous instructions' results. Therefore, special
care is required when executing self-modifying code.
3.1.3.2 Memory-Mapped I/O
The characteristics of certain peripheral devices and the
overlapping of instruction execution in the pipeline of the
NS32GX32 require that special handling be applied to memory-mapped liD references. liD references differ from
memory references in two significant ways, imposing the
following requirements:
DATA WRITE
TL/EE/l0253-10
FIGURE 3-3. Memory References for
Consecutive Instructions
(An arrow from one reference to another Indicates that
the first reference always precedes the second.)
1. Reading from a peripheral port can alter the value read
on the next reference to the same port or another port in
the same device. (A characteristic called here "destructive-reading".) Serial communication controllers and
FIFO buffers commonly operate in this manner. As explained in "Instruction Pipeline" above, the NS32GX32
can read the source operands for one instruction while
the previous instruction is executing. Because the previous instruction may cause a trap, an interrupt may be
recognized, or the flow of control may be otherwise altered, it is a requirement that destructive-reading of
source operands before the execution of an instruction
be avoided.
Another consequence of overlapping the operations for several instructions, is that the CPU may fetch an instruction
and read its source operands, even though the instruction is
not executed (e.g., due to the occurrence of an exception).
Special care is needed in the handling of memory-mapped
liD devices. The CPU provides special mechanisms to ensure that the references to these devices are always performed in the order implied by the program. Refer to Section
3.1.3.2 for details.
2-23
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3.0 Functional Description (Continued)
struction execution means that the CPU completes writing
all previous instructions' results to memory, then begins
fetching and executing the next instruction.
2. Writing to a peripheral port can alter the value read from
another port of the same device. (A characteristic called
here "side-effects of writing"). For example, before reading the counter's value from the NS32202 Interrupt Control Unit it is first necessary to freeze the value by writing
to another control register.
For example, when a new value is loaded into the PSR by
executing an LPRW instruction, the pipeline is flushed and a
serializing operation takes place. This is necessary since
the privilege level might have changed and the instructions
following the LPRW instruction must be fetched again with
the new privilege level.
However, as mentioned above, the NS32GX32 can read the
source operands for one instruction before writing the results of previous instructions unless the addresses indicate
a dependency between the read and write references. Consequently, it is a requirement that read and write references
to peripheral that exhibit side-effects of writing must occur in
the order dictated by the instructions.
The CPU serializes instruction execution after executing one
of the following instructions: BICPSRW, BISPSRW, BPT,
CINV, OIA, FLAG (trap taken), LPR (CFG, INTBASE, PSR,
UPSR, OCR, BPC, OSR, and CAR only), RETT, RETI, and
SVC. Figure 3-4 shows the memory references after serialization.
The NS32GX32 supports 2 methods for handling memorymapped 110. The first method is more general; it satisfies
both requirements listed above and places no restriction on
the location of memory-mapped peripheral devices. The
second method satisfies only the requirement for side effects of writing, and it restricts the location of memorymapped 110 devices, but it is more efficient for devices that
do not have destructive-read ports.
Note 1: LPRB UPSR can be executed in User Mode to serialize instruction
execution.
Note 2: After an instruction that writes a result to memory is executed, the
updating of the result's memory location may be delayed until the
next serializing operation.
Note 3: When reset or a nonrestartable bus error exception occurs, the CPU
discards any results that have not yet been written to memory.
The first method for handling memory-mapped 110 uses two
signals: 10lNH and 100EC. When the NS32GX32 generates
a read bus cycle, it asserts the output signal IOINH if either
of the 110 requirements listed above is not satisfied. That is,
10lNH is asserted during a read bus cycle when (1) the read
reference is for an instruction that may not be executed or
(2) the read reference occurs while a write reference is
pending for a previous instruction. When the read reference
is to a peripheral device that implements ports with destructive-reading or side-effects of writing, the input signal
10DEC must be asserted; in addition, the device must not
be selected if IOINH is active. When the CPU detects that
the 100EC input signal is active while the IOINH output signal is also active, it discards the data read during the bus
cycle and serializes instruction execution. See the next section for details on serializing operations. The CPU then generates the read bus cycle again, this time satisfying the requirements for 1/0 and driving IOINH Inactive.
INSTRUCTION N
INSTRUCTION N+ 1
INSTRUCTION rETCH
INSTRUCTION rETCH
~\ /~\
DATA WRITE
DATA WRITE
TL/EE/10253-11
FIGURE 3·4. Memory References after Serialization
3.1.4 Slave Processor Instructions
The NS32GX32 recognizes two groups of instructions being
executable by external slave processors:
• Floating Point Instructions
• Custom Slave Instructions
Each Slave Instruction Set is enabled by a bit in the Configuration Register (Section 2.1.4). Any Slave Instruction which
does not have its corresponding Configuration Register bit
set will trap as undefined, without any Slave Processor communication attempted by the CPU. This allows software simulation of a non-existent Slave Processor.
The second method for handling memory-mapped 1/0 uses
a dedicated region of memory. The NS32GX32 treats all
references to the memory range from address FFOOOOOO to
address FFFFFFFF inclusive in a special manner.
3.1.4.1 Slave Instruction Protocol
While a write to a location in this range is pending, reads
from locations in the same range are delayed. However,
reads from locations with addresses lower than FFOOOOOO
may occur. Similarly, reads from locations in the above
range may occur while writes to locations outside of the
range are pending.
Slave Processor instructions have a three-byte Basic Instruction field, consisting of an 10 Byte followed by an Operation Word. The 10 Byte has three functions:
1) It identifies the instruction as being a Slave Processor
instruction.
It is to be noted that the CPU may assert IOINH even when
the reference is within the dedicated region. Refer to Section 3.5.8 for more information on the handling of 110 devices.
2) Ifspecifies which Slave Processor will execute It.
3) It determines the format of the following Operation Word
of the instruction.
Upon receiving a Slave Processor Instruction, the CPU initiates the sequence outlined in Figure 3-5. While applying
Status code 11111 (Broadcast 10 Section 3.5.4.1), the CPU
transfers the 10 Byte on bits 024-031, the operation
3.1,3.3 Serializing Operations
After executing certain instructions or processing an exception, the CPU serializes instruction execution. Serializing in-
2-24
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3.0 Functional Description
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SEND OPERAND
(BUS STATUS 11101)
=
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READ RESULT
(BUS STATUS
11101)
=
READ SLAVE STATUS
(BUS STATUS = 11110)
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TL/EE/l02S3-12
FIGURE 3·5. Slave Instruction Protocol: CPU Actions
2-25
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3.0 Functional Description (Continued)
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OPCOOE (HIGH)
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FIGURE 3-6. 10 and Operation Word
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ZERO
TS
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FIGURE 3-7. Slave Processor Status Word
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word on bits 08-023 in a swapped order of bytes and a
non-used byte XXXXXXXX (X = don't care) on bits 00-07
(Figure 3-6).
If the slave asserts FSSR, then the NS32GX32 reads a 32bit status word from the slave. The CPU checks bit 0 in the
slave's status word to determine whether to update the PSR
flags or to process an exception. Figure 3-7 shows the format of the slave's status word.
All slave processors observe the bus cycle and inspect the
identification code. The slave selected by the identification
code continues with the protocol; other slaves wait for the
next slave instruction to be broadcast.
If the Q bit in the status word is 0, the CPU updates the N, Z
and L flags in the PSR.
After transferring the slave instruction, the CPU sends to the
slave any source operands that are located in memory or
the General-Purpose registers. The CPU then waits for the
slave to assert SON or FSSR. While the CPU is waiting, it
can perform bus cycles to fetch instructions and read
source operands for instructions that follow the slave instruction being executed. If there are no bus cycles to perform, the CPU is idle with a special Status indicating that it is
waiting for a slave processor. After the slave asserts SON or
FSSR, the CPU follows one of the two sequences described
below.
If the Q bit in the status word is set to 1, the CPU processes
either a Trap (UNO) if TS is 1 or a Trap (SLAVE) if TS is O.
Note 1: Only the floating·point and custom compare instructions are allowed
to return a value of 0 for the Q bit when the FSSR signal is activat·
ed. All other instructions must always set the Q bit to 1 (to signal a
Trap), when activating FSSR.
Note 2: While executing CINV instruction, the CPU displays the operation
code and source operand using slave processor write bus cycles, as
described in the protocol above. Nevertheless, the CPU does not
wait for SON or FSSR to be asserted while executing these Instruc·
tions. This Information can be used to monitor the contents of the
on·chlp Instruction Cache, and Data Cache.
Note 3: The slave processor must be ready to accept new slave Instruction
at any time, even while the slave Is executing another instruction or
waiting for the CPU to read results.
If the slave asserts SDf'j, then the CPU checks whether the
instruction stores any results to memory or the General-Purpose registers. The CPU reads any such results from the
slave by means of 1 or 2 bus cycles and updates the destination.
2-26
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3.0 Functional Description
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(Continued)
3.1.4.2 Floating Point Instructions
in any format; the size is determined by the suffix on the
mnemonic. Similarly, an "i" indicates an integer size (Byte,
Word, Double Word) selected by the corresponding mnemonic suffix.
Table 3-1 gives the protocols followed for each Floating
Point instruction. The instructions are referenced by their
mnemonics. For the bit encodings of each instruction, see
Appendix A.
Any operand indicated as being of type "c" will not cause a
transfer if the register addressing mode is specified. It is
assumed in this case that the slave processor is already
holding the operand internally.
The Operand class columns give the Access Class for each
general operand, defining how the addressing modes are
interpreted (see Instruction Set Reference Manual).
For the instruction encodings, see Appendix A.
The Operand Issued columns show the sizes of the operands issued to the Floating Point Unit by the CPU. liD" indicates a 32-bit Double Word. "i" indicates that the instruction
specifies an integer size for the operand (B = Byte, W =
Word, D = Double Word). "f" indicates that the instruction
specifies a Floating Point size for the operand (F = 32-bit
Standard Floating, L = 64-bit Long Floating).
3.2 EXCEPTION PROCESSING
Exceptions are special events that alter the sequence of
instruction execution. The CPU recognizes three basic types
of exceptions: interrupts, traps and bus errors.
An interrupt occurs in response to an event signalled by
activating the NMI or INT input signals. Interrupts are typically requested by peripheral devices that require the CPU's
attention.
The Returned Value Type and Destination column gives the
size of any returned value and where the CPU places it. The
PSR-Bits-Affected column indicates which PSR bits, if any,
are updated from the Slave Processor Status Word (Figure
3-7).
Traps occur as a result either of exceptional conditions
(e.g., attempted division by zero) or of specific instructions
whose purpose is to cause a trap to occur (e.g., supervisor
call instruction).
Any operand indicated as being of type "f" will not cause a
transfer if the Register addressing mode is specified. This is
because the Floating Point Registers are physically on the
Floating Point Unit and are therefore available without CPU
assistance.
A bus error exception occurs when the BER signal is activated during an instruction fetch or data transfer required by
the CPU to execute an instruction.
When an exception is recognized, the CPU saves the PC,
PSR and optionally the MOD register contents on the interrupt stack and then it transfers control to an exception service procedure.
3.1.4.3 Custom Slave Instructions
Provided in the NS32GX32 is the capability of communicating with a user-defined, "Custom" Slave Processor. The instruction set provided for a Custom Slave Processor defines
the instruction formats, the operand classes and the communication protocol. Left to the user are the interpretations
of the Op Code fields, the programming model of the Custom Slave and the actual types of data transferred. The protocol specifies only the size of an operand, not its data type.
Details on the operations performed in the various cases by
the CPU to enter and exit the exception service procedure
are given in the following sections.
It is to be noted that the reset operation is not treated here
as an exception. Even though, like any exception, it alters
the instruction execution sequence.
Table 3-2 lists the relevant information for the Custom Slave
instruction set. The designation "c" is used to represent an
operand which can be a 32-bit (liD") or 64-bit ("Q") quantity
The reason being that the CPU handles reset in a significantly different way than it does for exceptions.
Refer to Section 3.5.3 for details on the reset operation.
2-27
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C")
•
C")
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N
3.0 Functional Description (Continued)
TABLE 3·1. Floating Point Instruction Protocols
CJ
N
C")
(J)
Mnemonic
Z
.......
It)
N
N
•
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CJ
C")
N
C")
(J)
Z
.......
0
N
N
·
C")
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CJ
N
C")
(J)
Z
ADDf
SUSf
MULf
DIVf
MOVf
ASSf
NEGf
CMPf
FLOORfi
TRUNCfi
ROUNDfi
MOVFL
MOVLF
MOVif
LFSR
SFSR
POLYf
DOTf
SCALSf
LOGSf
Operand 1
Class
read.f
read.f
read.f
read.f
read.f
read.f
read.f
read.f
read.f
read.f
read.f
read.F
read.L
read.i
read.D
Operand 2
Class
rmw.f
rmw.f
rmw.f
rmw.f
write.f
write.f
write.f
read.f
write.i
write.i
write.i
write.L
write.F
write.f
N/A
write.D
read.f
read.f
rmw.f
write.f
read.f
read.f
read.f
read.f
N/A
Operand 1
Issued
f
Operand 2
Issued
f
f
N/A
N/A
N/A
Returned Value
Type and Dest.
ftoOp.2
ftoOp.2
ftoOp.2
fto Op.2
fto Op.2
fto Op.2
fto Op.2
DtoOp.2
fto FO
fto FO
ftoOp.2
ftoOp.2
PSR Bits
Affected
none
none
none
none
none
none
none
N,Z,L
none
none
none
none
none
none
none
none
none
none
none
none
Returned Value
Type and Dest.
ctoOp.2
ctoOp.2
ctoOp.2
cto Op.2
ctoOp.2
ctoOp.2
ctoOp.2
ctoOp.2
N/A
N/A
itoOp.2
itoOp.2
itoOp.2
ctoOp.2
QtoOp.2
DtoOp.2
N/A
DtoOp.2
N/A
D to Op.1
PSR Bits
Affected
none
none
none
none
none
none
none
none
N,Z,L
N,Z,L
none
none
none
none
none
none
none
none
none
none
N/A
F
L
i
D
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
f
N/A
itoOp.2
itoOp.2
itoOp.2
L to Op.2
FtoOp.2
fto Op.2
N/A
TABLE 3·2. Custom Slave Instruction Protocols
Mnemonic
CCALOc
CCAL1c
CCAL2c
CCAL3c
CMOVOc
CMOV1c
CMOV2c
CMOV3c
CCMPOc
CCMP1c
CCVOci
CCV1ci
CCV2ci
CCV3ic
CCV4DQ
CCV5QD
LCSR
SCSR
LCR·
SCR·
Operand 1
Class
read.c
read.c
read.c
read.c
read.c
read.c
read.c
read.c
read.c
read.c
read.c
read.c
read.c
read.i
read.D
read.Q
read.D
N/A
read.D
write.D
Operand 2
Class
rmw.c
rmw.c
rmw.c
rmw.c
write.c
write.c
write.c
write.c
read.c
read.c
write.i
write.i
write.i
write.c
write.Q
write.D
N/A
write.D
N/A
N/A
Operand 1
Issued
c
c
c
c
c
c
c
c
c
c
c
c
c
i
D
Q
D
N/A
D
N/A
Note:
o = Double Word
I = Integer size (B,W,D) specified in mnemonic.
c = Custom size (0:32 bits or Q:64 bits) specified in mnemonic.
• = Privileged Instruction: will trap if CPU is in User Mode.
NI A = Not Applicable to this instruction.
2·28
Operand 2
Issued
c
c
c
c
N/A
N/A
N/A
N/A
c
c
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
z
3.0 Functional Description
en
w
(Continued)
3.2.1 Exception Acknowledge Sequence
reads the double·word entry from the Interrupt Dispatch tao
ble at address 'INTBASE + vector x 4'. See Figures 3·8
and 3·9. The CPU uses this entry to call the exception servo
ice procedure, interpreting the entry as an external proce·
dure descriptor.
A new module number is loaded into the MOD register from
the least·significant word of the descriptor, and the static·
base pointer for the new module is read from memory and
loaded into the SB register. Then the program·base pointer
for the new module is read from memory and added to the
most·significant word of the module descriptor, which is in·
terpreted as an unsigned value. Finally, the result is loaded
into the PC register.
When an exception is recognized, the CPU goes through
three major steps:
1) Adjustment of Registers. Depending on the source of the
exception, the CPU may restore and/or adjust the con·
tents of the Program Counter (PC), the Processor Status
Register (PSR) and the currently·selected Stack Pointer
(SP). A copy of the PSR is made, and the PSR is then set
to reflect Supervisor Mode and selection of the Interrupt
Stack. Trap (TRC) and Trap (OVF) are always disabled.
Maskable interrupts are also disabled if the exception is
caused by an interrupt, Trap (DBG), Trap (ABT) or bus
error.
2) Vector Acquisition. A vector is either obtained from the
data bus or is supplied internally by default.
Direct-Exception Mode Enabled
Direct-Exception Mode Disabled
The Direct·Exception mode is disabled while the DE bit in
the CFG register is 0 (Section 2.1.4). In this case the CPU
first pushes the saved PSR copy along with the contents of
the MOD and PC registers on the interrupt stack. Then it
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........
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en
w
~
The Direct·Exception mode is enabled when the DE bit in
the CFG register is set to 1. In this case the CPU first
pushes the saved PSR copy along with the contents of the
PC register on the Interrupt Stack. The word stored on the
Interrupt Stack between the saved PSR and PC register is
reserved for future use; its contents are undefined. The CPU
then reads the double·word entry from the Interrupt Dis·
patch Table at address 'INTBASE + vector x 4'. The CPU
uses this entry to call the exception service procedure, inter·
preting the entry as an absolute address that is simply load·
ed into the PC register. Figure 3·10 provides a pictorial of
the acknowledge sequence. It is to be noted that while the
3) Service Call. The CPU performs one of two sequences
common to all exceptions to complete the acknowledge
process and enter the appropriate service procedure.
The selection between the two sequences depends on
whether the Direct·Exception mode is disabled or en·
abled.
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MEMORY
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NON-VECTORED INTERRUPT
1
NUl
NO~ASKABLEINTERRUPT
2
RESERVED
3
SLAVE
SLAVE PROCESSOR TRAP
CASCADE AD DR 0
·
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CASCADE TABLE
~~
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CASCADE ADDR 14
",,"AUPT ••
I
CASCADE ADDR 15
AEGISTER
J
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FIXED INTERRUPTS
AND TRAPS
r
VECTORED
INTERRUPTS
DISPATCH TABLE
:t
4
ILL
ILLEGAL OPERATION TRAP
5
SVC
SUPERVISOR CALL TRAP
1
DVZ
DIVIDE BY ZERO TRAP
7
FLG
FLAG TRAP
1
BPT
BREAKPOINT TRAP
8
TRC
TRACE TRAP
10
UND
UNDEFINED INSTRUCTION TRAP
11
RBE
RESTARTABLE BUS ERROR
12
NBE
NON-RESTARTABLE BUS ERROR
13
OVF
INTEGER OVERFLOW TRAP
14
DBG
DEBUG TRAP
15
RESERVED
11
VECTORED
INTERRUPTS
1"1."
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TL/EE/10253-13
FIGURE 3-8. Interrupt Dispatch Table
2·29
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3.0 Functional Description
(Continued)
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STATUS
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MODULE
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MOD
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MOD
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CASCADE TABLE
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DISPATCH
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-111---r-l---111---1
DESCRIPTOR
a
1_-
OFFSET
MODULE
0
1
MOD REGISTER ~
I
MODULE TABLE
NEW MODULE
I
MODULE TABLE ENTRY
j
MODULE TABLE ENTRY
32
- r-----,
STATIC BASE POINTER
UNK BASE POINTER
~
PROGRAM BASE POINTER
i'
(RESERVED)
SBREGISTER
PROGRAM COUNTER
I
I
4-
ENTRY POINT ADDRESS
NEW STATIC BASE
FIGURE 3-9. Exception Acknowledge Sequence.
Direct-Exception Mode Disabled.
2-30
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TL/EE/l0253-15
3.0 Functional Description
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(Continued)
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(PUSH)
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ENTRY POINT ADDRESS
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TL/EE/l0253-17
FIGURE 3-10. Exception Acknowledge Sequence.
Direct-Exception Mode Enabled.
direct-exception mode is enabled, the CPU can respond
more quickly to interrupts and other exceptions because
fewer memory references are required to process an exception. The MOD and S8 registers, however, are not initialized
before the CPU transfers control to the service procedure.
Consequently, the service procedure is restricted from executing any instructions, such as CXP, that use the contents
of the MOD or S8 registers in effective address calculations.
mode procedures, RETT can also adjust the Stack Pointer
(SP) to discard a specified number of bytes from the original
stack as surplus parameter space.
RETI is used to return from a maskable interrupt service
procedure. A difference of RETT, RETI also informs any
external interrupt control units that interrupt service has
completed. Since interrupts are generally asynchronous external events, RETI does not discard parameters from the
stack.
80th of the above instructions always restore the Program
Counter (PC) and the Processor Status Register from the
interrupt stack. If the Direct-Exception mode is disabled,
they also restore the MOD and S8 register contents. Figures 3-11 and 3-12 show the RETT and RETI instruction
flows when the Direct-Exception mode is disabled.
3.2.2 Returning from an Exception Service Procedure
To return control to an interrupted program, one of two instructions can be used: RETT (Return from Trap) and RETI
(Return from Interrupt).
RETT is used to return from any trap, non-maskable interrupt or bus error service procedure. Since some traps are
often used deliberately as a call mechanism for supervisor
2-31
PI
o
M
N
M
•
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3.0 Functional Description
(Continued)
CJ
1+---32 BITS _
N
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PROGRAM COUNTER
(J)
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N
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•
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I
I
~ETURN ADDRESS
STATUS
I
PSR
MODULE
I
~O~
--li----------I---
+-__
PC
~------~----~
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CJ
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M
MODULE
TABLE
(J)
Z
MODULE TABLE ENTRY
t
MODULE TABLE ENTRY
STATIC BASE POINTER
-
""""
LINK BASE POINTER
PROGRAM BASE POINTER
~~------------~
LOWER
ADDRESSES
(RESERVED)
PARAMETERS
n
BYTES
SBREGISTER
STATIC BASE
STACK SELECTED
IN NEWLY·
POPPEDPSR.
HIGHER
ADDRESSES
POP AND
DISCARD
TLlEE/10253-18
FIGURE 3-11. Return from Trap (RETT n) Instruction Flow.
Direct-Exception Mode Disabled.
3.2.3 Maskable Interrupts
3.2.3.2 Vectored Mode: Non-Cascaded Case
The INT pin is a level-sensitive input. A continuous low level
is allowed for generating multiple interrupt requests. The input is maskable, and is therefore enabled to generate interrupt requests only while the Processor Status Register I bit
is set. The I bit is automatically cleared during service of an
INT, NMI, Trap (DBG), or Bus Error request, and is restored
to its original setting upon return from the interrupt service
routine via the RETT or RETI instruction.
The INT pin may be configured via the SETCFG instruction
as either Non-Vectored (CFG Register bit I = 0) or Vectored (bit I = 1).
In the Vectored mode, the CPU uses an Interrupt Control
Unit (ICU) to prioritize many interrupt requests. Upon receipt
of an interrupt request on the INT pin, the CPU performs an
"Interrupt Acknowledge, Master" bus cycle (Section
3.5.4.6) reading a vector value from the low-order byte of
the Data Bus. This vector is then used as an index into the
Dispatch Table in order to find the External Procedure Descriptor for the proper interrupt service procedure. The service procedure eventually returns via the Return from Interrupt (RETI) instruction, which performs an End of Interrupt
bus cycle, informing the ICU that it may re-prioritize any interrupt requests still pending. The ICU provides the vector
number again, which the CPU uses to determine whether it
needs also to inform a Cascaded ICU (see below).
3.2.3.1 Non-Vectored Mode
In the Non-Vectored mode, an interrupt request on the INT
pin will cause an Interrupt Acknowledge bus cycle, but the
CPU will ignore any value read from the bus and use instead
a default vector of zero. This mode is useful for small systems in which hardware interrupt prioritization is unnecessary.
In a system with only one ICU (16 levels of interrupt), the
vectors provided must be in the range of 0 through 127; that
is, they must be positive numbers in eight bits. By providing
2-32
z
3.0 Functional Description
en
w
(Continued)
N
C)
><
W
·
N
N
"END OF INTERRUPT"
o
......
BUS CYCLE
Z
en
w
N
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N
N
·
INTERRUPT
CONTROl
UNIT
C11
......
Z
en
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I--- 32 BITS - - t
PROGRAM COUNTER
STATUS
I
I
MODULI!
PaR
~:r-
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(POP)
I
RETURN ADDRESS
N
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LOWER
ADDRESSES
W
o
PC
____
(P_OP)
_ _ _ _- t - PSR
I
MOD
MOD
INTERRUPT
STACK
HIGHER
ADDRESSES
MODULE
TABLE
,
L . . - - - - - - - - - - - . - j M O O U L E TABLE ENTRY
J
MODULE TABLI! ENTRY
STATIC BASI! POINTER
- ~
LINK BASE POINTER
PROGRAM BASE POINTER
(RESERVED)
STATICBUE
SBREGISTER
TL/EE/l0253-19
FIGURE 3-12. Return from Interrupt (RETI) Instruction Flow.
Direct-Exception Mode Disabled.
2-33
o('I)
·
N
3.0 Functional Description
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C!J
a negative vector number, an ICU flags the interrupt source
as being a Cascaded ICU (see below).
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.......
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N
N
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(Continued)
3.2.3.3 Vectored Mode: Cascaded Case
In order to allow more levels of interrupt, provision is made
in the CPU to transparently support cascading. Note that
the Interrupt output from a Cascaded ICU goes to an Interrupt Request input of the Master ICU, which is the only ICU
which drives the CPU INT pin. Refer to the ICU data sheet
for details.
Z
In a system which uses cascading, two tasks must be performed upon initialization:
N
N
1) For each Cascaded ICU in the system, the Master ICU
must be informed of the line number on which it receives
the cascaded requests.
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.......
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N
('I)
t/)
Z
3.2.4 Non-Maskable Interrupt
The Non-Maskable Interrupt is triggered whenever a falling
edge is detected on the NMI pin. The CPU performs an
"Interrupt Acknowledge, Master" bus cycle (Section
3.5.4.6) when processing of this interrupt actually begins.
The Interrupt Acknowledge cycle differs from that provided
for Maskable Interrupts in that the address presented is
FFFFFF0016. The vector value used for the Non-Maskable
Interrupt is taken as 1, regardless of the value read from the
bus.
The service procedure returns from the Non-Maskable Interrupt using the Return from Trap (RETI) instruction. No
special bus cycles occur on return.
3.2.5 Traps
Traps are processing exceptions that are generated as direct results of the execution of an instruction.
2) A Cascade Table must be established in memory. The
Cascade Table is located in a NEGATIVE direction from
the location indicated by the CPU Interrupt Base (INTBASE) Register. Its entries are 32-bit addresses, pointing
to the Vector Registers of each of up to 16 Cascaded
ICUs.
The return address saved on the stack by any trap except
Trap (TRC) and Trap (OBG) is the address of the first bye of
the instruction during which the trap occurred.
When a trap is recognized, maskable interrupts are not disabled except for the case of Trap (OBG).
Figure 3-9 illustrates the position of the Cascade Table. To
find the Cascade Table entry for a Cascaded ICU, take its
Master ICU line number (0 to 15) and subtract 16 from it,
giving an index in the range -16 to -1. Multiply this value
by 4, and add the resulting negative number to the contents
of the INTBASE Register. The 32-bit entry at this address
must be set to the address of the Hardware Vector Register
of the Cascaded ICU. This is referred to as the "Cascade
Address."
There are 10 trap conditions recognized by the NS32GX32
as described below.
Trap (SLAVE): An exceptional condition was detected by
the Floating Point Unit or another Slave Processor during
the execution of a Slave Instruction. This trap is requested
via the Status Word returned as part of the Slave Processor
Protocol (Section 3.1.4.1).
Trap (ILL): Illegal operation. A privileged operation was attempted while the CPU was in User Mode (PSR bit U = 1).
Upon receipt of an interrupt request from a Cascaded ICU,
the Master ICU interrupts the CPU and provides the negative Cascade Table index instead of a (positive) vector number. The CPU, seeing the negative value, uses it as an index
into the Cascade Table and reads the Cascade Address
from the referenced entry. Applying this address, the CPU
performs an "Interrupt Acknowledge, Cascaded" bus cycle,
reading the final vector value. This vector is interpreted by
the CPU as an unsigned byte, and can therefore be in the
range of 0 through 255.
In returning from a Cascaded interrupt, the service procedure executes the Return from Interrupt (RETI) instruction,
as it would for any Maskable Interrupt. The CPU performs
an "End of Interrupt, Master" bus cycle, whereupon the
Master ICU again provides the negative Cascade Table index. The CPU, seeing a negative value, uses it to find the
corresponding Cascade Address from the Cascade Table.
Applying this address, it performs an "End of Interrupt, Cascaded" bus cycle, informing the Cascaded ICU of the completion of the service routine. The byte read from the Cascaded ICU is discarded.
Trap (SVC): The Supervisor Call (SVC) instruction was executed.
Trap (OVZ): An attempt was made to divide an integer by
zero. (The FPU trap is used for Floating Point division by
zero.)
Trap (FLG): The FLAG instruction detected a "1" in the
PSR F bit.
Trap (BPT): The Breakpoint (BPT) instruction was executed.
Trap (TRC): The instruction just completed is being traced.
Refer to Section 3.3.1 for details.
Trap (UNO): An Undefined-Instruction trap occurs when an
attempt to execute an instruction is made and one or more
of the following conditions is detected:
1. The instruction is undefined. Refer to Appendix A for a
description of the codes that the CPU recognizes to be
undefined.
2. The instruction is a floating point instruction and the F-bit
in the CFG register is O.
Note: If an interrupt must be masked off, the CPU can do so by setting the
corresponding bit In the interrupt mask register of the interrupt controller.
3. The instruction is a custom slave instruction and the C-bit
in the CFG register is O.
4. The reserved general adressing mode encoding (10011)
is used.
However, if an interrupt Is set pending during the CPU Instruction that
masks off that interrupt, the CPU may still perform an interrupt ac·
knowledge cycle following that instruction since it might have sampled
the iNT line before the ICU deasserted it. This could cause the ICU to
provide an invalid vector. To avoid this problem the above operation
should be performed with the CPU Interrupt disabled.
5. Immediate addressing mode is used for an operand that
has access class different from read.
2-34
z
3.0 Functional Description
en
w
(Continued)
6. Scaled Indexing is used and the basemode is also Scaled
Indexing.
In this case, any results that have not yet been written to
memory are discarded, and any pending traps other than
Trap (DBG) for external condition, are eliminated. The PC
value saved on the stack is undefined.
7. The instruction is a floating-point or custom slave instruction that the FPU or custom slave detects to be undefined. Refer to Section 3.1.4.1 for more information.
The NS32GX32 does not respond to bus errors indicated
for instructions that are not executed. For example, no bus
error exception occurs in response to asserting the BER
signal during a bus cycle to prefetch an instruction that is
not executed because the previous instruction caused a
trap.
Trap (OVF): An Integer-Overflow trap occurs when the V-bit
in the PSR register is set to 1 and an Integer-Overflow condition is detected during the execution of an instruction. An
Integer-Overflow condition is detected in the following cases:
If a bus error is detected during a data transfer required for
the processing of another exception or during the ICU read
cycle of a RETI instruction, then the CPU considers it as a
fatal bus error and enters the 'HALTED' state.
1. The F-flag is 1 following execution of an ADDi, ADDQi,
ADDCi, SUBi, SUBCi, NEGi, ABSi, or CHECKi instruction.
2. The product resulting from a MULi instruction cannot be
represented exactly in the destination operand's location.
Note 1: If the address and control signals associated with the last bus cycle
that caused a bus error are latched by external hardware, then the
information they provide can be used by the service procedure for
restartable bus errors to analyze and resolve the exception recognized by the CPU. This can be accomplished because upon detecting a restartable bus error, the NS32GX32 stops making memory
references for subsequent instructions until it determines whether
the instruction that caused the bus error is executed and the exception is processed.
3. The quotient resulting from a DEli, DIVi, or QUOi instruction cannot be represented exactly in the destination operand's location.
4. The result of an ASHi instruction cannot be represented
exactly in the destination operand's location.
5. The sum of the 'INC' value and the 'INDEX' operand for
an ACBi instruction cannot be represented exactly in the
index operand's location.
Note 2: When a non-restartable bus error is recognized, the service procedure must execute the CINV instruction to invalidate the on-chip
caches. This is necessary to maintain coherence between them and
external memory.
Trap (DB G): A debug trap occurs when one or more of the
conditions selected by the settings of the bits in the DCR
register is detected. This trap can also be requested by activating the input signal DBG. Refer to Section 3.3.2 for more
information.
3.2.7 Priority Among Exceptions
The CPU checks for specific exceptions at various pOints
while executing an instruction. It is possible that several exceptions occur simultaneously. In that event, the CPU responds to the exception with highest priority.
Note 1: Following execution of the WAIT instruction, then a Trap (OBG) can
be pending for a PC-match condition. In such an event, the Trap
(OBG) is processed immediately.
Figure 3-13 shows an exception processing flowchart. A
non-restartable bus error is assigned highest priority and is
serviced immediately regardless of the execution state of
the CPU.
Note 2: If an attempt is made to execute a privileged custom instruction
while in User-Mode and the C-bit in the CFG register is 0, then Trap
(UNO) occurs.
Note 3: While operating in User-Mode, if an attempt is made to execute a
privileged instruction with an undefined use of a general addressing
mode (either the reserved encoding is used or else scaled-index or
immediate modes are incorrectly used), the Trap (UNO) occurs.
Before executing an instruction, the CPU checks for pending Trap (DBG), interrupts, and Trap (TRC), in that order. If a
Trap (DBG) is pending, then the CPU processes that exception, otherwise the CPU checks for pending interrupts. At
this point, the CPU responds to any pending interrupt requests; nonmaskable interrupts are recongized with higher
priority than maskable interrupts. If no interrupts are pending, then the CPU checks the P-flag in the PSR to determine
whether a Trap (TRC) is pending. If the P-flag is 1, a Trap
(TRC) is processed. If no Trap (DBG), interrupt or Trap
(TRC) is pending, the CPU begins executing the instruction.
Note 4: If an undefined instruction or illegal operation is detected, then no
data references are performed for the instruction.
Note 5: For certain instructions that are relatively long to execute, such as
OEIO, the CPU checks for pending interrupts during execution of the
instruction. In order to reduce interrupt latency, the NS2532 can
suspend executing the instruction and process the interrupt. Refer
to Section B.5 in Appendix B for more information about recognizing
interrupts in this manner.
3.2.6 Bus Errors
A bus error exception occurs when the BER signal is asserted in response to an instruction fetch or data transfer that is
required to execute an instruction.
While executing an instruction, the CPU may recognize up
to three exceptions:
Two types of bus errors are recognized: Restartable and
Non-Restartable. Restartable bus errors are recognized during read bus cycles. All other bus errors are non-restartable.
2. trap (DBG) or interrupt, if the instruction is interruptible
1. restartable bus error
3. one of 7 mutually exclusive traps: SLAVE, ILL, SVC, DVZ,
FLG, BPT, UND
The CPU responds to restartable bus errors by suspending
the instruction that it was executing. When a non-restartable
bus error is detected, the CPU responds immediately and
the instruction being executed is terminated.
If no exception is detected while the instruction is executing,
then the instruction is completed and the PC is updated to
point to the next instruction. If a Trap (OVF) is detected,
then it is processed at this time.
2-35
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FIGURE 3·13. Exception Processing Flowchart
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3.0 Functional Description
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While executing the instruction, the CPU checks for enabled
debug conditions. If an enabled debug condition is met, a
Trap (DBG) is held pending until after the instruction is completed (see Note 3). If another exception is detected before
the instruction is completed, the pending Trap (DBG) is removed and the DSR register is not updated.
Note 1: Trap (DBG) can be detected simultaneously with Trap (OVF). In this
event, the Trap (OVF) is processed before the Trap (DBG).
Note 2: An address·compare debug condition can be detected while processing a bus error, interrupt, or trap. In this event, the Trap (DBG)
is held pending until after the CPU has processed the first exception.
7. If "Byte" is in the range -16 through -1, then the interrupt source is Cascaded. (More negative values are reserved for future use.) Perform the following:
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a. Read the 32-bit Cascade Address from memory. The
address is calculated as INTBASE + 4* Byte.
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b. Read "Vector," applying the Cascade Address just
read and Status Code 00101 (Interrupt Acknowledge,
Cascaded).
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8. Perform Service (Vector, Return Address), Figure 3-14.
3.2.8.2 Restartable Bus Error Sequence
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2. Clear the PSR P bit.
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3.2.8 Exception Acknowledge Sequences: Detailed Flow
3. Copy the PSR into a temmporary register, then clear PSR
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For purposes of the following detailed discussion of exception acknowledge sequences, a single sequence called
"service" is defined in Figure 3-14.
4. Set "Vector" to 11.
5. Set "Return Address" to the address of the first byte of
Note 3: Between operations of a string instruction, the CPU responds to
pending operand address compare and external debug conditions
as well as interrupts. If a PC-match debug condition is detected
while executing a string instruction, then Trap (DBG) is held pending
until the instruction has completed.
bits T, V, U, S and I.
the suspended instruction.
Upon detecting any interrupt request, trap or bus error condition, the CPU first performs a sequence dependent upon
the type of exception. This sequence will include saving a
copy of the Processor Status Register and establishing a
vector and a return address. The CPU then performs the
service sequence.
6. Perform Service (Vector, Return Address), Figure 3-14.
3.2.8.3 SLAVE/ILL/SVC/DVZ/FLG/BPTlUND Trap
Sequence
1. Restore the currently selected Stack Pointer and the
Processor Status Register to their original values at the
start of the trapped instruction.
3.2.8.1 Maskable/Non-Maskable Interrupt Sequence
This sequence is performed by the CPU when the NMI pin
receives a falling edge, or the INT pin becomes active with
the PSR I bit set. The interrupt sequence begins either at
the next instruction boundary or, in the case of an interruptible instruction (e.g., string instruction), at the next interruptible point during its execution.
2. Set "Vector" to the value corresponding to the trap type.
SLAVE:
ILL:
SVC:
DVZ:
FLG:
BPT:
UND:
1. If an interruptible instruction was interrupted and not yet
completed:
a. Clear the Processor Status Register P bit.
Vector = 3.
Vector = 4.
Vector = 5.
Vector = 6.
Vector = 7.
Vector = 8.
Vector = 10.
b. Set "Return Address" to the address of the first byte of
the interrupted instruction.
3. If Trap (ILL) or Trap (UND)
Otherwise, set "Return Address" to the address of the
next instruction.
4. Copy the Processor Status Register (PSR) into a tempo-
2. Copy the Processor Status Register (PSR) into a temporary register, then clear PSR bits T, V, U, S, P and I.
5. Set "Return Address" to the address of the first byte of
3. If the interrupt is Non-Maskable:
6. Perform Service (Vector, Return Address), Figure 3-14.
a. Clear the Processor Status Register P bit.
rary register, then clear PSR bits T, V, U, Sand P.
the trapped instruction.
a. Read a byte from address FFFFFF0016, applying
Status Code 00100 (Interrupt Acknowledge, Master).
Discard the byte read.
3.2.8.4 Trace Trap Sequence
1. In the Processor Status Register (PSR), clear the P bit.
2. Copy the PSR into a temporary register, then clear PSR
bits T, V, U and S.
b. Set "Vector" to 1.
c. Go to Step 8.
3. Set "Vector" to 9.
4. Set "Return Address" to the address of the next instruction.
5. Perform Service (Vector, Return Address), Figure 3-14.
4. If the interrupt is Non-Vectored:
a. Read a byte from address FFFFFE0016, applying
Status Code 00100 (Interrupt Acknowledge, Master).
Discard the byte read.
b. Set "Vector" to O.
3.2.8.5 Integer-Overflow Trap Sequence
c. Go to Step 8.
1. Copy the PSR into a temporary register, then clear PSR
bits T, V, U, Sand P.
5. Here the interrupt is Vectored. Read "Byte" from address
2. Set "Vector" to 13.
FFFFFE0016, applying Status Code 00100 (Interrupt Acknowledge, Master).
6. If "Byte"
8.
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0, then set "Vector" to "Byte" and go to Step
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Functional Description (Continued)
3. Set "Return Address" to the address of the next instruction.
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4. Perform Service (Vector, Return Address), Figure 3-14.
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Besides the Breakpoint (BPT) instruction that can be used
to generate soft breaks, the CPU also provides instruction
tracing as well as debug trap (or hardware breakpoints) ca·
pabilities. Details on these features are provided in the fol·
lowing sub-sections.
A debug condition can be recognized either at the next instruction boundary or, in the case of an interruptible instruction, at the next interruptible point during its execution.
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3.3 DEBUGGING SUPPORT
The NS32GX32 provides serveral features to assist in pro·
gram debugging.
3.3.1 Instruction Tracing
Instruction tracing is a very useful feature that can be used
during debugging to single-step through selected portions of
a program. Tracing is enabled by setting the T-bit in the PSR
Register. When enabled, the CPU generates a Trace Trap
(TRG) after the execution of each instruction.
c. Go to Step 4.
At the beginning of each instruction, the T bit is copied into
the PSR P (Trace "Pending") bit. If the P bit is set at the end
of an instruction, then the Trace Trap is activated. If any
other trap or interrupt request is made during a traced in·
struction, its entire service procedure is allowed to complete
before the Trace Trap occurs. Each interrupt and trap se·
quence handles the P bit for proper tracing, guaranteeing
only one Trace Trap per instruction, and guaranteeing that
the Return Address pushed during a Trace Trap is always
the address of the next instruction to be traced.
3. Set "Return Address" to the address of the next instruction.
4. Set "Vector" to 14.
5. Copy the Processor Status Register (PSR) into a temporary register, then clear PSR bits T, V, U, S, P and I.
6. Perform Service (Vector, Return Address), Figure 3-14.
3.2.8.7 Non-Restartable Bus Error Sequence
1. Set "Vector" to 12.
Due to the fact that some instructions can clear the T and P
bits in the PSR, in some cases a Trace Trap may not occur
at the end of the instruction. This happens when one of the
privileged instructions BICPSRW or LPRW PSR is executed.
2. Set "Return Address" to "Undefined".
3. Copy the Processor Status Register (PSR) into a temporary register, then clear PSR bits T, V, U, S, P and I.
4. Perform a dummy read of the Slave Status Word to reset
the Slave Processor.
5. Perform Service (Vector, Return Address), Figure 3-14.
TABLE 3-3. Summary of Exception Processing
Instruction
Ending
Cleared Before
Saving PSR
Cleared After
Saving PSR
Suspended
Terminated
P
Undefined
TVUSI
TVUSPI
Interrupt
Before Instruction
None/P*
TVUSPI
ILL, UNO
SLAVE,SVC, DVZ, FLG,BPT
OVF
TRC
DBG
Suspended
Suspended
Completed
Before Instruction
Before Instruction
P
None
None
P
TVUS
TVUSP
TVUSP
TVUS
TVUSPI
Exception
Restartable Bus Error
Nonrestartable Bus Error
None/P*
'Note: The P bit of the saved PSR is cleared in case the exception is acknowledged before the instruction is completed (e.g., interrupted string instruction). This is
to avoid a mid-instruction trace trap upon return from the Exception Service Routine.
Service (Vector, Return Address):
1) Push the PSR copy onto the Interrupt Stack as a 16-blt value.
2) If Direct-Exception mode Is selected, then go to step 4.
3) Push MOD Register Into the Interrupt Stack as a 16-blt value.
4) Read 32-blt Interrupt Dispatch Table (lOT) entry at address 'INTBASE
+
vector x 4'.
5) If Direct-Exception mode Is selected, then go to Step 10.
6) Move the L.S. word of the lOT entry (Module Field) Into the MOD register.
7) Read the Program Base pOinter from memory address 'MOD
Program counter.
+ S',and add to It the M.S. word of the lOT entry (Offset Field), placing the result In the
S) Read the new Static Base pOinter from the memory address contained In MOD, plaCing It Into the SB Register.
9) Go to Step 11.
10) Place lOT entry In the Program Counter.
11) Push the Return Address onto the Interrupt Stack as a 32-blt quantity.
12) Serialize: Non-sequentially fetch first Instruction of Exception Service Routine.
Note: Some of the Memory Accesses indicated in the service sequence may be performed in an order different from the one shown.
FIGURE 3-14. Service Sequence
2-38
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3.0 Functional Description
(Continued)
In other cases, it is still possible to guarantee that a Trace
Trap occurs at the end of the instruction, provided that special care is taken before returning from the Trace Trap Service Procedure. In case a BICPSRB instruction has been executed, the service procedure should make sure that the T
bit in the PSR copy saved on the Interrupt Stack is set before executing the RETT instruction to return to the program
begin traced. If the RETT or RETI instructions have to be
traced, the Trace Trap Service Procedure should set the P
and T bits in the PSR copy on the Interrupt Stack that is
going to be restored in the execution of such instructions.
signal at the beginning of the next instruction, synchronously with PFS. If the instruction is not completed because a
higher priority trap is detected, the BP signal mayor may not
be asserted.
Note 1: The assertion of BP is not affected by the setting of the TR bit in the
DCR register.
Note 2: While executing the MOVUS and MOVSU instructions, the com·
pare·address condition is enabled for the User space memory refer·
ence under control of the UD·bit in the DCR.
Note 3: When the LPRi instruction is executed to load a new value into the
BPC, CAR or DCR, it is undefined whether the address·compare
and PC-match conditions, in effect while executing the instruction,
are detected under control of the old or new contents of the loaded
register. Therefore, any LPRi instruction that alters the control of the
address-compare or PC-match conditions should use register or immediate addressing mode for the source operand.
Note: If instruction tracing is enabled while the WAIT instruction is executed,
the Trap (TRG) occurs after the next interrupt, when the interrupt
service procedure has returned.
3.3.2 Debug Trap Capability
The CPU recognizes three different conditions to generate a
Debug Trap:
1) Address Compare
3.4 ON-CHIP CACHES
The NS32GX32 provides two on-chip caches: the Instruction Cache (IC) and the Data Cache (DC).
2) PC Match
3) External
These are used to hold the contents of frequently used
memory locations.
The IC and DC can be individually enabled by setting appropriate bits in the CFG Register (See Section 2.1.4).
These conditions can be enabled and monitored through
the CPU Debug Registers.
The CPU also provides a locking feature that allows the
contents of the IC and DC to be locked to specific memory
locations. This is accomplished by setting the LlC and LDC
bits in the CFG register.
Cache locking can be successfully used in real-time applications to guarantee fast access to critical instruction and data
areas.
Details on the organization and function of each of the
caches are provided in the following sections.
An address-compare condition is detected when certain
memory locations are either read or written. The doubleword address used for the comparison is specified in the
CAR Register. The address-compare condition can be separately enabled for each of the bytes in the specified double-word, under control of the CBE bits of the OCR Register.
The VNP bit in the DCR controls whether virtual or physical
addresses are compared, The CRD and CWR bits in the
DCR separately enable the address compare condition for
read and write references; the CAE bit in the DCR can be
used to disable the compare-address condition independently from the other control bits. The CPU examines the
address compare condition for all data reads and writes,
reads of memory locations for effective address calculations, Interrupt-Acknowledge and End-of-Interrupt bus cycles, and memory references for exception processing.
The PC-match condition is detected when the address of
the instruction equals the value specified in the BPC register. The PC-match condition is enabled by the PCE bit in the
DCR.
Detection of address-compare and PC-match conditions is
enabled for User and Supervisor Modes by the UD and SO
bits in the OCR. The DEN-bit can be used to disable detection of these two conditions independently from the other
control bits,
Note: The size and organization of the on-chip caches may change In future
Series 32000 microprocessors. This however, will not affect software
compatibility.
3.4.1 Instruction Cache (IC)
The basic structure of the instruction cache (IC) is shown in
Figure 3-15.
The IC stores 512 bytes of code in a direct-mapped organization with 32 sets. Direct-mapped means that each set
contains only one block, thus each memory location can be
loaded into the IC in only one place.
Each block contains a 23-bit tag, which holds the most-significant bits of the physical address for the locations stored
in the block, along with 4 double-words and 4 validity bits
(one for each double-word).
A 4-double-word instruction buffer is also provided, which is
loaded either from a selected cache block or from external
memory. Instructions are read from this buffer by the loader
unit and transferred to an a-byte instruction queue.
An external condition is recognized whenever the DBG signal is activated.
When the CPU detects an address-compare or PC-match
condition while executing an instruction or processing an
exception, then Trap (DBG) occurs if the TR bit in the OCR
is 1, When an external debug condition is detected, Trap
(DBG) occurs regardless of the TR bit. The cause of the
Trap (DBG) is indicated in the DSR Register.
The IC mayor may not be enabled to cache an instruction
being fetched by the CPU. It is enabled when the IC bit in
the CFG Register is set to 1.
If the IC is disabled, the CPU bypasses it during the instruction fetch and its contents are not affected. The instruction
is read directly from external memory into the instruction
buffer.
When an address-compare or PC-match condition is detected while executing an instruction, the CPU asserts the BP
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FIGURE 3-15. Instruction Cache Structure
Note: If the IC is enabled for a certain instruction and a 'miss' occurs due to
a tag mismatch, the CPU will clear all the validity bits of the selected
tag before fetching the instruction from external memory. If the CIIN
input signal is activated during the fetching of that instruction, the
validity bits are not set and the IC is not updated.
When the IC is enabled, the instruction address bits 4 to 8
are used to select the IC set where the instruction may be
stored. The tag corresponding to the single block in the set
is compared with the 23 most-significant bits of the instruction's physical address. The 4 double-words in this block are
loaded into the instruction buffer and the 4 validity bits are
also retrieved. Bits 2 and 3 of the instruction's physical address select one of these double-words and the associated
validity bit.
3.4.2 Data Cache (DC)
The Data Cache (DC) stores 1,024 bytes of data in a twoway set associative organization as shown in Figure 3-16.
If the tag matches and the selected double-word is valid, a
cache 'hit' occurs and the double-word is directly transferred to the instruction queue for decoding; otherwise a
cache 'miss' will result.
Each of the 32 sets has 2 cache blocks. Each block contains a 23-bit tag, which holds the most-significant bits of
the address for the locations stored in the block, along with
4 double-words and 4 validity bits (one for each doubleword).
In the latter case, if the cache is not locked, the CPU will
take the following actions.
The DC is enabled for a data read when all of the following
conditions are satisfied.
• The DC bit in the CFG Register is set to 1.
First, if the tag of the selected block does not match, the tag
is loaded with the 23 most-significant bits of the instruction
address and all the validity bits are cleared. Then, the instruction is read from external memory into the instruction
buffer.
• The reference is not an interlocked read resulting from
executing a CBITI or SBITI instruction.
If the DC is disabled, the CPU bypasses it during the data
read and its contents are not affected. The data is read
directly from external memory. The DC is also bypassed for
Interrupt-Acknowledge and End-of-Interrupt bus cycles.
If the CIIN input signal is not active during the fetching of the
missing instruction, then the IC is updated and the instruction double-words fetched from memory are stored into it
with the validity bits set.
When the DC is enabled for a data read, the address bits 4
to 8 are used to select the DC set where the data may be
stored.
If the cache is locked, its contents are not affected, as the
CPU reads the missing instruction from external memory.
The tags corresponding to the two blocks in the set are
compared to the 23 most-significant bits of the address. Bits
2 and 3 of the address select one double-word in each
block and the associated validity bit.
Whenever the CPU accesses external memory, whether or
not the IC is enabled, it always fetches instruction doublewords in a non-wrap-around fashion. Refer to Sections
3.5.4.3 and 3.5.6 for more information.
If one of the tag matches and the selected double-word in
the corresponding block is valid, a cache 'hit' occurs and
the data is used to execute the instruction; otherwise a
cache 'miss' will result. In the latter case, if the cache is not
locked, the CPU will take the following actions.
The contents of the instruction cache can be invalidated by
software through the CINV instruction. Refer to Section
3.4.3 for details. Clearing the IC bit in the CFG Register also
invalidates the instruction cache. Refer to Section C.2 for
information on loading the CFG register.
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FIGURE 3-16. Data Cache Structure
First, if the tag of either block in the set matches the data
address, that block is selected for updating. Otherwise, if
neither tag matches, then the least recently used block is
selected; its tag is loaded with the 23 most-significant bits of
the data address, and all the validity bits are cleared.
3.4.3 Cache Coherence Support
The NS32GX32 provides means for maintaining coherence
between the on-chip caches and external memory. The
CINV instruction can be executed to invalidate the Instruction Cache and/or Data Cache; the CINV instruction can
also be executed to invalidate a single 16-byte block in either or both caches.
Then, the data is read from external memory; up to 4 double-word bits are read into the cache in a wrap-around fashion. Refer to Sections 3.5.4.3 and 3.5.6 for more information.
In hardware, the use of the caches can be inhibited for individual locations using the CIIN input signal.
If the CIIN and IODEC input signals are both inactive during
the bus cycles performed to read the missing data, then the
DC is updated, as each double-word is read from memory,
and the corresponding validity bit is set. If the cache is
locked, its contents are not affected, as the CPU reads the
missing data from external memory.
Whenever a CINV instruction is executed, the operation
code and operand appear on the system interface using
slave processor bus cycles. Thus, invalidations of the onchip caches by software can be monitored externally.
Note, however, that the software is responsible for communicating to the external circuitry the values of the cache enable and lock bits in the CFG Register, since the CPU does
not generate any special cycle (e.g., Slave Cycle) when the
CFG Register is loaded.
The DC is enabled for a data write whenever the DC bit in
the CFG Register is set to 1, including interlocked writes
resulting from executing the C81TI and S81T1 instructions.
The DC does not use write allocation. This means that, during a write, if a cache 'hit' occurs, the DC is updated, otherwise it is unaffected. The data is always written through to
external memory.
3.5 SYSTEM INTERFACE
This section provides general information on the NS32GX32
interface to the external world. Descriptions of the CPU requirements as well as the various bus characteristics are
provided here. Details on other device characteristics including timing are given in Chapter 4.
The contents of the data cache can be invalidated by software through the CINV instruction. Clearing the DC bit in the
CFG Register also invalidates the data cache. Refer to Section C.2 for information on loading the CFG register.
Note: If the DC Is enabled for a certain data reference and a "miss" occurs
due to tag mismatch. the CPU will clear all the validity bits for the least
recently used tag before reading the data from external memory. II
either CIIN or 'fODEC are activated during the data read bus cycles.
the validity bits are not set and the DC is not updated.
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3.5.1 Power and Grounding
3.5.2 Clocking
The NS32GX32 requires a single 5-volt power supply, applied on 21 pins. The logic voltage pins (VCCl1 to VCCl6)
supply the power to the on-chip logic. The buffer voltage
pins (VCCB1 to VCCB14) supply the power to the output
drivers of the chip. The bus clock power pin (VCCClK) is
the power supply for the on-chip clock drivers. All the voltage pins should be connected together by a power (VCC)
plane on the printed circuit board.
The NS32GX32 requires a single-phase input clock signal
(ClK) with frequency twice the CPU's operating frequency.
This clock signal is internally divided by two to generate two
non-overlapping phases PHI1 and PHI2. One single-phase
clock signal BClK in phase with PHI1 and its complement
BClK, are also generated and output by the CPU for timing
reference.
Following power-on, the phase relationship between BClK
and ClK is undefined. Nevertheless, in some systems it
may be necessary to synchronize the CPU bus timing to an
external reference. The SYNC input signal can be used to
initialize the phase relationship between ClK and BClK.
SYNC can also be used to stretch BClK (low) while ClK is
toggling.
The NS32GX32 grounding connections are made on 20
pins. The logic ground pins (GNDl1 to GNDl6) are the
ground pins for the on-chip logic. The buffer ground pins
(GNDB1 to GNDB13) are the ground pins for the output
drivers of the chip. The bus clock ground pin (GNDClK) is
the ground connection for the on-chip clock drivers. All the
ground pins should be connected together by a ground
plane on the printed circuit board.
SYNC is sampled on each rising edge of ClK. As shown in
Figure 3-18, whenever SYNC is sampled low, BClK stops
toggling and stays low. On the first rising edge that SYNC is
sampled high, BClK is driven high and then toggles on each
subsequent rising edge of ClK.
Both power and ground connections are shown in Figure
3-17.
+5V
Every rising edge of BClK defines a transition in the timing
state ("T-State") of the CPU.
VCCL1 - 6
One T-State represents the execution of one microinstruction within the CPU and/or one step of an external bus
transfer.
VCCB1 -14
OTHER VCC
VCCClK 1 - -..... CONNECTIONS
(Vee PLANE)
Note: The CPU requirement on the maximum period of BCLK must be satis·
fied when SYNC is asserted at times other than reset.
3.5.3 Resetting
NS32GX32
CPU
The RST input pin is used to reset the NS32GX32. The CPU
samples RST synchronously on the rising edge of BClK.
Whenever a low level is detected, the CPU responds immediately. Any instruction being executed is terminated; any
results that have not yet been written to memory are discarded; and any pending bus errors, interrupts, and traps
are eliminated. The internal latches for the edge-sensitive
NMI and DBG signals are cleared.
GNDL1 - 6
GNDBI-13
OTHER GROUND
GNDCLK
J - -....... CONNECTIONS
(GND PLANE)
TLlEE/10253-24
FIGURE 3·17. Power and Ground Connections
I
I
I
I
I
I
I
I
I
I
elK [
:::~mtml \I\j m
FIGURE 3·18. Bus Clock Synchronization
2-42
TLlEE/10253-25
z
3.0 Functional Description
en
w
(Continued)
The CPU stores the PC contents in the RO Register and the
PSR contents in the least-significant word of R1, leaving the
most-significant word undefined. The PC is then cleared to 0
and so are all the implemented bits in the PSR, MSR, MCR
and CFG registers. The DEN-bit in the OCR Register is also
cleared to O. After reset, the remaining implemented bits in
OCR and the contents of all other registers are undefined.
The CPU begins executing the instruction at Address O.
3.5.4.1 Bus Status
o
......
The Bus Status pins are interpreted as a five-bit value, with
STO the least significant bit. Their values decode as follows:
en
w
00000 The bus is idle because the CPU does not yet need
to access the bu s.
00001
While in the Reset state, the CPU drives the signals ADS,
BEO-3, BMT, CC5f\JF and HLDA inactive. The data bus is
floated and the state of all other output signals is undefined.
00010 The bus is idle because the CPU has halted after
detecting a bus error while processing an exception.
m
Note 2: II S'Y'ffi': Is asserted while the CPU Is being reset, then BClK does
not toggle. Consequently, S'Y'ffi': must be high lor at least 126 ClK
cycles while ~ Is low.
00011
The bus is idle because the CPU is waiting for a
Slave Processor to complete executing an instruction.
00100
Interrupt Acknowledge. Master.
00101
I.- ~ CYCLES
64 CLo;aCK_
00110 End of Interrupt, Master.
The CPU is performing a read cycle to indicate that
it is executing a Return from Interrupt (RETI) instruction at the completion of an interrupt's service
procedure.
RST [
f-+----
~
50)J.s
TL/EE/10253-26
00111
FIGURE 3-19. Power-On Reset Requirements
[
C
---~~r-\
\\\~
Interrupt Acknowledge, Cascaded.
The CPU is reading an interrupt vector to acknowledge a maskable interrupt request from a Cascaded Interrupt Control Unit.
JLSL
BCLK[._-+--,
RST
The bus is idle because the CPU is waiting for an
interrupt following execution of the WAIT instruction.
The CPU is reading an interrupt vector to acknowledge an interrupt request.
Vcc[j
End of Interrupt, Cascaded.
The CPU is performing a read cycle from a Cascaded Interrupt Control Unit to indicate that it is executing a Return from Interrupt (RETI) instruction at the
completion of an interrupt's service procedure.
~ 64:=r-CLOCK
.
01000 Sequential Instruction Fetch.
CYCLES
~
The CPU is fetching the next double-word in sequence from the instruction stream.
TL/EE/10253-27
01001
FIGURE 3-20. General Reset Timing
Non-Sequential Instruction Fetch.
The CPU is fetching the first double-word of a new
sequence of instruction. This will occur as a result
of any JUMP or BRANCH, any exception, or after
the execution of certain instructions.
3.5.4 Bus Cycles
The NS32GX32 CPU will perform bus cycles for one of the
following reasons:
01010 Data Transfer.
1. To fetch instructions from memory.
The CPU is reading or writing an operand for an
instruction, or it is referring to memory while processing an exception.
2. To write or read data to or from memory or peripheral
devices. Peripheral input and output are memory mapped
in the Series 32000 family.
3. To acknowledge an interrupt and allow external circuitry
to provide a vector number, or to acknowledge completion of an interrupt service routine.
01011
4. To transfer information to or from a Slave Processor.
01100
Read RMW Class Operand.
The CPU is reading an operand with access class
of read-modify-write.
In terms of bus timing, cases 1 through 4 above are identical. For timing specifications, see Section 4. The only external difference between them is the 5-bit code placed on the
Bus Status pins (STO-ST4). Slave Processor cycles differ in
that separate control signals are applied (Section 3.5.4.7).
Read for Effective Address Calculation.
The CPU is reading a pointer from memory in order
to calculate an effective address for Memory Relative or External addressing modes.
2-43
><
The CPU presents five bits of Bus Status information on
pins STO-ST4. The various combinations on these pins indicate why the CPU is performing a bus cycle. or, if it is idle
on the bus, then why is it idle.
On application of power, RST must be held low for at least
50 tJ.s after Vee is stable. This is to ensure that all on-chip
voltages are completely stable before operation. Whenever
a Reset is applied, it must also remain active for not less
than 64 BCLK cycles. See Figures 3-19 and 3-20.
Note 1: II fmIIj Is active at the time
Is de asserted, the CPU acknowledges ~ belore performing any bus cycle.
N
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3.0 Functional Description
><
11101
C")
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11110
Lt)
I
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N
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en
z
o
""
N
11111
Tl
T2
I T1 OR
nI
BCLK [
Read Slave Processor Status.
The CPU is reading a status word from a slave
processor after the slave processor has activated
the FSSR signal.
N
><
ANY
I T- STATE I
The CPU is transferring an operand to or from a
Slave Processor.
N
en
(Continued)
Transfer Slave Processor Operand.
Broadcast Slave Processor ID
+
-~ X
~
AO-31 [
~
OPCODE.
DO-3{
The CPU is initiating the execution of a Slave Instruction by transferring the first 3 bytes of the instruction, which specify the Slave Processor identification and operation.
ZV/~ fj~ ~-
-- -- -G)-
~
ODIN [
1--
~-.
/
I
N
3.5.4.2 Basic Read and Write Cycles
><
The sequence of events occurring during a basic CPU access to either memory or peripheral device is shown in Figure 3-21 for a read cycle, and Figure 3-22 for a write cycle.
ADS [
The cases shown assume that the selected memory or peripheral device is capable of communicating with the CPU at
full speed. If not, then cycle extension may be requested
through the RDY line. See Section 3.5.4.4.
BMT [
C")
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en
z
'0
I~
- V i0
/
CONf [
A full speed bus cycle is performed in two cycles of the
BCLK clock, labeled T1 and T2. For both read and write bus
cycles the CPU asserts ADS during the first half of T1 indicating the beginning of the bus cycle. From the beginning of
T1 until the completion of the bus cycle the CPU drives the
Address Bus and other relevant control signals as indicated
in the timing diagrams. For cacheable data read cycles the
CPU also drives the CASEC signal to indicate the block in
the DC set where the data will be stored. If the bus cycle is
not cancelled (e.g., state T2 is entered in the next clock
cycle), the confirm signal (CONF) is asserted in the middle
of T1. Note that due to a bus cycle cancellation, the BMT
signal may be asserted at the beginning of T1, and then
deasserted before the time in which it is guaranteed valid
(see Section 4.4.2).
\. ~
\.. / \.. /
/
ROY [
~ V;~ V;~ Ifh IIfh IIfh ~
/J /11 /1/
BRT [
~ V/~ V/~ Ifh rih If,!h 'I
Ifh Ifh
BER [
h rih 'Iii'Iii Vii ,/1/
"
~ Vh Vh
/
BOUT [
em[iJ '1h '1h VII ,/11,/11Vh VII 'III 'III
A confirmed bus cycle is completed at the end of T2, unless
a cycle extension is requested. Following state T2 is either
state T1 of the next bus cycle, or an idle T-state, if the CPU
has no bus cycle to perform.
BWO-l, [
CIIN,IODEC
In case of a read cycle the CPU samples the data bus at the
end of state T2.
BEO-3, STO- 4, [
UjS, IOINH
If a bus exception is detected, the data is ignored.
For write bus cycles, valid data is output from the middle of
T1 until the end of the cycle. When a write bus cycle is
immediately followed by another write cycle, the CPU keeps
driving the bus with the data related to the previous cycle
until the middle of state T1 of the second bus cycle.
CASEC [
'l. III VI} VII II} ~
-~ X
~
~-
-
~
I---
x:-- ~
ex
'1~ Ilh 'I/,
X - DC
~
~ KI - I--
TL/EE/l0253-28
FIGURE 3·21. Basic Read Cycle
The CPU always inserts an idle state before a write cycle
when the write immediately follows a confirmed read cycle.
Note: The CPU can initiate a bus cycle with a Tl·state and then cancel the
cycle, such as when a Cache hit occurs. In such a case, the CONF
signal remains High and the BMT signal is driven High; the Tl-state is
followed by another T1-state or an idle T-state.
2-44
3.0 Functional Description
ANY
IT-STATE I
Tl
T2
z
en
w
(Continued)
I T1 OR
I\)
The sequence of events for burst cycles is shown in Figure
3-23. The case shown assumes that the selected memory is
capable of communicating with the CPU at full speed. If not,
then cycle extension can be requested through the ROY
line. See Section 3.5.4.4.
nI
BCLK [
A Burst cycle is composed of two parts. The first part is a
regular cycle (opening cycle), in which the CPU outputs the
new status and asserts all the other relevant control signals.
In addition, the Burst Out Signal (BOUT) is activated by the
CPU indicating that the CPU can perform Burst cycles. If the
selected memory allows Burst cycles, it will notify the CPU
by activating the burst in signal (BIN). BIN is sampled by the
CPU in the middle of T2 on the falling edge of BCLK. If the
memory does not allow burst (BIN high), the cycle will terminate at the end of T2 and BOUT will go inactive immediately. If the memory allows burst (BIN low), and the CPU has
not deasserted BOUT, the second part of the Burst cycle
will be performed and BOUT will remain active until termination of the Burst.
AO-3{
DO-3{
Z Ifh 'Ih ~ K
DATA OUT ~
'\
/
ODIN [
\. / \..V
ADS [
I~I - - /
'0
Bt,tT [
\. .I
~
/
CONr[
1/
---V
'l.Vlh II/, II/, If//, 'I/, Ih /J /11 /1/
BRT [
'l.Vfh '1h 'Ih lIfil (Iii 'I
~ Ifh 'I;j
BER [
h Vii Vii 'Iii '/il VI/
'VVII ,/11
BOUT [
/
BEO-3, [
STO- 4, U/S
'/VI; VII Vlj Vlj ~
.-tx:
~
~
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I\)
I
I\)
U1
.......
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I\)
G>
><
w
I\)
W
o
As shown in Figures 3-23 and 4-8 (in Section 4), the CPU
samples ROY at the end of each nibble. It extends the access time for the burst transfer if ROY is inactive.
The CPU initiates burst read cycles in the following cases.
1. An instruction must be fetched (Status = 01000 or
01001), and the instruction address does not fall within
the last double-word in an aligned 16-byte block (e.g.,
address bits 2 and 3 are not both equal to 1).
2. A data item must be read (Status = 01010, 01011 or
01100), and both of the following conditions are met.
• The data cache is enabled and not locked. (OC = 1
and LOC = 0 in the CFG register.)
BiN [ iJ VII Vii '/il ,/1,VII ,/1, ,/11VII VII
BWO-{
I
I\)
o
.......
The second part consists of up to 3 nibbles, labeled T2B. In
each of them a data item is read by the CPU. For each
nibble in the burst sequence the CPU forces the 2 least-significant bits of the address to 0 and increments address bits
2 and 3 to select the next double-word; all the byte enable
signals (BEO-3) are activated.
\.. -
ROY [
G>
><
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I\)
• The bus cycle is not an interlocked data access performed while executing a CBITI or SBITI instruction.
ex Vh I//hIfll,
The Burst sequence will be terminated when one of the
following events occurs.
tx
1. The last instruction double-word in an aligned 16-byte
block has been fetched.
2. The CPU detects that the instructions being prefetched
are no longer needed due to an alteration of the flow of
control. This happens, for example, when a Branch instruction is executed or an exception occurs.
TL/EE/l0253-29
FIGURE 3-22. Write Cycle
3.5.4.3 Burst Cycles
3. 4 double-words of data have been read by the CPU. The
double-words are transferred within an aligned 16-byte
block in a wrap-around order. For example, if a source
operand is located at address 104, then the burst read
cycle transfers the double-words at 104, 108, 112, and
100, in that order.
The NS32GX32 is capable of performing burst cycles in order to increase the bus transfer rate. Burst is only available
in instruction fetch cycles and data read cycle from 32-bit
wide memories. Burst is not supported in operand write cycles or slave cycles.
2-45
PI
3.0 Functional Description
(Continued)
ANY
I T- STATE I
Tl
I
T2
I
T28
I
T28
I
T28
I T1 OR
nI
8CLK [
x-- DC
AO-3{
ODIN [
~
DC -- D<
VII VI/,~
~t)- -(!~Kit)- -(!NJ
\.
/
\. V
I\.V
I~ 10- V
I~ ~ V
"
00-31 [
~
ADS [
~~
8t.4T [
I\:
I
CONF [
I--
~ Vfh Vh Vh Vh VII VA
ROY [
Jj ~ Jj t:\ Jj ~ /)V/,I Vh
8EO- 3 [
I\,
BiN [
Vh VII Vh V,lj VA Jj PA
80UT [
"
I
/1 k'A fl VfL VII. Vfh t'lh tiL
l/
8RT [
'j 'II. 'III 'III Vh VII VI ~ {/ ~
8ER [
'l. /Ih '1h ,/11 'II) VII VI ~ {f ~V
V
~ (f '<
•
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N
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.......
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·
U1
.......
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><
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Q
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CJ
3.0 Functional Description
(Continued)
ANY
IT-STATE I
C\I
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.......
.
T1
I
T2
I T2(W) ITI ORTII
BCLK [
Il)
C\I
C\I
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CJ
-
.- DC ~
I--
AO-3{
C")
en
z
.......
lX.
I--
C\I
DO-3{
'I. 'II. "/1. ?--
--. -- -- -- ~
I--
. _.
Q
~
C\I
~
ODIN [
C")
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CJ
C\I
C")
en
ADS [
z
Bt.lT [
/
\.V I\. t/
I\.V
I~
I~ I - -V
~I - -
1/
II
CONF [
V
\. -
RDY [
'I. If/I 1/1. 'II. '1/1. If/h '1/
~ t}..
/J Vh '///
BRT [
Z "fh ~ rLh "Ih ~hVii Vh r/
'<
•
W
N
N
Q
'"
Z
(J)
W
N
G')
><
W
N
N•
U1
X
X
X
X
X
X
X
X
Vector:
Range: 0-127
X
X
Vector: Same as
in Previous Int.
Ack. Cycle
X
X
Cascade Index:
range -16 to -1
'"
Z
(J)
W
N
G')
><
W
N
•
W
Q
D. Vectored Interrupt Sequences: Cascaded
Interrupt Acknowledge
1
00100 FFFFFE0016
o
o
(The CPU here uses the Cascade Index to find the Cascade Address)
2
001101
Cascade
0
See Note
Address
Interrupt Return
o
1
00110 FFFFFE0016
(The CPU here uses the Cascade Index to find the Cascade Address)
2
00111
Cascade
0
See Note
Address
X = Don't Care
Not.: SEO-'E3E3 signals will be activated according to the cascaded leu address
X
Vector, range 16-255; on appropriate byte of
data bus.
o
X
X
X
X
X
X
Cascade Index:
Same as in
previous Int.
Ack. Cycle
X
fI
2·49
o
r-----------------------------------------------------------------------------~
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"en
3.0 Functional Description
ANY
IT- STATE I
N
T1
T2
(Continued)
ANY
IT - STATE I
I T1 or Ti I
T1
T2
I T1 or Ti I
C")
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BCLK [
BCLK [
......
II)
N
N
•
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00-31 [
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SPC [
o
ODIN [
N
C")
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><
N
N
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"/
~
I
DATA OUT
00-3{
-"
I
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I
8
SPC [
\.
ODIN [
\.
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STO-4 [
STO-4[
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TL/EE/10253-33
TLlEE/10253-32
FIGURE 3-25. Slave Processor Write Cycle
FIGURE 3-26. Slave Processor Read Cycle
3.5.5 Bus Exceptions
The NS32GX32 has the capability of handling errors occurring during the execution of a bus cycle. These errors can
be either correctable or incorrectable, and the CPU can be
notified of their occurrence through the input signals SRT
and/or SER.
When BER is sampled active, the CPU completes the bus
cycle normally. If a bus error occurs during a bus cycle for a
reference required to execute an instruction, then a bus error exception is recognized. However, if an error occurs during an acknowledge cycle of another exception or during
the ICU read cycle of a RETI instruction, the CPU interprets
the event as a fatal bus error and enters the 'halted' state.
Bus Retry
If a bus error can be corrected, the CPU may be requested
to repeat the erroneous bus cycle. The request is done by
asserting the SRT signal. SRT is sampled at the end of
state T2 or T2S.
In this state the CPU floats its address and data buses and
places a special status code on the STO-4 lines. The CPU
can exit this condition only through a hardware reset. Refer
to Section 3.2.6 for more details on bus error.
Note 1: If the erroneous bus cycle is extended by means of wait states, then
the CPU uses the values of BRT and/or BER sampled during the
last wait state.
When the CPU detects that SRT is active, it completes the
bus cycle normally, but ignores the data read in case of a
read cycle, and maintains a copy of the data to be written in
case of a write cycle. Then, after a delay of two clock cycles, it will start executing the bus cycle again.
Note 2: If the CPU samples both BRT and BER active, BRT has higher
priority. The bus error indication is ignored, and the bus cycle is
repeated.
Note 3: If BER is asserted during a bus cycle of a multi-cycle data transfer,
the CpU completes the entire transfer normally, but the data will be
Ignored. The CPU also ignores any subsequent assertion of BER
during the same data transfer.
If the transfer cycle is multiple (e.g., for non-aligned data),
only the problematic part will be repeated.
For instance, if a non-aligned double-word is being transferred and the second half of the transfer fails, only the
second part will be repeated.
Note 4: Neither BRT nor BEi"l should be asserted during the T2 state of a
slave processor bus cycle.
3.5.6 Dynamic Bus Configuration
The same applies for a retry during a burst sequence. The
repeated cycle will begin where the read operation failed
(rather than the first address of the burst) and will finish the
original burst.
Figures 3-27 and 4-10 (in Section 4) show the SRT timing
for a basic access cycle and for burst cycles respectively.
The NS32GX32 is tuned to operate with 32-bit wide memory
and peripheral devices. The bus also supports a-bit and
16-bit data widths, but at reduced efficiency. The CPU can
switch from one bus width to another dynamically; the only
restriction is that the bus width cannot change for locations
within an aligned 16-byte block.
The CPU always waits for SRT to be HIGH before repeating
the bus cycle. While SRT is lOW, the CPU places all the
output signals shown in Figure 4-11 in a TRI-STATE@ condition.
The CPU determines the bus width in effect for a bus cycle
by using the values of the SWO and SW1 signals sampled
during the last T2 state. Values of SWO and SW1 sampled
before the last T2 state or during T2S states are ignored.
Whenever a bus width other than 32-bit is detected by the
CPU, two idle states are inserted before the next bus cycle
is initiated. These idle states are only inserted once during
an operand access, even if more than two bus cycles are
needed to complete the access.
Bus Error
If a bus error is incorrectable the CPU may be requested to
interrupt the current process and branch to an appropriate
procedure to handle the error. The request is performed by
activating the SER signal. SER is sampled by the CPU at
the end of state T2 or T2S on the rising edge of SClK.
2-50
z
3.0 Functional Description
en
w
(Continued)
N
Q
><
W
N
N•
ANY
IT-STATE I
Tl
I
T2
1T1 ORTI I
TI
I
T1
I
T2
I T1 orTI I
o
.......
BCLK [
Z
AO-3{ ~ - X
X DC ~ .-{
DO-3{ZIf//' (Ih ?-- -- 10-- ~ ,- -- -. -- -_.
~
I--
X
~
/
N
Q
><
--I<
w
\.V
~
o
Bt.1T [
CONF [
r0
I~ ;.-.V
I~V
I~
~
V
I~I--V
1/I\-
/
~
RDY [
'l. 1/11 Ifll 1/11 Ifll."II ~ /J VI) [/f.L Vb V/i rtIJVh V\. L) VI/ VI
BRT [
VI.
'lVI} VII VII VI/' VI/' ~ /. (/1. V/I VI/ VI) VI, Vii '(/ ~ If//'.-
BER [
Z 'II. rll. rlh '(III rll."
BOUT [
~
/
Vl
rlhVh VIJ Vh VIJ VIJ V ~ If//'
1060I-I
"
joIoo6
BiN [ h 'ih 'ihVIJ VIJ 'lIJ '/IJ VI) VI/ Vfl Vfl 'IfL ILL VfL VLL III /1/ V/
BWO-l, [
CIIN,IODEC
BEO- 3, ?TO- 4, [
U/S,IOINH
CASEC [
'I.'II 'Il VI/' III
-- X-- tx
X:xrill "IhIflh'II 'II /1) ~ex '/h 'ihrh
~
X,.,.
~
IX
DC- X
~
~K~ "I/, 'I/, ~
-~K
r-~
~
TL/EE/10253-34
FIGURE 3·27. Bus Retry During a Basic Read Cycle
2-51
.
oC")
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3.0 Functional Description (Continued)
The various combinations for BWO and BW1 are shown below.
The following subsections provide detailed descriptions of
the access sequences performed in the various cases.
C")
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N
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BW1
BWO
0
0
1
1
0
1
0
1
Note: Although the NS32GX32 ignores the BIN signal for S-bit and 16-bit
bus widths, it is recommended that BIN be asserted only if the system
supports burst transfers. This is to ensure compatibility with future
versions of the CPU that might support burst transfers for S-bit and
16-bit buses.
Reserved
a-Bit Bus
16-Bit Bus
32-Bit Bus
AO--------------------~
BE3-----,
BE1--------~
N
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.......
.
o
N
N
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N
C")
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CACH------~~--.....,
The bus width is always 32 bits during slave cycles (See
Section 3_5.4.7). An important feature of the NS32GX32 is
that it does not impose any restrictions on the data alignment, regardless of the bus width .
Bus accesses are performed in double-word units. Accesses of data operands that cross double-word boundaries are
decomposed into two or more aligned double-word accesses.
The CPU provides four byte enable signals (BEO-3) which
facilitate individual byte accessing on either a 32-bit or a
16-bit bus.
8 BITS
8 BITS
AI-31
Figures 3-28 and 3-29 show the basic interfaces for 32-bit
and 16-bit memories. An a-bit memory interface (not shown)
is even simpler since it does not use any of the BEO-3
signals and its single bank is always enabled whenever the
memory is selected. Each byte location in this case is selected by address bits AO-31.
The NS32GX32 does not keep track of the bus width used
in previous instruction fetches or data accesses. At the beginning of every memory transaction, the CPU always assumes that the bus is 32-bit wide and the BEO-3 signals are
activated accordingly.
DO -15
TL/EE/l0253-36
FIGURE 3-29. Basic Interface for 16-Blt Memories
The BOUT signal is also asserted during instruction fetches
or data reads if the conditions for bursting are satisfied. If
the bus is other than 32-bit wide, the BIN signal is ignored
and BOUT is deasserted at the beginning of the T state
following T2, since burst cycles are not allowed for a-bit or
16-bit buses.
3.5.6.1 Instruction Fetch Sequences
The CPU performs two types of instruction fetch cycles: sequential and non-sequential. These can be distinguished
from each other by the differing status combinations on pins
STO-4. For non-sequential instruction fetches the CPU
presents on the address bus the exact byte address of the
first instruction in the instruction stream that is about to begin; for sequential instruction fetches, the address of the
next aligned instruction double-word is presented on the address bus. The CPU always activates all byte enable signals
(BEO-3) for both sequential and non-sequential fetches.
BOUT is also asserted during T2 if the addressed doubleword is not the last in an aligned 16-byte block. Tables 3-5
to 3-7 show the fetch sequence for the various bus widths.
CACH------.-~--._+_--~~--~
(NOTE)
8 BITS
\.---------1
BBITS
32-Blt Bus Width
The CPU reads the entire double-word present on the data
bus into its internal instruction buffer.
A2-31
If BOUT and BIN are both active, the CPU reads up to 3
consecutive double-words using burst cycles. Burst cycles
are used for instruction fetches regardless of whether the
accesses are cacheable.
00-31~
________________________
~
TL/EE/l0253-35
FIGURE 3-28. Basic Interface for 32-Blt Memories
Note: The CACR signal must be asserted during cacheable read accesses.
2-52
z
3.0 Functional Description
en
w
(Continued)
N
Example: JUMP @5
Example JUMP @6
• A fetch cycle is performed at address 6 with 8EO-3 all
active.
• The word at address 4 is then fetched if the access is
cacheable.
8-Blt Bus Width
The instruction byte on the bus lines 00-7 is fetched. The
CPU performs three consecutive cycles to read the remaining bytes within the required double-word, while keeping
8EO-3 all active. The 4 bytes are then assembled into a
double-word and transferred into the instruction buffer. For
a non-sequential fetch, if the access is not cacheable, the
CPU will only read the upper bytes within the instruction
double-word starting with the byte at the instruction address.
Example: JUMP @7
• The CPU performs a fetch cycle at address 5 with 8EO-3
all active.
• Two burst cycles are then performed and addresses 8 and
12 are output while 8EO-3 are kept active.
16-Blt Bus Width
The word on the least-significant half of the data bus is read
by the CPU. This is either the even or the odd word within
the required instruction double-word, as determined by address bit 1.
The CPU then complements address bit 1, clears address
bit 0 and initiates a bus cycle to read the other word, while
keeping all the 8EO-3 signals active.
These two words are then assembled into a double-word
and transferred into the instruction buffer.
In case of a non-sequential fetch, if the access is not cacheable and the instruction address selects the odd word within
the instruction double-word, the even word is not fetched.
1.
2.
• The CPU performs a fetch cycle at address 7 with 8EO-3
all active.
• 8ytes at addresses 4, 5 and 6 are then fetched consecutively if the access is cacheable.
TABLE 3-5. CacheablelNon-Cacheable Instruction Fetches from a 32-Bit Bus
In a burst access four bytes are fetched with the L.S. bits of the address set to 00.
A 'C' on the data bus refers to cacheable fetches and indicates that the byte is placed in the instruction cache. An 'I' refers
to non-cacheable fetches and indicates that the byte is ignored.
Number
of Bytes
Address
LSB
Address
Bus
Bytes to be Fetched
1
11
80
-
10
81
80
-
-
A
2
3
01
82
81
80
-
A
4
00
83
82
81
80
A
A
Data Bus
BEO-3
LLLL
LLLL
LLLL
LLLL
80
C/I
CII
C/I
81
80
C/I
C/I
82
81
80
C/I
83
82
81
80
TABLE 3-6. CacheablelNon-Cacheable Instruction Fetches from a 16-Blt Bus
1. A bus access marked with '.' in the 'Address 8us' column is performed only if the fetch is cacheable.
Address
Bus
Number
of Bytes
Address
LSB
1
11
80
-
-
-
A
*A - 3
2
10
81
80
-
-
A
*A - 2
Bytes to be Fetched
3
01
82
81
80
-
A
A+1
4
00
83
82
81
80
A
A+2
2-53
BEO-3
LLLL
LLLL
LLLL
LLLL
LLLL
LLLL
LLLL
LLLL
Data Bus
-
-
-
-
80
C
C/I
C
81
C
80
C
80
82
C/I
81
-
81
83
80
82
-
Q
><
W
N
I
N
o
.......
Z
en
w
N
Q
><
W
N
I
N
UI
.......
Z
en
w
N
Q
><
W
N
I
W
o
oC")
N
C")
3.0 Functional Description
><
C!J
N
C")
U)
Z
......
an
(Continued)
TABLE 3-7_ Cacheable/Non·Cacheable Instruction Fetches from an 8-Blt Bus
Number
of Bytes
Address
LSB
11
~
Address
Bus
Bytes to be Fetched
A
BO
*A - 3
*A - 2
*A - 1
N
C")
><
C!J
N
C")
U)
2
10
B1
BO
A
A+1
*A - 2
*A - 1
Z
......
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><
C!J
3
01
B2
B1
BO
A
A+1
A+2
*A - 1
N
C")
U)
Z
4
00
B3
B2
B1
BO
3.5.6.2 Data Read Sequences
A
A+1
A+2
A+3
BEO-3
LLLL
LLLL
LLLL
LLLL
LLLL
LLLL
LLLL
LLLL
LLLL
LLLL
LLLL
LLLL
LLLL
LLLL
LLLL
LLLL
Data Bus
-
-
-
-
-
-
-
BO
C
C
C
BO
B1
C
C
BO
B1
B2
C
BO
B1
B2
B3
16-Blt Bus Width
The word on the least-significan't half of the data bus is read
by the CPU. The CPU can then perform another access
cycle with address bit 1 complemented and address bit 0
cleared to read the other word within the addressed doubleword.
If the access is cacheable, the entire double-word is read
and stored into the cache.
If the access is not cacheable, the CPU Ignores the bytes in
the double-word not selected by BEO-S. In this case, the
second access cycle is not performed, unless selected
bytes are contained in the second word.
Example: MOVB @5, RO
The CPU starts a data read access by placing the exact
address of the operand on the address bus. The byte enable lines are activated to select only the bytes required by
the instruction being executed. This prevents spurious accesses to peripheral devices that might be sensitive to read
accesses, such as those which exhibit the characteristic of
destructive reading. If the on-chip data cache is internally
enabled for the read access, the BOUT signal is asserted at
the beginning of state T2. BOOT will be deasserted if the
data cache is externally inhibited (through CIIN or IODEC),
or the bus width is other than 32 bits. During cacheable
accesses the CPU always reads all the bytes in the doubleword, whether or not they are needed to execute the instruction, and stores them into the data cache. The external
memory, in this case, must place the data on the bus regardless of the state of the byte enable signals.
If the data cache is either internally or externally inhibited
during the access, the CPU ignores the bytes not selected
by the BEO-3 signals. Data read sequences for the various
bus widths are shown in tables 3-8 to 3-10.
32-Blt Bus Width
The entire double-word present on the bus is read by the
CPU. If the access is cacheable and the memory allows
burst accesses, the CPU reads up to 3 additional doublewords within the aligned 16-byte block containing the first
byte of the operand. These burst accesses are performed in
a wrap-around fashion within the 16-byte block.
Example: MOVW @5, RO
• The CPU reads a word at address 5 while keeping BE1
active.
• If the access is not cacheable, the CPU ignores byte O.
• If the access is cacheable, the CPU performs another access cycle, with BEO-3 all active, to read the word at
address 6.
8-Blt Bus Width
The data byte on the bus lines 00-7 is read by the CPU.
The CPU can then perform up to 3 access cycles to read
the remaining bytes in the double-word.
If the access is cacheable, the entire double-word is read
and stored into the cache.
If the access is not cacheable, the CPU will only perform
those access cycles needed to read the selected bytes.
Example: MOVW @5, RO
• The CPU reads a double-word at address 5 while keeping
BE1 and BE2 active.
• The CPU reads the byte at address 5 while keeping BE1
and BE2 active.
• If the access is not-cacheable, BOUT is deasserted and
the data bytes 0 and 3 are ignored.
• If the access is not cacheable, the CPU activates BE2 and
reads the byte at address 6.
• If the access is cacheable, the CPU performs three bus
cycles with BEO-3 all active, to read the bytes at addresses 6,7 and 4.
• If the access is cacheable, the CPU performs burst cycles
with BEO-3 all active, to read the double-words at addresses 8, 12, and O.
2-54
z
en
w
3.0 Functional Description (Continued)
N
C)
TABLE 3-8. Cacheable/Non-Cacheable Data Reads from a 32-Blt Bus
In a burst access four bytes are read with the L.S. bits of the address set to 00.
A 'C' on the data bus refers to cacheable reads and indicates that the byte is placed in the data cache. An 'I' refers to noncacheable reads and indicates that the byte is ignored.
1.
2.
Number
of Bytes
Address
LSB
1
00
-
1
01
BO
Bytes to be Read
-
Address
Bus
BEO-3
Data Bus
HHHL
C/I
C/I
C/I
BO
BO
-
A
HHLH
C/I
C/I
80
C/I
A
HLHH
C/I
80
C/I
C/I
.......
-
A
LHHH
BO
C/I
C/I
C/I
en
N
C)
11
BO
-
2
00
-
B1
BO
A
HH LL
C/I
C/I
B1
BO
2
01
-
B1
BO
A
HLLH
C/I
81
80
C/I
2
10
B1
BO
-
-
A
LLHH
B1
BO
C/I
C/I
3
00
-
82
81
BO
A
HLLL
C/I
B2
81
BO
3
01
82
B1
BO
-
A
LLLH
B2
B1
BO
C/I
4
00
B3
B2
B1
BO
A
LLLL
B3
B2
B1
BO
01
Address
Bus
Data to be Read
-
-
-
BO
-
BO
-
BEO-3
Cach.
NonCach.
A
*A + 2
HHHL
LLLL
HHHL
A
HHLH
LLLL
HHLH
•A+ 1
10
-
BO
-
-
A
*A - 2
HLHH
LLLL
HLHH
1
11
BO
-
-
-
A
•A- 3
LHHH
LLLL
LHHH
-
-
B1
80
A
*A + 2
HH LL
LLLL
HH LL
-
B1
BO
-
A
A+1
HLLH
LLLL
HLLH
HLHH
A
*A - 2
LLHH
LLLL
LLHH
2
00
01
10
81
BO
-
-
3
00
-
B2
B1
BO
A
A+2
H LLL
LLLL
HLLL
HLHH
3
01
B2
B1
BO
-
A
A+1
LLLH
LLLL
LLLH
LLHH
BO
A
A+2
LLLL
LLLL
LLLL
LLHH
00
83
B2
B1
2-55
-
-
-
-
-
-
-
-
2
4
Data Bus
-
1
2
W
N
N
U1
TABLE 3-9. Cacheable/Non-Cacheable Data Reads from a 16-Blt Bus
1. A bus access marked with '.' in the 'Address Bus' column is performed only if the read is cacheable.
1
.
A
1
-
><
BO
-
00
Z
-
10
1
Q
.......
N
C)
1
Address
LSB
N
N
en
w
-
Number
of Bytes
><
•
W
-
-
-
-
-
CII
C
BO
C
BO
C
C/I
C
C/I
C
BO
C
BO
C
C/I
C
B1
C
BO
C
BO
C/I
C/I
81
B1
C
BO
C
B1
C/I
BO
82
BO
B2
C/I
81
B1
B3
80
B2
Z
w
><
w
~
W
Q
o
~
C")
3.0 Functional Description
><
(Continued)
TABLE 3-10. CacheableINon-Cacheable Data Reads from an 8-Blt Bus 08-12
CI
N
C")
en
z
......
.
an
N
N
Number
_ of Bytes
Address
LSB
Address
Bus
Data to be Read
1
00
-
-
-
BO
A
"A + 1
"A + 2
"A + 3
1
01
-
-
BO
-
A
"A + 1
"A + 2
"A - 1
-
BO
-
-
A
"A + 1
"A - 2
"A - 1
C")
><
CI
N
C")
en
z
......
o
N
N
C")
><
CI
1
10
N
C")
en
z
1
11
BO
-
-
-
2
00
-
-
B1
BO
2
01
-
B1
BO
-
2
3
10
00
B1
-
BO
B2
-
B1
BO
3
01
B2
B1
BO
-
4
00
B3
B2
B1
BO
A
"A - 3
"A - 2
"A - 1
A
A+1
"A + 2
"A + 3
A
A+1
"A + 2
"A - 1
A
A+1
"A - 2
"A - 1
A
A+1
A+2
"A +' 3
A
A+1
A+2
"A - 1
A
A+1
A+2
A+3
BEO-3
Cacho
NonCach.
HHHL
LLLL
LLLL
LLLL
HHLH
LLLL
LLLL
LLLL
HLHH
LLLL
LLLL
LLLL
LHHH
LLLL
LLLL
LLLL
HHLL
LLLL
LLLL
LLLL
HLLH
LLLL
LLLL
LLLL
LLHH
LLLL
LLLL
LLLL
HLLL
LLLL
LLLL
LLLL
LLLH
LLLL
LLLL
LLLL
LLLL
LLLL
LLLL
LLLL
HHHL
Data Bus
-
HHLH
-
HLHH
-
-
-
-
LHHH
-
-
HHLL
HHLH
-
-
HLLH
HLHH
LLHH
LHHH
-
-
HLLL
HLLH
HLHH
LLLH
LLHH
LHHH
LLLL
LLLH
LLHH
LHHH
-
-
-
-
-
-
-
-
-
BO
C
C
C
-
BO
C
C
C
-
-
-
-
-
-
BO
C
C
C
BO
C
C
C
BO
B1
C
C
BO
B1
C
C
BO
B1
C
C
BO
B1
B2
C
BO
B1
B2
C
BO
B1
B2
B3
3.5.6.3 Data Write Sequences
32-Blt Bus Width
In a write access the CPU outputs the operand address and
asserts only the byte enable lines needed to select the specific bytes to be written.
The CPU performs only one access cycle to write the selected bytes within the addressed double-word.
Example: MOVB RO, @6
In addition, the CPU duplicates the data to be written on the
appropriate bytes of the data bus in order to handle a-bit
and 16-bit buses.
• The CPU duplicates byte 2 of the data bus into byte 0 and
performs a write cycle at address 6 with BE2 active.
16-Blt Bus Width
The various access sequences as well as the duplication of
data are summarized in tables 3-11 to 3-13.
Up to two access cycles are needed to complete the write
operation.
2-56
z
(J)
3.0 Functional Description (Continued)
w
I\)
Example: MOVW RO, @5
signals. By asserting HOLD, an external device requests access to the bus. On receipt of HLDA from the CPU, the
device may perform bus cycles, as the CPU at this point has
placed all the output signals shown in Figure 3-30 into the
TRI-STATE condition.
• The CPU duplicates byte 1 of the data bus into byte 0 and
performs a write cycle at address 5 with BE1 and BE2
active.
• A write at address 6 is then performed with BE2 active
and the original byte 2 of the data bus placed on byte O.
8-Blt Bus Width
To return control of the bus to the CPU, the external device
sets HOLD inactive, and the CPU acknowledges return of
the bus by setting HLDA inactive.
Up to 4 access cycles are needed in this case to complete
the write operation.
Example: MOVB RO, @7
The CPU samples HOi]) in the middle of each T-state on
the falling edge of BCLK. If ROID is asserted when the bus
is idle between access sequences, then the bus is granted
immediately (see Figure 3-2U). If HOLD is asserted during
an access sequence, then the bus is granted immediately
after the access sequence, including any retried bus cycles,
has completed (see Figure 4-13). Note that an access sequence can be composed of several bus cycles if the bus
width is 8 or 16 bits.
• The CPU duplicates byte 3 of the data bus into bytes 0
and 1, and then performs a write cycle at address 7 with
BE3 active.
3.5.7 Bus Access Control
The NS32GX32 has the capability of relinquishing its control
of the bus upon request from a DMA device or another CPU.
This capability is implemented with the HOLD and HLDA
Address
LSB
1
00
1
01
1
10
-
Data to be Written
Address
Bus
BEO-3
Data Bus
-
-
BO
A
HHHL
BO
-
A
HHLH
•
•
•
•
BO
BO
BO
-
A
HLHH
•
BO
•
BO
-
-
-
A
LHHH
BO
BO
BO
A
HH LL
•
•
•
BO
B1
B1
BO
•
BO
1
11
BO
2
00
2
01
-
B1
BO
HLLH
•
B1
BO
BO
10
B1
BO
-
-
A
2
A
LLHH
B1
BO
B1
BO
3
00
-
B2
B1
BO
A
HLLL
•
B2
B1
BO
3
01
B2
B1
BO
-
A
LLLH
B2
B1
BO
BO
4
00
B3
B2
B1
BO
A
LLLL
B3
B2
B1
BO
Number
of Bytes
Address
LSB
1
00
1
01
1
10
-
1
11
BO
2
00
2
01
-
TABLE 3-12. Data Writes to a 16-Blt Bus
Data to be Written
-
Address
Bus
BEO-3
Data Bus
-
BO
A
HHHL
•
BO
-
A
HHLH
-
HLHH
-
-
A
•
•
A
LHHH
BO
B1
BO
A
HHLL
B1
BO
-
A
A+1
HLLH
HLHH
•
•
BO
•
•
•
•
BO
BO
BO
BO
•
BO
•
•
BO
BO
B1
BO
B1
BO
•
•
BO
B1
2
10
B1
BO
-
-
A
LLHH
B1
BO
B1
BO
3
00
-
B2
B1
BO
A
A+2
HLLL
HLHH
•
•
B2
B1
•
•
BO
B2
B2
B1
-
A
A+1
LLLH
LLHH
B2
B1
•
•
BO
B2
BO
B1
BO
A
A+2
LLLL
LLHH
B3
B2
•
•
B1
B3
BO
B2
3
4
01
00
B3
B2
BO
B1
><
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•
I\)
Q
......
Z
(J)
w
I\)
Ci)
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w
I\)
N
U1
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(J)
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I\)
Ci)
><
w
•
W
I\)
Q
TABLE 3-11. Data Writes to a 32-Blt Bus
1. Bytes on the data bus marked with '.' are undefined.
Number
of Bytes
Ci)
2-57
o
~
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3.0 Functional Description (Continued)
><
CJ
TABLE 3-13. Data Writes to an 8-Blt Bus
N
C")
Number
of Bytes
Address
LSB
1
00
1
01
><
CJ
1
10
-
C")
1
11
80
2
00
U)
Z
.......
LI)
~
C")
N
U)
Z
.......
.
o
N
N
C")
><
CJ
N
~
Z
2
2
3
3
4
01
10
00
01
00
Address
Bus
Data to be Written
-
-
-
80
A
80
A
A
A+1
-
-
-
-
81
80
-
81
80
81
80
80
-
82
82
81
83
82
A
A
-
A
A+1
-
-
A
A+1
81
80
A
A+1
A+2
80
81
-
A
A+1
A+2
80
A
A+1
A+2
A+3
2-58
BEO-3
HHHL
HHLH
HLHH
LHHH
HHLL
HHLH
HLLH
HLHH
LLHH
LHHH
HLLL
HLLH
HLHH
LLLH
LLHH
LHHH
LLLL
LLLH
LLHH
LHHH
Data Bus
•
80
80
80
80
•
80
80
80
81
•
•
•
•
•
•
80
81
81
80
•
•
•
81
80
81
•
•
•
•
82
81
•
•
•
•
•
•
82
81
80
•
•
•
•
•
•
83
82
81
•
•
•
•
•
•
•
•
•
•
80
•
•
•
•
•
80
81
80
81
80
81
82
80
81
82
80
81
82
83
z
en
w
3.0 Functional Description (Continued)
TI
TI
~
TI
BCLK [
-- -00-3{-- }- -- ---- .-- -- --
AO-3{
,-
~-
po-- ~S- ~--
{
po-- ~S- po--
--
X
><
W
~
~
Q
......
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en
w
-- ---- ....
(-
~-
~
C)
><
W
~-
.
r-
~
~
--- C~ -'- --- -- ----- \. /
'- --- -- ---- I~ - V
'- .-- -- ----- \ - - -- --
ODIN [
~S- po - -
~--
U1
......
z
~-
en
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~
~S-
ADS [
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•
W
~
~S-
BI.4T [
~S-
CONF [
HOLD [
C)
"Jifth
TI
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Q
r--
r~
JJ
HLDA [
\
BOUT [
'- ~--
..
rt
BEO- 3 [
r
~--
CASEC [
r
~--
/
-\.
-( X
--- -_. -- -( ~ -J
~-- ~S- ~--
~
1--' ~S- ~--
~S- ~
r--
~
I---
p0-
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rt
STO- 4 [
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TL/EE/10253-37
FIGURE 3-30. Hold Acknowledge. (Bus Initially Idle.)
Note: The status indicates 'IDLE' while the bus is granted. If the cause of the IDLE changes (e.g., CPU starts waiting for an interrupt), the status also changes.
state T2. If the cycle is extended, then the CPU uses the
10DEC value sampled during the last wait state. If a bus
error or a bus retry occurs, the sampled 10DEC value is
ignored. 10DEC must be kept high during burst transfer cycles.
When 10DEC is active during a bus cycle for which 10lNH is
asserted, the CPU discards the data and applies the special
handling required for I/O devices. Figure 3-31 shows a possible implementation of an I/O device interface where the
address mapping of the I/O devices is fixed.
In an open system configuration, 10DEC could be generated
by the decoding logic of each I/O device subsystem.
The CPU will never grant the bus between interlocked read
and write bus cycles.
Note: If an external device requires a very short latency to get control of the
bus, the bus retry signal (BRn can be used instead of hold. See
Section 3.5.5.
3.5.8 Interfacing Memory-Mapped I/O Devices
In Section 3.1.3.2 it was mentioned that some special precautions are needed when interfacing I/O devices to the
NS32GX32 due to its internal pipelined implementation.
Two special signals are provided for this purpose: 10lNH
and 10DEC. The CPU asserts 10lNH during a read bus cycle
to indicate that the bus cycle should be ignored if an I/O
device is selected. The system responds by asserting
10DEC to indicate to the CPU that an I/O device has been
selected. 10DEC is sampled by the CPU in the middle of
Note 1: When IODEC is active in response to a read bus cycle, the CPU
treats the reference as noncacheable.
Note 2: iOiNH is kept inactive during write cycles.
2-59
. r---------------------------------------------------------------------------3.0 Functional Description
Q
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3.5.10 Internal Status
The NS32GX32 provides information on the system interface concerning its internal activity.
CJ
N
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U)
Z
.......
Lt)
NS32GX32
CPU
The UlS signal will indicate the state of the U bit in the PSR
except in the following cases:
While executing a MOVUS instruction it will be '1' during the
source read.
ADDRESS
N
N
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C")
U)
Z
.......
.
Q
N
N
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><
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U)
Z
While executing a MOVSU instruction it will be '1' during the
destination write.
TL/EE/10253-38
N
FIGURE 3-31. Typical 110 Device Interface
The PFS signal is asserted for one BClK cycle when the
CPU begins executing a new instruction. The ISF signal is
driven High along with PFS if the new instruction does not
follow the previous instruction in sequence. More specifically, ISF is High along with PFS after processing an exception
or after executing one of the following instructions: ACB
(branch taken), Bcond (branch taken), BR, BSR, CASE,
CXP, CXPD, DIA, JSR, JUMP, RET, RETT, RETI, and RXP.
3.5.9 Interrupt and Debug Trap Requests
Three signals are provided by the CPU to externally request
interrupts and/or a debug trap. INT and NMI are for maskable and non-maskable interrupts respectively. DBG is used
for requesting an external debug trap.
The CPU samples INT and NMI on every other rising edge
of BClK, starting with the second rising edge of BClK after
RST goes high.
NMI is edge-sensitive; a high-to-Iow transition on it is detected by the CPU and stored in an internal latch, so that there
is no need to keep it asserted until it is acknowledged.
INT is level-sensitive and, as such, once asserted, it must
be kept asserted until it is acknowledged.
The DBG signal, like NMI, is edge-sensitive; it differs from
NMI in that the CPU samples it on each rising edge of
BClK. DBG can be asserted asynchronously to the CPU
clock, but it should be at least 1.5 clock cycles wide in order
to be recognized.
If DBG meets the specified setup and hold times, it will be
recognized on the rising edge of BClK deterministically.
Refer to Figures 4-19 and 4-20 for more details on the timing of the above Signals.
The BP signal is asserted for one BClK cycle when an address-compare or PC-match condition is detected. If the BP
signal is asserted one BClK cycle after PFS, it indicates
that an address-compare debug condition has been detected. If BP is asserted at any other time, it indicates that a PCMatch debug condition has been detected.
While executing a CINV instruction, the CPU displays the
operation code and source operand using slave processor
write bus cycles.
During idle bus cycles, the signals STO-ST4 indicate whether the CPU is waiting for an interrupt, waiting for a Slave
Processor to complete executing an instruction or halted.
m
Note: If the
signal is pulsed to request a non-maskable Interrupt, it may
be necessary to keep it asserted for a minimum of two clock cycles to
guarantee its detection, unless extra logic ensures that the pulse occurs around the BCLK sampling edge.
2-60
z
en
w
4.0 Device Specifications
N
Ci)
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•
ADDRESS
""KI"{
W
N
N
DATA
o
........
BUS ACCESS {
CONTROL
Z
en
w
N
RESET
Ci)
EXCEPTION [
REOUEST
><
W
N
N•
BUS TIt.4ING AND
CONTROL OUTPUTS
U1
........
Z
INTERNAL {
STATUS
en
w
NS32GX32
N
Ci)
><
W
N
W
·
BWO-I
o
SLAVE TIt.4ING
} AND CONTROL
CACHE CONTROL {
TL/EE/l0253-39
FIGURE 4-1. NS32GX32 Interface Signals
4.1 NS32GX32 PIN DESCRIPTIONS
Descriptions of the NS32GX32 pins are given in the following sections.
4.1.2 Input Signals
ClK
Clock.
Input Clock used to derive all CPU Timing.
Included are also references to portions of the functional
description, Section 3.
Figure 4-1 shows the NS32GX32 interface signals grouped
according to related functions.
Synchronize.
When SYNC is active, BCLK will stop toggling. This signal can be used to synchronize
two or more CPUs (Section 3.5.2).
Note: An asterisk next to the signal name indicates a TRI-STATE condition
for that signal when fR5lJ5 is acknowledged or during an extended
retry.
Hold Request.
When active, causes the CPU to release the
bus for DMA or multiprocessing purposes
(Section 3.5.7).
4.1.1 Supplies
VCCl1-6
logic Power.
Note:
+ 5V positive supplies for on-chip logic.
VCCB1-14
VCCClK
GNDl1-6
GNDB1-13
GNDClK
If the fR5lJ5 signal is generated asynchronously, its set
up and hold times may be violated. In this case it is recommended to synchronize it with the falling edge of
BCLK to minimize the possibility of metastable states.
Buffers Power.
+ 5V positive supplies for on-chip output
buffers.
Bus Clock Power.
+ 5V positive supply for on-chip clock drivers.
logic Ground.
Ground references for on-chip logic.
Buffers Ground.
Ground references for on-chip output buffers.
Bus Clock Ground.
Ground reference for on-chip clock drivers.
The CPU provides only one synchronization stage to minImize the HLDA latency. This is to avoid speed degradations in cases of heavy fR5lJ5 activity (I.e. DMA controller
cycles interleaved with CPU cycles).
RST
INT
2-61
Reset.
When RST is active, the CPU is initialized to
a known state (Section 3.5.3).
Interrupt.
A low level on this signal requests a maskable interrupt (Section 3.5.9).
Nonmaskable Interrupt.
A High-to-Low transition of this signal requests a nonmaskable interrupt (Section
3.5.9).
oC") .-------------------------------------------------------------------------.
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4.0 Device Specifications (Continued)
DBG
C")
en
z
.......
Debug Trap Request.
4.1.3 Output Signals
BCLK
Bus Clock.
A High-to-Low transition of this signal requests a debug trap (Section 3.5.9).
N
CIIN
It)
~
N
C")
><
CJ
N
Output clock for bus timing (Section 3.5.2).
Cache Inhibit In.
Bus Clock Inverse•
When active, indicates that the location referenced in the current bus cycle is not cacheable. CIIN must not change within an aligned
16-byte block.
Inverted output clock.
Hold Acknowledge.
Activated by the CPU in response to the
HOLD input to indicate that the CPU has released the bus.
I/O Decode.
C")
en
Indicates to the CPU that a peripheral device
is addressed by the current bus cycle. The
value of IODEC must not change within an
aligned 16-byte block (Section 3.5.8) .
z
.......
o
N
N
•
><
CJ
C")
Program Flow Status.
A pulse on this Signal indicates the beginning
of execution for each instruction (Section
3.5.10).
Force Slave Status Read.
ISF
When asserted, indicates that the. slave
status word should be read by the CPU (Section 3.1.4.1). An external 10 kn resistor
should be connected between FSSR and
Vee·
N
C")
en
z
Indicates along with PFS that the instruction
beginning execution is sequential (ISF Low)
or non-sequential (ISF High).
U/S
Slave Done.
User/Supervisor.
User or supervisor mode status (Section
3.5.10).
Used by a slave processor to signal the completion of a slave instruction (Section
3.1.4.1). An external 10 kn resistor should be
connected between SON and Vee.
Break Point.
This signal is activated when the CPU detects a PC or operand-address match debug
condition (Section 3.3.2).
Burst In.
CASEC
When active, indicates to the CPU that the
memory supports burst cycles (Section
3.5.4.3).
·Cache Section.
For cacheable data read bus cycles indicates
the Section of the on-chip Data Cache where
the data will be placed; undefined for other
bus cycles.
Ready.
While this signal is not active, the CPU extends the current bus cycle to support a slow
memory or peripheral device.
BWO-1
Internal Sequential Fetch.
110 Inhibit.
Indicates that the current bus cycle should
be ignored if a peripheral device is addressed.
Bus Width.
These lines define the bus width (8, 16 or 32
bits) for each data transfer; BWO is the least
significant bit. The bus width must not
change within an aligned 16-byte block-encodings are:
Slave Processor Control.
Data strobe for slave processor transfers.
·Burst Out.
When active, indicates that the CPU. is requesting to perform burst cycles.
OO-Reserved
01--8 Bits
Interlocked Operation.
10-16 Bits
When active, indicates that interlocked cycles are being performed (Section 3.5.4.5).
11-32 Bits
Bus Retry.
• Data Direction.
When active, the CPU will reexecute the last
bus cycle (Section 3.5.5).
Indicates the direction of a data transfer. It is
low for reads and high for writes.
Bus Error.
·Conflrm Bus Cycle.
When active, indicates that an error occurred
during a bus cycle. It is treated by the CPU as
the highest priority exception after reset.
When active, indicates that a bus cycle initiated by ADS is valid; that is, the bus cycle has
not been cancelled (Section 3.5.4.2).
2-62
z
en
4.0 Device Specifications (Continued)
BMT
w
I\)
*Begln Memory Transaction.
01000-Sequentiallnstruction Fetch.
When Stable Low indicates that the current
bus cycle is valid; that is, the bus cycle has
not been cancelled (Section 3.5.4.2).
01010-Data Transfer.
Q
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w
I\)
•
I\)
01 001-Non-Sequentiallnstructlon Fetch.
ADS
* Address Strobe.
01 011-Read Read-Modify-Write Operand.
01100-Read for Effective Address.
BEO-3
When active, indicates that a bus cycle has
begun and a valid address Is on the address
bus.
*Byte Enables.
r101)
Used to selectively enable data transfers on
bytes 0-3 of the data bus.
11100
STO-4
o
z
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en
w
N
Q
><
w
Reserved.
·
I\)
I\)
U1
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z
11101-Transfer Slave Operand.
11110-Read Slave Status Word.
Status.
Bus cycle status code; STO is the least significant. Encodings are:
en
w
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Q
11111-Broadcast Slave ID.
OOOOO-idle: CPU Inactive on Bus.
AO-31
• Address Bus.
Used by the CPU to output a 32-bit address
at the beginning of a bus cycle. AO is the
least significant.
00001-ldle: WAIT Instruction.
00010-ldle: Halted.
00011-ldle: The bus is idle while the slave
processor is executing an instruction.
4.1.4InputlOutput Signals
00100-lnterrupt Acknowledge, Master.
00-31
><
w
·
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o
·Data Bus.
00101-lnterrupt Acknowledge, Cascaded.
Used by the CPU to input or output data during a read or write cycle respectively.
00110-End of Interrupt, Master.
00111-End of Interrupt, Cascaded.
4.2 ABSOLUTE MAXIMUM RATINGS
All Input or Output Voltages with
Respect to GND
Power Dissipation
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Case Temperature Under Bias
Storage Temperature
-0.5Vto +7V
4W
Note: Absolute maximum ratings indicate limits beyond
which permanent damage may occur. Continuous operation
at these limits is not intended,' operation should be limited to
those conditions specified under Electrical Characteristics.
O°C to + 95°C
- 65°C to + 150°C
4.3 ELECTRICAL CHARACTERISTICS NS32GX32-20, 25: TeASE = 0° to + 95°C, Vee = 5V ± 10%, GND = OV
NS32GX32-30: TeASE = 0° to + 95°C, Vee = 5V ±5%, GND = OV.
Symbol
Parameter
Typ
Max
Units
VIH
High Level Input Voltage
2.0
Vee + 0.5
V
VIL
Low Level Input Voltage
-0.5
0.8
V
VOH
High Level Output Voltage
IOH
= -400 p,A
VOL
Low Level Output Voltage
AO-11, DO-31, DDIN
CONF, BMT
BCLK, BCLK
All Other Outputs
IOL
IOL
IOL
IOL
=
=
=
=
IL
Input Load Current
o ~ VIN
IL
Leakage Current (Output and
I/O. pins in TRI-STATE/lnput Mode)
0.4 ~ VIN ~ Vee
CIN
CLK Input Capacitance
lee
Active Supply Current
Conditions
Min
2.4
V
0.45
0.45
0.45
0.45
V
V
V
V
-20
20
p,A
-20
20
p,A
4mA
6mA
16mA
2mA
~ Vee
pF
10
lOUT = 0, TA
Vee = 5V
= 25°C
2-63
700 @ 30 MHz
600 @ 25 MHz
470@20MHz
800 @ 30 MHz
700 @ 25 MHz
575 @ 20 MHz
rnA
fJ
4.0 Device Specifications (Continued)
Connection Diagram
S@@@@@@@@@@@@@@@@
R@@@@@@@@@@@@@@@@
P@@@@@@@@@@@@@@@@
N@@@@@@@@@@@@@@@@
M@@@
@@@
L@@@
@@@
K@@@
@@@
J @@ @
NS32GX32
@@ @
H@@@
@@@
G@@@
@@@
F@@@
@@@
E@@@
@@@
D@@@@@@@@@@@@@@@@
C@@@@@@@@@@@@@@@@
B@@@@@@@@@@@@@@@@
A@@@@@@@@@@@@@@@
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
TL/EEI10253-40
Bottom View
FIGURE 4-2. 17S-Pln PGA Package
NS32GX32 Pinout Descriptions
Desc
Pin
Desc
Reserved
Reserved
Reserved
BP
15F
RST
NMI
GNOB1
Reserved
VCC82
Reserved (2)
Reserved (1)
Reserved (2)
Reserved (2)
VCCB1
Reserved
VCCB4
Reserved
Reserved
VCCB3
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
812
B13
B14
B15
026
Reserved
Reserved
VCCL2
Reserved
PF5
FSSR
INT
VCCL1
GNOL2
Reserved (2)
Reserved (2)
Reserved (2)
Reserved (2)
030
028
Pin
B16
C1
C2
C3
C4
C5
SON
C6
Reserved
C7
BCLK
C8
VCCCLK
C9
SYNC
C10
Reserved (2) C11
Reserved (2) C12
VCCL6
C13
029
C14
027
C15
025
C16
U/S
01
Reserved
02
Reserved
03
GNOL3
04
GNOB2
05
DBG
06
Reserved
07
BCLK
08
GNOCLK
09
CLK
010
Reserved (2) 011
031
012
GNOL1
013
Desc
Pin
GNOB13
VCCB14
023
IOINH
014
015
016
E1
E2
GNOB3
E3
024
E14
022
E15
020
E16
A30
F1
~
F2
Reserved F3
021
F14
019
F15
018
F16
A29
G1
A31
G2
VCC85
G3
GNOB12 G14
017
G15
016
G16
A27
H1
A28
H2
GNOB4
H3
VCCB13
H14
015
H15
014
H16
A26
J1
A25
J2
A24
J3
reo
Desc
Pin
Desc
Pin
Delc
Pin
GNOL6
VCCL5
013
VCC86
A23
GNOL4
GNOB11
011
012
A22
A21
VCCL3
08
09
010
A20
GNOB5
A17
05
07
VCCB12
A19
A18
A14
A11
VCC88
GN087
5T4
HLOA
J14
J15
J16
K1
K2
K3
K14
K15
K16
L1
L2
L3
L14
L15
L16
M1
M2
M3
M14
M15
M16
N1
N2
N3
N4
N5
N6
N7
N8
GNOL5
N9
N10
N11
N12
N13
N14
N15
N16
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
P16
R1
R2
R3
R4
R5
AO
VCCB9
Reserved
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
51
52
53
54
55
56
S7
58
59
510
511
512
513
514
515
516
CONF
ROY
AO[[)
VCCB11
GNOB10
04
06
A16
VCC87
GNOB6
A10
A6
A2
5T3
GNOB8
VCCL4
BE1
GNOB9
BWO
m
Reserved
DO
03
A15
A12
A9
A7
A4
SPC
BE3
VCC810
ADS
BW1
SEA
CIIN
02
A13
A8
A5
A3
A1
ST2
ST1
STO
l300T
tmTfJ
BE2
BEO
BMT
BR'f
~
01
Note 1: This pin should be grounded.
Note 2: This pin should be connected to logical high.
All other reserved pins should be left open.
2-64
z
en
w
4.0 Device Specifications (Continued)
I\)
4.4.1 Definitions
All the timing specifications given in this section refer to
O.BV or 2.0V on all the signals as illustrated in Figures 4-3
and 4-4, unless specifically stated otherwise.
.ru[
S1G'[
S~[
Ci)
ABBREVIATIONS:
L.E.-Ieading edge R.E.---rising edge
T.E.-training edge F.E.-falling edge
4.4 SWITCHING CHARACTERISTICS
><
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0
.......
Z
en
w
2.0V
BClK[
I\)
O.SV
Ci)
2.0V
O.SV
tslGlh
tslGh
SIG{
------------ 2."V
2.0V
O.SV
S~{
O."5V
tSIG2v
tSIG2h
2.0V
UV
2.4V
t SIGh
tSIGlh
CJ'1
.......
z
en
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tSIG21
Ci)
tSIG2h
O."5V
TL/EE/10253-42
O.SV
- - - -- --- - - -- --O."5V
FIGURE 4·4. Input Signals Specification Standard
TL/EE/10253-41
FIGURE 4·3. Output Signals Specification Standard
2-65
><
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·
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W
0
o
C?
N
CW)
><
CJ
N
CW)
(J)
Z
.......
LI)
N
N
CW)
><
CJ
N
4.0 Device Specifications (Continued)
4.4.2 Timing Tables
4.4.2.1 Output Signals: Internal Propagation Delays, NS32GX32-20, NS32GX32-25, NS32GX32-30
• Maximum times assume capacitive loading of 100 pF on the clock signals and 50 pF on all the other signals. A minimum
capacitance load of 50 pF on BClK and BClK is also assumed .
• The output to input timings (e.g., Address to RDY, Address to BER, etc.) are at least 2 ns better than the worst case values
calculated from the output valid and Input setup times relative to BClK or B'CD<.
Name
Figure
Description
Reference/Conditions
CW)
(J)
NS32GX32-20
NS32GX32-25
NS32GX32-30
Units
Min
Max
Min
Max
Min
Max
100
40
100
33.3
100
ns
tscp
4-24
Bus Clock Period
R.E., BClK to Next
R.E., BClK
50
N
tSCh
4-24
BClK High Time
20
16
13
><
CJ
At 2.0V on BClK
(Both Edges)
tSCI
4-24
BClK low Time
At O.BV on BClK
(Both Edges)
20
16
13
tscr
(Note 1)
4-24
BClK Rise Time
O.BV to 2.0V on
R.E., BClK
5
4
3
ns
tsCt
(Note 1)
4-24
BClK Fall Time
2.0V to O.BV on
F.E., BClK
5
4
3
ns
tNSCh
4-24
BClK High Time
At 2.0V on BClK
(Both Edges)
20
16
13
tNSCI
4-24
BClK low Time
At O.BV on BClK
(Both Edges)
20
16
13
tNSCr
(Note 1)
4-24
BClK Rise Time
O.BV to 2.0V on
R.E., BClK
5
4
3
ns
tNSCt
(Note 1)
4-24
BClK Fall Time
2.0V to O.BV on
F.E., BClK
5
4
3
ns
tCSCdr
4-24
ClKto BClK
R.E. Delay
2.0V on R.E., ClK to
2.0V on R.E., BClK
20
17
15
ns
tCSCdf
4-24
ClKto BClK
F.E. Delay
2.0V on R.E., ClK to
O.BV on F.E., BClK
20
17
15
ns
tCNSCdr
4-24
ClKto BClK
R.E. Delay
2.0V on R.E., ClK to
O.BV on R.E., BClK
20
17
15
ns
tCNSCdt
4-24
ClKto BClK
F.E. Delay
2.0V on R.E., ClK to
O.BV on F.E., BClK
20
17
15
ns
tSCNBCr
(Note 1
4-24
Bus Clocks Skew
2.0V on R.E., BClK to
O.BV on F.E., BClK
-2
+2
-2
+2
-2
+2
ns
tSCNSCtr
(Note 1)
4-24
Bus Clocks Skew
O.BV on F.E., BClK to
2.0V on R.E., BClK
-2
+2
-2
+2
-2
+2
ns
B
ns
Z
.......
o
N
CW)
N
CW)
(J)
Z
tAv
4-5,4-6
Address Bits 0-31 After R.E., BClK Tl
Valid
tAh
4-5,4-6
Address Bits 0-31 After R.E., BClK Tl or Ti
Hold
tAt
4-11,4-12 Address Bits 0-31 After F.E., BClK Ti
Floating
tAnt
4-11,4-12 Address Bits 0-31 After F.E., BClK Ti
Not Floating
11
0
9
0
17
21
0
Note 1: Guaranteed by characterization. Due to tester conditions, this parameter is not 100% tested.
2-66
0
0
ns
13
0
ns
ns
z
en
w
4.0 Device Specifications (Continued)
~
C)
><
w
4.4.2.1 Output Signals: Internal Propagation Delays, NS32GX32-20, NS32GX32-25, NS32GX32-30 (Continued)
Name
Figure
Description
Reference/Conditions
NS32GX32-20
Min
tAS v
tASh
toov
tOOh
4-8
4-8
Address Bits A2, A3
Valid (Burst Cycle)
After RE., BCLK T2B
Address Bits A2, A3
Hold (Burst Cycle)
After R.E., BCLK T2B
4-6,4-15 Data Out Valid
4-6,4-15 Data Out Hold
After RE., BCLK T1 or Ti
Before SPC T.E.
tOOf
4-7
Data Bus Floating
After RE., BCLK
T10rTi
tOOnf
4-7
Data Bus
Not Floating
After F.E., BCLK T1
tSMTv
4-5,4-7
BMT Signal Valid
After R.E., BCLK T1
tSMTh
4-5,4-7
BMT Signal Hold
After RE., BCLK T2
4-11,4-12 BMT Signal Floating
After F.E., BCLK Ti
tSMThf
4-11,4-12 BMTSignal
Not Floating
After F.E., BCLK Ti
CONF Signal Active
After R.E., BCLK T1
4-5,4-8
CONF Signal Inactive After R.E., BCLK T1 or Ti
After F.E., BCLK Ti
tAOSia
4-5,4-8
ADS Signal Inactive
After F.E., BCLK T1
tAOS w
4-6
ADS Pulse Width
At 0.8V (Both Edges)
tAOSf
After F.E., BCLK Ti
tAOSnf
4-11,4-12 ADS Signal
Not Floating
After F.E., BCLK Ti
BEn Signals Valid
After R.E., BCLK T1
tSEh
4-6,4-8
BEn Signals Hold
After RE., BCLK T1,
Ti orT2B
tSEf
4-11,4-12 BEn Signals Floating
After F.E., BCLK Ti
tSEnf
4-11,4-12 BEn Signals
Not Floating
After F.E., BCLK Ti
tOOINnf 4-11,4-12 ODIN Signal
Not Floating
tSPc a
4-14,4-15 SPC Signal Active
ns
en
w
~
0.5 tscp
+ 11
><
w
·
~
~
U1
ns
.......
en
w
z
0
ns
8
6
5
ns
><
w
ns
o
0
17
0
32
0
0.5 tsc p
27
0
0
ns
ns
ns
9
8
ns
13
ns
0
9
17
0
0
ns
ns
8
8
ns
13
ns
0
0
17
ns
0
0
15
ns
ns
0
9
ns
ns
13
17
ns
ns
0
0
19
8
0
0
0
ns
13
9
11
8
9
12
11
ns
0
9
11
0
2-67
13
17
21
After R.E., BCLK T1
ns
11
0
After F.E., BCLK Ti
ns
21
21
After RE., BCLK T1 or Ti
23
0.5tscp
0.5 tscp
0.5 tscp
0.5 tscp
0.5 tscp
+ 11
+8
+9
15
After F.E., BCLK Ti
ns
0
17
11
After RE., BCLK T1
13
0
0
0
4-6,4-8
ODIN Signal Hold
z
ns
0
0.5 tscp
+12
21
tSEv
4-5,4-6
8
·
~
o
.......
0
After RE., BCLK T1
4-11,4-12 ADS Signal Floating
4-11,4-12 ODIN Signal Floating
Max
0
0
ADS Signal Active
tOOINf
0.5 tscp
+13
4-11,4-12 CONF Signal Floating After F.E., BCLK Ti
ODIN Signal Valid
0
0
4-5,4-8
tOOINh
0
21
4-5,4-8
4-5,4-6
9
21
tAOSa
tOOINv
Min
~
·
~
tSMTf
tCONFnf 4-11,4-12 CONFSignal
Not Floating
Max
~
Units
C)
Data Out Setup
(Slave Write)
tCONFf
11
After R.E., BCLK T1
4-15
tCONFia
Min
NS32GX32-30
C)
toospc
tCONFa
Max
NS32GX32-25
ns
12
ns
w
oC")
I
N
4.0 Device Specifications (Continued)
><
4.4.2.1 Output Signals: Internal Propagation Delays, NS32GX32-20, NS32GX32-25, NS32GX32-30 (Continued)
C")
"enz
N
C")
Name
Figure
Description
Reference/Conditions
.......
NS32GX32-20 NS32GX32-25 NS32GX32-30
Min
Max
Min
Max
Min
Units
Max
It)
N
I
N
C")
><
"en
N
tSPCia
tDDSPC
(Note 1)
C")
z
.......
tHLDAa
4-14,4-15 SPC Signal Inactive
4-14
ODIN Valid to
SPCActive
4-12,4-13 HLDA Signal Active
4-12
HLDA Signal Inactive
After R.E., BCLK Ti, T1 or T2
Before SPC L.E.
19
0
15
12
ns
0
0
ns
After F.E., BCLK Ti
15
11
10
ns
o
tHLDAia
After F.E., BCLK Ti
15
11
10
ns
N
C")
tSTv
4-5,4-14 Status (STO-4) Valid
After R.E., BCLK T1
11
9
8
ns
tSTh
4-5,4-14 Status (STO-4) Hold
After R.E., BCLK T1 or Ti
N
><
"en
N
C")
z
0
0
ns
0
tSOUTa
4-8,4-9
BOUT Signal Active
After R.E., BCLK T2
15
12
11
ns
tSOUTia
4-8,4-9
BOUT Signal Inactive
After R.E., BCLK
Last T2B, T1 or Ti
15
12
11
ns
After F.E., BCLK Ti
21
17
13
ns
tSOUTf
4-11,4-12 BOUT Signal Floating
tSOUTn! 4-11,4-12 BOUT Signal
Not Floating
After F.E., BCLK Ti
0
0
ns
0
tlLO a
4-7
Interlock Signal Active
After F.E., BCLK Ti
11
9
8
ns
tlLOia
4-7
Interlock Signal Inactive After F.E., BCLK Ti
11
9
8
ns
tpFS a
4-21
PFS Signal Active
After F.E., BCLK
15
11
10
ns
tPFSia
4-21
PFS Signal Inactive
After F.E., Next BCLK
15
11
10
ns
tlSFa
4-22
ISF Signal Active
After F.E., BCLK
15
11
10
ns
tlSFia
4-22
ISF Signal Inactive
After F.E., Next BCLK
15
11
10
ns
tSPa
4-23
BP Signal Active
After F.E., BCLK
15
11
10
ns
tSPia
4-23
BP Signal Inactive
After F.E., Next BCLK
15
11
10
ns
tusv
4-5
U/S Signal Valid
After R.E., BCLK T1
8
ns
tUSh
4-5
U/S Signal Hold
After R.E., BCLK T1 or Ti
tCAS v
4-5
CASEC Signal Valid
After F.E., BCLK T1
tCASh
4-5
CASEC Signal Hold
After R.E., BCLK T1 or Ti
tCAS,
4-11,4-12 CASEC Signal Floating
After F.E., BCLK Ti
tCASn!
4-11,4-12 CASEC Signal
Not Floating
After F.E., BCLK Ti
tlOl v
4-5
IOINH Signal Valid
After R.E., BCLK T1
tlOl h
4-5
IOINH Signal Hold
After R.E., BCLK T1 or Ti
11
0
15
0
0
11
10
0
13
10
0
ns
ns
0
11
0
ns
ns
0
17
15
0
ns
0
0
21
Note 1: Guaranteed by characterization. Due to tester conditions, this parameter is not 100% tested.
2·68
9
0
ns
ns
z
en
w
4.0 Device Specifications (Continued)
N
G')
4.4.2.2 Input Signal Requirements: NS32GX32-20, NS32GX32-25, NS32GX32-30
Name
Figure
Description
Reference/Conditions
><
W
NS32GX32-20
NS32GX32-25
NS32GX32-30
Min
Max
Min
Max
Min
Max
25
50
20
50
16.6
50
Units
N
I
N
o
.......
Z
en
w
tc p
4-24
Input Clock Period
R.E., ClK to Next
R.E, ClK
tCh
4-24
ClK High Time
At 2.0V on ClK
(Both Edges)
0. 5tc p
-5ns
0.5 tc p
-5 ns
0.5 tc p
-4ns
><
W
0. 5tc p
-5ns
0.5 tc p
-5 ns
0.5 tc p
-4ns
.......
Z
tCI
4-24
ClK low Time
At 0.8V on ClK
(Both Edges)
tC r
(Note 1)
4-24
ClK Rise Time
0.8V to 2.0V on R.E, ClK
tCt
4-24
ClK Fall Time
2.0V to 0.8V on F.E, ClK
ns
NI
N
U1
en
w
5
4
3
ns
N
G')
5
4
3
ns
W
N
I
W
><
(Note 1)
o
to Is
4-5,4-14 Data In Setup
Before R.E., BClK T1 or Ti
13
11
9
ns
tOlh
4-5,4-14 Data In Hold
After R.E., BClK T1 or Ti
1
1
1
ns
tROY s
4-5
ROY Setup Time
Before R.E., BClK T2(W),
T10rTi
22
18
15
ns
tROYh
4-5
ROY Hold Time
Ater R.E., BClK T2(W),
T10rTi
1
1
1
ns
tsws
4-5
BWO-1 Setup Time Before F.E., BClK T2 or T2(W)
21
17
14
ns
4-5
BWO-1 Hold Time
tSWh
tHO LOs
N
G')
4-12,4-13 HOLD Setup Time
After F.E., BClK T2 or T2(W)
Before F.E., BClK
1
1
1
ns
21
17
14
ns
1
1
1
ns
21
17
14
ns
1
1
1
ns
21
17
14
ns
1
1
1
ns
21
17
14
ns
1
1
1
ns
21
17
14
ns
1
1
1
ns
50
40
30
p.s
tHOLOh
4-12
HOLD Hold Time
After F.E., BClK
tSINs
4-8
BIN Setup Time
Before F.E., BClK T2 or T2(W)
tSINh
4-8
tSERs
4-6,4-8
BER Setup Time
Before R.E., BClK T1 or Ti
tSERh
4-6,4-8
BER Hold Time
After R.E., BClK T1 or Ti
tSRTs
4-6,4-8
BRT Setup Time
Before R.E., BClK T1 or Ti
tSRTh
4-6,4-8
BRT Hold Time
After R.E, BClK T1 or Ti
tlOO s
4-5
IODEC Setup Time
Before F.E., BClK T2 or T2(W)
tlOO h
4-5
IODEC Hold Time
After F.E., BClK T2 or T2(W)
tpWR
(Note 1)
4-26
Power Stable to
R.E. of RST
After VCC Reaches 4.5V
tRST s
4-27
RST Setup Time
Before R.E, BClK
14
12
11
ns
tRSTw
4-27
RST Pulse Width
At 0.8V (Both Edges)
64
64
64
tsc p
BIN Hold Time
After F.E., BClK T2 or T2(W)
Note 1: Due to tester conditions, this parameter Is not 100% tested.
2·69
o
M
I
C'II
M
4.0 Device Specifications (Continued)
CJ
4.4.2.2 Input Signal Requirements: NS32GX32-20, NS32GX32-25, NS32GX32-30 (Continued)
><
C'II
M
en
Z
.......
Name
Figure
Description
Reference/Conditions
Min
Lt)
C'II
I
C'II
NS32GX32-20
Max
NS32GX32-25
Min
Max
NS32GX32-30
Min
Units
Max
tClis
4-5
CIIN Setup Time
Before F.E., BCLK T2
21
17
14
ns
><
tClih
4-5
CIIN Hold Time
After F.E., BCLK T2
1
1
1
ns
C'II
tiNTs
4-19
INT Setup Time
Before R.E., BCLK
14
12
11
ns
Z
.......
tlNTh
4-19
INT Hold Time
After R.E., BCLK
1
1
1
ns
C'II
C'II
tNMls
4-19
NMI Setup Time
Before R.E., BCLK
20
17
16
ns
M
tNMlh
4-19
NMI Hold Time
After R.E., BCLK
1
1
1
ns
CJ
tsos
4-16
SON Setup Time
Before R.E., BCLK
14
12
11
ns
tSOh
4-16
SON Hold Time
After R.E., BCLK
1
1
1
ns
tFSSR s
4-17
FSSR Setup Time
Before R.E., BCLK
14
12
11
ns
tFSSRh
4-17
FSSR Hold Time
After R.E., BCLK
1
1
1
ns
tSYNC s
4-25
SYNC Setup Time
Before R.E., CLK
10
8
7
ns
tSYNCh
4-25
SYNC Hold Time
After R.E., CLK
1
1
1
ns
tOBG s
4-20
OBG Setup Time
Before R.E., BCLK
14
12
11
ns
tOBGh
4-20
OBG Hold Time
After R.E., BCLK
1
1
.1
ns
M
CJ
M
en
.
o
><
C'II
M
en
Z
2-70
z
en
w
4.0 Device Specifications (Continued)
N
C)
4.4.3 Timing Diagrams
><
W
ANY
I T- STATE I
Tl
T2
I T2 (W) I T1 OR
.......
BCLK [
-
--
r
~- ~~
t AOSa -
ADS [
Bt.n[ r0
CONF [
-~
I--
1/
--
{
--
1/ \
RDY [
BEO-3 [
STO-4 [
U/S [
~tJ::
~teAsv
X
ROYh
tSTh
tUSh
bt-r:1<
~tellh
X
~
-.!
~
'= ~
lX
IODEC [
IOINH [
~
l-
tIOO~
tlO1v '"
·
C
X
CIIN [
---
><
W
N
W
t BWh
...
X
...
tells
CASEC [
N
C)
r-~eONFla
--n..:
tusv
en
w
~ t - -V
N¥\-t
tSTv
Z
\.V
~~
- Xr
- Xr
U1
.......
I-tOOINh
tBWStL 1--
BWO-{
·
N
N
~-.
I¥
.,..If
\cONF'a
><
W
~Olh
-
I- tBt.CTh
!o-
t-
IN
tAOSla
w
N
C)
~_tJ.
~-.
{ltOOINV
DDIN [
en
_~tAh
}-I--. --
DO-3{
Z
-X
--DC -----~
~ tAv
AO-31 [
·
N
N
C
nI
t lOOh
I
~
X
-X
~ASh
t lO1h
I
TL/EE/l0253-43
FIGURE 4·5. Basic Read Cycle Timing
2·71
oC")
•
><
CJ
N
C")
4.0 Device Specifications (Continued)
ANY
IT-STATE I
N
C")
U)
Z
.......
.
T1
T2
BCLK [
..
Lt)
N
N
C")
><
tAv AO-31 [
CJ
N
C")
U)
Z
00-3{
.......
C")
C")
;
\: ~..slt ~
Bton [
f0
U)
Z
-
DATA OUT ~
~
-
....
I
~~ /
\.
1/
~
\. /
RDY [
XD<
BWO-{
t BEv 8EO-3 [
l~tOOINh
I\.V
1/
CONF [
!
tOOh
~
ADS [
><
CJ
N
I}- f-(
ODIN [
tAh
IX
I-
tOJNV-
o
~
/+
[)(
t~ ....
I T1 OR TI I
....
~
X
tBEh
IX
~BRTs
H f-
I}'
BRT [
t BERs
BER [
~
fi
-t
M....
tBRTI
~
STO-4 [
U/s[
TL/EE/10253-44
Note: An Idle State is always inserted before a Write Cycle when the
Write immediately follows a confirmed Read Cycle. AO-31, ODIN,
BEO-3, STO-4 remain unchanged during this idle state.
FIGURE 4·6. Write Cycle Timing
2-72
z
en
w
4.0 Device Specifications (Continued)
N
C)
><
W
·
N
N
o
.....
Z
en
w
AO - 3{-+_-+--+, '+---1r-+--+----!-+--+---I-+-_+' ""t---..;- I':tOOnti - . tOOt
00-31 [-+--+~fJ'})-~-t--K-€!8>-+--+--+-(~ DATA OUT ~}ol-+--+--+--+---.n. tOOINv
tODINh/
r
N
C)
><
•
U1
.....
Z
en
w
W
N
N
r
r-
DDiN[-+_~-+-'L~_~-+--++-Jr~~
ADS [
Bt,tT [
\..v Itt
><
I\..V
t'j'_ ~'=W.l'"'l-BM_T+h~~'"~"" ~V
{t . .
tcONFe. -
BEO - 3 [
N
C)
r
W
N
W
·
o
tcONFIe.
X
XI'-!--+-_
BRT[~-+~~__~~/ \~~~--+-~/ \~~_
BER[~-+~~__~~/ \~-+--~~~/ \~-+-_
STO - 4 [-+--+_+'
"'+--I--+_+--+--+_~-+--+_+-' "'+---+-_
U/S [-+--+_+'
'"+--I--+_+--I--+_~-+--+_+-' "'+---+-_
TL/EE/l0253-45
FIGURE 4-7. Interlocked Read and Write Cycles
2·73
o .--------------------------------------------------------------------,
·
C"')
C\I
C"')
4.0 Device Specifications (Continued)
><
c"
ANY
IT - STATE I
C\I
C"')
CJ)
z
......
...
Lt)
·
><
C\I
C\I
C"')
T1
I
T2
I
~ tAv
tABv-
X
AO-3{
c"
C\I
C"')
CJ)
z
......
T2B
I
T2B
I
T2B
I T1 OR
nI
BCLK [
[
00-31
~
~
to--
~=D< D<
~
~
\.l~KD-KD- -(!N
"
I
o
C\I
C\I
•
><
c"
C\I
C"')
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t ADSa -
ADS [
CJ)
z
BMT [
CONF [
L
\.
ODIN [
C"')
r0
t AOSla
\...V
I~ ~V
-/
I~ l"""- V
~--tcoNra
/ 1\ /
tBWSI)(- fk~
\.
ROY [
,
:-
BWO-{
BEO- 3 [
-- t
tBEv
~ iI_
tBOUTa -
~
I--
lLf\ / r\ '/
I-tBINh
./
;
:-
~
f.
r-
tBER~iBER [
tBOUTla-
;
tBRT~1
BRT [
[
{Ioc,
/
BiN [
CIIN [
J\. t--
L~ L
)(
tB1NSt;l
BOUT [
t
t CONFla -
ex
~1~ \. /
\.V \.
~h \. V \.V
\.
~~
Tl/EE/10253-46
FIGURE 4-8. Burst Read Cycles
2-74
z
(J)
W
4.0 Device Specifications (Continued)
N
G')
ANY
IT-STATE I
T1
T2
T2B
I T2B(W) I T1 or
n
><
W
N
I
N
I
o
.......
Z
(J)
W
N
G')
><
W
N
I
N
U1
.......
Z
(J)
W
N
G)
><
W
N
I
W
o
BOUT [
TLlEE/10253-47
FIGURE 4·9. External Termination of Burst Cycles
ANY
I T- STATE I
T1
T2
T2B
I T1 or
n
I
TL/EE/10253-4B
FIGURE 4·10. Bus Error or Retry During Burst Cycles
Note: Two idle state are always inserted by the CPU following the assertion of BRT.
2-75
o
·
C")
N
C")
r---------------------------------------------------____________________--.
4.0 Device Specifications (Continued)
><
CJ
I
N
T2
C")
tJ)
Z
......
Lt)
·
N
N
AO-3{
C")
><
CJ
N
C")
tJ)
00-3{
Z
......
o
·
><
N
N
I
~~~--~~ ~:
I T1 or
nI
-
tOOINf
ODIN [
-
\..V
ADS [
N
C")
tJ)
Z
TI
-~tAf
C")
CJ
TI
I~~
Bt.fT [
--r-
t Anf
~~
--
l"t-t--
-"r.~~t-·
- r":'Ff _.
- ~I
-- _.
x-;ep.
-
~S-
BRT [
~ t7fi ~
Ii ~
Jj ~
Ii ?A
- -to{· --
-.(K ---w: t
-·ftf
--
~-.
I--
tAOSnf
~S- 1--
~~ po_.
-
~~ po_.
...
tBEf
BEO-3 [
po_.
tOOINnf
t AOSf
1/
CONF [
-- -KD<
~~
~
tcoN~nf
·fCf'
~~ 1--.
.( X
/A IW '<
W
.
I\)
W
o
Vf
1\
·{tx'
..-
r
A
.....
r--
I: toUTn!
tOUT!
'i---r-·
-0
I:.
tf
tHLDAla .....
--
~T ~-
-. ,I teAS!
CASEC [
.
I\)
(J1
.( lornN,1
V
~1:1_.
tHOLDs~
I
I
><
W
I\)
~T ~-
- - -Sf !'"-
t HLra
.r
G)
,\.{I
--00
HLDA [
--00
w
I\,)
--00
I
I
-. {
(f)
- - ~T ~if
..... I:. tBt.4Tn!
r-tHOLDi
I
Z
-- ~~ ~- -ED<
_.
'T~-- -- ~ - {- --
~B~t -. - -
---
~
o
......
1---
~':'t -.
--ADS [
BMT. [
(
IIDIlINt
DDIN[
I\)
~
--r-
-
><
W
"J-UD--L
TI
--00
--~T---
~~!
::D<
\.
~
~
~
~
~
rr
"rr
"
TLlEE/10253-50
FIGURE 4·12. Hold Timing (Bus Initially Idle)
PI
2-77
C) r---------------------------------------------------------------------------------------~
C")
N
C")
4.0 Device Specifications (Continued)
><
CJ
ANY
IT-STATE I
N
T1
T2
TI
TI
ANY.
IT- STATE,
C")
t/)
BCLK [
Z
.......
.
in
N
N
DO - 3{-+_+--+,>-~-+--CI
C")
N
C")
I T1 or TI I
T2
BCLK [
AO-31 [
><
CJ
T1
ADS [
t/)
Z
.......
C)
N
N
•
><
CJ
SPC [
CONr [
DDIN[~ ~~~~~~~ ~~ ~
C")
.....
HOLD [
N
C")
t/)
Z
STO - 4
HLDA [
.....
.....
[--..+.....-+--+" 1o-l-~.....+-.....,r '-+--+-_
TL/EE/10253-52
FIGURE 4·14. Slave Processor Read Timing
TL/EE/10253-51
FIGURE 4·13. HOLD Acknowledge Timing
(Bus Initially Not Idle)
ANY
,T - STATE,
I
T1
T2
I T1 or TI I
,
,
BCLK[FLrUL
I
iI
I
tSOI
sOn
SON [
TL/EE/10253-54
SPC [
FIGURE 4·16. Slave Processor Done
I
ODIN [-+-01--1"
STO - 4
[-+-_+--+'
I
I
BCLK[FLrUL
"'I-.....o!--+O-+'
""+-~_
tF~SRS
I
I I
trssRn
rSSR [
TL/EE/10253-53
FIGURE 4·15. Slave Processor Write Timing
TLlEE/10253-55
FIGURE 4·17. FSSR Signal Timing
2-78
z
en
4.0 Device Specifications (Continued)
w
N
C)
><
•
W
N
N
C
RST
......
Z
en
[-+_+--+-_+'
w
N
C)
rnIT[~__~~~~__~-r~~-~__~-f
><
W
·
N
N
U1
......
Z
en
w
TL/EE/l0253-57
FIGURE 4·18.INT and NMI Signals Sampling
Note 1: iNT and
Note 2: iNT is level sensitive, and once asserted, it should not be deasserted until it is acknowledged.
I
I
I
I
I
DBC [
I
I
I
tPf~a
I
I I
BCLK[JLr1JLIL
I tDBGhI
tOBGST!
tPfSla
TL/EE/l0253-58
TL/EE/l0253-59
FIGURE 4·19. Debug Trap Request
I
I
I
I
tlS~a
I
It I
FIGURE 4·20. PFS Signal Timing
BCLK[JLr1JLIL
~[
lsna
BP[
TL/EE/l0253-60
TL/EE/l0253-61
FIGURE 4·21. ISF Signal Timing
FIGURE 4·22. Break Point Signal Timing
2·79
><
•
W
N
W
C
NMI are sampled on every other riSing edge of BClK, starting with the second rising edge of BClK after RS'i' goes high.
BCLK[JLr1JLIL
N
C)
4.0 Device Specifications (Continued)
'-"----tNBCp,----+I
TL/EE/10253-62
FIGURE 4-23. Clock Waveforms
cLKU-Ll-L1-u-~hh.hJL
t~YNCII
It
I
-
SYNC
I
SYNCh
[
t~YNCs
W -.....-+-.....-
........-
TL/EE/10253-63
FIGURE 4-24. Bus Clock Synchronization
BCLK[__........
Jl-rLJI
tRSTI '\
RST[
-----------------~S
TL/EE/10253-64
FIGURE 4-25. Power-on Reset
BCLK[~JLn.-rl..
JI
RST
'1: 'I
tRSTI
tRSTW
[--\-S....~-~
55
r--TL/EE/10253-65
FIGURE 4-26. Non-Power-on Reset
2-80
z
en
w
Appendix A: Instruction Formats
·
N
N
T = Translated
B = Backward
U/W = 00: None
01: While Match
11: Until Match
f = Floating Point Type Field
F = 1 (Std. Floating: 32 bits)
L = 0 (Long Floating: 64 bits)
o
........
Z
en
w
N
G)
><
W
Configuration bits, in SETCFG Instruction:
c = Custom Type Field
D = 1 (Double Word)
Q = 0 (Quad Word)
I
1
I
1
I
1
I
1
I
I
C
Res
·
N
N
F
(J1
........
Note: Reserved bit must be set to 0 when executing SETCFG.
op = Operation Code
Valid encodings shown with each format.
Z
7
gen, gen 1, gen 2 = General Addressing Mode Field
See Section 2.2 for encodings.
0
I 'co'nd' 11' 0 ' 1' 0 I
reg = General Purpose Register Number
Bcond
·
o
i
i
op
Format 1
15
-0000
-0001
-0010
-0011
-0100
-0101
-0110
-0111
cond: Condition Code (above), in Scond.
ADDQ
CMPQ
SPR
Scond
2-81
ENTER
EXIT
NOP
WAIT
DIA
FLAG
SVC
BPT
81 7
, ,
'Sh'ort
gen
areg: CPU Dedicated Register, in LPR, SPA.
0000 = US
0001 = DCR
0010 = BPC
0011 = DSR
0100 = CAR
0101-0111 = (Reserved)
1000 = FP
1001 = SP
1010 = SB
1011 = USP
1100 = CFG
1101 = PSR
1110 = INTBASE
1111 = MOD
><
W
W
7
Short Immediate value. May contain:
quick: Signed 4-bit value, in MOVQ, ADDQ,
CMPQ, ACB.
N
G)
o
(BR)
BSR
RET
CXP
RXP
RETT
RETI
SAVE
RESTORE
en
w
N
FormatO
cond = Condition Code Field
0000 = EQual: Z = 1
0001 = Not Equal: Z = 0
0010 = Carry Set: C = 1
0011 = Carry Clear: C = 0
0100 = Higher: L = 1
0101 = Lower or Same: L = 0
0110 = Greater Than: N = 1
0111 = Less or Equal: N = 0
1000 = Flag Set: F = 1
1001 = Flag Clear: F = 0
1010 = LOwer: L = 0 and Z = 0
1011 = Higher or Same: L = 1 or Z = 1
1100 = Less Than: N = 0 and Z = 0
1101 = Greater or Equal: N = 1 or Z = 1
1110 = (Unconditionally True)
1111 = (Unconditionally False)
=
><
W
I U/W I BIT I
i = Integer Type Field
B = 00 (Byte)
W = 01 (Word)
D = 11 (Double Word)
short
N
G)
Options: in String Instructions
NOTATIONS:
, ,
1
Format 2
ACB
MOVQ
LPR
-000
-001
-010
-011
-1000
-1001
-1010
-1011
-1100
-1101
-1110
-1111
op
0
11 ' 1 1
-100
-101
-110
oCf)
N
Cf)
><
CJ
C\I
Cf)
t/)
Z
.......
&I)
~
Cf)
><
CJ
C\I
Cf)
t/)
CXPD
-0000
BICPSR
-0010
-0100
JUMP
-0110
BISPSR
Trap (UNO) on XXX1, 1000
TL/EE/10253-66
-1010
-1100
-1110
ADJSP
JSR
CASE
FormatS
EXT
CVTP
INS
CHECK
MOVSU
MOVUS
Z
.......
.
o
C\I
C\I
SI7
15
Cf)
o
I
i
I
-000
INDEX
FFS
-001
-010
-011
-110, reg = 001
-110,reg = 011
-100
-1 01
op
><
CJ
C\I
Cf)
Format 4
t/)
Z
ADD
CMP
BIC
ADDC
MOV
OR
-0000
-0001
-0010
-0100
-0101
-0110
-1000
-1001
-1010
-1100
-1101
-1110
SUB
ADDR
AND
SUBC
TBIT
XOR
Format 9
MOVif
LFSR
MOVLF
MOVFL
-000
-001
-010
-011
ROUND
TRUNC
SFSR
FLOOR
-100
-101
-110
-111
7
0
---I
I I I I I I I 1
___ 0 1 1 1 1 1 1 0
Format 5
MOVS
-0000
-0001
CMPS
Trap (UNO) on 1XXX, 01XX
TL/EE/10253-67
SETCFG
SKPS
Format 10
-0010
-0011
Trap (UNO) Always
o
1 1 1 1 0
Format 11
Format 6
ROT
ASH
CBIT
CBITI
Trap (UNO)
LSH
SBIT
SBITI
-0000
-0001
-0010
-0011
-0100
-0101
-0110
-0111
NEG
NOT
Trap (UNO)
SUBP
ABS
COM
IBIT
ADDP
S7
i
ADDf
MOVf
CMPf
Note 3
SUBf
NEGf
Note 2
Note 1
-1000
-1001
-1010
-1011
-1100
-1101
-1110
-1111
o
1 100 1 1 1 0
Format 7
MOVM
CMPM
INSS
EXTS
MOVXBW
MOVZBW
MOVZiD
MOVXiD
-0000
-0001
-0010
-0011
-0100
-0101
-0110
-0111
MUL
MEl
Trap (UNO)
DEI
QUO
REM
MOD
DIV
-1000
-1001
-1010
-1011
-1100
-1101
-1110
-1111
2-82
-0000
-0001
-0010
-0011
-0100
-0101
-0110
-0111
DIVf
Note 1
Note 3
Note 1
MULf
ABSf
Note 2
Note 1
-1000
-1001
-1010
-1011
-1100
-1101
-1110
-1111
~------------------------------------------------------------------------.
Appendix A: Instruction Formats (Continued)
-0000
-0001
-0010
-0011
-0100
-0101
-0110
-0111
Note 2
Note 1
POLYf
OOTf
SCALBf
LOGBf
Note 2
Note 1
N
CCV3
LCSR
CCV5
CCV4
Note 2
Note 1
Note 3
Note 1
Note 2
Note 1
Note 2
Note 1
-1000
-1001
-1010
-1011
-1100
-1101
-1110
-1111
---I
I I I I I I I
-000
-001
-010
-011
CCV2
CCV1
SCSR
CCVO
-100
-101
-110
-111
~
U1
......
z
Format 15.5
1
Trap (UNO) Always
CCALO
CMOVO
CCMPO
CCMP1
CCAL1
CMOV2
Note 2
Note 1
-0000
-0001
-0010
-0011
-0100
-0101
-0110
-0111
CCAL3
CMOV3
Note 3
Note 1
CCAL2
CMOV1
Note 2
Note 1
-1000
-1001
-1010
-1011
-1100
-1101
-1110
-1111
23
111
Format 14
gen 1
Format 15.7
CINV -1001
Trap (UNO) on OOXX, 01 XX, 1000, 101 X, 11 XX
Note 2
Note 1
Note 3
Note 3
Note 2
Note 1
Note 2
Note 1
161 15
10 Byte
Format 15
-0000
-0001
-0010
-0011
-0100
-0101
-0110
-0111
-1000
-1001
-1010
-1011
-1100
-1101
-1110
-1111
Note 2
Note 1
Note 3
Note 1
Note 2
Note 1
Note 2
Note 1
If nnn = 010,011,100,110 then Trap (UND) Always.
(Custom Slave)
Operation Word Format
7
---I
0
I I I I II I
___ 0 1 0 1 1 1 1 0
23
1
TL/EE/10253-69
000
gen 1
Format 16
Trap (UNO) Always
Format 15.0
LCR
SCR
Z
rn
w
><
w
101
TL/EE/10253-68
nnn
.
N
N
o
......
C)
Format 13
Operation Word
><
W
N
7
___ 1 0 0 1 1 1 1 0
rn
w
C)
Format 15.1
Format 12
z
-0010
-0011
7
---I
0
I I I I I I I
___ 1 1 0 1 1 1 1 0
1
TL/EE/l0253-70
Trap (UNO) on all others
Format 17
Trap (UNO) Always
001
7
0
---I
I I I I I I I 1
___ 1 0 0 0 1 1 1 0
TLlEE/10253-71
2-83
rn
w
N
C)
><
w
~
w
o
o
('f)
•
><
CJ
N
('f)
Appendix A: Instruction
Formats (Continued)
N
Format 18
('f)
U)
Z
......
it)
Trap (UND) Always
7
0
---I xI xI xI 0 I 0 I 1 I 1 I 0 1
___
·
N
N
('f)
><
TL/EE/10253-72
CJ
N
('f)
U)
Z
......
o
N
N
•
><
CJ
Format 19
Trap (UND) Always
Implied Immediate Encodlngs:
o
7
('f)
r1
N
U)
Z
5. The program does not modify itself. Refer to Section 8.4
for more information.
6.. The program does not depend on the execution of certain complex instructions to be non-interruptible. Refer
to Section 8.5 on. "Memory-Mapped 1/0" for more information.
7. The program does not use the custom slave instructions
CATSTO and CATST1, as they are not supported by the
NS32GX32 and will result in a Trap (UND) when their
execution is attempted.
rO
Register Mark, Appended to SAVE, ENTER
('f)
o
7
Register Mark, Appended to RESTORE, EXIT
o
7
: offset :
be reserved or undefined. For example, if the count operand's value for an LSHi instruction is not within the
range specified by the Series 32000 Instruction Set Reference Manual, then the results produced by the
NS32GX32 may differ from those of the NS32032.
3. The program does not depend on the use of a Memory
Management Unit (MMU).
4. The program does not depend on the detection of bus
errors according to the implementation of the NS32332.
For example, the NS32GX32 distinguishes between re~
startable and nonrestartable bus errors by transferring
control to the appropriate bus-error exception service
procedure through one of two distinct entries in the Interrupt Dispatch Table. In contrast, the NS32332 uses a
single entry in the Interrupt Dispatch Table for all bus
errors.
leng;h - 1
B.2 ARCHITECTURE EXTENSIONS
The NS32GX32 implements the following extensions of the
Series 32000 architecture using previously reserved control
bits, instruction encodings, and memory locations. Extensions implemented earlier in the NS32332, such as 32-bit
addressing, are not listed.
1. The DC, LDC, IC, and LlC bits in the CFG register have
been defined to control the on-chip Instruction and Data
Caches. The DE-bit in the CFG register has been defined to enable Direct-Exception Mode.
2. The V-flag in the PSR register has been defined to enable the Integer-Overflow Trap.
3. The DCR, 8PC, DSR, and CAR registers have been defined to control debugging features. Access to these
registers has been added to the definition of the LPR
and SPR instructions.
4. Access to the CFG and SP1 registers has been added
to the definition of the LPR and SPR instructions.
Offset/Length Modifier Appended to INSS, EXTS
Note 1: Opcode not defined; CPU treats like MOV, or CMOVc. First operand
has access class of read; second operand has access class of write; f or c
field selects 32- or 64-bit data.
Note 2: Opcode not defined; CPU treats like ADD, or CCALc. First operand
has access class of read;, second operand has access class of read-modifywrite; f or c field selects 32- or 64-bit data.
Note 3: Opcode not defined; CPU treats like CMP, or CCMPc. First operand
has access class of read;, second operand has access class of read; f or c
field selects 32- or 64-bit data.
Appendix B. Compatibility Issues
The NS32GX32 is compatible with the Series 32000 architecture implemented by the NS32532, NS32032, NS32332,
and previous microprocessors in the family. Compatibility
means that within certain limited constraints, programs that
execute on one of the earlier Series 32000 microprocessors
will produce identical results when executed on the
NS32GX32. Compatibility applies to privileged operating
systems programs, as well as to non-privileged applications
programs. This appendix explains both the restrictions on
compatibility with previous Series 32000 microprocessors
and the extensions to the architecture that are implemented
by the NS32GX32.
5. The CINV instruction has been defined to invalidate
control of the on-chip Instruction and Data Caches.
6. Direct-Exception Mode has been added to support faster interrupt service time and systems without module
tables.
7. A new entry has been added to the Interrupt Dispatch
Table for supporting vectors to distinguish between restartable and nonrestartable bus errors. Two additional
entries support Trap (OVF) and Trap (D8G).
B.1 RESTRICTIONS ON COMPATIBILITY
If the following restrictions are observed, then a program
that executes on an earlier Series 32000 microprocessor
will produce identical results when executed on the
NS32GX32 in an appropriately configured system:
B.3 INTEGER OVERFLOW TRAP
A new trap condition is recognized for integer arithmetic
overflow. Trap (OVF) is enabled by the V-flag in the PSR.
This new trap is important because detection of integer
overflow conditions is required for certain programming languages, such as ADA, and the PSR flags do not indicate the
occurrence of overflow for ASHi, DIVi and MULi instructions.
1. The program is not time-dependent. For example, the
program should not use instruction loops to control realtime delays.
2. The program does not use any encodings of instructions, operands, addresses, or control fields identified to
2-84
z
en
w
Appendix B. Compatibility Issues (Continued)
More details on integer overflow are given in Section 3.2.5,
where a description of all the cases in which an overflow
condition is detected is also provided.
INTEGER ARITHMETIC
8.5 MEMORY-MAPPED 1/0
As was mentioned in Section 3.1.3.2, certain peripheral devices exhibit characteristics identified as "destructive-reading" and "side-effects of writing" that impose requirements
for special handling of memory-mapped I/O references.
The NS32GX32 supports two methods to use on references
to memory-mapped peripheral devices that exhibit either or
both of these characteristics.
For peripheral devices that exhibit only side-effects of writing, correct operation can be ensured either by locating the
device between addresses FFOOOOOO (hex) and FF7FFFFF
(hex) in the address space or by observing the first 2 restrictions listed below. For peripheral devices that exhibit destructive-reading, all the following restrictions must be observed to ensure correct operation:
1. References to the device must be inhibited while the
CPU asserts the output signal IOINH.
2. The input signal IODEC must be asserted by the system
on references to the device.
3. The device cannot be used for instruction fetches, reads
of effective addresses.
4. If an instruction that reads a source operand from the
device crosses a page boundary, then no Trap (ABT) or
restartable bus error can occur during fetches from the
page with higher addresses.
5. The device can be used as a source operand only for
instructions in the list below.
ABSi
CBITi
MOVMi
SBITIi
SUBi
CBITIi
MOVXi
ADDi
MOVZi
SUBCi
ADDCi
CMPi
CMPQi
NEGi
SUBPi
ADDPi
NOTi
TBITi
ADDQi
COMi
ORi
XORi
ANDi
IBITi
ROTi
LSHi
ASHi
SBITi
BICi
MOVi
This restriction arises because the CPU can respond to
interrupt requests during the execution of complex instruction in order to reduce interrupt latency. Thus, the
CPU may read the source operands for a DEID instruction (extended-precision divide), begin calculating the instruction's results, and then respond to an interrupt request before completing the instruction. In such an
event, the instruction can be executed again and completed correctly after the interrupt service procedure returns unless one of the source operands was altered by
destructive-reading.
The V-flag in the PSR enables Trap (OVF) to occur following
execution of an integer arithmetic instruction whose result
cannot be represented exactly in the destination operand's
location.
If the number of bits required to represent the resulting quotient of a DEI instruction exceeds half the number of bits of
the destination, then the contents of both the quotient and
remainder stored in the destination are undefined.
The ADDR instruction can be used in place of integer arithmetic instructions to perform certain calculations. In this
case however, integer overflow is not detected by the CPU.
LOGICAL INSTRUCTIONS
The V-flag in the PSR enables Trap (OVF) to occur following
execution of an ASHi instruction whose result cannot be
represented exactly in the destination operand's location.
ARRAY INSTRUCTIONS
The V-flag in the PSR enables Trap (OVF) to occur following
execution of a CHECKi instruction whose source operand is
out of bounds.
PROCESSOR CONTROL INSTRUCTIONS
The V-flag in the PSR enables Trap (OVF) to occur following
execution of an ACBi instruction if the sum of the "inc" value and the "index" operand cannot be represented exactly
in the "index" operand's location.
8.4 SELF-MODIFYING CODE
The Series 32000 architecture does not have special provisions to optimally support self-modifying programs.
Nevertheless, on the NS32332 and previous Series 32000
microprocessors it is possible to execute self-modifying
code according to the following sequence:
1. Modify the appropriate instruction.
2. Execute a JUMP instruction or other instruction that
causes the microprocessor's instruction queue to be
flushed.
3. Execute the modified instruction.
For example, an interactive debugger may follow the sequence above after reaching a breakpoint in a program being monitored.
The same program may not produce identical results when
executed on the NS32GX32 due to effects of the Instruction
Cache and branch prediction. In order to execute self-modifying code on the NS32GX32 it is necessary to do the following:
1. Modify the appropriate instruction.
2. If the modified instruction is on a cacheable page, execute CINV to invalidate the contents of the Instruction
Cache.
3. Execute an instruction that causes a serializing operation. See Section 3.1.3.3.
4. Execute the modified instruction.
Appendix C. Instruction Set
Extensions
The following sections describe the differences and extensions to the Series 32000 instruction set (as presented in the "Series 32000 Instruction Set Reference Manual") implemented by the NS32GX32.
No changes or additions have been made to the usermode instruction set, and only a few privileged instructions have been added.
2-85
N
G)
><
W
N
N
·
o
........
Z
en
w
N
G)
><
W
N
N•
en
........
Z
en
w
N
G)
><
W
N
•
W
o
Appendix C.lnstruction Set Extensions
C.1 PROCESSOR SERVICE INSTRUCTIONS
The CFG register, User Stack Pointer (SP1), and Debug
Registers can be loaded and stored using privileged forms
of the LPRi and SPRi instructions.
When the SETCFG instruction is executed, the CFG register
bits 0 through 3 are loaded from the instruction's short field,
bits 4 through 7 are forced to 1, and bits S through 12 are
forced to O.
TABLE C-1. LPRi/SPRi New 'Short' Field Encodings
The LPRi and SPRi instructions can be used to load and
store the User Stack Pointer (USP or SP1), the Configuration Register (CFG) and the Debug Registers in addition to
the Processor Registers supported by the previous Series
32000 CPUs. Access to these registers is privileged.
Figure C-t and Table C-1 show the instruction formats and
the new 'short' field encodings for LPRi and SPRi.
Flags Affected: No flags affected by loading or storing the
USP, CFG, or Debug Registers.
Illegal Instruction Trap (ILL) occurs if an
attempt is made to load or store the USP,
CFG or Debug Registers while the U-flag
is 1.
s
I
I
src
11~
I
, 17
I I I I I
short 1. 1 1 0 1 1.
I
procreg
S
I
I
gen
I
,
17
I short
0001
Breakpoint Program Counter
BPC
0010
Debug Status Register
DSR
0011
Compare Address Register
CAR
0100
User Stack Pointer
USP
1011
Configuration Register
CFG
1100
options, src
gen
read. D
The CINV instruction invalidates the contents of locations in
the on-chip Instruction Cache and Data Cache. The instruction can be used to invalidate either the entire contents of
the on-chip caches or only a 16-byte block. In the latter
case, the 2S most-significant bits of the source operand
specify the physical address of the aligned 16-byte block;
the 4 least-significant bits of the source operand are ignored. If the specified block is not located in the on-chip
caches, then the instruction has no effect. If the entire
cache contents is to be invalidated, then the source operand is read, but its value is ignored.
Options are specified by listing the letters A (invalidate All), I
(Instruction Cache), and D (Data Cache). If neither the I nor
D option is specified, the instruction has no effect.
In the instruction encoding, the options are represented in
the A, I, and D fields as follows:
A: O-invalidate only a 16-byte block
1-invalidate the entire cache
I: O-do not affect the Instruction Cache
1-invalidate the Instruction Cache
D: O-do not affect the Data Cache
1-invalidate the Data Cache
Flags Affected: None
Illegal Operation Trap (ILL) occurs if an atTraps:
tempt is made to execute this instruction
while the U-flag is 1.
Examples:
1. CINV A, D, I, R3 1E A7 1B
2. CINV I, R3
1E 2719
Example 1 invalidates the entire Instruction Cache and Data
Cache.
Example 2 invalidates the 16-byte block whose physical address in the Instruction Cache is contained in R3.
Load and Store Processor Registers
procreg,
src
Syntax: LPRI
short
gen
read.i
SPRI
procreg
dest
short
gen
write.i
gen
short field
DCR
Cache Invalidate
Syntax: CINV
C.2 INSTRUCTION DEFINITIONS
This section provides a description of the operations and
encodings of the new NS32GX32 privileged instructions.
11~
procreg
Debug Condition Register
Register
The contents of the on-chip Instruction Cache and Data
Cache can be invalidated by executing the privileged instruction CINV. While executing the CINV instruction, the
CPU generates 2 slave bus cycles on the system interface
to display the first 3 bytes of the instruction and the source
operand.
Traps:
(Continued)
:°1
LPRi
I I I I I
:01
1. 0 1 0 1 1.
dest
procreg
SPRi
FIGURE C-1. LPRIISPRllnstruction Formats
2-S6
z
3. Cache misses can cause the flow of instructions through
the pipeline to be delayed, as can non-aligned references. Section 0.4 explains the performance impact for
these forms of storage delays.
Appendix C. Instruction Set
Extensions (Continued)
123'~e~'
src
115
aj7
°1
10iAII 010'1'0'0'1'1'1 0'0'0'1'1'1'1'0
The effective time Teft needed to execute an Instruction is
given by the following formula:
options
CINV
FIGURE C-2. CINV Instruction Format
Telf = T e + Td + T s
Te is the execution time in the pipeline in the absence of
data dependencies between instructions and storage delays, Td is the delay due to data dependencies, and T 5 is the
effect of storage delays.
Appendix D. Instruction
Execution Times
0.2 BASIC EXECUTION TIMES
Instruction flow in sequence through the pipeline stages implemented by the Loader, Address Unit, and Execution Unit.
In almost all cases, the Loader is at least as fast at decoding an instruction as the Address Unit is at processing the
instruction. Consequently, the effects of the Loader can be
ignored when analyzing the smooth flow of instructions in
the pipeline, and it is only necessary to consider the times
for the Address Unit and Execution Unit. The time required
by the Loader to fetch and decode instructions is significant
only when there are control dependencies between instructions or Instruction Cache misses, both of which are explained later.
The time for the pipeline to advance from one instruction to
the next is typically determined by the maximum time of the
Address Unit and Execution Unit to complete processing of
the instruction on which they are operating. For example, if
the Execution Unit is completing instruction n in 2 cycles
and the Address Unit is completing instruction n+ 1 in 4
cycles, then the pipeline will advance in 4 cycles. For certain
instructions, such as RESTORE, the Address Unit waits until
the Execution Unit has completed the instruction before
proceeding to the next instruction. When such an instruction
is in the Execution Unit, the time for the pipeline to advance
is equal to the sum of the time for the Execution Unit to
complete instruction n and the time for the Address Unit to
complete instruction n+ 1. The processing times for the
Loader, Address Unit, and Execution Unit are explained below.
The NS32GX32 achieves its performance by using an advanced implementation incorporating a 4-stage Instruction
Pipeline, an Instruction Cache and a Data Cache into a single integrated circuit.
As a consequence of this advanced implementation, the
performance evaluation for the NS32GX32 is more complex
than for the previous microprocessors in the Series 32000
family. In fact, it is no longer possible to determine the execution time for an instruction using only a set of tables for
operations and addressing modes. Rather, it is necessary to
consider dependencies between the various instructions executing in the pipeline, as well as the occurrence of misses
for the on-Chip caches.
The following sections explain the method to evaluate the
performance of the NS32GX32 by calculating various timing
parameters for an instruction sequence. Due to the high
degree of parallelism in the NS32GX32, the evaluation techniques presented here include some simplifications and approximations.
0.1 INTERNAL ORGANIZATION
AND INSTRUCTION EXECUTION
The NS32GX32 is organized internally as a functional units
as shown in Figure 1. The functional units operate in parallel
to execute instructions in the 4-stage pipeline. The structure
of this pipeline is shown in Figure 3-2. The Instruction Fetch
and Instruction Decode pipeline stages are implemented in
the loader along with the a-byte instruction queue and the
buffer for a decoded instruction. The Address Calculation
pipeline stage is implemented in the address unit. The Execute pipeline stage is implemented in the Execution Unit
along with the write data buffer that holds up to two results
directed to memory.
0.2.1 Loader Timing
The Loader can process an instruction field on each clock
cycle, where a field is one of the following:
• An opcode of 1 to 3 bytes including addressing mode
specifiers.
The Address Unit and Execution Unit can process instructions at a peak rate of 2 clock cycles per instruction, enabling a sustained pipeline throughput at 30 MHz of
15 MIPS (million instructions per second) for sequences of
register-to-register, immediate-to-register, memory-to-register instructions and register-to-memory. Nevertheless, the
execution of instructions in the pipeline is reduced from the
peak throughput of 2 cycles by the following causes of delay:
• Up to 2 index bytes, if scaled index addressing mode is
used.
• A displacement.
• An immediate value of 8, 16 or 32 bits.
The Loader requires additional time in the following cases:
• 1 additional cycle when 2 consecutive double-word fields
begin at an odd address.
1. Complex operations, like division, require more than 2 cycles in the Execution Unit, and complex addressing
modes, like memory relative, require more than 2 cycles
in the Address Unit.
• 2 cycles in total to process a double-precision floatingpoint immediate value.
2. Dependencies between instructions can limit the flow
through the pipeline. A data dependency can arise when
the result of one instruction is the source of a following
instruction. Control dependencies arise when branching
instructions are executed. Section 0.3 describes the
types of instruction dependencies that impact performance and explains how to calculate the pipeline delays.
2-87
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en
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Appendix D. Instruction Execution Times (Continued)
The delay is 1 cycle when the register is modified 2 instructions before its use as a base register, as shown in this
example .
n: ADDD Rl,RO
n+l: MOVD 4(SP),R:5
n+2: MOVD 4(RO),R2
For instructions with 2 general addressing modes, 2 additional cycles are required when both addressing modes refer to memory. Certain general addressing modes require an
additional processing time, as shown in Table 0-1. For example, the instruction MOVD 4(8(FP», TOS requires 7 cycles in the Address Unit; 2 cycles for the basic time, an
additional 2 cycles because both modes refer to memory,
and an additional 3 cycles for Memory Relative addressing
mode.
n: ADDD Rl.RO
; modify RO
n+l: MOVD 4 (SP)[RO :B] .R2
; RO is index register
delay 1 cycle
TABLE D-1. Additional Address Unit Processing
Time for Complex Addressing Modes
Memory Relative
External
Scaled Indexing
modify RO
RO not used
RO is base register,
delay 1 cycle
When an instruction uses an index register that is the destination of the previous instruction, a delay of 1 cycle occurs,
as shown in the example below. If the register is modified 2
or more instructions prior to its use as an index register,
then no delay occurs.
Z
Mode
modify RO
RO is base register,
delay :5 cycles
n: ADDD Rl.RO
n+l: MOVD 4(RO).R2
D.2.2 Address Unit Timing
The processing time of the Address Unit depends on the
instruction's operation and the number and type of its general addressing modes. The basic time for most instructions
is 2 cycles. A relatively small number of instructions require
an additional address unit time, as shown in the timing tables in Section 0.5.5. Floating-point instructions as well as
Custom-Slave instructions require an additional 3 cycles
plus 2 cycles for each quad-word operand in memory.
Additional
Cycles
Bypass circuitry in the Execution Unit generally avoids delay
when a register modified by one instruction is used as the
source operand of the following instruction, as in the following example.
3
8
n: ADDD Rl.RO
n+l: MOVD RO.R2
2
modify RO
RO is source register.
no delay
D.2.3 Execution Unit Timing
The Execution Unit processing times for the various
NS32GX32 instructions are provided in Section 0.5.5. Certain operations cause a break in the instruction flow through
the pipeline.
Some of these operation simply stop the Address Unit,
while others flush the instruction queue as well. The information on how to evaluate the penalty resulting from instruction flow breaks is provided in the following sections.
For the uncommon case where the operand in the source
register is larger than the destination of the previous instruction, a delay of 2 cycles occurs. Here is an example.
n: ADDB Rl.RO
n+l: MOVD RO.R2
modify byte in RO
; RO dw Source operand.
2 cycle delay
Note: The Address Unit does not make any differentiation between CPU
and FPU registers. Therefore, register interlocks can occur between
integer and floating-point Instructions.
D.3 INSTRUCTION DEPENDENCIES
Interactions between instructions in the pipeline can cause
delays. Two types of interactions can arise, as described
below.
D.3.1.2 Memory Interlocks
When an instruction reads a source operand (or address for
effective address calculation) from memory that depends on
the destination of either of the previous 2 instructions, a
delay occurs. The CPU detects a dependency between a
read and a write reference in the following cases, which
include some false dependencies in addition to all actual
dependencies:
D.3.1 Data Dependencies
In certain circumstances the flow of instructions in the pipeline will be delayed when the result of an instruction is used
as the source of a succeeding instruction. Such interlocks
are automatically detected by the microprocessor and handled with complete transparency to software.
• Either reference crosses a double-word boundary
• Address bits 0 through 11 are equal
D.3.1.1 Register Interlocks
• Address bits 2 through 11 are equal and either reference
is for a word
When an instruction uses a base register that is the destination of either of the previous 2 instructions, a delay occurs.
Modifications of the Stack Pointer resulting from the use of
TOS addressing mode do not cause any delay. Also, there
is no delay for a data dependency when the instruction that
modifies the register is one for which the Address Unit
stops. The delay is 3 cycles when, as in the following example, the base register is modified by the immediately preceding instruction.
• Address bits 2 through 11 are equal and either reference
is for a double-word
The delay for a memeory interlock is 4 cycles when, as in
the following example, the memory location is modified by
the immediately preceding instruction.
n: ADDQD 1.4(SP)
modify 4(SP)
n+1: CMPD 10.4(SP) ; read. 4(SP).
4 cycle delay
2-88
z
Appendix D.lnstruction Execution Times (Continued)
0.4 STORAGE DELA VS
The flow of instructions in the pipeline can be delayed by
off-Chip memory references that result from misses in the
on-chip storage buffers and by misalignment of instructions
and operands. These considerations are explained in the
following sections. The delays reported assume no wait
states on the external bus and no interference between instruction and data references.
The delay is 2 cycles when the memory location is modified
2 instructions before its use as a source operand or effective address, as shown in this example.
n: ADDQD l,4(SP) ; modify 4(SP)
n+l: MOVD RO,Rl
no reference to 4(SP)
n+2: CMPD 10, 4(SP); read 4(SP),
2 cycles delay
Certain sequences of read and write references can cause
a delay of 1 cycle although there is no data dependency
between the references. This arises because the Data
Cache is occupied for 2 cycles on write references. In the
absence of data dependencies, read references are given
priority over write references. Therefore, this delay only occurs when an instruction with destination in memory is followed 2 instructions later by an instruction that refers to
memory (read or write) and 3 instructions later by an instruction that reads from memory. Here is an example:
n: MOVD RO,4(SP)
memory write
n+l: MOVD R6,R7
any instruction
n+2: MOVD 8(SP),RO
memory read or write
n+3: MOVD 12(SP),Rl; memory read
delayed 1 cycle
0.4.1 Instruction Cache Misses
An Instruction Cache miss causes a 5 cycle gap in the fetching of instructions. When the miss occurs for a non-sequential instruction fetch, the pipeline is idle for the entire gap, so
the delay is 5 cycles. When the miss occurs for a sequential
fetch, the pipeline is not idle for the entire gap because
instructions that have been prefetched ahead and buffered
can be executed. The delay for misses on non-sequential
instruction fetches can be estimated to be approximately
half the gap, or 2.5 cycles.
0.4.2 Data Cache Misses
A Data Cache miss causes a delay of 2 cycles. When a
burst read cycle is used to fill the cache block, then 3 additional cycles are required to update the Data Cache. In case
a burst cycle is used and either of the 2 instructions following the instruction that caused the miss also reads from
memory, then an additional delay occurs: 3 cycle delay
when the instruction that reads from memory immediately
follows the miss, and 2 cycle delay when the memory read
occurs 2 instructions after the miss.
0_3.2 Control Dependencies
The flow of instructions through the pipeline is delayed
when the address from which to fetch an instruction depends on a previous instruction, such as when a conditional
branch is excuted. The Loader includes special circuitry to
handle branch instructions (ACB, BR, Bcond, and BSR) that
serves to reduce such delays. When a branch instruction is
decoded, the Loader calculates the destination address and
selects between the sequential and non-sequential instruction streams. The non-sequential stream is selected for unconditional branches. For conditional branches the selection is based on the branch's direction (forward or backward) as well as the tested condition. The branch is predicted taken in any of the following cases.
0.4.3 Instruction and Operand Alignment
When a data reference (either read or write) crosses a double-word boundary, there is a delay of 2 cycles.
When the opcode for a non-sequential instruction crosses a
double-word boundary, there is a delay of 1 cycle. No delay
occurs in the same situation for a sequential instruction.
There is also a delay of 2 cycles when an instruction fetch is
located on a different page from the previous fetch and
there is a hit in the Instruction Cache. This delay, which is
due to the time required to translate the new page's address, also occurs following any serializing operation.
• The branch is backward.
• The tested condition is either NE or LE.
Measurements have shown that the correct stream is selected for 64% of conditional branches and 71 % of total
branches.
If the Loader selects the non-sequential stream, then the
destination address is transferred to the Instruction Cache.
For conditional branches, the Loader saves the address of
the alternate stream (the one not selected). When a conditional branch instruction reaches the Execution Unit, the
condition is resolved, and the Execution Unit signals the
Loader whether or not the branch was taken. If the branch
had been incorrectly predicted, the Instruction Cache begins fetching instructions from the correct stream.
The delay for handling a branch instruction depends on
whether the branch is taken and whether it is predicted correctly. Unconditional branches have the same delay as correctly predicted, taken conditional branches.
Another form of delay occurs when 2 consecutive conditional branch instructions are executed. This delay of 2 cycles
arises from contention for the register that holds the alternate stream address in the Loader.
Control dependencies also arise when JUMP, RET, and other non-branch instructions alter the sequential execution of
instructions.
0.5 EXECUTION TIME CALCULATIONS
This section provides the necessary information to calculate
the Te portion of the effective time required by the CPU to
execute an instruction.
The effects of data dependencies and storage delays are
not taken into account in the evaluation of Te, rather, they
should be separately evaluated through a careful examination of the instruction sequence.
The following assumptions are made:
- The entire instruction, with displacements and immediate operands, is present in the instruction queue when
needed.
- All memory operands are available to the Execution Unit
and Address Unit when needed.
- Memory writes are performed at full speed through the
write buffer.
- Where possible, the values of operands are taken into
consideration when they affect instruction timing, and a
range of times is given. When this is not done, the worst
case is assumed.
2-89
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Appendix D.
Instru~tion
Execution Times
D.5.1 Definitions
Teu
Time required by the Execution Unit to execute an
instruction.
Tau
Total processing time in the Address Unit.
Tad
Extra time needed by the Address Unit, in addition
to the basic time, to process more complex cases.
Tad can be evaluated as follows:
N
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Z
.......
C)
N
N
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Ty1 and Ty2 are related to operands 1 and 2 respectively. Their values are given below.
"
Ty(1, 2) = 3 if Memory Relative
8 if External
2 if Scaled Indexing
o if any other addressing mode
The following parameters are only used for floating-point
execution time calculations.
><
N
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U)
Z
Memory, except Top of Stack
Top of Stack
Any addressing mode
a and b represent the addressing modes of operands 1 and 2 respectively. Both of them can be
any addressing mode. (e.g., means
memory to CPU register).
3. The notation 'Break K' provides pipeline status information after executing the instruction to which 'Break K' applies. The value of K is interpreted as follows:
K = 0 The Address Unit was stopped by the instruction
but the pipeline was not flushed. The Address
Unit can start processing the next instruction immediately.
K > 0 The pipeline was flushed by the instruction. The
Address Unit must wait for K cycles before it can
start processing the next instruction.
K < 0 The Address Unit was stopped at the beginning
of the Instruction but it was restarted IKI cycles
before the end of it. The Address Unit can start
processing the next Instruction IKI cycles before
the end of the instruction to which 'Break K' applies.
4. Some instructions must wait for pending writes to complete before being able to execute. The number of cycles
that these instructions must wait for, is between 6 and 7
for the first operand in the write buffer and 2 for the second operand, if any.
5. The CBITIi and SBITIi instructions will execute a RMW
access after waiting for pending writes. The extra time
required for the RMW access is only 3 cycles since the
read portion is overlapped with the time in the Execution
Unit.
6. The keyword defined for the Bcond instruction have the
following meaning:
BTPC Branch Taken, Predicted Correctly
BTPI
Branch Taken, Predicted Incorrectly
BNTPC Branch Not Taken, Predicted Correctly
BNTPI Branch Not Taken, Predicted Incorrectly
Tad = Tx + Ty1 + Ty2
Tx = 2 if the instruction has two general operands
and both of them are in memory.
o otherwise.
"
Tanp
Additional Address Unit time needed to process
floating-point instructions (Section 0.2.2). Tanp can
be calculated as follows:
Tanp = 3
Ttcs
Ttsc
+ 2 • (Number of 64-bit operands in
memory)
Time required to transfer 10 and Opcode, if no operand needs to be transferred to the slave. Otherwise, it is the time needed to transfer the last 32
bits of operand data to the slave. In the latter case
the transfer of 10 and Opcode as well as any operand data except the last 32 bits is included in the
Execution Unit timing.
Time required by the CPU to complete the floatingpoint instruction upon receiving the DONE signal
from the slave. This includes the time to process
the DONE signal itself in addition to the time needed to read the result (if any) from the slave.
This parameter is related to the floating-point operand size as follows:
Standard floating (32 bits): I = 0
Long floating (64 bits):
I = 1
D.5.2 Notes on Table Use
1. In the Teu column the notation n1
mum, n2 maximum.
~
D.5.3 Teff Evaluation
The Te portion of the effective execution time for a certain
instruction in an instruction sequence is obtained by performing the following steps:
1. Label the current and previous instruction in the sequence with nand n-1 respectively.
n2 means n1 mini-
2. In the notes column, notations held within angle brackets
< > indicate alternatives in the operand addressing
modes which affect the execution time. A table entry
which is affected by the operand addressing may have
multiple values, corresponding to the alternatives. This
addressing notations are:
< I>
< R>
Immediate
CPU register
Memory
FPU register, either 32 or 64 bits
(Continued)
2. Obtain from the tables the values of Teu and Tau for instruction nand Teu for instruction n -1.
3. For floating-point instructions, obtain the values of Ttcs
and Ttsc.
4. Use the following formula to determine the execution time
Te·
Te = func (Tau(n), Teu(n -1), TfIt(n -1),
Break (n-1» + Teu(n) + TfIt(n)
2-90
z
(J)
w
Appendix D. Instruction Execution Times (Continued)
func provides the amount of processing time in the Address
Unit that cannot be hidden. Its definition is given below.
o
if Tau(n) ~ (Teu (n-1) + Tfit (n-1))
AND NOT Break (n -1)
Tau(n) - Teu (n-1)
if Tau(n) > (Teu(n-1) + TfIt(n-1))
AND NOT Break (n -1)
Tau(n)
+
0.5.4 Instruction Timing Example
This section presents a simple instruction timing example
for a procedure that recursively evaluates the Fibonacci
function. In this example there are no data dependencies or
storage buffer misses; only the basic instruction execution
times in the pipeline, control dependencies, and instruction
alignment are considered.
if (Tau(n) + K) > 0
AND Break (n-1)
K
I\)
The following is the source of the procedure in C.
if (Tau(n) + K) ~ 0
AND Break (n-1)
K is the value associated with Break (n -1).
+
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.
Z
i f (x
>
(J)
2)
w
return (fib(x-l) + fib(x-2»;
G')
return(l) ;
I\)
><
w
~
w
o
The assembly code for the procedure with comments indicating the execution time is shown below. The procedure
requires 26 cycles to execute when the actual parameter is
less than or equal to 2 (branch taken) and 99 cycles when
the actual parameter is equal to 3 (recursive calls).
5. Calculate the total execution time T eft by using the following formula:
Teft = Te + T d + Ts
Where Td and T s are dependent on the instruction sequence, and can be obtained using the information provided in Section 0.4.
_Ll:
I\)
I\)
(
Tfpu
movd
r3,tos
movd
r4,tos
movd
rl,r3
cmpqd
$(2) ,r3
bge
.Ll
movd
r3,rl
addqd
$(-2),rl
_fib
bsr
movd
rO,r4
movd
r3,rl
addqd
$(-1) ,rl
_fib
bsr
addd
r4,rO
movd
tos,r4
movd
tos,r3
ret
$(0)
• align 4
movqd
$(1) ,rO
movd
tos,r4
movd
tos,r3
ret
$(0)
w
......
Tfpu is the execution time in the Floating-Point Unit.
_fib:
Z
(J)
U1
else
Ttsc
o
......
I\)
unsigned fib(x)
int
X;
Tfit only applies to floating-point instructions and is always 0 for other instructions. It is evaluated as follows:
+
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•
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o
Tfit = ttcs
G')
2
2
2
2
2
2
2
3
2
2
2
3
2
2
2
4
cycles
cycles
cycles
cycles
cycles, Break 2 If Branch Taken
cycles
cycles
cycles
cycles + 4 Cycles due to RET
cycles
cycles
cycles
cycles + 1 cycle alignment + 4 cycles due to RET
cycles
cycles
cycles, break 4
4
2
2
4
cycles + 4 cycles due to BGE
cycles
cycles
cycles, Break 4
2-91
C) r---------------------------------------------------------------------------------------~
Cf)
•
><
CJ
N
Appendix D. Instruction Execution Times (Continued)
N
0.5.5 Execution Timing Tables
The following tables provide the execution timing information for all the NS32GX32 instructions. The table for the floating-point
instructions provides only the CPU portion of the total execution time. The FPU execution times can be found in the NS32381
datasheet.
Cf)
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0.5.5.1 Basic Instructions
Mnemonic
Teu
ABSi
5
2 + Tad
ACBi
5
2 + Tad
ADDi
2
2 + Tad
ADDCi
2
2 + Tad
ADDPi
9
2 + Tad
ADDQi
2
2 + Tad
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ADDR
ADJSPi
2
5
3
2 + Tad
2 + Tad
2
2 + Tad
ASHi
9
2 + Tad
2~3
2
2
2
2
2
2
2
Mnemonic
Tau
CINV
10
2 + Tad
CMPi
2
2 + Tad
If incorrect prediction
then Break 1
CMPMi
i= B,W
i= D
BTPC
BTPI
BNTPC
BNTPI
(see Note 5 in
Section D.5.2)
Break 0
Break 0
Break 2
Break 2
2
2 + Tad
BICPSRi
6
2 + Tad
Wait for pending writes.
Break 5
BISPSRi
6
2 + Tad
Wait for pending writes.
Break 5
30
21
2
2
BR
2~3
2
BSR
2~3
3 + Tad
2
CMPSi
7 + 13 * n
2 + Tad
n = number
of elements.
Break 0
CMPST
6 + 20 * n
2 + Tad
n = number
of elements.
Break 0
COMi
2
2 + Tad
CVTP
5
4 + Tad
CXP
17
CXPD
21
DIVi
(30
2 + Tad
13
28 + 4 * i
5 + Tad
3
2
~
40) + 4 * i
7
2 + Tad
Break 5
CBITi
10
14
2
2 + Tad
Break 0
CBITIi
18
2 + Tad
Wait for pending writes.
Execute interlocked
RMW access. Break 5
CHECKi
10
2 + Tad
Break 5
11 + Tad Break 5
2 + Tad
i = 0/4/12
for B/W/D.
Break 0
Break 5
i = 0/4/12
for B/W/D
ENTER
15 + 2 * n
3
n = number
of registers
saved.
Break 0
EXIT
8+ 2*n
2
n = number
of registers
restored
EXTi
12
13
8
8 + Tad
EXSi
11
14
6
6 + Tad
FFSi
11+3*i
2 + Tad
i = number
of bytes
Break 5
CASEi
Wait for
pending
writes.
Break 5
n = number
of elements.
Break 0
6+ 8*n
DIA
Modular
Direct
Notes
CMPQi
DEli
BICi
BPT
Teu
4 + Tad
ANDi
BCONO
Notes
Tau
Break -3
Break -3.
If SRC is out of bounds
and the V bit in the PSR
is set, then add trap
time.
Break -3
2-92
~----------------------------------------------------------------------~
Appendix D. Instruction Execution Times
w
(Continued)
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G)
D.5.5.1 Basic Instructions (Continued)
Mnemonic
Teu
Tau
FLAG
4
32
21
2
2
2
IBITi
10
14
INDEXi
43
INSi
15
18
INSSi
14
19
Notes
Mnemonic
No trap
Trap, Modular
Trap, Direct
If trap then:
(wait for
pending writes;
Break5}
2
2 + Tad
If
then Break 0
5 + Tad
8
8 + Tad
6
6 + Tad
JSR
3
9 + Tad Break 5
JUMP
3
4 + Tad Break 5
LPRi
6
2 + Tad CPU Reg = FP,
SP, USP, SP, MOD.
Break 0
2 + Tad CPU Reg = CFG,
INTBASE, DSR,
BPC, UPSR.
Wait for pending
writes.
Break 5
2 + Tad CPU Reg = DCR,
PSR CAR. Wait for
pending writes.
Break 5
7
LSHi
3
MEli
13 + 2 * i
MODi
(34 - . 49) 2 + Tad i = 0/4112
forBIWID
+ 4*i
MOVi
MOVMi
MOVQi
MOVSi
MOVST
2
5 + 4*n
2
Teu
Notes
Tau
MOVSVi
9
2 + Tad Wait for
pending writes.
Break 5
MOVUSi
11
2+ Tad Wait for
pending writes.
Break 5
><
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2
2 + Tad
<11
......
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13 + 2 * i 2 + Tad i = 0/4/12
forB/WID.
General case.
24
2 + Tad If MULDand
o ~ SRC ~ 255
NEGi
2
2 + Tad
NOP
2
2
NOTi
3
2 + Tad
ORi
2
2 + Tad
~
REMi
(32 - . 42) 2 + Tad i = 0/4/12
forB/WID
+ 4*i
n = number
of registers
restored.
Break 0
RET
4
3
Break 4
RETI
19
13
29
22
5
5
5
5
Noncascaded, Modular
Noncascaded, Direct
Cascaded, Modular
Cascaded, Direct
5
5
Modular
Direct
Wait for
pending writes.
Break 5
2 + Tad
2 + Tad n = number
of elements.
Break 0
ROTi
7
RXP
8
2 + Tad
Break 5
5
2 + Tad
SCONDi
3
2 + Tad
SAVE
8 + 2*n
2
SBITi
10
14
><
w
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(30 - . 40) 2 + Tad i = 0/4/12
forB/WID
+ 4*i
14
8
G)
o
QUOi
RETI
2·93
G)
MOVZii
Wait for
pending writes.
Break 5
16 + 9 * n 2 + Tad n = number
of elements.
Break 0
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2 + Tad
2 + Tad
n = number
of elements.
12 + 4 * n 2 + Tad No options.
14 + 8 * n 2 + Tad B, W andlor U
Options in effect.
Break 0
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RESTORE 7+2*n2
5 + Tad i = 0/4/12
forB/W/D.
Break 0
><
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MOVXii
MULi
Break 0
5
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n = number
of registers.
Break 0
2
2 + Tad
Break 0
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r-------------------------------------------------------------------------------,
N Appendix D. Instruction Execution Times (Continued)
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>< D.5.5.1 Basic Instructions (Continued)
"
Mnemonic
Z
SBITIi
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Teu
10
18
Mnemonic
2
2 + Tad
N
><
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Tau
2
2 + Tad
SUBCi
2
2 + Tad
SUBPi
6
2 + Tad
SVC
32
21
2
2
SETCFG
C)
SKPSi
8 + 6· n
2 + Tad n = number of
elements.
Break 0
TBITi
8
11
2
2 + Tad
"
SKPST
6+20·n 2 + Tad n = numberof
elements.
Break 0
WAIT
3
2
Z
SPRi
XORi
2
2 + Tad
.
C'I
C'I
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><
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UJ
5
3
2
Notes
Modular
Direct
Wait for
pending writes.
Break 5
Z
""
6
Teu
SUBi
Wait for pending
writes. Execute
interlocked RMW
access.
Break 5
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Notes
Tau
Break 5
2 + Tad CPU Reg =
PSR,CAR
2 + Tad CPU Reg =
all others
2-94
If < M > then break 0
Wait for pending
writes. Wait
for interrupt
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Appendix D. Instruction Execution Times (Continued)
N
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0.5.5.2 Floating-Point Instructions, CPU Portion
Mnemonic
MOVf,NEGf,
ABSf, lOGBf
Tau
><
Tau
Ttcs
Ttsc
Notes
2
4 + 3 *1
6 + 3 *1
6 + 3 *1
11+4*1
13 + 7 *1
2
2
2
2
2
2
+
+
+
+
+
+
Tanp
Tanp + Tad
Tanp
Tanp
Tanp + Tad
Tanp + Tad
2
2
2
2
2
2
1
1
1
1
3 + 2 *1
3 + 2 *1
Break - (1 + I)
, <1M> Break - (1 + I)
2
4 + 3 *1
6 + 3 *1
6 + 3 *1
17+7*1
19+10*1
2
2
2
2
2
2
+
+
+
+
+
+
Tanp
Tanp
Tanp
Tanp
Tanp + Tad
Tanp + Tad
2
2
2
2
2
2
1
1
1
1
3 + 2 *1
3 + 2 *1
Break - (1 + I)
, <1M> Break - (1 + I)
AOUNDfi, TAUNCfi,
FlOOAfi
11
11 +4*1
13
13 + 7 * I
2 +
2 +
2+
2 +
Tanp
Tanp + Tad
Tanp + Tad
Tanp + Tad
2
2
2
2
3
3
3
3
Break - 1
Break - (1 + I)
, Break -: 1
, <1M> Break - (1 + I)
CMPf
18
20 + 3 *1
23+3*1
25 + 6·1
2 + Tanp
2 + Tanp + Tad
2 + Tanp + Tad
2 + Tanp + Tad
2
2
2
2
POlYt, DOTt
2
4 + 3 *1
6 + 3 *1
11+4*1
13 + 7 * I
2
2
2
2
2
+
+
+
+
+
Tanp
Tanp + Tad
Tanp
Tanp + Tad
Tanp + Tad
2
2
2
2
2
1
1
1
1
1
,
Break - (1 + I)
, , <1M>,
Break - (1 + I)
MOVif
6
13
6 + 3 *1
13 + 7 * I
2
2
2
2
+
+
+
+
Tanp
Tanp + Tad
Tanp + Tad
Tanp + Tad
2
2
2
2
1
1
Break - 1
, ,
, <1M>
Break - (1 + I)
lFSA
6
6 + 3 *1
6 + 3 *1
6 + 3 *1
2
2
2
2
+
+
+
+
Tanp
Tanp + Tad
Tanp
Tanp
2
2
2
2
1
1
1
1
SFSA
11
2 + Tanp + Tad
2
3
Break - 1
MOVFl
4
6
2 + Tanp
2 + Tanp + Tad
2
2
1
1
, ,
15
17
2 + Tanp + Tad
2 + Tanp + Tad
2
2
4
9
2 + Tanp
2 + Tanp + Tad
2
2
15
20
2 + Tanp + Tad
2 + Tanp + Tad
2
2
ADDf,SUBf,
MULt,DIVf,
SCAlBf
MOVlF
2·95
+
+
+
+
2
2
2
2
*1
*1
*1
*1
, <1M>, ,
Break 3
Break 0
, <1M> Break 0
1
1
, ,
Break 0
, <1M> Break 0
.
W
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.-----------------~-------------------------------------------------------------------,
~National
PRELIMINARY
~ Semiconductor
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NS32CG16-10/NS32CG16-15
• High-Performance Printer/Display Processor
CD
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General Description
Features
The NS32CG16 is a 32-bit microprocessor in the Series
32000® family that provides special features for graphics
applications. It is specifically designed to support page oriented printing technologies such as Laser, LCS, LED, lonDeposition and InkJet.
The NS32CG16 provides a 16 Mbyte linear address space
and a 16-bit external data bus. It also has a 32-bit ALU, an
eight-byte prefetch queue, and a slave processor interface.
The capabilities of the NS32CG16 can be expanded by using an external floating point unit which interfaces to the
NS32CG16 as a slave processor. This combination provides optimal support for outline character fonts.
The NS32CG16's highly efficient architecture, in addition to
the built-in capabilities for supporting BITBLT (BIT-aligned
BLock Transfer) operations and other special graphics functions, make the device the ideal choice to handle a variety
of page description languages such as PostscriptTM and
PCLTM.
•
•
•
•
•
•
•
•
•
•
Software compatible with the Series 32000 family
32-bit architecture and implementation
16 Mbyte linear address space
Special support for imaging applications such as printers, faxes and scanners
- 18 graphics instructions
- Binary compression/expansion capability for font
storage using RLL encoding
- Pattern magnification for Epson and HP LaserJet™
emUlations
- 6 BITBLT instructions on chip
- Interface to an external BITBLT processing unit for
very fast BITBLT operations (optional)
Floating point support via the NS32081 or the NS32381
for outline fonts, scaling and rotation
On-chip clock generator
Optimal interface to large memory arrays via the
DP84xx family of DRAM controllers
Power save mode
High-speed CMOS technology
68-pin plastic PCC package
Block Diagram
ADD/DATA
CONTROLS Ie STATUS
REGISTER SET
N AS
WICROCOOE ROW
AND
CONTROL LOGIC
IJ]J]
crG
GRAPHICS
LOGIC
REGISTER
DATA
I
t _______________ •
32 BIT INTERNAL BUS
TL/EE/9424-1
2-96
z
en
1.0 Product Introduction
CAl
N
The NS32CG16 is a high speed CMOS microprocessor in
the Series 32000 family. It is software compatible with all
the other CPUs in the family. The device incorporates all of
the Series 32000 advanced architectural features, with the
exception of the virtual memory capability.
Large, Uniform Addressing. The NS32CG16 has 24-bit
address pointers that can address up to 16 megabytes without any segmentation; this addressing scheme provides
flexible memory management without added-on expense.
Modular Software Support. Any software package for the
Series 32000 family can be developed independent of all
other packages, without regard to individual addressing. In
addition, ROM code is totally relocatable and easy to access, which allows a significant reduction in hardware and
software cost.
Brief descriptions of the NS32CG16 features that are
shared with other members of the family are provided below:
Powerful Addressing Modes. Nine addressing modes
available to all instructions are included to access data
structures efficiently.
Software Processor Concept. The Series 32000 architecture allows future expansions of the instruction set that can
be executed by special slave processors, acting as extensions to the CPU. This concept of slave processors is
unique to the Series 32000 family. It allows software compatibility even for future components because the slave
hardware is transparent to the software. With future advances in semiconductor technology, the slaves can be
physically integrated on the CPU chip itself.
To summarize, the architectural features cited above provide three primary performance advantages and characteristics:
Data Types. The architecture provides for numerous data
types, such as byte, word, doubleword. and BCD, which may
be arranged into a wide variety of data structures.
Symmetric Instruction Set. While avoiding special case
instructions that compilers can't use, the Series 32000 family incorporates powerful instructions for control operations,
such as array indexing and external procedure calls, which
save considerable space and time for compiled code.
Memory-to-Memory Operations. The Series 32000 CPUs
represent two-address machines. This means that each operand can be referenced by anyone of the addressing
modes provided.
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• High-Level Language Support
• Easy Future Growth Path
This powerful memory-to-memory architecture permits
memory locations to be treated as registers for all useful
operations. This is important for temporary operands as well
as for context switching.
• Application Flexibility
EI
2-97
U) r---------------------------------------------------------------------------------------,
....
I
....
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Table of Contents
CD
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1.0 PRODUCT INTRODUCTION
3.0 FUNCTIONAL DESCRIPTION (Continued)
3.4.7 Slave Processor Communication
3.4.7.1 Slave Processor Bus Cycles
3.4.7.2 Slave Operand Transfer Sequences
1.1 NS32CG16 Special Features
2.0 ARCHITECTURAL DESCRIPTION
2.1 Register Set
3.5 Bus Access Control
2.1.1 General Purpose Registers
2.1.2 Address Registers
2.1.3 Processor Status Register
2.1.4 Configuration Register
3.6 Instruction Status
3.7 Exception Processing
3.7.1 Exception Acknowledge Sequence
3.7.2 Returning from an Exception Service Procedure
3.7.3 Maskable Interrupts
3.7.3.1 Non-Vectored Mode
3.7.3.2 Vectored Mode: Non-Cascaded Case
3.7.3.3 Vectored Mode: Cascaded Case
3.7.4 Non-Maskable Interrupt
3.7.5 Traps
3.7.6 Instruction Tracing
3.7.7 Priority Among Exceptions
3.7.8 Exception Acknowledge Sequences: Detailed
Flow
3.7.8.1 Maskable/Non-Maskable Interrupt
Sequence
3.7.8.2 Trap Sequence: Traps Other Than Trace
3.7.8.3 Trace Trap Sequence
2.2 Memory Organization
2.2.1 Dedicated Tables
2.3 Instruction Set
2.3.1 General Instruction Format
2.3.2 Addressing Modes
2.3.3 Instruction Set Summary
2.4 Graphics Support
2.4.1 Frame Buffer Addressing
2.4.2 BITBLT Fundamentals
2.4.2.1 Frame Buffer Architecutre
2.4.2.2 BIT Alignment
2.4.2.3 Block Boundaries and Destination Masks
2.4.2.4 BITBLT Directions
2.4.2.5 BITBLT Variations
2.4.3 Graphics Support Instructions
2.4.3.1 BITBLT (Bit-aligned BLock Transfer)
2.4.3.2 Pattern Fill
2.4.3.3 Data Compression, Expansion and
Magnify
2.4.3.3.1 Magnifying Compressed Data
3.8 Slave Processor Instructions
3.8.1 Slave Processor Protocol
3.8.2 Floating Point Instructions
4.0 DEVICE SPECIFICATIONS
4.1 NS32CG16 Pin Descriptions
4.1.1 Supplies
4.1.2 Input Signals
4.1.3 Output Signals
4.1.4 Input-Output Signals
3.0 FUNCTIONAL DESCRIPTION
3.1 Power and Grounding
3.2 Clocking
4.2 Absolute Maximum Ratings
3.2.1 Power Save Mode
3.3 Resetting
4.3 Electrical Characteristics
3.4 Bus Cycles
4.4 Switching Characteristics
4.4.1 Definitions
4.4.2 Device Testing
4.4.3 Timing Tables
4.4.3.1 Output Signals: Internal Propagation
Delays
4.4.3.2 Input Signal Requirements
4.4.4 Timing Diagrams
3.4.1 Bus Status
3.4.2 Basic Read and Write Cycles
3.4.3 Cycle Extension
3.4.4 Data Access Sequences
3.4.4.1 Bit Accesses
3.4.4.2 Bit Field Accesses
3.4.4.3 Extending Multiple Accesses
3.4.5 Instruction Fetches
3.4.6 Interrupt Control Cycles
Appendix A: INSTRUCTION FORMATS
2-98
z
List of Illustrations
NS32CG16 Internal Registers ................................................................................... 2-1
Processor Status Register (PSR) ................................................................................. 2-2
Configuration Register (CFG) .................................................................................... 2-3
Module Descriptor Format .......................................................................................2-4
A Sample Link Table ...........................................................................................2-5
General Instruction Format ..............................................................................•....... 2-6
Index Byte Format .............................................................................................2-7
Displacement Encodings ........................................................................................2-8
Correspondence between Linear and Cartesian Addressing ......................................................... 2-9
32-Pixel by 32-Scan Line Frame Buffer ........................................................................... 2-10
Overlapping BITBLT Blocks .................................................................................... 2-11
B B Instructions Format ........................................................................................2-12
BITWT Instruction Format ......................................................................................2-13
EXTBLT Instruction Format .......................................•............................................ 2-14
MOVMPi Instruction Format .................................................................................... 2-15
TBITS Instruction Format ......................................................................................2-16
SBITS Instruction Format ...............................................................................•......2-17
SBITPS Instruction Format ..................................................................................... 2-18
Bus Activity for a Simple BITBLT Operation ........•.............................................................. 2-19
Power and Ground Connections .............................................................................•... 3-1
Crystal Interconnections ...............................................•........................•........•......3-2
Power-On Reset Requirements .................................................................................. 3-3
General Reset Timings ..................•......................................................................3-4
Bus Connections .........................•..............................................................•......3-5
Read Cycle Timing ........................•.......................................................•.......•.... 3-6
Write Cycle Timing ......................................................................................•......3-7
Cycle Extension of a Read Cycle ................................................................................. 3-8
Memory Interface .............................................................................................. 3-9
Slave Processor Connections .................................................................................. 3-1 0
Slave Processor Read Cycle ...................................................................................3-11
Slave Processor Write Cycle ....................................................................................3-12
HOLD Timing, Bus Initially Idle .................................................................................. 3-13
HOLD Timing, Bus Initially Not Idle ..............................................................................3-14
Interrupt Dispatch and Cascade Tables ....................................•...............................•.•... 3-15
Exception Acknowledge Sequence .............................................................................. 3-16
Return from Trap (RETTn) Instruction Flow ...............................................•....................... 3-17
Return from Interrupt (RETI) Instruction Flow ..............................•...................................•.. 3-18
Interrupt Control Unit Connections (16 Levels) ............................•..•.....................•..........•... 3-19
Cascaded Interrupt Control Unit Connections ................................•.....................•.............. 3-20
Service Sequence .................................•.............•............................................3-21
Slave Processor Protocol ..............................................•.......................................3-22
Slave Processor Status Word Format ...............................•.............................•.............. 3-23
Connection Diagram ................................•.....................•............•........•............... 4-1
Timing Specification Standard (CMOS Output Signals) .............................................................. 4-2
Timing Specification Standard (TTL Input Signals) ......•...........................................•......•........ 4-3
Test Loading Configuration .................•........•..............................•......•................•.•..4-4
Read Cycle ..............................................................................•.....................4-5
Write Cycle ..............................................................•.....................•...........•...4-6
HOLD Acknowledge Timing (Bus Initially Not Idle) ......•........................................................... 4-7
HOLD Timing (Bus Initially Idle) .....•................•........................................................•..4-8
DMAC Initiated Bus Cycle ....................................................................................... 4-9
2-99
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List of Illustrations (Continued)
Slave Processor Write Timing ...................................................................................4-10
Slave Processor Read Timing ..........................................................•.............•.........4-11
SPC Timing ..................................................................................................4-12
Relationship of PFS to Clock Cycles .....................................................................••......4-13
Relationship between Last Data Transfer of an Instruction and PFS Pulse of Next Instruction .......................... .4-14
Guaranteed Delay, PFS to Non-Sequential Fetch ..................................................................4-15
Guaranteed Delay, Non-Sequential Fetch to PFS ..........................................•....................... 4-16
Relationship of ILO to First Operand Cycle of an Interlocked Instruction .......•...... , ............................... 4-17
Relationship of ILO to Last Operand Cycle of an Interlocked Instruction .............................................. 4-18
Relationship of ILO to Any Clock Cycle ..........................................................................4-19
Clock Waveforms ............................................................•................................4-20
Power-On Reset ..............................................................................................4-21
Non-Power-On Reset .................................................................................•........4-22
INT Interrupt Signal Detection .........................................................•........................4-23
NMllnterrupt Signal Timing .....................................................................................4-24
List of Tables
NS32CG 16 Addressing Modes ......................................•..........................•................•2-1
NS32CG16 Instruction Set Summary ...........................................•..............................•..2-2
'OP' and 'i' Field Encodings ...................................................••.........•...•.•.............•..2-3
External Oscillator Specifications ................................•.•................................•..•••.......•3-1
Bus Cycle Categories ..........................•.....................••.........................................3-2
Access Sequences ..............•......... " ...........••.........•..........••................................. 3-3
Interrupt Sequences .................................••.........................................................3-4
Floating Point Instruction Protocols .............................•..•.........•....•...............................3·5
Test Loading Characteristics ..•........••.................................•............•...........•.•.. " ....... 4-1
2-100
~----------------------------------------------------------~z
1.0 Product Information
en
w
(Continued)
I\)
1.1 NS32CG16 SPECIAL FEATURES
In addition to the above Series 32000 features, the
NS32CG16 provides features that make the device extremely attractive for a wide range of applications where
graphics support, low chip count, and low power consumption are required.
The most relevant of these features are the graphics support capabilities, that can be used in applications such as
printers, CRT terminals, and other varieties of display systems, where text and graphics are to be handled.
Graphics support is provided by eighteen instructions that
allow operations such as BITBLT, data compression/expansion, fills, and line drawing, to be performed very efficiently.
In addition, the device can be easily interfaced to an external BITBLT Processing Unit (BPU) for high BITBLT performance.
The NS32CG16 allows systems to be built with a relatively
small amount of random logic. The bus is highly optimized
to allow simple interfacing to a large variety of DRAMs and
peripheral devices. All the relevant bus access signals and
clock signals are generated on-chip. The cycle extension
logic is also incorporated on-chip.
The device is fabricated in a low-power, double-poly, single
metal, CMOS technology. It also includes a power-save feature that allows the clock to be slowed down under software
control, thus minimizing the power consumption. This feature can be used in those applications where power saving
during periods of low performance demand is highly desirable.
The bus characteristics and the power save feature are described in the "Functional Description" section. A general
overview of BITBLT operations and a description of the
graphics support instructions is provided in Section 2.4. Details on all the NS32CG16 instructions can be found in the
NS32CG16 Printer/Display Processor Programmer's Reference Supplement and the related NS32CG16 supplement.
Below is a summary of the instructions that are directly applicable to graphics along with their intended use.
Instruction
The BitBlt group of instructions provide a
method of quickly imaging characters, creating
patterns, windowing and other block oriented
effects.
MOVMP
Move Multiple Pattern is a very fast instruction
for clearing memory and drawing patterns and
lines.
TBITS
Q
Set' Bit String is a very fast instruction for filling
objects, outline characters and drawing
horizontal lines.
The TBITS and SBITS instructions support
Group 3 and Group 4 CCITT communications
(FAX).
SBITS
Set Bit Perpendicular String is a very fast
instruction for drawing vertical, horizontal and
45° lines.
In printing applications SBITS and SBITPS may
be used to express portrait and landscape
respectively from the same compressed font
data. The size of the character may be scaled as
it is drawn.
SBITPS
SBIT
CBIT
TBIT
IBIT
The Bit group of instructions enable single pixels
anywhere in memory to be set, cleared, tested
or inverted.
INDEX
The INDEX instruction combines a multiply-add
sequence into a single instruction. This provides
a fast translation of an X-Y address to a pixel
relative address.
.
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w
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2.0 Architectural Description
2.1 REGISTER SET
The NS32CG16 CPU has 17 internal registers grouped according to functions as follows: 8 general purpose, 7 address, 1 processor status and 1 configuration. Figure 2-1
shows the NS32CG16 internal registers.
General Purpose
~ 3281ts ----+
Address
3281ts ----+
~
Application
BBAND
BBOR
BBFOR
BBXOR
BBSTOD
BITWT
EXTBLT
o
Application
Instruction
PC
RO
SPO
R1
SP1
R2
FP
R3
SB
R4
INTBASE
R5
I
R6
MOD
R7
Configuration
Processor Status
PSR
I
ICFG I
FIGURE 2-1. NS32CG16 Internal Registers
2.1.1 General Purpose Registers
There are eight registers (RO-R7) used for satisfying the
high speed general storage requirements, such as holding
temporary variables and addresses. The general purpose
registers are free for any use by the programmer. They are
32 bits in length. If a general purpose register is specified for
Test Bit String will measure the length of 1's or
O's in an image, supporting many data
compression methods (RLL), TBITS may also
be used to test for boundaries of images.
2-101
PI
.
U')
,....
CD
,....
......
IRI
Q)
IR3
IR5
IR7
CASCADED
NS32202
ICU
IRe
HARDWARE
INTERRUPTS
N
IRll
0
C>
......
Q)
......
IR13
IR15
I
GOIIRO
U1
Gl/1R2
G2/1R4
FROM
ADDRESS
DECODER
CS
iNT
G3/1R8
G4/1RI
INTERRUPTS
OR
BIT 110
G5/1Rl0
G8/1R12
G7/1R14
CONTROL
NS32CGI6
CPU
GROUP
MASTER
NS32202
ICU
ADDR
STATUS 1
!NT
INT
FROM
ADDRESS
DECODER
CS
TL/EE/9424-27
FIGURE 3-20. Cascaded Interrupt Control Unit Connections
3.7.4 Non-Maskable Interrupt
The Non-Maskable Interrupt is triggered whenever a falling
edge is detected on the NMI pin. The CPU performs an
"Interrupt Acknowledge, Master" bus cycle when processing of this interrupt actually begins. The Interrupt Acknowledge cycle differs from that provided for Maskable Interrupts in that the address presented is FFFF00 16. The vector
value used for the Non-Maskable Interrupt is taken as 1,
regardless of the value read from the bus.
The service procedure returns from the Non-Maskable Interrupt using the Return from Trap (RETT) instruction. No
special bus cycles occur on return.
3.7.5 Traps
Traps are processing exceptions that are generated as direct results of the execution of an instruction. The Return
Address pushed by any trap except Trap (TRC) is the address of the first byte of the instruction during which the trap
occurred. Traps do not disable interrupts, as they are not
associated with external events. Traps recognized by
NS32CG16 CPU are:
Trap (SLAVE): An exceptional condition was detected by
the Floating Point Unit during the execution of a Slave Instruction. This trap is requested via the Status Word returned as part of the Slave Processor Protocol (Section
3.8.1).
For the full sequence of events in processing the NonMaskable Interrupt, see Section 3.7.7.1.
2-137
I
......
0
......
Z
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.
Lt)
,...
CD
,...
~
(.)
N
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......
.
o
,...
3.0 Functional Description (Continued)
Trap (ILL): Illegal operation. A privileged operation was attempted while the CPU was in User Mode (PSR bit U = 1).
Trap (SVC): The Supervisor Call (SVC) instruction was executed.
CD
,...
Trap (OVZ): An attempt was made to divide an integer by
zero. (The SLAVE trap is used for Floating Point division by
zero.)
~
(.)
N
Trap (FLG): The FLAG instruction detected a "1" in the
CPU PSR F bit.
en
Trap (BPT): The Breakpoint (BPT) instruction was executed.
('I)
z
to the debugger. On the instructions mentioned above, several single-step commands may be required to complete the
instruction, ONLY when interrupts are occurring.
There are some methods to give the appearance of singlestepping for these NS32CG16 instructions.
1. MON16/MONCG monitors the return from single-step
trap vector, PC value. If the PC has not changed since the
last single-step command was issued, the single-step operation is repeated. It is also advisable to ensure that one of
the NS32CG 16 instructions is being single-stepped, by inspecting the first byte of the address pointed to by the PC
register. If it is OxOE, then the instruction is an NS32CG16specific instruction.
2. A breakpoint following the instruction would also trap after the instruction had completed.
Trap (TRC): The instruction just completed is being traced.
See Section 3.7.6.
Trap (UNO): An undefined opcode was encountered by the
CPU.
Note: If instruction tracing is enabled while the WAIT instruction is executed,
the Trap (TAC) occurs after the next interrupt, when the interrupt
service procedure has returned.
3.7.6 Instruction Tracing
Instruction tracing is a feature that can be used during debugging to single-step through selected portions of a program. Tracing is enabled by setting the T-bit in the PSR
Register. When enabled, the CPU generates a Trace Trap
(TRG) after the execution of each instruction.
3.7.7 Priority Among Exceptions
The NS32CG16 CPU internally prioritizes simultaneous interrupt and trap requests as follows:
1) Traps other than Trace
At the beginning of each instruction, the T bit is copied into
the PSR P (Trace "Pending") bit. If the P bit is set at the end
of an instruction, then the Trace Trap is activated. If any
other trap or interrupt request is made during a traced instruction, its entire service procedure is allowed to complete
before the Trace Trap occurs. Each interrupt and trap sequence handles the P bit for proper tracing, guaranteeing
only one Trace Trap per instruction, and guaranteeing that
the Return Address pushed during a Trace Trap is always
the address of the next instruction to be traced.
Due to the fact that some instructions can clear the T and P
bits in the PSR, in some cases a Trace Trap may not occur
at the end of the instruction. This happens when one of the
privileged instructions BICPSRW or LPRW PSR is executed.
(Highest priority)
2) Non-Maskable Interrupt
3) Maskable Interrupts
4) Trace Trap
(Lowest priority)
3.7.8 Exception Acknowledge Sequences: Detail Flow
For purposes of the following detailed discussion of interrupt and trap acknowledge sequences, a Single sequence
called "Service" is defined in Figure 3-21. Upon detecting
any interrupt request or trap condition, the CPU first performs a sequence dependent upon the type of interrupt or
trap. This sequence will include pushing the Processor
Status Register and establishing a Vector and a Return Address. The CPU then performs the Service sequence.
3.7.8.1 Maskable/Non-Maskable Interrupt Sequence
In other cases, it is still possible to guarantee that a Trace
Trap occurs at the end of the instruction, provided that special care is taken before returning from the Trace Trap Service Procedure. In case a BICPSRB instruction has been executed, the service procedure should make sure that the T
bit in the PSR copy saved on the Interrupt Stack is set before executing the RETT instruction to return to the program
begin traced. If the RETT or RETI instructions have to be
traced, the Trace Trap Service Procedure should set the P
and T bits in the PSR copy on the Interrupt Stack that is
going to be restored in the execution of such instructions.
This sequence is performed by the CPU when the NMI pin
receives a falling edge, or the INT pin becomes active with
the PSR I bit set. The interrupt sequence begins either at
the next instruction boundary or, in the case of the String
instructions, or Graphics instructions which have interior
loops (BBOR, BBXOR, BBAND, BBFOR, EXTBLT, MOVMP,
SBITPS, TBITS), at the next interruptible point during its execution. The graphics instructions are interruptible.
1. If a String instruction was interrupted and not yet completed:
a. Clear the Processor Status Register P bit.
While debugging the NS32CG16 instructions which have interior loops (BBOR, BBXOR, BBAND, BBFOR, EXTBLT,
MOVMP, SBITPS, TBITS), special care must be taken with
the single-step trap. If an interrupt occurs during a singlestep of one of the graphics instructions, the interrupt will be
serviced. Upon return from the interrupt service routine, the
new NS32CG16 instruction will not be re-entered, due to a
single-step trap. Both the NMI and INT interrupts will cause
this behavior. Another single-step operation (S command in
DBG16/MONCG) will resume from where the instruction
was interrupted. There are no side effects from this early
termination, and the instruction will complete normally.
b. Set "Return Address" to the address of the first byte
of the interrupted instruction.
Otherwise, set "Return Address" to the address of the
next instruction.
2. Copy the Processor Status Register (PSR) into a temporary register, then clear PSR bits S, U, T, P and I.
3. If the interrupt is Non-Maskable:
a. Read a byte from address FFFF0016, applying Status
Code 0100 (Interrupt Acknowledge, Master: Section
3.4.1). Discard the byte read.
For all other Series 32000 instructions, a single-step operation will complete the entire instruction before trapping back
b. Set
"Vector" to 1.
c. Go to Step 8.
2-138
3.0 Functional Description
z
(Continued)
4. If the interrupt is Non·Vectored:
3) Copy the Processor Status Register (PSR) into a tempo·
rary register, then clear PSR bits S, U, P and T.
a. Read a byte from address FFFE0016, applying Status
Code 0100 (Interrupt Acknowledge, Master: Section
3.4.1). Discard the byte read.
4) Push the PSR copy onto the Interrupt Stack as a 16·bit
value.
b. Set "Vector" to O.
5) Set "Return Address" to the address of the first byte of
the trapped instruction.
c. Go to Step 8.
5. Here the interrupt is Vectored. Read "Byte" from ad·
dress FFFE0016, applying Status Code 0100 (Interrupt
Acknowledge, Master: Section 3.4.1).
6. If "Byte" ~ 0, then set "Vector" to "Byte" and go to
Step 8.
7. If "Byte" is in the range -16 through -1, then the inter·
rupt source is Cascaded. (More negative values are reo
served for future use.) Perform the following:
o
1) In the Processor Status Register (PSR), clear the P bit.
.......
2) Copy the PSR into a temporary register, then clear PSR
bits S, U and T.
U1
6) Perform Service (Vector, Return Address), Figure 3·21.
3.0 SLAVE PROCESSOR INSTRUCTIONS
The NS32CG16 supports only one group of instructions, the
floating point instruction set, as being executable by a slave
processor. The floating point instruction set is validated by
the F bit in the CFG register.
If a floating·point instruction is encountered and the F bit in
the CFG register is not set, a Trap(UND) will result, without
any slave processor communication attempted by the CPU.
This allows software emulation in case an external floating
point unit (FPU) is not used.
2) Move the Module field of the Descriptor into the tempo·
rary MOD Register.
3) Read the Program Base pointer from memory address
MOD + 8, and add to it the Offset field from the Descrip·
tor, placing the result in the Program Counter.
4) Read the new Static Base pointer from the memory ad·
dress contained in MOD, placing it into the SB Register.
Slave Processor instructions have a three·byte Basic In·
struction field, consisting of an 10 Byte followed by an Opere
ation Word. The 10 Byte has three functions:
5) Flush Queue: Non·sequentially fetch first instruction of
Interrupt Routine.
1) It identifies the instruction as being a Slave Processor
instruction.
6) Push MOD Register onto the Interrupt Stack as a 16·bit
value. (The PSR has already been pushed as a 16·bit
value.)
3) It determines the format of the following Operation Word
of the instruction.
3.8.1 Slave Processor Protocol
2) It specifies which Slave Processor will execute it.
Upon receiving a Slave Processor instruction, the CPU initio
ates the sequence outlined in Figure 3-22. While applying
Status Code 1111 (Broadcast ID, Section 3.4.1), the CPU
transfers the 10 Byte on the least·significant half of the Data
Bus (ADO-AD7). All Slave Processors input this byte and
decode it. The Slave Processor selected by the 10 Byte is
activated, and from this point the CPU is communicating
only with it. If any other slave protocol was in progress (e.g.,
an aborted Slave instruction), this transfer cancels it.
7) Push the Return Address onto the Interrupt Stack as a
32·bit quantity.
8) Copy temporary MOD Register to MOD Register.
FIGURE 3·21. ServIce Sequence
Invoked during AlllnterruptlTrap Sequences
3.7.0.2 Trap Sequence: Traps Other Than Trace
1) Restore the currently selected Stack Pointer and the
Processor Status Register to their original values at the
start of the trapped instruction.
2) Set "Vector"
SLAVE:
ILL:
SVC:
DVZ:
FLG:
BPT:
UNO:
The CPU next sends the Operation Word while applying
Status Code 1101 (Transfer Slave Operand, Section 3.4.1).
Upon receiving it, the Slave Processor decodes it, and at
this point both the CPU and the Slave Processor are aware
of the number of operands to be transferred and their sizes.
The Operation Word is swapped on the Data Bus; that is,
bits 0-7 appear on pins AD8-AD15 and bits 8-15 appear
on pins ADO-AD7.
to the value corresponding to the trap type.
Vector = 3.
Vector = 4.
Vector = 5.
Vector = 6.
Vector = 7.
Vector = 8.
Vector = 10.
2·139
z
6) Perform Service (Vector, Return Address), Figure 3·21.
5) Set "Return Address" to the address of the next instruction.
1) Read the 32·bit External Procedure Descriptor from the
Interrupt
Dispatch
Table:
address
is
Vector·4+ INTBASE Register contents.
•
.......
o
......
3.7.0.3 Trace Trap Sequence
4) Set "Vector" to 9.
b. Read "Vector", applying the Cascade Address just
read and Status Code 0101 (Interrupt Acknowledge,
Cascaded: Section 3.4.1).
8. Push the PSR copy (from Step 2) onto the Interrupt
Stack as a 16·bit value.
9. Perform Service (Vector, Return Address), Figure 3·21.
ServIce (Vector, Return Address):
.......
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3) Push the PSR copy onto the Interrupt Stack as a 16·bit
value.
a. Read the 32·bit Cascade Address from memory. The
address is calculated as INTBASE + 4· Byte.
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3.0 Functional Description
(!J
Using the Addressing Mode fields within the Operation
Word, the CPU starts fetching operands and issuing them to
the Slave Processor. To do so, it references any Addressing
Mode extensions which may be appended to the Slave
Processor instruction. Since the CPU is solely responsible
for memory accesses, these extensions are not sent to the
Slave Processor. The Status Code applied is 1101 (Transfer
Slave Processor Operand, Section 3.4.1).
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(Continued)
While the Slave Processor is executing the instruction, the
CPU is free to prefetch instructions into its queue. If it fills
the queue before the Slave Processor finishes, the CPU will
wait, applying Status Code 0011 (Waiting for Slave).
Upon receiving the pulse on SPC, the CPU uses SPC to
read a Status Word from the Slave Processor, applying
Status Code 1110 (Read Slave Status). This word has the
format shown in Figure 3-23. If the Q bit ("Quit", Bit 0) is set,
this indicates that an error was detected by the Slave Processor. The CPU will not continue the protocol, but will immediately trap through the Slave vector in the Interrupt Table.
Certain Slave Processor instructions cause CPU PSR bits to
be loaded from the Status Word.
Status Combinations:
Send ID (I D): Code 1111
Xfer Operand (OP): Code 1101
Read Status (ST): Code 1110
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Step
Status
1
2
3
4
ID
CPU Sends ID Byte.
OP
CPU Sends Operation Word.
OP
CPU Sends Required Operands.
Action
The last step in the protocol is for the CPU to read a result,
if any, and transfer it to the destination. The Read cycles
from the Slave Processor are performed by the CPU while
applying Status Code 1101 (Transfer Slave Operand).
Slave Starts Execution. CPU PreFetches.
5
3.8.2 Floating Point Instructions
Table 3-5 gives the protocols followed for each Floating
Point instruction. The instructions are referenced by their
mnemonics. For the bit encodings of each instruction, see
Appendix A.
Slave Pulses SPC Low.
6
7
ST
CPU Reads Status Word. (Trap? Alter
Flags?)
OP
CPU Reads Results (If Any).
FIGURE 3-22. Slave Processor Protocol
After the CPU has issued the last operand, the Slave Processor starts the actual execution of the instruction. Upon
completion, it will signal the CPU by pulsing SPC low.
Mnemonic
Operand 1
Class
TABLE 3·5. Floating Point Instruction Protocols
Operand 2
Operand 1
Operand 2
Class
Issued
Issued
ADDf
SUBf
MULf
DIVf
read.f
read.f
read.f
read.f
rmw.f
rmw.f
rmw.f
rmw.f
MOVf
ABSf
NEGf
read.f
read.f
read.f
write.f
write.f
write.f
CMPf
read.f
read.f
FLOORfi
TRUNCfi
ROUNDfi
read.f
read.f
read.f
write.i
write.i
write.i
f
MOVFL
MOVLF
read.F
read.L
write.L
write.F
F
L
MOVif
read.i
write.f
LFSR
SFSR
read.D
N/A
D
N/A
write.D
N/A
POLYf
DOTf
SCALBf
LOGBf
read.f
read.f
read.f
read.f
read.f
read.f
rmw.f
write.f
Note:
o=
Double Word
= integer size (B,W,D) specified in mnemonic.
f = Floating Point type (F,L) specified in mnemonic.
Nt A = Not Applicable to this instruction.
i
2-140
Returned Value
Type and Dest.
PSR Bits
Affected
ftoOp.2
ftoOp.2
ftoOp.2
fto Op. 2
none
none
none
none
N/A
N/A
N/A
fto Op. 2
ftoOp.2
ftoOp.2
none
none
none
N/A
N,Z,L
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
ito Op. 2
ito Op. 2
itoOp.2
none
none
none
LtoOp.2
FtoOp.2
none
none
N/A
fto Op. 2
none
N/A
DtoOp.2
none
none
fto FO
fto FO
ftoOp.2
ftoOp.2
none
none
none
none
z
4.1.2 Input Signals
Reset Input.
RSTI
Schmitt triggered, asynchronous signal used to
generate a CPU reset. See Section 3.3.
3.0 Functional Description (Continued)
The Operand class columns give the Access Class for each
general operand, defining how the addressing modes are
interpreted (see Series 32000 Instruction Set Reference
Manual).
Note:
The reset signal is a true asynchronous input. Therefore. no
external synchronizing circuit is needed.
The Operand Issued columns show the sizes of the oper·
ands issued to the Floating Point Unit by the CPU. "0" indio
cates a 32·bit Double Word. "i" indicates that the instruction
specifies an integer size for the operand (B = Byte,
W = Word, 0 = Double Word). "f" indicates that the instruc·
tion specifies a Floating Point size for the operand (F = 32·
bit Standard Floating, L=64·bit Long Floating).
When RSTI changes right before the falling edge of CTTL,
and meets the specified set·up time, it will be recognized on
that falling edge. Otherwise it will be recognized on the failing edge of CTTL in the following clock cycle.
Hold Request.
When active, causes the CPU to release the
bus for DMA or multiprocessing purposes. See
Section 3.5.
The Returned Value Type and Destination column gives the
size of any returned value and where the CPU places it. The
PSR Bits Affected column indicates which PSR bits, if any,
are updated from the Slave Processor Status Word (Figure
Note:
If the HOLD signal is generated asynchronously, its set up
and hold times may be violated. In this case, it is recommended to synchronize it with CTTL to minimize the possibility of metastable states.
3·23).
15
8 7
I 00000000 IN
Z F 0 0 L0
NewPSRBltVaIUe(I)~
"auit": Terminate Protocol. Trap(FPU).
The CPU provides only one synchronization stage to minimize the HLDA latency. This is to avoid speed degradations
in cases of heavy HOLD activity (I.e., DMA controller cycles
interleaved with CPU cycles).
al
J
Interrupt.
A low level on this pin requests a maskable interrupt. INT must be kept asserted until the interrupt is acknowledged.
TLlEE/9424-28
FIGURE 3-23. Slave Processor Status Word Format
Any operand indicated as being of type "f" will not cause a
transfer if the Register addressing mode is specified. This is
because the Floating Point Registers are physically on the
Floating Point Unit and are therefore available without CPU
assistance.
Non-Maskable Interrupt.
A High-to-Low transition on this signal requests
a non-maskable interrupt
Continuous Wait.
Causes the CPU to insert continuous wait
states if sampled low at the end of T2 and each
following T-State. See Section 3.4.3.
4.0 Device Specifications
4.1 NS32CG16 PIN DESCRIPTIONS
The following is a brief description of all NS32CG 16 pins.
The descriptions reference portions of the Functional Description, Section 3.
WAIT1-2
Unless otherwise indicated, reserved pins should be left
open.
Note: During a DMA cycle, WAIT1-2 should be kept inactive
unless they are also monitored by the DMA Controller.
Wait states, in this case, should be generated through
CWAIT.
Note: An asterisk next to the signal name indicates a TRI-STATE condition
for that signal during HOLD acknowledge.
4.1.1 Supplies
VCCL
Two-Bit Wait State Inputs.
These inputs, collectively called WAIT1-2, allow from zero to three wait states to be specified. They are binary weighted. See Section
3.4.3.
OSCIN
Logic Power.
+ 5V positive supply for on-chip logic.
Crystal/External Clock Input.
Input from a crystal or an external clock source.
See Section 3.2.
VCCCTTL, Buffers Power.
VCCFCLK, + 5V positive supplies for on-chip output
VCCAD,
buffers.
VCCIO
4.1.3 Output Signals
A 16-A23 *Hlgh-Order Address Bits.
These are the most significant 8 bits of the
memory address bus.
VSSL
HBE
Logic Ground.
Ground reference for on-chip logic.
VSSFCLK, Buffers Ground.
VSSNTSC, Ground reference for on·chip output buffers.
VSSHAD,
VSSLAD,
VSSIO
2·141
*High Byte Enable.
Status signal used to enable data transfers on
the most significant byte of the data bus.
en
w
N
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.
.......
en
.......
o
z
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en
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N
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.
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en
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~------------------------------------------------------------------------------------------,
4.0 Device Specifications (Continued)
STO-3
Status.
TSO
U)
Bus cycle status code; STO is the least significant.
Encodings are:
Z
OOOO-idle: CPU Inactive on Bus.
o
,....
•
CD
,....
0001-ldle: WAIT Instruction.
N
C")
......
The falling edge of TSO identifies the beginning
of state T2 of a bus cycle. The rising edge identifies the beginning of state T4.
DBE
OSCOUT
01 OO-Interrupt Acknowledge, Master.
N
C")
Z
0110-End of Interrupt, Master.
0111-End of Interrupt, Cascaded.
1000-Sequential Instruction Fetch.
FCLK
1001-Non-Sequentiallnstruction Fetch.
Fast Clock.
This clock is derived from the clock waveform
on OSCIN. Its frequency is either the same as
OSCIN or is lower, depending upon the scale
factor programmed into the CFG register. See
Section 3.2.1.
1010-Data Transfer.
1011-Read Read-Modify-Write Operand.
1100-Read for Effective Address.
1101-Transfer Slave Operand.
1110-Read Slave Status Word.
PHI1, PHI2 Two-Phase Clock.
These outputs provide a two-phase clock with
frequency half that of FCLK. They can be used
to clock the DP8510/DP8511 BPU. The trace
lengths of PHI1 and PHI2 should be shorter
than 4 inches (10 centimeters) when connected
to the BPU.
1111-Broadcast Slave ID.
U/S
Crystal Output.
This line is used as the return path for the crystal (if used). When an external clock source is
used, OSCOUT should be left unconnected or
loaded with no more than 5 pF of stray capacitance.
0101-lnterrupt Acknowledge, Cascaded.
U)
Data Buffers Enable.
Used to control external data buffers. It is active
when the data buffers are to be enabled.
0010-(Reserved)
0011-ldle: Waiting for Slave.
"o
TImIng State Output.
User/Supervisor.
User or Supervisor Mode status. High indicates
User Mode; low indicates Supervisor Mode.
Interlocked OperatIon.
CTTL
When active, indicates that an interlocked operation is being executed.
System Clock.
This clock is similar to PHI1 but has a much
higher driving capability. The skew between its
rising edge and PHI1 rising edge is kept to a
minimum.
Hold Acknowledge.
Activated by the CPU in response to the HOLD
input to indicate that the CPU has released the
bus.
4.1.4 Input-Output SIgnals
ADO-15
*Address/Data Bus.
Program Flow Status.
A pulse on this signal indicates the beginning of
execution of an instruction.
Multiplexed Address/Data information. Bit 0 is
the least significant bit of each.
BPU Cycle.
Slave Processor Control.
This signal is activated during a bus cycle to
enable an external BITBLT processing unit. The
EXTBLT instruction activates this signal. *
Used by the CPU as the data strobe output for
slave processor transfers; used by a slave processor to acknowledge completion of a slave instruction. See Section 3.4.7.1.
Reset Output.
This signal becomes active when RSTI is low,
initiating a system reset.
*Data DIrection.
Status signal indicating the direction of the data
transfer during a bus cycle. During HOLD acknowledge this signal becomes an input and
determines the activation of RD or WR.
Read Strobe.
Activated during CPU or DMAC read cycles to
enable reading of data from memory or peripherals. See Section 3.4.2.
* Address Strobe
WrIte Strobe.
Controls address latches; signals the beginning
of a bus cycle. During HOLD acknowledge this
signal becomes an input and the CPU monitors
it to detect the beginning of a DMA cycle and
generate the relevant strobe signals. When a
DMA is used, ADS should be pulled up to Vee
through a 10 k!l resistor.
Activated during CPU or DMAC write cycles to
enable writing of data to memory or peripherals.
°Note: BPO is low (Active) only during bus cycles involving
pre-fetching instructions and execution of EXTBLT
operands. It is recommended that BPU, ADS and
status lines (STO-ST3) be used to qualify BPU bus
cycles. If a DMA circuit exists In the system, the
HLDA signal should be used to further qualify BPU
cycles. BPO may become active during T 4 of a nonBPU bus cycle, and may become inactive during T4
of a BPU bus cycle. BPU must be qualified by ADS
and status lines (STO-ST3) to be used as an external gating signal.
2-142
z
4.0 Device Specifications (Continued)
4.2 ABSOLUTE MAXIMUM RATINGS
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Temperature Under Bias
O°Cto +70°C
Storage Temperature
- 65°C to + 150°C
4.3 ELECTRICAL CHARACTERISTICS: TA
All Input or Output Voltages with
-0.5Vto +7V
Respect to GND
Note: Absolute maximum ratings indicate limits beyond
which permanent damage may occur. Continuous operation
at these limits is not intended; operation should be limited to
those conditions specified under Electrical Characteristics.
en
w
N
o
C)
.
..""
0')
..""
o
.......
Z
en
w
N
oC)
= O°C to + 70°C, Vee = 5V ± 5%, GND = OV
..""
Symbol
Parameter
Conditions
Min
Typ
Max
Units
0')
U1
High Level Input Voltage
(Note 4)
2.0
Vee + 0.5
V
VIL
Low Level Input Voltage
(Note 3)
-0.5
0.8
V
VT+
RSTI Rising Threshold Voltage
= 5.0V (Note 5)
Vee = 5.0V (Note 5)
2.5
3.5
V
VIH
VHYS
RSTI Hysteresis Voltage
VXL
OSCIN Input Low Voltage
VXH
OSCIN Input High Voltage
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
IlLS
II
IL
Vee
SPC Input Current (low)
Input Load Current
o ~ VIN
Leakage Current
Output and 110 Pins in
TRI·STATE Input Mode
0.4 ~ VOUT ~ Vee
lee
Active Supply Current
PHI1, 2 High Level Output Voltage
1.8
V
0.5
V
4.5
= -400 j.LA (Note 6)
IOL = 4 rnA (Note 6)
VIN = O.4V, SPC in Input Mode
VPH
0.8
IOH
~
Vee, All Inputs except SPC
= 0, T A = 25°C (Note 2)
= -400 j.LA
IOL = 4 rnA
V
0.45
V
0.05
1.0
rnA
-20
20
j.LA
-20
20
j.LA
200
rnA
140
lOUT
IOH
V
2.4
0.9 Vee
PHI1, 2 Low Level Output Voltage
0.1 Vee
Note 1: Care should be taken by designers to provide a minimum inductance path between the Vss pins and system ground in order to minimize noise.
Note 2: lec is affected by the clock scaling factor selected by the C and M bits in the CFG register, see Section 3.2.1.
Note 3: VIL min-in the range of -0.5V to -1.5V, the pulse must be s: 20 ns, and the period between pulses ~ 120 ns.
Note 4: VIH max-in the range of Vee + 0.5V to Vee + 2.0V, the pulse must be s: 25 ns, and the period between pulses ~ 120 ns.
Note 5: Not 100% tested.
Note 6: All outputs except PHI1 and PHI2.
VPL
2·143
V
V
•
..""
....•
U) ~--------------------------------------------------------------------------------------,
....
~
U)
4.0 Device Specifications (Continued)
o
N
6S-Pln PCC Package
Cf)
U)
~ ~ ~ I~ I~ I~ ~I~ I I ~ ~ ~ ~ ~ ~ ~
Z
....C;
....ch
~
~
Cf)
ST2
28
U)
ST3
prs
29
A16
DDIN
30
VCCAD
z
A18
A17
ADS
AD15
SPC
AD14
VCCIO
AD13
HBE
AD12
HOLDA
ADll
HOLD
AD10
RSTO
AD9
WAITl
AD8
WAIT2
VSSLAD
CWAIT
AD7
VSSL
AD6
OSCIN
AD5
RSTI
AD4
TL/EE/9424-29
Bottom View
FIGURE 4-1. Connection Diagram
4.4 SWITCHING CHARACTERISTICS
CnL[_~r~-2.0_V------------
O.BV
4.4.1 Definitions
All the timing specifications given in this section refer to
O.BV or 2.0V on the rising or falling edges of CTTL when the
capacitive loading of CTIL is 100 pF, unless specifically
stated otherwise. The timing specifications refer to O.B or
2.0V on the TIL output and input signals as illustrated in
Figures 4-2 and 4-3 unless specifically stated otherwise.
[ --+--------""\.-1-----~tS~IG:!.!1I------- --~O.-BV--O.45V
2.4V
SIG1
__
tSIG2h
SIG2
[
_ _ _ _ _ _--"
.....------uv
~
2.0V
- ------------O.45V
TL/EE/9424-30
FIGURE 4-2. Timing Specification Standard
(TTL Output Signals)
2·144
z
en
w
N
o
C)
4.0 Device Specifications (Continued)
ABBREVIATIONS:
4.4.2 DEVICE TESTING
L.E. -leading edge
R.E. - rising edge
T.E. - trailing edge
F.E. - falling edge
em[
......
Q)
TEST EQUIPMENT
r-----------.,
•
......
Q
.......
2.0VC
Z
______________________
O~.8~V~
J:-~~G!!-:: - - - o.a~I'_---_+_-
PROGRAMMABLE
CURRENT
SOURCE/SINK
SIGl[---------..
t:t
~
....-,.---.....
T--: VIN :>: Vee)
2.0V:>:VOH:>:VCC+ 0.5V
-0.5V:>:VOL:>:0.BV
Input Load
Current
High Level
Input Voltage
Low Level
Input Voltage
-20 /LA:>: 11:>:20 /LA
2.0V:>:VIH:>:VCC+ 0.5V
-0.5V:>:VIL:>:0.45V
-20 /LA:>: 11:>:20 /LA
2.0V:>:VIH:>:VCC+ 0.5V
-0.5V:>:VIL:>:0.BV
50pF
iLO, HLDA, PFS,
BPO, RSTO, RD,
WR, TSO, DBE,
FCLK, ODiN, ADS
RSTI, HOLD, INT,
High Level
Output Voltage
(IOH = - 400 /LA)
50pF
NMI, eWAlT, WAff1-2
OSCIN
50pF
ADO-15, A16-23,
CTIL
100pF
PHI1,PHI2
30pF
(Note 2)
(Note 2)
~
30pF
2.0V:>:VOH:>:VCC+ 0.5V
-0.5V:>:VOL:>:0.BV
see Table
3·1
2.0V:>:VOH:>:VCC+ 0.5V
-0.5V:>:VOL:>:0.8V
OSCOUT
(Note 1)
2.0V:>:VOH:>:VCC+ 0.5V
-0.5V:>:VOL:>:0.BV
-20 /LA:>:II:>:20 /LA
4.5V :>: VIH:>: Vee + 0.5V
-0.5V:>:VIL:>:0.5V
-20 /LA:>: 11:>:20 /LA
2.4V:>:VIH:>:VCC+ 0.5V
-0.5V:>:VIL:>:0.45V
50 /LA:>: II:>: 1.0 mA
2.0V:>:VIH:>:VCC+ 0.5V
-0.5V:>:VIL:>:0.4V
Not. 1: The maximum capacitive loading of 05COUT Is given In Table 3·1 when the NS32CG16's oscillator Is driven with a crystal. If a Single phase clock source is
used, 05COUT should be left unconnected or loaded with no more than 5 pF of stray capacitance.
Note 2: As stated in Table 4.4.3.
2-145
.
......
Q)
......
U'I
FIGURE 4.4. Test Loading Configuration
FIGURE 4-3. Timing Specification Standard
(TTL Input Signals)
Signal Name
en
N
oC)
w
.
,...
CD
,...
4.0 Device Specifications (Continued)
CJ
4.4.3 Timing Tables
C")
4.4.3.1 Output Signals: Internal Propagation Delays, NS32CG16-10 and NS32CG16-15
&t)
oN
U)
Z
.......
.
o
,...
CD
,...
CJ
o
N
C")
U)
Name
Figure
Description
Reference/Conditions
tCTp
4-20
CTIL Clock Period
R.E., CTIL to Next R.E., CTIL
tCTh
4-20
CTIL High Time
At 1.5V (Both Edges)
(see Note 1)
25 pF-100 pF Capacitive Load
Z
NS32CG16-10
NS32CG16-15
(Note 3)
Units
Min
Max
Min
Max
100
1000
66
1000
ns
0.40
0.57
0.46
0.58
tcTp
tCTI
4-20
CTILLowTime
AtO.8V
25 pF-100 pF Capacitive Load
0.42
0.56
0.40
0.53
tCTp
tCTr
4-20
CTIL Rise Time
0.8V to 2.0V VCC on R.E., CTIL
0
8
0
6
ns
tCTt
4-20
CTIL Fall Time
2.0V to 0.8V VCC on F.E., CTIL
0
8
0
6
ns
tCLw(1,2)
4-20
PHI1, PHI2 Pulse Width
At 2.0V on PHI1, PHI2
(Both Edges)
0.35
0.55
0.32
0.53
tCTp
tCLh
4-20
Clock High Time
At 90% VCC on PHI1, PHI2
(Both Edges)
0.22
0.50
0.28
0.50
tcTp
tnOVL(1,2)
4-20
PHI1, PHI2, Non-Overlap
Time
At 50% VCC on PHI1, PHI2
tXFr
4-20
OSCIN to FCLK
R.E. Delay
80% VCC on R.E., OSCIN
to R.E., FCLK
tFCr
4-20
FCLKtoCTIL
R.E. Delay
R.E., FCLK to R.E., CTIL
tFCf
4-20
FCLKtoCTIL
F.E. Delay
R.E., FCLK to F.E., CTIL
tPCr
4-20
CTILand PHI1 Skew
R.E., CTIL to R.E., PHI1
tALv
4-5
Address Bits 0-15 Valid
after R.E., CTIL T1
tALh
4-5
Address Bits 0-15 Hold
after R.E., CTIL T2
tAHv
4-5
Address Bits 16-23 Valid
after R.E., CTIL T1
tAHh
4-5
Address Bits 16-23 Hold
after R.E., CTIL Next T1 or Ti
tAUr
4-5
Address Bits 0-15
floating (during read)
after R.E., CTIL T2
ns
2
2
29
2
25
ns
-2
10
-2
10
ns
-2
10
-2
10
ns
-4
4
-4
4
ns
40
4
30
ns
40
0
30
ns
5
0
5
ns
5
ns
0
38
5
28
ns
ADO-AD15
36
ns
4
4
26
Floating (Note 2)
Note 1: Device testing Is performed using the Test Loading Characteristics In Table 4.1. Additional timing data for CTIL with various capacitive loads Is not 100%
tested.
Note 2: tALnlr Is address bits 0-15 floating or not active after R.E. CTIL T1. This Is only valid If the previous CPU cycle was a read (Figure 4.5). A previous wrlte
may have "data" active into T1 of the next cycle which then becomes "address" during T1.
Note 3: 15 MHz specifications are only guaranteed when tcTp = 66 ns.
tALnfr
4-5
2
2-146
zen
4.0 Device Specifications (Continued)
w
N
(')
4.4.3.1 Output Signals: Internal Propagation Delays, NS32CG16-10 and NS32CG16-15 (Continued)
Name
Figure
Description
Reference/Conditions
NS32CG16-10
Min
tAu
4·7
ADO-AD15 Floating
(Caused by HOLD)
after R.E., CTIL Ti
tAHf
4·7
A 16-A23 Floating
after R.E., CTIL Ti
tALnf
4·5,4·8
Address Bits 0-15
Not Floating
after R.E., CTIL T1
tAHnf
4·8
tov
4·6,4·10
tOh
4·6,4·10
Max
C)
NS32CG16-15
Min
.....
Q)
Units
Max
I
o
"-
z
25
18
ns
en
w
25
18
ns
(')
26
ns
.....
N
Address Bits 16-23
Not Floating
after R.E., CTIL T4
Data Valid (Write Cycle)
after R.E., CTIL T2 or T1
4
36
4
4
36
4
50
26
ns
38
ns
0
Data Hold
after R.E., CTIL Next T1 or Ti
0
4·5
ADS Signal Active
after R.E., CTIL T1
5
35
5
26
tAOSia
4·5
ADS Signal Inactive
after F.E., CTIL T1
5
35
5
25
tAOSw
4·6
ADS Pulse Width
at 15% VCC (Both Edges)
tAOSf
4·7
ADS Floating
after R.E., CTIL Ti
55
40
tAOSr
4·8
ADS Return from Floating
after R.E., CTIL Ti
55
40
tALAOSs
4·6
Address Bits 0-15 Setup
before ADS T.E.
25
20
ns
tAHAOSs
4·6
Address Bits 16-23 Setup
before ADS T.E.
25
20
ns
tALAOSh
4·5
Address Bits 0-15 Hold
after ADS T.E.
12
12
tHBEv
4·5
HBE Signal Valid
after R.E., CTIL T1
tHBEh
4·5
HBE Signal Hold
after R.E., CTIL Next T1 or Ti
tHBEf
4·7
HBE Signal Floating
after R.E., CTIL Ti
55
40
ns
tHBEr
4·8
HBE Return from Floating
after R.E., CTIL Ti
55
40
ns
tOOINv
4-5
DDIN Signal Valid
after R.E., CTIL T1
65
38
ns
tOOINh
4-5
DDIN Signal Hold
after R.E., CTIL Next T1 or Ti
tOOINf
4·7
DDIN Floating
after R.E., CTIL Ti
55
40
ns
40
ns
30
ns
25
ns
ns
ns
0
0
ns
ns
0
0
ns
ns
38
60
ns
ns
tOOINr
4-8
DDIN Return from Floating
after R.E., CTIL Ti
55
tSPCa
4·10
SPC Output Active
after R.E., CTIL T1
35
5
26
ns
tSPCia
4-10
SPC Output Inactive
after R.E., CTIL T4
35
5
26
ns
tSPCnf
4-12
SPC Output Non-Forcing
(Note 2)
after F.E., CTIL T4
tHLOAa
4·7
HLDA Signal Active
after R.E., CTIL Ti
50
26
ns
tHLOAia
4·8
HLDA Signal Inactive
after R.E., CTIL Ti
50
26
ns
tSTv
4-5
Status STO-ST3 Valid
after R.E., CTIL T4
(before T1, see Note 1)
45
38
ns
tSTh
4·5
Status STO-ST3 Hold
after R.E., CTIL T4
4·5
BPU Signal Valid
after R.E., CTIL T4
30
ns
tCTp
+ 10
tCTp
+8
0
0
45
ns
ns
5
BPU Signal Hold
5
ns
after R.E., CTIL T4
4·5
Note 1: Every memory cycle starts with T4, during which Cycle Status is applied. If the CPU was idling, the sequence will be: " ... Ti, T4, T1 ... ". If the CPU was
not idling, the sequence will be: " '" T4, T1 ... ".
Note 2: If the CPU is connected directly to the FPU and the CTTL loading is not violated, the CPU and FPU will function correctly together. The CPU and FPU
connect directly without buffers. They should be located less than 4 inches (10 centimeters) apart. tspca and tSPCia will track each other on all CPU's and therefore
it is not possible to have a minimum tSPCia and a maximum tSPCa value. The pulse width minimum, tsPCw, of the FPU will not be violated by the NS32CG 16 when
connected directly to the FPU.
tBPUh
2·147
C)
.....
Q)
I
CJ1
tAOSa
tBPUv
.....
Lt)
orI
CD
0r-
e"
4.0 Device Specifications (Continued)
o
N
4.4.3.1 Output Signals: Internal Propagation Delays, NS32CG16-10 and NS32CG16-15 (Continued)
en
Name
C")
z
........
oor-
Figure
Description
Reference/Conditions
NS32CG16-10
Min
NS32CG16-15
Units
Max
Min
Max
15
2
12
ns
0
10
ns
15
ns
15
ns
tTSOa
4-5
TSO Signal Active
tTSOia
4-5
TSO Signal Inactive
after R.E., CTIL T4
15
tAOa
4-5
RD Signal Active
after R.E., CTIL T2
20
C")
tAOia
4-5
RD Signal Inactive
after R.E., CTIL T4
20
z
tWAa
4-6
WR Signal Active
after R.E., CTIL T2
20
tWRia
4-6
WR Signal Inactive
after R.E., CTIL T4
20
tOBEa(A)
4-5
DBE Active (Read Cycle)
after F.E., CTIL T2
tOBEa(W)
4-6
DBE Active (Write Cycle)
after R.E., CTIL T2
DBE Inactive
after F.E., CTIL T 4
tUSv
4-5
U/S Signal Valid
after R.E., CTIL T 4
tUSh
4-5
U/S Signal Hold
after R.E., CTIL T 4
tPFSa
4-13
PFS Signal Active
after F.E., CTIL
50
38
ns
tPFSia
4-13
PFS Signal Inactive
after F.E., CTIL
50
38
ns
tpFSw
4-13
PFS Pulse Width
at 15% Vee (Both Edges)
tNSPF
4-16
Nonsequential Fetch
to Next PFS Clock Cycle
after R.E., CTIL T1
tpFNS
4-15
PFS Clock Cycle to
Next Nonsequential Fetch
before R.E., CTIL T1
tlXPF
4-14
Last Operand Transfer
of an Instruction to
Next PFS Clock Cycle
before R.E., CTIL T1 of
First Bus Cycle of Transfer
after R.E., CTIL T2
I
CD
0r-
e"
o
N
en
tOBEia
4-5,4-6
5
t
0
15
ns
15
ns
21
15
ns
28
15
ns
23
15
ns
40
30
0
5
I
ns
ns
70
45
ns
4
4
teTp
4
4
teTp
0
0
tCTp
tllOs
4-17
ILO Signal Setup
before R.E., CTIL T1 of
First Interlocked Read Cycle
30
30
ns
tllOh
4-18
ILO Signal Hold
after R.E., CTIL T3 of Last
Interlocked Write Cycle
5
5
ns
tllOa
4-19
ILO Signal Active
after R.E., CTIL
55
35
ns
tllOia
4-19
ILO Signal Inactive
after R.E., CTIL
55
35
ns
tASTOa
4-22
RSTO Signal Active
after R.E., CTIL
21
15
ns
tASTOia
4-22
RSTO Signal Inactive
after R.E., CTIL
21
15
ns
tATOI
4-22
Reset to Idle
after F.E. of RSTO
10
10
teTp
tATOF
4-22
Reset to Fetch
after R.E. of RSTO
8
8
teTp
2-148
z
en
w
4.0 Device Specifications (Continued)
N
4.4.3.2 Input Signal Requirements: NS32CG16-10 and NS32CG16-15
Name
Figure
Description
Reference/Conditions
txp
4-20
OSCIN Clock Period
R.E., OSCIN to Next R.E., OSCIN
tXh
4-20
OSCIN High Time
(External Clock)
at 4.2V (Both Edges)
4-20
OSCIN Low Time
at 1.0V (Both Edges)
tXI
NS32CG16-10
NS32CG16-15
Min
Max
Min
Max
50
500
33
500
Units
ns
11
ns
16
11
ns
18
15
ns
7
7
ns
tOl s
Data In Setup
before R.E., CTTL T4
tOlh
4-5,4-11
Data In Hold
(see Note 1)
after R.E., CTTL T 4
tCWs
4-5,4-6
CWAIT Signal Setup
before R.E., CTTL T3 orT3(w)
20
20
ns
tCWh
4-5,4-6
CWAIT Signal Hold
after R.E., CTTL T3 or T3(w)
5
5
ns
tws
4-5,4-6
WAITn Signals Setup
before R.E., CTTL T3 or T3(w)
20
20
ns
tWh
4-5,4-6
WAITn Signals Hold
after R.E., CTTL T3 or T3(w)
5
5
ns
tHLOs
4-7,4-8
HOLD Setup Time
before R.E., CTTL TX2 or Ti
30
22
ns
tHLOh
4-7,4-8
HOLD Hold Time
after R.E., CTTL Ti
0
0
ns
tpWR
4-21
Power Stable to RSTI R.E.
after VCC Reaches 4.5V
50
33
p's
tRSTs
4-21,4-22
RSTI Signal Setup
before F.E., CTTL
20
20
ns
tRSTw
4-22
RSTI Pulse Width
at O.BV (Both Edges)
64
64
tCTp
tSPCh
4-12
SPC Hold Time
(see Note 3)
after R.E., CTTL
0
0
ns
tlNTh
4-23
INT Signal Hold
after Interrupt Acknowledge
tNMlw
4-24
NMI Pulse Width
at 0.8V (Both Edges)
tSPCd
4-12
SPC Pulse Delay
from Slave
after F.E., CTTL T 4
tsPCs
4-12
SPC Input Setup
tAOSs
4-9
ADS Input Setup
tAOSh
4-9
ADS Input Hold
(see Note 2)
after F.E., CTTL T1
tOOINs
4-9
DDIN input Setup
tOOINh
4-9
DDIN Input Hold
8
8
tCTp
70
50
ns
2
2
tCTp
before F.E., CTTL
37
30
ns
before F.E., CTTL
15
10
ns
10
10
ns
before F.E., CTTL
15
10
ns
after R. E., CTTL T 4
7
5
ns
Note 2: ADS must be deasserted before state T4 of the DMA controller cycle.
Note 3: Not tested, guaranteed by design.
2-149
.
o
z
'"
en
w
16
4-5,4-11
Note 1: tDlh is always less than or equal to tRDia.
oG')
.....
0')
.....
N
oG')
.....
0')
.....
.
U1
--•
-o
U) . - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .
U)
CJ
4.0 Device Specifications (Continued)
4.4.4 TIMING DIAGRAMS
'"
('t)
en
T4 OR n
z......
--o.
-o
T1
T2
T3
T4
nOR T1
U)
CJ
'"
en
('t)
ADO-ADI5 [
_-+-__-+'
A16-A23 [
_--+-__-+0'
z
ADS [
HBE
[-+---i-'
ODIN [
-+--~-~-+--+-~--_+-+_~~--r_-
STO-ST3 [
U/s [
BPU [
rso[
RD[
DBE[
TL/EE/9424-32
FIGURE 4-5. Read Cycle
2-150
z
en
w
N
oC)
4.0 Device Specifications (Continued)
T4 OR
n
T1
T2
T3
T3(W)
T3(W)
JLrLILILILrL
~
-)t\-t>t
T4
I--
---.
~tDv
ADO-AD15 [
- ------
_.
~tAl.AOSI
-.
~tODINv
N
o
C)
.
~
-"
en
I...-.-
-"
U1
-~tODINh
1\
DDIN [
BPU [
z
en
w
tOh
-
HBE [
U/s [
en
•
-"
o
.......
V
...
STO-ST3 [
-"
~
~ t AHAOSs
~~t
-.
rL
-
------ -):
1---.
n
-lC
DATA OUT
1---.
A16-A23 [
T1 OR
~
)
=tx
=tx
]X
)
)
I
~
tWRIl - .
tWRIIl - .
\
tOBEIl(W) - .
DBE[
fi
-.
~
~~ ~ ~ ~
~
tW. - .
WAIT1 [
~~ ~~~
~
tOBElIl
t
\k-1\
~
t CW. - .
CWAIT [
rl-
-.
'---.
tcwh
~ ~~ ~ ~ ~
k-tWh
TUEE/9424-33
FIGURE 4·6. Write Cycle
2-151
....
U) r---------------------------------------------------------------------------------------~
I
....
CD
4.0 Device Specifications (Continued)
(!J
o
N
C"')
tn
Z
.......
....o
....
TXl
TX2
T4
TI
TI
TI
cm[
I
CD
(!J
o
N
C"')
HOLD [
tn
Z
HlOA [
(FLOATING)
----L----
ADO-AD15 [
(FLOATING)
----L----
A16-A2J [
(FLOATING)
I
TL/EE/9424-34
FIGURE 4·7. HOLD Acknowledge Timing (Bus Initially Not Idle)
Note: When the bus is not idle, fID[O must be asserted before the rising edge of CTIL of the timing state that precedes state T41n order for the request to be
acknowledged.
2-152
z
en
w
I\)
oC)
4.0 Device Specifications (Continued)
T4 OR TI
TI
TI
TI
TI
TI
T4 OR TI
T1 OR TI
...&.
c:n
•
o
.......
...&.
em [
Z
en
w
I\)
HOLD
o
[
C)
.
...&.
c:n
...&.
U1
HLOA
[
ADS
[
HBE
[
ODIN
[
TLlEE/9424-35
FIGURE 4·8. HOLD Timing (Bus Initially Idle)
2·153
an
"t-
•
CD
"t-
4.0 Device Specifications (Continued)
C!J
o
C\I
C")
(J)
z
......
o"t-
•
CPU STATES
DMAC STATES
n
n
n
n
n
n
n
n
T1
T2
T3
T3(W)
T4
Tl OR
n
cm[
CD
"t-
C!J
o
C\I
C")
(J)
HOLD
[
HLDA
[
ADS
[
ODIN
[
TSO
[
CWAIT
[
WAIT1-2
[
z
,
(HIGH)
TLlEE/9424-36
FIGURE 4·9. DMAC Initiated Bus Cycle
Note 1: ADS must be deactivated before state T4 of the DMA controller cycle.
Note 2: During a DMA cycle WAIT1-2 must be kept inactive unless they are monitored by the DMA Controller. A DMA cycle is similar to a CPU cycle. The
NS32CG16 generates TSO, RD, WR and DBE. The DMAC drives the address/data lines HBE, ADS and ODIN.
Note 3: During a DMA cycle, if the ADS signal is pulsed in order to initiate a bus cycle, the HOLD signal must remain asserted until state T 4 of the DMAC cycle.
2-154
,------------------------------------------------------------------------------, z
en
w
4.0 Device Specifications (Continued)
N
11
T4
11
oG)
.
T4
-"'"
0)
-"'"
cm [
o
.......
CTIL [
z
en
w
N
o
G)
ADO-15 [
.
Aoo-15 [
-"'"
0)
-"'"
U1
SPC
[
SPC
[
ODIN
[
ODIN
[
STo-ST3 [
NEXT CYCLE
STATUS
STATUS VALID
STO-ST3 [
(HIGH)
ADS [
STATUS VALID
ADS [
TL/EE/9424-37
(FROO
(FROO
FIGURE 4-11. Slave Processor Read Timing
T4
cm
(HIGH)
TLlEE/9424-38
FIGURE 4-10. Slave Processor Write Timing
11
NEXT STATUS
r
u
f\
~ t 1--+-m- u_ _mu-1-:'3- mum m_m· mu__ mu-~l~:- --
c~~ 1
I
TL/EE/9424-39
FIGURE 4-12. SPC Timing
After transferring the last operand to the FPU, the CPU turns OFF the
output driver and holds SPC high with an internal 5 kS1 pullup.
cm [
TL/EE/9424-40
FIGURE 4-13. Relationship of PFS to Clock Cycles
2-155
II)
,...
I
CD
,...
4.0 Device Specifications (Continued)
~
FIRST BUS CYCLE
oN
T1
('I)
1'2
NEXT
13
T4
(J)
Z
......
o
,...
I
CD
,...
~
o
N
('I)
(J)
Z
TL/EE/9424-41
Note: In a transfer of a Read-Modify-Write type operand, this is the Read transfer, displaying RMW Status (Code 1011).
FIGURE 4-14. Relationship Between Last Data Transfer of an Instruction and PFS Pulse of Next Instruction
T1
CTTL [
m[b
/
tpFNS
.1
s~[
X
CODE 1001
TL/EE/9424-42
FIGURE 4-15. Guaranteed Delay, PFS to Non-Sequential Fetch
1
T1
I
11'21···1
1
1
CTTL[
Aoi[
CODE 1001
STI).3 [
-r----------------ir------~------------
PFi[
'NSPF
TL/EE/9424-43
FIGURE 4-16. Guaranteed Delay, Non-Sequential Fetch to PFS
I
13 OATI
I
T40RTI
I
T1
12
13
T4
CTTL[
AOi[
iLO[
TLlEE/9424-44
FIGURE 4-17. Relationship of ILO to First Operand Cycle of an Interlocked Instruction
2-156
z
en
w
N
o
C)
4.0 Device Specifications (Continued)
I
T30RTI
I
T40RTi
I
T1
T2
T3
.
......
T4
0')
......
o
CTTL[
'-
AOS[
en
w
N
oC)
z
.
......
0')
......
U1
-+____________~~I
ILO[ ______________
TL/EE/9424-45
FIGURE 4-18. Relationship of ILO to Last Operand Cycle of an Interlocked Instruction
TLlEE/9424-46
FIGURE 4-19. Relationship of ILO to Any Clock Cycle
OSCIN [
Feu< [
TL/EE/9424-47
FIGURE 4-20. Clock Waveforms
2-157
.
II)
,...
<0
,...
4.0 Device Specifications (Continued)
C!J
(.)
C\I
CW)
VCC
C/)
z
......
.
o
,...
<0
,...
cm[
C!J
(.)
C\I
CW)
C/)
z
Rsn [
RSro [
____________________________
~~--------~
TL/EE/9424-4B
FIGURE 4-21. Power-On Reset
------,..,..~
~JL
S
1----+---tR-STw
RST1 [
RSTO [
ADO-I 5. [
AI 6-23.
SPC
TL/EE/9424-49
FIGURE 4-22. Non-Power-On Reset
Note 1: During Reset the HOLD signal must be kept high.
Note 2: After RSTI is deasserted the first bus cycle will be an instruction fetch at address zero.
CTTL
[ JUlll,JlJlSLJL
~[
INTA [
\\\\\
I~ ~F
--------I)~
I
TLlEE/9424-50
FIGURE 4-23. INT Interrupt Signal Detection
Note 1: Once INT is asserted, it must remain asserted until it is acknowledged.
Note 2: INTA is the Interrupt Acknowledge bus cycle (not a CPU signal). Refer to Section 3.4.1 and Table 3.4.
~[
TL/EE/9424-51
FIGURE 4-24. NMllnterrupt Signal Timing
2·158
zen
w
Appendix A: Instruction Formats
IC I M
B = 00 (Byte)
W = 01 (Word)
7
D = 11 (Double Word)
f = Floating Point Type Field
L = 0 (Long Floating: 64 bits)
Bcond
I
See Sec. 2.3.2 for encodings.
BSR
RET
CXP
RXP
RETI
RETI
SAVE
RESTORE
1
= 0
0010 = Carry Set: C = 1
0011 = Carry Clear: C = 0
=
Higher: L = 1
0101 = Lower or Same: L = 0
0110
= Greater Than: N = 1
0111 = Less or Equal: N = 0
-0000
-0001
-0010
-0011
-0100
-0101
-0110
-0111
15
1000 = Flag Set: F = 1
I I
gen
1001 = Flag Clear: F = 0
1010 = LOwer: L
1011
= 0 and Z = 0
= Higher or Same: L
= 1 or Z
= 1
=
Greater or Equal: N
=
1 or Z
=
1
1111 = (Unconditionally False)
=
-000
-001
-010
-011
AD DO
CMPO
SPR
Scond
1110 = (Unconditionally True)
short
I I
1 1 1
op
10 0 1 01
-1000
-1001
-1010
-1011
-1100
-1101
-1110
-1111
ENTER
EXIT
NOP
WAIT
DIA
FLAG
SVC
BPT
1
01 7 I I
ISh~rt I op
0
11 111
Format 2
1100 = Less Than: N = 0 and Z = 0
1101
.
.....
UI
0
Format 1
cond = Condition Code Field
0100
,.,.....
en
7
reg = General Purpose Register Number
Not Equal: Z
en
w
(BR)
gen, gen 1, gen 2 = General Addressing Mode Field
=
0
I I
111
01
1110
cond
(")
Valid encodings shown with each format.
EOual: Z
.....
0
......
z
FormatO
op = Operation Code
=
=
.
en
F
~
F = 1 (Std. Floating: 32 bits)
0001
(")
Configuration bits in SETCFG instruction:
i = Integer Type Field
0000
,.,
.....
~
NOTATIONS
ACB
MOVO
LPR
-100
-101
-110
Short Immediate value. May contain
quick: Signed 4·bit value, in MOVO, ADDO, CMPO,
ACB.
15
cond: Condition Code (above), in Scond.
I I I
gen
01 7
I
1
~p'
0
11 I 1 I 1 I 1 I 1 1
1
areg: CPU Dedicated Register, in LPR, SPA.
Format 3
0000 = UPSR
CXPD
BICPSR
JUMP
BISPSR
0001 - 0111 = (Reserved)
1000 = FP
1001 = SP
1010 = SB
-0000
-0010
-0100
-0110
ADJSP
JSR
CASE
Trap (UND) on XXX1, 1000
1011 = (Reserved)
1100 = (Reserved)
15
1101 = PSR
I
1110 = INTBASE
1111 = MOD
Options: in String Instructions""""_ _"---"T_-'
I
T
U/W
B
B =
ADD
CMP
BIC
ADDC
MOV
OR
Backward
=
I I I I
gen 1
0
1
7
1
I 1
I I I
op
gen2
1
1
Format 4
T
= Translated
U/W
-1010
-1100
-1110
00: None
01: While Match
11: Until Match
2·159
-0000
-0001
-0010
-0100
-0101
-0110
SUB
AD DR
AND
SUBC
TBIT
XOR
-1000
-1001
-1010
-1100
-1101
-1110
0
B
....
....
C!J
It)
I
CD
Appendix A: Instruction Formats
(Continued)
o
N
C"')
CJ)
Z
.......
....o
....
C!J
I
CD
o
N
C"')
CJ)
Z
Format 9
FormatS
-0000
MOVS
CMPS
-0001
-0010
SETCFG
SKPS
-0011
-0100
BBSTOO
-0101
EXTBLT
-0110
BBOR
-0111
MOVMP
No Operation on 1111
-1000
-1001
-1010
-1011
-1100
-1101
-1110
BITWT
TBITS
BBANO
SBITPS
BBFOR
SBITS
BBXOR
MOVif
LFSR
MOVLF
MOVFL
-000
-001
-010
-011
-100
-101
-110
-111
ROUND
TRUNC
SFSR
FLOOR
7
---I
0
I I II I I I
___ 0 1 1 1 1 1 1 0
TL/EE/9424-53
8 7
i
0
o1 o0
Trap (UND)
Format 10
Always
o
1 1 1 0
1 1 1 1 0
Format 6
ROT
ASH
CBIT
CBITI
Trap (UNO)
LSH
SBIT
SBITI
-0000
-0001
-0010
-0011
-0100
-0101
-0110
-0111
1
NEG
NOT
Trap (UNO)
SUBP
ABS
COM
IBIT
ADDP
-1000
-1001
-1010
-1011
-1100
-1101
-1110
-1111
Format 11
AODf
MOVf
CMPf
(Note 3)
SUBf
NEGf
Trap (UNO)
Trap (UND)
-0000
-0001
-0010
-0011
-0100
-0101
-0110
-0111
OIVf
(Note 1)
Trap (UNO)
Trap (UNO)
MULf
ABSf
Trap (UNO)
Trap (UNO)
-1000
-1001
-1010
-1011
-1100
-1101
-1110
-1111
0
1 1
o0
0
1 1 1 0
111110
Format 7
MOVM
CMPM
INSS
EXTS
MOVXBW
MOVZBW
MOVZiO
MOVXiD
-0000
-0001
-0010
-0011
-0100
-0101
-0110
-0111
MUL
MEl
Trap (UND)
DEI
QUO
REM
MOD
OIV
-1000
-1001
-1010
-1011
-1100
-1101
-1110
-1111
Format 12
(Note 2)
(Note 1)
POLYf
OOTf
SCALBf
LOGBf
Trap (UNO)
Trap (UND)
-0000
-0001
-0010
-0011
-0100
-0101
-0110
-0111
(Note 2)
(Note 1)
Trap (UNO)
Trap (UNO)
(Note 2)
(Note 1)
Trap (UNO)
Trap (UNO)
-1000
-1001
-1010
-1011
-1100
-1101
-1110
-1111
"Instructions with Format 12 are available only when the NS32381 Is used.
o
7
---I
TL/EE/9424-52
Format 8
EXT
-000
INDEX
-001
CVTP
FFS
-010
INS
-011
CHECK
Trap (UNO) on -110and -111
I I I I I I I
_.. 1 0 0 1 1 1 1 0
I
TLlEE/9424-54
-100
-101
Trap (UNO)
Format 13
Always
~=IOiOiOi1i1i 1'1'01
TL/EE/9424-55
2-160
z
en
w
Appendix A: Instruction Formats (Continued)
N
7
Format 14
Trap (UNO)
0
---I xI xI xI 0 I 0 I 1 I 1 I ~ 1
Always
U'
--I
__
1
I I I I I I I
n n n 1 0 1 1 0
TL/EE/9424-60
Format 19
Trap (UNO)
TL/EE/9424-56
N
....
G)
Always
Implied Immediate Encodlngs:
---I
I I I I I I I
o
1
r1
Register Mask, appended to SAVE, ENTER
TL/EE/9424-57
Format 16
o
7
Always
r1
7
0
r2
r3
r4
r5
r6
Register Mask, appended to RESTORE, EXIT
---I
I I I I I I I 1
___ 1 1 0 1 1 '1 1 0
7
TL/EE/9424-58
I
Format 17
Always
0
:offset :
I~ngth -:1
I
Offset/Length Modifier appended to INSS, EXTS
7
0
---I
I I I I I I I 1
___ 1 0 0 0 1 1 1
~
TL/EE/9424-59
Format 18
Trap (UNO)
......
z
o
___ 0 1 0 1 1 1 1 0
Trap (UNO)
Q)
w
7
Trap (UNO)
....
....o•
en
Always
Format 15
Trap (UNO)
oG)
Always
Note 1: Opcode not defined; CPU treats like MOVf. First operand has access class of read; second operand has access class of write; f·field selects 32·bit or
54·bit data.
Note 2: Opcode not defined; CPU treats like ADDf. First operand has access class of read; second operand has access class of read·modify·write. f·field selects
32·bit or 54·bit data.
Note 3: Opcode not defined; CPU treats like CMPf. First operand has access class of read; second operand has access class of read. f·field selects 32·bit or 54·bit
data.
2-161
.
Q)
....
U1
Section 3
Slave Processors
Section 3 Contents
NS32381-15, NS32381-20, NS32381-25, NS32381-30 Floating-Point Units................
NS32081-10, NS32081-15 Floating-Point Units.........................................
3·2
3-3
3-32
z
~National
PRELIMINARY
~ Semiconductor
en
w
N
W
.
CX)
...I.
...I.
U1
......
Z
NS32381-15/NS32381-20/NS32381-25/NS32381-30
Floating-Point Unit
en
w
N
.
W
CX)
...I.
N
General Description
o
The FPU is fabricated with National's advanced double-metal CMOS process. It is available in a 68-pin Pin Grid Array
(PGA) package or 68-pin Plastic package.
The NS32381 is a second generation, CMOS, floating-point
slave processor that is fully software compatible with its
forerunner, the NS32081 FPU. The NS32381 FPU functions
with National's Embedded System Processors™, the
NS32GX32 and the NS32CG16, and with any Series 32000
CPU, from the NS32008 to the NS32532, in a tightly coupled slave configuration. The performance of the NS32381
has been increased over the NS32081 by architecture improvements, hardware enhancements, and higher clock frequencies. Key improvements include the addition of a 32-bit
slave protocol, an early done algorithm to increase CPU/
FPU parallelism, an expanded register set, an automatic
power down feature, expanded math hardware, and additional instructions.
Features
• Compatible with NS32008, NS32016, NS32C016,
NS32032, NS32C032, NS32332, NS32532, NS32CG16
and NS32GX32 microprocessors
• Selectable 16-bit or 32-bit Slave Protocol
• Format compatible with IEEE Standard 754-1985 for
binary floating point arithmetic
• Early done algorithm
• Single (32-bit) and double (64-bit) precision operations
a Eight on-chip (64-bit) data registers
• Automatic power down mode
• Full upward compatibility with existing 32000 software
• High speed double-metal CMOS design
II 68-pin PGA package
• 68-pin plastic package
The NS32381 FPU contains eight 64-bit data registers and
a Floating-Point Status Register (FSR). The FPU executes
20 instructions, and operates on both single and doubleprecision operands. Three separate processors in the
NS32381 manipulate the mantissa, sign, and exponent.
The CPU and NS32381 FPU form a tightly coupled computer cluster, which appears to the user as a single processing
unit. The CPU and FPU communication is handled automatically, and is user transparent.
FPU Block Diagram
Control
Unit
Execution
Unit
Interface
and
storage Unit
CONTROL BUS
TL/EE/91S7-1
FIGURE 1-1
3-3
.....
o
N
Table of Contents
CO
C")
N
C")
C/)
Z
.......
.....
Il)
....
CO
4.0 DEVICE SPECIFICATIONS
1.0 PRODUCT INTRODUCTION
4.1 Pin Descriptions
1.1 IEEE Features Supported-Standard 754-1985
4.1.1 Supplies
1.2 Operand Formats
4.1.2 Input Signals
1.2.1 Normalized Numbers
1.2.2 Zero
4.1.3 Output Signals
N
1.2.3 Reserved Operands
4.1.4 Input/Output Signals
C/)
1.2.4 Integers
4.2 Absolute Maximum Ratings
1.2.5 Memory Representations
4.3 Electrical Characteristics
C")
C")
Z
4.4 Switching Characteristics
2.0 ARCHITECTURAL DESCRIPTION
4.4.1 Definitions
2.1 Programming Model
4.4.2 Timing Tables
2.1.1 Floating-Point Registers
4.4.2.1 Output Signal Propagation Delays for all
CPUs
2.1.2 Floating-Point Status Register (FSR)
2.1.2.1 FSR Mode Control Fields
4.4.2.2 Output Signal Propagation Delays for the
NS32008, NS32016, NS32032 CPUs
2.1.2.2 FSR Status Fields
2.1.2.3 FSR Software Fields (SWF)
4.4.2.3 Output Signal Propagation Delays for the
32-Bit Slave Protocol NS32332 CPU
2.2 Instruction Set
4.4.2.4 Output Signal Propagation Delays for the
32-Bit Slave Protocol NS32532 CPU
2.3 Exceptions
3.0 FUNCTIONAL DESCRIPTION
4.4.2.5 Input Signal Requirements for all CPUs
3.1 Power and Grounding
4.4.2.6 Input Signal Requirements for the
NS32008, NS32016, NS32032 CPUs
3.2 Automatic Power Down Mode
4.4.2.7 Input Signal Requirements for the 32-Bit
Slave Protocol NS32332 CPU
3.3 Clocking
3.4 Resetting
4.4.2.8 Input Signal Requirements for the 32-Bit
Slave Protocol NS32532 CPU
3.5 Bus Operation
4.4.2.9 Clocking Requirements for all CPUs
3.5.1 Bus Cycles
3.5.2 Operand Transfer Sequences
APPENDIX A: NS32381 PERFORMANCE ANALYSIS
3.6 Instruction Protocols
3.6.1 General Protocol Sequence
3.6.2 Early Done Algorithm
3.6.3 Floating-Point Protocols
3-4
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List of Illustrations
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FPU Block Diagram ............................................................................................ 1-1
c".)
Floating-Point Operand Formats ................................................................................. 1-2
...I.
Integer Format .............................................................................•.........•......... 1-3
Register Set ................................•..................................................................2-1
The Floating-Point Status Register ..........•.................................................................... 2-2
Floating-Point Instruction Formats ................................................................................ 2-3
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Recommended Supply Connections ..................•........................................................... 3-1
...I.
Power-On Reset Requirements .................................................................................. 3-2
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General Reset Timing ..............................•...........................................................3-3
System Connection Diagram with the NS32532 CPU ............................................................... 3-4a
System Connection Diagram with the NS32332 CPU ............................................................... 3-4b
System Connection Diagram with the NS32008, NS32016 or NS32032 CPU ......................................•... 3-4c
System Connection Diagram with the NS32CG16 CPU ............................................................. 3-4d
Slave Processor Read Cycle (NS32008, NS32016, NS32032 and NS32332 CPUs) ..................................... 3-5
Slave Processor Read Cycle (NS32532 CPU) ...................................................................... 3-6
Slave Processor Write Cycle (NS32008, NS32016, NS32032 and NS32332 CPUs) ................................•.... 3-7
Slave Processor Write Cycle (NS32532 CPU) ...................................................................... 3-8
ID and Opcode Format 16-Bit Slave Protocol ...................................................................... 3-9
ID and Opcode Format 32-Bit Slave Protocol .................................................................•... 3-1 0
FPU Status Word Format ..................................................................................•...3-11
16-Bit General Slave Instruction Protocol: FPU Actions ............................................................ 3-12
32-Bit General Slave Instruction Protocol: FPU Actions ............................................................ 3-13
68-Pin PGA Package .........•.................................................................................4-1
Timing Specification Standard (Signal Valid After Clock Edge) ........................................................ 4-2
Timing Specification Standard (Signal Valid Before Clock Edge) ...................................................... 4-3
Clock Timing ..................................................................................................4-4
Power-On Reset ...............................................................................................4-5
Non-Power-On Reset ............................................•..............................................4-6
RST Release Timing ............................................................................................4-7
Read Cycle from FPU (NS32008, NS32016, NS32032 CPUs) ........................................................ 4-8
Write Cycle to FPU (NS32008, NS32016, NS32032 CPUs) ........................................................... 4-9
Read Cycle from FPU (NS32332 CPU) ............................•.............................................. 4-10
Write Cycle to FPU (NS32332 CPU) ............................................................................. 4-11
SDN332 Timing (NS32332 CPU) ..........................................................................•..... 4-12
SDN332 (TRAP) Timing (NS32332 CPU) ........................................................................ .4-13
Read Cycle from FPU (NS32532 CPU) ...........................................................................4-14
Write Cycle from FPU (NS32532 CPU) ...........................................................................4-15
SDN532 Timing (NS32532 CPU) ................................................................................4-16
FSSR Timing (NS32532 CPU) ..................................................................................4-17
SPC Pulse from FPU ..........................................................................................4-18
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List of Tables
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Sample F Fields ............................................................................................... 1-1
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Sample E Fields ............................................................................................... 1-2
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Normalized Number Ranges ..........................................................................•.......•.. 1-3
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32-Bit General Slave Instruction Protocol .......................................................................•.. 3-2
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Floating-Point Instruction Protocols ...............................................................................3-3
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1.0 Product Introduction
The NS32381 Floating-Point Unit (FPU) provides high
speed floating-point operations for the Series 32000 family,
and is fabricated using National high-speed CMOS technology. It operates as a slave processor for transparent expansion of the Series 32000 CPU's basic instruction set. The
FPU can also be used with other microprocessors as a peripheral device by using additional TTL and CMOS interface
logic. The NS32381 is compatible with the IEEE FloatingPoint Formats.
exponent. The bias value is 011 ... 112, which is either 127
(single precision) or 1023 (double precision). Thus, the true
exponent can be either positive or negative, as shown in
Table 1-2.
TABLE 1-2. Sample E Fields
1.1 IEEE FEATURES SUPPORTED-STANDARD 754-1985
b) Add, subtract, multiply, divide and compare operations
c) Conversions between different floating-point formats
d) Conversions between floating-point and integer formats
The S bit indicates the sign of the operand. It is 0 for positive and 1 for negative. Floating-point numbers are in signmagnitude form, that is, only the S bit is complemented in
order to change the sign of the represented number.
e) Round floating-point number to integer (round to nearest, round toward negative infinity and round toward
zero, in double or single-precision)
f) Exception signaling and handling (invalid operation, divide by zero, overflow, underflow and inexact)
1.2.1 Normalized Numbers
Normalized numbers are numbers which can be expressed
as floating-point operands, as described above, where the E
field is neither all zeroes nor all ones.
1.2 OPERAND FORMATS
The N32381 FPU operates on two floating-point data
types-single precision (32 bits) and double precision (64
bits). Floating-point instruction mnemonics use the suffix F
(Floating) to select the single precision data type, and the
suffix L (Long Floating) to select the double precision data
type.
The value of a Normalized number can be derived by the
formula:
( -1)S X 2(E-Bias) X (1 + F)
The range of Normalized numbers is given in Table 1-3.
1.2.2 Zero
A floating-point number is divided into three fields, as shown
in Figure 1-2.
There are two representations for zero-positive and negative. Positive zero has all-zero F and E fields, and the S bit is
zero. Negative zero also has all-zero F and E fields, but its S
bit is one.
The F field is the fractional portion of the represented number. In Normalized numbers (Section 1.2.1), the binary point
is assumed to be immediately to the left of the most significant bit of the F field, with an implied 1 bit to the left of the
binary point. Thus, the F field represents values in the range
1.0 ~ x < 2.0.
1.2.3 Reserved Operands
The IEEE Standard for Binary Floating·Point Arithmetic provides for certain exceptional forms of floating-point operands. The NS32381 FPU treats these forms as reserved
operands. The reserved operands are:
• Positive and negative infinity
• Not-a-Number (NaN) values
• Denormalized numbers
Both Infinity and NaN values have al\ ones in their E fields.
Denormalized numbers have all zeroes in their E fields and
non·zero values in their F fields.
The NS32381 FPU causes an Invalid Operation trap (Section 2.1.2.2) if it receives a reserved operand, unless the
operation is simply a move (without conversion). The FPU
does not generate reserved operands as results.
TABLE 1-1. Sample F Fields
Binary Value
1.000 ... 0
1.010 ... 0
1.100 ... 0
1.110 ... 0
Decimal Value
1.000 ... 0
1.250 ... 0
1.500 ... 0
1.750 ... 0
t
Implied Bit
The E field contains an unsigned number that gives the binary exponent of the represented number. The value in the
E field is biased; that is, a constant bias value must be subtracted from the E field value in order to obtain the true
Single Precision
23 22
31 30
Is I
Represented Value
1.5x2- 1 = 0.75
1.5X20 = 1.50
1.5 X 21 = 3.00
Two values of the E field are not exponents. 11 ... 11 signals a reserved operand (Section 1.2.3). 00 ... 00 represents the number zero if the F field is also all zeroes, otherwise it signals a reserved operand.
a) Basic floating-point number formats
FFleld
000 ... 0
010 ... 0
100 ... 0
110 ... 0
FFleld
100 ... 0
100 ... 0
100 ... 0
E Field
011 ... 110
011 ... 111
100 ... 000
E
F
8
23
o
Double Precision
63 62
Is I
o
5251
F
E
11
52
FIGURE 1-2. Floating-Point Operand Formats
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1.0 Product Introduction (Continued)
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TABLE 1-3. Normalized Number Ranges
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Single Precision
2127 x (2 - 2- 23)
= 3.40282346 x 1038
Double Precision
21023 x (2 - 2- 52)
= 1.7976931348623157 x 10308
Least Positive
2- 126
= 1.17549436 X 10- 38
2- 1022
= 2.2250738585072014 X 10- 308
Least Negative
-(2- 126)
= -1.17549436
-(2- 1022)
= -2.2250738585072014 x 10- 308
Most Positive
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tn
Z
x 10- 38
-2 127 X (2 - 2- 23)
= - 3.40282346 x 1038
Most Negative
-2 1023 X (2 - 2- 52)
= -1.7976931348623157 X 10308
Note: The values given are extended one full digit beyond their represented accuracy to help in generating rounding and conversion algorithms.
address. The only exception to this rule is the Immediate
addressing mode, where the operand is held (within the instruction format) with the most significant byte at the lowest
address.
1.2.4 Integers
In addition to performing floating-point arithmetic, the
NS32381 FPU performs conversions between integer and
floating-point data types. Integers are accepted or generated by the FPU as two's complement values of byte (8 bits),
word (16 bits) or double word (32 bits) length.
2.0 Architectural Description
See Figure 1-3 for the Integer Format and Table 1-4 for the
Integer Fields.
n-1
S
2.1 PROGRAMMING MODEL
The Series 32000 architecture includes nine registers that
are implemented on the NS32381 Floating-Point Unit (FPU).
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n-2
I
2.1.1 Floating-Point Registers
There are eight registers (LO-L7) on the NS32381 FPU for
providing high-speed access to floating-point operands.
Each is 64 bits long. A floating-point register is referenced
whenever a floating-point instruction uses the Register addressing mode (Section 2.2.2) for a floating-point operand.
All other Register mode usages (Le., integer operands) refer
to the General Purpose Registers (RO-R7) of the CPU, and
the FPU transfers the operand as if it were in memory.
FIGURE 1-3. Integer Format
TABLE 1-4. Integer Fields
S
Value
Name
0
I
Positive Integer
1
1- 2 n
Negative Integer
Note: These registers are all upward compatible with the 32-bit NS320Bl
registers, (FO-F7), such that when the Register addressing mode is
specified for a double precision (64-bit) operand, a pair of 32·bit regIsters holds the operand. The programmer specifies the even register
of the pair which contains the least significant half of the operand and
the next consecutive register contains the most significant half.
Note: n represents the number of bits In the word, B for byte, 16 for word
and 32 for double-word.
1.2.5 Memory Representations
The NS32381 FPU does not directly access memory. However, it is cooperatively involved in the execution of a set of
two-address instructions with its Series 32000 Family CPU.
The CPU determines the representation of operands in
memory.
2.1.2 Floating-Point Status Register (FSR)
The Floating-Point Status Register (FSR) selects operating
modes and records any exceptional conditions encountered
during execution of a floating-point operation. Figure 2-2
shows the format of the FSR.
In the Series 32000 family of CPUs, operands are stored in
memory with the least significant byte at the lowest byte
\+-~-- 64--=1-+
f4--32-..f
I
F'SR
I
LSDW ---. least significant double word
t.fSDW ---. most significant double word
·1·
32
t.fSDW
t.fSDW
t.fSDW
t.fSDW
t.fSDW
t.fSDW
t.fSDW
t.fSDW
n /LO
Ll
F'37L2
L3
F'5 /L4
L5
F'77L6
L7
32
F'O/LO LSDW
Ll LSDW
F'2 /L2 LSDW
L3 LSDW
F'4 /L4 LSDW
L5 LSDW
F'67L6 LSDW
L7 LSDW
TL/EE/9157 -36
FIGURE 2-1. Register Set
31
17
9876543210
16 15
IReserved IRt.fB I
I SWf
TLlEE/9157-37
FIGURE 2-2. The Floating-Point Status Register
3-8
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2.0 Architectural Description
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(Continued)
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2.1.2.1 FSR Mode COJ;ltrol Fields
010 Overflow. A result (either floating-point or integer) of a
floating-point instruction is too great in magnitude to
be held in the format of the destination operand. Note
that rounding, as well as calculations, can cause this
condition.
The FSR mode control fields select FPU operation modes.
The meanings of the FSR mode control bits are given below.
Rounding Mode (RM): Bits 7 and 8. This field selects the
rounding method. Floating-point results are rounded whenever they cannot be exactly represented. The rounding
modes are:
011
00 Round to nearest value. The value which is nearest to
the exact result is returned. If the result is exactly halfway between the two nearest values the even value
(LSB = 0) is returned.
01
100 Illegal Instruction. Any instruction forms not included
in the NS32381 Instruction Set are detected by the
FPU as being illegal.
101 Invalid Operation. One of the floating-point operands
of a floating-point instruction is a Reserved operand,
or an attempt has been made to divide zero by zero
using the DIVf instruction.
Round toward zero. The nearest value which is closer
to zero or equal to the exact result is returned.
10 Round toward positive infinity. The nearest value which
is greater than or equal to the exact result is returned.
11
Divide by zero. An attempt has been made to divide a
. non-zero floating-point number by zero. Dividing zero
by zero is considered an Invalid Operation instead
(below).
110 Inexact Result. The result (either floating-point or integer) of a floating-point instruction cannot be represented exactly in the format of the destination operand, and a rounding step must alter it to fit. This condition is always reported in the TT field and IF bit unless
any other exceptional condition has occurred in the
same instruction. In this case, the TT field always contains the code for the other exception and the IF bit is
not altered. A trap is caused by this condition only if
the lEN bit is set; otherwise the result is rounded and
delivered, and no trap occurs.
Round toward negative infinity. The nearest value
which is less than or equal to the exact result is returned.
Underflow Trap Enable (UEN): Bit 3. If this bit is set, the
FPU requests a trap whenever a result is too small in absolute value to be represented as a normalized number. If it is
not set, any underflow condition returns a result of exactly
zero.
Inexact Result Trap Enable (lEN): Bit 5. If this bit is set,
the FPU requests a trap whenever the result of an operation
cannot be represented exactly in the operand format of the
destination. If it is not set, the result is rounded according to
the selected rounding mode.
111
(Reserved for future use.)
Underflow Flag (UF): Bit 4. This bit is set by the FPU whenever a result is too small in absolute value to be represented
as a normalized number. Its function is not affected by the
state of the UEN bit. The UF bit is cleared only by writing a
zero into it with the Load FSR instruction or by a hardware
reset.
2.1.2.2 FSR Status Fields
The FSR Status Fields record exceptional conditions encountered during floating-point data processing. The meanings of the FSR status bits are given below:
Inexact Result Flag (IF): Bit 6. This bit is set by the FPU
whenever the result of an operation must be rounded to fit
within the destination format. The IF bit is set only if no other
error has occurred. It is cleared only by writing a zero into it
with the Load FSR instruction or by a hardware reset.
Trap Type (TT): bits 0-2. This 3-bit field records any exceptional condition detected by a floating-point instruction. The
TT field is loaded with zero whenever any floating-point instruction except LFSR or SFSR completes without encountering an exceptional condition. It is also set to zero by a
hardware reset or by writing zero into it with the Load FSR
(LFSR) instruction. Underflow and Inexact Result are always
reported in the TT field, regardless of the settings of the
UEN and lEN bits.
Register Modify Bit (RMB): Bit 16. This bit is set by the
FPU whenever writing to a floating point data register. The
RMB bit is cleared only by writing a zero with the LFSR
instruction or by a hardware reset. This bit can be used in
context switching to determine whether the FPU registers
should be saved.
000 No exceptional condition occurred.
001 Underflow. A non-zero floating-point result is too small
in magnitude to be represented as a normalized floating-point number in the format of the destination operand. This condition is always reported in the TT field
and UF bit, but causes a trap only if the UEN bit is set.
If the UEN bit is not set, a result of Positive Zero is
produced, and no trap occurs.
2.1.2.3 FSR Software Field (SWF)
Bits 9-15 of the FSR hold and display any information written to them (using the LFSR and SFSR instructions), but are
not otherwise used by FPU hardware. They are reserved for
use with NSC floating-point extension software.
3-9
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2.0 Architectural Description
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2.2 INSTRUCTION SET
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2.2.1 Floating-Point Instruction Set
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(Continued)
An operand designation (gen1, gen2) indicates a choice of
addressing mode expressions. This choice affects the binary pattern in the corresponding gen1 or gen2 field of the
instruction format. Refer to Table 2-1 for the options available and their patterns .
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This section describes the floating-point instructions executed by the FPU in conjunction with the CPU. These instructions form a subset of the Series 32000® instruction set and
take 9, 11, and 12 encoding formats. A list of all the Series
32000 instructions as well as details on their formats and
addressing modes can be found in the appropriate CPU
data sheets.
Further details of the exact operations performed by each
instruction are found in the Series 32000 Instruction Set
Reference Manual.
Movement and Conversion
Certain notations in the following instruction description tables serve to relate the assembly language form of each
instruction to its binary format in Figure 2-3.
The following instructions move the gen1 operand to the
gen2 operand, leaving the gen1 operand intact.
Format Op
Instruction
11
0001 MOVf
gen1,gen2
Format 9
I
I
I
I I
gen2
op
II
f
I
i
ar
;. 0
I
0
I I I I I I 1
0 1 1 1 1 1 0i
OPERATION WORD
9
010 MOVLF
gen1, gen2
Move, converting
from double
precision to
single precision.
9
011
gen1, gen2
Move, converting
from single
precision to
double
precision.
9
000 MOVif
gen1, gen2
Move, converting
from any integer
type to any
floating-point
type.
9
100 ROUNDfi
gen1, gen2
Move, converting
from floatingpoint to the
nearest integer.
9
101
TRUNCfi
gen1, gen2
Move, converting
from floatingpoint to the
nearest integer
closer to zero.
9
111
FLOORfi
gen1, gen2
Move, converting
from floatingpoint to the
largest integer
less than or
equal to its
value.
10 BYTE
TL/EE/9157 -5
MOVFL
Format 11
23
I
16 15
1 I
I
gen2
I
•
I
I
op
al7 I
I I I I I I
f 1\ 1
0 1 1 1 1 1 0i
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OPERATION WORD
0
I
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TL/EE/9157 -6
Format 12
23
iii
gen 2
Iiiop i I0 If i1 i1 1 i1i 1i 1 iii
1 0
TLlEE/9157-7
FIGURE 2-3. Floating-Point Instruction Formats
The Format column indicates which of the three formats in
Figure 2-3 represents each instruction.
The Op column indicates the binary pattern for the field
called "op" in the applicable format.
The Instruction column gives the form of each instruction as
it appears in assembly language. The form consists of an
instruction mnemonic in upper case, with one or more suffixes (i or f) indicating data types, followed by a list of operands (gen1, gen2).
An i suffix on an instruction mnemonic indicates a choice of
integer data types. This choice affects the binary pattern in
the i field of the corresponding instruction format as follows:
Suffix i
B
W
D
Data Type
Byte
Word
Double Word
Note: The MOVLF instruction f bit must be 1 and the i field must be 10.
The MOVFL instruction f bit must be 0 and the i field must be 11.
Arithmetic Operations
I Field
The following instructions perform floating-point arithmetic
operations on the gen1 and gen2 operands, leaving the result in the gen2 operand.
00
01
11
Note: POLY and DOT use the additional third implied operand.
POLY and DOT put their result to LO/FO register and not to GEN2.
An f suffix on an instruction mnemonic indicates a choice of
floating-point data types. This choice affects the setting of
the f bit of the corresponding instruction format as follows:
Suffix f
F
L
Data Type
Single Precision
Double Precision (Long)
Description
Move without
conversion
Format
11
Op
0000
Instruction
ADDf gen1,gen2
f Bit
1
11
0100
SUBf
gen1,gen2
Subtract gen1
from gen2.
o
11
1100
MULf
gen1,gen2
Multiply gen2 by
gen1.
3-10
Description
Add gen1 to gen2.
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2.0 Architectural Description
Format Op
(N)
Instruction
en
Description
Rounding
11
1000 DIVf
gen1, gen2 Divide gen2 by gen1.
11
0101 NEGf
gen1, gen2 Move negative of
gen1 to gen2.
11
1101 ASSf
gen1, gen2 Move absolute value
of gen1 to gen2.
12
0100 SCAlSf gen1, gen2 Move gen2*2g en1 to
gen2, for integral
values of gen1
without computing
2g en1 .
(N)
12
0101 lOG Sf gen1, gen2 Move the unbiased
exponentofgen1 to
gen2.
(N)
12
0011 DOTf
gen1, gen2 Move (gen1*gen2)
+ lO to lO.(*)
(N)
12
0010 POLYf
gen1, gen2 Move (lO*gen1)
gen2 to lO.(*)
The FPU supports all IEEE rounding options: Round toward
nearest value or even significant if a tie. Round toward zero,
Round toward positive infinity and Round toward negative
infinity.
Upon detecting an exceptional condition in executing a
floating-point instruction, the FPU requests a TRAP by pulsing the SPC line for one clock cycle, pulsing the SDN332
line for two and a half clock cycles and pulsing the FSSR
line for one clock cycle. (The user will connect the correct
lines according to the CPU being used).
+
(N): Indicates NEW instruction.
In addition, the FPU sets the Q bit in the status word register. The CPU responds by reading the status word register
(refer to Section 3.6.1 for its format) while applying status
h'E (transferring status word) on the status lines. A trapped
instruction returns no result (even if the destination is FPU
register) and does not affect the CPU PSR. The FPU records exceptional cause in the trap type (IT) field of the FSR.
If an illegal opcode is detected, the FPU sets the TS bit in
the slave processor status word register, indicating a trap
(UNO).
(·)The third impled operand used by these instructions can be either FO or
LO depending on whether 'floating' or 'long' data type is specified in the
opcode.
Comparison
The Compare instruction compares two floating-point values, sending the result to the CPU PSR Z and N bits for use
as condition codes. See Figure 3-11. The Z bit is set if the
gen1 and gen2 operands are equal; it is cleared otherwise.
The N bit is set if the gen1 operand is greater than the gen2
operand; it is cleared otherwise. The CPU PSR l bit is unconditionally cleared. Positive and negative zero are considered equal.
Op
11
0010
3.0 Functional Description
3.1 POWER AND GROUNDING
Description
Instruction
CMPf
gen1, gen2
The NS32381 requires a single 5V power supply, applied on
the Vee pins. These pins should be connected together by
a power (Ved plane on the printed circuit board. See Figure
3-1.
Compare gen1
to gen2.
Floating-Point Status Register Access
The grounding connections are made on the GND pins.
These pins should be connected together by a ground
(GND) plane on the printed circuit board. See Figure 3-1.
The following instructions load and store the FSR as a 32bit integer.
Format
Op
9
001
110
9
Description
Instruction
lFSR
SFSR
gen1
gen2
load FSR
Store FSR
Note: All instructions support all of the NS32000 family data formats (for
external operands) and all addressing modes are supported.
+5V
+5V
NS32381
TL/EE/9157-8
PGAPackage
TL/EE/9157 -43
PLCC Package
FIGURE 3-1. Recommended Supply Connections
3-11
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2.3 EXCEPTIONS
The FPU supports five types of exceptions: Invalid operation, Division by zero, Overflow, Underflow and Inexact Result. When an exception occurs, the FPU mayor may not
generate a trap depending upon the bit setting in the FSR
Register. The user can disable the Inexact Result and the
Underflow traps. If an undefined Floating-Point instruction is
passed to the FPU an Illegal Instruction trap will occur. The
user can't disable trap on Illegal Instruction.
Notes:
Format
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3.0 Functional Description (Continued)
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FIGURE 3-2. Power-On Reset Requirements
3.2 AUTOMATIC POWER DOWN MODE
either one byte (8 bits), one word (16 bits) or one double
word (32 bits) to or from the FPU. During all bus cycles, the
SPC line is driven by the CPU as an active low data strobe,
and the FPU monitors pins STO-ST3 to keep track of the
sequence (protocol) established for the instruction being executed. This is necessary in a virtual memory environment,
allowing the FPU to retry an aborted instruction.
The NS32381 supports a power down mode in which the
device consumes only 10% of its original power at 30 MHz.
The NS32381 enters the power down mode (internal clocks
are stopped with phase two high) if it does not receive an
SPC pulse from the CPU within 256 clocks.
The FPU exits the power down mode and returns to normal
operation after it receives an SPC from the CPU. There is no
extra delay caused by the FPU being in the power down
mode.
3.5.1 Bus Cycles
A bus cycle is initiated by the CPU, which asserts the proper
status on (STO-ST3) and pulses SPC low. The status lines
are sampled by the FPU on the leading (falling) edge of the
SPC pulse except for the 32532 CPU. When used with the
32532 CPU, the status lines are sampled on the rising edge
of ClK in the T2 state. If the transfer is from the FPU (a
slave processor read cycle), the FPU asserts data on the
data bus for the duration of the SPC pulse. If the transfer is
to the FPU (a slave processor write cycle), the FPU latches
data from the data bus on the trailing (rising) edge of the
SPC pulse. Figures 3-5, 3-6, 3-1 and 3-8 illustrate these
sequences.
3.3 CLOCKING
The NS32381 FPU requires a single-phase TIL clock input
on its ClK pin (pin A8). Different Clock sources can be used
to provide the ClK signal depending on the application. For
example, it can come from the 8ClK of the NS32532 CPU.
It can also come from the CTIl pin of the NS32C201 Timing Control Unit, if it is required.
3.4 RESETTING
The RST pin serves as a reset for on-chip logic. The FPU
may be reset at any time by pulling the RST pin low for at
least 64 clock cycles. Upon detecting a reset, the FPU terminates instruction processing, resets its internal logic, and
clears the FSR to all zeroes.
The direction of the transfer and the role of the bidirectional
SPC line are determined by the instruction protocol being
performed. SPC is always driven by the CPU during slave
processor bus cycles. Protocol sequences for each instruction are given in Section 3.6.
On application of power, RST must be held low for at least
30 ,..,s after Vee is stable. This ensures that all on-chip voltages are completely stable before operation. See Figures
3-2 and 3-3.
CLK
3.5.2 Operand Transfer Sequences
An operand is transferred in one or more bus cycles. For the
16-8it Slave Protocol a 1-byte operand is transferred on the
least significant byte of the data bus (00-07). A 2-byte operand is transferred on the entire bus. A 4-byte or 8-byte
operand is transferred in consecutive bus cycles, least significant word first.
JLrLSLILfl---I<1:64 CLOCK--..l
- - -.._I'ftft'm'f'!'"
m
rI
CYCLES
I
For the 32-8it Slave Protocol a 4-byte operand is transferred on the entire data bus in a single bus cycle and an
8-byte 'operand is transferred in two consecutive bus cycles
with the most significant byte transferred on data bits (0007). The complete operand transfer of bytes 80-87 where
80 is the least significant byte would appear on the data bus
as 84, 85, 86, 87 followed by 80, 81, 82, 83 in the second
bus cycle.
TL/EE/9157 -10
FIGURE 3-3. General Reset Timing
3.5 BUS OPERATION
Instructions and operands are passed to the NS32381 FPU
with slave processor bus cycles. Each bus cycle transfers
3-12
z
3.0 Functional Description
(Continued)
en
w
+5V
Q)
N
.
W
..--
_+5V
.....
.....
U1
: 10k
.:
..~1k
,,10k
.
1k
~
NOE
SPC
PSO
.
Q)
.....
PS1
N
Q
....
) DO-D31
I'
~
STO
STO
(NS32381)
CPU
STI
STI
FPU
ST2
ST2
ST4
T
N
~
(NS32532)
SDN
w
W
DDIN
32-BIT
DATA BUS
.A
00-D31
zen
1k
SPC
~
DDIN
......
ST3
....
SDN532
FSSR
FSSR
BClK
ClK
RST
RESERVED
RESERVED
RESERVED
~
~
~
RST
I
-==
TL/EE/9157-38
FIGURE 3-4a. System Connection Diagram with the NS32532 CPU
+5V
+5V
+5V
4
.
"
."
NOE
PSO
:~1k
"1k
10k
~
SPC
PS1
SPC
.A
ADO-AD31
32-BIT
DATA BUS
....
00-D31
't
I'
(NS32332)
STO
STO
(NS32381)
CPU
STI
r'
STI
FPU
ST2
r'
ST2
..
ST3
~
ST3
RESERVED
~
~
RESERVED
~
RESERVED
DT/SDONE
SDN332
"
RST
RSTjill
1
RSTO
SYSTEM ...
RESET
I
II
ClK
cm
"'7
Rsn
NS32C201
TCU
TL/EE/9157-39
FIGURE 3-4b. System Connection Diagram with the NS32332 CPU
3·13
C) .-----------------------------------------------------------------------------------~
N
C;
3.0 Functional Description (Continued)
Cf)
N
+5V
Cf)
en
)
Z
......
II)
10k
.....
.....•
co
-
~- ~
~
Cf)
N
pso
NOE
Cf)
en
z
PSI
1
SPC
ll'/SPC
16-BIT
DATA BUS
A
ADO-ADI5
I\.
00-015
'I
Y
(NS32032)
STO
STO
(NS32381)
(NS32016)
ST1
STI
rpu
(NS32008)
---+
ST2
.......-.. ST3
CPU
-:.=
RESERVED
-
RST
RST/ABT
r
--'"
I
~
RESERVED
!!.-
ClK
-==
cm
RSTO
SYSTEM ...
RESET '
ML.
RESERVED
Rsn
NS32C201
TCU
TL/EE/9157-40
FIGURE 3-4c. System Connection Diagram with the NS32008, NS32016 or NS32032 CPU
+5V
+5V
)
:= 10k
• lk
~ ~
PSO
NOE
SPC
A
16-BIT
DATA BUS
I\.
00-015
'I
"
STO
STI
CPU
---+
.......-..
STO
STI
(NS32381)
ST2
rpu
ST3
-:.=
RSTI
.1
SPC
ADO-ADI5
(NS32CGI6)
PSI
RESERVED
-
..
cm
RESERVED
_
.
RST
RESERVED
ClK
SYSTEM
RESET
ML.
~
~
-:.=
TL/EE/9157-41
FIGURE 3-4d. System Connection Diagram with the NS32CG16 CPU
3-14
z
3.0 Functional Description
en
w
I\)
w
C)
(Continued)
STO,ST1 _ _,,",_ _ _V_AL'"'I"IO_ _ _
.
-""
-""
U1
.J~
m ___________~NDTE11
......
z
~
en
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I\)
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C)
.
-""
I\)
00-015 - - - -
---
..I>- --
--<",___
---
o
VA_L_IO_F_RO_M_F_PU_ _
TLlEE/9157-12
Note 1: FPU samples CPU status here.
FIGURE 3·5. Slave Processor Read Cycle (NS3200B, NS32016, NS32032 and NS32332 CPUs)
r
Ti
elK
+
(NOTE 1)
STO-
ST4
1U11Z7IZx'--_ _---JXll//II/
JJZ!!IZ/
\'--_ _--'1
OO-D31---------------~<~______________
_J»----------
Note 1: FPU samples CPU status here.
FIGURE 3·6. Slave Processor Read Cycle (NS32532 CPU)
3-15
TL/EE/9157-13
o
N
,....
•
CO
3.0 Functional Description (Continued)
C")
N
C")
en
z
.......
it)
,....
,....•
STD. STI
VALID
- - - - - - - - - - , 1 (NOTE 1)
CO
C")
N
m
C")
(NOTE 2)
en
z
VALID FROM CPU
00-015 - - - - - -
TL/EE/9157-14
Note 1: FPU samples CPU status here.
Note 2: FPU samples data bus here.
FIGURE 3-7. Slave Processor Write Cycle (NS32008, NS32016, NS32032 and NS32332 CPU)
r
T2---1
TI
elK
~
STO-ST3
ODIN
(NOTE I)
71711///1X--~X!-"Z"""'71""""'Z/""""'Z~71""""71~Z
//7I///!IY
'<7I//71Z/1
\"---~t
(NOTE 2)
OO-D31----------------------------«~_____________J)~-------------TL/EE/9157-15
Note 1: FPU samples CPU status here.
Note 2: FPU samples data bus here.
FIGURE 3-8. Slave Processor Write Cycle (NS32532 CPU)
3-16
z
3.0 Functional Description
en
w
(Continued)
N
W
CD
3.6 INSTRUCTION PROTOCOLS
2) It specifies which Slave Processor will execute it.
3.6.1 General Protocol Sequences
3) It determines the format of the following Operation Word
of the instruction.
The NS32381 supports both the 16-bit and 32-bit General
Slave protocol sequences. See Tables 3-1,3-2 and Figures
3-12,3-13 respectively.
Upon receiving a slave processor instruction, the CPU initiates a sequence outlined in either Table 3-1 or 3-2, depending on the PSO and PS1, to allow for the 16-bit or 32-bit
slave protocol. The NS32008, NS32016, NS32C016,
NS32032, NS32C032 and NS32CG 16 all communicate with
the NS32381 using the 16-bit Slave Protocol. The NS32332,
NS32532 and NS32GX32 CPUs communicate with the
NS32381 using a 32-bit Slave Protocol; a different version is
provided for each CPU.
Slave Processor instructions have a three-byte Basic Instruction field, consisting of an ID byte followed by an Operation Word. See Figure 3-9 for the ID and Opcode format
16-bit Slave Protocol and Figure 3-10 for the ID and Opcode
Format 32-bit Slave Protocol. The ID Byte has three functions:
...I.
•
...I.
U'I
......
Z
en
w
N
W
CD
...I.
•
N
o
1) It identifies the instruction to the CPU as being a Slave
Processor instruction.
TABLE 3-1. 16-Blt General Slave Instruction Protocol
Step
Status
1
2
3
4
ID (1111)
OP (1101)
OP (1101)
5
6
7
ST(1110)
OP (1101)
Action
CPU sends ID Byte
CPU sends Operation Word
CPU sends required operands (if any)
Slaves starts execution (CPU prefetches)
Slave pulses SPC low
CPU Reads Status Word
CPU Reads Result (if destination is
memory and if no TRAP occurred)
TABLE 3-2. 32-Blt General Slave Instruction Protocol
Step
Status
Action
1
ID(1111)
OP (1101)
CPU sends ID and Operation Word
CPU sends required operands (if any)
Slaves starts execution (CPU prefetches)
Slave signals DONE or TRAP or CMPf
CPU Reads Status Word (If TRAP was signaled
or a CMPf instruction was executed)
CPU Reads Result (if destination is memory and
if no TRAP occurred)
2
3
4
5
ST(1110)
6
OP (1101)
TABLE 3-3. Floating-Point Instruction Protocols
Mnemonic
ADDf
SUBf
MULf
DIVf
MOVf
ABSf
NEGf
CMPf
FLOORfi
TRUNCfi
ROUNDfi
MOVFL
MOVLF
MOVif
LFSR
SFSR
SCALBf
LOGBf
DOTf
POLYf
Operand 1
Class
Operand 2
Class
Operand 1
Issued
Operand 2
Issued
read.f
read.f
read.f
read.f
read.f
read.f
read.f
read.f
read.f
read.f
read.f
read.F
read.L
read.i
read.D
rmw.f
rmw.f
rmw.f
rmw.f
write.f
write.f
write.f
read.f
write.i
write.i
write.i
write.L
write.F
write.f
f
f
f
f
f
f
f
f
f
f
f
F
L
i
D
f
f
f
f
N/A
write.D
rmw.f
write.f
read.f
read.f
read.f
read.f
read.f
read.f
N/A
N/A
N/A
N/A
N/A
fto Op.
fto Op.
fto Op.
fto Op.
fto Op.
fto Op.
fto Op.
2
2
2
2
2
2
2
f
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
itoOp.2
itoOp.2
itoOp.2
LtoOp.2
FtoOp.2
fto Op. 2
f
f
f
f
f
Returned Value
Type and Destination
N/A
f
f
N/A
Dto Op. 2
fto Op.2
fto Op.2
*f to FO/LO
*f to FO/LO
= Double Word
= Integer size (B, W, D) specified in mnemonic.
f = Floating-Point type (F, L) specified in mnemonic.
N/A = Not Applicable to this Instruction.
D
I
·The "returned value" can go to either FO or LO depending on the "f" bit in the opcode, I.e., whether "floating" or "long" data type is used.
3-17
PSR Bits
Affected
none
none
none
none
none
none
none
N,Z,L
none
none
none
none
none
none
none
none
none
none
none
none
EI
o
N
•
,..
CO
C")
N
r-------------------------------------------------------------------~
3.0 Functional Description (Continued)
7
o
tion and for the CPU to continue with the 16-Bit Slave Protocol by reading the FPU's Status Word Register.
C")
U)
Z
......
II)
For the 32-bit Slave Protocol, upon completion of the instruction, the FPU will signal the CPU by pulsing either
SONXXX or FSSR (Force Slave Status Read).
10 Byte
,..
,..•
15
CO
7
I OPCOOE (low)
C")
0
A half clock cycle SON332 pulse with a NS32332 CPU, or a
one clock cycle SON532 pulse with a NS32532 or
NS32GX32 CPU, indicates a valid completion of the instruction and that there is no need for the CPU to read its Status
Word Register.
OPCOOE (high)
N
C")
Byte 1
Byte 0
Operation Word
FIGURE 3·9. 10 and OPCODE Format
16·Blt Slave Protocol
U)
Z
31
23
10
15
7
But if there is a need for the CPU to read FPU's Status Word
Register, a two and a half clock cycle SON332 (from
NS32332) or a one clock cycle FSSR pulse (from NS32532
or NS32GX32) will be issued instead.
0
IOPCOOE (low)IOPCOOE (high)1 XXXXXXXX
I
In all cases for both the 16-Bit and 32-Bit Slave Protocols
the CPU will use SPC to read the Status Word from the
FPU, while applying status code (1110). This word has the
format shown in Figure 3-11. If the Q bit ("Quit", Bit 0) is set,
this indicates that an error (TRAP) has been detected by the
FPU. The CPU will not continue the protocol, but will immediately trap through the Slave vector in the Interrupt Table. If
the instruction being performed is CMPf (Section 2.2.3) and
the Q bit is not set, the CPU loads Processor Status Register (PSR) bits N, Z and L from the corresponding bits in the
FPU Status Word. The FPU always sets the L bit to zero.
Byte 3
Byte 2
Byte 1
Byte 0
FIGURE 3·10. 10 and OPCODE Format
32·Blt Slave Protocol
For the 16-bit Slave Protocol the CPU applies Status Code
1111 (Broadcast 10), and sends the 10 Byte on the least
significant half of the Oata Bus (00-07). The CPU next
sends the Operation Word while applying Status Code 1101
(Transfer Slave Operand). The Operation Word is swapped
on the Oata Bus; that is, bits 0-7 appear on pins 08-015,
and bits 8-15 appear on pins 00-07.
The last step will be for the CPU to read the result, provided
there are no errors and the results destination is in memory.
Here again the CPU uses SPC to read the result from the
FPU and transfer it to its destination. These Read cycles
from the FPU are performed by the CPU while applying
Status Code 1101 (Transfer Slave Operand).
For the 32-bit Slave Protocol the CPU applies Status Code
1111 and sends the 10 Byte (different 10 for each format) in
byte 3 (024-031) and the Operation Word in bytes 1 and 2
in a single double word transfer. The Operation Word is
swapped such that OPCOOE low appears on byte 2 (016023) and OPCOOE high appears on byte 1 (08-015). Byte
o (00-07) is not used.
15
All Slave Processors input and decode the data from these
transfers. The Slave Processor selected by the 10 Byte is
activated and from this point on the CPU is communicating
with it only. If any other slave protocol is in progress (e.g., an
aborted Slave instruction), this transfer cancels it. Both the
CPU and FPU are aware of the number and size of the
operands at this point.
ZERO
Bit
ITSI
7
ZERO
0
INlzlolololLlolJ
Description
(0)
Q:
Set to "1" if an FPU TRAP (error) occurred.
Using the Addressing Mode fields within the Operation
Word, the CPU starts fetching operands and issuing them to
the FPU. To do so, it references any Addressing Mode extensions appended to the FPU instruction. Since the CPU is
solely responsible for memory accesses, these extensions
are not sent to the Slave Processor. The Status Code applied is 1101 (Transfer Slave Processor Operand).
(2)
(6)
L:
Z:
Cleared to "0" by the FPU.
(7)
N:
Set to "1" if the second operand is less than
the first operand. Otherwise it is cleared to
After the CPU has issued the last operand, the FPU starts
~actual execution of the instruction. A one clock cycle
SPC pulse is used to indicate the completion of the instruc-
(15)
TS:
Cleared to '0" by a valid CMPf.
Set to "1" if the second operand is equal to
the first operand. Otherwise it is cleared to
"0".
"0".
3-18
Set to "1" if the TRAP is (UNO) and cleared to
"0" if the TRAP is (FPU).
FIGURE 3·11. FPU Status Word Format
z
3.0 Functional Description
en
eN
(Continued)
N
eN
.
C)
.....
.....
U1
.......
z
en
eN
N
eN
C)
.....
N•
C
READ OPERAND
(BUS STATUS = 1101)
GO
TL/EE/9157-16
FIGURE 3·12. 16·Bit General Slave Instruction Protocol: FPU Actions
READ OPERAND
(BUS STATUS = 1101)
Pulse Active
-1
SDN332 for 2 clock
__
or
SDN532 for 1 clock (DONE)
TL/EE/9157-17
FIGURE 3·13. 32·Bit General Slave Instruction Protocol: FPU Actions
3-19
C)
N
....•
co
(f)
N
(f)
U)
Z
......
Lt)
........•
co
(f)
N
(f)
U)
Z
r------------------------------------------------------------------------------------,
3.0 Functional Description
(Continued)
3.6.2 Early Done Algorithm
4.1.2 Input Signals
ClK
Clock: TIL-level clock signal.
The NS32381 has the ability to modify the General Slave
protocol sequences and to boost the performance of the
FPU by 20% to 40%. This is called the Early Done Algorithm .
Data Direction In: Active low. Status signal indicating the direction of data transfers during a
bus cycle .
Early Done is defined by the fact that the destination of an
instruction is an FPU register and that the instruction and
range of operands cannot generate a TRAP (error). When
these conditions are met the FPU will send a SDNXXX or
SPC pulse after receiving all of the operands from the CPU
and before executing the instruction. Hence this becomes
an early done as compared to the General Slave Protocols.
STO-ST3
1100- Reserved
1101- Transferring Operation Word or Operand
1110- Reading Status Word
1111- Broadcasting Slave ID
In the case of the 16-bit Slave Protocol in which the CPU
always reads the slave status word, the FPU will force all
zeroes to be read. The CPU can then send the next instruction to the FPU and save the general protocol overhead.
The FPU will start the new instruction immediately after finishing the previous instruction.
Note: The NS32332 generates four status lines and the
NS32532 generates five. The user should connect the
status lines as shown below:
SFSR, CMPF and CMPl do not generate an Early Done.
3.6.3 Floating-Point Protocols
Table 3-3 gives the protocols followed for each floatingpoint instruction. The instructions are referenced by their
mnemonics. For the bit encodings of each instruction, see
section 2.2.3.
The Operand Class columns give the Access Classes for
each general operand, defining how the addressing modes
are interpreted by the CPU (see Series 32000 Instruction
Set Reference Manual).
The Operand Issued columns show the sizes of the operands issued to the Floating-Point Unit by the CPU. "D" indicates a 32-bit Double Word. "i" indicates that the instruction
specifies an integer size for the operand (B = Byte, W =
Word, D = Double Word). "f" indicates that the instruction
specifies a floating-point size for the operand (F = 32-bit
Standard Floating, l = 64-bit long Floating).
RST
NOE
PSO, PS1
NS32332
NS32532
NS32381
STO
STO
STO
ST1
ST1
ST1
ST2
ST2
ST2
ST3
ST3
ST4
Reset: Active low. Resets the last operation
and clears the FSR register.
New Opcode Enable: Active high. This signal
enables the new opcodes available in the
NS32381.
Protocol Select: Selects the slave protocol to
be used. PSO is the least significant and rightmost bit.
OO-Selects 16-bit protocol.
01-Selects 32-bit protocol for NS32332.
10-Reserved.
11-Selects 32-bit protocol for NS32532.
4.1.3 Output Signals
SDN332
The Returned Value Type and Destination column gives the
size of any returned value and where the CPU places it. The
PSR Bits Affected column indicates which PSR bits, if any,
are updated from the FPU Status Word (Figure 3-11).
Any operand indicated as being of type "f" will not cause a
transfer if the Register addressing mode is specified, because the Floating-Point Registers are physically on the
Floating-Point Unit and are therefore available without CPU
assistance.
SDN532
4.0 Device Specifications
4.1 PIN DESCRIPTIONS
4.1.1 Supplies
The following is a brief description of all NS32381 pins.
Vee
GND
Status: Bus cycle status code from CPU. STO is
the least significant and rightmost bit.
Power: + 5V positive supply.
Ground: Ground reference for both on-Chip logic and drivers connected to output pins.
Slave Done 332: Active low. This signal is for
use with the NS32332 CPU only. If held active
for a half clock cycle and released this pin indicates the successful completion of a floatingpoint instruction by the FPU. Holding this pin
active for two and a half clock cycles indicates
TRAP or that the CMPf instruction has been executed.
Slave Done 532: Active low. This signal is for
use with the NS32532 CPU only. When active it
indicates successful completion of a floatingpoint instruction by the FPU.
Force Slave Status Read: Active low. This signal is for use with the NS32532 CPU only.
When active it indicates TRAP or that the CMPf
instruction has been executed.
4.1.4 Input/Output Signals
*DO-D31 Data Bus: These are the 32 signal lines which
carry data between the NS32381 and the CPU.
SPC
Slave Processor Control: Active low. This is the
data strobe signal for slave transfers. For the
32-bit protocol, SPC is only an input signal.
·For the 16·bit Slave Protocol the upper sixteen data input signals (016031) and ODIN should be left floating.
3-20
z
en
w
4.0 Device Specifications (Continued)
I\)
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........•
Q)
Connection Diagrams
U1
......
@@@@@@@@@
K@€)@@@@@@@€)@
J @ @
@@
@@
H@ @
G@@
@@
NS32381
F@@
@@
E @@
@@
D@@
@@
C @ @d
z
en
w
I\)
w
....•
Q)
I\)
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@ @
B@€)@@@@@@@€)@
A
@@@@@@@@@
1 2 3 4 5 6 7 8 9 10 11
TL/EE/9157-18
Bottom View
Order Number NS32381
See NS Package Number US8D
FIGURE 4-1. S8-Pln PGA Package
NS32381 Pinout Descriptions
Desc
Vee
01
00
PS1 (Note 1)
GNO
GNO
ClK
RST
Reserved (Note 2)
Reserved (Note 2)
02
017
016
PSO (Note 1)
GNO
NOE (Note 1)
Reserved (Note 3)
Reserved (Note 2)
Vee
015
018
03
031
014
019
Vee
030
Vee
04
020
013
029
Reserved (Note 3)
05
Pin
Desc
028
GNO
GNO
021
012
027
06
022
011
SON332
07
023
A2
A3
A4
A5
A6
A7
A8
A9
A10
81
82
83
84
85
86
87
88
89
810
811
C1
C2
C10
C11
01
02
010
011
E1
E2
E10
E11
F1
F2
SPC
SON532
Vee
08
GNO
026
GNO
Vee
Reserved (Note 3)
STO
ST1
Reserved (Note 3)
GNO
024
025
09
010
OOIN
Vee
ST2
ST3
FSSR
Note 1: CMOS input; never float.
Note 2: Pin should be grounded.
Note 3: Pin should be left floating.
3-21
Pin
F10
F11
G1
G2
G10
G11
H1
H2
H10
H11
J1
J2
J10
J11
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
l2
l3
l4
l5
l6
l7
l8
19
l10
o
N
~
4.0 Device Specifications (Continued)
('I')
~
en
Connection Diagrams (Continued)
z
......
II)
~
z
0
.....
.....
I
co
('I')
..,
N
~ ~
('I')
en
8>
0::
N
N
Q
co
Q
N
Q
>~i!
(.!)
Lo.I
II)
10
Q
Lo.I
0::
0
N
Q
..,.
Q
0>
0
..,
Q
00
0
N
Q
>~i!
(.!)
z
Vee
D17
D25
Dl
Vee
GND
D16
D9
PSO
D26
PSI
DO
GND
Dl0
GND
1
NS32381
epu
DDIN
NOE
Vee
GND
Vee
ST2
RESERVED NOTE 1
STO
elK
ST3
RESERVED NOTE 2
RST
STl
Vee
RESERVED NOTE 2
TL/EE/9157 -42
Bottom View
Order Number NS32381V-15, NS32381V-20, NS32381V-25 or NS32381V-30
See NS Package Number V68
FIGURE 4-2. 68-Pln Plastic Chip Carrier Package
Note 1: All these pins should be left open.
Note 2: All these pins should be grounded.
3-22
4.0 Device Specifications (Continued)
4.2 ABSOLUTE MAXIMUM RATINGS
All Input or Output Voltages
with Respect to GND
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
ESD Rating
Note: Absolute maximum ratings indicate limits beyond
which permanent damage may occur. Continuous operation
at these limits is not intended; operation should be limited to
those conditions specified under Electrical Characteristics.
95°C
Maximum Case Temperature
Storage Temperature
- 65°C to + 150°C
4.3 ELECTRICAL CHARACTERISTICS T A
-0.5Vto +7.0V
2000V (in human body model)
= O°C to 70·C, Vee = 5V ± 5%, GND = OV
Max
Units
VIH
High Level Input Voltage·
2.0
Vee +0.5
V
VIL
Low Level Input Voltage·
-0.5
O.B
V
VOH
High Level Output Voltage
IOH
= -400 J.l.A
VOL
Low Level Output Voltage
IOL
= 2 rnA
II
Input Load Current·
o =:;: VIN
VIH
Symbol
Parameter
Conditions
Min
Typ
V
2.4
0.4
V
-10.0
10.0
J.l.A
High Level Input Voltage
for PSO, PS1, NOE
3.5
Vee +0.5
V
VIL
Low Level Input Voltage
for PSO, PS1, NOE
-0.5
1.5
V
II
Input Load Current
for PSO, PS1, NOE
o =:;: VIN
-100
100
J.l.A
IL
Leakage Current
(Output and 1/0 Pins
in TRI-STATE®/lnput Mode)
0.4 =:;: VOUT =:;: 2.4V
-20.0
20.0
J.l.A
IcC
Active Supply Current
lOUT
= 0, TA = 25°C, Vec = 5V
300
rnA
Icc
Power Down Current
lOUT
= 0, TA = 25°C, VCC = 5V
60
rnA
=:;: Vee
=:;: Vee
"Except PSO. PS1. NOE and Reserved pins.
Note: PSO. PSl NOE pins have to be connected to either GND or Vee (possible via resistor) as it is shown in Figure 3·48, 3-4b. 3-4c, and 3-4d
4.4 SWITCHING CHARACTERISTICS
ABBREVIATIONS
4.4.1 Definitions
L.E. -
Leading Edge
R.E. -
Rising Edge
All the Timing Specifications given in this section refer to
O.BV and 2.0V on all the input and output signals as illustrated in Figures 4.3 and 4.4, unless specifically stated otherwise.
T.E. -
Trailing Edge
F.E. -
Falling Edge
CLK
[)t·
v
eLK
5101
SIG2
-'t\ D.BV
[
[
SIGl
\
ISIGll
I
tSIG2h
2.4V
O.BV
O.45V
SIG2
2.4V
l'w
[
[
[
"V(C
D.BV
..~
--2.4V
ISIGll
O.45V
2.4V
2.DV
L
tSIG2h
O.45V
TL/EE/9157-2D
FIGURE 4-4. Timing Specification Standard
(Signal Valid before Clock Edge)
O.4SV
TL/EE/9157-19
FIGURE 4-3. Timing Specification Standard
(Signal Valid after Clock Edge)
3-23
o
N
I
0p-
eC)
(f)
4.0 Device Specifications (Continued)
N
4.4.2 Timing Tables (Maximum times assume temperature range O°C to 70°C)
(/)
4.4.2.1 Output Signal Propagation Delays for all CPUs (16·8It Slave Protocol)
(Maximum times assume capacitive loading of 100 pF)
(f)
Z
......
an
opI
0p-
eC)
(f)
Symbol Figure
NS32381·15
Reference/
Conditions
Description
Min
N
Max
NS32381·20
Min
NS32381·25
Max
Min
Units
Max
(f)
(/)
Z
tSPCFw
4·18
SPC Pulse Width
from FPU
AtO.8V
(Both Edges)
SPC Output Active
ns
tCLKp - 10 tCLKp + 10 tCLKp - 10 tCLKp + 10 tCLKp - 10 tCLKp + 10
tSPCFa
4·18
After ClK R.E.
17
17
15
ns
tSPCFia
4·18 SPC Output Inactive After ClK R.E.
38
33
25
ns
tSPCFf(1) 4·18 SPC Output Floating After ClK F.E.
35
30
25
ns
4.4.2.2 Output Signal Propagation Delays for the NS32008, NS32016 and NS32032 CPUs
Maximum times assumes capacitive loading of 100 pF
Symbol
Figure
Description
Reference/
Conditions
NS32381·15
NS32381·20
Min
Min
Max
NS32381·25
Max
Min
Units
Max
tov
4-8
Data Valid (00-015)
After SPC L.E.
30
18
ns
to,(1)
4-8
00-015 Floating
After SPC T.E.
30
30
ns
4.4.2.3 Output Signal Propagation Delays for the 32·81t Slave Protocol NS32332 CPU
Maximum times assume capacitive loading of 100 pF unless otherwise specified
Symbol
Figure
Description
Reference/
Conditions
tov
4-10
Data Valid
After SPC L.E.;
75 pF Cap. loading
tOh
4·10
Data Hold
After SPC T.E.
to,(1)
4-10
tsoNa
4-12,13
tSDNh
tSDNw
tSDN,(1)
tSTRPw
Data Floating
After SPC T.E.
Slave Done Active
After ClK F.E.
4-13
Slave Done Hold
After ClK R.E.
4-12
Slave Done
Pulse Width
AtO.8V
(Both Edges)
4·12,13
Slave Done Floating
After ClK R. E.
4-13
Slave Done (TRAP)
Pulse Width
AtO.8V
(Both Edges)
Note 1: Not 100% tested.
3·24
NS32381·15
Min
Units
Max
25
ns
8
3
% tCLKp -10
2%tCLKp-10
ns
30
ns
28
ns
33
ns
%tCLKp +10
ns
30
ns
2%tCLKp +10
ns
z
en
4.0 Device Specifications (Continued)
(,)
N
(,)
Q)
4.4.2.4 Output Signal Propagation Delays for the 32-81t Slave Protocol NS32532 CPU
Maximum times assume capacitive loading of 50 pF
Symbol
Figure
U1
.........
NS32381-
Reference!
Conditions
Description
.....
.....•
z
25
20
30
Units
en
(,)
N
Min
Max
Min
Max
Min
(,)
Q)
Max
tov
4·14
Data Valid
After SPC L.E.
tOh
4·14
Data Hold
After ClK R.E.
tOl(1)
4·14
Data Floating
After SPC T.E.
30
30
30
ns
tsoa
4·16
Slave Done Active
After ClK R.E.
35
25
20
ns
tSOh
4·16
Slave Done Hold
After ClK R.E.
tSO f (1)
4·16
Slave Done Floating
After ClK R. E.
tFSSR a
4·17
Forced Slave Status
Read Active
After ClK R.E.
tFSSRh
4·17
Forced Slave Status
Read Hold
After ClK R.E.
tFSSR,!1)
4·17
Forced Slave Status
Read Floating
After ClK R.E.
35
35
3
35
3
3
2
ns
20
ns
30
30
30
ns
35
25
20
ns
20
ns
30
ns
30
Units
33
2
ns
33
2
25
2
25
2
2
30
30
4.4.2.5 Input Signal Requirements with all CPUs
NS32381Symbol
Reference!
Conditions
Figure
Description
4·5
Power·On Reset Duration
After ClK R.E.
30
30
30
30
J.Ls
tRSTw
4·6
Reset Pulse Width
At 0.8V (Both Edges)
64
64
64
64
tCLKp
tRSTs
4·7
Reset Setup Time
Before ClK R.E.
10
14
12
11
ns
tRSTh
4·7
Reset Hold
After elK R.E.
0
0
0
0
ns
15
Min
tPWR
25
20
Max
Min
Max
Min
Max
Min
Max
4.4.2.6 Input Signal Requirements with the NS32008, NS32016, NS32032 CPUs
Symbol
Figure
Description
Reference!
Conditions
NS32381-15
Min
tss
4·8
Status (STO-ST1) Setup
Before SPC L.E.
20
tSh
4·8
Status (STO-ST1) Hold
After SPC L.E.
tos
4·9
Data Setup (00-015)
Before SPC T.E.
tOh
4·9
Data Hold (00-015)
tspCw
4·8
SPC Pulse Width
from CPU
Max
NS32381-20
NS32381-25
Min
Min
Max
Units
Max
20
15
ns
20
20
17
ns
25
20
15
ns
After SPC T.E.
20
20
15
ns
AtO.8V
(Both Edges)
35
35
28
ns
Note 1: Not 100% tested.
3·25
.....
N•
o
o
C\I
•
orCO
C")
C\I
4.0 Device Specifications (Continued)
4.4.2.7 Input Signal Requirements with the 32-Blt Slave Protocol NS32332 CPU
C")
UJ
Z
.......
.
Symbol
Figure
Reference!
Description
ororCO
NS32381-15
Conditions
Lt)
Min
Units
Max
tSTs
4-11
Status Setup
Before SPC L.E.
20
ns
tSTh
4-11
Status Hold
After SPC L.E.
20
ns
tos
4-11
Data Setup
Before SPC T.E.
20
ns
tOh
4-11
Data Hold
After SPC T.E.
20
ns
tspCw
4-11
SPC Pulse Width
At O.BV (Both Edges)
35
ns
C")
C\I
C")
UJ
Z
4.4.2.8 Input Signal Requirements with the 32-Bit Slave Protocol NS32532 CPU
NS32381
Symbol
Figure
Reference!
Conditions
Description
20
Min
25
Min
Max
30
Max
Min
Units
Max
tSTs
4-15
Status Setup
Before ClK (T2) R.E.
25
20
20
ns
tSTh
4-15
Status Hold
After ClK (T2) RE.
20
10
10
ns
tOOINs
4-15
Data Direction In Setup
Before SPC L.E.
0
0
0
ns
tOOINh
4-15
Data Direction In Hold
After SPC T.E.
10
10
10
ns
tos
4-15
Data Setup
Before SPC T.E.
6
6
4
ns
4-15
Data Hold
After SPC T.E.
20
10
10
ns
tspc s
4-14,15
SPCSetup
Before ClK RE.
20
20
20
ns
tSPCh
4-14,15
SPCHold
After ClK R.E.
0
0
0
ns
tOh
4.4.2.9 Clocking Requirements with all CPUs
NS32381
Symbol
Figure
Description
Reference!
Conditions
15
20
25
30
Units
Min
Max
Min
Max
Min
Max
Min
Max
tCLKh
4-4
Clock High Time
At 2.0 V (Both Edges)
25
1000
20
1000
16
1000
13
1000
ns
tCLKI
4-4
Clock low Time
At O.BV (Both Edges)
25
DC
20
DC
16
DC
13
DC
ns
tCTr(1)
4-4
Clock Rise Time
Between O.BV and 2.0V
3
ns
tCTi 1)
4-4
Clock Fall Time
Between 2.0V and O.BV
3
ns
tCLKp
4-4
Clock Period
ClK R.E. to Next ClK RE.
DC
ns
7
5
7
Note 1: Not 100% tested.
3-26
66
DC
4
5
50
DC
4
40
DC
33.3
4.0 Device Specifications (Continued)
4.4.3 Timing Diagrams
elK
TL/EE/9157 -21
FIGURE 4-5. Clock Timing
TLlEE/9157 -22
FIGURE 4-S. Power-On Reset
eLK
SLJLfLSLIL
m_{
r--
t"~
TLlEE/9157-23
FIGURE 4-7. Non-Power-On Reset
I
ClK~
9
j--tRSTs-l
RSTh/
RST
----'
TL/EE/9157 -24
FIGURE 4-S. RST Release Timing
Note: The rising edge of RST must occur while elK is high, as shown.
ClK
STO, ST1
--.....I
?llX
VALID
x071/1//Z
ItSSj~tSh~
_tspcw-T
tDv-j ~ I--tOf:j
00-015
-----------<
VALID FROM FPU
r-
TL/EE/9157 -25
FIGURE 4-9. Read Cycle from FPU (NS3200S, NS3201S, NS32032 CPUs)
3-27
o
N
,...•
CO
.---------------------------------------------------------------------------~
4.0 Device Specifications (Continued)
C")
N
C")
t/)
ClK
Z
.......
,...
,...•
----'
it)
STO, ST1lllX
CO
x07111111
VALID
1-",1 C="h---l
C")
N
C")
t/)
SPC
Z
----ctspcw--l~L
tos - j
tOh::j
r-----
DO-D1S-Z'-:Zl""'lZ""V"/X"""
VALID fROt.! CPU
~
TLlEE/9157-26
FIGURE 4-10. Write Cycle to FPU (NS32008, NS32016, NS32032 CPUs)
I-Tl
ru[
sro-Sl3[mzmoX___
S~[
Dv
OO_D3{ ________t_
H
__
fVWD
T4--j
p_m___m_m
TLlEE/9157 -27
FIGURE 4-11. Read Cycle from FPU (NS32332 CPU)
I-Tl
'I'
T4--j
DO-D3{---------.....(JI'-__"'If).--------TL/EE/9157 -28
FIGURE 4-12. Write Cycle to FPU (NS32332 CPU)
3·28
z
en
w
4.0 Device Specifications (Continued)
N
W
....•
....
U1
co
C~[
.....
z
en
w
____ [-----~~!~~~t:~~~ _____ _
N
W
.
SDN332
....
co
N
tsDNw
TL/EE/9157-29
FIGURE 4-13. SDN332 Timing (NS32332 CPU)
tso..
~r
___
--l_~~tSDNf
TL/EE/9157-30
FIGURE 4-14. SDN332 (TRAP) Timing (NS32332 CPU)
r
T1
"I'
T2--j
tOl]
"""If - ----
O O - D 3 t [ - - - - - - - - - - e J l_
- _ _D_AT_A_VA_LI_D_ _
TLlEE/9157-31
FIGURE 4-15. Read Cycle from FPU (NS32532 CPU)
3-29
o
.
o
N
'I"'"
CO
4.0 Device Specifications (Continued)
C")
rn
N
C")
(J)
Z
.......
it)
'I"'"
•
ru[
~
'I"'"
CO
C")
N
C")
(J)
STO-ST3
'I'
t:t
[""""'ZZ""""'ZZ-,-r'ZZ""""'ZZ"""""ZX
STS
-1
Z
T2-j
.J~h
X1......-ZZ,.......,...71.,....,...7Z-7Z....,..-p7Z~7
I
DO-"{-----------. See DC Electrical Characteristics table.
3.4 BUS OPERATION
Instructions and operands are passed to the NS32081 FPU
with slave processor bus cycles. Each bus cycle transfers
either one byte (8 bits) or one word (16 bits) to or from the
FPU. During all bus cycles, the SPC line is driven by the
CPU as an active low data strobe, and the FPU monitors
Grounding connections are made on two pins. logic Ground
(GNDl, pin 12) is the common pin for on-chip logic, and
Buffer Ground (GNDB, pin 13) is the common pin for the
output drivers. For optimal noise immunity, it is recommended that GNDl be attached through a single conductor directly to GNDB, and that all other grounding connections be
made only to GNDB, as shown below (Figure 3-1).
10kn~
+5V
SPC
AID 0-15
Vee 24
SERIES
32000
CPU
FPU
GNDl
STO
STI
SPC
SPC
16-BIT ....
00-15
'DATA BUS r
STO ..... STO NS32081
sn ..... STI FPU
RST
RST
...
IL
NS32081
12
: microprocessor family. It is
a support circuit that minimizes the software and real-time
overhead required to handle multi-level, prioritized interrupts. A single NS32202 manages up to 16 interrupt sources,
resolves interrupt priorities, and supplies a single-byte interrupt
vector to the CPU.
• 16 maskable interrupt sources, cascadable to 256
• Programmable 8- or 16-bit data bus mode
• Edge or level triggering for each hardware interrupt with
individually selectable polarities
• 8 software interrupts
• Fixed or rotating priority modes
• Two 16-bit, DC to 10 MHz counters, that may be concatenated into a single 32-bit counter
• Optional a-bit 1/0 port available in a-bit data bus mode
• High-speed XMOSTM technology
• Single, + 5V supply
• 40-pin, dual in-line package
The NS32202 can operate in either of two data bus modes:
16-bit or 8-bit. In the 16-bit mode, eight hardware and eight
software interrupt positions are available. In the 8-bit mode,
16 hardware interrupt positions are available, 8 of which can
be used as software interrupts. In this mode, up to 16 additional ICUs may be cascaded to handle a maximum of 256
interrupts.
Two 16-bit counters, which may be concatenated under program control into a single 32-bit counter, are also available
for real-time applications.
Basic System Configuration
I+-
iNf
NS32018
MASTER
CPU
GRDUP
NS32202
ICU
.i.
: : : ) NON·CASCADED
INTERRUPT SOURCES
I+:--
++0;-
iNf
:
1+ •
'---""
CASCADED
:
N532202
ICU
CASCADED
INTERRUPT
SOURCES
-
++0;-
iNf
CASCADED
N532202
ICU
TL/EE/5117-1
4-3
....
o
~
Table of Contents
o
N
N
Cf)
U)
Z
1.0 PRODUCT INTRODUCTION
3.0 ARCHITECTURAL DESCRIPTION (Continued)
3.9 FPRT· First Priority Registers (R14, R15)
1.1 I/O Buffers
1.2 Read/Write Logic and Decoders
3.10 MCTL· Mode Control Register (R16)
1.3 Timing and Control
3.11 OSCASN • Output Clock Assignment (R17)
1.4 Priority Control
3.12 CIPTR • Counter Interrupt Pointer Register (R18)
3.13 PDAT· Port Dada Register (R19)
1.5 Counters
3.14 IPS· Interrupt/Port Select Register (R20)
2.0 FUNCTIONAL DESCRIPTION
3.15 PDIR • Port Direction Register (R21)
2.1 Reset
3.16 CCTL • Counter Control Register (R22)
2.2 Initialization
3.17 CICTL • Counter Interrupt Control Register (R23)
2.3 Vectored Interrupt Handling
3.18 LCSVlHCSV • L·Counter Starting Value/H·Counter
Starting Value Registers (R24, R25, R26, and R27)
2.3.1 Non·Cascaded Operation
3.19 LCCV /HCCV • L·Counter Current Value/H·Counter
Current Value Registers (R28, R29, R30, and R31)
2.3.2 Cascade Operation
2.4 Internal ICU Operating Sequence
3.20 Register Initialization
2.5 Interrupt Priority Modes
4.0 DEVICE SPECIFICATIONS
2.5.1 Fixed Priority Mode
4.1 NS32202 Pin Descriptions
2.5.2 Auto·Rotate Mode
4.1.1 Power Supply
2.5.3 Special Mask Mode
4.1.2 Input Signals
2.5.4 POlling Mode
4.1.3 Output Signals
3.0 ARCHITECTURAL DESCRIPTION
4.1.4 Input/Output Signals
3.1 HVCT· Hardware Vector Register (RO)
4.2 Absolute Maximum Ratings
3.2 SVCT • Software Vector Register (R1)
4.3 Electrical Characteristics
3.3 ELTG • Edge/Level Triggering Registers (R2, R3)
4.4 Switching Characteristics
3.4 TPL • Triggering Polarity Registers (R4, RS)
4.4.1 Definitions
3.5 IPND • Interrupt Pending Registers (R6, R7)
4.4.1.1 Timing Tables
3.6 ISRV • Interrupt In·Service Registers (R8, R9)
4.4.1.2 Timing Diagrams
3.7 IMSK • Interrupt Mask Registers (R10, R11)
3.8 CSRC· Cascaded Source Registers (R12, R13)
List of Illustrations
NS322021CU Block Diagram ...............•...........•...................•.................................... 1·1
Counter Output Signals in Pulsed Form and Square Waveform for Three Different Initial Values ....................•...... 1·2
Counter Configuration and Basic Operations .................................................................•..... 1·3
Interrupt Control Unit Connections in 16·Bit Bus Mode .....................•........................................ 2·1
Interrupt Control Unit Connections in 8·Bit Bus Mode ............................................................... 2·2
Cascaded Interrupt Control Unit Connections in 8·Bit Bus Mode •.....................•............................... 2·3
CPU Interrupt Acknowledge Sequence ........................... '" .............................................. 2·4
Interrupt Dispatch and Cascade Tables ...........•...............................................................2·5
CPU Return from Interrupt Sequence ................................................•............................2·6
ICU Interrupt Acknowledge Sequence ......................•......................•..............................2·7
ICU Return from Interrupt Sequence .............................................................................. 2·8
ICU Internal Registers ...........................•..............................................................3·1
HVCT Register Data Coding ................•....................................................................3·2
Recommended ICU's Initialization Sequence .........................................•............................3·3
NS322021CU Connection Diagram ...............................................................................4·1
Timing Specification Standard ...................................................................................4·2
READIINTA Cycle ..............................•.......•......................................................4·3
Write Cycle ....................................................................................................4·4
Interrupt Timing in Edge Triggering Mode ................... , ............. , ........................................ 4·5
Interrupt Timing in Level Triggering Mode .........................................................................4·6
Externallnterrupt.Sampling-Clock to be Provided at Pin COUT/SCIN When in Test Mode •............................... 4·7
Internallnterrupt·Sampling-Clock to be Provided at Pin COUT /SCIN ....................•............................. 4·8
Relationship Between Clock Input at Pin CLK and Counter Output Signals at Pins COUT /SCIN or GO/RO-G3/R6,
in Both Pulsed Form and Square Waveform .......................................................................4-9
4-4
.-------------------------------------------------------------------~z
en
w
1.0 Product Introduction
The NS32202 ICU functions as an overall manager in an
interrupt-oriented system environment. Its many features
and options permit the design of sophisticated interrupt systems.
Figure 1-1 shows the internal organization of the NS32202.
As shown, the NS32202 is divided into five functional
blocks. These are described in the following paragraphs:
1.11/0 BUFFERS AND LATCHES
The I/O Buffers and Latches block is the interface with the
system data bus. It contains bidirectional buffers for the
data I/O pins. It also contains registers and logic circuits
that control the operation of pins GO/IRO, ... ,G7/IR14
when the ICU is in the a-bit bus mode.
1.2 READ/WRITE LOGIC AND DECODERS
The Read/Write Logic and Decoders manage all internal
and external data transfers for the ICU. These include Data,
Control, and Status Transfers. This circuit accepts inputs
from the CPU address and control buses. In turn, it issues
commands to access the internal registers of the ICU.
Vee
G7/IR14 +-+
G611R12 +-+
GSliR1D +-+
G411R8+-+
G311R6+-+
G2IIR4+-+
Gl11R2 +-+
GOIIRO +-+
D7 +-+
06+-+
DS+-+
D4+-+
D3+-+
02+-+
01+0+
DO..-.
STl
!NT
IRI
The Priority Control Block contains 16 units, one for each
interrupt position. These units provide thl3 following functions.
• Sensing the various forms of hardware interrupt signals e.g. level (high/low) or edge (rising/failing)
• Resolving priorities and generating an interrupt request to the CPU
• Handling cascaded arrangements
• Enabling software interrupts
• Providing for an automatic return from interrupt
• Enabling the assignment of any interrupt position to
the internal counters
• Providing for rearrangement of priorities by assigning
the first priority to any interrupt position
• Enabling automatic rotation of priorities
.....•
1.5 COUNTERS
1.3 TIMING AND CONTROL
GND
o
This block contains two 16-bit counters, called the H-counter and the L-counter. These are down counters that count
from an initial value to zero. Both counters have a 16-bit
register (designated HCSV and LCSV) for loading their restarting values. They also have registers containing the current count values (HCCV and LCCV). Both sets of registers
are fully described in Section 3.
The Timing and Control Block contains status elements that
select the ICU operating mode. It also contains state machines that generate all the necessary sequencing and control signals.
1..L
N
N
1.4 PRIORITY CONTROL
IR3
IRS
IR7
IR9
IRll
IR13
IR15
I i~---.
L.:
PRIORITY
CONTROL
I/O BUFFERS
AND
I+---'i
LATCHES
.....
TIMING
AND
CONTROL
1----1-.1 co,:"
-~--'
I: ·~/S~
CLK
READ/WRITE LOGIC
AND DECODERS
iii t
AD
Al
A2
FIGURE 1-1. NS322021CU Block Diagram
4-5
A3
A4
TL/EE/5117-2
N
<:)
1.0 Product Introduction
2.0 Functional Description
(Continued)
The counters are under program control and can be used to
generate interrupts. When the count reaches zero, either
counter can generate an interrupt request to any of the 16
interrupt positions. The counter then reloads the start value
from the appropriate registers and resumes counting. Figure
1-2 shows typical counter output signals available from the
NS32202.
2.1 RESET
The ICU is reset when a logic low signal is present on the
RST pin. At reset, most internal ICU registers are affected,
and the ICU becomes inactive.
2.2 INITIALIZATION
After reset, the CPU must initialize the NS32202 to establish
its configuration. Proper initialization requires knowledge of
the ICU register's formats. Therefore, a flowchart of a recommended initialization sequence is shown in (Figure 3-3)
after the discussion of the ICU registers.
The maximum input clock frequency is 2.5 MHz.
A divide-by-four prescaler is also provided. When the prescaler is used, the input clock frequency can be up to 10
MHz.
The operation sequence shown in Figure 3-3 ensures that
all counter output pins remain inactive until the counters are
completely initialized.
When intervals longer than provided by a 16-bit counter are
needed, the L- and H-counters can be concatenated to form
a 32-bit counter. In this case, both counters are controlled
by the H-counter control bits. Refer to the discussion of the
Counter Control Register in Section 3 for additional information. Figure 1-3 summarizes counter read/write operations.
2.3 VECTORED INTERRUPT HANDLING
For details on the operation of the vectored interrupt mode
for a particular Series 32000 CPU, refer to the data sheet for
INPUT CLOCK
COUNTER
CONTENTS
(INIT. VALUE=2)· _ _ _ _ _ _ _ _ _ _ _.....,
r---------....
U
OUTPUT IN
PULSED FORM
If
OUTPUT IN
SQUARE WAVEFORM
COUNTER
CONTENTS
Upo-----.. .Ur------..,lf
(INIT. VALUE = 1) - - - - - - - - - .
OUTPUT IN
PULSED FORM
L
OUTPUT IN
SQUARE WAVEFORM
COUNTER
CONTENTS
(INIT. VALUE=O) _ _ _ _--,
OUTPUT IN
PULSED FORM
OUTPUT IN
SQUARE WAVEFORM
TL/EE/5117-4
FIGURE 1-2. Counter Output Signals In Pulsed Form and Square Waveform for Three Different Initial Values
4-6
z
2.0 Functional Description
en
w
(Continued)
that CPU. In this discussion, it is assumed that the NS32202
is working with a CPU in the vectored interrupt mode. Several ICU applications are discussed, including non-cascaded
and cascaded operation. Figures 2-1, 2-2, and 2-3 show
typical configurations of the ICU used with the NS32016
CPU.
rupt Output (INT) pin and generates an interrupt vector byte.
The interrupt vector byte identifies the interrupt source in its
four least significant bits. When the CPU detects a low level
on its Interrupt Input pin, it performs one or two interrupt
acknowledge cycles depending on whether the interrupt request is from the master ICU or a cascaded ICU. Figure 2-4
shows a flowchart of a typical CPU Interrupt Acknowledge
sequence.
A peripheral device issues an interrupt request by sending
the proper signal to one of the NS32202 interrupt inputs. If
the interrupt input is not masked, the ICU activates its Inter-
I
STARTING VALUE
LCSV/HCSV
o :~
.....,II: ..... ;a...
r
~, 0:
Dl
co
CI>
~
<
!;;:
COUNTER
FREEZE COUNTER READINGS
Q
....<
~
I
2:
,.
I
CURRENT VALUE
LCCV/HCCV
0
C
1
I ..
r
""II ...... :,..
TL/EE/5117-5
BASIC OPERATIONS:
~ ~ (lOB)
~ ~ (lOB)
@ ~ (lOB)
WRITING TO LCSV/HCSV
READING LCSV IHCSV
WRITING TO LCCV IHCCV
(only possible when counters are halted)
READING LCCV/HCCV
@J ~
@J ~
(lOB)
(lOB)
(only possible when counter
readings are frozen)
COUNTER COUNTS AND READINGS ARE
NOT FROZEN
COUNTER RELOADS STARTING VALUE
(occurs on the clock cycle following
the one in which it reaches zero)
FIGURE 1-3. Counter Configuration and Basic Operations
4-7
I\)
I\)
o
I\)
.....
I
o
....o
S
2.0 Functional Description (Continued)
N
N
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Z
A16-A23
lO-A23
iiil
r-+l
LATCH
I
I
I
L
lO-A4
M-A4
HBE
IR15 ~
Ci
IRU
+-
STl
In
IRll
iHT
iNi
+-
HS32018
CPU
T
ADS
I
r
r--+
ACDRESS
DECODER
HS32202
ICU
Diiiii
BUFFER
PHil
J
ADO-AC1S
PHIZ
DO-D1S
DO-D71
GOIIRD-07/IR14
r
f
PHil
PHIZ
ADS
HS32201
Teu
DDIN
iffil
---,1
WKI
iffi
WK
IR9
+-
IR7
+-
IRS
+-
IR3
+--
IRl
+--
DO-D15
TL/EE/5117-6
FIGURE 2-1. Interrupt Control Unit Connections In 16-Blt Bus Mode
A16-A23
r
r-+l
HS32018
CPU
ADS
LATCH
t
I
Al-AS
I
I
.~
MORESS
DECODER
OND~
r--+
lD-A23
AO-A4
HBE
Ci
sn
sn
iHT
iNi
ODIN
BUFFER
DO-07
ADO-AC15 '"
PHil
PHIZ
t
PHil
t
DO-D7
G7/IR14
G6/IR1Z
GSIIR10
G4/IRI
G3/IRS
GZ/IR4
Gl/IRZ
HS32202 GO/IRO
leu
IR15
IR13
IRll
1R9
~
PHIZ
ADS
HS32201
Teu
DDIN
iffil
iii)
-.L
Wi
WKI
IR7
IR5
IR3
IRl
DO-D15
NOTE: In the a-Bit Bus Mode the Master ICU Registers appear at even
addresses (AO = 0) since the ICU communicates with the least significant byte of the CPU data bus.
FIGURE 2-2. Interrupt Control Unit Connections In 8-Bit Bus Mode
4-8
.....
.....
.....
.....
.....
.....
+-+
+-+
++-++-++-++-
TL/EE/5117-7
2.0 Functional Description
zen
w
(Continued)
N
.....
N
o
N
o
A1-AS-'o.
. AO-M
GND~
07111114
GI I 11112
05/11110
GC/IU
G3/1R1
GZ/III4
~
~
~
CASCADED GlIlRZ
f+-+
HIE
Ci
IT1
NS32202
GO/IIO
ICU
OO-D7
ID
M
roo
A11-A23
~
NS320HI
CPU
ADS
LATCH
I
I
I
1
I =: I
iii
PH"
iiii
J
ADO-AD15
PHI2
I
f
f
'""
PHI2
I
BUFFO
A1-AS
07/1114
Gl/II12
GND ...... HIE
G5/1110
GC/IU
63/1R1
GZ/IU
In
MASTER 01/1112
iii NS32202 001Il10
ICU
11115
11113
OO-D7
OO-D7
11111
AO-M
cs
IT1
I
I'
1111
1117
ADS
NS32201
TCU
DOlI
-.
IRS
iii
~,
WI,
~
1.13 f41111 f+IRtf+1171+IRSf41R3f4.1f4-
AD-A23
P'
,
1115
~
,.
Wi
IR3
1111
~
~
~
~
~
~
:::-
:=
+++-
:::
OO-D15
TL/EE/5117-B
FIGURE 2-3. Cascaded Interrupt Control Unit Connections In 8·Blt Bus Mode
4-9
o
.....
S
2.0 Functional Description
(Continued)
N
N
CW)
en
z
• Condo A is true if current Instruction is terminated
or an Interruptible point in a string Instruction is
reached.
TL/EE/5117 -9
FIGURE 2-4. CPU Interrupt Acknowledge Sequence
4·10
2.0 Functional Description
(Continued)
2.3.2 Cascaded Operation. In cascaded operation, one or
more of the interrupt inputs of the master ICU are connected to the Interrupt Output pin of one or more cascaded
ICUs. Up to 16 cascaded ICUs may be used, giving a system total of 256 interrupts.
In general, vectored interrupts are serviced by interrupt routines stored in system memory. The Dispatch Table stores
up to 256 external procedure descriptors for the various
service procedures. The CPU INTBASE register points to
the top of the Dispatch Table. Figure 2-5 shows the layout
of the Dispatch Table. This figure also shows the layout of
the Cascade Table, which is discussed with ICU cascaded
operation.
Note: The number of cascaded ICUs is practically limited to 15 because the
Dispatch Table for the NS32016 CPU is constructed with entries 1
through 15 either used for NMI and Trap descriptors, or reserved for
future use. Interrupt position 0 of the master ICU should not be cascaded, so It can be vectored through Dispatch Table entry 0, reserved
for non-vectored interrupts. In this case, the non-vectored interrupt
entry (entry 0) is also available for vectored interrupt operation, since
the CPU is operating in the vectored interrupt mode.
2_3.1 Non-Cascaded Operation. Whenever an interrupt request from a peripheral device is issued directly to the master ICU, a non-cascaded interrupt request to the CPU results. In a system using a single NS32202, up to 16 interrupt
requests can be prioritized. Upon receipt of an interrupt request on the INT pin, the CPU performs a Master InterruptAcknowledge bus cycle, reading a vector byte from address
FFFE0016. This vector is then used as an index into the
dispatch table in order to find the External Procedure Descriptor for the proper interrupt service procedure. The service procedure eventually returns via the Return-fram-Interrupt (RET) instruction, which performs a Return-from-Interrupt bus cycle, informing the ICU that it may re-prioritize any
interrupt requests still pending. Figure 2-6 shows a typical
CPU RETI sequence. In a system with only one ICU, the
vectors provided must be in the range of 0 through 127; this
can be ensured by writing OXXXXXXX into the SVCT register. By providing a negative vector value, the master ICU
flags the interrupt source as a cascaded ICU (see below).
The address of the master ICU should be FFFE0016. (*)
Cascaded ICUs can be located at any system address. A list
of cascaded ICU addresses is maintained in the Cascade
Table as a series of sixteen 32-bit entries.
(·)Note: The CPU status corresponding to both, master interrupt acknowledge and return from interrupt bus cycles, as well as address bit
AS, could be used to generate the chip select (CS) signal for accessing the master ICU during one of the above cycles. In this case
the master ICU can reside at any system address. The only limitation is that the least significant 5 or 6 address bits (6 in the S-bit bus
mode) must be zero. The address bit AS must be decoded to prevent an NMI bus cycle from reading the hardware vector register of
the ICU. This could happen, since the NS32016 CPU performs a
dummy read cycle from address FFFF0016, with the same status
as a master INTA cycle, when a non-maskable-interrupt is acknowledged.
MEMORY
THESE ADDRESSES ARE
USED BY THE CPU DURING
THE SECOND CYCLE OF
AN INTAOR RETI
SEDUENCE TO GET THE
INTERRU~ VECTOR FROM
A CASCADED ICU.
CASCADE TABLE
~~~~------~----N-VI-O-ES-C-RI-~-OR----+-NMIANOTRAP
OESCRI~ORS *
I
RESERVED*
INT.
DESCRI~OR
(INTBASE+4· VECTOR)
16
INTERRU~
DISPATCH TABLE
1----------------
INT. DESCRI~OR N
~------------~
INT.
DESCRI~OR
255
MASTER ICU'S
HVCT REGISTER
-
CPU READS THIS LOCATION DURING
ARST CYCLE OF INTA OR RETI
SEQUENCE TO GET EITHER
THE INTERRU~ VECTOR OR
A CASCADE TABLE INDEX FROM
THE MASTER ICU.
• Table entries 1 to 15 should not be used by the ICU since they contain NMI and Trap Descriptors
or are reserved for future use. (For more details refer to NS32016 data sheet.)
FIGURE 2-5. Interrupt Dispatch and Cascade Tables
4-11
TL/EE/5117-10
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r-----------------------------------------------------------------------~
2.0 Functional Description (Continued)
oro
cascaded ICU, of course, has its own set of 16 unique interrupt vectors, one vector for each of its 16 interrupt positions.
The CPU interprets the vector value read during a Cascaded Interrupt Acknowledge cycle as an unsigned number.
Thus, this vector can be in the range 0 through 255.
When a cascaded interrupt service routine completes its
task, it must return control to the interrupted program with
the same RETI instruction used in non-cascaded interrupt
service routines. However, when the CPU performs a Master Return From Interrupt cycle, the CPU accesses the master ICU and reads the negative Cascade Table index identifying the cascaded ICU that originally received the interrupt
request. Using the cascaded ICU address, the CPU now
performs a Cascaded Return From Interrupt cycle, informing
the cascaded ICU that the service routine is over. The byte
provided by the cascaded ICU during this cycle is ignored.
2_4 INTERNAL ICU OPERATING SEQUENCE
The NS32202 ICU accepts two interrupt types, software and
hardware.
Software interrupts are initiated when the CPU sets the
proper bit in the Interrupt Pending (IPND) registers (R6, R7),
located in the ICU. Bits are set and reset by writing the
proper byte to either R6 or R7. Software interrupts can be
masked, by setting the proper bit in the mask registers (R10,
R11).
EXECUTE CASCADED
ICU CYCLE AND READ
VECTOR FROM
CASCADED ICU
Hardware interrupts can be either internal or external to the
ICU. InternallCU hardware interrupts are initiated by the onchip counter outputs. External hardware interrupts are initiated by devices external to the ICU, that are connected to
any of the ICU interrupt input pins.
Hardware interrupts can be masked by setting the proper bit
in the mask registers (R10, R11). If the Freeze bit (FRZ),
located in the Mode Control Register (MCTL), is set, all incoming hardware interrupts are inhibited from setting their
corresponding bits in the IPND registers. This prevents the
ICU from recognizing any hardware interrupts.
Once the ICU is initialized, it is enabled to accept interrupts.
If an active interrupt is not masked, and has a higher priority
than any interrupt currently being serviced, the ICU activates its Interrupt Output (INT). Figure 2-7 is a flowchart
showing the ICU interrupt acknowledge sequence.
TL/EE/5117-11
FIGURE 2-6. CPU Return from Interrupt Sequence
The master ICU maintains a list (in the CSRC register pair)
of its interrupt positions that are cascaded. It also provides a
4-bit (hidden) counter (in-service counter) for each interrupt
position to keep track of the number of interrupts being
serviced in the cascade ICUs. When a cascaded interrupt
input is active, the master ICU activates its interrupt output
and the CPU responds with a Master Interrupt Acknowledge
Cycle. However, instead of generating a positive interrupt
vector, the master ICU generates a negative Cascade Table
index.
The CPU responds to the active INT line by performing an
Interrupt Acknowledge bus cycle. During this cycle, the ICU
clears the IPND bit corresponding to the active interrupt position and sets the corresponding bit in the Interrupt In-Service Registers (lSRV). The 4-bit in-service counter in the
master ICU is also incremented by one if the fixed priority
mode is selected and the interrupt is from a cascaded ICU.
The ISRV bit remains set until the CPU performs a RETI bus
cycle and the 4-bit in-service counter is decremented to
zero. Figure 2-8 is a flowchart showing ICU operation during a RETI bus cycle.
The CPU interprets the negative number returned from the
master ICU as an index into the Cascade Table. The Cascade Table is located in a negative direction from the Dispatch Table, and it contains the virtual addresses of the
hardware vector registers for any cascaded NS32202s in
the system. Thus, the Cascade Table index supplied by the
master ICU identifies the cascaded ICU that requested the
interrupt.
When the ISRV bit is set, the INT output is disabled. This
output remains inactive until a higher priority interrupt position becomes active, or the ISRV bit is cleared.
An exception to the above occurs in the master ICU when
the fixed priority mode is selected, and the interrupt input is
connected to the INT output of a cascaded ICU.ln this case
the ISRV bit does not inhibit an interrupt of the same priority.
Once the cascaded ICU is identified, the CPU performs a
Cascaded Interrupt Acknowledge cycle. During this cycle,
the CPU reads the final vector value directly from the cascaded ICU, and uses it to access the Dispatch Table. Each
This is to allow nesting of interrupts in a cascaded ICU.
4-12
z
en
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2.0 Functional Description (Continued)
PI.)
PI.)
Q
PI.)
.....•
Q
• Condo B is true if anyone of the following conditions is satisfied.
1) No interrupt is being serviced
2) There Is a pending unmasked Interrupt with
priority higher than that of the Interrupt being
serviced.
3) There is a pending unmasked interrupt from a
cascaded ICU with priority higher or same as that
of the highest priority interrupt position in the
master ICU with the ISRV bit set.
--.....;:....--
TLlEE/5117-12
FIGURE 2-7.ICU Interrupt Acknowledge Sequence
4-13
I]
~
o'I"'"
•
N
o
2.0 Functional Description
(Continued)
N
N
C")
UJ
Z
~------~~------------~
YES
RESET
INTERRUPT ISRV BIT
AND ASSIGN FIRST
PRIORITY TO NEXT
INTERRUPT POSITION
RESET
INTERRUPT
ISRV BIT
TL/EE/5117-13
FIGURE 2-8. leu Return from Interrupt Sequence
4·14
z
2.0 Functional Description
en
w
I'\)
(Continued)
The bits of the ISRV registers are changed with either the
Set Bit Interlocked or Clear Bit Interlocked instructions (SBITIW or CBITIW). The in-service bit is cleared to enable lower priority interrupts and set to disable them.
2.5 INTERRUPT PRIORITY MODES
The NS32202 ICU can operate in one of four interrupt priority modes: Fixed Priority; Auto-Rotate; Special Mask; and
Polling. Each mode is described below.
Note: For proper operation of the ICU, an interrupt service routine must set
its ISRV bit before executing the RETI instruction. This prevents the
RETI cycle from clearing the wrong ISRV bit.
2.5.1 Fixed Priority Mode
In the Fixed Priority Mode (also called Fully Nested Mode),
each interrupt position is ranked in priority from 0 to 15, with
o being the highest priority. In this mode, the processing of
lower priority interrupts is nested with higher priority interrupts. Thus, while an interrupt is being serviced, any other
interrupts of the same or lower priority are inhibited. The ICU
does, however, recognize higher priority interrupt requests.
2.5.4 Polling Mode
The Polling Mode gives complete control of interrupt priority
to the system software. Either some or all of the interrupt
positions can be assigned to the polling mode. To assign all
interrupt positions to the polling mode, the CPU interrupt
enable flag is reset. To assign only some of the interrupt
positions to the polling mode, the desired interrupt positions
are masked in the Interrupt Mask registers (lMSK). In either
case, the polling operation consists of reading the Interrupt
Pending (IPND) registers.
When the interrupt service routine executes its RETI instruction, the corresponding ISRV bit is cleared. This allows any
lower priority interrupt request to be serviced by the CPU.
At reset, the default priority assignment gives interrupt IRO
priority 0 (highest priority), interrupt IR1 priority 1, and so
forth. Interrupt IR15 is, of course, assigned priority 15, the
lowest priority. The default priority assignment can be altered by writing an appropriate value into register FPRT (L)
as explained in Section 3.9.
If necessary, the IPND read can be synchronized by setting
the Freeze (FRZ) bit in the Mode Control register (MCTL).
This prevents any change in the IPND registers during the
read. The FRZ bit must be reset after the polling operation
so the IPND contents can be updated. If an edge-triggered
interrupt occurs while the IPND registers are frozen, the interrupt request is latched, and transferred to the IPND registers as soon as FRZ is reset.
Note: When the ICU generates an interrupt request to the CPU for a higher
priority interrupt while a lower priority interrupt is still being serviced by
the CPU, the CPU responds to the interrupt request only if its internal
interrupt enable flag is set. Normally, this flag is reset at the beginning
of an interrupt acknowledge cycle and set during the RETI cycle. If the
CPU is to respond to higher priority interrupts during any interrupt
service routine, the service routine must set the internal CPU interrupt
enable flag, as soon during the service routine as desired.
The polling mode is useful when a single routine is used to
service several interrupt levels.
3.0 Architectural Description
2.5.2 Auto-Rotate Mode
The NS32202 has thirty-two a-bit registers that can be accessed either individually or in pairs. In 16-bit data bus
mode, register pairs can be accessed with the CPU word or
double-word reference instructions. Figure 3-1 shows the
ICU internal registers. This figure summarizes the name,
function, and offset address for each register.
The Auto Rotate Mode is selected when the NTAR bit is set
to 0, and is automatically entered after Reset. In this mode
an interrupt source position is automatically assigned lowest
priority after a request at that position has been serviced,
Highest priority then passes to the next lower priority position. For example, when servicing of the interrupt request at
position 3 is completed (ISRV bit 3 is cleared), interrupt position 3 is assigned lowest priority and position 4 assumes
highest priority. The nesting of interrupts is inhibited, since
the interrupt being serviced always has the highest priority.
Because some registers hold similar data, they are grouped
into functional pairs and assigned a single name. However,
if a Single register in a pair is referenced, either an L or an H
is appended to the register name. The letters are placed in
parentheses and stand for the low order a bits (L) and the
high order a bits (H). For example, register R6, part of the
Interrupt Pending (IPND) register pair, is referred to individually as IPND(L).
This mode is used when the interrupting devices have to be
assigned equal priority. A device requesting an interrupt, will
have to wait, in the worst case, until each of the 15 other
devices has been serviced at most once.
The following paragraphs give detailed descriptions of the
registers shown in Figure 3-1.
2.5.3 Special Mask Mode
The Special Mask Mode is used when it is necessary to
dynamically alter the ICU priority structure while an interrupt
is being serviced. For example, it may be desired in a particular interrupt service routine to enable lower priority interrupts during a part of the routine. To do so, the ICU must be
programmed in fixed priority mode and the interrupt service
routine must control its own in-service bit in the ISRV registers,
3.1 HVCT -
HARDWARE VECTOR REGISTER (RO)
The HVCT register is a single register that contains the interrupt vector byte supplied to the CPU during an Interrupt
Acknowledge (INTA) or Return From Interrupt (RETI) cycle.
The HVCT bit map is shown below:
7
6
5
4
320
B
4-15
B
B
B
v
v
v
v
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.......
o
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.....
N
C)
3.0 Architectural Description
(Continued)
N
N
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REG. NUMBER AND
ADDRESS I HEX.
REG.
NAME
REG. FUNCTION
RO (0016)
HVCT-
HARDWARE VECTOR
R1 (0116)
SVCT-
SOFTWARE VECTOR
R3 (0316)
R2 (0216)
ELTG-
EDGE/LEVEL TRIGGERING
R5 (0516)
R4 (0416)
TPL-
TRIGGERING POLARITY
R7 (0716)
R6 (0616)
IPND-
INTERRUPTS PENDING
R9 (0916)
R8 (0816)
ISRV-
INTERRUPTS IN-SERVICE
R11 (0816)
R10 (OA16)
IMSK-
INTERRUPT MASK
R13 (OD16)
R12 (OC16)
CSRC-
CASCADED SOURCE
R15 (OF16)
R14 (OE16)
FPRT-
FIRST PRIORITY
R16 (1016)
MCTL-
MODE CONTROL
R17(1116)
OCASN-
OUTPUT CLOCK ASSIGNMENT
R18 (1216)
CIPTR-
COUNTER INTERRUPT POINTER
R19 (1316)
PDAT-
PORT DATA
R20 (1416)
IPS-
INTERRUPTIPORT SELECT
R21 (1516)
PDIR-
PORT DIRECTION
R22 (1616)
CCTL-
COUNTER CONTROL
R23 (1716)
CICTL-
COUNTER INTERRUPT CONTROL
R25 (1916)
R24 (1816)
LCSV-
L-COUNTER STARTING VALUE
R27 (1816)
R26 (1A16)
HCSV-
H-COUNTER STARTING VALUE
R29 (1016)
R28 (1C16)
LCCV-
L-COUNTER CURRENT VALUE
R31 (1F16)
R30 (1E16)
HCCV-
H-COUNTER CURRENT VALUE
FIGURE 3-1.ICU Internal Registers
4-16
z
3.0 Architectural Description (Continued)
ST1
The BBBB field is the bias which is programmed by writing
BBBB00002 to the SVCT register (R1). The WVV field identifies one of the 16 interrupt positions. The contents of the
HVCT register provide various information to the CPU, as
shown in Figure 3-2:
CPU
.
o
leu
-
N
-""
o
The ELTG registers determine the input trigger mode for
each of the 16 interrupt inputs. Each input is aSSigned a bit
in this register pair. An interrupt input is level-triggered if its
bit in ELTG is set to 1. The input is edge-triggered if its bit is
cleared. At reset, all bits in ELTG are set to 1.
If the auto-rotate priority mode is selected, the FPRT register is also
cleared, thus preventing any interrupt from being acknowledged. In
this case a re-intialization of the FPRT register is required for the
iCU to acknowledge interrupts again.
If odd-numbered interrupt positions must be used for software interrupts, the edge triggering mode must be selected
and the corresponding interrupt inputs should be prevented
from changing state.
= 1 (RETI
3.4 TPL - TRIGGERING POLARITY
REGISTERS (R4, R5)
If the auto-rotate mode is selected, a priority rotation is aiso performed.
The TPL registers determine the polarity of either the active
level or the active edge for each of the 16 interrupt inputs.
As with the ELTG registers, each input is assigned a bit.
Possible triggering modes for the various combinations of
ELTG and TPL bits are shown below.
TPL BIT
TRIGGERING MODE
ELTG BIT
Falling Edge
o
o
Rising Edge
o
1
Low Level
1
o
1
High Level
1
3.2 SVCT - SOFTWARE VECTOR REGISTER (R1)
The SVCT register is a copy of the HVCT register. It allows
the programmer to read the contents of the HVCT register
without initiating a INTA or RETI cycle in the ICU. It also
allows a programmer to change the BBBB field of the HVCT
register. The bit map of the SVCT register is the same as for
the HVCT register.
During a write to SVCT, the four least significant bits are
unaffected while the four most significant bits are written
into both SVCT and HVCT (R1 and RO).
Software interrupt positions are not affected by their TPL
bits. At reset, all TPL bits are set to O.
The SVCT register is updated dynamically by the ICU. The
four least significant bits always contain the vector value
that would be returned to the CPU if a INTA or RETI cycle
were executed. Therefore, when reading the SVCT register,
the state of the CPU ST1 pin is used to select either pending interrupt data or in-service interrupt data. For example, if
the SVCT register is read with ST1 = 0 (as for an INTA
cycle), the VWV field contains the encoded value of the
highest priority pending interrupt. On the other hand, if the
SVCT register is read with ST1 = 1, the VVVV field contains
the encoded value of the highest priority in-service interrupt.
Note 1: If edged-triggered interrupts are to be handled, the TPL register
should be programmed before the ELTG register.
This prevents spurious interrupt requests from being generated during the ICU initialization from edge-triggered interrupt positions.
Note 2: Hardware interrupt inputs connected to cascaded ICUs must have
their TPL bits set to O.
3.5 IPND -INTERRUPT PENDING REGISTERS (RS, R7)
The IPND registers track interrupt requests that are pending
but not yet serviced. Each interrupt position is assigned a bit
in IPND. When an interrupt is pending, the corresponding bit
in IPND is set. The IPND data are used by the ICU to generate interrupts to the CPU. These data are also used in polling operations.
Note: If the CPU ST1 output is connected directly to the ICU ST1 input, the
vector read from SVCT is always the RETI vector. If both the INTA
and RETI vectors are desired, additional logic must be added to drive
the ICU ST1 input. A typical circuit is shown below. In this circuit, the
state of the ICU ST1 input is controlled by both the CPU ST1 output
and the selected address bit.
RETI CYCLE (ST1 = 1)
INTA CYCLE (ST1 = 0)
Highest priority pending interrupt is from:
VVW
N
N
STI
")
3.3 ELTG - EDGE/LEVEL TRIGGERING
REGISTERS (R2, R3)
Note 2: If the HVCT register is read with ST1 = 0 (INTA cycle) and no
unmasked interrupt is pending, the binary value 88881111 is returned and any pending edge-triggered interrupt in pOSition 15 is
cleared.
BBBB
_
I AS OR AS
TL/EE/5117-14
Note 1: The ICU always interprets a read of the HVCT register as either an
INTA or RETI cycle. Since these cycles cause internal changes to
the ICU, normal programs must never read the ICU HVCT register.
If a read of the HVCT register is performed with ST1
cycle), the binary value 88881111 is returned.
en
w
Highest priority in-service interrupt was from:
cascaded ICU
J
any other source
cascaded ICU
1111
I
programmed bias·
1111
encoded value of the highest
priority pending interrupt
I
I
any other source
programmed bias·
encoded value of the highest
priority in-service interrupt
·The Programmed bias for the master ICU must range from 0000 to 01112 because the CPU interprets a one In the most significant bit position as a Cascade Table
Index indicator for a cascaded ICU.
FIGURE 3-2. HVCT Register Data Coding
4-17
"
y
....•
o
N
3.0 Architectural Description
N
N
The IPND registers are also used for requesting software
interrupts. This is done by writing specially formatted data
bytes to either IPND(L) or IPND(H). The formats differ for
registers R6 and R7. These formats are shown below:
o
Cf)
tJ)
Z
IPND(L) (R6) IPND(H) (R7) Where:
S
=
(Continued)
3.7 IMSK -INTERRUPT MASK REGISTERS (R10, R11)
Each NS32202 interrupt position can be individually
masked. A masked interrupt source is not acknowledged by
the ICU. The IMSK registers store a mask bit for each of the
ICU interrupt positions. If an interrupt position's IMSK bit is
set to 1, the position is masked.
SOOOOPPP
S0001 PPP
Set (S
=
1) or Clear (S
=
0)
The IMSK registers are controlled by the system software.
At reset, all IMSK bits are set to 1, disabling all interrupts.
PPP = is a binary number identifying one of
eight bits
Note: If an Interrupt must be masked off, the CPU can do so by setting the
corresponding bit In the IMSK register. However, if an Interrupt Is set
pending during the CPU instruction that masks off that Interrupt, the
CPU may still perform an Interrupt acknowledge cycle following that
Instruction since it might have sampled the INT line before the ICU
deasserted It. This could cause the ICU to provide an Invalid vector.
To avoid this problem, the above operation should be performed with
the CPU Interrupt disabled.
Note: The data read from either R6 or R7 are different from that written to
the register because the ICU returns the register contents, rather than
the formatted byte used to set the register bits.
The ICU automatically clears a set IPND bit when the pending interrupt request is serviced. All pending interrupts in a
register can be cleared by writing the pattern 'X1 XXXXXX'
to it (X = don't care). To avoid conflicts with asynchronous
hardware interrupt requests, the IPND registers should be
frozen before pending interrupts are cleared. Refer to the
Mode Control Register description for details on freezing
the IPND registers.
3.S CSRC - CASCADED SOURCE
REGISTERS (R12, R13)
The CSRC registers track any cascaded interrupt positions.
Each interrupt position is assigned a bit in the CSRC registers. If an interrupt position's CSRC bit is set, that position is
connected to the INT output of another NS322021CU, i.e., it
is a cascaded interrupt.
At reset, all IPND bits are set to O.
Note: The edge sensing mechanism used for hardware Interrupts In the
NS32202 ICU is a latching device that can be cleared only by acknowledging the interrupt or by changing the trigger mode to level
sensing. Therefore, before clearing pending interrupts in the IPND
registers, any edge-triggered Interrupt Inputs must first be switched to
the level-triggered mode. This clears the edge-triggered interrupts;
the remaining interrupts can then be cleared in the manner described
above. This applies to clearing the interrupts only. Edge-triggered interrupts can be set without changing the trigger mode.
At reset, the CSRC registers are set to O.
Note 1: If any cascaded ICU Is used, the CSRC register should be cleared
during Initialization (if the Initialization does not follow a hardware
reset) by writing zeroes into It. This should be done before setting
the bits corresponding to the cascaded Interrupt positions. This operation ensures that the 4-bit in-service counters (associated with
each Interrupt position to keep track of cascaded Interrupts) always
get cleared when the ICU Is re-initialized.
3.6 ISRV - INTERRUPT IN·SERVICE
REGISTERS (RS, R9)
Note 2: Only the Master ICU should have any CSRC bits set. If CSRC bits
are set In a cascaded ICU, incorrect operation results.
The ISRV registers track interrupt requests that are currently being serviced. Each interrupt position is assigned a bit in
ISRV. When an interrupt request is serviced by the ICU, its
corresponding bit is set in the ISRV registers. Before generating an interrupt to the CPU, the ICU checks the ISRV registers to ensure that no higher priority interrupt is currently
being serviced.
The FPRT registers track the ICU interrupt position that currently holds first priority. Only one bit of the FPRT registers
is set at one time. The set bit indicates the interrupt position
with first (highest) priority.
3.9 FPRT -
FIRST PRIORITY REGISTERS (R14, R1S)
The FPRT registers are automatically updated when the ICU
is in the auto-rotate mode. The first priority interrupt can be
determined by reading the FPRT registers. This operation
returns a 16-bit word with only one bit set. An interrupt position can be assigned first priority by writing a formatted data
byte to the FPRT(L) register. The format is shown below:
7
6
5
432
1
0
Each time the CPU executes an RETI instruction, the ICU
clears the ISRV bit corresponding to the highest priority interrupt in service. The ISRV registers can also be written
into by the CPU. This is done to implement the special mask
priority mode.
At reset, the ISRV registers are set to O.
x
Note: If the ICU initialization does not follow a hardware reset. the ISRV
register should be cleared during initialization by writing zeroes into it.
x
x
Where: XXXX =
FFFF =
x
F
F
F
F
Don't Care
A binary number from 0 to 15 indicating the interrupt position assigned first priority.
Note: The byte above is written only to the FPRT(L) register. Any data written to FPRT(H) is ignored.
At reset the FFFF field is set to 0, thus giving interrupt position 0 first priority.
3.10 MCTL -
MODE CONTROL REGISTER (R16)
The contents of the MCTL set the operating mode of the
NS32202 ICU. The MCTL bit map is shown below.
76
543210
4-18
z
tJ)
3.0 Architectural Description (Continued)
CFRZ
CFRZ = 0 =
CFRZ = 1 =
COUTO
>
>
COUTM = 0 =
>
COUTM = 1 =
> Pulsed Form
FRZ = 1 =
>
>
Square Wave Form
NTAR = 1 =
T16N8 = 0 =
L
L
LLLL =
A 4-bit binary number identifying the
interrupt position assigned to the Lcounter.
of a counter output to an interrupt position also requires
to be set in the CICTL register. If a counter output Is
an interrupt position, external hardware Interrupts at that
ignored.
PORT DATA REGISTER (R19)
Used only in the 8-bit Bus Mode. This register controls the
function of the pins GO/IRO, ... ,G7/1R14. Each of these
pins is individually programmed as an I/O port, if the corresponding bit of IPS is 0; as an interrupt source, if the corresponding bit is 1. The assignment of the H-Counter output
to GOIIRO, ... ,G3/1R6 by means of reg. OCASN overrides
the assignment to these pins as 1/0 ports or interrupt inputs.
IPND Frozen
At Reset, all the IPS bits are set to 1.
Note: Whenever a bit in the IPS register is set to zero, to program the
corresponding pin as an 1/0 port, any pending interrupt on the corresponding interrupt position will be cleared.
> Auto-Rotate Mode
> Fixed Mode
3.15 PDIR -
PORT DIRECTION REGISTER (R21)
Used only in the 8-bit Bus Mode. This register determines
the direction of any of the pins GO/IRO, ... ,G7/1R14 programmed as 1/0 ports by the IPS register. A logic 1 indicates an input, while a logic 0 indicates an output.
8-Bit Bus Mode
16-Bit Bus Mode
o.
At Reset, all the PDIR bits are set to 1.
3.16 CCTL -
3.11 OCASN - OUTPUT CLOCK
ASSIGNMENT REGISTER (R17)
Used only in the 8-bit Bus Mode. The four least significant
bits of this register control the output clock assignments on
pins GO/IRO, ... ,G3/1R6. If any of these bits is set to 1, the
clock generated by either the H-Counter or the H + L-Counter will be output to the corresponding pin. The four most
significant bits of OCASN are not used. At Reset the four
least significant bits are set to O.
L
3.14 IPS -INTERRUPTIPORT SELECT REGISTER (R20)
IPND Not Frozen
At reset, all MCTL bits except COUTO, are reset to
COUTO is set to 1.
L
Used only in the 8-bit Bus Mode. This register is used to
input or output data through any of the pins GOI
IRO, ... ,G7/1R14 programmed as 1/0 ports by the IPS register. Any pin programmed as an output delivers the data
written into PDAT. The input pins ignore it. Reading PDAT
provides the logical value of all 1/0 pins, INPUT and OUTPUT.
> Square Wave Form
> Pulsed Form
>
>
H
A 4-bit binary number identifying the
interrupt position assigned to the HCounter (or the H + L-counter if the
counters are concatenated).
3.13 PDAT -
Controls the data bus mode of operation.
T16N8 = 1 =
H
At reset, all bits in the CIPTR are set to 1. (This means both
counters are assigned to interrupt position 15.)
Determines whether the ICU is in the AUTOROTATE or FIXED Priority Mode. In AUTOROTATE mode, the interrupt source at the
highest priority position, after being serviced, is
assigned automatically lowest priority. In this
mode, the interrupt in service always has highest priority and nesting of interrupts is therefore
inhibited.
NTAR = 0 =
H
Where: HHHH =
Note: Assignment
control bits
assigned to
position are
Freeze Bit. In order to allow a synchronous
reading of the interrupt pending registers
(lPND), their status may be frozen, causing the
ICU to ignore incoming requests. This is of special importance if a polling method is used.
FRZ = 0 =
T16N8
H
Used only in the 8-bit Bus Mode. This bit controls the clock wave form on any of the pins
GO/IRO, ... ,G3/1R6 programmed as counter
output.
CLKM = 1 =
NTAR
LCCV and HCCV Frozen
When the COUT/SCIN pin is programmed as
an output (COUTO = 0), this bit determines
whether the output signal is in pulsed form or in
square wave form.
CLKM = 0 =
FRZ
The CIPTR register tracks the assignment of counter outputs to interrupt positions. A bit map of this register is shown
below.
765432
0
LCCV and HCCV Not Frozen
> COUTISCIN is Output
> COUTISCIN is Input
COUTO = 0 =
CLKM
3.12 CIPTR - COUNTER INTERRUPT
POINTER REGISTER (R18)
Determines whether the COUTISCIN pin is an
input or an output. COUT/SCIN should be
used as an input only for testing purposes. In
this case an external sampling clock must be
provided otherwise hardware interrupts will not
be recognized.
COUTO = 1 =
COUTM
W
Note: The Interrupt sensing mechanism on pins GOIIRO, ... ,G311R6 Is not
disabled when any of these pins is programmed as clock output.
Thus, to avoid spurious Interrupts, the corresponding bits In register
IPS should also be set to zero.
Determines whether or not the NS32202 counter readings are frozen. When frozen, the
counters continue counting but the LCCV and
HCCV registers are not updated. Reading of
the true value of LCCV and HCCV is possible
only while they are frozen.
COUNTER CONTROL REGISTER (R22)
The CCTL register controls the operating modes of the
counters. A bit map of CCTL is shown below.
765432
1
0
ICCONlcFNPsicOUT11cOUTOIcRUNHIcRUNLlcDCRHlcDCRLI
CCON
4-19
Determines whether the counters are independent or concatenated to form a single 32-bit
counter (H + L-Counter). If a 32-bit counter is
selected, the bits corresponding to the H-
N
N
o
N
•
....Ao
o
o
,...
•
N
o
3.0 Architectural Description (Continued)
Counter will control the H + L-Counter, while
the bits corresponding to the L-Counter are not
used.
N
N
C")
(/)
Z
CCON
CCON
CFNPS
=
=
0
1
=>
=>
control bits. In this case the CIEL bit should be set to zero to
avoid spurious interrupts from the L-Counter. A bit map of
the CICTL register is shown following.
76543210
Two 16-bit Counters
ICERH ICIRH ICIEH IWENH ICERL ICIRL ICIEL IWENL I
One 32-bit Counter
Determines whether the external clock is
prescaled or not.
CERH
H-Counter Error Flag. This bit is set (1) when a
second interrupt request from the H-Counter
(or H + L-Counter) occurs before the first request is acknowledged.
CIRH
H-Counter Interrupt Request. It is set (1) when
an interrupt is pending from the H-Counter (or
H + L-Counter). It is automatically reset when
the interrupt is acknowledged.
CIEH
H-Counter Interrupt Enable. When it is set, the
H-Counter (or H + L-Counter) interrupt is enabled.
WENH
H-Counter Control Write Enable. When WEHN
is set (1), bits CERH, CIRH, and CIEH can be
written.
CERL
L-Counter Error Flag. This bit is set (1) when a
second interrupt request from the L-Counter
occurs before the first request is acknowledged.
CIRL
L-Counter Interrupt Request. It is set (1) when
an interrupt is pending from the L-Counter. It is
automatically reset when the interrupt is acknowledged.
CIEL
L-Counter Interrupt Enable. When it is set (1),
the L-Counter interrupt is enabled.
WENL
L-Counter Control Write Enable. When WENL
is set (1), bits CERL, CIRL, and CIEL can be
written.
CFNPS = 0 = > Clock Prescaled (divided by 4)
CFNPS = 1 = > Clock Not Prescaled.
COUT1&
COUTO
These bits are effective only when the COUT I
SCIN pin is programmed as an OUTPUT
(COUTD bit in reg. MCTL is 0). Their logic levels are decoded to provide different outputs for
COUTISCIN, as detailed in the table below:
~OUT1 COUTO COUTISCIN Output Signal
0
0
Internal Sampling Oscillator
Zero Detect Of L-Counter
Zero Detect Of H-Counter
Zero Detect Of H + L-Counter*
0
1
0
1
1
1
·If the H- and L-Counters are not concatenated and
COUT1/COUTO are both 1, the COUT/SCIN pin is active
when either counter reaches zero.
CRUNH
Determines the state of either the H-Counter or
the H + L-Counter, depending upon the status
of CCON.
CRUNH = 0 =
Halted
> H-Counter or H + L-Counter
CRUNH = 1 = > H-Counter or H + L-Counter
Running
CRUNL
Effective only when CCON = O. This bit determines whether the L-Counter is running or halted.
CRUNL
CDCRH
=
0
=>
L-Counter Halted
CRUNL = 1 = > L-counter Running
Effective only when CRUNH = 0 (Counter Halted). This bit is the single cycle decrement signal for either the H-Counter or the H + L-Counter.
CDCRH
=
0
= > No Effect
= > Decrement
CDCRH = 1
H + L-Counter
CDCRL
Note: Setting the write enable bits (WENH or WENL) and writing any of the
other CICTL bits are concurrent operations. That is, the ICU will ignore any attempt to alter CICTL bits if the proper write enable bit is
not set in the data byte.
Effective only when CRUNL
=
At reset, all CICTL bits are set to O. However, if the counters
are running, the bits CIRL, CERL, CIRH and CERH may be
set again after the reset signal is removed.
3.18 LCSVIHCSV - L-COUNTER STARTING VALUEI
H-COUNTER STARTING VALUE REGISTERS
(R24, R25, R26, AND R27)
H-Counter or
0 and CCON
The LCSV and HCSV registers store the start values for the
L-Counter and H-Counter, respectively. Each time a counter
reaches zero, the start value is automatically reloaded from
either LCSV or HCSV, one clock cycle after zero count is
reached. Loading LCSV or HCSV from the CPU must be
synchronized to avoid writing the registers while the reloading of the counters is occurring. One method is to halt the
counters while the registers are loaded.
=
O. This bit is the single cycle decrement signal
for the L-Counter.
CDCRL
CDCRL
=
=
0
1
=>
=>
No Effect
Decrement L-Counter
Note: The bits CDCRL and CDCRH are set when a logic 1 is written into
them, but, they are automatically cleared after the end of the write
operation. This is needed to accomplish the decrement operation.
Therefore, these bits always contain 0 when read.
When the 16-bit counters are concatenated, the LCSV and
HCSV registers hold the 32-bit start count, with the least
significant byte in R24 and the most significant byte in R27.
Reset does not affect the CCTL bits.
3.19 LCCVIHCCV - L-COUNTER CURRENT VALUEI
H-COUNTER CURRENT VALUE REGISTERS
(R28, R29, R30, AND R31)
3.17 CICTL-COUNTER INTERRUPT
CONTROL REGISTER (R23)
The LCCV and HCCV registers hold the current value of the
counters. If the CFRZ bit in the MCTL register is reset (0),
these registers are updated on each clock cycle with the
current value of the counters. LCCV and HCCV can be read
only when the counter readings are frozen (CFRZ bit in the
The CICTL register controls the counter interrupts and records counter interrupt status. Interrupts can be generated
from either of the 16-bit counters. When the counters are
concatenated, the interrupt control is through the H-Counter
4-20
z
3.0 Architectural Description
en
w
(Continued)
N
N
o
N
.....•
o
HALT COUNTERS
BY CLEARINO
BITS CRUNL ANO
CRUNH IN
REO. CCTL
WRITE COUNTER'S
STARTING VALUES
INTO LCCV AND
HCCV TO AVOID
LONG INITIAL
COUNTS
RESET COUTO BIT
IN YCTL TO
PROGRAM toUT / SCtN
PIN AS AN OUTPUT
AHD ENABLE THE
INTERNAL INTERRUPT
SAMPLING CLOCK
START COUNTERS
BY SmlNO BITS
CRUNL AND/OR
CRUNH IN REO. ccn
TLlEE/5117-15
FIGURE 3-3. Recommended leU's Initialization Sequence
4-21
....•
Q
N
Q
N
N
CW)
en
z
Status (ST1): Status signal from the CPU. When the Hardware Vector Register is read, this signal differentiates an
INTA cycle from an RETI cycle. If ST1 = 0 the ICU initiates
an INTA cycle. If ST1 = 1 an RETI cycle will result.
Interrupt Requests (IR1, IR3 ••• , IR15): These eight inputs are used for hardware interrupts. Each may be individually triggered in one of four modes: Rising Edge, Falling
Edge, low level, or High level.
Counter Clock (ClK): External clock signal to drive the ICU
internal counters.
3.0 Architectural
Description (Continued)
MCTl register is 1). They can be written only when the
counters are halted (CRUNl and/or CRUNH bits in the
CCTl register are 0). This last feature allows new initial
count values to be loaded immediately into the counters,
and can be used during initialization to avoid long initial
counts.
When the 1S-bit counters are concatenated, the lCCV and
HCCV registers hold the 32-bit current value, with the least
significant byte in R28 and the most significant byte in R31.
4.1.3 Output Signals
Interrupt Output (INT): Active low. This signal indicates
that an interrupt is pending.
3.20 REGISTER INITIALIZATION
Figure 3-3 shows a recommended initialization procedure
for the ICU that sets up all the ICU registers for proper operation.
4.1.4 Input/Output Signals
Data Bus 0';'7 (DO through 07): Eight low-order data bus
lines used in both 8-bit and 1S-bit bus modes.
General Purpose I/O Lines (GOIIRO, G1I1R2, ••• ,G7/
IR14): These pins are the high-order data bits when the ICU
is in the 1S-bit bus mode. When the ICU is in the 8-bit bus
mode, each of these can be individually assigned one of the
following functions:
• Additional Hardware Interrupt Input (IRO through
IR14)
• General Purpose Data Input
• General Purpose Data Output
• Clock Output from H-Counter (Pins GO/IRO through
G3/IRS only)
It should be noted that, for maximum flexibility in assigning
interrupt priorities, the interrupt positions corresponding to
pins GO/IRO, ... ,G7/IR14 and IR1, ... ,IR15 are interleaved.
4.0 Device Specifications
4.1 NS32202 PIN DESCRIPTIONS
4.1.1 Power Supply
Power (Vee): + 5V DC Supply
Ground (GND): Power Supply Return
4.1.2 Input Signals
Reset (RST): Active low. This signal initializes the ICU. (The
ICU initializes to the 8-bit bus mode.)
Chip Select (CS): Active low. This signal enables the ICU to
respond to address, data, and control signals from the CPU.
Addresses (AO through A4): Address lines used to select
the ICU internal registers for read/write operations.
High Byte Enable (HBE): Active low. Enables data transfers on the most-significant byte of the Data Bus. If the ICU
is in the 8-bit Bus Mode, this signal is not used and should
be connected to either GND or Vee.
Read (RD): Active low. Enables data to be read from the
ICU's internal registers.
Write (WR): Active low. Enables data to be written into the
ICU's internal registers.
Counter or Oscillator Output/Sampling Clock Input
(COUT/SCIN): As an output, this pin provides either a clock
Signal generated by the ICU internal oscillator, or a zero
detect signal from one or both of the ICU counters. As an
input, it is used for an external clock, to override the internal
oscillator used for interrupt sampling. This is done only for
testing purposes.
4-22
z
4.0 Device Specifications
en
w
(Continued)
I\)
I\)
oI\)
4.2 ABSOLUTE MAXIMUM RATINGS
Note: Absolute maximum ratings indicate limits beyond
which permanent damage may occur. Continuous operation
at these limits is not intended; operation should be limited to
those conditions specified under Electrical Characteristics.
O°Cto + 70°C
Temperature Under Bias
- 65°C to + 150°C
Storage Temperature
All Input or Output Voltages with
-0.5Vto +7.0V
Respect to GND
1.5 Watt
Power Dissipation
4.3 ELECTRICAL CHARACTERISTICS
TA = 0° to 70°C, Vee = +5V ± 5%, GND = OV
Symbol
Parameter
Conditions
Min
Input Low Voltage
Max
Units
0.8
V
0.45
V
2.0
Input High Voltage
Output Low Voltage
lee
Typ
IOL = 2 rnA
Output High Voltage
IOH = -400 fJ-A
Leakage Current
(Output and I/O Pins in TRI-STATE/lnput mode)
0.4 ::;: VIN ::;: Vee
Input Load Current
Yin = Oto Vee
Power Supply Current
lout = 0, T = O°C
-20
20
-20
20
fJ-A
300
rnA
40"-- Vee
39 ___ IR13
00-2
STlG7I1R14G6I1R12GSIIR10G411R8G311R6G2IIR4GlI1R2GOIIRO0706050403020100GNO-
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
38
37
36
35
NS32202
leu
"--IRll
"--IRS
"--IR7
___ IRS
34....-IR3
33 "--IRl
32-ClJ(
31"-- Wii
3O"--RD
29 "-- CauT I SetH
281-- HBE
27~m
261--A4
25 I-- A3
24~A2
23~Al
22~AO
211--ts
Top View
Order Number NS32202D-6, NS32202D-10
See NS Package Number D40C
FIGURE4-1
4-23
V
2.4
Connection Diagram
IRIS- 1
V
TL/EE/5117 -3
fJ-A
.....
I
o
o
,...
N
o
C'I
C'I
4.0 Device Specifications (Continued)
4.4 SWITCHING CHARACTERISTICS
C")
(/)
Z
4.4.1 Definitions
Abbreviations:
All the timing specifications given in this section refer to
O.BV or 2.0V on the input and output signals as illustrated in
Figure 1, unless specifically stated otherwise.
L.E.-Ieading edge
T.E.-trailing edge
=x
~:: TEST POINTS
~::
TEST POINTS
R.E.-rising edge
F.E.-falling edge
x:
TL/EE/5117-16
FIGURE 4-2. Timing Specification Standard
4.4 ..1.1 Timing Tables
Symbol
Figure
Description
Reference/Conditions
NS32202·10
Min
Units
Max
READ CYCLE
tAhRDia
4-3
Address Hold Time
After RD T.E.
10
tAsRDa
4-3
Address Setup Time
Before RD L.E.
35
ns
tCShRDia
4-3
CS Hold Time
After RD T.E.
15
ns
tCSsRDa
4-3
CS Setup Time
Before RD L.E.
30
tDhRDia
4-3
Data Hold Time
After RD T.E.
tRDaDv
4-3
Data Valid
After RD L.E.
tROw
4-3
RD Pulse Width
At O.BV (Both Edges)
160
ns
tSsRDa
4-3
ST1 Setup Time
Before RD L.E.
ns
tShRDia
WRITE CYCLE
4-3
ST1 Hold Time
After RD T.E.
35
-30
5
ns
ns
50
ns
150
ns
ns
tAhWRia
4-4
Address Hold Time
After WR T.E.
10
ns
tAsWRa
4-4
Before WR L.E.
35
ns
tCShWRia
4-4
Address Setup Time
CSHoldTime
After WR T.E.
15
ns
tCSsWRa
4-4
CS Setup Time
Before WR L.E.
30
ns
tDhWRia
4-4
Data Hold Time
After WR T.E.
10
ns
tDsWRia
4-4
Data Setup Time
Before WR T.E.
70
ns
tWRiaPf
4-4
Port Output Floating
After WR T.E. (To PDIR)
200
ns
tWRiaPv
4-4
Port Output Valid
After WR T.E.
200
ns
tWRw
4-4
WR Pulse Width
At O.BV (Both Edges)
4-24
160
ns
z
4.0 Device Specifications (Continued)
en
w
4.4.1.1 Timing Tables (Continued)
(;)
Symbol
N
N
N
Figure
Description
Reference/Conditions
NS32202-10
Min
Units
Max
OTHER TIMINGS
tcOUTI
4·B
Internal Sampling Clock
low Time
tCOUTD
tSCINh
4·B
Internal Sampling Clock Period
4-7
External Sampling Clock High Time
At 2.0V (Both Edges)
tSCINI
4-7
External Sampling Clock low Time
At O.BV (Both Edges)
tSCIND
tCh
4·7
External Sampling Clock Period
External Clock High Time
(Without Prescaler)
tChp
4·9
External Clock High Time
(With Prescaler)
At 2.0V (Both Edges)
tCI
4·9
At O.BV (Both Edges)
tClp
4·9
External Clock low Time
(Without Prescaler)
External Clock low Time
(With Prescaler)
tey
4·9
External Clock Period
(Without Prescaler)
teyp
4·9
tGCOUTI
4·9
External Clock Period
(With Prescaler)
Counter Output Transition Delay
tCOUTw
4·9
Counter Output Pulse
Width in Pulsed Form
At O.BV (Both Edges)
tACKIA
4·5
Interrupt Request Delay
After Previous Interrupt
Acknowledge
tlAld
4·5
INT Output Delay
After Interrupt
Request Active
tlRw
4·5
Interrupt Request Pulse
Width in Edge Trigger
At O.BV (Both Edges)
RST Pulse Width
At O.BV (Both Edges)
4·9
tRSTw
At O.BV (Both Edges)
At 2.0V (Both Edges)
At O.BV (Both Edges)
50
ns
400
ns
100
ns
100
ns
BOO
ns
100
ns
40
ns
100
ns
40
ns
400
ns
ns
100
After ClK F.E.
300
ns
50
ns
500
ns
BOO
ns
50
ns
400
ns
4.4.1.2 Timing Diagrams
K
)
ADDRESS
ST1~
-IAIRDI-
IShRDii
~ICSIRDI-
C!
-IAIIRDiI-
-ISIRDI-
m
IROw
-ICShRDiI-1
.,~
\
IRDIo.
DATA BUS -
-
-
-
-
-
-
-
-I
-
-
-
-
-
-------------
J:
FIGURE 4-3. READIINTA Cycle
4-25
IohRDia-1
DATAVAUD
----
----
TLlEE/5117-17
.....•
(;)
o
~
S
4.0 Device Specifications (Continued)
C\I
C\I
C")
~
ADDRESS
-tAIIWltia-
DATA BUS
OUTPUT PORT
DATA
DATAVAUD
...................................................................................................................- - J
TL/EE/5117-16
FIGURE 4-4. Write Cycle
o (INTA)
TLlEE/5117-19
FIGURE 4-5. Interrupt Timing in Edge Triggering Mode
IR
iIif
____
~'''x""",,-____r
\~
~r:
\_-_/
1iii(INTA)
FIGURE 4-6. Interrupt Timing in Level Triggering Mode
4-26
TL/EE/5117-20
z
en
w
4.0 Device Specifications (Continued)
I\)
I\)
o
I\)
....o•
CLK
TL/EE/Sl17 -21
Note: Interrupts are sampled on the rising edge of elK.
FIGURE 4-7. Externallnterrupt-Sampllng-Clock to be Provided at Pin COUT/SCIN When In Test Mode
SCLK
TL/EE/Sl17-22
FIGURE 4-8. Internallnterrupt-Sampllng-Clock Provided at Pin COUTISCIN
elK
COUNTER OUTPUT
IN SQUARE - - - - " " WAVEFORM
TL/EE/Sl17-23
FIGURE 4-9. Relationship Between Clock Input at Pin ClK and Counter Output Signals at Pins COUTISCIN or
GO/RO, ... ,G3/R6, In Both Pulsed Form and Square Waveform
II
4-27
C)
,...
r---------------------------------------------------------------------------------~
~ ~National
&l ~ Semiconductor
PRELIMINARY
z
NS32203-10 Direct Memory Access Controller
General Description
Features
The NS32203 Direct Memory Access Controller (DMAC) is
a support chip for the Series 32000 1fil microprocessor family
designed to relieve the CPU of data transfers between
memory and I/O devices. The device is capable of packing
data received from 8-bit peripherals into 16-bit words to reduce system bus loading. It can operate in local and remote
configurations. In the local configuration it is connected to
the multiplexed Series 32000 bus and shares with the CPU,
the bus control signals from the NS32201 Timing Control
Unit (TCU). In the remote configuration, the DMAC, in conjunction with its own TCU, communicates with I/O devices
and/or memory through a dedicated bus, enabling rapid
transfers between memory and I/O devices. The DMAC
provides 4 16-bit I/O channels which may be configured as
two complementary pairs to support chaining.
• Direct or Indirect data transfers
• Memory to Memory, I/O to I/O or Memory to I/O
transfers
• Remote or Local configurations
• 8-Bit or 16-Bit transfers
• Transfer rates up to 5 Megabytes per second
• Command Chaining on complementary channels
• Wide range of channel commands
• Search capability
• Interrupt Vector generation
• Simple interface with the Series 32000 Family of
Microprocessors
• High Speed XMOSTM Technology
• Single + 5V Supply
• 48-Pin Dual-In-Line Package
Block Diagram
A16-A23
REQO
ADO-AD15
ACKO
HBE
ODIN
ADS
Cs
ROY
CLK
BREQ
BGRT
HOLD
HLDA
lORD
IOWR
REQ1
u
C3
g
ACK1
w
u
~
cr::
~
;r:
REQ2
en
~
II)
ACK2
REQ3
iNT
RST/HLT
ACK3
TL/EE/8701-1
4-28
z
Table of Contents
1.0 PRODUCT INTRODUCTION
2.0 FUNCTIONAL DESCRIPTION
2.2 Data Transfer Operations
2.2.1 Indirect Data Transfers
2.2.2 Direct (FLYBY) Data Transfers
2.3 Local Configuration
2.4 Remote Configuration
2.5 Data Source (Destination) Attributes
2.6 Word Assembly/Disassembly
2.7 Auto Transfer
2.8 Search
2.9 Interrupts
2.10 Transfer Modes
2.11 Chaining
2.12 Channel Priorities
3.0 ARCHITECTURAL DESCRIPTION
3.1 Global Registers
3.1.1 CONF - Configuration Register
3.1.2 HVCT - Hardware Vector Register
3.1.3 SVCT - Software Vector Register
3.1.4 STAT - Status Register
3.2 Control Registers
3.2.1 COM - Command Register
3.2.2 SRCH - Search Register
3.0 ARCHITECTURAL DESCRIPTION (Continued)
3.3 Parameter Registers
3.3.1 SRC - Source Address Register
3.3.2 DST - Destination Address Register
3.3.3 LNGT - Block Length Register
4.0 DEVICE SPECIFICATIONS
4.1 NS32203 Pin Descriptions
4.1.1 Supplies
4.1.2 Input Signals
4.1.3 Output Signals
4.1.4 Input/Output Signals
4.2 Absolute Maximum Ratings
4.3 Electrical Characteristics
4.4 Switching Characteristics
4.4.1 Definitions
4.4.2 Timing Tables
4.4.2.1 Output Signals: Internal Propagation
Delays
4.4.2.2 Input Signal Requirements
4.4.2.3 Clocking Requirements
4.4.3 Timing Diagrams
Appendix A: Interfacing Suggestions
en
w
N
N
.
o
W
......
o
List of Illustrations
Power-on Reset Requirements ................................................................................... 2-1
General Reset Timing ..........................................................................................2-2
Recommended Reset Connections ............................................................................... 2-3
Indirect Read Cycle ............................................................................................2-4
Indirect Write Cycle (Single Transfer Mode) ........................................................................ 2-5
Direct Memory-To-I/O Data Transfer (Single Transfer Mode) ......................................................... 2-6
Direct I/O-To-Memory Data Transfer (Single Transfer Mode) ......................................................... 2-7
NS322031nterconnections ......................................................................................2-8
Write to NS32203 Internal Registers ................................................................ ; ............. 2-9
Read from NS32203 Internal Registers .......................................................................... 2-10
NS 32203 Internal Registers .....................................................................................3-1
NS32203 Connection Diagram ...................................................................................4-1
Timing Specification Standard (Signal Valid After Clock Edge) ........................................................ 4-2
Timing Specification Standard (Signal Valid Before Clock Edge) ..................................................... .4-3
Write to DMAC Registers ........................................................................................4-4
Read From DMAC Registers .....................................................................................4-5
Clock Timing .............................................................................................•....4-6
Indirect Write Cycle ............................................................................................. 4-7
Indirect Read Cycle ............................................................................................4-8
Direct I/O-To-MemoryTransfer ..................................................................................4-9
Direct Memory-To-I/O Transfer ................................................................................. 4-10
HOLD/RQ[5A Sequence Start ...•.............................................................................4-11
HOLD/HOLDA Sequence End .................................................................................. 4-12
Bus Request/Grant Sequence Start ......•......•...............................................................4-13
Bus Request/Grant Sequence End ..............................................................................4-14
Ready Sampling ...........•..................................................................................4-15
REOn/ ACKn Sequence (DMAC Initially Not Idle) .................................................................. 4-16
REOn/ACKn Sequence (DMAC Initially Idle) ......................................................................4-17
Halted Cycle .................................................................................................4-18
Interrupt On Match/No Match ..................................................................................4-20
Interrupt On Halt ..............................................................................................4-21
Power-on Reset •.............................................................................................4-22
Non-Power-on Reset ..........................................................................................4-23
NS322031nterconnections in Remote Configuration ................................................................ A-1
4-29
II
III
,....
Q
I
('I')
Q
N
N
('I')
en
z
1.0 Product Introduction
The NS32203 Direct Memory Access Controller (DMAC) is
specifically designed to minimize the time required for high
speed data transfers in a Series 32000-based computer
system. It includes a wide variety of options and operating
modes to enhance data throughput and system optimization, and to allow dynamic reconfiguration under program
control.
begin. A set of registers is provided for each channel to
control the type of operation for that channel.
The NS32203 can operate in two basic system configurations: local and remote. In the local configuration, the DMAC
and the CPU share the same bus (address" data and control) and only one of them can perform data transfers on the
bus at anyone time. In this configuration, the DMAC and the
CPU also share a Timing Control Unit (TCU) and a single set
of address latches. Since this configuration yields a minimum part-count system, it offers a good cost/performance
trade-off in many situations.
Timing and Control Loglc_ This block generates all the
sequencing and control signals necessary for the operation
of the DMAC.
The remote configuration is intended to minimize the CPU
bus use. In this configuration, the NS32203 liD devices and
optional buffer memory have their own dedicated bus (remote bus) so that an liD transfer may be performed without
loading the CPU bus (local bus).
The RST IHlT line serves both as a reset input for the onchip logic and as a DMAC HALT input. Resetting is accomplished by pulling RST/HlT low for at least 64 clock cycles.
Upon detecting a Reset, the DMAC terminates any Data
transfer in progress, resets its internal logic and enters an
inactive state. On application of power, RSTIHlT must be
held low for at least 50 ,..,S after Vee is stable. This is to
ensure that all on-chip voltages are stable before operation.
Whenever reset is applied, the rising edge must occur while
the clock signal on the ClK pin is high (see Figure 2-1 and
2-2). The NS32201 TCU provides circuitry to meet the reset
requirements. Figure 2-3 shows the recommended connections. The HALT function is accomplished when RST/HlT
is activated for 1 or 2 clock cycles and then released. It can
be used to stop any data transfer in progress in case of a
bus error. As soon as HALT is acknowledged by the
NS32203, the current transfer operation is terminated. See
Figure 4-18.
Bus Interface Unit. The bus interface unit controls all data
transfers between peripheral liD devices and memory
whenever the DMAC is in control of the bus. This unit also
controls the transfer of data between the CPU and the
DMAC internal registers.
Priority Resolver. This block resolves contentions among
channels requesting service simultaneously.
2.0 Functional Description
2.1 RESETTING
Communication between the dedicated bus and the CPU
bus may be initiated at any time by either the CPU or the
NS32203. The DMAC accesses the CPU bus whenever a
data transfer tolfrom memory or any liD device residing on
this bus is to be performed. The CPU, in turn, accesses the
dedicated bus for reading status data or for programming
either the DMAC or its liD devices.
The NS32203 internal organization consists of seven functional blocks as illustrated in the block diagram. Descriptions of these blocks are given below.
DMA Channels. The NS32203 provides four channels.
Each channel accepts a request from a peripheral liD device and informs it when data transfer cycles are about to
V
4.5V,~
_________
~~·S""'
_____
CC--./
eLK
s-fLfl
--+---~
~"~O~~~:~l
~-------~50~S------~--~
FIGURE 2-1. Power-On Reset Requirements
4-30
TLlEE/8701-2
z
2.0 Functional Description
en
w
(Continued)
I\)
I\)
o
CLK~~
W
.....
I
o
1--64 CLOCK CYCLES-.!
RS'i'/HIJ--"'~""'~~"""'~\\
55
r
TLlEE/8701-3
FIGURE 2-2. General Reset Timing
Vee
NS32201
TCU
NS32203
Dt.lAC
•
'-• RESET
•
•._-------EXTERNAL RESET
(OPTIONAL)
..
SYSTEt.l RESET
RESET SWITCH
(OPTIONAL)
HALT
(OPTIONAL)
TL/EE/8701-4
FIGURE 2-3. Recommended Reset Connections
2.2 DATA TRANSFER OPERATIONS
Each channel can be programmed for indirect or direct data
transfers. Detailed descriptions of these transfer types are
provided in the following sub-sections.
After the NS32203 has been initialized by software, it is
ready to transfer blocks of data, containing up to 64 kbytes,
between memory and 110 devices, without further intervention required of the CPU. Upon receiving a transfer request
from an 110 device, the DMAC performs the following operations:
2.2.1 Indirect Data Transfers
In this mode of operation, each byte or word transfer between source and destination requires at least two bus cycles. The data is first read into the DMAC and subsequently
it is written into the destination. The bus cycles in this case
are similar to the CPU bus cycles when the MMU is not
used. This mode is slower than the direct mode, but is the
only one that allows some data manipulation like Byte
Search or Word Assembly/Disassembly. Figure 2-4 and 2-5
show the read and write cycle timing diagrams related to
indirect data transfers. If a search operation is specified,
extra clock cycles may be added following each read cycle.
1) Acquires control of the bus
2) Acknowledge the requesting 110 device which is connected to the highest priority channel.
3) Starts executing data transfer cycles according to the values stored into the control registers of the channel being
serviced.
4) Terminates data transfers and relinquishes control of the
bus as soon as one of the programmed conditions is met.
4-31
2.0 Functional Description (Continued)
n
n
T2
T1
T3
T4
I T1
OR
nI
CLK[
A16-23
[~rm.~~~K:::t=E~~CtlX=!
ADO-15 [
lORD [
m[
ACKii[
mnD[~
____~____~__~____-+____~____+-____~
HLDA [
NS32201 SIGNALS
RO[
TL/EE/8701-5
FIGURE 2·4. Indirect Read Cycle
4-32
z
2.0 Functional Description
en
w
(Continued)
N
.
N
TI
ClK [
A16-23 [
ADO-15 [
T1
TI
T2
T3
n-ILrLfL
'hVIIIIII/I 1/111111/
-_IL
VIIt
I T1
T4
ruIL
X
r-
...A.
o
- --
-- --
X
DATA OUT
U
ADS [
1mIR[
HBE [
W
I
~
ADDRESS VALID
ADDR.
OR TI
o
~- -~
1\
.~~
- --
X-
VALID
+
ROY [
1\
IOWR [
ACKn [
I
I
\
I
r
~
WR[
NSF'SiT
TL/EE/8701-6
FIGURE 2·5. Indirect Write Cycle (Single Transfer Mode)
Note: If burst mode is selected. HOLD is released at the end of the transfer operation.
4-33
o'P"
•
C")
2.0 Functional Description
N
N
2.2.2 Direct (Flyby) Data Transfers
UJ
This mode of operation allows a very high data transfer rate
between source and destination. Each data byte or word to
be transferred requires only a single bus cycle instead of
two separate read and write cycles, which are typical of the
indirect mode. The DMAC accomplishes direct data transfers by activating lORD, during memory write cycles, and
10WR, during memory read cycles.
o
C")
Z
(Continued)
direct data transfers. Figures 2-6 and 2-7 show the timing
diagrams of direct memory-to-I/O and I/O-to-memory transfers respectively.
Note 1: In the direct mode each c.hannel can control only one I/O device
because the I/O device is hardwired to the ACKn output of the
corresponding channel. in the indirect mode, a channel can control
multiple devices as long as each device is selected through its own
address rather than the ACKn output. However, the possiblity of
selecting a single I/O device by the ACKn output is maintained in
the indirect mode as well.
An 1/0 device, in the direct mode, is usually enabled by the
proper acknowledge signal (ACKn) from the DMAC. No
search or word assemblyldisassembly are possible during
TI
CLK [
A16-23 [
TI
Note 2: Whenever the DMAC is either idle or is performing indirect transfers,
it generates the lORD and 10WR signals as a replica of RD and WR.
This simplifies the logic required to access 1/0 devices wired for
direct data transfers.
Tl
_rL rL rL
'I/I///////) ~///////i VlJ.
ADDR.
I Tl
T4
ADDRESS VALID
__
.L
:}·W~~ DATA
----
-~-- I-"
x::::
I
~
~
l~
~C ~
U
ADS [
ODIN [
OR TI
rLfl-- n.....rL
.-
ADO-IS [
T3
T2
.~~
HBE [
\
X- -
VALID
'/\
+
ROY [
lORD [
IOWR
!\
[
I
\
ACKn [
I
I
HOLD [
HLDA [
._r\
r
....
NS32201 SIGNtS
RB[
I
I
FIGURE 2-6. Direct Memory-To-I/O Data Transfer (Single Transfer Mode)
4-34
TLlEE/8701-7
z
2.0 Functional Description
en
w
(Continued)
N
even though it is directed to an 110 device and is related to
an indirect data transfer. This causes the system to be quite
sensitive to the volume of data handled by the DMAC. Thus,
the overall system performance decreases as the volume of
data increases. A possible solution to this problem is to use
the remote configuration, described in the following section.
A significant advantage of the local configuration is its simplicity.
2.3 LOCAL CONFIGURATION
As previously mentioned, in the local configuration the
DMAC shares with CPU and MMU the multiplexed address I
data bus as well as the control signals from the NS32201
TCU. A typical local configuration is shown in Figure 2-8.
The DMAC, in the local configuration, must gain control of
the bus whenever a data transfer cycle is to be performed,
n
n
T1
RDY[:.~
lORD [
IOWR[
ACKn [
HOLD[-r____~----~----~----~----~J
HLM[-t____~----~----~----~--~~--~---J
TL/EE/8701-8
FIGURE 2-7. Direct I/O-To-Memory Data Transfer (Single Transfer Mode)
4-35
.
N
C
W
....A.
C
NS32203-10
I\)
N141
Ar/SPC
rLT
RST/ABT
PFS
NS320t6 U/S
ADS
CPU
S1O-3
ROY
HLDA
ODIN
PHil
PHI2
HOLD
INT
Ar/SPC
FLT
RST/ABT
PFS
U/S NS32082
ADS
14I4U
~
STO-3
~
ROY
HLDAI
ODIN
PHil
PHI2
PAY
HOLD
RSTI
r--- HLDAO
A
't
A
~
<'I
lJ
a>
1111
PHI1~
"'L
PHI2
~
NS32201
TCU
ADS
i&
ODIN
ROY
()
CS
r+ RD
r+
-
ViR I--
--
0
4
"4'[
q
-
~TA
T
"
11
~6-2300-1~ ~
,
=
L
~-
CD
ADDR 00-15
~~
(I)
()
...
~
'-
~
7
r-
~
~
-6"
....
0"
00-151\
::
::::s
I'
g>
c:
CD
....
I!JJn
DECODER
O
a:;-
ADMmfU
v~Q
'"'
n
ADDR 00-15
ADDR 00-7
16-BIT I/O
DEVICE
8-BIT I/O
DEVICE
S:
AO-23 ....
v
r--- ~CS
CS
REO
ACKI ~
REOI
ACK2
RE02
ACK3
RE03 ~
lORD
_ _ IO~
RDWR
r-+
BREO
~
~
e!-
14E140RY
WR
...::
'
BUFFERS 'I
'f\-..[},
HLDA
HBE
CS
HOLD
ADS
ACKO
RST
ODIN NS32203
ROY
D14AC REOO
ci"
::::s
HBE
~4J
cm
cm
RD
....
L ~{t-{i5
U~
~
."
C
::::s
.
HBE
A16-23 00-15
<
Q
r
REO
RD WR
I •
~
TL/EE/8701-9
FIGURE 2-8. NS32203 Interconnections In local Configuration
Note 1: The 16 Bit I/O device is wired for direct transfers.
Note 2: The data buffers should not be enabled during direct data transfers or CPU accesses to the DMAC registers.
z
2.0 Functional Description
en
w
(Continued)
The CPU can either be interrupted by BGRf or it can poll
BGRT to determine when the dedicated bus can be accessed. The DMAC, in turn, before accessing the CPU bus,
has to gain control of it. This is accomplished through the
usual request-acknowledge mechanism performed by
means of the HQ[5 and HLDA signals.
Figure A-1 in Appendix A shows an Interconnection diagram
of a basic remote configuration. Both TCUs are clocked by
the same clock signal. They are synchronized during reset
by the RWEi'JISYNC signal so that their output clocks are in
phase. Figures 2-9 and 2-10 show the timing diagrams for
read and write accesses to the NS32203 internal registers.
2.4 REMOTE CONFIGURATION
The remote configuration is intended to minimize CPU Bus
usage. In this configuration, the DMAC, buffer memory and
I/O devices reside on a dedicated bus. Communication between the dedicated bus and the CPU bus is achieved by
means of TRI-STATE buffers. Whenever the CPU needs to
access the dedicated bus, it issues a bus request to the
NS32203 by activating the BREQ signal. As the dedicated
bus becomes Idle, the DMAC pulls off the bus and acknowledges the CPU request by activating BGRf. This output is
also used as a control signal for the interconnection logic of
the two buses.
NS32201 SIGNALS
TL/EE/8701-10
FIGURE 2-9. Write to NS32203 Internal Registers
NS32201 SIGNALS
TL/EE/8701-11
FIGURE 2-10. Read from NS322031nternai Registers
4·37
N
N
o
~
.....
o
....•
2.0 Functional Description
N
N
2.5 DATA SOURCE (DESTINATION) ATTRIBUTES
2.7 AUTO TRANSFER
en
Two types of data source (destination) are recognized: I/O
device and memory. If the source (destination) is an I/O
device, its address register is not changed after a data
transfer; if it is memory, its address register is either incremented or decremented after any data transfer, according
to the value of the corresponding direction bit. In the remote
configuration, any data source (destination) may reside either on the CPU bus or on the dedicated bus. If it resides on
the dedicated bus, the NS32203 does not activate the
HOLD request line when an access to the source (destination) is performed, unless a direct transfer with a data destination (source) residing on the CPU bus is required.
Data can be transferred in either 8 bit or 16 bit units. The
DMAC always considers the memory to be 16 bits wide.
Thus, if an 8 bit transfer is specified, address bit AO will
determine the byte of the data-bus where the transfer takes
place. If AO = 0, the transfer occurs on the low order byte.
If AO = 1, it occurs on the high order byte. Different transfer
widths can be specified for source and destination. However, some limitations exist in specifying these transfer widths
when certain operations must be performed. These limitations are explained below.
The NS32203 initiates a data transfer as a result of a request from an I/O device. In some cases a data transfer
may be necessary without the corresponding request signal
being asserted. This can happen, for example, when a block
of data is to be moved from one memory region to another.
In such cases, the auto transfer mode can be selected by
setting an appropriate bit in the command register. The
DMAC will initiate a data transfer regardless of the REOn
signal for that channel.
C) , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,
C")
C)
C")
z
(Continued)
Note: For proper operation, when auto transfer is required, the low order
byte of the command register (containing the auto·transfer enable bit)
should be written into after the other registers controlling the channel
operation have been initialized.
2.8 SEARCH
The NS32203 provides a search capability that can be used
to detect the occurrence of a certain data pattern. The
search is performed by comparing each data byte with the
search register, in conjunction with the mask register. An
appropriate bit in the command register indicates whether
the search continues 'UNTIL' a match occurs, or 'WHILE' a
match exists. The search operation does not necessarily
involve a data transfer. The DMAC allows a block of data to
be searched without requiring any data transfer between
source and destination. When performing a search, the user
can specify whether or not the matched byte will be transferred. If 'INCLUSIVE SEARCH' is specified (INC = 1), the
matched byte will be transferred, and the channel parameters will be updated accordingly. In this case, if a 16 bit word
has been read from the data source and the search condition is satisfied by the low order byte, then the high order
byte is transferred as well. If 'EXCLUSIVE SEARCH' is
specified (INC = 0), the transfer will terminate with the last
byte before the search condition was satisfied, and the parameters will point to the last transferred byte.
1) If a transfer block has an odd number of bytes or is not
word aligned, an 8 bit width for source and destination
should be selected.
2) 16-bit I/O transfers can not be specified with 8 bit
memory transfers.
3) Memory to memory transfers should have the same
width.
Note 1: If source and destination are both memory, DMAC transfers can
only be performed in indirect mode.
Note 2: If source and destination are both I/O devices and direct mode is
being used, the source device is accessed by lORD and ACKn; the
destination device is accessed by WR (from the NS32201) and CS
(from the address decoder). This allows a one direction data trans·
fer only from one I/O device (source) to another. If data is to be
transferred in both directions in direct mode between two I/O devic·
es, two channels must be used (one for each direction of transfer),
and extra hardware is required to control the read and write Signals
to the two I/O devices.
Search is not possible during direct transfers.
2.9 INTERRUPTS
The NS32203 provides interrupt circuitry that can be used to
generate an interrupt whenever a data transfer is completed
or a search condition is met. If an NS32202 ICU is used, the
INT signal from the DMAC should be connected to an interrupt input of the ICU. When an interrupt occurs and the
corresponding interrupt acknowledge (INTA) or return from
interrupt (RETI) cycle is executed by the CPU, the NS32203
supplies its own vector as if it were a cascaded ICU. For
such operation the virtual address of the interrupt vector
register should be placed in the ICU cascade table, described in the NS32016 and NS32202 data sheets. See
section 3.1.2.
Note 3: When an a·bit transfer is related to an I/O device, the other half of
the l6·bit data bus is considered as DON'T CARE, and the ABE/
signal may be activated.
2.6 WORD ASSEMBLYIDISASSEMBLY
This feature is automatically enabled when indirect transfers
are selected, with data transferred between an 8-bit wide
I/O device and a 16-bit I/O device or memory. For every 16bit I/O device or memory access, the DMAC accesses the
8-bit I/O device twice, assembling two data bytes into a 16bit word or breaking a 16-bit word into two data bytes, depending on the direction of transfer. The word assembly/disassembly feature allows a significant increase in the
transfer speed and minimizes the CPU bus usage when the
transfer occurs between an 8-bit I/O device residing on the
dedicated bus, and a 16-bit I/O device or memory residing
on the CPU bus. Word assembly/disassembly is not possible during direct data transfers.
2.10 TRANSFER MODES
When the NS32203 is in the inactive state and a channel
requests service, the DMAC gains control of the bus and
enters the active state. It is in this state that the data transfer takes place in one of the following modes:
SINGLE TRANSFER MODE
In single transfer mode, the NS32203 makes a single byte
or word transfer for each HOLD/HLDA handshake sequence.
Note: Requests from other channels are not acknowledged in the middle of
a word assembly/disassembly. If this is unacceptable, a bit transfers
should be specified for both source and destination.
In this case the request signal from the I/O device is edge
sensitive, that is, a single transfer is performed each time a
4-38
z
2.0 Functional Description
en
w
(Continued)
The priority resolver checks the priorities on every cycle. If a
channel is being serviced and a higher priority request is
received, the channel operation is suspended and control
passes to the higher priority channel, unless the lock bit for
the lower priority channel is set. If the lock bit is set, that
channel operation is continued until completion before control passes to the higher priority channel. The bus is always
released for at least two clock cycles when control passes
from one channel to another.
falling edge on REOn occurs. To perform multiple transfers,
it is therefore necessary to temporarily deassert REOn after
each transfer is initiated. If auto transfer mode is selected,
the bus is released between two transfers for at least one
clock cycle.
BURST (DEMAND) TRANSFER MODE
In burst transfer mode the DMAC will continue making data
transfers until REOn goes inactive. Thus, the 110 device
requesting service may suspend data transfer by bringing
REOn inactive. Service may be resumed by asserting REOn
again. If the auto transfer mode is selected, the DMAC will
perform a single burst of data transfers until the end-transfer
condition is reached.
Two types of priority encodings are available as software
selectable options.
The first is fixed priority which fixes the channels in priority
order based on the decreasing values of their numbers.
Channel 3 has the lowest priority, while channel 0 has the
highest.
Note 1: In either of the transfer modes described above, data transfers can
only occur as long as the byte count is not zero or a search condition is not met. Whenever any of these conditions occur, the
NS32203 terminates the current operation and releases the bus for
at least one clock cycle.
The second option is variable priority. The last channel that
receives service becomes the lowest priority channel
among all other channels with variable priority, while the
channels which previously had lower priority will get their
priorities increased. If variable priority is selected for all four
channels, any liD device requesting service is guaranteed
to be acknowledged after no more than three higher priority
services have occurred. This prevents any channel from
monopolizing the system. Priority types can be intermixed
for different channels.
Note 2: Whenever the DMAC releases ROCD, it waits for HLDA to go inactive for at least one clock cycle before reasserting ROCD again to
continue the transfer operation.
2.11 CHAINING
The NS32203 provides a chaining feature that allows the
four DMAC channels to be regarded as two complementary
pairs. Channels 0 and 1 form the first pair, while channels 2
and 3 form the second pair. Each pair is programmed independently by setting the corresponding bit in the configuration register. When two channels are complementary, only
the even channel can perform transfer operations, while the
odd one serves as temporary storage for the new control
values and parameters loaded for the chaining operation. If
an operation is being performed by the even channel of a
pair and an end-condition is reached, the channel is not
returned to the inactive state; rather, a new set of control
values with or without parameters is loaded from the complementary channel and a new operation is started. During
the reload operation the bus is released for at least two
clock cycles. At the end of the second operation the channel returns to the inactive state, unless a new set of values
has been loaded into the complementary channel by the
CPU.
As an example, let channels 0, 2 and 3 have variable priority
and channel 1 fixed priority. Channel 2 receives service first,
followed by channel O. The priority levels among all channels will change as follows.
Priority Initial Order Next Order
Final Order
High 3
ch.O ACK ~ ch.O
ch.3
2
ch.1
ch.1 ch.1 ~ fixed priority
1 ACK ~ ch.2
ch.3
ch.2
Low 0
ch.3
ch.2
ch.O
Whenever the PT bit (priority type) in the command register
is changed, the priority levels of all the channels are reset to
the initial order. If only one channel has variable priority,
then no change in priority will occur from the initial order.
Note: If the lock bit is not set, three idle states are inserted between the
write cycle of a previous burst indirect transfer and the next read
cycle.
The chaining feature can be used to transfer blocks of data
tolfrom non-contiguous memory segments. For example,
the CPU can load channel 0 and 1 with control values and
parameters for the first two blocks. After the operation for
the first block is completed by channel 0, the control values
and parameters stored in channel 1 are transferred to channel 0, during an update cycle, and a second operation is
started. The CPU, being notified by an interrupt, can load
channel 1 registers with control values and parameters for
the third data block.
3.0 Architectural Description
The NS32203 has 128 8-bit registers that can be addressed
either individually or in pairs, using the 7 least significant bits
of the address bus and the high byte enable signal HBE.
Seventy-one of these registers are reserved, while the rest
are accessible by the CPU for readlwrite operations. Figure
3-1 shows the NS32203 internal registers together with their
address offsets. Detailed descriptions of these registers are
given in the following sections.
Note 1: Whenever a reload operation occurs, the register values of the com·
plementary channel are affected. Thus, the CPU must always load a
new set of values into the complementary channel if another chain·
ing operation is required.
3.1 GLOBAL REGISTERS
The global registers consist of one configuration, one status
and two interrupt vector registers. They are shared by all
channels, and they control the overall operation of the
NS32203.
Note 2: When the chain option is selected, the CPU must be given the op·
portunity to acquire the bus for enough time between DMAC opera·
tions, in order for the complementary channel to be updated.
2.12 CHANNEL PRIORITIES
The NS32203 has four 110 channels, each of which can be
connected to an liD device. Since no dependency exists
between the different 110 devices, a priority level is assigned to each liD channel, and a priority resolver is provided to resolve multiple requests activated simultaneously.
3.1.1 CONF-Conflguratlon Register
This register controls the hardware configuration of the
NS32203 as well as the chaining feature.
4-39
N
N
.
o
W
-4
o
0
..•
(f)
0
C'I
C'I
(f)
(/)
3.0 Architectural Description
(Continued)
The CONF register format is shown below:
6
4
2
5
7
3
1
0
z
I I I
XXXXX
CNF -
C1
CO
CO
CNF
=
=
0
1
= >
= >
= 0 = > Channels not complementary
= 1 = > Channel 1 complementary to channelO
CNF
Configuration Bit. Determines whether
NS32203 is in local or remote configuration.
CNF
CO-
CO
C1-
the
Local Configuration
Chaining bit for channels 2 and 3. Determines
whether or not channels 2 and 3 are complementary.
C1
Remote Configuration
C1
Chaining bit for channels 0 and 1. Determines
whether or not channel 0 and 1 are complementary.
= 0 = > Channels not complementary
= 1 = > Channel 3 complementary to channel2
XXXXX -
Reserved. These bits should be set to O.
At reset, all CONF bits are reset to zero.
Note: The CNF bit should never be set by the software if the DMAC is wired
for local configuration, otherwise bus conflicts will result.
23
Channel 0
Control
Registers
Channel 0
Parameter
Registers
Channel 1
Control
Registers
Channel 1
Parameter
Registers
Channel 2
Control
Registers
Channel 2
Parameters
Registers
Channel 3
Control
Registers
Channel 3
Parameter
Registers
Global
Registers
{
{
{
{
{
{
{
{
1
COM (H)
SRC(H)
DST(H)
COM (H)
16
(02 16)
COM(M)
(01 16)
7
0
COM(L)
(0016)
Command
SRCH
(04 16)
Search Pattern
MSK
(08 16)
Search Mask
(0016)
SRC(L)
(OC16)
Source Address
DST(M)
(1116)
DST(L)
( 1016)
Destination Address
LNGT(H)
( 1516)
LNGT(L)
( 1416)
Block Length
COM(M)
(21 16)
COM(L)
(20 16)
Command
SRCH
(24 16)
Search Pattern
MSK
(28 16)
Search Mask
(OE16)
SRC(M)
( 12 16)
(2216)
8
15
SRC(H)
(2E 16)
SRC(M)
(20 16)
SRC(L)
(2C 16)
Source Address
DST(H)
(32 16)
DST(M)
(31 16)
DST(L)
(30 16)
Destination Address
LNGT(H)
(35 16)
LNGT(L)
(34 16)
Block Length
COM(M)
(41 16)
COM(L)
(40 16)
Command
SRCH
(4416)
Search Pattern
MSK
(48 16)
Search Mask
COM (H)
SRC(H)
DST(H)
COM(H)
(42 16)
(4E 16)
SRC(M)
(40 16)
SRC(L)
(4C 16)
Source Address
(52 16)
DSC(M)
51 16)
DST(L)
(50 16)
Destination Address
LNGT(H)
(5516)
LNGT(L)
(5416)
Block Length
COM(M)
(61 16)
COM(L)
(60 16)
Command
SRCH
(64 16)
Search Pattern
(62 16)
MSK
(68 16)
Search Mask
SRC(H)
(6E 16)
SRC(M)
(60 16)
SRC(L)
(6C 16)
Source Address
DST(H)
(72 16)
DST(M)
(71 16)
DST(L)
(70 16)
Destination Address
LNGT(H)
(75 16)
LNGT(L)
(74 16)
Block Length
CONF
(78 16)
Configuration
SVCT
(5C 16)
Software Vector
HVCT
(7C 16)
Hardware Vector
STAT(L)
(7E 16)
Status
STAT(H)
(7F 16)
FIGURE 3-1_ NS322031nternai
4-40
eglsters
z
en
Col
3.0 Architectural Description (Continued)
3.1.2 HVCT -
15 14 13 12 11 10
Hardware Vector Register
E
Channel number. Represents the number of the interrupting channel
E-
Error code. Determines whether a normal operation
completion or an error condition has occurred on
the interrupting channel.
channel # 3
TC -
6
5
4
3
2
1
0
channel # 2
channel # 1
channel # 0
Transfer Complete.
Indicates the completion of a channel operation, regardless of the state of the length register or whether
a match/no match condition occurred.
MN -
Match/No Match Bit.
This bit is set when a match/no match condition occurs.
CH -
> Normal Operation Completion
E = 1 = > A second interrupt was generated by
E=0 =
Channel Halted.
Set when a channel operation is halted by pulling the
RST/HLT pin.
the same channel before the first interrupt was serviced.
BIAS -
7
The status of each channel is defined in a four-bit field as
described below:
CN
CN -
8
IMElcHIMNI TC IMEI CHIMNI TclMEI CHIMNI TclMEI CHIMNI Tci
This register contains the interrupt vector byte that is supplied to the CPU during an interrupt acknowledge (INTA) or
return from interrupt (RETI) cycle. The HVCT register format
is shown below.
7
6
543
2
0
BIAS
9
ME -
Programmable bias. This field is programmed by
writing the pattern BBBBBOOO into the HVCT register.
Multiple events. This bit is set when more than one of
the above conditions have occurred.
Note: If an interrupt is enabled, the corresponding bit in the status register is
not cleared upon read, unless the interrupt is acknowledged.
3.2 CONTROL REGISTERS
The NS32203 always interprets a read of the HVCT register
as either an interrupt acknowledge (INTA) cycle or a return
from interrupt (RETI) cycle. Since these cycles cause internal changes to the DMAC, normal programs should never
read the HVCT register (see next section). The DMAC distinguishes an INTA cycle from a RETI cycle by the state of
an internal flip-flop, called Interrupt Service Flip-Flop, that
toggles every time the HVCT register is read. This flip-flop is
cleared on reset or when the HVCT register is written into.
When an interrupt is acknowledged by the CPU, the INT
signal is deasserted unless another interrupt from a lower
priority channel is pending. In this case the INT signal is
deasserted when the acknowledge cycle for the second interrupt is performed.
Each of the four channels has three control registers, consisting of a 24-bit command register, an 8-bit search register
and an 8-bit mask register.
3.2.1 COM - Command Register
The command register controls the operation of the associated channel. It is divided into three separately addressable
parts: COM(L), COM(M) and COM (H). The format of each
part and bit functions are shown below.
COM(L) -
Command Register (Low-Byte)
7
6
5
4
AT
LK
PT
UW
I I I I
For this reason, if the INT signal is connected to an interrupt
input of the NS32202 ICU, the triggering mode of that interrupt position should be 'low level'.
CC -
I
3
INC
Command Code
> Channel Disabled.
> Search
CC = 10 = > Data Transfer
CC = 11 = > Data Transfer and Search
CC = 00 =
CC =01 =
Furthermore, if that ICU interrupt input is programmed for
cascaded operation and nesting of interrupts from other devices connected to the ICU is to be allowed, then the ICU
interrupt input connected to the DMAC should be masked
off during the interrupt service routine, before the CPU interrupt is reenabled. This is because the DMAC does not provide interrupt nesting capability.
01 -
Direct/Indirect Transfers
01 = 0 =
> Indirect Transfers
01 = 1 = > Direct Transfers
An interrupt from a certain channel can be acknowledged
only after the return from interrupt from a previously acknowledged interrupt is performed.
INC -
3.1.3 SVCT - Software Vector Register
UW -
Inclusive/Exclusive Search
INC =0 =
INC = 1 =
UW = 1 =
PT -
PT =0 =
LK -
The status register contains status information of the
NS32203, and can be used when the interrupts are not enabled. Each set bit is automatically cleared when a read
operation is performed. The format of this register is shown
in the following figure.
> Search UNTIL
> Search WHILE
> Fixed
> Variable
Priority lock
LK = 0 =
LK = 1 =
4-41
Inclusive Search
Priority type
PT = 1 =
3.1.4 STAT - Status Register
Exclusive Search
Search type
UW =0 =
The SVCT register is an image of the HVCT register. It is a
read-only register used for diagnostics. It allows the programmer to read the interrupt vector without affecting the
interrupt logic of the NS32203. The format of the SVCT register is the same as that of the HVCT register.
>
>
> Priority Unlocked
> Priority Locked
o
2
I 01
CC
N
N
....o.
o
Col
....o•
3.0 Architectural Description
N
N
AT -
Cf)
o
Cf)
(Continued)
Auto transfer
(J)
Z
AT =0 = > Auto Transfer Disabled
AMN -
Action after Match/No Match
AMN =00 = > Disable Channel
AT = 1 = > Auto Transfer Enabled
AMN = 01 = > Continue
At Reset, the CC bits in COM(L) are cleared, disabling the
channel.
AMN = 10 = > Load Control Values from Complementary Channel and Continue
AMN = 11 = > Load Control Values and Parameters from Complementary Channel
and Continue
Note: The CC bits can be cleared by software during an indirect data trans·
fer to stop the transfer. This, however, should not be done during
direct data transfers. See section 3.3.3.
TCI-
COM(M) - Command Register (Middle-Byte)
76543210
I DO I OW I DL I DT
ST -
TCI = 1 = > Interrupt
I SO I sw I SL I ST I
MNI- Interrupt Mask on "Match/No Match"
Source Type
MNI = 0 = > No Interrupt
ST =0 = >1/0 Device
MNI = 1 = > Interrupt
ST = 1 = > Memory
SL -
HLI-
Source Location
(Effective only in the remote configuration)
3.2.2 SRCH - Search Register
SL =1 = > Remote
This a-bit register holds the value to be compared with the
data transferred during the channel operation.
Source Width
SW = 0 = > a Bits
SW = 1 = > 16 Bits
SO -
3.2.3 MSK - Mask Register
The a-bit mask register determines which bits of the transferred data are compared with corresponding search register bits. If a mask register bit is set to 0, the corresponding
search register bit is ignored in the compare operation. At
reset, all the MSK bits are set to O.
Source Direction
SO =0 =>Up
SO =1 = > Down
DT -
Destination Type
DT = 0 = > 1/0 Device
3.3 PARAMETER REGISTERS
Each channel has three parameter registers, consisting of a
24-bit source address register, a 24-bit destination address
register and a 16-bit block length register.
SO = 1 = > Memory
DL -
Destination Location
(Effective only in the remote configuration)
3.3.1 SRC - Source Address Register
DL =0 = > Local
DL
OW -
The source address register points to the physical address
of the data source. When the data source is an 1/0 device,
the register does not change during the transfer operation.
When the data source is memory, the register is incremented or decremented by either one or two after each transfer.
= 1 = > Remote
Destination Width
OW = 0 = > a Bits
OW = 1 = > 16 Bits
DO -
3.3.2 DST - Destination Address Register
The destination address register points to the physical address of the data destination. When the data destination is
an 1/0 device, the register does not change during the
transfer operation. When the data destination is memory,
the register is incremented or decremented by either one or
two after each transfer.
Destination Direction.
DO =0 = > Up
DO =1 =>Down
COM (H) - Command Register (High-Byte)
7
6
5
I HLII MNII TCII
XTM -
4
AMN
3
2
1
0
3.3.3 LNGT ~ Block Length Register
The block length register holds the number of bytes in the
block to be transferred. It is decremented by either one or
two after each transfer.
IATCI OM I X
Reserved. (Should be set to 0)
Transfer Mode
OM = 0 = > Single Transfer
Note: A direct data transfer can be stopped by writing zeroes into the LNGT
register. The number of bytes transferred can be determined in this
case, from the value of either the SRC or the DST register.
OM = 1 = > Burst Transfer
ATC -
Interrupt Mask on "Channel Halted"
HLI = 0 = > No Interrupt
HLI = 1 = > Interrupt
SL =0 = > Local
SW -
Interrupt Mask on "Transfer Complete"
TCI = 0 = > No Interrupt
Action after Transfer Complete
ATC = 0 = > Disable Channel
ATC = 1 = > Load Control Values and Parameters from Complementary Channel
and Continue
4-42
z
en
w
4.0 Device Specifications
N
4.1. NS32203 PIN DESCRIPTIONS
The following is a brief description of all NS32203 pins. The
descriptions reference portions of the Functional Description, Section 2.0.
Connection Diagram
A22
Vee
A21
A23
A20
Cs
A19
BREQ
A18
BGRT
A17
RST/HlT
A16
iNf
ADIS
HOLD
AD14
HlDA
AD13
REQ3
AD12
ACK3
ADll
REQ2
AD10
ACK2
AD9
REQI
AD8
ACKI
AD7
REQO
AD6
ACKO
ADS
HBE
AD4
ODIN
AD3
lORD
AD2
IOWR
ADI
ADS
ADO
ROY
GND
ClK
o
Ready (RDY): Active high. When inactive, the DMA Controller extends the current bus cycle for synchronization with
slow memory or peripherals. Upon detecting ROY active,
the DMAC terminates the bus cycle.
Channel Request 0-3 (REQO - REQ3): Active low. These
lines are used by peripheral devices to request DMAC service.
o
Bus Request (BREQ): Used only in the remote configuration. This signal, when asserted, forces the DMAC to stop
transferring data and to release the bus. It must be activated
by the CPU before any CPU access to the remote bus is
performed. In the local configuration this signal should be
connected to Vee via a 4.7k resistor. Section 2.4.
Hold Acknowledge (HlDA): Active low. When asserted,
indicates that control of the system bus has been relinquished by the current bus master and the DMAC can take
control of the bus.
Clock (ClK): Clock signal supplied by the CTTL output of
the NS32201 TCU.
4.1.3 OUTPUT SIGNALS
Address Bits 16-23 (A16-A23): Most significant 8 bits of
the address bus.
Hold Request (HOLD): Active low. Used by the DMAC to
request control of the system bus.
Channel Acknowledge 0-3 (ACKO - ACK3): These lines
indicate that a channel is active. When a channel's request
is honored, the corresponding acknowledge line is activated
to notify the peripheral device that it has been selected for a
transfer cycle. Section 2.2.2.
Bus Grant (BGRT): Used only in the remote configuration.
This signal is used by the DMAC to inform the CPU that the
remote bus has been relinquished by the DMAC and can be
accessed by the CPU. Section 2.4.
I/O Read (lORD): Active low. Enables data to be read from
a peripheral device. Section 2.2.2.
I/O Write (IOWR): Active low. Enables data to be written to
a peripheral device. Section 2.2.2.
TL/EE/B701-12
Top View
FIGURE 4-1. NS32203 Dual-ln-L1ne Package
Interrupt (I NT): Active low. Used to generate an interrupt
request when a programmed condition has occurred. Section 2.9.
Order Number NS32203D or NS32203N
See NS Package Number D48A or N48A
4.1.1 SUPPLIES
4.1.4 INPUT/OUTPUT SIGNALS
Power (Vee>: +5V positive supply.
Address/Data 0-15 (ADO-AD15): Multiplexed Address/
Data bus lines. Also used by the CPU to access the DMAC
internal registers.
Ground (GND): Ground reference for on-chip logic.
4.1.2 INPUT SIGNALS
High Byte Enable (HBE): Active low. Enables data transfers on the most significant byte of the data bus.
Address Strobe (ADS): Active low. Controls address latches and indicates the start of a bus cycle.
Reset/Halt (RST/HlT): Active low. If held active for 1 or 2
clock cycles and released, this signal halts the DMAC operation on the active channel. If held longer, it resets the
DMAC. Section 2.1.
Data Direction in (DDIN): Active low. Status signal indicating the direction of data flow in the current bus cycle.
4-43
.
N
Chip Select (CS): When low, the device is selected, enabling CPU access to the DMAC internal registers.
W
-r.
.
C) , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,
.....
C")
C)
C'I
4.0 Device Specifications (Continued)
C\I
4.2 ABSOLUTE MAXIMUM RATINGS
tJ)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
C")
z
Temperature Under Bias
O·C to + 70·C
- 65·C to + 150·C
Storage Temperature
All Input or Output Voltages with
Respect to GND
-0.5Vto +7V
Power Dissipation
1.1 Watt
4.3 ELECTRICAL CHARACTERISTICS T A
Symbol
VOH
ICC
Note: Absolute maximum ratings indicate limits beyond
which permanent damage may occur. Continuous operation
at these limits is not intended; operation should be limited to
those conditions specified under Electrical Characteristics.
=
0 to + 70·C, Vee
=
± 5%, GND =
5V
OV
Conditions
Parameter
Min
Typ
Max
Units
High Level Input Voltage
2.0
Vee + 0.5
V
Low Level Input Voltage
-0.5
0.8
V
IOH
= -
Low Level Output Voltage
IOl
=
Input Load Current
0< VIN ~ Vee
Leakage Current
Output and I/O Pins in TRI-STATE/lnput Mode
0.4 ~ VIN ~ Vee
Active Supply Current
lOUT
High Level Output Voltage
=
0, TA
=
ABBREVIATIONS:
L.E. T.E. -
J
2.0V
O.BV
'\j
SIG1
SIG2
V
-20
20
p.A
-20
20
p.A
300
mA
180
25·C
4.4.1 Definitions
ClK
0.45
2 mA
4.4 SWITCHING CHARACTERISTICS
All the timing specifications given in this section refer to
0.8V and 2.0V on all the input and output signals as illustrated in Figures 4-2 and 4-3, unless specifically stated otherwise.
V
2.4
400 p.A
leading edge
trailing edge
R.E. F.E. -
rising edge
falling edge
ClK ___________2.0V
__
K-
O~.B_V~.~
tSIG11.::::j
tSIG2h
SIG1
O.8V
~~-2.0V
O.BV
tSIG1I 1+-tSIG2h~
SIG2
TL/EE/8701-13
FIGURE 4-2. Timing Specification Standard
(Signal Valid after Clock Edge)
2.0V
TL/EE/8701-14
FIGURE 4-3. Timing Specification Standard
(Signal Valid before Clock Edge)
4-44
z
4.0 Device Specifications (Continued)
en
w
4.4.2 Timing Tables
o
I\)
I\)
w
.....•
4.4.2.1 Output Signals: Internal Propagation Delays, NS32203·10
Maximum Times Assume Capacitive loading of 100 pF.
Name
Figure
o
Referencel
Conditions
Description
NS32203·10
Min
Units
Max
tAlv
4-7
Address Bits 0-15 Valid
After R.E., ClK T1
tAlh
4-9
Address Bits 0-15
Hold Time
After R.E., ClK T2
tAHv
4-7
Address Bits 16-23 Valid
After R.E., ClK T1
tAHh
4-7
Address Bits 16-23 Hold
After R.E., ClK T1
orTi
5
ns
tALAOSs
4-8
Address Bits 0-15 Set Up
Before ADS T.E.
25
ns
tAHAOSs
4-8
Address Bits 16-23 Set Up
Before ADS T.E.
25
ns
tALAOSh
4-9
Address Bits 0-15
Hold Time
After ADS T.E.
15
JLs
tAU
4-8
Address Bits 0-15 Floating
After R.E., ClK T2
25
ns
tev
4-7
Data Valid (Write Cycle)
After R.E., ClK T2
50
ns
tOh
4-7
Data Hold (Write Cycle)
After R.E., ClK T1
orTi
toOv
4-5
Data Valid (Reading
DMAC Registers)
After R.E., ClK T3
tOOh
4-5
Data Hold (Reading
DMAC Registers)
After R.E., ClK T4
tHBEv
4-7
HBE Signal Valid
After R.E., ClK T1
tHBEh
4-7
HBE Signal Hold
After R.E., ClK T1
orTi
tOOINv
4-8
ODIN Signal Valid
After R.E., ClK T1
tOOINh
4-8
ODIN Signal Hold
After R.E., ClK T1
orTi
tAOSa
4-7
After R.E., ClK T1
35
ns
tAOSia
4-7
After R.E., ClK T1
40
ns
tAOSw
4-7
ADS Signal Active
ADS Signal Inactive
ADS Pulse Width
tALz
4-12.4-13
ADO-AD15 Floating
After R.E., ClK Ti
55
ns
tAHz
4-12,4-13
A16-A23 Floating
After R.E., ClK Ti
55
ns
tAOSz
4-12,4-13
ADS Floating
After R.E., ClK Ti
55
ns
tHBEz
4-12,4-13
HBE Floating
After R.E., ClK Ti
55
ns
tOOINz
4-12,4-13
ODIN Floating
After R.E., ClK Ti
55
ns
tHlOa
4-11
HOLD Signal Active
After R.E., ClK Ti
50
ns
tHlOia
4-12
HOLD Signal Inactive
After R.E., ClK Ti
orT4
50
ns
tlNTa
4·19,4-21
INT Signal Active
After R.E., ClK Ti
40
ns
tACKa
4-16,4-17,4-7
ACKn Signal Active
After R.E., ClK T1
50
ns
tACK!a
4-16,4-17,4-7
ACKn Signal Inactive
After F.E., ClK T4
35
ns
atO.8V
(Both Edges)
4-45
50
5
ns
ns
50
ns
ns
0
50
10
50
ns
ns
0
65
0
ns
ns
ns
30
o,..
•
('I)
o
N
N
('I)
en
4.0 Device Specifications (Continued)
Name
Figure
Referencel
Conditions
Description
z
NS32203-10
Min
Units
Max
tSGATa
4-13
BGRT Signal Active
After R.E., ClK
65
ns
tSGATia
4-14
BGRT Signal Inactive
After R.E., ClK
65
ns
tlORDa
4-8,4-9
lORD Active
After R.E., ClK T2
40
ns
tlORDia
4-8
lORD Inactive (During
Indirect Transfers)
After R.E., ClK T4
40
ns
tlOROia
4-9
lORD Inactive (During
Direct Transfers)
After F.E., ClK T4
40
ns
40
ns
40
ns
40
ns
tlOWRa
4-7,4-10
IOWRActive
After R.E., ClK T2
tlOWRia
4-7
IOWR Inactive (During
Indirect Transfers)
After R.E., ClK T4
tlOWRdia
4-10
IOWR Inactive (During
Direct Transfers)
After F.E., ClK T3
4.4.2.2 Input Signal Requirements: NS32203-10
tPWA
4-22
Power Stable to
RST/HlT R.E.
After Vee Reaches
4.75V
tRSTw
4-23
RST IHlT Pulse Width
(Resetting the DMAC)
at 0.8V (Both Edges)
tASTs
4-24
RST IHlT Set Up Time
(Resetting the DMAC)
Before F.E., ClK
tHLTs
4-18
RSTIHlT Setup Time
(Halting a DMAC Transfer)
Before R.E., ClK T3
tHLTh
4-19
RSTIHlT Hold Time
(Halting a DMAC Transfer)
After R.E., ClK T4
50
fLs
64
tCp
15
ns
25
ns
10
ns
tOl s
4-6
Data in Setup Time
Before R.E., ClK T3
15
ns
tOlh
4-6
Data in Hold
After R.E., ClK T4
3
ns
tOl s
4-6
Data in Setup Time
(Writing to DMAC Registers)
After R.E., ClK T3
15
ns
tOlh
4-6
Data in Hold
(Writing to DMAC Registers)
After R.E., ClK T 4
3
ns
tHLOAs
4-11,4-12
HOLDA Setup Time
Before R.E., ClK
25
ns
tHLOAh
4-11
HlDA Hold Time
After R.E., ClK
10
ns
tROYs
4-15
ROY Setup Time
Before R.E.,
ClK T2 orT3
20
ns
tROYh
4-15
ROY Hold Time
After R.E., ClK T3
5
ns
tREOs
4-16,4-17
REQn Setup Time
Before R.E., ClK
50
ns
tAEOh
4-16,4-17
REQn Hold Time
After R.E., ClK
10
tSAEOs
4-13
BREQ Setup Time
Before R.E., ClK
25
4-46
ns
z
en
w
4.0 Device Specifications (Continued)
Name
Figure
N
N
Referencel
Conditions
Description
NS32203·10
Min
Units
o
BREQ Hold Time
After R.E., ClK
10
ns
tALAoSis
4-6
Address Bits 0-5 Setup
Before ADS T.E.
20
ns
tALAoSih
4-6
Address Bits 0-5 Hold
After ADS T.E.
20
ns
tHBEs
4-6
HBE Setup Time
Before R.E., ClK T1
10
ns
tHBEih
4-6
HBE Hold Time
After R.E., ClK T4
40
ns
tAoSs
4-6
ADS L.E. Setup Time
Before R.E., ClK T1
40
ns
tAoSiw
4-6
ADS Pulse Width
ADS L.E. to ADS T.E.
35
ns
tCSs
4-6
CS Setup Time
Before R.E., ClK T1
15
ns
tCSh
4-6
CS Hold Time
After R.E., ClK T4
40
ns
too INs
4-6
DDIN Setup Time
Before R.E., ClK T2
30
ns
toolNh
4-6
DDIN Hold Time
After R.E., ClK T4
40
ns
4.4.2.3 Clocking Requirements: NS32203-10
Name
Figure
Referencel
Conditions
Description
NS32203-10
Min
Units
Max
tClKh
4-4
Clock High Time
At 2.0V (Both Edges)
42
ns
tClK1
4-4
Clock low Time
At O.BV (Both Edges)
42
ns
tClKp
4-4
Clock Period
R.E., ClK to Next
R.E. ClK
100
ns
4.4.3 Timing Diagrams
tcLKp
tcLKh
elK
2.0V
C.BV
tCLKI
TL/EE/8701-17
FIGURE 4-4. Clock Timing
4-47
W
....Ao
Max
4-13
tBREQh
.
o
....o•
Cf)
o
4.0 Device Specifications (Continued)
N
N
Cf)
Tl
U)
Z
T2
T3
elK [
ADS [
ADO-IS [
ODIN [
HBE[~,~__~__________~______,~
cs[
TL/EE/8701-18
FIGURE 4-5. Read from DMAC Registers
Tl
T2
T3
T4
I Tl
OR
n
ODIN [
TL/EE/8701-15
FIGURE 4-6. Write to DMAC Registers
4·48
zen
4.0 Device Specifications (Continued)
w
N
.
N
T1
T2
T3
o
W
T4
.....
o
ROY [
IOWR [
TL/EE/B701-18
FIGURE 4·7. Indirect Write Cycle
ROY [
(HIGH)
IOWR [
(HIGH)
I
tlORDla
lORD [
ACKn [
TL/EE/B701-19
FIGURE 4·8. Indirect Read Cycle
4-49
o"PI
C")
o
4.0 Device Specifications (Continued)
'"
'"
en
I
C")
z
T1
T2
T3
T4
eLK [
ADO -15
[~,"-_ _~
A 16- 23 [-+-",'--+--+------+--+--10,,"ADS [
HBE[~,--~-----+--+-~~
ODIN [
ROY [
lORD [
IOWR [
ACKn [
TL/EE/8701-20
FIGURE 4-9. Direct 1/0 to Memory Transfer
T1
T3
T2
T4
CLK [
ADO-15 [
A 16-23 [
ADS [
HBE [
ODIN [
(HIGH)
ROY [
I
lORD [
tlOWRdla
IOWR [
ACKn [
TL/EE/8701-21
FIGURE 4·10. Direct Memory to 1/0 Transfer
4·50
z
en
w
4.0 Device Specifications (Continued)
I
n
I n
ClK[~
N
N
n
.
o
I n
W
T2
Tl
-&.
o
tHlD~
HOLD [
HlDA [
ADO-1S[-
------~
A 16-23 [ .
- - - - - -
AOS[-
----
rvfADDRESS VALID
H8E [ •
ODIN [ .
I
<
VALID
- - - -
- - - -
- - - -
VALID
TL/EE/8701-22
FIGURE 4·11. HOLD/HOLDA Sequence Start
T1
I
T2
T3
I
T4
n
ClK [
HOLD [
HlDA[
ADO-IS [
A 16-23[
ADS [
H8E[
TL/EE/8701-23
FIGURE 4·12. HOLD/HOLDA Sequence End
Note 1: DMAC in local configuration.
Note 2: The FiOID/HOLDA sequence shown above is related to the single transfer mode.
In burst transfer mode FiOID is deactivated two cycles later.
4-51
o
,....
S
4.0 Device Specifications (Continued)
N
N
~
I
n
I
n
I
n
I
n
ClK[..rt...nJ.LrL
Z
~BREOS
tBREOh
BREO [
BGRT [
ADO -15
[+ __-+-.....~\-+-_--!J
A16 -23
[-+----t--~ 'r-t----+'
ADS [
HBE
[~---+-~'H---I-"
DDIN
[-+----t--~ 'r-+----+'
TLlEE/B701-24
FIGURE 4·13. Bus Request/Grant Sequence Start
ClK [
n
I n
n
n
11
T2
BREQ [
BGRT [
ADO-IS [ -
------~
A 16-23[ -
------<
I
- - rvfADDRESS VALID
ADS [ .
HBE [ .
- - - -
- - - -
- - - -
- - - - - -
<
VALID
DDIN [ .
- - - -
- - - -
- - - -
- - - - - -
<
VALID
TLlEE/B701-25
FIGURE 4·14. Bus Request/Grant Sequence End
Note 1: DMAC in remote configuration.
Note 2: If BREQ is asserted in the middle of a DMAC transfer, the transfer will always be completed.
4·52
z
en
w
4.0 Device Specifications (Continued)
I
T1
I
T2
I
N
N
T3
CLK~
[
I
T3
I
o
T3
....o•
W
T4
R~[~JJi-~ ~tRDTh
TL/EE/8701-26
FIGURE 4-15. Ready Sampling
T3
T4
Tl
T2
I
T3
T4
REOn [
ACKn [
ADS [
TL/EE/8701-27
FIGURE 4-16. REQn!ACKn Sequence (DMAC Initially Not Idle)
I
TI
I
TI
CLK~
[
I
T1
T2
I
T3
T4
tREOs
TL/EE/8701-28
FIGURE 4-17. REQn! ACKn Sequence (DMAC Initially Idle)
4-53
....o.
C")
o
4.0 Device Specifications
(Continued)
N
N
C")
T1
U)
Z
I
T2
I
T3
T4
I n
elK [
ADS [
RST/HLT [
DDIN [
HOlD[
TL/EE/B701-29
FIGURE 4·18. Halted Cycle
Note 1: Halt may occur in previous T·States. It must be applied for 1 or 2 clock cycles.
Note 2: If BREQ is asserted in the middle of a DMAC transfer, the transfer will always be completed.
T1
T2
I
T3
I
T4
I n
n
ADS [
IN{
TL/EE/B701-30
FIGURE 4·19. Interrupt on Transfer Complete
4·54
z
en
w
I\,)
4.0 Device Specifications (Continued)
.
I\,)
T1
I
T2
T3
I
n
I n
T4
I n
o
w
n
-'"
o
ADS [
iID[
t lNTa
• MATCH ON
'.HIGH BYTE
iNr[
TL/EE/8701-31
FIGURE 4-20. Interrupt on MatchINo Match
Note: If inclusive search is specified a write cycle is performed before INT is activated.
T1
T2
I
T3
I
T4
I n
ClK [
ADS [
iID/WR [
RST/HlT [
iNr[
TL/EE/6701-32
FIGURE 4-21. Interrupt on Halt
Vee
elK
RST/HLT
4.SV
-~I--""
s-IL
tpWR~
------------------srJf
TL/EE/8701-34
TL/EE/6701-33
FIGURE 4-23. Non Power on Reset
FIGURE 4-22. Power on Reset
4-55
NS32203-10
l>
DATA BUFmIS
..
-~
"'i:,'~-" •
::::~,;,«
± = CW~
HOlD
iiIiiI RST/ABT
~
~;
f
~Q
:1
i
J
~
RSTO
DBE
RS11 XII
~:~~~
-LPrrD-
-,-
ex
r---
em
"K
occao I
~Q p..
ex
4
1-..+
JD/WRj
fiBr,lCiAlf
~ ~
~gr ~-=r 0__~ ~~;v
tn
0>
HOlD HlDABRt08GRT
RSf/~~
ClJ(
ROY
"='
a
:: --,,;:
ACK3
AI6-23
i~ ~
.... :
~:
em
ROY
-
ADDRESS
DECODER
I~
~L
IS
>C.
1>
......
::::s
CD
.....
D)
()
c
CO
CO
CD
...enO·
::::s
en
L.-
~"'~
~.
~1:~!:IIIIIJS
~
~
RD
DBE
Co
en
7
r !q~
'-;;"'~
I
::::s
S·
~;-
_
'0
'0
CD
CO
~~----,
"':L
~-+M~j
~
J~
~~nb
rL--. ~~
H~-+--f----+---t-HttI---oI..L~t:::=J
-=rJ
su-- 'LJ
--'
.;>.
a~
SlDWAC
~
.. r 0iB£
•...",
I I · ~}
--'-
'" -~
U
--~
~~.
., •
~l
=
"""'i~T-----
~~"=. ~ •
~
..:~
-~
_~,,_
ROIQTE ADDRESS BUS
aHBE
IJ
_
Ell
>-
•
_
l1li
~
--~
•
• _~,.
>
:~
..
,)
..
TUEE/8701-35
FIGURE A-1. NS32203 Interconnections in Remote Configuration.
Note: This logic does not support direct (flyby) DMAC transfers.
z
en
PRELIMINARY w
N
o
C)
~National
D Semiconductor
Q)
N
...&.
NS32CG821 microCMOS Programmable
1M Dynamic RAM Controller/Driver
General Description
Features
The NS32CG821 dynamic RAM controller provides a low
cost, single chip interface between dynamic RAM and the
NS32CG16. The NS32CG821 generates all the required access control signal timing for DRAMs. An on-chip refresh
request clock is used to automatically refresh the DRAM
array. Refreshes and accesses are arbitrated on chip. If
necessary, a WAIT output inserts wait states into memory
access cycles, including burst mode accesses. RAS low
time during refreshes and RAS precharge time after refreshes and back to back accesses are guaranteed through the
insertion of wait states. Separate on-chip precharge counters for each RAS output can be used for memory interleaving to avoid delayed back to back accesses because of
precharge.
• Allows zero wait state operation
• On chip high precision delay line to guarantee critical
DRAM access timing parameters
• microCMOS process for low power
• High capacitance drivers for RAS, CAS, WE and DRAM
address on chip
• On chip support for page and static column DRAMs
• Byte enable signals on chip allow byte writing with no
external logic
• Selection of controller speeds: 20 MHz and 25 MHz
• On board access refresh arbitration logic
• Direct interface to the NS32CG 16 microprocessor
• 4 RAS and 4 CAS drivers (the RAS and CAS configuration is programmable)
Control
# of Pins
# of Address
(PLCC)
Outputs
68
10
NS32CG821
Largest
DRAM
Possible
Direct Drive
Memory
Capacity
1 Mbit
8 Mbytes
Block Diagram
NS32CG821 DRAM Controller
BANK ADDRESS IN ............,.'---I~I
ROW ADDRESS IN
--+--+---I~I
COLmAN ADDRESS IN
--+-.....,.'-t~1
MODE LOAD
-+---I~I
ADDRESS
OUT
....._-"r"""'f-_-..Ii
CONTROL INPUTS
SYSTEt.4 CLOCK
RASO-3
CASO-3
FIGURE 1
4-57
TL/F/l0126-1
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~National
PRELIMINARY
~ Semiconductor
HPC16083/HPC26083/HPC36083/HPC460831
HPC16003/HPC26003/HPC36003/HPC46003
High-Performance microControliers
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General Description
Features
The HPC16083 and HPC16003 are members of the HPCTM
family of High Performance microControllers. Each member
of the family has the same core CPU with a unique memory
and I/O configuration to suit specific applications. The
HPC16083 has 8k bytes of on-chip ROM. The HPC16003
has no on-chip ROM and is intended for use with external
direct memory. Each part is fabricated in National's advanced microCMOS technology. This process combined
with an advanced architecture provides fast, flexible I/O
control, efficient data manipulation, and high speed computation.
• HPC family-core features:
- 16-bit architecture, both byte and word
-16-bit data bus, ALU, and registers
- 64k bytes of external direct memory addressing
- FAST-200 ns for fastest instruction when using
20.0 MHz clock, 134 ns at 30 MHz
- High code efficiency-most instructions are single
byte
- 16 x 16 multiply and 32 x 16 divide
- Eight vectored interrupt sources
- Four 16-bit timer/counters with 4 synchronous outputs and WATCHDOG logic
- MICROWIRE/PLUS serial I/O interface
- CMOS-very low power with two power save modes:
IDLE and HALT
• UART-full duplex, programmable baud rate
• Four additional 16-bit timer/counters with pulse width
modulated outputs
• Four input capture registers
• 52 general purpose I/O lines (memory mapped)
• 8k bytes of ROM, 256 bytes of RAM on chip
• ROMless version available (HPC16003)
• Commercial (O°C to + 70°C), industrial (- 40°C to
+ 85°C), automotive (-40°C to +105°C) and military
( - 55°C to + 125°C) temperature ranges
The HPC devices are complete microcomputers on a single
chip. All system timing, internal logic, ROM, RAM, and I/O
are provided on the chip to produce a cost effective solution
for high performance applications. On-chip functions such
as UART, up to eight 16-bit timers with 4 input capture registers, vectored interrupts, WATCHDOGTM logic and MICROWIRE/PLUSTM provide a high level of system integration.
The ability to address up to 64k bytes of external memory
enables the HPC to be used in powerful applications typically performed by microprocessors and expensive peripheral
chips. The term "HPC16083" is used throughout this datasheet to refer to the HPC16083 and HPC16003 devices unless otherwise specified.
The microCMOS process results in very low current drain
and enables the user to select the optimum speed/power
product for his system. The IDLE and HALT modes provide
further current savings. The HPC is available in 68-pin
PLCC, LCC, LOCC, PGA and 84-Pin TapePak® packages.
.....
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::z: Block Diagram (HPC16083 with 8k ROM shown)
~-----------------------~
, 't t
ROY 1l[Jj Iimf STATUS
CKICKDCK2
I ______ --------------~~~~~
4-58
TL/DD/BB01-1
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o
DP8510 BITBLT Processing Unit
General Description
Features
The DP8510 BITBLT Processing Unit (BPU) is a high-performance microCMOS device designed for use in raster
graphics applications. It implements, in high-speed pipe lined
logic, the data operations which are fundamental to BITBLT
(BIT boundary Block Transfer) graphics: shifting, masking
and bitwise logic operations. Under control of external hardware such as a state machine or a general-purpose microprocessor, it provides all necessary data path operations,
easing the implementation of a wide variety of BITBLT systems. A number of input pins control the proper data flow in
the BPU. A simple handshake scheme is used to interface
the CPU, the BPU and the memory system.
The BPU has two modes, BITBLT and line drawing. The
mode is set by the elL pin. The line-drawing mode can be
treated as a special case BITBLT with height and width
equal to one.
• Supports all 16 classical BITBLT functions
• Pipelined data input for high system throughput
• Flexible architecture allows BPU to be used with a
state machine or processor
• Multiple BPUs can be used for multiple bitplanelcolor
applications
• Line drawing support
• Compatible with static or dynamic RAMs, including
Video DRAMs
• Compatible with page mode, nibble mode and static
column RAMs
• 32-bit to 16-bit barrel shifter
• 16-bit data port
• 16-word FIFO
• 16-bit logic operations
• 20 MHz operation
• Single + 5 volt supply
• All inputs and outputs TTL-compatible
• Packaged in a 44-pin PCC (commercial) or 44-pin PGA
(MIL)
• Single-bit pixel 1/0 port
• A member of National's Advanced Graphics Chip Set
• microCMOS technology
In order to perform a BITBLT operation, the BPU's control
register must first be loaded with four parameters: the shift
number, left and right masks and the function select code, a
total of 16 bits. BITBLT can then proceed, as directed by an
external processor or state machine. It is the responsibility
of the controller to generate appropriate addresses for the
BITBLT, to interface with the frame buffer's memory control
circuitry, and to control the BPU itself.
Block Diagram
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~ Semiconductor
DP8511 BITBLT Processing Unit (BPU)
General Description
The DP8511 BITBLT Processing Unit (BPU), a member of
National Semiconductor's Advanced Graphics Chip Set
(AGeS), is a high performance microCMOS device intended
for use in raster graphics applications. Specifically designed
to complement the DP8500 Raster Graphics Processor
(RGP), the BPU performs data operations that are elementary to BITBLT (BIT boundary Block Transfer) graphics:
Shift, mask, and bitwise logical manipulation of memory. Under the control of the RGP, the BPU performs the necessary
BITBLT data path operations at pipelined hardware speeds.
A simple set of control lines interfaces the BPU to the RGP
and to the system memory.
The BPU has two modes of operation: BITBLT and Line
Drawing. BITBLT performs shift and logical operations on
blocks of 16-bit data words. Line drawing performs similar
operations on single-bit pixel data by utilizing a single bit
pixel port (PDn). This port allows data read and read-modifywrite operations on single pixels across a number of bitplanes, giving access to pixel depth. The BPU provides both
pixel level processing commonly used in image processing
applications and extremely fast planar operations used
most frequently in color graphics.
pendent of the CR, so that multiple bitplanes can be updated Simultaneously while each BPU performs different logical
operations on its own destination data.
Features
• Interfaces directly to the DP8500 Raster Graphics
Processor or any general purpose controller
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
The BPU's operation is controlled by the values loaded to
the Control Register (CR) and the Function Select Register
(FSR). This dual register configuration of the DP8511 allows
for high throughput in multi-plane systems that incorporate a
BPU per plane. This performance advantage is achieved by
allowing the flexibility of changing the FSR's contents inde-
20 MHz operation
Supports all 16 classical BITBLT functions
Pipe lined data input for high system throughput
Provides performance independent of the number of
bitplanes
Line Drawing support
Compatible with static, dynamic RAMs, and Video
RAMs
Compatible with page mode, nibble mode and static
column RAMs
32-bit to 16-bit barrel shifter
16-bit data port, Single bit pixel port
16-word FIFO
16-bit logic operations
Single + 5V supply
All inputs and outputs TTL compatible
2 micron microCMOS technology
Packaged in a 44-pin PCC (commercial) or 44-pin PGA
(MIL)
Connection Diagrams
44-Pln Plastic Chip Carrier (PCC)
~
~
~ 6
5
IW WIWIW
~ If
4
r'tf J 't Ttl
3
2
N
~
~
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1 «43 42 41 40
06- 7
39 -09
05- 8
38 -010
LVCC - 9
04- 10
37 - BGN02
36 -LGNo
BGND3- 11
35 -011
03 - 12
34
i-
BVCCI
33 I- 012
BVCCO - 13
02- 14
321-BGNol
BGNoo- 15
311-013
01- 16
301-014
00- 17
29 r-015
18 19 20 21 22 23 24 25 26 27 28
TL/F/9337-1
N.C. = No Connection
Top View
Order Number DP8511V
See NS Package Number V44A
4-60
Section 5
Development Systems
and Software Tools
Section 5 Contents
NS32CG161SE Development Tool...................................................
SYS32/30 PC-Add-In Development Package ..........................................
Series 32000 GENIX Native and Cross-Support (GNX) Development Tools (Version 3) ......
Series 32000 GNX-Version 3 C Optimizing Compiler ....................................
Series 32000 GNX-Version 3 Fortran 77 Optimizing Compiler. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Series 32000 GNX-Version 3 Pascal Optimizing Compiler................................
5·2
5-3
5-10
5-16
5-21
5-25
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NS32CG16 ISE Development Tool
TLlEE/10334-4
•
•
•
•
•
hardware breakpoints based on
• Two
events
2k deep, event triggered, real time, trace
• display
in mnemonic and machine
NS32CG 16 emulator for software and
hardware development and debugging
512 kbytes of mappable memory for
emulation
15 MHz, 0 wait state access to emulation
memory
Sixteen definable events-match on
address and data, no match on address
and data and match on status conditions
(address fetch, data read/write, slave
cycle and interrupt acknowledge)
Thirty-six software breakpoints using
NS32CG16's BPT instruction
•
•
•
•
•
formats
Execution time measurement with 1 ,...,s
resolution
On screen menu for command selection
FPU (Floating Point Unit) and BPU (Bit
Aligned Block Transfer Processing Unit)
support
Software support via GNXTM tools
Includes PC interface board and cable
1.0 Product Overview
The NS32CG 16 ISE is a full featured emulator for the
development of NS32CG 16 based systems. The emulator works with SYS32/20 and SYS32/30 hosts. Up
to 512 kbytes of memory ·may be mapped onto the
target, allowing users to download their software into
mapped (or emulation) memory. The emulator supports single stepping, 36 software breakpoints and 2
hardware breakpoints based on any of sixteen pre-
defined events. Events may be defined as match on
address & data, no match on address & data and
match on status conditions (address fetch, data readl
write, slave cycle and interrupt acknowledge). A 2k
deep real time trace may be triggered by any of the
sixteen pre-defined events and displayed in mnemonic or machine formats. The emulator supports execution time measurement with a resolution of 1 p.s.
5-3
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1.0. Product Overview (Continued)
The emulator connects to a high speed parallel interface board on the development system host. The emulator connects to the target system via a probe unit
and target cable. An IC plug at the end of the target
cable fits into the CPU socket on the target board. The
probe unit contains an NS32CG16 microprocessor for
emulation.
The emulator software resides in a DOS environment
on the host. The emulator runs from a DOS environment on the host. An on-screen menu enables command selection.
Commands supported by the emulator include:
Program down-loading
Assembly language debugging
Symbolic access to program variables
Modification of CPU registers and Memory locations
FPU and BPU slave processor support
Single stepping and software breakpoints
Trace display
On-screen command prompting facility
Full software support is provided by National's GNX
tools in the UNIX® environment of the SYS32/20 or
SYS32/30 host. The object files produced by the
compilation (or assembly) and linking process in the
UNIX environment may be converted into DOS-format
files and loaded into the emulator.
2.0 Description of Features
The NS32CG16 ISE consists of a main emulator unit,
a probe unit with target cable and IC plug, an interface
cable and PC interface board that resides on the host.
Figure 1 shows a pictorial view of the emulator.
Ho.
1
2
3
4
5
6
7
8
9
10
11
12
Items
PC/AT keyboard
IBt.I-PC/AT
Display
Target systlm
Probe unit
Main unit
Interface board
Interface cable
Power cable
Probe cable
Tafltlt cable
IC plug
TL/EE/10334-1
FIGURE 1. NS32CG16 Emulator System
5-4
z
2.0 Description of Features (Continued)
2.1 NS32CG161SE System Configuration
Sixteen events may be defined based on the following:
match on address and data
no match on address and data
match on status conditions (address fetch, data
read/write, slave cycle and interrupt acknowledge)
In specifying the formats for the address and data, for
example, any combination of Os, 1s or Xs (don't cares)
may be used. For example FFXO or XXFF (in hexadecimal) are valid formats for specifying address and
data.
All symbolic information in the source program is retained during debugging.
The emulator software resides in a DOS environment
on the system host. The emulator runs from the DOS
environment and may be invoked from the DOS directory in which the emulator software resides and commands may then be issued to control the operating
mode of the emulator. An on-screen menu enables
selection of commands with prompting facility. Commands are provided to download, execute and debug
programs. The command structure supports symbolic
access to program variables.
Software support is provided by National's GNX tools
in the UNIX environment on the SYS32 host. A user
program may be edited, compiled and linked in this
environment to obtain an executable object file. The
object file may then be converted into DOS-format
and copied into the DOS environment, by using the
udcp (UNIX to DOS copy) utility in the UNIX environment. This resulting DOS-format file may be directly
loaded into emulation memory by emulator commands. The ducp (DOS to UNIX copy) utility may be
used (in the UNIX environment) to convert files in the
DOS-format (in the DOS environment) to UNIX-format
(in the UNIX environment). Both udcp and ducp also
support conversion of ASCII files.
Figure 2 shows the NS32CG16 ISE system configuration.
2.2 Description of the System
The development system consists of the SYS32/20 or
SYS32/30 host computer with the emulator interface
board, the emulator and probe units and the IC plug
(located at the end of the target cable) which fits into
the CPU socket on the target board. The emulator
SCSI interface board enables high speed parallel
communication between the emulator and the host.
The probe unit contains an NS32CG16 microprocessor for emulation.
The emulator unit consists of Controller, Memory,
Trace and Breakpoint and Probe Interface boards.
The Controller board communicates with the SCSI interface on the host and with all other boards in the
emulator unit. The Probe Interface board communicates with the probe unit.
The Memory Board provides 512 kbytes of emulation
memory, with O-wait state access at 15 MHz. Sixteen
memory partitions may be mapped in 4 kbyte blocks
with write protection capability. 4 kbytes of the available memory is used by the emulator's monitor, and
the remaining memory may be used for emulation.
The Trace and Breakpoint board supports trace and
breakpoint capabilities. The 2k deep trace of address,
data and status may be displayed in mnemonic or machine formats, and may be triggered by any of 16 predefined events. Two hardware breakpoints (based on
any of the 16 predefined events) and 36 software
breakpoints are supported.
Execution time measurement is accomplished with a
resolution of 1 p.s, and may be measured between two
instruction execution addresses or between the occurrence of any two of the 16 predefined events.
IBt.I-PC/AT
or
Compatible
I
Emulator
Interface
11-10--1
r
32CG16
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Target System
Emulator
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TL/EE/l0334-2
FIGURE 2. NS32CG161SE System Configuration
II
5-5
2.0 Description of Features (Continued)
2.3 The Development Process
Figure 3 shows the development process in the different environments.
DOS
Emulator Software
dos QUITt
+ unix
UNIX
Edit, Compile/Assemble &:
Link -> Object flle
udcp, ducp utilities
exit
+dos
t
DOS
Emulator Software
exit
f
.emul
EMULATOR
Program Loading
Program Execution
Program Debug
exit
+dos
t
DOS
Emulator Software
TLlEE/l0334-3
FIGURE 3. The Development Process
2.4 Command Summary
The following is a summary of the commands supported by the emulator.
CONFIGURATION COMMANDS
Mapping address Thru address RomlRAmlTArgetlLocked
Maps 4 kbyte memory blocks in the specified address range as ROM, RAM, Target or Locked memory space.
MOnitor address
This command maps a single 4 kbyte memory block at specified address for use by the monitor.
Interrupt EnablelOlsable Nmllint
Enables or Disables the selected interrupt NMI or INT.
OMa EnablelOisable
Enables or Disables DMA transfers when the CPU is not accessing the bus.
Break EnablelOlsable MonltorlRom write
Enables or Disables a break in program execution when an access to Monitor address space or a write to the
ROM address space occurs.
Load CofflSform file Offset
Loads a specified file in COFF or Motorola S formats into memory at a specified offset from address O.
Store file From address Thru address
Stores the program data in the specified address range in memory into the specified file in Motorola S format.
Clear
Clears all the symbols used in the program.
5-6
2.0 Description of Features (Continued)
2.4 Command Summary (Continued)
The following is a summary of the commands supported by the emulator
DISPLAY COMMANDS
Display Configuration
Displays the current configuration of the emulator.
Display Register Format GenerallSlnglelOouble
Displays CPU registers in the specified format.
Display Memory address Format BytelWordlOwordlOwordlMnemonlclSlnglelOouble
Displays memory contents starting at specified address in the specified format.
Display Trace TrlggerlTOplBottomlline MnemonlclMAchlne
Displays results of the trace with the specified display position and display format.
The display position may be specified at the Trigger point or the top of the trace or the bottom of the trace or a
specified line number on the trace.
The display format may be specified to be in mnemonic or machine formats.
Display SWbreak
Displays all the software breakpoints.
Display Event
Displays all the pre-defined events.
DATA MANIPULATION COMMANDS
Register Format GenerallSinglelOouble
Specifies the display and change formats for register commands.
MOdify reg To data
Modifies the specified register to the specified data.
Memory address Format BytelWordlOwordlOwordlMnemonlclSlnglelOOuble
Specifies the display and change formats for memory commands.
MOdify address Thru address To data
Modifies the memory locations in the specified address range to the specified data.
EVENT SETUP COMMANDS
Event
Initiates the event definition process.
Add Address = I# address Data = I# data Status OfflFetchlOatalOReadlOWritellntacklSlave
Adds an event with specified address match or nomatch, with specified data match or nomatch, and specified
status conditions.
Replace number Address = I# address Data
= I# data Status OfflFetchlOatalOReadlOWritellntacklSlave
Replaces the event with the specified event number with the new event defined with the specified address
match or nomatch, with specified data match or nomatch, and specified status conditions.
DELete Aliinumber
Deletes all currently defined events or the event with the specified event number.
II
5-7
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CJ
oN
2.0 Description of Features (Continued)
2.4 Command Summary (Continued)
The following is a summary of the commands supported by the emulator.
('I)
(J)
Z
SOFTWARE BREAKPOINT COMMANDS
SWbreak
Initiates the setup of software breakpoints.
Add address
Adds a software breakpoint at specified address.
Replace number To address
Replaces the breakpoint address of a pre-defined breakpoint (referenced by the specified number) with the
new specified address.
DELete Aliinumber
Deletes all the pre-defined software breakpoints or the pre-defined breakpoint with the specified number.
Set EnablelDisable Aliinumber
Enables or disables the state of all pre-defined software breakpoints or the pre-defined software breakpoint
(referenced by the specified number).
PROGRAM EXECUTION COMMANDS
RESet
Resets the CPU.
Go From address Until address1lEvent# Or address2lEvent# Times number
Executes program from specified address until a match occurs on the specified address (address1) or on the
specified event (hardware breakpoint # 1), or until a match occurs on the specified address (address2) or on
the specified event (hardware breakpoint # 2). A specified number of times a specified match occurs may also
be used to control program execution. If the hardware breakpoint conditions are omitted, then program execution breaks on the software breakpoints that may be set and enabled.
Step From address
Executes one instruction from the specified address.
Trace From address Trigger address1lEvent# Or address2lEvent#
Enables the trace from the specified address, with the trigger points being defined by address1 or a specified
event or by address2 and a specified event.
MEAsure From address Start address1lEvent# End address2lEvent#
Enables program execution from specified address with execution time being measured from specified start
address1 or event until the specified end address2 or event.
Quit
Forces a break in program execution and stops the CPU.
EMULATOR CONTROL COMMANDS
CANcel
Resets the emulator to its initial state at start-up.
EXIT
Exits from the emulator environment to the DOS environment.
DOS
Suspends temporarily to the DOS environment from the emulator environment.
MAcro file
Executes command lines stored in the specified macro file in text format.
5-8
3.0 Specifications
4.0 Ordering Information
Environment
NSS-ISE-CG16 NS32CG16 Emulator.
The NS32CG16 ISE is designed to operate in a laboratory environment. The
emulator unit may be mounted horizontally (flat) or vertically.
Temperature Operative: + 15°C to + 50°C
Storage: -40°C to + 60°C
Humidity
10% to 90% relative, non-condensing
Altitude
Operative 15000 feet
Power
NS32CG16 ISE requires a standard
Requirements AC power outlet (125V AC).
III
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SYS32/30 PC Add-In
Development Package
TL/EE/9420-1
•
•
•
•
•
•
•
Support for other Series 32000®
development products:
-SPLICE
- National's Series 32000 Development
Board family
- Optimizing Compilers: C,
FORTRAN 77, Pascal
• Easy-to-use DOS/UNIX interface
15 MHz NS32332/NS32382 Add-In board
for an IBM® PC/ AT® or compatible
system
2-3 MIP system performance
No wait-state, on-board memory in 4-, 8or 16-Mbyte configurations
Operating system derived from AT&T's
UNIX® System V Release 3
Multi-user support
GENIXTM Native and Cross-Support
(GNXTM) language tools. Includesassembler, linker, libraries, debuggers
Product Overview
The SYS32TM/30 is a complete, high-performance
development package that converts an IBM PCI AT or
compatible computer into a powerful multi-user system for developing applications that use National
Semiconductor Embedded System Processors™ or
Series 32000 microprocessor family components. The
SYS32/30 add-in processor board containing the Series 32000 device cluster with the NS32332 microprocessor allows programs to run on a personal
computer at speeds greater than those of a VAXTM
11/780. The chip cluster on the processor board includes the NS32332 Central Processing Unit,
NS32382 Memory Management Unit, NS32C201 Timing Control Unit and the NS32081 Floating-Point Unit.
Along with the processor board, the SYS32/30 package contains the OpUS5™ operating system which is
derived from GENIX V.3, National Semiconductor's
5-10
Product Overview (Continued)
The SYS32/30 processor board plugs into the PCI AT
bus, uses the standard control and data signals, and
appears to the PCI AT as 16 bytes in the PCI AT Input/Output (1/0) space. Communication between the
PCI AT and the board is accomplished via this address space. This architecture allows the board to interface to the PCI AT in the same manner as any other
PCIAT peripheral. The PCIAT processes 110 commands while the SYS32/30 processor board continues with regular operation. 1/0 is requested via interrupt to the PCI AT, which then performs the data
transfer using Direct Memory Access (DMA). (See Figure 1).
The processor board requires two slots in the PCI AT
motherboard and plugs into a single long 16-bit bus
slot. The space of the second slot is needed to accommodate the piggybacked memory board attached
to the processor board. No additional connections are
required.
port of AT&T's UNIX System V Release 3. Specially
developed software is included to efficiently integrate
the NS32332 processor board and the host PCI AT
processor, allowing them to function as a complete
UNIX computer system. National's Series 32000 GENIX Native and Cross-Support (GNX) language tools
are included in the SYS32/30 package to provide stable and effective tools for software development. Optional compilers are available for FORTRAN 77, C,
and Pascal.
Functional Description
15 MHz ADD-IN PROCESSOR BOARD FOR AN IBM PC/AT
OR COMPATIBLE SYSTEM
The SYS32/30 development package contains a
processor board designed around the Series 32000
chip set. This chip set includes the NS32332 Central
Processing Unit, NS32382 Memory Management Unit,
NS32C201 Timing Control Unit, and the NS32081
Floating-Point Unit.
This processor board forms the high-performance
center of the computer system with the host PCI AT
processor. Peripherals are under the control of the
PCI AT's microprocessor and are located either on the
PCI AT motherboard or on other boards in the PCI AT
chassis. The PCI AT handles all direct access to devices and serves as an integral dedicated 110 processor.
2-3 MIPS SYSTEM PERFORMANCE
The NS32332 CPU and associated devices operating
at 15 MHz provide computing power greater than that
of a VAX 11/780. Sustained performance for the
NS32332 device cluster is 2-3 VAX MIPS (Million Instructions Per Second). An example of relative performance using the widely recognized Dhrystone
benchmark is shown in Figure 2.
DOS
UTILITIES
SYS32/30
A
to..
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~ DATA
I'
K'I DATA v
K
SYS32/30 DRIVERS
AND
CONTROL
OPMON PROGRAM
PC
HARDWARE
UNIX ENVIRONMENT
n
1;
;1--1\
\r-V
PC
PERIPHERALS
DOS ENVIRONMENT
TL/EE/9420-2
FIGURE 1
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Functional Description
(Continued)
able time in regenerating complex software systems
after changes are made. The uucp software allows
users on different UNIX systems to communicate using electronic mail and to transfer files over dial-up or
serial communications links. Menu-driven system administration is available for system setup, adding users, controlling communication lines, installing software packages, changing passwords, and other administrative functions.
U)
>
U)
DHRYSTONE 1.1
SYS32/30
ADDITIONAL SUPPORT UTILITIES
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UNIX operating system, not contained in AT&T's UNIX
System V Release 3, are supplied as part of the package. These utilities are listed in Table I.
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The Tools for Documenters package, derived from the
AT&T Documenter's WorkbenchTM Utility, provides
the Series 32000 programmer with the tools to prepare documentation. The major components of this
package are shown in Table II.
ON-BOARD MEMORY CONFIGURATIONS
OF 4, 8 OR 16 MBYTES
The processor board is configured with either 4, 8, or
16 Mbytes of zero wait-state physical memory. It is
possible to upgrade the 4- or 8-Mbyte configuration to
16 Mbytes through the purchase of an optional 16Mbyte memory card.
TABLE II. Tools for Documenters Utilities
Description
Name
OPERATING SYSTEM
The SYS32/30 operating system is derived from
GENIX V.3, National Semiconductor's port of
AT&T's UNIX System V Release 3.
The UNIX operating system is a powerful, multi-user,
multitasking operating system that includes the following key features:
Demand-Paged Virtual Memory
Hierarchical file system
Source Code Control System (SCCS)
UNIX to UNIX copy (uucp)
"make" utility
Menu-driven system administration
The UNIX operating system has a proven reputation
as an effective and productive environment for efficient software development. UNIX allows multiple users to work simultaneously on the same computer and
project. The Source Code Control System (SCCS) automatically tracks program revisions as development
work progresses. The "make" software saves valu-
nroff
A text formatter for line printers
troff
A text formatter for typesetters
mm
A macro package
mmt
A macro package
eqn
A troff preprocessor for typesetting
mathematics on a phototypesetter
neqn
A troff preprocessor for typesetting
mathematics on a terminal
tbl
A preprocessor for formatting tables
pic
A preprocessor for graphic illustrations
col
A filter to nroff for processing multicolumn
text output, as from tbl
NETWORKING CAPABILITY
The SYS32/30 based development system configured to support networking using the TCP/IP protocol
allows project development using multiple systems, including SYS32/30 based systems, VAX/VMSTM (using TCP/IP), SUN-3ISunOS™ and VAX/ULTRIX. The
5-12
~------------------------------------------------------------------------.
Functional Description
(Continued)
compatibility design of the GNX language tools allows
software modules developed on these networked systems to be linked together on a single system for execution as one program. Networking requires that additional hardware and software be installed in the system. Third party products that enable networking are
listed in the SYS32/30 configuration guide.
opment hosts (VAX/VMS or VAX/ULTRIX, for example) to be linked with modules created on the
SYS32/30 system. This flexibility is most valuable
where non-centralized software development is desired and the systems are able to transfer or share
files via a common network. Information for configuring the SYS32/30 for integration into a network is
contained in the configuration guide.
Compilers are available separately as optional software to allow individual selection of the application
language. The C, FORTRAN 77 and Pascal compilers
are the result of National's optimizing compiler project
and reflect state-of-the-art compiler technology for optimizing execution speed. For additional details about
the GNX tools consult the GNX tools data sheet.
MANUALS
A complete manual set for the operating system and
related software is included in the SYS32/30 package. This includes:
Installation instructions for the PC Add-in board
Installation instructions for software
UNIX System V.3 reference manuals and user guides
GNX Language Tools Manuals
Tools for Documenters Reference Manual
Berkeley Utilities Manual
SUPPORT FOR AN INTEGRATED DEVELOPMENT
ENVIRONMENT
The SYS32/30 contains the functionality and compatibility needed to utilize other tools available from National Semiconductor for developing and debugging
Series 32000-based applications. These tools include
the SPLICE software debugger, NS32GG16-ISE, the
Series 32000 Development Board set, and National's
Embedded System Processor evaluation boards for
the NS32CG16 and NS32GX32 processors.
The NS32CG16 ISE is a full featured emulator for development of NS32CG16 based systems. Software is
developed on the SYS32/30, then transferred to the
DOS partition of the development system for download by the ISE.
The SPLICE development tool provides a communication link between a Series 32000 target and a development system host. This connection allows users to
download and map their software onto target memory
and then debug this software using National Semiconductor's GNX debugger. Consult the SPLICE data
sheet for more information.
The GNX debugger also directly supports the HewlettPackard HP64772 NS32532/NS32GX32 in-system
emulator. This combination provides powerful integrated support for high-level source debugging and insystem emulation of the NS32532 or NS32GX32 processors.
The Series 32000 development boards and Embedded System Processor evaluation boards used with
the SYS32/30 are specifically designed to assist the
user in evaluating and developing hardware and software for embedded systems and the Series 32000
family of CPUs.
MULTI-USER SUPPORT
The SYS32/30 operating system is an interactive,
multi-user, multitasking operating system. Many activities or jobs can be performed simultaneously when
serial ports are added to the host system. These additional serial ports are used for terminals, printers, modems, IIO-to-development boards, IIO-to-target hardware, or for communication with National's SPLICE
debugging tool. Information about third party products
that provide additional serial ports is contained in the
SYS32/30 configuration guide.
GNXLANGUAGETOOLS
The GENIX Native and Cross-Support (GNX) language tools allow the user to compile, assemble, and
link user programs to create executable files. These
files can then be executed and debugged on a Series
32000 development board, target system application
hardware, or a 32000/UNIX-based system such as
the SYS32/30.
The GNX language tools include the assembler, linker, debuggers, libraries, and the monitor software for
all Series 32000 development boards in both PROM
and source code form.
The Series 32000 GNX language tools are based on
AT&T's Common Object File Format (COFF). Under
COFF, object modules created by any of the GNX
compilers or the GNX assembler may be linked to
object modules of any other translator in the GNX
tools. Optimizing compilers are available for C,
FORTRAN 77, and Pascal.
The COFF file format also allows object modules that
have been created by the GNX tools on other devel-
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Functional Description
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DOS/UNIX INTEGRATION
Figure 3.) The output of the assembler is an object file
which can be linked to other object file and lor libraries, resulting in an executable file.
Since the SYS32/30 provides a Series 32000 native
environment, the executable file may be run on the
host SYS32/30 system or loaded into RAM on either
a target system, an Embedded System Processor
evaluation board or one of the Series 32000 development boards. The source-level software debuggers in
the GNX tools provide powerful facilities for debugging software on the target system.
The GNX debugger is capable of downloading and
controlling the execution of software on the target system. Executable monitor software is provided in
PROMs in the SYS32/30 package for the Series
32000 development boards and the Embedded System Processor evaluation boards. Monitor software is
also provided in source form in the GNX language
tools so application designers can modify and port the
monitor to suit the needs of their target system.
After debugging, the executable file created by linking
can also be converted to PROM format using the GNX
nburn utility.
The SYS32/30 PC add-in development package allows easy transfer of data between DOS and the
UNIX operating system. A system console user can
switch between either operating system using only a
few keystrokes. A shell interface allows DOS commands to be executed from the UNIX shell, UNIX
commands to be executed from DOS, and files to be
transferred between the UNIX and DOS partitions on
the system disk. In addition, the user can suspend the
SYS32/30 operation, enter DOS, run an application,
and then return to the SYS32/30 environment.
Series 32000 Application Development
The SYS32/30 with the PCI AT operates as a local
host computer system for integrating application software into target prototype boards containing Series
32000 components. Programs can be written in assembly language or in a higher level language. Optional compilers are available for C, FORTRAN 77, and
Pascal.
During compilation, the compilers generate assembly
code which is assembled by the GNX assembler. (See
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TL/EE/9420-4
FIGURE 3
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Configuring a System
Basic Kits
The SYS32/30 PC Add-In package supports a variety
of configurations. Based on developer needs, the final
configuration may need extra serial I/O ports, and/or
networking capability. A hard disk of sufficient size is
also an important part of the configuration. A configuration guide that outlines available options and recommended products for configuring the SYS32/30 development system is available.
Host system elements required for SYS32/30 operation are:
- IBM PCI AT or compatible system
- Two full length slots in the motherboard
- 512 Kbytes of RAM
- PC-DOS 3.1 or later
- 1.2-Mbyte floppy disk drive
- Adequate hard disk storage (see the next section
on disk size)
The SYS32/30 Add-In Development package is available in three basic kits:
NSS-SYS30-KIT1
For IBM-AT and compatible
systems
PC Add-In coprocessor board
with 4 Mbytes on-board memory
UNIX System V.3 based operating system
GNX Language Tools
Tools for Documenters
Berkeley Utilities
Installation instructions for the
PC Add-In board
Installation instructions for software
UNIX System V.3 reference
manuals and user guides
GNX Language Tools Manuals
Tools For Documenters Reference Manuals
Berkeley Utilities Manual
Same as KIT1 except with
NSS-SYS30-KIT2
8 Mbytes of on-board memory
Same as KIT1 except with
NSS-SYS30-KIT3
16 Mbytes of on-board memory
Note: The SYS32/30 processor board actually plugs into a single slot.
The second slot is required to accommodate the space taken by
the piggybacked memory board attached to the NS32332 processor board.
The SYS32/30 PC/AT Add-In Development Package
runs on an IBM PCI AT or compatible computer. If an
IBM PCI AT is not used for the host system, it is important to remember that compatibility can vary between
IBM PC/AT compatible systems. The SYS32/30 processor board may not be adequately supported by systems that lack full IBM PC/AT compatibility. The configuration guide available contains a list of IBM PC/AT
compatible systems that have the required compatibility.
MEMORY UPGRADE
To upgrade the memory size to 16 Mbytes after the
purchase of KIT1 or KIT2, the following 16-Mbyte
memory board must be purchased to replace the existing memory board:
NSS-SYS30-MEM16 16-Mbyte memory board.
HARD DISK CAPACITY
Several factors influence the size selected for a hard
disk. Consideration should include the number of users for the system, space for user files, the size of the
application to be developed, and extra software packages and compilers that must reside on the system.
For example, a 50-Mbyte hard disk is the minimum
size recommended for a SYS32/30-based development environment. This provides sufficient space for a
single-user account, the UNIX operating system and
utilities, the GNX tools, compiler software, basic DOS
software, and a moderate size application. Disk drives
with even greater capacity than the minimum sizes indicated here should be considered for additional users
or software and to provide for growth of the system.
When selecting hard disk drives or other peripheral
devices, it is important that the device conform to the
industry-standard for peripheral devices designed for
use on the PCI AT bus.
Optional Software Packages
(A prerequisite for use is the purchase of one of the
above basic kits).
NSW-C-3-BHBF3
Optimizing C Compiler
NSW-F77-3-BHBF3 Optimizing FORTRAN 77 Compiler
NSW-PAS-3-BHBF3 Optimizing Pascal Compiler
NSW-NET-BHBF3
Networking software
NSP-SYS32/V3-MS Additional operating system
manual set
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environment for Series 32000
• Supports software development on
VAXTM, Sun-3®, and SYS32™
development hosts
• Supports Common Object File Format
(COFF)
• Includes versatile configuration
definition utility
•
Includes source code for board-level
monitors
• Includes complete floating-point unit
emulation software
• Supports optional C, FORTRAN 77, and
Pascal optimizing compilers
• Supports SPLICE development tool
Introduction
The Series 32000 GNX-Version 3 (GENIX Native and
Cross-Support) development tools consist of assembler, linker, debuggers, monitors, basic I/O routines,
libraries, optional high-level language compilers, and
other tools to aid in the development of applications
for the Series 32000 microprocessor family. The GNX
tools allow users to compile, assemble, and link application programs to create executable files. These files
can then be executed and debugged on Series 32000based development hosts, such as the SYS32/20 and
SYS32/30, or on a Series 32000-based target board.
After debugging, the executable files can be convert-
ed to binary/hexedecimal files suitable as input to
PROM programmers for burning PROMs.
The Series 32000 GNX development tools are based
on the Common Object File Format (COFF), as developed by AT&T and enhanced by National Semiconductor Corporation. This allows files developed on different hosts and in different high-level languages to
be easily integrated.
Supported Development Hosts
The Series 32000 GNX development tools are available hosted for cross-development on the VAX se-
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FIGURE 1. Sample Development Process
ries of computers, running the VMSTM, UNIX® (bsd),
and ULTRIX operating systems and on a Sun-3 workstation running SunOS™. Also supported are National
Semiconductor's SYS32/20 and SYS32/30 development environments. Table I summarizes the GNX
commands for each environment.
The SYS32/20 and SYS32/30 PC-Add-In Development Packages are complete, high-performance
packages that convert an IBM-PCI ATTM or compatible computer into a powerful multi-user system for developing applications that use the Series 32000 family. The SYS32 systems are based on the Series
32000 processor family; the SYS32/20 includes an
NS32032 Central Processing Unit, and the SYS32/30
is based on the NS32332 CPU. Both the SYS32/20
and SYS32/30 run a derivative of the AT&T System
V.3 UNIX operating system. Because these host systems are themselves based on the Series 32000 processor family, application code can be debugged on
the host system without down-loading to target hardware.
Figure 1 illustrates a typical development process.
TABLE I. Commands for SYS32,
VAX/UNIX, and VAX/VMS
SYS32
VAX/UNIX
VAX/VMS
ar
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nasm
nmcc
ncmp
dbg32
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gts
nmeld
nlorder
monfix
nburn
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nstrip
nar
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monfix
nburn
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Tools Components
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The GNX Development Tools comprise the following
utilities and support libraries:
Ar
This utility maintains groups of files combined into a
single archive file. Ar is used to create and update
library files as used by the GNX linker Id.
As
The GNX assembler, as, assembles Series 32000 assembly language source programs and generates relocatable object modules. Relocatable object modules
must be linked to create executable load modules.
DBG32
DBG32 is an interactive symbolic debugger. It can be
used for remote debugging in conjunction with a host
and any target hardware that includes a Series 32000
GNX monitor. DBG32 allows source-level debugging
and includes an easy-to-use on-line help facility.
Floating-Point Enhancement and
Emulation (FPEE) Library
When a floating-point unit (FPU) is not present, the
floating-point enhancement and emulation (FPEE) library provides low-cost floating-point support by emulating the Series 32000 FPU instructions. When an
FPU is present, FPEE enhances the FPU by providing
additional functionality as recommended by Draft 10
of the ANSI/IEEE Task 754 Proposal for Binary Floating-Point Arithmetic (IEEE 754). FPEE meets the IEEE
754 standard for double-precision arithmetic.
The FPEE library is provided in source form and as a
binary library suitable for its particular GNX tool-set
environment. The source includes all support routines
necessary to build the FPEE library. The FPEE library
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can be configured to enhance/emulate either the
NS32081 FPU or the NS32381 FPU.
GNX Target Setup (GTS)
The GNX tools support the full line of Series 32000
central processing units and peripheral devices,
based on user-defined parameters. The GNX Target
Setup (GTS) utility allows users to easily define the
characteristics of the target system at one time. This
information is saved in a file on the host system, which
is examined each time a GNX utility is invoked. These
parameters are used to tailor the application code to
characteristics of the particular hardware.
GTS operates both interactively and non-interactively
and includes an easy-to-use interface and on-line help
facility.
Ld
The GNX linker, Id, creates executable files by combining object files, providing relocation, and resolving
external references. The linker also processes symbolic debugging information. The linker includes a
powerful directives language, which allows the user to
precisely control the linking process.
Lorder
Lorder finds ordering relations for object libraries. The
input may be one or more object or library archive
(see ar) files. The output of lorder can be processed
to find an ordering of a library suitable for one-pass
access by the linker.
Math Libraries
The math libraries (libm.a and lib381 m.a) contain standard math functions that support both the NS32081
and NS32381 floating-point units. These functions are
highly optimized for the Series 32000 architecture.
Table II contains a list of the available math functions.
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TABLE II Available Math Functions
acos
acosh
asin
asinh
atan
atan2
atanh
bessel
cabs
cbrt
ceil
compound
copysign
cos
cosh
drem
exp
exp2
expm1
fabs
facos
facosh
fasin
fasinh
fatan
fcabs
fcbrt
fceil
fcompound
fcopysign
fcos
fcosh
fdrem
fexp
fexp2
fexpm1
ffabs
ffinite
ffloor
ffmod
fhypot
finf
finite
flog
flog10
flog1p
flog2
floor
fmod
fneg
fp-gmathenv
fp-getexptn
fp-getround
fp-gettrap
fp-procentry
fp-procexit
fp-smathenv
fp-setexptn
fp-setround
fp-settrap
fp-testrap
fp-tstexptn
fpgtrpvctrv
fpi
Note: All math hbrary functions are provided In single and double precision versions.
5-18
fpow
fpstrpvctr
frelation
frem
frint
fsin
fsinh
fsqrt
ftan
ftan2
ftanh
gamma
hypot
inf
log
log10
log1p
log2
neg
nextdouble
nextfloat
pi
pow
randomx
relation
rem
rint
sin
sinh
sqrt
tan
tanh
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Tools Components (Continued)
Monitors
representation, and object file format, mixed-language
programming is greatly simplified, aiding in the porting
of existing applications to the Series 32000 architecture.
Mon16, mon32, mon332, mon332b, mon532 and
mon32GX are PROM-based firmware monitors for use
on a Series 32000-based development board. The
monitors allow the user to load, execute, and debug
development board programs with the dbg32 debugger running on a host computer system. The monitors
also provide run-time services, such as physical I/O,
interrupt handling, and error handling in the form of
supervisor calls.
C Optimizing Compiler
The GNX-Version 3 C Optimizing Compiler fully implements the C programming language, as defined in The
C Programming Language by B. Kernighan and D. Ritchie. The C Optimizing Compiler is also compatible
with the UNIX System V C compiler, derived from the
portable C compiler (pcc). Several features of the
draft ANSI C standard (X3J11) are supported.
Source to each monitor is provided so that it may be
modified, assembled, linked, and installed on other
Series-32000 based target boards.
Monfix
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FORTRAN 77 Optimizing Compiler
Monfix is a utility that creates a Series 32000 bootstrap program by modifying a Series 32000 GNX executable file.
Nburn
The GNX-Version 3 FORTRAN 77 Optimizing Compiler fully implements the FORTRAN 77 programming
language, as defined by the American Standard publication Programming Language FORTRAN (ANSI
X3.9-1978). In addition, a command-line option is provided that forces the compiler to accept as input only
programs that adhere to the FORTRAN 66 standard.
Nburn loads the specified bytes of a file to an EPROM
burner in one of several user-specified formats, including ASCII-HEX and S-record.
Nm
The nm utility displays the symbol table of a Series
32000 GNX object file.
Pascal Optimizing Compiler
The GNX-Version 3 Pascal Optimizing Compiler fully
implements the Pascal programming language, as de-
Size
fined by the International Standards Organization
(ISO) standard ISO dp7185 level 1. Several useful
extensions to the Pascal language are supported. A
command-line option is provided that forces the compiler to accept as input only programs that adhere to
the ISO standard.
The size utility displays size information for each section and optional header information of a Series 32000
GNX object file.
Strip
The strip utility strips symbol and line number information from a Series 32000 GNX object file.
SPLICE Support
Optional Compilers
The GNX development tools enable the use of the
SPLICE development tool, which can be used to debug software/hardware on a Series 32000 target.
SPLICE provides a communication link between a Series 32000 target and a development system host that
allows users to down-load and map their software
onto target memory and debug this software using the
dbg32 debugger. The monitor resident on the SPLICE
communicates with dbg32 on the development host.
A substantial amount of application code is developed
in a high-level language; therefore, the speed and efficiency of the application are functions not only of
processor speed, but also of quality of code generated by the high-level language compiler. An inefficient
compiler can extract a significant performance penalty. Likewise, a significant performance improvement
can be achieved for a much lower cost in software
rather than hardware. For this reason. National Semiconductor has developed a line of optimizing compilers that generate extremely efficient code for the Series 32000 architecture.
Each of the optimizing compilers includes the state-ofthe-art GNX optimizer, based on advanced optimization theory developed over the past 15 years. In addition, because all GNX-Version 3 optimizing compilers
use a standard calling sequence, internal intermediate
Source Products
The GNX development tools, as well as the optional
optimizing compilers, are available in source form for
use in porting to other potential development environments. Source code is provided on a VAX/UNIX bsd
tape. Contact Series 32000 Marketing for more information regarding GNX source availability.
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Licensing
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All binary versions of the Series 32000 GNX development tools require the execution of National Semiconductor's binary user agreement. Because the GNX development tools contain AT&T proprietary code, a
System V source license is prerequisite for obtaining a
source version of the GNX tools. Contact Series
32000 Marketing for more information regarding specific licensing issues.
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Each software package is delivered with one copy of
each appropriate manual. Additional manual sets may
be ordered using the following order codes:
NSP-ASM-NX3-MS:
Manual set included with NSW-ASM-3-BHAF3 and
NSW-ASM-3-BHBF3
NSP-ASM-X3-MS:
Manual set included with NSW-ASM-3-BRVX, NSWASM-3-BCVX, and NSW-ASM-3-BCSX
NSP-ASM-M3-MS:
Manual set included with NSW-ASM-3-BRVM and
NSW-ASM-3-BCVM
NSP-C-V3-M:
Manual set delivered with Optimizing C compiler (all
hosts)
NSP-F77-V3-M:
Manual set delivered with Optimizing FORTRAN 77
compiler (all hosts)
NSP-PAS-V3-M:
Manual set delivered with Optimizing Pascal compiler
(all hosts)
For further information regarding National Semiconductor's software development tools and development hosts, please refer to the following datasheets:
GNX-Version 3 C Optimizing Compiler
GNX-Version 3 FORTRAN 77 Optimizing Compiler
GNX-Version 3 Pascal Optimizing Compiler
SYS32/20 PC-Add-In Development Package
SYS32/30 PC-Add-In Development Package
SPLICE Development Tool
Customer Support
National Semiconductor offers a full 90-day warranty
period. Extended warranty provisions can be arranged
by calling National Semiconductor's Technical Support Engineering Center at the toll-free number listed
below.
National Semiconductor's Technical Support Engineering Center has highly trained technical specialists
available to assist customers over the telephone with
any product-related technical problems.
For more information, please call (800) 759-0105 (in
the United States and Canada). Outside North America, please contact your local National Semiconductor
office.
CD
C
Micro VAX/ULTRIX:
NSW-ASM-3-BCVX
Sun-3:
NSW-ASM-3-BCSX
Supported Host Environments and Order Codes:
SYS32/20:
NSW-ASM-3-BHAF3 (included with SYS32/20 kit)
SYS32/30:
NSW-ASM-3-BHBF3 (included with SYS32/30 kit)
VAX/VMS:
NSW-ASM-3-BRVM
VAX/ULTRIX (UNIX bsd):
NSW-ASM-3-BRVX
Micro VAX/VMS:
NSW-ASM-3-BCVM
5-20
CJ)
~
National Semiconductor
PRELIMINARY
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Series 32000® GNX-Version 3
C Optimizing Compiler
Code
Generator
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Assembly
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TL/EE/10363-1
• Generates high-quality code for the
Series 32000 architecture
• Implements the C Language as defined
by B. Kernighan and D. Ritchie in The C
Programming Language
• Uses state-of-the-art optimization
techniques
• Supports mixed-language programming
• Includes a complete run-time C library
and highly optimized math library
• Incorporates many draft-proposed ANSI
C standard (X3J11) features
• Compiles under UNIX®, ULTRIXTM, and
VMSTM operating systems
1.0 Introduction
A substantial amount of application code is developed
in a high-level language. Therefore, the speed and efficiency of the application are functions not only of
processor speed, but also of quality of code generated by the high-level language compiler. An inefficient
compiler can extract a significant performance penalty. Likewise, a significant performance improvement
can be achieved for much lower cost in software rather than hardware. For this reason, National Semiconductor has developed a line of optimizing compilers
that generate extremely efficient code for the Series
32000 architecture.
The C Optimizing Compiler is also compatible with the
UNIX Systtem V C compiler, derived from the fully portable C compiler (pcc). Several features of the draft
ANSI C standard (X3J 11) are supported.
The input to the C Optimizing Compiler is a C language source program. The output, controlled by
command-line options, is either a Series 32000 executable module, a Series 32000 object module, or Series 32000 assembly code.
1.2 Native and Cross-Support
The GNX-Version 3 C Optimizing Compiler is available
hosted as a cross-support compiler on the VAXTM series of computers, running the VMS, UNIX (bsd), and
ULTRIX operating systems and on a Sun-3® workstation running SunOS™. Also supported are National
Semiconductor's SYS32TM/20 and SYS32/30 development environments.
1.1 Product Overview
The Series 32000 GNX-Version 3 C Optimizing Compiler is a member of National Semiconductor's optimizing compiler family, which also includes compilers
that support the Pascal and FORTRAN 77 programming languages. Because all three optimizing compilers use a standard calling sequence, internal intermediate representation, and object file format, mixed-language programming is greatly simplified. The ability to
use mixed-language programming simplifies the porting of pre-existing applications and code reuse. A detailed discussion of mixed-language programming is
presented in the GNX- Version 3 C Optimizing Compiler Reference Manual.
The C Optimizing Compiler fully implements the C
Language, as defined by B. Kernighan and D. Ritchie.
1.3 GNX Development Tools
The GNX-Version 3 C Optimizing Compiler is an integral component of the GNX CrOSS-Development tool
set. The GNX-Version 3 Assembler Package includes
the Series 32000 assembler, the GNX linker, debuggers, libraries, and development board monitors. The
GNX-Version 3 Assembler Package is a prerequisite
for the GNX-Version 3 C Optimizing Compiler. See the
GNX-Version 3 Development Tools Datasheet for
more information on the GNX Tools.
5-21
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r-------------------------------------------------------------------------------~
1,0 Introduction (Continued)
• Void data type
• Signed and unsigned bitfields
• Volatile type; variables can be declared as type
volatile to make them inaccessible to the optimizer. This is useful for mapping to external devices.
• Const keyword
The void, volatile, and const extensions conform to
ANSI C standard (X3J11) features.
The output of the front end is a proprietary intermediate representation that can be either used as input to
the optional optimizer phase or passed directly to the
code generator. This intermediate language, known
as IR32, is an attributed tree-structured representation. IR32 is completely high-level language independent; all of the GNX optimizing compilers produce the
same internal representation. This allows a common
back end to be shared by all GNX optimizing compilers.
The SYS32/20 and SYS32/30 PC-Add-In Development Packages are complete, high-performance
packages that convert an IBM®-PCTM/AT or compatible computer into a powerful multi-user system for developing applications that use the Series 32000 family. The SYS32 systems are based on the Series
32000 processor family; the SYS32/20 includes an
NS32032 Central Processing Unit, and the SYS32/30
is based on the NS32332 CPU. Both the SYS32/20
and SYS32/30 run a derivative of the UNIX System
V.3 operating system. Because these host systems
are themselves based on the Series 32000 processor
family, application code can be debugged on the host
system without down-loading to target hardware.
2.0 Compiler Structure
The C Optimizing Compiler is a modular language
processor consisting of five separate programs: the
driver, the macro preprocessor (cpp), the parser (front
end), the optimizer, and the code generator.
2.4 The Optimizer
The macro. preprocessor is the standard C preprocessor, known as cpp. The macro preprocessor's input is
the C source program with preprocessor macros; its
output is processed C code, with all preprocessor
commands expanded and transformed as necessary.
The macro preprocessor can be used to define constants, insert text from another file, or conditionally
include or exclude source code from compilation
based on a testable condition.
The state-of-the-art GNX optimizer is based on advanced optimization theory developed over the past
15 years. Depending on the compiler and application
code characteristics, the GNX optimizer improves
code performance from 15 to 200 percent beyond that
of other compilers.
The GNX-Version 3 C optimizer is the most innovative
component of the GNX Optimizing Compilers. The optimizer's input is an IR32 intermediate representation
file; its output is an optimized IR32 file. The optimization pass is optional.
Unlike many other optimizers that are local in nature,
optimizations are performed across the whole program by using sophisticated global-data-flow analysis.
The optimization process can be thought of as a fivestep sequence. The sequence of optimizations has
been carefully chosen to ensure that each optimization is performed to maximum effect and to provide
more opportunities for later optimizations. These
steps are as follows:
2.3 The C Language Parser (front end)
Step One-Local Optimizations
The front end of the C Optimizing Compiler is derived
from the UNIX portable C compiler (pcc), with bug fixes and extensions included. The front end's input is C
source code; its output is an intermediate representation that can be passed either to the optimizer or the
code generator.
Among the extensions implemented in the front end
are:
The source program is read-in one procedure at a
time. A procedure is then partitioned into basic blocks:
sequences of code that have branches only at entry
or exit. Optimizations performed at this stage include:
• Value Propagation-replacing variables with their
most recent values
• Constant Folding-evaluating expressions that
consist solely of constants
• Redundant Assignment Elimination--eliminating
assignments that are not used or that are reassigned prior to use
2.1 The Driver
The driver is a program that parses and interprets the
command line and, in turn, sequentially calls each of
the other programs, based on its input and the command-line options invoked. Under the UNIX operating
system, the assembler and linker are also automatically invoked by the driver as required; under VMS,
the assembler is invoked by the driver, and linking is
done at the command line.
2.2 The Macro Preprocessor (cpp)
• Unsigned constants
• Enumerated types
• Improved structure manipulation; structures can be
assigned, passed as parameters to functions, and
returned by functions. Structure and union member
names can be reused in other structures and unions in the same module. No limit is imposed on the
size of structures.
5-22
en
CD
....
2.0 Compiler Structure (Continued)
The relationships between the various optimizations
are illustrated as follows:
The program Sequence
a = 4;
if (a*8 < 0) b
else b
20;
=
program flow. Optimizations performed at this stage
include:
• Branch Elimination-branches to branches are
removed. Code may be reordered to eliminate
branches.
• Dead Code Removal--code that will never be executed is removed.
The following diagram is an example of a flow graph:
= 15;
••• code which uses b but
not 8 •••
TL/EE/l0363-2
20
a~4
>= 0) goto Ll
b~15
goto L2
20
L2:
which after "constant folding" becomes
a~4
if (true) goto Ll
b~15
goto L2
Ll:
b~20
L2:
"dead code removal" results in
a~4
goto Ll
Ll: b
~
U;
0'
::s
N'
5'
which is transformed by "value propagation" into
~
~
<
CD
cc
L2:
Ll: b
Z
-
>= 0) goto Ll
goto L2
if (4*8
C)
o
b~15
~
N
o
'C
3'
a~4
Ll: b
w
o
o
o
w
is translated by the compiler front end into the following intermediate code
if (a*8
CD'
rn
20
L2:
which is transformed by another "flow optimization" into
a~4
b~20
Since there is no further use of a, a
dundant assignment:"
"2,
Global-data-flow analysis is a process that identifies
desirable global code transformations that can speed
code execution. Since studies have shown that most
programs spend 90 percent or more of their time in
loops, particular attention is paid to transformations
that allow loops to execute faster. This involves several techniques:
• Fully Redundant Expression Elimination-Expressions that are computed twice on the same
path are instead computed only once, with the result saved, usually in a register.
• Partially Redundant Expression Elimination-If
a path exists that contains a computation and a
path exists that does not contain a computation,
the computation is placed in each path. This makes
the expression fully redundant, allowing it to be
eliminated.
• Loop Invariant Code Motion-Values that are
computed repeatedly inside of a loop are instead
computed outside the loop and the result saved.
• Strength Reduction-Complex instructions are
replaced by simpler substitutes (Le., multiplications
may be replaced with a sequence of additions).
• Induction Variable Elimination-Variables that
maintain a fixed relation to other variables are replaced.
CD"
....
Register allocation is the process of placing variables
in registers rather than main memory, allowing much
faster access times. Proper allocation of registers can
lead to significant improvement in execution speed.
Most optimizing compilers attempt register allocation
for local variables, to avoid problems caused by "aliasing," or referring to a variable in more than one way.
By using a sophisticated algorithm, the GNX-Version 3
C Optimizing Compiler considers nearly all variables
as candidates for register allocations.
4 is a "re-
b~20
Step Two-Flow Optimizations
A flow graph is constructed. Each basic block is a
node in the graph, with "arrows" drawn to represent
5-23
o
3
Step Three-Global-Data-Flow Analysis
Step Four-Register Allocation
~
o
~
.!!
r-------------------------------------------------------------------------------~
's.
2,0 Compiler Structure (Continued)
o
The algorithm used by the optimizer is called the coloring algorithm, derived from graph theory. The "live
range" of each variable is constructed. The live range
is the program path along which a variable has a value; assignment to a variable generally starts a new
live range, which terminates with the last use of that
value. Two variables that do not have intersecting live
ranges can share a register. More frequently used
variables are given priority for register allocation. In
this way, maximum usage can be made of the registers. Other optimizations performed at this stage are:
• Allocation Of Safe And Scratch Registers-By
convention, registers RO through R2 and FO
through F3 are considered "scratch" registers;
their values are not retained across procedure
calls. Usage of these registers can reduce overhead of procedure calls.
• Register Parameter Allocation-For static routines, parameters are passed in registers whenever
possible.
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Step Five-Code Rewrite
Code is rewritten in IR32 to be passed to the code
generator. Code is reorganized where necessary to
increase performance.
2.5 The Code Generator
The code generator's input is an IR32 file; its output is
assembly code that can be assembled by the GNX
assembler into an object module.
The code generator matches expression trees with
optimal code sequences. Several "peephole" optimizations are performed by the code generator: further reduction of arithmetic identities, stack and frame
alignments, and stre~gth reductions.
In addition, the target CPU and FPU are taken into
consideration when code is produced. Sequences of
code are chosen based on the characteristics of the
target processor specified by the user. This further increases code efficiency.
3,0 Ordering Information
Supported Host Environments and Order Codes:
SYS32/20:
MicroVAX/VMS:
NSW-C-3-BHAF3
NSW-C-3-BCVM
SYS32/30:
MlcroVAX/ULTRIX:
NSW-C-3-BHBF3
NSW-C-3-BCVX
VAX/VMS:
Sun-3:
NSW-C-3-BRVM
NSW-C-3-BCSX
VAX/ULTRIX (UNIX bsd):
NSW-C-3-BRVX
GNX-Version 3 Assembler and Cross-Development
tools (required for use with the Optimizing C Compiler):
SYS32/30:
NSW-ASM-3-BHAF3 (provided with SYS32/20 system)
NSW-ASM-3-BHBF3 (providSYS32/30:
ed with SYS32/30 system)
NSW-ASM-3-BRVM
VAX/VMS:
VAX/ULTRIX
NSW-ASM-3-BRVX
(UNIX bsd:)
MicroVAX/VMS:
NSW-ASM-3-BCVM
MicroVAX/ULTRIX: NSW-ASM-3-BCVX
NSW-ASM-3-BCSX
Sun-3:
For further information regarding National Semiconductor's software development tools and development hosts, please refer to the following datasheets:
GNX-Version 3 Development Tools
GNX-Version 3 FORTRAN 77 Compiler
GNX-Version 3 Pascal Compiler
SYS32/20 PC-Add-In-Development Package
SYS32/30 PC-Add-In-Development Package
5-24
r------------------------------------------------------------------------------,
~
PRELIMINARY
National Semiconductor
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Series 32000® GNX-Version 3
FORTRAN 77 Optimizing Compiler
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Code
Generator
FORTRAN 77
Assembly
Code
TL/EE/l0362-1
• Supports mixed-language programming
• Includes complete FORTRAN intrinsic
function and I/O libraries
• Implements many extensions to
standard FORTRAN 77
• Compiles under UNIX®, ULTRIXTM, and
VMSTM operating systems
• Generates high-quality code for the
Series 32000 architecture
• Implements the FORTRAN 77 Language
as described by the American Standard
publication Programming Language
FORTRAN (ANSI X3.9-1978)
• Uses state-of-the-art optimization
techniques
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1.0 Introduction
defined by the American Standard publication Programming Language FORTRAN (ANSI X3.9-1978). In
addition, a command-line option is provided that
forces the compiler to accept as input only programs
that adhere to the FORTRAN 66 standard.
The input to the FORTRAN 77 Optimizing Compiler is
a FORTRAN 77 language source program. The output, controlled by command-line options, is either a
Series 32000 executable module, ~ Series 32000 object module, or Series 32000 assembly code.
A substantial amount of application code is developed
in a high-level language. Therefore, the speed and efficiency of the application are functions not only of
processor speed, but also of quality of code generated by the high-level language compiler. An inefficient
compiler can extract a significant performance penalty. Likewise, a significant performance improvement
can be achieved for much lower cost in software rather than hardware. For this reason, National Semiconductor has developed a line of optimizing compilers
that generate extremely efficient code for the Series
32000 architecture.
1.2 Native and Cross-support
The GNX-Version 3 FORTRAN 77 Optimizing Compiler is available hosted as a cross-support compiler on
the VAXTM series of computers, running the VMS,
UNIX (bsd), and ULTRIX operating systems. Also supported are National Semiconductor's SYS32TM/20
and SYS32/30 development environments.
1.1 Product Overview
The Series 32000 GNX-Version 3 FORTRAN 77 Optimizing Compiler is a member of National Semiconductor's optimizing compiler family, which also includes
compilers that support the C and Pascal programming
languages. Because all three optimizing compilers use
a standard calling sequence, internal intermediate
representation, and object file format, mixed-language
programming is greatly simplified. The ability to use
mixed-language programming simplifies the porting of
pre-existing applications and code reuse. A detailed
discussion of mixed-language programming is presented in the GNX- Version 3 FORTRAN 77 Optimizing Compiler Reference Manual.
The FORTRAN 77 Optimizing Compiler fully implements the FORTRAN 77 programming language, as
1.3 GNX Development Tools
The GNX-Version 3 FORTRAN 77 Optimizing Compiler is an integral component of the GNX Cross-development tool set. The GNX-Version 3 Assembler Package includes the Series 32000 assembler, the GNX
linker, debuggers, libraries, and development board
monitors. The GNX-Version 3 Assembler Package is a
prerequisite for the GNX-Version 3 FORTRAN 77 Optimizing Compiler. See the GNX- Version 3 Development Tools Datasheet for more information on the
GNX Tools.
5·25
CD
-.
~ r-----------------------------------------------------~---------------------------
'is.
1,0 Introduction (Continued)
o
The SYS32/20 and SYS32/30 PC-Add-In Development Packages are complete, high-performance
packages that convert an IBM®-PCTM/ AT or compatible computer into a powerful multi-user system for developing applications that use the Series 32000 family. The SYS32 systems are based on the Series
32000 processor family; the SYS32/20 includes an
NS32032 Central Processing Unit, and the SYS32/30
is based on the NS32332 CPU. Both the SYS32/20
and SYS32/30 run a derivative of the UNIX System
V.3 operating system. Because these host systems
are themselves based on the Series 32000 processor
family, application code can be debugged on the host
system without down-loading to target hardware.
E
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• Hollerith (nh) notation
• Variable-length program lines
• unlimited identifier length and underscores in identifier names
• non-integer constants (binary, octal, and hexadecimal)
• recursion; procedures may call themselves directly
or through a chain of other procedures
Note: A command-line option is provided that will force the compiler to
accept only code that conforms to the FORTRAN 77 (or
FORTRAN 66) standard (ANSI X3.9-1978).
The output of the front end is a proprietary intermediate representation that can be either used as input to
the optional optimizer phase or passed directly to the
code generator. This intermediate language, known
as IR32, is an attributed tree-structured representation. IR32 is completely high-level language independent; all of the GNX optimizing compilers produce the
same internal representation. This allows a common
back end to be shared by all GNX optimizing compilers.
2,0 Compiler Structure
The FORTRAN 77 Optimizing Compiler is a modular
language processor consisting of five separate programs: the driver, the macro preprocessor (cpp), the
parser (front end), the optimizer, and the code generator.
2.1 The Driver
2.4 The Optimizer
The driver is a program that parses and interprets the
command line and, in turn, sequentially calls each of
the other programs, based on its input and the command-line options invoked. Under the UNIX operating
system, the assembler and linker are also automatically invoked by the driver as required; under VMS,
the assembler is invoked by the driver, and linking is
done at the command line.
The macro preprocessor is the standard C-Ianguage
preprocessor, known as cpp. Preprocessing is an optional step and is performed only if macros are defined
in the FORTRAN 77 source code. The macro preprocessor's input is the FORTRAN 77 program with preprocessor macros; its output is processed FORTRAN
77 code, with all preprocessor commands expanded
and transformed as necessary. The macro preprocessor can be used to define constants, insert text from
another file, or conditionally include or exclude source
code from compilation based on a testable condition.
The state-of-the-art GNX optimizer is based on advanced optimization theory developed over the past
15 years. Depending on the compiler and application
code characteristics, the GNX optimizer improves
code performance from 15 to 200 percent beyond that
of other compilers.
The GNX-Version 3 FORTRAN 77 optimizer is the
most innovative component of the GNX Optimizing
Compilers. The optimizer's input is an IR32 intermediate representation file; its output is an optimized IR32
file. The optimization pass is optional.
Unlike many other optimizers that are local in nature,
optimizations are performed across the whole program by using sophisticated global-data-flow analysis.
The optimization process can be throught of as a fivestep sequence. The sequence of optimizations has
been carefully chosen to ensure that each optimization is performed to maximum effect and to provide
more opportunities for later optimizations. These
steps are as follows:
2.3 FORTRAN 77 Language Parser (front end)
Step One-Local Optimizations
The FORTRAN 77 language parser, known as
f77_fe, takes as input a FORTRAN 77 program. The
output is an intermediate representation that can be
passed either to the optimizer or the code generator.
Several extensions to standard FORTRAN are implemented in the FORTRAN 77 language parser.
The source program is read-in one procedure at a
time. A procedure is then partitioned into basic
blocks: sequences of code that have branches only
at entry or exit. Optimizations performed at this stage
include:
• Value Propagation-replacing variables with their
most recent values
• Constant Folding-evaluating expressions that
consist solely of constants
• Redundant Assignment Elimination-eliminating
aSSignments that are not used or that are reassigned prior to use
2,2 The Macro Preprocessor (cpp)
Among the extensions implemented in the front end
are:
• Double Complex data type; each datum is represented by a pair of double-precision real variables.
• Short Integer data type; declarations of type
Integer'" 2 are accepted
5·26
en
(1)
...
2.0 Complier Structure (Continued)
(ii'
The relationships between the various optimizations
are illustrated as follows:
program flow. Optimizations performed at this stage
include:
• Branch elimination-branches to branches are
removed. Code may be reordered to eliminate
branches.
• Dead code removal-code that will never be executed is removed.
The following diagram is an example of a flow graph:
The program Sequence
a
= 4
IF (a • 8 .LT. 0) THEN
b = 15
ELSE
b
=
w
I\)
o
o
o
G)
Z
><
...<:en
(1)
0'
::s
w
20
-n
ENDIF
... code which uses b but not a ...
is translated by the Compiler front end into the following intermediate code
o
:D
-I
:D
:tZ
.......
.......
a~4
if (a • 8 > = 0) goto L1
TL/EE/l0362-2
b~15
Step Three-Global-Data-Flow Analysis
goto L2
L1: b ~ 20
L2: ...
which is transformed by "value propagation" into
Global-data-flow analysis is a process that identifies
desirable global code transformations that can speed
code execution. Since studies have shown that most
programs spend 90 percent or more of their time in
loops, particular attention is paid to transformations
that allow loops to execute faster. This involves several techniques:
• Fully redundant expression elimination-Expressions that are computed twice on the same
path are instead computed only once, with the result saved, usually in a register.
• Partially redundant expression elimination-If a
path exists that contains a computation and a path
exists that does not contain a computation, the
computation is placed in each path. This makes the
expression fully redundant, allowing it to be eliminated.
• Loop invariant code motion-Values that are
computed repeatedly inside of a loop are instead
computed outside the loop and the result saved.
• Strength reduction-Complex instructions are replaced by simpler substitutes (Le., multiplications
may be replaced with a sequence ot' additions).
• Induction variable elimination-Variables that
maintain a fixed relation to other variables are replaced.
a~4
if (4 • 8 > = 0) goto L1
b~15
goto L2
L1: b ~ 20
L2: ...
which after "constant folding" becomes
a~4
if (true) goto L1
b~15
goto L2
L1: b ~ 20
L2: ...
"dead code removal" results in
a~4
goto L1
L1: b ~ 20
L2: ...
which is transformed by another "flow optimization" into
Step Four-Register Allocation
a~4
Register allocation is the process of placing variables
in registers rather than main memory, allowing much
faster access times. Proper allocation of registers can
lead to significant improvement in execution speed.
Most optimizing compilers attempt register allocation
for local variables, to avoid problems caused by "aliasing," or referring to a variable in more than one way.
By using a sophisticated algorithm, the GNX-Version 3
FORTRAN 77 Optimizing Compiler considers nearly
all variables as candidates for register allocations.
b~20
Since there is no further use of a, a
dundant assignment:"
en
~
4 is a "re-
b~20
Step Two-Flow Optimizations
A flow graph is constructed. Each basic block is a
node in the graph, with "arrows" drawn to represent
5-27
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5'
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~----------------------------------------------------------------------------~
2.0 Compiler Structure (Continued)
The algorithm used by the optimizer is called the col·
orlng algorithm, derived from graph theory. The "live
range" of each variable is constructed. The live range
is the program path along which a variable has a value; assignment to a variable generally starts a new
live range, which terminates with the last use of that
value. Two variables that do not have intersecting live
ranges can share a register. More frequently used
variables are given priority for register allocation. In
this way, maximum usage can be made of the registers. Other optimizations performed at this stage are:
• Allocation of safe and scratch registers-By
convention, registers RO through R2 and FO
through FS are considered "scratch" registers;
their values are not retained across procedure
calls. Usage of these registers can reduce overhead of procedure calls.
• Register Parameter Allocation-for static routines, parameters are passed in registers whenever
possible.
Step Flve-Code Rewrite
Code is rewritten in IRS2 to be passed to the code
generator. Code is reorganized where necessary to
increase performance.
2.5 The Code Generator
The code generator's input is an IRS2 file; its output is
assembly code that can be assembled by the GNX
assembler into an object module.
The code generator matches expression trees with
optimal code sequences. Several "peephole" optimizations are performed by the code generator: further reduction of arithmetic identities, stack and frame
alignments, and strength reductions.
In addition, the target CPU and FPU are taken into
consideration when code is produced. Sequences of
code are chosen based on the characteristics of the
target processor specified by the user. This further increases code efficiency.
3.0 Ordering Information
Supported Host Environments and Order Codes:
SYSS2/20:
VAX/ULTRIX (UNIX bsd):
NSW-F77-S-BHAFS
NSW-F77-S-BRVX
SYSS2/S0:
Micro VAX/VMS:
NSW-F77-S-BHBFS
NSW-F77 -S-BCVM
VAX/VMS:
Micro VAX/ULTRIX:
NSW-F77-S-BRVM
NSW-F77 -S-BCVX
GNX-Version S Assembler and Cross-development
tools (required for use with the Optimizing FORTRAN
77 Compiler):
SYSS2/S0:
NSW-ASM-S-BHAFS
(provided with SYSS2/20
system)
NSW-ASM-S-BHBFS
SYSS2/S0:
(provided with SYSS2/S0
system)
VAX/VMS:
NSW-ASM-S-BRVM
VAX/ULTRIX (UNIX bsd): NSW-ASM-S-BRVX
Micro VAX/VMS:
NSW-ASM-S-BCVM
Micro VAX/ULTRIX:
NSW-ASM-S-BCVX
For further information regarding National Semiconductor's software development tools and development hosts, please refer to the following datasheets:
GNX-Version S Development Tools
GNX-Version S C Compiler
GNX-Version S Pascal Compiler
SYSS2/20 PC-Add-In-Development Package
SYSS2/S0 PC-Add-In-Development Package
5-28
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National Semiconductor
PRELIMINARY
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Series 32000® GNX-Version 3 Pascal
Optimizing Compiler
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Supports mixed-language programming
Includes a complete Pascal run-time
library and highly optimized math library
• Implements many extensions to
standard Pascal
• Compiles under UNIX®, ULTRIXTM and
VMSTM operating systems
•
Generates high-quality code for the
Series 32000 architecture
• Implements the Pascal Language as
described by the International Standards
Organization (ISO) standard ISO dp7185
level 1
• Uses state-of-the-art optimization
techniques
1.0 Introduction
The Pascal Optimizing Compiler fully implements the
Pascal programming language, as defined by the International Standards Organization (ISO) standard
ISO dp7185 level 1, with several useful extensions to
the compiler extensions found in the University of California, Berkeley Pascal compiler (pc). In addition, a
command-line option is provided that forces the compiler to accept as input only programs that adhere to
the ISO standard.
The input to the Pascal Optimizing Compiler is a Pascal language source program. The output, controlled
by command-line options, is either a Series 32000 executable module, a Series 32000 object module, or
Series 32000 assembly code.
A substantial amount of application code is developed
in a high-level language. Therefore, the speed and efficiency of the application are functions not only of
processor speed, but also of quality of code generated by the high-level language compiler. An inefficient
compiler can extract a significant performance penalty. Likewise, a significant performance improvement
can be achieved for much lower cost in software rather than hardware. For this reason, National Semiconductor has developed a line of optimizing compilers
that generate extremely efficient code for the Series
32000 architecture.
1.1 Product Overview
The Series 32000 GNX-Version 3 Pascal Optimizing
Compiler is a member of National Semiconductor's
optimizing compiler family, which also includes compilers that support the C and FORTRAN 77 programming languages. Because all three optimizing compilers use a standard calling sequence, internal intermediate representation, and object file format, mixed-language programming is greatly simplified. The ability to
use mixed-language programming simplifies the porting of pre-existing applications and code reuse. A detailed discussion of mixed-language programming is
presented in the GNX-Version 3 Pascal Optimizing
1.2 Native and Cross-Support
The GNX-Version 3 Pascal Optimizing Compiler is
available hosted as a cross-support compiler on the
VAXTM series of computers, running the VMS, UNIX
(bsd), and ULTRIX operating systems. Also supported
are National Semiconductor's SYS32TM/20 and
SYS32/30 development environments.
1.3 GNX Development Tools
The GNX-Version 3 Pascal Optimizing Compiler is an
integral component of the GNX Cross-development
tool set. The GNX-Version 3 Assembler Package includes the Series 32000 assembler, the GNX linker,
Compiler Reference Manual.
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Among the extensions implemented in the front end
are:
• Separate compilation; programs can be divided into
a number of files that can be compiled separately
• Longreal data type; double-precision (64-bit) floating point values
• String padding of constant strings with blanks
• Conversions of pointers to integers and vice versa
• Unlimited identifier length and underscores in identifier names
• Non-integer constants (binary, octal, and hexadecimal)
• Constant expressions; constants can be defined in
terms of mathematical expressions
• predefined argc and argv functions; allows application programs to easily accept and process command-line arguments
debuggers, libraries, and development board monitors. The GNX-Version 3 Assembler Package is a prerequisite for the GNX-Version 3 Pascal Optimizing
Compiler. See the GNX- Version 3 Development Tools
Datasheet for more information on the GNX Tools.
The SYS32/20 and SYS32/30 PC-Add-In Development Packages are complete, high-performance
packages that convert an IBM-PCTM/AT or compatible computer into a powerful multi-user system for developing applications that use the Series 32000 family. The SYS32 systems are based on the Series
32000 processor family; the SYS32/20 includes an
NS32032 Central Processing Unit, and the SYS32/30
is based on the NS32332 CPU. Both the SYS32/20
and SYS32/30 run a derivative of the UNIX System
V.3 operating system. Because these host systems
are themselves based on the Series 32000 processor
family, application code can be debugged on the host
system without down-loading to target hardware.
Note: A command-line option is provided that will force the compiler to
accept only code that conforms to the ISO Pascal standard ISO
dp7185 level 1.
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2.0 Compiler Structure
'i:
The Pascal Optimizing Compiler is a modular language processor consisting of five separate programs:
the driver, the macro preprocessor (cpp), the parser
(front end), the optimizer, and the code generator.
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The output of the front end is a proprietary intermediate representation that can be either used as input to
the optional optimizer phase or passed directly to the
code generator. This intermediate language, known
as IR32, is an attributed tree-structured representation. IR32 is completely high-level language independent; all of the GNX optimizing compilers produce the
same internal representation. This allows a common
back end to be shared by all GNX optimizing compilers.
2.1 The Driver
The driver is a program that parses and interprets the
command line and, in turn, sequentially calls each of
the other programs, based on its input and the command-line options invoked. Under the UNIX operating
system, the assembler and linker are also automatically invoked by the driver as required; under VMS,
the assembler is invoked by the driver, and linking is
done at the. command line.
2.4 The Optimizer
The state-of-the-art GNX optimizer is based on advanced optimization theory developed over the past
15 years. Depending on the compiler and application
code characteristics, the GNX optimizer improves
code performance from 15 to 200 percent beyond that
of other compilers.
The GNX-Version 3 Pascal optimizer is the most innovative component of the GNX Optimizing Compilers.
The optimizer's input is an IR32 intermediate representation file; its output is an optimized IR32 file. The
optimization pass is optional.
Unlike many other optimizers that are local in nature,
optimizations are performed across the whole program by using sophisticated global-data-flow analysis.
The optimization process can be thought of as a fivestep sequence. The sequence of optimizations has
been carefully chosen to ensure that each optimize is
performed to maximum effect and to provide more opportunities for later optimizations. These steps are as
follows:
2.2 The Macro Preprocessor (cpp)
The macro preprocessor is the standard C-Ianguage
preprocessor, known as cpp. Preprocessing is an optional step and is performed only if macros are defined
in the Pascal source code. The macro preprocessor's
input is the Pascal program with preprocessor macros;
its output is processed Pascal code, with all preprocessor commands expanded and transformed as necessary. The macro preprocessor can be used to define constants, insert text from another file, or conditionally include or exclude source code from compilation based on a testable condition.
2.3 The Pascal Language Parser (front end)
The Pascal language parser, known as pas_fe, takes
as input a Pascal program. The output is an intermediate representation that can be passed either to the
optimizer or the code generator. Conformant array parameters, as defined in the ISO level 1 Standard, are
fully supported. Several extensions to standard Pascal
are implemented in the Pascal language parser.
Step One-Local Optimizations
The source program is read-in one procedure at a
time. A procedure is then partitioned into basic
blocks: sequences of code that have branches only
5-30
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2.0 Compiler Structure (Continued)
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at entry or exit. Optimizations performed at this stage
include:
• Value Propagation-replacing variables with their
most recent values
• Constant Foldlng-evaluating expressions that
consist solely of constants
• Redundant Assignment Ellmlnatlon-eliminating
assignments that are not used or that are reassigned prior to use
The relationship between the various optimizations
are illustrated as follows:
The program sequence
a:= 4;
if (a * 8 < 0) then b : = 15;
b:= 20;
... code which uses b but not a ...
is translated by the Compiler front end into the following intermediate code
a+--4
if (a * 8 > = 0) goto L1
b +-- 15
goto L2
L1: b +-- 20
L2: ...
which is transformed by "value propagation" into
a+--4
if (4 * 8 > = 0) goto L1
b +-- 15
goto L2
L1: b +-- 20
L2: ...
which after "constant folding" becomes
a+--4
if (true) goto L1
b +-- 15
goto L2
L1: b +-- 20
L2: ...
"dead code removal" results in
a+--4
goto L1
L1: b +-- 20
L2: ...
which is transformed by another "flow optimization" into
a+--4
b +-- 20
Step Two-Flow Optimizations
A flow graph is constructed. Each basic block is a
node in the graph, with "arrows" drawn to represent
program flow. Optimizations performed at this stage
include:
• Branch elimination-branches to branches are
removed. Code may be reordered to eliminate
branches.
• Dead code removal---code that will never be executed is removed.
The following diagram is an example of a flow graph:
TL/EE/10365-2
Step Three-Global-Data-Flow Analysis
Global-data-flow analysis is a process that identifies
desirable global code transformations that can speed
code execution. Since studies have shown that most
programs spend 90 percent or more of their time in
loops, particular attention is paid to transformations
that allow loops to execute faster. This involves several techniques:
• Fully redundant expression elimination-Expressions that are computed twice on the same
path are instead computed only once, with the result saved, usually in a register.
• Partially redundant expression elimination-If a
path exists that contains a computation and a path
exists that does not contain a computation, the
computation is placed in each path. This makes the
expression fully redundant, allowing it to be eliminated.
• Loop Invariant code motion-Values that are
computed repeatedly inside of a loop are instead
computed outside the loop and the result saved.
• Strength reductlon-Complex instructions are replaced by simpler substitutes (I.e., multiplications
may be replaced with a sequence of additions).
• Induction variable elimination-Variables that
maintain a fixed relation to other variables are replaced.
Since there is no further use of a, a+--4 is a "redundant assignment:"
b +-- 20
Step Four-Register Allocation
Register allocation is the process of placing variables
in registers rather than main memory, allowing much
faster access times. Proper allocation of registers can
lead to significant improvement in execution speed.
Most optimizing compilers attempt register allocation
for local variables, to avoid problems caused by "aliasing," or referring to a variable in more than one way.
By using a sophisticated algorithm, the GNX-Version 3
Pascal Optimizing Compiler considers nearly all variables as candidates for register allocations.
5-31
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2.0 Compiler Structure (Continued)
3.0 Ordering Information
Supported Host Environments and Order Codes:
SYS32/20:
NSW-PAS-3-BHAF3
SYS32/30:
NSW-PAS-3-BHBF3
VAX/VMS:
NSW-PAS-3-BRVM
VAX/ULTRIX (UNIX bsd):
NSW-PAS-3-BRVX
Micro VAX/VMS:
NSW-PAS-3-BCVM
Micro VAX/ULTRIX:
NSW-PAS-3-BCVX
GNX-Version 3 Assembler and Cross-development
tools (required for use with the Optimizing Pascal
Compiler):
SYS32/20:
NSW-ASM-3-BHAF3 (provided
with SYS32/20 system)
NSW-ASM-3-BHBF3 (provided
SYS32/30:
with SYS32/30 system)
VAX/VMS:
NSW-ASM-3-BRVM
VAX/ULTRIX
(UNIXbsd):
NSW-ASM-3-BRVX
MicroVAX/VMS:
NSW-ASM-3-BCVM
MicroVAX/ULTRIX: NSW-ASM-3-BCVX
For further information regarding National Semiconductor's software development tools and development hosts, please refer to the following datasheets:
GNX-Version 3 Development Tools
GNX-Version 3 C Compiler
GNX-Version 3 FORTRAN 77 Compiler
SYS32/20 PC-Add-In Development Package
SYS32/30 PC-Add-In Development Package
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The algorithm used by the optimizer is called the coloring algorithm, derived from graph theory. The "live
range" of each variable is constructed. The live range
is the program path along which a variable has a value; assignment to a variable generally starts a new
live range, which terminates with the last use of that
value. Two variables that do not have intersecting live
ranges can share a register. More frequently used
variables are given priority for register allocation. In
this way, maximum usage can be made of the registers. Other optimizations performed at this stage are:
• Allocation of safe and scratch registers-By
convention, registers RO through R2 and FO
through F3 are considered "scratch" registers;
their values are not retained across procedure
calls. Usage of these registers can reduce overhead of procedure calls.
• Register Parameter Allocation-For static routines, parameters are passed in registers whenever
possible.
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Step-Five-Code Rewrite
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Code is rewritten in IR32 to be passed to the code
generator. Code is reorganized where necessary to
increase performance.
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2.5 The Code Generator
The code generator's input is an IR32 file; its output is
assembly code that can be assembled by the GNX
assembler into an object module.
The code generator matches expression trees with
optimal code sequences. Several "peephole" optimizations are performed by the code generator: further reduction of arithmetic identities, stack and frame
alignments, and strength reductions.
In addition, the target CPU and FPU are taken into
consideration when code is produced. Sequences of
code are chosen based on the characteristics of the
target processor specified by the user. This further increases code efficiency.
5-32
Section 6
Physical Dimensions!
Appendices
Section 6 Contents
Glossary of Terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Physical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bookshelf
Distributors
6-2
6-3
6-10
Glossary
In our efforts to be concise and precise, we often invent new words or acronyms to use as shorthand representations of "things"
that require much longer names if the jargon is not used. Being humans, we then become very impressed with our ability to
exclude those not in "the know" and another "in" group is formed. This glossary has been developed to help bridge this
language gap. We know it will help. We hope you will use it.
Abort-The first step of recovery when an instruction or its operand(s) is not available in main memory. An Abort is initiated by
the Memory Management Unit (MMU) and handled by the CPU.
Absolute Address-An address that is permanently assigned to a fixed location in main memory. In assembly code, a pattern
of characters that identifies a fixed storage location.
Access Time-The time interval between when a request for information is made and the instant this information is available.
Access Class-The five Series 32000 access classes are memory read, memory write, memory read-modify-write, memory
address, and register address. The access class informs the Series 32000 CPU how to interpret a reference to a general
operand. Each instruction assigns an access class to each of it two operands, which in turn fully defines the action of any
addressing mode in referencing that operand.
Accumulator-A register which stores the result of an ALU operation.
Ada-A high level language designed for the Department of Defense. It gives preference to full English words. It is meant to be
the standard military language.
Address-An expression, usually numerical, which designates a specific location in a storage or memory device.
Address-Data Reglster-A register which may contain either address or data, sometimes referred to as a general-purpose
register.
Address Strobe-Control signal used to tell external devices when the address is valid on the external address bus.
Address Translation-The process by which a logical address emanating from the CPU is transformed into a physical address
to main memory. This is performed by the Memory Management Unit (MMU) in Series 32000 systems. Logical address to
Physical address mapping is established by the operating system when it brings pages into main memory.
Addressing Mode-The manner in which an operand is accessed. Series 32000 CPUs have nine addressing modes: Register,
Register Relative, Memory Relative, Immediate, Absolute, External, Top-of Stack, Memory Space, and Scaled Indexing.
Algorithm-A set of procedures to which a given result is obtained.
Alignment-The issue of whether an instruction must begin on a byte, double byte, or quad byte address boundary.
ALU-Arithmetic Logic Unit. A computational subsystem which performs the arithmetic and logical operations of a digital
system.
Array-A structured data type consisting of a number of elements, all of the same data type, such that each data element can
be individually identified by an integer index. Arrays represent a basic storage data type used in all high-level languages.
ASCII-(American National Standard Code for Information Interchange, 1968). This standard code uses a character set generally coded as 7-bit characters (8-bits when using parity check). Originally defined to allow human readable information to be
passed to a terminal, it is used for information interchange among data processing systems, communication systems, and
associated equipment. The ASCII set consists of alphabetic, numeric, and control characters. Synonymous with USASCII.
Assemble-To prepare a machine language program (also called machine code or object code) from a symbolic language
program by substituting absolute operation codes for symbolic operation codes and absolute or relocatable addresses for
symbolic addresses. Machine code is a series of ones and zeros which a computer "understands".
Assembler-This program changes the programmer's source program (written in English assembly language and understandable to the programmer) to the 1's and O's that the machine "understands". In particular, the Assembler converts assembly
language to machine code. This machine code output is called the OBJECT file.
Assembly Language-A step up in the language chain. This is a set of instructions which is made up of alpha numeric
characters which, with study, are understandable to the programmer. Different type of machines have different assembly
languages, so the assembly language programmer must learn a different set of instructions each time s/he changes machine.
Associative Cache-A dual storage area where each data entry has an associated "tag" entry. The tags are simultaneously
compared to the input value (a logical address) in the case of the MMU, and if a matching tag is found, the associated data entry
is output. An associative cache is present within the MMU in Series 32000 systems to provide logical-to-physical address
translation.
Asynchronous Devlce-A device in which the speed of operation is not related to any frequency in the system to which it is
connected.
BASIC-This acronym stands for Beginner's All-purpose Symbolic Instruction Code. BASIC is one of the most "English like" of
the high level languages and is usually the first programming language learned.
Baud Rate-Data transfer rate. For most serial transmission protocols, this is synonymous with bits-per-second (bps).
BCD-Binary Coded Decimal. A binary numbering system for coding decimal numbers. A 4-bit grouping provides a binary value
range from 0000 to 1001, and codes the decimal digits "0" through "9". To count to 9 requires a single 4-bit grouping; to count
to 99 takes two groupings of 4 bits; to count to 999 takes three groupings of 4 bits, etc.
Benchmark-In terms of computers, this refers to a software program designed to perform some task which will demonstrate
the relative processing speed of one computer versus another.
6-3
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Glossary (Continued)
Bit-An abbreviation of "binary digit". It is a unit of information represented by either a one or a zero.
Bit Fleld-A group of bits addressable as a single entity. A bit field is fully specified by the location of its least significant bit and
its length in bits. In Series 32000 systems, bit fields may be from one to 32 bits in length.
Branch-A nonsequential flow in a software instruction stream.
Breakpolnt-A place in a routine specified by an instruction, instruction digit, or other condition, where the software program
flow will be interrupted by external intervention or by a monitor routine.
Buffer-An isolating circuit used to avoid reaction of a driven circuit on the corresponding driver circuit. Buffers also supply
increased current drive capacity.
Bus-A group of conductors used for transmitting signals or power.
Bus Cycle-The time necessary to complete one transfer of information requiring the use of external address, data and control
buses.
Byte-Eight bits.
Byte Enable-BEO to BE3. CPU control signals which activate memory banks, each bank providing one byte of data per
address.
C-A highly structured high level language developed by Bell Laboratories to optimize the size and efficiency of the program.
This language has gained much popularity because it allows the programmer to get close to the hardware (low level) as well as
being a high level language. Before C, the programmer who had to address the hardware had to use assembly language or
machine code.
Cache-See Associative Cache.
Cache Hit-In the MMU, logical-to-physical address translation takes place via the associative cache. For this to happen, the
addressed page must be resident in physical memory such that a logical address tag is present in the MMU's translation cache.
Cache Miss-When a logical address is presented to the MMU, and no physical address translation entry is found In the MMU's
associative cache.
Cascaded-Stringing together of units to expand the operation of the unit. Interrupt Control Units present in a Series 32000
system which are in addition the Master ICU are referred to as "cascaded" ICUs; I.e., interrupts cascade from a second-level
ICU through the master ICU to the CPU.
Clock-A device that generates a periodic Signal used for synchronization.
Clock Cycle-After making a low-to-high transition, the clock will have completed one cycle when it is about to make another
low-to-high transition. This time is equal to 1If where f = the clock frequency.
COBOL-This acronym stands for "Common Business Oriented Language". It is a language especially good for bookkeeping
and accounting.
COFF·COMMON OBJECT FILE FORMAT is a standard way of constructing files developed by AT&T for the express purpose of
making all files similar. This will help reduce the situation where large files developed by one organization won't run on another
organization's equipment simply because the software interfaces are different. It provides a great potential for savings in both
time and money.
Compile-To take a program written in a High-Level Language such as C, Pascal, or FORTRAN and convert it into an objectcode format which can be loaded into a computer's main memory. During compilation, symbolic HLL statements, called source
code, are converted into one or more machine instructions which the CPU "understands". A compiler also calls the assemble
function.
Complier-The program that converts from Source to Machine Code. The conversion is from a particular high level language to
machine code. For example, the C compiler will convert a C source program written by a programmer to machine code. This
machine code output is in the same format as that of the assembler and is also called an OBJECT file.
CPU-Central Processing Unit. The portion of a computer system that contains the arithmetic logic unit, register file, and other
control oriented subsystems. It performs arithmetic operations, controls instruction processing, and provides timing signals and
other housekeeping operations.
Cross Support-The alternative to using a "Native" development like SYS32 to develop your programs is to use Cross Support
software. "Native" means that the CPU in the development system is the same as the CPU in the system being developed.
Cross support software is all of the necessary programs for development that operate on one CPU, but generate code for
another CPU. Use of the VAX to generate Series 32000 code is a good example of cross support.
Demand·Paged Virtual Memory-A virtual memory method in which memory is divided into blocks of equal size which are
referred to as pages. These pages are then moved back and forth between main memory and secondary storage as required by
the CPU. Demand paging reduces the problem of memory fragmentation which results in unused memory space.
Dispatch Table-In Series 32000 systems, this is an area of memory which contains interrupt descriptors for all possible
hardware interrupts and software traps. The interrupt descriptor directs the CPU to the module descriptor for the procedure
which is designed to handle that particular interrupt.
Dlsplacement-A numerical offset from a known point of reference. Displacements are used in programming to facilitate
position independent code, such that a given program can be loaded anywhere in memory. In Series 32000 processors, a
displacement is contained in the instruction itself.
6-4
Glossary (Continued)
DMA-Direct Memory Access. A method that uses a small processor (DMA Controller) whose sole task is that of controlling
input-output or data movement. With DMA, data is moved into or out of the system without CPU intervention once the DMA
controller has been initialized by the CPU and activated.
Double-Preclslon-With reference to 32000 floating-point arithmetic, a double-precision number has a 52-bit fraction field, 11bit exponent field and a sign bit (64-bits total).
Double Word-Two words, i.e., 32 bits.
Edltor-A program which allows a person to write and modify text. This program can be as complicated as the situation
requires, from the very simple line editor to the most complicated word processor. Letters, numbers and unprintable control
characters are stored in memory so that they can be recalled for modification or printing. The programmer uses this device to
enter the program into the computer. At this stage, the program is recognizable to both the programmer and the computer as
lines of English text. This English version of the program is known as the SOURCE.
Emulate-To imitate one system with another, such that the imitating system accepts the same data, executes the same
programs, and achieves the same results as the imitated system.
Exception-An occurrence which must be resolved through CPU intervention. An exception results in the suspension of normal
program flow. In Series 32000 systems, exceptions occur as a result of a hardware reset, interrupt or software traps. Execution
of floating-point instructions may also result in occurrences which must be resolved through CPU intervention.
Exponent-In scientific notation, a numeral that indicates the power to which the base is raised.
EXEC2-NSC's Real Time Executive for Series 32000.
FIFO-First-in first-out. A FIFO device is one from which data can be read out only in the same order as it was entered, but not
necessarily at the same rate.
Floating-Point-A method by which computers deal with numbers having a fractional component. In general, it pertains to a
system in which the location of the decimal/binary point does not remain fixed with respect to one end of numerical expressions,
but is regularly recalculated. The location of the point is usually given by expressing a power of the base.
FORTRAN-A high level language written for the scientific community. It makes heavy use of algebraic expressions and
arithmetic statements.
FP-Frame Pointer. CPU register which points to a dynamically allocated data area created at the beginning of a procedure by
the ENTER instruction.
FPU-Floating-Point Unit is a slave processor in Series 32000 systems which implements in hardware all calculations needed to
support floating-point arithmetic, which otherwise would have to be implemented in software. The NS32081 FPU provides highspeed floating point instructions for single (32-bit) and double (64-bit) precision. Supports IEEE standard for binary floating point
arithmetic. Compatible with NS32032, NS32C032, NS32016, NS32C016 and NS32008 CPUs.
Fragmented-The term used to describe the presence of small, unused blocks of memory. The problem is especially common
in segmented memory systems, and results in inefficient use of memory storage.
Frame-A block of memory on the stack that provides local storage for parameters in the current procedure.
GENIX-The NSC version of the UNIX operating system, ported to work with the Series 32000. It also has all of the necessary
utilities added so that program development can be accomplished.
Hardware-Physical equipment, e.g., mechanical, magnetic, electrical, or electronic devices, as opposed to the software
programs or method in which the hardware is used.
High Level Languages-These are languages which are not dependent on the type of computer on which they run. A program
written in a high level language will generally run on any computer for which there is a compiler for that language. This feature
makes high level languages "Portable", i.e., the same program will run on many different types of computers. A HLL requires a
compiler or interpreter that translates each HLL statement into a series of machine language instructions for a particular
machine.
ICU-Interrupt Control Unit. A memory-mapped microprocessor support chip in Series 32000 systems which handles external
interrupts as well as additional software traps. The ICU provides a vector to the CPU to identify the servicing software procedure.
Indexing-In computers, a method of address modification that is by means of index registers.
Index Reglster-A register whose contents may be added to or subtracted from the operand address.
Indirect Addressing-Programming method where the initial address is the storage location of a word which is the actual
address. This indirect address is the location of the data to be operated upon.
Instructlon-A statement that specifies an operation and the values or locations of its operands, i.e., it tells the CPU what to do
and to what.
Instruction Cycle-The period of time during which a programmed system executes a particular instruction.
Instruction Fetch-The action of accessing the next instruction from memory, often overlapped by its partial execution.
Instruction Queue-With Series 32000 CPUs, this is a small area of RAM organized as a FIFO buffer which stores prefetched
instructions until the CPU is ready to execute them.
Interpreter-A program which translates HLL statements into machine instructions at run time, i.e., while the program is
executing, and is co-resident with the user program.
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Glossary (Continued)
Interrupt-To signal the CPU to stop a software program in such a way that it can be resumed and branch to another section of
code. Interrupts can be caused by events external or internal to the CPU, and by either software or hardware.
INTBASE-Interrupt Base Register. In the Series 32000, a 32-bit CPU register which holds the address of the dispatch table
containing addresses for interrupts and traps.
ISE-In-System Emulator. A computer system which imitates the operation of another in terms of software execution. In
microprocessor system development, the ISE takes the place of the microprocessor by means of a connector at the end of an
umbilical cable. Not only does the ISE perform all the functions of the microprocessor, but it also allows the engineer to debug
his system by setting breakpoints on various conditions, permits tracing of program flow, and provides substitution memory
which may be used in place of actual target system memory.
ISV-Independent Software Vendor. A vendor, independent from National Semiconductor, who ports or develops software for
Series 32000 components. They in turn sell this software to our customers who are designing Series 32000 based products.
Kernel-This is the name given to the core of the operating system. Other programs are added to the kernel to provide the
features of the operating system. The kernel provides control and synchronization.
Language-A set of characters and symbols and the rules for using them. In our context, it is the "English like" format of the
instructions which are understood by both the programmer and the computer.
Library-High level languages as well as assembly language contain many routines which are used over and over again. To
prevent the programmer from having to write the routine every time it is needed, these routines are stored in libraries to be
referenced each time they are needed. These libraries are also OBJECT files.
Linear Address Space-An address space where addresses start at location zero and proceed in a linear fashion (Le., with no
holes or breaks) to the upper limit imposed by the total number of bits in a logical address.
Link Base-In the Series 32000, Module Descriptor entry which points to a table in memory containing entries which reference
variables or entry points in Modules external to the one presently executing.
Linker-Large programs are generally broken down to component parts and farmed out to several programmers. Each one of
these parts is called a MODULE. Each programmer will develop the module using either high level or assembly language, then
"assemble" assembly language modules or "compile" high level language modules. A programmer tells the linker how to
connect these modules to make the program run. The linker makes these connections, resolves all questions about data
needed by one module, but contained in another, finds all library routines, and cleans up any other loose ends. The output from
the linker is called BINARY file and is the file that will run on the computer.
Logical Address Space-The range of addresses which a programmer can assign in a software program. This range is
determined by the length of the computer's address registers.
LSB-Least Significant Bit. The bit in a string of bits representing the lowest value.
Machine Code-The code that a computer recognizes. Specifies internal register files and operations that directly control the
computer's internal hardware.
Machine Language-The ones and zeros which are "understood" by the machine. This is often called "Binary Code." The
programmer must be able to understand the bit patterns to be able to decipher the language. Each machine has a unique
machine language.
Main Memory-The program and data storage area in a computer system which is physically addressed by the microprocessor
or MMU address lines.
Mantissa-In a floating-point number, this is the fractional component.
Mapping-The process whereby the operating system assigns physical addresses in main memory to the logical addresses
assigned by the software.
Memory-Mapped-Referring to peripheral hardware devices which are addressed as if they were part of the computer's
memory space. They are accessed in the same manner as main memory, i.e., through memory read/write operations.
Microcode-A sequence of primitive instructions that control the internal hardware of a computer. Their execution is initiated by
the decoding of a software instruction. Microcode is maintained in special storage and often used in place of hardwired logic.
Microcomputer-A computer system whose Central Processing Unit is a Microprocessor. Generally refers to a board-level
product.
Minlcomputer-A "box-level" computer with system capabilities generally between that of a microcomputer and a mainframe.
MMU-Memory Management Unit. This is a slave processor in Series 32000 which aids in the implementation of demand-paged
virtual memory. It provides logical to physical address translation and initiates an instruction abort to the CPU when a desired
memory location is not in main memory.
MOD-Mod Register. In the Series 32000, a 16-bit CPU register which holds the address of the Module Descriptor of the
currently executing software module.
Module-An independent subprogram that performs a specific function and is usually part of a task, i.e., part of a larger
program.
Module Descriptor-In the Series 32000, a set of four 32-bit entries found in main memory. Three are currently defined and
point to the static data area, link table, and first instruction of the module it describes. The fourth is reserved.
6-6
Glossary (Continued)
Modularlty-A software concept which provides a means of overcoming natural human limitations for dealing with programming
complexity by specifying the subdivision of large and complex programming tasks into smaller and simpler subprograms, or
modules, each of which performs some well-defined portion of the complete processing task.
MSB-Most Significant Bit. The bit in a string of bits representing the highest value.
NET-Short for NETWORK and describes a number of computers connected to each other via phone or high speed links. A net
is convenient for exchanging common information in the form of "mail" as well as for data exchange.
NMI-Nonmaskable Interrupt. A hardware interrupt which cannot be disabled by software. It is generally the highest priority
interrupt.
Object Code-Output from a compiler or assembler which is itself executable machine code (or is suitable for processing to
produce executable machine code).
Operand-In a computer, a datum which is processed by the CPU. It is referenced by the address part of an instruction.
Operating System-A collection of integrated service routines used by the computer to control the sequence of programs. The
operating system consists of software which controls the execution of computer programs and which may provide storage
assignment, input/output control, scheduling, data management, accounting, debugging, editing, and related services. Their
sophistication varies from small monitor systems, like those used on boards, to the large, complex systems used on main
frames.
Operating System Mode-In this mode, the CPU can execute all instructions in the instruction set, access all bits in the
Processor Status Register, and access any memory location available to the processor.
.
Operator-In the description of an instruction, it is the action to be performed on operands.
Page Fault-A hardware generated trap used to tell the operating system to bring the missing page in from secondary storage.
Page Swap-The exchange of a page of software in secondary storage with another page located in main memory. The
operating system supervises this operation, which is executed by the CPU and involves external devices such as disk and DMA
controllers.
Page Table-A 1K-byte area in main memory containing 256 entries which describe the location and attributes of all pointer
tables, Le., a list of pointer table addresses.
Perlpheral-A device which is part of the computer system and operates under the supervision of the CPU. Peripheral devices
are often physically separated from the CPU.
Pascal-A high level language designed originally to teach structured programming. It has become popular in the software
community and has been expanded to be a versatile language in industry.
Physical Address-The address presented to main memory, either by the CPU or MMU.
Pointer Table-A 512-byte page located either in main memory or secondary storage containing 128 entries. Each entry
describes an individual page of the software program. Each page of the software program may reside in main memory or in
secondary storage.
Pop-To read a datum from the top of a stack.
PORT-To port an operating system is to cause that particular operating system to operate with a defined hardware package.
GENIX is the NSC version of UNIX which has been ported to SYS32. The operating system for other Series 32000 based
systems will differ in some degree from SYS32 and the NSC GENIX binary will not operate. It is now necessary to modify GENIX
to fit the situation caused by the new hardware. The GENIX SOURCE is used because this is the program that is most readily
understood by the programmer. The source is changed, compiled, and linked to get a new binary for that particular machine.
Primitive Data Type-A data type which can be directly manipulated by the hardware. With Series 32000, these are integers,
floating-point numbers, Booleans, BCD digits, and bit fields.
Procedure-A subprogram which performs a particular function required by a module, Le., by a larger program; an ordered set
of instructions that have a general or frequent use.
Process-A task.
Program Base-Module Descriptor entry which points to the first instruction in the module being described.
Program Counter-CPU register which specifies the logical address of the currently executing instruction.
Protection-The process of restricting a software program's access to certain portions of memory using hardware mechanisms. Typically done at the operating system and page level.
PSR-Processor Status Register. A 16-bit register on Series 32000 CPU's which contains bits used by the software to make
decisions and determine program flow.
Push-to write a datum to the top of a stack.
Quad word-Four words, Le., 64 bits.
Queue-A First-In-First-Out data storage area, in which the data may be removed at a rate different from that at which it was
stored.
Real Time-The actual time in human terms, related to a process. In a UNIX system, real time is total elapsed time, CPU time is
the percent of time a process is actually in the CPU. Sys time is the time spent in system mode, and user time is the time spent in
user mode.
6-7
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Glossary (Continued)
Real Time Operating Systems-An operating system which operates with a known and predictable response time limit, so that
it can control a physical event.
Record-A structured data type with multiple elements, each of which may be of a different data type, e.g., strings, arrays,
bytes, etc.
Register-A temporary storage location, usually in the CPU, which holds digital data.
Relative Address-The number that specifies the difference between the base address and the absolute address.
Relocatable-In reference to software programs, this is code which can be loaded into any location in main memory without
affecting the operation of the program.
Return Address-The address to which a subroutine call, interrupt or trap subroutine will return after it is finished executing.
Routine-A procedure.
Royalty-Royalty is money paid to the inventor for each item of product sold. A good analogy to use is the music business. Any
time a song is used, the songwriter is paid a royalty. Think of UNIX as a song and GENIX or SYSTEM Vas special arrangements.
For each shipment of GENIX or SYSTEM V, the customer pays a royalty to NSC who, in turn, pays a royalty to AT&T.
SB-In the Series 32000 Static Base Register. Points to the start of the static data area for the currently executing module.
Secondary Storage-This is generally slow-access, nonvolatile memory such as a hard-disk which is used to store the pages
of software programs not currently needed by the CPU.
Segmented Address Space-Term used to describe the division of allocatable memory space into blocks of segments of
variable size.
Setup Time-The minimum amount of time that data must be present at an input to ensure data acceptance when the device is
clocked.
Slave Processor-A processor which cooperates with the main microprocessor in executing certain instructions from the
instruction stream. A slave processor generally accelerates certain functions which increases overall system throughput. Examples of slave processors are the FPU and MMU of Series 32000.
Software-Programs or data structures that execute instructions or cause instructions to be executed and that will cause the
computer to do work.
Software License-NSC does not sell software. Rather, we license the right to use our software. A software license is required
for all Series 32000 software. We use the license to protect NSC's interests and to assist in honoring our commitment to AT&T.
The license is also the vehicle which we use to track customers so that updates can be issued in a timely manner.
Software QI A-It is the charter of the Quality Assurance people to ensure that when a software product reaches the customer
that it is "bug" free. In the real world, it is impossible to test every combination of functions, so some bugs do get through. The
QI A engineer develops test programs which rigorously test the product prior to its introduction to the market place.
SP1-ln the Series 32000, User Stack Pointer. Points to the top of the User Stack and is selected for all stack operations while
in User Mode.
SPO-In the Series 32000, Interrupt Stack Pointer. Points to the top of the interrupt stack. It is used by the operating system
whenever an interrupt or trap occurs.
Stack-A one-dimensional data structure in which values are entered and removed one datum at a time from a location called
the Top-of-Stack. To the programmer, it appears as a block of memory and a variable called the Stack Pointer (which points to
the top of the stack).
Stack Pointer-CPU register which points to the top of a stack.
Static Base Reglster-A 32-bit CPU register which points to the beginning of the static data area for the currently executing
module.
String-An array of integers, all of the same length. The integers may be bytes, words, or double words. The integers may be
interpreted in various ways (see ASCII).
Subroutlne-A self-contained program which is part of a procedure.
Symmetry-A computer architecture is said to be symmetrical when any instruction can specify any operand length (byte, word
or double word) and make use of any address-data register or memory location while using any addressing mode.
Synchronous-Refers to two or more things made to happen in a system at the same time, by means of a common clock
signal.
Tag-A label appended to some data entry used in a look-up process whereby the desired datum can be identified by its tag.
Task-The highest-level subdivision of a user software program. The largest program entity that a computer's hardware directly
deals with.
TCU-Timing Control Unit. A device used to provide system clocks, bus control signals and bus cycle extension capability for
Series 32000.
Trap-An internally generated interrupt request caused as a direct and immediate result of the encounter of an event.
T-State-One clock period. If the system clock frequency is 10 MHz, one T-State will take 100 ns to complete. Operations
internal and external to the CPU are synchronized to the beginning and middle of the T-States. There are four T-States in a
normal Series 32000 CPU bus cycle.
6-8
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Glossary (Continued)
UNIXTM-An operating system developed at Bell Laboratories in the early 1970s. Software programs that run under UNIX are
written in the high·level language C, making them highly portable. UNIX systems do not distinguish user programs from operat·
ing system programs in either capability or usage, and they allow users to route the output of one program directly into the input
of another. This operating is unique and is becoming very popular in the microcomputer world.
USENET-A net to which UNIX systems in the United States connect. Some systems in Europe and Australia also use this net
for the purpose of passing information.
User-A software program. The total set of tasks (instructions) that accomplish a desired result. Tasks are managed by the
operating system.
User Mode-Machine state in which the executing procedure has limited use of the instruction set and limited access to
memory and the PSR.
uucp-Software which allows UNIX computers to pass information to other UNIX systems.
Varlable-A parameter that can assume any of a given set of values.
Vector-Byte provided by the ICU (Interrupt Control Unit) which tells the CPU where within the Descriptor table the descriptor is
located for the interrupt it has just requested.
Virtual Address-Address generated by the user to the available address space which is translated by the computer and
operating system to a physical address of available memory.
Virtual Memory-The storage space that may be regarded as addressable main storage by the system. The operating system
maps Virtual addresses into physical (main memory) addresses. The size of virtual memory is limited by the method of memory
management employed and by the amount of secondary storage available, not by the actual number of main storage locations,
so that the user does not have to worry about real memory size or allocation.
VMS-This is the operating system designed by Digital Equipment Corporation for their VAX series of computers. The original
Series 32000 software was developed on a VAX which was being controlled by the VMS Operating System.
Walt-State-An additional clock period added to a CPU memory cycle which gives an external memory device additional time to
provide the CPU with data. Also used by bus arbitration circuitry to hold the CPU in an idle state until access to a shared
resource is gained.
Wlnchester-Small, hard·disk media commonly found in personal computers.
Word-A character string or bit string considered as the primary data entity. For historical reasons, a word is a group of 16 bits
in Series 32000 systems.
6-9
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~National
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Bookshelf of Technical Support Information
National Semiconductor Corporation recognizes the need to keep you informed about the availability of current technical
literature.
This bookshelf is a compilation of books that are currently available. The listing that follows shows the publication year and
section contents for each book.
Please contact your local National sales office for possible complimentary copies. A listing of sales offices follows this
bookshelf.
We are interested in your comments on our technical literature and your suggestions for improvement.
Please send them to:
Technical Communications Dept. M/S 16300
2900 Semiconductor Drive
P.O. Box 58090
Santa Clara, CA 95052-8090
ALS/AS LOGIC DATABOOK-1987
Introduction to Bipolar Logic • Advanced Low Power Schottky • Advanced Schottky
ASIC DESIGN MANUAL/GATE ARRAYS & STANDARD CELLS-1987
SSIIMSI Functions • Peripheral Functions • LSIIVLSI Functions • Design Guidelines • Packaging
CMOS LOGIC DATABOOK-1988
CMOS AC Switching Test Circuits and Timing Waveforms. CMOS Application Notes. MM54HC/MM74HC
MM54HCT/MM74HCT. CD4XXX. MM54CXXX/MM74CXXX. Surface Mount
DATA ACQUISITION LINEAR DEVICES-1989
Active Filters • Analog Switches/Multiplexers • Analog-to-Digital Converters • Digital-to-Analog Converters
Sample and Hold • Temperature Sensors • Voltage Regulators. Surface Mount
DATA COMMUNICATION/LAN/UART DATABOOK-1989
LAN IEEE 802.3 • High Speed Serial/IBM Data Communications. ISDN Components. UARTs
Modems • Transmission Line Drivers/Receivers
DISCRETE SEMICONDUCTOR PRODUCTS DATABOOK-1989
Selection Guide and Cross Reference Guides • Diodes • Bipolar NPN Transistors
Bipolar PNP Transistors • JFET Transistors. Surface Mount Products • Pro-Electron Series
Consumer Series • Power Components • Transistor Datasheets • Process Characteristics
DRAM 'MANAGEMENT HANDBOOK-1989
Dynamic Memory Control • Error Detection and Correction. Microprocessor Applications for the
DP8408A109A117/18/19/28/29. Microprocessor Applications for the DP8420Al21A122A
Microprocessor Applications for the NS32CG821
EMBEDDED SYSTEM PROCESSOR DATABOOK-1989
Embedded System Processor Overview. Central Processing Units • Slave Processors • Peripherals
Development Systems and Software Tools
F100K DATABOOK-1989
Family Overview. F1 OOK Datasheets • 11 C Datasheets • 10K and 100K Memory Datasheets
Design Guide • Circuit Basics. Logic Design • Transmission Line Concepts • System Considerations
Power Distribution and Thermal Considerations. Testing Techniques. Quality Assurance and Reliability
FACTTM ADVANCED CMOS LOGIC DATABOOK-1989
Description and Family Characteristics • Ratings, Specifications and Waveforms
Design Considerations • 54AC17 4ACXXX • 54ACT174ACTXXX
FAST® ADVANCED SCHOTTKY TTL LOGIC DATABOOK-Rev. 1-1988
Circuit Characteristics. Ratings, Specifications and Waveforms. Design Considerations. 54F174FXXX
FAST® APPLICATIONS HANDBOOK-REPRINT
Reprint of 1987 Fairchild FAST Applications Handbook
Contains application information on the FAST family: Introduction. Multiplexers. Decoders. Encoders
Operators· FIFOs. Counters. TTL Small Scale Integration. Line Driving and System Design
FAST Characteristics and Testing • Packaging Characteristics. Index
GENERAL PURPOSE LINEAR DEVICES DATABOOK-1989
Continuous Voltage Regulators • SWitching Voltage Regulators • Operational Amplifiers • Buffers • Voltage Comparators
Instrumentation Amplifiers • Surface Mount
GRAPHICS HANDBOOK-1989
Advanced Graphics Chipset. DP8500 Development Tools. Application Notes
INTERFACE DATABOOK-1988
Transmission Line Drivers/Receivers • Bus Transceivers. Peripheral Power Drivers • Display Drivers
Memory Support. Microprocessor Support. Level Translators and Buffers • Frequency Synthesis • Hi-Rei Interface
LINEAR APPLICATIONS HANDBOOK-1986
The purpose of this handbook is to provide a fully indexed and cross-referenced collection of linear integrated circuit
applications using both monolithic and hybrid circuits from National Semiconductor.
Individual application notes are normally written to explain the operation and use of one particular device or to detail various
methods of accomplishing a given function. The organization of this handbook takes advantage of this innate coherence by
keeping each application note intact, arranging them in numerical order, and providing a detailed Subject Index.
LS/S/TTL DATABOOK-1989
Contains former Fairchild Products
Introduction to Bipolar Logic • Low Power Schottky • Schottky • TTL • TTL-Low Power
MASS STORAGE HANDBOOK-1989
Rigid Disk Pulse Detectors. Rigid Disk Data Separators/Synchronizers and ENDECs
Rigid Disk Data Controller. SCSI Bus Interface Circuits. Floppy Disk Controllers • Disk Drive Interface Circuits
Rigid Disk Preamplifiers and Servo Control Circuits • Rigid Disk Microcontroller Circuits • Disk Interface Design Guide
MEMORY DATABOOK-1988
PROMs, EPROMs, EEPROMs • Flash EPROMs and EEPROMs • TTL I/O SRAMs
ECL I/O SRAMs • ECL I/O Memory Modules
MICROCONTROLLER DATABOOK-1989
COP400 Family • COP800 Family. COPS Applications • HPC Family • HPC Applications
MICROWIRE and MICROWIRE/PLUS Peripherals. Microcontroller Development Tools
MICROPROCESSOR DATABOOK-1989
Series 32000 Overview • Central Processing Units • Slave Processors • Peripherals
Development Systems and Software Tools. Application Notes. NSC800 Family
PROGRAMMABLE LOGIC DATABOOK & DESIGN MANUAL-1989
Product Line Overview • Datasheets • Designing with PLDs • PLD Design Methodology. PLD Design Development Tools
Fabrication of Programmable Logic • Application Examples
REAL TIME CLOCK HANDBOOK-1989
Real Time Clocks and Timer Clock Peripherals • Application Notes
RELIABILITY HANDBOOK-1986
Reliability and the Die -Internal Construction. Finished Package. MIL-STD-883. MIL-M-38510
The Specification Development Process. Reliability and the Hybrid Device. VLSIIVHSIC Devices
Radiation Environment • Electrostatic Discharge • Discrete Device • Standardization
Quality Assurance and Reliability Engineering • Reliability and Documentation • Commercial Grade Device
European Reliability Programs • Reliability and the Cost of Semiconductor Ownership
Reliability Testing at National Semiconductor. The Total Militaryl Aerospace Standardization Program
883B/RETSTM Products. MILS/RETSTM Products. 883/RETSTM Hybrids. MIL-M-38510 Class B Products
Radiation Hardened Technology • Wafer Fabrication - Semiconductor Assembly and Packaging
Semiconductor Packages • Glossary of Terms • Key Government Agencies • ANI Numbers and Acronyms
Bibliography. MIL-M-38510 and DESC Drawing Cross Listing
SPECIAL PURPOSE LINEAR DEVICES DATABOOK-1989
Audio Circuits • Radio Circuits. Video Circuits • Motion Control Circuits. Special Function Circuits
Surface Mount
TELECOM MUN ICATIONS-1987
Line Card Components • Integrated Services Digital Network Components • Modems
Analog Telephone Components • Application Notes
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