1989_National_LS_S_TTL_Logic_Databook 1989 National LS S TTL Logic Databook
User Manual: 1989_National_LS_S_TTL_Logic_Databook
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co
CD
CO
~ National
~ Semiconductor
400044
LS/S/TTL
Logic
Databook
1989
Introduction to Bipolar Logic
Low Power Schottky
Schottky
TTL
TTL - Low Power
Physical Dimensions
iii
II
••
•
[II
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without notice, to change said circuitry or opaciflcations.
iv
Table of Contents
Alpha-Numeric Index by Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vi
Section 1-lntroduction to Bipolar Logic
Guide to Bipolar logic Device Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Consolidation of National Semiconductor and Fairchild Semiconductor. . . . . . . . . . . . . . .
IC Device Testing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Index ..............................................................
Glossary of Terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-3
1-7
1-9
1-17
1-26
1-31
Section 2-Low Power Schottky. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Commercial Products (DM74lS, DM96lS)
Mill Aero Products (54lS, DM54lS, 96lS)
2-3
Section 3--Schottky . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Commercial Products (DM74S, DM93S, DM96S)
Mill Aero Products (DM54S)
3-3
Section 4-TTL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Commercial Products (DM74, DM93, DM96)
Mill Aero Products (54, DM54, DM71, 93, DM93, 96)
4-3
Section 5-TTL - Low Power ....................................................
Mill Aero Products (DM54l, 93l, 96l)
5-3
Section 6-Physical Dimensions
Physical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Bookshelf
Sales and Distribution Offices
v
6-3
Alpha-Numeric Index by Family
Low Power Schottky-Commercial Products
DM74LSOO Quad 2-lnput NAND Gate ...................................•..................... 2-3
DM74LS02 Quad 2-lnput NOR Gate .......................................................... 2-5
DM74LS03 Quad 2-lnput NAND Gate with Open-Collector Outputs ............................... 2-7
DM74LS04 Hex Inverter .................................................................... 2-9
DM74LS05 Hex Inverter with Open-Collector Outputs .......................................... 2-11
DM74LS08 Quad 2-lnput AND Gate ..........•.............................................. 2-13
DM74LS09 Quad 2-lnput AND Gate with Open-Collector Outputs ............................... 2-15
DM74LS10 Triple 3-lnput NAND Gate ....................................................... 2-17
DM74LS11 Triple 3-lnput AND Gate ......................................................... 2-19
DM74LS12 Triple 3-lnput NAND Gate with Open-Collector Outputs .............................. 2-21
DM74LS13 Dual 4-lnput Schmitt Trigger ..................................................... 2-23
DM74LS14 Hex Inverter with Schmitt Trigger Inputs ........................................... 2-26
DM74LS15 Triple 3-lnput AND Gate with Open-Collector Outputs ............................... 2-29
DM74LS20 Dual4-lnput NAND Gate ........................................................ 2-32
DM74LS21 Dual4-lnput AND Gate .......................................................... 2-34
DM74LS22 Dual 4-lnput NAND Gate with Open-Collector Outputs ............................... 2-36
DM74LS26 Quad 2-lnput NAND Buffers with High-Voltage Open-Collector Outputs ................ 2-39
DM74LS27 Triple 3-lnput NOR Gate .................................. , ........ " ............ 2-41
DM74LS28 Quad 2-lnput NOR Buffer ......................... , .............................. 2-43
DM74LS30 8-lnput NAND Gate .. " ......................................................... 2-46
DM74LS32 Quad 2-lnput OR Gate .......................................................... 2-48
DM74LS33 Quad 2-lnput NOR Buffer with Open-Collector Outputs .............................. 2-50
DM74LS37 Quad 2-lnput NAND Buffer ....................................................... 2-52
DM74LS38 Quad 2-lnput NAND Buffer with Open-COllector Outputs .... , ........................ 2-54
DM74LS40 Dual4-lnput NAND Buffer ....................................................... 2-56
DM74LS42 BCD to Decimal Decoder ........................................................ 2-59
DM74LS47 BCD to 7-Segment Decoder/Driver ............................................... 2-62
DM74LS48 BCD to 7-Segment Decoder ..................................................... 2-67
DM74LS51 Dual2-Wide 2-lnput, 2-Wide 3-lnput AND-OR-INVERT Gate ......................... 2-74
DM74LS54 4-Wide 2-lnput AND-OR-INVERT Gate ............................................ 2-77
DM74LS55 2-Wide 4-lnput AND-OR-INVERT Gate ...... , ., '" ...........•...... " ............ 2-79
DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and
Complementary Outputs ................................................................. 2-81
DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear, and Complementary
Outputs ...........................................................•.................... 2-84
DM74LS75 Quad Latch .................................................................... 2-87
DM74LS83A 4-Bit Binary Adder with Fast Carry ............................................... 2-90
DM74LS85 4-Bit Magnitude Comparator ..................................................... 2-94
DM74LS86 Quad 2-lnput EXCLUSIVE-OR Gate ............................................... 2-98
DM74LS90 Decade Counter ............................................................... 2-101
DM74LS93 4-Bit Binary Counter .......................................•................... 2-101
DM74LS95B 4-Bit Right! Left Shift Register ................................................. 2-1 08
DM74LS107A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Clear and
Complementary Outputs ................................................................ 2-113
DM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and
Complementary Outputs .......................................•........................ 2-116
DM74LS112A Dual Negative-Edge-Triggered J-K Flip-Flop with Preset, Clear, and
Complementary Outputs ................................................................ 2-119
DM74LS122 Retriggerable Monostable Multivibrator (One-Shot) with Clear and Complementary
Outputs ............................................................................... 2-129
DM74LS123 Dual Retriggerable Monostable Multivibrator (One-Shot) with Clear and
Complementary Outputs ....................•........................................... 2-133
vi
Alpha-Numeric Index by Family (Continued)
Low Power Schottky-Commercial Products (Continued)
DM7 4LS125A Quad TRI-STATE Buffer ..................................................... 2-137
DM74LS126A Quad TRI-STATE Buffer ..................................................... 2-140
DM74LS132 Quad 2-lnput Schmitt Trigger NAND Gate .............................. , ........ 2-143
DM74LS133 13-lnput NAND Gate ......... " ............................................... 2-146
DM74LS136 Quad 2-lnput EXCLUSIVE-OR Gate with Open-Collector Outputs ................... 2-148
DM74LS138 3-to-8 Line Decoder/Demultiplexer ............................................. 2-150
DM74LS139 DuaI2-to-4 Line Decoder/Demultiplexer ........................................ 2-150
DM74LS151 1-of-8 Line Data Selector/Multiplexer with Complementary Outputs ................. 2-155
DM74LS153 Dual1-of-4 Line Data Selectors/Multiplexers .................................... 2-161
DM74LS154 4-to-16 Line Decoder/Demultiplexer ............................................ 2-164
DM74LS155 DuaI2-to-4 Line Decoder/1-to-4 Line Demultiplexer .............................. 2-167
DM74LS156 Dual 2-to-4 Line Decoder / 1-to-4 Line Demultiplexer with Open-Collector Outputs ..... 2-167
DM74LS157 Quad 2-to-1 Line Data Selector/Multiplexer ...................................... 2-171
DM74LS158 Quad 2-to-1 Line Inverting Data Selector/Multiplexer .............................. 2-171
DM74LS160A Synchronous Presettable BCD Decade Counter ................................. 2-175
DM7 4LS161 A Synchronous 4-Bit Binary Counter with Asynchronous Clear ...................... 2-180
DM7 4LS162A Synchronous Presettable BCD Decade Counter ................................. 2-175
DM7 4LS163A Synchronous 4-Bit Binary Counter with Synchronous Clear ....................... 2-180
DM7 4LS164 8-Bit Serial In/Parallel Out Shift Register with Asynchronous Clear .................. 2-188
DM74LS165 8-Bit Parallel In/Serial Out Shift Register with Complementary Outputs .............. 2-191
DM74LS166 8-Bit Parallel or Serial In/Serial Out Shift Register ................................ 2-195
DM74LS169A Synchronous 4-Bit Up/Down Binary Counter ............... , ................... 2-203
DM74LS170 4-by-4 Register File with Open-Collector Outputs ................................. 2-208
DM74LS173A 4-Bit TRI-STATE D Register ...................... , ........................... 2-212
DM74LS174 Hex D Flip-Flop with Clear ..................................................... 2-216
DM74LS175 Quad D Flip-Flop with Clear and Complementary Outputs .......................•.. 2-216
DM74LS181 4-Bit Arithmetic Logic Unit ..................................................... 2-221
DM74LS190 Synchronous BCD Up/Down Decade Counter with Mode Control ................... 2-228
DM74LS191 Synchronous 4-Bit Up/Down Binary Counter with Mode Control .................... 2-228
DM74LS192 Up/Down Decade Counter with Separate Up/Down Clocks ........................ 2-234
DM74LS193 Synchronous 4-Bit Up/Down Binary Counter with Dual Clock ....•.................. 2-238
DM74LS194A 4-Bit Bidirectional Universal Shift Register ........ , .. , ...... " ....... " ......... 2-243
DM74LS195A 4-Bit Parallel Access Shift Register .. " ..........•..... '" .... " '" ... , ........ 2-247
DM74LS196 Presettable Decade Counter. '" ........ " .... '" " ............................ 2-251
DM74LS197 Presettable Binary Counter .................................................... 2-255
DM74LS221 Dual Monostable Multivibrator (One-Shot) with Schmitt Trigger Input ................ 2-259
DM74LS240 Octal TRI-STATE Inverting Buffer/Line Driver/Line Receiver ....................... 2-264
DM74LS241 Octal TRI-STATE Buffer/Line Driver/Line Receiver ............................... 2-264
DM74LS243 Quadruple Bus Transceiver .................................................... 2-267
DM74LS244 Octal TRI-STATE Buffer/Line Driver/Line Receiver ............................... 2-270
DM74LS245 Octal TRI-STATE Bus Transceiver .............................................. 2-273
DM74LS247 BCD to 7 -Segment Decoder/Driver with Open-Collector Outputs ................... 2-276
DM74LS248 BCD to 7-Segment Decoder with 2 kn. Pull-Up Resistors ........................... 2-279
DM74LS249 BCD to 7 -Segment Decoder with Open-Collector Outputs .......................... 2-282
DM74LS251 TRI-STATE 1-of-8 Line Data Selector/Multiplexer with Complementary Outputs ...... 2-286
DM74LS253 Dual TRI-STATE 1-of-4 Line Data Selector/Multiplexer ............................ 2-289
DM74LS256 Dual4-Bit Addressable Latch .................................................. 2-292
DM74LS257B Quad TRI-STATE 2-to-1 Line Data Selector/Multiplexer .......................... 2-296
DM74LS258B Quad TRI-STATE 2-to-1 Line Inverting Data Selector/Multiplexer ................. 2-296
DM74LS259 8-Bit Serial In to Parallel Out Addressable Latch .................................. 2-301
DM74LS260 Dual5-lnput NOR Gate ....................................................... 2-304
DM74LS266 Quad 2-lnput EXCLUSIVE-NOR Gate with Open-Collector Outputs ................. 2-306
vii
Alpha-Numeric Index by Family (Continued)
Low Power Schottky-Commercial Products (Continued)
DM74LS273 8-Bit Register with Clear ....................................................... 2-308
DM74LS279 Quad S-R Latch .............................................................. 2-311
DM74LS283 4-Bit Binary Adder with Fast Carry .............................................. 2-314
DM74LS290 Decade Counter ............................................................. 2-318
DM74LS293 4-Bit Binary Counter .........................................•................ 2-322
DM74LS295A 4-Bit Shift Register with TRI-STATE Outputs .................................... 2-326
DM74LS298 Quad 2-Port Register (Multiplexer with Storage) .................................. 2-330
DM74LS299 8-lnput Universal Shift/Storage Register with Common Parallel 110 Pins ............. 2-333
DM74LS322 8-Bit Serial/Parallel Register with Sign Extend ................................... 2-338
DM74LS323 8-Bit Universal Shift/Storage Register with Synchronous Reset and Common I/O
Pins ..................................................................................2-343
DM74LS347 BCD to 7-Segment Decoder/Driver ............................................. 2-348
DM74LS352 Dual1-of-4 Line Inverting Data Selector/Multiplexer .............................. 2-350
DM74LS353 Dual 4-lnput Multiplexer with TRI-STATE Outputs ................................. 2-353
DM74LS365A Hex TRI-STATE Buffer/Bus Driver ............................................ 2-357
DM74LS366A Hex TRI-STATE Inverting Buffer/Bus Driver .................................... 2-360
DM74LS367A Hex TRI-STATE Buffer/Bus Driver ............................................ 2-363
DM74LS368A HexTRI-STATE Inverting Buffer/Bus Driver .................................... 2-366
DM74LS373 Octal TRI-STATE Transparent D Latch .......................................... 2-369
DM74LS374 Octal TRI-STATE Positive Edge-Triggered D Flip-Flop ............................ 2-369
DM74LS375 4-Bit Latch ..•.....•......................................................... 2-374
DM74LS377 Octal D Flip-Flop with Common Enable and Clock ................................ 2-377
DM74LS378 Parallel D Register with Enable ................................................. 2-380
DM74LS379 Quad Parallel Register with Enable ............................................. 2-384
DM74LS380 Multifunction Octal Register ................................................... 2-387
DM74LS380A Multifunction Octal Register .................................................. 2-390
DM74LS390 Dual Decade (Bi-Quinary) Counter .............................................. 2-394
DM74LS393 Dual 4-Bit Binary Counter ...................................................... 2-398
DM74LS395 4-Bit Shift Register with TRI-STATE Outputs ..................................... 2-401
DM74LS447 BCD to 7-Segment Decoder/Driver ............................................. 2-404
DM74LS450 16:1 Multiplexer .....•........................................................ 2-407
DM74LS450A 16:1 Multiplexer ............................................................. 2-410
DM74LS451 Dual 8:1 Multiplexer .......................................................... 2-414
DM74LS451A Dual 8:1 Multiplexer ......•.........•........................................ 2-417
DM74LS453 Quad 4:1 Multiplexer .......................................................... 2-421
DM74LS453A Quad 4:1 Multiplexer ........................................................ 2-424
DM74LS460 1O-Bit Comparator. ........................................................... 2-428
DM74LS460A 10-Bit Comparator .......................................................... 2-431
DM74LS461 Octal Counter ..•......•...................................................... 2-435
DM74LS461A Octal Counter ..•...........•...........•............•..............•....... 2-438
DM74LS465 (DM71/81 LS95A) Octal TRI-STATE Buffer/Bus Driver ............................ 2-442
DM74LS466 (DM71/81 LS96A) Octal TRI-STATE Inverting Buffer/Bus Driver .................... 2-442
DM74LS467 (DM71/81 LS97A) Octal TRI-STATE Buffer/Bus Driver ............................ 2-442
DM74LS468 (DM71/81 LS98A) Octal TRI-STATE Inverting Buffer/Bus Driver .......•...•........ 2-442
DM74LS469 8-Bit Up/Down Counter .......................................•........... '" .2-446
DM74LS469A 8-Bit Up/Down Counter ...................................................... 2-449
DM74LS490 Dual Decade Counter ......................................................... 2-453
DM74LS49110-Bit Counter ............................................................... 2-456
DM74LS491 A 1O-Bit Counter ...........................................................•.. 2-459
DM74LS498 Octal Shift Register ........................................................... 2-463
DM74LS498A Octal Shift Register ......................................................... 2-466
DM74LS502 8-Bit Successive Approximation Register ........................................ 2-470
viii
Alpha-Numeric Index by Family (Continued)
Low Power Schottky-Commercial Products (Continued)
DM74LS503 8-Bit Successive Approximation Register with Expansion Control ................... 2-474
DM74LS533 Octal Transparent Latch with TRI-STATE Outputs ................................ 2-477
DM74LS534 Octal D Flip-Flop with TRI-STATE Outputs ....................................... 2-480
DM74LS540 Octal BufferI Line Driver with TRI-STATE Outputs ................................ 2-483
DM74LS563 Octal D Latch with TRI-STATE Outputs ......................................... 2-486
DM74LS564 Octal D Flip-Flop with TRI-STATE Outputs ....................................... 2-489
DM74LS573 Octal D Latch with TRI-STATE Outputs ......................................... 2-492
DM74LS574 Octal D Flip-Flop with TRI-STATE Outputs ....................................... 2-495
DM74LS645 Octal TRI-STATE Bus Transceiver .............................................. 2-498
DM74LS670 TRI-STATE 4-by-4 Register File ................................................ 2-501
DM74LS952 Dual TRI-STATE 8-Bit Positive Edge-Triggered Rank Shift Register ................. 2-505
DM74LS962 Dual TRI-STATE 8-Bit Positive Edge-Triggered Rank Shift Register ................. 2-511
DM96LS02 Dual Retriggerable Resettable Monostable Multivibrator (One-Shot) .................. 2-517
Low Power Schottky-MILl Aero Products
54LSOO/DM54LSOO Quad 2-lnput NAND Gate ................................................. 2-3
54LS02/DM54LS02 Quad 2-lnput NOR Gate .................................................. 2-5
54LS03/DM54LS03 Quad 2-lnput NAND Gate with Open-COllector Outputs ....................... 2-7
54LS04/DM54LS04 Hex Inverter ............................................................. 2-9
54LS05/DM54LS05 Hex Inverter with Open-Collector Outputs .................................. 2-11
54LS08/DM54LS08 Quad 2-lnputAND Gate ................................................. 2-13
54LS09/DM54LS09 Quad 2-lnput AND Gate with Open-Collector Outputs ....................... 2-15
54LS1 0/DM54LS1 0 Triple 3-lnput NAND Gate ................................................ 2-17
54LS11 IDM54LS11 Triple 3-lnput AND Gate ................................................. 2-19
DM54LS12 Triple 3-lnput NAND Gate with Open-Collector Outputs .............................. 2-21
54LS13 Dual 4-lnput Schmitt Trigger ........................................................ 2-23
54LS14 Hex Inverter with SchmittTrigger Inputs .............................................. 2-26
54LS15 Triple 3-lnput AND Gate with Open-Collector Outputs .................................. 2-29
54LS20/DM54LS20 Dual4-lnput NAND Gate ................................................ 2-32
54LS21/DM54LS21 Dual 4-lnput AND Gate .................................................. 2-34
54LS22 Dual 4-lnput NAND Gate with Open-Collector Outputs .................................. 2-36
54LS26 Quad 2-lnput NAND Buffers with High-Voltage Open-Collector Outputs ................... 2-39
54LS27/DM54LS27 Triple 3-lnput NOR Gate ................................................. 2-41
54LS28 Quad 2-lnput NOR Buffer ................................. " ........................ 2-43
54LS30/DM54LS30 8-lnput NAND Gate ..................................................... 2-46
54LS32/DM54LS32 Quad 2-lnput OR Gate .................................................. 2-48
54LS33 Quad 2-lnput NOR Buffer with Open-Collector Outputs ................................. 2-50
54LS37 Quad 2-lnput NAND Buffer ................................ " ........................ 2-52
54LS38/DM54LS38 Quad 2-lnput NAND Buffer with Open-Collector Outputs ..................... 2-54
54LS40 Dual 4-lnput NAND Buffer .......................................................... 2-56
54LS42/DM54LS42 BCD to Decimal Decoder ................................................ 2-59
54LS47 BCD to 7-Segment Decoder/Driver .................................................. 2-62
54LS48 BCD to 7-Segment Decoder ........................................................ 2-67
54LS49 BCD to 7-Segment Decoder with Open-Collector Outputs ............................... 2-71
54LS51 Dual2-Wide 2-lnput, 2-Wide 3-lnput AND-OR-INVERT Gate ............................. 2-74
54LS54 4-Wide 2-lnput AND-OR-INVERT Gate ............................................... 2-77
54LS55 2-Wide 4-lnput AND-OR-INVERT Gate ............................................... 2-79
DM54LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and
Complementary Outputs ................................................................. 2-81
54LS74/DM54LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear, and
Complementary Outputs ................................................................. 2-84
DM54LS75 Quad Latch .................................................................... 2-87
54LS83A/DM54LS83A 4-Bit Binary Adder with Fast Carry ...................................... 2-90
ix
Alpha-Numeric Index by Family (Continued)
Low Power Schottky-MILl Aero Products (Continued)
54LS85/DM54LS85 4-Bit Magnitude Comparator ............................................. 2-94
DM54LS86 Quad 2-lnput EXCLUSIVE-OR Gate ............................................... 2-98
54LS95B 4-Bit Right/Left Shift Register ..................................................... 2-108
DM54LS107A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Clear and
Complementary Outputs ................................................................ 2-113
54LS109/DM54LS109A Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and
Complementary Outputs ................................................................ 2-116
54LS112/DM54LS112A Dual Negative-Edge-Triggered J-K Flip-Flop with Preset, Clear, and
Complementary Outputs ................................................................ 2-119
54LS113 Dual Positive-Edge-Triggered J-K Flip-Flop with Preset and Complementary Outputs ..... 2-122
54LS114 Dual Negative-Edge-Triggered J-K Flip-Flop with Common Clocks, Clear, and
Complementary Outputs ................................................................ 2-125
54LS125/DM54LS125A Quad TRI-STATE Buffer ............................................ 2-137
54LS126 Quad TRI-STATE Buffer .......................................................... 2-140
DM54LS132 Quad 2-lnput Schmitt Trigger NAND Gate ....................................... 2-143
54LS133 13-lnput NAND Gate ............................................................. 2-146
54LS136/DM54LS136 Quad 2-lnput EXCLUSIVE-OR Gate with Open-Collector Outputs .......... 2-148
54LS 138/DM54LS138 3-to-8 Line Decoder/Demultiplexer .................................... 2-150
54LS139/DM54LS139 DuaI2-to-4 Line Decoder/Demultiplexer ............................... 2-150
54LS 151/DM54LS 151 1-of-8 Line Data Selector/ Multiplexer with Complementary Outputs ........ 2-155
54LS152 8-lnput Multiplexer ............................................................... 2-158
54LS153/DM54LS153 DuaI1-of-4 Line Data Selectors/Multiplexers ........................... 2-161
DM54LS154 4-to-16 Line Decoder/Demultiplexer ............................................ 2-164
54LS155/DM54LS155 DuaI2-to-4 Line Decoders/1-to-4 Line Demultiplexer .................... 2-167
54LS156/DM54LS156 Dual 2-to-4 Line Decoders/1-to-4 Line Demultiplexer with
Open-Collector Outputs ................................................................ 2-167
54LS157/DM54LS157 Quad 2-to-1 Line Data Selector/Multiplexer ............................. 2-171
54LS158/DM54LS158 Quad 2-to-1 Line Inverting Data Selector/Multiplexer .................... 2-171
54LS160A Synchronous Presettable BCD Decade Counter .................................... 2-175
54LS161 AlDM54LS161 A Synchronous 4-Bit Binary Counter with Asynchronous Clear ............ 2-180
54LS162A Synchronous Presettable BCD Decade Counter .................................... 2-175
54LS163A1DM54LS163A Synchronous 4-Bit Binary Counter with Synchronous Clear ............. 2-180
54LS164/DM54LS164 8-Bit Serial In/Parallel Out Shift Register with Asynchronous Clear ......... 2-188
54LS165 8-Bit Parallel In/Serial Out Shift Register with Complementary Outputs ................. 2-191
54LS168 Synchronous Bi-Directional BCD Decade Counter ................................... 2-199
54LS169/DM54LS169A Synchronous 4-Bit Up/Down Binary Counter .......................... 2-203
54LS170 4-by-4 Register File with Open-Collector Outputs .................................... 2-208
54LS173 4-BitTRI-STATE D Register ...................................................... 2-212
54LS174/DM54LS174 Hex D Flip-Flop with Clear ............................................ 2-216
54LS175/DM54LS175 Quad D Flip-Flop with Clear and Complementary Outputs ................. 2-216
54LS181 4-Bit Arithmetic Logic Unit ........................................................ 2-221
DM54LS190 Synchronous BCD Up/Down Decade Counter with Mode Control ................... 2-228
DM54LS191 Synchronous 4-Bit Up/Down Binary Counter with Mode Control .................... 2-228
54LS192 Up/Down Decade Counter with Separate Up/Down Clocks ........................... 2-234
54LS193/DM54LS193 Synchronous 4-Bit Up/Down Binary Counter with Dual Clock .............. 2-238
54LS194A 4-Bit Bidirectional Universal Shift Register ......................................... 2-243
54LS195A 4-Bit Parallel Access Shift Register ............................................... 2-247
54LS240/DM54LS240 Octal TRI-STATE Inverting Buffer/Line Driver/Line Receiver .............. 2-264
54LS241/DM54LS241 Octal TR I-STATE Buffer/Line Driver/Line Receiver ...................... 2-264
54LS244 Octal TRI-STATE Buffer/Line Driver/Line Receiver .................................. 2-270
54LS245/DM54LS245 Octal TRI-STATE Bus Transceiver ..................................... 2-273
54LS247 BCD to 7-Segment Decoder/Driver with Open-Collector Outputs .....................• 2-276
x
Alpha-Numeric Index by Family (Continued)
Low Power Schottky-MIL/Aero Products
(Continued)
54LS248 BCD to 7 -Segment Decoder with 2 kn Pull-Up Resistors .............................. 2-279
54LS249 BCD to 7-Segment Decoder with Open-Collector Outputs ............................. 2-282
DM54LS251 TRI-STATE 1-of-8 Line Data Selector/Multiplexer with Complementary Outputs ...... 2-286
54LS253/DM54LS253 Dual TRI-STATE 1-of-4 Line Data Selector/Multiplexer ................... 2-289
54LS256 Dual 4-Bit Addressable Latch ..................................................... 2-292
54LS257 A/DM54LS257B Quad TRI-STATE 2-to-1 Line Data Selector/Multiplexer ............... 2-296
54LS258A1DM54LS258B Quad TRI-STATE 2-to-1 Line Inverting Data Selector/Multiplexer ....... 2-296
54LS259 8-Bit Serial In to Parallel Out Addressable Latch ..................................... 2-301
54LS260 Dual 5-lnput NOR Gate .......................................................... 2-304
54LS266 Quad 2-lnput EXCLUSIVE-NOR Gate with Open-Collector Outputs ........... '" ...... 2-306
54LS273 8-Bit Register with Clear .......................................................... 2-308
54LS279/DM54LS279 Quad S-R Latch ..................................................... 2-311
54LS283/DM54LS283 4-Bit Binary Adder with Fast Carry ..................................... 2-314
54LS295A 4-Bit Shift Register with TRI-STATE Outputs ....................................... 2-326
54LS298 Quad 2-Port Register (Multiplexer with Storage) ..................................... 2-330
54LS299 8-lnput Universal Shift/Storage Register with Common Parallel I/O Pins ................ 2-333
54LS322 8-Bit Serial/Parallel Register with Sign Extend ....................................... 2-338
54LS323 8-Bit Universal Shift/Storage Register with Synchronous Reset and Common I/O Pins ... 2-343
54LS347 BCD to 7-Segment Decoder/Driver ................................................ 2-348
54LS352 DuaI1-of-4 Line Inverting Data Selector/Multiplexer .............. " ................. 2-350
54LS353 Dual4-lnput Multiplexer with TRI-STATE Outputs .................................... 2-353
54LS365A1DM54LS365A Hex TRI-STATE Buffer/Bus Driver ................•................. 2-357
54LS366A Hex TRI-STATE Inverting Buffer/Bus Driver ....................................... 2-360
54LS367A1DM54LS367A Hex TRI-STATE Buffer/Bus Driver .................................. 2-363
54LS368A1DM54LS368A Hex TRI-STATE Inverting Buffer/Bus Driver .......................... 2-366
DM54LS373 Octal TRI-STATE Transparent D Latch .......................................... 2-369
54LS374/DM54LS374 Octal TRI-STATE Positive Edge-Triggered D Flip-Flop ................... 2-369
54LS375 4-Bit Latch ..................................................................... 2-374
54LS377 Octal D Flip-Flop with Common Enable and Clock ................................... 2-377
54LS378 Parallel D Register with Enable .................................................... 2-380
54LS379 Quad Parallel Register with Enable ................................................ 2-384
DM54LS380 Multifunction Octal Register ................................................... 2-387
DM54LS380A Multifunction Octal Register .................................................. 2-390
54LS395 4-Bit Shift Register with TRI-STATE Outputs ........................................ 2-401
54LS447 BCD to 7-Segment Decoder/Driver ........ '" ....... '" ....•........•............. 2-404
DM54LS450 16:1 Multiplexer ................................ " ............................ 2-407
DM54LS450A 16:1 Multiplexer ......•................................................•..... 2-410
DM54LS451 Dual 8:1 Multiplexer .......................................................... 2-414
DM54LS451A Dual 8:1 Multiplexer ......................................................... 2-417
DM54LS453 Quad 4:1 Multiplexer ......................................•................... 2-421
DM54LS453A Quad 4:1 Multiplexer ..................................•..........•.......... 2-424
DM54LS460 1O-Bit Comparator ............................................................ 2-428
DM54LS460A 10-Bit Comparator .....................................•........ , ..........• 2-431
DM54LS461 Octal Counter .•......................•.....................................•. 2-435
DM54LS461 A Octal Counter ......••..........•.......•..........••........•.............. 2-438
DM54LS469 8-Bit Up/Down Counter .............••........................................ 2-446
DM54LS469A 8-Bit Up/Down Counter ...................................................... 2-449
54LS490 Dual Decade Counter ............................................................ 2-453
DM54LS491 1O-Bit Counter ............................................................... 2-456
DM54LS491 A 1O-Bit Counter .............................................................. 2-459
DM54LS498 Octal Shift Register ....................... , , , ................................. 2-463
DM54LS498A Octal Shift Register ......................................................... 2-466
xi
Alpha-Numeric Index by Family (Continued)
Low Power Schottky-MIL/ Aero Products (Continued)
54LS502 8-Bit Successive Approximation Register ........................................... 2-470
54LS503 8-Bit Successive Approximation Register with Expansion Control ...................... 2-474
54LS670/DM54LS670 TRI-STATE 4-by-4 Register File ....................................... 2-501
96LS02 Dual Retriggerable Resettable Monostable Multivibrator (One-Shot) ..................... 2-517
Schottky-Commercial Products
DM74S00 Quad 2-lnput NAND Gate ...................................................•...... 3-3
DM74S02 Quad 2-lnput NOR Gate ........................................................... 3-5
DM74S03 Quad 2-lnput NAND Gate with Open-Collector Outputs ................................ 3-7
DM74S04 Hex Inverter ...................................................................... 3-9
DM74S05 Hex Inverter with Open-Collector Outputs ........................................... 3-11
DM74S08 Quad 2-lnput AND Gate .......................................................... 3-13
DM74S09 Quad 2-lnput AND Gate with Open-Collector Outputs ................................. 3-15
DM74S10 Triple 3-lnput NAND Gate ..•......................•............................... 3-17
DM74S11 Triple 3-lnputAND Gate .......................................................... 3-19
DM74S20 Dual4-lnput NAND Gate ..............•...............•....•..................... 3-21
DM74S30 8-lnput NAND Gate ..............•............................................... 3-23
DM74S32 Quad 2-lnput OR Gate ........................................................... 3-25
DM74S40 Dual4-lnput NAND Buffer ....................................................•... 3-27
DM74S51 Dual2-Wide 2-lnput AND-OR-INVERT Gate ..........................•.............. 3-29
DM74S64 4-Wide AND-OR-INVERT Gate .................................................... 3-31
DM74S74 Dual Positive-Edge-Triggered D Flip-Flop with Preset, Clear, and Complementary
Outputs ................................................................................3-33
DM74S86 Quad 2-lnput EXCLUSIVE-OR Gate ..................................•.......•..... 3-36
DM74S109 Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary
Outputs ........•....•.....•....•..............•..................................•..... 3-38
DM74S112 Dual Negative-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary
Outputs ................................•...............................................3-41
DM74S113 Dual Negative-Edge-Triggered J-K Flip-Flop with Preset and Complementary Outputs ... 3-44
DM74S132 Quad 2-lnput Schmitt Trigger NAND Gate .......................................... 3-47
DM74S133 13-lnput NAND Gate ............•............................................... 3-50
DM74S138 3-to-8 Line Decoder/Demultiplexer ............................................... 3-52
DM74S139 DuaI2-to-4 Line Decoder/Demultiplexer ........................................... 3-52
DM74S140 Dual4-lnput NAND 50n Line Driver ............................................... 3-56
DM74S151 1-of-8 Line Data Selector/Multiplexer with Complementary Outputs ................... 3-59
DM74S153 DuaI1-of-4 Line Data Selector/Multiplexer ......................................... 3-63
DM74S157 Quad 2-to-1 Line Data Selector/Multiplexer ........................................ 3-66
DM74S158 Quad 2-to-1 Line Inverting Data Selector/Multiplexer ................................ 3-66
DM74S161 Synchronous 4-Bit Binary Counter with Asynchronous Clear .......................... 3-71
DM74S163 Synchronous 4-Bit Binary Counter with Synchronous Clear ........................... 3-71
DM74S174 Hex D Flip-Flop with Clear ....................................................... 3-77
DM74S175 Quad D Flip-Flop with Clear and Complementary Outputs ............................ 3-77
DM74S181 Arithmetic Logic UnitlFunction Generator .......................................... 3-81
DM74S182 Look-Ahead Carry Generator .................................................... 3-90
DM74S194 4-Bit Bidirectional Universal Shift Register ......................................... 3-94
DM7 4S 195 4-Bit Parallel Access Shift Register ............................................... 3-98
DM74S240 Octal TRI-STATE Inverting Buffer/Line Driver/Line Receiver ........................ 3-102
DM74S241 Octal TRI-STATE Buffer/Line Driver/Line Receiver ................................ 3-102
DM74S244 Octal TRI-STATE Buffer/Line Driver/Line Receiver ................................ 3-102
DM74S251 TRI-STATE 1-of-8 Line Data Selector/Multiplexer with Complementary Outputs ....... 3-105
DM74S253 Dual TRI-STATE 1-of-4 Line Data Selector/Multiplexer ............................. 3-109
DM74S257 Quad TRI-STATE 2-to-1 Line Data Selector/Multiplexer ............................ 3-112
DM74S258 Quad TRI-STATE 2-to-1 Line Inverting Data Selector/Multiplexer .................... 3-112
xii
Alpha-Numeric Index by Family (Continued)
Schottky-Commercial Products (Continued)
DM74S280 9-Bit Parity Generator/Checker ......................................•.......... 3-117
DM74S283 4-Bit Binary Adder with Fast Carry ............................................... 3-121
DM74S299 TRI-STATE 8-Bit Universal Shift/Storage Register ................................. 3-125
DM74S373 Octal TRI-STATE Transparent D Latch ........................................... 3-130
DM74S374 Octal TRI-STATE Positive-Edge-Triggered D Flip-Flop ............................. 3-130
DM74S381 Arithmetic Logic Unit/Function Generator ........................................ 3-135
DM93S00 4-Bit Universal Shift Register ...........•......................................... 3-139
DM93S41 4-Bit Arithmetic Logic Unit ....................................................... 3-142
DM93S43 4-Bit by 2-Bit Twos Complement Multiplier ......................................... 3-149
DM93S46 High Speed 6-Bitldentity Comparator ............................................. 3-153
DM93S47 High Speed 6-Bit Identity Comparator ....................................... '" ., .3-157
DM93S62 9-lnput Parity Checker/Generator ................................................ 3-160
DM96S02 Dual Retriggerable Resettable Monostable Multivibrator (One-Shot) ................... 3-165
Schottky-Mill Aero Products
DM54S00 Quad 2-lnput NAND Gate ........•................................................. 3-3
DM54S02 Quad 2-lnput NOR Gate ...................................................•...•.•. 3-5
DM54S04 Hex Inverter .....................................................................• 3-9
DM54S08 Quad 2-lnput AND Gate ..................................•...................•... 3-13
DM54S10 Triple 3-lnput NAND Gate .................................•................... '" .3-17
DM54S11 Triple 3-lnputAND Gate ...............................................•.......... 3-19
DM54S20 Dual4-lnput NAND Gate ......................................................... 3-21
DM54S30 8-lnput NAND Gate ....................................•......................... 3-23
DM54S32 Quad 2-lnput OR Gate .........................•...........•..................... 3-25
DM54S40 Dual 4-lnput NAND Buffer ........................................................ 3-27
DM54S64 4-Wide AND-DR-INVERT Gate ...•..............•................................. 3-31
DM54S74 Dual Positive-Edge-Triggered D Flip-Flop with Preset, Clear, and Complementary
Outputs ................................................................................3-33
DM54S86 Quad 2-lnput EXCLUSIVE-OR Gate ...............................................• 3-36
DM54S112 Dual Negative-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary
Outputs ..........................................................•.....................3-41
DM54S113 Dual Negative-Edge-Triggered J-K Flip-Flop with Preset and Complementary
Outputs ................................................................................ 3-44
DM54S133 13-lnput NAND Gate ............................................................ 3-50
DM54S138 3-to-8 Line Decoder/Demultiplexer .................................... " .. , ...... 3-52
DM54S139 DuaI2-to-4 Line Decoder/Demultiplexer ................•.........................• 3-52
DM54S140 Dual4-lnput NAND 50n Line Driver ............................................... 3-56
DM54S 151 1-of-8 Line Data Selector/Multiplexer with Complementary Outputs ................... 3-59
DM54S153 DuaI1-of-4 Line Data Selector/Multiplexer ......................................... 3-63
DM54S157 Quad 2-to-1 Line Data Selector/Multiplexer ........... ; ..•.•....................... 3-66
DM54S158 Quad 2-to-1 Line Inverting Data Selector/Multiplexer ................................ 3-66
DM54S161 Synchronous 4-Bit Binary Counter with Asynchronous Clear .......................... 3-71
DM54S163 Synchronous 4-Bit Binary Counter with Synchronous Clear ........................... 3-71
DM54S174 Hex D Flip-Flop with Clear ....................................................... 3-77
DM54S175 Quad D Flip-Flop with Clear and Complementary Outputs ............................ 3-77
DM54S181 Arithmetic Logic Unit/Function Generator ..................•....................... 3-81
DM54S182 Look-Ahead Carry Generator ..........................••.....................•.• 3-90
DM54S194 4-Bit Bidirectional Universal Shift Register ......................................... 3-94
DM54S 195 4-Bit Parallel Access Shift Register ..............•................................ 3-98
DM54S240 Octal TRI-STATE Inverting Buffer/Line Driver/Line Receiver ........................ 3-102
DM54S241 Octal TRI-STATE Buffer/Line Driver/Line Receiver .......•..•..................... 3-102
DM54S244 Octal TRI-STATE Buffer/Line Driver/Line Receiver •...•.............•.......•.•... 3-102
DM54S251 TRI-STATE 1-of-8 Line Data Selector/Multiplexer with Complementary Outputs ......• 3-105
xiii
Alpha-Numeric Index by Family (Continued)
Schottky-MillAero Products (Continued)
DM54S253 Dual TRI-STATE 1-of-4 Line Data Selector/Multiplexer ............................. 3-109
DM54S257 Quad TRI-STATE 2-to-1 Line Data Selector/Multiplexer ., ...•...••...••.•........•• 3-112
DM54S258 Quad TRI-STATE 2-to-1 Line Inverting Data Selector/Multiplexer ...............•..•• 3-112
DM54S280 9-Bit Parity Generator/Checker ................................................. 3-117
DM54S283 4-Bit Binary Adder with Fast Carry ............................................... 3-121
DM54S373 Octal TRI-STATE Transparent D Latch ........................................... 3-130
DM54S374 Octal TRI-STATE Positive-Edge-Triggered D Flip-Flop •.•......•....•.....•..•.•..• 3-130
TTL-Commercial Products
DM7400 Quad 2-lnput NAND Gate •.................•...............•..•.••........•......... 4-3
DM7401 Quad 2-lnput NAND Gate with Open-Collector Outputs ......••.•••.•....••••.•.•.•• '" .4-5
DM7402 Quad 2-lnput NOR Gate .............................................•....•..•.•.... 4-7
DM7403 Quad 2-lnput NAND Gate with Open-Collector Outputs •......•.••.•••.••..•..•.•....... 4-9
DM7404 Hex Inverter ...................................•.....•....•.....•........•....•..• 4-11
DM7405 Hex Inverter with Open-Collector Outputs ............................................ 4-13
DM7406 Hex Inverting Buffer/Driver with High-Voltage Open-Collector Outputs ................••. 4-15
DM7407 Hex Buffer/Driver with High-Voltage Open-Collector Outputs ......•...........•....••.. 4-17
DM7408 Quad 2-lnput AND Gate ................•..........•.........•....•................ 4-19
DM7409 Quad 2-lnput AND Gate with Open-Collector Outputs ..................•••.......•..... 4-21
DM7410 Triple 3-lnput NAND Gate ......................................................... .4-23
DM7411 Triple 3-lnput AND Gate ..•....•................................................... 4-25
DM7414 Hex Schmitt Trigger Inverter ........................................................ 4-27
DM7416 Hex Inverting Buffer/Driver with High-Voltage Open-Collector Outputs ....•..•........... 4-30
DM7417 Hex Buffer/Driver with High-Voltage Open-Collector Outputs ..•........•......•....••.• 4-32
DM7420 Dual4-lnput NAND Gate ........................•................................. .4-34
DM7425 Dual4-lnput NOR Gate with Strobe .............................••.•............... .4-36
DM7426 Quad 2-lnput NAND Buffer with High-Voltage Open-Collector Outputs ..•................ 4-38
DM7427 Triple 3-lnput NOR Gate ..•....•................... , ...........•.•.......•..•...... 4-40
DM7430 8-lnput NAND Gate ......................•......••.............•.....•...•....•... 4-42
DM7432 Quad 2-lnput OR Gate .........................................................•... 4-44
DM7437 Quad 2-lnput NAND Buffer •..............•.........•.........•....•................ 4-46
DM7438 Quad 2-lnput NAND Buffer with Open-Collector Output •.•..•....•••.••............•... 4-48
DM7439 Quad 2-lnput NAND Buffer with Open-Collector Output •.........•.•.•............•.... 4-50
DM7440 Dual4-lnput NAND Buffer •.•....••....•..•••....••.•.••••••..•••.•..•.•.••..•.•... .4-52
DM7442A BCD to Decimal Decoder .•.•...•••..••..•.•••••••.••.••.••..••.•..••.••••.••••.•• 4-55
DM7445 BCD to Decimal Decoder/Driver ................................................... .4-58
DM7446A BCD to 7-Segment Decoder/Driver with Open-Collector Outputs ....•.•..•.•..•....•... 4-61
DM7447A BCD to 7-Segment Decoder/Driver with Open-Collector Outputs •...•....•...••••.•••. .4-61
DM7450 Expandable Dual2-Wide 2-lnput AND-OR-INVERT Gate .•.•.•.••..••. " ••••.•..•••.•. .4-66
DM7451 Dual2-Wide 2-lnput AND-OR-INVERT Gate ..........•.....•.•...•.•.•.•.•..•..•..•. .4-69
DM7473 Dual Positive-Edge-Triggered Master-Slave J-K Flip-Flop with Clear and Complementary
Outputs ......•..•...••.••.••..•.•.•.....••..••••.•.•.•••....••.•••..••••..•••.••••.•.•. 4-72
DM7474 Dual Positive-Edge-Triggered D Flip-Flop with Preset. Clear and Complementary
Outputs ....•.••.•.••. '.' •.•.•..•....•......•..•....•....•.......••...•.•..•.•....•...... 4-75
DM7475 4-Bit Bistable Latch •....•.....•.•.•.••..•.•..•.•.••......•.•••..••.••.•••.•••••.•. 4-78
DM7476 Dual J-K Flip-Flop with Preset and Clear ............................................ .4-81
DM7485 4-Bit Magnitude Comparator ........................................................ 4-87
DM7486 Quad 2-lnput EXCLUSIVE-OR Gate .•..•.•••.....••.••..•..•.•••...•.••.•.••.•.••.• .4-91
DM7490A Decade Counter ...............................•........................•........ 4-94
DM7493A 4-Bit Binary Counter ............•.........•.....................................• 4-94
DM7495 4-Bit Parallel Access Shift Register ................................................. 4-1 01
DM7497 Synchronous Modulo 64 Bit Rate Multiplier .......•..••.................•.•..•.••...• 4-104
xiv
Alpha-Numeric Index by Family (Continued)
TTL-Commercial Products
(Continued)
DM74121 Monostable Multivibrator (One-Shot) with Schmitt Trigger Input, Clear, and
Complementary Outputs ................................................................ 4-116
DM74122 Retriggerable Resettable Multivibrator (One-Shot) with Clear ......................... 4-120
DM74123 Dual Retriggerable Monostable Multivibrator (One-Shot) with Clear and
Complementary Outputs ................................................................ 4-124
DM74125 Quad TRI-STATE Buffer ......................................................... 4-128
DM74132 Quad 2-lnput NAND Gate with Schmitt Trigger Inputs ............................... .4-131
DM74145 BCD to Decimal Decoder/Driver ................................................. .4-134
DM74150 1-of-16 Line Data Selector/Multiplexer ............................................ 4-141
DM7 4151 A 1-of-8 Line Data Selector/Multiplexer with Complementary Outputs .................. 4-141
DM74153 Dual1-of-4 Line Data Selector/Multiplexer ......................................... 4-147
DM74154 4-to-16 Line Decoder/Demultiplexer .............................................. 4-150
DM74155 DuaI2-to-4 Line Decoder/1-to-4 Line Demultiplexer ................................ .4-153
DM74157 Quad 2-to-1 Line Data Selector/Multiplexer ........................................ 4-156
DM7 4161 A Synchronous 4-Bit Binary Counter with Asynchronous Clear ........................ 4-159
DM74163A Synchronous 4-Bit Binary Counter with Synchronous Clear .......................... 4-159
DM74164 8-Bit Serial In/Parallel Out Shift Register with Asynchronous Clear .................... 4-167
DM74165 8-Bit Parallel-to-Serial Converter .................................................. 4-170
DM74170 4-by-4 Register File with Open-Collector Outputs ................................... 4-177
DM74173 4-BitTRI-STATE D Register ...................................................... 4-181
DM7 417 4 Hex D Flip-Flop with Clear ....................................................... 4-185
DM74175 Quad D Flip-Flop with Clear and Complementary Outputs ........................... .4-185
DM74180 9-Bit Parity Generator/Checker .................................................. .4-190
DM74184 BCD-to-Binary Converter ........................................................ 4-201
DM74185A Binary-to-BCD Converter ...................................................... .4-201
DM74191 Synchronous Up/Down 4-Bit Binary Counter with Mode Control. ...................... 4-209
DM74197 Presettable Binary Counter ..................................................... .4-223
DM74279 Quad Set-Reset Latch ......................................... " ................ 4-227
DM74283 4-Bit Binary Full Adder with Fast Carry ............................................. 4-229
DM9300 4-Bit Positive-Edge-Triggered Parallel or Serial Access Shift Register ................... 4-255
DM9301 1-of-10 Line Decoder ............................................................ .4-259
DM9308 Dual 4-Bit Latch ................................................................ .4-262
DM9309 Dual 1-of-4 Line Data Selector/Multiplexer with Complementary Outputs ................ 4-265
DM9311 4-to-16 Line Decoder/Demultiplexer ............................................... 4-268
DM9312 1-of-8 Line Data Selector/Multiplexer .............................................. .4-272
DM9314 Quad Latch ...................•................................................. 4-276
DM9316 Synchronous 4-Bit Binary Counter ................................................. 4-280
DM9318 8 to 3 Line Priority Encoder ....................................................... .4-287
DM9321 Dual 1-of-4 Decoder .............................................................. 4-291
DM9322 Quad 1-of-2 Line Data Selector/Multiplexer ......................................... 4-294
DM9324 5-Bit Comparator ................................................................4-297
DM9328 Dual 8-Bit Shift Register ......................................................... .4-301
DM9334 8-Bit Addressable Latch .......................................................... 4-305
DM9338 8-Bit Multiple Port Register ........................................................4-309
DM9368 7-Segment Decoder/Driver/Latch with Constant Current Source Outputs .............. .4-316
DM9370 7-Segment Decoder/Driver/Latch with Open-Collector Outputs ........................ 4-322
DM9374 7-Segment Decoder/Driver/Latch with Constant Current Sink Outputs .................. 4-327
DM9386 4-Bit Quad EXCLUSIVE-NOR with Open-Collector Outputs ............................ 4-334
DM9601 Retriggerable Monostable Multivibrator (One-Shot) with Complementary Outputs ........ 4-337
DM9602 Dual Retriggerable Monostable Multivibrator (One-Shot) with Complementary Outputs .... 4-341
DM96101 Quad 2-lnput Positive NAND Buffer with Open-Collector Outputs ................... ~ .. 4-346
xv
Alpha-Numeric Index by Family (Continued)
TTL-MillAero Products
5400/DM5400 Quad 2-lnput NAND Gate ..................................................... .4-3
DM5401 Quad 2-lnput NAND Gate with Open-Collector Outputs ................................. 4-5
5402/DM5402 Quad 2-lnput NOR Gate ...................................................... .4-7
DM5403 Quad 2-lnput NAND Gate with Open-Collector Outputs ................................. 4-9
5404/DM5404 Hex Inverter ...........................................•.............•...... 4-11
DM5405 Hex Inverter with Open-Collector Outputs ............................................ 4-13
DM5406 Hex Inverting Buffer/Driver with High-Voltage Open-Collector Outputs •.............•.... 4-15
DM5407 Hex Buffer/Driver with High-Voltage Open-Collector Outputs ........................... 4-17
5408/DM5408 Quad 2-lnput AND Gate ...................................................... 4-19
5409 Quad 2-lnput AND Gate with Open-COllector Outputs ..........•....•...........•......... 4-21
541 0/DM541 0 Triple 3-lnput NAND Gate ................................................... .4-23
DM5414 Hex Schmitt Trigger Inverter. ...................................................... .4-27
DM5416 Hex Inverting Buffer/Driver with High-Voltage Open-Collector Outputs ................... 4-30
DM5417 Hex Buffer/Driver with High-Voltage Open-COllector Outputs ....•........•............. 4-32
5420/DM5420 Dual4-lnput NAND Gate .....................................•....•........ , .4-34
5425 Dual 4-lnput NOR Gate with Strobe .................................................... .4-36
DM5426 Quad 2-lnput NAND Buffer with High-Voltage Open-Collector Outputs ................... 4-38
5430/DM5430 8-lnput NAND Gate .......................................................... 4-42
5432/DM5432 Quad 2-lnput OR Gate ................................................•...... 4-44
5437/DM5437 Quad 2-lnput NAND Buffer ................................................... 4-46
DM5438 Quad 2-lnput NAND Buffer with Open-Collector Output ................................ 4-48
5440 Dual4-lnput NAND Buffer ........•.................................................... 4-52
5442A1DM5442A BCD to Decimal Decoder ...............•......•................•......... .4-55
DM5445 BCD to Decimal Decoder/Driver ................................................... .4-58
DM5447A BCD to 7-Segment Decoder/Driver with Open-Collector Outputs ...................... .4-61
5451 Dual 2-Wide 2-lnput AND-OR-INVERT Gate .....................................•...... .4-69
5473/DM5473 Dual Positive-Edge-Triggered Master-Slave J-K Flip-Flop with Clear and
Complementary Outputs .................................................................4-72
5474/DM5474 Dual Positive-Edge-Triggered D Flip-Flop with Preset, Clear and Complementary
Outputs ................................................................................4-75
5475/DM5475 4-Bit Bistable Latch .......................................................... 4-78
5476/DM5476 Dual J-K Flip-Flop with Preset and Clear .....................................•. .4-81
5483A 4-Bit Binary Full Adder with Fast Carry ................................................ .4-84
5485/DM5485 4-Bit Magnitude Comparator ................................................. .4-87
5486/DM5486 Quad 2-lnput EXCLUSIVE-OR Gate ........................................... .4-91
5490/DM5490A Decade Counter ........................................................... 4-94
DM5493A 4-Bit Binary Counter .....•....................................................... 4-94
5495A 4-Bit Parallel Access Shift Register .................................................. 4-101
5497 Synchronous Modulo 64 Bit Rate Multiplier ............................................. 4-104
DM54107 Dual Master-Slave J-K Flip-Flop with Clear and Complementary Outputs ............... 4-110
DM54109 Dual Positive-Edge-Triggered J-K Flip-Flops with Preset and Clear .................... 4-113
54121/DM54121 Monostable Multivibrator (One-Shot) with Schmitt Trigger Input, Clear, and
Complementary Outputs ................•............................................... 4-116
54122 Retriggerable Resettable Multivibrator (One-Shot) with Clear ........................... .4-120
54123 Dual Retriggerable Monostable Multivibrator (One-Shot) with Clear and Complementary
Outputs ...........................................................................•...4-124
54125/DM54125 Quad TRI-STATE Buffer .................................................. 4-128
DM54132 Quad 2-lnput NAND Gate with Schmitt Trigger Inputs ................................ 4-131
DM54145 BCD to Decimal Decoder/Driver .................................................. 4-134
DM54148 8-Line Decimal to 3-Line Octal Priority Encoder ..................................... 4-137
54150/DM54150 1-of-16 Line Data Selector/Multiplexer ...................................... 4-141
54151 AlDM54151 A 1-of-8 Line Data Selector/Multiplexer with Complementary Outputs .......... 4-141
xvi
Alpha-Numeric Index by Family (Continued)
TTL-MillAero Products (Continued)
54153/DM54153 DuaI1-of-4 Line Data Selector/Multiplexer .................................. 4-147
54154/DM54154 4-to-16 Line Decoder/Demultiplexer ........................................ 4-150
DM54155 DuaI2-to-4 Line Decoder/1-to-4 Line Demultiplexer ................................. 4-153
54157/DM54157 Quad 2-to-1 Line Data Selector/Multiplexer .................................. 4-156
54161/DM54161 A Synchronous 4-Bit Binary Counter with Asynchronous Clear .................. 4-159
DM54163A Synchronous 4-Bit Binary Counter with Synchronous Clear .......................... 4-159
54164 8-Bit Serial In/Parallel Out Shift Register with Asynchronous Clear ...................... .4-167
54165 8-Bit Parallel-to-Serial Converter .................................................... .4-170
DM54166 8-Bit Parallel or Serial In/Serial Out Shift Register ................................... 4-173
54170 4-by-4 Register File with Open-Collector Outputs ....................................... 4-177
54173/DM54173 4-BitTRI-STATE D Register .....•......................................... 4-181
54174/DM54174 Hex D Flip-Flop with Clear ................................................. 4-185
54175/DM54175 Quad D Flip-Flop with Clear and Complementary Outputs ..................... 4-185
DM54180 9-Bit Parity Generator/Checker ................................................... 4-190
DM54181 Arithmetic Logic Unit/Function Generator .......................................... 4-193
54191/DM54191 Synchronous Up/Down 4-Bit Binary Counter with Mode Control ............... .4-209
DM54193 Synchronous Up/Down 4-Bit Binary Counter with Dual Clock ......................... 4-214
DM54194 4-Bit Bidirectional Universal Shift Register ......................................... 4-219
54279 Quad Set-Reset Latch ....•......................................................... 4-227
54283 4-Bit Binary Full Adder with Fast Carry ................................................ 4-229
54298 Quad 2-Port Register (Multiplexer with Storage) ....................................... .4-233
DM54365 Hex TRI-STATE Buffer/Bus Driver ................................... " ... " ..... .4-236
DM54367 Hex TRI-STATE Buffer/Bus Driver ....................... '" ...................... 4-239
DM54368 Hex TRI-STATE Inverting Buffer/Bus Driver ......... " .... " ...................... .4-242
DM7123 Quad TRI-STATE 1-of-2 Line Data Selector/Multiplexer .............................. .4-245
DM7130 10-Bit Magnitude Comparator with Open-Collector Outputs ............................ 4-248
DM7136 6-Bit Unified Bus Comparator with Open-Collector Outputs ........................... .4-250
DM7160 6-Bit Magnitude Comparator with Open-Collector Outputs ............................. 4-253
9300 4-Bit Positive-Edge-Triggered Parallel or Serial Access Shift Register ...................... 4-255
9301 1-of-10 Line Decoder ................................................................ 4-259
9308 Dual 4-Bit Latch .................................................................... 4-262
9309 DuaI1-of-4 Line Data Selector/Multiplexer with Complementary Outputs .................. .4-265
9311/DM9311 4-to-16 Line Decoder/Demultiplexer .......................................... 4-268
9312 1-of-8 Line Data Selector/Multiplexer ................................................. .4-272
9314 Quad Latch ........................................................................4-276
9316/DM9316 Synchronous 4-Bit Binary Counter ........................................... .4-280
9318/DM9318 8 to 3 Line Priority Encoder .................................................. 4-287
9321 Dual 1-of-4 Decoder ................................................................. 4-291
9322/DM9322 Quad 1-of-2 Line Data Selector/Multiplexer .................................... 4-294
9324 5-Bit Comparator ................................................................... 4-297
9328 Dual8-Bit Shift Register ............................................................. 4-301
9334/DM9334 8-Bit Addressable Latch ..................................................... 4-305
9338 8-Bit Multiple Port Register .........................................................•. 4-309
9348 12-lnput Parity Checker/Generator .................................................... 4-313
9601/DM9601 Retriggerable Monostable Multivibrator (One-Shot) with Complementary
Outputs ...............................................................................4-337
9602/DM9602 Dual Retriggerable Monostable Multivibrator (One-Shot) with Complementary
Outputs ...............................................................................4-341
TTL (Low Power)-MII/ Aero
DM54LOO Quad 2-lnput NAND Gate .......................................................... 5-3
DM54L02 Quad 2-lnput NOR Gate ........................................................... 5-5
DM54L04 Hex Inverter .................................................•.................... 5-7
xvii
Alpha-Numeric Index by Family (Continued)
nL (Low Power)-Mill Aero (Continued)
DM54l10 Triple 3-lnput NAND Gate .......................................................... 5-9
DM54l72 AND-Gated Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs ... 5-11
DM54l73 Dual J-K Flip-Flop with Clear and Complementary Outputs ............................ 5-14
DM54l74 Dual Positive-Edge-Triggered D Flip-Flop with Preset, Clear, and Complementary
Outputs .................................................................................5-17
DM54l93 4-Bit Binary Counter ..................•........................................... 5-20
DM54l95 4-Bit Parallel Access Shift Register ................................................. 5-23
DM54l98 4-Bit Data Selector/Storage Register •.............................•.............•.. 5-26
93100 4-Bit Universal Shift Register ........•................................................ 5-28
93l011-of-10 Decoder .................................................................... 5-33
93108 Dual 4-Bit Latch ...........•........................................................ 5-36
93109 Dual 4-lnput Multiplexer .............................................................. 5-39
93110 BCD Decade Counter/4-Bit Binary Counter ............................................. 5-42
93l 12 8-lnput Multiplexer .................................................................. 5-48
93114 Quad latch ......•.........•........................................•.............. 5-52
93L16 BCD Decade Counter/4-Bit Binary Counter ....................... , ............ " ....... 5-42
93121 DuaI1-of-4 Decoder .........•.....•................................................. 5-56
93L22 Quad 2-lnput Multiplexer ............................................................. 5-59
93L24 5-Bit Comparator ...................•............................................... 5-62
93128 Dual 8-Bit Shift Register ..............................................•.............. 5-65
93134 8-Bit Addressable latch ............................................................. 5-69
93138 8-Bit Multiple Port Register .............................. '" ...........•........... , .. 5-74
96102 Dual Retriggerable Resettable Monostable Multivibrator (One-Shot) ....................... 5-78
xviii
Section 1
Introduction to
Bipolar Logic
Section 1-lntroduction to Bipolar Logic
Guide to Bipolar Logie Device Families. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Consolidation of National Semiconductor and Fairchild Semiconductor............. ... ....
IC Device Testing. ....................................... .......... ... ...... ... ....
Functional Index ...................................................................
Glossary of Terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Waveforms....... .............. .......... ........... ............. ..... . ..... ..
1-3
1-7
1-9
1-17
1-26
1-31
Guide to Bi~olar Logic
Device Families
Since the introduction of the first saturating logic bipolar integrated circuit family (DM54/DM74), there have been many
developments in the process and manufacturing technologies as well as circuit design techniques which have produced new generations (families) of bipolar logic devices.
Each generation had advantages and disadvantages over
the previous generations. Today National provides seven
bipolar logic families.
TTL
Low Power TTL
Low Power Schottky
Advanced Low Power Schottky
Schottky
Advanced Schottky
FAST
is sacrificed. The propagation delays are increased threefold. These devices have a typical power dissipation of 1
mW per gate and typical propagation delay of 33 ns, making
this family ideal for applications where power consumption
and heat dissipation are the critical parameters.
LOW POWER SCHOTTKY (DM54LS/DM74LS and 54LS)
The low power Schottky family features a combined fivefold
reduction in current and power when compared to the TTL
family. Gold doping commonly used in the TTL devices reduces switching times at the expense of current gain. The
LS process overcomes this limitation by using a surface barrier diode (Schottky diode) in the baker clamp configuration
between the base and collector junction of the transistor. In
this way, the transistor is never fully saturated and recovers
quickly when base drive is interrupted. Using shallower diffusion and soft-saturating Schottky diode clamped transistors,
higher current gains and faster turn-on times are obtained.
The National LS circuits and a majority of the former Fairchild LS circuits do not use the mUlti-emitter inputs. They
use diode-transistor inputs which are faster and give increased input breakdown voltage; the input threshold is
-O.1V lower than TTL. A few'of the former Fairchild LS
circuits use the traditional emitter inputs and thus have input
breakdown ratings of 5.5V. These circuits are the open-collector gate types 'LS03, 'LS05, 'LS22 and 'LS136; flip-flop
types 'LS74, 'LS109, 'LS112 and 'LS113; and the clock inputs of the 'LS490. Another commonly used input is the
vertical substrate PNP transistor. In addition to fast switching, it exhibits very high impedance at both the high and low
input states, and the transistor's current gain CP) significantly reduces input loading and provides better output performance. The output structure is also modified with a Darlington
transistor pair to increase speed and improve drive capability. An active pull-down transistor (03) is incorporated to
(DM54/DM74)
(54L)
(DM54LS/DM74LS)
(DM!'4ALS/DM74ALS)
(DM54S/DM74S)
(DM54AS/DM74AS)
(54FI74F)
TTL LOGIC (DM54/DM74) and (54xx)
TTL logic was the first saturating logic integrated circuit family introduced, thus setting the standard for all the future
families. It offers a combination of speed, power consumption, output source and sink capabilities suitable for most
applications. This family offers the greatest variety of logic
functions. The basic gate (see Figure 1) features a multipleemitter input configuration for fast switching speeds, active
pull-up output to provide a low driving source impedance
which also improves noise margin and device speed. Typical device power dissipation is 10 mW per gate and the
typical propagation delay is 10 ns when driving a 15
pF/4000 load.
LOW POWER TTL (DM54L)
The low power family has essentially the same circuit configuration as the TTL devices. The resistor values, however,
are increased by nearly tenfold, which results in tremendous
reduction of power dissipation to less than "'Ao of the TTL
family. Because of this reduction of power, the device speed
40kA
20kA
5000
INPUT A
INPUT~8~r==~{
OUTPUT
OUTPUT
TL/F/5534-1
FIGURE 1_ DM5400/DM7400
TUF/5534-7
FIGURE 2. DM54LOO
1-3
yield a symmetrical transfer characteristic (squaring network). This family achieves circuit performance exceeding
the standard TIL family at fractions of its power consumption. The typical device power dissipation is 2 mW per gate
and typical propagation delay is IOns while driving a 15 pF I
2 k!l load.
In addition to the pin-to-pin compatibility of the ALS family, a
large number of MSI and LSI functions are introduced in the
high density 24-pin 300 mil DIP. These devices offer the
designers greater cost effectiveness with the advantages of
reduced component count, reduced circuit board real-estate, increased functional capabilities per device and improved speed-power perfomance.
The basiC ALS gate schematic is quite similar to the LS
gate. It consists of either the PNP transistor or the diode
inputs, Darlington transistor pair pull-up and active pulldown (squaring network) at the output. Since the shallower
diffusions and thinner oxides will cause ALS devices to be
more susceptible to damage from electro-static discharge,
additional protection via a base-emitter shorted transistor is
included at the input for rapid discharge of high voltage static electricity. Furthermore, the inputs and outputs are
clamped by Schottky diodes to prevent them from swinging
excessively below ground level. A buried N + guard ring
around all input and output structures prevents crosstalk.
The ALS family has a typical power dissipation of 1 mW per
gate and typical propagation delay time of 4 ns into a
50 pF/2 k!l load.
SCHOTTKY (DM54S/DM74S)
This family features the high switching speed of unsaturated
bipolar emitter-coupled logic, but consumes more power
than standard TIL devices. To achieve this high speed, the
Schottky barrier diode is incorporated as a clamp to divert
the excess base current and to prevent the transistor from
reaching deep saturation. The Schottky gate input and internal circuitry resemble the standard TIL gate except the resistor values are about one-half the TTL value. The output
section has a Darlington transistor pair for pull-up and an
active pull-down squaring network. This family has power
dissipation of 20 mW per gate and propagation delays three
times as fast as TIL devices with the average time of 3 ns
while driving 15 pF/280!l load.
ADVANCED LOW POWER SCHOTTKY
(DM54ALS/DM74ALS)
The advanced low power Schottky family is one of the most
advanced TIL families. It delivers twice the data handling
efficiency and still provides up to 50% reduction in power
consumption compared to the LS family. This is possible
because of a new fabrication process where components
are isolated by a selectively grown thick-oxide rather than
the P-N junction used in conventional processes. This refined process, coupled with improved circuit design techniques, yields smaller component geometries, shallower diffusions, and lower junction capacitances. This enables the
devices to have increased fT in excess of 5 GHz and improved switching speeds by a factor of two, while offering
much lower operating currents.
ADVANCED SCHOTTKY (DM54AS/DM74AS)
This family of devices is designed to meet the needs of the
system deSigners who require the ultimate in speed. Utilizing Schottky barrier diode clamped transistors with shallower diffusions and advanced oxide-isolation fabrication techniques, the AS family achieves the fastest propagati.on delay that bipolar technology can offer. The AS family. has
virtually the same circuit configuration as the ALS family. It
has PNP transistor or diode inputs with electrostatic protection base-emitter shorted transistors. The output totem-pole
consists of a Darlington pair transistor pull-up and an active
1,1011.
INPUT B~-t-+l"""
60
OUTPUT
TLlF/S534-2
FIGURE 3a. 54174LSOO
TL/F/5534-3
FIGURE 3. DM54LSOO/DM74LSOO
1-4
G)
pull-down squaring network. The inputs and outputs are
Schottky clamped to attenuate critical transmission line reflections. In addition, the circuit contains the "Miller Killer"
network at the output section to improve output rise time
and reduce power consumption during switching at high
repetition rates. The AS family yields typical power dissipation of 7 mW per gate and propagation delay time of 1.5 ns
when driving a 50 pF/2 kO load.
chip sizes are substantially reduced. The base and emitter
ends terminate in the oxide wall; masks can thus overlap
the device area into the isolation oxide. This overlap feature
eliminates the extremely close tolerances normally required
for base and emitter masking, and the standard photolithographic processes can be used.
SELECTING A FAMILY
Two factors shoud be considered when choosing a logic
family for application, speed and power consumption. New
logic families were created to improve the speed or lower
the power consumption of the previous families. The following tables rate each family.
FAST® TECHNOLOGY
FAST (Fairchild Advanced Schottky TTL) circuits are made
with the advanced isoplanar II process, which produces
transistors with very high, well-controlled switching speeds,
extremely small parasitic capacitances and fT in excess of
5 GHz. Isoplanar is an established National process, used
for years in the manufacture of bipolar memories. CMOS,
subnanosecond ECL and 13LTM (Isoplanar Integrated Injection Logic) LSI devices.
Speed
Fastest
AS/F
Slowest
--.--t
INPUT A
b
CC
n"
o
~"
n
~
F
AS
TTL
High
S
t---1~-+-"" OUTPUT
TL/F/5534-4
FIGURE 4. DM54S00/DM74S00
--.--t
INPUT B
TL/F/5534-5
FIGURE 5" DM54ALSOO/DM74ALSOO
1-5
m
-6"
o
iii'
....
ft)
L
ALS
LS
Vee
Vee
o
Power Consumption
ALS
LS
TTL
L
-
Low
S
In the isoplanar process, components are isolated by a selectively grown thick oxide rather than the p + isolation region used in the planar process. Since this oxide needs no
separation from the base-collector regions, component and
c
is:
ft)
~
iii"
UJ
Vee
26
'-+--+----+_ OUTPUT
INPUT A -~HI--f-+""'---I
INPUT B -~~-f--+"...I
TL/F/5534-6
FIGURE 6. DM54ASOO/DM74ASOO
1-6
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~National
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Consolidation of National Semiconductor
and Fairchild Semiconductor
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The combination of National Semiconductor and Fairchild
Semiconductor provides the largest selection of Bipolar
Logic Devices available anywhere. Recognizing that two of
the major product lines overlap-Low Power Schottky and
Standard TTL-both the Mill Aero and Commercial products
were consolidated so as to have the least impact on their
customers.
pie, the QUAD 2-INPUT NAND Gates, DM54LSOO and
54LSOO are both available. The former's performance is described by RET's (Reliability Electrical Test specifications);
and the latter's by a Table I. This is done to prevent considerable inconvenience to our customers who would have had
to modify their Source Control Drawings were a change
made to the device or its name.
While the datasheets in this databook do not describe the
full performance of the Mill Aero devices, the Table I and lor
the RET's do, and may be obtained through your local Field
Sales Offices or Representatives.
In terms of nomenclature, National Semiconductor uses the
prefix "OM" to represent all National-origin MillAero devices. The Fairchild-origin Mill Aero devices uses no "OM" prefix. Ordering information is included as well.
MilitaryI Aerospace Products
All of the MillAero MIL-STD-883 devices were maintained
for both National and Fairchild. In other words, the same
mask set, fab processes and electrical tests and specifications were continued for all devices previously made by
Fairchild Semiconductor as well as National Semiconductor,
whether there was duplication of a device or not. For examOM
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MIL-STO-883/C
'--_ _ _ _ _ _ _-il Device Number
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Package Outline
J = Ceramic Dual-In-Line Package
W = Ceramic Flat Package
E = Ceramic Leadless Chip Carrier Package
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Military Device Family
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Military
Package Outline
= Ceramic Dual-In-Line Package
F = Ceramic Flat Package
L = Ceramic Leadless Chip Carrier Package
o
' - - - - - - - - - - - - - - - 11I
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Device Number
Military Device Family
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Commercial Products
The majority of products in the Low Power Schottky,
Schottky and TTL logic families produced by National and
Fairchild are nearly identical in performance and considerably overlap in portfolio size. All of the sole source functions
were retained after the consolidation to minimize the impact
to our customers. Fairchild devices that remain in the logic
family portfolios are now designated by the National nomenclature. Where a Fairchild device was named 74LS373PC, it
will now be referenced to as a DM74LS373N. Please refer
to the ordering format below.
A+
~
Commercial Burn-In
Package Option
N = Plastic
M = SOIC
J = Ceramic
'-----------i!
Device Number
' - - - - - - - - - - - - - 11I Commercial/Device Family
1 Digital Monolithic
I
1-8
o
Ie Device Testing
c
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-
eQ
Understanding the intent and practice of IC device testing is
vital to insuring both the quality and proper usage of integrated circuits. All National Semiconductor data sheets list
the AC and DC parameters with min and/or max limits,
along with forcing functions. Understanding when a part
fails the limit, and which forcing functions are really tighter,
is critical when determining if an IC device is good or bad.
Certain other devices will have "triple sink" outputs that can
drive 3 times the standard IOL and IOH currents. These devices are generally bus drivers, or drivers intended to drive
highly capacitive loads. Finally, there are certain devices
that have PNP inputs that reduce the IlL loading to typically
-200 /-LA, thus allowing an increased DC fan-in of 20. One
must therefore be careful when interfacing many different
types of devices, even in the same family, and not Simply go
the "fan-out of 10" rule.
When dealing with any kind of device specification, it is important to note that there exists a pair of test conditions that
define that test: the forcing function and the limit. Forcing
functions appear under the column labeled "Conditions"
and define the external operating constraints placed upon
the device tested. The actual test limit defines how well the
device responds to these constraints. For example, take the
parameter VOH(min) for the DM74LSOO. It is tested at
VCC(min) = 4.75V commercial, using an IOH = -400 /-LA. If
we required an IOH = -BOO /-LA, this would be a "tighter"
test, as the output voltage drops with increased IOH. Hence,
a device that would pass the -800 /-LA IOH would also pass
the - 400 /-LA IOH' but not necessarily the other way around.
Futhermore, VOH tracks with Vcc, which is why VCC(min) is
the worst-case testing, and not VCC(max)' Finally, forcing inputs to threshold represents the most difficult testing because this puts those inputs as close as possible to the
actual switching point and guarantees that the device will
meet the VIHIVIL spec.
All of National's databook parameters are defined and guaranteed for "worst-case testing." Input loading currents (fanin) are tested at the input and Vcc levels that most increase
that loading, while the output drive capability (fan-out) is
tested at the input and Vcc levels that most decrease that
capability. Icc is tested with the input conditions and Vcc
level that yield the greatest Icc value, and VCLAMP is tested
such that the negative voltage is maximized for the given
clamp current. The fan-in and fan-out specs are contained
in the IIH, IOH' IlL and IOL values. To guarantee these fan-in
and fan-out limits at 10, the IOL must be at least 10 times
the IlL and the IOH must be at least 10 times the IIH. Be
aware that the fan-in and fan-out specifications are valid
only within a given device family. The standard input loading
and output drives are shown in Table I.
Notice that the IOL is at least 10 times the IlL and that the
IOH is greater than 10 times the IIH. Also notice that these
are "standard" drive and load currents for single sink outputs and inputs. Certain devices may have multiple load inputs where the input line goes to several input structures
and has, say, 2 or 3 times the normal IlL and IIH loading.
TABLE I. Fan-ln/Fan-Out
Device Family
Input Loading
TTL
IlL = -1.6 mA
IIH = 40/-LA
Low Power
Schottky
IlL
=
IIH
Schottky
IlL
IIH
= 20/-LA
= -2mA
= 50/-LA
-400/-LA
. 1-9
Output Drive
IOL = 16mA
IOH = - 400/-LA
IOL = 4 mA (Mil)
IOL = 8 mA (Com)
IOH = -400/-LA
IOL
IOH
= 20mA
=
-1 mA
Tables II and III show the "direction" of the looser/tighter
testing for most common DC parameters. Notice that one
can tighten either the forcing function or the limit, or both.
Tightening either one is sufficient to insure a tighter test.
Also notice the difference between max and min limits. For
los (double-ended limits), even though -20 mA is more
positive than -100 mA, and is mathematically the max limit,
the magnitude of the number is the determining factor when
deciding which is the max limit. The negative sign simply
implies the direction that the current is going, with a negative current leaving the device, and a positive current entering the device. Table II shows the direction of tighter forcing
functions, while Table III shows the direction of tighter limits.
TABLE II. Looser/Tighter Forcing Functions Example: DM74LSOO
Condition
11K
10H
10L
VI
VIH
Vil
Vo
Vee
Test
Looser
Nominal
Tighter
Units
VIK
VOH
VOL
II
IIH
ill
los
Icc
-17
-350
3
6.5
2.6
0.5
0.1
5.0
-18
-400
4
7
2.7
0.4
0.0
5.5
-19
-450
5
7.5
2.8
0.3
-0.1
6.0
mA
p.A
mA
V
V
V
V
V
TABLE III. Looser/Tighter Test Limits Example: DM74LSOO
Parameter
VIH(min)
VIL(max)
VIK(max)
VOH(min)
VOL(max)
II(min)
IIH(max)
IIL(max)
10S(max)
10S(min)
ICCH(max)
ICCL(max)
Looser
Nominal
Tighter
Units
2.1
0.7
-1.6
2.6
0.6
6.5
50
-450
-110
-10
1.7
4.5
2.0
0.8
-1.5
2.7
0.5
7.0
40
-400
-100
-20
1.6
4.4
1.9
0.9
-1.4
2.8
0.4
7.5
30
-390
-90
-30
1.5
4.3
V
V
V
1-10
V
V
V
p.A
p.A
mA
rnA
mA
rnA
Following are the test set-ups that are used to test the DC
parametrics. In each case, the gate connection, equivalent
circuit schematic and resultant voltage/current plot are
shown.
measured. For typical LS products, the military and commercial test points are indicated on the VOL vs IOl graph. In
each case, the device must not exceed the VOL spec when
the IOl current is being forced.
The indicated graphs are typical of LS products and are
simi liar to other bipolar logic families. The schematics
shown are for single inversion devices and represent generalized circuits.
OUTPUT VOLTAGE HIGH LEVEL (VOH)
One input is tied high (any value above 2.0V) and the other
input is forced at the Vil threshold (assuming a single inversion gate). The minimum Vee value is used. Each input is
tested independently and the IOH current is forced. The resulting VOH is measured. The VOH vs IOH graph shows the
military and commercial VOH/IOH test points for standard
LS products.
OUTPUT VOLTAGE LOW LEVEL (Vou
Both inputs are connected to logic "1" values (assuming an
inverting gate) and forced at the VIH specs. Vee minimum is
used, and IOl is forced on the output. The resulting VOL is
VOlVS IOL
VOHvslOH
o Typical LS Device Curve
20 Typical LS Device Curve
JII' ~
16
l
12
l
~
II
~
Mil:
Com:
10L
VOL
4.0 rnA
B.OmA
0.40V
O.SOV
)
-100
1-+-+-+""-1-+--1
-400
I---r.--f--HH--+-I--I
IOH
-400,.A
-400,.A
Mil:
Com:
VOH
2.SV
2.7V
j
o
o
0.2 0.4 0.6 0.8 1.0 1.2 1.4
VoL (VI
2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VO/I (VI
TlIF/6731-1
TlIF/6731-2
Vcc=MIN
$IoK
VIN
LOW
TL/F/6731-3
TlIF/6731-4
Vcc:=MIN
-4~---"""~VcC=MIN
•
10K
TlIF/6731-5
TlIF/6731-6
1-11
INPUT CURRENT HIGH LEVEL (IIH)
IIH tests the input leakage in the high state. For MET, diode,
and PNP input, the test set-up consists of all inputs except
the one under test tied high (greater than VIH). The remaIning input has the VIH value forced upon it, and the resultant
IIH is measured. This test checks for emitter-to-collector inverse transistor action for MET inputs, and reverse bias
leakage for diode and PNP inputs.
For MET Inputs, there is also an additional set-up for IIH
testing that checks for emitter-to-emitter transistor action.
This is done with all the other inputs tied to ground.
INPUT CURRENT LOW LEVEL (In)
One input at a time is tested with the other inputs tied to a
solid "1" value~Vcc is set to the maximum value and the
VIL value is forced. IlL is then measured.
MAXIMUM INPUT CURRENT (II)
liar BVIN testing is the same as the emitter-to-collector
leakage test (IIH) and guarantees that the input will not pass
more than the specified current at the stated specification
(100 /LA at 7V for LS).
IlL is intended to measure the value of the base pull-up resistor on the input, and to guarantee the maximum input
load an Ie presents.
liN va VIN (High State)
20 Typical LS Device Curve
10
Standard Inputs.
I - (Vee - (VIL + VSH)]
IL R1.
Diode Inputs
I - (Vee - (VIL + VSE))
IL R1 X {j
PNPlnputs
o
liN vs VIN (Low State)
Typical LS Device Curve
-1011
15r-+-+-+-~-r-r-r~
i
I - (Vee-(VIL + VsEl]
IL -,
R1
t-HH--t--t-+-+-I
.i
J
"".
"",-
"""
If
~"
-
IlL
-400 p.A
VIL
O.40V
-4011
-5
,
-5011
1.2 1.4 1.6 l.a 2.0 2.2 2.4 2.6 2.a
VIN IVI
o 0.2 0.4 0.6 0.8 1.0 1.2 1.4
VILIVI
TL/F/6731-6
TUF/6731-7
Vcc=MAX
OP~::b-
LOGIC 1
YIN
TUF/6731-10
TL/F/6731-9
hH
TUF/6731-12
TUF/6731-11
1-12
OUTPUT SHORT CIRCUIT CURRENT (lOS)
loS is measured with VCC(max) and the OV forced on the
output while it is in the high state. The resultant current Is
measured. The purpose of this is to check the los resistor
that forms the Darlington's collector pull-up. This parameter
is important as it reflects both the maximum current the device will draw and the maximum drive it will provide when it
is switching from low to high.
Caution must be taken when measuring TTL, LS and S outputs as the power dissipated on the die will be substantial.
los shorts should not be maintained in excess of one second or damage to the device may result.
SUPPLY CURRENT HIGH LEVEL (ICCH) AND SUPPLY
CURRENT LOW LEVEL (ICCl)
Both ICCH and leeL are tested using the Vee maximum value. The inputs are set to the values necessary to achieve
the output in the desired state. All outputs are left open,
neither sourcing nor sinking current. The goal of this test is
to guarantee the maximum quiescent operating power that
the device will draw.
Vo vs los
Typical LS Device Curve
-20
~,,~
i..;o>'
-80
-100
~
ICClVSVCC
2.5 Typical LS Device Curve
,,-
los
Min
-20
Max
-100
2.0
Volts
5.25V
,;-
/
"
0.5
V'
0.0
o
ICC
I.SmA
o
0.5 1.0 1.5 2.0 2.5 3.0 3.5
Yo IV)
1
/
4
Vec (V)
TL/F/6731-14
TL/F/6731-13
V!:e=MAX
",.",~ ....
5
"'''-9VccDMAX
-.
AND
LOGIC
LOOIC "0"
OPEN
'::'
TL/F/6731-16
TL/F/6731-15
V!:c=MAX
.....- - - -.......... V!:e=MAX
•
YoUT =OV
TL/F/6731-18
TUF/6731-17
1-13
~r-------------------------------------------------------------~
=i
{!!.
8
'?'
c_
5:::!
the output will have the greatest drive capability and the
TRI-STATE control can effectively "turn off" the output under these conditions.
INPUT CLAMP VOLTAGE {VIC OR VIKl
VCLAMP(Vlld is measured with all but one input tied high and
the 11K current forced on the remaining input. Vcc is set to
the minimum and the VIK voltage is measured.
TRI-STATE ISINK: Output is set in the high state and then
TRI-STATE mode. VOZl = O.4V is then applied. The current drawn out of the device is then measured.
OUTPUT TRI-5TATE CURRENT HIGH LEVEL (IOZH) AND
OUTPUT TRI-5TATE CURRENT LOW LEVEL (IOZL)
TRI-STATE ISOURCE: Output is set in the low state and then
TRI-STATE mode. VOZH = 2.7V is then applied. The current drawn into the device is then measured.
TRI-STATE'" ISINK and ISOURCE are measured with the output control input tied to the appropriate threshold value
(usually VIL = O.BV) and with VCC(max). This is to insure that
IOZHVSVOZH
(TRI-STATE ISOURCE),
IOZLVSVOZl
(TRI-STATE ISINK)
Typical LS Device Curve
VCLAMP VS ICLAMP
o Typical LS Device Curve
J~
I(
1
j
12
1&
20
-1.6
ICLAMP
VCLAMP
-18mA
-1.5V
20
10
10
J
I
-1.2
10Z
Voz
IOZl - 20,.A 0.4V
IOZH 20 ,.A 2.7V
~
-10
iozH
lOlL
-20
0.5 1.0 1.5 2.0 2.5 3.0 3.5
VozIV)
-0.8 -0.4
VCLAMP IV)
Tl/F/6731-19
r:::t:"
Tl/F/6731-20
Vee = MIN
hN:::l.J-
Vcc=MAX
Tl/F/6731-21
YcC=MIN
J
Rl
INPUT
ilL
OUTPUT CONTROL
Tl/F/6731-22
Tl/F/6731-23
1-14
HIGH LEVEL OUTPUT CURRENT (OPEN-COLLECTOR
DEVICES ONLY)
AC SWITCHING CHARACTERISTICS
The AC switching characteristics are generally measured in
units of time (commonly in nanoseconds), and define how
long it takes for the signal to propagate from the input to the
output. The definitions used in determining the pass/fail
status of each limit are not the same for AC as they are for
DC. The distinction lies in the fact that for DC operation
there exists one characteristic V-I curve on which the device
must operate. Devices are good if they operate on the correct side of the limit, and bad if they operate on the wrong
side of the limit. When dealing with certain AC parameters
(fMAX, tSET-UP tHOLD tRELEASE tpw), the device can, and
usually does, operate on both sides of the databook limit.
The limit really implies a boundary that all devices are guaranteed to exceed. Depending upon the parameter, the device will either operate at all values above and some below
the limit, or it will operate at all values below and some
above the limit. In each case, the device is only guaranteed
to operate for all values on one side of the limit. Although
the device will also operate beyond the limit, it is not guaranteed to. Furthermore, device operation beyond the limit is
not considered a failure. For instance, take the fMAX parameter with a min limit of 25 MHz. All devices are guaranteed
to operate at all frequencies below 25 MHz and will operate
in excess of 25 MHz, although this is not guaranteed. Now,
take the example of tSET-UP with a minimum limit of 25 ns.
All of the devices are guaranteed to operate with a set-up
time of 25 ns and longer, and will operate with set-up times
below 25 ns, although this is not guaranteed either. Be
aware that both of these specifications are listed in the minimum column in the databook, but the interpretation of what
is failing differs significantly.
ICEX Is tested with the output in the high state. Vee is set to
5.0V and the specified voltage (5.5V for LS) is applied to the
output. The inputs are at the threshold values (O.8V and
2.0V, depending upon the logic to put output in the high
state) and the resulting ICEX leakage current is measured.
ICEXVSVOUT
(Open-Collector Device)
250 Typical LS Device Curve
200
ICEX
VOUT
250 p.A 5.5V
150
~,OO
11
50
~
-50
01234567
VOUT IVI
TUF16731-24
Propagation delays (called prop delays and denoted by the
symbols tpHL and tPLH) are specified as maximum limits,
and guarantee the maximum time one must wait to insure
that the correct data has appeared at the device's output.
Each propagation delay is specified from one input to one
output only.
TUF16731-25
Vee MAX
I
Input set-up and hold times (including tRELEASE) specify
how long one input must be stable at a particular logic level
prior to an action occurring at another input. For example,
take the DM54174LS74 positive-edge-triggered D flip-flop.
The "set-up 1" specification defines how long a logic "1"
must be present and stable at the DATA input prior to the
positive edge of the CLOCK to insure that the device will
recognize that data as a "1". There also exists a "hold 1"
specification which specifies how long a logic "1" must be
held after the active edge of CLOCK for the device to recognize that logic "1". Both the set-up and hold times must
always be met or the device will not necessarily bring in the
proper data. Set-up times are generally pOSitive, while hold
VIN LOW {
TLIF16731-26
1-15
•
cn.-----------------------------------------------------------------------------~
IB
~
~
times may be either positive or negative, usually negative.
The meaning of a negative hold time Is that the data may be
removed from the Input prior to the active edge of CLOCK,
and the CLOCK will still bring in the desired data. Set-up
and hold times are speciflad as minimum values, since this
defines the minimum time data must be stable prior to any
change at the CLOCK input. Removing the data sooner than
the minimum time may cause improper action on the part of
the device.
tRELEASE is specified on devices where there is an input
that must be set inactive prior to the active edge of CLOCK.
Such inputs are usually overriding inputs like CLEAR and
PRESET. With CLEAR active, it will prevent the device from
switching on the CLOCK signal. tRELEASE is defined as the
time it takes for the CLEAR input to "release" the device for
clocking action, and is specified as a minimum. This represents the maximum delay required between CLEAR going
inactive and the active edge of CLOCK to insure proper
device operation.
All devices that have a CLOCK input also have a specification that defines the maximum speed that the CLOCK can
be driven, called fMAX. This specification is defined as a
minimum specification and states that all of the devices will
be able to operate at frequencies up to 25 MHz. For the
DM54/74LS74 with an fMAX of 25 MHz, all of the devices
are guaranteed to operate at all clock frequencies, up to
and including 25 MHz. Aithough no devices are guaranteed
to operate above fMAX (only below it), most devices will
operate beyond the maximum speCification. The minimum
limit does not state that the device will not operate below
fMAX or that any devices that do are bad, but rather that all
the devices will operate up to the limit.
Table IV shows the direction of the tighter testing for the
more common AC parameters. All prop dealys (those AC
parameters that have the symbols tpLH or tpHU have simple
minImax limits. The device is guaranteed to operate within
the bounds of the minImax limits, and any operation outside
these limits denotes a device failure. tSET-UP, tHOLD, fMAX,
and tRELEASE parameters have limits that denote guaranteed operation boundaries (i.e., the device is guaranteed to
operate up to the boundary) but no guarantee is made concerning the device operation (or lack of it) beyond the
boundary.
For detailed information on the AC waveforms, please see
the test waveforms in this section.
TABLE IV. LooserlTlghter AC Test Limits Example: DM74LS74
Test
fmax(mln)
tPLH(max)
tPHL(max)
tW(min)
tW(min)
tsET-UP(min)
tsET-UP(mln)
tHOLD(min)
From
Looser
Nominal
Tighter
Units
CLR, PRE, eLK
CLR, PRE, CLK
CLOCK HIGH
PRE,CLRLOW
DATA HIGH
DATA LOW
All DATA
24
26
31
21
26
21
21
1
25
25
30
20
25
20
20
0
26
24
29
19
24
19
19
-1
MHz
ns
ns
ns
ns
ns
ns
ns
1-16
~NatiOnal
Semiconductor
Functional Index
Arithmetic Operators
Technology
Function/Description
STD
Type
54
Adder/Binary 4-Bit with Fast
Carry
ALU with Carry Look Ahead
'83
X
'283
X
'181
X
S
L
TTL
74
54
X
74
54
LS
74
54
No.
of Bits
No.
of Pins
16
74
X
4
X
X
X
X
4
16
X
X
X
X
4
24
X
'381
X
4
20
93541
X
4
24
Binary to BCD Converter
'185
X
6
16
BCD to Binary Converter
'184
X
6
16
4X2
24
Lookahead Carry Generator
'182
Multiplier/Twos Complement
93543
9-Bit Parity Generator/Checker
'180
X
X
X
93562
12-Bit Parity Generator/Checker
4-Bit Magnitude
with Expander
16
X
'280
Comparator
X
X
9348
X
'85
X
X
X
X
9
14
X
9
14
X
9
14
12
16
4
16
X
X
X
5-Bit Magnitude
9324
5
16
Hi-5peed 6-Bit
Identity with
Expander
93546
X
6
16
Hi-Speed 6-Bit
Identity with
OC'
93547
X
6
16
6-Bit Unified
BuswithOC'
7136
X
6
16
6-Bit Magnitude
withOe'
7160
X
6
16
10-Bit
Magnitude with
OC'
7130
X
10
24
'97
X
64
16
6-Bit Binary Rate Multiplier
X
'OC : Open Collector
1-17
II
Counters
Technology
FunctIon/DescrIption
4·Bit Binary Counter
Type
'93
STD
S
L
TTL
54
74
54
X
X
X
74
54
74
54
'97
X
X
Asynchronous Decade Counter
'90
X
X
Synchronous 4-Bit Binary
Counter with Asynchronous
Clear
'161
X
X
Synchronous Presettable BCD
Decade Counter
'160
X
Synchronous 4-Bit Binary
Counter with Synchronous Clear
'163
X
Synchronous Presettable BCD
Decade Counter
Clock
Edge
No.
of PIns
''-
14
.../
16
74
X
X
'293
Synchronous Modulo 64-Bit
Rate Multiplier
Up/Down
LS
14
X
X
'-
14
X
X
.../
16
X
X
.../
16
X
X
.../
16
'162
X
X
.../
16
Synchronous Bidirectional BCD
Decade Counter
'168
X
X
.../
16
Synchronous 4-Bit Up/Down
Binary Counter
'169
X
X
X
.../
16
Synchronous Up/Down Decade
Counter with Mode Control
'190
X
X
X
.../
16
Synchronous 4-Bit Up/Down
Binary Counter with Mode
Control
'191
X
X
X
X
.../
16
Synchronous 4-Bit Up/Down
Binary Counter with Dual Clock
'193
X
X
X
X
.../
16
Asynchronous Presettable
Decade Counter
'196
X
'-
14
Asynchronous Presettable
Binary Counter
'197
X
'-
14
BCD Decade Counter/4-Bit
Binary Counter
X
X
X
X
X
X
X
9310
9316
X
TRI-STATE4D Programmable
4·Bit Binary Counter
7556
X
Decade Counter with Separate
Up/Down Clocks
'192
Decade Counter
'290
Dual Decade (Bi-Quinary)
Counter
'390
Dual4-Bit Binary Counter
'393
Dual Decade Counter
'490
X
X
.../
16
X
.../
16
.../
16
.../
16
X
'-
14
X
'-
16
X
''-
14
X
X
1-18
X
X
X
16
Decoders/Demultiplexers
Technology
Function/Description
Type
Dual 1 of4
9321
STD
TTL
L
54
74
54
X
X
X
X
X
74
'139
'155
LS
S
54
74
X
54
X
'156
10f8
9301
X
X
'45
X
X
'42
X
X
X
1 of 10
X
X
9301
X
X
Active
Low
Enable
Active
Low
Outputs
No.
of Pins
2+2
1 +1
4+4
16
74
X
X
2+1
1 +1
4+4
16
X
X
2
2+1
4+4
16
X
X
2
2+1
4+4
16
3
1
8
16
X
'138
'145
Address
Input
X
3
1
8
16
X
X
3
1
8
16
X
X
3
2
8
16
3
1
8
16
4 (BCD)
10
16
4 (BCD)
10
16
4 (BCD)
10
16
10
16
X
'45
X
X
'42
X
X
'145
X
X
4 (BCD)
1 of 16
9311
X
X
4
2
16
24
'154
X
X
4
2
16
24
8 to 3·Line Priority
Encoder
9318
X
X
'148
X
X
X
X
X
8
16
8
16
Display Decoders/Drivers
Technology
Function/Description
1 of 10 Driver (DC·)
BCDt07·Seg
Decoder/Driver (DC·)
BCDt07·Seg
Decoder/Driver
STD
TTL
Type
L
S
Active
Hi/Low
LS
74
Ripple
Blanking
No.
of Pins
54
74
'45
X
X
L
'145
X
X
L
X
L
X
16
'46
54
74
54
54
74
16
16
L
X
16
H
X
14
X
L
X
16
X
X
H
X
16
'347
X
X
L
X
16
'447
X
X
L
X
16
'48
X
X
H
X
16
'248
X
X
H
X
16
L
X
16
'47
X
X
X
'49
X
'247
X
'249
X
9370
X
9374
X
L
X
16
9368
X
H
X
16
'OC : Open Collector
1·19
II
Flip Flops-Single & Dual
Technology
Function/Description
OualJK
STD
TTL
Type
L
54
74
54
'73
X
X,
X
X
'76
X
'107
X
'109
X
S
54
74
74
54
74
X
X
X
X
X
X
X
'112
X
X
'113
X
X
X
J, K
X
J, K
../
X
J,K
J,K
''''-
D
../
Clock
Inputs
Broadside
Pinout
X
J, K
X
J, K
X
'72
X
'74
X
X
X
X
X
Direct
Set
Clock
Edge
'''-
J,K
J, K
'114
Dual 0
Inputs
LS
X
Direct
Clear
No.
of Pins
X
14
X
16
X
14
X
X
16
X
X
16
X·
14
X
X
14
X
X
14
X
X
14
'Does not apply to LS.
Flip Flopa-Multlple
Technology
STD
TTL
L
No.
of Pins
54
74
54
74
54
4·Bit 0 Flip Flop
'175
X
X
X
X
X
X
4xO
../
6·Bit 0 Flip Flop
'174
X
X
X
X
X
X
6XO
../
X
16
8·Bit 0 Flip Flop
'374
X
X
X
X
8XO
../
X
20
X
X
8xO
../
'534
X
8XO
../
'574
X
8XO
../
X
'564
X
8XD
../
X
X
8XO
../
1xD
L
16
2X4XO
'-
16
74
LS
TRI-STATE
Output
Type
54
S
Data
Inputs
Function/Description
'377
X
'373
8·Bit Multiple Port
Register
9338
X
Quad 2·Port Register
'298
X
X
X
X
74
X
X
1·20
X
16
20
X
20
X
20
20
X
20
Gates
Technology
Function/Description
NAND
NOR
AND
Exclusive-OR
Type
No.
of Pins
LS
74
54
74
X
X
X
X
X
X
X
14
X
X
X
14
'12
X
X
14
'13
X
X
14
74
54
X
X
X
Quad 2·lnput NAND
withOC'
'01
X
X
'03
X
X
Triple 3·lnput NAND
'10
X
X
Triple 3·lnput NAND
withOC'
Dual4·lnput Schmitt
Trigger
Dual 4·lnput NAND
'20
Dual 4·lnput NAND
withOC'
'22
X
'30
X
X
Quad 2·lnput Schmitt
Trigger NAND
'132
X
X
13·lnput NAND
'133
Quad 2·lnput NOR
'02
X
X
Dual 4·lnput NOR
with Strobe
'25
X
X
'27
Dual 5·lnput NOR
'260
Quad 2·lnput AND
'08
X
X
Quad 2·lnput AND
withOC'
'09
X
X
'11
Triple 3-lnput AND
withOC'
'15
Dual4-lnput AND
'21
Quad Ex-OR
'86
Quad 2-lnput Ex-OR
withOC'
'136
4-Bit Quad Ex-NOR
withOC'
9386
Quad 2-lnput ExNORwithOC'
'266
Expandable Dual
2-Wide 2-lnput
'50
'32
X
X
X
X
14
X
14
X
X
X
14
X
X
X
14
X
X
X
X
16
X
X
X
X
14
X
X
X
14
X
X
X
X
X
X
14
X
X
X
Triple 3·lnput NOR
Triple 3-lnput AND
74
14
X
8·lnput NAND Gate
Quad 2-lnput ORI
Inverters
S
54
54
'00
Exclusive-NOR
OR
Gates
Invert
L
Quad 2·lnput NAND
OR
AND
STD
TTL
X
X
X
X
X
14
X
X
14
X
X
X
14
X
X
X
14
X
X
14
X
X
14
14
X
X
X
X
X
X
X
14
X
X
14
X
X
14
X
14
X
X
X
14
14
Dual 2-Wide 2-lnput
'51
'54
X
X
X
X
14
4-Wide 2-lnput
2-Wide 4-lnput
'55
X
X
14
4-Wide
'64
Hex Inverters
'04
X
X
Hex Inverter with OC'
'05
X
X
Hex Schmitt Trigger
Inverter
'14
X
X
X
X
X
'OC : Open Collector
1-21
X
14
X
X
X
X
X
X
14
X
X
X
14
X
X
14
14
II
Latches
Technology
Function
4·Bil 0 Latch
STD
TTL
Type
'75
L
54
74
X
X
54
S
74
54
LS
74
'375
Dual4·Bit 0 Latch
9308
X
X
X
4·Bit 0 Latch
9314
X
X
X
8·Bit 0 Latch
Data
Inputs
Enable
Inputs
(Level)
TRI·STATE
Outputs
No.
01 Pins
54
74
X
X
4XO
2(H)
X
X
4XD
2(H)
16
8XO
2X2
ANO
24
16
4xO
1(L)
16
X
8xO·
1(H)
X
20
'533
X
8XO
1(H)
X
20
'563
X
8XO
1(H)
X
20
'573
X
8XO
1(L)
X
20
1xO
1(L)
16
X
'373
X
X
X
X
X
B·Bit Addressable
Latch
9334
'259
X
X
1xO
1(L)
16
Dua14-Bit
Addressable
Latch
'256
X
X
BXO
2(L)
16
4·Bit RS Latch
'279
X
X
4X(R"S)
X
X
"'0" only for SKY.
1·22
16
Line and Bus Drivers/Transceivers/Receivers
Technology
Function/Description
STD
TTL
Type
Quad 2 NAND Buffer
'37
Quad 2 NAND Buffer with OC'
'26
'38
54
X
X
X
'39
'96101
Dual 4 NAND Buffer
'40
X
74
X
X
X
X
X
X
'140
Quad 2 NOR Buffer
'28
Quad 2 NOR Buffer with OC'
'33
Quad TRI-STATE Buffer
'125
X
X
X
X
X
X
X
X
X
X
X
X
X
54
74
54
74
'07
Hex Inverting Buffer/Driver with
High Voltage OC'
'06
Hex TRI-STATE Buffer/Bus
Driver
'365
Hex Inverting TRI-STATE
Buffer/Bus Driver
'368
Octal Buffer/Line Driver with
TRI-STATE Outputs
'540
Octal TRI-STATE Buffer/Bus
Driver
'465
Octal TRI-STATE Inverting
Buffer/Bus Driver
'466
Octal TRI-STATE Buffer/Line
Driver/Line Receiver
'241
Octal TRI-STATE Inverting
Buffer/Line Driver/Line Receiver
'240
Octal TRI-STATE Bus
Transceiver
'245
'17
'16
'367
54
X
X
X
X
X
14
14
X
X
X
X
X
X
X
X
X
X
14
14
14
14
14
14
14
14
14
14
'366
'467
'468
X
X
X
X
X
X
X
X
X
'243
X
'645
14
14
X
X
X
X
X
X
'244
74
X
X
X
14
'126
Hex Buffer/Driver with High
VoltageOC'
No.
of Pins
LS
S
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
16
16
16
16
20
20
20
20
20
20
20
20
14
20
20
•
'OC: Open Collector
1-23
I
Monostables (One-Shots)
Technology
No of
STD
TTL
L
Resettable
Min
Output
(tw) ns
No.
of Pins
50
14
X
45
14
2
40
14
2
40
14
In~ uts
LS
Function/Description
Type
54
74
Pos.
Neg.
Single Retriggerable
9601
X
X
2
2
'122
X
X
2
2
2
1
54
S
74
54
74
54
X
'122
Single NonRetriggerable
Dual Retriggerable
'121
X
X
9602
X
X
X
X
96S02
X
96LS02
X
'123
Dual NonRetriggerable
74
X
X
1
1
X
72
16
1
1
X
27
16
1
1
X
35
16
1
1
X
45
16
'123
X
1
1
X
40
16
'221
X
1
1
X
40
16
Multiplexers
Technology
Function/Description
Quad 2-lnput
Type
STD
TTL
L
54
74
54
9322
X
X
X
'157
X
X
True
Outputs
54
74
1
X
X
X
X
X
1
X
'158
X
X
X
X
1
'257
X
X
X
X
1
X
X
X
X
1
X
X
Clocked
X
'153
X
X
'253
X
X
'151
X
X
'251
X
Quad 2-lnput
TRI-STATE
7123
X
16-lnput
'150
X
X
16
16
TRI-STATE
16
16
16
X
X
2
X
X
X
X
2
TRI-STATE
X
X
2
X
X
2
16
X
16
TRI-STATE
16
X
X
16
X
X
X
X
1
X
X
16
X
X
X
X
1
TRI-STATE
TRI-STATE
16
X
14
1
X
X
16
1
X
X
'152
9312
16
X
X
X
No.
of Pins
16
TRI-STATE
X
'353
9309
Complementary
Outputs
X
X
'352
8·lnput
Enable
Inputs
74
'298
74
LS
54
'258
Dual4-lnput
S
X
X
1
1-24
16
X
24
Registers
Technology
Function/Description
Paralielln/ParalielOut
Shift Right
Type
STD
TTL
S
L
54
74
54
9300
X
X
X
'95
X
X
X
74
54
74
X
No. of
Bits
Serial
Entry
Parallel
Entry
No. of Bits
Clock
Edge
No.
of Pins
16
54
74
4
J, K
4S
X
X
4
D
4S
X
X
4
J, K
4S
...-r
'-...-r
X
X
'195
LS
14
16
Paralielln/Paraliel Out
Shift Right (TRI·STATE)
'295
X
X
4
D
4S
'--
14
'395
X
X
4
D
4S
16
Parallel In/Paraliel Out
Bidirectional
'194
X
X
X
4
DR,DL
4S
'-...-r
QuadD
'173
X
X
X
X
'379
Quad 2 Port Register
'298
Parallel D Register
'378
Multiport Register
9338
X
X
X
X
4
4S
X
X
4
4S
X
X
4
2D(Mux)
X
X
X
'322
6
6S
8
D
X
X
8
2D
8S
16
...-r
...-r
'-...-r
...-r
...-r
20
...-r
14
...-r
...-r
...-r
...-r
...-r
...-r
...-r
...-r
16
16
16
16
16
16
Serial/Parallel In,
Parallel, Serial Out, Shift
Right
Serialln/Paraliel Out,
Shift Right
'164
X
X
X
X
8
2D
ParaliellSerialln, Serial
Out, Shift Right
'165
X
X
X
X
8
D
8A
'166
X
X
8
D
8S
Successive Approx.
Register
'502
X
X
8
D
'503
X
X
8
D
8
D
2503
Paralielln/Paraliel Out
Bidirectional
(TRI-8TATE)
'299
Serialln/SerialOut,
Shift Right
9328
Octal D Register
'273
Register
File
I (OC')
I (TRI·STATE)
8·Bit Shift Register
(TRI·STATE)
Data Selector/Storage
Register
X
X
'323
X
X
X
X
8
DR,DL
8S
X
X
8
DR,DL
8S
2x8
2x2D
Mux
X
16
16
16
16
20
20
16
X
X
8
8S
...-r
20
X
X
4X4
4A
'--
16
X
X
4X4
4A
16
'952
X
8
'962
X
8
'-...-r
...-r
'--
'170
X
X
'670
'98
X
4
'S = Synchronous, A = Asynchronous, OC : Open Collector
1·25
2 D(Mux)
18
18
16
•
Glossary of Terms
DC Operating Conditions and Characteristics
GENERAL DEFINITIONS
OUTPUT CURRENT PARAMETERS
I: Current is the flow of electric charge from one potential to
another through a conductor. The unit of measure is the
Ampere, or Amp, abbreviated A. One Amp is equal to the
current flowing through one ohm of resistance when one
volt is applied across that resistance. Common units found
in the semiconductor industry are the milliampere, abbreviated mA, equal to 0.001A and the microampere, abbreviated p.A, equal to 0.000001 A. Negative current is defined as
current flowing out of a device terminal and positive current
is defined as current flowing into a device terminal.
ICEX Output Leakage Current: The current flowing into an
open collector output when input conditions have been applied that, according to the product specification, will cause
the output to be in the logic high state. This test checks the
reverse breakdown of the output transistor.
lo(off) OffoState Output Current: The current flowing into
an output with input conditions applied that, according to the
product specification, will cause the output switching element to be in the off state.
NOTE: This parameter is usually specHied for open collector outputs Intend·
ed to drive devices other than logic circuits, such as displays. Any
leakage current applied to a display may cuase the display to be
activated.
V: Voltage, or the electromotive force which causes current
to flow through a conductor. One Ampere of current flowing
through one ohm of resistance develops a potential difference of one volt across that resistance. The unit of measure
is the Volt, abbreviated V, and a common unit is the millivolt,
abbreviated mV, equal to O.OOW.
10H High Level Output Current: The current flowing out of
an output with input conditions applied that, according to the
product specification, will establish a logic high level at the
output. This test guarantees the current sourcing (drive) capability of the output and the fan-out specified for the family.
INPUT CURRENT PARAMETERS
II Maximum High Level Input Current: Current flowing into
an input when that input has the maximum voltage specified
for the family applied to it. This test is used to guarantee the
minimum reverse breakdown voltage of the input structure.
10L Low Level Output Current: The current flowing into an
output with input conditions applied that, according to the
product specification, will establish a logic low level at the
output. This test guarantees the current sinking capability of
the output and the fan-out specified for the family.
IIH High Level Input Current: The current flowing into an
input when that input has a high level voltage equal to the
minimum high level output voltage specified for the family.
This test is used to check the emitter-to-emitter leakage and
the inverse transistor action of a multi-emitter transistor input, the input leakage of a diode, PNP transistor, or CoB
short type of input, and to guarantee the fan-in specified for
the family.
los Output Short-CIrcuit Current: The current out of an
output when that output is shorted to ground, or another
specified potential, with input conditions applied that, according to the product specification, will establish a logiC
high level at the output.
loz High-Impedance State Output Current: These tests
guarantee that the device will not excessively load a bus
line when the device output is put into the TRI-STATE~
mode.
11K Input Clamp Current: The current flowing out of an input when that input is pulled below ground. This test is used
to guarantee the integrity of the input clamp diode. The input
clamp diode is used to limit the voltage swings on the input
by clamping the negative excursions to a level equal to one
diode drop below ground. This serves to reduce ringing on
an incoming Signal. Pulling the input below ground for an
extended length of time can cause parasitic transistor action
to occur between adjacent tanks on the die which can
cause erroneous data to occur on the outputs of the device.
To prevent this, voltages on the inputs during operation
(other than high speed ringing) should be limited to no more
than O.SV below ground at all times.
10ZH (or ISINK>: The current flowing into an output with input
conditions applied to the output control pin such that the
output is in the high impedance state and input conditions
applied to the other inputs that, according to the product
specification, will establish a logic low level at the output.
10zL
Features
Where: Nl (lOH) = total maximum output high current for all
outputs tied to pull-up resistor
• Alternate Military/Aerospace device (54LS09) is available. Contact a National Semiconductor Sales Office/
Distributor for specifications.
N2 (IIH) = total maximum input high current for all
inputs tied to pull-up resistor
N3 (lid = total maximum input low current for all
inputs tied to pull-up resistor
Connection Diagram
Dual·ln·Llne Package
Vee
14
Al
B4
V4
A4
Bl
B3
II
12
13
A2
VI
A3
V3
V2
GND
10
B2
TL/F/6348-1
Order Number 54LS09DMQB, 54LS09FMQB, DM54LS09J, DM54LS09W, DM74LS09M or DM74LS09N
See NS Package Number E20A, J14A, M14A, N14A or W14S
Function Table
v=
AS
Inputs
H
L
Output
A
B
V
L
L
L
H
H
H
L
L
L
L
H
H
= High logic level
= Low Logic Level
2-15
•
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaran·
teed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Output Voltage
7V
Operating Free Air Temperature Range
DM54LS and 54LS
-55·C to + 125·C
DM74LS
O·Cto +700C
-65·C to + 150·C
Storage Temperature Range
Recommended Operating Conditions
Symbol
DM74LS09
DM54LS09
Parameter
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
V
Vee
Supply Voltage
VIH
High Level Input Voltage
Vil
Low Level Input Voltage
0.7
0.8
VOH
High Level Output Voltage
5.5
5.5
V
IOl
Low Level Output Current
4
8
rnA
TA
Free Air Operating Temperature
70
·c
V
2
2
-55
a
125
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Typ
(Note 1)
Min
Max
Units
VI
Input Clamp Voltage
Vee = Mln,ll = -1B rnA
-1.5
V
'eEX
High Level Output
Current
Vee = Min, Vo = 5.5V
VIH = Min
100
/lA
VOL
Low Level Output
Voltage
Vee = Min, IOl = Max
Vil = Max
DM54
DM74
0.35
0.5
IOl = 4 rnA, Vee = Min
DM74
0.25
0.4
'I
Input Current @Max
Input Voltage
Vee = Max, VI = 7V
0.25
0.4
0.1
V
rnA
IIH
High Level Input Current
Vee = Max, VI = 2.7V
20
/lA
III
Low Level Input Current
Vee = Max, VI = O.4V
-0.36
rnA
leeH
Supply Current With
Outputs High
Vee = Max
2.4
4.8
rnA
leel
Supply Current With
Outputs Low
Vee = Max
4.4
B.B
rnA
Switching Characteristics at Vee =
5V and TA = 25·C (See Section 1 for Test Waveforms and Output Load)
RL = 2kO
Symbol
Parameter
CL = 15pF
Units
CL=50pF
Min
Max
Min
Max
tplH
Propagation Delay Time
Low to High Level Output
5
20
8
45
ns
tpHL
Propagation Delay TIme
High to Low Level Output
4
15
6
27
ns
Note 1: Aillypicals are at Vee = SV. TA = 2S'C.
2·16
J?"A National
~ Semiconductor
54LS 1O/DM54LS 1O/DM7 4LS 10
Triple 3-lnput NAND Gates
General Description
Features
This device contains three independent gates each of which
performs the logic NAND function.
• Alternate Military! Aerospace device (54LS10) is available. Contact a National Semiconductor Sales Office!
Distributor for specifications.
Connection Diagram
Dual-In-Llne Package
Vee
14
AI
CI
11
12
AZ
81
83
C3
VI
13
8Z
A3
V3
VZ
GNU
10
C2
TUF/6349-1
Order Number 54LS10DMQB, 54LS10FMQB, 54LS10LMQB,
DM54LS10J, DM54LS10W, DM74LS10M or DM74LS10N
See NS Package Number E20A, J14A, M14A, N14A or W14B
Function Table
y = ABC
Inputs
Output
Y
A
B
C
X
X
X
L
H
L
X
X
X
H
H
H
H
L
L
H
= High Logic Level
L = Low Logic Level
X = Either Low or High Logic Level
H
2-17
II
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Operating Free Air Temperature Range
DM54LS and 54LS
- 55'C to + 125'C
DM74LS
O'Cto +70'C
Storage Temperature Range
- 65'C to + 150'C
Recommended Operating Conditions
Symbol
DM54LS10
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
10H
High Level Output Current
DM74LS10
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
10l
Low Level Output Current
TA
Free Air Operating Temperature
Units
Min
2
V
V
0.7
0.8
V
-0.4
-0.4
mA
8
mA
70
·C
4
-55
125
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Min
Typ
(Note 1)
DM54
2.5
3.4
DM74
2.7
3.4
Conditions
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vcc = Min,ll = -18 mA
VOH
High Level Output
Voltage
Vee = Min, 10H = Max,
Vil = Max
Low Level Output
Voltage
Vcc = Min,lol = Max,
VIH = Min
DM54
0.25
DM74
0.35
0.5
10l = 4 mA, Vcc = Min
DM74
0.25
0.4
VOL
II
Input Current @ Max
Input Voltage
Vcc = Max, VI = 7V
V
0.4
0.1
V
mA
IIH
High Level Input Current
Vee = Max, VI = 2.7V
20
IJ-A
III
Low Level Input Current
Vcc = Max, VI = 0.4V
-0.36
mA
los
Short Circuit
Output Current
Vcc = Max
(Note 2)
ICCH
Supply Current with
Outputs High
Vee = Max
ICCl
Supply Current with
Outputs Low
Vcc = Max
Switching Characteristics at Vcc =
DM54
-20
-100
DM74
-20
-100
mA
0.6
1.2
mA
1.8
3.3
mA
5V and T A = 25'C (See Section 1 for Test Waveforms and Output Load)
Rl = 2kn
Symbol
Parameter
CL = 50pF
CL = 15pF
Units
Min
Max
Min
Max
tpLH
Propagation Delay Time
Low to High Level Output
3
10
4
15
ns
tpHL
Propagation Delay Time
High to Low Level Output
3
10
4
15
ns
Note 1: All typlcals are at Vee = 5V, Til = 25'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
2-18
~
.....
.....
~National
~ Semiconductor
54LS11/DM54LS11/DM74LS11 Triple a-Input AND Gates
General Description
Features
This device contains three independent gates each of which
performs the logic AND function.
• Alternate military/aerospace device (54LS11) is available. Contact a National Semiconductor Sales Office/
Distributor for specifications.
Connection Diagram
Dual-In-Line Package
Vee
l14
Cl
13
83
C3
VI
11
12
A3
V3
10
....
r_
L-.::::I }-
-
-
r----I'
Al
)-
A2
81
V2
C2
82
P
GND
TUF/6350-1
Order Number 54LS11DMQB, 54LS11FMQB, 54LS11LMQB,
DM54LS11J, DM54LS11W, DM74LS11M or DM74LS11N
See NS Package Number E20A, J14A, M14A, N14A or W14B
Function Table
y= ABC
Inputs
Output
A
B
C
Y
X
X
X
L
L
L
X
H
X
X
H
L
L
L
H
= High Logie Level
L = Low Logic Level
X = Either Low or High Logic Level
H
2-19
H
•
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these/imits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Operating Free Air Temperature Range
DM54LS and 54LS
- 55'C to + 125'C
DM74LS
O'Cto +70"C
Storage Temperature Range
-65'Cto + 150'C
Recommended Operating Conditions
Symbol
DM54LS11
Parameter
Vcc
Supply Voltage
VIH
High Level Input Voltage
DM74LS11
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
2
V
V
Vil
Low Level Input Voltage
0.7
0.8
V
10H
High Level Output Current
-0.4
-0.4
mA
10l
Low Level Output Current
4
8
mA
TA
Free Air Operating Temperature
70
'c
-55
0
125
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
= Min,ll =
VI
Input Clamp Voltage
Vee
VOH
High Level Output
Voltage
Vcc = Min, 10H
VIH = Min
= Max
Low Level Output
Voltage
Vcc = Min, IOl
Vil = Max
= Max
VOL
Input Current @ Max
Input Voltage
Typ
(Note 1)
DM54
2.5
3.4
DM74
2.7
3.4
-18 mA
= 4 mA, Vcc = Min
Vee = Max, VI = 7V
IOl
II
Min
Conditions
Max
Units
-1.5
V
V
DM54
0.25
0.4
DM74
0.35
0.5
DM74
0.25
0.4
0.1
V
mA
IIH
High Level Input Current
Vee
p.A
Low Level input Current
Vcc
-0.36
mA
los
Short Circuit
Output Current
= Max, VI = 2.7V
= Max, VI = 0.4V
Vcc = Max
20
III
DM54
-20
-100
(Note 2)
DM74
-20
-100
mA
ICCH
Supply Current with
Outputs High
Vee
= Max
1.8
3.6
mA
ICCl
Supply Current with
Outputs Low
Vee
= Max
3.3
6.6
mA
Switching Characteristics at Vcc = 5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
Rl = 2kO
Units
Symbol
Parameter
Cl = 1SpF
Cl = SOpF
Min
Max
Min
Max
tplH
Propagation Delay Time
Low to High Level Output
4
13
6
18
ns
tpHl
Propagation Delay Time
High to Low Level Output
3
11
5
18
ns
Note 1: A1llypicals are at Vee = 5V, TA = 25'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
2-20
~National
~ Semiconductor
DM54LS 12/DM7 4LS 12 Triple 3-lnput NAND Gates
with Open-Collector Outputs
General Description
Pull-Up Resistor Equations
This device contains three independent gates each of which
performs the logic NAND function. The open-collector outputs require external pull-up resistors for proper logical operation.
R
Connection Diagram
Vee (Min) - VOH
+ N2 (IIH)
MAX = N, (lOH)
RMIN = Vee (Max) - VOL
IOL - N3 (11Ll
Where: N1 (IOH) = total maximum output high current for all
outputs tied to pull-up resistor
N2 (IIH) = total maximum Input high current for all
Inputs tied to pull-up resistor
N3 (lILl = total maximum Input low current for all
inputs tied to pull-up resistor
Function Table
y= AB
Dual·ln·Llne Package
Vee
1;4
YI
Cl
13
12
C3
11
--
I
A3
Y3
Inputs
10
~
-
V
Al
a3
Output
A
B
C
Y
X
X
L
H
X
L
X
H
L
X
X
H
H
H
H
L
H = High Logic Level
L = Low Logic Level
X = Either Low or High Logic Level
4
al
A2
a2
C2
TL/F/6351-1
Order Number DM54LS12J, DM54LS12W,
DM74LS12M or DM74LS12N
See NS Package Number J14A, M14A, N14A or W14B
•
2·21
!J
N
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The devica should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Output Voltage
7V
Operating Free Air Temperature Range
DM54LS
- 55'C to + 125'C
DM74LS
O'Cto +700C
Storage Temperature Range
- 65'C to + 1500C
Recommended Operating Conditions
Symbol
DM54LS12
Parameter
DM74LS12
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
0.7
0.8
VOH
High Level Output Voltage
5.5
5.5
V
IOL
Low Level Output Current
4
8
mA
TA
Free Air Operating Temperature
70
·c
2
2
-55
125
V
V
0
V
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
VI
Input Clamp Voltage
ICEX
High Level Output
Current
VOL
Low Level Output
Voltage
Conditions
= Min,ll = -18 mA
Vcc = Min, Vo = 5.5
VIL = Max
Vcc = Min,lOL = Max
VIH = Min
Vcc
= 4 mA, Vcc = Min
Vee = Max, VI = 7V
IOL
II
Input Current @ Max
Input Voltage
Typ
(Note 1)
Min
Max
Units
-1.5
V
100
/-LA
DM54
0.25
0.4
DM74
0.35
0.5
DM74
0.25
0.4
0.1
= Max, VI = 2.7V
= Max, VI = O.4V
Vcc = Max
V
mA
IIH
High Level Input Current
Vcc
20
/-LA
IlL
Low Level Input Current
Vcc
-0.36
mA
ICCH
Supply Current with
Outputs High
0.7
1.4
mA
leeL
Supply Current with
Outputs Low
1.8
3.3
mA
Vee
= Max
Switching Characteristics at Vcc = 5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
RL = 2kfi
Symbol
Parameter
CL = 15pF
CL=50pF
Units
Min
Max
Min
Max
tpLH
Propagation Delay Time
Low to High Level Output
6
20
20
45
ns
tpHL
Propagation Delay Time
High to Low Level Output
3
15
4
20
ns
Note 1: All typIcals are at Vee = 5V, TA = 25'C.
2-22
~National
~ Semiconductor
54LS13/DM74LS13
Dual 4-lnput Schmitt Trigger
General Description
This device contains two independent gates each of which
perform the logic NAND function. Each input has hysteresis
which increases the noise immunity and transforms a slowly
changing input signal to a fast changing jitter free output.
Connection Diagram
Dual-In-Llne Package
....:,1+---,'-./
~Vcc
-~
-~
2
NC~
4
rUNC
5
.--r!!!
[:t
TLlF/l0166-1
Order Number 54LS13DMQB, 54LS13FMQB,
54LS13LMQB, DM74LS13M or DM74LS13N
See NS Package Number E20A,
J14A, M14A, N14A or W14B
•
2·23
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maxim'!m ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
54LS
-55'Cto + 125'C
DM74LS
O'Cto +70'C
Storage Temperature Range
-65'Cto + 150'C
Recommended Operating Conditions
Symbol
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
DM74LS13
54LS13
Parameter
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
0.7
0.6
V
2
2
V
10H
High Level Output Current
-0.4
-0.4
mA
10L
Low Level Output Current
4
8
mA
TA
Free Air Operating Temperature
70
'C
-55
125
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
= Min, II = -18 mA
= Mln,loH = Max,
VIL = Max
Vee = Min, 10L = Max,
VIH = Min
10L = 4 mA, Vee = Min
Vee = Max, VI = 10V
VI
Input Clamp Voltage
Vee
VOH
High Level Output
Voltage
Vee
VOL
Low Level Output
Voltage
II
Input Current @ Max
Input Voltage
Min
Conditions
54LS
2.5
DM74
2.7
Typ
(Note 1)
Max
Units
-1.5
V
V
0.4
54LS
DM74
0.5
DM74
0.4
V
0.1
mA
/loA
mA
IIH
High Level Input Current
Vee
Low Level Input Current
Vee
-0.4
los
Short Circuit
Output Current
= Max, VI = 2.7V
= Max, VI = 0.4V
Vee = Max
20
IlL
54LS
-20
-100
(Note 2)
DM74
-20
-100
mA
ICCH
Supply Current with
Outputs High
Vee = Max
VIN = GND
6.0
mA
IceL
Supply Current with
Outputs Low
Vee = Max
VIN = OPEN
7.0
mA
VT+
Positive-Going
Threshold Voltage
Vce
= +5.0V
1.5
2.0
V
VT-
Negative-Going
Threshold Voltage
Vee
= +5.0V
0.6
1.1
V
VT+ - VT-
Hysteresis Voltage
Vce
0.4
V
Input Current at PositiveGoing Threshold
Vee
=
=
+5.0V
IT+
+ 5.0V, VIN
= VT+
-0.14'
mA
IT-
Input Current at NegativeGoing Threshold
Vee
=
+5.0V, VIN
= VT-
-0.18'
'Typical Value
Note 1: All typlcals are at Vrx; = SV. TA = 2S'C.
Note 2: Not more than one output should be shorted at a time. and the duration should not exceed one second.
2-24
mA
Switching Characteristics
Vee =
+ 5.0V. TA = + 25°C (See Section 1 for test waveforms and output load)
RL = 2kO,CL = 15pF
Symbol
Parameter
54LS
Min
DM74
Max
Min
Units
Max
tpLH
Propagation Delay Time
Low to High Level Output
22
25
ns
tpHL
Propagation Delay Time
High to Low Level Output
27
30
ns
PI
2·25
~ r------------------------------------------------------------------------,
..~ ~National
~ Semiconductor
54lS14/DM74lS14 Hex Inverters
with Schmitt Trigger Inputs
General Description
This device contains six independent gates each of which
performs the logic INVERT function. Each input has hysteresis which increases the noise immunity and transforms a
slowly changing input signal to a fast changing, jitter free
output.
Connection Diagram
Dual-In-Llne Package
AI
A6
V6
VI
AZ
AS
VS
A4
V4
TLiF/6353-1
Order Number 54LS14DMQB, 54LS14FMQB,
54LS14LMQB, DM74LS14M or DM74LS14N
See NS Package Number E20A, J14A, M14A, N14A or W14B
Function Table
Y=A
Output
Input
H
A
Y
L
H
H
L
= High Logic Level
L = Low Logic Level
2-26
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
7V
Input Voltage
Operating Free Air Temperature Range
-55'Cto +125'C
54LS
DM74LS
O'Cto +70'C
Storage Temperature Range
-65'Cto +150'C
Recommended Operating Conditions
Symbol
54LS14
Parameter
DM74LS14
Units
Min
Nom
Max
Min
Nom
Max
Vee
Supply Voltage
4.5
5
5.5
4.75
5
5.25
V
VT+
Positive-Going Input
Threshold Voltage (Note 1)
1.5
1.6
2.0
1.4
1.6
1.9
V
VT-
Negative-Going Input
Threshold Voltage (Note 1)
0.6
0.8
1.1
0.5
0.8
1
V
0.4
0.8
0.4
0.8
HYS
Input Hysteresis (Note 1)
10H
High Level Output Current
-0.4
-0.4
rnA
10l
Low Level Output Current
4
8
mA
TA
Free Air Operating Temperature
70
·c
-55
125
0
V
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
VI
Input Clamp Voltage
VOH
High Level Output
Voltage
= Min,ll = -18 rnA
Vee = Min, 10H = Max
Vil = Max
Low Level Output
Voltage
Vee = Min, 10l
VIH = Min
IT+
Input Current at
Positive-Going Threshold
Vee
= Min, 10l = 4 mA
= 5V, VI = VT+
DM74
IT-
Input Current at
Negative-Going Threshold
Vee
= 5V, VI = VT-
DM74
II
Input Current @ Max
Input Voltage
Vee
DM74
Vee
54LS
VOL
Vee
Vee
IIH
High Level Input Current
IlL
Low Level Input Current
los
Short Circuit
Output Current
leeH
Supply Current with
Outputs High
Supply Current with
Outputs Low
Note 1: vee = sv.
Note 2: All typicals are at Vee = SV, TA = 2S'C.
leel
Typ
(Note 2)
= Max
= Max, VI = 7V
= Max, VI = 10.0V
Vee = Max, VI = 2.7V
Vee = Max, VI = 0.4V
Vee = Max
(Note3)
Vee
= Max
Vee
= Max
54LS
2.5
3.4
DM74
2.7
3.4
Units
-1.5
V
V
54LS
0.25
0.4
DM74
0.35
0.5
DM74
0.25
0.4
V
-0.14
mA
-0.18
mA
0.1
mA
20
p.A
-0.4
mA
54LS
-20
-100
DM74
-20
-100
Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one aecend.
2-27
Max
mA
8.6
16
mA
12
21
mA
Switching Characteristics at Vee = 5V and T A = 25°C (See Section 1 for Test Waveforms and Output Load)
RL
Symbol
CL
Parameter
=
=
2k!l
15pF
CL
=
50pF
Units
Min
Max
Min
Max
tpLH
Propagation Delay Time
Lowto'High Level Output
5
22
8
25
ns
tpHL
Propagation Delay Time
High to Low Level Output
5
22
10
33
ns
2-28
~National
~ Semiconductor
54LS15/DM74LS15
Triple 3-lnput AND Gate
with Open-Collector Outputs
General Description
This device contains three independent gates, each of
which perform the logic AND function. The outputs are
open-collector.
Connection Diagram
Dual·ln·Llne Package
TL/F/l0167-1
Order Number 54LS15DMQ8, 54LS15FMQ8,
DM74LS15M or DM74LS15N
See NS Package Number J14A, M14A, N14A or W148
•
2-29
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Input Voltage
7V
Operating Free Air Temperature Range
54LS
-55·C to + 125·C
DM74LS
O·Cto +70"C
Storage Temperature Range
- 65·C to + 150·C
Recommended Operating Conditions atVcc = +5.0V, TA = +25·C
Symbol
54LS15
Parameter
Vcc
Supply Voltage
DM74LS15
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
V
VIH
High Level Input Voltage
Vil
Low Level Input Voltage
2
0.7
2
0.8
VOH
High Level Output Voltage
5.5
5.5
V
IOl
Low Level Output Current
4
8
mA
TA
Free Air Operating Temperature
70
·c
-55
125
V
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
= Min,ll = -18 mA
= Max,
VI
Input Clamp Voltage
Vee
VOL
Low Level Output
Voltage
Vcc = Min, IOl
VIH = Min
II
Input Current @ Max
Input Voltage
Vee
IIH
High Level Input Current
Vcc
III
Low Level Input Current
IOH
High Level
Output Current
ICCH
Supply Current with
Outputs High
IOl
Supply Current with
Outputs Low
Note 1: All typlcals are al Vee = 5V. TA = 25"C.
ICCl
= 4 mA, Vcc = Min
= Max, VI = 10V
= Max, VI = 2.7V
Vcc = Max, VI = O.4V
Vcc = Max, Vo = 5.5V
Vee
VIN
Min
Typ
(Note 1)
Max
Units
-1.5
V
54LS
0.4
DM74
0.5
DM74
0.4
0.1
V
mA
20
p.A
-0.4
mA
100
p.A
= Max, VIN = OPEN
3.6
mA
= GND
6.6
mA
2-30
Switching Characteristics
= +5.0V, TA = +25'C (See Section 1 for test waveforms and output load)
Vee
Symbol
RL = 2k!l
CL = 15pF
Parameter
Units
Max
54LS
DM74
tpLH
Propagation Delay Tima
Low to High Laval Output
24
20
ns
tpHL
Propagation Dalay Tima
High to Low Laval Output
18
14
ns
•
2·31
~
~ ~National
~ Semiconductor
54LS20/DM54LS20/DM74LS20 Dual 4-lnput NAND Gates
General Description
Features
This device contains two independent gates each of which
performs the logic NAND function.
• Alternate Military/Aerospace device (54LS20) is available. Contact a National Semiconductor Sales Office/
Distributor for specifications
Connection Diagram
Dual-In-Une Package
D2
C2
13
AI
111
V2
10
DI
CI
81
A2
82
NIC
12
VI
Order Number 54LS20DMQB, 54LS20FMQB, 54LS20LMQB,
DM54LS20J, DM54LS20W, DM74LS20M or DM74LS20N
See NS Package Number E20A, J14A, M14A, N14A or W14B
Function Table
y = ABCD
Inputs
Output
A
B
C
D
Y
X
X
X
X
X
X
L
L
L
L
H
X
X
X
X
X
X
H
H
H
H
H
H
H
L
= High Logic Level
L = Low logic Level
X = Either Low or High Logic Level
H
2-32
TLiF/6355-1
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Operating Free Air Temperature Range
DM54LS and 54LS
- 55'C to + 125'C
DM74LS
O'Cto +70'C
Storage Temperature Range
-65'Cto + 150'C
Recommended Operating Conditions
Symbol
DM54LS20
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
Vil
Low Level Input Voltage
10H
High Level Output Current
DM74LS20
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
0.7
0.8
V
-0.4
-0.4
mA
8
mA
70
'C
2
10l
Low Level Output Current
TA
Free Air Operating Temperature
Units
Min
V
2
4
-55
125
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Min
Typ
(Note 1)
DM54
2.5
3.4
DM74
2.7
3.4
Conditions
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vee = Min, 11= -18 mA
VOH
High Level Output
Voltage
Vee = Min, 10H = Max,
Vil = Max
Low Level Output
Voltage
Vee = Min, 10l = Max,
VIH = Min
DM54
0.25
0.4
DM74
0.35
0.5
10l = 4 mA, Vee = Min
DM74
0.25
0.4
VOL
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 7V
V
0.1
V
mA
IIH
High Level Input Current
Vee = Max, VI = 2.7V
20
poA
IlL
Low Level Input Current
Vee = Max, VI = O.4V
-0.36
mA
los
Short Circuit
Output Current
Vee = Max
{Note 2)
leeH
Supply Current with
Outputs High
Vee = Max
leel
Supply Current with
Outputs Low
Vee = Max
Switching Characteristics at Vee =
DM54
-20
-100
DM74
-20
-100
mA
0.4
0.8
mA
1.2
2.2
mA
5V and T A = 25'C (See Section 1 for Test Waveforms and Output Load)
Rl = 2kO
Symbol
Parameter
CL = 15pF
Units
CL = 50pF
Min
Max
Min
Max
tpLH
Propagation Delay Time
Low to High Level Output
3
10
4
15
ns
tpHL
Propagation Delay Time
High to Low Level Output
3
10
4
15
ns
Note 1: All typical. are at Vee = 5V, TA = 25'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
2-33
•
_
!J ~ National
r---------------------------------------------------------------------~
C"I
~ Semiconductor
54LS21/DM54LS21/DM74LS21 Dual 4-lnput AND Gates
General Description
Features
This device contains two independent gates each of which
performs the logic AND function.
• Alternate Military/Aerospace device (54LS21) is available. Contact a National Semiconductor Sales Officel
Distributor for specifications.
Connection Diagram
Dual-In-Llne Package
02
C2
11
12
13
A2
82
NrC
V2
10
->-]
81
Al
J:
Cl
VI
01
TL/F/6356-1
Order Number 54LS21DMQB, 54LS21FMQB, 54LS21LMQB,
DM54LS21J, DM54LS21W, DM74LS21M or DM74LS21N
See NS Package Number E20A, J14A, M14A, N14A or W14B
Function Table
Y = ABCD
Output
Inputs
A
B
C
D
Y
X
X
X
L
H
X
X
L
X
H
X
L
X
X
H
L
X
X
X
H
L
L
L
L
H
= High Logic Level
= Low logic Level
X = erther Low or High Logic Level
H
L
2-34
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Input Voltage
7V
Operating Free Air Temperature Range
DM54LS and 54LS
-55'C to + 125'C
DM74LS
O'Cto +70'C
Storage Temperature Range
-65'Cto +150'C
Recommended Operating Conditions
DM54LS21
Parameter
Symbol
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
10H
DM74LS21
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
2
V
V
0.7
0.6
V
High Level Output Current
-0.4
-0.4
mA
10L
Low Level Output Current
4
6
mA
TA
Free Air Operating Temperature
70
'c
-55
125
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Min
Typ
(Note 1)
DM54
2.5
3.4
DM74
2.7
3.4
Conditions
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vee = Min, 11= -16 mA
VOH
High Level Output
Voltage
Vee = Min, 10H = Max,
VIH = Min
Low Level Output
Voltage
Vee = Min, 10L = Max,
VIL = Max
DM54
0.25
0.4
DM74
0.35
0.5
10L = 4 mA, Vee = Min
DM74
0.25
0.4
VOL
II
Input Current @ Max
Input Voltage
Vee = Max. VI = 7V
V
0.1
V
mA
IIH
High Level Input Current
Vee = Max. VI = 2.7V
20
",A
IlL
Low Level Input Current
Vee = Max, VI = O.4V
-0.36
mA
los
Short Circuit
Output Current
Vee = Max
(Note 2)
ICCH
Supply Current with
Outputs High
Vee = Max
ICCL
Supply Current with
Outputs Low
Vee = Max
Switching Characteristics at Vee =
DM54
-20
-100
DM74
-20
-100
mA
1.2
2.4
mA
2.2
4.4
mA
5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
RL = 2kO
Symbol
Parameter
CL = 15pF
Units
CL = 50pF
Min
Max
Min
Max
tpLH
Propagation Delay Time
Low to High Level Output
4
13
6
16
ns
tpHL
Propagation Delay Time
High to Low Level Output
3
11
5
16
ns
Note 1: All typicals are at Vee
= 5V. TA = 25·C.
Note 2: Not more than one output should be shorted at a time. and the duration should not exceed one second.
2-35
~ ~National
~ Semiconductor
54LS22/DM74LS22
Dual 4-lnput NAND Gate
(with Open-Collector Output)
General Description
The 'LS22 contains two independent NAND gates, each
with four data inputs.
Connection Diagram
Dual-In-Llne Package
NC.l
4
5
TLlF/l0188-1
Order Number 54LS22DMQB, 54LS22FMQB,
DM74LS22M or DM74LS22N
See NS Package Number J14A, M14A, N14A or W14B
2-36
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operatiOn.
Operating Free Air Temperature Range
54LS
-55'Cto +125"C
DM74LS
O'Cto +70'C
Storage Temperature Range
-65'Cto + 150'C
Recommended Operating Conditions
Symbol
54LS22
Parameter
VCC
Supply Voltage
VIH
High Level Input Voltage
DM74LS22
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
V
2
V
VIL
Low Level Input Voltage
0.7
0.8
V
VOH
High Level Output Voltage
5.5
5.5
rnA
8
rnA
70
'C
IOL
Low Level Output Current
TA
Free Air Operating Temperature
4
-55
125
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
=
=
VI
Input Clamp Voltage
Vcc
ICEX
High Level
Output Current
Vcc = Min, Vo
VIL = Max
=
5.5V,
VOL
Low Level Output
Voltage
VCC = Min, IOL
VIH = Min
=
Max,
Min, II
-18 rnA
= 4 rnA, Vcc = Min
VCC = Max, VI = 5.5V
IOL
II
Input Current @ Max
Input Voltage
IIH
High Level Input Current
Vee
Low Level Input Current
Vee
=
=
Max, VI
IlL
ICCH
Supply Current
Outputs High
Vcc
=
Max, VIN
=
ICCL
Supply Current
Outputs Low
Vcc
=
Max, VIN
=
Max, VI
Min
=
=
Typ
(Note 1)
Max
Units
-1.5
V
100
p.A
54LS
0.4
DM74
0.5
DM74
0.4
0.1
V
rnA
2.7V
20
p.A
O.4V
-0.4
rnA
GND
0.8
rnA
Open
2.2
rnA
Note 1: All typical. are at Vee = 5V, TA = 25"C.
II
2-37
Switching Characteristics
at Vee = +S,OV. TA = +2SoC (See Section 1 for test waveforms and output load)
Symbol
RL = 2 kO, CL = 1SpF
Parameter
Min
Units
Max
tpLH
Propagation Delay Time
Low to High Level Output
22
ns
tpHL
Propagation Delay Time
High to Low Level Output
24
ns
2-38
~National
~ Semiconductor
54LS26/DM74LS26 Quad 2-lnput NAND Gates
with High Voltage Open-Collector Outputs
General Description
Pull-Up Resistor Equations
This device contains four independent gates each of which
performs the logic NAND function. The open-collector outputs require external pull-up resistors for proper logical operation.
Vo (Min) - VOH
R
MAX = N, (IOH)
R
These gates feature high-voltage output ratings (up to 15V)
for interfacing with 12V systems. Although the outputs are
rated for 15V, the device supply is still rated for 5V.
MIN =
+ N2 (IIH)
Vo (Max) - VOL
IOL - Na (IIU
Where: N, (IOH) = total maximum output high current for
all outputs tied to pull-up resistor
N2 (IIH) = total maximum input high current for all
inputs tied to pull-up resistor
Ns (IIU = total maximum input low current for all
inputs tied to pull-up resistor
Connection Diagram
Dual-In-Llne Package
B4
14
AI
A4
V4
VI
BI
B3
11
12
13
A2
A3
Y3
V2
GND
10
B2
Tl/F/6358-1
Order Number 54LS26DMQB, 54LS26FMQB, DM74LS26M or DM74LS26N
See NS Package Number J14A, M14A, N14A or W14B
Function Table
y= AB
Inputs
Output
B
y
L
L
L
H
H
H
L
H
H
H
H
L
A
H = High Loglo Level
L = Low Logic Level
2-39
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Output Voltage
15V
Operating Free Air Temperature Range
- 55·C to + 125·C
54LS
O·Cto +70·C
DM74LS
- 65·C to + 150·C
Storage Temperature Range
Recommended Operating Conditions
Symbol
54LS26
Parameter
Vcc
Supply Voltage
V,H
High Level Input Voltage
DM74LS26
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
V
2
V
VIL
Low Level Input Voltage
0.7
0.8
VOH
High Level Output Voltage
15
15
V
IOL
Low Level Output Current
4
8
mA
TA
Free Air Operating Temperature
70
·c
-55
125
0
V
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Input Clamp Voltage
Vcc
ICEl<
High Level Output
Current
Vee = Min
VIL = Max
Low Level Output
Voltage
Vee = Min, IOL
V,H = Min
= 15V
Vo = 12V
=
Max
= 4 mA, Vec = Min
Vcc = Max, VI = 5.5V
'I
Input Current @ Max
Input Voltage
IIH
High Level Input Current
Vcc
= Max, VI = 2.7V
IlL
Low Level Input Current
Vce
=
Max, VI
ICCH
Supply Current with
Outputs High
Vcc
=
Max
ICCL
Supply Current with
Outputs Low
Vce
=
Max
=
O.4V
Switching Characteristics at Vcc = 5V and TA =
Max
Units
-1.5
V
1000
Vo
IOL
/LA
50
54LS
0.4
DM74
0.35
0.5
DM74
0.25
0.4
V
0.1
mA
20
/LA
54LS
-0.40
DM74
-0.36
mA
0.8
1.6
mA
2.4
4.4
mA
25·C (See Section 1 for Test Waveforms and Output Load)
RL
Symbol
Typ
(Note 1)
= Min, II = -18 mA
VI
VOL
Min
Parameter
=
2 kO, CL
= 15 pF
Max
Units
54LS
DM74
tpLH
Propagation Delay Time
Low to High Level Output
27
32
ns
tpHL
Propagation Delay Time
High to Low Level Output
18
28
ns
Note 1: All typicals are at Vee
= 5V, TA = 25"e.
2-40
~National
~ Semiconductor
54LS27/DM54LS27/DM74LS27
Triple 3-lnput NOR Gates
General Description
Features
This device contains three independent gates each of which
performs the logic NOR function.
• Alternate Militaryl Aerospace device (54LS27) is available. Contact a National Semiconductor Sales Officel
Distributor for specifications.
Connection Diagram
Dual-In-Llne Package
Vee
14
AI
VI
CI
12
13
BI
B3
C3
A3
V3
11
A2
V2
B2
TUF/6359-1
Order Number 54LS27DMQB, 54LS27FMQB, 54LS27LMQB,
DM54LS27J, DM54LS27W, DM74LS27M or DM74LS27N
See NS Package Number E20A, J14A, M14A, N14A or W14B
Function Table
Y=A+B
Inputs
H
L
Output
A
B
Y
L
L
H
H
L
H
L
H
H
L
L
L
= High logic Level
= Low Logic Level
2-41
•
_..
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings'
beyond which the safety of the device
teed. The device should not be operflted.~Ii i/,' , ,
parametric values defined in the "Electric
table are not guaranteed at the absolute.'n':,",;" .
The "Recommended Operating ConditiO!
the conditions for actual device opera!i:;'I/.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
- 55·C to + 125·C
DM54lS and 54lS
O·Cto +70·C
DM74lS
- 65·C to + 150·C
Storage Temperature Range
Recommended Operating Conditions
Symbol
DM71\LS27
DM54LS27
Parameter
Min
Nom
Max
Min
Nom
4.5
5
5.5
4.75
5
".
~-
Vee
Supply Voltage
VIH
High level Input Voltage
VIL
low level Input Voltage
10H
High level Output Current
...
0.7
.-
-0.4
10L
low level Output Current
TA
Free Air Operating Temperature
4
-55
-
.--
...
0
125
..
Parameter
Conditions
Input Clamp Voltage
Vcc = Min, II = -18 rnA
VOH
High level Output
Voltage
Vcc = Min, 10H = Max,
VIL = Max
low level Output
Voltage
Vee = Min, 10l = Max,
VIH = Min
DM54
0.25
DM74
0.35
10l = 4 rnA, Vcc = Min
DM74
0.25
Input Current @ Max
Input Voltage
II
IJ,::'
c. '
"
-
..
,
DM54
2.5
3.4
DM74
2.7
3.4
il'
",'
Typ
(Note 1)...
Min
VI
VOL
\'
.-
~..
Electrical Characteristics over recommended operating free air temperature range (unless
Symbol
5.?'.>
2
2
..
.1
..
·-
· ..
0.1
t).i
.. -. -"
IIH
High level Input Current
Vee = Max, VI = 2.7V
?D
III
low level Input Current
Vcc = Max, VI = 0.4V
- -O.:.'fj
loS
Short Circuit
Output Current
Vee = Max
(Note 2)
ICCH
Supply Current with
Outputs High
Vee = Max
leel
Supply Current with
Outpulslow
Vee = Max
-20
DM74
-20
---- .- -
..
..
1\;')
1(':'
..
2
.--."
Switching Characteristics at Vee =
~
3.4
5V and TA = 25·C (See Section 1 for Test Waveforms and
Parameter
...
CL = 15pF
CL = 50pF
Max
Min
3
13
5
3
10
4
Min
Ma
-~-.
tpLH
Propagation Delay Time
low to High level Output
tpHl
Propagation Delay Time
High to low level Output
;,; ;
-
RL=2kO
Symbol
\:
0,:'
OJ.
Vcc = Max, VI = 7V
DM54
10
·-
15
--
Note 1: All typlcals are at Vee = SV, TA = 2S'C.
Nota 2: Not more than ona output should be shorted at a time, and the duration should not exceed one seccnd.
2-42
.'
f
I
(,1:1:
i\
'1
!
~National
~ Semiconductor
54LS28/DM74LS28
Quad 2-lnput NOR Buffer
General Description
The 'LS28 contains four independent gates each of which
perform the logic NOR function.
Connection Diagram
Dual·ln·Llne Package
GND 7
TL/F/10169-1
Order Number 54LS28DMOB, 54LS28FMOB, 54LS28LMOB,
DM74LS28M or DM74LS28N
See NS Package Number E20A, J14A, M14A, N14A or W14B
2-43
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
Note: The "Absolute MaJdmum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maJdmum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
7V
Input Voltage
7V
Operating Free Air Temperature Range
54LS
-55'C to + 125'C
DM74LS
O'Cto +70'C
Storage Temperature Range
- 65'C to + 150'C
Recommended Operating Conditions
Symbol
Vcc
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
DM74LS28
54LS28
Parameter
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
V
2
2
0.7
0.8
V
10H
High Level Output Current
-1.2
-1.2
mA
10L
Low Level Output Current
12
24
mA
TA
Free Air Operating Temperature
70
'C
-55
125
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
VI
Input Clamp Voltage
VOH
High Level Output
Voltage
= Min,ll = -18 mA
Vee = Min, 10H = Max,
VIL = Max
Low Level Output
Voltage
Vcc = Min, 10L
VIH = Min
II
Input Current @ Max
Input Voltage
Vee
IIH
High Level Input Current
IlL
Low Level Input Current
= Max, VI = 2.7V
Vee = Max, VI = 0.4V
los
Short Circuit
Output Current
Vee = Max
(Note 2)
ICCH
Supply Current with
Outputs High
Vee
= Max
ICCL
Supply Current with
Outputs Low
Vee
= Max
VOL
Vee
10L
Nol. 1: All typlcals are at Vee
Min
Conditions
= Max,
= 12 mA, Vee = Min
= Max, VI = 10V
54LS
2.5
DM74
2.7
Max
Units
-1.5
V
V
54LS
0.4
DM74
0.5
DM74
0.4
0.1
Vee
mA
/LA
-0.4
mA
54LS
-30
-130
-30
-130
= 5V, TA = 25'C.
V
20
DM74
Nol. 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
2-44
Typ
(Note 1)
mA
3.6
mA
13.8
mA
Switching Characteristics
at Vee = + 5.0V, TA = + 25°C (See Section 1 for test waveforms and output load)
Symbol
RL = 2kO
CL = 15pF
Parameter
Min
Units
Max
tpLH
Propagation Delay Time
Low to High Level Output
20
ns
tpHL
Propagation Delay Time
High to Low Level Output
20
ns'
2-45
c
~------------------------------------------------------------------------,
!I ~ National
~ Semiconductor
54LS30/DM54LS30/DM74LS30
a-Input NAND Gate
General Description
Features
This device contains a single gate which performs the logic
NAND function.
• Alternate Military/Aerospace device (54LS30) is available. Contact a National Semiconductor Sales Office/
Distributor for specifications.
Connection Diagram
Dual-In-Line Package
YrCC
14
H
re
y
N
12
10
11
P
A
GNO
TL/F/6360-1
Order Number 54LS30DMQB, 54LS30FMQB,
54LS30LMQB, DM54LS30J, DM54LS530W, DM74LS30M or DM74LS30N
See NS Package Number E20A, J14A, M14A, N14A or W14B
Function Table
Y = ABCDEFGH
Inputs
Output
AthruH
Y
All Inputs H
One or More
Input L
L
H
H = High logic Level
L = Lew Logic Level
2-46
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
DM54LS and 54LS
-55'Cto + 125'C
DM74LS
O'Cto +70'C
Storage Temperature Range
-65'C to + 150'C
Recommended Operating Conditions
Symbol
DM54LS30
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
Vil
Low Level Input Voltage
IOH
High Level Output Current
DM74LS30
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
IOl
Low Level Output Current
TA
Free Air Operating Temperature
Units
Min
2
V
V
0.7
0.8
V
-0.4
-0.4
mA
8
mA
70
'C
4
-55
125
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Min
Typ
(Note 1)
DM54
2.5
3.4
DM74
2.7
3.4
Conditions
Units
-1.5
V
VI
Input Clamp Voltage
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
Vil = Max
Low Level Output
Voltage
Vee = Min, 10l = Max
VIH = Min
DM54
0.25
0.4
DM74
0.35
0.5
IOl = 4 mA, Vee = Min
DM74
0.25
0.4
VOL
Vee = Min, 11= -18 mA
Max
V
V
II
Input Current @ Max
Input Voltage
Vec = Max, VI = 7V
IIH
High Level Input Current
Vec = Max, VI = 2.7V
20
/LA
III
Low Level Input Current
Vec = Max, VI = 0.4V
-0.4
mA
los
Short Circuit
Output Current
Vec = Max
(Note 2)
ICCH
Supply Current with
Outputs High
Vcc = Max
leel
Supply Current with
Outputs Low
Vcc = Max
Switching Characteristics at Vcc =
0.1
DM54
-20
-100
DM74
-20
-100
mA
mA
0.35
0.5
mA
0.6
1.1
mA
5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
RL = 2kO
Symbol
Parameter
CL = 15pF
Units
CL = 50pF
Min
Max
Min
Max
tplH
Propagation Delay Time
Low to High Level Output
4
12
5
18
ns
tpHl
Propagation Delay Time
High to Low Level Output
4
15
5
20
ns
Note 1: All typlcals are at Vee = 5V, TA = 25'C.
Note 2: Not more than one output should be shorted at a time. and the duration should not exceed one second.
2-47
•
~
!I
J?!I National
~ Semiconductor
54LS32/DM54LS32/DM74LS32
Quad 2-lnput OR Gates
General Description
Features
This device contains four independent gates each of which
performs the logic OR function.
• Alternate Military/Aerospace device (54LS32) is available. Contact a National Semiconductor Sales Office/
Distributor for specifications.
Connection Diagram
Dual-In-Llne Package
Vee
B4
A4
Y4
B3
A3
A1
B1
Y1
A2
B2
va
Y3
TL/F/83B1-1
Order Number 54LS32DMQB, 54LS32FMQB, 54LS32LMQB,
DM54LS32J, DM54LS32W, DM74LS32M or DM74LS32N
See NS Package Number E20A, J14A, M14A, N14A or W14B
Function Table
Y=A+B
Inputs
H
L
Output
A
B
Y
L
L
H
H
L
H
L
H
L
H
H
H
= High logic Level
= Lew Leglc Level
2-48
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the Natlonai Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
7V
Input Voltage
7V
Operating Free Air Temperature Range
DM54LS and 54LS
-55'Cto +125'C
DM74LS
O'Cto +70'C
Storage Temperature Range
-65'Cto + 150'C
Recommended Operating Conditions
Symbol
DM54LS32
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
10H
High Level Output Current
DM74LS32
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
10L
Low Level Output Current
TA
Free Air Operating Temperature
Units
Min
2
0.7
0.8
V
-0.4
-0.4
rnA
8
rnA
70
'C
4
-55
V
V
125
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Min
Typ
(Note 1)
DM54
2.5
3.4
DM74
2.7
3.4
Conditions
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vee = Min, II = -18mA
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
VIH = Min
Low Level Output
Voltage
Vee = Min, 10L = Max
VIL = Max
DM54
0.25
0.4
DM74
0.35
0.5
10L = 4 mA, Vee = Min
DM74
0.25
0.4
VOL
II
input Current @ Max
input Voltage
V
Vee = Max, VI = 7V
0.1
V
mA
IIH
High Level Input Current
Vee = Max, VI = 2.7V
20
pA
IlL
Low Level Input Current
Vee = Max, VI = O.4V
-0.36
mA
los
Short Circuit
Output Current
Vee = Max
(Note 2)
leeH
Supply Current with
Outputs High
Vee = Max
ieeL
Supply Current with
Outputs Low
Vee = Max
Switching Characteristics at Vee =
DM54
-20
-100
DM74
-20
-100
mA
3.1
6.2
rnA
4.9
9.8
rnA
5V and T A = 25'C (See Section 1 for Test Waveforms and Output Load)
RL = 2 kO
Symbol
Parameter
CL = 15pF
Units
CL = 50pF
Min
Max
Min
Max
tpLH
Propagation Delay Time
Low to High Level Output
3
11
4
15
ns
tpHL
Propagation Delay Time
High to Low Level Output
3
11
4
15
ns
Note 1: All typlcals are at Vcc = 5V, TA = 25'C.
Note 2: N~t more than one output should be shorted at a time, and the duration should not exceed one second.
2-49
•
~r----------------------------------------------------------------'
~ J?A National
~ Semiconductor
54LS33/DM74LS33
Quad 2-lnput NOR Buffer with Open-Collector Outputs
General Description
This device contains four independent gates each of which
perform the logic NOR function. Outputs are open-collector.
Connection Diagram
Dual-In-Llne Package
14 V
13 cc
2
3
4
GND
5
6
7
TL/F/l0170-1
Order Number 54LS33DMQB, 54LS33FMQB, DM74LS33M or DM74LS33N
See NS Package Number J14A, M14A, N14A or W14B
2-50
-
;{3u'f~lLlm
Raiings
(Note)
specified devices are required,
u t·lational Semiconductor Sales
io, iJlmiiability and specifications.
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
';G
7V
7V
7V
.;. I, ",lperature
Range
- 55·C to + 125·C
O·Cto +70·C
-65·Cto + 150·C
f'ldfige
.c;d
O~ei'aiing
Conditions
54LS33
Parameter
, Voltage
GlJel Input Voltage
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
V
2
.evel Output Voltage
-55
V
0.7
O.B
5.5
5.5
V
12
24
mA
70
·C
v\,_, L(Nel Output Current
ir Operating Temperature
Units
Min
'. ~:. (' I .H\fellnput Voltage
I
DM74LS33
125
0
V
::[. ~ ~lu'a!lG~el(isiicS over recommended operating free air temperature range (unless otherwise noted)
'~ll "hlsler
Conditions
Min
_.
lar,lp Voltage
Ii::'
:
:iqh La vel Output
i
:t:lrnllt
Vee
vol Output
. J.....
----'.. ;:I/,C llirent
'I
=
Min, I,
=
-1B mA
Vee = Min, Vo
V,L = Max
=
5.5V,
Vee = Min, IOL
V,H = Min
=
Max,
= 12 mA, Vee = Min
Vee = Max, V, = 7V
IOL
@
Max
Typ
(Note 1)
'. ::1 .. '
Units
-1.5
V
100
".A
54LS
0.4
DM74
0.5
DM74
0.4
V
0.1
!'I V \ ;Iiage
U)
Max
mA
....
','d Input Current
Vee
2.7V
20
".A
,,"'Input Current
Vee
0.4V
-0.4
mA
3.6
mA
13.B
mA
= Max, V, =
= Max, V, =
Vee = Max
V,N = GND
Vee = Max
V,N = Open
--------
Current with
; High
Cllrrent with
·,L.ow
----
Vee = 5V. TA = 25'C.
~:r.;i(ac~ei'isiicS at Vee = 5V and TA = 25·C (See Section 1 for Test Waveforms and Output Load)
RL = 2kO
CL = 15pF
Parameter
r
I
I .-
Min
Units
Max
Propagation Delay Time
Low to High Level Output
22
ns
Propagation Delay Time
High to Low Level Output
22
ns
2-51
§ ~National
~ Semiconductor
54LS37/DM74LS37
Quad 2-lnput NAND Buffers
General Description
This device contains four independent buffer gates each of
which performs the logic NAND function.
Connection Diagram
Dual·ln·Une Package
Vee
14
AI
V4
A4
B4
12
13
BI
11
VI
A2
B3
A3
V3
yz
GNU
10
B2
TL/F/6362·1
Order Number 54LS37DMOB, 54LS37FMOB, 54LS37LMOB,
DM74LS37M or DM74LS37N
See NS Package Number E20A, J14A, M14A, N14A or W14B
Function Table
Y=AB
Inputs
H
L
Output
A
B
Y
L
L
H
H
L
H
L
H
H
H
H
L
= High Logic Level
= Lew Leglc Level
2-52
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
54LS
-55'Cto + 125'C
DM74LS
O'Cto +70'C
Storage Temperature Range
- 65'C to + 150'C
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Recommended Operating Conditions
Symbol
54LS37
Parameter
Vcc
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
IOH
High Level Output Current
DM74LS37
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
IOL
Low Level Output Current
TA
Free Air Operating Temperature
Units
Min
V
2
V
0.7
0.8
V
-1.2
-1.2
rnA
24
rnA
70
'C
12
-55
125
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
= Min,ll = -18 rnA
= Max
VI
Input Clamp Voltage
Vee
VOH
High Level Output
Voltage
Vee = Min, 10H
VIL = Max
Low Level Output
Voltage
Vee = Min, 10L
VIH = Min
VOL
= Max
Typ
(Note 1)
Min
54LS
2.5
DM74LS
2.7
Input Current @ Max
Input Voltage
IIH
High Level Input Current
IlL
Low Level Input
-1.5
V
V
54LS
0.4
DM74LS
= 12 rnA, Vee = Min
Vcc = Max, VI = 10V (54LS)
VI = 7V (DM74LS)
Vee = Max, VI = 2.7V
54LS
Vee = Max, VI = 0.4V
Current
Units
3.4
IOL
II
Max
0.35
0.5
0.25
0.4
V
0.1
rnA
20
/J- A
-0.40
rnA
-0.36
DM74LS
Short Circuit
Output Current
Vee = Max
(Note 2)
ICCH
Supply Current with
Outputs High
Vee
= Max
0.9
2
rnA
leeL
Supply Current with
Outputs Low
Vee
= Max
6
12
rnA
los
54LS
-30
-130
DM74LS
-20
-100
rnA
Switching Characteristics at Vee = 5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
54LS
Symbol
Parameter
CL
DM74LS
CL = 150pF,
RL = 6670
= 50pF
Min
Units
Max
Min
Max
tpLH
Propagation Delay Time
Low to High Level Output
20
4
18
ns
tpHL
Propagation Delay Time
High to Low Level Output
20
4
21
ns
Note 1: All typicals are at Vex = SV, TA = 2S'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
2-53
II
~
~ ~National
~ Semiconductor
54LS38/DM54LS38/DM74LS38
Quad 2-lnput NAND Buffers
with Open-Collector Outputs
General Description
Pull-Up Resistor Equations
This device contains four independent gates, each of which
performs the logic NAND function. The open-collector outputs require external pull-up resistors for proper logical operation.
R
Vee (Min) - VOH
MAX = N, (IOH) + N2 (lIH)
R
Vee (Max) - VOL
MIN = IOL - Na (lIU
Features
Where: N, (IOH) = total maximum output high current for all
outputs tied to pull-up resistor
N2 (IIH) = total maximum input high current for all
inputs tied to pull-up resistor
N3 (lIU = total maximum input low current for all
inputs tied to pull-up resistor
• Alternate Military/Aerospace device (54LS38) is available. Contact a National Semiconductor Sales Office/
Distributor for specifications.
Connection Diagram
Dual·ln·Line Package
Vee
84
AI
BI
A4
V4
VI .
A2
B3
A3
V3
B2
V2
GNO
Tl/F/6363-1
Order Number 54LS38DMQB, 54LS38FMQB, 54LS38LMQB,
DM54LS38J, DM74LS38M or DM74LS38N
See NS Package Number E20A, J14A, M14A, N14A or W14B
Function Table
V= AB
Inputs
H
L
Output
A
B
V
L
L
H
H
L
H
L
H
H
H
H
L
= High Logic Level
= Low logiC Level
2·54
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
OHlce/Dlstrlbutors for availability and speCifications.
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Supply Voltage
7V
Input Voltage
7V
Output Voltage
7V
Operating Free Air Temperature Range
-55'C to + 125'C
DM54LS and 54LS
DM74LS
O'Cto +70'C
Storage Temperature Range
-65'C to + 150'C
Recommended Operating Conditions
Symbol
DM54LS38
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
VOH
High Level Output Voltage
DM74LS38
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
·0.7
0.8
V
5.5
5.5
V
24
mA
70
·c
2
2
IOL
Low Level Output Current
TA
Free Air Operating Temperature
Units
Min
V
12
-55
125
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
VI
Input Clamp Voltage
leEX
High Level Output
Current
VOL
Low Level Output
Voltage
Conditions
= Min,ll = -18 mA
Vee = Min, Vo = 5.5V
VIL = Max
Vcc = Min, IOl = Max
VIH = Min
Input Current @ Max
Input Voltage
IIH
High Level Input Current
III
Low Level Input Current
ICCH
Supply Current with
Outputs High
ICCl
Supply Current with
Outputs Low
Typ
(Note 1)
Vee
= 12 mA, Vee = Min
Vcc = Max, VI = 7V
IOl
II
Min
Max
Units
-1.5
V
250
p.A
DM54
0.25
0.4
DM74
0.35
0.5
DM74
0.25
0.4
0.1
= Max, VI = 2.7V
= Max, VI = 0.4V
Vee = Max
V
mA
Vee
20
p.A
Vee
-0.36
mA
0.9
2
mA
6
12
mA
Vee
= Max
Switching Characteristics at Vee = 5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
Rl = 6670
Symbol
Parameter
Units
Cl = 45pF
CL = 150pF
Max
Min
tplH
Propagation Delay Time
Low to High Level Output
Propagation Delay Time
High to Low Level Output
Note 1: All typical. are at Vee = 5V, TA = 25'C.
tpHl
2·55
Min
Max
22
48
ns
22
29
ns
•
~ ~National
~ Semiconductor
54LS40/DM74LS40
Dual4-lnput NAND Buffer
General Description
This device contains two independent gates each of which
perform the logic NAND function.
Connection Diagrams
Dual·ln·Une Package
...! I - -\..../
..JI--
13
NC..A
cc
12
.J_
....l! ---,
...L 1 (
GND..l
tliv
J
ll.NC
10
t"fL L
LL
TLlF/10171-1
Order Number 54LS40DMQB, 54LS40FMQB, 54LS40LMQB, DM74LS40M or DM74LS40N
See NS Package Number E20A, J14A, M14A, N14A or W14B
2·56
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
- 55·C to + 125·C
54LS
O·Cto +70·C
DM74LS
Storage Temperature Range
-65·Cto +150·C
Recommended Operating Conditions
Symbol
54LS40
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
Vil
Low Level Input Voltage
10H
High Level Output Current
DM74LS40
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
10l
Low Level Output Current
TA
Free Air Operating Temperature
Units
Min
V
2
V
0.7
0.8
V
-1.2
-1.2
mA
24
mA
70
·C
12
-55
125
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
=
=
VI
Input Clamp Voltage
Vee
VOH
High Level Output
Voltage
Vee = Min, 10H
Vil = Max
=
Low Level Output
Voltage
Vee = Min, 10l
VIH = Min
=
VOL
Min, II
-18rnA
Max,
Max,
= 4 rnA, Vee = Min
Vee = Max, VI = 10V
10l
II
Input Current @ Max
Input Voltage
IIH
High Level Input Current
Vee
III
Low Level Input Current
Vee
los
Short Circuit
Output Current
Vee = Max
(Note 2)
ICCH
Supply Current with
Outputs High
Vee
=
Max, VIN
=
GND
ICCl
Supply Current with
Outputs Low
Vee
=
Max, VIN
=
OPEN
=
=
Max, VI
Max, VI
Min
=
=
54LS
2.5
DM74
2.7
Typ
(Note 1)
Max
Units
-1.5
V
V
54LS
0.4
DM74
0.5
DM74
0.4
0.1
V
rnA
2.7V
20
p.A
O.4V
-1.6
mA
54LS
-30
-130
DM74
-30
-130
Note 1: All typicals are at Vee = SV, TA = 2s'e.
Note 2: Note more than one output should be shorted at a time, and the duration should not exceed one second.
2-57
rnA
1.0
rnA
6.0
rnA
•
I
Switching Characteristics
Vcr; = +S.OV. TA = +2SoC (See Section 1 for test v
Symbol
Parameter
tpLH
Propagation Delay Time
Low to High Level OUlpl)
tpHL
Propagation Delay Time
High to Low Level OUtPlI
_NatiOnal
Semiconductor
54LS42/DM54LS42/DM74LS42 BCD/Decimal Decoders
General Description
Features
These BCD-to-decimal decoders consist of eight inverters
and ten, four-input NAND gates. The inverters are connected in pairs to make BCD input data available for decoding
by the NAND gates. Full decoding of input logic ensures
that all outputs remain off for all invalid (10-15) input conditions.
• Diode clamped inputs
• Also for applications as 4-line-to-16-line decoders; 3line-to-B-line decoders
• All outputs are high for invalid input conditions
• Alternate Military/Aerospace device (54LS42) is available. Contact a National Semiconductor Sales Office/
Distributor for specifications.
Connection Diagram
Function Table
Dual-In-Line Package
8
INPUTS
Vee
i
A
15
18
14
OUTPUTS
,
e
0
13
9
p-
r
I
0
,
0
1
2
3
4
9
10
2
I
3
3
4
5
5
6
7
,8
9
71 8
6
5
4
2
6
BCD Inputs
I
N
GND
OUTPUTS
V
TL/F/6365-1
A
L
I
D
Order Number 54LS42DMQB, 54LS42FMQB,
DM54LS42J, DM54LS42W, DM74LS42M or DM74LS42N
See NS Package Number J16A, M16A, N16E or W16A
DeCimal Outputs
0
1
2
3
4
5
6
7
8
9
L L L L
L L H H
L H L H
L H H H
H L L H
H
L
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L H L H H H
L H H L H H
L H H H H H
H L L L H H
H L L H H H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
L
H L H H H H
H H H H H H
L L H H H H
L H H H H H
H L H H H H
H H H H H H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
D C
7
8
11
12
No.
,
L
L
L
L
L
H
H
H
H
H
H
L
L
H
H
H
H
B
A
H ~ High Level
L
~
Low Level
Logic Diagram
(I)
INPUT A
(IS)
INPUTS (14)
A
~OUTPUTO
~
~OUTPUTI
ii
~OUTPUT3
(2)
~0UTPUT2
4>8
(13)
~
OUTPUT 4
C
~OUTPUT5
4>c
~OUTPUT6
INPUTC
(9)
(12)
INPUT D
ii
~
~D
OUTPUT 7
(10)
~
OUTPUTS
~,OUTPUT 9
TlIF/S365-2
2·59
Absolute Maximum Ratings (Note)
Note: The "Absolute MSJdmum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute mSJdmum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
- 55·C to + 125·C
DM54LS and 54LS
DM74LS
O·Cto +70"C
- 65·C to + 150·C
Storage Temperature Range
Recommended Operating Conditions
Symbol
DM54LS42
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
DM74LS42
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
2
V
V
0.7
0.8
V
IOH
High Level Output Current
-0.4
-0.4
mA
IOL
Low Level Output Current
4
8
mA
TA
Free Air Operating Temperature
70
·c
Electrical Characteristics
Symbol
-55
125
over recommended operating free air temperature range (unless otherwise noted)
Conditions
Parameter
VI
Input Clamp Voltage
VOH
High Level Output
Voltage
= Min, II = -18 mA
Vee = Min, IOH = Max
VIL = Max, VIH = Min
Low Level Output
Voltage
Vee = Min, IOL = Max
VIL = Max, VIH = Min
VOL
IOL
= 4 mA, Vee = Min
= Max, VI = 7V
Input Current @ Max
Input Voltage
Vee
IIH
High Level Input Current
Vee
Low Level Input Current
los
Short Circuit
Output Current
Min
Typ
(Note 1)
Vee
II
IlL
0
DM54
2.5
3.4
DM74
2.7
3.4
Max
Units
-1.5
V
V
DM54
0.25
DM74
0.35
0.4
0.5
DM74
0.25
0.4
0.1
mA
20
p.A
-0.4
mA
= Max, VI = 2.7V
Vee = Max, VI = 0.4V
Vee = Max
DM54
-20
-100
(Note 2)
DM74
-20
-100
Supply Current
Vee = Max (Note 3)
lee
Note 1: All typicals are at Vo::, = 5V, T" = 25'e.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: 10::, Is measured with all outputs open and all Inputs grounded.
2-60
7
V
13
mA
mA
II
Switching Characteristics
at Vee = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
RL
=
2kO
Parameter
From (Input)
To (Output)
tpHL
Propagation Delay Time
High to Low Level Output
A, B, C, or D (2 Levels
of Logic) to Output
25
30
ns
tpHL
Propagation Delay Time
High to Low Level Output
A, B, C, or D (3 Levels
of Logie) to Output
30
35
ns
tpLH
Propagation Delay Time
Low to High Level Output
A, B, C, or D (2 Levels
of Logic) to Output
25
30
ns
tpLH
Propagation Delay Time
Low to High Level Output
A, B, C, or D (3 Levels
of Logie) to Output
30
35
ns
Symbol
CL
Min
2·61
=
15pF
Max
CL
Min
=
50pF
Units
Max
~National
~ Semiconductor
54LS47/DM74LS47
BCD to 7-Segment Decoder/Driver
General Description
Features
The 'LS47 accepts four lines of BCD (8421) Input data, generates their complements Internally and decodes the data
with seven ANDIOR gates having open-collector outputs to
drive indicator segments directly. Each segment output is
guaranteed to sink 24 mA in the ON (LOW) state and withstand 15V in the OFF (HIGH) state with a maximum leakage
current of 250 /LA. Auxiliary inputs provided blanking, lamp
test and cascadable zero-suppression functions. Also see
the 'LS47 data sheet.
•
•
•
•
Open-collector outputs
Drive indicator segments directly
Cascadable zero-suppression capability
'lamp test input
Connection Diagram
Dual-In-Llne Package
AO- 1
Al- 2
'-./
16
:-Vcc
15 ~f
14 ~g
LT- 3
13 ~e:
BI/RBO- 4
Riii- 5
12
Hi
11~c
A2- 6
A:5- 7
10 ~a
GND- 8
91-;;
TUF/9817-1
Order Number 54LS47DMQB, 54LS47FMQB,
DM74LS47M or DM74LS47N
See NS Package Number J16A, M16A, N16E or W16A
Pin Names
AO-A3
RBI
LT
BIIRBO
a-g
Description
BCD Inputs
Ripple Blanking Input (Active LOW)
Lamp Test Input (Active LOW)
Blanking Input (Active LOW) or
Ripple Blanking Output (Active LOW)
'Segment Outputs (Active LOW)
'OC-Open Collector
2-62
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
54LS
-55'Cto + 125'C
DM74LS
O'Cto +70'C
Storage Temperature Range
- 65'C to + 150'C
Recommended Operating Conditions
Symbol
54LS47
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
DM74SL47
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
V
V
2
VIL
Low Level Input Voltage
0.7
0.8
V
10H
High Level Output Current
@ 15V = VOH'
-50
-250
p.A
10L
Low Level Output Current
12
24
mA
TA
Free Air Operating Temperature
70
'C
-55
125
0
'OFF stale al a-g.
Electrical Characteristics
Over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Min
Conditions
Typ
(Note 1)
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vee = Min, II = -18 rnA
VOH
High Level
Output Voltage
Vee = Min, 10H = Max,
VIL = Max
Low Level
Output Voltage
Vee = Min, 10L = Max,
VIH = Min
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 10V
IIH
High Level Input Current
Vee = Max, VI = 2.7V
20
/LA
IlL
Low Level Input Current
Vee = Max, VI = O.4V
-0.4
rnA
los
Short Circuit
Output Current
Vee = Max
(Note 2), los at BIIRBO
Supply Current
Vee = Max
VOL
10L = 4 rnA, Vee = Min
Icc
54LS
2.4
DM74
2.7
V
3.4
54LS
0.4
DM74
0.35
0.5
DM74
0.25
0.4
100
54LS
-0.3
-2.0
DM74
-0.3
-2.0
13
Note 1: All typlcals are at Vee = SV, TA = 2S'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
2-63
V
p.A
mA
mA
~
Switching Characteristics at Vee =
+5.0V, TA = +25°C
RL = 6650
Symbol
Parameter
CL = 15 pF
Conditions
Min
Units
Max
Propagation Delay
Antoa-g
100
100
ns
Propagation Delay
tpLH
RBitoa-g*
tpHL
'[1' = HIGH, AO-A3 = LOW
100
100
ns
tpLH
tpHL
Functional Description
The 'LS47 decodes the Input data in the pattern Indicated in
the Truth Table and the segment identification illustration. If
the input data is decimal zero, a LOW signal applied to the
RBI blanks the display and causes a multidiglt display. For
example, by grounding the RBI of the highest order decoder
and connecting its BI/RBO to RBI of the next lowest order
decoder, etc., leading zeros will be suppressed. Similarly, by
grounding RBI of the lowest order decoder and connecting
Its BIIRBO to RBi of the next highest order decoder, etc.,
trailing zeros will be suppressed. Leading and trailing zeros
can be suppressed simultaneously by using external gates,
i.e.: by driving RBI of a intermediate decoder from an OR
gate whose Inputs are BIIABO of the next highest and lowest order decoders. Bi7RBO also serves as an unconditional blanking input. The internal NAND gate that generates
the RBO signal has a resistive pull-up, as opposed to a
totem pole, and thus BIIABO can be forced LOW by external means, using wired-collector logic. A LOW Signal thus
applied to BIIABO turns off all segment outputs. This blanking feature can be used to control display intensity by varying the duty cycle of the blanking Signal. A LOW Signal applied to LT turns on all segment outputs, provided that
BIIRBO is not forced LOW.
2-64
Logic Diagram
RIPPLE-BLEAKING
INPUT
INPUT
BLANKING INPUT OR
RIPPLE-BLANKING
OUTPUT
OUTPUT
TLlF/9817-3
Numerical Designations-Resultant Displays
10
11
12
13
14
15
TL/F/9817-4
•
2-65
Logic Symbol
liiIi!
AO AI A2 A3 LT RBI
a b c d e f
BI/
g RBO
X~~~y~~y
TUF/9817-2
Vee = Pin 16
GND = PinS
Truth Table
Decimal
or
Function
Outputs
Inputs
Note
LT
RBI
A3
A2
A1
AO
BIIRBO
a
Ii
c
Ii
Ii
f
-
H
H
H
H
H
X
X
X
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
H
H
H
H
H
L
H
L
L
L
L
L
L
L
L
H
L
L
H
L
L
L
H
L
H
L
H
H
H
H
H
L
L
H
H
H
H
H
X
X
X
X
X
L
L
L
L
H
H
H
H
H
L
L
L
H
H
L
L
H
L
H
L
H
H
H
H
H
H
L
H
L
L
L
H
H
L
L
L
L
L
L
L
H
L
L
H
L
H
H
L
H
L
L
L
L
H
L
L
L
L
H
L
H
H
H
H
H
X
X
X
X
X
H
H
H
H
H
L
L
L
H
H
L
H
H
L
L
H
L
H
L
H
H
H
H
H
H
L
H
H
H
L
L
H
H
L
H
L
H
L
H
H
H
L
L
H
L
H
L
H
H
H
L
H
H
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
Bi
x
X
X
RBi
H
L
L
X
L
X
L
X
L
X
L
H
X
L
X
H
H
L
L
H
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
L
H
H
H
L
L
H
H
H
L
L
H
H
H
L
L
H
H
H
L
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
LT
x
x
x
x
9
1
1
2
3
4
Note 1: Bl7li!ro is wire-AND logic serving as blanking Input (iii) andlor ripple-blanking output (ABO). The blanking out (ill) must be open or held at a HIGH level
when output functions 0 through 15 are desired, and ripple-blanking Input (RBi) must be open or at a HIGH level If blanking or a decimal 0 Is not desired. X = input
may be HIGH or LOW.
Note 2: When a LOW levalls applied to the blanking Input (forced condition) all segment outputs go to a HIGH level regardless of the state of any other input
condition.
Note 3: When ripple-blanking input (i'iBi) and inputs AO, AI, A2 and A3 are LOW level, with the lamp test input at HIGH level, all segment outputs go to a HIGH
leval and the ripple-blanking output (ABO) goes to a LOW level (response condition).
Note 4: When the blanking Input/ripple-blanking output (Bl7li!ro) is open or held at a HIGH level, and a LOW level Is applied to lamp test Input, all segment outputs
go to a LOW level.
2-66
driver transistors. Auxiliary inputs provide lamp test, blanking and cascadable zero-suppression functions.
, I .,
I' he 'LS48 decodes the input data in the pattern indicated in
[ile Truth Table and the segment identification illustration.
16
Vee
15
f
14
9
13
a
12
b
11
10
9
TL/F/l0172-1
DM74LS48M, or DM74LS48N
',iii, M16A, N16E or W16A
,/:~~ClB,
•
;':/
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
54LS
-55'C to + 125'C
DM74LS
O"Cto +70'C
Storage Temperature Range
-65'Cto + 150"C
Recommended Operating Conditions
Symbol
54LS48
Parameter
DM74LS48
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
0.7
0.8
2
V
2
V
V
10H
High Level Output Current
-50
-50
p.A
10L
Low Level Output Current
2.0
6.0
mA
TA
Free Air Operating Temperature
70
'c
-55
125
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 1)
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vee = Min, 11= -18 mA
VOH
High Level Output
Voltage
Vee Min, 10H = Max,
VIL = Max
10FF
Output High Current
Segment Outputs
Vee = Min, Vo = 0.85V
VOL
Low Level Output
Voltage
Vee = Min, 10L = Max,
VIH = Min
54LS
0.4
DM74
0.5
10L = 2.0 mA, Vee = Min
DM74
0.4
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 10V
54LS
2.4
DM74
2.4
V
-1.3
mA
V
0.1
mA
IIH
High Level Input Current
Vee = Max, VI = 2.7V
20
p.A
IlL
Low Level Input Current
Vee = Max, VI = O.4V
-0.4
mA
los
Short Circuit
Output Current
Vee = Max, Vo = OV
at BI/RBO (Note 2)
54LS
-0.3
-2
DM74
-0.3
-2
Supply Current
Vee = Max, VIN = 4.5V
leeH
Note 1: All Iypicals are at Vee = SV, TA = 2S'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Switching Characteristics at Vee =
Symbol
CL = 15pF
Min
tpLH
tpHL
Note: IT = HIGH, Ao-Aa
=
38
mA
5V and T A = 25'C (See Section 1 for Test Waveforms and Output Load)
Parameter
tpLH
tpHL
mA
Units
Max
Propagation Delay Time
Antoa-g
100
100
ns
Propagation Delay Time
RBI to a-f
100
100
ns
HIGH.
2-68
Numerical Designations-Resultant Displays
101 112131l11S16111BI91c 1.:Jlul:l~ I
0
I
2
3
4
5
6
7
8
9
10
II
12
13
14
IS
I
TLIFll0172-4
Truth Table
Decimal
Or
Function
Inputs
Outputs
LT
RBI
A3
A2
AI
Ao
BI/RBO
a
b
c
d
e
f
g
0 (Note 1)
1 (Note 1)
2
3
H
H
H
H
H
X
X
X
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
L
H
H
H
L
H
L
H
L
L
L
L
L
H
H
4
5
6
7
8
H
H
H
H
H
X
X
X
X
X
L
L
L
L
H
H
H
H
H
L
L
L
H
H
L
L
H
L
H
L
H
H
H
H
H
L
H
L
H
H
H
L
L
H
H
H
H
H
H
H
L
H
H
L
H
L
L
H
L
H
H
H
H
L
H
H
H
H
L
H
9
10
11
12
13
H
H
H
H
H
X
X
X
X
X
H
H
H
H
H
L
L
L
H
H
L
H
H
L
L
H
L
H
L
H
H
H
H
H
H
H
L
L
L
H
H
L
L
H
L
H
L
H
L
L
L
H
H
L
H
L
H
L
L
L
H
L
L
H
H
H
H
H
H
H
14
15
H
H
X
H
L
X
X
X
H
H
H
H
H
H
X
L
L
H
H
L
L
L
H
H
H
H
H
L
L
L
L
L
L
L
Bi (Note 2)
X
X
X
L
L
L
L
L
L
L
L
RBI (Note3)
L
L
L
L
L
L
L
L
L
L
L
L
LT (Note 4)
X
X
X
X
X
H
H
H
H
H
H
H
H
Note 1: Eii7RBO Is wired-AND logic serving as blanking input (ei) and/or ripple-blanking output (ABO)- The blanking out (Iii) must be open or held at a HIGH level
n
when output functions 0 through 15 are desired. and ripple-blanking input (Alii) must be open or ata HIGH level blanking of a decimal 0 is not desired_ X = input
may be HIGH or LOW_
Note 2: When a LOW level Is applied to the blanking input (forced condition) all segment outputs go to a LOW level. regardless of the state of any other Input
condition_
Note 3: When ripple-blanking Input (RBI) and Inputs Ao. AI. A2. and A3 are at LOW level. with the lamp test Input at HIGH level. all segment outputs go to a LOW
level and the ripple-blanking output (ABO) goes to a LOW level (response conditlon)_
Note 4: When the blanking Input/ripple-blanking output (Bi/RBO) is open or held at a HIGH level. and a LOW level is applied to lamp test input. all segment outputs
go to a HIGH level.
Logic Symbol
liiI~b
AO AI A2 A3 IT RBI
a b c d e f
I~ I~ III It ! I~ I~ !
Vee = Pin 16
GND = PinS
2-69
FII
I
BI/
9 RBO
TLiF/l0172-2
~
Logic Diagram
RIPPLE-BLANKING
INPIIT
INPUT
BLANKING INPIIT OR
RIPPLE-BLANKING
OIlTPUT
OIlTPUT
TUF/l0172-3
2-70
~National
~ Semiconductor
54LS49 BCD to 7-Segment Decoder
General Description
The 54LS49 translates four lines of BCD (8421) input data
into the 7-segment numeral code as shown in the Function
Table. It has open-collector outputs and is logically the 14pin verson of the' 48, without the lamp test and ripple blanking features. Also see the 'LS249 data sheet.
Connection Diagram
Logic Symbol
Dual·ln·Llne Package
\.J
A2- 2
141-Vcc
13 - f
iii- 3
12 -9
AI- 1
A3- 4
11-&
AO- 5
10 -b
e- 6
9 -c
GI'ID- 7
8 -d
iii i b
AO
AI
A2
& bed
A3
e
BI
f
9
TL/F/l0204-2
TUF110204-1
Vee
Order Number 54LS49DMQB or 54LS49FMQB
See NS Package Number J14A or W14B
= Pin 14
GND = Pin 7
Pin Names
Description
AO-A3
Bi
BCD Inputs
Blanking Input (Active LOW)
Segment Outputs (Active HIGH)
a-g
Numerical Designations-Resultant Displays
I -I -I I I I- I- -I I-I I-I
I I I
I I
I I I
I I
I -I
I-I
I_I
0
1
2
3
4
5
6
7
8
2·71
9
I
10
11
tJ
12
I
-
13
I
I
15
"TL/F110204-3
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required.
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
- 55·C to + 125·C
54LS
Storage Temperature Range
- 65·C to + 150·C
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at theselimiis. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Recommended Operating Conditions
Symbol
54LS49
Parameter
Vee
Supply Voltage
V,H
High Level Input Voltage
Units
Min
Nom
Max
4.5
5
5.5
V
2
V
V,L
Low Level Input Voltage
0.7
V
IOH
High Level Output Current
250
p..A
IOL
Low Level Output Current
4
mA
TA
Free Air Operating Temperature
125
·c
-55
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Conditions
Parameter
V,
Input Clamp Voltage
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
I,
Input Current @ Max
Input Voltage
I'H
High Level Input Current
I,L
Low Level Input Current
Icc
Supply Current
Min
= Min,l, = -18 mA
Vee = Min, IOH = Max,
V,L = Max, V,H = Min
Vee = Min, IOL = Max,
V,H = Min, V,L = Max
Vee = Max, V, = 10.0V
Typ
(Note 1)
Vee
Max
Units
-1.5
V
2.5
V
= Max, V, = 2.7V
Vee = Max, V, = O.4V
Vee = Max
Vee
0.4
V
0.1
mA
20
p..A
-0.4
mA
15
mA
Note 1: All typical. are at Vr;;c = SV, TA = 2S'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Switching Characteristics Vee = + 5.0V, TA = + 25·C (See Section 1 for waveforms and output load)
54LS
Symbol
Parameter
CL
Min
= 15pF
Units
Max
tpLH
tpHL
Propagation Delay; RL
An to a-g
= 2 kO
100
100
ns
tpLH
tpHL
Propagation Delay; RL
= 6 kO
Bi to a-g
100
100
ns
2-72
ren
Function Table
~
co
Decimal
Inputs
Outputs
or
Function
A3
A2
A1
AO
Bi
a
b
c
d
e
0
1
2
3
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
L
H
H
H
L
H
L
H
L
L
L
L
L
H
H
4
5
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
H
H
H
H
H
L
H
L
H
H
L
L
H
H
H
H
H
L
H
H
L
L
L
H
L
H
H
H
L
H
H
H
L
10
11
H
H
H
H
L
L
L
L
L
L
H
H
L
H
L
H
H
H
H
H
H
H
L
L
H
H
L
L
H
H
L
H
H
L
H
H
H
L
H
L
H
H
L
L
H
H
H
H
12
13
14
15
H
H
H
H
H
H
H
H
L
L
H
H
L
H
L
H
BI
X
X
X
X
H
H
H
H
L
L
H
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
H
L
L
L
L
H
L
L
H
H
H
L
L
H
H
H
L
L
6
7
8
9
Note
9
2
Note 1: The blanklng Input must be open or held at a HIGH level when output functions 0 through 15 are desired.
Nole 2: When a LOW level Is applied to the blanklng Input all segment outputs go to a LOW level regardless of the state of any other input condition. X
may be HIGH or LOW.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= Input
Logic Diagram
BI
A3
A2
AI
AO
a
TLlF/I0204-4
2-73
_.---------------------------------------------------------------------,
!i ~ National
~ Semiconductor
54LS51/DM74LS51 Dual 2-Wide 2-lnput,
2-Wide 3-lnput AND-OR-INVERT Gates
General Description
This device contains two independent combinations of
gates each of which performs the logic ANO-OR-INVERT
function. Each package contains one 2-wide 2-input and
one 2-wide 3-input AND-DR-INVERT gates.
Connection Diagram
Dual·ln·Llne Package
vee
CI
BI
FI
EI
01
YI
AI
A2
B2
C2
DZ
YZ
GND
Order Number 54LS51DMQB, 54LS51FMQB,
54LS51LMQB, DM74LS51M or DM74LS51N
See NS Package Number E20A, J14A, M14A, N14A or W14B
Function Table
Y1 = (A 1)(B1)(C1)
+ (D1)(E1)(F1)
Output
Inputs
A1
B1
C1
D1
E1
F1
Y1
H
H
H
X
X
X
X
X
X
H
H
H
L
L
Other Combinations
Y2 = «A2) (B2)
H
+ (C2) (D2»
Output
Inputs
A2
B2
C2
D2
Y2
H
H
X
X
X
X
H
H
L
L
Other combinations
H
= High Logic Level
L
=
Low Logic Level
X = Either Low or High logic Level
2-74
H
TL/F/6369-1
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
54LS
-55"eto + 125"e
DM74LS
O"eto +70"e
Storage Temperature Range
-65"eto +150"e
Recommended Operating Conditions
Symbol
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
10H
High Level Output Current
10L
Low Level Output Current
TA
54LS51
Parameter
DM74LS51
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
Free Air Operating Temperature
Units
Min
V
2
-55
V
0.7
0.8
V
-0.4
-0.4
mA
4
8
mA
70
"C
125
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
VI
Input Clamp Voltage
VOH
High Level Output
Voltage
Low Level Output
Voltage
VOL
Conditions
Min
Vee = Min, 11= -18 mA
Vee = Min, 10H = Max,
VIL = Max
54LS
2.5
DM74
2.7
Vee = Min, 10L = Max,
VIH = Min
54LS
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 10V (54LS)
IIH
High Level Input Current
Low Level Input Current
-1.5
V
V
3.4
0.35
0.5
0.25
0.4
V
mA
Vee = Max, VI = 2.7V
20
".A
Vee = Max, VI = O.4V
54LS
-0.40
DM74
-0.36
Vee = Max
(Note 2)
ICCH
Supply Current with
Outputs High
Vee = Max
ICCL
Supply Current with
Outputs Low
Vcc = Max
Note 1: All typlcals are at Vee
Units
0.1
Short Circuit
Output Current
los
Max
0.4
DM74
10L = 4 mA, Vcc = Min
IlL
Typ
(Note 1)
54LS
-20
-100
DM74
-20
-100
= 5V, TA = 25"C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
2-75
mA
mA
0.8
1.6
mA
1.4
2.8
mA
fI
_
!I
r-----------------------------------------------------------------------------~
Switching Characteristics at Vee = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
54LS51
DM74LS51
CL = 15pF,
RL = 2kO
CL = 50pF,
RL=2kO
Min
Units
Max
Min
Max
tpLH
Propagation Delay Time
Low to High Level Output
20
4
18
ns
tpHL
Propagation Delay Time
High to Low Level Output
20
3
15
ne
2-76
~National
~ Semiconductor
54LS54/DM74LS54
4-WIDE, 2-lnput AND-OR-INVERT Gate
General Description
This device contains a combination of four, two input AND
gates whose outputs are connected to a four input NOR
Gate.
Connection Diagram
Dual·ln·Llne Package
14 V
13
..---t.::::..
cc
12
GND
TL/F/10173-1
Order Number 54LS54DMQB, 54LS54FMQB, DM74LS54M or DM74LS54N
See NS Package Number J14A, M14A, N14A or W14B
fI
2·77
Absolute Maximum Ratings
(Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
54LS
DM74LS
- 55'C to + 125'C
O'Cto +70'C
Storage Temperature Range
-55'Cto + 150'C
Recommended Operating Conditions
Symbol
54LS54
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
Vil
Low Level Input Voltage
DM74LS54
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
0.7
0.8
V
2
2
V
10H
High Level Output Voltage
-0.4
-0.4
mA
10l
Low Level Output Current
4
8
mA
TA
Free Air Operating Temperature
70
'C
-55
125
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
54LS
2.5
DM74LS
2.7
VI
Input Clamp Voltage
VOH
High Level Output
Voltage
= Min,ll = -18 mA
Vcc = Min, 10H = Max,
Vil = Max
Low Level Output
Voltage
Vee = Min, 10l
VIH = Min
VOL
Vee
= Max,
= 4 mA, Vee = Min
Vee = Max, VI = 10V
10L
II
Input Current @ Max
Input Voltage
IIH
High Level Input Current
III
Low Level Input Current
los
Short Circuit
Output Current
Typ
(Note 1)
Max
Units
-1.5
V
V
54LS
0.4
DM74LS
0.5
DM74LS
0.4
V
0.1
mA
20
p.A
-0.4
mA
= Max, VI = 2.7V
Vee = Max, VI = 0.4V
Vee = Max
54LS
-20
-100
(Note 2)
DM74LS
-20
-100
Vcc
mA
ICCH
Supply Current with
Outputs High
Vee = Max
VIN = GND
1.6
mA
ICCl
Supply Current with
Outputs Low
Vcc = Max
VIN = Open
2.0
mA
Switching Characteristics at Vee = 5V and TA =
Symbol
25'C (See Section 1 for Test Waveforms and Output Load)
Cl
Parameter
= 15pF,Rl = 2kO
Min
Units
Max
tpLH
Propagation Delay Time
Low to High Level Output
15
ns
tpHL
Propagation Delay Time
High to Low Level Output
15
ns
Note 1: All Iypleals are at Vee = 5V, TA = 25"C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
2-78
~National
~ Semiconductor
54LS55/DM74LS55
2-Wide, 4-lnput AOI Gate
General Description
This device contains a combination of AND-DR-INVERT
functions. The internal gates are configured as two,
four-input AND gates with their outputs connected to a
two-input NOR gate.
Connection Diagram
Dual-In-Llne Package
1
\.J
2
3
4
NC.2.
NC..!
GNo2
~v
13 CC
12
II
q;n-
11
~
~NC
8
TL/F/10174-1
Order Number 54LS55DMQB, 54LS55FMQB,
DM74LS55M or DM74LS55N
See NS Package Number J14A, M14A, N14A or W14B
•
2-79
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Input Voltage
7V
Operating Free Air Temperature Range
-55·Cto +125·C
54LS
DM74LS
O"Cto +70"C
-65·Cto + 150·C
Storage Temperature Range
Recommended Operating Conditions
Symbol
54LS55
Parameter
Vcc
Supply Voltage
VIH
High Level Input Voltage
Vil
Low Level Input Voltage
10H
High Level Output Current
10l
Low Level Output Current
TA
Free Air Operating Temperature
DM74LS55
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
2
2
V
0.7
0.8
V
-0.4
-0.4
mA
8
mA
70
·C
4
-55
125
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
VI
Input Clamp Voltage
Vcc = Min, II = -18 mA
VOH
High Level Output Voltage
Vcc = Min, 10H = Max,
Vil = Max
Low Level Output Voltage
VOL
,
Typ
(Note 1)
Min
54LS
2.5
DM74
2.7
Max
Units
-1.5
V
V
Vee = Min, 10l = Max,
VIH = Min
54LS
0.4
DM74
0.5
10l = 4 mA, Vcc = Min
DM74
0.4
II
Input Current @ Max
Input Voltage
Vcc = Max, VI = 10V
V
0.1
mA
IIH
High Level Input Current
Vcc = Max, VI = 2.7V
20
".A
III
Low Level Input Current
Vcc = Max, VI = O.4V
-0.4
mA
los
Short Circuit
Output Current
Vcc = Max
(Note 2)
ICCH
Supply Current with Outputs High
Vcc = Max, VIN = GND
0.8
mA
ICCl
Supply Current with Outputs Low
Vcc = Max, VIN = Open
1.3
mA
54LS
-20
-100
DM74
-20
-100
mA
Note 1: All typlcals are at Vee = 5V, TA = 25'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Switching Characteristics
Vcc = +5.0V, TA = + 25'C (See Section 1 for Test Waveforms and Output Load)
Symbol
CL = 15 pF, RL = 2 kO
Parameter
Min
tplH
tpHl
Propagation Delay Time
15
15
2-80
Units
Max
ns
~National
~ Semiconductor
DM54LS73A/DM74LS73A Dual Negative-Edge-Triggered
Master-Slave J-K Flip-Flops with Clear
and Complementary Outputs
General Description
This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and
K data is processed by the flip-flops on the falling edge of
the clock pulse. The clock triggering occurs at a voltage
level and is not directly related to the transition time of the
negative going edge of the clock pulse. The data on the J
and K inputs is allowed to change while the clock is high or
low without affecting the outputs as long as setup and hold
times are not violated. A low logic level on the clear input
will reset the outputs regardless of the levels of the other
inputs.
Connection Diagram
Dual-In-line Package
J1
CLK 1
CLR 1
01
GND
K1
VCC
K2
02
CLR 2
J2
TL/F/6372-1
Order Number DM54lS73AJ, DM54LS73AW, DM74lS73AM or DM74lS73AN
See NS Package Number J14A, M14A, N14A or W14B
Function Table
Inputs
Outputs
ClR
ClK
J
K
L
H
H
H
H
H
X
.j,
.j,
.j,
.j,
X
L
H
L
H
X
X
L
L
H
H
X
H
Q
Q
L
H
00
00
H
L
L
H
Toggle
00
00
H = High Logic Level
L = Low logic Level
x
= EHher Low or High logic level
J. = Negative going edge of pulse.
00 = The output logic level before the indicated input conditions were established.
Toggle = Each output changes to the complement of Its previous level on
each failing edge of the clock pulse.
2-81
•
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
Input Voltage
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
7V
7V
Operating Free Air Temperature Range
DM54LS
- 55·C to + 125·C
DM74LS
O·Cto +700C
Storage Temperature Range
- 65·C to + 150·C
Recommended Operating Conditions
Symbol
DM54LS73A
Parameter
VCC
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
IOH
High Level Output Current
DM74LS73A
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
V
V
2
0.7
0.8
V
-0.4
-0.4
mA
IOL
Low Level Output Current
8
mA
fCLK
Clock Frequency (Note 2)
0
30
0
30
MHz
fCLK
Clock Frequency (Note 3)
0
25
0
25
MHz
tw
Pulse Width
(Note 2)
tw
Pulse Width
(Note 3)
4
Clock High
20
20
Preset Low
25
25
Clear Low
25
25
Clock High
25
25
Preset Low
30
30
Clear Low
30
30
ns
ns
tsu
Setup Time (Notes 1 and 2)
20J,
20J,
ns
tsu
Setup Time (Notes 1 and 3)
25J,
25J,
ns
ns
tH
Hold Time (Notes 1 and 2)
oJ,
oJ,
lH
Hold Time (Notes 1 and 3)
5J,
5J,
TA
Free Air Operating Temperature
-55
125
Note 1: The symbol (-!-) Indicates the failing edge of the clock pulse Is used for reference.
Note 2: CL = 15 pF, RL = 2 kn, TA = 25'C and Vee = 5V.
Note 3: CL = 50 pF, RL = 2 kn, TA = 25'C and Vee = 5V.
2-82
0
ns
70
·C
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
=
=
Min
Typ
(Note 1)
Max
Units
-1.5
V
V,
Input Clamp Voltage
Vee
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
V'L = Max, V'H = Min
DM54
2.5
3.4
DM74
2.7
3.4
Low Level Output
Voltage
Vee = Min, 10L = Max
V'L = Max, V'H = Min
DM54
0.25
0.4
DM74
0.35
0.5
DM74
0.25
0.4
Input Current @ Max
Input Voltage
= 4 mA, Vee =
Vee = Max
V, = 7V
High Level Input
Current
Vee = Max
V, = 2.7V
VOL
Min, I,
-18 mA
10L
I,
I'H
I,L
los
lee
Low Level Input
Current
Vee = Max
V, = O.4V
Short Circuit
Output Current
Vee = Max
(Note 2)
Supply Current
Vee
=
Parameter
J, K
0.1
Clear
0.3
Clock
0.4
J, K
20
Clear
60
Clock
BO
J, K
-0.4
Clear
-0.8
Clock
-O.B
DM54
-20
-100
DM74
-20
-100
4
Max (Note 3)
Switching Characteristics at Vee =
Symbol
Min
V
5V and TA
=
From (Input)
To (Output)
6
V
mA
p.A
mA
mA
mA
25'C (See Section 1 for Test Waveforms and Output Load)
RL
CL
Min
=
15pF
Max
=
2kO
CL
Min
=
50pF
Units
Max
fMAX
Maximum Clock
Frequency
tpHl
Propagation Delay Time
High to Low Level Output
Clear
toO
20
28
ns
tplH
Propagation Delay Time
Low to High Level Output
Clear
toO
20
24
ns
tplH
Propagation Delay Time
Low to High Level Output
Clock to
OorO
20
24
ns
tpHl
Propagation Delay Time
High to Low Level Output
Clock to
OorO
20
28
ns
25
30
MHz
Note 1: All typical. are at Vcc - SV, TA - 25'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second. For devices, with feedback from the outputs, where
shorting the outputs to ground may cause the outputs to change logic state, an equivalent test may be performed where Vo - 2.2SV and 2.12SV for DMS4 and
DM74 series, respectively, with the minimum and maximum limits reduced by one half from their stated values. This is very useful when using automatic test
equipment
Note 3: With all outputs open, Icc is measured with the Q and Q outputs high in turn. At the lime of measurement, the clock is grounded.
2-83
•
~
!j
~ National
~ Semiconductor
54LS7 4/DM54LS74A/DM7 4LS74A
Dual Positive-Edge-Triggered D Flip-Flops
with Preset, Clear and Complementary Outputs
General Description
violated. A low logic level on the preset or clear inputs will
set or reset the outputs regardless of the logic levels of the
other inputs.
This device contains two independent positive-edge-triggered D flip-flops with complementary outputs. The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse. The triggering occurs at a
voltage level and is not directly related to the transition time
of the rising edge of the clock. The data on the D input may
be changed while the clock is low or high without affecting
the outputs as long as the data setup and hold times are not
Features
• Alternate military/aerospace device (54LS74) is available. Contact a National Semiconductor Sales Office/
Distributor for specifications.
Connection Diagram
Dual-In-Llne Package
Vee
ClH2
ot
02
ClK 1
ClK2
PH2
PH 1
01
02
TL/F/6373-1
Order Number 54LS74DMQB, 54LS74FMQB, 54LS74LMQB,
DM54LS74AJ, DM54LS74AW, DM74LS74AM or DM74LS74AN
See NS Package Number E20A, J14A, M14A, N14A or W14B
Function Table
Inputs
Outputs
PR
CLR
CLK
D
Q
L
H
L
L
L
L
L
H
H"
H
H
H
H
H
H
X
X
X
H
H
H
X
X
X
t
t
L
X
L
H"
H
L
00
Q
L
H
00
H = High Logic Level
X = Either Low or High Logic Level
L = Low Logic Level
t = PosHlve-golng TransHion
• = This conflguratlon Is nonstable; that Is, Hwill not persist when either the preset
and/or clear Inputs return to their inactive (high) level.
00 = The output logic level of a before the indicated input conditions were established.
2-84
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "E/ectrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Input Voltage
7V
Operating Free Air Temperature Range
DM54LS and 54LS
-55'Cto +125'C
DM74LS
O'Cto +70'C
Storage Temperature Range
-65'Cto +150'C
Recommended Operating Conditions
Symbol
Vee
Supply Voltage
VIH
High Level Input Voltage
DM74LS74A
DM54LS74A
Parameter
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
V
V
2
Vil
Low Level Input Voltage
0.7
0.8
V
IOH
High Level Output Current
-0.4
-0.4
mA
IOl
Low Level Output Current
4
8
mA
felK
Clock Frequency (Note 2)
0
25
0
25
MHz
felK
Clock Frequency (Note 3)
0
20
0
20
MHz
tw
Pulse Width
(Note 2)
Clock High
18
18
Preset Low
15
15
tw
Pulse Width
(Note 3)
Clear Low
15
15
Clock High
25
25
Preset Low
20
20
Clear Low
20
20
ns
ns
tsu
Setup Time (Notes 1 and 2)
20t
20t
ns
tsu
Setup Time (Notes 1 and 3)
25t
25t
ns
tH
Hold Time (Note 1 and 4)
ot
ot
TA
Free Air Operating Temperature
-55
125
0
ns
70
'C
Note 1: The symbol (i) indicates the rising edge of the clock pulse is used for reference.
Note 2: CL = lS pF, RL = 2 kll, TA = 2S'C, and Vee = SV.
Note 3: CL = SO pF, RL = 2 kll, TA = 2S'C, and Vee = SV.
Note 4: TA = 2S'C and Vee = SV.
•
2-85
I
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 1)
= Mln,ll = -18 mA
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vee
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
VIL = Max, VIH = Min
DM54
2.5
3.4
DM74
2.7
3.4
Low Level Output
Voltage
Vee = Min, 10L = Max
VIL = Max, VIH = Min
DM54
0.25
0.4
DM74
0.35
0.5
DM74
0.25
0.4
Input Current @Max
Input Voltage
= 4 mA, Vee = Min
Vee = Max
VI = 7V
VOL
10L
II
IIH
High Level Input
Current
Vee = Max
VI = 2.7V
Low Level Input
Current
Vee = Max
VI = 0.4V
Clock
0.1
Preset
0.2
Clear
0.2
Data
20
Clock
20
Clear
40
Short Circuit
Output Current
Vee = Max
(Note 2)
mA
/LA
40
Data
-0.4
Clock
-0.4
Preset
-0.8
mA
-0.8
Clear
lOS
V
0.1
Data
Preset
IlL
V
DM54
-20
-100
DM74
-20
-100
mA
Supply Current
4
8
mA
Vee = Max (Note 3)
typlcals are at Vee = SV. TA = 2S'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second. For devices, with feedback from the outputs, where
shorting the outputs to ground may cause the outputs to change logic state an equivalent test may be performad where Vo = 2.25V and 2.t25V for DM54 and
DM74 series, respectively, with the minimum and maximum limits reduced by one half from their stated values. This Is very useful when using automatic tast
equipment
Note 3: With ail outputs open, Icc Is measured with CLOCK grounded after selting the Q and a outputs high in tum.
lee
Note 1: All
Switching Characteristics at Vee = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
From (Input)
To (Output)
RL
CL
Min
= 15pF
Max
= 2kO
CL
Min
= 50pF
Units
Max
fMAX
Maximum Clock Frequency
tpLH
Propagation Delay Time
Low to High Level Output
Clock to
QorO
20
25
35
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clock to
QorO
30
35
ns
tpLH
Propagation Delay Time
Low to High Level Output
Preset
toQ
25
35
ns
tpHL
Propagation Delay Time
High to Low Level Output
Preset
toO
30
35
ns
tpLH
Propagation Delay Time
Low to High Level Output
Clear
toO
25
35
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clear
toQ
30
35
ns
25
2-86
MHz
~National
~ Semiconductor
DM54LS75/DM74LS75 Quad Latches
General Description
These latches are ideally suited for use as temporary storage for binary information between processing units and input/output or indicator units. Information present at a data
(D) input is transferred to the
output when the enable is
high, and the output will follow the data input as long as
the enable remains high. When the enable goes low,
the information (that was present at the data input at the
time the transition occured) is retained at the output until
the enable is permitted to go high.
These latches feature complementary
and 0 outputs
from a 4-bit latch, and are available in 16-pin packages.
Connection Diagram
Function Table (Each Latch)
a
a
a
a
Dual-In-Une Package
01
16
02
15
ENf~LE
02
GNO
11
12
14
Inputs
03
03
10
04
9
Enable
Q
Q
L
H
H
L
H
H
L
L
ao
00
H
X
H
Outputs
D
= High Level, L = Low Level, X = Don't Care
= The Level of a Before Ihe High-Ie-Low Transition of ENABLE
00
2
01
01
3
02
4
ENABLE
6
5
03
VCC
3-4
7
04
TLlF/6374-1
Order Number DM54LS75J, DM54LS75W,
DM74LS75M or DM74LS75N
See NS Package Number J16A, M16A, N16A or W16A
Logic Diagram (Each Latch)
~,.~.
~,~.
fII
LATCH
ENABLE
TL/F/6374-2
2-87
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaran·
teed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
- 55·C to + 125·C
DM54LS
DM74LS
O·Cto +700C
Storage Temperature Range
-65:C to + 150·C
Recommended Operating Conditions
Symbol
DM54LS75
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
Vil
Low Level Input Voltage
10H
High Level Output Current
DM74LS75
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
2
V
V
0.7
0.8
V
-0.4
-0.4
mA
B
mA
10l
Low Level Output Current
tw
Enable Pulse Width (Note 4)
20
4
20
ns
Isu
Setup Time (Note 4)
20
20
ns
tH
Hold Time (Note 4)
0
0
TA
Free Air Operating Temperature
-55
125
ns
70
0
·C
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
= Min, II =
Min
Typ
(Note 1)
Max
-1.5 .
VI
Input Clamp Voltage
Vee
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
VIL = Max, VIH = Min
DM54
2.5
3.5
DM74
2.7
3.5
Low Level Output
Voltage
Vee = Min, 10L = Max
Vil = Max, VIH = Min
DM54
0.25
0.4
DM74
0.35
0.5
= 4 mA, Vee = Min
Vee = Max, VI = 7V
DM74
0.25
0.4
VOL
-18 mA
10L
'I
IIH
IlL
los
Input Current @ Max
Input Voltage
= Max, VI = 2.7V
High Level Input
Current
Vee
Low Level Input
Current
Vee
Short Circuit
Output Current
Vee = Max
(Note2)
= Max, VI = O.4V
D
0.1
0.4
D
20
Enable
80
D
-0.4
Enable
-1.6
DM54
-20
-100
DM74
-20
-100
2·88
6.3
V
V
Enable
Supply Current
Vee = Max (Note 3)
lee
Note 1: All typlcals are at Vee = 5V, TA = 25"C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: lee is measured with all outputs open and all inputs grounded.
Note 4: TA = 25"C and Vee = 5V.
Units
12
V
mA
p.A
mA
mA
mA
Switching Characteristics at Vee =
Symbol
Parameter
5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
RL = 2kn
From (Input)
To (Output)
CL = 15pF
Min
Max
CL = 50pF
Min
Units
Max
tpLH
Propagation Delay Time
Low to High Level Output
Dto
Q
27
30
ns
tpHL
Propagation Delay Time
High to Low Level Output
Dto
Q
17
25
ns
tpLH
Propagation Delay Time
Low to High Level Output
Dto
20
25
ns
Propagation Delay Time
High to Low Level Output
Dto
Q
15
20
ns
tpLH
Propagation Delay Time
Low to High Level Output
Enable to
Q
27
30
ns
tpHL
Propagation Delay Time
High to Low Level Output
Enable to
Q
25
30
ns
tpLH
Propagation Delay Time
Low to High Level Output
Enable to
30
30
ns
Propagation Delay Time
High to Low Level Output
Enable to
15
20
ns
tpHL
tpHL
Q
Q
Q
2·89
~National
~ Semiconductor
54LS83A/DM54LS83A/DM74LS83A
4-Bit Binary Adders with Fast Carry
General Description
Features
These full adders perform the addition of two 4-bit binary
numbers. The sum (l:) outputs are provided for each bit and
the resultant carry (C4) is obtained from the fourth bit.
These adders feature full internal look ahead across all four
bits. This provides the system designer with partial lookahead performance at the economy and reduced package
count of a ripple-carry implementation.
The adder logic, including the carry, is implemented in its
true form meaning that the end-around carry can be accomplished without the need for logic or level inversion.
• Full-carry look-ahead across the four bits
• Systems achieve partial look-ahead performance with
the economy of ripple carry
• Typical add times
Two 8-bit words 25 ns
Two 16-bit words 45 ns
• Typical power dissipation per 4-bit adder 95 mW
• Alternate Military/Aerospace device (54LS83A) is available. Contact a National Semiconductor Sales Office/
Distributor for specifications.
Connection Diagram
Dual-In-Llne Package
84
1:4
16
15
1:4
C4
14
CO
GND
13
J
12
81
A1
11
1:1
10
C4
CO
81
A1
A3
83
1:2
82
9
... 84
r-
A4
A2
1:3
2
A4
1:3
3
6
A3
1:2
7
82
B
A2
TL/F/637B-1
Order Number 54LSB3ADMOB, 54LSB3AFMOB,
DM54LSB3AJ, DM54LSB3AW, DM74LSB3AWM or DM74LSB3AN
See NS Package Number J16A, M16B, N16E or W16A
2-90
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaran·
teed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Input Voltage
7V
Operating Free Air Temperature Range
DM54LS and 54LS
- 55'C to + 125'C
DM74LS
O'Cto +70'C
Storage Temperature Range
-65'C to + 150'C
Recommended Operating Conditions
Symbol
DM54LS83A
Parameter
Vee
Supply Voltage
DM74LS83A
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
0.7
0.8
V
VIH
High Level Input Voltage
Vil
Low Level Input Voltage
10H
High Level Output Current
-0.4
-0.4
mA
10l
Low Level Output Current
4
8
mA
TA
Free Air Operating Temperature
70
'C
2
2
-55
125
V
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 1)
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vee = Min, 11= -18 mA
VOH
High Level Output
Voltage
Vee = Min, IOH = Max
Vil = Max, VIH = Min
DM54
2.5
3.4
DM74
2.7
3.4
Low Level Output
Voltage
Vee = Min, IOl = Max
Vil = Max, VIH = Min
DM54
0.25
0.4
DM74
0.35
0.5
10l = 4 mA, Vee = Min
DM74
0.25
0.4
Input Current @ Max
Input Voltage
Vee = Max
VI = 7V
AorB
0.2
CO
0.1
High Level Input
Current
Vee = Max
VI = 2.7V
AorB
40
CO
20
Low Level Input
Current
Vee = Max
VI = 0.4V
AorB
-0.8
CO
-0.4
Short Circuit
Output Current
Vee = Max
(Note 2)
DM54
-20
-100
DM74
-20
-100
lee1
Supply Current
Vee = Max (Note 3)
19
34
mA
lee2
Supply Current
Vee = Max (Note 4)
22
39
mA
VOL
II
IIH
III
los
Note 1: All typicals are at Vee = SV, TA = 2S'C.
Note 2: Not more than one output should be shorted at a Ume, and the duration should not exceed one second.
Note 3: ICCl is measured with all outputs open, all B inputs low and all other inputs at 4.SV, or all inputs at 4.SV.
Note 4: ICC2 is measured with all outputs open and all inputs grounded.
2-91
V
V
mA
/LA
mA
mA
•
Switching Characteristics at Vee =
5V and T A = 25°C (See Section 1 for Test Waveforms and Output Load)
RL=2kO
Symbol
From (Input)
To (Output)
Parameter
CL = 15pF
Propagation Delay Time
Low to High Level Output
~1
tpHL
Propagation Delay Time
High to Low Level Output
to
l:10rl:2
tpLH
Propagation Delay Time
Low to High Level Output
CO to
tpHL
Propagation Delay Time
High to Low Level Output
CO to
l:3
tpLH
Propagation Delay Time
Low to High Level Output
CO to
Propagation Delay TIme
High to Low Level Output
CO to
Propagation Delay Time
Low to High Level Output
At,BI
Propagation Delay Time
High to Low Level Output
Ai,Bi
Propagation Delay Time
Low to High Level Output
co to
Propagation Delay Time
High to Low Level Output
co to
tpLH
Propagation Delay Time
Low to High Level Output
tpHL
Propagation Delay Time
High to Low Level Output
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
CO to
or ~2
Units
CL = 50pF
Max
Min
Min
Max
24
28
ns
24
30
ns
24
28
ns
24
30
ns
24
28
ns
24
30
ns
24
28
ns
24
30
ns
17
24
ns
17
25
ns
AbBi
toC4
17
24
ns
Ai,Bi
toC4
17
26
ns
co
~3
~4
~4
tO~1
tO~i
C4
C4
Truth Table
Outputs
~
Inputs
WhenC2 = L
~X
A3
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
B3
~X
A4
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
B4
X X
~3
L
~4
~ y; X
L
L
H
H
H
H
L
L
L
L
L
L
L
L
L
L
H
H
H
H
L
L
L
H
H
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
~3
C4
L
L
L
H
H
H
H
w~
WhenC2 = H
H
H
H
l:4
L
L
L
H
H
H
H
H
H
L
L
L
L
L
L
L
H
H
L
L
H
~
L
L
L
L
L
H
H
H
H
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
TLlF/6378-3
H = High Level, L = Low Level
Nota: Input conditions at AI, Bl, A2, B2, and CO are used to determine outputs 1: 1 and 1:2 and the value of the internal CarTY C2. The values at 02, A3, B3, AA, and
B4 are then used to determine outputs 1:3, 1:4, and 04.
2·92
Logic Diagram
(14)
"""-----C4
A3-_~_
"---+ 8, A < 8, and A = 8 outputs of a
stage handling less-significant bits are connected to the corresponding inputs of the next stage handling more-significant bits. The stage handling the least-significant bits must
have a high-level voltage applied to the A = 8 input. The
cascading path is implemented with only a two-gate-Ievel
delay to reduce overall comparison times for long words.
Features
• Typical power dissipation 52 mW
• Typical delay (4-bit words) 24 ns
• Alternate Military/Aerospace device (54LSB5) is available. Contact a National Semiconductor Sales Office/
Distributor for specifications.
Connection Diagram
Dual-In-Llne Package
DATA INPUTS
A3
B2
~
A2
U
A1
~
AO
B1
n
11
BO
10
-
9
Order Number 54LSB5DMOB,
54LS85FMOB, 54LS85LMOB,
DM54LS85J, DM54LS85W,
DM74LSB5M or DM74LS85N
See NS Package Number E20A,
J16A, M16A, N16E or W16A
I-
1
2
3
4
5
6
7
IB
B3
DATA
AB
A>B
A=B
A
A3 <
A3 =
A3 =
A3 =
A3 =
A3 =
A3 =
A3 =
A3 =
A3 =
A3 =
A3 =
A3 =
H
83
83
83
83
83
83
83
83
83
83
83
83
83
83
Cascading
Inputs
Outputs
A2,B2
A1,B1
AO,BO
A>B
AB
A
A2 <
A2 =
A2 =
A2 =
A2 =
A2 =
A2 =
A2 =
A2 =
A2 =
A2 =
82
82
82
82
82
82
82
82
82
82
82
82
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
>
<
=
=
=
=
=
=
=
=
81
81
81
81
81
81
81
81
81
81
X
X
X
AO>
AO <
AD =
AO =
AO =
AO =
AO =
AO =
80
80
80
80
80
80
80
80
X
X
X
X
X
X
X
X
X
H
L
L
= High Level, L = Low Level, X = Don'\ Cere
2-94
X
L
L
L
L
L
H
H
L
L
L
H
H
H
L
L
Absolute Maximum Ratings
(Note)
Note: The ''Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
DM54LS and 54LS
- 55'C to + 125'C
DM74LS
O'Cto +70'C
Storage Temperature Range
-65'Cto + 150'C
Recommended Operating Conditions
Symbol
DM54LS85
Parameter
Vcc
Supply Voltage
VIH
High Level Input Voltage
DM74LS85
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
2
V
V
VIL
Low Level Input Voltage
0.7
0.8
V
10H
High Level Output Current
-0.4
-0.4
rnA
10L
Low Level Output Current
4
8
rnA
TA
Free Air Operating Temperature
70
'C
-55
125
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Min
Typ
(Note 1)
DM54
2.5
3.4
DM74
2.7
3.4
Conditions
Max
Units
-1.5
V
VI
Input Clamp Voltage
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
VIL = Max, VIH = Min
Low Level Output
Voltage
Vee = Min, 10L = Max
VIL = Max, VIH = Min
DM54
0.25
DM74
0.35
0.5
10L = 4 rnA, Vee = Min
DM74
0.25
0.4
Vee = Max
VI = 7V
AB
20
Others
60
AB
-0.4
Others
-1.2
DM54
-20
-100
DM74
-20
-100
10
Nole 2: Not more than one oulput should be shorted at a time, and the duration should not exceed one second.
Nole 3: lee is measured with all outputs open, A = B grounded and all other Inputs at4.SV.
V
0.1
A>B
= SV, TA = 2S'C.
2-95
V
20
rnA
/LA
rnA
rnA
rnA
Switching Characteristics at Vee =
Symbol
Parameter
From
Input
5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
To
Output
Number of
Gate Levels
RL = 2kO
CL = 15pF
Min
tpLH
tpHL
Max
CL = 50pF
Min
Units
Max
Propagation Delay Time
Low-to-High Level Output
AnyAorB
Data Input
AB
3
36
42
A=B
4
40
40
Propagation Delay Time
High-ta-Low Level Output
AnyAorB
Data Input
A < B,
A>B
3
30
40
A=B
4
30
40
ns
ns
tpLH
Propagation Delay Time
Low-to-High Level Output
AB
1
22
26
ns
tpHL
Propagation Delay Time
High-to-Low Level Output
AB
1
17
26
ns
tpLH
Propagation Delay Time
Low-to-High Level Output
A=B
A=B
2
20
25
ns
tpHL
Propagation Delay Time
High-to-Low Level Output
A=B
A=B
2
17
26
ns
tpLH
Propagation Delay Time
Low-to-High Level Output
A>B
orA= B
AB
orA = B
A---(15)
A3
B3 (1)
)0-<
>-
o1b
L
AB
A1
B1
(13)
(14)
Jo-
~
PD-
(2)
(8)
(3)
A=B
(4)
p(12)
)0(11)
~
PA~
oJr-<
AO
BO
A>B
~
r
A2
B2
(5)
(10)
~
(9)
(7)
A > 1000 pF the output is defined as:
Tw
f J~c~~t~.~R.:
,-.,u.
104
!~
103
",
IOZ
~
om
~R",·
10
10
100
1000
CEXT (pF)
TlIF/6385-2
FIGURE 1
= KRxCx
where [Rx is in kn]
[Cx is in pF]
[Tw is in nsl
K::::: 0.37
2-131
•
Operating Rules (Continued)
The K factor is not a constant, but, varies with Cx. See
Figure 2.
100 "F
10
REXT=IOK
CEXT-loo0 pF
TA_25 DC
tA~~ 5~ri
10 "F
-- -
Vee= 5.0V
1 "F
Ei 0.1 "F
... 104 pF
-5
103 pF
102 pF
10pF
-10
i'-
4
TUF/63BS-6
FIGURE 5
TL/F/63BS-3
FIGURE 2
10
4. The switching diode required for most TIL one-shots
when using an electrolytic timing capacitor is not needed
for the 'LS122 and should not be used.
5. To obtain variable pulse width by remote trimming, the
following circuit is recommended:
Rm=10K
cm = 1000 pF
Vec=5.0V
-
PIN(13)~tCx
PIN (11)
5.5
4.5
Vee (VI
0 .2 .4 .6 .B 1.0 1.2 1.4 1.6
"K" COEFFICIENT
-5
,......
'"
........
........
R,,_
I
-10
-60 -30 0 30 60 90 120 150
AMBIENT TEMPERATURE (DCI
Vee
TL/F/63BS-4
TUF/63BS-7
Note: "Rremote" should be as close to the device pins as possible.
FIGURE 3
FIGURE 6
6. The retriggerable pulse width is calculated as shown below:
8. Under any operating condition Cx and Rx must be kept
as close to the one-shot device pins as possible to minimize stray capacitance, to reduce noise pick-up, and to
reduce I-R and Ldildt voltage developed along their connecting paths. If the lead length from Cx to pins (13) and
(11) is greater than 3 cm, for example, the output pulse
width might be quite different from values predicted from
the appropriate equations. A non-inductive and low capacitive path is necessary to ensure complete discharge
of Cx in each cycle of its operation so that the output
pulse width will be accurate.
9. Vee and ground wiring should conform to good high-frequency standards and practices so that switching transients on the Vcc and ground return leads do not cause
interaction between one-shots. A 0.01 /-LF to 0.10 /-LF bypass capaCitor (disk ceramic or monolithic type) from Vee
to ground is necessary on each device. Furthermore, the
bypass capaCitor should be located as close to the Vee
pin as space permits.
T = Tw + tpLH = 0.50 x Rx x Cx + TpLH
The retriggered pulse width is equal to the pulse width
plus a delay time period (Figure 4).
INPUT
OUTPUT
-.J
TUF/63BS-S
FIGURE 4
7. Output pulse width variation versus Vee and operation
temperatures: Figure 5 depicts the relationship between
pulse width variation versus Vee; and Figure 6 depicts
pulse width variation versus temperatures.
'For further detailed device characteristics and output performance
please raler to the NBC one-shot application note AN-366.
2-132
~National
~ Semiconductor
DM7 4LS 123 Dual Retriggerable One-Shot
with Clear and Complementary Outputs
General Description
The DM74LS123 is a dual retriggerable monostable multivibrator capable of generating output pulses from a few nanoseconds to extremely long duration up to 100% duty cycle.
Each device has three Inputs permitting the choice of either
leading edge or trailing edge triggering. Pin (A) is an activelow transition trigger input and pin (8) is an active-high transition trigger input. The clear (CLR) input terminates the output pulse at a predetermined time independent of the timing
components. The clear input also serves as a trigger input
when it is pulsed with a low level pulse transition (l...f'). To
obtain the best trouble free operation from this device
please read the operating rules as well as the NSC one-shot
application notes carefully and observe recommendations.
Features
•
•
•
•
Compensated for Vee and temperature variations
Triggerable from CLEAR input
DTL, TIL compatible
Input clamp diodes
Functional Description
The basic output pulse width is determined by selection of
an external resistor (Rx) and capaCitor (Cx). Once triggered,
the basic pulse width may be extended by retriggering the
gated active-low transition or active-high transition inputs or
be reduced by use of the active-low or CLEAR input. Retrlggering to 100% duty cycle is possible by application of an
input pulse train whose cycle time Is shorter than the output
cycle time such that a continuous "HIGH" logic state is
maintained at the "a" output.
• DC triggered from active-high transition or active-low
transition inputs
• Retriggerable to 100% duty cycle
Connection Diagram
Function Table
Dual·ln·Llne Package
Inputs
CLEAR
Q1
13
62
CLR2
12
B2
b1
A2
10
9
ClR
Q
Outputs
A
B
Q
Q
L
L
L
H
H
H
l...f'
l...f'
l...f'
L
X
x
X
X
H
H
X
X
L
L
J,
t
H
t
L
H
H
..n.
..n.
..n.
H = High Logic Level
1
A1
2
B1
L = Low Logic Level
X = Can Be Either Low or High
t = Positive Going Transition
.j. = Negative Going Transition
Q
ClR
5
Q2
16 17 la
.J1. = A Positive Pulse
l.I' = A Negative Pulse
CEXT REXT/ GND
2
CEXT
2
TLIFI63B6-1
Order Number DM74LS123M or DM74LS123N
See NS Package Number M16A or N16E
2-133
PI
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. ThlfJ dlfJvice should not be operatlfJd at these limits. ThlfJ
paramlfJtric values definlfJd in the "Electrical Characteristics"
table are not guarantelfJd at thlfJ absolute maximum ratings.
The "RecommendlfJd Operating Conditions" table will dlfJfine
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
O'Cto +70'C
Storage Temperature
- 65'C to + 150'C
Recommended Operating Conditions
Symbol
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
Min
Nom
Max
Units
4.75
5
5.25
V
0.8
V
2
V
10H
High Level Output Current
-0.4
mA
10L
Low Level Output Current
8
mA
tw
Pulse Width
(Note 6)
REXT
External Timing Resistor
CEXT
External Timing Capacitance
CWIRE
Wiring Capacitance
at REXT/CEXT Terminal
TA
Free Air Operating Temperature
Electrical Characteristics
Symbol
AorS High
40
AorS Low
40
Clear Low
40
ns
5
kn
260
No Restriction
0
p.F
50
pF
70
'C
over recommended operating free air temperature range (unless otherwise noted)
Parameter
Conditions
Min
Typ
(Note 1)
= Min, II = -18 mA
VI
Input Clamp Voltage
Vee
VOH
High Level Output
Voltage
Vee = Min,loH = Max
VIL = Max, VIH = Min
VOL
Low Level Output
Voltage
Vee = Min, 10L = Max
VIL = Max, VIH = Min
2.7
= 4 mA, Vee = Min
Vee = Max, VI = 7V
10L
Max
Units
-1.5
V
3.4
V
0.35
0.5
0.25
0.4
V
II
Input Current @ Max
Input Voltage
IIH
High Level Input Current
Vee
20
p.A
IlL
Low Level Input Current
Vee
-0.4
mA
los
Short Circuit
Output Current
(Note 2)
-100
mA
= Max, VI = 2.7V
= Max, VI = O.4V
Vee = Max
0.1
-20
mA
Supply Current
Vee = Max (Notes 3,4 and 5)
12
20
mA
lee
Note 1: All typical. are at Vee = 5V, TA = 25'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: Quiescent lee Is measured (aller clearing) with 2.4V applied to all clear and A Inputs, B inputs grounded, all outputs open, Cexr = 0.02 "F, and
REXT = 25 kO.
Note 4: lee is measured In the triggered state with 2.4V applied to all clear and BInputs, Ainputs grounded, all outputs open, CEXT = 0.02 "F, and REXT = 25 kO.
Note 5: With all outputs open and 4.5V applied to all data and clear inputs, lee Is measured aller a momentary ground, then 4.5V is applied to the clock.
Note 6: TA = 25'C and Vee = 5V.
2-134
Switching Characteristics at Vee = 5V and TA = 25°C
RL
Symbol
Parameters
From (Input)
To (Output)
CL = 15pF
CEXT = 0 pF, REXT
Min
= 2kG
= 5 kG
CEXT
Max
CL = 15pF
= 1000 pF, REXT =
Min
10 KG
Units
Max
tpLH
Propagation Delay TIme
Low to High Level Output
AtoQ
33
ns
tpLH
Propagation Delay Time
Low to High Level Output
BtoQ
44
ns
tpHL
Propagation Delay Time
High to Low Level Output
Atoa
45
ns
tpHL
Propagation Delay Time
High to Low Level Output
Btoa
56
ns
tpLH
Propagation Delay Time
Low to High Level Output
Cleartoa
45
ns
tpHL
Propagation Delay TIme
High to Low Level Output
CleartoQ
27
ns
twO(Min)
Minimum Width of Pulse
at Output Q
AorBtoQ
200
ns
tW(out)
Output Pulse Width
AorBtoQ
4
5
,...s
Operating Rules
4. The multiplicative factor K is plotted as a function of Cx
below for design considerations:
100 ~F
1. An external resistor (Rx) and an external capacitor (Cx)
are required for proper operation. The value of Cx may
vary from 0 to any necessary value. For small time constants high-grade mica, glass, polypropylene, polycarbonate, or polystyrene material capacitors may be used. For
large time constants use tantalum or special aluminum
capacitors. If the timing capacitors have leakages approaching 100 nA or if stray capacitance from either terminal to ground is greater than 50 pF the timing equations
may not represent the pulse width the device generates.
r,.~1;q
10 ~F
Vee = 5.0V
1 ~F
E0.1 ~F
u
l04pF
103 pF
2. When an electrolytic capacitor is used for Cx a switching
diode is oiten required for standard TTL one-shots to prevent high inverse leakage current. This switching diode is
not needed for the 'LS123 one-shot and should not be
used. In general the use of the switching diode is not
recommended with retriggerable operation.
102 pF
10 pF
...
o
.2 .4 .6 .8 1.0 1.2 1.4 1.6
'"K'" COEFFICIENT
TL/F/6386-2
FIGURE 1
3. For Cx > > 1000 pF the output pulse width (Twl is defined as follOWS:
Tw = KRxCx
where [Rx is in kG]
[Cx is in pFl
lTw is in nsl
K::::; 0.37
2-135
~
?!i
Operating Rules (Continued)
10
5. For Cx < 1000 pF see Figure 2 for Tw vs Cx family
curves with Rx as a parameter:
105
TAK25°C_~
Rm=10K
Cm-l000 pF
Vee=5.0V
R=250K
Vee-5.0V
-
-5
~.50K
-10
-60 -30 0 30 60 90 120 150
AMBIENT TEMPERATURE 1°C)
10
10
100
Cm IpF}
TL/F/6386-7
1000
TUF/6386-3
FIGURE 2
6. To obtain variable pulse widths by remote trimming, the
following circuit is recommended:
PIN
PIN
I
Rx
Y ..-'+,.-
-r
Cx
~
Rremole
II} OR (14) .....J
Vee
TLlF/6386-4
FIGURE 3
Note: "Rremoto" should be as close to the device pin as possible.
7. The retriggerable pulse width is calculated as shown below:
T = Tw + tpLH = K x Rx x Cx + tpLH
The retriggered pulse width is equal to the pulse width
plus a delay time period (Figure 4).
INPUT
OUTPUT
---1
TL/F/6386-5
FIGURE 6
9. Under any operating condition Cx and Rx must be kept
as close to the one-shot device pins as possible to minimize stray capacitance, to reduce noise pick-up, and to
reduce I-R and Ldildt voltage developed along their
connecting paths. If the lead length from Cx to pins (6)
and (7) or pins (14) and (15) is greater than 3 cm, for
example, the output pulse width might be quite different
from values predicted from the appropriate equations. A
non-inductive and low capacitive path is necessary to
ensure complete discharge of Cx in each cycle of its
operation so that the output pulse width will be accurate.
10. The CEXT pins of this device are internally connected to
the internal ground. For optimum system performance
they should be hard wired to the system's return ground
plane.
11. Vee and ground wiring should conform to good high-frequency standards and practices so that switching transients on the Vee and ground return leads do not cause
interaction between one-shots. A 0.01 /-LF to 0.10 /-LF
bypass capacitor (disk ceramic or monolithic type) from
Vee to ground is necessary on each device. Furthermore, the bypass capacitor should be located as close
to the Vee-pin as space permits.
For further detailed device characteristics and output pertonnance
please rater to the NSC one-ahot application note AN-336.
FIGURE 4
8. Outpu1 pulse width variation versus Vee and temperatures: Figure 5 depicts the relationship between pulse
width variation versus Vee, and Figure 6 depicts pulse
width variation versus temperatures.
10
REn-l0K
Cm"'I000 pF
f-- TA=25°C
o
~
-5
---
-10
4
-. ........
R-l0K
!==fR-l0
17} OR 115}
- ...... .r
5.5
4.5
Vee IV)
TL/F/6386-6
FIGURES
2-136
~National
~ Semiconductor
54LS125A/DM54LS125A/DM74LS125A
Quad TRI-STATE® Buffers
General Description
that two outputs will attempt to take a common bus to opposite logic levels, the disable time is shorter than the enable
time of the outputs.
This device contains four independent gates each of which
performs a non-inverting buffer function. The outputs have
the TRI-STATE feature. When enabled, the outputs exhibit
the low impedance characteristics of a standard LS output
with additional drive capability to permit the driving of bus
lines without external resistors. When disabled, both the
output transistors are turned off presenting a high-impedance state to the bus line. Thus the output will act neither as
a significant load nor as a driver. To minimize the possibility
Features
• Alternate Military/Aerospace device (54LS125) is available. Contact a National Semiconductor Sales Office/
Distributor for specifications.
Connection Diagram
Dual-In-Llne Package
vcc
C4
\14
A4
13
\2
1
A1
C1
Y4
12
C3
11
13
4
Y1
C2
A3
10
15
9
1&
A2
Y2
Y3
8
17
GND
TL/F/6387-'
Order Number 54LS125ADMQB, 54LS125AFMQB, 54LS125ALMQB,
DM54LS125AJ, DM54LS125AW, DM74LS125AM or DM74LS125AN
See NS Package Number E20A, J14A, M14A, N14A or W14B
Function Table
Y=A
Inputs
Output
A
C
Y
L
H
X
L
L
H
L
H
Hi-Z
= High Logic Level
= Low Logic Level
X = Either Low or High Logic Level
Hi-Z = TRI·STATE (Outputs are disabled)
H
L
2-137
II
Absolute Maximum Ratings (Note)
If 'Mllitary/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
DM54LS and 54LS
- 55'C to + 125'C
DM74LS
O'Cto +70'C
Storage Temperature Range
- 65'C to + 150'C
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Recommended Operating Conditions
Symbol
DM54LS125A
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
DM74LS125A
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
2
V
V
VIL
Low Level Input Voltage
0.7
0.8
V
IOH
High Level Output Current
-1
-2.6
mA
24
mA
70
'C
IOL
Low Level Output Current
TA
Free Air Operating Temperature
12
-55
125
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
VI
Input Clamp Voltage
VOH
High Level Output
Voltage
VOL
Low Level Output
Voltage
Conditions
= Min, II = -18 mA
Vee = Min, IOH = Max
VIL = Max, VIH = Min
Vee = Min, IOL = Max
VIL = Max
IOL = 12 mA, Vee = Min
Vee = Max, VI = 7V
Input Current @ Max
Input Voltage
IIH
High Level Input
Current
Vee
IlL
Low Level Input
Current
Vee
IOZH
Off-State Output Current
with High Level Output
Voltage Applied
los
IcC
Typ
(Note 1)
Vee
II
IOZL
Min
2.4
Max
Units
-1.5
V
3.4
V
DM54
0.25
0.4
DM74
0.35
0.5
DM74
0.25
0.4
V
0.1
mA
= Max, VI = 2.7V
20
",A
= Max, VI = 0.4V
-0.4
mA
Vee = Max, Vo = 2.4V
VIH = Min, VIL = Max
20
p.A
Off-State Output Current
with Low Level Output
Voltage Applied
Vee = Max, Vo = 0.4V
VIH = Min, VIL = Max
-20
",A
Short Circuit
Output Current
Vee = Max
(Note 2)
Supply Current
Vee
DM54
-20
-100
DM74
-20
-100
= Max (Note 3)
Nole 1: All typlcals are at Vcc = SV, Til = 25"C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: Icc Is measured with the data control (C) Inputs at 4.SV and the data Inputs grounded.
2-138
11
20
mA
mA
Switching Characteristics at Vee =
5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
RL
Symbol
Parameter
CL
Min
=
=
667.0.
CL
50pF
Max
Min
=
150pF
Units
Max
tpLH
Propagation Delay Time Low
to High Level Output
15
21
ns
tpHL
Propagation Delay Time High
to Low Level Output
18
22
ns
tPZH
Output Enable Time to
High Level Output
25
35
ns
tpZL
Output Enable Time to
Low Level Output
25
40
ns
tpHz
Output Disable Time from
High Level Output (Note 1)
20
ns
tpLZ
Output Disable Time from
Low Level Output (Note 1)
20
ns
Note 1: CL
= 5pF.
2-139
~National
~ Semiconductor
54LS126/DM74LS126A Quad TRI-STATE® Buffers
General Description
This device contains four independent gates each of which
performs a non-inverting buffer function. The outputs have
the TRI-5TATE feature. When enabled, the outputs exhibit
the low Impedance characteristics of a standard LS output
with additional drive capability to permit the driving of bus
lines without external resistors. When disabled, both the
output transistors are turned off presenting a high-impedance state to the bus line. Thus the output will act neither as
a significant load nor as a driver. To minimize the possibility
that two outputs will attempt to take a common bus to opposite logic levels, the disable time is shorter than the enable
time of the outputs.
Connection Diagram
Dual-In-Llne Package
C4
A4
13
Al
Cl
Y4
12
11
CZ
VI
A3
C3
Y3
10
A2
Y2
P
GND
TL/F/6388-1
Order Number 54LS126DMQB, 54LS126FMQB, DM74LS126AM or DM74LS126AN
See NS Package Number M14A, N14A or W14B
Function Table
Y=A
Inputs
Output
A
C
L
H
L
H
X
H
H
L
Hi-Z
H = High Logic Level
L
= Low Logic Level
X = Either Low or High Logic Level
H~Z
= TRI-STATE (Outputs are disabled)
2-140
Y
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
54LS
-55'C to + 125'C
DM74LS
O'Cto +70'C
Storage Temperature Range
-65'Cto + 150'C
Recommended Operating Conditions
Symbol
54LS126
Parameter
DM74LS126A
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
V
VCC
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
0.7
0.8
10H
High Level Output Current
-1
-2.6
mA
10L
Low Level Output Current
12
24
mA
TA
Free Air Operating Temperature
70
'C
2
2
-55
125
V
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
=
=
VI
Input Clamp Voltage
Vcc
VOH
High Level Output
Voltage
Vcc = Min, 10H
VIH = Min
VOL
Low Level Output
Voltage
Vcc = Min, 10L = Max
VIL = Max, VIH = Min
Min, II
Min
-18 mA
=
Max
Input Current @ Max
Input Voltage
IIH
High Level Input Current
IlL
Low Level Input
Current
10ZH
Off-State Output Current
with High Level Output
Voltage Applied
10ZL
los
Max
Units
-1.5
V
2.4
V
54LS
0.4
DM74
= 12 mA, Vcc = Min
Vcc = Max, VI = 10V (54LS)
VI = 7V (DM74)
Vee = Max, VI = 2.7V
Vcc = Max, VI = O.4V
10L
II
Typ
(Note 1)
0.35
0.5
0.25
0.4
V
0.1
mA
20
p.A
-0.4
mA
Vcc = Max, Vo = 2.4V
VIH = Min, VIL = Max
20
p.A
Off-State Output Current
with Low Level Output
Voltage Applied
Vcc = Max, Vo = O.4V
VIH = Min, VIL = Max
-20
/Jo A
Short Circuit
Output Current
Vcc = Max
(Note 2)
54LS
-30
-130
DM74
-20
-100
mA
lee
Supply Current
Vee = Max (Note 3)
DM74
22
mA
ICCL
Supply Current
VI = OV
54LS
24
mA
ICCH
Supply Current
VI = 4.5V
54LS
20
mA
Nole 1: All typicals are at Vce = 5V, TA = 25·C.
Nole 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Nota 3: Icc is measured with both the output control and data inputs grounded.
2·141
12
PI
Switching Characteristics at Vee = 5V and TA = 25"C (See Section 1 for Test Waveforms and Output Load)
54LS
Symbol
Parameter
CL
Min
DM74LS
= 50pF
Max
CL = 150pF,
RL = 6670
Min
Units
Max
tpLH
Propagation Delay Time Low
to High Level Output
15
21
ns
tpHL
Propagation Delay Time High
to Low Level Output
18
22
ns
tPZH
Output Enable Time to
High Level Output
30
36
ns
tpzL
Output Enable Time to
Low Level Output
20
42
ns
tpHZ
Output Disable Time from
High Level Output (Note 1)
30
ns
tpLZ
Output Disable Time from
Low Level Output (Note 1)
30
ns
Note 1: CL = 5pF.
2·142
~National
~ Semiconductor
DM54LS132/DM74LS132 Quad 2-lnput
NAND Gates with Schmitt Trigger Inputs
General Description
This device contains four independent gates each of which
performs the logic NAND function. Each input has hysteresis which increases the noise immunity and transforms a
slowly changing input signal to a fast changing. jitter free
output.
Connection Diagram
Dual-In-Llne Package
Vee
B4
A4
V4
B3
A3
V3
V2
GND
10
AI
BI
A2
VI
B2
TLlF/6389-1
Order Number DM54LS132J, DM54LS132W, DM74LS132M or DM74LS132N
See NS Package Number J14A, M14A, N14A or W14B
Function Table
Y =AB
Inputs
Output
A
B
Y
L
L
L
H
H
H
L
H
H
H
H
L
H = High Logic Level
L = Low Logic Level
2-143
•
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications,
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
OM54LS
- 55·C to + 125·C
OM74LS
O·Cto +70·C
Storage Temperature Range
-65·C to + 150·C
Recommended Operating Conditions
Symbol
DM74LS132
DM54LS132
Parameter
Units
Min
Nom
Max
Min
Nom
Max
Vee
Supply Voltage
4.5
5
5.5
4.75
5
5.25
V
VT+
Positive-Going Input
Threshold Voltage (Note 1)
1.4
1.6
1.9
1.4
1.6
1.9
V
VT-
Negative-Going Input
Threshold Voltage (Note 1)
0.5
0.8
1
0.5
0.8
1
V
0.4
0.8
0.4
0.8
HYS
Input Hysteresis (Note 1)
10H
High Level Output Current
-0.4
-0.4
rnA
10l
Low Level Output Current
4
8
rnA
TA
Free Air Operating Temperature
70
·c
-55
125
0
V
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 2)
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vee = Min, 11= -18 rnA
VOH
High Level Output
Voltage
Vee = Min, 10H = Max,
VI = VT- Min
OM54
2.5
3.4
OM74
2.7
3.4
Low Level Output
Voltage
Vee = Min, 10l = Max,
OM 54
0.25
0.4
= VT+ Max
10l = 4 rnA, Vee = Min
Vcc = 5V, VI = VT+
OM74
0.35
0.5
OM74
0.25
0.4
VOL
VI
IT+
Input Current at
Positive-Going Threshold
IT-
Input Current at
Negative-Going Threshold
Vee = 5V, VI = VT-
II
Input Current @ Max
Input Voltage
Vcc = Max, VI
V
-0.14
rnA
-0.18
rnA
= 7V
= Max, VI =
V
0.1
rnA
IIH
High Level Input Current
Vcc
III
Low Level Input Current
Vee = Max, VI = O.4V
los
Short Circuit
Output Current
Vcc = Max
(Note 3)
ICCH
Supply Current with
Outputs High
Vee
= Max
5.9
11
rnA
leel
Supply Current with
Outputs Low
Vcc
= Max
8.2
14
rnA
2.7V
/loA
rnA
OM 54
-20
-100
OM74
-20
-100
Note I: vee = 5V
Note 2: All typlcals ara at Vee = 5V, TA = 25"C.
Nota 3: Not more than one output should be shorted at a Ume, and the duration should not exceed one second.
2-144
20
-0.4
rnA
Switching Characteristics at Vee 5V and TA =
25°C (See Section 1 for Test Waveforms and Output Load)
RL = 2kO
Symbol
Parameter
CL=50pF
CL = 15pF
Units
Min
Max
Min
Max
tpLH
Propagation Delay Time
Low to High Level Output
5
22
8
25
ns
tpHL
Propagation Delay Time
High to Low Level Output
5
22
10
33
ns
2-145
~r---------------------------------------------------------------~
~
!i
~ National
~ Semiconductor
54LS 133/DM74LS 133
13-lnput NAND Gate
General Description
This device contains one, 13-input gate that performs the
logic NAND functions.
Connection Diagram
Dual-In-Llne Package
TLlF/9818-1
Order Number 54LS133DMQB, 54LS133FMQB,
54LS133LMQB, DM74LS133M or DM74LS133N
See NS Package Number E20A, J16A, M16A, N16E or W16A
2-146
Absolute Maximum Ratings
(Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for acutal device operatiOn.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
54LS
- 55·C to + 125·C
O·Cto +70·C
DM74LS
Storage Temperature Range
-65·Cto +150·C
Recommended Operating Conditions
Symbol
54LS133
Parameter
DM74LS133
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
0.7
0.8
V
Vcc
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
10H
High Level Output Current
-0.4
-0.4
mA
10L
Low Level Output Current
4
8
mA
TA
Free Air Operating Temperature
70
·C
2
2
-55
125
V
0
Electrical Characteristics Over recommended operating free air temperature range (unless otherwise noted)
Parameter
Symbol
Conditions
Min
Typ
(Note 1)
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vcc = Min, II = -18 mA
VOH
High Level Output
Voltage
Vcc = Min, 10H = Max
VIL = Max
54LS
2.5
DM74
2.7
Low Level Output
Voltage
Vec = Min, 10L = Max
VIH = Min
DM74
0.35
0.5
10L = 4 mA, Vcc = Min
DM74
0.25
0.4
II
Input Current @ Max
Input Voltage
Vcc = Max, VI = 10V
IIH
High Level Input Current
Vcc = Max, VI = 2.7V
20
,...A
IlL
Low Level Input Current
Vcc = Max, VI = 0.4V
-0.4
mA
los
Short Circuit
Output Current
Vcc = Max
(Note 2)
ICCH
Supply Current with
Outputs High
Vee = Max, VIN = GND
ICCL
Supply Current with
Outputs Low
Vee = Max, VIN = Open
VOL
V
3.4
54LS
0.4
V
0.1
mA
54LS
-20
-100
DM74
-20
-100
mA
0.5
mA
1.1
mA
Note 1: All typical. are at Vee = SV, TA = 2S'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Switching Characteristics at Vce =
Symbol
5V and T A = 25·C (See Section 1 for Test Waveforms and Output Load)
RL=2kO,CL=15pF
Parameter
Min
Units
Max
tpLH
Propagation Delay Time
Low to High Level Output
15
ns
tpHL
Propagation Delay Time
High to Low Level Output
38
ns
2-147
•
~
!i
~ National
~ Semiconductor
54LS 136/DM54LS 136/DM74LS 136
Quad 2-lnput Exclusive-OR Gate
with Open-Collector Outputs
General Description
Features
This device contains four independent gates, each of which
performs the logic exclusive-OR function.
• Alternate Military/Aerospace device (54LS136) is available. Contact a National Semiconductor Sales Office/
Distributor for specifications.
Connection Diagram
Dual-In-Llne Package
,.!Lv
13 CC
..-----1-":'::'"
L---~
5
GND
CZs-
10
. . :. ._~=- t-_- -'~J ~lTL/F/9819-1
Order Number 54LS136DMQB, 54LS136FMQB,
DM54LS136J, DM54LS136W, DM74LS136M or DM74LS136N
See NS Package Number J14A, M14A, N14A or W14B
Truth Table
Output
Inputs
A
B
z
L
L
L
L
H
H
H
L
H
L
H
H
H = HIGH Voltage Level
L = LOW Voltage Level
2-148
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
-55'C to + 125'C
DM54LS and 54LS
DM74LS
O'Cto +70'C
Storage Temperature Range
-65'C to + 150'C
Recommended Operating Conditions
Symbol
DM54LS136
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
IOL
Low Level Output Current
Units
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
0.7
0.8
V
4
8
rnA
70
·C
2
2
-55
Free Air Operating Temperature
TA
DM74LS136
Min
125
V
0
Electrical Characteristics Over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
=
=
VI
Input Clamp Voltage
Vee
VOL
Low Level Output
Voltage
Vee = Min, IOL
VIH = Min
IOL
Min,ll
Input Current @ Max
Input Voltage
Vee
IIH
High Level Input Current
Vee
IlL
Low Level Input Current
lee
Supply Current
Max, VI
Vee
=
=
Vee
=
Max
Max, VI
Typ
(Note 1)
-18 rnA
=
Max
= 4 rnA, Vee = Min
= Max, VI = 10V
II
Min
=
=
Max
Units
-1.5
V
DM54
0.25
0.4
DM74
0.35
0.5
DM74
0.25
0.4
V
0.2
rnA
2.7V
40
/LA
O.4V
-0.6
rnA
10
rnA
Note 1: All typicals are at Vee = SV, TA = 2S'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Switching Characteristics at Vee =
5V and TA
=
25'C (See Section 1 for Test Waveforms and Output Load)
= 2kO
CL = 15pF
RL
Symbol
Parameter
Min
Units
Max
tpLH
Propagation Delay Time
Low to High Level Output
23
ns
tpHL
Propagation Delay Time
High to Low Level Output
23
ns
2·149
•
~National
~ Semiconductor
54LS 138/DM54LS 138/DM74LS 138,
54LS 139/DM54LS 139/DM74LS 139
Decoders/Demultiplexers
General Description
These Schottky-clamped circuits are designed to be used in
high-performance memory-decoding or data-routing applications, requiring very short propagation delay times. In
high-performance memory systems these decoders can be
used to minimize the effects of system decoding. When
used with high-speed memories, the delay times of these
decoders are usually less than the typical access time of the
memory. This means that the effective system delay introduced by the decoder is negligible.
The LS138 decodes one-of-eight lines, based upon the conditions at the three binary select inputs and the three enable
inputs. Two active-low and one active-high enable inputs
reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented with no external inverters, and a 32-line decoder requires only one
inverter. An enable input can be used as a data input for
demultiplexing applications.
The LS139 comprises two separate two-line-to-four-line decoders in a single package. The active-low enable input can
be used as a data line in demultiplexing applications.
All of these decoders/demultiplexers feature fully buffered
inputs, presenting only one normalized load to its driving
circuit. All inputs are clamped with high-performance
Schottky diodes to suppress line-ringing and simplify system
design.
Features
• Designed specifically for high speed:
Memory decoders
Data transmission systems
• LS138 3-lo-8-line decoders incorporates 3 enable inputs to simplify cascading and/or data reception
• LS139 contains two fully independent 2-to-4-line decoders/demultiplexers
• Schottky clamped for high performance
• Typical propagation delay (3 levels of logiC)
LS138 21 ns
LS139 21 ns
• Typical power dissipation
LS138 32 mW
LS139 34 mW
• Alternate
Military/Aerospace
devices
(54LS138,
54LS139) are available. Contact a National Semiconductor Sales Office/ Distributor for specifications.
Connection Diagrams
Dual-In-Llne Package
Dual-In-Llne Package
DATA OUTPUTS
vcc
116
.
,~----------~----------,
YO
Y1
15
Y3
Y2
14
13
Y4
12
Y5
11
ENABLE
G2
vCC
Y6
10
116
9
,
\15
!
SELECT
.
B2
A2
\14
.,
\13
DATA OUTPUTS
2YO
\12
1 !
\
2Y1
\11
~
2Y2
,
2Y3
9
\10
.A
po
r-
Ie>
2
A
B
SELECT
3
C
4
5
6
J
Y77 G!:
1
ENABLE
G1
G2A G2B
G1
..
' - -.....- - - ' OUTPUT
ENABLE
12
. .
A1
J
13
B1
SELECT
TL/F/6391-1
Order Number 54LS138DMQB, 54LS138FMQB,
54LS138LMQB, DM54LS138J, DM54LS138W,
DM74LS138M or DM74LS138N
See NS Package Number E20A, J16A,
M16A, N16E or W16A
.
DATA OUTPUTS
TUF/6391-2
Order Number 54LS139DMQB, 54LS139FMQB,
54LS139LMQB, DM54LS139J, DM54LS139W,
DM74LS139M or DM74LS139N
See NS Package Number E20A, J16A,
M16A, N16E or W16A
2-150
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
DM54LS and 54LS
- 55·C to + 125·C
DM74LS
O·Cto +70"C
Storage Temperature Range
-65·Cto +150·C
Recommended Operating Conditions
Symbol
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
DM74LS138
DM54LS138
Parameter
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
0.7
0.8
V
2
V
2
IOH
High Level Output Current
-0.4
-0.4
mA
IOL
Low Level Output Current
4
8
mA
TA
Free Air Operating Temperature
70
·C
Max
Units
-1.5
V
-55
125
0
'LS138 Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 1)
= Min,ll = -18 mA
VI
Input Clamp Voltage
Vee
VOH
High Level Output
Voltage
Vee = Min, IOH = Max,
VIL = Max, VIH = Min
DM54
2.5
3.4
DM74
2.7
3.4
Low Level Output
Voltage
Vee = Min, IOL = Max,
VIL = Max, VIH = Min
DM54
0.25
DM74
0.35
0.5
= 4 mA, Vee = Min
Vee = Max, VI = 7V
DM74
0.25
0.4
VOL
IOL
II
Input Current @ Max
Input Voltage
= Max, VI = 2.7V
= Max, VI = O.4V
Vee = Max
V
0.4
0.1
V
mA
IIH
High Level Input Current
Vee
20
poP.
IlL
Low Level Input Current
Vee
-0.36
mA
los
Short Circuit
Output Current
(Note 2)
DM54
-20
-100
DM74
-20
-100
Supply Current
Vee = Max (Note 3)
lee
Note 1: All typicals are at Vcc = 5V, TA = 25'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: Icc is measured with all outputs enabled and open.
2-151
6.3
10
rnA
mA
II
'LS138 Switching Characteristics
= 5V and TA = 25"C (See Section 1 for Test Waveforms and Output Load)
at Vee
Symbol
Parameter
From (Input)
To (Output)
RL
Levels
of Delay
CL
Min
=
=
2kfl
15pF
Max
CL
= 50pF
Min
Units
Max
tpLH
Propagation Delay Time
Low to High Level Output
Select to
Output
2
18
27
ns
tpHL
Propagation Delay Time
High to Low Level Output
Select to
Output
2
27
40
ns
tpLH
Propagation Delay Time
Low to High Level Output
Select to
Output
3
18
27
ns
tpHL
Propagation Delay Time
High to Low Level Output
Select to
Output
3
27
40
ns
tpLH
Propagation Delay Time
Low to High Level Output
Enable to
Output
2
18
27
ns
tpHL
Propagation Delay Time
High to Low Level Output
Enable to
Output
2
24
40
ns
tpLH
Propagation Delay Time
Low to High Level Output
Enable to
Output
3
18
27
ns
tpHL
Propagation Delay Time
High to Low Level Output
Enable to
Output
3
28
40
ns
Recommended Operating Conditions
Symbol
DM54LS139
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
IOH
DM74LS139
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
2
V
V
0.7
0.8
V
High Level Output Current
-0.4
-0.4
rnA
IOL
Low Level Output Current
4
8
mA
TA
Free Air Operating Temperature
70
"C
-55
125
2-152
0
'LS 139 Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Min
Typ
(Note 1)
DM54
2.5
3.4
DM74
2.7
3.4
Conditions
=
=
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vee
VOH
High Level Output
Voltage
Vee = Min, 10H = Max,
VIL = Max, VIH = Min
Low Level Output
Voltage
Vee = Min, 10L = Max
VIL = Max, VIH = Min
DM54
0.25
0.4
DM74
0.35
0.5
= 4 mA, Vee = Min
Vee = Max, VI = 7V
DM74
0.25
0.4
VOL
Min,ll
-18 mA
10L
II
Input Current @ Max
Input Voltage
IIH
High Level Input Current
Vee
=
=
=
Max, VI
IlL
Low Level Input Current
Vee
los
Short Circuit
Output Current
Vee
Max
(Note 2)
Supply Current
Vee
lee
=
Max, VI
=
=
V
V
0.1
mA
2.7V
20
p.A
O.4V
-0.36
mA
DM54
-20
-100
DM74
-20
-100
11
6.8
Max (Note 3)
mA
mA
NOle 1: All typicals are at Vee = SV. TA = 2S'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Nole 3: lee is measured with all outputs enabled and open.
'LS139 Switching Characteristics
at Vee
=
5V and T A
Symbol
=
25'C (See Section 1 for Test Waveforms and Output Load)
From (Input)
To (Output)
Parameter
RL
CL
Min
=
=
15pF
2kO
CL
Max
=
Units
50pF
Min
Max
tpLH
Propagation Delay Time
Low to High Level Output
Select to
Output
18
·27
ns
tpHL
Propagation Delay Time
High to Low Level Output
Select to
Output
27
40
ns
tpLH
Propagation Delay Time
Low to High Level Output
Enable to
Output
18
27
ns
tpHL
Propagation Delay Time
High to Low Level Output
Enable to
Output
24
40
ns
Function Tables
LS13B
LS139
Inputs
Enable
Outputs
Select
Enable
G1 G2· C B A VO V1
X
H
L
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
Inputs
X X X
X X X
H
L
L
L
L
H
H L
H H
L
H
H
H
H
H
H
H
L H
H H
H L H
H H H
L
L
L
L
L
H
H
H
H
L
H
H
H
H
H
H
Outputs
Select
V2 V3 V4 V5 V6 V7
G
B
A
VO
V1
V2
V3
H
H
H
H
L
H
H
L
L
L
L
X
X
H
H
H
L
L
L
H
L
H
H
L
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
L
H = High Level, L = Low Level, X = Don'\ Care
'G2=G2A+G2B
H = High Level. L = Low Level. X = Don'\ Care
2-153
L
=r------------------------------------------------------------------------
i
!J
!J
Logic Diagrams
LS138
DATA
OUTPUTS
A (1)
SELECT
B (2)
INPUTS
C (3)
TLlFf6391-3
LS139
ENABLE G1 (1)
DATA
(12)2YO
ENABLE G2 (15)
OUTPUTS
(11)2Y1
TLlFf6391-4
2-154
lii
.....
~National
U1
.....
~ Semiconductor
54LS 151/DM54LS 151/DM7 4LS 151
Data SelectorIMultiplexer
General Description
Features
This data selector/multiplexer contains full on-chip decoding to select the desired data source. The 'LS151 selects
one-of-eight data sources. The 'LS151 has a strobe input
which must be at a low logic level to enable these devices.
A high level at the strobe forces the W output high, and the
Y output low.
The 'LS151 features complementary Wand Y outputs.
•
•
•
•
•
Select one-of-eight data lines
Performs parallel-to-serial conversion
Permits multiplexing from N lines to one line
Also for use as Boolean function generator
Typical average propagation delay time data input to W
output 12.5 ns
• Typical power dissipation 30 mW
• Alternate Military/Aerospace device (54LS151) is available. Contact a National Semiconductor Sales Office/
Distributor for specifications.
Connection Diagram
Dual-In-Line Package
DATA INPUTS
04
15
14
3
2
02
03
06
05
01
13
A
5
y
C
B
10
11
12
4
DO
DATA INPUTS
DATA SELECT
07
7\8
6
W
9
STROBE GNO
OUTPUTS
TUF/6392-1
Order Number 54LS151DMQB, 54LS151FMQB, 54LS151LMQB,
DM54LS151J, DM54LS151W, DM74LS151M or DM74LS151N
See NS Package Number E20A, J16A, M16A, N16E or W16A
Truth Table
Inputs
Select
H
C
B
A
X
X
X
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
~
High Level, L
DO, 01...07
~
~
Outputs
Strobe
S
y
W
H
L
L
L
L
L
L
L
L
L
DO
D1
D2
D3
04
05
06
07
H
DO
D1
D2
03
04
05
06
07
Low Level, X = Don't Care
the level of the respective 0 input
2-155
•
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
DM54LS and 54LS
- 55'C to + 125'C
DM74LS
O"Cto +70'C
Storage Temperature Range
- 65'C to + 150'C
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Recommended Operating Conditions
Symbol
DM54LS151
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
10H
High Level Output Current
Low Level Output Current
TA
Free Air Operating Temperature
Symbol
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
10L
Electrical Characteristics
DM74LS151
2
V
0.7
0.8
V
-0.4
-0.4
mA
8
mA
70
'C
4
-55
125
0
over recommended operating free air temperature range (unless otherwise noted)
Parameter
Conditions
Min
Typ
(Note 1)
= Min,ll = -18 rnA
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vee
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
VIL = Max, VIH = Min
DM54
2.5
3.4
DM74
2.7
3.4
Low Level Output
Voltage
Vee = Min, 10L = Max
VIL = Max, VIH = Min
DM54
0.25
0.4
DM74
0.35
0.5
= 4 rnA, Vee = Min
Vee = Max, VI = 7V
DM74
0.25
0.4
VOL
10L
II
Input Current @ Max
Input Voltage
V
V
0.1
V
rnA
IIH
High Level Input Current
Vee
p.A
Low Level Input Current
Vee
-0.4
rnA
los
Short Circuit
Output Current
= Max, VI = 2.7V
= Max, VI = O.4V
Vee = Max
20
IlL
DM54
-20
-100
(Note 2)
DM74
-20
-100
Supply Current
Vee = Max (Note 3)
lee
Note 1: All typlcals are at Vcc = 5V, TA = 25'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Not. 3: Icc Is measured with all outputs open, strobe and data select Inputs at 4.5V, and all other Inputs open.
2-156
6
10
rnA
rnA
Switching Characteristics at Vee =
RL=2kO
From (Input)
To (output)
Parameter
Symbol
5V and T A = 25°C (See Section 1 for Test Waveforms and Output Load)
CL = 15pF
Min
....
Units
CL = 50pF
Min
Max
~
....
CJI
Max
tpLH
Propagation Delay Time
Low to High Level Output
Select
(4 Levels) to Y
43
46
ns
tpHL
Propagation Delay Time
High to Low Level Output
Select
(4 Levels) to Y
30
36
ns
tpLH
Propagation Delay Time
Low to High Level Output
Select
(3 Levels) to W
23
25
ns
tpHL
Propagation Delay Time
High to Low Level Output
Select
(3 Levels) to W
32
40
ns
tpLH
Propagation Delay Time
Low to High Level Output
Strobe
toY
42
44
ns
tpHL
Propagation Delay Time
High to Low Level Output
Strobe
toY
32
40
ns
tpLH
Propagation Delay Time
Low to High Level Output
Strobe
toW
24
27
ns
tpHL
Propagation Delay Time
High to Low Level Output
Strobe
toW
30
36
ns
tpLH
Propagation Delay Time
Low to High Level Output
DOthru D7
toY
32
35
ns
tpHL
Propagation Delay Time
High to Low Level Output
DO thru D7
toY
26
33
ns
tpLH
Propagation Delay Time
Low to High Level Output
DOthru D7
toW
21
25
ns
tpHL
Propagation Delay Time
High to Low Level Output
DOthru D7
toW
20
27
ns
Logic Diagram
LS151
STROB~~
(ENABLE) (4)
00
}01
(3)
>-f"
(2)
~
Address Buffers for 54LS151174LS151
A A ii
02
f-- H
03 (1)
r-r
04(15)
r"'f"
DATA
INPUTS
}-
~ --.
~
~OUTPUTY
(6)
OUTPUTW
~
r-r
(14)
05
....r-
-r
,A
A
ii
B
!!2!.....(>
(9)
C
1-"
-v
1 -"
-v
TL/F/6392-3
>-f"
(12)
07
C
['~
c
)(13)
06
SE~~~
(BINARY)
B
}}-
Bee,
TUF/6392-2
See Address Buffers to the Right
2·157
II
~
!!i
~ National
~ Semiconductor
54LS152
a-Input Multiplexer
General Description
The 54LS152 is a high speed 8-input digital multiplexer. It
provides, in one package, the ability to select one line of
data from up to eight sources. The 54LS152 can be used as
a universal function generator to generate any logic function
of four variables. It is supplied in Flatpak only; for Dual-InLine Package applications use the 'LS151.
Connection Diagram
Logic Symbol
Dual·ln·Llne Package
14- 1
'-/
14
-Vee
13- 2
13 -15
1 0 - SO
12- 3
12 1-16
9 -
51
11- 4
111-17
8 -
52
10- 5
10 r-SO
Z-
6
9 r-Sl
GND- 7
81-S2
1011121314151617
z
TL/F/l0206-2
TLlF/10206-1
vee = Pin 14
GND = Pin 7
Order Number 54LS152FMQB
See NS Package Number W14B
Pin Names
10-17
SO-S2
Z
Description
Truth Table
Data Inputs
Select Inputs
Inverted Data Outputs
Inputs
S1
so
Z
L
L
L
L
L
L
L
H
H
H
H
io
i1
i2
is
L
L
H
H
H
H
H
H
H
H
H = HIGH Voltage Lavel
L = LOW Voltage Lavel
2·158
output
S2
L
L
L
i4
i5
i6
i7
Absolute Maximum Ratings
(Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaran·
teed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
-55'Cto +25'C
54LS
Storage Temperature Range
-65'C to + 150'C
Recommended Operating Conditions
Symbol
54LS152
Parameter
Units
Min
Nom
Max
4.5
5
5.5
V
0.7
V
Vee
Supply Voltage
V,H
High Level Input Voltage
V,l
Low Level Input Voltage
10H
High Level Output Current
-0.4
mA
10l
Low Level Output Current
4.0
mA
TA
Free Air Operating Temperature
125
'C
V
2
-55
Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
Conditions
V,
Input Clamp Voltage
Vee = Min, I, = -18 mA
VOH
High Level
Output Voltage
Vee = Min, 10H = Max,
V,l = Max, V,H = Min
VOL
Low Level
Output Voltage
Vee = Min, 10l = Max,
V,H = Min, V,l = Max
I,
Input Current @
Max Input Voltage
Vee = Max, V, = 10.0V
I'H
High Level
Input Current
Vee = Max, V, = 2.7V
I,l
Low Level
Input Current
Vee = Max, V, = 0.5V
los
Short Circuit
Output Current
Vee = Max
(Note 2)
lee
Supply Current
Vee = Max (Note 3)
Min
Typ
(Note 1)
2.5
Max
Units
-1.5
V
3.4
V
0.4
V
0.1
mA
20
p.A
-30
-400
p.A
-20
-100
mA
9
mA
Note 1: All typical. are at Vee = SV, TA = 2S'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Switching Characteristics Vee = + 5.0V, TA = + 25'C (See Section 1 for test waveforms and output load)
Symbol
CL=15pF
Parameter
Min
Units
Max
tplH
lpHl
Propagation Delay, Sn to Z
23
32
ns
tplH
tpHl
Propagation Delay, In to Z
21
20
ns
2·159
Functional Description
The 54LS152 is a logical implementation of a single pole, a-position switch with the switch position controlled by the state of
three Select inputs, SO, 51, 52. The logic function provided at the output is:
Z = (10 - SO - 51 - 52 + 11 - SO - 51 - 52 + 12 - SO - 51 - 52 + 13 - SO - 51 - 52
+ 14-S0-S1-S2 + 15-S0-S1-S2 + IS-SO-S1-S2 + 17-S0-S1-S2).
The 54LS152 provides the ability, in one package, to select from eight sources of data or control information.
Logic Diagram
10
11
12
13
14
IS
16
17
so
SI
S2
TL/F110206-3
2-1S0
~National
~ Semiconductor
54LS 153/DM54LS 153/DM74LS 153
Dual 4-Line to 1-Line Data Selectors/Multiplexers
General Description
Each of these data selectors/multiplexers contains inverters and drivers to supply fully complementary, on-chip, binary decoding data selection to the AND-OR-invert gates.
Separate strobe inputs are provided for each of the two
four-line sections.
Features
• Permits multiplexing from N lines to 1 line
• Performs at parallel-to-serial conversion
• Strobe (enable) line provided for cascading (N lines to
n lines)
• High fan-out, low impedance, totem pole outputs
• Typical average propagation delay times
- From data 14 ns
- From strobe 19 ns
- From select 22 ns
• Typical power dissipation 31 mW
• Alternate Military/Aerospace device (54LS153) is available. Contact a National Semiconductor Sales Office/
Distributor for specifications.
Connection Diagram
Dual-In-Line Package
DATA INPUTS
Order Number 54LS153DMQB, 54LS153FMQB,
54LS153LMQB, DM54LS153J, DM54LS153W,
DM74LS153M or DM74LS153N
See NS Package Number E20A, J16A, M16A,
N16EorW16A
STROBE B
lG SELECT
DATA INPUTS
TL/F/6393-1
Logic Diagram
Function Table
STROBE G1 (1)
tCO (81
Select
Inputs
1e1 (5)
B
A
CO
C1
C2
1C2 (4)
X
X
X
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
H
X
X
X
X
X
X
X
X
DATA 1
'C3 (31
f"
(111
Data Inputs
X
X
X
X
X
X
L
H
X
X
X
X
L
H
X
X
Strobe
Output
C3
G
Y
X
X
X
X
X
X
H
L
L
L
L
L
L
L
L
L
L
H
L
H
L
H
L
H
X
L
H
2C'
DATA 2
2C2C121
Select inputs A and B are common to both sections.
H
2C3(13)
STROBE 02(15)
2-161
= High Level. L = Low Level, X = Oon't Care
•
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and speclflcaUons.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
DM54LS and 54LS
- 55·C to + 125·C
DM74LS
O·Cto +70"C
-65·C to + 150" C
Storage Temperature Range
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Recommended Operating Conditions
Symbol
DM54LS153
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
10H
DM74LS153
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
V
V
2
0.7
0.8
V
High Level Output Current
-0.4
-0.4
mA
10L
Low Level Output Current
4
8
mA
TA
Free Air Operating Temperature
70
·c
Electrical Characteristics
Symbol
-55
125
0
over recommended operating free air temperature range (unless otherwise noted)
Parameter
Conditions
Min
Typ
(Note 1)
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vee = Min, 11= -18 mA
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
VIL = Max, VIH = Min
DM54
2.5
3.4
DM74
2.7
3.4
Low Level Output
Voltage
Vee = Min, 10L = Max
VIL = Max, VIH = Min
DM54
0.25
0.4
DM74
0.35
0.5
10L = 4 mA, Vee = Min
DM74
0.25
0.4
VOL
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 7V
V
0.1
V
mA
IIH
High Level Input Current
Vee = Max, VI = 2.7V
20
p.A
IlL
[ow Level Input Current
Vee = Max, VI = 0.4V
-0.36
mA
los
Short Circuit
Output Current
Vee = Max
(Note 2)
-100
mA
DM54
-20
DM74
-20
Supply Current
Vee = Max (Note 3)
Note 1: All Iypicals are at Vee ~ 5V, TA ~ 25" C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: Icc Is measured with all outputs open and all other inputs grounded.
lee
2-162
-100
6.2
10
mA
Switching Characteristics
...
Ii)
at Vee
=
5V and TA
=
25°C (See Section 1 for Test Waveforms and Output Load)
en
Co)
RL
=
2 kll
From (Input)
Symbol
Parameter
to (Output)
CL
Min
=
15pF
Max
CL
Min
=
50pF
Units
Max
tpLH
Propagation Delay Time
Low to High Level Output
DatatoY
15
20
ns
tpHL
Propagation Delay Time
High to Low Level Output
DatatoY
26
35
ns
tpLH
Propagation Delay Time
Low to High Level Output
SelecttoY
29
35
ns
tpHL
Propagation Delay Time
High to Low Level Output
Select to Y
38
45
ns
tpLH
Propagation Delay Time
Low to High Level Output
Strobe to Y
24
30
ns
tpHL
Propagation Delay Time
High to Low Level Output
Strobe toY
32
40
ns
•
2-163
~
."
r--------------------------------------------------------------------------------,
§ ~National
~ Semiconductor
DM54LS154/DM74LS154 4-Line to 16-Line
Decoders/Demultiplexers
General Description
Features
Each of these 4-line-to-16-lIne decoders utilizes TTL circuitry to decode four binary-coded inputs into one of sixteen
mutually exclusive outpu1s when both the strobe inputs, G1
and G2, are low. The demultiplexing function Is performed
by using the 4 input lines to address the output line, passing
data from one of the strobe inputs with the other strobe
input low. When either strobe input is high, all outputs are
high. These demultiplexers are ideally suited for implementing high-performance memory decoders. All inputs are buffered and input clamping diodes are provided to minimize
transmission-line effects and thereby simplify system design.
• Decodes 4 binary-coded inputs into one of 16 mutually
exclusive outputs
• Performs the demultiplexing function by distributing data
from one input line to anyone of 16 outputs
• Input clamping diodes simplify system design
• High fan-out, low-impedance, totem-pole outputs
• Typical propagation delay
3 levels .of logic 23 ns .
Strobe 19 ns
• Typical power dissipation 45 mW
Connection and Logic Diagrams
A
Dual-In-Llne Package
INPUTS
Vl~24
A
23
B
22
C
D
21
OUTPUTS
G2
20
19
G1
15
18
17
14
16
13
12
15
-I----.
B
C
11
14
D
A
>-1----.
(2)
"""
(3)
B
( 18)
(4)
>-
0-
(5)
3
4
C
( 23)
A
A
1
A
T
ii
B
22)
,0
2
G
G2
( 19)
1
o
13
G1
roO
(1)
2
3
2
5
4
3
4
7
6
5
6
9
8
7
8
10
9
11 112
10, GND
-V C
",,"-
(7)
D
( 20
D
0
6
7
(9)
......
(10)
f--,.
(11)
D
I
5
(8)
~
TLiF 16394-1
Order Number DM54LS154J,
DM74LS154WM or DM74LS154N
See NS Package Number J24A, M24B or N24A
(6)
"""
C
( 21)
c
OUTPUTS
>-
D
~
c:
8
01
9
10
I----. (13)
11
C
"""
(14)
12
~
"""-
ii
A
"""
Gt::
A
B
C
(15)
13
(16)
14
(17)
15
D
TL/F/6394-2
2-164
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
DM54LS
-55'C to + 125'C
DM74LS
O'Cto +70'C
Storage Temperature Range
-65'C to + 150'C
Recommended Operating Conditions
Symbol
DM54LS154
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
DM74LS154
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
0.7
0.8
V
2
2
V
10H
High Level Output Current
-0.4
-0.4
mA
10L
Low Level Output Current
4
8
mA
TA
Free Air Operating Temperature
70
'C
Electrical Characteristics
Symbol
-55
125
0
over recommended operating free air temperature range (unless otherwise noted)
Parameter
Conditions
Typ
(Note 1)
Min
Max
Units
-1.5
V
VI
Input Clamp Voltage
VOH
High Level Output
Voltage
= Min, II = -18 mA
Vee = Min, 10H = Max
VIL = Max, VIH = Min
Low Level Output
Voltage
Vee = Min, 10L = Max
VIL = Max, VIH = Min
DM54
0.25
0.4
DM74
0.35
0.5
= 4 mA, Vee = Min
Vee = Max, VI = 7V
DM74
0.25
0.4
VOL
Vee
10L
II
Input Current @ Max
Input Voltage
IIH
High Level Input Current
Vee
IlL
Low Level Input Current
Vee
los
Short Circuit
Output Current
Vee
Max
(Note 2)
Supply Current
Vee
Icc
Note 1: All typical. are at Vee
=
=
=
Max, VI
Max, VI
=
=
=
DM54
2.5
3.4
DM74
2.7
3.4
V
0.1
V
mA
2.7V
20
p.A
O.4V
-0.4
mA
DM54
-20
-100
DM74
-20
-100
14
9
Max (Note 3)
mA
mA
= 5V, TA = 25·C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one .econd.
Note 3: lee Is measured with all outputs open and all input. grounded.
Switching Characteristics
at Vee
=
5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
RL
=
2k!l
Parameter
From (Input)
To (Output)
tpLH
Propagation Delay Time
Low to High Level Output
Data to
Output
30
35
ns
tpHL
Propagation Delay Time
High to Low Level Output
Data to
Output
30
35
ns
tpLH
Propagation Delay Time
Low to High Level Output
Strobe to
Output
20
25
ns
tpHL
Propagation Delay Time
High to Low Level Output
Strobe to
Output
25
35
ns
Symbol
CL
Min
2-165
=
15pF
Max
CL
Min
=
50pF
Units
Max
fII
Function Table
Inputs
Outputs
G1
G2
D
C
B
A
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
X
X
X
X
X
X
X
X
X
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
= High Level, L = Low Level, X
X
X
X
= Don't Care
2·166
Ii)
....
•
Ii)
....
~NatiOnal
U1
U1
Semiconductor
U1
54LS 155/DM54LS 155/DM74LS 155,
54LS 156/DM54LS 156/DM7 4LS 156
Dual 2-Line to 4-Line Decoders/Demultiplexers
en
General Description
Features
These TIL circuits feature dual 1-line-to-4-line demultiplexers with individual strobes and common binary-address inputs in a single 16-pin package. When both sections are
enabled by the strobes, the common address inputs sequentially select and route associated input data to the appropriate output of each section. The individual strobes permit activating or inhibiting each of the 4-bit sections as desired. Data applied to input C1 is inverted at its outputs and
data applied at C2 is true through its outputs. The inverter
following the C1 data input permits use as a 3-to-B-line decoder, or 1-to-B-line demultiplexer, without external gating.
Input clamping diodes are provided on these circuits to minimize transmission-line effects and simplify system design.
• Applications:
Dual 2-to-4-line decoder
Dual 1-to-4-line demultiplexer
3-to-B-line decoder
1-to-B-line demultiplexer
• Individual strobes simplify cascading for decoding or
demultiplexing larger words
• Input clamping diodes simplify system design
• Choice of outputs:
Totem-pole (LS155)
Open-collector (LS156)
• Alternate Military/Aerospace device (54LS155/156) is
available. Contact a National Semiconductor Sales Office/Distributor for specifications.
Connection Diagram and Function Tables
Dual-In-Llne Package
DATA
C2
vcc
STROBE
G2
SELECT
INPUT
~~
~~ ~
DATA
Cl
1
B
lY3
Ii
lY2
A
B
5
4
\
2YO
1,0 19
11
,G2 ~2
A
Order Number 54LS155DMQB, 54LS155FMQB,
54LS155LMQB, DM54LS155J, DM54LS155W,
DM74LS155M, DM74LS155N, 54LS156DMQB,
54LS156FMQB, DM54LS156J, DM54LS156W,
DM74LS156M or DM74LS156N
See NS Package Number E20A, J16A,
M16A, N16E or W16A
,
2Yl
2Y2
12
101 Cl
13
STROBE SELECT
Gl
INPUT
B
.
i'3
~'ijf~
\2
OUTPUTS
2Y3
1,6 \,5 \,4
l'
.
A
A
6
I
2-Llne-to-4-Llne Decoder or
1-Llne-to-4-Llne Demultiplexer
I
Inputs
Select
7
lVI
lVO
.
Gl:
OUTPUTS
TL/F/6395-1
3-Llne-to-8-Llne Decoder or
1-Llne-to-8-Llne Demultiplexer
Inputs
Select
Ct B A
G:f;
X XX
H
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
L L
L H
H L
H H
L L
L H
H L
HH
(1)
(2)
(3)
(4)
A
G1
C1
1YO
1Y1
1Y2
1Y3
X
X
X
L
L
H
H
L
H
L
H
H
L
L
L
L
X
X
X
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
L
Inputs
(5)
(6)
Select
(7)
2YO 2Y1 2Y2 2Y3 1YO 1Y1 1Y2 1Y3
H
L
H
H
H
H
H
H
H
Data
B
Outputs
Strobe
(0)
Or Data
Outputs
Strobe
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
Data
B
A
G2
C2
2YO
2Y1
2Y2
2Y3
X
X
L
H
L
H
H
L
L
L
L
X
L
L
H
H
X
X
X
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
L
L
L
L
H
tC = inputs Cl and C2 connected together
;G = inputs Gl and G2 connected together
H = high level, L = low level, X = don't care
2-167
PI
Outputs
Strobe
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
- 55·C to + 125·C
DM54LS and 54LS
DM74LS
O·Cto +700C
Storage Temperature Range
- 65·C to + 150·C
Recommended Operating Conditions
Symbol
DM74LS155
DM54LS155
Parameter
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
0.7
0.8
V
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
VOH
High Level Output Current
-0.4
-0.4
mA
10L
Low Level Output Current
4
8
mA
TA
Free Air Operating Temperature
70
·C
Max
Units
-1.5
V
2
2
-55
125
V
0
'LS155 Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 1)
VI
Input Clamp Voltage
Vee = Min,ll = -18 mA
VOH
High Level Output
Voltage
Vee = Min,lOH = Max
VIL = Max, VIH = Min
DM54
2.5
3.4
DM74
2.7
3.4
Low Level Output
Voltage
Vee = Min, 10L = Max
VIL = Max, VIH = Min
DM54
0.25
0.4
DM74
0.35
0.5
10L = 4 mA, Vee = Min
DM74
0.25
0.4
VOL
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 7V
IIH
High Level Input Current
V
V
0.1
mA
Vee = Max, VI = 2.7V
20
p.A
-0.36
mA
IlL
Low Level Input Current
Vee = Max, VI = 0.4V
los
Short Circuit
Output Current
Vee = Max
(Note 2)
DM54
-20
-100
DM74
-20
-100
Supply Current
Vee = Max (Note 3)
typlcals are at Vet:. = 5V, TA = 25" C.
Nota 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: let:. Is measured with all outputs open, A,B, and C1 Inputs at 4.5V, and C2, G1, and G2 Inputs grounded.
Icc
Note 1: All
2-168
6.1
10
mA
mA
'LS155 Switching Characteristics
at Vee
=
5V and T A
=
Symbol
25·C (See Section 1 for Test Waveforms and Output Load)
RL
From (Input)
To (Output)
Parameter
CL
=
= 2kn
15pF
Min
CL
Max
=
Units
50pF
Min
Max
tpLH
Propagation Delay Time
Low to High Level Output
A,B,C2,G1
orG2 to Y
18
22
ns
tpHL
Propagation Delay Time
High to Low Level Output
A,B,C2,G1
orG2toY
27
35
ns
tpLH
Propagation Delay Time
Low to High Level Output
AorB
toY
18
24
ns
tpHL
Propagation Delay Time
High to Low Level Output
AorB
toY
27
35
ns
tpLH
Propagation Delay Time
Low to High Level Output
C1
toY
20
24
ns
tpHL
Propagation Delay Time
High to Low Level Output
C1
toY
27
35
ns
Recommended Operating Conditions
Symbol
DM54LS156
Parameter
DM74LS156
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
V
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
0.7
0.8
VOH
High Level Output Voltage
5.5
5.5
V
IOL
Low Level Output Current
4
8
mA
TA
Free Air Operating Temperature
70
·C
Max
Units
-1.5
V
100
/LA
2
2
-55
125
V
0
'LS156 Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
VI
Input Clamp Voltage
leEx
High Level Output
Current
VOL
Low Level Output
Voltage
Conditions
= Min, II = -18 mA
Vee = Min, Vo = 5.5V
VIL = Max, VIH = Min
Vee = Min, IOL = Max
VIL = Max, VIH = Min
Typ
(Note 1)
Vee
= 4 mA, Vee = Min
Vee = Max, VI = 7V
IOL
II
Input Current @ Max
Input Voltage
IIH
High Level Input Current
IlL
Low Level Input Current
Vee
Icc
Supply Current
Vee
Note 1: All typical. are at Vee
Min
Vee
=
=
=
Max, VI
Max, VI
=
=
DM54
0.25
0.4
DM74
0.35
0.5
0.25
0.4
DM74
V
0.1
rnA
2.7V
20
/LA
O.4V
-0.36
mA
10
mA
Max (Note 2)
= 5V. TA = 25' C.
Note 2: lee i. measured wHh all outputs open. A. B. and Cl inputs at 4.5V. and C2. Gl. and G2 grounded.
2-169
6.1
'II
'LS156 Switching Characteristics
at Vee
=
5V and TA
=
25°C (See Section 1 for Test Waveforms and Output Load)
RL
=
2kO
Parameter
From (Input)
To (Output)
tpLH
Propagation Delay Time
Low to High Level Output
A,B,C2,G1
orG2toY
28
53
ns
tpHL
Propagation Delay Time
High to Low Level Output
A,B,C2,G1
orG2toY
33
43
ns
tPLH
Propagation Delay Time
Low to High Level Output
AorB
toY
28
53
ns
tpHL
Propagation Delay Time
High to Low Level Output
AorB
toY
33
43
ns
tpLH
Propagation Delay Time
Low to High Level Output
C1
toY
28
53
ns
tpHL
Propagation Delay Time
High to Low Level Output
C1
toY
34
43
ns
Symbol
CL
Min
=
15pF
CL
Max
Min
=
50pF
Max
Logic Diagram
STROBE (2)
~OUTPUT
G'~
OATA (1)
1YO
~OUTPUT
lYl
Cl
SELECT (3)
B
1
~OUTPUT
1Y2
~OUTPUT
lY3
SELECT (13)
A
1 =t>-
~OUTPUT
2YO
~OUTPUT
2Vl
DATA (15)
C2
r-- ~OUTPUT
STROBE (14)
G2
~)OUTPUT
2Y2
2V3
TLlF/6395-2
2-170
Units
&;
....
~National
~
•
&;
....
~ Semiconductor
UI
CD
54LS 157/DM54LS 157/DM74LS 157,
54LS 158/DM54LS 158/DM74LS 158
Quad 2-Line to 1-Line Data Selectors/Multiplexers
General Description
Features
These data selectors/multiplexers contain inverters and
drivers to supply full on-chip data selection to the four output gates. A separate strobe input is provided. A 4-bit word
is selected from one of two sources and is routed to the four
outputs. The LS157 presents true data whereas the LS158
presents inverted data to minimize propagation delay time.
II Buffered inputs and outputs
Applications
II Expand any data input point
II Multiplex dual data buses
II Typical Propagation Time
LS157 9 ns
LS158 7 ns
III Typical Power Dissipation
LS157 49 mW
LS158 24 mW
II Alternate
Military/Aerospace
device
(54LS157,
54LS158) is available. Contact a National Semiconductor Sales Office/Distributor for specifications.
II Generate four functions of two variables (one variable
is common)
II Source programmable counters
Connection Diagrams
Dual-In-Llne Package
STROBE
INPUTS
OUTPUT
Dual-In-Llne Package
INPUTS
STROBE
OUTPUT
1~6
15
14
2
13
12
6
5
4
S
~
VI
SELECT
INPUTS
OUTPUT
11
A2
B2
10
16
9
.1
7
V2
'IiiPliiS' OUTPUT
INPUTS
8
GNO
15
14
INPUTS
OUTPUT
12
11
10
12345
8
7J.~
s
~
SELECT
INPUTS
13
9
VI
A2
B2
va GND
OUTPUT ~ OUTPUT
TL/F/8398-2
TL/F/8396-1
Order Number 54LS158DMQB, 54LS158FMQB,
54LS158LMQB, DM54LS158J, DM54LS158W,
DM74LS158M or DM74LS158N
See NS Package Number E20A, J16A,
M16A, N16E or W16A
Order Number 54LS157DMQB, 54LS157FMQB,
54LS157LMQB, DM54LS157J, DM54LS157W,
DM74LS157M or DM74LS157N
See NS Package Number E20A, J16A,
M16A, N16E or W16A
Function Table
Inputs
H
OUTPUT
VCTCG~Y4~Y3
VCCG~Y4~Y3
OutputY
Strobe
Select
A
B
LS157
LS158
H
X
X
L
L
L
L
L
L
L
H
H
X
X
L
H
L
L
H
L
H
H
H
X
X
X
= High Level, L = Low Level, X =
Don't Care
2-171
H
L
H
L
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaran·
tBBd. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table ara not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace apeclfled devices are required..
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
- 55'C to + 125'C
DM54LS and 54LS
DM74LS
O'Cto +70"C
Storage Temperature Range
-65°C to + 150'C
Recommended Operating Conditions
Symbol
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
10H
High Level Output Current
DM74LS157
DM54LS157
Parameter
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
0.7
0.8
V
-0.4
-0.4
mA
2
2
10L
Low Level Output Current
TA
Free Air Operating Temperature
Units
Min
V
4
-55
125
0
8
mA
70
·C
Max
Units
-1.5
V
'LS157 Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Conditions
Parameter
Min
Typ
(Note 1)
= Min, II = -18 mA
VI
Input Clamp Voltage
Vee
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
VIL = Max, VIH = Min
DM54
2.5
3.4
DM74
2.7
3.4
Low Level Output
Voltage
Vee = Min, 10L = Max
VIL = Max, VIH = Min
DM54
0.25
0.4
DM74
0.35
0.5
= 4 mA, Vee = Min
Vee = Max
DM74
0.25
0.4
VOL
IOL
II
IIH
IlL
los
Icc
Input Current @ Max
Input Voltage
VI
= 7V
V
SorG
0.2
AorB
0.1
High Level Input
Current
Vee = Max
VI = 2.7V
SorG
40
AorB
20
Low Level Input
Current
Vee = Max
VI = O.4V
SorG
-0.8
AorB
-0.4
Short Circuit
Output Current
Vee = Max
(Note 2)
DM54
-20
-100
DM74
-20
-100
Supply Current
Vee
= Max (Note 3)
Note 1: Aillypicals are at Vcc = 5V, TA = 25'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: ICC Is measured w~h 4.5V applied to all inputs and all outputs open.
2·172
9.7
16
V
mA
IJ-A
mA
mA
mA
'LS157 Switching Characteristics
at Vee = 5V and T A = 25'C (See Section 1 for Test Waveforms and Output Load)
Symbol
RL = 2kO
From (Input)
To (Output)
Parameter
CL = 15pF
Min
Units
CL = 50pF
Max
Max
Min
tpLH
Propagation Delay Time
Low to High Level Output
Data
toY
14
18
ns
tpHL
Propagation Delay Time
High to Low Level Output
Data
toY
14
23
ns
tpLH
Propagation Delay Time
Low to High Level Output
Strobe
toY
20
24
ns
tpHL
Propagation Delay Time
High to Low Level Output
Strobe
toY
21
30
ns
tpLH
Propagation Delay Time
Low to High Level Output
Select
toY
23
28
ns
tpHL
Propagation Delay Time
High to Low Level Output
Select
toY
27
32
ns
Recommended Operating Conditions
Symbol
DM74LS158
DM54LS158
Parameter
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
0.7
0.8
V
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
10H
High Level Output Current
-0.4
-0.4
mA
10L
Low Level Output Current
4
8
mA
TA
Free Air Operating Temperature
70
'C
Max
Units
-1.5
V
2
V
2
-55
125
0
'LS158 Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Min
Typ
(Note 1)
DM54
2.5
3.4
DM74
2.7
3.4
Conditions
VI
Input Clamp Voltage
Vee = Min, 11= -18 mA
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
VIL = Max, VIH = Min
Low Level Output
Voltage
Vee = Min, 10L = Max
VIL = Max, VIH = Min
OM 54
0.25
0.4
DM74
0.35
0.5
10L = 4 mA, Vee = Min
DM74
0.25
0.4
Input Current @ Max
Input Voltage
Vee = Max
VI = 7V
SorG
0.2
AorB
0.1
High Level Input
Current
Vee = Max
VI = 2.7V
Low Level Input
Current
Vee = Max
VI = O.4V
Short Circuit
Output Current
Vee = Max
(Note 2)
VOL
II
IIH
IlL
los
SorG
40
AorB
20
SorG
-0.8
AorB
-0.4
OM 54
-20
-100
DM74
-20
-100
Supply Current
Vee = Max (Note 3)
Icc
Note 1: All typlcals are at Vec = 5V, TA = 25'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Nota 3: Icc Is measured with 4.5V applied to all Inputs and all outputs open.
2-173
V
4.8
8
V
mA
/LA
mA
mA
mA
'LS158 Switching Characteristics
at Vee
= 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
From (Input)
To (Output)
RL
CL
= 2kO
= 15pF
Min
CL
Max
= 50pF
Min
Units
Max
tpLH
Propagation Delay Time
Low to High Lavel Output
Data
toY
12
18
ns
tpHL
Propagation Delay Time
High to Low Level Output
Data
toY
12
21
ns
tpLH
Propagation Delay Time
Low to High Level Output
Strobe
toY
17
23
ns
tpHL
Propagation Delay Time
High to Low Level Output
Strobe
toY
18
28
ns
tpLH
Propagation Delay Time
Low to High Level Output
Select
toY
20
24
ns
tpHL
Propagation Delay Time
High to Low Level Output
Select
toY
24
36
ns
Logic Diagrams
LS157
LS158
Al (2)
Al (2)
~Vl
81 (3)
~Vl
81 (3)
-
r-;:::::j
t:::L.
A2(5)
A2(5)
>-l.
~"
(7) V2
82(6)
82(6)
;:::::L
-
A3 (11)
83(10)
A3 (11)
(9) Y3
(9) Y3
B3(10)
c:I
C:::L
A4 (14)
A4 (14)
-
(12) V4
..--
84 (13)
SELECT (1)
i>-
STR08E (15)
e{>-
84 (13)
t:::L.
----
(12) Y4
..--
~
SELECT (1)
i>-
STROBE (15)
:{>--
;:::::L
TL/F/6396-4
TUF/6396-3
2-174
'?JI National
~ Semiconductor
54LS160A/DM74LS160A,54LS162A/DM74LS162A
Synchronous Presettable BCD Decade Counters
General Description
Features
The 'LS160 and 'LS162 are high speed synchronous decade counters operating in the BCD (8421) sequence. They
are synchronously presettable for application in programmable dividers and have two types of Count Enable inputs plus
a Terminal Count output for versatility in forming synchronous multistage counters. The 'LS160 has an asynchronous
Master Reset input that overrides all other inputs and forces
the outputs LOW. The 'LS162 has a Synchronous Reset
input that overrides counting and parallel loading and allows
all outputs to be simultaneously reset on the rising edge of
the clock.
•
•
•
•
Synchronous counting and loading
High speed synchronous expansion
Typical count rate of 35 MHz
Fully edge triggered
Connection Diagram
Dual·in·Line Package
iR- 1
'-'
CP- 2
PO- 3
16 ~Vcc
15 ~TC
14 rOO
13 rOI
12 ~02
Pl- 4
P2- 5
P3- 6
11~03
CEP- 7
10
~CEl
9~PE
GND- 8
TLlF/l0177-1
'MR lor 'LS160
'SF! for 'LS162
Order Number 54LS160ADMQB, 54LS160AFMQB, 54LS160ALMQB,
54LS162ADMQB, 54LS162AFMQB, 54LS162ALMQB, DM74LS160AM,
DM74LS160AN, DM74LS162AM or DM74LS162AN
See NS Package Number E20A, J16A, M16A, N16E or W16A
Pin
Names
CEP
CET
CP
MR (,160)
SR(,162)
PO-P3
PE
00-03
TC
Description
Logic Symbol
Count Enable Parallel Input
Count Enable Trickle Input
Clock Pulse Input (Active Rising Edge)
Asynchronous Master Reset
Input (Active LOW)
Synchronous Reset
Input (Active LOW)
Parallel Data Inputs
Parallel Enable Input
(Active LOW)
Flip-Flop Outputs
Terminal Count Output
l iii i
PE PO PI P2 P3
7-CEP
10- CEl
TC 1--15
2-CP
OR 00 01 02 Q3
l,~ I~ I~
111
TLlF/l0177-2
vcc = Pin 16
GND
2·175
=
'MAlor'LS160
Pin 8 'SA lor 'LS162
Absolute Maximum Ratings
(Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
54LS
- 55'C to + 125'C
DM74lS
O'Cto +70'C
Storage Temperature Range
-65'C to + 150'C
Recommended Operating Conditions
Symbol
54LS160Al162A
Parameter
Vee
Supply Voltage
DM74LS160Al162A
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
0.7
0.8
V
VIH
High level Input Voltage
Vil
low level Input Voltage
2
2
IOH
High level Output Current
-0.4
-0.4
mA
IOl
low level Output Current
4
8
mA
70
'C
-55
125
V
TA
Free Air Operating Temperature
!s(H)
ts(l)
Setup Time, HIGH or lOW
Pn to CP
20
20
20
20
0
ns
th(H)
th(l)
Hold Time, HIGH or lOW
PntoCP
0.0
0.0
0.0
0.0
ns
ts(H)
ts(l)
Setup Time, HIGH or lOW
PEtoCP
20
20
20
20
ns
th(H)
th(l)
Hold Time, HIGH or lOW
PEtoCP
0
0
0
0
ns
!s(H)
!s(l)
Setup Time, HIGH or lOW
CEP, CET or SR to CP
20
20
20
20
ns
th(H)
th(l)
Hold Time, HIGH or lOW
CEP, CET or SR to CP
0
0
0
0
ns
tw(H)
tw(l)
CP Pulse Width,
HIGH or lOW
15
25
15
25
ns
twILl
MR Pulse Width
lOW ('160)
15
15
ns
tree
Recovery Time
MR to CP (,160)
20
20
ns
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 1)
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vee = Min, 11= -18 mA
VOH
High level Output
Voltage
Vee = Min, IOH = Max,
Vil = Max
54lS
2.5
DM74
2.7
low level Output
Voltage
Vee = Min, IOl = Max,
VIH = Min
54lS
0.4
DM74
0.5
IOl = 4 rnA, Vee = Min
DM74
0.4
VOL
Note 1: All typlcals are at Vee = 5V, TA = 25·C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed ana second.
2-176
V
V
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted) (Continued)
Symbol
Parameter
Conditions
Min
Typ
(Note 1)
Max
Units
II
Input Current @ Max
Input Voltage
Vcc = Max, VI
PE, CET Inputs
=
10V Inputs
0.1
0.2
mA
IIH
High Level Input Current
Vcc = Max, VI
PE, CET Inputs
=
2.7V Inputs
20
40
p.A
IlL
Low Level Input Current
Vcc
=
0.4V Inputs
=
Max, VI
54LS
-0.4
DM74
-1.6
mA
-0.8
PE, CET Inputs
mA
Short Circuit
Output Current
Vcc = Max
(Note 2)
ICCH
Supply Current with
Outputs HIGH
Vcc = Max, PE = GND
CP = ....r, Other Inputs = 4.5V
31
mA
ICCL
Supply Current with
Outputs LOW
Vcc
= Max, VIN =
cp=....r
31
mA
los
54LS
-20
-100
DM74
-20
-100
GND
mA
Switching Characteristics Vcc = + 5.0V, T A = + 25°C
Symbol
RL = 2kO
CL = 15pF
Parameter
Min
Units
Max
f max
Maximum Clock Frequency
25
tpLH
tpHL
Propagation Delay
CP to TC
25
21
MHz
ns
tpLH
tpHL
Propagation Delay
CP to an
20
27
ns
tpLH
tpHL
Propagation Delay
CPtoan
24
27
ns
tpLH
tpHL
Propagation Delay
CETtoTC
14
14
ns
tpHL
Propagation Delay
MR to an ('160)
28
ns
Functional Description
The 'LS160 and 'LS162 count modulo-10 in the BCD (8421)
sequence. From state 9 (HLLH) they increment to state 0
(LLLL). The '161 and '163 count modul0-16 binary sequence. From state 15 (HHHH) they increment to state 0
(LLLL). The clock inputs of all flip-flops are driven in parallel
through a clock buffer. Thus all changes of the a outputs
(except due to Master Reset of the 'LS160) occur as aresuit of, and synchronous with, the LOW-to-HIGH transition
of the CP input signal. The circuits have four fundamental
modes of operation, in order of precedence: asynchronous
reset (,LS160), synchronous reset ('LS162), parallel load,
count-up and hold. Five control inputs-Master Reset (MR,
'LS160), Synchronous Reset (SR, 'LS162), Parallel Enable
(PE), Count Enable Parallel (CEP) and Count Enable Trickle
(CET}-determine the mode of operation, as shown in the
Mode Select Table. A LOW signal on MR overrides all other
inputs and asynchronously forces all outputs LOW. A LOW
signal on SR overrides counting and parallel loading and
allows all outputs to go LOW on the next rising edge of CPo
A LOW Signal on PE overrides counting and allows information on the Parallel Data (P n) inputs to be loaded into the
flip-flops on the next rising edge of CPo With PE and MR
('LS160) or SR ('LS162) HIGH, CEP and CET permit counting when both are HIGH. Conversely, a LOW signal on either CEP or CET inhibits counting.
The 'LS160A and 'LS162A use D-type edge-triggered flipflops and changing the SR, PE, CEP and CET inputs when
the CP is in either state does not cause errors, provided that
the recommended setup and hold times, with respect to the
rising edge of CP, are observed.
2-177
Functional Description (Continued)
The Terminal Count (TC) output is HIGH when CET is HIGH
and the counter is in its maximum count state (9 for the
decade counters, 15 for the binary counters). To implement
synchronous multistage counters, the TC outputs can be
used with the CEP and CET inputs in two different ways.
Mode Select Table
These two schemes are shown in the 9310 data sheet. The
TC output is subject to decoding spikes due to internal race
conditions and is therefore not recommended for use as a
clock or asynchronous reset for flip-flops, counters or registers. In the decade counters of the 'LS160, 'LS162, the TC
output is fully decoded and can only be HIGH in state 9.
'SR
PE
CET
CEP
L
H
H
H
H
X
X
X
X
X
H
L
H
X
L
L
H
H
H
X
'For the 'LSl62
H = HIGH Voltage Level
L = LOW Vollage Level
X = Immatertal
LOGIC EOUATIONS:
Count Enable = CEP - CET - PE
TC = 00-01 - 02-03 -CET
State Diagrams
'LS160, 'LS162
TUF/l0177-5
2-178
Action on the Rising
Clock Edge (.../" )
RESET (Clear)
LOAD (Pn - . On)
COUNT (Increment)
NO CHANGE (Hold)
NO CHANGE (Hold)
Logic Diagrams
'LS160
PO
P2
P1
P3
~--~'~~~----~~----------~+--------------1;--------------'
CEP
co-L~~------ti1t-------r1r1Hr-------t-t-1i-------1r1-'
TC
CP
Wi
00
01
02
03
TUF/l0177-3
'LS162
PO
P2
P1
P3
~
C£P
co
TC
cp--~~-JL-1-----1---11~;:::~~::::~::~::::l:::::li::~::=1F=::::t=gr~
00
Q2
01
03
TUF/l0177-4
2-179
~National
~ Semiconductor
54LS 161 A/DM54LS 161 A/DM7 4LS 161 A,
54LS 163A/DM54LS 163A/DM74LS 163A
Synchronous 4-Bit Binary Counters
General Description
These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting
designs. The LS161A and LS163A are 4-bit binary counters.
The carry output is decoded by means of a NOR gate, thus
preventing spikes during the normal counting mode of operation. Synchronous operation is provided by having all flipflops clocked simultaneously so that the outputs change coincident with each other when so instructed by the countenable inputs and internal gating. This mode of operation
eliminates the output counting spikes which are normally
associated with asynchronous (ripple clock) counters. A
buffered clock input triggers the four flip-flops on the rising
(positive-going) edge of the clock input waveform.
These counters are fully programmable; that is, the outputs
may be preset to either level. As presetting is synchronous,
setting up a low level at the load input disables the counter
and causes the outputs to agree with the setup data after
the next clock pulse, regardless of the levels of the enable
input. Low-to-high transitions at the load input are perfectly
acceptable, regardless of the logic levels on the clock or
enable inputs. The clear function for the LS161A is asynchronous; and a low level at the clear input sets all four of
the flip-flop outputs low, regardless of the levels of clock,
load, or enable inputs. The clear function for the LS163A is
synchronous; and a low level at the clear inputs sets all four
of the flip-flop outputs low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous
clear allows the count length to be modified easily, as decoding the maximum count desired can be accomplished
with one external NAND gate. The gate output is connected
to the clear input to synchronously clear the counter to all
low outputs.
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional
gating. Instrumental in accomplishing this function are two
count-enable inputs and a ripple carry output.
must be high to count,
Both count-enable inputs (P arid
and input T is fed forward to enable the ripple carry output.
The ripple carry output thus enabled will produce a high-level output pulse with a duration approximately equal to the
high-level portion of the QA output. This high-level overflow
ripple carry pulse can be used to enable successive cascaded stages. High-to-Iow level transitions at the enable P or T
inputs may occur, regardless of the logiC level of the clock.
n
These counters feature a fully independent clock circuit.
Changes made to control inputs (enable P or T or load) that
will modify the operating mode have no effect until clocking
occurs. The function of the counter (whether enabled, disabled, loading, or counting) will be dictated solely by the
conditions meeting the stable set-up and hold times.
Features
•
•
•
•
•
•
•
•
•
•
Synchronously programmable
Internal look-ahead for fast counting
Carry output for n-bit cascading
Synchronous counting
Load control line
Diode-clamped inputs
Typical propagation time, clock to Q output 14 ns
Typical clock frequency 32 MHz
Typical power dissipation 93 mW
Alternate
Military/Aerospace
device
(54LS161,
54LS163) is available. Contact a National Semiconductor Sales Office/Distributor for speclficaitons.
Connection Diagram
Dual-In-Llne Package
RIPPLE
CARRY •
]:
OUTPUTS
•
OUJ:~T 1:4
1~2
I I I I I
j,3
Order Numbers 54LS161ADMQB, 54LS161AFMQB,
54LS161ALMQB, 54LS163ADMQB, 54LS163AFMQB,
54LS163ALMQB, DM54LS161AJ, DM54LS161AW,
DM54LS163AJ, DM54LS163AW, DM74LS161AM,
DM74LS161AN, DM74LS163AM or DM74LS163AN
See NS Package Number E20A, J16A,
M16A, N16E or W16A
o
I I I I I
1
2
r r r 1r
6
CLEAR CLOCK • A B C
X
D EN~BLE GND
DATA iNPUTS
TLlF/6397-1
2-180
Iii
...
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and speclflcatlons_
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
DM54LS and 54LS
-55'C to + 125'C
DM74LS
O'Cto +70'C
Storage Temperature Range
-65'Cto + 150'C
Recommended Operating Conditions
Symbol
DM54LS161A
Parameter
DM74LS161A
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
0.7
0.8
V
mA
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
IOH
High Level Output Current
-0.4
-0.4
IOL
Low Level Output Current
4
8
mA
feLK
Clock Frequency (Note 1)
0
25
0
25
MHz
Clock Frequency (Note 2)
0
20
0
20
MHz
Pulse Width
(Note 1)
Clock
20
6
20
6
Clear
20
9
20
9
Pulse Width
(Note 2)
Clock
25
25
Clear
25
25
Setup Time
(Note 1)
Data
20
8
20
8
Enable P
25
17
25
17
Load
25
15
25
15
tw
tsu
Setup Time
(Note 2)
Hold Time
(Note 1)
tH
Hold Time
(Note 2)
tREL
2
Data
20
20
EnableP
30
30
Load
30
30
ns
ns
ns
ns
Data
0
-3
0
-3
Others
0
-3
0
-3
ns
Data
5
5
Others
5
5
Clear Release Time (Note 1)
20
20
ns
Clear Release Time (Note 2)
25
25
ns
Free Air Operating Temperature
TA
V
2
-55
Note 1: CL
~
15 pF, RL
~
2 kn, TA
~
25"C and Vee
~
5.5V.
Note 2: CL
~
50 pF, RL
~
2 kn, TA
~
25'C and Vee
~
5.5V.
2-181
125
0
ns
70
'C
...
•
Iii
...en
en
:I>
~
'LS161 Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Min
Conditions
Typ
(Note 1)
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vee = Min, 11= -18 mA
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
Vil = Max, VIH = Min
DM54
2.5
3.4
DM74
2.7
3.4
Low Level Output
Voltage
Vee = Min, 10l = Max
Vil = Max, VIH = Min
DM54
0.25
0.4
DM74
0.35
0.5
10l = 4 mA, Vee = Min
DM74
0.25
0.4
Input Current @ Max
Input Voltage
Vee = Max
VI = 7V
EnableT
0.2
Clock
0.2
Load
0.2
Others
0.1
EnableT
40
Clock
40
Load
40
Others
20
VOL
II
IIH
IlL
los
ICCH
High Level Input
Current
Low Level Input
Current
Vee = Max
VI = 2.7V
Vee = Max
VI = O.4V
Short Circuit
Output Current
Vee = Max
(Note 2)
Supply Current with
Outputs High
Vee = Max
(Note 3)
V
EnableT
-0.8
Clock
-0.8
Load
-0.8
Others
-0.4
DM54
-20
-100
DM74
-20
-100
18
31
Supply Current with
Vee = Max
19
Outputs Low
(Note 4)
Note 1: All typical. are at Voc = 5V, TA = 25'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: lOCH I. measured with the load high, then again with the load low, with all other inputs high and all outputs open.
Note 4: Icel is measured whh the clock Input high, then again with the clock Input low, with all othsr Inputs low and all outputs open.
ICCl
32
V
mA
p.A
mA
mA
mA
mA
'LS161 Switching Characteristics
at Vee = 5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
From (Input)
To (Output)
RL = 2kn
CL = 15pF
Min
Max
25
CL = 50pF
Min
Units
Max
fMAX
Maximum Clock Frequency
tplH
Propagation Delay Time
Low to High Level Output
Clock to
Ripple Carry
24
30
ns
tpHl
Propagation Delay Time
High to Low Level Output
Clock to
Ripple Carry
30
38
ns
tplH
Propagation Delay Time
Low to High Level Output
Clock to Any Q
(Load High)
22
27
ns
tpHl
Propagation Delay Time
High to Low Level Output
Clock to Any Q
(Load High)
27
38
ns
2-182
20
MHz
'LS161 Switching Characteristics
at Vee = 5V and T A = 25'C (See Section 1 for Test Waveforms and Output Load) (Continued)
Symbol
RL = 2kO
From (Input)
To (Output)
Parameter
CL = 15pF
Min
CL=50pF
Max
Min
Units
Max
tpLH
Propagation Delay Time
Low to High Level Output
Clock to Any Q
(Load Low)
24
30
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clock to Any Q
(Load Low)
29
38
ns
tpLH
Propagation Delay Time
Low to High Level Output
EnableTto
Ripple Carry
18
27
ns
tpHL
Propagation Delay Time
High to Low Level Output
EnableTto
Ripple Carry
15
27
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clear to
AnyQ
35
45
ns
Recommended Operating Conditions
Symbol
Vcc
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
IOH
IOL
fOLK
tw
Not. 1: OL
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
2
V
V
V
-0.4
-0.4
mA
Low Level Output Current
4
8
mA
Clock Frequency (Note 1)
0
25
0
25
MHz
Clock Frequency (Note 2)
0
20
0
20
MHz
Pulse Width
(Note 1)
Clock
20
6
20
6
Clear
20
9
20
9
Setup Time
(Note 1)
Hold Time
(Note 1)
Clock
25
25
Clear
25
25
Data
20
8
20
8
EnableP
25
17
25
17
15
25
15
Load
25
20
20
EnableP
30
30
Load
30
30
Data
0
-3
0
-3
Others
0
-3
0
-3
Data
5
5
Others
5
5
Clear Release TIme (Note 1)
20
20
25
Free Air Operating Temperature
-55
= 15 pF. RL = 2 kO. TA = 2S"0 and Vee = SV.
Not. 2: CL = 50 pF. RL = 2 kO. TA
= 2S"0 and Vee
= 5V.
2-183
ns
ns
Data
Clear Release Time (Note 2)
TA
Max
High Level Output Current
Hold Time
(Note 2)
tREL
Units
Nom
0.8
Setup Time
(Note 2)
tH
DM74LS163A
Min
0.7
Pulse Width
(Note 2)
tsu
DM54LS163A
Parameter
ns
ns
ns
ns
ns
25
125
0
ns
70
'C
•
'LS163 Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Min
Typ
(Note 1)
2.5
3.4
DM74
2.7
3.4
Conditions
Max
Units
-1.5
V
VI
Input Clamp Voltage
VOH
High Level Output
Voltage
Vcc = Min, 10H = Max
VIL = Max, VIH = Min
DM54
Low Level Output
Voltage
Vcc = Min, 10L = Max
VIL = Max, VIH = Min
DM54
0.25
0.4
DM74
0.35
0.5
10L = 4 mA, Vcc = Min
DM74
0.25
0.4
Vcc = Max
VI = 7V
EnableT
0.2
Clock, Clear
0.2
Load
0.2
Others
0.1
EnableT
40
Load
40
Clock, Clear
40
VOL
II
IIH
Input Current @ Max
Input Voltage
High Level Input
Current
Vee = Min, 11= -18 mA
Vcc = Max
VI = 2.7V
V
Others
IlL
Low Level Input
Current
Vee = Max
VI = 0.4V
los
ICCH
Vec = Max
(Note 2)
Supply Current with
Outputs High
Vee = Max
(Note 3)
mA
p.A
20
EnableT
-0.8
Clock, Clear
-0.8
Load
-0.8
mA
-0.4
Others
Short Circuit
Output Current
V
DM54
-20
-100
DM74
-20
-100
18
31
Supply Current with
Vcc = Max
18
Outputs Low
(Note 4)
NOle ,: All typlcals are at vee = 5V, TA = 25'C.
Nole 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
NOle 3: lOCH Is measured w~h the load high, then again w~h the load low, w~h all other inputs high and all outputs open.
Nole 4: leel is measured with the clock input high, then again with the clock Input low, with all other inputs low and all outputs open.
ICCL
32
mA
mA
mA
'LS163 Switching Characteristics
at Vcc = 5V and TA = 25"C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
From (Input)
To (Output)
RL = 2kO
CL = 15pF
Min
Max
25
CL = 50pF
Min
Units
Max
fMAX
Maximum Clock Frequency
tpLH
Propagation Delay Time
Low to High Level Output
Clock to
Ripple Carry
24
30
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clock to
Ripple Carry
30
38
ns
tpLH
Propagation Delay Time
Low to High Level Output
Clock to Any Q
(Load High)
22
27
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clock to Any Q
(Load High)
27
38
ns
2-184
20
MHz
r-
en
....
'LS163 Switching Characteristics
en
....
l>
at Vee = 5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load) (Continued)
Symbol
•
RL = 2kO
From (Input)
To (Output)
Parameter
CL = 15pF
Min
Max
CL = 50pF
Min
Units
Co)
Max
l>
tpLH
Propagation Delay Time
Low to High Level Output
Clock to Any Q
(Load Low)
24
30
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clock to Any Q
(Load Low)
29
38
ns
tpLH
Propagation Delay Time
Low to High Level Output
EnableTto
Ripple Carry
18
27
ns
tpHL
Propagation Delay Time
High to Low Level Output
EnableTto
Ripple Carry
15
27
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clear to Any Q
(Note 1)
35
45
ns
Note 1: Tha propagation dalay claar to output is maasurad from tha clock input transition.
Logic Diagram
LS163A
(2)
CLOCK
(3)
DATA A - - - - - - - - '
(7)
ENABLE P --[;:><>-..1
(10)
ENABLE T ---C»--.......----,
(5)
DATA
c -------1t=tT=rr11~=l:J
(6)
DAmD-------1rCf~FF~~E=~J
TL/F/6397-2
The LS161A is similar, however, the clear buffer is connected directly to the flip flops.
2-185
In....
en
Parameter Measurement Information
Switching Time Waveforms
CLOCK
INPUT
OV
"'lH
(MEASURE AT .... , I
OUTPUT VoH--t--+I---+,""
a..
OUTPUT
VOL
VOH
lie VOL
VOH
OUTPUT
lie VOl
OUTPUT
00
Vo.
VOL
VOH
RIPPLE
CARRY
OUTPUT VOL
TLlF/6397-3
Nota A: The Input pulses are supplied by generatora having the !ollowlng characteristics: PRR ,; 1 MHz. duty cycle ,; 50%, Zotrr:= son, t,.,; 10 ns,t, ,; 10 ns.
V81Y PRR to meesure !MAX.
Note B: Outputs Qo and carry are tested at "'+16 where", Is the blt time when all outputs are low.
Note C: VREF = 1.5V.
Switching Time Waveforms
3.IV
CI.OClCINPUT
LS181A
CLEAR
'NPUT
LOAD
INPUT
DATA 'NPUTS
A.B.C.AND D
VAEF
OV
••OV
twCClOCKI
OV
3.0V
IooTUP
VREF
OV
3.0V
DY
QQUTPUTS VOH
LS181A
VOL
3.0V
ENABLEPDR
ENABLET
OY
VOH
CARRY
VOL
CLQCIC INPUT 3.DY
LSI83A
OV--
aOUTPUTS
VOH
LSI83A
VOL
TLlF/6397-4
Note A: Tha input pulses are supplied by generators having the following characteristics: PRR ,; 1 MHz, duly cycle'; SO%, Zour ::::
PRR to measure !MAX.
Note B: Enable P and enable T setup times are measured at", +0Nota C: VREF = l.aV.
2-186
son, t,. ,; 6 ns, I, ,; 6 ns. V81Y
Timing Diagram
LS161A, LS163A Synchronous Binary Counters
Typical Clear, Preset, Count and Inhibit Sequences
CLEAR - - - - - ,
LSI61A
CLEAR - - -...
LS163A
LOAD
r--------------
r--------------
A
B
-+----'" _____________ _
DATA
C
r---+---., -- -- -- -- -- - - - - - - - - -
o
r---+--"T--------------
[
INPUTS
CLOCK
LS161A
L _____________ _
L _____________ _
----+.,
CLOCK - - - ,
LS163A
ENABLEP
ENABLE T
----1---1-1
---+--l-I
+_-+_-+..,-__--'
RIPPLE CARRV _ _ _ _
OUTPUT
12
13
14
15
1-----
COUNT-----II----INHIBIT ----~
CLEAR PRESET
TL/F/6397-5
Sequence:
(1) Clear outputs 10 zero
(2) Presello binary !welve
(3) Count to thirteen, fourteen, fifteen, zero, one, and two
(4) InhibH
•
2·187
...
CD
§ ~National
~ Semiconductor
54LS 164/DM54LS 164/DM74LS 164
a-Bit Serialln/Paraliel Out Shift Registers
General Description
Features
These 8-bit shift registers feature gated serial inputs and an
asynchronous clear. A low logic level at either input inhibits
entry of the new data, and resets the first flip-flop to the low
level at the next clock pulse, thus providing complete control over incoming data. A high logic level on either input
enables the other input, which will then determine the state
of the first flip-flop. Data at the serial inputs may be changed
while the clock is high or low, but only information meeting
the setup and hold time requirements will be entered. Clocking occurs on the low-to-high level transition of the clock
input. All inputs are diode-clamped to minimize transmission-line effects.
•
•
•
•
•
•
Connection Diagram
Function Table
Gated (enable/disable) serial inputs
Fully buffered clock and serial inputs
Asynchronous clear
Typical clock frequency 36 MHz
Typical power dissipation 80 mW
Alternate Military/Aerospace device (54LS164) is available. Contact a National Semiconductor Sales Office/
Distributor for specifications.
Dual-ln-L1ne Package
VCC
114
OH
OG
13
OF
12
OE
11
10
outputs
Inputs
OUTPUTS
CLEAR CLOCK
9
8
r-
Clear
Clock
A
B
OA
OB
L
H
H
H
H
X
X
X
X
X
L
L
aAO
H
L
H
aBO
aAn
aAn
aAn
L
t
t
t
x
X
L
H
L
L
..'
...
...
...
...
...
OH
L
aHO
aGn
aGn
aGn
= High Level (steady state), L = Low Level (steady state)
= Don't Care (any Input, including trans~ions)
t = Transition from low to high level
H
X
1
3
2
~
4
!lA
SERIAL INPUTS
OB
5
6
17
Oc
09
GND
OAO, 0BO, OHO = The level of OA, OB, or OH, respactively, before the
Indicatad steady·state Input conditions were established.
OAn, OGn = The level 01 OA or O(l before the most recent
the clock; Indicates a one-bit shift.
t
transition of
OUTPUTS
TL/F/6396-1
Order Number 54LS164DMOB, 54LS164FMOB,
54LS164LMOB, DM54LS164J, DM54LS164W,
DM74LS164M or DM74LS164N
See NS Package Number E20A,
J14A, M14A, N14A or W14B
Logic Diagram
CLEA.~(·~I----~~O---'-------'-----~~----~~-----1-------'------~------~
CLOC.~(·~I----~~'---+---'---+---~--~-4~~~~~-4---1---+---'--~--'
OUTPUTS
TLiF/6398-2
2-188
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" tables will de·
fine the conditions for actual device operation.
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
DM54LS and 54LS
-55'Cto +125'C
DM74LS
O'Cto +70'C
Storage Temperature Range
-65'Cto +150'C
Recommended Operating Conditions
Symbol
DM54LS164
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
10H
High Level Output Current
DM74LS164
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
Low Level Output Current
felK
Clock Frequency (Note 4)
tw
Pulse Width
(Note 4)
V
0.7
0.8
V
-0.4
-0.4
rnA
4
0
25
0
L Clock
20
20
Clear
20
20
I
V
2
2
10l
Units
Min
8
rnA
25
MHz
ns
tsu
Data Setup Time (Note 4)
17
17
ns
tH
Data Hold Time (Note 4)
5
5
ns
tREl
Clear Release Time (Note 4)
TA
Free Air Operating Temperature
30
30
-55
125
ns
0
70
'C
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
VI
Input Clamp Voltage
VOH
High Level Output
Voltage
Low Level Output
Voltage
VOL
= Min, II = -18 rnA
= Min, 10H = Max
Vil = Max, VIH = Min
Vee = Min, 10l = Max
Vil = Max, VIH = Min
= 4 rnA, Vee = Min
Vee = Max, VI = 7V
II
Input Current @ Max
Input Voltage
IIH
High Level Input Current
Vee
III
Low Level Input Current
Vee
los
Short Circuit
Output Current
Vee
Max
(Note 2)
Note
Supply Current
1: All typical. are at Vcc = SV, TA = 25"C.
Typ
(Note 1)
DM54
2.5
3.4
DM74
2.7
3.4
Vee
Vee
10l
Icc
Min
Conditions
Vee
=
=
=
=
Max, VI
Max, VI
=
=
Max
Units
-1.5
V
V
DM54
0.25
0.4
DM74
0.35
0.5
DM74
0.25
0.4
0.1
V
mA
2.7V
20
p.A
O.4V
-0.4
rnA
DM54
-20
-100
DM74
-20
-100
Max (Note 3)
16
27
rnA
rnA
Note 2: Not more than one output should be shorted at a Ume, and the duration should not exceed one second.
Note 3:
input.
Icc is measured with all outputs open, the SERIAL input grounded, the CLOCK input at 2.4V, and a momentary ground, then 4.SV, applied to the CLEAR
Nole 4: TA
= 2S'C and Vee = SV.
2-189
Switching Characteristics
Symbol
at Vcc = 5V and T A = 25°C (See Section 1 for Test Waveforms and Output Load)
RL = 2 kO
From (Input)
To (Output)
Parameter
CL = 15pF
Min
Max
CL = 50pF
Min
Units
Max
fMAX
Maximum Clock Frequency
tpLH
Propagation Delay Time
Low to High Level Output
Clock to
Output
25
MHz
27
30
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clock to
Output
32
40
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clear to
Output
36
45
ns
Timing Diagram
CLEARLJ
~~I'
LJ
I
I
INPUTS
I
S
~r
CLOCK
OA - - - ,
I
Os - - - ,
---
I
I
Oc : : : '
---,
OD
-----,
OUTPUTS
I
OE ___ I
---,
OF ___ I
OG
:::1
---,
"L.JL. I
L..ILI
I
OH ___ I
4-L
I
flI
•
CLEAR
CLEAR
TLlF/639B-3
2·190
~National
~ Semiconductor
54LS 165/DM7 4LS 165 a-Bit Parallel
In/Serial Output Shift Registers
General Description
This device is an 8-bit serial shift register which shifts data in
the direction of QA toward QH when clocked. Parallel-in access is made available by eight individual direct data inputs,
which are enabled by a low level at the shift/load input.
These registers also feature gated clock inputs and complementary outputs from the eighth bit.
Clocking is accomplished through a 2-input NOR gate, permitting one input to be used as a clock-inhibit function. Holding either of the clock inputs high inhibits clocking, and holding either clock input low with the load input high enables
the other clock input. The clock-inhibit input should be
changed to the high level only while the clock input is high.
Parallel loading is inhibited as long as the load input is high.
Connection Diagram
Data at the parallel inputs are loaded directly into the register on a high-to-Iow transition of the shift/load input, regardless of the logic levels on the clock, clock inhibit, or serial
inputs.
Features
•
•
•
•
•
•
Complementary outputs
Direct overriding (data) inputs
Gated clock inputs
Parallel-to-serial data conversion
Typical frequency 35 MHz
Typical power dissipation 105 mW
Dual-In-Llne Package
CLOCK
PARALLEL INPUTS
VCC INHIBIT ' D
116
15
1
2
SHIFT / CLOCK
LOAD
C
14
13
12
4
3
F
E
SERIAL OUTPUT
A \ INPUT
OH
B
5
G
11
10
9
6
7
IB
H
.~------~--------~
OUTPUT GND
PARALLEL INPUTS
OH
TUF/6399-1
Order Number 54LS165DMQB, 54LS165FMQB, DM74LS165WM or DM74LS165N
See NS Package Number J16A, M16B, N16E or W16A
Function Table
Inputs
Shlftl
Load
Clock
Inhibit
L
X
L
L
L
H
H
H
H
H
Clock
Serial
X
L
X
X
t
t
H
X
Internal
Outputs
Parallel
A ...H
QA
QB
a... h
a
QAO
b
QBO
QAn
OAn
aBO
X
X
X
X
L
X
H
L
OAO
H = High Level (steady state), L = Low Level (steady state)
X = Don't Care (any Input, Including translUons)
t = Transition from low.to-hlgh level
= The level of steady·state Input at Inputs A through H, respectively.
a...h
OAO, Oao, OHO = The level of 0A. Oa, or 0H. respectively, before the indicated steady·state input conditions were esteblished.
OAn, OGn = The level of OA or QG, respectively, before the most recent t transition of the clock.
2-191
Output
QH
h
QHO
QGn
OGn
OHO
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
-55·C to + 125·C
54LS
DM74LS
O·Cto +70"C
- 65·C to + 150·C
Storage Temperature Range
Note: The "Absolute Maximum Ratings" ara those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Recommended Operating Conditions
Symbol
Parameter
Min
4.5
Vee
Supply Voltage
VIH
High Level Input Voltage
Vil
10H
10l
Low Level Input Voltage
High Level Output Current
Low Level Output Current
Clock Frequency (Note 1)
felK
felK
tw
tsu
tH
TA
VI
VOH
VOL
II
IIH
III
los
5
DM74LS165
Nom
Max
4.75
5
5.25
Min
Max
5.5
2
2
4
30
0
Pulse Width
(Note2)
Setup Time
(Note6)
Clock
18
0
25
Load
Parallel
Serial
15
10
10
15
10
20
Enable
Shift
10
30
45
10
5
-55
Hold Time (Note 6)
Free Air Operating Temperature
0.8
-0.4
8
V
mA
mA
25
20
MHz
MHz
ns
ns
70
·c
over recommended operating free air temperature range (unless otherwise noted)
Parameter
Conditions
Min
Typ
(Note 3)
= Min,ll = -18 mA
Input Clamp Voltage
High Level Output
Voltage
Vee = Min, 10H = Max
Vil = Max, VIH = Min
54LS
DM74
Low Level Output
Voltage
Vee = Min, 10l = Max
VIL = Max, VIH = Min
54LS
Input Current @ Max
Input Voltage
10l = 4 mA, Vee = Min
Vee = Max, VI = 7V (DM74)
VI = 10V (54LS)
High Level Input
Current
Vee = Max
VI = 2.7V
Low Level Input
Current
Vee = Max
VI = 0.4V
Short Circuit
Output Current
Vee = Max
(Note4)
Vee
V
ns
0
0
125
Units
V
0.7
-0.4
Clock Frequency (Note 2)
Electrical Characteristics
Symbol
54LS165
Nom
2.5
2.7
Max
Units
-1.5
V
V
3.4
0.4
DM74
0.35
0.25
Shift/Load
0.5
0.4
Others
0.3
0.1
Shift/Load
60
Others
Shift/Load
20
-1.2
Others
54LS
-20
-0.4
-100
DM74
-20
-100
V
mA
p.A
mA
mA
Supply Current
21
36
mA
Vee = Max (Note 5)
lee
Note': CL = 15 pF, RL = 2 kO, TA = 25'C and Vee = 5V
Note 2: CL = SO pF, RL = 2 kO, TA = 25'C and Vee = SV
Note 3: All typlcals are at Vee = 5V, TA = 2S' C.
Note 4: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 5: With all outputs open, clock Inhibit and shift/load at 4.SV, and a clock pulse applied to the CLOCK input, lee Is measured first with the parallel inputs at
4.5V, then again grounded.
Note 8: TA = 25'C and Vce = SV.
2-192
.. ,.. ~'"'. "
"
Switching Characteristics
Symbol
at Vee = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
From (Input)
To (Output)
Parameter
54LS
DM74LS
CL = 15pF
RL = 2kn
CL = 50pF
Min
fMAX
tpLH
Maximum Clock Frequency
Max
Min
25
Units
Max
20
MHz
Propagation Delay Time
Low to High Level Output
Load to
AnyQ
30
37
ns
tpHL
Propagation Delay Time
High to Low Level Output
Load to
AnyQ
30
42
ns
tpLH
Propagation Delay Time
Low to High Level Output
Clock to
AnyQ
30
42
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clock to
AnyQ
30
47
ns
tpLH
Propagation Delay Time
Low to High Level Output
H
toQH
20
27
ns
tpHL
Propagation Delay Time
High to Low Level Output
30
37
ns
tpLH
Propagation Delay Time
Low to High Level Output
H
toQH
H
toOH
30
32
ns
tpHL
Propagation Delay Time
High to Low Level Output
H
toOH
25
32
ns
Timing Diagram
Typical Shift, Load, and Inhibit Sequences
CLOCK
CLOCK INHIBIT
L
SERIAL INPUT
SHIFT ILOAD
-
U
A.--J
B
IH1
L
til
c.--J
D
DATA
L
til
E
I
F---'
L
G.--J
H.--J
OUTPUTQH
OUTPUTQH
I
-----
iHl
IH1
===1
I-'NHIBIT
H
H
L
H
L
H
L
H
L
L
H
L
H
L
H
L
I
SERIAL SHIFT
LOAD
TL/F/6399-3
2-193
LS165
r
o
(Q
Cr
c
i'
(Q
Si1
3
PARALLEL INPUTS
B
C
(9)
OUTPUT QH
~
...
CD
(7)
INPUT
OUTPUTQH
SHIFT I (1)
LOAD
-----c{>
(2)
CLOCK - - - - - - ,
CLOCK (15)
INHIBIT _ _ _ _--I
TLlF/6399-2
~National
~ Semiconductor
DM74LS166
8-Bit Paraliel-ln/Serial-Out Shift Registers
General Description
These parallel-in or serial-in, serial-out shift registers feature
gated clock inputs and an overriding clear input. All inputs
are buffered to lower the drive requirements to one normalized load, and input clamping diodes minimize switching
transients to simplify system design. The load mode is established by the shift/load input. When high, this input enables the serial data input and couples the eight flip-flops for
serial shifting with each clock pulse. When low, the parallel
(broadside) data inputs are enabled and synchronous loading occurs on the next clock pulse. During parallel loading,
serial data flow is inhibited. Clocking is accomplished on
the low-to-high-Ievel edge of the clock pulse through a twoinput NOR gate, permitting one input to be used as a clockenable or clock-inhibit function. Holding either of the clock
inputs high inhibits clocking; holding either low enables the
other clock input. This allows the system clock to be free
running, and the register can be stopped on command with
the other clock input. The clock-inhibit input should be
changed to the high level only while the clock input is high.
A buffered, direct clear input overrides all other inputs, including the clock, and sets all flip-flops to zero.
Connection Diagram
Dual-In-Llne Package
PARALLEL
PARALLEL INPUTS
SHIFT I INPUT OUTPUT ,
VCC LOAD
H
OH
G
F
E
116
15
14
13
12
11
CLEAR
10
9
Order Number DM74LS166WM or DM74LS166N
See NS Package Number M16B or N16A
SERIAL
INPUT
2
4
3
5
A
B
C
D CLO:K CLO:K G!:
' - - - _ . . - - - - ' INHIBIT
PARALLEL INPUTS
TL/F/6400-1
Function Table
Inputs
Clear
L
H
H
H
H
H
Shlftl
Load
Clock
Inhibit
X
X
L
H
H
X
L
L
L
L
X
H
Clock
X
L
t
t
t
t
Serial
X
X
X
H
L
X
Parallel
Internal
Outputs
Output
QH
A ... H
QA
X
X
L
L
L
QAO
QBO
QHO
a ... h
X
X
X
a
H
L
QAO
QB
b
h
QAn
QAn
QBO
QGn
QGn
QHO
= High Level (steady state), L = Low Level (steady state)
= Don't care (any input. including tranSitions)
t = Transition from low 10 high level
a •.• h = The level of steady-state input at inputs A through H. respectively
0AD. aBO. OHD = The level of 0A. Oe. 0H. respectively. before the Indicated steady-state input condHions were established
0An. 0Gn. = The level of OA. OG. respectively. before the most recent t transition of the clock
H
X
2-195
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
DM74LS
O·Cto +70·C
Storage Temperature Range
-65·C to + 150·C
Recommended Operating Conditions
Symbol
DM74LS166
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
Vil
Low Level Input Voltage
10H
High Level Output Current
10l
Low Level Output Current
fClK
Clock Frequency (Note 1)
tsu
Nom
Max
4.75
5
5.25
V
2
Clock Frequency (Note 2)
tw
Units
Min
Pulse Width (Note 6)
Setup Time (Note 6)
V
0.8
V
-0.4
mA
8
mA
0
25
MHz
0
20
MHz
Clock
20
Clear
20
Mode
30
Data
20
tH
Hold Time (Note 6)
0
TA
Free Air Operating Temperature
0
ns
ns
ns
·c
70
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 3)
Max
Units
-1.5
V
VI
Input Clamp Voltage
VCC = Min, II = -18 mA
VOH
High Level Output
Voltage
Vcc = Min, 10H = Max
Vil = Max, VIH = Min
VOL
Low Level Output
Voltage
Vcc = Min, 10l = Max
Vil = Max, VIH = Min
0.35
0.5
10l = 4 mA, Vcc = Min
0.25
0.4
II
Input Current @ Max
Input Voltage
Vcc = Max, VI = 7V
2.7
3.4
V
V
0.1
mA
IIH
High Level Input Current
Vcc = Max, VI = 2.7V
20
III
Low Level Input Current
Vcc = Max, VI = O.4V
-0.4
fJ-A
mA
los
Short Circuit
Output Current
Vcc = Max
(Note 4)
-100
mA
-20
Supply Current
22
38
Vcc = Max (Note 5)
mA
Icc
Note t: CL = 15 pF, RL = 2 kO, TA = 25'C and Vcc = 5V.
Note 2: CL = 50 pF, RL = 2 kO, TA = 25"C and Vee = 5V.
Note 3: All typicals are at Vee = 5V, TA = 25'C.
Note 4: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note S: With all outputs open, 4.5V applied to the serial Input, all other inputs except the CLOCK grounded, Icc Is measured after a momentary ground, then 4.5V Is
applied to the CLOCK.
Note 6: TA = 25'C and Vee = 5V.
2-196
Switching Characteristics at Vee =
RL = 2kO
From (Input)
To (Output)
Parameter
Symbol
5V and T A = 25°C (See Section 1 for Test Waveforms and Output Load)
CL = 15pF
Min
CL = 50pF
Max
Units
Max
Min
fMAX
Maximum Clock
Frequency
tpLH
Propagation Delay Time
Low to High Level Output
Clock to
Output
8
35
38
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clock to
Output
8
35
41
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clear to
Output
6
30
36
ns
25
20
MHz
Parameter Measurement Information
Voltage Waveforms
IW(CLEAR)
CLEAR
INPUT
3.0V-_ __.
\
vREF
I
OV-------t'----J
CLOCK 3.0V
INPUT
OV
---,,..-.t---,,,;}
VREF
II.
I n +1
VREF
~
f--ISETUP-
~v.
i
VREF
OUTPUT a
VREF
t:
ISETUP
VREF
+ __
-
PHL
(CLEAR-a)
VREF
tPLH
(CLOCK-a).....
-
VREF
f.
--';;-V.
VREF
t--- {;fHOLD~
f-OIW-=t=C=LO=.C=Kc,::),-\
ISETUP
DATA 3.0V
INPUT
VREFjr
(SEE TEST TABLE) OV _ _ _ _
~---J
VOH
(Nole D)
VREF
HOLD
VREF
tPHL
(CLOCK-a)
VREF
'"-----TUF/6400-2
Test Table for Synchronous Inputs
Data Input
for Test
Shift/Load
Output Tested
(See Note C)
H
OV
4.5V
QH atTN + 1
QHatTN+S
Serial Input
Note A: The clock pulse has the following characteristics: tWleloek) ., 20 ns and PRR = 1 MHz. The clear pulse has the following characteristics: tw(elear) ., 20 ns
and tHOLD = 0 ns. When testing fMAX. vary the clock PRR.
Note B: A clear pulse is applied prior to each test.
Note C: Propagation delay times (tpLH and tpHU are measured at In + 1. Proper shifting of data Is verified at In + 8 with a functionallesl.
Note D: In = bil time before clocking transilion
1"+ 1 = billime after one clocking Iransltion
t"+8 = bll time after elghl clocking transilions
Note E: VREF = l.aV.
2-197
I
!j
Logic Diagram
TL/F/6400-3
Timing Diagram
Typical Clear, Shift, Load, Inhibit and Shift Sequences
CLOCK
CLOCK INHIBIT
CLEAR
SERIAL INPUT
SHIFT/LOAD
A __
B __
~r-
~r-
__________________ __-J
__________________ ____ ____
~
~
~
-+~
________________________
C
PARALLEL
INPUTS
D
E
F
G
H __
~r-
O~UTQH :::~~
__________________ __-J
~
____________________-J
H
H
I------SERIAL S H I F T - - - - - - I
CLEAR
TL/F/6400-4
2-198
~National
~ Semiconductor
54LS168 Synchronous Bi-Directional
BCD Decade Counter
General Description
The 54LS168 is a fully synchronous 4-state up/down counter featuring a preset capability for programmable operation,
carry lookahead for easy cascading and a U/O input to control the direction of counting. it counts in the BCD (8421)
sequence and all state changes, whether in counting or parallelloading, are initiated by the LOW-to-HIGH transition of
the clock.
Connection Diagram
Logic Symbol
Dual-In-Llne Package
UfDCPPOPlP2P3CEP-
1
2
3
4
5
6
7
'-/
~ iii
16 I-Vcc
15 I-TC
14 1-00
13 1-01
12 -02
11 -Q3
i
PE PO PI P2 P3
I-ufo
7-
20
20
Load
25
25
UfD
30
30
ns
ns
tH
Hold Time (Note 3)
0
TA
Free Air Operating Temperature
ns
0
-55
125
0
70
·C
Note 1: CL = 15 pF, RL = 2 kil, TA = 25'C and Vee = 5V.
Note 2: CL = 50 pF, RL = 2 kil, TA = 25'C and Vee = 5V.
Note 3: TA = 25"C and Vee = 5V.
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
= Min, II =
VI
Input Clamp Voltage
VCC
VOH
High Level Output
Voltage
Vcc = Min, 10H = Max
Vil = Max, VIH = Min
Low Level Output
Voltage
Vcc = Min, 10l = Max
Vil = Max, VIH = Min
VOL
IIH
III
los
lee
Input Current @ Max
Input Voltage
High Level Input
Current
Low Level Input
Current
Short Circuit
Output Current
Supply Current
Typ
(Note 4)
DM54
2.5
3.4
DM74
2.7
3.4
-18 mA
= 4 mA, Vcc = Min
Vee = Max
VI = 7V
Vee = Max
VI = 2.7V
Vee = Max
VI = 0.4V
Vee = Max
10l
II
Min
Conditions
(NoteS)
Vee
Max
Units
-1.5
V
V
DM54
0.25
0.4
DM74
0.35
0.5
DM74
0.25
0.4
EnableT
0.2
Others
0.1
EnableT
40
Others
20
EnableT
-0.8
Others
-0.4
DM54
-20
-100
DM74
-20
-100
= Max (Note 6)
20
34
Note 4: All typicals are at Vee = 5V and TA = 25'C.
Note 5: Not more than one output should be shorted at a time, and Ihe duration should not exceed one second.
Note 6: Icc Is measured alter a momentary 4.5V, then ground, is applied to the CLOCK with all other inputs grounded and all the oulputs open.
2-204
V
mA
,.,.A
mA
mA
mA
Switching Characteristics at Vcc = 5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
RL = 2kn
From (Input)
Parameter
Units
Symbol
CL = 15pF
CL = 50pF
To (Output)
Min
Max
Min
Max
fMAX
Maximum Ciock
Frequency
tpLH
Propagation Delay Time
Low to High Level Output
Ciockto
Ripple Carry
35
39
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clock to
Ripple Carry
35
44
ns
tpLH
Propagation Delay Time
Low to High Level Output
Clock to
Any 0
20
24
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clock to
Any 0
23
32
ns
tpLH
Propagation Delay Time
Low to High Level Output
EnableTto
Ripple Carry
18
24
ns
tpHL
Propagation Delay Time
High to Low Level Output
EnableTto
Ripple Carry
18
28
ns
tpLH
Propagation Delay Time
Low to High Level Output
Up/Down to
Ripple Carry (Note 1)
25
30
ns
tpHL
Propagation Delay Time
High to Low Level Output
Up/Down to
Ripple Carry (Note 1)
29
38
ns
25
20
MHz
Note 1: The propagation delay from UP/DOWN to RIPPLE CARRY must be measured with the counter at either a minimum or a maximum count. As the logic level
of the up/down input is changed, the ripple carry output will follow. If the count is minimum, the ripple carry output transition will be In phase. If the count is
maximum, the ripple carry output will be out of phase.
2·205
m
....
Logic Diagram
~
LS169A Binary Coun er
~
I
-
(3)
e&.OCK
'21
...
2
I
rM
TA
~~.
elK
I
r
..
Lr-.
ctI~
'0"
•
~
lil~.
JJ
(4,
a,;...;
J
r--
p
I
J
~
~jp
cc--r
'"
DATAC-
--'
ft:
~
19
QC~QC
J
...::
_11'
UP OWN
-VL
Joo,
I
r-
...:±i
r-!
DATA 0
,.,
lNABLl't!!!.'
1;-
0af--T1!!!
QQ
~
WJ
LOAD
tf
,ti
~
....... ,t1l"" Vb
---l
~
Lb
I'
I
I
+-
t---
-
-
t..--
...!..!.!!
TL/F/6401-2
2-206
Timing Diagram
LS169A Binary Counters
Typical Load, Count, and Inhibit Sequences
LOAD
L----1
.-
A
L.._
B
DATA
INPUTS
C
L-_
D
'-_
CLOCK
PANDT
QC __
..J
QD __
...J
RIPPLE - - -r--++--,
CARRY
OUTPUT __ ..J
13
14
15
I
1
0
II---COUNT UP
2
2
--+1-, INHIBlT--I
2
1
0
15
14
13
1-1-'--COUNT DOWN - - -
~
LOAD
TLlF/6401 -3
2-207
~
§ ~National
~ Semiconductor
54LS170/DM74LS170
4 x 4 Register File with Open-Collector Outputs
General Description
Features
The 'LS170 contains 16 high speed, low power, transparent
D-type latches arranged as four words of four bits each, to
function as a 4 x 4 register file. Separate read and write
inputs, both address and enable, allow simultaneous read
and write operation. Open-collector outputs make it possible
\0 connect up to 128 outputs in a wired-AND configuration
to increase the word capacity up to 512 words. Any number
of these devices can be operated in parallel to generate an
n-blt length. The '670 provides a similar function to this device but it features TRI-STATEQI) outputs.
•
•
•
•
Connection Diagram
Logic Symbol
Simultaneous read/write operation
Expandable to 512 words of n-bits
Typical access time of 20 ns
Low leakage open-collector outputs for expansion
ZYiii
Dual·ln·Llne Package
02- I
03- 2
04RAIRAO0403-
3
4
5
6
7
GNO- 8
'-'
14- WAO WE 01 02 D3 04
16 I-Vcc
15 1-01
14 I-WAO
13 I-WAI
13-WAI
5 - RAO
4 - RAI RE 01 02 03 04
12 I-WE
II -iiE
10 -01
9 -02
~ I~
vee = Pin 16
GND = PinS
TL/F/992D-1
Order Number 54LS170DMOB, 54LS170FMOB,
DM74LS170WM or DM74LS170N
See NS Package Number J16A, M16B, N16E or W16A
Pin Names
Description
01-04
WAO-WA1
Data Inputs
Write Address Inputs
Write Enable Input (Active LOW)
Read Address Inputs
Read Enable Input (Active LOW)
Data Outputs
WE
RAO, RA1
FiE
01-04
1l 1
2-208
TLlF/9820-2
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaran·
teed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum raffngs.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
10V
Operating Free Air Temperature Range
-55·Cto +125·C
54LS
DM74
O·Cto +70·C
Storage Temperature Range
-65·Cto + 150·C
Recommended Operating Conditions
Symbol
54LS170
Parameter
DM74LS170
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
V
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
0.7
0.8
IOH
High Level Output Current
20
20
".A
IOL
Low Level Output Current
4
8
mA
70
·C
2
2
-55
V
TA
Free Air Operating Temperature
ts
Setup Time HIGH or LOW
On to Rising WE
10
10
ns
th
Hold Time HIGH or LOW
On to Rising WE
5.0
5.0
ns
ts
Setup Time HIGH or LOW
WAn to Falling WE
10
10
ns
th
Hold Time HIGH or LOW
WAn to Rising WE
5.0
5.0
ns
tw(L)
WE or RE Pulse Width LOW
25
25
ns
125
0
Electrical Characteristics
Over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
=
=
VI
Input Clamp Voltage
Vee
VOH
High Level
Output Voltage
Vee = Min, 10H
VIL = Max
=
Low Level
Output Voltage
Vee = Min, 10L
VIH = Min
=
VOL
Min,ll
Input Current @ Max
Input Voltage
IIH
IlL
los
High Level Input Current
Max,
Max,
= 4 mA, Vec = Min
VCC = Max, VI = 10V
Low Level Input Current
Short Circuit
Output Current
Vce
Vce
=
=
Max, VI
Max, VI
=
=
2.7V
O.4V
Vec = Max
(Note 2)
54LS
2.0
DM74
2.7
Supply Current
2·209
Max
Ulnts
-1.5
V
V
3.4
54LS
0.4
DM74
0.35
0.5
DM74
0.25
0.4
Dns, RAO, WAO
0.1
WE,RE
0.2
Inputs
20
RE,WE
40
RE,WE
-0.06
-0.8
RA1, WA1
-0.05
-0.4
DATA, RAO, WAO
-0.03
-0.4
54LS
-20
-100
DM74
-20
-100
Vec = Max, Dn, WE,
RE = 4.5V, WAn, RAn = GND
Note 1: All typicals are at Vee = SV. TA = 2S'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one .econd.
lee
Typ
(Note 1)
-18 mA
IOL
II
Min
40
V
mA
p.A
mA
mA
mA
,.
Switching Characteristics
= +5.0V, TA = +25'C, (See Section 1 for waveforms and load configurations)
RL = 2k,CL = 15pF
Symbol
Parameter
Conditions
Vee
Min
Units
Max
tpLH
tpHL
Propagation Delay'
RAO or RA1 to On
35
35
ns
tpLH
tpHL
Propagation Delay
REtoOn
30
30
ns
tpLH
tpHL
Propagation Delay
WE to On
35
35
ns
tpLH
tpHL
Propagation Delay
DntoOn
35
35
ns
'Measured at least 25 ns after entry of new data at selected location.
Switching Waveforms
WAO,WAI \ \ \ \ \
\Xvm
I\\\\\\\\\\\\\\\
~th
~Is-Dl-D4 \ \ \ \ \ \ \ \ \ \
~\\\\ \ \ \
.\\ \ \ \\\\\\\\\\Xvm
.1-=="15- I+-th-
\'-\\'-\
Iw(L)
Vm =I.5V
(I.3V for LS)
WE
TUF/9B20-4
FIGURE a
Write Function Table
Write Inputs
Dlnputsto
WE
WA1
WAO
L
L
L
L
L
L
H
H
H
H
H
X
X
H = HIGH Voltage Level
Read Function Table
Read Inputs
L
L
Word 0
Word 1
Word 2
Word 3
None (Hold)
L = LOW Voltage Level
2-210
Outputs from
RE
RA1
RAO
L
L
L
L
L
L
H
H
H
H
H
X
X
L
L
X = Immaterial
Word 0
Word 1
Word 2
Word 3
None (High Z)
Logic Diagram
I
G
Q
D
1
6,
.1
1
.1
1
iiE-
I~
RAG
~}--
-
04
03
2-211
02
0~LlF/9B20_3
•
~
~ ~National
~ Semiconductor
54LS 173/DM7 4LS 173A
TRI-STATE® 4-Bit D-Type Register
General Description
This four-bit register contains D-type flip-flops with totempole TRI-STATE~ outputs, capable of driving highly capacitive or low-impedance loads. The high-impedance state and
increased high-logic-level drive provide these flip-flops with
the capability of driving the bus lines in a bus-organized system without need for interface or pull-up components.
To minimize the possibility that two outputs will attempt to
take a common bus to OPPOSite logic levels, the output control circuitry is designed so that the average output disable
times are shorter than the average output enable times.
Gated enable inputs are provided for controlling the entry of
data into the flip-flops. When both data-enable inputs are
low, data at the 0 inputs are loaded into their respective flipflops on the next positive transition of the buffered clock
Input. Gate output control inputs are also provided. When
both are low, the normal logic states of the four outputs are
available for driving the loads or bus lines. The outputs are
disabled independently from the level of the clock by a high
logic level at either output control input The outputs then
present a high impedance and neither load nor drive the bus
line. Detailed operation is given in the truth table.
• TRI-STATE outputs interface directly with system bus
• Gated output control lines for enabling or disabling the
outputs
• Fully independent clock eliminates restrictions for operating in one of two modes:
Connection Diagram
Function Table
Dual-In-Llne Package
116
01
14
15
CLEAR
02
10
OUTPUT
CONTROL 10
~
11
M
2
N
3
01
OUTPUT CONTROL
03
13
20
20
4
02
30
3Q
5
03
-G2
04
12
Parallel load
Do nothing (hold)
• For application as bus buffer registers
Inputs
DATA ENABLE
INPUTS
.
DATAtNPUTS
Vee CLEAR
Features
11
Clear
10 \9
tr
40
H
L
L
L
L
L
DATA
ENABLE
CK
4Q
6
7
Data
Enable
Clock
G1
X
L
t
t
t
t
Data
G1
G2
0
X
X
H
X
L
L
X
X
X
H
L
L
X
X
X
X
L
H
Output
Q
L
00
00
00
L
H
When either M or N (or both) is (are) high the output is
disabled to the high-impedance state; however,
sequential operation of the flip-flops is not affected.
J8
Q4 CLOCK GND
.
H
OUTPUTS
= High Level (Steady Slate)
L = Low Level (Steady State)
TL/F/6403-1
Order Number 54LS173DMQB, 54LS173FMQB,
54LS173LMQB, DM74LS173AM or DM74LS173AN
See NS Package Number E20A, J16A,
M16A, N16E or W16A
t = Low-to-High Level Transition
X = Don't Care (Any Input Including Transitions)
00 = The Level of Q Before the Indicated Steady Slate Input Conditions
Were Established.
2-212
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
Input Voltage
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaran·
teed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
7V
7V
Operating Free Air Temperature Range
- 55·C to + 125·C
54LS
DM74LS
O·Cto +70·C
Storage Temperature Range
-65·Cto + 150·C
Recommended Operating Conditions
Symbol
54LS173
Parameter
Vec
Supply Voltage
VIH
High Level Input Voltage
DM74LS173A
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
2
V
V
VIL
Low Level Input Voltage
0.7
0.8
V
10H
High Level Output Current
-1
-2.S
mA
IOL
Low Level Output Current
fCLK
Clock Frequency (Note 1)
24
mA
30
12
0
30
MHz
0
20
MHz
Clock Frequency (Note 2)
tw
tsu
tH
Pulse Width
(Note 3)
Clock
20
17
Clear
17
17
Setup Time
(Note 3)
Enable
17
23
Data
15
15
Hold Time
(Note 3)
Enable
0
0
Data
5
0
tREL
Clear Release Time
TA
Free Air Operating Temperature
Note 1: CL
10
ns
ns
ns
ns
10
-55
125
0
70
·C
= 45 pF, RL = 6670, TA = 25'C and Vee = 5V.
= 6670, TA = 25'C and Vee = 5V.
= 25'C and Vee = 5V.
Note 2: CL = 150 pF, RL
Note 3: TA
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
VI
Input Clamp Voltage
Vee = Min, 11= -18 mA
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
VIL = Max, VIH = Min
VOL
Low Level Output
Voltage
Vee = Min, 10L = Max
VIL = Max, VIH = Min
10L = 4 mA, Vee
= Min
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 7V
IIH
High Level Input Current
Min
Typ
(Note 5)
Max
Units
-1.5
V
2.4
V
0.4
54LS
DM74
0.35
0.5
DM74
0.25
0.4
V
0.1
mA
Vce = Max, VI = 2.7V
20
IlL
Low Level Input Current
Vce = Max, VI = O.4V
-0.4
10ZH
Off·State Output Current with High
Level Output Voltage Applied
Vee = Max, Vo = 2.7V
VIH = Min, VIL = Max
20
/LA
10ZL
Off-State Output Current with Low
Level Output Voltage Applied
Vee = Max, Vo = O.4V
VIH = Min, VIL = Max
-20
/LA
los
Short Circuit
Output Current
Vcc = Max
(NoteS)
Supply Current
Vee
Icc
•
I
/LA
mA
= Max (Note 7)
2·213
54LS
-20
-100
DM74
-20
-100
17
30
mA
mA
Switching Characteristics at Vee =
Symbol
Parameter
5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
From (Input)
To (Output)
54LS
DM74LS
CL = SOpF
CL = 1S0pF
RL = 6670
Min
Max
Min
Units
Max
fMAX
Maximum Clock
Frequency
tpLH
Propagation Delay Time
Low to High Level Output
Clock to
Output
28
34
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clock to
Output
28
40
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clear to
Output
30
40
ns
tPZH
Output Enable Time
to High Level Output
Output Control
(M orN) toAnyQ
23
34
ns
tPZL
Output Enable Time
to Low Level Output
Output Control
(M or N) to Any Q
28
45
ns
tpHZ
Output Disable Time from
High Level Output (Note 8)
.Output Control
(M or N) to Any Q
17
25
ns
tpLZ
Output Disable Time from
Low Level Output (Note 8)
Output Control
(M or N) to Any Q
23
25
ns
30
20
ns
Note 4: All typicals are at Vee = 5V. TA = 25"C.
Note 5: Not more than one output should be shorted at a time. and the duration should not exceed one second.
Nate S: lee Is measured with all outputs open: Clear grounded after a momentary 4.5V; N. G1. G2 and all data inputs grounded: and the CLOCK and M Input at
4.5V.
Nate 7: CL = 5 pF.
2·214
Logic Diagram
OUWUT{M~(i1)~--~__________________________________- ,
CONTROL
N _(_2)___"
DATA ..:.(.;.;14:.:,)____________.J-__,''''
01
OA~~ """";;;:...----+-----+---r~
CLOCK (7)
DATA
~(.;,;12:.:.)______~----.J-
__r"'\
03
DATA~(~l~l)~____~--------r_""
D4
CLEAR
(1~5.)i~~--------------__------~--~
TLlF/6403-2
2-215
;e
!i J?'A National
~
.... ~ Semiconductor
!)
54LS 174/DM54LS 174/DM7 4LS 174,
54LS175/DM54LS175/DM74LS175
Hex/Quad D Flip-Flops with Clear
General Description
Features
These positive-edge-triggered flip-flops utilize TTL circuitry
to implement D-type flip-flop logic. All have a direct clear
input, and the quad (175) versions feature complementary
outputs from each flip-flop.
Information at the D inputs meeting the setup time requirements Is transferred to the 0 outputs on the positive-going
edge of the clock pulse. Clock triggering occurs at a particular voltage level and Is not directly related to the transition
time of the positive-going pulse. When the clock input is at
either the high or low level, the D Input signal has no effect
at the output.
•
•
•
•
•
LS174 contains six flip-flops with single-rail outputs
LS175 contains four flip-flops with double-rail outputs
Buffered clock and direct clear inputs
Individual data input to each flip-flop
Applications include:
Buffer/storage registers
Shift registers
Pattern generators
• Typical clock frequency 40 MHz
• Typical power dissipation per flip-flop 14 mW
• Alternate
Military/Aerospace
device
(54LS174,
54LS175) is available. Contact a National Semiconductor Sales Office/Distributor for specifications.
Connection Diagrams
Dual·ln·Llne Package
VCC
06
06
05
05
Dual·ln·Llne Package
04
04
CLOCK
VCC
04
04
03
03
03
02
02
02
CLOCK
13
4
CLEAR
01
01
02
02
03
03
CLEAR
GNO
01
TLlF/6404-,
01
GNO
TL/F/6404-2
Order Number 54LS174DMQB, 54LS174FMQB,
54LS174LMQB, DM54LS174J,
DM54LS174W, DM74LS174M or DM74LS174N
See NS Package Number E20A, J16A,
M16A, N16E or W16A
Order Number 54LS175DMQB, 54LS175FMQB,
54LS175LMQB, DM54LS175J
DM54LS175W, DM74LS175M or DM74LS175N
See NS Package Number E20A, J16A,
M16A, N16E or W16A
Function Table (Each Flip-Flop)
Inputs
Clear
Clock
L
H
H
H
L
H = High Level (steady state)
Outputs
D
Q
Qt
X
X
t
t
H
L
L
H
L
H
L
H
X
00
00
L = Low Level (steady state)
x = Don't Care
t
= Transition from low to high level
= The level of C before the Indicated steady-state Input conditions were
established.
t = LS175 only
Co
2-216
Absolute Maximum Ratings
(Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and speciflcations_
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
DM54LS and 54LS
-55·Cto + 125·C
DM74LS
O·Cto +70·C
-65·Cto +150·C
Storage Temperature Range
Recommended Operating Conditions
Symbol
DM54LS174
Parameter
Vcc
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
10H
High Level Output Current
10L
Low Level Output Current
Clock Frequency (Note 1)
fCLK
Clock Frequency (Note 2)
tw
Pulse Width
(Note 6)
Units
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
fCLK
I
I
DM74LS174
Min
2
V
V
0.7
0.8
V
-0.4
-0.4
mA
4
0
30
0
25
8
mA
0
30
MHz
0
25
MHz
Clock
20
20
Clear
20
20
ns
tsu
Data Setup Time (Note 6)
20
20
ns
tH
Data Hold Time (Note 6)
0
0
ns
tREL
Clear Release Time (Note 6)
25
25
TA
Free Air Operating Temperature
-55
125
ns
0
70
·C
Max
Units
-1.5
V
'LS 17 4 Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 3)
VI
Input Clamp Voltage
Vcc = Min, II = -18 mA
VOH
High Level Output
Voltage
Vcc = Min, 10H = Max
VIL = Max, VIH = Min
DM54
2.5
3.4
DM74
2.7
3.4
Low Level Output
Voltage
VCC = Min, 10L = Max
VIL = Max, VIH = Min
DM54
0.25
0.4
DM74
0.35
0.5
10L = 4 mA, VCC = Min
DM74
0.25
0.4
VOL
II
Input Current@Max
Input Voltage
VCC = Max, VI = 7V
IIH
High Level Input Current
Vcc = Max, VI = 2.7V
IlL
Low Level Input
Current
Vcc = Max
VI = 0.4V
los
Short Circuit
Output Current
0.1
mA
20
p.A
Clear
-0.4
Data
-0.36
DM54
-20
-100
DM74
-20
-100
Supply Current
Vcc = Max (Note 5)
16
26
Icc
Note 1: CL = 15 pF. RL = 2 kn. TA = 2S·C and Vee = SV.
Note 2: CL = 50 pF, RL = 2 kn, TA = 2S·C and Vee = SV.
Note 3: All typical. are at Vee = SV, TA = 2S·C.
Note 4: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 5: With all outputs open and 4.SV applied to all data and clear Inputs, lee Is measured after a momentary ground, then 4.SV applied to the clock.
Note 6: TA = 2S·C and Vee = SV.
2-217
V
-0.4
Clock
Vee = Max
(Note 4)
V
mA
mA
mA
•
'LS174 Switching Characteristics
at Vee
=
Symbol
5V and TA
=
25·C (See Section 1 for Test Waveforms and Output Load)
RL
From (Input)
To (Output)
Parameter
CL
=
=
2kO
15pF
Min
CL
=
Units
50pF
Min
Max
Max
fMAX
Maximum Clock Frequency
tplH
Propagation Delay Time
Low to High Level Output
Clock to
Output
30
32
ns
tpHl
Propagation Delay Time
High to Low Level Output
Clock to
Output
30
36
ns
tpHl
Propagation Delay Time
High to Low Level Output
Clear to
Output
35
42
ns
30
25
MHz
Recommended Operating Conditions
Symbol
DM54LS175
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
Vil
Low Level Input Voltage
IOH
High Level Output Current
IOl
Low Level Output Current
Clock Frequency (Note 1)
fOLK
Clock Frequency (Note 2)
tw
Pulse Width
(Note 3)
I
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
0.7
0.8
V
-0.4
-0.4
rnA
2
fOLK
I
DM74LS175
2
4
0
30
0
25
V
8
rnA
0
30
MHz
0
25
MHz
Clock
20
20
Clear
20
20
ns
tsu
Data Setup Time (Note 3)
20
20
tH
Data Hold TIme (Note 3)
0
0
ns
tREl
Clear Release Time (Note 3)
25
25
ns
TA
Free Air Operating Temperature
-55
125
= 15 pF, RL = 2 kn, TA = 25"C and Vee = 5V.
Note 2: CL = 50 pF, RL = 2 kn, TA = 25"C and Vee = 5V.
Note 3: TA = 25"C and Vee = 5V.
Note 1: CL
2·218
0
ns
70
·C
Ii)
....
'LS175 Electrical Characteristics
~
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 1)
•
Max
Units
-1.5
V
VI
Input Clamp Voltage
VOH
High Level Output
Voltage
= Min,ll = -18 mA
Vee = Min, 10H = Max
VIL = Max, VIH = Min
Low Level Output
Voltage
Vee = Min, 10L = Max
VIL = Max, VIH = Min
DM54
0.25
0.4
DM74
0.35
0.5
= 4 mA, Vee = Min
Vee = Max, VI = 7V
DM74
0.25
0.4
VOL
Vee
10l
II
Input Current@Max
Input Voltage
IIH
High Level Input Current
Vee
IlL
Low Level Input
Current
Vee = Max
VI = 0.4V
Short Circuit
Output Current
Vee = Max
(Note 2)
Supply Current
Vee
DM54
2.5
3.4
DM74
2.7
3.4
Ice
....
.....
U1
V
= Max, VI = 2.7V
V
0.1
mA
20
",A
Clock
-0.4
Clear
-0.4
mA
-0.36
Data
los
Ii)
DM54
-20
-100
DM74
-20
-100
= Max (Note 3)
11
18
mA
mA
'LS175 Switching Characteristics
at Vee
= 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
From (Input)
To (Output)
RL
CL
Min
= 15pF
Max
30
= 2kO
CL
Min
= 50pF
Units
Max
fMAX
Maximum Clock Frequency
tpLH
Propagation Delay Time
Low to High Level Output
Clock to
QorO
30
32
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clock to
QorO
30
36
ns
tpLH
Propagation Delay Time
Low to High Level Output
Clear to
25
29
ns
0
25
MHz
Propagation Delay Time
Clear to
35
42
ns
High to Low Level Output
Q
Note 1: All typicals are at Vee = SV. TA = 2S'C.
Note 2: Not more than one output should be shorted at a time. and the duration should not exceed one second.
Note 3: With all outputs open and 4.SV applied to all data and clear inputs. Icc is measured after a momentary ground. then 4.SV applied to the clock input
tpHL
FJI
2-219
It)
....r-.
•
oo:r
r-.
....
en
en
-J
Logic Diagrams
LS174
-J
LS175
(3)
01
(4)
(2)
0
01
01
U
(2)
0
01
0
CLOCK
(3)
0
01
CLEAR
(5)
(4)
02
02
02
(7)
0
0
02
CLOCK
(6)
0
02
CLEAR
(6)
(12)
03
03
03
(10)
0
03
0
CLOCK
(11)
03
(13)
(11)
D4
04
04
(15)
0
04
0
CLOCK
CLOCK
(14)
0
04
CLEAR
CLEAR
(13)
05
05
TLlF/6404-4
CLEAR
(15)
(14)
D8
D
0
06
CLOCK
CLOCK
CLEAR
CLEAR
TL/F/6404-3
2-220
~
....
~National
....
CO
~ Semiconductor
54LS181/DM74LS181
4·Bit Arithmetic Logic Unit
General Description
Features
The 'LS181 is a 4·bit Arithmetic Logic Unit (ALU) which can
perform all the possible 16 logic operations on two variables
and a variety of arithmetic operations.
• Provides 16 arithmetic operations: add, subtract, com·
pare, double, plus twelve other arithmetic operations
• Provides all 16 logic operations of two variables: exclu·
sive·OR, compare, AND, NAND, OR, NOR, plus ten
other logic operations
• Full lookahead for high speed arithmetic operation on
long words
Connection Diagram
Dual-In-Llne Package
80AO5352-
1
2
3
4
\...../
24
23
22
21
51- 5
50- 6
Cn -
rVcc
rAI
r81
-A2
20 -82
19 -A3
18 -83
7
M- 8
17
FO- 9
Fl- 10
F2- 11
GND- 12
-Ci
16 -Cn+4
15 -p
14 -A=B
13 -F3
TL/F/9821-1
Order Number 54LS181DMQB, 54LS181FMQB or DM74LS181N
See NS Package Number J24A, N24A or W24C
Pin Names
AO-A3
80-83
SO-S3
M
Cn
FO-F3
A=B
G
P
Cn +4
Description
Operand Inputs (Active LOW)
Operand Inputs (Active LOW)
Function Select Inputs
Mode Control Input
Carry Input
Function Outputs (Active LOW)
Comparator Output
Carry Generate Output (Active LOW)
Carry Propagate Output (Active LOW)
Carry Output
2-221
•
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
- 55·C to + 125·C
54LS
DM74LS
O"Cto +70·C
Storage Temperature Range
-65·C to + 150·C
Recommended Operating Conditions
Symbol
Vee
Supply Voltage
VIH
High Level input Voltage
Vil
Low Level Input Voltage
DM74LS181
54LS181
Parameter
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
V
V
2
0.7
O.B
V
IOH
High Level Output Current
-0.4
-0.4
mA
IOl
Low Level Output Current
4
8
mA
TA
Free Air Operating Temperature
70
·c
-55
125
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
= Min, II = -18 mA
= Max,
VI
input Clamp Voltage
Vee
VOH
High Level Output
Voltage
Vee = Min, IOH
Vil = Max
Low Level Output
Voltage
Vee = Min, IOl
VIH = Min
VOL
= Max,
= 4 mA, Vee = Min
Vee = Max, VI = 10V
IOl
II
IIH
III
lOS
IcC
Input Current @ Max
Input Voltage
High Level Input Current
Low Level Input Current
Vee
Vee
Min
54LS
2.5
DM74
2.7
Supply Current
Vee = Max, Bn, Cn = GND
Sn, M, An = 4.5V
-1.5
V
0.4
0.35
0.5
DM74
0.25
0.4
V
M input
An,Sn
Sn
Cn
0.1
0.3
0.4
0.5
mA
An,Sn
Sn
Cn
20
60
BO
100
p.A
An,Sn
Sn
Cn
-0.4
-1.2
-1.6
-2.0
mA
54LS
-20
-100
DM74
-20
-100
54LS
35
DM74
37
Note 1: All typlcals are al Vee = 5V, TA = 25'C.
Note 2: Not more than one output should be shorted al a time, and Ihe duration should nol exceed one second.
2-222
Units
DM74
= Max, VI = OAV
Vee = Max
(Note 2)
Max
V
54LS
= Max, VI = 2.7V
Short Circuit
Output Current
Typ
(Note 1)
mA
mA
~
......
co
......
Switching Characteristics
Vee
= + 5.0V. T A = + 25 C (See Section 1 for waveforms and
D
load configurations)
54LS/DM74LS
Symbol
Parameter
Conditions
CL
Min
=
Units
15pF
Max
M
=
GND
27
20
ns
Propagation Delay
CntoF
M
=
GND
26
20
ns
tpLH
tpHL
Propagation Delay
A or B to G (Sum)
M. 51. 52 = GND;
51.53 = 4.5V
29
23
ns
tpLH
tpHL
Propagation Delay
A or B to G (Dill)
M. So. 53 = GND;
51.52 = 4.5V
32
26
ns
tpLH
tpHL
Propagation Delay
A or B to is (Sum)
M. 51. 52 = GND;
50.53 = 4.5V
30
30
ns
tpLH
tpHL
Propagation Delay
A or B to is (Dill)
M. So. 53 = GND;
51.52 = 4.5V
30
33
ns
tpLH
tpHL
Propagation Delay
Ai or Bj to Fj (Sum)
M. 51. 52 = GND;
50.53 = 4.5V
32
25
ns
tpLH
tpHL
Propagation Delay
Aj or Bj to Fj (Dill)
M. So. 53 = GND;
51.52 = 4.5V
32
33
ns
tpLH
tpHL
Propagation Delay
A or B to F (Logic)
M
33
29
ns
tpLH
tpHL
Propagation Delay
A or B to Cn +4 (Sum)
M.S1.S2 = GND;
50.53 = 4.5V
38
38
ns
tpLH
tpHL
Propagation Delay
A or B to Cn +4 (Dill)
M. So. 53 = GND;
51.52 = 4.5V
41
41
ns
tpLH
tpHL
Propagation Delay
AorBtoA = B
M. So. 53 = GND;
51. 52 = 4.5V;
RL = 2 kO to 5.0V
50
62
ns
Propagation Delay
tpLH
tpHL
Cn to Cn+4
tpLH
tpHL
=
4.5V
2-223
....
co
....
~
Sum Mode Test Table I
Symbol
Input
Under
Test
Function Inputs 50 =
53 = 4.5V.51 = 52 = M = OV
Other Input
Same Bit
Other Data Inputs
Output
Under
Test
Apply
4.SV
Apply
GND
Apply
4.SV
Apply
GND
AI
Si
None
Remaining
AandS
Cn
FI
Si
AI
None
Remaining
AandS
Cn
FI
A
S
None
None
Remaining
A and S. Cn
is
S
A
None
None
Remaining
A and S. Cn
is
A
None
S
Remaining
S
Remaining
A.Cn
G
tpLH
tpHL
S
None
A
Remaining
S
Remaining
A.Cn
G
tpLH
tpHL
A
None
S
Remaining
S
Remaining
A.Cn
Cn +4
S
None
A
Remaining
S
Remaining
A.Cn
Cn +4
Cn
None
None
All
A
All
S
AnyF
OrCn +4
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
Ditt Mode Test Table II
Symbol
Input
Under
Test
Function Inputs 51
Other Input
Same Bit
= 52 = 4.5V. 50 = 53 = M = OV
Other Data Inputs
Apply
4.SV
Apply
GND
Apply
4.SV
Apply
GND
Output
Under
Test
tpLH
tpHL
A
None
S
Remaining
A
Remaining
s.Cn
Fi
tpLH
tpHL
S
A
None
Remaining
A
Remaining
S.C n
Fi
A
None
None
Remaining
AandS. Cn
is
S
A
None
None
Remaining
AandS.Cn
is
A
S
None
None
Remaining
AandS. Cn
G
S
None
A
None
Remaining
AandS. Cn
G
A
None
S
Remaining
A
Remaining
s.Cn
A=B
tpLH
tpHL
S
A
None
Remaining
A
Remaining
s.Cn
A=B
tpLH
tpHL
A
S
None
None
Remaining
AandS. Cn
Cn +4
tPLH
tpHL
S
None
A
None
Remaining
A and S. Cn
Cn +4
tpLH
tpHL
Cn
None
None
All
AandS
None
Cn +4
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
S
2·224
Logic Mode Test Table III
Other Input
Same Bit
Input
Under
Test
Symbol
Function Inputs S1 = S2 =
M
=
4.5V,
so =
S3
=
Other Data Inputs
Apply
4.5V
Apply
GND
Apply
4.5V
Apply
GND
&;
.....
OV
CD
.....
Output
Under
Test
tpLH
tpHL
A
S
None
None
Remaining
AandB, Cn
AnyF
tpLH
tpHL
S
A
None
None
Remaining
AandS, Cn
AnyF
Functional Description
The 'LS181 is a 4-bit high speed parallel Arithmetic Logic
Unit (ALU). Controlled by the four Function Select inputs
(SO-S3) and the Mode Control input (M), it can perform all
the 16 possible logic operations or 16 different arithmetic
operations on active HIGH or active LOW operands. The
Function Table lists these operations
When the Mode Control input (M) is HIGH, all internal carries are inhibited and the device performs logic operations
on the individual bits as listed. When the Mode Control input
is LOW, the carries are enabled and the device performs
arithmetic operations on the two 4-bit words. The device
incorporates full internal carry lookahead and provides for
either ripple carry between devices using the Cn + 4 output,
or for carry lookahead between packages using the signals
P (Garry Propagate) and G (Carry Generate). In the ADD
mode, P indicates that F is 15 or more, while G indicates
that F is 16 or more. In the SUBTRACT mode, P indicates
that F is zero or less, while G indicates that F is less than
zero. P and G are not affected by carry in. When speed
requirements are not stringent, it can be used in a simple
ripple carry mode by connecting the Carry output (Cn+ 4)
signal to the Carry input (Cn) of the next unit. For high speed
operation the device is used in conjunction with the 9342 or
93S42 carry lookahead circuit. One carry lookahead pack-
age is required for each group of four 'LS181 devices. Carry
lookahead can be provided at various levels and offers high
speed capability over extremely long word lengths.
The A = B output from the device goes HIGH when all four
F outputs are HIGH and can be used to indicate logiC equivalence over four bits when the unit is in the subtract mode.
The A = B output is open-collector and can be wired-AND
with other A = B outputs to give a comparison for more
than four bits. The A = B signal can also be used with the
Cn +4 signal to indicate A> B and A < B.
The Function Table lists the arithmetic operations that are
performed without a carry in. An incoming carry adds a one
to each operation. Thus, select code LHHL generates A
minus B minus 1 (2s complement notation) without a carry
in and generates A minus B when a carry is applied. Because subtraction is actually performed by complementary
addition (1 s complement), a carry out means borrow; thus a
carry is generated when there is no underflow and no carry
is generated when there is underflow. As indicated, this device can be used with either active LOW inputs producing
active LOW outputs or with active HIGH inputs producing
active HIGH outputs. For either case the table lists the operations that are performed to the operands labeled inside the
logiC symbol.
Function Table
Mode Select
Inputs
Active LOW Operands
& Fn Outputs
Active HIGH Operands
& Fn Outputs
S3
S2
S1
SO
Logic
(M = H)
Arithmetic' •
(M = L)(Cn = L)
Logic
(M = H)
Arithmetic"
(M = L)(Cn = H)
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
H
A
AB
A+B
Logic 1
A minus 1
AB minus 1
AB minus 1
minus 1
A
A+B
AB
Logic 0
A
A+B
A+S
minus 1
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
H
A+B
B
AEIlB
A+B
A plus (A + S)
AB plus (A + S)
A minus B minus 1
A+B
AB
S
AEIlB
AB
ApiusAB
(A + B) plus AS
A minus B minus 1
AB minus 1
H
H
H
H
L
L
L
L
L
L
H
H
L
H
L
H
AB
AEIlB
B
A+B
A plus (A + B)
AplusB
AS plus (A + B)
A+B
A+B
AEIlB
B
AB
ApiusAB
AplusB
(A + B) plus AB
AB minus 1
H
H
H
H
H
H
H
H
L
L
H
H
L
H
L
H
Logic 0
AS
AB
A
A plus A'
AB plus A
AS minus A
A
LogiC 1
A+S
A+B
A
AplusA'
(A + B) plus A
(A + S)plusA
A minus 1
'Each bit is shifted to the next move significant position.
"Arithmetic operaUons expressed In 2s complement notation.
2-225
.r-------------------------------------------------------------------------------------,
CD
!i
Logic Symbols
Active High Operands
2
1 23 22 21 20 19 18
7
16
8
54LS/74LS181
4-BIT ARITHMETIC
LOGIC UNIT
6
5
14
17
4
P
15
3
9
10
11
13
TL/F/9821-3
Active Low Operands
2
1 23 22 21 20 19 18
7
16
8
54LS/74LS181
4-BIT ARITHMETIC
LOGIC UNIT
6
5
14
17
4
15
3
9
10
11
Vee = Pin 24
GND = Pin 12
2-226
13
TUF/9821-4
Ii)
....
....
Logic Diagram
(II)
,:;1 ......--+++.;==1
» .......- - - - 0 <>
1
1::1---1-+++.......-1
I~
---1-+++.......-1
,;; ......--f-++..;==I
,~
1<
'"...
"
0
''''
,i:
I S l - - - - -.......-I
~------------------------------~~
2-227
~
0)
r------------------------------------------------------------------------------------,
~
!I ~National
o• ~ Semiconductor
0)
~
!I DM54LS 190/DM74LS 190, DM54LS 191/DM74LS 191
Synchronous 4-Bit Up/Down Counters with Mode Control
General Description
These circuits are synchronous, reversible, up/down counters. The LS191 is a 4-bit binary counter and the LS190 is a
BCD counter. Synchronous operation Is provided by having
all flip-flops clocked simultaneously, so that the outputs
change simultaneously when so Instructed by the steering
logic. This mode of operation eliminates the output counting
spikes normally associated with asynchronous (ripple clock)
counters.
The outputs of the four master-slave flip-flops are triggered
on a low-to-high level transition of the clock input, if the
enable input is low. A high at the enable input inhibits counting. Level changes at either the enable input or the down/
up input should be made only when the clock input is high.
The direction of the count is determined by the level of the
down/up input. When low, the counter counts up and when
high, it counts down.
These counters are fully programmable; that is, the outputs
may be preset to either level by placing a low on the load
input and entering the desired data at the data inputs. The
output will change independent of the level of the clock input. This feature allows the counters to be used as moduloN dividers by simply modifying the count length with the
preset inputs.
The clock, down/up, and load inputs are buffered to lower
the drive requirement; which significantly reduces the number of clock drivers, etc., required for long parallel words.
Two outputs have been made available to perform the cascading function: ripple clock and maximum/minimum count.
The latter output produces a high-level output pulse with a
duration approximately equal to one complete cycle of the
clock when the counter overflows or underflows. The ripple
clock output produces a low-level output pulse equal in
width to the low-level portion of the clock input when an
overflow or underflow condition exists. The counters can be
easily cascaded by feeding the ripple clock output to the
enable input of the succeeding counter if parallel clocking Is
used, or to the clock input if parallel enabling is used. The
maximum/minimum count output can be used to accomplish look-ahead for high-speed operation.
Features
•
•
•
•
•
•
•
•
•
•
Counts 8-4-2-1 BCD or binary
Single down/up count control line
Count enable control input
Ripple clock output for cascading
Asynchronously presettable with load control
Parallel outputs
Cascadable for n-bit applications
Average propagation delay 20 ns
Typical clock frequency 25 MHz
Typical power dissipation 100 mW
Connection Diagram
Dual-In-Llne-Package
.
INPUTS
I
INPUTS
OUT!'UTS
DATA
RIPPLE MAXI
A
CLOCK CLOCK MIN
C
16
15
14
LOAD
13
12
11
4
5
6
DATA
C
10
DATA
D
9
--
2
DATA
~
INPUT
QB
3
QA
OUTPUTS
ENABLE DOWNI Qc
G
UP,
INPUTS
7
.
QD
Is
GND
OUTPUTS
TLlF/6405·1
Order Number DM54LS190J, DM54LS191J, DM54LS190W,
DM54LS191W, DM74LS190M, DM74LS191M, DM74LS190N, or DM74LS191N
See NS Package Number
J16A, M16A, N16A or W16A
2-228
Absolute Maximum Ratings
~
....
(Note)
CO
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
DM54LS
- 55'C to + 125'C
DM74LS
O'Cto +70'C
Storage Temperature Range
-65'C to + 150'C
Recommended Operating Conditions
Symbol
DM54LS190, LS191
Parameter
DM74LS190, LS191
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
0.7
0.8
V
mA
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
10H
High Level Output Current
-0.4
-0.4
10L
Low Level Output Current
4
8
mA
feLK
Clock Frequency (Note 4)
20
MHz
tw
Pulse Width
(Note 4)
I
I
2
2
0
20
V
0
Clock
25
25
Load
35
35
ns
tsu
Data Setup Time (Note 4)
20
20
tH
Data Hold Time (Note 4)
0
0
ns
tEN
Enable Time to Clock (Note 4)
30
30
ns
TA
Free Air Operating Temperature
-55
125
ns
0
70
'C
Max
Units
-1.5
V
'LS190 and 'LS191 Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
=
= -
VI
Input Clamp Voltage
Vee
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
VIL = Max, VIH = Min
VOL
Low Level Output
Voltage
Vee
VIL
Input Current @ Max
Input Voltage
= 4 mA, Vee =
Vee = Max
VI = 7V
High Level Input
Current
=
=
Min,ll
IIH
IlL
los
Typ
(Note 1)
DM54
2.5
3.4
DM74
2.7
18 mA
Min, 10L = Max
Max, VIH = Min
10L
II
Min
Conditions
Min
V
3.4
DM54
0.25
0.4
DM74
0.35
0.5
DM74
0.25
0.4
Enable
0.3
Others
0.1
Vee = Max
VI = 2.7V
Enable
60
Others
20
Low Level Input
Current
Vee = Max
VI = 0.4V
Enable
-1.08
Others
-0.4
Short Circuit
Output Current
Vee = Max
(Note 2)
DM54
-20
-100
DM74
-20
-100
Supply Current
Vee = Max (Note 3)
Icc
Nate 1: All typlcals are at Vee = 5V, TA = 25'C.
Nate 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Nate 3: Icc is measured with all inputs grounded and all outputs open.
Nate 4: TA = 25'C and Vee = 5V.
2-229
20
35
V
mA
/LA
mA
mA
mA
Q
•
~
....
CO
....
'LS190 and 'LS191 Switching Characteristics
at Vee = 5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
From (Input)
To (Output)
RL = 2kO
CL = 15pF
Min
Max
CL = 50pF
Min
Units
Max
fMAX
Maximum Clock
Frequency
tpLH
Propagation Delay Time
Low to High Level Output
Load to
AnyQ
33
43
ns
tpHL
Propagation Delay Time
High to Low Level Output
Load to
AnyQ
50
59
ns
tpLH
Propagation Delay Time
Low to High Level Output
Data to
AnyQ
22
26
ns
tpHL
Propagation Delay Time
High to Low Level Output
Data to
AnyQ
50
62
ns
tpLH
Propagation Delay Time
Low to High Level Output
Clock to
Ripple Clock
20
24
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clock to
Ripple Clock
24
33
ns
tpLH
Propagation Delay Time
Low to High Level Output
Clock to
AnyQ
24
29
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clock to
AnyQ
36
45
ns
tpLH
Propagation Delay Time
Low to High Level Output
Clock to
Max/Min
42
47
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clock to
Max/Min
52
65
ns
tpLH
Propagation Delay Time
Low to High Level Output
Up/Down to
Ripple Clock
45
50
ns
tpHL
Propagation Delay Time
High to Low Level Output
Up/Down to
Ripple Clock
45
54
ns
tpLH
Propagation Delay Time
Low to High Level Output
Down/Up to
Max/Min
33
36
ns
tpHL
Propagation Delay Time
High to Low Level Output
Down/Up to
Max/Min
33
42
ns
tpLH
Propagation Delay Time
Low to High Level Output
Enable to
Ripple Clock
33
36
ns
tpHL
Propagation Delay Time
High to Low Level Output
Enable to
Ripple Clock
33
42
ns
20
2-230
20
MHz
----------------------------------------------------------------------------~----: ~
Logic Diagrams
LS190 Decade Counters
•
fii
CLOCK(14)
-0.
CD
-0.
-
OOWNI (5)
UP
~"'--->VJ--i-----:=~
DATA (15)
NPUTA
ENABLEG
r
~
I
]
-
_.J==~=r]
(13) RIPPLE
CLOCK
(12) MAXIMIN
'---l~I--""--~-OUTPUT
y
(4)~
~
~n~(1~O)~--~~~~~ttil:tj"ph!--~~--~--_,6
Lr-
INPUT C
r-- _
~ ·k
'::r)L>-
LOAD
(11)
Pin (16) = Vee. Pin (8) = GND
TL/F/6405-2
2-231
J
PRESE~ ~~
OUTPUT Oc
CLOCK
'y"'1
•
....
....
0)
~
Logic Diagrams (Continued)
LS191 Binary Counters
•
C)
0)
....
~
( 14)
CLOCK
DOWN I
(5)
~I
....
UP
r
DATA (15)
INPUT A
ENABLEG
(4
~RIPPLE
-Ef
"'J
)~
CLOCK
(12) MAXI MIN
OUTPUT
-F
J
J..
---~OUTP
J PRESET
QA
~"CLOCK
~
DATA (1)
INPUTB
L---
"J.
[
n
-
kCLOCK
~
KCLEARQeh
r
f--J
~
--
j
I--
CLOCK
1
PRESET ~
OUTPUTQD
J
aD
L..c/>CLOCK
~L.""Y"~
-y
TL/F/6405-3
2-232
PRESET ~~O
UTPUTQC
QC
~ KCLyRQC~
Iy
tt»
I
b
:rp
(11)
PRESEJB ~ OUTPUTQe
-V
L
LOAD
1--1 J
J
E3
DATA (9)
INPUTD
KC~RQA~
11"
g;:p
DATA (10)
INPUTC
f-
Pin 16)
= Vee, Pin (8) = GND
...o
lii
Timing Diagrams
CD
LS190 Decade Counters
Typical Load, Count, and Inhibit Sequences
LOAD
DATA
•
......
lii
L
CD
r
INPUTS
B
:
CLOCK
DOWN/UP
ENABLE
H
L
H
-H-~
RIPPLE CLOCK: : ..
'
--I
r----t---r-r--.
17
8
9
0 1 2
2 2 1 0 9
8
7
!jl--COUNT UP
'INHIBIT
I--COUNT DOWN-I
I
LOAD
TUF/6405-4
LS191 Binary Counters
Typical Load, Count, and Inhibit Sequences
LOAD
DATA \ :
INPUTS :
CLOCK
DOWN/UP
ENABLE
OA--
_-IH
Oa-"";
Oc : : ...
' -tt---,
00 --I
- _j-I-t+---"~--r--~~--~~-----
MAX/MIN
'----t----+-+---'
-I
--4
-H-~ r----t---+-+---,
RIPPLE CLOCK: : ..
'
--I
113 14 15
0
1 2
!jl--COUNT UP
2
2
1
0
15 14
13
I INHIBIT II-COUNT DOWN--I
LOAD
TUF/6405-5
2·233
s:
!i
~ National
~ Semiconductor
54LS192/DM74LS192 Up/Down Decade Counter
with Separate Up/Down Clocks
General Description
The 'LS192 is an up/down BCD decade (8421) counter.
Separate Count Up and Count Down Clocks are used and in
either counting mode the circuits operate synchronously.
The outputs change state synchronous with the LOW-toHIGH transitions on the clock inputs.
Separate Terminal Count Up and Terminal Count Down outputs are provided which are used as the clocks for a subsequent stage without extra logic, thus simplifying multistage
counter designs. Individual preset inputs allow the circuits to
be used as programmable counters. Both the Parallel Load
(pc) and the Master Reset (MR) inputs asynchronously
override the clocks.
Connection Diagram
Logic Symbol
Dual-In-Llne Package
P1- 1
01- 2
00- 3
16 -Vee
15 ~PO
141-MR
CPo- "
CP u - 5
02- 6
13 I-TCD
12 I-TCu
11 f-PL
03- 7
GND- 8
10
XYi'fi
PL PO P1 P2 P3
5 - CPu
4 - CPo
TCu ~12
8
TCo ~13
MR 00 01 02 03
TUF/l017B-2
vee = Pin 16
~P2
GND
9 ~P3
= PinS
TUF/IOI7B-l
Order Number 54LS192DMOB, 54LS192FMOB,
54LS192LMOB, DM74LS192M or DM74LS192N
See NS Package Number E20A, J16A,
M16A, N16E or W16A
Pin Names
CPu
CPo
MR
PL
PO-P3
00-03
TCo
TCu
Mode Select Table
Description
Count Up Clock Input
(Active Rising Edge)
Count Down Clock Input
(Active Rising Edge)
Asynchronous Master Reset Input
(Active HIGH)
Asynchronous Parallel Load Input
(Active LOW)
Parallel Data Inputs
Flip-Flop Outputs
Terminal Count Down (Borrow)
Output (Active LOW)
Terminal Count Up (Carry)
Output (Active LOW)
MR
PL
CPu
CPo
Mode
H
L
L
L
L
X
X
X
X
X
H
.../
H
H
H
.../
Reset (Asyn.)
Preset (Asyn.)
No Change
Count Up
CountDown
L
H
H
H
H = HIGH Voltage Level
L = LOW Voltage Level
x = Immaterial
2-234
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
54lS
-55·Cto +125·C
DM74lS
O·Cto +70·C
- 65·C to + 150·C
Storage Temperature Range
Recommended Operating Conditions
Symbol
54LS192
Parameter
Vee
Supply Voltage
VIH
High level Input Voltage
VIL
low level Input Voltage
10H
High level Output Voltage
DM74LS192
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
2
V
V
0.7
0.8
V
-0.4
-0.4
mA
8
mA
70
·C
10L
low level Output Current
TA
Free Air Operating Temperature
to (H)
ts(l)
Setup Time HIGH or lOW
Pnto Pl
20
20
20
20
ns
th (H)
th (l)
Hold Time HIGH or lOW
Pnto Pl
3
3
3
3
ns
Iw (l)
CP Pulse Width lOW
17
17
ns
Iw (l)
Pl Pulse Width lOW
20
20
ns
Iw(H)
MR Pulse Width HIGH
15
15
ns
tree
Recovery Time, MR to CP
3
3
ns
tree
Recovery Time, Pl to CP
10
10
ns
4
-55
125
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
VI
Input Clamp Voltage
VOH
High level Output Voltage
VOL
low level Output Voltage
Conditions
= Min,ll = -18mA
Vee = Min,loH = Max,
VIL = Max
Vee
= Min, 10L = Max,
VIH = Min
10L = 4 mA, Vee = Min
Vee = Max, VI = 10V
Vee
II
Input Current @ Max
Input Voltage
IIH
High level Input Current
Vee
IlL
low level Input Current
Vee
los
Short Circuit
Output Current
Vee
Max
(Note 2)
Supply Current
Vee = Max, MR, Pl
Other Inputs = 4.5V
Icc
Note 1: All
Min
=
=
=
Max, VI
Max, VI
=
=
54lS
2.5
DM74
2.7
Typ
(Note 1)
Max
Units
-1.5
V
V
54lS
0.4
DM74
0.5
DM74
0.4
0.1
V
mA
2.7V
20
IJoA
0.4V
-0.4
mA
=
54lS
-20
-100
DM74
-20
-100
GND
typicals are at Vee = SV, TA = 2S'e.
one output should be shorted at a time, and the duration should not excead one second.
Note 2: Not more than
2-235
31
mA
mA
FII
Switching Characterisitcs
Vee = +0.5V, TA = +2SOC (See 'Section 1 for waveforms and load configurations)
RL = 2k
CL = 15pF
Parameter
Symbol
Units
Min
Max
MHz
f max
Maximum Count Frequency
tpLH
tpHL
Propagation Delay
CPu or CPo to an
30
31
28
tpLH
tpHL
Propagation Delay
CPutoTCu
16
21
tpLH
tpHL
Propagation Delay
CPo to TCo
16
24
tpLH
tpHL
Propagation Delay
PntoOn
20
30
tpLH
tpHL
Propagation Delay
PLtoO n
32
30
tpHL
Propagation Delay, MR to an
25
ns
ns
ns
ns
Functional Description
The '192 is an asynchronously presettable decade and 4-bit
binary synchronous up/down (reversible) counter. The operating modes of the '192 decade counter and the '193 binary counter are identical, with the only difference being the
count sequences as noted in the State Diagram. Each circuit contains four master/slave flip-flops, with internal gating and steering logic to provide master reset, individual preset, count up, and count down operations.
Each flip-flop contains JK feedback from slave to master
such that a LOW-to-HIGH transition on its T input causes
the slave, and thus the a output to change state. Synchronous switching, as opposed to ripple counting, is achieved
by driving the steering gates of all stages from a common
Count Up line and a common Count Down line, thereby
causing all state changes to be initiated simultaneously. A
LOW-to-HIGH transition on the Count Up input will advance
the count by one; a similar transition on the Count Down
input will decrease the count by one. While counting with
one clock input, the other should be held HIGH. Otherwise,
the circuit will either count by twos or not at all, depending
on the state of the first flip-flop, which cannot toggle as long
as either Clock input is LOW.
The Terminal Count Up (TI:u) and Terminal Count Down
(fOo) outputs are normally HIGH. When a circuit has
reached the maximum count state (9 for the '192, 15 for the
'193), the next HIGH-to-LOW transition of the Count Up
Clock will cause TCu to go LOW. TCu will stay LOW until
CPu goes HIGH again, thus effectively repeating the Count
Up Clock, but delayed by two gate delays. Similarly, the TCo
output will go LOW when the circuit is in the zero state and
the Count Down Clock goes LOW. Since the TC outputs
repeat the clock waveforms, they can be used as the clock
Input signals to the next higher order circuit in a multistage
counter.
TCu = 00-03- CPu
TCo = 00 - 01 - 02 - 03 - CPo
Each circuit has an asynchronous parallel load capability
permitting the counter to be reset. When the Parallel Load
(PL) and the Master Reset (MR) inputs are LOW, information present on the Parallel Data inputs (PO-P3) is loaded
into the counter and appears on the outputs regardless of
the conditions of the clock inputs. A HIGH signal on the
Master Reset input will disable the preset gates, override
both Clock inputs, and latch each a output in the LOW
state. If one of the Clock inputs is LOW during and after a
reset or load operation, the next LOW-to-HIGH transition of
that Clock will be interpreted as a legitimate signal and will
be counted.
State Diagram
.--.
0,
_.--.
-I"'"'"'L.
--1..!.J:"---
2
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--1!J:"---
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-._~-
2-236
TLIF110178-4
...
~
Logic Diagram
>-5
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2·237
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r-------------------------------------------------------------------------,
~ National
~ Semiconductor
54LS 193/DM54LS 193/DM74LS 193
Synchronous 4·Bit Up/Down Binary
Counters with Dual Clock
General Description
This circuit is a synchronous up/down 4-bit binary counter.
Synchronous operation is provided by having all flip-flops
clocked simultaneously, so that the outputs change together when so instructed by the steering logic. This mode of
operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters.
The outputs of the four master-slave flip-flops are triggered
by a low-to-high level transition of either count (clock) input.
The direction of counting is determined by which count Input
is pulsed while the other count input is held high.
The counter is fully programmable; that is, each output may
be preset to either level by entering the desired data at the
inputs while the load input is low. The output will change
Independently of the count pulses. This feature allows the
counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs.
A clear input has been provided which, when taken to a high
level, forces all outputs to the low level; independent of the
count and load inputs. The clear, count, and load inputs are
buffered to lower the drive requirements of clock drivers,
etc., required for long words.
These counters were designed to be cascaded without the
need for external circuitry. Both borrow and carry outputs
are available to cascade both the up and down counting
functions. The borrow output produces a pulse equal in
width to the count down input when the counter underflows.
Similarly, the carry output produces a pulse equal in width to
the count down input when an overflow condition exists.
The counters can then be easily cascaded by feeding the
borrow and carry outputs to the count down and count up
inputs respectively of the succeeding counter.
Features
•
•
•
•
•
Fully independent clear input
Synchronous operation
Cascading circuitry provided internally
Individual preset each flip-flop
Alternate Military/Aerospace device (54LS193) is available. Contact a National Semiconductor Sales Office/
Distributor for specifications..
Connection Diagram
Dual·ln-Llne Package
INPUTS
,----.--.,
Vee
116
t
OUll'UTS
r------.
.
I I
! ! I
-
~
I I
1
DATA B
INPUT
.
INPUTS
DATA DATA
D
C
CLEAR BORFW CAjRY LOtD
9
15
114
13
12
11
110
DATA
12
13
QB
QA
'------'
OUTPUTS
I I
4
5
COUNT COUNT
DOWN
UP
'------'
INPUTS
16
17
QD
Qc
'------'
Is
GND
OUll'UTS
TLIF16406-1
Order Number 54LS193DMQB, 54LS193FMQB, 54LS193LMQB,
DM54LS193J, DM54LS193W, DM74LS193M or DM74LS193N
See NS Package Number E20A, J16A, M16A, N16E or W16A
2-238
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
DM54LS and 54LS
-55'Cto + 125'C
DM74LS
O'Cto +70'C
Storage Temperature Range
-65'Cto +150'C
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table wi" define
the conditions for actual device operation.
Recommended Operating Conditions
Symbol
Vcc
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
DM74LS193
DM54LS193
Parameter
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
V
V
2
0.7
0.8
V
mA
IOH
High Level Output Current
-0.4
-0.4
10L
Low Level Output Current
4
8
mA
fCLK
Clock Frequency (Note 1)
0
25
0
25
MHz
Clock Frequency (Note 2)
0
20
0
20
MHz
tw
Pulse Width of Any Input (Note 6)
20
20
ns
tsu
Data Setup Time (Note 6)
20
20
ns
tH
Data Hold Time (Note 6)
0
0
ns
tREL
Release Time (Note 6)
40
40
TA
Free Air Operating Temperature
Electrical Characteristics
Symbol
-55
125
0
'C
over recommended operating free air temperature range (unless otherwise noted)
Parameter
Conditions
VI
Input Clamp Voltage
VOH
High Level Output
Voltage
= Min, II = -18 mA
Vee = Min, 10H = Max
VIL = Max, VIH = Min
Low Level Output
Voltage
Vcc = Min, IOL = Max
VIL = Max, VIH = Min
VOL
ns
70
Min
Typ
(Note 3)
Vcc
10L
= 4 mA, Vcc = Min
= Max, VI = 7V
II
Input Current @ Max
Input Voltage
Vcc
IIH
High Level Input Current
Vcc
IlL
Low Level Input Current
los
Short Circuit
Output Current
= Max, VI = 2.7V
Vcc = Max, VI = 0.4V
Vcc = Max
(Note 4)
DM54
2.5
3.4
DM74
2.7
3.4
Units
-1.5
V
V
DM54
0.25
DM74
0.35
0.5
DM74
0.25
0.4
0.4
0.1
mA
20
p.A
mA
-20
-100
DM74
-20
-100
19
V
-0.4
DM54
Supply Current
Vcc = Max (Note 5)
Icc
Nole 1: CL = IS pF, RL = 2 kfi, IA = 2S'C and Vee = SV.
Nole 2: CL = SO pF, RL = 2 kfi, IA = 25'C and Vee = SV.
Nole 3: All typicals are at Vee = SV, TA = 2S'C.
Nole 4: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 5: lee is measured with all outputs open, CLEAR and LOAD inputs grounded, and all other inputs at 4.5V.
Nole 6: TA = 25'C and Vee = SV.
2-239
Max
34
mA
mA
Switching Characteristics
at Vee = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
RL = 2kO
Symbol
Parameter
From (Input)
To (Output)
CL = 15pF
Min
Max
CL = 50pF
Min
Max
20
25
Units
MHz
fMAX
Maximum Clock Frequency
tpLH
Propagation Delay Time
Low to High Level Output
Count Up
to Carry
26
30
ns
tpHL
Propagation Delay Time
High to Low Level Output
Count Up
to Carry
24
36
ns
tpLH
Propagation Delay Time
Low to High Level Output
CountDown
to Borrow
24
29
ns
tpHL
Propagation Delay Time
High to Low Level Output
CountDown
to Borrow
24
32
ns
tpLH
Propagation Delay Time
Low to High Level Output
Either Count
to Any 0
38
45
ns
tpHL
Propagation Delay Time
High to Low Level Output
Either Count
to Any 0
47
54
ns
tpLH
Propagation Delay Time
Low to High Level Output
Load to
Any 0
40
41
ns
tpHL
Propagation Delay Time
High to Low Level Output
Load to
Any 0
40
47
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clear to
Any 0
35
44
ns
2·240
r-------------------------------------------------------------~~
....
Logic Diagram
CD
Co)
DATA (15)
INPUT A
DOWN (4)
COUNT
UP (5)
COUNT
"""
~.
'1-
(13) BORROW
0 UTPUT
"'f
(12) cARRY
0 UTPUT
...I
.....
~r-~,
T
-
OA
....
Lrp tL)=r
-
DATA (1)
INPUT B
r-r""
..J
LL
r-' "- i---"
Oe
(2)
~ OUTPUT
0e
T
cr
OATA (10)
INPUT C
Oe
~ tL)=r
~
r=w""
1--1
r-'l....
-
-DATA (9)
INPUT D
CLEA
R (14)
-
....
(6)
Oc~~ OUTPUT
Oc
T
Oc
=r)c> tL)=r
-
-
II
"""
rL-"""
.... 1--1
r-'~ I 00
(7)
~ OUTPUT 00
T
00
LOAD
(11)
."
2·241
~
-
TLlF/6406-2
...
!J
C':I
en
Timing Diagrams
Typical Clear, Load, and Count Sequences
CL~R~~
_______________________________________________________
LOAD
A
~~--~----------------------------------------------.
.. ---------------------------------------------I
.-----------------------------------------------
DATA
B __
~_+--~~----------------------------------------------.
C
~~--~----------------------------------------------.
D
~~--~----------------------------------------------.
._---------------------------------------------I
._----------------------------------------------
roum-----~~--+-+---~
UP
COUNT-----~~--~+---~-------------------+--~
DOWN
OUTPUTS
CARRY
BORROW
,.---.......
.-----.
cmR
PRESET
I
r-14
15
0
coum UP
1
21 I
-----i
r--1
0
15
COUNT DOWN
14
13
1
----i
TLlF/6406-3
Note A: Clear overrides loed, data, and count Inputs.
Note B: When counting up, count-down input must be high; when counting down, count-up input must be high.
2-242
~National
~ Semiconductor
54LS194A/DM74LS194A 4-Bit
Bidirectional Universal Shift Register
General Description
This bidirectional shift register is designed to incorporate
virtually all of the features a system designer may want in a
shift register; they feature parallel inputs, parallel outputs,
right-shift and left-shift serial inputs, operating-mode-control
inputs, and a direct overriding clear line. The register has
four distinct modes of operation, namely:
Parallel (broadside) load
Shift right (in the direction QA toward QD)
Shift left (in the direction QD toward QA)
Inhibit clock (do nothing)
Serial data for this mode is entered at the shift-right data
input. When SO is low and S1 is high, data shifts left synchronously and new data is entered at the shift-left serial
input.
Clocking of the flip-flop is inhibited when both mode control
inputs are low.
Features
Synchronous parallel loading is accomplished by applying
the four bits of data and taking both mode control inputs, SO
and S 1, high. The data is loaded into the associated flipflops and appear at the outputs after the positive transition
of the clock input. During loading, serial data flow is inhibited.
Shift right is accomplished synchronously with the rising
edge of the clock pulse when SO is high and S1 is low.
• Parallel inputs and outputs
• Four operating modes:
Synchronous parallel load
Right shift
Left shift
Do nothing
• Positive edge-triggered clocking
• Direct overriding clear
Connection Diagram
Dual-In-Llne Package
OUTPUTS
aC
as
14
00
13
CLOCK
12
11
51
SO
10
9
-
2
CLEAR SHIFT
RIGHT
SERIAL
INPUT
4
3
6
A ____
8
__/- - - - -0J
~
~
PARALLEL INPUTS
SHI:T
LEFT
Gl:
SERIAL
INPUT
TUF/6407-1
Order Number 54LS194ADMQB, 54LS194AFMQB,
54LS194ALMQB, DM74LS194AM or DM74LS194AN
See NS Package Number E20A, J16A, M16A, N16E or W16A
2-243
•
Absolute Maximum Ratings (Note)
If Military/Aerospace specIfIed devIces are required,
please contact the NatIonal SemIconductor Sales
OffIce/DIstributors for availabilIty and specifIcatIons..
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
54LS
- 55'C to + 125'C
DM74LS
O'Cto +70'C
Storage Temperature Range
- 65'C to + 150'C
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Recommended Operating Conditions
Symbol
54LS194A
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
10H
High Level Output Current
Max
MIn
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
Low Level Output Current
fCLK
Clock Frequency (Note 1)
30
Clock Frequency (Note 2)
Pulse Width
(NoteS)
Setup Time
(Note 3)
tsu
Units
Nom
10L
tw
DM74LS194A
MIn
2
0.7
0.8
V
-0.4
-0.4
mA
8
mA
4
0
25
22
0
20
Clock
17
20
Clear
12
20
Mode
25
30
Data
16
20
0
tH
Hold Time (Note 3)
0
0
tREL
Clear Release Time (Note 3)
18
25
Free Air Operating Temperature
Note 1: CL = 1S pF, TA = 25'C and Vee = SV.
Note 2: CL = 50 pF. RL = 2 kG, TA = 25'C and Vee = SV.
Not. 3: TA = 2S'C and Vee = SV.
TA
V
V
-55
125
MHz
ns
ns
ns
ns
0
70
'C
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
= Min, II = -18mA
= Min, 10H = Max
VIL = Max, VIH = Min
VCC = Min, 10L = Max
VIL = Max, VIH = Min
10L = 4 mA, Vee = Min
Vee = Max, VI = 7V
VI
Input Clamp Voltage
Vee
VOH
High Level Output
Voltage
Vee
VOL
Low Level Output
Voltage
Min
54LS
2.5
DM74
2.7
Typ
(Note 4)
Max
Unlta
-1.5
V
V
3.4
54LS
0.4
DM74
0.35
0.5
V
0.4
I,
Input Current @ Max
Input Voltage
IIH
High Level Input Current
VCC
20
IJoA
IlL
Low Level Input Current
Vee
-0.4
mA
los
Short Circuit
Output Current
0.1
= Max, VI = 2.7V
= Max, VI = 0.4V
Vee = Max
54LS
-20
-tOO
(Note 5)
DM74
-20
-tOO
mA
rnA
Supply Current
23
mA
VCC = Max (Note 6)
15
lee
Note 4: All typIcals are at Vee = SV. TA = 2S'O.
Note 5: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 8: With all outputs open. inputs Athrough 0 grounded, and 4.SV applied to SO, $1, CLEAR. and the serial inputs. lee Is tested with momentary ground. then
4.SV applied to CLOCK.
2-244
Switching Characteristics at Vcc = 5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
54LS
From (Input)
Symbol
Parameter
To (Output)
CL
=
DM74LS
CL = 50pF
RL = 2kO
15pF
Min
Max
Min
Unlta
Max
fMAX
Maximum Clock
Frequency
tpLH
Propagation Delay Time
Low to High Level Output
Clock to
AnyC
21
26
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clock to
AnyC
24
35
ns
30
20
MHz
Propagation Delay Time
Clear to
26
38
ns
High to Low Output
AnyC
Nole 1: All typlcals are at Vee = SV, TA = 25'C.
Nole 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: With all outputs open, Inputs A through D grounded, and 4.5V applied to so, SI, CLEAR, and the serial Inputs, Icc Is tesled with momentary ground, then
4.SV applied to CLOCK.
tpHL
Logic Diagram
LS194A
PARAL.LElINPUTS
•141
A
(31
CON~~:
{
(\01
S1
INPUTS
,.,
D
C
lSi
......
-yo
......
...
v
(9),....,
so
SHIFT
RIGHT (2)
SHIFT
171 LEFT
SERIAL
INPUT
SERIAL
INPUT
s ac
s aD
CLOCK
R
CLOCK
CLOCK
R
CLEAR
CLEAR
W
CLOCK fl1 ) ' "
CL.EAR1II V
5 a.
;LOCK
I
"
-v
R
ClEAR
I
CLEAR
I
(15)
(14)
aA
(121
113)
a.
ac
Do
PARALLEL OUTPUTS
TL/F/6407-2
Function Table
Inputs
Clear
L
H
H
H
H
H
H
H
Mode
Clock
S1
SO
X
X
X
X
X
H
L
L
H
H
L
H
H
H
L
L
L
t
t
t
t
t
L
X
Outputs
Serial
Parallel
Left
Right
A
X
X
X
X
X
X
X
X
X
X
H
L
X
X
X
X
X
H
L
X
X
X
X
a
B
X
X
b
X
X
X
X
X
C
X
X
0
X
X
c
d
X
X
X
X
X
X
X
X
X
X
OA
Os
Oc
OD
L
L
Cao
L
CCO
L
Coo
d
CCn
CCn
H
L
COO
CAO
a
H
L
Can
Can
CAO
b
c
CAn
CAn
CCn
CCn
Cao
Can
Can
COn
COn
Ceo
H = High Level (steady state), L = Low Level (steady state), X = Don't Care (any input, including transitions)
t = Transition from low to high level
a, b, c, d = The level of steady state Input at inputs A, B, C or D, respectively.
OAO, Oso, Oeo, 000 = The level of OA, Os, Oe, or 000 respectively, before the indicated steady state input conditions were established.
OAn, OSn, Oen, OOn = The level of OA, Os, 00, respectively, before the most·recent t transition of the clock.
2·245
•
Timing Diagram
Typical Clear, Load, Right-Shlft, Left-Shlft,lnhlblt, and Clear Sequences
CLOCK
[so
MODE
CONTROL
INPUTS S1
CLEAR
SERIAL [R
DATA
INPUTS L
PARALLEL{:
DATA
INPUTS C
D
OUTPUTS
f:: ~
-+-+--1
Qc:
QD
:-+--+-~
__1--- INHIBIT
CLEAR LOAD
CLEAR
TUF/6407-3
2-246
~National
~ Semiconductor
54LS 195A/DM7 4LS 195A
4-Bit Parallel Access Shift Register
General Description
Features
This 4-bit register features parallel inputs, parallel outputs,
J-K serial inputs, shiftlload control input, and a direct overriding clear. All inputs are buffered to lower the input drive
requirements. The registers have two modes of operation:
•
•
•
•
Parallel (broadside) load
•
Shift (in the direction QA toward Qo)
•
•
Parallel loading is accomplished by applying the four bits of
data and taking the shiftlload control input low. The data is
loaded into the associated flip-flop and appears at the outputs after the positive transition of the clock input. During
loading, serial data flow is inhibited.
Synchronous parallel load
Positive-edge-triggered clocking
Parallel inputs and outputs from each flip-flop
Direct overriding clear
J and K inputs to first stage
Complementary outputs from last stage
For use in high-performance:
accumulatorsl processors
serial-to-parallel, parallel-to-serial converters
Typical clock frequency 39 MHz
Typical power dissipation 70 mW
•
•
Shifting is accomplished synchronously when the shiftlload
control input is high. Serial data for this mode is entered at
the J-K inputs. These inputs permit the first stage to perform
as a J-K, D, or T-type flip-flop as shown in the truth table.
Connection Diagram
Dual-In-Llne Package
OUTPUTS
QB
Qc
14
QD
13
SHIFT I
CLOCK LOAD
aD
12
11
10
9
-c
2
CLEAR
J
456
3
K
SERIAL INPUTS
,A
B
.
C
PARALLEL INPUTS
7
D
18
GND
TLiF/6408-1
Order Number 54LS195ADMQB, 54LS195AFMQB,
54LS195ALMQB, DM74LS195AM or DM74LS195AN
See NS Package Number E20A, J16A, M16A, N16E or W16A
2-247
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
54LS
- 55·C to + 125·C
DM74LS
O·Cto +70·C
- 65·C to + 150·C
Storage Temperature Range
Recommended Operating Conditions
Symbol
54LS195A
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
IOH
High Level Output Current
IOL
Low Level Output Current
feLK
Clock Frequency (Note 1)
DM74LS195A
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
2
V
0.8
V
-0.4
-0.4
mA
SO
0
SO
0
8
mA
0
SO
MHz
0
25
MHz
Pulse Width
(NoteS)
Clock
16
16
Clear
14
12
Setup TIme
(NoteS)
Shift/Load
25
25
Data
15
15
tH
Hold Time (Note S)
0
0
tREL
Shift/Load Release Time (Note S)
10
10
Clear Release Time (Note S)
25
25
tsu
Free Air Operating Temperature
1: CL = IS pF, TA = 25"C and Vee = SV.
Note 2: CL = SO pF, RL = 2 kG, TA = 2S'C and Vee = SV.
Note 3: TA = 2S'C and Vee = SV.
TA
-55
V
0.7
4
Clock Frequency (Note 2)
tw
Units
Min
125
ns
ns
ns
ns
0
70
·C
Note
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
= Min,ll = -18 mA
VI
Input Clamp Voltage
Vce
VOH
High Level Output
Voltage
Vce = Min, IOH = Max
VIL = Max, VIH = Min
54LS
2.5
DM74LS
2.7
Low Level Output
Voltage
Vee = Min, IOL = Max
VIL = Max, VIH = Min
54LS
VOL
Input Current @ Max
Input Voltage
Max
Units
-1.5
V
V
S.4
0.4
DM74LS
= 4 mA, Vee = Min
Vee = Max, VI = 7V
IOL
II
Typ
(Note 4)
0.S5
0.5
0.25
0.4
V
0.1
mA
".A
mA
IIH
High Level Input Current
Vee
Low Level Input Current
Vee
-0.4
los
Short Circuit
Output Current
= Max, VI = 2.7V
= Max, VI = O.4V
Vee = Max
20
IlL
54LS
-20
-100
(Note 5)
DM74LS
-20
-100
mA
Supply Current
14
Vee = Max, (Note 6)
21
mA
4: All typlcals are at Vee = SV, TA = 2S'C.
Note 6: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Nole 6: With all Inputs open, SHIFTILOAD grounded, and 4.SV applied to the J, K, and data inputs, lee is measured by applying a momentary ground, then 4.SV 10
the CLEAR and then applying a momentary ground then 4.SV to the CLOCK.
lee
Note
2-248
Switching Characteristics at Vcc =
Symbol
5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
From (Input)
To (Output)
Parameter
54LS
DM74LS
CL = 15pF
RL = 2kO
CL = 50pF
Min
Max
Min
Units
Max
fMAX
Maximum Clock
Frequency
tpLH
Propagation Delay Time
Low to High Level Output
Clock to
AnyQ
21
26
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clock to
AnyQ
24
35
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clear to
AnyQ
26
38
ns
30
25
MHz
Function Table
Inputs
Clear
Shift!
Load
outputs
Serial
Clock
J
Parallel
A
K
B
Qs
QA
C
Qc
X
X
X
X
X
L
L
L
X
X
X
X
X
a
b
C
d
a
b
C
L
t
H
L
X
X
X
X
X
X
QCO
QAO
QSO
H
X
L
H
X
X
X
QSn
QAO
QAO
i
H
L
L
X
X
X
X
L
QSn
QAn
t
H
H
X
X
X
X
H
H
QSn
QAn
t
X
H
H
L
X
X
X
QSn
QAn
aAn
t
H = High Level (sleady slale), L = Low Level (sleady stale), X = Oon'l Care (any input, including Iransilions)
t = Transition from low 10 high level
a, b, c, d = The level of sleady slale Inpul al A, S, C, or 0, respeclively.
OAQ, Oao, Oco, 000 = The level of OA, Oa, Oc, or 00, respeclively, before Ihe indicaled sleady slate Input conditions were established.
OAn, Oan, OCn = The level of OA, Oa, Oe, respectively, before the mosl recenl transition of the clock.
L
H
H
H
H
H
H
QD
QD
L
d
QOO
QCn
QCn
QCn
QCn
H
D
d
000
acn
acn
acn
acn
Logic Diagram
SERIAL
INPUT
,....-......".
J
SHIFT ILOAO (9)
CONTROL
CLOCK(10)
CLEAR(1)
(2)
K
(3)
PARALLEL INPUTS
,
A
(4)
t
~
'-
)
'---
ckn J
~ ~LOCK
RQA
S
-
OAI--
.
(7)
IV IV
'---
CLOCK
R
S OB
'----
mfu.
i CLt
I CLt
(15)
OA
0
(8)
'--
~
,
C
B
(5)
~hl!
~CLOCK
R
S
0
(14)
Oc
I..--
0
(13)
CLOCK
S O0b.
(12)
11)
0000
.
PARALLEL OUTPUTS
TL/F/6408-2
2-249
Timing Diagram
Typical Clear, Shift, and Load Sequences
CLOCK
CLEAR
SERIAL {JK
INPUTS
SHFT/LOAD;:~~::::~~~::::::::::::::::::::::~~~+=::::::::::::::::::::
PARALLEL{:
DATA
~S
C __
~
+-____________________
________
~
D'---+-------+--------------------~r_--t_-----------------
OUTPUTJ~~:
tOc---TI------~r--------00:="""1_ _-+_ _ _ _..... ___
CLEAR
LOAD
TL/F/8408-3
2-250
~National
~ Semiconductor
DM74LS196
Presettable Decade Counter
General Description
Features
The 'LS196 decade ripple counter is partitioned into divideby-two and divide-by-five sections which can be combined
to count either in BCD (8421 l sequence or in a bi-quinary
mode producing a 50% duty cycle output. Both circuit types
have a Master Reset (MRl input which overrides all other
inputs and asynchronously forces all outputs LOW. A Parallel Load input (PLl overrides clocked operations and asynchronously loads the data on the Parallel Data inputs (Pn)
into the flip-flops. This preset feature makes the circuits usable as programmable counters. The circuits can also be
used as 4-bit latches, loading data from the Parallel Data
inputs when PL is LOW and storing the data when PL is
HIGH. In the counting modes, state changes are initiated by
the falling edge of the clock.
• High counting rates-typically 60 MHz
• Choice of counting modes-BCD, bi-quinary, binary
• Asynchronous preset and master reset
Connection Diagram
Logic Symbol
Dual-In-Line Package
PL-l
02- 2
14 -Vee
13 -Mil
8--Cl CPO
P2- 3
PO- 4
12 -03
11 -P3
6--Cl CPl
00- 5
CPl- 6
10 -PI
GND- 7
PL PO PI P2 P3
MR 00 01 02 03
9 -01
8 -CPO
TL/F/l0179-2
= Pin 14
GND = Pin 7
vee
TUF/l0179-1
Order Number DM74LS196M or DM74LS196N
See NS Package Number M14A or N14A
Description
Pin Names
CPO
CP1
PO-P3
PL
00-03
.;- 2 Section Clock Input
(Active Falling Edge)
.;- 5 Section Clock Input
(Active Falling Edge)
Asynchronous Master Reset Input
(Active LOW)
Parallel Data Inputs
Asynchronous Parallel Load Input
(Active LOW)
Flip-Flop Outputs
2-251
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
input Voitage
7V
Operating Free Air Temperature Range
DM74LS
O'Cto +70'C
Storage Temperature Range
-65'Cto + 150'C
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of ttie device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute inaximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Recommended Operating Conditions
Symbol
DM74LS196
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
10H
High Level Output Current
Units
Min
Nom
Max
4.75
5
5.25
V
2
V
0.8
V
-0.4
mA
8
mA
70
'C
10L
Low Level Output Current
TA
Free Air Operating Temperature
0
ts(H)
ts (L)
Setup Time HIGH or LOW
Pnto PL
8
12
ns
th (H)
th (L)
Hold Time HIGH or LOW
PntoPL
0
6
ns
tw(H)
CPO Pulse Width HIGH
12
ns
tw(H)
CP1 Pulse Width HIGH
24
ns
tw (L)
PL Pulse Width LOW
18
ns
tw(L)
MR Pulse Width LOW
12
ns
tree
Recovery Time PL to CPn
16
ns
tree
Recovery Time MR to CPn
18
ns
Electrical Characteristics Over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 1)
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vee = Min. II = -18 mA
VOH
High Level Output Voltage
Vee = Min. 10H = Max. VIL = Max'
VOL
Low Level Output Voltage
Vee = Min. 10L = Max. VIH = Min
0.35
0.5
10L = 4 mAo Vee = Min
0.25
0.4
II
Input Current @ Max Input Voltage
Vee = Max. VI = 10V
IIH
High Level Input Current
Vee = Max. VI = 5.5V. CP1
IlL
Low Level Input Current
Vee = Max. VI = 0.4V
los
Short Circuit Output Current .
Vee = Max (Note 2)
Supply Current
Vee = Max. VIN = GND
lee
Note 1: All typtcals are at Vee = 5V, TA = 25'C.
Nota 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
2-252
2.7
V
3.4
0.1
-20
V
mA
40
jJoA
-0.4
mA
-100
mA
20
mA
Switching Characteristics
= + 5.0V, TA = + 25°C (See Section 1 for waveforms and load configurations)
Vee
Symbol
RL = 2k
CL = 15pF
Parameter
Min
fmax
Maximum Count Frequency at CPO
45
22.5
Units
Max
MHz
f max
Maximum Count Frequency at CP1
tpLH
tpHL
Propagation Delay
CPO to 00
15
15
MHz
ns
tpLH
tpHL
Propagation Delay
CP1 to 01
15
15
ns
tpLH
tpHL
Propagation Delay
CP1 to 02
34
34
ns
tpLH
. tpHL
Propagation Delay
CP1 to 03
15
21
ns
tpLH
tpHL
Propagation Delay
PntoOn
25
35
ns
tpLH
tpHL
Propagation Delay
PL to On
31
37
ns
tpHL
Propagation Delay MR to On
42
ns
Functional Description
The '196 and '197 are asynchronous presettable decade
and binary ripple counters. The '196 decade counter is partitioned into divide-by-two and divide-by-five sections while
the '197 is partitioned into divide-by-two and divide-by-eight
sections, with all sections having a separate Clock input. In
the counting modes, state changes are initiated by the
HIGH-to-LOW transition of the clock signals. State changes
of the 0 outputs, however, do not occur simultaneously because of the internal ripple delays. When using external logic to decode the 0 outputs, designers should bear in mind
that the unequal delays can lead to decoding spikes and
thus a decoded signal should not be used as a clock or
strobe. The CPO input serves the 00 flip-flop in both circuit
types while the CP1 input serves the divide-by-five or divideby-eight section. The 00 output is designed and specified to
drive the rated fan-out plus the CP1 input. With the input
frequency connected to CPO and with 00 driving CP1, the
'197 forms a straight forward modul0-16 counter, with 00
the least significant output and 03 the most significant output.
The' 196 decade counter can be connected up to operate in
two different count sequences. With the input frequency
connected to CPO and with 00 driving CP1, the circuit
counts in the BCD (8421) sequence. With the input frequency connected to CP1 and 03 driving CPO, 00 becomes the
low frequency output and has a 50% duty cycle waveform.
Note that the maximum counting rate is reduced in the latter
(bi-quinary) configuration because of the interstage gating
delay within the divide-by-five section.
The '196 and '197 have an asynchronous active LOW Master Reset input (MR) which overrides all other inputs and
forces all outputs LOW. The counters are also asynchronously presettable. A LOW on the Parallel Load input (PL)
overrides the clock inputs and loads the data from Parallel
Data (PO-P3) inputs into the flip-flops. While PL is LOW, the
counters act as transparent latches and any change in the
Pn inputs will be reflected in the outputs. In order for the
intended parallel data to be entered and stored, the recommended setup and hold times with respect to the rising
edge of PL should be observed.
2-253
U)
G)
~
r----------------------------------------------------------------------------,
Logic Diagram
PI
PO
P2
P3
~--_.------a~~~~----------~--------~H_--------__,
PL---- > 1000 pF, the output pulse width (Tw) is defined as follows:
Tw = KRxCx
where [Rx is in kn1
[Cx is in pF1
[TW is in ns1
K:::: Ln2 = 0.70
4. The multiplicative factor K Is plotted as a function of Cx
below for design considerations:
100 ~F
6. To obtain variable pulse widths by remote trimming, the
following circuit is recommended:
PlN(7IOR(lS)
PIN (6) OR (14)
I
J
Rx
y;-~
ex
RremOll
Vee
TL/F/6409-5
Note: "Rremote" should be as close to the one-shot as possible.
FIGURE 3
7. Output pulse width versus Vee and temperatures: Figure
4 depicts the relationship between pulse width variation
versus Vee. Rgure 5 depicts pulse width variation versus
temperatures.
10
...co
..
iii!
z:
Rm=SK
CuT-l000 pF
TA=2So C
5
0
~
~
r-T''''''''''''''''''''''''''''''''''''''''''''''''''''''''
IT~.125~CI
-S
-10
4
10 ~F 1-++-1-++-1-++ VCC'=S.OV
4.5
S
&.S
6
Vee (V)
l~FI-+~rr~~r+~rr~
Ei
TL/F/6409-6
FIGURE 4
0.1 ~F
.. 104 pF rt-HH--H-tl-t-t+H-+-I
10
103 pF I-+~rr~-I-r++rr~
102 pF l-+~rr~~H+-rr~
...
...z:
i'
10 pF 0
.2
.4
.6
.8
5
Rm=10K
CEXT .. 1000 pF
Vee=S.OV
CD
Z
C
1.0 1.2 1.4
TL/F/6409-3
0
~
FIGURE 1
5. For Cx < 1000 pF see Figure 2 for Tw vs Cx family
curves with Rx as a parameter:
~
-S
-10 '---'--'---I.__'---'-....L.--'
-60 -3D 0 30 60 90 120 lS0
AMBIENT TEMPERATURE (OC)
TUF/6409-7
100
FIGURE 5
8. Duty cycle is defined as TwIT x 100 in percentage, if it
goes above 50% the output pulse width will become
shorter. If the duty cycle varies between low and high
values, this causes output pulse width to vary, or jitter (a
function of the REXT only). To reduce jitter, REXT should
be as large as possible, for example, with REXT = 100k
jitter is not appreciable until the duty cycle approaches
90%.
1000
Cm IpF)
TL/F/6409-4
FIGURE 2
2-262
Operating Rules (Continued)
9. Under any operating condition Cx and Rx must be kept
as close to the one-shot device pins as possible to minimize stray capacitance, to reduce noise pick-up, and to
reduce I-R and Ldi/dt voltage developed along their
connecting paths. If the lead length from Cx to pins (6)
and (7) or pins (14) and (15) is greater than 3 cm, for
example, the output pulse width might be quite different
from values predicted from the appropriate equations. A
non-inductive and low capacitive path is necessary to
ensure complete discharge of Cx in each cycle of its
operation so that the output pulse width will be accurate.
10. Although the 'LS221's pin-out is identical to the 'LS123
it should be remembered that they are not functionally
identical. The 'LS123 is a retriggerable device such that
the output is dependent upon the input transitions when
its output "0" is at the "High" state. Furthermore, it is
recommended for the 'LS123 to externally ground the
CEXT pin for improved system performance. However,
this pin on the 'LS221 Is not an internal connection to
the device ground. Hence, if substitution of an 'LS221
onto an 'LS123 design layout where the CEXT pin is
wired to the ground, the device will not function.
11. Vee and ground wiring should conform to good high-frequency standards and practices so that switching transients on the Vee and ground return leads do not cause
interaction between one-shots. A 0.01 /-tF to 0.10 /-tF
bypass capacitor (disk ceramic or monolithic type) from
Vee to ground is necessary on each device. Furthermore, the bypass capacitor should be located as close
to the Vee-pin as space permits.
For further detailed device characteristics and output performance,
please refer to the NSC one-shot application note AN-366.
2-263
...,..
r---------------------------------------------------------------------------~
~ ~National
:. ~ Semiconductor
~
~ 54LS240/DM54LS240/DM74LS240,
54LS241/DM54LS241/DM74LS241
Octal TRI-STATE® Buffers/Line Drivers/Line Receivers
General Description
These buffers/line drivers are designed to improve both the
performance and PC board density of TRI-STATE buffers/
drivers employed as memory-address drivers, clock drivers,
and bus-oriented transmitters/ receivers. Featuring 400 mV
of hysteresis at each low current PNP data line input, they
provide improved noise rejection and high fanout outputs
and can be used to drive terminated lines down to 1330.
Features
•
•
•
•
TRI-STATE outputs drive bus lines directly
PNP inputs reduce DC loading on bus lines
Hysteresis at data inputs improves noise margins
Typical IOL (sink current)
54LS
12 mA
74LS
24 mA
• TypicallOH (source current)
54LS
-12 mA
74LS
-15 mA
• Typical propagation delay times
Inverting
10.5 ns
Noninverting 12 ns
• Typical enable/disable time 18 ns
• Typical power dissipation (enabled)
Inverting
130 mW
Noninverting 135 mW
• Alternate
Military/Aerospace
devices
(54LS240/
54LS241) are available. Contact a National Semiconductor Sales Office/ Distributor for specifications.
Connection Diagrams
Dual-In-Llne Package
Dual-In-Llne Package
Vee 2G
lY4 fAl
lAl
2Y4
lA2 2Y3 lA3
2Y2
lA4 2Yl GND
TLlF/6411-1
Order Number 54LS240DMQB, 54LS240FMQB,
54LS240LMQB, DM54LS240J,
DM74LS240WM or DM74LS240N
See NS Package Number E20A, J20A,
M20B, N20A or W20A
IG
IAI
lYl
2A4
lY2 2A3
IY3
2A2 IV4 2AI
2Y4
IA2
2Y3
2Y2
lA4 2YI GND
TL/F/641'-2
IA3
Order Number 54LS241DMQB, 54LS241FMQB,
54LS241LMQB, DM54LS241J,
DM74LS241WM or DM74LS241 N
See NS Package Number E20A, J20A,
M20B, N20A or W20A
Function Tables
LS240
LS241
Inputs
Inputs
Output
Outputs
G
A
Y
G
G
1A
2A
1Y
L
L
H
L
H
H
L
Z
L
L
H
L
H
X
X
X
X
X
X
X
L
H
Z
H
H
L
X
X
X
L = Low logic Level
H = High logic Level
X = Either Low or High Logic Level
Z = High Impedance
2-264
X
X
X
X
L
H
X
2Y
L
H
Z
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
DM54LS, 54LS
-55'Cto + 125'C
DM74LS
O'Cto +70'C
Storage Temperature Range
- 65'C to + 150'C
Recommended Operating Conditions
Symbol
DM54LS240, 241
Parameter
DM74LS240, 241
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
0.7
0.8
V
10H
High Level Output Current
-12
-15
mA
10L
Low Level Output Current
12
24
mA
TA
Free Air Operating Temperature
70
'C
2
V
2
-55
125
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
=
=
=
Min
-1.5
VI
Input Clamp Voltage
Vee
HYS
Hysteresis (VT + - VT-)
Data Inputs Only
Vee
VOH
High Level Output Voltage
Vee = Min, VIH = Min
VIL = Max,lOH = -1 mA
DM74
Vee = Min, VIH = Min
VIL = Max,lOH = -3 mA
DM54/DM74
Min,ll
VOL
Low Level Output Voltage
-18 mA
Min
Vee = Min, VIH
VIL = 0.5V, 10H
Typ
Max Units
(Note 1)
0.2
= Min
= Max
DM54/DM74
= 12mA
= Max
V
0.4
V
3.4
V
2.7
2.4
2
Vee = Min
VIL = Max
VIH = Min
10L
Vee = Max
VIL = Max
VIH = Min
Vo
= 2.7V
20
p.A
Vo
= O.4V
-20
p.A
0.1
mA
10L
10ZH
Off-State Output Current,
High Level Voltage Applied
10ZL
Off-State Output Current,
Low Level Voltage Applied
II
Input Current at Maximum
Input Voltage
Vee = Max, VI = 7V (DM74)
VI = 10V (OM 54)
IIH
High Level Input Current
Vee
IlL
Low Level Input Current
Vee
los
Short Circuit Output Current Vee
lee
Supply Current
=
=
Max, VI
Max, VI
DM74
0.4
DM54
0.4
DM74
0.5
= 2.7V
= 0.4V
= Max (Note 2)
-40
Vee = Max,
Outputs Open
2-265
20
p.A
-0.2
mA
-225
mA
Outputs High
LS240, LS241
13
23
Outputs Low
LS240
26
44
LS241
27
46
Outputs Disabled LS240
29
50
LS241
32
54
Not. ,: All typical. are at Vee = SV, TA = 2S'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
V
mA
PI
Switching Characteristics at Vee =
Symbol
tpLH
tpHL
tpZL
tPZH
tpLZ
tpHZ
tpLH
tpHL
tpZL
tpZH
5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
Parameter
Conditions
DM54LS
DM74LS
Max
Max
Propagation Delay Time
Low to High Level Output
CL=45pF
RL = 6670
LS240
18
14
LS241
18
18
Propagation Delay Time
High to Low Level Output
CL=45pF
RL = 6670
LS240
18
18
LS241
18
18
Output Enable Time to
Low Level
CL = 45pF
RL = 6670
LS240
30
30
LS241
30
30
Output Enable Time to
High Level
CL=45pF
RL = 6670
LS240
23
23
LS241
23
23
Output Disable Time
from Low Level
CL = 5pF
RL = 6670
LS240
25
25
LS241
25
25
Output Disable Time
from High Level
CL = 5pF
RL = 6670
LS240
18
18
LS241
18
18
Propagation Deiay Time
Low to High Level Output
CL = 150pF
RL = 6670
LS240
18
LS241
21
Propagation Delay Time
High to Low Level Output
CL = 150pF
RL = 6670
Output Enable Time to
Low Level
Output Enable Time to
High Level
LS240
22
LS241
22
CL = 150pF
RL = 6670
LS240
33
LS241
33
CL = 150pF
RL = 6670
LS240
26
LS241
26
Note: 54LS Output load is CL - 50 pF lor IpLH, IpHLo IpZL and IpZH.
2-266
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
~National
~ Semiconductor
DM74LS243 Quadruple Bus Transceiver
General Description
Features
This four data line transceiver is designed for asynchronous
two-way communications between data buses. It can be
used to drive terminated lines down to 1330.
• Two-way asynchronous communication between data
buses
• PNP inputs reduce DC loading on bus line
• Hysteresis at data inputs improves noise margin
Connection Diagram
Dual-In-Llne Package
Vee
GBA
Ne
1B
2B
3B
4B
TlIF/6412-1
Order Number DM74LS243WM or DM74LS243N
See NS Package Number M14B or N14A
Function Table
Data Port
Status
Control
Inputs
GAB
GBA
A
H
H
H
0
L
H
L
L
L
.
B
I
•
ISOLATED
I
0
'Possibly destructive oscillation may occur If the transceivers are enabled
In both directions at once.
I
= Input, 0 = Oulput.
H = High Logic Level, L = Low logic Lavel.
2-267
tI
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
7V
Input Voltage
AnyG
AorB
7V
5.5V
Operating Free Air Temperature Range
DM74LS
Storage Temperature Range
O·Cto +70·C
-65·C to + 150"C
Recommended Operating Conditions
Symbol
DM74LS243
Parameter
Units
Min
Nom
Max
4.75
5
5.25
V
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
0.8
V
10H
High Level Output Current
-15
rnA
10L
Low Level Output Current
24
rnA
TA
Free Air Operating Temperature
70
·c
2
V
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Conditions
Parameter
Min
VI
Input Clamp Voltage
Vee = Min, 11= -18 rnA
HYS
Hysteresis (VT + - VT -)
(Data Inputs Only)
Vee = Min
VOH
High Level Output Voltage
Vee = Min, VIH = Min
VIL = Max,IOH = -1 rnA
2.7
Vee = Min, VIH = Min
VIL = Max, IOH = -3 rnA
2.4
0.2
Vee = Min, VIH = Min
VIL = 0.5V, IOH = Max
VOL
Low Level Output Voltage
Typ
(Note 1)
Max
Units
-1.5
V
0.4
V
3.4
V
2
Vee = Min
VIL = Max
VIH = Min
10L = 12 rnA
Vee = Max
VIL = Max
VIH = Min
Vo = 2.7V
0.4
V
IOL = Max
0.5
IOZH
Off-State Output Qurrent,
High Level Voltage Applied
IOZL
Off-State Output Current,
Low Level Voltage Applied
II
Input Current at Maximum
Input Voltage
Vee = Max
IIH
High Level Input Current
Vee = Max, VI = 2.7V
20
".A
IlL
Low Level Input Current
Vee = Max, VI = O.4V
-0.2
rnA
lOS
Short Circuit Output Current
Vee = Max (Note 2)
-225
rnA
lee
Supply Current
Vee = Max
Outputs
Open
Vo = 0.4V
40
".A
-200
p.A
VI = 5.5V
L AorB
0.1
mA
VI = 7V
I
0.1
rnA
AnyG
-40
Outputs High
22
38
Outputs Low
29
50
Outputs Disabled
32
54
Note 1: All typlcals are at Vee = 5V, TA = 25'C.
Note 2: Not more than one output should be shorted at a time. and the duration should not exceed one second.
2-268
rnA
Switching Characteristics at Vee =
Symbol
Parameter
5V, TA = 25·C (See Section 1 for Test Waveforms and Output Load)
Max
Units
tpLH
Propagation Delay Time
Low to High Level Output
CL=45pF
RL = 6670
Conditions
Min
18
ns
tpHL
Propagation Delay Time
High to Low Level Output
CL = 45pF
RL = 6670
18
ns
tpZL
Output Enable Time to
Low Level
CL = 45pF
RL = 6670
30
ns
tpZH
Output Enable Time to
High Level
CL = 45pF
RL = 6670
23
ns
tpLZ
Output Disable Time
from Low Level
CL = 5pF
RL = 6670
25
ns
tpHZ
Output Disable Time
from High Level
CL = 5pF
RL = 6670
18
ns
tpLH
Propagation Delay Time
Low to High Level Output
CL = 150pF
RL = 6670
21
ns
tpHL
Propagation Delay Time
High to Low Level Output
CL = 150pF
RL = 6670
22
ns
tPZL
Output Enable Time to
Low Level
CL = 150pF
RL = 6670
33
ns
tpZH
Output Enable Time to
High Level
CL = 150 pF
RL = 6670
26
ns
fI
,
2·269
~ r---------------------------------------------------------------------------~
~
~
J?A National
~ SemiconducIDr
54LS244/DM74LS244 Octal TRI-STATE®
Buffers/Line Drivers/Line Receivers
General Description
These buffers/line drivers are designed to improve both the
performance and PC board density of TRI-STATE buffers/
drivers employed as memory-address drivers, clock drivers,
and bus-oriented transmitters/receivers. Featuring 400 mV
of hysteresis at each low current PNP data line input, they
provide improved noise rejection and high fanout outputs
and can be used to drive terminated lines down to 1330..
Features
• TRI-STATE outputs drive bus lines directly
• PNP inputs reduce DC loading on bus lines
• Hysteresis at data inputs improves noise margins
• Typical IOL (sink current)
54LS
12 mA
74LS
24 mA
• Typical IOH (source current)
54LS
-12 mA
74LS
-15 mA
• Typical propagation delay times
Inverting
10.5 ns
Noninverting 12 ns
• Typical enable/disable time 18 ns
• Typical power dissipation (enabled)
Inverting
130 mW
Noninverting 135 mW
Connection Diagram
Dual-In-Llne Package
vee 20
10
1A1
2Y4
1A2
2Y3
1A3
1Y3
2A2
1Y4 2A1
2Y2
1A4
2Y1 GND
TLlF/8442-1
Order Number 54LS244DMQB, 54LS244FMQB, 54LS244LMQB,
DM74LS244WM or DM74LS244N
See NS Package Number E20A, J20A, M20B, N20A or W20A
Function Table
Inputs
Output
~
A
Y
L
L
H
L
H
L
H
X
Z
L = Low Logic Level
H = High logic Level
X = Either Low or High Logic Level
Z = High Impedance
2-270
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
-55·C to + 125·C
54LS
O·Cto +70·C
DM74LS
Storage Temperature Range
-65·Cto + 150·C
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaran·
teed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Recommended Operating Conditions
Symbol
54LS244
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
DM74LS244
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
V
2
V
VIL
Low Level Input Voltage
0.7
0.8
V
10H
High Level Output Current
-12
-15
mA
10L
Low Level Output Current
12
24
mA
70
·C
TA
-55
Free Air Operating Temperature
125
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 1)
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vee = Min, II = -18 mA
HYS
Hysteresis (VT+ - VT-)
Data Inputs Only
Vee = Min
VOH
High Level Output Voltage
Vee = Min, VIH = Min
VIL = Max,IOH = -1 mA
DM74
Vee = Min, VIH = Min
VIL = Max, 10H = -3 mA
54LS/DM74
Vee = Min, VIH = Min
VIL = 0.5V, 10H = Max
54LS/DM74
Vee = Min
VIL = Max
VIH = Min
IOL=12mA
54LS/DM74
0.4
10L = Max
DM74
0.5
V
Vee = Max
VIL = Max
VIH = Min
Vo = 2.7V
20
/LA
-20
/LA
0.1
mA
20
/LA
VOL
Low Level Output Voltage
0.2
10ZH
Off·State Output Current,
High Level Voltage Applied
10ZL
Off·State Output Current,
Low Level Voltage Applied
II
Input Current at Maximum
Input Voltage
IIH
High Level Input Current
Vee = Max
= 7V (DM74)
= 10V (54LS)
VI = 2.7V
IlL
Low Level Input Current
Vee = Max
VI = 0.4V
los
Short Circuit Output Current
Icc
Supply Current
Vee = Max
Vee
Vo
V
3.4
V
2.7
2.4
2
= 0.4V
VI
VI
= Max (Note 2)
Vee = Max,
Outputs Open
0.4
-0.5
54LS
-50
DM74
-40
-200
!LA
-225
mA
Outputs High
13
23
Outputs Low
27
46
Outputs Disabled
32
54
Note 1: All typlcals are at Vee = 5V, TA = 25'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
2·271
mA
•
Switching Characteristics at Vee =
Symbol
Parameter
5V. TA = 25°C (see Section 1 for Test Waveforms and Output Load)
54LSMax
DM74LSMax
Units
tpLH
Propagation Delay Time
Low to High Level Output
CL=45pF
RL = 6670
Conditions
18
18
ns
tpHL
Propagation Delay Time
High to Low Level Output
CL = 45pF
RL = 6670
18
18
ns
tpZL
Output Enable Time 10
Low Level
CL = 45pF
RL = 6670
30
30
ns
tPZH
Outpul Enable Time 10
High Level
CL = 45pF
RL = 6670
23
23
ns
tpLZ
Output Disable Time
from Low Level
CL = 5pF
RL = 6670
25
25
ns
IpHZ
Output Disable Time
from High Level
CL=5pF
RL = 6670
18
18
ns
tpLH
Propagation Delay Time
Low to High Level Output
CL = 150pF
RL = 6670
21
ns
tpHL
Propagation Delay Time
High to Low Level Output
CL = 150pF
RL = 6670
22
ns
tpZL
Output Enable Time to
Low Level
CL = 150pF
RL = 6670
33
ns
IpZH
Output Enable Time 10
High Level
CL = 150pF
RL = 6670
26
ns
Note: 54LS Output Load Is CL = 50 pF for IpLH. IpHL. IpZL and IpZH.
2-272
~National
~ Semiconductor
54LS245/DM54LS245/DM74LS245
TRI-STATE® Octal Bus Transceiver
General Description
• PNP inputs reduce DC loading on bus lines
These octal bus transceivers are designed for asynchronous two-way communication between data buses. The
control function implementation minimizes external timing
requirements.
The device allows data transmission from the A bus to the B
bus or from the B bus to the A bus depending upon the logiC
level at the direction control (DIR) input. The enable input
(G) can be used to disable the device so that the buses are
effectively isolated.
II Hysteresis at bus inputs improve noise margins
• Typical propagation delay times, port-to-port 6 ns
• Typical enable/disable times 17 ns
• IOL (sink current)
54LS
12 rnA
74LS
24 rnA
• IOH (source current)
54LS
-12 rnA
74LS
-15 rnA
II Alternate Military/Aerospace device (54LS245) is available. Contact a National Semiconductor Sales Office/
Distributor for speCifications.
Features
• Bi-Directional bus transceiver in a high-density 20-pin
package
II TRI-STATE outputs drive bus lines directly
Connection Diagram
Dual-In-Llne Package
ENABLE
vee
G
DIR
B1
A2
A1
B2
A3
B3
B4
A4
AS
BS
A6
B6
B7
B8
A7
AB
GND
Order Number 54LS245DMQB, 54LS245FMQB, 54LS245LMQB,
DM54LS245J, DM54LS245W, DM74LS245WM or DM74LS245N
See NS Package Number E20A, J20A, M20B, N20A or W20A
Function Table
Enable
G
L
L
H
H
= High Level. L
Direction
Control
DIR
L
H
Operation
B data to A bus
A data to B bus
Isolation
X
= Low Level, X
= I·'" Ip~ "'rt
2-273
TLlF/6413-1
•
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
DIRorG
7V
AorB
5.5V
Operating Free Air Temperature Range
- 55·C to + 125·C
DM54LS and 54LS
DM74LS
O·Cto +70·C
Storage Temperature Range
-65·C to + 150"C
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
perametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operatiOn.
Recommended Operating Conditions
Symbol
DM54LS245
Parameter
DM74LS245
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
0.7
0.8
V
10H
High Level Output Current
-12
-15
mA
24
mA
70
·c
10L
Low Level Output Current
TA
Free Air Operating Temperature
V
2
2
V
12
-55
125
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
VI
Input Clamp Voltage
Vee = Min, II = -18 mA
HYS
HysteresiS (VT +
Vee = Min
VOH
High Level Output Voltage
VOL
- VT-)
Low Level Output Voltage
Min
0.2
Vee = Min, VIH = Min
VIL = Max,IOH = -1 mA
DM74
Vee = Min, Vil = Min
Vil = Max, 10H = -3 mA
DM54/DM74
Vee = Min, VIH = Min
Vil = 0.5V, 10H = Max
DM54/DM74
Vee = Min
Vil = Max
VIH = Min
Typ
(Note 1)
Max
Units
-1.5
V
0.4
V
3.4
V
2.7
2.4
2
10l = 12mA
DM74
IOl = Max
DM54
0.4
0.4
DM74
0.5
V
10ZH
Off-State Output Current,
High Level Voltage Applied
10Zl
Off-State Output Current,
Low Level Voltage Applied
II
Input Current at Maximum
Input Voltage
Vee = Max
IIH
High Level Input Current
Vee = Max, VI = 2.7V
20
/LA
IlL
Low Level Input Current
Vee = Max, VI = 0.4V
-0.2
mA
los
Short Circuit Output Current
Vee = Max (Note 2)
-225
mA
lee
Supply Current
Outputs High
Vee = Max
Vil = Max
VIH = Min
Vo = 2.7V
Vo = O.4V
20
/LA
-200
/LA
AorB
VI = 5.5V
0.1
DIRorG
VI= 7V
0.1
-40
48
70
Outputs Low
62
90
Outputs at Hi-Z
64
95
Vee = Max
Note 1: All typieals are at Vee = 5V. TA = 25'C.
Note 2: Not more than one output should be shorted at a time, nol to exceed one second duration
2-274
mA
mA
Switching Characteristics Vee = 5V, TA = 25°C (See Section 1 for Test Waveforms and Output Load)
DM54174
Symbol
Parameter
Conditions
LS245
Min
tpLH
Propagation Delay Time, Low-to-High-Level Output
tpHL
Propagation Delay Time, High-to-Low-Level Output
tPZL
Output Enable Time to Low Level
tpZH
Output Enable Time to High Level
tpLZ
Output Disable Time from Low Level
tpHZ
Output Disable Time from High Level
tpLH
Propagation Delay Time, Low-to-High-Level Output
tpHL
Propagation Delay Time, High-to-Low-Level Output
tPZL
Output Enable Time to Low Level
tpzH
Output Enable Time to High Level
CL
RL
CL
RL
CL
RL
= 45pF
= 6670
= 5pF
= 6670
= 150pF
= 6670
Units
Max
12
ns
12
ns
40
ns
40
ns
25
ns
25
ns
16
ns
17
ns
45
ns
45
ns
•
2-275
~
!J
~NaHonal
~ Semiconductor
54LS247/DM74LS247
BCD to 7-Segment Decoder/Driver
with Open-Collector Outputs
General Description
The 'LS247 has active LOW open-collector outputs guaranteed to sink 12 mA (Military) or 24 mA (Commercial). It has
the same electrial characteristics and pin connections as
the 'LS47. The only difference is that the 'LS247 will ight the
top bar (segment a) for numeral 6 and the bottom bar (segment d) for number 9. For detailed description and specifications please refer to the 'LS47 data sheet.
Connection Diagram
Logic Symbol
7
2
6
3
5
Dual-In-Llne Package
Al
16
A2
2
15
Vee
i
IT
3
14
Hi/RBO
4
13
a
RBi
5
12
ii
13 12 11 10 9 15 14 4
A3
6
11
AO
GND
7
10
d
Vee = Pin 16
GND = Pin 8
8
9
9
TUF/9B22-2
TUF/9B22-1
Order Number 54LS247DMQB, 54LS247FMQB,
DM74LS247M or DM74LS247N
See NS Package Number J16A, M16A, N16E or W16A
Pin Names
AO-AS
RBI
LT
Bi/RBO
-a-g-
Description
BCD Inputs
Ripple Blanking Input (Active LOW)
Lamp Test Input (Active LOW)
Blanking Input (Avtive LOW) or
Ripple Blanking Output (Active LOW)
Segment Outputs (Active LOW)
2-276
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
54LS
DM74LS
-55'Cto + 125'C
O'Cto +70'C
Storage Temperature Range
-65'C to + 150'C
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Recommended Operating Conditions
Symbol
DM74LS247
54LS247
Parameter
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
0.7
0.8
V
10H
High Level Output Current
-50
-50
,.,.a
10L
Low Level Output Current
12
24
mA
TA
Free Air Operating Temperature
70
'C
2
2
-55
125
V
V
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 1)
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vee = Min, 11= -18mA
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
VIL = Max
10FF
Output High Current
Segement Outputs
Vee = 5.5V, VM = 15V
VOL
Low Level Output
Voltage
Vee = Min, 10L = Max
VIH = Min
54LS
DM74LS
0.35
0.5
10L = 12 mA, Vee = Min
DM74LS
0.25
0.5
54LS
2.4
DM74LS
2.4
V
3.4
250
,.,.A
0.5
V
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 10V
IIH
High Level Input Current
Vee = Max, VI = 2.7V
20
,.,.A
IlL
Low Level Input Current
Vee = Max, VI = 0.4V
-0.4
mA
Vee = Max, VI = O.4V
Bi/RBO Input
-1.2
mA
lOS
Short Circuit
Output Current
Vee = Max
(Note 2)
0.1
54LS
-0.3
-2.0
DM74LS
-0.3
-2.0
Supply Current
Vee = Max
typicals are at Vee = 5V, TA = 25'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
lee
Note 1: All
2-277
13
mA
mA
mA
Switching Characteristics Vee = + 5V, TA = + 25°C (See Section 1 for Test Waveforms and Output Load)
RL = 2 kO (54LS = 6650)
Symbol
Parameter
CL = 15pF
Units
Min
Max
tpLH
Propagation Delay Time
Low to High Level Output
100
ns
tpLH
Propagation Delay Time
High to Low Level Output
100
ns
2-278
~National
~ Semiconductor
54LS248/DM74LS248 BCD to 7-Segment Decoder
(with 2 kn Pull-Up Resistors)
General Description
The 'LS248 has active HIGH outputs with internal 2 k!l pullup resistors. It has the same electrical characteristics and
pin connections as the 'LS48. The only difference is that the
'LS248 will light the top bar (segment a) for numeral 6 and
the bottom bar (segment d) for numeral 9. For detailed description and specifications please refer to the 'LS48 data
sheet.
Connection Diagram
Logic Symbol
Dual-In-Llne Package
Al- 1
\.J
16
A2- 2
15 - f
[f- 3
14 -g
4
13 -a
iiiii-s
12 '-b
BI/RBO -
II i i bb
-Vee
A3- 6
11 '-c
AO- 7
10 ~d
GND- 8
91-e
AO Al A2 A3 LT RBI
BI/
abcdefgRBO
1~ A1'1 1~
!
1'5
1~ ~
TL/F/10181-2
vce - Pin 16
GND - PinS
TL/F/10181-1
Order Number 54LS248DMOB, 54LS248FMOB,
DM74LS248M or DM74LS248N
See NS Package Number J16A, M16A, N16E or W16A
Pin Names
AO-A3
a-g
Description
BCD Inputs
Ripple Blanking Input (Active LOW)
Lamp Test Input (Active LOW)
Blanking Input (Active LOW) or
Ripple Blanking Output (Active LOW)
Segment Outputs (Active HIGH)
•
2-279
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
54LS
- 55'C to + 125'C
DM74LS
O'Cto +70'C
Storage Temperature Range
- 65'C to + 150'C
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Recommended Operating Conditions
Symbol
-
54LS248
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
10H
High Level Output Voltage
DM74LS248
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
2
10L
Low Level Output Current
TA
Free Air Operating Temperature
Units
Min
V
0.7
0.8
V
-0.1
-0.1
mA
6
mA
70
'C
2
-55
V
125
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 1)
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vee = Min, II = -18 mA
VOH
High Level Output Voltage
Vee = Min. 10H = Max.
VIL = Max
54LS
2.4
DM74
2.4
Vee = Min, 10L = Max.
VIH = Min
54LS
0.4
DM74
0.5
10L = 3.2 mAo Vee = Min
DM74
0.4
VOL
Low Level Output Voltage
V
V
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 10V
IIH
High Level Input Current
Vee = Max, VI = 2.7V
20
".A
IlL
Low Level Input Current
Vee = Max, VI = 0.4V
-0.4
mA
los
Short Circuit
Output Current
Vee = Max
(Note 2)
lee
Supply Current
Vee = Max
10FF
Output High Current
Segment Inputs. Vo = 0.85V
Not. 1: All typlcals are at Vee = SV, TA = 2S·C.
Not. 2: Not more than one output should be shorted at a time,
0.1
54LS
-0.3
-2.0
DM74
-0.3
-2.0
38
-1.3
and the duration should not exceed one second.
2-280
mA
mA
mA
".A
Switching Characteristics
Vee =
+ 5.0V, T A = + 25°C (See Section 1 for waveforms and load configurations)
Symbol
Parameter
RL
= 2k!l.,CL = 15pF
Min
Max
Units
tplH
Propagation Delay Time
Low to High Level Output
100
ns
tpHL
Propagation Delay Time
High to Low Level Output
100
ns
2·281
m
r---------------------------------------------------------------------~
~ ~National
~ Semiconductor
54LS249/DM74LS249
BCD to 7-Segment Decoder
(with Open-Collector Outputs)
General Description
The 'LS249 has active HIGH open-collector outputs and incorporates the Lamp Test and BI/RBO inputs. Additionally,
the 'LS249 will light the top bar (segment a) for numeral 6
and the bottom bar (segment d) for numeral 9.
Connection Diagram
Logic Symbol
Dual-In-Llne Package
Al- 1
'--/
16
iiii 11
-Vee
A2- 2
15 - f
iJ-
3
Bi/RBO-
4
14 """0
13 r-a
Riii- 5
12 r-b
A3- 6
11 r-c
AO- 7
10l-d
GND- 8
91-,
AD AI A2 A3
LT RBI
Bl/
abcd'foRBO
TL/F/l0213-2
TlIF/l0213-1
vee = Pin 16
GND
Order Number 54LS249DMBO, 54LS249FMBO or
DM74LS249N
See NS Package Number J16A, N16E or W16A
Pin Names
Ao-Aa
Eli
LT
BI/RBO
a-g
Description
BCD Inputs
Blanking Input (Active LOW)
Lamp Test Input (Active LOW)
Blanking Input (Active LOW) or
Ripple Blanking Output (Active LOW)
Segment Outputs (Active HIGH)
2-282
= Pin 8
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and speclficatlons_
Supply Voltage
7V
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "£Iectrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Input Voltage
7V
Operating Free Air Temperature Range
54LS
-55'C to + 125'C
DM74LS
O'Cto +70'C
Storage Temperature Range
-65'Cto + 150'C
Recommended Operating Conditions
Symbol
54LS249
Parameter
Vee
Supply Voltage
V,H
High Level Input Voltage
V,L
Low Level Input Voltage
DM74LS249
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
0.7
0.8
V
2
2
V
10H
High Level Output Current
-0.25
-0.25
mA
10L
Low Level Output Current
4
8
mA
TA
Free Air Operating Temperature
70
·c
-55
125
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
=
=
V,
Input Clamp Voltage
Vee
VOH
High Level Output Voltage
Vee = Min, 10H
V,L = Max
=
Vee = Min, 10L
V,H = Min
=
VOL
Low Level Output Voltage
Min,l,
Max,
Max,
= 4 mA, Vee = Min
Vee = Max, V, = 10V
Input Current @ Max
Input Voltage
I'H
High Level Input Current
Vee
I,L
Low Level Input Current
Vee
los
Icc
Short Circuit
Output Current
Vee
Supply Current
Vee
=
=
=
=
Max, V,
Max, V,
=
=
54LS
2.4
DM74
2.7
=
Units
-1.5
V
V
0.4
DM74
0.35
0.5
DM74
0.25
0.4
mA
20
p.A
-0.03
-0.4
BIIRBO
-0.09
-1.2
54LS
-0.3
-2.0
DM74
-20
-100
4.5V
Nole 2: Not more than one output should be shorted at a time. and the duration should not exceed one second.
V
0.1
Inputs
Nole 1: All typicals are at Vee = SV. TA = 2S'C.
2-283
Max
3.4
54LS
2.7V
0.4V
Max (Note 2)
Max, V,N
Typ
(Note 1)
-18 mA
10L
I,
Min
15
mA
mA
mA
•
Switching Characteristics
at Vee =
+ 5.0V, TA = + 25°C (See Section 1 for Test Waveforms and Output Load)
RL =.2kll
Symbol
CL = 15pF
Parameter
Min
Units
Max
tpLH
tpHL
An to a-g (54LS RL = 2 kn)
Propagation Delay Time
100
100
ns
tpLH
tpHL
Bi to a-g (54LS RL =
Propagation Delay Time
6 kill
100
100
ns
Numerical Designations-Resultant Displays
I-I
I_I
0
,, ,-, -,, ,-,, ,-, ,-, , -,, , , , , , '-' , ,,
I-I I-I
1
3
2
4
5
6
7
B
10
9
11
14
13
12
15
TLlF/l0213-3
Truth Table
Decimal
or
Function
Outputs
Inputs
Note
LT
A3
A2
Ai
Ao
BIIRBO
a
b
c
d
e
f
g
0
1
2
3
H
H
H
H
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
L
H
H
H
L
H
L
H
L
L
L
L
L
H
H
4
5
6
H
H
H
H
H
L
L
L
L
H
H
H
H
H
L
L
L
H
H
L
L
H
L
H
L
H
H
H
H
H
L
H
L
H
H
H
L
L
H
H
H
H
H
H
H
L
H
H
L
H
L
L
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
L
L
H
H
L
H
H
L
L
H
L
H
L
H
H
H
H
H
H
H
L
L
L
H
H
L
L
H
L
H
L
H
L
L
L
H
H
L
H
L
H
L
L
L
H
L
L
H
H
H
H
H
H
H
7
8
9
10
11
12
13
1
1
H
L
L
L
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
L
L
L
L
L
L
L
Bi
L
L
X
X
X
X
X
L
L
L
L
L
L
2
LT
L
X
X
X
X
H
H
H
H
H
H
H
H
3
Note 1: IIDRIil:) Is wired-AND logic serving as blanking Input (81) and/or ripple-blanking oulput (FiiID). The blanking out (1i1) must be open or held at a HIGH level
when output functions 0 through 15 are desired. X = input may be HIGH or LOW.
Note 2: When a LOW level Is applied to the blanking Input (forced condition) all segment oulputs go to a LOW level, regardless of the state of any other Input
condHlon.
Note 3: When the blanking Input/ripple·blanklng oulput (1!17l'i!iO) is open or held at a HIGH level, and a LOW level is applied to lamp test input, all segment oulpuls
go to a HIGH level.
14
15
2-284
Logic Diagram
BLANKING INPUT
LAIoIP-lEST
INPUT
BLANKING INPUT OR
RIPPLE-BLANKING
OUTPUT
,r_______________
U
~
INPUT
_________________
~A
M
~\
M
OUTPUT
TLlF/l0213-4
•
2-285
.-
,--------------------------------------------------------------------------------,
~ ~National
~ Semiconductor
DM54LS251/DM74LS251
TRI-STATE® Data Selectors/Multiplexers
General Description
Features
These data selectors/multiplexers contain full on-chip binary decoding to select one-of-eight data sources. and feature
a strobe-controlled TRI-STATE output. The strobe must be
at a low logic level to enable these devices. The TRI-STATE
outputs permit direct connection to a common bus. When
the strobe input is high. both outputs are in a high-impedance state in which both the upper and lower transistors of
each totem-pole output are off. and the output neither drives
nor loads the bus significantly. When the strobe is low. the
outputs are activated and operate as standard TTL totempole outputs.
•
•
•
•
•
•
To minimize the possibility that two outputs will attempt to
take a common bus to opposite logic levels. the output control circuitry is designed so that the average output disable
time is shorter than the average output enable time.
Connection Diagram
TRI-STATE version of LS151
Interface directly with system bus
Perform parallel-to-serial conversion
Permit multiplexing from N-lines to one line
Complementary outputs provide true and inverted data
Maximum number of common outputs
54LS 49
74LS 129
• Typical propagation delay time (0 to Yl
54LS 17 ns
74LS 17 ns
• Typical power dissipation
54LS 35 mW
74LS 35 mW
Function Table
Dual-In-Line Package
.
i
vCC
16
'04
15
OS
14
06
OATA SELECT
07'
13
12
A
11
Select
C'
B
10
9
DATA INPUTS
.:../--...---.;W~6
.....
STR:BE
Strobe
Gl:
OUTPUTS
TLlF/6415-1
Order Number DM54LS251J, DM54LS251W,
DM74LS251M or DM74LS251N
See NS Package Number J16A, M16A, N16E or W16A
2-286
y
c
B
A
S
X
L
L
L
L
H
H
H
H
X
L
L
H
H
L
L
H
H
X
L
H
L
H
z
L
L
L
L
L
L
L
L
00
01
H
L
H
L
H
= High Logic Level, L = Low Logic Level,
X = Don't Care, Z = High Impedance (011)
DO, D1 •.• D7 = The level of the respective D Input
H
,,;,0;;3;..1__.;;0=.22_....;0:;.1;..3_...:DD...:,4,
Outputs
Inputs
.
OATA INPUTS
02
03
04
05
06
07
W
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
DM54LS
-55'Cto + 125'C
DM74LS
O'Cto +70'C
Storage Temperature Range
-65'Cto +150'C
Recommended Operating Conditions
Symbol
DM54LS251
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
DM74LS251
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
2
V
V
VIL
Low Level Input Voltage
0.7
0.8
V
10H
High Level Output Current
-1
-2.6
mA
24
mA
70
'C
10L
Low Level Output Current
TA
Free Air Operating Temperature
Electrical Characteristics
Symbol
12
-55
125
0
over recommended operating free air temperature range (unless otherwise noted)
Parameter
Min
Typ
(Note 1)
DM54
2.4
3.4
DM74
2.4
3.1
Conditions
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vee = Min, 11= -18 mA
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
VIL = Max, VIH = Min
Low Level Output
Voltage
Vee = Min, 10L = Max
VIL = Max, VIH = Min
DM54
0.25
0.4
DM74
0.35
0.5
10L = 12 mA, Vee = Min
DM74
0.25
0.4
VOL
V
V
II
Input Current @ Max
Input Voltage
IIH
High Level Input Current
Vee = Max, VI = 2.7V
20
p.A
IlL
Low Level Input Current
Vee = Max, VI = 0.4V
-0.4
mA
IOZH
Off-State Output Current
with High Level Output
Voltage Applied
Vee = Max, Vo = 2.7V
VIH = Min, VIL = Max
20
p.A
Off-State Output Current
with Low Level Output
Voltage Applied
Vee = Max, Vo = 0.4V
VIH = Min, VIL = Max
-20
p.A
Short Circuit
Output Current
Vee = Max
(Note 2)
leel
Supply Current
Vee = Max (Note 3)
6.1
10
mA
lee2
Supply Current
Vee = Max (Note 4)
7.1
12
mA
IOZL
los
Vee = Max, VI = 7V
0.1
DM54
-20
-100
DM74
-20
-100
Note 1: All typicals are at Vcc = SV, TA = 2S'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: ICCt is measured with the oulputs open, STROBE grounded, and all other Inputs at 4.SV.
Note 4: ICC2 is measured with the outputs open and all inputs at 4.SV.
2-287
mA
mA
•
Switching Characteristics
Symbol
at Vee
Parameter
= 5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
RL = 6670
From (Input)
Units
CL = 45pF
CL = 150pF
to (Output)
Min
Propagation Delay Time
Low to High Level Output
Propagation Delay Time
High to Low Level Output
Propagation Delay Time
Low to High Level Output
Propagation Delay Time
High to Low Level Output
Propagation Delay Time
Low to High Level Output
Propagation Delay Time
High to Low Level Output
Propagation Delay Time
Low to High Level Output
Propagation Delay Time
High to Low Level Output
Output Enable Time to
High Level Output
Output Enable Time to
Low Level Output
Output Disable Time from
High Level Output (Note 1)
Output Disable Time from
Low Level Output (Note 1)
Output Enable Time to
High Level Output
Output Enable Time to
Low Level Output
Output Disable Time from
High Level Output (Note 1)
Output Disable Time from
Low Level Output (Note 1)
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tPZH
tPZL
tpHZ
IpLZ
tPZH
tpZL
tpHZ
tpLZ
Note 1: CL
~
A,B,C
(4 Levels) to Y
A,B,C
(4 Levels) to Y
A,B,C
(3 Levels) to W
A,B,C
(3 Levels) to W
D
toY
D
toY
D
toW
D
toW
Strobe
toY
Strobe
toY
Strobe
toY
Strobe
toY
Strobe
toW
Strobe
toW
Strobe
toW
Strobe
toW
Max
Min
Max
45
53
ns
45
53
ns
33
38
ns
33
42
ns
28
35
ns
28
38
ns
15
25
ns
15
25
ns
45
60
ns
40
51
ns
45
ns
25
ns
27
40
ns
40
47
ns
55
ns
25
ns
5 pF
Logic Diagram
(:=~~~
(7)Jo,.
DO (4) v
r---=;~
01 (3)
~r=§I,.J-
02 (2)
F~
~~ ~
03 (1)
DATA
INPUTS
(5) OUTPUT Y
(6)OUTPUTW
D4 (15)
tT
05 (14)
06 (13)
§I,.J-
07 (12)
-'I' ""~
SELECT
(BINARY)
B
c
v
(10)"
...
J>-
(9) "
-"
v
s....>-
A
r:;:::-A
...
.
B
B
C
c
TUF/6415-2
2·288
~National
~ Semiconductor
54LS253/DM54LS253/DM74LS253
TRI-STATE® Data Selectors/Multiplexers
General Description
Features
Each of these Schottky-clamped data selectors/multiplexers contains inverters and drivers to supply fully complementary, on-Chip, binary decoding data selection to the
AND-OR gates. Separate output control inputs are provided
for each of the two four-line sections.
The TRI-STATE outputs can interface directly with data
lines of bus-organized systems. With all but one of the common outputs disabled (at a high impedance state), the low
impedance of the single enabled output will drive the bus
line to a high or low logic level.
•
•
•
•
•
•
•
Connection Diagram
Function Table
TRI-STATE version of LS153 with same pinout
Schottky-diode-clamped transistors
Permit multiplexing from N-lines to one line
Performs parallel-to-serial conversion
Strobel output control
High fanout totem-pole outputs
Typical propagation delay
Data to output 12 ns
Select to output 21 ns
• Typical power dissipation 35 mW
• Alternate Military/Aerospace device (54LS253) is available. Contact a National Semiconductor Sales Office/
Distributor for specifications.
Dual-In-Line Package
OUTPUT
CONTROL
VC'i
p6
G2
15
Select
Inputs
,--_ _
D_AT_A...I_NP_UT_S_ _, OUTPUT
y
SELECT' 2 3
t14
113
2p
p2
2(P
p1
~2
y
2 O
19
po
G1
12
J: J:
1C~ 1J~
SELECT '":..:..:.-..;..;......-----~,
DATA INPUTS
OuJ:UT
Y1
Output
Control
Output
B
A
CO
Cl
C2
C3
G
y
X
L
L
L
L
H
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
L
H
Z
L
H
X
X
X
X
H
L
L
L
L
L
L
L
L
L
L
L
H
L
H
H
H
1
OUTPUT
CONTROL
Data Inputs
H
H
L
H
X
X
X
X
H
X
L
L
H
X
X
X
X
H
L
H
L
H
Address Inputs A and B are common to both sections.
H = High Level. L = Low Level, X = Don't Care. Z = High Impedance (off).
Gl:
TL/F/6416-1
Order Number 54LS253DMQB, 54LS253FMQB,
54LS253LMQB, DM54LS253J, DM54LS253W,
DM74LS253M or DM74LS253N
See NS Package Number E20A, J16A,
M16A, N16E or W16A
•
2-289
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaran·
teed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
OM54LS and 54LS
- 55'C to + 125'C
OM74LS
O'Cto +70'C
Storage Temperature Range
-65'Cto + 150'C
Recommended Operating Conditions
Symbol
DM54LS253
Parameter
DM74LS253
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
0.7
0.8
V
10H
High Level Output Current
-1
-2.6
mA
10L
Low Level Output Current
12
24
mA
70
'C
TA
2
2
-55
Free Air Operating Temperature
125
V
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
VI
Input Clamp Voltage
VOH
High Level Output
Voltage
= Min,ll = -18 mA
Vee = Min, 10H = Max
VIL = Max, VIH = Min
Low Level Output
Voltage
Vee = Min,lOL = Max
VIL = Max, VIH = Min
II
Input Current @ Max
Input Voltage
Vee
IIH
High Level Input Current
= Max, VI = 2.7V
Vee = Max, VI = 0.4V
Vee = Max, Vo = 2.7V
VIH = Min, VIL = Max
VOL
Low Level Input Current
10ZH
Off·State Output Current
with High Level Output
Voltage Applied
10Zl
los
ICCl
Typ
(Note 1)
Vee
10L
IlL
Min
= 12 mA, Vee = Min
= Max, VI = 7V
OM54
2.4
3.4
OM74
2.4
3.1
Vee = Max, Vo = 0.4
VIH = Min, VIL = Max
Short Circuit
Output Current
Vee = Max
(Note 2)
Supply Current
Vee
-1.5
V
V
0.4
OM74
0.5
OM74
0.4
mA
20
p.A
-0.4
mA
20
p.A
-20
p.A
OM 54
-20
-100
-20
-100
= Max (Note 3)
V
0.1
OM74
Supply Current
Vee = Max (Note 4)
lee2
Note 1: All typicals are at Vcc = 5V, TA = 25"C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: ICC1 is measured with all outputs open, and all the inputs grounded.
Note 4: icc2 is measured with the outputs open, OUTPUT CONTROL at 4.5V and all other inputs grounded.
2·290
Units
OM54
Vee
Off·State Output Current
with Low Level Output
Voltage Applied
Max
mA
7
12
mA
8.5
14
mA
Switching Characteristics at Vee =
5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
~
Co:!
Symbol
RL = 6670
From (Input)
To (Output)
Parameter
CL
Min
= 45pF
CL
Max
= 150pF
Min
Units
Max
Propagation Delay Time
Low to High Level Output
Data
toY
25
35
ns
Propagation Delay Time
High to Low Level Output
Data
toY
20
30
ns
Propagation Delay Time
Low to High Level Output
Select
toY
45
54
ns
Propagation Delay Time
High to Low Level Output
Select
toY
32
44
ns
tPZH
Output Enable Time
to High Level Output
Output
Control to Y
18
32
ns
tPZL
Output Enable Time
to Low Level Output
Output
Control to Y
23
35
ns
Output Disable Time
from High Level Output (Note 1)
Output
ControltoY
41
ns
Output Disable Time
from Low Level Output (Note 1)
Output
Control toY
27
ns
tpLZ
Note 1: CL
= 5 pF.
Logic Diagram
CONT~~~~~
_(1_)- - q
>----....;--~~Ht-""';
b
r;-r r.
DATA 1[ : : :
(7)
OUTPUT Y1
1C2-------t-tH-HI+1C3(3)
....
H
a(2)
(14)
A
(111'0~)_ _~====~~~r-,
2CO-
~
2C1~--------~H-H-r~
DATA 2
1;..1-2)------------~FI--=~~:;:tl
(11)
2C2
(13)
(9)OUTPUT Y2
-_.H-a-_
2C3::----------~~~~~
OUTPUTI;..15...;.)_-ct-"'>_ _ _ _
CONTROL G2
-v
L...._ _ _ _...
TL/F/6416-2
2-291
•
U)
r--------------------------------------------------------------------------------,
~ ~National
~ Semiconductor
54LS256/DM74LS256
Dual 4·Bit Addressable Latch
General Description
The 'LS256 is a dual 4-bit addressable latch with common
control inputs; these include two Address inputs (AO, A 1),
an active LOW enable input (E) and an active LOW Clear
input (CL). Each latch has a Data input (D) and four outputs
(00-03).
could impose a transient wrong address. Therefore, this
should be done only while in the memory mode (E = CL =
HIGH).
When the Enable (E) is HIGH and the Clear input (CL) is
LOW, all outputs (00-03) are LOW. Dual 4-channel demultiplexing occurs when the CL and E are both LOW. When
CL is HIGH and E is LOW, the selected output (00-03),
determined by the Address inputs, follows D. When the E
goes HIGH, the contents of the latch are stored. When operating in the addressable latch mode (E = LOW, CL =
HIGH), changing more than one bit of the Address (AO, A 1)
•
•
•
•
•
Connection Diagram
3
2
1 15
14
13
E
~
16 -Vee
-Ci:
Al- 2
15
Da -
14 -E:
3
Serial-to-parallel capability
Output from each storage bit available
Random (addressable) data entry
Easily expandable
Active low common clear
Logic Symbol
Dual-in-Line Package
AO- 1
Features
OOa - 4
01 a - 5
13 -Db
12 -03 b
02a - 6
11-02b
03a - 7
10 -Olb
GND- 8
9 '-OOb
~
E
AD
AD
AI
AI
CL....
... CL
OOa 01a 02a 03a
TL/F/9823-1
1! 1~
Pin Names
E
CL
OOa-0 3a
00b-0 3b
!
1~ }1
A
TL/F/9823-2
Order Number 54LS256DMQB,
54LS256FMQB or DM74LS256N
See NS Package Number J16A,
N16EorW16A
AO,A1
Ds,Db
OOb 01b 02b 03b
vee = Pin 16
GND
= PinS
Description
Common Address Inputs
Data Inputs
Common Enable Input (Active LOW)
Conditional Clear Input (Active LOW)
Side A Latch Outputs
Side B Latch Outputs
2-292
Truth Table
Inputs
outputs
Mode
QO
Q1
Q2
Q3
X
L
L
L
L
Clear
L
L
H
H
D
L
L
L
L
D
L
L
L
L
D
L
L
L
L
D
Demultiplex
X
X
01-1
01-1
01-1
01-1
Memory
L
H
L
H
L
L
H
H
D
01-1
01-1
01-1
01-1
D
01-1
01-1
Addressable
Latch
01-1
01-1
D
01-1
01-1
01-1
01-1
D
CL
E
AO
A1
L
H
X
L
L
L
L
L
L
L
L
L
H
L
H
H
H
H
H
H
H
L
L
L
L
1-1 = Billime before address change or rising edge of E
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Mode Selection
E
CL
Mode
L
H
L
H
H
H
L
L
Addressable Latch
Memory
Active HIGH 4·Channel Demultiplexers
Clear
Logic Diagram
QDa
QI
Q2
Q3
QDb
Qlb
Q2b
Q3b
TUF/9B23-3
2·293
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Input Voltage
7V
Operating Free Air Temperature Range
- 55·C to + 125·C
54LS
OM74LS
O·Cto +70·C
Storage Temperature Range
- 65·C to + 150"C
Recommended Operating Conditions
Symbol
54LS256
Parameter
DM74LS256
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
0.7
0.8
V
Vee
Supply Voltage
VIH
High Level Input Voltage
Vil
Low Level Input Voltage
10H
High Level Output Current
-0.4
-0.4
rnA
10l
Low Level Output Current
4
8
rnA
70
·C
2
TA
Free Air Operating Temperature
ts(H)
Setup Time HIGH, On to E
2
-55
125
20
V
0
20
ns
ns
IJ,(H)
Hold Time HIGH, On to E
0
0
ts(L)
Setup Time LOW, On to E
15
15
ns
th (L)
Hold Time LOW, On to E
0
0
ns
Is (H)
Is (L)
Setup Time HIGH or LOW,
An toE
0
0
ns
twILl
E Pulse Width LOW
17
17
ns
Electrical Characteristics
Over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 1)
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vee = Min, 11= -18 rnA
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
Vil = Max
54LS
2.5
OM74
2.7
Low Level Output
Voltage
Vee = Min, 10l = Max
VIH = Min
OM74
0.35
0.5
10l = 4 rnA, Vee = Min
OM74
0.25
0.4
Input Current @ Max
Input Voltage
Vee = Max, VI = 10V
Inputs
0.1
E
0.2
High Level Input Current
Vee = Max, VI = 2.7V
Inputs
20
E
40
VOL
II
IIH
III
los
lee
Low Level Input Current
Vee = Max, VI = 0.4V
Short Circuit
Output Current
Vee = Max
(Note 2)
Supply Current
Vee = Max
V
3.4
54LS
0.4
Inputs
-0.4
E
-0.8
54LS
-20
-100
OM74
-20
-100
25
Note 1: All typlcals are at Vee = SV, TA = 2S'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
2-294
V
rnA
poA
rnA
rnA
rnA
Switching Characteristics
= + 5.0V, TA = + 25'C (See Section 1 for waveforms and load configurations)
Vee
Symbol
RL = 2kO
CL = 15pF
Parameter
Units
Max
tpLH
tpHL
Propagation Delay
EtoOn
27
24
ns
tpLH
tpHL
Propagation Delay
30
20
ns
30
29
ns
18
ns
tpLH
tpHL
tpLH
Dn to On
Propagation Delay
AntoOn
Propagation Delay
CLtoO n
fII
2-295
'?:A National
~ Semiconductor
54LS257A/DM54LS257B/DM7 4LS257B,
54LS258A/DM54LS258B/DM74LS258B
TRI-STATE® Quad 2-Data Selectors/Multiplexers
General Description
Features
These Schottky-clamped high-performance multiplexers
feature TAl-STATE outputs that can interface directly with
data lines of bus-organized systems. With all but one of the
common outputs disabled (at a high impedance state), the
low impedance of the single enabled output will drive the
bus line to a high or low logic level. To minimize the possibility that two outputs will attempt to take a common bus to
OPPOSite logic levels, the output enable circuitry is designed
such that the output disable times are shorter than the output enable times.
This TAl-STATE output feature means that n-bit (paralleled)
data selectors with up to 258 sources can be implemented
for data buses. It also permits the use of standard TTL registers for data retention throughout the system.
• TAl-STATE versions LS157 and LS158 with same pinouts
• Schottky-clamped for Significant improvement in A-C
performance
• Provides bus interface from multiple sources in highperformance systems
• Average propagation delay from data input 12 ns
• Typical power dissipation
LS257B 50 mW
LS258B 35 mW
• Altemate military/aerospace devices (54LS257A1
54LS258A) are available. Contact a National Semiconductor Sales Office/Distributor for specifications.
Connection Diagrams
Dual·tn-Llne Package
OUTPUT ~ OUTPUT
VCC CONTROL A4
114
Y4
i
16
15
14
13
3
4
12
Dual·ln-Llne Package
~
OUTPUT ~ OUTPUT
Vee CONTROL A4
114
Y4
OUTPUT
83
Y3
A3
11
10
8
7
-1~8
9
15
14
13
12
INPUTS
A3"'B3
11
OUTPUT
Y3
10
9
-
1
.18
SEl.ECT
SELECT AI
81
Yl
A2
82
Y2
GIlD
----....-... OUTPUT -----.,........ OUTPUT
INPUTS
INPUTS
2
AI
~
4
YI
OUTPUT
5
A2
8
82
~
7
Y2
_18
GNO
OUTPUT
TL/F/6417-2
TL/F/6417-1
Order Number 54LS258ADMQB, 54LS258AFMQB,
54LS258ALMQB, DM54LS258BJ, DM54LS258BW,
DM74LS258BM or DM74LS258BN
See NS Package Number E20A, J16A,
M16A, N16E or W16A
Order Number 54LS257ADMQB, 54LS257AFMQB,
54LS257ALMQB, DM54LS257BJ, DM54LS257BW,
DM74LS257BM or DM74LS257BN
See NS Package Number E20A, J16A,
M16A, N16E or W16A
Function Table
Inputs
Output V
Output
Control
Select
A
H
X
X
L
L
L
L
L
L
L
H
H
3
81
B
X
X
H X
X L
X H
H = High Level, L = Low Level, X
Z = High Impedance (off)
2-296
LS257
LS258
Z
L
H
L
H
Z
H
= Don'l Care,
L
H
L
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Input Voltage
7V
Operating Free Air Temperature Range
DM54lS and 54lS
- 55'C to + 125'C
DM74lS
O'Cto +70'C
Storage Temperature Range
-65'Cto + 150'C
Recommended Operating Conditions
Symbol
DM54LS257B
Parameter
DM74LS257B
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
low level Input Voltage
0.7
0.8
V
IOH
High Level Output Current
-1
-2.6
mA
IOL
low level Output Current
12
24
mA
TA
Free Air Operating Temperature
70
'C
2
2
-55
125
V
0
'LS257B Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 1)
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vee = Min, 11= -18 mA
VOH
High level Output
Voltage
Vcc = Min, IOH = Max
VIL = Max, VIH = Min
DM54
2.4
3.4
DM74
2.4
3.1
low level Output
Voltage
Vee = Min, IOL = Max
VIL = Max, VIH = Min
DM54
0.25
0.4
DM74
0.35
0.5
IOL = 12 mA, Vcc = Min
DM74
0.25
0.4
Input Current @ Max
Input Voltage
Vee = Max,
VI = 7V
Select
0.2
Other
0.1
High level Input
Current
Vee = Max,
VI = 2.7V
Select
40
Other
20
low level Input
Current
Vee = Max,
VI = O.4V
Select
-0.8
Other
-0.4
Off-State Output Current
with High level Output
Voltage Applied
Vee = Max, Vo = 2.7V
VIH = Min, VIL = Max
20
)LA
Off-State Output Current
with low level Output
Voltage Applied
Vee = Max, Vo = 0.4V
VIH = Min, VIL = Max
-20
)LA
Short Circuit
Output Current
Vcc = Max
(Note 2)
ICCH
Supply Current with
Outputs High
Vee = Max (Note 3)
ICCL
Supply Current with
Outputs low
Vee
VOL
II
IIH
IlL
IOZH
10ZL
los
= Max (Note 3)
DM54
-20
-100
DM74
-20
-100
2-297
V
mA
)LA
mA
rnA
5.9
10
mA
9.2
16
mA
19
rnA
Supply Current with
Vee = Max (Note 3)
12
Outputs Disabled
Note 1: All typlcals are at Vee = 5V, TA = 25"C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: Icc Is measured with all outputs open and all possible inputs grounded, while achieving the stated output conditions.
IccZ
V
fI
'LS257B Switching Characteristics
at Vee = 5V and TA = 25·C (See Section 1 for Test Waveforms and Output Load)
Symbol
RL = 6670
From (Input)
To (Output)
Parameter
CL = 45pF
Min
CL = 150pF
Min
Max
Units
Max
tpLH
Propagation Delay Time
Low to High Level Output
Data to
Output
18
27
ns
tpHL
Propagation Delay Time
High to Low Level Output
Data to
Output
18
27
ns
tpLH
Propagation Delay Time
Low to High Level Output
Select to
Output
28
35
ns
tpHL
Propagation Delay Time
High to Low Level Output
Selectto
Output
35
42
ns
tpZH
Output Enable TIme
to High Level Output
Output
Control to Y
15
27
ns
tPZL
Output Enable Time
to Low Level Output
Output
Contralto Y
28
38
ns
tpHZ
Output Disable Time from
High Level Output (Note 1)
Output
ControltoY
26
ns
tpLZ
Output Disable Time from
Low Level Output (Note 1)
Output
ControltoY
25
ns
Note 1: CL
= 5 pF.
Recommended Operating Conditions
Symbol
DM54LS258B
Parameter
DM74LS258B
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
0.7
0.8
V
IOH
High Level Output Current
-1
-2.6
mA
24
mA
70
·C
2
IOL
Low Level Output Current
TA
Free Air Operating Temperature
2
V
12
-55
125
0
'LS258B Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Min
Typ
(Note 1)
DM54
2.4
3.4
DM74
2.4
3.1
Conditions
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vee = Min,ll = -18 mA
VOH
High Level Output
Voltage
Vee = Min, IOH = Max
VIL = Max, VIH = Min
Low Level Output
Voltage
Vee = Min, IOL = Max
VIL = Max, VIH = Min
DM54
0.25
0.4
DM74
0.35
0.5
IOL = 12 mA, Vee = Min
DM74
0.25
0.4
Input Current @ Max
Input Voltage
Vee = Max,
VI =7V
Select
0.2
Other
0.1
High Level Input
Current
Vee = Max,
VI = 2.7V
Select
40
Other
20
VOL
II
IIH
2-298
V
V
mA
p.A
'LS258B Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted) (Continued)
Symbol
Parameter
Conditions
Min
I
Typ
(Note 1)
Max
Units
Low Level Input
Current
Vcc = Max,
VI = 0.4V
Off·State Output Current
with High Level Output
Voltage Applied
Vcc = Max, Vo = 2.7V
VIH = Min, VIL = Max
20
/LA
Off·State Output Current
with Low Level Output
Voltage Applied
Vcc = Max, Vo = O.4V
VIH = Min, VIL = Max
-20
/LA
Short Circuit
Output Current
Vcc = Max
(Note 2)
ICCH
Supply Current with
Outputs High
Vcc
= Max (Note 3)
ICCL
Supply Current with
Outputs Low
Vcc
= Max (Note 3)
Iccz
Supply Current with
Outputs Disabled
Vcc
=
IlL
10ZH
10ZL
los
I
I
I
Select
-0.8
Other
-0.4
DM54
-20
-100
DM74
-20
-100
mA
mA
4.1
7
mA
9
14
mA
12
19
mA
Max (Note 3)
Note 1: All typicals are at Vee = SV, TA = 2S'C.
Nota 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: Icc Is measurad with all outputs open and all possible Inputs grounded, while achieving the stated output conditions.
'LS258B Switching Characteristics
at Vcc
=
5V and T A
Symbol
=
25°C (See Section 1 for Test Waveforms and Output Load)
Parameter
From (Input)
To (Output)
RL
CL
Min
=
45pF
Max
=
6670
CL
Min
=
150pF
Units
Max
tpLH
Propagation Delay Time
Low to High Level Output
Data to
Output
18
27
ns
tpHL
Propagation Delay Time
High to Low Level Output
Data to
Output
18
27
ns
tpLH
Propagation Delay Time
Low to High Level Output
Select to
Output
28
35
ns
tpHL
Propagation Delay Time
High to Low Level Output
Select to
Output
35
42
ns
tPZH
Output Enable Time
to High Level Output
Output
ControltoY
15
27
ns
tpZL
Output Enable Time
to Low Level Output
Output
Control toY
28
38
ns
tpHZ
Output Disable Time from
High Level Output (Note 4)
Output
Control toY
26
ns
tpLZ
Output Disable Time from
Low Level Output (Note 4)
Output
ControltoY
25
ns
Note 4: CL
= 5 pF.
2·299
•
ID
CD
In
C'\I
Logic Diagrams
!I
•
LS257B
ID
.....
In
C'\I
!I
OUTPUT(15)
CONTROL(2)
A1
(3)
81
(5)
A2
(6)
82
(11)
A3
(10)
83
(14)
A4
B4
(13)
TLlF/6417-3
LS258B
OUTPUT (15)
CONTROL (2)
Al~--------
______
~--~
81 (3)
. A2~(5~1______~____~~__~
82(6)
(10)
83i~~----+-------~~~
(14)
A4~------~----~~r-~
(13)
84·~------~----~~--~
Y4
TL/F/6417-4
2-300
~National
~ Semiconductor
54LS259/DM74LS259 a-Bit Addressable Latches
General Description
Features
These 8-bit addressable latches are designed for general
purpose storage applications in digital systems. Specific
uses include working registers, serial-holding registers, and
active-high decoders or demultiplexers. They are multifunctional devices capable of storing single-line data in eight
addressable latches, and being a 1-of-8 decoder or demultiplexer with active-high outputs.
• 8-Bit parallel-out storage register performs serial-to-parallel conversion with storage
• Asynchronous parallel clear
• Active high decoder
• Enable/disable input simplifies expansion
• Direct replacement for Fairchild 9334
• Expandable for N-bit applications
• Four distinct functional modes
• Typical propagation delay times:
Enable-to-output 18 ns
Data-to-output 16 ns
Address-to-output 21 ns
Clear-to-output 17 ns
Four distinct modes of operation are selectable by controlling the clear and enable inputs as enumerated in the function table. In the addressable-latch mode, data at the datain terminal is written into the addressed latch. The addressed latch will follow the data input with all unaddressed
latches remaining in their previous states. In the memory
mode, all latches remain in their previous states and are
unaffected by the data or address inputs. To eliminate the
possibility of entering erroneous data in the latches, the enable should be held high (inactive) while the address lines
are changing. In the 1-of-8 decoding or demultiplexing
mode, the addressed output will follow the level of the D
input with all other outputs low. In the clear mode, all outputs are low and unaffected by the address and data inputs.
Connection Diagram
• Fan-out
IOL (sink current)
54LS2594 rnA
74LS259 8 rnA
IOH (source current) -0.4 rnA
• Typical Icc 22 rnA
Function Table
Inputs
Dual-In-Llne Package
vce
CLEAR
116
15
E
07
D
14
13
06
12
05
11
04
10
9
Clear
E
H
H
H
L
L
H
Output of
Addressed
Latch
Each
Other
Output
Function
D
aiO
D
L
aiO
aiO
L
L
Addressable Latch
Memory
8-Line Demultiplexer
Clear
L
L
Latch Selection Table
Select Inputs
3
2
A
B
c
5
4
00
01
6
02
Is
7
Q3
GND
Order Number 54LS259DMQB, 54LS259FMQB,
54LS259LMQB, DM74LS259WM or DM74LS259N
See NS Package Number E20A, J16A,
M16B, N16E or W16A
B
A
L
L
L
L
L
L
H
H
H
H
L
L
L
0
1
2
3
4
H
5
H
H
L
H
6
7
H
H
H
H
TL/F/6418-1
Latch
Addressed
C
L
L
H = High Level, L = Low Level
D = the Level 01 the Data Input
0,0 = the Level of OJ (I = O. 1•... 7, as Appropriate) belore the Indicated
Steady-State Input Conditions Were Established.
2-301
PI
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
54LS
- 55'C to + 125'C
DM74LS
O"Cto +70'C
Storage Temperature Range
-65"Cto + 150'C
Recommended Operating Conditions
Symbol
Vee
Supply Voltage
VIH
High Level Input Voltage
DM74LS259
54LS259
Parameter
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
2
VIL
Low Level Input Voltage
10H
High Level Output Current
10L
Low Level Output Current
tw
Pulse Width
(Note 7)
Enable
17
15
Clear
17
15
Setup TIme
(Notes 1, 2, 3 & 7)
Data
20t
15t
Select
15 !.
15 !.
Hold Time
(Notes 1, 2 & 7)
Data
5t
ot
Select
ot
-55
ot
tsu
tH
TA
V
V
0.7
0.8
V
-0.4
-0.4
mA
8
mA
4
Free Air Operating Temperature
Units
Min
125
ns
ns
ns
0
70
'C
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 4)
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vee = Min, 11= -18 mA
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
VIL = Max, VIH = Min
Low Level Output
Voltage
Vee = Min, 10L = Max
VIL = Max, VIH = Min
54LS
DM74
0.35
0.5
10L = 4 mA, Vee = Min
DM74
0.25
0.4
Input Current @ Max
Input Voltage
Vee = Max, VI = 7V
VI = 10V
DM74
IIH
High Level Input
Current
Vee = Max, VI = 2.7V
IlL
Low Level Input
Current
Vee = Max, VI
Enable
Vee = 5.0, VI
Short Circuit
Output Current
Vee = Max
(Note 5)
Supply Current
Vee
VOL
II
lOS
lee
54LS
2.5
DM74
2.7
V
3.4
0.4
V
0.1
mA
20
/LA
54LS
= O.4V
-0.4
= 0.4V
mA
-0.8
54LS
-20
-100
DM74
-20
-100
= Max (Note 6)
22
36
mA
mA
Note 1: The symbols (J., t) Indicate the edge of the clock pulse used for reference: t for rising edge, J. for failing edge.
NDta 2: Setup and hold times are with reference to the enable Input.
NDte S: The select·to-enable setup Ome 18 the Ome before the Hlgh·to·Low enable transiOon thattha select must be Slable so that the correct latch Is selected and
the others not affected.
Note 4: All typlcals are at Vee - SV, TA - 2S'O.
Note S: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 8: lee Is measured with all Inputs at4.5V, and all outputs open.
Nota 7: TA ~ 25'e and Vee = 5V.
2-302
Switching Characteristics at Vee = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
DM74LS
54LS
CL = 50pF
RL = 2kO
Parameter
From (Input)
To (Output)
tpLH
Propagation Delay Time
Low to High Level Output
Enable to
Output
27
38
ns
tpHL
Propagation Delay Time
High to Low Level Output
Enable to
Output
24
32
ns
tpLH
Propagation Delay Time
Low to High Level Output
Data to
Output
30
35
ns
tpHL
Propagation Delay Time
High to Low Level Output
Data to
Output
20
30
ns
tpLH
Propagation Delay Time
Low to High Level Output
Select to
Output
30
41
ns
tpHL
Propagation Delay Time
High to Low Level Output
Select to
Output
29
38
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clear to
Output
18
36
ns
Symbol
CL
Min
=
15pF
Max
Min
Units
Max
•
2·303
~ ~National
~ Semiconductor·
54LS260/DM74LS260
Dual5-lnput NOR Gate
General Description
This device contains two individual five input gates. each of
which perform the logic NOR function.
Connection Diagram
Dual-In-Llne Package
TLlF/9824-1
Order Number 54LS260DMQB, 54LS260FMQB,
54LS260LMQB, DM74LS260M or DM74LS260N
See NS Package Number E20A, J14A, M14A, N14A or W14B
2-304
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Input Voltage
7V
Operating Free Air Temperature Range
54LS
-55'C to + 125'C
DM74LS
O'Cto +70'C
Storage Temperature Range
-65'Cto +150'C
Recommended Operating Conditions
Symbol
54LS260
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
10H
High Level Output Current
10L
Low Level Output Current
TA
Free Air Operating Temperature
DM74LS260
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
V
2
V
0.7
0.8
V
-0.4
-0.4
mA
8
mA
70
·C
4
-55
125
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Typ
(Note 1)
Min
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vee = Min, 11= - 18 mA
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
Vil = Max
54LS
2.5
DM74
2.7
Low Level Output
Voltage
Vee = Min, 10l = Max
VIH = Min
54LS
0.4
DM74
0.5
10l = 4 mA, Vee = Min
DM74
0.4
VOL
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 10V
IIH
High Level Input Current
Vee = Max, VI = 2.7V
III
Low Level Input Current
Vee = Max, VI = 0.4V
Short Circuit
Output Current
los
Vee = Max
(Note 2)
V
V
0.1
mA
20
",A
54LS
-0.40
DM74
-0.36
54LS
-20
-100
DM74
-20
-100
mA
mA
ICCH
Supply Current with Outputs High
Vee = Max, VIN = GND
4.0
mA
leel
Supply Current with Outputs Low
Vee = Max, VIN = Open
5.5
mA
Nole 1: All typicals are at Vee
= 5V, TA = 25'C.
Nole 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Switching Characteristics
Vcc = + 5V, TA = + 25'C (See Section 1 for Test Waveforms and Ouput Load)
Symbol
Rl = 2kO,Cl = 15pF
Parameter
Min
Units
Max
tplH
Propagation Delay Time
Low to High Level Output
10
ns
tpHl
Propagation Delay Time
High to Low Level Output
12
ns
2-305
•
~
r------------------------------------------------------------------,
~ ~National
~ Semiconductor
54LS266/DM74LS266
Quad 2-lnput Exclusive-NOR Gate
with Open-Collector Outputs
General Description
This device contains four independent gates each of which
performs the logic exclusive-OR function. Outputs are open
collector.
Connection Diagram
Dual·ln·Llne Package
AO""":'+---.
BO
00-91--.....
Al~l--..,
Bl
01
GND
TUF/l0182-1
Order Number 54LS266DMQB, 54LS266FMQB, DM74LS266M or DM74LS266N
See NS Package Number J14A, M14A, N14A or W14B
Truth Table
Inputs
Outputs
A
B
Z
L
L
H
H
L
H
L
H
H
L
L
H
H = HIGH Voltage Level
L
= LOW Voltage Level
2·306
Absolute Maximum Ratings
(Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "£/ectrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
54LS
- 55'C to + 125'C
DM74LS
O'Cto +70'C
Storage Temperature Range
-65'C to + 150'C
Recommended Operating Conditions
Symbol
54LS266
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
10H
High Level Output Current
Min
4.5
DM74LS266
Min
Nom
Max
5
5.5
4.75
5
5.25
2
10L
Low Level Output Current
TA
Free Air Operating Temperature
Units
Nom
Max
V
V
2
0.7
0.8
V
-0.1
-0.4
mA
8
mA
70
'C
4
-55
125
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
VI
Input Clamp Voltage
Vee = Min, 11= -18 mA
VOH
High Level Output
Voltage
Vee = Min, 10H = Max,
VIL = Max
Low Level Output
Voltage
Vee = Min, 10L
VIH = Min
VOL
=
Max,
10L - 4 mA, Vee - Min
II
Input Current @ Max
Input Voltage
DM74
2.7
Units
-1.5
V
V
54LS
0.4
DM74
0.5
DM74
0.4
V
=
Max, VI
=
10V
=
Max, VI
=
=
2.7V
40
IJ-A
0.4V
-0.8
mA
IIH
High Level Input Current
Vee
Low Level Input Current
Vee = Max, VI
los
Short Circuit
Output Current
Vee = Max
(Note 2)
Supply Current
Vee = Max
Switching Characteristics at Vee =
Symbol
2.5
Max
Vee
IlL
Icc
54LS
Typ
(Note 1)
mA
0.2
54LS
-20
-100
DM74
-20
-100
mA
13
5V and TA
=
mA
25'C (See Section 1 for Test Waveforms and Output Load)
RL = 2kO
CL = 15pF
Parameter
Min
Units
Max
tpLH
Propagation Delay Time
Low to High Level Output
23
ns
tpHL
Propagation Delay Time
High to Low Level Output
23
ns
Nole 1: All typicals are at Vee = 5V, TA = 25'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
2-307
•
§ ~National
~ Semiconductor
54LS273/DM74LS273
8-Bit Register with Clear
General Description
Features
The 'LS273 is a high speed 8-bit register, consisting of eight
Ootype flip-flops with a common Clock and an asynchronous
active LOW Master Reset. This device is supplied in a 20pin package featuring 0.3 Inch row spacing.
•
•
•
•
Edge-triggered
8-bit high speed register
Parallel in and out
Common clock and master reset
Connection Diagram
Dual-In-Llne Package
Mii-l
"-"
00- 2
00- 3
01- 4
01- 5
20 -Vee
19 -07
18 -07
17 1-06
161-06
02- 6
02- 7
03- 8
151-05
14 1-05
13 1-04
03- 9
121-04
l11-CP
GNO- 10
TUF/9825-1
Order Number 54LS273DMQB, 54LS273FMQB,
54LS273LMQB, DM74LS273M or DM74LS273N
See NS Package Number E20A, J20A, M20B,
N20AorW20A
Pin Names
CP
00-07
MR
00-07
Description
Clock Pulse Input (Active Rising Edge)
Oatalnputs
Asynchronous Master Reset Input
(Active LOW)
Flip-Flop Outputs
2-308
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
54LS
-55'C to + 125'C
DM74LS
O'Cto +70'C
Storage Temperature Range
-65'Cto + 150'C
Recommended Operating Conditions
Symbol
54LS273
Parameter
Vee
Supply Voltage
V,H
High Level Input Voltage
V,L
Low Level Input Voltage
10H
High Level Output Current
10L
Low Level Output Current
DM74LS273
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
2
-55
V
V
0.7
0.8
V
-0.4
-0.4
mA
4
8
mA
70
'c
TA
Free Air Operating Temperature
t 8 (H)
t 8 (L)
Setup Time HIGH or LOW
Dn to CP
15
15
125
15
15
0
ns
th(H)
th(L)
Hold Time HIGH or LOW
Dn toCP
5
5
5
5
ns
tw(H)
tw(L)
CP Pulse Width HIGH or LOW
20
20
20
20
ns
tw(L)
MR Pulse Width LOW
20
20
ns
tree
Recovery Time
MRtoCP
15
15
ns
Electrical Characteristics
Over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
= Min,l, = -18 mA
= Max,
V,
Input Clamp Voltage
Vee
VOH
High Level Output
Voltage
Vee = Min, 10H
V,L = Max
Low Level Output
Voltage
Vee = Min, 10L
V,H = Min
VOL
= Max,
= 4 mA, Vee = Min
Vee = Max, V, = 10V
10L
I,
Input Current @ Max
Input Voltage
I'H
High Level Input Current
Vee
= Max, V, =
2.7V
=
0.4V
I,L
Low Level Input Current
Vee
los
Short Circuit
Output Current
Vee = Max
(Note 2)
Max, V,
=
Min
54LS
2.5
DM74
2.7
Max
Units
-1.5
V
V
3.4
0.4
54LS
DM74
0.35
0.5
DM74
0.25
0.4
V
0.1
mA
20
/LA
-0.4
mA
54LS
-20
-100
DM74
-20
-100
Supply Current
Vee = Max
lee
Note 1: All typical. are at Vee = SV, TA = 2S'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
2-309
Typ
(Note 1)
27
mA
mA
•
Switching Characteristics
Vee =
+ 5.0V, TA
=
+ 25°C (See Section 1 for waveforms and load configurations)
CL = 15pF
Symbol
Parameter
DM74LS
54LS
Min
Min
Max
Unite
Max
fmax
Maximum Clock Frequency
tpLH
tpHL
Propagation Delay
CP to On
32
32
24
24
ns
tpLH
Propagation Delay
MR to an
32
27
ns
30
30
Functional Description
MHz
Truth Table
The 'LS273 is an S-bit parallel register with a common Clock
and common Master Reset. When the MR Input is LOW, the
o outputs are LOW, independent of the other inputs. Information meeting the setup and hold time requirements of the
D inputs Is transferred to the 0 outputs on the LOW-toHIGH transition of the clock input.
MR
L
H
H
Inpute
CP
Dn
Qn
X
X
L
H
L
...r
...r
Outputs
H
L
H = HIGH Voltage Level
L = LOW VoHage Level
X = Immaterial
Logic Symbol
3
It
~
7 8 13
1~
17 18
CP
1 2 5 6 9 12 15 16 19
TLlF/9825-2
Vee = Pin 20
GND = Pin 10
Logic Diagram
DO
.1
D2
D3
2-310
~
D5
DO
D7
~National
~ Semiconductor
54LS279/DM54LS279/DM74LS279
Quad S-R Latches
General Description
The 'LS279 consists of four individual and independent SetReset Latches with active low inputs. Two of the four latches have an additonal S input ANDed with the primary S
input. A Iowan any S input while the R input is high will be
stored in the latch and appear on the corresponding a output as a high. A Iowan the R input while the S input is high
will clear the output to a low. Simultaneous transistion of
the Rand S inputs from low to high will cause the output
a
a
to be indeterminate. Both inputs are voltage level triggered
and are not affected by transition time of the input data.
Features
• Alternate military/aerospace device (54LS279) is available. Contact a National Semiconductor Sales Office/
Distributor for specifications.
Connection Diagram
Dual-In-Llne Package
Vee
48
4R
1R
181
182
10
2ii
3!i1
3R
30
28
20
GND
TL/F/6420-1
Order Number 54LS279DMQB, 54LS279FMQB, 54LS279LMQB,
DM54LS279J, DM74LS279M or DM74LS279N
See NS Package Number E20A, J16A, M16A, N16E or W16A
Function Table
Inputs
H
L
Output
S(l)
R
Q
L
L
L
H
H"
H
H
H
L
L
H
00
= High Level
= Low Level
00 = The Level of 0 before the Indicated input cond"lons were established.
'This output level is pseudo sleble; that is, it may not persist when the 5 and A
inputs return to their Inactive (high) level.
Note1: For latches with double 5 Inputs:
H
= both 5
inputs high
L = one or both S Inputs low
2-311
•
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National SemIconductor Sales
Office/Distributors for availability and speCifIcatIons.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
- 55·C to + 125·C
DM54LS and 54LS
DM74LS
O·Cto +70·C
Storage Temperature Range
-65·C to + 1500C
Recommended Operating Conditions
Symbol
DM54LS279
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
10H
10L
TA
Free Air Operating Temperature
DM74LS279
UnIts
MIn
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
V
V
2
0.7
0.8
V
High Level Output Current
-0.4
-0.4
mA
Low Level Output Current
4
8
mA
70
·c
-55
125
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
= Min, II = -18 mA
= Min, 10H = Max
VIL = Max, VIH = Min
Vcc = Min, 10L = Max
VIL = Max, VIH = Min
VI
Input Clamp Voltage
Vcc
VOH
High Level Output
Voltage
Vee
VOL
Low Level Output
Voltage
MIn
Typ
(Note 1)
DM54
2.5
3.5
DM74
2.7
3.5
CondItIons
= 4 mA, Vcc = Min
Vcc = Max, VI = 7V
10L
II
Input Current @ Max
Input Voltage
IIH
High Level Input
Current
VCC
IlL
Low Level Input
Current
VCC
los
Short Circuit
Output Current
Vcc = Max
{Note 2)
DM54
Max
UnIts
-1.5
V
V
0.25
0.4
DM74
0.35
0.5
DM74
0.25
0.4
V
0.1
rnA
= Max, VI = 2.7V
20
p.A
= Max, VI = 0.4V
-0.4
mA
DM54
-20
-100
DM74
-20
-100
Supply Current
Vee = Max (Note 3)
at Vcc = SV, TA = 2S'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: Icc Is measured with all A Inputs grounded, all 5 inputs at 4.SV and all outputs open.
Icc
Nole 1: All typlcals are
2-312
3.8
7
mA
mA
Switching Characteristics at Vee = 5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
RL
= 2kn
Parameter
From (Input)
To (Output)
tpLH
Propagation Delay Time
Low to High Level Output
Sto
Q
22
25
ns
tpHL
Propagation Delay Time
High to Low Level Output
Sto
Q
15
23
ns
tpHL
Propagation Delay Time
High to Low Level Output
Rto
Q
27
33
ns
Symbol
CL
Min
2-313
=
15pF
Max
CL
Min
=
50pF
Units
Max
~ ~ National
.
~ Semiconductor
54LS283/DM54LS283/DM74LS283
4·Bit Binary Adders with Fast Carry
General Description
Features
These full adders perform the addition of two 4-bit binary
numbers. The sum (I) outputs are provided for each bit and
the resultant carry (C4) is obtained from the fourth bit.
These adders feature full internal look ahead across all four
bits. This provides the system designer with partial lookahead performance at the economy and reduced package
count of a ripple-carry implementation.
• Full-carry look-ahead across the four bits
• Systems achieve partial look-ahead performance with
the economy of ripple carry
• Typical add times
Two B-bit words 25 ns
Two 16-bit words 45 ns
• Typical power dissipation per 4-blt adder 95 mW
• Alternate Military/Aerospace device (54LS283) is available. Contact a National Semiconductor Sales Office/
Distributor for specifications.
The adder logic, including the carry, is implemented in its
true form meaning that the end-around carry can be accomplished without the need for logic or level inversion.
Connection Diagram
Dual-In-Llne Package
A3
B3
15
2
1
1:2
B2
1:3
14
3
A2
A4
13
12
4
1:1
B4
11
5
A1
8
B1
C4
1:4
10
7
CO
9
18
GND
TUF/6421-1
Order Number 54LS283DMQB, 54LS283FMQB, 54LS283LMQB,
DM54LS283J, DM54LS283W, DM74LS283M or DM74LS283N
see NS Package Number E20A, J18A, M16A, N16E or W16A
2-314
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
DM54LS and 54LS
- 55'C to + 125'C
DM74LS
O'Cto +70'C
Storage Temperature Range
- 65'C to + 150'C
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Recommended Operating Conditions
Symbol
DM54LS283
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
10H
10L
TA
Free Air Operating Temperature
DM74LS283
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
V
V
2
0.7
O.B
V
High Level Output Current
-0.4
-0.4
mA
Low Level Output Current
4
8
mA
70
'C
-55
125
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 1)
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vee = Min, II = -18 mA
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
VIL = Max, VIH = Min
DM54
2.5
3.4
DM74
2.7
3.4
Low Level Output
Voltage
Vee = Min, 10L = Max
VIL = Max, VIH = Min
DM54
0.25
0.4
DM74
0.35
0.5
IOL = 4 mA, Vee = Min
DM74
0.25
0.4
Input Current @ Max
Input Voltage
Vcc = Max
VI = 7V
A,S
0.2
CO
0.1
High Level Input
Current
Vee = Max
VI = 2.7V
A,S
40
CO
20
Low Level Input
Current
Vcc = Max
VI = O.4V
A,S
-0.8
CO
-0.4
Short Circuit
Output Current
Vee = Max
(Note 2)
Supply Current
Vcc = Max (Note 3)
VOL
II
IIH
IlL
los
ICCl
DM54
-20
-100
DM74
-20
-100
Supply Current
Vee = Max (Note 4)
ICC2
Nota 1: Aillypicals are at Vcc = 5V, TA = 25'C.
Nota 2: Not more than one output should be shorted at a time, and the duration should not exceed one sacond.
Nota 3: ICCI is measured with all outputs open, all 8 inputs low and all other inputs a14.5V, or all inputs aI4.5V.
Nota 4: IC02 is measured with all outputs open and all Inputs grounded.
2-315
V
V
mA
".A
mA
mA
19
34
mA
22
39
mA
•
Switching Characteristics at Vcc =
5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
RL = 2kO
Symbol
From (Input)
To (Output)
Parameter
CL = 15pF
Min
CL=50pF
Max
Min
Units
Max
tpLH
Propagation Delay Time
Low to High Level Output
CO to
:I1,:I2
24
28
ns
tpHL
Propagation Delay Time
High to Low Level Output
CO to
:I1, :I2
24
30
ns
tpLH
Propagation Delay Time
Low to High Level Output
CO to
:I3
24
28
ns
tpHL
Propagation Delay Time
High to Low Level Output
CO to
:I3
24
30
ns
tpLH
Propagation Delay Time
Low to High Level Output
CO to
:I4
24
28
ns
tpHL
Propagation Delay Time
High to Low Level Output
CO to
:I4
24
30
ns
tpLH
Propagation Delay Time
Low to High Level Output
AjorBI
to :Ij
24
28
ns
tpHL
Propagation Delay Time
High to Low Level Output
Aj or Bj
to :Ij
24
30
ns
tpLH
Propagation Delay Time
Low to High Level Output
CO to
C4
17
24
ns
tpHL
Propagation Delay Time
High to Low Level Output
CO to
C4
17
25
ns
tpLH
Propagation Delay Time
Low to High Level Output
AjorBj
toC4
17
24
ns
tpHL
Propagation Delay Time
High to Low Level Output
AjorBj
toC4
17
26
ns
Function Table
Outputs
~ ~
Input
WhenC2 = L
% X
A3
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
B3
~X
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
B4
WhenC2 = H
X X X X X X
:I3
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
l:4
L
L
L
H
H
H
H
L
H
H
H
L
L
L
L
H
l:3
C4
L
L
L
L
L
L
L
H
L
L
L
H
H
H
H
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
l:4
L
H
H
H
H
L
L
L
H
L
L
L
L
H
H
H
C4
L
L
L
L
L
H
H
H
L
H
H
H
H
H
H
H
TL/F/6421-3
H = Hjgh Level, L = Low Level
Nota: Input condjtions at AI, 81, A2, 82, and CO are used to determine outputs 1:1 and 1:2 and the value of the Internal carry C2. The values at C2, A3, 83, A4, and
84 are then used to determine outputs 1:3, 1:4, and C4.
2-316
~--------------------------li
Logic Diagram
LS283
\n----(9)
C4
B3
A3 ":':""-4"""-__
B2
A2"':';;:'_"",,-_
"'--1"OL.._~----'~~1
TUF/6421-2
•
2-317
~
II?A National
~ Semiconductor
DM74LS290 4-Bit Decade Counter
General Description
The 'LS290 counter is electrically and functionally identical
to the 'LS90. Only the arrangement of the terminals has
been changed for the 'LS290.
Each of these monolithic counters contains four masterslave flip-flops and additional gating to provide a divide-bytwo counter and a three-stage binary counter for which the
count cycle length is divide-by-five.
This counter has a gated zero reset and gated set-to-nine
inputs for use in BCD nine's complement applications.
To use the maximum count length (decade) of this counter,
the B input is connected to the QA output. The input count
pulses are applied to input A and the outputs are as de-
scribed in the appropriate function table. A symmetrical divide-by-ten count can be obtained from the 'LS290 counter
by connecting the Qo output to the A input and applying the
input count to the B input which gives a divide-by-ten square
wave at output QA.
Features
• GND and Vee on Corner Pins
(Pins 7 and 14 respectively)
• Typical power disSipation 45 mW
• Count frequency 42 MHz
Connection Diagram
Dual-In-Llne Package
RO(2)
RO(l)
INPUT
S
INPUT
A
13
12
11
10
3
"
5
12
R9(1)
NC
R9(2)
Oc
Os
00
B
6
1
NC
17
GNO
TLIF/6422-1
Order Number DM74LS290M or DM74LS290N
See NS Package Number M14A or N14A
2-318
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics'·
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Input Voltage
7V
Operating Free Air Temperature Range
O'Cto +70'C
DM74LS
Storage Temperature Range
-65'C to + 150'C
Recommended Operating Conditions
Symbol
DM74LS290
Parameter
Vcc
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
Units
Min
Nom
Max
4.75
5
5.25
V
0.8
V
2
V
10H
High Level Output Current
-0.4
mA
10L
Low Level Output Current
8
mA
fCLK
Clock Freq. (Note 1)
fCLK
tw
Clock Freq. (Note 2)
Pulse Width (Note 6)
AtoOA
0
32
BtoOB
0
16
AtoOA
0
20
BtoOB
0
10
A
15
B
30
Reset
15
tREL
Reset Release Time (Note 6)
25
TA
Free Air Operating Temperature
0
MHz
MHz
ns
ns
70
'C
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
VI
Input Clamp Voltage
VOH
High Level Output
Voltage
VOL
Low Level Output
Voltage
II
IIH
IlL
Input Current @ Max
Input Voltage
High Level Input
Current
Low Level Input
Current
Min
Conditions
= Min, II = -18 mA
Vcc = Min, 10H = Max
VIL = Max, VIH = Min
Vcc = Min, 10L = Max
VIL = Max, VIH = Min
10L = 4 mA, VCC = Min
VCC = Max, VI = 7V
Typ
(Note 3)
Vcc
VCC
= Max, VI = 2.7V
Vee = Max
VI = 0.4V
los
Short Circuit
Output Current
Vee = Max
(Note 4)
Icc
Supply Current
VCC
2.7
2-319
Units
-1.5
V
3.4
V
0.35
0.5
0.25
0.4
Reset
0.1
A
0.2
B
0.4
Reset
20
A
40
B
80
Reset
-0.4
A
-2.4
B
-3.2
-20
= Max (Note 5)
Max
9
V
mA
p.A
mA
-100
mA
15
mA
•
Switching Characteristics at Vee = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
RL = 2kO
From (Input)
Symbol
Parameter
Units
CL = 15pF
CL = 50pF
To (Output)
fMAX
Maximum Clock
Frequency
Min
Max
Min
AtoQA
32
20
BtoQB
16
10
tpLH
Propagation Delay Time
Low to High Level Output
tpHL
Propagation Delay Time
High to Low Level Output
tpLH
Propagation Delay Time
Low to High Level Output
Ato
QA
Ato
QA
Ato
Qo
tpHL
Propagation Delay Time
High to Low Level Output
Ato
Qo
tpLH
Propagation Delay Time
Low to High Level Output
tpHL
Propagation Delay Time
High to Low Level Output
Bto
QB
Bto
QB
tpLH
Propagation Delay Time
Low to High Level Output
Bto
Qc
tpHL
Propagation Delay Time
High to Low Level Output
tpLH
Propagation Delay Time
Low to High Level Output
tpHL
Propagation Delay Time
High to Low Level Output
Bto
Qc
Bto
Qo
Bto
Qo
tpLH
Propagation Delay Time
Low to High Level Output
tpHL
Propagation Delay Time
High to Low Level Output
Max
MHz
16
23
ns
18
30
ns
48
60
ns
50
68
ns
16
23
ns
21
35
ns
32
48
ns
35
53
ns
32
48
ns
35
53
ns
SET·9 to
QA,QO
30
38
ns
SET·9to
QB,QC
40
53
ns
Propagation Delay Time
SET·Oto
40
53
High to Low Level Output
AnyQ
Note 1: CL = IS pF, RL = 2 kll, TA = 2S'C and Vee = SV.
Note 2: CL = 50 pF, RL - 2 kll, TA = 2S'C and Vee = SV.
Note 3: Aillypicals are at Vee = 5V, TA = 2S'C.
Note 4: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 5: lee is measunsd with all outputs open, both RO Inputs grounded following momentary connection to 4.SV and all other Inputs grounded.
Note 6: TA = 2S'C and Vee SV.
tpHL
2·320
ns
r
Function Tables
BCD Count Sequence
(See Note A)
QD
0
1
2
3
4
L
L
L
L
L
L
L
L
H
H
5
6
7
8
9
Qc
L
L
L
L
H
H
H
H
L
L
Qs
L
L
H
H
L
L
H
H
L
L
R9(2)
~
o
]
(3)
J
QA
L
H
L
H
L
H
L
H
L
H
~
OA
CLOCK
INPUT A
K
Y
LJ
(5)
a
as
(11)
INPUT S
CLOCK
K
High Logic Level
L = Low Logic Level
X
(9)
a
(10)
Note A: Output QA is connected to input B for
BCD count
H
N
CD
(1)
R9(1)
Output
Count
en
Logic Diagram
n
Either Low or High Logic Level
Bi-Quinary (5-2)
(See Note B)
J
Output
Count
QA
0
1
2
3
4
L
L
L
L
L
H
H
H
H
H
5
6
7
8
9
Qs
L
L
L
L
H
L
L
L
L
H
Qc
QD
(4)
a
Oc
CLOCK
L
L
H
H
L
L
L
H
H
L
L
H
L
H
L
L
H
L
H
L
K
~
I
l :::J J
Note S: Output QD is connected to input A for biquinary count.
!
(8)
a
00
CLOCK
Q t--
~K
(12)
RO(l)
RO(2)
r-
J
(13)
TlIF/6422-2
Reset/Count Truth Table
Reset Inputs
Outputs
RO(l)
RO(2)
R9(1)
R9(2)
QD
Qc
Qs
QA
H
H
X
X
L
L
X
H
H
X
L
X
X
L
L
X
H
X
L
X
L
X
L
H
L
X
L
X
L
L
H
L
L
L
L
L
L
L
L
H
COUNT
COUNT
COUNT
COUNT
2-321
~
G)
,----------------------------------------------------------------------------,
~ ~National
~ Semiconductor
DM74LS293 4-Bit Binary Counter
General Description
The 'LS293 counter is electrically and functionally identical
to the 'LS93. Only the arrangement of the terminals has
been changed for the 'LS293.
To use the maximum count length (four-bit binary) of these
counters, the B input is connected to the QA output. The
input count pulses are applied to input A and the outputs are
as described in the appropriate function table.
Each of these monolithic counters contains four masterslave flip-flops and additional gating to provide a divide-bytwo counter and a three-stage binary counter for which the
count cycle length is divide-by-eight.
Features
• GND and Vee on Corner Pins (Pins 7 and 14
respectively)
• Typical power dissipation 45 mW
• Count frequency 42 MHz
All of these counters have a gated zero reset.
Connection Diagram
Dual-In-Llne Package
vr4
11
NC
RO(2)
13
12
NC
RO(l)
12
13
NC
INPUT
B
INPUT
A
11
10
4
5
Oc
OB
OA
9
16
NC
Order Number DM74LS293M or DM74LS293N
See NS Package Number M14A or N14A
2-322
00
B
17
GND
TL/F/6423-1
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
O·Cto +70·C
DM74LS
-65·Cto + 150·C
Storage Temperature Range
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Recommended Operating Conditions
Symbol
DM74LS293
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
Units
Min
Nom
Max
4.75
5
5.25
V
0.8
V
V
2
IOH
High Level Output Current
-0.4
mA
IOL
Low Level Output Current
8
mA
feLK
Clock Frequency
(Note 1)
AtoOA
0
32
BtoOB
0
16
Clock Frequency
(Note 2)
AtoOA
0
20
BtoOB
0
10
Pulse Width
(Note 6)
A
15
B
30
Reset
15
feLK
tw
tREL
Reset Release Time (Note 6)
25
TA
Free Air Operating Temperature
0
MHz
MHz
ns
ns
·c
70
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
=
=
VI
Input Clamp Voltage
Vee
VOH
High Level Output
Voltage
Vee = Min,lOH = Max
VIL = Max, VIH = Min
VOL
Low Level Output
Voltage
Vee = Min, IOL = Max
VIL = Max, VIH = Min
II
Input Current @ Max
Input Voltage
Vee = Max
VI = 7V
IOL
IIH
IlL
High Level Input
Current
Low Level Input
Current
=
Min,ll
4 mA, Vee
=
Vee = Max
(Note 4)
lee
Supply Current
Vee
=
2.7
Min
Vee = Max
VI = 0.4V
Short Circuit
Output Current
Typ
(Note 3)
-18 mA
Vee = Max
VI = 2.7V
los
Min
-1.5
V
V
0.35
0.5
0.25
0.4
Reset
0.1
A
0.2
B
0.2
Reset
20
A
40
B
40
V
mA
p.A
-0.4
A
-2.4
B
-1.6
-20
2-323
Units
3.4
Reset
Max (Note 5)
Max
9
mA
-100
mA
15
mA
Switching Characteristics at Vee =
5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
RL = 2kCl.
From (Input)
Symbol
Parameter
CL = 15pF
To (Output)
Min
tMAX
Maximum Clock
Frequency
Max
CL=50pF
Min
AtoOA
32
20
BtoOB
16
10
Units
Max
MHz
tpLH
Propagation Delay Time
Low to High Level Output
AtoOA
16
23
ns
tpHL
Propagation Delay Time
High to Low Level Output
AtoOA
18
30
ns
tpLH
Propagation Delay Time
Low to High Level Output
AtoOD
70
87
ns
tpHL
Propagation Delay Time
High to Low Level Output
AtoOD
70
93
ns
tpLH
Propagation Delay Time
Low to High Level Output
BtoOB
16
23
ns
tpHL
Propagation Delay Time
High to Low Level Output
BtoOB
21
35
ns
tpLH
Propagation Delay Time
Low to High Level Output
BtoOc
32
48
ns
tpHL
Propagation Delay Time
High to Low Level Output
BtoOc
35
53
ns
tpLH
Propagation Delay Time
Low to High Level Output
BtoOD
51
71
ns
tpHL
Propagation Delay Time
High to Low Level Output
BtoOD
51
71
ns
tpHL
Propagation Delay Time
High to Low Level Output
SET-Oto
Any 0
40
53
ns
Nole I: CL = 15 pF, RL = 2 kfl, TA = 2S'C and Vee = SV.
Nole 2: CL = SO pF, RL = 2 kfl, TA = 2S'C and Vee = SV.
Note 3: All typicals are at Vee = SV, TA = 2S'C.
Nole 4: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 5: lee is measured with all outputs open, both RO inputs grounded following momentary connection to 4.SV and all other Inputs grounded.
Note 6: TA
= 2S'C and Vee = SV.
2-324
Function Tables
Count Sequence (See Note C)
0
1
2
3
4
5
6
7
B
9
10
11
12
13
14
15
Reset/Count Truth Table
Outputs
Count
QD
QC
QB
QA
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
Reset Inputs
H
Outputs
RO(1)
RO(2)
QD
Qc
QB
QA
H
L
H
L
L
L
L
X
L
COUNT
COUNT
X
= High Level, L = Low Level, X = Don't Care.
Nole C: Output QA is connected to Input B.
Logic Diagram
LS293
-
(9)
J
O-OA
('0)
CLOCK
INPUT A
K
"I
J
15)
0
Oa
(11)
CLOCK
INPUT B
K
T
r--J
'--<
(4)
O--Oc
>CLOCK
•
K
-r
J
(a)
Q~OD
--- >
CLOCK
K
""T
(12)
RO(')
R0(2) (13)
]
TL/F/6423-2
Note: The J and K Inputs shown without connection are for reference only and are functionally at a high level.
2-325
~National
r.I Semiconductor
54LS295A/DM74LS295A
4-Bit Shift Register with TRI-STATE® Outputs
General Description
Features
The 'LS295A is a 4-bit shift register with serial and parallel
synchronous operating modes, and independent TRISTATE output buffers. The Parallel Enable input (PE) controls the shift-right or parallel load operation. All data transfers and shifting occur synchronous with the HIGH-to-LOW
clock transition.
The TRI-STATE output buffers are controlled by an active
HIGH Output Enable input (OE). Disabling the output buffers
does not affect the shifting or loading of input data, but it
does inhibit serial expansion. The device is fabricated with
the Schottky barrier diode process for high speed.
•
•
•
•
Connection Diagram
Logic Symbol
Fully synchronous serial or parallel data transfers
Negative edge-triggered clock input
Parallel enable mode control input
TRI-STATE bussable output buffers
iii i i
Dual-In-Llne Package
'-.....,I
PE PO PI P2 P3
14 I-Vcc
131-00
Os-I
PO- 2
PI- 3
P2- 4
P3- 5
PE- 6
121-01
111-02
101-03
91-CP
GND- 7
al-OE
I-Os
9-(l CP
a-OE
00
01
TL/FI10183-2
TL/F110183-1
PE
Os
PO-P3
OE
CP
00-03
03
vee = Pin 14
GND = Pin 7
Order Number 54LS295ADMQB, 54LS295AFMQB,
DM74LS295AM or DM74LS295AN
See NS Package Number J14A, M14A, N14A or W14B
Pin Names
02
Description
Parallel Enable Input (Active HIGH)
Serial Data Input
Parallel Data Inputs
TRI-STATE Output Enable Input (Active HIGH)
Clock Pulse Input (Active Falling Edge)
TRI-STATE Outputs
2-326
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
Input Voltage
Operating Free Air Temperature Range
54LS
OM74LS
Storage Temperature Range
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
7V
7V
-55'Cto + 125'C
O'Cto +70'C
- 65'C to + 150'C
Recommended Operating Conditions
Symbol
54LS295A
Parameter
DM74LS295A
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
0.7
0.8
V
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
VOH
High Level Output Current
-1.0
-2.6
rnA
10L
Low Level Output Current
4
8
mA
TA
Free Air Operating Temperature
70
'C
ts(H)
ts(L)
Setup Time HIGH or LOW
OS, Pn to CP
20
20
20
20
ns
th(H)
th (L)
Hold Time HIGH or LOW
OS, Pn to CP
10
10
10
10
ns
ts(H)
ts (L)
Setup Time HIGH or LOW
PEtoCP
20
20
20
20
ns
th (H)
th (L)
Hold Time HIGH or LOW
PEtoCP
0
0
0
0
ns
twILl
CP Pulse Width LOW
20
20
ns
2
V
2
-55
125
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 1)
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vee = Min, 11= -18 rnA
VOH
High Level Output
Voltage
Vee = Min, 10H = Max,
VIL = Max
54LS
2.4
OM74
2.4
Low Level Output
Voltage
Vee = Min, 10L = Max,
VIH = Min
54LS
0.4
OM74
0.5
10L = 4 rnA, Vee = Min
OM74
0.4
VOL
V
V
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 10V
IIH
High Level Input Current
Vee = Max, VI = 2.7V
20
",A
IlL
Low Level Input Current
Vee = Max, VI = 0.4V
-0.4
mA
los
Short Circuit
Output Current
Vee = Max
(Note 2)
Supply Current
Outputs ON
Vee = Max, Pn = GNO
PE, OS, OE = 4.5V, CP = ' -
23
rnA
Outputs OFF
Vee = Max, PE, OS = 4.5V
Pn, OE, CP = GNO
25
rnA
leeH
2-327
0.1
54LS
-20
-100
OM74
-20
-100
rnA
rnA
•
Electrical Characteristics (Continued)
over recommended operating free air temperature range (unless otherwise noted)
Symbol
IOZH
IOZL
Parameter
Conditions
Min
Typ
(Note 1)
Max
Units
Off·State Output Current
with High Level Output
Voltage Applied
Vee = Max, Vo = 2.7V
VIH = Min, VIL = Max
20
/J- A
Off·State Output Current
with Low Level Output
Voltage Applied
Vee = Max, Vo = O.4V
VIH = Min, VIL = Max
-20
/J- A
Note 1: All Iyplcals are at Vee = 5V. TA = 25'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Switching Characteristics
= + 5.0V, TA = + 25'C (See Section 3 for waveforms and load configurations)
Vee
54174LS
Symbol
Parameter
RL
Min
= 2kO,CL = 15pF
Units
Max
f max
Maximum Shift Frequency
tpLH
tpHL
Propagation Delay
CP to Q n
30
30
26
ns
tPZH
tpZL
Output Enable Time
18
20
ns
tpHZ
tpLZ
Output Disable Time
24
20
ns
2·328
MHz
In
Functional Description
I\)
CD
This device is a 4-bit shift register with serial and parallel
synchronous operating modes. It has a Serial Data (Os) and
four Parallel Data (PO-P3) inputs and four parallel TRISTATE output buffers (00-03). When the Parallel Enable
(PE) input is HIGH, data is transferred from the Parallel Data
inputs (PO-P3) into the register synchronous with the HIGHto-LOW transition of the Clock (CP). When the PE is LOW, a
HIGH-to-LOW transition on the clock transfers the serial
data on the Os input to the register 00, and shifts data from
00 to 01, 01 to 02 and 02 to 03. The input data and
parallel enable are fully edge-triggered and must be stable
only one setup time before the HIGH-to-LOW clock transition.
The TRI-STATE output buffers are controlled by an active
HIGH Output Enable input (OE). When the OE is HIGH, the
four register outputs appear at the 00-03 outputs. When
OE is LOW, the outputs are forced to a high impedance
OFF state. The TRI-STATE output buffers are completely
independent of the register operation, i.e., the input transitions on the OE input do not affect the serial or parallel
data transfers of the register. If the outputs are tied together, all but one device must be in the high impedance state to
avoid high currents that would exceed the maximum ratings.
Designers should ensure that Output Enable Signals to TRISTATE devices whose outputs are tied together are deSigned so there is no overlap.
~
Mode Select Table
Operating
Mode
Inputs
PE
CP
Shift Right
I
I
'-
Parallel Load
h
''-
Outputs
Ds Pn
QO
Q1
Q2
Q3
I
h
X
X
L
H
qo
qo
q1
q1
q2
q2
X
Pn
pO
p1
p2
p3
'The indicaled dala appears allhe Q outputs when OE is HIGH. When OE is
LOW, Ihe Indicaled data Is loaded Inlo the register. bul the outputs are all
forced to the high impedance OFF slale.
Pn (qn) - Lower case letters indicate the state of the referenced input (or
output) one set-up time prior to the HIGH·to·LOW clock transition.
I - LOW Voltage level one set·up lime prior 10 the HIGH-la-LOW clock
transition.
h = HIGH Voltage level one sel-up lime prior to Ihe HIGH-lo-lOW clock
transition.
H - HIGH Voltage level
L = LOW Voltage Level
X - Immalerial
Logic Diagram
PI
PO
P3
P2
PE
OE--I~------------------------~--~-----------4--+------------4--+-----------~
01
00
02
03
TL/F/l0183-3
2-329
•
m
~------------------------------------------------------------------------,
~ ~National
~ Semiconductor
54LS298/DM74LS298 Quad 2-Port
Register Multiplexer with Storage
General Description
Features
The 'LS298 is a quad 2-port register. It is the logical equivalent of a quad 2-input multiplexer followed by a quad 4-bit
edge-triggered register. A Common Select input selects between two 4-bit input ports (data sources). The selected
data is transferred to the output register synchronous with
the HIGH-to-LOW transition of the Clock input.
• Select from two data sources
• Fully edge-triggered operation
• Typical power dissipation of 65 mW
Connection Diagram
Logic Symbol
Dual-In-Une Package
I1b- 1
\.../
iiiiiiii
l1a- 2
16 r-Vcc
15 r-Qa
108- 3
14 r.Qb
10-S
10b- 4
13 r-Qc
11--cl....·c__...J
gl'i
2-337
~ r-------------------------------------------------------------------------------~
~
!i
~ National
~ Semiconductor
54LS322/DM74LS322
8-Bit Serial/Parallel Register with Sign Extend
General Description
The 'LS322 is an 8-bit shift register with provision for either
serial or parallel loading and with TRI-STATE® parallel outputs plus a bi-state serial output. Parallel data inputs and
parallel outputs are multiplexed to minimize pin count. State
changes are initiated by the rising edge of the clock. Four
synchronous modes of operation are possible: hold (store),
shift right with serial entry, shift right with sign extend and
parallel load. An asynchronous Master Reset (MR) input
overrides clocked operation and clears the register. The
'322 is specifically designed for operation with the '384 Multiplier and provides the sign extend function required for the
'384.
Connection Diagram
Logic Symbol
19 3 17
Dual-In-Llne Package
RE
SIP
2
19
Vee
S
DO
3
18
SE
2
20
1/07
4
01
18
1/05
5
1/06
11
1/03
6
1/04
8
1/01
7
1/02
OE
i.iR
8
1/00
9
00
GNO
10
CP
9
4
16
GND = Pin 10
Order Number 54LS322DMQB, 54LS322FMQB,
DM74LS322WM or DM74LS322N
See NS Package Number J20A, M20B, N20A or W20A
Pin Names
sip
SE
S
00,01
CP
MR
OE
00
1/00-1/07
6 14
7 13 12
TLIF19828-2
vee = Pin 20
TLIFI982B-1
RE
5 'IS
Description
Register Enable Input (Active LOW)
Serial (HIGH) or Parallel (LOW)
Mode Control Input
Sign Extend Input (Active LOW)
Serial Data Select Input
Serial Data Inputs
Clock Pulse Input (Active Rising Edge)
Asynchronous Master Reset Input
(Active LOW)
TRI-STATE Output Enable Input
(Active LOW)
Bi-State Serial Output
Multiplexed Parallel Inputs or
TRI-STATE Parallel Outputs
2-338
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Input Voltage
10V
Operating Free Air Temperature Range
54LS
- 55·C to + 125·C
DM74LS
O·Cto +70·C
Storage Temperature Range
-65·Cto + 150·C
Recommended Operating Conditions
Symbol
54LS322
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Vollage
IOH
IOL
DM74LS322
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
2
V
V
0.7
0.8
High Level Output Current
-0.4
-0.4
mA
Low Level Output Current
4
8
mA
70
·C
-55
V
TA
Free Air Operating Temperature
ts (H)
ts (L)
Selup Time HIGH or LOW
REtoCP
24
24
24
24
ns
th (H)
Ih (L)
Hold Time HIGH or LOW
REloCP
5
5
0
0
ns
Is (H)
Is (L)
Setup Time HIGH or LOW
DO, 01 or liOn to CP
15
15
10
10
ns
th (H)
th (L)
Hold Time HIGH or LOW
DO, 01 or liOn 10 CP
5
5
0
0
ns
Is (H)
ts (L)
Selup Time HIGH or LOW
SEtoCP
15
15
15
15
ns
th (H)
th (L)
Hold Time HIGH or LOW
SEtoCP
0
0
0
0
ns
ts(H)
ts (L)
Setup Time HIGH or LOW
SPloCP
24
24
24
24
ns
ts(H)
Is (L)
Setup Time HIGH or LOW
StoCP
15
15
15
15
ns
th (H)
Ih (L)
Hold Time HIGH or LOW
SorSPtoCP
0
0
0
0
ns
Iw(H)
CP Pulse Widlh HIGH
15
15
ns
Iw(L)
MR Pulse Width LOW
15
15
ns
I,ee
Recovery Time
MRtoCP
15
15
ns
125
2-339
0
Electrical Characteristics
Over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
= Min,ll = -18 mA
= Max
VI
Input Clamp Voltage
Vee
VOH
High Level Output
Voltage
Vee = Min, 10H
VIL = Max
Low Level Output
Voltage
Vee = Min,lOL
VIH = Min
VOL
= Max
Input Current @ Max
Input Voltage
High Level Input Current
IIH
= 4 mA, Vee = Min
Vee = Max, VI = 10V
Low Level Input Current
IlL
Short Circuit
Output Current
los
Vee
2.5
DM74
2.7
0.4
DM74
0.35
0.5
DM74
0.25
0.4
S Input
0.2
SE Input
0.3
Sinput
40
SE Input
60
S Input
-0.8
SElnput
-1.2
I I/On
I On
54LS
-30
-130
-20
-100
-20
-100
= Max
Vee
Vee = VeeH
VOZH = 2.7V
V
mA
p.A
-0.4
DM74
Supply Current
V
20
Max
(Note 2)
TRI·STATE Output Off
Current HIGH
-1.5
0.1
= 0.4V
Max, VI = 0.4V
Max, VI = 0.4V
lee
Units
V
Max, VI
10ZH
Max
3.4
= Max, VI = 2.7V
=
Vee =
Vee =
Vee =
Vee
54LS
54LS
10L
II
Typ
(Note 1)
Min
TRI·STATE Output Off
Vee = VeCH
Current LOW
VOZL = O.4V
Nole 1: All typical. are at Vee = 5V, TA = 25'C.
Nole 2: Not more than one output should be shorted at a time. and the duration should not excoed one second.
10ZL
mA
mA
60
mA
40
p.A
-0.4
mA
Switching Characteristics
Vee
= + 5.0V, TA = + 25·C (See Section 1 for waveforms and load configurations)
RL
Symbol
Parameter
= 2kO,CL = 15pF
DM74LS
54LS
Min
Max
Min
Units
Max
f max
Maximum Clock Frequency
tpLH
tpHL
Propagation Delay
CPto I/On"
25
35
25
34
ns
tpLH
tpHL
Propagation Delay
CPtoOO
26
28
26
29
ns
tpHL
Propagation Delay
MRto I/On"
35
34.1
ns
tpHL
Propagation Delay
MR to 00
28
28
ns
tPZH
tPZL
Output Enable Time
OEto I/On"
18
25
21.5
23.9
ns
"CL
35
= 50 pF
2·340
35
MHz
Switching Characteristics
Vee
= + 5.0V, TA = + 25°C (See Section 1 for waveforms and load configurations)
CL
Symbol
Parameter
= 15pF
DM74LS
54LS
Min
Max
Units
Max
Min
tpHZ
tpLZ
Output Disable Time
OE to I/On'
15
20
15
15
ns
tpzH
tpZL
Output Enable Time
S/PtoI/On"
22
30
25.2
25.8
ns
Output Disable Time
SPto lIOn'
23
23
40.2
26.8
ns
tpHZ
tpLZ
'CL = 5pF
"CL = 50 pF
Functional Description
The LS322 contains eight D-type edge triggered flip-flops
and the interstage gating required to perform right shift and
the intrastage gating necessary for hold and synchronous
parallel load operations. A LOW signal on RE enables shifting or parallel loading, while a HIGH signal enables the hold
mode. A HIGH signal on SIP enables shift right, while a
LOW signal disables the TRI-STATE output buffers and enabies parallel loading. In the shift right mode a HIGH signal
on SE enables serial entry from either DO or D1, as determined by the S input. A LOW signal on SE enables shift right
but 07 reloads its contents, thus performing the sign extend
function required for the '384 Twos Complement Multiplier.
A HIGH signal on OE disables the TRI-STATE output buffers, regardless of the other control inputs. In this condition
the shifting and loading operations can still be performed.
Mode Table
Inputs
Mode
Outputs
MR
RE
SIP
SE
S
OE'
CP
1/07
1/06
1/05
1/04
1/03
1/02
1/01
1/00
00
L
L
X
X
X
X
X
X
X
X
L
H
X
X
L
L
L
L
L
L
L
L
Z
Z
Z
Z
Z
Z
Z
Z
L
L
Parallel
Load
H
L
L
X
X
X
--'
17
16
15
14
13
12
11
10
10
Shift
Right
H
H
L
L
H
H
H
H
L
H
L
L
--'
--'
DO
D1
07
07
06
06
05
05
04
04
03
03
02
02
01
01
01
01
Sign
Extend
H
L
H
L
X
L
--'
07
07
06
05
04
03
02
01
01
Clear
Hold
H
H
X
X
X
L
--' NC NC NC NC NC NC NC NC NC
'When the en: input is HIGH. all lIOn terminals are at tha high·lmpedance state; sequential operation or clearing 01 the register is not affected.
Note 1: 17-10 = The level 01 the steady·state Input at the respective 1/0 terminal is loaded Into the fllp.flop while the flip-flop outputs (except 00) are Isolated from
the 1/0 terminal.
Note 2: DO. 01 = The level of the steady-state Inputs to the serial multiplexer input.
Note 3: 07-00 = The level of the respective an flip·flop prior to the last Clock LOW-to-HIGH transition.
NC = No Change Z = High-Impedance Output Stete H = HIGH Voltage Level L = LOW Voltage Lavel
2-341
N~--------------------------------------------~
N
~
Logic Diagram
2-342
~National
~ Semiconductor
54LS323/DM74LS323
8-Bit Universal Shift/Storage Register
with Synchronous Reset and Common I/O Pins
General Description
Features
The 'LS323 is an 8-bit universal shift/storage register with
TRI-STATE® outputs. Its function is similar to the 'LS299
with the exception of Synchronous Reset. Parallel load inputs and flip-flop outputs are multiplexed to minimize pin
count. Separate inputs and outputs are provided for flipflops 00 and 07 to allow easy cascading. Four operation
modes are possible: hold (store), shift left, shift right, and
parallel load. All modes are activated on the LOW-to-HIGH
transition of the Clock.
• Common I/O for reduced pin count
• Four operation modes: shift left, shift right, parallel load
and store
• Separate continuous inputs and outputs from 00 and
07 allow easy cascading
• Fully synchronous reset
• TRI-STATE outputs for bus oriented applications
Connection Diagram
Dual-In-Line Package
50- 1
0[1- 2
0[2- 3
"-..../
I-Vcc
19 1-51
18 1-057
17 I-Q7
1/06- 4
1/041/021/00QO-
20
5
6
7
8
Sii- 9
16 1-1/07
15 1-1/05
14 1-1/03
13 1-1/01
12 I-ep
GNO- 10
111-050
TL/F/9829-1
Order Number 54LS323DMQB, 54LS323FMQB, DM74LS323WM or DM74LS323N
See NS Package Number J20A, M20B, N20A or W20A
Pin Names
Description
CP
Clock Pulse Input (Active Rising Edge)
Serial Data Input for Right Shift
Serial Data Input for Left Shift
SO,SI
Mode Select Inputs
SR
Synchronous Reset Input (Active LOW)
OE1, OE2 TRI-STATE Output Enable Inputs (Active LOW)
1/00-1/07 Parallel Data Inputs or TRI-STATE
Parallel Outputs
Serial Outputs
00,07
DsO
Ds7
2-343
•
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
10V
Operating Free Air Temperature Range
54LS
- 55·C to + 125·C
OM74LS
O·Cto +700C
Storage Temperature Range
-65·C to + 150·C
Recommended Operating Conditions
Symbol
54LS323
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
IOH
High Level Output Current
DM74LS323
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
2
V
V
0.7
0.8
V
-0.4
-0.4
mA
8
mA
70
·C
IOL
Low Level Output Current
TA
Free Air Operating Temperature
ts(H}
ts (L)
Setup Time HIGH or LOW
SO orS1 to CP
24
24
24
24
ns
th(H}
th(L}
Hold Time HIGH or LOW
SOorS1 toCP
5
5
0
0
ns
Is (H)
Is (L)
Setup Time HIGH or LOW
lIOn, OSO, OS7 to CP
15
15
10
10
ns
ih (H)
th(L)
Hold Time HIGH or LOW
lIOn, OSO, OS7 to CP
5
5
0
0
ns
ts (H)
ts (L)
Setup Time HIGH or LOW
SRtoCP
30
20
15
15
ns
th (H)
Hold Time HIGH or LOW
SRtoCP
0
0
0
0
ns
CP Pulse Width HIGH or LOW
15
15
15
15
ns
ih (L)
!w(H)
!w(L}
4
-55
125
2-344
0
Electrical Characteristics
Over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
VI
Input Clamp Voltage
Vee = Min, 11= -IB mA
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
VIL = Max
54LS
2.5
DM74
2.7
Low Level Output
Voltage
Vee = Min, 10L = Max
VIH = Min
54LS
10L = 4 mA, Vee = Min
Input Current @ Max
Input Voltage
Vee = Max, VI = 10V
VOL
II
Typ
(Note 1)
Max
Units
-1.5
V
V
3.4
0.4
DM74
0.35
0.5
DM74
0.25
0.4
Sn Inputs
High Level Input Current
IIH
0.1
mA
0.2
mA
20
/LA
Vee = Max, VI = 2.7V
Sn Inputs
Low Level Input Current
IlL
Vee = Max, VI = 0.4V
Sn Inputs
V
40
/LA
-0.4
mA
-O.B
mA
54LS
-20
-100
DM74
-20
-100
Short Circuit
Output Current
Vee = Max
(Note 2)
lee
Supply Current
Vee = Max
60
mA
10ZH
TRI-STATE Output Off
Current HIGH
Vee = VeeH
VOZH = 2.7V
40
/LA
10ZL
TRI-STATE Output Off
Current LOW
Vee = VeeH
VOZL = 0.4V
-400
/LA
los
Nole
mA
1: All typicals are at Vee = SV. TA = 2S'C.
Not more than one output should be shorted at a time, and the duration should not exceed one seccnd.
Nate 2:
Switching Characteristics
Vee =
+ 5.0V, TA = + 25'C (See Section 1 for waveforms and load configurations)
54LS323
Symbol
CL = 15pF
Parameter
Min
fmax
Maximum Input Frequency
tpLH
tpHL
Propagation Delay
CPtoQOorQ7
tpLH
tpHL
DM74LS323
RL = 2kn,CL = 15pF
Max
35
Min
Units
Max
35
MHz
26
2B
23
25
ns
Propagation Delay
CPtoi/On
25
35
25
29
ns
tpZH
tPZL
Output Enable Time
CL = 50pF
lB
25
lB
23
ns
tpHZ
tpLZ
Output Disable Time
CL = 5pF
15
20
15
15
ns
2-345
•
~
('II
!I
r---------------------------------------------------------------------------------,
Functional Description
The 'LS323 contains eight edge-triggered Ootype flip-flops
and the interstage logic necessary to perform synchronous
reset, shift left, shift right, parallel load and hold operations.
The type of operation is determined by SO and 51 as shown
in the Mode Select Table. All flip-flop outputs are brought
out through TRI-STATE buffers to separate I/O pins that
also serve as data inputs in the parallel load mode. QO and
Q7 are also brought out on other pins for expansion in serial
shifting of longer words.
A LOW signal on SR overrides the Select inputs and allows
the flip-flops to be reset by the next rising edge of CPo All
other state changes are also initiated by the LOW-to-HIGH
CP transition. Inputs can change when the clock is in either
state provided only that the recommended setup and hold
times, relative to the rising edge of CP, are observed.
A HIGH signal on either OEI or OE2 disables the TRISTATE buffers and puts the 1/0 pins in the high impedance
state. In this condition the shift, load, hold and reset operations can still occur. The TRI-STATE buffers are also disabled by HIGH signals on both SO and 51 in preparation for
a parallel load operation.
Mode Select Table
Inputs
Response
SR S1 SO CP
..r
..r
..r
..r
Synchronous Reset; QO-Q7 = LOW
L X X
H H H
Parallel Load; lIOn - Qn
H L H
Shift Right; 050 - QO, QO - Ql, etc.
H H L
Shift Left; OS7 - Q7, Q7 - Q6, etc.
HHHXHold
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Logic Symbol
18
I
I-SO
050
057
19-51
1 2 - CP
071--17
2~OE
3 -otl...,..I
5R 00 1/00 1/01 1/02 1/03 1/04 1/05 1/06 1/07
T ! ! 1~ ! 1~ ! 1~ ! 1~
Vee = Pin 20 TlIF/9829-2
GND = Pin 10
2-346
Logic Diagram
o
(II
l:ll
2-347
a..
U
8
I~ I~
~
"II'
r-------------------------------------------------------------------------,
~ ~National
~ Semiconductor
54LS347/DM74LS347
BCD to 7-Segment Decoder/Driver
General Description
The 'LS347 is the same as the 'LS47 except that the Output
OFF Voltage, VOH, is specified as 7.0V rather than 15V, with
the same IOH limit of 250 I'A For all other information
please refer to the 'LS47 data sheet.
Connection Diagram
Logic Symbol
Dual-In-Llne Package
'-../
16
r-Vcc
Al- 2
15
H
LT- 3
14
~g
AD- 1
BI/RBD- 4
13
~ii
R8i-s
12
Hi
A2- 6
11
-c
A3- 7
10
-d
GND- 8
Iii i b b
AD
Al
A2
A3
LT
RBI
BI/
abcdefgRBO
TUF/l0184-2
9 -i
Vee = Pin 16
GND = PinS
TL/F/l0184-1
Order Number 54LS347DMQB, 54LS347FMQB,
DM74LS347M or DM74LS347N
See NS Package Number J16A, M16A, N16E or W16A
Pin Names
AO-A3
RBI
LT
§i/RBO
a-g
Description
BCD Inputs
Ripple Blanking Input (Active LOW)
Lamp Test Input (Active LOW)
Blanking Input (Active LOW) or
Ripple Blanking Output (Active LOW)
·Segment Outputs (Active LOW)
'OC--Open Collector
2-348
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
54LS
DM74LS
- 55'C to + 125'C
O'Cto +70'C
Storage Temperature Range
- 65'C to + 150'C
Recommended Operating Conditions
Symbol
54LS347
Parameter
DM74LS347
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
V
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
0.7
0.8
IOH
High Level Output Voltage
-50
-50
/LA
IOL
Low Level Output Current
12
24
rnA
TA
Free Air Operating Temperature
70
'C
2
2
-55
125
V
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Condlt.lons
Typ
(Note 1)
Min
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vee = Min, 11= -18 rnA
VOH
High Level Output
Voltage
Vee = Min, VOH = Max,
VIL = Max
Low Level Output
Voltage
Vee = Min, IOL = Max,
VIH = Min
54LS
0.4
DM74
0.5
IOL = 4 rnA, Vee = Min
DM74
0.4
VOL
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 10V
IIH
High Level Input Current
Vee = Max, VI = 2.7V
IlL
Low Level Input Current
Vee = Max, VI = O.4V
los
Short Circuit
Output Current
Vee = Max
(Note 2)
54LS
2.5
DM74
2.7
Supply Current
lee
V
0.1
mA
20
/LA
-0.03
-0.4
mA
mA
-0.09
-1.2
54LS
-0.3
-2.0
DM74
-0.3
-2.0
BIIRBO Input
IOFF
V
rnA
Vee = Max
13
mA
Segment Outputs, Va = 7V
250
/LA
Switching Characteristics
at Vee = 5V and TA = 25'C (See Section 1 for Test Waveforms and Output Loading)
Symbol
CL = 15pF
Parameter
Min
tpLH
tpHL
Propagation Delay
Antoii-g
Propagation Delay
tpLH
RBI toii-g
tpHL
Note 1: All typical. are at Vee = SV, TA = 2S'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
2-349
Units
Max
100
100
ns
ns
100
100
ns
ns
~
an
!i
r----------------------------------------------------------------------------,
~ National
~ Semiconductor
54LS352/DM74LS352 Dual4-Line to
1-Line Data Selectors/Multiplexers
General Description
• Inverting version of DM54174LS153
• Permits multiplexing from N lines to 1 line
• Performs parallel-ta-serial conversion
• Strobe (enable) line provided for cascading (N lines to
n lines)
• High fan-out, low-impedance, totem-pole outputs
• Typical average propagation delay times
From data 15 ns
From strobe 19 ns
From select 22 ns
• Typical power dissipation 31 mW
Connection Diagram
Function Table
Each of these data selectors/multiplexers contains inverters and drivers to supply fully complementary, on-chip, binary decoding data selection to the AND-OR-invert gates.
Separate strobe inputs are provided for each of the two
four-line sections.
Features
Select
Inputs
Dual-In-Llne Package
vcc
STROBE
A
G2
SELjCT
15
116
14
1
DATA INPUTS
TT
13
2t
2C1
12
10
111
I I
I
B
ii
A
1
~
1 I
12 ,1: ,1: J:
B
STROBE
G1
SELECT
ii
J:
A
Ye
I
I
A
~
B
OUTPUT
I
A
I
Data Inputs
Strobe
Output
B
A
CO
C1
C2
C3
G
Y
X
X
X
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
H
X
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
L
H
H
L
L
L
L
L
L
L
L
H
H
L
H
L
H
L
H
L
X
X
X
X
X
X
L
H
X
X
X
X
Select inputs A and B are common 10 bolh sections.
H
, OUCUT IN:
Y1
DATA INPUTS
TL/F/6425-1
Order Number 54LS352DMQB, 54LS352FMQB,
DM74LS352M or DM74LS352N
See NS Package Number J16A, M16A, N16E or W16A
2-350
= High Level. L = Low Level, X
= Don'l Care
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Note: The ''Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
54LS
-55· C to + 125·C
DM74LS
O·Cto +70·C
Storage Temperature Range
-65· Cto +150· C
Recommended Operating Conditions
Symbol
54LS352
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
Vil
Low Level Input Voltage
DM74LS352
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
2
V
V
0.7
0.8
V
10H
High Level Output Current
-0.4
-0.4
mA
10l
Low Level Output Current
12
8
rnA
TA
Free Air Operating Temperature
70
·C
Electrical Characteristics
Symbol
-55
125
0
over recommended operating free air temperature range (unless otherwise noted)
Parameter
Conditions
Min
Typ
(Note 1)
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vee = Min, 11= -18 rnA
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
Vil = Max, VIH = Min
54LS
2.5
DM74
2.7
Low Level Output
Voltage
Vcc = Min, 10l = Max
Vil = MaX, VIH = Min
54LS
DM74
0.35
0.5
10l = 4mA
Vee = Min
DM74
0.25
0.4
VOL
V
3.4
0.4
V
Input Current @ Max
Input Voltage
Vee = Max, VI = 10V
54LS
Vee = Max, VI = 7V
DM74
IIH
High Level Input Current
Vee = Max, VI = 2.7V
20
!JoA
III
Low Level Input Current
Vee = Max, VI = O.4V
-0.4
rnA
los
Short Circuit
Output Current
Vee = Max
(Note 2)
II
0.1
54LS
-20
-100
DM74
-20
-100
Supply Current
Vee = Max (Note 3)
Icc
Note 1: All typlcals are at Vcc = 5V, TA = 25'e.
Nole 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Nole 3: Icc Is measured wtth all outputs open and all other Inputs at ground.
2-351
6.2
10
rnA
rnA
rnA
Switching Characteristics
at Vee
From
(Input)
To
(Output)
Parameter
Symbol
= 5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
54LS
CL
Min
DM74LS
CL = 50pF
RL = 2kO
= 15pF
Min
Max
Units
Max
tpLH
Propagation Delay Time
Low to High Level Output
DatatoY
12
24
ns
tpHL
Propagation Delay Time
High to Low Level Output
DatatoY
12
35
ns
tpLH
Propagation Delay Time
Low to High Level Output
Select to Y
22
33
ns
tpHL
Propagation Delay Time
High to Low Level Output
SeleottoY
38
47
ns
tpLH
Propagation Delay Time
Low to High Level Output
Strobe to Y
15
29
ns
tpHL
Propagation Delay Time
High to Low Level Output
Strobe to Y
20
41
ns
Logic Diagram
STROBE Gl (1)
100 (6)
lCl (5)
DATA 1
~~.
(7) OUTPUT
Yl
-I
lC2(4)
lC3 (3)
~~
'~(' ~
A(~
(10)
200
~~
2Cl(11)
DATA 2
2C2 (12)
Y2
2C3 (13)
!~
STROBE G2
TLIF16425-2
2-352
'?'A National
~ Semiconductor
54LS353/DM74LS353
Dual4-lnput Multiplexer with TRI-STATE® Outputs
General Description
Features
The '353 is a dual 4-input multiplexer with TRI-STATE outputs. It can select two bits of data from four sources using
common select inputs. The outputs may be individually
switched to a high impedance state with a HIGH on the
respective Output (OE) inputs, allowing the outputs to interface directly with bus oriented systems. It is fabricated with
the Schottky barrier diode process for high speed and is
completely compatible with all National TTL families.
• Inverted version of 'LS253
• Schottky process for high speed
• Multifunction capability
Connection Diagram
Logic Symbol
Dual·ln·Llne Package
..........,
OE.-
1
SI- 2
13. - 3
12. - 4
1, . - 5
10. - 6
7
GND- 8
z.-
16 -Vee
15 -DEb
14 ,....SO
biii i 'f'l' 'i 'i b
OE" lOa 11 a 12a 13a lOb 11 b 12b 13b OEb
14- SO
13,...13b
12""12b
11""I,b
2 - SI
Za
Zb
10 !-IOb
9 !-Zb
TL/F/10185-2
vee = PinlS
TL/F/10185-1
GND
Order Number 54LS353DMQB, 54LS353FMQB,
DM74LS353M or DM74LS353N
See NS Package Number J16A, M16A, N16E or W16A
Pin Names
IOa-13a
IOb-13b
SO,S1
OEa
OEb
Za,Zb
= PinS
Description
Side A Data Inputs
Side B Data Inputs
Common Select Inputs
Side A Output Enable Input (Active Low)
Side B Output Enable Input (Active Low)
TRI·STATE Outputs (Inverted)
2·353
•
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
54LS
- 55'C to + 125'C
DM74LS
O'Cto +70'C
Storage Temperature Range
- 65'C to + 150'C
Recommended Operating Conditions
Symbol
54LS353
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
Vil
Low Level Input Voltage
10H
10L
TA
Free Air Operating Temperature
DM74LS353
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
2
V
V
0.7
0.8
V
High Level Output Current
-1.0
-2.6
mA
Low Level Output Current
12
24
mA
70
'C
-55
125
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
= Min, II = -18 mA
= Max,
VI
Input Clamp Voltage
VCC
VOH
High Level Output
Voltage
Vcc = Min, 10H
VIL = Max
Low Level Output
Voltage
Vee = Min, 10L
VIH = Min
VOL
= Max,
= 4 mA, Vcc = Min
Vcc = Max, VI = 10V
10L
Min
54LS
2.5
DM74
2.7
Typ
(Note 1)
Max
Units
-1.5
V
V
54LS
0.4
DM74
0.5
DM74
0.4
V
II
Input Current @ Max
Input Voltage
IIH
High Level Input Current
Vcc
20
p.A
IlL
Low Level Input Current
Vcc
-0.4
mA
los
Short Circuit
Output Current
(Note 2)
= Max, VI = 2.7V
= Max, VI = 0.4V
Vcc = Max
0.1
54LS
-30
-130
DM74
-30
-130
mA
rnA
ICCl
Supply Current
Outputs HIGH
Vcc = Max,
In, Sn, OEn = GND
12
rnA
Iccz
Supply Current
Outputs OFF
Vee = Max,OEn
In,Sn = GND
14
rnA
10ZH
TRI-STATE Output OFF
Current HIGH
Vcc = VCCH
VOZH = 2.7V
20
p.A
10Zl
TRI-STATE Output OFF
Current LOW
Vee = VCCH
VOZL = 0.4V
-20
p.A
= 4.5V
Nole 1: All typicals are at Vee = 5V, TA = 25'C.
Nole 2; Not more than one output should be shoned at a time, and the duration should not exceed one second.
2-354
Switching Characteristics Vee = + 5.0V, TA = + 25°C (See Section 1 for test waveforms and output loads)
RL = 2kO,CL = 50pF
Symbol
Parameter
Units
Max
Min
tpLH
tpHL
Propagation Delay
SntoZn
24
32
ns
tpLH
tpHL
Propagation Delay
In tOZn
15
15
ns
tpZH
tPZL
Output Enable Time
OE to Zn
18
18
ns
tpHZ
tpLZ
Output Disable Time
OEtoZn
18
18
ns
Functional Description
The 'LS353 contains two identical4-input multiplexers with
TRI-STATE outputs. They select two bits from four sources
selected by common Select inputs (SO, 51). The 4-input
multiplexers have individual Output Enable (OEa>, OEb) inputs which when HIGH, force the outputs to a high impedance (high Z) state. The logic equations for the outputs are
shown below:
If the outputs of TRI-STATE devices are tied together, all
but one device must be in the high impedance state to avoid
high currents that would exceed the maximum ratings. Designers should ensure that Output Enable signals to TRISTATE devices whose outputs are tied together are designed so that there is no overlap.
= OEa-(IOa-Sl-S0 + 11a-Sl-S0 + 12a-Sl-S0 + 13a-Sl-S0)
Zb = OEb • (lOb - 51 - SO + 11 b - 51 - SO + 12b - 51 - SO + 13b - 51 - SO)
Za
Truth Table
Select
Inputs
Output
Enable
Data Inputs
Output
SO
S1
10
11
12
13
OE
Z
X
X
X
X
X
X
L
L
H
L
L
L
L
H
X
X
X
L
X
X
X
X
X
X
H
L
L
L
(Z)
H
L
H
H
L
L
H
H
L
H
H
H
H
X
X
X
X
X
H
X
X
X
X
X
L
H
X
X
X
X
X
L
H
L
L
L
L
L
L
H
L
H
L
Address inputs SO and 51 are common to both sections.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
(Z) = High Impedance
2-355
•
fa
!}
Logic Diagram
OEb
13b
12b
lIb
lab
so
SI
138
128
118
TL/F/10185-3
2-356
~National
~ Semiconductor
54LS365A/DM54LS365A/DM74LS365A
Hex TRI-STATE® Buffers
General Description
This device contains six independent gates each of which
performs a non-inverting buffer function. The outputs have
the TRI-STATE feature. When enabled. the outputs exhibit
the low impedance characteristics of a standard LS output
with additional drive capability to permit the driving of bus
lines without external resistors. When disabled. both the
output transistors are turned off presenting a high-impedance state to the bus line. Thus the output will act neither as
a significant load nor as a driver. To minimize the possibility
that two outputs will attempt to take a common bus to opposite logic levels. the disable time is shorter than the enable
time of the outputs.
Features
• Alternate Military/Aerospace device (54LS365A) is
available. Contact a National Semiconductor Sales Office/Distributor for specifications.
Connection Diagram
Dual·ln·Line Package
V6
A6
VI
Al
12
13
14
iiI
A5
V2
A2
V5
A4
V4
10
11
V3
A3
GND
TLIFI6427-1
Order Number 54LS365ADMQB, 54LS365AFMQB, 54LS365ALMQB,
DM54LS365AJ, DM54LS365AW, DM74LS265AM or DM74LS365AN
See NS Package Number E20A, J16A, M16A, N16E or W16A
Function Table
Y=A
Input
Output
G2
A
Y
H
X
X
H
L
L
X
X
Hi-Z
Hi-Z
H
L
G1
L
L
H
L
= High Logic Level
= Low Logic Level
X = Either Low or High Logic Level
H
L
HI-Z = TRI-STATE (Outputs are disabled)
2-357
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
DM54LS and 54LS
-55'Cto + 125'C
DM74LS
O'Cto +70'C
Storage Temperature Range
-65'Cto + 150'C
Note: The "Absolute Maximum Ratings" ara those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guarant88d at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Recommended Operating Conditions
Symbol
DM74LS365A
DM54LS365A
Parameter
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
0.7
0.8
V
10H
High Level Output Current
-1
-2.6
mA
24
mA
70
'C
2
2
10L
Low Level Output Current
TA
Free Air Operating Temperature
V
12
-55
125
V
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 1)
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vee = Min, 11= -18 mA
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
VIL = Max, VIH = Min
VOL
Low Level Output
Voltage
Vee = Min, 10l = Max
Vil = Max, VIH = Min
DM54
0.25
0.4
DM74
0.35
0.5
= 12 mA, Vee = Min
Vee = Max, VI = 7V
DM74
0.25
0.4
10l
II
Input Current @ Max
Input Voltage
IIH
High Level Input Current
Vee = Max, VI
III
low Level Input
Current
Vee = Max, VI
(Note 4)
= 2.7V
= 0.5V
10Zl
los
Off-State Output Current
with High Level Output
Voltage Applied
3.4
A Input
V
mA
20
/Jo A
-20
/Jo A
A Input
-0.4
= Max, VI = 0.4V
Vee = Max, Vo = 2.4V
VIH = Min, Vil = Max
G Input
-0.4
Off-State Output Current
with Low Level Output
Voltage Applied
Vee = Max, Vo = 0.4V
VIH = Min, Vil = Max
Short Circuit
Output Current
Vee = Max
(Note 2)
mA
20
/JoA
-20
IJoA
DM54
-20
-100
DM74
-20
-100
Supply Current
Vee = Max (Note 3)
Icc
Note 1: Aillypicals are at Vcc = SV. TA = 2S'C.
Note 2: Not more than one output should be shorted at a time. and the duration should not exceed one second.
Note 3: Icc is measured with the DATA Inputs grounded and the OUTPUT CONTROLS at 4.SV.
Note 4: Both G inputs are at 2V.
Note 5: Both G Inputs at O.4V.
2-358
V
0.1
Vee = Max, VI = 0.4V
(Note 5)
Vee
10ZH
2.4
14
24
mA
mA
Switching Characteristics at Vee = 5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
RL
Symbol
Parameter
CL
Min
=
50pF
Max
= 6670
CL
Min
=
150pF
Units
Max
tpLH
Propagation Delay Time Low
to High Level Output
16
25
ns
tpHL
Propagation Delay Time High
to Low Level Output
16
25
ns
tPZH
Output Enable Time to
High Level Output
30
40
ns
tPZL
Output Enable Time to
Low Level Output
30
40
ns
tpHZ
Output Disable Time from
High Level Output (Note 6)
20
ns
tpLZ
Output Disable Time from
Low Level Output (Note 6)
20
ns
Note 6: CL
= 5 pF.
FII
2-359
'?A National
~ semiconductor
54LS366A/DM74LS366A
Hex TRI-STATE® Inverting Buffers
General Description
This device contains six independent gates each of which
performs an Inverting buffer function. The outputs have the
TRI-STATE feature. When enabled, the outputs exhibit the
low impedance characteristics of a standard LS output with
additional drive capability to permit the driving of bus lines
without external reSistors. When disabled, both the output
transistors are turned off presenting a high-impedance state
to the bus line. Thus the output will act neither as a significant load nor as a driver. To minimize the possibility that two
outputs will attempt to take a common bus to opposite logic
levels, the disable time is shorter than the enable time of the
outputs.
Connection Diagram
Dual-ln·Llne Package
vee
02
AS
01
A1
Y1
YS
A5
Y5
A4
Y2
A3
Y3
GND
TLlF/642B-l
Order Number 54LS366ADMOB, 54LS366AFMOB,
54LS366ALMOB, DM74LS366AM or DM74LS366AN
See NS Package Number E20A, J16A, M16A, N16E or W16A
Function Table
Y=A
Inputs
Output
G1
G2
A
Y
H
X
L
L
X
H
L
L
X
X
L
H
Hi-Z
Hi-Z
H
L
H=
L=
X=
HI-Z
High logic Level
Low Logic Level
Either Low or High Logic Level
= TRI-9TATE (Outputs are disabled)
2-360
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and speclflcatlons_
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
DM54LS
-55'Cto +125'C
DM74LS
O'Cto +70'C
Storage Temperature Range
-65'Cto +150'C
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Recommended Operating Conditions
Symbol
54LS366A
Parameter
Vee
Supply Voltage
DM74LS366A
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
VIH
High Level Input Voltage
2
2
VIL
Low Level Input Voltage
0.7
0.8
V
V
10H
High Level Output Current
-1
-2.6
mA
10L
Low Level Output Current
12
24
mA
TA
Free Air Operating Temperature
70
'C
-55
125
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
= Min,ll =
Min
Typ
(Note 1)
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vee
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
VIL = Max, VIH = Min
VOL
Low Level Output
Voltage
Vee = Min, 10L = Max
VIL = Max, VIH = Min
54LS
0.25
0.4
DM74
0.35
0.5
10L = 12 mA, Vee = Min
DM74
0.25
0.4
Vee = Max, VI = 7V
DM74
Vee = Max, VI = 10.0V
54LS
II
Input Current @ Max
Input Voltage
= Max, VI =
-18 mA
2.4
IIH
High Level Input Current
Vee
IlL
Low Level Input
Current
Vee = Max, VI = 0.5V
(Note 4)
A Input
Vee = Max, VI = 0.4V
(NoteS)
A Input
Vee = Max, VI = 0.4V
G Input
10ZH
10ZL
los
3.4
2.7V
V
V
0.1
mA
20
/LA
-20
/LA
-0.4
mA
-0.4
Off-State Output Current
with High Level Output
Voltage Applied
Vee = Max, Vo = 2.4V
VIH = Min, VIL = Max
20
!LA
Off-State Output Current
with Low Level Output
Voltage Applied
Vee = Max, Vo = O.4V
VIH = Min, VIL = Max
-20
/LA
Short Circuit
Output Current
Vee = Max
(Note 2)
54LS
-30
-130
DM74
-20
-100
Supply Current
Vec = Max (Note 3)
Icc
Note 1: All typical. are at Vee = 5V, TA = 25'C.
Note 2: Not more than one output should be shorted at a time, and the duration shoUld not exceed one second.
Note 3: Icc is measured with the DATA inputs grounded and the OUTPUT CONTROLS at 4.5V.
Note 4: Both G Inputs are at 2V.
Note 5: Both G inputs at O.4V.
2-361
12
21
mA
mA
til
Switching Characteristics at Vee = 5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
DM74LS
54LS
Symbol
Parameter
CL
Min
=
CL = 150pF
RL = 6670
50pF
Max
Min
Units
Max
tpLH
Propagation Delay Time Low
to High Level Output
12
25
ns
tpHL
Propagation Delay Time High
to Low Level Output
22
25
ns
tPZH
Output Enable Time to
High Level Output
24
35
ns
tpZL
Output Enable Time to
Low Level Output
30
40
ns
tpHZ
Output Disable Time from
High Level Output (Note 6)
25
ns
tpLZ
Output Disable TIme from
Low Level Output (Note 6)
20
ns
Note 6: CL
= 5 pF.
2·362
~National
~ Semiconductor
54LS367A/DM54LS367 A/DM7 4LS367A
Hex TRI-STATE® Buffers
General Description
This device contains six independent gates each of which
performs a non-inverting buffer function. The outputs have
the TRI-STATE feature. When enabled. the outputs exhibit
the low impedance characteristics of a standard LS output
with additional drive capability to permit the driving of bus
lines without external resistors. When disabled. both the
output transistors are turned off presenting a high-impedance slate to the bus line. Thus the output will act neither as
a significant load nor as a driver. To minimize the possibility
that two outputs will attempt to lake a common bus to opposite logic levels. the disable time is shorter than the enable
time of the outputs.
Features
• Alternate military/aerospace device (54LS367A) is
available. Contact a National Semiconductor sales office/ distributor for specifications.
Connection Diagram
Dual-In-Llne Package
vee
02
01
A1
A6
2
Y6
3
Y1
AS
Y2
A4
Y4
6
7
8
A3
Y3
GND
S
4
A2
YS
TUF/6429-1
Order Number 54LS367ADMQB, 54LS367AFMQB, 54LS367ALMQB, DM54LS367AJ,
DM54LS367AW, DM74LS367AM or DM74LS367AN
See NS Package Number E20A, J16A, M16A, N16E or W16A
Function Table
Y=A
Inputs
Output
A
G
Y
L
H
L
L
H
L
H
Hi-Z
X
= High Logic level
l = low legic level
X = Either low or High logic level
H
Hi-Z = TRI-STATE (Outputs are disabled)
2-363
PI
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Operating Free Air Temperature Range
DM54LS
- 55·C to + 125·C
DM74LS
OOCto +700C
Storage Temperature Range
-65·C to + 150·C
Recommended Operating Conditions
Symbol
DM64LS367A
Parameter
DM74LS367A
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
0.7
0.8
V
2
2
V
10H
High Level Output Current
-1
-2.6
mA
10L
Low Level Output Current
12
24
mA
TA
Free Air Operating Temperature
70
·c
-55
125
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Min
Conditions
=
=
Typ
(Note 1)
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vee
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
VIL = Max, VIH = Min
VOL
Low Level Output
Voltage
Vee = Min, 10L = Max
VIL = Max, VIH = Min
DM54
0.25
0.4
DM74
0.35
0.5
= 12 mA, Vee = Min
Vee = Max, VI = 7V
DM74
0.25
0.4
Min, II
-18 mA
10L
2.4
II
Input Current @ Max
Input Voltage
IIH
High Level Input
Current
Vee
Max, VI
=
2.7V
IlL
Low Level Input
Current
Vee = Max, VI
(Note 4)
=
0.5V
A Input
Vee = Max, VI
(Note 5)
=
O.4V
A Input
=
= Max, VI = O.4V
Vee = Max, Vo = 2.4V
VIH = Min, VIL = Max
Vee
10ZH
10ZL
los
lee
Off-State Output Current
with High Level Output
Voltage Applied
Off-State Output Current
with Low Level Output
Voltage Applied
Vee = Max, Vo = 0.4V
VIH = Min, VIL = Max
Short Circuit
Output Current
Vee = Max
(Note 2)
Supply Current
Vee
=
mA
20
/LA
-20
/LA
mA
-0.4
G Input
20
/LA
-20
/LA
DM54
-20
-100
DM74
-20
-100
Max (Note 3)
Note 3: Icc is measured with the DATA inputs grounded and the OUTPUT CONTROLS at 4.5V.
Note 4: Both G Inputs are at 2V.
Note 5: Both G inputs at O.4V.
V
0.1
-0.4
Note 1: All typlcals are at Vee = 5V. TA = 25'e.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one seoond.
2-364
V
3.4
14
24
mA
mA
Switching Characteristics at Vee =
5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
RL= 66m
Symbol
Parameter
CL = 150pF
CL = 50pF
Min
Max
Min
Units
Max
tpLH
Propagation Delay Time Low
to High Level Output
16
25
ns
tpHL
Propagation Delay Time High
to Low Level Output
16
25
ns
tpZH
Output Enable Time to
High Level Output
30
40
ns
tPZL
Output Enable Time to
Low Level Output
30
40
ns
tpHZ
Output Disable Time from
High Level Output (Note 6)
20
ns
tpLZ
Output Disable Time from
Low Level Output (Note 6)
20
ns
Nole 6: CL = 5 pF.
2·365
~National
~ Semiconductor
54LS368A/DM54LS368A/DM74LS368A
Hex TRI-STATE® Inverting Buffers
General Description
This device contains six independent gates each of which
performs an inverting buffer function. The outputs have the
TRI-STATE feature. When enabled, the outputs exhibit the
low impedance characteristics of a standard LS output with
additional drive capability to permit the driving of bus lines
without external resistors. When disabled, both the output
transistors are turned off presenting a high-impedance state
to the bus line. Thus the output will act neither as a significant load nor as a driver. To minimize the possibility that two
outputs will attempt to take a common bus to opposite logic
levels, the disable time is shorter than the enable time of the
outputs.
Features
• Alternate Military/Aerospace device (54LS368) is available. Contact a National Semiconductor Sales Office/
Distributor for specifications.
Connection Diagram
Dual·ln·Llne Package
vee
G2
A6
Y6
YS
A4
Y4
9
1
G1
2
A1
3
Y1
4
A2
S
Y2
6
A3
7
Y3
8
GND
TUF/6430-1
Order Number 54LS368ADMQB, 54LS368AFMQB, 54LS368ALMQB,
DM54LS368AJ, DM54LS368AW, DM74LS368AM or DM74LS368AN
See NS Package Number E20A, J16A, M16A, N16E or W16A
Function Table
Y=A
Inputs
Output
A
G
Y
L
H
X
L
L
H
H
L
Hi-Z
= High Logic Level
= Low Logic Level
X = Either Low or High Logic Level
H
L
HI-Z = TAl-STATE (Outputs are disabled)
2-366
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operatiOn.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
DM54LS and 54LS
- 55'C to + 125'C
DM74LS
O'Cto +70'C
Storage Temperature Range
- 65'C to + 150'C
Recommended Operating Conditions
Symbol
DM54LS368A
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
DM74LS368A
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
2
V
V
VIL
Low Level Input Voltage
0.7
0.8
V
10H
High Level Output Current
-1
-2.6
mA
24
mA
70
'C
10L
Low Level Output Current
TA
Free Air Operating Temperature
12
-55
125
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
=
=
VI
Input Clamp Voltage
Vee
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
VIL = Max, VIH = Min
VOL
Low Level Output
Voltage
Vee = Min, 10L = Max
VIL = Max, VIH = Min
Min, II
Min
-18 mA
= 12 mA, Vee = Min
Vee = Max, VI = 7V
10l
2.4
0.5
0.25
0.4
=
2.7V
IlL
Low Level Input
Current
Vee = Max, VI
(Note 4)
=
0.5V
A Input
Vee = Max, VI
(Note 5)
=
O.4V
A Input
los
Off-State Output Current
with Low Level Output
Voltage Applied
Vee = Max, Vo = OAV
VIH = Min, Vil = Max
Short Circuit
Output Current
Vee = Max
(Note 2)
V
0.1
mA
20
/LA
-20
p.A
-0.4
mA
-0.4
G Input
20
/LA
-20
/LA
DM54
-20
-100
DM74
-20
-100
Supply Current
Vee = Max (Note 3)
Icc
Note 1: All typlcals are at Vee = SV, TA = 2S'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: lee is measured with the DATA inputs grounded and the OUTPUT CONTROLS at4.SV.
Note 4: Both G inputs are at2V.
Note 5: Both G Inputs at O.4V.
2-367
V
DM74
Max, VI
10Zl
3.4
0.4
Vee
Off-State Output Current
with High Level Output
Voltage Applied
V
0.35
High Level Input
Current
10ZH
-1.5
0.25
IIH
= Max, VI = OAV
Vee = Max, Vo = 2.4V
VIH = Min, Vil = Max
Units
DM54
Input Current @ Max
Input Voltage
Vee
Max
DM74
II
=
Typ
(Note 1)
12
21
mA
mA
•
Switching Characteristics at Vee =
5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
RL = 6670
Symbol
Parameter
CL=50pF
Min
CL = 150pF
Max
Min
Units
Max
tpLH
Propagation Delay Time Low
to High Level Output
15
25
ns
tpHL
Propagation Delay TIme High
to Low Level Output
18
25
ns
tPZH
Output Enable TIme to
High Level Output
30
35
ns
tPZL
Output Enable Time to
Low Level Output
30
40
ns
tpHZ
Output Disable Time from
High Level Output (Note 6)
20
ns
tpLZ
Output Disable Time from
Low Level Output (Note 6)
20
ns
Note 6: CL = 5 pF.
2·368
•
~National
~ Semiconductor
DM54LS373/DM74LS373,
54LS37 4/DM54LS37 4/DM7 4LS37 4
TRI-STATE® Octal D-Type Transparent
Latches and Edge-Triggered Flip-Flops
General Description
Features
These a-bit registers feature totem-pole TRI-STATE outputs
designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high-logic level drive provide these registers with
the capability of being connected directly to and driving the
bus lines in a bus-organized system without need for interface or pull-up components. They are particularly attractive
for implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers.
(Continued)
II Choice of a latches or a D-type flip-flops in a single
package
• TRI-STATE bus-driving outputs
iii Full parallel-access for loading
• Buffered control inputs
• P-N-P inputs reduce D-C loading on data lines
• Alternate military/aerospace device (54LS374) is available. Contact a National Semiconductor sales office/
distributor for specifications.
Connection Diagrams
Dual-In-Line Packages
'LS373
vee
80
80
70
70
60
ENABLE
60
50
50
G
Order Number
DM54LS373J,
DM54LS373W,
DM74LS373N or
DM74LS373WM
See NS Package Number
J20A, M20B, N20A or
W20A
OUTPUT
CONTROL
10
10
20
20
30
30
4D
40
GNO
TL/F/6431-1
'LS374
vee
80
80
70
70
60
60
50
50
CLOCK
Order Number
54LS374DMQB,
54LS374FMQB,
54LS374LMQB,
DM54LS374J,
DM54LS374W,
DM74LS374WM or
DM74LS374N
See NS Package Number
E20A,J20A,M20B,N20A
orW20A
OUTPUT
CONTROL
10
10
20
20
30
30
.10
4Q
GNO
TL/F/6431-2
2-369
General Description
(Continued)
The eight latches of the DM54174LS373 are transparent 0type latches meaning that while the enable (G) is high the
outputs will follow the data (D) inputs. When the enable is
taken low the output will be latched at the level of the data
that was set up.
A buffered output control input can be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high-impedance state. In the high-impedance
state the outputs neither load nor drive the bus lines significantly.
The output control does not affect the internal operation of
the latches or flip-flops. That is, the old data can be retained
or new data can be entered even while the outputs are off.
a
The eight flip-flops of the DM54174LS374 are edge-triggered D-type flip flops. On the positive transition of the
clock, the a outputs will be set to the logic states that were
set up at the 0 inputs.
Function Tables
DM54174LS374
DM54174LS373
Output
Control
Enable
G
L
L
L
H
H
H
L
X
D
Output
H
L
H
L
X
X
00
Z
Output
Control
Clock
D
Output
t
t
H
L
H
L
L
X
X
00
Z
L
L
L
H
X
H = High Level (Steady State), L = Low Level (Steady State), X = Don't Care
t = Transition from low-Io-high lavel, Z = High Impedance State
00 = The level of the output before steady·state input conditions were established.
Logic Diagrams
DM54174LS373
Transparent Latches
DM54174LS374
Posltlve-Edge-Triggered Flip-Flops
C~~(l~)-------q,~---,
lD
(3)
2D
(4)
C~.....;.(l~)-------a
lD
(3)
10
t-+-----10
2D
(4)
20
20
3D .....;.(7..;..)----t--i
3D
(7)
30
4D
t-+-cc>-'---
(8)
4D
40
50
(13)
eo
(14)
7D
(17)
eo
(18)
3Q
(8)
40
5D
(13)
1--+-<0"":":";;:'" 50
50
6D
(14)
60
I-+-"':";;;~ 80
7D
(17)
70
70
8D
(18)
80
80
CLOCK (11)
TL/F/6431-3
TUF/6431-4
2-370
Absolute Maximum Ratings
(See Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
Storage Temperature Range
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
7V
-65'Cto + 150'C
Operating Free Air Temperature Range
DM54LS and 54LS
- 55'C to + 125'C
DM74LS
O'Cto +70'C
Recommended Operating Conditions
Symbol
Vee
Supply Voltage
VIH
High Level Input Votage
DM74LS373
DM54LS373
Parameter
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
V
V
2
VIL
Low Level Input Voltage
0.7
0.8
V
10H
High Level Output Current
-1
-2.6
mA
10L
Low Level Output Current
24
mA
tw
Pulse Width
(Note 2)
L
I
12
Enable High
15
15
Enable Low
15
15
tsu
Data Setup Time (Notes 1 & 2)
5.,l.
5.,l.
tH
Data Hold Time (Notes 1 & 2)
20.,l.
20.,l.
TA
Free Air Operating Temperature
-55
125
ns
ns
ns
0
70
'C
Max
Units
-1.5
V
Note 1: The symbol (J,) indicates the falling edge of the clock pulse is used for reference.
Nate 2: TA
= 25'C and Vee = 5V.
'LS373 Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Min
Conditions
=
=
VI
Input Clamp Voltage
Vee
VOH
High Level Output Voltage
Vee = Min
10H = Max
VIL = Max
VIH = Min
DM54
Vee = Min
IOL = Max
VIL = Max
VIH = Min
DM54
10L = 12 mA
Vee = Min
DM74
VOL
Low Level Output Voltage
II
Input Current @ Max
Input Voltage
IIH
High Level Input Current
IlL
Low Level Input Current
10ZH
Off-State Output
Current with High
Level Output
Voltage Applied
10ZL
lOS
Icc
Vee
=
Min,ll
Max, VI
Typ
(Note 1)
-18 mA
2.4
3.4
2.4
3.1
V
DM74
DM74
=
0.25
0.4
0.35
0.5
V
0.4
7V
0.1
mA
Vee
20
Vee
-0.4
/LA
mA
20
/LA
-20
/LA
= Max, VI = 2.7V
= Max, VI = 0.4V
Vee = Max, Vo = 2.7V
VIH = Min, VIL = Max
\
Off-State Output
Current with Low
Level Output
Voltage Applied
Vee = Max, Vo = 0.4V
VIH = Min, VIL = Max
Short Circuit
Output Current
Vee = Max
(Note 2)
Supply Current
Vee = Max
DM54
-50
-225
DM74
-50
-225
24
2-371
40
mA
mA
'LS373 Switching Characteristics atVce = 5VandTA = 25·C
(See Section 1 for Test Waveforms and Output Load)
Symbol
tplH
tpHL
tplH
tpHL
tPZH
tpZl
tpHZ
From
(Input)
To
(Output)
Parameter
RL
CL
= 6670
= 45pF
Min
CL
= 150pF
Min
Max
Units
Max
Propagation Delay
Time Low to High
Level Output
Data
to
Q
18
26
ns
Propagation Delay
Time High to Low
Level Output
Data
to
Q
18
27
ns
Propagation Delay
Time Low to High
Level Output
Enable
to
Q
30
38
ns
Propagation Delay
Time High to Low
Level Output
Enable
to
Q
30
36
ns
Output Enable
Time to High
Level Output
Output
Control
to AnyQ
28
36
ns
Output Enable
Time to Low
Level Output
Output
Control
to Any Q
36
50
ns
Output Disable
Time from High
Level Output (Note 3)
Output
Control
toAnyQ
20
ns
Output Disable
Output
Time from Low
Control
25
Level Output (Note 3)
to AnyQ
Note 1: Aillypicals are at Vee = 5V, TA = 25'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: CL = 5 pF.
tpLZ
ns
Recommended Operating Conditions
Symbol
DM54LS374
Parameter
DM74LS374
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
Vce
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
0.7
0.8
V
IOH
High Level Output Current
-1
-2.6
mA
2
2
12
V
V
IOl
Low Level Output Current
24
mA
fClK
Clock Frequency (Note 2)
0
35
0
35
MHz
fCLK
Clock Frequency (Note 3)
0
20
0
20
MHz
tw
Pulse Width
(Note 4)
I
I
Clock High
15
15
Clock Low
15
15
Isu
Data Setup Time (Notes 1 & 4)
20t
20t
tH
Data Hold Time (Notes 1 & 4)
1t
1t
-55
Free Air Operating Temperature
TA
Note 1: The symbol (t) indicates the rising edge of the clock pulse Is used for reference.
Note 2: CL = 45 pF, RL = 6670, TA = 25·C and Vee = 5V.
Note 3: CL = 150 pF, RL = 667n, TA = 2S·C and Vee = SV.
Note 4: T... = 2S·C and Vee = 5V.
2-372
125
0
ns
ns
ns
70
·C
'LS374 Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 1)
= Min,ll = -18 mA
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vee
VOH
High Level Output Voltage
Vee = Min
10H = Max
VIL = Max
VIH = Min
DM54
2.4
3.4
DM74
2.4
3.1
Vee = Min
10L = Max
VIL = Max
VIH = Min
DM54
0.25
0.4
DM74
0.35
0.5
10L = 12mA
Vee = Min
DM74
VOL
Low Level Output Voltage
V
Input Current @ Max
Input Voltage
Vee
= Max, VI = 2.7V
= Max, VI = 0.4V
Vee = Max, Vo = 2.7V
VIH = Min, VIL = Max
IIH
High Level Input Current
Low Level Input Current
IOZH
Off·State Output
Current with High
Level Output
Voltage Applied
IOZL
los
lee
0.4
0.25
= Max, VI = 7V
II
IlL
V
0.1
mA
Vee
20
Vee
-0.4
IlA
mA
20
IlA
-20
IlA
Off·State Output
Current with Low
Level Output
Voltage Applied
Vee = Max, Vo = O.4V
VIH = Min, VIL = Max
Short Circuit
Output Current
Vee = Max
(Note 2)
Supply Current
Vee
DM54
-50
-225
DM74
-50
-225
= Max
27
45
mA
mA
'LS374 Switching Characteristics at Vee = 5V and TA = 25'C
(See Section 1 for Test Waveforms and Output Load)
RL
Symbol
Parameter
CL
Min
= 6670
= 45pF
Max
35
CL
Min
= 150pF
Units
Max
fMAX
Maximum Clock Frequency
tpLH
Propagation Delay Time
Low to High Level Output
20
28
32
ns
tpHL
Propagation Delay Time
High to Low Level Output
28
38
ns
tpZH
Output Enable Time
to High Level Output
28
44
ns
tPZL
Output Enable Time
to Low Level Output
28
44
ns
tpHZ
Output Disable Time
from High Level Output (Note 3)
20
Output Disable Time
25
from Low Level Output (Note 3)
Nota 1: All typlcals are al Vee = 5V, TA = 25'C.
Nola 2: Not more Ihan one oulpul should be shorted al a lime, and the durallon should nol exceed one second.
Note 3: CL = 5 pF.
tpLZ
2·373
MHz
ns
ns
•
§ ~National
~ Semiconductor
54LS375/DM74LS375
4-Bit Latch
General Description
The 'LS375 is a 4-bit D-type latch for use as temporary storage for binary information between processing units and input/output or indicator units. When its Enable (E) input is
HIGH, a latch is transparent, i.e., the Q output will follow the
D input each time it changes. When E is LOW a latch stores
the last valid data present on the D input preceding the
HIGH-to-LOW transition of E. The 'LS375 is functionally
identical to the 'LS75 except for the comer power pins.
Connection Diagram
Logic Symbol
. Dual·ln·Llne Package
01- 1
01- 2
01- 3
El,2- 4
02- 5
02- 6
02- 7
GNO- 8
'-'
16
I I i
-Vee
01
15 -04
14 -04
13 -04
03
04
4-El,2
12- E3,4
01
12 -E3,4
11 ~03
10 ~03
9 ~03
02
03
04
TlIF/9830-2
Vee = Pin 16
GND = PinS
TL/F/9830-1
Order Number 54LS375DMQB,
54LS375FMQB, DM74LS375M or DM74LS375N
See NS Package Number
J16A, M16A, N16E or W16A
Pin Name
D1-D4
E1,2
E3,4
Q1-Q4
Q1-Q4
02
Description
Data Inputs
Latches 1, 2 Enable Inputs
Latches 3, 4 Enable Inputs
Latch Outputs
Complementary Latch Outputs
2-374
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
10V
Operating Free Air Temperature Range
54LS
-55'Cto + 125'C
OM74LS
O'Cto +70'C
Storage Temperature Range
-65'Cto +150'C
Recommended Operating Conditions
Symbol
54LS375
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
10H
High Level Output Current
DM74LS375
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
2
V
V
0.7
0.8
V
-0.4
-0.4
mA
8
rnA
70
'C
10L
Low Level Output Current
TA
Free Air Operating Temperature
4
t 8 (H)
Is (L)
Setup Time HIGH or LOW
On to En
20
20
ns
th (H)
th (L)
Hold Time HIGH or LOW
Onto En
0
0
ns
tw(H)
En Pulse Width HIGH
20
15
ns
-55
125
0
Electrical Characteristics
Over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
= Min,ll =
VI
Input Clamp Voltage
Vee
VOH
High Level Output
Voltage
Vee = Min,lOH
VIL = Max
= Max,
Low Level Output
Voltage
Vee = Min,lOL
VIH = Min
= Max,
VOL
Input Current @ Max
Input Voltage
IIH
High Level Input Current
= 4 mA, Vee = Min
Vee = Max, VI = 10V
54LS
2.5
OM74
2.7
=
IlL
los
Short Circuit
Output Current
Vee = Max
(Note 2)
Max, VI
V
V
OM74
0.35
0.5
0.25
0.4
= 0.4V
Enable Input
V
0.1
mA
0.4
mA
20
p.A
80
p.A
-0.4
mA
-1.2
mA
54LS
-20
-100
OM74
-20
-100
Supply Current
lee
Vee = Max
Note 1: All typical. are at Vee = 5V, TA = 25'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
2-375
-1.5
OM74
Enable Input
Vee
Units
0.4
= Max, VI = 2.7V
Low Level Input Current
Max
3.4
54LS
Enable Input
Vee
Typ
(Note 1)
-18 mA
10L
II
Min
12
rnA
mA
Switching Characteristics
Vee = +5.0V. TA = + 25"C (See Section 1 for waveforms and load configurations)
54LS/DM74LS
Parameter
Symbol
CL = 15pF
Min
Units
Max
tpLH
tpHL
Propagation Delay
DntoQn
27
23
ns
tpLH
tpHL
Propagation Delay
DntoOn
20
15
ns
tpLH
tpHL
Propagation Delay
En to Qn
27
25
ns
tpLH
tpHL
Propagation Delay
En to On
30
18
ns
Truth Table (Each Latch)
IIn
tn
tn + 1
D
Q
H
L
H
L
I
I
= BR time before Enable negative going transition.
In +1 = Bit time after Enable negative going transition.
H = HIGH Voltage Lavel
L = LOW Voltage Level
Logic Diagram (1/4 of diagram shown)
-I
DATA
ENABLE
--
.-
!
TO OTHER LATCH
-
ij
1
Q
I
TLIF/9830-3
2-376
~National
~ Semiconductor
54LS377/DM74LS377
Octal 0 Flip-Flop with Common Enable and Clock
General Description
Features
The 'LS377 is an 8-bit register built using advanced low
power Schottky technology. This register consists of eight
Ootype flip-flops with a buffered common clock and a buffered common input enable. The device is packaged in the
space-saving (0.3 inch row spacing) 20-pin package.
• 8-bit high speed parallel registers
• Positive edge-triggered Ootype flip-flops
• Fully buffered common clock and enable inputs
Connection Diagram
Dual-In-Line Package
E- 1
'-/
00- 2
00- 3
20 rVcc
19 rQ7
01- 4
18 r07
17 r06
01- 5
16 rQ6
02- 6
15 rOS
02- 7
14 rOS
03- 8
13 f-04
03- 9
12 r04
11 rep
GNO- 10
TLlF/9831-1
Order Number 54LS377DMQB, 54LS377FMQB,
54LS377LMQB, DM74LS377WM or DM74LS377N
See NS Package Number
E20A, J20A, M20B, N20A or W20A
Pin Names
E
00-07
CP
00-07
Description
Enable Input (Active LOW)
Oata Inputs
Clock Pulse Input (Active Rising Edge)
Flip-Flop Outputs
•
2-377
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
54LS
-55'Cto + 125'C
OM74LS
O"Cto +70"C
Storage Temperature Range
- 65'C to + 150"C
Note: The "Absolute Maximum Ratings" are those valuss
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum retings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Recommended Operating Conditions
Symbol
54LS377
Parameter
DM74LS377
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
0.7
0.6
V
Vee
Supply VoHage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
10H
High Level Output Current
-0.4
-0.4
mA
10L
Low Level Output Current
4
8
mA
70
'C
2
2
-55
125
V
TA
Free Air Operating Temperature
taCH)
ta (L)
Setup Time HIGH or LOW
Dn toCP
20
20
10
10
0
ns
It,(H)
It,(L)
Hold Time HIGH or LOW
On toCP
5.0
5.0
5.0
5.0
ns
ts(H)
ta (L)
Setup Time HIGH or LOW
EtoCP
10
20
10
20
ns
th (H)
It,(L)
Hold Time HIGH or LOW
EtoCP
5.0
5.0
5.0
5.0
ns
tw(H)
tw(L)
CP Pulse Width HIGH or LOW
20
20
20
20
ns
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 1)
Max
Units
-1.5
V
VI
Input Clamp Voltage
VOH
High Level Output
Voltage
= Min,ll = -18 mA
Vee = Min, 10H = Max
VIL = Max
Low Level Output
Voltage
Vee = Min, 10L = Max
VIH = Min
54LS
OM74
0.35
0.5
10L = 4 mA, Vee
OM74
0.25
0.4
II
Input Current @ Max
Input Voltage
Vee
IIH
High Level Input Current
Vee
VOL
IlL
Low Level Input Current
los
Short Circuit
Output Current
Vee
= Min
= Max, VI = 10V
54LS
2.5
OM74
2.7
V
3.4
0.4
0.1
mA
20.0
p.A
-0.4
mA
= Max, VI = 2.7V
Vee = Max, VI = 0.4V
Vee = Max
54LS
-20
-100
(Note 2)
OM74
-20
-100
Supply Current
Vee = Max
1: All typIcais are at Vee = 5V, TA = 25'C.
Note 2: Not more than one output should be shorted at a Ume, and the duration should not exceed one sacond.
Icc
Note
2-378
V
28
mA
mA
Switching Characteristics
Vee =
+ 5.0V, TA
=
+ 25°C (See Section 1 for waveforms and load configurations)
RL
Parameter
Symbol
=
2kO,CL
15pF
Units
Max
Min
Maximum Clock Frequency
=
MHz
30
25
25
Propagation Delay
CP to Q n
Functional Description
ns
Truth Table
The 'lS377 consists of eight edge-triggered D flip-flops with
individual D inputs and Q outputs. The Clock (CP) and Enable input (EO) are common to all flip-flops.
Inputs
When E is lOW, new data is entered into the register on the
next lOW-to-HIGH transition of CPo When E is HIGH, the
register will retain the present data independent of the CPo
Output
E
CP
On
On
H
l
l
X
X
../
../
H
l
No Change
H
l
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Logic Symbol
1 3 4
11
7 8 13 14 17 18
CP
2
5
6
9 12 15 16 19
TUF/9831-2
Vee = Pin 20
GND = Pin 10
Logic Diagram
~-c~~-+--~--~~--t-~--t--+--~-+--~~~;---t-~--r--+--~-+--;--'
QO
01
02
03
04
05
06
07
TL/F/9831-3
2-379
~
!I
~ National
~ Semiconductor
54LS378/DM74LS378 Parallel 0 Register with Enable
General Description
Features
The 'LS378 is a 6-bit register with a buffered common enable. This device is similar to the 'LS174, but with common
Enable rather than common Master Reset.
•
•
•
•
•
Connection Diagram
Logic Symbol
6-bit high speed parallel register
Positive edge-triggered Ootype inputs
Fully buffered common clock and enable inputs
Input clamp diodes limit high speed termination effects
Full TTL and CMOS compatible
Dual-In-Line Package
f- 1
""-..../
16
A iii
-Vee
111
Y Ii
00- 2
15 -05
00- 3
14 -05
01- 4
13 '-04
01- 5
12 '-04
02- 6
11
10
~03
02- 7
~03
I I I I I I
GNO- 8
9
~CP
2
E 000102030405
9 - CP
00 01 02 03 04 05
5
7 10 12 15
TL/F/9B32-2
vee = Pin 16
GND = PinS
TL/F/9B32-1
Order Number 54LS378DMQB, 54LS378FMQB,
DM74LS378M or DM74LS378N
See NS Package Number J16A, M16A, N16E or W16A
Pin Names
E
00-05
CP
00-05
Description
Enable Input (Active LOW)
Data Inputs
Clock Pulse Input (Active Rising Edge)
Flip-Flop Outputs
2-380
Absolute Maximum Ratings
(Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
10V
Operating Free Air Temperature Range
54LS
DM74LS
-54'Cto + 125'C
O'Cto +70'C
Storage Temperature Range
- 65'C to + 150'C
Recommended Operating Conditions
Symbol
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
10H
High Level Output Current
DM74LS378
54LS378
Parameter
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
V
V
2
0.7
0.8
V
-0.4
-0.4
mA
8
mA
70
'C
10L
Low Level Output Current
TA
Free Air Operating Temperature
4
ts(H)
Setup Time HIGH, Dn to CP
20
20
ns
th (H)
Hold Time HIGH, Dn to CP
5.0
5.0
ns
Is (L)
Setup Time LOW, Dn to CP
20
20
ns
th (L)
Hold Time LOW, Dn to CP
5.0
5.0
ns
Is (H)
Setup Time HIGH, E to CP
30
30
ns
th (H)
Hold Time HIGH, E to CP
5.0
5.0
ns
Is (L)
Setup Time LOW, E to CP
30
30
ns
th (L)
Hold Time LOW, E to CP
5.0
5.0
ns
tw(H)
CP Pulse Width HIGH
20
20
ns
-55
125
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
= Min,ll = -18mA
= Min, 10H = Max,
VIL = Max
Vee = Min, 10L = Max,
VIH = Min
VI
Input Clamp Voltage
Vee
VOH
High Level Output
Voltage
Vee
VOL
Low Level Output
Voltage
= 4 rnA, Vee = Min
Vee = Max, VI = 10V
10L
II
Input Current @ Max
Input Voltage
= Max, VI = 2.7V
= Max, VI = O.4V
Vee = Max
Min
54LS
2.5
DM74
2.7
Typ
(Note 1)
Max
Units
-1.5
V
V
3.4
0.4
54LS
DM74
0.35
0.5
DM74
0.25
0.4
0.1
V
mA
IIH
High Level Input Current
Vee
20.0
/LA
IlL
Low Level Input Current
Vee
-0.4
mA
los
Short Circuit
Output Current
(Note 2)
Icc
Supply Current
Vee
54LS
-20
-100
DM74
-20
-100
= Max Dn; E = GND, CP = ../
Nole 1: All typlcals are at Vee = 5V. TA = 25'C.
Note 2: Not more than one output should be shorted at a time. and the duration should not exceed one second.
2-381
22
mA
mA
•
Switching Characteristics
Vee = + 5.0V, TA = + 25°C (See Section 1 for waveforms and load configurations)
Symbol
2kO,CL = 15pF
Parameter
Min
fmax
Maximum Clock Frequency
tpLH
tpHL
Propagation Delay
CPtoQn
Units
Max
30
MHz
27
27
ns
Truth Table
Functional Description
The 'LS378 consists of eight edge-triggerad Ootype flip-flops
with individual 0 inputs and Q outputs. The Clock (CP) and
Enable (E) inputs are common to all flip-flops.
Inputs
When the E input is LOW, new data is entered into the
register on the LOW-to-HIGH transition of the CP input.
When the E input is HIGH the register will retain the present
data independent of the CP input.
CP
Dn
H
L
L
.../
.../
.../
X
No change
H
L
H
L
H - HIGH Voltage Level
L - LOW Voltage Level
X - Immaterial
2-382
Output
E
Logic Diagram
CP
--
01
DO
CP
0
CP
0
r-- E
-E
02
CP
0
r-- E
03
CP
0
r-- E
04
CP
0
r-- E
05
CP
0
r-- E
Q
Q
Q
Q
Q
Q
QO
Ql
Q2
Q3
04
Q5
TL/F/9832-3
2·383
~
!} ~ National
~ Semiconductor
54LS379/DM74LS379
Quad Parallel Register with Enable
General Description
Features
The LS379 is a 4-bit register with buffered common Enable.
This device is similar to the LS175 but features the common
Enable rather than common Master Reset.
•
•
•
•
Connection Diagram
Logic Symbol
Edge-triggered O-type inputs
Buffered positive edge-triggered clock
Buffered common enable input
True and complement outputs
Dual-In-Llne Package
f-
1
\....../
QO- 2
16 ~Vcc
15 ~Q3
00- 3
14 ~03
DO- 4
13
01- 5
12 1-02
01- 6
111-02
Ql- 7
10 I-Q2
GND- B
91-CP
~
E
i i
00
Y Y
01
02
03
9 - CP
~D3
QO
E
CP
QO-Q3
00-03
Q3
TUF/10186-2
GND
TL/F/l01B6-1
00-03
Q2
Vee = Pin 16
Order Number 54LS379DMQB, 54LS379FMQB,
54LS379LMQB, DM74LS379M or DM74LS379N
See NS Package Number E20A,
J16A, M16A, N16E or W16A
Pin
Names
Ql
Description
Enable Input (Active LOW)
Oatalnputs
Clock Pulse Input (Active Rising Edge)
Flip-Flop Outputs
Complement Outputs
2-384
= PinS
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Operating Free Air Temperature Range
54LS
-55·Cto +125·C
DM74LS
O·Cto +70·C
Storage Temperature Range
- 65·C to + 150·C
Recommended Operating Conditions
Symbol
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
10H
High Level Output Current
DM74LS379
54LS379
Parameter
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
V
V
2
0.7
0.8
V
-0.4
-0.4
mA
8
mA
70
·C
10L
Low Level Output Current
TA
Free Air Operating Temperature
ts(H)
ts(L)
Setup Time HIGH or LOW
DntoCP
20
20
th(H)
th(L)
Hold Time HIGH or LOW
DntoCP
5
5
ts(H)
ts(L)
Setup Time HIGH or LOW
EtoCP
25
25
th(H)
th(L)
Hold Time HIGH or LOW
EtoCP
5
5
tw(L)
CP Pulse Width LOW
17
17
4
-55
125
0
ns
ns
ns
ns
ns
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 1)
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vee = Min, 11= -18 mA
VOH
High Level Output
Voltage
Vee = Min, 10H = Max,
VIL = Max
54LS
2.5
DM74
2.7
Low Level Output
Voltage
Vee Min, 10L = Max,
VIH = Min
54LS
0.4
DM74
0.5
10L = 4 mA, Vee = Min
DM74
0.4
VOL
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 10V
V
0.1
V
mA
IIH
High Level Input Current
Vee = Max, VI = 2.7V
20
p.A
IlL
Low Level Input Current
Vee = Max, VI = 0.4V
-0.4
mA
los
Short Circuit
Output Current
Vee = Max
(Note 2)
54LS
-20
-100
DM74
-20
-100
Supply Current
Vee = Max
Icc
Note 1: All typicals are at Vee = SV, TA = 2s'e.
Note 2: Note more than one output should be shorted at a time, and the duration should not exceed one second.
2-385
18
mA
mA
Switching Characteristics
Vee
= + S.OV, TA = + 2S'C (See Section 1 for test waveforms and output load)
RL = 2 kO, CL = 15pF
Symbol
Parameter
Min
f max
Maximum Clock Frequency
tpLH
tpHL
Propagation Oelay
CPtoQn
Units
Max
30
MHz
27
27
Functional Description
ns
Truth Table
The LS379 consists of four edge-triggered Ootype flip-flops
with individual 0 inputs and Q and Q outputs. The Clock
(CP) and Enable (E) inputs are common to all flip-flops.
When the E input is HIGH, the register will retain the present
data independent of the CP input. The On and E inputs can
change when the clock is in either state, provided that the
recommended setup and hold times are observed.
Inputs
E
Outputs
On
CP
H
.../
X
L
L
.../
.../
H
L
On
On
No
Change
H
L
No
Change
L
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Logic Diagram
Dl
00
CP
D2
D3
.....
!
CP
-
!
D
CP
r-
E
Q
!
D
r-
E
.
E
!
D
CP
-
CP
D
Q
E
Q
Q
Q
Q
Q
Q
00
al
a,
a2
02
a3
~
E
ao
03
TUF/l0186-3
2-386
~National
~ Semiconductor
DM54LS380/74LS380
Multifunction Octal Register
General Description
The 'LS380 is an 8-bit synchronous register with parallel
load, load complement, preset, clear, and hold capacity.
Four control inputs (LD, POL, CLR, PRj provide one of four
operations which occur synchronously on the rising edge of
the clock (CK). The LS380 combines the features of the
LS374, LS377, LS273 and LS534 into a single 300 mil wide
package.
The LOAD operation loads the inputs (Dr Do) into the output register (OrOo), when POL is HIGH, or loads the compliment of the inputs when POL is LOW. The CLEAR operation resets the output register to all LOWs. The PRESET
operation presets the output register to all HIGHs. The
HOLD operation holds the previous value regardless of
clock transitions. CLEAR overrides PRESET, PRESET overrides LOAD, and LOAD overrides HOLD.
Connection Diagram
The output register (07-00) is enabled when OE is LOW,
and disabled (HI-Z) when OE is HIGH. The output drivers
will sink the 24 mA required for many bus interface standards.
Features/Benefits
• Octal Register for general purposes interfacing
applications
• 8 bits match byte boundaries
• Bus-structured pinout
• 24-pin SKINNYDIP saves space
• TRI-STATEIID outputs
• Low current PNP inputs reduce loading
Standard Test Load
81
Top View
5V..../o-
DATA
,m'oo
124
23
~
22
~
21
20
OUT
~ ~
19
~
18
17
~
16
~\~
15
~
14
HI
13
OUTPUT -
"0 :
r---
01
Q2
03
04
05
08
8-81T
CK
-0 ':0
01
02
05
06
[11,00
01
D2D3~05
~
03
04
9
CK
~~ 0De 0 - -
REGISTER
POL_
07
10
...- - .
l\"
TL/L/8339-2
11 J.12
07, POL GND
DATA
IN
TLlL/8339-1
Order Number OM54LS380J,
OM74lS38OJ or OM74lS380N
See NS Package Number J24F or N24C
fII
Function Table
OC ClK ClR PR lO POL 07-00 07-00 Operation
H
X
X X X X
LtLXXX
LtHLXX
LtHHHX
L
t
H H L
H
L
t
H H L
L
2-387
X
X
X
X
D
D
Z
HI-Z
LCLEAR
HPRESET
o HOLD
D
LOAD true
[j
LOADcomp
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage Vcc
Input Voltage
Off-State Output Voltage
Storage Temperature
5.5V
-65° to
+ 150"C
7V
5.5V
Operating Conditions
Symbol
Military
Parameter
Min
Typ
5
Vcc
Supply Voltage
4.5
TA
Operating Free-Air Temperature
-55
tw
Width of Clock
tsu
Set-UpTime
th
Hold Time
Commercial
Min
Typ
Max
5.5
4.75
5
5.25
V
125·
0
75
°C
High
40
40
Low
35
35
60
ns
50
-15
0
Units
Max
ns
-15
0
·Case temperature
Electrical Characteristics Over Operating Conditions
Symbol
Vil
Parameter
Test Conditions
Min
Typt
Low-Level Input Voltage
Max
Units
0.8
V
VIH
High-Level Input Voltage
VIC
Input Clamp Voltage
Vcc=MIN
11=-18mA
-1.5
V
III
Low-Level Input Current
Vcc=MAX
VI=O.4V
-0.25
mA
IIH
High-Level Input Current
Vcc=MAX
VI=2.4V
25
p.A
II
Maximum Input Current
Vcc=MAX
VI=5.5V
1
mA
Low-Level Output Voltage
Vcc=MIN
Vil =0.8V
VIH=2V
0.5
V
VOL
VOH
High-Level Output Voltage
Vcc=MAX
Vil =0.8V
VIH=2V
Output Short-Circuit Current'
Vcc=5.0V
IOZH
los
Vcc=MIN
Vil =0.8V
VIH=2V
Off-State Output Current
IOZl
V
2
MIL
IOl=12mA
COM
IOl=24mA
MIL
IOH= -2 mA
COM
IOH=-3.2mA
2.4
V
-100
Vo=O.4V
Vo=2.4V
-30
Vo=OV
Supply Current
Vcc=MAX
Icc
• No more Ihan one oulpul should be shorted al a lime and duration of Ihe short-circuil should nol exceed one second
t All typical values are al Vcc=SV. TA=2S'C
120
p.A
100
p.A
-130
mA
180
mA
Switching Characteristics Over Operating Conditions
Symbol
Parameter
fMAX
Maximum Clock Frequency
tpo
ClocktoQ
tpzx
Output Enable Delay
tpxz
Output Disable Delay
Test Conditions
(See Test Load)
Military
Min
Commercial
Typ
Max
20
R1=2000
R2 = 3900
2-388
Units
Typ
Max
35
20
30
ns
35
55
35
45
ns
35
55
35
45
ns
12.5
10.5
CL =50pF
Min
MHz
Logic Diagram
Octal Register
CK.!l-b_--------,
_------1f----_23 m
Ef&S
DO~3
L----t---'
PDL_11--..o'&-_~
~============~~~fiE
13
12
~
TL/L/8339-4
2-389
~National
~ Semiconductor
DM54LS380A/DM74LS380A
Multifunction Octal Register
General Description
The 'LS380A is an 8-bit synchronous register with parellel
load, load complement, preset, clear and hold capacity.
Four control inputs (LD, POL, CLR, PR) provide one of four
operations which occur synchronously on the riSing edge of
the clock (CK). The 'LS380A combines the features of the
'LS374, 'LS377, 'LS273 and 'LS534 into a single 300 mil
wide package.
The output register (07-00) is enabled when OE is LOW
and disabled (HI-Z) when OE is HIGH. The output drivers
will sink 24 rnA required for many bus interface standards.
Features
• Octal Register for general purpose interfacing applications
• 8 bits match byte boundaries
• Low current PNP inputs reduce loading
• Bus-structured pinout
• TRI-STATE@ outputs
• 24-pin SKINNYDIP saves space
The LOAD operation loads the inputs (07 -DO) into the output register (07-00), when POL is HIGH, or loads the compliment of the inputs when POL is LOW. The CLEAR operation resets the output register to all LOWs. The PRESET
operation presets the output register to all HIGHs. The
HOLD operation holds the previous value regardless of
clock transitions. CLEAR overrides PRESET, PRESET overrides LOAD, and LOAD overrides HOLD.
Connection Diagram
Top View
OATA
OUT
,m'oo
124
23
~
22
00
-
~
21
01
~
20
02
~
19
03
~
18
04
17
05
~
~'~
16
15
06
PRO-
B-BIT
REOISTER
DE 0 - POL _
-0 LD
00
01
02
03
04
05
06
[II , 00
01
02
03
04
05
06
07
9
CK
13
07
-0 CLR
CK
~
14
10
11 .1.12
07 , POL GNO
OATA
IN
TL/L/l0229-1
Order Number OM54lS380AJ, OM74LS380AJ, OM74LS380AN or OM74LS380AV
See NS Package Number J24F, N24C or V28A
Function Table
OC ClK ClR
H
L
L
L
L
L
X
X
t
t
t
t
t
L
H
H
H
H
PR lO POL 07-00 Q7-QO Operation
X X
X X
L X
H
H
H
H
L
L
X
X
X
X
X
X
X
X
a
H
L
0
D
0
2-390
Z
L
H
D
HI-Z
CLEAR
PRESET
HOLD
LOAD true
LOADcomp
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Vee Supply Voltage
Input Voltage
Off·State Output Voltage
Storage Temperature
-65'C to
ESO Tolerance
Czap = 100 pF
Rzap = 1500n
Test Method: Human Body Model
Test Specification: NSC SOP 5·028
7V
5.5V
5.5V
+ 150'C
>1000V
Recommended Operating Conditions
Symbol
Military
Parameter
Min
Commercial
Typ
Max
Min
5.5
Vee
Supply Voltage
4.5
5
TA
Operating Free·Air Temperature
-55
25
Te
Operating Case Temperature
Units
Typ
Max
4.75
5
5.25
V
0
25
75
'C
125
'C
Electrical Characteristics Series 24A Over Recommended Operating Temperature Range
Symbol
Parameter
Test Conditions
Min
VIH
High Level Input Voltage
Vil
Low Level Input Voltage
(Note 2)
Vie
Input Clamp Voltage
Vee
VOH
High Level Output Voltage
Min
Vee
Vil = 0.8V
VIH = 2V
10H
Vee = Min
Vil = 0.8V
VIH = 2V
10l = 12mA
MIL
10l = 24mA
COM
Vee = Max
Vil = 0.8V
VIH = 2V
Va = 2.4V
Val
10ZH
Low Level Output Voltage
Off·State Output Current (Note 3)
10Zl
(Note 2)
=
=
Typ
Max
2
=
10H =
Va
V
-0.8
Min, 11= -18mA
-2mA
MIL
-3.2mA
COM
2.4
Units
0.8
V
-1.5
V
2.9
0.3
= 0.4V
V
0.5
V
100
p.A
-100
p.A
mA
II
Maximum Input Current
Vee = Max, VI = 5.5V
1
IIH
High Level Input Current (Note 3)
Vee = Max, VI = 2.4V
25
p.A
III
Low Level Input Current (Note 3)
Vee = Max, VI = O.4V
-0.04
-0.25
mA
los
Output Short·Circuit Current
Vee = 5V
-70
-130
mA
Icc
Supply Current
Vee = Max
135
180
mA
-30
Va = OV (Note 4)
Note 1: Absolule maximum ratings are Ihose values beyond which Ihe device may be permanenUy damaged. They do nol mean thallhe device may be operaled al
Ihese values.
Note 2: These are absolule vollages with respect 10 the ground pin on Ihe device and Include all overahoots due 10 syslem andlor lesler noise. Do nol allempllo
lesllhese values wilhoul suitable equipment.
Note 3: 110 leakage as Ihe worsl case of 10ZX or IIX. e.g., IlL and 10Zl.
Note 4: During lOS measurmen!, only one outpul al a lime should be grounded. Permanenl damage otherwise may result.
II
I
2·391
:E
~
Switching Characteristics Over Recommended Operating Conditions
Symbol
Parameter
ts
Set-Up Time from Input
tw
Width of Clock
I
I Low
High
Commercial
Military
Test Conditions
Min
Typ
Max
Min
Typ
Units
Max
40
20
30
20
ns
20
7
15
7.
ns
35
15
25
15
ns
0
-15
0
-15
tH
Hold Time
Telk
Clock to Output
CL = 50pF
10
25
10
15
ns
Tpzx
Output Enable Delay
CL = 50pF
19
35
19
30
ns
Tpxz
Output Disable Delay
CL=5pF
15
35
15
30
ns
fmax
Maximum Frequency
15.3
Test Load
22.2
"=;;}
vee
MIL
Rl = 390
R2 = 750
OUTPUT
Tel
...--
EQUIVALENT INPUT
COM'L
Rl = 200
R2 = 390
"2
1M'
INPUT
--
~"
"
-=-
J""
r
r
...
Set-Up and Hold
..
~~.~
DATA
INPUT
--
vee
n
n
"'0
.,...
--
Test Waveforms
,;(Vt (SEE NOTE AI
TYPICAL OUTPUT
.00 NOM
~
~~
INPUT
MHz
BkQNOM
TUl/l0229-2
ClOCK
32
Schematic of Inputs and Outputs
ft.
":"
32
ns
OUTPUT
.:~
_--
":'
":'
TLll/l0229-3
3V
OV
Pulse Width
3V
8
HIGH·LEYEL
PULSE
DV
TUl/l0229-4
LOW·lEVEL
Vr
PULSE
Nota A: VT = I.SV.
Note B: Cl Includes probe and jig capacitsnce.
Note C: In the examples above. the phase relationships between Inpuls and
oU1puts have been chosen arbitrarily.
Vr
TL/l/l0229-5
Enable and Disable
ENABLE
IENAaLE~NOIIIN'UTi
NOftMALLYHIOH
OUTPUT
IS. OPEN)
NORMAUY LOW
IS' :~~~~
I'oH:X
~
.::.d;------
1'o':R,,------..
,ZtI
~
Z
---...i ...,
Z
I'ot.
... ,
I",
j
-z+[4\1'T-!...O.S.'
I",
I--i ~
' if--J. o.sv
T
TUUI0229-6
2-392
Logic Diagram
Octal Register
CK...!I'-{>-_ _ _ _ _ _ _ _ _ _ _- .
r-___________~----------~23~
~
001;:3
POL.:..:lI'-j,;~=:....J L..'::=========~
12
r-
TLlLlI0229-7
2-393
~
!i
~ National
~ Semiconductor
DM74LS390 Dual4-Bit Decade Counter
General Description
Features
Each of these monolithic circuits contains eight masterslave flip-flops and additional gating to implement two individual four-bit counters in a single package. The 'LS390 incorporates dual divide-by-two and divide-by-five counters,
which can be used to implement cycle lengths equal to any
whole andlor cumulative multiples of 2 andlor 5 up to divide-by-100. When connected as a bi-quinary counter, the
separate divide-by-two circuit can be used to provide symmetry (a square wave) at the final output stage. The 'LS390
has parallel outputs from each counter stage so that any
submultiple of the input count frequency is available for system-timing signals.
• Dual version of the popular 'LS90
• 'LS390 ... individual clocks for A and B flip-flops provide dual + 2 and + 5 counters
• Direct clear for each 4-bit counter
• Dual 4-bit version can significantly improve system densities by reducing counter package count by 50%
• Typical maximum count frequency ... 35 MHz
• Buffered outputs reduce possibility of collector commutation
Connection Diagram
Function Tables
Dual-In-Llne Package
BCD Count Sequence
(Each Counter)
(See Note A)
OUTPUTS
Ycc
[,6
2
OUTPUT
CLEAR
20A
2A
15
14
Y
2B
113
112
I
A
B
OA
CLpR
...
20B
111
200
200
110
19
I
I
I
Oa
Oc
00\
I
1
lA
2
\3
1
lOA
CLEAR OUTPUT
!
'i
14
18
Qc
Qa
QA
L
L
L
L
L
L
H
H
L
L
8
L
L
L
L
L
L
L
L
H
9
H
L
H
L
H
L
H
L
H
L
H
2
3
4
5
6
7
A
A
QD
0
1
Y
CLEAR
OA
OB
00
I
I
\5
\6
\7
\8
10C
100
GND
lOB
Outputs
Count
00\
I
H
H
H
H
H
H
L
L
L
L
BI-Qulnary (5-2)
(Each Counter)
(See Note B)
OUTPUTS
TLIF/8433-1
Order Number DM74LS390M or DM74LS390N
See NS Package Number M16A or N16E
Outputs
Count
0
1
2
3
4
5
6
7
8
9
Note
QA
QD
Qc
Qa
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
L
L
L
L
H
L
L
L
L
L
H
H
H
L
L
H
L
L
L
A: Output QA is connected to input B lor BCD count.
Note B: Output Qo Is connected to Input A lor Bi.quinary count
Note C: H
2-394
~
High Level, L
~
Low Level.
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
Clear
AorB
7V
5.5V
Operating Free Air Temperature Range
DM74LS
O·Cto +70·C
-65·C to + 150·C
Storage Temperature Range
Recommended Operating Conditions
Symbol
DM74LS390
Parameter
Units
Min
Nom
Max
4.75
5
5.25
V
0.8
V
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
IOH
High Level Output Current
-0.4
mA
IOL
Low Level Output Current
8
mA
fCLK
Clock Frequency (Note 1)
fCLK
tw
tREL
TA
1: CL
Nole 2: CL
Nole
Clock Frequency (Note 2)
Pulse Width (Note 1)
2
V
AtoOA
0
25
BtoOe
0
20
AtoOA
0
20
BtoOe
0
15
A
20
B
25
Clear High
20
Clear Release Time (Notes 3 & 4)
Free Air Operating Temperature
MHz
MHz
ns
25..1-
ns
0
·C
70
= 15 pF, RL = 2 kn, TA = 25'C and Vee = 5V.
= 50 pF, RL = 2 kn, TA = 25'C and Vee = 5V.
Nole 3: The symbol (J.) indicates the falling edge of the clear pulse is used for reference.
Nole 4: TA
= 25'C and Vee = 5V.
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
VI
Input Clamp Voltage
VOH
High Level Output
Voltage
VOL
Low Level Output
Voltage
II
IIH
Input Current @ Max
Input Voltage
High Level Input
Current
Min
Conditions
= Min, II = -18 mA
Vcc = Min, IOH = Max
VIL = Max, VIH = Min
VCC = Min, IOL = Max
VIL = Max, VIH = Min
IOL = 4 mA, Vcc = Min
Vee = Max, VI = 7V
Vee = Max
VI = 5.5V
Typ
(Note 1)
VCC
Vee = Max
VI = 2.7V
2-395
2.7
Max
Units
-1.5
V
V
3.4
0.35
0.5
0.25
0.4
Clear
0.1
A
0.2
B
0.4
Clear
20
A
40
B
80
V
mA
",A
PI
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted) (Continued)
Symbol
IlL
los
Parameter
Conditions
Low Level Input
Current
Vee
Short Circuit
Output Current
Vee
= Max, VI = O.4V
= Max (Note 2)
Min
Typ
(Note 1)
Max
Clear
-0.4
A
-1.6
B
-2.4
DM74
-20
-100
Supply Current
15
26
Vee = Max (Note 3)
Icc
Note 1: All typicals are at Vce = 5V. TA = 25"C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: ICC Is measured with all outputs open, both CLEAR inputs grounded following momentary connection to 4.5 and all other Inputs grounded.
Units
mA
mA
mA
Switching Characteristics at Vee = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
From (Input)
To (Output)
RL
CL
Min
fMAX
Maximum Clock
Frequency
= 15pF
Max
= 2kO
CL
Min
AtoQA
25
20
BtoQB
20
15
= 50pF
Units
Max
MHz
tpLH
Propagation Delay Time
Low to High Level Output
AtoQA
20
24
ns
tpHL
Propagation Delay Time
High to Low Level Output
AtoQA
20
30
ns
tpLH
Propagation Delay Time
Low to High Level Output
AtoQe
60
81
ns
tpHL
Propagation Delay Time
High to Low Level Output
AtoQe
60
81
ns
tpLH
Propagation Delay Time
Low to High Level Output
BtoQB
21
27
ns
tpHL
Propagation Delay Time
High to Low Level Output
BtoQB
21
33
ns
tpLH
Propagation Delay Time
Low to High Level Output
BtoQe
39
51
ns
tpHL
Propagation Delay Time
High to Low Level Output
BtoQe
39
54
ns
tpLH
Propagation Delay Time
Low to High Level Output
BtoQD
21
27
ns
tpHL
Propagation Delay Time
High to Low Level Output
BtoQD
21
33
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clear to
AnyQ
39
45
ns
2-396
Logic Diagram
'LS390
INPUT A ..;,(..,;1,..,;1,;;,5):....-_ _ _ _ _ _ _ _ _ _-T
CLEAR
~
Oc
(5, 9) OUTPUT
-OC
iL>T
CLEAR
~
L~T
OD ~ OUTPUT
OD
CLEAR
CLEAR (2, 12)
.."
INPUT
TL/F/6434-2
2·400
MHz
~National
~ Semiconductor
54LS395/DM74LS395
4-Bit Shift Register with TRI-STATE® Outputs
General Description
Features
The LS395 is a 4-bit shift register with TRI-STATE outputs
and can operate in either a synchronous parallel load or a
serial shift-right mode. as determined by the Select input An
asynchronous active LOW Master Reset (MR) input overrides the synchronous operations and clears the register_
An active LOW Output Enable (OE) input controls the TRISTATE output buffers. but does not interfere with the other
operations_ The fourth stage also has a conventional output
for linking purposes in multi-stage serial operations_
•
•
•
•
Connection Diagram
Logic Symbol
Shift right or parallel 4-bit register
TRI-STATE outputs
Input clamp diodes limit high speed termination effects
Fully CMOS and TTL compatible
iii i i
Dual-In-Llne Package
iiR-l
Ds- 2
Po- 3
Pl- 4
P2- 5
P3- 6
S- 7
GNO- 8
'-/
16 ~Vcc
15 f-OO
S PO PI P2 P3
2 - 0S
14
~01
10-(l CP
13
12
~02
9-(l DE
Q3~11
MR 00 01 02 03
~03
11~Q3
10
i-CP
TLlF/9B33-2
9f-OE
Vee = Pin 16
GND = Pin 8
TL/F/9833-1
Order Number 54LS395DMQB, 54LS395FMQB,
54LS395LMQB, DM74LS395WM or DM74LS395N
See NS Package Number
E20A, J16A, M16B, N16E or W16A
Mode Select Table
Outputs @tn + 1
Inputs@tn
Operating Mode
MR
CP
S Os Pn 00
Asynchronous Reset
Shift. SET First Stage
X X X X
H "- L H X
H
Shift. RESET First Stage
Parallel Load
H
H
X
L
L
""-
L
L
L
H X Pn PO
In. In+ 1 = Time before and after CP HIGH-IO-LOW Iransltlon
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immalerial
2-401
01
02
03
L
L
L
OOn 01n 02n
OOn 01n 02n
P1
P2 P3
•
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
7V
Input Voltage
10V
Operating Free Air Temperature Range
-55·C to + 125·C
54LS
OM74LS
O·Cto +70·C
Storage Temperature Range
- 65·C to + 150·C
Recommended Operating Conditions
Symbol
Vee
Supply Voltage
VIH
High Level Input Voltage
Vil
Low Level Input Voltage
10H
High Level Output Current
DM74LS395
54LS395
Parameter
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
2
V
V
0.7
0.8
V
-0.4
-0.4
mA
8
mA
70
·C
4
10l
Low Level Output Current
TA
Free Air Operating Temperature
ts(H)
Is (L)
Setup Time HIGH or LOW
S, Os or Pn to CP
20
20
20
20
ns
Ih(H)
Ih (L)
Hold TIme HIGH or LOW
S, Os or Pn to CP
5
5
5
5
ns
!w(L)
CP Pulse Width LOW
18
18
ns
!w (L)
MR Pulse Width LOW
20
20
ns
-55
125
0
Electrical Characteristics Over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
VI
Input Clamp Voltage
VOH
High Level Output
Voltage
Low Level Output
Voltage
VOL
Conditions
Min
Typ
(Note 1)
Vee = Min, 11= -18 mA
Max
Units
-1.5
V
Vee = Min, 10H = Max
Vil = Max
54LS
2.5
OM74
2.7
Vee = Min, 10l = Max
VIH = Min
54LS
OM74
0.35
0.5
10l = 4 mA, Vee = Min
OM74
0.25
0.4
V
0.4
V
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 10V
IIH
High Level Input Current
Vee = Max, VI = 2.7V
20
/Jo A
III
Low Level Input Current
Vee = Max, VI = O.4V
-0.4
mA
los
Short Circuit
Output Current
Vee = Max
(Note 2)
Supply Current with
Outputs OFF
Vee = Max, OE, OS, S = 4.5V
CP = '-., Pn = GNO
29
mA
Supply Current with
Outputs ON
Vee = Max, Os, S = 4.5V
OE, CP, Pn = GNO
25
mA
10ZH
TRI-STATE Output Off
Current HIGH
Vee = VeeH
VOZH = 2.7V
20
/JoA
IOZl
TRI-STATE Output Off
Current LOW
Vee = VeeH
VOZl = 0.4V
-20
IJoA
lee
0.1
54LS
-20
-100
OM74
-20
-100
Note 1: All typlcals are at Vee = SV, TA = 2S'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
2-402
mA
mA
Switching Characteristics
Vee =
+ 5.0V, TA = + 25'C (See Section 1 for waveforms and load configurations)
54LS/DM74LS
Symbol
Parameter
RL=2kO,CL= 15pF
Min
Max
fmax
Maximum Shift Frequency
tpLH
tpHL
Propagation Delay
CPtoO n
35
25
ns
tpHL
Propagation Delay
MR to On
35
ns
tpZH
tPZL
Output Enable Time
20
20
ns
tpHZ
tpLZ
Output Disable Time
17
23
ns
30
MHz
Functional Description
served. When the S input is LOW, a CP HIGH-LOW transition transfers data in 00 to ai, 01 to 02, and 02 to 03. A
left-shift is accomplished by connecting the outputs back to
the Pn inputs, but offset one place to the left, i.e., 03 to P2,
02 to PI, and 01 to PO, with P3 acting as the linking input
from another package.
When the OE input is HIGH, the output buffers are disabled
and the 00-03 outputs are in a high impedance condition.
The shifting, parallel loading or resetting operations can still
be accomplished, however.
The LS395 contains four D-type edge-triggered flip-flops
and auxiliary gating to select a D input either from a Parallel
(P n) input or from the preceding stage. When the Select
input is HIGH, the Pn inputs are enabled. A LOW signal in
the S input enables the serial inputs for shift-right operations, as indicated in the Truth Table.
State changes are initiated by HIGH-to-LOW transitions on
the Clock Pulse (CP) input. Signals on the Pn, DS and S
inputs can change when the Clock is in either state, provided that the recommended setup and hold times are ob-
Logic Diagram
P1
S-{~.c~--------~~-----------ri~----------~~~--------~
~--------------~
~----~~--~~~~--+-----~---+--~~----~--~---+----~
~-----d~~--+-----------4---~----------~--~----------~
~----~~~~~---------.---+----------~--~--------~
TLlF/9833-3
2-403
~ r---------------------------------------------------------------------~
"'III'
~ ~National
~ Semiconductor
54LS447/DM74LS447
BCD to 7-Segment Decoder/Driver
General Description
The 'LS447 is the same as the 'LS247 except that the Output OFF Voltage, VOH is specified as 7.0V rather than 15V,
with the same IOH limit of 250 p.A. For all other information
please refer to the 'LS247 data sheet
Connection Diagram
Dual-In-Une Package
110- 1
"-/
"1- 2
Cf- 3
BI/RBO- 4
R8i- 5
A2- 6
113- 7
16 I-Vcc
15 H
14 1-9
13 -8
12 -ii
11
10 -Ci
-c
GND- 8
9
-ii
TUF/l0187-1
Order Number 54LS447FMQB, 54LS447FMQB, DM74LS447M or DM74LS447N
See NS Package Number J16A, M16A, N16E or W16A
2-404
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and speclflcatlons_
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
54LS
-55'Cto + 125'C
DM74LS
O'Cto +70'C
Storage Temperature Range
-65'Cto + 150'C
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical CharacterisUcs"
table are not guaranteed at the absolute maximum raUngs.
The "Recommended Operating Conditions" table will define
the condiUons for actual device operation.
Recommended Operating Conditions
Symbol
54LS447
Parameter
DM74LS447
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
0.7
0.8
2
V
2
V
V
10H
High Level Output Current
-50
-50
p.A
10L
Low Level Output Current
12
24
mA
TA
Free Air Operating Temperature
70
'C
-55
125
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
= Min, II = -18 mA
= Max,
VI
Input Clamp Voltage
Vee
VOH
High Level Output
Voltage
Vee = Min, IOH
VIL = Max
IOFF
High Level Output Current
Segment Outputs, VM
VOL
Low Level Output
Voltage
Vee Min, IOL
VIH = Min
= 12 mA, Vee = Min
Vee = Max, VI = 10V
IIH
High Level Input Current
Vee
IlL
Low Level Input Current
Vee = Max, VI
BIIRBO Inputs
Short Circuit
Output Current
los
2.4
DM74
2.4
Max
Units
-1.5
V
V
3.4
250
54LS
IOL
Input Current @ Max
Input Voltage
54LS
= 7.0V
= Max,
II
Typ
(Note 1)
Min
p.A
0.4
DM74
0.35
0.5
DM74
0.25
0.4
V
0.1
= Max, VI = 2.7V
= 0.4V
Vee = Max
{Note 2)
mA
20
p.A
-0.03
-0.4
mA
-0.09
-1.2
mA
54LS
-0.3
-2.0
DM74
-0.3
-2.0
Supply Current
Vee = Max
lee
Note 1: All typical. are at Vee = 5V, TA = 25"C.
Note 2: Not more than one output should be shorted at a Ume, and the duration should not exceed one second.
mA
13
mA
Switching Characteristics at Vee = 5V, TA = 25'C (See Section 1 for Test Waveforms and Output Load).
RL = 2kn,CL = 15pF
Symbol
Parameter
Units
Min
tpLH
tpHL
Propagation Delay
Max
100
100
2-405
ns
•
Logic Symbol
2
abc
6
d
7
State Diagram
3
5
•
TL/F110187-3
13 12 11 10 9 15 14 4
TUF/l0187-2
Vee = Pin 16
GND = PinS
2-406
II?'A National
PRELIMINARY
~ Semiconductor
DM54LS450/DM74LS450 16: 1 Multiplexer
General Description
Features/Benefits
The 16:1 Mux selects one of sixteen inputs, EO through E15,
specified by four binary select inputs, A. B, C, and D. The
true data is output on Y and the inverted data on W. Propagation delays are the same for both inputs and addresses
and are specified for 50 pF loading. Outputs conform to the
standard 8 mA LS totem pole drive standard.
• 24-pin SKINNYDIP saves space
• Similar to 74150 (Fat DIP)
• Low current PNP inputs reduce loading
Connection Diagram
Standard Test Load
81
Top View
Vee
r~4
A
23
B
22
Y
21
20
5V-/0-
W E15 E14 E13 E12 E11
19
18
17
16
15
14
13
Hl
OUTPUT-....-
COY
A
-EO
El
1
EO
2
~
..LCL
W E15 E14 E13 E12
1"
EllE2
E3
3
~
E4
4
E3
E5
5
E4
£6
6
~
E7
7
~
B
E7
EB
E9 El0
9
~
10
~
11 .1.12
ru
~
TL/L/8338-1
Order Number DM54LS450J, DM74LS450J,
DM74LS450N or DM74LS450V
See NS Package Number J24F, N24C or V28A
Function Table
Input
Select
Output
D
C
B
A
W
V
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
EO
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
E13
E14
E15
EO
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
E13
E14
E15
2-407
.....
H2
TL/L/8338-2
Absolute Maximum Ratings
If Military/Aerospace specified devices are reqUired,
please contact the National Semiconductor Sales
OHlce/Dlstrlbutors for availability and specifications.
Supply Voltage Vee
Off-State Output Voltage
5.5V
Storage Temperature
-65· to
+ 150"C
7V
Input Voltage
5.5V
Operating Conditions
Symbol
Military
Parameter
Min
Nom
5
Vee
Supply Voltage
4.5
TA
Operating Free-Air Temperature
-55
Commercial
Units
Max
Min
Nom
Max
5.5
4.75
5
5.25
V
125·
0
75
·C
·Case temperature
Electrical Characteristics Over Operating Conditions
Symbol
Parameter
Test Conditions
Min
Typt
Max
Units
VIL
Low-Level Input Voltage
VIH
High-Level Input Voltage
VIC
Input Clamp Voltage
Vee = MIN
11=-lBmA
-1.5
V
IlL
Low-Level Input Current
Vee = MAX
VI = 0.4V
-0.25
mA
O.B
2
V
V
IIH
High-Level Input Current
Vee = MAX
VI=2.4V
25
p.A
II
Maximum Input Current
Vee = MAX
VI=5.5V
1
mA
VOL
Low-Level Output Voltage
Vee = MIN
VIL =O.BV
VIH=2V
0.5
V
VOH
High-Level Output Voltage
Vcc=MIN
VIL =O.BV
VIH=2V
Output Short-Circuit Current·
los
IOL=8rnA
MIL
IOH=-2rnA
COM
IOH=-3.2rnA
Vee=5.0V
Vo=OV
2.4
V
-30
Supply Current
Vee = MAX
Icc
'No more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
tAil typical values are atVcc=5V. TA=25"C.
60
-130
rnA
100
mA
Switching Characteristics Over Operating Conditions
Symbol
tPD
Parameter
Any Input to Y or W
Test Conditions
(See Test Load)
Military
Min
CL=50pF
Rl=5600
R2=1.1kO
2-40B
Commercial
Typ
Max
25
45
Min
Units
Typ
Max
25
40
ns
---------------~~
Logic Diagram
~
o
16:1 Mux
23
'~
EO
El
2
22
'1/
20
21
'M
~
.J
1
~
2
~
3
f=t
~VCC
r
'"
I
J
~
E3
E4
E5
E6
E7
E8
E9
El0
Ell
E12
E13
4
~
5
~
~
6
~
7
"'
"'
"'
J
""
I
1---1
"""""1
~
r
~
8
~
9
10
~
11
r----r
JI
19
18
r-;:::::
~
13
r---;
14
~
15
~
f
•
I
~
E14
16
I
E15
--,
f
.J
17
" " ' - "f
""
12
I
TL/L/B33B-3
2-409
i ~National
!J ~ Semiconductor
DM54LS450A/DM74LS450 16:1 Multiplexer
General Description
Features
The 16:1 Mux selects one of sixteen inputs, EO through E15,
specified by four binary inputs, A, B, C and D. The true data
Is output on Y and the inverted data on W. Propagation
delays are the same for both inputs and addresses and are
specified for 50 pF loading. Outputs conform to the standard 8 rnA LS totem pole drive standard.
•
•
•
•
Connection Diagram
Function Table
24-pin SKINNYDIP saves space
Similar to 74150 (Fat Dip)
Low current PNP inputs reduce loading
15 ns typical propagation delay
Input
Select
Top View
Vee
f24
ABC
23
22
0
21
ABC
I"""
1
2D
0
11
Y
18
17
16
15
2
E1
14
I
E2
E3
E4
4
E3
5
E4
E&
E5
&
E5
13
L
L
L
L
L
W E15 E14 Ell E12
EI1
E2
D
W E11 E14 E13 E12 Ell
ED
E1
ED
Y
E7
7
E9
8
L
L
E9 El0
E5
E7
L
~
•
E9
10
E9
11 .1.12
m~D
TL/L/l0228-1
Order Number DM54LS450AJ, DM74LS450AJ,
DM74LS450AN or DM74LS450AV
See NS Package Number
J24F, N24C or V28A
B
L
A
W
Y
L
EO
L
L
L
L
H
H
H
L
E2
H
L
H
H
H
L
H
H
EO
E1
E2
E3
E4
E5
E6
E7
EB
E9
E10
E11
E12
E13
E14
E15
H
L
L
H
H
H
L
L
L
H
H
H
H
L
H
H
L
L
H
H
H
H
H
H
2-410
Output
C
L
E1
E3
H
L
H
E4
L
H
E6
E7
L
H
~
L
E10
H
E5
EB
E11
L
ru
H
E'i3
L
H
rn
E14
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for avaffabillty and specifications.
Supply Voltage Vee
- 0.5V to + 7V (Note 2)
Input Voltage
-1.5V to + 5.5V (Note 2)
-1.5V to + 5.5V (Note 2)
Off-State Output Voltage
- 30.0 mA to + 5.0 mA (Note 2)
Input Current
Output Current (IOU
+100mA
- 65·C to + 150·C
Storage Temperature
Ambient Temperature with
Power Applied
Junction Temperature with
Power Applied
ESO Tolerance
CZAP = 100 pF
RZAP = 15000
Test Method: Human Body Model
Test Specification: NSC SOP-5-02B
- 65·C to + 125·C
- 65·C to + 150·C
2000V
Recommended Operating Conditons
Symbol
Military
Parameter
Min
Nom
5
Vee
Supply Voltage
4.5
TA
Operating Free-Air Temperature
-55
Commercial
Units
Max
Min
Nom
Max
5.5
4.75
5
5.25
V
125
0
75
·c
Electrical Characteristics Over Recommended Operating Conditions
Symbol
Parameter
Test Conditions
VIL
Low Level Input Voltage (Note 3)
VIH
High Level Input Voltage (Note 3)
Vie
Input Clamp Voltage
Vee
IlL
Low Level Input Current
Vee
IIH
II
Min
Typ
Max
Units
0.8
V
V
2
= Min, I = -18 mA
-1.5
V
-0.25
mA
High Level Input Current
= Max, VI = 0.4V
Vee = Max, VI = 2.4V
25
p.A
Maximum Input Current
Vee = Max, VI = 5.5V
1
mA
VOL
Low Level Output Voltage
Vee = Min
10L = 8mA
0.5
V
VOH
High Level Output Voltage
Vee = Min
IOH=-2mA
MIL
10H = -3.2mA
COM
lOS
Output Short-Circuit Current (Note 4)
Vee = 5V, Vo = OV
V
2.4
-30
-130
mA
Supply Current
Vcc = Max, Outputs Open
60
100
mA
Icc
Nole I: Absolute maximum ratings are Ihose values beyond which the device may be permanenlly damaged. Proper operation is nol guaranteed outSide Ihe
specified recommended operaling conditions.
Nole 2: Some device pins may be raised above these limits during programming operations according to the applicable specification.
Nole 3: These are absolule voltages wllh respect 10 Ihe ground pin on Ihe device and Include all overshools due to system andlor tesler noise. Do nol attempllo
tesllhese values withoul suitable equipment.
Nole 4: To avoid invalid readings in other parameler lasls, il is praferable 10 conduct Ihe los test lasl. To minimize inlernal heating, only one oulpul should be
shorted at a time with maximum duration of 1.0 second each. Prolonged shorting of a high output may raise Ihe chip temperature above normal and permanent
damage may resull
2-411
..
~
II)
!J
Switching Characteristics Over Operating Conditions
Symbol
Parameter
Military
Test Conditions
Min
Tpd
Input to Output
CL = 50pF
I
I
Test Load
Typ
Commercial
I
I
Max
I
I
Min
35
I
I
Typ
30
ns
Test Waveform
5V
Propagation Delay
Rl
INPUT
VT
3V
VT
... 1PLH!- .... I PHL !OUTPUT----t---t
MILICOM
Al = 560
A2
Units
Max
= 1.lk
~±
IN-PHASE
OUTPUT
R2
- -==
OUT OF PHASE
OUTPUT
VT
VT
OV
VOH
VOL
... IpHL ...... IpLH ~
VT
VT
TLlLlI0228-2
VOH
VOL
TLlL/l0228-3
Notes:
VT = I.SV
CL Includes probe and jig capacl1ance.
In lhe el<8fTlples above. the phase relationships be1ween inpu1s and outputs
have been chosen arbitrarily.
Schematic of Inputs and Outputs
o----..-----------------.. . .
EQUIVALENT INPUT
Vee
TYPICAL OUTPUT
-oVee
5k.ll. NOM.
40.0. NOM.
' - -....
, .rl-+-oOUTPUT
Jl"'J
rV
~
~~----4--------------~--~
TL/L/l0228-4
2-412
Logic Diagram
LS450A
A
23
~~l
22
21
)1 ~
20
~
...J
EO
24
1
J
r
El
Vee
2
-,
E2
3
-,
E3
4
J
'r---J
.~
E4
E5
5
,
6
~
~
E6
E7
E8
7
,
}-~
8
--,
El0
10
-,
El 1 13
J
14
-,
El 3 16
-,
E15
J
'-
-,
E14
~
}--
11
-,
El 2
~w
9
-,
E9
19
I
16
,
•
~
J
'-
~
12
17
-,
~
TLlLl1022B-5
2-413
_ r-------------------------------------------------------------------------,
!J ~ National
~
~ Semiconductor
DM54LS451/DM74LS451 Dual 8:1 Multiplexer
General Description
Features/Benefits
The Oual 8:1 Mux selects one of eight inputs, 00 through
07, specified by three binary select inputs, A, B, and C. The
true data is output on Y when strobed by S. Propagation
delays are the same for inputs, addresses and strobes and
are specified for 50 pF loading. Outputs conform to the
standard 8 mA LS totem pole drive standard.
• 24-pin SKINNYOIP saves space
• Twice the density of 74LS151
• Low current PNP inputs reduce loading
Connection Diagram
Standard Test Load
51
Top View
Vee
i"24
A
B
23
H
C
5
~
IV
H
5V-/o-
2Y 207 206 205 204 203
a
~
n "
"
~
HI
tl
OUTPUT-....-
A
C
S
IV
2V
-LCL
207 206 205 204
r- 100
T
203 -
101 102 103 104 105 106 107 200 201 202
6
7
8
9
10
11 .1,,'2
100 101 102 103 104 105 106 107 200 ·201 202 GNO
TUL/B337-1
Order Number DM54LS451J, DM74LS451J,
DM74LS451N or DM74LS451V
See NS Package Number J24F, N24C or V28A
Function Table
Inputs
Select
Outputs
Strobe
C
B
A
S
X
X
X
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
H
L
L
L
L
L
L
L
L
2-414
y
H
00
01
02
03
04
05
06
07
.......
H2
TL/U8337-2
Absolute Maximum Ratings
If MIlitary/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage Vee
Input Voltage
Off-State Output Voltage
5.5V
-65·Cto
Storage Temperature
+ 150·C
7V
5.5V
Operating Conditions
Symbol
Vee
Military
Parameter
Supply Voltage
Operating Free-Air Temperature
TA
·ease Temperature
Min
Nom
4.5
5
Commercial
-55
Units
Max
Min
Nom
Max
5.5
4.75
5
5.25
V
125'
0
75
·C
Electrical Characteristics Over Operating Conditions
Symbol
Parameter
Test Conditions
Min
Typt
Max
Units
0.8
V
VIL
Low-Level Input Voltage
VIH
High-Level Input Voltage
VIC
Input Clamp Voltage
Vee = MIN
11=-18mA
-1.5
V
IlL
Low-Level Input Current
Vee = MAX
VI=0.4V
-0.25
mA
IIH
High-Level Input Current
Vee = MAX
VI=2.4V
25
/LA
II
Maximum Input Current
Vee = MAX
VI=5.5V
1
mA
0.5
V
VOL
2
Vcc=MIN
VIL =0.8V
VIH=2V
Low-Level Output Voltage
VOH
High-Level Output Voltage
Vec=MIN
VIL =0.8V
VIH=2V
los
Output Short-Circuit Current'
Vec=5.0V
V
IOL=8mA
MIL
IOH=2mA
COM
IOH=-3.2mA
2.4
V
-30
Vo=OV
Supply Current
Vcc=MAX
Icc
'No more than one output should be shorted at a time and duration of the short·circuit should not exceed one second.
t All typical values are Vcc=SV, TA=2S"e.
60
-130
mA
100
mA
Switching Characteristics Over Operating Conditions
Symbol
tpD
Parameter
Any Input to Y
Test Conditions
(See Test Load)
Military
Min
CL =50pF
R1=560fl
R2=1.1f1
2-415
Commercial
Typ
Max
25
45
Min
Units
Typ
Max
25
40
ns
•
Logic Diagram
LS451
A
23
22
~~'
~~'
21
~2D
~~.
r
.J
lDO
.l..{>V
101
2
......
..,
~
~
102
lD
-y>
3-y>~
~
-.!i Vcc
J'
-'
)---,
!
10...-
r-r
19 IV
-;::::
104 - y > v
~
05-Y>....
r-r
I
D6.l..{>v
107-y>...,.
r---:
I
.....-,
F
.1
9
......
200~
201
IO
r;-
-v
~
2D2
1
.1L...f::>. .
~
203
r
r
r-a..!:::::::
~v
.!!..{>
--r
18
1
204
~v
.!!..{>
2V
~
-.,
..J
205.!!..{>V
2DS.!L.f>
r;"""'.,
J
1
207 .!!..{>.....
--r
2-416
r
1
TL/L/8337-3
~National
~ Semiconductor
DM54LS451 A/DM7 4LS451A
Dual 8: 1 Multiplexer
General Description
Features
The Dual Mux selects one of eight inputs, DO through D7,
specified by three binary select inputs, A, Band C. The true
data is output on Y when strobed by S. Propagation delays
are the same for inputs, addresses and strobes and are
specified for 50 pF loading. Outputs conform to the standard 8 rnA LS totem pole drive standard.
•
•
•
•
Connection Diagram
Function Table
24-pin SKINNYDIP saves space
Twice the density of 74LS151
Low current PNP inputs reduce loading
15 ns typical propagation delay
Top View
Vee
1~4
ABC
23
A
22
8
lY
S
21
C
20
S
2Y
19
1Y
Inputs
207 206 205 204 203
18
2Y
17
16
15
14
13
207 206 205 204
I""" 100
203 -
101 102 103 104 105 106 107 200 201 202
1
2
3
4
5
6
7
B
9
10
Outputs
Strobe
Select
C
B
A
S
X
L
L
L
L
H
H
H
H
X
L
L
H
H
L
L
H
H
X
L
H
L
H
L
H
L
H
H
L
L
L
L
L
L
L
L
y
H
DO
D1
D2
D3
D4
D5
D6
D7
11 .r2
100 101 102 103 104 105 106 107 200 201 202 UNO
TL/L/I 0227-1
Order Number DM54LS451AJ, DM74LS451AJ,
DM74LS451AN or DM74LS451AV
See NS Package Number J24F, N24C or V28A
•
2-417
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage Vee
- O.SV to + 7V (Note 2)
Input Voltage
-1.SV to + S.SV (Note 2)
Off-State Output Voltage
-1.SVto +S.SV (Note 2)
Input Current
-30.0 mA to + S.O mA (Note 2)
Output Current (IoU
+100mA
- 6S·C to + 1S0·C
Storage Temperature
Ambient Temperature with
Power Applied
Junction Temperature with
Power Applied
ESO Tolerance
CZAP = 100 pF
RZAP = 1S00.o.
Test Method: Human Body Model
Test Specification: NSC SOP-S-028
-6S·Cto + 12S·C
-6S·Cto +1S00C
2000V
Recommended Operating Conditions
Symbol
Military
Parameter
Min
Nom
S
Vee
Supply Voltage
4.S
TA
Operating Free-Air Temperature
-SS
Commercial
Units
Max
Min
Nom
Max
S.S
4.7S
S
S.2S
V
12S
0
7S
·c
Electrical Characteristics Over Recommended Operating Conditions
Symbol
Parameter
VIL
Low Level Input Voltage (Note 3)
VIH
High Level Input Voltage (Note 3)
VIC
Input Clamp Voltage
IlL
Low Level Input Current
IIH
High Level Input Current
II
Maximum Input Current
VOL
Low Level Output Voltage
VOH
High Level Output Voltage
los
Output Short-Circuit Current (Note 4)
Test Conditions
Min
Typ
Max
Units
0.8
V
2
= Min,l = -18mA
Vcc = Max, VI = 0.4V
Vcc = Max, VI = 2.4V
VCC = Max, VI = S.SV
Vee = Min
IOL = 8mA
IOH = -2mA
Vee = Min
IOH = -3.2mA
Vee = SV, Vo = OV
Vec = Max, Outputs Open
Vcc
MIL
V
-1.S
V
-0.2S
mA
2S
p.A
1
mA
O.S
V
2.4
V
COM
-30
-130
mA
Supply Current
60
100
mA
Icc
Note 1: Absolute maximum ratings are those values beyond which the device may be permanently damaged. Proper operation Is not guaranteed outside the
specified recommended operating conditions.
Note 2: Some device pins may be raised above these limits during programming operations according to the applicable specification.
Note 3: These are absolute voltages with respect to the ground pin on the device and include all overshoots due to system andlor tester noise. Do not attempt to
test these values without suitable equipment.
Note 4: To avoid invalid readings in other parameter tests, "is preferable to conduct the lOS test last. To mlnimlzelntemal heating, only one output should be
shorted at a time with maximum duration of 1.0 second each. Prolonged shorting of a high output may raise the chip temperature above normal and parmanent
damage may result.
2-418
r-
tJ)
Switching Characteristics Over Recommended Operating Conditions
Symbol
Parameter
Military
Test Conditions
Min
Tpcl
Input to Output
CL = 50pF
I
I
Test Load
Commercial
I
I
Typ
15
Max
Min
30
I
I
I
I
Typ
15
Units
l>
Max
25
ns
Test Waveform
5V
Propagation Delay
Rl
OUTPUT----....MIL/COM
Rl = 560
R2
~
CII
.....
=
~±
..
INPUT
....
tpLHI+- tpHL ..
VT
OV
VOH
VOL
.. tpHL ~-tpLH ~
OUT OF PHASE
OUTPUT
Uk
3V
VT
VT
IN-PHASE
OUTPUT
R2
VT
VT
VOH
VrJ
TLlL/1D227-2
VOL
TL/L/1D227-3
Noter.
VT = 1.5V
CL Includes probe and Ilg capaci1ance.
In the examples above, \he phase relationships between Inputs and outputs
have been chosen arbitrarily.
Schematic of Inputs and Outputs
EQUIVALENT INPUT
Veeo---~~------
TYPICAL OUTPUT
-----
5k4 NOM.
~,
~ r.".
.............
INPUT
-
404 NOM.
r",
--- ----
i~
~
~,
.....
..-.
-I-
~,
-I-
~~
Vee
OUTPUT
rV
--~
~
ti-
,.
-----
-==
-
-:.:
2-419
TLlLll D227-4
fII
....0(
~
Logic Diagram
~
LS451A
A
23
-8
22
21
,:,l ~ ~
100
101
,.
24
1
~
102
~
103
~
104
~
105
~
.....
106
~
107
~
200
20
~
......,
Vee
,
•
,
}--
-==
f"'1
,
......, } - ,
......,
19
1Y
~
•
f"'1
9
f"'1
201
202
203
204
205
206
207
10
.1L.[>
.!!..{>
.!!..{>
,
)-f"'1
17
.....:::::::
,
.....,
15
.!!..{>
1
-:
~
18
2Y
~
}--
12
--,
TLlLl1 0227-5
2-420
~National
~ Semiconductor
DM54LS453/DM74LS453
Quad 4: 1 Multiplexer
General Description
Features/Benefits
The quad 4:1 Mux selects one of four inputs, CO through C3,
specified by two binary select Inputs, A and 8. The true data
Is output on Y. Propagation delays are the same for Inputs
and addresses and are specified for 50 pF loading. Outputs
conform to the standard 8 mA LS totem pole drive standard.
• 24-pln SKINNYDIP saves space
• Twice the density of 74LS153
• Low current PNP Inputs reduce loading
Connection Diagram
Standard Test Load
Top View
Vee
j'24
A
23
B
22
4C3
21
lY
20
2Y
3Y
19
4Y
18
4C2 4Cl 4CD 3C3
17
16
15
14
HI
13
OUTPUT
A
~
B
4C3
1Y
2Y
3Y
4Y
.LCL
J
4C2 4Cl 4CO
3C3~
lCO
lCl lC2 lC3 2CO 2Cl 2C2 2C3 3CO 3Cl 3C2
6
7
8
9
10
11 J12
lCD lCl lC2 lC3 2CD 2Cl 2C2 2C3 3CD 3Cl 3C2 GND
TUU8336-1
Order Number DM54LS453J,
DM74LS453J or DM74LS453N
See NS Package Number J24F or N24C
Function Table
INPUT
SELECT
OUTPUTS
y
B
A
L:
L
H
L
H
L
H
H
2-421
CO
C1
C2
C3
H2
~
TL/L/8338-2
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage Vee
Off-State Output Voltage
5.5V
Storage Temperature
-66" to
+ 150"C
7V
Input Voltage
5.5V
Operating Conditions
Symbol
Vce
Military
Parameter
Supply Voltage
Operating Free-Air Temperature
TA
'Case temperature
Min
Typ
4.5
5
Commercial
-55
Units
Max
Min
Typ
Max
5.5
4.75
5
5.25
V
125"
0
75
·C
Electrical Characteristics Over Operating Conditions
Symbol
Parameter
Test Conditions
Min
Typt
Max
Units
0.8
V
VIL
Low-Level Input Voltage
VIH
High-Level Input Voltage
VIC
Input Clamp Voltage
Vee = MIN
11=-18mA
-1.5
V
IlL
Low-Level Input Current
Vce=MAX
VI = 0.4V
-0.25
mA
IIH
High-Level Input Current
Vce=MAX
VI = 2.4V
25
IJoA.
II
Maximum Input Current
Vee = MAX
VI=5.5V
1
mA
VOL
Low-Level Output Voltage
Vee = MIN
VIL =0.8V
VIH=2V
0.5
V
VOH
High-Level Output Voltage
Vcc=MIN
VIL =0.8V
VIH=2V
2
Output Short-Circuit Current"
los
V
IOL=8mA
MIL
IOH=-2mA
COM
IOH=-3.2mA
2.4
Vee=5.0V
V
-30
Vo=OV
Supply Current
Vee = MAX
Icc
'No more than one output should be shorted at a time and duration of the short·circuH should not exceed one second.
tAli typical values are al Vr;c = 5V. TA=25'C
60
-130
mA
100
mA
Switching Characteristics Over Operating Conditions
Symbol
tpD
Parameter
Any Input to Y
Test Conditions
(See Test Load)
Military
Min
CL =50pF
RI=560n
R2=1.1 kn
2-422
Commercial
Typ
Max
25
45
Min
Units
Typ
Max
25
40
ns
Logic Diagram
LS453
24
--Vee
lCO
lCl 2
lC2 3
lC3 4
2CO 5
2Cl 6
2C2 7
2C3 8
3CO 9
3Cl 10
3C2 11
3C3 13
4CD 14
4Cl 15
4C2 16
4C3 21
TLlL/8336-3
fII
2-423
~
~ ~National
~ ~ Semiconductor
DM54LS453A/DM74LS453A Quad 4:1 Multiplexer
General Description
Features
The quad 4:1 Mux selects one of four Inputs, CO through C3,
specified by two binary select Inputs, A and B. The true data
Is output on Y. Propagation delays are the same for Inputs
and addresses and specified for 50 pF loading. Outputs
conform to the standard 8 mA LS totem pole drive standard.
•
•
•
•
24-pln SKINNYDIP saves space
Twice the density of 74LS153
Low current PNP Inputs reduce loading
15 ns typical propagation delay
Connection Diagram
Top View
VC1:
i~4
A
23
A
-
B 4C3 lY
22
B
21
2Y
20
4C3 lY
3Y
I.
2Y
4Y
18
3Y
4C2 4Cl 4CO 3C3
17
4Y
18
1&
14
13
4C2 4Cl 4CO
3C3i-
lCO
lCl lC2 lC3 2CO 2Cl 2C2 2C3 3CO 3Cl 3C2
Z
3
4
&
6
7
B
9
10
11 .1.12
lCO lCl ICZ Ica ZCO 2CI 2C2 2C3 3CD 3CI' 3C2' GNO
TL/L/10226-1
Order Number DM54LS453AJ, DM74LS453AJ, DM74LS453AN or DM74LS453AV
See NS Package Number J24F, N24C or V28A
Function Table
Input
Select
Outputs
y
B
A
L
L
H
H
L
H
L
H
2-424
CO
C1
C2
C3
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
-0.5V to + 7V (Note 2)
Supply Voltage Vee
-1.5V to + 5.5V (Note 2)
Input Voltage
-1.5V to + 5.5V (Note 2)
Off-State Output Voltage
Input Current
- 30.0 mA to + 5.0 mA (Note 2)
Output Current (loLl
+100mA
-65'Cto + 150·C
Storage Temperature
Ambient Temperature with
Power Applied
Junction Temperature with
Power Applied
ESD Tolerance
CZAP = 100 pF
RZAP = 15000
Test Method: Human Body Model
Test Specification: NSC SOP5-028
-65·Cto + 125·C
-65·C to + 150·C
2000V
Recommended Operating Conditions
Symbol
Military
Parameter
Min
Nom
5
Vee
Supply Voltage
4.5
TA
Operating Free-Air Temperature
-55
Commercial
Units
Max
Min
Nom
Max
5.5
4.75
5
5.25
V
125
0
75
·c
Electrical Characteristics Over Recommended Operating Conditions
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
0.8
V
VIL
Low Level Input Voltage (Note 3)
VIH
High Level Input Voltage (Note 3)
Vie
Input Clamp Voltage
Vee = Min, I = -18 mA
-1.5
V
IlL
Low Level Input Current
Vee = Max, VI = 0.4V
-0.25
mA
IIH
High Level Input Current
Vee = Max, VI = 2.4V
25
/LA
II
Maximum Input Current
Vee = Max, VI = 5.5V
1
mA
VOL
Low Level Output Voltage
Vee = Min
IOL=8mA
0.5
V
VOH
High Level Output Voltage
Vee = Min
10H = -2mA
MIL
10H = -3.2mA
COM
los
Output Short-Circuit Current (Note 4)
lee
Supply Current
Note 1: Absolute maximum ratings are those
specified recommended operating conditions.
2
Vee = 5V, Va = OV
V
2.4
-30
V
-130
mA
60
100
mA
Vee = Max, Outputs Open
values beyond which the device may be permanently damaged. Proper operation is not guaranteed outside the
Nole 2: Some
device pins may be raised above these limits during programming operations according to the applicable specification.
respect to the ground pin on the device and include all overshoots due to system andlor tester noise. Do not attempt to
test these values without suitable equipment.
Note 4: To avoid invalid readings in other parameter tests, it is preferable to conduct the los test last To minimize internal healing, only one output should be
shorted at a Ume with maximum duration of 1.0 second each. Prolonged shorting of a high output may raise the chip temperature above normal and permanent
damage may result.
Note 3: These are absolute voltages with
fI
2-425
..
~
an
!J
Switching Characteristics Over Operating Conditions
Symbol
Parameter
Military
Test Conditions
Min
Tpd
Input to Output
CL = 50pF
Commercial
I
Typ
Max
I
15
30
Test Load
I
Min
I
Units
Typ
I
Max
15
I
25
ns
Test Waveform
5V
Propagation Delay
Rt
OUTPUT----t---+
MIL/COM
At = 560
A2 = Uk
~±
..
INPUT
Vr'
tpLH t+ ... tpHL~
I£VT
IN-PHASE
OUTPUT
R2
3V
VT
VT~
OV
VOH
VOL
.. tpHL 1+'" tpLH 1+
OUT OF PHASE
OUTPUT
VT
VT
TLlLl10226-2
VOH
VOL
TLlLl10226-3
Notes:
VT = 1.5V
CL Includes probe and Jig capacitance.
In the examples above, the phase relationships between Inputs and outputs
have been chosen artJilrarily.
Schematic of Inputs and Outputs
o----1_-----------------.....-o
EQUIVALENT INPUT
Vee
TYPICAL OUTPUT
~
5k4 NOM.
Vee
404 NOM.
'--~
... fl-....-oOUTPUT
"'J
rV
."
-;..
ti'
~~~-~~------------------+-------.
TL/LlI0226-4
2·426
Logic Diagram
LS453A
24
-Vee
lCO
lCl 2
lC2 3
lC3
2CO 5
2Cl
2C2
2C3 8
3CO 9
3Cl 10
3C2 11
3C3 13
4CO 14
4Cl
15
4C2 16
4C3
21
TL/L/l0226-5
2-427
~ ~National
~ Semiconductor
DM54LS460/DM74LS460 10-Bit Comparator
General Description
Features/Benefits
The 'LS460 is a 10-bit comparator with true and complement comparison status outputs. The device compares two
10-bit data strings (Ag - Ao and 8g - 80) to establish if this
data is Equivalent (EO = HIGH and NE = LOW) or Not Equivalent (EO = LOW and NE=HIGH).
Outputs conform to the usual 8 mA LS totem-pole drive
standard.
•
•
•
•
Connection Diagram
Standard Test Load
True and complement comparison status outputs
24-pin SKINNYDIP saves space
Low current PNP inputs reduce loading
Expandable in 10-bit increments
SI
6V-/o-
Top View
COMPARISON
STATUS
Vee
r~4
B9
AI
23
B9
BB
22
AI
'"iiE"""EQ'
AB
21
II
20
AI
19
18
EO
HE
Rl
B7
A7
17
87
BB
16
A7
A6
15
2
BB
3
M
4
~
5
~
6
H
7
AB
13
TL/Ll8335-3
15-
COMPARATOR
1
14
86 AS
III-lIT
~
B5
8
~
9
M
10
"
11 f2
~
TL/L/8335-1
AI
Order Number DM54LS46OJ,
DM74LS460J, or DM74LS460N
See NS Package Number J24F or N24C
Function Table
A9-AO
89-80
EQ
NE
A
A
H
L
8
A
8
8
H
L
L
H
2-428
Operation
}
Equivalent (A = 8)
Not Equivalent (kF8)
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage Vee
7V
Input Voltage
Off-State Output Voltage
Storage Temperature
5.5V
5.5V
-65' to + 150'C
Operating Conditions
Symbol
Vee
Military
Parameter
Supply Voltage
Operating Free-Air Temperature
TA
'Case Temperature
Commercial
Units
Min
Typ
Max
Min
Typ
Max
4.5
5
5.5
4.75
5
5.25
V
125"
0
75
'C
-55
Electrical Characteristics Over Operating Conditions
Symbol
Parameter
Test Conditions
Min
Typt
Max
Units
0.8
V
VIL
Low-Level Input Voltage
VIH
High-Level Input Voltage
Vie
Input Clamp Voltage
Vcc=MIN
11=-18mA
-1.5
V
IlL
Low-Level Input Current
Vcc=MAX
VI = O.4V
-0.25
mA
IIH
High-Level Input Current
Vcc=MAX
VI = 2.4V
25
IJ-A
II
Maximum Input Current
Vce=MAX
VI = 5.5V
1
mA
VOL
Low-Level Output Voltage
Vcc=MIN
VIL =0.8V
VIH=2V
0.5
V
VOH
High-Level Output Voltage
Vcc=MIN
VIL =0.8V
VIH=2V
los
Output Short-Circuit Current'
Vce=5.0V
V
2
IOL=8mA
MIL
10H= -2 mA
COM
V
2.4
IOH=-3.2mA
-30
Vo=OV
Supply Current
Vce=MAX
Icc
'No more than one output should be shorted at a time and duration of the short-circuit should not exceed one second
tAli typical values are at Vcc=sv, TA=2S'C
60
-130
mA
100
mA
Switching Characteristics Over Operating Conditions
Symbol
tpD
Parameter
Any Input to EQ or NE
Test Conditions
(See Test Load)
Commercial
Military
Min
CL =50pF
R1=5600
R2=1.1 kO
Typ
Max
25
45
Min
Units
Typ
Max
25
40
ns
EI
2-429
Logic Diagram
LS460
TL/L/B335-2
2-430
J?A National
~ Semiconductor
DM54LS460A/DM74LS460A 10-Bit Comparator
General Description
Features
The 'LS460A is a 10-bit comparator with true complement
comparison status outputs. The device compares two 10-bit
data strings (Ag - AO and Bg - BO) to establish if this data is
Equivalent (EQ=HIGH and NE=LOW) or Not Equivalent
(EQ=LOW and NE=HIGH).
•
•
•
•
•
True and complement comparison status outputs
24-pin SKINNYDIP saves space
Low current PNP inputs reduce loading
Expandable in 10-bit increments
15 ns typical propagation delay
Outputs conform to the usual 8 mA LS totem-pole drive
standard.
Connection Diagram
Top View
COMPARISON
STATUS
Vee
"1"24
B9
A9
23
BB
22
'"'iiE""EO
AS
21
20
1
2
~
lS
B7
A7
17
B6
16
A6
15
10-BIT
COMPARATOR
r- AD
M
19
3
M
4
~
5
~
6
~
7
~
B5
14
13
sn-
8
~
9
M "
10
11 J~2
M
~
TLlLlI0225-1
Order Number DM54LS460AJ, DM74LS460AJ, DM74LS460AN or DM74LS460AV
See NS Package Number J24F, N24C or V28A
Function Table
A9-AO
89-80
EQ
NE
A
B
A
A
B
B
H
H
L
L
L
H
Operation
}
Equivalent (A = B)
Not Equivalent (A;6B)
•
2-431
Absolute Maximum Ratings (Note 1)
Ambient Temperature
with Power Applied
Junction Temperature
with Power Applied
ESO Tolerance
CZAP = 100 pF
RZAP = 15000
Test Method: Human Body Model
Test Specification: NSC SOP·5·026
If MIlitary/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vee)
- 0.5 to + 7V (Note 2)
-1.5 to + 5.5V (Note 2)
Input Voltage
-1.5 to + 5.5V (Note 2)
Off·State Output Voltage
Input Current
-30.0 mA to + 5.0 mA (Note 2)
+100mA
Output Current (loLl
Storage Temperature
-65·C to + 1500C
-65·C to + 125·C
- 65·C to + 150·C
2000V
Recommended Operating Conditions
Symbol
Military
Parameter
Min
Nom
5
Vee
Supply Voltage
4.5
TA
Operating Free·Air Temperature
-55
Commercial
Units
Max
Min
Nom
Max
5.5
4.75
5
5.25
V
125
0
75
·C
Electrical Characteristics Over Recommended Operating Conditions
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
0.6
V
VIL
Low Level Input Voltage (Note 3)
VIH
High Level Input Voltage (Note 3)
VIC
Input Clamp Voltage
Vee = Min, I = -16mA
-1.5
V
IlL
Low Level Input Current
Vee = Max, VI = 0.4V
-0.25
mA
IIH
High Level Input Current
Vee = Max, VI = 2.4V
25
".A
II
Maximum Input Current
Vee = Max, VI = 5.5V
1
mA
VOL
Low Level Output Voltage
Vee = Min
IOL=6mA
0.5
V
VOH
High Level Output Voltage
Vee = Min
10H = -2mA
2
10H = -3.2mA
loS
Output Short·Circuit Current
(Note 4)
Vee = 5V, Vo = OV
I MIL
I COM
V
2.4
-30
V
-130
mA
Supply Current
60
100
mA
Vee = Max, Outputs Open
Icc
Note 1: Absolute maximum ratings are those values beyond which the device may be pennanently damaged. Proper operation is not guaranteed outside the
specifled recommended operating condHions.
Note 2: Some device pins may be raised above these limits during programming operations according to the applicable speclflcation.
Note 3: The.. are absolute voltages with respect to the ground pin on the device and include all overshoots due to system andlor tester noise. Do not attempt to
test these values without suHable equipment.
Note 4: To avoid Invalid readings In other parameter tests, It Is preferable to conduct the loS te.tlasl. To minimize Internal heating, only one output should be
shorted at a time wHh a maximum duration of 1.0 second each. Prolonged shorting of a high output may raise the chip temperature above normal and permanent
damage may reoull.
2·432
Switching Characteristics Over Recommended Operating Conditions
Symbol
Military
Test Conditions
Parameter
Min
Tpd
Input to Output
I
Typ
I
CL=50pF
Test Load
Commercial
I
Max
I
35
Min
I
I
Typ
I
I
Units
Max
30
ns
Test Waveform
5V
Propagation Delay
INPUT
Rt
VT
.. t PLH!-+tPHL I-
MIL/COM
OUTPUT----.....-
~±
Rl
....
R2
3V
Vr'
= 560
= 1.1k
VT
IN-PHASE
OUTPUT
Vr
OV
VOH
VOL
.. tpHL 1-+ tpLH ~
R2
OUT OF PHASE
OUTPUT
~VT
VT
VOH
VOL
TUU10225-3
TUU10225-2
Notes:
VT = 1.5V
CL includes probe and jig capacitance.
in the examples above, the phase relationships between inputs and outputs
have been chosen arbitrarily.
Schematic of Inputs and Outputs
EQUIVALENT INPUT
Vee o---~",,-----
-------------.. . -oVee
lYPlCAL OUTPUT
5kD. NOM,
4OD. NOM,
~,
r~
Jk'" r... .---~
INPUT o-...-t---fo.-....----.
.......
lJ ......- - 1
J~
"-
L-~
.... 'f-+-oOUTPUT
II"'J
r,/
~
~~~--~~--------------4-----'
TUL/l0225-4
2·433
I
logic Diagram
10-BII Comparator
A8~
BB,g..,
A9~
B9~
AB~
BO~
Al4-\
81-4-/
A2-!-\
82~
A3-H
83~
9
M"fo\
acf,-/
:40
A8~
86~
A74k
B72-i
12
TUL110225-5
2·434
~National
~ Semiconductor
DM54LS461/DM74LS461 Octal Counter
General Description
The LS461 is an 8-bit synchronous counter with parallel
load, clear, and hold capability. Two function select inputs
(10, 11) provide one of four operations which occur synchronously on the rising edge of the clock (CK).
The LOAD operation loads the inputs (07-00) into the output register (07-00). The CLEAR operation resets the output register to all LOWs. The HOLD operation holds the
previous value regardless of clock transitions. The INCREMENT operation adds one to the output register when the
carry-in input is TRUE (ci = LOW), otherwise the operation
is a HOLD. The carry-out (CO) is TRUE (CO = LOW) when
the output register (OrOo) is all HIGHs, otherwise FALSE
(CO = HIGH).
Two or more LS461 octal counters may be cascaded to
provide larger counters. The operation codes were chosen
such that when 11 is HIGH, 10 may be used to select between LOAD and INCREMENT as in a program counter
(JUMPIINCREMENT).
Features/Benefits
• Octal counter for microprogram-counter, DMA controller
and general purpose counting applications
• 8 bits match byte boundaries
• Bus-structured pinout
• 24-pin Skinny Dip saves space
• TRI-STATE@) outputs drive bus lines
• Low current PNP inputs reduce loading
• Expandable in 8-bit increments
The output register (07-00) is enabled when OE is LOW,
and disabled (HI-Z) when OE is HIGH. The output drivers
will sink the 24 mA required for many bus interface standards.
Connection Diagram
Standard Test Load
SI
Top View
~~:
02
~
~
ol:n~Y
w a a u a a "
5V..../o-
03· 04
05
06
lIr
Rl
H
OUTPUT -
...- - t
...LCL
i.e
-
DO
01
02
03
04
05
06
CI
8·BIT
COUNTER
CK
r- 10
cop.
OEIo-111-
DO
01
02
03
04
05
06
07
10 ,DO
01
02
03
04
05
06
07,
10
CK
T
07
DATA
IN
'1.1,'2
DND
I,
TUU8334-1
Order Number OM54LS461J,
OM74LS461J or OM74LS461N
See NS Package Number J24F or N24C
Function Table
OE
CK
H
L
L
L
L
L
X
t
t
t
t
t
11
10
CI
X X X
L L X
L H X
H L X
H
H
H
H
H
L
07-00
07-00
Operation
X
X
X
0
X
X
Z
HI-Z
CLEAR
HOLD
LOAD
HOLD
INCREMENT
2-435
L
a
0
a
a plus 1
R2
iF
TUUB334-2
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage Vee
Input Voltage
Off-State Output Voltage
Storage Temperature
5.5V
-65'C to
+ 150'C
7V
5.5V
Operating Conditions
Symbol
Military
Parameter
Min
Typ
5
Vee
Supply Voltage
4.5
TA
Operating Free-Air Temperature
-55
tw
Width of Clock
I
I
Commercial
Min
Typ
Max
5.5
4.75
5
5.25
V
125·
0
75
'C
Low
40
35
High
30
25
tsu
Set UpTime
60
th
Hold Time
0
Units
Max
ns
50
-15
ns
-15
0
-Case Temperature
Electrical Characteristics OVer Operating Conditions
Symbol
Parameter
Test Conditions
VIL
Low-Level Input Voltage
VIH
High-Level Input Voltage
VIC
Input Clamp Voltage
Vcc=MIN
Min
Typt
Max
Units
0.8
V
11=-18mA
-1.5
V
mA
2
V
IlL
Low-Level Input Current
Vcc=MAX
VI=O.4V
-0.25
ilH
High-Level Input Current
Vcc=MAX
VI=2.4V
25
pA
II
Maximum Input Current
Vcc=MAX
VI = 5.5V
1
mA
VOL
Low-Level Output Voltage
0.5
V
VOH
IOZL
High-Level Output Voltage
Vee = MIN
VIL =0.8V
VIH=2V
Off-State Output Current
Vee = MAX
VIL =0.8V
VIH=2V
Output Short-Circuit Current·
Vcc=5.0V
IOZH
los
Vcc=MIN
VIL =0.8V
VIH=2V
MIL
IOL =12mA
COM
IOL=24mA
MIL
IOH=-2mA
COM
V
2.4
IOH=-3.2mA
-100
Vo=0.4V
Vo=2.4V
Vee=OV
-30
Supply Current
Vee = MAX
Icc
'No more than one output should be shorted at a time and duration of the short·circuit should not exceed one second
t All typical values are at Vrx;=SV. TA=2S'C.
120
p.A
100
p.A
-130
rnA
180
rnA
Switching Characteristics Over Operating Conditions
Symbol
Parameter
Test Conditions
(See Test Load)
Military
Min
Commercial
Typ
Max
35
Units
Typ
Max
60
35
50
ns
20
35
20
30
ns
55
95
55
80
ns
10.5
Min
fMAX
Maximum Clock Frequency
tpD
CSI to CSO Delay
tpD
Clock to Q
tpD
Clock to CO
tpzx
Output Enable Delay
35
55
35
45
ns
tpxz
Output Disable Delay
35
55
35
45
ns
CL =50pF
R1=200n
R2=390 n
2-436
12.5
MHz
Logic Diagram
~
~
J
-
'
l
.
c
LS461
__________________________________
"--LL-__
I -. --,,~-,";;. aD
....._ _
Z1Q1
a,'
~_
a, •
11Q3
114 '
....0.4--D_-';:.,' III
D. •
•
11QI
11Q7
TLlL/8334-3
2-437
~National
~ Semiconductor
DM54LS461A/DM74LS461 A Octal Counter
General Description
The LS461A is an 8-bit synchronous counter with parallel
load, clear and hold capability. Two function select inputs
(10, 11) provide one of four operations which occur synchronously on the rising edge of the (CK).
Two or more LS461A octal counters may be cascaded to
provide larger counters. The operation codes were chosen
such that when 11 is HIGH 10 may be used to select between LOAD and INCREMENT as in a program counter
(JUMPIINCREMENn.
The LOAD operation loads the inputs (07-00) into the output register (Q7-QO). The CLEAR operation resets the output register to all LOWs. The HOLD operation holds the
previous value regardless of the clock transitions. The INCREMENT operation adds one to the output register when
the carry-in input is TRUE (Ci = LOW), otherwise the operation is a HOLD. The carry-out (CO) is True (CO = LOW)
when the output register (Q7-QO) is all HIGHs, otherwise
FALSE (CO = HIGH).
The output register (Q7-QO) is enabled when ()E is LOW,
and disabled (HI-Z) when ()E is HIGH. The output drivers
will sink 24 mA required for many bus interface standards.
Features
• Octal counter for microprogram-counter, DMA controller
for general purpose counting applications
• 8 bits match byte boundaries
• Low current PNP inputs reduce loading
• Bus-structured pinout
• TRI-STATEIIl> outputs drive bus lines
• 24-pin SKINNYDIP saves space
• Expadable in 8-bit increments
Connection Diagram
Top View
'::J:
'CI
Vee
CARRY
IN '00
fZ4
23
02
01
21
22
00
01
m
03' 04
20
02
19
03
18
04
05
06
16
17
05
06
C:~Y
15
8·aR
r---~CK
14
~
13
Q7
~~
DE 0---
COUNTER
01
1,-
020304D5"
DT
~
~
10
~
ill
CO 0-
-0 CI
-
Q7'
~M
H.~
H
"
11
~
J.
12
G~
DATA
IN
TL/L/l0224-1
Order Number DM54LS461AJ, DM74LS461AJ, DM74LS461AN or DM74LS461AV
See NS Package Number J24F, N24C or V28A
Function Table
OE
CK
11
10
CI
07-00
07-00
Operation
H
L
L
L
L
L
X
X
X
t
t
t
t
t
L
L
L
H
L
X
X
X
X
X
X
X
H
L
X
X
Z
L
Q
0
Q
Q Plus 1
HI-Z
CLEAR
HOLD
LOAD
HOLD
INCREMENT
H
H
H
H
H
0
2-438
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Vee Supply Voltage
7V
Input Voltage
5.5V
Off-State Output Voltage
5.5V
-65·C to
Storage Temperature
ESD Tolerance
Czap = 100 pF
Rzap = 1500
Test Method: Human Body Model
Test Specification: NSC SOP 5-028
+ 150·C
>1000V
Recommended Operating Conditions
Symbol
Military
Parameter
Min
Commercial
Max
4.75
5
5.25
V
0
25
75
·C
Max
Min
5.5
Vee
Supply Voltage
4.5
5
TA
Operating Free-Air Temperature
-55
25
Te
Operating Case Temperature
Units
Typ
Typ
·c
125
Electrical Characteristics Series 24A Over Recommended Operating Temperature Range
Symbol
Parameter
Test Conditions
Min
V,H
High Level Input Voltage
(Note 2)
V,L
Low Level Input Voltage
(Note 2)
Vie
Input Clamp Voltage
Vee = Min,lI = -18 mA
VOH
High Level Output Voltage
Vee = Min
V,L = 0.8V
V,H = 2V
IOH=-2mA
MIL
10H = -3.2mA
COM
Vee = Min
V,L = 0.8V
V,H = 2V
10L = 12 mA
MIL
10L = 24mA
COM
Vee = Max
V,L = 0.8V
V,H = 2V
Low Level Output Voltage
VOL
Off-State Output Current (Note 3)
10ZH
10ZL
Typ
Max
-0.8
2.4
Units
V
2
0.8
V
-1.5
V
2.9
V
0.5
V
Vo = 2.4V
100
p.A
Vo = O.4V
-100
p.A
mA
0.3
I,
Maximum Input Current
Vee = Max, V, = 5.5V
1
I'H
High Level Input Current (Note 3)
Vee = Max, V, = 2.4V
25
p.A
I,L
Low Level Input Current (Note 3)
Vee = Max, V, = 0.4V
-0.04
-0.25
mA
los
Output Short-Circuit Current
Vee = 5V
-70
-130
mA
lee
Nota
Vo = OV (Note 4)
-30
180
Supply Current
135
mA
Vee = Max
1: Absolute maximum ratings are those values beyond which the device may be permanently damaged. They do not mean that the device may be oparated at
these values.
Note 2: These are absolute voltages with respect to the ground pin on the device and include all overshoots due to system and/or tester noise. Do not attempt to
test these values without suiteble equipment.
Nota 3: 110 leakage as the worst case of 10ZX or IIX, e.g., I,L and 10ZL.
Note 4: During los measurement, only one output at a time should be grounded. Pennanent damage otherwise may result.
..
2-439
•
Switching Characteristics Over Recommended Operating Conditions
Symbol
Parameter
Military
Test Conditions
ts
Set-Up Time from Input
tw
Width of Clock
Min
Typ
Commercial
Max
Min
Typ
Units
Max
40
20
30
20
ns
High
20
7
15
7
ns
Low
35
15
25
15
ns
= 50pF
= 50pF
CL = 50pF
CL = 5pF
Tpd
CBi to CBO Delay
CL
23
35
23
30
ns
Tclk
Clock to Output
CL
10
25
10
15
ns
Tpzx
Output Enable Delay
19
35
19
30
ns
Tpzx
Output Disable Delay
15
35
15
30
ns
tH
Hold Time
f max
Maximum Frequency
Test Load
.~
Tel
-15
0
-15
ns
15.3
32
22.2
32
MHz
Schematic of Inputs and Outputs
TYPICAL OUTPUT
EQUIVALENT INPUT
....-_..
vee
vee
RI
MIL
RI = 390
R2 = 750
OUTPUT
COM'L
RI = 200
R2 = 390
'kg NOM
R2
":"
0
.....
INPUT
40Q
~
~. ~,
....... r"
-n
-- --
':'
TL/L/I0224-2
~
.
,
'"~
"".t)
--
":"
. ·n.·
INPUT
DATA
INPUT
":"
TL/LI'0224-3
3V
OV
Pulse Width
3V
8
HIGH·LEVEL
PULSE
OV
TL/LI1 0224-4
LOW·LEVEL
"
PULSE
Propagation Delay
~I"H.
IN·PIIABE
OUTPUT
..J1rvr
~~HL·
OUT OFPIIAIE
OUTPUT
"~
"
TL/LI1 0224-6
3V
",,1\..
INPUT - - - - - . / ( "
,:~
----
~Vr (SEE NOTE AI
CLOCK
OUTPUT
.,...
Test Waveforms
Set-Up and Hold
NOM
R
Enable and Disable
ov
I--,,"L.
~
~H
~::>f
EHABLE
IENAILI "N OR INPUT)
':'~
NORMALLYHIOH
~H
~I'--
~L
I--"LH.
~~
OUTPUT
~H
181 OPENI
Z
NORMALLY LOW
OUTPUT
lSI eLOSEDI
~L
~L
TLlLI1 0224-5
Not. A: VT = 1.5V.
Note B: CL Includes probe and Jig capacitance.
Note C: In the examples above, the phass relationships between Inputs and
outputs have been chosen arbitrarily.
2-440
I
---1..
~
'ZH
l.IV
~~l.IV
IrzL
IPH'
~D.IV
"" l--jL:I:
O.5V
I
TL/L/l0224-7
Logic Diagram
Octal Counter
ex
lL-~~----------------------------------l
~vcc
----------------------+-------o<~"a
DO
..L-----+:bt:=**=1[)
Z1 01
".
- . ' _ _ _.::.1IQ3
.. 7
..
._. L-""'~_.;;.17 ..
" ..
15'7
TL/LI10224-8
2-441
~National
~ Semiconductor
DM7 4LS465/DM74LS466/DM7 4LS467/DM7 4LS468
TRI-STATE® Octal Buffers
General Description
These devices provide eight, two-input buffers in each package. All employ the newest low-power-Schottky TTL technology. One of the two inputs to each buffer is used as a
control line to gate the output into the high-impedance
state, while the other input passes the data through the buffer. The 'LS465 and 'LS467 present true data at the outputs,
while the 'LS466 and 'LS468 are inverting. On the 'LS465
and 'LS466 versions, all eight TRI-STATE enable lines are
common, with access through a 2-input NOR gate. On the
'LS467 and 'LS468 versions, four buffers are enabled from
one common line, and the other four buffers are enabled
from another common line. In all cases the outputs are
placed in the TRI-STATE condition by applying a high logic
level to the enable pins. These devices represent octal, low
power-Schottky versions of the very popular DM54174365,
366, 367, and 368 (DM8095, 96, 97, and 98) TRI-STATE
hex buffers.
Features
• Octal versions of popular DM74365, 366, 367, and 368
(DM8095, 96, 97 and 98)
• Typical power dissipation
DM74LS465, 467 80 mW
DM74LS466, 468 65 mW
• Typical propagation delay
DM74LS465,467 15 ns
DM74LS466,468 10 ns
• Low power-Schottky, TRI-STATE technology
Connection Diagrams
Dual-In-Llne Packages
~
~
VI
AI
n
A2
"
A4
~
~
GND
~
VI
AI
n
A2
"
U
~
G2A8V8A7Y7M
ABV8A7V7A11
AI
VI
AI
V2
A3
va
GND
TLlF/6435-2
Tl/F/6435-1
A4
V4
GND
TLlF/6435-3
., "
AIY2A3Y3UY4
Order Numbers DM74LS465WM, DM74LS465N, DM74LS466WM,
DM74LS466N, DM74LS467WM, DM74LS467N, DM74LS468WM or DM74LS468N
See NS Package Number M20B or N20A
2-442
GND
TLlF/6435-4
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
DM74LS
Storage Temperature Range
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaran·
teed. The device should not be operated at these limits. the
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
O'Cto +70'C
-65'C to + 150'C
Recommended Operating Conditions
Symbol
DM74LS465, 466, 467, 468
Parameter
Units
Min
Nom
Max
4.75
5
5.25
V
0.8
V
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
IOH
High Level Output Current
-5.2
rnA
IOl
Low Level Output Current
24
rnA
TA
Free Air Operating Temperature
70
'C
V
2
0
'LS465 and 'LS467 Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
= Min,ll =
VI
Input Clamp Voltage
Vee
VOH
High Level Output
Voltage
Vee = Min, IOH = Max
VIL = Max, VIH = Min
VOL
Low Level Output
Voltage
Vee = Min, IOL = Max
Vil = Max, VIH = Min
Min
Typ
(Note 1)
-18 rnA
Input Current @Max
Input Voltage
IIH
High Level Input Current
III
Low Level Input
Current
-1.5
V
V
0.5
= 12 rnA, Vee = Min
Vee = Max, VI = 7V
= Max, VI = 2.7V
VI = 0.5V
Vee = Max
VI = 0.4V
Units
2.7
V
0.4
10L
II
Max
Vee
0.1
rnA
20
".A
A (Note 3)
-20
A (Note 4)
-50
G
-50
".A
Off·State Output Current
with High Level Output
Voltage Applied
Vee = Max, Vo = 2.4V
VIH = Min, Vil = Max
20
".A
Off·State Output Current
with Low Level Output
Voltage Applied
Vee = Max, Vo = 0.4V
VIH = Min, Vil = Max
-20
".A
los
Short Circuit
Output Current
Vee = Max
(Note 2)
-100
mA
Icc
Supply Current
Vee
26
rnA
10ZH
IOZl
Nola 1: All typicals are at Vce
-20
= Max (Note 3)
= 5V, TA = 25'C.
Nole 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Nola 3: Both G Inputs are at2V.
Nota 4: Both G inputs are at O.4V.
2·443
16
•
'LS465 and 'LS467 Switching Characteristics
at Vee = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
RL = 6670
Symbol
Parameter
CL = 50pF
Min
CL = 150pF
Max
Min
Units
Max
tpLH
Propagation Delay Time
Low to High Level Output
16
25
ns
tpHL
Propagation Delay Time
High to Low Level Output
28
40
ns
tPZH
Output Enable Time
to High Level Output
25
30
ns
tPZL
Output Enable Time
to Low Level Output
30
42
ns
tpHZ
Output Disable Time
from High Level Output (Note 1)
20
ns
tpLZ
Output Disable Time
from Low Level Output (Note 1)
27
ns
Note 1: CL = 5 pF.
'LS466 and 'LS468 Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 2)
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vee = Min, II = -18 mA
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
VIL = Max, VIH = Min
VOL
Low Level Output
Voltage
Vee = Min, 10L = Max
VIL = Max, VIH = Min
0.5
10L = 12 mA, Vee = Min
0.4
II
Input Current @Max
Input Voltage
IIH
High Level Input Current
Vee = Max, VI = 2.7V
IlL
Low Level Input
Current
Vee = Max
10ZH
10ZL
los
DM74
2.7
V
Vee = Max, VI = 7V
V
0.1
rnA
20
/LA
VI = 0.5V
A (Note 4)
-20
VI = 0.4V
A (Note 5)
-50
G
-50
!LA
Off·State Output Current
with High Level Output
Voltage Applied
Vee = Max, Vo = 2.4V
VIH = Min, VIL = Max
20
!LA
Off-State Output Current
with Low Level Output
Voltage Applied
Vee = Max, Vo = O.4V
VIH = Min, VIL = Max
-20
/LA
Short Circuit
Output Current
Vee = Max
(Note 3)
-100
mA
21
mA
-20
Supply Current
Vee = Max (Note 5)
lee
Note 2: All typical. are at Vee = 5V, TA = 25'C.
Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Nota 4: Both l3lnputs are at 2V.
Note 5: Both ~ Inputs are at O.4V.
2-444
13
'LS466 and 'LS468 Switching Characteristics
at Vee
=
5V and TA
=
25'C (See Section 1 for Test Waveforms and Output Load)
=
RL
Symbol
Parameter
CL
Min
=
6670
50pF
CL
Max
=
Units
150pF
Min
Max
tpLH
Propagation Delay Time
Low to High Level Output
10
16
ns
tpHL
Propagation Delay Time
High to Low Level Output
17
30
ns
tpZH
Output Enable Time
to High Level Output
15
30
ns
tpZL
Output Enable Time
to Low Level Output
35
45
ns
tpHZ
Output Disable Time
from High Level Output (Note 1)
20
ns
tpLZ
Output Disable Time
from Low Level Output (Note 1)
27
ns
Nale 1: CL
= 5 pF.
Function Tables
LS465
Inputs
LS466
Output
G2
A
Y
H
X
X
H
L
L
X
X
Hi-Z
Hi-Z
H
L
G1
L
L
H
L
Inputs
G2
A
Y
H
X
X
H
L
L
X
X
Hi-Z
Hi-Z
L
H
L
L
Output
G
A
H
L
L
H
L
X
H
L
LS468
LS467
Inputs
Output
G1
Inputs
Y
Hi-Z
H
L
H = High Logic Level
L = Low Logic Level
X = EHher High or Low Logic Level
HI-Z = High Impedance (Off) State
2-445
Output
G
A
H
L
L
X
H
L
Y
Hi-Z
L
H
~ ~National
~ Semiconductor
DM54lS469/DM74LS469 8-Bit Up/Down Counter
General Description
The 'LS469 is an a-bit synchronous up/down counter with
parallel load and hold capability. Three function-select inputs (LD, UD, CBI) provide one of four operations which
occur synchronously on the rising edge of the clock (CK).
The LOAD operation loads the inputs (07-00) into the output register (07-00). The HOLD operation holds the previous value regardless of clock transitions. The INCREMENT
operation adds one to the output register when the carry-in
input is TRUE (CBI = LOW), otherwise the operation is a
HOLD. The carry-out (CBO) is TRUE (CBO=LOW) when
the output register (OrOo) is all HIGHs, otherwise FALSE
(CBO=HIGH). The DECREMENT operation subtracts one
from the output register when the borrow-in input is TRUE
(CBI = LOW), otherwise the operation is a HOLD. The borrow-out (CBO) is TRUE (CBO= LOW) when the output register (07-00) is all LOWs, otherwise FALSE (CBO=HIGH).
The output register (07-00) is enabled when OE is LOW,
and disabled (HI-Z) when OE is HIGH. The output drivers
will sink the 24 mA required for many bus-interface standards. Two or more 'LS469 octal up/down counters may be
cascaded to provide larger counters.
Connection Diagram
Standard Test Load
Features/Benefits
• a-bit up/down counter for microprogram-counter, DMA
controller and general-purpose counting applications
• a bits matches byte boundaries
• Bus-structured pinout
• 24-pin SKINNYDIP saves space
• TRI-STATE® outputs drive bus lines
• Low current PNP inputs reduce loading
• Expandable in a-bit increments
Top View
~
Vee
CARRYI
BORRDW
IN 'uo
l~4
23
-<:
-
U1
n
22
UO
CBI
U2
U1
~
U2
~CK
DATA
OUT
U3 U4
a
81
~
U5
a
U3 U4
8-BIT
UP/ODWN
COUNTER
CARRYI
BORRDW
U7' OUT 1m
U6
n
~
U5
U6
III ,DO
01
"
~
R1
~
DUTPUT-.....-
t·
U7 0CBD
':"
DEC--
02
03
04
05
06
02
03
04
05
06
UO 007
9
CK
5v--7o-
10
11 J.12
07, U1I GND
DATA
IN
TLlLlB333-1
Order Number OM54LS469J,
OM74LS469J or OM74LS469N
See NS Package Number J24F or N24C
Function Table
OE CK LO UO CBI 07-00
H
L
L
L
L
L
X
X
t
t
t
t
t
L
H
H
H
H
X
X
X
X
L
L
H
H
H
L
H
L
X
0
X
X
X
X
2-446
07-00
Z
HI-Z
LOAD
HOLD
0
plus 1 INCREMENT
HOLD
0
minus 1 DECREMENT
0
o
o
Operation
....
R2
1:-
TLlLlB333-3
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage Vee
Off-State Output Voltage
5.5V
-65'Cto
Storage Temperature
+ 150'C
7V
Input Voltage
5.5V
Operating Conditions
Symbol
Military
Parameter
Min
Typ
5
Vee
Supply Voltage
4.5
TA
Operating Free-Air Temperature
-55
tw
Width of Clock
tsu
Set UpTime
60
th
Hold Time
0
I
I
Commercial
Units
Max
Min
Typ
Max
5.5
4.75
5
5.25
V
125'
0
75
'C
Low
40
35
High
30
25
10
ns
50
-15
ns
-15
0
·Case Temperature
Electrical Characteristics Over Operating Conditions
Symbol
Parameter
Test Conditions
Min
Typt
Max
Units
Vil
Low-Level Input Voltage
VIH
High-Level Input Voltage
VIC
Input Clamp Voltage
Vee = MIN
11=-lBmA
-1.5
V
III
Low-Level Input Current
Vcc=MAX
VI=0.4V
-0.25
mA
IIH
High-Level Input Current
Vcc=MAX
VI=2.4V
25
,..A
II
Maximum Input Current
Vee = MAX
VI=5.5V
1
mA
VOL
Low-Level Output Voltage
Vee = MIN
Vil =O.BV
VIH=2V
0.5
V
VOH
10Zl
High-Level Output Voltage
2
Vee=MIN
Vil =O.BV
VIH=2V
Off-State Output Current
Vee = MAX
Vil =O.BV
VIH=2V
Output Short-Circuit Current'
Vee=5.0V
10ZH
los
O.B
MIL
10l =12 mA
COM
10l =24mA
MIL
IOH=-2mA
COM
IOH=-3.2mA
2.4
V
-100
Vo=O.4V
Vo=2.4V
-30
Vo=OV
V
V
Supply Current
Vee = MAX
Icc
'No more than one output should be shorted at a time and duration of the short·circuit should not exceed one second
t All typical values are Vcc=5V, TA=25'C.
120
p.A
100
p.A
-130
mA
lBO
mA
Switching Characteristics Over Operating Conditions
Symbol
Parameter
Test Conditions
(See Test Load/Waveforms)
Commercial
Military
Min
Typ
Max
35
Min
Units
Typ
Max
60
35
50
ns
20
35
20
30
ns
55
95
55
BO
ns
fMAX
Maximum Clock Frequency
tpo
CBI to CBO Delay
10.5
tpo
Clock to Q
tpo
ClocktoCBO
tpzx
Output Enable Delay
20
45
20
35
ns
tpxz
Output Disable Delay
20
45
20
35
ns
Cl =50pF
R1=200n
R2=390n
2-447
12.5
MHz
•
~
~
~
Logic Diagram
LS469
CK~l~
__________________________,
j] =.2-t:!t:::=~
2! vcc
r-------------+-----~m
DO,!3-----r-~+=::t=D---1
TL/L/B333-2
2·448
~National
~ Semiconductor
DM54LS469A/DM74LS469A 8-Bit Up/Down Counter
General Description
The 'LS469A is an a-bit synchronous up/down counter with
parallel load and hold capability. Three function-select inputs (LD, UD, CBI) provide one of four operations which
occur synchronously on the rising edge of the clock (CK).
The LOAD operation loads the inputs (D7-DO) into the output register (07-00). The HOLD operation holds the previous value regardless of clock transitions. The INCREMENT
operation adds one to the output register when the carry-in
input is TRUE (CBI = LOW), otherwise the operation is a
HOLD. The carry-out (CBO) is True (CBO = LOW) when
the output register (07-00) is all HIGHs, otherwise FALSE
(CBO = HIGH). The DECREMENT operation subtracts one
from the output register when the borrow-in input is TRUE
(CBI = LOW), otherwise the operation is a HOLD. The borrow-out (CBO) is true (CBO = LOW) when the output register (07-00) is all LOWs, otherwise FALSE (CBO = HIGH).
The output register (07-00) is enabled when OE is LOW,
and disabled (HI-Z) when OE is HIGH. The output drivers
will sink the 24 mA required for many bus-interface standards. Two or more 'LS469A octal up/down counters may
be cascaded to provide larger counters.
Features
• Octal Register for general purpose interfacing
applications
• a bits match byte boundaries
• Low current PNP inputs reduce loading
• Bus-structured pinout
• TRI-STATEIlil outputs
• 24-pin SKINNYDIP saves space
Connection Diagram
Top View
m
CBi
OATA
CARRYI
CARRYI
OUT
BORROW
BORROW
Vee IN ·'"00--01---........
--- OUT DE
06- -07'
02 03 04- -05
.
'1~4
23
22
00
01
02
-<: CBI
-
CK
-<:
~~
01
02
03 04
8-BIT
UPIDOWN
COUNTER
03
04
05
06
07
CBO
po
DEp-05
06
~~ po
OATA
IN
TLlLl10223-1
Order Number OM54LS469AJ, OM74LS469AJ, OM74LS469AN or OM74LS469AV
See NS Package Number J24F, N24C or V28A
Function Table
OE CK LO UO CSI 07-00
H
L
L
L
L
L
X
t
t
t
t
t
X
L
H
H
H
H
X
X
L
L
H
H
X
X
H
L
H
L
X
D
X
X
X
X
2-449
07-00
Operation
Z
HI-Z
D
LOAD
HOLD
0
o Plus 1 INCREMENT
HOLD
0
o Minus 1 DECREMENT
•
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vee>
Input Voltage
Off-State Output Voltage
Storage Temperature
ESO Tolerance
Czap = 100 pF
Rzap = 1500
Test Method: Human Body Model
Test Specification: NSC SOP 5-028
7V
5.5V
>1000V
5.5V
-65·Cto
+ 150·C
Recommended Operating Conditions
Symbol
Military
Parameter
Min
Commercial
Max
4.75
5
5.25
V
0
25
75
·C
Max
Min
5.5
Vee
Supply Voltage
4.5
5
TA
Operating Free-Air Temperature
-55
25
Te
Operating Case Temperature
Units
Typ
Typ
·C
125
Electrical Characteristics Series 24A Over Recommended Operating Temperature Range
Symbol
Parameter
Test Conditions
VIH
High Level Input Voltage
(Note 2)
Vil
Low Level Input Voltage
(Note 2)
Min
Vie
Input Clamp Voltage
Vee = Min. II = -18 mA
High Level Output Voltage
Vee = Min
Vil = 0.8V
VIH = 2V
IOH=-2mA
MIL
10H = -3.2mA
COM
Vee = Min
Vil = 0.8V
VIH = 2V
10l = 12mA
MIL
10l = 24mA
COM
Off-State Output Current
(Note 3)
Vee = Max
Vil = 0.8V
VIH = 2V
II
Maximum Input Current
IIH
High Level Input Current (Note 3)
III
Low Level Input Current (Note 3)
Vee = Max. VI = O.4V
los
Output Short-Circuit Current
Vee = 5V
Ice
Supply Current
Vee = Max
10ZH
10Zl
Low Level Output Voltage
Max
2.4
Units
V
-0.8
VOH
VOL
Typ
2
0.8
V
-1.5
V
2.9
V
0.5
V
Vo = 2.4V
100
p.A
Vo = 0.4V
-100
p.A
Vee = Max. VI = 5.5V
1
mA
Vee = Max. VI = 2.4V
25
fJ-A
-0.04
-0.25
mA
-70
-130
mA
135
180
mA
Vo = OV (Note 4)
0.3
-30
Note 1: Absolute maximum ratings are those values beyond which the device may be permanently damaged. They do not mean that the device maybe operated at
these values.
Note 2: These are absolute voltages with respect to the ground pin on the device and include all overshoots due to system andlor tester noise. Do not attempt to
test these values without suHable equipment.
Note 3: 1/0 leakage as the worst case 01 10ZX or IIX. e.g .• IlL and 10ZL
Note 4: During los measurement. only one output at a time should be grounded. Permanent damage otherwise may result.
2-450
Switching Characteristics Over Recommended Operating Conditions
Symbol
Parameter
Is
Set-Up Time from Input
tw
Width of Clock
l High
I Low
Commercial
Military
Test Conditions
Min
Typ
40
20
Max
Units
Min
Typ
30
20
ns
ns
20
7
15
7
35
15
25
15
Max
ns
tpd
CBI to CBO Delay
CL = 50pF
23
35
23
30
ns
!elk
Clock to Output
CL = 50pF
10
25
10
15
ns
tpzx
Output Enable Delay
CL=50pF
19
35
19
30
ns
tpzx
Output Disable Delay
CL = 5pF
15
35
15
30
ns
tH
Hold Time
f max
Maximum Frequency
Test Load
-15
0
-15
ns
15.3
32
22.2
32
MHz
Schematic of Inputs and Outputs
"=i1
EQUIVALENT INPUT
MIL
RI ~ 390
R2 ~ 750
DUTPUT
Tel
COM'L
RI ~ 200
R2 ~ 390
TYPICAL OUTPUT
-----
Vee
R,
~
0
Vee
BkQ NOM
..OC HOM
~
H2
.....
-=
--
(~
......
INPUT
~
,.
TUUI0223-2
'"~
~
....(
~
--
~,.
"ll'o.
Test Waveforms
.".
3V
ClOCK
-:~
----
Set-Up and Hold
.".
TLiL/I0223-3
. ; (Vi (SEE NOTE AI
INPUT
OV
~~n~
-
Pulse Width
3V
DATA
HIGH·LEVEL
I '"
"'I'\,
C
'" I"
PULSE
INPUT
OV
TL/L/l0223-4
LOW·lEVEL
'"
PULSE
Propagation Delay
,NPUT
"'\..
..,1"",
I-,,"L.
OUT OF PHASE
OUTPUT
TULI1 0223-6
3V
--.J~'"
1-"".
IN·PHASE
OUTPUT
OUTPUT
~~
OV
'''L-
~
"'~~
.-
Enable and Disable
...
Yo.
ENABLE
IEN'BLE PIN OR 'NPUT)
YoL
Yo.
NORMAL~~~~~
VOL
I
VOH
151 OPEN)
Z
NORMALLY LOW
Z
1m
-,
TLlL/l0223-5
Note A: VT ~ 1.5V.
Note B: CL Includes probe and jig capacitance.
Note C: In the examples above, the phase relationships between inputs and
outputs have been chosen arbitrarily.
OUTPUT
(51 CLOSED)
~
~
1:'~~
~
''''
VOL--
1.5V
UV
I,,"z-
''''
i~05V
i-;lL:I05V
I
TLlL110223-7
2-451
~
~
Logic Diagram
~
8-Bit Up/Down Counter
CK~l-D
____________________________1
2! vcc
ITi~2-t:::!t::=::::l
TL/L/l0223-8
2-452
~National
~ Semiconductor
54LS490/DM74LS490
Dual Decade Counter
General Description
Features
The 'LS490 contains a pair of high speed 4-stage ripple
counters. Each half of the 'LS490 has individual Clock, Master Reset and Master Set (Preset 9) Inputs. Each section
counts in the 8421 BCD code.
• Dual version of 54LS174LS90
• Individual asynchronous clear and preset to 9 for each
counter
• Count frequency-typically 65 MHz
• Input clamp diodes limit high speed termination effects
• TIL and CMOS compatible
Connection Diagram
Dual-In-Llne Package
CPa- 1
\......I
MRa- 2.
16 r-Vcc
15 r-CPb
QOa- 3
14 r-MRb
MSa- 4
13 r-QOb
Qla- 5
12. -t.tSb
Q2.a- 6
11 -Qlb
Q3a- 7
10 -Q2.b
GND- 8
9 -Q3b
TL/F/l01BB-l
Order Number 54LS490DMQB, 54LS490FMQB, DM54LS490M or DM54LS490N
See NS Package Number J16A, M16A, N16E or W16A
Pin Names
MS
MR
CP
00-03
Description
Master Set (Set to 9) Input (Active HIGH)
Master Reset Input (Active HIGH)
Clock Pulse Input (Active Falling Edge)
Counter Outputs
•
2-453
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and speclflcatlons_
Supply Voltage
7V
Input Voltage
7V
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Operating Free Air Temperature Range
54LS
- 55·C to + 125·C
DM74LS
O·Cto +70"C
Storage Temperature Range
-65·Cto + 150·C
Recommended Operating Conditions
Symbol
54LS490
Parameter
Vee
Supply V.ltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
10H
High Level Output Current
DM74LS490
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
2
V
V
0.7
0.8
V
-0.4
-0.4
mA
8
mA
70
·C
10L
Low Level Output Current
TA
Free Air Operating Temperature
-55
tw(L)
CP Pulse Width LOW
12.5
12.5
ns
tw(H)
MR, MS Pulse Width HIGH
20
20
ns
tree
Recovery Time, MR or MS to CP
15
15
ns
4
125
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 1)
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vee = Min, 11= -18 mA
VOH
High Level Output
Voltage
Vee = Min, 10H = Max,
VIL = Max
Low Level Output
Voltage
Vee = Min, 10L = Max,
VIH = Min
54LS
0.4
DM74
0.5
10L = 4 mA, Vee = Min
DM74
0.4
VOL
II
IIH
IlL
los
= Max, VI =
Input Current @ Max
Input Voltage
Vee
High Level Input Current
Vee = Max, VI = 2.7V
Low Level Input Current
Short Circuit
Output Current
Vee
= Max, VI =
10V
0.4V
Vee = Max
(Note 2)
54LS
2.5
DM74
2.7
Inputs
100
CP
200
Inputs
20
CP
40
Inputs
-0.03
-0.4
Gil
-0.18
-2.4
54LS
-20
-100
DM74
-20
-100
Supply Current
Vee = Max
Iyplcels are at Vex; = SV, TA = 2S·C.
Nole 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Icc
Note 1: All
2-454
V
26
V
/LA
/LA
mA
mA
mA
r-
C/)
Switching Characteristics
Vee =
+ 5.0V, TA
olio
CO
+ 25'C (See Section 1 for test waveforms and output load)
=
Symbol
RL
Parameter
C)
= 2 kO, CL = 15pF
MIn
UnIts
Max
f max
Maximum Clock Frequency
tpLH
tpHL
Propagation Delay
CPtoOO
15
15
ns
tpLH
tpHL
Propagation Delay
CPtoOlor03
30
30
ns
tpLH
tpHL
Propagation Delay
CP to 02
45
45
ns
tpLH
tpHL
Propagation Delay
MS to On
35
35
ns
tpHL
Propagation Delay
MRtoOn
39
ns
Logic Diagram
MHz
40
(one-half shown)
lotS
CP--------,
IotR
QO
Ql
Q2
Q3
TLlF/101BB-4
State Diagram
Logic Symbol
4,12
lotS
1,15
CP
t.lR QO Ql Q2 Q3
2,14
5,11
3,13
7,9
TLlF/101BB-3
6,10
TL/F/101B8-2
Vee = Pin 16
GND = Pin 8
2-455
•
...
r---------------------------------------------------------------------------~
~ '?A National
~ Semiconductor
DM54LS491/74LS491 10-Bit Counter
General Description
Features/Benefits
The ten-bit counter can count up, count down, set, and load
2 LSB's, 2 MSB's and 6 middle bits high or low as a group.
All operations are synchronous with the clock. SET overrides LOAD, COUNT and HOLD. LOAD overrides COUNT.
COUNT is conditional on CIN, otherwise it holds.
All outputs are enabled when OE is low, otherwise HIGH-Z.
The 24 mA IOL outputs are suitable for driving RAM/PROM
address lines in video graphics systems.
•
•
•
•
•
Connection Diagram
Standard Test Load
CRT vertical and horizontal timing generation
Bus-structured pinout
24-pin SKINNYDIP saves space
TRI-STATE" outputs drive bus lines
Low current PNP inputs reduce loading
SI
5V-7o-
Top View
DATA
OUT
Vee / QO
[24
23
Ql
Q2
22
21
Q3
20
Q4
19
Rl
Q5
Q6
18
07
17
08
16
Q9 \
15
14
1m
OUTPUT-......-
13
..LCL
J
r-
III-BIT
COUNTER
CK
00
01 02-07 08
09
LO CNT UP
CK \ 00
01 02-07 08
09 , til
9
C'RT lIP
SET CIN
10
II.r2
SET ~ GNO
OATA
IN
TL/Ll8332-1
Order Number OM54LS491J,
OM74LS491J or OM74LS491N
See NS Package Number J24F or N24C
Function Table
IcE CK SET LO CNT CIN UP 09·00
H X
L
L
L
L
L
L
t
t
t
t
t
t
X
H
L
L
L
L
L
X
X
L
H
H
H
H
X
X
X
H
L
L
L
X
X
X
X
H
L
L
X
X
X
X
X
L
H
X
X
D
X
X
X
X
2-456
09·00
Operation
Z
Hi-Z
Set all HIGH
H
LOADD
D
HOLD
Q
Q
HOLD
Qplus 1 Count UP
Q minus 1 CountDN
.....
R2
~
TL/L/8332-2
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage Vee
Input Voltage
Off-State Output Voltage
5.5V
-65· to
Storage Temperature
+ 150·C
7V
5.5V
Operating Conditions
Symbol
Military
Parameter
Min
Typ
5
Vee
Supply Voltage
4.5
TA
Operating Free-Air Temperature
-55
tw
Width of Clock
I
I
Commercial
Min
Typ
Max
5.5
4.75
5
5.25
V
125"
0
75
·C
High
40
40
Low
35
35
tsu
Set-UpTime
60
th
Hold Time
0
Units
Max
ns
50
-15
ns
0
-15
Min
Typt
• Case temperature
Electrical Characteristics Over Operating Conditions
Symbol
Parameter
V,l
Low-Level Input Voltage
V,H
High-Level Input Voltage
V'c
Input Clamp Voltage
Test Conditions
Max
Units
0.8
V
V
2
Vee = MIN
1,=-18mA
-1.5
V
mA
I,l
Low-Level Input Current
Vee = MAX
V,=O.4V
-0.25
I'H
High-Level Input Current
Vee = MAX
V, = 2.4V
25
/LA
I,
Maximum Input Current
Vee = MAX
V,=5.5V
1
mA
VOL
Low-Level Output Voltage
Vee = MIN
V,l =0.8V
V'H=2V
0.5
V
VOH
IOZl
High-Level Output Voltage
Off-State Output Current
IOZH
Vee=MIN
V,l =0.8V
V'H=2V
Output Short-Circuit Current·
Vee=5.0V
Icc
Supply Current
Vee=MAX
• No more than one output should be shorted at a time and duration of the
All typical values are at Vcc~5V.
IOl =12mA
COM
IOl =24mA
MIL
IOH= -2 mA
COM
IOH=3.2mA
Vee = MAX
V,l =0.8V
V'H=2V
los
t
MIL
V
2.4
Vo=O.4V
-100
Vo=2.4V
100
J.'A
-130
mA
180
mA
-30
Vo=OV
120
short~circuit
/LA
should not exceed one second.
TA~25'C
Switching Characteristics Over Operating Conditions
Symbol
Parameter
fMAX
Maximum Clock Frequency
tpo
ClocktoQ
tpzx
Output Enable Delay
tpxz
Output Disable Delay
Test Conditions
(See Test Load)
Commercial
Military
Min
Typ
Max
Rl=200n
R2=390n
2-457
Typ
Units
Max
12.5
10.5
Cl=50pF
Min
MHz
20
35
20
30
ns
35
55
35
45
ns
35
55
35
45
ns
Logic Diagram
10-Blt Up/Down Counter
TLlL/8332-3
2-458
~National
~ Semiconductor
DM54LS491 A/DM7 4LS491A
10-Bit Counter
General Description
Features
The ten-bit counter can count up, count down, set, and load
2 LSB's, 2 MSB's and 6 middle bits high or low as a group.
All operations are synchronous with the clock. SET overrides LOAD, COUNT and HOLD. LOAD overrides COUNT.
COUNT is conditional on CIN, otherwise it holds.
•
•
•
•
•
CRT vertical and horizontal timing generation
Bus-structured pinout
Low current PNP inputs reduce loading
TRI-STATE® outputs
24-pin SKINNYDIP saves space
All outputs are enabled when OE is low, otherwise HIGH-Z.
The 24 mA IOL outputs are suitable for driving RAM/PROM
address lines in video graphics systems.
Connection Diagram
~'OO
I~
H
~
~
n
~
~
~
~
~
a
~
~
~
IT
~
a
~\~
~
10·BIT
COUNTER
-I>CK
00
01 02-07 08
CK \ 00
01 02-07 DB
U
OE 0-
09
LO
CNT UP SET CIN
09 ,
III Cfll' UP
9
.
N
10
SET
11 J..12
lriii
GNO
OATA
IN
TUL/l0222-1
Order Number DM54LS491AJ, OM74LS491AJ, DM74LS491AN or OM74LS491AV
See NS Package Number J24F, N24C or V28A
Function Table
OE
CK
H
L
L
L
L
L
L
SET
LO
CNT
CIN
UP
09-00
Q9-QO
Operation
X
X
t
t
t
t
t
t
H
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Z
H
D
Q
Q
Q Plus 1
QMinus 1
Hi-Z
Set all HIGH
LOADD
HOLD
HOLD
Count Up
CountDown
L
H
H
H
H
H
L
L
L
H
L
L
L
H
2-459
D
X
X
X
X
PI
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage, Vee
ESO Tolerance
Czap = 100 pF
Rzap = 15000
Test Method: Human Body Model
Test Specification: NSC SOP 5-028
7V
Input Voltage
Off-State Output Voltage
Storage Temperature
5.5V
>1000V
5.5V
+ 150'C
- 65'C to
Recommended Operating Conditions
Symbol
Military
Parameter
Commercial
Units
Min
Typ
Max
Min
Typ
Max
5.5
4.75
5
5.25
V
a
25
75
'C
Vee
Supply Voltage
4.5
5
TA
Operating Free-AirTemperature
-55
25
Te
Operating Case Temperature
125
'C
Electrical Characteristics Series 24A Over Recommended Operating Temperature Range
Symbol
VIH
Parameter
High Level Input Voltage
Conditions
Low Level Input Voltage
(Note 2)
Vie
Input Clamp Voltage
Vee
VOH
High Level Output Voltage
Vee = Min
Vil = 0.8V
VIH = 2V
IOH
Vee = Min
Vil = 0.8V
VIH = 2V
IOl
Off-State Output Current
(Note 3)
Vee = Max
Vil = 0.8V
VIH = 2V
Vo
IOZH
10Zl
Low Level Output Voltage
=
Min,lI
Typ
Max
2
Vil
VOL
Min
(Note 2)
=
IOH
IOl
Vo
=
=
-2mA
-3.2mA
V
-0.8
-18 mA
Units
0.8
V
-1.5
V
MIL
COM
=
=
12mA
MIL
24mA
COM
=
=
2.4
2.9
0.3
V
0.5
V
2.4V
100
p.A
O.4V
-100
p.A
II
Maximum Input Current
Vee
1
mA
Vee
Max, VI
=
=
5.5V
High Level Input Current
(Note 3)
=
=
Max, VI
IIH
2.4V
25
p.A
III
Low Level Input Current
(Note 3)
Vee
=
Max, VI
=
0.4V
-0.04
-0.25
mA
los
Outut Short-Circuit Current
Vee
-70
-130
mA
lee
=
=
5V
Supply Current
135
180
mA
Vee
Vo
=
OV (Note 4)
-30
Max
Note 1: Absolute maximum ratings are those values beyond which the device may be permanently damaged. They do not mean that the device may be operated at
these values.
Note 2: These are absolute voltages with respect to the ground pin on the device and include all overshoots due to system andlor tester noise. Do not attempt to
test these values without suitable equipment.
Note 3: 1/0 leakage as the worst case of 10ZX or IIX, e.g., IlL and 10Zl.
Note 4: During los measurement, only one output at a time should be grounded. Permanent damage otherwise may result.
2-460
Switching Characteristics Over Recommended Operating Conditions
Parameter
Symbol
ts
Setup Time from Input
tw
Width of Clock
I
I
Commercial
Military
Test Condition
Min
Typ
Max
Min
Typ
Units
Max
40
20
30
20
ns
High
20
7
15
7
ns
low
35
15
25
15
ns
0
-15
0
-15
ns
tH
Hold Time
tClK
Clock to Output
CL = 50pF
10
25
10
15
ns
tpzx
Output Enable Delay
CL = 50pF
19
35
19
30
ns
tpxz
Output Disable Delay
CL = 5pF
15
35
15
30
fMAX
Maximum Frequency
15.3
Test Load
32
MHz
Schematic of Inputs and Outputs
.~
Tel
MIL
Rl = 390
R2 = 750
Rt
COM'L
Rl = 200
R2 = 390
EQU1VAlEIH INPUT
Vee
f'rPiCAlOUTPUl'
-----
vee
40Q HOM
8kQ NOM
OUTPUT
HZ
':"
ns
32
22.2
....
INPUT
r-f.... ~
"
':"
--
P"
TLlLlI0222-2
~
~~:
~,
--
wn
--
"'U
OUTPUT
u...
-:~
----
.".
.".
TL/L/l0222-3
Test Waveforms
-
Set-up and Hold
CLOCK
INPUT
DATA
INPUT
~Vt
Pulse Width
3V
HIGH-lEVEL
PULSE
(SEE NOTE AI
""·'R"·
V~I\.
Vr
Vr
c
OV
lOW·lEVEL
3V
Vr
PULSE
DV
TLlL/l0222-4
It'
TLlLlI0222-S
Enable and Disable
v"
ENABLE
(ENABLE PIN OR INPUTI 1.5V
J!<
x:::
I
VoL
---:~
Nole A: VT = 1.SV.
OUTPUT
Nole B: CL includes probe and Jig capacitance.
Nole B: tn the examples above, the phase relationships between inputs and
outputs have been chosen arbitrarily.
IS1 OPEN)
z
NORMALLY LOW
z
OUTPUT
(St CLOSED)
'ZH-
----,- 1.IV
~,.SV
I,ZL
VoL--
j
I""
I,U
I~05V
~D5V
---r
TL/L/l0222-6
2-461
c(
....
~
~
Logic Diagram
10-Bit Up/Down Counter
CK!...J>-----:-==-:-----,
TLlL/10222-7
2-462
~National
~ Semiconductor
DM54LS498/DM74LS498 Octal Shift Register
General Description
The LS498 is an 8-bit synchronous shift register with parallel
load and hold capability. Two function select inputs (la, 11)
provide one of four operations which occur synchronously
on the rising edge of the clock (CK).
The LOAD operation loads the input (D7-DO) into the output register (07-00)' The HOLD operation holds the previous value regardless of clock transitions. The SHIFT LEFT
operation shifts the output register, 0, one bit to the left; 00
is replaced by L1RO. RILO outputs 07.
The SHIFT RIGHT operation shifts the output register, 0,
one bit to the right; 07 is replaced by RILO. L1RO outputs
00·
The output register (07-00)-is enabled when OE is LOW,
and disabled (HI-Z) when OE is HIGH. The output drivers
will sink the 24 mA required for many bus interface standards.
Connection Diagram
Two or more LS498 octal shift registers may be cascaded to
provide larger shift registers as shown in the application
section.
Features/Benefits
• Octal shift register for serial to parallel and parallel to
serial applications
• 8 bits match byte boundaries
• Bus-structured pinout
• 24-pin SKINNYDIP saves space
• TRI-STATE® outputs drive bus lines
• Low current PNP inputs reduce loading
• Expandable in 8-bit increments
Standard Test Load
Top View
LlRD
SHIFT
vfC
DATA
110 '00
I~
~
01
~
u
00
02
01
03
~
02
I - LlRO
I.
00
04
~
03
05
a
04
"
05
01
02
03
04
a
06
10
a
~
M
DUTPUT -
07
RILO t-
05
t, ~.
....- - .
TLlLIB331-2
DEle>-lIt07
06
9
CK
Rl
07' 110 ll!'
06
8·BIT
SHIFT
REGISTER
,....--!>CK
r-
RILO
SHIFT
D~T
10
11 .112
",00:...-;;.;01.......;0;;,2.....;;03;....,..;0:;.,;4-.,;;0;;.,5....;;.;06.......;0",7, 11
OATA
GNO
IN
TLlL18331-1
Order Number DM54LS498J,
DM74LS498J or DM74LS498N
See NS Package Number J24F or N24C
Function Table
OE
CK
11
10
H
L
L
L
L
X
X
i
i
i
i
L
L
H
H
0 7- 0 0
0 7- 0 0
Operation
X
X
L
H
L
H
X
X
X
Z
L
SR(O)
SL(O)
D
HI-Z
HOLD
SHIFT RIGHT
SHIFT LEFT
LOAD
D
2-463
•
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage Vcc
Input Voltage
Off-State Output Voltage
5.5V
Storage Temperature
-65' to
+ 150'C
7V
5.5V
Operating Conditions
Symbol
Military
Parameter
Min
Typ
5
Vee
Supply Voltage
4.5
TA
Operating Free-Air Temperature
-55
tw
Width of Clock
I
I
Commercial
Min
Typ
Max
5.5
4.75
5
5.25
V
125-
0
75
'C
Low
40
35
High
30
25
tsu
Set-UpTime
60
th
Hold Time
0
Units
Max
ns
50
-15
ns
0
-15
Min
Typt
"Case temperature
Electrical Characteristics Over Operating Conditions
Symbol
Parameter
Test Conditions
Max
Units
0.8
V
11=-18mA
-1.5
V
Vcc=MAX
VI=O.4V
-0.25
mA
Vcc=MAX
VI=2.4V
25
p,A
Maximum Input Current
Vcc=MAX
VI=5.5V
1
mA
Low-Level Output Voltage
Vcc=MIN
Vil =0.8V
VIH=2V
0.5
V
Vil
Low-Level Input Voltage
VIH
High-Level Input Voltage
VIC
Input Clamp Voltage
Vee = MIN
III
Low-Level Input Current
IIH
High-Level Input Current
II
VOL
VOH
10Zl
High-Level Output Voltage
Off-State Output Current
10ZH
2
Vcc=MIN
Vil =0.8V
VIH=2V
MIL
IOl=12mA
COM
IOl=24mA
MIL
10H= -2 mA
COM
IOH=-3.2mA
Vcc=MAX
Vil =0.8V
VIH=2V
los
Output Short-Circuit Current'
Vcc=5.0V
Icc
Supply Current
Vcc=MAX
V
2.4
V
-100
Vo=0.4V
VO=2.4V
-30
Vo=OV
120
p,A
100
p,A
-130
mA
180
mA
-No more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
tAli typical values are at Vcc=5V, TA=25'C
Switching Characteristics Over Operating Conditions
Symbol
Parameter
Test Conditions
(See Test Load)
Military
Min
Commercial
Typ
Max
35
Units
Typ
Max
60
35
50
ns
20
35
20
30
ns
55
95
55
80
ns
10.5
Min
fMAX
Maximum Clock Frequency
tpo
10, 11 to lIRO, RILO
tpo
Clock to Q
tpo
Clock to lIRO, RILO
tpzx
Output Enable Delay
35
55
35
45
ns
tpxz
Output Disable Delay
35
55
35
45
ns
Cl =50pF
Rl=200n
R2=390n
2-464
12.5
MHz
Logic Diagram
Octal Shift Register
CK~1-t>_----------------------,
-2.! vcc
.----------------+------[>_-1r-"'-23 lIRO
oo.iJ-----1FFFf$==1D
~-[>_-_2~2 00
01.!4--------!FF1=f=!=D
OJ!B-----1FFFf=!=D
04!.7--------!~~F=D
05.! B____----!~~=I=D
DB 9
16 06
D7 10
15 Q7
+1>__
L -__________________
•
..,....~14 RlLO
TLiL/8331-3
2-465
~National
~ Semiconductor
DM54LS498A/DM74LS498A
Octal Shift Register
General Description
The LS498A is an 8-bit synchronous shift register with parallel load and hold capability. Two function-select inputs (10.
11) provide one of four operations which occur synchronouslyon the rising edge of the clock (CK).
The LOAD operation loads the inputs (07-00) into the output register (07-00). The HOLD operation holds the previous value regardless of clock transitions. The SHIFT LEFT
operation shifts the output register O. one bit to the left; 00
is replaced by LIRa. LIRa outputs 00.
The output register (07-00)-is enabled when OE is LOW.
and disabled (HI-Z) when DE is HIGH. The output drivers
will sink the 24 rnA required for many bus interface standards.
Connection Diagram
Two or more LS498 octal shift registers may be cascaded to
provide larger shift registers as shown in the application.
Features
• Octal shift register for serial to parallel and parallel to
serial applications
• 8 bits match byte boundaries
• Low current PNP inputs reduce loading
• Bus-structured pinout
• TRI-STATE@ outputs
• 24-pin SKINNYOIP saves space
• Expandable in 8-bit increments
Function Table
OE
CK
11
10
07-00
07-00
Operation
H
L
L
L
L
X
X
X
t
t
t
t
L
L
H
H
L
H
L
H
X
X
X
X
Z
L
SR(O)
SL(O)
0
HI-Z
HOLD
SHIFT RIGHT
SHIFT LEFT
LOAD
Top View
vr
24
DATA
URO
SHIFT
110 'aD
23
...--
r-
1
CK
2
la
Q3
a2
al
22
aD
I-
RILO
O~T
21
al
20
a2
URO
02
4
3
01
19
a3
18
a4
a7'
a6
17
a5
16
as
5
02
6
03
7
04
ill
14
13
a7
I-
OEP--
I,I05
Q4
Q3
s~r
15
RILO
8·BIT
SHIFT
REOISTER
CK
la
00 01
,DO
a5
Q4
8
05
06
07
9
06
10
07,
11
I,
J
12
GNO
DATA
IN
TUUI0221-1
Order Number OM54LS498AJ. OM74LS498AJ.
OM74LS498AN or OM74LS498AV
See NS Package Number J24F. N24C or V28A
2-466
0
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage Vee
7V
Input Voltage
5.5V
Off-State Output Voltage
5.5V
Storage Temperature
ESD Tolerance
Czap = 100 pF
Rzap = 15000
Test Method: Human Body Model
Test Specification: NSC SOP 5-028
-65· to
+ 150·C
>1000V
Recommended Operating Conditions
Symbol
Military
Parameter
Min
Commercial
Max
4.75
5
5.25
V
0
25
75
·C
Max
Min
5.5
Vee
Supply Voltage
4.5
5
TA
Operating Free-Air Temperature
-55
25
Te
Operating Case Temperature
Units
Typ
Typ
·C
125
Electrical Characteristics Series 24A Over Recommended Operating Temperature Range
Symbol
Parameter
Test Conditions
VIH
High Level Input Voltage
(Note 2)
VIL
Low Level Input Voltage
(Note 2)
Vie
Input Clamp Voltage
Vee
VOH
High Level Output Voltage
Vee = Min
VIL = 0.8V
VIH = 2V
IOH=-2mA
Vee = Min
Vil = 0.8V
VIH = 2V
= 12mA
10l = 24mA
Off-State Output Current
(Note 3)
Vee = Max
Vil = 0.8V
VIH = 2V
Vo
II
Maximum Input Current
IIH
High Level Input Current
(Note 3)
= Max, VI = 5.5V
Vee = Max, VI = 2.4V
III
Low Level Input Current
(Note 3)
Vee
= Max, VI = 0.4V
los
Output Short-Circuit Current
Vee
= 5V
VOL
10ZH
10Zl
Low Level Output Voltage
Min
Typ
Max
Units
0.8
V
-1.5
V
V
2
= Min, II = -18 mA
10H
-0.8
MIL
= -3.2 mA COM
2.4
2.9
MIL
10L
0.3
COM
= 2.4V
Vo = 0.4V
= OV (Note 4)
-30
0.5
V
100
p,A
-100
p,A
1
mA
25
p,A
-0.04
-0.25
mA
-70
-130
mA
Vee
Vo
V
Supply Current
135
180
mA
Vee = Max
lee
Nole 1: Absolute maximum ratings are those values beyond which the device may be permanently damaged. They do not mean that the device may be operated at
the.. values.
Nole 2: These are absolute voltages with respect to the ground pin on the device and include all overshoots due to system and/or tester noi... Do not attempt to
test these values without suitable equipment.
Nole 3: I/O leakage as the worst case of 10ZX or IIX, e.g., IlL and 10ZL
Nole 4: During los measuremen~ only one output at a time should be grounded. Permanent damage otherwise may result.
2-467
Switching Characteristics Over Operating Conditions
Symbol
Parameter
Military
Test Conditions
Min
Typ
Commercial
Max
Min
Typ
Units
Max
Ts
Setup Time from Input
40
20
30
20
ns
Tw
Width of Clock
20
7
15
7
ns
TPD
10,11 to LlRO, RILO
TCLK
Clock to Output
Tpzx
Output Enable Delay
Tpx
Output Disable Delay
TH
Hold Time
fMAX
Maximum Frequency
High
Low
35
25
15
ns
23
35
23
30
ns
10
25
10
15
ns
19
35
19
30
ns
15
35
15
30
ns
0
-15
0
-15
ns
15.3
32
22.2
32
MHz
Test Load
Schematic of Inputs and Outputs
.~
EQUIVALENT INPUT
vee
.,
MIL
Rl ~ 390
OUTPUT
R2
~.2
Tel
15
= 50pF
CL = 50pF
CL = 50pF
CL = 5pF
CL
~
750
COM'L
Rl ~ 200
R2
~
TYPICAL OUTPUT
-----
'ee
40Q NOM
BkQ NOM
""
390
INPUT
~
--
(~
~
n
--
TL/L/l0221-2
Test Waveforms
'-.Set-Up and Hold
3V
CLOCK
BV
~~n~·
DATA
INPUT
":"
":"
TUU10221-3
3V
Pulse Width
BV
TUL/l0221-4
.-
HIGH·LEVEL
PULSE
I
"
'PL'·
IN·PHASE
OUTPUT
,,'\,
-'nIL-
~r.,
-'ntl
OUT OF PHASE
OUTPUT
~X'
~
1-"""~
LOW·lEVEL
PULSE
3V
o.
~
,,~,
"
TLlL/l0221-6
'OH
Enable and Disable
'OL
...
ENABLE
(ENABLE"NO.'NPllTi
'OL
TL/L110221-5
Note A: VT
"
G"
Propagation Delay
IHPUT--..J
,:~
.---
fiVT (SEE NOTE A)
INPUT
OUTPUT
VJl'oo
--
~r
n
NORMAl~~:~~~
(S101'£"1
1.5V.
'OH
Ji<
I
VoH I'ZN
NORMALLY LOW
OUTPUT
(81 CLOSEDI
1.5V
Z
------r
Z
----1. 1.IY
Note B: CL includes probe and jig capacitance.
Note C: In the examples above, the phase relationships between inputs and
outputs have been chosen arbitrarily.
~
'v~~~
"lL
Yol--
''''' I~O"
"',
1-jL:I0 ..
----r
TL/LI1 0221-7
2-468
Logic Diagram
Octal Shift Register
CK~'-C>---------------------~
-1! vcc
1,12-ti:=fi~~::~:~=========t=====~I>-__~23 URD
---*4:$$=$::[)
D'o!..'
D2.!5----4=t=1~~::[)
--4:$$1=$::[)
031.6
D,17_ _~$$$==t)
DS!B--4=t=1$$::[)
.7 05
D6l9--4=t=1~~::[)
'---------------i-D..........,.-"'14 RILO
'3 n
.2
~
TL/LII 0221-8
2-469
~
!j
J?'A National
~ Semiconductor
54LS502/DM74LS502
8-Bit Successive Approximation Register
General Description
The LS502 is an B-bit register with the interstage logic necessary to perform serial-to-parallel conversion and provide
an active LOW Conversion Complete (CC) signal coincident
with storage of the eighth bit. An active LOW Start (5) input
performs synchronous initialization which forces 07 LOW
and all other outputs HIGH. Subsequent clocks shift this 07
LOW signal downstream which simultaneously backfills the
register such that the first serial data (D input) bit is stored in
07, the second bit in 06, the third in 05, etc. The serial
input data is also synchronized by an auxiliary flip-flop and
brought out on 00.
Connection Diagram
Designed primarily for use in the successive approximation
technique for analog-to-digital conversion, the LS502 can
also be used as a serial-to-parallel converter ring counter
and as the storage and control element in recursive digital
routines.
Features
• Low power Schottky version of 2502
• Storage and control for successive approximation A to
D conversion
• Performs serial-to-parallel conversion
Logic Symbol
Dual-In-Llne Package
QD- 1
'-'
D
16 I-Vcc
15 I-Q7
cc-
2
QO- 3
10 -CI 5
14 I-Q7
Ql- 4
-s
D- 7
10
9 -CP
GND- 8
CCpo-2
Q7
13 I-Q6
12 I-Q5
11 -Q4
Q2- 5
Q3- 6
QD 1--1
9-CP
Q6 Q5 Q4 Q3 Q2 Ql QO
TL/F/10189-2
vee = Pin 16
GNO = Pin 8
TLlF/10189-1
Order Number 54LS502DMOB, 54LS502FMOB,
.
DM74LS502WM or DM74LS502N
See NS Package Number J16A, M16B, N16E or W16A
Pin
Names
D
5
CP
00
CC
00-07
'07
Description
Serial Data Input
Start Input (Active LOW)
Clock Pulse Input (Active Rising Edge)
Synchronized Serial Data Output
Conversion Complete Output (Active LOW)
Parallel Register Outputs
Complement of 07 Output
2-470
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
54lS
-55'Cto + 125'C
DM74lS
O'Cto +70'C
Storage Temperature Range
-65'Cto + 150'C
Recommended Operating Conditions
Symbol
Vee
Supply Voltage
VIH
High level Input Voltage
VIL
low level Input Voltage
10H
High level Output Current
DM74LS502
54LS502
Parameter
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
0.7
0.8
V
-0.4
-0.4
mA
8
mA
70
'C
2
2
V
10L
low level Output Current
TA
Free Air Operating Temperature
ts(H)
ts(l)
Setup Time HIGH or lOW
StoCP
5
5
5
5
ns
th(H)
th(l)
Hold Time HIGH or lOW
StoCP
5
5
5
5
ns
ts(H)
ts(l)
Setup Time HIGH or lOW
DtoCP
5
5
5
5
ns
th(H)
Hold Time HIGH or lOW
DtoCP
5
5
5
5
ns
CP Pulse Width HIGH or lOW
20
20
20
20
ns
~(l)
tw(H)
twILl
4
-55
125
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
=
=
VI
Input Clamp Voltage
Vee
VOH
High level Output
Voltage
Vee = Min, 10H
VIL = Max
low level Output
Voltage
Vee Min, 10L
VIH = Min
II
Input Current @ Max
Input Voltage
Vee
VOL
10L
Min, II
=
-18 mA
=
Max,
Max,
= 4 mA, Vee = Min
= Max, VI = 10V
=
=
=
IIH
High level Input Current
Vee
IlL
low level Input Current
Vee
los
Short Circuit
Output Current
Max
Vee
(Note 2)
Max, VI
Max, VI
Min
=
=
54lS
2.5
DM74
2.7
Typ
(Note 1)
Max
Units
-1.5
V
V
54lS
0.4
DM74
0.5
DM74
0.4
0.1
V
mA
2.7V
20
p.A
O.4V
-1.2
mA
54lS
-20
-100
DM74
-20
-100
Supply Current
Vee = Max
Icc
Note 1: All typlcals are at Vee = 5V, TA = 25"C.
Note 2: Note more than one output should be shorted at a time, and the duration should not exceed one second.
2·471
65
mA
mA
~
Switching Characteristics Vee = + 5.0V, TA = + 25'C (See Section 1 for test waveforms and output loads)
Symbol
RL
Parameter
= 2kO,CL = 15pF
Min
f max
Maximum Clock Frequency
Units
Max
25
MHz
Propagation Delay
CPtoOnorCC
35
25
ns
Functional Description
The register stages are composed of transparent RS latches arranged in master/slave pairs. The master and slave
latches are enabled separately by non-overlapping complementary signals <1>1 and <1>2 derived internally from the CP
input. Master latches are enabled when CP is LOW and
slave latches are enabled when CP is HIGH. Information is
transferred from master to slave, and thus to the outputs, by
the LOW-to-HIGH transition of CPo
o
START -() S
CLOCK CP
QD -
cc po- CQNVERSION
Q7
Q6 Q5 Q4 Q3 Q2 Ql QO
COMPLrn
Yt-HH-+-+-+-+---
Initializing the register requires a LOW signal on S while
exercising CPo With Sand CP LOW, all master latches are
SET (0 side HIGH). A LOW-to-HIGH CP transition, with S
remaining LOW, then forces the slave latches to the condition wherein 07 is LOW and all other register outputs, including CC, are HIGH. This condition will prevail as long as
S remains LOW, regardless of subsequent CP rising edge.
To start the conversion process, S must return to the HIGH
state. On the next CP rising edge, the information stored in
the serial data input latch is transferred to 00 and 07, while
Q6 is forced to the LOW state. On the rising edge of the
next seven clocks, this LOW signal is shifted downstream,
one bit at a time, while the serial data enters the register
position one bit behind .this LOW Signal, as shown in the
Truth Table. Note that after a serial data bit appears at a
particular output, that register position undergoes no further
changes. After the shifted LOW signal reaches CC, the register is locked up and no further changes can occur until the
register is initialized for the next conversion process.
IISB
DIGITAL
OUTPUT
~
B-BIT D/A CQNVERTER
LSB
~
~
ANALOG INPUT
TLlF/l01S9-4
FIGUREa.
r.s.
Figure a shows a simplified hook-up of a LS502, a D/ A converter and a comparator arranged to convert an analog input voltage into an 8-bit binary number by the successive
approximation technique. Figure b is an idealized graph
showing the various values that the D/A converter output
voltage can assume in the course of the conversion. The
vertical axis is calibrated in fractions of the full-scale output
capability of the D/A converter and the horizontal axis represents the successive states of the Truth Table. At time t1,
Q7 is LOW and 06-QO are HIGH, causing the D/A output
to be one-half of full scale. If the analog input voltage is
greater than this voltage the comparator output (hence the
D input of the LS502) will be LOW, and at times t2 the D/ A
output will rise to three-fourths of full scale because Q7 will
remain LOW and contribute 50% while Q6 is forced LOW
and contributes another 25%. On the other hand, if the analog input voltage is less than one-half of full scale, the comparator output will be HIGH and 07 will go HIGH at 12. Q6
will still be forced LOW at t2, and the D/ A output will decrease to 25% of full scale. Thus with each successive
clock, the D/A output will change by smaller increments.
When the conversion is completed at t9, the binary number
represented by the register outputs will be the numerator of
the fraction n/256, representing the analog input voltage as
a fraction of the full scale output D/ A converter.
7/8
~
3/4
en
::I
2
5/B
:sz
0
~
1/2
,!.
::>
I!:
::>
0
3/8
~
Q
1/4
I/B
TLlF/l01S9-5
FIGUREb.
2-472
Truth Table
Inputs
tJ"ime
Outputs
tn
0
S
OD
07
06
05
04
03
02
01
00
CC
0
1
2
X
07
06
L
H
H
X
X
X
L
07
07
X
H
L
X
H
H
X
H
H
X
H
H
X
H
H
X
H
H
X
H
H
X
H
H
3
4
5
6
06
04
03
02
H
H
H
H
06
05
04
03
07
07
07
07
06
06
06
06
L
05
05
05
H
L
04
04
H
H
L
03
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
7
01
00
H
H
H
H
02
01
00
07
07
07
07
06
06
06
06
05
05
05
05
04
04
04
04
03
03
03
03
02
02
02
02
L
01
01
01
H
L
H
H
L
L
8
9
10
X
X
X
00
00
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Logic Diagram
TL/F/l0189-3
Note: Cell logic is repeated for register stages Q5 to Q1.
2-473
~
Q
,----------------------------------------------------------------------------,
~ ~National
~ Semiconductor
54LS503/DM74LS503
8-Bit Successive Approximation
Register (with Expansion Control)
General Description
Features
The 'LS503 register is basically the same as the 'LS502
except that it has an active LOW Enable (E) input that is
used in cascading two or more packages for longer word
lengths. A HIGH signal on E, after a START operation,
forces 07 HIGH and prevents the device from accepting
serial data. With the E input of an 'LS503 connected to the
CC output of a preceding (more significant) device, the
'LS503 will be inhibited until the preceding device is filled,
causing its CC output to go LOW. This LOW signal then
enables the 'LS503 to accept the serial data on subsequent
clocks. For a description of the starting, shifting and conversion operations, please see the 'LS502 data sheet.
• Performs serial-to-parallel conversion
• Expansion control for longer words
• Storage and control for successive approximation
A to D conversion
• Low power Schottky version of 2503
Connection Diagram
Logic Symbol
Dual·ln·Llne Package
E- 1
'-"
16
15
14
13
12
cc- 2
00010203D-
3
4
5
6
7
I-Vcc
Hi7
1-07
1-06
I~E
10~S
9-CP
1-05
111-04
10 1-5
91-CP
GND- 8
CCo-2
07
06 05 04 03 02 01 QO
TL/F/10190-2
Vee = Pin 16
GND = PinS
TLlF/10190-1
Order Number 54LS503DMQB, 54LS503FMQB,
D74LS503WM or DM74LS503N
See NS Package Number J16A, M16B, N16E or W16A
Pin Names
D
S
CP
E
CC
00-07
07
Description
Serial Data Input
Start Input (Active LOW)
Clock Pulse Input (Active Rising Edge)
Conversion Enable Input (Active LOW)
Conversion Complete Output (Active LOW)
Parallel Register Outputs
Complement of 07 Output
2-474
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
54LS
-55·C to + 125·C
DM74LS
O·Cto +70·C
Storage Temperature Range
- 65·C to + 150·C
Recommended Operating Conditions
Symbol
54LS503
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
IOH
IOL
DM74LS503
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
V
V
2
0.7
0.8
High Level Output Voltage
-0.4
-0.4
mA
Low Level Output Current
4
8
mA
70
·C
-55
V
TA
Free Air Operating Temperature
ts(H)
ts(L)
Setup Time HIGH or LOW
StoCP
5
5
5
5
ns
th (H)
th (L)
Hold Time HIGH or LOW
StoCP
5
5
5
5
ns
ts(H)
ts (L)
Setup Time HIGH or LOW
StoCP
5
5
5
5
ns
th (H)
th (L)
Hold Time HIGH or LOW
DtoCP
5
5
5
5
ns
tw(H)
tw (L)
CP Pulse Width HIGH or LOW
20
20
20
20
ns
125
0
Electrical Characteristics Over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
=
=
VI
Input Clamp Voltage
Vee
VOH
High Level Output Voltage
Vee = Min, 10H
VIL = Max
=
Vee = Min, 10L
VIH = Min
=
VOL
Low Level Output Voltage
Min, II
-18 mA
Max,
Max,
= 4 mA, Vee = Min
Vee = Max, VI = 10V
IOL
II
Input Current @ Max
Input Voltage
=
=
=
IIH
High Level Input Current
Vee
IlL
Low Level Input Current
Vee
los
Short Circuit
Output Current
Vee
Max
(Note 2)
Supply Current
Vee
Icc
Note 1: All typlcals are at Vee
=
Max, VI
Min
=
54LS
2.5
DM74
2.7
Typ
(Note 1)
Max
Units
-1.5
V
V
54LS
0.4
DM74
0.5
DM74
0.4
0.1
2.7V
Max, VI = 0.4V
20
p.A
mA
-20
-100
DM74
-20
-100
65
Max
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
2-475
mA
-0.8
54LS
= SV, TA = 2S·e.
V
mA
mA
~
~
!1
,---------------------------------------------------------------------------------,
Switching Characteristics
Vee
= + 5.0V, TA = + 25°C (See Section
Symbol
1 for Test Waveforms and Output Load)
RL = 2 kO, CL = 15 pF
Parameter
Min
Units
Max
f max
Maximum Count Frequency
tpLH
tpHL
Propagation Delay
CPtoQnorCC
35
25
ns
tpLH
tpHL
Propagation Delay
EtoQ7
20
24
ns
MHz
25
Logic Diagram
CP
-CO'
.2
r----------
TL/F/10190-3
Note: Cell logic is repeated for register stages 05 to 01.
Connection for Longer Word Lengths
cc
MOST SIGNIFICANT
LEAST SIGNIFICANT
TLlF/10190-4
2·476
~National
~ Semiconductor
DM74LS533
Octal Transparent Latch
with TRI-STATE® Outputs
General Description
The 'LS533 consists of eight latches with TRI-STATE outputs for bus organized system applications. The flip-flops
appear transparent to the data when Latch Enable (LE) is
HIGH. When LE is LOW, the data that meets the setup
times is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH the bus output is in
the high impedance state. The 'LS533 is the same as the
'LS373, except that the outputs are inverted. For detailed
Connection Diagram
specifications please see the 'LS373 data sheet, but note
that the propagation delays from data to output are 5.0 ns
longer for the 'LS533 than for the 'LS373.
Features
• Eight latches in a single package
• TRI-STATE outputs for bus interfacing
Logic Symbol
iii i It Ii YIi
Dual-In-Llne Package
OE-l
00-
2
'-../
20 ~Vcc
19 ~07
00- 3
18 r-07
01- 4
17 r-06
0152-
5
16
6
15 ~05
14
~05
03- 8
13
~D4
03-
12 ~04
GNO- 10
11- LE
l-C OE
His
02- 7
9
DO 01 02 03 04 05 06 07
00 01 02 03 04 05 06 07
TL/F/9BII-2
Vee = Pin 20
GND = Pin 10
11 r-LE
TL/F/9Bll-l
Order Number DM74LS533WM or DM74LS533N
See NS Package Number M20B or N20A
Pin Names
00,07
LE
OE
00-07
Description
Data Inputs
Latch Enable Input (Active HIGH)
Output Enable Input (Active LOW)
Complementary TRI-STATE Outputs
2-477
•
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
Input Voltage
Note: The "Absolute Maximum Ratings are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametriC values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
7V
7V
Operating Free Air Temperature Range
DM74LS
Storage Temperature Range
O"Cto +70'C
- 65'C to + 150'C
Recommended Operating Conditions
Symbol
DM74LS533
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
IOH
High Level Output Current
IOl
Low Level Output Current
TA
Free Air Operating Temperature
Units
Min
Nom
Max
4.75
5
5.25
V
2
V
0.8
V
-0.4
mA
24
mA
70
·c
0
Electrical Characteristics
Over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
VI
Input Clamp Voltage
Vee = Min, 11= -18 mA
VOH
High Level Output
Voltage
Vee = Min, IOH = Max,
Vil = Max
DM74
Val
Low Level Output
Voltage
Vee = Min, IOl = Max,
VIH = Min
DM74
10l = 12 mA, Vee = Min
DM74
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 10V
2.7
Typ
(Note 1)
Max
Units
-1.5
V
3.4
0.35
V
0.5
V
0.4
0.1
mA
IIH
High Level Input Current
Vee = Max, VI = 2.7V
20
/LA
IlL
Low Level Input Current
Vee = Max, VI = 0.4V
-0.4
mA
los
Short Circuit
Output Current
Vee = Max
(Note 2)
-100
mA
DM74
-20
leez
Supply Current
Vee = Max
46
mA
10Zl
TRI-STATE Output Off
Current LOW
Vee = VeeH
VOZl = 0.4V
-20.0
p.A
Vee = VeeH
VOZH = 2.7V
20.0
/LA
TRI-STATE Output Off
Current HIGH
Note 1: All typicals are at Vee = 5V, TA = 25"e.
10ZH
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
2-478
Switching Characteristics
Vee = + 5.0V, TA = + 25'C (See Section 1 for waveforms and load configurations)
CL = 15pF
Symbol
Parameter
RL = 2k!l
Min
Units
Max
tpLH
TpHL
Propagation Delay
DatatoQx
32
23
ns
tpLH
tpHL
Propagation Delay
LEtoQx
36
25
ns
tpZL
tpzH
Output Enable Time
OEtoQx
22
2
ns
tpHZ
tpLZ
Output Enable Time
OEtoQx
34
27
ns
2-479
~
,-------------------------------------------------------------------------,
~ ~National
~ Semiconductor
OM74LS534
Octal O-Type Flip-Flop {With TRI-STATE® Outputs}
General Description
The 'LS534 is a high speed, low power octal Ootype flip-flop
featuring separate Ootype inputs for each flip-flop and TRISTATE outputs for bus oriented applications. A buffered
Clock (CP) and Output Enable (OE) is common to all flipflops. The 'LS534 is the same as the 'LS374 except that the
outputs are inverted.
Connection Diagram
Logic Symbol
Dual-In-Llne Package
OE
00
Vee
DO
D7
07
Dl
11
5
16
6
15
05
D2
7
14
D5
4
7
8 13 14 17 18
2
5
6
9 12 15 16 19
CP
OE
D6
D1
02
3
06
OJ
D4
03
04
TL/F/9812-2
vee ~ Pin 20
GND ~ Pin 10
GND
TLlF/9812-1
Order Number DM74LS534WM or DM74LS534N
See NS Package Number M20B or N20A
Pin Name
00-07
CP
OE
00-07
Description
Oata Inputs
Clock Pulse Input (Active Rising Edge)
TRI-STATE Output Enable Input (Active LOW)
Complementary TRI-STATE Outputs
2-480
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
DM74LS
O'Cto +70'C
Storage Temperature Range
-65'Cto + 150'C
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Recommended Operating Conditions
Symbol
DM74LS534
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
VOH
High Level Output Current
Units
Min
Nom
Max
4.75
5
5.25
V
2
V
0.8
V
-2.6
mA
24
mA
70
'C
10L
Low Level Output Current
TA
Free Air Operating Temperature
0
ts(H)
ts (L)
Setup Time HIGH or LOW
Dn toCP
20
20
ns
th (H)
th (L)
Hold Time HIGH or LOW
Dn to CP
0
0
ns
tw(H)
tw(L)
CP Pulse Width HIGH or LOW
15
15
ns
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 1)
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vee = Min, II = -18 mA
VOH
High Level Output
Voltage
Vee = Min, 10H = Max'
VIL = Max VIH = Min
VOL
Low Level Output
Voltage
Vee = Min, 10L = Max
VIL = Max, VIH = Min
0.35
0.5
10L = 12 mA, Vee = Min
0.25
004
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 7V
204
3.3
V
V
0.1
mA
IIH
High Level Input Current
Vee = Max, VI = 2.7V
20
/LA
IlL
Low Level Input Current
Vee = Max, VI = 0.5V
-20
/LA
10ZH
Off-State Output Current
with High Level Output
Voltage Applied
Vee = Max, Vo = 2AV
VIH = Min, VIL = Max
20
/LA
Off-State Output Current
with Low Level Output
Voltage Applied
Vee = Max, Vo = OAV
VIH = Min, VIL = Max
-20
/LA
Short Circuit
Output Current
Vee = Max
(Note 2)
10ZL
los
-20
Vee = Max (Note 3)
Supply Current
Icc
Note 1: All typicals are at Vee ~ SV, TA ~ 2S'C.
Note 2: Not more than one output should be shorted at a time. and the duration should not exceed one second.
Note 3: lee is measured with the DATA inputs grounded and the OUTPUT CONTROLS at 4.5V.
2-481
-100
45
mA
mA
~
C'I)
II')
~
r---------------------------------------------------------------------------------,
Switching Characteristics
= + 5.0V, TA = + 25°C (See Section 1 for test waveforms and output loads)
Vee
Symbol
RL = 2kO,CL = 45pF
Parameter
Min
fmax
tPZH
tpZL
Maximum Clock Frequency
Units
Max
35
MHz
Propagation Delay
CPtoQn
28
28
ns
Output Enable Time
28
28
ns
Output Disable Time
20
25
ns
Functional Description
Truth Table
The '534 consists of eight edge-triggered flip-flops with individual D-type inputs and TRI-STATE true outputs. The buffered clock and buffered Output Enable are common to all
flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold times requirements on the LOW-to-HIGH Clock (CP) transistion. With the
Output Enable (OE) LOW, the contents of the eight flip-flops
are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE
input does not affect the state of the flip-flops.
Inputs
Outputs
Dn
CP
OE
On
H
L
.../
.../
L
H
X
X
L
L
H
Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z
= High Impedance
Logic Diagram
CP
07
TLlF/9812-3
2-482
~National
~ Semiconductor
DM74LS540
Octal Buffer/Line Driver with TRI-STATE® Outputs
General Description
Features
The DM74LS540 is similar in function to the 'LS240, except
that the inputs and outputs are on opposite sides of the
package (see Connection Diagram). This pinout arrangement makes this device especially useful as an output port
for microprocessors, allowing ease of layout and greater PC
board density.
•
•
•
•
Hysteresis at inputs to improve noise margin
PNP inputs reduce loading
TRI-STATE outputs drive bus lines
Inputs and outputs opposite side of package, allowing
easier interface to micropro'cessors
• Fully TTL and CMOS compatible
Connection Diagram
Dual-In-Line Package
E1
Vee
10
E2
11
00
12
01
13
02
14
03
15
04
16
05
17
06
07
TLIFI9813-1
Order Number DM74LS540WM or DM74LS540N
See NS Package Number M20B or N20A
Truth Table
Pin Name
E1,E2
10-7
00-7
Description
Inputs
Output Enable (Active Low)
Data Inputs
Data Outputs
E2
D
L
H
L
H
X
X
X
X
L
H
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
2-483
Outputs
E1
L
L
Z
Z
H
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
Operating Free Air Temperature
DM74LS
7V
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
O'Cto +70'C
-65'Cto + 150'C
Storage Temperature Range
Recommended Operating Conditions
Symbol
DM74LS540
Parameter
Vee
Supply Voltage
Units
Min
Nom
Max
4.75
5
5.25
V
VIH
High Level Input Voltage
Vil
Low Level Input Voltage
O.B
V
V
10H
High Level Output Current
-3
mA
24
mA
70
·c
2
10l
Low Level Output Current
TA
Free Air Operating Temperature
0
Electrical Characteristics
Over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 1)
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vee = Min, 11= -18 mA
VOH
High Level Output
Voltage
Vee = Min, IOH = Max,
Vil = Max
VOL
Low Level Output
Voltage
Vee = Min, 10l ;", Max,
VIH = Min
0.35
0.5
10l = 4 mA, Vee = Min
0.25
0.4
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 10V
2.7
3.4
V
0.1
V
mA
IIH
High Level Input Current
Vee = Max, VI = 2.7V
20
p.A
III
Low Level Input Current
Vee = Max, VI = 0.4V
-0.2
mA
los
Short Circuit
Output Current
Vee = Max
(Note 3)
-225
mA
Icc
Supply Current
Vee = Max
50
mA
10ZH
TRI-STATE Output Off
Current High
Vee = VeeH, VOZH = 2.7V
20
IJ-A
10Zl
TRI-STATE Output Off
Current low
Vee = VeeH, VOZl = 0.4V
-20
IJ-A
Note 1: All typicals are at Vee
-50
= SV, T A = 2S'C.
Note 2: Not more than one output should be shorted at at time, and the duration should not exceed one second.
2-484
Switching Characteristics
at Vee
=
Symbol
5V and T A
=
25'C (See Section 1 or Test Waveforms and Output Loading)
Parameter
Conditions
tpLH
tpHL
Propagation Delay
Data to Output
CL
=
50pF
tPZH
tPZL
Output Enable Time
RL
=
6670, CL
=
tpLZ
tpHZ
Output Disable Time
RL
=
6670,CL
=
'DC limits apply over operating temperature range; AC limits apply at TA =
Min
Max
Units
14
16
ns
50 pF
23
30
ns
50pF
25
16
ns
+ 25' and Vee
=
+ 5.0V.
PI
2-465
f8
!1 ~ National
~ Semiconductor
DM74LS563
Octal D-Type Latch with TRI-STATE® Outputs
General Description
The 'LS563 is a high speed octal latch with buffered common Latch Enable (LE) and buffered common Output Enable (OE) inputs.
This device is functionally indentical to the 'LS573, but has
inverted outputs.
Connection Diagram
Logic Symbol
Dual-In-Llne Package
CiE-l
00- 2
01- 3
02- 4
03- 5
04- 6
05- 7
\.J
iiiiiIii
20 -Vee
19 -00
18 -01
00 01 02 03 04 05 06 07
ll-LE
I~OE
17 1"'"02
16 r03
15 !-04
14 ~05
06- 8
07- 9
13 ~06
GNO- 10
11 !-LE
00 01 02 03 04 05 06 07
TLlF/1D214-2
12 ~07
Vee = Pin 20
GND = Pin 10
TLlF/1D214-1
Order Number DM74LS563WM or DM74LS563N
See NS Package Number M20B or N20A
Pin
Names
00-07
LE
OE
00-07
Description
Data Inputs
Latch Enable Input (Active HIGH)
TRI-STATE Output Enable Input (Active LOW)
TRI-STATE Latch Outputs
2-486
Absolute Maximum Ratings
(Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
OM74LS
Storage Temperature Range
O'Cto +70'C
-65'Cto +150'C
Recommended Operating Conditions
Symbol
DM74LS563
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
10H
High Level Output Current
Units
Min
Nom
Max
4.75
5
5.25
V
2
V
0.8
V
-2.6
mA
24
mA
70
'C
10L
Low Level Output Current
TA
Free Air Operating Temperature
0
ts (H)
ts (L)
Setup Time HIGH or LOW
Onto LE
0
0
ns
th (H)
th (L)
Hold Time HIGH or LOW
Onto LE
10
10
ns
tw(H)
LE Pulse Width
HIGH or LOW
15
15
ns
twILl
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 1)
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vee = Min, 11= -18 mA
VOH
High Level Output Voltage
Vee = Min, 10H = Max,
VIL = Max, VIH = Min
VOL
Low Level Output Voltage
Vee = Min, 10L = Max,
VIL = Max, VIH = Min
0.35
0.5
10L = 12 mA, Vee = Min
0.25
0.4
II
Inpu.t Current
IIH
High Level Input Current
3.3
V
V
Vee = Max, VI = 7V
0.1
mA
Vee = Max, VI = 2.7V
20
",A
IlL
Low Level Input Current
Vee = Max, VI = 0.5V
-20
",A
10ZH
Off-State Output Current with High
Level Output Voltage Applied
Vee = Max, Vo = 2.4V
VIH = Min, VIL = Max
20
",A
10ZL
Off·State Output Current with Low
Level Output Voltage Applied
Vee = Max, Vo = O.4V
VIH = Min, VIL = Max
-20
",A
los
Short Circuit Output Current
Vee = Max
(Note 2)
-100
mA
40
mA
@
Max Input Voltage
2.4
-20
Supply Current
Vee = Max (Note 3)
Icc
NOle 1: All typicals are at Vcc = 5V. TA = 25'C.
Nole 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: icc is measured with the DATA inputs grounded and the OUTPUT CONTROLS at 4.5V.
2-487
Switching Characteristics
Vee
= + 5.0V, TA = + 25°C (See Section 1 for test waveforms and output loading)
Symbol
RL = 2kO
CL = 15pF
Parameter
Min
Units
Max
tpLH
tpHL
Propagation Delay
Onto On
23
25
ns
tpLH
tpHL
Propagation Delay
LE to On
35
35
ns
tPZH
tpZL
Output Enable Time
28
36
ns
tpHZ
tpLZ
Output Disable Time
20
25
ns
Functional Description
puts a setup time preceding the HIGH-to-LOW transition of
LE. The TRI-STATE buffers are controlled by the Output
Enable (OE) input. When OE is LOW, the buffers are in the
bi-state mode. When OE is HIGH the buffers are in the high
impedance mode but this does not interfere with entering
new data into the latches.
The 'LS563 contains eight D-type latches with TRI-STATE
output buffers. When the Latch Enable (LE) input is HIGH,
data on the On inputs enters the latches. In this condition
the latches are transparent, i.e., a latch output will change
state each time its 0 input changes. When LE is LOW the
latches store the information that was present on the 0 in-
Logic Diagram
00
01
02
D3
D4
05
06
07
LE
OE
07
TLlF110214-3
2-488
~National
~ Semiconductor
OM74LS564
Octal O-Type Flip-Flop (with TRI-STATE® Outputs)
General Description
Features
The 'LS564 Is a high speed low power octal flip-flop with a
buffered common Clock (CP) and a buffered common Output Enable (OE). The Information presented to the D Inputs
Is stored In the flip-flops on the LOW-to-HIGH Clock (CP)
transition
This device Is functionally Identical to the 'LS574, but has
Inverted outputs. For complete discussions of operations,
truth tables, AC and DC electrical specifications, refer to the
'LS374 data sheet.
• Inputs and outputs on opposite sides of package allowIng easy Interface with microprocessors
• Useful as Input or output port for microprocessors
• Functionally Identical to 'LS574
• Input clamp diodes limit high speed termination effects
• Fully TIL and CMOS compatible
Connection Diagram
Logic Symbol
2
Dual-In-Llne Package
or
20
Vee
00
2
19
00
01
3
18
01
02
4
17
03
02
03
04
04
05
05
06
06
07
9
12
07
GHO
10
11
CP
11
3
00-07
6
7
8
9
OE
00 01 02 03 04 05 06 07
19 18 17 16 15 14 13 12
TLlF/l0191-2
vee
~
Pin 20
GND ~ Pin 10
TL/F/l0191-1
DO-D7
CP
OE
5
CP
Order Number DM74LS564WM or DM74LS564N
See NS Package Number M20B or N20A
Pin Names
4
Description
Data Inputs
Clock Pulse Input (Active Rising Edge)
TRI-STATE'" Output Enable Input
(Active LOW)
TRI-STATE Outputs
2-489
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
DM74LS
Storage Temperature Range
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table wilf define
the conditions for actual device operation.
O·Cto +70·C
-65·C to + 150·C
Recommended Operating Conditions
Symbol
DM74LS564
Parameter
Vee
Supply Voltage
Units
Min
Nom
Max
4.75
5
5.25
V
0.8
V
VIH
High Level Input Voltage
Vil
Low Level Input Voltage
2
V
10H
High Level Output Current
-2.6
rnA
10l
Low Level Output Current
24
mA
TA
Free Air Operating Temperature
70
·c
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 1)
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vee = Min, 11= -18 mA
VOH
High Level Output
Voltage
Vee = Min, 10H = Max,
Vil = Max
VOL
Low Level Output
Voltage
Vee = Min, 10l = Max,
VIH = Min
0.35
0.5
10l = 12 rnA, Vee = Min
0.25
0.4
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 10V
IIH
High Level Input Current
III
los
lee
Supply Current
Vee = Max
10ZH
TRI-STATE Output OFF
Current HIGH
Vee = VeeH, VOlH = 2.7V
TRI-STATE Output OFF
Current LOW
Nole 1: All typicals are at Vee ~ sv. TA ~ 2S'C.
Vee = VeeH, VOll = O.4V
lOll
2.7
3.4
V
V
0.1
mA
Vee = Max, VI = 2.7V
20
p,A
Low Level Input Current
Vee = Max, VI = O.4V
-0.4
mA
Short Circuit
Output Current
Vee = Max
(Note 2)
-130
mA
60
mA
20
p,A
-20
p,A
-30
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
2-490
Switching Characteristics
Vee =
+ 5.0V, TA
Symbol
=
+ 25°C (See Section 1 for test waveforms and output load)
Max
Units
tplH
tpHl
Propagation Delay
CP to On
Parameter
Min
28
28
ns
tPZH
tpZl
Enable Time
OE to On
28
28
ns
tpHZ
tpLZ
Enable Time
OEtoOn
20
25
ns
ts
Setup Time
DntoCP
5
ns
th
Hold Time ,
DntoCP
5
ns
tw(H)
twILl
Pulse Width
(HIGH/LOW) CP
20
10
ns
fII
2·491
~ ~National
~ Semiconductor
DM74LS573
Octal D-Type Latch (with TRI-STATE® Outputs)
General Description
Features
The 'l.S573 Is a high speed octal latch with buffered common Latch Enable (LE) and buffered common Output Enable (OE) Inputs.
This device Is functionally Identical to the 'LS373, but has
different pinouts. For truth tables, discussion of operations
and AC and DC specifications, please refer to the 'LS373
data sheet.
• Inputs and outputs on opposite sides of package
allowing easy Interface with microprocessors
• Useful as Input or output port for microprocessors
• Functionally Identical to 'LS373
• Input clamp diodes limit high speed termination effects
• Fully TIL and CMOS compatible
Connection Diagram
Logic Symbol
iiiiiIii
os
Dual-In-Llne Package
Of-I
00- 2
01- 3
02- 4
03- 5
04- 6
\.../
DO 01 02 03 04
20 --Vee
19 !-OO
18 !-Ol
17 !-02
16 1-03
15 1-04
05- 7
06- 8
07- 9
14 1-05
13 1-06
GNO- 10
lll-LE
1'-LE
l-cl OE
00 01 02 03 04 OS 06 07
TUF/9814-2
vee = Pin 20
GND = Pin 10
121-07
TUF/9814-1
Order Number DM74LS573WM or DM74LS573N
See NS Package Number M20B or N20A
Pin Names
00-07
LE
OE
00-07
06 07
DescriptIon
Data Inputs
Lateh Enable Input (Active HIGH)
TRI-STATE Output Enable Input (Active LOW)
TRI-STATE Latch Outputs
2-492
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
DM74LS
Storage Temperature Range
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
O'Cto +70'C
-65'C to + 150'C
Recommended Operating Conditions
Symbol
DM74LS
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
Units
Min
Nom
Max
4.75
5
5.25
V
2
V
Vil
Low Level Input Voltage
0.8
V
10H
High Level Input Current
-2.6
mA
10l
Low Level Output Current
24
mA
TA
Free Air Operating Temperature
70
'C
0
Electrical Characteristics
Over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
VI
Input Clamp Voltage
VOH
High Level Output
Voltage
VOL
Low Level Output
Voltage
Conditions
= Min, II = -18 mA
Vcc = Min, 10H = Max,
Vil = Max
Vcc = Min. 10l = Max,
VIH = Min
10L = 4 mA, Vee = Min
Vcc = Max, VI = 10V
Min
Typ
(Note 1)
Vce
II
Input Current @ Max
Input Voltage
IIH
High Level Input Current
Vee
III
Low Level Input Current
Vee
los
Short Circuit
Output Current
Vee = Max
(Note 2)
Ice
Supply Current
Vec
10ZH
TRI-STATE Output
off Current High
Vec = VeeH
VOZH = 2.7V
10Zl
TRI-STATE Output
off Current Low
Vcc = VCCH
VOZl = O.4V
=
=
=
Max, VI
Max, VI
=
=
2.7
Max
Units
-1.5
V
3.4
V
0.35
0.5
0.25
0.4
1
V
mA
2.7V
20
/LA
0.4V
-0.4
mA
-130
mA
50
mA
20
/LA
-20
/LA
-30
Max
Note 1: All typicals are at Vee = SV. TA = 2S'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
2-493
Switching Characteristics
at Vee
= 5V and TA = 25°C (see Section 1 for Test Waveforms and output loading)
RL = 2kO,
Symbol
CL
Parameter
Min
=
15pF
Units
Max
tpLH
tpHL
Propagation Delay
DatatoQ
27
tpLH
tpHL
Propagation Delay
LEtoQ
36
tPZH
tPZL
TRI·STATE Enable Time
OEtoQ
20
25
ns
tpHZ
tpLZ
TRI·STATE Enable Time
OEtoQ
20
25
ns
ts(H)
ts(L)
Setup Time (High/Low)
Data to LE
fh(H)
th(L)
Hold Time (High/Low)
Data to LE
tw(H)
Pulse Width (High)
Data to LE
18
25
3
7
3
7
15
2·494
ns
ns
ns
ns
ns
~National
~ Semiconductor
DM74LS574
Octal D-Type Flip-Flop (with TRI-STATE® Outputs)
General Description
The 'LS574 is a high speed low power octal flip-flop with a
buffered common Clock (CP) and a buffered common Output Enable (OE). The information presented to the D inputs
is stored in the flip-flops on the LOW-to-HIGH Clock (CP)
transition.
This device is functionally identical to the 'LS374 except for
the pinouts.
Connection Diagram
Logic Symbol
iiiiiIii
Dual-In-Line Package
liE-I
'-.../
20
00 01 02 03 04 05 06 07
-Vee
00- 2
19 -00
ll-CP
01- 3
1--(1 OE
02- 4
18 -01
17 -02
03- 5
16 -03
04- 6
15 :-04
05- 7
06- 8
14 1-05
13 1-06
07- 9
121-07
GNO- 10
lll-CP
00 01 02 03 04 OS 06 07
TLlF/9815-2
Vee = Pin 20
GND = Pin 10
TLlF/9815-1
Order Number DM74LS574WM or DM74LS574N
See NS Package Number M20B or N20A
2-495
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
DM74LS
Storage Temperature Range
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
O'Cto +70'C
-65'Cto + 150'C
Recommended Operating Conditions Vee =
Symbol
+5.0V, TA = +25'C
DM74LS574
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
IOH
IOL
Units
Min
Nom
Max
4.75
5
5.25
V
V
2
0.8
V
High Level Output Current
-2.6
mA
Low Level Output Current
24
mA
TA
Free Air Operating Temperature
0
70
'C
ts (H)
ts (L)
Setup Time HIGH or LOW
DntoCP
20
20
ns
th (H)
th (L)
Hold Time HIGH or LOW
DntoCP
0
0
ns
tw(H)
tw (L)
CP Pulse Width
HIGH or LOW
15
15
ns
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
VI
Input Clamp Voltage
Vee = Min, II = -18 mA
VOH
High Level Output
Voltage
Vee = Min, IOH = Max,
VIL = Max, VIH = Min
VOL
Low Level Output
Voltage
Vee = Min, IOL = Max,
VIL = Max, VIH = Min
IOL
=
12 mA, Vee = Min
II
Input Current @ Max
Input Voltage
Vee = Max, VI
IIH
High Level Input Current
IlL
Low Level Input Current
IOZH
IOZL
=
7V
Min
2.4
Typ
(Note 1)
Max
Units
-1.5
V
V
3.3
0.35
0.5
0.25
0.4
V
0.1
mA
Vee = Max, VI = 2.7V
20
p.A
Vee = Max, VI = 0.5V
-20
p.A
Off-State Output Current
with High Level Output
Voltage Applied
Vee = Max, Vo = 2.4V
VIH = Min, VIL = Max
20
p.A
Off-State Output Current
with Low Level Output
Voltage Applied
Vee = Max, Vo = O.4V
VIH = Min, VIL = Max
-20
p.A
2-496
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted) (Continued)
Symbol
Parameter
Short Circuit (Note 2)
Output Current
los
Vee
Typ
(Note 1)
Conditions
Min
= Max
-20
Max
Units
-100
rnA
45
rnA
Supply Current
Vee = Max (Note 3)
Icc
Note 1: Aillypicals are at Vee = SV, TA = 2S'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: Icc is measured with the DATA inputs grounded and the OUTPUT CONTROLS at 4.SV.
Note 4: Both IT Inputs are at 2V.
Note 5: Both IT inputs at O.4V.
Switching Characteristics
Vee =
+ 5.0V, TA
=
+ 25°C (See Section 1 for test waveforms and output load)
Symbol
RL = 2kO,
CL = 45pF
Parameter
Units
Min
35
Maximum Clock Frequency
fmax
tPZH
tpzL
Max
MHz
Propagation Delay
CPtoOn
28
28
ns
Output Enable Time
28
28
ns
Output Disable Time
20
25
ns
Truth Table
Functional Description
The LS574 consists of eight edge-triggered flip-flops with
individual D-type inputs and TRI-STATE true outputs. The
buffered clock and buffered Outputs Enable are common to
all flip-flops. The eight flip-flops will store the state of their
individual D inputs that meet the setup and hold times requirements on the LOW-to-HIGH Clock (CP) transition. With
the Output Enable (OE) LOW, the contents of the eight flipflops are available at the outputs. When the OE is HIGH, the
outputs go to the high impedence state. Operation of the
OE input does not affect the state of the flip-flops,
Inputs
Outputs
On
CP
OE
On
H
L
H
L
..r
..r
L
L
X
X
H
Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Logic Diagram
i
CP
I
l:
OE-c(>
I
i
I
i
I
I
I
:11: : t: :11: :J: :1: : I: : : :J
1'1'1'1'1'1'1'1'
TLlF/98t5-3
2-497
~ ~National
~ Semiconductor
DM74LS645 Octal Bus Transceivers
General Description
Features
These octal bus transceivers are designed for asynchronous two-way communication between data buses. The devices transmit data from the A bus to the B bus or from the
B bus to the A bus depending upon the level at the direction
control (DIR) input. The enable input (G) can be used to
disable the device so that the buses are effectively isolated.
• Bi-directional bus transceivers in high-density 20-pin
packages
• Hysteresis at bus inputs improves noise margins
• TRI-STATEI!> outputs
Connection Diagram
Dual-In-Llne Package
ENABLE
~
~
M
~
~
~
H
~
"
M
H
M
M
M
H
~
"
~
M
~
Order Number DM74LS645WM or DM74LS645N
See NS Package Number M20B or N20A
Function Table
Control
Inputs
H
'LS645
G
DIR
L
L
H
L
H
X
B data to A bus
A data to B bus
Isolation
= High Level
L = Low Level
X = Irrelevant
2-498
TLlF/9056-1
Absolute Maximum Ratings
(Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
DM74LS
Storage Temperature Range
O'Cto +70'C
-55'C to + 150'C
Recommended Operating Conditions
Symbol
DM74LS645
Parameter
Units
Min
Nom
Max
5
5.25
V
Vee
Supply Voltage (Note 1)
4.75
VIH
High Level Input Voltage
2
VIL
Low Level Input Voltage
0.6
V
V
10H
High Level Output Current
-15
mA
10L
Low Level Output Current
24
mA
TA
Free Air Operating
Temperature
70
'C
0
IElectrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Conditions
(Note 2)
Parameter
VI
Input Clamp Voltage
Vee
HyS
Hysteresis (VT +
Aor B Input
Vee
VOH
High Level Output Voltage
VOL
- V_)
Low Level Output Voltage
=
=
Min, II
=
Min
Typ
(Note 3)
18 mA
Min
Vee = Min, VIH
VIL = Max
=
Vee = Min, VIH
VIL = Max
=
2V,
2V,
0.2
0.4
10H
2.4
3.4
10H
2
= -3mA
= Max
10L = 12 mA
10L = 24mA
Max
Units
-1.5
V
V
V
0.25
0.4
0.35
0.5
V
10ZH
Off-State Output Current,
High Level Voltage Applied
Vee = Max, G at 2V,
Vo = 2.7V
20
p.A
10ZL
Off-State Output Current,
Low Level Voltage Applied
Vee = Max, G at 2V
Vo = O.4V
-400
/LA
II
Input Current at
Maximum Input Voltage
Vee
=
Max
I AorB
I DIRorG
=
=
Vee =
IIH
High Level Input Current
Vee
Max, VIH
IlL
Low Level Input Current
Vee
Max, VIL
los
Short Circuit Output Current
(Note 4)
Icc
Total Supply
Current
VI
VI
=
=
5.5V
0.1
7V
0.1
= 2.7
= 0.4V
Max
-40
Vee = Max,
Outputs Open
Outputs High
Outputs Low
Outputs at Hi-Z
Note 1: Voltage values are with respect to the network ground terminal.
Note 2: For conditions shown as Min or Max, use the appropriate value specified under Recommended Operating Conditions.
Note 3: All typicals are at Vee = SV, TA = 2S'C.
Note 4: Not more than one output should be shorted at a time, and the duration should not exceed one second.
2-499
mA
20
/LA
-0.4
mA
-225
mA
48
70
62
90
64
95
mA
fII
Switching Characteristics at Vee =
Symbol
Parameter
5V and T A = 25°C
From (Input)
To (Output)
RL - 6670
CL
Min
= 45pF
Max
CL
Min
= 5pF
Units
Max
tpLH
Propagation Delay Time
Low to High Level Output
AtoB
15
ns
tpHL
Propagation Delay Time
High to Low Level Output
AtoB
15
ns
tpLH
Propagation Delay Time
Low to High Level Output
BtoA
15
ns
tpHL
Propagation Delay Time
High to Low Level Output
BtoA
15
ns
tpZL
Output Enable Time
to Low Level
G
toA
40
ns
tPZH
Output Enable Time
to High Level
G
toA
40
ns
tpZL
Output Enable Time
to Low Level
G
to B
40
ns
tpZH
Output Enable Time
to High Level
G
to B
40
ns
tpLZ
Output Disable Time
to Low Level
G
toA
25
ns
tpHZ
Output Disable Time
to High Level
G
toA
25
ns
tpLZ
Output Disable Time
to Low Level
G
toB
25
ns
tpHZ
Output Disable Time
to High Level
G
toB
25
ns
2-500
'?A National
~ Semiconductor
54LS670/DM54LS670/DM74LS670
TRI-STATE® 4-by-4 Register Files
General Description
These register files are organized as 4 words of 4 bits each,
and separate on-Chip decoding is provided for addressing
the four word locations to either write-in or retrieve data.
This permits writing into one location, and reading from another word location, simultaneously.
Four data inputs are available to supply the word to be
stored. Location of the word is determined by the write select inputs A and B, in conjunction with a write-enable signal. Data applied at the inputs should be in its true form.
That is, if a high level signal is desired from the output, a
high level is applied at the data input for that particular bit
location. The latch inputs are arranged so that new data will
be accepted only if both internal address gate inputs are
high. When this condition exists, data at the D input is transferred to the latch output. When the write-enable input, Gw,
is high, the data inputs are inhibited and their levels can
cause no change in the information stored in the internal
latches. When the read-enable input, GR, is high, the data
outputs are inhibited and go into the high impedance state.
and the read time (24 ns typical). The register file has a nonvolatile readout in that data is not lost when addressed.
All inputs (except read enable and write enable) are buffered to lower the drive requirements to one normal Series
54LS174LS load, and input clamping diodes minimize
switching transients to simplify system design. High speed,
double ended AND-OR-INVERT gates are employed for the
read-address function and have high sink current, TRISTATE outputs. Up to 128 of these outputs may be wireAND connected for increasing the capacity up to 512 words.
Any number of these registers may be paralleled to provide
n-bit word length.
Features
• Alternate Military/Aerospace device (54LS670) is available. Contact a National Semiconductor Sales Office/
Distributor for specifications.
The individual address lines permit direct acquisition of data
stored in any four of the latches. Four individual decoding
gates are used to complete the address for reading a word.
When the read address is made in conjunction with the
read-enable signal, the word appears at the four outputs.
This arrangement-data entry addressing separate from
data read addressing and individual sense line - eliminates
recovery times, permits simultaneous reading and writing,
and is limited in speed only by the write time (27 ns typical)
• For use as:
Scratch pad memory
Buffer storage between processors
Bit storage in fast multiplication designs
• Separate read/write addressing permits simultaneous
reading and writing
• Organized as 4 words of 4 bits
• Expandable to 512 words of n-bits
• TRI-STATE versions of DM54LS170/DM74LS170
• Fast access times 20 ns typ
Connection Diagram
Function Tables
WRITE TABLE (SEE NOTES A, B, AND C)
Dual-In-Line Package
vrc
16
DATA
WRITE SELECT
INPUT
....------
WA
Dl
15
14
WB
OUTPUTS
ENABLE
Gw
13
\12
Write Inputs
.------.
GR
11
01
02
10
9
1
Word
WB
WA
GW
0
1
2
3
L
L
H
H
L
H
L
H
O=D
00
O=D
00
00
00
X
00
00
00
00
00
00
X
L
L
L
L
H
r-
1
00
00
O=D
00
READ TABLE (SEE NOTES A AND D)
Read Inputs
D2
O=D
00
00
00
2
\3
4
D3
D4
RB
DATA
INPUTS
.
I
_\5
RA
~
READ
0~6
l: G!:
~
OUTPUTS
SELECT
TL/F/6436-1
Order Number 54LS670DMQB, 54LS670FMQB,
54LS670LMQB, DM54LS670J, DM54LS670W,
DM74LS670M or DM74LS670N
See NS Package Number E20A,
J16A, M16A, N16A or W16A
RB
L
L
H
H
RA
L
H
L
H
X
X
GR
L
L
L
L
H
Outputs
Q1
Q2
Q3
Q4
WOB1
W1B1
W2B1
W3B1
Z
WOB2
W1B2
W2B2
W3B2
Z
WOB3
W1B3
W2B3
W3B3
Z
WOB4
W1B4
W2B4
W3B4
Z
Note A: H = High Level, L
Impedance (Off).
=
Low Level, X
=
Don't Care, Z
=
High
Note B: (a = D) = The four selected internal flip-flop outputs will assume
the states applied to the four external data inputs.
Note C: 00
established.
=
Note D: WOBt
2-501
The level of
a before the indicated input conditions were
= The first bit of word 0, etc.
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
DM54LS and 54LS
-55'C to + 125'C
DM74LS
O'Cto +70'C
Storage Temperature Range
- 65'C to + 150'C
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guarenteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Recommended Operating Conditions
Symbol
DM74LS670
DM54LS670
Parameter
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
0.7
0.8
V
-2.6
mA
24
mA
2
IOH
High Level Output Current
-1
IOL
Low Level Output Current
12
tw
Write Enable Pulse Width
(Note 3)
Isu
Setup Time
(Notes 1 &3)
tH
tLATeH
Hold Time
(Notes 1 &3)
25
25
Data
10
10
WA,WB
15
15
Data
15
15
WA,WB
5
5
25
25
Latch Time for New Data
(Notes 2 &3)
V
V
2
ns
ns
ns
ns
Free Air Operating
-55
125
0
70
'C
Temperature
Note 1: Times are with respect to the Write-Enable input. Write-Select time will protect the data written into the previous address. If protection of data in the
previous address, tsETUP ~A. We) can be ignored. As any address selection sustained lor the linal 30 ns 01 the Write· Enable pulse and during tH (WA. We) will
result in data being written Into that location. Depending on the duration 01 the Input conditions. one or a number 01 previous addresses may have been written into.
Note 2: Latch time is the time allowed lor the internal output 01 the latch to assume the state 01 new data. This is important only when attempting to read from a
location immediately alter that location has received new data.
Note 3: TA = 2S'C and Vee = SV.
TA
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Input Clamp Voltage
Vee
VOH
High Level Output Voltage
Vee = Min, IOH = Max
VIL = Max. VIH = Min
VOL
Low Level Output Voltage
Vee = Min, IOL
IOL = Max, VIH
IIH
Input Current @ Max
Input Voltage
High Level Input Current
Typ
(Note 1)
= Min,ll = -18 mA
VI
II
Min
= Max
= Min
Vec = Max
VI = 7V
Vec = Max
VI = 2.7V
2-502
2.4
Max
Units
-1.5
V
3.4
V
DM54
0.25
0.4
DM74
0.34
0.5
D,RorW
0.1
Gw
0.2
GR
0.3
D,RorW
20
Gw
40
GR
60
V
mA
/1- A
Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted) (Continued)
Symbol
IlL
10ZH
10ZL
los
lee
Parameter
Low Level Input Current
Conditions
Vee = Max
VI = 0.4V
Typ
(Note 1)
Min
0, R,orW
-0.4
Gw
-0.8
GR
-1.2
Units
mA
Off-State Output Current
with High Level Output
Voltage Applied
Vee = Max, Vo = 2.7V
VIH = Min, VIL = Max
20
/l-A
Off-State Output Current
with Low Level Output
Voltage Applied
Vee = Max, Vo = O.4V
VIH = Min, VIL = Max
-20
p.A
Short Circuit
Output Current
Vee = Max
(Note 2)
Supply Current
Vee
DM54
-20
-100
DM74
-20
-100
= Max (Note 3)
Switching Characteristics at Vee =
30
Parameter
50
mA
mA
5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
RL
Symbol
Max
From (Input)
To (Output)
CL
Min
= 45pF
Max
= 6670.
CL
Min
= 150pF
Units
Max
tpLH
Propagation Delay Time
Low to High Level Output
Read Select
toO
40
50
ns
tpHL
Propagation Delay Time
High to Low Level Output
Read Select
toO
45
55
ns
tpLH
Propagation Delay Time
Low to High Level Output
Write Enable
toO
45
55
ns
tpHL
Propagation Delay Time
High to Low Level Output
Write Enable
toO
50
60
ns
tpLH
Propagation Delay Time
Low to High Level Output
Data
toO
45
55
ns
tpHL
Propagation Delay Time
High to Low Level Output
Data
toO
40
50
ns
tPZH
Output Enable Time
to High Level Output
Read Enable
to Any 0
35
45
ns
tPZL
Output Enable Time
to Low Level Output
Read Enable
to Any 0
40
50
ns
tpHZ
Output Disable Time from
High Level Output (Note 4)
Read Enable
to Any 0
50
Output Disable Time from
Read Enable
35
Low Level Output (Note 4)
to Any 0
Note 1: All typical. are at Vcc = 5V, TA = 25·C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: Icc is measured with 4.5V applied to all DATA inputs and both ENABLE Inputs, all ADDRESS input. are grounded and all outputs are open.
Note 4: eL = 5 pF.
tpLZ
2-503
ns
ns
Ell
~
Logic Diagram
01 (15)
OUTPUTS
DATA
INPUTS
03(2)
(4)
(11) (5)
RB
GR
RA
REAOINPUT
TLlF/6436-2
2·504
~National
~ Semiconductor
DM74LS952
Dual Rank 8-Bit TRI-STATE® Shift Registers
General Description
Features
These circuits are TRI-STATE, edge-triggered, 8-bit I/O registers in parallel with 8-bit serial shift registers which are
capable of operating in any of the following modes: parallel
load from I/O pins to register "A", parallel transfer down
from register "A" to serial shift register "S", parallel transfer
up from shift register "S" to register" A", serial shift of register "S", synchronously clear. Since the registers are edgetriggered by the positive transition of the clock, the control
lines which determine the mode or operation are completely
independent of the logic level applied to the clock. Designed for bus-oriented systems, these circuits have their
TRI-STATE inputs and outputs on the same pins.
• Registers are edge-triggered by the positive transition
of the clock
• All inputs are PNP transistors
• Input disable dominates over output disable
• Output high impedance state does not impede any other mode of operation
• 8-bit I/O pins are TRI-STATE buffers
• Typical shift frequency is 36 MHz
• Typical power dissipation is 305 mW
• All control inputs are active when in an "L" logic state
• Devices can be cascaded into N-bit word
Connection Diagram
vcc
\18
I/O 1
I/O 2
17
Dual-In-Line Package
1103 I/O 4 I/O 5
1106
I/O 7
13
12
11
16
\15
\14
I/O 8
10
~l
-t
-
CONTROL
lOGIC
0
-L
r-I
DISO
2
3
1
DISI
\4
upl)'
TRANSFER
DISTU
5
6
DISTD
DISS
Os-Serial output
CLK-Clock
GND-Ground
j
7
Os
I/O 1 ... I/O 8-8-bit I/O pins
J
lOWER SHIFT REG "S"
~
I
1
DISs-Shift disable
UPPER REG "N'
UDOWN
DISo-Output disable
Is-Serial input
DIS,-Input disable
DISTU-Transfer up disable
DISTD-Transfer down disable
t- f-
I/O SUFFERS
Pin Description
8
ClK
Vcc-Supply Voltage
19
GND
TLlF/6437-1
Top View
Order Number DM74LS952N
See NS Package Number N18A
2-505
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
DM74LS
Storage Temperature Range
O'Cto +70'C
- 65'C to + 150'C
Lead Temperature (Soldering, 10 seconds)
300"C
Recommended Operating Conditions
Symbol
DM74LS952
Parameter
Vee
Supply Voltage
VIH
High-Level Input Voltage
VIL
Low-Level Input Voltage
IOH
High-Level Output Current
Units
Min
Typ
Max
4.75
5
5.25
V
0.8
V
-5.2
mA
2
V
IOL
Low-Level Output Current
!eLoeK
Clock Frequency (Note 5)
0
16
mA
25
MHz
Clock Pulse
High Pulse Width (Note 5)
25
17
ns
Low Pulse Width (Note 5)
15
7
ns
tSET·UP
Data Set-Up Time (Note 5)
10
tHOLD
Data Hold Time (Note 5)
0
TA
Free Air Operating Temperature
0
ns
ns
70
'C
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
DM74LS952
Conditions (1)
Min
Typ(2)
Units
Max
-1.5
VI
Input Clamp Voltage
Vee = Min, 11= -18 mA
VOH
High-Level Output Voltage
Vee = Min, VIH = 2V,
VIL = VIL Max
IOH = -5.2mA
VOL
Low-Level Output Voltage
Vee = Min, VIH = 2V,
VIL = VILMax
IOL = 8mA
0.25
0.4
IOL = 16mA
0.35
0.5
II
Input Current at Maximum
Input Voltage
V
V
2.4
Vee = Max, VI = 5.5V
V
0.1
mA
p.A
IIH
High-Level Input Current
Vee = Max, VI = 2.7V
20
IlL
Low-Level Input Current
Vee = Max, VI = O.4V
-50
p.A
los
Short-Circuit Output Current
Vee = Max (3)
-100
mA
Icc
Supply Current
Vee = Max (4)
99
mA
10FF
TRI-STATE 110 Current
Vee = Max, VIH = 2V
Vo = 2.4V
20
p.A
Vo = O.4V
-20
p.A
-20
61
Note 1: For conditions shown as min or max, use the appropriate value specified under recommended operating conditions.
Note 2:
All
typical values are at Vee
= SV. TA = 2S'C.
Note 3: Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
Note 4: lee is measured with serial output open, the clock and shift disable input at 2.4V.
Note 5:
TA =
2S'C and Vee
= SV.
2-506
All
other control inpuls and 110 pins grounded.
Switching Characteristics at Vee = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
Conditions
Min
Max
Units
MHz
fMAX
Maximum Clock Frequency
25
tpLH
Propagation Delay Time, Low-to-High-Level
from Clock to Any Outputs
7
33
ns
tpHL
Propagation Delay Time, High-to-Low Level
from Clock to Any Output
10
48
ns
CL
= 15 pF, RL = 1 kO
tENABLE
Enable Time from Any Control Inputs
5
24
ns
tOISABLE
Disable Time from Any Control Inputs
6
27
ns
tPZH
Output Enable Time to High Level
5
23
ns
tPZL
Output Enable to Low Level
4
18
ns
tpHZ
Output Disable Time from High Level
5
23
ns
tpLZ
Output Disable Time from Low Level
6
27
ns
CL
= 5 pF, RL = 1 kO
Logic Diagram
1/01
1/02
DlSo
~
~
D CK O
"DISloDlSTUo-
=g
DlSsO--
~
CK
~
CK Q
-{)
IS
-{)
~~ ...• ~
"-
~
DI&rDD-
'l
'--
~ ...
CK
Q
D
CKO
K
Y>
Os CLOCK
TL/F/6437-2
2-507
LS952
Function Table
Table I
8-Bit1l0
DISo DIS, DISTU DISrD DISs ClK Is
Pins
H
L
X
H
L
X
H
L
X
H
L
X
0,
H
L
0>
X
'"o
H
L
X
X
==
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
H
H
H
H
L
H
H
H
L
L
L
X
X
X
H
H
L
L
L
L
L
L
L
X
X
X
H
H
L
H
H
H
H
H
H
L
L
L
H
H
L
L
L
L
H
H
H
L
L
L
X
X
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
i
Content of Upper Reg. "A"
Content of lower Serial Shift Reg. "B"
B1
B2
B3
B4
B5
B6
B7
B8
X
X
X
Hi-Z
Output
Input
a1 a2 a3 a4 a5 a6 a7 a8
a1 a2 a3 a4 a5 a6 a7 a8
I, 12 Is 14 Is 16 17 Is
bl
b1
b1
b2
b2
b2
b3
b3
b3
b4
b4
b4
b5
b5
b5
b6
b6
b6
b7
b7
b7
b8
b8
b8
b8
Stable state
b8
b8 Entering data from I/O to reg. "A"
X
X
X
Hi-Z
Output
Input
b1
b1
bl
b1
b1
b2
b2
b2
b3
b3
b3
b4
b4
b4
b5
b5
b5
b6
b6
b6
b7
b7
b7
b8
b8
b8
b8
Transfer data up from reg. "B" to reg. "A"
b8
b8 Reg. "A" will OR data from 1/0 to reg. "B"
X
X
X
Hi-Z
Output
Input
a1
a1
I,
a2 a3 a4 a5 a6 a7 a8
a2 a3 a4 a5 a6 a7 aB
12
14
Is 16 17 Is
13
a1
a1
a1
a2
a2
a2
a3
a3
a3
a4
a4
a4
a5
a5
a5
a6
a6
a6
a7
a7
a7
aB
aB
a8
a8
Transfer data down from reg. "A" to reg. "B"
a8
a8 Entering data and transfer down
X
X
X
Hi-Z
Output
Input
L
L
I,
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
d
d
d
Hi-Z
Output
Input
a1
a1
I,
d
d
d
Hi-Z
Output
Input
b1
b1
b2 b3 b4 b5 b6 b7 b8
b2 b3 b4 b5 b6 b7 b8
b2 b3 b4 b5 b6 b7 b8
b2 b3 b4 b5 b6 b7 b8
+- +- +-DOR- - -
L
L
L
L
16
17
Is
L
L
L
a2 a3 a4 a5 a6 a7 aB
a2 a3 a4 a5 a6 a7 a8
12
Is 14 Is 16 17 Is
d
d
d
b1
b1
b1
b2
b2
b2
b3
b3
b3
b4
b4
b4
b5
b5
b5
b6
b6
b6
b7
b7
b7
b7
Serial shifting in the lower reg. "B"
b7
b7 Entering data and serial shifting
d
d
d
b1
b1
b1
b2
b2
b2
b3
b3
b3
b4
b4
b4
b5
b5
b5
b6
b6
b6
b7
b7
b7
b7
Transfer up and serial shifting
b7
b7 DOR function and serial shifting
12
L
L
14
L
L
Is
+- +- +-DOR- - -
H~Z/Oulpullinpull '" High impedance state/oulpul state/inpul state
=- The content of the upper register "A"/the lower serial shift register "B" before the most recent t
transition of the clock
I, ... 18 '" The level of steady state inpuls of the 1/0 pins
DOR '" "Data ORing function" ORing data from both 1/0 pins and register "B", i.e., 11
d '" Data of the sanal input
-_.
--
+
b', 12
+
b2, 13
+ bS •.. 18 +
bS
L
L
L
(1)
(2)
(3)
Synchronously clear both registers to
logic "L" level
Enter data to reg. "A" clear reg. "B"
L
L
L
L
Is
Don't Care
a1 ... aB/b1 ... b8
Comments
Os
A1 A2 A3 A4 A5 A6 A7 A8
Timing Diagram
DM54174LS952
CLK
-
4
! l -r L r L ! l - r L ! L
BEFORE
CLOCK
PULSE #
I/O 1 • • • liD 8
01
01
01
01
...!J..
O'SO
UPPER REG "A"
I
I
D'S,
L
OISTO
IS
1102
1103
1104
- -'
- -,
- -'
- -,
,
I
,
1107
1/08
IS
I
-+/
LOWER SHIFT REG "8"
10
-I
TR'-STATE
f--
IY-I'I
I II
I I
I
r-
Os
10
I I
l
I
I
rt1I
10
IL-J
I
rt1-
10
~
-'
I
1105
1/06
~
I
OISS
1/01
L
I
O'STU
01
01
01
01
10
10
10
10
10
10
10
10
00
00
00
001
I
I
rt1-
I
4
o
l
I
Bl
B2
I
L
I
B3
-'
:!!
~~
B4
I
I
I
I
I
I
I
I
I
~!I!
0"
B5
Ot:
~iii
B8
0
B7
I
B8
I
-'w
ILl<
u
I
I
l
I
I
I
I
I
Os
I
L
I
1
TL/F/6437-3
2·509
•
~
AC Test Circuit and Switching Time Waveforms
TEST POINT
All diodes are 1N916 or 1N3064.
CL includes probe and jig capacitance.
5k
TLlF/6437-4
HIGH CLOCK
PULSE WIDTH-
3 V - - + ,........
OV
LOW CLOCK
PULSE WIDTH - 3V--------------------~
OISI. DlSTU
OISTD& DISS 1 . 3 V - - - - - - - - - - -
~------------~-------'
3V----------------------~rr~~
I/O&IS 1.3V - - - - - - - - - - - - - - - - - - - - - 1 OV---------------------------------------'
1/0
VOL
----"""T"-'i
3V------,~--~
DIS01.3V----1OV----
TLlF/6437-5
All Input pulses are supplied by generators having t,
s:
15 ns, tl
s:
6 ns, PRR
s:
1 MHz, ZOUT :::: 500.
Cascading Packages
Cascading Packages for N-Bit Word
1101
1108
1/01
I I I I I I I I
I1
IS
I
DISc
DM54LS852
Os
I
•• •
1/08
NI/OPINS
I I I I I I I I
II
DM54LS852
I
IS
Os
r
r
I
1
DlSI
DlSTU
DISrD
DISS
ClK
TL/F/6437-6
2·510
~National
~ Semiconductor
DM74LS962
Dual Rank 8-Bit TRI-STATE® Shift Registers
General Description
Features
These circuits are TRI-STATE, edge-triggered, S-bit I/O registers in parallel with S-bit serial shift registers which are
capable of operating in any of the following modes: parallel
load from I/O pins to register "A", parallel transfer down
from register "A" to serial shift register "8", parallel transfer
up from shift register "8" to register "A", serial shift of register "8", or exchange data between register "A" and shift
register "8". Since the registers are edge-triggered by the
positive transition of the clock, the control lines which determine the mode or operation are completely independent of
the logic level applied to the clock. Designed for bus-oriented systems, these circuits have their TRI-STATE inputs and
outputs on the same pins.
• Registers are edge-triggered by the positive transition
of the clock
• All inputs are PNP transistors
• Input disable dominates over output disable
• Output high impedance state does not impede any other mode of operation
• S-bit I/O pins are TRI-STATE buffers
• Typical shift frequency is 36 MHz
• Typical power dissipation is 305 mW
• All control inputs are active when in an "L" logic state
• Devices can be cascaded into N-bit word
Connection Diagram
Dual-In-Llne Package
vcc
118
I/O 1
I/O 2
I/O 3
16
17
I/O 4
115
I/O 5
I/O 6
13
114
I/O 7
12
11
CONTROL
lOGIC
~
I/O BUFFERS
f---I
UPPER REG "A"
r-L
DISO
3
1
DISI
I
upD
TRANSFER
5
6
DISTU DISTD
DISS
14
DISo-Output disable
8
7
Os
ClK
Vcc-8upply Voltage
9
1
GND
TUF/643B-l
Top View
Order Number DM74LS962N
See NS Package Number N18A
2-511
DISTD-Transfer down disable
DISs-8hift disable
Og-8erial output
CLK-Clock
GND-Ground
I/O 1 ... I/O 8-S-bit I/O pins
I
lOWER SHIFT REG "B"
~
I
2
t- -
{}
1!DOWN
1
10
Pin Description
Is-Serial input
DISI-Input disable
DISTU-Transfer up disable
~l
~
I/O 8
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
Note: The "Absolute MBJdmum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute mBJdmum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
7V
Operating Free Air Temperature Range
DM74LS
O·Cto +70"C
-65·Cto + 150·C
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
300·C
Recommended Operating Conditions
Symbol
DM74LS962
Parameter
Units
Min
Typ
Max
4.75
5
5.25
V
0.8
V
Vee
Supply Voltage
VIH
High-Level Input Voltage
VIL
Low-Level Input Voltage
10H
High-Level Output Current
-5.2
mA
10L
Low-Level Output Current
16
mA
feLOeK
Clock Frequency (Note 5)
0
25
MHz
Clock
Pulse
High Pulse Width (Note 5)
25
17
ns
Low Pulse Width (Note 5)
15
7
ns
tSET-UP
Data Set-Up Time (Note 5)
10
tHOLD
Data Hold Time (Note 5)
0
TA
Free Air Operating Temperature
0
2
V
ns
ns
·C
70
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions (1)
Min
Typ(2)
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vee = Min,ll = -18 mA
VOH
High-Level Output Voltage
Vee = Min, VIH = 2 V,
VIL = VILMax
10H = -2.6mA
Vee = Min, VIH = 2 V,
VIL = VIL Max
IOL=8mA
0.25
0.4
10L = 16mA
0.35
0.5
VOL
Low-Level Output Voltage
II
Input Current at Maximum
Input Voltage
Vee = Max, VI = 5.5V
IIH
High-Level Input Current
IlL
Low-Level Input Current
los
Short-Circuit Output Current
Vee = Max (3)
Icc
Supply Current
Vee = Max (4)
10FF
TRI-STATE 110 Current
Vee = Max, VIH = 2V
10H = -5.2mA
V
2.4
0.1
mA
Vee = Max, VI = 2.7V
20
p.A
Vee = Max, VI = 0.4V
-50
p.A
-100
mA
99
mA
-20
61
Vo = 2.4V
20
p.A
Vo = O.4V
-20
p.A
Note 1: For conditions shown as min or max, use the appropriate value specified under recommended operating
cond~ions.
Note 2: All typical values are at Vee = 5V, TA = 2S'O.
Note 3: Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
Note 4: Icc is measured with serial output open, the clock and shift disable Input at 2.4V. All other control Inputs and 110 pins grounded.
Note 5: TA
V
= 2S'O and Vcc = SV.
2-512
Switching Characteristics Vee = 5V and TA = 25·C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
Min
Conditions
Max
Units
fMAX
Maximum Clock Frequency
25
tpLH
Propagation Delay Time, Low-to-High-Level
from Clock to Any Outputs
7
33
ns
tpHL
Propagation Delay Time, High-to-Low Level
from Clock to Any Outputs
10
48
ns
CL
= 15 pF, RL = 1 kO
MHz
tENABLE
Enable Time from Any Control Inputs
5
24
ns
tOISABLE
Disable Time from Any Control Inputs
6
27
ns
tZH
Output Enable Time to High Level
5
23
ns
tZL
Output Enable to Low Level
4
18
ns
tHZ
Output Disable Time from High Level
5
23
ns
tLZ
Output Disable Time from Low Level
6
27
ns
CL
= 5 pF, RL = 1 kO
Logic Diagram
1/01
1/02
DiSc
"\
~
CK Q
DISI<>DISTU<>-
~
DISS<>--
-{)
CK Q
K>
~
CK
-{)
~~ .... ~
......
IS
DISTDO-
\
'---
~ ...
CK
Q
D
CK ii
----c
----c
Os CLOCK
TL/F/6438-2
2-513
II
LS962
Function Table
Table I
DISo
..,.~
DIS,
DISru
DISro
DISs ClK
H
l
X
H
H
L
H
H
H
H
H
H
H
H
H
H
L
X
H
H
L
L
L
L
H
H
H
H
H
H
H
L
X
H
H
L
H
H
H
L
L
L
X
X
X
H
L
X
H
H
L
L
L
L
L
L
L
X
X
X
H
L
X
H
H
L
H
H
H
H
H
H
L
L
L
H
L
X
H
H
L
L
L
L
H
H
H
L
L
L
X
X
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
8-Blt 110
Is
Pins
Content of Upper Reg. "A"
Content of lower Serial Shift Reg. "B"
A2
A3 A4
A5
A6
A7
A8
B1
B2
B3
B4
B5
B8
B7
B8
a8
a8
Is
b1
b1
b1
b2
b2
b2
b3
b3
b3
b4
b4
b4
b5
b5
b5
b6
b6
b6
b7
b7
b7
b8
b8
b8
b8
b8
b8
X
X
X
Hi-Z
Output
Input
a1
a1
a2
a2
a3
a3
a4
a4
a5
a5
a6
a6
a7
a7
11
12
13
14
15
16
17
X
X
X
Hi-Z
Output
Input
b1
b1
b2 b3 b4 b5 b6 b7 b8
b2 _
b3_b4OORb5______
b6 b7 b8
_
b1
b1
b1
b2
b2
b2
b3
b3
b3
b4
b4
b4
b5
b5
b5
b6
b6
b6
b7
b7
b7
b8
b8
b8
b8
b8
b8
X
X
X
Hi-Z
Output
Input
a1
a1
a2
12
13
14
15
16
17
a1
a1
a1
a2
11
a8
a8
Is
a2
a2
a3
a3
a3
a4
a4
a4
a5
a5
a5
a6
a6
a6
a7
a7
a7
a8
a8
a8
a8
a8
a8
X
X
X
Hi-Z
Output
Input
b1
b1
b2
b2
b3
b3
b4
b4
b5
b5
b6
b6
b7
b7
b8
b8
a2
a2
a2
a3
a3
a3
a4
a4
a4
a5
a5
a5
a6
a6
a6
a7
a7
a7
a8
as
a8
a8
a8
a8
d
d
d
Hi-Z
Output
Input
a1
a1
11
12
-OOR-- - - - a4 a5 a6 a7 a8
a4 a5 a6 a7 a8
13
14
15
16
17
Is
a1
a1
a1
d
d
d
b1
b1
b1
b2
b2
b2
b3
b3
b3
b4
b4
b4
b5
b5
b5
b6
b6
b6
b7
b7
b7
b7
b7
b7
d
d
d
Hi-Z
Output
Input
b1
b1
b2
b2
b3
b3
d
d
d
b1
b1
b1
b2
b2
b2
b3
b3
b3
b4
b4
b4
b5
b5
b5
b6
b6
b6
b7
b7
b7
b7
b7
b7
a3
a3
a2
-
-
a5
a5
a6
a6
a7
a7
a3
a3
a2
a2
-
a4
a4
-
b4
b4
b5
b5
b6
b6
b7
b7
b8
b8
-OOR-- - - - -
x '" Don't Care
H~Z/Ouipull'nput/ '" High impedance slate/output slate/Input slate
al •.. as/bl ••• b8 '" The content of the upper register "A"/the lower serial shift register "B" before the most recent
11 ••. 18 '" The level of steady slate inputs of the 110 pins
DOR '" "Dala ORing function" ORing dala from both 110 pins and register "B", i.e., 11
d '" Dala of the serial Input
+ bl, 12 +
b2, 13
t
transition of the clock
+ b3 •.. 18 + bS
Comments
Os
A1
Stable state
Entering data from I/O to reg. "A"
Transfer data up from reg. "B" to reg. "A"
Reg. "A" will OR data from I/O to reg. "B"
Transfer data down from reg. "A" to reg. "B"
Entering data and transfer down
(1) Exchange data between registers
(2) Beside data exchanging, reg. "A"
(3) will "OR" data from I/O and reg. "B"
Serial shifting in the lower reg. "B"
Entering data and serial shifting
Transfer up and serial shifting
OOR function and serial shifting
Timing Diagram
DM54174LS962
ClK
- ! l -! l -!l-r-~ru:-L
I
015 0
DIS,
L
J
1/06
--
f.-I
h
- f.-I
- h
- f.-I
- h
-
1/08
S
0:
w
r----,
I
----'
I I
h----1
~
L
I
B3
~
....
85
~
u
B6
I
B7
10
10
r
Os
10
10
1_1
10
10
10
1):
01
01
01
01
01
01
01
01
10
10
10
10
11
11
11
11
01
01
01
01
j-~
I
I
I
I
I
'--
I
'--
I
I
'--
zw
...
lOWER SHIFT REG ··B··
I
I
0
01
I
8'
84
..u..
I
I I
I
- h
II
0:
4
I
I
I I
01
----1
I I
81
C/)
w
-
TRI·STATE
I
I
1/07
I-
I-I
I
1/08
01
~
~
-
I/O 5
IS
10
IS
1/04
L~
l
DISS
1/03
01
I
DISTD
I/O 2
1/01
UPPER REG ··A··
I
j
DISTU
I/O 1
BEFORE
CLOCK
PULSE #
I
!---
B8
Os
TLlF/6438-3
2-515
~
~
AC Test Circuit and Switching Time Waveforms
TEST POINT
All diodes are 1N916 or 1N3064.
CL Includes probe and Jig capacitance.
TLIFI6438-4
HIGH CLOCK
PULSE WIDTH-
3V--+._
DIS" DISTU
DISTD& DISS 1.3Y
OY
3Y
110 &Is 1.3Y
OY
IpdL
110
VOL
3Y
DISO 1.3Y
OY
ILZ
TUFI8438-5
All Input pulses are supplied by generators having I, ,; 15 ns. If ,; 6 ns. PRR ,; 1MHz, lour
'"
50n.
Cascading Packages
Cascading Packages for N-Bit Word
1/08
1/01
I1
IS
I
DlSo
DM54LS962
Os
I
• • • N 1/0 PINS
1/08
1/01
I I I I I IJJ
I I I I I I I I
II
DM74LS962
IS
~J
Os
I
1
1
DlSI
DISru
DISm
DlSS
CLK
TLIF/843B-6
2-516
. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - , U)
Q)
~
~National
~ Semiconductor
I\)
96LS02/DM96LS02
Dual Retriggerable Resettable Monostable Multivibrator
General Description
Features
The 96LS02 is a dual retriggerable and resettable monostable multivibrator. The one-shot provides exceptionally wide
delay range, pulse width stability, predictable accuracy and
immunity to noise. The pulse width is set by an external
resistor and capacitor. Resistor values up to 1.0 M!l reduce
required capacitor values. Hysteresis is provided on both
trigger inputs of the 96LS02 for increased noise immunity.
• Required timing capacitance reduced by factors of 10
to 100 over conventional designs
• Broad timing resistor range-l.0 k!l to 2.0 M!l
• Output Pulse Width is variable over a 2000:1 range by
resistor control
• Propagation delay of 35 ns
• 0.3V hysteresis on trigger inputs
• Output pulse width independent of duty cycle
• 35 ns to 00 output pulse width range
Connection Diagram
Dual-In-Llne Package
CX1 - 1
RX1 - 2
C01 - 3
'-.../
14
13
11- 4
To-
16 r-Vcc
15 r-CX2
5
r-RX2
r-C02
12Hl
Ql- 6
11 f- To
01- 7
10 r-Q2
GND- 8
9 r-02
TL/F/9BI6-1
Order Number 96LS02DMQB, 96LS02FMQB, DM96LS02M or DM96LS02N
See NS Package Number J16A, M16A, N16E or W16A
Pin Names
io
io
11
CD
Q
Q
Description
Trigger Input (Active Falling Edge)
Schmitt Trigger Input (Active Falling Edge)
Schmitt Trigger Input (Active Rising Edge)
Direct Clear Input (Active LOW)
True Pulse Output
Complementary Pulse Output
2-517
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
10V
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Operating Free Air Temperature Range
96LS Military
- 55·C to + 125·C
O·Cto +70·C
DM96LS Commercial
Storage Temperature Range
- 65·C to + 150·C
Recommended Operating Conditions
Symbol
Vee
Supply Voltage
VIH
High Level Input Voltage.
VIL
Low Level Input Voltage
IOH
High Level Output Current
DM96LS02 (COM)
96LS02 (MIL)
Parameter
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
0.7
0.8
V
-0.4
-0.4
mA
8
mA
70
·C
2
IOL
Low Level Output Current
TA
Free Air Operating Temperature
Units
Min
2
V
4
-55
125
0
Electrical Characteristics
Over recommended operating free air temperature range (unless otherwised noted)
Symbol
Parameter
Conditions
VI
Input Clamp Voltage
Vee
VOH
High Level
Output Voltage
Vee
VOL
=
=
Min, II
Min, IOH
Input Current @ Max
Input Voltage
IIH
High Level Input Current
Vee
IlL
Low Level Input Current
Vee
=
=
=
Max, VI
Max, VI
Short Circuit
Vee
Output Current
(Note 2)
Icc
Supply Current
Vee
VT+
Positive-Going Threshold
Voltage, io, 11
VT-
Negative-Going Threshold
Voltage, io, 11
Nole 1: All typicals are at Vee
~
5V, TA
=
Max,
= Max
Vee = Min, IOL = Max,
VIH = Min
IOL = 4 mA, Vee = Min
Vee = Max, VI = 10V
Low Level
Output Voltage
~
=
Typ
(Note 1)
-18 mA
VIL
II
los
=
Min
=
=
MIL
2.5
COM
2.7
Max
Units
-1.5
V
V
3.4
MIL
0.4
COM
0.35
0.5
COM
0.25
0.4
0.1
V
mA
2.7V
20
,...A
0.4V
-0.4
mA
Max
MIL
-20
-100
COM
-20
-100
Max
MIL
0.7
COM
0.8
2S·C.
Nole 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
2-518
mA
36
mA
2.0
V
V
Switching Characteristics
Vee =
+ 5.0V. TA
=
+ 25'C (See Section 1 for waveforms and load configurations)
96LS(MIL)
Symbol
Parameter
DM96LS (COM)
CL = 15pF
Min
CL = 15pF
Max
tpLH
Propagation Delay
Ritoa
45
tpHL
Propagation Delay
Ritoa
33
tpLH
Propagation Delay
11 toO
45
tpHL
Propagation Delay
11 toa
33
tpHL
Propagation Delay
CDtoa
25
tpLH
Propagation Delay
CDtoa
30
Min
Units
Max
55
ns
50
ns
60
ns
55
ns
30
ns
35
ns
ns
tw(L)
10 Pulse Width LOW
15
15
tw(H)
11 Pulse With HIGH
30
30
ns
tw(L)
CD Pulse Width LOW
22
22
ns
tw(H)
Minimum a Pulse Width HIGH
tw
a Pulse Witdh
20
70
25
55
ns
4.25
5.0
4.1
4.5
p.s
1
Rx
Timing Resistor Range"
1000
kfl
t
Change in a Pulse
Width over Temperature
1.0
%
t
Change in a Pulse
Width over Vee Range
0.8
1.5
%
'Applies only over commercial VCC and TA range for 96502.
Functional Description
Operation Notes
The 96LS02 dual retriggerable resettable monostable multivibrator has two DC coupled trigger inputs per function. one
active LOW (i0) and one active HIGH (11). The 11 input and
io Input of the 96LS02 utilize an internal Schmitt trigger with
hysteresis of 0.3V to provide increased noise immunity. The
use of active HIGH and LOW inputs allows either rising or
falling edge triggering and optional non-retriggerable operation. The inputs are DC coupled making triggering independent of input transition times. When input conditions for triggering are met. the a output goes HIGH and the external
capacitor is rapidly discharged and then allowed to recharge. An input trigger which occurs during the timing cycle
will retrigger the circuit and result in a remaining HIGH. The
output pulse may be terminated (a to the LOW state) at any
time by setting the Direct Clear input LOW. Retriggering may
be inhibited by tying the a output to io or the a output to 11.
Differential sensing techniques are used to obtain excellent
stability over temperature and power supply variations and a
feedback Darlington capacitor discharge circuit minimizes
pulse width variation from unit to unit. Schottky TTL output
stages provide high switching speeds and output compatibility with all TTL logic families.
TIMING
1. An external resistor (Rx) and an external capacitor (Cx)
are required as shown in the Logic Diagram. The value of
RX may vary from 1.0 kfl to 1.0 Mfl (96LS02).
2. The value of Cx may vary from 0 to any necessary value
available. If. however. the capacitor has significant leakage
relative to Vee/Rx the timing equations may not represent
the pulse width obtained.
3. Polarized capacitors may be used directly. The (+ ) termlnal of a polarized capacitor is connected to pin 1 (15). the
(-) terminal to pin 2(14) and Rx. Pin 1(15) will remain posltive with respect to pin 2(14) during the timing cycle.
4. The output pulse width tw for Rx ~ 10 kfl and Cx ~
1000 pF is determined as follows:
tw = 0.43 RxCx
Where Rx is in kfl. Cx is in pF. t is in ns or Rx is in kfl. Cx is
in p.F. t is in ms.
5. The output pulse width for Rx < 10 kfl or Cx < 1000 pF
should be determined from pulse width versus Cx or Rx
graphs.
6. To obtain variable pulse width by remote trimming. the
following circuit is recommended:
I.Okn
PlN2
(14)~--------------b
PINI ( I S ) J
'-AS CLOSE AS POSSIBLE
TO OEVICE
Rx -1.5 kn
v~o-----------------TL/F/9818-4
2-519
~
!J~
,---------------------------------------------------------------------------------,
Operation Notes (Continued)
2. Input signals to the 96LS02 exhibiting slow or noisy transitions can use either trigger as both are Schmitt triggers.
3. When non-retriggerable operation is required, i.e., when
input triggers are to be ignored during quasi-stable state,
input latching is used to inhibit retriggering.
4. An overriding active LOW level direct clear is provided on
each multivibrator. By applying a LOW to the clear, any timing cycle can be terminated or any new cycle inhibited until
the LOW reset input is removed. Trigger inputs will not produce spikes in the output when the reset is held LOW. A
LOW-to-HIGH transition on Co will not trigger the 96LS02. If
the CD input goes HIGH coincident with a trigger transition,
the circuit will respond to the trigger.
7. Under any operating condition, Cx and Rx (Min) must be
kept as close to the circuit as possible to minimize stray
capacitance and reduce noise pickup.
8. Vee and ground wiring should conform to good high frequency standards so that switching transients on Vee and
ground leads do not cause interaction between one shots.
Use of a 0.01 I£F to 0.1 I£F bypass capacitor between Vee
and ground located near the circuit is recommended.
TRIGGERING
1. The minimum negative pulse width into io is 8.0 ns; the
minimum positive pulse width into 11 is 12 ns.
Cl
Rl
+ H_"'II\fIr--Vcc
Q
+
OUTPUTIL
Cl
Rl
HP-"'V\fII--Vcc
OUlPUTIL
J
L
INPUT--"--:::ooo.
INPUT
Q
POSITIVE EDGE TRIGGER
NEGATIVE EDGE TRIGGER
TL/F/9816-5
TL/F/9816-6
Triggering Truth Table
Pin No's.
5(11)
4(12)
3(13)
H-L
H
L
L-H
X
X
H
H
L
Logic Symbol
Operation
RX
Trigger
Trigger
Reset
6(10)
H = HIGH Voltage Level .. VIH
L = LOW Voltage Level ,. VIL
X = Immaterial (either H or L)
H -+ L = HIGH to LOW Voltage Level Transition
L -+ H = LOW to HIGH Voltage Level Transition
(12)4
(11)5
•_____
7(9)
vee = Pin 16
GNO = Pin 8
(13)3
TUF/9816-2
2-520
Logic Diagram
96LS02
TL/F/9BI6-3
Typical Performance Characteristics
Output tw VB
RxandCx
105
52
11 Delay TIme VB TA
Vcc= 5.0V
cL=15pF
50
48
48
!PUl- TRUE OUTPUT (Q)
42
I
~
ln~~wm~~~-u~~
In
10
102
105
36
34
~
90
RX=1 kll
Cx= 100pF
'1. =ISpF
vcc=snv
.....
0
40
36
36
34
32
~
I'
Q
I
!PH - COMPLEIIEHT OUTPUT (Q)
32
-55-:15-15 5 25 045 65 851051251045
Output tw VB T A
100
~
12
42
i"'o
!PUl- TRUE OUTPUT (Q)
I I
I
N--J
"'"
I I
I l.J.....
ipHL - COMPLEMENT OUTPUT (ii)
30
I I
I I I
I
2B
-55-:15-15 5 25 045 65 85 1051251045
TA -AIIBIEHT TEIIPERATURE-CC
Normalized atw vs TA
104_&
Pulse WIdth vs Rx Cx
RX=10kll
Cx=I000pF
-
-- -..,...
I-
-1
Vcc=5.0V
CL= 15pF
TA -AIIBIEHT TEMPERATURE-CC
+2
+1
§.
io Delay TIme vs TA
46
44
Ii!
I\.
Iw - OUTPUT PULSE WIDllt (}As)
2
I
5
44
~
48
~
Vcc -5.OV-'
lwi4~1"
Vcc= 5.5V
1-0...-""""
N'~
Vccl~ ~
I
I I
25
75
TA -AIIBIEHT lEIIPERATURE-CC
125
25
75
TA - AIIBIEHT lEIIPERATURE - CC
125
TIMING CAPACITOR Cx - pF
TL/F/9BI6-7
•
2·521
Input Pulse
f .. 100 kHz
Amp" 30V
1=100nl-
J
Q
WIdth .. 100 ns
t,
5ns
=",;
I.5V
~
1.5V
}
tw
1.5V
tpHL
~
TLlF/9816-8
FIGURE A
2-522
Section 3
Schottky
Section 3-Schottky
Schottky-Commerclal Products
DM74800 Quad 2-lnput NAND Gate..................................................
DM74802 Quad 2-lnput NOR Gate... .... ... .. .... . ... .. ... .. ... . ...... .... ... . .... ..
DM74803 Quad 2-lnput NAND Gate with Open-Collector Outputs.... ........... . ... ... . .
DM74804 Hex Inverter.................. ... .. .. ... ......... .... ........... . ... .. . .. .
DM74805 Hex Inverter with Open-Collector Outputs .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM74808 Quad 2-lnput AND Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM74809 Quad 2-lnput AND Gate with Open-Collector Outputs. . . . . . . . . . . . . . . . . . . . . . . . . .
DM74810 Triple 3-lnput NAND Gate.... ............. ..... ......... . .......... ... ... . .
DM74811 Triple 3-lnput AND Gate ...................................................
DM74820 Dual4-lnput NAND Gate.......... .. ... . . ... ......... .... .. ..... ... ...... ..
DM74830 8-lnput NAND Gate ....................... , ...... '" . ...... .... ..... . ... . .
DM74832 Quad 2-lnput OR Gate.. ...... . ..... ... . . ... ..... . .... .............. .. .... .
DM74840 Dual4-lnput NAND Buffer.. ... .. ..... ... . ... . ..... ... .... .. ..... ...... ... . .
DM74851 Dual2-Wide 2-lnput AND-OR-INVERT Gate .............................. , . . .
DM74864 4-Wide AND-OR-INVERT Gate .............................................
DM74S74 Dual Positive-Edge-Triggered D Flip-Flop with Preset, Clear, and Complementary
Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM74S86 Quad 2-lnput EXCLUSIVE-OR Gate. ... ... .. ... ....... ... . ...... ..... ... ....
DM748109 Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and
Complementary Outputs ..........................................................
DM748112 Dual Negative-Edge-Triggered J-K Flip-Flop with Preset, Clear, and
Complementary Outputs ..........................................................
DM748113 Dual Negative-Edge-Triggered J-K Flip-Flop with Preset and Complementary
Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM74S132 Quad 2-lnput Schmitt Trigger NAND Gate. .... ..... ... ...... .. ... ...... ... ..
DM74S13313-lnput NAND Gate.....................................................
DM74S138 3-to-8 Line Decoder/Demultiplexer. ... ........ ..... ... .... ....... ... ... ....
DM74S139 DuaI2-to-4 Line Decoder/Demultiplexer. .. ........ ..... . ... .. ... .. ... . .... .
DM74S140 Dual4-lnput NAND 500. Line Driver........................................
DM74S151 1-of-8 Line Data Selector/Multiplexer with Complementary Outputs ............
DM74S153 DuaI1-of-4 Line Data Selector/Multiplexer..................................
DM74S157 Quad 2-to-1 Line Data Selector/Multiplexer... ...... .... ........... .........
DM74S158 Quad 2-to-1 Line Inverting Data Selector/Multiplexer. .. ... .. ........ .. ... ....
DM74S161 Synchronous 4-Bit Binary Counter with Asynchronous Clear...................
DM74S163 Synchronous 4-Bit Binary Counter with Synchronous Clear . . . . . . . . . . . . . . . . . . . .
DM7 4S174 Hex D Flip-Flop with Clear.. . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .. . . . . . . . . . . . . .
DM74S175 Quad D Flip-Flop with Clear and Complementary Outputs .................... ,
DM74S181 Arithmetic Logic Unit/Function Generator. . ... ..... . ....... .. ..... ... .. .... .
DM74S182 Look-Ahead Carry Generator .. , ., .. , ... . .... ... .. .... .... ............ ... . .
DM74S194 4-Bit Bidirectional Universal Shift Register.... ..... .......... .. ..... ....... . .
DM74S195 4-Bit Parallel Access Shift Register ........... ,. ............ .. ..... ........ .
DM74S240 Octal TRI-STATE Inverting Buffer/Line Driver/Line Receiver... ..... ..... . ....
DM74S241 Octal TRI-STATE Buffer/Line Driver/Line Receiver. . ......... ..... ...... ....
DM74S244 Octal TRI-STATE Buffer/Line Driver/Line Receiver...... .... .. ..... . ... .....
DM74S251 TRI-STATE 1-of-8 Line Data Selector/Multiplexer with Complementary Outputs ..
DM74S253 Dual TRI-STATE 1-of-4 Line Data Selector/Multiplexer.... ...... .... ...... ...
3-3
3-5
3-7
3-9
3-11
3-13
3-15
3-17
3-19
3-21
3-23
3-25
3-27
3-29
3-31
3-33
3-36
3-38
3-41
3-44
3-47
3-50
3-52
3-52
3-56
3-59
3-63
3-66
3-66
3-71
3-71
3-77
3-77
3-81
3-90
3-94
3-98
3-102
3-102
3-102
3-105
3-109
Section 3-Schottky (Continued)
Schottky-Commercial Products (Continued)
DM74S257 Quad TRI-STATE 2-to-1 Line Data Selector/Multiplexer .......................
DM74S258 Quad TRI-STATE 2-to-1 Line Inverting Data Selector/Multiplexer.. . . . .. . .. .. ..
DM74S280 9-Bit Parity Generator/Checker. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM74S283 4-Bit Binary Adder with Fast Carry ..........................................
DM74S299 TRI-STATE 8-Bit Universal Shift/Storage Register.. .... . . .. .. . .. . . . . . . ... . ..
DM74S373 Octal TRI-STATE Transparent 0 Latch .....................................
DM74S374 Octal TRI-STATE Positive-Edge-Triggered 0 Flip-Flop ........................
DM74S381 Arithmetic Logic Unit/Function Generator ...................................
DM93S00 4-Bit Universal Shift Register. .. . .. .. . .. . .. .. .. . . .. .. . . .. .. ... ..... ..... .. ..
DM93S41 4-Bit Arithmetic LogiC Unit. . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . ..
DM93S43 4-Bit by 2-Bit Twos Complement Multiplier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM93S46 High Speed 6-Bit Identity Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM93S47 High Speed 6-Bit Identity Comparator. ... . . . ... . . . .. . .... .. . .. .. ... ... ... . ...
DM93S62 9-lnput Parity Checker/Generator. . . .. . . . .. .. . .. .. .. .... .. .. ... ... . .. ... . ...
DM96S02 Dual Retriggerable Resettable Monostable Multivibrator (One-Shot) .............
Schottky-Mill Aero Products
DM54S00 Quad 2-lnput NAND Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54S02 Quad 2-lnput NOR Gate ...................................................
DM54S04 Hex Inverter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54S08 Quad 2-lnput AND Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54S10 Triple 3-lnput NAND Gate..................................................
DM54S11 Triple 3-lnput AND Gate ...................................................
DM54S20 Dual 4-lnput NAND Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54S30 8-lnput NAND Gate .......................................................
DM54S32 Quad 2-lnput OR Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54S40 Dual 4-lnput NAND Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54S64 4-Wide AND-OR-INVERT Gate .............................................
DM54S74 Dual Positive-Edge-Triggered 0 Flip-Flop with Preset, Clear, and Complementary
Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54S86 Quad 2-lnput EXCLUSIVE-OR Gate .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54S112 Dual Negative-Edge-Triggered J-K Flip-Flop with Preset, Clear, and
Complementary Outputs ..........................................................
DM54S113 Dual Negative-Edge-Triggered J-K Flip-Flop with Preset and Complementary
Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54S133 13-lnput NAND Gate.....................................................
DM54S138 3-to-8 Line Decoder/Demultiplexer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54S139 DuaI2-to-4 Line Decoder/Demultiplexer....................................
DM54S140 Dual4-lnput NAND 500. Line Driver.. . . . . .. . . .. .. .. ... . . . .. . . . .. . . .. . . .. . . .
DM54S1511-of-8 Line Data Selector/Multiplexer with Complementary Outputs............
DM54S153 DuaI1-of-4 Line Data Selector/Multiplexer..................................
DM54S157 Quad 2-to-1 Line Data Selector/Multiplexer.................................
DM54S158 Quad 2-to-1 Line Inverting Data Selector/Multiplexer. . . . . . . . . . . . . . . . . . . . . . . . .
DM54S161 Synchronous 4-Bit Binary Counter with Asynchronous Clear. . . . . . . . . . . . . . . . . . .
DM54S163 Synchronous 4-Bit Binary Counter with Synchronous Clear....................
DM54S174 Hex 0 Flip-Flop with Clear. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54S175 Quad 0 Flip-Flop with Clear and Complementary Outputs .....................
DM54S181 Arithmetic Logic Unit/Function Generator. ... .... .... .. .. .. . ... .. . .. .... . ...
DM54S182 Look-Ahead Carry Generator.. .. . ... ... .. .. . .. ..... ... .. .. . .. .. .. . .. . ... . .
DM54S194 4-Bit Bidirectional Universal Shift Register.. .. . .. ..... ... .. .. . ... . .. ... . . .. ..
DM54S195 4-Bit Parallel Access Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54S240 Octal TRI-STATE Inverting Buffer/Line Driver/Line Receiver. . .. . .. . .. ..... ...
DM54S241 Octal TRI-STATE Buffer/Line Driver/Line Receiver. .. ... .. .. . . .. . . .. ........
3-112
3-112
3-117
3-121
3-125
3-130
3-130
3-135
3-139
3-142
3-149
3-153
3-157
3-160
3-165
3-3
3-5
3-9
3-13
3-17
3-19
3-21
3-23
3-25
3-27
3-31
3-33
3-36
3-41
3-44
3-50
3-52
3-52
3-56
3-59
3-63
3-66
3-66
3-71
3-71
3-77
3-77
3-81
3-90
3-94
3-98
3-102
3-102
Section 3-Schottky (Continued)
Schottky-Mill Aero Products (Continued)
DM54S244 Octal TRI-STATE Buffer/Line Driver/Line Receiver..... ..... ..... ...........
DM54S251 TRI-STATE 1-of-8 Line Data Selector/Multiplexer with Complementary Outputs..
DM54S253 Dual TRI-STATE 1-of-4 Line Data Selector/Multiplexer... ... .. .. ... ..........
DM54S257 Quad TRI-STATE 2-to-1 Line Data Selector/Multiplexer... ..... ..... ...... ....
DM54S258 Quad TRI-STATE 2-to-1 Line Inverting Data Selector/Multiplexer. ........ .....
DM54S280 9-Bit Parity Generator/Checker. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM54S283 4-Bit Binary Adder with Fast Carry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM54S373 Octal TRI-STATE TransparentD Latch......... .... .. .... .... ... ....... . .•.
DM54S374 Octal TRI-STATE Positive-Edge-Triggered D Flip-Flop.. .... .... .. . ....... . ...
3-102
3-105
3-109
3-112
3-112
3-117
3-121
3-130
3-130
,---------------------------------------------------------------------, o
~
o
~National
~ Semiconductor
DM54S00/DM74S00 Quad 2-lnput NAND Gates
General Description
This device contains four independent gates each of which
performs the logic NAND function.
Connection Diagram
Dual·ln·Llne Package
Vee
B4
A4
Al
Bl
VI
V4
A2
B]
A]
V]
B2
Y2
GND
TL/F/6489-1
Order Number DM54S00J, DM54S00W, DM74S00M or DM74S00N
See NS Package Number J14A, M14A, N14A or W14B
Function Table
y= AB
Inputs
Output
A
B
Y
L
L
H
H
L
H
L
H
H
H
L
H
H = High Logic Level
L = Low Logic Level
II
3·3
Absolute Maximum Ratings
(Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual devIce operation.
" Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
-55·Cto +125·C
DM54S
O·Cto +70·C
DM74S
Storage Temperature Range
-65·Cto + 1500C
Recommended Operating Conditions
Symbol
DM54S00
Parameter
DM74S00
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
0.8
0.8
V
IOH
High Level Output Current
-1
-1
mA
20
mA
70
·C
2
IOL
Low Level Output Current
TA
Free Air Operating Temperature
2
V
20
-55
125
V
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Min
Typ
(Note 1)
DM54
2.5
3.4
DM74
2.7
3.4
Conditions
Parameter
VI
Input Clamp Voltage
Vee = Min, 11= -18 mA
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
VIL = Max
VOL
Low Level Output
Voltage
Vee = Min, 10L = Max
VIH = Min
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 5.5V
I
I
Max
Units
-1.2
V
V
0.5
V
1
mA
IIH
High Level Input Current
Vee = Max, VI = 2.7V
50
",A
IlL
Low Level Input Current
Vee = Max, VI = 0.5V
-2
mA
los
Short Circuit
Output Current
Vee = Max
(Note 2)
ICCH
Supply Current with
Outputs High
Vee = Max
leeL
Supply Current with
Outputs Low
Vee = Max
Switching Characteristics at Vee =
I
I
DM54
-40
-100
DM74
-40
-100
mA
10
16
mA
20
36
mA
5V and T A = 25·C (See Section 1 for Test Waveforms and Output Load)
RL = 280.(1
Symbol
Parameter
CL = 15pF
Units
CL = 50pF
Min
Max
Min
Max
tpLH
Propagation Delay Time
Low to High Level Output
2
4.5
2
7
ns
tpHL
Propagation Delay Time
High to Low Level Output
2
5
2
8
ns
Note 1: All typicals are at Vee = SV, TA = 2S'C.
Note 2: Not more than one output should be shorted at a time and the duration should nol exceed one second.
3-4
~National
~ Semiconductor
DM54S02/DM74S02 Quad 2-lnput NOR Gates
General Description
This device contains four independent gates each of which
performs the logic NOR function.
Connection Diagram
Dual-In-Line Package
Vee
14
Yl
84
Y4
A4
AI
Y3
11
12
13
A2
Y2
81
83
A3
82
GND
10
Order Number DM54S02J, DM54S02W or DM74S02N
See NS Package Number J14A, N14A or W14B
Function Table
Y=A+B
Inputs
Output
A
B
Y
L
L
H
H
L
H
L
H
H
L
L
L
H
~
High Logic Level
L
~
Low Logic Level
3-5
TUF/6490-1
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
Input Voltage
Note: The ''Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the ''Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
7V
5.5V
Operating Free Air Temperature Range
DM54S
- 55'C to + 125'C
DM74S
O'Cto +70'C
Storage Temperature Range
-65'Cto + 150"C
Recommended Operating Conditions
Symbol
DM54S02
Parameter
DM74S02
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
Vcc
Supply Voltage
VIH
High Level Input Voltage
Vil
Low Level Input Voltage
0.8
0.8
V
2
2
V
10H
High Level Output Current
-1
-1
mA
10l
Low Level Output Current
20
20
mA
TA
Free Air Operating Temperature
70
'C
-55
125
0
Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
Min
Typ
(Note 1)
DM54
2.5
3.4
DM74
2.7
3.4
Conditions
= Min, II = -18 rnA
= Max I
VI
Input Clamp Voltage
Vcc
VOH
High Level Output
Voltage
Vcc = Min, 10H
Vil = Max
VOL
Low Level Output
Voltage
Vcc = Min, 10l = Max
VIH = Min
II
Input Current @ Max
Input Voltage
Vee
I
Units
-1.2
V
V
= Max, VI = 5.5V
= Max, VI = 2.7V
= Max, VI = 0.5V
Vcc = Max
Max
0.5
V
1
rnA
IIH
High Level Input Current
Vee
50
/LA
III
Low Level Input Current
Vcc
-2
mA
lOS
Short Circuit
Output Current
(Note 2)
I
I
DM54
-40
-100
DM74
-40
-100
mA
ICCH
Supply Current with
Outputs High
Vcc
= Max
17
29
mA
ICCl
Supply Current with
Outputs Low
Vcc
= Max
26
45
mA
Switching Characteristics at Vee = 5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
Rl = 2800
Symbol
Parameter
Units
CL = 15pF
CL = 50pF
Min
Max
Min
Max
tplH
Propagation Delay Time
Low to High Level Output
1.5
5.5
2
7.5
ns
tpHl
Propagation Delay Time
High to Low Level Output
1.5
5.5
2
7.5
ns
Note 1: All typlcals are at Vee = SV, TA = 2S'C.
Nole 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
3-6
~National
~ Semiconductor
DM74S03 Quad 2-lnput NAND Gates
with Open-Collector Outputs
General Description
Pull-Up Resistor Equations
This device contains four independent gates each of which
performs the logic NAND function. The open-collector outputs require external pull-up resistors for proper logical operation.
R
Vee (Min) - VOH
MAX = N1 (lOH) + N2 (lIH)
R
Vee (Max) - VOL
IOL - N3 (lIU
MIN =
Where: N1 (IOH) = total maximum output high current for all
outputs tied to pull-up resistor
N2 (IIH) = total maximum input high current for all
inputs tied to pull-up resistor
N3 (lIU = total maximum input low current for all
inputs tied to pull-up resistor
Connection Diagram
Dual-ln-L1ne Package
Vee
14
AI
84
A4
BI
V4
12
13
83
11
VI
A2
A3
V3
V2
GND
10
B2
TL/F/6491-1
Order Number DM74S03N
See NS Package Number N14A
Function Table
y= AB
Inputs
Output
A
B
Y
L
L
H
H
L
H
L
H
H
H
H
L
H = High Logic Level
L = Low logic Level
3-7
•
Absolute Maximum Ratings
(Note)
Supply Voltage
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
7V
5.5V
Input Voltage
Output Voltage
7V
Operating Free Air Temperature Range
DM74S
O'Cto +70"C
Storage Temperature Range
-55'Cto + 150"C
Recommended Operating Conditions
Symbol
DM74S03
Parameter
Units
Min
Nom
Max
4.75
5
5.25
V
Vee
Supply Voltage
VIH
High Level Input Voltage
Vil
Low Level Input Voltage
0.8
V
VOH
High Level Output Voltage
5.5
V
20
mA
70
'C
2
IOl
Low Level Output Current
TA
Free Air Operating Temperature
V
0
Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
Conditions
Typ
(Note 1)
Min
Max
Units
VI
Input Clamp Voltage
Vee = Min, 11= -18 mA
-1.2
V
ICEX
High Level Output
Current
Vee = Min, Vo = 5.5V
Vil = Max
250
/LA
VOL
Low Level Output
Voltage
Vee = Min, IOl = Max
VIH = Min
0.5
V
II
Input Current @ Max
Input Voltage
Vcc = Max, VI = 5.5V
1
mA
IIH
High Level Input Current
Vcc = Max, VI = 2.7V
50
/LA
III
Low Level Input Current
Vcc = Max, VI = 0.5V
-2
mA
ICCH
Supply Current with
Outputs High
Vee = Max
6.0
13.2
rnA
ICCl
Supply Current with
Outputs Low
Vee = Max
20
36
mA
Switching Characteristics at Vee =
5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
RL = 2800
Symbol
Parameter
CL = 15pF
Units
CL=50pF
Min
Max
Min
Max
tpLH
Propagation Delay Time
Low to High Level Output
2
7.5
3
11
ns
tpHl
Propagation Delay Time
High to Low Level Output
2
7
3
11
ns
Note 1: All typicals are at Vee = 5V, TA = 25'C.
3-8
~National
~ Semiconductor
DM54S04/DM74S04 Hex Inverting Gates
General Description
This device contains six independent gates each of which
performs the logic INVERT function.
Connection Diagram
Dual·ln·Llne Package
VC;(:
14
Al
A6
V6
lJ
12
A2
VI
AS
VS
II
A4
V4
Y3
GND
10
Y2
A3
Order Number DM54S04J, DM54S04W, DM74S04M or DM74S04N
See NS Package Number J14A, M14A, N14A or W14B
Function Table
V=A
Input
Output
A
V
L
H
L
H
H
= High Logic Level
L = Low Logic Level
3-9
TL/F/6442-1
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "E/ectrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Input Voltage
5.5V
Operating Free Air Temperature Range
DM54S
- 55'C to + 125'C
DM74S
O'Cto +70'C
Storage Temperature Range
-65'Cto + 150'C
Recommended Operating Conditions
Symbol
Vee
Supply Voltage
VIH
High Level Input Voltage
DM74S04
DM54S04
Parameter
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
V
V
2
Vil
Low Level Input Voltage
0.8
0.8
V
iOH
High Level Output Current
-1
-1
mA
10l
Low Level Output Current
20
20
mA
TA
Free Air Operating Temperature
70
·C
-55
0
125
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Min
Typ
(Note 1)
DM54
2.5
3.4
DM74
2.7
3.4
Conditions
VI
Input Clamp Voltage
Vee = Min,ll = -18 mA
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
VIL = Max
VOL
Low Level Output
Voltage
Vee = Min, 10L = Max
VIH = Min
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 5.5V
I
I
Max
Units
-1.2
V
V
0.5
V
1
mA
IIH
High Levellnput'Current
Vee = Max, VI = 2.7V
50
/LA
IlL
Low Level Input Current
Vee = Max, VI = 0.5V
-2
mA
los
Short Circuit
Output Current
Vee = Max
(Note 2)
leeH
Supply Current with
Outputs High
Vcc = Max
ICCl
Supply Current with
Outputs Low
Vee = Max
Switching Characteristics at Vee =
I
I
DM54
-40
-100
DM74
-40
-100
mA
15
24
mA
30
54
mA
5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
RL = 2800
Symbol
tpLH
Parameter
Propagation Delay Time
Low to High Level Output
CL=15pF
CL = 50pF
Units
Min
Max
Min
Max
2
4.5
2
7
ns
8
ns
Propagation Delay Time
2
5
2
High to Low Level Output
Note 1: All typlcals are at Vee = SV, TA = 2S"C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
tpHL
3-10
CJ)
Q
U1
~National
~ Semiconductor
DM74S05 Hex Inverters
with Open-Collector Outputs
General Description
Pull-Up Resistor Equations
This device contains six independent gates each of which
performs the logic INVERT function. The open-collector outputs require external pull-up resistors for proper logical operation.
R
- Vee (Min) - VOH
MAX - Nl (lOH) + N2 (lIH)
R
MIN =
Vee (Max) - VOL
IOL - N3(11Ll
Where: Nl (lOH) = total maximum output high current for all
outputs tied to pull-up resistor
N2 (lIH) = total maximum input high current for all
inputs tied to pull-up resistor
N3 (11Ll = total maximum input low current for all
inputs tied to pull-up resistor
Connection Diagram
Dual-In-Llne Package
Vee
14
AI
AS
V6
A6
12
13
A2
Vl
V5
A4
V4
V3
GND
10
"
A3
V2
TLlF/6443-1
Order Number DM74S05M or DM74S05N
See NS Package Number M14A or N14A
Function Table
Y=A
Input
Output
A
Y
L
H
L
H
H = High Logic Level
L
= Low Logic Level
3-11
&I
Absolute Maximum Ratings (Note)
Supply Voltage
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
7V
Input Voltage
5.5V
Output Voltage
7V
Operating Free Air Temperature
Range
O·Cto +70·C
Storage Temperature Range
- 65·C to + 150·C
Recommended Operating Conditions
Symbol
Parameter
Min
Nom
Max
Units
4.75
5
5.25
V
Vil
Low Level Input Voltage
0.8
V
VOH
High Level Output Voltage
5.5
V
IOl
Low Level Output Current
20
mA
TA
Free Air Operating Temperature
70
·c
Vee
Supply Voltage
VIH
High Level Input Voltage
2
V
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Typ
(Note 1)
Min
Max
Units
VI
Input Clamp Voltage
Vee = Min, 11= -18 mA
-1.2
V
leEX
High Level Output
Current
Vee = Min, Vo = 5.5V
Vil = Max
250
p.A
VOL
Low Level Output
Voltage
Vee = Min, IOl = Max
VIH = Min
0.5
V
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 5.5V
1
mA
IIH
High Level Input Current
Vee = Max, VI = 2.7V
50
p.A
III
Low Level Input Current
Vee = Max, VI = 0.5V
-2
mA
ICCH
Supply Current with
Outputs High
Vee = Max
9
19.8
mA
ICCl
Supply Current with
Outputs Low
Vee = Max
30
54
mA
Switching Characteristics at Vcc =
5V and T A = 25·C (See Section 1 for Test Waveforms and Output Load)
RL = 2800.
Symbol
Parameter
CL = 15pF
CL=50pF
Units
Min
Max
Min
Max
tplH
Propagation Delay Time
Low to High Level Output
2
7.5
3
11
ns
tpHl
Propagation Delay Time
High to Low Level Output
2
7
3
11
ns
Note 1: All Iypicals are al Vee = SV, TA = 2S'C.
3-12
~National
~ Semiconductor
DM54S08/DM74S08 Quad 2-lnput AND Gates
General Description
This device contains four independent gates each of which
performs the logic AND function.
Connection Diagram
Dual·in·Llne Package
Vee
A1
V4
A4
84
A2
V1
81
BJ
82
AJ
V2
VJ
GND
TLlF/6444-1
Order Number DM54S08J, DM54SD8W or DM74S08N
See NS Package Number J14A, N14A or W14B
Function Table
y= AB
Inputs
Output
A
B
Y
L
L
H
H
L
H
l
H
L
l
l
H
H
~
High Logic Level
L
~
Low Logic Level
•
3·13
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Note: The "Absolute Maximum Ratings" are those valuss
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric valuss defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum raUngs.
The "Recommended Operating CondiUons" table will define
the condiUons for actual device operation.
Operating Free Air Temperature Range
DM54S
- 55'C to + 125'C
DM74S
O'Cto +70'C
Storage Temperature Range
-65'C to + 150'C
Recommended Operating Conditions
Symbol
Vee
DM74S08
DM54S08
Parameter
Supply Voltage
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
VIH
High Level Input Voltage
2
2
Vil
Low Level Input Voltage
0.8
0.8
V
V
10H
High Level Output Current
-1
-1
mA
20
mA
70
'C
20
10l
Low Level Output Current
TA
Free Air Operating Temperature
-55
125
0
Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
Min
Typ
(Note 1)
DM54
2.5
3.4
DM74
2.7
3.4
Conditions
= Min, II = -18 mA
= Max I
VI
Input Clamp Voltage
Vee
VOH
High Level Output
Voltage
Vee = Min, 10H
Vil = Max
VOL
Low Level Output
Voltage
Vee = Min, 10l
VIH = Min
II
Input Current @ Max
Input Voltage
Vee
I
Units
-1.2
V
V
= Max
= Max, VI = 5.5V
= Max, VI = 2.7V
= Max, VI = 0.5V
Vee = Max
Max
0.5
V
1
mA
IIH
High Level Input Current
Vee
50
p.A
III
Low Level Input Current
Vee
-2
mA
los
Short Circuit
Output Current
(Note 2)
I
I
DM54
-40
-100
DM74
-40
-100
mA
ICCH
Supply Current with
Outputs High
Vee
= Max
18
32
mA
leel
Supply Current with
Outputs Low
Vee
= Max
32
57
mA
Switching Characteristics at Vee = 5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
RL
Symbol
Parameter
CL
= 2800
= 15pF
CL
= 50pF
Units
Min
Max
Min
Max
tplH
Propagation Delay Time
Low to High Level Output
2.5
7
3
9
ns
tpHl
Propagation Delay Time
High to Low Level Output
2.5
7.5
3
11
ns
Nate 1: All typlcals are at Vee = 5V, TA = 25'C.
Nate 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
3-14
,---------------------------------------------------------------------,
~National
~ Semiconductor
DM74S09 Quad 2-lnput AND Gates
with Open-Collector Outputs
General Description
Pull-Up Resistor Equations
This device contains four independent gates each of which
performs the logic AND function. The open·collector outputs require an external pull-up resistor for proper logical
operation.
R
Vcc (Min) - VOH
MAX = N1 (IOH)
+ N2 (IIH)
_
V""CC,,-,-{M....:ax--:-:-)--:-:-V.."O""L
RMIN =
IOL - Ns {IILl
Where: N1 (IOH) = total maximum output high current for all
outputs tied to pull-up resistor
N2 (IIH) = total maximum input high current for all
inputs tied to pull-up resistor
Ns {IILl = total maximum input low current for all
inputs tied to pull-up resistor
Connection Diagram
Dual-In-Llne Package
vee
14
AI
04
A4
12
13
01
Y4
03
11
A2
YI
02
Function Table
Y = AB
Output
A
B
Y
L
L
H
H
L
H
L
H
L
L
L
H
H = High Logic Level
L = Low Logic Level
3-15
Y3
Y2
GND
10
Order Number DM74S09N
See NS Package Number N14A
Inputs
A3
TL/F/6465-1
~
~
Absolute Maximum Ratings
(Note)
Supply Voltage
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum raungs.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
7V
Input Voltage
5.5V
Output Voltage
7V
Operating Free Air Temperature Range
DM74S
O·Cto +70·C
- 65·C to + 150·C
Storage Temperature Range
Recommended Operating Conditions
Symbol
DM74S09
Parameter
Units
Min
Nom
Max
4.75
5
5.25
V
V
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
0.8
VOH
High Level Output Voltage
5.5
V
IOL
Low Level Output Current
20
mA
TA
Free Air Operating Temperature
70
·c
V
2
0
Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
Conditions
Typ
(Note 1)
Min
Max
Units
VI
Input Clamp Voltage
Vee = Min, 11= -18mA
-1.2
V
leEX
High Level Output
Current
Vee = Min, Vo = 5.5V
VIH = Min
250
/LA
VOL
Low Level Output
Voltage
Vee = Min, IOL = Max
VIL = Max
0.5
V
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 5.5V
1
mA
IIH
High Level Input Current
Vee = Max, VI = 2.7V
50
/LA
III
Low Level Input Current
Vee = Max, VI = 0.5V
-2
mA
ICCH
Supply Current with
Outputs High
Vee = Max
18
32
mA
ICCl
Supply Current with
Outputs Low
VCC = Max
32
57
mA
Switching Characteristics at Vec =
5V and TA = 25·C (See Section 1 for Test Waveforms and Output Load)
RL = 2800.
Symbol
Parameter
CL = 15pF
CL = 50pF
Units
Min
Max
Min
Max
tpLH
Propagation Delay Time
Low to High Level Output
3
10
4
18
ns
tpHL
Propagation Delay Time
High to Low Level Output
3
10
4
18
ns
Note 1: All typlcals are at Vee
= 5V, TA = 25"C.
3-16
en
....
C)
~National
~ Semiconductor
DM54S10/DM74S10 Triple a-Input NAND Gates
General Description
This device contains three independent gates each of which
performs the logic NAND function.
Connection Diagram
Dual-In-Llne Package
Vee
1~4
Cl
VI
13
C3
83
11
12
'--
A3
1
2
~
3
81
8
9
10
-----I
AI
V3
4
A2
82
5
C2
~
J: J:
Order Number DM54S10J, DM54S10W or DM74S10N
See NS Package Number J14A, N14A or W14B
Function Table
y= ABC
Inputs
Output
A
B
C
Y
X
X
X
L
L
L
H
X
X
X
H
H
H
H
H
L
H
~
High Logic Level
L
~
Low Logic Level
X
~
Either Low or High Logic Level
3-17
TL/F/6446-1
...
o
CI)
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Input Voltage
5.5V
Operating Free Air Temperature Range
DM54S
- 55'C to + 125'C
DM74S
O'Cto +70'C
Storage Temperature Range
-55'Cto + 150'C
Recommended Operating Conditions
Symbol
DM54S10
Parameter
DM74S10
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
Vee
Supply Voltage
VIH
High Level Input Voltage
Vil
Low Level Input Voltage
0.8
0.8
V
10H
High Level Output Current
-1
-1
mA
20
mA
70
'C
2
2
10l
Low Level Output Current
TA
Free Air Operating Temperature
V
20
-55
125
0
Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
Min
Typ
(Note 1)
DM54
2.5
3.4
DM74
2.7
3.4
Conditions
Max
Units
-1.2
V
VI
Input Clamp Voltage
VOH
High Level Output
Voltage
Vee = Min, IOH = Max
Vil = Max
VOL
Low Level Output
Voltage
Vee = Min, IOl = Max
VIH = Min
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 5.5V
IIH
High Level Input Current
Vee = Max, VI = 2.7V
50
p.A
III
Low Level Input Current
Vee = Max, VI = 0.5V
-2
mA
los
Short Circuit
Output Current
Vcc = Max
(Note 2)
ICCH
Supply Current with
Outputs High
Vee = Max
ICCl
Supply Current with
Outputs Low
Vee = Max
Vee = Min, 11= -18mA
Switching Characteristics at Vee =
I
I
I
I
V
0.5
V
1
mA
DM54
-40
-100
DM74
-40
-100
mA
7.5
12
mA
15
27
mA
5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
RL = 2800
Symbol
Parameter
CL = 1SpF
CL = SOpF
Units
Min
Max
Min
Max
tplH
Propagation Delay Time
Low to High Level Output
2
4.5
2
7
ns
tpHl
Propagation Delay Time
High to Low Level Output
2
5
2
8
ns
Nole 1: All typlcals are at Vee = 5V, TA = 25'C.
Nole 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
3-18
....
....
r---------------------------------------------------------------------~0
~National
~ Semiconductor
DM54S11/DM74S11 Triple a-Input AND Gates
General Description
This device contains three independent gates each of which
performs the logic AND function.
Connection Diagram
Dual-In-Line Package
Cl
vr;4
13
83
C3
VI
11
12
V3
A3
~
'--
>j
-I
2
1
4
3
5
Jz
6
Al
81
8
9
10
AZ
82
C2
J:
Order Number DM54S11J, DM54S11Wor DM74S11N
See NS Package Number J14A, N14A or W14B
Function Table
Y = ABC
Inputs
Output
A
B
C
Y
X
X
L
H
X
L
X
H
L
X
X
H
L
L
L
H
H = High l.ogle Level
L = Law Lagle Level
X = Either Low or High Lagle Level
3-19
TL/F/6447-1
........
en
AbsQlute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be opereted at these limits. The
parametric values defined in the "£Ieetrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
DM54S
- 55'C to + 125'C
DM74S
O'Cto +70'C
Storage Temperature Range
- 65'C to + 150'C
Recommended Operating Conditions
Symbol
Vee
Supply Voltage
DM74S11
DM54S11
Parameter
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
VIH
High Level Input Voltage
Vil
Low Level Input Voltage
0.8
2
0.8
V
10H
High Level Output Current
-1
-1
mA
10l
Low Level Output Current
20
20
mA
TA
Free Air Operating Temperature
70
'C
2
-55
125
V
0
Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
Min
Typ
(Note 1)
DM54
2.5
3.4
DM74
2.7
3.4
Conditions
= Min, II =
Max
Units
-1.2
V
VI
Input Clamp Voltage
Vec
VOH
High Level Output
Voltage
Vcc = Min, 10H
VIH = Min
= Max
Val
Low Level Output
Voltage
Vcc = Min, 10l
Vil = Max
= Max
II
Input Current @ Max
Input Voltage
Vcc
IIH
High Level Input Current
Vcc
50
p.A
III
Low Level Input Current
Vee
-2
mA
los
Short Circuit
Output Current
(Note 2)
-18 mA
I
I
V
= Max, VI = 5.5V
= Max. VI = 2.7V
= Max, VI = 0.5V
Vcc = Max
I
I
0.5
V
1
mA
DM54
-40
-100
DM74
-40
-100
mA
ICCH
Supply Current with
Outputs High
Vcc
= Max
13.5
24
mA
ICCl
Supply Current with
Outputs Low
Vcc
= Max
24
42
mA
SWitching Characteristics at Vcc = 5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
Rl
Symbol
tplH
Parameter
Propagation Delay Time
Low to High Level Output
CL
= 2800
= 15pF
CL
= 50pF
Units
Min
Max
Min
Max
2.5
7
3
9
ns
11
ns
Propagation Delay Time
2.5
7.5
3
High to Low Level Output
Note 1: All typical. are at Vee - 5V, TA - 25'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
tpHl
3-20
r---------------------------------------------------------------------~~
~
~National
~ Semiconductor
DM54520/DM74520 Dual 4-lnput NAND Gates
General Description
This device contains two independent gates each of which
performs the logic NAND function.
Connection Diagram
Dual-In-Llne Package
C2
02
13
NC
82
111
12
A2
V2
10
-~
Al
J:
81
CI
01
VI
TLIFI6449-1
Order Number DM54S20J, DM54S20W or DM74S20N
See NS Package Number J14A, N14A or W14B
Function Table
y = ABCD
Inputs
Output
A
B
C
D
Y
X
X
X
L
X
X
L
X
X
L
X
X
L
X
X
X
H
H
H
H
H H H H
L
= High Logic Level
L = Low Logic Level
X = Either Low or High Logic Level
H
3-21
•
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safely of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
- 55·C to + 125·C
DM54S
O·Cto +70·C
DM74S
Storage Temperature Range
-65·Cto + 150·C
Recommended Operating Conditions
Symbol
DM54S20
Parameter
DM74S20
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
Vee
Supply Voltage
VIH
High Level Input Voltage
Vil
Low Level Input Voltage
0.8
0.8
V
IOH
High Level Output Current
-1
-1
mA
10l
Low Level Output Current
20
20
mA
TA
Free Air Operating Temperature
70
·C
2
2
-55
125
V
0
Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
Min
Typ
(Note 1)
DM54
2.5
3.4
DM74
2.7
3.4
Conditions
VI
Input Clamp Voltage
Vee = Min,ll = -18 mA
VOH
High Level Output
Voltage
Vee = Min,loH = Max
Vil = Max
VOL
Low Level Output
Voltage
Vee = Min, 10l = Max
VIH = Min
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 5.5V
I
I
Max
Units
-1.2
V
V
0.5
V
1
mA
IIH
High Level Input Current
Vee = Max, VI = 2.7V
50
~
ill
Low Level Input Current
Vee = Max, VI = 0.5V
-2
mA
los
Short Circuit
Output Current
Vee = Max
(Note 2)
ICCH
Supply Current with
Outputs High
Vce = Max
leel
Supply Current with
Outputs Low
Vee = Max
Switching Characteristics at Vee =
I
I
DM54
-40
-100
DM74
-40
-100
mA
5
8
mA
10
18
mA
5V and TA = 25·C (see Section 1 for Test Waveforms and Output Load)
RL = 2800
Symbol
Parameter
CL = 15pF
Units
CL = 50pF
Min
Max
Min
Max
tplH
Propagation Delay Time
Low to High Level Output
2
4.5
2
7
ns
tpHl
Propagation Delay Time
High to Low Level Output
2
5
2
8
ns
are at Vee = 5V. TA = 25"C.
than one output should be shorted o.t a time. and the duration should not exceed one second.
Note 1: Alllypicals
Note 2: Not more
3-22
.---------------------------------------------------------------------~0
~
~National
~ Semiconductor
DM54S30/DM74S30 B-Input NAND Gate
General Description
This device contains a single gate which performs the logic
NAND function.
Connection Diagram
Dual·ln·Line Package
vIC
114
H
NC
113
11
D
C
A
v
G
12
TL/F/6451-1
Order Number DM54S30J, DM54S30W or DM74S30N
See NS Package Number J14A, N14A or W14B
Function Table
Y = ABCDEFGH
Inputs
Output
AthruH
Y
All InpulsH
One or More
InpulL
L
H
H
~
High Logic Level
L
~
Low Logic Level
•
3·23
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Input Voltage
5.5V
Operating Free Air Temperature Range
-55·C to + 125·C
DM54S
DM74S
O·Cto +70·C
-65·Cto + 150·C
Storage Temperature Range
Recommended Operating Conditions
Symbol
DM74S30
DM54S30
Parameter
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
0.8
0.8
V
10H
High Level Output Current
-1
-1
mA
10L
Low Level Output Current
20
20
mA
TA
Free Air Operating Temperature
125
70
·C
2
V
2
-55
0
Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
Min
Typ
(Note 1)
DM54
2.5
3.4
DM74
2.7
3.4
Conditions
Max
Units
-1.2
V
VI
Input Clamp Voltage
VOH
High Level Output
Voltage
= Min. II = -18 mA
Vee = Min. IOH = Max I
VIL = Max
VOL
Low Level Output
Voltage
Vee = Min. IOL
VIH = Min
II
Input Current @ Max
Input Voltage
Vee
IIH
High Level Input Current
Vee
50
/J- A
III
Low Level Input Current
Vee
-2
mA
los
Short Circuit
Output Current
(Note 2)
Vee
I
V
= Max
= Max. VI = 5.5V
= Max. VI = 2.7V
= Max. VI = 0.5V
Vee = Max
I
I
0.5
V
1
mA
DM54
-40
-100
DM74
-40
-100
mA
ICCH
Supply Current with
Outputs High
Vee
= Max
3
5
mA
leel
Supply Current with
Outputs Low
Vee
= Max
5.5
10
mA
Switching Characteristics at Vee = 5V and TA = 25·C (See Section 1 for Test Waveforms and Output Load)
RL = 2800
Symbol
Parameter
Units
CL = 50pF
CL = 15pF
Min
Max
Min
Max
tpLH
Propagation Delay Time
Low to High Level Output
2
6
2
8
ns
tpHL
Propagation Delay Time
High to Low Level Output
2
7
3
10
ns
Note 1: All typical. are at Vee = 5V. TA = 25'C.
Note 2: Not more than one output should be shorted at a time. and the duration should not exceed one second.
3-24
,---------------------------------------------------------------------, 0
fd
~National
~ Semiconductor
DM54S32/DM74S32 Quad 2-lnput OR Gates
General Description
This device contains four independent gates each of which
performs the logic OR function.
Connection Diagram
Dual-In-Llne Package
vee
B4
A1
B1
A4
Y4
B3
A2
B2
Y3
Y2
GND
TL/F16452-1
Order Number DM54S32J, DM54S32W or DM74S32N
See NS Package Number J14A, N14A or W14B
Function Table
Y=A+B
Inputs
Output
A
B
Y
L
L
H
L
H
L
H
H
H
L
H
H
H = High Logic Level
L
= Low Logic Level
3-25
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
Input Voltage
Note: The "Absolute Maxiinum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
7V
5.5V
Operating Free Air Temperature Range
DM54S
- 55'C to + 125'C
DM74S
O'Cto +700C
- 65·C to + 150·C
Storage Temperature Range
Recommended Operating Conditions
Symbol
Vec
Supply Voltage
VIH
High Level Input Voltage
DM74S32
DM54S32
Parameter
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
2
V
V
Vil
Low Level Input Voltage
0.8
0.8
V
10H
High Level Output Current
-1
-1
mA
20
mA
70
·c
10l
Low Level Output Current
TA
Free Air Operating Temperature
20
-55
125
0
Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol
Min
Typ
(Note 1)
DM54
2.5
3.4
DM74
2.7
3.4
Conditions
Parameter
Max
Units
-1.2
V
VI
Input Clamp Voltage
Vee = Min, 11= -18 mA
VOH
High Level Output
Voltage
Vcc = Min, 10H = Max
VIH = Min
VOL
Low Level Output
Voltage
Vec = Min, 10l = Max
Vil = Max
II
Input Current @ Max
Input Voltage
Vec = Max, VI = 5.5V
IIH
High Level Input Current
Vee = Max, VI = 2.7V
50
p.A
III
Low Level Input Current
Vee = Max, VI = 0.5V
-2
mA
loS
Short Circuit
Output Current
Vcc = Max
(Note 2)
lecH
Supply Current with
Outputs High
Vcc = Max
ICCl
Supply Current with
Outputs Low
Vcc = Max
Switching Characteristics at Vcc =
I
J
I
I
V
0.5
V
1
mA
DM54
-40
-100
DM74
-40
-100
mA
18
32
mA
38
68
mA
5V and TA = 25·C (See Section 1 for Test Waveforms and Output Load)
RL = 2800
Symbol
tplH
Parameter
Propagation Delay Time
Low to High Level Output
Propagation Delay Time
High to Low Level Output
Nola 1: All typicals are at Vee = SV. TA = 2S'C.
tpHl
CL = 50pF
CL=15pF
Units
Min
Max
Min
Max
2
7
2
9
ns
2
7
2
9
ns
Note 2: Not more than one output should be shorted at a time. and the duration should not exceed one second.
3-26
~National
~ Semiconductor
DM54S40/DM74S40 Dual 4-lnput NAND Buffers
General Description
This device contains two independent gates each of which
performs the logic NAND function.
Connection Diagram
Dual·ln·Llne Package
C2
02
A2
82
NrC
II
12
13
V2
10
~
2
I
81
Al
J:
&
4
Cl
6
J1
01
J:
TL/F/6453-1
Order Number DM54S40J, DM54S40W or DM74S40N
See NS Package Number J14A, N14A or W16B
Function Table
y = ABCD
Inputs
Output
D
Y
X
L
L
X
X
X
H
H
H
H
H
A
B
C
X
X
X
X
X
L
L
X
H
X
X
H
H
L
= High logic Level
L = Low logic Level
X = Either Low or High logic Level
H
•
3·27
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Input Voltage
5.5V
Operating Free Air Temperature Range
DM54S
- 55'C to + 125'C
DM74S
O'Cto +70'C
Storage Temperature Range
- 65'C to + 150'C
Recommended Operating Conditions
Symbol
DM54S40
Parameter
DM74S40
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
0.8
0.8
V
10H
High Level Output Current
-3
-3
mA
10L
Low Level Output Current
60
60
mA
TA
Free Air Operating Temperature
70
'C
2
2
-55
125
V
V
0
Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
Conditions
Typ
(Note 1)
Min
Max
Units
-1.2
V
VI
Input Clamp Voltage
Vee = Min, 11= -18 mA
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
VIL = Max
VOL
Low Level Output
Voltage
Vee = Min, 10L = Max
VIH = Min
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 5.5V
IIH
High Level Input Current
Vee
IlL
Low Level Input Current
= Max, VI =
Vee = Max, VI =
los
Short Circuit
Output Current
Vee = Max
(Note 2)
ICCH
Supply Current with
Outputs High
Vee
= Max
10
18
mA
leel
Supply Current with
Outputs Low
Vee
= Max
25
44
mA
I
I
DM54
2.5
3.4
DM74
2.7
3.4
V
0.5
V
1
mA
2.7V
100
/lA
0.5V
-4
mA
I
I
Switching Characteristics at Vee = 5V and TA =
DM54
-50
-225
DM74
-50
-225
mA
25'C (See Section 1 for Test Waveforms and Output Load)
Rl = 930.
Parameter
Symbol
Cl
= 50pF
CL = 150pF
Units
Min
Max
Min
Max
tplH
Propagation Delay Time
Low to High Level Output
2
6.5
3
9
ns
tpHl
Propagation Delay Time
High to Low Level Output
2
6.5
3
9
ns
Note 1: All typIcals are at Vee
~
5V, TA ~ 25'C.
Note 2: Not more than one output should be shorted at a time. and the duration should not exceed one second.
3-28
~National
~ Semiconductor
DM74S51 Dual 2-Wide 2-lnput
AND-OR-INVERT Gates
General Description
This device contains two Independent combinations of
gates each of which performs the logic AND·OR·INVERT
function.
Connection Diagram
Dual-In-Llne Package
MAKE NO EXTERNAL
CONNECTION
.
Bl
Vee
14
AZ
CZ
BZ
Cl
VI
VZ
GND
10
11
13
Al
Dl
DZ
Order Number DM74S51N
See NS Package Number N14A
Function Table
Y=AB+CD
Output
Inputs
A
B
C
0
Y
H
X
H
X
X
H
X
H
L
L
All other
combinations
H
L
= High Logic Level
= Low Logic Level
X = Either Low or High Logic Level
3·29
H
TUF/6454-1
Absolute Maximum Ratings (Note)
7V
Supply Voltage
Input Voltage
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaran·
teed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
5.5V
Operating Free Air Temperature Range
DM74S
O'Cto +70'C
-65'Cto + 150'C
Storage Temperature Range
Recommended Operating Conditions
Symbol
DM74S51
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
Units
Min
Nom
Max
4.75
5
5.25
V
2
V
Vil
Low Level Input Voltage
0.8
V
10H
High Level Output Current
-1
mA
20
rnA
70
·c
10l
Low Level Output Current
TA
Free Air Operating Temperature
0
Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
Conditions
=
=
Typ
(Note 1)
Min
Max
Units
-1.2
V
VI
Input Clamp Voltage
Vee
VOH
High Level Output
Voltage
Vee = Min,IOH
Vil = Max
=
Max
VOL
Low Level Output
Voltage
Vee = Min, 10l
VIH = Min
=
Max
II
Input Current @ Max
Input Voltage
Vee
=
Max, VI
=
5.5V
IIH
High Level Input Current
Vee
=
Max, VI
50
p.A
III
Vee = Max, VI
=
=
2.7V
Low Level Input Current
0.5V
-2
mA
los
Short Circuit
Output Current
Vee
=
Max (Note 2)
-100
mA
ICCH
Supply Current with
Outputs High
Vee
=
Max
8.2
17.8
mA
ICCl
Supply Current with
Outputs Low
Vee
=
Max
14
22
mA
Min, II
Switching Characteristics at Vee =
-18 mA
I
DM74
5V and TA
Parameter
CL
3.4
V
-40
=
=
0.5
V
1
mA
25"C (See Section 1 for Test Waveforms and Output Load)
RL
Symbol
2.7
=
2800
Units
CL=50pF
15pF
Min
Max
Min
Max
tplH
Propagation Delay Time
Low to High Level Output
2
5.5
3
8
ns
tpHl
Propagation Delay Time
High to Low Level Output
2
5.5
3
8
ns
Note 1: All typlcals are al Vee = 5V. TA = 25'C.
Note 2: Not more than one output should be shorted al a time, and the duration should not exceed one second.
3·30
~National
~ Semiconductor
DM54S64/DM74S64 4-Wide AND-OR-INVERT Gates
General Description
This device contains a combination of gates which performs
the logic AND-DR-INVERT function.
Connection Diagram
Dual-In-Line Package
v
D
vc:c:
13
14
12
GND
H
A
Order Number DM54S64J, DM54S64W or DM74S64N
See NS Package Number J14A, N14A or W14B
Function Table
Y = ABCD
+ EF + GHI + JK
Inputs
Output
C
D
E
F
G
H
I
J
K
Y
H H H
X X X
X X X
X X X
H
X
X
X
X
H
X
X
X
H
X
X
X
X
H
X
X X
X X
H H
X X
X
X
X
H
X
X
X
H
L
L
L
L
A
B
All other combinations
H = High logic level
l = low logic level
X = Either low or High logic level
3-31
H
TUF/6455-1
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
DM54S
-55'C to + 125'C
DM74S
O'Cto +70'C
Storage Temperature Range
- 65'C to + 150'C
Recommended Operating Conditions
Symbol
Vee
Supply Voltage
VIH
High Level Input Voltage
DM74S64
DM54S64
Parameter
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
2
V
V
Vil
Low Level Input Voltage
0.8
0.8
V
10H
High Level Output Current
-1
-1
mA
20
mA
70
'C
10l
Low Level Output Current
TA
Free Air Operating Temperature
20
-55
125
0
Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
Min
Typ
(Note 1)
OM 54
2.5
3.4
DM74
2.7
3.4
Conditions
=
=
Max
Units
-1.2
V
VI
Input Clamp Voltage
Vcc
VOH
High Level Output
Voltage
Vcc = Min, 10H
Vil = Max
=
VOL
Low Level Output
Voltage
Vcc = Min, 10l
VIH = Min
=
Max
II
Input Current @ Max
Input Voltage
Vcc
=
Max, VI
=
5.5V
=
=
Max, VI
=
=
2.7V
50
/LA
0.5V
-2
mA
Min, II
IIH
High Level Input Current
Vcc
III
Low Level Input Current
Vcc
los
Short Circuit
Output Current
Vcc = Max
(Note 2)
ICCH
Supply Current with
Outputs High
Vcc
=
Max
ICCl
Supply Current with
Outputs Low
Vee
=
Max
Max, VI
-18 mA
MaX
I
I
I
I
V
0.5
V
1
mA
OM 54
-40
-100
DM74
-40
-100
mA
7
12.5
mA
8.5
16
mA
Switching Characteristics at Vcc = 5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
Rl
Symbol
Parameter
Cl
=
=
280n
15pF
Cl
=
Units
50pF
Min
Max
Min
Max
tpLH
Propagation Delay Time
Low to High Level Output
2
5.5
3
8
ns
tpHL
Propagation Delay Time
High to Low Level Output
2
5.5
3
8
ns
Note 1: All typical. are at Vee = 5V. TA = 25'C.
Note 2: Not more than one output should be shorted at a time. and the duration should not exceed one second.
3-32
~National
~ Semiconductor
DM54S7 4/DM7 4S7 4
Dual Positive-Edge-Triggered D Flip-Flops
with Preset, Clear, and Complementary Outputs
General Description
This device contains two independent positive-edge-triggered D flip-flops with complementary outputs. The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse. The triggering occurs at a
voltage level and is not directly related to the transition time
of the rising edge of the clock. The data on the D input may
be changed while the clock is low or high without affecting
the outputs as long as setup and hold times are not violated.
A low logic level on the preset or clear inputs will set or
reset the outputs regardless of the logic levels of the other
inputs.
Connection Diagram
Dual-In-line Package
ClR Z
vee
[14
ClK Z
OZ
113
11z
I
I
I"L--
PR Z
-
....
ClR 1
~
y
r-
I
C~: pJ: K
1:
1
0
8
9
I
1
19
~~
6
I>
iIz
OZ
1,0
6
ill
G!:
TLlF/6457-1
Order Number DM54S74J, DM54S74W, DM74S74M or DM74S74N
See NS Package Number J14A, M14A, N14A or W14B
Function Table
Inputs
Outputs
Q
PR
ClR
ClK
D
Q
l
H
H
X
X
X
X
X
X
H
L
L
H
H·
i
i
H
L
L
L
H
H
H
H
H
H
L
X
H*
H
L
L
H
L
00
00
= High Logic Level
X = Eilher Low or High Logic Level
L = Low Logic Level
f = Posilive-going Transilion
• = This configuration is nonstable; that is. it will not persist when either the
H
preset andlor clear inputs return to its inactive (high) level.
00
= The output logic level of 0
before the indicated input conditions were established.
3-33
II
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the ssfety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Offlce/Dlatrlbutors for svallablllty and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
- 55·C to + 125·C
DM54S
DM74S
O·Cto +70·C
Storage Temperature Range
-65·C to + 150"C
Recommended Operating Conditions (See Section 1 for Test Waveforms and Output Load)
Symbol
DM54S74
Parameter
DM74S74
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
VCC
Supply Voltage
VrH
High Level Input Voltage
VrL
Low Level Input Voltage
O.B
O.B
V
IOH
High Level Output Current
-1
-1
mA
IOL
Low Level Output Current
20
20
mA
fCLK
Clock Frequency (Note 2)
0
110
fCLK
Clock Frequency (Note 3)
0
95
tw
Pulse Width
(Note 2)
Clock High
6
6
Clock Low
7.3
7.3
Clear Low
7
7
Preset Low
7
7
Clock High
B
B
Clock Low
9
9
Clear Low
9
9
tw
Pulse Width
(Note 3)
2
2
Preset Low
V
V
75
0
110
75
MHz
65
0
95
65
MHz
ns
ns
9
9
tsu
Setup Time (Notes 1 & 2)
3t
3t
ns
tsu
Setup Time (Notes 1 & 3)
3t
3t
ns
tH
Input Hold Time (Notes 1 & 2)
2t
2t
ns
tH
Input Hold Time (Notes 1 & 3)
2t
TA
Free Air Operating Temperature
-55
Nata 1: The symbol (t) Indicates the riSing edge at the clocl< pulse is used for reference.
Nota 2: CL
Nata 3: CL
= 1S pF, RL = 2800, TA = 2S'C and Vee
= SO pF, RL = 2800, TA = 25'C and Vee
ns
2t
125
= SV.
= SV.
3-34
0
70
'c
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
VI
Input Clamp Voltage
Vee = Min,ll = - 18 rnA
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
VIL = Max, VIH = Min
VOL
Low Level Output
Voltage
Vee = Min, 10L = Max
VIH = Min, VIL = Max
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 5.5V
IIH
High Level Input
Current
Vee = Max
VI = 2.7V
IlL
Min
Typ
(Note 1)
DM54
2.5
3.4
DM74
2.7
3.4
Conditions
Low Level Input
Current
Vee = Max
VI = 0.5V
(Note 4)
Max
Units
-1.2
V
V
lOS
Vee = Max
(Note 2)
V
1
rnA
D
50
Clear
150
Preset
100
Clock
100
D
-2
Clear
-6
Preset
-4
DM54
-40
-100
DM74
-40
-100
30
50
Supply Current
Vee = Max, (Note 3)
lee
Note 1: All typicals are at Vee - 5V, TA - 25"C.
Note 2: Not more than one output should be shorted at a time. and the duration should not exceed one second.
Note 3: With all outputs open. Icc is measured with the Q and Q outputs high in turn. At the time of measurement, the clock is grounded.
Note 4: Clear is tested with preset high and preset is tested with clear high.
Switching Characteristics at Vee =
Symbol
Parameter
,..A
mA
-4
Clock
Short Circuit
Output Current
0.5
rnA
mA
5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
From (Input)
To (Output)
RL = 2800.
CL = 15pF
Min
CL = 50pF
Max
Min
Units
Max
fMAX
Maximum Clock
Frequency
tp'.H
Propagation Delay Time
Low to High Level Output
Preset
toO
6
9
ns
tpLH
Propagation Delay Time
Low to High Level Output
Clear
toO
6
9
ns
tpHL
Propagation Delay Time
High to Low Level Output
(Clock High)
Preset
toO
13.5
17
ns
Propagation Delay Time
High to Low Level Output
(Clock Low)
Preset
toO
8
14
ns
Propagation Delay Time
High to Low Level Output
(Clock High)
Clear
to
a
13.5
16
ns
Propagation Delay Time
High to Low Level Output
(Clock Low)
Clear
to
a
8
13
ns
tpLH
Propagation Delay Time
Low to High Level Output
Clock to
aorO
9
12
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clock to
aorO
9
14
ns
tpHL
tpHL
tpHL
75
3-35
65
MHz
•
I
~National
~ Semiconductor
DM54S86/DM74S86 Quad 2-lnput Exclusive-OR Gates
General Description
This device contains four independent gates each of which
performs the logic Exclusive-OR function.
Connection Diagram
Dual-In-Llne Package
A1
81
Y1
A2
82
Y2
GND
TL/F/645B-1
Order Number DM54SB6J, DM54SB6W or DM74SB6N
See NS Package Number J14A, N14A or W14B
Function Table
Y=AeB=AB+AB
Inputs
Output
A
B
L
L
L
L
H
H
H
L
H
H
H
L
H ~ High Logic Level
L ~ Low Logic Level
3-36
Y
(J)
Absolute Maximum Ratings
CD
en
(Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
- 55·C to + 125·C
DM54S
O·Cto +70·C
DM74S
Storage Temperature Range
-65·C to + 150·C
Recommended Operating Conditions
Symbol
Vcc
Supply Voltage
VIH
High Level Input Voltage
DM74S86
DM54S86
Parameter
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
2
V
V
VIL
Low Level Input Voltage
0.8
0.8
V
10H
High Level Output Current
-1
-1
mA
20
mA
70
·C
10L
Low Level Output Current
TA
Free Air Operating Temperature
20
-55
125
0
Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
Min
Typ
(Note 1)
DM54
2.5
3.4
DM74
2.7
3.4
Conditions
Max
Units
-1.2
V
VI
Input Clamp Voltage
Vcc = Min, II = -18 mA
VOH
High Level Output
Voltage
Vcc = Min, 10H = Max
VIL = Max, VIH = Min
VOL
Low Level Output
Voltage
Vcc = Min, 10L = Max
VIH = Min, VIL = Max
II
Input Current @ Max
Input Voltage
Vcc = Max, VI = 5.5V
IIH
High Level Input Current
Vcc = Max, VI = 2.7V
50
p.A
IlL
Low Level Input Current
Vcc = Max, VI = 0.5V
-2
mA
los
Short Circuit
Output Current
Vcc = Max
(Note 2)
ICCH
Supply Current with
Outputs High
Vcc = Max
(Note 3)
35
50
mA
ICCL
Supply Current with
Outputs Low
Vcc = Max
(Note 4)
50
75
mA
I
I
L
I
V
0.5
V
1
mA
DM54
-40
-100
DM74
-40
-100
mA
Note 1: All typicals are at Vee = SV, TA = 2S'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: ICCH is measured with all outputs open, one input of each gale at 4.SV, and the other inputs grounded.
Note 4: lecl is measured with all outputs open and all inputs grounded.
Switching Characteristics at Vcc =
Symbol
Parameter
5V and TA = 25·C (See Section 1 for Test Waveforms and Output Load)
From (Input)
to (Output)
RL = 2800
CL = 15pF
Min
tpLH
tpHL
Propagation Delay Time
Low to High Level Output
Propagation Delay Time
High to Low Level Output
AorB
toY
3·37
Max
CL = 50pF
Min
Units
Max
10.5
14
ns
10
13
ns
!..-
en ~National
~ Semiconductor
DM74S109 Dual JK Positive
Edge-Triggered Flip-Flop
General Description
This device consists of two high speed, completely independent transition clocked JK flip-flops. The clocking operation
is independent of rise and fall times of the clock waveform.
The JK design allows operation as a D flip-flop (refer to 'S74
data sheet) by connecting the J and K inputs together.
Connection Diagram
Dual-In-Llne Package
1
\....../
16
COl 2
-¥-..- ~~cc
Jl-- - Jfol
CD 0- ~C02
Kl.2.. -C Kl
J - ,!LJ2
CPl.....!. -
K o-rlLi<2
CPl
501 -2. -C SOl
Ql...!.. ~ Ql
01.2..
GND...!.
CP So
r-c Ql
r!LCP2
o-rll-502
Q Q ~ ~Q2
'--
'""""
9 02
TL/F/9802-1
Order Number DM74S109N
See NS Package Number N16E
Truth Table
Inputs
Asynchronous Inputs:
Outputs
LOW input to So sets Q to HIGH level
@tn + 1
J
K
L
H
L
H
L
H
H
L
Q
LOW input to CD sets Q to LOW level
Q
Clear and Set are independent of clock
Simultaneous LOW on CD and
No Change
L
H
H
L
makes both Q and
Q HIGH
Toggles
In = Bit time before clock pulse
tn + 1 = Bit time after clock pulse
H = HIGH Voltage Level
L
= LOW VoHage Level
Logic Symbol
11
J,
SOl
2 - Jl
6
Qll--
14
-
7
Ql ~
12
CP
13
~ K
4 - CPl
3 - ( Kl
Q 1--10
J
Q P-9
CD
COl
TLiF/9802-2
= Pin1S
GNO = PinS
vee
3-38
So
....en
Absolute Maximum Ratings (Note)
Q
CD
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
DM74S
Storage Temperature Range
O·Cto +70·C
- 65·C to + 150·C
Recommended Operating Conditions
Symbol
DM74S109
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
Units
Min
Nom
Max
4.75
5
5.25
V
2
V
VIL
Low Level Input Voltage
0.8
V
10H
High Level Output Current
-1
mA
20
mA
70
·C
10L
Low Level Output Current
TA
Free Air Operating Temperature
ts(H)
Setup Time
Is (L)
I n or Kn to CPn
th(H)
th (L)
I n or Kn to CPn
0
Hold Time
6.0
6.0
ns
0
0
ns
tw(H)
tw(L)
CPn Pulse Width
7.0
6.5
ns
tw(L)
COn or SOn Pulse Width LOW
6.0
ns
Electrical Characteristics
Over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
VI
Input Clamp Voltage
Vee = Min, II = -18 mA
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
VIL = Max
VOL
Low Level Output
Voltage
Vee = Min, 10L = Max
VIH = Min
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 5.5V
IIH
High Level Input Current
IlL
Low Level Input Current
los
Short Circuit
Output Current
Vee = Max
(Note 2)
ICC
Supply Current
Vee = Max
Vep = OV
Min
2.7
Typ
(Note 1)
Max
Units
-1.2
V
3.4
0.35
V
0.5
V
1
mA
Vee = Max, VI = 2.7V
50
/LA
Vee = Max, VI = 0.5V
-2.0
mA
-100
mA
52
mA
-40
Nota 1: All typlcals are at Vee = SV, TA = 2S'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
3-39
Switching Characteristics
Vee =
+ 5.0V, TA = + 25°C (See Section 1 for waveforms and load configurations)
Symbol
CL = 15pF
RL = 2800
Parameter
Max
Min
Maximum Clock Frequency
Unlta
MHz
75
Propagation Delay
CPn to an or an
9.0
11
Propagation Delay
6.0
COn or SOn to an or an
5V. TA = 25'C.
11
ns
ns
Note 1: Alllyplcals are at vee Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Logic Diagram (one half shown)
~~""'-Q
Co--.....-=......
CP -~-I-H
...----'
TL/F/9B02-3
3·40
r---------------------------------------------------------------------~
~National
0
....
....N
~ Semiconductor
DM54S 112/DM7 4S 112 Dual Negative-Edge-Triggered
Master-Slave J-K Flip-Flops with Preset,
Clear, and Complementary Outputs
General Description
This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and
K data is processed by the flip-flops on the falling edge of
the clock pulse. The clock triggering occurs at a voltage
level and is not directly related to the transition time of the
negative going edge of the clock pulse. Data on the J and K
inputs can be changed while the clock is high or low without
affecting the outputs as long as setup and hold times are
not violated. A low logic level on the preset or clear inputs
will set or reset the outputs regardless of the logic levels of
the other inputs.
Connection Diagram
Dual-In-line Package
vee
elR 1
elR Z
elK Z
elKI
Kl
Jl
PRI
KZ
01
JZ
PR Z
OZ
iii
iiz
GNO
TL/F/6459-1
Order Number DM54S112J or DM74S112N
See NS Package Number J16A or N16E
Function Table
Inputs
Outputs
PR
ClR
ClK
J
K
Q
L
H
L
L
X
X
X
L
L
L
X
X
X
H
H
X
X
X
H·
H
H·
H
H
H
H
H
H
H
H
H
H
-J,
-J,
-J,
-J,
L
L
L
00
00
H
L
L
H
H
H
H
X
X
H
L
H
Q
Toggle
00
00
H = High Logic Level
X = Either Low or High Logic Level
L = Low Logic Level
J. = Negative going edge of pulse.
00 = The output logic level of 0 before the Indicated input conditions were
established •
• = This configuration is nonstable; that is, it will not persist when either the
preset andlor clear inputs return to its inactive (high) level.
Toggle = Each output changes to the complement of its previous level on
each 'ailing edge of the clock pulse.
3-41
•
N
....
....
fI)
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaran·
teed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Input Voltage
5.5V
Operating Free Air Temperature Range
DM54S
-55·Cto + 125·C
DM74S
O"Cto +70·C
Storage Temperature Range
-65·Cto + 150"C
Recommended Operating Conditions (See Section 1 for Test Waveforms and Output Load)
Symbol
DM54S112
Parameter
DM74S112
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
VCC
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
0.8
0.8
V
IOH
High Level Output Current
-1
-1
mA
IOL
Low Level Output Current
20
20
mA
fCLK
Clock Frequency (Note 2)
0
125
80
0
125
80
MHz
fCLK
Clock Frequency (Note 3)
0
80
60
0
80
60
MHz
lw
Pulse Width
(Note 2)
Clock High
6
6
Clock Low
6.5
6.5
Clear Low
8
8
tw
Pulse Width
(Note 3)
2
2
Preset Low
8
8
Clock High
8
8
Clock Low
8
8
Clear Low
10
10
Preset Low
V
V
ns
ns
10
10
tsu
Setup Time (Notes 1 & 4)
7J.
7J.
IH
Input Hold Time (Notes 1 & 4)
OJ.
OJ.
ns
0
·C
-55
Free Air Operating Temperature
TA
Note 1: The symbol (,J.) Indicates the falling edge at the clock pulse Is used for reference.
Note 2: Cl = IS pF, Rl = 2800, TA = 2S'C and Vee = SV.
Note 3: Cl = SO pF, Rl = 2800, TA = 2S'C and Vee = SV.
Note 4: TA = 25'C and Vee = sv.
3·42
125
ns
70
....
....
N
fJ)
Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
Conditions
VI
Input Clamp Voltage
Vee = Min, 11= -18mA
VOH
High level Output
Voltage
Vee = Min, 10H = Max
VIL = Max, VIH = Min
VOL
low level Output
Voltage
Vee = Min, IOL = Max
VIH = Min, VIL = Max
II
Input Current @ Max
Input Voltage
Vee
IIH
High level Input
Current
Vee = Max
VI = 2.7V
IlL
Low level Input
Current
Min
Typ
(Note 1)
DM54
2.5
3.4
DM74
2.7
3.4
Max
Units
-1.2
V
V
= Max, VI = 5.5V
Vee = Max
VI = 0.5V
(Note 4)
Short Circuit
Output Current
Vee = Max
(Note 2)
V
1
mA
J, K
50
Clear
100
Preset
100
Clock
100
J,K
-1.6
Clear
-7
Preset
-7
p,A
mA
-4
Clock
los
0.5
DM54
-40
-100
DM74
-40
-100
Supply Current
50
Vee = Max (Note 3)
30
lee
Nole 1: All typicals are at VCC = 5V, TA = 25'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Nole 3: With all outputs open, Icc is measured with the a and Ci outputs high in turn. At the time of measurement, the clock Input Is grounded.
Nole 4: Clear Is tested with preset high and preset is tested with clear high.
mA
mA
Switching Characteristics at Vee = 5V and TA = 25'C (See Section 1 for Test Waveforms and Output load)
Symbol
Parameter
From (Input)
To (Output)
RL
CL
Min
= 15pF
= 2800
CL
Max
Min
= 50pF
Units
Max
fMAX
Maximum Clock
Frequency
tpLH
Propagation Delay Time
Low to High Level Output
Preset
toO
7
9
ns
tpHL
Propagation Delay Time
High to Low Level Output
Preset
toa
7
12
ns
tpLH
Propagation Delay Time
Low to High Level Output
Clear
toa
7
9
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clear
toO
7
12
ns
tpLH
Propagation Delay Time
Low to High Level Output
Clock to
Oora
7
9
ns
tpHL
Propagation Delay Time
High to low level Output
Clock to
Oora
7
12
ns
80
3-43
60
MHz
•
I
,...
,...
~
II)
,----------------------------------------------------------------------------,
~National
~ SemiconfJuctor
DM54S 113/DM7 4S 113 Dual Negative-Edge-Triggered
Master-Slave J-K Flip-Flops with Preset
and Complementary Outputs
General Description
negative going edge of the clock pulse. Data on the J and K
inputs may be changed while the clock is high or low without
affecting the outputs as long as setup and hold times are
not violated. A low logic level on the preset input will set the
outputs regardless of the logic levels of the other inputs.
This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and
K data is processed by the flip-flops on the falling edge of
the clock pulse. The clock triggering occurs at a voltage
level and is not directly related to the transition time of the
Connection Diagram
Dual-In-line Package
vicc
CLK2
14
K2
J2
ii2
Q2
PTR 2
10
11
12
13
6
iiI
KI
CLK I
TLlF/6460-1
Order Number DM54S113J or DM74S113N
See NS Package Number J14A or N14A
Function Table
Outputs
Inputs
PR
l
H
H
H
H
H
elK
J
K
X
X
X
H
l
J.
l
l
H
H
00
00
H
L
l
H
J.
l
H
L
H
H
X
X
00
J,
J,
Q
Q
Toggle
00
H = High Logic Level
X = Either Low or High Logic Level
L = Low Logic Level
.j. = Negative going edge of pulse.
00 = The output logic level of Q before the Indicated Input condiUons were established.
Toggle = Each output changes to the complement of its previOUS level on each falling edge of the clock pulse.
3-44
......
tn
Absolute Maximum Ratings (Note)
Co)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Input Voltage
5.5V
Operating Free Air Temperature Range
DM54S
-55·C to + 125·C
DM74S
O·Cto +70·C
Storage Temperature Range
-65·Cto + 150·C
Recommended Operating Conditions (See Section 1 for Test Waveforms and Output Load)
Symbol
DM54S113
Parameter
VCC
Supply Voltage
VIH
High Level Input Voltage
DM74S113
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
2
V
V
Vil
Low Level Input Voltage
0.8
0.8
V
IOH
High Level Output Current
-1
-1
mA
IOl
Low Level Output Current
20
mA
fClK
Clock Frequency (Note 2)
0
125
80
0
125
80
MHz
fClK
Clock Frequency (Note 3)
0
80
60
0
80
60
MHz
tw
Pulse Width
(Note 2)
Clock High
6
6
Clock Low
6.5
6.5
Preset Low
8
8
Pulse Width
(Note 3)
Clock High
8
8
tw
20
Clock Low
8
8
Preset Low
10
10
tsu
Setup Time (Notes 1 & 4)
7J,
7J,
tH
Input Hold Time (Notes 1 & 4)
oJ,
oJ,
TA
Free Air Operating Temperature
-55
125
Note 1: The symbol ( !) indicates the falling edge at the clock pulse is used for reference.
Note 2: CL
Note 3: CL
Note 4: TA
= IS pF, RL = 28011, TA = 2S'C and Vee = SV.
= SO pF, RL = 28011, TA = 2S'C and Vee = SV.
= 2S'C and Vee = SV.
3-45
0
ns
ns
ns
ns
70
·C
....
....
en
CI)
Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
VI
Input Clamp Voltage
VOH
High Level Output
Voltage
= Min,ll = - 18 mA
Vee = Min, 10H = Max
VIL = Max, VIH = Min
VOL
Low Level Output
Voltage
Vee = Min, 10L = Max
VIH = Min, VIL = Max
II
Input Current @ Max
Input Voltage
Vee
IIH
High Level Input
Current
Vee = Max
VI = 2.7V
IlL
los
Low Level Input
Current
Short Circuit
Output Current
Min
Typ
(Note 1)
DM54
2.5
3.4
DM74
2.7
3.4
Conditions
Vee
= Max, VI = 5.5V
Vee = Max
VI = 0.5V
Vee = Max
(Note 2)
Max
Units
-1.2
V
V
0.5
V
1
mA
J,K
50
Preset
100
Clock
100
J,K
-1.6
Preset
-7
Clock
-4
DM54
-40
-100
DM74
-40
-100
Supply Current
Vee = Max, (Note 3)
30
50
typicals are at Vcc, = 5V, TA = 25'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: With all outputs open, Icc, Is measured with the Q and a outputs high in tum. At the time of measurement, the clock input Is grounded.
lee
/LA
rnA
mA
rnA
Note 1: All
Switching Characteristics at Vee = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
RL = 2800
From (Input)
Parameter
Units
Symbol
CL
=
15pF
CL = 50pF
To (Output)
Min
Max
Min
Max
fMAX
Maximum Clock
Frequency
tpLH
Propagation Delay Time
Low to High Level Output
Preset
toO
7
9
ns
tpHL
Propagation Delay Time
High to Low Level Output
Preset
toO
7
12
ns
tpLH
Propagation Delay Time
Low to High Level Output
Clock to
OorO
7
9
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clock to
OorO
7
12
ns
80
3-46
60
MHz
~National
~ Semiconductor
DM74S132
Quad 2-lnput Schmitt Trigger NAND Gate
General Description
This device contains four independent gates that perform
the logic NAND function. Each gate has two inputs that are
Schmitt Triggers.
Connection Diagram
Dual-In-Llne Package
14 Vee
GND
Tl/F/9803-1
Order Number DM74S132N
See NS Package Number N14A
3-47
Absolute Maximum Ratings
(Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for acutal device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications_
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
DM74S
Storage Temperature Range
O·Cto +70·C
- 65·C to + 150·C
Recommended Operating Conditions
Symbol
DM74S132
Parameter
Units
Min
Nom
Max
4.75
5
5.25
Vcc
Supply Voltage
VIH
High Level Input Voltage
V
VIL
Low Level Input Voltage
0.8
V
10H
High Level Output Current
-1
mA
V
2
20
mA
0
70
·C
VT+
Positive-Going
Threshold Voltage
1.6
1.9
V
VT-
Negative-Going
Threshold Voltage
1.1
1.4
V
VT+-VT-
Hysteresis Voltage
0.2
V
IT+
Input Current at PositiveGoing Threshold
-0.9""
mA
-1.1"
mA
10L
Low Level Output Current
TA
Free Air Operating Temperature
Input Current at NegativeGoing Threshold
'DC limits apply over operating temperature range; AC limits apply at TA
IT-
=
+2S'C and Vee
=
+S.OV.
'" "'Typical Value.
Electrical Characteristics Over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 1)
Max
Units
-1.2
V
VI
Input Clamp Voltage
Vcc = Min,ll = -18 mA
VOH
High Level Output
Voltage
Vcc = Min, 10H = Max
VIL = Max
VOL
Low Level Output
Voltage
Vcc = Min, 10L = Max
VIH = Min
II
Input Current @ Max
Input Voltage
Vcc = Max, VI = 5.5V
IIH
High Level Input Current
Vee = Max, VI = 2.7V
50
p.A
IlL
Low Level Input Current
Vee = Max, VI = 0.5V
-2.0
mA
loS
Short Circuit
Output Current
Vcc = Max
(Note 2)
-100
mA
ICCH
Supply Current with
Outputs High
Vcc = Max
44
mA
68
mA
Supply Current with
Outputs Low
Nole 1: All Iypicals are at Vee = SV. TA = 2S·C.
ICCL
2.7
0.35
-40
Vcc = Max
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
3-48
V
3.4
0.5
V
1
mA
Switching Characteristics Vee = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
RL = 2800
Symbol
Parameter
Units
CL = 15pF
Min
Max
tpLH
Propagation Delay Time
Low to High Level Output
10.5
ns
tpHL
Propagation Delay Time
High to Low Level Output
13
ns
•
3·49
~ .---------------------------------------------------------------------~
~
Ui ~ National
~ Semiconductor
DM54S133/DM74S133 13-lnput NAND Gate
General Description
This device contains a single gate which performs the logic
NAND function.
Connection Diagram
Dual-In-Llne Package
VIC
116
K
M
15
14
H
13
12
11
V
\10
.1
)0-
~p
A
c
o
G
J:
Order Number DM54S133J, DM74S133M or DM74S133N
See NS Package Number J16A, M16A or N16E
Function Table
Y = ABCDEFGHIJKLM
Inputs
Output
AthruM
Y
All InputsH
One or More
Inputl
l
H
H = High logic Level
L = Low Logic Level
3·50
TL/F/6462-1
Absolute Maximum Ratings
(Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the condItions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
- 55·C to + 125·C
DM54S
O·Cto +70·C
DM74S
-65·Cto + 150·C
Storage Temperature Range
Recommended Operating Conditions
Symbol
DM54S133
Parameter
DM74S133
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
0.8
0.8
V
10H
High Level Output Current
-1
-1
mA
10L
Low Level Output Current
20
20
mA
TA
Free Air Operating Temperature
70
·c
2
2
-55
125
V
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Min
Typ
(Note 1)
DM54
2.5
3.4
DM74
2.7
3.4
Conditions
VI
Input Clamp Voltage
Vee = Min, 11= -18 mA
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
VIL = Max
VOL
Low Level Output
Voltage
Vee = Min, 10L = Max
VIH = Min
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 5.5V
I
I
Max
Units
-1.2
V
V
0.5
V
1
mA
IIH
High Level Input Current
Vee = Max, VI = 2.7V
50
p.A
IlL
Low Level Input Current
Vee = Max, VI = 0.5V
-2
mA
los
Short Circuit
Output Current
Vee = Max
(Note 2)
leeH
Supply Current with
Outputs High
Vee = Max
ICCL
Supply Current with
Outputs Low
Vee = Max
Switching Characteristics at Vee =
I
I
DM54
-40
-100
DM74
-40
-100
mA
3
5
mA
5.5
10
mA
5V and TA = 25·C (See Section 1 for Test Waveforms and Output Load)
RL = 2800
Parameter
Symbol
CL = 15pF
CL = 50pF
Units
Min
Max
Min
Max
tpLH
Propagation Delay Time
Low to High Level Output
2
6
2
8
ns
tpHL
Propagation Delay Time
High to Low Level Output
2
7
3
10
ns
Note 1: All typical. are at Vee
= 5V. TA = 25'C.
Note 2: Not mora than one output should be shorted at a time, and the duration should not exceed one second.
3-51
•
CD
....
•
CO
.... ~ Semiconductor
en
CO)
en ~National
CO)
DM54S138/DM74S138, DM54S139/DM74S139
Decoders/Demultiplexers
General Description
Features
These Schottky-clamped circuits are designed to be used in
high-performance memory-decoding or data-routing applications, requiring very short propagation delay times. In
high-performance memory systems these decoders can be
used to minimize the effects of system decoding. When
used with high-speed memories, the delay times of these
decoders are usually less than the typical access time of the
memory. This means that the effective system delay introduced by the decoder is negligible.
• Designed specifically for high speed:
Memory decoders
Data transmission systems
• S138 3-to-8-line decoders incorporates 3 enable inputs
to simplify cascading and/or data reception
• S139 contains two fully independent 2-to-4-line decoders/demultiplexers
• Schottky clamped for high performance
• Typical propagation delay time (3 levels of logic)
S138 8 ns
S139 7.5 ns
• Typical power dissipation
S138 245 mW
S139 300 mW
The S138 decodes one-of-eight lines, based upon the conditions at the three binary select inputs and the three enable
inputs. Two active-low and one active-high enable inputs
reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented with no external inverters, and a 32-line decoder requires only one
inverter. An enable input can be used as a data input for
demultiplexing applications.
The S139 comprises two separate two-line-to-four-line decoders in a single package. The active-low enable input can
be used as a data line in demultiplexing applications.
All of these decoders/demultiplexers feature fully buffered
inputs, presenting only one normalized load to its driving
circuit. All inputs are clamped with high-performance
Schottky diodes to suppress line-ringing and simplify system
design.
Connection Diagrams
Dual-In-Llne Package
Dual-In-Llne Package
DATA OUTPUTS
/
vcc
116
YO
Yl
15
Y2
14
13
Y3
Y4
12
ENABLE
G2
vcc
,
11
Y5
V6
10
116
9
115
1
.
SELECT
.
A2
DATA OUTPUTS
\
B2
114
J
,
/
2VO
2Yl
2Y2
.. 110
113
112
\11
I
A
-.! 1
2V3
9
~
Ie>
~
rO
I
1
A
2
B
\
SELECT
3
C,
4
G2A
,
5
G2B
6
Gl
7
Y7
, OUTPUT
1
I
12
13
Bl
ENABLE AI
,
,
Gl
SELECT
18
GND
\
ENABLE
'(
.r
14
lYO
\5
IVI
,
.
~
.r
I!:
I!:
,
G!:
OATA OUTPUTS
TL/F/6466-1
TL/F/6466-2
Order Number DM54S13BJ, DM54S139J, DM54S13BW, DM54139W, DM74S138N or DM74S139N
See NS Package Number J16A, N16E or W16A
3-52
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and speclflcatlons_
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
DM54S
-55' C to + 125'C
DM74S
O'Cto +70'C
Storage Temperature Range
-65' C to + 150' C
Recommended Operating Conditions
Symbol
DM54S138,S139
Parameter
DM74S138,S139
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
0.8
0.8
-1
mA
20
mA
70
'C
2
2
10H
High Level Output Current
-1
10L
Low Level Output Current
20
TA
Free Air Operating Temperature
Electrical Characteristics
Symbol
-55
125
V
0
V
over recommended operating free air temperature (unless otherwise noted)
Parameter
Min
Typ
(Note 1)
DM54
2.5
3.4
DM74
2.7
3.4
Conditions
VI
Input Clamp Voltage
Vee = Min, II = -18 rnA
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
VIL = Max, VIH = Min
VOL
Low Level Output
Voltage
Vee = Min, 10L = Max
VIH = Min, VIL = Max
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 5.5V
I
I
Max
Units
-1.2
V
V
0.5
V
1
mA
IIH
High Level Input Current
Vee = Max, VI = 2.7V
50
p.A
IlL
Low Level Input Current
Vee = Max, VI = 0.5V
-2
mA
los
Short Circuit
Output Current
Vee = Max
(Note 2)
Supply Current (5138)
Vee = Max (Note 3)
49
74
rnA
Supply Current (5139)
Vee = Max (Note 3)
60
90
mA
Icc
Icc
Note 1:
All
I
I
DM54
-40
-100
DM74
-40
-100
typicals are at Vee = 5V. TA = 25'C.
Note 2: Not more than one oulput should be shorted at a time. and the duration should nol exceed one second.
Note 3: Icc is measured with
all outputs enabled and open.
3-53
mA
'S 138 Switching Characteristics
at Vee = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output load)
Parameter
From
(Input)
to
(Output)
tpLH
Propagation Delay Time
low to High level Output
Select to
Output
2
7
9
ns
tpHL
Propagation Delay Time
High to low level Output
Select to
Output
2
10.5
14
ns
tpLH
Propagation Delay Time
low to High level Output
Select to
Output
3
12
14
ns
tpHL
Propagation Delay Time
High to low level Output
Select to
Output
3
12
15
ns
tpLH
Propagation Delay Time
low to High level Output
Enable to
Output
2
8
10
ns
tpHL
Propagation Delay Time
High to low level Output
Enable to
Output
2
11
14
ns
tpLH
Propagation Delay Time
low to High level Output
Enable to
Output
3
11
13
ns
tpHL
Propagation Delay Time
High to low level Output
Enable to
Output
3
11
14
ns
Symbol
RL = 2800
Levels
of Delay
CL = 15pF
Min
Max
CL = 50pF
Min
Units
Max
'S139 Switching Characteristics
at Vee = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output load)
Symbol
Parameter
From
(Input)
to
(Output)
RL = 2800
Levels
of Delay
CL = 15pF
Min
Max
CL = 50pF
Min
Units
Max
tpLH
Propagation Delay Time
low to High level Output
Select to
Output
2
7.5
10
ns
tpHL
Propagation Delay Time
High to low level Output
Select to
Output
2
10
13
ns
tpLH
Propagation Delay Time
low to High level Output
Select to
Output
3
12
13
ns
tpHL
Propagation Delay Time
High to low level Output
Select to
Output
3
12
15
ns
tpLH
Propagation Delay Time
low to High level Output
Enable to
Output
2
8
10
ns
tpHL
Propagation Delay Time
High to low level Output
Enable to
Output
2
10
13
ns
3-54
...
en
...•
en
Function Tables
Co)
CD
S138
S139
Inputs
Enable
Inputs
Outputs
Select
Enable
G1 G2* C B A YO Y1 Y2 Y3 Y4 Y5 Y6 Y7
X
L
H
H
H
H
H
H
H
H
H
X
L
L
L
L
L
L
L
L
X
X
L
L
L
L
H
H
H
H
X
X
L
L
H
H
L
L
H
H
X
X
L
H
L
H
L
H
L
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
Outputs
Co)
CO
Select
G
B
A
YO
Y1
Y2
Y3
H
L
L
L
L
X
X
L
L
H
H
L
H
L
H
H
L
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
L
H = high level, L = low level, X = don't care (either low or high logic level)
"G2=G2A+G2B
H = high level, L = low level, X = don't care (either low or high logic level)
Logic Diagrams
S138
ENABLE [::A (.:..:;.:,))_ _
INPUTS
~
G2B (5)
DATA
OUTPUTS
A (1)
SELECT
INPUTS
B (2)
C (3)
TLIF/6466-3
S139
ENABLE G1 (1)
•
DATA
OUTPUTS
ENABLE G2 (15)
(11)2Y1
TL/F/6466-4
3-55
~
;n ~ National
~ Semiconductor
DM54S140/DM74S140
Dual 4-lnput NAND 50.0. Line Driver
General Description
This device contains two Independent line driver gates each
of which performs the logic NAND function.
Connection Diagram
Dual·ln·Llne Package
Vee
114
1
A1
D2
C2
13
2
B1
B2
NC
12
13
NC
A2
111
10
4
5
C1
D1
19
Y2
8
~
1 17
6
Y1
GND
Order Number DM54S140J or DM74S140N
See NS Package Number J14A or N14A
Function Table
y
ABCD
=
Inputs
Output
A
B
C
D
Y
X
X
X
L
H
X
X
L
X
H
X
L
X
X
H
L
X
X
H
H
H
H
L
H = High logic Level
L = Low Logic Level
X
= Either Low or High Logic Level
3·56
X
H
TUF/6467-1
Absolute Maximum Ratings
...en
~
(Note)
Q
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "£/ectrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Input Voltage
5.5V
Operating Free Air Temperature Range
DM54S
- 55'C to + 125'C
DM74S
O'Cto +70'C
Storage Temperature Range
-65'C to + 150'C
Recommended Operating Conditions
Symbol
DM74S140
DM54S140
Parameter
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
Vcc
Supply Voltage
VIH
High Level Input Voltage
Vil
Low Level Input Voltage
0.8
0.8
V
10H
High Level Output Current
-3
-3
rnA
60
mA
70
'C
2
10l
Low Level Output Current
TA
Free Air Operating Temperature
V
2
60
-55
125
0
Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
Conditions
VI
Input Clamp Voltage
Vcc = Min, II = -18 rnA
VOH
High Level Output
Voltage
Vee = Min, Vil = Max
10H = Max
Low Level Output
Voltage
Vee = Min, 10l = Max
VIH = Min
II
Input Current @ Max
Input Voltage
Vcc = Max, VI = 5.5V
Typ
(Note 1)
I
DM54
2.5
3.4
I
DM74
2.7
3.4
Vil = 0.5V, Ro = 50n to GND
VOL
Min
Max
Units
-1.2
V
V
2.0
0.5
V
1
rnA
IIH
High Level Input Current
Vcc = Max, VI = 2.7V
100
p.A
III
Low Level Input Current
Vcc = Max, VI = 0.5V
-4
rnA
los
Short Circuit
Output Current
Vcc = Max
(Note 2)
ICCH
Supply Current with
Outputs High
Vcc = Max
ICCl
Supply Current with
Outputs Low
Vcc = Max
l
I
3-57
DM54
-50
-225
DM74
-50
-225
mA
10
18
mA
25
44
mA
•
~
....
en
Switching Characteristics at Vee =
5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
RL = 930
Symbol
Parameter
CL
= 50pF
CL
= 150pF
Units
Min
Max
Min
Max
tpLH
Propagation Delay Time
Low to High Level Output
2
6.5
3
9
ns
tpHL
Propagation Delay Time
High to Low Level Output
2
6.5
3
9
ns
Note 1: All typlcals are at Vee = 5V, TA = 25'0.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
3·58
~--------------------------------------------------------------------------~
en
....
....
en
~National
~ Semiconductor
DM54S151/DM74S151 1-of-8 Data Selector/Multiplexer
with Complementary Outputs
General Description
Features
These data selectors/multiplexers contain full on-chip decoding to select the desired data source. The '5151 selects
one-of-eight data sources. The '5151 has a strobe input
which must be at a low logic level to enable these devices.
A high level at the strobe forces the W output high and the Y
output low.
•
•
•
•
•
The '5151 features complementary Wand Y outputs.
Select one-of-eight data lines
Performs parallel-to-serial conversion
Permits multiplexing from N lines to one line
Also for use as Boolean function generator
Typical average propagation delay time, data input to W
output 4.5 ns
• Typical power dissipation 225 mW
Connection Diagram
Dual-In-Llne Package
DATA INPUTS
vce
4
116
S
bs b4
6
DATA SELECT
7
ABC
113 b2 j,1. j,o
9
I I I I I
04
os
06
07
A
B
01
DO
Y
W
S
C
03
02
I I J 11
1 12 13 14 15 16 17 18
3
2
1
OATA INPUTS
0
-Y
W STROBEGND
OUTPUTS
TL/F/6468-1
Order Number DM54S151J, DM54S151W or DM74S151N
See NS Package Number J16A, N16E or W16A
Function Table
Outputs
Inputs
Select
C
B
A
Strobe
S
X
L
L
L
X
L
L
X
H
L
H
L
L
L
H
H
H
H
L
L
L
H
L
H
H
H
L
L
L
L
L
L
H
L
H
H
= high level, L = low level, X = don't care
DO, Dl ... D7 = the level of the respective D input
H
3-59
y
W
L
00
01
02
03
04
05
06
07
H
00
01
02
03
04
05
06
07
....
an
....
en
Absolute Maximum Ratings (Not~)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
DM54S
- 55'C to + 125·C
DM74S
O'Cto +70·C
Storage Temperature Range
- 65'C to + 150·C
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Recommended Operating Conditions
Symbol
DM54S151
Parameter
DM74S151
Units
Min
Nom
Max
Min
Nom
Max
5
5.5
4.75
5
5.25
Vee
Supply Voltage
4.5
VIH
High Level Input
Voltage
2
VIL
Low Level Input
Voltage
0.8
0.8
V
IOH
High Level Output
Current
-1
-1
mA
IOL
Low Level Output
Current
20
20
mA
TA
Free Air Operating
Temperature
70
·C
2
-55
125
V
V
0
Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
Min
Typ
(Note 1)
DM54
2.5
3.4
DM74
2.7
3.4
Conditions
VI
Input Clamp Voltage
Vee = Min, 11= -18 mA
VOH
High Level Output
Voltage
Vee = Min, IOH = Max,
VIL = Max, VIH = Min
VOL
Low Level Output
Voltage
Vee = Min, IOL = Max
VIH = Min, VIL = Max
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 5.5V
IIH
High Level Input
Current
Vee = Max, VI = 2.7V
IlL
Low Level Input
Current
Vee = Max, VI = 0.5V
los
Short Circuit
Output Current
Vee = Max
(Note 2)
I
I
I
I
Units
-1.2
V
0.5
V
1
mA
50
",A
-2
mA
DM54
-40
-100
DM74
-40
-100
Supply Current
Vee = Max (Note 3)
Icc
Note 1: All typlcals are at Vee = SV, TA = 2S'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: Icc Is measured with the strobe and data select inputs at 4.SV, all other Inputs and outputs open.
3-60
Max
45
70
mA
mA
Switching Characteristics at Vee =
5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
RL
Symbol
Parameter
From (Input)
To (Output)
CL
Min
=
15pF
=
2800
CL
Max
Min
=
50pF
Units
Max
tpLH
Propagation Delay Time
Low to High Level Output
SelecttoY
(4 Levels)
18
21
ns
tpHL
Propagation Delay Time
High to Low Level Output
SelecttoY
(4 Levels)
18
21
ns
tpLH
Propagation Delay Time
Low to High Level Output
SelecttoW
(3 Levels)
15
18
ns
tpHL
Propagation Delay Time
High to Low Level Output
Select to W
(3 Levels)
13.5
17
ns
tpLH
Propagation Delay TIme
Low to High Level Output
Strobe
toY
16.5
19
ns
tpHL
Propagation Delay Time
High to Low Level Output
Strobe
toY
18
21
ns
tpLH
Propagation Delay Time
Low to High Level Output
Strobe
toW
13
16
ns
tpHL
Propagation Delay Time
High to Low Level Output
Strobe
toW
12
16
ns
tpLH
Propagation Delay Time
Low to High Level Output
DOthru 07
toY
12
15
ns
tpHL
Propagation Delay Time
High to Low Level Output
DOthru 07
toY
12
15
ns
tpLH
Propagation Delay Time
Low to High Level Output
DOthru 07
toW
7
9
ns
tpHL
Propagation Delay Time.
High to Low Level Output
DOthru 07
toW
7
10
ns
•
3·61
....
an
....
tn
Logic Diagram
8151
DATA [A
SELECT
B
(BINARV)
C
--;.;:KJ--q ; _ - - -...
TLiF/6468-2
3-62
rn
.....
U1
~National
Co)
~ Semiconductor
DM54S 153/DM74S 153 Dual 1 of 4 Line Data
Selectors/Multiplexers
General Description
Features
Each of these data selectors/multiplexers contains inverters and drivers to supply fully complementary, on-chip, binary decoding data selection to the AND-DR-invert gates.
Separate strobe inputs are provided for each of the two
four-line sections.
• Permits multiplexing from N lines to 1 line
• Performs parallel-to-serial conversion
• Strobe (enable) line provided for cascading (N lines to
n lines)
• High fan-out, low-impedance, totem-pole outputs
• Typical average propagation delay times
From data 6 ns
From strobe 9.5 ns
From select 12 ns
• Typical power dissipation 225 mW
Logic and Connection Diagrams
Dual-In-Line Package
DATA INPUTS
vcc
STROBE A
G. SELECT .C3
• OUTPUT
.co
y.
'C'
.Cl
lCl
'CO OUTPUT GND
• Yl
DATA 1
~: :;.; . .-: ---+t-I::::~
DATA 2
~
STROBE
----oI==t==t3:r1
01
zcz(;;;'·;;..)
B
1C3
SELECT'
1C'
DATA INPUTS
t)
.d'::;3 i;:==~:;§t[)
TL/F/6469-2
Order Number DM54S153J or DM74S153N
See NS Package Number J16A or N16E
STROBE G.('.!)
TL/F/6469-1
Function Table
Select
Inputs
Data Inputs
Output
B
A
CO
C1
C2
C3
G
y
X
X
X
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
H
X
X
X
L
H
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
H
L
L
L
L
L
L
L
L
L
L
H
L
H
L
H
L
H
X
X
X
X
X
X
Select inputs A and B are common
H
Strobe
~
High Level, L
~
Low Level, X
L
H
to both sections.
~
Don't Care
3-63
•
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
OHlce/Dlstrlbutors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
- 55·C to + 125·C
DM54S
DM74S
O·Cto +70·C
-65·Cto + 150"C
Storage Temperture Range
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Recommended Operating Conditions
Symbol
. DM54S153
Parameter
DM74S153
Units
Min
Nom
Max
Min
Nom
Max
5
5.5
4.75
5
5.25
V
Vee
Supply Voltage
4.5
VIH
High Level Input
Voltage
2
VIL
Low Level Input
Voltage
0.8
0.8
V
10H
High Level Output
Current
-1
-1
mA
10L
Low Level Output
Current
20
20
mA
TA
Free Air Operating
Temperature
70
·C
2
-55
125
V
0
Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
VI
Input Clamp Voltage
VOH
High Level Output
Voltage
Min
Typ
(Note 1)
DM54
2.5
3.4
DM74
2.7
3.4
Conditions
= Min, II = -18 mA
= Min, 10H = Max,
VIL = Max, VIH = Min
Vcc = Min, 10L = Max
VIH = Min, VIL = Max
Vcc
Vcc
VOL
Low Level Output
Voltage
II
Input Current @ Max
Input Voltage
Vcc
IIH
High Level Input
Current
IlL
los
I
I
Max
Units
-1.2
V
V
0.5
V
= Max, VI = 5.5V
1
mA
Vcc
= Max, VI = 2.7V
50
/LA
Low Level Input
Current
Vee
= Max, VI = 0.5V
-2
mA
Short Circuit
Output Current
Vcc = Max
(Note 2)
I
I
DM54
-40
-100
DM74
-40
-100
Supply Current
Vcc = Max (Note 3)
typical. are at Vee = 5V, TA = 25·C.
Nota 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Nota 3: lee i. measured with all outputs open and all Inputs grounded.
lee
Nate 1: All
3-64
45
70
mA
mA
Switching Characteristics at Vee =
rn
.....
5V and T A
=
25'C (See Section 1 for Test Waveforms and Output Load)
RL
Symbol
Parameter
From (Input)
To (Output)
CL
Min
=
1SpF
Max
=
2800
CL
Min
=
SOpF
Units
Max
tpLH
Propagation Delay Time
Low to High Level Output
Data
toY
9
12
ns
tpHL
Propagation Delay Time
High to Low Level Output
Data
toY
9
12
ns
tpLH
Propagation Delay Time
Low to High Level Output
Select
toY
18
20
ns
tpHL
Propagation Delay Time
High to Low Level Output
Select
toY
18
21
ns
tpLH
Propagtion Delay Time
Low to High Level Output
Strobe
toY
15
18
ns
tpHL
Propagation Delay Time
High to Low Level Output
Strobe
toY
13.5
17
ns
3·65
c.n
Co)
m r----------------------------------------------------------------------------.
Ln
....
tn ~National
•
II; ~ Semiconductor
....
tn
DM54S 157/DM74S 157, DM54S 158/DM74S 158
Quad 1 of 2 Line Data Selectors/Multiplexers
General Description
Features
These data selectors/multiplexers contain inverters and
drivers to supply full on-chip data selection to the four output gates. A separate strobe input is provided. A 4-bit word
is selected from one of two sources and is routed to the four
outputs. The 5157 presents true data whereas the 5158
presents inverted data to minimize propagation delay time.
• Buffered inputs and outputs
• Typical propagation time
51575 ns
51584 ns
• Typical power dissipation
5157250 mW
5158195 mW
Applications
• Expand any data input point
• Multiplex dual data buses
• Generate four functions of two variables (one variable
is common)
• 50urce programmable counters
Connection Diagrams (Dual-In-Line Packages)
STROBE
vcc
1~6
G
15
INPUTS
OUTPUT
INPUTS
' A4
B4
Y4
' A3
B3
14
13
12
11
OUTPUT
vcc
Y3
10
9
STROBE
INPUTS
OUTPUT
INPUTS
OUTPUT
G
'A4
B4'
Y4
'A3
B3'
Y3
116
-
15
14
13
2
3
4
12
11
10
9
-
3
4
6
S
,A:
B1
Y1
A:
B2
Y:
G!:
SELECT
INPUTS' OUTPUT ' INPUrS ' OUTPUT
S
A1
B1.
Y1
SELECT
INPUTS
OUTPUT
TL/F/6470-1
TLlF/6470-2
Order Number DM54S157J, DM54S157W or DM74S157N
See NS Package Number J16A, N16E or W16A
Order Number DM54S158J, DM54S158W or DM74S158N
See NS Package Number J16A, N16E or W16A
Function Table
Inputs
OutputY
Strobe
Select
A
B
S157
S158
H
L
L
L
L
X
L
L
X
L
H
H
H
X
X
X
X
X
L
L
L
H
L
H
H
H
L
H
L
H
H = High Level. L = Low Level, X = Don't Care
3-66
Absolute Maximum Ratings
tJ)
.....
en
(Note)
.....a
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaran·
teed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
DM54S
-55'Cto +125'C
DM74S
O'Cto +70'C
Storage Temperature Range
-65'Cto + 150'C
Recommended Operating Conditions
Symbol
DM74S157
DM54S157
Parameter
Units
Min
Nom
Max
Min
Nom
Max
5
5.5
4.75
5
5.25
Vee
Supply Voltage
4.5
VIH
High Level Input
Voltage
2
VIL
Low Level Input
Voltage
0.8
0.8
V
10H
High Level Output
Current
-1
-1
mA
IOL
Low Level Output
Current
20
20
mA
TA
Free Air Operating
Temperature
70
'C
2
-55
125
V
V
0
'8157 Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
Min
Typ
(Note 1)
DM54
2.5
3.4
DM74
2.7
3.4
Conditions
VI
Input Clamp Voltage
Vee = Min, II = -18 mA
VOH
High Level Output
Voltage
Vee = Min
IOH = Max
VIL = Max
VIH = Min
Max
Units
-1.2
V
V
VOL
Low Level Output
Voltage
Vee = Min, 10L = Max
VIH = Min, VIL = Max
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 5.5V
IIH
High Level Input
Current
Vee = Max
VI = 2.7V
SorG
100
AorB
50
High Level Input
Current
Vee = Max
VI = 0.5V
SorG
-4
AorB
-2
Short Circuit
Output Current
Vee = Max
(Note 2)
DM54
-40
-100
DM74
-40
-100
Supply Current
Vee = Max
(Note 3)
IlL
los
lee
50
Note 1: All typicals are at Vee = SV. TA = 2S'C.
Note 2: Not more than one output should be shorted at a lime. and the duration should not exceed one second.
Note 3: ICC is measured 4.SV applied to all inputs and all outputs open.
3·67
0.5
V
1
mA
78
IJoA
mA
mA
mA
•
....en
tJ)
CO
'S157 Switching Characteristics at Vee =
5V and TA = 25'C
(See Section 1 for Test Waveforms and Output Load)
Symbol
tpLH
tpHl
tplH
tpHl
tplH
tpHl
From
(Input)
To
(Output)
Parameter
Propagation Delay
Time Low to High
Level Output
Data
to
Propagation Delay
Time High to Low
Level Output
RL
CL
= 2800
= 15pF
Min
CL
Max
= 50pF
Min
Units
Max
7.5
10
ns
Data
to
Y
6.5
10
ns
Propagation Delay
Time Low to High
Level Output
Strobe
to
Y
12.5
15
ns
Propagation Delay
Time High to Low
Level Output
Strobe
to
12
15
ns
Propagation Delay
Time Low to High
Level Output
Select
to
Y
15
17
ns
Propagation Delay
Time High to Low
Level Output
Select
to
15
17
ns
y
y
y
Recommended Operating Conditions
Symbol
DM74S158
DM54S158
Parameter
Units
Min
Nom
Max
Min
Nom
Max
5
5.5
4.75
5
5.25
Vee
Supply Voltage
4.5
VIH
High Level Input
Voltage
2
Vil
Low Level Input
Voltage
0.8
0.8
V
IOH
High Level Output
Current
-1
-1
mA
IOl
Low Level Output
Current
20
20
mA
TA
Free Air Operating
Temperature
70
'C
2
-55
125
3-68
0
V
V
....
(J)
'S 158 Electrical Characteristics
UI
.....
•
over recommended operating free air temperature (unless otherwise noted)
....
(J)
Symbol
Parameter
Conditions
VI
Input Clamp Voltage
VOH
High Level Output
Voltage
= Min,ll =
Vee = Min
10H = Max
VIL = Max
VIH = Min
Vee
Typ
(Note 1)
Min
-18mA
OM 54
2.5
3.4
DM74
2.7
3.4
Max
Units
-1.2
V
V
VOL
Low Level Output
Voltage
Vee = Min, IOL = Max
VIH = Min, VIL = Max
II
Input Current @ Max
Input Voltage
Vee
IIH
High Level Input
Current
Vee = Max
VI = 2.7V
SorG
100
AorB
50
Low Level Input
Current
Vee = Max
VI = 0.5V
SorG
-4
AorB
-2
Short Circuit
Output Current
Vee = Max
(Note 2)
DM54
-40
-100
DM74
-40
-100
leel
Supply Current
Vee
lee2
Supply Current
Vee
IlL
los
=
=
=
Max, VI
=
0.5
V
1
mA
5.5V
39
Max (Note 3)
Max (Note 4)
'S158 Switching Characteristics at Vee =
5VandTA
=
UI
CD
/LA
mA
mA
61
mA
81
mA
25'C
(See Section 1 for Test Waveforms and Output Load)
Symbol
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
From
(Input)
To
(Output)
Parameter
Propagation Delay
Time Low to High
Level Output
Data
to
Propagation Delay
Time High to Low
Level Output
Data
to
Propagation Delay
Time Low to High
Level Output
Strobe
to
Propagation Delay
Time High to Low
Level Output
Strobe
to
Propagation Delay
Time Low to High
Level Output
Select
to
Propagation Delay
Time High to Low
Level Output
Select
to
Note 1: All typlcals are at Vee
~
SV, TA
~
RL
CL
=
=
28011
15pF
Min
Max
CL
Min
=
Units
50pF
Max
6
9
ns
6
9
ns
11.5
12
ns
12
14
ns
12
15
ns
12
15
ns
y
y
y
y
y
Y
2S·C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: ICCI Is measured with all outputs open and all Inputs at 4.SV.
Note 4: ICC2 is measured with B, G, and 5 inputs grounded, A Inputs at 4.SV, and all outputs open.
3·69
•
~~~~==~-------------------------------------U)
•
t;
..(/)
Logic Diagrams
8157
Al (2)
Bl (3)
A2.(5_)______________~~~~
B2_(6_)______________~~~~
A3 (11)
B3 (10)
A4 (14)
B4 (13)
STROBE G ;-:(1!t'5_)- - - -.....
SELECT S .(1.;.).....
_<:1'-
-----1--<:.
j
TL/F/6470-3
8158
Al (2)
+-__
Bl_(3_)______________
~~
A2_(5_)______________+-~~~
B2 (6)
A3 (11)
B3 (10)
A4 (14)
B4 (13)
_:r-_
STROBE G j;(1i\5;...)- - - -....
...-----'---J
,., ..... ,
L
I
ci'
L
I
~
IT
v QC
1121
J
1-~r---1~-HH-I-=t§~~~
CL.~--:J
~.~
I
-
., 0::' -
~
0_
"-
~r~QD-(11
I
J
-'='>---
-'
_::::'"'
.;<>"'-_ _ _ _ __
) ( S 161 option
TLIF16471-2
3-74
en
....
m
....
en
....•
Timing Diagram
S161, S163 Synchronous Binary Counters
Typical Clear, Preset, Count and Inhibit Sequences
m
~
CLEAR----'
8161
CLEAR
5163
LOAD
r-------------r-------------r---+---T--------------
A --+-----'" _ _ _ _ _ _ _ _ _ _ _ _ _ _
B
DATA
{
INPUTS
C
D
CLOCK
5161
L _____________ _
.---4----..-----------------+..,
CLOCK
8163
ENABLE P
ENABLE T
---1---41
---+-+J
QA--
{
OUTPUTS
==
Q.-lie
-If--+_-+_--'
QD--
RIPPLEOCUAT~~~----+--+-IZ-+1~3-1..,4-.....15
I----COUNT ----·I~~--INHIBIT--CLEAR PRESET
TUFf6471-3
•
3·75
....~
....co•
....
en
en
Parameter Measurement Information
SwItchIng TIme Waveforms
CLOCK
INPUT
-F\-I
OV
IpLH
IpHL
(MEASURE AT IN")
(MEASURE AT IN")
OUTPUT VOH--+--h~---!_
OA
OUTPUT
O.
r---",
VOL
VOH
VOL
VOH
OUTPUT
Dc VOL
VOH
OUTPUT
00
RIPPLE
CARRY
OUTPUT
VOH
VOL
TL/F/6471-4
Note A: The Inpul pulses are supplied by generators having the following characteristics: PRR .: I MHz, duty cycle.: SO%, ZOUT '"
t,. .: 2.S ns, It .: 2.5 n8. Vary PRR 10 measure fMAX.
Note B: Outputs Qo and carry arelested alln
+
son. For S161/163,
16 for S161, S163 wherein Is Ihe bit time when all oulpuls are low.
Note C: VREF - 1.6V.
SwItchIng TIme Waveforms
CLOCK INPUT 3 . 0 V - - - - - - - ' ' '
ISlA
OV:::~----~::::$:====~~~~-------
3.0V
CLEAR
INPUT
OV---t~~~
LOAD 3.0V --t---t----"""I.
INPUT
DATA INPUTS
A, B, C, AND 0
o OUT~~1~
OV---t----1-----++~~
3.0V
----I----+-----+t,.-'"
VOH
VOL--+--V~~--+---~JI
ENABLE P OR
ENABLET
3.0V ---tf---1-----+---rt--'\.
OV---~~---~---~~~I
VOH--4---4--~=+~-L-~---~~;,.--,
CARRY
VOL--~-~~~_+--_+-----J
CLOCK INPUT 3.0V
IS3A
OOUT~~~! VOH - - - -....'""
VDL--------+~~~-------_+-'
TL/F/6471-5
Note A: The Input pulses are supplied by generators having the following characteristics: PRR .: 1 MHz, duty cycle.: SO%, ZOUT '" SOO.t,. .: 2.S ns, It .: 2.5 n••
Vary PRR 10 measure fMAX.
Note B: Enable P and enable T setup times are measured at In + O.
Note C: VREF = 1.5V.
3·76
-.,..•
r-----------------------------------------------------------------~0
......
I?A National
~ Semiconductor
tJ)
......
en
DM54S174/DM74S174, DM54S175/DM74S175
Hex/Quad D Flip-Flops with Clear
General Description
Features
These positive-edge-triggered flip-flops utilize TTL circuitry
to implement D-type flip-flop logic. All have a direct clear
input, and the quad (175) versions feature complementary
outputs from each flip-flop.
•
•
•
•
•
Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going
edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition
time of the positive-going pulse. When the clock input is at
either the high or low level, the D input signal has no effect
at the output.
S174 contain six flip-flops with single-rail outputs.
S175 contain four flip-flops with double-rail outputs.
Buffered clock and direct clear inputs
Individual data input to each flip-flop
Applications include:
Buffer/storage registers
Shift registers
Pattern generators
• Typical clock frequency 110 MHz
• Typical power dissipation per flip-flop 75mW
Connection Diagrams
Dual-In-Llne Package
VCC
06
D6
D5
05
D4
Dual·ln·Llne Package
04
CLOCK
D3
03
D2
02
CLOCK
13
4
CLEAR
01
D1
D2
Q2
D3
03
GND
TL/F/6472-1
GND
TLlF/6472-2
Order Number DM54S174J, DM54S175J, DM54S175W, DM74S174N or DM74S175N
See NS Package Number J16A, N16E or W16A
Function Table (Each Flip-Flop)
Inputs
Outputs
Clear
Clock
D
Q
L
H
H
H
x
t
t
X
H
L
X
L
H
L
Qo
L
at
H
L
H
00
= High Level (steady state)
L = Low Level (steady state)
X = Don't Care
t = Transition from low to high level
H
00 = The level of a before the indicated steady·state Input conditions were established.
t = St75 only
3-77
•
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guarenteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual ci9vice operation.
If MIlitary/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
DM54S
- 55·C to + 125·C
O·Cto +70·C
DM74S
Storage Temperature Range
-65'Cto + 150'C
Recommended Operating Conditions See Section 1 for Test Waveforms and Output Load
Symbol
DM74S175
DM54S174
Parameter
Unlta
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
VCC
Supply Voltage
VIH
High Level Input Voltage
Vil
Low Level Input Voltage
0.8
0.8
V
IOH
High Level Output Current
-1
-1
mA
IOl
Low Level Output Current
20
20
mA
2
2
V
fClK
Clock Frequency (Note 1)
0
110
75
0
110
75
MHz
fClK
Clock Frequency (Note 2)
0
90
85
0
90
85
MHz
tw
Pulse Width
(Note 1)
Clock
7
7
Clear
10
10
Pulse Width
(Note 2)
Clock
9
9
Clear
ns
tsu
tH
IREl
TA
12
12
Data Setup Time (Note 1)
5
5
Data Setup Time (Note 2)
7
7
Data Hold Time (Note 1)
3
3
Data Hold Time (Note 2)
5
5
ns
Clear Release Time (Note 1)
5
5
Clear Release Time (Note 2)
7
7
Free Air Operating Temperature
ns
ns
-55
125
= 1S pF, RL = 2800, TA = 2S'C and Vee = SV.
Note 2: ~ = SO pF, RL = 2800, TA = 2S'C and Vee = SV.
Note 1: CL
3-78
0
70
·C
Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
Min
Typ
(Note 1)
DM54
2.5
3.4
DM74
2.7
3.4
Conditions
= Min,ll = -18 mA
VI
Input Clamp Voltage
Vee
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
VIL = Max, VIH = Min
VOL
Low Level Output
Voltage
Vee = Min, 10L = Max
VIH = Min, VIL = Max
II
Input Current @ Max
Input Voltage
Vee
IIH
High Level Input
Current
IlL
los
I
I
Max
Units
-1.2
V
V
0.5
V
= Max, VI = 5.5V
1
mA
Vee
= Max, VI = 2.7V
50
p.A
Low Level Input
Current
Vee
= Max, VI = 0.5V
-2
mA
Short Circuit
Output Current
Vee = Max
(Note 2)
lee
Supply Current
(S174)
Vee = Max
(Note 3)
90
144
mA
lee
Supply Current
(S175)
Vee = Max
(Note 3)
60
96
mA
Switching Characteristics at Vee =
I
I
DM54
-40
-100
DM74
-40
-100
5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
RL
Symbol
Parameter
mA
From (Input)
To (Output)
CL
Min
= 15pF
Max
CL
Min
= 50pF
Units
Max
fMAX
Maximum Clock Frequency
tpLH
Propagation Delay Time
Low to High Level Output
Clock to
Output
12
15
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clock to
Output
17
21
ns
tpLH
Propagation Delay Time
Low to High Level Output
(S175 Only)
15
18
ns
22
23
ns
Propagation Delay Time
High to Low Level Output
Nole I: All typicals are at Vee = SV. TA = 2S'C.
tpHL
75
= 2800
Clear to
Q
Clear
toQ
65
MHz
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: With all outputs open and 4.SV applied to all DATA and CLEAR inputs. Icc is measured aller a momentary ground. then 4.SV applied to the CLOCK input.
3-79
........
en
........-.:r•
en
II)
Logic Diagrams
5174
5175
(3)
01
(2)
0
01
01
U
(2)
(4)
D
Q1
0
CLOCK
CLOCK
CLEAR
CLEAR
(3)
0
(4)
02
(5)
(5)
0
02
02
0
01
(7)
D
0
02
CLOCK
(6)
0
02
CLEAR
(12)
(6)
03
03
03
(10)
0
03
0
CLOCK
(11)
0
CLEAR
(11)
04
(13)
(10)
0
03
CLEAR
04
04
0
(15)
0
04
0
CLOCK
CLOCK
CLOCK
CLEAR
(14)
0
CLEAR
04
CLEAR
(13)
05
(12)
0
TLlF16472-4
05
0
CLOCK
CLEAR
os
(15)
(14)
0
0
06
CLOCK
CLOCK
CLEAR
CLEAR
TLIF16472-3
3-80
tJ)
.....
.....
CQ
~NatiOnal
Semiconductor
DM54S181/DM74S181 Arithmetic Logic
Unit/Function Generators
General Description
Features
These arithmetic logic units (ALU)/function generators perform 16 binary arithmetic operations on two 4-bit words, as
shown in Tables 1 and 2. These operations are selected by
the four function-select lines (SO, 51, 52, 53) and include
addition, subtraction, decrement, and straight transfer.
When performing arithmetic manipulations, the internal carries must be enabled by applying a low-level voltage to the
mode control input (M). A full carry look-ahead scheme is
available in these devices for fast, simultaneous carry generation by means of two cascade-outputs (P and G) for the
four bits in the package. When used in conjunction with the
DM54S182/DM74S182 full carry look-ahead circuits, highspeed arithmetic operations can be performed. The typical
addition times shown below illustrate how little time is required for addition of longer words, when full carry lookahead is employed. The method of cascading 182 circuits
with these ALU's to provide multi-level full carry look-ahead
is illustrated under typical applications data for the
DM54S182/DM74S182.
(Continued)
• Arithmetic operating modes:
Addition
Subtraction
Shift operand A one position
Magnitude comparison
Plus twelve other arithmetic operations
• Logic function modes:
EXCLUSIVE-OR
Comparator
AND, NAND, OR, NOR
Plus ten other logic operations
• Full look-ahead for high-speed operations on long
words
Connection Diagram
Pin Designations
Dual-In-Llne Package
OUTPUTS
INPUTS
.
,
A2
vcc AI Bl
f24
2322
..
\
B2
21
A3 B3
20 19
18
G Cn+4 P A=B F3
17
16
15 14
1
13
p-
-<:
,BO
,
2
3
AD S3
4
.
5
52 51
INPUTS
6
7
so Cn
8
9
,\"FO
M
10
Fl
11112
,
Designation
Pin Nos.
Function
A3, A2, A1, AO
19,21,23,2
Word A Inputs
83,82,81,80
18,20,22,1
Word 8 Inputs
53,52,51, SO
3,4,5,6
Function-Select
Inputs
Cn
7
Inv. Carry Input
M
8
Mode Control
Input
F3,F2,F1,FO
13,11,10,9
Function Outputs
A=B
14
Comparator Output
P
15
Carry Propagate
Output
Cn +4
16
Inv. Carry Output
G
17
Carry Generate
Output
Vce
24
Supply Voltage
GND
12
Ground
F2 GND
OUTPUTS
TL/F/6473-1
Order Number DM54S181J or DM74S181N
See NS Package Number J24A or N24A
3-81
•
....
co
C;;
General Description
(Continued)
If high speed is not important, a ripple-carry input (C n) and a
ripple-carry output (Cn+4) are available. However, the ripple-carry delay has also been minimized so that arithmetic
manipulations for small word lengths can be performed
without external circuitry.
relative magnitude information. Again, the ALU should be
placed in the subtract mode by placing the function select
inputs 53, 52, 51, SO at L, H, H, L, respectively.
These circuits have been designed to not only incorporate
all of the designer's requriements for arithmetic operations,
but also to provide 16 possible functions of two Boolean
variables without the use of external circuitry. These logic
functions are selected by use of the four function-select inputs (SO, 51, 52, 53) with the mode-control input (M) at a
high level to disable the internal carry. The 16 logiC functions are detailed in Tables 1 and 2 and include exclusiveOR, NAND, AND, NOR, and OR functions.
These circuits will accommodate active-high or active-low
data, if the pin designations are interpreted as shown below.
Subtraction is accomplished by 1's complement addition,
where the 1's complement of the subtrahend is generated
internally. The resultant output is A-B-1, which requires
an end-around or forced carry to provide A-B.
The 5181 can also be utilized as a comparator. The A = B
output is internally decoded from the function outputs (FO,
F1, F2, F3) so that when two words of equal magnitude are
applied at the A and B inputs, it will assume a high level to
indicate equality (A = B). The ALU should be in the subtract
mode with Cn = H when performing this comparison. The A
= B output is open-collector so that it can be wire-AND
connected to give a comparison for more than four bits. The
carry output (Cn + 4) can also be used to supply
ALU SIGNAL DESIGNATIONS
The DM545181/DM745181 can be used with the signal
designations of either Figure 1 or Figure 2.
The logic functions and arithmetic operations obtained with
signal designations as in Figure 1 are given in Table I; those
obtained with the signal designations of Figure 2 are given
in Table II.
Package Count
Number
of
Bits
Typical
Addition Times
1 t04
5t08
9to 16
17 to 64
20 ns
30ns
30ns
50ns
Arlthmetlcl
Logic Units
Look Ahead
Carry Generators
Carry Method
Between
ALU's
1
2
30r4
5to 16
0
0
1
2to 5
None
Ripple
Full Look-Ahead
Full Look-Ahead
Pin Number
2
1
23
22
21
20
19
18
9
10
11
13
7
16
15
Active-High Data (Table I)
AO
BO
A1
B1
A2
B2
A3
B3
FO
F1
F2
F3
Cn
Cn+4
X
y
Active-Low Data (Table II)
AO
80
A1
81
A2
82
A3
83
FO
F1
F2
F3
Cn
Cn+4
P
G
Input
Cn
Output
Cn +4
Active-High Data
(Figure 1)
Active-Low Data
(Figure 2)
H
H
L
L
H
L
H
L
A:S:B
A:S:B
A:S:B
A:S:B
A:S:B
A:S:B
A:S:B
A:S:B
3-82
17
General Description
en
.....
Q)
.....
(Continued)
(2) (1)
(23) (22) (21) (20) (19) (18)
I I 11 J I I I
(7)
---<
rc
AO 80
Al 81
A2 82
A3 83
Cn
A = 8 I-- (14)
S181
(8)- r-- M
FO
Fl
F2
F3
(t
(ll)
(1'1)
(1~)
(3) 1(4)
VO XO
Cn+4
(!)
x
V
1(17) (15)
TT (t(T TT
VI Xl
V2 X2
V3 X3
X 1--(7)
(1~
S182
Cn
V t--(10)
Cn+ x
Cn+ y
Cn+ z
(X)
(X)
J)
TLlF/6473-2
FIGURE 1
TABLE I
Active High Data
Selection
53
52
51
SO
M=H
Logic
Functions
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
F=A
F=A+B
F = AB
F=O
F = AB
F=S
F=AEIlB
F = AS
F=A+B
F=AEIlB
F=B
F=AB
F=1
F=A+8
F=A+B
F=A
M = Lj Arithmetic Operations
Cn = H (no carry)
Cn = L (with carry)
F=A
F=A+B
F=A+S
F = Minus 1 (2's Campi)
F = A Plus AS
F = (A + B) Plus AS
F = A Minus B Minus 1
F = AS Minus 1
F = APlusAB
F = A Plus B
F = (A + S) PlusAB
F = AB Minus 1
F = A PlusA*
F = (A + B) Plus A
F = (A + 8) Plus A
F = A Minus 1
F=APlus1
F = (A + B) Plus 1
F = (A + S) Plus 1
F = Zero
F = A Plus As Plus 1
F = (A + B) Plus AS Plus 1
F = A Minus B
F= AS
F = A Plus AB Plus 1
F = A Plus B Plus 1
F = (A + 8) PlusAB Plus 1
F= AB
F=APlusAPlus1
F = (A + B) PlusA Plus 1
F = (A + 8) Plus A Plus 1
F=A
'Each bit Is shifted to the next more significant position.
3·83
......co
tn
General Description (Continued)
TT (r(r (A' (!' (1'T'
AO BO
(71_~
A1 B1
A2 B2
A3 B3
Cn
A=B
S181
~(141
(81- ~ M
FO
F1
F2
Cn +4
F3
JI (XI (X) (XI (l61
)T T TIl)
(3t4
GO PO
(';;j
G1 P1
G2 P2
P
G
l17 (15)
TT
G3 P3
P P-(71
S182
Cn
GP-(10)
Cn + x
Cn + y
Cn + z
(1t
)11
(t
TL/F/6473-3
FIGURE 2
TABLE II
Active Low Data
Selection
M=H
S3
S2
S1
SO
Logic
Functions
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
F=A
F= AS
F=A+B
F=1
F=A+B
F=S
F=AIIlB
F=A+S
F= AB
F=AIIlB
F=B
F=A+B
F=O
F = A+ AS
F=AB
F=A
M = L" Arithmetic Operations
Cn = L (no carry)
Cn = H (with carry)
F = A Minus 1
F = AS Minus 1
F = AS Minus 1
F = Minus 1 (2's Compl)
F = A Plus (A + S)
F = AB Plus (A + B)
F = A Minus B Minus 1
F=A+S
F = A Plus (A + B)
F = APlusB
F = AS Plus (A + B)
F=A+B
F=APlusA*
F = AB Plus A
F = AS Plus A
F=A
F=A
F = AB
F= AS
F = Zero
F = A Plus (A + S) Plus 1
F = AB Plus (A + S) Plus 1
F = A Minus B
F=(A+S)Plus1
F = A Plus (A + B) Plus 1
F = A Plus B Plus 1
F = AS Plus (A + B) Plus 1
F = (A + B) Plus 1
F = A Plus A Plus 1
F = AB PlusA Plus 1
F =AS PlusA Plus 1
F = APlus1
'Each bills shifted 10 Ihe next more slgnificanl posilion.
3-84
....
....
(f)
Absolute Maximum Ratings
Q)
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
Input Voltage
Output Voltage (A
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
7V
=
5.5V
5.5V
B Output)
Operating Free Air Temperature Range
DM54S
-55'Cto + 125'C
DM74S
O'Cto +70'C
Storage Temperature Range
- 65'C to + 150'C
Recommended Operating Conditions
Symbol
DM54S181
Parameter
DM74S181
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
0.8
0.8
V
VOH
High Level Output
Voltage (A = B Output)
5.5
5.5
V
10H
High Level Output
Current (All Except A
-1
-1
mA
20
mA
70
'C
=
2
2
B)
10L
Low Level Output Current
TA
Free Air Operating
Temperature
V
20
-55
125
0
Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
Conditions
=
=
VI
Input Clamp Voltage
Vee
leEX
High Level Output
Current (A = B Output)
Vee = Min, Vo
VIL = Max, VIH
VOH
High Level Output
Voltage (All Except A
=
B)
Min,ll
VOL
Low Level Output
Voltage
Vee = Min, 10L = Max
VIH = Min, VIL = Max
II
Input Current @ Max
Input Voltage
Vee
IIH
High Level Input
Current
Vee = Max
VI = 2.7V
IlL
Max, VI
=
DM54
2.5
3.4
DM74
2.7
3.4
5.5V
Vee = Max
VI = 0.5V
Low Level Input
Current
Typ
(Note 1)
-18 mA
= 5.5V
= Min
Vee = Min, 10H = Max
VIL = Max, VIH = Min
=
Min
Short Circuit Output Current
(Any Output Except A = B)
Vee
=
Max (Note 2)
lee
Supply Current
Vee
=
Max (Note 3)
NOle 1: All typicals are at Vcc
~
SV. TA
~
Units
-1.2
V
250
".A
V
0.5
V
1
mA
Mode
50
AorB
150
S
200
Carry
250
Mode
-2
AorB
-6
S
-8
".A
mA
-10
Carry
los
Max
-40
120
-100
mA
220
mA
2S·C.
Nole 2: Not more than one output should be shorted at a time. and the duration should not exceed one second.
Nole 3: Icc is measured for the following conditions: A. SO through 53. M. and A inputs at 4.SV. all other inputs grounded and all outputs open. B. SO through 53
and M inputs at 4.SV. all other inputs grounded and all outputs open.
3-85
•
....
co
....
en
Switching Characteristics Vee =
Symbol
Parameter
tPLH
Propagation Delay Time,
Low-to-High Level Output
Conditions
5V, T A = 25°C (5ee 8ection 1 for Test Waveforms and Output Load)
From
To
(Input) (Output)
DMS4174
S181
RL = 2800,
CL = 1SpF
Min
tpHL
Propagation Delay Time,
High-to-Low Level Output
tpLH
Propagation Delay Time, M = OV,50 =
Low-to-High Level Output 53 = 4.5V
51 = 52 = OV
Propagation Delay Time,
(8UMmode)
High-to-Low Level Output
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
Cn
Any A
orB
Propagation Delay Time,
M = OV
Low-to-High Level Output
(5UMor
Propagation Delay Time, DIFFmode)
High-to-Low Level Output
AnyF
Any A
orB
G
Propagation Delay Time, M = OV,50 =
Low-to-High Level Output 83 = 4.5V
81 = 52 = OV
Propagation Delay Time,
High-to-Low Level Output (5UMmode)
P
Propagation Delay Time, M = OV,50 =
Low-to-High Level Output 83 = OV
Any A
81 = 82 = 4.5V or B
Propagation Delay TIme,
High-to-Low Level Output (DiFFmode)
Propagation Delay Time, M = OV,80 =
Low-to-High Level Output 83 = 4.5V
81 = 52 = OV
Propagation Delay Time,
(8UMmode)
High-to-Low Level Output
AjorBj
Propagation Delay Time, M = OV,50 =
Low-to-High Level Output 83 = OV
AjorBj
81 = 52 = 4.5V
Propagation Delay Time,
(DIFFmode)
High-to-Low Level Output
Propagation Delay Time,
Low-to-High Level Output M = 4.5V
Propagation Delay Time, (logic mode)
AjorBj
tpHL
Propagation Delay Time, M = OV,80 =
Low-to-High Level Output 83 = OV
Any A
81 = 52 = 4.5V orB
Propagation Delay Time,
High-to-Low Level Output (DIFFmode)
10.5
14
10.5
14
18.5
22
18.5
22
23
27
23
27
12
14
12
14
12
15
12
15
15
19
15
20
12
15
12
15
15
19
15
20
16.5
20
16.5
20
20
24
22
24
20
24
22
24
23
26
30
33
ns
ns
ns
ns
ns
ns
ns
ns
P
Fj
Fj
Fj
High-to-Low Level Output
tpLH
Max
G
Propagation Delay Time, M = OV,50 =
Low-to-High Level Output 83 = OV
Any A
51 = 52 = 4.5V orB
Propagation Delay Time,
(DIFFmode)
High-to-Low Level Output
Any A
orB
Min
Cn +4
Cn +4
Propagation Delay Time, M = OV,50 =
Low-to-High Level Output 53 = 4.5V
51 = 52 = OV
Propagation Delay Time,
High-to-Low Level Output (5UMmode)
Max
Units
Cn +4
Propagation Delay Time, M = OV,50 =
Low-to-High Level Output 53 = OV
Any A
51 = 82 = 4.5V orB
Propagation Delay Time,
(DIFFmode)
High-to-Low Level Output
Cn
RL = 2800,
CL = SOpF
ns
ns
ns
A=B
3-86
ns
tn
....
CD
....
Parameter Measurement Information
Logic Mode Test Table
Function Inputs: S1 = S2 = M = 4.5V, SO = S3 = OV
Parameter
tpLH
Input
Under
Test
Other Input
Same Bit
Other Data Inputs
Output
Waveform
Apply
4.5V
Apply
GND
Apply
4.5V
Apply
GND
Aj
BI
None
None
Remaining
AandB,Cn
Fi
Out·of·Phase
Bi
Ai
None
None
Remaining
AandB,Cn
Fi
Out·of·Phase
Output
Under
Test
Output
Waveform
tpHL
tpLH
Output
Under
Test
tpHL
SUM Mode Test Table
Function Inputs: SO = 53 = 4.5V, S1 = S2 = M = OV
Parameter
tpLH
Input
Under
Test
Other Input
Same Bit
Apply
4.5V
Apply
GND
Apply
4.5V
Apply
GND
Ai
Bi
None
Remaining
AandB
Cn
Fi
In·Phase
Bi
AI
None
Remaining
AandB
Cn
Fj
In-Phase
Ai
Bi
None
None
Remaining
AandB,Cn
P
In-Phase
Bi
Ai
None
None
Remaining
A and B,Cn
P
In-Phase
Ai
None
Bi
Remaining
B
Remaining
A,Cn
G
In-Phase
Bi
None
Ai
Remaining
B
Remaining
A,C n
G
In-Phase
Cn
None
None
All
A
All
B
AnyF
orCn +4
In-Phase
Ai
None
Bj
Remaining
B
Remaining
A,en
Cn +4
Out-of-Phase
Bi
None
Ai
Remaining
B
Remaining
A,C n
Cn +4
Out-of-Phase
tpHL
tpLH
tpHL
tpLH
Other Data Inputs
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
•
3-87
....
....
en
GO
Parameter Measurement Information (Continued)
DIFF Mode Test Table
Function Inputs: S1 = S2 = 4.5V, SO = S3 = M = OV
Parameter
tpLH
Input
Under
Test
Other Input
Same Bit
Apply
Bi
Remaining
A
Remaining
B,Cn
Fi
In-Phase
AI
None
Remaining
A
Remaining
B,Cn
FI
Out-ot-Phase
AI
None
Bi
None
Remaining
AandB,Cn
P
In-Phase
Bi
Ai
None
None
Remaining
AandB,Cn
P
Out-ot-Phase
Ai
Bi
None
None
Remaining
A and B, Cn
G
In-Phase
Bi
None
Ai
None
Remaining
A and B,C n
G
Out-ot-Phase
Ai
None
Bj
Remaining
A
Remaining
B,Cn
A=B
In-Phase
Bi
Ai
None
Remaining
A
Remaining
B,Cn
A=B
Out-ot-Phase
Cn
None
None
All
AandB
None
Cn +4
or any F
In-Phase
AI
Bj
None
None
Remaining
A.B.Cn
Cn +4
Out-ot-Phase
Bj
None
Ai
None
Remaining
A,B,Cn
Cn +4
In-Phase
Ai
None
BI
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
Output
Waveform
Apply
GND
Apply
GND
Apply
Output
Under
Test
4.5V
4.5V
tpHL
tpLH
Other Data Inputs
tpHL
3-88
en
....
....
Logic Diagram
Q)
~
(3)
(4)
52
(5)
51
(6)
50
53
-~
B3
( 18)
A3
(19)
_too..
B2
( 20)
-v
W>-
~
~
- roI>
( 22)
p or X
rl
I
JL
~
C n+4
(16)
(15)
I
(21)
B1
~
I~ =n
~
G or Y
(17)
F
(13)
&
~~
(11)
F
....:
A=B
(14 )
1
(23)
L.-
BO
(1)
-"
-v
~
~
'1
AO
M
>u
~
.rJ
(10)
(9)
F1
FO
(2)
~
Vee = PIN 24
GND = PIN 12
Cn
(7)
TllF/6473-4
3·89
~NatiOnal
Semiconductor
DM54S 182/DM7 4S 182 Look-Ahead Carry Generators
General Description
These circuits are high-speed, look-ahead carry generators,
capable of anticipating a carry across four binary adders or
groups of adders. They are cascadable to perform full lookahead across n-bit adders. Carry, generate-carry, and propagate-carry functions are provided as shown in the pin designation table.
When used in conjunction with the 161 arithmetic logic unit,
these generators provide high-speed carry look-ahead capability for any word length. Each S162 generates the lookahead (antiCipated carry) across a group of four ALU's and,
in addition, other carry look-ahead circuits may be employed
to antiCipate carry across sections of four look-ahead packages up to n-bits. The method of cascading circuits to perform multi-level look-ahead is illustrated under typical application data.
Carry input and output of the ALU's are in their true form,
and the carry propagate (P) and carry generate (G) are in
negated form; therefore, the carry functions (inputs, outputs,
Connection Diagram
cn+x Cn+ y
cn
G2
15
116
,
, ,
P2
vcc
14
13
12
11
G
cn+z
10
1
G1
9
-
r<
\
Features
• Typical propagation delay time 7 ns
• Typical power dissipation 260 mW
Pin Designations
Dual-In-Llne Package
INPUTS
OUTPUTS
,
generate, and propagate) of the look-ahead generators are
implemented in the compatible forms for direct connection
to the ALU. Reinterpretations of carry functions, as explained on the 161 data sheet are also applicable to and
compatible with the look-ahead generator. Positive logiC
equations for the S162 are:
Cn+x=GO+POCn
Cn + y = G1 + P1 GO + P1 PO Cn
Cn + z = G2 + P2G1 + P2P1 GO + P2P1 POCn
G = G3 (P3 + G2)(P3 + P2 + G1)
(P3 + P2 + P1 + GO)
P = P3P2P1 PO
2
P1
3
GO
4
,
PO
5
G3
6
P3
I
7
18
P
GND
OUTPUT
INPUTS
TL/F/6474-1
Order Number DM54S182J or DM74S182N
See NS Package Number J16A or N16E
3-90
Designation
Pin Nos.
Function
GO, G1, G2, G3
3,1,14,5
Active Low
Carry Generate Inputs
PO,P1,P2,P3
4,2,15,6
Active Low
Carry Propagate Inputs
Cn
13
Carry Input
Cn+x,Cn + y,
Cn + z
12,11,9
Carry Outputs
G
10
Active Low
Carry Generate Output
P
7
Active Low
Carry Propagate Output
Vee
16
Supply Voltage
GND
6
Ground
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
DM54S
-55'Cto + 125'C
DM74S
O'Cto +70'C
Storage Temperature Range
-65'C to + 150'C
Recommended Operating Conditions
Symbol
DM54S182
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
DM74S182
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
2
V
V
VIL
Low Level Input Voltage
O.S
O.S
V
IOH
High Level Output Current
-1
-1
mA
20
mA
70
'C
IOL
Low Level Output Current
TA
Free Air Operating Temperature
20
-55
125
0
Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
Input Clamp Voltage
Vee
VOH
High Level Output
Voltage
Vcc = Min, IOH = Max
VIL = Max, VIH = Min
VOL
Low Level Output
Voltage
Vcc = Min, IOL = Max
VIH = Min, VIL = Max
II
Input Current @ Max
Input Voltage
Vcc
IIH
High Level Input
Current
Vcc = Max
VI = 2.7V
Low Level Input
Current
Typ
(Note 1)
DM54
2.5
3.4
DM74
2.7
3.4
= Min,ll = -1SmA
VI
IlL
Min
Conditions
= Max, VI = 5.5V
Vcc = Max
VI = 0.5V
ICCH
ICCL
Units
-1.2
V
V
0.5
V
1
mA
PO, P1 orG3
200
P3
100
P2
150
Cn
GO,G2
50
350
G1
400
PO, P1 orG3
-S
P3
-4
P2
-6
Cn
GO,G2
-2
mA
-16
Short Circuit
Output Current
Vcc = Max
(Note 2)
DM54
-40
-100
DM74
-40
-100
Supply Current with
Outputs High
Vcc = Max
(Note 3)
DM54
39
55
DM74
39
55
Supply Currents with
Outputs Low
Vcc = Max
(Note 4)
DM54
69
99
69
109
DM74
Note 1: All typicals are at Vee = 5V, TA = 25'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: ICCH is measured with all outputs open, inputs P3 and G3 at 4.5V, and all other inputs grounded.
Note 4: ICCL is measured with all outputs open, inputs GO, G 1, and G2 at 4.5V, and all other inputs grounded.
3-91
/Jo A
-14
G1
los
Max
mA
mA
mA
•
N
....co
rn
Switching Characteristics at Vee =
5V and T A = 25'C (See Section 1 for Test Waveforms and Output Load)
RL = 2800.
From (Input)
Symbol
Parameter
CL = 15pF
To (Output)
Min
Propagation Delay Time
Low to High Level Output
to Cn + x, v, Z
Propagation Delay Time
High to Low Level Output
to Cn + x, Y,Z
tpLH
Propagation Delay Time
Low to High Level Output
tpHL
tpLH
GNorPN
Max
CL = 50pF
Min
Units
Min
7
10
ns
7
11
ns
GNorPN
toG
7.5
11
ns
Propagation Delay Time
High to Low Level Output
GNorPN
toG
10.5
14
ns
tpLH
Propagation Delay Time
Low to High Level Output
PN
to P
6.5
10
ns
tpHL
Propagation Delay Time
High to Low Level Output
PN
toP
10
14
ns
tpLH
Propagation Delay Time
Low to High Level Output
to Cn + x, y, Z
10
13
ns
Propagation Delay Time
High to Low Level Output
to Cn + x, Y,Z
10.5
14
ns
tpHL
tpHL
GNorPN
Cnto
Cnto
3·92
r---------------------------------------------------------------------, ....
0
~
Logic Diagram
(7) P
P3
(6)
G3 __~-+~--~+_~~L_J
(5)
P2 (15)
G2--~~----_+_+~~_L__'
(14)
P1
G1
PO
GO
en
(2)
(1)
(4)
(3)
Vee = PIN 16
(13)
GND = PIN 8
TUF/6474-2
Typical Application
64·Bit ALU, Full·Carry Look Ahead in Three Levels
,.,
TUF/6474-3
A and B Inputs, and F outputs of 181 are nol shown.
3·93
.r---------------------------------------------------------~
....
G)
en ~National
~ Semiconductor
DM54S 194/DM7 4S 194
4-Bit Bidirectional Universal Shift Registers
Shift right is accomplished synchronously with the rising
edge of the clock pulse when SO is high and 51 is low.
Serial data for this mode is entered at the shift-right data
input. When SO is low and 51 is high, data shifts left synchronously and new data is entered at the shift-left serial
input.
General Description
These bidirectional shift registers are designed to incorporate virtually all of the features a system designer may want
in a shift register; they feature parallel inputs, parallel outputs, right-shift and left-shift serial inputs, operating-modecontrol inputs, and a direct overriding clear line. The register
has four distinct modes of operation, namely:
Clocking of the flip-flop is inhibited when both mode control
inputs are low.
Parallel (broadside) load
Shift right (in the direction QA toward QD)
Shift left (in the direction 00 toward OA)
Inhibit clock (do nothing)
Features
• Parallel inputs and outputs
• Four operating modes:
Synchronous parallel load
Right shift
Left shift
Do nothing
• Positive edge-triggered clocking
• Direct overriding clear
• Typical clock frequency 105 MHz
• Typical power dissipation 425 mW
Synchronous parallel loading is accomplished by applying
the four bits of data and taking both mode control inputs, SO
and 51, high. The data are loaded into the associated flipflops and appear at the outputs after the positive transition
of the clock input. During loading, serial data flow is inhibited.
Connection Diagram
Dual-In-Llne Package
OUTPUTS
VCC
116
'OA
Os
15
2
CLEAR SHIFT
RIGHT
SERIAL
INPUT
14
Oc
OD
13
12
CLOCK
11
3
4
5
a
c
D6
A
'-------:---'
PARALLEL INPUTS
S1
10
SHI:T
LEFT
SERIAL
INPUT
Order Number DM54S194J or DM74S194N
See NS Package Number J16A or N16E
3-94
so
9
G!:
TlIF/6475-1
Absolute Maximum Ratings (Note)
If MIlitary/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
DM54S
-55"C to + 125"C
DM74S
O"Cto +70"C
Storage Temperature Range
-65"Cto + 150"C
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Recommended Operating Conditions
Symbol
DM54S194
Parameter
DM74S194
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
Vcc
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
0.6
0.6
V
mA
2
V
V
2
10H
High Level Output Current
-1
-1
10L
Low Level Output Current
20
20
mA
fCLK
Clock Frequency (Note 1)
0
105
70
0
105
70
MHz
fCLK
Clock Frequency (Note 2)
0
90
60
0
90
60
MHz
tw
Pulse Width
(Note 3)
Setup Time
(Note 3)
tsu
Clock
7
7
Clear
12
12
Mode
11
11
Data
5
5
tH
Hold Time (Note 3)
3
3
tREL
Clear Release Time (Note 3)
9
9
TA
Note 1: CL
Note 2: CL
Note 3: TA
~
~
~
Free Air Operating Temperature
IS pF. RL ~ 2800, TA ~ 2S"C and Vec ~ SV.
SO pF, RL ~ 2800, TA ~ 2S"C and Vee ~ SV.
2S"C and Vee ~ SV.
-55
125
ns
ns
ns
ns
70
0
"C
Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
Min
Typ
(Note 4)
DM54
2.5
3.4
DM74
2.7
3.4
Conditions
VI
Input Clamp Voltage
VOH
High Level Output
Voltage
= Min, II = -16 mA
Vcc = Min, 10H = Max
VIL = Max, VIH = Min
VOL
Low Level Output
Voltage
Vcc = Min, 10L = Max
VIH = Min, VIL = Max
II
Input Current @ Max
Input Voltage
Vcc
IIH
High Level Input Current
Vcc
IlL
Low Level Input Current
los
Short Circuit
Output Current
Vcc
= Max, VI = 5.5V
= Max, VI = 2.7V
Vcc = Max, VI = 0.5V
Vcc = Max
(Note 5)
Max
Units
-1.2
V
V
0.5
V
1
mA
50
/LA
-2
mA
DM54
-40
-100
DM74
-40
-100
mA
Supply Current
65
135
Vcc = Max (Note 6)
mA
Icc
Note 4: All typicals are at Vee ~ SV, TA ~ 25"C.
Note 5: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 6: With all outputs open, inputs A through D grounded, and 4.SV applied to SO, 51, CLEAR, and the SERIAL inputs, IcC is tested with a momentary ground,
then 4.SV applied to CLOCK.
3-95
II
Switching Characteristics at Vee = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
Symbol
RL
From (Input)
To (Output)
Parameter
CL
= 280n
= 15pF
Min
CL
Max
= 50pF
70
Units
Max
Min
fMAX
Maximum Clock Frequency
tpLH
Propagation Delay Time
Low to High Level Output
Clock
toO
60
MHz
12
15
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clock
toO
16.5
20
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clear
toO
18.5
23
ns
Function Table
Inputs
Mode
Clear
L
H
H
H
H
H
H
H
Clock
S1
SO
X
X
X
X
Outputs
Serial
Parallel
Left
Right
A
B
C
D
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
t
t
t
t
t
QA
QB
Qc
L
aAO
a
H
L
aBn
aBn
aAO
L
aBO
b
aAn
aAn
aen
aen
aBO
L
aeo
c
aBn
aBn
aon
aon
aeo
H
H
b
c
d
a
L
X
X
X
X
H
H
L
H
X
X
X
L
X
L
X
X
H
H
X
X
X
H
L
L
X
X
X
X
X
X
X
X
X
X
X
L
L
X
H = High Level (steady state). L = Low Level (steady state). X = Don't Care (any input, Including transitions).
t = Transition from low to high level.
s, b, c, d = The level of steady state Input at Inputs A, e, C, or 0, respectively.
OAO, aBO, Oce, 000 = The level of OA, Os, Oc, or 00, respectively, before the indicated steady state input conditions were established.
OAn, OBn, OCn, OOn = The level of OA, Os, Oc respectively, before the most recent t transition of the clock.
QD
L
000
d
aen
aen
H
L
000
Logic Diagram
5194
PARALLEL INPUTS
•,31
MODE { Sf,fOI ..
....
~ "I~
••OFT
B
D
C
'41
,61
lSI
.........
-'"
,....
SHFT
lIGHT (2)
(7) LEFT
SERIAL
INPUT
"RIAL
INPUT
• a.
CLOC1< 'U!J-."
Cl.EAR(1) .....
,......
s
aa
• Ilc
CLQCft
R
CLQCft
CLOCK
CLEAR
CLEAR
CLEAR
•
1
•
1
(15)
1
aa
, QA
(141
(13)
Ilc
PARALLEL OUTPUTS
~
(12)
""
TL/F/6475-2
3·96
r---------------------------------------------------------------------~~
.....
CQ
Timing Diagram
,j:Io,
Typical Clear, Load, Right-Shift, Left-Shift, Inhibit, and Clear Sequences
CLOCK
MODE
CONTROL
INPUTS
Iso
Sl
I
CLEAR
SERIAL
DATA
INPUTS
R
L
PARALLEL{:
DATA
INPUTS C
L
o
~ -+-+_H~
H
OUTPUTS { :
QC _
H
QD :-+-+_-1
__-i---INHIBIT
CLEAR LOAD
CLEAR
TL/F/6475-3
3-97
...
~ .---------------------------------------------------------------------------~
~
en
~National
~ Semiconductor
DM54S195/DM74S195 4-Bit Parallel Access
Shift Registers
General Description
These 4-bit registers feature parallel inputs, parallel outputs,
J-K serial inputs, shiftlload control input, and a direct overriding clear. All inputs are buffered to lower the input drive
requirements. The registers have two modes of operation:
The high-performance S195, with a 105 MHz typical shift
frequency, is particularly attractive for very high-speed data
processing systems. In most cases existing systems can be
upgraded merely by using this Schottky-clamped shift register.
Parallel (broadside) load
Shift (in the direction QA toward Qo)
Features
Parallel loading is accomplished by applying the four bits of
data and taking the shiftlload control input low. The data is
loaded into the associated flip-flop and appears at the outputs after the positive transition of the clock input. During
loading, serial data flow is inhibited.
•
•
•
•
Synchronous parallel load
Positive-edge-triggered clocking
Parallel inputs and outputs from each flip-flop
Direct overriding clear
J and K inputs to first stage
Complementary outputs from last stage
For use in high-performance:
accumulators/processors
serial-to-parallel, parallel-to-serial converters
Typical clock frequency 105 MHz
Typical power dissipation 350 mW
•
Shifting is accomplished synchronously when the shiftlload
control input is high. Serial data for this mode is entered at
the J-K inputs. These inputs permit the first stage to perform
as a J-K, D, or T-type flip-flop as shown in the truth table.
•
•
•
•
Connection Diagram
Dual·ln·Llne Package
OUTPUTS
Os
Qc
14
Qo
13
SHIFT
CLOCK LOAD
aD
11
12
10
9
-
2
CLEAR
SERIAL INPUTS
5
4
3
J
B
A
7
6
C
o
18
GNO
PARALLEL INPUTS
TL/F/6476-1
Order Number DM54S195J or DM74S195N
See NS Package Number J16A or N16E
3-9B
(f)
.....
Absolute Maximum Ratings
(I)
(II
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
DM54S
- 55'C to + 125'C
DM74S
O'Cto +70'C
Storage Temperature Range
-65'C to + 150'C
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Recommended Operating Conditions
Symbol
DM54S195
Parameter
DM74S195
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
0.8
0.8
V
10H
High Level Output Current
-1
-1
mA
10L
Low Level Output Current
20
20
mA
feLK
Clock Frequency (Note 1)
feLK
Clock Frequency (Note 2)
tw
Pulse Width
(Note 3)
Clock
7
7
Clear
12
12
Setup Time
(Note 3)
Shift/Load
11
11
Data
5
5
tsu
2
0
105
70
0
90
60
0
105
70
MHz
0
90
60
MHz
tH
Data Hold Time (Note 3)
3
3
tREL
Shift/Load Release Time (Note 3)
6
6
Clear Release Time (Note 3)
9
9
-55
Free Air Operating Temperature
TA
Note 1: CL = 1S pF. RL = 280n. TA = 2S"C and Vcc = SV.
Note 2: CL = SO pF. RL = 280n, TA = 2S"C and Vee = SV.
Note 3: TA = 2S"C and Vee = SV.
V
2
125
ns
ns
ns
ns
0
70
'C
Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
Min
Typ
(Note 4)
DM54
2.5
3.4
DM74
2.7
3.4
Conditions
VI
Input Clamp Voltage
Vee = Min, 11= -18 mA
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
VIL = Max, VIH = Min
VOL
Low Level Output
Voltage
Vee = Min, 10L = Max
VIH = Min, VIL = Max
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 5.5V
I
I
Max
Units
-1.2
V
V
0.5
V
1
mA
IIH
High Level Input Current
Vee = Max, VI = 2.7V
50
/LA
IlL
Low Level Input Current
Vee = Max, VI = 0.5V
-2
mA
los
Short Circuit
Output Current
Vee = Max
(Note 5)
I
I
DM54
-40
-100
DM74
-40
-100
mA
Supply Current
mA
Vee = Max (Note 6)
70
109
Icc
Note 4: All typicals are at Vee = SV, TA = 2S"C.
Note 5: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 6: With all inputs open, SHIFTILOAD grounded, and 4.SV applied to the J, K, and data inputs, Icc is measured by applying a momentary ground, then 4.SV to
the CLEAR and then applying a momentary ground then 4.SV to the CLOCK.
3-99
•
Switching Characteristics at Vcc =
5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
RL = 2800
From (Input)
To (Output)
Parameter
Symbol
CL = 15pF
Min
CL = 50pF
Max
Min
Units
Max
fMAX
Maximum Clock
Frequency
tpLH
Propagation Delay Time
Low to High Level Output
Clock to
Any 0
12
15
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clock to
Any 0
16.5
20
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clear to
Any 0
18.5
23
ns
60
70
MHz
Function Table
Inputs
Clear
Shift!
Load
Outputs
Serial
Clock
Parallel
K
J
A
B
QA
C
QB
Qc
X
X
L
L
X
X
X
X
X
X
L
b
c
d
a
b
c
L
X
X
a
X
H
L
X
X
X
X
X
Oeo
OAO
OBO
X
H
L
H
X
X
X
OAO
OAO
OSn
H
L
L
X
X
X
X
L
OAn
OSn
X
X
H
H
H
X
X
H
OAn
OSn
H
H
L
X
X
X
X
OAn
OAn
OSn
i
H = High Level (steady state), L = Low Level (steady state), X = Don't Care (any Input, Including transitions)
t = Transition from low to high level
a, b, c, d = The level of steady state Input at A, B, C. or 0, respectively.
OAQ, aBO, Oco, ODD ~ The level of OA, OB, Oe, or aD, respectively, before the Indicated steady state input conditions were established.
QAn, OBn, Oen = The level of OA, OB, Oe, respectively, before the most recent transition of the clock.
L
H
H
H
H
H
H
QD
QD
L
d
H
000
000
OCn
OCn
OCn
OCn
Ocn
OCn
OCn
OCn
D
t
t
t
t
d
Logic Diagram
SERIAL
INPUT
~
K
J
SHIFT! LOAD (9)
CONTROL
(10)
CLOCK
CLEAR
(1)
(2)
(3)
.
PARALLEL INPUTS
A
(4)
,
C
S
(5)
D
(6)
(7)
t
~ ~
Bt
'----
R
~
~I>CLOCK
S
~
IV IV
'----
,,,Lol.
R
~I>CLOCK
(15)
?A
'---
S ~
'--
I
R
~I>CLDCK
(14)
as
CL~~R
'--CLOCK
R ODhl
S ~
'--
a
(13~~t1111
(12)OD~D
PARALLEL OUTPUTS
TL/F/6476-2
3·100
.------------------------------------------------------------------.0
.....
Timing Diagram
CD
U1
Typical Clear, Shift, and Load Sequences
CLOCK
CLEAR
SERIAL
INPUTS
{J
K::::t:::::~__~~::::::::::::::::::::::~--~:t:::::::::::::::::::::
SHIFT/ LOAD
PARALLEL(:
DATA
INPUTS C __.....,~-------+------___________________I
D __.....,~-------+--------------------------L_+----4_---------------------
OUTPUTsl:~~:
QC __
~,--------+_--------~
QD:=~--------+_---------------'
I
CLEAR
LOAD
TL/F/6476-3
•
3-101
~National
....• ~ Semiconductor
~
tn
• DM54S240/DM74S240, DM54S241/DM7 4S241,
C)
'Oil'
N
tn
DM54S244/DM74S244 Octal TRI-STATE®
Buffers/Line Drivers/Line Receivers
General Description
These buffers/line drivers are designed to improve both the
performance and PC board density of TRI-8TATE buffers/
drivers employed as memory-address drivers, clock drivers,
and bus-oriented transmitters/receivers. Featuring 400 mV
of hysteresis at each low current PNP data line input, they
provide improved noise rejection and high fanout outputs,
and can be used to drive terminated lines down to 133(1..
Features
• TRI-8TATE outputs drive bus lines directly
• PNP inputs reduce DC loading on bus lines
• Hysteresis at data inputs improves noise margins
• Typical IOL (sink current)
548 48 mA
748 64 mA
• Typical IOH (source current)
548 -12 mA
748 -15 mA
• Typical propagation delay times
Inverting 4.5 ns
Noninverting 6 ns
• Typical enable/disable times 9 ns
• Typical power disSipation (enabled)
Inverting 450 mW
Noninverting 538 mW
Connection Diagrams
Dual-in-Line Package
Dual-in-Line Package
Vee
20
lVl
2M
Iva 2A3
IV3
2A2 IV4 2Al
lG
lAl
2V4
lA2
2Y3 lA3
2n
1M 2Yl GND
Vee
20
lYl
2A4
lY2 2A3
lY3
2A2
1Y4 2A 1
lG
lA 1
2Y4
lA2
2Y3
2Y2
lA4
2Yl GND
lA3
TL/F/6478-1
TLlF/6478-2
Order Number DM54S240J,
DM74S240WM or DM74S240N
See NS Package Number
J20A, M20B or N20A
Order Number DM54S241J
or DM74S241 N
See NS Package Number
J20AorN20A
Dual-in-Line Package
Vee
zG
10
1A1
1Y4 2A 1
2Y4
1A2
2V3
1A3
2V2
1A4 2Y1 GND
TL/F/6478-3
Order Number DM54S244J,
DM74S244WM or DM74S244N
See NS Package Number
J20A, M20B or N20A
3-102
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
DM54S
- 55·C to + 125·C
O·Cto +70·C
DM74S
Storage Temperature Range
- 65·C to + 150·C
Recommended Operating Conditions
Symbol
DM54S
Parameter
DM74S
Units
Min
Typ
Max
Min
Typ
Max
4.5
5
5.5
4.75
5
5.5
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
0.8
0.8
V
IOH
High Level Output Current
-12
-15
mA
64
mA
70
·C
2
IOL
Low Level Output Current
TA
Free Air Operating Temperature
V
2
V
48
-55
125
0
Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
VI
Input Clamp Voltage
Vee = Min,ll = -18 mA
Hys
Hysteresis (VT + - VT -)
(Data Inputs Only)
Vee = Min
VOH
High Level Output Voltage
Vee = 4.75V, VIH = 2V
VIL = 0.8V,IOH = -1 mA
Min
0.2
I
DM74
Vee = Min, VIH = 2V
VIL = 0.8V, IOH = -3 mA
VOL
Low Level Output Voltage
IOZH
Off-State Output Current,
High Level Voltage Applied
IOZL
Off-State Output Current,
Low Level Voltage Applied
II
Input Current at Maximum
Input Voltage
IIH
IlL
Vee = Min
IOL = Max
VIL = 0.8V, VIH = 2V
Vee = Max
VIL = 0.8V
VIH = 2V
I DM54
I DM74
Vo = 0.5V
VI = 5.5V
High Level Input Current
Vee = Max
VI = 2.7V
Low Level Input Current
Vee = Max
VI = 0.5V
I AnyA
I AnyG
3-103
Units
-1.2
V
0.4
V
3.4
V
2
Vo = 2.4V
Vee = Max
Max
2.7
2.4
Vee = Min, VIH = 2V
VIL = 0.5V,IOH = Max
Typ
(Note 1)
0.55
V
0.55
50
/LA
-50
/LA
1
mA
50
/LA
-400
/LA
-2
mA
•
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (Continued)
Symbol
Parameter
Conditions
los
Short Circuit Output Current
Vee = Max (Note 2)
Icc
Supply
Current
Outputs
High
Typ
(Note 1)
Min
-50
Outputs
Low
Outputs
Disabled
Max
Units
-225
mA
DM54S240
80
DM74S240
80
135
DM54S241, 244
95
147
DM74S241,244
95
160
DM54S240
100
145
DM74S240
100
150
DM54S241, 244
120
170
DM74S241, 244
120
180
DM54S240
100
145
123
DM74S240
100
150
DM54S241, 244
120
170
DM74S241, 244
120
180
mA
Note 1: All typical values are at Vee = SV, TA = 2S'C.
Nota 2: Not mOle than one output should be shorted at a time and duration should not exceed one second.
Switching Characteristics Vee =
Symbol
tpLH
tpHL
tpZL
tpZH
tpLZ
tpHZ
tpLH
tpHL
tPZL
tPZH
5V, TA = 25°C (See Section 1 for Test Waveforms and Output Load)
Min
Max
Propagation Delay Time
Low to High Level Output
Parameter
CL=45pF
RL = 900
Conditions
DM54/74S240
2
7
DM54/74S241 , 244
2
9
Propagation Delay Time
High to Low Level Output
CL = 45pF
RL = 900
DM54174S240
2
7
DM54174S241, 244
2
9
Output Enable Time to
Low Level
CL = 45pF
RL = 900
DM54174S240
3
15
DM54174S241,244
3
15
Output Enable Time to
High Level
CL = 45pF
RL = 900
DM54174S240
2
10
DM54/74S241,244
3
12
Output Disable Time
from Low Level
CL = 5pF
RL = 900
DM54/74S240
4
15
DM54174S241,244
2
15
Output Disable Time
from High Level
CL = 5pF
RL = 900
DM54174S240
2
9
DM54174S241, 244
2
9
Propagation Delay Time
Low to High Level Output
CL = 150pF
RL = 900
DM54174S240
3
10
DM54174S241 , 244
4
12
Propagation Delay Time
High to Low Level Output
CL = 150pF
RL = 900
DM54174S240
3
10
DM54/74S241,244
4
12
Output Enable Time to
Low Level
CL = 150pF
RL = 900
Output Enable Time to
High Level
CL=150pF
RL = 900
3-104
DM54/74S240
6
21
DM54174S241 , 244
6
21
DM54174S240
4
12
DM54174S241,244
4
15
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
,---------------------------------------------------------------------, 0
N
UI
....
~National
~ Semiconductor
DM54S251/DM74S251 TRI-STATE® 1 of 8 Line
Data Selector/Multiplexer
General Description
Features
These data selectors/multiplexers contain full on-chip binary decoding to select one-of-eight data sources, and feature
a strobe-controlled TRI-STATE output. The strobe must be
at a low logic level to enable these devices. The TRI-STATE
outputs permit direct connection to a common bus. When
the strobe input is high, both outputs are in a high-impedance state in which both the upper and lower transistors of
each totem pole output are off, and the output neither drives
nor loads the bus significantly. When the strobe is low, the
outputs are activated and operate as standard TTL totempole outputs.
•
•
•
•
•
•
TRI-STATE version of S151
Interface directly with system bus
Perform parallel-to-serial conversion
Permit multiplexing from N-lines to one line
Complementary outputs provide true and inverted data
Max no. of common outputs
54S 39
74S 129
• Typical propagation delay time (0 to Y) 8 ns
• Typical power dissipation 275 mW
To minimize the possibility that two outputs will attempt to
take a common bus to opposite logic levels, the output control circuitry is designed so that the average output disable
time is shorter than the average output enable time.
Connection Diagram
Function Table
DATA SELECT
DATA !NPUTS
'04
15
D5
14
D6
13
D7'
A
12
11
~
Inputs
C'
10
Select
9
c
B
A
S
X
x
L
X
L
H
L
L
L
L
L
H
H
H
H
H
2
, 03
D2
3
D1
DATA INPUTS
Outputs
Strobe
H
L
H
H
L
L
L
H
H
L
H
H
L
L
L
L
L
L
L
L
y
W
z
Z
DO
01
00
01
02
03
04
05
02
03
04
05
06
06
07
07
4
H = High logic level, l = low logic level
DO.
X = Don't Care, Z = High Impedance (Off)
OUTPUTS
DO, 01 ..• 07 = The level of the respective 0 input
TL/F/64BO-l
Order Number DM54S251J or DM74S251N
See NS Package Number J16A or N16E
3-105
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
7V
Supply Voltage
Input Voltage
5.5V
Operating Free Air Temperature Range
DM54S
- 55'C to + 125'C
DM74S
O'Cto +70'C
Storage Temperature Range
-65'Cto + 150'C
Recommended Operating Conditions
Symbol
DM54S251
Parameter
DM74S251
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
Vee
Supply Voltage
VIH
High Level Input Voltage
Vil
Low Level Input Voltage
0.8
0.8
V
2
2
V
10H
High Level Output Current
-2
-6.5
rnA
10l
Low Level Output Current
20
20
rnA
TA
Free Air Operating Temperature
70
·c
-55
125
0
Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
VI
Input Clamp Voltage
VOH
High Level Output
Voltage
Conditions
= Min,ll = -18 rnA
Vee = Min, IOH = Max
Vil = Max, VIH = Min
Low Level Output Voltage
Vee = Min, 10l = Max
VIH = Min, Vil = Max
II
Input Current @ Max
Input Voltage
Vee
IIH
High Level Input
Vee
Low Level Input Current
10ZH
Off-State Output Current
with High Level
Output Voltage Applied
10Zl
los
lee
Typ
(Note 1)
Vee
Val
III
Min
=
Max, VI
=
I
I
DM54
2.4
3.4
DM74
2.4
3.2
5.5V
= Max, VI = 2.7V
Vee = Max, VI = 0.5V
Vee = Max, Va = 2.4
VIH = Min, Vil = Max
Off-State Output Current
with Low Level
Output Voltage Applied
Vee = Max, Va = 0.5
VIH = Min, Vil = Max
Short Circuit
Output Current
Vee = Max
(Note 2)
Supply Current
Vee
=
-1.2
V
V
0.5
V
1
rnA
50
p.A
-2
rnA
50
p.A
-50
p.A
I
DM54
-40
-100
L
DM74
-40
-100
typical. are at Vee = SV, TA = 2S'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: Icc Is measured with the outputs open and allinpuls at 4.SV.
3-106
Units
/
Max (Note 3)
Note 1: All
Max
55
85
rnA
rnA
en
Switching Characteristics at Vcc =
5V and T A = 25'C (See Section 1 for Test Waveforms and Output Load)
RL = 2800
From (Input)
Symbol
Parameter
To (Output)
CL = 15pF
Min
Max
CL = 50pF
Min
Units
Max
tpLH
Propagation Delay Time
Low to High Level Output
A,B,orC
(4 Levels) to Y
18
21
ns
tpHL
Propagation Delay Time
High to Low Level Output
A,B,orC
(4 Levels) to Y
19.5
23
ns
tpLH
Propagation Delay Time
Low to High Level Output
A, B,orC
(3 Levels) to W
15
18
ns
tpHL
Propagation Delay Time
High to Low Level Output
A, B,orC
(3 Levels) to W
13.5
17
ns
tpLH
Propagation Delay Time
Low to High Level Output
DtoY
12
15
ns
tpHL
Propagation Delay Time
High to Low Level Output
DtoY
12
15
ns
tpLH
Propagation Delay Time
Low to High Level Output
DtoW
7
10
ns
tpHL
Propagation Delay Time
High to Low Level Output
DtoW
7
10
ns
tpZH
Output Enable Time
to High Level Output
Strobe
toY
19.5
ns
tPZL
Output Enable Time
to Low Level Output
Strobe
toY
21
ns
tpHZ
Output Disable Time
to High Level Output (Note 1)
Strobe
toY
8.5
ns
tpLZ
Output Disable Time
to Low Level Output (Note 1)
Strobe
toY
14
ns
tPZH
Output Enable Time
to High Level Output
Strobe
toW
19.5
ns
tPZL
Output Enable Time
to Low Level Output
Strobe
toW
21
ns
tpHZ
Output Disable Time
to High Level Output (Note 1)
Strobe
toW
8.5
ns
tpLZ
Output Disable Time
to Low Level Output (Note 1)
Strobe
toW
14
ns
Nale 1: CL = 5 pF.
3-107
N
UI
....
,..
r-------------------------------------------------------------------------------~
~ Logic Diagram
STROBE (7)
(ENABLE) ~q::--------------r_--------_,
OO~(4~)----------r==r~~~:)
01 (3)
02~(2~)_________l~~~Et~
DATA
INPUTS
03~(1~)_________t~~~E}~
~~3~K>-<~~~
D4 (15)
05 (14)
06 (13)
07 (12)
A
ii
B
c
TLIF/6480-2
3-108
~National
~ Semiconductor
DM54S253/DM74S253
Dual TRI-STATE® 1 of 4 Line Data Selectors/Multiplexers
General Description
Features
Each of these Schottky-clamped data selectors/multiplexers contains inverters and drivers to supply fully complementary, on-chip, binary decoding data selection to the
AND-OR gates. Separate output control inputs are provided
for each of the two four-line sections.
•
•
•
•
•
•
•
The TRI-STATE outputs can interface directly with data
lines of bus-organized systems. With all but one of the common outputs disabled (at a high impedance state), the low
impedance of the single enable output will drive the bus line
to a high or low logiC level.
Connection Diagram
TRI-STATE version of S153 with same pin-out
Schottky-diode-clamped transistors
Permits multiplexing from N lines to 1 line
Performs parallel-T-serial conversion
Strobe/output control
High fan-out totem-pole outputs
Typical propagation delay
From data to output 6 ns
From select to output 12 ns
• Typical power dissipation 275 mW
Function Table
Select
Inputs
Dual-In-Line Package
DATA INPUTS
Data Inputs
Output
Control
Output
B
A
CO
C1
C2
C3
G
y
X
X
X
L
H
X
X
X
X
X
X
X
Z
L
L
X
X
X
X
X
H
L
L
L
L
X
X
X
X
X
H
H
H
H
H
H
H
L
L
H
H
H
X
X
X
X
X
X
L
H
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
H
L
H
L
H
L
H
Address inputs A and B are common to both sections.
H
1
OUTPUT
CONTROL
Gl
DATA INPUTS
TLiF16481-1
Order Number DM54S253J, DM54S253W or DM74S253N
NS Package Number J16A, N16E or W16A
3-109
~
High Level, L
~
Low Level. X = Don't Care. Z = High Impedance
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
5.5V
Input Voltage
Operating Free Air Temperature Range
DM54S
-55'Cto + 125'C
DM74S
O'Cto +70'C
Storage Temperature Range
-65'Cto + 150'C
Recommended Operating Conditions
Symbol
DM54S253
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
DM74S253
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
2
V
V
VIL
Low Level Input Voltage
0.8
0.8
V
10H
High Level Output Current
-2
-6.5
mA
20
mA
70
'C
10l
Low Level Output Current
TA
Free Air Operating Temperature
20
-55
125
0
Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
=
=
VI
Input Clamp Voltage
Vee
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
Vil = Max, VIH = Min
VOL
Low Level Output
Voltage
Vee = Min, 10l = Max
VIH = Min, Vil = Max
II
Input Current @ Max
Input Voltage
Vee
=
Max, VI
=
5.5V
IIH
High Level Input
Current
Vee
=
Max, VI
=
2.7V
III
Low Level Input
Current
Vee
=
Max, VI
=
0.5V
10ZH
Off-State Output Current with
High Level Output
Voltage Applied
Vee = Max, Vo = 2.4V
VIH = Min, Vil = Max
10Zl
Off-State Output Current with
Low Level Output
Voltage Applied
Vee = Max, Vo = 0.5V
VIH = Min, Vil = Max
los
Short Circuit
Output Current
Vee = Max
(Note 2)
Supply Current
Vee
lee
Min
Typ
(Note 1)
DM54
2.4
3.4
DM74
2.4
3.2
Conditions
=
Min,ll
-18 mA
-1.2
V
V
0.5
V
1
mA
50
poA
-2
mA
50
poA
-50
p.A
DM54
-40
-100
-40
-100
Max (Note 3)
3-110
Units
DM74
Nota 1: All typlcals are at Vee ~ 5V, TA ~ 25"C.
Note 2.: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: lee is measured with all outputs open.
Max
55
70
mA
mA
Switching Characteristics at Vee =
5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
RL = 280n
From (Input)
Symbol
Parameter
CL = 50pF
CL = 15pF
To (Output)
Min
Max
Min
Units
Max
tpLH
Propagation Delay Time
Low to High Level Output
Data
toY
9
12
ns
tpHL
Propagation Delay Time
High to Low Level Output
Data
toY
9
12
ns
tpLH
Propagation Delay Time
Low to High Level Output
Select
toY
18
21
ns
tpHL
Propagation Delay Time
High to Low Level Output
Select
toY
18
21
ns
tPZH
Output Enable Time
to High Level Output
Output Control
toY
16.5
19.5
ns
tpZL
Output Enable Time
to Low Level Output
Output Control
toY
18
21
ns
tpHZ
Output Disable Time to
High Level Output (Note 1)
Output Control
toY
9.5
ns
tpLZ
Output Disable Time
to Low Level Output (Note 1)
Output Control
toY
15
ns
Note I: CL
~
5 pF.
Logic Diagram
OUTPUT (I)
CONTROL GI (6)
-~
r
(5)
(7)
ICI
DATA 1
(4)
H
lC2
L....t--
H
lC3(3)
~I
B~
(14)
A
(10)
2CO
(II)
2CI
DATA 2
OUTPUT VI
(12)
2C2
Ii>~
~
:-t
(13)
2C3
OUTPUT (15)
CONTROLG2
OUTPUT V2
'--
3-111
TLlF/6481-2
~National
~ Semiconductor
DM54S257/DM7 4S257, DM54S258/DM74S258
TRI-STATE® Quad 1 of 2 Data Selectors/Multiplexers
General Description
Features
These Schottky-clamped high-performance multiplexers
feature TRI-STATE outputs that can interface directly with
data lines of bus-organized systems. With all but one of the
common outputs disabled (at a high impedance state), the
low impedance of the single enabled output will drive the
bus line to a high or low logic level. To minimize the possibility that two outputs will attempt to take a common bus to
opposite logic levels, the output enable circuitry is designed
such that the output disable times are shorter than the output enable times.
This TRI-STATE output feature means that n-bit (paralleled)
data selectors with up to 258 sources can be implemented
for data buses. It also permits the use of standard TTL registers for data retention throughout the system.
• TRI-STATE versions S157, S158, with same pin-outs
• Schottky-clamped for significant improvement in A-C
performance
• Provides bus interface from multiple sources in highperformance systems
• Average propagation delay from data input
S257 4.8 ns
S2584 ns
• Typical power dissipation
5257320 mW
S258 280 mW
Connection Diagrams
Dual-In-Llne Package
Dual-In-Line Package
INPUTS
A3
11
2
SELECT
A1
3
B3
INPUTS
OUTPUT
B4
VCC CONTROL A4
OUTPUT
V3
10
9
l16
15
4
V1
~--~' OUTPUT
INPUTS
A1
13
14
2
SELECT
B1
OUTPUT
V4
3
12
4
B1
Y1
~
OUTPUT
,
INPUTS
11
5
A2
6
B2
~
TL/F/6462-1
Function Table
Inputs
H
L
L
L
L
10
9
.18
7
Y2
GND
OUTPUT
TLlF/6482-2
Order Number DM54S257J, DM54S258J, DM54S257W, DM74S257N or DM74S258N
See NS Package Number J16A, N16E or W16A
Output
Control
OUTPUT
V3
B3
A3
OutputY
Select
A
B
S257
S258
X
L
L
X
L
Z
H
H
X
X
X
X
X
L
L
Z
H
L
H
H
L
H
H
= High Level. L = Low Level, X = Don't Care
Z = High Impedance (off)
H
3-112
L
H
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
DM54S
- 55'C to + 125'C
DM74S
O'Cto +70'C
Storage Temperature Range
- 65'C to + 150'C
Recommended Operating Conditions
Symbol
DM54S257
Parameter
DM74S257
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
0.8
0.8
V
10H
High Level Output Current
-2
-6.5
mA
10L
Low Level Output Current
20
20
mA
TA
Free Air Operating Temperature
70
·C
2
2
-55
125
V
0
'8257 Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)
Parameter
Symbol
Min
Typ
(Note 1)
DM54
2.4
3.4
DM74
2.4
3.2
Conditions
=
=
Max
Units
-1.2
V
VI
Input Clamp Voltage
Vee
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
VIL = Max, VIH = Min
VOL
Low Level Output
Voltage
Vee = Min, 10L = Max
VIH = Min, VIL = Max
II
Input Current @ Max
Input Voltage
Vee
IIH
High Level Input
Current
Vee = Max
VI = 2.7V
Select
100
Other
50
Low Level Input
Current
Vee = Max,
VI = 0.5V
Select
-4
Other
-2
Off-State Output Current
with High Level Output
Voltage Applied
Vee = Max, Va = 2.4V
VIH = Min, VIL = Max
50
p.A
Off-State Output Current with
Low Level Output
Voltage Applied
Vee = Max, Va = 0.5V
VIH = Min, VIL = Max
-50
p.A
Short Circuit
Output Current
Vee = Max
(Note 2)
leeH
Supply Current with Outputs High
Vee
leeL
Supply Current with Outputs Low
Vee
leez
Supply Current with Outputs Disabled
Vee
IlL
10ZH
10ZL
los
Nole I: All typlcals are at Vee
=
=
=
=
Min, II
Max, VI
-18 mA
=
5.5V
V
0.5
V
1
mA
DM54
-40
-100
DM74
-40
-100
p.A
mA
mA
Max (Note 3)
44
68
mA
Max (Note 3)
60
93
mA
Max (Note 3)
64
99
mA
SV, TA ~ 2S·C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: lee is measured with all outputs open and all possible inputs grounded, while achieving the stated output conditions.
~
3-113
'S257 Switching Characteristics
at Vee = 5V and T A = 25'C (See Section 1 for Test Waveforms and Output Load)
Symbol
RL = 2800
From (Input)
To (Output)
Parameter
CL = 15pF
Min
CL = 50pF
Max
Min
Units
Max
tpLH
Propagation Delay Time
Low to High Level Output
Data to
Output
7.5
11
ns
tpHL
Propagation Delay Time
High to Low Level Output
Data to
Output
6.5
10
ns
tpLH
Propagation Delay Time
Low to High Level Output
Select to
Output
15
16
ns
tpHL
Propagation Delay Time
High to Low Level Output
Select to
Output
15
16
ns
tpZH
Output Enable Time
to High Level Output
Output
ControltoY
19.5
23
ns
tPZL
Output Enable Time
to Low Level Output
Output
Control toY
21
24
ns
tpHZ
Output Disable Time
to High Level Output (Note 1)
Output
Control toY
8.5
ns
tpLZ
Output Disable Time
to Low Level Output (Note 1)
Output
Control toY
14
ns
Note 1: CL
= 5 pF.
Recommended Operating Conditions
Symbol
DM54S258
Parameter
DM74S258
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
Vec
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
0.8
0.8
V
IOH
High Level Output Current
-2
-6.5
mA
20
mA
70
'C
2
IOL
Low Level Output Current
TA
Free Air Operating Temperature
2
V
20
-55
125
V
0
'S258 Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
Min
Typ
(Note 1)
DM54
2.4
3.4
DM74
2.4
3.2
Conditions
Max
Units
-1.2
V
VI
Input Clamp Voltage
Vee = Min,ll = -18 mA
VOH
High Level Output
Voltage
Vee = Min, IOH = Max
VIL = Max, VIH = Min
VOL
Low Level Output
Voltage
Vee = Min, IOL = Max
VIH = Min, VIL = Max
II
Input Current @ Max
Input Voltage
Vee
IIH
High Level Input
Current
Vee = Max,
VI = 2.7V
Select
100
Other
50
Low Level Input
Current
Vee = Max,
VI = 0.5V
Select
-4
Other
-2
IlL
= Max, VI = 5.5V
3-114
V
0.5
V
1
mA
/LA
mA
en
N
'S258 Electrical Characteristics
U1
......
•
en
N
over recommended operating free air temperature (unless otherwise noted) (Continued)
Symbol
Parameter
Conditions
Min
Typ
(Note 1)
Max
Units
Off-State Output Current
with High Level Output
Voltage Applied
Vcc = Max, Vo = 2.4V
VIH = Min, VIL = Max
50
/LA
Off-State Output Current with
Low Level Output
Voltage Applied
Vcc = Max, Vo = 0.5V
VIH = Min, VIL = Max
-50
/LA
Short Circuit
Output Current
Vcc = Max
(Note 2)
ICCH
Supply Current with
Outputs High
Vcc = Max
(NoteS)
S6
56
mA
ICCl
Supply Current with
Outputs Low
Vcc = Max
(NoteS)
52
81
mA
87
mA
10ZH
10Zl
los
I
I
DM54
-40
-100
DM74
-40
-100
Supply Current with
Vcc = Max
56
Outputs Disabled
(NoteS)
Note 1: All typicals are at Vec = SV, TA = 2S·C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: Icc is measured with all outputs open and all possible inputs grounded, while achieving the stated output conditions.
leez
U1
CD
mA
'S258 Switching Characteristics
at Vcc = 5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
From (Input)
To (Output)
Rl = 2800.
CL = 15pF
Min
Max
CL = 50pF
Min
Units
Max
tplH
Propagation Delay Time
Low to High Level Output
Data to
Output
6
9
ns
tpHl
Propagation Delay Time
High to Low Level Output
Data to
Output
6
9
ns
tplH
Propagation Delay Time
Low to High Level Output
Select to
Output
12
15
ns
tpHl
Propagation Delay Time
High to Low Level Output
Select to
Output
12
15
ns
tpZH
Output Enable Time
to High Level Output
Output
Control toY
19.5
2S
ns
tPZl
Output Enable Time
to Low Level Output
Output
ControltoY
21
24
ns
tpHZ
Output Disable Time
to High Level Output (Note 1)
Output
ControltoY
8.5
ns
Output Disable Time
to Low Level Output (Note 1)
Note 1: CL = SpF.
Output
Control to Y
14
ns
tpLZ
S-115
•
Logic Diagrams
S257
OUTPUT(15)
CONTROL((22~)~____________~r-~
A1
:...
B1
(~3)~--+----""fl
A2 (~5)~_ _+-_--t-r~
~(6:!..)---~I------t-r
B2
(11)
A3
B3
A4
(10)
(14)
TL/F/6482-3
S258
OUTPUT (15)
CONTROLA1':;
((:2~)'::"------"f"1
-----+--------r
B1£(3~)
A2(5)
B2~(6~)____~____~;_
-+____t-r-,
Bd·~10~)_ _
(14)
A4
(11~3~)____~____
B4-
_irr
TLIF/6482-4
3-116
~National
~ Semiconductor
DM54S280/DM74S280 9-Bit Parity Generators/Checkers
General Description
These universal, nine-bit parity generators/checkers utilize
Schottky-clamped TTL high-performance circuitry, and feature odd/even outputs to facilitate operation of either odd or
even parity applications. The word-length capability Is easily
expanded by cascading.
Input buffers are provided so that each input represents
only one normal 74S load, and full fan-out to 10 normal
Series 74S loads is available from each of the outputs at
low logic levels. A fan-out to 20 normal Series 74S loads is
provided at high logic levels, to facilitate connection of unused inputs to used inputs.
The S280 can be used to upgrade the performance of most
systems utilizing the DM74180 parity generator/checker. Although the S280 is implemented without expander inputs,
the corresponding function is provided by the availability of
all input at pin 4, and no internal connection at pin 3. This
permits the S280 to be substituted for the 180 in existing
designs to produce an identical function, even if S280's are
mixed with existing 180's.
Features
• Generates either odd or even parity for nine data lines
• Cascadable for N-bits
• Can be used to upgrade existing systems using MSI
parity circuits
• Typical data-to-output delay-14 ns
Connection Diagram
Dual-In-Line Package
INPUTS
Vcc
F
T14
113
E
D
112
C
111
10
B
A
9
8
I
4
G
5
6
I
l:
INPUT
EVEN
l:
ODD
H
INPUTS
OUTPUTS
TLIFI6483-1
Order Number DM54S280J, DM54S280W, DM74S280M or DM74S280N
See NS Package Number J14A, M14A, N14A or W14B
Function Table
Number of Inputs (A
Outputs
Thru I) that are High ~ Even ~ Odd
0,2,4,6,8
1,3,5,7,9
3-117
H
L
L
H
•
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Input Voltage
5.5V
Operating Free Air Temperature Range
DM54S
- 55'C to + 125'C
DM74S
O'Cto +70'C
Storage Temperature Range
- 65'C to + 150'C
Recommended Operating Conditions
Symbol
DM54S280
Parameter
DM74S280
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
0.8
0.8
V
10H
High Level Output Current
-1
-1
mA
10L
Low Level Output Current
20
20
mA
TA
Free Air Operating Temperature
70
'C
V
2
2
-55
125
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
VI
Input Clamp Voltage
Vee = Min. 11= -18 mA
VOH
High Level Output
Voltage
Vee = Min. 10H = Max
VIL = Max. VIH = Min
VOL
Low Level Output
Voltage
Vee = Min, 10L = Max
VIH = Min, VIL = Max
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 5.5V
2.7
Typ
(Note 1)
Max
Units
-1.2
V
3.4
V
0.5
V
1
mA
IIH
High Level Input Current
Vee = Max, VI = 2.7V
50
IJ.A
IlL
Low Level Input Current
Vee = Max, VI = 0.5V
-2
mA
los
Short Circuit
Output Current
Vee = Max
(Note 2)
Supply Current
Vee Max (Note 3)
Icc
I
I
DM54
-40
-100
DM74
-40
-100
Note 1: All typicals are at Vee = 5V, TA = 25'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not excead one second.
Note 3: Icc is measured wHh all inputs grounded and all outputs opan.
3-118
67
105
mA
mA
Switching Characteristics at Vee
Symbol
Parameter
= 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
From (Input)
To (Output)
RL = 280(1
CL = 15pF
Min
Propagation Delay Time
Low to High Level Output
l: Even
Propagation Delay Time
High to Low Level Output
l: Even
tpLH
Propagation Delay Time
Low to High Level Output
tpHL
Propagation Delay Time
High to Low Level Output
tpLH
tpHL
Data to
Max
RL = 280(1
CL = 50pF
Min
Units
Max
21
24
ns
18
21
ns
Data to
l: Odd
21
24
ns
Data to
l: Odd
18
21
ns
Data to
Logic Diagram
TL/F/6463-2
•
3-119
B Typical Applications
Three S280's can be used to Implement a 25-line parity
generator/checker. This arrangement will provide parity in
typically 25 ns. (See Figure 1.)
As an alternative, the outputs of two or three parity generators/checkers can be decoded with a 2-input (S86) or
A
B
C
D
E
3-input (S135) exclusive-OR gate for 18 or 27-line parity applications.
Longer word lengths can be implemented by cascading
S280's. As shown in Figure 2, parity can be generated for
word lengths up to 81 bits in typically 25 ns.
A
B
I
C
EVEN
D
E
5280
F
I
EVEN
5280
F
G
G
H
H
I
I
H
~
A
B
EVEN
H
L
~
~
A
B
C
D
I
C
L~OOO
EVEN
D
E 5280
F
G
ODD
EVEN
E
H
F
G
I
H
I
EVEN
H
~
L~
EVEN
ODD
5280
I
ODD
H ~ EVEN
L ~OOO
I
A
B
C
0
E
F
G
H
TLiF16483-3
I
EVEN
5280
TO OTHER
5280'5
TL/F/6483-4
FIGURE 1. 2S-Llne Parity/Generator Checker
FIGURE 2. 81-Llne Parity/Generator Checker
3-120
CJ)
N
ClO
W
~National
~ Semiconductor
DM54S283/DM74S283 4-Bit Binary Adders
with Fast Carry
General Description
Features
These full adders perform the addition of two 4-bit binary
numbers. The sum (l:) outputs are provided for each bit and
the resultant carry (C4) is obtained from the fourth bit.
These adders feature full internal look ahead across all four
bits. This provides the system designer with partial lookahead performance at the economy and reduced package
count of a ripple-carry implementation.
• Full-carry look-ahead across the four bits
• Systems achieve partial look-ahead performance with
the economy of ripple carry
• Typical add times
Two B-bit words 15 ns
Two 16-bit words 30 ns
• Typical power dissipation 510 mW
The adder logic, including the carry, is implemented in its
true form meaning that the end-around carry can be accomplished without the need for logic or level inversion.
Connection Diagram
Dual-In-Line Package
B3
A3
15
l:3
14
A4
13
C4
l:4
B4
12
11
10
-
-
2
U
9
B2
3
A2
4
l:1
5
A1
6
B1
7
CO
Order Number DM54S283J or DM74S283N
See NS Package Number J16A or N16E
3-121
18
GND
TL/F/6484-1
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaran·
teed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
DM54S
-55'C to + 125'C
DM74S
O'Cto +70'C
Storage Temperature Range
-65'Cto + 150'C
Recommended Operating Conditions
Symbol
DM54S283
Parameter
DM74S283
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
0.8
0.8
V
-0.5
-0.5
High Level Output
Current (Other Outputs)
-1
-1
Low Level Output
Current (Output C4)
10
10
Low Level Output
Current (Other Outputs)
20
20
Vcc
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
10H
High Level Output
Current (Output C4)
2
2
V
mA
10L
mA
-55
Free Air Operating Temperature
TA
125
0
70
'C
Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
Conditions
=
VI
Input Clamp Voltage
Vee
VOH
High Level Output
Voltage
Vee = Min
10H = Max
VIL = Max
VIH = Min
Min,ll
=
DM54
Vee = Min, 10L = Max
VIH = Min, VIL = Max
II
Input Current @ Max
Input Voltage
Vee
=
Max, VI
=
5.5V
IIH
High Level Input Current
Vee
=
=
=
Max, VI
=
=
2.7V
Low Level Input Current
Vee
Short Circuit
Output Current
Vee
Max
(Note 2)
leel
Supply Current
Vee
ICC2
Supply Current
Vee
=
=
Max, VI
2.5
3.4
2.7
3.4
0.5V
-1.2
V
0.5
V
1
mA
50
p.A
-2
mA
-20
-100
Other Outputs
-40
-100
mA
Max (Note 3)
80
120
mA
Max (Note 4)
95
160
mA
Note 2: Not more than one output should be shorted al a time, and the duration should not exceed one second.
Note 4:
Units
C40utput
Note 1: All typical. are at Vcc - SV, TA - 25"C.
Note 3:
Max
V
DM74
Low Level Output
Voltage
los
Typ
(Note 1)
-18 mA
VOL
IL
Min
ICCI is measured with all outputs open, all B inputs low and all other inputs at 4.SV.
ICC2 is measured with all outputs open and all inputs at4.SV.
3·122
Switching Characteristics at Vee = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
Symbol
RL = 2800
From (Input)
To (Output)
Parameter
CL = 15pF
Min
tpLH
tpHL
Propagation Delay Time
Low to High Level Output
~1 or~2
Propagation Delay Time
High to Low Level Output
~1
CL = 50pF
Max
CO to
CO to
or ~2
Min
Units
Max
18
20
ns
18
20
ns
18
20
ns
18
20
ns
18
20
ns
18
20
ns
Propagation Delay Time
Low to High Level Output
CO to
Propagation Delay Time
High to Low Level Output
CO to
Propagation Delay Time
Low to High Level Output
CO to
Propagation Delay Time
High to Low Level Output
CO to
tpLH
Propagation Delay Time
Low to High Level Output
Ai,Si
toSi
18
20
ns
tpHL
Propagation Delay Time
High to Low Level Output
Aj,Si
toSi
18
20
ns
tpLH
Propagation Delay Time
Low to High Level Output (Note 1)
CO to
11
15
ns
Propagation Delay Time
High to Low Level Output (Note 1)
CO to
11
15
ns
tpLH
Propagation Delay Time
Low to High Level Output (Note 1)
Ai,Si
toC4
12
16
ns
tpHL
Propagation Delay Time
High to Low Level Output (Note 1)
Ai,Si
toC4
12
16
ns
tpLH
tpHL
tpLH
tpHL
tpHL
Note 1: RL
~
~3
~3
~4
~4
~4
~4
560n.
Function Table
Output
w~
w~
WhenC2 = L
WhenC2 = H
Input
% X X X X X X X X X
A3
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
H
~
B3
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
A4
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
~3
B4
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
~4
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
L
L
H
H
H
H
L
H
H
H
L
L
L
L
H
~3
C4
L
L
L
L
L
L
L
H
L
L
L
H
H
H
H
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
l:4
L
H
H
H
H
L
L
L
H
L
L
L
L
H
H
H
C4
L
L
L
L
L
H
H
H
L
H
H
H
H
H
H
H
TL/F/6484-3
High Level, L ~ Low Level
Note: Input conditions at A1, B1, A2, B2, and CO are used to determine outputs I1
B4 are then used to determine outputs I3, I4, and C4.
and I2 and the value of the internal carry C2. The values at C2, A3, B3, A4, and
3·123
~ ~L~O~9;~iC~D~~ia~g~r:a~m-----------------------------------------------S283
(9)
C4
(11)
84 .............J-.....
'""
(10)
~};4
A4
(12)
(15)
83 -"'11,.........-
.....
(14)
A3--~
(2)
82 ...........- - 1 -.....
A2~(3~)~l~>-----~
(6)
81 ......,.........-
.....
~
~I1
A1 __
(5...
) ~
CO
_.;.(7)..;....../
TL/F/6484-2
3-124
J?lI National
~ Semiconductor
DM74S299
TRI-STATE® 8-Bit Universal Shift/Storage Registers
Description
Features
This Schottky TIL eight-bit universal register features multiplexed inputs/outputs to achieve full eight bit data handling
in a single 20-pin package. Two function-select inputs and
two output-control inputs can be used to choose the modes
of operation listed in the function table.
• Multiplexed inputs/outputs provide improved bit
density
• Four modes of operation:
Hold (Store)
Shift Left
Shift Right
Load Data
• TRI-STATE outputs drive bus lines directly
• Can be cascaded for N-bit word lengths
• Operates with outputs enabled or at high Z
• Guaranteed shift (clock) frequency 50 MHz
• Typical power dissipation 700 mW
Synchronous parallel loading is accomplished by taking
both function-select lines, SO and 51, high. This places the
TRI-STATE outputs in a high-impedance state, which permits data that is applied on the input/output lines to be
clocked into the register. Reading out of the register can be
accomplished while the outputs are enabled in any mode. A
direct overriding input is provided to clear the register
whether the outputs are enabled or off.
Connection Diagram
Dual-In-Llne Package
vCC
SHIFT
SHIFT
LEFT
RIGHT
S1
SL Qw H/QHF/QFP/QpB/QBCLOCK SR
120 119
118
117 118
115
114
113
12
11
I I
S1
SL
QH' H/QH F/QF P/Qp B/QB CK
r- so
SR
r-
G
1
SO
-\2
G1
\3
4
5
6
7
8
9
\10
G2 G/QG E/QE C/QC AlQA QA' CLEAR GND
OUTPUT
CONTROLS
TLlF/6485-1
Order Number DM74S299N
See NS Package Number N20A
•
3-125
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required.
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
DM74S
O'Cto +70'C
Storage Temperature Range
-65'C to + 150'C
Note: The "Absolute Maximum Ratings" ara those values
beyond which the safety of the device cannot be guaran·
teed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Recommended Operating Conditions
Symbol
(See Section 1 for Test Waveforms and Output Load)
DM74S299
Parameter
Units
Min
Nom
Max
4.75
5
5.25
Vcc
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
0.8
IOH
High Level Output Current (OA thru OH)
-6.5
High Level Output Current (OA'. OH')
-0.5
IOL
V
V
2
Low Level Output Current (OA thru OH)
20
High Level Output Current (OA', OH')
6
V
rnA
mA
fCLK
Clock Frequency (Note 2)
0
70
50
MHz
fCLK
Clock Frequency (Note 3)
0
60
40
MHz
tw
Pulse Width (Note 5)
Setup Time (Notes 4 & 5)
Isu
Clock High
10
Clock Low
10
ClearLow
10
ns
Select
15t
Data High
7t
DataLow
5t
ns
tH
Hold Time (Notes 4 & 5)
5t
tREL
Clear Release Time (Note 5)
10t
Free Air Operating Temperature
Note 1: The symbol (t) Indicates the rising edge of the clock pulse Is used for reference.
Note 2: CL = 15 pF, RL = 2800, TA = 2SOC and Vee = 5V.
Note 3: CL = 50 pF, RL = 2800, TA = 2SOC and Vee = 5V.
Note 4: Data Includes the two serial inputs and Ihe eight inpul/output dala lines.
Note 5: TA = 25'C and Vee = 5V.
TA
ns
ns
0
70
'C
Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
Input Clamp Voltage
Vee
VOH
High Level Output
Voltage
VCC = Min, IOH = Max
VIL = Max, VIH = Min
VOL
Low Level Output
Voltage
Vee = Min, IOL = Max
VIH = Min, VIL = Max
II
Input Current @ Max
Input Voltage
VCC
IIH
High Level Input
Current
Vee = Max
VI = 2.7V
All typicals are al vee
= 5V,
Typ
(Note 1)
OAthruOH
2.4
3.2
OA',OH'
2.7
3.4
= Min,ll = -18 mA
VI
Note 1:
Min
Conditions
TA
=
3-126
Units
-1.2
V
V
0.5
= Max, VI = 5.5V
25'C.
Max
1
Athru H,
50,51
100
Any Other
50
V
mA
pA
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted) (Continued)
Symbol
IlL
10ZH
10ZL
los
Parameter
Conditions
Low Level Input
Current
Vee = Max
VI = 0.5V
Typ
(Note 1)
Min
Max
Units
-2
Clock, Clear
50,51
-0.5
Other
-0.25
mA
Off-State Output Current with
High Level Output Voltage
Applied (QA thru QH)
Vee = Max, Vo = 2.4V
VIH = Min, VIL = Max
100
/LA
Off-State Output Current with
Low Level Output Voltage
Applied (QA thru QH)
Vee = Max, Vo = 0.5V
VIH = Min, VIL = Max
-250
/LA
Short Circuit Output
Current (QA thru QH)
Vee = Max (Note 2)
Short Circuit Output
Current (QA" QH')
Vee = Max (Note 2)
-40
-100
-20
-100
mA
Supply Current
Vee = Max
lee
Note 1: Ali typicals are at Vee ~ SV, TA ~ 25°C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Switching Characteristics
140
225
mA
at Vee = 5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
RL = 2800 (Note 2)
Symbol
Parameter
From (Input)
To (Output)
CL = 15pF
Min
Max
CL = 50pF
Min
Units
Max
fMAX
Maximum Clock
Frequency
tpLH
Propagation Delay Time
Low to High Level Output (Note 2)
Clock to
QA' orQH'
20
22
ns
tpHL
Propagation Delay Time
High to Low Level Output (Note 2)
Clock to
QA' orQH'
20
23
ns
tpLH
Propagation Delay Time
Low to High Level Output
Clock to
QA thruQH
21
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clock to
QA thruQH
21
ns
tpHL
Propagation Delay Time
High to Low Level Output (Note 2)
Clear to
QA,orQH'
24
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clear to
QAthruQH
24
ns
tPZH
Output Enable Time
to High Level Output
<31,<32 to
QAthruQH
18
ns
tpZL
Output Enable Time
to Low Level Output
G1,G2to
QA thruQH
18
ns
tpHZ
Output Disable Time
to High Level Output (Note 1)
G1, G2to
QA thruQH
12
ns
<31, <32 to
QA thruQH
12
ns
Output Disable Time
to Low Level Output (Note 1)
Note 1: CL ~ 5 pF.
Note 2: RL ~ 1Kn for delays measured to ON and OH'.
Note 3: For testing fMAX ali outputs are loaded simultaneously.
tpLZ
(Note 3)
3-127
40
50
21
MHz
•
Function Table
Inputs
Mode
Function
Clear Select
S1
Inputs/Outputs
SO G1t G2t
X
L
L
X
outputs
Output
Serial
Control Clock
A/QA B/Qs C/Qc D/QD E/QE F/QF G/QG H/QH QA' QH'
SL SR
L
L
L
L
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
X
X
aAO
aAO
aBO
aBO
aeo
aeo
aDO
aoo
aEO
aEO
aFO
aFO
aGO
aGO
aHO aAO aHO
aHO aAO aHO
X
X
H
L
H
L
aAn
aAn
aBn
aBn
aon
aon
aon
aon
aEn
aEn
aFn
aFn
aGn
aGn
H
L
aGn
aGn
H
L
X
X
aBn
aBn
aon
aon
aon
aon
aEn
aEn
aFn
aFn
aGn
aGn
aHn
aHn
H
L
aBn
aBn
H
L
X
X
a
b
c
d
a
f
9
h
a
h
Claar
L
L
Hold
H
H
L
L
X
L
L
L
L
X
X
Shift Right
H
H
L
L
H
H
L
L
L
L
Shift Left
H
H
H
H
L
L
L
L
L
L
Load
H
H
H
X
X
t
t
t
t
t
L
L
L
L
L
L
L
tWhen one or both output control. are high the eight Input/output terminals are disabled to the hlgh·lmpedance state; however, sequential operation or
clearing 01 the register Is nOl affected
a••. h = the level 01 the steady·state Input at Inputs A through H, respectively. The.e data are loaded Into the flip-flops while the fllp·flop outputs are Isolated
from the Input/output" terminals.
QAO...OtiO = The output loglc level 01 Qx belore the Indicated Input conditions were established.
H = high levet, L = low logic level, X = either low or high logic level
QAn...Otin = The output loglc level before the active transition ( t) 01 the clock Input.
3-128
r-
o
ce
n"
c
iii"
S1
ce
...
SO
~~
D)
3
SHIFT
510FT
(11)
LEFT
SERIAL
INPUT
D
rHf-+f---,(",'8",) ~~~~L
u
INPUT
~
I\)
CO
CLOCK (12)
+8.
~
.~~-------;:-~:t::~::::~~t:~~::::~:t::~::::~~i:::t:::::~~~:t::::::~~::t:::::~~t:~~::::~:±
__~____-'t(~1~7) °H'
(A'
QA'
('
CLEAR
rt
_f'''
QUTPUT
CONTROLS
{Gl
(3)
G2
(7)
A/OA
(13)
I
BlOB
(6)
C/Oe
(14)
DIOn
(5)
E/OE
(15)
FIOF
(4)
G/OG
(16)
HlOH
TLlF/B485-2
66~S
iii
~National
~ Semiconductor
DM54S373/DM74S373, DM54S37 4/DM7 4S37 4
TRI-STATE® Octal D-Type Transparent Latches
and Edge-Triggered Flip-Flops
General Description
Schmitt-trigger buffered inputs at the enable! clock lines
simplify system design as ac and dc noise rejection is improved by typically 400 mV due to the input hysteresis. A
buffered output control input can be used to place the eight
outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state
the outputs neither load nor drive the bus lines Significantly.
These a-bit registers feature totem-pole TRI-STATE outputs
designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high-logic-level drive provide these registers with
the capability of being connected directly to and driving the
bus lines in a bus-organized system without need for interface or pull-up components. They are particularly attractive
for implementing buffer registers, I!O ports, bidirectional
bus drivers, and working registers.
The eight latches of the DM5417 4S373 are transparent
D-type latches meaning that while the enable (G) is high the
Q outputs will follow the data (D) inputs. When the enable is
taken low the output will be latched at the level of the data
that was set up.
The output control does not affect the internal operation of
the latches or flip,flops. That is, the old data can be retained
or new data can be entered even while the outputs are off.
Features
• Choice of a latches or a D-type flip-flops in a single
package
• TRI-STATE bus-driving outputs
• Full parallel-access for loading
• Buffered control inputs
• P-N-P input reduce D-C loading on data lines
The eight flip-flops of the DM54!74S374 are edge-triggered
D-type flip-flops. On the positive transition of the clock, the
Q outputs will be set to the logic states that were set up at
the D inputs.
Connection Diagrams
Dual-In-Line Package
ENABLE
OUTPUT
CONTROL
00
00
ro
ro
00
10
1D
2D
2Q
3Q
~
3D
~
~
G
4D
40
GND
Order Number DM54S373J,
DM74S373WM or
DM74S373N
See NS Package Number
J20A, M20B or N20A
TLlF/64B6-1
8Q
aD
Dual-In-Llne Package
7D
70
eo
eD
5D
50
CLOCK
Order Number DM54S374J,
DM74S374WM or
DM74S374N
See NS Package Number
J20A, M20B or N20A
OUTPUT
10
CON11IOL
TL/F/64B6-2
3-130
r--------------------------------------------------------------------------,0
~
w
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
Storage Temperature Range
-65'C to + 150'C
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
-55'Cto + 125'C
DM54S
O'Cto +70'C
DM74S
•
~
......
0l:Io
Function Tables
DM54174S374
Truth Table
DM54174S373
Truth Table
Output
Control
Enable
G
L
L
L
H
H
H
L
X
H
D
Output
H
L
H
L
X
X
00
Output
Control
L
L
L
H
Z
Clock
D
Output
t
t
H
L
H
L
L
X
X
00
X
Z
= High Level (Steady State), L = Low Level (Steady State). X = Don't Care
i
= Transition from low·to·high level, Z = High Impedance State
00 = The level 01 the output before
steady·state input conditions were established.
Logic Diagrams
DM54174S374
Posltlve-Edge-Triggered Flip-Flops
DM54174S373
Transparent Latches
c~~~-!.(1:':')----"-"-- so
50
60
I--+-"':":::!so
20
30 -"'-'---i--i
30
50
t--+-""""'"-(7)
30 -.:.(7,,:,'_ _
40
10
(4)
I--+-""::::"- 20
+--1
t--+--'-~
(17)
70
70
(18)
80
(18)
80
80
TL/F/6486-3
TL/F/6486-4
3·131
•
'8373 Recommended Operating Conditions (See Section 1 for Test Waveforms and Output Load)
Symbol
DM54S373
Parameter
DM74S373
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
Vee
Supply Voltage
VIH
High Levl!llnput Voltage
Vil
Low Level Input Voltage
0.8
0.8
V
10H
High Level Output Current
-2
-6.5
mA
10l
Low Level Output Current
20
20
mA
tw
Pulse Width
(Note 2)
2
2
Enable
High
6
6
Enable
Low
7.3
7.3
V
ns
tsu
Data Setup Time (Notes 1 and 3)
ot
ot
tH
Data Hold Time (Notes 1 and 3)
10t
10 t
TA
Free Air Operating Temperature
-55
125
ns
ns
0
70
·C
1: The symbol (.j.) Indicates the falling edge of the clock pulse is used for reference.
2: CL = 15 pF. RL = 2800, TA = 25'C and Vec = 5V.
Note 3: TA = 25'C and Vee = 5V.
Note
Note
'8373 Electrical Characteristics
Symbol
over recommended operating free air temperature (unless otherwise noted)
Parameter
Conditions
VI
Input Clamp Voltage
VOH
High Level Output
Voltage
Vee = Min
10H = Max
Vil = Max
VIH = Min
VOL
Low Level Output
Voltage
Vee = Min, 10l = Max
VIH = Min, Vil = Max
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 5.5V
Min
Typ
(Note 4)
Vee = Min,ll = -18 mA
DM54
2.4
3.4
DM74
2.4
3.2
Max
Units
-1.2
V
V
0.5
V
1
mA
IIH
High Level Input Current
Vee = Max, VI = 2.7V
50
/LA
III
Low Level Input Current
Vee = Max, VI = 0.5V
-250
/LA
10ZH
Off-State Output
Current with High
Level Output
Voltage Applied
Vee = Max, Vo = 2.4V
50
/LA
Off-State Output
Current with Low
Level Output
Voltage Applied
Vee = Max, Vo = 0.5V
-50
/LA
Short Circuit
Output Current
Vee = Max
(Note 5)
DM54
-40
-100
DM74
-40
-100
Supply Current
Vee = Max
Outputs High or Low
10Zl
los
Icc
VIH = Min, Vil = Max
VIH = Min, Vil = Max
Outputs Disabled
Note 4: All typicals are at Vee
= 5V, TA = 25'C.
Note 5: Not more than one output should be shorted at a time, and the duration should not exceed one second.
3-132
105
160
190
mA
mA
'S373 Switching Characteristicsatvcc = 5V and TA = 25·C
(See Section 1 for Test Waveforms and Output Load)
RL
Symbol
From (Input)
Parameter
CL
To (Output)
=
Min
=
15pF
2800
CL
Max
=
50pF
Min
Units
Max
tplH
Propagation Delay Time Low
to High Level Output
Data to
AnyQ
12
14
ns
tpHl
Propagation Delay Time High
to Low Level Output
Data to
AnyQ
12
16
ns
tplH
Propagation Delay Time Low
to High Level Output
Enable to
AnyQ
14
14
ns
tpHl
Propagation Delay Time High
to Low Level Output
Enable to
AnyQ
18
21
ns
tPZH
Enable Time to
High Level Output
Output Control
to Any Q
15
17
ns
tpZl
Output Enable Time to
Low Level Output
Output Control
to Any Q
18
23
ns
tpHZ
Output Disable Time to
High Level Output (Note 1)
Output Control
to Any Q
9
ns
tpLZ
Output Disable Time to
Low Level Output (Note 1)
Output Control
to Any Q
12
ns
Note 1: Cl
= 5 pF
'S374 Recommended Operating Conditions
(See Section 1 for Test Waveforms and Output Load)
Symbol
DM74S374
DM54S374
Parameter
UnIts
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
Vcc
Supply Voltage
V,H
High Level Input Voltage
V,l
Low Level Input Voltage
0.8
0.8
V
IOH
High Level Output Current
-2
-6.5
rnA
IOl
Low Level Output Current
20
20
rnA
fClK
Clock Frequency (Note 2)
fClK
Clock Frequency (Note 3)
tw
Pulse Width
(Note 2)
Pulse Width
(Note 3)
V
V
2
0
100
75
0
100
75
MHz
0
100
75
0
100
75
MHz
Clock
High
6
6
Clock
Low
7.3
7.3
Clock
High
15
15
Clock
Low
15
15
ns
tsu
Data Setup TIme (Notes 1 and 4)
5t
5t
ns
tH
Data Hold Time (Notes 1 and 4)
2t
2t
ns
TA
Free Air Operating Temperature
-55
125
Note 1: The symbol (t) Indicates the rising edge 01 the clock pulse is used for reference.
Note 2: Cl = 15 pF, Rl = 280n, TA = 25'C and Vee = sv.
Note 3: Cl = 50 pF, Rl = 280n, TA = 2S'C and Vee = SV.
Note 4: TA = 2S'C and Vee = SV.
3-133
0
70
·C
•
'S374 Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
MIn
Typ
(Note 1)
DM54
2.4
3.4
DM74
2.4
3.2
CondItIons
=
=
VI
Input Clamp Voltage
Vee
VOH
High Level Output
Voltage
Vee = Min
10H = Max
Vil = Max
VIH = Min
VOL
Low Level Output
Voltage
Vee = Min, 10l = Max
VIH = Min, Vil = Max
II
Input Current @ Max
Input Voltage
Vee
=
Max, VI
=
5.5V
IH
High Level Input
Current
Vee
=
Max, VI
=
2.7V
III
Low Level Input
Current
Vee
=
Max, VI
=
0.5V
10ZH
Off-State Output
Current with High
Level Output
Voltage Applied
10Zl
los
lee
Min,ll
-18 mA
Max
UnIts
-1.2
V
V
0.5
V
1
mA
50
p.A
-250
p.A
Vee = Max, Vo = 2.4V
VIH = Min, Vil = Max
50
p.A
Off-State Output
Current with Low
Level Output
Voltage Applied
Vee = Max, Vo = 0.5V
VIH = Min, Vil = Max
-50
p.A
Short Circuit
Output Current
Vee = Max
(Note 2)
Supply Current
Vee
=
DM54
-40
-100
DM74
-40
-100
Outputs High
Max
mA
110
Outputs Low
90
140
Outputs Disabled
mA
160
Note 1: All typicals are at Vee = 5V, TA = 25'C.
Note 2: Not more than one output should be shorted at a lime, and the duralion should not exceed one second.
'S374 Switching Characteristics at Vee =
5V and T A
=
25'C
(See Section 1 for Test Waveforms and Output Load)
RL
From (Input)
Symbol
Parameter
To (Output)
CL
Min
=
15pF
Max
=
2800.
CL
Min
=
50pF
Units
Max
fMAX
Maximum Clock Frequency
75
75
MHz
tpLH
Propagation Delay Time Low
to High Level Output
Clock to
AnyQ
15
15
ns
tpHl
Propagation Delay Time High
to Low Level Output
Clock to
AnyQ
17
20
ns
tPZH
Output Enable Time to
High Level Output
Output Control
to Any Q
15
17
ns
tpZl
Output Enable Time to
Low Level Output
Output Control
to Any Q
18
23
ns
tpHZ
Output Disable Time from
High Level Output (Note 1)
Output Control
to Any Q
9
ns
tpLZ
Output Disable Time from
Low Level Output (Note 1)
Output Control
to Any Q
12
ns
Note 1: CL
= 5 pF
3-134
_NatiOnal
Semiconductor
DM748381 Arithmetic Logic
Unit/Function Generator
General Description
Features
The '5381 is a Schottky TTL arithmetic logic unit (ALU)I
function generator that performs eight binary arithmeticllogic operations on two 4-bit words as shown in the function
table. These operations are selected by the three functionselect lines (SO, 51, S2). A full carry look-ahead circuit is
provided for fast, simultaneous carry generation by means
of two cascade outputs (p and G) for the four bits in the
package. The method of cascading 5451821745182 lookahead carry generators with these ALU's to provide multilevel full carry look-ahead is illustated under typical applications data for the '5182. The typical addition times shown
illustrate the short delay time required for addition of longer
words when full look-ahead is employed. The eXClUSive-OR,
AND, or OR function of two Boolean variables is provided
without the use of external circuitry. Also, the outputs can
be either cleared (low) or preset (high) as desired.
• A fully parallel 4-Bit ALU in 20-pin package for 0.300inch row spacing
• Ideally suited for high-density economical processors
• Parallel inputs and outputs and full look-ahead provide
system flexibility
• Arithmetic and logic operations selected specifically to
simplify system implementation:
A minus B
B minus A
A pius B
and five other functions
• Schottky-clamped for high performance
16-bit add time ... 26 ns typ using look-ahead
32-bit add time ... 34 ns typ using look-ahead
Connection Diagram
Pin Designations
Dual-In-Llne Package
INPUTS
Vee
120
A2
b9
B2
-1~8
A3
117
I I
A2
B2
A3
OUTPUTS
B3
1,8
en
1,5
ji
G
F3
114
~3
1'2
1
AI
en
p
G
F3
Designation
Pin Nos_
Function
A3, A2, A1, AO
17,19,1,3
Word A Inputs
B3,B2,B1,BO
16,18,2,4
Word B Inputs
52,51,50
7,6,5
Function-Select
Inputs
Cn
15
Carry Input for
Addition, Inverted
Carry Input for
Subtraction
F3,F2,F1,FO
12,11,9,8
Function Outputs
is
14
Inverted Carry
Propagate Output
G
13
Inverted Carry
Generated Output
Vee
20
Supply Voltage
GND
10
Ground
F2
AO
BO
Ij2 I
so
SI
S2
FO
Fl
I I I I I
13
Bl
11
I I I I I
B3
AI
Bl
F2
14
AO
BO
J.5
so
INPUTS
16
SI
J'
S2
18
19
-FO
F1
__1'0
GND
OUTPUTS
TL/F/6487-1
Order Number DM74S381N
See NS Package Number N20A
Function Table
Selection
H
S2
S1
SO
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
Arithmetic/Logic
Operation
CLEAR
BMINUSA
A MINUS B
A PLUS B
AGlB
A+B
AB
PRESET
= high level, L = low level
3-135
•
Absolute Maximum Ratings (Note)
Supply Voltage
Input Voltage
Operating Free Air Temperature Range
Storage Temperature Range
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guarant88d. The device should not be operated at th8Selimits. The
perametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
7V
5.5V
O·Cto +70·C
- 65·C to + 150"C
Recommended Operating Conditions
Symbol
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
Min
Nom
Max
Units
4.75
5
5.25
V
2
V
VIL
Low Level Input Voltage
0.8
V
IOH
High Level Output Current
-1
mA
20
mA
70
·c
IOL
Low Level Output Current
TA
Free Air Operating Temperature
0
Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
Conditions
Input Clamp Voltage
Vee
VOH
High Level Output
Voltage
Vee = Min, 10H = Max,
VIL = Max, VIH = Min
VOL
Low Level Output
Voltage
Vee = Min,lOL = Max
VIH = Min, VIL = Max
II
Input Current @ Max
Input Voltage
Vee
IIH
High Level Input
Current
Vee = Max
VI = 2.7V
los
Low Level Input
Current
Short Circuit
Output Current
2.7
Max
Units
-1.2
V
3.4
= Max, VI = 5.5V
Vee = Max
VI = 0.5V
Vee
Typ
(Note 1)
= Min,ll = -18mA
VI
IlL
Min
V
0.5
V
1
mA
AnyS
50
Cn
250
Any Other
200
AnyS
-2
Cn
-8
Any Other
-6
= Max (Note 2)
-40
Supply Current
Vee = Max
lee
Note 1: All typicalsare atVcc = 5V,TA = 25'C.
Note 2: Not mora than one output should be shorted at a time, and the duration should not exceed one second.
3-136
105
/LA
mA
-100
mA
160
mA
Switching Characteristics at Vee = 5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
RL
Symbol
Parameter
From (Input)
To (Output)
CL
Min
=
15PF'
Max
=
2800
CL
Min
=
50pF
Units
Max
tpLH
Propagation Delay Time
Low to High Level Output
Cnto
AnyF
17
19
ns
tpHL
Propagation Delay Time
High to Low Level Output
Cnto
AnyF
17
19
ns
tpLH
Propagation Delay Time
Low to High Level Output
AorB
toG
20
23
ns
tpHL
Propagation Delay Time
High to Low Level Output
AorB
toG
20
23
ns
tpLH
Propagation Delay Time
Low to High Level Output
AorB
to j5
18
21
ns
tpHL
Propagation Delay Time
High to Low Level Output
AorB
to j5
18
21
ns
tpLH
Propagation Delay Time
Low to High Level Output
AjorBj
to Fj
27
30
ns
tpHL
Propagation Delay Time
High to Low Level Output
AjorBj
to Fj
25
27
ns
tpLH
Propagation Delay Time
Low to High Level Output
Sto
Any
30
33
ns
tpHL
Propagation Delay Time
High to Low Level Output
Sto
Any
30
33
ns
•
3-137
-~------------------------------------------~
~
U)
Logic Diagram
C
n
115)
(4)
80
.
~~
~
.....
FLJ-
v
(3)
:?J
B
00
·l~
P
FO
}-
(2)
8'
....
"v
0'
(')
(18)
82
...v
:~
9;...1
~
~~
B)J
......
02
('.)
(16)
..
83
v
......
03
('7)
~
~~
e-=J
I:f
}-
~D
(S)
S2
..
...
(7) ......
I"'~
... I
~
.v...
h-
~ D~ F3
=f)
('4)
ji
)-
..
5' ---v
F2
:::f}-
p(5)
~
F'
.r-o.
13
so ---v
-~
p-1
frl->"
rU
It
~
~P
(13)
II
I}-
TLIFI6487-2
3·138
r---------------------------------------------------------------------------~ U)
~
~National
g
~ Semiconductor
DM93S00
4-Bit Universal Shift Register
General Description
Features
This device is 4-bit universal shift register. As a high speed
multifunctional sequential logic block, it is useful in a wide
variety of register and counter applications. It may be used
in serial-serial, shift left, shift right, serial-parallel, parallelserial, and parallel-parallel data register transfers.
• Asynchronous master reset
• J, R inputs to first stage
Connection Diagram
Logic Symbol
Dual-In-Line Package
tJR-l
J- 2
\,J
R- 3
POPlP2P3-
4
5
6
7
16
15
14
13
12
iii i I
f-Vcc
1-00
1-01
1-02
2- J
03 ~11
10- CP
3--(l K MR 00 01 02 03
r
~03
11~Q3
10 f-CP
GND- 8
PE PO PI P2 P3
lLLLl
TLlF/10164-2
vcc = Pin 16
91-PE
GND = PinS
TLlF/10164-1
Order Number DM93S00N
See NS Package Number N16E
Truth Table
Operating
Mode
Shift Mode
Parallel
Entry Mode
Inputs (MR = H)
Outputs
@ tn
+1
PE
J
K
PO
P1
P2
P3
00
01
02
03
03
H
H
H
L
L
L
H
L
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
00
00
00
00
01
01
01
01
02
02
02
02
02
02
02
02
L
L
X
X
X
X
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
L
H
'In + 1 = Stale after next lOW-la-HIGH clock transilion.
H = HIGH Voltage level
L = lOW Vollage level
X = Immalerial
00
00
H
•
3-139
Absolute Maximum Ratings
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
DM93S
O'Cto +70'C
Storage Temperature Range
- 65'C to + 150'C
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Recommended Operating Conditions
Symbol
DM93S00
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
Units
Min
Nom
Max
4.75
5
5.25
V
V
2
VIL
Low Level Input Voltage
O.S
V
10H
High Level Output Current
-1
mA
20
mA
70
'C
10L
Low Level Output Current
TA
Free Air Operating Temperature
ts (H)
ts (L)
J, K and PO-P3 to CP
th (H)
th (L)
J, K and PO-P3 to CP
ts(H)
!s(L)
0
Setup TIme HIGH or LOW,
6.0
6.0
ns
0
0
ns
Setup Time HIGH or LOW,
PE to CP
S.O
S.O
ns
th (H)
th (L)
Hold Time HIGH or LOW,
PEtoCP
0
0
ns
!w(H)
!w(L)
CP Pulse Width
HIGH or LOW
7.0
7.0
ns
twILl
MR Pulse Width LOW
12
ns
trec
Recovery Time
MRtoCP
5.0
ns
Hold Time HIGH or LOW,
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
VI
Input Clamp Voltage
Vee = Min,ll = -1S mA
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
VIL = Max
VOL
Low Level Output
Voltage
Vee = Min, 10L = Max
VIH = Min
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 5.5V
Min
2.7
Typ
(Note 1)
Max
Units
-1.2
V
3.4
0.35
V
0.5
V
1
mA
IIH
High Level Input Current
Vee = Max, VI = 2.7V
50
p.A
IlL
Low Level Input Current
Vee = Max, VI = 0.5V
-2.0
mA
los
Short Circuit
Output Current
Vee = Max
(Note 2)
60
mA
120
mA
20
Supply Current
Vee = Max
Icc
Note 1: All Iypicals are at Vee = SV. TA = 2S'e.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
3-140
,---------------------------------------------------------------------------------.U)
Co)
Switching Characteristics at Vee =
5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
en
o
Q
Symbol
RL = 2800.
CL = 15pF
Parameter
Min
Units
Max
f max
Maximum Shift
Frequency
tpLH
tpHL
Propagation Delay
CPtoOn
8.5
12
ns
tpHL
Propagation Delay
MRtoOn
23
ns
70
MHz
Functional Description
D-type input for general applications by tying the two pins
together. When the PE input is LOW, the DM93S00 appears
as four common clocked D flip-flops. The data on the parallel inputs PO-P3 is transferred to the respective 00-03
outputs following the LOW-to-HIGH clock transition. Shift
left operation (03 - 02) can be .achieved by tying the an
outputs to the Pn-1 inputs and holding the PE input LOW.
The Logic Diagrams and Truth Table indicate the functional
characteristics of the DM93S00 4-bit shift register. The device is useful in a wide variety of shifting, counting and storage applications. It performs serial, parallel, serial-to-parallei, or parallel-to-serial data transfers.
The DM93S00 has two primary modes of operation, shift
right (00 - 01) and parallel load, which are controlled by
the state of the Parallel Enable (PE) input. When the PE
input is HIGH, serial data enters the first flip-flop 00 via the
J and K inputs and is shifted one bit in the direction
00 - 01 - 02 - 03 following each LOW-to-HIGH
clock transition. The JK inputs provide the flexibility of the
JK type input for special applications, and the simple
All serial and parallel data transfers are synchronous, occuring after each LOW-to-HIGH clock transition. Since the
DM93S00 utilizes edge triggering, there is no restriction on
the activity of the J, K, Pn and PE inputs for logic operation-except for the setup and release time requirements. A
LOW on the asynchronous Master Reset (MR) input sets all
a outputs LOW, independent of any other input condition.
Logic Diagram
K
00
P3
P2
PI
PO
01
02
CP
t.lii
03 Q3
TLlF/l0164-3
3-141
_
i
r---------------------------------------------------------------------------~
~National
~ Semiconductor
DM93S41
4-Bit Arithmetic Logic Unit
General Description
The DM93S41 4·bit arithmetic logic units can perform all the
possible 16 logic operations on two variables and a variety
of arithmetic operations; the Add and Subtract modes are
the most important. The DM93S41 is a pin replacement for
the 54174181.
Connection Diagram
Dual-in-Line Package
80
AO
Vee
AI
S3
81
Pin Name
Description
AO-A3,80-83
SO-53
Operand Inputs (Active LOW)
Function Select Inputs
Mode Control Input
Carry Input
Function Outputs (Active LOW)
Comparator Output
Carry Generate Output (Active LOW)
Carry Propagate Output (Active LOW)
Carry Output
M
52
A2
51
82
50
A3
CU
FO-F3
A=B
G
Cn
83
p
t.I
G
Cn +4
ro
Cn+4
F'1
p
F'2
A=B
GND
F'3
TL/F/9805-1
Order Number DM93S41N
See NS Package Number N24A
Logic Symbols
Active Low Operands
2
Active High Operands
1 23 22 21 20 19 18
2
7
1 23 22 21 20 19 18
7
8
Cn + 4
16
Cn +4
16
50
A=B
14
5
51
G
17
"
52
P
15
8
6
50
A=B
14
6
G
17
5
51
4
52
3
53
P
FO
F1
F2
F3
9
10
11
13
15
3
TLlF/9805-2
3-142
53
Fa
F1
F2
F3
9
10
11
13
TL/F/9805-3
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
Operating Free Air Temperature Range
DM93S
Storage Temperature Range
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaran·
teed. The device should not be operated at these limits. The
parametric values defined in the "£/ectrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operatiOn.
5.5V
O'Cto +70'C
- 65'C to + 150'C
Recommended Operating Conditions
Symbol
DM93S41
Parameter
VCC
Supply Voltage
VIH
High Level Input Voltage
Units
Min
Nom
Max
4.75
5
5.25
V
2
V
Vil
Low Level Input Voltage
0.8
V
10H
High Level Output Current
-1
rnA
20
rnA
70
'C
10l
Low Level Output Current
TA
Free Air Operating Temperature
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
VI
Input Clamp Voltage
Vcc = Min,ll = - 18 rnA
VOH
High Level Output
Voltage
Vcc = Min, 10H = Max
Vil = Max
VOL
Low Level Output
Voltage
VCC = Min, 10l = Max
VIH = Min
II
Input Current @ Max
Input Voltage
Vcc = Max, VI = 5.5V
Min
2.7
Typ
(Note 1)
Max
Units
-1.2
V
3.4
0.35
V
0.5
V
1
rnA
IIH
High Level Input Current
Vcc = Max, VI = 2.7V
50
/LA
III
Low Level Input Current
Vcc = Max, VI = 0.5V
-1.6
rnA
los
Short Circuit
Output Current
Vcc = Max
(Note 2)
-100
rnA
ICCl
Supply Current
Vcc = Max
M, SO-53 = 4.5V
All Other Inputs = OV
150
rnA
Vcc = Max
Cn,80-83 = GND
All Other Inputs = 4.5V
140
rnA
ICCH
Note
Supply Current
1: All typical. are at Vec
~
5V. TA
~
-40
25"C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
3-143
Switching Characteristics
Vee
= + 5.0V, TA = + 25°C (See Section 1 for waveforms and
load configurations)
CL = 15pF
Symbol
Parameter
Conditions
RL
Min
=
Units
2800.
Max
tpLH
tpHL
Propagation Delay
Cn toCn +4
M
=
Gnd
12
12
ns
tpLH
tpHL
Propagation Delay
CntoF
M
=
Gnd
12
12
ns
tpLH
tpHL
Propagation Delay
AnorBntoG
M, 51, 52 = Gnd
50,53 = 4.5V
14
14
ns
tpLH
tpHL
Propagation Delay
AnorBntoG
M, SO, 53 = Gnd
51,52 = 4.5V
15
15
ns
tpLH
tpHL
Propagation Delay
AnorBntoP
M, 51, 52 = Gnd
50,53 = 4.5V
14
14
ns
tpLH
tpHL
Propagation Delay
AnorBntoP
M, S0, 53 = Gnd
51,52 = 4.5V
15
15
ns
tpLH
tpHL
Propagation Delay
AjorBjtoFI
M, 51, 53 = Gnd
50,53 = 4.5V
20
20
ns
tpLH
tpHL
Propagation Delay
AjorBjto Fj
M, S0, 53 = Gnd
51,52 = 4.5V
21
21
ns
tpLH
tpHL
Propagation Delay
AjorBjtoFj+1
M, 51, 52 = Gnd
50,53 = 4.5V
24
24
ns
tpLH
tpHL
Propagation Delay
AjorBjtoFj+1
M, S0, 53 = Gnd
51,52 = 4.5V
25
25
ns
tpLH
tpHL
Propagation Delay
AnorBntoF
M
20
20
ns
tpLH
tpHL
Propagation Delay
An orBn to Cn + 1
M, 51, 52 = Gnd
50,53 = 4.5V
18.5
18.5
ns
tpLH
tpHL
Propagation Delay
AnorBntoCn + 1
M, S0, 53 = Gnd
51,52 = 4.5V
23
23
ns
tpLH
tpHL
Propagation Delay
An orBnto A = B
M, S0, 53 = Gnd
51,52 = 4.5V
RL = 4000. to 5.0V
23
23
ns
=
4.5V
3·144
Functional Description
The DM93S41 is a 4-bit high speed parallel arithmetic logic
unit (ALU). Controlled by the four Function Select inputs
(SO-S3) and the Mode Control input (M), it can perform all
the 16 possible operations or 16 different arithmetic operations on active HIGH or active LOW operands. The Function
Table below lists these operations.
When the Mode Control input (M) is HIGH, all internal carries are inhibited and the device performs logic operations
on the individual bits as listed. When the Mode Control input
is LOW, the carries are enabled and the device performs
arithmetic operations on the two 4-bit words. The device
incorporates full internal carry lookahead and provides for
either ripple carry between devices using the Cn +4 output,
or for carry lookahead between packages using the signals
j5 (Carry Propagate) and G (Carry Generate). j5 and G are
not affected by carry in. When speed requirements are not
stringent, the DM93S41 can be used in a simple ripple carry
mode by connecting the Carry output (C n+ 4) signal to the
Carry input (Cn) of the next unit. For super high speed operation the Schottky DM93S41 should be used in conjunction
with the' 42 carry lookahead circuit.
The A = B output from the DM93S41 goes HIGH when all
four Fn outputs are HIGH and can be used to indicate logic
equivalence over four bits when the unit is in the subtract
mode. The A = B output is open-collector and can be
wired-AND with the other A = B outputs to give a comparison for more than four bits. The A = B signal can also be
used with the Cn +4 signal to indicate A > B and A < B.
The Function Table lists the arithmetic operations that are
performed without a carry in. An incoming carry adds a one
to each operation. Thus select code LHHL generates A minus B minus 1 (2s complement notation) without a carry in
and generates A minus B when a carry is applied. Because
subtraction is actually performed by complementary addition (ls complement), a carry out means borrow; thus a
carry is generated when there is no underflow and no carry
is generated when there is underflow.
As indicated the '41 can be used with either active LOW
inputs producing active LOW outputs or with active HIGH
inputs producing active HIGH outputs. For either case the
table lists the operations that are performed to the operands
labeled inside the logic symbol.
Function Table
Mode Select
Inputs
S3
S2
Sl
SO
L
L
L
L
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
L
L
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
L
H
L
H
H
H
H
H
H
H
H
H
L
L
H
H
L
H
L
H
Active Low Inputs
& Outputs
Active High Inputs
& Outputs
Logic Arithmetic··
(M = H)
(M = L) (Cn = L)
Logic Arithmetic··
(M= H)
(M = L) (C n = H)
A
AB
A+B
Logic 1
A+B
B
ACllB
A+B
AB
ACllB
B
A+B
Logic 0
AB
AB
A
A minus 1
AB minus 1
ABminus 1
minus 1
A plus (A + B)
AB plus (A + B)
A minus B minus 1
A+B
A plus (A + B)
A plus B
AB plus (A + B)
A+B
A plus A·
AB plusA
ABminusA
A
tEach bit is shifted to the next more significant position
•• Arithmetic operations expressed in 28 complement notation
H = HIGH Voltage Level
L = LOW Voltage Level
3-145
A
A+B
AB
Logic 0
AB
B
ACllB
AB
A+B
ACllB
B
AB
Logic 1
A+B
A+B
A
A
A+B
A+B
minus 1
ApiusAB
(A + B) plus AB
A minus B minus 1
ABminus 1
ApiusAB
A plus B
(A + B) plus AB
ABminus 1
AplusA*
(A + B) plus A
(A + B) plus A
A minus 1
~
~
~
en
r-----------------------------------------------------------------------------,
Logic Diagram
,~
..,..---HH--F.::::3
X)-1-----<>""
,!:1 ----HH-......- I
,~
.....--+l-I-F-'3
I~
---+l-I-t-+-I
'''' ....---I-I-I-F=I
,~
1<
...'"
II
0
''''
,...
1Si!-----_-I
~-----------------~~,
3-146
,:=
SUM MODE TEST TABLE I. Function Inputs: 80 = 83 = 4.5V, 81 = 82 = M = OV
Symbol
Input
Under
Test
Other Input
Other Data Input
Same Bit
Apply
4.5V
Apply
GND
Apply
4.5V
Apply
GND
Output
Under
Test
tpLH
tpHL
AI
Si
None
Remaining
AtoS
Cn
Fi
tpLH
tpHL
Si
Ai
None
Remaining
AtoS
Cn
Fi
tpLH
tpHL
Ai
Si
None
Cn
Remaining
AandS
Fi+ 1
tpLH
tpHL
Si
Ai
None
Cn
Remaining
Aand8
Fi+1
tpLH
tpHL
A
8
None
None
Remaining
Aand8, Cn
p
tpLH
tpHL
8
A
None
None
Remaining
Aand8, Cn
p
tpLH
tpHL
A
None
8
Remaining
8
Remaining
A,Cn
G
tpLH
tpHL
8
None
A
Remaining
8
Remaining
A,C n
G
tpLH
tpHL
A
None
8
Remaining
8
Remaining
A,Cn
Cn + 4
tpLH
tpHL
8
None
A
Remaining
8
Remaining
A,Cn
Cn + 4
tpLH
tpHL
Cn
None
None
All
A
All
8
AnyF
orCn + 4
DIFF MODE TEST TABLE II. Function Inputs: 81 = 82 = 4.5V,80 = 83 = M = OV
Symbol
Input
Under
Test
Other Input
Other Data Inputs
Same Bit
Apply
4.5V
Apply
GND
Apply
4.5V
Apply
GND
Output
Under
Test
tpLH
tpHL
A
None
8
Remaining
A
Remaining
8,C n
Fi
tpLH
tpHL
8
A
None
Remaining
A
Remaining
8,Cn
Fi
tpLH
tpHL
Ai
None
81
Remaining
B,Cn
Remaining
A
FI+ 1
tpLH
tpHL
BI
AI
None
Remaining
B,C n
Remaining
A
FI+ 1
tpLH
tpHL
A
None
B
None
Remaining
AandB,Cn
p
tpLH
tpHL
B
A
None
None
Remaining
AandB, Cn
p
tpLH
tpHL
A
8
None
None
Remaining
Aand8,Cn
G
3-147
•
DIFF MODE TEST TABLE II. Function Inputs: 81 = 82 = 4.5V.80 = 83 = M = OV (Continued)
Symbol
Input
Under
Test
Other Input
Same Bit
Apply
Other Data Inputs
Apply
GND
Apply
4.5V
4.5V
Apply
GND
Output
Under
Test
tpLH
tpHL
B
None
A
None
Remaining
AandB, Cn
G
tpLH
tpHL
A
None
B
Remaining
A
Remaining
B,Cn
A=B
tpLH
tpHL
B
A
None
Remaining
A
Remaining
B,Cn
A=B
tpLH
tpHL
A
B
None
None
Remaining
AandB,C n
Cn + 4
tpLH
tpHL
B
None
A
None
Remaining
AandB,Cn
Cn + 4
tpLH
tpHL
Cn
None
None
All
AandB
None
Cn + 4
LOGIC MODE TEST TABLE III. Function Inputs: 81 = 82 = M = 4.5V, SO = S3 = OV
Symbol
Input
Under
Test
Other Input
Same Bit
Apply
Other Data Inputs
Apply
GND
Apply
4.5V
4.5V
Apply
GND
Output
Under
Test
tpLH
tpHL
A
B
None
None
Remaining
AandB, Cn
AnyF
tpLH
tpHL
B
A
None
None
Remaining
AandB, Cn
AnyF
3-148
~National
~ Semiconductor
DM93S43
4-Bit by 2-Bit Twos Complement Multiplier
General Description
The DM93843 is a high-speed twos complement multiplier.
The device is a 4-bit by 2-bit building block that can be
connected in an iterative array to perform multiplication of
two binary numbers of variable lengths. The device can generate the twos complement product, without correction, of
two binary numbers presented in twos complement notation.
Connection Diagram
Logic Symbol
Dual·ln·Llne Package
X4
24
Vee
Cn
2
23
Y-l
X3
3
22
YO
X2
Yl
Xl
P
XO
Kl
50
K2
51
K3
S2
55
S3
54
13
23
Y-l
22
YO
6
5
4
3
1 19 18 17 16
21
KO
X-I
GND
7
Cn+4
13
2
20
50
51
8
52
10
53
54
55
11
14
15
TLlF/9806-2
vee = Pin 24
Cn+4
GND
= Pin 12
TL/F/9606-1
Order Number DM93S43N
See NS Package Number N24A
Description
Pin Name
X-I, X3, X4,
XO,Xl,X2
VO,V-l,Vl
Cn
KO-KS
j5
80-85
Cn+4
Multiplicand Inputs
Multiplier Inputs
Carry Input
Constant Inputs
Polarity Control Input (Active
Low for High Operands)
Product Outputs
Carry Output
3-149
•
Absolute Maximum Ratings
(Note)
It Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
DM93S
Storage Temperature Range
O'Cto +70'C
- 65'C to + 150'C
Recommended Operating Conditions
Symbol
DM93S43
Parameter
Units
Min
Nom
Max
4.75
5
5.25
V
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
0.8
V
10H
High Level Output Current
-1
mA
10L
Low Level Output Current
20
mA
TA
Free Air Operating Temperature
70
'C
2
V
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
=
=
Min
Typ
(Note 1)
Max
Units
-1.2
V
VI
Input Clamp Voltage
Vee
VOH
High Level Output Voltage
Vee = Min, 10H
VIL = Max
=
Max
VOL
Low Level Output Voltage
Vee = Min, 10L
VIH = Min
=
Max
II
Input Current @ Max
Input Voltage
Vee
=
Max, VI
=
5.5V
IIH
High Level Input Current
Vee
Max, VI
40
p.A
Low Level Input Current
Vee
=
=
2.7V
IlL
0.5V
-1.6
mA
los
Short Circuit Output Current
Vee
=
=
=
-100
mA
149
mA
Min,ll
Max, VI
-18 mA
2.7
3.4
0.35
-40
Max (Note 2)
Supply Current
Vee = Max
lee
Note 1: Aillypicals are at Vee = 5V, TA = 25'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
V
0.5
V
1
mA
Switching Characteristics
Vee
=
+ 5.0V, T A
Symbol
=
+ 25'C (See Section 1 for waveforms and load configurations)
CL
Parameter
Min
=
15pF
Units
Max
tpLH
tpHL
Propagation Delay
Cn toCn +4
9.0
9.0'.
ns
tpLH
tpHL
Propagation Delay
CntoSo-Sa
13
11
ns
tpLH
tpHL
Propagation Delay
Cn toS4,S5
16
15
ns
3-150
Switching Characteristics
Vee =
+ 5.0V, TA
Symbol
=
+ 25'C (See Section 1 for waveforms and load configurations) (Continued)
CL = 15pF
Parameter
Min
Units
Max
tpLH
tpHL
Propagation Delay
kntoCn +4
12
13
ns
tpLH
tpHL
Propagation Delay
kntoSO - S3
14
12
ns
tpLH
tpHL
Propagation Delay
kn toS4, S5
19
17
ns
tpLH
tpHL
Propagation Delay
xn to Cn + 4
15
24
ns
tpLH
tpHL
Propagation Delay
xn to SO - S3
25
25
ns
tpLH
tpHL
Propagation Delay
xnto S4, S5
30
21
ns
tpLH
tpHL
Propagation Delay
yntoC n +4
25
27
ns
tpLH
tpHL
Propagation Delay
yn to SO - S3
28
27
ns
tpLH
tpHL
Propagation Delay
ynto S4, S5
32
30
ns
Functional Description
The DM93S43 is a super fast hardware multiplier employing
Schottky technology and twos complement arithmetic. It
multiplies a multiplicand of four bits by a multiplier of two bits
and forms a basic iterative logic cell. It can also multiply in
active HIGH (positive logic) or active LOW (negative logic)
representations by reinterpreting the active levels of the inputs, outputs and the Polarity Control (P). The binary number with 1 as the most significant bit is treated as a negative
number represented in twos complement form. These
DM93S43 iterative logic cells can be connected to imple-
ment multiplication of an X-bit number by a V-bit number.
This application requires X • Y + 4 • 2 packages and the
resulting product has X + Y bits. At the beginning of the
array, a constant can be presented at the K inputs that will
be added to the least significant part of the product. The
packages can be connected in parallel, triangular or split-array scheme depending on the speed requirement. The '41
ALU can be used with these multipliers in the split-array
scheme to obtain high speed multiplication.
3-151
~ .---------------------------------------------------------------------~
~
TABLE I. Switching Test Conditions
~
G)
Input'
InputsatOV
(Remaining Inputs at 4.5 V)
Outputs
en
en + 4, 50 - 53, 54, 55
P,y-l,yl All x
kO
kl
k2
k3
k3
en + 4, 50 - 53, 54, 55
en + 4,51 - 53,54,55
en + 4, 52, 53, 54, 55
53
54,55
P,y-l,yl
i>; y-l, yl
i>;y-1,yl
i>;y-l,yl
P, y-l, yl
x-l
xO
xl
x2
x3,x4
x3,x4
x3,x4
en + 4, 50 - 53, 54, 55
en + 4, 50 - 53, 54, 55
en + 4, 51 - 53, 54, 55
en + 4, 52, 53, 54, 55
53
54,55
54,55
P, y-l, yl, All k
P, y-l, yl, All k
P, y-l, yl, All k
P, y-l, yl, All k
P, y-l, yl, All k, en
P, y-l, All k, en
y-l
yO
yl
en + 4, 50 - 53, 54, 55
en + 4, 50 - 53, 54, 55
en + 4, 50 - 53, 54, 55
All x
All x
All x
All x
All x, en
P,y-l,AII k
P, Xl, x2, x3, x4, All k
P, xl, x2, x3, x4, All k
xO, xl, x2, x3, x4, All k
Logic Diagram
55
TLiF/980B-3
3-152
~National
~ Semiconductor
DM93S46
High-Speed 6-Bit Identity Comparator
General Description
The DM93S46 is a very high speed 6-bit identity comparator. The device compares two words of up to six bits and
indicates identity in less than 12 ns. It is easily expandable
to any word length by using either serial or parallel expansion techniques. When the Enable input (E) is LOW, it
forces the output LOW.
Connection Diagram
Logic Symbol
Dual-in-Line Package
AO- 1
'-../
16 -Vee
15 -85
80- 2
Al- 3
91- 4
A2-5
14 -AS
13 -94
82- 6
11 r-83
E- 7
10 r- A3
GND- 8
12
AO 80 AI 81 A2 82 A3 83 Ao4 84 AS 85
7- E
A=8
~A4
TL/F/9B07-2
9 r-A=8
Vee = Pin 16
GND = Pln18
TL/F/9B07-1
Order Number DM93S46N
See NS Package Number N16E
Pin Name
AO-A5
80-85
E
A=8
Description
Word A Inputs
Word 8 Inputs
Enable Input (Active High)
A Equal to 8 Output
•
3-153
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Ottlce/Dlstrlbutors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
DM93S
Storage Temperature Range
O'Cto +70'C
- 65'C to + 150'C
Recommended Operating Conditions
Symbol
DM93S46
Parameter
Units
Min
Nom
Max
4.75
5
5.25
V
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
0.8
V
10H
High Level Output Current
-1
mA
10L
Low Level Output Current
20
mA
TA
Free Air Operating Temperature
70
'C
V
2
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 1)
Max
Units
-1.2
V
VI
Input Clamp Voltage
Vee = Min, 11= - 18 mA
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
VIL = Max
VOL
Low Level Output
Voltage
Vee = Min, 10L = Max
VIH = Min
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 5.5V
ilH
High Level Input Current
Vee = Max, VI = 2.7V
50
/LA
IlL
Low Level Input Current
Vee = Max, VI = 0.5V
-20
mA
los
Short Circuit
Output Current
Vee = Max
(Note 2)
-100
mA
70
mA
2.7
3.4
V
0.35
-40
0.5
V
1
mA
Supply Current
Vee = Max
Icc
Note 1: All typical. are at Vee = SV. TA = 2S'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Switching Characteristics
Vee = + 5.0V, T A = + 25'C (See Section 1 for waveforms and load configurations)
Symbol
Parameter
Conditions
CL = 15pF
Min
Max
Units
tpLH
tpHL
Propagation Delay
AnorBntoA = B
E = 4.5V, Other Inputs = 4.5V,
Test Each Input Individually
3.0
3.0
17
tpLH
tpHL
Propagation Delay
AnorBntoA = B
E = 4.5V, Other inputs = Gnd,
Test Each Input Individually
3.0
3.0
14
15
ns
tpLH
tpHL
Propagation Delay
EtoA = B
An = Bn
2.0
2.0
10
10
ns
3-154
17
ns
Truth Table
Functional Description
The DM93S46 is a very high speed 6-bit identity comparator. The A = B output is HIGH when the Enable (E) is HIGH
and the two 6-bit words are equal. Equality is determined by
Exclusive-NOR circuits which individually compare the
equivalent bits from each word. When any two of the equivalent bits from each word have different logic levels, the A
= B output is LOW.
(A = B) = (AO Ell BO) • (A~) • (A2 Ell B2) •
(A3 Ell B3) • (A4 Ell B4) • (A5 Ell B5) • E
Output
Inputs
E
A=B
An,Bn
L
L
H
H
An =
An*
An*
An =
L
L
L
H
8n
8n
8n
8n
H = HIGH Voltage Level
L = LOW Voltage Level
An active HIGH Enable (E) provides a means of fast ripple
expansion. By connecting the A = B output of the first
stage of the comparator to the enable of the next stage, the
comparator can be expanded in S-bit increments at an addtional 4.5 ns per stage. An even faster expansion technique
is achieved by connecting the A = B outputs to a Schottky
NAND gate. This method compares two words of up to 76
bits each in 15 ns (typical) using the '133 13-input Schottky
NAND gate.
Logic Diagram
AOBO
At Bt
A2B2
A3B3
MB4
ASB5
E
..LL..LL..LL.ll..LL..LL
A=B
TLlF/9BD7-5
•
3-155
Ripple Expansion
AO
eo
AS 85
A6 B6
•
93546
93546
A=B
A=B
A11B11
A12 812 • • • • • • • • • • • • A17 817
(A=B)'E
TL/F/9807-3
Note: This simple method of expansion adds 4.5 ns for each additional '46 used.
AU BO
AS B5
A6 B6
••••••
A11 811
A12 812 • • • • • • • • • • • • AI7 817
TL/F/9B07-4
Note: This method of expansion adds one gate delay ('" 3 ns) to the '46, independent of the word length that is compared.
3·156
~National
~ Semiconductor
DM93S47
High Speed 6-Bit Identity Comparator
General Description
The DM93S47 Is a very high speed 6-blt Identity comparator. The device features an open-collector output for wiredOR expansion and active LOW enable. The DM93S47 Is
fabricated with the Schottky barrier diode process for high
speed, and is completely compatible with all TTL families.
This device Is recommended for applications where wiredOR expansion Is desired and the speed of an active pull-up
Is not required. The DM93S47 Is a pln-for-pln replacement
for the DM7160/B160.
Connection Diagram
Logic Symbol
Iii iii If VYYIi Ii
Dual-In-Llne Package
AO- 1
BO- 2
'-'
AlBlA2B2-
3
4
5
6
14 :-A5
13 -B4
12 :-A4
lli-B3
E:-
7
10 i-A3
9 i-A=B
GND- 8
AO 80 AI Bl A2 B2 A3 83 A4 84 AS B5
16 -Vee
15 -B5
7-0
E
A=8
vee
= Pin 16
GND = Pin 8
TL/F/9808-1
Order Number DM93S47N
See NS Package Number N16E
Truth Table
Inputs
Output
A=B
E
L
L
H
H
H
L
An =
An
An.,o
An =
*
Bn
Bn
Bn
Bn
= HIGH Voltage Level
= LOW Voltage Level
3-157
H
L
H
H
TL/F/9BOB-2
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" fable will define
the conditions for actual device operation.
If Military/Aerospace specified devlcea are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
Input Voltage
Operating Free Air Temperature
Range (DM93S)
Storage Temperature Range
7V
5.5V
O'CIo +700C
-65'C to + 1500C
Recommended Operating Conditions
Symbol
DM93S47
Parameter
Vee
Supply Voltage
VIH
High Level Input Current
Units
Min
Nom
Max
4.75
5
5.25
V
V
2
VIL
Low Level Input Current
0.8
V
10H
High Level Output Current
-1
rnA
20
mA
70
·c
10L
Low Level Output Current
TA
Free Air Operating Temperature
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
= Min, II = -18mA
= Max,
Min
Typ
(Note 1)
Max
Units
-1.2
V
VI
Input Clamp Voltage
Vee
VOH
High Level Output
Voltage
Vee = Min,loH
VIL = Max
VOL
Low Level Output
Voltage
Vee = Min, 10H
VIH = Min
II
Input Current @ Max
Input Voltage
Vee
IIH
High Level Input Current
Vee
50
p.A
IlL
Low Level Input Current
Vee
-2.0
mA
los
Short Circuit Output Current
-100
mA
65
rnA
2.7
= Max,
0.35
= Max, VI = 5.5V
= Max, VI = 2.7V
= Max, VI = 0.5V
Vee = Max (Note 2)
Vee = Max
-40
Supply Current
Note 1: All typIcals are at Vee = 5V, TA = 25'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
lee
3-158
3.4
V
0.5
V
1
mA
.-----------------------------------------------------------------------------,
Switching Characteristics
Vee = + 5.0V, TA = + 25'C (See Section 1 for Waveforms and Load Configurations)
Symbol
Parameter
:e;
CL = 15 pF, RL = 2800
Conditions
Min
Max
Units
tpLH
tpHL
Propagation Delay
AnorBntoA = B
E = GND, Other Inputs = 4.5V,
Test Each Input Individually
5.0
5.0
17
tpLH
tpHL
Propagation Delay
AnorBntoA = B
E = GND, Other Inputs = GND,
Test Each Input Individually
4.0
4.0
14
15
ns
tpLH
tpHL
Propagation Delay
EtoA = B
An"'" Bn
3.0
3.0
10
10
ns
Functional Description
~
Co)
en
ns
17
Logic Diagram
The DM93S47 is a very high speed 6-bit identity comparator. When enabled (E input LOW), the A = B output is HIGH
if the two 6-bit words are equal. When disabled (E input
HIGH), the A = B output is forced HIGH. Equality is determined by Exclusive-NOR circuits which individually compare
the equivalent bits from each word. Since the A = B output
state is determined by the equality of each pair of inputs, the
equivalent An and Bn pins can be interchanged to facilitate
board layout or wiring. The active LOW Enable (E) can be
used as a high speed strobe. When the Enable is HIGH, the
A = B output is forced HIGH. This allows devices tied to a
common wired-OR (actually wired-AND) node to be strobed
individually or in groups. Only the enabled devices will determine the state of the output node.
AO 80
A181
A2 82
A383
A484
A585
ililil..LLilil
(A = B) = E + (AO e BO) • (A1 e B1) • (A2 e B2) •
(A3 e B3) • (A4 e B4) • (A5 e B5)
A=8
TL/F/9BOB-3
&I
3-159
I '?A
National
~ Semiconductor
DM93S62
9-lnput Parity Checker/Generator
General Description
The DM93S62 Is a very high speed 9·lnput parity checkerl
generator for use In error detection and error correction ap·
pllcatlons. The DM93S62 provides odd and even parity for
up to nine data bits. The even parity output (PE) Is HIGH If
an even number of Inputs are HIGH and 'E Is LOW. The odd
parity output (PO) will be HIGH If an odd number of Inputs
are HIGH and 'E Is LOW. A HIGH level on the Enable ('E)
Input forces both outputs LOW.
Connection Diagram
Logic Symbol
Iii i 'i 'l"i 'i i
Dual·ln-Llne Package
10-1
11- 2
12- 3
13- 4
18- 5
po-
6
GND- 7
\...../
14 -Vee
13.-17
12,...,6
8~ E
" .... ,5
101-14
9,...PE
81-[
PO
PE
TL/F/9809-2
Vee = Pln14
GND = Pin 7
TL/F/9809-1
Order Number DM93S62N
NS Package Number N14A
Pin Name
Description
Data Inputs
Output Enable (Active Low)
Odd Parity Output
Even Parity Output
10-18
'E
PO
PE
Truth Table ('E =
LOW)
Number of Inputs
Outputs
10-18 that are HIGH
PO
PE
1,3,5,7,9
H
L
L
H
0,2,4,6,8
H = HIGH Voltage Level
L = LOW Voltage Level
3·160
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
Operating Free Air Temperature Range
DM93S
Storage Temperature Range
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaran·
teed. The device should not be operated at these limits. The
parametric values defined in the "£Iectrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
5.5V
O·Cto +70·C
- 65·C to + 150·C
Recommended Operating Conditions
Symbol
DM93S62
Parameter
Units
Min
Nom
Max
4.75
5
5.25
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
O.S
V
V
2
V
10H
High Level Output Current
-1
mA
10L
Low Level Output Current
20
mA
TA
Free Air Operating Temperature
70
·c
0
Electrical Characteristics Over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 1)
Max
Units
-1.2
V
VI
Input Clamp Voltage
Vee = Min,ll = -1SmA
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
VIL = Max
VOL
Low Level Output
Voltage
Vee = Min, IOL = Max
VIH = Min
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 5.5V
IIH
High Level Input Current
Vee = Max, VI = 2.7V
IlL
Low Level Input Current
Vee = Max, VI = 0.5V,10-IS
-1.6
Vee = Max, VI = 0.5V, E Only
-3.2
lOS
Short Circuit
Output Current
Vee = Max
(Note 2)
Icc
Supply Current
Vee = Max
2.7
0.35
-40
V
3.4
0.5
V
1
mA
50
".A
mA
-100
mA
65
mA
Note 1: All typicals are at Vee = SV, TA = 2S'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
&I
3·161
N
I
Switching Characteristics
Vee =
+ S.OV, TA = + 2S'C (See Section 1 for waveforms and load configurations)
Symbol
CL = 1SpF
Parameter
Min
Units
Max
tpLH
tpHL
Propagation Delay
10-17 to PE
26
22
ns
tpLH
tpHL
Propagation Delay
IBto PE
12
9.0
ns
tpLH
tpHL
Propagation Delay
10-17 to PO
26
26
ns
tpLH
tpHL
Propagation Delay
IB to PO
13
13
ns
tpLH
tpHL
Propagation Delay
EtoPE
7.0
7.0
ns
tpLH
tpHL
Propagation Delay
EtoPO
7.0
7.0
ns
Functional Description
The DM93S62 is a very high speed 9-input parity checker or
generator. It is intended primarily for error detection in systems which transmit data in B-bit bytes, but it can be expanded to any number of data inputs. Both even and odd
parity outputs are available to allow maximum flexibility for
both parity generation and parity checking. When the device
is enabled (E = LOW), the Even Parity output (PE) Is HIGH
when an even number of inputs is HIGH, and the Odd Parity
output (PO) is HIGH when an odd number of Inputs is HIGH.
The active LOW Enable (E) controls the state of both outputs; when the Enable (E) is HIGH, both outputs will be
LOW. The Enable may be used to strobe the outputs at very
high speeds to synchronize or inhibit the parity data.
The DM93S62 has been designed with two sections using
Exclusive-NOR comparison techniques. Eight data inputs
10-17 represent one section which will generate a parity bit
in 16 ns to 20 ns. The ninth input (IB) bypasses three levels
of logic and switches the outputs in 6.0 ns to 9.0 ns. This
feature may be used to compensate for delayed arrival of
the parity bit, allowing faster system cycle times (Figure a).
The fast IB input is also useful when more than nine bits are
to be checked. The output of one DM93S62 drives the IB
input of a second DM93S62, providing a 17-bit parity check
in 29 ns (typ).
When some inputs of the DM93S62 are not used, such as
for words of less than nine bits or when using parallel expansion techniques, there is an optimum delay scheme for
termination of the unused inputs (see Table II). In essence,
if one of the inputs of any Exclusive-NOR stays HIGH, the
delay from the other input to the output is minimized.
3-162
TABLE II. Termination Recommendations for Less than Nine Bits
Number of
Data Inputs
10
11
12
13
14
15
16
17
18
3
4
5
00
00
00
L
L
L
01
01
01
L
L
L
02
02
02
L
L
L
L
03
03
L
L
L
L
L
04
6
00
00
00
01
01
01
02
02
02
03
03
03
04
04
04
L
L
05
05
05
06
L
L
07
L
06
L
7
B
AO
AO
AI
AI
A2
A2
A3
A3
M
A4
AS
AS
A6
A6
A7
A7
I
rr
-
10 11 12 13 14 15 16 17 18
1-
-
10 11 12 13 14 15 16 17 18
r
DM93S62
PO
I
TRANSM ISSION
MEDIUM
DM93S62
E
-
PE
I
DELAYED
PARITY
INPUT
PO
PE
I
I
CHECKER
ERROR
FLAG
TL/F/9809-3
FIGURE a. Fast Input 18 allows Higher System Speed
•
3·163
i
Logic Diagram
IO~
11~
12~
13~
PE
14~
15~
PO
16~
17~
18
PO =(10 ~ 11 ~ 12 ~ 13 ~ 14 ~ 15 ~ 16 ~ 17 ~ 18) •
PE=(l0~11~12~13~14~15~16~17~18).
E
E
TL/F/9609-4
3·164
r--------------------------------------------------------------------------------, en
U)
(J)
~National
;G
~ Semiconductor
DM96S02
Dual Retriggerable Resettable
Monostable Multivibrator
General Description
The DM96S02 is a dual retriggerable and resettable monostable multivibrator. This one-shot provides exceptionally
wide delay range, pulse width stability, predictable accuracy
and immunity to noise. The pulse width is set by an external
resistor and capacitor. Resistor values up to 2.0 MO for the
DM96S02 reduce required capacitor values. Hysteresis is
provided on the positive trigger input of the DM96S02 for
increased noise immunity.
Connection Diagram
Logic Symbol
Vee
Dual·ln·Llne Package
16
1
16 r-Vee
RX1 -
2
I:D,-
3
01- 6
15 r-Cn
14 r-RX2
13 r-C D2
12 r-11
11 r- To
01-
7
10 r-02
GND- 8
9 r-02
CX1 -
11- 4
To- 5
o ~6(10)
(12)~:dJ
(11)5
-.-/ T
o P-7(9)
TL/F/9810-1
Order Number DM96S02N
See NS Package Number N16E
TL/F/9810-2
vcc
GND
= Pin 16
= Pin 8
Triggering Truth Table
Pin Names
10
11
Co
Q1-2
Q1-2
CX1,2
RX1,2
Description
Trigger Input (Active Falling Edge)
Schmitt Trigger Input (Active Rising-Edge)
Direct Clear Input (Active LOW)
True Pulse Output
Complementary Pulse Output
External Capacitor Connection
External Resistor Connection
5(11)
Pin Number
4(12)
H-L
H
L
L-H
X
X
3(13)
H
H
L
H = HIGH Voltage Level:' VIH
L = LOW Voltage Level ,,; VIL
x = Immaterial (either H or L)
H -+ L = HIGH 10 LOW Voltage LevellranBlllon
L -+ H = LOW 10 HIGH Voltage Level transition
3-165
Operation
Trigger
Trigger
Reset
•
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
Operating Free Air Temperature Range
Storage Temperature Range
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
5.5V
O'Cto +70'C
- 65'C to + 150'C
Recommended Operating Conditions
Symbol
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
Conditions
Min
Nom
Max
Units
4.75
5
5.25
V
2
V
VIL
Low Level Input Voltage
0.8
V
10H
High Level Output Current
-1
mA
20
mA
70
'C
2.0
V
10L
Low Level Output Current
TA
Free Air Operating Temperature
VT+
Positive-Going Threshold
Voltage, io, 11
Vee
=
5.0V
VT-
Negative-Going
Threshold Voltage, i o• 11
Vee
=
5.0V
Vex
Capacitor Voltage
Pin 1 (15) Referenced
to Pin 2 (14)
Vee = 4.75V
to 5.25V
0
0.8
Rx = 1.0 kO,
Rx:2 10 kO,
Rx> 1.0MO
V
-0.85
-0.5
-0.4
3.0
3.0
3.0
V
Electrical Characteristics
OVer recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
=
=
Min
Typ
(Note 1)
Max
Units
-1.2
V
VI
Input Clamp Voltage
Vee
VOH
High Level
Output Voltage
Vee = Min,loH
VIL = Max
=
-1.0 mA,
VOL
Low Level
Output Voltage
Vee = Min, 10L
VIH = Min
=
Max,
II
Input Current @ Max
Input Voltage
Vee
=
Max, VI
=
5.5V
=
=
Max, VI
=
=
2.7V
20
/LA
0.4V
-1.0
mA
-100
mA
75
mA
Min,ll
IIH
High Level Input Current
Vee
IlL
Low Level Input Current
Vee
los
Short Circuit
Output CUrrent
Vee = Max
(Note 2)
Icc
Supply Current
Vee
=
Max, VI
-18 mA
2.7
0.35
-40
Max
3-166
3.4
V
0.5
V
1
mA
Switching Characteristics
Vcc = + 5.0V, TA = + 25'C (See Section 1 for waveforms and load configurations)
Symbol
Parameter
CL = 15pF
Conditions
Min
tpLH
Propagation Delay
10toQ
tpHL
Units
Max
Figures
15
ns
Propagation Delay
10toO
19
ns
tpLH
Propagation Delay
11 toQ
19
ns
tpHL
Propagation Delay
11 toO
20
ns
tpHL
Propagation Delay
CotoQ
20
ns
tpLH
Propagation Delay
CotoO
14
ns
tw(L)
10 Pulse Width LOW
8.0
ns
!w(H)
11 Pulse Width HIGH
12
ns
!w(L)
Co Pulse Width LOW
7.0
ns
!w(H)
Minimum Q Pulse Width HIGH
Rx = 1.0kO, Cx = 10pF
Including Jig and Stray
30
45
ns
!w
Q Pulse Width
Rx = 10 kO, Cx = 1000 pF
5.2
5.8
/Ls
Rx
Timing Resistor Range·
TA= -55'Cto+125'C
Vee = 4.5V to 5.5V
1.0
2000
kO
tAl
Change in Q Pulse Width
over Temperature
Rx = 10 kO, Cx = 1000 pF
1.0
%
tAv
Change in Q Pulse Width
over VCC Range
TA = 25'C, VCC = 4.75Vto
5.25V, Rx = 10 kO,
Cx = 1000pF
TA = 25'C, Vcc = 4.5V to
5.5V, Rx = 10 kO,
Cx = 1000pF
1.0
%
'Applies only over commercial Vee and TA range for OM96S02.
Note 1: All typicals are at Vee = 5V. TA = 25'C
Note 2: Not more than one output should be shorted at a time. and the duration should not exceed one second.
Switching Waveforms
iNPUT PULSE
100 kHz
Amp" 3.0V
Width" 100 ns
t, = tr:> 5ns
I ..
~oonsVIN
-f
I.SV
l,tpLH,
I.SV
Q
tw
Q
I.SV
tpHL
~
TLlF/9810-8
Flgurea.
3-167
•
I
Logic Diagram
, ,
,'-'
-,
GND8
~:'l!.0~:
TLlF/981 0-3
Typical Performance Characteristics
11 Delay Time
vsTA
Outputtw
vsRxandCx
103~.
I I I
17
,
~
!;
5
0
fa
Ycc=5.OV
11.=1 PF I I I ~
IPMi. - COIIPlEIIENT OUTPUT (il)
16
15
14
I I I
13
~,
S-
I I 1
12
i
IpLH TRUE OUTPUT (0)
11
10
o
I I I
-
50
25
75
tw - OUTPUT PULSE WlD1H - }.I'
TA - AMBIENT TENPERATURE - "C
..,
I'"
Normalized botw vs TA
104
+1.0
tCI8
+0&
Pulse Width vs RxCx
i
!!i
it
I,
Ii! -o.a
l
-1.0
0
25
50
TA - AMBIENT lEI1PWTURE - "C
75
10
nMING CAPACITOR
ex - pF
TL/F/9810-7
Functional Description
The 96S02 dual retriggerable resettable monostable multivibrator has two DC coupled trigger inputs per function, one
active LOW (TO) and one active HIGH (11). The 11 input utilizes an internal Schmitt trigger with hysteresis of 0.3V to
provide increased noise Immunity. The use of active HIGH
and LOW Inputs allows either rising or falling edge triggering
and optional non-retriggerable operation. The Inputs are DC
coupled making triggering independent of input transition
times. When input conditions for triggering are met the 0
output goes HIGH and the external capacitor is rapidly discharged and then allowed to recharge. An input trigger
which occurs during the timing cycle will retrigger the circuit
and result in 0 remaining HIGH. The output pulse may be
terminated (0 to the LOW state) at any time by setting the
Direct Clear input LOW. Retriggering may be inhibited by
tying the Q output to io or the 0 output to 11. Differential
sensing techniques are used to obtain excellent stability
over temperature and power supply variations and a feedback Darlington capacitor discharge circuit minimizes pulse
width variation from unit to unit. Schottky TTL output stages
provide high switching speeds and output compatibility with
all TTL logic families.
3-168
, - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - , U)
en
en
Operation Notes
TIMING
1. An external resistor (Rx) and an external capacitor (Cx)
are required as shown in the Logic Diagram. The value of
Rx may vary from 1.0 k!l to 2.0 M!l (DM96S02).
2. The value of Cx may vary from 0 to any necessary value
available. If, however, the capacitor has significant leakage relative to Vee/Rx the timing equations may not represent the pulse width obtained.
3. Polarized capacitors may be used directly. The ( +) terminal of a polarized capacitor is connected to pin 1(15), the
(-) terminal to pin 2(14) and Rx. Pin 1(15) will remain
positive with respect to pin 2(14) during the timing cycle.
However, during quiescent (non-triggered) conditions, pin
1(15) may go negative with respect to pin 2(14) depending on values of Rx and Vee. For values of Rx ~ 10 k!l
the maximum amount of capacitor reverse polarity, pin
1(15) negative with respect to pin 2(14) is 500 mV. Most
tantalum electrolytic capacitors are rated for safe reverse
bias operation up to 5% of their working forward voltage
rating; therefore, capaCitors having a rating of 10 WVdc
or higher should be used with the DM96S02 when Rx ~
10 k!l.
4. The output pulse width tw for Rx ~ 10 k!l and Cx ~
1000 pF is determined as follows:
tw = 0.55 RxCx
Where Rx is in k!l, Cx is in pF, t is in ns or RTX is in k!l,
Cx is in p.F, t is in ms.
5. The output pulse width for RX < 10 k!l or Cx < 1000 pF
should be determined from pulse width versus Cx or Rx
graphs.
6. To obtain variable pulse width by remote trimming, the
following circuit is recommended:
7. Under any operating condition, Cx and Rx (Min) must be
kept as close to the circuit as possible to minimize stray
capacitance and reduce noise pickup.
8. Vee and ground wiring should conform to good high frequency standards so that switching transients on Vee
and ground leads do not cause interaction between one
shots. Use of a 0.01 p.F to 0.1 p.F bypass capaCitor between Vee and ground located near the circuit is recommended.
TRIGGERING
1. The minimum negative pulse width into io is 8.0 ns; the
minimum positive pulse width into 11 is 12 ns.
2. Input signals to the DM96S02 exhibiting slow or noisy
transitions should use the positive trigger input 11 which
contains a Schmitt trigger. Input signals to the 96LS02
exhibiting slow or noisy transitions can use either trigger
as both are Schmitt triggers.
3. When non-retriggerable operation is required, i.e., when
input triggers are to be ignored during quasi-stable state,
input latching is used to inhibit retriggering.
4. An overriding active LOW level direct clear is provided on
each multivibrator. By applying a LOW to the clear, any
timing cycle can be terminated or any new cycle inhibited
until the LOW reset input is removed. Trigger inputs will
not produce spikes in the output when the reset is held
LOW. A LOW-to-HIGH transition on CD will not trigger the
DM96S02. If the CD input goes HIGH coincident with a
trigger transition, the circuit will respond to the trigger.
1.0k.n
PIN 2
(14)~--------------b
-L
PIN 1 (15)J
Rx-1.5k.n
'-AS CLOSE AS POSSIBLE
TO DEVICE
voco-----------------+
Cl
TUF/981 0-4
Rl
VCC
Q
OUTPUTIL
J
L
Q
OUTPUTIL
INPUT
INPUT
Q
Q
Co
NEGATIVE EDGE TRIGGER
POSITIVE EDGE TRIGGER
TUF/9810-5
3-169
TL/F/9810-6
S
I
I
I
I
i
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
i
I
I
I
I
I
Section 4
TTL
II
Section 4-TTL
TTL-Commercial Products
DM7400 Quad 2-lnput NAND Gate.. .. .•. .•.•. .•. .. .•.. .. .... .. .. .. •... •. .. . .. . . .•.•.
DM7401 Quad 2-lnput NAND Gate with Open-Collector Outputs.. .. .. .. ... . .... ..... .... .
DM7402 Quad 2-lnput NOR Gate. ... . . ... .. ... ..... .. .. .. .... .. ....... .... .. . .... ....
DM7403 Quad 2-lnput NAND Gate with Open-COllector Outputs ..... '...... . ... .. ... .. ....
DM7404 Hex Inverter ........•.•...•.............•...•............. " . . • . . . . • . . . . . . .
DM7405 Hex Inverter with Open-Collector Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7406 Hex Inverting Buffer/Driver with High-Voltage Open-Collector Outputs............
DM7407 Hex Buffer/Driver with High-Voltage Open-Collector Outputs. . . . . . . . . . . . . . . . . . . . .
DM7408 Quad 2-lnput AND Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7409 Quad 2-lnput AND Gate with Open-Collector Outputs.. .. . . ... . . . .. . . .. . .. ... . ..
DM7410 Triple 3-lnput NAND Gate.. . .. . ... .. ... .. ... ....... ... . . .. . . . .. .. ... .. ... ...
DM7411 Triple 3-lnput AND Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7414 Hex Schmitt Trigger Inverter . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7416 Hex Inverting Buffer/Driver with High-Voltage Open-Collector Outputs ............
DM7417 Hex Buffer/Driver with High-Voltage Open-Collector Outputs. . . . . . . .. . . . . . . . . . . . .
DM7420 Dual4-lnput NAND Gate....................................................
DM7425 Dual4-lnput NOR Gate with Strobe..... ... ...... . ... .. .. .. ... . .... .. ... .. ....
DM7426 Quad 2-lnput NAND Buffer with High-Voltage Open-Collector Outputs. . . . . . . . . . . . .
DM7427 Triple 3-lnput NOR Gate. .. . . . .. ...... ... .. .... .. .... ........ . ..... ... .. ....
DM7430 8-lnput NAND Gate .................. , ..... .... .. .... .... .... . . .............
DM7432 Quad 2-lnput OR Gate....... ............. .. .... . ..... ... .. ... . ... .. ........
DM7437 Quad 2-lnput NAND Buffer ............................................... '"
DM7438 Quad 2-lnput NAND Buffer with Open-Collector Output. . . . . . . . . . . . . . . . . . . . . . . . . .
DM7439 Quad 2-lnput NAND Buffer with Open-Collector Output. ... .. ... . .. . ... .. ..... ...
DM7440 Dual4-lnput NAND Buffer ........ , .. .... ......... .... .... . .. ... . . .. ... ... ...
DM7442A BCD to Decimal Decoder. ... ... ... ... .. ... ....... ... .. ... .... ... .. ........
DM7445 BCD to Decimal Decoder/Driver. . . . . . . .. . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . .
DM7446A BCD to 7-Segment Decoder/Driver with Open-Collector Outputs ..... '" ., ..... ,
DM7447A BCD to 7-Segment Decoder/Driver with Open-Collector Outputs. . . . . . . . . . . . . . . .
DM7450 Expandable Dual2-Wide 2-lnput AND-OR-INVERT Gate ........................
DM7451 Dual2-Wide 2-lnput AND-OR-INVERT Gate ...................................
DM7473 Dual Positive-Edge-Triggered Master-Slave J-K Flip-Flop with Clear and
Complementary Outputs ..........................................................
DM7474 Dual Positive-Edge-Triggered D Flip-Flop with Preset, Clear and Complementary
Outputs. . . . . . . . •. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7475 4-Bit Bistable Latch .................................................... , ....
DM7476 Dual J-K Flip-Flop with Preset and Clear...... .... .. .... ......... . .. . . . ........
DM7485 4-Bit Magnitude Comparator. .... .. .... .......... .. .... ..... ... . ... ... ... ....
DM7486 Quad 2-lnput EXCLUSIVE-OR Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . .
DM7490A Decade Counter. .... ....... . .. . ..... ... ........ ... .. .. .. ... . . ....... . . ...
DM7493A 4-Bit Binary Counter.. ....... . ... ...... ... ...... .... .. .. .. . ... . ....... .....
DM7495 4-Bit Parallel Access Shift Register. ...... ... .. .............. ... . ... . .. ... ....
DM7497 Synchronous Modulo 64 Bit Rate Multiplier ....................................
DM74121 Monostable Multivibrator (One-Shot) with Schmitt Trigger Input, Clear, and
Complementary Outputs .............................•............................
DM74122 Retriggerable Resettable Multivibrator (One-Shot) with Clear. . . . . . . . . . . . . . . . . . ..
4-3
4-5
4-7
4-9
4-11
d-13
4-15
4-17
4-19
4-21
4-23
4-25
4-27
4-30
4-32
4-34
4-36
4-38
4-40
4-42
4-44
4-46
4-48
4-50
4-52
4-55
4-58
4-61
4-61
4-66
4-69
4-72
4-75
4-78
4-81
4-87
4-91
4-94
4-94
4-101
4-104
4-116
4-120
Section 4-TTL (Continued)
TTL-Commercial Products (Continued)
DM74123 Dual Retriggerable Monostable Multivibrator (One-Shot) with Clear and
Complementary Outputs ......................................................... .
DM74125 Quad TRI-STATE Buffer .................................................. .
DM74132 Quad 2-lnput NAND Gate with Schmitt Trigger Inputs ......................... .
DM74145 BCD to Decimal Decoder/Driver ........................................... .
DM74150 1-of-16 Line Data Selector/Multiplexer ...................................... .
DM74151 A 1-of-8 Line Data Selector/Multiplexer with Complementary Outputs ........... .
DM74153 DuaI1-of-4 Line Data Selector/Multiplexer .................................. .
DM74154 4-to-16 Line Decoder/Demultiplexer ........................................ .
DM74155 DuaI2-to-4 Line Decoder/1-to-4 Line Demultiplexer .......................... .
DM74157 Quad 2-to-1 Line Data Selector/Multiplexer .................................. .
DM7 4161 A Synchronous 4-Bit Binary Counter with Asynchronous Clear .................. .
DM74163A Synchronous 4-Bit Binary Counter with Synchronous Clear ................... .
DM74164 8-Bit Serial In/Parallel Out Shift Register with Asynchronous Clear .............. .
DM74165 8-Bit Parallel-to-Serial Converter ........................................... .
DM74170 4-by-4 Register File with Open-Collector Outputs ............................. .
DM74173 4-BitTRI-STATE 0 Register ............................................... .
DM7 417 4 Hex 0 Flip-Flop with Clear ................................................. .
DM74175 Quad 0 Flip-Flop with Clear and Complementary Outputs ...................... .
DM74180 9-Bit Parity Generator/Checker ............................................ .
DM74184 BCD-to-Binary Converter .................................................. .
DM74185A Binary-to-BCD Converter ............................................... "
DM74191 Synchronous Up/Down 4-Bit Binary Counter with Mode Control ................ .
DM74197 Presettable Binary Counter ................................................ .
DM74279 Quad Set-Reset Latch ........................................... " ....... .
DM74283 4-Bit Binary Full Adder with Fast Carry ...................................... .
DM9300 4-Bit Positive-Edge-Triggered Parallel or Serial Access Shift Register ............ .
DM9301 1-of-10 Line Decoder ...................................................... .
DM9308 Dual 4-Bit Latch ........................................................... .
DM9309 DuaI1-of-4 Line Data Selector/Multiplexer with Complementary Outputs ......... .
DM9311 4-to-16 Line Decoder/Demultiplexer .....................................•....
DM9312 1-of-8 Line Data Selector/Multiplexer ................... '" ........ , ......... .
DM9314 Quad Latch ............................................................... .
DM9316 Synchronous 4-Bit Binary Counter .........................................•..
DM9318 8 to 3 Line Priority Encoder ................................................. .
DM9321 DuaI1-of-4 Decoder ....................................................... .
DM9322 Quad 1-of-2 Line Data Selector/Multiplexer ......... '" ................. " .... .
DM9324 5-Bit Comparator .......................................................... .
DM9328 Dual 8-Bit Shift Register ...................................................•.
DM9334 8-Bit Addressable Latch .........•.....•............................•........
DM9338 8-Bit Multiple Port Register ......•.•..................•..................•...
DM9368 7-Segment Decoder/Driver/Latch with Constant Current Source Outputs ......... .
DM9370 7-Segment Decoder/Driver/Latch with Open-Collector Outputs ........... " '" ..
DM9374 7-Segment Decoder/Driver/Latch with Constant Current Sink Outputs .•.•.••...••
DM9386 4-Bit Quad EXCLUSIVE-NOR with Open-Collector Outputs •....•....•...........
DM9601 Retriggerable Monostable Multivibrator (One-Shot) with Complementary Outputs ...
DM9602 Dual Retriggerable Monostable Multivibrator (One-Shot) with Complementary
Outputs ..................................•......................................
DM96101 Quad 2-lnput Positive NAND Buffer with Open-Collector Outputs ............... .
4-124
4-128
4-131
4-134
4-141
4-141
4-147
4-150
4-153
4-156
4-159
4-159
4-167
4-170
4-177
4-181
4-185
4-185
4-190
4-201
4-201
4-209
4-223
4-227
4-229
4-255
4-259
4-262
4-265
4-268
4-272
4-276
4-280
4-287
4-291
4-294
4-297
4-301
4-305
4-309
4-316
4-322
4-327
4-334
4-337
4-341
4-346
TTL-Mill Aero Products
5400/DM5400 Quad 2-lnput NAND Gate ............................................. .
DM5401 Quad 2-lnput NAND Gate with Open-Collector Outputs ......................... .
4-3
4-5
•
Section 4-TTL (Continued)
TTL-Mill Aero Products (Continued)
5402/DM5402 Quad 2-lnput NOR Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM5403 Quad 2-lnput NAND Gate with Open-Collector Outputs. . . . . . . . . . . . . . . . . . . . . . • . . .
5404/DM5404 Hex Inverter..... ........... ..... ..... ................... ....... . .. .. .
DM5405 Hex Inverter with Open-Collector Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM5406 Hex Inverting Buffer/Driver with High-Voltage Open-Collector Outputs ..•.........
DM5407 Hex Buffer/Driver with High-Voltage Open-Collector Outputs. . . . . . . . . . . . . . • . . . . . .
5408/DM5408 Quad 2-lnput AND Gate ...............................................
5409 Quad 2-lnput AND Gate with Open-Collector Outputs ..............................
541 0/DM541 0 Triple 3-lnput NAND Gate. . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . .
DM5414 Hex Schmitt Trigger Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM5416 Hex Inverting Buffer/Driver with High-Voltage Open-Collector Outputs ....•.......
DM5417 Hex Buffer/Driver with High-Voltage Open-Collector Outputs. . . • . . . • . . . . • . . . . . . . .
5420/DM5420 Dual 4-lnput NAND Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5425 Dual4-lnput NOR Gate with Strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM5426 Quad 2-lnput NAND Buffer with High-Voltage Open-Collector Outputs. . . . . . . . . . . . .
5430/DM5430 8-lnput NAND Gate .............................•.....................
5432/DM5432 Quad 2-lnput OR Gate. . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . .
5437/DM5437 Quad 2-lnput NAND Buffer. . . . . . • . . . . . . • . • . . . . . • • . . . . . . . . . • . • . . . . . . . . . .
DM5438 Quad 2-lnput NAND Buffer with Open-Collector Output. . . . • . • . . . . . . . . . . . . . . . . . . .
5440 Dual 4-lnput NAND Buffer . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . • . . . . • . • . . . . . . . . . . . . . .
5442A1DM5442A BCD to Decimal Decoder. • . . • . . . • . • . . • • • . . . . . . • . . . . . . . . • . . . . . . . . • . . .
DM5445 BCD to Decimal Decoder/Driver. . . . . . . . . • . . . . . . • . . . • . . . . •. . . •• . . . . . • . • • • . • •• .
DM5447A BCD to 7 -Segment Decoder/Driver with Open-Collector Outputs • . • . . • . . . • • . . . • .
5451 Dual2-Wide 2-lnput AND-OR-INVERT Gate .....•............•..•.•.•..•..••.....
5473/DM5473 Dual Positive-Edge-Triggered Master-Slave J-K Flip-Flop with Clear and
Complementary Outputs.... .•.. .•.. .•.••.•.. ....•.•.•...... ...•...•••.... ..••...•
5474/DM5474 Dual Positive-Edge-Triggered 0 Flip-Flop with Preset, Clear and
Complementary Outputs ................•............................•......•.•.••
5475/DM5475 4-Bit Bistable Latch ..................•....•..•••.......•.•..........••
5476/DM5476 Dual J-K Flip-Flop with Preset and Clear •....•......•.•.•..•.•..•...•....
5483A 4-Bit Binary Full Adder with Fast Carry .. . . . . . . . • . . . . • . . . • . . . . • . • . • • . • . • . • . . . . . . .
5485/DM5485 4-Bit Magnitude Comparator. . . . . . . . . . • . . . . . . • . • . . . . • . • . . . . . . • . • . . . . . . . .
5486/DM5486 Quad 2-lnput EXCLUSIVE-OR Gate . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . .
5490/DM5490A Decade Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . •
DM5493A 4-Bit Binary Counter. . . . . . . . . . . . . . . . . • . . . . . . . . . . • . . . . • . • . • . • . . . . • . . . • . • . . . .
5495A 4-Bit Parallel Access Shift Register...... . ... ...... .................. ...•.. .....
5497 Synchronous Modulo 64 Bit Rate Multiplier. .... .. ... ........................ .....
DM54107 Dual Master-Slave J-K Flip-Flop with Clear and Complementary Outputs. • . • . . . . .•
DM54109 Dual Positive-Edge-Triggered J-K Flip-Flops with Preset and Clear. . . . • . . . . . . . . ..
54121/DM54121 Monostable Multivibrator (One-Shot) with Schmitt Trigger Input, Clear, and
Complementary Outputs ...........................•..••.•.•....•........•........
54122 Retriggerable Resettable Multivibrator (One-Shot) with Clear......... ...•. .... ....•
54123 Dual Retriggerable Monostable Multivibrator (One-Shot) with Clear and
Complementary Outputs .•.............•......•.•...••...•.•..•.•.•...••.•..•.•.•.•
54125/DM54125 Quad TRI-STATE Buffer ..•........•..•...•...•..•...............•...
DM54132 Quad 2-lnput NAND Gate with Schmitt Trigger Inputs............. ....•......•.
DM54145 BCD to Decimal Decoder/Driver ............................................
DM54148 8-Line Decimal to 3-Line Octal Priority Encoder...............................
54150/DM54150 1-of-16 Line Data Selector/Multiplexer. . . . . . . . . . . .• • . . . . . . •. • . . . . . . • .•
54151 AlDM54151 A 1-of-8 Line Data Selector/Multiplexer with Complementary Outputs. . ...
54153/DM54153 DuaI1-of-4 Line Data Selector/Multiplexer ........••...•••.•.••.•...•..
54154/DM54154 4-to-16 Line Decoder/Demultiplexer ...................•.•.••.......•.
4-7
4-9
4-11
4-13
4-15
4-17
4-19
4-21
4-23
4-27
4-30
4-32
4-34
4-36
4-38
4-42
4-44
4-46
4-48
4-52
4-55
4-58
4-61
4-69
4-72
4-75
4-78
4-81
4-84
4-87
4-91
4-94
4-94
4-101
4-104
4-110
4-113
4-116
4-120
4-124
4-128
4-131
4-134
4-137
4-141
4-141
4-147
4-150
Section 4-TTL (Continued)
TTL-Mill Aero Products (Continued)
DM54155 DuaI2-to-4 Line Decoder/1-to-4 Line Demultiplexer .......................... .
54157/DM54157 Quad 2-to-1 Line Data Selector/Multiplexer ........................... .
54161 /DM54161 A Synchronous 4-Bit Binary Counter with Asynchronous Clear ........... .
DM54163A Synchronous 4-Bit Binary Counter with Synchronous Clear ................... .
54164 8-Bit Serial In/Parallel Out Shift Register with Asynchronous Clear ................. .
54165 8-Bit Parallel-to-Serial Converter .............................................. .
DM54166 8-Bit Parallel or Serial In/Serial Out Shift Register ............................ .
54170 4-by-4 Register File with Open-Collector Outputs ................................ .
54173/DM54173 4-Bit TRI-STATE D Register ......................................... .
5417 4/DM54174 Hex D Flip-Flop with Clear .......................................... .
54175/DM54175 Quad D Flip-Flop with Clear and Complementary Outputs ............... .
DM54180 9-Bit Parity Generator/Checker ............................................ .
DM54181 Arithmetic Logic Unit/Function Generator ................................... .
54191/DM54191 Synchronous Up/Down 4-Bit Binary Counter with Mode Control ......... .
DM54193 Synchronous Up/Down 4-Bit Binary Counter with Dual Clock ................... .
DM54194 4-Bit Bidirectional Universal Shift Register ................................... .
54279 Quad Set-Reset Latch ....................................................... .
54283 4-Bit Binary Full Adder with Fast Carry ......................................... .
54298 Quad 2-Port Register (Multiplexer with Storage) .........•........................
DM54365 Hex TRI-STATE Buffer/Bus Driver .......................................... .
DM54367 Hex TRI-STATE Buffer/Bus Driver ...............•............. , ....•.....•..
DM54368 Hex TRI-STATE Inverting Buffer/Bus Driver ........•.........................
DM7123 Quad TRI-STATE 1-of-2 Line Data Selector/Multiplexer ..............•..•.......
DM7130 1O-Bit Magnitude Comparator with Open-Collector Outputs ........•....•.....•..
DM7136 6-Bit Unified Bus Comparator with Open-Collector Outputs ....•....•....•........
DM7160 6-Bit Magnitude Comparator with Open-Collector Outputs ••.•.•....•..........•.
9300 4-Bit Positive-Edge-Triggered Parallel or Serial Access Shift Register ...•.............
9301 1-of-10 Line Decoder ..................•..............................•........
9308 Dual 4-Bit Latch .............................................................. .
9309 DuaI1-of-4 Line Data Selector/Multiplexer with Complementary Outputs ............ .
9311/DM9311 4-to-16 Line Decoder/Demultiplexer .................................... .
93121-of-8 Line Data Selector/Multiplexer ........................................... .
9314 Quad Latch .................................................................. .
9316/DM9316 Synchronous 4-Bit Binary Counter ...................................... .
9318/DM9318 8 to 3 Line Priority Encoder ............................................ .
9321 DuaI1-of-4 Decoder .......................................................... .
9322/DM9322 Quad 1-of-2 Line Data Selector/Multiplexer ............................. .
9324 5-Bit Comparator ............................................................. .
9328 Dual 8-Bit Shift Register ....................................................... .
9334/DM9334 8-Bit Addressable Latch .............................................. .
9338 8-Bit Multiple Port Register ..........................•..........................
9348 12-lnput Parity Checker/Generator. '" .............. " ......................... .
9601/DM9601 Retriggerable Monostable Multivibrator (One-Shot) with Complementary
Outputs ........................................................................ .
9602/DM9602 Dual Retriggerable Monostable Multivibrator (One-Shot) with Complementary
Outputs ........................................................................ .
4-153
4-156
4-159
4-159
4-167
4-170
4-173
4-177
4-181
4-185
4-185
4-190
4-193
4-209
4-214
4-219
4-227
4-229
4-233
4-236
4-239
4-242
4-245
4-248
4-250
4-253
4-255
4-259
4-262
4-265
4-268
4-272
4-276
4-280
4-287
4-291
4-294
4-297
4-301
4-305
4-309
4-313
4-337
4-341
•
o
o
~National
~ Semiconductor
5400/DM5400/DM7400
Quad 2-lnput NAND Gates
General Description
Features
This device contains four independent gates each of which
performs the logic NAND function.
• Alternate Military/Aerospace device (5400) is available.
Contact a National Semiconductor Sales Office/Distributor for specifications.
Connection Diagram
Dual-In-Llne Package
Vee
14
Al
B4
A4
13
V4
11
12
VI
81
B3
A2
A3
V3
V2
GND
10
B2
TLlF/6613-1
Order Number 5400DMQB, 5400FMQB, DM5400J, DM5400W or DM7400N
See NS Package Number J14A, N14A or W14B
Function Table
V= AB
Inputs
Output
A
B
V
L
L
H
H
L
H
L
H
H
H
H
L
H = High Logic Level
L
= Low Logic Level
•
4-3
8
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Input Voltage
5.5V
Operating Free Air Temperature Range
DM54 and 54
-55·Cto + 125·C
DM74
O·Cto +70·C
Storage Temperature Range
-65·Cto + 150"C
Recommended Operating Conditions
Symbol
DM5400
Parameter
DM7400
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
0.8
0.8
V
Vee
Supply Voltage
VIH
High Level Input Voltage
Vil
Low Level Input Voltage
10H
High Level Output Current
-0.4
-0.4
rnA
10l
Low Level Output Current
16
16
rnA
TA
Free Air Operating Temperature
70
·c
2
2
-55
125
V
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
=
Min,ll
=
Min
VI
Input Clamp Voltage
Vee
VOH
High Level Output
Voltage
Vcc = Min, 10H
Vil = Max
=
Max
VOL
Low Level Output
Voltage
Vee = Min, 10l
VIH = Min
=
Max
II
Input Current @ Max
Input Voltage
Vcc
=
Max, VI
= 5.5V
=
=
Max, VI
= 2.4V
Max, VI
=
IIH
High Level Input Current
Vcc
III
Low Level Input Current
Vcc
los
Short Circuit
Output Current
VCC = Max
(Note 2)
ICCH
Supply Current with
Outputs High
Vcc
=
Max
leel
Supply Current with
Outputs Low
Vcc
=
Max
Typ
(Note 1)
-12 rnA
2.4
Units
-1.5
V
3.4
V
0.2
0.4V
I
I
Max
0.4
V
1
mA
40
",A
-1.6
mA
DM54
-20
-55
DM74
-18
-55
mA
4
8
rnA
12
22
mA
Switching Characteristics at VCC = 5V and TA = 25·C (See Section 1 for Test Waveforms and Output Load)
Symbol
tplH
Parameter
Propagation Delay Time
Low to High Level Output
Conditions
Cl
Rl
= 15pF
= 4000
Propagation Delay Time
High to Low Level Output
Note 1: All typical. are at Vee - 5V, TA - 25·C.
tpHl
Note 2: Not more than one output should be shorted at a time.
4-4
Min
Max
Units
22
ns
15
ns
,-------------------------------------------------------------------------, 0
.....
~National
~ Semiconductor
DM5401/DM7401 Quad 2-lnput NAND Gates
with Open-Collector Outputs
General Description
Pull-Up Resistor Equations
This device contains four independent gates each of which
performs the logic NAND function. The open-collector outputs require external pull-up resistors for proper logical operation.
R
Vee (Min) - VOH
MAX = Nl (lOH) + N2 (lIH)
R
Vee (Max) - VOL
IOL - Na (11Ll
MIN =
Where: Nl (IOH) = total maximum output high current for all
outputs tied to pull-up resistor
N2 (IIH) = total maximum input high current for all
inputs tied to pull-up resistor
Na (lILl = total maximum input low current for all
inputs tied to pull-up resistor
Connection Diagram
Dual-In-Llne Package
V4
vee
14
VI
B4
A4
12
13
Bl
Al
V3
11
V2
B3
A3
B2
GNU
10
A2
Order Number DM5401J, DM5401W or DM7401N
See NS Package Number J14A, N14A or W14B
Function Table
v=
AB
Inputs
Output
A
B
V
L
L
H
H
L
H
L
H
H
H
H
L
H = High Logic Level
L = Low Logic Level
4-5
TL/F/6614-1
....o
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Input Voltage
5.5V
Output Voltage
7V
Operating Free Air Temperature Range
DM54
-55'Cto + 125'C
DM74
O'Cto +70'C
Storage Temperature Range
-65'C to + 150'C
Recommended Operating Conditions
Symbol
DM5401
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
DM7401
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
V
2
V
VIL
Low Level Input Voltage
0.8
0.8
VOH
High Level Output Voltage
5.5
5.5
V
IOL
Low Level Output Current
16
16
mA
TA
Free Air Operating Temperature
70
'C
-55
125
0
V
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
=
=
Typ
(Note 1)
Min
Max
Units
-1.5
V
250
/LA
0.4
V
1
mA
VI
Input Clamp Voltage
Vee
leEX
High Level Output
Current
Vee = Min, Vo
VIL = Max
=
5.5V
VOL
Low Level Output
Voltage
Vee = Min, IOL
VIH = Min
=
Max
II
Input Current @ Max
Input Voltage
Vee
=
Max, VI
=
5.5V
IIH
High Level Input Current
Vee
40
/LA
IlL
=
=
2.4V
Vee
=
=
Max, VI
Low Level Input Current
0.4V
-1.6
mA
leeH
Supply Current with
Outputs High
Vee
=
Max
4
8
mA
leeL
Supply Current with
Outputs Low
Vee
=
Max
12
22
mA
Min,ll
Max, VI
-12 mA
0.2
Switching Characteristics at Vee = 5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
tpLH
Propagation Delay Time
Low to High Level Output
tpHL
Propagation Delay Time
High to Low Level Output
Note 1: All typical. are al Yee
Conditions
CL
RL
RL
=
=
=
15pF
4 kO (tpLH)
4000 (tpHU
= 5Y, TA = 25·C.
4-6
Min
Max
Units
45
ns
15
ns
~National
~ Semiconductor
5402/DM5402/DM7402
Quad 2-lnput NOR Gates
General Description
Features
This device contains four Independent gates each of which
performs the logic NOR function.
• Alternate Mllltary/Areospace device (5402) Is available.
Contact a National Semiconductor Sales Office/Distributor for specifications.
Connection Diagram
Dual·ln·Llne Package
vee
14
VI
V4
84
11
12
13
83
A3
82
GND
10
A2
V2
81
AI
V3
A4
TlIF/6492-1
Order Number 5402DMQB, 5402FMQB, DM5402J, DM5402W or DM7402N
See NS Package Number J14A, N14A or W14B
Function Table
Y=A+B
Inputs
Output
A
B
Y
L
L
H
H
L
H
L
H
H
L
L
L
H = High Logic Level
L
= Low logic Level
4-7
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
DM54 and 54
- 55'C to + 125'C
DM74
O'Cto +70'C
Storage Temperature Range
-65'C to + 150'C
Recommended Operating Conditions
Symbol
DM5402
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
10H
High Level Output Current
DM7402
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
10L
Low Level Output Current
Free Air Operating Temperature
V
2
2
TA
Units
Min
V
0.8
0.8
V
-0.4
-0.4
mA
16
-55
125
0
16
mA
70
·c
Max
Units
-1.5
V
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
VI
Input Clamp Voltage
Vee = Min, 11= -12 mA
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
VIL = Max
VOL
Low Level Output
Voltage
Vee = Min, 10L = Max
VIH = Min
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 5.5V
IIH
High Level Input Current
IlL
Low Level Input Current
los
Short Circuit
Output Current
Vee = Max
(Note 2)
ICCH
Supply Current with
Outputs High
Vcc = Max
ICCL
Supply Current with
Outputs Low
Vee = Max
1
mA
Vee = Max, VI = 2.4V
40
/LA
Vee = Max, VI = O.4V
-1.6
mA
I
I
-20
-55
DM74
-18
-55
Propagation Delay Time
Low to High Level Output
CL = 15pF
RL = 4000.
tpHL
Propagation Delay Time
High to Low Level Output
~
mA
8
16
mA
14
27
mA
5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
tpLH
5V, TA
0.2
DM54
Conditions
~
V
V
Parameter
Note 1: All typlcals are at Vee
3.4
0.4
Switching Characteristics at Vee =
Symbol
2.4
Typ
(Note 1)
25"C.
Note 2: Not more than one output should be shorted at a time.
4-8
Min
Max
Units
22
ns
15
ns
,-------------------------------------------------------------------------, 0
Co)
~National
~ Semiconductor
DM5403/DM7403 Quad 2-lnput NAND Gates
with Open-Collector Outputs
General Description
Pull-Up Resistor Equations
This device contains four independent gates each of which
performs the logic NAND function. The open-collector outputs require external pull-up resistors for proper logical operation.
R
Vcc (Min) - VOH
+ N2 (IIH)
MAX = Nl (lOH)
--,VC",C:....:(,-M_ax"",)_-_V-,O<.=L
RMIN = IOL - Na (11Ll
Where: Nl (lOH) = total maximum output high current for all
outputs tied to pull-up resistor
N2 (IIH) = total maximum input high current for all
inputs tied to pull-up resistor
Na (11Ll = total maximum input low current for all
inputs tied to pull-up resistor
Connection Diagram
Dual-in-Line Package
vee
84
A4
V4
83
A3
V3
AI
81
VI
A2
82
V2
GND
Order Number DM5403J or DM7403N
See NS Package Number J14A or N14A
Function Table
y= AB
inputs
Output
A
B
Y
L
L
L
H
H
H
L
H
H
H
H
L
H
~
High Logic Level
L
~
Lew Logic Level
4-9
TLlF/6493-1
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table ara not guaranteed at the absolute maximum ratings.
The "Racommended Operating CondItIons" table will define
the conditions for actual device operatiOn.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Output Voltage
7V
Operating Free Air Temperature Range
DM54
-55'0 to +125'0
DM74
0'0 to +70'0
Storage Temperature Range
-65'0 to + 150'0
Recommended Operating Conditions
Symbol
DM5403
Parameter
DM7403
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
Vco
Supply Voltage
VIH
High Level Input Voltage
Vil
Low Level Input Voltage
0.6
0.8
V
VOH
High Level Output Voltage
5.5
5.5
V
16
mA
70
'0
IOl
Low Level Output Ourrent
TA
Free Air Operating Temperature
2
2
V
16
-55
125
0
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
=
=
Typ
(Note 1)
Min
Max
Units
-1.5
V
250
/Jo A
0.4
V
1
mA
VI
Input Olamp Voltage
Vee
leEX
High Level Output
Ourrent
Vee = Min, Vo
Vil = Max
=
5.5V
VOL
Low Level Output
Voltage
Vee = Min, IOl
VIH = Min
=
Max
II
Input Ourrent @ Max
Input Voltage
Vcc
=
Max, VI
=
5.5V
=
=
2.4V
40
/JoA
0.4V
-1.6
mA
4
8
mA
12
22
mA
Min. II
IIH
High Level Input Current
Vee
Low Level Input Current
Vee
=
=
Max, VI
III
ICCH
Supply Current with
Outputs High
Vee
=
Max
ICOl
Supply Current with
Outputs Low
Vee
=
Max
Max, VI
-12 mA
0.2
Switching Characteristics at Vee = 5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
tplH
Propagation Delay Time
Low to High Level Output
tpHL
Propagation Delay Time
High to Low Level Output
Conditions
Cl
Rl
RL
=
=
=
15pF
4 ko. (tpLH)
4000. (tpHU
Note 1: All typical. are at Vee - SV, TA - 2S'C.
4-10
Min
Max
Units
45
ns
15
ns
r---------------------------------------------------------------------~
J?A National
0
.co.
~ Semiconductor
5404/DM5404/DM7404
Hex Inverting Gates
General Description
Features
This device contains six independent gates each of which
performs the logic INVERT function.
• Alternate Military/Aerospace device (5404) is available.
Contact a National Semiconductor Sales Office/Distributor for specifications.
Connection Diagram
Dual-In-Line Package
Vee:
14
Al
A6
13
VI
AS
Y6
12
A2
YS
11
A4
Y4
Yl
GNU
10
Al
Y2
TL/F/6494-1
Order Number 5404DMQB, 5404FMQB, DM5404J, DM5404W, DM7404M or DM7404N
See NS Package Number J14A, M14A, N14A or W14B
Function Table
V=A
Inputs
Output
A
V
L
H
H
L
H = High Logic Level
L = Low Logic Level
•
4-11
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are thoss valuss
beyond which the safety of the device cannot be guarenteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Seles
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
- 55·C to + 125·C
DM54 and 54
DM74
O·Cto +700C
-65·Cto + 1500C
Storage Temperature Range
Recommended Operating Conditions
Symbol
DM5404
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
10H
High Level Output Current
DM7404
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
10L
Low Level Output Current
TA
Free Air Operating Temperature
Unite
Min
V
V
2
0.8
0.8
V
-0.4
-0.4
mA
16
-55
125
0
16
mA
70
·C
Max
Unite
-1.5
V
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
VI
Input Clamp Voltage
VOH
High Level Output
Voltage
VOL
Low Level Output
Voltage
II
Input Current @ Max
Input Voltage
IIH
High Level Input Current
IlL
Low Level Input Current
los
Short Circuit
Output Current
Conditions
Min
= Min,ll = -12 mA
Vee = Min, 10H = Max
VIL = Max
Vcc = Min, 10L = Max
VIH = Min
Vcc = Max, VI = 5.5V
Typ
(Note 1)
Vee
= Max, VI = 2.4V
Vee = Max, VI = 0.4V
DM54
Vee = Max I
2.4
3.4
V
0.2
Vee
(Note 2)
ICCH
Supply Current with
Outputs High
Vcc
= Max
leeL
Supply Current with
Outputs Low
Vee
= Max
I
DM74
0.4
V
1
mA
40
p.A
-1.6
mA
-20
-55
-18
-55
mA
6
12
mA
18
33
mA
Switching Characteristics at Vcc = 5V and TA = 25·C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
Conditions
tpLH
Propagation Delay Time
Low to High Level Output
CL=15pF
RL = 4000
tpHL
Propagation Delay Time
High to Low Level Output
Nole 1: All typlcals are at Vee - 5V, T... = 25'0.
Note 2: Not more than on. output should b. shorted at a time.
4-12
Min
Max
Unit.
22
ns
15
ns
r-------------------------------------------------------------------------,c
(II
~National
~ Semiconductor
DM5405/DM7405 Hex Inverters
with Open-Collector Outputs
General Description
Pull-Up Resistor Equations
This device contains six independent gates each of which
performs the logic INVERT function. The open-collector outputs require external pull-up resistors for proper logical operation.
R
Vee (Min) - VOH
MAX = Nl (lOH) + N2 (lIH)
R
MIN =
Vee (Max) - VOL
IOL - N3 (110
Where: Nl (lOH) = total maximum output high current for all
outputs tied to pull-up resistor
N2 (lIH) = total maximum input high current for all
inputs tied to pull-up resistor
N3 (110 = total maximum input low current for all
inputs tied to pull-up resistor
Connection Diagram
Dual-In-Line Package
Vee
14
Al
AS
V6
A6
12
13
A2
VI
VS
II
A4
V4
Y3
GND
10
Y2
A3
Order Number DM5405J, DM5405W or DM7405N
See NS Package Number J14A, N14A or W14B
Function Table
Y=A
Input
Output
A
Y
L
H
H
L
H = High Logic Level
L
= Low Logic Level
4-13
TL/F/6495-1
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Input Voltage
5.5V
Output Voltage
7V
Operating Free Air Temperature Range
DM54
-55'Cto +125'C
DM74
O'Cto +70'C
Storage Temperature Range
-65'Cto + 150'C
Recommended Operating Conditions
Symbol
DM5405
Parameter
DM7405
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
0.8
0.8
V
VOH
High Level Output Voltage
5.5
5.5
V
16
mA
70
'C
IOL
Low Level Output Current
TA
Free Air Operating Temperature
2
V
2
V
16
-55
125
0
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Typ
(Note 1)
Min
Max
Units
VI
Input Clamp Voltage
Vee = Min, II = -12 mA
-1.5
V
leEX
High Level Output
Current
Vee = Min, Vo = 5.5V
VIL = Max
250
/LA
VOL
Low Level Output
Voltage
Vee = Min, IOL = Max
VIH = Min
0.4
V
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 5.5V
1
mA
0.2
IIH
High Level Input Current
Vcc = Max, VI = 2.4V
40
/LA
IlL
Low Level Input Current
Vcc = Max, VI = O.4V
-1.6
mA
ICCH
Supply Current with
Outputs High
Vee = Max
6
12
mA
leeL
Supply Current with
Outputs Low
Vee = Max
18
33
mA
Switching Characteristics at Vee =
Symbol
5V and T A = 25'C (See Section 1 for Test Waveforms and Output Load)
Parameter
Conditions
tpLH
Propagation Delay Time
Low to High Level Output
tpHL
Propagation Delay Time
High to Low Level Output
CL = 15 pF
RL = 4 kn (tpLH)
RL = 4000, (tpHu
Note 1: All typical. are at Vee = 5V, TA = 25·C.
4-14
Min
Max
Units
55
ns
15
ns
~National
~ Semiconductor
DM5406/DM7406 Hex Inverting Buffers with
High Voltage Open-Collector Outputs
General Description
Pull-Up Resistor Equations
This device contains six Independent buffers each of which
performs the logic INVERT function. The open-collector outputs require external pull-up resistors for proper logical operation.
R
Vo (Min) - VOH
+ N2 (IIH)
MAX = N1 (lOH)
RMIN = Vo (Max) - VOL
IOL - Na (IIU
Where: N1 (lOH) = total maximum output high current for all
outputs tied to pull-up resistor
N2 (IIH) = total maximum input high current for all
inputs tied to pull-up resistor
Na (lIU = total maximum Input low current for all
inpuls lied 10 pull-up resistor
Connection Diagram
Dual-In-Llne Package
Vee
14
Al
AS
13
VI
AS
VS
12
A2
VS
11
A4
V4
V3
GND
10
V2
A3
TUF/6496-1
Order Number DM5406J, DM5406W, DM7406M or DM7406N
See NS Package Number J14A, M14A, N14A or W14B
Function Table
Y=A,
Input
Output
A
y
L
H
L
H
H = High Logic Level
L = Low Logic Level
4-15
Absolute Maximum Ratings (Note)
Note: Th6 "Absolut6 Maximum Ratings" ar6 thoS6 values
b6yOnd which the safety of th6 d6viC6 cannot b6 guarant66d. Th6 devic6 should not b6 Op6f8tfJd at th6se limits. The
paramfltric valu6s d6finfJd in the "EI6Ctrical Charact6ristics"
tabl6 am not guamnf6ed at the abSOlUt6 maximum ratings.
Th6 "R6comm6nded Operating Conditions" table will defin6
th6 conditions for actual d6viC6 operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and speclflcatlons_
Supply Voltage
7V
5.5V
Input Voltage
Output Voltage
30V
Operating Free Air Temperature Range
- 55·C to + 125·C
DM54
O·Cto +70"C
DM74
Storage Temperature Range
-65·C to + 150"C
Recommended Operating Conditions
Symbol
DM7406
DM5406
Parameter
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
V
Vcc
Supply Voltage
VIH
High Level Input Voltage
Vil
Low Level Input Voltage
0.8
0.8
VOH
High Level Output Voltage
30
30
V
IOl
Low Level Output Current
30
40
mA
TA
Free Air Operating Temperature
70
·c
2
2
-55
125
V
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
=
=
VI
Input Clamp Voltage
Vee
leEx
High Level Output
Current
Vee = Min, Vo
Vil = Max
=
30V
VOL
Low Level Output
Voltage
Vcc = Min,lOl
VIH = Min
=
Max
Min,ll
Typ
(Note 1)
Min
-12 mA
Input Current @ Max
Input Voltage
IIH
High Level Input Current
III
Low Level Input Current
= 16 mA, Vee = Min
Vee = Max, VI = 5.5V
ICCH
Supply Current with
Outputs High
leel
Supply Current with
Outputs Low
=
Vcc =
Vee =
Vcc
Vee
=
Max, VI
Max, VI
=
=
Units
-1.5
V
250
/LA
0.7
V
0.4
IOl
II
Max
1
mA
2.4V
40
/LA
0.4V
-1.6
mA
30
48
mA
27
51
mA
Max
Max
Switching Characteristics at Vcc = 5V and TA = 25·C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
tplH
Propagation Delay Time
Low to High Level Output
tpHl
Propagation Delay Time
High to Low Level Output
Note 1: All typicals are at Vee
Conditions
Cl
Rl
=
=
= 5V. TA = 25"C.
4-16
15pF
1100
Min
Max
Units
15
ns
23
ns
r-------------------------------------------------------------------------, -...0
~National
~ Semiconductor
DM5407/DM7407 Hex Buffers with
High Voltage Open-Collector Outputs
General Description
Pull-Up Resistor Equations
This device contains six independent gates each of which
performs a buffer function. The open-collector outputs require external pull-up resistors for proper logical operation.
R
Vo (Min) - VOH
MAX = Nl (IOH) + N2 (lIH)
R
MIN =
Vo (Max) - VOL
IOL - Na {lILl
Where: Nl (IOH) = total maximum output high current for all
outputs tied to pull-up resistor
N2 (IIH) = total maximum input high current for all
inputs tied to pull-up resistor
Na {IILl = total maximum input low current for all
inputs tied to pull-up resistor
Connection Diagram
Dual-In-Line Package
Vee
14
A1
A6
V6
AS
12
13
V1
A2
V5
II
A4
V4
V3
GND
10
V2
A3
TUF/6497-1
Order Number DM5407J, DM5407W, DM7407M or DM7407N
See NS Package Number J14A, M14A, N14A or W14B
Function Table
Y=A
H
Input
Output
A
V
L
L
H
H
= High Logic Level
L = Low LogiC Level
4-17
Absolute Maximum Ratings
(Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
5.5V
Input Voltage
Output Voltage
SOV
Operating Free Air Temperature Range
DM54
-55'Cto + 125'C
DM74
O'Cto +70'C
Storage Temperature Range
-65'Cto + 150'C
Recommended Operating Conditions
Symbol
DM7407
DM5407
Parameter
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
Vcc
Supply Voltage
VIH
High Level Input Voltage
V,L
Low Level Input Voltage
0.8
0.8
VOH
High Level Output Voltage
SO
SO
V
IOL
Low Level Output Current
SO
40
mA
TA
Free Air Operating Temperature
70
'C
2
V
2
-55
V
0
125
V
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
ConditIons
Typ
(Note 1)
MIn
= Min, II = -12 mA
= SOV
VI
Input Clamp Voltage
Vcc
ICEX
High Level Output
Current
Vcc = Min, Vo
VIH = Min
VOL
Low Level Output
Voltage
Vcc = Min, IOL
VIL = Max
= Max
= 16mA, Vcc = Min
Vcc = Max, VI = 5.5V
Input Current @ Max
Input Voltage
IIH
High Level Input Current
Vce = Max, VI
IlL
Low Level Input Current
Vee = Max, VI = 0.4V
ICCH
Supply Current with
Outputs High
Vec = Max
ICCL
Supply Current with
Outputs Low
Vcc = Max
Units
-1.5
V
250
p.A
0.7
V
0.4
IOL
II
Max
1
= 2.4V
mA
40
p.A
-1.6
mA
29
41
mA
21
SO
mA
Switching Characteristics at Vec = 5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
ConditIons
tpLH
Propagation Delay Time
Low to High Level Output
CL = 15pF
RL = 1100.
tpHL
Propagation Delay Time
High to Low Level Output
Note 1: All
typical. are at Vee
= 5V. TA = 25"C.
4-18
Min
Max
UnIts
10
ns
SO
ns
o
CO
~Nationai
~ Semiconch.JJcltor
5408/DM5408/DM7408
Quad 2-lnput AND Gates
General Description
features
This device contains four independent gates each of which
performs the logic AND function.
IJ Alternate Military/Aerospace device (5408) is available.
Contact a National Semiconductor Sales Office/Distributor for specifications.
Connection Diagram
Dual-In-Llne Package
A1
Y1
81
A2
83
A3
Y3
82
Y2
GND
TL/F/6498-1
Order Number 540BDMQB, 540BFMQB, DM540BJ, DM5408W or DM7408N
See NS Package Number J14A, N14A or W14B
Function Table
y= AB
Inputs
Output
A
B
Y
L
L
H
H
L
H
L
H
L
L
L
H
H = High Logic Level
L = Low Logic Level
II
4-19
co
Q
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
Note: The "Absolute Maximum RaUngs" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
DM54 and 54
- 55'C to + 125'C
DM74
O'Cto +70'C
Storage Temperature Range
-65'C to + 150'C
Recommended Operating Conditions
Symbol
DM5408
Parameter
Vcc
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
IOH
High Level Output Current
DM7408
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
IOL
Low Level Output Current
TA
Free Air Operating Temperature
Units
Min
V
2
V
0.8
0.8
V
-0.8
-0.8
mA
16
mA
70
'C
16
-55
125
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
= Min, II = -12 mA
= Max
VI
Input Clamp Voltage
Vee
VOH
High Level Output
Voltage
Vee = Min, IOH
VIL = Max
VOL
Low Level Output
Voltage
Vcc = Min, IOL
VIH = Min
II
Input Current @ Max
Input Voltage
Vee
2.4
= Max
Typ
(Note 1)
Units
-1.5
V
V
3.4
0.2
= Max, VI = 5.5V
= Max, VI = 2.4V
= Max, VI = 0.4V
DM54
Vcc = Max I
Max
0.4
V
1
mA
IIH
High Level Input Current
Vee
40
/LA
IlL
Low Level Input Current
Vcc
-1.6
mA
los
Short Circuit
Output Current
(Note 2)
I
DM74
-20
-55
-18
-55
= Max
leeH
Supply Current with
Outputs High
Vee
ICCL
Supply Current with
Outputs Low
Vee = Max
mA
11
21
mA
20
33
mA
Switching Characteristics at Vee = 5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
tpLH
Propagation Delay Time
Low to High Level Output
tpHL
Propagation Delay Time
High to Low Level Output
Conditions
CL
RL
= 15pF
= 4000
Note 1: All typical. are at Vee = SV. TA = 2S"C.
Note 2: Not more than one output should be shorted at a time.
4-20
Min
Max
Units
27
ns
19
ns
~National
~ Semiconductor
5409/DM7409 Quad 2-lnput AND Gates
with Open-Collector Outputs
General Description
Pull-Up Resistor Equations
This device contains four independent gates each of which
performs the logic AND function. The open-collector outputs require external pull-up resistors for proper logical operation.
R
Vee (Min) - VOH
MAX = Nl (lOH) + N2 (lIH)
R
MIN =
Vee (Max) - VOL
IOL - Na (III)
Where: Nl (IOH) = total maximum output high current for all
outputs tied to pull-up resistor
N2 (IIH) = total maximum input high current for all
inputs tied to pull-up resistor
Na (lILl = total maximum input low current for all
inputs tied to pull-up resistor
Connection Diagram
Dual-In-Llne Package
Vee
B4
A4
Al
Bl
VI
V4
A2
B3
A3
V3
B2
V2
GND
Order Number 5409DMQB, 5409FMQB or DM7409N
See NS Package Number J14A, N14A or W14B
Function Table
y= AB
Inputs
Output
A
B
y
L
L
L
H
H
H
L
L
L
L
H
H
H = High Logic Level
L
=
Low Logic Level
4-21
TLlF/6499-1
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
7V
input Voltage
5.5V
7V
Output Voltage
Operating Free Air Temperature Range
-55·Cto + 125·C
54
O·Cto +70·C
DM74
Storage Temperature Range
-65·Cto + 150·C
Recommended Operating Conditions
Symbol
DM7409
5409
Parameter
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
V
Vcc
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
0.8
0.8
VOH
High Level Output Voltage
5.5
5.5
V
IOL
Low Level Output Current
16
16
mA
TA
Free Air Operating Temperature
70
·c
2
V
2
-55
125
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Typ
(Note 1)
Min
Max
Units
VI
Input Clamp Voltage
Vcc = Min, II = -12 mA
-1.5
V
ICEX
High Level Output
Current
Vcc = Min, Vo = 5.5V
VIH = Min
250
/LA
VOL
Low Level Output
Voltage
Vcc = Min, IOL = Max
VIL = Max
0.4
V
II
Input Current @ Max
Input Voltage
Vcc = Max, VI = 5.5V
1
mA
0.2
IIH
High Level input Current
Vcc = Max, VI = 2.4V
40
/LA
IlL
Low Level Input Current
Vcc = Max, VI = O.4V
-1.6
mA
ICCH
Supply Current with
Outputs High
Vcc = Max
11
21
mA
ICCL
Supply Current with
Outputs Low
Vcc = Max
20
33
mA
Switching Characteristics at Vcc =
Symbol
5V and TA = 25·C (See Section 1 for Test Waveforms and Output Load)
Parameter
Conditions
tpLH
Propagation Delay Time
Low to High Level Output
CL = 15pF
RL = 4000
tpHL
Propagation Delay Time
High to Low Level Output
Note 1: All typical. are at Vee = SV, TA = 2S'C.
4-22
Min
Max
Units
32
ns
24
ns
.....
o
~National
~ Semiconductor
541 O/DM541 O/DM7 410
Triple 3-lnput NAND Gates
General Description
Features
This device contains three independent gates each of which
performs the logic NAND function.
• Alternate Military/ Aerospace device (5410) is available.
Contact a National Semiconductor Sales Office/Distributor for specifications.
Connection Diagram
Dual-In-Line Package
VI
Cl
13
C3
12
B3
A3
V3
lD
11
--»-
.-------.-I.J
2
AI
Bl
A2
B2
C2
V2
J:
TL/F/BSOO-l
Order Number 5410DMQB, 5410FMQB, DM5410J, DM5410Wor DM7410N
See NS Package Number J14A, N14A or W14B
Function Table
y= ABC
Inputs
Output
A
B
C
Y
X
X
X
L
L
X
X
X
H
H
H
H
H
L
L
H
= High Logic Level
L = Lew Logic Level
X = Either Low or High Logic Level
H
4-23
o.-
Absolute Maximum Ratings (Note)
Note: The ''Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
OHice/Distributors for availability and speciflcations_
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
DM54 and 54
- 55'C to + 125'C
DM74
O"Cto +70'C
Storage Temperature Range
-65'Cto + 150'C
Recommended Operating Conditions
Symbol
DM5410
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
Vil
Low Level Input Voltage
10H
High Level Output Current
DM7410
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
10L
Low Level Output Current
TA
Free Air Operating Temperature
Units
Min
V
2
V
0.8
0.8
V
-0.4
-0.4
mA
16
mA
70
'C
16
-55
0
125
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
= Min, II = -12 mA
= Max
Typ
(Note 1)
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vee
VOH
High Level Output
Voltage
Vee = Min, IOH
VIL = Max
VOL
Low Level Output
Voltage
Vee = Min, 10l
VIH = Min
II
Input Current @ Max
Input Voltage
Vee
IIH
High Levell nput Current
Vee
p.A
Low Level Input Current
Vee
-1.6
mA
los
Short Circuit
Output Current
= Max, VI = 2.4V
= Max, VI = O.4V
DM54
Vee = Max
40
III
-20
-55
(Note 2)
-18
-55
2.4
= Max
3.4
V
0.2
= Max, VI = 5.5V
leeH
Supply Current with
Outputs High
Vee
= Max
leel
Supply Current with
Outputs Low
Vee
= Max
DM74
0.4
V
1
mA
mA
3
6
mA
9
16.5
mA
Switching Characteristics at Vee = 5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
IplH
Propagation Delay Time
Low to High Level Output
tpHl
Propagation Delay Time
High to Low Level Output
Conditions
CL
RL
= 15pF
= 4000
Nola 1: Aillypicals are at Vee = 5V, TA = 25"C.
Nota 2: Not more than one output should be shorted at a time.
4-24
Min
Max
Units
22
ns
15
ns
r---------------------------------------------------------------------~
~National
-_
~ Semiconductor
DM7411
Triple 3-lnput AND Gate
General Description
This device contains three independent gates with three
data inputs each which perform the logic AND function.
Connection Diagram
Dual-In-Llne Package
14V
2
13 CC
4----.11r-~
TLlF/9774-1
Order Number DM7411N
NS Package Number N14A
•
4·25
....
....
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operations.
7V
Supply Voltage
Input Voltage
Operating Free Air
Temperature Range (DM74)
5.5V
O"Cto +70'C
Storage Temperature Range
-65'C to + 150'C
Recommended Operating Conditions
Symbol
DM7411
Parameter
Vcc
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
10H
Units
Min
Typ
Max
4.75
5
5.25
V
V
2
0.8
V
High Level Output Current
-0.4
mA
10L
Low Level Output Current
16
mA
TA
Free Air Operating Temperature
70
'C
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Conditions
Parameter
=
=
Typ
(Note 1)
Min
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vcc
VOH
High Level Output
Voltage
Vcc = Min, 10H
VIL = Max
=
Max,
VOL
Low Level Output
Voltage
Vee = Min,lOL
VIH = Min
=
Max,
II
Input Current @ Max
Input Voltage
Vcc
=
Max, VI
=
5.5V
IIH
High Level Input Current
Vcc
Max, VI
40
/LA
Low Level Input Current
Vee
=
=
2.4V
IlL
=
=
0.4V
-1.6
rnA
loS
Short Circuit
Output Current
Vee = Max
(Note 2)
-57
rnA
ICCH
Supply Current with
Outputs High
Vcc
=
Max
15
rnA
ICCL
Supply Current with
Outputs Low
Vcc
=
Max
24
rnA
Switching Characteristics at Vcc =
Symbol
Parameter
tpLH
Propagation Delay Time
Low to High Level Output
tpHL
Propagation Delay Time
High to Low Level Output
Min, II
Max, VI
-12 rnA
3.4
2.4
V
0.2
-18
5V and TA
=
=
=
Note 1: All Iyplcals are at Vee = 5V. TA = 25'C.
Nota 2: Not more than one output should be shorted at a time.
4-26
V
1
rnA
25'C (See Section 1 for Test Waveforms and Output Load)
Conditions
CL
RL
0.4
15pF,
4000
Min
Max
Units
27
ns
19
ns
r-------------------------------------------------------------------------, .a:._
~National
~ Semiconductor
DM5414/DM7414 Hex Inverter with
Schmitt Trigger Inputs
General Description
This device contains six independent gates each of which
performs the logic INVERT function. Each input has hysteresis which increases the noise immunity and transforms a
slowly changing input signal to a fast changing, jitter free
output.
Connection Diagram
Dual-In-Llne Package
Vee
A6
V6
A5
V5
A4
V4
TL/F/6503-1
Order Number DM5414J, DM5414Wor DM7414N
See NS Package Number J14A, N14A or W14B
Function Table
V=A
Input
Output
A
V
L
H
H
L
H = High Logic Level
L = Low Logic Level
•
4-27
Absolute Maximum Ratings
(Note)
If Military/Aeroapace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
-55·Cto + 125·C
DM54
DM74
O·Cto +70"C
Storage Temperature Range
-65·C to + 150"C
Recommended Operating Conditions
Symbol
DM5414
Parameter
DM7414
Units
Min
Nom
Max
Min
Nom
Max
Vee
Supply Voltage
4.5
5
5.5
4.75
5
5.25
V
VT+
Positive-Going Input
Threshold Voltage (Note 1)
1.5
1.7
2
1.5
1.7
2
V
VT-
Negative-Going Input
Threshold Voltage (Note 1)
0.6
0.9
1.1
0.6
0.9
1.1
V
0.4
0.8
0.4
0.8
HYS
Input Hysteresis (Note 1)
10H
High Level Output Current
-0.8
-0.8
mA
10L
Low Level Output Current
16
16
mA
TA
Free Air Operating Temperature
70
·C
-55
125
0
V
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
=
=
=
Min
Typ
(Note 2)
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vee
VOH
High Level Output
Voltage
Vcc
Min, 10H
VI = VT-Min
=
Max
VOL
Low Level Output
Voltage
Vee = Min, 10l
VI = VT+Max
=
Max
IT+
Input Current at
Positive-Going Threshold
Vcc
=
5V, VI
=
VT+
IT-
Input Current at
Negative-Going Threshold
Vee
=
5V, VI
=
VT-
II
Input Current @ Max
Input Voltage
Vee
=
Max, VI
=
5.5V
IIH
High Level Input Current
Vee
40
p.A
Vcc
=
=
2.4V
Low Level Input Current
O.4V
-1.2
mA
los
Short Circuit
Output Current
=
=
=
Max, VI
IlL
Vcc
Max
(Note 3)
ICCH
Supply Current with
Outputs High
Vee
=
Max
leel
Supply Current with
Outputs Low
Vee
=
Max
Min, II
Max, VI
-12 mA
I
J
Note 1: Vee = 5V
Note 2: All typical. are at Vee = 5V. TA = 25'C.
Note 3: Not more than one output should be shorted at a time.
4-28
2.4
V
3.4
0.2
0.4
V
-0.43
mA
-0.56
mA
1
DM54
-18
-55
DM74
-18
-55
mA
mA
22
36
mA
39
60
mA
Switching Characteristics at Vee = SV and TA = 2SoC (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
tpLH
Propagation Delay Time
Low to High Level Output
tpHL
Propagation Delay Time
High to Low Level Output
Conditions
CL
RL
= 1SpF
= 4000
4-29
Min
Max
Units
22
ns
22
ns
....
~ ~----------------------------------------------------------------------~
~National
~ Semiconductor
DM5416/DM7416 Hex Inverting Buffers with
High Voltage Open-Collector Outputs
General Description
Pull-Up Resistor Equations
This device contains six independent gates each of which
performs the logic INVERT function. The open-collector outputs require external pull-up resistors for proper logical operation.
R
Vo (Min) - VOH
MAX = Nl (lOH) + N2 (lIH)
R
Vo(Max) - VOL
MIN = IOL - N3 (lId
Where: Nl (lOH) = total maximum output high current for all
outputs tied to pull-up resistor
N2 (lIH) = total maximum input high current for all
inputs tied to pull-up resistor
N3 (IlL) = total maximum input low current for all
inputs tied to pull-up resistor
Connection Diagram
Dual-In-Llne Package
Vee
14
AI
A6
13
VI
V6
A5
12
A2
V5
II
A4
V4
V3
GND
10
V2
A3
Order Number DM5416J, DM5416Wor DM7416N
See NS Package Number J14A, N14A or W14B
Function Table
Y=A
Input
Output
A
Y
L
H
H
L
H = High Logic Level
L = Low Logic Level
4-30
TLlF/6504-1
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
Output Voltage
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
5.5V
15V
Operating Free Air Temperature Range
-55'C to + 125'C
DM54
DM74
O'Cto +70'C
Storage Temperature Range
-65'C to + 150'C
Recommended Operating Conditions
Symbol
DM5416
Parameter
DM7416
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
VOH
High Level Output Voltage
15
15
V
IOL
Low Level Output Current
30
40
mA
TA
Free Air Operating Temperature
70
'C
2
V
2
V
0.8
-55
0.8
125
0
V
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
=
=
VI
Input Clamp Voltage
Vee
leEX
High Level Output
Current
Vee = Min, Vo
VIL = Max
=
15V
VOL
Low Level Output
Voltage
Vee = Min, IOL
VIH = Min
=
Max
Min, II
Typ
(Note 1)
Min
-12 rnA
= 16 mA, Vee = Min
Vee = Max, VI = 5.5V
Input Current @ Max
Input Voltage
IIH
High Level Input Current
Vee
IlL
Vee
=
=
Max, VI
Low Level Input Current
leeH
Supply Current with
Outputs High
Vce
=
Max
ICCl
Supply Current with
Outputs Low
Vee
=
Max
Switching Characteristics at Vec =
Symbol
Parameter
tpLH
Propagation Delay Time
Low to High Level Output
tpHL
Propagation Delay Time
High to Low Level Output
Max, VI
=
=
5V and TA
250
".A
V
0.4
1
rnA
40
".A
-1.6
mA
30
48
mA
27
51
rnA
=
=
4-31
V
2.4V
=
Nole 1: All typical. are al Vee = 5V, TA = 25'0.
-1.5
O.4V
25'C (See Section 1 for Test Waveforms and Output Load)
Conditions
CL
RL
Units
0.7
IOL
II
Max
15pF
110n
Min
Max
Units
15
ns
23
ns
~
..-
r-------------------------------------------------------------------------,
~National
~ Semiconductor
DM5417/DM7417 Hex Buffers with
High Voltage Open-Collector Outputs
General Description
Pull-Up Resistor Equations
This device contains six independent gates each of which
performs a buffer function. The open-collector outputs require external pull-up resistors for proper logical operation.
Vo (Min) - VOH
R
MAX = N, (IOH) + N2 (lIH)
R
Vo (Max) - VOL
MIN = IOL - Na (lILl
Where: N, (lOH) = total maximum output high current for all
outputs tied to pull-up resistor
N2 (IIH) = total maximum input high current for all
inputs tied to pull-up resistor
Ns (lILl = total maximum input low current for all
inputs tied to pull-up resistor
Connection Diagram
Dual-In-Llne Package
vee
14
V6
A6
V5
A5
12
13
A4
V4
V3
GND
10
"
4
At
VI
A2
V2
A3
Order Number DM5417J, DM5417W or DM7417N
See NS Package Number J14A, N14A or W14B
Function Table
Y=A
H
Input
Output
A
Y
L
H
L
H
= High Logic Level
L = Low Logic Level
4-32
TL/F/6505-1
....
......
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
Input Voltage
Output Voltage
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
7V
5.5V
15V
Operating Free Air Temperature Range
DM54
-55'Cto +125'C
DM74
O'Cto +70'C
Storage Temperature Range
- 65'C to + 150'C
Recommended Operating Conditions
Symbol
DM5417
Parameter
Vcc
Supply Voltage
VIH
High Level Input Voltage
DM7417
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
V
2
V
VIL
Low Level Input Voltage
0.8
0.8
VOH
High Level Output Voltage
15
15
V
IOL
Low Level Output Current
30
40
mA
TA
Free Air Operating Temperature
70
'c
-55
125
0
V
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
VI
Input Clamp Voltage
ICEX
High Level Output
Current
VOL
Low Level Output
Voltage
II
Input Current @ Max
Input Voltage
Conditions
Typ
(Note 1)
Min
= Min, II = -12 mA
Vcc = Min, Vo = 15V
VIH = Min
Vcc = Min, IOL = Max
Vcc
Max
Units
-1.5
V
250
".A
0.7
= Max
IOL = 16 mA, Vcc = Min
Vcc = Max, VI = 5.5V
VIL
V
0.4
1
= Max, VI = 2AV
= Max, VI = OAV
Vcc = Max
mA
IIH
High Level Input Current
Vcc
40
".A
IlL
Low Level Input Current
Vcc
-1.6
mA
ICCH
Supply Current with
Outputs High
29
41
mA
ICCL
Supply Current with
Outputs Low
21
30
mA
Vcc
=
Max
Switching Characteristics at Vcc = 5V and T A = 25'C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
tpLH
Propagation Delay Time
Low to High Level Output
tpHL
Propagation Delay Time
High to Low Level Output
Conditions
CL
RL
= 15pF
= 1100
Note 1: All typical. are at Vee = 5V, TA = 25"C.
4-33
Min
Max
Units
10
ns
30
ns
•
~National
~ Semiconductor
5420/DM5420/DM7420
Dual4-lnput NAND Gates
General Description
Features
This device contains two independent gates each of which
performs the logic NAND function.
• Alternate Military/Aerospace device (5420) is available.
Contact a National Semiconductor Sales Office/Distributor for specifications.
Connection Diagram
Dual-In-Line Package
C2
02
82
NIC
111
12
13
A2
10
V2
9
-
I
2
4
Jc
5
l
AI
81
01
Cl
~
J6
J:
TLlF/6506-1
Order Number 5420DMQB, 5420FMQB, DM5420J, DM5420W or DM7420N
See NS Package Number J14A, N14A or \llJ14B
Function Table
v=
ABCD
Inputs
Output
A
B
C
D
V
X
X
X
X
X
X
L
H
L
L
X
X
X
H
H
H
L
L
X
X
X
H
H
H
H
H = High Logic Level
L = Low Logic Level
X = Either Low or High Logic Level
4-34
N
o
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
-55'C to + 125'C
DM54 and 54
DM74
O'Cto +70'C
Storage Temperature Range
-65'C to + 150'C
Recommended Operating Conditions
Symbol
DM5402
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
Vil
Low Level Input Voltage
10H
High Level Output Current
DM7402
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
10l
Low Level Output Current
TA
Free Air Operating Temperature
Units
Min
V
2
V
0.8
0.8
V
-0.4
-0.4
mA
16
mA
70
'C
16
-55
125
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
VI
Input Clamp Voltage
Vee = Min,ll = -12 mA
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
Vil = Max
VOL
Low Level Output
Voltage
Vee = Min,lOl = Max
VIH = Min
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 5.5V
2.4
Typ
(Note 1)
Max
Units
-1.5
V
3.4
V
0.2
0.4
V
1
mA
IIH
High Level Input Current
Vee = Max, VI = 2.4V
40
IJ-A
III
Low Level Input Current
Vee = Max, VI = O.4V
-1.6
mA
los
Short Circuit
Output Current
Vee = Max
(Note 2)
leeH
Supply Current with
Outputs High
Vee = Max
ICCl
Supply Current with
Outputs Low
Vee = Max
Switching Characteristics at Vee =
Symbol
I
I
DM54
-20
-55
DM74
-18
-55
mA
2
4
mA
6
11
mA
5V and T A = 25'C (See Section 1 for Test Waveforms and Output Load)
Parameter
Conditions
tplH
Propagation Delay Time
Low to High Level Output
Cl=15pF
Rl = 4000
tpHl
Propagation Delay Time
High to Low Level Output
Note 1: All typicals are at Vee = 5V, TA = 25'C.
Note 2: Not more than one output should be shorted at a time.
4-35
Min
Max
Units
22
ns
15
ns
•
~ r---------------------------------------------------------------------~
N
~National
~ Semiconductor
5425/DM7425
Dual4-lnput NOR Gate (with Strobe)
General Description
This device contains two, 4-input gates that perform the logic NOR function. The output of each NOR gate is gated
(strobed) by pin 3 and pin 11 by positive true logic i.e., logic
"1" equals output on.
Connection Diagram
Dual-In-Llne Package
_1~---,'-/
2
14
r;-;-Vcc
12
r l!...
10
7
GNDTL/F/9775-1
Order Number 5425DMQB, 5425FMQB, DM7425J or DM7425N
See NS Package Number J14A, N14A and W14B
4-36
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Note: The ''Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "£lectrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Input Voltage
5.5V
Operating Free Air Temperature Range
-55'Cto + 125'C
54
DM74
O'Cto +70'C
Storage Temperature Range
-65'Cto + 150'C
Recommended Operating Conditions
Symbol
5425
Parameter
Vcc
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
10H
High Level Output Current
10L
Low Level Output Current
TA
Free Air Operating Temperature
DM7425
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
V
V
2
0.8
0.8
V
-0.8
-0'.4
mA
16
mA
70
'C
16
-55
125
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
VI
Input Clamp Voltage
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
II
Input Current @ Max
Input Voltage
IIH
High Level Input Current
Low Level Input Current
IlL
los
Short Circuit
Output Current
Conditions
= Min, II = -12 mA
Vcc = Min, 10H = Max
VIL = Max
Vcc = Min, 10L = Max
VIH = Min
Vcc = Max, VI = 5.5V
Min
Typ
(Note 1)
Vcc
2.4
Max
Units
-1.5
V
3.4
V
0.2
0.4
V
1
mA
Vcc = Max,
VI = 2.4V
Strobe
160
Inputs
40
Vcc
= Max,
= O.4V
Vee = Max
Strobe
-6.4
VI
Inputs
-1.6
(Note 2)
54
-20
-55
DM74
-18
-57
p.A
mA
mA
IceH
Supply Current with
Outputs High
Vec
= Max
16
mA
ICCl
Supply Current with
Outputs Low
Vee
= Max
19
mA
Switching Characteristics at Vee = 5V, TA = 25'C (See Section 1 for Test Waveforms and Output Load)
Symbol
tpLH
Parameter
Propagation Delay Time
Low to High Level Output
Conditions
CL
RL
= 15 pF
= 4000
Propagation Delay Time
High to Low Level Output
Note 1: All typicals are at Vee = 5V, TA = 25'C.
tpHL
Note 2: Not more than one output should be shorted at a time.
4-37
Min
Max
Units
22
ns
15
ns
'?'A National
~ Semiconductor
DM5426/DM7426 Quad 2-lnput NAND Gates
with High Voltage Open-Collector Outputs
General Description
Pull-Up Resistor Equations
This device contains four independent gates each of which
performs the logic NAND function. The open-collector outputs require external pull-up resistors for proper logical operation.
R
Vo (Min) - VOH
MAX = N1 (IOH) + N2 (IIH)
R
Vo (Max) - VOL
MIN = IOL - N3 (IIU
Where: N1 (IOH) = total maximum output high current for all
outputs tied to pull-up resistor
N2 (IIH) = total maximum input high current for all
inputs tied to pull-up resistor
N3 (IIU = total maximum input low current for all
inputs tied to pull-up resistor
Connection Diagram
Dual-In-Llne Package
Vee
14
AI
84
83
11
12
13
81
Y4
A4
YI
A2
A3
Y3
Y2
GND
10
82
TL/F/6506-1
Order Number DM5426J or DM7426N
See NS Package Number J14A or N14A
Function Table
Y =AB
Inputs
Output
A
B
Y
L
L
L
H
H
H
L
H
H
H
H
L
H = High Logic Level
L = Low Logic Level
4-38
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaran·
teed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Output Voltage
15V
Operating Free Air Temperature Range
OM 54
-55'C to + 125'C
DM74
O'Cto +70'C
Storage Temperature Range
- 65'C to + 150'C
Recommended Operating Conditions
Symbol
DM5426
Parameter
DM7426
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
0.8
0.8
V
VOH
High Level Output Voltage
15
15
V
16
mA
70
'C
2
IOL
Low Level Output Current
TA
Free Air Operating Temperature
V
2
16
-55
125
0
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Typ
(Note 1)
Min
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vee = Min, 11= -12 mA
leEx
High Level Output
Current
Vee = Min
VIL = Max
VOL
Low Level Output
Voltage
Vee = Min, IOL = Max
VIH = Min
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 5.5V
IIH
High Level Input Current
Vee = Max, VI = 2.4V
40
/LA
IlL
Low Level Input Current
Vee = Max, VI = 0.4V
-1.6
mA
ICCH
Supply Current with
Outputs High
Vec = Max
4
8
mA
leeL
Supply Current with
Outputs Low
Vee = Max
12
22
mA
Switching Characteristics at Vee =
Symbol
5V and T A
Vo = 15V
1000
Vo = 12V
50
Parameter
Conditions
Propagation Delay Time
Low to High Level Output
CL = 15pF
RL = 1 kG (tpLH)
tpHL
Propagation Delay Time
High to Low Level Output
~
SV, TA
~
0.4
V
1
mA
= 25'C (See Section 1 for Test Waveforms and Output Load)
tpLH
Note 1: All typical. are al Vee
/LA
2S'C.
4-39
Min
Max
Units
24
ns
17
ns
~National
~ Semiconductor
DM7427 Triple 3-lnput NOR Gates
General Description
This device contains three independent gates each of which
performs the logic NOR function.
Connection Diagram
Dual-tn-Line Package
VI
Cl
14
13
12
11
2
3
4
81
AI
83
C3
A2
A3
C2
82
TL/F /6509-1
Order Number DM7427N
See NS Package Number N14A
Function Table
Y=A+B+C
Output
Inputs
A
B
C
Y
L
X
X
H
L
X
H
X
L
H
X
X
H
L
L
L
H = High Logic Level
L
X
= Low Logic Level
= enher High or Low Logic Level
4-40
V3
Absolute Maximum Ratings
(Note)
Supply Voltage
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
DM74
Storage Temperature Range
O'Cto +70'C
- 65'C to + 150'C
Recommended Operating Conditions
Symbol
DM7427
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
10H
Units
Min
Nom
Max
4.75
5
5.25
V
V
2
0.8
V
High Level Output Current
-0.8
rnA
10L
Low Level Output Current
16
rnA
TA
Free Air Operating Temperature
70
'C
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
VI
Input Clamp Voltage
Vee = Min, 11= -12 rnA
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
VIL = Max
VOL
Low Level Output
Voltage
Vee = Min, 10L = Max
VIH = Min
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 5.5V
IIH
High Level Input Current
Units
-1.5
V
3.4
V
V
1
rnA
Vee = Max, VI = 2.4V
40
p.A
-1.6
rnA
-57
rnA
10
16
rnA
16
26
rnA
Low Level Input Current
Vee = Max, VI = O.4V
los
Short Circuit
Output Current
Vee = Max (Note 2)
leeH
Supply Current with
Outputs High
Vee = Max
leeL
Supply Current with
Outputs Low
Vee = Max
Switching Characteristics at Vee =
0.2
-18
5V and T A = 25'C (See Section 1 for Test Waveforms and Output Load)
Parameter
Conditions
tpLH
Propagation Delay Time
Low to High Level Output
CL = 15pF
RL = 4000
tpHL
Propagation Delay Time
High to Low Level Output
Nole 1: All typicals are al Vee
2.4
Max
0.4
IlL
Symbol
Typ
(Note 1)
Min
= SV. TA = 2S·C.
Nole 2: Not more than one output should be shorted at a time.
4-41
Min
Max
Units
11
ns
15
ns
~National
~ Semiconductor
5430/DM5430/DM7430
a-Input NAND Gate
• Alternate Military/Aerospace device (5430) is available.
Contact a National Semiconductor Sales Office/Distrib·
utor for specifications.
General Description
This device contains a single gate which performs the logic
NAND function.
Connection Diagram
Dual·ln-Llne Package
VIC
12
114
v
G
H
11
rr=~~bJoP
4
A
c
GND
D
TL/F/6510-1
Order Number 5430DMBQ, 5430FMQB, DM5430J, DM5430W or DM7430N
See NS Package Number J14A, N14A or W14B
Function Table
Y = ABCDEFGH
Inputs
Output
A thru H
Y
AlllnputsH
One or More
InputL
L
H
H = High Logic Level
L = Low Logic Level
4·42
Absolute Maximum Ratings (Note)
Note: The "Abso/ute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
DM54 and 54
-55'C to + 125'C
DM74
O'Cto +70'C
Storage Temperature Range
-65'C to + 150'C
Recommended Operating Conditions
Symbol
DM5430
Parameter
Vcc
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
DM7430
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
V
2
V
0.8
0.8
V
10H
High Level Output Current
-0.4
-0.4
mA
10L
Low Level Output Current
16
16
mA
TA
Free Air Operating Temperature
70
'C
-55
125
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
=
=
Min
Typ
(Note 1)
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vcc
VOH
High Level Output
Voltage
Vcc = Min, 10H
VIL = Max
=
Max
VOL
Low Level Output
Voltage
VCC = Min, 10L
VIH = Min
=
Max
II
Input Current @ Max
Input Voltage
VCC
=
Max, VI
=
5.5V
=
=
Max, VI
=
=
2.4V
40
/LA
O.4V
-1.6
mA
Min, II
IIH
High Level Input Current
Vcc
IlL
Low Level Input Current
Vcc
los
Short Circuit
Output Current
Vcc = Max
(Note 2)
ICCH
Supply Current with
Outputs High
Vcc
=
Max
ICCL
Supply Current with
Outputs Low
Vcc
=
Max
Max, VI
-12 mA
Switching Characteristics at Vcc = 5V and TA =
Symbol
Parameter
tpLH
Propagation Delay Time
Low to High Level Output
tpHL
Propagation Delay Time
High to Low Level Output
=
=
Note 1: All typicals are at Vcc = sv. TA = 2S'C.
Note 2: Not more than one output should be shorted at a time.
4-43
3.4
V
0.2
0.4
V
1
mA
DM54
-20
-55
DM74
-18
-55
mA
1
2
mA
3
6
mA
25'C (See Section 1 for Test Waveforms and Output Load)
Conditions
CL
RL
2.4
15pF
4000
Min
Max
Units
22
ns
15
ns
~National
~ Semiconductor
5432/DM5432/DM7432
Quad 2-lnput OR Gates
General Description
Features
This device contains four independent gates each of which
performs the logic OR function.
• Alternate Military/ Aerospace device (5432) is available.
Contact a National Semiconductor Sales Office/Distributor for specifications.
Connection Diagram
Dual-In-Llne Package
Vee
B4
A4
Y4
A1
B1
V1
A2
B3
B2
A3
Y2
V3
GND
TLlF/6511-1
Order Number 5432DMQB, 5432FMQB, DM5432J, DM5432W or DM7432N
See NS Package Number J14A, N14A or W14B
Function Table
Y=A+B
Inputs
Output
A
B
Y
L
L
H
H
L
H
L
H
L
H
H
H
H = High LogiC Level
L = Low logic Level
4-44
W
N
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Note: The "Absolute MaxImum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Input Voltage
5.5V
Operating Free Air Temperature Range
DM54 and 54
- 55·C to + 125·C
O·Cto +70·C
DM74
Storage Temperature Range
-65·Cto + 150·C
Recommended Operating Conditions
Symbol
DM5432
Parameter
DM7432
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
0.8
0.8
V
Vcc
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
10H
High Level Output Current
-0.8
-0.8
mA
10L
Low Level Output Current
16
16
mA
TA
Free Air Operating Temperature
70
·C
Max
Units
-1.5
V
2
V
2
-55
125
0
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
VI
Input Clamp Voltage
Vcc = Min, II = -12 mA
VOH
High Level Output
Voltage
Vcc = Min, 10H = Max
VIH = Min
VOL
Low Level Output
Voltage
Vcc = Min, 10L = Max
VIL = Max
II
Input Current @ Max
Input Voltage
Vcc = Max, VI = 5.5V
2.4
Typ
(Note 1)
3.4
V
0.2
0.4
V
1
mA
IIH
High Level Input Current
Vcc = Max, VI = 2.4V
40
".A
IlL
Low Level Input Current
Vcc = Max, VI = O.4V
-1.6
mA
los
Short Circuit
Output Current
Vcc = Max
(Note 2)
ICCH
Supply Current with
Outputs High
Vcc = Max
ICCL
Supply Current with
Outputs Low
Vcc = Max
Switching Characteristics at Vcc =
Symbol
DM54
-20
-55
DM74
-18
-55
mA
15
22
mA
23
38
mA
5V and TA = 25·C (See Section 1 for Test Waveforms and Output Load)
Parameter
Conditions
tpLH
Propagation Delay Time
Low to High Level Output
CL=15pF
RL = 4000
tpHL
Propagation Delay Time
High to Low Level Output
Note 1: All typical. are at Vee = 5V, TA = 25'C.
Note 2: Not more than one output should be shorted at a time.
4-45
Min
Max
Units
15
ns
22
ns
~National
~ Semiconductor
5437/DM5437/DM7437
Quad 2-lnput NAND Buffers
General Description
Features
This device contains four independent gates each of which
performs the logic NAND function.
• Alternate Military/Aerospace device (5437) is available.
Contact a National Semiconductor Sales Office/Distributor for specifications.
Connection Diagram
Dual-In-Llne Package
vee
14
AI
84
A4
V4
II
12
13
VI
81
A2
83
A3
V3
V2
GND
10
82
TUF/6512-1
Order Number 5437DMQB, 5437FMQB, DM5437J, DM5437W or DM7437N
See NS Package Number J14A, N14A or W14B
Function Table
y= AB
Inputs
H
Output
A
B
Y
L
L
H
H
L
H
L
H
H
H
H
L
= High Logic Level
L = Low Logic Level
4-46
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operatiOn.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
-55·Cto +125·C
DM54 and 54
DM74
O·Cto +70·C
-65·Cto + 150·C
Storage Temperature Range
Recommended Operating Conditions
Symbol
DM5437
Parameter
DM7437
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
0.8
0.8
V
Vcc
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
IOH
High Level Output Current
-1.2
-1.2
mA
IOL
Low Level Output Current
48
48
mA
TA
Free Air Operating Temperature
70
·C
2
V
2
-55
125
0
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
= Min. II = -12 mA
= Max
VI
Input Clamp Voltage
Vcc
VOH
High Level Output
Voltage
Vcc = Min. IOH
VIL = Max
VOL
Low Level Output
Voltage
Vcc = Min. 10L
VIH = Min
II
Input Current @ Max
Input Voltage
Vcc
2.4
= Max
Typ
(Note 1)
Units
V
3.3
V
0.2
= Max. VI = 5.5V
= Max. VI = 2.4V
= Max. VI = 0.4V
Vee = Max
Max
-1.5
0.4
V
1
mA
/J- A
mA
IIH
High Level Input Current
Vcc
40
IlL
Low Level Input Current
Vcc
-1.6
loS
Short Circuit
Output Current
(Note 2)
ICCH
Supply Current with
Outputs High
Vcc = Max
ICCL
Supply Current with
Outputs Low
Vcc = Max
Switching Characteristics at Vcc =
Symbol
I
I
DM54
-20
-70
DM74
-18
-70
mA
9
15.5
mA
34
54
mA
5V and TA = 25·C (See Section 1 for Test Waveforms and Output Load)
Parameter
Conditions
tpLH
Propagation Delay Time
Low to High Level Output
CL = 45pF
RL = 133.!l
tpHL
Propagation Delay Time
High to Low Level Output
Not. 1: All typical. are at Vee = 5V. TA = 25'C.
Note 2: Not more than one output should be shorted at a time.
4-47
Min
Max
Units
22
ns
15
ns
II
~National
~ Semiconductor
DM5438/DM7438 Quad 2-lnput NAND Buffers
with Open-Collector Outputs
General Description
Pull-Up Resistor Equations
This device contains four independent gates each of which
performs the logic NAND function. The open-collector outputs require extemal pull-up resistors for proper logical operation.
R
Vee (Min) - VOH
MAX = N1 (IOH) + N2 (IIH)
R
Vee (Max) - VOL
MIN =
IOL - N3 (11Ll
Where: N1 (IOH) = total maximum output high current for all
outputs tied to pull-up resistor
N2 (IIH) = total maximum input high current for all
inputs tied to pull-up resistor
N3 (11Ll = total maximum input low current for all
inputs tied to pull-up resistor
Connection Diagram
Dual-In-Llne Package
AI
81
A2
VI
83
A3
Y3
82
Y2
GND
Order Number DM5438J, DM5438W, DM7438M or DM7438N
See NS Package Number J14A, M14A, N14A or W14B
Function Table
y= AB
Outpu1
Inputs
A
B
Y
L
L
H
H
L
H
L
H
H
H
H
L
H - High Logic Level
L - Low logic Level
4-48
TL/F/6513-1
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
Output Voltage
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
5.5V
7V
Operating Free Air Temperature Range
-55'Cto + 125'C
DM54
O'Cto +70'C
DM74
Storage Temperature Range
-65'Cto + 150'C
Recommended Operating Conditions
Symbol
DM5438
Parameter
Vcc
Supply Voltage
VIH
High Level Input Voltage
DM7438
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
V
2
V
VIL
Low Level Input Voltage
0.8
0.8
VOH
High Level Output Voltage
5.5
5.5
V
IOL
Low Level Output Current
48
48
mA
TA
Free Air Operating Temperature
70
'C
-55
125
0
V
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Typ
(Note 1)
Min
= Min, II = -12 mA
= 5.5V
VI
Input Clamp Voltage
Vcc
ICEX
High Level Output
Current
Vcc = Min, Vo
VIL = Max
VOL
Low Level Output
Voltage
Vee = Min, IOL
VIH = Min
II
Input Current @Max
Input Voltage
Vec
IIH
High Level Input Current
IlL
Low Level Input Current
lecH
Supply Current with
Outputs High
= Max, VI = 2.4V
Vce = Max, VI = O.4V
Vee = Max
ICCL
Supply Current with
Outputs Low
= Max
= Max, VI = 5.5V
= Max
Units
-1.5
V
250
/LA
0.4
V
1
mA
40
/LA
-1.6
mA
5
8.5
mA
34
54
mA
Vec
Vee
Max
Switching Characteristics at Vee = 5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
tpLH
Propagation Delay Time
Low to High Level Output
tpHL
Propagation Delay Time
High to Low Level Output
Note 1: All typical. are at Vee
~
5V. TA
~
Conditions
CL
RL
= 45pF
= 1330
25"C.
4-49
Min
Max
Units
22
ns
18
ns
~National
~ Semiconductor
DM7439 Quad 2-lnput NAND Buffer
with Open-Collector Output
General Description
This device contains four independent gates with two data
inputs, each which performs the logic NAND function.
Connection Diagram
Dual·ln·Llne Package
TL/F/9776-1
Order Number DM7439N
See NS Package Number N14A
4-50
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
DM74
Storage Temperature Range
+ 70°C
+ 150°C
O°Cto
-65°C to
Recommended Operating Conditions
Symbol
DM7439
Parameter
Vcc
Supply Voltage
V,H
High Level Input Voltage
V,L
Low Level Input Voltage
Units
Min
Nom
Max
4.75
5
5.25
V
2
V
0.8
V
10H
High Level Output Current
-0.25
mA
10L
Low Level Output Current
48
mA
TA
Free Air Operating Temperature
70
'C
0
IElectrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Min
Conditions
=
=
V,
Input Clamp Voltage
Vcc
VOH
High Level Output Voltage
Vcc = Min, 10H
V,L = Max
VOL
Low Level Output Voltage
Vcc
V,H
Min, I,
Typ
(Note 1)
-12 mA
=
= Min
= 2.0V
250 JJ-A
2.4
Max
Units
-1.5
V
3.4
V
10L
=
48mA
10L
=
60mA
0.5
10L
=
80mA
0.6
0.2
0.4
V
Vcc
=
Max, V,
=
High Level Input Current
Vcc
=
Max, V,
=
2.4V
40
JJ-A
Low Level Input Current
Vcc
=
Max, V,
=
0.4V
-1.6
mA
los
Short Circuit
Output Current
Vcc
=
Max (Note 2)
-57
mA
ICCH
Supply Current with
Outputs High
Vcc
=
Max
8.5
mA
ICCL
Supply Current with
Outputs Low
Vcc
=
Max
54
mA
at Vcc
=
5V and TA
I,
Input Current @ Max
Input Voltage
I'H
I,L
Switching Characteristics
Symbol
Parameter
tpLH
Propagation Deiay Time
Low to High Level Output
tpHL
Propagation Delay Time
High to Low Level Output
Note 1: All typical. are at Vee
~
5V, TA
~
5.5V
=
-18
=
=
25"C.
Note 2: Not more than one output should be shorted at a time.
4-51
mA
25'C (See Section 1 forTest Waveforms and Output Load)
Conditions
CL
RL
1
15pF
400.0
Min
Max
Units
22
ns
18
ns
~National
~ Semiconductor
5440/DM7440 Dual4-lnput NAND Buffer
General Description
This device contains two, 4 input gates that perform the
Logic NAND function. Outputs have 48 mA IOL.
Connection Diagrams
Dual-In-Llne Package
NC
2
14 V
13 CC
3
12
Cerpak
14
13
NC
4
Vee
5
Ne
12
11 GND
10
9
8
GND
TLlF/9777-1
TL/F/9777-2
Order Number 5440DMQB, DM5440J or DM7440N
See NS Package Number J14A or N14A
Order Number 5440FMQB
See NS Package Number W14B
4·52
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
Input Voltage
Operating Free Air Temperature Range
54
DM74
Storage Temperature Range
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
7V
5.5V
- 55'C to + 125'C
O'Cto +70'C
-65'C to + 150'C
Recommended Operating Conditions
Symbol
5440
Parameter
Vcc
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
10H
High Level Output Current
10L
Low Levei Output Current
TA
Free Air Operating Temperature
DM7440
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
2
V
0.8
0.8
V
-1.2
-0.4
mA
48
mA
70
'C
Max
Units
-1.5
V
48
-55
V
125
0
Electrical Characteristics
Over recommended operating free air temperature range (unless otherwise noted)
Symbol
Conditions
Parameter
=
=
Min
Typ
(Note 1)
VI
Input Clamp Voltage
Vcc
VOH
High Level Output Voltage
Vcc = Min, 10H
VIL = Max
=
Max
VOL
Low Level Output Voltage
Vcc = Min, 10l
VIH = Min
=
Max
II
Input Current @ Max
Input Voltage
Vee
=
Max, VI
=
5.5V
=
=
=
Max, VI
=
=
2.4V
40
/J- A
Max, VI
0.4V
-1.6
mA
Min. II
IIH
High Level Input Current
Vcc
III
Low Level Input Current
Vcc
los
Short Circuit
Output Current
Vcc
Max
(Note 2)
ICCH
Supply Current with
Outputs High
Vcc
=
Max
ICCl
Supply Current with
Outputs Low
VCC
=
Max
-12 mA
I
I
NDte 1: All typlcals are at Vee - SV, TA - 2S'C.
NDte 2: Not more than one output should be shorted at a time.
4-53
2.4
3.4
0.2
V
0.4
V
1
mA
54
-20
-70
DM74
-18
-70
mA
8
mA
27
mA
Switching Characteristics
at Vee = 5V and T A = 25°C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
tpLH
Propagation Delay Time
Low to High Level Output
tpHL
Propagation Delay Time
High to Low Level Output
Conditions
CL
RL
= 15 pF
= 400.0.
4-54
Min
Max
Units
22
ns
15
ns
~Nal1onal
~ Semiconductor
5442A/DM5442A/DM7442A
BCD to Decimal Decoders
General Description
Features
These BCD·to·decimal decoders consist of eight inverters
and ten, four·input NAND gates. The inverters are connected in pairs to make BCD input data available for decoding
by the NAND gates. Full decoding of input logic ensures
that all outputs remain off for all invalid (10-15) input conditions.
• Diode clamped inputs
• Also for application as 4-line-to-16-line decoders; 3-lineto-B-line decoders
• All outputs are high for invalid Input conditions
• Typical power dissipation 140 mW
• Typical propagation delay 17 ns
• Alternate Military/Aerospace device (5442A) is available. Contact a National Semiconductor Sales Office/
Distributor for specifications.
Connection Diagram
Dual-In-Line Package
OUTPUTS
INPUTS
vee
I ..
e
B
A
••
.5
9
D
••
.3
••
11
9
7 J8
4
GND
OUTPUTS
TLIFI6516-1
Order Number 5442ADMQB, 5442AFMQB, DM5442AJ, DM5442AW or DM7442AN
See NS Package Number J16A, N16E or W16A
Function Table
BCD Input
No.
Decimal Output
2
3
4
5
6
7
8
9
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
D
C
B
A
0
0
1
2
3
4
L
L
L
L
L
L
L
L
L
H
L
L
L
L
H
H
H
H
H
H
L
L
H
L
H
H
H
H
L
H
H
5
6
7
B
L
L
L
H
H
H
H
H
L
L
L
H
H
L
L
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
H
H
H
H
L
L
H
H
L
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
9
I
N
V
A
L
I
0
H
L
H = High Level
L = Low Level
4·55
III
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Operating Free Air Temperature Range
DM54 and 54
-55'Cto + 125'C
DM74
O'Cto +70'C
Storage Temperature Range
-65'C to + 150'C
Recommended Operating Conditions
Symbol
Vcc
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
IOH
High Level Output Current
DM7442A
DM5442A
Parameter
Min
Nom
Max
Min
4.5
5
5.5
4.75
Low Level Output Current
TA
Free Air Operating Temperature
Max
5
5.25
2
2
IOL
Units
Nom
V
0.8
0.8
V
-0.8
-0.8
mA
16
mA
70
·c
16
-55
V
125
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
VI
Input Clamp Voltage
Vee = Min, 11= -12 mA
VOH
High Level Output
Voltage
Vee = Min, IOH = Max
VIL = Max, VIH = Min
VOL
Low Level Output
Voltage
Vee = Min, 10L = Max
VIH = Min, VIL = Max
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 5.5V
2.4
Typ
(Note 1)
Max
Units
-1.5
V
V
3.4
0.2
0.4
V
1
mA
IIH
High Level Input Current
Vee = Max, VI = 2.4V
40
".A
IlL
Low Level Input Current
Vee = Max, VI = 0.4V
-1.6
mA
los
Short Circuit
Output Current
Vee = Max
(Note 2)
DM54
-20
-55
DM74
-18
-55
Supply Current
Vee = Max
(Note 3)
DM54
28
41
DM74
28
56
Icc
Note 1: All typicals are at Vee
= 5V, TA = 25'C.
Note 2: Not more than one output should be shorted at a time.
Note 3:
ICC is measured with all outputs open and all inputs grounded.
4·56
mA
mA
Switching Characteristics at Vee =
Max
Units
25
ns
Propagation Delay Time
High to Low Level Output
from A, B, C or 0 through
3 Levels of Logic
30
ns
Propagation Delay Time
Low to High Level Output
from A, B, C or 0 through
2 Levels of Logic
25
ns
Propagation Delay Time
Low to High Level Output
from A, B, C or 0 through
3 Levels of Logic
30
ns
Symbol
tpHL
tpHL
tpLH
tpLH
5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
Parameter
Conditions
Propagation Delay Time
High to Low Level Output
from A, B, Cor 0 through
2 Levels of Logic
CL = 15pF
RL = 400.0
Min
Logic Diagram
INPUT A (15)
(1)
~OUTPUTO
i
~
INPUT B (14)
(2)
~OUTPUT1
~OUTPUT2
~OUTPUT3
i
Lt>B
~.OUTPUT 4
C
~OUTPUT5
(6)
INPUT C
(13)
INPUTD (12)
4>c
~OUTPUT6
-
D
~
4>D
(9)
OUTPUT 7
(10)
OUTPUT 6
I
(11)
~OUTPUT9
T1/F/6516-2
•
4-57
U) r---------------------------------------------------------------------------~
"'II'
~National
~ Semiconductor
DM5445/DM7445 BCD to Decimal Decoders/Drivers
General Description
Features
These BCD-to-decimal decoders/drivers consist of eight inverters and ten, four-input NAND gates. The inverters are
connected in pairs to make BCD input data available for
decoding by the NAND gates. Full decoding of BCD input
logic ensures that all outputs remain off for all invalid
(10-15) binary input conditions. These decoders feature
high-performance, NPN output transistors designed for use
as indicator/relay drivers, or as open-collector logic-circuit
drivers. The high-breakdown output transistors are compatible for interfacing with most MOS integrated circuits.
• Full decoding of input logic
• 80 mA sink-current capability
• All outputs are off for invalid BCD input conditions
Connection Diagram
Function Table
Inputs
INPUTS
A
B
DeB A 0 1 2 3 4 5 6 7 8 9
o L L L L L H H H H H H H H H
OUTPUTS
c
Outputs
No.r---~--_+----------~----------~
Dual-In-Llne Package
1
2
3
4
o
BCD-to-Decimal
5
0123456789
6
7
8
9
I
N
V
A
OUTPUTS
TL/F/6517-1
Order Number DM5445J, DM5445W or DM7445N
See NS Package Number J16A, N16E or W16A
L
I
o
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H = High Level (Off), L = Low Level (On)
4-58
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Output Voltage
SOV
Operating Free Air Temperature Range
DM54
- 55'C to + 125'C
DM74
O'Cto +70'C
Storage Temperature Range
- 65'C to + 150'C
Recommended Operating Conditions
Symbol
DM7445
DM5445
Parameter
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
O.B
O.B
VOH
High Level Output Voltage
30
30
V
IOL
Low Level Output Current
20
20
mA
TA
Free Air Operating Temperature
70
'C
2
V
V
2
-55
125
0
V
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
VI
Input Clamp Voltage
leEX
High Level Output
Current
VOL
Low Level Output
Voltage
II
Input Current @ Max
Input Voltage
Conditions
Typ
(Note 1)
Min
= Min,ll = -12 mA
Vee = Min, Vo = 30V
VIL = Max, VIH = Min
Vee = Min, IOL = Max
VIH = Min, VIL = Max
IOL = BOmA
Vee = Min
Vee = Max, VI = 5.5V
Vee
Max
Units
-1.5
V
250
p,A
0.2
0.4
0.5
0.9
V
1
= Max, VI = 2.4V
= Max, VI = 0.4V
Vee = Max
I DM54
mA
IIH
High Level Input Current
Vee
40
p,A
IlL
Low Level Input Current
Vec
-1.6
mA
Icc
Supply Current
I
(Note 2)
Switching Characteristics
Symbol
at Vee
Propagation Delay Time
Low to High Level Output
tpHL
Propagation Delay Time
High to Low Level Output
62
43
70
mA
= 5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
Parameter
tpLH
DM74
43
Conditions
CL
RL
= 15pF
= 100.(1
Note 1: All typicals are at Vee = 5V. TA = 25'C.
Note 2: Icc is measured with all inputs grounded and all outputs open.
4-59
Min
Max
Units
49.5
ns
49.5
ns
..
U) r-------------------------------------------------------------------------------~
Logic Diagram
TLlF/6517-2
4·60
r-------------------------------------------------------------------------------------,
~National
•
;;:
~ Semiconductor
~
DM7446A, DM5447A/DM7447A
BCD to 7-Segment Decoders/Drivers
General Description
The 46A and 47A feature active-low outputs designed for
driving common-anode LEDs or incandescent indicators directly. All of the circuits have full ripple-blanking input/output controls and a lamp test input. Segment identification
and resultant displays are shown on a following page. Display patterns for BCD input counts above nine are unique
symbols to authenticate input conditions.
All of the circuits incorporate automatic leading and/or trailing-edge, zero-blanking control (RBI and RBO). Lamp test
(LT) of these devices may be performed at any time when
the BI/RBO node is at a high logic level. All types contain
an overriding blanking input (BI) which can be used to control the lamp intensity (by pulsing) or to inhibit the outputs.
Features
• All circuit types feature lamp intensity modulation
capability
• Open-collector outputs drive indicators directly
• Lamp-test provision
• Leading/trailing zero suppression
Connection Diagram
Dual-In-Llne Package
OUTPUTS
gab
15
14
13
3
4
c
d
12
11
5
6
e
10
9
--
2
B
C
INPUTS
~
~
LAMP BII RBO
RBI
TEST
~
INPUTS
Order Number DM5447AJ, DM7446AN or DM7447AN
See NS Package Number J16A or N16E
4-61
TL/F/6518-1
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Input Voltage
5.5V
Operating Free Air Temperature Range
-55'Cto + 125'C
DM54
O'Cto +70'C
DM74
Storage Temperature Range
- 65'C to + 150'C
Recommended Operating Conditions
Symbol
DM7446A
Parameter
Units
Min
Nom
Max
4.75
5
5.25
Vee
Supply Voltage
VIH
High Level Input Voltage
V
VIL
Low Level Input Voltage
VOH
High Level Output Voltage (a thru g)
30
V
10H
High Level Output Current (BIIRBO)
-0.2
p.A
10L
Low Level Output Current (a thru g)
40
mA
10L
Low Level Output Current (BIIRBO)
8
mA
TA
Free Air Operating Temperature
70
'C
V
2
0.8
0
V
'46A Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
VI
Input Clamp Voltage
Vee = Min, 11= -12 mA
VOH
High Level Output
Voltage (BIIRBO)
Vee = Min
10H = Max
leEX
High Level Output
Current (a thru g)
Vee = Max, Vo = 30V
VIL = Max, VIH = Min
VOL
Low Level Output
Voltage
Vee = Min, 10L = Max
VIH = Min, VIL = Max
II
Input Current @ Max
Input Voltage
IIH
IlL
Min
2.4
Typ
(Note 1)
Max
Units
-1.5
V
3.7
V
250
p.A
0.4
V
Vee = Max, VI = 5.5V
(Except BIIRBO)
1
mA
High Level Input
Current
Vee = Max, VI = 2.4V
(Except BIIRBO)
40
p.A
Low Level Input
Current
Vee = Max
VI = O.4V
los
Short Circuit
Output Current
Vee = Max (BIIRBO)
Icc
Supply Current
Vee = Max
(Note 2)
Nole 1: All typicals are at Vee
I
I
0.3
BIIRBO
-4
Others
-1.6
60
= SV. TA = 2S'C.
Nole 2: Icc Is measured with all outputs open and all inputs at 4.SV.
4-62
mA
-4
mA
103
mA
'46A Switching Characteristics
at Vee = 5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
Conditions
tpLH
Propagation Delay Time
Low to High Level Output
CL = 15 pF
RL = 1200
tpHL
Propagation Delay Time
High to Low Level Output
Min
Max
Units
100
ns
100
ns
Recommended Operating Conditions
Symbol
DM5447A
Parameter
DM7447A
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
0.8
0.8
V
VOH
High Level Output
Voltage (a thru g)
15
15
V
10H
High Level Output
Current (BI/RBO)
-0.2
-0.2
/LA
10L
Low Level Output
Current (a thru g)
40
40
mA
10L
Low Level Output
Current (BI/RBO)
8
8
mA
TA
Free Air Operating Temperature
70
'C
Max
Units
-1.5
V
2
-55
125
V
V
2
0
'47A Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
VI
Input Clamp Voltage
Vee = Min, 11= -12 rnA
VOH
High Level Output
Voltage (BI/RBO)
Vee = Min
10H = Max
leEX
High Level Output
Current (a thru g)
Vee = Max, Vo = 15V
VIL = Max, VIH = Min
VOL
Low Level Output
Voltage
Vee = Min, 10L = Max
VIH = Min, VIL = Max
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 5.5V
IIH
High Level Input Current
Vee = Max, VI = 2.4V
IlL
Low Level Input
Current
Vee = Max
VI = 0.4V
los
Short Circuit
Output Current
Vee = Max (BI/RBO)
lee
Supply Current
Vee = Max
(Note 2)
Min
2.4
Typ
(Note 1)
V
3.7
0.3
250
/LA
0.4
V
1
mA
40
/LA
-4
BI/RBO
-4
DM54
60
85
DM74
60
103
Note 1: Ali typical. are at Vcc - SV, TA - 2S'C.
Note 2: Icc is measured with ali outputs open and ali inputs at 4.5V.
4-63
mA
-1.6
Others
mA
mA
•
'47A Switching Characteristics
at Vee
= 5V and TA = 25"C (See Section 1 for Test Waveforms and Output load)
Symbol
Conditions
Parameter
tpLH
Propagation Delay Time
Low to High Level Output
tpHL
Propagation Delay Time
High to low Level Output
CL
RL
Min
= 15pF
= 1200
Max
Units
100
ns
100
ns
Function Table
46A,47A
Decimal or
Function
LT
RBI
D
C
B
A
0
1
H
H
.H
X
L
L
L
L
L
L
L
H
2
3
H
H
X
X
L
L
L
L
H
H
4
5
H
H
X
X
L
L
H
H
6
7
H
H
X
X
L
L
8
9
H
H
X
X
10
11
H
H
12
13
14
15
Inputs
BI/RBO
(Note 1)
Outputs
Note
a
b
c
d
e
f
9
H
H
L
H
L
L
L
L
L
H
L
H
L
H
H
H
L
H
H
H
L
L
L
L
H
L
L
L
L
H
H
H
L
L
L
L
L
H
H
H
H
L
L
H
L
L
H
L
H
H
L
L
L
L
H
H
H
H
L
H
H
H
H
L
H
L
L
L
L
H
L
H
L
H
L
H
H
H
L
L
L
L
L
H
H
H
L
L
L
L
L
L
L
H
L
H
L
L
L
L
X
X
H
H
L
L
H
H
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
L
L
H
H
X
X
H
H
H
H
L
L
L
H
H
H
H
L
L
H
H
H
H
L
H
H
L
L
L
L
H
H
X
X
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
L
H
L
H
L
H
BI
X
X
X
X
X
X
L
H
H
H
H
H
H
H
(3)
RBI
H
L
L
L
L
L
L
H
H
H
H
H
H
H
(4)
(2)
(5)
LT
L
X
X
X
X
X
H
L
L
L
L
L
L
L
Note 1: BIIRBO Is a wire-ANO logic serving as blanking input (BI) andlor rlpple-bianklng output (RBO).
Note 2: The blanking Input (BI) must be open or held at a high logic level when output functions 0 through 15 are desired. The ripple-blanking input (RBI) must
be open or high ff blanking of a decimal zero Is not desired.
Note 3: When a low logic level is applied directly to 1he blanking input (BI), all segment outputs are high regardless of the level 01 any ofher input
Note 4: When ripple-blanking input (RBI) and inputs A, B, C, and 0 are at a low level with 1he lamp test input high, all segment outputs go H and tile rippleblanking output (RBO) goes to a low level (response condition).
Note 5: When the blanking input/ripple-blsnklng output (BI/RBO) is open or held high and a low is applied to tile lamp-test input, all segment outputs are L .
H = High level, L = Low level, X = Don't Care
4·64
Logic Diagram
46A,47A
TL/F/6518-2
•
4-65
Q ,------------------------------------------------------------------,
In
~National
~ Semiconductor
DM7450 Expandable Dual2-Wide 2-lnput
AND-OR-INVERT Gate
General Description
This device contains two independent combinations of
gates. each of which perform the logic AND·DR·INVERT
function. One set of gates has an expander node.
Connection Diagram
Dual-In-Llne Package
11
10
9
8
TL/F/9778-1
Order Number DM7450N
See NS Package Number N14A
4·66
U1
C)
Absolute Maximum Ratings
(Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
DM74
Storage Temperature Range
O'Cto +70'C
-65'Cto + 150'C
Recommended Operating Conditions
Symbol
DM7450
Parameter
Vcc
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
10H
Units
Min
Nom
Max
4.75
5
5.25
V
V
2
0.8
V
High Level Output Current
-0.4
mA
10L
Low Level Output Current
16
mA
TA
Free Air Operating Temperature
70
'c
0
Electrical Characteristics
Over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
= Min, II = -12 mA
Vcc = Min, 10H = -400 p.A
VIL = Max
Vcc = Min, 10L = Max
VIH = Max
VCC = Max, VI = 5.5V
VI
Input Clamp Voltage
VOH
High Level Output
Voltage
VOL
Low Level Output
Voltage
II
Input Current @ Max
Input Voltage
Ix
Expander Current
V1 = 0.4V,IOL
Vcc = Min, TA
Min
Typ
(Note 1)
Vcc
Max, VI
VCC
=
=
=
Supply Current with
Outputs High
VCC
=
Max
ICCL
Supply Current with
Outputs Low
Vcc
=
Max
VSE(Q)
Base-Emitter Voltage
of Output Transistor Q
11 = 0.62mA
10L = 16mA
R1 = on
IIH
High Level Input Current
Vcc
IlL
Low Level Input Current
Vcc
los
Short Circuit
Output Current
ICCH
Max, VI
=
=
=
=
2.4
Units
-1.5
V
3.4
0.2
16 mA
Min
Max
V
0.4
V
1
mA
3.1
mA
2.4V
40
p.A
O.4V
-1.6
mA
-57
mA
8
mA
14
mA
1.0
V
Max (Note 2)
4-67
-18
•
Switching Characteristics at Vee =
Symbol
5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
Parameter
Conditions
tpLH
Propagation Delay Time
Low to High Level Output
CL = 15pF
RL = 4000.
tpHL
Propagation Delay Time
High to Low Level Output
Note 1: All typicals are at Vee
= 5V, TA = 25'C.
Note 2: Not more than one output should be shorted al a lime.
4·68
Min
Max
Units
22
ns
15
ns
....
r---------------------------------------------------------------------,~
~National
~ Semiconductor
5451/DM7451
DuaI2-Wide, 2-lnput AOI Gate
General Description
This device contains two independent combinations of
gates, each of which perform the logic AND-DR-INVERT
function.
Connection Diagram
Dual-In-Llne Package
TL/F/9719-1
Order Number 5451DMQB, 5451FMQB or DM7451N
See NS Package Number J14A, N14A or W14B
4-69
.-
II)
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and speclficatlons_
Supply Voltage
7V
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for acutual device operation.
Input Voltage
5.5V
Operating Free Air Temperature Range
54
- 55'C to + 125'C
DM74
O'Cto +70'C
Storage Temperature Range
-65'C to + 150'C
Recommended Operating Conditions
Symbol
5451
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
Vil
Low Level Input Voltage
10H
High Level Output Current
DM7451
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
10l
Low Level Output Current
TA
Free Air Operating Temperature
Units
Min
V
2
0.8
0.8
V
-0.8
-0.4
mA
16
mA
70
'C
16
-55
V
125
0
Electrical Characteristics Over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 1)
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vcc=Min,ll= -12mA
VOH
High Level Output
Voltage
Vcc = Min, 10H = Max
Vil = Max
VOL
Low Level Output
Voltage
Vcc = Min, 10l = Max
VIH = Min
II
Input Current @ Max
Input Voltage
Vcc = Max, VI = 5.5V
IIH
High Level Input Current
VCC = Max, VI = 2.4V
40
,...A
III
Low Level Input Current
Vcc = Max, VI = 0.4V
-1.6
mA
los
Short Circuit
Output Current
Vce = Max
(Note 2)
ICCH
Supply Current with
Outputs High
Vec = Max
ICCl
Supply Current with
Outputs Low
Vcc = Max
2.4
3.4
0.2
V
0.4
V
1
mA
54
-20
-55
DM74
-18
-57
4-70
mA
8
mA
14
mA
Switching Characteristics at Vee =
Symbol
en
....
5V and TA = 25"C (See Section 1 for Test Waveforms and Output Load)
Parameter
Conditions
tpLH
Propagation Delay Time
Low to High Level Output
CL = 15 pF
RL = 4000.
tpHL
Propagation Delay Time
High to Low Level Output
Min
Max
Units
22
ns
15
ns
Note 1: All typicals are at Vee = 5V, TA = 25°C.
Note 2: Not more than one output should be shorted at a time.
III
4·71
~
r--
,----------------------------------------------------------------------------,
~National
~ Semiconductor
5473/DM5473/DM7473
Dual Master-Slave J-K Flip-Flops with Clear
and Complementary Outputs
General Description
This device contains two independent positive pulse triggered J-K flip-flops with complementary outputs. The J and
K data is processed by the flip-flops after a complete clock
pulse. While the clock is low the slave is isolated from the
master. On the positive transition of the clock. the data from
the J and K inputs is transferred to the master. While the
clock is high the J and K inputs are disabled. On the negative transition of the clock. the data from the master is transferred to the slave. The logic states of the J and K inputs
must not be allowed to change while the clock is high. Data
transfers to the outputs on the falling edge of the clock
pulse. A low logiC level on the clear input will reset the outputs regardless of the logic states of the other inputs.
Features
• Alternate Military/Aerospace device (5473) is available.
Contact a National Semiconductor Sales Office/Distributor for specifications.
Connection Diagram
Dual·ln·Line Package
01
Jl
14
01
13
GND
12
K2
/11
02
/10
1
A
A
"-----l
I
1
6
ClKl
CLR 1
ClK2
ClR 2
P
J2
TLlF/6525-1
Order Number 5473DMQB, 5473FMQB, DM5473J, DM5473W or DM7473N
See NS Package Number J14A, N14A or W14B
Function Table
Inputs
CLR
L
H
H
H
H
CLK
X
..n..
..n..
..n..
..n..
H
outputs
J
X
L
H
L
H
K
X
L
L
H
H
Q
L
Q
X = Either Low or High Logic Level
.I1. = Positive pulse data. the J and K inputs must be held constant while
the clock is high. Data is transferred to the outputs on the falling edge of the
clock pulse.
L
H
00
00
H
L
L
H
Toggle
= High logic Level
= Low LogiC Level
00 = The output logic level before the indicated Input conditions were established .
Toggle = Each output changes 10 the complement of its previous level on
each high level clock pulse.
4-72
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
DM54 and 54
- 55·C to + 125·C
DM74
O·Cto +70"C
Storage Temperature Range
-65·Cto + 150"C
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
perametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Recommended Operating Conditions
Symbol
DM5473
Parameter
Vee
Supply Voltage
VIH
High level Input Voltage
VIL
low Level Input Voltage
DM7473
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
0.8
0.8
V
mA
2
2
V
IOH
High level Output Current
-0.4
-0.4
IOL
Low Level Output Current
16
16
mA
fCLK
Clock Frequency (Note 5)
0
15
MHz
tw
Pulse Width
(Note 5)
Clock High
20
20
Clock Low
47
47
Clear low
25
25
ot
oJ,
tsu
Input Setup Time (Note 1 & 5)
tH
Input Hold Time (Note 1 & 5)
ot
oJ,
TA
Free Air Operating Temperature
-55
15
125
0
ns
ns
ns
0
70
·c
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
VI
Input Clamp Voltage
Vee = Min,ll = -12 mA
VOH
High level Output
Voltage
Vee = Min, IOH = Max
VIL = Max, VIH = Min
VOL
Low Level Output
Voltage
Vee = Min, IOL = Max
VIH = Min, VIL = Max
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 5.5V
IIH
High Level Input
Current
Vee = Max
VI = 2.4V
IlL
los
lec
Low Level Input
Current
VCC = Max
VI = 0.4V
Min
2.4
Typ
(Note 2)
Max
Units
-1.5
V
3.4
0.2
V
0.4
V
1
mA
J,K
40
Clock
80
Clear
80
J,K
-1.6
Clock
-3.2
Clear
-3.2
Short Circuit
Output Current
Vce = Max
(Note 3)
DM54
-20
-55
DM74
-18
-55
Supply Current
Vee = Max, (Note 4)
Note 1: The symbol ( f. .J.) Indicates the edge 01 the clock pulse is used lor reference:
18
34
(f) lor rising edge. (.J.) lor lalling edge.
Note 2: All typicals are at Vee = 5V, TA = 25'C.
Note 3: Not more than one output should be shorted at a time.
Noh! 4: With all outputs open, Icc Is measured with the Q and Q outputs high In turn. At the time 01 measurement the clock input grounded.
Note 5: TA
= 25'C and Vcc = 5V.
4-73
p.A
mA
mA
mA
•
Switching Characteristics at Vee = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
RL = 4000
From (Input)
Symbol
Parameter
Units
CL = 15pF
To (Output)
Min
Max
fMAX
Maximum Clock
Frequency
tpHL
Propagation Delay Time
High to Low Level Output
Clear
toO
40
ns
tpLH
Propagation Delay Time
Low to High Level Output
Clear
toO
25
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clock to
QorO
40
ns
tpLH
Propagation Delay Time
Low to High Level Output
Clock to
QorO
25
ns
15
4·74
MHz
~National
~ Semiconductor
5474/DM5474/DM7474
Dual Positive-Edge-Triggered D Flip-Flops
with Preset, Clear and Complementary Outputs
General Description
This device contains two independent positive-edge-triggered D flip-flops with complementary outputs. The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse. The triggering occurs at a
voltage level and is not directly related to the transition time
of the rising edge of the clock. The data on the D input may
be changed while the clock is low or high without affecting
the outputs as long as the data setup and hold times are not
violated. A low logic level on the preset or clear inputs will
set or reset the outputs regardless of the logic levels of the
other inputs.
Features
• Alternate Military/Aerospace device (5474) is available.
Contact a National Semiconductor Sales Office/Distributor for specifications.
Connection Diagram
Dual·ln·llne Package
vIC
T
D2
ClR 2
2
10
~
I--
roo
--
I>
9
Y
1
-
!
b
.... 1:
K 13
ClR 1
il2
n2
PR2
111
12
13
114
ClK
1
J~ X
ClK 1
6
iii
G1:
Tl/F/6526-1
Order Number 5474DMQB, 5474FMQB, DM5474J, DM5474W, DM7474M or DM7474N
See NS Package Number J14A, M14A, N14A or W14B
Function Table
Inputs
outputs
PR
ClR
ClK
D
Q
Q
L
H
L
H
H
H
H
L
L
H
H
H
X
X
X
X
H
X
L
X
i
i
H
L
H'
H
L
L
H
H'
L
H
L
X
00
00
H = High Logic Level
X = Either Low or High Logic Level
L = Low logic Level
i = Posltive·going transition of the clock .
• = This configuration Is nonstable; that is. It will not persist when either the preset andlor clear
inputs return to their inactive (high) level.
00 = The output logic level of 0 before the indicated input conditions were established.
4-75
•
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
OM54 and 54
-55'Cto +125'C
OM74
O'Cto +70'C
Storage Temperature Range
-65'Cto + 150'C
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaran·
teed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Recommended Operating Conditions
Symbol
DM5474
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
DM7474
Min
Nom
Max
4.5
2
5
5.5
Min
4.75
Units
Max
5.25
V
V
O.B
-0.4
V
rnA
2
VIL
Low Level Input Voltage
10H
10L
High Level Output Current
Low Level Output Current
Clock Frequency (Note 2)
0
Pulse Width
(Note 2)
30
37
30
37
30
30
30
30
feLK
tw
Nom
5
O.B
-0.4
16
Clock High
Clock Low
Clear Low
Preset Low
15
Input Setup Time (Notes 1 & 2)
20j
tsu
5j
Input Hold Time (Notes 1 & 2)
tH
-55
Free Air Operating Temperature
TA
Nole 1: The symbol (t) indicates the rising edge of the clock pulse Is used for reference.
Nole 2: TA ~ 2S'C and Vee - SV.
0
16
rnA
15
MHz
ns
20j
5j
125
ns
ns
0
70
'C
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
VI
VOH
VOL
II
IIH
Conditions
Parameter
Input Clamp Voltage
High Level Output
Voltage
Low Level Output
Voltage
Input Current @ Max
Input Voltage
High Level Input
Current
Vee
= Min, II =
Min
-12 rnA
Vee = Min, 10H = Max
VIL = Max, VIH = Min
Vee = Min, 10L = Max
VIH = Min, VIL = Max
Vee = Max, VI = 5.5V
Vee = Max
VI = 2.4V
2.4
los
Low Level Input
Current
Short Circuit
Output Current
Max
Units
-1.5
V
3.4
0.2
V
0.4
V
1
rnA
0
40
Clock
BO
120
Clear
Preset
IlL
Typ
(Note 3)
Vee = Max
VI = O.4V
(Note 6)
Clock
40
-1.6
-3.2
Clear
Preset
-3.2
-1.6
Vee = Max
(Note 4)
OM 54
-20
-55
OM74
Max (Note 5)
-1B
-55
0
Supply Current
17
30
Vee =
Icc
Note 3: All typlcals are at Vee = SV, TA = 2S'C.
Note 4: Not more than one output should be shorted at a Hme.
Note 5: With all outputs open, lee is measured with the Q and Q outputs high In turn. At the time of measurement the clock is grounded.
Note 6: Clear Is tested with preset high and preset is tested with clear high.
4·76
/loA
mA
rnA
rnA
Switching Characteristics at Vee =
Symbol
Parameter
5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
RL
CL
From (Input)
To (Output)
Min
=
=
4000
15pF
Units
Max
fMAX
Maximum Clock
Frequency
tpHL
Propagation Delay Time
High to Low Level Output
Preset
toa
40
ns
tpLH
Propagation Delay Time
Low to High Level Output
Preset
toO
25
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clear
toO
40
ns
tpLH
Propagation Delay Time
Low to High Level Output
Clear
toa
25
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clock to
Oora
40
ns
tpLH
Propagation Delay Time
Low to High Level Output
Clock to
Oora
25
ns
15
MHz
•
4-77
~National
~ Semiconductor
5475/DM5475/DM7475
Quad Latches
General Description
a
These latches feature complementary
and 0 outputs
from a 4-bit latch and are available in 16-pin packages.
These latches are ideally suited for use as temporary storage for binary information between processing units and input/output or indicator units. Information present at a data
(D) input is transferred to the input when the enable (G) is
high, and the output will follow the data input as long as
the enable remains high. When the enable goes low, the
information (that was present at the data input at the time
the transition occurred) is retained at the output until the
enable is permitted to go high.
a
a
Features
• Alternate Military/Aerospace device (5475) is available.
Contact a National Semiconductor Sales Office/Distributor for specifications.
a
Connection Diagram
Function Table (Each Latch)
Dual-In-Line Package
01
16
E~~~LE
02
02
15
14
GNO
12
Outputs
Inputs
03
04
03
11
10
9
D
G
Q
Q
L
H
H
L
H
H
L
L
ao
00
H
X
H = High Level, L = Low Level, X = Don't
Care, 00 = The Level of 0 Before the Highto·Low Transition of G
2
3
02
5
4
ENABLE
3-4
Vee
6
03
7
04
TUF/6527-1
Order Number 5475DMQB, 5475FMQB, DM5475J,
DM5475W or DM7475N
See NS Package Number J16A, N16E or W16A
Logic Diagram
(Each Latch)
75
JO-..-oo
00-....<)(
ENABLE
DATA
4-78
TUF/6527-2
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
DM54 and 54
-55'C to + 125'C
DM74
O'Cto +70'C
Storage Temperature Range
- 65'C to + 150'C
Recommended Operating Conditions
Symbol
DM5475
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
10H
High Level Output Current
DM7475
Min
Nom
Max
4.5
5
5.5
Units
Min
Nom
Max
4.75
5
5.25
2
2
V
V
0.8
0.8
V
-0.4
-0.4
mA
16
mA
10L
Low Level Output Current
tw
Enable Pulse Width (Note 4)
20
20
ns
tsu
Setup Time (Note 4)
20
20
ns
tH
Hold Time (Note 4)
5
5
ns
TA
16
Free Air Operating Temperature
-55
125
0
70
'C
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 1)
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vee = Min, 11= -12 mA
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
VIL = Max, VIH = Min
VOL
Low Level Output
Voltage
Vee = Min, 10L = Max
VIH = Min, VIL = Max
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 5.5V
IIH
High Level Input Current
Vee = Max, VI = 2.4V
80
/LA
IlL
Low Level Input Current
Vee = Max, VI = 0.4V
-3.2
mA
los
Short Circuit
Output Current
Vee = Max
(Note 2)
DM54
-20
-55
DM74
-18
-55
Supply Current
Vee = Max
(Note 3)
DM54
32
46
DM74
32
50
Icc
Nale 1: All typlcals are al Vcc ~ 5V, TA ~ 25'C.
Nale 2: Not more than one output should be shorted at a time.
Nale 3: Icc is measured with all inputs grounded and all outputs open.
Nate 4: TA ~ 25'C and Vee ~ 5V.
2.4
3.4
0.2
V
0.4
V
1
mA
mA
mA
III
4-79
Switching Characteristics at Vee =
Symbol
Parameter
5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
RL
CL
From (Input)
To (Output)
MIn
= 400(1
= 15pF
UnIts
Max
tpHL
Propagation Delay Time
High to Low Level Output
DtoO
25
ns
tpLH
Propagation Delay Time
Low to High Level Output
DtoO
30
ns
tpHL
Propagation Delay Time
High to Low Level Output
DtoO
15
ns
tpLH
Propagation Delay Time
Low to High Level Output
DtoO
40
ns
tpHL
Propagation Delay Time
High to Low Level Output
GtoO
15
ns
tpLH
Propagation Delay TIme
Low to High Level Output
GtoO
30
ns
tpHL
Propagation Delay Time
High to Low Level Output
GtoO
15
ns
tpLH
Propagation Delay Time
Low to High Level Output
GtoO
30
ns
4·80
~National
~ Semiconductor
5476/DM5476/DM7476
Dual Master-Slave J-K Flip-Flops with Clear,
Preset, and Complementary Outputs
General Description
This device contains two independent positive pulse triggered J-K flip-flops with complementary outputs. The J and
K data is processed by the flip-flop after a complete clock
pulse. While the clock is low the slave is isolated from the
master. On the positive transition of the clock, the data from
the J and K inputs is transferred to the master. While the
clock is high the J and K inputs are disabled. On the negative transition of the clock, the data from the master is trans-
ferred to the slave. The logic state of J and K inputs must
not be allowed to change while the clock is high. The data is
transfered to the outputs on the falling edge of the clock
pulse. A low logic level on the preset or clear inputs will set
or reset the outputs regardless of the logic levels of the
other inputs.
Features
• Alternate Military/Aerospace device (5476) is available.
Contact a National Semiconductor Sales Office/Distributor for specifications.
Connection Diagram
Function Table
Dual·ln·line Package
Kl
Ql
iiI
GND
KZ
Q2
Inputs
iiz
JZ
PR
ClR
ClK
L
H
H
L
L
H
H
H
H
L
X
X
X
H
H
H
H
.n..
.n..
.n..
.n..
16
ClK 1
PR 1
ClR 1
Jl
Vee
ClKZ
PRZ
ClRZ
Tl/F/6526-1
Order Number 5476DMQB, 5476FMQB,
DM5476J, DM5476W or DM7476N
See NS Package Number J16A, N16E or W16A
H
= High Logic Level
L
=
X
= Eilher Low or High Logic Level
Outputs
J
K
Q
x
x
X
H
L
L
X
X
L
L
H
H
H
X
L
H
L
H
HO
HO
00
00
H
L
H
L
Toggle
Low Logic Level
.J1. = Positive pulse dala. The J and K inpuls must be held constant while
lhe clock is high. Data is lransfered to the oulpuls on the falling edge of the
clock pulse.
• = This configuration is nonstable; that is, it will not persist when the preset
and/or clear inpuls relum 10 their Inactive (high) level.
00 = The output logic level before the indicated input conditions were es·
tablished.
Toggle = Each output changes to the complement of its previous level on
each complete active high level clock pulse.
4-81
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors tor availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
DM54 and 54
-55'Cto + 125'C
DM74
O'Cto +70'C
Storage Temperature Range
-65'Cto +150'C
Recommended Operating Conditions
Symbol
Vee
Supply Voltage
V,H
High Level Input Voltage
V,l
Low Level Input Voltage
IOH
High Level Output Current
DM7476
DM5476
Parameter
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
V
V
2
0.8
0.8
V
-0.4
-0.4
mA
IOL
Low Level Output Current
felK
Clock Frequency (Note 6)
0
16
tw
Pulse Width
(Note 6)
Clock High
20
20
Clock Low
47
47
Preset Low
25
25
15
0
Clear Low
25
25
tsu
Input Setup Time (Notes 1 & 6)
oj
oj
tH
Input Hold Time (Notes 1 & 6)
O.J,
O.J,
TA
Free Air Operating Temperature
-55
125
16
mA
15
MHz
ns
ns
ns
0
70
'C
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 2)
2.4
3.4
= Min,l, = -12 mA
V,
Input Clamp Voltage
Vee
VOH
High Level Output
Voltage
Vee = Min, IOH = Max
V,L = Max. V,H = Min
VOL
Low Level Output
Voltage
Vee = Min, IOL = Max
V,H = Min, V,L = Max
I,
Input Current @ Max
Input Voltage
Vee
I'H
High Level Input
Current
Vee = Max
V, = 2.4V
-1.5
0.2
= Max, V, = 5.5V
Icc
V
1
mA
J, K
40
80
Clear
80
-1.6
Clock
-3.2
(Note 5)
Clear
-3.2
Short Circuit
Output Current
Vee = Max
(Note 3)
DM54
-20
-55
DM74
-18
-55
Supply Current
Vee
= Max (Note 4)
18
34
Note 3: Not more than one output should be shorted at a time.
Note 4: With all outputs open, Icc Is measured with the Q and 0 outputs high In turn. At the time of measurement the clock Input is grounded.
Note 5: Clear is measured with preset high and preset Is measured with clear high.
4-82
mA
-3.2
Note 1: The symbol (t, .1.) Indicates the edge of the clock pulse is used for reference (t) for rising edge. ( .j.) for failing edge.
Note 2: All typicals are at Vee = 5V, TA = 25·C.
Note 6: TA = 25"C and Vee = 5V.
p.A
80
J, K
Preset
los
V
0.4
Vee = Max
V, = 0.4V
Low Level Input
Current
Units
V
Clock
Preset
I,l
Max
mA
mA
Switching Characteristics at Vee = 5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
RL
CL
From (Input)
To (Output)
Min
= 4000
= 15pF
Units
Max
fMAX
Maximum Clock
Frequency
tpHL
Propagation Delay Time
High to Low Level Output
Preset
toO
40
ns
tpLH
Propagation Delay Time
Low to High Level Output
Preset
toQ
25
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clear
toQ
40
ns
tpLH
Propagation Delay Time
Low to High Level Output
Clear
toO
25
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clock to
QorO
40
ns
tpLH
Propagation Delay Time
Low to High Level Output
Clock to
QorO
25
ns
15
4-83
MHz
~National
~ Semiconductor
5483A
4·Bit Binary Full Adder with Fast Carry
General Description
The '83A high speed 4·blt binary full adders with Internal
carry lookahead accept two 4·blt binary words (Ao-Aa, BoBa) and a Carry Input (Co). They generate the binary Sum
outputs (So-Sa) and the Carry output (C4) from the most
significant bit. They operate with either HIGH or active LOW
operands (positive or negative logic). The '283 Is recom·
mended for new designs since It features standard corner
power pins.
Connection Diagram
Logic Symbol
Dual·ln·Llne Package
\,.../
A3- 1
16 !-B3
15 !-53
52- 2
A2-3
14 !-C4
B2- 4
13 I-CO
Vcc - 5
51- 6
12 I-GND
AO BO Al B1 A2 B2 A3 B3
13-CO
C41--14
50 51 52 53
111-BO
B1- 7
10 !-AO
A1- 8
91-50
I I I I
9
6 2 15
TL/F/9613-2
= Pin 5
GND = Pin 12
vee
TLlF/9613-1
Order Number 5483ADMQB or 5483AFMQB
See NS Package Number J16A or W16A
Description
Pin Names
A Operand Inputs
B Operand Inputs
Carry Input
5umOuputs
CarryOuput
Ao-Aa
Bo-B3
Co
So-53
C4
Truth Table
Inputs
Outputs
Co
Ao
A1
A2
A3
Bo
B1
B2
B3
So
S1
S2
S3
C4
Logic Levels
L
L
H
L
H
H
L
L
H
H
H
L
L
H
Active HIGH
Active LOW
0
1
0
1
1
0
0
1
1
0
1
0
0
1
0
1
1
0
1
0
1
0
0
1
0
1
1
0
= HIGH Voltage Level
L = LOW Voltage Level
H
4·84
(10 + 9 = 19)
(carry + 5 + 6
= 12)
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
-55·C to + 125·C
DM54
-65·Cto +150·C
Storage Temperature Range
Recommended Operating Conditions
Symbol
5483A
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
10H
High Level Output Current
10L
Low Level Output
Current
TA
I
I
Units
Min
Nom
Max
4.5
5
5.5
V
V
2
O.B
V
-O.B
rnA
Sn
16
C4
B
-55
Free Air Operating Temperature
rnA
·C
125
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
VI
Input Clamp Voltage
Vee = Min, 11= -18 rnA
VOH
High Level Output Voltage
Vee = Min, 10H = Max,
VIL = Max, VIH = Min
VOL
Low Level Output Voltage
Vee = Min, 10L = Max,
VIH = Min, VIL = Max
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 5.5V
IIH
High Level Input Current
IlL
Low Level Input Current
los
Short Circuit
Output Current
Vee = Max (Note 2)
Typ
(Note 1)
Max
Units
-1.5
V
V
2.4
0.4
V
1
rnA
Vee = Max, VI = 2.4V
40
/LA
Vee = Max, VI = O.4V
-1.6
rnA
I
I
Outputs
-20
-55
C4
-20
-70
Supply Current
Vee = Max
Icc
Note 1: All typicals are at Vce = SV, TA = 2S'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
99
rnA
rnA
•
4-85
Switching Characteristics Vee =
Symbol
+5.0V, TA = +25"C
CL
RL
Parameter
= 15pF
= 4000
Min
Units
Max
Propagation Delay
tpLH
tpHL
Co to Sn
21
21
ns
tpLH
tpHL
Propagation Delay
An or Bn toS n
24
24
ns
tpLH
tpHL
Propagation Delay
Co to C4
14
16
ns
tpLH
tpHL
Propagation Delay
An orBn toC4
14
16
ns
Functional Description
The '83A adds two 4-bit binary words (A and B) plus the
incoming carry. The binary sum appears on the sum outputs
(SO-53) and outgoing carry (C4) outputs.
Due to the symmetry of the binary add function the '83A can
be used either with all inputs and outputs active HIGH (positive logic) or with all inputs and outputs active LOW (negative logic). Note that with active HIGH inputs, Carry In can
not be left open, but must be held LOW when no carry in is
intended.
Interchanging inputs of equal weight does not affect the operation, thus Co, Ao, Bo can be arbitrarily assigned to pins
10,11,13, etc.
Co + (Ao + Bo) + 2 (Al + Bl) + 4 (A2 + B2) + 8 (A3 +
B3) = So + 251 + 452 + 853 + 16C4
Where: (+) = plus
Logic Diagram
co
AD
90
50
91
Al
51
A2
92
A3
53
S2
93
C4
TL/F/9613-3
4-86
r-------------------------------------------------------------------------------------,
~National
CD
en
~ Semiconductor
5485/DM5485/DM7485
4-Bit Magnitude Comparators
General Description
These 4-bit magnitude comparators perform comparison of
straight binary or BCD codes. Three fully-decoded decisions
about two 4-bit words (A, B) are made and are externally
available at three outputs. These devices are fully expandable to any number of bits without external gates. Words of
greater length may be compared by connecting comparators in cascade. The A > B, A < B, and A = B outputs of a
stage handling less-significant bits are connected to the corresponding inputs of the next stage handling more-significant bits. The stage handling the least-significant bits must
have a high-level voltage applied to the A = B input. The
cascading paths are implemented with only a two-gate-Ievel
delay to reduce overall comparison times for long words.
Features
• Typical power dissipation 275 mW
• Typical delay (4-bit words) 23 ns
• Alternate Military/Aerospace device (5485) is available.
Contact a National Semiconductor Sales Office/Distributor for specifications.
Connection Diagram
Dual-In-Line Package
DATA INPUTS
,
A3
vCC
B2
Al
A2
Bl
115114113112111
116
I
I
A3
B2
A2
Bl
Al
AO
BO
110
9
I
AO
BO
B3
ABA>BA=BABA>BA=BAB
40
Others
120
AB
-1.6
Others
-4.8
DM54
-20
-55
DM74
-18
-55
55
Note 1: All typlcals are at Vcc = 5V, TA = 25'C.
Note 2: Not more than one output should be shorted at a time.
Note 3: ICC is measured with all outputs open, A = B Input grounded and all other inputs at 4.5V.
4-88
88
p.A
mA
mA
mA
Switching Characteristics at Vee =
5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
Number of
Gate Levels
RL = 400.0
CL = 15pF
Parameter
From
Input
To
Output
Propagation Delay Time
Low-to-High Level Output
AnyAor8
Data Input
A<8
A>B
3
26
A=8
4
35
A<8
A>8
3
30
A=8
4
30
Symbol
Min
tpLH
tpHL
Propagation Delay Time
High-to-Low Level Output
AnyAor8
Data Input
Units
Max
ns
ns
tpLH
Propagation Delay Time
Low-to-High Level Output
A<8
orA = 8
A>8
1
11
ns
tpHL
Propagation Delay Time
High-to-Low Level Output
A<8
orA = 8
A>8
1
17
ns
tpLH
Propagation Delay Time
Low-to-High Level Output
A=8
A=8
2
20
ns
tpHL
Propagation Delay Time
High-to-Low Level Output
A=8
A=8
2
17
ns
tpLH
Propagation Delay Time
Low-to-High Level Output
A>8
orA = 8
A<8
1
11
ns
tpHL
Propagation Delay Time
High-to-Low Level Output
A>8
orA= 8
A<8
1
17
ns
Function Table
Comparing
Inputs
A3,B3
A3>
A3 <
A3 =
A3 =
A3 =
A3 =
A3 =
A3 =
A3 =
A3 =
A3 =
A3 =
A3 =
A3 =
H
83
83
83
83
83
83
83
83
83
83
83
83
83
83
= High Level,
Cascading
Inputs
Outputs
A2,B2
A1,B1
AO,BO
A>B
AB
A 82
A2 < 82
A2 = 82
A2 = 82
A2 = 82
A2 = 82
A2 = 82
A2 = 82
A2 = 82
A2 = 82
A2 = 82
A2 = 82
L = Low Level, X
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
>
<
=
=
=
=
=
=
=
=
81
81
81
81
81
81
81
81
81
81
= Don't Care
AO>
AO <
AO =
AO =
AO =
AO =
AO =
AO =
80
80
80
80
80
80
80
80
X
X
H
L
H
L
4-89
Logic Diagram
r-A3
(15)
B3 (1)
:P-
>~~
(5)
A>B
~
A2
B2
AB
(13)
(14)
Y>-
~
~
D-
(2)
(6)
(3)
A=B
(4)
DA1
B1
(12)
Jo(11)
~
p~
....--..
j::3
(10)
AO
BO
)0(II)
(7)
A
CLR 1
Q
Jl
01
TUF/6537-1
Order Number DM54109J or DM54109W
See NS Package Number J16A or W16A
Function Table
Inputs
Outputs
PR
ClR
ClK
J
K
Q
Q
l
H
l
H
H
H
H
H
H
l
L
H
H
H
H
H
X
X
X
X
X
X
L
H
l
H
X
X
X
X
L
L
H
H
X
H
l
H·
L
l
H
H·
H
t
t
t
t
L
Toggle
00
00
H
L
00
00
= High Logic Level
= Low Logic Level
i = Rising Edge of Pulse.
H
L
• = This configuration is nonstabJe; that Is. H: will not persist when preset
and clear inputs return to their inactive (high) level.
00 = The output logic level of 0 before the indicated input conditions were
established.
Toggle = Each output changes to the complement of its previous level on
each active transition of the clock pulse.
4-113
...g
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and speciflcations_
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
- 55·C to + 125·C
DM54
Storage Temperature Range
- 65·C to + 150·C
Note: The "Absolute Maximum Ratings" ara those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table ara not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Recommended Operating Conditions
Min
4.5
2
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
High Level Output Current
10H
10L
Units
Max
5.5
V
V
0.8
-1.2
Low Level Output Current
V
mA
mA
MHz
16
Clock Frequency (Note 6)
0
Pulse Width
(Note 6)
Clock High
20
20
20
20
Isu
Clock Low
Preset Low
Clear Low
Input Setup Time (Notes 1 & 6)
tH
Input Hold Time (Notes 1 & 6)
TA
Free Air Operating Temperature
feLK
tw
DM54109
Nom
5
Parameter
Symbol
30
ns
ns
15t
10,j..
-55
ns
·c
125
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
VI
Input Clamp Voltage
Vee = Min, 11= -12 mA
VOH
High Level Output
Voltage
Low Level Output
Voltage
Input Current @ Max
Input Voltage
High Level Input
Current
Vee = Min, 10H = Max
VIL = Max, VIH = Min
VOL
II
IIH
IlL
Low Level Input
Current
Vcc = Min, 10L = Max
VIH = Min, VIL = Max
Vee = Max, VI = 5.5V
J,K
Preset
Clock
Clear
J,K
Vee = Max
VI = 0.4V
Preset
(Note 5)
Clock
Clear
Vee = Max (Note 3)
Vee = Max
VI = 2.4V
Min
Typ
(Note 2)
2.4
3.4
0.2
Max
Units
-1.5
V
V
0.4
V
1
mA
40
80
80
160
-1.6
-3.2
.4-114
mA
-3.2
-4.8
Short Circuit
-30
-85
Output Current
Supply Current
Vee = Max (Note 4)
20
30
ICC
Nota 1: The symbol (t) indicates the rising edge of the clock pulse is used for reference.
Note 2: All typicals are at Vee = 5V, TA = 25"C.
Note 3: Not more than one output should be shorted at a time.
Note 4: Wnh all outputs open, lee Is measured with the a and a outputs high In turn. At the time of measurement the clock Input grounded.
Nota 6: Clear is tested with preset high and preset is tested with clear high.
Note 6: TA = 25·C and Vee = 5V.
los
p.A
mA
mA
Switching Characteristics at Vee =
Symbol
Parameter
5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
RL = 4000
CL = 15pF
From (Input)
To (Output)
Min
Units
Max
fMAX
Maximum Clock
Frequency
tpLH
Propagation Delay Time
Low to High Level Output
Preset
toO
14
ns
tpHL
Propagation Delay Time
High to Low Level Output
Preset
toO
29
ns
tpLH
Propagation Delay Time
Low to High Level Output
Clear
taO
14
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clear
toO
25
ns
tpLH
Propagation Delay Time
Low to High Level Output
Clock to
OorO
18
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clock to
OorO
28
ns
30
4-115
MHz
....
N
....
~National
~ Semiconductor
54121/DM54121/DM74121 One-Shot with
Clear and Complementary Outputs
General Description
The DM54/74121 is a monostable multivibrator featuring
both positive and negative edge triggering with complementary outputs. An internal 2kO timing resistor is provided for
design convenience minimizing component count and layout problems. This device can be used with a single external
capacitor. Inputs (A) are active-low trigger transition inputs
and input (8) is an active-high transition Schmitt-trigger input that allows jitter-free triggering from inputs with transition rates as slow as 1 volt/second. A high immunity to
Vcc noise of typically 1.5V is also provided by internal circuitry at the input stage.
•
•
•
•
•
•
•
Jitter free Schmitt-trigger input
Excellent noise immunity typically 1.2V
Stable pulse width up to 90% duty cycle
TTL, DTL compatible
Compensated for Vee and temperature variations
Input clamp diodes
Alternate Military/Aerospace device (54121) is available. Contact a National Semiconductor Sales Office/
Distributor for specifications.
Functional Description
• Triggered from active-high transition or active-low transition inputs
• Variable pulse width from 30 ns to 28 seconds
The basic output pulse width is determined by selection of
an internal resistor RINT or an external resistor (Rx) and
capacitor (Cx). Once triggered the output pulse width is independent of further transitions of the inputs and is a function of the timing components. Pulse width can vary from a
few nano-seconds to 28 seconds by choosing appropriate
Rx and Cx combinations. There are three trigger inputs from
the device, two negative edge-triggering (A) inputs, one positive edge Schmitt-triggering (8) input.
Connection Diagram
Function Table
To obtain optimum and trouble free operation please read
operating rules and NSC one-shot application notes carefully and observe recommendations.
Features
Inputs
Dual·ln·Llne Package
vcc
NC
NC
REXTI
CeXT CEXT
RINT
NC
h4 J,3 112 111 110 19
2k I
1
18
T
~J
1 12
Q
NC
~~
A1
3 14
A2
15
B
16
Q
17
GND
TUF/6536-1
Order Number 54121DMQB, 54121FMQB,
DM54121J, DM54121W or DM74121N
See NS Package Number JI4A, N14A or W14B
A2
B
Q
Q
L
X
X
X
H
H
L
H
H
X
H
L
L
L
L
H
H
H
H
J.
H
J.
J.
L
X
X
L
..J1..
..J1..
..J1..
..J1..
..J1..
"1I
"1I
"1I
"1I
"1I
J.
= High Logic Level
= Low Logic Level
X = Can Be Either Low or High
t = PosRive Going Trensitlon
.J- = Negative GOing Transition
SL = A PosRive Pulse
LJ = A Negative Pulse
H
L
4-116
Outputs
AI
L
X
H
H
H
t
t
Absolute Maximum Ratings
....N
....
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
DM54
-55'C to + 125'C
DM74
O'Cto +70'C
Storage Temperature Range
-65'C to + 150'C
Recommended Operating Conditions
Symbol
DM54121
Parameter
Min
Vee
Supply Voltage
VT+
Positive-Going Input Threshold
Voltage at the A Input (Vee = Min)
VT-
Negative-Going Input Threshold
Voltage at the A Input (Vee = Min)
VT+
Positive-Going Input Threshold
Voltage at the 8 Input (Vee = Min)
VT-
Negative-Going Input Threshold
Voltage at the 8 Input (Vee = Min)
10H
High Level Output Current
DM74121
Nom
Max
Min
5
5.5
4.75
1.4
2
4.5
0.8
1.4
1.5
0.8
0.8
2
1.3
Units
Nom
Max
5
5.25
V
1.4
2
V
1.4
V
1.5
0.8
2
V
-0.4
mA
16
mA
VIs
1.3
V
-0.4
10L
Low Level Output Current
tw
Input Pulse Width (Note 1)
dV/dt
Rate of Rise or Fall of
Schmidt Input (8) (Note 1)
1
1
dV/dt
Rate of Rise or Fall of
Logic Input (A) (Note 1)
1
1
V/p.s
REXT
External Timing Resistor (Note 1)
CEXT
DC
External Timing Capacitance (Note 1)
Duty Cycle (Note 1)
TA =
2S'C and Vee
40
ns
1.4
30
1.4
40
kn
0
1000
0
1000
p.F
RT=2kn
RT = REXT (Max)
Free Air Operating Temperature
TA
Note 1:
I
I
16
40
-55
67
67
90
90
125
0
70
%
'C
= SV.
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 1)
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vee = Min, 11= -12 mA
VOH
High Level Output
Voltage
Vcc = Min, 10H = Max,
VIL = Max, VIH = Min
VOL
Low Level Output
Voltage
Vee = Min, 10L = Max,
VIH = Min, VIL = Max
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 5.5V
IIH
High Level Input
Current
Vec = Max
VI = 2.4V
Al,A2
40
8
80
Low Level Input
Current
Vee = Max
VI = O.4V
Al,A2
-1.6
8
-3.2
Short Circuit
Output Current
Vce = Max
(Note 2)
DM54
-20
-55
DM74
-18
-55
Supply Current
Vce = Max
Quiescent
13
25
Triggered
23
40
IlL
los
Icc
Note 1: All typicals are at Vee = 5V,
TA =
2S·C.
Note 2: Not more than one output should be shorted at a time.
4-117
2.4
3.4
0.2
V
0.4
V
1
mA
p.A
mA
mA
mA
....N
....
Switching Characteristics
at Vee
=
5V and TA
Parameter
From (Input)
To (Output)
tpLH
Propagation Delay Time
Low to High Level Output
A1,A2
toO
tpLH
Propagation Delay Time
Low to High Level Output
Bto
tpHL
Propagation Delay Time
High to Low Level Output
tpHL
Propagation Delay Time
High to Low Level Output
tW(OUT)
Output Pulse
Width Using the
Internal Timing Resistor
Symbol
tw(OUT)
tW(OUT)
=
25°C (See Section 1 for Test Waveforms and Outout Load)
Conditions
Min
Max
Units
70
ns
55
ns
A1,A2
toO
80
ns
B
toO
65
ns
150
ns
50
ns
600
800
ns
6
8
ms
CEXT = 80pF
RINT to Vee
CL = 15pF
RL = 400.0
a
A1,A20rB
toO,a
CEXT = 80pF
RINT to Vee
RL = 400.0
CL = 15 pF
Output Pulse
Width Using Zero
Timing Capacitance
A1,A2
toO,a
CEXT = OpF
RINTtoVee
RL = 400.0
CL = 15pF
Output Pulse
Width Using External
Timing Resistor
A1,A2
toO,a
CEXT = 100pF
RINT = 10k.o
RL = 400.0
CL = 15pF
A1,A2
toO,a
CEXT = 1,...F
RINT = 10 k.o
RL = 400.0
CL = 15pF
70
Operating Rules
105
1. To use the internal 2 k.o timing resistor, connect the RINT
pin to Vee.
2. An external resistor (Rx) or the internal resistor (2 k.o)
and an external capacitor (Cx) are required for proper
operation. The value of Cx may vary from 0 to any necessary value. For small time constants use high-quality
mica, glass, polypropylene, polycarbonate, or polystyrene
capacitors. For large time constants use solid tantalum or
special aluminum capacitors. If the timing capacitors
have leakages approaching 100 nA or if stray capacitance from either terminal to ground is greater than 50 pF
the timing equations may not represent the pulse width
the device generates.
3. The pulse width is essentially determined by external timing components Rx and Cx. For Cx < 1000 pF see Figure 1 deSign curves on Twas function of timing components value. For Cx > 1000 pF the output is defined as:
TA=2SoC
Vcc=5.0V
104
!
]a
R=SOK
f=R=2SK
103
~
102
"R=1.4K.
~R=SK
10
10
100
CEXT (pF)
1000
TUF/653B-2
FIGURE 1
4. If Cx is an electrolytic capacitor a switching diode is often
required for standard TTL one-shots to prevent high inverse leakage current (Figure 2).
tw = KRxCx
where [Rx is in Kilo-ohm!
..
[CX is in pico Farad!
[TW is in nano second!
[K::::: 0.7!
Rx
0
~'"""
Cx
l--
PIN (10)
TL/F/6538-3
FIGURE 2
4-118
r-------------------------------------------------------------------------------------,
Operating Rules
(Continued)
5. Output pulse width versus Vee and operation temperatures: Figure 3 depicts the relationship between pulse
width variation versus Vee. Figure 4 depicts pulse width
variation versus ambient temperature.
6. The uK" coefficient is not a constant, but varies as a
function of the timing capacitor Cx. Figure 5 details this
characteristic.
100 ~F
10
10
REXT=5K
CEXT= 1000 pF
TA =25°C
r--
--
w
..
'"
z
co:
::c
f-""""
~
1l
-5
~F
1 ~F
8 0.1 ~F
.. 104 pF
103 pF
102 pF
10 pF
0 .2
-10
4
4.5
5
5.5
.4 .6 .8 1.0 1.2 1.4 1.6
"K" COEFFICIENT
TL/F/8538-6
Vee (V)
FIGURE 5
TUF/6538-4
FIGURE 3
10
REXT=5K
CEXT=1000 pF
Vee=5.0V
'" i'-5
7. Under any operating condition Cx and Ax must be kept
as close to the one-shot device pins as possible to minimize stray capacitance, to reduce noise pick-up, and to
reduce I x A and Ldi/dt voltage developed along their
connecting paths. If the lead length from Cx to pins (10)
and (11) is greater than 3 cm, for example, the output
pulse width might be quite different from values predicted
from the appropriate equations. A non-inductive and low
capacitive path is necessary to ensure complete discharge of Cx in each cycle of its operation so that the
output pulse width will be accurate.
r-....
.........
-
r-
-10
-60 -30 0 30 60 90 120 150
AMBIENT TEMPERATURE (OC)
TUF/6538-5
FIGURE 4
8. Vee and ground wiring should conform to good high-frequency standards and practices so that switching transients on the Vee and ground return leads do not cause
interaction between one-shots. A 0.01 ,..F to 0.10 ,..F bypass capacitor (disk ceramic or monolithic type) from Vee
to ground is necessary on each device. Furthermore, the
bypass capacitor should be located as close to the Veepin as space permits.
For further detailed device characteristics and output performance please
refer to the NSC one·shot application note, AN·3S6.
4-119.
-4
to.)
-4
~
~
..-
r----------------------------------------------------------------------------,
'?'A National
~ Semiconductor
54122/DM74122
Retriggerable Resettable Multivibrator
General Description
The '122 features positive and negative DC level triggering
inputs, complementary outputs, an optional 10 kn internal
timing resistor and an overriding Direct Clear (CD) input.
When the circuit is in the quasi-stable (delay) state, another
trigger applied to the inputs (per Truth Table) will cause the
delay period to start again, without disturbing the outputs.
This process can be repeated indefinitely and thus the output pulse period (0 HIGH, LOW) can be made as long as
desired. Alternatively, a delay period can be terminated
by a LOW signal applied to Co, which also prevents triggering. An internal connection from Co to the input gate makes
it possible to trigger the circuit by a positive-going signal on
Co, as shown in the Truth Table. For timing capacitor values
greater than 1000 pF, the output pulse width is defined as
follows:
Connection Diagram
Logic Symbol
Iw = 0.32 RxCx (1.0 + 0.7/Rx)
Where tw is in ns, Rx is in kn and Cx is in pF.
a
13
11
Dual-In-Llne Package
14
Vee
A2
2
13
RxCx
NC
Al
81
3
12
82
4
11
CD
5
10
Q
6
9
GND
7
8
3
4
RINT
Q
5
TLlF/10212-2
Vee = Pin 14
GNO = Pin 7
NC = Pins 10 and 12
TLlF/10212-1
Pin Names
Al,A2
8 1,82
0,0
6
Cx
NC
Order Number 54122DMQB, 54122FMQB or DM74122N
See NS Package Number J14A, N14A or W14B
Co
8
1
2
Description
Trigger Inputs (Active Falling Edge)
Trigger Inputs (Active Rising Edge)
Direct Clear Inputs (Active LOW)
Outputs
4-120
......
Absolute Maximum Ratings
N
N
(Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
54
-55'Cto +125'C
DM74
O'Cto +70'C
Storage Temperature Range
- 65'C to + 150'C
Recommended Operating Conditions
Symbol
54122
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
Low Level Input Voltage
10H
High Level Output Current
10L
Low Level Output Current
TA
Free Air Operating Temperature
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.5
0.8
0.8
V
-0.8
-0.8
mA
16
mA
70
'C
16
-55
125
Parameter
-55
+5.0V, TA = +25'C
DM74
Conditions
Min
Trigger Pulse Width
Rx
External Timing Resistor
I
I
Cx
Units
Max
40
XC
Over Operating Vee and
Temperature Range
XM
V
V
2
Recommended Operating Conditions Vee =
Iw
Units
Nom
2
VIL
Symbol
DM74122
Min
ns
5.0
50
5.0
25
kn
No Restrictions
External Timing Capacitor
pF
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
VI
Input Clamp Voltage
Vee = Min, II = -12 mA
VOH
High Level Output Voltage
Vee = Min, 10H = Max,
VIL = Max
VOL
Low Level Output Voltage
Vee = Min, VIH = Min
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 5.5V
IIH
High Level Input Current
Vee = Max, VI = 2.4V
IlL
Low Level Input Current
Vee = Max, VI = 0.4V
los
Short Circuit Output Current
Vee = Max (Note 2)
Icc
Supply Current
Vee = Max
Min
Max
Units
-1.5
V
2.4
V
0.4
V
1
mA
Inputs
40
Clear
80
Inputs
-1.6
Clear
-3.2
-10
Nole I: All typical. are at Vee = 5V. TA = 25·C.
Nole 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
4-121
Typ
(Note 1)
/LA
mA
-40
mA
28
mA
III
Switching Characteristics
Vee = +5.0V. TA = + 25°C (See Section 3 for waveforms and load configurations)
54174
Symbol
Parameter
Conditions
CL = 15pF
RL = 4000.
Min
tpLH
Propagation Delay
BtoO
tpLH
Propagation Delay
AtoO
tpLH
Propagation Delay
Btoa
tpHL
Propagation Delay
Atoa
tpLH
Propagation Delay
CDtoa
Cx = 0 pF. Rx = 5 ko.
Figure 3-1. Figure s
Cx = 0 pF. Rx = 5 ko.
Figure 3-1, Figure 3-10
tpHL
Propagation Delay
CDtoO
lw(out)
Pulse Width at 0 with Zero
Timing Capacitor
Cx = 0 pF. Rx = 5 ko.
Figure 3-1. Figure s
tw(out)
Pulse Width with External
Timing Components
Cx = 1000 pF. Rx = 10 ko.
Figure 3-1. Figures
Triggering Truth Table
Inputs"
Response
CD
A1
A2
81
82
L
X
X
H
X
"""""""""-
X
L
X
H
X
X
L
H
X
X
X
H
No Trigger
No Trigger
No Trigger
Trigger
X
H
L
L
X
H
X
X
.../
.../
.../
H
L
X
H
H
No Trigger
No Trigger
Trigger
Trigger
X
X
H
.../
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
'Input pins 1 and 2 are logically interchangeable. as are Input pins 3 and 4.
4-122
3.08
Units
Max
28
ns
33
ns
36
ns
40
ns
40
ns
27
ns
65
ns
3.76
p.s
r----------------------------------------------------------------------------, __
~
Pulse Width vs Rx and Cx
30 kD.
20 kD.
15 kD.
10 kD.
7.5 kD.
5.0 kD.
on
c
~
....~
103
8
~ ~~
~
['\
"-
'/
"- '\.1\..
~
.-
:::l
I>.
,
.~ I'\~
5
",,'"
~ ~~
!30
....
~
III
0
i.--'~
i--'~
102
8
--
I>.
2
3 4
,V
'" [,.'< >'
. /~ ~
)'"
10
1.0
~
6 B 10
2
3 4
6 8102
2
3 4
6 8103
TIMING CAPACITOR Cx - pF
TL/F/10212-3
Timing Capacitor Cx-pF
TL/F/10212-4
FIGURE A
4·123
~National
~ Semiconductor
54123/DM74123 Dual Retriggerable One-Shot with
Clear and Complementary Outputs
General Description
Features
The '123 is a dual retriggerable monostable multivibrator
capable of generating output pulses from a few nano-seconds to extremely long duration up to 100% duty cycle.
Each device has three inputs permitting the choice of either
leading-edge or trailing edge triggering. Pin (A) is an activelow transition trigger input and pin (8) is an active-high transition trigger input. The clear (ClR) input terminates the output pulse at a predetermined time independent of the timing
components.
• DC triggered from active-high transition or active-low
transition inputs
• Retriggerable to 100% duty cycle
• Direct reset terminates output pulse
• Compensated for Vee and temperature variations
• DTl, TTL compatible
• Input clamp diodes
National's '123 device features a unique logic realization not
implemented by other manufacturers. The "Clear" input will
not trigger the device, a design tailored for applications
where it shall only terminate or reduce a liming pulse.
To obtain the besl and trouble free operation from this device please read the operating rules as well as the NSC
one-shot application notes carefully and observe recommendations.
Functional Description
The basic output pulse width is determined by selection of
an external resistor (Rx) and capaCitor (Cx). Once triggered,
the basic pulse width may be extended by retriggering the
gated active-low transition or active-high transition inputs or
be reduced by use of the active-low transition clear input.
Retriggering to 100% duty cycle is possible by application of
an input pulse train whose cycle time is shorter than the
output cycle time such that a continuous "HIGH" logic state
is maintained at the "a" output.
Connection Diagram
Dual-In-Llne Package
Triggering Truth Table
Inputs
<1:XT 1
14
Ql
13
Q2
CLR 2
B2
12
Response
A
B
CLR
x
X
l
l
X
"-
H
H
No Trigger
No Trigger
Trigger
H
l
.J
.J
l
H
X
H
.J
No Trigger
Trigger
Trigger
"-
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
5
Bl
CLR 1
Q2
TL/F/6539-1
Order Number 54123DMQB, 54123FMQB or DM74123N
See NS Package Number J16A, N16A or W16A
4-124
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be gua.ranteed The device should not be operated at these limits. The
parametric values defined in the "£Iectrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
54
- 55'C to + 125'C
DM74
O'Cto +70'C
Storage Temperature
-65'Cto +150'C
Recommended Operating Conditions
Symbol
54123
Parameter
Vcc
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
DM74123
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
0.8
0.8
V
2
2
V
IOH
High Level Output Current
-0.8
-0.8
mA
IOL
Low Level Output Current
16
16
mA
tw
Pulse Width
(Note 5)
Twa
(Min)
Minimum Width of
Pulse at (Note 5)
AorB High
40
AorB Low
40
Clear Low
40
AorB
a
REXT
External Timing Resistor
CEXT
External Timing Capacitance
CWIRE
Wiring Capacitance
at REXT/CEXT Terminal (Note 5)
TA
Free Air Operating Temperature
ns
80
5
65
ns
50
kO
No Restriction
-55
125
0
/L F
50
pF
70
'C
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
= Min, II = -12 mA
= Min, IOH = Max
VIL = Max, VIH = Min
Vee = Min, IOL = Max
VIH = Min, VIL = Max
Vee = Max, VI = 5.5V
VI
Input Clamp Voltage
Vee
VOH
High Level Output
Voltage
Vee
VOL
Low Level Output
Voltage
II
Input Current @ Max
Input Voltage
IIH
High Level Input
Current
Vee = Max
VI = 2.4V
Low Level Input Current
Vee
IlL
los
Short Circuit
Output Current
= Max, VI = 0.4V
Vee = Max
(Note 2)
Min
54
2.4
DM74
2.5
Typ
(Note 1)
Max
Units
-1.5
V
3.4
0.2
V
0.4
V
1
mA
Data
40
Clear
80
Clear
-3.2
Data
-1.6
54
-10
-40
DM74
-10
-40
/LA
mA
mA
Supply Current
Vee = Max (Notes 3 and 4)
46
66
mA
Icc
Nate 1: All typlcals are at Vce = 5V. TA = 25'C.
Nate 2: Not more than one output should be shorted at a time.
Nate 3: Quiescent Icc is measured (after clearing) wnh 2.4V applied to all clear and A inputs. B inputs grounded, all outputs open,CEXT = 0.02 fLF. and REXT =
25 KO.
Nate 4: Icc i. measured in the triggered state with 2.4Y applied to all clear and B Inputs, A inputs grounded. all outputs open, CEXT = 0.02 fLF. and REXT = 25 kO.
Note 5: TA = 25'C and Yee = 5V.
4-125
Switching Characteristics
at Vee
= 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
54123
DM74123
CL = 15 pF, RL = 4000
CEXT = 0 pF, REXT = 5 kO
Min
Max
CL = 15 pF, RL = 4000
CEXT = 1000 pF, REXT = 10 KO
Min
Max
Parameter
From (Input)
To (Output)
tpLH
Propagation Delay Time
Low to High Level Output
AtoO
33
33
ns
tpLH
Propagation Delay Time
Low to High Level Output
BtoO
28
28
ns
tpHL
Propagation Delay Time
High to Low Level Output
AtoO
40
40
ns
tpHL
Propagation Delay Time
High to Low Level Output
BtoO
36
36
ns
tpLH
Propagation Delay Time
Low to High Level Output
Clear to 0
40
40
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clear to 0
27
27
ns
Output Pulse Width'
AorBtoO
3.76
/Ls
Symbol
tw(out)
'CECT
3.08
3.76
3.08
Units
= 1000 pF. RElIT = 10 kO
Operating Rules
1. An external resistor (RX> and external capacitor (Cx) are
required for proper operation. The value of Cx may vary
from 0 to any necessary value. For small time constants
high-grade mica, glass, polypropylene, polycarbonate, or
polystyrene material capacitors may be used. For large
time constants use tantalum or special aluminum capacitors. If the timing capacitors have leakages approaching
100 nA or if stray capacitance from either terminal to
ground is greater than 50 pF the timing equations may
not represent the pulse width the device generates.
2. When an electrolytic capacitor is used for Cx a switching
diode is often required for standard TTL one-shots to prevent high inverse leakage current (Figure 2). However, its
use in general is not recommended with retriggerable operation.
3. The output pulse width (Tw) for Cx > 1000 pF is defined
as follows:
TW = K Rx Cx (1 + O.71Rx)
where [Rx is in Kilo-ohm]
[Cx is in pico Farad]
[Tw is in nano second]
[K:::: 0.34]
4. The multiplicative factor K is plotted as a function of CX
below for design considerations:
100 "F
Rx
ex
l-PIN(6)
TLIF/6539-3
FIGURE 2
5. For Cx < 1000 pF see Figure 3 for Tw vs Cx family
curves with Rx as a parameter:
105
.s
~
10
-R=SOK
~ ~.
It'
R=IOK
R-251<,
100
10
1000
CEXT (pF)
TLIF16539-4
FIGURE 3
6. To obtain variable pulse width by remote trimming, the
following circuit is recommended:
Vcc-&.ov
PIN (7)
Rx
PI"'~il
I
D.l"F
11J4pF
ex
Rremota
PIN (61
198pF
~"~
l02pF
lDpF
103
102
I "F
j
lA=2S"C
vcc=s.ov
104
lA-25°C
10 "F
D
... ~~m
1'-1'-
-
TL/F/6539-5
Note: "R,emoto" should be as close to the one·shot as possible.
••
.• 1.0 1.2 1.4 1.6
0 .2 .4
"K" COEFFICIENT
FIGURE 4
TLlF/6539-2
FIGURE 1
4-126
r-------------------------------------------------------------------------------------,
Operating Rules
(Continued)
7. The retriggerable pulse width is calculated as shown below:
10
T = Tw + tpLH = KX Rx x Cx + tpLH
The retriggered pulse width is equal to the pulse width
plus a delay time period (Figure 5).
"-
"
REXT a lOK
CEXT a 1000 pF
VCC-5.0V
r--....
INPUT
-5
OUTPUT
-10
-60 -30
TL/F/6539-6
FIGURES
90 120 150
9. Under any operating condition Cx and Rx must be kept
as close to the one-shot device pins as possible to minimize stray capacitance, to reduce noise pick-up, and to
reduce I x Rand Ldi/dt voltage developed along their
connecting paths. If the lead length from Cx to pins (6)
and (7) or pins (14) and (15) is greater than 3 cm, for
example, the output pulse width might be quite different
from values predicted from the appropriate equations. A
non-inductive and low capacitive path is necessary to
ensure complete discharge of Cx in each cycle of its
operation so that the output pulse width will be accurate.
'"
..,'"C
~
Z
~
-5
-10~--~--~--~--~
5.5
VCC (V)
TLlF/6539-7
FIGURE 6
60
"
TLlF/6539-6
III
4.5
30
~
FIGURE 7
REXT a 5K
CEXT a lOOO pF
TA=2S·C
4
0
.........
AMBIENT TEMPERATURE ,·C)
B. Output pulse width versus Vee and Temperatures: Figure
6 depicts the relationship between pulse width variation
versus operating Vee. Figure 7 depicts pulse width variation versus ambient temperatures.
10
~
I\)
Col)
10. The CEXT pins of this device are internally connected to
the internal ground. For optimum system performance
they should be hard wired to the system's return ground
plane.
• However, it should be noted that although the 74221
series one-shot is pin-for-pin compatiable with the
'123 device, its CEXT pin is not an internal connection
to ground. Hence, if substitution of an '221 on to an
'123 design layout whose CEXT pin is wired to the
ground is attempted, the '221 device will not functionl
11. Vee and ground wiring should conform to good high-frequency standards and practices so that switching transients on the Vee and ground return leads do not cause
interaction between one-shots. A 0.01 IlF to 0.10 IlF
bypass capacitor (disk ceramic or monolithic type) from
Vee to ground is necessary on each device. Furthermore, the bypass capacitor should be located as close
to the Vee pin as space permits.
'For further detailed device characteristics and output performance
please refer to the NSC one-shot application note, AN-366•
•
4-127
~National
~ Semiconductor
54125/DM54125/DM74125
Quad TRI-STATE® Buffers
General Description
To minimize the possibility that two outputs will attempt to
take a common bus to opposite logic levels, the disable time
is shorter than the enable time of the outputs.
This device contains four independent gates each of which
performs a non-inverting buffer function. The outputs have
the TRI-STATE feature. When enabled, the outputs exhibit
the low impedance characteristics of a standard TTL output
with additional drive capability at the high Logic level to permit the driving of bus lines without external pull-up resistors.
When disabled, both the output transistors are turned off
presenting a high-impedance state to the bus line. Thus the
output will act neither as a significant load nor as a driver.
Features
• Alternate Military/Aerospace device (54125) is available. Contact a National Semiconductor Sales Officel
Distributor for specifications.
Connection Diagram
Dual-In-Llne Package
VCC
C4
114
1
C1
A4
13
12
Ai
V4
12
C3
11
13
4
Vi
C2
A3
9
10
15
16
Y2
A2
V3
8
17
GND
TLlF/6540-1
Order Number 54125DMOB, 54125FMOB, DM54125J, DM54125W or DM74125N
See NS Package Number J14A, N14A or W14B
Function Table
Y=A
Inputs
Output
A
C
Y
L
H
L
L
X
H
L
H
Hi-Z
H = High logic Level
L = Low logic Level
X = Either Low or High Logic Level
HI-Z = TRI-5TATE (OUtputs are disabled)
4-128
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Input Voltage
5.5V
Operating Free Air Temperature Range
DM54 and 54
- 55·C to + 125·C
DM74
O·Cto +70·C
Storage Temperature Range
- 65·C to + 150·C
Recommended Operating Conditions
Symbol
DM54125
Parameter
DM74125
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
Vee
Supply Voltage
VIH
High Level Input Voltage
Vil
Low Level Input Voltage
0.8
0.8
V
IOH
High Level Output Current
-2
-5.2
mA
16
mA
70
·C
2
IOl
Low Level Output Current
TA
Free Air Operating Temperature
2
V
16
-55
125
V
0
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
VI
Input Clamp Voltage
Vee = Min, 11= -12 mA
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
Vil = Max, VIH = Min
Val
Low Level Output
Voltage
Vee = Min, IOl = Max
VIH = Min, Vil = Max
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 5.5V
Min
2.4
Typ
(Note 1)
Max
Units
-1.5
V
3.3
0.2
V
0.4
V
1
mA
IIH
High Level Input Current
Vee = Max, VI = 2.4V
40
p.A
III
Low Level Input Current
Vee = Max, VI = O.4V
-1.6
mA
IIZl
Off-State Input Current
with Low Level Input
Voltage Applied
Vee = Max, VI = 0.4V
-40
p.A
Off-State Output Current
with High Level Output
Voltage Applied
Vee = Max, Va = 2.4V
VIH = Min, Vil = Max
40
p.A
Off-State Output Current
with Low Level Output
Voltage Applied
Vee = Max, Va = O.4V
VIH = Min, Vil = Max
-40
p.A
Short Circuit
Output Current
Vee = Max
(Note 2)
10ZH
10Zl
los
Icc
Nole
Supply Current
1: All typicals are at Vcc ~ sv, TA
L DM54
I DM74
-30
-70
-28
-70
Vee = Max (Note 3)
~
2S"C.
Nola 2: Not more than one output should be shorted at a time.
Nole 3:
Icc Is measured wtth the output control (C) inputs at 4.SV, the data inputs grounded, and the outputs open.
4-129
36
54
mA
mA
Switching Characteristics at Vee =
5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
RL
Symbol
Parameter
CL
= 5pF
Min
= 4000.
CL
Max
Min
=
Units
50pF
Max
tpLH
Propagation Delay Time
Low to High Level Output
15
ns
tpHL
Propagation Delay Time
High to Low Level Output
18
ns
tPZH
Output Enable Time to
High Level Output
18
ns
tPZL
Output Enable Time to
Low Level Output
25
ns
tpHZ
Output Disable Time from
High Level Output
8
ns
tpLZ
Output Disable Time from
Low Level Output
14
ns
4·130
,----------------------------------------------------------------------,
Co)
N
~National
~ Semiconductor
DM54132/DM74132 Quad 2-lnput NAND Gates with
Schmitt Trigger Inputs
General Description
This device contains four independent gates each of which
performs the logic NAND function. Each input has hysteresis which increases the noise immunity and transforms a
slowly changing input signal to a fast changing, jitter-free
output.
Connection Diagram
Dual·ln·Llne Package
Vee
84
V4
A4
83
A3
V3
Y2
GNU
10
Al
VI
81
A2
82
TUF/6542-1
Order Number DM54132J or DM74132N
See NS Package Number J14A or N14A
Function Table
y= AB
Inputs
Output
A
B
V
L
L
H
H
L
H
L
H
H
H
H
L
H = High Logic Level
L
= Low Logic Level
•
4-131
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Input Voltage
5.5V
Operating Free Air Temperature Range
- 55·C to + 125·C
DM54
DM74
O·Cto +70·C
Storage Temperature Range
- 65·C to + 150·C
Recommended Operating Conditions
Symbol
DM54132
Parameter
DM74132
Units
Min
Typ
Max
Min
Typ
Max
Vee
Supply Voltage
4.5
5
5.5
4.75
5
5.25
VT+
Positive-Going Input
Threshold Voltage (Note 1)
1.5
1.7
2
1.5
1.7
2
VT-
Negative-Going Input
Threshold Voltage (Note 1)
0.6
0.9
1.1
0.6
0.9
1.1
V
HYS
Input HystereSis (Note 1)
0.4
0.8
0.4
0.8
IOH
High Level Output Current
-0.8
mA
16
mA
70
·c
-0.8
IOL
Low Level Output Current
TA
Free Air Operating Temperature
16
-55
125
0
V
V
V
Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
=
=
VI
Input Clamp Voltage
Vee
VOH
High Level Output
Voltage
Vee = Min, IOH
VI = VT-Min
VOL
Low Level Output
Voltage
Vee = Min, IOL = Max
VI = VT+Max
IT+
Input Current at
Positive-Going Threshold
Vee
5V, VI
=
VT+
IT-
Input Current at
Negative-Going Threshold
Vee = 5V, VI
=
VT-
II
Input Current @ Max
Input Voltage
Vee
IIH
High Level Input Current
Vee
IlL
Low Level Input Current
los
Short Circuit
Output Current
=
Min,ll
Max
Max, VI
=
5.5V
=
Vee =
Vee =
Max, VI
=
=
2.4V
Max, VI
DM54
2.4
3.4
DM74
2.4
3.4
Vee
=
Max
leeL
Supply Current with
Outputs Low
Vee
=
Max
0.2
= SV.
= SV, TA = 2S'C.
Nole 3: Not more than one output should be shorted at a time.
4-132
Max
Units
-1.5
V
V
0.4
V
-0.43
mA
-0.56
mA
1
-0.8
0.4V
Max
(Note 3)
Supply Current with
Outputs High
Nole 2: All typical. are at Vet;
Typ
(Note 2)
-12 mA
=
=
leeH
Note 1: Vet;
Min
Conditions
mA
40
p,A
-1.2
mA
DM54
-18
-55
DM74
-18
-55
mA
15
24
mA
26
40
mA
Switching Characteristics at Vee = 5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
Symbol
RL = 400.0.
CL = 15pF
Parameter
Min
Units
Max
tpLH
Propagation Delay Time
Low to High Level Output
22
ns
tpHL
Propagation Delay Time
High to Low Level Output
22
ns
4-133
J?'A National
~ Semiconductor
DM54145/DM74145
BCD to Decimal Decoders/Drivers
General Description
Features
These BCD-to-decimal decoders/drivers consist of eight inverters and ten, four-input NAND gates. The inverters are
connected in pairs to make BCD input data available for
decoding by the NAND gates. Full decoding of BCD input
logic ensures that all outputs remain off for all invalid (1015) binary input conditions. These decoders feature highperformance, NPN output transistors designed for use as
indicator/relay drivers, or as open-collector logic-circuit drivers. The high-breakdown output transistors are compatible
for interfacing with most MOS integrated circuits.
• Full decoding of input logic
• 80 mA sink-current capability
• All outputs are off for invalid BCD input conditions
Connection Diagram
Function Table
Dual-In-Llne Package
INPUTS
\
B
A
15
C
14
D
,
OUTPUTS
9
8
11
12
13
NO.~_I_n~pu_t_8__+-________0_u_t~p_ut_8________~
DeB A 0 1 2 3 4 5 6 7 8 9
7
10
o L L L L L H H H H H H H H H
9
L
L
L
L
5 L
6 L
7
L
B H
9
H
I
H
N H
V H
A H
L H
I H
1
2
3
4
3
2
o
\
2
5
4
3
4
7
6
5
6
18
GND
OUTPUTS
TLlF/6544-1
Order Number DM54145J, DM54145W or DM74145N
See NS Package Number J16A, N16E or W16A
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
o
H
4-134
= High Level (Off). L =
Low Level (On)
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Input Voltage
5.5V
Operating Free Air Temperature Range
-55'Cto +125'C
DM54
DM74
O'Cto +70'C
Storage Temperature Range
-65'Cto + 150'C
Recommended Operating Conditions
Symbol
DM54145
Parameter
DM74145
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
O.B
O.B
V
VOH
High Level Output Voltage
15
15
V
20
mA
70
'C
2
IOL
Low Level Output Current
TA
Free Air Operating Temperature
Electrical Characteristics
Symbol
2
V
20
-55
125
0
over recommended operating free air temperature range (unless otherwise noted)
Parameter
Conditions
Typ
(Note 1)
Min
= Min, II = -12 mA
Max
Units
VI
Input Clamp Voltage
Vee
-1.5
V
leEx
High Level Output
Current
Vee = Min, VOH = Max
VIL = Max, VIH = Min
250
p.A
VOL
Low Level Output
Voltage
Vee = Min, IOL = Max
VIH = Min, VIL = Max
0.4
V
IOL = SOmA
Vee = Min
II
Input Current @ Max
Input Voltage
Vee
IIH
High Level Input Current
Vee
IlL
Low Level Input Current
lee
Supply Current
Switching Characteristics
= Max, VI = 5.5V
Vee = Max
(Note 2)
at Vee
40
p.A
mA
I
DM54
43
62
DM74
43
70
mA
= 5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
Parameter
Conditions
CL = 15pF
RL = lOOn
tpHL
Propagation Delay Time
High to Low Level Output
Note 1: All typical. are at Vee = 5V, TA = 25'C.
Icc is measured with
mA
-1.6
J
Propagation Delay Time
Low to High Level Output
Note 2:
1
= Max, VI = 2.4V
Vee = Max, VI = 0.4V
tpLH
Symbol
0.9
0.5
all outputs open and all inputs grounded.
4-135
Min
Max
Units
30
ns
30
ns
~
.....
Logic Diagram
(9) OUTPUT 7
(10) OUTPUT 8
TL/F/6544-2
4-136
~National
~ Semiconductor
DM54148 Priority Encoder
General Description
Features
This TTL encoder features priority decoding of the input
data to ensure that only the highest-order data line is encoded, The DM54148 encodes eight data lines to three-line
(4-2-1) binary (octal), Cascading circuitry (enable input E1
and enable output EO) has been provided to allow octal expansion without the need for external circuitry, For all types,
data inputs and outputs are active at the low logic level,
• Encodes 8 data lines to 3-line binary (octal)
• Applications include:
N-bit encoding
Code converters and generators
Connection Diagram
Dual·ln·Llne Package
OUTPUTS
Vee 'EO
r16
15
14
2
4
INPUTS
GS' • 3
5
13
4
3
7
6
OUTPUT
0' AO
2
12
11
5
6
E1, ,A2
INPUTS
10
9
71 8
AI, GND
OUTPUTS
TLiF/6545-1
Order Number DM54148J or DM54148W
See NS Package Number J16A or W16A
Function Table
DM54148
Inputs
E1
0
H
L
L
L
L
L
L
L
L
L
X
H
X
X
X
X
X
X
X
L
outputs
2
3
4
5
6
7
A2
A1
AO
GS
EO
X
H
X
X
X
X
X
X
X
H
X
X
X
X
X
X
H
X
X
X
X
X
H
X
X
X
X
H
X
X
X
H
X
X
H
H
H
H
H
H
H
H
L
L
L
L
H
L
H
H
H
H
L
H
L
H
H
H
H
H
L
L
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H = High Logic Level, L = Low Logic Level, X = Don't Care
4·137
L
H
H
H
H
H
H
H
H
H
H
L
L
H
L
H
H
--
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
DM54
-55'C to + 125'C
- 65'C to + 150'C
Storage Temperature Range
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Recommended Operating Conditions
Symbol
DM54148
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
10H
High Level Output Current
Units
Min
Nom
Max
4.5
5
5.5
V
2
10L
Low Level Output Current
TA
Free Air Operating Temperature
V
-55
0.8
V
-0.8
mA
16
mA
125
'C
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 1)
= Min. II = -12 mA
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vcc
VOH
High Level Output
Voltage
Vee = Min. 10H = Max
VIL = Max. VIH = Min
VOL
Low Level Output
Voltage
Vee = Min. 10L = Max
VIH = Min. VIL = Max
II
Input Current @Max
Input Voltage
Vee
IIH
High Level Input
Current
Vee = Max
VI = 2.4V
o Input
40
Others
80
Low Level Input
Current
Vee = Max
VI = 0.4V
o Input
-1.6
Others
-3.2
los
Short Circuit
Output Current
Vee
ICCI
Supply Current
Vee
IlL
2.4
V
= Max. VI = 5.5V
= Max (Note 2)
= Max (Note 3)
Vee = Max (Note 4)
Supply Current
lee2
Note 1: All typicals are at Vee = 5V, TA = 25'C.
Note 2: Not more than one output should be shorted at a time.
Nota 3: ICCI is measured wHh Inputs El and 7 grounded, other Inputs and outputs open.
Note 4: IC02 is measured with all Inputs and all outputs open.
4-138
0.4
V
1
mA
/LA
mA
-85
mA
40
60
mA
35
55
mA
-35
Switching Characteristics at Vee = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
From (Input)
RL = 4000, CL = 15 pF
Parameter
Waveform
Units
Symbol
To (Output)
to AO, 1,2
tpHL
Propagation Delay Time
High to Low Level Output
othru 7
toAO, 1,2
tpLH
Propagation Delay Time
Low to High Level Output
Othru 7
toAO, 1, 2
tpHL
Propagation Delay Time
High to Low Level Output
Othru7
toAO, 1,2
tpLH
Propagation Delay Time
Low to High Level Output
othru 7
Propagation Delay Time
High to Low Level Output
othru 7
Propagation Delay Time
Low to High Level Output
othru 7
Propagation Delay Time
High to Low Level Output
othru 7
Propagation Delay Time
Low to High Level Output
E1 to
AO,1,2
tPHL
Propagation Delay Time
High to Low Level Output
E1 to
AO,1,2
tpLH
Propagation Delay Time
Low to High Level Output
E1 toGS
tpHL
Propagation Delay Time
High to Low Level Output
E1 toGS
tpLH
Propagation Delay Time
Low to High Level Output
E1 to EO
Propagation Delay Time
High to Low Level Output
E1 to EO
tpHL
tpLH
tpHL
tpLH
tpHL
Min
othru 7
Propagation Delay Time
Low to High Level Output
tpLH
to EO
In-Phase
Output
Out-of-Phase
Output
Out-of-Phase
Output
to EO
In-Phase
Output
toGS
toGS
In-Phase
Output
In-Phase
Output
In-Phase
Output
Max
15
ns
14
ns
19
ns
19
ns
10
ns
25
ns
30
ns
25
ns
16
ns
15
ns
13
ns
15
ns
15
ns
30
ns
•
4-139
~
.... Logic Diagram
0(10)
1 (11)
2
(12)
3 (13)
4 (1)
5 (2)
6 (3)
7 (4)
EI (5)
TL/F/6545-2
4-140
r--------------------------------------------------------------------------------. ...
...o•
~National
U\
...
~ Semiconductor
U\
l>
54150/DM54150/DM74150,
54151A/DM54151A/DM74151A
Data Selectors/Multiplexers
General Description
Features
These data selectors/multiplexers contain full on-chip decoding to select the desired data source. The 150 selects
one-of-sixteen data sources; the 151 A selects one-of-eight
data sources. The 150 and 151A have a strobe input which
must be at a low logic level to enable these devices. A high
level at the strobe forces the W output high and the Y output
(as applicable) low.
The 151 A features complementary Wand Y outputs, whereas the 150 has an inverted (W) output only.
•
•
•
•
•
•
The 151 A incorporates address buffers which have symmetrical propagation delay times through the complementary paths. This reduces the possibility of transients occurring
at the output(s) due to changes made at the select inputs,
even when the 151A outputs are enabled (i.e., strobe low).
150 selects one-of-sixteen data lines
151A selects one-of-eight data lines
Performs parallel-to-serial conversion
Permits multiplexing from N lines to one line
Also for use as Boolean function generator
Typical average propagation delay time, data input to W
output
150
11 ns
151A
9 ns
• Typical power dissipation
150
200 mW
151A 135 mW
• Alternate Military/Aerospace device (54150, 54151A) is
available. Contact a National Semiconductor Sales Office/Distributor for specifications.
Connection Diagrams
Dual-In-Une Package
.
Vee E8
1'24
Dual-In-Llne Package
.
DATA INPUTS
E9 El0 Ell E12 E13 E14 E15
23
22
21
20
19
2
3
456
DATA SELECT
14
DATA SELECT
DATA INPUTS
Vee D4
ABC
18
17
16
15
13
7
8
9
1011J12
116
D5
15
14
D6
D7
13
234
E7 E6 E5 E4 E3 E2 El EO STROBE W D GND
'--------------------'
OUT DATA
SELECT
DATA INPUTS
D3
D2
Dl
DATA INPUTS
TLlF/6546-1
DO
A
C
12
11
10
9
5
6
7
18
Y W STROBE GND
'-----'
OUTPUTS
TLlF/6546-2
Order Number 54151ADMQB, 54151AFMQB,
DM54151AJ, DM54151AW or DM74151AN
See NS Package Number J16A, N16E or W16A
Order Number 54150DQMB, 54150FMQB,
DM54150J or DM74150N
See NS Package Number J24A, N24A or W24C
4-141
c(
.,...
II)
.,...
•
~
.,...
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and speclflcatlons_
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
DM54 and 54
- 55·C to + 125·(;
O·Cto +70·C
DM74
-65·Cto +150·C
Storage Temperature Range
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Recommended Operating Conditions
Symbol
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
10H
High Level Output Current
10L
Low Level Output Current
TA
DM74150
DM54150
Parameter
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
2
Free Air Operating Temperature
Units
Min
-55
V
V
0.8
0.8
V
-0.8
-0.8
rnA
16
16
mA
70
·C
Max
Units
-1.5
V
125
0
'150 Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
= Min, II = -12 mA
Vee = Min, 10H = Max
VIL = Max, VIH = Min
Vee = Min, 10L = Max
VIH = Min, VIL = Max
Vee = Max, VI = 5.5V
VI
Input Clamp Voltage
VOH
High Level Output
Voltage
VOL
Low Level Output
Voltage
II
Input Current @ Max
Input Voltage
IIH
High Level Input Current
IlL
Low Level Input Current
= Max, VI = 2.4V
Vee = Max, VI = 0.4V
los
Short Circuit
Output Current
Vee = Max
(Note 2)
Typ
(Note 1)
Vee
2.4
V
Vee
I
I
V
1
mA
40
/LA
-1.6
mA
DM54
-20
-55
DM74
-18
-55
Vee = Max, (Note 3)
Supply Current
Icc
Note 1: All typlcals are at Vee = 5V, TA = 25'C.
Note 2: Not more than one output should be shorted at a time.
Note 3: lee Is measured with the strobe and data select inputs at 4.5V, all other Inputs and outputs open.
4-142
0.4
40
68
mA
mA
.....
g:
'150 Switching Characteristics
•
.....
UI
.....
at Vee = 5V and TA = 25·C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
RL = 4000, CL = 15 pF
From (Input)
To (Output)
Min
Units
l>
Max
tpLH
Propagation Delay TIme
Low to High Level Output
Select
toW
35
ns
tpHL
Propagation Delay Time
High to Low Level Output
Select
toW
33
ns
tpLH
Propagation Delay Time
Low to High Level Output
Strobe
toW
24
ns
tpHL
Propagation Delay Time
High to Low Level Output
Strobe
toW
30
ns
tpLH
Propagation Delay Time
Low to High Level Output
EO·E15
toW
20
ns
tpHL
Propagation Delay Time
High to Low Level Output
EO·E15
toW
14
ns
Recommended Operating Conditions
Symbol
DM54151A
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
IOH
High Level Output Current
IOL
Low Level Output Current
TA
Free Air Operating Temperature
DM74151A
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
0.8
0.8
V
-0.8
-0.8
mA
16
mA
70
·C
16
-55
V
V
2
125
0
II
4-143
....
c(
....
•
f&
....
In
'151 A Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 1)
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vee = Min,ll = -12mA
VOH
High Level Output
Voltage
Vee = Min, IOH = Max
VIL = Max, VIH = Min
VOL
Low Level Output
Voltage
Vee = Min,lOL = Max
VIH = Min, VIL = Max
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 5.5V
IIH
High Level Input Current
Vee = Max, VI = 2.4V
40
fJ-A
IlL
Low Level Input Current
Vee = Max, VI = 0.4V
-1.6
mA
los
Short Circuit
Output Current
Vee = Max
(Note 2)
Supply Current
Vee = Max, (Note 3)
lee
I
I
V
2.4
0.4
V
1
mA
DM54
-20
-55
DM74
-18
-55
27
48
mA
mA
Note 1: All typicals are at Vcc = 5V, TA = 2S'C.
Note 2: Not more than one output should be shorted at a time.
Note 3: Icc Is measured wHh the strobe and data select inputs at4.5V, all other Inputs and outputs open.
'151A Switching Characteristics
at Vec = 5V and TA = 25"C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
From (Input)
To (Output)
RL = 400n, CL = 15 pF
Min
Units
Max
tpLH
Propagation Delay Time
Low to High Level Output
Select
(4 Levels) to Y
38
ns
tpHL
Propagation Delay Time
High to Low Level Output
Select
(4 Levels) to Y
30
ns
tpLH
Propagation Delay Time
Low to High Level Output
Select
(3 Levels) to W
26
ns
tpHL
Propagation Delay TIme
High to Low Level Output
Select
(3 Levels) to W
30
ns
tpLH
Propagation Delay Time
Low to High Level Output
Strobe
toY
33
ns
tpHL
Propagation Delay Time
High to Low Level Output
Strobe
toY
30
ns
tpLH
Propagation Delay Time
Low to High Level Output
Strobe
toW
21
ns
tpHL
Propagation Delay Time
High to Low Level Output
Strobe
toW
25
ns
tpLH
Propagation Delay Time
Low to High Level Output
00·07
toY
24
ns
tpHL
Propagation Delay Time
High to Low Level Output
00·07
toY
24
ns
tpLH
Propagation Delay Time
Low to High Level Output
00·07
toW
14
ns
tpHL
Propagation Delay TIme
High to Low Level Output
00·07
toW
14
ns
4·144
r--------------------------------------------------------------------, -g:
--•
Logic Diagrams
UI
150
~
STROBE (9)
(ENABLE)
EO
(8)
)EI
(7)
}E2
(6)
)E3
E4
ES
E6
DATA
INPUlS
E7
(5)
-
(3)
(2)
E9
)}-
"""
)~
(I)
(23)
...:::::
'---
>"l
fEB
)-
-
(4)
(10)
ty
(22)
OUTPUT W
r-;::=:::
~
,-1
}EIO
Ell
(21)
""""
(20)
~
(19)
~
(18)
~
)}-
EI2
)E13
)EI4
EI5
(17)
(16)
(IS)
(14)
DATA
SELECT
(BINARY)
.-1_
A
IB _........
(13)
(II)
)-
I
A
.,
8
}
C
I~
~
~
TL/F/6546-3
4-145
......
•
...~
cC
LI)
Logic Diagrams
Address Buffers for
54151A174151A
151A
AABBCC
DATA[A~
SELECT
(BINARY)
B
c
TL/F/6546-5
» ....._.....:(:;:6) OUTPUT W
TUF/6546-4
See Address Buffers Below
Function Tables
54150174150
54151A/75151A
Inputs
Inputs
select
H
D
C
B
A
Strobe
S
X
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
X
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
X
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
X
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Low Level, X
= Don't Cere
= High Level, L =
Outputs
Select
C
B
A
Strobe
S
X
L
L
L
L
H
H
H
H
X
L
L
H
H
L
L
H
H
X
L
H
L
H
L
H
L
H
H
L
L
L
L
L
L
L
L
W
H
EO
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
E13
E14
E15
Outputs
H = High Level, L = Low Level, X = Don't Care
DO, 01 .•• 07 = the level of the respective 0 input
Eli, ~ ... "Ei5 = the complement of the level of the respective E Input
4-146
y
W
L
H
00
01
02
03
04
05
06
07
00
01
02
03
04
05
06
07
r-------------------------------------------------------------------------------~
Co)
~National
~ Semiconductor
54153/DM54153/DM74153 Dual 4-Line to 1-Line
Data Selectors/Multiplexers
General Description
Features
Each of these data selectors/multiplexers contains inverters and drivers to supply fully complementary, on-chip, binary decoding data selection to the AND-OR-invert gates.
Separate strobe inputs are provided for each of the two
four-line sections.
• Permits multiplexing from N lines to 1 line
• Performs parallel-to-serial conversion
• Strobe (enable) line provided for cascading (N lines to
n lines)
• High fan-out, low-impedance, totem-pole outputs
• Typical average propagation delay times
From data 11 ns
From strobe 1B ns
From select 20 ns
iii Typical power dissipation 170 mW
11:1 Alternate Military/Aerospace device (54153) is available. Contact a National Semiconductor Sales Office/
Distributor for specifications.
Connection Diagram
Function Table
Dual-In-Line Package
Select
Inputs
DATA INPUTS
STROBE A
vec
G2 SELECT 2C3
2C2
2Cl
• OUTPUT
2CO
V2
Data Inputs
Strobe
Output
B
A
CO
C1
C2
C3
G
Y
X
L
L
L
L
H
H
H
H
X
L
L
H
H
L
L
H
H
X
L
H
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
L
H
H
L
L
L
L
L
L
L
L
L
L
H
L
H
L
H
L
H
Select inputs A and 8 are common to bolh sections.
H = High Level, L = Low Level, X = Don't Care
STROBE
B
lC3
Gl SELECT'
lC2
...
CI1
ICl
lCO OUTPUT GND
VI
DATA INPUTS
TL/F/6547-1
Order Number 54153DMQB, 54153FMQB, DM54153J,
DM54153W or DM74153N
See NS Package Number J16A, N16E or W16A
4-147
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
OHlce/Dlstrlbutors for availability and speCifications.
Supply Voltage
7V
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Input Voltage
5.5V
Operating Free Air Temperature Range
DM54 and 54
-55'Cto + 125'C
DM74
O'Cto +70'C
Storage Temperature Range
-65'C to + 150'C
Recommended Operating Conditions
Symbol
DM54153
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
Vil
Low Level Input Voltage
10H
High Level Output Current
10l
Low Level Output Current
Free Air Operating Temperature
Symbol
Parameter
Units
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
0.8
0.8
V
-0.8
-0.8
mA
16
mA
70
'C
2
TA
Electrical Characteristics
DM74153
Min
2
V
16
-55
125
0
over recommended operating free air temperature range (unless otherwise noted)
Conditions
Min
Typ
(Note 1)
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vee=Min,11 = -12mA
VOH
High Level Output
Voltage
Vcc = Min, IOH = Max
Vil = Max, VIH = Min
VOL
Low Level Output
Voltage
Vce = Min, 10l = Max
VIH = Min, Vil = Max
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 5.5V
IIH
High Level Input Current
Vee = Max, VI = 2.4V
40
p.A
III
Low Level Input Current
Vee = Max, VI = O.4V
-1.6
mA
los
Short Circuit
Output Current
Vee = Max
(Note 2)
DM54
-20
-55
DM74
-18
-57
Supply Current
Vee = Max
(Note 3)
DM54
34
52
DM74
34
60
ICC
Note 1: All typicals are at Vee = 5V, TA = 25'C.
Note 2: Not more than one output should be shorted at a time.
Note 3: ICC is measured with the outputs open and all inputs grounded.
4·148
2.4
3.2
0.2
V
0.4
V
1
mA
mA
mA
...
Switching Characteristics
Symbol
at Vee
Parameter
= 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
From (Input)
RL = 4000, CL = 30 pF
Units
To (Output)
Max
Min
tpLH
Propagation Delay Time
Low to High Level Output
DatatoY
18
ns
tpHL
Propagation Delay Time
High to Low Level Output
DatatoY
23
ns
tpLH
Propagation Delay Time
Low to High Level Output
SelecttoY
34
ns
tpHL
Propagation Delay Time
High to Low Level Output
SelecttoY
34
ns
tpLH
Propagation Delay Time
Low to High Level Output
Strobe to Y
30
ns
tpHL
Propagation Delay Time
High to Low Level Output
Strobe to Y
23
ns
Logic Diagram
(1)
STROBE Gl
-=F1
(6)
lCO
...;
lCl (5)
(7) OUTPUT
VI
DATA 1
~-I
lC2 (4)
lC3 (3)
(2)
SELECT {
1
:{>-
I
\>-
B
A(14)
f2Cco(10)
(11)
2Cl
~
DATA 2
2C2(12)
....
(9) OUTPUT
V2
~
2C3(13)
(15)
STROBEG2
TLlF/6547-2
4-149
U'I
W
~
....
Ln
,----------------------------------------------------------------------------,
~National
~ Semiconductor
54154/DM54154/DM74154
4-Line to 16-Line Decoders/Demultiplexers
General Description
Features
Each or these 4-line-to-16-line decoders utilizes TIL circuitry to decode four binary-coded inputs into one of sixteen
mutually exclusive outputs when both the strobe inputs, G1
and G2, are low. The demultiplexing function is performed
by using the 4 input lines to address the output line, passing
data from one of the strobe inputs with the other strobe
input low. When either strobe input is high, all outputs are
high. These demultiplexers are ideally suited for implementing high-performance memory decoders. All inputs are buffered and input clamping diodes are provided to minimize
transmission-line effects and thereby simplify system design.
• Decodes 4 binary-coded inputs into one of 16 mutually
exclusive outputs
• Performs the demultiplexing function by distributing data
from one input line to anyone of 16 outputs
• Input clamping diodes simplify system deSign
• High fan-out, low-impedance, totem-pole outputs
• Typical propagation delay
3 levels of logic 19 ns
Strobe 18 ns
• Typical power dissipation 170 mW
• Alternate Military/Aerospace device (54154) is available. Contact a National Semiconductor Sales Office/
Distributor for specifications.
Connection Diagram
Dual-In-Line Package
INPUTS
vGC
124
ABC
23
22
21
OUTPUTS
G2 G1"15
D
20
19
18
17
14
16
1~
15
12
11'
14
13
0-
2
,o
1
3
2
4
3
5
4
6
5
7
6
OUTPUTS
8
7
9
8
10
9
11 .1.12
10, GND
TL/F/654B-1
Order Number 54154DMQB, 54154FMQB, DM54154J or DM74154N
See NS Package Number J24A, N24A or W24C
4-150
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Input Voltage
5.5V
Operating Free Air Temperature Range
-55'Cto + 125'C
DM54 and 54
O'Cto +70'C
DM74
Storage Temperature Range
-65'C to + 150'C
Recommended Operating Conditions
Symbol
Vee
Supply Voltage
V,H
High Level Input Voltage
V,L
Low Level Input Voltage
10H
High Level Output Current
10L
Low Level Output Current
Free Air Operating Temperature
Symbol
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
TA
Electrical Characteristics
DM74154
DM54154
Parameter
2
0.8
0.8
V
-0.8
-0.8
mA
16
mA
70
'C
16
-55
V
V
125
0
over recommended operating free air temperature range (unless otherwise noted)
Parameter
Conditions
Min
Typ
(Note 1)
Max
Units
-1.5
V
V,
Input Clamp Voltage
Vee = Min,l, = -12 mA
VOH
High Level Output
Voltage
Vee = Min,loH = Max
V,L = Max, V,H = Min
VOL
Low Level Output
Voltage
Vee = Min, 10L = Max
V,H = Min, V,L = Max
I,
Input Current @ Max
Input Voltage
Vee = Max, V, = 5.5V
I'H
I,L
High Level Input Current
Vee = Max, V, = 2.4V
40
poA
Low Level Input Current
Vee = Max, V, = O.4V
-1.6
mA
los
Short Circuit
Output Current
Vee = Max
(Note 2)
Supply Current
Vee = Max
(Note 3)
Icc
Nole 1: All typical. are at Vee
2.4
3.2
V
0.25
0.4
V
1
mA
OM 54
-20
-55
DM74
-18
-57
DM54
34
49
DM74
34
56
mA
mA
= SV, TA = 2S·e.
Note 2: Not more than one output should be shorted at a time.
Note 3: Icc is measured
w~h
all outputs open and all Inputs grounded.
Switching Characteristics
Symbol
at Vee = 5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
Parameter
From (Input)
To (Output)
RL = 4000, CL = 15 pF
Min
Units
Max
tpLH
Propagation Delay Time
Low to High Level Output
Data to
Output
36
ns
tpHL
Propagation Delay Time
High to Low Level Output
Data to
Output
33
ns
tpLH
Propagation Delay Time
Low to High Level Output
Strobe to
Output
30
ns
tpHL
Propagation Delay Time
High to Low Level Output
Strobe to
Output
27
ns
4-151
•
·...
1ft
,-----------------------------------------------------------------------------,
Function Table
Inputs
outputs
G1
G2
0
C
B
A
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
X X X X
X X X X
X X X X
H = HIgh Level, L = Low Level, X = Don't Care
Logic Diagram
~I-o-
A _
(1)
B_
e D
A
~I--.
(2)
~
(3)
B
18)
1
2
19)
(4)
~
INPUTS
(22)
B
A
1
A
1
ii
(5)
~
(6)
B
(7)
~
"""-
C
( 21)
e
-v
(8)
"""-
(10)
1-----
(11)
~"""-
(13)
D
I
4
5
6
7
OUTPUTS
D~
( 20
3
C
(9)
D
2
G
e
( 23
A
o
D
D
8
9
10
11
C
(14)
12
~
ii
(15)
13
A
~
(16)
14
G'-
A
B
4-152
e
i-
D-
(17)
TUF/654B-2
r--------------------------------------------------------------------------------, CII__
CII
~National
~ Semiconductor
DM54155/DM74155 Dual 2-Line to 4-Line
Decoders/Demultiplexers
General Description
These TTL circuits feature dual 1-line-to-4-line demultiplexers with individual strobes and common binary-address inputs in a single 16-pin package. When both sections are
enabled by the strobes, the common address inputs sequentially select and route associated input data to the appropriate output of each section. The individual strobes permit activating or inhibiting each of the 4-bit sections as desired. Data applied to input C1 is inverted at its outputs and
data applied at C2 is true through its outputs. The inverter
following the C1 data input permits use as a 3-to-S-line decoder, or 1-to-S-line demultiplexer, without external gating.
Input clamping diodes are provided on these circuits to minimize transmission-line effects and simplify system design.
Features
• Applications:
Dual 2-to-4-line decoder
Dual 1-to-4-line demultiplexer
3-to-S-line decoder
1-to-S-line demultiplexer
• Individual strobes simplify cascading for decoding or
demultiplexing larger words
• Input clamping diodes simplify system design
Connection Diagram and Function Tables
Dual-In-Llne Package
Y~C
DATA
STROBE
C2
G2
A
116 Ls l14 -113
2-Llne-to-4-Llne Decoder or
1-Llne-to-4-Line Demultiplexer
OUTPUTS
_ _ _ _ _ _-..
SE1.ECT
INPUT ,..2Y3
112
2Y2
2Yl
Outputs
Inputs
2YO
111 110 19
Select
Strobe
Data
B
A
G1
C1
1VO
1V1
1Y2
1Y3
x
X
H
X
H
H
L
L
H
H
L
H
H
L
L
H
H
H
H
L
H
H
L
L
L
L
H
H
H
H
H
L
X
L
H
H
H
H
H
H
H H
X X
Inputs
Select
11
DATA
Cl
TLlF/6S49-1
Order Number DM54155J, DM54155W or DM74155N
See NS Package Number J16A, N16A or W16A
H
H
L
H
Outputs
Strobe
Data
B
A
G2
C2
2YO
2Y1
2Y2
2Y3
X
L
X
L
H
L
X
H
H
L
H
H
L
L
H
H
L
H
H
H
H
H
H
H
L
L
L
X
L
L
L
L
H
H
H
H
H
H
H
L
H
H
H
L
X X
H
H
3-Line-to-8-Llne Decoder or
1-Llne-to-8-Llne Demultiplexer
Inputs
tC = inputs C1 and C2 connected together
*G = InpU1s G1 and G2 connected together
H = high level. L = low level. X = don't care
Select
ct
4-153
Outputs
g:r~=:
(0)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
B A
G:j:
2YO 2Y1 2Y2 2Y3 1VO 1Y1 1Y2 1Y3
XXX
LLL
LLH
LHL
LHH
HLL
H LH
HHL
HHH
H
L
L
L
L
L
L
L
L
H
H
H
H H
H
H
H
LHHHHHHH
HLHHHHHH
HHLHHHHH
H
H
H
L
H
H
H
H
HHHHLHHH
H
H
H
H H
L
H
H
H
H
H
H H
H
L
H
H
H
H
H H
H
H
L
•
Absolute Maximum Ratings
(Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The devies should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
DM54
- 55·C to + 125·C
DM74
O"Cto +70"C
-65·Cto + 150"C
Storage Temperature Range
Recommended Operating Conditions
Symbol
Vcc
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
DM74155
DM54155
Parameter
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
2
V
V
0.8
0.8
V
10H
High Level Output Current
-0.8
-0.8
mA
10L
Low Level Output Current
16
16
mA
TA
Free Air Operating Temperature
70
·c
Electrical Characteristics
Symbol
Parameter
-55
125
0
over recommended operating free air temperature range (unless otherwise noted)
Conditions
Min
VI
Input Clamp Voltage
Vcc=Min,ll= -12 mA
VOH
High Level Output
Voltage
Vcc = Min,loH = Max
VIL = Max, VIH = Min
VOL
Low Level Output
Voltage
Vcc = Min, 10L = Max
VIH = Min, VIL = Max
II
Input Current @ Max
Input Voltage
VCC = Max, VI= 5.5V
Typ
(Note 1)
Max
Units
-1.5
V
V
2.4
0.4
V
1
mA
IIH
High Levell nput Current
Vee = Max, VI = 2.4V
40
p.A
IlL
Low Level Input Current
Vee = Max, VI = 0.4V
-1.6
mA
los
Short Circuit
Output Current
Vee = Max
(Note 2)
-55
mA
Icc
Supply Current
Vcc = Max
(Note 3)
DM54
-20
DM74
-18
25
35
DM74
25
40
Note 1: All typlcals are at Vcc = 5V. TA = 25'C.
Note 2: Not more than one output should be shorted at a time.
Nole 3: Icc Is measured with the outputs open, A, B, and Cl Inputs at 4.5V, and C2, Gl, and G2 Inputs grounded.
4-154
-55
DM54
mA
....
Switching Characteristics
Symbol
at Vee
Parameter
=
5V and TA
=
From (Input)
To (Output)
25°C (See Section 1 for Test Waveforms and Output Load)
RL
= 4000, CL =
Min
15 pF
Units
Max
tpLH
Propagation Delay Time
Low to High Level Output
A,B,C2,G1
orG2toY
20
ns
tpHL
Propagation Delay Time
High to Low Level Output
A,B,C2,G1
orG2toY
27
ns
tpLH
Propagation Delay Time
Low to High Level Output
AorB
toY
FSC
ns
tpHL
Propagation Delay Time
High to Low Level Output
AorB
toY
32
ns
tpLH
Propagation Delay Time
Low to High Level Output
C1
toY
24
ns
tpHL
Propagation Delay Time
High to Low Level Output
C1
toY
27
ns
Logic Diagram
STROBE (2)
~OUTPUT
G'~
1YO
~OUTPUT
DATA (1)
C1
1Y1
~OUTPUT
1Y2
SELECT (3)
B
~OUTPUT
1Y3
~OUTPUT
SELECT (13)
A
2YO
V-
~OUTPUT
2Y1
DATA (15)
C2
~OUTPUT
STROBE (14)
G2
~OUTPUT
2Y2
2Y3
TL/F/6549-2
4·155
en
en
~National
~ Semiconductor
54157/DM54157/DM74157
Quad 2-Line to 1-Line Data Selectors/Multiplexers
General Description
Features
These data selectors/multiplexers contain inverters and
drivers to supply full on-chip data selection to the four output gates. A separate strobe input is provided. A 4-bit word
is selected from one of two sources and is routed to the four
outputs.
•
•
•
•
Applications
Buffered inputs and outputs
Typical propagation time 9 ns
Typical power dissipation 150 mW
Alternate Military/Aerospace device (54157) is available. Contact a National Semiconductor Sales Office/
Distributor for specifications.
• Expand any data input point
• Multiplex dual data buses
• Generate four functions of two variables (one variable
is common)
• Source programmable counters
Connection Diagram
Dual-In-Llne Package
STROBE
G
Vee
116
i
INP.UTS
OUTPUT
INPUTS
OUT
A4
B4
V4
• A3
B3'
V:UT
15
14
13
11
12
10
S ,A: B: Y14 A: B26
SELECT
INPUTS
i
OUTPUT '
INPUTS
i
v:
OUTPUT
9
G!~
TL/F/6550-1
Order Number 54157DMQB, 54157FMQB, DM54157J, DM54157W or DM74157N
See NS Package NumberJ16A, N16E or W16A
Function Table
Inputs
H
OutputY
Strobe
Select
A
B
H
X
X
L
L
L
L
L
L
L
X
X
X
H
H
H
X
X
H
L
L
H
H
= High Level, L = Low Level, X = Don't Care
4-156
L
L
Absolute Maximum Ratings
........
UI
(Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
DM54 and 54
-55'Cto + 125'C
DM74
O'Cto +70'C
Storage Temperature Range
-65'Cto + 150'C
Recommended Operating Conditions
Symbol
DM54157
Parameter
Vee
Supply Voltage
V,H
High Level Input Voltage
V,L
Low Level Input Voltage
DM74157
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
0.8
0.8
V
2
2
V
10H
High Level Output Current
-0.8
-0.8
mA
10L
Low Level Output Current
16
16
mA
TA
Free Air Operating Temperature
70
'C
-55
125
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
V,
Input Clamp Voltage
Vee = Min, I, = -12 mA
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
V,L = Max, V,H = Min
VOL
Low Level Output
Voltage
Vee = Min, 10L = Max
V,H = Min, V,L = Max
I,
Input Current @ Max
Input Voltage
Vee = Max, V, = 5.5V
Min
2.4
Typ
(Note 1)
Max
Units
-1.5
V
3.4
V
0.4
V
1
mA
I'H
High Level Input Current
Vee = Max, V, = 2.4V
40
/LA
I,L
Low Level Input Current
Vee = Max, V, = O.4V
-1.6
mA
los
Short Circuit
Output Current
Vce = Max
(Note 2)
I
I
DM54
-20
-55
DM74
-18
-55
Supply Current
Vee = Max (Note 3)
Icc
Hote 1: All typicals are at Vee = SV, TA = 2S'C.
Note 2: Not more than one output should be shorted at a time.
Hote 3: ICC is measured with 4.SV applied to all inputs and all outputs open.
4-157
30
48
mA
mA
Switching Characteristics at Vee =
Symbol
5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
From (Input)
To (Output)
Parameter
RL = 4000, CL = 15 pF
Min
Units
Max
tPLH
Propagation Delay Time
Low to High Level Output
Data
toY
14
ns
tpHL
Propagation Delay Time
High to Low Level Output
Data
toY
14
ns
tpLH
Propagation Delay Time
Low to High Level Output
Strobe
toY
20
ns
tpHL
Propagation Delay Time
High to Low Level Output
Strobe
toY
21
ns
tpLH
Propagation Delay Time
Low to High Level Output
Select
toY
23
ns
tpHL
Propagation Delay Time
High to Low Level Output
Select
toY
27
ns
Logic Diagram
157
A1 (2)
.......f.-.
(4) V1
81 (3)
t::::i
A2(5)
(7)
V2
82(6)
-
'""t::::i
A3(11)
(9) V3
B3(10)
t::J
.......-
A4 (14)
.--.
84(13)
~
SELECT~~
STROBE (15)
(12)
V4
-
;::=I
:{>TL/F/6550-2
4·158
r------------------------------------------------------------------------------------, c:n
»
J?;I National
~
~
•
~ Semiconductor
54161/DM54161A/DM74161A
DM54163A/DM74163A Synchronous 4-Bit Counters
General Description
These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting
deSigns. The 161A and 163A are 4-bit binary counters. The
carry output is decoded by means of a NOR gate, thus preventing spikes during the normal counting mode of operation. Synchronous operation is provided by having all f1ipflops clocked simultaneously so that the outputs change coincident with each other when so instructed by the countenable inputs and internal gating. This mode of operation
eliminates the output counting spikes which are normally
associated with asynchronous (ripple clock) counters. A
buffered clock input triggers the four flip-flops on the rising
(positive-going) edge of the clock input waveform.
These counters are fully programmable; that is. the outputs
may be preset to either level. As presetting is synchronous,
setting up a low level at the load input disables the counter
and causes the outputs to agree with the setup data after
the next clock pulse, regardless of the levels of the enable
input. Low-to-high transitions at th910ad input of the 161A
and 163A are perfectly acceptable, regardless of the logic
levels on the cloCk or enable inputs. The clear function for
the 161 A is asynchronous; and a low level at the clear input
sets all four of the flip-flop outputs low, regardless of the
levels of clock, load, or enable inputs. The clear function for
the 163A is synchronous; and a low level at the clear input
sets all four of the flip-flop outputs low after the next clock
pulse, regardless of the levels of the enable inputs. This
synchronous clear allows the count length to be modified
easily, as decoding the maximum count desired can be accomplished with one external NAND gate. The gate out-
put is connected to the clear input to synchronously clear
the counter to all low outputs. Low-to-high transitions at the
clear input of the 163A are also permissible, regardless of
the logic levels on the clock, enable, or load inputs.
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional
gating. Instrumental in accomplishing this function are two
count-enable inputs and a ripple carry output. Both countenable inputs (P and T) must be high to count, and input T is
fed forward to enable the ripple carry output. The ripple carry output thus enabled will produce a high-level output pulse
with a duration approximately equal to the high-level portion
of the QA output. This high-level overflow ripple carry pulse
can be used to enable successive cascaded stages. Highto-low-level transitions at the enable P or T inputs of the
161A through 163A may occur, regardless of the logic level
on the clock.
Features
II Synchronously programmable
•
•
•
•
•
..
Internal look-ahead for fast counting
Carry output for n-bit cascading
Synchronous counting
Load control line
Diode-clamped inputs
Alternate Military/Aerospace device (54161) is available. Contact a National Semiconductor Sales Office!
Distributor for specifications.
Connection Diagram
Dual·ln·Line Package
VIC
16
RIPPLE
CARRY
OUfUT
15
,
°A
114
OUTPUTS
08
113
Oc
112
.
OD
111
ENABLE
T
LOAD
9
110
I I I I I
I I I I I
1
2
CLEAR CLOCK
15
16
C
D
'~-------'/
DATA INPUTS
17
ENABLE
18
GND
P
TUF/6551-1
Order Number 54161DMQB, 54161FMQB, DM54161AJ, DM54161AW,
DM54163AJ, DM54163AW, DM74161AN or DM74163AN
See NS Package Number J16A, N 16E or W16A
4-159
~
CD
....
•
cc
....
CD
....
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guarant66d. The device should not be operated at these limits. The
perametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace 8peclfled devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
7V
Supply Voltage
Input Voltage
5.5V
Operating Free Air Temperature Range
DM54 and 54
-55·C to + 125"C
DM74
O"Cto +70"C
Storage Temperature Range
-65·Cto + 150"C
Recommended Operating Conditions
Symbol
DM54161Aand 163A
Parameter
DM74161Aand 163A
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
0.8
0.8
V
mA
Vcc
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
IOH
High Level Output Current
-0.8
-0.8
IOL
Low Level Output Current
16
16
mA
fCLK
Clock Frequency (Note 6)
0
25
MHz
tw
Pulse Width
(Note 6)
Clock
25
25
Clear
20
20
tsu
Setup Time
(Note 6)
2
2
0
25
Data
20
20
EnableP
34
34
Load
25
25
Clear (Note 5)
20
20
tH
Hold Time (Note 6)
TA
Free Air Operating Temperature
V
ns
ns
0
0
-55
125
ns
0
70
·c
Max
Units
-1.5
V
Electrical Characteristics
Over recommended operating free air temperature range (unless otherwise noted)
Symbol
Conditions
Parameter
Input Clamp Voltage
Vcc
VOH
High Level Output
Voltage
Vee = Min.loH = Max
VIL = Max. VIH = Min
VOL
Low Level Output
Voltage
Vee = Min. IOL = Max
VIH = Min. VIL = Max
II
Input Current @ Max
Input Voltage
Vcc
IIH
High Level Input
Current
Vee = Max
IlL
Low Level Input
Current
2.4
= 2.4V
= 0.4V
4-160
3.4
0.2
= Max. VI = 5.5V
Vee = Max
VI
Typ
(Note 1)
= Min. II = -12mA
VI
VI
Min
V
0.4
V
1
rnA
EnableT
80
Clock
80
Others
40
EnableT
-3.2
Clock
-3.2
Others
-1.6
p.A
mA
Electrical Characteristics
•
Over recommended operating free air temperature range (unless otherwise noted) (Continued)
Symbol
los
ICCH
ICCl
Parameter
Conditions
Typ
(Note 1)
Min
Max
Short Circuit
Output Current
Vcc = Max
(Note 2)
DM54
-20
-57
DM74
-20
-57
Supply Current
with Outputs High
Vcc = Max
(Note 3)
DM54
59
85
DM74
59
94
Supply Current
with Outputs Low
Vcc = Max
(Note 4)
DM54
63
91
DM74
63
101
Units
rnA
rnA
rnA
Note 1: All typicals are at Vee ~ sv, TA ~ 2S·C.
Note 2: Not more than one output should be shorted at a time.
Note 3: ICCH is measured with the lOAD high, then again with the lOAD low, with all inputs high and all outputs open.
Note 4: ICCl is measured with the CLOCK high, then again with the CLOCK input low, with all inputs low and all outputs open.
Note 5: Applies to '163A which has synchronous clear inputs.
Note 6: TA ~ 2S·C and Vee ~ SV.
Switching Characteristics at Vcc = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
From (Input)
To (Output)
RL
= 4000, CL = 15 pF
Min
Units
Max
fMAX
Maximum Clock
Frequency
tplH
Propagation Delay Time
Low to High Level Output
Clock to
Ripple Carry
27
ns
tpHl
Propagation Delay Time
High to Low Level Output
Clock to
Ripple Carry
24
ns
tplH
Propagation Delay Time
Low to High Level Output
Clock
(Load High) to a
20
ns
tpHl
Propagation Delay Time
High to Low Level Output
Clock
(Load High) to a
32
ns
tplH
Propagation Delay Time
Low to High Level Output
Clock
(Load Low) to a
21
ns
tpHl
Propagation Delay Time
High to Low Level Output
Clock
(Load Low) to a
32
ns
tplH
Propagation Delay Time
Low to High Level Output
EnableTto
Ripple Carry
16
ns
tpHL
Propagation Delay Time
High to Low Level Output
EnableTto
Ripple Carry
16
ns
25
MHz
Clear (Note 7)
Propagation Delay Time
36
toa
High to Low Level Output
Note 7: Propagation delay for clearing is measured from the clear input for the 161 A or from the clock input transition for the 163A.
tpHl
4-161
ns
a•
,..
Logic Diagrams
161A
,..
CD
,..
0(
)O----IK
>c)---------i~ti========._11r CLOCK
Q
>O.....--+--t JCLEAR
>O--t-t K
Q
(4)
DATAS
~I-------i::l===+~+==r:
}O--+--t-t J CLEAR
>O---+--t K
CLOCK
(5)
DATAC
::::...-------t;~=I=+l~t±=:I
Q
}CH-i--I J CLEAR
"lQ.---+---1 K
Q
CLOCK
(6)
DATAD
:::..--------t~~*=I=I=F*+=::::t
Q
)0......- - 1 J CLEAR
lJ~~~~~~~~~~~~~~~~~
Xl---CARRY
(15) OUTPUT
RIPPLE
TL/F/6551-3
4-162
~--------------------------------------------~~
01
Logic Diagrams (Continued)
~
):.
•
163A
x::1----iK
a
~O----------~rt_r--------_1~~CLOCK
Q
XlH-+--I J CLEAR
Xl_-+--IK
CLOCK
(4)
DATAB
.;,.-T-------+:t===1=t+:t=~ll
Q
')C~-.f--I J CLEAR
Xl_-i--IK
CLOCK
(5)
DATAC
---------"H+1=+I=I=::t:1~=r~
Q
X)-4~+--I J CLEAR
(11)
Xll---t--i K
a
aD
CLOCK
(6)
DATA 0
~-------tt=l=I=l:::t:l~:t=IF=I
Q
}O.....---fJ CLEAR
lJW~~~~~~~~~~g~~~~~:
Xl_--CARRY
(15) RIPPLE
OUTPUT
TLlF/6551-8
4-163
~
~
•
"f1ops Is
not affected.
2
N
Clock
G1
tf
~
.
3
01
4
02
-A
......
(0)
5
03
6
04
7
Ie
H
~
high level (steady state)
L
~
low level (steady state)
t
X
CLOCK GND
~ low-to· high level transition
~
don't care (any input including transitions)
00 = the level of 0 before the indicated steady state input conditions were
established
OUTPUTS
TL/F/6556-1
Order Number 54173DMQB, 54173FMQB,
DM54173J, DM54173Wor DM74173N
See NS Package Number J16A, N16E or W16A
4-181
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
DM54 and 54
- 55'C to + 125'C
DM74
O'Cto +70'C
Storage Temperature Range
-65'Cto +150'C
Recommended Operating Conditions
Symbol
DM54173
Parameter
DM74173
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
Vee
Supply Voltage
VIH
High Level Input Voltage
Vil
Low Level Input Voltage
0.8
0.8
V
mA
2
2
V
10H
High Level Output Current
-2
-5.2
10l
Low Level Output Current
16
16
mA
fClK
Clock Frequency (Note 4)
25
MHz
tw
Pulse Width
(Note 4)
tsu
tH
0
25
0
Clock
20
20
Clear
20
20
Setup Time
(Note 4)
Enable
17
17
Data
10
10
Hold Time
(Note 4)
Enable
2
2
Data
10
10
tREL
Clear Release Time (Note 4)
TA
Free Air Operating Temperature
10
ns
ns
ns
10
-55
125
ns
0
·C
70
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
=
=
VI
Input Clamp Voltage
Vcc
VOH
High Level Output
Voltage
Vcc = Min, 10H = Max
Vil = Max, VIH = Min
VOL
Low Level Output
Voltage
Vcc = Min, 10L = Max
VIH = Min, VIL = Max
II
Input Current @ Max
Input Voltage
Vcc
=
Min, II
Max, VI
Min
-12 mA
=
Typ
(Note 1)
Max
Units
-1.5
V
2.4
5.5V
= Max, VI = 2.4V
= Max, VI = 0.4V
Vcc = Max, Vo = 2.4V
VIH = Min, Vil = Max
Vcc = Max, Vo = O.4V
VIH = Min, Vil = Max
Vee = Max
I
V
0.4
V
1
mA
IIH
High Level Input Current
Vcc
40
p.A
III
Low Level Input Current
Vcc
-1.6
mA
IOZH
Off-State Output Current with High
Level Output Voltage Applied
40
p.A
10ZL
Off-State Output Current with Low
Level Output Voltage Applied
-40
p.A
los
Short Circuit
Output Current
I
(Note 2)
DM54
-30
-70
DM74
-30
-70
mA
50
72
mA
Vcc = Max (Note 3)
sv, TA ~ 2S'C.
Note 2: Not more than one output should be shorted at a time.
Note 3: lee is measured with all outputs open, CLEAR grounded after a momentary connection to 4.SV: N, G1, G2 and all DATA Inputs grounded: and the CLOCK
input and M Input at 4.SV.
Note 4: TA = 2S'C and Vee ~ SV.
Icc
Supply Current
Note 1: All typicals are at Vee
~
4-182
Switching Characteristics
Symbo,l
Parameter
........
at Vee = 5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
Co)
RL = 400n
From (Input)
To (Output)
CL=5pF
Min
Max
CL = 50pF
Min
Units
Max
MHz
fMAX
Maximum Clock Frequency
tpLH
Propagation Delay Time
Low to High Level Output
Clock to
Output
25
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clock to
Output
28
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clear to
Output
27
ns
tPZH
Output Enable Time
to High Level Output
Output Control
toO
7
30
ns
tPZL
Output Enable Time
to Low Level Output
Output Control
toO
7
30
ns
tpHZ
Output Disable Time
from High Level Output
Output Control
toO
3
14
ns
tpLZ
Output Disable Time
from Low Level Output
Output Control
toO
3
20
ns
25
•
4-183
~ r---------------------------------------------------------------~
.........
Logic Diagram
OUTPUT
CONTROL
{uNJ(~2t)~==:)------------------.,
(1)
DATA .:(..:,14;;:)_ _ _ _ _ _i-_r""'l
01
r---I O
Q
CLOCK
DATA {G1 (9)
ENABLE G2,_(_10_)" ' - _
CLEAR
DATA~(..:.13~)_ _~~_ _+-~r_~
02
>-+-+-to
Q
Q
CLOCK
Q
CLEAR
-;r-__-;r--r~
DATA..;(..:.12~)____
03 -
-t________-;""-'\
DATA ..:(..:,11,;:,)____
D4
TLlF/6556-2
4-184
r------------------------------------------------------------------------------------,
•
-4
~
5417 4/DM5417 4/DM7 417 4, 54175/DM54175/DM74175
Hex/Quad D Flip-Flops with Clear
General Description
Features
These positive-edge triggered flip-flops utilize TTL circuitry
to implement D-type flip-flop logic. All have a direct clear
input, and the quad (175) version features complementary
outputs from each flip-flop.
•
•
•
•
•
Information at the 0 inputs meeting the setup and hold time
requirements is transferred to the 0 outputs on the positivegoing edge of the clock pulse. Clock triggering occurs at a
particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input
is at either the high or low level, the 0 input signal has no
effect at the output.
174 contains six flip-flops with single-rail outputs
175 contains four flip-flops with double-rail outputs
Buffered clock and direct clear inputs
Individual data input to each flip-flop
Applications include:
Buffer/storage registers
Shift registers
Pattern generators
• Typical clock frequency 40 MHz
• Typical power dissipation per flip-flop 38 mW
• Alternate Military/Aerospace device (54174, 54175) is
available. Contact a National Semiconductor Sales Office/ Distributor for specifications.
Connection Diagrams
Dual·ln·Llne Package
06
D6
D5
05
04
Dual·ln·Line Package
04
VCC
CLOCK
Q4
D4
D3
03
D2
02
CLOCK
13
4
CLEAR
01
01
02
02
03
03
CLEAR
GND
Dl
01
Order Number 54175DMQB, 54175FMQB, DM54175J,
DM54175W or DM74175N
See NS Package Number J16A, N16E or W16A
Order Number 54174DMQB, 54174FMQB, DM54174J,
DM54174Wor DM74174N
See NS Package Number J16A, N16E or W16A
Function Table (Each Flip-Flop)
Inputs
Outputs
Clear
Clock
D
Q
Qt
L
X
X
L
H
H
H
H
t
t
H
H
L
L
X
L
H
00
00
L
L
= High Level (steady state)
= Low Level (steady state)
X
= Don't Care
t = Transition from low to high level
00
t
=
GND
TL/F/6557-2
TLlF/6557-1
H
......
0l:Io
'?'A National
~ Semiconductor
VCC
-4
= The level of Q before the indicated steady·state input condilions were established.
175 only
4-185
~
....
•
....
~
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Operating Free Air Temperature Range
DM54 and 54
- 55·C to + 125·C
O·Cto +70·C
DM74
Storage Temperature Range
- 65·C to + 150·C
Recommended Operating Conditions
Symbol
DM54174
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
Vil
Low Level Input Voltage
DM74174
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
0.8
0.8
V
2
2
V
10H
High Level Output Current
-0.8
-0.8
mA
10l
Low Level Output Current
16
16
mA
fClK
Clock Frequency (Note 4)
0
30
MHz
tw
Pulse Width
(Note 4)
25
25
Clock High
10
10
20
Clock Low
30
0
ns
Clear
20
tsu
Data Setup Time (Note 4)
20
20
ns
tH
Data Hold Time (Note 4)
0
0
ns
tREl
Clear Release Time (Note 4)
30
30
TA
Free Air Operating Temperature
-55
125
ns
0
70
·C
'174 Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
VI
Input Clamp Voltage
Vee = Min, 11= -12 mA
VOH
High Level Output
Voltage
VCC = Min, 10H = Max
VIL = Max, VIH = Min
VOL
Low Level Output
Voltage
Vce = Min, 10l = Max
VIH = Min, Vil = Max
II
Input Current @ Max
Input Voltage
Vee = Max, VI
Typ
(Note 1)
Units
-1.5
V
V
2.4
= 5.5V
= Max, VI = 2.4V
= Max, VI = 0.4V
Vee = Max
Max
0.4
V
1
mA
IIH
High Level Input Current
Vee
40
/LA
III
Low Level Input Current
Vee
-1.6
mA
los
Short Circuit
Output Current
(Note 2)
lee
Supply Current
Vee = Max (Note 3)
I
I
DM54
-20
-57
DM74
-18
-57
45
65
Note 1: All typicals are at Vee = SV, TA = 2S'C.
Note 2: Not mora than one output should be shorted at a time.
Note 3: With all outputs open and all DATA and CLEAR Inputs at 4.SV, lee is measured after a momentary ground, then 4.SV applied to the CLOCK input
Note 4: TA
= 2S'C and Vee = SV.
4-186
rnA
mA
....
~
.........•
'174 Switching Characteristics
at Vcc = 5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
RL
From (Input)
To (Output)
en
= 400n, CL = 15 pF
Min
Units
Max
fMAX
Maximum Clock
Frequency
tplH
Propagation Delay Time
Low to High Level Output
Clock to
AnyQ
25
ns
tpHl
Propagation Delay Time
High to Low Level Output
Clock to
AnyQ
25
ns
tpHl
Propagation Delay Time
High to Low Level Output
Clear to
AnyQ
40
ns
MHz
30
Recommended Operating Conditions
Symbol
Vcc
Supply Voltage
VIH
High Level Input Voltage
Vil
Low Level Input Voltage
IOH
DM74175
DM54175
Parameter
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
2
V
V
0.8
0.8
V
High Level Output Current
-0.8
-0.8
mA
IOl
Low Level Output Current
16
16
mA
fClK
Clock Frequency (Note 1)
0
30
MHz
tw
Pulse Width
(Note 1)
25
tsu
Clock Low
30
0
25
Clock High
10
10
Clear
20
20
Data Setup Time (Note 1)
20
20
ns
ns
tH
Data Hold Time (Note 1)
0
0
tREl
Clear Release Time (Note 1)
30
30
TA
Free Air Operating Temperature
Nate 1: TA =
25'C and Vce
=
-55
t25
0
ns
ns
70
'C
5V.
•
4-187
...•
...~
~
'175 Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
= Min, II = -12 mA
Vee = Min, IOH = Max
VI
Input Clamp Voltage
Vee
VOH
High Level Output
Voltage
VIL = Max, VIH = Min
Typ
(Note 1)
Max
Units
-1.5
V
2.4
V
VOL
Low Level Output
Voltage
Vee = Min, IOL = Max
VIH = Min, VIL = Max
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 5.5V
IIH
High Level Input Current
Vee = Max, VI = 2.4V
40
p.A
IlL
Low Level Input Current
Vee = Max, VI = 0.4V
-1.6
mA
los
Short Circuit
Output Current
Vee = Max
(Note 2)
Supply Current
Vee = Max (Note 3)
lee
I
I
0.4
V
1
mA
DM54
-20
-57
DM74
-18
-57
30
45
mA
mA
'175 Switching Characteristics
at Vee = 5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
From (Input)
To (Output)
RL = 4000, CL = 15 pF
Min
Units
Max
fMAX
Maximum Clock
Frequency
tpLH
Propagation Delay Time
Low to High Level Output
Clock to
AnyQorO
25
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clock to
AnyQorO
25
ns
tpLH
Propagation Delay Time
Low to High Level Output
Clear to
Any 0
25
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clear to
AnyQ
40
ns
30
MHz
Note 1: All typicals are at Vcc = SV, TA = 25'C.
Note 2: Not more than one output should be shorted at a time.
Note 3: With all outputs open and 4.SV applied to all DATA and CLEAR inputs, ICC is measured ailer a momentary ground then 4.5V applied to the CLOCK.
4-188
..........
..........•
Logic Diagrams
",.
174
175
(3)
Dl
(2)
D
0
en
(4)
Dl
01
(2)
D
01
0
CLOCK
(3)
0
01
CLEAR
(4)
(5)
D2
02
D2
(7)
D
0
02
CLOCK
(6)
0
CLEAR
(6)
D3
(7)
D
02
CLEAR
0
(12)
03
D3
(10)
D
03
0
CLOCK
CLOCK
CLEAR
CLEAR
(11)
(11)
D4
0
(10)
D
0
(13)
D4
04
CLOCK
CLEAR
(13)
(14)
00 ~~------~~~
CLOCK
05
0
o
04
0
(14)
0
CLEAR
04
CLEAR
(12)
D
(15)
D
CLOCK
CLOCK
D5
03
TL/F/6557-4
(15)
06
CLEAR
CLEAR
TLlF/6557-3
4·189
...
i
~National
~ Semiconductor
DM54180/DM74180 9-Bit Parity Generators/Checkers
General Description
These universal 9·blt (8 data bits plus 1 parity bit) parity
generators/checkers feature odd/even outputs and control
inputs to facilitate operation in either odd or even parity ap·
plications. Depending on whether even or odd parity is be·
ing generated or checked, the even or odd input can be
utilized as the parity or 9th·bit input. The word· length capa·
bility is easily expanded by cascading.
Input buffers are provided so that each data input repre·
sents only one normalized series 54174 load. A full fan·out
to 10 normalized series 54174 loads is available from each
of the outputs at a low logic level. A fan·out to 20 normal·
ized loads is provided at a high logic level to facilitate the
connection of unused inputs to used inputs.
Connection Diagram
Dual·ln·Llne Package
INPUTS
vee
T~4
E
F
D
12
13
A'
B
C
11
10
9
4
5
a
a
'2
G
H.
INPUTa
3
EVEN
INPUT
ODD l:-EVEN l:-ODO
INPUT OUTPUT OUTPUT
TL/F/6559-1
Order Number DM54180J, DM54180W or DM74180N
See NS Package Number J14A, N14A or W14B
Function Table
Inputa
l: of H'aat
l:
Even
Odd
H
L
Even
Odd
Even
H
L
Odd
H
L
L
H
Even
L
H
L
H
Odd
L
H
H
L
X
H
H
L
L
X
L
L
H
H
Athru H
H
outputs
l:
= High Level. L = Low Level, X = Don'\ Care
4·190
....
00
Q
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
DM54
-55'C to + 125'C
DM74
O'Cto +70'C
Storage Temperature Range
-65'Cto + 150'C
Recommended Operating Conditions
Symbol
DM54180
Parameter
DM74180
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
0.8
0.8
V
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
10H
High Level Output Current
-0.8
-0.8
mA
10L
Low Level Output Current
16
16
mA
TA
Free Air Operating Temperature
70
'C
2
2
-55
125
V
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
=
=
Min
Typ
(Note 1)
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vee
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
VIL = Max, VIH = Min
VOL
Low Level Output
Voltage
Vee = Min, 10L = Max
VIH = Min, VIL = Max
II
Input Current @ Max
Input Voltage
Vee
IIH
High Level Input
Current
Vee = Max
VI = 2.4V
Odd or Even
80
Data
40
Low Level Input
Current
Vee = Max
VI = O.4V
Odd or Even
-3.2
Data
-1.6
Short Circuit
Output Current
Vee = Max
{Note 2)
DM54
-20
-55
DM74
-18
-55
Supply Current
Vee = Max
(Note 3)
DM54
34
49
DM74
34
56
IlL
los
ICC
Nole 1: All typlcals are at Vee
=
Min, II
Max, VI
-12 mA
=
V
2.4
5.5V
= SV, TA = 2S'C.
Nole 2: Not more than one output should be shorted at a time.
Nole 3: Icc Is measured with EVEN and ODD inputs at 4.SV, all other inputs and outputs open.
4-191
0.4
V
1
mA
p.A
mA
mA
mA
Switching Characteristics at Vee = SV and TA = 2SoC (See Section 1 for Test Waveforms and Output Load)
Parameter
From (Input)
To (Output)
tpLH
Propagation Delay Time
Low to High Level Output
Data to
l: Even
tpHL
Propagation Delay Time
High to Low Level Output
Data to
l: Even
tpLH
Propagation Delay Time
Low to High Level Output
tpHL
Symbol
Conditions
Min
Max
Units
60
ns
68
ns
Data to
l: Odd
48
ns
Propagation Delay Time
High to Low Level Output
Data to
l: Odd
38
ns
tpLH
Propagation Delay Time
Low to High Level Output
Data to
l: Even
48
ns
tpHL
Propagation Delay Time
High to Low Level Output
Data to
l: Even
38
ns
tpLH
Propagation Delay Time
Low to High Level Output
Data to
l: Odd
60
ns
tpHL
Propagation Delay Time
High to Low Level Output
Data to
l:Odd
68
ns
tpLH
Propagation Delay Time
Low to High Level Output
Even or Odd to
l: Even or l: Odd
20
ns
tpHL
Propagation Delay Time
High to Low Level Output
l: Even or l: Odd
10
ns
CL = 1SpF
RL = 4000
Odd Input Low
CL = 1SpF
RL = 4000
Odd Input High
CL
RL
=
=
1SpF
4000
Even or Odd to
Logic Diagram
'b~
~!N:)
---l
B (9)
(10)
DATA
INPUTS
(12)
:ll!t)~
~[> H><>-
(1)
>'~
..... 0
:!C)
(5) :!: EVEN
OUTPUT
OUTPUT
ODD (4)
INPUT
EVEN (3)
INPUT
TLlF/6559-2
4-192
....
....CD
~NatiOnal
Semiconductor
DM54181
Arithmetic Logic Unit/Function Generators
General Description
Features
These arithmetic logic units (ALU)/function generators perform 16 binary arithmetic operations on two 4-bit words, as
shown in Tables I and II. These operations are selected by
the four function-select lines (SO, S1, S2, S3) and include
addition, subtraction, decrement, and straight transfer.
When performing arithmetic manipulations, the internal carries must be enabled by applying a low-level voltage to the
mode control input (M). A full carry look-ahead scheme is
available in these devices for fast, simultaneous carry generation by means of two cascade-outputs (P and G) for the
four bits in the package. When used in conjunction with the
DM54S182 full carry look-ahead circuits, high-speed arithmetic operations can be performed. The typical addition
times shown below illustrate how little time is required for
addition of longer words, when full carry look-ahead is employed. The method of cascading 182 circuits with these
ALU's to provide multi-level full carry look-ahead is illustrated under typical applications data for the DM54S182.
(Continued)
a Arithmetic operating modes:
Addition
Subtraction
Shift operand A one position
Magnitude comparison
Plus twelve other arithmetic operations
a Logic function modes:
EXCLUSIVE-OR
Comparator
AND,NAND,OR,NOR
Plus ten other logic operations
a Full look-ahead for high-speed operations on long
words
Connection Diagram
Pin Designations
Dual-In-Line Package
vcc
.
,
A1
B1
B2
21
1242322
OUTPUTS
,
A2
Designation
.
INPUTS
I
A3 B3
20
19
18
17
15 14
16
,BO
2
AO
3
S3
4
S2
5
S1
6
SO
7
cn
8
M
9
, ,FO
INPUTS
10
F1
Function
A3, A2, A1, AO
19,21,23,2
Word A Inputs
83,82,81,80
18,20,22,1
Word 8 Inputs
S3, S2, S1 , SO
3,4,5,6
Function-Select
Inputs
Cn
7
Inv. Carry Input
M
8
Mode Control
Input
F3,F2,F1,FO
13,11,10,9
Function Outputs
A=8
14
Comparator Output
P
15
Carry Propagate
Output
Cn+4
16
Inv. Carry Output
G
17
Carry Generate
Output
Vee
24
Supply Voltage
GND
12
Ground
13
P-
-C
1
,
G Cn+4 P A=B F3
Pin Nos.
11 J12
,
F2 GND
OUTPUTS
TLiF /6560-1
Order Number DM54181J
See NS Package Number J24A
Number
of
Bits
Typical
Addition Times
1 t04
5t08
9to 16
17 to 64
20ns
30 ns
30 ns
50 ns
Package Count
Arithmeticl
Logie Units
Look Ahead
Carry Generators
Carry Method
Between
ALU's
1
2
30r4
5to 16
0
0
1
2to 5
None
Ripple
Full Look-Ahead
Full Look-Ahead
4-193
......co
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaran·
teed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
7V
Input Voltage
5.5V
Output Voltage (A = B Output)
5.5V
Operating Free Air Temperature Range
DM54
- 55·C to
-65·Cto
Storage Temperature Range
+ 125·C
+ 150·C
Recommended Operating Conditions
Symbol
DM54181
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
Units
Min
Nom
Max
4.5
5
5.5
V
2
V
Vil
Low Level Input Voltage
0.8
V
VOH
High Level Output
Voltage (A = B Output)
5.5
V
10H
High Level Output
Current (All Except A = B)
-800
/LA
10l
Low Level Output Current
16
mA
TA
Free Air Operating
Temperature
125
·C
-55
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 1)
Max
Units
VI
Input Clamp Voltage
Vee = Min, 11= -12 mA
-1.5
V
leEX
High Level Output
Current (A = B Output)
Vee = Min, Vo = 5.5V
Vil = Max, VIH = Min
250
/LA
VOH
High Level Output
Voltage (All Except A = B)
Vee = Min, 10H = Max
Vil = Max, VIH = Min
VOL
Low Level Output
Voltage
Vee = Min, IOl = Max
VIH = Min, Vil = Max
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 5.5V
IIH
High Level Input
Current
Vee = Max
VI = 2.4V
III
Low Level Input
Current
Vee = Max
VI = 0.4V
2.4
V
Short Circuit Output
Current (All Except A = B)
Vee = Max
VI = 2.4V
IceH
Supply Current with
Outputs High
Vee = Max
(Note 3)
mA
40
120
S
160
Carry
200
Mode
-1.6
AorB
-4.8
S
-6.4
/LA
mA
-8
Supply Current with
Vee = Max
Outputs Low
(Note 4)
Nole 1: All typicals are at Vcc = 5V, TA = 25·C.
Nole 2: Not more than one output should be shorted at a time.
Nole 3: lOCH is measured with SO through S3, M, and A inputs at 4.5V, all other inputs grounded and all outputs open.
Nole 4: ICCl is measured with SO through 53 and M Inputs at 4.5V, all other inputs grounded and all outputs open.
4-194
1
Mode
-20
Icel
V
AorB
Carry
los
0.4
-55
mA
88
127
mA
92
135
mA
Switching Characteristics Vee =
5V, TA = 25'C (See Section 1 for Test Waveforms and Output Load)
DM54181
Symbol
Parameter
From
(Input)
To
(Output)
Conditions
RL = 4000, CL = 15 pF
Min
tpLH
Propagation Delay Time,
Low-to-High Level Output
tpHL
Propagation Delay Time,
High-to-Low Level Output
tpLH
Propagation Delay Time,
Low-to-High Level Output
tpHL
Propagation Delay Time,
High-to-Low Level Output
tpLH
Propagation Delay Time,
Low-to-High Level Output
tpHL
Propagation Delay Time,
High-to-Low Level Output
tpLH
Propagation Delay Time,
Low-to-High Level Output
tpHL
Propagation Delay Time,
High-to-Low Level Output
tpLH
Propagation Delay Time,
Low-to-High Level Output
tpHL
Propagation Delay Time,
High-to-Low Level Output
tpLH
Propagation Delay Time,
Low-to-High Level Output
tpHL
Propagation Delay Time,
High-to-Low Level Output
tpLH
Propagation Delay Time,
Low-to-High Level Output
tpHL
Propagation Delay Time,
High-to-Low Level Output
tpLH
Propagation Delay Time,
Low-to-High Level Output
tpHL
Propagation Delay Time,
High-to-Low Level Output
tpLH
Propagation Delay Time,
Low-to-High Level Output
tpHL
Propagation Delay Time,
High-to-Low Level Output
tpLH
Propagation Delay Time,
Low-to-High Level Output
tpHL
Propagation Delay Time,
High-to-Low Level Output
tpLH
Propagation Delay Time,
Low-to-High Level Output
tpHL
Propagation Delay Time,
High-to-Low Level Output
tpLH
Propagation Delay Time,
Low-to-High Level Output
tpHL
Propagation Delay Time,
High-to-Low Level Output
Units
Max
18
Cn
Cn +4
ns
19
Any A
orB
Any A
orB
Cn
Any A
orB
Any A
orB
Any A
orB
Any A
orB
AjorBj
AjorBj
Aj or Bj
Cn +4
Cn +4
AnyF
M = OV,SO =
S3 = 4.5V
S1 = S2 = OV
(SUM mode)
M = OV,SO =
S3 = OV
S1 = S2 = 4.5V
(DIFFmode)
M = OV
(SUM or
DIFFmode)
M = OV,SO =
S3 = 4.5V
S1 = S2 = OV
(SUM mode)
G
M = OV,SO =
S3 = OV
S1 = S2 = 4.5V
(DIFFmode)
G
M = OV,SO =
S3 = 4.5V
S1 = S2 = OV
(SUM mode)
P
M = OV,SO =
S3 = OV
S1 = S2 = 4.5V
(DIFFmode)
P
M = OV,SO =
S3 = 4.5V
S1 = S2 = OV
(SUM mode)
Fj
M = OV,SO =
S3 = OV
S1 = S2 = 4.5V
(DIFFmode)
Fj
M = 4.5V
(logic mode)
Fj
30
ns
33
30
ns
33
19
ns
18
19
ns
19
20
ns
25
19
ns
25
25
ns
25
30
ns
30
24
ns
24
28
ns
30
Any A
orB
A=B
4-195
M = OV,SO =
S3 = OV
S1 = S2 = 4.5V
(DIFFmode)
40
ns
40
....
CD
....
General Description
(Continued)
If high speed is not important, a ripple-carry input (Cn> and a
ripple-carry output (C n + 4) are available. However, the ripple-carry delay has also been minimized so that arithmetic
manipulations for small word lengths can be performed
without external circuitry.
These circuits will accommodate active-high or active-low
data, if the pin designations are Interpreted as shown below.
Subtraction Is accomplished by 1's complement addition,
where the 1's complement of the subtrahend is generated
internally. The resultant output is A-B-1, which requires
an end-around or forced carry to provide A-B.
The 181 can also be utilized as a comparator. The A = B
output is internally decoded from the function outputs (FO,
F1, F2, FS) so that when two words of equal magnitude are
applied at the A and B inputs, it will assume a high level to
indicate equality (A = B). The ALU should be in the subtract
mode with Cn = H when performing this comparison. The A
= B output is open-collector so that it can be wire-AND
connected to give a comparison for more than four bits.
The carry output (Cn +4) can also be used to supply
relative magnitude information. Again, the ALU should be
placed in the subtract mode by placing the function select
inputs SS, 52, 51, SO at L, H, H, L, respectively.
These circuits have been designed to not only incorporate
all of the designer's requirements for arithmetic operations,
but also to provide 16 possible functions of two Boolean
variables without the use of external circuitry. These logic
functions are selected by use of the four function-select inputs (SO, 51, 52, 53) with the mode-control input (M) at a
high level to disable the internal carry. The 16 logic functions are detailed in Tables 1 and 2 and include exclusiveOR, NAND, AND, NOR, and OR functions.
ALU SIGNAL DESIGNATIONS
The DM54181 can be used with the signal designations of
either Figure 1 or Figure 2.
The logic functions and arithmetic operations obtained with
signal designations as in Figure 1 are given in Table I; those
obtained with the signal designations of Figure 2 are given
in Table II.
Pin Number
2
1
23
22
21
20
19
18
9
10
11
13
7
16
15
Active-High Data (Table I)
AO
BO
A1
B1
A2
B2
AS
BS
FO
F1
F2
FS
Cn
Cn +4
X
17
y
Active-Low Data (Table II)
AO
BO
A1
B1
A2
B2
AS
BS
FO
F1
F2
FS
Cn
Cn +4
P
G
Input
Cn
Output
Cn +4
Active-High Data
(Figure 1)
Active-Low Data
(Figure 2)
H
H
L
L
H
L
H
L
A:>:B
A>B
AB
A:;;:B
4-196
General Description
(2) (1)
(23) (22)
....00
....
(Continued)
(21) (20)
(2)
(19) (18)
81
(7)
(7)
Cn
(8)
M
A2
82
181
(14)
(8)
FO
F1
A3
83
A=8
(14)
F2
GO
(7)
(7)
(13)
S182
en
(13)
y
(12)
(11)
Cn
(10)
(10)
(12)
(9)
(11)
(9)
TL/F /6560-3
TL/F/6560-2
FIGURE 2
FIGURE 1
TABLE I
Active High Data
Selection
S3
S2
S1
SO
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
H
H
H
H
L
L
L
L
L
H
L
H
L
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
L
L
H
H
L
L
H
H
H
L
H
L
H
L
H
M=H
Logic
Functions
F=A
F=A+B
F =AB
F=O
F=AB
F=S
F=AEIlB
F=AS
F=A+B
F=AEIlB
F=B
F= AB
F=1
F=A+B
F=A+B
F= A
M = L; Arithmetic Operations
en
= H (no carry)
F=A
F=A+B
F=A+S
F = Minus 1 (2's Compl)
F = A Plus AS
F = (A + B) Plus AS
F = A Minus B Minus 1
F = AS Minus 1
F = A Plus AB
F = A Plus B
F = (A + B) PlusAB
F = AB Minus 1
F = A PlusA*
F = (A + B) Plus A
F = (A + B) Plus A
F = A Minus 1
en
= L (with carry)
F=APlus1
F = (A + B) Pius 1
F = (A + S) Plus 1
F = Zero
F = A Plus AS Plus 1
F = (A + B) Plus AS Plus 1
F = A Minus B
F= AS
F = A Plus AB Plus 1
F = A Plus B Plus 1
F = (A + B) Plus AB Plus 1
F = AB
F = A Plus A Plus 1
F = (A + B) Plus A Plus 1
F = (A + B) Plus A Plus 1
F=A
'Each bit Is shifted to the next more significant position.
•
4-197
,...
co
,...
General Description (Continued)
TABLE II
Active Low Data
Selection
S3
S2
S1
SO
M=H
Logic
Functions
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
F=A
F= AB
F=A+B
F=1
F=A+B
F=S
F=AEIlB
F=A+S
F=AB
F=AEIlB
F=B
F=A+B
F=O
F= AS
F = AB
F=A
M = L; Arithmetic Operations
Cn = L (no carry)
Cn = H (with carry)
F = A Minus 1
F = ABMinus 1
F = ABMinus 1
F = Minus 1 (2's Com pi)
F = A Plus (A + S)
F = AB Plus (A + B)
F = A Minus B Minus 1
F=A+S
F = A Plus (A + B)
F = A Plus B
F = AS Plus (A + B)
F=A+B
F = APlusA·
F = AB PlusA
F = ASPlusA
F=A
F=A
F = AB
F= AS
F = Zero
F = A Plus (A + S) Plus 1
F = AB Plus (A + S) Plus 1
F = A Minus B
F = (A + S) Plus 1
F=APlus(A+ B) Plus 1
F=APlusBPlus1
F = AS Plus (A + B) Plus 1
F = (A + B) Plus 1
F = A Plus A Plus 1
F = AB Plus A Plus 1
F =AS Plus A Plus 1
F = A Plus 1
tEach bit is shifted to the next more significant pOSition.
Parameter Measurement Information
Logic Mode Test Table
Function Inputs: S1 = S2 = M = 4.5V, SO = S3 = OV
Parameter
tpLH
Input
Under
Test
Other Input
Same Bit
Other Data Inputs
Output
Waveform
Apply
4.5V
Apply
GND
Apply
4.5V
Apply
GND
Aj
Bj
None
None
Remaining
AandB, Cn
Fj
Out·ol-Phase
Bj
AI
None
None
Remaining
A and B, Cn
F,
Out-ol-Phase
tpHL
tpLH
Output
Under
Test
tpHL
SUM Mode Test Table
Function Inputs: SO = S3 = 4.5V, S1 = S2 = M = OV
Parameter
tpLH
Input
Under
Test
Other Input
Same Bit
Apply
4.5V
Apply
GND
Aj
Bj
None
Remaining
AandB
Cn
Fj
In-Phase
Bj
Aj
None
Remaining
AandB
Cn
Fj
In-Phase
Aj
Bj
None
None
Remaining
Aand B,Cn
P
In-Phase
Bj
AI
None
None
Remaining
A and B,Cn
P
In-Phase
tpHL
tpLH
Output
Waveform
Apply
GND
tpHL
tpLH
Output
Under
Test
Apply
4.5V
tpHL
tpLH
Other Data Inputs
tpHL
4-198
.....
QC)
Parameter Measurement Information
.....
(Continued)
SUM Mode Test Table
Function Inputs: SO = S3 = 4.5V, S1 = S2 = M = OV (Continued)
Parameter
tpLH
Input
Under
Test
Other Input
Same Bit
Apply
4.5V
Apply
GND
Ai
None
Bi
Remaining
B
Remaining
A,Cn
G
In·Phase
Bi
None
AI
Remaining
B
Remaining
A,Cn
G
In·Phase
Cn
None
None
All
A
All
B
AnyF
orCn +4
In·Phase
Ai
None
Bi
Remaining
B
Remaining
A,Cn
Cn +4
Out·ol·Phase
Bi
None
Ai
Remaining
B
Remaining
A,Cn
Cn +4
Out·ol·Phase
Output
Under
Test
Output
Waveform
tpHL
tpLH
tpHL
tpLH
Output
Waveform
Apply
GND
tpHL
tpLH
Output
Under
Test
Apply
4.5V
tpHL
tpLH
Other Data Inputs
tpHL
DIFF Mode Test Table
Function Inputs: S1 = S2 = 4.5V, SO = S3 = M = OV
Parameter
tpLH
Input
Under
Test
Other Input
Same Bit
Apply
4.5V
Apply
GND
Apply
4.5V
Apply
GND
Ai
None
Bi
Remaining
A
Remaining
B,C n
FI
In· Phase
BI
AI
None
Remaining
A
Remaining
B,C n
Fi
Out·ol·Phase
Ai
None
Bi
None
Remaining
AandB, Cn
P
In·Phase
Bi
Ai
None
None
Remaining
AandB, Cn
P
Out·ol·Phase
AI
BI
None
None
Remaining
Aand B,Cn
G
In·Phase
Bi
None
Ai
None
Remaining
Aand B,Cn
G
Out·ol·Phase
Ai
None
BI
Remaining
A
Remaining
B,Cn
A=B
In·Phase
Bi
Ai
None
Remaining
A
Remaining
B,C n
A=B
Out·ol·Phase
Cn
None
None
All
AandB
None
Cn +4
or any F
In·Phase
Ai
Bi
None
None
Remaining
A,B,Cn
Cn +4
Out·ol·Phase
Bi
None
AI
None
Remaining
A,B,C n
Cn +4
In·Phase
tpHL
tpLH
tpHL
tpLH
Other Data Inputs
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
4·199
_ r---------------------------------------------------------------------______-,
co
Logic Diagram
13)
14)
53
52
15)
5' 16)
50
83 -~
( '8)
....
('9)
-'"
....
(20)
G or
~r
~
V
Y
('7)
,
~
'--
I:::r\.
~
('6) Cn
+4
p or X
('5)
JD
I
-
rJ·
F3
('3)
J
12')
,- r¢
(22)
~~
~
(11)
F2
A=B
('4:
,
hf)
123)
0_
(11
~
~
r51
F1
(10)
D
~'
AO
M
to
.rJ
(9)
FO
12)
18)
cn
TL/F/6560-4
= PIN24
GND = PIN 12
Vee
4-200
~National
•
.....
CD
~ Semiconductor
en
DM74184/DM74185A
BCD-to-Binary and Binary-to-BCD Converters
General Description
These monolithic converters are derived from the 256-bit
read only memories, DM5488, and DM7488. Emitter con·
nections are made to provide direct read·out of converted
codes at outputs V8 through Vl, as shown in the function
tables. These converters demonstrate the versatility of a
read only memory in that an unlimited number of reference
tables or conversion tables may be built into a system. Both
of these converters comprehend that the least significant
bits (LSB) of the binary and BCD codes are logically equal,
and In each case the LSB bypasses the converter as iIIus·
trated in the typical applications. This means that a 6-bit
converter is produced in each case. Both devices are cas·
cadable to N bits.
An overriding enable input is provided on each converter
which when taken high inhibits the function, causing all out·
puts to go high. For this reason, and to minimize power
consumption, unused outputs V7 and V8 of the 185A and all
"don't care" conditions of the 184 are programmed high.
The outputs are of the open·collector type.
b. Shift right, examine, and correct after each shift until the
least significant decade contains a number smaller than
eight and all other converted decades contain zeros.
In addition to BCD·to·binary conversion, the DM74184 is
programmed to generate BCD 9's complement or BCD 10's
complement. Again, in each case, one bit of the comple·
ment code is logically equal to one of the BCD bits; there·
fore, these complements can be produced on three lines.
As outputs V6, V7 and V8 are not required in the BCD·to·bi·
nary conversion, they are utilized to provide these comple·
ment codes as specified in the function table when the de·
vices are connected as shown.
DM74185A BINARY-TO-BCD CONVERTERS
The function performed by these 6-bit binary·to·BCD con·
verters is analogous to the algorithm:
a. Examine the three most significant bits. If the sum is
greater than four, add three and shift left one bit.
DM74184 BeD·TO-BINARY CONVERTERS
b. Examine each BCD decade. If the sum is greater than
four, add three and shift left one bit.
The 6-bit BCD·to·binary function of the DM74184 is analo·
gous to the algorithm:
c. Repeat step b until the least·significant binary bit is in the
least·significant BCD location.
a. Shift BCD number right one bit and examine each dec·
ade. Subtract three from each 4-bit decade containing a
binary value greater than seven.
(Continued)
Connection Diagram
r-----.. .------"
BINARY SELECT
vcc
116
ENABLE
G
15
2
,Y1
Y2
E
0
14
3
Y3
C
13
12
4
Y4
B
A
11
OUTPUT
YB
10
5
6
7
Y5
Y6
Y7
9
18
GND
OUTPUTS
TL/F/6561-1
Order Number DM74184N or DM74185AN
See NS Package Number N16E
4-201
•
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
7V
Supply Voltage
Input Voltage
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
5.5V
Output Voltage
7V
Operating Free Air Temperature
Range
O'Cto +70'C
Storage Temperature Range
-65'C to + 150'C
Recommended Operating Conditions
Symbol
Parameter
Min
Nom
Max
Units
4.75
5
5.25
V
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
0.8
V
VOH
High Level Output Voltage
5.5
V
12
rnA
70
'C
2
IOL
Low Level Output Current
TA
Free Air Operating Temperature
V
0
'184 and '185A Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 1)
Max
Units
VI
Input Clamp Voltage
Vee = Min, 11= -12 mA
-1.5
leEX
High Level Output
Current
Vee = Min, Vo = 5.5V
VIL = Max, VIH =. Min
100
p.A
VOL
Low Level Output
Voltage
Vee = Min, IOl = Max
VIH = Min, Vil = Max
0.4
V
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 5.5V
1
rnA
V
IIH
High Level Input Current
Vee = Max, VI = 2.4V
25
p.A
III
Low Level Input Current
Vee = Max, VI = 0.4V
-1
rnA
ICCH
Supply Current with
Outputs High
Vee = Max
65
95
rnA
leeL
Supply Current with
Outputs Low
Vee = Max
80
99
rnA
'184 and '185A Switching Characteristics
at Vee = 5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
RL 1 = 4000, RL2 = 6000
CL = 15 pF (See Test Circuit)
From (Input)
To (Output)
Min
Units
Max
tpLH
Propagation Delay Time
Low to High Level Output
EnableG
to Output
35
ns
tpHL
Propagation Delay Time
High to Low Level Output
EnableG
to Output
35
ns
tpLH
Propagation Delay Time
Low to High Level Output
Binary Select
to Output
35
ns
tpHl
Propagation Delay Time
High to Low Level Output
Binary Select
to Output
35
ns
Note 1: All typicals are at Vee = SV. TA = 2S'C.
4-202
r-------------------------------------------------------------------------------------, -"co
Ao
General Description (Continued)
•
DM74184 BCD-to-Blnary
TABLE I. Package Count and Delay Times
for BCD-to-Blnary Conversion
Input
(Decades)
Packages
Required
2
3
4
5
6
2
6
12
19
28
6-Blt Converter
,....-.........,.--""----,
BAD
,25
C
o
I
20
80
200
280
400
520
BCD's10's
Complement Converter
BCD
BCD
B
24 23 22 21
Max
56
140
196
280
364
BCD9's
Complement Converter
LSD
MSO
Total Delay Times (ns)
Typ
C
B
A
5V
0
C
B
A
,
6·BIT BINARY OUTPUT
TL/F/6561-2
NONC NB NA
BCD' 9'5
COMPLE~ENT
TO TC TB TA
,
\,
BCD 10'S COMPLEMENT
TLlF/6561-4
TL/F/6561-3
DM74185A Binary-to-BCD
TABLE II. Package Count and Delay Times
for Blnary-to-BCD Conversion
Input
(Bits)
Packages
Required
4t06
70r8
9
10
11
12
13
14
15
16
17
18
19
20
1
3
4
6
7
8
10
12
14
16
19
21
24
27
Total Delay Times (ns)
Typ
Max
6-Blt Converter
25
50
75
100
125
125
150
175
175
200
225
225
250
275
40
80
120
160
200
200
240
280
280
320
360
360
400
440
6·BIT BINARY INPUT
4-203
BAD
C B
I
A
To '. . --LS""'O-6-BIT BCD OUTPUT
TLlF/6581-5
•
:g
....
•
co
....
Function Tables
oo:r
Inputs
Binary
Words
Outputs
E
Binary Select
C
B
D
A
G
V8
V7
V6
V5
V4
V3
Y2
V1
0
2
4
6
1
3
5
7
l
l
l
l
l
l
l
l
l
l
l
l
l
l
H
H
l
H
l
H
l
l
l
l
H
H
H
H
H
H
H
H
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
H
H
l
H
l
H
8
10
12
14
9
11
13
15
l
l
l
l
l
l
l
l
H
H
H
H
l
l
H
H
l
H
l
H
l
l
l
l
H
H
H
H
H
H
H
H
l
l
l
l
l
l
l
l
l
H
H
H
H
l
l
l
l
l
l
H
l
l
H
l
16
18
20
22
17
19
21
23
l
l
l
l
H
H
H
H
l
l
l
l
l
l
H
H
l
H
l
H
l
l
l
l
H
H
H
H
H
H
H
H
l
l
l
l
l
l
H
H
H
H
l
l
l
H
l
l
H
l
l
l
H
l
l
H
24
26
28
30
25
27
29
31
l
l
l
l
H
H
H
H
H
H
H
H
l
l
H
H
L
H
l
H
l
l
l
l
H
H
H
H
H
H
H
H
l
l
l
l
H
H
H
H
l
l
l
H
l
l
H
l
H
H
l
l
l
H
l
l
32
34
36
38
33
35
37
39
H
H
H
H
l
l
l
l
l
l
l
l
l
l
H
H
l
H
l
H
l
l
l
l
H
H
H
H
H
H
H
H
l
l
l
l
H
H
H
H
H
H
H
H
l
l
l
H
l
H
H
l
H
l
H
l
40
42
44
46
41
43
45
47
H
H
H
H
l
l
l
l
H
H
H
H
l
l
H
H
l
H
l
H
l
l
l
l
H
H
H
H
H
H
H
H
H
H
H
H
l
l
l
l
l
l
l
l
l
l
l
l
l
l
H
H
l
H
l
H
48
50
52
54
49
51
53
55
H
H
H
H
H
H
H
H
l
l
l
l
l
l
H
H
l
H
l
H
l
l
l
l
H
H
H
H
H
H
H
H
H
H
H
H
l
l
l
l
l
H
H
H
H
l
l
l
l
l
l
H
l
l
H
l
56
58
60
62
57
59
61
63
H
H
H
H
H
H
H
H
H
H
H
H
l
l
H
H
l
H
l
H
l
l
l
l
H
H
H
H
H
H
H
H
H
H
H
H
l
l
H
H
H
H
l
l
l
H
l
H
l
l
L
L
H
l
l
H
X
X
X
X
X
H
H
H
H
H
H
H
H
H
All
Enable
4-204
,------------------------------------------------------------------------------------------, co
.,..
Function Tables (Continued)
~
•
BCD-to-Blnary Converter
Inputs
(See Note A)
BCD
Words
BCD 9's or BCD 10's Complement Converter
Outputs
(See Note B)
E D C BAG V5 V4 V3 V2 V1
o
1
2
3
4
6
5
7
6
9
10
12
14
16
18
11
17
19
20
21
22
23
13
15
24
25
26
28
27
29
30
31
32
33
34
36
38
35
37
39
Any
Et
o
LLLLLLL L L L L
LLLLHLLLLLH
LLLHLLLLLHL
LLLHHLLLLHH
LLHLLLLLHLL
1
2
3
4
LHLLLLLLHLH
LHLLHLLLHHL
LHLHLLLLHHH
LHLHHLLHLLL
LHHLLLLHLLH
HLLLLL
HLLLHL
HLLHLL
HLLHHL
HLHLLL
Inputs
(See Note C)
BCD
Word
5
6
7
8
9
V8
V7
V6
LLLLLH
LLLHLH
LLHLLL
LLHHLL
LHLLLL
L
L
H
H
H
H
L
H
L
H
L
LHLHLL
L
LHHLLL
L
LHHHLL
LHLLLLL
LHLLHLL
H
L
L
L
L
L
H
L
H
L
L
L
L
H
L
L
L
L
L
D
C
BAG
o
H
1
L
L
L
L
L
L
H
3
4
H
H
H
H
L
H
H
L
5
H
L
H
6
H
H
L
H
H
H
H
7
8
9
L
L
H
L
L
H
L
L
H
Any
L
L
L
L
L
H
H
H
H
H
L
L
H
H
H
H
L
L
L
H
L
H
H
H
L
HHLLLL L
HHLLHLH
HHLHLLH
HHLHHLH
HHHLLLH
H
L
L
L
H
L
L
L
H
L
L
H
H
L
H
L
L
L
H
XXXXXHH
H
H
H
2
Outputs
(See Note D)
L
L
L
L
L
H
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
H
H
H
L
H
H
L
L
L
L
L
L
H
H
H
L
H
L
H
L
L
L
L
L
L
L
L
H
H
L
x
x x x x
H
H
H
H
H
H
H = High Level, L = Low Level, X = Don't Care
Nole A: Input Conditions other than those shown produce highs at outputs Yl through Y5.
Nole B: Output Y6, Y7, and YB are not used for BCD·to-Binary conversion.
Nole C: Input conditions other than those shown produce highs at outputs Ye, Y7, and YS.
Nole D: Outputs Yl through Y5 are not used for BCD 9's or BCD 10's complement conversion.
tWhen these devices are used as complement converters, Input E Is used as a mode control. With this input low, the BCD 9's complement is generated; when it is
high, the BCD 10's complement Is generated.
Test Circuit
Typical Applications
BCD
Vee
MSD
LSD
,----j.--~\
~,--~.--~,
IIIII
I
E
DeB
A
I
V5 V4 V3 V2 VI
I
TLlF/6561-6
IE
I
I
DeB
A
CL Includes probe and jig capaCitance
IV5 V4 V3 V2 VI
~ ~ ~ ~ ~
OPEN B6 B5 B4 B3 B2 Bl BO
,
I
BINARV
TLlF/6561-7
FIGURE 1. BCD-to-Blnary Converter
for Two BCD Decades
MSD-Most significant decade
LSD-Least significant decade
Each rectangle represents a DM741S4
4-205
•
In
....co
•
co
....
Typical Applications (Continued)
'IS'
BCD
MSO
LSD
in
'05 C5 B5 AS 04 C4 B4 A4' '03 C3 B3 A3'
C2 B2 A2 '01 CI BI AI'
'00 CO
BO AO'
JIIII
r O C BAIl
Y5 Y4 Y3 Y2 Yl
E
0
I I
I
C
~I
B
I
OP~N
0
1 I I
~
I
C
~I
5 V4 V3 V2 VI
0
C
B
Atl
I
I I I
~I
I I
rOC B
V5 V4 V3 V2 VI
I I I
~I
C
II
I I I
~I
rOC B
V5 V4 V3 V2 VI
Jc
I
I
B
l
AJ
~I
I,E 0 C B
V5 V4 V3 V2 V,
I I
I
lEOCBAJ
BAIl
J
I I
I
Y5 Y4 Y3 Y2 VI
I
I I I
rOCB:1
V5 V4 V3 V2 VI
J _1 I
rOCBA~1
Y5 Y4 V3 Y2 VI
I
r O C BAIl
V5 V4 Y3 V2 VI
OPEN
C
V5 V4 V3 V2 VI
I
BAil
11 J
0
I I J
0
C
5 V4 V3 Y2 VI
rOC B
Y5 V4 V3 V2 VI
I
I I I
0
V5 V4 V3 Y2 YI
I
r O C B :1
V5 V4 V3 V2 VI
I,E
B AJ
Y5 V4 V3 Y2 VI
I
E
I,E 0 C B
Y5 V4 V3 V2 V,
J
I LI
~
roc
~I
IE
I,E 0 C BAIl
V5 Y4 Y3 V2 YI
J _1
I,E 0 C B
Y5 V4 V3 V2 VI
I
J
'"--'
IE
I
OJEN
IJ
j
0 C B A
1
V5 V4 Y3 V2 V,
I I
B
I
Y5 V4 V3 V2 VI
v,
E
B
I I I
I,E 0 C B A,I
V5 V4 Y3 Y2
n
C
Y5 Y4 Y3 V2 y:1
I
~E
0
I,E
Y5 Y4 Y3 Y2 Y'
I
I
lED
C
BAIl
Y5 Y4 Y3 V2 VI
I I
I
~I
IE 0 C B
Y5 V4 V3 Y2 YI
I
I
~I
0 C B
V5 V4 V3 Y2 V I
IE
I 11
~I
'*'
I
IE 0 C B
Y5 V4 Y3 V2 VI
I I I
r O C BAIl
V5 V4 V3 V2 VI
I I
++ +
~~19B18B17B16B15B14B13B12Bl1Bl0.. B9
B8
8786
6584
BINARV
FIGURE 2. BCD.to·Binary Converter for Six BCD Decades
MSD-Most significant decade
LSD-Least significant decade
Each rectangle represents a DM74184
4-206
8382 Bt
80
TLlF/6561-9
....
:
Typical Applications (Continued)
....CD•
"' .,,'" 1
BCD
MSD
BINARY
LSD
r-------,\ ,..,------...., ,..-----....,
CI\
~
,--J '"'_ _ _- . J
MSD
LSD
BCD
TL/F/8561-10
FIGURE 4. 6-Blt Blnary-to-BCD Converter
MSD-Most significant decade
LSD-Least slgnnicant decade
Nole A: Each rectangle represents a DM74185A.
Nole B: All unused E inpuls are grounded.
B9 BB B7 B6 B5 B4 B3 B2 Bl BO
OPEN' '. .-----B~I~N~A~R~Y~----oJ
TLlF/6561-6
FIGURE 3. BCD-to-Blnary Converter
for Three BCD Decades
MSD-Most slgnmcant decade
LSD-Least significant decade
Each rectangle represents a DM74184
BINARY
BINARY
B8 B7 B6 B5 B4 B3 B2 Bl BO
B7 B6 B5 B4 B3 B2 B1 BO
,"-_._oJ' ...
' _ _--',
MSD
BCD
.
1 0 . . \_ _ _- - ' ;
LSD
BCD
TLlF/6561-11
TL/F/6561-12
FIGURE 5. 8-Blt Blnary-to-BCD Converter
FIGURE 6. 9-Blt Blnary-to-BCD Converter
MSD-Most significant decade
LSD-Least significant decade
MSD-Mosl Significant decade
LSD-Least significant decade
Note A: Each rectangle represents a DM74185A.
Note B: All unused E inputs are grounded.
Nole A: Each rectangle represen1s a DM74185A.
Nole B: All unused E inputs are grounded.
4·207
•
...~
•...•
Typical Applications (Continued)
CD
BINARY
0'15814 B13B12B11B10B988 87 B6 85 B4 8382 8180'
IIII I
lEO
C
B
AI
1v6 Y5 '4 V3 Y2 Y1
I
I
E DeB AI
Y5 Y4 V3 Y2
lED
1~6
C
BAilE
V5 Y4 V3 ,2
IE
,tIlVS
0
C
0
Y11
C
B AW
AI
B
Y4 V3 Y2
v11
0
C
B AI
IV5 V4 V3 V2 Vl1\V5V4 V3 V2 VII
l
EO
C
B
AW
DeB AI\
DeB AI
V6Y5 Y4 V3 Y2 y,IlVS Y4 V3 V2 Y111V5 V4 V3 V2
IE DeB
Ane
0
C
B
AW
Y11
DeB
A
IV5 V4 V3 V2 vl11v5 V4 V3 V2 Vl1\V5 V4 V3 V2 VI
I
lED
C
B AW DeB AI\D
C
B AI
IV6 '5 Y4 V3 Y2 y,IIVS Y4 V3 Y2 Y111'4 V3 Y2 Y11
10
TL/F/6561-13
FIGURE 7. 12-Blt Blnary-to-BCD
Converter (See Note B)
C
B
AI
IV4 V3 V2 y,1
~ ~ ~ ~
MSD
LSD
BCD
TL/F/6561-14
FIGURE 8. 16-Blt Blnary-to-BCD Converter (See Note B)
MSD-Most signiflcant decade
LSD-Least slgnlflesnt deesde
Nole A: Each rectangle represents a DM74185A.
Nole S: All unused E Inputs are grounded.
4·208
r-------------------------------------------------------------------------------------, CD
-A
-A
~National
~ Semiconductor
54191/DM54191/DM74191 Synchronous Up/Down
4-Bit Binary Counter with Mode Control
General Description
This circuit is a synchronous, reversible, up/down counter.
The 191 is a 4-bit binary counter. Synchronous operation is
provided by having all flip-flops clocked simultaneously so
that the outputs change simultaneously when so instructed
by the steering logic. This mode of operation eliminates the
output counting spikes normally associated with asynchronous (ripple clock) counters.
The outputs of the four master-slave flip-flops are triggered
on a low-to-high level transition of the clock input, if the
enable input is low. A high at the enable input inhibits counting. Level changes at either the enable input or the down/
up input should be made only when the clock input is high.
The direction of the count is determined by the level of the
down/up input. When low, the counter counts up and when
high, it counts down.
This counter is fully programmable; that is, the outputs may
be preset to either level by placing a low on the load input
and entering the desired data at the data inputs. The output
will change independent of the level of the clock input. This
feature allows the counters to be used as modulo-N dividers
by simply modifying the count length with the preset inputs.
The clock, down/up, and load inputs are buffered to lower
the drive requirement; which significantly reduces the number of clock drivers, etc., required for long parallel words.
Two outputs have been made available to perform the cascading function: ripple clock and maximum/minimum count.
The latter output produces a high-level output pulse with a
duration approximately equal to one complete cycle of the
clock when the counter overflows or underflows. The ripple
clock output produces a low-level output pulse equal in
width to the low-level portion of the clock input when an
overflow or underflow condition exists. The counters can be
easily cascaded by feeding the ripple clock output to the
enable input of the succeeding counter if parallel clocking is
used, or to the clock input if parallel enabling is used. The
maximum/minimum count output can be used to accomplish look-ahead for high-speed operation.
Features
•
•
•
•
•
•
•
Single down/up count control line
Count enable control input
Ripple clock output for cascading
Asynchronously presettable with load control
Parallel outputs
Cascadable for n-bit applications
Alternate Military/Aerospace device (54191) is available. Contact a National Semiconductor Sales Office/
Distributor for specifications.
Connection Diagram
Dual·ln·Llne Package
INPUTS
OUTPUTS
INPUTS
DATA
RIPPLE MAXI
A
a.OCK CLOCK MIN
15
2
DATA
~
INPUT
OB
14
3
QA
12
4
5
ENABLE DOWN I
.G
OUTPUTS
13
LOAD
11
6
Qc
DATA
DATA
C
D
10
9
7 JB
OD
GND
UP,
INPUTS
OUTPUTS
Order Number 54191DMQB, 54191FMQB,
DM54191J, DM54191W or DM74191N
See NS Package Number J16A, N 16E or W16A
4-209
TL/F/6562-1
......
G)
Absolute Maximum Ratings
(Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table ara not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
DM54 and 54
-55·Cto +125·C
O·Cto +70·C
DM74
Storage Temperature Range
R~commended
-65·C to + 150·C
Operating Conditions
Symbol
DM54191
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
DM74191
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
2
V
V
Vil
Low Level Input Voltage
0.8
0.8
V
10H
. High Level Output Current
-0.8
-0.8
mA
10l
Low Level Output Current
felK
Clock Frequency (Note 4)
tw
Pulse Width
(Note 4)
16
0
I
I
20
0
Clock
25
25
Load
35
35
16
mA
20
MHz
ns
tsu
Data Setup Time (Note 4)
28
28
ns
tH
Hold Time (Note 4)
0
0
ns
tREl
Load Release Time (Note 4)
30
30
ns
TA
Free Air Operating Temperature
Electrical Characteristics
Symbol
-55
Conditions
VI
Input Clamp Voltage
Vee = Min, 11= -12mA
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
Vil = Max, VIH = Min
VOL
Low Level Output
Voltage
Vee = Min, 10l = Max
VIH = Min, Vil = Max
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 5.5V
IIH
High Level Input
Current
Vee = Max
VI = 2.4V
Low Level Input
Current
Vee = Max
VI = 0.4V
Short Circuit
Output Current
Vee = Max
(Note 2)
Supply Current
Vee = Max
(Note 3)
los
lee
0
70
·c
over recommended operating free air temperature range (unless otherwise noted)
Parameter
III
125
Min
2.4
Typ
(Note 1)
Max
Units
-1.5
V
3.4
0.2
V
0.4
V
1
mA
Enable
120
Others
40
Enable
-4.8
Others
-1.6
DM54
-20
-65
DM74
-18
-65
DM54
65
99
DM74
65
105
typlcals are at Vee = 5V, TA = 25'C.
one output should be shorted at a time.
Note 3: lee Is measured with all inputs grounded and all outputs open.
Note 4: TA = 25'C and Vee = 5V.
Note 1: All
Note 2: Not more than
4-210
/LA
mA
mA
mA
Switching Characteristics
Symbol
......
CD
at Vee
Parameter
=
5V and TA
=
From (Input)
To (Output)
25'C (See Section 1 for Test Waveforms and Output Load)
RL
Min
=
4000, CL
=
15 pF
Units
Max
fMAX
Maximum Clock Frequency
tpLH
Propagation Delay Time
Low to High Level Output
Load to
AnyQ
33
ns
tpHL
Propagation Delay Time
High to Low Level Output
Load to
AnyQ
70
ns
tPLH
Propagation Delay Time
Low to High Level Output
Data to
AnyQ
22
ns
tpHL
Propagation Delay Time
High to Low Level Output
Data to
AnyQ
70
ns
tpLH
Propagation Delay Time
Low to High Level Output
Clock to
Ripple Carry
20
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clock to
Ripple Carry
24
ns
tpLH
Propagation Delay Time
Low to High Level Output
Clock to
AnyQ
24
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clock to
AnyQ
36
ns
tpLH
Propagation Delay Time
Low to High Level Output
Clock to
MaxIMin
42
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clock to
MaxIMin
52
ns
tpLH
Propagation Delay Time
Low to High Level Output
DownlUpto
Ripple Carry
45
ns
tpHL
Propagation Delay Time
High to Low Level Output
Down/Upto
Ripple Carry
45
ns
tpLH
Propagation Delay Time
Low to High Level Output
Down/Upto
MaxIMin
33
ns
tpHL
Propagation Delay Time
High to Low Level Output
Down/Upto
MaxIMin
33
ns
tpLH
Propagation Delay Time
Low to High Level Output
EnableGto
Ripple Carry
24
ns
tpHL
Propagation Delay Time
High to Low Level Output
EnableG to
Ripple Carry
24
ns
20
4-211
MHz
,..
~ Logic Diagram
191 Binary Counter
CLOCK (
DOWN I
UP
14)
(5)
I
r
DATA (15)
INPUT A
(4)
ENABLEG
~
~RIPPLE
....--18
J
CLOCK
(12) MAXI MIN
OUTPUT
::r
J Y
~
DATA (1)
INPUT B
PRfsET
OA
J
~
L--
J
I--
KCL.1ROA
./
r
J
L
-J
I--<
~
PRESET ~O
OB
UTPUTOB
CLOCK
f-- KCLEAROBr
~
:J
J y
~
i::I
n
DATA (9)
INPUTD
OUTP
b
~
DATA (10)
INPUT C
---1~
CLOCK
rL
-J
PRESET ~~,
Oc
OUTPUTOC
I--< CLOCK
f--
KCL~fOC~
-
J .?
t!}
(11)
LOAD
lH' ...l",I-<.!!!
L-c
L'C~".'J
:J
~
TL/F/6562-2
4-212
OUTPUTOD
CLOCK
Pin (16)
Vee. Pin (8)
~
GND
r-------------------------------------------------------------------------------~
Timing Diagrams
191 Decade Counter
Typical Load, Count, and Inhibit Sequences
LOAD
DATA
INPUTS
I:
:
CLOCK
DOWN/UP
ENABLE
_-;H
OA--
OB--.
QC :
:r-I -++---.
QD -~!
- -I--U-----~----t_--~~----~...-----~
MAX/MIN
--I
:RIPPLE CLOCK:
:i-I -+i----.
-~
r-----t----+-+---..
113 14 15 0
1 2
2
2 1
0
15 14 13
!J.I--COUNT UP
INHIBIT I I--COUNT DOWN--I
LOAD
I
4·213
TL/F/6562-3
...
...
CD
~
G)
..-
r----------------------------------------------------------------------------,
~National
~ Semiconductor
DM54193 Synchronous Up/Down
4-Bit Binary Counter with Dual Clock
General Description
This circuit is a synchronous up/down 4-bit binary counter.
Synchronous operation is provided by having all flip-flops
clocked simultaneously, so that the outputs change together when so instructed by the steering logic. This mode of
operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters.
The outputs of the four master-slave flip-flops are triggered
by a low-to-high level transition of either count (clock) input.
The direction of counting is determined by which count input
is pulsed, while the other count input is held high.
This counter was deSigned to be cascaded without the need
for external circuitry. Both borrow and carry outputs are
available to cascade both the up and down counting functions. The borrow output produces a pulse equal in width to
the count down input when the counter underflows. Similarly, the carry output produces a pulse equal in width to the
count up input when an overflow condition exists. The counter can then be easily cascaded by feeding the borrow and
carry outputs to the count down and count up inputs respectively of the succeeding counter.
This counter is fully programmable; that is, each output may
be preset to either level by entering the desired data at the
inputs while the load input is low. The output will change
independently of the count pulses. This feature allows the
counter to be used as modulo-N divider by Simply modifying
the count length with the preset inputs.
•
•
•
•
Features
Fully independent clear input
Synchronous operation
Cascading circuitry provided internally
Individual preset each flip-flop
A clear input has been provided which, when taken to a high
level, forces all outputs to the low level; independent of the
count and load inputs. The clear, count, and load inputs are
buffered to lower the drive requirements of clock drivers,
etc., required for long words.
Connection Diagram
Dual-In-Llne Package
INPUTS
,......--....,
OUTPUTS
,......-.....,
Vee
[ 16
.
INPUTS
,
DATA
CLEAR BORROW CARRY LOAD
A
115
114
113
112
111
DATA
D
9
DATA
C
[ 10
I I ! ! ! I
-
I-
I I
1
DATA B
INPUT
12
13
Qa
QA
'--'"
OUTPUTS
I I
4
5
COUNT COUNT
DOWN
UP
'--'"
INPUTS
16
17
Is
Qc
Qo
GND
'--'"
OUTPUTS
Order Number DM54193J or DM54193W
See NS Package Number J16A or W16A
4-214
TUF/6563-1
Absolute Maximum Ratings
....CD
Co:I
(Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature
Range
-55'C to
Storage Temperature Range
-65'C to
+ 125'C
+ 150'C
Recommended Operating Conditions
Symbol
Parameter
Min
Nom
Max
Units
4.5
5
5.5
V
0.8
V
High Level Output Current
-0.4
mA
10l
Low Level Output Current
16
mA
felK
Clock Frequency (Note 4)
0
20
MHz
tw
Pulse Width
(Note 4)
Clock Low
30
Clock, Clear High
Load Low
20
Vee
Supply Voltage
VIH
High Level Input Voltage
Vil
Low Level Input Voltage
10H
V
2
tsu
Data Setup Time (Note 4)
20
tH
Hold Time (Note 4)
0
TA
Free Air Operating Temperature
25
ns
ns
ns
-55
125
'C
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 1)
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vee = Min,ll = -12 mA
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
Vil = Max, VIH = Min
VOL
Low Level Output
Voltage
Vee = Min, 10l = Max
VIH = Min, Vil = Max
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 5.5V
IIH
High Level Input Current
Vee = Max, VI = 2.4V
40
/LA
III
Low Level Input Current
Vee = Max, VI = O.4V
-1.6
mA
los
Short Circuit Output Current
Vee = Max (Note 2)
-55
mA
89
mA
2.4
V
-20
Supply Current
Vee = Max (Note 3)
Icc
Note 1: All typical. are at Vee = SV. TA = 2S' e.
Note 2: Not more than one output should be shorted at a time.
Nole 3: Icc Is measured wHh all outputs open, CLEAR and LOAD Inputs grounded. and all other inputs at 4.SV.
Note 4: TA = 2S'C and Vee = SV.
65
0.4
V
1
mA
III
4-215
Switching Characteristics
Symbol
at Vee = 5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
Parameter
From (Input)
To (Output)
RL = 4000, CL = 15 pF
Min
Units
Max
fMAX
Maximum Clock Frequency
tpLH
Propagation Delay Time
Low to High Level Output
Count Up
to Carry
20
26
ns
tpHL
Propagation Delay Time
High to Low Level Output
Count Up
to Carry
24
ns
tpLH
Propagation Delay Time
Low to High Level Output
CountDown
to Borrow
24
ns
tpHL
Propagation Delay Time
High to Low Level Output
CountDown
to Borrow
24
ns
tpLH
Propagation Delay Time
Low to High Level Output
Either Count
toO
38
ns
tpHL
Propagation Delay Time
High to Low Level Output
Either Count
toO
47
ns
tpLH
Propagation Delay Time
Low to High Level Output
Load
toO
40
ns
tpHL
Propagation Delay Time
High to Low Level Output
Load
toO
40
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clear
toO
35
ns
4-216
MHz
.....
CD
W
Logic Diagrams
193
oOWN (4)
CO UNT
(13) BORROW
OUTPUT
'\....
(12) CARRY
OUTPUT
..r
-
oATA(15)
INP UT A
'In.
I
[Lf
......
......
l
0A
1-..£2 OUTPUT 0A
pT
UP (5)
COU NT
OA
.,..
D ~
,- h
OATA (1)
INPUT B
~
-
r-I '7e' I-~ OUTPUT as
I?T
Os
1
OAIA (10)
INPUT C
,
Lrh
:L>T
'"L.../
- "'\n.
~
-
~t-~OU
:::::::::j
,-
Oc
::[»
DATA (9)
INPUT 0
CLEAR
(14)
TPUT 0c
poT
:L>T
,~
"j=L.J
~
Ff
,
,...JI-
(7)
0D t--~ OUTPU T 0D
I?T
LOAO~
,,
11)
OD
I
TLiF/6563-2
4-217
Timing Diagram
193 Binary Counter
Typical Clear, Load, and Count Sequences
~w--Il~
_____________________________________
LOAD
r-+-+--+~,
--- ----- ---- ------ -- --- -- -- -- -- ----- -- ------ ---
I:::::::::::::::::::::::::::::::::::::::::::::::
,
--+-+--H----------------------------------------------r-++--+-" -- -- -- ----- -------- -- -- -- --- -- --- -- -- - -- -------
DATA
M-+-H;::::::::::::::::::::::::::::::::::::::::':::::::
~U~----+~---+-r--'
UP
~NT ...-+_+---~4_---4_------------------------4___,
DOWN
OUTPUTS
00 ___ _
CARRY
BORROW
I
21' I
I-- ~u~ ----t I-- ~NT
14
15
0
1
1
0
UP
Nole A: Clear overrides load, data, and count inputs,
Nole B: When counting up, count-down input must be high, when counting down, count-up input must be high,
4-218
15
14
13
1
DOWN - - ;
TUF/6563-3
r------------------------------------------------------------------------------------,
~
co
oIi>o
~National
~ Semiconductor
DM54194
4-Bit Bidirectional Universal Shift Registers
General Description
This bidirectional shift register is designed to incorporate
virtually all of the features a system designer may want in a
shift register; it features parallel inputs, parallel outputs,
right-shift and left-shift serial inputs, operating-mode-control
inputs, and a direct overriding clear line. The register has
four distinct modes of operation, namely:
Parallel (broadside) load
Shift right (in the direction QA toward QD)
Shift left (in the direction QD toward QA)
Inhibit clock (do nothing)
Synchronous parallel loading is accomplished by applying
the four bits of data and taking both mode control inputs, SO
and 51, high. The data is loaded into the associated flipflops and appears at the outputs after the positive transition
of the clock input. During loading, serial data flow is inhibited.
Shift right is accomplished synchronously with the riSing
edge of the clock pulse when SO is high and 51 is low.
Serial data for this mode is entered at the shift-right data
input. When SO is low and 51 is high, data shifts left synchronously and new data is entered at the shift-left serial
input.
Clocking of the flip-flop is inhibited when both mode control
inputs are low. The mode controls of the DM541941
DM74194 should be changed only while the clock input is
high.
Features
• Parallel inputs and outputs
• Four operating modes:
Synchronous parallel load
Right shift
Left shift
Do nothing
• Positive edge-triggered clocking
• Direct overriding clear
• Typical clock frequency 36 MHz
• Typical power dissipation 195 mW
Connection Diagram
Dual-In-Llne Package
OUTPUTS
Qe
QC
14
2
CLEAR SHIFT
RIGHT
SERIAL
INPUT
3
A
QD \ CLOCK
13
4
e
12
c
5
11
D6
~-----Y------~
PARALLEL INPUTS
S1
10
SHI~
9
G!:
~FT
SERIAL
INPUT
Order Number DM54194J or DM54194W
See NS Package Number J16A or W16A
4-219
so
TL/F/6564-1
•
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
OM 54
-55'Cto + 125'C
Storage Temperature Range
-65'Cto + 150'C
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Recommended Operating Conditions
Symbol
DM54194
Parameter
Units
Min
Nom
Max
4.5
5
5.5
V
0.8
V
Vee
Supply Voltage
VIH
High Level Input Voltage
Vil
Low Level Input Voltage
10H
High Level Output Current
-0.8
mA
16
mA
25
MHz
10l
Low Level Output Current
felK
Clock Frequency (Note 4)
tw
Pulse Width (Note 4)
tsu
2
V
0
Clock
20
Clear
20
Mode
30
Data
20
Setup Time (Note 4)
tH
Hold Time (Note 4)
0
tREl
Clear Release Time (Note 4)
25
TA
Free Air Operating Temperature
36
ns
ns
ns
ns
-55
125
'C
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 1)
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vee = Min, 11= -12 mA
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
Vil = Max, VIH = Min
VOL
Low Level Output
Voltage
Vee = Min, 10l = Max
VIH = Min, Vil = Max
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 5.5V
IIH
High Level Input Current
Vee = Max, VI = 2.4V
40
/LA
III
Low Level Input Current
Vee = Max, VI = 0.4V
-1.6
mA
los
Short Circuit Output Current
Vee = Max (Note 2)
-57
mA
2.4
3.4
0.2
-20
V
0.4
V
1
mA
Supply Current
39
63
mA
Vee = Max (Note 3)
Icc
Note 1: All typical. are at Vee = SV. TA = 2S'C.
Note 2: Not more than one output should be shorted at a time.
Nola 3: With all outputs open, Inputs A through D grounded, and 4.SV applied to SO, SI, CLEAR and the serlallnputs, lee Is tested with a momentary ground, then
4.SV applied to CLOCK.
Note 4: TA = 2S'C and Vee = SV.
4-220
Switching Characteristics at Vee = 5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
Symbol
From (Input)
To (Output)
Parameter
RL
= 4000, CL = 15 pF
Min
Units
Max
MHz
fMAX
Maximum Clock Frequency
tpLH
Propagation Delay Time
Low to High Level Output
Clock
toO
25
22
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clock
toO
26
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clear
toO
30
ns
Function Table
Inputs
Mode
Clear
S1
Clock
SO
outputs
Serial
Left
Right
Parallel
A
B
C
QA
QB
X
X
X
X
X
X
X
X
X
L
L
X
X
L
X
X
X
X
X
X
OBO
OAO
H
H
X
X
b
b
d
a
c
a
X
X
X
X
L
H
H
X
H
OAn
L
H
X
L
X
X
X
X
L
OAn
L
H
H
X
X
X
X
X
OBn
Oen
H
L
L
X
X
X
X
X
OBn
OCn
L
X
L
X
X
X
X
X
X
OAO
OBO
H = High Level (steady state), L = Low Level (steady state), X = Don't Care (any input, including transitions)
j = Transition from low to high level; a, b, c, d = The level of steady state input at inputs A, B, C, or D, respectively
OAO, OBO, OCO, ODO = The level of OA, OB, Oc, or OD, respectively, before the indicaled steady slale inpul condilions were established.
CAn. OBn. Ceo. COn = The level of OA. Oa. Qc. respectively. before the most recent t transition of the clock.
L
H
H
H
H
H
H
H
t
t
t
t
t
4·221
Qc
QD
D
L
Oco
c
OBn
OBn
OOn
OOn
Oeo
L
000
d
Oen
Oen
H
L
000
Logic Diagram
194
SHIFT
RIGHT
SERIAL
PARALLEL INPUTS
INPUT
A
(2)
(3)
o
C
15)
B
(4)
(6)
SHIFT
LEFT
SERIAL
INPUT
(7)
(12)
(13)
(14)
DC
DB
Do,
PARALLEL OUTPUTS
TL/F/6564-2
Timing Diagram
Typical Clear, Load, Right-Shift, Left-Shift,
Inhibit and Clear Sequences
CLOCK
MODE!SO
(NPUTS S1
CONTROL
CLEAR
SERIAL! R
DATA
INPUTS L
PARALLEL{:
DATA
INPUTS C
D
OUTPUTS{::
:~
ac:
QD
:+-+---4
--i---INHIBIT
CLEAR LOAD
CLEAR
TL/F/6564-3
4-222
......
CD
.....
~National
~ Semiconductor
DM74197
Presettable Binary Counters
General Description
The '197 ripple counter contains divide-by-two and divideby-eight sections which can be combined to form a modulo16 binary counter. State changes are initiated by the falling
edge of the clock. The '197 has a Master Reset (MR) input
which overrides all other inputs and asynchronously forces
all outputs LOW. A Parallel Load input (PL) overrides
clocked operations and asynchronously loads the data on
the Parallel Data inputs (Pn) into the flip-flops. This preset
feature makes the circuit usable as a programmable counter. The circuit can also be used as a 4-bit latch, loading
data from the Parallel Data inputs when PL is LOW and
storing the data when PL is HIGH.
Connection Diagram
Dual-In-Llne Package
PL-l
14 ~VCC
Q2- 2
13H.lR
P2- 3
12
PO- 4
QO- 5
II~P3
~Q3
10 -PI
CPl- 6
9 -Ql
GND- 7
8 -CPO
TUF/97B4-1
Order Number DM74197N
See NS Package Number N14A
Pin Names
CPO
CPl
PO-P3
PL
00
01-03
Description
+ 2 Section Clock Input
(Active Falling Edge)
+ 8 Section Clock Input
(Active Falling Edge)
Asynchronous Master Reset Input
(Active LOW)
Parallel Data Inputs
Asynchronous Parallel Load Input
(Active LOW)
+ 2 Section Output"
+ 8 Section Outputs
'00 output is guaranteed to drive the full rated fan-out plus the CPl input.
•
4-223
Absolute Maximum Ratings
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specIfied devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
Operating Free Air Temperature Range
DM74
Storage Temperature Range
5.5V
O"Cto +70"C
-65·Cto + 150·C
Recommended Operating Conditions
Symbol
DM74197
Parameter
Vee
Supply Voltage
VIH
High level Input Voltage
VIL
low level Input Voltage
Units
Min
Nom
Max
4.75
5
5.25
V
V
2
0.8
V
IOH
High level Output Current
-0.25
IOL
low level Output Current
16
mA
70
·C
mA
TA
Free Air Operating Temperature
0
Is (H)
ts (l)
Setup Time HIGH or lOW
Pn to Pl
10
15
ns
th (H)
th (l)
Hold TIme HIGH or lOW
Pnto Pl
0
0
ns
tw(H)
CPO Pulse Width HIGH
20
ns
tw(H)
CP1 Pulse Width HIGH
30
ns
tw(l)
Pl Pulse Width lOW
20
ns
tw(l)
liilR Pulse Width lOW
15
ns
tree
Recovery TIme Pl to CPn
20
ns
tree
Recovery Time MR to CPn
20
ns
Electrical Characteristics
Over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
= Min, II = -12 mA
= Max
VI
Input Clamp Voltage
Vee
VOH
High level Output Voltage
Vee = Min,lOH
VIL = Max
VOL
low level Output Voltage
Vee = Min,loL
VIH = Min
II
Input Current @ Max
Input Voltage
Vee
IIH
High level Input Current
IlL
low level Input Current
los
Short Circuit
Output Current
Min
2.4
= Max
Typ
(Note 1)
Max
Units
-1.5
V
3.4
0.2
V
0.4
V
1
mA
Vee
1
mA
Vee
40
~
-1.6
mA
-57
mA
59
mA
= Max, VI = 5.5V
= Max, VI = 5.5V, CPl
= Max, VI = 2.4V
Vee = Max, VI = 0.4V
Vee = Max
(Note 2)
Supply Current
Vee = Max, All Inputs
Icc
Note 1: All typical. are at Vee = 5V. TA = 25"e.
Nole 2: Not more than one output should be shorted at a time.
4-224
= GND
-18
.....
CO
.....
Switching Characteristics
Vee =
+ 5.0V, TA = + 25'C (See Section 1 for waveforms and load configurations)
Symbol
CL = 15pF
Parameter
Units
RL = 4000.
Min
Max
f max
Maximum Count
Frequency at CPO
50
MHz
f max
Maximum Count
Frequency at CPl
25
MHz
tpLH
tpHL
Propagation Delay
CPO to 00
12
15
ns
tpLH
tpHL
Propagation Delay
CPl to 01
18
21
ns
tpLH
tpHL
Propagation Delay
CPl to 02
36
42
ns
tpLH
tpHL
Propagation Delay
CPl to 03
54
63
ns
tpLH
tpHL
Propagation Delay
Pn to On
24
38
ns
tpLH
tpHL
Propagation Delay
PLtoO n
33
36
ns
tpHL
Propagation Delay
MRtoOn
37
ns
Logic Symbol
bi Yi r
PL PO Pt P2 P3
8-0 CPO
6-0 CPt
MR 00 Ot 02 03
X! ! L~
Vee = Pin 14
GND = Pin 7
4-225
TUF/9784-2
.;- 16 State Diagram
Mode Selection Table
Inputs
Response
MR
PL
CP
L
H
H
X
L
H
X
X
"'-
an Forced LOW
Pn -+ an
Count Up
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
TLIF19784-3
Logic Diagram
P1
PO
P2
P3
~---.------a)~~~----------~--------~~--------~
~O------------~~
~1--------------------~----~----------~------~~
01
00
02
03
TLIF19784-4
4-226
,----------------------------------------------------------------------------, ......
~
CD
~National
~ Semiconductor
54279/DM74279 Quad Set-Reset Latch
General Description
This device contains four independent set-reset type flipflops with one Q output each.
Connection Diagram
Dual·ln·llne Package
lR---r-\..
Vee
4S
lSI
1S2 -,-""1.-r
lQ.....;.+-----'
4ft
'-----+~4Q
2R
2S
3S2
2Q
3R
~D
~
3S1
TLIFI97B5-1
Order Number 54279DMQB, 54279FMQB or DM74279N
NS Package Number J16A, N16E or W16A
Pin Names
Description
Reset Inputs (Active Low)
Set Inputs (Active low)
Outputs
Rn
Sn
Q
Truth Table
51
l
l
X
H
H
H
Inputs
52
l
X
l
H
H
R
Output
Q
l
H
H
l
H
h
H
H
l
No Change
= HIGH Voltage Level
L = LOW Voltage Level
X
= Immaterial
h = The output is HIGH as long as 51 or 52 is LOW. " all inputs go HIGH
simultaneously, the output state is indeterminate; otherwise, it follows the
Truth Table.
4-227
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
OHlce/Dlstrlbutors for availability and speCifications.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
54
-55'Cto + 125'C
DM74
O'Cto +70'C
Storage Temperature Range
- 65'C to + 150"C
Recommended Operating Conditions
Symbol
DM74279
54279
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
VIL
Low Level Input Voltage
IOH
High Level Output Current
IOL
Low Level Output Current
TA
Free Air Operating Temperature
Units
Min
V
2
V
0.8
0.8
V
-0.8
-0.8
mA
16
mA
70
·c
16
-55
125
0
Electrical Characteristics
over Recommended Operating Free Air Temperature Range (Unless Otherwise Noted)
Symbol
Parameter
Conditions
VI
Input Clamp Voltage
Vee = Min, 11= -12 mA
VOH
High Level
Output Voltage
Vee = Min,IOH = Max,
VIL = Max
VOL
Low Level
Output Voltage
Vee = Min, IOL = Max,
VIH = Min
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 5.5V
IIH
High Level Input Current
2.4
Typ
(Note 1)
Max
Units
-1.5
V
3.4
V
1
mA
Vee = Max, VI = 2.4V
40
p.A
-1.6
mA
Low Level Input Current
Vee = Max, VI = O.4V
los
Short Circuit
Output Current
Vee = Max
(Note 2)
Supply Current
Vee = Max, R = OV
0.2
V
0.4
IlL
lee
Min
I 54
J DM74
-20
-55
-18
-57
30
mA
Switching Characteristics
Symbol
54/DM74
Parameter
Min
Units
Max
tpLH
tpHL
Propagation Delay
StoQ
22
15
ns
tpHL
Propagation Delay
RtoQ
27
ns
Note 1: All typical. are at Vex; = SV, TA = 2S'C.
Note 2: Not more than one output should be shorted at a time.
4-228
mA
r-------------------------------------------------------------------------,~
co
Co)
'?'A National
~ Semiconductor
54283/DM74283
4-Bit Binary Full Adder (with Fast Carry)
General Description
The '283 high speed 4-bit binary full adders with internal
carry lookahead accept two 4-bit binary words (AO-AS, 8083) and a Carry input (CO), They generate the binary Sum
outputs (SO-53) and the Carry output (C4) from the most
significant bit. They operate with either active HIGH or active LOW operands (positive or negative logic),
Connection Diagram
Dual-In-Llne Package
Sl-l
"-"
81- 2
A1- 3
16 -Vee
15 -82
50- 4
14 -A2
13 -52
AO- 5
12 :-A3
80- 6
11 :-83
CO- 7
10 f-53
GND- 8
9 r-C4
TUF/9786-1
Order Number 54283DMQB, 54283FMQB or DM74283N
See NS Package Number J16A, N16E or W16A
Description
Pin Names
A Operand Inputs
8 Operand Inputs
Carry Input
Sum Outputs
Carry Output
AO-A3
80-83
CO
SO-53
C4
•
4-229
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
Operating Free Air Temperature Range
54
DM74
Storage Temperature Range
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation~
5.5V
- 55'C to + 125'C
O'Cto +70'C
-65'Cto + 150'C
Recommended Operating Conditions
Symbol
54283
Parameter
Vcc
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
DM74283
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
0.8
0.8
V
2
V
2
10H
High Level Output Current
-0.4
-0.4
mA
10L
Low Level Output Current
16
16
mA
TA
Free Air Operating Temperature
70
'C
Max
Units
-1.5
V
-55
125
0
Electrical Characteristics
Over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
VI
Input Clamp Voltage
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
II
Input Current @ Max
Input Voltage
IIH
High Level Input Current
Conditions
= Min, II = -12 mA
Vcc = Min, IOH = Max
VIL = Max
Vee = Min, IOL = Max
VIH = Min
Vee = Max, VI = 5.5V
Min
Typ
(Note 1)
Vcc
2.4
3.4
0.2
V
0.4
V
1
mA
Vcc
= Max, VI = 2.4V
40
/Jo A
= Max, VI = 0.4V
-1.6
mA
IlL
Low Level Input Current
Vcc
los
Short Circuit
Output Current at Sn
Vee = Max
(Note 2)
54
-20
-55
DM74
-20
-55
Short Circuit
Output Current at C4
Vee = Max
(Note 2)
54
-20
-70
DM74
-18
-70
Supply Current with
Outputs High
Vee
los
ICCH
= Max
54
99
DM74
110
Note 1: All typical. are at Vee = SV. TA = 2S'C.
Not. 2: Not more than one output should be shorted at a time.
4-230
mA
mA
mA
Switching Characteristics
Vee =
+ 5.0V, TA
=
+ 25'C (See Section
Symbol
1 for waveforms and load configurations)
CL = 15 pF, RL = 4000
Parameter
Min
Units
Max
tpLH
tpHL
Propagation Delay
COorS n
21
21
ns
tpLH
tpHL
Propagation Delay
An or 8 n to Sn
24
24
ns
tpLH
tpHL
Propagation Delay
CO to C4
14
16
ns
tpLH
tpHL
Propagation Delay
An or 8 n to C4
14
16
ns
Functional Description
The '283 adds two 4-bit binary words (A plus 8) plus the
incoming carry CO. The binary sum appears on the Sum
(SO-S3) and outgoing carry (C4 outputs. The binary weight
of the various inputs and outputs is indicated by the subscript numbers, representing powers of two.
2 0 (AO + 80 + CO) + 21 (A1 + 81) + 22(A2 + 82) +
23 (A3 + 83) = SO + 2S1 + 4S2 + 8S3 + 16C4
Where (+) = plus
Interchanging inputs of equal weight does not affect the operation. Thus CO, AO, 80 can be arbitrarily assigned to pins
5, 6 and 7. Due to the symmetry of the binary add function,
the '283 can be used either with all inputs and outputs active HIGH (positive logic) or with all inputs and outputs active LOW (negative logic). Note that if CO is not used it must
be tied LOW for active HIGH logic or tied HIGH for active
LOW logic.
Example:
Due to pin limitations, the intermediate carries of the '283
are not brought out for use as inputs or outputs. However,
other means can be used to effectively insert a carry into, or
bring a carry out from, an intermediate stage. Rgure a
shows a way of making a 3-bit adder. Tying the operand
inputs of the fourth adder (A3, 83) LOW makes S3 dependent ony on, and equal to, the carry from the third adder.
Using somewhat the same principle,Figure b shows a way
of dividing the '283 into a 2-bit and a I-bit adder. The third
stage adder (A2, 82, S2) is used merely as a means of
getting a carry (Cl 0) signal into the fourth stage (via A2 and
82) and bringing out the carry from the second stage on S2.
Note that as long as A2 and 82 are the same, whether
HIGH or LOW, they do not infuence S2. Similarly, when A2
and 82 are the same the carry into the third stage does not
influence they carry out of the third stage. Figure c shows a
method of implementing a 5-input encoder, where the inputs
are equally weighted. The outputs SO, SI and S2 present a
binary number equal to the number of inputs 11-15 that are
true. Figure d shows one method of implementing a 5-input
majority gate. When three or more of the inputs 11-15 are
true, the output M5 is true.
CO AOAI A2A3 BOBI B2B3 SOSI S2S3 C4
Logic Levels L L H L H H L L H H H L L H
~ctive HIGH 0 0 1 0 1 1 0 0 1 1 1 0 0 1
~ctiveLOW 1 1 0 1 0 0 1 1 0 0 0 1 1 0
Active HIGH: 0
+ 10 +
9 = 3
+ 16
Active LOW:
I I I I I I
1+
I T
5
+6
=
12 + 0
L
C10
AD BO A1 B1
AD BO A1 B1 A2 B2 A3 B3
-
J IJJ
AD BO A1 B1
C4-
CO
SO
I
Sl
I
S2
I
L-C3
TLlF/9786-3
FIGURE a. 3-Bit Adder
I
rl
A;oai o
,, A2 B2 A3 B3
,
I
,,
CO- CO
S3
I
SO
Sl
52
Jo
J1
J2
C4-C11
,
\
I
S3
: s!o
TLlF/9786-4
FIGURE b. 2-Bit and I-Bit Adders
4-231
~ .---------------------------------------------------------------------------~
re
Functional Description (Continued)
13
11 12
13
r 1 1 ; Ii
I I
co
-
C4
50
51
52
AO BO Al Bl A2 B2 A3 B3
C4-
CO
53
50
51
I
I
52
S3
I
M5
TLIFI97B6-5
FIGURE c. 5-lnput Encoder
TLIFI97BB-6
FIGURE d. 5-lnput Majority Gate
Logic Symbol
5
7
6
3
2 14 15 12 11
CO
C4
50
51
4
52
53
13
10
TLIFI9786-2
vee = Pin 16
GND=Pin8
Logic Diagram
co
AO
80
so
AI
51
81
KI.
92
A3
53
52
93
C4
TUF19786-7
4·232
r-------------------------------------------------------------------------,
J?'A National
~
CD
CD
~ Semiconductor
54298
Quad 2-Port Register (Multiplexer With Storage)
General Description
Features
The '298 is a quad 2-port register. It is the logical equivalent
of a quad 2-input multiplexer followed by a quad 4-bit edgetriggered register. A Common Select input selects between
two 4-bit input ports (data sources). The selected data is
transferred to the output register synchronous with the
HIGH-to-LOW transition of the Clock input.
- Select from two data sources
_ Fully edge-triggered operation
Connection Diagram
Logic Symbol
iii Iii I i
Dual-In-Une Package
I1 b -
16 ~Vcc
1
11.- 2
15 ~Oa
10- S
10.- 3
14 r-0b
13 r-O.
12 r-Od
ll-C CP
10b- "
11.- 5
11d- 6
11 ~CP
10d- 7
10
~s
TLlF/l0215-2
9 ~IO.
GND- 8
vee = Pin 16
GND = PinS
TL/F/l0215-1
Order Number 54298DMQB or 54298FMQB
See NS Package Number J16A or W16A
Pin Names
S
CP
lOa-lad
11a-11d
Oa,Od
Description
Common Select Input
Clock Pulse Input (Active Falling Edge)
Source a Data Inputs
Source 1 Data Inputs
Flip-Flop Outputs
•
4-233
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature
Range
- 55'C to + 125'C
Storage Temperature Range
-65'Cto + 150'C
Recommended Operating Conditions
Symbol
54298
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
Units
Min
Nom
Max
4.5
5
5.5
V
2
V
VIL
Low Level Input Voltage
O.B
V
10H
High Level Output Current
-O.B
mA
10L
Low Level Output Current
16
mA
125
'c
-55
TA
Free Air Operating Temperature
ts(H)
ts(L)
Setup Time HIGH or LOW
StoCP
25
25
ns
th (H)
th (L)
Hold Time HIGH or LOW
StoCP
0
0
ns
ts(H)
ts(L)
Setup TIme HIGH or LOW
lox or 11x to CP
15
15
ns
th (H)
th (L)
Hold Time HIGH or LOW
lox or 11x to CP
5.0
5.0
ns
Iw(H)
twILl
CP Pulse Width HIGH or LOW
20
20
ns
Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
Conditions
Min
= Min, II = -12 mA
VI
Input Clamp Voltage
Vee
VOH
High Level
Output Voltage
Vee = Min, 10H = Max,
VIL = Max, VIH = Min
VOL
Low Level
Output Voltage
Vee = Min, 10L = Max,
VIH = Min, VIL = Max
II
Input Current @
Max Input Voltage
Vee
IIH
High Level
Input Current
IlL
loS
Typ
(Note 1)
Max
Units
-1.5
V
2.4
V
0.4
V
= Max, VI = 5.5V
1
mA
Vee
= Max, VI = 2.4V
40
/LA
Low Level
Input Current
Vee
= Max, VI = O.4V
-1.6
mA
Short Circuit
Output Current
Vee = Max
(Note 2)
-57
mA
65
mA
-20
Supply Current
Vee = Max (Note 3)
lee
Note 1: All typlcals are at Vee = SV, TA = 2S'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: lee Is measured with all outputs open and all inputs grounded.
4-234
r-------------------------------------------------------------------------------------~ ~
Switching Characteristics Vee = + 5.0V, TA = + 25°C (See Section 1 for test waveforms and output load)
Symbol
CL = 15pF
RL = 4000
Parameter
Min
Units
Max
Propagation Delay, CP to Q n
27
ns
32
Functional Description
~
Truth Table
This device is a high speed quad 2-port register. It selects
four bits of data from two sources (ports) under the control
of a Common Select Input (5). The selected data is transferred to the 4-bit output register synchronous with the
HIGH-to-LOW transition of the Clock input (CP). The 4-blt
output register is fully edge-triggered. The Data inputs {lnx>
and Select input (5) need be stable only one setup time
prior to the HIGH-to-LOW transition of the clock for predictable operation.
Inputs
Output
S
lox
11x
Qx
I
I
h
h
I
h
X
X
X
X
I
h
L
H
L
H
I = LOW Voltage Level one setup time prior to the HIGH·Io-LOWclock
transition.
h = HIGH Voltage Level one setup time prior to the HIGH·to·LOW clock
transition.
H = HIGH Voltage level
L = LOW Voltage level
X = Immaterial
Logic Diagram
Qd
TLIFll0215-3
4-235
•
~National
~ Semiconductor
DM54365 Hex TRI-STATE® Buffers
General Description
This device contains six independent gates each of which
performs a non-inverting buffer function. The outputs have
the TRI-STATE feature. When enabled, the outputs exhibit
the low impedance characteristics of a standard TTL output
with additional drive capability to permit the driving of bus
lines without external resistors. When disabled, both the
output transistors are turned off presenting a high-impedance state to the bus line. Thus the output will act neither as
a significant load nor as a driver. To minimize the possibility
that two outputs will attempt to take a common bus to opposite logiC levels, the disable time is shorter than the enable
time of the outputs.
Connection Diagram
Dual-In-Llne Package
A4
V4
10
111
AI
VI
A2
V2
A3
V3
GND
TLlF/6570-1
Order Number DM54365J or DM54365W
See NS Package Number J16A or W16A
Function Table
Y=A
Input
Output
01
02
A
Y
L
L
H
X
L
L
X
H
L
H
X
X
L
H
Hi-Z
Hi-Z
H = High LogiC Level
L = Low Logic Level
X = Either Low or High Logic Level
HI·Z = TRI·STATE (Outputs are disabled)
4-236
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature
Range
-55'Cto + 125'C
Storage Temperature Range
- 65'C to + 150'C
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "£Iectrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Recommended Operating Conditions
Symbol
DM54365
Parameter
Units
Min
Nom
Max
4.5
5
5.5
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
0.8
V
10H
High Level Output Current
-2
mA
10L
Low Level Output Current
32
mA
TA
Free Air Operating Temperature
125
'C
Electrical Characteristics
Symbol
Input Clamp Voltage
VOH
High Level Output
Voltage
VOL
Low Level Output
Voltage
II
Input Current @ Max
Input Voltage
IIH
High Level Input Current
IlL
Low Level Input Current
10ZH
10ZL
lOS
2
Off-State Output Current
with High Level Output
Voltage Applied
V
-55
over recommended operating free air temperature range (unless otherwise noted)
Parameter
VI
V
Conditions
= Min,ll = -12 mA
Vee = Min, 10H = Max
VIL = Max, VIH = Min
Vee = Min, 10L = Max
VIH = Min, VIL = Max
Vee = Max, VI = 5.5V
Min
Typ
(Note 1)
Vee
2.4
0.2
= Max, VI = 2.4V
Vee = Max
A
VI = 0.5V (Note 4)
Vee = Max
A
VI = 0.4V (Note 5)
Vee = Max
G
VI = 0.4V
Vee = Max, Va = 2.4V
VIH = Min, VIL = Max
Vee = Max, Va = 0.4V
VIH = Min, VIL = Max
Short Circuit Output Current
Vee
= Max (Note 2)
Supply Current
Vee = Max (Note 3)
ICC
Note 1: All typlcals are at Vee - 5V, TA = 25'C.
Note 2: Not more than one output should be shorted at a time.
Note 3: Icc Is measured with the data Inputs grounded, and the output controls at 4.5V.
Note 4: Both (3' Inputs are at 2V.
Note 6: Both ~ Inputs are at O.4V.
4-237
Units
-1.5
V
3.1
Vee
Off-State Output Current
with Low Level Output
Voltage Applied
Max
V
0.4
V
1
mA
40
,..A
-40
-1.6
mA
-1.6
-40
59
40
/loA
-40
/loA
-115
mA
85
mA
$witching Characteristics
at Vee = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
RL = 4000
Symbol
CL = 5pF
Parameter
Min
CL = 50pF
Max
Min
Units
Max
tpLH
Propagation Delay Time
Low to High Level Output
16
ns
tpHL
Propagation Delay Time
High to Low Level Output
22
ns
tPZH
Output Enable Time to
High Level Output
35
ns
tpZL
Output Enable Time to
Low Level Output
37
ns
tpHZ
Output Disable Time from
High Level Output
11
ns
tPL2
Output Disable Time from
Low Level Output
27
ns
4-238
~--------------------------------------------------------------------------~ ~
G)
......
~National
~ Semiconductor
DM54367 Hex TRI-STATE® Buffers
General Description
This device contains six independent gates each of which
performs a non-inverting buffer function. The outputs have
the TRI-STATE feature. When enabled, the outputs exhibit
the low impedance characteristics of a standard TIL output
with additional drive capability to permit the driving of bus
lines without external resistors. When disabled, both the
output transistors are turned off presenting a high-impedance state to the bus line. Thus the output will act neither as
a signficant load nor as a driver. To minimize the possibility
that two outputs will attempt to take a common bus to opposite logic levels, the disable time is shorter than the enable
time of the outputs.
Connection Diagram
Dual-In-Llne Package
vee
16
1I2
15
A6
A5
V6
14
11
12
13
A4
V5
V4
10
4
ill
Al
VI
V2
AZ
A3
V3
Order Number DM54367J or DM54367W
See NS Package Number J16A or W16A
Function Table
Y=A
Input
Output
G
A
Y
L
L
H
L
H
X
L
H
Hi-Z
H = High Logic Level
L = Low LogiC Level
X = Either Low or High Logic Level
Hi-Z = TRI-5TATE (Outputs are disabled)
4-239
GNU
TL/F/6572-1
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
Operating Free Air Temperature
Range
Storage Temperature Range
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
5.5V
- 55'C to
-65'Cto
+ 125'C
+ 150"C
Recommended Operating Conditions
Symbol
DM54367
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
Units
Min
Nom
Max
4.5
5
5.5
V
2
V
VIL
Low Level Input Voltage
0.8
V
10H
High Level Output Current
-2
mA
32
mA
125
·c
10L
Low Level Output Current
TA
Free Air Operating Temperature
-55
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
VI
Input Clamp Voltage
Vee = Min, 11= -12 mA
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
VIL = Max, VIH = Min
VOL
Low Level Output
Voltage
Vee = Min, 10L = Max
VIH = Min, VIL = Max
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 5.5V
IIH
High Level Input Current
Vee = Max, VI = 2.4V
III
Low Level Input
Current
Vee = Max
VI = 0.5V (Note 4)
A
Vee = Max
VI = O.4V (Note 5)
A
Vee = Max
VI = 0.4V
G
2.4
Typ
(Note 1)
Max
Units
-1.5
V
3.1
0.2
V
0.4
V
1
mA
40
/LA
-40
-1.6
mA
-1.6
Off-State Output Current
with High Level Output
Voltage Applied
Vee = Max, Vo = 2.4V
VIH = Min, Vil = Max
40
/LA
Off-State Output Current
with Low Level Output
Voltage Applied
Vee = Max, Va' = O.4V
VIH = Min, Vil = Max
-40
/LA
los
Short Circuit Output Current
Vee = Max (Note 2)
-115
mA
lee
Supply Current
Vee = Max (Note 3)
85
mA
10ZH
10Zl
Note 1: All typicals are at Vee = SV, TA = 2S'C.
Note 2: Not more than one output should be shorted at a time.
Note 3: Icc is measured wHh the data inputs grounded and the output controls at 4.SV.
Note 4: Both II Inputs are at 2V.
Note 5: Both G inputs are at O.4V.
4-240
-40
65
Switching Characteristics at Vee =
5V and TA = 25·C (See Section 1 for Test Waveforms and Output Load)
RL = 4000
Symbol
CL = 50pF
CL = 5pF
Parameter
Min
Max
Min
Units
Max
tpLH
Propagation Delay Time
Low to High Level Output
16
ns
tpHL
Propagation Delay Time
High to Low Level Output
22
ns
tPZH
Output Enable TIme
to High Level Output
35
ns
tpZL
Output Enable Time
to Low Level Output
37
ns
tpHZ
Output Disable Time
from High Level Output
11
ns
tpLZ
Output Disable Time
from Low Level Output
27
ns
4-241
~National
~ Semiconductor
DM54368 Hex TRI-STATE® Inverting Buffers
General Description
This device contains six independent gates each of which
performs an inverting buffer function. The outputs have the
TRI-STATE feature. When enabled, the outputs exhibit the
low impedance characteristics of a standard TTL output
with additional drive capability to permit the driving of bus
lines without external resistors. When disabled, both the
output transistors are turned off presenting a high-impedance state to the bus line. Thus the output will act neither as
a significant load nor as a driver. To minimize the possibility
that two outputs will attempt to take a common bus to opposite logic levels, the disable time is shorter than the enable
time of the outputs.
Connection Diagram
Dual-In-Llne Package
AS
A6
A1
Y1
A2
Y4
Y2
Y3
GND
Order Number DM54368J or DM54368W
See NS Package Number J16A or W16A
Function Table
Y=A
Inputs
Output
G
A
Y
L
L
L
H
H
L
H
X
Hi-Z
H = High logic Level
L = Low logic Level
X
= Either Low or High Logic Level
= TRI-STATE (Outputs are dissbled)
HI·Z
4-242
TUF/6573-1
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
Operating Free Air Temperature
Range
Storage Temperature Range
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
5.5V
-55'Cto
-65'Cto
+ 125'C
+ 150'C
Recommended Operating Conditions
Symbol
DM54368
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
Units
Min
Nom
Max
4.5
5
5.5
V
2
V
Vil
Low Level Input Voltage
O.B
V
10H
High Level Output Current
-2
mA
32
mA
125
'C
10l
Low Level Output Current
TA
Free Air Operating Temperature
Electrical Characteristics
Symbol
-55
over recommended operating free air temperature range (unless otherwise noted)
Parameter
Conditions
Min
VI
Input Clamp Voltage
Vee = Min, 11= -12 mA
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
Vil = Max, VIH = Min
VOL
Low Level Output
Voltage
Vee = Min, 10l = Max
VIH = Min, Vil = Max
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 5.5V
IIH
High Level Input Current
Vee = Max, VI = 2.4V
III
Low Level Input Current
Vee = Max
VI = 0.5V (Note 4)
A
Vee = Max
VI = 0.4V (Note 5)
A
Vee = Max
VI = 0.4V
G
2.4
Typ
(Note 1)
Max
Units
-1.5
V
3.1
0.2
V
0.4
V
1
mA
40
p.A
-40
-1.6
mA
-1.6
Off-State Output Current
with High Level Output
Voltage Applied
Vee = Max, Vo = 2.4V
VIH = Min, Vil = Max
40
p.A
Off-State Output Current
with Low Level Output
Voltage Applied
Vee = Max, Vo = 0.4V
VIH = Min, Vil = Max
-40
p.A
los
Short Circuit Output Current
Vee = Max (Note 2)
-115
mA
Icc
Supply Current
Vee = Max (Note 3)
77
mA
10ZH
10Zl
Nola 1: All typicals are at Vee
= SV, TA = 2S·C.
Nole 2: Not more than one output should be shorted at a time.
Nole 3: Icc is measured with the data inputs grounded, and the output controls al 4.SV.
Nole 4: Both Ci Inputs are a12V.
Nole 5: Both Ci inputs are at OAV.
4·243
-40
59
Switching Characteristics
at Vee = 5V and TA = 25·C (See Section 1 for Test Waveforms and Output Load)
RL = 4000
Symbol
Parameter
CL = 5pF
Min
Units
CL = 50pF
Max
Min
Max
tpLH
Propagation Delay TIme
Low to High Level Output
17
ns
tpHL
Propagation Delay Time
High to Low Level Output
16
ns
tPZH
Output Enable Time to
High Level Output
35
ns
tPZL
Output Enable TIme to
Low Level Output
37
ns
tpHZ
Output Disable Time from
High Level Output
11
ns
tpLZ
Output Disable Time from
Low Level Output
27
ns
4-244
,----------------------------------------------------------------------------, ....
~
N
W
J?"A National
~ Semiconductor
DM7123 Quad 2-lnput
Data Selectors/Multiplexers
General Description
Features
This device contains four 2-input multiplexers with common
input select logic and common output disable circuitry. The
DM7123 provides TRI-STATEI!> outputs. When the enable/
strobe input is at a low logic level, the outputs of all devices
are conventional TTL. However, when the enable/strobe input is raised to a high logic level, the outputs of the DM7123
go to the high-impedance third state. This device provides
the designer with TRI-STATE and/or low power pin/pin replacements for the popular DM9322 and DM54/DM74157
multiplexers.
• Pin equivalents popular DM9322 and DM54/DM74157
multiplexers
• Both conventional TTL and TRI-STATE outputs
available
• Typical propagation delay 9.5 ns
• Typical power dissipation 200 mW
Connection Diagram
Dual-In-Line Package
INPUTS
INPUTS
,..-.......--..... OUTPUT ,..-.......--.....
vcc ENABLE A4
B4
Y4
A3
B3
1,6
15
14
13
12
10
11
9
-
-
3
2
S
OUTPUT
Y3
A1
B1
Y1
6
5
4
B2
A2
Y2
OUTPUT
OUTPUT
SELECT
7
INPUTS
INPUTS
TUF/6574-1
Order Number DM7123J or DM7123W
See NS Package Number J16A or W16A
Function Table
Enable
L
L
L
Select
L
L
L
H
H
H
X
Inputs
Outputs
A
B
Y
L
H
X
X
X
X
X
L
H
L
H
L
H
Hi-Z
X
L = Low logic Level, H = High Logic Level
X = Either Low or High logic Level
HI-Z = TRI-STATE (Outputs are disabled)
4-245
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
7V
Supply Voltage
Input Voltage
5.5V
Operating Free Air Temperature Range
- 55·C to + 125·C
DM71
-65·C to + 150· C
Storage Temperature Range
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Recommended Operating Conditions
Symbol
DM7123
Parameter
Units
Min
Nom
Max
4.5
5
5.5
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
O.B
V
10H
High Level Output Current
-2
mA
10L
Low Level Output Current
16
mA
125
·C
TA
Symbol
2
V
-55
Free Air Operating Temperature
Electrical Characteristics
V
over recommended operating free air temperature range (unless otherwise noted)
Parameter
Conditions
VI
Input Clamp Voltage
Vee = Min,ll = -12mA
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
VIL = Max, VIH = Min
VOL
Low Level Output
Voltage
Vee = Min, 10L = Max
VIH = Min, VIL = Max
II
Input Current @ Max
Input Voltage
Vee
= Max, VI
Min
Typ
(Note 1)
Max
Units
-1.5
V
2.4
V
= 5.5V
0.4
V
1
mA
IIH
High Level Input Current
Vee = Max, VI = 2.4V
40
iJ.A
IlL
Low Level Input Current
Vee = Max, VI = O.4V
-1.6
mA
10ZH
Off-State Output Current
with High Level Output
Voltage Applied
Vee = Max, Vo = 2.4V
VIH = Min, VIL = Max
40
iJ.A
Off-State Output Current
with Low Level Output
Voltage Applied
Vee = Max, Vo = 0.4V
VIH = Min, VIL = Max
-40
iJ.A
Short Circuit
Output Current
Vee = Max
(Note 2)
-70
mA
51
mA
10ZL
los
-30
Supply Current
Vee = Max (Note 3)
Icc
Note 1: All typical. are at Vee = 5V, TA = 25·C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: Icc is measured with the Inputs grounded, and all outputs open.
4-246
40
r-------------------------------------------------------------------------------------, .....
~
Switching Characteristics
Symbol
at Vee = SV and TA = 2SoC (See Section 1 for Test Waveforms and Output Load)
From (Input)
To (Output)
Parameter
CL = 5pF
Min
CL = 50pF
Max
Min
Max
N
W
Units
Propagation Delay Time
Low to High Level Output
Data to
Output
4
15
ns
Propagation Delay Time
High to Low Level Output
Data to
Output
S
18
ns
Propagation Delay Time
Low to High Level Output
Select to
Output
S
23
ns
Propagation Delay Time
High to Low Level Output
Select to
Output
8
24
ns
tPZH
Output Enable Time to
High Level Output
Enable
toO
9
25
ns
tPZL
Output Enable Time to
Low Level Output
Enable
toO
10
30
ns
Output Disable Time from
High Level Output
Enable
toO
4
11
ns
Output Disable Time from
Low Level Output
Enable
toO
9
27
ns
Logic Diagram
84
SELEcr
(1)
A4
(13)
lc
83
(14)
A3
(10)
(11)
82
A2
(6)
81
(s)
Al
(3)
(2)
I
Vcc=PIN 16
GND = PIN 8
rNABLE(lS)
~O-----4-+--_~---+-+_--...J
.t
.!(12)
Y4
(9)
Y3
.l
(7)
Y2
(4)
Yl
TLlF/6574-2
•
4·247
~National
~ Semiconductor
DM7130 Magnitude Comparators
General Description
Features
This device offers comparisons to determine equality between two binary words. The DM7130 compares two ten-bit
words. A strobe override is provided. When the strobe is
taken to a high logic level, the output is forced to a high
logic level. The device also features open collector outputs
for expansion.
• Typical propagation delay 21 ns
• Typical power dissipation 240 mW
• Open-collector outputs for expansion
Connection Diagram
Dual-tn-Une Package
Vee A10 B10
A9
B9
A8
B8
A7
B7
A6
B8
OUTPUT
V
13
A1
B1
A2
B2
A3
B3
A4
B4
AS
BSSTROBE GND
Order Number DM7130J
See NS Package Number J24A
Function Table
Condition
A= B,A0;6 B
A=B
A0;6B
STROBE
S
Output
H
H
H
L
L
H = High logic Level
L = Low logic Level
4-248
y
L
TL/F/6575-1
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
Operating Free Air Temperature Range
-55·C to
DM71
Storage Temperature Range
-65·Cto
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "£Iectrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
5.5V
+ 125·C
+ 150·C
Recommended Operating Conditions
Symbol
DM7130
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
Units
Min
Nom
Max
4.5
5
5.5
V
V
2
Vil
Low Level Input Voltage
0.8
V
VOH
High Level Output Voltage
5.5
V
16
mA
125
·C
IOl
Low Level Output Current
TA
Free Air Operating Temperature
-55
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
=
=
VI
Input Clamp Voltage
Vee
leEX
High Level Output
Current
Vee = Min, Vo
VIH = Min
=
5.5V
VOL
Low Level Output
Voltage
Vee = Min, IOl
Vil = Max
=
Max
II
Input Current @ Max
Input Voltage
Vee
IIH
High Level Input Current
III
Low Level Input Current
Icc
Supply Current
Parameter
-12mA
0.2
Max
Units
-1.5
V
100
/LA
0.4
V
1
mA
=
Max, VI
=
5.5V
Vee
=
=
Vee =
Max, VI
40
/LA
Max, VI
=
=
2.4V
Vee
O.4V
-1.6
mA
70
mA
Switching Characteristics at Vee =
Symbol
Min, II
Typ
(Note 1)
Min
48
Max (Note 2)
5V and TA
=
From (Input)
To (Output)
25·C (See Section 1 for Test Waveforms and Output Load)
RL
=
Min
400n,CL
=
15pF
Units
Max
tplH
Propagation Delay Time
Low to High Level Output
Data to
Output
25
ns
tpHl
Propagation Delay Time
High to Low Level Output
Data to
Output
40
ns
tplH
Propagation Delay Time
Low to High Level Output
Strobe to
Output
18
ns
tpHl
Propagation Delay Time
High to Low Level Output
Strobe to
Output
30
ns
Note 1: All typicals are at Vee ~ 5V. TA ~ 25'C.
Note 2: Icc is measured with all inpuls grounded and all outputs open.
4-249
III
~National
~ Semiconductor
DM7136 6-Bit Unified Bus Comparator
with Open-Collector Outputs
General Description
Features
The DM7136 compares two binary words of two-to-six bits
in length and indicates matching (bit-for-bit) of the two
words. Inputs for one word are 54/74 series-compatible TIL
inputs, whereas those of the second word are high-impedance receivers driven by a terminated data bus. These bus
inputs include 0.65V typical hysteresis which provides 1.4V
noise immunity. The DM7136 has open-collector outputs
which go to the high state upon equality and is expandable
to n bits by coliector-ORing. The device has an output latch
which is strobe controlled.
The transfer of information to the output occurs when the
STROBE input goes from a logic "1" to a logic "0" state.
Inputs may be changed while the STROBE is at the logic
"1" level, without affecting the state of the output. These
devices are useful as address comparators in computer systems utilizing unified data bus organization.
•
•
•
•
•
Low bus input current 15 p.A typ
High bus input noise immunity 1.4V typ
Bus inputs comply with IEEE 488-1975
TIL-compatible output
Output latch provision
Connection Diagram
Dual-In-Llne Package
86
T8
15
14
2
81
T1
3
82
85
T5
B4
13
4
T2
12
5
B3
T4
OUTPUT
11
10
8
7
T3
fiiiOiiE
9
J8
GND
(BUS INPUT) (TTL INPUT)
TL/F/6577-1
Order Number DM7136J or DM7136W
See NS Package Number J16A or W16A
Function Table
Output
Condition
DM7118136
H
L
L
°Lalched In previous sta18.
H
L
= High logic Level
= Low Logic Level
4-250
.......
.....
Absolute Maximum Ratings (Note)
(0)
en
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
DM71
- 55'C to + 125'C
Storage Temperature Range
-65'Cto +150'C
Recommended Operating Conditions
Symbol
DM7136
Parameter
Units
Min
Nom
Max
Vee
Supply Voltage
4.5
5
5.5
V
VT+
Positive-Going Input
Threshold Voltage for
Bus Inputs (Note 1)
1.4
1.75
2
V
Negative-Going Input
Threshold Voltage for
Bus Inputs (Note 1)
0.9
1.1
1.35
V
VT-
VIH
High Level Input
Voltage for TTL
and Strobe Inputs
2
V
Low Level Input
Voltage for TTL
and Strobe Inputs
0.8
VOH
High Level Output Voltage
5.5
V
IOL
Low Level Output Current
16
mA
TA
Free Air Operating Temperature
125
'C
VIL
-55
V
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 2)
Max
Units
VI
Input Clamp Voltage
Vee = Min, 11= -12 mA
-1.5
V
leEX
High Level Output
Current
Vee = Min, Vo = 5.5V
VIL = Max, VIH = Min
250
/LA
VOL
Low Level Output
Voltage
Vee = Min, IOL = Max
VIH = Min, VIL = Max
0.4
V
II
Input Current @ Max
Input Voltage
Vee = Max
VI = 5.5V
High Level Input
Current
Vee = Max
VI = 2.4V
Low Level Input
Current
Vee = Max
VI = O.4V
TTL
-1.6
Strobe
-2.4
Bus Input Current
VI = 4V
Vee = Max
15
50
Vee = OV
1
50
50
74
IIH
IlL
liN
TTL
1
Strobe
2
TTL
40
Strobe
80
Supply Current
Vee = Max (Note 3)
Icc
Note 1: Vee = 5V.
Nole 2: Alilypicals are at Vee = 5V. TA = 25'0.
Nole 3: Icc is measured with all inputs grounded and all outputs open.
4-251
mA
/LA
mA
/LA
mA
Switching Characteristics at Vee = 5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load) .
RL = 4000.
From (Input)
Symbol
Parameter
Units
CL = 15pF
To (Output)
Min
Max
tpLH
Propagation Delay Time
Low to High Level Output
TIL to
Output
30
ns
tpHL
Propagation Delay Time
High to Low Level Output
TIL to
Output
30
ns
tpLH
Propagation Delay Time
Low to High Level Output
Busto
Output
45
ns
tpHL
Propagation Delay Time
High to Low Level Output
Busto
Output
45
ns
tpLH
Propagation Delay Time
Low to High Level Output
Strobe to
Output
30
ns
tpHL
Propagation Delay Time
High to Low Level Output
Strobe to
Output
30
ns
Logic Diagram
"~
B1 (1)
R
n~
B2 (3)
R
n~
B3 (5)
R
"~
B4 (11) R
T5
~
~
L-..(
~
(9) OUTPUT
as (13) R
T6
B6 (15)
R = High Impedance
Bus Recel••r
'fr)
STROBE
4-252
TUF/6577-2
r---------------------------------------------------------------------------~ ~
.....
en
~National
Q
~ Semiconductor
DM7160 Magnitude Comparator
General Description
Features
This device offers comparisons to determine equality between two binary words. The DM7160 compares two six-bit
words. A strobe override is provided. When the strobe is
taken to a high logic level, the output is forced to a high
logic level. The device also features open-collector outputs
for expansion.
• Typical propagation delay 21 ns
• Typical power disSipation 205 mW
• Open-collector outputs for expansion
Connection Diagram
Dual-In-Llne Package
Vee
A6
B6
AS
OUTPUT
BS
A4
B4
V
9
8
A1
B1
A2
B2
A3
B3
SmOBE GND
TL/F/657B-l
Order Number DM7160J or DM7160W
See NS Package Number J16A or W16A
Function Table
Condition
A = B,A"- B
A=B
A"-B
STROBE
S
Output
H
H
H
L
L
y
L
H = High Logic Level
L = Low Logic Level
II
4-253
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
DM71
- 55'C to
Storage Temperature Range
- 65'C to
+ 125'C
+ 150'C
Recommended Operating Conditions
Symbol
DM7160
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
Units
Min
Nom
Max
4.5
5
5.5
V
V
2
VIL
Low Level Input Voltage
0.8
VOH
High Level Output Voltage
5.5
V
IOL
Low Level Output Current
16
mA
TA
Free Air Operating Temperature
125
'C
Electrical Characteristics
Symbol
-55
V
over recommended operating free air temperature range (unless otherwise noted)
Parameter
Conditions
Min
Typ
(Note 1)
Max
Units
VI
Input Clamp Voltage
Vce = Min,ll = -12 mA
-1.5
V
ICEX
High Level Output
Current
Vcc = Min, Vo = 5.5V
VIL = Max
100
p.A
VOL
Low Level Output
Voltage
Vee = Min, IOL = Max
VIH = Min
0.4
V
II
Input Current @ Max
Input Voltage
Vcc = Max, VI= 5.5V
1
mA
0.2
IIH
High Level Input Current
Vcc = Max, VI = 2.4V
40
p.A
IlL
Low Level Input Current
Vcc = Max, VI = 0.4V
-1.6
mA
Icc
Supply Current
Vee = Max (Note 2)
60
mA
Switching Characteristics
Symbol
41
at Vcc = 5V and T A = 25'C (See Section 1 for Test Waveforms and Output Load)
Parameter
From (Input)
To (Output)
RL = 400n,CL = 15pF
Min
Units
Max
tpLH
Propagation Delay Time
Low to High Level OUtput
Data to
Output
25
ns
tpHL
Propagation Delay Time
High to Low Level Output
Data to
Output
40
ns
tpLH
Propagation Delay Time
Low to High Level Output
Strobe to
Output
18
ns
30
ns
Propagation Delay Time
Strobe to
High to Low Level Output
Output
Note 1: All typlcals are at Vee - SV, TA = 2S'C.
Note 2: lee Is measured with all Inputs grounded and all outputs open.
tpHL
4-254
~
o
o
~National
~ Semiconductor
9300/DM9300 4-Bit Parallel-Access Shift Register
General Description
The 9300 4-bit registers feature parallel inputs, parallel outputs, JK serial inputs, shift/load control input, and a direct
overriding clear. The registers have two modes of operation:
parallel (broadside) load and shift (in direction OA toward
00)·
Parallel loading is accomplished by applying the four bits of
data and taking the shift/load control input low. The data is
loaded into the associated flip-flops, and appears at the outputs after the positive transition of the clock input. During
loading, serial data flow is inhibited.
Shifting is accomplished synchronously when the shift/load
control input is high. Serial data for this mode is entered at
the JK inputs. These inputs permit the first stage to perform
as a JK, D or T-type flip-flop as shown in the function table.
These shift registers are fully compatible with most other
TTL and DTL families. All inputs, including the clock, are
buffered to lower the drive requirements to one normalized
Series 54174 load.
Features
•
•
•
•
•
Fully buffered inputs
Direct overriding clear
Synchronous parallel load
Parallel inputs and outputs from each flip-flop
Positive edge-triggered clocking
• J and K inputs to first stage
• Typical shift frequency-39 MHz
Connection Diagram
Dual-In-Line Package
OUTPUTS
OB
14
ar;
00
Oc
13
SHiFT/
CLOCK
11
12
LOAD
10
9
Order Number 9300DMQB,
9300FMQB or DM9300N
See NS Package Number
J16A, N16E or W16A
1
CLEAR
3
2
K
J
4
5
PI
,PO
SERIAL INPUTS
8
P2
7
P3,
I
B
GND
PARALLEL INPUTS
TUF/6600-1
Function Table
Inputs
Clear
Shlftl
Load
L
H
H
H
H
H
H
Clock
Outputs
Serial
Parallel
J
K
PO
P1
P2
P3
X
X
X
X
X
X
X
a
b
c
d
L
X
X
X
t
t
t
t
L
L
H
H
H
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
H
H
H
H
t
QA
QB
Qc
QD
QD
L
a
L
b
L
c
H
OAO
OAO
OBO
OAO
OAn
OAn
OAn
OCO
Oan
Oan
Oan
Oan
L
d
000
000
OCn
OCn
OCn
Oan
OCn
Ocn
OCn
OCn
L
H
OAn
H = High Level (Sleady State)
L = Low Level (Sleady Siale)
X
= Don't Care
t = Transition from low.to·hlgh level
= The level of steady state Input at PO, PI, P2, or P3 respectively.
OAO, OBO, OCO, 000 = The level of OA, OB, Oc, or 00, respectively before the Indicated steady state input conditions were established.
OAn, OBn, OCn = The level of OA, OB, Oc, respectively, before the mosl recent t transition of Ihe clock.
a, b, c, d,
4-255
d
•
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum RaUngs" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at th8Selimits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating CondiUons" table will define
the conditions for actual device operaUon.
If Military/Aerospace specified devices are required,
please contact the National semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
-65·C to + 150·C
Storage Temperature Range
Operating Free Air Temperature Range
- 55·C to + 125·C
Military
Commercial
O"Cto +70·C
Recommended Operating Conditions
Symbol
Vee
Supply Voltage
VIH
High Level Input Voltage
Vil
10H
10l
Low Level Input Voltage
High Level Output Current
Low Level Output Current
felK
tw
Clock Frequency (Note 5)
tsu
Min
4.5
Clear
25
Setup Time
(Note 5)
SIL
Data
36
18
Clear
36
Data Hold Time (Note 5)
Min
Nom
5.5
4.75
2
5
Units
Max
5.25
30
Free Air Operating Temperature
0
16
V
mA
mA
30
MHz
16
11
30
30
15
13
20
30
13
ns
13
-11
ns
0
0
10
-55
ns
10
125
V
V
0.8
-0.8
9.6
Clock
S/L Release Time (Notes 1 and 5)
Max
0.8
-0.48
Pulse Width
(Note 5)
tREl
TA
Nom
5
2
0
17
tH
Commercial
Military
Parameter
ns
70
0
·c
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
= Min,ll = -12 mA
VI
Input Clamp Voltage
Vee
VOH
High Level Output
Voltage
Vee = Min,lOH = Max
Vil = Max, VIH = Min
VOL
Low Level Output
Voltage
Input Current @ Max
Input Voltage
High Level Input Current
Vee = Min, 10L = Max
VIH = Min, Vil = Max
Vee = Max, VI = 5.5V
II
IIH
= Max,
= 2.4V
Vee
VI
los
Low Level Input Current
Vee = Max,
VI = 0.4V
Short Circuit
Output Current
Vee = Max
(Note 3)
Supply Current
Vee = Max
(Note 4)
Max
Units
-1.5
V
2.4
Input
CP Input
V
0.4
V
1
mA
40
Input
80
92
-1.6
CP Input
PE InpUt
MIL
-20
-3.2
-3.7
-80
COM
-18
-55
PE Input
III
Typ
(Note 2)
/LA
mA
mA
MIL
86
mA
COM
92
Note 1: RELEASE TIME: tRELEASE Is defined as the maximum time allowed for the logic level to be present at the logic input prior to the clock transition from low to
high in order for the fllp·flop(s) not to na.pond.
Note 2: All typical. are at Vee = SV, TA = 25"C.
Note 3: Not mona than one output should be shorted at a time.
Note 4: With all outputs open, SHIFT/LOAD grounded, and 4.SV applied to J, K, and data Inputs,lee is measured by applying momantary ground, then 4.SV to
CLEAR, and then to CLOCK.
Note 5: TA = 2S'C and Vee = SV.
lee
4·256
Switching Characteristics
at Vee
=
5V and TA
=
25°C (See Section 1 for Test Waveforms and Output Load)
Commercial
Military
Symbol
Parameter
From (Input)
To (Output)
RL
=
4000, CL
Min
=
15 pF
Max
30
RL
=
4000, CL = 15 pF
Min
Units
Max
fMAX
Maximum Clock Frequency
tpLH
Propagation Delay Time
Low to High Level Output
Clock to
Output
20
22
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clock to
Output
24
26
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clear to
Output
37
30
ns
4-257
30
MHz
9300
en
()
:T
CD
3
S»
0'
c
DM9300
iii'
Vee (16),
,
R1
4k
~R2
?1.5k
R4
2k
.,,
,
'R
1"::11 ,
,
A2B
1.Sk
1.Sk
R30
4k
I
'A P ",
R31
4k
,
A42
A44
1.Sk
4k
ce
iiJ
,P:'I (llt 'a ,
3
ClEAR (1)
..,.
(B)
GNDl,
'"
01
Q)
11_. II.n
U
"'
±
11U3)
K
±
II
:
-
(5)
P1
± II
:
-
(5)
P2
!=
-
J~)
TLIF/6600-2
co
Co)
IIiI Semiconductor
National
CI
.....
9301/DM9301
1-of-10 Decoders
General Description
Features
These BCD-to-decimal decoders consist of eight inverters
and ten 4-input NAND gates. The inverters are connected in
pairs to make BCD input data available for decoding by the
NAND gates. Full decoding of valid input logic ensures that
all outputs remain "OFF" for all invalid input conditions.
These circuits provide familiar TIL inputs and outputs which
are compatible for use with other TIL and DTL circuits. DC
noise margins are typically 1V and power dissipation is typically 125 mW. The diode-clamped, buffered inputs represent only one normalized Series 54/74 load.
•
•
•
•
•
Connection Diagram
Function Table
No.
Dual-In-Line Package
INPUTS
,
Vee
A
15
116
OUTPUTS
.
'0
B
14
1
13
2
12
4'
3
11
10
1
2
.
9
po
.--
e
Direct replacement for Signetics 8252
Diode-clamped inputs
All outputs are high for invalid BCD input conditions
Typical power dissipation 125 mW
Typical propagation delay 20 ns
0
INPUTS
,
3
,5
4
6
5
7
6
8
7
9
,
18
D C B A
0
1
2
3
4
5
6
7
8
9
L L
L L
L L
L L
L H
L
L
H
H
L
L
H
L
H
L
L
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
5
6
7
8
9
L
L
L
H
H
H
H
H
L
L
L
H
H
L
L
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
L
I
H
H
H
H
H
H
L
L
H
H
H
H
H
H
L
L
H
H
L
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
I
D
OUTPUTS
TLiF/6601-1
Order Number 9301DMQB, 9301FMQB or DM9301N
See NS Package Number J16A, N16E or W16A
4-259
Decimal Outputs
0
1
2
3
4
N
V
A
L
GND
BCD Inputs
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
5.5V
Operating Free Air Temperature Range
- 55·C to + 125·C
Military
Commercial
O·Cto 70·C
Storage Temperature Range
-65·C to
+ 150·C
Recommended Operating Conditions
Symbol
Military
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
10H
High Level Output Current
Low Level Output Current
TA
Free Air Operating Temperature
Symbol
Units
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
10L
Electrical Characteristics
Commercial
Min
O.B
O.B
V
-O.B
-O.B
mA
16
mA
70
·C
16
-55
V
V
2
125
0
over recommended operating free air temperature range (unless otherwise noted)
Parameter
Conditions
Min
Typ
(Note 1)
= Min, II = -12 mA
VI
Input Clamp Voltage
Vee
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
VIL = Max, VIH = Min
VOL
Low Level Output
Voltage
Vee = Min, 10L = Max
VIH = Min, VIL = Max
II
Input Current @ Max
Input Voltage
Vee
Max
Units
-1.5
V
V
2.4
0.4
V
1
mA
= Max, VI = 5.5V
IIH
High Level Input Current
Vee
p.A
Low Level Input Current
Vee
-1.6
mA
los
Short Circuit
Output Current
= Max, VI = 2.4V
= Max, VI = 0.4V
MIL
Vee = Max
40
IlL
-20
-70
(Note 2)
-20
-55
lee
Supply Current
Switching Characteristics
Symbol
Parameter
COM
Vee = Max
(Note 3)
MIL
44
COM
at Vee = 5V and TA
25
Propagation Delay Time
Low to High Level Output
tpHL
Propagation Delay Time
High to Low Level Output
mA
41
= 25·C (See Section 1 for Test Waveforms and Output Load)
Military
Conditions
Min
tpLH
mA
CL = 15pF
RL = 4000
Nola 1: All typical. are at Vee = 5V, TA = 25'C.
Note 2: Not more than one output should be shorted al a lime.
Note 3: Icc is measured with the outputs open and allinpuls grounded.
4-260
Commercial
Max
Min
Units
Max
35
30
ns
30
30
ns
<0
W
....o
Logic Diagram
9301
B
B
(3)
C
OUTPUT 5
(4)
C
OUTPUT 6
0
0
TLiF/6601-2
4-261
~National
~ Semiconductor
9308/DM9308 Dual 4·Bit Latch
General Description
The 9308 is a dual 4-bit D-type latch designed for general
purpose storage applications in digital systems. Each latch
contains both an active LOW Master Reset input an active
LOW Enable inputs. The 74116 is a pin for pin equivalent of
the 9308.
Connection Diagram
Logic Symbol
2 3
Dual-In-Line Package
MR
faa
fla
24
2
4
6
8 10
Vee
23
Q3b
22
D3b
DDa
QOa
4-BIT LATCH 1
D2b
Dla
Qlb
Qla
Dlb
4-BIT LATCH 2
D2a
QOb
Q2a
DDb
D3a
fib
vee = Pin24
Q3a
fOb
GND
GND
MRb
5 7
9 11
13
TL/F/10208-2
TL/F/10208-1
Order Number 9308DMQB, 9308FMQB or DM9308N
See NS Package Number J24A, N24A or W24C
Pin Names
Description
Doa-D3a}
DOb-D3b
'l:oa, 'l:1a, 'l:Ob, 'l:1b
MRa,MRb
AND Enable Inputs (Active LOW)
Master Reset Inputs (Active LOW)
~oa-~3a }
Parallel Latch Outputs
QOb-Q3b
17 19 21 23
Parallel Latch Inputs
4-262
= Pin 12
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
MIL
-55·Cto +125·C
COM
O·Cto +70·C
Storage Temperature Range
-65·Cto +150·C
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaran·
teed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Recommended Operating Conditions
Symbol
Military
Parameter
Commercial
Units
Min
Nom
Max
Min
Nom
Max
5
5.5
4.75
5
5.25
Vee
Supply Voltage
4.5
VIH
High Level Input
Voltage
2
VIL
Low Level Input
Voltage
10H
2
V
V
0.8
0.8
V
High Level Output
Current
-0.8
-0.8
mA
10L
Low Level Output
Current
16
16
mA
TA
Free Air Operating
Temperature
70
·C
Is (H)
Setup Time HIGH, On to En
6
10
ns
th (H)
Hold Time HIGH, On to En
4
-2.0
ns
Is(Ll
Setup Time LOW, On to En
10
12
ns
th (L)
Hold Time LOW, On to En
4
8
ns
!w(L)
En Pulse Width LOW
18
18
ns
tw(L)
MR Pulse Width LOW
18
18
ns
tree
Recovery Time, MR to En
10
8
ns
-55
125
0
Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
Conditions
VI
Input Clamp Voltage
Vee = Min,ll = -18 mA
VOH
High Level Output
Voltage
Vee = Min, 10H = Max,
VIL = Max, VIH = Min
VOL
Low Level Output
Voltage
Vee = Min, 10L = Max
VIH = Min, VIL = Max
II
Input Current @ Max
Input Voltage
IIH
Min
Typ
(Note 1)
Max
Units
-1.5
V
2.4
V
0.4
V
Vee = Max, VI = 5.5V
1
mA
High Level Input
Current
Vee = Max, VI = 2.4V
40
/LA
IlL
Low Level Input
Current
Vee = Max, VI = 0.4V
-1.6
mA
los
Short Circuit
Output Current
Vee = Max
(Note 2)
MIL
-20
-70
COM
-20
-57
Supply Current
Vee = Max (Note 3)
Icc
Nate 1: All typlcals are at Vee = 5V, TA = 25'C.
Nate 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Nate 3: IcC is measured with all outputs open and all inputs grounded.
100
4·263
mA
mA
Functional Description
Truth Table
Data can be entered into the latch when both of the enable
Inputs are LOW. As long as this logic condition exists, the
output of the latch will follow the input. If either of the enable
inputs goes HIGH, the data present in the latch at that time
is held in the latch and is no longer affected by data input.
The master reset overrides all other input conditions and
forces the outputs of all the latches LOW when a LOW signal is applied to the Master Reset input.
MR
EO
E1
D
On
Operation
H
H
H
L
L
L
L
L
H
L
H
X
L
H
Qn-1
Data Entry
Data Entry
Hold
H
H
L
H
H
X
L
H
X
X
X
X
Qn-1
Qn-1
L
Hold
Hold
Reset
an -1 = Previous Output State
an = Present Output State
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immatarial
Logic Diagram
01
DO
02
03
01
00
03
02
TL/F/10208-3
Switching Characteristics Vee = + 5.0V, TA = + 25'C (See Section 1 for test waveforms and output load.)
9308
Symbol
CL
RL
Parameter
Min
= 15pF
= 4000
Units
Max
tpLH
tpHL
Propagation Delay
En to Qn
30
22
ns
tpLH
tpHL
Propagation Delay
On to Qn
15
18
ns
tpHL
Propagation Delay
MRtoQn
22
ns
4-264
,------------------------------------------------------------------------, w
~
CI
~National
~
~ Semiconductor
9309/DM9309 Dual 4·Bit Data Selectors/Multiplexers
General Description
Features
These data selectors/multiplexers contain inverter/drivers
to supply full complementary, on-chip, binary decoded data
selection,
- Complementary outputs
_ Dual one-of-four data selectors
The 9309/DM9309 contains two separate 4-bit multiplexers
with complementary Y and Y outputs; however, the two sections have common address select inputs,
Connection Diagram
Dual-tn-Line Package
OUTPUTS
i
Y2
VCC
15
118
Y2
SELECT
INPUT
A
14
.
DATA INPUTS
f
2CO
13
2C1
12
\
2C2
11
2C3
10
9
I""""
2
.
Y1
Y1
OUTPUTS
4
5
1CO
1C1
3
SELECT
INPUT
B
\
.
8
7
1C2
1C3,
18
GND
DATA INPUTS
TUFI6602-1
Order Number 9309DMQB, 9309FMQB or DM9309N
See NS Package Number J16A, N16E or W16A
Function Table
Inputs
Select
Outputs
Data
B
A
CO
C1
C2
C3
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
H
X
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
L
H
Select Inputs A end B are common \0 both sections,
H
= High Level, L = Low Level, X = Don'\ Care,
4-265
y
V
L
H
L
H
L
H
L
H
H
L
H
L
H
L
H
L
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
Military
- 55'C to + 125'C
Commercial
O'Cto +70'C
Storage Temperature Range
- 65'C to + 150'C
Recommended Operating Conditions
Symbol
Commercial
Military
Parameter
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
0.8
0.8
V
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
10H
High Level Output Current
-0.8
-0.8
mA
10L
Low Level Output Current
16
16
mA
TA
Free Air Operating Temperature
70
'C
2
2
-55
125
V
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
VI
Input Clamp Voltage
Vee = Min, 11= -12 mA
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
VIL = Max, VIH = Min
VOL
Low Level Output
Voltage
Vee = Min, 10L = Max
VIH = Min, VIL = Max
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 5.5V
IIH
High Level Input
Current
Vee = Max, VI = .2.4V
IlL
Low Level Input
Current
Vee = Max, VI = O.4V
los
Short Circuit
Output Current
Vee = Max
(Note 2)
lee
Supply Current
Note 1: All typlcals are at Vcc
~
5V. TA
I
J
2.4
Typ
(Note 1)
Max
Units
-1.5
V
3.4
0.2
V
0.4
V
1
mA
40
/LA
-1.6
mA
MIL
-20
-70
COM
-30
-85
Vee = Max (Note 3)
~
Min
25'C.
NOIe 2: Not more than one output should be shorted at a time.
Nole 3: Icc is measured with the outputs open and all inputs at 4.5V.
4-266
27
44
mA
mA
Switching Characteristics at Vee =
Symbol
Parameter
5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
Military
From (Input)
To (Output)
Commercial
RL = 4000, CL = 15 pF
Min
Max
Units
Min
Max
tpLH
Propagation Delay Time
Low to High Level Output
Select
toY
29
40
ns
tpHL
Propagation Delay Time
High to Low Level Output
Select
toY
27
36
ns
tpLH
Propagation Delay Time
Low to High Level Output
Select
toY
21
24
ns
tpHL
Propagation Delay Time
High to Low Level Output
Select
toY
21
29
ns
tpLH
Propagation Delay Time
Low to High Level Output
Data
toY
20
27
ns
tpHL
Propagation Delay Time
High to Low Level Output
Data
toY
21
34
ns
tpLH
Propagation Delay Time
Low to High Level Output
Data
toY
12
21
ns
tpHL
Propagation Delay Time
High to Low Level Output
Data
toY
13
13
ns
Logic Diagram
9309
1C3
- }-
r-I
(7)
-
~
1C2 (6)
-
H--r
-
(9)
~
2C2(10)
-
2C1 (11)
SELECT (3)
INPUTB
1 ''''- )
Y2
(15)
OUTPUTS
Y2
- }-
2CO (12)
SELECT(13)
INPUT A
OUTPUTS
Y1
-
1CO (4)
2C3
""'}
(1)
-- }-
1C1 (5)
DATA
INPUTS
1
.~
t>- - i>-
-
TUF/6602-2
4-267
..- r--------------------------------------------------------------------------------,
~National
~ Semiconductor
9311/DM9311 4-Line to 16-Line
Decoders/Demultiplexers
General Description
Features
Each of these 4-line-to-16-line decoders utilizes TTL circuitry to decode four binary-coded inputs into one of sixteen
mutually exclusive outputs when both the strobe inputs, G1
and G2, are low. The demultiplexing function is performed
by using the 4 input lines to address the output line, passing
data from one of the strobe inputs with the other strobe
input low. When either strobe input is high, all outputs are
high. These demultiplexers are ideally suited for implementing high-performance memory decoders. All inputs are buffered and input clamping diodes are provided to minimize
transmission-line effects and thereby simplify system design.
• Pin for pin with popular DM54154174154
• Decodes 4 binary-coded inputs Into one of 16 mutually
exclusive outputs
• Performs the demultiplexing function by distributing data
from one input line to anyone of 16 outputs
• Input clamping diodes simplify system design
• High fan-out, low-impedance, totem-pole outputs
• Typical propagation delay 19 ns
• Typical power dissipation 170 mW
• Alternate Military/Aerospace device (9311) is available.
Contact a National Semiconductor Sales Office/Distributor for speCifications.
Connection Diagram
Dual-In-Llne Package
INPUTS
Vee 'A
T24
e
B
23
22
OUTPUTS
D
21
02
20
01' '15
19
18
14
17
13
18
12
15
11'
14
13
0-
2
,0
4
3
2
3
5
4
6
5,
7
6
8
7
9
8
10
9
11 _112
10, OND
OUTPUTS
Order Number 9311 DMQB, 9311 FMQB, DM9311J or DM9311N
See NS Package Number J24A, N24A or W24C
4-268
TUF/6604-1
Absolute Maximum Ratings
....
....
(Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "£fectrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
It Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Otflce/Dlstrlbutors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
- 55·C to + 125·C
Military
Commercial
O·Cto +70·C
Storage Temperature Range
-65·Cto + 150·C
Recommended Operating Conditions
Symbol
Military
Parameter
Vcc
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
Commercial
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
2
V
V
O.B
O.B
V
10H
High Level Output Current
-O.B
-O.B
mA
10L
Low Level Output Current
16
16
mA
TA
Free Air Operating Temperature
70
·c
-55
125
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
=
=
VI
Input Clamp Voltage
Vcc
VOH
High Level Output
Voltage
Vee = Min,IOH = Max
VIL = Max, VIH = Min
VOL
Low Level Output
Voltage
Vcc = Min, 10L = Max
VIH = Min, VIL = Max
II
Input Current @ Max
Input Voltage
Vcc
= Max, VI = 5.5V
IIH
High Level Input
Current
Vcc
=
Max, VI
=
2.4V
IlL
Low Level Input
Current
Vcc
=
Max, VI
=
O.4V
los
Short Circuit
Output Current
Vee = Max
(Note 2)
Supply Current
Vcc = Max
(Note 3)
Icc
Min, II
Min
Typ
(Note 1)
-12 mA
2.4
Max
Units
-1.5
V
V
3.4
0.25
0.4
V
1
mA
40
p.A
-1.6
mA
MIL
-20
-55
COM
-18
-57
MIL
34
49
COM
34
56
mA
mA
Nate 1: All typical. are at vcc = SV, TA = 2S'C.
Nate 2: Not more than one output should be shorted at a time.
Nate 3: Icc is measured with all inputs grounded and all outputs open.
•
4-269
.,...
.,...
Switching Characteristics at Vee = 5V and TA = 25"C (See Section 1 for Test Waveforms and Output Load)
Symbol
RL
From (Input)
To (Output)
Parameter
= 4000, CL = 15 pF
Min
Units
Max
tpLH
Propagation Delay Time
Low to High Level Output
Data to
Output
27
ns
tpHL
Propagation Delay Time
High to Low Level Output
Data to
Output
30
ns
tpLH
Propagation Delay Time
Low to High Level Output
Strobe to
Output
25
ns
tpHL
Propagation Delay Time
High to Low Level Output
Strobe to
Output
27
ns
Function Table
Inputs
Outputs
G1
G2
D
C
B
A
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
H
H
L
L
H
H
L
L
H
L
H
L
H
L
H
L
H
0
L
H
H
H
H
H
H
H
H
L
L
H
L
L
L
L
H
L
H
L
L
L
H
H
H
L
L
H
L
L
H
L
L
H
L
H
H
L
L
H
H
L
H
H
L
L
H
H
H
X
X
X
X
H
L
H
H
L
X
X
X
H
X
H
H
X
X
X
X
H
H = High Level, L = Low Level, X = Don't Care.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
.H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
4-270
L
.----------------------------------------------------------------------------,
Logic Diagram
DM9311
A
B
C
,....
D
A
'"""
~)~ o
--
H.
Gl
(2)
~
B
(18)
.......
2
G
(~
G2
)~ 3
~
(5)
4
C
23)
I
INPUTS
B( 22)
K-
(7)
6
B
(21)
I
(6)
5
B
I
c
~
A
A
-v
~-
C
c
~
i--
(8)
7
OUTPUTS
(9)
8
D
1-,"","-
(10)
D
20)
L
..... i - -
B
D
9
(11)
10
~ i--
C
,... ~
~
~
ii
'"""
.....
A
...
(13)
(14)
11
12
(15)
13
(16)
14
A
tat:
B
C
D
17)
15
TL/F/6604-2
II
4-271
.... ,----------------------------------------------------------------------------,
~
~
~National
~ Semiconductor
9312/DM9312 One of Eight Line
Data Selectors/Multiplexers
General Description
Features
These data selectors/multiplexers contain inverter/drivers
to supply full complementary, on-chip, binary decoded data
selection.
The 9312 is a single a-bit multiplexer with complementary
outputs and a strobe control. When the strobe is low, the
function is enabled. When a high logic level is applied to the
strobe, the output is forced to the logic zero state regardless
of the logic level of the data inputs.
•
•
•
•
Selects one-of-eight data sources
Performs parallel to serial conversion
Strobe controlled outputs
Complementary outputs
Connection Diagram
Dual-In-Llne Package
.
SELECT INPUTS
OUTPUTS
y
y'
16
14
2
.
DO
'e
13
DATA
A'
12
4
3
02
01
B
IN~
10
9
11
5
D4
D3
smOBE
6
7
05
D6
,
DATA INPUTS
TL/F/6605-1
Order Number 9312DMQB, 9312FMQB or DM9312N
See NS Package Number J16A, N16E or W16A
Function Table
Inputs
outputs
Select
C
B
A
G
X
X
X
H
L
L
L
L
L
L
L
H
H
H
H
L
L
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
Strobe
~
L
L
L
High Level, L
DO, 01 •.. 07
~
~
Low Level, X
~
Don't Care.
The level of the respective 0 input
4-272
y
y
L
00
01
02
03
04
05
06
07
00
01
02
03
04
05
06
07
H
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "£Iectrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
Military
- 55'C to + 125'C
Commercial
O'Cto +70'C
Storage Temperature Range
- 65'C to + 150'C
Recommended Operating Conditions
Symbol
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
Commercial
Military
Parameter
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
0.8
0.8
V
-0.8
rnA
16
rnA
70
'C
10H
High Level Output Current
-0.8
10L
Low Level Output Current
16
TA
Free Air Operating Temperature
-55
V
V
2
125
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
VI
Input Clamp Voltage
Vee = Min, 11= -12 rnA
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
VIL = Max, VIH = Min
VOL
Low Level Output
Voltage
Vee = Min, 10L = Max
VIH = Min, VIL = Max
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 5.5V
IIH
High Level Input
Current
Vee = Max, VI = 2.4V
IlL
Low Level Input
Current
Vee = Max, VI = 0.4V
los
Short Circuit
Output Current
Vee = Max
(Note 2)
lee
Supply Current
Nole 1: All typicals are at Vee
~
SV, TA
I
I
Min
2.4
Max
Units
-1.5
V
3.4
0.2
V
0.4
V
1
rnA
40
IJoA
-1.6
rnA
MIL
-20
-70
COM
-30
-85
Vee = Max, (Note 3)
~
Typ
(Note 1)
27
44
rnA
rnA
2S'C.
Nole 2: Not more than one output should be shorted at a time.
Nole 3: Icc is measured with the STROBE and DATA SELECT inputs 4.SV and all other inputs and outputs open.
II
4-273
Switching Characteristics at Vee = 5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
Military
Commercial
Parameter
From (Input)
To (Output)
tpLH
Propagation Delay Time
Low to High Level Output
Selectz
toY
34
33
ns
tpHL
Propagation Delay Time
High to Low Level Output
Select
toY
34
35
ns
tpLH
Propagation Delay Time
Low to High Level Output
Select
toY
24
28
ns
tpHL
Propagation Delay Time
High to Low Level Output
Select
toY
26
25
ns
tpLH
Propagation Delay Time
Low to High Level Output
Data
toY
24
23
ns
tpHL
Propagation Delay Time
High to Low Level Output
Data
toY
24
25
ns
tpLH
Propagation Delay Time
Low to High Level Output
Data
toY
14
13
ns
tpHL
Propagation Delay Time
High to Low Level Output
Data
toY
16
13
ns
tpLH
Propagation Delay Time
Low to High Level Output
Strobe
toY
30
33
ns
tpHL
Propagation Delay Time
High to Low Level Output
Strobe
toY
30
32
ns
tpLH
Propagation Delay Time
Low to High Level Output
Strobe
toY
20
19
ns
tpHL
Propagation Delay Time
High to Low Level Output
Strobe
toY
23
21
ns
Symbol
RL
Min
4-274
= 4000, CL = 15 pF
Max
Min
Units
Max
.---------------------------------------------------------------------,
Logic Diagram
~
Co)
....
I\)
9312
STROBE (10»
,~(1~r:::::;:===t=t-~
DO
01 (2)
02
.;..;.(3)---;ffiFr1~b
DATA
INPUTS
04(5)
05(6)
06 (7)
B
c
TLiF/6605-2
II
4-275
....~ r---------------------------------------------------~------------------__,
~ ~National
~ Semiconductor
9314/DM9314 Quad Latch
General Description
The '9314 is a multifunctional 4-bit latch designed for general purpose storage applications in high speed digital systems. All outputs have active pull-up circuitry to provide high
capacitance drive and to provide low impedance in both
logic states for good noise immunity.
Connection Diagram
Logic Symbol
Dual-In-Llne Package
E-
1
151-QO
00- 3
02- 6
141-51
131-Ql
12 -02
11 -53
03- 7
10 -Q3
GNO- 8
9-t.iR
01- "
52- 5
bib i bib i b
161-Vcc
50- 2
E DO 50 01 51 02 52 03 53
MR
QO
01
Q2
Q3
T
1~
1~
1~
,~
TL/F/979B-2
vee =
Pin 16
GND = PinB
TUF/97BB-1
Order Number 9314DMQB, 9314FMQB or DM9314N
See NS Package Number J16A, N16E or W16A
Pin Names
E
00-03
SO-S3
MR
00-03
Description
Enable Input (Active LOW)
Data Inputs
Set Inputs (Active LOW)
Master Reset Input (Active LOW)
Latch Outputs
4-276
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
Military
Commercial
-55'Cto + 125'C
O'Cto +70'C
Storage Temperature Range
- 65'C to + 150'C
Recommended Operating Conditions
Symbol
Military
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
10H
High Level Output Current
10L
Low Level Output Current
Commercial
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
2
V
V
0.8
0.8
V
-0.8
-0.8
mA
16
mA
70
·C
16
TA
Free Air Operating Temperature
-55
ts (H)
ts(L)
Setup Time HIGH or LOW
Onto!:
5.0
18
5.0
18
ns
th(H)
th (L)
Hold Time HIGH or LOW
Onto!:
0
5.0
0
5.0
ns
ns
125
0
ts(H)
Setup Time HIGH, On to Sn
8.0
8.0
th (L)
Hold Time LOW, On to Sn
8.0
8.0
ns
tw(L)
E Pulse Width LOW
18
18
ns
tw(L)
MR Pulse Width LOW
18
18
ns
tree
Recovery Time, MR to E
0
0
ns
Electrical Characteristics
Over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
=
= =
VI
Input Clamp Voltage
Vee
VOH
High Level Output Voltage
Vee = Min, 10H
VIL = Max
VOL
Low Level Output Voltage
Vee = Min, 10L
VIH = Min
II
Input Current @ Max
Input Voltage
Vee
=
Min, VI
=
5.5V
IIH
High Level Input Current
Vee
=
Max, VI
=
2.4V
Min,ll
=
Min
12 mA
Max
2.4
Max
Low Level Input Current
Vee
=
Shorl Circuit
Output Current
Max, VI
Vee = Max
(Note 2)
Supply Current
Vee
Icc
Nole 1: All typical. are at Vee = 5V. TA = 25'C.
Note 2: Not more than one output should be shorted at a lime.
=
Units
-1.5
V
V
0.4
V
1
mA
40
/LA
60
=
-1.6
0.4V
mA
-2.7
Oatalnputs
los
Max
3.4
0.2
Oata Inputs
IlL
Typ
(Note 1)
I
I
MIL
-20
-70
COM
-20
-70
55
Max
4-277
mA
mA
•
Switching Characteristics Vee =
Symbol
+5.0V, TA
=
+ 25°C (See Section 1 for waveforms and load configurations)
CL
Parameter
=
15pF
Min
Units
Max
tpLH
tpHL
Propagation Delay
'EtoO n
24
24
ns
tpLH
tpHL
Propagation Delay
On to On
12
24
ns
tpLH
Propagation Delay
MR to On
18
ns
tpHL
Propagation Delay
Sn to On
24
ns
Functional Description
Truth Table
The '9314 consists of four latches with a common active
LOW Enable input and active LOW Master Reset input.
When the Enable goes HIGH, data present in the latches is
stored and the state of the latch is no longer affected by the
Sn and On inputs. The Master Reset when activated overrides all other input conditions forcing all latch outputs LOW.
Each of the four latches can be operated in one of two
modes:
0-TYPE LATCH-For D-type operation the S input of a latch
is held LOW. While the common Enable is active the latch
output follows the 0 input. Information present at the latch
output is stored in the latch when the Enable goes HIGH.
SET/RESET LATCH-During set/reset operation when the
common Enable is LOW a latch is reset by a LOW on the 0
input, and can be set by a LOW on the S input if the 0 input
is HIGH. If both Sand 0 inputs are LOW, the 0 input will
dominate and the latch will be reset. When the Enable goes
HIGH, the latch remains in the last state prior to disablement. The two modes of latch operation are shown in the
Truth Table.
MR
E
D
S
Qn
H
H
H
L
L
H
L
H
L
L
o Mode
X
X
L
H
On-1
H
H
H
H
H
L
L
L
L
H
L
H
L
H
L
L
H
H
R/SMode
X
X
L
H
L
On-1
On-1
L
X
X
X
L
H ~ HIGH Voltage Level
L ~ LOW Voltage Level
x ~ Immaterial
an-I ~ Previous Output State
an ~ Present Output State
4-278
Operation
Reset
Logic Diagram
00
01
02
03
TUF/9788-3
•
4·279
~
.C')
a>
,------------------------------------------------------------------------,
~National
~ Semiconductor
9316/DM9316 Synchronous 4-Bit Counters
General Description
These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting
designs. The 9316 is a 4-bit binary counter. The carry output
is decoded by means of a NOR gate, thus preventing spikes
during the normal counting mode of operation. Synchronous
operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each
other when so instructed by the count-enables inputs and
internal gating. This mode of operating eliminates the output
counting spikes which are normally associated with asynchronous (ripple clock) counters. A buffered clock input triggers the four flip-flops on the rising (positive-going) edge of
the clock input waveform.
These counters are fully programmable; that is, the outputs
may be preset to either level. As presetting is synchronous,
setting up a low level at the load input disables the counter
and causes the outputs to agree with the setup data after
the next clock pulse regardless of the levels of the enable
input. Low-to-high transitions at the load input are perfectly
acceptable regardless of the logic levels on the clock or
enable inputs. The clear function is asynchronous and a low
level at the clear input sets of the flip-flop outputs low regardless of the levels of clock, load, or enable inputs.
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional
gating. Instrumental in accomplishing this function are two
count-enable inputs and a ripple carry output. Both countenable inputs (P and T) must be high to count, and input T is
fed-forward to enable the ripple carry output. The ripple carry output thus enabled will produce a high-level output pulse
with a duration approximately equal to the high-level portion
of the QA output. This high-level overflow ripple carry pulse
can be used to enable successive cascaded stages. Highto-low level transitions at the enable P or T inputs may occur
regardless of the logic level in the clock.
Features
•
•
•
•
•
•
•
Internal look-ahead for fast counting
Carry output for n-bit cascading
Synchronous counting
Load control line
Diode-clamped inputs
Typical clock frequency 35 MHz
Pin-for-pin replacements popular 54/74 counters
5416A17416A (binary)
• Alternate Military/Aerospace device (9316) is available.
Contact a National Semiconductor Sales Office/Distributor for specifications.
Connection Diagram
Dual-In-Llne Package
RIPPLE
CARRY
OUTPUT
Vee
116
OUTPUTS
QA
15
14
2
CLEAR CLOCK
13
3
A
Qc
Os
12
5
4
B
C
QD
11
6
D
ENABLE
T
LOAD
10
7
ENABLE
P
9
18
GND
DATA INPUTS
TUF/6606-1
Order Number 9316DMQB, 9316FMQB, DM9316J
DM9316W or DM9316N
See NS Package Number J16A, N16E or W16A
4-280
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
Military
-55'Cto +125'C
Commercial
O'Cto +70'C
Storage Temperature Range
- 65'C to + 150'C
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Recommended Operating Conditions
Symbol
Vcc
VIH
VIL
10H
10L
fCLK
tw
tsu
tH
TA
Parameter
Min
4.5
2
Supply Voltage
High Level Input Voltage
Low Level Input Voltage
High Level Output Current
Low Level Output Current
Clock Frequency (Note 6)
Pulse Width
Clock
(Note 6)
Clear
Setup Time
Data
(Note 6)
EnableP
Load
Clear
Any Hold Time (Notes 1 & 6)
Free Air Operating Temperature
Military
Nom
5
0
25
20
20
20
25
20
0
-55
Max
5.5
0.8
-0.8
16
25
125
Min
4.75
2
Commercial
Nom
Max
5.25
5
0.8
-0.8
16
25
0
25
20
20
20
25
20
0
0
Units
V
V
V
mA
mA
MHz
ns
ns
70
ns
'C
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
VI
VOH
VOL
II
Parameter
Input Clamp Voltage
High Level Output
Voltage
Low Level Output
Voltage
Input Current @ Max
Input Voltage
High Level Input
Current
Conditions
Min
Typ
(Note 2)
Vcc = Min, II = -12 mA
Vcc = Min, 10H = Max
VIL = Max, VIH = Min
Vcc = Min, 10L = Max
VIH = Min, VIL = Max
Vcc = Max, VI = 5.5V
2.4
Max
Units
-1.5
V
3.4
0.2
V
0.4
V
1
mA
Clock
80
80
EnableT
Other
40
-3.2
Low Level Input
Clock
Vcc = Max
IlL
Current
VI = 0.4V
-3.2
EnableT
-1.6
Other
-20
-57
Short Circuit
Vcc = Max
MIL
los
Output Current
(Note3)
-57
-18
COM
Supply Current with
59
85
MIL
Vcc = Max
ICCH
Outputs High
(Note4)
COM
59
94
Supply Current with
91
MIL
63
Vcc = Max
ICCL
Outputs Low
(Note 5)
63
101
COM
Note 1: The minimum HOLD time is as specified or as long as the CLOCK input lakes to rise from O.BV to 2V, whichever is longer.
Note 2: All typicals are at Vee = 5V, TA = 25'C.
Note 3: Not more than one output should be shorted at a time.
Note 4: ICCH is measured with the LOAD Input high, then again with the LOAD input low, wHh all other inputs high and all outputs open.
Note 5: leeL is measured with the CLOCK input high, then again with the CLOCK input low, with all other inputs low and all outputs open.
Note 6: TA = 25'C and Vcc = 5V.
IIH
Vcc = Max
VI = 2.4V
4-281
".A
".A
rnA
rnA
rnA
III
Switching Characteristics at Vee =
Symbol
Parameter
5V and TA = 25"C (See Section 1 for Test Waveforms and Output Load)
From (Input)
To (Output)
RL = 4000, CL = 15 pF
Min
Units
Max
fMAX
Maximum Clock Frequency
tplH
Propagation Delay Time
Low to High Level Output
Clock
toRC
25
27
ns
tpHl
Propagation Delay Time
High to Low Level Output
Clock
toRC
24
ns
tplH
Propagation Delay Time
Low to High Level Output
Clock
toO
20
ns
tpHl
Propagation Delay Time
High to Low Level Output
Clock
toO
23
ns
tplH
Propagation Delay Time
Low to High Level Output
Clock
toO
21
ns
tpHl
Propagation Delay Time
High to Low Level Output
Clock
toO
25
ns
tplH
Propagation Delay Time
Low to High Level Output
ENT
toRC
15
ns
tpHl
Propagation Delay Time
High to Low Level Output
ENT
toRC
16
ns
tpHl
Propagation Delay Time
High to Low Level Output
Clear
toO
36
ns
4·282
MHz
Logic Diagram
9316
~
.~
V
CLOCK
DATA A
CLEA
DATA
LOA
~
B (4)
D(9)
.~rfi>
0JCLEAR
Y
K
~~1
v
ENABLE P
ENABLE
~l
R (1)
(14)
Q ........ ~
CLOCK
L
I
(3)
K
-<
Q~~ QB
CLOCK
01J
CLEAR
Y
1-
P»
T(10)
(5)
DATAC
~
K
~1
(12)
QI---<~ QC
I-C ~CLOCK
oJ CLEAR
T
c::t:
(6)
DATAD
~~
~§¢D
I
K
Q
---4~ QD
CLOCK
0JCLEAR
I
rI.......L
"'
(15) RIPPLE
CARRY
OUTPUT
TLlF/6606-2
•
4·283
co
.,...
~
Timing Diagram
9316 Synchronous Binary Counters
Typical Clear, Preset, Count and Inhibit Sequences
CLEAR
LOAD
r--------------
INP
DAUTTAS (C:D
~=====:====:r=
=============
r----"1f-----.-------------L _____________ _
.-----1---..,.--------------
CLOCK
ENABLE P _ _ _-1-_4_1
ENABLE T _ _ _-1-_4_1
RIPPLEO~~~ ----t--t-""12;-1-;1":;'3"""7'14:--t.
15
0
1
2
---COUNT---- ---INHIBITCLEAR PRESET
TLlF/6606-3
Sequence:
(1) Clear outputs to zero.
(2) Preset to binary twelve.
(3) Count to thirteen, fourteen, fifteen, zero, one, and two.
(4) Inhibit
4·284
Parameter Measurement Information
Switching Time Waveforms
CLOCK
INPUT
OV
IpLH
(MEASURE AT IN+l)
VOH
OUTPUT
OA
--+-f-,.----Io_
VOL _ _
-+-.1
VOH---+-------+_
OUTPUT
Os
VOL----+-----------~---~~~-~-'
IpHL
(MEASURE AT IN+S)
OUTPUT
Oc
VOH
--+------~_
VOL---~----------~----·'-~~-~-'
VOH----~------------~_
OUTPUT
OD
RIPPLE
CARRY
OUTPUT
VOL---4-----------4----,-~~---J
VOH
-----+ ,----------'"
VOL _ _ _- '
TL/F/6606-4
Note A: The input pulses are supplied by a generalor having Ihe following characteristics: PRR ,; 1 MHz, duty cycle,; 50%, ZOUT '"
son,,, ,; 10 ns, If ,; 10 ns.
Vary PRR to measure fMAX'
Note B: Outputs 00 and carry are lested at In + 16 for 9316/8316, where In is Ihe bit lime when all outputs are low.
Note c: VREF
~
t.5V.
Ell
4·285
.... r-----------------------------------------------------------------------------,
~
I
Parameter Measurement Information (Continued)
Switching Time Waveforms
3.0 V ----------------'"'\
CLOCK INPUT
ov:::~--------;::::::$::;:::~~~~~~---------------
3.0 V
CLEAR
INPUT
OV
LOAD
INPUT
DATA INPUTS
A.B,C,ANDD
Q OUTPUTS
9316
3.0 V
-~:::::::t:!!£~~ r-I.4~~-------
ov----~--~~------f
VOH
-----t-_
VOL----~--r~~------+_-----+~
ENABLEPOR
ENABLET
3.0 v ----+------I-------L-.---.4...-!~
ov----~----~----~~-'
VOH----+-----4----~~~~--4---------~~·,.~~
CARRY
VOL----~----~------~----~----------J
TL/F/S60S-5
Note k The inpul pulses are supplied bygeneralors having Ihe following characteristics: PRR
Note B: Enable P and Enable T setup times are measured alln + 16 for 8316/9316.
Note C: VREF
= I.SV.
4-286
~
1 MHz. duty cycle
~
50%. loUT:::: SOO.t,
~
10 ns. If
~
10 ns.
r---------------------------------------------------------------------------~
co
Co)
-"
~National
00
~ Semiconductor
DM9318 Priority Encoders
General Description
Features
These TTL encoders feature priority decoding of the input
data to ensure that only the highest-order data line is encoded. All inputs are buffered to represent one normalized
Series 54/74 load. The DM9318 and DM8318 encode eight
data lines to three-line (4-2-1) binary (octal). Cascading circuitry (enable input El and enable output EO) has been provided to allow octal expansion without the need for external
circuitry. For all types, data inputs and outputs are active at
the low logic level.
• Pin for pin with popular DM5414817 4148
• Encodes 8 data lines to 3-line binary (octal)
• Applications include:
N-bit encoding
Code converters and generators
• Typical data delay 10 ns
• Typical power dissipation 190 mW
Connection Diagram
Dual-In-Line Package
.
OUTPUTS
EO
15
1
3
14
2
2
.
7
El,
AO
10
9
Is
7
6
A2
INPUTS
OUTPUT
0
11
5
4
6
1
12
13
3
5
,4
,_______I_NP
.....U'-T_S_____."
GS
A1
.
GND
OUTPUTS
TUF/6607-1
Order Number DM9318J, DM9318N or DM9318W
See NS Package Number J16A, N16E or W16A
Function Table
Outputs
Inputs
E1
D
1
2
3
4
5
6
7
A2
A1
AD
GS
EO
H
L
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
L
H
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
H
H
L
L
H
H
L
L
H
H
H
H
L
H
L
H
L
H
L
H
H
H
L
L
L
L
L
L
L
L
H
L
H
H
H
H
H
H
H
H
L
L
H
L
H
H
L
H
H
H
L
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
H
H = High Logic Level, L = Low Logic Level, X = Don't Care
4-287
•
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Operating Free Air Temperature Range
Military
-55·Cto + 125·C
Commercial
O"Cto +70·C
Storage Temperature Range
-65·Cto + 150"C
Recommended Operating Conditions
Symbol
Military
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
10H
High Level Output Current
Commercial
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
0.8
0.8
V
-0.8
-0.8
mA
16
mA
70
·C
2
10L
Low Level Output Current
TA
Free Air Operating Temperature
Units
Min
2
V
16
-55
125
0
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
=
=
VI
Input Clamp Voltage
Vee
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
VIL = Max, VIH = Min
VOL
Low Level Output
Voltage
Vee = Min, 10L = Max
VIH = Min, VIL = Max
II
Input Current @ Max
Input Voltage
Vee
IIH
High Level Input
Current
Vee = Max
VI = 2.4V
Low Level Input
Current
Vee = Max
VI = O.4V
Short Circuit
Output Current
Vee = Max
(Note 2)
leel
Supply Current
Condition 1
Vee
=
Max, (Note 3)
lee2
Supply Current
Condition 2
Vee
=
Max, (Note 4)
IlL
los
=
Min, II
Max, VI
Min
Typ
(Note 1)
-12rnA
=
Max
Units
-1.5
V
2.4
V
5.5V
0.4
V
1
rnA
o Input
40
Others
80
o Input
-1.6
Others
-3.2
MIL
-35
-85
COM
-35
-85
Note 1: All typical. are al Vee = 5V. TA = 25'C.
Nole 2: Not more than one output should be shorted al a time.
Note 3: ICCI is measured with all inputs and outputs open.
Note 4: 1CC2 Is measured with Inputs 7 and EI grounded and outputs open.
4-288
/LA
rnA
rnA
35
55
rnA
40
60
mA
CD
Switching Characteristics at Vee =
Symbol
Parameter
5V and TA
=
25'C (See Section 1 for Test Waveforms and Output Load)
From (Input)
To (Output)
o
tpLH
Propagation Delay Time
Low to High Level Output
thru 7 to
ABCD In Phase
tpHL
Propagation Delay Time
High to Low Level Output
thru 7 to
ABCD In Phase
tpLH
Propagation Delay Time
Low to High Level Output
thru 7 to
ABCD Out of Phase
tpHL
Propagation Delay Time
High to Low Level Output
thru 7 to
ABCD Out of Phase
tpLH
Propagation Delay Time
Low to High Level Output
othru 7 to EO
Propagation Delay Time
High to Low Level Output
othru 7to EO
Propagation Delay Time
Low to High Level Output
othru 7 to GS
Propagation Delay Time
High to Low Level Output
othru7to GS
tpLH
Propagation Delay Time
Low to High Level Output
tpHL
RL
=
Min
4000, CL
=
15 pF
Units
Max
15
ns
14
ns
19
ns
19
ns
9
ns
21
ns
27
ns
21
ns
EI toAO, 1,2
In Phase
15
ns
Propagation Delay Time
High to Low Level Output
EI toAO,1, 2
In Phase
15
ns
tpLH
Propagation Delay Time
Low to High Level Output
EltoGS
In Phase
12
ns
tpHL
Propagation Delay Time
High to Low Level Output
EI to GS
In Phase
15
ns
tpLH
Propagation Delay Time
Low to High Level Output
Elto EO
In Phase
15
ns
tpHL
Propagation Delay Time
High to Low Level Output
Ello EO
In Phase
26
ns
tpHL
tpLH
tpHL
o
o
o
Out 01 Phase
Out 01 Phase
In Phase
In Phase
4-289
W
.....
CCI
....
~~------------------------------------------------------------I
~
Logic Diagram
9318
1(O~(1~°fr)~~~~~~~~~~~F=P--r~~
11 >-___--,
(15)
EO
-)~+t+t---q
(12)
2
(13)
3 -~tt-----t~
INPUTS
(1)
4
--4itt-.q
(2)
5 ---4>tt-.q
6 (3)
(4)
7 - -.....------,
--~===~O
(5)
"
EI----t>-
t::I
4·296
TLlF/660B-2
,-------------------------------------------------------------------------,
~National
~
!i
~ Semiconductor
9324/DM9324 5-Bit Comparator
General Description
The 9324 expandable comparators provide comparison between two 5-bit words and give three outputs-"Iess than",
"greater than" and "equal to". A HIGH on the active LOW
Enable Input forces all three outputs LOW.
Connection Diagram
Dual-In-Une Package
E- 1
16 -Vee
AB
BO- 3
14 -A=B
Bl- 4
B2- 5
13 -AO
12 -AI
83- 6
11-42
84- 7
10 -A3
GND- 8
9 -A4
TUF/9792-1
Order Number 9324DMQB, 9324FMQB, or DM9324N
See NS Package Number J16A, N16E or W16A
Pin Names
E
AO-A4
BO-B4
AB
A=B
DescrIption
Enable Input (Active LOW)
Word A Parallel Inputs
Word B Parallel Inputs
A Less than B Output (Active HIGH)
A Greater than B Output (Active HIGH)
A Equal to B Output (Active HIGH)
•
4-297
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safely of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
Input Voltage
Operating Free Air Temperature Range
Military
Commercial
Storage Temperature Range
7V
5.5V
- 55'C to + 125'C
O'Cto +70'C
- 65'C to + 150'C
Recommended Operating Conditions
Symbol
Military
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
10H
High Level Output Current
10L
Low Level Output Current
TA
Free Air Operating Temperature
Commercial
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
0.8
0.8
V
-0.8
-0.8
mA
16
mA
70
'C
16
-55
V
V
2
125
0
Electrical Characteristics Over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 1)
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vee = Min, II = -12 mA
VOH
High Level Output Voltage
Vee = Min, 10H = Max
VIL = Max
VOL
Low Level Output Voltage
Vee = Min, 10L = Max
VIH = Min
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 5.5V
IIH
High Level Input Current
Vee = Max, VI = 2.4V
80
/LA
IlL
Low Level Input Current
Vee = Max, VI = O.4V
-3.2
mA
los
Short Circuit
Output Current
Vee = Max
(Note 2)
Supply Current
Vee = Max
Icc
I
I
2.4
3.4
0.2
V
0.4
V
1
mA
MIL
-20
-70
COM
-20
-70
81
typicals are at Vee = 5V, TA = 25'C.
Note 2: Not more than one output should be shorted at a time.
Note 1: All
4-298
mA
mA
Switching Characteristics
Vee = +5.0V, TA = +25'C (See Section 1 for waveforms and load configurations)
Symbol
CL = 15pF
Parameter
Min
Units
Max
tpLH
tpHL
Propagation Delay
EtoA = 8
14
14
ns
tpLH
tpHL
Propagation Delay
An,8n toA> 8
25
22
ns
tpLH
tpHL
Propagation Delay
An, 8 n toA < 8
26
21
ns
tpLH
tpHL
Propagation Delay
An,8n toA=B
30
32
ns
Functional Description
Truth Table
The '24 5-bit comparators use combinational circuitry to directly generate "A greater than 8" and "A less than 8"
outputs. As evident from the logic diagram, these outputs
are generated in only three gate delays. The "A equals 8"
output is generated in one additional gate delay by decoding
the" A neither less than nor greater than 8" condition with a
NOR gate. All three outputs are activated by the active LOW
Enable Input (E).
Tying the A > 8 output from one device into an A input on
another device and the A < 8 output into the corresponding
8 input permits easy expansion.
Inputs
Outputs
E
An
Bn
AB
A=B
H
L
L
L
X
X
L
L
L
H
L
L
H
L
L
H
L
L
Word A = Word B
Word A > Word 8
Word 8 > Word A
H = HIGH Voltage Level
L = LOW Voltage Level
x = Immaterial
The A4 and 84 inputs are the most significant inputs and
AO, 80 the least significant. Thus if A4 is HIGH and 84 is
LOW, the A > 8 output will be HIGH regardless of all other
inputs except E.
Logic Symbol
13 12 11 10 9
3
4
5
6
7
I I I I I I I I I I
AD AI A2 A3 A4 80 81 82 83 84
1-(1 E
A B
A B
A=B
I
I
I
15
2
14
vee = Pin 16
GND
= Pin6
4-299
TLlF/9792-2
Logic Diagram
)0_--'<8
)0....- - . > 8
TUF/9792-3
4·300
r---------------------------------------------------------------------------~ U)
~
N
~National
m
~ Semiconductor
9328/DM9328 Dual 8-Bit Shift Register
General Description
The '9328 is a high speed serial storage element providing
16 bits of storage in the form of two B-bit registers. The
multifunctional capability of this device is provided by several features: 1) additional gating is provided at the input to
both shift registers so that the input is easily multiplexed
between two sources; 2) the clock of each register may be
provided separately or together;- 3) both the true and complementary outputs are provided from each B-blt register,
and both registers may be master cleared from a common
input.
Connection Diagram
Logic Symbol
13
Dual-In-Llne Package
Mil
[
.... 07
'"
ti
!il
'"
16
2
15
3
14
Vee
11
12
14
10---'---"""
9
S
01
4
13
07 ill
S ~
VI
5
12
01
DO
6
11
DO
CP
7
10
GND
8
9
"I !:l
15
465
-
CP
CP
COM
3
7-.--._~
2
TL/F/9793-1
Order Number 9328DMOB, 9328FMOB or DM932BN
See NS Package Number J16A, N16E or W16A
TL/F/9793-2
vee = Pin16
GND = PinS
Pin Names
S
00,01
CP
MR
Q7
Q7
Description
Data Select Input
Data Inputs
Clock Pulse Input (Active HIGH)
Common (Pin 9)
Separate (Pins 7 and 10)
Master Reset Input (Active LOW)
Last Stage Output
Complementary Output
4-301
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guarenteed The device should not be operated at thesellmlls. The
parametric values defined In the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
Military
- 55'C to + 125'C
Commercial
O'Cto +70'C
Storage Temperature Range
-65'C to + 150'C
Recommended Operating Conditions
Symbol
Military
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
IOH
High Level Output Current
Commercial
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
2
V
V
0.8
0.8
V
-0.4
-0.4
mA
16
mA
70
'c
IOL
Low Level Output Current
TA
Free Air Operating Temperature
16
ts(H}
ts (L)
Setup Time HIGH or LOW
On toCP
20
20
20
20
ns
th(H}
th (L)
Hold Time HIGH or LOW
On toCP
0
0
0
0
ns
Iw(H}
Iw (L)
Clock Pulse Width HIGH
or LOW
25
25
25
25
ns
-55
125
0
Iw (L)
MR Pulse Width with CP HIGH
30
30
ns
Iw(L}
MR Pulse Width with CP LOW
40
40
ns
tree
Recovery Time MR to CP
33
33
ns
Electrical Characteristics
Over Recommended Operating Free Air Temperature Range (Unless Otherwise Noted)
Symbol
Parameter
Conditions
VI
Input Clamp Voltage
Vee = Min, 11= -12 mA
VOH
High Level Output Voltage
Vee = Min, IOH = Max
VIL = Max
VOL
Low Level Output Voltage
Vee = Min, IOL = Max
VIH = Min
II
Input Current @ Max Input Voltage
IIH
High Level Input Current
IlL
Low Level Input Current
Min
2.4
Typ
(Note I)
Max
Units
-1.5
V
3.4
0.2
V
0.4
V
Vee = Max, VI = 5.5V
1
mA
Vee = Max, VI = 2.4V
MR, On Inputs
40
CP Inputs
60
S Inputs
80
CP (COM) Inputs
120
Vee = Max, VI = O.4V
MR, Dn Inputs
-1.6
CP Inputs
-2.4
S Inputs
-3.2
CP (COM) Input
-4.8
4-302
/LA
mA
Electrical Characteristics
Over Recommended Operating Free Air Temperature Range (Unless Otherwise Noted) (Continued)
Symbol
Parameter
Short Circuit
Output Current
los
Conditions
Vee = Max
(Note 2)
I
I
Typ
(Note 1)
Min
Max
MIL
-20
-70
COMM
-20
-70
Supply Current
Vee = Max
lee
Nole 1: All typlcals are al Vce = SV. TA = 2S'C.
Nole 2: Not more than one output should be shorted at a time.
Units
mA
77
mA
Switching Characteristics
Vee
= + 5.0V, T A = + 25'C (See Section
Symbol
1 for waveforms and load configurations)
CL
RL
Parameter
=
=
15pF
4000
Min
Units
Max
f max
Maximum Shift Right Frequency
tpLH
tpHL
Propagation Delay
CPtoQ70rQ7
20
35
ns
tpHL
Propagation Delay MR to Q7
50
ns
20
MHz
Functional Description
The two B-bit shift registers have a common clock input (pin
9) and separate clock inputs (pins 10 and 7). The clocking
of each register is controlled by the OR function of the separate and the common clock input. Each register is composed of eight clocked RS master/slave flip-flops and a
number of gates. The clock OR gate drives the eight clock
inputs of the flip-flops in parallel. When the two clock inputs
(the separate and the common) to the OR gate are LOW.
the slave latches are steady. but data can enter the master
latches via the Rand S input. During the first LOW-to-HIGH
transition of either, or both simultaneously, of the two clock
inputs, the data inputs (R and S) are inhibited so that a later
change in input data will not affect the master; then the now
trapped information in the master is transferred to the slave.
When the transfer is complete, both the master and the
slave are steady as long as either or both clock inputs remain HIGH. During the HIGH-to-LOW transition of the last
remaining HIGH clock input, the transfer path from master
to slave is inhibited first, leaving the slave steady in its present state. The data inputs (R and S) are enabled so that new
data can enter the master. Either of the clock inputs can be
used as clock inhibit inputs by applying a logiC HIGH signal.
Each B-bit shift register has a 2-input multiplexer in front of
the serial data input. The two data inputs DO and 01 are
controlled by the data select input (S) following the Boolean
expression:
Serial data in: So
=
SDO
+ SOl
An asynchronous master reset is provided which, when activated by a LOW logic level, will clear all 16 stages independently of any other input signal.
Shift Select Table
OUTPUT
INPUTS
S
DO
01
Q7 (tn + 8)
L
L
H
H
L
H
X
X
X
X
L
H
L
H
L
H
H = HIGH Voltage Level
L = LOW Voltage Level
x = Immaterial
n + 8 = indicates state alter eight clock pulse
4-303
Logic Diagram
DI--.r"""
DO----'"-J"""........
DI--..r-........
DO----'"-....----
s
~,------------~~~~----~----~~----~------~------~----~~----~------~--~
TL/F/9793-3
4·304
r-------------------------------------------------------------------------,~
Co)
Co)
~National
.Do
~ Semiconductor
9334/DM9334 8-Bit Addressable Latch
General Description
The DM9334 is a high speed a-bit Addressable Latch designed for general purpose storage applications in digital
systems. It is a multifunctional device capable of storing single line data in eight addressable latches, and being a oneof-eight decoder and demultiplexer with active level high
outputs. The device also incorporates an active level low
common clear for resetting all latches, as well as an active
level low enable.
The DM9334 has four modes of operation which are shown
in the mode selection table. In the addressable latch mode,
data on the data line (D) is written into the addressed latch.
The addressed latch will follow the data input with all nonaddressed latches remaining in their previous states. In the
memory mode, all latches remain in their previous state and
are unaffected by the data or address inputs.
In the one-of-eight decoding or demultiplexing mode, the
addressed output will follow the state of the D input with all
other inputs in the low state. In the clear mode all outputs
are low and unaffected by the address and data inputs.
When operating the device as an addressable latch, changing more than one bit of the address could impose a transient wrong address. Therefore, this should only be done
while in the memory mode.
The function tables summarize the operation of the product.
Features
•
•
•
•
•
•
•
Common clear
Easily expandable
Random (addressable) data entry
Serial to parallel capability
a bits of storage/ output of each bit available
Active high demultiplexing/decoding capability
Alternate Military/Aerospace device (9334) is available.
Contact a National Semiconductor Sales Office/Distributor for speCifications.
Connection Diagram
Dual·ln·L1ne Package
Vee
116
1
AO
E
15
2
A1
D0706
14
3
A2
12
13
4
00
5
01
11
6
02
05
10
7
03
04
9
18
GND
TL/F/6609-1
Order Number 9334DMQB, 9334FMQB, DM9334J or DM9334N
See NS Package Number J 16A, N 16E or W16A
II
4-305
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operatIon.
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
Military
- 55'C to + 125'C
0' to +70'C
Commercial
Storage Temperature Range
- 65'C to + 150'C
Recommended Operating Conditions
Symbol
Military
Parameter
Vee
Supply Voltage
V,H
High Level Input Voltage
V,L
Low Level Input Voltage
Commercial
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
0.6
0.8
V
2
V
2
10H
High Level Output Current
-0.8
-0.8
mA
10L
Low Level Output Current
16
16
mA
tw
ENABLE Pulse Width
(Fig. 1) (Note 4)
tsu
Setup Time
(Note 4)
tH
TA
Hold Time
(Note 4)
19
13
19
13
Data 1 (Fig. 4)
20
13
20
13
Data 0 (Fig. 4)
20
14
20
14
Address (Fig. 6)
(Note 1)
10
5
10
5
Data 1 (Fig. 4)
0
-10
0
-10
Data 0 (Fig. 4)
0
-13
0
-13
-55
Free Air Operating Temperature
125
ns
ns
ns
0
70
'C
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
=
=
Min
Typ
(Note 2)
Max
Units
-1.5
V
V,
Input Clamp Voltage
Vee
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
V,L = Max, V,H = Min
VOL
Low Level Output
Voltage
Vee = Min, 10L = Max
V,H = Min, V,L = Max
I,
Input Current @ Max
Input Voltage
Vee
I'H
High Level Input
Current
Vee = Max
V, = 2.4V
Elnput
60
Others
40
Low Level Input
Current
Vee = Max
V, = 0.4V
E Input
-2.4
Others
-1.6
Short Circuit
Output Current
Vee = Max
(Note 3)
I,L
los
=
Min, I,
Max, V,
-12 mA
=
2.4
3.6
0.2
5.5V
V
0.4
V
1
mA
MIL
-30
-100
COM
-30
-100
/LA
mA
mA
Supply Current
B6
mA
56
Vee = Max
Icc
Note 1: The ADDRESS setup time is the time before the negative ENABLE transition that the ADDRESS must be stable so that the correct latch Is addressed
without affecting the other latches.
Note 2: All typicals are at Vee = SV, TA = 2S'C.
Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 4: TA = 2S'C and Vee = SV.
4-306
Switching Characteristics at Vee = 5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
From (Input)
RL = 4000, CL = 15 pF
Symbol
Parameter
Units
To (Output)
Max
Min
tpLH
Propagation Delay Time
Low to High Level Output
Enable to
Output, Fig. 1
28
ns
tpHL
Propagation Delay Time
High to Low Level Output
Enable to
Output, Fig. 1
27
ns
tpLH
Propagation Delay Time
Low to High Level Output
Data to
Output, Fig. 2
35
ns
tpHL
Propagation Delay Time
High to Low Level Output
Data to
Output, Fig. 2
28
ns
tpLH
Propagation Delay Time
Low to High Level Output
Address to
Output, Fig. 3
35
ns
tpHL
Propagation Delay Time
High to Low Level Output
Address to
Output, Fig. 3
35
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clear to
Output, Fig. 5
31
ns
function Tables
E
C
Mode
L
H
L
H
H
L
H
L
Addressable Latch
Memory
Active High Eight
Channel Demultiplexer
Clear
Inputs
Present Output States
Mode
C
E
D
AD
A1
A2
QD
Q1
Q2
Q3
Q4
Q5
QS
Q7
L
H
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
L
L
H
H
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
0
0
0
0
0
0
0
0
0
0
0
0
0
L
L
H
H
H
H
L
H
H
X
X
X
X
QN-l
H
H
H
H
L
L
L
L
L
H
L
H
L
L
H
H
L
L
L
L
L
L
L
L
L
H
QN-l
QN-l
•
0
.
0
0
0
0
0
H
H
L
L
L
H
H
H
L
L
L
L
H
Memory
QN-l
QN-l
L
H
QN-l
QN-l
QN-l
QN-l
QN-l
0
0
0
H
H
L
0
0
Demultiplex
0
L
0
•
Clear
Addressable
Latch
0
H
H
QN-l
QN-l
QN-l
QN-l
= Don'l Care Condition
= Low Voltage Level
H = High Voltage Level
x
L
QN-1 = Previous Oulpul Stale
4-307
L
H
..
C")
~
Logic Diagram
9334
TL/F/S609-2
Switching Time Waveforms
D
Q
TLlF/S609-4
Other Conditions: E
= L, C = H, A = Stable
Figure 2
TLlF/S609-3
Other Conditions: C
= H, A = Stable
Figure 1
D
At
At
Q
Ot
TLlF/S609-6
TL/F/6609-5
Other Conditions: E = L, C
Other CondHions: C
= L, 0 = H
= H, A = Stable
Figure 4
Figure 3
TL/F/6609-8
TL/F/6609-7
Other CondRons: E = H
Other Conditions: C
=H
FIgure 5
Figure 6
Note: The shaded areas Indicate when the Inputs are permitted to change for predictable output performance.
4·308
r----------------------------------------------------------------------------, U)
c.:I
c.:I
~National
00
~ Semiconductor
9338/DM9338 8-Bit Multiple Port Register
General Description
The DM933B is an B-bit multiple port register designed for
high speed random access memory applications where the
ability to simultaneously read and write is desirable_ A common use would be as a register bank in a three address
computer. Data can be written into anyone of the eight bits
and read from any two of the eight bits simultaneously.
Connection Diagrams
Dual-In-Llne Package
80-1
'-/
81- 2
82- 3
16 !-Vcc
15 !-AO
ZB- 4
14 I-A1
13 I-A2
Zc- 5
C2- 6
12 !-DA
11 !-CP
C1- 7
10 !-SLE
GND- 8
91-CO
TLlF/9794-1
Order Number 9338DMQB, 9338FMQB or DM9338N
See NS Package Number J16A, N16E or W16A
Pin Names
AO-A2
DA
80-82
CO-C2
CP
SLE
Za
Zc
Description
Write Address Inputs
Data Input
8 Read Address Inputs
C Read Address Inputs
Clock Pulse Input (Active Rising Edge)
Slave Enable Input (Active LOW)
8 Output
COutput
•
4-309
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Input Voltage
5.5V
Operating Free Air Temperature Range
Military
-55'Cto +125'C
Commercial
O'Cto +70'C
Storage Temperature Range
-65'C to + 150'C
Recommended Operating Conditions
Symbol
Military
Parameter
Vee
Supply Voltage
VIH
High level Input Voltage
VIL
low level Input Voltage
10H
High level Output Current
Commercial
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
2
2
V
V
0.8
0.8
V
-0.8
-0.8
mA
16
mA
70
'C
10L
low level Output Current
TA
Free Air Operating Temperature
ts(H)
ts (l)
Setup Time HIGH or lOW
DA toCP
20
12
20
12
ns
th (H)
th (l)
Hold Time HIGH or lOW
DA toCP
0
-8.0
0
-8.0
ns
ts (H)
ts (l)
Setup Time HIGH or lOW
An toCP
10
10
10
10
ns
th (H)
th (l)
Hold Time HIGH or lOW
An toCP
0
0
0
0
ns
tw(H)
tw (l)
CP Pulse Width HIGH or lOW
23
13
23
13
ns
16
-55
125
0
Electrical Characteristics
Over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 1)
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vee = Min, 11= -12 mA
VOH
High level Output Voltage
Vee = Min, 10H = Max
VIL = Max
VOL
low level Output Voltage
Vee = Min, 10L = Max
VIH = Min
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 5.5V
IIH
High level Input Current
Vee = Max, VI = 2.4V
27
p,A
IlL
low level Input Current
Vee = Max, VI = O.4V
-1.1
mA
los
Short Circuit
Output Current
Vee = Max
(Note 2)
I
I
Supply Current
Vee = Max
are at Vee = 5V, TA = 25'C.
Note 2: Not more than one output should be shorted at a time.
2.4
3.4
0.2
V
0.4
V
1
mA
Mil
-10
-70
COM
-10
-70
135
Icc
Note 1: Aillypicals
4-310
mA
mA
Switching Characteristics
Vee
= + 5.0V, TA = + 25'C (See Section
1 for waveforms and load configurations)
CL
Symbol
=
15pF
9338 (MIL)
Parameter
Min
DM9338 (COM)
Max
Min
Max
Units
tpLH
tpHL
Propagation Delay
Bn orCn to Zn
40
35
13
18
40
35
ns
tpLH
tpHL
Propagation Delay
DA toZ n
45
50
25
25
45
50
ns
tPLH
tpHL
Propagation Delay
CPtoZ n
35
30
18
13
35
30
ns
Functional Description
The 9338 8-bit multiple port register can be considered a 1bit slice of eight high speed working registers. Data can be
written into anyone and read from any two of the eight
locations simultaneously. Master/slave operation eliminates
all race problems associated with simultaneous read/write
activity from the same location. When the clock input (CP) is
LOW data applied to the data input line (DA) enters the
selected master. This selection is accomplished by coding
the three write input select lines (AO-A2) appropriately.
Data is stored synchronously with the rising edge of the
clock pulse.
data during the read operation. The state of each slave is
determined by the state of the master selected by its associated set of read address inputs.
The method of parallel expansion is shown in Figure a. One
9338 is needed for each bit of the required word length. The
read and write input lines should be connected in common
on all of the devices. This register configuration provides
two words of n-bits each at one time, where n devices are
connected in parallel.
logic Symbol
The information for each of the two slaved (output) latches
is selected by two sets of read address inputs (BO-B2 and
CO-C2). The information enters the slave while the clock is
HIGH and is stored while the clock is LOW. If Slave Enable
is LOW (SLE), the slave latches are continuously enabled.
The signals are available on the output pins (ZB and Zc).
The input bit selection and the two output bit selections can
be accomplished independently or simultaneously. The data
flows into the device, is demultiplexed according to the state
of the write address lines and is clocked into the selected
latch. The eight latches function as masters and store the
input data. The two output latches are slaves and hold the
'i Y I Iii I i
It
AO AI A2 BO BI B2 CO CI C2
12- DA
11- CP
10-(l SLE
Ib
Ie
1
!
TL/F/9794-2
vee = Pin 16
GND = PinB
01
DA
CLOCK
AINPUT {
SELECT
}.,
}.,
D. CP SLE
AD
L - AI
' - - A2
9338
BD 8-BIT
BI MULTIPLE
PORT
r - - B2 REGISTER
CD
CI
C2 IB Ie
D. CP SLE
A
-
-
'--
~~
B
'---- A2
r--
-
-
9338
BD B-BIT
BI MULTIPLE
B2 PORT
REGISTER
CD
CI
C2 Is Ie
...
BOUTPUT {
SELECT
C OUTPUT {
SELECT
J
B. b
B WORD
FIGURE a. Parallel Expansion
4·311
Lb
C WORD
TUF/9794-4
=
~
Logic Diagram
A0-i:>Ot-------'
90
91-1;»t--..1
B2-t,;;>01r--..1
co-t,;;>01r----'
Cl-1;»p----..1
C2-C~r----.J
Ze
TUF/9794-3
4·312
r-------------------------------------------------------------------------,
~
~National
~ Semiconductor
9348
12-lnput Parity Checker/Generator
General Description
The 9348 is a 12-input parity checker/generator generating
odd and even parity outputs. It can be used in high speed
error detection applications.
Connection Diagram
Logic Symbol
Dual-In-Line Package
15- 1
16 ~Vcc
16- 2
15 ~14
17- 3
14 H3
18- 4
13
19- 5
12~11
r y y YY
Iii iii I
14
10 11
12 13
15 16 17 18 19 110 111
~12
110- 6
11
~IO
111- 7
10
~PE
GND- 8
~
Co)
PO
PE
1
1~
TLlF/9795-2
9 ~PO
Vcc = Pin 16
GND = Pin 8
TLlF/9795-1
Order Number 9348DMOB or 9348FMOB
See NS Package Number J16A or W16A
Pin Names
Description
10-111
PO
Parity Inputs
Odd Parity Output
Even Parity Output
PE
4-313
Absolute Maximum Ratings
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and speclflcatlons_
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
Military
- 55'C to
Storage Temperature Range
-65'Cto
+ 125'C
+ 150'C
Recommended Operating Conditions
Symbol
9348
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
10H
High Level Output Current
Units
Min
Nom
Max
4.5
5
5.5
V
2
10L
Low Level Output Current
TA
Free Air Operating Temperature
V
-55
0.8
V
-0.8
rnA
16
rnA
125
·c
Electrical Characteristics
Over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
VI
Input Clamp Voltage
Vee
VOH
Vee
Min. 10H
VOL
Low Level Output Voltage
II
Input Current @ Max
Input Voltage
=
=
Vee =
Vee =
Min. II
High Level Output Voltage
IIH
High Level Input Current
=
Vee =
Vee =
Max. VI
IlL
Low Level Input Current
los
Short Circuit Output Current
Vee
Supply Current
Vee
Icc
Note 1: All typlcals are atVce = 5V. TA = 2S'C.
Note 2: Not more than one output should be shorted at a time.
=
=
-12 rnA
= Max. VIL =
Min. 10L = Max. VIH =
Max. VI = 5.5V
Max. VI
Typ
(Note 1)
Min
Conditions
=
=
Max
Max
Units
-1.5
V
0.4
V
1
rnA
2.4
V
Min
2.4V
80
IJ.A
0.4V
-3.2
rnA
-70
rnA
82
rnA
-20
Max (Note 2)
Max
Switching Characteristics
Vee
= + 5.0V. T A = + 25'C (See Section
Symbol
Parameter
1 for waveforms and load configuration)
CL
RL
Conditions
Min
=
=
15pF
4000
Units
Max
tpLH
tpHL
Propagation Delay
14 to PO
12. 13. 17. 18 = GND; Other
Inputs (except 14) HIGH
46
42
ns
tpLH
tpHL
Propagation Delay
14 to PE
12.13.17.18 = GND; Other
Inputs (except 14) HIGH
51
48
ns
tpLH
Propagation Delay
13 to PO
17 = HIGH; Other Inputs
(except 13) = GND
27
ns
tpHL
Propagation Delay
14 to PO
All Inputs (except 14)
25
ns
4-314
=
GND
Functional Description
The 9348 is a 12-input parity generator. It provides odd and even parity for up to 12 data bits. The Even Parity output (PE) will be
HIGH if an even number of logic ones are present on the inputs. The Odd Parity output (PO) will be HIGH if an odd number of
logic ones are present on the inputs. The logic equations for the outputs are shown below.
PO = 10 Ell 11 Ell 12 Ell 13 Ell 14 Ell 15 Ell 16 Ell 17 Ell 18 Ell 19 Ell 110 Ell 111
PE = 10 Ell 11 Ell 12 Ell 13 Ell 14 Ell 15 Ell 16 Ell 17 Ell 18 Ell 19 Ell 110 Ell 111
Note: Less through delay is encountered from the 10, 11, 12 and 13 inputs than 14 thru 111 inputs. Therefore, if some signals Bre slower than others, the slower
signals should be applied to these four inputs for maximum speed.
Truth Table
Inputs
Outputs
10-111
H
PO
PE
All Twelve
AnyOne
Any Two
Any Three
Inputs LOW
Inputs HIGH
Inputs HIGH
Inputs HIGH
L
H
L
H
H
L
H
L
Any Four
Any Five
Any Six
Any Seven
Inputs HIGH
Inputs HIGH
Inputs HIGH
Inputs HIGH
L
H
L
H
H
L
H
L
Any Eight
Any Nine
Any Ten
Any Eleven
Any Twelve
Inputs HIGH
Inputs HIGH
Inputs HIGH
Inputs HIGH
Inputs HIGH
L
H
L
H
L
H
L
H
L
H
= HIGH Voltage Level
L = LOW Voltage Level
Logic Diagram
,::~~
19~~
18~
f')o-oI>-PO
:~~
-
-Lo[>-PE
15~~
14~
:~~
III
11~~
IO~
TL/F/9795-3
4-315
m ,---------------------------------------------------------------------,
~
G)
~ National
~ Semiconductor
DM9368 7-Segment Decoder/Driver/Latch
with Constant Current Source Outputs
General Description
The DM9368 is a 7-segment decoder driver incorporating
input latches and constant current output circuits to drive
common cathode type LED displays directly.
Connection Diagram
Dual-In-Llne Package
'-/
16
-Vee
-f
ROi-s
15
14
13
12
A3- 6
II'-c
AO- 7
10 rd
GND- 8
91-8
Al- 1
A2- 2
i:E- 3
RBO- 4
-g
-a
-b
TL/F/9796-1
Order Number DM9368N
See NS Package Number N16E
Pin Name
AO-A3
RBO
RBI
a-g
LE
Description
Address (Data) Inputs
Ripple Blanking Output (Active Low)
Ripple Blanking Input (Active Low)
Segment Drivers-Outputs
Latch Enable Input (Active Low)
4-316
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
Operating Free Air Temperature Range
Storage Temperature Range
5.5V
O'Cto +70'C
-65'Cto +150'C
Recommended Operating Conditions
Symbol
DM9368
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
Vil
Low Level Input Voltage
10H
High Level Output Current
10l
Low Level Output Current
Units
Min
Nom
Max
4.75
5
5.25
V
0.8
V
16
mA
70
'C
2
V
-80
/LA
TA
Free Air Operating Temperature
0
t 8 (H)
Setup Time High
An to LE
30
ns
th(H)
Hold Time HIGH
An to LE
0
ns
!s(L)
Setup Time LOW
An to LE
20
ns
th(L)
Hold Time LOW
An to LE
0
ns
twILl
LE Pulse Width LOW
45
10H
Segment Output HIGH Current
-16
10l
Segment Output LOW Current
-250
ns
-22
mA
250
/LA
Electrical Characteristics
Over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
= Min,ll = -12 mA
= Max,
VI
Input Clamp Voltage
Vee
VOH
High Level
Output Voltage
Vee = Min, 10H
Vil = Max
VOL
Low Level
Output Voltage
Vee = Min, 10l
VIH = Min
II
Input Current @ Max
Input Voltage
Vee
Min
2.4
= Max,
Max
Units
-1.5
V
V
3.4
0.2
= Max, VI = 5.5V
= Max, VI = 2.4V
= Max, VI = 0.4V
Vee = Max
Typ
(Note 1)
0.4
V
1
mA
IIH
High Level Input Current
Vee
40
/LA
III
Low Level Input Current
Vee
-1.6
mA
los
Short Circuit
Output Current
(Note 2)
-57
mA
67
mA
Icc
Supply Current
Vee = Max, Outputs Open,
Data & Latch Inputs = OV
Note 1: Alltyplcals are at Vee = SV, TA = 2S'C.
Nola 2: Not more than one output should be shorted at a time.
4-317
-18
i§en
Switching Characteristics
Yee = 5.0Y, TA = 25°C (See Section 1 for Waveforms and Load Configuations)
Symbol
CL
RL
Parameter
= 15pF
= 1000
Min
Units
Max
tpLH
tpHL
Propagation Delay
An toa-g
40
70
ns
tpLH
tpHL
Propagation Delay
LEto a-g
70
90
ns
Functional Description
The '68 is a 7-segment decoder driver designed to drive 7segment common cathode LED displays. The '68 drives any
common cathode LED display rated at a nominal 20 mA at
1.7Y per segment without need for current limiting resistors.
This device accepts a 4-bit binary code and produces output
drive to the appropriate segments of the 7-segment display.
It has a hexadecimal decode format which produces numerIc codes "0" thru "9" and alpha codes "A" through "F"
using upper and lower case fonts.
Latches on the four data inputs are controlled by an active
LOW latch enable LE. When the LE is LOW, the state of the
outputs is determined by the input data. When the LE goes
HIGH, the last data present at the inputs is stored in the
latches and the outputs remain stable. The LE pulse width
necessary to accept and store data is typically 30 ns which
allows data to be strobed into the '68 at normal TTL speeds.
This feature means that data can be routed directly from
high speed counters and frequency dividers into the display
without slowing down the system clock or providing intermediate data storage.
Another feature of the '68 is that the unit loading on the data
inputs is very low (-100 IJ.A Max) when the latch enable is
HIGH. This allows '68s to be driven from an MOS device in
multiplex mode without the need for drivers on the data
lines.
The '68 also has provision for automatic blanking of the
leading and/or trailing edge zeros in a multidigit decimal
number, resulting In an easily readable decimal display conforming to normal writing practice. In an eight digit mixed
integer fraction decimal representation, using the automatic
blanking capability, 0060.0300 would be displayed as 60.03.
Leading edge zero suppression is obtained by connecting
the Ripple Blanking Output (RBO) of a decoder to the Ripple Blanking Input (RBI) of the next lower stage device. The
most significant decoder stage should have the RBI input
grounded; and since suppression of the least significant integer zero in a number is not usually desired, the RBI input
of this decoder stage should be left open. A similar procedure for the fractional part of a display will provide automatic
suppression of trailing edge zeros. The RBO terminal of the
decoder can be OR-tied with a modulating signal via an isolating buffer to achieve pulse duration intensity modulation.
A suitable signal can be generated for this purpose by forming a variable frequency multivibrator with a cross coupled
pair of TTL or DTL gates.
Logic Symbol
Iliiit
AD A1 A2 A3 LE RBI
Vee
= Pin 16
GND = PIN 8
TL/F/9796-2
4-318
Truth Table
INPUTS
BINARY
STATE
IT RBi
•
-
OUTPUTS
A3 A2 A1 AO
a
c
b
d
•
f
9 RBO
0
0
1
H
L L
L H
L X
X
L
L
L
X
L
L
L
X
L
L
L
X
L
L
H
--STABLE----L L L L L L L
H H H H H H L
L H H L L L L
2
3
4
5
L
L
L
L
X
X
X
X
L
L
L
L
L
L
H
H
H
H
L
L
L
H
L
H
H
H
L
H
H
H
H
L
L
H
H
H
H
H
L
H
H
L
L
L
L
L
H
H
6
7
8
10
L
L
L
L
L
X
X
X
X
X
L
L
H
H
H
H H
H H
L L
L L
L H
L
H
L
H
L
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
L
L
11
12
13
14
15
L
L
L
L
L
X
X
X
X
X
H
H
H
H
H
L H
H L
H L
H H
H H
H
L
H
L
H
L
H
L
H
H
L
L
H
L
L
H
L
H
L
L
X
X
X
X
X
X
L
L
L
9
X
DISPLAY
H
L
H
H
STABLE
BLANK
H
H
H
H
H
H
H
H
,:'
H
L
H
L
H
H H
L L
H H
H H
H H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
L
H
H
H
L
H
H
H
H
H
H
H
H
L
L
L
L L··
,-,
:
::
'-I
::'
:;.
TL/F /9796-4
8
'::
I::
I:.
'd
E
;:
BLANK
TL/F/9796-B
"'The RBI will blank the display only if a binary zero is stored in the latches .
... "'The RBO used as an input overrides all other input conditions.
H
~
HIGH Voltage Level
L ~ LOW Voltage Level
X = Immaterial
Logic Diagram
r--------------------------,I
AO---+---------------,
I
I
I
I
I
I
I
a
I
b
L-~LA~T~CH~________~----~----------------~I~
~---------A1
A2
A3
---------------~
1-0F-16
DECODER
16
SEGMENT
ENCODER
7
OUTPUT
DEVICES
d
LATCH
LATCH
LATCH
IT
RBi
~-------------------RBO
TL/F/9796-3
4-319
•
CD ,---------------------------------------------------------------------------------,
!
Numerical Designations
o
234
5
7
8
10
11
12
13
14
15
I01/12131'"1IS161118191Rlb1Cld1EIFI
TUF/9796-5
Parallel Data Display System with Ripply Blanking
Common Cathode LED Display
~--~--------------~~------------------------------,
4-BlTm
4-BlTm
4-BlTm
DECADE OR
DECADE OR
DECADE OR
BINARY
COUNltR
BINARY
COUNTER
BINARY
COUNTER
S:~~------r-r-~~~-------+-+-+-+~----------------------~~~-i-'
9368
9368
I I
9368
OTHER
DIGITS
8 8
I I
LEAST SIGNIFICANT
DIGIT
8
MOST SIGNIFICANT
DIGIT
TLlF/9796-6
4-320
(I)
Co)
en
co
Display Demultiplexing System with Ripple Blanking
Common Cathode LED Display
~-----------------------------------------+:/
STROBE INPUT
OR DIGIT ADDRESS
(SEE NOTE 5)
BCD MULTPLEX
I
DATA
/+------,
+-----------+!I I
I I
I
~
AO AI A2 A3 EL RBt
7-SEGMENT DECODER
DRIVER/LATCH
RBOa b c d •
f g
YII
II
~
9.
AO At A2 A3
RBO
7-SEGMENT DECODER
DRIVER/LATCH
RBOe b c d • f 9
~II
1
I
III
foI&
I J
-"
1..
LEAST SIGNIFICANT
DIGIT
-
"
"1..
-""
MOST SIGNIFICANT
DIGIT
TL/F/9796-7
Note: Digit address data must be non·overlapping. Standard TTL decoders like the 9301, 9311, 7442 or 74155 must be strobed, sincathe address decoding
glitches could cause erroneous data to be slrobed into the latches.
4·321
~National
~ Semiconductor
DM9370 7-Segment Decoder/Driver/Latch
with Open-Collector Outputs
General Description
The DM9370 is a 7-segment decoder driver incorporating
input latches and output circuits to directly drive incandescent displays. It can also be used to drive common anode
LED displays in either a multiplexed mode or directly with
the aid of external current limiting resistors.
Connection Diagram
Dual-in-Line Package
'-/
16
-Vee
A2- 2
15
-i
u:- 3
RBO- 4
14
13
-9
-&:
R8i-s
12
-ii
A3- 6
AO- 7
l1-e
10 :"'(j
GND- 8
91-8
Al- 1
TL/F/9797-1
Order Number DM9370N
See NS Package Number N16E
Pin Names
AO-A3
LE
RBI
RBO
a-g
Description
Address Inputs
Latch Enable Input (Active LOW)
Ripple Blanking Input (Active LOW)
Ripple Blanking as Output (Active LOW)
as Input (Active LOW)
Segment Outputs (Active LOW)
4-322
Absolute Maximum Ratings
(Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The devic should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
Input Voltage
Operating Free Air Temperature Range
Commercial
Storage Temperature Range
7V
5.5V
O'Cto +70'C
- 65'C to + 150'C
Recommended Operating Conditions
Symbol
DM9370
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
Units
Min
Nom
Max
4.75
5
5.25
V
2
V
VIL
Low Level Input Voltage
O.B
V
10H
High Level Output Current
-BO
/LA
3.2
mA
70
'C
10L
Low Level Output Current
TA
Free Air Operating Temperature
t 9 (H)
ts (L)
Setup Time HIGH or LOW
An to LE
30
20
ns
th(H)
th (L)
Hold Time HIGH or LOW
An to LE
0
0
ns
twILl
LE Pulse Width LOW
45
ns
0
Electrical Characteristics
Over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
VI
Input Clamp Voltage
Vee = Min, 11= -12 mA
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
VIL = Max
VOL
Low Level Output
Voltage
Vee = Min, IOL = Max
VIH = Min
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 5.5V
IIH
High Level Input Current
IlL
los
VOH
Output HIGH Voltage
RBO
Vee = Min, 10H -80 /LA
VOL
Output LOW Voltage
RBO
10L = 3.2mA
Min
2.4
Typ
(Note 1)
Max
Units
-1.5
V
V
3.4
0.4
V
1
mA
Vee = Max, VI = 2.4V
40
p.A
Low Level Input Current
Vee = Max, VI = 0.4V
-1.6
mA
Short Circuit
Output Current
Vee = Max
(Note 2)
-70
mA
- -
a-g
10L = 25mA
I
DM74
I Vee = M'In
I
0.2
-20
V
2.4
0.4
V
0.4
10H
Output HIGH Current, a-g
250
/LA
Icc
Power Supply Current
Vee = Max
105
/LA
A1, A2, A3, LE = GND
Vee = Max, Outputs Open
105
Ao, A1, A2, LE = GND
Vee = Max, Outputs Open
94
4-323
mA
•
Ie
~
Switching Characteristics
Vee = +5.0V, TA = +25°C (See Section 1 for waveforms and load configurations)
Syml:lol
CL
RL
Parameter
= 15PF
= soon
Min
Units
Max
tpLH
tpHL
Propagation Delay
Antoa-g
75
50
ns
tpLH
tpHL
Propagation Delay
LEtoa-g
90
70
ns
Functional Description
The '70 has active LOW outputs capable of sinking in excess of 25 mA which allows It to drive a wide variety of
7-segment Incandescent displays dlreclly. It may also be
used to drive common anode LED displays, multiplexed or
directly with the aid of suitable current limiting resistors. This
device accepts a 4-blt binary code and produces output
drive to the appropriate segments of the 7-segment display.
It has a hexadecimal decode format which produces numerIc codes "0" through "9" and alpha codes "A" through "F"
using upper and lower case fonts.
Latches on the four data Inputs are controlled by an active
LOW latch enable LE. When the LE Is LOW, the state of the
outputs Is determined by the Input data. When the LE goes
HIGH, the last data present at the Inputs Is stored In the
latches and the outputs remain stable. The LE pulse width
necessary to accept and store data is typically 30 ns which
allows data to be strobed Into the '70 at normal TTL speeds.
This feature means that data can be routed direclly from
high speed counters and frequency dividers Into the display
without slowing down the system clock or providing intermediate data storage.
The latch/decoder combination Is a'sir'!'lple system which
drives Incandescent displays with multiplexed data Inputs
from MOS time clocks, DVMs, calculator chips, etc. Data
Inputs are multiplexed while the displays are In static mode.
This lowers component and insertion costs since several
circuits-seven diodes per display, strobe drivers, a sepa-
rate display voltage source, and clock failure detect circuits-traditionally found in incandescent multiplexed display systems are eliminated. It also allows low strobing rates
to be used without display flicker.
Another '70 feature is the reduced loading on the data inputs when the Latch Enable is HIGH (only 10 p.A typ). This
allows many '70s to be driven from a MOS device in multiplex mode without the need for drivers on the data lines.
The '70 also provides automatic blanking of the leading
and/or trailing-edge zeroes in a multidigit decimal number,
resulting in an easily readable decimal display conforming to
normal writing practice. In an B-digit mixed integer fraction
decimal representation, using the automatic blanking capability, 0060.0300 would be displayed as 60.03. Leadlngedge zero suppression Is obtained by connecting the Ripple
Blanking Output (RBO) of a decoder to the Ripple Blanking
Input (RBI of the next lower stage device. The most significant decoder stage should have the RBI Input grounded;
and since suppression of the least significant Integer zero in
a number is not usually desired, the RBI input of this decoder stage should be left open. A similar procedure for the
fractional part of a display will provide automatic suppression of trailing-edge zeroes. The RBO terminal of the decoder can be OR-tied with a modulating signal via an Isolating
buffer to achieve pulse duration Intensity modulation. A suitable signal can be generated for this purpose by forming a
variable frequency multlvlbrator with a cross coupled pair of
TTL or DTL gates.
Logic Symbol
II i i bb
AD At A2 A3 LE RBI
RBDa bed e f 9
!!!!!!!~
Vee = Pin 16
GND = PlnB
4-324
TL/F/9797-2
~----------------------------------------------------------------------------------~ U)
(0)
~
Truth Table
INPUTS
BINARY
STATE
--0
OUTPUTS
[ERiii A3 A2 A1 AO
•
0
1
H
L L
L H
L X
X X
L L
L L
L L
2
3
4
5
L
L
L
L
X
X
X
X
6
7
8
9
10
L
L
L
L
L
11
12
13
14
15
L
L
L
L
L
X
X X
-c
ii b
- i
d •
Ii
RBO
DISPLAY
X
L
L
L
X
L
L
H
-STABLEH H H H H H H
L L L L L L H
H L L H H H H
H
L
STABLE
BLANK
H
H
(I
L
L
L
L
L H
L H
H L
H L
L
H
L
H
L
L
H
L
L
L
L
H
H
L
L
L
L L
L H
H H
L H
H
H
L
L
L
L
L
L
H
H
H
H
<
X
X
X
X
X
L
L
H
H
H
H
H
L
L
L
H
H
L
L
H
L
H
L
H
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
H
H
L
H
L
H
L
L
H
L
L
L
L
H
L
L
L
H
H
H
H
H
oS
X
X
X
X
X
H
H
H
H
H
L
H
H
H
H
H H
L L
L H
H L
H H
H
L
H
L
L
H
H
L
H
H
L
H
L
H
H
L L
L L
L L
L L
H L
L
L
H
L
L
L H
H H
L H
L H
L H
X
H H
X X
X
H H H
H H L"
:
,
::
'1
S
,-,
"
'1
:::
.,=.
,'-
.,
Tl/F/9797-4
E
F
BLANK
Tl/F/9797-6
'The RBI will blank the display only if binary zero is stored in the latches.
··RBO used as an input overdrives all other input conditions.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Numerical Designation
o
2
3
4
5
6
7
8
9
10
11
12
13
14
15
IDI/12131l-11S16111BI91RlblCIdiEIFI
TLlF/9797-5
•
4-325
Logic Diagram
r--------------------------~
AO-......
-------,
---4---------+-.. 1-0r-16
DECODER
'--..:::;=~_ _ _.....
~----------
---------------~
16
SEGMEHT
ENCODER
7
OUTPUT
DEVICES
Al-----I--r------:-::::-:------~
LArCH
A2----~~~--------~~----------~~
LATCH
u----~_4--------~~----------~
LATCH
~------------------------------------RIPPLE
~~---------------mffi
iiiii
4-329
TL/F/l0210-3
t!
~
Truth Table
Binary
State
Inputs
Outputs
-
LE
RBI
A3
A2
A1
AO
a
Ii
c
•
1
H
L
L
L
L
H
X
X
L
L
L
X
L
L
L
X
L
L
L
X
L
L
H
H
L
H
H
L
L
H
L
L
2
3
4
6
L
L
L
L
X
X
X
X
L
L
L
L
L
L
H
H
H
H
L
L
L
H
L
H
L
L
H
L
L
L
L
H
H
L
L
L
L
L
H
L
6
7
8
9
10
L
L
L
L
L
X
X
X
X
X
L
L
H
H
H
H
H
L
L
L
H
H
L
L
H
L
H
L
H
L
L
L
L
L
H
H
L
L
L
H
L
L
L
L
H
11
12
13
14
16
L
L
L
L
L
X
X
X
X
X
H
H
H
H
H
L
H
H
H
H
H
L
L
H
H
H
L
H
L
H
L
H
H
L
H
H
L
H
L
H
X
X
X
X
X
X
X
H
H
0
0
Display
e
f
STABLE
H
H
L
L
H
H
H
L
H
H
H
H
H
L
H
H
Stable
Blank
L
H
H
H
H
H
L
L
L
L
L
L
H
H
H
H
2
3
4
6
L
H
L
L
H
L
H
L
H
H
L
H
L
L
H
L
H
L
L
L
H
H
H
H
H
6
7
8
9
H
L
H
H
H
L
H
L
H
H
L
L
L
L
H
L
L
L
L
H
L
L
H
L
H
H
H
H
H
H
BLANK
H
H
H
H
H
L"
BLANK
d
g
RBO
--.
0
1
fOb
'Dc
d
TL/F/l02tO-4
E
H
L
P
'The 'ABi will blank the display only If a binary zero Is stored In the latches.
"FIBO used as an input overrides all other Input condHions.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Numerical Designations
o
2
3
4
5
6
7
8
9
10
11
12
13
14
101 112131l-11516111B191-IEIHIL IPI
4-330
15
I
TUF110210-5
Applications
It is possible with common anode 7-segment LED displays
and constant current sink decoder drivers to save substantial amounts of power by carefully choosing operating points
on display supply voltage. First, examine the power used in
the normal display driving method where the display and
decoder driver are both operated from a + 5.0V regulated
supply (Vee = Vs).
can maintain approximately 15 mA with as little as 0.5V
across the output device. By using a separate power source
(Vs, Figure C) for the LEOs, which is set to the LED VF plus
the offset voltage of the driver, as much as 280 mW can be
saved per digit. i.e.,
Vs = VF (Max) + Vollset
= 2.0V + O.5V
= 2.5V
PT = 2.5V x 14 mA (from Figure B) x 7
= 245 mW
The power dissipated by the LED and the driver outputs is
(Vee x Iseg x n Segments). The total power dissipated with a
15 mA LED displaying an eight (8) would be:
These figures show that using a separate supply to drive the
LEOs can offer significant display power savings. In battery
powered equipment, two rechargeable nickle-cadmium cells
in series would be sufficient to drive the display, while four
such cells would be needed to operate the logic units.
PTOT = 5.0V x 15 mA x 7
= 525 mW
Of this 525 mW, the power actually required to drive the
LED is dependent on the VF drop of each segment. Most
GaAsP LEDs exhibit either a 1.7V or a 3.4V forward voltage
drop. Therefore, the required total power for seven segments would be:
Another method to save power is to apply intensity modulation to the displays (Figure DJ. It is well known that LED
displays are more efficient when operated in pulse mode.
There are two reasons: one, the quantum efficiency of the
LED material is better; secondly the eye tends to peak detect. Typically a 20% off duty cycle to displays (GaAsP) will
produce the same brightness as operating under dc conditions.
P(1.7) = 1.7V x 15 mA x 7
= 178.5 mW
P(3.4) = 3.4V x 15 mA x 7
= 357 mW
The remaining power is dissipated by the driver outputs
which are maintaining the 15 mA constant current required
by the LEOs. Most of this power is wasted, since the driver
Vs
COMMON
ANODE
LED
vee
..,
"
"
CURRENT
FLOW
~
TUF/l0210-11
FIGURE C_ Separate Supply for LED Displays
4-331
~
G)
Applications (Continued)
LEAST SIGNIFICANT DECADE
AI A2 A4 AB
- - - ----------
Cl C2 C4 C8
- - -
---------- - - - ---------.
INTENSITY
: MODULATION ~_--4-4-4-4---_--4-4-4-4----1--4-4-4-4-----,
I
INPUT
I
MOST SIGNIFICANT DECADE
Dl D2 D4 DB
Bl B2 B4 B8
I
I
LATCH
ENABLE
INVERTER CAN BE
IMPLEMENTED WITH
ONE TRANSISTOR AND
A RESISTOR FOR
EACH DECADE
1 1
I I
I I
I I
TO 7-SEGMENT DISPLAYS
TL/F110210-6
All Inverters are DTL 9936 or Open Colleclor TIL 7405
FIGURE D. Intensity Control by RBO Pulse Duty Cycle
Therefore, the removal of a large portion of the filtered dc
current requirement (display power) substantially reduces
the transformer loading.
There are two basic approaches. First (Figure E) is the direct full wave rectified unregulated supply to power the displays. The '74 decoder driver constant current feature maintains the specified segment current after the LED diode
drop and 0.5V saturation voltage has been reached
("'2.2V). Care must be exercised not to exceed the '74
power ratings and the maximum voltage that the decoder
driver sees in both the "on" and "off" modes.
The second approach (Figure F) uses a 3-terminal voltage
regulator such as the 7805 to provide dc pulsed power to
the display with the peak dc voltage limited to +5.0V. This
approach allows easier system thermal management by
heat sinking the regulator rather than the display or display
drivers. When this power source is used with an intensity
modulation scheme or with a multiplexed display system,
the frequencies must be chosen such that they do not beat
with the 120 Hz full wave rectified power frequency.
Low Power, Low Cost Display Power Sources-In small
line operated systems using TTL/MSI and LED or incandes·
cent displays, a significant portion of the total dc power is
consumed to drive the displays. Since it is irrelevant whether displays are driven from unfiltered dc or pulsed dc (at fast
rates), a dual power system can be used that makes better
utilization of transformer rms ratings. The system utilizes a
full wave rectified but unsmoothed dc voltage to provide the
displays with 120 Hz pulsed power while the reset of the
system is driven by a conventional dc power circuit. The
frequency of 120 Hz is high enough to avoid display flicker
problems. The main advantages of this system are:
• Reduced transformer rating
• Much smaller smoothing capaCitor
• Increased LED light output due to pulsed operation
With the standard capacitor filter circuit, the rms current (full
wave) loading of the transformer is approximately twice the
dc output. Most commercial transformer manufacturers rate
transformers with capacitive input filters as follows:
Full Wave Bridge Rectifier Circuit
Transformer rms current = 1.8 x dc current required
Full Wave Center Tapped Rectifier Circuit
Transformer rms current = 1.2 x dc current required
4-332
r-------------------------------------------------------------------------------------~ U)
Co)
Applications
~
(Continued)
Vs UNREGULATED FULL WAVE\
RECTIFIED DISPLAY VOLTAGE _ "
VCC=5V~r__;:::t::;_--_r--;:::t::;----~
FOR LOGIC
COMMON
ANODE
LED
1~11
6:1
TL/F/l0210-7
FIGURE E. Direct Unregulated Display Supply
1:311
6:]
TUF/l0210-B
FIGURE F. Pulsed Regulated Display Supply
4-333
~National
~ Semiconductor
DM9386 4-Bit Quad Exclusive-NOR
with Open-Collector Outputs
General Description
The DM9386 consists of four independent Exclusive-NOR
gates with open-collector outputs. Single 1-bit comparisons
may be made with each gate, or multiple bit comparisons
may be made by connecting the outputs of the four gates
together. Typical power dissipation is 170 mW. The DM9386
is equivalent to the 8242.
Connection Diagram
Dual·ln-Llne Package
14 I-Vcc
AO- 1
80- 2
131-A3
00- 3
12 -83
01- 4
11 -03
81- 5
Al- 6
10 -02
GND- 7
8 -A2
9 -82
TL/F/9798-1
Order Number DM9386N
See NS Package Number N14A
Pin Names
Description
AO,BO
A1, B1
Gate 0 Inputs
Gate 1 Inputs
Gate 2 Inputs
Gate 3 Inputs
Gate Outputs
A2,B2
A3,B3
00-03
4-334
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
Operating Free Air Temperature Range
Commercial
Storage Temperature Range
5.5V
O'Cto +70'C
- 65'C to + 150'C
Recommended Operating Conditions
Symbol
Parameter
Min
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
10H
High Level Output Current
10L
Low Level Output Current
TA
Free Air Operating Temperature
Nom
Max
Units
5
5.25
V
0.8
V
-0.150
rnA
25
rnA
70
'C
4.75
V
2
-0.150
0
Electrical Characteristics
Over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
=
=
Typ
(Note 1)
Min
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vee
VOH
High Level
Output Voltage
Vee = Min, 10H
VIL = Max
=
Max,
VOL
Low Level
Output Voltage
Vee = Min, 10L
VIH = Min
=
Max,
II
Input Current @ Max
Input Voltage
Vee
=
Max, VI
=
5.5V
IIH
High Level Input Current
Vee
Max, VI
80
/LA
Low Level Input Current
Vee
=
=
2.4V
IlL
=
=
0.4V
-3.2
rnA
los
Short Circuit
Output Current
Vee = Max
(Note 2)
-57
rnA
Icc
Supply Curent
Vcc = Max,
VIN(A), VIN(S)
47.5
rnA
Min,ll
Max, VI
-12 rnA
V
3.4
2.4
0.2
-18
=
0.4V
0.4
V
1
rnA
Switching Characteristics at Vee = 5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
tpLH
Propagation Delay Time
Low to High Level Output
tpHL
Propagation Delay Time
High to Low Level Output
Conditions
CL
RL
= 30pF
= 5300
Nole 1: All typicals are al Vee = 5V, TA = 25'C.
Nole 2: Nol more than one output should be shorted at a time.
4·335
Min
Max
Units
25
ns
25
ns
Logic Symbol
1
2
Truth Table
6
5
8
Inputs
9 13 12
00
01
02
03
3
10 MHz
• Flexibility of operation-optional retriggeringllock-out
capability
• Output pulse width range-50 ns to 00
• Leading or trailing edge triggering
• Complementary outputs/inputs
• Input clamping diodes
• DTLlTTL compatible logic levels
• Alternate Military/Aerospace device (9601) is available.
Contact a National Semiconductor Sales Office/Distributor for specifications.
Connection Diagram
Dual-In-Line Package
Q
9
A1
B1
A2
B2
He
8
GND
TL/F/6610-1
Order Number 9601DMQB, 9601FMQB, DM9601J, DM9601W or DM9601N
See NS Package Number J14A, N14A or W14B
Function Table
Inputs
Outputs
A1
A2
B1
B2
Q
H
H
X
X
L
X
X
L
X
X
X
X
L
L
L
X
X
X
H
X
X
X
L
L
L
H
J,
J,
J,
J,
H
t
H
H
L
H
H
t
t
H
H
H
H
H
H
H
H
H
t
4-337
L
L
L
Jl..
Jl..
L
Jl..
Jl..
Jl..
Jl..
Jl..
Q
H
H
H
H
l...J
l...J
H
l...J
l...J
l...J
l...J
l...J
H
~
High Logic Level
L
~
Low LogiC Level
X
~
Either Low or
High LogiC Level
t
~
Low to High Level
Transition
.J, ~ High to Low Level
Transition
.n. ~ Positive Pulse
1..f"
~
Negative Pulse
II
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
- 55·C to + 125·C
Military
Commercial
O· to +700C
-65·C to + 150·C
Storage Temperature Range
Recommended Operating Conditions
Symbol
Vee
Supply Voltage
VIH
High Level Input
Voltage
CommerCial
Military
Parameter
TA = -55·C
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
1.9
1.8
1.7
TA = 75·C
V
1.6
TA = 125·C
Low Level Input
Voltage
1.5
TA = -55·C
0.85
0.85
TA = O·C
TA = 25·C
0.9
0.85
TA = 75·C
0.85
-0.72
High Level Output Current
10L
Low Level Output Current
TA
Free Air Operating Temperature
V
0.85
TA = 125·C
10H
V
2
TA = O·C
TA = 25·C
VIL
Units
Min
10
-55
125
0
-0.96
mA
12.8
mA
75
·c
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Conditions (Note 3)
Parameter
VI
Input Clamp Voltage
Vee = Min, 11= -12 mA
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
VIL = Max, VIH = Min, (Note 4)
VOL
Low Level Output
Voltage
Vee = Min, 10L = Max
VIL = Max, VIH = Min
(Note 4)
IIH
High Level Input
Current
Vee = Max, VI = 4.5V
IlL
Low Level Input
Current
Vee = Max
Short Circuit
Output Current
Vee = Max
(Notes 2 and 4)
lOS
Min
Typ
(Note 1)
Max
Units
-1.5
V
V
2.4
MIL
0.4
COM
0.45
60
MIL VIN = OAOV
-1.6
COM VIN = 0.45V
-1.6
MiL
-10
-40
COM
-10
-40
Supply Current
25
Vee = Max
Icc
Not. 1: All typical. are at Vee = SV, TA = 2S'C.
Not. 2: Not more than one output should be shorted at 8 time.
Not. 3: Unless otherwise noted, Rx = 10k between PIN 13 and Vee on all tests.
Note 4: Ground PIN 11 for VOL test on PIN 6, VOH and lOS tests on PIN 8. Opan PIN 11 for VOL test on PIN 8, VOH and lOS tests on PIN 6.
4-338
V
p.A
mA
mA
mA
Switching Characteristics at Vee =
Symbol
From (Input)
To (Output)
Parameter
tpLH
tpHL
C&:I
CD
5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
Conditions
Propagation Delay Time
Low to High Level Output
Negative Trigger
Input to
True Output
Propagation Delay Time
High to Low Level Output
Negative Trigger
Input to
Complement Output
Min
Max
Units
40
ns
40
ns
65
ns
3.76
/los
50
pF
CL = 15pF
Cx= 0
Rx = 5kO
tpW(MIN)
Minimum True Output
Pulse Width
tpw
Pulse Width
Rx = 10kO
Cx = 1000 pF
CSTRAY
Maximum Allowable
Wiring Capacitance
Pin 13 to GND
3.08
Rx
External Timing Resistor
DM96
25
kO
Rx
External Timing Resistor
DM86
50
kO
Operating Rules
1. An external resistor Rx and an external capacitor Cx are
required for operation. The value of Rx can vary between
the limits shown in switching characteristics. The value of
Cx is optional and may be adjusted to achieve the required output pulse width.
5. Retrigger pulse width (see Figure :3) is calculated as follows:
tw = tpw
+
tpLH = K RxCx [ 1
+
0.7]
Rx
+
tpLH
2. Output pulse width tpw may be calculated as follows:
tpw = K RxCx [ 1
-~
+ -0.7] (for Cx > 103 pF)
Rx K::::: 0.34
QOUTPUT
RX in kO, Cx in pF and tpw in ns.
(For Cx
<
103 pF, see curve.)
P=c
TL/F/6610-4
FIGURE 3
3. Rx and Cx must be kept as close as possible to the
circuit in order to minimize stray capacitance and noise
pickup. If remote trimming is required, Rx may be split up
such that at least RX(MIN) must be as close as possible
to the circuit and the remote portion of the trimming resistor R < RX(MAX) - Rx.
4. Set-up time (t1) for input trigger pulse must be > 40 ns.
(See Figure 1).
Release time (t2) for input trigger pulse must be
(See Figure 2).
Typical UK" Coefficient Variation vs Timing Capacitance
The multiplicative factor UK" varies as a function of the timing capacitor, Cx. The graph below details this characteristic:
100 ~F
> 40 ns.
10 ~F
~A\"~5tcl
Vcc=5.0V
1 ~F
2.5V
J-" \:
1.5 V
iii 0.1 ~F
'" 104 pF
103 pF
1.5 V
102 pF
VIN
TL/F/6610-2
10 pF
FIGURE 1
0 .2 .4 .6 .8 1.0 1.2 1.4 1.6
"K" COEFFICIENT
TLlF/6610-5
VIN
:C:F
1.5V
'For further detailed device characteristics and output performance. please
refer to the NSC one-shot application note, AN-366.
2.5V
1.5V
TL/F/6610-3
FIGURE 2
4-339
CI
......
~
i
r-------------------------------------------------------------------------------------,
Typical Performance Characteristics
Output Pulse Width vs
Timing Resistance And
104 Capacitance For Cx < 103 pF
V.
~
RX- 5Ok
:r:::.I-I
H-ti
~5k
10
1
~xm30k
R~=20k
"""
RX
i
~ 10~~
LI
'1
Normalized Output
Pulse Width vs Ambient
Temperature
1
.10
1.05
"-
I
0.85
0.80
10
-75
i
TA~25"C
zo
25
!j!:
~
Vee =5.0 V
18
/
12
1/
V
OPERATING DUTY CYClE ("")
100
10
I-
V
4.0 ~
60
=
I
,- .-
1.00
n_
20
30
RX - EXTERNAL
40
50
REaISTANCE (kO)
-
....-
,/
0.85
0.80
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE (V)
Output Pulse Width vs
Ambient Temperature
!
80
i
70
~
~
8.0
60
TA=25"C
RX 10k
Cx= 103111'
1.05
125
Cx = 103111'
1
40
75
~
1.0
I:
""
Pulse Width vs Timing
Resistance
zo
VCC = 5.0Y
RX = 10k
Cx = 103111'
1.2
1.10
TA - AMBIENT TEMPERATURE ('C)
Normalized Output
Pulse Width vs
Operating Duty Cycle
1.4
-25
i
i
i
"' "
1.00
Cx. 11IIING CAPACITANCE (pi')
i
i
Vee = 5.0 V
RX a 10k
Cx = 103111'
"\
Normalized Output
Pulse Width vs Supply
Voltage
i
I
-s.ov
VCC
RX = S.Ok
Cx=O
COMPLEMENTARY OUTPUT
-!-'
TRUE OUTPUT
50
30
10
-76
-25
25
75
126
TA - AMBIENT 'lBlPERATURE ('C)
TL/F/661 0-6
Schematic Diagram
(13)
(11)
TL/F/6610-7
4·340
r----------------------------------------------------------------------------, en
U)
o
~National
1\:1
~ Semiconductor
9602/DM9602 Dual Retriggerable,
Resettable One Shots
General Description
Features
These dual resettable, retriggerable one shots have two inputs per function; one which is active high, and one which is
active low. This allows the designer to employ either leading-edge or trailing-edge triggering, which is independent of
input transition times. When input conditions for triggering
are met, a new cycle starts and the external capacitor is
allowed to rapidly discharge and then charge again. The
retriggerable feature permits output pulse widths to be extended. In fact a continuous true output can be maintained
by having an input cycle time which is shorter than the output cycle time. The output pulse may then be terminated at
any time by applying a low logic level to the RESET pin.
Retriggering may be inhibited by either connecting the Q
output to an active high input, or the Q output to an active
low input.
•
•
•
•
•
•
70 ns to co output width range
Resettable and retriggerable--O% to 100% duty cycle
TTL input gating-leading or trailing edge triggering
Complementary TTL outputs
Optional retrigger lock-out capability
Pulse width compensated for Vee and temperature
variations
• Alternate Military/Aerospace device (54xxx) is available.
Contact a National Semiconductor Sales Office/Distributor for specifications.
Connection Diagram
Dual-In-Llne Package
vcc
CEXT2
REXT'
CEXT2
116
15
14
CLR2
13
02
10
I
9
__
I
I
CEXT1
2
3
REXT'
CEXT1
CLR1
14
15
B1
A1
7
6
01
0'1
18
GND
TUF/6611-1
Order Number 9602DMQB, 9602FMQB or DM9602N
See NS Package Number J16A, N16E or W16A
Function Table
Pin No's.
A
H
Operation
B
CLR
H-L
L
H
L-H
X
X
H
H
L
= High Voltage Level
L = Low Voltage Level
X = Don't Care
4-341
Trigger
Trigger
Reset
•
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
Military
- 55°C to + 125°C
Commercial
O°Cto + 70°C
Storage Temperature Range
- 65°C to + 150°C
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Recommended Operating Conditions
Symbol
Vee
Supply Voltage
VIH
High Level Input
Voltage
VIL
Military
Parameter
Low Level Input
Voltage
=
TA =
TA =
TA =
TA =
TA =
TA =
TA =
TA =
TA =
TA
-55°C
Commercial
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
1.9
1.8
1.7
V
1.65
75°C
125°C
V
2
O°C
25°C
, Units
Min
1.5
0.85
-55°C
0.85
O°C
0.9
25°C
0.85
V
0.85
75°C
0.85
125°C
10H
High Level Output Current
-0.8
-0.8
mA
10L
Low Level Output Current
16
16
mA
TA
Free Air Operating Temperature
75
°C
Electrical Characteristics
Symbol
-55
125
over recommended operating free air temperature range (unless otherwise noted)
Parameter
Conditions (Note 3)
Input Clamp Voltage
Vee
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
VIL = Max, VIH = Min
(Note 4)
Low Level Output
Voltage
Vee = Min, 10L = Max
VIL = Max, VIH = Min
(Note 4)
IIH
High Level Input Current
IlL
Low Level Input
Current
lee
Typ
(Note 1)
= Max, VI = 4.5V
Vee = Max
= Min
Short Circuit
Output Current
Vee = Max, VOUT
(Notes 2 and 4)
Supply Current
Vee
= 1V
= Max
Max
Units
-1.5
V
2.4
V
MIL
0.4
COM
0.45
60
Vee
Vee
los
Min
= Min, II = -12 mA
VI
VOL
0
= 0.40V
COM VI = 0.45V
MIL VI = 0.40V
COM VI = 0.45V
V
/LA
-1.6
MIL VI
-1.6
-1.24
mA
-1.41
MIL
-25
COM
-35
MIL
39
45
COM
39
50
mA
mA
Note 1: All typical. are at Vee ~ 5V, TA ~ 25·C.
Note 2: Not more than one output should be shorted at a time.
Note 3: Unless otherwise noted, Rx ~ 10k for all tests.
Note 4: Ground PIN 1 (15) for VOL on PIN 7(9) or VOH and los on PIN 6(10) and apply momentary ground to PIN 4(12). Open PIN 1(15) for VOL on PIN 6(10) or VOH
and los on PIN 7(9),
4-342
CD
Switching Characteristics Vee =
Symbol
Parameter
Military
Conditions
Min
tpLH
Propagation Delay Time,
Low-to-High Level Output
Negative Trigger Input
to True Output
tpHL
Propagation Delay Time,
High-to-Low Level Output
Negative Trigger Input
To Complement Output
tpw(MIN)
Minimum True Output
Pulse Width
CL = 15 pF
Cx = 0
Rx = 5k!1
Commercial
Min
Max
tpw
Pulse Width
Rx = 10k!1
Cx = 1000pF
CSTRAY
Maximum Allowable Wiring
Capacitance
Pins 2,14 to
GND
Rx
External Timing Resistor
3.0B
Units
Max
35
40
ns
43
4B
ns
90
100
100
110
5
25
5
C
Cx
ex
~ lr ~ ••
",>oJ
'"' Vee
.A
3.0B
3.76
50
Logic Diagrams
(15)
(6)
3.76
p.s
50
pF
50
k!1
",>ojVee
rl
,A
(2)
.A.AA.
114)
(10)
Q-
Q --'--'-
(4)
(12) _
§:J
~
CD
N
ns
Minimum Complement
Pulse Width
(1)
en
o
5V, TA = 25'C (See Section 1 for Test Waveforms and Output Load)
-
Q~
CD
_
(9)
Q
f--
Y(13)
r(3)
TL/F/6611-2
TL/F/6611-3
1. An external resistor (Rx) and external capacitor (Cx) are
required as shown in the Logic Diagram.
4. If electrolytic type capacitors are to be used, the following
three configurations are recommended:
Operating Rules
2. The value of Cx may vary from 0 to any necessary value
available. If, however, the capacitor has leakages approaching 3.0 p.A or if stray capacitance from either terminal to ground is more than 50 pF, the timing equations
may not represent the pulse width obtained.
A. Use with low leakage capacitors:
The normal RC configuration can be used predictably
only if the forward capacitor leakage at 5.0V is less
than 3 p.A, and the inverse capacitor leakage at 1.0V is
less than 5 p.A over the operational temperature
range.
3. The output pulse with (t) is defined as follows:
t = K RxCx [1
where:
+ ~J
10rCx> 103pF
K:::: 0.34
(14)
vee~PIN2
Rx
ex
Rx is in k!1, Cx is in pF
tisinns
for Cx
<
R < 0.6 Rx (Max)
103 pF, see Figure 1.
lor K vs Cx see Figure 6.
4-343
~(151
PIN 1
TL/F/6611-4
Operating Rules (Continued)
B. Use with high inverse leakage current electrolytic capacitors:
7. Input Trigger Pulse Aules (See Triggering Truth Table)
The diode in this configuration prevents high inverse
leakage currents through the capacitor by preventing
an inverse voltage across the capacitor. The use of
this configuration is not recommended with retriggerable operation.
INPUT
2.S v --+~-...... I
ov
QOUTPUT
t ~ 0.3ACx
TL/F/6611-B
V~(14)
CC
PIN 2
R
(Pin 3(13) = HIGH)
Input to Pin 5(11),
Pin 4(12) = LOW
Cx
L(IS)
,PIN 1
tl, ts = Min. Positive Input Pulse Width> 40 ns
t2,
4
= Min. Negative Input Pulse Width > 40 ns
TL/F/6611-S
2.SV
C. Use to obtain extended pulse widths:
INPUT
This configuration can be used to obtain extended
pulse widths, because of the larger timing resistor allowed by beta multiplication. Electrolytics with high inverse leakage currents can be used.
A < Ax (0.7) (hFE 01) or
lesser
1.5 V
ov
QOUTPUT
4 kk
2'sv=
13-
~
--I
(Pin 3(13) = HIGH)
Pin 5(11) = HIGH
B. The retriggerable pulse width is calculated as shown below:
01: NPN silicon transistor with hFE requirements of
above equations, such as 2N5961 or 2N5962.
tw = t + tpLH =
t ~ 0.3 ACx
INPUT
Ry
K Ax Cx (1
vec 1 & Q l(14)
pulse widths greater than 500 ns, tw can be approximated as t. Retriggering will
not occur if the retrigger pulse comes within::::: 0.3 ex (ns) after the initial trigger
PIN 1
puis. 0.... during tho discharg. cycl.).
9. Aeset Operation-An overriding clear (active LOW level)
is provided on each one shot. By applying a LOW to the
reset, any timing cycle can be terminated or any new cycle inhibited until the LOW reset input is removed. Trigger
inputs will not produce spikes in the output when the reset is held LOW.
TUF/6611-6
This configuration is not recommended with retriggerable operation.
5. To obtain variable pulse width by remote trimming, the
following circuit is recommended:
(15)
s: RX (Min)
.:::r
PIN 1
Vee
IL..-__
TL/F/66"-'0
~(1S)
Rx
I-·IW-I
Th. roIrigg.r pulse width Is .quallo lho pulse width (t) plus a d.lay tim•. For
PIN 2
--Is
~Ci.OSEAS...... POSSIBLE TO DEVICE
+ ~J + tpLH
JlI--_-!rl.......-_-.....___
o OUTPUT ~
(14)
I::.
fU.v
--'1.5V
Input to Pin 4(12)
Ax (min) < Ay < Ax (max)
(5 kO s: Ay s: 10 kO is recommended)
PIN 2
1.5 V
TL/F16611-9
< 2.5 MO, whichever is the
Cx
OVIpLH
INPUT
R c: RX (Max) - RX
RESET
0---------
QOUTPUT
oOUTPUT
TLlF/66"-7
6. Under any operating condition, Cx and Ax (min) must be
kept as close to the circuit as possible to minimize stray
capacitance and reduce noise pickup.
TUF/6611-11
10. Vee and Ground wiring should conform to good high
frequency standards so that switching transients on Vee
and Ground leads do not cause interaction between one
shots. Use of a 0.01 to 0.1 ",F bypass capacitor between Vee and Ground located near the DM9602 is recommended.
"'For further detailed device characteristics and output performance, please
refer to the NSC one·shot application note, AN-366.
4-344
r-------------------------------------------------------------------------------------, en
U)
Typical Performance Characteristics
C)
I\)
W1. 10
104
/. ~ ....
RX - 50k
~
-
" . ~<
~
-
r'
IRX - 20k
RX ;011'=
..... ~
...... r-
~
III
ZO.90
-75
102
10
103
Cx • TIMING CAPACITANCE IpF)
1
"
oo
~0.95
~
III
I
I
10
1.05
~
5
i'Rx =30k
.);-
RX = 5k
~
~ /
~
VCC = 5.0 V
RX = 10 k!l
Cx = l03pF
~
1/
-25
25
75
TL/F/6611-13
TLlF/6611-12
FIGURE 2. Normalized Output Pulse Width
vs Ambient Temperature
FIGURE 1. Output Pulse Width vs Timing Resistance
and Capacitance for Cx < 103 pF
18
'iO'
.=.:z:
:z:
VCC = 5.0~
Cx = 103 pF
j
en
oJ
w
10
V
:::I
I>.
5I>.
50
L
IIIoJ
L
I>.
/'
~ 1.00
Q
~ 0.95
;
L
40
i
50
,,/
",
0.90
4.0
Px • EXTERNAL TIMING RESISTOR (Kill
4.5
5.0
TL/F/6611-14
140
i
130
~
120
III
5
110
I
TLlF/6611-15
I
i
100,.F
I I
.. O.l,.F
ti
104 pF
L
~
70
60
-75
-25
25
u
..vi
103 pF
I .J...-I'
102 pF
TR~E~UTpr
75
Vcc=5.0V
l,.F
COMPLEMENTARY OUTPUT
80
+A;"~5~CI
10,.F
RX = 5 k!l
Cx =0
CL = 15 pF
90
6.0
FIGURE 4. Normalized Output Pulse Width
vs Supply Voltage
V~C = 5.0V
1>.100
5.5
VCC • SUPPLY VOLTAGE (V)
FIGURE 3. Pulse Width vs Timing Resistor
i
, V
/'
o
30
,.
1.05
!:i
V
20
TA = 25'C
RX = 10 k!l
Cx = 103 pF
:::I
6
2
10
1.10
~
/
14
I:i
125
TA' AMBIENT TEMPERATURE IOC)
10pF
125
TA • AMBIENT TEMPERATURE I'C)
TL/F/6611-16
r"-I'-
o
.2
.4 .6 .8 1.0 1.2 1.4 1.6
"K" COEFFICIENT
TL/F/6611-17
FIGURE 5. Minimum Output Pulse Width
vs Ambient Temperature
FIGURE 6. Typical uK" Coefficient Variation
va Timing Capacitance
4·345
_r-----------------------------------------------------------------~
o
i
~National
~ Semiconductor
DM96101
Quad 2-lnput Positive NAND Buffer
with Open-Collector Output
General Description
The DM96101 is similar to the 54/7439, except that the
outputs are specified at three levels of IOL; in the HIGH
state the IOH current is specified at two levels of VOH. During switching transitions, output current change rate is typically 4.0 mAIns.
Connection Diagram
Dual-In-Llne Package
GND
TL/F/9799-1
Order Number DM96101N
Se NS Package Number N14A
4-346
CD
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
Operating Free Air Temperature Range
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditIons for actual device operation.
5.5V
O'Cto +70'C
-65'C to + 150'C
Storage Temperature Range
Recommended Operating Conditions
Symbol
Parameter
Vcc
Supply Voltage
VIH
High Level Input Voltage
Vil
Low Level Input Voltage
10H
High Level Output Current
Min
Nom
Max
Units
4.75
5
5.25
V
V
2
0.8
V
-0.05
mA
10L
Low Level Output Current
16
mA
TA
Free Air Operating Temperature
70
'C
0
Electrical Characteristics
Over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
=
=
VI
Input Clamp Voltage
Vcc
VOH
High Level
Output Voltage
Vcc = Min, 10H
Vil = Max
VOL
Low Level
Output Voltage
Vcc = Min,
VIH = VIN
II
Input Current @ Max
Input Voltage
Vcc
=
Max, VI
IIH
High Level Input Current
Vcc
=
Max
Min,ll
Min
-12 mA
=
Max
=
10l =
10l =
10l
=
2.4
=
=
VIN
=
80mA
0.6
1
2.4V
40
5.5V
1000
Vcc
Vcc = Max
(Note 2)
ICCH
Supply Current
with Outputs High
Vcc
=
Max, VIN
=
OV
ICCl
Supply Current
with Outputs Low
Vcc
=
Max, VIN
=
Open
Symbol
Parameter
tplH
Propagation Delay Time
Low to High Level Output
tpHL
Propagation Delay Time
High to Low Level Output
V
0.5
Low Level Input Current
O.4V
-18
=
=
=
Note 1: All typicals are at Vee = SV, TA = 2S'C.
Note 2: Not more than one output should be shorted at a time.
4-347
V
mA
p.A
-1.6
mA
-57
mA
8.5
mA
54
mA
25'C (See Section 1 for Test Waveforms and Output Load)
Conditions
Cl
Rl
V
60 mA
Short Circuit
Output Current
5V and TA
-1.5
0.4
los
Switching Characteristics at Vcc =
Units
48mA
IlL
Max, VIN
Max
3.4
5.5V
VIN
=
Typ
(Note 1)
45pF
1200
Min
Max
Units
22
ns
25
ns
en
....
....o
Section 5
TTL - Low Power
II
Section 5-TTL· Low Power
TTL (Low Power)-MillAero
DM54l00 Quad 2·lnput NAND Gate ........•.........•.......................••......
DM54l02 Quad 2·lnput NOR Gate. . . • . . . • . . • . . . . . . . . . • . . • . • • . . . . . • . • . . • . . . . . . . . . . . . . .
DM54l04 Hex Inverter. . . . . . . . . . . . . • . . • . . . . • . • . . • . • . . . . • . . • . . . . . . . . . . . . • . . . . . . . . . . . .
DM54l 10 Triple 3·lnput NAND Gate. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . . . . . . . . . .
DM54l72 AND·Gated Master·Slave J·K Flip·Flop with Preset, Clear, and Complementary
Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54l73 Dual J·K Flip·Flop with Clear and Complementary Outputs. ... ... .... . .... .... ..
DM54l74 Dual Positive·Edge·Triggered 0 Flip·Flop with Preset, Clear, and Complementary
Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54l93 4·Bit Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54l95 4·Bit Parallel Access Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54l98 4·Bit Data Selector/Storage Register...... ....... .. .. . .. . . .. . . ..... ... ... ...
93100 4·Bit Universal Shift Register. . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
93101 1·of·10 Decoder .............................................................
93108 Dual 4·Bit latch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . .
93109 Dual 4·lnput Multiplexer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
93110 BCD Decade Counter /4·Bit Binary Counter. .. .. . . .. .. . .. .. . .. . .. .. .. . .. . .. .. .. . .
93l 12 8·lnput Multiplexer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . .
93114 Quad latch. . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
93L16 BCD Decade Counter /4·Bit Binary Counter .. . .. .. .. .. .. .. .. . . .. .. .. . .. . .. .. .. .. .
93121 Dual 1·of·4 Decoder. . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
93122 Quad 2·lnput Multiplexer ...... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
93124 5·Bit Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
93128 Dual 8·Bit Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
93134 8·Bit Addressable latch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
93138 8·Bit Multiple Port Register... ....... ... ....... .... ...... ... . ... . . . .. ..... .....
96102 Dual Retriggerable Resettable Monostable Multivibrator (One-Shot) ................
5·3
5·5
5·7
5·9
5·11
5·14
5·17
5·20
5·23
5·26
5·28
5·33
5·36
5·39
5·42
5·48
5·52
5·42
5·56
5·59
5·62
5·65
5·69
5·74
5-78
b
C)
~National
~ Semiconductor
DM54LOO
Quad 2-lnput NAND Gates
General Description
This device contains four independent gates each of which
performs the logic NAND function.
Connection Diagram
Function Table
v=
Dual·ln·Line Package
Vee
14
Al
B4
A4
V4
B3
A3
Inputs
V3
13
Bl
VI
A2
B2
AB
Output
A
B
V
L
L
L
H
H
H
L
H
H
H
H
L
H
~
High Logic Level
L
~
Low Logic Level
GND
V2
TL/F/6654-1
Order Number DM54LOOJ or DM54LOOW
See NS Package Number J14A or W14B
•
5·3
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" am those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
perametric values defined in the "Electrical Characteristics"
table am not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and spacHlcations.
Supply Voltage
8V
Input Voltage
Operating Free Air Temperature Range
DM57L
-55·C to
Storage Temperature Range
-65·Cto
5.5V
+ 125·C
+ 150·C
Recommended Operating Conditions
Symbol
DM54LOO
Parameter
Vec
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
10H
High Level Output Current
10L
Low Level Output Current
Free Air Operating Temperature
Symbol
Nom
Max
4.5
5
5.5
V
V
2
TA
Electrical Characteristics
Units
Min
-55
0.7
V
-0.2
rnA
2
rnA
125
·c
over recommended operating free air temperature (unless otherwise noted)
Parameter
Conditions
VOH
High Level Ouput
Voltage
Vee = Min, 10H
VIL = Max
= Max
VOL
Low Level Output
Voltage
Vee = Min. 10L
VIH = Min
= Max
II
Input Current @ Max
Input Voltage
Vee
= Max. VI = 5.5V
IIH
High Level Input
Current
Vee
= Max. VI = 2.4V
IlL
Low Level Input
Current
Vcc
= Max. VI = 0.3V
los
Short Circuit
Output Current
Vee = Max
(Note 2)
ICCH
Supply Current with
Outputs High
Vce
= Max
ICCL
Supply Current with
Outputs Low
Vee
= Max
Min
Typ
(Note 1)
2.4
3.3
Max
Units
V
0.15
0.3
V
0.1
rnA
10
p.A
-0.18
rnA
-15
rnA
0.44
0.8
rnA
1.16
2.04
rnA
-3
Note 1: All typlcals are at Vee = 5V. TA = 25"C.
Nate 2: Not more than one should be shorted at a time.
Switching Characteristics at Vee = 5V and TA = 25·C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
Conditions
tpLH
Propagation Delay
Low to High Level Output
RL = 4kO
CL = 50pF
tpHL
Propagation Delay
High to Low Level Output
5-4
Min
Max
Units
60
ns
60
ns
b
N
~National
~ Semiconductor
DM54l02 Quad 2-lnput NOR Gates
General Description
This device contains four independent gates each of which
performs the logic NOR function.
Connection Diagram
Dual-In-Line Package
V4
14
VI
84
A4
81
Al
V3
11
12
13
83
A3
82
GNO
10
A2
V2
TUF/6656-1
Order Number DM54L02J or DM54L02W
See NS Package Number J14A or W14B
Function Table
Y=A+B
Inputs
Output
A
B
Y
L
L
H
H
L
H
L
H
H
H
~
High Logic Level
L
~
Low Logic Level
L
L
L
•
5-5
N
9
Absolute Maximum Ratings (Note)
Note: The "Absolute MSJdmum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "£Ieetrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
BV
Input Voltage
5.5V
Operating Free Air Temperature Range
DM54L
-55'Cto
Storage Temperature Range
- 65'C to
+ 125'C
+ 150'C
Recommended Operating Conditions
Symbol
DM54L02
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
Vil
Low Level Input Voltage
10H
High Level Output Current
Units
Min
Nom
Max
4.5
5
5.5
V
0.7
V
-0.2
mA
2
mA
125
'C
2
10l
Low Level Output Current
TA
Free Air Operating Temperature
V
-55
Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Parameter
Conditions
Min
Typ
(Note 1)
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
Vil = Max
2.4
3.3
VOL
Low Level Output
Voltage
Vee = Min, 10l = Max
VIH = Min
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 5.5V
IIH
High Level Input Current
Symbol
Units
V
0.3
V
0.1
mA
Vee = Max, VI = 2.4V
10
,.,.A
-0.18
rnA
-15
mA
O.B
1.6
mA
1.4
2.6
rnA
III
Low Level Input Current
Vee = Max, VI = 0.3V
los
Short Circuit
Output Current
Vee = Max
(Note 2)
ICCH
Supply Current with
Outputs High
Vcc = Max
leCL
Supply Current with
Outputs Low
Vce = Max
Switching Characteristics at Vee =
Symbol
Max
0.15
-3
5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
Parameter
Conditions
tpLH
Propagation Delay Time
Low to High Level Output
RL = 4 kO
Cl = 50pF
tpHl
Propagation Delay Time
High to Low Level Output
Note 1: All typicals are at Vee = SV. TA = 2s·e.
Note 2: Not more than one output should be shorted at a time.
5-6
Min
Max
Units
60
ns
60
ns
J?)I National
~ Semiconductor
DM54L04 Hex Inverting Gate
General Description
This device contains six independent gates each of which
performs the logic INVERT function.
Connection Diagram
Dual-In-Llne Package
vee
14
Al
A6
V6
12
13
A2
VI
AS
11
V2
V5
A4
V4
V3
GND
ID
A3
TL/F/6616-1
Order Number DM54L04J or DM54L04W
See NS Package Number J14A or W14B
Function Table
Y=A
Input
Output
A
Y
L
H
H
L
H = High Logic Level
L = Low Logic Level
5-7
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
8V
Input Voltage
5.5V
Operating Free Air Temperature Range
DM54L
-55'Cto
Storage Temperature Range
- S5'C to
+ 125'C
+ 150'C
Recommended Operating Conditions
Symbol
DM54L04
Parameter
Vcc
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
IOH
High Level Output Current
Units
Min
Nom
Max
4.5
5
5.5
V
2
IOL
Low Level Output Current
TA
Free Air Operating Temperature
V
-55
0.7
V
-0.2
mA
2
mA
125
'C
Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
Conditions
= Max
Min
Typ
(Note 1)
2.4
3.3
Max
Units
VOH
High Level Output
Voltage
Vee = Min, IOH
VIL = Max
VOL
Low Level Output
Voltage
Vec = Min
IOL = Max
VIH = Min
II
Input Current @ Max
Input Voltage
Vcc
IIH
High Level Input Current
Vee
10
p.A
IlL
Low Level Input Current
VCC
-0.18
mA
los
Short Circuit
Output Current
(Note 2)
-15
mA
V
0.15
= Max, VI = 5.5V
= Max, VI = 2.4V
= Max, VI = 0.3V
VCC = Max
-3
0.3
V
0.1
mA
ICCH
Supply Current with
Outputs High
Vcc
= Max
O.S
1.2
mA
ICCL
Supply Current with
Outputs Low
Vcc
= Max
1.7
3.0S
mA
Switching Characteristics at Vcc = 5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
tpLH
Propagation Delay Time
Low to High Level Output
tpHL
Propagation Delay Time
High to Low Level Output
Conditions
RL
CL
= 4kfi,
= 50pF
Note 1: All typicals are at Vee = sv, TA = 2S'C.
Note 2: Not more than one output should be shorted at a time.
5-8
Min
Max
Units
SO
ns
SO
ns
r.....
Q
~National
~ Semiconductor
DM54L10
Triple a-Input NAND Gates
General Description
This device contains three independent gates each of which
performs the logic NAND function.
Connection Diagram
Dual-In-Llne Package
]:4
VI
Cl
Il
Cl
11
12
Vl
10
-
~
-
~
l .
1
Al
Al
Bl
A2
Bl
B2
C2
V2
TUF/6619-1
Order Number DM54L 10J or DM54L 10W
See NS Package Number J 14A or W14B
Function Table
y= ABC
Inputs
Output
A
B
C
Y
X
X
L
X
L
X
L
X
X
H
H
H
H
H
H
L
H = High Logic Level
L = Low Logic Level
X = Either Low or High Logic Level
•
5-9
....-Io
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
8V
Input Voltage
Operating Free Air Temperature Range
DM54L
- 55'C to
Storage Temperature Range
-65'Cto
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
5.5V
+ 125'C
+ 150'C
Recommended Operating Conditions
Symbol
DM54L10
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
10H
High Level Output Current
Units
Min
Nom
Max
4.5
5
5.5
V
0.7
V
-0.2
mA
2
mA
125
'C
2
10L
Low Level Output Current
TA
Free Air Operating Temperature
V
-55
Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 1)
2.4
3.3
VOH
High Level Output
Voltage
Vee = Min,lOH = Max
VIL = Max
VOL
Low Level Output
Voltage
Vee = Min, 10L = Max
VIH = Min
II
Input Current @ Max
Input Voltage
Vcc = Max, VI = 5.5V
IIH
High Level Input
Current
Vee = Max, VI = 2.4V
IlL
Low Level Input
Current
Vee = Max, VI = 0.3V
los
Short Circuit
Output Current
Vee = Max
(Note 2)
ICCH
Supply Current with
Outputs High
Vee = Max
leeL
Supply Current with
Outputs Low
Vcc = Max
Switching Characteristics at Vee =
Symbol
Units
V
0.15
0.3
V
0.1
mA
10
/LA
-0.18
mA
-15
mA
0.33
0.6
mA
0.87
1.53
mA
-3
5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
Parameter
Conditions
tpLH
Propagation Delay Time
Low to High Level Output
RL = 4kO,
CL=50pF
tpHL
Propagation Delay Time
High to Low Level Output
Note 1: All typical. are at Vee = 5V. TA
Max
= 25'0.
Note 2: Not more than one output should be shorted at a time.
5-10
Min
Max
Units
60
ns
60
ns
J?A National
~ Semiconductor
DM54L72 AND-Gated Master-Slave J-K Flip-Flop
with Preset, Clear and Complementary Outputs
General Description
This device contains a positive pulse triggered master-slave
J-K flip-flop with complementary outputs. Multiple J and K
inputs are AN Oed together to produce the internal J and K
function for the flip-flop. The J and K data is processed by
the flip-flop after a complete clock pulse. While the clock is
low the slave is isolated from the master. On the positive
transition of the clock, the data from the AND gates is transferred to the master. While the clock is high the AND gate
inputs are disabled. On the negative transition of the clock
the data from the master is transferred to the slave. The
logic state of the J and K inputs must not be allowed to
change while the clock is in the high state. Data is transferred to the outputs on the falling edge of the clock pulse.
A low logic level on the preset or clear inputs sets or resets
the outputs regardless of the logic levels of the other inputs.
Connection Diagram
Function Table
Inputs
Dual·ln·llne Package
Vee
PR
ClK
K3
K2
Kl
Q
Outputs
PR
ClR
ClK
J
(Note 1)
K
(Note 1)
Q
Q
L
H
L
H
H
H
H
H
L
L
H
H
H
H
X
X
X
X
X
X
X
X
X
H
L
H*
L
H
H*
.n..
.n..
.n..
.n..
L
H
L
H
L
L
H
H
00
00
L
H
L
H
Toggle
Note 1: J ~ (Jl)(J2)(J3), K ~ (Kl)(K2)(K3)
NC
Jl
J2
J3
GND
TUF/6629-1
Order Number DM54l72J or DM54l72W
See NS Package Number J14A or W14B
H ~ High Logic Level
X ~ Either Low or High Logic Level
L ~ Low Logic Level
J'1.. ~ Positive pulse. The J and K inputs must be held constant while the
clock is high. Data is transferred to the outputs on the falling edge of the
clock pulse.
0 0 ~ The output logic level before the indicated input conditions were established.
'" = This configuration is nonstable; that is, it will not persist when the preset
and/or clear inputs return to their inactive (high) level.
Toggle ~ Each output changes to the complement of its previous level on
each complete high level clock pulse.
5-11
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
BV
Input Voltage
5.5V
Operating Free Air Temperature Range
DM54L
- 55·C to + 125·C
Storage Temperature Range
-65·C to + 150·C
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guarateed
The device should not be operated at these limits. The para·
metric values defined in the "Electrical Characteristics" tao
ble are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Recommended Operating Conditions
Symbol
DM54L72
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
Vil
Low Level Input Voltage
Units
Min
Nom
Max
4.5
5
5.5
2
V
V
Clock
0.6
Others
0.7
V
IOH
High Level Output Current
-0.2
mA
2
mA
6
MHz
IOl
Low Level Output Current
felK
Clock Frequency (Note 2)
tw
Pulse Width (Note 2)
0
Clock High
100
Clock Low
100
Preset Low
100
Clear Low
100
tsu
Input Setup Time (Notes 1 & 2)
ot
tH
Input Hold Time (Notes 1 & 2)
O,J..
TA
Free Air Operating Temperature
-55
Nate 1: The symbols (t, ,J.) indicate the edge of the clock pulse used for reference:
Note 2: TA = 2S'C and Vee = SV.
5·12
ns
t
for rising edge, ,J. for falling edge.
ns
ns
125
·C
Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 1)
2.4
3.3
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
VIL = Max, VIH = Min
VOL
Low Level Output
Voltage
Vee = Min, 10L = Max
VIL = Max, VIH = Min
II
Input Current @ Max
Input Voltage
Vee = Max
VI = 5.5V
IIH
IlL
los
High Level Input
Current
Low Level Input
Current
Short Circuit
Output Current
Vee = Max
VI = 2.4V
Vee = Max
VI = 0.3V
Vee
Max
V
0.15
0.3
J,K
100
Clear
200
Preset
200
Clock
200
J,K
10
Clear
20
Preset
20
Clock
-200
J,K
-0.18
Clear
-0.36
Preset
-0.36
Clock
-0.36
= Max
Units
-3
V
p.A
p.A
mA
-15
mA
Supply Current
1.44
Vee = Max (Note 2)
0.76
typical. are at Vee = SV, TA = 2S'C.
Note 2: WHh all outputs open, Icc is measured wHh the a and a outputs high in tum. At the time of measurement the clock Input is grounded.
mA
lee
Nole 1: All
Switching Characteristics at Vee = 5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
From (Input)
To (Output)
RL
= 4kO,CL = 50pF
Min
Units
Max
fMAX
Maximum Clock Frequency
tpLH
Propagation Delay Time
Low to High Level Output
Preset
toO
MHz
75
ns
tpHL
Propagation Delay Time
High to Low Level Output
Preset
toO
150
ns
tpLH
Propagation Delay Level Output
Low to High Level Output
Clear
toO
75
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clear
toO
150
ns
tpLH
Propagation Delay Time
Low to High Level Output
Clock to
OorO
10
75
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clock to
OorO
10
150
ns
6
5-13
~National
~ Semiconductor
DM54L73 Dual Master-Slave J-K Flip-Flops
with Clear and Complementary Outputs
General Description
This device contains two independent positive pulse triggered J-K flip-flops with complementary outputs. The J and
K data is processed by the flip-flops after a complete clock
pulse. While the clock is low the slave is isolated from the
master. On the positive transition of the clock, the data from
the J and K inputs Is transferred to the master. While the
clock is high, the data from the J and K inputs are
disabled. On the negative transition of the clock, the data
from the master is transferred to the slave. The logic states
of the J and K inputs must not be allowed to change while
the clock is high. Data is transferred to the outputs on the
falling edge of the clock pulse. A low logic level on the clear
input will reset the outputs regardless of the logic states of
the other inputs.
Connection Diagram
Dual-In-Llne Package
iiI
Jl
14
13
ClK 1
ClR 1
Ql
GND
Q2
ii2
ClR2
J2
K2
12
10
Kl
ClK2
Vee
TUF/6530-1
Order Number DM54L73J or DM54L73W
See NS Package Number J14A or W14B
Function Table
Inputs
Outputs
CLR
CLK
J
K
L
H
H
H
H
X
SL
SL
SL
SL
X
L
H
L
H
X
L
L
H
H
Q
Q
L
H
00
00
H
L
L
H
Toggle
H = High Logic Level
X = Either Low or High Logic Level
L = Low Lagle Lavel
..n.. = Positive pulse data. The J and K Inputs must be held constant while
the clock Is high. Data Is transferred to the outputs on the falling edge of the
clock pulse.
00 = The output logiC level before the indicated Input condijions were
established.
Toggle = Each output changes to the complement of Us previous level on
each complete high level clock pulse.
5-14
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device can not be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
8V
Input Voltage
5.5V
-65'C to
+ 150'C
Operating Free Air Temperature Range
-55'C to
DM54L
+ 125'C
Storage Temperature Range
Recommended Operating Conditions
Symbol
DM54L73
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
Vil
Low Level Input Voltage
Units
Min
Nom
Max
4.5
5
5.5
2
V
V
Clock
0.6
Others
0.7
V
IOH
High Level Output Current
-0.2
IOl
Low Level Output Current
2
mA
felK
Clock Frequency (Note 2)
6
MHz
tw
Pulse Width (Note 2)
0
CloekHigh
100
Clock Low
100
Clear Low
100
tsu
Input Setup Time (Notes 1 & 2)
tH
Input Hold Time (Notes 1 & 2)
ot
oJ-
Free Air Operating Temperature
-55
TA
Nate 1: The symbols (t, J.) Indicate the edge of the clock pulse used for reference:
Note 2: TA = 2S'C and Vee = SV.
5-15
mA
t for rising edge, J. for falling edge.
ns
ns
ns
125
'C
Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 1)
2.4
3.3
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
VIL = Max, VIH = Min
VOL
Low Level Voltage
Voltage
Vee = Min, 10L = Max
VIL = Max, VIH = Min
II
Input Current @ Max
Input Voltage
Vee = Max
VI = 5.5V
IIH
High Level Input
Current
Vee = Max
VI = 2.4V
Vee = Max
VI = 0.3V
los
Short Circuit
Output Current
Vee = Max
Icc
Supply Current
Vee = Max (Note 2)
Note 1: All typlcals are at Vee = SV, TA = 2S'C.
Note 2: With all outputs open, Icc Is measured wHh the Q and
Units
V
0.15
0.3
J, K
100
Clear
200
Clock
200
V
p.A
10
J,K
Low Level Input
Current
IlL
Max
Clear
20
Clock
-200
J, K
-0.18
Clear
-0.36
Clock
-0.36
-3
1.5
p.A
mA
-15
mA
2.88
mA
ti outputs high in tum. At the time of moasuromen~ tho clock Is grounded.
Switching Characteristics Vee = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
From (Input)
To (Output)
RL = 4 kfi, CL = 50 pF
Min
Max
Units
MHz
fMAX
Maximum Clock Frequency
tpHL
Propagation Delay Time
High to Low Level Output
6
CleartoQ
150
ns
tpLH
Propagation Delay Time
Low to High Level Output
Clear to Q
75
ns
tpLH
Propagation Delay Time
Low to High Level Output
Clock to Q or Q
10
75
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clock to Q or Q
10
150
ns
5-16
~National
~ Semiconductor
DM54L74 Dual Positive-Edge-Triggered D Flip-Flops
with Preset, Clear, and Complementary Outputs
General Description
This device contains two independent positive-edge-triggered D flip-flops with complementary outputs. The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse. The triggering occurs at a
voltage level and is not directly related to the transition time
of the rising edge of the clock. The data on the D input
may be changed while the clock is low or high without affecting the outputs as long as the data setup and hold times
are not violated. A low logic level on the preset or clear
inputs will set or reset the outputs regardless of the logic
levels of the other inputs.
Connection Diagram
Oual-In-Llne Package
CLR Z
PR Z
13
ilz
Q2
10
I
-
>
>
I
iiI
TL/F/6631-1
Order Number OM54L74J or OM54L74W
See NS Package Number J14A or W14B
Function Table
Inputs
Outputs
PR
CLR
CLK
0
Q
Q
L
H
L
H
H
H
H
L
L
H
H
H
X
X
X
X
X
X
t
t
H
L
H
L
H"
H
L
L
H
H"
L
H
X
00
00
L
H = High Logic Level
X = EHher Low or High Logic Level
L = Low logic Level
t = Positive-going transition.
00 = The oulputloglc level of 0 before the indicated input conditions were
established.
• = This configuration Is nonstable; that is, it will not persist when either the
preset and/or clear Inputs returned to their Inactive (high) level.
5-17
•
Absolute Maximum Ratings (Note)
Note: The ''Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
8V
Input Voltage
Operating Free Air Temperature Range
DM54l
-55'Cto
Storage Temperature Range
- 65'C to
5.5V
+ 125'C
+ 150'C
Recommended Operating Conditions
Symbol
DM54L74
Parameter
VCC
Supply Voltage
VIH
High level Input Voltage
VIL
low level Input Voltage
IOH
High level Output Current
IOl
Low level Output Current
fClK
Clock Frequency (Note 2)
tw
Pulse Width (Note 2)
Nom
Max
4.5
5
5.5
2
0
Clock High
75
Clock low
75
Preset low
75
Clear low
tsu
50t
tH
Input Hold Time (Notes 1 & 2)
15t
TA
Free Air Operating Temperature
-55
Note 1: The symbol ( t) indicates the rising edge of the clock pulse is used for reference.
~
2S'C and Vee
~
V
V
0.7
V
-0.2
rnA
2
rnA
6
MHz
ns
75
Input Setup Time (Notes 1 & 2)
Note 2: TA
Units
Min
SV.
5-18
ns
ns
125
'C
Electrical Characteristics
Symbol
over recommended operating free air temperature (unless otherwise noted)
Parameter
Conditions
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
VIL = Max, VIH = Min
VOL
Low Level Output
Voltage
Vee = Min, 10L = Max
VIL = Max, VIH = Min
II
Input Current @ Max
Input Voltage
Vee = Max
VI = 5.5V
IIH
High Level Input
Current
Vee = Max
VI = 2.4V
Min
Typ
(Note 1)
2.4
3.3
Max
V
0.15
0.3
D
100
Clear
300
Preset
200
Clock
200
D
10
Clear
30
Preset
20
Clock
IlL
Low Level Input
Current
Vee = Max
VI = 0.3V
-0.18
Clear
-0.36
Preset
-0.18
Clock
-0.36
Short Circuit
Output Current
Vee
= Max
lee
Supply Current
Vee
= Max (Note 2)
V
/loA
/loA
20
D
los
Units
-3
1.6
mA
-15
mA
3
mA
Nate 1: All typlcals are at Vee = SV, TA = 2S·C.
Nate 2: With all outputs open, Icc Is measured with the Q and (j outputs high in turn. At the time of measurement, the clock input Is grounded.
Switching Characteristics
Symbol
at Vee
Parameter
= 5V and TA = 25'C (See Section 1 for Test Waveforms and Output Load)
RL = 4 kO, CL = 50pF
From (Input)
To (Output)
Min
Max
Units
fMAX
Maximum Clock Frequency
tpLH
Propagation Delay Time
Low to High Level Output
Preset
toO
60
ns
tpHL
Propagation Delay Time
High to Low Level Output
Preset
toO
120
ns
IpLH
Propagation Delay Time
Low to High Level Output
Clear
toO
60
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clear
toO
120
ns
tpLH
Propagation Delay Time
Low 10 High Level Output
Clock to
OorO
10
90
ns
tpHL
Propagation Delay Time
High 10 Low Level Oulput
Clock to
OorO
10
120
ns
6
MHz
•
5-19
~
~
,----------------------------------------------------------------------------,
~National
~ Semiconductor
DM54L93
Decade, Divide-by-12, and Binary Counters
General Description
Features
Each of these monolithic counters contains four masterslave flip-flops and additional gating to provide a divide-bytwo counter and a three-stage binary counter for which the
count cycle length is divide-by-eight.
• Typical power dissipation 16 mW
• Count frequency 15 MHz
To use their maximum count length (decade, divide-bytwelve, or four-bit binary), the B input is connected to the QA
output. The input count pulses are applied to input A and the
outputs are as described in the appropriate truth table.
Connection Diagram
Function Tables
COUNT SEQUENCE
(See Note A)
Dual-In-Llne Package
INPUT
A
QD
14
12
GND
111
Qc
10
INPUT
8
08
9
Output
Count
8
QD
Qc
Q8
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
o
2
3
4
5
6
7
8
9
10
2
R0(1)
RO(2)
11
12
TL/F/6637-1
Order Number DM54L93J or DM54L93W
See NS Package Number J14A or W14B
13
14
15
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
RESET/COUNTTRUTH TABLE (Note B)
Reset Inputs
RO(I)
RO(2)
H
L
X
H
X
L
Output
Qc
L
Qs
L
L
COUNT
COUNT
Note A: Output QA Is connected to Input 8
Note B: H
5-20
= High Level. L = Low Level. X = Don·t Cere.
L
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
Input Voltage
Operating Free Air Temperature Range
- 55·C to
DM54L
Storage Temperature Range
- 65·C to
Note: The "Abso/ute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "£Iectrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
8V
5.5V
+ 125·C
+ 150·C
Recommended Operating Conditions
Symbol
DM54L93
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
Units
Min
Nom
Max
4.5
5
5.5
V
2
VIL
Low Level Input Voltage
IOH
High Level Output Current
IOL
Low Level Output Current
feLK
Clock Frequency (Note 5)
tw
Pulse Width (Note 5)
V
0
0.7
V
-0.2
mA
2
mA
6
MHz
90
A
B
90
Reset
200
tREL
Reset Release time (Note 5)
200
TA
Free Air Operating Temperature
-55
ns
ns
·C
125
Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 1)
2.4
3.4
VOH
High Level Output
Voltage
Vee = Min, 10H = Max
VIL = Max, VIH = Min
VOL
Low Level Output
Voltage
Vee = Min, 10L = Max
VIL = Max, VIH = Min
(Note 4)
Input Current @ Max
Input Voltage
Vee = Max
VI = 5.5V
II
IIH
IlL
High Level Input
Current
Low Level Input
Current
Vee = Max
VI = 2.4V
Vee = Max
VI = 0.3V
los
Short Circuit
Output Current
Vee = Max
(Note 2)
Icc
Supply Current
Vee
=
Max
V
0.15
0.3
Reset
0.1
A
0.2
B
0.2
Reset
10
A
20
B
20
Reset
-0.18
A
-0.36
B
-0.36
-3
Units
V
mA
poP.
mA
-15
mA
5.5
mA
Max (Note 3)
Note 1: All typlcals are at Vee ~ SV, TA = 2S'C.
Note 2: Not more than one output should be shorted at a time.
Note 3: Icc Is measured with all outputs open. RO Inputs grounded following momentary connection to 4.SV and all other inputs grounded.
Note 4: QA outputs are tested at IOL
Note 5: TA = 2S'C and Vee
~
~
max plus the limit value of IlL for the B input. This permits driving the B input while maintaining full fan..,ut capability.
SV.
5-21
Switching Characteristics at Vee =
5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
= 4kO,CL = 50pF
Parameter
From (Input)
To (Output)
RL
fMAX
Maximum Clock Frequency
AtoOA
6
tpLH
Propagation Delay Time
Low to High Level Output
AtoOo
400
ns
tPHL
Propagation Delay Time
High to Low Level Output
AtoQo
400
ns
Symbol
Min
Max
MHz
Logic Diagram
13
O-OA
INPUT A .;.14,;....._ _ _ _-a>CLOCK
K
J
9
O~~Os
INPUT B .;.8_ _ _-+_-a>CLOCK
K
10
J
1......0
o_~OC
CLOCK
K
-
12
J
--<
Of-o-Oo
CLOCK
K
RO(I).~
RO(2) 2
f
TL/F/6637-2
The J and K Inputs shown without connection are lor rel.rence only and are lunctionally at a high level.
5-22
Units
~National
~ Semiconductor
DM54L95 4-Bit Parallel Access Shift Registers
General Description
mode control is high by connecting the output of each flipflop to the parallel input of the previous flip-flop (OD to input
C, etc.) and serial data is entered at input D. The clock input
may be applied simultaneously to clock 1 and clock 2 if both
modes can be clocked from the same source.
Changes at the mode control input should normally be
made while both clock inputs are low; however, conditions
described in the last three lines of the truth table will also
ensure that register contents are protected.
These 4-bit registers feature parallel and serial inputs, parallel output, mode control, and two clock inputs. The registers
have three modes of operation.
Parallel (broadside) load
Shift right (the direction OA toward OD)
Shift left (the direction OD toward 0A)
Parallel loading is accomplished by applying the four bits of
data and taking the mode control input high. The data is
loaded into the associated flip-flops and appears at the outputs after the high-to-Iow transition of the clock-2 input. During loading, the entry of serial data is inhibited.
Shift right is accomplished on the high-to-Iow transition of
clock 1 when the mode control is low; shift left is accomplished on the high-ta-Iow transition of clock 2 when the
Features
• Typical maximum clock frequency 14 MHz
• Typical power dissipation mW
Connection Diagram
Dual-In-Line Package
OUTPUTS
OUTPUTS
...----.-...
INPUT A
OA
14
Os
13
GND
In
12
CLOCK 2
L-SHlFT
(LOAD)
...----.-...
Oc
10
00
9
8
Order Number DM54L95J
orDM54L95W
See NS Package Number
J14AorW14B
<0-
<0-
14
3
SERIAL INPUT 8 INPUT C
INPUT
Vee
6
INPUT D . MODE CLOCK 1
CONTROL R-SHIFT
TLlF/6638-1
Function Table
Inputs
Mode
Control
H
H
H
L
L
L
t
J.
J.
t
t
Clocks
2 (L)
1 (R)
H
X
X
X
J.
J.
L
X
X
L
L
L
H
H
H
J.
J.
L
L
H
L
H
Outputs
Parallel
Serial
X
X
X
X
H
L
X
X
X
X
X
QA
Qs
Qc
QD
X
OAO
OBO
OCO
a
b
c
ODD
d
d
OBn
OAO
H
L
OAO
OAO
OAO
OAO
OAO
OCn
OBO
OAn
OAn
OBn
OBO
OBO
OBO
OBO
ODn
OCO
OBn
OBn
OCO
OCO
OCO
OCO
OCO
A
B
C
D
X
X
X
a
b
c
OBt
X
X
X
X
X
X
X
X
Oct
X
X
X
X
X
X
X
X
ODt
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
d
d
ODO
OCn
OCn
ODO
ODO
ODO
ODO
ODO
tShllling lell requires external conneclion of Os to A, Oc to B, 00 to C. Serial data Is entered at input D.
H = High Level (Steady State), L = Low Level (Steady State), X = Don't Care (Any input, Including transitions).
J. = Transition from high to low level. t = Transition from low to high level.
a, b, c, d, = The level of steady state Input at Inpuls A, B, C, or D, respectively.
OAO, Oso, Oco, 000 = The level of OA, Os, OC, or 00, respectively, before the indicated steady state input conditions were established.
OAn, OSn, CCn, COn = The level of CA, Cs, Oc, or Co, respectively, before the most recent J. transition of the clock.
5-23
II
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
8V
Input Voltage
5.5V
Operating Free Air Temperature Range
DM54L
- 55·C to + 125·C
Storage Temperature Range
-65·Cto + 150"C
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Recommended Operating Conditions
Symbol
DM54L95
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
Vil
Low Level Input Voltage
10H
High Level Output Current
Units
Min
Nom
Max
4.5
5
5.5
V
V
2
0.7
V
-0.2
mA
10l
Low Level Output Current
fClK
Clock Frequency (Note 1)
0
tW(ClK)
Pulse Width of Clock (Note 1)
90
ns
tsu
Data Setup Time (Note 1)
50
ns
tEN
TIme to Enable
Clock (Note 1)
Clock 1
120
ns
Clock 2
100
ns
ns
I
I
tH
Data Hold Time (Note 1)
0
tiN
TIme to Inhibit Clock 1 or Clock 2 (Note 1)
0
mA
MHz
ns
-55
Free Air Operating Temperature
TA
Note 1: TA = 25"C and Vee = 5V.
2
6
·C
125
Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 1)
2.4
3.1
Max
VOH
High Level Output
Voltage
VCC = Min,loH = Max
VIL = Max, VIH = Min
VOL
Low Level Output
Voltage
VCC = Min, IOL = Max
VIL = Max, VIH = Min
II
Input Current @ Max
Input Voltage
VCC = Max
VI = 5.5V
Mode
0.2
Others
0.1
High Level Input
Current
Vee = Max
VI = 2.4V
Mode
20
Others
10
Low Level Input
Current
VCC = Max
VI = 0.3V
Mode
-0.36
Others
-0.18
Short Circuit
Output Current
Vcc = Max
(Note 2)
IIH
IlL
los
0.13
-3
Units
V
0.3
-15
V
mA
p.A
mA
mA
Supply Current
8
mA
4.8
Vcc = Max (Note 3)
lee
Note 1: All typical. are at Vee = 5V. TA 25'C
Note 2: Not more than one oulput should be shorted al a lime.
Note 3: lee Is measured with all oulpuls and sBfiallnput open; A, B, C, and 0 Inpuls grounded; mode control at 4.5V; and a momentary 3V, then ground, applied to
both clock Inputs.
5-24
Switching Characteristics at Vee =
From (Input)
To (Output)
Parameter
Symbol
5V and T A 25'C (See Section 1 for Test Waveforms and Output Load)
RL
= 40,CL = 50pF
Min
Max
Units
6
fMAX
Maximum Clock Frequency
tpLH
Propagation Delay Time
Low to High Level Output
Clock to
Output
MHz
90
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clock to
Output
90
ns
Logic Diagram
DATA INPUTS
A
IIODE
c
B
8
~OL---1~;~~.~~----';------------';------------';~--------~
~~--~----r---~
~c:'~
___
8 __-L..J
CLOCK
12
10
Oc
CIa
OUTPUTS
TLIF/6638-2
•
5-25
~National
~ Semiconductor
DM54L98 4-Bit Storage Register
General Description
Absolute Maximum Ratings (Note)
This data selector/storage register is composed of four S-R
master-slave flip-flops, four AND-OR INVERT gates, one
buffer, and six inverter/drivers.
When the word select input is low, word 1 (A1, 81, C1, D1)
is applied to the flip-flops. A high level input to word select
will cause the selection of word 2 (A2, 82, C2, D2). The
selected word is shifted to the output terminals on the negative-going edge of the clock pulse.
Typical clock frequency is 12 MHz.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
8V
Input Voltage
5.5V
Operating Free Air Temperature Range
DM54L
-55'Cto + 125'C
-65'C to + 150'C
Storage Temperature Range
Note: The "Abso/ute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operatiOn.
Connection Diagram
Logic Diagram
Dual-In-Llne-Package
~6
15
14
13
12
11
10
9
1
A2
2
AI
3
Bl
4
5
6
B2
Cl
C2
7
D2
1
6
OND
INPUTS
TLlF/6639-1
Order Number DM54L98J or DM54L98W
See NS Package Number J16A or W16A
1:>-___.....1
CLOCK ;...(1""0)_ _ _ _ _ _ _
TL/F/6639-2
5-26
Recommended Operating Conditions
Symbol
DM54L98
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
Vil
Low Level Input Voltage
10H
High Level Output Current
Nom
Max
4.5
5
5.5
V
V
2
10l
Low Level Output Current
felK
Clock Frequency (Note 4)
0
tw
Clock Pulse Width (Note 4)
100
tsu
Setup Time (Note 4)
Data High
100
Data Low
120
Select High
150
Select Low
TA
Units
Min
V
mA
2
mA
6
MHz
65
ns
ns
100
-55
Free Air Operating Temperature
0.7
-0.2
·C
125
Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
Conditions
Min
2.4
VOH
High Level Output Voltage
Vee = Min, 10H = Max
Vil = Max, VIH = Min
VOL
Low Level Output Voltage
Vee = Min, 10l = Max,
Vil = Max, VIH = Min
II
Input Current @ Max Input Voltage
= Max, VI = 5.5V
Vee = Max, VI = 2.4V
Vee = Max, VI = O.SV
Vee = Max (Note S)
Vee = Max (Note 2)
IIH
High Level Input Current
IlL
Low Level Input Current
los
Short Circuit Output Current
Typ
(Note 1)
Max
V
0.15
Vee
-S
Supply Current
Icc
Note 1: All typlcals are al Vee = 5V, TA = 25'C.
Note 2: Icc Is measured wllh all oulpule open and all Inpuls grounded.
Note 3: Not more than one output should be shorted at a time.
Note 4: TA = 25'C and Vee = 5V.
Units
6
O.S
V
0.1
mA
10
/LA
-0.18
mA
-15
mA
8
mA
Switching Characteristics at Vee = 5V and TA = 25·C (See Section 1 for Test Waveforms and Output Load)
RL = 4kO,CL = 50pF
From (Input)
Symbol
Parameter
To (Output)
Min
Max
6
Units
fMAX
Maximum Clock Frequency
tplH
Propagation Delay Time
Low to High Level Output
Clock to
Output
80
ns
tpHL
Propagation Delay Time
High to Low Level Output
Clock to
Output
100
ns
5-27
MHz
~National
~ Semiconductor
93lDD
4-Bit Universal Shift Register
General Description
Features
The 93LOO is a 4-bit universal shift register. As a high speed
multifunctional sequential logic block, it is useful in a wide
variety of register and counter applications. It may be used
in serial-serial, shift left, shift right, serial-parallel, parallelserial, and parallel-parallel data register transfers.
• Asynchronous master reset
• J, K inputs to first stage
Connection Diagram
Logic Symbol
6i i j J
Dual-In-Llne Package
ijR-l
J- 2
16 r-Vcc
15 r-QO
R- 3
141-Ql
PO- 4
131-Q2
Pl- 5
12 -Q3
P2- 6
11 -Q3
P3- 7
10 -CP
GND- 8
9-i'E
PE PO PI P2 P3
2- J
10- CP
Q3P-ll
3~K
MR QO Ql Q2 Q3
TLlF/9576-2
vee = Pin 16
GND = PinS
TLlF/9576-1
Order Number 93LOODMQB or 93LOOFMQB
See NS Package Number J16A or W16A
Pin Names
PE
PO-P3
J
K
CP
MR
QO-Q3
03
Description
Parallel Enable Input (Active LOW)
Parallel Inputs
First Stage J Input (Active HIGH)
First Stage K Input (Active LOW)
Clock Pulse Input (Active Rising Edge)
Master Reset Input
Parallel Outputs
Complementary Last Stage Output
5-28
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
Operating Free Air Temperature Range
MIL
-65'Cto
5.5V
+ 125'C
Recommended Operating Conditions
Symbol
93LOO(MIL)
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
Units
Min
Nom
Max
4.5
5
5.5
V
0.7
V
V
2
IOH
High Level Output Voltage
-0.4
mA
IOL
Low Level Output Current
4.8
mA
TA
Free Air Operating Temperature
125
'C
ts (H)
ts (L)
Setup Time HIGH or LOW,
J, K and PO-P3 to CP
60
60
ns
th (H)
Ih (L)
Hold Time HIGH or LOW,
J, K and PO-P3 to CP
0
0
ns
Is (H)
ts (L)
Setup Time HIGH or LOW,
PEtoCP
68
68
ns
th (H)
th (L)
Hold Time HIGH or LOW,
PEtoCP
0
0
ns
tw(H)
Iw(L)
CP Pulse Width
HIGH or LOW
38
38
ns
tw(L)
MR Pulse Width LOW
53
ns
tree
Recovery Time, MR to CP
70
ns
-55
•
5-29
Electrical Characteristics
Over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
VI
Input Clamp Voltage
Vee = Min,ll = -10 mA
VOH
High Level Output Voltage
Vee = Min, 10H = Max,
Vil = Max, VIH = Min
Val
Low Level Output Voltage
Vee = Min, 10l = Max,
VIH = Min, Vil = Max
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 5.5V
IIH
High Level Input Current
Vee = Max, VI = 2.4V
Vee = Max, VI = 0.3V
Low Level Input Current
III
Short Circuit
Output Current
los
Min
2.4
Typ
(Note 1)
Max
Units
-1.5
V
3.4
V
0.3
V
1
mA
Inputs
20
CP
40
PE
46
Inputs
-400
CP
-800
PE
-920
Vee = Max
(Note 2)
-2.5
Supply Current
Vee = Max
lee
Note 1: All typical. are at Vee = SV. TA = 2s'e.
Note 2: Not more Ihan one output should be shorted al a time, and the duration should nol exceed one second.
/kA
/kA
-25
mA
23
mA
Switching Characteristics
Vee =
+ 5.0V, TA = + 25°C (See Section 1 for waveforms and load configurations)
93L
Symbol
CL = 15pF
Parameter
Min
Units
Max
fmax
Maximum Shift Frequency
10
tplH
tpHl
Propagation Delay
CPtoQn
35
51
ns
tpHl
Propagation Delay, MA to Qn
60
ns
5-30
MHz
r-------------------------------------------------------------------------------------~
Functional Description
When the PE input is lOW, the 93100 appears as four common clocked D flip-flops. The data on the parallel inputs
PO-P3 is transferred to the respective 00-03 outputs following the lOW-to-HIGH clock transition. Shift left operation (03 - 02) can be achieved by tying the an outputs to
the Pn-1 inputs and holding the PE input lOW.
All serial and parallel data transfers are synchronous, occuring after each lOW-ta-HIGH clock transition. Since the
93100 utilizes edge triggering, there is no restriction on the
activity of the J, K, Pn and PE inputs for logic operation-except for the setup and release time requirements. A lOW on
the asynchronous Master Reset (MR) input sets all 0 outputs lOW, independent of any other input condition.
The logic Diagrams and Truth Table indicate the functional
characteristics of the 93100 4-bit shift register. The device is
useful in a wide variety of shifting, counting and storage
applications. It performs serial, parallel, serial-to-parallel, or
parallel-to-serial data transfers.
The 93100 has two primary modes of operation, shift right
(00 - 01) and parallel load, which are controlled by the
state of the Parallel Enable (PE) input. When the PE input is
HIGH, serial data enters the first flip-flop 00 via the J and K
inputs and is shifted one bit in the direction
00 - 01 - 02 - 03 following each lOW-to-HIGH
clock transition. The JK inputs provide the flexibility of the
JK type input for special applications, and the simple D-type
input for general applications by tying the two pins together.
U)
Co:!
b
o
Truth Table
Operating
Mode
Inputs (MR = H)
Outputs
@
tn + 1
PE
J
K
PO
P1
P2
P3
QO
Q1
Q2
Q3
Q3
Shift Mode
H
H
H
H
l
l
H
H
l
H
l
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
l
00
00
H
00
00
00
00
01
01
01
01
02
02
02
02
02
02
02
02
Parallel
Entry Mode
l
l
X
X
X
X
l
H
l
H
l
H
l
H
l
H
l
H
l
H
l
H
H
l
'tn+1 ~ Indicates state after next LOW·to·HIGH clock transilion.
H = HIGH Voltage Level
L ~ LOW Voltage Level
X = Immaterial
•
5-31
o ,----------------------------------------------------------------------,
9
CO)
CD
Logic Diagram
..,
10
~----~---------~
rr---::=:::::...l...-------I-~
lit'
1><
5-32
I~
~--------------------------------------------------------------------------~
U)
Co)
b
.....
~National
~ Semiconductor
93L01
1-of-10 Decoder
General Description
Features
The 93101 multipurpose decoders are designed to accept
four inputs and provide ten mutually exclusive outputs.
•
•
•
•
Connection Diagram
Logic Symbol
Multifunction capability
Mutually exclusive outputs
Demultiplexing capability
Typical power dissipation of 45 mW
Ii
Dual-In-llne Package
A2-1
A3- 2
05- 3
06- 4
07- 5
08- 6
'-'
AD
16 I-Vcc
15 I-AO
14 -AI
09- 7
13 -00
12 -01
11-02
10 -03
GND- 8
9 -04
Al
A2
i
A3
00 01 02 03 04 05 06 07 08 09
TLIFI95B3-2
vcc
GND
TLlF195B3-1
= Pin 16
=
Pin 8
Order Number 93L01DMQB or 93L01FMQB
See Package Number J16A or W16A
Pin Names
AO-AS
50-59
Description
Address Inputs
Decoder Outputs (Active lOW)
LI
5·33
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
Operating Free Air Temperature Range
MIL
-55·C to
-65·Cto
Storage Temperature Range
5.5V
+ 125·C
+ 150·C
Recommended Operating Conditions
Symbol
93101 (Mil)
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
Units
Min
Nom
Max
4.5
5
5.5
V
2
V
VIL
Low Level Input Voltage
IOH
High Level Output Current
-400
V
p.A
IOL
Low Level Output Current
4.8
mA
TA
Free Air Operating Temperature
125
·c
0.7
-55
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
=
=
Min
Typ
(Note 1)
Max
Units
-1.5
V
VI
Input Clamp Voltage
Vee
VOH
High Level Output
Voltage
Vee = Min, IOH = Max,
VIL = Max, VIH = Min
VOL
Low Level Output
Voltage
Vee = Min, IOL = Max,
VIH = Min, VIL = Max
II
Input Current @ Max
Input Voltage
Vee
=
Max, VI
=
5.5V
=
=
=
Max, VI
=
=
2.4V
20
p.A
0.3V
-400
p.A
-25
mA
=
Max (Note 3)
13
mA
Min,ll
IIH
High Level Input Current
Vee
IlL
Low Level Input Current
Vee
los
Short Circuit
Output Current
Max
Vee
(Note 2)
lee
Supply Current
Vee
Max, VI
-10 mA
V
2.4
0.3
V
1
-2.5
mA
Nol. 1: All typical. are at Vcc = 5V. TA = 25"C.
Note 2: Nol more than one output should be shorted at a time. and the duration should not exceed one second.
Nol. 3: ICC is measured with all outputs open and all Inputs grounded.
Switching Characteristics
Vee
= + 5.0V, TA = + 25·C (See Section 3 for waveforms and
Symbol
load configurations)
CL
Parameter
Min
tpLH
tpHL
Propagation Delay
An to On
=
15pF
Units
Max
36
36
5·34
ns
r---------------------------------------------------------------------------------,
Functional Description
The 93L01 decoder accepts four active HIGH BCD inputs
and provides ten mutually exclusive active LOW outputs, as
shown by logic symbol or diagram. The active LOW outputs
facilitate addressing other MSI units with active LOW input
enables. The logic design of the 93L01 ensures that all out-
puts are HIGH when binary codes greater than nine are
applied to the inputs. The most significant input A3 produces a useful inhibit function when the 93L01 is used as a
1-ot-8 decoder.
U)
w
b
....
Truth Table
Inputs
outputs
AO
A1
A2
A3
00
01
02
03
04
05
06
07
08
09
L
H
L
H
L
L
H
H
L
L
L
L
L
L
L
L
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
L
H
L
L
H
H
H
H
H
H
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
H
H
H
H
L
H
L
H
L
L
H
H
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
H
H
L
H
L
H
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H = HIGH Voltage Level
L = LOW Voltage Level
Logic Diagram
Al
AD
I
A3
c
C)
l
)7
I
A2
I
I
II
I
I
I-
Jl
LI
YYYYYYYYYY
00
02
04
05
06
07
08
09
TL/F/9593-3
II
5-35
~National
~ Semiconductor
93l0S
Dual 4-Bit latch
General Description
The 93l0e is a dual 4-bit D-type latch designed for general
purpose storage applications in digital systems. Each latch
contains both an active lOW Master Reset input and active
lOW Enable inputs.
Connection Diagram
Logic Symbol
Dual-In-Llne Package
3 "
i.iR
Vee
EOa
Q3b
Ela
D3b
DDa
Q2b
QOa
D2b
Dla
Qlb
Qla
Dlb
D2a
QOb
Q2a
DOb
D3a
[lb
Q3a
[Db
GND
i.iRb
6
8 10
4-BIT LATCH 2
4-BIT LATCH 1
1 5
7
13 17 19 21 23
9 11
TL/F/9594-2
vee = Pin 24
GND = Pin
TUF/9594-1
Order Number 93L08DMQB or 93L08FMQB
See NS Package Number J24A or W24C
Pin Names
DeSCription
DOa-D3a}
DOb-D3b
EOa, E1 a, EOb, E1 b,
MRa,MRb
AND Enable Inputs (Active lOW)
Master Reset Inputs (Active lOW)
OOa-03a}
OOb-03b
Parallel latch Inputs
Parallel latch Outputs
5-36
12
Absolute Maximum Ratings
(Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
Mil
- 55·C to
Storage Temperature Range
-65·Cto
+ 125·C
+ 150·C
Recommended Operating Conditions
Symbol
Parameter
Min
Nom
Max
Units
4.5
5
5.5
V
0.7
V
Vee
Supply Voltage
VIH
High level Input Voltage
VIL
low level Input Voltage
10H
High level Output Current
-400
p.A
IOL
low level Output Current
4.8
rnA
125
·C
V
2
-55
TA
Free Air Operating Temperature
ts(H)
Setup Time HIGH, On to En
8
ns
th(H)
Hold Time HIGH, On to En
1
ns
ts (l)
Setup Time lOW, On to En
18
ns
th (l)
Hold Time lOW, On to En
4
ns
tw(l)
En Pulse Width lOW
32
ns
tw(l)
MR Pulse Width lOW
30
ns
tree
Recovery Time, MR to En
10
ns
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
VI
Input Clamp Voltage
Vee = Min, II = -10 rnA
VOH
High level Output Voltage
Vee = Min, 10H = Max,
VIL = Max, VIH = Min
VOL
low level Output Voltage
Vee = Min, 10L = Max,
VIH = Min, VIL = Max
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 5.5V
IIH
High level Input Current
Vee = Max, VI = 2.4V
IlL
lOS
low level Input Current
Short Circuit
Output Current
Vee = Max, VI = 0.3V
Vee = Max (Note 2)
Min
Max
Units
-1.5
V
V
2.4
0.3
V
1
rnA
Inputs
20
On
30
Inputs
-400
On
-640
-2.5
Supply Current
Vee = Max (Note 3)
lee
Note 1: All typicals are at Vee ~ Sv. TA ~ 2S·C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: ICC is measured with all outputs open and all inputs grounded.
5-37
Typ
(Note 1)
p.A
p.A
-25
rnA
29
rnA
Switching Characteristics
Vee =
+ 5.0V, TA = + 25°C (See Section 3 for waveforms and load configurations)
Symbol
CL
Parameter
=
15pF
Min
Units
Max
tpLH
tpHL
Propagation Delay
"EntoOn
45
38
ns
tpLH
tpHL
Propagation Delay
DntoOn
27
29
ns
tpHL
Propagation Delay
MRtoOn
30
Functional Description
Truth Table
EO
E1
MR
Data can be entered into the latch when both of the enable
inputs are lOW. As long as this logic condition exists, the
output of the latch will follow the input. If either of the enable
inputs goes HIGH, the data present in the latch at that time
is held in the latch and is no longer affected by data input.
The master reset overrides all other input conditions and
forces the outputs of all the latches lOW when a lOW signal is applied to the Master Reset input.
D
On
Operation
l
H
l
l
H
X
On-1
Data Entry
Data Entry
Hold
l
X
X
X
On-1
On-1
H
H
H
l
l
l
H
H
H
H
H
X
X
l
On-1
ns
l
l
l
Hold
Hold
Reset
~
Previous Output State
an ~ Present Output State
H ~ HIGH Voltage Level
L ~ LOW Voltage Level
X ~ Immaterial
Logic Diagram
DO
01
02
03
EO El
TLlF/9594-3
5-38
r--------------------------------------------------------------------------------,U)
Co)
i
J?'A National
~ Semiconductor
93109
Dual 4-lnput Multiplexer
General Description
Features
The 93109 monolithic dual 4-input digital multiplexers consist of two multiplexing circuits with common input select
logic. Each circuit contains four inputs and fully buffered
complementary outputs. In addition to multiplexer operation,
the 93109 can generate any two functions of three variables. Active pullups in the outputs ensure high drive and
high speed performance. Because of its high speed performance and on-chip select decoding, the 93109 may be
cascaded to multiple levels so that any number of lines can
be multiplexed onto a single output bus.
• Multifunction capability
• On-chip select logic decoding
• Fully buffered complementary outputs
Connection Diagram
Logic Symbol
Dual·ln·Llne Package
Zb- 1
'-/
Zb- 2
16 I-Vcc
151-Za
51- 3
14 I-Za
10b- 4
13 1-50
I1b- 5
121-IOa
12b- 6
11i-l1a
13b- 7
10 i-12a
GND- 8
9i-13a
IDa l1a 12a 13a lOb 11b 12b 13b
13-50
3-51
Za
Pin Names
IOb-13b
Zb
Zb
Zb
TL/F/9602-2
TL/F/9602-1
Za
Zb
vee = Pin 16
GND = PinS
Order Number 93L09DMQB or 93L09FMQB
See NS Package Number J16A or W16A
SO,S1
IOa-13a
Za
Za
Description
Common Select Inputs
Multiplexer A Inputs
Multiplexer A Output
Complementary Multiplexer A Output
Multiplexer B Inputs
Multiplexer B Output
Complementary Multiplexer B Output
5-39
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
- 55·C to + 125·C
MIL
Storage Temperature Range
- 65·C to + 150·C
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Recommended Operating Conditions
Symbol
93L09(MIL)
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
Units
Min
Nom
Max
4.5
5
5.5
V
0.7
V
2
V
IOH
High Level Output Current
-400
/loA
IOL
Low Level Output Current
4.8
mA
TA
Free Air Operating Temperature
125
·c
-55
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
VI
Input Clamp Voltage
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
II
Input Current @ Max
Input Voltage
IIH
High Level Input Current
IlL
Low Level Input Current
loS
Short Circuit
Output Current
Conditions
= Min. II = -10mA
Vee = Min, IOH = Max,
VIL = Max, VIH = Min
Vee = Min, IOL = Max,
VIH = Min, VIL = Max
Vee = Max, VI = 5.5V
Min
Vee
= Max, VI = 2.4V
Vcc = Max, VI = 0.3V
Vee = Max (Note 2)
Max
Units
-1.5
V
2.4
Vee
-10
Supply Current
Icc
Vee = Max
Nole 1: All typical. are at Vee = 5V, TA = 25"C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
5-40
Typ
(Note 1)
V
0.3
V
1
mA
20
/loA
-400
/loA
-40
mA
11.5
mA
Switching Characteristics Vee =
Symbol
+5.0V, TA = +25°C
CL = 15pF
Parameter
Min
Units
Max
tpLH
tpHL
Propagation Delay
So to
70
60
ns
tpLH
tpHL
Propagation Delay
Sa toZ•
55
50
ns
tpLH
tpHL
Propagation Delay
10 to Z.
70
65
ns
tpLH
tpHL
Propagation Delay
SatoZa
40
60
ns
z.
Functional Description
Truth Table
The 93L09 dual 4-input multiplexers are able to select two
bits of either HIGH or LOW data or control from up to four
sources, in one package. The 93L09 is the logical implementation of two-pole, four-position switch, with the pOSition
of the switch being set by the logic levels supplied to the
two select inputs. Both assertion and negation outputs are
provided for both multiplexers. The logic equations for the
outputs are shown below:
Select
Inputs
+ 11aoSI 0 SO + 12a 0 51 - SO + 13aoSI - SO
lOb-51 - SO + lib -SI -SO + 12a 0 51 - SO + 13bo 51 0 so
Zb ~
The 93L09 is frequently used to move data from a group of
registers to a common output bus. The particular register
from which the data came would be determined by the state
of the select inputs. A less obvious application is as a function generator. The 93L09 can generate two functions of
three variables. This is useful for implementing random gating functions.
Outputs
(a or b)
51
10
11
12
13
Z
Z
L
L
H
H
L
L
L
L
L
H
X
X
X
X
L
H
X
X
X
X
X
X
X
X
L
H
L
H
H
L
H
L
L
L
H
H
H
H
H
H
X
X
X
X
X
X
X
X
L
H
X
X
X
X
L
H
L
H
L
H
H
L
H
L
~
HIGH voltage level
LOW voltage level
Immaterial
50
Za ~ lOa 0 510 SO
Inputs
(a or b)
H
L
~
x
~
Logic Diagram
IDa
SO
-I
Sl
-I
-I
l1a
12a
13a
I I
lOb
I1b
12b
13b
I I
I J (LLJ{ 11LL) I llLL)( 1ILL)
'L1P
L¥
,)
\)
-
c
j
Zs
5-41
is
-
Zb
ib
TL/F/9602-3
c .-------------------------------------------------------------------------,
.....~ ~National
c• ~ Semiconductor
.....
C")
G)
93L10/93L16
BCD Decade Counter14-Bit Binary Counter
General Description
Features
The 9311 0 is a high speed synchronous BCD decade counter and the 93116 is a high speed synchronous 4-bit binary
counter. They are synchronously presettable. multifunctional MSI building blocks useful in a large number of counting.
digital integration and conversion applications. Several
states of synchronous operation are obtainable with no external gating packages required through an internal carry
lookahead counting technique.
•
•
•
•
Connection Diagram
Logic Symbol
Synchronous counting and parallel entry
Decoded terminal count
Built-in Carry Circuitry
Easy interfaCing with DTl. lPDTl. and TIL families
! iii i
Dual-In-llne Package
'-/
Pl- 4
P2- 5
16 '-Vee
15 r-TC
14 r-OO
13 r-Ol
12 r-02
P3- 6
CEP- 7
111-03
10 I-CET
GND- 8
91-iiE
t.iR-l
CP- 2
po- 3
PE PO PI P2 P3
7 - CEP
10- CET
TC r--15
2-CP
MR 00 01 02 03
11~ ,~ ,~
TLlF/9603-2
Vee = Pin 16
GND = PinS
TLIFI9603-1
Order Number 93l 10DMQB, 93l10FMQB,
93l16DMQB or 93l16FMQB
See NS Package Number J16A or W16A
Pin Names
CEP
CET
CP
MR
PO-P3
PE
00-03
TC
,1,
Description
Count Enable Parallel Input
Count Enable Trickle Input
Clock Pulse Input (Active Rising Edge)
Asynchronous Master
Reset Input (Active lOW)
Parallel Data Inputs
Parallel Enable Input (Active lOW)
Flip-Flop Outputs
Terminal Count Output
5-42
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
-55'Cto + 125'C
Mil
Storage Temperature Range
-65'Cto +150'C
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Recommended Operating Conditions
Symbol
93L 10/93L16 (MIL)
Parameter
Vee
Supply Voltage
VIH
High level Input Voltage
VIL
low level Input Voltage
IOH
IOL
~
ro
....
Absolute Maximum Ratings
Units
Min
Nom
Max
4.5
5
5.5
2
V
V
0.7
V
High level Output Voltage
-400
p.A
low level Output Current
4.8
mA
125
'C
-55
TA
Free Air Operating Temperature
ts(H)
taIL)
Setup Time HIGH or lOW
PntoCP
75
75
ns
th(H)
th(l)
Hold Time HIGH or lOW
Pnto CP
10
10
ns
ts(H)
ts(l)
Setup Time HIGH or lOW
PEtoCP
(Note 2)
53
ns
th(H)
th(l)
Hold Time HIGH or lOW
PE to CP
7.0
(Note 2)
ns
ts(H)
ts(l)
Setup Time HIGH or lOW
CEP or CETto CP
26
(Note 1)
ns
th(H)
th(l)
Hold Time HIGH or lOW
CEP or CET to CP
(Note 1)
10
ns
tw(H)
twILl
CP Pulse Width
25
25
ns
twILl
MR Pulse Width lOW
65
ns
Recovery Time, MR to CP
30
ns
Nate 1: The Setup Time '"!s(l)'" and Hold Time '"",(H)'" between the Count Enable (CEP and CET) and the Clock (CP) indicate that the HIGH-to-LOW transition of
the CEP and CET must occur only while the Clock is HIGH for conventional operation.
Nate 2: The Setup Time '"!s(H)'" and Hold Time '"th(l)'" between the Parallel Enable (i5E) and Clock (CP) indicate that the lOW-Io-HIGH transition of the PE must
occur only while the Clock is HIGH for conventional operation.
tree
5-43
•
~
r-
....
Q)
CD
..-
...J
C')
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
G)
•
Q
..-
...J
C')
G)
Symbol
Parameter
Conditions
=
=
VI
Input Clamp Voltage
Vee
VOH
High Level Output Voltage
Vee = Min, 10H = Max,
VIL = Max, VIH = Min
VOL
Low Level Output Voltage
Vee = Min, 10L = Max,
VIH = Min, VIL = Max
II
Input Current @ Max
Input Voltage
Vee
=
Max, VI
=
5.5V
IIH
High Level Input Current
Vee
=
Max, VI
=
2.4V
Min,ll
Min
Typ
(Note 1)
-10 mA
2.4
Low Level Input Current
Vee
=
Max, VI
=
0.3V
los
Short Circuit
Output Current
Vee
=
Max (Note 2)
Icc
Supply Current
Vee
=
Max
Nole 1: All typicals are at Vee
Units
-1.5
V
V
3.4
Inputs
0.3
V
1
mA
20
CET,CP,PE
IlL
Max
40
",A
Pn
13.3
Inputs
-400
CET,CP, PE
-800
Pn
-267
-2.5
",A
-25
mA
27.5
mA
= 5V, TA = 25"C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Switching Characteristics
Vee
= + 5.0V, TA = + 25°C (See Section 1 for waveforms and load configurations)
Symbol
CL
Parameter
Min
=
15pF
Units
Max
fmax
Maximum Count Frequency
13
MHz
IpLH
tpHL
Propagation Delay
CPtoQ
32
39
tpLH
tpHL
Propagation Delay
CPtoTC
66
tpLH
tpHL
Propagation Delay
CETtoTC
35
30
ns
tpHL
Propagation Delay, MR to Q
72
ns
30
5-44
ns
ns
, - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - , U)
Functional Description
The 93L10 counts modul0-10 in the BCD (8421) sequence.
From state 9 (HLLH) it increments to state 0 (LLLL). The
93L 16 counts modulo-16 in binary sequence. From state 15
(HHHH) it increments to state 0 (LLLL). The clock inputs of
all flip-flops are driven in parallel through a clock buffer.
Thus all changes of the Q outputs (except due to Master
Reset) occur as a result of, and synchronous with, the LOWto-HIGH transition of the CP input signal. The circuits have
four fundamental modes of operation, in order of precedence: asynchronous reset, parallel load, count-up and
hold. Four control inputs-Master Reset (MRI, Parallel Enable (PE), Count Enable Parallel (CEP) and Count Enable
Trickle (CEn-determine the mode of operation, as shown
in the Mode Select Table. A LOW Signal on MR overrides all
other inputs and asynchronously forces all outputs LOW. A
LOW signal on PE overrides counting and allows information on the Parallel Data (Pn) inputs to be loaded into the
flip-flops on the next rising edge of CPo With PE and MR
HIGH, CEP and CET permit counting when both are HIGH.
Conversely, a LOW signal on either CEP or CET inhibits
counting.
The 93L10 and 93L16 contain masterslave flip-flops which
are "next-state catching" because of the JK feedback. This
means that when CP is LOW, information that would change
the state of a flip-flop, whether from the counting logic or
the parallel entry logiC if either mode is momentarily enabled, enters the master and is locked in. Thus to avoid
inadvertently changing the state of a master latch, and the
subsequent transfer of the erroneous information to the
slave when the clock rises, it is necessary to insure that
neither the counting mode, nor the parallel entry mode is
momentarily enabled while CP is LOW.
spikes due to internal race conditions and is therefore not
recommended for use as a clock or asynchronous reset for
flip-flops, counters or registers. If a decade counter is preset
to an illegal state, or assumes an illegal state when power is
applied, it will return to the normal sequence within two
counts, as shown in the state diagrams.
.-....w
o
•
w
.....
U)
en
MULTISTAGE COUNTING
The '10/'16 counters may be cascaded to provide multistage synchronous counting. Two methods commonly used
to cascade these counters are shown in Figures 8 and b.
In multistage counting, all less significant stages must be at
their terminal count before the next more significant counter
is enabled. The '10/'16 internally decodes the terminal
count condition and "AN Os" it with the CET input to generate the terminal count (TC) output. This arrangement allows
one to perform series enabling by connecting the TC output
(enable signal) to the CET input of the following stage, Figure 8. The setup requires very few interconnections, but has
the following drawback: since it takes time for the enable to
ripple through the counter stages, there is a reduction in
maximum counting speed. To increase the counting rate, it
is necessary to decrease the propagation delay of the TC
signal, which is done in the second method.
The scheme illustrated in Figure b permits multistage counting, limited by the fan-out of the terminal count. The CEP
input of the '10/'16 is internally "ANDed" with the CET input
and as a result, both must be HIGH for the counter to be
enabled. The CET inputs are connected as before except
for the second stage. There the CET input is left floating and
is therefore HIGH. Also, all CEP inputs are connected to the
terminal output of the first stage. The advantage of this
method is best seen by assuming all stages except the second and last are in their terminal condition. As the second
stage advances to its terminal count, an enable is allowed
to trickle down to the last counter stage, but has the full
cycle time of the first counter to reach it. Then as the TC of
the first stage goes active (HIGH), all CEP inputs are activated, allowing all stages to count on the next clock.
The Terminal Count (TC) output is HIGH when CET is HIGH
and the counter is in its maximum count state (9 for the
decade counters, 15 for the binary counters-fully decoded
in both types). To implement synchronous multistage counters, the TC outputs can be used with the CEP and CET
inputs in two different ways. These two schemes are shown
in Figures 8 and b. The TC output is subject to decoding
•
5-45
~
,..
....
~
r-----------------------------------------------------------------------------~
Logic Diagrams
•
o
,..
P1
PO
....
93L10
P2
P2
~
CEP
CET
CP
Q2
Q1
QO
MR
TC
. Q3
TL/F/9603"3
P1
PO
93L16
P2
P2
Pi:
CEP
CET~~----------~~~~~~~----------~::::::::::::::::~====~--)
CP
QO
Q1
Q2
TC
Q3
TUF/9603-4
5-46
~----------------------------------------------------------------------------, ~
Co)
....
....
o
Mode Select Table
Inputs
H
PE
CEP
CET
CP
L
H
H
H
H
X
X
X
X
X
X
.f
L
H
H
H
•
........
Response
MR
L
X
X
Clear; All Outputs LOW
Parallel Load; Pn an
Hold
Hold; TC = LOW
Count Up
X
X
L
H
H
~
Co)
.f
en
= HIGH Voltage Level
L = LOW Voltage Level
X
= Immaterial
Logic Equations
Count Enable = MR • PE • CEP • CET
Terminal Count = CET. 00 • 01 • 02 • 03 ('16)
Terminal Count = CET • 00 • 01 • 02 • 03 (,10)
State Diagrams
93L10
93L16
TL/F/9603-5
TL/F/9603-6
CEP
CEP
CEI 9310 - 9316
TC
CET 9310-9316
CEP
TC
CP
CP
CEP
CET 9310-9316
TC
CP
CEI 9310 - 9316
CEP
TC
CEI 9310 - 9316
CP
TC
CP
l ~~M~clNT
STAGES
CLOCK---------------+-------------+-------------+-------------+-------------+
TL/F/9603-7
FIGURE a_ Synchronous Multistage Counting Scheme (Slow)
CEP
CET 9310-9316
CEP
TC
CET 9310 - 9316
TC
CEI 9310-9316
TC
CEI 9310 -9316
TC
CEI 9310 - 9316
TC
CP
TO MORE
SIGNIFICANT
STAGES
II
-------------t.J
CLOCK-------------....------------....------------....------------....
TLlF/9603-8
FIGURE b_ Synchronous Multistage Counting Scheme (Fast)
5·47
.... ,-------------------------------------------------------------------------,
~
....I
C")
G»
'?A National
~ Semiconductor
93L12
a-Input Multiplexer
General Description
Features
The 93112 is a monolithic, high speed, 8-input digital multiplexer circuit. It provides, in one package, the ability to select qne bit of data from up to eight sources. The 93112 can
be used as a universal function generator to generate any
logic function of four variables. Both assertion and negation
outputs are provided.
• Multifunction capability
• On-chip select logic decoding
• Fully buffered complementary outputs
Connection Diagram
Logic Symbol
Dual-In-llne Package
10- 1
11- 2
12- 3
13- 4
\J
blfiiiiIi
16 '-Vee
15 rZ
11-50
14 ~Z
13 ~S2
14- 5
15- 6
12
11
16- 7
10
rE
GND- 8
9
~17
12-51
13-52
~SI
~SO
Order Number 93l12DMQB or 93l12FMQB
See NS Package Number J16A or W16A
Description
Pin Names
E
10-17
Z
Z
Z
!
115
vee = Pin 16
GND=PinB
TL/F/9610-1
SO-52
Z
Select Inputs
Enable Input (Active lOW)
Multiplexer Inputs
Multiplexer Output
Complementary Multiplexer Output
5-48
TLlF/9610-2
CD
Co)
r.....
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
MIL
-55'Cto +125'C
Storage Temperature Range
- 65'C to + 150'C
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "£Iectrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Recommended Operating Conditions
Symbol
93L12 (MIL)
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
Units
Min
Nom
Max
4.5
5
5.5
V
2
V
0.7
V
10H
High Level Output Current
-400
poA
10L
Low Level Output Current
4.6
mA
TA
Free Air Operating Temperature
125
'C
-55
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
VI
Input Clamp Voltage
Vee = Min,ll = -10 mA
VOH
High Level Output Voltage
Vee = Min, 10H = Max,
VIL = Max, VIH = Min
VOL
Low Level Output Voltage
Vee = Min, 10L = Max,
VIH = Min, VIL = Max
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 5.5V
Min
2.4
Typ
(Note 1)
Max
Units
-1.5
V
3.4
V
0.3
V
1
mA
IIH
High Level Input Current
Vee = Max, VI = 2.4V
20
poA
IlL
Low Levell nput Current
Vee = Max, VI = 0.3V
-400
poA
los
Short Circuit Output Current
Vee = Max (Note 2)
-25
mA
13.3
mA
-2.5
Supply Current
Vee = Max (Note 3)
ICC
Note 1: All typlcals are at Vee = 5V, TA = 25'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: lee Is measured with all outputs open and all inputs grounded.
5-49
N
Switching Characteristics
Vee
=
+5.0V, TA
=
+25"C (See Section 1 for waveforms and load configurations)
Symbol
CL
Parameter
= 15pF
. Min
Units
Max
tpLH
tpHL
Propagation Delay
SOtoZ
60
75
ns
tpLH
tpHL
Propagation Delay
SOtoZ
70
50
ns
tpLH
tpHL
Propagation Delay
EtoZ
60
75
ns
tpLH
tpHL
Propagation Delay
"EtoZ
70
45
ns
tpLH
tpHL
Propagation Delay
IntoZ
70
65
ns
tpLH
tpHL
Propagation Delay
IntoZ
55
55
ns
Functional Description
The 93L12 provides the ability, in one package, to select
from eight sources of data or control information. By proper
manipulation of the inputs, the 93L12 can provide any logic
function of four variables and its negation. Thus any number
of random logic elements used to generate unusual truth
tables can be replaced by one 93L12.
The 93L12 is a logical implementation of a single pole, eight
position switch with the switch position controlled by the
state of three Select inputs, SO, 51, 52. Both assertion and
negation outputs are provided. The Enable input (E) is active LOW. When it is not activated the negation output is
HIGH and the assertion output is LOW, regardless of all
other inputs. The logic function provided at the output is:
Z = E • (10 • SO • 51 .52 + 11 • SO • 51 • 52
+ 12 • 50 •
+ 14 .50 •
+ 16. 50 •
+ 17 • SO •
51
51
51
51
•
•
•
•
52 + 13 • SO • 51 • 52
52 + 15 • SO • 51 • 52
52
52).
Truth Table
Inputs
-
Outputs
E
S2
S1
SO
10
11
12
13
14
15
16
17
Z
Z
H
L
L
L
X
X
X
X
L
L
L
L
L
L
L
L
H
L
H
X
X
X
X
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
L
H
L
L
H
L
L
L
L
L
L
L
L
L
L
X
X
H
X
X
L
X
X
X
X
H
H
X
X
X
L
X
X
H
X
X
X
H
H
H
H
L
L
L
L
L
L
L
H
H
X
H
H
H
L
L
L
L
L
H
X
X
X
X
X
X
X
X
L
L
L
L
L
H
H
H
H
H
L
H
H
H
H
H
L
L
X
X
X
X
X
X
X
X
X
X
H
H
X
X
X
X
X
X
X
X
L
H = HIGH Vollage Level
L = LOW Vollage Level
X = Immaterial
5-50
X
X
X
X
X
X
X
X
X
X
H
X
X
X
X
H
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
X
X
X
X
H
L
L
H
H
L
L
H
X
X
H
L
X
L
H
X
H
L
L
H
H
L
L
H
H
X
X
X
X
X
H
X
X
X
X
X
L
H
L
H
L
H
L
,----------------------------------------------------------------, w
Logic Diagram
....Nr-
~
11
10
S2
51
so
-
-.
12
13
14
16
15
17
-
I -
I
,., 1 -v
.'1""
~
'I""
~
. -
-
~
-
~
-
I
T
~
.
~
.......
.
~
"'1""
~
~
)1
~
z
z
TL/F/9610-3
5·51
.... r----------------------------------------------------------------------------,
~
..J
~
J?JI National
~ Semiconductor
93114 Quad latch
General Description
Features
The 93114 is a multifunctional 4-bit latch designed for general purpose storage applications in high speed digital systems. All outputs have active pull-up circuitry to provide high
capacitance drive and to provide low impedance in both
logic states for good noise immunity.
• Can be used as single input 0 latches or set/reset
latches
• Active low enable gate input
• Overriding master reset
Connection Diagram
Logic Symbol
Jili!ili~
Dual-In-llne Package
E- 1
'-"
16
E 00 50 01 51 02 52 03 53
-Vee
50-2
15 -00
00- 3
14
01- 4
131-01
52-
-s;
5
121-02
02- 6
111-53
03- 7
101-03
GNO- 8
9~iiR
MR
00
Y 1~
9
Pin Names
DO-03
00-03
,13
12
Description
Enable Input (Active LOW)
Data Inputs
Set Inputs (Active LOW)
Master Reset Input (Active LOW)
Latch Outputs
5-52
03
I I
10
TLlF/9612-2
Pin 16
GND = PinS
TLlF/9612-1
SO-S3
MR
02
vee =
Order Number 93l14DMQB or 93l14FMQB
See NS Package Number J16A or W16A
E
01
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
Operating Free Air Temperature Range
MIL
-55'Cto
Storage Temperature Range
-65'C to
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
5.5V
+ 125'C
+ 150'C
Recommended Operating Conditions
Symbol
93L14 (MIL)
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
IOH
IOL
Units
Min
Nom
Max
4.5
5
5.5
2
V
V
0.7
V
High Level Output Voltage
-400
p.A
Low Level Output Current
4.8
mA
125
'C
-55
TA
Free Air Operating Temperature
ts (H)
Is (L)
Setup Time HIGH or LOW
On to 'E
10
20
ns
th(H)
th (L)
Hold Time HIGH or LOW
onto'E
0
10
ns
ts (H)
Setup Time HIGH, On to Sn
15
ns
th (L)
Hold Time LOW, On to Sn
5
ns
tw(L)
E Pulse Width LOW
30
ns
tw(L)
MR Pulse Width LOW
25
ns
tree
Recovery Time, MR to E
5
ns
5-53
.......
...I
I
Electrical Characteristics
Over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
VI
Input Clamp Voltage
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
II
Input Current @ Max
Input Voltage
IIH
High Level Input Current
Vee
Vee
= Max, VI = 2.4V
= Max, VI = 0.3V
Max
Units
-1.5
V
2.4
V
0.3
V
1
mA
Inputs
20
On
30
Inputs
-400
On
-600
Vee = Max
(Note 2)
Short Circuit
Output Current
lOS
= Min, II = -10 mA
Vee = Min, 10H = Max,
VIL = Max, VIH = Min
Vee = Min, 10L = Max,
VIH = Min, VIL = Max
Vee = Max, VI = 5.5V
Typ
(Note 1)
Vee
Low Level Input Current
IlL
Min
-2.5
Supply Current
Vee = Max (Note 3)
lee
Note 1: All typicals are at Vee = 5V, TA = 25'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: lee is measured with all outputs open and all Inputs grounded.
poA
poA
-25
mA
16.5
mA
Switching Characteristics
Vee
=
+5.0V, TA
Symbol
=
+25°C (See Section 1 for waveforms and load configurations)
CL
Parameter
Min
= 15pF
Units
Max
tpLH
tpHL
Propagation Delay
EtoOn
45
36
ns
tpLH
tpHL
Propagation Delay
On to an
30
30
ns
tpLH
Propagation Delay, MR to an
30
ns
tpHL
Propagation Delay, Sn to an
33
ns
5·54
CD
...r-
Co)
Functional Description
Truth Table
01:00
The 93L14 consists of four latches with a common active
LOW Enable input and active LOW Master Reset input.
When the Enable goes HIGH, data present in the latches is
stored and the state of the latch is no longer affected by the
Sn and Dn inputs. The Master Reset when activated over·
rides all other input conditions forcing all latch outputs LOW.
Each of the four latches can be operated in one of two
modes:
O·TYPE·LATCH-For O·type operation the S input of a
latch is held LOW. While the common Enable is active the
latch output follows the 0 input. Information present at the
latch output Is stored in the latch when the Enable goes
HIGH.
SET/RESET LATCH-During set/reset operation when the
common Enable is LOW a latch is reset by a LOW on the 0
input, and can be set by a LOW on the S input if the D input
is HIGH. If both Sand D inputs are LOW, the D input will
dominate and the latch wi! be reset. When the Enable goes
HIGH, the latch remains in the last state prior to disable·
ment. The two modes of latch operation are shown in the
Truth Table.
MR
E
D
S
On
H
H
H
L
L
H
L
H
L
L
X
X
L
L
On-I
H
H
H
H
H
L
L
L
L
H
L
H
L
H
L
L
H
H
X
X
On-I
On-I
L
X
X
X
L
Operation
o Mode
L
H
L
R/SMode
RESET
H = HIGH Voltage Level
L = LOW Voltage Level
x = Immaterial
On-1 = Previous Output State
on = Present Output State
Logic Diagram
Mil
E
so
51
00
QO
52
01
Ql
53
02
Q2
03
Q3
TL/F/9612-3
5·55
~National
~ Semiconductor
93L21
Dual 1-of-4 Decoder
General Description
Features
The 93L21 consists of two independent multipurpose decoders, each designed to accept two inputs and provide
four mutually exclusive outputs. In addition an active LOW
enable input, which gives demultiplexing capability, is provided for each decoder.
•
•
•
•
Connection Diagram
Logic Symbol
Multifunction capability
Mutually exclusive outputs
Demulliplexing capability
Active low enable for each decoder
15
3
2
13
14
Dual-In-Llne Package
Ea
AOa
16
2
15
Vee
DECODER a
Eb
Ala
AOb
OOa
Alb
01a
OOb
02a
01b
03a
02b
GND
03b
4
5
6
DECODER b
12
7
11
10
9
TL/F/10197-2
vee =
Pin 16
GND = Pin 8
TUF/10197-1
Order Number 93L21DMQB or 93L21FMQB
See NS Package Number J16A or W16A
Description
Pin Names
Ea,Eb
AOa,A1a,AOb,Alb
Enable Inputs (Active LOW)
Address Inputs
OOa-03a}
COb-03b
Decoder Outputs (Active LOW)
5-56
co
Co)
r-
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
Input Voltage
Operating Free Air Temperature Range
MIL
-55'Cto
Storage Temperature Range
-65'Cto
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
7V
5.5V
+ 125'C
+ 150'C
N
....
Recommended Operating Conditions
Symbol
93L12 (MIL)
Parameter
Units
Min
Nom
Max
5
5.5
Vee
Supply Voltage
4.5
VIH
High Level Input
Voltage
2
VIL
Low Level Input
Voltage
V
V
V
0.7
10H
High Level Output Current
-400
p.A
10L
Low Level Output Current
4.8
mA
TA
Free Air Operating
125
'C
-55
Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
Conditions
=
=
VI
Input Clamp Voltage
Vee
VOH
High Level Output
Voltage
Vee = Min,loH = Max,
VIL = Max, VIH = Min
VOL
Low Level Output
Voltage
Vee = Min, 10L = Max,
VIH = Min, VIL = Max
II
Input Current @ Max
Input Voltage
Vee
=
Max, VI
=
5.5V
IIH
High Level Input
Current
Vee
=
Max, VI
=
2.4V
IlL
Low Level Input
Current
Vee
=
Max, VI
=
0.3V
los
Short Circuit
Output Current
Vee = Max
(Note 2)
lee
Supply Current
Vee
=
Min,lI
Min
-10 mA
Typ
(Note 1)
Max
Units
-1.5
V
2.4
-2.5
Max (Note 3)
V
0.3
V
1
mA
20
p.A
-400
p.A
-25
mA
13.2
mA
Note 1: All typlcals are at Vee = 5V, TA = 25'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: Icc is measured with all outputs open and all inputs grounded.
•
5-57
.~
I
.-------------------------------------------------------------------------------~
Functional Description
Truth Table (Each Decoder)
The 93L21 consists of two separate decoders each designed to accept two binary weighted inputs and provide
four mutually exclusive active LOW outputs as shown in the
logic symbol. Each decoder can be used as a 4-output demultiplexer by using the enable as a data input.
Inputs
Outputs
E
AO
A1
00
01
02
03
L
L
L
L
H
L
H
L
H
L
L
H
H
X
X
L
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
L
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Logic Diagram
OOa
Oob
ADa
01a
AOb
01b
Ala
02a
Alb
02b
03b
03a
fa
Eb
TLlF/10197-3
Switching Characteristics Vee = + 5.0V, TA = + 25'C (See Section 1 for test waveforms and output load.)
Symbol
CL = 15pF
Parameter
Min
Units
Max
tPLH
tPHL
Propagation Delay
AntoDn
50
65
ns
tPLH
tPHL
Propagation Delay
'EntoDn
40
52
ns
5-58
r---------------------------------------------------------------------------~
~
~National
N
~ Semiconductor
93L22
Quad 2-lnput Multiplexer
General Description
Features
The 93L22 quad 2-input digital multiplexers consist of four
multiplexing circuits with common select and enable logic;
each circuit contains two inputs and one output.
• Multifunction capability
• On-chip select logic decoding
• Fully buffered outputs
Connection Diagram
Logic Symbol
Dual-In-Llne Package
5- 1
'-/
10a- 2
16 I-Vcc
15 H
l1a- 3
14 I-i0e
Za- 4
13 I-Ile
10b- 5
12 I-Ze
I1b- 6
lll-lOd
Zb- 7
10 I-Ild
GND- 8
91-Zd
[
lOa l1a lOb I1b 10e l1e 10d I1d
1-5
Za
Zb
Ze
Zd
4
7
12
9
TUF/1019B-2
TL/F/1019B-1
= Pin 16
GND = Pin 8
Vee
Order Number 93L22DMQB or 93L22FMQB
See NS Package Number J16A or W16A
Truth Table
Pin Names
S
E
lOa-lad}
11a-11d
Za-Zd
U)
Co)
Inputs
Description
Common Select Input
Enable Input (Active LOW)
Multiplexer Inputs
Multiplexer Outputs
S
IOn
11n
Zn
H
L
L
L
L
X
H
H
L
L
X
X
X
L
H
X
L
H
X
X
L
L
H
L
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
5-59
Output
E
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
5.5V
Operating Free Air Temperature Range
MIL
-55·Cto
- 65·C to
Storage Temperature Range
+ 125·C
+ 150·C
Recommended Operating Conditions
Symbol
93L22 (MIL)
Parameter
Vee
Supply Voltage
VIH
High Level Input Voltage
Units
Min
Nom
Max
4.5
5
5.5
V
V
2
VIL
Low Level Input Voltage
IOH
High Level Output Current
IOL
Low Level Output Current
TA
Free Air Operating Temperature
-55
0.7
V
-400
/LA
4.8
mA
125
·c
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
=
=
VI
Input Clamp Voltage
Vee
VOH
High Level Output Voltage
Vee = Min,loH = Max,
VIL = Max, VIH = Min
VOL
Low Level Output Voltage
Vee = Min. 10L = Max,
VIH = Min, VIL = Max
II
Input Current @ Max
Input Voltage
Vee
IIH
High Level Input Current
IlL
Low Level Input Current
los
Short Circuit
Output Current
lee
Supply Current
Min,ll
Min
-10 mA
Typ
(Note 1)
Max
Units
-1.5
V
2.4
V
0.3
V
1
mA
=
Max, VI
=
5.5V
Vee
=
=
Vee =
Max, VI
20
!LA
Max, VI
=
=
2.4V
Vee
0.3V
-400
/LA
-25
mA
13.2
mA
Vee
=
Max, (Note 2)
-2.5
Max
Note 1: All typicals are at Vee = 5V, TA = 25'C.
Note 2: Not more than one output should be shorted at a time, and the duration should not excesd one second.
5-60
r------------------------------------------------------------------------------------------,
w
I\)
I\)
Vee = +5.0V, TA = + 25'C (See Section 1 for test waveforms and output load)
Symbol
U)
r
Switching Characteristics
CL = 15pF
Parameter
Min
Units
Max
tPLH
tPHL
Propagation Delay
StoZn
36
tPLH
tPHL
Propagation Delay
10 or 11 to Zn
30
22
ns
tPLH
tPHL
Propagation Delay
EtoZn
27
27
ns
ns
49
Functional Description
A common use of the 93L22 is the moving of data from a
The 93L22 quad 2-input multiplexer provides the ability to
select four bits of either data or control from two sources, in
one package. The Enable input (E) is active LOW. When not
activated all outputs (Zn) are LOW regardless of all other
inputs.
The 93L22 quad 2-input multiplexer is the logical implementation of a four-pole, two position switch, with the position of
the switch being set by the logic levels supplied to the one
select input. The logic equations for the outputs are shown
below:
Za = E. (Ila. S + lOa 0 S) Zb = E. (llb. S + lOb. S)
ZC = E. (Ilc· S + 10c. S) Zd = E. (Ild. S + 10d. S)
group of registers to four common output busses. The particular register from which the data comes is determined by
the state of the select input. A less obvious use is as a
function generator. The 93L22 can generate four functions
of two variables with one variable common. This is useful for
implementing random gating functions.
Logic Diagram
IOd
I1d
Zd
IOe
l1e
Ze
lOb
I1b
Zb
lOa
l1a
Za
TL/F/l0198-3
5-61
~National
~ Semiconductor
93L24
5-Bit Comparator
General Description
Features
The 93L24 expandable comparator provides comparison
between two 5-bit words and gives three outputs-"Iess
than", "greater than" and "equal to", A HIGH on the active
LOW Enable Input forces all three outputs LOW,
• Three separate outputs: AB, A=B
• Easily expandable
• Active low enable input
Connection Diagram
Logic Symbol
y Tiii ii,
Dual-In-Llne Package
E- 1
AB
14 -A=8
13 -AO
12
11
10
9
1-(l E
A>8
A<8
A=8
1~
!
1~
:-Al
:-A2
i-A3
r-A4
TL/F/l0199-2
vee = Pin 16
GND
= PinS
TUF/l0199-1
Order Number 93L24DMQB or 93L24FMQB
See NS Package Number J16A or W16A
Truth Table
Pin Names
E
AO-A4
BO-B4
AB
A=B
Description
Outputs
Inputs
E
Enable Input (Active LOW)
Word A Parallel Inputs
Word B Parallel Inputs
A Less than B Output (Active HIGH)
A Greater than B Output (Active HIGH)
A Equal to B Output (Active HIGH)
H
L
L
L
An
Bn
AB
X
X
L
L
L
H
L
L
H
L
Word A = Word B
Word A > Word B
Word B < Word A
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immate~aI
5-62
A=B
L
H
L
L
Absolute Maximum Ratings
(Note)
If MIlitary/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
Operating Free Air Temperature Range
MIL
-55'Cto
Storage Temperature Range
-65'Cto
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaran·
teed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
5.5V
+ 125'C
+ 150'C
Recommended Operating Conditions
Symbol
93L24 (MIL)
Parameter
Vee
Supply Voltage
V,H
High Level Input Voltage
V,L
Low Level Input Voltage
Units
Min
Nom
Max
4.5
5
5.5
V
0.7
V
2
V
10H
High Level Output Current
-400
p,A
10L
Low Level Output Current
4.8
mA
TA
Free Air Operating Temperature
125
·c
-55
Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
Conditions
= Min, I, = -10 mA
Vee = Min, 10H = Max,
V,L = Max, V,H = Min
Vee = Min, 10L = Max,
V,H = Min, V,L = Max
Vee = Max, V, = 5.5V
V,
Input Clamp Voltage
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
I,
Input Current @ Max
Input Voltage
I'H
High Level Input Current
Vee
I,L
Low Level Input Current
Vee
los
Short Circuit
Output Current
Icc
Supply Current
Min
Vee
Max, V,
Vee
=
=
=
Vcc
=
Max
Max, V,
=
=
Typ
(Note 1)
Max
Units
-1.5
V
V
2.4
0.3
V
1
mA
2.4V
40
p,A
0.3V
-0.8
mA
-25
mA
21
mA
Max (Note 2)
-2.5
Nole 1: All typicals ara al vee - 5V, TA - 25"C.
Nole 2: Nol mora than ana output should ba shorted al a lima, and Iha duration should nol exceed ana second.
II
5·63
~
!l
CO)
m
r---------------------------------------------------------------------------------,
Switching Characteristics
Vee =
+ S.OV, TA = + 2SoC (See Section 1 for test waveforms and output load)
CL = 15pF
Parameter
Symbol
Min
Units
Max
tpLH
tpHL
Propagation Delay
E toA=B; EtoAB
32
3S
ns
tpLH
tpHL
Propagation Delay
AntoA>B; Bn toA>B
S4
7S
ns
tpLH
tpHL
Propagation Delay
AntoAB output from one device into an A input on
another device and the A < B output into the corresponding
B input permits easy expansion.
The A4 and 84 inputs are the most significant inputs and
AO, 80 the least significant Thus if A4 is HIGH and 84 is
LOW, the A> 8 output will be HIGH regardless of all other
inputs except E.
Logic Diagram
JO-r----A<·
A=D
.;0----- A>.
.
D3
D2
"
DO
TL/F/10199-3
S·64
r------------------------------------------------------------------------------------, w
U)
rI\)
~National
CD
~ Semiconductor
93L28
Dual 8-Bit Shift Register
General Description
Features
The 93L2B is a high speed serial storage element providing
16 bits of storage in the form of two B-bit registers. The
multifunctional capability of this device is provided by several features: 1) additional gating is provided at the input to
both shift registers so that the input is easily multiplexed
between two sources; 2) the clock of each register may be
provided separately or together; 3) both the true and complementary outputs are provided from each B-bit register,
and both registers may be master cleared from a common
input.
• 2-input multiplexer provided at data input of each
register
• Gated clock input circuitry
II Both true and complementary outputs provided from
last bit of each register
II Asynchronous master reset common to both registers
Connection Diagram
Logic Symbol
13
Dual-In-Llne Package
11
12
Vee
Q7
N
..,
'"
5
iii
Dl
Iii
'"
DO
14
10
Q7
Q7
'"
*l
~
MR
'"
4
15
5
CP
CP
COM
3
7
Q7
TUF/l0200-1
2
MR
Order Number 93L28DMQB or 93L28FMQB
See NS Package Number J16A or W16A
TL/F/l0200-2
Vee = Pin 16
GND = PinS
Pin
Names
S
00,01
CP
MR
Q7
Q7
Description
Data Select Input
Data Inputs
Clock Pulse Input (Active HIGH)
Common (Pin 9)
Separate (Pins 7 and 10)
Master Reset Input (Active LOW)
Last Stage Output
Complementary Output
5-65
Absolute Maximum Ratings (Note)
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Ottlce/Dlstrlbutors for availability and specifications.
Supply Voltage
Input Voltage
Operating Free Air Temperature Range
MIL
- 55'C to
Storage Temperature Range
-65'Cto
7V
5.5V
+ 125'C
+ 150"C
Recommended Operating Conditions
Symbol
93L28 (MIL)
Parameter
Units
Min
Nom
Max
4.5
5
5.5
V
0.7
V
Vee
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
IOH
High Level Output Current
-400
/LA
IOL
Low Level Output Current
4.8
mA
125
'C
V
2
-55
TA
Free Air Operating Temperature
ts(H)
ts(L)
Setup Time HIGH or LOW
Dn toCP
30
30
ns
th(H)
ih(L)
Hold Time HIGH or LOW
Dn toCP
0
0
ns
tw(H)
twILl
Clock Pulse Width
HIGH or LOW
55
55
ns
!w(L)
MR Pulse Width with CP HIGH
60
ns
twILl
MR Pulse Width with CP LOW
70
ns
5-66
Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Parameter
Symbol
Conditions
VI
Input Clamp Voltage
Vee = Min, 11= -10 mA
VOH
High Level Output Voltage
Vee = Min, 10H = Max,
VIL = Max, VIH = Min
VOL
Low Level Output Voltage
Vee = Min, 10L = Max,
VIH = Min, VIL = Max
II
Input Current @ Max
Input Voltage
Vee = Max, VI = 5.5V
IIH
HIGH Level
Input Current
Vee = Max, VI = 2.4V
LOW Level
Input Current
IlL
Vee = Max, VI = 0.3V
los
Short Circuit
Output Current
Vee = Max
(Note 2)
ICC
Supply Current
Vee = Max
Note 1: All typlcals are at Vce
Min
Typ
(Note 1)
Max
Units
-1.5
V
2.4
V
MR,Dx
0.3
V
1
mA
20
CP (7,10)
30
S
40
p.A
CPCom
60
MR,Dx
-400
CP (7,10)
-600
S
-800
CPCom
-1200
-2.5
p.A
-25
mA
25.3
mA
= SV, TA = 2S'C.
Nole 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Switching Characteristics
Vee =
+ 5.0V. TA
Symbol
=
+ 25'C (See Section 1 for test waveforms and output load)
CL = 15pF
Parameter
Min
Units
Max
f max
Maximum Shift Right Frequency
5.0
tpLH
tpHL
Propagation Delay
CPto Q7 or 07
45
80
ns
tpHL
Propagation Delay MR to Or
110
ns
MHz
II
5·67
Functional Description
The two 8-bit shift registers have a common clock input (pin
9) and separate clock inputs (pins 10 and 7). The clocking
of each register is controlled by the OR function of the separate and the common clock input. Each register is composed of eight clocked RS master/slave flip-flops and a
number of gates. The clock OR gate drives the eight clock
inputs of the flip-flops in parallel. When the two clock inputs
(the separate and the common) to the OR gate are LOW,
the slave latches are steady, but data can enter the master
latches via the Rand S input. During the first LOW-to-HIGH
transition of either, or both simultaneously, of the two clock
inputs, the data inputs (R and S) are inhibited so that a later
change in input data will not affect the master; then the now
trapped information in the master is transferred to the slave.
When the transfer is complete, both the master and the
slave are steady as long as either or both clock inputs remain HIGH. During the HIGH-to-LOW transition of the last
remaining HIGH clock input, the transfer path from master
to slave is inhibited first, leaving the slave steady in its present state. The data inputs (R and S) are enabled so that new
data can enter the master. Either of the clock inputs can be
used as clock inhibit inputs by applying a logic HIGH signal.
Each 8-bit shift register has a 2-input multiplexer in front of
the serial data input. The two data inputs DO and D1 are
controlled by the data select input (S) following the Boolean
expression:
Serial data in: SD = SDO
+
SD1
An asynchronous master reset is provided whiCh, when activated by a LOW logic level, will clear all 16 stages independently of any other input signal.
ShiH Select Table
Inputs
Output
S
DO
01
Q7 (t"+8)
L
L
H
H
L
H
X
X
X
X
L
H
L
H
L
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
n+ 8 = Indicates slate after eight clock pulse
Logic Diagram
01
DO
01
DO
~------------a;~----~------~----~------~-----+------~-----+------4---~
TLlF/l0200-3
5-68
, - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - , U)
Co)
r-
~National
Co)
.c:.
~ Semiconductor
93L34
a-Bit Addressable latch
General Description
Features
The 93L34 is an B-bit addressable latch designed for general purpose storage applications in digital systems. It is a
multifunctional device capable of storing single line data in
eight addressable latches, and being a one·of-eight decoder
and demultiplexer with active level HIGH outputs. The device also incorporates an active LOW common clear for resetting all latches, as well as, an active LOW enable.
•
•
•
•
•
•
Connection Diagram
Logic Symbol
Serial to parallel capability
Eight bits of storage with output of each bit available
Random (addressable) data entry
Active high demultiplexing or decoding capability
Easily expandable
Common conditional clear
~
Dual-In-Line Package
AO- 1
\J
16
I-Vcc
1 - AO
A2- 3
I-a::
14 I-E
00- 4
13 1-0
3 - A2
01- 5
12 1-07
02- 6
111-06
03- 7
10 1-05
GNO- 8
91-04
2 - Al
Cl 00 01 02 03 04 05 06 07
TL/F/10201-2
vee
GND
TUF/10201-1
Order Number 93L34DMQB or 93L34FMQB
See NS Package Number J16A or W16A
Description
Pin Names
AO-A3
D
E
CL
00-07
o
E
15
Al- 2
Address Inputs
Data Input
Enable Input (Active LOW)
Clear Input (Active LOW)
Parallel Latch Outputs
5-69
~
~
Pin 16
Pin 8
Absolute Maximum Ratings
(Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and speciflcatlons_
Supply Voltage
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
Military
-55'Cto
Storage Temperature Range
-65'Cto
+ 125'C
+ 150'C
Recommended Operating Conditions
Symbol
93L34 (Mil)
Parameter
Vee
Supply Voltage
VIH
High level Input Voltage
Vil
low level Input Voltage
Units
Min
Nom
Max
4.5
5
5.5
V
0.7
V
2
V
IOH
High Level Output Voltage
-400
/loA
IOl
low level Output Current
4.8
mA
TA
Free Air Operating Temperature
125
'C
ts (H)
Setup Time HIGH, D to E
45
ns
th (H)
Hold Time HIGH, D to E
-5
ns
!s(l)
Setup Time lOW, D to E
45
ns
th (l)
Hold Time lOW, D to E
-7
ns
!s (H)
ts (l)
Setup Time HIGH or lOW
An toE
10
10
ns
-55
tw(l)
E Pulse Width lOW
26
ns
tw(l)
Cl Pulse Width lOW
35
ns
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
= Min, 11=
VI
Input Clamp Voltage
Vee
VOH
High level Output Voltage
Vee = Min, 10H = Max,
Vil = Max, VIH = Min
VOL
low level Output Voltage
Vee = Min, 10l = Max,
VIH = Min, VIL = Max
II
Input Current @ Max
Input Voltage
Vee = Max, VI
= 5.5V
IIH
High level Input Current
Vee = Max, VI
= 2.4V
IlL
los
low level Input Current
Short Circuit
Output Current
Min
Conditions
Vee = Max, VI
Vee
-10 mA
= 0.3V
= Max (Note 2)
Max
Units
-1.5
V
2.4
V
0.3
V
1
mA
Inputs
20
E
30
Inputs
-0.4
E
-0.6
-2.5
Supply Current
Vee = Max (Note 3)
leo
Note 1: All Iypicals are at Vee = 5V, TA = 25'0.
Not. 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: IcC Is measured with all outputs open and all Inputs grounded.
5-70
Typ
(Note 1)
p.A
mA
-25
mA
21
mA
Switching Characteristics Vee = + 5.0V, TA = + 25'C (See Section 1 for Test Waveforms and Output Load)
Symbol
CL = 15pF
Parameter
Min
~
Units
Max
tpLH
tpHL
Propagation Delay
Etoon
45
42
ns
tpLH
tpHL
Propagation Delay
Dtoon
65
45
ns
tpLH
tpHL
Propagation Delay
An to an
66
66
ns
55
ns
tpHL
~
t;
Propagation Delay
rn: to an
Functional Description
Mode Select Table
The 93L34 has four modes of operation which are shown in
the Mode Select Table. In the addressable latch mode, data
on the data line (D) is written into the addressed latch. The
addressed latch will follow the Data input with all non-addressed latches remaining in their previous states. In the
memory mode, all latches remain in their previous state and
are unaffected by the data or address inputs. To eliminate
the possibility of entering erroneous data into the latches,
the Enable should be held HIGH while the Address lines are
changing. In the 1-of-8 decoding or demultiplexing mode,
the addressed output will follow the state of the D input with
all other outputs in the LOW state. In the clear mode all
outputs are LOW and unaffected by the address and data
inputs. When operating the 93L34 as an addressable latch,
changing more than one bit of the address could impose a
transient wrong address. Therefore, this should only be
done while in the memory mode.
E
CL
Mode
Addressable Latch
Memory
Active HIGH 8-Channel Demultiplexer
Clear
L
H
H
H
L
H
L
L
II
5-71
Truth Table
Inputs
Outputs
Mode
CL
E
AO
A1
A2
00
01
02
03
04
05
06
07
L
L
L
L
H
L
L
L
X
L
H
L
X
L
L
H
X
L
L
L
L
D
L
L
L
L
D
L
L
L
L
D
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Clear
Demultiplex
L
L
H
H
H
L
L
L
L
L
L
L
L
H
H
X
X
X
01-1
01-1
01-1
01-1
01-1
01-1
01-1
01-1
Memory
H
H
H
L
L
L
L
H
L
L
L
H
L
L
L
D
01-1
01-1
01-1
D
01-1
01-1
01-1
D
01-1
01-1
01-1
01-1
01-1
01-1
01-1
Qt-1
Qt-1
Qt-1
01-1
01-1
01-1
01-1
01-1
Addressable
Lalch
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
H
H
H
01-1
01-1
Qt-1
Qt-1
01-1
01-1
D
H
H
•
L
•
= HIGH Voltage Level
L
= LOW Voltage Level
X
= Immaterial
5·72
01-1
Ot-1
= Previous Output State
r---------------------------------------------------------------------________
,~
W
r
Logic Diagram
w
.I:loo
» ____ 07
» ___1--06
)0-...--05
Q-------4:~----_r+++;~H ~;=======~
)t)_,__04
)0-...--03
A2---'''''..........
A1
}O-...--02
AO
",D_'__Ol
0---,
~_'__OO
TL/F/10201-3
5-73
~National
~ Semiconductor
93138
8-Bit Multiple Port Register
General Description
Features
The 93L38 Is an 8·bit multiple port register designed for high
speed random access memory applications where the ablll·
ty to simultaneously read and write is desirable. A common
use would be as a register bank in a three address comput·
er. Data can be written into anyone of the eight bits and
read from any two of the eight bits simultaneously. The cir·
cult uses TTL technology and is compatible with all TTL
families.
• Master/slave operation permitting simultaneous write/
read without race problems
• Simultaneously read two bits and write one bit in any
one of eight bit positions
• Readily expandable to allow for larger word sizes
Connection Diagram
Logic Symbol
Dual·ln·Llne Package
80- 1
81- 2
82- 3
zs- "
ZC- 5
C2- 6
Cl- 7
GND- 8
\",.../
16 I-Vcc
I-AO
I-Al
15
14
13
12
AO AI A2 80 81 82 CD Cl C2
12- DA
1-A2
11- CP
I-DA
l11-CP
10 I-SLE
91-CO
10 -
(15)
-eX2
-RX2
-CO2
11 .. T2 (14)
(11) 5- 60 ••
12. t.l
= RELEASE nUE > 60 ••
CX - TIMING CAPACITANCE - pF
TL/F/10203-5
Input to Pin 4 (12)
Pins 5 (11) and 3 (13)
TL/F/10203-6
FIGURE a
=H
•
5-81
~ ~------------------------------------------------------------------------------~
9 Typical Characteristics
~
twvaVcc
~
I
1.2
TA = 25"C
!!l
tw(mln) va TA
I! ISO
I
I
l - RX=3IkA~
i! 1.1 r- ex = lGOOpI'
liD
I~
I"""
.....
~
-
I~
I"""
I
IZ5 r-
~
40
4S
5.0
y
5.5
II-~--
'r- Y~ = ~.oY
RX=2DkA
I- ex = 0
100
1
,~
I I
~1IJ.a:rAR'f~~
i
1m
~
1.G1
L.oo
i
..... 1- i-""
0S9
z
I
75
IZ5
TA - AMBIENT IIMPERATURE - "C
Yee - SUPPLY VOLTAGE - Y
~
~
I I
so_75
Y~=~.DYL[
= 39kA
ex = IDOOpF
RX
~0J8
-75
-so -25
0
25 50 75 100 125
TA - AMBIENT IIMPERATURE - "C
TL/F1I0203-7
t'00nsj
1.5V
~tPLHt=
INPUT PULSE
, .. 25kHz
Amp" 3,OV
Width .. 100 ns
t, = It:s: IOns
_~~_______I-J),l --------~~
va
:t-~-}.
-ItPHL~
TL/F110203-B
FIGUREb
5·82
Section 6
Physical Dimensions
Section 6-Physical Dimensions
Physical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Bookshelf
Sales and Distribution Offices
6-3
r-----------------------------------------------------------------------------, :::r
~
':i
~National
~ Semiconductor
All dimensions are in inches (millimeters)
~
c
3'
CD
:I
(I)
20 Terminal Ceramic Leadless Chip Carrier (E)
NS Package Number E20A
:::I
(I)
~
0.015
(0.381)
MIN TVP
~II-~
(1.600-1.905)
0'
0.007-0.011
(0.178-0.279)
~""',,",I"H'*"'"
~I
nTYP
t
LDETAILA
Top View
45" x 0.015tO.ol0
(0,381 ±0.254)
Side View
0.045 -0.055
(1.143-1.397)
TYP
8ottomVIew
0.003
..!!:.!!!!.
(0.076)-,
,r-(0.381)
MIN TVP ~ MAX TVP
0.022
+
!
~f~
MAXTYP
(0.152)
MIN7YP
Detail A
E20AIREVOI
14 Lead Ceramic Dual-In-Line Package (J)
NS Package Number J14A
0.785
0.025
(0.635)
RAD
(19.939)~
\'
MAX
12
11
10
I
8
t
0.220-0.310
(5.588-7.874)
'--T:-."T.:T"'I":T'T:'II"'T':T"1":'1"'r.1r-'
L
0.018t11.003
(OA57 ±tJ.D76)
0.098
(U89)
MAX BOTH ENDS
-11-
~
(2,540±0.254)
----.l
0.125-UOO
(3.175-5.080)
0.150
(3,81)
MIN
6-3
J14AIR!VGj
16 Lead Ceramic Dual-In-Line Package (J)
NS Package Number J16A
0,025
(0,635)
RAD
0,005-0,020
(0,127 - 0,508)
RAD TYP
.--=l.
0,290-0,320
I
~~J(7'3~_8'120)
95' ±5'
0,180
(4,572)
-I
0,200
(5,080)
MAX
0,005--1
~ ~~~~~~~~~~l~-_~~__~-L
0,008-0,012
(0,203 - 0,305)
MAX
J
0,080
0,310-0,410
(7,874 -10,41)
I
I--
(2,~~
BOTH
ENDS
JI6A{AeVK)
20 Lead Ceramic Dual-In-Line Package (J)
NS Package Number J20A
0,985
~------(25,019)
,------+1
MAX
0,180
(4,572)
MAX
0,055 ± 0,005
(l,a97±0,127)
0.280 - 0,320
(7'386-8'120)~
GLASS SEALANT
0.200
(5,080)
MAX
,
0.125-0.200
(3.175-5,080)
0.008-0,012
(0,203-0,305)
k- 0,310-0.410
0,018±0.003 _II~
(0.457±0,078)
II
(7.874-10.41)
0,100±0,010
(2,540 ± 0,254)
J20A (REV MI
6-4
~----------------------------------------------------------------------------,~
::r
24 Lead Ceramic Dual-In-Line Package (J)
NS Package Number J24A
':i
I
1.290
~-------------(32J66)------------~·-
MAX
1
::s
rn
o·
::s
GLASS
rn
0.514-0.526
/"-. ,n;~;r .T", ,T ; -r.,r r-r.r-r:;-n-; ; . .,n;:;r-" '"i'' '
0.030-0.055
(0.762-1.397)
RAD TVP
0.590-0.620 ~
CI
3'
C1I
0.600
(15.2~)
fMAX
0.025
(0.635)
RAD
~
~
0.005
~ "iT"' ~ .~~
95" l5"
I_
.'" - .,.--..,J
0.008-0.012
0.685 -0.060
r---- (
tll.635) 17.40 -1.524
_
I
.-~
0.098
0.125-0.200
(3.175-5.080)
(2.489)
MAX
MIN
0.150
(3.810)
MIN
J24AtR!VHI
24 Lead Ceramic Dual-In-Line Package (J)
NS Package Number J24F
I.29D
.!:!!
RAD
(8.835)
1~"-------(32.77)
MAX-------"1
t
+f •
!!-----0.1+2-5(3.175)
MIN
95' tJ;'
I....... 0.310-DA10
0.ODS-0.012
1
I-- (7.874-1DAll -l
~:~-0.306)
JI4I(IIEVGJ
6-5
14 Lead (0.150" Wide) Molded Small Outline Package (M)
NS Package Number M14A
0.150-0.157
(3.810-3.988) 0.010-0.020 450
(0.254-0.508) )(
r-
0.008-0.010
iDToi='D.i5i)
TYP ALL LEADS
r
0.053 - 0.069
(1.34&-1.753)
t
SOMAXTYP
ALL LEADS
IJC±~
0.1104
(0.102)
ALL LEAD TIPS
SEJ1IING
PLANE
,
~a
~J
f ot
(0.35&)
(1.270)
TYP
(0.406-1.270)
TYP ALL LEADS
0.004-0.010
(0.102-0.254)
-~t4~
I JL-=I
-
[J-0.020
(0.356-0.50S) TYP
.!:!!!!!. TYP
(0.203)
M14A(REVHI
14 Lead (0.300" Wide) Molded Small Outline Package (M)
NS Package Number M148
Ii
I
0.34&-0.3&2
(8.788-9.195)14 13 12 11 10 9 8
0.394 - 0.419
(10.01-10.&4)
.!:!!ll._
(0.686)
r
0.291-0.299
(7.391-7.&95) -
0.009-0.013
(0.229-0.330)
TYP ALL LEADS
1
""--'=:::1'"-'"
0.093-0.104
(2.3&2-2.842)
~)(45°
(0.432)
~
,
* *
TYP
8° MAX
ALL LEADS
~-+
LJ1
r
~
.!:.2!!!.
(0.102)
ALL LEAD
TIPS
J [
f
0.030-0.050
(0.7&2-1.270)
TYP ALL LEADS
T
(1.270)
TYP
6·6
~---*-t
~
~J
0.037-0.044
(0.940-1.118)
0.004-0.012
(0.102-0.306)
SEJ1IIN8
JL~TYp
PlANE
(0.358-0.483)
r--------------------------------------------------------------------------.~
~
16 Lead (0.150" Wide) Molded Small Outline Package (M)
NS Package Number M 16A
~
S2
:I
CD
i
o·
::I
en
30'
~~:;:;:::::;::;::~
8~
LEAD NO.1
IDENT
..!!:!!!!!.MAX
(0.254)
~ X451Ir~:~~:=~::)
10.254-0.508)
r
0.053-0.069
(1.346-1.753)
80 MAX TVP
All LEADS
L
."oF
}\h.
+
o.ooC -r-j L-=:J0.050
10.203-0.254)
TYP All lEADS
I
0.004
(0.102)
ALL LEAD TIPS
--1>0
0.004-0.010
~
*
J
O.050J
(1.270)
TYP
(0.406-1.270)
TYP ALL LEADS
~f
SEAliNG
PLANE
0.014-0.020 TYP
(0.356 -0.508)
0.008
(0.203) TYP
M16ACReVH)
16 Lead (0.300" Wide) Molded Small Outline Package (M)
NS Package Number M16B
~~~~~~~R=~~
2
3
4
5
& 7
8---,
..!!:!!!!!.MAX
(0.254)
~
12.362-2.642)
t
SEIITING
PlANE
f
0.1114
(0.102)
ALL lEAD TIPS
0.004-0.012
~ iG.iOi=ffii
~~
I::~) I I ~
-
-11.270)
TYP
JlJ L~-0'020TYP
10.356-0.508)
.!mTYP
10.203)
6·7
Mt88(REVE,I
o
.~
i
r-----------------------------------------------------------------------------~
20 Lead (0.300" Wide) Molded Small Outline Package (M)
NS Package Number M20B
E
..
0.496-0.512
(12.698-13.1JIJS)
C
"8
~
Q.
LEAD NO.1
IDENT
12345&78
0.010-0.829 05"
(0.2&4-0.737) x
tr
0.211-0.219
i7.391-71ii
0.093-0.101
(2.362-2.842)
•L
----.I
Jiii
m
_~. JJ£JrltlIlG1::~
tf II
(:.~::)
.
_
(::~:::::)
JL
_~
(1.270)
m
II
&ERr1HG
_ _ .!.!!!!=W!m
tPlANE
(0.356-0.508)
..!!!!!!.TYP
(0.203)
M20B(R[Vf)
24 Lead (0.300" Wide) Molded Small Outline Package (M)
NS Package Number M24B
5
~
(7.391-7.5941
0.037-0.044
10.940-1.1181
0.l1li9-0.013
10.2211-0.3301
TYPALLWOI
8
14
13
9
10
11
12
0.D93-0.104
t
t~J~
L
-tr:::::!)J=,==;=t==..!~~
iIToii
7
15
i2.iiH.iiii
+
0.004
6
"I
1&
~
11.2701
10.76Z-1·2701
TYP ALL LEADS
ALL LEAD npg
6-8
10.356-0.4831
TYP
."
:r
14 Lead Molded Dual-In-Line Package (N)
NS Package Number N14A
l.
fl
c
3'
CD
::s
!!.
o
::s
(I)
~DIA ~MAX
(2.3371
(0.7621 DEPTH
OPTION 1
OPTION 02
0.13510.005
(3.42910.1271
0.300-0.320
4'lYP
OPTIONAL
~
(~:~!~I
MIN
I'. . I~
Ir Iso,L lYP
0.125-0.150
(3.175-3.8101
II
0.014-0.023 TYP- _
(0.355 -0.584)
--
_
..
0.07510.015
(1.90510.3811
..... 0.10010.010 lYP
(2.54010.2541
0.05010.010 TYP
(1.270 -0.2541
h~~1
~
~!;'J
~~
L
o.280
(7.1121___
MIN
ol8-0.016 lYP
(0.203-0.4081
.
0.325 ~~:~~
/8255 +1.015)
~ •
-0.381
N,.4A.IREYfl
16 Lead Molded Dual-In-Line Package (N)
NS Package Number N16A
0.092
(2.337)
DIANDM
(2XI
I·
+0040.1
0.325 -0:016
(8255 .1.016)
.
-0.381
tJ I- J
0.009-0.015
(0.229-0.3811
0.075 to.015
(1.905 '0.381)
0.100 to.Ol0
(2.640 '0.264)
N1BAtREVEI
6·9
o
C
o
"iii
c
CD
E
r---------------------------------------------------------------------------------,
16 Lead Molded Dual-In-Line Package (N)
NS Package Number N16E
is
B
"=.
.c
a.
INDEX
AREA
PIN NO. 1
IDENT
OPTION 01
OPTION 02
0.130±0.01l5
(3.302 ±0.127)
0'125-0~150
(3.175-3.810)
0.300-0.320
C-"U'
L
0.014-0.023
(0.356 0.584)
TYP
III
JIL~
0.050 ±0.010
(1.27D ±0.254)
TVP
I§3F"L~'m
~!s'J
~~
I
90' ±4' TYP
0.030±0.015
(0.762±0.381)
(0.203-0.406)
0.280
_(7.112) __
MIN
0.100±0.010
(2.54D±0.254)
TYP
0.325 ~~::~
f8 255 +1.016)
. -0.381
~
18 Lead Molded Dual-In-Line Package (N)
NS Package Number N18A
0.843-0.810
(21Al-ZZ.l0)
J!:!!!!
X 0.030
IZ.33&)
(0.76Z)
NOM
MAX
DEEP (2 PLCS)
15
14
13
-::-j
12
11
D
f0.250 ±o.oos
(6.35D±0.127)
~
O'210~
(7.112)
1ffi=i::;::::;:;:;n;:;=:r.;:::;:::;:=;::;:;n;:;=r.rI~
MIN
0.300-0.320
Ir:O~':;1
~
I·
I
±4'~
90'
TVP
(0.501)
0.125-0.140 I MIN
13.175-3.556)
+0.040 ..
0.325 ...1.015
/8.255 +1.018)
~
-0.311
0.100 ±OJlIO
12.540 ±O.254)
TVP
N18AIREVE)
6·10
N16e!REVF)
,-----------------------------------------------------------------------------,
20 Lead Molded Dual-In-Line Package (N)
NS Package Number N20A
1.013-1.040
125.73-26.42)
0.092 X0.030
(2.337 X 0.762)
MAXOP
rl~~11
!!!.
3"
ft)
0.032±0.005~D
19
~==~====±:17==1=6~1=.~14~=I3~I=Z=='~I~~
10.813±0.127)
RAO
0.260 ±0.005
16.604 ±0.127)
1'.
~
o
0"
~
NO.lI0ENT~
o
I
OPTION 2
0.130 0.005
11.651)
~.~~++~~~~~~~
------r-----------~
-90"0. 004
0.009_0.01JJ
10.229-O.3Bl )
TYP
°1
0.125-0.140
(3.175 3.556)
0.060.0.005
11.524.0.127)
:~~~
PIN
om" jR=;I;1ffimffi=rrr;:fi=rn=r.T'T7:r=r.=r;:;;;=I-.l
0.065
0.325
~
n"
c
=:1
PIN NO. 110ENT""",,-1 ~ +
~
t
0.020
(0.50B)
MIN
fU55 +1.016)
~
-O.3Bl
N20AjREVGj
24 Lead Molded Dual-In-Line Package (N)
NS Package Number N24A
1--___________
1.243-1.270 ------------0--1
(31.57-32.26)
0.062
11.676)
RAO
PIN NO.1 IDENT
I
Z
DOTTED OUTLINES
REFLECT ALTERNATE
~:J
MOLDED BODY CONFIGURATION
114.73)
0.030
MIN
-(0.-762-)
0.015
0.600-0.620
MAX
11.905)
r:
L ...,..,,.-__++-____--=-:.:....-++-_..,,._+-___....
!F115.24-15.148)
0.009-0.015
iD.2ii=ffiii
0.075 ±0.015
(1.906 ±0.381)
~
~
TYP
t t
0.015
0.018
-(0.381)
_
_•±o.o
__
~ 0.100 to.Ol0;-11-- (OA57 _0.076) 13.175-3.556) MIN
I--
~
(2.640 '0.264)
N24AIREvet
6-11
•
24 Lead (0.300" Wide) Dual-In-Line Package (N)
NS Package Number N24C
0.D92
i2.337i
(2 PLS)
f
0.28D±0.DD5
(6.&D4±0.127)
I
0.300-0.320
r:'~'1
~J
0.065
(1.651)
0.076±0.015
(1.905±0.311)
I
IN24C(REVF)
28 Lead Plastic Chip Carrier (V)
NS Package Number V28A
l
68MCHAT
D••
(1.2TO)
r
1+--+1--;"- 0.130
16
I
(3:2)
NOM
PEDmAL
VIEW A-A
~JB
x4/i'
0.1"-0.1111
(4.111-4.m)
+
!:!!!!=l!:m.
(0.6111-0.113)
TYP
t
f t
0.104-0.111
(2.842-2.197)
--.,
6-12
14 Lead Ceramic Package (W)
NS Package Number W14B
0.026 -0.035
(0.660 -0.889)
TYP
t~L . o-o~·
(0.203-0.305)
DETAIL A
0.004-0.006
(0.102 -0.152)
TYP
Jl
J
TVP
~.(~:~:) MAX TYP
W14BIREV H}
16 Lead Ceramic Package (W)
NS Package Number W16A
0.050-0.0BO
(1.270 - 2.032)
1
0.004 -0.006 TYP-I
(0.102-0.152)
0.371-0.390
(9.423 -9.906)
1t
0.007 -0.018
10.178-0.457)
TYP
0.050±0.005 TYP
(1.270±0.127)
~I_O.OOOMINTYP
.t.
0.250 - 0.370
(6.350-9.39B)
I
. - 16151413121110 9
0.300
(7.620)
MAX GLASS
f
f
-t JL
T,"-u"
0.245 -0.275
'
DETAIL A---"'1
--~2,
(6.223 -6.985)
3 4 5 6 7 8
(0.203-0.305)
I
!, 'J.
PIN NO. ...J
10ENT
0.026-0.040
(0.660-1.016)
TYP~ If.r --
0.250 -0.370
(6.350 -9.398)
~
II
0.015-0.019
-.j I- (0.381- 0.482)
TYP
6-13
W16A(REV HI
DETAIL A
o
j
r-------------------------------------------------------------------------------~
20 Lead Ceramic Package (W)
NS Package Number W20A
- r-
is
~
~
.c
0.030 -0.040
._
'--,..
(0.762-1.016) TYP - - 1-
L
0.060-0.090
(1.624-2.288)
~TYP-;"'+I
(1.270±0.127)
r
0.540 MAX~
(13.72)'-
_11-...-.
0 005 MINTVP
.
1~-(0.127)
a.
r
0.250-0.320
(6.350-8.128)
~
0.215
D
-r
(7.239)
SEE
DETAIL A
0.004-0.006
(0.102-0.152)
m-IL
~-
0.260-0.270
h, . . . . , . . .
j
PIN '1
IDENT
r
20 19 1817 1616 14 13 12 11 - - - -
~""
I
0.2&0-0.320
(6.350 -8.128)
1
"-
JL
1'L
--l
0.008-0.012
(0.203-0.305)
DETAIL A
~ -.(~::)MAXTYP
O.015-0.019
(D.381-0.483) TYP
W2OAIRI:VD!
24 Lead Ceramic Package (W)
NS Package Number W24C
- IM-I
I-
0.080-0.090
0.030-0.040 _ _
(2.032-2~~::!±O'005
(0.762-1.016j~
(1.270±0.127)
0.590-0.625
1...
11~14.99-15.88)
_1_
0.005 MIN TVP
(0.127)
1
-t
0.250-0.3Z0
(6.350-8.1Z8)
~
D.400
(10.16)
MAXGLASS
(~::~!~~::~:)
'-
!
0.365-0.380
(9.Z71-9.65Z)
)
z
n
'
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