1989_OKI_Vacuum_Flourescent_Driver_Data_Book 1989 OKI Vacuum Flourescent Driver Data Book

User Manual: 1989_OKI_Vacuum_Flourescent_Driver_Data_Book

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DATA BOOK

OKI

VACUUM FLUORESCENT
DRIVER

FIRST EDITION
ISSUE DATE: OCT. , 1989

VACUUM
FLUORESCENT
DRIVER
DATA BOOK
1989/1990

VACUUM FLUORESCENT
DISPLAY TUBE DRIVER
LINE-UP AND TYPICAL
CHARACTERISTICS

PACKAGING

RELIABILITY INFORMATION

-DATA SHEETS

CONTENTS
1.

2.

VACUUM FLUORESCENT DISPLAY TUBE DRIVER·
LINE-UP AND TYPICAL CHARACTERISTICS . . . . • . . . . . . . . . . . . . . . . . .. .

3

PACKAGING
• 18 PIN PLASTIC DIP

............................................

10

• 28 PIN PLASTIC DIP

..... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10

• 40 PIN PLASTIC DIP

.. . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11

• 30 PIN PLASTIC SDIP

. . .. . .. ... . .. .. . . . .. .. .. .. .. .. ... .. . .. . . .. .

11

• 42 PIN PLASTIC SDIP

. .. . .. .. .. . . .. . . . . .. .. . . .. ... .. .. .. . ... . .. .

12

• 64 PIN PLASTIC SDIP

...........................................

12

• 44 PIN PLASTIC QFP ............................................

13

• 56 PIN PLASTIC QFP ............ '....... . ........................

15

• 60 PIN PLASTIC QFP ............................................

17

• 64 PIN PLASTIC QFP ............................................

18

• 32 PIN PLASTIC SOP ............................................

20

• 60 PIN PLASTIC SOP ............................................

22

• 44 PIN PLASTIC QFJ (PLCC) ......................................

23

3.

RELIABILITY INFORMATION

4.

DATA SHEETS
•

DRIVER·
MSL912

8-Bit Parallel-in Parallel-out

.. . . . . . . . . . . . ..

39

MSL915

8-Bit Parallel-in Parallel-out

... . . . . . . . . . . ..

42

MSL917

8-Bit Parallel-in Parallel-out

. . . . . . . . . . . . . .. 45

MSL918

8-Bit Parallel-in Parallel-out

............. "

MSCl163

40-Bit Anode Driver ....................•..

51

MSC7751

40-Bit Anode-Driver .......................

61

MSC7701

40-Bit Grid Driver .........................

72

MSC1150/1171/1173

10-Bitl20-Bitl32-BitAnode/Grid Driver

48

...... 83

MSC1164

20-Bit Anode/Grid Driver ..................

MSC1165

20-Bit Anode/Grid Driver .................. 100

MSC1162

40-Bit Anode/Grid Driver .................. 110

MSC1172

40-Bit Anode/Grid Driver .................. 120

MSC1149-XX

Dot Driver

MSC1187-XX

Dot Driver with Dimming Function

MSM5267B-15

Dot Driver

............................... 165

MSM5328

Dot Driver

............................... 172

MSC1178/1179

7-Segment Driver ......................... 179

MSC1190

7-Segment Driver ......................... 192

90

............................ ,. .. 133
... . . . . .. 146

o CONTROLLER
MSC7110-Xxn112-XX 12-Segment, 16 Digit/16-Segment, 12-Digit

.207

MSC1937-01

16-Segment, 16-:Digit (Alphanumeric)

...... 224

MSC1951-01

16-Segment, 16-Digit (Bargraph and Numeric) 235

MSC7125-XX

5 x 7 Dot Matrix, 8-Digit ................... 249

MSC7128-XX

5 x 7 Dot Matrix, 16-Digit ......... ~ ........ 262

o LEVEL METER

"

MSC1124

2-channeI12-Dot Level Meter IC (Static) ..... 283

MSC1146B

2-channel 15-D~,~ Level Meter IC (Dynamic) .. 294

ONE CHIP MICROCONTROLLER

MSC6458

4-Bit 1-chip Microcontroller

............... 307

VACUUM FLUORESCENT DISPLAY
TUBE DRIVER LINE-UP
AND TYPICAL CHARACTERISTICS

VACUUM FLUORESCENT DISPLAY TUBE DRIVER LINE-UP AND
TYPICAL CHARACTERISTICS '
8 bit
PARALLEL-IN
PARALLEL-OUT

H

ri'

DRIVER

H

H
J-

ANODE/GRID
DRIVER

DOT DRIVER

MSL915

I--

MSL917

"'--

MSL918

MSC7751

40 bit

J-

MSC7701

r-~

10 bit

I----

MSCl150

~

20 bit

1--

MSCl164

-

MSCl165

I

H

I--

rc

ANODE DRIVER :

GRID DRIVER

MSL912

40 bit

MSCl163

-

MSCl171

32 bit

J-~

MSCl173

40 bit

TI

I
I

*
*
*
*
*

MSCl162
MSCll72

I

MSCl149-XX

-

MSCl187-XX

-I MSM52678-15

-L

Y

H

CONTROLLER

t-

7-SEGMENT DRIVER

rl
H

12-SEGMENT
16-SEGMENT

I
I

MSCl178

H

MSCl179

-

MSCl190

16DIGIT ~

MSC7110-XX
MSC1937-01
MSC1951-01

Y
LEVEL METER

;16 DIGIT

;

H

MSM5328

5x 7 DOT MATRIX

I
I

ONE CHIP
MICROCONTROLLER

8DIGIT

r---I
r---I

16 DIGIT

!-

MSC7128-XX

STATIC

I-

MSC1124

12 DIGIT

LDYNAMIC J--I

MSC7112-XX
MSC7125-XX

MSCl1468
MSC6458·

.1

*

Under development

3

• DRIVER
J:o,

OUTPUT CURRENT

TYPE

NUMBER OF
OUTPUT

OUTPUT
VOLTAGE

SINK

SOURCE

MSL912RS

-

8

+30V

-

-40mA

MSL91SRS

-

8

-60V

-

MSL917RS

-

8

-80V

MSL918RS

-

8

+30V

MSC1149-XX RS/GS

-

DEVICE NAME

Large
Small

8
25

+18V

SHIFT
RESISTER

LATCH

EMITTER FOLLOWER + PULL DOWN

-

-

8 Drivers

-40mA

EMITTER FOLLOWER + PULL DOWN

-

-

8 Drivers

-

-90mA

EMITTER FOLLOWER

-

-

8 Drivers

-

-40mA

EMITTER FOLLOWER

-

-

8 Drivers

PUSH PULL

34

33

large O.SmA
Small O.SmA

Large -2mA
Small -a.8mA

OUTPUT CIRCUIT

REMARKS

Auto Load Circuit

MSC11S0RS

DATAISCAN

10

+60V

2mA

-2SmA

PUSH PULL

10

10

MSC1162GS

DATAISCAN

40

+6SV

2mA

-40mA

PUSH PULL

40

40

Bi-

<:>

;:!

~

Index Mark

CI:

o.soryp

Se 11 tin

~.l~tO.l0

:J)

0.30tO.l0

0.1

Pill n e

SSOP60-P-700-L

20. OOtO. 30

bu

lool

0

lfi

]

IndexMa~

d~

22

11~0±0.10

~

PLASTIC SOP
SSOP60-P-700-V1 K

20 • OOiO. 30

kJi)

@

ft

]

0:!~5iO. 10

0.30iO.l0

0
',= . '.

'I\':::-::'"

Index Mark

/

Q;
0.60TYP

Jl

~

!
Seatin

0.1

~

O~I

?~~

C>~

N_



n
c

•

A

Quality
Testong

ill
~

Shipment
Delivery

<

n ..
Storage
Control

~ ~ackaging 1

CD

3
Service

I

..

·1
.1
~

I

ReliabIlity
Englneerong

I

Failure
Report
Analysis.

Service

I
1

auality Asaurance
& Quality Control
Sill" Activities

I

....

IJ Transportation
II Control

i

~

i

r

J

~

(I)

I

r

..
.

~

r---

r- r---

Iloa""" '"' ' ' ' ' ' '1
InformatIon AnalySIS
Quality Evaluatoon
oFaolure AnalYSIS

0

Quality Management and Educatron

I.

Quality Control Program + ReliabIlIty Program
V

I

Quality Assurance
-

--

--

-

-

- -

----------

•

Acceptance Inspection
Electrical Test
Regular Check of Measuring
EQuipment

Production
Process
Wafer Process
&

Assembly

•

Production Process Ouality Control
Lot Control
EQuipment Conditions
In-Process Inspection
4 Thermal Screening
Seal Test

I
•

•
•
•

Group A Test
Group B Test
Group C Test

Early Removal of Defective Devices

Figure 2 Manufacturing Process

Devices which pass these lot guarantee inspections are stored in a warehouse awaiting shipment to customers. Standards are also set up for
handling, storage and transportation during this
period, thereby ensuring quality prior to delivery.
Figure 2 shows the manufacturing flow of the
completed device.

5) At Oki, all devices are subjected to thorough
quality checks. If, by chance, a failure does
occur after delivery to the customer, defective
devices are processed and the problem rectified
immediately to minimize the inconvenience to
the customer in accordance with the following
flowchart.

Request for
technical
improvement

r - Re~~i-;~ -I
results of
I
investigation
,~___ & improvement

...a C
(l)
--E

~.~
~
::Jco

I

Report on
results of
investigation

C'.c c.
a:(l)~E
__ _

I
L _ ~ ~!:r~v.:~e~t
Request for
manufacturing
improvement

Figure 3

Failure report process

29

•
•
•

Service
Failure Analysis
Customer Information Analysis

~

t

Target QualitY

QualitY Assurance
&
Quality Control

•
•
,.

Quality and Reliability Information
QualitY Evaluation
Defective Analysis
ReliabilitY Engineering
Quality Management and Education

•
•
•

Operation Standard
Technical Standard
Quality Standard
Design Review
Prototype Review

3. EXAMPLE OF RELIABILITY TEST
RESULTS
We have' outlined the quality assurance
system and the underlying concepts employed
by Oki. Now, we will give a few examples of the
reliability tests performed during the developmental and production prototype stages. All reliability tests performed by Oki conform to the following standards.
MIL-STD-883B, JIS C 7022, EIAJ-IC-121
Since these reliability tests must determine performance under actual working conditions in a
short period of time, they are performed under
severe test conditions. For example, the 125°C
high temperature continuous operation test performed for 1000 hours is equivalent to testing
device life from 2 to 300 years of use at Ta =
40°C.
By repeating these accelerated reliability tests,
device quality Is checked and defects analyzed.
The resulting Information is extremely useful in
rlmproving the manufacturing processes. Some
of the more common defects in LSI elements and
their analysis are described on next page.

30

Design Quality

LIFE TEST RESULTS

* MSC1162GS-V1K

;${

MSL915RS

MSM5267B-XXGS-VK

MSC7110SS

8-BIT
PARALLEL-IN
PARALLEL-OUT

DOT DRIVER

12-SEGMENT,
16-DIGIT

Part Name

Function
Test Item

High
Temperature
Bias Test

Temperature
Humidity
Bias Test

Test Condition

Sample

Te~tt-fours

Size (pc,)

or Cycle,

MSL915RS ..............

Note 1

MSM5267B-XXGS-XX

....

Note 2

MSC7110SS .............

Note 3

MSC1162GS-VIK

Note 4

........

88

Test Hours
or Cycle,

2000
(H)

0

88

2000
(H)

Failures

Sample

Testtlours

Size(pcs)

or Cycles

Failures

MSL915RS ..............

Note 1

MSM5267B-XXGS-XX

....

Note 2

MSC7110SS .............

Note 3

MSCl162GS-VIK

Note 4

........

100

Temperature
Cycling Test

- 65°C ~ RT ~ 150°C
(30 min) (5 min) (30 min)

100

Ta = 121°C RH= 100%
2 atm

50

• Note 1 (MSL915RS)
VI-GND 7V, V-GND

22

2000
(H)

1000
(H)
500
(Cy)
200
(H)

2000

88

0

100

0

22

0

100

0

50

2000
(H)

(H)

1000
(H)
500
(Cy)
200
(H)

0

100

0

22

0

100

0

50

• Note 3 (MS(7110SS)
VDD-VSS = 5.sV, VDD-VEE = 4sV

• Note 2 (MSM5267B-XXGS-VK)
VDD-GND = 18V

=60V

0

Te-stHours
or Cycles

0

88

2000
(H)

0

100

1000
(H)

0

22

500
(Cy)

0

100

200
(H)

0

50

Failures

i

85°C85% 72H STORAGE
125°C 16H BAKE

REFLOW SOLDERING PACKAGE
SURFACE TEMP
LIFE TEST

2000
(H)

0

2s0·C

REFLOW TEMP PROFILE

2000
(H)

1000
(H)
500
(Cy)
200
(H)

0

0

0

0

• Note 4(MSCl162GS-V1K)
VCC-GND = 5.sV, VHV-GND = 6sV

WTHE PRE DISPOSITION OF EACH SAMPLE

~

Sample
Size (pc,)

Referr~ Standard

MIL-STD-883C
Method 1005

-

Ta = 85°C PH=85%
Bias Condition

Ta= 150°C

=

Sample

Size (PC,)

Ta = 125°C
Bias Condition

High
Temperature
Storage

Pressure
Cooker Test

Failures

40-BIT
ANODE/GRID
DRIVER

_-....--240°C

200·C
ls0·C
100·C '--...L--L..-=-1_L-.L.....L-L-.l---lL-l.-...L._ _
(sec)
30
60
90

-

MIL-STD-883C
Method 1008
MIL-STD-883C
Method 1010

-

W
IV

ENVIRONMENTAL TEST RESULTS

Part Name

MSL91SRS

MSMS267B-

MSC7110SS

MSCl162GS-V1K

12-SEGMENT,
16-DIGIT

40-BIT
ANODE/GRID
DRIVER

XXGS-VK
Function
Test Item

Test Condition

Soldering Heat Test
Thermal
Environmental
Test

Sample Size
(pes)

DOT DRIVER
Sample Size

Failures

(pes)

Failures

Sample Size
(pes)

Sample Size
Failures

(pes)

Failures

Method 2003

Temperature
Cycling Test
I

l

Lead
Intgrity

Referred Standard

MIL-STD-883C

260·C 10 sec

I
t

Thermal Shock Test

Other
Test

8-BIT
PARALLEL-IN
PARALLEL-OUT

Tensile

Bending

Solderability

-6S·C=: RT= lS0·C
(30 min) (5 min) (30 min)
(20 cycles)

22

0

22

0

22

0

22

0

Method 1010

100·C=0·C
(5 min) (Smin)
10 cycles

MIL-STD-BB3C
Method 1911

18P/42P Dip SOOg 10sec
44P/60P Flat 100g 10 sec
18P/42P Dip 250g 90· 3 times
44P/60P Flat SOg 90· 2 times
230'C

5 sec

MIL-STD-883C

11

0

11

0

11

0

11

0

22

0

22

0

22

0

22

0

MIL-STD-883C
Method 2004

MIL-STD-8B3C
Method 2003

4. SEMICONDUCTOR MEMORY
FAILURES
The life-span characteristics of semiconductor
elements in general (not only semiconductor Ie
devices) is described by the curve shown in the
diagram below. Although semiconductor
memory failures are similar to those of ordinary
integrated circuits, the degree of integration
(miniaturization), manufacturing complexity and
other circuit element factors influence their incidence.

al conditions) in the development stage to
reduce this type of failure. In addition to checking
endurance against surge currents, special protective circuits are incorporated in the input and
output sections.

~

AI
~'

Alurr::nun:
,
vVire

Input section

~!<11'",qt7R-+
, __ "
t
t

Poly Si

Destruction
position

Semiconductor Element Failure Rate Curve

~
;;
0::
CIJ

2'OJ

u..

Initial SHIPPING
failure
~

Wear·out
Random _ _ _........=failure
failure

\
\

m>1
I

\

\
\

\

I

General
electronic
devices

,
~

___

m<1.

~:1__

I

J_--,. ;,"

'---v---"

Debugging by burn·in
screening

I

-+

/

Time

Semiconductor
elements

1) Surge Destruction
This is destruction of the input/output stage circuits by external surge currents or static electricity. The accompanying photograph shows a
point of contact between aluminum and polysilicon that has been dissolved by a surge current. A hole has formed in the substrate silicon,
leading to a short circuit. This kind of failure is
traceable in about 30% of defective devices returned to the manufacturer. Despite miniaturization of semiconductor memory co'mponent elements (which means the elements themselves
are less resistant), these failures usually occur
during assembly and other handling operations.
At Oki, all devices are subjected to static electricity intensity tests (under simulated operation-

Ex.:mplo of surge destruction

2) Oxide Film Insulation Destruction (Pin Holes)
Unlike surge destruction, this kind of failure
is caused by manufacturing defects. Local weakened sections are ruptured when subjected to
external electrical stress. Although this problem
is accentuated by the miniaturization of circuit
elements, it can be resolved by maintaining an
ultra-clean manufacturing environment and
through 100% burn-in screening.
3) Surface Deterioration due to Ionic Impurities
Under some temperature and electric field conditions, charged ionic impurities moving within the
oxide film previously resulted in occasional deterioration of silicon surfaces. This problem has
been eliminated by new surface stabilization
techniques.
4) Photolithographic Defects
Integrated circuits are formed by repeated photographic etching processes. Dust and
scratches on the mask (which corresponds to a
photographic negative) can cause catastrophic
defects. At present, component elements have
been reduced in size to the order of 10 cm
through miniaturization. However, the size of
dust and scratches stays the same. At Oki, a
high degree of automation, minimizing human intervention in the process, and unparalleled
cleanliness, solves this problem.

Photolithographic Defect

33

5) Aluminum Corrosion
Aluminum corrosion is due to electrolytic reactions caused by the presence of water and
minute impurities. When aluminum dissolves,
lines break. This problem is unique to the plastic
capsules now used widely to reduce costs. Oki
has carefully studied the possible cause and
effect relationship between structure and manufacturing conditions on the one hand, and the
generation of aluminum corrosion on the other.
Refinements incorporated in Oki LSls permit superior endurance to even the most severe high
, humidity conditions.
6) Alpha·Particle Soft Failure
This problem occurs when devices are highly
miniaturized, such as in 1 megabit RAMs. The inversion of memory cell data by alpha-particle
generated by radio-active elements like uranium
and thorium (present in minute quantities, measured in ppb) in the ceramic package material
causes defects. Since failure is only temporary
and normal operation restored quickly, this is
referred to as a "soft" failure. At Oki we have
eliminated the problem by coating the chip surface of 1 megabit RAMs with a resin which effectively screens out these alpha-particles.

7) Degradation in Performance Characteristics
Due to Hot Electrons
With increased 'miniaturization of circuit elements, internal electric field strength in the channels increases since the applied voltage remains
the same at 5V. As a result, electrons flowing in
the channels, as shown in the accompanying diagram, tend to enter into the oxide film near the
drain, leading to degradation of performance. Although previous low-temperature operation tests
have indicated an increase of this failure; we
have confirmed by our low-temperature acceleration tests, including checks on te'st element
groups, that no such problem exists in Oki LSls.

Drain

+VG

G~

~

VD

,

:

Source

P
Package ceramic

Hot electrons

Substrate silicon

Characteristic deterioration caused

by hot electrons
--:-~-:-:-:7"""7~""':"':'"'lf---:---:--c~~~ Sil icon oxide
_p~:.;;.;...:...:..:...,~:..:;,t.::;.;..."::':"":'~I'-"-"":"",:,,,,-,- film

/-t-t_ "
Q-partlcle
Ionization along
the Q·particle path

34

Substrate silicon

With further prog'ress in the miniaturization of circuit components, failures related to pin hole
oxide film destruction and photolithography have
increased. To eliminate these defects during
manufacturing, Oki has been continually improving its production processes based on reliability
tests and information gained from the field. And
we subject all devices to high-temperature burnin screening for 48 to 96 hours to ensure even
greater reliability.

Driver

I

OKI semiconductor
MSL912
a-BIT PARALLEL-IN PARALLEL-OUT

GENERAL DESCRIPTION
The MSL912 is a high voltage vacuum fluorescent display tube driver, which uses positive voltage
and contains eight circuits. Each output contains a pull-down resistor, which allows the driver to
directly drive the vacuum fluorescent display tube.
Input may be driven directly by the TTL or CMOS.

PIN CONFIGURATION
(Top View) 18 Lead Plastic DIP
IN,

OUT,
OUT2
OUT 3
OUT 4
OUTs
OUT 6
OUT 7
OUTs

V+

CIRCUIT CONFIGURATION
(1 of 8 units)

,,..---------I
I
I
I
I
I

I
I
I
I
I
I

~

70Kn

~

I
I
I
I
I
I
I

31Kn

IN

V+

OUT

1.4Kn
1S0Kn

GND

39

ELECTRICAL CHARACTERISTICS
•

Absolute Maximum Ratings
Symbol

Parameter

Limits

Unit

-0.3-35

V

- 0.5-10

V

- 0.3-35

V

+0.6--45

mA

Supply voltage

V+

Input voltage

VI

,Output voltage

Vo

Output current

10

=25°C
Ta =25°C
Ta =25°C
Ta =25°C, only one

Tstg

-

-55- + 150

°C

Symbol

Condition

Limits

Unit

Supplyvo!tage

Y+

15-30

V

Input voltage

VI

-

0-7

V

+ 0.5- -40

mA

+0.5- - 5

mA

+ 0.5x8- -40

mA

-30-+75

DC

Storage temperature

•

Condition
Ta

circuit ON

Recommended Operating Conditions
Parameter

Only one circuit
ON'"
Output current

10

Per circuit when all
circuits are ON'"
Total output
current'"

'"
•

Duty:

-

Top

Operating temperature
50% max.

DC Characteristics
(Ta =

- 30- + 75°C, TYP: Ta = 25°C)

Condition
Parameter

Unit
V + (V)

VI(V)

IO(mA)

MIN

TYP

MAX

-

2.5

-

-

V

1.0

V

20

80

JlA

0.09

0.22

mA

0.29

0.7

mA

High input toltage

VIH

30

Low input voltage

VIL

30

-

Low input current

IlL

30

1.0

IIH1

30

2.5

IIH2

30

7

High output voltage

VOH

30

2.5

-40

27

28.5

-

V

Low output voltage

VOL

30

1.0

0

-

1.0

3.0

V

ICCOFF

30

All INPUTS

0

-

0.04.

0.4

mA

2.5

0

-

12

17

mA

All INPUTS

Vo=
27V

60

150

270

KQ

High input current

Supply current

Pull-down resistor

40

Specification

Symbol

ICCON

30

RpD

30

1.0
All INPUTS

0

-

APPLICATION NOTE
OV

+25V

I

I
V+

Vee (Voo)
TIL or CMOS

Vacuum

IN MSL912RS OUT'I---~-<""')--:l~
GND

GND (Vss)

J
I
. - -_ _ _ _ _ _ _ _ _---J

b

fluorescent
display tube

OUT = _ 5- + 25V

-5V
+5V

+30V

I'

I'
V+

VeC

Vacuum
fluorescent
display tube

OUT=O- +30V

OV

(Note) When noise level on input or output signal is high, use a clamping diode.

Information furnished by OKI is believed to be accurate and
reliable. However, no responsibility is assumed by OKI for its use;
nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by
implication or otherwise under any patent rights of OKI.

41

OKI semiconductor
MSL915
8-BIT PARALLEL-IN PARALLEL-OUT

GENERAL DESCRIPTION
The MSL915 is a high voltage vacuum fluorescent display tube driver, which uses negative voltage
and contains eight circuits. Each output contains a pull-down resistor, which allows the driver to
directly drive the vacuum fluorescent display tube.
Input may be driven di rectly by the TIL or CMOS.

PIN CONFIGURATION
(Top View) 18 Lead Plastic DIP
INl

OUT l
OUT 2
OUT 3
OUT4
OUTs
OUTs
OUT 7

GND

CIRCUIT CONFIGURATION

(1

of 8 units)

.-----~--~----~----~-oGND
I
I

I
I

IN

I
I

17KQ

~
I

I
I
I

I
I

14KQ

~~~----~--OOUT

lAKQ
1S0KQ

~------------------------~----~~v-

42

ELECTRICAL CHARACTERISTICS
•

Absolute Maximum Ratings
Symbol'

Parameter

Condition

Limits

Unit

V-

Ta=25°C

GND + 0.3-GND - 65

V

Input voltage

VI

Ta=25°C

GND + 0.5-GND -10

V

Output voltage

Vo

Ta = 25°C

GND + 0.3-V - - 0.5

V

Output current

10

Ta = 25°C, only one
circuit ON

+ 0.9- -45

mA

Tstg

-

- 55- + 150

°C

Symbol

Condition

Limits

Unit

V-

-

GND - 20-GND - 60

V

GND-GND-7

V

Only one circuit
ON*

+ O.S- -40

mA

Per circuit when all
circuits are ON*

+ O.S- - 5

mA

+O.SxS- ~40

mA

- 30- + 75

°C

Supply voltage

Storage temperature

•

Recommended Operating Conditions
Parameter
Supply voltage
Input voltage

VI

Output current

10

Total output
current·
Operating temperature

•
•

Duty:

-

Top'
50% max.

DC Characteristics
(Ta = - 30",:, + 75°C, TYP: Ta = 25°C)
Condition
Parameter

Specification

Symbol

Unit
V-(V)

VI(V)

IO(mA)

MIN

TYP

MAX

-

-

-

-

- 1.S

V

-

V

-70

-280

}lA

- 0.23

-1.2

mA

- 0.58

- 2.6

mA

- 1.5

-3

V

High input voltage

VIH

-60

Low input voltage

VIL

- 60

High input current

IIH

-60

-1.5

IIL1

-60

-4

IIL2

-60

-7

High output voltage

VOH

-60

-4

-40

Low output voltage

VOL

-60

- 1.5

0

- 55

- 59

-

V

ICC OFF

-60

All INPUTS

0

-

0.7

1.3

mA

6

12

mA

60

150

270

KQ

Low input current

Supply current
ICCON
Pull-down resistor

RpD

-60
-60

- 1.5
All INPUTS

-4

0

All INPUTS

Vo=
-3V

0

-4

-

43

APPLICATION NOTE
+5V

cr
I

J

Vee (voo)

GND

TIL or CMOS

IN MSL915RS OUT

GND(Vss)

V-

OV

-SSV

Vacuum

I---~<-)-~~
.

~

fluorescent
display tube

OUT = + 5- - 5SV

ov
9
T

I

Vee (VOO)

GND

TIL or CMOS
GND (Vss)

v-

1

-SV

V&uum

IN MSL91SRS OUT I---«-)-~Oo-j

"----

fluorescent

display tube
OUT=O--60V

-60V

(Note) When noise level on input or output signal is high, use a clamping diode.

Information furnished by OKI is believed to be accurate and
reliable. However, no responsibility is assumed by OKI for its use;
nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by
implication or otherwise under any patent rights of OKI.

44

OKI semiconductor
MSL917
8-BIT PARALLEL-IN PARALLEL-OUT

GENERAL DESCRIPTION
The MSL917 is a high voltage vacuum fluorescent display tube driver, which uses negative voltage
and contains eight circuits. Each output does not contain a pull-down resistor, hence it should be
connected to an external resistor (about 150KQ).
Input may be driven directly by the TIL or CMOS. The vacuum fluorescent display tube driver may
also be used as a high voltage·and current driver.

PIN CONFIGURATION
(Top View) 18 Lead Plastic DIP
OUT,
OUT2

OUT 3

OUTs
OUT 6
OUT 7

GND

CIRCUIT CONFIGURATION
(1 of 8 units)
IN

GND
I
I
I
I
I
I

o---~I--~--~~----;
I
I
I
I
I

12KQ

~

I

I

~
I
I
I
I
I
I

1KQ

I
I
I
I
I
I
I
I
I
I

OUT

L--------------------------------r"')OV45

ELECTRICAL CHARACTERISTICS
•

Absolute Maximum Ratings
Symbol

Condition

Limits

Unit

Supply voltage

V-

Ta=25°C

GND + 0.3-GND - 85

V

Input voltage

VI

Ta=25°C

GND + 0.5-GND - 10

V

Output voltage

Vo

Ta=25°C

GND + 0.3-GND - 85

V

Output current

10

Ta = 25°C, only one
circuit ON

0- - 100

mA

Tstg

-

Parameter

Storage temperature

o

~

°C

150

Recommended Operating Conditions
Symbol

Condition

Limits

Unit

Supply voltage

V-

GND - 20-GND - 80

V

Input voltage

VI

-

Parameter

Output current

10

Operating temperature
*

•

- 55-

GND-GND-7

V

Only one circuit
ON*

0--90

mA

Per circuit when all
circuits are ON*

0- -11

mA

Total output
current

0--90

mA

-30- + 75

°C

-

Top

Duty:

50% max.

DC Characteristics
(Ta = - 30- + 75°C, TYP: Ta = 25°C)
Condition
Parameter

Unit
V-{V)

V,{V)

10(mA)

RL(Q)

MIN

TYP

MAX

-

-

-

- 1.5

-4

-

High input voltage

V'H

-80

-

Low input voltage

VIL

-80

-

High input current

IIH

-80

-/1.5

Low input current

11L1

-80

-4

IIL2

-80

-7

-

VOH

-80

-4

-90

-

0

*1
150K

-75

-79

-

-

*1
150

-

0.7

1.3

mA

-

*1
150K

-

8

14

mA

High output voltage
Low output voltage

VOL

-80

ICCOFF

-80

ICCON

-80

-1.5
All INPUTS

-1.5

Supply current

* 1 RL connection method
46

Specification

Symbol

All INPUTS

-4

-

-

-

V
V

-70

-280

llA

-0.23

- 1.2
-2.6

mA

-0.58
-2.0

-3.0

V

mA

V

RL CONNECTION METHOD
GND

f

.....
~

...,

.....
...,

...,
~

I,

0,

I
I
I
I
I
I
I
I
I
I

I
I
I
I
I
I
I
I
I

,-

1-1l - I -i -

I

Is

Os

I

b

V-

APPLICATION NOTE+5V

9

I

I

Vee (Voo)
TIL or CMOS

GND

GND (V 55)

b

IN MsL917Rs OUT
V-

Vacuum
~

• ~

b

,OV

fluorescent

R

display tube
OUT= + 5- -75V

-75V

OV

cr
r

I

Vee (Voo)
TIL or CMOS
GND (Vss)

1
-SV

GND
IN MSL917RS OUT
V-

Vacuum
~

fluorescent

>RL~

display tube

L

b

OUT=O--80V

-80V

(Note) When noise level on input or output signal is high, use a clamping diode.

Information furnished by OKI is believed to be accurate and
reliable. However, no responsibility is assumed by OKI for its use;
nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by
implication or otherwise under ilny pJtcnt rights of OKI.

47

OKI semiconductor
MSL918
8-BIT PARALLEL-IN PARALLEL-OUT

GENERAL DESCRIPTION
The MSL918 is a high voltage vacuum fluorescent display tube driver, which uses positive voltage
and contains eight circuits. Each output does not contain a pull-down resistor, hence it should be
connected to an external resistor (about 150 KQ).
Input may be driven directly by the TIL or CMOS. The vacuum fluorescent display tube driver may
also be used as a high voltage and current driver.

PIN CONFIGURATION
(Top View) 18 Lead Plastic DIP

CIRCUIT CONFIGURATION
, (1 of 8 units)

r----------+------+-----+-------+-1---n V+

I
I
I
I

I
I
I
I
I
I

I

I
I

....L.

~\

¢.

I
I
I
I

:.

31KO

IN

1.4KO

OUT

18KO

GND

48

I
I
I
I
I
I
I
I
I
I

ELECTRICAL CHARACTERISTICS
•

Absolute Maximum Ratings
Parameter

Symbol

Condition

Limits

Unit

Supply voltage

V+

Ta=25°C

-0.3- +35

V

Input voltage

VI

Ta=25°C

-0.5- + 10

V
V

Output voltage

Vo

Ta=25°C

-0.3-V+

Output current

10

Ta = 25°C, only one
circuit ON

-45

rnA

Tstg

-

- 55- + 150

°C

Symbol

Condition

Limits

Unit

V+

-

+15-+30

V

Storage temperature

o Recommended Operating Conditions
Parameter
Supply voltage
Input voltage

Output current

10

Operating temperature

*

•

0-+7

V

Only one circuit
ON*

0--40

mA

Per circuit when all
circuits are ON*

0- -11

mA

Total output
current*

0--90

rnA

- 30- + 75

°C

VI

Duty:

-

Top
50% max.

DC Characteristics
(Ta = - 30- + 75°C, TYP: Ta = 25°C)
Condition
Parameter

Specification
Unit

Symbol
V+(V)

VI(V)

10(mA)

RL(Q)

MIN

TYP

MAX

-

2.5

-

V

-

-

-

1.0

V

-80

pA

0.15

mA

0.5

mA

-

V

3.0

V

0.4

mA

14

mA

High input voltage

VIH

+30

Low input voltage

VIL

+30

-

Low input current

IlL

+30

1.0

High input current

IIHl

+ 30

2.5

-

IIH2

+30

7

-

High output voltage

VOH

+30

2.5

Low output voltage

VOL

+30

1.0

Icc OFF

+30

All INPUTS

ICCON

+30

1.0

-40

-

27

0

*1
150K

-

-

*1
150

-

-

-

*1
150K

-

9.5

Supply current
All INPUTS

* 1 RL connection method

2.5

-20

Rl CONNECTION METHOD
V+

f
.....

.....
.....
.....
.....
.....

.....
.....

I,

01

I

I

I
I
I
I
I
I
I
I

I
I
I
I
I
I
I
I

- r-- r-

~

I

I

IS

Os

1
1

.0

GND

APPLICATION NOTE
OV

+2SV

I

I

VeC25°C

145

0c/w

2

Operating
Temperature

'Top

Thv::;i50V

-40- +85

°C

-

Storage
Temperature

Tstg

-

- 55- + 150

°C

-

Input Voltage

NOTES:

860 [Derate 6.9
mW/C above 25°C]

1) Maximum Supply Voltage for GND
2) Derate 6.9 mW/Ck above 25°C
Refer to the following formula.
Tj

56

=P x Rj - a + Ta (P:

Max current consumption)

•

Recommended Operating Conditions

Parameter

Symbol

Condition

Min.

Max.

Unit

Logic Supply
Voltage

Vee

Applicable to logic supply voltage
terminal

4.5

5.5

V

Driver Supply
Voltage

Vhv

Applicable to driver supply voltage
terminal

10

65

V

High Level Input
Voltage

Vih

Applicable to all input
terminals

Vee=4.5V

3.6

V

Vee= 5.5V

4.4

Vii

Applicable to all output
terminals

Vee= 4.5V

-

0.9

V

low level Input
Voltage
Driver High level
Output Current

lohvh

Driver low level
Output Current

lohvl

ClK Frequency

V

V ee =5.5V

-

1.1

V

Applicable to all driver output terminal

-

-2

rnA

Applicable to all driver output terminal

-

2

rnA

f

See timing chart

-

4

MHz

twclk

See timing chart

75

-

ns

Data in Setup
Time

tds

See timing chart

50

-

ns

Data in Hold
Time

tdh

See timing chart

50

-

ns

twls

See timing chart

80

-

ns

ClK - LS Delay
Time

tdcl

See timing chart

50

-

ns

LS - ClK Delay
Time

tdle

See timing chart

0

-

ns

LS - CHG Delay
Time

tdleg

See timing chart

0

-

ps

LS- Cl Delay
Time

tdld

See timing chart

0

-

ps

twehg

See timing chart

2

-

ps

twd

See timing chart

2

-

ps

Top

-

-40

+85

°c

ClK Pulse width

lS Pulse Width

CHG Pulse Width

I
Cl PUlse width
Operating
Temperature

57

•

DC Characteristics

Parameter
Logic Standby
Current

Vcc=5V± 10%, Vhv= 10V-65V, Ta= -40°Cto + 85°C

Symbol
Icc 1

Condition
No Load
Vee= 5.5V

Icc 2
Driyer Standby
Current

IhV1

No Load
Vee = 5.5V

'hV 2
High Level Input
Voltage

Vih

Min.

Typ.

Max.

Unit

-

4.3

6.65

All Input: High, All
Driver Output: High,
Ta = 25°C

-

0.5

1.0

All Driver Output: Low

-

-

'1

pA

All Driver Output:
High, Ta = 25°C

-

2.45

3.8

mA

Vee=4.5V

3.15

-

Vee= 5.SV

3.85

V

Vee = 4.SV

-

-

1.35

V

-

1.65

V

-

±1

pA

All Input:

Low

rnA

V

Low Level Input
Voltage

Vii

Input Leakage
Current

'in

Ta= 25°(

-

Input
Capacitance

Cin

Ta= 25°C

-

15

-

pF

Vee=4.SV

4.2

-

Vee = 5.5V

5.2

-

'v

Vee = 4.5V

-

High Level Data
Output Voltage

Vodh 1

Vee=5.5V

10= - 20pA

Low Level Data
Output Voltage

Vodl1

10 = 20pA

High Level Data
Output Voltage

Vodh2

10= -0.1mA

Low Level Data
Output Voltage

Vodl2

Driver High Level
Output Voltage

Vohvh

Vee= 5.5V

10=0.1mA

-

Vee=4.5V

3.5

Vee =5.5V

4.5

Vee=4.5V
Vee= 5.5V
'ohv= - 2mA

-

-

V

0.2

V

0.2

V

-

V

-

V

1.1

V

1.1

V

-

-

V

-

3.0

V

-

-

Vhv-3

-

,

Driver Low Level
Output Voltage

58

Vohvl

'ohv=2mA

o AC Characteristics
Vcc=5V, Vhv=65V, Ta=25°e
Item

Symbol

Remarks

Min.

Typ.

Max.

Unit

-

100

150

nS

elK - Dout Delay Time

tpd

See timing chart and test circuit

DelayTime low - High

tdlh

See timing chart and test circuit

-

0.3

1

}lS

Transit Time low - High

ttlh

See timing chart and test circuit

2

5

}lS

DelayTime High - low

tdhl

See timing chart and test circuit

0.3

1

}lS

Transit Time High - Low

tthl

See timing chart and test circuit

-

2

5

}lS

o Timing Chart

TEST CIRCUIT

20pF

Vee

Vhv

30KO

65V

s.OV

DOUT

30pF

Information furnished ·by OKI is believed to be accurate and
reliable. However, no responsibility is assumed by OKI for its use;
nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by
implication or otherwise under any patent rights of OKI.

60

OKI semiconductor
MSC7 751

(Underdevelopment)

40-Bit ANODE DRIVER

GENERAL DESCRIPTION
The MSC7751 is a monolithic IC using the high withstand voltage driver process for hybridizing
CMOS and DMOS transistors on one chip.
The logic portion such as the input stage, shift register and latch is formed b,y CMOS, and the
output driver requiring a high withstand voltage is formed by DMOS transistors.
Since the pin assigment allows single side pattern formation on the printed circuit board, the
display unit can be reduced.
The bidirectional shift register facilitates the pattern design when the devices are arranged
symmetrically with the display at the center axis.

FEATURES
o

Logic supply voltage

+5V

o

VF driver supply voltage

-200V

o

Driver output current
(Iohvh)
(Iohvl)

- 2 mA (All driver output high)
+2mA

o

Clock frequency

o

Built-in 40-bit latch

o

Built-in 40-bit bidirectional shift register

o

60 Pi n FLAT Package

5.5 MHz

61

BLOCK DIAGRAM

Vee

51150

LS

VHV
VHV
(1-20) (21-40)

CL

FIB

CLOCK
HV01

RESET

HV02

....
t:
25°C

145

°CJW

-40- +85

°C

- 55- + 150

°C

Power Dissipation

Pd

Attenuation Rate

Rj-a

Operating temperature

Top

Storage temperature

Tstg

Ta~

VHV~

130V

---

2

Notes: 1. The maximum voltage which can be applied to the GND terminal.
2.

Thermal resistance ofthe package (between junction and
atmosphere).
The junction temperature (Tj) expressed by the equation
indicated below should not exceed 150°C.
Tj = p'x Rj - a + Ta (P: Maximum power consumption of IC)

67

•

Recommended Operating Conditions
Parameter

Symbol

Conditions

MIN

MAX

Unit

Logic supply voltage

Vee

Applicable to logic power
terminal

4.5

5.5

V

Driver supply voltage

VHV

Applicable to driver power
terminal

10

200

V

High level input voltage

VIH

Applicable to all

Vee=4.5V

3.6

-

V

input terminals

Vee = 5.5V

4.4

-

Applicable to all

Vee=4.5V

-

0.9

input terminals

Vee= 5.5V

-

1.1

Low level input voltage

VIL

V

Driver high level output
current

IOHVH

Applicable to all driver output
terminals

-

-2

mA

Driver low level output
current

IOHVL

Applicable to all driver output
terminals

-

2

mA

f0

See Timing chart

-

5.5

MHz

twclkl

See Timing chart

70

nS

Data setup time

tds

See Timing chart

20

-

Data hold time

tdh

See Timing chart

45

-

nS

LS pulse width

twls

See Timing chart

80

nS

CLK-LS delay time

tdcl

See Timing chart

45

LS-CL delay time

tdlcl

See Timing chart

0

-

CL pulse width

t wcl

See Timing chart

2

-

115

Operating temperature
range

Top

See Timing chart

-40

+85

°C

Clock frequency
Clock pulse width

nS

nS
nS

•

DC Characteristics
Parameter
Logic supply current

Symbol
ICCl

Conditions

MIN

TYP

MAX

Unit

No load

All inputs

: Low

-

-

50

Vce" 5.5V

All inputs

: High

-

-

200

-

-

50

}lA

2.5

4.0

mA

1.35

V

ICC2

All driver outputs : High

llA

Driver supply

IHVl

No load

All driver outputs : Low

current

IHV2

Vcc =5.5V

All driver outputs : High

High level input

VIH

Vcc =4.5V

Applicable to all input

3.15

Vcc =5.5V

terminals

3.85

Vcc =4.5V

Applicable to all input

-

-

Vcc =5.5V

terminals

-

-

1.65

V

-

-

±1

}lA

voltage
Low level input

VIL

voltage

Input leak current

IILEEK

Ta =25°C

Input terminals except CL
terminal

High level input

IIH

current
Input capacity
High level data

CIN
. VODH

20

50

100

25

60

200

Ta = 25°C

-

15

Vcc=4.5V

3.5

-

Vcc=5.5V

4.5

-

-

-

VODL

0.9

10=

~O.lmA

output voltage
High level driver

Low level driver

Vcc =4.5V
Vcc=5.5V

1.1

VOHVH

IOHv= -2mA

195

-

-

VOHVL

IOHv=2mA

-

-

5

output voltae

output voltae

Applicable to

10= -O.lmA

output voltage
Low level data

a: terminal

Vcc =5.5

Vcc=4.5V

V
V

}lA
pF

V

V

V

V

69

•

AC Characteristics

Parameter

Symb.ol

Conditios

MIN

TYP

MAX

Unit

Note

ClK-DOUT delay time

tpd

See Timing Chart and
Test Circuit

-

100

150

nS

4

Delay time :

l~H

tdlh

See Timing Chart and
Test Circuit

-

0.3

1

lIS

5,6

Transit time:

l~H

ttlh

See Timing Chart and
Test Circuit

-

2

5.

lIs

5

Delay time :

H~l

tdhl

See Timing Chart and
Test Circuit

-

0.3

1

lIs

5,6

Transit time:

H~l

tthl

See Timing Chart and
Test Circuit

-

2

5

lIs

5

Note 4:
Note 5 :
Note 6 :

•

Applicable to data output terminal.
Applicable to driver output terminal.
tdlh and Tdhl are delay times from CL signal.

Timing Chart
11f0

CLOCK

DIN

DOUT

lS

Cl

HWO{1, 2, 39, 40)

HVO(OTHERS)
ttlh

70

TEST CIRCUIT

20pF

Vee

Vhv

HVOl
100KQ

HV02

200V

I-----<:l~~

S.OV

30pF

Information furnished by OKI is believed to be accurate and reliable.
However, no responsibility is assumed by OKI for its use; nor for any
infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise
under any patent rights of OKI.

71

OKI semiconductor
M 5C7701

(Underdevelopment)

40-BIT GRID DRIVER

GENERAL ,DESCRIPTION
The MSCn01 is a monolithic IC using the high withstand voltage driver process for hybridizing
CMOS and DMOS transistors on one chip.
The logic portion such as the input stage, shift register and latch is formed by CMOS, and the
output driver requiring a high withstand voltage is formed by DMOS transistors.
Since the pin assigment allows single side pattern formation on the printed circuit board, the
display unit size can be reduced.
The bidirectional shift register facilitates the pattern design when the devices are arranged
symmetrically with the display at the center axis.

FEATURES
•

Logic supply voltage

+sV

•

VF driver supply voltage

+ 130V

•

VF driver output current
(Iohvh)

- 40 mA (1 driver output high)

(Iohvl)

+ 2 mA

•

Clock frequency

•

Built-in 40-Bit latch

•

Built-in 40-Bit bidirectional shift register

GI

60 Pin FLAT Package

72

5.5 MHz

BLOCK DIAGRAM

Vee

VHV
VHV
(1-20) (21-40)

51/50

L5

Q1

1,

L,

·Q2

12

L2

FIB

CLOCK
HVO 1

RESET
~

w

f-

HV02

~
l!)

w

~

fu...

:c
VI

:c
U

Z

g

6w

Cil
0

...J

~

....

0

o:::t

~

£5

iii

.....

Cil
6
o:::t

Q40

140

HV040

L.:40

D40

SO/51

GND

73

PIN CONFDIGURATION

(Top View) 60 Lead Plastic Flat Package

HVO 36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
37
38
39
40

74

0

HVO

5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
4
3
2

NC
VHV
NC
GND
NC
L5
NC
Vee
NC

NC
CL
NC
CLOCK
NC
RESET

50/51

51/50

NC
VHV
FIB.

PIN DESCRIPTION
Pin No.
1

Symbol
HVO

Name
1

Description

Driver output

1. Each terminal is a high withstand voltage driver
output terminal to drive the grid of the VF
display tube, which corresponds to each bit of
the shift register.
2. Each terminal can be directly connected to the
grid termi nal of the VF display tube.

20
411
60

HVO 40

22
39

VHV

Driver supply
voltage

1. This is a power terminal of the high withstand
voltage driver to drive the VF display tuve.

28

Vee

Logic supply
voltage

2. This is a power terminal of the logic portion.

36

CL

Clear input

1. This is an input terminal containing a pull-down
resistor.
2. The terminal is generally kept High. The driver
output, High or Low, is driven by the output of
the corresponding latch circuit.
3. When the terminal is Low, the driver outputs
are fixed to, "Low" regardless of the output of
the latch circuit.

26

LS

Latch strobe input

1. When the terminal is High, the latch circuit is
slewed, and the output of the shift register is
read into the latch circuit.
2. When the terminal is Low, the latch circuit holds
the output of the shift register immediately
before the terminal is turned Low.

34

CLOCK

Clock input

1. This is a clock terminal of the shift register. -The
data of the shift register is shifted at the falling
edge of a clock pulse.

32

RESET

Reset input

1. When the terminal is Low, all the data of the
shift register is Low. Generally and when not in
use, connect the terminal to the Vee terminal.

38

FIB

Shift direction
control input

1. When the terminal is Low, data is shifted from 1
to 40, and Pin 31 is a serial in terminal and Pin 30
is a serial out terminal.
2. When the terminal is High, data is shifted from
40 to 1, and Pin 30 is a serial in terminal and ~in
31 is a serial out terminal.

31

51/50

Serial input/serial
output

1. When the FIB terminal is Low, this terminal is a
serial data input terminal.
2. When the FIB terminal is High, this terminal is a
serial data output terminal.

30

50/51

Serial output/serial
input

1. When the FIB terminal is Low, this terminal is a
serial data Q.utput t~rminal.
2. When the FIB terminal is High, this terminal is a
serial data input terminal.

24

GND

GND

1. This is a grounding (GND) terminal.

75

SCHEMATIC DIAGRAMS OF LOGIC PORTION INPUT AND OUTPUT
TERMINAL CIRCUITS
Input terminal

GND
GND

Input -output terminal

---1

GND

5f150
SO/51

GND

76

GND

SCHEMATIC ,DIAGRAM OF DRIVER OUTPUT TERMINAL CIRCUIT
VHV

VHV

HVO

-~
GND

GND

FUNCTION TABLE

Q40

SO/51

L

L

L

L

L

L

L

L

X

H

Q'n

Q2n

Q38n

Q39n

Q39n

L

L

Q'n

Q2n

Q38n

Q39n

Q39n

H

Q2n

Q2n

Q3n

Q4n

Q40n

H

H

H

Q2n

Q2n

Q3n

Q4n

Q40n

L

L

CL

L5

Qn

HVOn

L

X

X

L

H

H

H

H

H

H

L

L

H

L

X

NC

CLK

F/B

51/50

Ql

Q2

Q3

L

X

L

X

L

L

L

X

H

L

L

L

H

L

H
H
H
H

----

Q39

RESET

L
L
L
L

L:
X:

Low Level,
Don't Ca~e,

H : High Level
NC : No Change

77
-6-

ELECTRICAL CHARACTERISTICS
•

Absolute Maximum Ratings
Symbol

Conditios

Limits

Unit

Note

Logic supply voltage

Vee

Applicable to logic
power terminal

- 0.3-6.5

V

1

Driver supply voltage

VHV

Applicable to
driver power
terminal

Vee- 15O

V

1

Input voltage

VIN

Applicable to all
input teminals

- 0.3-Vee + 0.3

V

1

Data ouptput voltage

Vod

Applicable to data
output terminal

- 0.3-Vee + 0.3

V

1

Driver output voltage

Vohv

Applicable to all
driver terminals

- 0.3-Vee + 0.3

V

1

25°C

860

mW

Ta>25°C

145

0c/w

-40- + 85

°C

- 55- + 150

°C.

Parameter

Power E>issipation

Pd

Attenuation Rate

Rj-a

Operating temperature

Top

Storage temperature

Tstg

Ta~

VHV~

130V

---

Notes: 1. The maximum voltage which can be applied to the GND terminal.
2. Thermal r~sistance of the package (between junction and
atmosphere).
The junction temperature (Tj) expressed by the equation
indicated below should not exceed 150°C.
Tj = P x Rj - a + Ta (P : Maximum power consumption of IC)

78

2

•

Recommended Operating Conditions
Parameter

Symbol

Conditions

MIN

MAX

Unit

Logic supply voltage

Vee

Applicable to logic power
terminal

4.5

5.5

V

Driver supply voltage

VHV

Applicable to logic power
terminal

10

130

V

High level input voltage

Applicable to all

Vee= 4.5V

3.6

VIH

-

input terminals

Vee= 5.5V

4.4

-

Applicable to all

Vee=4.5V

-

0.9

input terminals

Vee = 5.5V

-

1.1

-

-40

mA

2

mA

5.5

MHz

Low level input voltage

VIL

Driver high level output
current

IOHVH

1 driver output
Other driver outputs

Driver low level output
current

IOHVL

Applicable to all driver output
terminals

: High
: Low

V

V

f0

See timing chart.

-

twclkl

See timing chart.

70

Data setup time

tds

See timing chart.

20

Data hold time

tdh

See timing chart.

45

LS pulse width

twl s

See timing chart.

80

-

CLK-LS delay time

tdcl

See timing chart.

45

-

nS

LS-CL delay time

tdlcl

See timing chart.

0

nS

CL pulse width

t wcl

See timing chart.

2

-

Top

See timing chart.

-40

Clock frequency
Clock pulse width

Operating temperature

+85

nS
nS
nS
nS

lIS
°C

79

•

DC Characteristics

Parameter
Logic supply current

Symbol
ICC1

Conditions
No load

All inputs

vee = S.SV

All inputs
: High
: High
1 driver output
Other driver outputs: Low

ICC2

IHV1

Noload

All driver outputs : Low

current

IHV2

vee = S.SV

1 driver output,

High level input

VIH

Driver supply

voltage
Low level input

VIL

voltage
Input leak current

High level input

IILEEK

IIH

current
Input capacitance
High level data

CIN
VODH

Low level data

VODL

Low level driver

-

-

50

Unit

pA

-

-

200

-

-

50

llA

1.1

1.5

mA

-

Applicable to all input

3.15

-

vee = S.SV

3.85

1.35

V

V

vee = 4.SV

Applicable to all input

-

-

Vee= S.SV

terminals

-

-

1.65

V

Input term inals except CL

-

-

±1

llA

20

50

100

Vee= S.SV

25

60

200

Ta =2S0C

-

15

vee= 4.SV

3.5

-

vee=s.sv

4.5

-

-

0.9

Ta = 25°C
Vee=4.SV

10= -O.1mA

10= -O.1mA

terminal
Applicable to

Vee=4.SV
vee= s.sv

a: terminal

1.1

V

llA
pF
V

V

VOHVH

10Hv= -40mA

106

-

-

V

VOHVL

IOHV=2mA

-

-

4

V

output voltae

output voltae

MAX

terminals

output voltage
High level driver

: High

TYP

vee = 4.SV

output voltage

80

: Low

MIN

o

AC Characteristics

v'rr= 5V
Parameter

Symbol

CLK-DOUT delay time

tpd

V f.lv=

a=

MIN

TYP

MAX

Unit

Note

See timing chart
and test chart.

-

100

150

nS

4

Conditios

Delay time :

L~H

tdlh

See timing chart
and test chart.

-

0.3

1

}ls

5,6

Transit time:

L~H

ttlh

See timing chart
and test chart.

-

2

5

}lS

5

Delay time :

H~L

tdhl

See timing chart
and test chart.

-

0.3

1

}ls

5,6

Transit time:

H~L

tthl

See Timing chart
and test chart.

-

3

6

}ls

5

Note 4:
Note 5:
Note 6:

o

Applicable to data output terminal.
Applicable to driver output termin~
tdlh and Tdhl are delay times from CL signal.

Timing Chart
l/f0

DIH

DOUT

LS

CL

HVO( 1, 2, 39, 40)

HVO(OTHERS)

81

TEST CIRCUIT

20pF

Vhv

Vee

HVOl
3.2KQ

HV02
I

130V

I
I,
I
I
I
I
I
I
I

S.OV

I

HV040

50/51
~
-J

u

VI
-J

co

IU:

I~

or

Id

0
2
l!1

51/50

J

Information furnished by OKI is believed to be accurate and reliable.
However, no responsibility is assumed by OKI for its use; nor for any
infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise
under any patent rights of OKI.

82

OKI semiconductor
MSC1150/ MSC1171 / MSC1173

(Underdevelopment)

10-bit/20-bit/32-bit ANODE/GRID DRIVER

GENERAL DESCRIPTION
The MSC1150/MSC1171/MSC1173 are vacuum fluorescent display tube. ICs which consist of shift
registers, latches and VF driver outputs.

FEATURES
o

60-V output Voltage Swing Capability

•

2S-mA output Source Current Capability

•

Latches on all Driver outputs

•

POWER-aN-RESET circuit built in

BLOCK DIAGRAM

01

ON

vee

BLANKING

N bit LATCH

LATCH
ENABLE

DATA IN

D

11'

IN'
N bit SIR

CLOCK

D

R

SERIAL
OUT

83

PIN CONFIGURATION
MSC1150RS
DUAL-IN-LiNE PACKAGE
(TOP VIEW)
Q8

Q7~

Q6~

r;-o-;a
Q9
2
171= Ql0

3
4
5
6
LATCH ENA8LE(STROBE); 7
Q5~ 8

16=
15
14
13
.12;
111=

CLOCK

GND~
Voo ~

Q4L-~

SERIAL DATA OUT
Vee
DATAIN
BLANKING
Ql
Q2
Q3

MSC1171RS
DUAL-IN-LiNE PACKAGE
(TOP VIEW)
Vee
SERIAL OUT
Q20
Q19
Q18
Q17
Q16
Q1S
Q14
Q13
Q12
Qll
BLANKING
GND
~

~ 1

U

~2

28
27
26
25
24
23

~3
4
~ 5
~6
~7
F8
9
10

F
22F
21
20
19
F
18
F
171=
16
15 ...

~ 11
F 12

~13
14

Voo
DATA IN
Ql
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Ql0
LATCH ENABLE
CLOCK

MSC1173RS
DUAL-IN-LiNE PACKAGE
(TOP VIEW)
1
Vee
SERIAL OUT 2
3
Q32
4
Q31
Q30
5
6
Q29
Q28 7
Q27 8
Q26 9
10
Q25
Q24 Fll
Q23 F 12
Q22 F13
Q21
14
Q20
15
16
Q19
Q18 ~ 17
Q17 ~ 18
BLANKING ~ 19
20
GND

84

u

40
39
38
37
36
35
34 1=
33
32 1=
31 1=
30
29
28
27
26
25
24
23
22
21

Voo
DATA IN
Ql
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Ql0
Qll
Q12
Q13
Q14
Q15
Q16
LATCH ENABLE
CLOCK

.'

ELECTRICAL CHARACTERISTICS
•

Absolute Maximum Ratings

Parameter

Symbol

Limits

Unit

Logic Supply Voltage

Vdd

- 0.3 -- 6.5

V

Driver Supply Voltage

Vee

- 0.3 -- 65

V

Input Voltage

Vin

- 0.3 -- Vdd + 0.3

V

10

30

mA

1300 (Ta = 25°C)

mW

1200 (Ta = 25°C)

mW

1000 (Ta = 25°C)

mW

Maximum Output Current
Package Power
Dissipation

MSCl173RS
MSCl171RS

Pd

MSCl150RS

Operating Temperature

Top

-40 -- 85

°C

Storage Temperature

Tstg

- 55 -- 150

°C

85

DC Characteristics

•

Ta = - 40°C to + 85°C, Vdd = 4.5V to 5.5V, Vee = 1OV to 60V unless otherwise specified.
Parameter

Symbol

Conditions

Min

Max

Unit

Logic Supply Voltage

Vdd

4.5

5.5

V

. Driver Supply Voltage

Vee

10

60

V

Logie Supply Current

Idd

MSCl150
MSCl171

1
2

mA
mA

MSCl173

3

mA

MSCl150

4

mA

MSCl171

6
7

mA

MSCl150
MSCl171

3
4

mA
mA

MSCl173

6

mA

All Outputs Low

0.1

mA

-

V

All Outputs High

All Outputs Low

MSC1173
Driver Supply Current

lee

mA

All Outpts High (No Load)

High Level Input Voltage

Vih

0.7Vdd

Low Level Input Voltage

Vii

-

0.8

V

High Level Input Current

lih

Vih =Vdd

-

1

pA

Low Level Input Current

Iii

Vii = Gnd

-

-1

pA

High Level Output Voltage
(Q Outputs)

Vohl

lohl = - 25mA

Low Level Output Voltage
(Q Outputs)

Voll

V

-

3

V

1011 = 200pA

-

1.5

V

-

V

0.8

V

Voh2

loh2 = - 20pA

Low Level Output Voltage

Vol2

101 =20pA

86

-

1011=lmA

High Level Output Voltage
(Serial Out)

(Serial Out)

Vee- 3.5

Vdd - 0.5

-

o

AC Characteristics

Ta = - 40°C to + 85°C, Vdd = 4.5V to 5.5V, Vcc = 1OV to 60V unless othervise specified.

Parameter

Symbol

Conditions

Min

Max

Unit

Clock Frequency

f {CLOck}

See Figure 1

-

1

MHz

Pulse Duration, Clock High

tw {CKH}

See Figure 1

250

-

nS

Pulse Duration, Clock Low

tw {CKL}

See Figure 1

250

-

nS

tsu

See Figure 1

100

-

nS

th

See Figure 1

100

-

nS

td

CL = 15pF, See Figure 1

-

600

nS

Setup Time, Data Before Rising

"

Clock Edge
Hold Time, Data After Rising
. Clock Edge
Delay Time, Clock to Serial Out
Delay Time, Colck Rising Edge to

tCKH-LEH

See Figure 2

200

-

nS

tw {LEH}

See Figure 2

250

-

nS

-

1.5

11S

1

11S

Latch Enable High
Pulse Duration, Latch Enable
High
Delay Time, High-to-Low Level Q

tDHL

from LATCH ENABLE
from BLANKING

Output

See Figure 2&3,
CL= SOPF
Delay Time, Low-to-High Level Q

tDLH

Output

form LATCH ENABLE

-

1.5

from BLANKING

-

1

11S
11S

-

3

11S

-

2

11S

See Figure 2&3,
CL= 50PF
TRANSITION TIME,

tTHL

High-to-Low level Q Output
TRANSITION TIME,
Low-to-High level Q Output

CL= 50PF
See Figure 3

tTLH

CL= 50PF
See Figure 3

87

• Timing Chart

CLOCK

DATA IN

):
1

-------------------------5-0o/c~.~~-------------

SERIAL OUT

FIGURE 1. SERIAL DATA TIMING

C~OCK

~

LAST
PULSER

1

1

1

tCKH-LEH

\------tW(LEH)

1

II....
25°C

158

0c/w

2

Operating
Temperature

Top

Thv:;a 50V

-40- +85

°C

-

Storage
Temperature

Tstg

-

- 55- + 150

°C

.:..

Item

Input Voltage

NOTES:

1)

Maximum Supply Voltage for GND

2)

Derate 6.9 mW/Ck above 25°C

\

.

790 [Derate 6.3
mW/C above 25°C]

Refer to the foil owi ng form u I a.
Tj = P x Rj - a + Ta (P: Max current consumption)

95

\

•

Recommended Operating Conditions

Item

Symbol

Condition

Min.

Max.

Unit

Logic Supply
Voltage

Vee

Applicable to logic supply voltage
terminal

4.5

5.5

V

Driver Supply
Voltage

Vhv

Applicable to driver supply voltage
terminal

10

65

V

High Level Input
Voltage

Vih

Applicable to all input
terminals

Vee=4.5V

3.6

Vee= 5.5V

4.4

V

Vii

Applicable to all output
terminals

Vee=4.5V

-

0.9

V

Vee =5.5V

-

1.1

V

1 Output is High at a time

-

-40

mA

All driver output are High at a time

-

-2

mA

Applicable to all driver output terminal

-

2

mA

Low Level Input
Voltage
Driver High level
Output Current

lohvh 1

Driver High level
Output Current

lohvh 2

Driver low level
Output Current

lohvl

ClK Frequency

fcp

See timing chart

-

4

MHz

twcJk

See timing chart

75

-

ns

Data in Setup
Time

tds

See timing chart

50

-

ns

Data in Hold
Time

tdh

See timing chart

SO

-

ns

twls

See timing chart

80

-

ns

ClK - LS Del ay
Time

tdcJ

See timing chart

50

-

ns

LS - ClK Delay
Time

tdlc

See timing chart

0

-

ns

LS - CHG Delay
Time

tdlcg

See timing chart

0

-

}Is

LS- Cl Delay
Time

tdld

See timing chart

0

-

}IS

twehg

See timing chart

2

-

}Is

twd

See timing chart

2

-

}Is

Top

-

-40

+85

DC

ClK Pulse width

LS Pulse Width

CHG Pulse Width
CL PUlse width
Operating
Temperature

96

o

Vee = 5V ± 10%, Vhv = 1OV-65V, Ta = - 40°C to + 85°C

DC Characteristics

Item
Logic Standby
Current

Symbol
Icc 1

Condition

Icc2
Driver Standby
Current

IhV1

No Load
Vee = 5.5V

IhV2
High Level Input
Voltage

Vih

Low Level Input
Voltage

Vii

Input Leakage
Current

lin

Input
Capacitance

Cin

High Level Data
Output Voltage
Low Level Data
Output Voltage
High Level Data
Output Voltage
Low Level Data
Output Voltage

Vodh 1
V odl1
V odh2
-Vodl2

10= - 20llA
10= 20llA
10= -O.lmA
10=O.lmA

Typ.

Max.

Unit

-

2.3

3.4

All Input: High, All
Driver Output: High,
Ta = 25°C

-

0.5

·1.0

All Driver Output: Low

-

-

1

}lA

All Driver Output:
High, Ta = 25°C

-

1.3

2.0

mA

Vee=4.5V

3.15

-

Vee = 5.5V

3.85

Vee=4.5V

-

-

V ee =5.5V

All Input:

No Load
Vee = 5.5V

Min.
Low

rnA

-

V
V

-

1.35

V

-

-

1.65

V

Ta = 25°C

-

-

±1

}lA

Ta = 25°C

-

15

-

pF

Vee = 4.5V

4.2

-

5.2

Vee =4.SV

0.2

V

Vee = S.SV

-

-

-

V

Vee = 5.5V

-

0.2

V

Vee = 4.SV

3.5

-

V

Vee=5.SV

4.5

-

V

Vee = 4.SV

-

-

1.1

V

1.1

V

Vee

=S.5V

V

Driver High Level
Output Voltage

Vohvh

lohv= -40mA

Vhv-4

-

-

V

Driver Low Level
Output Voltage

Vohvl

lohv=2mA

-

-

3.0

V

97

• . AC Characteristics
Vcc = 5V, Vhv = 65V, Ta = 25°C
Item

Symbol

Remarks

Min.

Typ.

Max.

Unit

ClK - Dout DelayTime

tpd

See timing chart and test circuit

-

100

150

nS

Delay Time· low - High

tdlh

See timing chart and test circuit

0.3

1

pS

Transit Time Low - High

ttlh

See timing chart and test circuit

-

2

5

pS

Delay Time low - High

tdhl

See timing chart and test circuit

-

0.3

1

pS

Transit Time High - low

tthl

See timing chart and test circuit

-

2

5

pS

•

Timing Chart

98

TEST CIRCUIT

IlYO t--C)-+--,\M..--..,
1.5KO

65V

5.0 V

WV--.

flVO I--<>-"'..........

DIN

:l

u

r.n
....I

Information furnished by OKI is believed to be accurate and
reliable. However, no responsibility is assumed by OKI for its use;
nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by
implication or otherwise under any patent rights of OKI.

99

OKI semiconductor·
MSC1165
20-BIT ANODE/GRID DRIVER

GENERAL DESCRIPTION
The MSCl165 is a monolithic IC using the Bi-CMOS process,for hybridizing CMOS and bipolar
transistors on one chip.
The logic portion such as the input stage, shift register and latch is formed by CMOS, and the
output driver requiring a high withstand voltage is formed by bipolar transistors.

FEATURES
•

Logic supply voltage

+5V

•

V(driver supply voltage

+65V

•

VF driver output current
(lohvhl)
(lohvh2)
(lohvl)

•

Clock frequency

•

Built-in 20-bit latch

•

Built-in 20-bit shift register

•

28 Pin DIP Package

100

- 40 mA (1 driver output high)
- 2 mA (All driver output_high)
+2mA
4MHz

BLOCK DIAGRAM

HVO 1

HV02

0::

w

l-

I

19
w

I-

:c

05

In

0::
Iu..
In

.....
iii

U

~
.....

2>
N

2>
N

HV020
R-20

20 20

GND

•

101

PIN CONFIGURATION

(Top View) 28 lead Plastic DIP

HV017

HV018

HV016

HV019

HV01S

HV020

HV014

Vee

HV013

Cl

HV012

lS

HV011

CHG

HV010
,HV09

102

DIN
ClK

HV08

GND

HV07

Vhv

HV06

HV01

HVOS

HV02

HV04

HV03

PIN DESCRIPTION
Pin No.

Symbol

17

HVO 01

1
28

HVO
HVO

26

HVO 20

18

Name

Description

Driver output

1. Each terminal is a driver output terminal, which
corresponds to each bit of the shift register.

Vhv

Driver supply
voltage

1. This is a power terminal of the driver circuit.

19

GND

Driver GND
LOgic portion GND

1. This is a grounding terminal of the driver circuit,
and the logic portion.

24

CL

Clear input

1. This is an input terminal containing a pull-up
resistor.
2. The terminal is generally kept High. The driver
output, High of Low, iS,driven by the output of
the corresponding latch circuit.
3. When the terminal is Low, the driver outputs
are fixed to "Low" regardless of the output of
the latch circuit.

23

LS

Latch strobe input

1. This is an input terminal without a pull-up or
pull-down registor.
2. When the terminal is High, the latch circuit is
slewed, and the output of the shift register is
that of the latch circuit.
3. When the terminal is Low, the latch circuit holds
the output of the shift register immediately
before the terminal is turned Low.

21

DIN

Data input

1. This is an input terminal of the shift register to
input the display data in synchronization wiht a
clock pulse. (Positive logic)

25

Vee

Logic supply
voltage

1. This is a power terminal of the logic portion
(other than the driver circuit).

20

CLK

Clock input

1. This is an input terminal without a pull-up or
pull-down resistor
2. The data of the shift register is shifted at the
rising edge of a clock pulse.

22

CHG

Test input

1. This is an input terminal containing a pull-down
resistor.
2. The terminal is generally kept Low. When the
CL terminal is High, the driver output, High or
Low, is driven by theoutput of the
corresponding latch circuit. _
3. The terminal is Low and the CL terminal is High,
the driver output can be fixed to High
regardless of the output of the latch circuit.

17
18

I

103

SCHEMATIC DIAGRAM OF LOGIC PORTION INPUT TERMINAL
CIRCUIT

Vee

INPUT

GND

SCHEMATIC DIAGRAM OF DRIVER OUTPUT TERMINAL CIRCUIT

Vhv

HVO

GND

104

FUNCTION TABLE
ClK

R-1

R-2

R-3

R-4

H

H

R1 n

R2n

R3n

R19 n

l

L

R1n

R2n

R3 n

R19 n

DIN

-'
-'
Cl

CHG

lS

R.X

HVO.X

L

X

X

X

l

H

H

X

X

H

H

L

H

H

H

H

L

H

L

l

H

l

L

X

NC

....................

R-20

l: Low level, H: High, Level, X: Don't Care, NC: No Change

ELECTRICAL CHARACTERISTICS
o Absolute Maximum Ratings
Parameter

Symbol

Condition

Limits

Unit

Note

Logic portion ·supplYvoltage

Vee

Applicable to
logic power terminal

- 0.3-6.5

V

1

Driver supply voltage

Vhv

Applicable to driver
power terminal

Vee- 7O

V

1.2

Input voltage

Yin

Applicable to all the
input terminals

0.3-Vcc + 0.3

V

1

Driver drive frequency

fdrv

Duty less than 50%

a-so

kHz

Power Dissipation

Pd

Ta:i 25°C

1020

mW

Attenuation Rate

Rj -a

Ta>2SoC

122

°(Jw

Operating temperature

Top

Vhv;;aSOV

- 40- + 85

DC

Storage temperature

Tstg

-

- 55- + 150

°c

Note 1:

The maximum voltage which can be applied t the GND terminal.

Note 2:

Thermal resistance of the package (between junction and atmosphere)

2

The junction temperature (Tj) expressed by the equation indicated below
should not exceed lS0°e.
Tj = P x Rj - a + Ta

(P: Maximum power consumption of Ie)

105

•

Recommended Operating Conditions
Parameter·

Symbol

Condition

MIN

MAX

Unit

Vee

Applicable to logic power terminal

4.5

5.5

V

Vhv

Applicable to driver power terminal

10

65

V

High level input
voltage

Applicable to all input
terminals

Vcc=4.SV

3.6

-

V

VIH

Vcc = S.SV

4.4

-

V

low level input
I
voltage

Applicable to all input
terminals

Vcc=4.5V

-

0.9

V

VIL

Vcc=5.5V

-

1.1

V

Driver high level
output current

IOHVH
1

-

-40

mA

Driver high level
output current

IOHVH
All driver output: High
2

-

-2

mA

Driver low level
output current

IOHVL

2

mA

Clock frequency

fel

See Timing Chart

-

4

MHz

twclk

See Timing Chart

75

-

nS

logic supply voltage
Driver supply voltage

Clock pulse width

1 driver output: High
Other drive outputs: low

Applicable to all driver output
terminals

Data setup time

tds

Se~

Timing Chart

50

Data hold time

tdh

See Timing Chart

50

LS pulse width

twls

See Timing Chart

80

ClK-LS delay time

tdcl

See Timing Chart

lS-CLK delay time

tdlc

lS-CHG delay time

-

nS
nS
nS

50

-

See Timing Chart

0

-

nS

tdlcg

See Timing Chart

0

-

lIS

LS-CL delay time

tdlcl

See Timing Chart

0

CHG pulse width

twchg

See Timing Chart

2

-

TI pulse width

twcl

See Timing Chart

2

-

lIS

Operating
temperature range

Top

+85

°C

106

-

-40

nS

lIS
lIS

•

DC Characteristics
Vee = 5V ± 10%, Vhv = 10V-65V, Ra = - 40°C-SSoC
Parameter

Symbol

Condition

Iccl
Logic supply current
Icc2

Ihv2
Driver supply current
Ihv2

High input voltage

No load
Vee= 5.5V

No load
Vee= 5.SV

All inputs:High
All driver outputs:
High Ta = 25°C
All driver outputs:
Low
All driver oututs:
High Ta = 25°C

Vih

Low input voltage

Vii

Input leak current
Input capacity

D

All inputs:Low

VOH

Ta = 25°C

VOL

Ta = 25°C

High driver output
voltage

Vohvh

lohv= -40mA

Low driver output
voltage

Vohvl

lohv=2mA

MIN

TYP

MAX

-

2.3

3.4

'-

0.5

1.0

-

-

50

llA

1.3

2.0

rnA

-

-

Vee=4.5V

3.15

Vee=4.5V

3.85

Vee=4.5V

-

Vee= 4.5V

-

Unit
rnA

V

1.35

V

1.65

-

-

±1

11A

15

-

pF

Vhv-4

-

-

V

-

-

3.0

V

AC Characteristics
Parameter

,

Symbol

Condition

Vee = 5V, Vhv = 6SV,
Ta = 25°C
TYP MAX
MIN

Unit

Delay time L - H

tdlt)

See Timing Chart and Test
circuit.

-

0.3

1

11S

Transit time L- H

ttlh

See Timing Chart and Test
circuit.

-

2

5

llS

Delay time H - L

tdhl

See Timing Chart and Test
circuit.

-

0.3

1

llS

Transit time H - L

Uhl

See Timing Chart and Test
circuit.

-

2

5

llS

107

.....
o

CO

• Timing Chart

CLOCK~~T3J4 r
td~~1 ~

DIN

S

=9----------55------'
- ______ 1

,

5>

twd

LS

5
5

CHG

~d I. ·1
twch

CL

HVO (1,2,19,20)

9

~~

twcl

.--

~ twcl

55
.

5
-----'"

HVO (OTHERS)

5

ttlh

ttlh

tthl

tthl

,,
,,

o Test Circuit

20 pF
Vee

Vhv

HVO 01
1.SKQ

HVO 02
6SV

S.OV

HVO 20
DIN

~
...J

u

l!)
V\
...J

:L
U

Id

0

z

l!)

Jl

Information furnished by OKI is believed to be accurate and reliable.
However, no responsibility is assumed by OKI for its use; nor for any
infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise
under any patent rights of OKI.

109

OKI semiconductor
MSC11.62
40-81T ANODE/GRID DRIVER
GENERAL DESCRIPTION
The MSC1162 is a monolithic IC using the Bi-CMOS process for hybridizing CMOS and bipolar transistors
on the same chip. The logic portion such as the input stage, shift register and latch is formed by CMOS
and the output driver requiring a high withstand voltage is formed by bipoalr transistors.
Since the pin asignment allows single side pattern formation on the printed circuit board, the display
unit size can be reduced.
The bidirectional shift register facilitates the pattern design when the deivces are arranged
symmetrically with the display as the center axis.

FEATURES
Designed as a VFD grid driver for emitter-follower force output with 40-bit active pull down by built-in
40-bit bidirectional shift register and latch.

•
•
•

Logic Supply Voltage : Vcc
Driver Supply Voltage:

Vhv

Driver Output Current: lohvh:

+5V

• Built-in 40-Bit latch

+65V

• Built-in 40-Bit bidirectional shift register

-40mA

• Clock frequency: 4 MHz

lohvl : 2mA

110

• 60pinFLATPackage

-BLOCK DIAGRAM

ClK

DIN

HV02

t

J:
Vl

-J

<{

Z

o

[5
w

0:::

e

I
I
I

en

+-'

iii

6

'25 DC

145

DC/W

2

Operating
Temperature

Top

Thv;S 50V

-40- +85

°C

-

Storage
Temperature

Tstg

-

- 55- + 150

DC

-

NOTES:

1)

2)

860 [Derate 6.9
mW/C above 2SDC]

Maximum Supply Voltage for GND
Derate 6.9 mW/Ck above 25°C
Refer to the following formula"
Tj = P x Rj - a + Ta (P: Max current consumption)

115

•

Recommended Operating Conditions

parameter

Symbol

Condition

Min.

Max.

Unit

Logic Supply
Voltage

Vee

Applicable to logic supply voltage
terminal

4.5

5.5

V

Driver Supply
Voltage

Vhv

Applicable to driver supply voltage
terminal

10

65

V

High Level Input
Voltage

Vih

Applicable to all input
terminals

Vee = 4.5V

3.6

-

Vee = 5.5V

4.4

-

V

Applicable to all output
terminals

Vee=4.5V

-

0.9

V

1.1

V

1 Output is High at a time

-

-40

rnA

Applicable to all driver output terminal

-

2

rnA

Low Level Input
Voltage

Vii

Driver High level
Output Current

lohvh

Driver Low level
Output Current

lohvl

ClK Frequency

.

CLK Pulse width

V ec =5.5V

fcp

See timing chart

-

4

MHz

twclk

See timing chart

75

-

ns

See timing chart

50

-

ns

Data in Setup
Time

tds

Data in Hold
Time

tdh

See timing chart

50

-

ns

twls

See timing chart

80

-

ns

CLK - LS Delay
Time

tdcl

See timing chart

50

-

ns

LS - ClK Delay
Time

tdlc

See timing chart

0

-

ns

. LS - CHG Delay
Time

tdlcg

See timing chart

0

-

lIS

LS- Cl Delay
Time

tdld

See timing chart

0

-

lIS

twchg

See timing chart

2

-

' lIS

twc;

See timing chart

2

-

lIS

Top

-

-40

+85

,oc

LS Pulse Width

CHG Pulse Width
Cl PUlse width
Operating
Temperature

116

I

o

Vee = SV ± 10%, Vhv = 10V-6SV, Ta = - 40°C to + 85°C

DC Characteristics

Parameter
Logie Standby
Current

Symbol
Icc 1

IhV 1

Max.

-

4.3

6.65

0.5

1.0

All Driver Output: Low

-

-

1

pA

All Driver Output:
High, Ta = 25°C

-

2.45

3.8

rnA

-

V

-

V

Low

All Input: High,AII
Driver Output: High,
Ta = 25°C

No Load
Vee= S.SV

IhV2
High Level Input
Voltage

Typ.

All Input:

No Load
Vee= S.SV

lee2
Driver Standby
Current

Min.

Condition

Vih

Unit

rnA

Vee = 4.SV

3.15

-

Vee= S.SV

3.85

-

Vee=4.SV

-

-

1.35

V

Vee = S.SV

-

-

1.65

V

Low Level Input
Voltage

ViI

Input Leakage
Current

lin

Ta = 25°C

-

-

±1

pA

Inp!Jt
Capacitance

Cin

Ta = 25°C

-

15

-

pF

V

High Level Data
Output Voltage

Vodh 1

10= -20pA

Low Level Data
Output Voltage

Vodl1

lo=20pA

High Level Data
Output Voltage

Vodh 1

10= -0.1rnA

Low Level Data
Output Voltage

Vodl2

10=0.1mA

Driver High Level
Output Voltage

Vohvh

Driver Low Level
Output Voltage

Vohvl

Vee=4.SV

4.2

-

Vee= 5.5V

5.2

-

-

Vee=4.5V

-

-

0.2

V

-

0.2

V

Vee=S.SV

-

-

lohv= -40rnA

Vhv-4

-

-

lohv=2rnA

-

-

3.0

Vee=4.SV

3.5

Vee= S.SV

4.5

Vee= 4.SV

-

Vee=S.SV

-

V

V

-

V

1.1

V

1.1

V

'-" V
V

117

•

AC Characteristics

Vee = 5V, Vhv= 65V, Ta = 25°e
"

Item

•

Symbol

Remarks

Min.

Typ.

Max.

Unit

elK - Dout DeiayTime

tpd

See timing chart and test circuit

-

100

150

nS

Delay Time low - High

'tcIlh

See timing chart and test circuit

-

0.3

1

pS

Transit Time low - High

ttlh

See timing chart and test circuit

2

5

pS

Delay Time low - High

'tcIhl

See timing chart and test circuit

-

0.3·

1

pS

Transit Time High - low

tthl

See timing chart and test circuit

-

2

5

}is

Timing Chart

118

TEST CIRCUIT

Vee

65V

Vhv

HV011--o-......~IIr-.......,
I.5.KO

5.0V
HV040r-~o-~~v-......~

DOUT

30 pF

Information furnished by OKI is believed to be accurate and
reliable. However, no responsibility is assumed by OKI for its use;
nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by
implication or otherwise under any patent rights of OKI.

119

OKI semiconductor
MSC1172
40-BIT ANODE / GRID DRIVER

GENERAL DESCRIPTION
The MSC1172 is a monolithic IC using Bi-CMOS process for hybridizing CMOS and bipolar
transistors on one chip.
The logic portion such as the input stage, shift register and latch is formed by CMOS, and the
output driver requiring a high withstand voltage is formed by bipolar transistors.
Since the pin assigment allows single side pattern formation on the printed circuit board, the
display unit size can be reduced.
The bidirectional shift register facilitates the pattern design when the devices are arranged
symmetrically with the display at the center axis.

FEATURES
•

Logic supply voltage

(Ved

+5V

•

Driver supply voltage

(Vhv)

+70V

•

Driver output current
(lohvh2)

- 40 rnA (1 driver output.high)
- 2 rnA (All driver output_high)

(lohvl)

+2mA

(lohvh,)

4MHz

•

Clock frequency

•

Built-in 40-Bit latch

•

Built-in 40-Bit bidirectional shift register

•

60 Pin FLAT Package

120

BLOCK DIAGRAM

R-1

HV02
0::

w

R-2

2

2

t-

Il'

lE
w
0::

t-

~

:::c

:::c
ut:)

,II'
...J

<{

Z

a
i=
uw

.....
iii

0

0::

'25°C

145

0c/w

VHV~

-40- +85

°C

- 55- + 150

°c

Ta~

25°C

70V

-

2

-

Note 1: Maximum Supply Voltage for GND.
Note 2: Delete 6.9 mwrC above 25°C.
Refer to the following formul~.
Tj = P x Rj - a + Ta (P! Maximum power consumption)

127

• 'Recommended Operating Conditions
Symbol

Condition

MIN

MAX

Unit

Logic supply voltage

Vee

Applicable to logic power terminal

4.5

5.5

V

Driver supply voltage

VHV

Applicable to driver power
terminal

10

70

V

High level input voltage

VIH

Applicable to all
input terminals

vee = 4.SV

3.6
4.4

-

VIL

Applicable to all
input terminals

vee = 4.SV

-

0.9
-40

Applicable to all driver output
terminals

-

2

mA

f"

See timing chart

-

4

MHz

twclk

See timing chart

75

ns

Data setup time

tds

See timing chart

50

-

Data hold time

tdh

See timing chart

50

-

ns

LS pulse width

twls

See timing chart

80

-

ns

CLK-LS delay time

tdcl

See timing chart

SO

ns

LS-CLK delay time

tdle

See timing chart

0

LS-CHG delay time

tdlcg

See timing chart

0

-

LS-CL delay time

tdlcl

See timing chart

0
2
2

Parameter

Low level input voltage
Driver high level output
current
Driver low level output
current
Clock frequency
Clock pulse width

128

vee = S.SV

1 output High
VOHVH1 Applicable to all
VOHVH2 driver output terminals All outpts High
VOHVL

twehg

See timing chart

CL pulse width

tw£!.

See timing chart

Operating temperature

top

CHG pulse width

Vee= S.SV

,-40

1.1
-2

V
V
mA

ns

ns
lIS

-

lIs

+85

°C

lIS

lIs

•

DC Characteristics
Vcc=5V±10%,
Parameter
logic supply current

Driver supply current

Sy'mbol

VHv=10-70V,

Conditions

Ta= -40°C-+85°C

MIN

ICCl
t - - - - i No load
leC2 Vee = 5.5V

All inputs: Low
Inputs: Hlgn
All driver outputs: High
Ta =2Soe

0.5

1.0

IHVl
t----iNo load
IHV2 Vec = 5.5V

All driver outputs: Low

-

1.0

llA

2.31

4.22

mA

Vee=4.5V

High level input voltage

Vee=4.5V

Low level input voltage

3.98 7.08

All

All driver outputs: High
Ta =2Soe

All input terminals

Vee= 5.5V

3.85

All input terminals

IIHl
t----iVIN = Vec
IIH2
IlL 1

low level input current

t----iVIN = GND
IIL2

Input capacitance

-

el, RiL" terminals
All input terminals

-

V

-

1.35

V

-

1.65

V

Input terminals except the
eHG terminal

CHG terminal
lS, DIN, ClK, CHG
terminals

llA

V

3.15

Vee= 5.5V
High level input current

TYP MAX Unit

1.0
llA

10

80

-80

-10

LO
. 15

llA

pF

High level data output
voltage

VODH

VCC=4.5V
3.5
10 = - 0.1 mA I------'----+---t---+---i V
Vee=5.5V
4.5

low level data output
voltage

VODL

10 = O.lmA

High level driver output
voltage
low level driver output
voltage

Vee=4.5V

0.9

Vee = 5.5V

1.1

VOHVH 10HV = - 40mA

VOHVL 10HV = 2mA

V

V

-

3.0

V

129

•

AC Characteristics

Parameter

Symbol

Conditions

MIN
I

TYP

MAX

Unit

Note

CLK-DqUT delay time

tpd

See timing chart
and test circuit.

-

100

150

ns

4

Delay time: L-H

tdlh

See timing chart
and test circuit.

-

0.3

1.0

lls

5.6

Transit ti me: L-H

ttlh

See timing chart
and test circuit.

-

2.0

5.0

lls

5

Delay time: H-L

tdhl

See timing chart
and test circuit.

-

0.3

1.0

lls

5.6

Transit time: H-L

tthl

See timing chart
and test circuit.

-

2.0

5.0

lls

5

Note 4: Applicable to data output terminal.
Note 5: Applicable to driver output terminal.
Note 6: Tdlh and Tdhlare delay times from the CL signal.

130

o Timing Chart

1If"

CLOCK

DIN
----'1\.-tWcCJI'

.tr---------

I.

DOUT

LS

»)~

'I

7)

'If:

---~).

.CHG

a
HVO (1,2,39,40)

HVO (OTHERS)

....

w

7)
7)

•

14 .u'~9
. "
.

I trllh

1,,.--------..

c:

~---------~

II

ttlh

~

twCl

:I

Il~};
It~~~~~~~~
\

ttlh

I tt hi

.II~ tdlh

90%
10%

0%
10%

--------,
.r--------

tt hi

II tt Ih

\

\

TEST CIRCUIT

Vee

70V

Vhv

S.OV

Dour

30pF

Information furnished by OKI is believed to be accurate and reliable ..
However, no responsibility is assumed by OKI for its use; nor for any·
infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise
under any patent rights qf OKI.

132

OKI semiconductor
MSC1149-XX
DOT DRIVER

GENERAL DESCRIPTION
The MSC1149-XX is a vacuum fluorescent display tube driver Ie, which consists of a 34-bit shift
register, a 33-bit latch circuit (the 33 bits of the latch circuit correspond to bit 1 to bit 33 of the
shift register), and a matrix circuit for latch output and VF driver output.

FEATURES
•

Power supply voltage: BV to 18V

•

Input: TTL level

•

One-to-one correspondence established between latch output and V~ driver output by
matrix cord

•

POWER ON RESET circuit built in

•

Latch operation and shift register RESET performed sequentially by LOAD ENABLE signal
Self load mode generated by connection of LOAD ENABLE terminal and DATA OUT terminal

•

Number of bits increased by cascade connection

•

VF tube lighting test simplified by all VF outputs on H level via TEST terminal.

•

33-bit VF output: - 2 rnA for 8 bits, - 0.8 rnA for 25 bits Terminal connections

133

PIN CONFDIGURATION
MSCl149-XXGS-VK
(Top View) 44 Lead Plastic Flat Package

.
N

0

0

0

~ n
C 5 ~
-i n
-

;00;

Z

0

c

:;l

c

<
0

.......
-i

0

OUTPUT')

..

3'1
30
29
7

28

(NC)

(NC)

OUTPUT8
9
10
11
12

25

0

24
12

0

~
<;;

.:

v;

S

C;; :::j

z!)

23

.
ex; ;;; ~

~

MSCl149-XXRS
(Top View) 40 Lead Plastic DIP

VDD

Bi:ANi<

DATA IN

GND

CLOCK

LOAD ENA8LE

OUTPUT 1

DATA OUT

OUTPUT 2

OUTPUT 33

OUTPUT 3

OUTPUT 32

OUTPUT 4

OUTPUT 31

OUTPUT 5

OUTPUT 30

OUTPUT 6

OUTPUT 29

OUTPUT 7

OUTPUT 28

OUTPUT 8

OUTPUT 27

OUTPUT 9

OUTPUT 26

OUTPUT 10

OUTPUT 25

OUTPUT 11

OUTPUT 24

OUTPUT 12

OUTPUT 23

OUTPUT 13

OUTPUT 22

OUT~UT 14

OUTPUT 21

OUTPUT 15

OUTPUT 20

OUTPUT 16
OUTPUT 17

134

OUTPUT 19
21

OUTPUT 18

PIN DESCRIPTION
(1) DATA IN
This is a serial data input terminal of the.34-stage shift register.
(2) CLOCK
This is a clock input terminal of the shift register to shift an input signal at its leading
edge (Low to High).
(3) LOAD ENABLE
This is an input terminal to transfer the data of the shift register to the data latch circuit
to hold it. After the data is held, the terminal initializes the data of the shift register.
These functions are executed at the leading edge of an input signal.
(4) BLANK

This is an input terminal to turn all the OUTPUT terminals OFF (Low), which contains a
pull-up resistor ..
(5) OUTPUT1 to OUTPUT33

These are output terminals for the VF tube driver. Each terminal outputs data which is
transferred from the corresponding bit of the shift register and held in the data latch
circuit.
(6) DATA OUT

This is a data output terminal of the shift register to output data on the last stage of the
34-stage shift register.
(7) TEST

This is a terminal to turn all the OUTPUT terminals ON (High), which contains a pull-up
resistor. The terminal is used for the VF tube lighting test.
(8) Voo

This is a terminal to supply positive potential.
(9) GND

This is a grounding terminal.

135

BLOCK DIAGRAM

VDD
VF DRIVER

OUTPUT DRIVER

33 x 33 MATRIX

L._._._._

LOAD
ENABLE

DATA IN

33+ 1bit SIR

CLOCK

I

l._. _._. _ ._. _. _._ ._. _. _ ._._. _. _._ ._. _. _. _._. _. _. _. _. _._._ ._. _._._ ._.

GND

ELECTRICAL CHARACTERISTICS
•

Absolute Maximum Ratings
Parameter

I)

Condition

Limits

Unit

- 0.3-2.0

V

V,N

=25°C
Ta =25°C

- 0.3-Voo + 0.3

V

Tstg

-

- 65-150

°C

Power supply voltage

Voo

Input voltage
Storage temperature range

Ta

Operating Conditions
Parameter

136

Symbol

Symbol

Range

Unit

Power supply voltage

Voo

8-18

V

Operating temperature range

Top

-40- +85

°C

•

DC Characteristics
V oo =8-18V
Parameter

Symbol

High input voltage

VIH

Low input voltage

VIL

Ta= -40-+85°C

Condition

MIN

TYP

MAX

Unit

-

3.8

-

6

V

-0.3

-

0.8

V

Hi,gh output voltage

VOHl

Voo = 9.5V, IOHl = - 2mA
OUTP.UT14-21

Voo
-0.8

-

-

V

High output voltage

V OH2

Voo =9.5V, IOH2 = - 0.8mA
OUTPUTl-13,22-33

Voo
-0.8

-

-

V

VOLl

Voo = 9.5V
OUTPUTl-33 IOL = 5OO11A

Low output voltage

-

-

2

V

IOL= 2OO11A

-

-

1

V

IOL= 211A

-

-

0.3

V

IOH3 = - 2OO11A

4

-

6

V

No load

4.5

-

6

V

IOL = 2OO11A

-

-

0.8

pA

-'/

-'/

High output voltage
VOH3

Voo=9.5V
DATA OUT
-'/

Voo=9.5V
DATA OUT

Low output voltage

VOL 2

High input current

IIHl

CLOCK, DATA IN
LOAD
VIH = 5.5V

-5

-

5

llA

High input current

IIH2

BLANK
Ta = 25°C

-20

-

5

llA

Low input current

IILl

CLOCK, DATA IN
LOAD
VIL= OV

-5

-

5

llA

Low input current

IIL2

BLANK
Ta = 25°C

VIL=OV

-12S

-

-'10

}lA

High input current

IIH3

TEST
Ta = 25°C

VIH = 5.5V

-100

-

5

llA

Low input current

IIL3

TEST
Ta= 25°C

VIL=OV

-400

-

-20

llA

Operating current

100

No load

15

rnA

VIH = 5.5V

-

10

137

• AC Characteristics
Voo=8-18V
Parameter
Clock frequency
Clock pulse width
Data set up
Data hold time
Load pulse width

Symbol

Condition

MIN

fc

-

-

Pwc

HIGH pulse

Ta= -40- + 85°C
MAX

Unit

-

250

kHz

1.3

-

'-

}lS

TYP"

ts

-

1

-

tH

-

200

-

-

PWL

-

1.3

-

-

}lS

tOOB

CL = 100PF
BLANK

-

-

7

}lS

tooL

CL = 100PF
LOAD

-

-

8

}lS

-

5

}lS

Output delay time

CL= 100PF
20%-80% ofVoo

}lS
nS

Slew rate

tR

LOAD ENABLE-7CLOCK
setup time

tsc

.-

2

.-

-

}lS

CLOCK-7LOAD ENABLE
setup time

tSL

-

0

-

-

nS

• Timing ClJart

CLOCK
DATA IN

LOAD
ENABLE
BLANK
tOOL""*-~

OUTPUT

138

-+J.--I-of-tOOB

FUNCTIONAL DESCRIPTION
•

Shift Register Output Designation
First data bit read-in is stored in shift register #1, the last data bit read-in is stored in shift
register #33. When the shift registers are full, a high voltage level applied to the load enable
input will transfer the data from the shift register to the data latch, and then to the output
through the 33 x 33 matrix. This matrix determines shift register output designation. the
device is mask programmable for the 33 x 33 matrix, thus providing the capability of changing
the shift register output designation. The device has 34 shift registers and 33 data latches as
shown in the functional block diagram.
'

•

Self-Load Mode
In this mode data out (pin 4) is connected to load enable (pin 7), and the data word is
constructed with 34 bits (including the one self-load bit set to logic 1). At the 34th clock pulse,
the data is transferred from the shift register to the data latch and the output drivers through
the 33 x 33 matrix. Before the next clock pulse, the registers are zeroed.

FROM
MICROPROCESSOR

¢

DATA 2
CLOCK 3
BLANK
----140
LOAD ENABLE 38
DATA OUT

37
39

139

•

Non-Self-Load Mode
In this mode, the data out and the load enable pins are not connected, and the load enable.
input is controlled by an external source. There are two types of operation in this mode.
1.

The data word consists of 34 bits (including one self-load bit). To transfer data from the
shift registers to the data latch, a high-level voltage is applied to the load enable pin
before the rise of the clock pulse following the 34th clock pulse.

2. The data word consists of 33 bits without the self-load bit. To transfer the data, a high
voltage level is applied to the load enable pin before the rise of the 34th clock pulse.

FROM
MICROPROCESSOR

c)

DATA
CLOCK
BLANK
LOAD
·ENABLE

2
3
40
38
37
39

140

Data load timing example
1.

LOAD ENABLE singal externally supplied
1) Bit 1 to Bit 33 used

CLOCK
DATA IN

n--------l

. L~:~BLE
OUTPUT

/

n-------l

SIR RESET

(Internal) - - - - - - - - - - - - - - - - - - - - - - '

Notes: 1.

The data of DATAO is negligible.

2. When the LOAD ENABLE signal is held in the High level state as shown by the
dotted line, the shift register is held in the RESET state as shown by the dotted
line.
2)

Bit n to Bit 33 used (1 

R

.¢D~~
T~
~
. .

_
.LeI>

.

T

eI>

LatfSD - '
Q

'

~

MOS
L~.L
L
0 --B.E.
r\T
L
'NMOS

.LeI>

T

~VDD

-

eI>

0

LV

L

.L

,L

165

PIN CONFIGURATION

MSM
5267B-15

PIN DESCRIPTION
PIN#
1
2
3
4
5
6
7
8
9
10
11
12
13
14

166

Pin Name
Vdd

Data
Clock
Output 1
Output 2
Out put3
Output 4
Output 5
Output 6
Output 7
Output 8
Output 9
Output 10
Output 11

Comments
Input Positive supply voltage Terminal
Input Data Acquisition Terminal
Input Clock Terminal
Output Shift Register 32
Output Shift Register 21
Output Shift Register 22
Output Shift Register 23
Output Shift Register 30
Output Shift Register 13
Output Shift Register 14
Output Shift Register 15
Output Shift Register 1
Output Shift Register 33
Output Shift Register 5

PIN DESCRIPTION
PIN#

Pin Name

15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38

Output 12
Output 13
Out put 14
Output 15
Output 16
Output 17
Output 18
Output 19
Output 20
Output 21
Output 22
Output 23
Output 24
Out put 25
Output 26
Output27
Output 28
Output 29
Output 30
Output 31
Output 32
Output 33
Data Out
Load Enable

39
40

Vss
Blank

Comments
Output Shift Register 6
Output Shift Register 7
Output Shift Register 28
Output Shift Register 27
Output Shift Register 31
Output Shift Register 18
Output Shift Register 2
Output Shift Register 10
Output Shift Register 26
Output Shift Register 29
Output Shift Register 3
Output Shift Register 8
Output Shift Register 9
Output Shift Register 4
Output Shift Register 11
Output Shift Register 16
Output Shift Register 17
Output Shift Register 12
Output Shift Register 19
Output Shift Register 24
Output Shift Register 25
Output Shift Register 20
Output Data Shift Register
Input for Loading Word into Data Latch from Data Shift
Register
Ground Potential Terminal
Input for Turning Output Drivers Off

ELECTRICAL CHARACTERISTICS'
II

Absolute Maximum Ratings
Ta
Parameter

= 25°(, Unless otherwise specified

Symbol

Condition

Min

Max

Unit

Supply Vo.ltage

Voo

-

-0.3

20

V

Input Voltage

VI

-0.3

VDD + 0.3

V

Operating Temp

Ta

-40

85

°C

Storage Temp

Tst

-

-65

150

°C

167

•

AC Characteristics

Ta

= - 40°C to + 85°C, Voo =8V to 18V Unless otherwise specified
Characteristics

Condition

MIN

Either positive or negative

2.5

Symbol

Clock Frequency

Fe

Clock Pulse Width

Pwc

=
=

=

Slew Rate
Outputs; (1-33)

tR

Data Setup Time

ts

1

Data Hold Time

tH

200

CL 1OOpFt 20% t080%
or 80%t020% of Voo
V DO 8V or V DO 18V

OUTput Delayfrom Blank

tOOB

OUTput Delay from Load
Power on Reset Slew Rate

tOOL
PRSR

Load Pulse Width

PWL

CL
CL

MAX

Units

160

KHz

5·

ps

ps

=

=100pFVoo =8V
=1OOpFVDD =8V
0.001

ps

ns
7

ps

8

ps

10

V Ips

1.6

ps

o Timing Chart
...

 1(t------fc----~)'~1

~pwc

CLOCK
3.SV -

DATA IN

.

~t

3.SV O.8V - .

LOAD ENABLE
.

3~SV

-

O.8V -

BLANK
3.SV -

OUTPUT
3.SV O.8V -

168

~ ~th

h

O.8V-

T

" - _ _ _ _ _ _-J

ts
.

.
.

-------------------

o

DC Characteristics

Ta = - 40 to 85°C Unless otherwise specified
Characteristic
High Level Input
Voltage
Low Level Input
Voltage
High Input Current
(PIN 2, 3, 38)
Low Input Current
(PIN 2,3,38)
High Input Current
(PIN 40)
Low Input Current
(PIN 40)

SYM

Conditions

MIN

MAX

Unit

V\H

Voo=8to 18V

3.5

Voo+0.3

V

V\L

Voo= 8to 18V

-0.3

0.8

V

I\Hl

Voo=8to 18V. V\=Voo·

1

pA

I\L 1

Voo=8to 18V, V\=Vss

-1

pA

I\H2

Voo=8to 18V, V\=3.SV

-5

- 125

pA

I\L2

Voo=8to 18V, V\=VSS

-5

-125

pA

10

mA

7

mA

Voo = 8to 16V, All Outputs
open
Ta = - 40°C, 25°C
Supply Current

100

Voo=8to 16V,AII Ouputs
open
Ta = 85°C
Low Current
Output Drivers
(ON)
(PIN4 - 16,25 - 36)
Low Current
Output Drivers
.(ON)
(PIN 17 - 24)
High Current
OutPut Drivers
(ON)(PIN 17 - 24)
Output Drivers
(OFF) (PIN 4-36)
High Voltage
Data out (PIN37)
Low Voltage Dataout
(PIN37)

Vo Hl

Vo H2

Voo = 9.5V, IOH
= -1.5mA

Voo=9.SV,loH
= -6mA

Ta= 25°C
- 40°C

VDD-0.3

Ta = 8SoC

VDD-O.S
VDD -0.3

Ta= 25°C
- 40°C
Ta = 85°C

VOH2

Voo = 9.sV, IOH
= -30mA

Ta = 2SoC
- 40°C
Ta = 85°C

VOL

V

V
VDD-0.5
VDD-2.0

V
VDD-2.5
Vss + 0.2
Nss+s

Voo = 9.sV, IOL = lpAI SOOpA

VOHO

Voo = 9.SV, IOHO = - SOOpA

VOLD

IOLD= lpA

,

VDD-S

V
V

Vss + 0.4

V

FUNCTIONAL DESCRIPTION
•

Data Input
The data pattern (33 bits) supplied to the device through this inpu.t controls the output driver
state (On or Off).

1.

A high level turns the output driver on.

2.

A low level turns the output driver off.

169

• Clock Input
A Positive transition of the clock loads and shifts the data. This input also has a Schmitt trigger
which provides 0.3 volts of hysteresis.

• Blanking Input
A low-level voltage at this pin turns the output drivers off; an internal pull up is provided on
this pin.

• Load Enable
A high-level at this input tra~sfers the data from the shift register to the data latch, and sets
~he

shift register to zero.

First data bit read-in is stored in shift register #1, the last data bit read-in is stored in shift
register #33. When the shift registers are full, a high Voltage level applied to the load enable
input will transfer the data from the shift register to the data latch, and then to the output
through the 33 x 33matrix. This matrix determines shift register out put designation. ~he
device is mask programmable for the 33 x 33 matrix, thus providing the capability of changing
the shift register output designation. The device has 34 shift registers and 33 data latches as
shown in the functional block diagram.
There are two modes of operation:

• Self-Load Mode
In this mode Data Out (pin 37) is connected to Load Enable (pin 38), and the data word is
constructed with 33 bits (including the oneself-load bit set to logic 1 ). At the 34th clock pulse,
the data is transferred from the shift register to the data latch and the output drivers through
the 33 x 33matrix. Before the next clock pulse, the registers are zeroed.

FROM
MICROPROCESSOR

cJ ~~~~!o
LOAD ENABLE

DATA OUT

Vdd

38
37
39

• Non-Self-Load Mode
In this

mode~

the Data Out and the Load Enable pins are not connected, and the Load Enable

input is controlled by an external source. There are two types of operation in this mode.
1. the data word consists of 34 bits (including one self-load bit). To transfer data from the
shift registers to the data latch, a high-level voltage is applied to the Load Enable pin
before the rise of the clock pulse following the 34th clock pulse.
2.

The data word consists of 33bits without the self-load bit. To transfer the data, an high
. voltage level is applied to the Load Enable pin before ~he rise of the 34th clock pulse.

170

FROM
MICROPROCESSOR

Vdd

2
3

40
38
37
39

DATA OUT

When the display driver is used in a cascade configuration, a filler bit must be inserted
between each group of 33 data bits. The filler bit must be logic 1 when used with the selfloading mode and a logic 0 when used in the non-self-loading mode.

V?d
DATA 2 1 37
CLOCK 3
BLANK 40
LOAD

r---

38
39

-L.

-

DATA
OUT

~

V1 d
DATA 2 1 37
CLOCK 3
BLANK 40

~

38
39

DATA OUT

~

-L.

-

When the cascaded devices are used in self-load mode. the Data Out pin of the last device
must be connected to the load enable pin of all devices as shown in the above figure.
When two display drivers are cascaded, sufficient on-chip time delays allow the system to
operate within the speCification of the device and work in a system.
Up to 10 driver inputs may be connected to the Data Out pin (pin 37) of the last device.

Information furnished by OKI is believed to be accurate and
reliable. However, no responsibility is assumed by OKI for its use;
nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by
implication or otherwise underarfy patent rights of OKI.

171

OKI semiconductor
MSM5328
DOT DRIVER
GENERAL DESCRIPTION
The MSM5328RS is a CMOS multi-digit display driver and consists of a 34-bit shift register, a 33-bit
latch, and a 33-bit VF tube driver.

FEATURES
o

Complete static operation to ensure stability against noise

•

o

3 or 4-signalline connection with microcomputers.
Direct,drive of VF tubes (8 outputs of high-current drive, 25 outputs of low-current drive)

•

Capability of self-load mode.

•

Low power consumption.

•

Single power supply and operating voltage range of 8V to 18V

BLOCK DIAGRAM
o
o

Q~A

II>

OUT

R .

O~JT1

~

~T2

----,--

_ _ _ _;..-_.

O~UT3

:

~

OUTPUT32

----t----

OUTPUT33

BLANK

tvoo
I ~..LL ~MOS
~
o LV
,-

~
172

0

'L

'NMOS

..LL

L

PIN ·CONFIGURATION

1
2
3
4
5
6·
7
8
9
10
11
12
13
14
15
16
17
18
19
20

MSM·
5328

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

PIN DESCRIPTION
PIN#

Pin Name

1
2
3
4
5
6
7
8

Vdd

9
10
11
12
13
14

Data
Clock
Output 1
Output 2
Out put3
Output 4
Output 5
Output 6
Output 7
Output 8
Output 9
Output 10
Output 11

Comments
Input Positive supply voltage Terminal
Input Data Acquisition Terminal
Input Clock Terminal
Output Shift Register 32
Output Shift Register 21
Output Shift Register 22
Output Shift Register 23
Output Shift Register 30
Output Shift Register 13
Output Shift Register 14
Output Shift Register 15
Output Shift Register 1
Output Shift Register 33
Output Shift Register 5

173

PIN DESCRIPTION
PIN#

Pin Name

15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38

Output 12
Output 13
Out put 14
Output 15
Output 16
Output 17
Output 18
Output 19
Output 20
Output 21
Output 22
Output 23
Output 24
Out put 25
Output 26
Output 27
Output 28
Output 29
Output 30
Output31
Output 32
Output 33
Data Out
Load Enable

39'
40

Vss
Blank

Comments
Output Shift Register 6
Output Shift Register 7
Output Shift Register 28
Output Shift Register 27
Output Shift Register 31
Output Shift Register 18
Output Shift Register 2
Output Shift Register 10
Output Shift Register 26
Output Shift Register 29
Output Shift Register 3
Output Shift Register 8
Output Shift Register 9
Output Shift Register 4
Output Shift Register 11
Output Shift Register 16
Output Shift Register 17
Output Shift Register 12
Output Shift Register 19
Output Shift Register 24
Output Shift Register 25
Output Shift Register,20
Output Data Shift Register
Input for Loading Word into Data Latch from Data Shift
Register
Ground Potential Terminal
Input for Turning Output Drivers Off

ELECTRICAL CHARACTERISTICS
•

Absolute Maximum Ratings

Ta
Parameter

Symbol

Condition

Min

Max

Unit

Supply Voltage

Voo

-0.3

20

V

Ir:put Voltage

VI

-

, Operating Temp
Storage Temp

174

= 25°(, Unless otherwise specified

Ta
Tst

-0.3

VDD+0.3 '

V

-40

85

°C

- 65

150

°C

•

AC Characteristics

Ta = - 40°C to + 85°C, VDD =8V to 18V Unless otherwise specified
Characteristics
Clock Frequency

Condition

MIN

Either positive or negative

2.5

Symbol
Fe

Clock Pulse Width

Pwc
tR

Slew Rate
Outputs; ("·33)

CL = 100pFt = 20%t080%
or 80%t020% of Voo
Voo = 8V or Voo 18V

MAX

Units

160

KHz

5

lIs

lIs

=

Data Setup Time
Data Hold Time

1

ts
tH

OUTput Delay from Blank

tOOB

OUTput Delay from Load
Power on Reset Slew Rate

tOOL
PRSR

Load Pulse Width

PWL

lIs

200

=
=

=

ns
7

CL 1OOpFVoo 8V
CL 100p FV oo=8V

0.001
1.6

8
10

lIs
lIs
V / lIs
lIs

• Timing Chart
.....

 E------fc------l~1

CLOCK

BLANK

3.SV -

OUTPUT

3.SV O.BV -

175

•

DC Characteristics
Ta = - 40 to 85°C Unless otherwise specified
Characteristic
High Level Input
Voltage
Low Level Input
Voltage
High Input'Current
(PIN 2, 3, 38)
Low Input Current
(PIN 2,3,38)
High Input Current
(PIN 40)
Low Input Current
(PIN 40)

Conditions

SYM

MIN

MAX

Unit'

VIH

Voo= 8to l8V

3.5

Voo+ 0.3

V

VIL

Voo=8to l8V

-0.3

0.8

V

IIHl

Voo=8to 18V. VI=V OO

1

lIA

IlL 1

Voo = 8 to l8V,VI = Vss

- 1

lIA

IIH2

Voo=8to l8V, VI=3.5V

-5

-125

lIA

IIL2

Voo= 8to18V, VI = VSS

-5

-125

lIA

10

rnA

7

rnA

Voo = 8 to l6V, All Outputs
open
Ta = - 40°C, 25°C
Supply Current

100

Voo = 8 to 16V, All Ouputs
open
Ta = 85°C
Low Current
Output Drivers
(ON)
(P/N4 - 16,25 - 36)
High Current
OutPut Drivers
(On) (PIN 17 - 24)
Output Drivers
(OFF) (PIN 4-36)
High Voltage
Data out (P/N37)
Low Voltage Dataout
(P/N37)

VOHl

Vo H2

VOL

VOD = 9.sV, IOH
= - 0.8mA

VOD = 9.sV, IOH
= - 3.SmA

Ta = 25°C
- 40°C

Vo o - 0.3

Ta = 85°C

Voo-.O.s
Voo - 0.3

V

Ta = 2SoC
- 40°C

V

Ta = 8SoC

Voo - 0.5
Vss + 0.2
Nss+S

Voo = 9.sV, IOL = 1pA 1S00lIA

VOHO

Voo = 9.sV, IOHO = - sOOlIA

VOLD

IOLD = llIA

...

V
V

Voo-S
Vss + 0.4

V

FUNCTIONAL DESCRIPTION
•

Data Input
The data pattern (33 bits) supplied to the device through this input controls the output driver
state (On or Off).
1.

A high level turns the output driver on.

2.

A low level turns the output driver off .

• Clock Input
A Positive transition of the clock loads and shifts the
which prc;>vides 0.3 volts of hysteresis.

176

dat~.

This input also has a Schmitt trigger

o Blanking Input
A low-level voltage at this pin turns the output drivers off; an internal pull up is provided on
this pin.

o Load Enable
A high-level at this input transfers the data from the shift register to the data latch, and sets
the shift register to zero.
Fi rst data bit read-in is stored in shift register # 1, the last data bit read-i n is stored in shift
register #33. When, the shih registers are full a high Voltage level applied to the load enable
input will transfer the data from the shift register to the data latch. The device has 34 shift
registers and 33 data latches as shown in the functional block diagram.
There are two modes of operation:

o Self-Load Mode
In this mode Data Out (pin 37) is connected to Load Enable (pin 38), and the data word is
constructed with 33 bits (including the one self-load bit set to logic 1 ). At the 34th clock pulse,
the data is transferred from the shift register to the data latch and the output drivers. Before
the next clock pulse, the registers are zeroed.

FROM
MICROPROCESSOR

Vdd

cJ~~~~t

38
37

DATA OUT

39

o Non-Self-Load Mode
In this mode, the Data Out and the Load Enable pins are not connected, and the Load Enable
input is controlled by an external source. There are two types of operation in this mode.
1.

the data word consists of 34 bits (including one self-load bit). To transfer data from the
shift registers to the data latch, a high-level voltage is applied to the Load Enable pin
before the rise of the clock pulse following the 34th clock pulse.

2.

The data word consists of 33bits without the self-load bit. To transfer the data, an high
voltage level is applied to the Load Enable pin before the rise of the 34th clock pulse.

177

FROM
MICROPROCESSOR

Vdd

rA,,~~T~;
~BLANK
,
LOAD

40
38

ENABLE

37
39

When the display driver is used in a cascade configuration, a filler bit must be inserted
between each group of 33 data bits. The filler bit must be logic 1 when used with the selfloading mode and a logic 0 when used in the non-self-loading mode.

~yd
DATA 2 1 37
CLOCK 3
BLANK 40

~

38
39
-l-

-

DATA
OUT

~

V1 d
DATA 2 1 37
CLOCK 3
BLANK 40

~ 38
39

DATA OUT

~

-l-

-

When the cascaded devices are used in self-load mode. the Data Out pin of the last device
must be connected to the load enable pin of all devices as shown in the above figure.
When two display drivers are cascaded, sufficient on-chip time delays allow the system to
operate within the specification of the device and work in a system.
Up to 10 driver inputs may be connected to the Data Out pin (pin 37) of the last device.

Information furnished by OKI is believed to be accurate and
reliable'. However, no responsibility is assumed by OKI for its use;
nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by
implication or otherwise under any patent rights of OKI.

178

OKI semiconductor
MSC1178/ MSC1179
7-SEGMENT DRIVER

GENERAL DESCRIPTION
The MSC1178/79 is a BiCMOS structure static display driver to directly drive a vacuum fluorescent
(VF) display tube .. The'driver has a structure of a 56-pin flat package, which consists of a 35 bits
shift register, latch circuit, 7 segment decoder, VF high voltage driver, LED dot driver, dimming
OSC circuit, and dimming control circuit.
The driver i's suited to a driver for frequency or clock display of an automobile digital tuning'
system.

FEATURES
•

56-pin flat package (small)

•

2 supply voltages
Interface, logic portion, LED driver:
..vF display driver:· V DD

Vee

= + 4.5 to

+ 5.5 V

=+ 9 V to + 18 V

•

VF tube driven by positive voltage (VDD = + 18 V MAX)

•

VF tube directly connected:

•

Dimming oscillation circuit built in (capacitor and resistor externally connected)

o

Dif!1m!ng control circuit'built in, with duty (100%, 1/8, or 1/16) selectorinput terminal (L1GHTSW). Use the most significant bit (MSB) to select 1/8 or 1/16. L: 1/8, H: 1/16

•

With PWM IN input terminal to allow the PWM to
PWM generation circuit

•

3-digit 7 segment output, 13-flag output (10 = - 1 mA TYP)

•

9-LED dot display (10 =20 mA MAX)

•

Easy control by microprocessor and easy signal line connection (connected by three signal lines,
DATA IN, CLOCK, and LOAD)

•

7 display patterns selected by device {The MSC1178GS-K and the MSC1179GS-K differ in the 7
display patterns from each other.}
MSC1178GS-K

I-I
I

No pull down resistor required (CMOS push pull output)

contin~ously

control dimming, with external

MSC1179GS-K

-I
1

179

00

o

OJ

r

o

n

~

o
l>
G)
DATA IN

0.-

CLOCK

r-I

>

---.fL

0.-

LOAD

,,-

~

I

Shift Register (35 bits)

~

I

~MSB

LSB~

1

~I

Latch (35 bits) (Level latch by LOAD signal)

- '"

'7

SL

:'0>

- '"

:'00

17Decoder
Segment 1~ 7Segment
Decoder

-

I

p...J

~

OJ

~ 7Decoder
Segment

I

I·

#

-I

Output Gate

~

l~
Dim.
Control

1-f=£

-.0

DATA OUT

.~s~[
Tvss

f-o
~o

f-o
~

LlEGHTSW
:PWMOUT
PWMIN
O·E

PWM

Vee

-

(+5V)

Vss
(OV)

II (NPN Open
LED Driver
Drain) (9 pins)

1

VF Driver (Voo : 18V MAX) (34 pins)
1

1

~

I

0.- f -

.

Voo
(+9-18V)

l>

S.

PIN CONFIGURATION
(Top View) 56 Lead Plastic Flat Package

01
g1
f1

0

010
e1
d1

a1

c1

b1

09

g2

e2

f2

d2

a2

c2

b2

08

g3

e3

f3

d3

a3

c3

b3

07

02

06

I-

::>

o

o

-l

0

-l

.~
o

Note:

Pin 21 with a * mark is connected to Vss, and cannot be connected to another
pin. Pin 21 cannot be used independently ~s Vss but can be used as Vss
reinforcing line.

181

ELECTRICAL CHARACTERISTICS
•

Absolute maximum ratings
Parameter

Symbol

Supply voltage

Voo

Supply voltage

Vee

Input voltage
Maximum output current

VI
IOLD

Conditions

DATA IN, CLOCK, LOAD
LIGHT SW, PWMIN., O·E,
OSC

Limits

Unit

-0.3- + 19

V

-0.3- + 6.5

V

- 0.3-Vee + 0.3

V

25

rnA

LD1-LD9

Allowable package loss

Po

300

mW

Storage temperature

Tstg

- 55- + 150

°C

o

Recommended operating range .
Parameter

Symbol

Conditions

MIN

TYP

.MAX

Unit

Supply voltage

Voo

9

12

18

V

Supply voltage

Vee

4.5

5

5.5'

V

Input voltage

VIH

DATA IN, CLOCK, LOAD
LIGHT SW, PWM IN, O·E

0. 7Vce

Vee

V

Input voltage

VIL

DATA IN, CLOCK, LOAD
LIGHT SW, PWM IN, O·E

0

0. 2V ee

V

Output current

IOLD

LD1-LD9

20

rnA

Operating temperature

Top

+8~

°C

182

10
-40

e

DC characteristics
(Unless otherwise specified,
Parameter

Symbol

Vcc=sV,

Voo= 12V,

Condition

Ta= -40to + 85°C)

MIN

TYP

MAX

Unit

9

12

18

V

Vee

4.5

5

5.5

V

VIH

DATA IN, CLOCK, LOAD

0. 7V ee

Vee

V

VIL

LIGHT SW, PWM 'IN, O'E

0

0. 2V ee

V

Input leak

IIl.l

DATA IN, CLOCK,
LOAD
Vee= s.sV/
PWMIN, O'E, VI = Vee or OV

±1

pA

High level input
leak current

IIH

L1GHTSW VI = VCC = S.SV

1

llA

Low level input current

IIL2

-200

llA

Supply voltage

Voo

Supply voltage
High level input voltae
Low level input voltage

-20

-68

VOHl

DATA OUT, PWM OUT,
10 = - 4011A

4.3

4.9

V

High level output
voltage

VO'H2

a1-g3, D1-D13, 10 = -lmA

11.4

11.8

V

Low level output
voltage

VOLl

DATA OUT, PWM OUT,
10 = 40pA

0.1

0.4

V

VOL2

a1-g3, D1-D13, 10 = 100pA

0.2

0.7

V

Low level output
voltage

V0l3

LD1-LD9,10=20mA

0.2

1

V

High level output
leak current

ITH

LD1-LD9, Vo=Voo= 18V

10

llA

PWM IN = O'E = Vee,

0.1

mA

High level output
voltage

Low level output
~oltage

1001

VI = OV, VCC = S.OV

I-I
a 1-g3-)1: I character

Dl to D13 all high level
output, other input
terminals at OV or Vcc,
output at no load

Voo line_ supply current

1002

O'E = OV, Other input
terminals at OV or Vee,
output at no load

0.1

mA

lecl

osC=OV

Other input

0.1

mA

LIGHT SW = Vee

terminals at

ICC2
Vee line supply current

ICC3

R=51kQC .. O.04711F OVorV ee.
output at no
CR oscillaton.
load
LlGHTSW=OW

0.3

1

OSC '" OV. PWM IN = Vee
O'E '" Vcc .LOl-9:0N(Low). Other
input terminals at OVor Vee. output
at no load

9

20

mA

183

• AC characteristics
Conditions

Symbol

Parameter

MIN

TYP

MAX

Unit

1

MHz

fCLK

CLOCK

Minimum clock pulse width

twc

- CLOCK

400

nS

400

nS

Maximum clock frequency
Minimum load pulse width

tWL

LOAD

Clock input rise and breaking
time

tfe
tre

CLOCK

DATA IN~ CLOCK setup time

tsc

200

nS

DATA IN hold time

tHOLO

100

nS

DATA OUT
propagation delay
time

tpo

CLOCK~
CLOCK~

1

700

lIS

nS

DATA OUT hold time

tOH

150

nS

CLOCK~

tSL

500

nS

LOAD setup time

CR oscillation frequency

C =0.04711F,
R= 51kn

fosc

1

2

'>~k.l-O.5Vcc

O. 2V ee

4

• Timing Chart
twc

twc

CLOCK

"\

~

E

)

(

21Z""

I\.
tsc

~

~

><

DATA IN

-+-

tHOLO

'"

:K

O.7Vcc
O.2Vcc
(
(

tpo
tOH

)

'"
oO.O.7V cc

~ ~ O. 2V cc

DATA OUT
-+-

CLOCK
tSL

184

~

)B()
tWL

o.~vcc

.

'LOAD

I~

tIC

----:---.

o. 2V ee

------

-+-1

.
t;

kHz

MAJOR SECTIONS EQUIVALENT CIRCUIT
Output Gate & LED Driver
IOL

PWM

-E--

LDI
S

{

LD9

Display Data

Vo
VOL

=1VMAX

=20mA

Output Gate & VF Driver
Vo o (+9-18V)

PWM

-

Display Data

IOL

{

Level conversion

{

Vo

=(Voo -

IOH

= -1mAatV OD = 12V

Vo

=O.7V MAX

O.6V) MIN

19 l = 0.1 rnA at Voo = 12V

Dim control circuit
VCd+5V)

LlGHTSW

PWMOUT

(
128Hz

(TYP)
duty

OSC

2.048kHz

4bit Binary Counter

(TYP)

185

DATA DESCRIPTION
(Table a)
No.

Symbol

Function
Oimming control

Output terminal

1

OIM(MSB)

2

013

3

012

------

4

011

011

5

010

010

6

09

09

7

08

8

07

07
06

Oescription
"0" : 1/8duty, "1" 1116duty

013

012

Flag{VF)

08

9

06

10

OS

OS

11

04

04

12

03

03

13

02

02

"0": OFF
VF
driver

"1": ON

01

14

01

15

L09

Flag{LEO)

L09

16
17
18
19

01-8
01-4'
01-2
01-1

7 segment
d coder{ 1st digit)

al-gl

20
21
22
23

02-8
02-4
02-2
02-1

7 segment
decoder(2nd digit)

a2-g2

24
25
26
27

03-8
03-4
03-2
03-1

7 segment
decoder(3rd digit)

a3-g3

28

L08

L08

29

L07

L07

30

L06

31

LOS

32

L04

L04

33

L03

L03

34

L02

L02

35

L01(LSB)

LOl

LEO driver

7

See Table b.

Flag{LEO)

L06
LOS

VF
driver

LEO
driver

"0": OFF"1" :ON

Note: "No." indicates the output number of the shift register. The first bit for data
transfer is NO.1.

186

7 SEGMENT DECODER DISPLAY PATTERN
(Table b)
Input data

Output
Display
pattern

8

4

2

1

a

b

c

d

e

f

9

0

0

0

0

0

1

1

1

1

1

1

0

I I
I I

1

0

0

0

1

0

1

1

0

0

0

0

I
I

2

0

0

1

0

1

1

0

1

1

0

1

3

0

0

1

1

1

1

1

1

0

0

1

4

0

1

0

0

0

1

1

0

0

1

1

II
-I

5

O·

1

0

1

1

0

1

1

0

1

1

I
-I

6

0

1

1

0

1

0

1

1

1

1

1

I
I-I'

Remarks

-

_I

-I
-I
-I
-

-

7'

0

1

1

1

1

1

1

0

0

1

0

II
I

8

1

0

0

0

1

1

1

1

1

1

1

I I'
I-I

9

1

0

0

1

1

1

1

1

0

1

1

U

A

1

0

1

0

1

1

1

0

1

1

1

B

1

0

1

1

0

0

1

1

1

1

1

C

1

1

0

0

0

0

0

1

1

0

1

D

1

1

0

1

0

1

1

1

1

0

1

I-I

E

1

1

1

0

1

0

0

1

1

1

1

I
I

F

1

1

1

1

0

0

0

0

0

0

0

MSC1179GS-K:"

I
I"

-

-I

I I

-

I I

I

I-I

-I
-

I

-

-

Blank

187

FUNCTIONAL DESCRIPTION
•

DATA IN, CLOCK, LOAD:

Data set input terminals

(MSB)

DATA IN
CLOCK
LOAD
Display
contents

(LSB)

"l"
"0"

----~

----------------Jr'"--

_ _ _ _ _ _ _ _ _ _ ------- _ _ _ _ _ _ _ _ _ _ _ _XOata set display

Fig. a Data set timing chart example (PWM = 1, O·E = 1)
\

DATA IN is a data input terminal, Which is read into the internal shift register at the leading edge
of the clock input terminal CLOCK.
LOAD is a load input terminal, which loads data of the shift register, data of 35 bits at a time, into
the latch circuit. The timing chart above shows that, when a pulse is input to the LOAD terminal
after the data of 35 bits is input, the display data is ch~nged to a new one.

o

DATA OUT:

Data output terminal

DATA OUT is a terminal for cascade connection, the output of ~hich is connected to the DATA IN
terminal on the next stage.

MSC1178GS-K
IMSC1179GS-K
DATA IN
CLOCK

~---i

DATA IN DATA
CLOCK
OUT·
LOAD

MSC1178GS-K
IMSC1179GS-K

1--_--1

DATA IN
CLOCK
LOAD

"--------'

LOAD

Fig. 'b Cascade connecton

188

•

OSC:

Oscillation terminal

OSC is a capacitor (C) and resistor (R) connection terminal of the oscillation circuit for

d~ming

control. The oscillation frequency depends on the values of the external capacitor (C) and resistor
(R).

MSC 1178GS-K
IMSC1179GS-K

R
t-----~OSC

(Vss)
Fig. c External.circuit

The value for R should not be less than 30 kil. The oscillation frequency fose is expressed by the
following equation:
fose = _k_

C' R

(k; 5)
•

When no oscillation circuit is used (i.e the PWM OUT terminal is not used), connect the OSC
terminal to Vss.

o LIGHT SW :

Light switch input terminal

LIGHT SW is an input terminal with a pull-up resistor, which controls the PWM OUT output
waveform.(See Table c. )

o PWM OUT:

PWM output terminal

PWM OUT is a dimming PWM output terminal. When this terminal is connected to the PWM IN
input terminal, the display duty ratio can be changed to 1/1, 1/8, or 1/16. Table c is a function
table.
(Table c)
Display duty ratio

LIGHT SW input

MSB of data

Open or "H"

-

1/1

"L"

0

1/8

ilL"

1

1/16

II

"H
ilL"
[ -

Vee level
; Vss level
don't care
;

1

The frequency of a PWM OUT output signal is foscl16.
189

•

PWM IN:

PWM input terminal

PWM IN is C1dimming PWM input terminal. If the input is made High when the O·E is High, the
display is turned ON. If the input is made Low, th~ display is turned OFF.
Accondingly, when a signal at 100 to several 1OOs Hz (the duty ratio is variable) is input to the PWM
IN terminal, the display brightness can be continuously controlled.
When the PWM OUT output is connected to the PWM IN terminal, the display duty ratio, as
mentioned above, can be changed to one of the three values.

Vee level
Vss level

Display

I~I

)I

t,

)I

I~I(
ON

(lIt, = 100 to several laOs Hz)

OFF
Fig. d PWM IN input waveform

•

O·E:

Display output enable input terminal

When the input is High, the display state is normal. When the input is Low, all displays are turned
OFF.
If the O·E is kept low until the data of the latch circuit is determined when power is turned ON,
unnecessary displays can be eliminated.
Two O·E and PWN IN input signals are ANDed in the Ie to a PWM signal. The display is ON (normal)
when PWM =" 1" or OFF when PWM = "0".

l>
-a
-a

C

n
l>
~

+12V

§

~

~ ;:;- S' ~ ~
III ~~ ~ 3
~03~~
"0

3

50

S':I: S

o.C~O""

ID

:l

Vee -

"0

° ;;;.

m

an-g n
01-013
CPU

'g.~~a~

MSC
1178GS-K

c:~~o:o.

o ,,' c: ::::.:

z

o-f

Vee

~a:ao:J
::!.'

z

I"

o·

~f:;~~~
~ ID -""0 :l

o

*1

0-

~o~"<;
0 .... . , _ 0

L09
VF display

....

° . . . '"
:-~.~~~
'" ID

., ., c:

0"

III

ID

.,

3

*4

~'§:~~
Q. t:' 0"

48

OSC

44

O'E

ID

0"0"<; 0.

47

~.
::-~o
:::I:r-O"

"0 ::; ..... ID
::::,0.° 111

GNO

£ ~ ~§
g' ~ f:; ~
° .....Il!

*31

c

(MSC
1179GS-K)

LD7

LlGHTSW
PWM
OUT

LD)

IN

Vss OATAOUTI

LED

*216

II>

;; ~ g ~.
~s:~~
3 ~ ~
!!: III III III
:o'''<;~ ~

Note:

::l

*4

--

1.0

R=51Idl.C"O.047\lF(exam·ple)

* 1 The voltage for the LED may be supplied from + 12 V (Voo).
*2 When the DATA OUT terminal is connected to the DATA IN terminal on
the next stage. the system is made expandable. (See Fig. b. )
*3

Ifthe dimming control switch is turned ON. the VF display output duty
ratio is changed from 111 to 118 or 1116 (depending on the MSB of data).
(See Tables a and c. )

OKI semiconductor
MSC1190
7-SEGMENT DRIVER

GENERAL DESCRIPTION
The MSC1190GS is a Bi-CMOS structure static display driver to directly drive a vacuum fluor~scent
(VF) display tube. The driver has a structure of a 56-pin flat packa~e, which consists of a 35-bit shift
register, latch circuit, 7 segmemt decoder, VF' high voltage driver, LED dot driver, and dimming
control circuit.
The driver is suited to a driver for frequency or clock display of an automobile digital tuning
system.

FEATURES
•

56-pin flat package

•

2 supply voltages ( +' side)
Interface, logic portion, LED driver:
VF display driver:

Vee = + 4.5 to + 5.5 V

Voo = + 9 to + 18V

•

VF tube driven by positive voltage (Voo = + 18V MAX)

•

VF tube directly connected without a pull-down resistor
(CMOS push pull output)

•

Dil"Dming oscillation circuit built in (capacitor and resistor externally connected)

•

Dimming control circuit built in, with duty (1/1, 1/8, or 1/16) selector input terminal (LiGHTSW). Use the most significant bit (MSB) to select 1/8 or 1/16.

•

With PWM IN inputterminal to allow the PWM to continuously control dimming, witl~ external
PWM generation circuit (the LED driver is not affected by PWM IN input)

•

VF driver:

I

(10

3-digit 7 segment output, 13 flag outputs

= - 1 mATYP)
9 dot outputs (10 =25mAMAX)

•

LED driver:

•

Easily interface,d with microprocessor (by three inputs of DATA IN, CLOCK, and LOAD)

192

t:C

r-

"

o
n

A

o
~

G')

DATA IN
CLOCK

JL

>

I
LSB

, LOAD
/

-:z- ...... ...
'"

!>

...

_

....... ....... .......

......

D

I

JL

.::. ..:J

_

~

D

QI

....

~

LA

~

..., _

Cl

..... ' "

,.

w

1

. ..

-

....

. ..

- ....

. ..

I

17Decoder
Segment 1/7 Segment //7 Segment 1
Decoder
Decoder

I

1 Out Put Gate ~

Vss

---- -~F1:--.r!- +1,

.... .... .... ....

I

LED Driver

1 (NPN Open Drain)

(9 pins)

1

OutpufG'ate

I

I

I

~o,

~

~
I I

TT I

I

1

VF Driver (VDD : tBV MAX) (34 pins)

I

0- '--

C

C

fee

.C

'c

J

6_ 6N 6W '6.6
0"0 G
.
w 6
~

\D
W

~

~

~

(

,( C

~e;_c.e.

,c I (

e. ~'e

( C, C C C ( C
• II
.....

ern
_-...,.
-Q."_~

....

( 'C ( ( ( ( (

~I~;~:!:~ ~~

o

-

9 · ~·~·~· · · fC
~

~Dim.
~~
Control

(OV)

o

DATA OUT

I
+1·_z- MSB'

Latch (3Sbits) (Level latch by LOAD signal)

l

~

Vee
(+ SV)

.

....

::a

I

Shift Registor (35 bits)

c«

«

C

0 0 0010 0 0 0

N .....

"":Q'IO

a

_.CA.tA(;

C

(

=;: :.-:

000

TVss'
lIEGHTSW

~

PWM OUT

f-o' PWMIN

-

O'E

Voo
(+ 9-1BV)

~

~

PIN CONFDIGURATION,
(Top View) 56 Lea~ Plastic Flat Package

01
gl
fl
al

N

0

0

0

u

~

~

 >

VI

->

u

Vl

0

.-

~

~
~ ~

0

l!:}
~
~ a..
:J a.

w

6

0

010
el
dl
cl

bl

09

g2 .
f2

e2

a2

c2

b2

08

g3

e3

f3

d3

a3

c3

b3

07

02

06

d2

Note-; Pin 21 with a * mark is connected to
Vss, and cannot be connected to
another pin. Pin 21 cannot be used
independently as Vss but can be used
as a Vss reinforcing line.

194

ELECTRICAL CHARACTERISTICS
• Absolute maximum ratings
Parameter

Condition

Limits

Unit

Supply voltage

Voo

-0.3 ..... + 19

V

Supply voltage

Vee

- 0.3 ..... + 6.5

V

- 0.3 ..... Vee + 0.3

V

Input voltage
Maximum output current
Allowab,le package loss
Storage temperature

•

Symbol

VI

IOLD

DATA IN, CLOCK, LOAP
LIGHT SW, PWMIN, O·E,
OSC
LD1 ..... LD9

Po
Tstg

30

mA

300

mW
O(

- 55 ..... + 150

Recommended Operating Conditions
Parameter

Symbol

Condition

MIN

TYP

MAX

Unit

Supply voltage

Voo

9

12

18

V

Supply voltage

Vee

4.5

5

5.5

·V

Input voltage

VIH

DATA IN, CLOCK, LOAD
LIGHT SW, PWMIN, O·E

0. 7V ee

Vee

V

Input voltage

VIL

DATA IN, CLOCK, LOAD
LIGHT SW, PWMIN, O·E

0

0. 2V ee

V

Output current

IOLD

LD1 ..... LD9

25

mA

Operating temperature

Top

+85

°C

15
-40

195

•

DC characteristics
(Unless otherwise specified,
Parameter

Symbol

Supply voltage

Vee=5V,

Voo= 12V,

Condition

Ta= -40to + 85°C)

MIN

TYP

MAX

Unit

Voo

9

12

18

V

Supply voltage

Vce

4.5

5

5.5

V

High level input voltae

VIH

DATA IN, CLOCK, LOAD

0. 7V ee

Vce

V

Low level input voltage

Vil

LIGHT SW, PWM IN, O·E

0

0. 2V ee

V

Input leak

IILl

DATA IN, CLOCK,
LOAD
Vee=5.5V
PWM IN, O·E, VI = Vee orOV

±1

llA

High level input
leak current

IIH

LlGHTSW IVI = VCC = 5.5V

1

llA

Low level input current

IIl2

-200

llA

VI = OV, VCC = 5:0V

-20

-68

4.3

4.9

V

11.4

11.8

V

High level output
voltage

VO Hl

DATA OUT, PWM OUT,
10 = - 4011A

High level output
voltage

VOH2

al-g3, Dl-013, 10 = - lmA

Low level output
voltage

V OLl

DATAOUT,PWM OUT,
10 = 40 11A

0.1

0.4

V

Low level output
voltage

VOl2

al-g3, 01-013, 10= lOO11A

0.2

0.7

V

Low level output
voltage

V Ol3

LD 1-LD9, 10 = 25mA

0.25

0.8

V

High level output
leak current

ITH

L01-LD9, Vo=Voo= 18V

10

llA

PWM IN = O'E = Vee,

0.1

mA

1001

.

I-I

a l-g3~1: I character
D1 to 013"all high level
output, other input
terminals at 0 V or Vee,
output at no load

Voo line supply current

.

1002

O'E = OV, Other input
terminals at 0 V or Vee,
output at no load
"

0.1

mA

leel

ose .. ov

0.1

mA

LIGHT SW .. vee
ICC2

Vec line supply current

ICO

196

Other input
terminals at

R.. SlkOC .. O.04711F OVorvec,
output at no
CR oscillaton,
load
lIGHTSW=OW

0.3

1

OSC=OV,PWMIN .. Vee
O·E =VeC,l01-9:0N(low), Other
input terminals at 0 Vor Vee, output
at no load

9

20

mA

o AC characteristics
Vee = 5V
Parameter

± 10%, Ta = - 40- + 85°C, CL = 10PF

Symbol

Conditions

Maximum clock frequency

feLK

CLOCK

Minimum clock pulse width

twe

CLOCK

, 400

nS

Minimum load pulse width

tWL

LOAD

400

nS

Clock input rise and breaking
time

tfc
trc

CLOCK

DATA IN~ CLOCK setup time
CLOCK~
CLOCK~

DATA IN'hold time
DATA OUT
propagatiotl delay
time

MIN

TYP

MAX

Unit

1

MHz

1

l1S

tsc

200

nS

tHOLO

100

nS

I

700

tpo

nS

DATA OUT hold time

tOH

150

nS

CLOCK~

tSL

500

nS

LOAD setup time

CR Oscillating frequency

C = O.04711F,
R= 51kQ

fosc

1

4

2

kHz

TIMING CHART

..
CLOCK

~

twe

»-

~

7~

twc
IE

~

."",

2

f"

.>rt-0.svcc

I~

~

tsc
~

~

DATA IN

f"

~

O'2V~cy O.7Vcc

tiC

tHOLO
OlE

~

IE

tpo
tOH

O. 7Vcc
O. 2V cc

~I

t,c

~

X
IE

)0

)0

o. 7V cc

~ ~ o, 2V cc

DATA OUT

~

~

o. 7Vcc
CLOCK

1~..~-t_SL-~~i?4"
tWL
)0

o.svcc
LOAD

- - - - - - - - - -. .2Vc c ' -'--------'197

MAJOR SECTIONS EQUIVALENT CIRCUIT
Output Gate & LED Driver
OE

IOL
~

LDI
I
o LD9

Display Data

Vo =O.8vMAX
VOL = 2SmA

Output Gate & VF Driver
VD D (+ 9-18V)
PWM

Display Data

Vo =(Vo o -O.6V)MIN
IOL = -lmAatVoo= 12V

Level conversion

Vo =O.7VMAX
IOL=O.lmAatVoo= 12V
Dim control circuit
Ved +SV)

.~
MSB

80kQTYP

~
~

LIGHTSW

PWMOUT

(
128Hz

(TYP)
duty

OSC

2.048kHz

(TYP)

198

4bit Binary Counter

DATA DESCRIPTION
(Table a)
No.

Symbol

Function

1

DIM(MSB)

Dimming control

2

D13

DB

Output terminal

Description
"0" : 1I8duty, "1" 1/16duty

3

D12

D12

4

Dll

Dll

S

Dl0

Dl0

6

D9

7

D8

8

D7

D7

9

D6

D6

10

DS

DS

11

D4

D4
D3

"0": OFF

D9
Flag(VF)

D8

12

D3

13

D2

D2

14

D1

Dl

1S

LD9

Flag(LED)

LD9

16
17
18
19

Dl-8
D1-4
Dl-2
D1-1

7 segment
decoder(lst digit)

al-g1

20
21
22
23

D2-8
D2-4
D2-2
D2-1

7 segment
decoder(2nd digit)

a2-g2

24
25
26
27

D3-8
D3-4
D3-2
D3-1

.7 segment
decoder(3rd digit)

a3-g3

28

LD8

LDS

29

LD7

LD7

30

LD6

31

LDS

32

LD4

33

LD3

LD3

34

LD2

LD2

3S

LD1(LSB)

LDl

VF
driver

"1": ON

,

LED driver

See Table b.

Flag(LED)

LD6
LDS
lD4

VF
driver

I

LED
driver

"0": OFF
"1": ON

Note: "No." indicates the output number of the shift register. The first bit for data
transfer is NO.1.

199

7 SEGMENT DECODER DISPLAY PATTERN
(Table b)
Output

Input data

8

4

2

1

a

b

c

d

e

f

9

0

0

0

0

0

1

1

1

1

1

1

0

1

0

0

0

1

0

1

1

0

0

0

0

2

0

0

1

0

1

1

0

1

1

o.

1

3

0

0

1

1

1

1

1

1

0

0

1

4

0

1

0

0

0

1

1

0

0

1

1

II
-I

5

0

1

0

1

1

0

1

1

0

1

1

I
-I

6

0

1

1

0

1

0

1

1

1

1

1

n

I

7

200

0

1

1

1

1

1

1

0

0

1

0

Display pattern

-

I I
I I

-

1
1
_I
I

-I
-I
--

I

-

II
1

I I
I-I
-U
I
I I
-I I

8

1

0

0

0

1

1

1

1

1

1

1

9

1

0

0

1

1

1

1

1

0

1-

1

A

1

0

1

0

1

1

1

0

1

1

1

B

1

0

1

1

0

0

1

1

1

1

1

C

1

1

0

0

1

0

0

1

1

1

0

I

D

1

1

0

1

0

1

1

1

1

0

1

I-I

E

1

1

1

0

1

0

0

1

1

1

1

F

1

1

1

1

0

0

0

0

0

0

0

.

1

I-I

-I

1

I
I-

Blank

FUNCTIONAL DESCRIPTION
o

DATA IN, CLOCK, LOAD:

Data set input terminals

(MSB)

DATA IN

=

"1"
"0"

(LSB)

CLOCK

-------------"1'1....--

LOAD
Display
contents

_ _ _ _ _ _ _ _ _ _ ------- _ _ _ _ _ _ _ _ _-.JXData set display

Fig. a Data set timing chart example (PWM =1, O·E =1)

DATA IN is a data input terminal, which is read into the
ofthe clock input terminal CLOCK.

int~rnal

shift register at the leading edge

LOAD is a load input terminal, which loads data of the shift register, data of 35 bits at a time, into
the latch circuit. The timing chart above shows that, when a pulse is input to the LOAD terminal
after the data of 3S bits is input, the display data is changed to a new one.

•

DATA OUT:

Data o~tput terminal

DATA OUT is a terminal for cascade connection, the output of which is connected to the DATA IN
terminal on the next stage. \

MSCl190 GS

DATA IN

~---;

DATA IN DATA
CLOCK
OUT
LOAD

MSCl190 GS

I---~--l

DATA IN
CLOCK
LOAD
L
-_ _ _ _- - - '

CLOCK
LOAD

Fig. b Cascade connecton

201

o OSc:

Oscillation terminal

OSC is a capacitor (C) and resistor (R) connection terminal ofthe oscillation circuit for dimming
control. The oscillation frequency depends on the values of the external capacitor (C) and resistor
(R).

MSC 1190GS

R

._--'-----1 OSC

(Vss)
Fig. c External circuit
The value for Rshould not be less than 30,kQ. The oscillation frequency fosc is expressed by the
following equaton:
fosc =

c.k R

(k ~ 5)

When no oscillation circuit is used (i.e the PWM OUT terminal is not used); connect the OSC
terminal to Vss.

o LIGHT SW :

Light switch input terminal

LIGHT SW is an input terminal with a pull-up resistor, which controls the'PWM OUT output
waveform.(See Table c. )

o PWM OUT:

PWM output terminal

PWM OUT is a dimming PWM output terminal. When this terminal is connected to the PWM IN
input terminal, the display duty ratio can be changed to 1/1, 1/8, or 1/16. Table c is a function
table.
(Table c)
LIGHT SW input

MSB of data

Display duty ratio

Open or "H" .

-

1/1

"L"

0

1/8

"L"

1

1/16

"H" '. Vcc level
"L" ; Vss level
[ don't care

1

The frequency of a PWM OUT output signal is fosel16.
202

o PWM IN:

.'

PWM input terminal

PWM IN is a dimming PWM input terminal. If the input is made High when the O·E is High, the VF
display is turned ON. If the input is made Low, the display is turned OFF.
Accondingly, when a signal at 100 to several 1OOs Hz (the duty ratio is variable) is input to the PWM
IN terminal, the display brightness can be continuously controlled.
When the PWM OUT output is connected to the PWM IN terminal, the display duty ratio, as
mentioned above, can be changed to one of the three values.

Vee level

(
1~I

Vss level
(lIt, = 100 to severall00s Hz)

VF Display

ON

OFF
Fig. d PWM IN \nput waveform

•

Q·E:

Display output enable input terminal

When the input is High, the display state is normal. When the input is Low, all displays are turned
OFF,
IF the O'E is kept Low until the data of the latch circuit is determined when power is turned ON,
unnecessary displays can be eliminated.
Two O·E and PWN IN input signals are ANDed in the Ie to a PWM signal. The VF display is ON
(normal) when PWM =" 1" or OFF when PWM = "0". The LED display is turned ON or OFF by O'E
input but not affected by PWM IN input.

203

IV

»
""C

o

~

""C

r

n

»
::!

+12V ____________________~--------------------~

o

*1

2

+5V
§a?:~5"
~
s..~.::EO'
..., ~:J It) ...,

~ a-~ ~ ~
~ 33,-' ::!:
~~~~g
~

S;;

~ ~

..,. tl) ...... "0 :l
~ •• ~1:l 0 ~.

CPU
MSC
1190GS

~~.~~~

~:;; ~~. ~

~~. ~ ~

tl):J" Q.. 0::
Q.. ~ 0" tl)

O"o, D'~'C
Voo( + SV)
VSS (OV)
VEE (- 20-40)

0

r

0:1:

I

~

DOWN

~ ~

L 4 D'C'R

~OUNTER

t

~

r

DUTY

cym

1>T r

COUNTER

DIGIT TME COUTER

BLANK ~UTY

W

I

(0)

(11)

012

LED DRV

~
1LEDI

00-4

L

~

L-R LOAD

.......
~

I

-I

n

x-

x12

r

~
~

-a.
-a.

1

1~

,:::J

~

SEG P (b 1s)

D1

I 01

»
»
Ci')

SEG A (boJ

I

PLA0R
DECODER

LATCH

"0

_J

LEOS

xS

X

3!

z

n

o
Z

-n
MSC7112-xxSS
(Top View) 42 Lead Plastic Shrink DIP

MSC7110-xxSS
(Top View) 42 Lead Plastic Shrink DIP

Ci)

C
:::0

»

OSCI

~

LOAD

OSCI

LOAD

OSCO

DATA IN

OS CO

DATA IN

P.O.R

SCLK

P.O.R

SCLK

VOO

SEGA

VOO

SEGA

01

SEG B

01

SEG B

02

SEG C

02

SEG C

03

SEG 0

03

SEG 0

04

SEG E

04

SEG E

OS

SEG F

OS

SEG F

06

SEGG

06

SEGG

07

SEG H

07

SEG H

08

SEG I

08

SEG I

09

SEG J

09

SEG J

010

SEG K

010

SEG K

011

SEG L

011

SEG L

012

LED 1

012

SEGM

013

LE02

LEOl

SEG N

014

LE03

LE02

SEGO

01S

LE04
VEE ~

LED 3

SEG P

016

LE04

VEE

LEOS

VSS

LED 5

VSS

::!
'0
z

N
~

""C

N

2

n

o
2

:!2

Mse7110-xxGS
(Top View) 44 Lead Plastic Flat Package

Gl
C

MSC7112-xxGS
(Top View) 44 Lead Plastic Flat Package
-- o·

~~CTlCI)"

::0

»

::j

w
.... \oLn'
0
u

~

0

~

a.
\.?

w

U

0

6

VI

I

~

:1

\.?

I~

UJ
VI

~

~

0
0

>

~
...J

~

U

0

VI

0

->

~

0

...J

....

~t::
a.

.... 0
::J

o
,

'C1I

o

0 ....

>

.- E

o

'-

::J

va.

~e

VI

->

>
o

"C

DATA IN

b)

Data Word LSB/MSB Timing

END OF
DATA WORD~
LSB

14~~-----

~MIN

40US

230

------I

~

E----------- MIN

I.....

NEXT DATA WORD

120 US --------~

FUNCTIONAL DESCRIPTION
. The MSB value of 8-bit serial data determines whether the input data into MSC1937-01 is control
,data or display data .

.,

CONTROL DATA
. The control data can be input by setting MSB to "1". In addition, a command type and
associated data with the command is determined by the bit 6 to bit O.

Command

Function

MSB
bit 7

bit6

bit 5

bit4

bit3

bit2

bit 1

LSB
bitO

Buffer Pointer
Control

Specifies the RAM
address.

1

0

1

0

23

22

2'

20

Digit Counter
Control

Sets the number of
display digits.

1

1

0

0

23

22

2'

20

Duty Cycle
Control

Sets the duty value.

1

1

1

24

23

22

2'

20

TEST MODE

Sets the test mode.

1

0

0

20

X

X

X

X

X: Don't care

a) Buffer Pointer Control
This command changes the display contents only at an arbitrary digit. (The RAM write
address is set.)
Adecimal equivallent value of bits 0 - 4 should be set (desired digit number - 2).
(Example) When specifying AD4, the set value is 2 (0010).
Specified digit

Set value of
bits Ot04

Specified digit

Set value of
bits 0 t04

ADl

15 (1111)

AD9

7 (0111)

AD2

0 (OOOO)

AD10

8 (1000)

AD3

(0001)

AD11

9 (1001)

AD4

2 (0010)

AD12

10 (1010)

ADS

3 (0011)

AD13

11 (1011 )

AD6

4 (0100)

AD14

12 (1100)

AD7

5 (0101)

AD15

13 (1101 )

AD8

6 (0110)

AD16

14 (1110)

231

b) Digit Counter Control
This command sets the number of display digits.
Set the desired number of digits in bits 0 to 4.
Number of
display digits

Set value of
bits 0 to 4

Set value of
bit Ot04

Number of
displaydigits

(0001)

9

9 (1001)

2

2 (0010)

10

10 (1010)

3

3 (0011)

11

11 (1011)

4

4 (0100)

12

12 (1100)

5

5 (0101)

13

13 (1101)

6

6 (0110)

14

14 (1110)

7

7 (0111)

15

15 (1111 )

8

8 (1000)

16

o (0000)

c) Duty Cycle Control
This command sets the duty cycle of the driver output. This command allows the
brightness to be adjusted by 1/32 step. As shown in Figure 1, the blank type between digits
or between the segments is specified by 1 bit time on the hardware. Therefore, the set
value ranges from Oto 31.

I

i~'-r--------- 1 DISPLAY CYCLE - - - - - - - - .

GND
AD1
AD2
AD3
, AD4
ADS
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16

SGX

l

:31 BIT TIMES

512 BIT TIMES

v~
n
~~1_B_IT_.T_IM_E_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~~~----------

•

::

,i

~'_,~:

n
___

________________________________n

~---------------------------------------~

~rI~

-r~------~rI~--------------~-------------------~~
-+-r--------~rI~-------------------------~~

__________

~rt~

________________________________

-r~----------~rI~-------------------------------+-r--------------~rI~---------------------------­
~~--------------------~rt~-------------------------------------------------------JrI~------------------------------___________________________

-r
__________________________
-+-r
~~--------------------------~rI~------------------------__ ______________________________ _________________
____________________
-+~---------------------------------~r!L---------------__ _____________________________________ __________
GND -: ,- 31 BIT TIMES
·V -t1f!--_____
_______________________
________
~r!L_

~

~rI~

-+-r-------------------------------~rI~
~

~rt~

~rI~

i-I!-

1 BIT TIME

~rILF!~

Note: At the time of Duty Cycle

Figure 1 Output timing
232

~------

~~

=31

d) TEST MODE
This mode is not a user function, but is used for outgoing inspection.

•

DISPLAY DATA

=

By setting MSB '0', the display data can be entered. The address of PLA is specified by bit 6 to
bit 0 following MSB.
Table-1 provides the PLA code table.

()() 0_1I
01
~-

02

I-03

1- J
I I
-1-1

08

I I
1- -I
-

09

-

I
I
--

11

I

-

-

08

1_ J
I

18

\1
1\

I
\

28

20

30

I--

_0 C

DATA IN

b)

Data Word LSB/MSB Timing

END OF
DATA WORD~
LSB

I~----";"--

~MIN

40US

~

...--------------



NEXT DATA WORD

MIN 120US --------~I

241

FUNCTIONAL DESCRIPTION
The MSB value of 8-bit serial data determines whether the input data into MSC19S1-01 is control
data or display data.

•

CONTROL DATA
The control data can be input by setting MSB to" 1". In addition, a command type is
determined by the bit 6to bit~ following MSB.

Command

Function

MSB
bit 7

bit6

bitS

bit4

bit3

bit 2

bit 1

LSB
bitO

I

Buffer Pointer
Control

Specifies the RAM
address.

1

0

1

0

23

22

2'

20

Digit Counter
Control

Sets the number of
display digits.

1

1

0

0

23

22

2'

20

Duty Cycle
Control

Sets the duty value.

1

1

1

24

23

22

2'

20

TES'r MODE

Sets the test mode.

1

0

0

20

X

X

X

X

X: Don't care

a) Buffer Pointer Control
This command changes the Qisplay contents only at an arbitrary digit. (The RAM write
address is set.)
To input data into bits 0 to 4, set (desired digit - 2).
(Example) When specifying AD4, the set value is 2 (0010).
Specified digit

242

Set value of
bits Ot04

Specified digit

Set value of
bits 0 to 4

AD1

15 (1111)

AD9

7 (0111 )

AD2

0 (0000)

AD10

8 (1000)

AD3

(0001)

AD11

9 (1001)

AD4

2 (0010)

AD12

10 (1010)

ADS

3 (0011 )

AD13

11 (1011)

, AD6

4 (0100)

AD14

12 (1100) .

AD7

S (0101)

AD15

13 (1101)

AD8

6 (0110)

AD16

14 (1110)

b) Digit Counter Control
This command sets the number of display digits.
Set the desired number of digits in bits 0 to 4.
Numberof
display digits

Set value of
bitsOto4

Number of
display digits

Set value of
bitO to 4

(0001)

9

9 (1001)

2

2 (0010)

10

10 (1010)

3

3 (0011)

. 11

11 (1011)

4

4 (0100)

12

12 (1100)

5

5 (0101)

13

13 (1101)

6

6 (0110)

14

14 (1110)

7

7 (0111)

15

15 (1111)

8

8 (1000)

16

o (0000)

c) Duty Cycle Control
This command sets the duty cycle of the driver output. This command allows the
brightness to be adjusted by 1/32 step. As shown in Figure 1, the blank type between digits
or between the segments is specified by 1 bit ti me on the hardware. Therefore, the set
val ue ranges from 0 to 31.

GND
AD1
AD2
AD3
AD4
ADS
AD6
AD7
ADS
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16

-v

I

: I

-

1 DISPLAY CYCLE .
512 BIT TIMES

:31 BIT TIMES

--[3-r::;
I

GND
SGX

l'

J\

n

1 BIT TIME

n

n

n

n

n

n
rL'L-

n

n

n

n

n

n

n

n

n

n

n

:- 31 BIT TIMES
I

n

-v --hf!

1-11-

1 BIT TIME

Note: At the time of Duty Cycle

. Figure 1

n....n
=31

Output timing
243

d) TEST MODE
This mode is not a .user function, but is used for outgoing inspection .

•

DISPLAY DATA
By setting MSB= '0', the display data can be entered. The address of PLA is specified by bit 6 to
bit 0 following MSB.
Table-1 provides the PLA code table.

244

Input Code

Segment Driver Output Patterns (1 = On)

Function
7 6 5 4 3 2 1 0
0
0
0
0
0

o
o
o
o
o
o
o
o
o
o
o

XO'OOO
X 0 0 o 0
X 0 0 o 0
X 0 0 0 0
X 0 0 0 1
X 0 0 0 1
X 0 0 0 1
X 0 0 0 1
X 0 0 1 0
X 0 0 1 0
X 0 0 1 0
X 0 0 1 0
X 0 0 1 1
X 0 0 1 1
X 0 0 1 1
X 0 0 1 1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

0 X 1
0 X 1
0 X 1
X 1
X 1
X 1
X 1
X 1
X 1
X 1
oX 1
X 1
oX 1
X 1
X 1
·0 X 1

0

0
0
0
0

o
o
o
o
o
o
o
o
o
o
o
o

X
X
X'
X
X
X
X
X
X
X
X
X
X
X
X
X

o
o
o
o
o
o
o
o

o
o

oX
oX
oX
oX
oX
oX
oX
oX
oX
oX
oX
oX
oX
oX
oX
oX

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

SegmentAOn
Segment B On
Segment COn
Segment DOn
Segment EOn
Segment F On
Segment G On
Segment H On
Segment I On
Segment) On
Segment K On
Segment LOn
Segment M On
SegmentN On
SegmentO On
SegmentPOn

1

0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

SegmentAOn
Segment A & B On
Segment A·C On
Segment A·D On
Segment A·E On
Segment A·F On
Segment A·G On
Segment A·H On
SegmentA·IOn
Segment A·) On
Segment A·K On
Segment A·L On
Segment A·M On
Segment A·N On
Segment A·O On
Segment A·P On

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Number 0
Number 1
Number 2
Number 3
Number4
Number 5
Number 6'
Number7
NumberB
Number9
Letter P
Letter L
Comma
Blank
Decimal
Blank

1

0 0 0 0
0 0 0 1
0
1 0
0 0 1 1
1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0
0
1 0
1
1 0 1 0
1 0 1 1
1 1
0
1 1
1
1 1 1 0
1 1 1 1

NumberO
Number 1
Number 2
Number 3
Number4
'Number 5
Number6
Number 7
NumberS
Number9
Letter A
Letter B
Letter C
Letter D
Letter E
Letter F

0
0
0
0
0
0

o
o
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

o0

o0
o0
o0
o0
o0
o0
o0
o 1
o1
0 1
0 1
1
0 1
0 1
1

o
o
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

o

SGA

0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
1
1

o
o
1
1

o
0
1
1
0
0
1
1
0
0
1
1

o

o

o

o
o

o
o

SGS

SGC

SGD

SGE

SGF

SGG

SGH

SGI

SGJ

SGK

SGl

SGM SGN

SGO

SGP

PNT

TAIL

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1

'1
1
1
1
1
1
1

J
1
1
1
1
1
1
1
1
"
1
1
1

1
1
1
1

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
1
1
1

1

1

1

1
1

1

1
1
1
1
1

1
1
1
1
1
1
1
1
1

1
1
1
1
1

1
1
1
1

1
1
1
1
1
1
1
1
1
1
1

1
1
1
1

1

1
1
1
1

1

1

1
1

1

1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1

Table-l

1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1

1
1
1
1
1
1
1

1
1
1
1
1
1

1
1
1
1
1

1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
1
1

1
1

1
1

1
1

1
1

1
1

1

1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
1
1
1
1

1
1
1
1

1
1
1

1
1

1

1
1

1
1

1
1

1
1
I'

1
1

1
1

1
1

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
1

I'

I"

1

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

I'

PLA Code Table

,245

08

00

I

01

09

10

11

18

-I
-

02

03

04

05

06

07

I

I
I

-

OA

OB

OC

00

OE

OF

I

12

13

I

19

1A

-I
-- I

1B

14

I
I I

1C

15

I I
I I'

10

16

I I
I I

1E

17

I- I
I I

---

1F

-

,-- I

I I

I I
-,
I
-I- I
I- I
I-i
I I

-1 I
I I
I- I
I I

--

I- I
I- I

I 1
I I

28

I
I

29

-

21

-

22

I
I--

23

=1

24

I I
-I

25

26

-

I-

-

-- I

- ,
-I
I
I
-I
I
30

2C

-1 I
I

-

32

33

I-

I
I

2F

,•

34

• 35

.

SGF

I~

-I

I I
I

3C

-I

3D

II I

3E

-

I-

-

36

37

-- I

SGC
SGD

Table-2

3A

3B

SGB

SGE

-

39

-I

SGG

,

I

38

-

20

2E

I I
I

31

I,
2B

I
I- I

--

27

I

2A

-

I I
I I

SGA

16-SEGMENT
BARGRAPH

246

I- I

-

20

--

--

SGP
SGO
SGN
SGM
SGl
SGK
SGJ
SGI
SGH
SGG
SGF
SGE
SGO
SGC
SGB
SGA

,-- 1

PNT
TAil
7-SEGMENT
ALPHANUMERIC

PLA Code (At the time of 7-segment displ~y)

I

3F

l--I
I I

,-- I

-I
-

'-I

1 I

I
I- I

-

-

I
I

I
I- I
I
I

I

-

I

00 01

02

03

04

05 06

07

08 09 OA

011

OC 00

OE

OF

7·SEGMENT
CHAnACTEns .

SeE FIGURe 2
SGP
SGO
SGN
SGM
SGl
SGK
SGJ
SGI
SGIf
SGG
SGF
SFE
SGO
SGC
SGB
SGA

_
_
_.
_
_
_
_
_
_
_
_
_
_
_
_
_

IlAnGnAPli
CODES

10

11

12

13

14

15

16

17

16

19

1/\

III

1.C

10

IE

IF
7·SEGMENT
CHAnACTEns

SEE FIGUnE 2
SGP
SGO _
SGN _
SGM_
SGl _
SGK _
SGJ _
SGI _
SGli_
SGG _
SGF _
SGe _
SGO _
SGC _
SGB _
SGA _

BAnGnAPH
CODES

I/o

20

SGP _
SGO_
SGN _
SGM_
SGl _
SGK _
SGJ _
SGI _
SGH _
SGG _
SGF _
SGE _
SGO _
SGC _
SGB _
SGA _

21

22

23

24

25

26

27

28 29

2/\

211

2C

20

2E

2F

7·SEGMENT
CHARACTEns

10

•• PNT and TAil bOlh ,.1
••• PNT only ,u

SPECIAL
IlAnGnAPIf
CODES

30 31

\0

32

33 34
3.'4

35

36

37

56

7

SGP _
SGO _
SGN_
SGM_
SGl ~
SGK _
SGJ _
SGI _
SGH_
SGG _
SGF _
SGe _
SGO _
SGC _
SGB _
SGA --'-

36 39 J/\ 3B
8

9

A

3C

30

3E

CD

E

3F

FI

7·SEGMENT
CHARACTEnS

SPECIAL
BAnGnAPH
CODES

Table-3

PLA Code (At the time of bar display)

247

*

To set the comma and point, the display data at the display digit is input, then 2C and 2E
data are input.
(Note) Only when 2C and 2E data are entered, the write address in the RAM is not
automatically incremented .. For other data, the address specified by the Buffer
Pointer Control command is automatically incremented by one each time the
display dadta is input.

APPLICATION CIRCUIT

O'--------~------------~--------------------~
+5V

10pf

DATA

Voo

CLOCKA
HOST
SYSTEM

MSC1937·01
~--~-----~----------~ GND

ADX

SGX

POR

Rc

- VoisP

Information furnished by OKI is believed to be accurate and
reliable. However, no responsibility is assumed by OKI for its use;
nor for any infringements of patents or other rights of third
parties which ·may result from its use. No license is granted by
implication or otherwise under any patent rights of OKI.

248

OKI semiconductor
MSC712S-XX
5 x 7 DOT MATRIX, 8-DIGIT

GENERAL DESCRIPTION
The MSC7125-XX is a BiCMOS dot matrix display controller for vacuum fluorescent display tube ..
The MSC7125-XX drives displays with up to 8 grids with 35 anodes (dots) plus 5 annunciators. The
controller receives the serial data (command and display data) consisted of 2 bytes (16 bits) on the
high to low transition of the clock. The serial data entered ·into 16-bit shift register via DATA IN
terminal is automatically latched after.2 bytes data input is completed. Commands control the
on/off duty, starting char~cter position, number of characters to display. An internal PLA-type
character generator provides character decoding and dot pattern generation for 128 types of
characters.

FEATURES
•

Operating temperature

•

Logic supply voltage (Voo)

+ SV

•

Display voltage

+ 50V max

•

Driver output current

± 10%

-31 rnA (GRID 1,8)
-16 mA (GRID 2-7)
-4.5 rnA (SEG 36-40)
-0.3 mA (SEG 1-35)
203KHz max

•

Data transfer speed

•

Built-in oscillation circuit'

•

Built-in Power-on-reset circuit with external C

•

Serial data input for 2 bytes (16 bits) control and display data

•

Command functions

on/off duty cycle (1024 steps)
starting character position (1 to 8)
number of characters (1 to 8)

•

Built-in PLA-type character generator

•

60 pin flat package

128 types of characters (user programmable)

249

N

U1

0:1

o

. r-

on

f·--·_·_·_·'_·_·_·_·_·_·_·_··-·_·_·_·_·_·_·_·_·_·_·_·-.-._.-.-.-.-._._.-._._.-.-.-.-._._.-._._.-._._._._._.-.-._.-._._._.-._._._.,
RAM

cr----r--'\

LATCH

PLA

LATCH

~~~

"C

i
:
SEGl
SEG2

l

SEG34

CS

SEG3S
SEG36
SEG40

OSCO~

DECODER

DIGIT
DRV
GRIDl
GRID2

TEsn

TEST2

VDD

R

rr

CE
DIGIT
COUNT

G!

DUTY AND
BLANK
GENERATOR

I

L..._._._._._._

A

B

ADDRESS
COMP

GND

;i
iT

A=B

"..._._._._._._._._.

_._._._._._._._.-

._._._._._._._._._._._._._._._._._._._._._._.~
BLANK

DUTY AND BLANK

GRID3
GRI04
GRIDS
GRID6
GRID7
GRIDB

l>
~

:0

l>

S

PIN CONFIGURATION
46

45 44

43 42

41

40

39 38

37 36

35 34

33 32

31

47

30

48

29

49

28
27

50
51

TOP VIEW

26

52

60 PIN FLAT PACKAGE

25

53

24

54

23

55

22

56

21

57

20

58

19

59

18

60

17

O.
2

3

4·

5

6

7

8

9

10 11

12 13

14 15

16

1

VOISP

16

SEG34

31

SEG18

46

2

SEG31

17

GRID4

32

SEG17

47

SEG4
SEG9

3

GRID6

18

GRID3

33

SEG16

48

SEG10

4

GRIDS

19

SEG35

34

SEG15

49

SEG36

5

SEG26

20

SEG40

35

SEG14

50

SEG37

6

SEG32

21

SEG25

36

SEG13

51

POR

7

SEG39

22

CRID2

37

SEG12

52

Voo

8

SEG33

23

GND

38

SEG11

53

OSC1
OSCO

9

SEG38

24

SEG24

39

SEG1

54

10

SEG27

25

GRID1

40

SEG2

55

GND

11

GRID8

26

SEG23

41

SEG5

56

TEST1

12

SEG28

27

SEG22

42

SEG6

57

DATA IN

13

GRID7

28

SEG21

43

SEG7

58

SCLK

14

SEG29

29

SEG20

44

SEG8

59

CS

15

SEG30

30

SEG19

45

SEG3

60

TEST2

251

PIN DESCRIPTION

252

PIN#

PIN NAME

DESCRIPTION

PIN#

PIN NAME

DESCRIPTION

1

VDISP

DISPLAY VOLTAGE

31

SEG18

ANODE18 DRIVER OUTPUT

2

SEG31

ANODE31 DRIVER OUTPUT

32

SEG17

ANODE17 DRIVER OUTPUT

3

GRID6

GRID6 DRIVER OUTPUT

33

SEG16

ANODE16 DRIVER OUTPUT

4

GRIDS

GRIDS DRIVER OUTPUT

34

SEG15

ANODE15 DRIVER OUTPUT

5

SEG26

ANODE26 DRIVER OUTPUT

35

SEG14

ANODE14 DRIVER OUTPUT

6

SEG32

ANODE32 DRIVER OUTPUT

36

SEG13

ANODE13 DRIVER OUTPUT

7

SEG39

ANODE39 DRIVER OUTPUT

37

SEG12

ANODE12 DRIVER OUTPUT

8

SEG33

ANODE33 DRIVER OUTPUT

38

SEG11

ANODE11 DRIVER OUTPUT

9

SEG38

ANODE38 DElVER OUTPUT

39

SEG1

ANODE1 DRIVER OUTPUT

10

SEG27

ANODE27 DRIVER OUTPUT

40

SEG2

ANODE2 DRIVER OUTPUT

11

GRID8

GRID8 DElVER OUTPUT

41

SEG5

ANODES DRIVER OUTPUT

12

SEG28

ANODE28 DRIVER OUTPUT

42

SEG6

ANODE6 DRIVER OUTPUT

13

GRID7

GRID7 DRIVER OUTPUT

43

SEG7

ANODE7 DRIVER OUTPUT

14

SEG29

ANODE29 DRIVER OUTPUT

44

SEG8

ANODE8 DRIVER OUTPUT

15

SEG30

ANODE28 DRIVER OUTPUT

4S

SEG3

ANODI;3 DRIVER OUTPUT

16

SEG34

ANODE34 DRIVER OUTPUT

46

SEG4

ANODE4 DRIVER OUTPUT

16

GRID4

GRID4 DRIVER OUTPUT

47

SEG9

ANODE9 DRIVER OUTPUT

18

GRID3

GRID3 DRIVER OUTPUT

48

SEG10

ANODE10 DRIVER OUTPUT

19

SEG35

ANODE3S DRIVER OUTPUT

49

SEG36

ANODE36 DRIVER OUTPUT

20

SEG40

ANODE40 DRIVER OUTPUT

50

SEG37

ANODE37 DRIVER OUTPUT

21

SEG25

ANODE2S DRIVER OUTPUT

51

POR

POWER-ON-RESET INPUT

22

GRID2

GRID2 DRIVER OUTPUT

52

VDD

LOGIC VOLTAGE

23

GND

POWER & SIGNAL REFERENCE

53

OSC1

RC OSCILLATION

24

SEG24

ANODE24 DRIVER OUTPUT

54

OSCO

RC OSCILLATION

25

GRID1

GRID1 DRIVER OUTPUT

5S

GND

POWER & SIGNAL REFERENCE

26

SEG23

ANODE23 DRIVER OUTPUT

56

TEST1

TEST SIGNAL INPUT

27

SEG22

ANODE22 DRIVER OUTPUT

57

DATA IN

SERIAL DATA INPUT

28

SEG21

ANODE21 DRIVER OUTPUT

58

SCLK

SHIFT CLOCK INPUT

29

SEG20

ANODE20 DRIVER'OUTPUT

S9

CS

CHIP SELECT INPUT

30

SEG19

ANODE19 DRIVER OUTPUT

60

TEST2

TEST SIGNAL INPUT

ELECTRICAL CHARACTERISTICS
(I

Absolute Maximum Ratings
Parameter

•

Symbol

Rating

Unit

Power supply voltage

Voo

- 0.3-6.5

V

Disp~ay voltage

VOISP

-0.3-52

V

Input voltage

VIN

- 0.3-Voo + 0.3

V

Operating temperature range

Top

-40-85

°C

Storage temperature range

Tstg

- 65-150

°C

Operating Condition
Parameter

Symbol

Condition

MIN

TYPE

MAX

Unit

Power supply voltage

Voo

4.5

5.5

V

Display voltage

VOISP

Voo+2

50

V

High level input voltage

VIH

3.6

VOD

V

Low level input voltage

VIL

0

0.8

V

500

KHz

4

MHz

Clock Frequency
OSC Frequency

fc
fosc

75pf, 4.7KQ

1

2

253

•

DC Characteristics

sv

Ta = - 40- + 85°C, Voo =
± 10% unless otherwise noted.
All voltages are referenced to GND.
.
Parameter

Symbol

Condition

MIN

MAX

Unit

3.6

-

V

4.2

-

V

High level input voltage
(All inputs except OSCO)

VIHl

High level input voltage
(OSCO)

VIH2

Low level input voltage
(All input except OSCO)

VILl

-

0.8

V

Low level input voltage
(OSCO)

VIL2

-

0.5

V

High level input c,!!:!eDl(SCLK, DATA IN, C5, POR)

IIHl

VIHl =V oo

-5

5

}lA

High level input current
(TEST1; TEST2)

IIH2

VIH2=VOO

250

900

pA

High level input current
(OSCO)

IIH3

VIH3 = Voo

-10

10

pA

Low level input current
(SCLK, DATA IN, C5,
TEST1, TE5T2)

IILl

VILl =OV

-5

5

pA

Low level input current
(POR)

IIL2

VIL2= OV

-27

- 110

}lA

Low level input current
(OS CO)

IIL3

V 1L3 = OV

-10

10

llA

. High level output voltage
(SEG1-35)

VO Hl

IOHl = - 0.3mA-

V ol sp-2.0

-

V

High leve} output voltage
(SEG36-40)

VOH2

IO·H2 = - 4.SmA

Vo lsp-2.0

-

V·

High level output voltage
(GRID1, GRID8)

VOH3

IOH3= -31mA

VOls~-2.7

-

V

High level output voltage
(GRID2-7)

VO H4

IOH4= -16mA

VOlsp-2.7

-

V

Low level output voltage
(SEG1-40, GRID1-8)

VOLl

lOll = 10UA

-

254

Logic supply current

100

Display supply current

IOlsP

,

.

1

V

. fosc = 2.0MHz, No. load

15

mA

No load

10

mA

o AC Characteristics

=

Ta = - 40- + 85°C, Voo sv ± 10% unless otherwise noted.
All voltages are referenced to GND.
Parameter
SCLK cycle time
SCLI( clock pulse width

MIN

MAX

Unit

teyese

-

2

lIS

twse

1

-

lIS

Symbol

Condition

tos

0.5

Data hold time

tOH

0.5

CS set-up time

tess

1

CS hold time

tesH

OSC frequency

fosc

Data set-up time

R=4.7KQ,. C =7spf

lIS
lIS
. lIS

1

-

1

4

MHz

lIS

o Timing Chart

255

•

Data Word LSB/MSB Timing

SCLK

•

DATA INPUT OFF TIME tOOFF

32pSEC min.

DATA INPUT CYCLE toCYC

64pSEC min.

Power-on-Reset Timing

VOO

tpORON

tp R FF

paR

DATA VALID

DATA
OPTION 1
paR signal is generated by RC circuit.
paR ON TIME

tpORON

paR OFF TIME

tpOROFF

*

External 1pF Cap.

250mSEC type
50pSEC min.

Built-in 1OOKO pull-up resistor.

OPTION 2
paR signal is generated by peripheral circuit or host computer.
.

256

paR ON TIME

tpORON

50pSEC min.

paR OFF TIME

tpOROFF

50pSEC ";lin.

FUNCTIONAL DESCRIPTION
The data input of MSC 7125-XX consists of 2 byte (16 bits) serial data but the 3 bits (bit 15, 14, 13)
from MSB are taken as null data. This is because a number of data bis required for MSC 712S-XX is
13 bits but 2 bytes construction is used for easy interface with CPU. When the 16-bit data input has
been completed, MSC 7125-XX generates the load signal automatically and begins execution.
The value of bit 12 of 16-bit serial data determines whether the input data is control data or
display data.

•

Control Data
When bit 12 is "1", input data is recognized as control data. A type of command and the
associated data with the command are extracted from bit 11-0;
TABLE-1

Control data table

16-Bit Serial Input Wor~s
MSB
15 14

13

12

11

10

9

8

7

6

5

.4

3

2

1

X

X

1

0

0

X

X

X

X

X

X

X

22

2'

X

Function

LSB

0
2°

LOAD BUFFER
POINTER
(Position of character
to be changed)

X

X

X

1

0

1

X

X

X

X

X

X

X

22

2'

2°

LOAD DIGIT
COUNTER
(Number of
characters to be
displayed)

X

X' X

1

1

0

29

28

27

26

25

24

23

22

2'

2°

LOAD DUTY CYCLE
(On/off and dimming
control)

X

X

X

1

1

1

X

X

X

X

X

X

X

X

X

X

ENTER TEST MODE
(Not a userfunction)

Note:
a)

X means this bit is "don't care" bit.

Load buffer pointer
This command is used to modify individual characters by setting buffer pointer to any digit
position. (RAM write address is set)
A decimal equivalent value of bits 0-2 sho"uld be (the desired digit number-2).
(Example) In case of GRID 4, the setting value is 2 (010).
TABLE -2

Buffer Pointer Value (lower 3 bits)
C;haracter Controlled By

b)

Load buffer pointer codes
7

0

1

2

3

4

5

6

GRID 1 GRID2 GRID3 GRID4 GRIDS GRID6 GRID7 GRID8

Load digit counter
This command sets the number of display digits.
257

Set the desired digit number in bits 0-2. .
TABLE-3

Digit counter control codes

Digit Counter Value (lower 3 bits)

0

1

2

3

4

5

6

7

Number of Digits

8

1

2

3

4

5

6

7

c)

Load duty cycle
This command sets the duty cycle of driver output. With this command, 1024 step
adjustments of brightness can be done. As shown in Fig.-1, the.blank time between the
GRIDS is 32 bit times, and between the segments, 20 bit times on the hardware, hence the
setting range is 0 - 992.

~----------

GRID1

1 DISPLAY CYCLE
8192 bit times

32 bit times min

GRID2 - f - - - + - '
GRID3

-+_-_i_----J

GRID4

-+_-_i_---------'

GRID5~+---i-----------------~

GRID6-+----+-------------------------~

GRID7-+----+--------------------------------~

GRID8--+--~-----------------------~-------~

J
1004 bittimes

NOTES:
1. TIMING SHOWN IS FOR 8 CHARACTERS WITH DUTY CYCLE OF 992
2. THE DUTY CYCLE CODE CAN MODIFY THE DIGIT ON-TIME FROM OTO 992
BIT TIMES.
3. 1 BIT TIME = Tosc (= 1/fosc) = 0.5pS typical
Fig-1
258

Display timing chart

d)

Enter test mode
This mode is used for outgoing inspection and is not a user function.

o Display Data
Display data can be input by setting bit 12
bits 11 - 7 and PLA address from bits 6 -

=

"0". 5 bits annunciator data are extracted from

o.

Table 4

Display data

16-Bit Serial Input Words
MSB
15 14

X

X

13

12

11

10

9

8

7

6

5

4

3

2

1

X

O. 2"

2'0

29

28

27

26

25

24

23

22

2'

LSB
0

Function

LOAD DISPLAY
DATA
20 (Annunciator 5 bits
and pia 7 bits)

PLA Code is User Programmable.
The relation between the dots of vacuum fluorescent display tube and Segment output of MSC
7125-XX is as shown in Fig-2.

G[J []J ~ ~ ~
G;J ~ G;J. G;] ~
SEG1

SEG2

SEG3

SEG6

SEG7

SEG8

~
~
~
~

~
~
~
~
G;J ~
SEG11

SEG12

SEG16

SEG17 .

SEG21

SEG22

SEG26

SEG27

SEG31

SEG32

Fig-2

~
~
~
~
~
SEG13

SEG18

SEG23

SEG28

SEG33

.

SEG4

SEG5

SEG9

SEG10

~
~
~
~

~
~

SEG14

SEG19

SEG24

SEG15

SEG20

Q;J
SEG25

~
G;J ~
SEG29

SEG30

SEG34

SEG35

Dot-Segment output assignment

259

•

Power-On-Reset (POR)
The Power -On-Reset initializes the internal circuits when power is applied.
The following condition is established after Power-an-Reset.
a. The segment drivers are in the" L" state.
b. The grid drivers are in the
c.

~'L"

state.

The duty cycle is set to "0".

d. The digit counter is set to "8".
e. The buffer pointer points to the character controlled by GRID1.

260

APPLICATION NOTE
a) Application circuit

,~

_~l

""ANODE

VF DISPLAY

ANODE

(ANNUNCIATOR)

~GRID

K-

R1

~

ii:' ZD( =Ek)

I

.OOJOOII

7/[

~1

~
~

Ef

.1

I

I
Voo

-.!.3i ~_-:-"1 Z~
+

+5V

MCU

-r-

Voo

GRIDl-8

VOISP

SEG36-40 r - -

~

DATA IN

~

SCLK

MSC712S-XX
SEGl-35

G~D

GND (5 POR OSC1 OSCO

"1

z:-

I

R

J
-LC

I

T

7tl
b) Data set up flow

I
I

POWER 'ON
I

DIGIT COUNTER SET
I

I

DUTY CYCLE SET
(DIMMING)

I

BUFFER POINTER SET

I

DISPLAY DATA SET

I

I

I
I

T

INITIALIZATION
ROUTINE

I ~
I

I

Information furnished by OKI is believed to be accurate and
reliable. However, no responsibility is assumed by OKI for its use;
nor for any infringements of patents or other rights of third
parties which mJY result from its use. No license is granted by
implication or otherwise under any patent rights of OKI.

261

OKI semiconductor
MSC7128-XX
.5 x ~ DOT MATRIX, 16-DIGIT
GENERAL DESCRIPTION
The MSC7128-XX is a general purpose display controllers for vacuum. fluorescent display tube.
The Msci128-XX drives displays with up to 35 anodes (dots) and up to 16 grids (characters) plus a
cursor.
The controller accepts command and qisplay data input words on a clocked serial input line.
Commands control the on/off duty cycle, starting character position, number of characters to
display and display modes (PLA mode and Lamp Test mode).

An internal PLA-type character

generator provides character decoding and dot pattern generation for the full 128 characters.
No external drive circuit is required for displays that operate on 30mA of drive current up to 45
volts.
A 35x128-bit PLA (ROM) code is programmable.

FEATURES

•
•
•

Logic supply voltage (VD D)

+ 5V

VF driver supply voltage (VEE)

- 55V

Driver output current
VF grid driver

(source)

VF anode driver

(source)

-2mA

VF cursor driver

(source)

-10mA

-30mA

•

Direct drive capability for vacuum fluorescent display

•

Built-in oscillation circuit

•

Built-in power-on-reset circuit with external C

•

Serial host interface (data in, clock, chip select)

•

Serial data input for 8-bit control and display data words

•

Command functions
On/off duty cycle
Starting character position

•

1 to 16

Choice of 2-display ~odes

PLA mode, and Lamp Test mode

Built-in 35x128-bit PLA-type character generator
Character font
5x7
Numberofcharacters

:

Programmable PLA code
•
262

1 to 16

Number of characters

64 Pin shrink DIP package

128

OJ
i·-"fl·~·-·-·-·-·-·-·-·-·­

VOO

r-

on

._._._._._._._._ .. _._._ .

._._._._._._._._._._._0_._._._._._._._"-

A

SEG
DRIVER

o-L-

C

:;
Gl

::0

»

~

COMI
COM2

COM14
COMIS

TEST
STEP
TEST
COUNT

r-r

.COM16

h
I

Vss

--r--o
= ,

n;

BLANK

I
I

DUTY AND BLANK

i
i

,
!
!

'-.

'"enw

i
i
i

!I
i
i

RESET

i

_._._._._._ . .i

VEE

PIN CONFIGURATION
(Top View) 64 Lead Shrink Duallnline Package
·OSCO

CS

OSCI

DA

TEST COUNT

CP

TEST STEP

4

1

RESET

VSS

VDD1

VEE

VDDi

COM 1

SEG 1

COM 2

SEG 2

COM 3

SEG 3

COM 4

SEG 4

COM 5

SEG 5

COM 6

SEG 6

COM 7

SEG 7

COM 8

SEG 8

COM 9

SEG 9

COM 10

SEG 10

COM· 11

SEG 11

COM 12

SEG 12

COM 13

SEG 13

COM 14

SEG 14

COM 15
COM 16

SEG 16

SEG 36
SEG 35

SEG 17
1

SEG 18

SEG

SEG 19

SEG 33

SEG 20

SEG 32

SEG 21

SEG 31

SEG 22

SEG 30

SEG 23

SEG

SEG 24

SEG 28
SEG 27

264

SEG 26

PIN DESCRIPTION
Pin Name

Pin No.

Input, Output

Connected to

Function
V001 - Vss: Inner logic supply
voltage

VOO1

60

VOO2

59

Vss

5

VEe

6

DA

63

Input

M i crocom puter

Serial data input from LSS
(positive logic)

CP

63

Input

M i crocom puter

Shift clock input. Data is
shifW at the leading edge of
the CPo

es

64

Input

M icrocom puter

Chip select input. When the pin
is High, the serial data transfer
is inhibited.

Power source

V002 - VE"E: VF tube driving
circuit supply
voltage

CR oscillation, "external CR pin.
fosc =. 250KHz at C = 109pF and
R=47K

OSCI

2

Input

OS CO

1

Output

RESET

61

Input

COM 1

7

Output

S

S

VF tube grid
electrode

COM16

22

SEG 1

58

Output

s

S

VF tube anode
electrode

SEG35

24

VF tube 5x7-dot anode
electrode driving output. This
pin can be connected directly to
the VF tube. No pull-down
resistor is required. IOH>-2mA

SEG 36

23

Output

VF tube anode
electrode

VF tube cursor anode electrode
driving output. This pin can be
connected directly to the VF
tube. No pull-down resistor is
required. IOH>-10mA

TEST STEP

4

Input

Test mode setting input
{normally open)

TEST
COUNT

4

Input

Test clock input (normally
open)

Reset input (pull-up resistor
built in). When the pin is Low,
the internal logic is reset, and
the outputs of SSG 1 to SBG36
and COM1 to COM16 are Low.
VF tube grid electrode driving
output. This pin can be
connected directly to the VF
tube. No pull-down resistor is
required. IOH >-30mA

265

ELECTRICAL CHARACTERISTICS
•

Absolute Maximum Ratings
Parameter

Symbol

Power supply voltage (1)

Condition

Rating

Unit

Voo- Vss

- 0.3- +6.5

V

Power s~pply voltage (2)

Voo - VEE

0- +65

V

Input voltage

VIH - Vss

- 0.3-Voo + 0.3

V

-1.0

W

'- 55- + 150

°C

Power dissip~tion

Pd

Storage temperature

Tstg

. Output current

•

Ta;::;; 25°C

101

COM1- COM16

-40mA

mA

102

SEG1 - SEG35

-40mA

mA

103

SEG 36

-40mA

mA

Recommended Operating Condition
Symbol

Parameter
Power supply voltage

(1 )

Power supply voltage

(2)

High level input voltage
low level input voltage
CP Frequency

MAX

Unit

Voo - Vss

4.5

5.5

V

Voo - VEE

10

60

V

MIN

TYPE

0. 7V oo

V 1H - Vss '

V

. V1L - Vss
~

fcp

OSC Frequency

fosc

Operating temperature

Top

266

Condition

100pF, 47KQ

170
-20

220

0. 3V OD

V

500

KHz

270

KHz

+ 75

°C

o DC Characteristics
o

VOO-VSS=SV±10%, Voo-VEe=60V,Ta= -20-+7S C
Parameter

Condition

Symbol

High level input voltage

VIH

Low level input voltage

VIL

MIN

MAX

0. 7V oo

Unit
V

0. 3V oo

V

IIH,

DA, CP, CS
RESET, POR

Voo = 5.SV
VIN = SV

-5

5

pA

IIH2 ..

TEST STEP
TEST COUNT

Voo = S.SV
VIN = SV

0.25

1

mA

11L1

DA, CP, CS POR
TEST STEP
Voo = 5.SV
TEST COUNT
V IH = O.SV

-5

5

'llA

- 25

- 100

pA

High level input current

Low level input current
IIL2

RESET

Voo = S.SV
VIH = O.SV

VOH'

OSCO

IOH = - 500pA

Voo- 0.6

V

VOH2

COMl-16

IOH = - 30mA

Voo-4

V

VOH3

SEGl-3S

IOH = - 2rT1A

Voo- 3

V

VOH4

SEG36

IOH= -10mA

Voo-4

V

High level output voltage

Vss + 0.6

V

IOL= 100pA

VeE + 3

V

1m = 100pA

VeE + 3

V

VEE + 3

V

VOL1

OSCO

VOL2

COMl-16

VOL3

SEGl-3S

VOL4

SEG36

Im= 100pA

1m = 500pA

Low level output voltage

Iss,

All SEGs on, 16-digit display,
duty cycle 15/16, no load

15

mA

1552

All S.EG s Low, all COMs High

1.5

mA

lEE'

All SEG son, 16-digit display,
duty cycle 15/16, no load

1.0

mA

.IEE2

All ~EGs Low, all COMs High

15

mA

Supply current

267

'.

AC Characteristics
VOO- vss
Parameter

Symbol

=5V ± 10%, Ta =- 20;'" + 75°C

Condition

Unit

2

pS
pS

32T*

-

170

270

KHz

tcp

-

CP pulse width

t WCF

1

Data set-up time

tos

0.5

Data hold time

tOH

0.5

CS set-up time

tess

OSC frequency

"

1

tCSH
fosc

=

R 47KQ, C =100pF
*T

Data Timing Chart

CS

CP

DA

268

MAX

CP cycle time

CS hold time

•

MIN

= 1/fosc

pS
pS
pS
S

•

Data Word LSB/MSB Timing
r\:Xi
DAiA WORD

CP

DATA INPUT OFF TIME tDOFF

II

32T min

T = l/fosc

Reset Timing

VDD

~~ t_R_:S_E_i_O_~ ~
__

__

t~R~:S~;~-~O~:._- ~

_____

__

r----.

RESET

D~,;"A V~L:D

V

-l-

I

DA

OPTION 1
A capacitor is connected between the RESET pin and
RESET ON TIME
RESET OFF TIME
External capacitor:

Vss.

2S0mSEC type
tR~SETOFF

SOpSEC min.

1F

Built-in 100Kr.! pull-up resistor.
OPTION 2
A RESET si,gnal is externally input.
RESET ON TIME
RESET OFF TIME

tRESET ON

SOpSEC min.
SOpSEC min.

269

FUNCTIONAL DE,SCRIPTION
•

Data Transfer Method And Command Write Method
A display control command or data is written by the 8·bit serial transfer method. The figure
below shows the write timing chart. When the CS pin is Low, data can be transferred. Data 8
bits in length is input to the DA pin sequentially starting with the LSB. (LSB first)
, Data is shifted at the rising edge of a shift clock pulse which is input to the CP pin as shown in
the figure below. When data 8 bits in length is entered, an inner LOAD signal is automatically
generated, and data is written into the registers and RAM. Accordingly, there is no need to
input an external LOAD signal.
If t~e CS pin is changed from Low to High, the serial transfer is inhibited, and data, which is
entered after the CS pin is changed from High to Low, is recognized in units of 8 bits.

CS

~~______________________________________

DA
LSB

270

MSB

LSB

MSB

o

Command Type

First byte
No.

Second byte

Command
b7' b6

bS

b4

b3

b2

b1

bO

b7

b6

bS

b4

b3

b2

b1

bO

X

X

X

X

X3

X2

X,

Xo

0

Address Set

1

0

0

0

X

X

X

X

1

Character Code
Set

1

0

0

1

X,

X

X

X

2

Display Duty Set

1

0

1

0

X

X

X

X

X

X

X

X

DC3 DC2 DC, DCo

3

Number of Display
Digits Set

1

0

1

1

X

X

X

X

X

X

X

X

DG3 DG2 DG, DGo

4

Lamp Test

1

1

0

0

X

X

X

X

X

X

X

X

CU CH6 CHs CH4 CH3 CH2 CH, CHo

X

X

X

LT

*1 When character codes are to be continuously transferred, addresses are automatically
incremented (internally). Accordingly, neither the Address Set command nor the first
byte of the Character Code Set command are required to set the second and following
character codes.
*2 X: Don't care

271

•

Address Set Command
When the code pf a display character is to be set, this command is used to specify the display
location (digit number) of the character.
The relation between the digit number X and common outputs COM 1 to COM 16 is as follows:

X

COM input,

0

COM1

1

COM2

15

COM16

Command format
LSB

0

0

0

X

X

1st byte

X

X

LSB

X

X

X

X

X3

X,

X2

I

XO

, _------- --------,
....

\

I

V
I

Digit number X (0 to 15)

272

I,

2nd byte

•

Character Code Set Command
This command is used t,o specify the character to be displayed in t~e digit place specified by the
Address Set command. Bits 0 to 6 of the second byte are used to specify the character code,
H

and bit 7 is used to specify "Yes or "NoH of cursor display.

Command format

LSB

o

o

x

x

x

x

1st byte

LSB
CU

1 CH6H 1 CHs

.....

1 CH4

1 CH3

----------------- ..... ,

/

1 CH2

1 CH,

1 CHo 'I

2nd byte

------.-----------'

\'
7-bit character code
Select one of 128 codes

0:

Without cursor (SEG36 OFF)

1:

With cursor

(SEG36 ON)

An automatic address increment function is built in. to write multidigit di'splay character
codes, just issue the Address Set command. To transfer the second and following digit display
character codes, the first byte (operation code) of the Character Code command is not
required. Just input the second byte.
When this command is executed, 8-bit data after the second byte, which is provided before
the CS pin is turned High, is all treated as display character data.

Transfer examples of the Address Set command and the Character Set
command
CS

DATA
Address Set command

Character Set command

273

The display for COM3 and the following is changed.

Example 1:

LSB

0

0

0

X

X

X

X

' } Specify ttie digit
numberX
(COM3)

LSB
X

X

X

0

O·

X

0

0

01

X

X

X

0

=2

I

LSB
X

LSB

I

CU

CH6

CHs

CH4

CH3

CH2

CH,

CHo

CU

CH6

CHs

CH4

CH3

CH2

CH,

CHo

Write the character
code to be displayed
on COM4

CU

CH6

CHs

. CH 4

CH3

CH2

CH,

CHo

Write the character
code to be displayed
onCOMS

X

274

'}

. Write the first
character code

=1S (COM16) is followed by X =0 (COM1)

o

Number of Display Digits Set command
This command is used to set the digit count register and the number of display digits. The
number of digits to be set ranges from 1 to 16.

Command format
lSB

x

o

x

x

x
lSB

x

x

x

DGzl DG,

DGo-

,---------- \1 ---------I

Number of digits DG (0 to 15)

The relation between the value for DG to be set and COM under display control is as
follows:

DG

COM displayed

DG

COM displayed

0

COM,- COM'6

8

COM, - CaMs

1

COM,

9

COM, - COM9

2

COM, - COM2.

10

COM, - COMlO

3

COM, - COM3

11

COM,-COM"

4

COM, - COM 4

12

COM,- COM,z

5

COM, - CaMs

13

COM, - COM13

6

COM,- COM6

14

COM,- COM'4

7

COM, --COM7

15

COM, - COM'5

275

•

Display Duty Set command
Assuming the original oscillation cycle as T, the time allocated to 1-digit display i~ 64 T. The
actual display time may be specified as 0 to 60 T in increments of 4T. Assuming the number of
display digits as n and the parameter provided by the Display Duty Set command as DC, the
resultant display duty cycle ratio is as follows:

4 (DC)

(DC)

64n

16n

Command format
LSB

o

o

x.

x

x

x

x

I

x

x

x
LSB

DC3

DC2

DCo

DC,

,__________

I

_ _________ 1

\I
I

DC value (0 ~o 15)

•

Lamp Test command
This command is used to set the All-Segment D,isplay mode. If this occurs, the 36 segments for
each digit to be displayed are put into the ON state. The number of display digits and the
display duty cycle depend on the contents of the digit count register and of the duty register.
The contents of the internal RAM are not affected by this command. When the command is
released, the original display appears once again.
Command format
LSB

o

o

x

x

x

x

x

x

x

x

x
LSB

x

x

Normal mode
Lamp test
mode

276

c

Gi

=i
:j
t, = 64x 16 = 1024T

I .
COM1
COM2

S

I (""vee

n

~t2
~T~t3
~rlL_

2:

~

VEE ,

______
__________________________________________________ rIL-__________ _____________________________________________________
____________
________________________________________________
________________
________________________________________________
______________
_____________________________ ___

n

~,

::I:

l>

~Il~

COM3

~

-

~rl~

COM4·

~

~rl~

COMS

~Il~

COM6

________________

COM7
COMB
COM9
COM10
COM11

~n~

n

n n

------------------------------------~

______________________________

t3 =Blanktiming
1

~rl

T=~

fosc =24S KHz

n
n

COM13

------------------------------------~------~

COM14

-----------------------------------------~

n

t1 = 4.096ms
t2=240J1S

. rl

t3 =16 ps

COM1S

n=1to36
SEGn

,
N·

""

;:;:

=Frame count

t2 = Display timing.

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - I

51

~"

t1

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-..I

COM16

I

a.

___________________________

_ _ _ _ _ _ _ _ _......:;.._ _ _ _ _ _ _---I

COM12

0\

~

n~

______

~ ___________________________________________________ ~V~~

.

a.

iii"

"'C

Q.J

'<

POWER ON RESET OPERATION
Operations when the RESET pin is Low are as follows:
a.

All segment driver outputs are Low.

b.

All grid driver outputs are Low.

c.

The number ofdisplay digits is set to 16.

d. The display duty cycle is set to O.

TEST STEP AND TEST COUNT
These pins are used for inspection before shipment, and should not be used by the user.
When an Ie is mounted, leave them open or connect to Vss. If they are connected to other pins, a
malfunction may be caused .. '

278

,

RELATION BETWEEN SEGMENT OUTPUT AND VF TUBE DOTS

G;] ~
~ G;J
~~
~~
~ GlJJ
~~
~~
SEGl

SEG2

SEG6

SEG7

SEG11

SEG12

SEG16

SEG17

SEG21

SEG22

SEG26

SEG27

SEG31

SEG32

~ ~ G;J
G;J @J ~
~ ~ QJJ
~§ ~
~ §J ~
~~~
~ ~ G;J
SEG3

SEG4

SEGS

SEG8

SEG9

SEG10

SEG13

SEG14

SEG1S

SEG18

SEG19

SEG20

SEG23

SEG24

SEG25

SEG28

SEG29

SEG30

SEG33

SEG34

SEG35

Cursor

SEG36

279

APPLICATION NOTE
Heater transformer
VF DISPLAY

s-

A E
N G
o M
D E

E N
T

GRID (DIGIT)

Voo SEG1-SEG36

o

pU
o t
r P
t U
t

+5V

+
GND

DA

COM1-COM16

t'

MSC7128-XX

CP
CS

v

TEST
SETP

Rl
60V

+

ZD

Information furnished by OKI is believed to be accurate and
reliable; However, no responsibility is assumed by OKI for its use;
nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted 'by
implication or otherwise under any patent rights of OKI.

280

Level
Meter

OKI semiconductor
MSC1124
2-CHANNEL 12-DOT LEVEL METER IC (STATIC)

GENERAL DESCRIPTION
The MSC1124 is a static FLT driving audio 2-channellevel meter, which can be used for high fidelity
VTRs and audio equipment.

FEATURES
o

Direct in put of audio (analogue) signals

o

Log compression circuit built in (-20 dB to 8 dB, 12 dots)

o

High withstand voltage output, output voltage 35 V, supply voltage 36.5 V

o

Peak hold function built in, automatic and manual reset

•

Power ON reset circuit built in

o

2-power-source (GND shared) system

•

40-pin plastic DIP, 44-pin V plastic QFP

283

N

~

BLOCK DIAGRAM

VOOHu.
VOOo-.

R12

'V

l12

R11

l11

R2

L2

R1

GNDH~GNDH

GND~

L1

Peak hold reset (About 1 second. OSC: 10KHz)

PIN CONFIGURATION
MSCl124
(Top View) 40 Lead Plastic DIP

POR

OSC
TEST
M.MODE
A.MODE
RS

NC .

R4
R3

R2
R1

R7

GND

RB

GNDH

R9

L12

R10

L11

R11

L10

R12

L9

L7

LB

(This specification may be changed without notice.)

285

PIN CONFIGURATION
MSCl124
(Top View) 44 Lead Plastic Flat Package

0

TEST
OSC
POR

L12
L11
L10

V REF

L9
L8

Voo

GND

GND
L6

L7

LS

NC

L4

R12

L3
L2

@
L1

R6 RS

R11
R10

R4 R3

R2 R1 VooH R7

R8

R9

NOTE:

(This specification may be changed without notice.)

286

ELECTRICAL CHARACTERISTICS
•

Absolute Maximum Ratings
Parameter

Conditions

Rated value

Unit

Terminal

Supply voltage 1

Voo

Ta

=25°C

-0.2 .... 7.0

V

Voo, VREF

~upply volt~e 2
Between V
and
VEE)

VOOH

Ta

=25°C

- 0.2 .... 40

V

VOOH

Vl1

Ta

=25°C

- 0.2 .... VDD + 0.2

V

Except Rin
and Lin

II

Ta

=25°C VI =- 1.0V

10max

mA

=

-10max

mA

=

3max

mA

Input voltage

Input reverse current
Output current

101

Ta 25°C, source
current

Output current

102

Ta 25°C, sink
current

Input voltage

VI2

Ta

=25°C

- 0.7 .... VDD + 0.2

Allowable loss

Po

Ta

=25°C

650

Storage temperature

•

Symbol

Tstg

-

- 50 .... 125

V

All input pi ns

R1 .... R12
L1 .... L12

Rin, Lin

mW

°C ,

Operating Condition
Parameter

Conditions

Supply voltage 1

Voo

-

4.5 .... 5.5

V

Voo

Supply voltage 2

VOOH

-

8 .... 37

V

VOOH

Top

-

-10 .... 70

°C

Operating
temperature

Rated value

Uni.t

. Terminal

Symbol

287

• DC Characteristics
(VOO = 5.0V ± 0.5V,
Parameter
Input bias current

Symbol
IILl

Conditions
VIN=OV

Ta = - 10-70°C)

MIN

TYP

MAX

Unit

-

-

±1

}.LA

Terminal

Rin, lin
VI

-

High level input voltage

VIHl

-

Low level input voltage

VIL

-

High level input current

IIH

VI=VOO

Low level input current

IIL2

VI=OV

Input voltage

High level output
voltage

VOH

-

-

350

-

-

V

-

-

Voox
20%

V

-

-

±1

pA

-100

}.LA

Voo
x80%

-25

10= -0.2mA
VOOH = 36.5V

35

-50

-

rnVrms

-

V
\

A. MODE
M.MODE
P.O. R
TEST

Rl-R12
L1-L12

Low level output
voltage

VOLl

10=Q·lmA
VOOH = 36.5V

-

-

2

V

Low level output
voltage

VOL2

10=OmA
VOOH =40V

-

-

100

mV

Rl-R12
Ll-L12

Oscillation frequency

f(osc)

R= 10KQ
C= 0.02pF

6

14

KHz

OSC

\

10

FLR

-

f(osc) x 1/32

. Peak hold reset timing

pJ

-

f(osc) x 1/8192

POR release voltage

VIH2

-

Supply current 1

100H

Supply current 2

100

Supply current 3

100H
OFF

UR sampling frequency

288

VOOH " 36.5V

No load. all ~OTs ON
V ooH =36.5V

No load. all OOTsOFF
VOOH = 36.5V

No load. all DOTs OFF

4.0

-

-

-

-

15

rnA

VOOH

-

-

15

mA

VOO

-

-

2.2

mA

VOOH

V

POR, Voo

FUNCTIONAL DESCRIPTION
• paR

• asc
This is a C (capacitor) and R (resistor)
oscillation connection terminal to specify
the RlL sampling switching frequency and
the peak hold reset timing.
Example: R= 10Kn,
C = 0.0211F, fosc = 10KHz

The paR terminal with a capacitor
conne~ted is used for power on reset. The
reset release threshold voltage is 4.OV max.
The built-in pull.up resistor is about 100 Kn.
Select the capacitor value according to the
supply voltage at its leading edge. -

R
C = 2.211F~4. 711F
I

• M,MODE
When this terminal is made Low, the manual peak hold reset mode is set, and the peak hold
state is reset. For that purpose, the A. MODE terminal should be kept open.
When only the AUTO mode is to be used, connect the terminal to the Voo terminal.
"H" _ _ _ _ _ _-,
ilL"

--------------OL-J
I
I
I
I

I
I
I
I

-..~ ...4:E----- Reset

pulse width: 1OIlS min.

• A. MODE

If this terminal is made Low when M.MODE is selected, the system enters the AUTO mode
reset state. The AUTO mode reset timing is fosc x 1/8192.
When only the AUTO mode is to be used, keep the terminal Low. When power is turned
on, the AUTO mode is automatically set.
"H" _ _ _ _ _ _..,

"L"

--------------OL-J
-..~ ....4:E-----1011S min.

• Rin, Lin
These are an analogue input terminal to input an audio level signal.
Max. 350mVrms

289

• Rout, Lout
These are a capacitor (C) and resistor (R) connection terminal to hold the analogue input
peak.
Example: R= 10Kn,C= 10}lF

C

+-L

--r-

I

R

I

• RltoR12,L1toL12
These are a FLT dot output terminal

• VOOH

This is a power terminal !or Rl to R12 and L1 to L12.

• GNDH
This is

aGND terminal for Rl to R12 and L1 to L12.

• Voo
This is an analogue or logic system supply voltage terminal.

• GND
This is an analogue or logic system grounding terminal.

• TEST
This isa measurement input terminal, which is generally to be connected to the VDD
terminal.

•

VREF

This is a comparator reference power terminal, which is generally to be connected to the
VDD terminal

290

R/L THRESHOLD VOLTAGE TABLE
(Vref=5V± 1%,

Ta=25°C,

f= 1 KHz) ,

Symbol

Conditions

MIN

TYP

MAX

Unit

Threshold voltage 1

Cl

The output should be
offset. AJD

-

- 2,0

-

dB

Threshold voltage 2

C2

-17

-15

-13

dB

Threshold voltage 3

C3

-11.5

-10

-B.5

dB

Threshold voltage 4

C4

-B.O

-7

-6.0

dB

Threshold voltage 5

C5

-6.0

-5

-4.0

dB

Threshold voltage 6

C6

-4.0

-3

-2.0

dB

Threshold voltage 7

C7

-1.5

-1

-0.5

dB

Threshold voltage B

CB

Threshold voltage 9

C9

+0.5

+1

+ 1.5

dB

Threshold voltage 1'0

Cl0

+2.0

+3

+4.0

dB

Threshold voltage 11

Cll

+4.0

+5

+6.0

dB

Threshold voltage 12

C12

+6.5

+B

+9.5

dB

Parameter

The output CBlevel
should be 0 dB.

-

-

0

Terminal

dB

When the input is set to - 30 dB, all DOTs are off.

AC INPUT LEVEL VS DC INPUT LEVEL.
. Threshold voltage
Display [dB]

1

2

3

-20 -15 -10

AC input level [mV rms]

11

20

36

DC input level [mV]*

14

26

47

12

4

5

6

7

8

9

10

11

-7

-5

-3

-1

0

+1

+3

+5

+8

51

64

81

102

114

128

161

203

286

67

84

106

133

149

167

211

265

374

*The values in the table are TYP values.

291

INPUT/OUTPUT CIRCUIT·
• Rin, Lin

• R1-R12, l1-l12

16K
100n
10Kn

• OSC

• Lout, Rout

• M. MODE A. MODE,POR, TEST

soon

292

APPLICATION NOTE

VOO

Note: The base of
the PC board
should be
grounded (atone
pOint). The signal
line should be kept
away from noise
on VooHside.

VOOH

(High
voltage)

~othe
segment

,'-_ _ _ _...J/

To the segment on the left

on the left

II

To the segment on the right

Rl

10K

R2, R4
R3, R5
VR1, VR2
R6, R7

lOOK
10K
500
10K

Cl
C2
C3, C4
C5, C6
C7

2.211F-4.7JlF
:
,:
:
:

0.022JlF
1011F
2.21lF
4.711F

Information furnished by OKI is believed to be accurate and reliable.
However, no responsibility is assumed by OKI for its use; nor for any
infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise
under any patent rights of OKI.

293

OKI semiconductor
MSC1146B'
2-CHANNEL 1S-DOT LEVEL METER Ie (DYNAMIC)

GENERAL DESCRIPTION
The OKI MSC 1146B Bar graph Display Level Meter is a Bi-CMOS LSI general purpose display Level
Meter designed to interface with vacuum fluorescent type display.

FEATURES
•

Direct input of audio signals (AC signals)

•

DCinput

•

Peak hold function provided

•

Decibel display by anti-log compression ( + lOB to -:- 40dB)

•

Power ON reset circuit built in

•

FLT direct driving by high withstand voltage process (Pull~down resistor built in)

•

Grid driver output duty simply changed by C and R

•

28-pin lead plastic DIP, 30-pin shrink plastic DIP

294

BLOCK DIAGRAM

vref~

V REF

vcc~
GND~

URsample
pulse

UR
latch
circuit

OSC

H
H
Peak

0

15

0

14

H;9h

hold

vol~age

circuit

dnver
circuit

O2
timing

01
L-GRID

R-GRID
DUTY

LATCH signal
P.H.R power ON reset
L-GRID

""

\D
VI

R-GRID

VEE

PIN CONFIGURATION
30PIN Shrink DIP

0
3

28

4

27

•

26
6

25

7

24

8

23
22
21
20
19
18
17
16

15

1

VCC

1,1

NC

21

06

2

Rin

12

VEE

22

07

3

Rout

13

L-Grid

23

08

4

GND

14

R-Grid

24

09

5

Lin

15

01

25-- 010

6

Lout

16

02

26

011

7

Vref

17

03

27

012

8

PHR

18

04

28

013

9

OSC

19

05

29

014

10

DUTY

20

NC

30

015

(This specification may be changed without notice.)
296

ELECTRICAL CHARACTERISTICS
•

Absolute Maximum Ratings
Parameter

Conditions

Rated value

Unit

Terminal

. Vee

Ta = 25°C

- 0.2-7.0

V

VCC

~upplY volta&e 2
Between V and
VEE)

VEE

Ta = 25°C

VCC + 0.2- - 38

V

VEE

Input voltage

Vl1

Ta = 25°C

- 0.2-VDD + 0.2

V

Ta = 25°C,
VI= -1.0V

10MAX

rnA

Supply voltage 1

Input reverse current

II

-

Except Rin
and Lin

Output current

101

Ta = 25°C, source
current

-10MAX

rnA

01- 0 15

Output clJrrent

102

Ta = 25°C, source
current

- 50

rnA

L-Grid, R-Grid

Input voltage

VI2

Ta = 25°C

- 3.0,-VDD + 0.2

Allowable loss

P02

Ta = 70°C

480

Storage temperature

•

Symbol

- 50- + 125

Tstg

V

Rin, Lin

rnW
°C

Operating Condition
Parameter

Symbol

Supply voltage

Vee

Supply voltage

VEE

Operating
temperature

Top

Conditions

Between Vee and VE

Rated value

Unit

Terminal

4.5-5.5

V

VCC

-8--37 -

V

VEE

-10- :+-70

°C

297

•

DC Characteristics
VCC= 5.0 ± 0.5V

'Ta = -:' 10-70°C,
Specifications
Parameter

Symbol

Conditions

Unit
MIN

TYP

Terminal

MAX

.
Input bias current

IlL

Input voltage

VI

Vin=OV

± 1.0

pA'

3.5

VP.P

Rin, Lin

VCC
x80%

High level input voltage

VIHl

Low level input voltage

VILl

VCC
x20%

V

High level input current

IIH1

±1

pA

Low level·input current

IILl

-100

pA

V

PHR

-20

High level output
voltage

VOHl

10=-O.2mA
VEE =-36.0V. vee = 5V

Low level output
voltage

VOLl

10 = OmA. VEE = -36.5V
(Between vee and VEE)

Pull-down resistor

Ro

High level output
voltage

VOH2

Oscillation frequency

Vee = 5V,
VEE =-36.5V
~=-20mA.

fosc

UR sampling frequency

f. UR

Peak hold reset timing

PJ

EE =-36.5V. Vee = 5V
(Between Vee and VEE)

R= 10KQ,
C = 0.022pF

-50

3.5

10

V

200

mV

500

KQ

2.5
6

V
10

14

01- 0 15
R-Grid
L-Grid
R-Grid
L-Grid

KHz

OSC

V

VCC

,V

VREF

fosc x 1/32
\

fosc x 1/8192

POR release voltage

VIH2·

4.0

Voltage VREF

VREF

Vee=5V,
VEE =-36.5V

Supply current

IEEl

Vee = SV,VEE = -36.5V DUTY
1112
No load, all DOTs ON

5

mA

VEE

Supply current

IEE2

Vee = 5V,VEE = -36.5V DUTY
No load, all DOTs OFF 1112

5

mA

VEE

Supply c~rrent

lee

vec :=5V.V EE =-36.5V'
No load, all DOTs OFF

10

mA

Vee

-8

-5

Note: Voltage VEE is a voltage between the Vee and VEE terminals.

298

,200

01- 0 15

-2

FUNCTIONAL DESCRIPTION
VCC: This is an analogue or logic system
voltage input terminal.
Rin, Lin: These are audio input terminals to
directly input an alternating current
via a capacitor coupling. Max. 3.SV P.P
Rout, Lout: These terminals rectify an audio
alternating current with a capacitor
and resistor connected.

OSC: This is a C (capacitor )and R(resistor)
oscillation connection terminal to
specify the UR sampling and UR-Grid
switching frequency and the peak hold
reset timing.
R= 10kn
C= 0.02211F
fosc;: 10kHz

R

o
R
Standard:
R= 10Kn, C= l011F

Vref: This is an amplifier built-in voltage
output terminal. Connect a capacitor
of about l011F between the GND and
Vrefterminals.

P.H.R: This is a peak hold reset terminal.
When the terminal is Low, the reset
state is fixed. (Peak hold function
inhibition state: The peak hold
function is performed for an input of
- 10 dB or higher.)

299

DUTY: This terminal with a capacitor (C) and a resistor (R) connected is used to adjust the URGrid duty ratio and to change the FLT brightness.. When the terminal is fixed Low, the
duty ratio is about 1/4.

____________________,~1~0:s_c~_x~_~1_/~1:~:I~--~I~~
___________________~
.

fosc x 1/32

~------------------------------------):~

~

1 About 3.2 ms (1 cycle) at
f osc = 10KH z ,

'I
Wt can be adjusted by C and R. The maximum duty ratio is 1/4.
Vee

R

Example:
R= 10KQ,
C = 0.04611F,
Pulse width 270115
(Duty ratio: About 1112)

=

Pulse width calculation method
Wt

=0.587 x C x R(5)

When the

v~lue for R is non 0 K, the constant may be slightly changed.

Note: The resistance should not be less than 8K.
VEE: This is a FLT driving supply voltage terminal. The power supply system is as follows:

+

+
SV

36.SV

UR-Grid: This is a FLT grid driving output terminal. The timing waveform isshownin the
illustration for the DUTY terminal. The grid can be directly driven.

300

01 to 015: 'These terminals are FLTsegment terminal with a rull-ddwn resistor built-in to
directly drive the segment.
Note: Precautions for operation
Power ON and OFF sequence
Power connection diagram

2.

1.

a

o

o

b

Power source a

Power source b

When turning power on, turn the power source b on prior to or simultaneously with the
power source a. When turning power off, turn the power source a on prior to or
simultaneously with the power source b.
The time difference between a and b should be within 5 seconds as following time chart.
For 5 seconds, a current of 80 to l20mA (Vee

=SV) flows through the power sourcea.

This is a normal phenomenon. When the power source b is turned on, the system enters the
normal state.

Power source a
5 seconds

~

:~

~:

~

5 seconds

Power source b

301

THRESHOLD VOLTAGE TABLE
VCC=5V± 1%,

Ta=25°C

Specifications
Parameter

Terminal

Conditions

Unit
MIN

TYP

MAX

Threshold voltage 1

01

9

10

13

dB

Threshold voltage 2

02

6

8

9

dB

Threshold voltage.3

03 .

4

5 .

6

dB

4

dB

Threshold voltage 4

04

1.5

3

Threshold voltage 5

05

0.5

1

1.5

dB

Threshold voltage 6

06

-

0

-

dB

Threshold voltage 7

07

-1.5

-1

-0.5

dB

Threshold voltage 8

Os

-4

-3

-2

dB

Threshold voltage 9

09

-6

,-5

-4

dB

Threshold voltage 10

010

-8.5

-7

-6

dB

Threshold voltage 11

011

-13

-10

-8.5

dB

Threshold voltage 12

012

-18

-15

-13

dB

Threshold voltage 13

The input should be adjusted to 0 dB.

013

-25

- 20

-18

dB

Threshold voltage 14

014

-35

-30

- 25

dB

Threshold voltage 15

015

-45

-40

- 35

dB

OFF SET should be set to - 40 dB.

When the input is set to - 60 dB, all DOTs are off. The peak hold function is effective for an
input of - 10 dB (011) or higher.

AC INPUT LEVEL VS DC INPUT LEVEL
Threshold voltage
Display [dB]

4

3

2

5

7

6

8

9

10

10

8

5

3

1

0

-1

-3

-5

-7

782

622

440

349

278

247

221

175

139

110

1,107

879

622

494

393

350

312

248

197

156

11

12

13

14

15

Display [dB]

-10

-15

-20

- 3C

-40

ACinput level [mV rms]

78.5

44.0

24.7

7.85

2.47

111

62.2

35.0

11.1

3.50

AC input level [mV rms]
DC input level [mV]*
Threshold voltage

DC input level [mV]*

302

1

*

Input from the Lout or Rout
terminal..
The values in the table are
TYPvalues.

INPUT CIRCUIT
oRin, Lin

2kn
o-'VV'v

o OSC

~2kn~
2

kn

2kn
'VV'v·-----.-H

OUTPUT CIRCUIT
o L-Grid,'R-Grid

lOon
loon

15kn

o Lout, Rout

303

APPLICATION NOTE

...c

u..

CII

::l.

E
en
CII

11'1

ID

U

u..

c:
~

::l.

ID
~

0

~ ci
11'1
0:::

U

c:

N
N

LI'I

u..
~

~

+

::l.

0

~ ci

u)
M
I

~

0:::

v

U

0:::

>

c:
0
0
LI'I

M

0:::

c:
~

0

u..

::l.

~

0
u..

::l.

~ ~

N

0:::

N

U

N

....
0

c:

u..

~ ~

N

"0
"0 ~

U

.,J

~

:;
~

.~

en
0

Rj
C

ro

0:::

o
.~

en
0

"

Rj
C

ro

-I

Information furnished by OKI is believed to be accurate and reliable.
However, no responsibility is assumed by OKI for its use; nor for any
infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise
under any patent rights.of OKI.

304

::l.

N

One Chip
Microcontroller
===================:::==============================================================:J

OKIi

sernraficondlUlcQcr

MSC6458
OKI 4-BIT 1-CHIP MICROCONTROLLER
GENERAL DESCRI~TION
The MSC6458 is a high-speed, 4-bit 1-chip microcontroller with built-in FLT drivers/controllers developed
to support relatively large control systems.

FEATURES
• ROM: 8000 x 8 bits
• RAM: 512 x 4 bits
• Ports: I/O 24 ports (8 having 10L = 20 rnA)
Input 9 (2 also serving as interrupt inputs),
• FLT drivers (Withstand 12 (IOH = 20mA)
voltage 40V):
12 (IOH = 6mA)
• LED direct dnve available
• Interrupts: 7 lines (2 external, 5 internal)
• Built-in counters: 12 bits, timebase counter
16 bits, programmable counter
8 bits, high-speed
programmable timer/event
counter

•
•
•
•
•

Serial I/O: Built-in 8-bit SIO register
Oscillation circuit: Crystal or ceramic oscillation
Number of instructions: 147
Cycle time: 930 ns ( 4.3MHz)
Operating ranges: 4.5 to 5.5V ( 4.3MHz)
Voltage: 3.0 to 6.0V (1 MHz)
Temperature: -40 to +85°C
• Power dissipation (typical)
(display off): 9mA (5V, 4.3MHz)
2mA (3V. 1MHz)
o Power down: STOP instruction
•

Package: 64-pin shrink DIP/54- pin FLAT

BLOCK DIAGRAM

TO
Tl

TIl
SEGO
SEG 1
I
I
I
I

SEG 11

-VDD

-GND

210

3210

3210

3210

3210

307

LOGIC SYMBOL

PIN CONFIGURATION (TOP VIEW)
64 PIN PLASTIC "':~o
SHRINK DIP

.-Cl:

~WG

t.l; •• O~

:Jr
:JOJ

t'Wl."::I:

RESET
TEST
5V

"no.,II
·"I
""0'"111 X

OV

....

~~,~

FLTPow.,

.. -err:
::~
'·X
-1]£

]PO RT 6

"'JI:

I O,g'IOUIO~1

..,:m:
"':E

"'1':
""-l..!."'[

PORlI [

lorFlT

PORT1[
PORTe [

_JI:

I

PORT2[

:rn
X

:v:

M~
M~

M~
$1M
YUf

~M"
:If;

tlGt

:n::tfG'O

:n:

MO"

l': ...

:e:
::n: '''MO''
"OMG'J

X

'I Mil'.

Jr

fIU"'~

)iJ"OU"

;no

.~

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:K'IOU"

~1I:

::Jlj •• OU"

.-oIL
''':>I:

lIl..,ou"

"':n;

:~;:j

I ] Segmenl
Ouloul
lorFLT

n·oo

;g:'Mac

~_I

-:n:

.;~

~!L 'IOU"

JaJ"o.,',
X'Oo..'Q
X~

J!:~

~::;

::"'l_____~::.

PIN DESCRIPTION
Input!
Output

Function

When
reset

POO'
P01/SCK
P02/S0
P03/S1

Input!
Output

1/0 port
_
1/0 port (also used as serial clock input SCK)
1/0 port (also used as serial data output SO)
1/0 port (also serial data input SI)

"1"

P10/CIN
P11/TMO
P12/TCK
P13

Input!
Output

1/0 port (also used as count input CIN)
1/0 port (also used as timer output TMO)
1/0 port (also used timer clock input TCK)
1/0 port

Terminal

P20/lNTO
P22/1NT1

Input Port with Latch (falling~e sensitive)
also used as interrupt input INTO
Input Port with Latch ('0' level sensitive)
also used as interrupt input INn

-

P30 -P33

Input!
Output

1/0 port

"1 "

P60 -P63

Input!
Output

1/0 port

"0"

P40 -P43
P50 -P53

Output!
Input

1/0 port (lOL =20mA MAX)

"0"

P70 -P72
P80 -P83

Input

Input port with pull down register
Pull down register of P70 - P72 can be removed
by instruction

SEGO - SEG11

Output

FLT segment driver (dynamic)

"0"

T11/SEG12
-T8/SEG15

Output

FLT segment driver (dynamic)/Timing output,

"0"

"0"

T710UT7
-TOIOUTO

Output

FLT segment driver (static)/Timing output

OSCO
OSC1

Input!
Output

Crystal conneGtion terminal for system clock
oscillation

-

System reset input

-

Test pin (Open)

-

RESET

308

Input

"1 "

Input

TEST

Output

VFLT

Input

Power supply for FLT driving

-

VDD
GND

Input

System Power Supply

-

FUNCTIONAL DESCRIPTION
1. ROM
The ROM, organized in 8 bits, has a
maximum capacity of 8000 bytes.

2. RAM
The RAM is organized in 4 bits per word,
with a capacity of 512 words.
It is separated into two banks each 256
words long. Bank selection is accomplished via
internal ports. The RAM location in the banks is
addressed by the Hand L registers or by the
second byte of each instruction.
3. Ports (24 I/O, 7 input)
The 24 pseudo-bidirectional I/O ports effect
or control the exchange of data with external
sources. The ports are specified by the L
register or by codes contained in instructions.
Ports 4 and 5 may draw 10L up to 20mA.
The seven input ports have built-in pulldown
resistors. Up to 84 keys can be scanned by
assembling them in key matrices with the timing
outputs of th'e FLT drivers' (with 12 segments x
12 timings on display; also during automatic
display).
4. Interrupt Input Pins (2 terminals)
The INTO/P20 and INT1/P22 pins are
interrupt input pins. External interrupt request
flags of INTO/P20 pin and INT1/P22 pin can be
set by using interrup,t input pins:
, INTO/P20 pin ... positive edge or negative edge
input.
INT1 /P22 pin ... "0" level input.
These flags are automatically reset when
the appropriate external interrupts occur. These
pins are available for use as input ports when not
used as interrupt input pins.
5. FL T Drivers/Controllers (Automatic Display)
The FL T drivers have a withstand voltage of
40V in the positive direction from the GND level.
They comprise 12 ports that can draw 20mA as
10H (Timing outputs) and 12 ports that can draw
6mA as such (Segment outputs).
A choice of four display modes is supported
as listed below. A display RAM area is allocated
as part of the RAM space. Data is automatically
displayed when transferred to the display RAM.
(Two different display frequencies are
selectable.) Static output data can be displayed
by controlling the FL T drivers by programming.
Display modes (@4.1 94304 MHz)
(1) 12 Segments x 12 Timings
1/12 duty (85.3/341.3 Hz)
(2) 16 Segments x 8 Timings
1/8 duty (128/512 Hz)
(3) 16 Segments x 4 Timings +4 output"
1/4 duty (256/1 024Hz)
(4),16 Segments+8 output"
Program controlled
"output: static outputs

6. Stack (STACK) and Stack Pointer (SP)
The PC is saved In the stack when an
interrupt occurs or a CAL instruction is
execl\ted. It is recovered by the execution of an
RT instruction.
One fourth' of the RAM space (128 words
maximum, 32 levels) is available as a stack area.
A 4-word RAM area is used for "one" level in the
stack.
The stack pointer is an 8-bit up-down
counter (the MSB and 2 bits from LSB being
fixed at '1') indicating the next stack address to
use. It enables the RAM space to be used as a
pushdown stack. Data can also be transferr~d
between stack pointer and the H/L registers.
7. Interrupts
Seven interrupt lines are provided for eight
sources and eight levels of interrupts as follows,
(two external inputs):
(1) Display interrupt
Update to timing signals (positive edge)
(2) External interrupt1
Negative edge on the INTO/P20 pin
(3) External interrupt2
Positive edge on the INTO/P20 pin
_.
(4) External interrupt3
'0' input onthe INT1 /P22 pin
(5) Timebase interrupt
12-Bit timebase counter overflow
(6) Timer interrupt
16-Bit timer and timer register matched signal
(7) Counter interrupt
8-Bit counter and counter register matched
signal
(8) Serial/O interrupt
8-Bit shift register shift end signal
8. 12-Bit Timebase Counter
The timebase counter is made up of a 12-bit
binary counter. It generates an interrupt request
every time it overflows as a result of dividing the
OSCO input 212.
9. 16·Bit Programmable Timer/Event Counter
Comprising a 16-bit register, a 16-bit binary
counter, a comparator circiut, and a control
circuit, the programmable timer generates an
interrupt request when the register and counter
values are matched.
10. 8·Bit High·Speed Programmable
Timmer/Event Counter
The high-speed programmable timer/event
counter comprises an 8-bit register, an 8-bit
binary counter, a comparator circuit, and a
control circuit. Starting and stopping the counter
can be controlled by instructions. It generates an
interrupt request when the register and counter
values are matched.

309

11. a-Bit Serial 1/0
Serial 1/0 consists of an 8-bit shift register,
a 3-bit shift counter, and a control circuit. It is
used for serial data input and output. Serial data
input and output takes place synchronize~ with
a· shift clock. which is selectable between
internal and external clocks. The shift counter
automatically terminates a data transfer on
counting' eight shift clock pulses and generates
an interrupt request.
12. Registers (Ace, H, L, F)
The accumulator (Acc) is a 4-bit register
used to perform data transfers or calculations
wLth the RAM, other registers, ports and so on.
The Hand L registers are each a 4~bit
register. They transfer data to and from Acc and
SP (slack pointer) and address the RAM: The L
register is also used to specify ports to use.
The' F register is made up of four
independent flip-flops. It can be used as a
program "flag" or general-purpose register
because each of Ihese flip-flops permits
set/reset testing and transferring A-bit parallel
data to and from Acc by Instructions.
13. Timing Control (Te)
A 'a· input on the RESET pin for a certain
period initializes Internal circuitry and ports.
As the input side of clock pulses, the oseo
pin accepts clock pulses from an external
source. Clock pulses may also be .obtained by
configuring an oscillation circuit wi.th a crystal
oscillator or ceramic resonator connected to
oseo and OSC 1 ..

310

Load Instructions, etc.
Mnemonic
LAI

n

Code

8ytes

Cycles

90-9F

1

1

Description

,

A +-n

LLI

n

80-8F

1

1

L+-n

LHI

n

3E·7n

2

2

H +- n

LHLI

nn

15· nn

2

2

HL +- nn

LMI

nn

14· rin

2

2

M (w)'+- nn

LAL

21

1

1

A+-L

LLA

2D

1

1

L+-A

LAH

22

1

1

A+-H

LHA

2E

1

1

H+-A

LAM

38

1

1

A+-M

LMA

2F

1

1

M +-A

LAM +

24

1

1

A+- M, L +- L+1, Skip if L

= "0"

LAM-

25

1

1

A+- M, L +- L-1, Skip if L

= "F"

LMA+

26

1

1

M +- A, L +- L+1, Skip if L

= "0"

LMA-

27

1

1

M

+-: A, L +- L-1, Skip if L = "F"

LAMM

n2

39-38

1

1

A +- M, H +- H ¥ n2

LAMD

mm

10 ·mm

2

2

A+-Md

LMAD

mm

11·mm

2

2

Md +-A

X

28

1

1

A-M·

X+

3C

1

1

A-

M, L +- L + 1, Skip if L

= "0"

X-

2C

1

1

A-

M, L +-L-1, Skip if L

= "F"

M, H +- H ¥ n2

XM'

n2

29-28

1

1

A_

LMT

mm

19· mm

2

4

M (w) +- T (Md (w), A)

LAF

3E·54

2

2

A+-F

LFA

3E·5C

2

2

F+-A

LHLS

3E·53

2

2

HL +- SP

lSHL

3E·58

2

2

'SP-HL

IP

20

1

1

A+-P

OP

23

1

1

P+-A

IPD

p

3D· pD

2

2

A+-Pp

OPD

p

3D· pC

2

2

Pp +-A .

18

1

3

P4, P5 +- T (M (w), A)

OPT

311

Interrupt Control Instructions
Mne{'l0nic·

312

Description

Code

Bytes

Cycles

MEl.

3E·60

2

2

MEIF _"1"

MOl

3E·61

2

2

MEIF_"O"

EIXD

2

2

EIXDF -"1"

EIXU

3D· E8
3D· E9

2

EIXL

3D· EA

2
2

EIXUF -"1"
EIXLF _"1"

EIOP

3D· EB

2

2

EITB

30·08

2

2

EIDPF -"1"
EITBF _"1"

EITM

.30·09

2

2

EITMF-"1"

EICT

3D·OA

2

2

EICTF -"1"

EISR

3D· DB

DIXD

3D· E4

2
2

2
2 •

EIXDF -"0"

DIXU

3D· E5

2

2

EIXUF-"O"

DIXL

3D· E6

2

2

EIXLF -"0"

DIOP

3D· E1

2

2

DITB

.30·04

2

2

EIDPF-"O"
EITBF_"O"

DITM

30·05

2

2

EITMF-"O"

DICT

30·06

2

2

EICTF-"O"

DISR.

30·07

2

2

EISRF-"O'"

TIXO

3D· EO

2

2

Skip if EIXDF

TIXU

3D· E1

2

2

Skip if EIXUF

TIXL

3D· E2

2

2

TIDP

3D· E3·

2

2

TITB

3D· DO

2.

2

TITM

30·01

2

2

TICT

30·02

2

TISR

30·03

2
2

TOXD

30·20

2

2

TOXU

30·21

2

2

TOXL

30·22

2

2

TOOP

30·23

2

TOTB

3D· CO

2

2
2·

TOTM

3D· C1

2

2

TOCT

3D· C2

2

2

TOSR

3D· C3

2

2

ROXD

30·24

ROXU

30·25

2
2

2

IROXDF - '~O"
IROXUF-"O"

2

2

2

EISRF -"1"

= "1"
= "1"
Skip if EIXLF = "1"
Skip if EIDPF = "1"
Skip if EITBF = "1"
Skip if EITMF = "1"
Skip if EICTF = "1"
Skip if EISRF = "1"
Skip if IROXDF = "1"
Skip if IROXUF = "1"
Skip if IROXLF = "1"
Skip if,IRODPF = "1"
Skip if IROTBF = "1"
Skip if IROTMF = "1"
Skip if IROCTF = "1"
Skip if IROSRF = "1"

ROXL

30·26

2

2

IROXLF-"O"

ROOP

30·27

2

2

IRODPF-"O"

ROTB

3D· C4

2

2

IROTBF-"O"

ROTM

3D· C5

2

2

IROTMF-"O"

ROCT

3D· C6

2

2

IROCTF-"O"

ROSR

3D· C7

2

2

IROSRF -"0"

Increment/Decrement Instructions
Mnemonic

Code

Bytes

Cycles

INA

30

1

1

A _A+1, Skip if A

INL

31

1

1

L _ L+1, Skip if L = "0"

INH

32

1

1

H_ H+1, Skip if H = "0"

Description

= "0"

INM

33

1

1

M _ M+1, Skip if M = "0"

DCA

34

1

1

A -A-1, Skip if A

DCL

35

1

1

DCH

36

1

1

DCM

37

1

1

= "F"
L _ L-1, Skip if L = "F"
H _H-1, Skip if H = "F"
M _ M-1, Skip if M = "F"
Md _ Md+1, Skip if Md = "0"
Md _ Md-1, Skip if Md = "F"

INMD

mm

12· mm

2

2

DCMD

mm

13· mm

2

2

Code

Bytes

Cycles

54-57

1

1

Skip if A (n2)

Bit Handling Instructions, etc.
Mnemonic
TAB

n2

Descrip~ion

RAB

n2

64-67

1

1

A.(n2) -"0"

SAB

n2

74-77

1

1

A (n2) - "1"

TPB

n2

50-53

1

1

Skip if P (n2)

= "1"

= "1"

RPB

n2

60-63

1

1

P(n2) -"0"

SPB

n2

70-73

1

1

P (n2) - "1'!

TMB

n2

58-5B

1

1

Skip if M (n2)

RMB

n2

68-6B

1

1

M (n2) -"0"

5MB

n2

78-7B

1

1

M(n2)-"1"

TFB

n2

5C-5F

1

1

Skip if F (n2)

RFB

n2

6C-6F

1

1

F (n2) - "0"

SFB

n2

7C-7F

1

1

F (n2) - "1"

TPBD

p,n2,

3D" pO-3

2

2

Skip if Pp (n2)

RPBD

p,n2

3D· p4-7

2

2

Pp (n2) -"0"

SPBD

p,n2

3D· p8-B

2

2

Pp (n2) - "1"

TC

09

1

1

Skip if C

RC

08

1

1

C_"O"

SC

07

1

1

C_"1"

= "1"

= "1"

= "1"

= "1"

313

Arithmetic Instructions
Mnemonic

Code

Bytes

Cycles

Description

ADCS

01

1

1

C, A ~ C+A+M, Skip if C

ADS

02

1

1

A ~ A+M, Skip if Cy

ADC

03

1

1

C, A+-C+A+M

3E·4n

2

2

A+- A+n, Skip if Cy

DM

06

1

1

A +-A+6

DAS

OA

1

1

A+-A+10

AIS

n

= "1"

= "1"
= "1"

AND

00

1

1

A+-A/\M

OR

05

1

1

A+-AVM

EOR

04

1

1

A+-A¥M

CMA

OB

1

1

A+-A

CIA

OC

1

1

A+- A+1

RAL

OE

1

1

CC +-

3 +- 2 +- 1 +- 0:)
,--A _____

RAR

OF

1

1

~C-+

3-+2-+1-0)

,--A~

16

1

1

Skip if A

=M

CAl

n

3E· On

2

2

Skip if A

=n

CMI

n

3E·1n

2

2

SkipifM

=n

CLI

n

3E·2n

2

2

Skip if L

=n

CPI

p,n

17· pn

2

2

Skip if Pp

Code

Bytes

Cycles

CO-FF

1

1

PC +-a6

1A

1

2

PC +- (PC·+- A) +1

JM

1B

1

2

PC +- (M (w), A)

JP

a12

40 4F
OO-FF

2

2

PC +- a12

CAL

a12

AO AF
OO-FF

2

4

ST +- PC+2, PC +- a12, SP +- SP-4

CZP

a

Ba

1

4

ST +- PC+1, PC +- ?a, SP +- SP-4

LJP

a13

3F 3F
00-1F
00 FF

3

4

PC +- a13

LCAL

a13

3F 3F
80-9F
00 FF

3

4

ST +- PC+3, PC +- a13, SP +- SP-4

RT

1E

1

4

PC +- ST, SP +- SP+4

RTS

1F

1

4

PC +- ST,SP +- SP+4, then Skip

CAM

=n

Branch Instructions, etc.
Mnemonic
JCP

a6

JA

314

Description

Counter Control Instructions, etc.
Mnemonic
LCTM

I

Code

Bytes

Cycles

3E·51

2

2·

Description
CTR +-M (w)

LMCT

3E·59

2

2

M (w) +-CT

ECT

3D· BB

2

2

CTF +- "1"

(Counter Start)

DCT

3D· B7

2

2

CTF

"0"

(Counter Stop)

TCT

3D· B3

2

2

Skip if CTF = "1"

LTMM

3E·50

2

3

TMR +-M (2w)

LMTM

3E·58

2

3

M (2w) +-TM

LSRM

3E·52

2

2

SR +- M (w), SC +- "0"

LMSR

3E·5A

2

2

M (w) +-SR

ESR

3D· BA

2

2

SRF +- .i1"

(Shift Register Start)

DSR

. 3D· B6

2

2

SRF +-"0"

(Shift Register Stop)

TSR

3D· B2

2

2

Skip if SRF = "1"

Code

Bytes

Cycles

<-

SC: Shift Counter

CPU Control Instructions, etc.
Mnemonic

Description

PUSH

1C

1

3

ST ~ C, A, H, L. SP +- SP-4

POP

10

1

3

C, A, H, L +- ST, SP +- SP+4

HALT

3D· B8

2

2

Halt CPU

STOP

3D· B9

2

2

Stop CPU

NOP

00

1

1

No Operation

315

explanations of Instruction Symbols

A
H
L
F
M

: Accumulator (4-bit)
: H register (4-bit)
: L register (4-bit)
:.F register (4-bit)
: RAM word addressed by the Hand L registers
Md
: RAM word addressed by second byte of an instruction code
M(w)
: Two RAM words addressed by the Hand L register/H3-0 and L3-1 (a-bit)
Md(w) : Two RAM words addressed by second byte of an instruction code (a-bit)
M(2w) : Four RAM words addressed by the Hand L register/H3-0 and L3-2 (16-bit)
: Four RAM words (16-bit) allocated as a stack area
ST
: Stack pointer (a-bit)
SP
PC
: Program counter
P
: Port specified by the L register (4-bit)
: Port specified by 4 high-order bits of second byte of an instruction code (4-bit)
Pp
: a-Bit counter/register
.
CTA
: a-Bit programmable counter
CT
: Programmable counter start flag
CTF
: 16-Bit timer/register
TMA
: 16-Bit programmable timer
TM
: a-Bit shift register
SA
,
: Shift register start flag
SRF
(X, Y)
: ROM addre'ss data specified by al14 as X and a3-0 as Y (12-bit)
T(X, Y) : ROM table data specified by a 11-4 as X and a3-o as Y (a-bit)
: Immediate data (4-bit)
n
nn
: Immediate data (a-bit)
n2
: Two low-order bits of an instruction code
(n2)
: Bit specified by the two low-order bits of an instruction code
a
: ROM address data·
ax
: ROM address data (X-bit)
: RAM address data (a-bit) .
mm
: Carry flag
C
Cy
: Flag indicating a carry in a calculation result

316

ELECTRIC CHARACTERISTICS
• Absolute Maximum Ratings
Parameter

Symbol

Supply Voltage

VOO

Indicated Supply Voltage

VFLT

Input Voltage
Input Voltage

Conditions'

Limits

Ta = 25°C

VI
Ta = 25°C

Vo

V

VOO - 45

V

-0.3 - VOO

V

Input/output

-0.3 - VOO

V

Indicated output

-0.3 - VFLT

V

10

mA

40

mA '

SEGO - SEG1
Per pin
"H" Output Current
(Indicated Output)

"L" Output Current
(P4, P5)

Power Dissipation
Storage Temperature

Unit

-0.3 -7

TO - T11'
*

30

mA

Output terminal SEGO - SEG11
total
TO - Tl1

72
72

fnA

Per terminal

20

mA

P4 total

40

mA

OUTO - OUT7

10H

10L

Po

mA

P5 total

40

mA

Per package

SOO

mW

Per input/output terminal

50

mW

-

-55 - +150

°c

Tstg

* When timing output is used as static output

• Operating Conditions
Parameter

Symbol

Conditions

Limits

Unit

f (osc) ~ 4.3MHz

4.5 - 5.5

V

f (osc) ~ lMHz

3-S

V

10 -40

V

Supply Voltage

VOO

Indicated Supply Voltage

VFLT

-

Memory Retension Voltage

VOOH
Topr

Oscill,ation off

2-S

V

-

-40 - +85

°c

MOS Load

15

-

Operating Temperature
(Fan Out (Input/Output Port)

N

TTL Load

1

• DC Characteristics
Parameter

(V DO = 5V ±10%, Ta = -40 - +85°C)
Terminal applied Symbol

Conditions

Min.

Typ.

-

2.4

-

3.8

-

3.4
0

-

-

0

10 = -15~A
10= -SmA

TO - Tl1

10 = -20mA

VFLT-3.5

PO, Pl, P3,PS

10 = .1.SmA

P4, P5

10 = 10mA

-

*1
"H" Input Voltage

OS CO, RESET

VIH

P7, P8
ilL" Input Voltage

*2
P7,P8

VIL

*3
"H" Output Voltage

"L" Output Voltage

SEGO - SEGll

OSCl

VOH

VOL

10 = 15~A

SEGO - SEGll

10 = lmA

TO - T11

10 = lmA

OSCO
"H" Input Current

P2, RESET
P7(P73=0), P8
P7(P73=1 )

IIH

VI = VOO

Max.

Unit

VOO

V

VOO

V

VOO

V

0.8

V

-

1.S

V

4.2

-

-

V

VFLT-2.5

-

-

V

0.4

V

-

V

0.8

V

0.4

V

l.S

V

1.4

V

15

~A

1

~A

SO

~A

1

~A

317

Parameter

Terminal applied Symbol
OSCO
P2, RESET

"L" Input Current

Min.

Typ.

Max.

Unit

-

-15

J.lA

-30

J.lA

-1

-0.1

-

-

J.lA
mA

-1.2

mA

Conditions
VI

IlL

= OV

P7,P8
PO, Pl, P3,

"H" Output Current

P4,P5,P6

Current Consumption

VO = 2.4V

IOH
IDD

-

-

No load
f (osc) = 4.3MHz

-

12

20

mA

No load

-

1

100

J.lA

-

0.5

10

J.lA

-

2

100

J.lA

VO

= O.4V

,Current Consump'tion
(When stop mode condition)

IDDS

No load
VDD = 2V
Ta = 25°C

Current Consumption
(FLT driver section)

IFLT

No load
All F LT driver,
"L" level

* 1. Applied to PO, Pl, P2, P3, P4, P5, P6
*2. Applied to PO, Pl, P2, P3, P4, P5, P6, OSCO, RESET1
*3. Applied to PO, Pl, P3, P4, P5, P6, OSCl

• AC Characteristics

(VDD = 5V ±10%, Ta = 40 - +85°C)

Parameter
Clock (O.S.C 0) Pulse Width

Symbol'

Conditions

Min.

Typ.

Max.

Unit

t
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