1989_Rockwell_Communications_Products 1989 Rockwell Communications Products
User Manual: 1989_Rockwell_Communications_Products
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1989
COMMUNICATION PRODUCTS
DATA BOOK
Rockwell International
Semiconductor Products Division
©Rockwelll nternational Corporation 1989
All Rights Reserved
Printed in U.S.A.
Order No.4
January 1989
Rockwell Semiconductor Products Division is headquartered in Newport Beach, California with
Field Sales Offices located throughout the United States, Canada, Europe and the Far East. Their
listings, plus those of domestic and international representatives and distributors, appear in AppendlxA.
Definition of Document Types
Document Type
Product Status
Product Preview
Formative or
Development
The document type contains the general features
and/or specifications for a product in definition or
development. The features and/or specifications
may change in any manner without notice.
Product Summary
Development or
Production
This document type contains the general features
and/or specifications of a product in development or
in production. Additional information is usually
available in a separate document, not contained in
this book, such as a Designer's Guide.
Data Sheet
(Preliminary)
Sampling or
Pre-Production
This document type contains preliminary or
design-to-characteristic data for a product in
pre-production. Additional and/or refined
characteristic data will be released in subsequent
revisions to the document.
Data Sheet
Production
This document type contains final speCification
information resulting from measured
characteristics. This document type is subject to
revision if characteristics are further refined during
production.
Product Description
Production
This document type contains final specification
information resulting from measured characteristics
along with additional application aid information.
This document type is subject to revision if
characteristics are further defined during production.
Application Note
Development or
Production
This document type contains application aids in the
use of the subject product. Schematics included in
an application note are intended to convey system
design concept only.
Definition
NOTICE
Information furnished by Rockwell International Corporation is believed to be accurate and reliable.
However, no responsibility is assumed by Rockwell International for its use, nor any infringement of
patents or other rights of third parties which may result from it use. No license is granted by implication or
otherwise under any patent or patent rights of Rockwell International other than for circuitry embodied in a
Rockwell product. Rockwell International reserves the right to change circuitry at any time without notice.
All documents in this book are subject to change without notice.
ii
TABLE OF CONTENTS
Section 1· Dlal.Up Data Modems ................................................... 1-1
Product Family Overview ................................•..•..................... 1-2
R212DP Device Set Be1l212A Compatible ........................................... 1-3
R212AT Device Set "AT" Command Set Be1l212A Compatible .•.•.............••...••••. 1-5
RC224AT 2400 bps Modem Device Set with "AT" Commands . . . • . . . • . . . . . . . . . . . . . . . • . . .. 1-7
RC224EB2400 bps Modem Evaluator Board for RC224AT . . . . . . . • . • • . . . • . . . . . . . . . . . . •. 1-37
R12121200 bps Full-Duplex Modem ................. '.............................. 1-45
R2424 2400 bps Full-Duplex Modem .................... ',' .....•.............•..... 1-74
RC2424DP/DS 2400 bps Full-Duplex Modem Device Set .............•............... 1-103
RC2324DP/DS 2400 bps Full-Duplex Modem Device Set ............•........•....... 1-139
RC2324SME System Module ............... ' ......... '" .....•.......•.......... 1-176
RC2324SMEIDS System Module Device Set ....................................... 1-186
R96QT 9600 QuickTurn Modem ................................................. 1-187
R9696DP V.32 9600 bps Full-Duplex Modem ...........•.........................•. 1-215
Section 2 • Leased Line Data Modems •.............................................. 2-1
Product Family Overview ............................................. ; ............ 2-2
R208/201 4800 bps Modem .....•....................................... ',' ........ 2-3
R96DP 9600 bps Data Pump Modem .............................................. 2-26
R96FT 9600 bps Fast Train Modem ...........•..................................• 2-47
R96FT/SC 9600 bps Fast Train Modem with Forward Secondary Channel .........•...•... 2-63
R144DP V.3314.4 kbps Full-Duplex Modem ...............................•........ 2-78
R1496DP V.3314.4 kbpsN.32 9600 bps Full-Duplex Modem •...................•..... 2-103
Section 3 • Image Modems ......................................................... 3-1
Product Family Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-2
R24MFX 2400 bps MONOFAX Modem .............................................. 3-3
R24BKJ 2400 bps V.26 bis Modem ................................................ 3-19
R48MFX 4800 bps MONOFAX Modem ............................................. 3-35
R48PCJ 4800 bps PC Communication Modem ...................•..... , ............. 3-51
R24/48MEB Modem Evaluation Board ..•................................ :......... 3-67
R96MFX 9600 bps MONOFAX Modem ............................................. 3-80
R96EFX 9600 bps MONOFAX Modem with Error Detection ........... :...........•..... 3-103
R96MEB Modem Evaluation Board ..........................................•.... 3-128
R96PCJ 9600 bps PC Communication Modem ...................................... 3-144
R96FI9600 bps Facsimile Modem ............................................... '3-157
R96MD 9600 bps Facsimile Modem ......................... ; .................... 3-175
R144HD 14400 bps Half-Duplex Modem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-193
iii
TABLE OF CONTENTS (CONTINUED)
Section 4 - Data Modem Application Notes ..............•............••........•..... 4-1
An R6500/11-R2424 Intelligent Modem Design ..............•......................... 4-3
Interfacing Rockwell Signal Processor-Based Modems to an Apple lie Computer ............ 4-46
2400/1200/300 bps International Modem Design ..................................... 4-50
Quality of Received Data for Signal Processor-Based Modems ...•...................... 4-83
R2424 and R1212 Modems Auto Dial and Tone Detection ..•.........•.........•...... 4-104
8088 Microprocessor to R1212/R2424 Modem Interface .....•........................ 4-114
RC2424DP/DS Diagnostic Data Scaling ..................•.•.•.................... 4-119
RC2424DP/DS HDLC Features .......................•.......................... 4-130
Data Access Arrangement (DAA) Design for the R1496MM, R9696DP, and R144DP . . . • . . .. 4-135
R1496DP, R9696DP, and R144DP Programmer's Guide ..•..•....................... 4-148
R9696DP "AT" Command Set Capabilities ..........•................•............. 4-161
Section 5 - Image Modem Application Notes ............................ ;............. 5-1
R96FI/R96MD Modem Tone Detector Filter Tuning .................................... 5-3
R96FI/R96MD Modem Recommended Receive Sequence for Group 2 Facsimile ............. 5-9
DTMF Dialing Using the R96MD Modem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DTMF Dialing for R24MFX, R48MFX, R24BKJ, or R48BKJ .............................
R96MFX Modem Recommended Receive Sequence for Group 2 Facsimile ................
R96EFX HDLC Operation ...........................•...........................
R144HD DSP Programming Guide for the Host Computer ..............................
5-12
5-19
5-27
5-30
5-38
Section 6 - Digital Network Products ................................................ 6-1
Product Line Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
R8040 T-1 Tri-Port Memory ....................................................... 6-3
R8050 T-1 Serial Transmitter .............................................. , ....... 6-9
R8060 T-1 Serial Receiver ....................................................... 6-17
R8069 Line Interface Unit (LlU) ....... . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . .. 6-23
R8069A Enhanced T-1/PCM-30 Line Interface Unit (LlU) ...•........................... 6-46
R8070 T-1/CEPT PCM Transceiver .......................•........................ 6-47
R8070A T-1/CEPT PCM Transceiver .............................................. 6-93
R8071 ISDN/DMI Link Layer Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-94
R8075 CRC-4 Encoder/Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . .. . . . . . . . . . .. 6-144
RT9170 Intelligent T-1 Controller ....................•............................
R6551 Asynchronous Communications Interface Adapter (ACIA) .......................
R65C51 Asynchronous Communications Interface Adapter (ACIA) ......................
R65C52 Dual Asynchronous Communications Interface Adapter (DACIA) .................
6-162
6-165
6-185
6-206
R68C552 Dual Asynchronous Communications Interface Adapter (DACIA) ................ 6-225
R68560 Multi-Protocol Communications Controller (MPCC) ............................ 6-244
R68802 Local Network Controller (LNET) .......................................... 6-277
iv
TABLE OF CONTENTS (CONTINUED)
Section 7 - Digital Network Products Evaluation Tools .................................
R8069 Evaluation Board .........................................................
R8070 Evaluation Board .........................................................
R8071 Evaluation Board .........................................................
7-1
7-3
7-4
7-5
Section 8 - Digital Network Products Application Notes ................................ 8-1
R8069 Interface Transformer Specifications and Connections ............................ 8-3
Which Mode for Data Transmission? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-6
Monitoring and Controlling the Synchronization State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-8
Bipolar Violation/Loss of Carrier (RVLL) Signal Separation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10
Producing AMI Code from TPOS and TNEG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11
Zero Suppression Methods (B7, B8ZS and HDB3) .................................... 8-13
Finding the F-Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-16
D4/ESF Conversion Using the R8070 ........ . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-19
Loopback Testing with the RB070 ................................................. 8-23
Reporting Error Conditions in the RB070 . . . . . . . . . . .. . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-28
Receiver Synchronization in the R8070 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-32
Independent Channel Control for the R8070 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-42
Idle Code Generation ........................................................... 8-48
Alarm Handling in the RB070 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-52
An Off-Une Framer for the R8070 ...... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-55
Signaling Freeze with the R8070 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-60
Programming the R8071 ISDN/DMI Unk Layer Controller's Buffers ...... . . . . . . . . . . . . . . . .. 8-67
v
PART NOJDATA BOOK PAGE INDEX
R12121200 bps Full-Duplex Modem ........•..•..•...........•..............•..... 1-45
R144DP V.3314.4 kbps Full-Duplex Modem ••.•....•......•..•..•..............•... 2-78
R144HD 14400 bps Half-Duplex Modem •.... '" ................•........•......... 3-193
R1496DP V.3314.4 kbpsN.32 9600 bps Full-Duplex Modem ..•.............•.....•... 2-103
R208/201 4800 bps Modem.. . .. . .. .. . .. .. .. . . .. .. . . .. . .. . .. . . .. .. . .. . . . . . . . .. . . .. 2-3
R212AT Device Set "AT' Command Set Be1l212A Compatible .........•........•........ 1-5
R212DP Device Set Be1l212A Compatible ........................................... 1-3
R24/48MEB Modem Evaluation Board .......•.....••...................•.......... 3-67
R2424 2400 bps Full-Duplex Modem. . • . . . . • . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-74
R24BKJ 2400 bps V.26 bis Modem ••...........•...•.............................. 3-19
R24MFX 2400 bps MONOFAX Modem. . . • . . . . . . . . . • . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . .. 3-3
R48MFX 4800 bps MONOFAX Modem .......•.........•........................... 3-35
R48PCJ 4800 bps PC Communication Modem ..•............................•....... 3-51
R6551 Asynchronous Communications Interface Adapter (ACIA) .....................•. 6-165
R65C51 Asynchronous Communications Interface Adapter (ACIA) ...................... 6-185
R65C52 Dual Asynchronous Communications Interface Adapter (DACIA) . . . . . . . . . . . . . . . .. 6-206
R68560 Multi-Protocol Communications Controller (MPCC) ............................ 6-244
R68802 Local Network Controller (LNET) .......................................... 6-277
R68C552 Dual Asynchronous Communications Interface Adapter (DACIA) ....•........... 6-225
R8040 T-1 Tri-Port Memory ....................................................... 6-3
R8050 T-1 Serial Transmitter ...................................................... 6-9
R8060 T -1 Serial Receiver. . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-17
R8069 Line Interface Unit (LlU) •.......••.........•........................•...... 6-23
R8069A Enhanced T-1/PCM-30 Une Interface Unit (UU) .•............................. 6-46
R8070 T-1/CEPT PCM Transceiver ................................................ 6-47
R8070A T-1/CEPT PCM Transceiver .............................................. 6-93
R8071 ISDN/DMI Link Layer Controller . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-94
R8075 CRC-4 Encoder/Decoder .. . .. . .. . .. . .. . . . . . . . . . . . . . . . . . . .. . . . . . . . . .. . . . .. 6-144
R9696DP V.32 9600 bps Full-Duplex Modem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-215
R96DP 9600 bps Data Pump Modem .........•.................................... 2-26
R96EFX 9600 bps MONOFAX Modem with Error Detection ............................ 3-103
R96FI9600 bps Facsimile Modem ..••.•......................................... 3-157
R96FT 9600 bps Fast Train Modem ............................................... 2-47
R96FT/SC 9600 bps Fast Train Modem with Forward Secondary Channel ................. 2-63
R96MD 9600 bps Facsimile Modem .•........•................................... 3-175
R96MEB Modem Evaluation Board . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-128
R96MFX 9600 bps MONOFAX Modem . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-80
R96PCJ 9600 bps PC Communication Modem •.................................. '" 3-144
R96QT 9600 QuickTurn Modem ................................................. 1-187
vi
PART NO./DATA BOOK PAGE INDEX (CONTINUED)
RC224AT 2400 bps Modem Device Set with "AT" Commands ............................ 1-7
RC224EB 2400 bps Modem Evaluator Board for RC224AT ............................. 1-37
RC2324DP/DS 2400 bps Full-Duplex Modem Device Set ............................. 1-139
RC2324SME System Module ................................................... 1-176
RC2324SME/DS System Module Device Set ....................................... 1-186
RC2424DP/DS 2400 bps Full-Duplex Modem Device Set ............................. 1-103
RT9170 Intelligent T-1 Controller ................................................. 6-162
vii
MONOFAX is a registered trademark of Rockwellintemstional.
Microsoft Is a registered trademark of Microsoft Corporation.
HP and LaserJet are trademarks of Hewlett Packard.
Hayes Is a registered trademark of Hayes Microcomputer Products, Inc.
Smartcom Ills a trademark of Hayes Microcomputer Products, Inc.
Microcom Network Protocol and MNP are trademarks of Mlcrocom, Inc.
CROSSTALK is a registered trademark of Digital Communications Associatee, Inc.
viii
PRODUCT INDEX
Dial-Up Data Modems
•
~-----
1IEII
~L_e_a_se_d__L_in_e__D_at_a_M__o_d_em__s__________________________
Image Modems
L - - -_ _ _ _ _
•
II1II
~D_a_t_a_M_o_d_e_m__A_p_p_li_c_a_ti_o_n_N_o_t_es________________________
Image Modem Application Notes
•
'------------
~D_ig_i_ta_I_N_e_t_w_o_r_k_P_r_o_d_uc_t_s____________________________~
Digital Network Products Evaluation Tools
Digital Network Products Application Notes
ix
x
SECTION 1
I
I
Dial-Up Data Modems
Product Family Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-2
R212DP Device Set Be1l212A Compatible ........................................... 1-3
R212AT Device Set "AT" Command Set Bell 212A Compatible ........................... 1-5
RC224AT 2400 bps Modem Device Set with "AT" Commands ............................ 1-7
RC224EB 2400 bps Modem Evaluator Board for RC224AT . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-37
R12121200 bps Full-Duplex Modem ............................................... 1-45
R2424 2400 bps Full-Duplex Modem ............................................... 1-74
RC2424DP/DS 2400 bps Full-Duplex Modem Device Set .............................
RC2324DP/DS 2400 bps Full-Duplex Modem Device Set .............................
RC2324SME System Module ...................................................
RC2324SME/DS System Module Device Set .......................................
1-103
1-139
1-176
1-186
R96QT 9600 QuickTurn Modem ................................................. 1-187
R9696DP V.32 9600 bps Full-Duplex Modem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-215
1-1
~
DIAL-UP DATA MODEMS
EXPERIENCE MAKES A DIFFERENCE
Rockwell offers a complete line of 1200 to 9600 bits per second (bps) OEM modem products that can
easily be incorporated into your communications systems requiring high performance, quality and
reliability while maintaining a competitive cost advantage. Whether the modem application is for personal
computer communications or for installation into remote monitoring equipment, Rockwell has the product
with the features, form factor and cost advantage to meet your business objectives.
With the dial-up (PSTN) market advancing so quickly, time to market is critical. Rockwell offers a complete family of products that address every segment of the dial-up market. For the low power applications
such as laptops (battery powered), Rockwell offers the RC224AT, a complete single device modem, and
the RC2324DP, Rockwell's true quad function (V.21 , V.22A/B, V.22 bis, and V.23) modem. Rockwell also
provides products that easily assist you in migrating to higher speeds. The R96QT is a value added
V.22 bis modem that communicates at 9600 bps, and the RC9696DP is a "turbo charged" R9696DP with
fall-forward capability to 12000 bps full duplex operation. With throughput increasingly more critical over
dial-up lines, data compression and error correction protocols are crucial features. For integrated applications, Rockwell offers the RC224AT, which provides the "AT" command set, error correction and data
compression protocols in addition to standard modem features.
System designers now have a product line that completely meets their needs including a smooth migration path from all of Rockwell's current products to any future requirements.
Model
Data Speed
(bps)
Compliance
R212AT
1200,0-300
Bell 212A, 103; "AT" Command Set
R212DP
1200,0-300
Bell 212A, 103
R1212
1200,600,0-300
CCITT V.22 AlB; Bell 212A, 103
R2424
2400,1200,600,0-300
CCITT V.22 bis, V.22 AlB; Bell 212A, 103
RC224AT
2400,1200,600,0-300
CCITTV.22 bis, V.22 AlB, V.21; Bell 212A, 103;
"AT" Command Set
RC2324SME
2400,1200,600,0-300
CCITT V.22 bis, V.22 AlB, V.23, V.21, Bell 212A, 103;
V.25 bis Commands, "AT' Commands, MNP 3, 4, 5
RC2324DP
2400,1200,600,0-300
CCITT V.22 bis, V.22 AlB V.21 , V.23; Bell 212A, 103
R96QT
9600,7200,4800,2400,1200
600,300
V.29 (HDX). V.22 bis, V.22 AlB; Bell 212A, 103
1200,9600,4800,7200
V.32, V.22 bis, V.22, V.21 V.23; Bell 212A, 103
R9696DP
1-2
R212DP/DS and R212DP/EB
'1'
Rockwell
R212DP
Modem Device Set
Bell 212A Compatible
INTRODUCTION
FEATURES
The R212DP/DS Data Pump device set is a high performance
1200/300 bps modem. Using state-of-the-art VLSI technology,
the R212DP provides the entire modulation/demodulation
process, high and low band filtering, and complete auto dialing
function in only two devices.
• 2 DeVice Implementation
- R8200 Modulator/Demodulator
- 10468 Integrated Analog
The R212DP is ideal for data transmission over the 2-wire dial-up
network. Bell 212A and 103 compatible, the R212DP can handle
virtually all applications for full-duplex 1200 bps and 0 to 300 bps
asynchronous data transmission over the publiC switched
telephone network (PSTN).
The RS-232-C compatible interface integrates easily into a personal computer, box modem, terminal or any other communications product. The added feature of an integral asynchronous
serial auto dialer capable of dialing With DTMF tones or pulses
from its 40-byte character buffer offers the user added flexibility
in creating a 1200 bps modem customized for specific packaging
and functional requirements.
An R212DP/EB Evaluation Board IS also available to aid modem
system deSign and evaluation. Included on the pnnted Circuit
board are the R212DP/DS modem deVice set, RS-232-C connector, power connector, an RJ-11 phone jack, SIX LED indicators, and four configuration switches. The evaluation board
comes with an In-depth R212DP Device Set DeSigner's Guide
(Order No. 678) and a wall-mount power supply. All that is
required to use the R212DP/EB IS an RS-232-C cable connected
to a terminal or computer, and a phone cord.
• Bell 212A and 103 Compatible (2-Wlre Full-Duplex)
- Asynchronous
1200 bps DPSK (+1%, -2.5%)
0-300 bps FSK
Auto Fallback, Answer Mode
• DTE Interface
- Functionally: RS-232-C Compatible
- Electrically: TTL
• Auto/Manual Answer
• Auto/Manual Dial
- DTMF or Pulses
- 0-9 # ., T P CR (ASCII)
- 40-Byte Character Buffer
•
10-Bit Character Length
• Break Generation/Detection
• Send/Receive Space Disconnect
• Automatic Adaptive Equalizer
• Analog Loopback
- 0 to 300 bps, 1200 bps
• Packaging Options
- 40-pln PlastiC DIP
- 44-pln PLCC
40-PIN DIP
44-PIN PLCC
R212DP/DS Modem Device Set
Document No. 29220N77
Product Summary
1-3
Order No. 677
Rev. 2, February 1987
•
R212DP
Data Pump Modem Device Set
+SV
+SV
-sv
DTR
DCD
TxD
RxD
Ri_
CH
Ci
R8200-XX
OH
ORGIANS
10468-XX
}
TO
LINE
INTERFACE
o
Ai:--
MODULATORI
DEMODULATOR
DEVICE
INTEGRATED
ANALOG
DEVICE
R212DP/DS Modem Device Set Interface Diagram
SPECIFICATIONS
Environmental
Power Consumption
Temperature: Operating ooe to 70°C
Storage - 55°C to + 150°C
Relative Humidity: Up to 90% noncondensing. or a wet bulb
temperature up to 35°C, whichever is less.
+5 Vdc ±5% <300 mA
-5 Vdc ±5% <40 mA
600 mW (typical)
1-4
R212AT/DS and R212AT/EB
'1'
Rockwell
R212AT Modem Device Set
"AT" Command Set
Bell 212A Compatible
INTRODUCTION
FEATURES
The R212ATlDS ("AT" Command Set Compatible) device set
is a high performance 1200/300 bps modem. Using state-of-theart VLSI technology, the R212AT provides the entire modulation/
demodulation process, high and low band filtering, and an
enhanced "AT" Command Set in only two devices.
• 2 Device Implementation
- R8203 Modulator/Demodulator
- 10468 Integrated Analog
• Bell 212A and 103 Compatible (2-Wire Full-Duplex)
- 1200 bps DPSK ( + 1%, - 2.5%) asynchronous
- 0-300 bps FSK asynchronous
- Auto Fallback, Answer Mode
The R212AT is ideal for data transmission over the 2-wire dial-up
network. Be1l212A and 103 compatible, the R212ATcan handle
virtually all applications for full-duplex 1200 bps and 0 to 300 bps
asynchronous data transmission over the public switched
telephone network (PSTN).
• Auto/Manual Answer
The RS-232-C compatible interface integrates easily into a personal computer, box modem, terminal or any other communications product. The added features of the enhanced "AT"
Command Set offer the user added flexibility in creating a
1200 bps modem customized for specific packaging and functional requirements. The R212AT can be readily used with
industry standard communication software packages.
• Auto/Manual Dial
• "AT" Command Set (see reverse side)
• DTE Interface
- Functionally: RS-232-C Compatible
- Electrically: TIL
An R212AT/EB Evaluation Board is also available to aid modem
system design and evaluation. Included on the printed circuit
board are the R212AT/DS modem device set, RS-232-C connector, power connector, two RJ-11 phone jacks, 11 LED indicators, four configuration switches, and a speaker with volume
control. The evaluation board comes with a detailed R212AT
Device Set Designer's Guide (Order No. 686), and a wall-mount
power supply. All that is required to use the R212AT/EB is an
RS-232-C cable connected to a terminal or computer, and a
phone cord.
• Data Format
- 7 Data Bits; 1 or 2 Stop Bits; Even, Odd, or Fixed Parity
- 8 Data Bits; 1 or 2 Stop Bits; No Parity
• Automatic Adaptive Equalizer
• Packaging Options
- 40-pin Plastic DIP
- 44-pin PLCC
40-PIN DIP
44-PIN PLCC
R212AT/DS Modem Device Set
Document No. 29220N83
Product Summary
1-5
Order No. 683
Rev. 2, February 1987
•
R212AT
"AT" Compatible Modem Device Set
R212AT "AT" Command Set
Command
AT
AI
A
0
R
T
P
Sr?
Function
Command
Attention Code
Repeat Last Command
Answer
Dial
Reverse Dial
Tone Dial
Pulse Dial
Read Register
Sr=n
V
;
E
Function
Command
Set Register
Verbal/Numeric
Result Code
Pause
Return to Command
State After Dialing
Echo On/Off
H
I
M
0
Q
Z
+++
+5V
+5V
-5V
OSR
OTR
OCD
TxO
RxD
Ai
RB203-XX
1046B-XX
Ci
MR
AA
SPEAKER ON
}
TO
LINE
INTERFACE
0
MODULATOR/
DEMODULATOR
DEVICE
SPECIFICATIONS
Function
On/Off Hook
Returns Product Code
Speaker On/Off
On Line
Quiet On/Off
Reset
Escape Code
-=
INTEGRATED
ANALOG
DEVICE
R212AT/DS Modem Device Set Interfac.e Diagram
Environmental
Power Consumption
Temperature: Operating O°C to 70°C
Storage - 55°C to + 1S0°C
Relative Humidity: Up to 90% noncondensing, or a wet bulb
temperature up to 35°C, whichever is less.
+5 Vdc ±5% <300 mA
-5 Vdc ±5% <40 mA
600 mW (typical)
1-6
RC224AT
'1'
Rockwell
RC224AT 2400 bps Single Device Modem
with IIATII Commands
INTRODUCTION
FEATURES
No external microcomputer and PROM required
Built-in DTE interfaces supported:
Parallel 16C450
- Serial CCITT V.24 (EIA-232-D)
Implements new Hayes commands
&V, &Wn, &Yn, &Zn=x, and S=n as a dial
modifier
NVRAM interface allows storage of two user
configurations and four 36-digit dial strings
40-character command line
Automatic sleep mode and wake-up
Expansion PROM interface permitting usermodification of AT commands
Compatibilities
CCITT V.22 bis, V.22 AlB
Bell 212A and 103
Hayes "AT" 2400B and 2400 command set
Low power requirements:
305 mW (typical) operating
37 mW (typical) sleep (power down) mode
Call progress and dialing features:
Detect: busy, ringback and dial tone
Wait for quiet answer
Programmable speaker volume control
DTMF and pulse dial
Programmable pause interval
Flash PBX support
Wait for dial tone before dialing
Originate call from answer-mode modem
Automatic adaptive and fixed compromise
equalization
AlA1 feature for mUlti-line key telephones
RC224AT/1 (1 device) packaging
64-pin plastic QUIP
- 68-pin PLCC
RC224AT/2 (2-device set) packaging
DSP: 64-pin plastic QUIP or 68-pin PLCC
IA: 40-pin plastic DIP or 44-pin PLCC
-
The RC224AT is an integrated 2400 bps full-duplex
modem supplied in either one or two CMOS VLSI
packages. The RC224AT complies with CCITT V.22 bis
and V.22 AlB recommendations, and meets Be1l212A and
103 standards. The RC224AT also implements a 2400
"AT" command set.
Two versions of the RC224AT are available. The
RC224AT/1 integrates digital signal processing (DSP) and
integrated analog (IA) functions into a single VLSI
package.
The RC224AT/2 2-device set performs the same functions
as the RC224AT/1 single device with the addition of a
memory expansion bus. The RC224AT/2 supplies DSP
and IA functions in separate packages.
The RC224AT may operate over a parallel or serial
interface to the host. A hardware input selects either
parallel or serial host interface upon power tum-on or
reset. The parallel host interface emulates a 16C450
UART and is compatible with IBM PC, PC/XT, PC/AT, or
PS/2 systems. The serial host interface is CCITT V.24
(EIA-232-D) logic compatible with TIL levels.
RC224AT based modem designs reduce the bill of
material due to the elimination of an external
microprocessor and parallel/serial (UART) devices. This
results in significant cost savings for OEM customers.
Implemented in low power CMOS, the RC224AT is also
designed especially for portable and/or battery powered
applications. Power requirements are further reduced
when sleep (power down) mode is enabled.
The RC224AT is based on a new generation CMOS
microcontroller, the MicroDSP. The MicroDSP combines
the best features of an 8-bit microcomputer with a digital
signal processor. The MicroDSP enables the RC224AT to
handle traditional microprocessor functions, such as the
AT command interpretation, without degrading
performance in core modulation and demodulation of
digital signal processing functions.
Document No. 29200N54
Hayes
Data Sheet
(Preliminary)
1-7
IS
a registered trademark of Hayes Microcomputer Prcxlucts, Inc
Order No. MD54
Rev. 1, January 1989
•
RC224AT
2400 bps Single Device Modem with II A Til Commands
GENERAL DESCRIPTION
NVRAM Interface
The major hardware signal interfaces of the single-device
RC224AT/1 are illustrated in Figure 1-a. The major
hardware interface signals ofthe RC224AT/2 are shown in
Figure 1-b.
A serial interface to an optional user-supplied 1024-bit
non-volatile RAM (NVRAM) is provided, The NVRAM can
store up to two user-selectable cOnfigurations which can
take precedence over the factOry default setting, and can
store up to four 36-digit dial strings.
Additional design information is described in the RC224AT
Designer's Guide (Order No. 845).
Speaker Interface
An interface to an externally supplied speaker circuit is
provided. The speaker can be used to monitor call
progress. The AT Ln command can be used to adjust the
volume in suitable steps.
DEVICES
MlcroDSP
The MicroDSP is a medium speed modem engine offering
high speed central processing at a 6 MHz (internal clock)
instruction execution rate. The MicroDSP performs the
modem digital signal processing, command set
interpreting, line control, and modem control processing.
Two pulse rate multipliers optimize performance by
generating precision timing for the analog filters.
Expansion ROM Interface (RC224AT/2 Only)
An expansion bus is provided to interface with an optional
user-supplied 8k-byte PROM, as a user option. This
PROM can be used to alter the AT command set:
SLEEP (POWER DOWN) MODE
Integrated Analog
To minimize the modem power consumption, the
RC224AT includes a sleep (power down) mode which may
be enabled or disabled. If enabled, the RC224AT enters
sleep mode whenever the modem has been inactive from
30 seconds to one minute. (Note that the modem never
enters power down mode while in data mode.) The modem
returns to full operation whenever a ring ~ignal occurs, or
the host writes to the DSP (parallel interface) or the DTR
input is asserted (serial interface). In the serial interface,
the V.24 and indicator outputs are forced high in the sleep
mode to save power.
The integrated analog function is divided into three
sections: transmitter, receiver, and telephone line
interface. The transmitter section contains a
digital-to-analog (D/A) converter, bandsplit and lowpass
filters, a guard .tone generator, and a transmit level
attenuator. The receiver section implements variable gain
control, bandsplit filters, and an analog-to-digital (NO)
converter. The telephone interface circuitry provides relay
drivers for off-hook, talk/data, and NA1 relays.
SUPPORTED INTERFACES
TECHNICAL SPECIFICATIONS
"AT" Command Line
The selectable modem configurations, along with the
corresponding signaling (baud) rates and data rates, are
listed in Table 1.
A 40-character command line is provided. The command
line starts with AT and may contain several commands. A
separator is not required b~een the commands. The AT
prefix and the terminating CR prefIX are not counted in the
character total. Spaces are counted; as are left and right
parenthesis.
TONE GENERATION
DTMF Tone: A DTMF tone pair can be generated with an
frequency accuracy of ± 1.5%. The dial digit tone pairs are:
Dial Digit
0
1
2
3
4
5
6
7
8
9
Parallel Host Interface
When the parallel PC bus interface is selected by a
hardware input signal (use of HWT), a 16C450 compatible
parallel interface is provided.
Indicator Interface (Serial Interface only)
When the serial interface is selected, four signals are
by the DSP to the indicator interface (DCDL,
MRITEST, AAE, and OHRELAY). The 2-device
RC224AT/2 also outputs the DTRL indicator signal.
~ut
/I
A
B
Serial Host Interface
C
D
When the serial interface is selected by a hardware input
signal (SEREN = GND), a V.24 (EIA-232-D) compatible
interface is provided.
1-8
Tone 1
941
697
697
697
770
,770
770
852
852
852
941
941
697
770
852
941
Tone 2
1336
1209
1336
1477
1209
1336
1477
1209
1336
1477
1209
1477
1633
1633
1633
1633
2400 bps Single Device Modem with II A Til Commands
RC224AT
.-
RC224ATI1 DEVICE
I
DIGITAL
SIGNAL
PROCESSOR
(MICAODSp)
---
~
I
J
3~
SPEAKER
INTERFACE
3
2
~l
4
SERIAL
INTERFACE
I
1
ANTIALIASING
FILTER
COMPONENTS
ANCILLARY
CIRCUIT
INTERFACE
2
INDiCAlOR
INTERFACE
V.24
EIA-232-O
INTERFACE
2
INTEGRATED
ANALOG
(IA)
3
r=
TELEPHONE
LINE
INTERFACE
(OM)
I
I
I
NVRAM
INTERFACE
I
ANTIALIASING
FILTER
COMPONENTS
I
I
ANCILLARY
CIRCUIT
INTERFACE
I
SPEAKER
INTERFACE
I
I
a. Serial Host Interface
RC224ATI1 DEVICE
DIGITAL
SIGNAL
PROCESSOR
(MICAODSp)
----
2
HOST
PROCESSOR
PARALLEL
BUS
~
,2
INTEGRATED
ANALOG
(IA)
"-
"
j
16C450
INTERFACE
3~
I
3
I
NVRAM
INTERFACE
b. Parallel Host Interface
Figure 1-a. RC224AT/1 General Interface
1-9
TELEPHONE
LINE
INTERFACE
(DAA)
2400 bps Single Device Modem with II AT" Commands
RC224AT
AC224AT12 DEVICE SET
•
•
•
DIGITAL
SIGNAL
PIIOCES8OR
------ ~
(IIICIIOD8P)
INDlCII10R
INTERFACE
V.24
_oil
2
INTEGRATED
ANTIAUASING
IINIII.OG
VA)
COMPONENTS
FlIl'ER
-'-
~1
SERIAL
INTEAIWlE
TELEPHONE
LINE
INTEIIFM:E
(DIIII)
ANCII.LIIIIV
CIRCUIT
INTERFACE
2
4
2
t=
~
3
I
SPEAKER
INTEAFM:E
3
4
J
INTERFACE
...
NVRAM
INTEAIWlE
EXPANSION
IUS
...
INTERFACE
"
a. Serial Host Interface
.
AC22411TI2 DEVICE SET
•
DIGITAL
SIGNAL
PIIOCEIIBOII
(MICRODSP)
-----HDST
PROCESSOR
PARALLEL
IUS
•
¢:::)
INTEGRATED
ANALOG
VA)
~
2
111C48O
FlIl'ER
COIIPQNENTS
~
3
I
SPEAKER
INTERFACE
3
I
...
"
NVRAM
INTEAFM:E
-
EXPANSION
INTERFACE
b. Parallel Host Interface
Figure 1·b. RC224AT/2 Generallnlerface
1-10
TELEPHONE
LINE
INTEAIWlE
(DAII)
ANCILLARY
CIRCUIT
INTERFACE
"INTERFACE
IINT1ALIllSlNO
2400 bps Single Device Modem with" AT" Commands
RC224AT
Guard Tone: A guard tone of 550 :I: 20 Hz or 1800 :I: 20 Hz
can be generated at 3:1:1 dB or 6:1:1 db below the transmit
i
RECEIVER TIMING
Answer Tone: A CCITT (2100 :1:15 Hz) or Bell (2225 :1:10
Hz) answer tone is generated depending on the selected
configuration.
CARRIER RECOVERY
The modem can track a frequency offset up to:l:7 Hz in the
received carrier with less than a 0.2 dB degradation in bit
error rate (BER).
DATA ENCODING
The data encoding conforms to CCITT Recommendations
V.22 bis or V.22, or to Bell 212A or 103, depending on the
selected COnfiguration.
TRANSMISSION SPEED
With the parallel interface, the transmission rate of the host
computer must be 110, 300, 1200, or 2400 bps. The
modem will connect at the selected speed or will fallback
to the speed set by the remote modem with the serial
interface, the DTE transmission speed is speed sensed.
LINE EQUALIZATION
Transmitter and receiver digital filters compensate for
delay and amplitude distortion during operation on
nominal phone lines. In addition, automatic adaptive
equalization in the receiver minimizes the effects of
intersymbol interference.
TRANSMITTED DATA SPECTRUM
When the modem answers a call, it determines the
transmission speed from the carrier signal of the
originating modem. V.22 bis ORG can also adapt so that
the setting of the modem is matched to the remote system.
The transmitted spectrum is shaped by the square root of
AT COMMAND SET
a 75% raised cosine filter function.
The AT command set is Hayes 2400B compliant. The
commands are divided into three types; basic commands,
dial modifiers, and ampersand commands as listed in
Table 2. The supporting S registers are listed in Table 3.
mANSMIT LEVEL
The transmitter level is -10 dBm :1:1 dB.
SCRAMBLEFVDESCRAMBLER
AT COMMAND DATA RATE
The modem incorporates a self-synchronizing
scrambler/descrambler in accordance with the applicable
CCITT recommendation.
With the parallel interface, AT commands to the modem in
the local command state must be asynchronous, ASCII
coded, and transmitted at rates of 110, 300, 1200, or 2400
bps. With the serial interface, the rate is speed sensed for
parity and format.
RECEIVE LEVEL
The receiver satisfies performance requirements for a
received line signal from -9 dBm to -43 dBm. The carrier
detect is ON at -43 dBm and OFF at -48 dBm with a
minimum of 2 dB hysterisis.
Table 1. Configurations, Signaling Rates and Data Rates
Contlguration
Modulationt
Tranamltter C.rrI.r
_ _r
FreqlltlllCY (Hz) =0.01 ""
onglnat.
Oata Rat.
(bps)
Baud
(Symbols/Sec.)
Bits Par
Symbol
Con.tall.llon
",0.01""
Point.
V.~bI.
CAM
2400
1200
2400
600
4
16
V.22A/B
DP8K
2400
1200
1200
600
2
4
Ba1l212A
OPSK
2400
1200
1200
600
2
4
Bs11103
FSK
300
300
1
1
Not..:
2225M
20258
1270 M
10708
1.
Modulation lagend:
2.
M Indicalaa • mark condition, 8 indicetes • apsce condition.
QAM
DPSK
FSK
I
The modem can track a frequency error up to :1:0.01 % in
the associated transmit timing source.
level, respectively.
Quadrature Amplitude Modulation
Differential Ph_ Shift Keying
Frequency Shift Keying
1-11
•
RC224AT
2400
bps~Single
Table 2. RC224AT "AT" Command Set Summary
Basic
Commands
AT
A
AI
'Bn
C1
0
En
F1
Hn
In
Ln
Mn
On
P
Qn
Sn
Sn=
Sn?
T
Vn
Xn
Yn
Zn
+++'
,
P
R
S=n
T
W
@
I
0-9
A,B,C,D
Table 3. RC224AT S Register Summary
Function
Attention Code
Answer Command
Repeat Last Command
Communications Standard Option
Carrier Control Option
Dial Command
Off-line Character Echo Option
On-line Character Echo Option
Switch Hook Control Option,
Identification/Checksum ~ptlon
Speaker Volume Option
Speaker Control Option
On-line Commard
Pulse Dla~
ResuH Code Display Option
Selact an S Register
Write to an S Register
Read an S Register
Touch Tone Dial
ResuH Code Form Option
ResuH Code Set/Call Progress Option
Long Space Disconnect Option
Recall Stored Profile Command
Escape Code Sequence
Pause
Dial
Modifiers
Function
&Wn
&Xn
&Yn
&Zn=x
Ring to Answer On
Rlng'Count
Escape Code Character
Carriage Return Character
Line Feed Character
Back Space Character
Wait For Dial Tone
Wait Time for Data Carrier
Pause Time for Comma
Carrier Detect Response Time
Lost Carrier to Hang-up Delay
DTMF Dialing $peed
Escape Code Guard Time
Bit Mapped Options Register
Modem Test Options
Test Timer
Bit Mapped Options Register
Bit Mapped Options Register
Bit Mapped Options Register
Delay to DTR
RTS to CTS Delay Interval
Bit Mapped Options Register
HARDWARE INTERFACE SIGNALS
The RC224AT/2 pin assignments are shown in Figure 4
and listed in Table 5. The RC224AT/2 interface signals are
shown in Figure 5.
Function
Data Carrier Detect Option
Data Terminal Ready Option
Load Factory Defaults
Guard Tone Option
Auxiliary Relay Control
Communications Mode Option
Make to Break Ratio Selection
Communications Mode Option
Data Set Ready Option
Test Command Selection
View Active Configuration and User
Proflles*
Stors Active Profile*'
Synchronous Transmit Clock Source
Option
Select Stored Profile on Powerup Optlon*
Store Telephone Number (n=0:3)*
Function
SO*
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S14*
S16'
S18*
S21*
S22*
S23*
S25*
S26*
S27*
The RC224AT/1 pin assignments are shown in Figure 2
and listed in Table 4. The RC224AT/1 hardware interface
signals are shown in Figure 3.
N,*
&Cn
&Dn
&F
&Gn
&In
&Mn
&Pn
&Qn
&Sn
&Tn
&V
Register
Notes:
*This S-Reglster Is stored In the modem NVRAM upon
receipt of the &W command so that the contents are
preserved when modem power ,is removed.
Pulse Dial
Originate Call In Answer Mode
Dial Stored Number (n=0:3)*
Touch Tone Dial
Walt for Dial Tone
Return to Idle State
Wait for Quiet Answer Command
Flash Hook
Pause
Dial Digits/Characters
Ampersand
Commands
Device Modem with "AT" Commands
The RC224AT/1 and RC224AT/2 digital and analog
characteristics are described in Tables 6 and 7,
respectively.
The RC224AT hardware interface signals are described in
Table 8. The signal definitions apply to both RC224AT/1
and RC224AT/2 except as noted.
APPLICATION
, Recommended modem circuits based on the RC224AT/1
are shown in Figures 6-a and 6-b for serial and parallel
interfaces, respectively.
Recommended modem circuits based on the RC224AT/2
are shown in Figures 7-a and 7-b for serial and parallel
interfaces, respectively.
* = New Commands
1-12
2400 bps Single Device Modem with" AT" Commands
RC224AT
SPARE
iEiiEri
iiiii/lDLE
NVRCS
NVRDIO
ME
1l.KRELAY
SPARE
RlCD
iiEiiiT
o.VDC
NVR9K
SPARE
SPARE
'iiiii
iPKiiii
iiPKiiL
MIlA
MISA
MDA
OHRELAY
-WA
Mno
Mitt
AGNDt
MICS
DONDt
TRANOUT
MDS
MI2S
+IVA
MilS
62
61
-
60
59
CiiHs
64
1.
2
3
4
5
6
7
iiCii[
iii
9
to
tl
12
t3
Ciii
t5
t6
t7
t8
19
20
21
50
IAEN
MICA
MltA
MI2A
Ml7A
MIlA
MISS
48
47
48
45
44
22
23
43
42
4t
40
26
27
28
39
38
37
29
36
30
35
31
34
32
33
oSVOC
xn.o
HINT
HDIS
lLKRELAY
NVRDIO
xnJ
49
24
25
iiEiiEi'
xn.o
'iiSi
HD7
HOI
HOI
HIM
HD3
HOI
HOt
HDO
DOND3
DOND2
i
IOLEN
N_
DSR
DGND3
DOND2
51
iiiiii
HAG
HAl
DCO
53
52
14
NVRCS
HA2
MR
5&
57
5&
55
54
8
iiiiii
iiW'i'
Hci
IDLEN
63
xnJ
'iiSi
IAEN
iPKiiii"
MICA
MilA
MI2A
MI7A
MIfA
MISS
MI7S
MISS
MilS
Mlt4
Mite
AGND3
Mltl
RECOUT
RECIN
SIAS
AGND2
SPKRL
MIfA
MlSA
MI3A
0iiiiELAY
-WA
MilO
Milt
AGNDt
II17lI
MI8S
MISS
Mite
Mit.
AGND3
Mlt5
RECOUT
RECIN
SIAS
AGND2
4t
40
39
MI4S
38
37
DONDt
TRANOUT
MI3S
MI2S
+5VA
36
35
34
MilS
33
Serial Host Interface
Parallel Host Interface
64-PlnQUIP
~
~I Uill~~'~~I~~!!lel~1
1~~i~I~II!~n~iU~~1
G.~.~~~N_.~.~.~N_
iii
lUCREI.AY
SI'!IIIi
-B!!R
CDCDCDCDCDIDCDCI
•
IlESIT '
+SVDC
IMISK
~.~.~.ftN_m~.~.~N_
60
59
58
57
56
55
54
SPARI!
SPB
53
52
11!15!!!!
8PKAL
MIlA
MIlA
MIOA
MIlA
MI7A
50
51
-..ll!R
49
4.
47
4&
45
44
DGNDO
X1LO
a:>CI CD CD CD fDCDCD 60
•
HA'
HAG
mL
IDLEN
TUT
1M!!!!
4Z
59
5&
57
5&
55
54
53
IIESET
lYlL-
oSVOC
OHRElAY
HINT
11158
III7B
HIllS
52
51
1IJCRELAY
MIlS
MIlS
tm!!!!2
50
49
48
47
45
45
44
!!f!!!!!!
III••
SPKRI..
MIOA
MlSA
11'1.
AGNo.
11115
AECDUT
IlIOA
IlISA
I1I7A
H.c.
~.mO_N~W~CD~.~O_N"
NNN"""""""""" ••••
~=~g"~~~==~==~;~~
1~$~iEoloal~~~S;~
•••
-t-§z· -!mM
222
l~i~~EDI~~!~~~~~~
~
Serial Host Interface
22!2
8
i
2 • • • ~m~
Parallel Host Interface
68-Pln PLCC
Figure 2. RC224AT/1 Pin Assignments
1-13
DGNDZ
X1LO
XD.I...
1BT
4Z
lYlLOHREI.AY
MIlS
MI78
MI88
11188
lin-
11111
AGND.
11115
AECOUT
N.c.
2400 bps Single Device Modem with II A Til Commands
RC224AT
Table 4-a. RC224AT/1 Pin AsslgnmentsoSerlal
68.pln PLCC
Pin Number
64-PlnQUIP
Pin Number
Signal
Label
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
1
2
3
4
5
....am...
....m;FIEN
-6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
20
54
30
21
31
23
24
25
22
32
33
34
35
36
26
27
28
29
30
37
36
39
31
40
32
41
42
43
44
45
33
34
35
-
36
46
37
47
36
46
39
49
40
50
41
51
42
43
52
53
25
28
44
45
46
27
28
47
48
49
29
55
50
-
56
57
51
56
59
52
53
54
55
60
61
62
63
64
56
57
65
66
67
59
58
AJA1
IA
IA
IA
OA
IA/OA
....B2W...
RESET
+SVDC
IB
tflBlZK
OA
ME
~Y
F\QQI.K
~
TCQJ.K
...mL
SfKBI:I
SPKRL
MI6A
MISA
~
OHRELAY
-5VA
MilO
Mill
AGNOl
MI4B
DGNOl
TRANOUT
MI3B
MI2B
+5VA
MllB
AGND2
BIAS
RECIN
N,C.
RECOUT
MI15
AGND3
MI16
MI14
MI6B
MI8B
MI7B
MI5B
MI8A
MI7A
MI2A
MilA
MI4A
IAEN
J2...
TEST
Xlli
X110
DGND2
IA
OA
IA
~
~
..tl90
61
-BL
J,4B
OCOL
68-Pln PLCC
Pin Number
64-PlnQUIP
Pin Number
Signal
Label
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
1
2
3
4
5
.I::IBC.
I::I.WI
OA
OA
20
TOMI6B
TOMI5B
'TOMI3B
00
22
-6
7
8
9
10
11
12
13
14
15
16
17
18
19
21
TOMI4A
23
24
20
54
30
21
22
31
23
32
24
33
25
26
.34
35
36
0(00)
TOMI3A
TOMI2A
27
28
29
30
37
38
39
31
TOMI1A
40
41
33
34
I (DB)
42
43
o (DA)
44
45
32
35
-
36
46
37
47
48
49
36
39
40
TOMI6A
TOMI8A
TOMI7A
TOMI5A
TOMI8B
TOMI7B
TOMI2B
TOMI1B
TOMI4B
OA
50
41
51
42
43
OA
56
57
52
53
25
26
44
45
46
47
48
49
27
28
29
55
IA
IE
OB
50
-
51
52
53
54
55
58
59
60
0~3
QILI:IS
f:&l
62
63
64
VOTypa
OA
OA
OA
OA
OA
-
60
88
1
OTRIIOLE
NVRCS
~O
Table 4-b. RC224AT/1 Pin AsslgnmentsoParallel
61
OA
56,
62
63
64
OA
OA
OA
57
56
59
65
66
67
IA
OA
OA
-
60
88
HCS
NVRCS
~
AlAl
HAl
HAO
10LEN
~
RESET
+5VOC
HINT
HOIS
llKRELAY
~
SfKBI:I
SPKRL
MI6A
MISA
~
OHRELAY
-SVA
MilO
MI11
AGNOl
MI4B
OGNOl
TRANOUT
MI3B
MI2B
+5VA
MllB
AGND2
BIAS
RECIN
N.C.
RECOUT
MI15
AGND3
MI16
MI14
MI6B
MI8B
MI7B
MI5B
MI6A
MI7A
MI2A
MilA
MI4A
IAEN
J2...
TEST
Xlli
X110
DGND2
OGN03
HOO
HDl
HD2
I:IDa
NMI
HD4
H05
HD6
110 Type
IA
IA
IA
OA
IA
OA
IA
IA
I
OA
IA
IA
OA
OA
OA
IA/OA
OA
OA
TOMISB
TOMI5B
TOMI3B
00
TOMI4A
0(00)
·TO MI3A
TOMI2A
TO MilA
I (DB)
o (DA)
TOMI6A
TOMI8A
TOMI7A
TOMI5A
TOMI8B
TOMI7B
TOMI2B
TOMI1B
TOMI4B
OA
OA
IA
IE
OB
IAlOA
IA/OA
IA/OA
IA/OA
IA
IA/OA
IA/OA
IA/OA
IA/OA
IA
61
1
62
63
2
J::1QZ..
RING
3
64
Notes:
1. MI Modem Interconnection (e.g., MI7), see Figure 3.
2. N.C. No Connection, leave pin disconnected (open).
3.. I/O types are described In Table 6 (digital signals) and in
Table 7 (analog signals).
OA
2
IA
I~
3
RING
IA
Notes:
1. MI Modem Interconnection (e.g., MI7), see Figure 3.
2. N.C. No Connection, leave pin disconnected (open),
3. I/O types are described in Table 6 (digital signals) and In
Table 7 (analog signals).
=
=
=
=
1-14
2400 bps Single Device Modem with" AT" Commands
RC224AT
TRAN OUT
XTLI
ANTIALIASING
FILTER
COMPONENTS
REC OUT
CRYSTAL
RECIN
XTLO
OHRELAY
'-1
OHRELAY
DCDL
MRJTEST
AAE
INDICATOR
INTERFACE
TLKRaAY
~
ANCILLARY
SUPPORT
CIRCUITRY
IDLEN
IAEN
AlA1
RING
RC224ATI1
RXD
CI/HS
SPKREN
DCD
SPKRH
DSR
SPKRL
-
SFEAKER
RI
V,24
EIA-232-D
INTERFACE
NVRCS
CTS
NVRSK
NVRDIO
NVRAM
'--=-
TXD
DTR
+5V
f
~
RESET
Figure 3-a. RC224AT/1 Interface Signals-Serialinterface
1-15
..!2....
.,!!l!A.
TaEPHONE
LINE
INTERFACE
(OM)
RC224AT
2400 bps Single Device Modem with " AT" Commands
TRAN OUT'
XTLI
ANTIALIASJNG
FILTER
COMPONENTS
RECOUT
CRVSTAL
RECIN
XTLO
OHRELAY
HOIS
tICS
HAD
HWT
HINT
TLKRELAY
HAD
HA2
HOST
COMPUTER
PARALLEL
BUS
ANCILLARY
SUPPORT
CIRCUITRY
IOLEN
HA1
RC224AT/1
IAEN
AJA1
HOG
HD1
RING
H02
HD3
HD4
SPKREN
SPKRH
HD5
SPKRL
HD6
HD7
-
NVRCS
NVRSK
NVROIO
RESET
SPEAKER
NVRAM
~
Figure 3·b. RC224AT/1 Interface Signals.parallelinterface
1·16
~
~
TELEPHONE
UNE
INTEIIRICE
(OM)
2400 bps Single Device Modem with II AT" Commands
RC224AT
IAEN
...
64
Mil
XIU
62
61
60
59
58
57
5&
55
54
53
X1LO
52
+5VDC
DONO
DONO
OSR
51
50
49
48
47
RiNo
Mil
MI3
iiCiiL
iffii[
EiiW'i
EBRD
EBALE
Cii
iiCii
Al
/IIJ
OT/Al1
DBlAl0
DBlAI
DBlAI
D3/A7
SPKRL
SPKRH
AlAI
AAE
NVROI
Mil
:rr
DTR
36
35
34
33
iEiiEii
SPARE
NVRDO
EiiRii
EBALE
XIU
XILO
+5VDC
DONO
DONO
HDO
HOI
HDZ
HD3
HD4
H05
HD&
HOT
H/IIJ
HAl
HAl
SPARE
HCS
DZlAB
DOIM
DONO
+5VDC
+5VDC
iiESEi
Ml2
MI7
EBCSZ
EiiCSi
SPARE
iiXD
SPKREN
SPARE
SPARE
iXii
NVRSK
NVRCS
Al
/IIJ
OT/Al1
DBlAl0
DS/AI
D4/AI
D3/A7
54
53
52
DZlAB
51
50
49
48
47
46
45
44
01/AS
DOIM
DONO
+5VDC
+5VDC
iiESEi
MIZ
MI7
43
EBCSi
42
41
40
39
24
25
26
Z7
28
29
30
31
32
Serial Host Interface
AI
55
ZO
Z1
NVRDO
Mil
A12
A3
5&
22
Z3
iiWf
HRii
MI4
63
62
61
60
59
58
57
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
HotS
HINT
EBWT
D1/AS
45
44
43
42
41
40
39
38
iii
Mil
MI3
AI
1111
64
1.
2
Mil
IDLEN
RING
A12
A3
48
CVtts
MR/TEST
IAEN
"1
MI4
63
IDLEN
EBCSI
SPKREN
SPKRH
SPKRL
38
:rt
Mil
36
35
34
33
AlAI
NVRDI
NVRSK
NVReS
Parallel Host Interface
II4-Pln QUIP
=
EBALE
X1U
X1LO
+5VDC
DOND
1
~
8PKJII.
.
N.e.
~~~O~~~N_~~~~~~N_
m~~O~~MN_=~I~:=~~
10
11
12
13
14
15
16
17
18
19
20
60
59
58
57
56
55
54
53
52
51
50
•
Z1
49
22
23
24
25
26
48
47
48
45
44
~m~O_N~.~O~
N.e.
~
D7/A11
EBALE
X1U
X1LO
+SYDC
D8/A1.
D5/AI
D4/AI
D3/A7
D2IAI
DI/AS
DOIA4
DONO
DONO
HDO
HDI
HOZ
HD3
-
DOND
+SYDC
.RESET
HDtI
1112
HDI
~
EBCSI
HD7
N.c.
•
59
58
57
5&
55
54
53
52
51
50
Z1
49
22
23
24
25
26
48
47
46
45
44
~=~~~~~~~=~=~~;~~
• • O_N~
NNN~~ft~""""""
oooooooo~
10
11
12
13
14
15
16
17
18
19
20
••••
Serial Host Interface
Parallel Host Interface
611-PlnPLCC
Figure 4-8. RC224AT/2 Pin Asslgnments-DSP Device
1-17
N.c.
OJ/A11
DIIA10
DSlAi
D4/AI
D3/A7
D2IAI
DI/AS
DO/A4
DGND
+5VDC
~
AESET
II..
EBCS1
RC224AT
2400 bps Single Device Modem with" AT" Commands
M_
Ilne
.1.
.tvA
1111
AOND3
1111
IIns
1117
IIn2
AGNDe
RECOUT
DGND2
REC.,
BIAS
1111
AGND2
-&VA
iiEiETTC
lin
.tvA
POR
1112
lilt
illS
11111
TRANOUT
lLKRElAY
0iiiiEiAY
11117
11111
OGNDI
OGND3
AGNDS
1114
-&VA
.10
lin 3
11111
AGNDI
4O·PIN DIP (lA)
.. ~ .!C~"N
~5Ii~~i~~ii
CD""''''W_::~~:;:
1117
AONDe
OGND2
IllS
-&VA
RESETTC
POii
1111
IInI
lLKRElAY
OHRELAY
7
•
39
38
37
36
35
34
33
32
31
30
29
10
11
12
13
14
15
16
17
!I.e.
RECOUT
RECIN
BIAS
AGND2
lin
+IVA
1112
illS
TRANOUT
IIn7
:!=~ft==~=~t:;=
HI!C~E!i"I21!i~
.g~:I:I~i
!gZ
44·PIN PLCC
Figure 4-1». RC224AT/2 Pin As8lgnments·1A Device
1e18
2400 bps Single Device Modem with " AT" Commands
RC224AT
Table 5-b. RC224AT/2 DSP Pin Asslgnments-Parallel
Table 5-a. RC224AT/2 DSP Pin Assignments-Serial
aa.pln PLCC
Pin Number
64.pln QUIP
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
17
18
19
-9
10
11
12
13
14
15
16
17
Signal
Label
IAEN
MI5
OA
I~
IA
IA
RING
MI8
Jm...
QQQl.
DTRL
~
Eem
EBRD
EBALE
Xlll
X1l0
+5VDC
DGND
Q!.lliD
~
.Qli
20
18
19
21
20
~I/HS
22
21
23
24
25
22
23
MRm:ST
RI
SPKRL
SPKRH
26
24
-
27
28
25
29
27
28
30
31
32
33
26
29
34
30
31
32
35
33
36
37
34
38
39
40
35
36
37
J2PD
AIA1
AAE
NVRDI
~
--t:lIB-
SEREN
SPARE
NVRDO
NVRCS
N:iBSK
TXD
SPARE
SPARE
S~N
38
39
42
40
RXD
SPARE
-
...N&....
45
46
41
42
43
44
47
48
49
46
50
47
51
48
49
50
52
53
54
55
45
51
56
52
53
57
54
58
55
59
56
60
-
61
57
62
63
64
65
66
67
66
58
59
60
61
62
63
64
OA
OA
OA
OA
OA
IE
OB
~
EBCS2
MI7
-M!L
RESET
+5VDC
+5VDC
DGND
DO/A4
Dl/A5
D2/A6
D3/A7
D4/A8
D5/A9
D6/Al0
D7/Al1
N.C.
AO
Al
A2
A3
A12
MI6
MI4
Mil
68.pin PLCC
Pin Number
64-PinQUIP
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
17
OA
OA
OA
OA
18
19
20
21
-
9
10
11
12
13
14
15
16
17
18
19
20
OA
22
21
OA
OA
OA
23
24
25
23
24
26
-
OA
OA
OA
27
28
25
29
27
28
29
30
31
32
33
34
35
36
37
N&..
41
43
44
110
Type
30
31
32
33
34
35
36
37
IA
IA
IA
IA
OA
OA
IA
OA
IA
OA
OA
OA
38
39
40
41
42
43
44
45
46
47
OA
OA
IB
39
-
49
46
50
47
48
49
50
51
54
55
56
52
53
58
54
55
59
56
57
60
-
61
67
57
58
59
60
61
62
63
68
64
62
63
64
65
66
NOTES:
1. MI = Modem Interconnection (e.g., MI7), see Figure 3.
2. N.C. = No Connection, leave pin disconnected (open).
3. I/O types are described in Table 6 (digital signals) and in
Table 7 (analog signals), respectively.
38
40
48
53
OA
OA
OA
OA
OA
26
41
42
43
44
45
51
52
IAlOA
IAlOA
IAlOA
IAlOA
IAlOA
IAlOA
IAlOA
IAlOA
22
Signal
Label
IAEN
MI5
OA
I~
IA
IA
RING
MI8
MI3
HDIS
HINT
~
Eem
EBRD
EBALE
Xlll
X1l0
+5VDC
DGND
DGND
HDO
HDl
HD2
HD3
HD4
HD5
HD6
HD7
N.C.
HAO
HAl
HA2
SEARE
~
l:M'I
HRD
NVRDO
NVRCS
NVRSK
N.YBQI
AlAl
MI9
SPKRL
SPKRH
SPKREN
...N&....
~
EBCS2
MI7
OA
OA
OA
OA
OA
IE
OB
IAlOA
IAlOA
IAlOA
IAlOA
IAlOA
1A/0A
IAlOA
IAlOA
IA
IA
IA
IA
IA
IA
IA
OA
OA
OA
OA
OA
OA
OA
OA
OA
-M!L
RESET
+5VDC
+5VDC
DGND
DO/A4
Dl/A5
D2/A6
D3/A7
D4/A8
D5/A9
D6/Al0
D7/All
N.C.
AO
Al
A2
A3
A12
MI6
MI4
Mil
IB
IAlOA
IAlOA
IAlOA
IAlOA
IAlOA
IAlOA
IAlOA
IAlOA
OA
OA
OA
OA
OA
NOTES:
1. MI = Modem Interconnection (e.g., MI7), see Figure 3.
2. N.C. = No Connection, leave pin disconnected (open).
3. I/O types are described in Table 6 (digital signals) and in
Table 7 (analog signals), respectively.
1-19
i
VO
Type
•
RC224AT
2400 bps Single Device Modem with" AT" Commands
Table s.c. RC224AT/2 IA Pin Assignments
44-Pln PlCC
Pin Number
1
2
~
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
36
39
4CJ.Pln DIP
Pin Number
-1
2
3
4
-
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
-
26
27
28
29
30
31
32
33
34
35
-
40
36
41
37
42
43
36
44
40
39
SIgnal
Label
N.C.
AGND4
MI14
MJ6
MJ8
N.C.
MI7
AGND6
DGN02
MI5
~
RE~TC
FOR
110
Type
IA
IAJOA
MI9
MI18
UKBEI.8Y
OHRELAY
MI19
OGN03
-SVA
MilO
Mill
AGNOl
MI13
MI4
AGN05
OGNOl
N.C.
MI17
TRANOUT
MI3
MI2
+5VA
Mil
AGN02
BIAS
RECIN
RECOUT
N.C.
MI12
MI15
AGN03
+SVA
MI16
00
00
0(00)
I (DB)
O(DA)
LEGEND:
1. MI g Modem Interconnection (e.g., MI7), see Figure 3.
2. N.C. = No Connection, leave pin disconnected (open).
1-20
2400 bps Single Device Modem with" AT" Commands
RC224AT
RCZ24AT/Z DEYICE SET
MODEM
INTERCONNeCT
LINES
XTLI
CRYSTAL
TRAN OUT
XTLO
ANTI ALIASING
FILTER
COMPONENTS
REC OUT
Mil
MIZ
REC IN
~
~
MI3
TELEPHONE
LINE
INTERFACE
(OAA)
0HiiELAY
MI4
RC224AT/2
IA
MIS
MIS
:...I
MI7
MI8
Mig
+SY
I RESETTC
RESET
TLKRELAY
f
ANCILLARY
SUPPORT
CIRCUITRY
POR
IDLEN
IAEN
A1Al
OHRELAY
RING
OTRL
MR/TEST
AAE
INDICATOR
INTERFACE
SPKREN
DCDL
SPKRH
SPKRL
P-
NYRCS
NYRSK
RXD
CitHS
DCD
V.Z4
EJA.232.D
INTERFACE
SPEAKER
J
RC224AT/2
MICRODSP
NVRDI
NYRDO
EBCS2
DSR
EBWT
DO/A4
RI
Dl/AS
CTS
NVRAM
D2/A6
D3IA7
EYE
PATTERN
GENERATOR
D4/AB
TXD
DSIAB
D6/Al0
D7/A11
DTR
AO
b
~
EXPANSION
ROM
INTERFACE
Al
A2
IU
A12
Eiii!j
EBALE
Figure 5-a. RC224AT/2 Interface Signals-Serial Interface
1-21
2400 bps Single Device Modem with II AT" Commands
RC224AT
IIC224ATI2 DEVICE SET
A
MODEM
INTERCONNECf
Mil LINES
XTLI
CRYSTAL
XTID
TRAN OUT
RECOUT
RECIN
1111
1113
1114
ANTIALIASING
FILTER
COMPONENlS
~
~
TELEPHONE
LINE
INTERFACE
(DAAI
OHRELAY
illS'
1IC224ATI2
IA
1118
1117
1118
lilt
TLKRELAY
ANCILLARY
SUPPORT
CIRCUITRY
~
IOLEN
IAEN
m
RiNG
SPKREN
SPKAII
SPKRL
NVIICS
NVRSK
NVRDI
NVRDO
RC224ATI2
IIICROOSP
HDIS
HCS
HRD
HWT
HINT
HAIl
HAl
HAl
HDO
HOI
HD2
HOJ
HD4
HOS
HDe
HD7
HOST
COMPUTER
PARALLEl.
BUS
_I
SPEAKER
J
NVRAII
!Illti
E8WT
DO/M
D1/AB
D2/AB
EYE
PATTERN
GENERATOR
D3/A7
D4IAI
IWAB
II8IA10
D7/Al1
All
b
~
EXPANSION
ROM
INTERFACE
RESET
I
RESET TC
AI
A2
fa
A12
EilfD
&BALE
Figure Sob. RC224AT/2 Interface Signals.parallelinterface
1-22
2400 bps Single Device Modem with" AT" Commands
RC224AT
Table 6. Digital Interface Characteristics
Parameter
Input High Voltage
Type A
Type B
!)ymbol
VIH
Input Low Voltage
TypesA&B
Input Leakage Current
Type A (Non-mu~iplexed)
Output High Voltage
Type A
TypeD
VIL
Output Low Voltage
Type A
Type 0
Three-State (Off)
Type A Output
VOL
liN
Min.
-
Vee
Vee
-- Stores 767-2676 into the
NVRAM.
ATDS=1 Dials the telephone number
stored in the NVRAM.
SPEAKER COMMANDS
Figure 4c illustrates the tangential smearing resulting from
phase jitter and Figure 4d shows the effect of amplitude
distortion (either gain jitter or harmonic distortion). The
magnitude of the spreading is directly proportional to the
severity of the impairment, and represents the quality of
the signal or the likelihood of errors in the received data.
The following 'AT' commands can be used to control the
speaker:
Command
Function
Mn
Controls the speaker operation.
Ln
Adjusts the speaker volume.
Smartcom II is a Inldemark 01 Hayes Microoomputer Producls. Inc.
Hayes is a registered trademark 01 Hayes Microcom puler Producls. Inc.
CROSSTALK XVI is a registered trademark 01 Digital Communications AssocIates.
Inc.
1-41
•
RC224EB
2400 bps Modem Evaluation Board
y
I
I •
I
I
---I------~--• I.
• I •
I
x _ _+I __-+-__+-__
•
•
•
•
I
I·
•
I •
• I
I ·
•
II •
----{------f--(.) DECISION POINTS - 2400 BPS
. (-) DECISION BOUNDARIES (Includes x & y axis)
.
" ,
I
y
/
/
/
//
" " // •
--X----'~~---------• // " "
/
"
/
/
/
.
"
(.) DECISION POINTS -1200 BPS
(-) DECISION BOUNDARIES
Figure 3. Ideal Eye Patterns
1-42
RC224EB
2400 bps Modem Evaluation Board
a) IDEAL EYE PATTERN
b) WHITE NOISE
y
•
y
•
x-----------+-----------
•
x-----------+-----------
•
• X AND Y AXIS REPRESENT
DECISION BOUNDARIES
• SMEARING AROUND EACH
IDEAL LOCATION
c) PHASE JITTER
d) HARMONIC DISTORTION
y
y
x-----------+-----------
x-----------+-----------
• CONTINUOUSLY PERIODIC
PHASE SMEARING
• LITTLE OR NO AMPLITUDE
SMEARING
• NON·PERIODIC AMPLITUDE
SMEARING
• LITTLE PHASE EFFECT
• GAIN..JITTER (AM) EFFECT IS
SIMILAR AND IS PERIODIC
'DEGREE OF THE SPREADING OF THE EYE PATTERN IS PROPORTIONAL TO THE SEVERITY OF THE LINE DISTURBANCE
Figure 4. Typical Eye Patterns Showing Noise
1·43
RC224EB
2400 bps Modem Evaluation Board
GENERAL SPECFICATIONS
Parameter
Voltage'
Current (Normal) Current (Sleep mode)
@ZS'C
@25"C
Board Structure
+ 5VDC:l:5%
70mA
9.1 mA
+ 12VDC:l:5%
OA
100 mA2
-5VDC:l:5%
20mA
1.8mA
Note:
1. Input vottage ripple 50.1 volts peak-to-peak.
2. Only used to power speaker; 0 mA when speaker
turned off.
Parameter
Temperature
Operating
Storage
Relative Humidity
Altitude
Dimensions
Width
Length
Specification
1O'C to + 40'C
O'Cto+ 70'C
(Stored In heat sealed antistatic bag
and shipping container)
Up to 90% noncondensing. or a wet
bulb temperature up to 35·C.
whichever is less.
- 200 feet to + 10.000 feet
1-44
Specification
Single PC board Half Card IBM
PC/XT' and PC/AT compatible edge
connector.
4.20 In. (1 06.7)
5.23 in. (132.7 mm)
R1212
Integral Modems
'1'
Rockwell
R1212
1200 bps Full-Duplex Modem
INTRODUCTION
FEATURES
The Rockwell R1212 is a high performance full-duplex 1200 bps
modem. Using state-of-the-art VLSI and signal processing technology, the R1212 provides enhanced performance and reliability. The modem is assembled as a small module with a DIN connector (R1212M amd R1212DC).
• CCITT V.22 A, B Compatible
• Bell 212A and 103 Compatible
• Synchronous: 1200 bps, 600 bps ±0.01%
• Asynchronous: 1200 bps, 600 bps + 1%, - 2.5%,
0-300 bps
- Character Length 8, 9, 10, or 11 bits
• DTE Interface
- Functional: CCITT V.24 (RS-232-C) (Data/Control) and
Microprocessor Bus (Data/Configuration/Control)
- Electrical: TTL Compatible
• 2-wire Full-Duplex Operation
• Adaptive and Fixed Compromise Equalization
• Test Configurations:
- Local Analog Loopback
- Remote Digital Loopback
- Self Test
• Auto/Manual Answer
• Auto/Manual Dial-DTMF Tone or Pulse Dial
• Power Consumption: 2.3 Watts Typical
• Power Requirements: + 5 Vdc, ± 12 Vdc
• Two Functional Configurations:
- R1212DC (Direct Connect): DIN connector module with
FCC approved DAA Part 68 Interface
- R1212M: DIN connector module without DAA
Being CCITT V.22 A, Bcompatible, as well as Bell 212Aand 103
compatible, the R1212 fits most applications for full-duplex
1200 bps (synchronous and asynchronous) and 0 to 300 bps
asynchronous data transmission over the general switched telephone network, and over point-to-point leased lines.
The direct-connect, auto dial/answer features are specifically
designed for remote and central site computer applications. The
bus interface allows easy integration into a personal computer,
box modem, microcomputer, terminal or any other communications product that demands the utmost in reliability and
performance.
R1212M Modem
Document No. 29200N10
Data Sheet
1-45
Order No. MD10
Rev_ 5, January 1989
•
I
R1212
1200 bps Full-Duplex Modem
TECHNICAL SPECIFICATIONS
TRANSMITTER CARRIER AND SIGNALING
FREQUENCIES
The transmitter and signaling frequencies supported in the
R1212 are listed in Table 1.
3. DTMF Tones: The R1212 generates dual tone multi·
frequency tones. When the transmission of DTMF tones are
required, the CRQ and DTMF' bits (see Interface Memory
Definitions)must be set to a 1. When in this mode, the specific
DTMF tones generated are decided by loading the dial digit
register with the appropriate digit as shown in Table 2.
Table 2.
Table 1. Transmitter Carrier and Signaling
Frequencies Specifications
Frequency
(Hz ±D.01%)
Mode
V.22 low channel, Originate Mode
1200
V.22 high channel, Answer Mode
2400
Bell 212A high channel Answer Mode
2400
Bell 212A low channel Originate Mode
1200
Bell 1031113 Originating Mark
1270
Bell 1031113 Originating Space
1070
Bell 1031113 Answer Mark
2225
Bell 1031113 Answer Space
2025
Hex
00
01
02
03
04
05
06
07
08
09
OA
OB
OC
00
OE
OF
TONE GENERATION
The specifications for tone generation are as follows:
1. Answer Tones: The R1212 generates echo disabling tones
for both the CCITI and Bell configurations, as follows:
a. CCITT: 2100 Hz ± 15 Hz.
b. Bell: 2225 Hz ± 10 Hz.
2. Guard Tones: If GTS (see Interface Memory Definitions) is
low, an 1800 Hz guard tone frequency Is selected; if GTS is
high, a 553.846 Hz tone is employed. In accordance with the
CCITI V.22 Recommendation, the level of transmitted power
for the 1800 Hz guard tone is 6 ± 1 dB below the level of the
data power in the main channel. The total power transmitted
to the line is the same whether or not a guard tone is enabled.
If a 553.846 Hz guard Is used, its transmitted power is
3 ± 1 dB below the level of the main channel power, and again
the overall power transmitted to the line will remain constant
whether or not a guard tone is enabled. The device accom·
plishes this by redUCing the main channel transmit path gain
by .97 dB and 1.76 dB for the cases of the 1800 Hz and
553.846 Hz guard tones respectively.
Table 3.
Operating Mode
V.22:
(Alternative A)
Mode i
Mode ill
(Alternative B)
Mode i
Mode iii
Mode Ii
Mode iv
Bell 212A:
Dial Digits/Tone Pairs
Dial
Digits
Tone Pairs
0
1
2
3
4
5
6
7
8
9
941
697
697
697
no
no
no
652
852
652
941
697
* (B)
Spare
no
Spare (C)
Spare (D)
652
941
941
#
Spare (F)
10
1336
1209
1336
14n
1209
1336
14n
1209
1336
14n
1209
1633
1633
1633
1477
1633
1300 Hz Calling Tone
TONE DETECTION
The R1212 detects tones in the 340 ±5 Hzt0640 ±5 Hz band.
Detection Level: -10 dBm to -43 dBm
Response TIme: 17 ± 2 ms
SIGNALING AND DATA RATES
The signaling and data rates for the R1212 are defined in
Table 3.
Signaling and Data Rates
Signaling Rate (Baud)
Date Rate
600
600
1200 bps to.Ol% Synchronous
600 bps t 0.01% Synchronous
600
600
1200 bps to.Ol% Synchronous
600 bps to.Ol% Synchronous
1200 bps Asynchronous, 8, 9, 10 or 11 Bits Per Character
600 bps Asynchronous, 8, 9, 10 or 11 Bits Per Character
1200 bps to.Ol%, Synchronous/Asynchronous
o to 300 bps Asynchronous
600
o to 300
1-46
R1212
1200 bps Full-Duplex Modem
DATA ENCODING
PERMISSIVE/PROGRAMMABLE CONFIGURATIONS
The specifications for data encoding are as follows:
The R1212M transmit level is +6 dBm to allow a Data Access
Arrangement (DAA) to be used. The DAA then determines the
permissive or programmable configuration.
1. 1200 bps (11.22 and Bell 212A). The transmitted data is
divided into groups of two consecutive bits (dibits) formmg a
four-point signal structure.
The R1212DC transmit level is strapped in the permissive mode
so that the maximum output level is - 10 dBm ± 1.0 dBm.
2. 600 bps (\1.22). Each bit is encoded as a phase change relative to the phase preceding signal elements.
AUTOMATIC RECONFIGURATION
EQUALIZERS
The R1212 is capable of automatically configuring itself to the
compatibility of a remote modem. The R1212 can be in either the
answer or originate mode for this to occur. The R1212 adaptation
compatibilities are limited to V.22 AlB (1200 bps), Bell 212, and
Bell 103. If the R1212 is to originate in a specific configuration,
the MODE bits (see Interface Memory Definitions) must be set.
The R1212 provides equalization functions that improve performance when operating over low quality lines.
Automatic Adaptive Equalizer-An automatic adaptive equalizer is provided in the receiver circuit for V.22 and Bell 212A configurations.
Fixed Compromise Equalizer-A fixed compromise equalizer
is provided in the transmitter.
MODEM OPERATION
TRANSMITTED DATA SPECTRUM
Because the modem is implemented in firmware executed by a
specialized computer (the signal processor), operation can best
be understood by dividing this section into hardware circuits and
software Circuits. Hardware circuits include all pins on the
modem connector. Software circuits include configuration, control (soft strapping), status, and RAM access routines.
After making allowance for the nominal specified compromise
equalizer characteristic, the transmitted line signal has a frequency spectrum shaped by the square root of a 75 percent
raised cosine filter. Similarly, the group delay of the transmitter
output is within ± 150 microseconds over the frequency range
900 to 1500 Hz (low channel) and 2100 to 2700 Hz (high channel).
HARDWARE CIRCUITS
The functional interconnect diagram (Figure 1) shows the
modem connected into a system. In this diagram, any pOint that
is active when exhibiting the relatively more negative voltage of a
two voltage system (e.g., 0 Vdc for TTL or -12 Vdc for
RS-232-C) is called low active and is represented by association
with a small circle at the signal point. The particular voltage levels used to represent the binary states do not change the logic
symbol. Two types of 110 points that may cause confusion are
edge-triggered inputs and open-collector (open-source or opendrain) outputs. These signal points include the additional notation of a small triangle or a small half-circle (see signal IRQ),
respectively. Active low signals are named with an overscore
(e.g., paR). In deciding whether a clock output is high active or
low active, the convention followed is to assume that the clocking
(activating) edge appropriate to the host hardware is a transition
from the clocks active to its inactive state (Le., a trailing edge
trigger). A clock intended to activate logic on its rising edge is
called low active while a clock intended to activate logic on its
falling edge is called high active. When a clock input is associated with a small circle, the input activates on a falling edge. If
no circle is shown, the input activates on a rising edge.
SCRAMBLER/DESCRAMBLER
The R1212 incorporates a self-synchronizing scramblerIdescrambler. In accordance with the CCITT V.22 and the Bell
212A recommendations.
RECEIVED SIGNAL FREQUENCY TOLERANCE
The receiver circuit olthe R1212 can adapt to received frequency
errors of up to ± 7 Hz with less than a 0.2 dBm degradation in
BER performance.
RECEIVE LEVEL
The receiver circuit of the R1212 satisfies all specified performance requirements forthe received line signals from - 10 dBm to
- 48 dBm. The received line signal is measured at the receiver
analog input RXA.
The interconnect signals on Figure 1 are organized into six
groups of modem operation: overhead signals, V.24 interface
signals, microprocessor interface signals, DAA signals, analog
signals, and ancillary signals. Table 4 lists these groups along
With their corresponding connector pin numbers. The column
titled "Type" refers to designations found in the Hardware Circuits Interface Characteristics (Tables 5 and 6). The six groups
of hardware circuits are described in the following paragraphs.
TRANSMIT LEVEL
The R1212M output control circuitry contains a variable gain
buffer which reduces the modem output level. The R 1212M can
be strapped via the host interface memory to accomplish this.
1-47
R1212
1200 bps Full-Duplex Modem
plete. The R1212 POR sequence leaves the modem configured
as follows:
POWER·ON RESET
Basic modem operation can be understood most easily by beginning with the modem configured to default conditions. When the
modem is initially energized a signal called Power-On-Reset
(POR) causes the modem to assume a valid operational state.
The modem drives pin ·13C to ground during the beginning olthe
POR sequence. Approximately 10 ms after the low to high transition of pin 13C, the modem is ready for normal use. The POR
sequence is reinitiated anytime the + SV supply drops below
+ 3.SV for more than 30 ms, oran external device drives pin 13C
low for at least 31's. When an external low input is applied to
pin 13C, the modem is ready for normal use approximately
10 ms after the low input is removed. Pin 13C is not driven low by
the modem when the POR sequence is initiated externally. In all
cases, the POR sequence requires SO ms to 350 ms to com-
V 2.
INTERFACE
1200 bps
Asynchronous
10-bIt Character length
Constant Carrier
Serial Mode
Answer Mode
Auto Answer Disabled
RAM Access Code = 00
•
•
•
•
•
•
•
•
This configuration is suitable for performing high speed data
transfer over the public switched telephone network using the
serial data port. Individual features are discussed in subsequent
paragraphs.
ATS
r- - - - - - - - - - - ---,
CTS
TXD
I
rocU<
I
XTCLK
I
I
RLSO
AXD
RDClK
DTA
DSA
-"
I
RING
L_
I
WRITE
R1212
I
DATA BUS (8)
(4)
A
E
MODEM
I
I
I
I
DECODEA
r
CS (2)
.A
POA
}
I
I
TELEPHONE
LINE
I
I
:.?N~_J
---------- - - - - - - ----,
Reel
CCT
OH
,--OM
I
ELEPHONE
= } T LINE
AD
'----AXA
TXA
ANALOG
INTERFACE
I
I
I
I
I
I
I
R1212
L_ - - - - - - - - -M~~J
J
TSCLK
.... h
RBCLK
+5V
+12V
-12V
ANCILLARY
CIRCUIT
INTERFACE
AGNO
DGNO
Figure 1.
I
---
TLK
OAG
POWER
SUPPLY
I
I
R1212D
I
IAQ
+5
ANALOG
INTERFACE
TIP
I
I•
LINE MONITOR
I
r-
READ
(DTE)
ANCILLARY
CIRCUIT
INTERFACE
I
AI
HOST
PROCESSOR
OH
R1212 Modem Functional Interconnect Diagram
1-48
1200 bps Full-Duplex Modem
R1212
Table 4.
Name
Type
DIN
Pin No.
I
A. OVERHEAD SIGNALS
Ground (A)
AGND
31C,32C
Ground (D)
DGND
+5 volts
PWR
3C, BC,
SA, lOA
19C,23C,
28C,3OC
15A
12A
13C
+12 voRs
-12 voRs
POR
PWR
PWR
IIOB
Hardware Circuits
Description
Name
0113
02
01
DO
RS3
RS2
RSI
RSO
CSO
CSI
READ
WRITE
IRQ
1I0A
1I0A
1I0A
1I0A
1I0A
IIOA
IIOA
IIOA
IA
IA
IA
IA
IA
Analog Ground
Return
Dig~ Ground
Return
+ 5 voR supply
+ 12 voR supply
- 12 volt supply
Power-on-Reset
IA
IA
IA
OB
4C
4A
5C
IB
RXA(M)
TXA(M)
OC
25C
IB
OC
OC
24C
IB
OC
OC
21C
20A
18A
External Transmit
Clock
Transm~ Data Clock
Receive Data Clock
Request·to-Send
Clear-to-Send
Transmit Data
Rec81ve Data
Received Line Signal
Detector
Data Terminal Ready
Data Set Ready
Ring Indicator
22C
24A
IB
OC
32A
31A
TIPIRING (DC) AE
LINE
MONITOR (DC) AD
Register Select
(4-Lines)
7C
7A
IOC
22A
23A
21A
25A
D. ANALOG SIGNALS
Dete Bus (II-Lines)
6C
IB
OC
OC
Ai
1
t
SA
XTCLK
TDCLK
RDCLK
RTS
CTS
TXD
RXD
RLSD
DTR
DSR
lC
lA
2C
2A
3A
Descrtptlon
C. V.24 INTERFACE SIGNALS
B. MICROPROCESSOR INTERFACE SIGNALS
07
06
05
D4
DIN
Pin No.
Type
RJll Jacks
ReceIVe Analog Input
Transmit Analog
Output
Phone line Interface
30A
Analog Line Monitor
Ring Detect
Request Coupler Cut
Through
Coupler Cut Through
Oft-Hook Relay Status
E. OM INTERFACE SIGNALS
Chip Select
Receiver (Baud
Rate Device)
Chip Select
Transmitter
(Sample Rate
Device)
Reed Enable
Wme Enable
Interrupt Request
9C
12C
llA
llC
RD(M)
RCCT(M)
OC
IB
27A
28A
CCT(M)
OH
IB
29C
OC
29A
F. ANCILLARY INTERFACE SIGNALS
TBCLK
RBCLK
TLK
ORG
-
27C
26A
28C
16C
OC
OC
IC
IB
Transmrt Baud Clock
Receive Baud Clock
Talk (TLK = Data)
Originate (ORG =
Answer)
(M) R1212M Only, (DC) R1212DC Only, - = not applicable
Unused Inputs tied to +5V or ground requore Individual 10K 0 senes
reslslors
Table 5.
Digital Interface Characteristics
Input/Ouput Type
Symbol
Parameter
V,H
Input Voltage, High
V,L
VOH
VOL
Input Voltage, Low
Output Voltage, High
Output Voltage, Low
Input Current, Leakage
Output Current, High
Output Current, Low
Output Current, Leakage
Pull-up Current
(Short CirCUit)
Capacitive Load
Capacitive Drive
Circuit Type
I'N
IOH
IOL
IL
lpu
CL
CD
Notes: 1. I load = -100 pA
Units
IA
IB
IC
V
2.0 mono
2.0 min.
2.0 min
V
V
V
pA
rnA
mA
pA
pA
O.B max.
O.B max.
O.B max.
pF
pF
OA
08
OC
2.4 min.'
04 max'
0.4 max.'
04 max.'
1.6 max.
±10 max.
1.6 max.
±2.5 max.
-0.1 max.
1.6 max.
5
TIL
2.1 load = 1.6 mA
-240 max.
-10 min.
5
-240 max.
-10 min.
20
TIL
w/Pull-up
TIL
w/Pull-up
3.lIoad = -40 pA
1-49
110 A
2.0 mono
O.B
2.4
0.4
±2.5
1I0B
5.25
2.0
max. O.B
min' 2.4
max' 0.4
max 4
max.
min.
max.
mln.3
max.5
-240 max.
-10 min
100
TIL
-260 max.
-100 min.
10
40
100
100
100
100
Open-Drain
Open-Draon Open-Drain
3 State
w/Pull-up Transceiver w/Pull-up
4. V'N = 0.4 to 2.4 Vdc, Vee = 5.25 Vdc
5. I load = 0.36 rnA
R1212
1200 bps Full-Duplex Modem
Table 6.
Name
TXA
RXA
Characteristics
AA
The transmitter output impedance is 60411
±1% with an output level of +6 dBm.
To obtain a 0 dBm output, a 60011 load to
ground is needed.
AB
disregard all signals appearing on the interchange circuitsexcept Ai. DSR will switch to the OFF state when in test state.
The ON condition of DSR indicates the following:
Analog Interface Characteristics
Type
1. The modem is not in the talk state, i.e., an associated telephone handset Is not in control of the line.
2. The modem is not in the process of automatically establishing
a call via pulse or DTMF dialing.
The receiver input impedance is 23.7 KI1
±1%. The receive level at RXA must be
no greater than - 9 dBm (or - 6 dBm
with the 3DB bit enabled).
LINE
MONITOR
AD
The line monotor output impedance is
15KI1 ±5%.
TIP/RING
AE
The impedance of TIP with respect to
RING is 600 11.
3. The modem has generated an answer tone or detected
answer tone.
4. After ring indicate (Ai) goes ON, DSR waits at least two seconds before turning ON to allow the telephone company
equipment to be engaged.
.
.
OSR will go OFF 50 ms after OTR goes OFF, or 50 ms plus a
maximum of 4 seconds when the SSO bit is enabled.
V.24 INTERFACE
Request To Send (RTS)
Eleven hardware circuits provide timing, data, and control signals for implementing a serial interface compatible with CCITT
Recommendation V.24. These signals interface directly with circuits using TTL logic levels (OV, + 5V). These TTL levels are
suitable for driving the short wire lengths or printed circuitry normally found within stand-alone modem enclosures or eqUipment
cabinets. For driving longer cables, the voltage levels and connector arrangement recommended by EIA standard RS-232-C
are preferred.
RTS ON allows the modem to transmit data on TXD when ers
becomes active. In constant carrier mode, RTS cim be wired to
OTR. In controlled carrier operation, independent operation of
RTS turns the carrier ON and OFF. The responses to RTS are
shown in Table 7 (assume the modem is in data mode).
Table 7.
Leased or Dial
The sequence of events leading to successful data transfer from
transmitter to receiver is:
1. The transmitter is activated and a training sequence is sent.
Line1
Carrier ON
210 to 275 ms Scrambled
1 s Transmitted
CTS ON
CTS OFF
Carrier OFF
Constant Carrier
CTS OFF
CTS ON
Carrier ON
Carrier ON
Scrambled 1 s Data Transmitted
Transmitted
Note:
1. After handshake
4. The transmitter turns off after insuring that all data has had
time to be recovered at the receiver output.
RTSON
RTS OFF
Controlled Carrier
2. The receiver detects channel enel1lY above the prescribed
threshold level and synchronizes its operation to the
transmitter.
3. Data transfer proceeds to the end of the message.
RTS Responses
IS
complete.
Clear To Send (CTS)
CTS ON indicates to the terminal equipment that the modem will
transmit any data which are present on TXO. ers response times
from an ON or OFF condition of RTS are shown in Table 8.
Data Terminal Ready (DTR)
DTR prepares the modem to be connected to the communications channel, and maintains the connection established by the
DTE (manual answering) or internal (automatic answering)
meaQs. DTR OFF places the modem in the disconnect state.
Table 8. CTS Response Times
CTS
Translti~n
Constant Carrier
Controlled Carrier
<2 ms
<20 ms'
210 to 275 ms
<20 ms'
OFF to ON
ON to OFF
Data Set Ready (DSR)
Data Set Ready (DSR) ON indicates that the modem is in the
data transfer state. DSR OFF is an indication that the DTE is to
Note: 'Programmable
1-50
R1212
1200 bps Full-Duplex Modem
Transmit Data Clock (TDCLK)
RLSD will not respond to guard tones or answer tones.
The modem provides a Transmit Data Clock (TDCLK) output with
the following characteristics:
When RLSD is active, it indicates to the terminal equipment that
valid data is available on RXD.
1. Frequency. Selected data rate of 1200 Hz or 600 Hz
(±0.01%).
Transmitted Data (TXD)
The modem obtains serial data from the local DTE on this input.
2. Duty Cycle. 50 ± 1%.
Received Data (RXD)
TDCLK is provided to the user in both asynchronous and synchronous communications. TDCLK is not necessary in asynchronous communication but it can be used to supply a clock for
UARTIUSART timing (TDCLK is not valid in FSK). TDCLK is necessary for synchronous communication. In this case Transmit
Data (TXD) must be stable during the one fJ-s periods immediately preceding and following the rising edge of TDCLK.
The modem presents received dala to the local DTE on this
output.
Ring Indicator (AI)
The modem provides a Ring Indicator (Ai) output; its low state
indicates the presence of a ring signal on the line. The low condition appears approximately coincident with the ON segment of
the ring cycle (during rings) on the communication channel. (The
ring signal cycle is typically two seconds ON, four seconds OFF.)
The high condition of the Ai output is maintained during the OFF
segment of the ring cycle (between rings) and at all other times
when ringing is not being received. The operation of Ai is not
disabled by an OFF condition on DTR.
External Transmit Clock (XTCLK)
In synchronous communication where the user needs to supply
the transmit data clock, the input XTCLK can be used. The clock
supplied at XTCLK must exhibit the same characteristics of
TDCLK. The XTCLK input is then reflected at TDCLK.
Receive Data Clock (RDCLK)
RI will respond to ring signals in the frequency range of 15.3 Hz
to 68 Hz with voltage amplitude levels of 40 to 150 Vrms (applied
across TIP and RING), with the response times given in Table 13.
The modem provides a Receive Data Clock (RDCLK) output in
the form of a 50 ± 1% duty cycle squarewave. The low-to-high
transitions ofthis output coincide with the center of received data
bits. The timing recovery circuit is capable of tracking a ± .035%
(relative) frequency error in the associated transmit timing
source.
This OFF-to-ON (ON-to-OFF) response time is defined as the
time interval between the sudden connection (removal) of the
ring signal across TIP and RING and the subsequent ON (OFF)
transition of Ri.
RDCLK is provided to the user in both asynchronous and synchronous communications. RDCLK is not necessary in asynchronous communication but it can be used to supply a clock for
UARTlUSARTtiming (RDCLK is not valid in FSK). RDCLK is necessary for synchronous communication.
Table 9.
Received Line Signal Detector (RLSD)
The RLSD thresholds for both high and low channels are:
Ai Response Time
RI Transition
Response Time
OFF-Io-ON'
ON-Io-OFF
110 ± 50 ms (50% duly cycle)
450 ±50 ms
Note: 'The OFF-Io-ON lime is duly cycle dependent:
890 ms (15%) '" time", 50 ms (100%)
RLSD ON '" - 43 dBm
RLSD OFF s - 48 dBm
1-51
1200 bps Full-Duplex Modem
R1212
MICROPROCESSOR INTERFACE
rupt. Any of these sources can drive the host interrupt input low,
and the interrupt servicing process continues until all interrupts
have been cleared and all IRQ sources have returned to their
h!.9.f:1 impedance state. Because of the open-drain structure of
IRQ, an external pull-up resistor to + 5 volts is required at some
point on the IRQ line. The resistor value should be small enough
to pull the IRQ line high when all IRQ drivers are off (I.e., it must
overcome the leakage currents). The resistor value should be
large enough to limit the driver sink current to a level acceptable
to each driver. For the case where only the modem IRQ driver is
used, a resistor value of 5.6K ohms ± 20 oAl, 0.25 watt, is
sufficient.
Seventeen hardware circuits provide address, data, control, and
interrupt signals for implementing a parallel intli!rface compatible
with an 8080 microprocessor. With the addition of a few external
logic gates, the interface can be made compatible with a wide
variety of microprocessors such as 6500, 6800, or 68000.
The microprocessor interface allows a host microprocessor to
change modem configuration, read or write channel data as well
as diagnostic data, and supervise modem operation by means of
soft strappable control bits and modem status bits. The significance of the control and status bits and methods of data interchange are discussed in a later section devoted to software circuits. This section describes the operation of the interface from a
hardware standpoint.
DAAINTERFACE
The R1212M provides a Data Access Arrangement (OM) interface that is directly hardware and software compatible with the
ROM. Manual/automatic originate and answer are then controlled via the appropriate R1212M hardware ancillary circuits or
software control bits. The modem provides the only interface with
the microprocessor (MPU) bus, i.e., no ROM interface signals
must be directly controlled from the MPU bus.
Chip Select (CSO and CS1) and
Register Selects (RSO.RS1)
The signal processor to be accessed is selected by grounding
one of two unique chip select lines, CS1 or CSO. The selected
chip decodes the four address lines, RS3 through RSO, to select
one of sixteen internal registers. The most significant address bit
(23) is RS3 while the least significant address bit (2Dj is RSO.
Once the address bits have been decoded, the selected register
can be read from or written into via an 8-bit parallel data bus, 07
through DO. The most significant data bit (27) is 07 while the
least significant data bit (20) is 00.
Ring Detect (RD)
RD indicates to the modem by an ON (low) condition that a ringing signal is present. The signal (a 4N35 optoisolator compatible
output) into the RD input should not respond to momentary
bursts of ringing less than 125 ms in duration, or to less than
40 Vrms, 15 to 68 Hz, appearing across TIP and RING with
respect to ground. The ring is then reflected on Ri.
Read Enable (READ) and
Write Enable (WRITE)
Request Coupler Cut Through (RCCT)
Reading or writing is activated by pulsing either the READ line
high or the WRITE line low. During a read cycle, data from the
selected register is gated onto the data bus by means of threestate drivers. These drivers force the data lines high for a one bit
or low for a lero bit. When not being read, the three-state drivers
assume their' off, high-impedance, state. During a write cycle,
data from the data bus is copied into the selected register, with
high and low bus levels representing one bits and zero bits,
respectively. The timing required for correct read/write cycles is
illustrated in Figure 2. Logic necessary to convert the single Rm
output from a 65XX series microprocessor to the separate READ
and WRITE signals required by the modem is shown in Figure 3.
RCCT is used to request that a data transmission path through
the DAA be connected to the telephone line. When RCCT goes
OFF (low), the cut-through buffers are disabled and CCT should
go OFF (high). RCCT should be OFF during dialing but ON for
tone address signaling.
Coupler Cut Through (CCT)
An ON (low) signal to the CCT lead indicates to the modem that
the data transmission path through the OM is connected. This
input can always be ~ded if the two second billing delay
squelch is desired. If CCT is user controlled, the billing delay
squelch can only be 2 seconds or greater.
Interrupt Request (IRQ)
Off·Hook Relay Status (OH)
The final ~nal on the microprocessor interface is Interrupt
Request (IRQ). This signal may be connected to the host microprocessor interrupt request input in order to int~t host program execution for modem service. The use of IRQ is optional
and the method of software implementation is described in a
subsequent section, Software Circuits. The IRQ output structure
is an open-drain fleld-effect-transistor (FET). This form of output
allows IRQ to be connected in parallel to other sources of inter-
The modem provides an OH output which indicates the state of
the OH relay. A high condition on OH implies the OH relay is
closed and the modem is connected to the telephone line (offhook). A low condition on OH implies the OH relay is open (i.e.,
the modem is on-hook). The delay between the low-to-high or
high-ta-Iow transition of OH and the subsequent close-to-open or
open-ta-close transition of the OH relay is 8 ms maximum.
1-52
1200 bps Full-Duplex Modem
R1212
I
I
WRITE
READ
I
III
CSi
(i
= 0,1)
RSi
(i = 0-3)
READ
Di
(i
= 0-7)
Characteristic
CSi, RSi setup time prior
to Read or Write
Data access time after Read
Data hold time after Read
CSI, RSI hold time after
Read or Write
Write data setup time
Write data hold time
Write strobe pulse width
Figure 2.
.2
Symbol
Min
TCS
TDA
TDH
30
TCH
TWOS
TWOH
TWR
10
75
10
75
10
Max
Units
140
50
ns
ns
ns
ns
ns
ns
ns
Microprocessor Interface Timing Diagram
I~
READ
R1212
MODEM
WRITE
RiYi
Figure 3.
R/W to READ WRITE Conversion Logic
1-53
R1212
1200 bps Full-Duplex Modem
ANALOG SIGNALS (R1212M)
+____ )
TO
(
NETWORK _ _ _ _. .
Two connections are devoted to analog audio signals: TXA and
RXA.
r--
TO OTHER
EQUIPMENT
--,
11:2134516: R2424
Transmit Analog (TXA)
MINIATURE
I
I I
6 POSITION JACK I I
I)..
1.. ________ -'
The TXA output is suitable for driving a data access arrangement
for connection to either leased lines or the public switched telephone network. The transmitter output impedance is 604 ohms
± 1% with an output level of +6 dBm ± 1 dBm. To obtain a
o dBm output, a 600 ohm load to ground is needed.
A'
MODEM JACK
r- - - - --,
MINIATURE
:
6 POSITION PLUG I
RING (RED
Receive Analog (RXA)
RXA is an input to the receiver from a data access arrangement.
The input impedance is 23.7K ohms ± 1%. The received level at
RXAmust be no greater than -9 dBm(or -6 dBm withthe3DB
bit enabled).
tI j3141 j +! :
I
TELEPHONE
CORD
W~: J t ~':(GREEN
Figure 4.
WIRE)
RJ11 Telephone Jack
ANCILLARY CIRCUITS
Transmit Baud Clock (TBCLK) and
Received Baud Clock (RBCLK)
ANALOG SIGNALS (R1212DC)
Three analog signals are output by the R1212DC: LINE MONITOR, TIP and RING.
TBCLK and RBCLK are provided to the user at the baud rate
(600 Hz).
Talk (TLK)
Analog Line Monitor (LINE MONITOR)
TLK is an input which manually places the modem on-hook (relay
open, TLK = 0) or off-hook (relay closed, TLK = 1). The on-hook
condition is referred to as TALK mode and the off-hook condition
is referred to as DATA mode. TLK is used with ORG to manually
originate or answer a call. TLK should be 0 at power-on or resetlo
prevent the modem from inadvertently entering the data mode.
The LINE MONITOR output is suitable for a speaker interface. It
provides an output for all dialing signals, call progress Signals,
and the carrier signals. The output impedance is 15K ohms
± 1%. The signals which appear on LINE MONITOR are approximately the same level as the signals would appear on the network (assuming a 1 dB loss attributed to the audio transformer).
Originate (ORG)
ORG is an input which manually places the modem in the originate mode (ORG = 02.£!:.!.he answer mode (ORG = 1). To manually originate a call, ORG = 0 and TLK = O. Dial the number
using the telephone. When the other modem answers and sends
answer tone switch the TLK input from 0 to 1 plaCing the modem
off-hook.
Phone Line Interface (TIP and RING)
TIP and RING are the DAA analog outputs to the public switched
telephone network. These outputs use two RJ11 jacks in parallel
as the interface to the network (see Table 10 and Figure 4). The
R1212DC, which contains the DAA TIP and RING interface, has
been FCC Part 68 approved. The user need not apply for further
Part 68 approval. The impedance of TIP with respect to RING is
600 ohms.
To manually answer a call ORG = 1 and TLK = O. When the
phone rings switch the TLK input from 0 to 1 placing the modem
off-hook.
Off·Hook Relay Status (OH)
The modem provides an OH output which indicates the state of
the OH relay. A high condition on OH implies the OH relay is
closed and the modem is connected to the telephone line (offhook). A low condition on OH implies the OH relay is open (i.e.,
the modem is on-hook). The delay between the low-ta-high or
high-to-Iow transition of OH and the subsequent close-to-open or
open-to-close transition of the OH relay is 8 ms maximum.
Table 10. R1212DC Network Interface
Connector
Type
RJ11 Jack
Pin
Number
3
4
Name
Function
RING
TIP
One Side of TELCO Line
One Side of TELCO Line
1-54
R1212
1200 bps Full-Duplex Modem
SOFTWARE CIRCUITS
rupt each time it sets. This interrupt can then be cleared by a read
or write cycle from the host processor to register O. This operation is discussed in detail later in this section.
Operation of the microprocessor interface circuits was described
in the hardware section from the standpoint of timing and loadIdrive characteristics. In this section, operation of the microprocessor interface is described from a software standpoint.
Memory maps of the 32 addressable registers in the modem
receiver (CSO) and transmitter (CS1) interface memory are
shown in Figures 5 and 6, respectively. These registers may be
read or written on any host read or write cycle, but all eight bits of
that register are affected. In order to read a Single bit or a group of
bits in a register, the host processor must mask out unwanted
data. When writing a single bit or group of bits in a register the
host processor must perform a read-modify-write operation. That
is, the entire register is read, the necessary bits are set or reset in
the accumulator of the host, then the original unmodified bits and
the modified bits are written back into the register of the interface
memory.
The modem is implemented in firmware running on two special
purpose signal processors. These signal processors share the
computing load by performing tasks that are divided into two
areas. These areas are partitioned into receiver and transmitter
devices.
INTERFACE MEMORY
Each signal processor can communicate with the host processor
by means of a specialized, dual-port, scratch-pad memory called
interface memory. A set of sixteen a-bit registers, labeled register 0 through register F, can be read from or written into by either
the host processor or signal processor. The host communicates
via the microprocessor interface lines shared between the two
signal processors. The signal processor communicates via its
internal 1/0 bus. Information transfer from SP RAM to interface
memory is accomplished by the signal processor logic unit moving data between the SP main bus and the SP 1/0 bus. Two of the
16 addressable interface memory registers (Le., register 0 and
register E) have unique hardware connections to the interrupt
logic. It is possible to enable a bit in register E to cause an inter-
Figures 7 and a show the registers according to the overall function they perform in the receiver and transmitter, respectively.
Figures 9 and 10 show the power-on configuration for the R1212
modem receiver and transmitter devices, respectively.
Table 11 defines the individual bits in the interface memory. In the
Table 11 descriptions, bits in the interface memory are referred to
using the format Y:Z:Q. The chip number is specified by Y (0 or
1), the register number by Z (0 through F), and the bit number by
Q (0 through 7, with 0
LSB).
=
1-55
R1212
1200 bps Full-Duplex Modem
~
7
E
IRQ
ENSI NEWS
0
BUS
CRQ
C
a
-
-
-
-
A
ERDL
RDL
DL
ST
-
-
Reglate
6
4
5
F
9
-
7
6
2
1
0
~t
-
NEWC
-
-
-
-
LCD
RSD
-
-
-
-
AL
-
-
-
-
-
-
-
4
5
-
2
3
-
IRQ
ENSI NEWS
0
BUS
CRQ DATA AAE
C
DSRA
TXCLK
ERDL
-
DTR
-
CHAR
TX LEVEL
A
NEWC DDEI
GTE
RDL
Dl
ST
GTS
-
9
NAT'
-
ORG
LL
RTS
CC
EF
NTS
8
DLO
CTS
DSR
RI
-
-
7
-
6
-
-
-
-
-
-
-
-
4
RAM Data YTL (YRAMTL)
3
RAM Data XRM (XRAMRM)
3
RAM Data XTM (XRAMTM)
RAM Data XRL (XRAMRL)
0
-
-
-
1
-
0
~
7
6
5
I I
4
I
o I A G NOS TIC
F
3
2
I I
-
-
-
-
Notes
1
I
Figure 6.
~
0
Regis!
CON T'R 0 L
Transmitter (CS1) Interface Memory Map
7
I
F
6
I
5
I
4
I
3
I
2
I
HANDSHAKE
E
HANDSHAKE
0
CONFIGURATION
0
CONFIGURATION
C
CONFIGURATION
C
CONFIGURATION
a
CONFIGURATION
a
CONFIGURATION
A
CONFIGURATION
A
CONFIGURATION
9
STATUS
9
CONFIGURATION
8
STATUS
8
STATUS
7
RESERVED
7
RESERVED
6
RESERVED
6
RESERVED
5
DIAGNOSTIC
5
DIAGNOSTIC
4
DIAGNOSTIC
4
DIAGNOSTIC
3
DIAGNOSTIC
3
DIAGNOSTIC
2
DIAGNOSTIC
2
DIAGNOSTIC
1
RESERVED
1
RESERVED
0
RESERVED
0
DIAL DIGIT REGISTER
Bit
7
l I
6
5
I
4
3
I I
2
I
1
I
~
0
Bit
Figure 7. Receiver (CSO) Interface Memory Functions
Figure 8.
1-56.
1
I
0
DIAGNOSTIC CONTROL
E
~
-
-
Dial Digit Register
1. Not valid before R5312-16
(-) Indicates reserved for modem use only.
Receiver (CSO) Interface Memory Map
I
-
RAM Data XTL (XRAMTL)
-
-
Note
(-) Indicates reserved for modem use only.
Figure 5.
-
RAM Data YTM (YRAMTM)
2
-
-
AL
RLSD
5
-
SSD
DLSF'
-
RAM Data YRL (YRAMRL)
-
DDRE
TM
RAM Data YRM (YRAMRM)
-
-
MODE
4
1
0
3Da DTMF
5
2
1
RAM Access T
E
B
MODE
SPEED
6
F
-
CHAR
-
7
R.eglsle
RAM Access R
TONE ATD
8
3
7
I
6
I
5
I
4
I
3
I
2
I
1
I
0
Transmitter (CS1) Interface Memory Functions
1200 bps Full-Duplex Modem
R1212
.~
•
7
5
0
E
IRQ
0
0
ENSI NEWS
0
0
CRQ
0
0
- - - RDL
- • ERDL
• - - •
•
• - - • - - D
IUS
0
C
A
3
4
1
2
0
~
0
F
0
E
IRQ
D
IUS
C
DSRA
RAM~R
F
0
0
OL
0
0
0
-
NEWC
0
-CHAR- • - - - - - - - 0
LCD
1
1
ST
0
0
0
TONE
0
ATD
0
•
•
•
•
AL
0
MODE
0
SPEED
7
0
- RID
- - TM ALSO
1
0
-
A
1
0
-
7
~)
•
7
0
0
ENSI NEWS
0
0
•
CRa
DATA
0
0
0
•
TXCLK
0
0
0
5
TX LEVEL
3
4
RAM~T
0
-
AAE
0
0
0
NEWC DDEI
0
0
DTR
-
0
CHAR
1
0
-
GTE
GTS
3D.
0
0
ERDL
RDL
DL
ST
0
0
0
NAT
-
ORO
LL
RTS
CC
OLO
CTS
DSR
-
-
0
0
0
-
0
0
0
0
0
0
0
0
0
0
RAM DIlle YRL (RencIom)
4
RAM DIlle YTL (RencIom)
3
RAM DIlle XAM (RencIom)
3
RAM DIlle XTM (Random)
RAM DIlle XRL (RIIndom)
2
0
~
7
•
5
4
3
2
1
~
(-) 1ncI,-," ~ lor mocIem .... only.
Figure
-
DTMF
0
0
SSD
•
DLSF
0
AL
•
1
1
EF
NTS
0
0
RAM DIlle XTL (RIIndom)
- - - - -
- - -
DI8I DIgIt ReghIhIr (WrIte-OnIy RegIMer)
0
0
-
RI
4
1
0
DORE
RAM DIlle YTM (RencIom)
5
- - - - - - - - - - - - - - -
0
• - - - - - - - - - - - - - - 0
RAM DellI YAM
1
0
-
MODE
5
2
1
Z
7
•
5
4
3
Z
1
0
(-) Indlc_ ~ lor modem .... only.
t. R1212 Receiver (CSO) Interface Memory
Figure 10. R1212 Tranamltter (CS1) Interface Memory
Power On Configuration
Power On Configuration
1-57
R1212
1200 bps Full-Duplex Modem
Table 11. Interface Memory Definitions
Mnemonic
AAE
Name
Auto Answer Enable
Memory
Location
1:0:4
Description
When configuration bit ME is a I, the modem will automatically answer
when a ringing signal is present on the line. When ME is set to a I, the
modem will answer after one ring and go into data mode.
The modem goes off-hook 1 second after the on-to-off transition of the ring.
The ORG pin or ORG bit need not to be set to the answer polarity. If it is
desired to answer after more than one ring, then the user must' use the alternative answer method described under the OATA bit. The DTR pin or
the DTR bit must also be sat before the modem will auto answer. Writing a 0
into the AAE bit will cause the modem to go on-hook. This will occur only
when the modem auto answers using the ME bit.
AL
Analog Loopback
(O,I):B:O
When configuration bits AL are a I, the modem is in local analog loopback
(V.54 Loop 3). In this loop, the transmitter's analog output is coupled to the
receiver's analog input at a pOint near the modem's telephone line interface.
An attenuator is introduced into the loop such that the signal level coupled
into the receive path is attenuated 14 ± 1 dBm. The modem may be placed
into analog loopback in either the idle mode or the data mode. However, in
the data mode, setting the AL bits to a 1 will terminate the connection.
Analog loopback will only function in the high speed modes (1200, or 600
bps).
The DTE may be tested when the modem is in analog loopback. Also, all
parts of the modem except the line interface are checked. If no DTE is connected, the modem integrity may be verified by use of the self test function.
When entering analog loopback, set AL in the receiver to a 1 before setting
AL in the transmitter to a 1.
When exiting analog loopback, reset AL in the transmitter to a 0 before resetting AL in the receiver to a O.
ATD
Answer Tone Detected
BUS
Bus Select
0:8:6
When status bit ATO is a I, it signifies that the modem receiver detected the
answer tone. The bit is 1 set 75 ms after the answer tone is first detected,
and is cleared to a 0 when the modem goes on-hook. The user may clear
ATD manually after CTS is active.
(0,1):0:7
When configuration bits BUS are aI, the modem is in the parallel control
mode; and when 0, the modem is in the serial control mode. BUS can be in
either state to configure the modem.
Serial Control Mode
The serial mode uses standard V.24 (R5-232-C compatible) signals to
transfer channel data. The control signals used in serial control mode are
DTR, RTS, TLK, and ORG. Outputs such as RLSD and DSR are reflected
both in the interface memory and the V.24 interface. Once the bus bits have
been set to a 0, the state of the DTR, RTS, DATA, and ORG bits are
ignored.
Parallel Control Modt!!
The modem has the capability of modem control via the microprocessor bus.
Data transfer is maintained over the serial V.24 channel. The control bits
used in parallel control are DTR, RTS, ORG, and DATA.
The modem automatically defaults to the serial mode at power-on.
If the parallel control mode is to be used, it is recommended that the TLK pin
be tied to ground. A floating TLK pin will assume a logic 1 which will
immediately put the modem into the data mode before the BUS bits are set.
In either mode, the modem is configured by the host processor via the
microprocessor bus.
1-58
R1212
1200 bps Full-Duplex Modem
Table 11. Interface Memory Definitions (Continued)
Memory
LocatIon
CC
Controlled Carrier
1:9:2
Deecrlptlon
When configuration bi1 CC is a 1, the modem operates In controlled carrier;
when 0, the modem operates In constant carrier.
Controlled carrier allows the modem transmitter to be controlled by the RfS
pin or the RTS bi1. Its effect may be seen in the RTS and CTS descriptions.
CHAR
Character length Select
(O,1):C:(3.4)
These character length bits select either 8, 9, 10, or 11 bi1 characters
(Includes data, stop, and start bi1s) as shown below:
Configuration Word
~
'!
0
0
1
1
0
1
0
1
Configuration
8 bits
9 bits
10 bits
11 bits
It is possible to change character length during the data mode. Errors In the
deta will be expected between the changeover and the rasynchronizatlon
(which occurs on the next start bit after the change Is implemented).
CRQ
Call Request
(0,1):0:8
When configuration bi1 CRQ In chip 1 (the transmitter) is a 1, it places the
transmitter in auto dial mode. The dala then placed in the Dial Digi1 Register
is treated as digits to be dialed. The format for the data should be a hex
representation of the number to be dialed (if a 9 is to be dialed then an 09 18
should be loaded in DDR). CRQ in chip 1 should be a 1 for the duration of
the data mode. If CRQ in chip 1 is changed to a 0, the modem will go
on-hook. Also, see DDRE bi1.
When configuration bit CRQ In chip 0 (the receiver) Is a 1, the receiver goes
into tone detect mode. Any energy above threshold and In the 345 to 635 Hz
bandwidth Is reflected by the TONE bit. CRQ In chip 0 must be reset to a 0
(after the last dlgi1 was dialed and tone detection completed) before the
answer tone Is sent by the answering modem (after ringback is detected).
CRQ In chip 0 need not be used during auto dialing, but may be used to provide call progress Informalion as part of an intelligent auto dialing routine. An
example flowchart Is given In Figure 11.
FF (hex) should be loaded into the Dial Digit Register after the last digit is
dialed and tone detection is completed. This action also puts the modem in
dala mode and starts a 30 second abort timer. If tha handshake has not
been completed In 30 seconds the modem will go on-hook.
CTS
Clear-ta-Send
1:8:8
Whan status bit CTS is a 1, it Indicates to the terminal equipment that the
modem will transmit any data which are present at TXD.
CTS response times from an ON or OFF condition of RTS are shown below:
CTS Tranaitlon
OFF to ON
ON to OFF
• Programmable
Conlllant Carrier
s2 ms
s20 ms·
Controlled Carrier
210 to 275 ms
s20 ms·
DATA
TalkIDala
1:0:5
When control bit DATA is a 1, the modem is In the data state (off-hOOk); and
when 0, the modem is in the talk state (on-hook). This bit allows the modem
to go off-hook after a programmable number of rings by counting the required
number of RI biltransi1ions and then setting the DATA bi1 (assuming ORG - 0).
DDEI
Dial Digi1 Empty Interrupt
1:E:2
When handshake bit DDEI is a 1, an interrupt will occur when the Dial Digit
Register (1:0) Is empty (DDRE= 1). This is independent of the state of tha
ENSI bit. The Interrupt will set the IRQ bit and also assert the IRQ signal.
Loading tha Dial Digi1 Register wi1h a new digit will clear the Interrupt
condition.
.
1-59
R12:12
1200 bps Full-Duplex Modem
Table 11. Interface Memory Definitions (Continued)
Mnemonic
Neme
DpR
Dial I;>igit Register
DDRE
Dial Digit Register Empty
Memory
Locetlon
1:0:(0-7)
I:E:O
Description
DDR Is used to load the digits to be dialed. Example: If a 4 is to be dialed,
an 04 (hex) should be loaded. ThiS action also causes the Interrupt to be
cleared. The modem automatically accounts for the interdigit delay. Note:
DDR is a write-only register.
When handshake bit DDRE is a I, it indicates that the dial digit register Is
empty and can be loaded with a new digit to be dialed. If the DDEI bit is set,
the IRQ bit will be set when the DDRE bit is set. Also, the IRQ signal will be
generated.
After the DDR is loaded, DDRE goes to a 0 and the interrupts are
automatically cleared.
DL
Digital Loopback (Manual)
(O,I):A:5
When configuration bits DL are set to a I, the modem is manually placed in
digital loopback. DL should only be set during the data mode. The DSR and
CTS bits will be reset to a O. The local modem can then be tested from the
remote modem end by looping a remotely generated test pattern. At the
remote modem, all Interlace circuits behave normally as in the data mode.
At the conclusion of'the test, DL must be reset to a O. The local modem will
then return to the normal data mode with control reverting to the DTEs, DTA.
DL does not function in 300 bps.
DLO
Dial Line Occupied
1:8:7
When status bit DLO is a I, it indicates that the modem is In the auto dial
state, i.e., CRQ in the transmitter is a 1 and the modem is off-hook and
ready to dial.
DLSF
Disable Low Speed Fallbeck
I:C:O
When configuration bit DLSF is ai, the modem will not automatically
fallback to the 300 bps operating mode if it is configured for another data
rate. This bit is valid in originate mode only.
DSR
Data Set Ready
1:8:5
The ON condition of the status bit DSR Indicates that the modem is In the
data transfer state. The OFF condition of DSR IS an indication that the DTE
is to disregard all signals appearing on the interchange circuits - except RI.
DSR will switch to the OFF state when In test state. The ON condition of
DSR indicates the following:
The modem is not in the talk state, I.e., an associated telephone handset is
not in control of the line.
The modem is not in the process of automatically establishing a call via
pulse or DTMF dialing.
The modem has generated an answer tone or detected answer tone.
After ring indicate goes ON, DSR walts at least two seconds before turning
ON to allow the ,telephone comJ\any equipment to be engaged.
DSR will go OFF 50 msec after DTR goes OFF, or 50 msec plus a maximum
of 4 sec when the SSD bit is enabled.
DSRA
Data Set Ready in Analog
Loopback
I:C:7
' When configuration bit DSRA is a I, It causes DSR to be ON during analog
loopback.
1-60
R1212
1200 bps Full-Duplex Modem
Table 11.
Mnemonic
DTMF
Name
Touch Tones/Pulse Dialing
Interface Memory Definitions (Continued)
Memory
location
1:B:1
Deacrlptlon
When configuration bit DTMF is a 1, it tells the modem to auto dial using
tones; and when 0, the modem will dial using pulses.
The timing for the pulses and tones are as follows (power·on timing):
Pulses -
Relay open 64 ms
Relay closed 36 ms
Interdigit delay 750 ms
Tones -
Tone duration 95 ms
Interdigit delay 70 ms
The DTMF bit can be changed during the dialing process to allow either tone
or pulse dialing of consecutive digits. The output power level of the DTMF
tones is as follows:
± 15 dBm ± 1 measured at TXA for the R1212M
-1 dBm ± 1 measured at TIP/RING for the R1212DC
DTR
Data Terminal Ready
1:0:3
Control bit DTR must be a 1 for the modem to enter the data state, either
manually or automatically. DTR must also be a 1 in order for the modem to
automatically answer an incoming call.
During the data mode, DTR must remain at a 1, otherwise the connection will
be terminated if DTR resets to a 0 for greater than 50 ms.
EF
Enable Filters
ENSI
Enable New Status Interrupt
(O,1):E:6
When handshake bit ENSI is a 1, it causes an interrupt to occur when the
status bits in registers (0:[8,9]) and (1 :8) are changed by the modem.
(NEWS = 1). The IRO bit will be set to a 1 and the IRO signal will be
generated. The interrupt is cleared by writing a 0 into the NEWS bit.
ERDL
Enable Response to
Remote Digital Loopback
(O,1):A:7
When configuration bits ERDL are a 1, it enables the modem to respond to
another modem's remote digital loopback request, thus going into loopback.
When this occurs, the modem clamps RXD to a mark; resets the CTS, DSR
and RLSD bits to a 0 and turns the CTS, DSR and RLSD Signals to a logic 1.
The TM bit is set to inform the user of the test status. When th~ ERDL bits are
a 0, no response will be generated.
GTE
Guard Tone Enable
1:B:4
When configuration bit GTE is a 1, it causes the specified guard tone to be
transmitted (CCITI configurations only), according the state of the GTS bit. Note:
The guard tone will only be transmitted by the answering modem.
1:9:1
Setting CRO in the transmitter to a 1 disables the high and low band filters
used in data mode so that call progress tone detection can be done. Setting
CRO in the receiver to a 1 inserts a passband filter in the receive path which
passes energy in the 345 Hz to 635 Hz bandwidth. The high and low band
filters must be enabled and the passband filter disabled for the answer tone
and carrier to be detected. This occurs automatically during the auto dial process when EF is set to a O. In this case, the high and low band filters are
disabled when CRO in the transmitter is set to a 1. If tone detection is required, CRO in the receiver should be set to a 1. After dialing and call progress tone detection, CRO in the receiver is set to a 0 and FF is loaded into
the dial digit register. (Loading FF enables the high and low band filters). At
this time, the answer tone can be detected. To re-enable the high and low
band filters disabled by setting CRO in the transmitter, set EF to a 1. After
CRO in the transmitter and receiver is set to a 1 and tone detection is completed, it may be necessary to detect the answer tone before loading FF into
the dial digit register (see the section on sending 1300 Hz calling tone). At
that point, EF can be set to a 1 and CRO in the receiver set to a 0 so the
answer tone can be detected (using the ATD bit) and the 1300 Hz calling
tone can still be sent. Once the answer tone is detected, FF should be loaded into the dial digit register and the EF bit set to a O.
1-61
R1212
1200 bps Full-Duplex Modem
Table 11.
Mnemonic
Name
GTS
Guard Tone Select
IAQ
Interrupt
LCD
Loss of Carrier Disconnect
Interface Memory Definitions (Continued)
Memory
Location
Description
I:B:3
When configuration bit GTS is a 0, it selects the 1800 Hz tone; when GTE is
a 1 it selects the 550 Hz tone. The selected guard tone will be transmitted
only when GTE is enabled.
(O,I):E:7
When status bit IAQ is a I, it indicates that an interrupt has been generated.
The IAQ hardware signal is generated following the setting of the IAQ bit.
IAQ is cleared when either the NEWS bit is reset to a 0 or the DDA is
loaded with a number.
0:0:2
When configuration bit LCD is a I, the modem terminates a call when a loss
of received carrier energy is detected after 400 ms. After the first 40 ms of
loss of carrier. ALSO goes off. 380 ms later, if no carrier is detected, CTS
goes off, and the modem goes on-hook. If energy above threshold is
detected during the 360 ms period, ALSO will be set to a 1 again. If further
loss of energy occurs. the 400 ms time frame is restarted.
If LCD is set to a 0, ALSO will be set to a 1 when energy is above threshold,
but will not force the modem on-hook when energy falls below threshold. In
this case, it is necessary to re-enable LCD in order to put the modem on-hook.
LCD is not automatically disabled in leased line operation. The user must
write a 0 into LCD bits for this to occur.
LL
Leased Line
1:9:4
MODE
Mode Select
(O,I):A:(O,3)
When configuration bit LL is a I, the modem is in leased line operation;
when 0, the modem is in switched line operation. When LL is set to a I, the
modem immediately goes off-hook and into data mode.
These bits select the compatibility at which the modem is to operate, as
shown below:
Configuration Word
!
~
!
!!
0
0
0
1
1
1
1
0
0
1
0
0
0
0
1
1
0
0
0
1
1
0
1
0
0
1
0
1
Configuration
Bell 212A
Bell 212A
Bell 212A
V.22A
V.22B
V.22A
V.22B
1200 Sync.
1200 Async.
o to 300 Async.
1200 Sync.
1200 Async.
600 Sync.
600 Async.
NOTE: The Mode bits in both chips should be set exclusively of all other
bits, followed immediately by the setting of the NEWC bits. This will ensure
proper modem configuration.
Automatic Reconfiguretion
The modem is capable of automatically falling back during the handshake to
the compatibility of a remote modem. The modem can be in either the
answer or originate mode for this to occur. The compatibilities that the
modem are limited to adapt to are V.22 AlB (1200 bps), Bell 212 and
Bell 103. If the A1212 is to originate in a specific configuration, the MODE
bits must be set.
When the answer modem is configured for Bell 300 asynchronous and is
called by a 1200 bps modem, the handshake will be completed at 1200 bps.
NAT
No Answer Tone
1:9:7
When configuration bit NAT is a I, the modem will not transmit the 2100 Hz
CCITT answer tone. This bit is only valid for CCITT configurations. With this
bit enabled in answer mode, when the modem goes off-hook it will remain
silent for 75 ms and then transmit unscrambled ones.
1-62
1200 bps Full-Duplex Modem
R1212
Table 11. Interface Memory Definitions (Continued)
Mnemonic
Name
Memory
Location
Description
NEWC
New Configuration
(O,I):E:3
When the NEWC bit is a I, it tells the modem that a new configuration has
been written into the configuration registers. The modem will then read the
configuration registers and then reset NEWC to a O. NEWC must be set to a
1 after a new configuration has been written into the following ragisters:
(O:[A-D)) and (1 :[9-0)). The remaining registers do not require the use of
NEWC to tell the modem that new data was written into them.
NEWS
New Status
(O,I):E:5
When handshake bit NEWS is a I, ~ tells the user that there has been a
change of status in the status registers. The user must write a 0 into NEWS
to reset it. This action also causes the interrupt to be cleared.
NTS
No Transmitter Scrambler
1:9:0
When configuration bIt NTS is a I, when the modem is off·hook ~ will
transmit all data m an unscrambled form. This bit should be disablad if the
normal modem handshake is desired.
ORG
Originate/Answer
1:9:5
When ,C9nflguration bit ORG is a I, the modem is in onginate mode; and
when a 0 the modem is in answer mode. (This is only valid in manual
originate/answer and analog loopback). If ORG is a 1 in analog loopback, the
modem will transmit in the high band and receive in the low band. If ORG is
a 0 in analog loopback, the modem will transmit in the low band and receive
m the high band.
(None)
RAM Access R
0:F:0-7
Contains the RAM access code used in reading RAM locations in chip 0
(receiver device).
(None)
RAM Access T
I:F:0-7
Contains the RAM access code used in reading RAM locations in chip 1
(transmitter device).
XRAMRL
RAM Data XRL
0:2:0-7
Least significant byte of
XRAMRM
RAM Data XRM
0:3:0-7
Most significant byte of 16-bit word X used in reading RAM locations in chip O.
XRAMTL
RAM Data XTL
1.2:0-7
Least significant byte of 16-bit word X used in reading RAM locations in chip 1.
XRAMTM
RAM Data XTM
1:3:0-7
Most significant byte of 16-bit word X usad in reading RAM locations in chip 1.
YRAMRL
RAM Data YRL
0:4:0-7
Least significant byte of 16·bit word Y used in reading RAM locations in chip O.
YRAMRM
RAM Data YRM
0:5:0-7
Most significant byte of 16·b~ word Y used in reading RAM locations in chip O.
YRAMTL
RAM Data YTL
1:4:0-7
Least significant byte of 16-bit word Y used in reading RAM locations in chip 1.
YRAMTM
RAM Data YTM
1'5:0-7
Most significant byte of 16·bit word Y used in reading RAM locations in chip 1.
RDL
Remote Digital Loopback
(O,I):A:6
When configuration bits RDL are a I, it causes the modam to initiate a
request for the remote modem to go into digital loopback. RXD is clamped to
a mark and the CTS bit and CTS signal will be reset until the loop is
establishad. The TM bit is not set in this case, since the local modem in·
itiated the request. RDL does not function in 300 bps.
RI
Rmg Indicator
1:8:4
When status bit RI is a I, it indicates that a ringing signal is being detected.
The RI bit follows the ringing Signal w~.!!. a 1 during the on time and a zero
during the off time coincident with the RI signal. The following are the RI bit
response times:
16-b~
RI Bit Tranaltlon
OFF·to-ON'
ON·to-OFF
word X used in reading RAM locations in chip O.
Responsa
110 ± 50 ms (50% duty cycte)
450 ±5O ms
'The OFF·tcrON lime is duty cycle dependent: 890 ms (15%) .. lime .. 50 ms (100%)
This OFF·to-ON (or ON·to-OFF) response time is defined as the time interval
between the sudden connection (removal) of the ring signal across TIP and
RING and the subsequent trans~ion of the RI M.
1·63
R1212,
1200 bps Full-Duplex Modem
Table 11. Interface Memory Definitions (Continued)
Mnemonic
ALSO
Name
Received Line Signal
Detector
Memory
Location
0:8:0
Description
When status bit RLSD is a 1, it indicates that the carrier has successfully
been received. RLSD will not respond to the guard tones or answer tones.
RLSD response times are given below:
RLS01
OFF-to-ON
ON-to-OFF
Constant
Carrier
Controlled
Carrier
105 to 205 ms
10t024ms
105 to 205 ms
10 to 24 ms
Note:
1. After handshake has occurred.
ASD
Receive Space Disconnect
0:0:1
When configuration bit RSD is a 1, the modem goes on-hook after receiving
approximately 1,6 seconds of continuous spaces.
ATS
Request·to-Send
1:9:3
When cOl;llrol bit RTS is a 1, the modem transmits any data on TXD when
CTS bscomes active, In constant carrier mode, RTS should be set the same
time as DTR and then left ON, In controlled carrier operation, independent
oparation of RTS turns the carrier ON and OFF. The responses to RTS are
shown (assume the modem Is In data mode).
RTS Off
Leased or Dial Llne 1
RTS On
Controlled Carrier
CTS OFF
Carrier OFF
Carrier ON
210 to 275 ms Scrambled 1's
Transmitted
CTSON
Constant Carrier
CTS OFF
Carrier ON
Scrambled 1's
Transmitted
CTS ON
Carrier ON
Data Transmitted
Note:
1. After handshake is complele.
For ease of use in constant carrier mode, RTS should be turned ON the
same time as DTR.
SPEED
Speed Indication
0:9:(4,5)
The SPEED status bits reflect Ihe speed at which the modem is operating.
The SPEED bit representations are shown.
4
5
Speed
o
o
0
1
0
0-300
600
1200
Note:
The SPEED bits are not active
1-64
1
In
analog loopback and Illased line mode.
R1212
1200 bps Full-Duplex Modem
Table 11. Interface Memory Definitions (Continued)
Memory
Name
Mnemonic
SSD
Send Space Disconnect
ST
Self Test
Location
1:0'0
(O,I):A:4
Description
When configuration bit SSD is aI, it causes the modem to transmit
approximately 4 seconds of spaces before disconnecting, when DTR goes
from active to inactive state.
When configuration bit ST is a I, self test is activated. ST must be a 0 to end
the test. It Is possible to perform self test in analog loopback wtth or without a
DTE connected. During any self test, TXD and RTS are Ignored. Self test does
not test asynchronous-to-synchronous converter circuits in either the transmit·
ter or receiver.
Error detection is accompli~hed by monitoring the self test error counter in
the RAM. If the counter increments during the self test, an error was made.
The counter contents are available in the diagnostic register when the RAM
access code 00 is loaded In the diagnostic control register (O:F).
SeN Test End-to-End (Data Mode)
Upon activation of self test an internelly generated data pettern of alternate
binary ones and zeros (reversals) at the selected bit rete are applied to the
scrambler. An error detector, capable of identifying errors in a streem of
reversals are connected to the output of the descrambler.
SeN Test with Loop 3
Loop 3 is applied to the modem as defined in Recommendation V.54. Self
test is activated and DCE operation Is as In the end·to-end test, In this test
DTR is ignored.
SeN Test with Loop 2 (Data Mode)
The modem is conditioned to instigate a loop 2 at the remote modem as
specified in recommendation V.54. Self test is ectiveted and DCE operation
is as in the end-to-end test.
ST does not function in 300 bps.
3 dB Loss to Receive
Signal
I:B:2
When configuration btt 3DB is a I, it attenuates the received signal 3 dB.
This is only used if the modem will see 0 dBm or greater line signal at the
receiver input. Insertion of the 3 dB loss will then prevent saturation.
TM
Test Mode
0:8:1
When status btt TM is a I, it indicates that the modem has completed the
handshake and is in one of the following test modes: AL or RDL.
TONE
Tone Detect
0:8:7
TONE follows the energy detected in the 340 to 640 Hz frequency band. The
user must determine which tone is present on the line by determining the
duty cycle of the TONE bit. TONE is active only when CRa in chip 0 is a 1.
3DB
Detection Range: - 10 to - 43 dBm
Response Time: 17 ±2 ms
TXCLK
Transmtt Clock Select
I:C:(5,6)
TXCLK allows the user to designete the origin of the transmitter data clock,
as shown below:
Configuration Word
Transmit Clock
~
~
Internal
External
Slave
o
1
1
o
o
1
If external clock is chosen the user clock must be input at XTCLK. The clock
characteristics must be the same as TDCLK. The external clock will be
reflected by TDCLK.
If slave clock is chosen the transmitter is slaved to the receive clock. This is
also reflected by TDCLK.
1-65
R1212
1200 bps Full-Duplex Modem
Table 11. Interface Memory Definitions (Continued)
Memory
Location
Name
Mnemonic
I:B:(5-7)
Transmit Level
TX LEVEL
Description
TX LEVEL allows the user to change the transmit level at TIP and RING
(assuming the OAA has 10 dBm attenuation in the transmit path).
Configuration
Word
~
!
~
0
0
0
1
0
0
1
0
0
0
1
1
1
0
0
1
1
0
0
1
1
1
1
1
Transmit Level (:I: 1.0 dBm)
(at TIP and RING)
-10
-12
-14
-16
-18
-20
-22
-24
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
Internal Modem Timing
AUTO DIAL SEQUENCE
In a microprocessor environment it is necessary to know how
long various functions last or what the response times of certain
functions are. Since the modem is a part of the microprocessor
environment its timing and response times are necessary.
Table 12 provides the timing relationships between interface
memory bits and modem functions.
The following flow chart defines the auto dial sequence via the
microprocessor interface memory.
Table 12.
Internal Modem Timing
Paramater
Time Interval
NEWC bit checked
Transmitter
Receiver
Once per sample 1
Once per baud 2
NEWC bit set by host until
modem action
Transmitter
Receiver
s One baud time
One baud time
Control, Configuration bits read
Transmitter
Receiver
Status bits updated
Transmitter
Receiver
Status change reflected by
NEWS,IRQ
Transmitter
Receiver
Memory status reflected to
modem pin
Transmitter
Receiver
1. Sample Time
= 7200 Hz
Only after NEWC is set
ST, RSO-every sample,
all others after NEWC set
Once per sample
Once per baud
MIN < one sample lime
MAX one sample time
MIN one sample time
MAX one baud time
Figure 11. Auto Dial Sequence Flow Diagram
Note: The modem timing for the auto dialer accounts for inter·
digit delay for pulses and tones.
33.33
pS
33.33"s
2. Baud Time
= 600 Hz
1·66
R1212
1200 bps Full-Duplex Modem
SIGNAL PROCESSOR RAM ACCESS
access register 1:F, theXRAM registers 1:2 and 1:3 or the YRAM
registers 1:4 and 1:5, set the NEWC bit 1:E:3 to a 1. This action
causes the information to be transferred from interface memory
into SP RAM. Bit 7 of register I:F is cleared to a 0 by the modem
after the RAM is read. New data can be written into the SP RAM
after the NEWC bit is reset to a 0 by the SP.
RAM AND DATA ORGANIZATION
Each signal processor contains 128 words of random access
memory (RAM). Each word is 32-bits wide. Because the signal
processor is optimized for performing complex arithmetic, the
RAM words are frequently used for storing complex numbers.
Therefore, each word is organized into a real part (l6-bits) and an
imaginary part (l6-bits) that can be accessed independently.
The portion of the word that normally holds the real value is
referred to as XRAM. The portion that normally holds the imaginary value is referred to as YRAM. The entire contents of XRAM
and YRAM may be read by the host processor via the microprocessor interface.
Note:
Any transmitter RAM Write operation must always be preceded by a RAM read from the desired location. This is to
guarantee that the correct information is written into the 16
unchanged bits, since all transmitter RAM operations are
32 bit transiers with typically only 16 of the bits used.
Interface Memory Locations
Both the transmitter and receiver (chips 1 and 0, respectively)
allow data to be transferred from SP RAM into the interface memory. A 0 in transmitter bit 1:F:7 enables the SP to transfer 32 bits
of data from SP RAM to the XRAM and YRAM registers (16 bits
each) in the interface memory as specified by the RAM access
code in register 1:F. A 0 in receiver bit 0:F:7 enables the SP to
transfer 32 bits of data from SP RAM to the XRAM and YRAM
registers (16 bits each) in the interface memory as specified by
the access code in register O:F. To read the SP RAM in chip 1
(transmitter), load into 1:F the RAM access code which identifies
the 32 bits of data to transfer to the XRAM and YRAM registers.
Next, set the NEWC bit 1:E:3 to a 1. After transferring the data
from RAM to the XRAM or YRAM registers, the NEWC bit is reset
to a 0 by the SP. Chip 0 (receiver), on the other hand, will provide
the XRAM and YRAM data one sample time following the load-,
ing of the RAM access code into register O:F, and will continue to
provide the same data at one sample time intervals until a new
RAM access code is loaded.
The interface memory acts as an intermediary during these host
to signal processor RAM data exchanges. Information transfer
between RAM and interface memory is accomplished by the signal processor logic unit mOVing data between the SP main bus
and the SP 1/0 bus. The SP logic unit normally transfers a word
from RAM to interface memory once each clock cycle of the SP
device. In the transmitter, a word is transferred from SP RAM to
the interface memory every sample time. In the receiver, a word is
transferred from RAM to the interface memory every sample time
as well. Each RAM word transferred to the interface memory is
32-bits long. These bits are written by the SP logic unit into interface memory registers 5, 4, 3, and 2. Registers 3 and 2 contain
the most significant byte and least significant byte, respectively,
of the XRAM data. Registers 5 and 4 contain the most and least
significant bytes of YRAM data, respectively.
RAM Access Codes
The SP logic unit determines the SP RAM address to read from,
or write to, by the code stored in the RAM Access bits of interface
memory register F (RAM Access R in the receiver O:F and RAM
Access T in the transmitter 1:F).
When reading from or writing into RAM, no bits are provided for
handshaking or interrupt functions. The NEWC bit can be used
as a mechanism to provide sample and baud intervals. Since the
NEWC bit is checked, once per baud in chip 0 and once per
sample in chip 1, the user can set the NEWC bit and wait for it to
be cleared. Depending on which chip the NEWC bit was set, the
time interval from the setting to the clearing of the NEWC bit will
be either one sample or one baud time. This, however, will not
guarantee that the action of reading and writing the XRAM and
YRAM will occur in the middle of an actual sample or baud time.
Only the transmitter (chip 1) allows data to be transferred from
interface memory to SP RAM. When set to ai, bit 1:F:7 signals
the SP logic unit to disable transfer of SP RAM data to the interface memory, and instead, to transfer data from interface memory to SP RAM. When writing into SP RAM, 32 bits of data in the
XRAM and YRAM registers will be written into the appropriate
SP RAM location as specified by the RAM access code (82-86) in
register I:F (Table 13). Once the data is written into the RAM
1-67
R1212
1200 bps Full-Duplex Modem
Table 13
RAM Accass Codes
RAM A_Code
RAM Write
Chip
Reg. No.
40
41-40
14
01-00
53
11
-
0
0
0
0
0
0
0
2,3,4,5
2,3,4,5
2,3,4,5
2,3
2,3,4,5
2,3,4,5
2,3,4,5
51
-
0
2,3,4,5
-
0
0
0
0
2,3,4,5
4,5
2,3
·2,3
1
1
1
1
1
1
1
1
4,5
2,3
4,5
2,3
4,5
4,5
2,3
2,3
Node
Function
RAM Read
1
2
3
4
5
6
7
Demodulator Output
Low Pass Filter Output
Input Signal to Equalizer Taps
AGC Gain Word
Equalizer Tap Coefficients
Equalizer Output
Rotated Equalizer Output
(Received Point Eye Pattern)
Decision Points
(Ideal Eye Pattern)
Rotated Error
Rotation Angle
Phass Error
Self Teat Error Counter
56
6
9
10
11
12
52
12
10
00
DTMF Tone Duration
DTMF Interdigit Delay
Pulse Interdigtt Delay
Pulse Relay Make Time
Pulse Relay Break Time
Handshake Abort Counter
Handshake Abort Timer
CTS Off-Time
82
83
02
03
03
83
84
04
04
84
85
05
06
07
86
87
NOTE: 1. All the chip 1 access codes are not valid before R5312-13.
2. Access codes are hexadecimal.
3. Only chip 1 RAM can be written.
4.'CTS Off-Time is not valid before R5312-16.
ERROR RATES
Table 15. BER Summary
R1212
Bit error rate (BER) is a measure of the throughput of data on the
communication channel. It is the ratio of the number of received
bits in error to the number of transmitted bits. This number
increases with decreasing signal-to-nolse ratio (SNR). The type
of line disturbance and the modem configuration affect the BEA.
Bit Error Rate
Originate Mode
AnawerMode
1200 bps
1 x10- 5
8.3 dB
8.1 dB
600 bps
1 X 10- 5
5.0 dB
5.0 dB
300 bps
1 X 10- 5
10.4 dB
7.2 dB
=
Tables 14 through 16 summarize the SERs for verious conditions. Figure 12 shows the BER measurement setup.
Teat Condition: Signal Level
-43 dBm,
Sync for 1200 bps, 600 bps,
Async for 300 bps,
With 3002 Unconditioned Line.
Table 16. BER Summary
Table 14. BER Summary
R1212
Signal to Nolle Ratio
Date Rate
R1212
Signal to Nolee Ratio
SIgnal to Nolee Ratio
Data Rate
BIt Error Rate
Originate Mode
AnawerMode
Date Rate
Bit Error Rate
Originate Mode
AnawerMocle
1200 bps
1 x 10- 5
8.2 dB
7.9 dB
1200 bps
1 x 10- 5
7.7 dB
7.9 dB
600 bps
1 x10- 5
5.0 dB
5.0 dB
600 bps
1 x10- 5
4.6 dB
4.5 dB
300 bps
1 x10- 5
9.2 dB
7.0 dB
300 bps
1 x10- 5
9.3 dB
6.2 dB
=
Teat Condition: Signal Level = - 40 dBm,
Sync for 1200 bps, 600 bps,
Async for 300 bps,
Back·T0-8ack.
Teat Condition: Signal Level
-30 dBm,
Sync for 1200 bps, 600 bps,
Async for 300 bps,
With 3002 Unconditioned Line.
1·68
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----------
1200 bps Full-Duplex Modem
R1212
Table 17. Modem Power Requirements
Voltage
Tolerance
Current (Typical) @ 25°C
Current (Max) @ OOC
+5 Vdc
+12 Vdc
-12 Vdc
±5%
±5%
±5%
390mA
25mA
4mA
<455 mA
< 30 mA
< 5mA
Nota: All voHages must have ripple sO.1 volts peak-te-peak.
Table 18. Modem Environmental Restrictions
Parameter
Specification
Temperature
Operating
Storage
Relative Humidity:
Altitude
O°C to + 60°C (32°F to 140°F)
- 40°C to + 80°C (- 40°F to 176°F) (Stored in heat sealed antistatic bag and shipping contsiner)
Up to 00% noncondensing, or a wet bulb temperature up to 35°C, whichever is less.
-200 feet to + 10,000 feet
Table 19. Modem Mechanical Considerations
Paramater
Specification
Board Structure:
Single PC board with a 3-row 64-pin right angle male DIN connector with rows A and C populated.
The modem can also be ordered with the following DIN connector: 64-pin DIN right angle female,
64-pin DIN vertical male or 64-pin DIN vertical female.
Mating Connector:
Female 3-row 64-pin DIN reC9ptscle with rows A and C populated. Typical mating receptacle:
Winchester 968-6043-0531-1, Burndy R196B32RooAooZ1, or equivalent.
PCB Dimensions:
DC Version
Width
Length
Height
M Version
Width
Length
Height
Weight (max):
Lead Extrusion (max.):
3.937 In. (100 mm)
4.725 in. (120 mm)
0.75 in. (19 mm)
3.937 In.
3.328 in.
0.40 in.
0.45 Ibs.
0.100 in.
(100 mm)
(82 mm)
(10.2 mm)
(0.20 kg.)
(2.54 mm)
1-70
R1212
1200 bps Full-Duplex Modem
I
0.156 ± .003 DIA (4 PL)
(3.96)
---
MALE 64-PIN
DIN CONNECTOR
1~
£
f
0.156 ± .003 DIA (4 PL)
(3.96)
It- T
MALE 64-PIN
DIN CONNECTOR
T"
T
I
3.937
COMPONENT
SIDE
0.496
(12.6)
T~
COMPONENT
SIDE
Li
0.119
(3)
)---
--
-
1
0.496
(12.6)
1
---------- ----------~J:~~
_____ 2.625
3.275 (66.1)
O.
(1
4.100 (83.2)
0.200 MAX
/
1
COMPONENT AREA
~~-----_-- __/-n_,[D~~
~;i~
-rt:.062
(16)
•
0.100 MAX
(104) 4.725
(120)
r-----~,---------------------~ n-----r1_ ~~:~~~MAX-------- --- --- - --~~
1 1- - - - -
1(2.54)
--(1.6)
COMPONENT AREA
(2.54)
Figure 13.
0.100
Modem Printed Circuit Board Dimensions
1-71
MAX
R1212
1200 bps Full-Duplex Modem
FCC RULES PART 68 REQUIREMENTS
R1212 MODEM INSTALLATION AND
MAINTENANCE
The FCC Rules Part 68 requires that the telephone interface
leads shall:
This section contains installation instructions and maintenance
procedures forthe Rockwell R1212DC Modem. It also contains a
special notice from the Canadian Department of Communications (DOC) for Canadian operation and from the Federal Communications Commission (FCC) for United States operation.
1. Be reasonably phYSically separated and restrained from; not
routed in the same cable as; nor use the same connector as
leads or metallic paths connecting to power connections.
Note
GENERAL DESCRIPTION
Power connections are defined as the connections
between commercial power and any transformer, power
supply rectifier, converter or other circuitry associated
with the modem. The connections of the interface pins
(including the + 12 Vdc, -12 Vdcand +5 Vdc) are not
considered power connections.
The Rockwell R1212DC modem is designed to be used with the
United States or Canadian Telephone Switched Networks in 2wire full-duplex dial-up operation. The modem requires protective circuitry registered with the Federal Communications Commission (FCC) Part 68 which allows direct connection to the U.S.
switched telephone network. This circuitry also complies with
the Canadian Department of Communications (DOC) Terminal
Attachment Program (TAP) which similarly defines their
switched telephone network requirements.
2. Be reasonably physically separated and restrained from; not
routed in the same cable as; nor use adjacent pins on the
same connector as metalliC paths that lead to unregistered
equipment, when specification details provided to the FCC do
not show that the interface voltages are less than nonhazardous voltage source limits in Part 68.
The R1212DC features automatic dial and answer capabilities
along with surge suppression and hazardous voltage and longitudinal balance protection. Its maximum output signal level at the
telephone interface is set at -10 dBm ± 1 dBm (permissive
mode of operation).
Note
All the DIN connector interface voltages to the modem
have been established as non-hazardous.
Two standard telephone jack connectors (RJ11 s) are mounted
side by side on one edge of the board and are wired in parallel.
One is for connection to the telephone line network and the other
for the telephone headset connection.
ROUTING OF TELEPHONE INTERFACE LINES
In routing the telephone interface leads from the modem telephone connector jacks to the telephone line network connection,
the following precautions should be strongly considered for
safety.
INSTALLATION AND SIGNAL ROUTING
INSTRUCTIONS
1. The telephone interface routing path should be as direct and
as short as possible.
PHYSICAL MOUNTING
2. Any cable used In establishing this path should contain no
signal leads other than the modem telephone interface leads.
The modem module may be physically incorporated into the customer's end product by utilizing the four corner 0.156" diameter
mounting holes (for the self-hooking plastic type standoffs or for
bolting it down to some rigid structure) or by installing the module
into card guides.
3. Any connector used in establishing this path shall contain not
commercial power source signal leads, and adjacent pins to
the TIP and RING (T and R) pins in any such connector shall
not be utilized by any signals other than those shown in this
document.
ELECTRICAL INTERFACING INSTRUCTIONS
The electrical interfacing is accomplished via the DIN (Euro) connector (for external power inputs and digital logiC signals) and
the telco connectors (for the telephone network connection).
Note that the telephone interface connectors are physically separated from the modem interface control connector and extreme
care must be taken in routing the telephone interface leads from
the modem to the telephone network (line connector jack In the
wall).
MAINTENANCE PROCEDURE
Under the FCC Rules, no customer is authorized to repair
modems. In the event of a Rockwell modem malfunctioning,
return it for repair to an authorized ROCKWELL INTERNATIONAL distributor (if in Canada) or send it directly to the Semiconductor Products Division, Rockwell International Corporation, EI Paso, Texas 79906.
1-72
1200 bps Full-Duplex Modem
R1212
Sample label below:
SPECIAL INSTRUCTION TO USERS
Unit contains Registered Protective Circuitry which complies with Part 68 of FCC Rules.
If the Rockwell modem has been registered with the Federal
Communications Commission (FCC), you must observe the following to comply with the FCC regulations:
FCC Registration Number: AMQ9SQ-14211-DM-E
A. All direct connections to the telephone lines shall be made
Ringer Equivalence: 0.9B
through standard plugs and telephone company provided
jacks.
Note
B. It is prohibited to connect the modem to pay telephones or
party lines.
The Rockwell modem module has the FCC registration
number and ringer equivalence number permanently
affixed to the solder side of the PCB and any unit containing this modem shall use this information for the
label requirements.
C. You are required to notify the local telephone company of the
connection or disconnection of the modem, the FCC registration number, the ringer equivalence number, the particular line
to which the connection is made and the telephone number to
be associated with the jack.
Note
SPECIAL NOTICE FROM THE CANADIAN
DEPARTMENT OF COMMUNICATIONS
If the proper jacks are not available, you must order the
proper type of jacks to be installed by the telephone
company (VSOC RJll for permissive mode of operation).
The Canadian Department of Communications label identifies
certified equipment. This certification means that the equipment
meets certain telecommunications network protective, operational and safety requirements. The Department does not guarantee the equipment will operate to the user's satisfaction.
D. You should disconnect the modem from the telephone line if it
appears to be malfunctioning. Reconnect it only if it can be
determined that the telephone line and not the modem is the
source of trouble. If the Rockwell modem needs repair, return
it tothe ROCKWELL INTERNATIONAL CORPORATION. This
applies to the modem whether it is in or out of warranty. Do not
attempt to repair the unit as this is a violation of the FCC rules
and may cause danger to persons or to the telephone network.
Before installing this equipment, users should insure that it is
permiSSible to be connected to the facilities of the local telecommunications company. The equipment must also be installed
using an approved method of connection. In some cases, the
company's inside wiring associated with a single line individual
service may be extended by means of a certified jack-plug-cord
ensemble (telephone extension cord). The customer should be
aware that the compliance with the above conditions may not
prevent degradation of service in some situations. Existing telecommunications company requirements do not permit their
equipment to be connected to customer-provided jacks except
where specified by individual telecommunications company tariffs.
TELEPHONE COMPANY RIGHTS
AND RESPONSIBILITIES
A. The Rockwell modem contains protective circuitry to prevent
harmful voltages to be transmitted to the telephone network. If
such harmful voltages do occur, then the telephone company
may temporarily discontinue service to you. In this case, the
telephone company should:
The Department of Communications requires the Certificate
Holders to identify the method of network connection in the user
literature provided with the certified terminal equipment.
1. Promptly notify you of the discontinuance.
2. Afford you the opportunity to correct the situation which
caused the discontinuance.
Repairs to certified equipment should be made by an authorized
Canadian maintenance facility designated by the supplier. Any
repairs or alterations made by the user to this equipment, or
equipment malfunctions may give the telecommunications company cause to request the user to disconnect the equipment.
3. Inform you of your right to bring a complaint to the FCC
concerning the discontinuance.
B. The telephone company may make changes in its facilities
and services which may affect the operation of your equipment. It is, however, tile telephone company's responsibility to
give you adequate notice in writing to allow you to maintain
uninterrupted service.
Users should ensure for their own protection that the electrical
ground connections of the power utility, telephone lines and internal metallic water pipe system, if present, are connected
together. This precaution may be particularly important in rural
areas.
LABELING REQUIREMENTS
CAUTION
A. The FCC requires that the following label be prominently displayed on the outside surface of the customer's end product
and that the size of the label should be such that all the
required information is legible without magnification.
Users should not attempt to make such connections themselves, but should contact the appropriate electric inspection authority, or electrician, as appropriate.
1-73
R2424
Integral Modems
'1'
Rockwell
R2424
2400 bps Full-Duplex Modem
INTRODUCTION
FEATURES
The Rockwell R2424 is a high performance full-duplex 2400 bps
modem. Using state-of-the-art VLSI and signal processing technology, the R2424 provides enhanced performance and reliability. The modem is assembled as a small module with a DIN connector (R2424M and R2424DC) or a new, smaller module (seven
square inches) with a dual-in-line pin (DIP) interface.
•
•
•
•
•
Being CCITT V.22 bis, V.22 A, B compatible, as well as Bell 212A
and 103 compatible, the R2424 fits most applications for fullduplex 2400 and 1200 bps fallback (synchronous and asynchronous) and 0 to 300 bps asynchronous data transmission over the
general switched telephone network, and over point-to-point
leased lines.
•
•
•
•
•
•
•
•
The direct-connect, auto dial/answer features are specifically
designed for remote and central site computer applications. The bus
interface allows easy integration into a personal computer, box
modem, microcomputer, terminal or any other microprocessor.
based communications product.
The R2424DM, with its small form factor and DIP connection,
can be automatically installed and soldered onto a host module.
Its small size is ideal for internal "1/2-card" PC modem
applications.
•
CCITT V.22 bis, V.22 A, B Compatible
Bell 212A and 103 Compatible
Synchronous: 2400 bps, 1200 bps, 600 bps ± 0.01 %
Asynchronous: 2400 bps, 1200 bps, 600 bps + 1%, - 2.5%,
0-300 bps
- Character Length 8, 9, 10, or 11 bits
DTE Interface
- Functional: CCITT V.24 (RS-232-C) (Data/Control) and
Microprocessor Bus (Data/Configuration/Control)
- Electrical: TTL Compatible
2-wire Full-Duplex Operation
Adaptive and Fixed Compromize Equalization
Test Configurations:
- Local Analog Loopback
- Remote Digital Loopback
- Self Test
Auto/Manual Answer
Auto/Manual Dial-DTMF Tone or Pulse Dial
Power Consumption: 2:3 Watts Typical
Power Requirements: + 5 Vdc, ± 12 Vdc
Three Module Configurations:
- R2424DC (Direct Connect): DIN connector module with
FCC approved DAA Part 68 Interface
- R2424M: DIN connector module without DAA
- R2424DM: DIP connection module without DAA
Two Functional Versions
- R2424/US All data rates specified except 600 bps
- R2424/INT All data rates specified except 0-300 bps
R2424M Modem
Document No. 29200N11
R2424DM Modem
Data Sheet
1-74
Order No_ MD11
Rev. 6, January 1989
R2424
2400 bps Full-Duplex Modem
TECHNICAL SPECIFICATIONS
3. DTMF Tones: The R2424 generates dual tone multifrequency tones. When the transmission of DTMF tones are
required, the CRO and DTMF bits (see Interface Memory
Definitions)must be set to a 1. When in this mode, the specific
DTMF tones generated are decided by loading the dial digit
register with the appropriate digit as shown in Table 2 .
TRANSMITTER CARRIER AND SIGNALING
FREQUENCIES
The transmitter and signaling frequencies supported in the
R2424 are listed in Table 1.
Table 1.
Table 2.
Transmitter Carrier and Signaling
Frequencies Specifications
Frequency
(Hz ±O.O1%)
Mode
V.22 bls low channel, Originate Mode
V.22 low channel, Originate Mode
V.22 bis high channel. Answer Mode
V.22 high channel, Answer Mode
Bell 212A high channel Answer Mode
Bell 212A low channel Originate Mode
Bell 103/113 Originating Mark
Bell 103/113 Originating Space
Bell 103/113 Answer Mark
Bell 103/113 Answer Space
Hex
00
01
02
03
04
05
06
07
08
09
OA
OB
OC
OD
OE
OF
1200
1200
2400
2400
2400
1200
1270
1070
2225
2025
TONE GENERATION
The specifications for tone generation are as follows:
1. Answer Tones: The R2424 generates echo disabling tones
for both the CCITT and Bell configurations, as follows:
a. CCITT: 2100 Hz ± 15 Hz.
b. Bell: 2225 Hz ± 10 Hz.
2. Guard Tones: If GTS (see Interface Memory Definitions) is
low, an 1800 Hz guard tone frequency is selected; if GTS is
high, a 553.B46 Hz tone is employed. In accordance with the
CCITT V.22 Recommendation, the level of transmitted power
for the 1BOOHz guard tone is 6 ± 1 dB below the level of the
data power in the main channel. The total power transmitted
to the line is the same whether or not a guard tone is enabled.
If a 553.B46 Hz guard is used, its transmitted power is
3 ± 1 dB below the level of the main channel power, and again
the overall power transmitted to the line will remain constant
whether or not a guard tone is enabled. The device accomplishes this by reducing the main channel transmit path gain
by .97 dB and 1.76 dB for the cases of the 1BOO Hz and
553.B46 Hz guard tones respectively.
Table 3.
Operating Mode
Dial Digits/Tone Pairs
Dial
Digits
Tone Pairs
941
697
697
697
770
770
770
852
852
852
941
697
770
852
941
941
0
1
2
3
4
5
6
7
8
9
*
Spare (B)
Spare (C)
Spare (D)
#
Spare (F)
10
1300 Hz Calling Tone
TONE DETECTION
The R2424 detects tones in the 340 ± 5 Hz to 640
Detection Level: -10 dBm to -43 dBm
Response Time: 17 ±2 ms
SIGNALING AND DATA RATES
Signaling and Data Rates
Data Rate
Signaling Rate (Baud)
600
Synchronous/Asynchronous, 2400 bps ±0.01%
V.22 bls:
600
Synchronous/Asynchronous, 1200 bps ± 0.01 %
V.22:
(Alternative A)
Mode I
600
1200 bps ± 0.01 % Synchronous
600
600 bps ± 0.01 % Synchronous
600
600
1200 bps ± 0.01 % Synchronous
600 bps ± 0.01 % Synchronous
III
(Alternative B)
Mode i
Mode Iii
± 5 Hz band.
The signaling and data rates for the R2424 are defined in
Table 3.
V.22 bis:
Mode
1336
1209
1336
1477
1209
1336
1477
1209
1336
1477
1209
1633
1633
1633
1477
1633
Mode ii
1200 bps Asynchronous, 8, 9, 10 or 11 Bits Per Character
Mode iv
600 bps Asynchronous, 8, 9, 10 or 11 Bits Per Character
Bell 212A;
1200 bps ±0.01%, Synchronous/Asynchronous
o to 300 bps Asynchronous
600
o to 300
1-75
•
R2424
2400 bps Full-Duplex Modem
o dBm
DATA ENCODING
±1.0 dBm. The DAA then determines the permissive or
programmable configuration.
The specifications for data encoding are as follows:
1. 2400 bps (11,22 bis). The transmitted data is divided into
groups of four consecutive bits (quad bits) forming a 16-point
signal structure.
The R2424DC transmit level is strapped in the permissive mode
so that the maximum output level is -10 dBm ± 1.0 dBm.
2. 1200 bps (11,22 and Bell 212A). The transmitted data is
divided into groups of two consecutive bits (dibits) forming a
four-point signal structure.
AUTOMATIC SPEED RECOGNITION
The R2424 is capable of automatically configuring itself to the
compatibility of a remote modem. The R2424 can be in either the
answer or originate mode for this to occur. The compatibilities
that the R2424 are limited to adapt to are V.22 bis, V.22 AlB
(1200 bps), Bell 212, and Bell 103. If the R2424 is to originate in
a specific configuration, the MODE bits (see Interface Memory
Definitions)must be set.
3. 600 bps (11,22). Each bit is encoded as a phase change relative to the phase preceding signal elements.
EQUALIZERS
The R2424 provides equalization functions that improve performance when operating over low quality lines.
Automatic Adaptive Equalizer-An automatic adaptive equalizer is provided in the receiver circuit for V.22 bis, V.22 and Bell
212A configurations.
MODEM OPERATION
Because the modem is implemented in firmware executed by a
specialized computer (the signal processor), operation can best
be understood by dividing this section into hardware circuits and
software circuits. Hardware circuits include all pins on the
modem connector. Software circuits include configuration, control (soft strapping), status, and RAM access routines.
Fixed Compromise Equalizer-A fixed compromise equalizer
is provided in the transmitter.
TRANSMITTED DATA SPECTRUM
After making allowance for the nominal specified compromise
equalizer characteristic, the transmitted line signal has a frequency spectrum shaped by the square root of a 75 percent
raised cosine filter. Similarly, the group delay of the transmitter
output is within ± 150 microseconds over the frequency range
900 to 1500 Hz (low channel) and 2100 to 2700 Hz (high channel).
HARDWARE CIRCUITS
The functional interconnect diagram (Figure 1) shows the
modem connected into a system. In this diagram, any point that
is active when exhibiting the relatively more negative voltage of a
two voltage system (e.g., 0 Vdc for TTL or - 12 Vdc for
RS-232-C) is called low active and is represented by association
with a small circle at the signal point. The particular voltage levels used to represent the binary states do not change the logic
symbol. Two types of 110 pOints that may cause confusion are
edge-triggered inputs and open-collector (open-source or opendrain) outputs. These signal points include the additional notation of a small triangle or a small half-circle (see signal IRQ),
respectively. Active low signals are named with an overscore
(e.g., paR). In deciding whether a clock output is high active or
low active, the convention followed is to assume that the clocking
(activating) edge appropriate to the host hardware is a transition
from the clocks active to its inactive state (I.e., a trailing edge
trigger). A clock intended to activate logic on its rising edge is
called low active while a clock intended to activate logic on its
falling edge is called high active. When a clock input is associated with a small circle, the input activates on a falling edge. If
no circle is shown, the input activates on a riSing edge.
SCRAMBLER/DESCRAMBLER
The R2424 incorporates a self-synchronizing scrambler/descrambler. In accordance with the CCITT V.22 bis, V.22 and
the Bell 212A recommendations.
RECEIVED SIGNAL FREQUENCY TOLERANCE
The receiver circuit of the R2424 can adapt to received frequency
errors of up to ± 7 Hz with less than a 0.2 dBm degradation in
BER performance.
RECEIVE LEVEL
The receiver circuit of the R2424 satisfies all specified performance requirements for the received line signals from -10 dBm to
- 48 dBm. The received line signal is measured at the receiver
analog input RXA.
TRANSMIT LEVEL
The R2424M, R2424DM and R2424DC output control circuitry
contains a variable gain buffer which reduces the modem output
level. All three R2424 modems can be strapped via the host interface memory to accomplish this.
The interconnect signals on Figure 1 are organized into six
groups of modem operation: overhead Signals, V.24 interface
signals, microprocessor interface signals, DAA signals, analog
Signals, and ancillary signals. Table 4 lists these groups along
with their corresponding connector pin numbers. The column
titled "Type:' refers to designations found in the Hardware Circuits Interface Characteristics (Tables 5 and 6). The six groups
of hardware circuits are described in the following paragraphs.
PERMISSIVE/PROGRAMMABLE CONFIGURATIONS
The R2424M transmit level is + 6 dBm to allow a Data Access
Arrangement (DAA) to be used. The R2424DM transmit level is
1-76
2400 bps Full-Duplex Modem
R2424
POWER-ON RESET
•
•
•
•
•
•
•
•
Basic modem operation can be understood most easily by beginning with the modem configured to default conditions. When the
modem is initially energized a signal called Power-On-Reset
(POR) causes the modem to assume a valid operational state.
The modem drives pin 13C to ground during the beginning of the
POR sequence. Approximately 3S0 ms after the low to high transition of pin 13C, the modem is ready for normal use. The POR
sequence is reinitiated anytime the + SV supply drops below
+ 3.SV for more than 30 ms, or an external device drives pin 13C
low for at least 31's. When an external low input is applied to
pin 13C, the modem is ready for normal use approximately
3S0 ms after the low input is removed. Pin 13C is not driven low
by the modem when the POR sequence is initiated externally. In
all cases, the POR sequence requires 3S0 ms to complete. The
R2424 POR sequence leaves the modem configured as follows:
ThiS configuration is suitable for performing high speed data
transfer over the public switched telephone network using the
serial data port. Individual features are discussed in subsequent
paragraphs.
r- - - - - - - - - - - ----,
RTS
CTS
I
I
I
I
TXD
TDCLK
XTCLK
RLSO
RXD
V 24
INTERFACE
-"
RDCLK
DTR
DSR
X
RI
r
I
~
DECODER
r
R2424
MODEM
LINE MONITOR
ANALOG
INTERFACE
I
TIP
I
RING
}
TELEPHONE
LINE
R2424D
I
I
I
RCCT'
,---
CCT'
OH' OR OH2
I
I
DAA
AD' OR R02
I
I
I
I
I
I
~}T
'----
I
CS (2)
RXA
I
TXA
I
I
ANALOG
INTERFACE
ELEPHONE
LINE
I
I
I
I
I
I
L_ - - - - - - -R2424M/R242
- - - 4~O~YJ
I
POR
INTERFACE
- - - - - - - - - - ~N.:.Y_J
r- - - - - - - - - - - - ---,
IRQ
+5
CIRCUIT
-L
L_
WRITE
DATA BUS (8)
_ADDRESS BUS (4)
HOST
I
I
ANCILLARY
OH
I
READ' OR REA02
PROCESSOR
(DTE)
2400 bps
Asynch ronous
1O-bit Character length
Constant Carrier
Serial Control Mode
Answer Mode
Auto Answer Disabled
RAM Access Code = 00
TBCLK
I)
RBCLK
h.
TLK'
ORG'
+5V
ANCILLARY
CIRCUIT
INTERFACE
+12V
POWER
SUPPLY
-12V
AGND
DGND
Figure 1.
NOTES:
1 = DIN MODU LE ONLY.
2 = DIP MODULE ONLY.
R2424 Modem Functional Interconnect Diagram
1-77
R2424
2400 bps Full-Duplex Modem
Table 4.
Name
Type
DIN
Pin No.
DIP'
Pin No.
Hardware Circuits
Description
Name
A. OVERHEAD SIGNALS
AGND
31C,32C
23,39
Ground (D)
DGND
+5 volts
PWR
+12 volts
-12 volts
POR
PWR
PWR
1I0B
3C,8C,
5A, IDA
19C,23C,
26C,30C
15A
12A
13C
22,40,
51,60
1,21,
61
24
27
15
Analog Ground
Return
Digital Ground
Return
+ 5 volt supply
+ 12 volt supply
- 12 volt supply
Power-on-Reset
B. MICROPROCESSOR INTERFACE SIGNALS
CSI
READ
READ
WRITE
IRQ
1I0A
1I0A
1I0A
1I0A
1I0A
1I0A
1I0A
1I0A
IA
IA
IA
IA
IA
52
53
54
55
56
57
58
59
45
44
43
42
48
lC
lA
2C
2A
3A
4C
4A
5C
6C
6A
7C
7A
10C
IA
9C
IA
IA
IA
OB
DIP
Pin No.
Description
C. V.24 INTERFACE SIGNALS
Ground (A)
07
06
05
04
03
D2
Dl
DO
RS3
RS2
RSI
RSO
CSO
DIN
Pin No.
Type
llA
llC
2
TDCLK
RDCLK
RTS
CTS
TXD
RXD
RLSD
OC
OC
IB
OC
IB
OC
OC
23A
21A
25A
25C
24C
22C
24A
7
8
4
5
10
11
DTR
DSR
IB
OC
OC
21C
20A
18A
13
14
32A
31A
25
26
RJll Jacks
-
Receive Analog Input
Transmit Analog
Output
Phone Line Interface
30A
-
Analog Line MOnitor
-
Ring Detect
Ring Detect
Request Coupler Cut
Through
Coupler Cut Through
Off-Hook Relay Status
Off-Hook Relay Status
RXA (M/DM)
TXA (M/DM)
1
IB
OC
TIP/RING (DC) AE
LINE
MONITOR (DC) AD
t
Register Select
47
49
50
22A
-
-
External Transmit
Clock
Transmit Data Clock
Receive Data Clock
Request-to-Send
Clear-to-Send
Transmit Data
Receive Data
Received Line Signal
Detector
Data Terminal Ready
Data Set Ready
Ring Indicator
D ANALOG SIGNALS
Data Bus (8-Lines) 0
-
12C
-
IB
Ai
r
41
XTCLK
(4-LineS~
E. DAA INTERFACE SIGNALS
Chip Select
Receiver (Baud
Rate Device)
Chip Select Transmitter (Sample
Rate Device)
Read Enable
Read Enable
Write Enable
Interrupt Request
RD (M)
RD (OM)
RCCT (M)
IB
IB
OC
27A
28A
-
CCT(M)
OH
OH
IB
OC
OC
29C
29A
-
-
35
-
36
F. ANCILLARY INTERFACE SIGNALS
TBCLK
RBCLK
TLK
ORG
°Note: The R2424DM is only used in parallel control mode.
Thus, the Bus Select bits must be set to a 1 when uSing
the R2424DM.
OC
OC
IC
IB
27C
26A
28C
16C
6
9
-
Transmit Baud Clock
Receive Baud Clock
Talk (TLK = Data)
Originate
(ORG = Answer)
(M) R2424M only. (DC) R2424DC only. - = not applicable
(OM) R2424DM only.
Unused inputs lied to +5V or ground require indiVidual 10K Il series
resistors
Table 5
Digital Interface Characteristics
Input/Ouput Type
Symbol
Parameter
V ,H
Input Voltage, High
V ,l
VOH
VOL
I'N
10H
10L
IL
Ipu
Input Voltage, Low
Output Voltage, High
Output Voltage, Low
Input Current, Leakage
Output Current, High
Output Current, Low
Output Current, Leakage
Pull-up Current
(Short Circuit)
Capacitive Load
Capacitive Drive
CirCUit Type
CL
Co
Notes: 1. I load
=
-100 pA
Units
IA
IB
IC
V
2.0 min.
2.0 min.
2.0 min.
V
V
V
pA
rnA
rnA
0.8 max.
0.8 max.
0.8 max.
OA
OC
110 A
2.0 min.
2.4 min.'
0.4 max'
0.4 max.'
0.4 max.'
1.6 max.
±10 max.
1.6 max.
±25 max.
-0.1 max.
1.6 max.
pA
pA
pF
pF
2. I load
OB
5
TTL
=
1.6 rnA
-240 max.
-10 min.
5
-240 max
-10 m,n.
20
TTL
w/Pull-up
TTL
w/Pull-up
3 !load
=
-40 pA
1-78
4. V'N
0.8
2.4
0.4
±2.5
1I0B
5.25
2.0
max. 0.8
min.' 2.4
max' 0.4
max.'
max.
min.
max.
min. 3
max. s
-240 max.
-10 min.
100
TTL
-260 max.
-100 min.
10
40
100
100
100
100
Open-Drain Open-Drain
3 State
Open-Drain
w/Pull-up Transceiver w/Pull-up
= 0.4 to 2.4 Vdc,
Vee
= 525
Vdc
5. I load
= 0.36
rnA
2400 bps Full-Duplex Modem
R2424
Table 6.
Name
TXA
RXA
Analog Interface Characteristics
Type
Characteristics
AA
The transmitter output impedance is 60411
± t % with an output level of + 6 dBm.
To obtain a 0 dBm output, a 60011 load to
ground is needed.
AB
disregard all signals appearing on the interchange circuitsexcept Ai. DSR will switch to the OFF state when in test state.
The ON condition of OSR indicates the follOWing:
1. The modem is not in the talk state, I.e., an associated telephone handset is not in control of the line.
2. The modem is not in the process of automatically establishing
a call via pulse or DTMF dialing.
The receiver input Impedance IS 23.7 KI1
±1%. The receive level at RXA must be
no greater than - 9 dBm (or - 6 dBm
with the 3DB bit enabled).
LINE
MONITOR
AD
The line monitor output impedance is
15 KI1 ±5%.
TIP/RING
AE
The impedance of TIP wHh respect to
RING is 600 11.
3. The modem has generated an answer tone or detected
answer tone.
4. After ring indicate (Ai) goes ON, DSR waits at least two seconds before turning ON to allow the telephone company
equipment to be engaged.
DSR will go OFF 50 ms after OTR goes OFF, or 50 ms plus a
maximum of 4 seconds when the SSD bit is enabled.
V.24 INTERFACE
Request To Send (ATS)
Eleven hardware circuits provide timing, data, and control signals for implementing a serial interface compatible with CCITT
Recommendation V.24. These signals interface directly with circuits using TTL logic levels (OV, +5V). These TTL levels are
suitable for driving the short wire lengths or printed circuitry normally found within stand-alone modem enclosures or equipment
cabinets. For driving longer cables, the voltage levels and connector arrangement recommended by EIA standard RS-232-C
are preferred.
RTS ON allows the modem to transmit data on TXD when ers
becomes active. In constant carrier mode, RTS can be wired to
DTR. In controlled carrier operation, independent operation of
RTS turns the carrier ON and OFF. The responses to RTS are
shown in Table 7 (assume the modem Is in data mode).
Table 7_
RTS OFF
Leased or Dial L1na'
The sequence of events leading to successful data transfer from
transmitter to receiver is:
RTS Responses
CTS OFF
Carrier OFF
Carrier ON
210 to 275 ms Scrambled
IS Transmitted
CTSON
Constant Carrier
CTS OFF
Carrier ON
Scrambled Is
Transmitted
CTSON
Carrier ON
Data Transmitted
1. The transmitter is activated and a training sequence is sent.
2. The receiver detects channel energy above the prescribed
threshold level and synchronizes its operation to the
transmitter.
RTSON
Controlled Carrier
Note:
1. After handshake is complste.
3. Data transfer proceeds to the end of the message.
4. The transmitter turns off after insuring that all data has had
time to be recovered at the receiver output.
Clear To Send (CTS)
Data Terminal Ready (DTR)
ers ON indicates to the terminal equipment that the modem will
transmit any data which is present on TXD. crs response times
from an ON or OFF condition of RTS are shown in Table 8.
DTR prepares the modem to be connected to the communications channel, and maintains the connection established by the
DTE (manual answering) or internal (automatic answering)
means. DTR OFF places the modem in the disconnect state.
Table 8_ CTS Response Times
Data Set Ready (DSR)
Data Set Ready (D~ON indicates that the modem is in the
data transfer state. DSR OFF is an indication that the OTE is to
CTS Transition
Constant Carrier
Controlled Carriar
OFF to ON
ON to OFF
<2 ms
<20 ms'
210 to 275 ms
<20 ms'
Note: 'Programmable
1-79
2400 bps Full-Duplex Modem
R2424
Transmit Data Clock (TDCLK)
RLSD will not respond'to guard tones or answer tones.
The modem provides a Transmit Data Clock (TDCLK) output wi1h
the following characteristics:
'
When RLSD is active. it indicates to the terminal equipment that
valid data is available on RXD.
1. Frequency. Selected data rate of 2400 Hz. 1200 Hz or 600 Hz
Transmitted Data (TXD)
(±0.01%).
2. Duty Cycle. 50
The modem obtains serial data from the local DTE on this input.
± 1%.
TDCLK is provided to the user in both asynchronous and synchronous communications. TDCLK is not necessary in asynchronous communication but it can be used to supply a clock for
UARTfUSART timing (TDCLK is not valid in FSK). TDCLK is necessary for synchronous communication. In this case Transmit
Data (TXD) must be stable during the one f.'S periods immediately preceding and following the rising edge of TDCLK.
Received Data (RXD)
The modem presents received data to the local DTE on this
output.
Ring Indicator (RI)
The modem provides a Ring Indicator (Ai) output; its low state
indicates the presence of a ring signal on the line. The low condition appears approximately coincident with the ON segment of
the ring cycle (during rings) on the communication c!lannel. (The
ring signal cycle is typically two seconds ON. four seconds OFF.)
The high condition of the Ai output is maintained during the OFF
segment of the ring cycle (between rings) and at all other times
when ringing is not being received. The operation of Ai is not
disabled by an OFF condition on DTR.
External Transmit Clock (XTCLK)
In synchronous communication where the user needs to supply
the transmit data clock. the input XTCLK can be used. The clock
supplied at XTCLK must exhibit the same characteristics of
TDCLK. The XTCLK input is then reflected at TDCLK.
Receive Data Clock (RDCLK)
The modem provides a Receive Data Clock (RDCLK) output in
the form of a 50 ± 1% duty cycle squarewave. The low-to-high
transitions of this output coi ncide with the center of received data
bits. The timing recovery circuit is capable of tracking a ± .035%
(relative) frequency error in the associated transmit timing
source.
Ai will respond to ring signals in the frequency range of 15.3 Hz
to 68 Hz with voltage amplitude levels of 40 to 150 Vrms (applied
across TIP and RING). with the response times given in Table 13.
This OFF-to-ON (ON-to-OFF) response time is defined as the
time interval between the sudden connection (removal) of the
ring signal across TIP and RING and the subsequent ON (OFF)
transition of Ai.
RDCLK is prOVided to the user in both asynchronous and synchronous communications. RDCLK is not necessary in asynchronous communication but it can be used to supply a clock for
UART/USART timing (RDCLK is not valid in FSK). RDCLK is necessary for synchronous communication.
Table 9.
Ri Response Time
RI Transition
Response Time
ttO ±50 ms (50% duty cycle)
OFF-te-ON'
ON-to-OFF
450 ±50 ms
Note: 'The OFF-to-ON time is duty cycle dependent:
890 ms (t5%) ~ time ~ 50 rns (tOO%)
Received Line Signal Detector (RLSD)
The RLSD thresholds for both high and low channels are:
RLSD ON ~ -43 dBm
RLSD OFF :s; - 48 dBm
1-80
R2424
2400 bps Full-Duplex Modem
MICROPROCESSOR INTERFACE
to pull the IRQ line high when all IRQ drivers are off (i.e., it must
overcome the leakage currents). The resistor value should be
large enough to limit the driver sink current to a level acceptable
to each driver. For the case where only the modem IRQ driver is
used, a resistor value of 5.6K ohms ± 20%, 0.25 watt, is
sufficient.
Seventeen hardware circuits provide address, data, control, and
interrupt signals for implementing a parallel interface compatible
with an 8080 microprocessor. With the addition of a few external
logic gates, the interface can be made compatible with a wide
variety of microprocessors such as 6500, 6800, or 68000.
DAA INTERFACE (R2424M)
The microprocessor interface allows a host microprocessor to
change modem configuration, read or write channel data as well
as diagnostic data, and supervise modem operation by means of
soft strappable control bits and modem status bits. The significance of the control and status bits and methods of data interchange are discussed in a later section devoted to software circuits. This section describes the operation of the interface from a
hardware standpoint.
The R2424M provides a Data Access Arrangement (DAA)
interace that is directly hardware and software compatible with
the RDAA. Manual/automatic originate and answer are then controlled via the appropriate R2424M hardware ancillary circuits or
software control bits. The modem provides the only interface with
the microprocessor (MPU) bus, i.e., no RDAA interface signals
must be directly controlled from the MPU bus.
Chip Select (CSO and CS1) and
Register Selects (RSO-RS 1)
Ring Detect (RD)
RD low indicates to the modem by an ON condition that a
ringing signal is present. The Signal (a 4N35 optoisolator compatible output) into the RD input should not respond to momentary bursts of ringing less than 125 ms in duration, orlo less than
40 Vrms, 15 to 68 Hz, appearing across TIP and RING with
respect to ground. The ring is then reflected on Ri.
The signal processor to be accessed is selected by grounding
one of two unique chip select lines, CS1 or CSO. The selected
chip decodes the four address lines, RS3 through RSO, to select
one of sixteen internal registers. The most significant address bit
(~) is RS3 while the least significant address bit (2°) is RSO.
Once the address bits have been decoded, the selected register
can be read from or written into via an 8-bit parallel data bus, 07
through DO. The most significant data bit (27) is 07 while the
least significant data bit (2D) is DO.
Request Coupler Cut Through (RCCT)
RCCT is used to request that a data transmission path through
the DAA be connected to the telephone line. When RCCT goes
OFF (low), the cut-through buffers are disabled and CCT should
go OFF (high). RCCT should be OFF during dialing but ON for
tone address signaling.
Read Enable (READ) and
Write Enable (WRITE)
Reading or writing is activated by pulsing either the READ input
high (R2424M) or READ input low (R2424DM), or the WRITE
input low. During a read cycle, data from the selected register is
gated onto the data bus by means of three-state drivers. These
drivers force the data lines high for a one bit or low for a zero bit.
When not being read, the three-state drivers assume their off,
high-impedance, state. During a write cycle, data from the data
bus is copied into the selected register, with high and low bus
levels representing one bits and zero bits, respectively. The timing required for correct read/write cycles is illustrated in Figure 2.
Logic necessary to convert the Single Rm output from a
65XX series microprocessor to the separate READ/READ and
WRITE Signals required by the modem is shown in Figure 3.
Coupler Cut Through (CCT)
An ON (low) signal to the CCT lead indicates to the modem that
the data transmission path through the DAA is connected. This
input can always be ~ded if the two second billing delay
squelch is desired. If CCT is user controlled, the billing delay
squelch can only be 2 seconds or greater.
Off-Hook Relay Status (OH)
The modem provides an OH output which indicates the state of
the OH relay. A high condition on OH implies the OH relay is
closed and the modem is connected to the telephone line (offhook). A low condition on OH implies the OH relay is open (i.e.,
the modem is on-hook). The delay between the low-to-high or
high-to-Iow transition of OH and the subsequent close-to-open or
open-to-close transition of the OH relay is 8 ms maximum.
Interrupt Request (IRQ)
The final.!!9.nal on the microprocessor interface is Interrupt
Request (IRQ). This signal may be connected to the host microprocessor interrupt request input in order to interrupt host program execution for modem service. The use of IRQ is optional
and the method of software implementation is described in a
subsequent section, Software Circuits. The IRQ output structure
is an o~drain field-effect-transistor (FET). This form of output
allows IRQ to be connected in parallel to other sources of interrupt. Any of these sources can drive the host interrupt input low,
and the interrupt servicing process continues until all interrupts
have been cleared and all IRQ sources have returned to their
!!!9t' impedance state. Because of the open-drain structure of
IRQ, an external pull-up resistor to + 5 volts is required at some
point on the IRQ line. The resistor value should be small enough
DAAINTERFACE(R2424DM)
The R2424DM provides the following DAA interface signals: RD,
OH, TXA and RXA. Manual/automatic originate and answer are
controlled via appropriate software control bits.
Ring Detect (RD)
RD indicates to the modem by an ON (high) condition that a
ringing signal is present. The Signal (a 4N35 optoisolator compatible output) into the RD input should not respond to momentary bursts of ringing less than 125 ms in duration, or to less than
1-81
I
•
R2424
2400 bps Full-Duplex Modem
WRITE
READ
CSl
(i
= 0,1)
RSi
(i
= 0-3)
READ (R2424DM)
Di
(i = 0-7)
Characteristic
eSi, RSi setup time prior
to Read or Write
Data access time after Read
Data hold time after Read
eSi, RSi hold time after
Read/Read or Write
Write data setup time
Write data hold time
Write strobe pulse width
Figure 2,
Symbol
Min
TeS
lOA
lOH
30
TeH
TWOS
TWDH
TWR
10
75
10
75
10
Max
Units
140
50
ns
ns
ns
ns
ns
ns
ns
Microprocessor Interface Timing Diagram
R2424DM
ONLY
~------~~
:;»;"---1 READ/READ
R2424
MODEM
RiW
----+--(1
Figure 3.
P-----------~WRITE
RIW to READ WRITE Conversion Logic
1-82
R2424
2400 bps Full-Duplex Modem
40 Vrms, 15 to 68 Hz, appearing across TIP and RING with
respect to ground. The ring is then reflected on Rio
Table 10. R2424DC Network Interface
Off-Hook Relay Status (OH)
The modem provides an OH output which indicates the state of
the Off-Hook relay. A low condition on OH implies the Off-Hook
relay is closed and the modem is connected to the telephone line
(off-hook). A high condition on OH implies the Off-Hook relay is
open (i.e., the modem is on-hoo~The delay between the low-tohigh or high-to-Iow transition of OH and the subsequent close-toopen or open-to-close transition of the Off-Hook relay is 8 ms
maximum.
Connector
Type
Pin
Number
Name
Function
RJll Jack
3
4
RING
TIP
One Side of TELCO Line
One Side of TELCO Line
TO
(
NETWORK
----.+----
,--
ANALOG SIGNALS (R2424M/R2424DM)
--,
51& I
L ______~ J
MINIATURE
11 : 213 4
~
6 POSITION JACK
Two connections are devoted to analog audio signals: TXA and
RXA.
) TO OTHER
EQUIPMENT
I
R2424
MODEM JACK
r- - - - --,
I tI
Transmit Analog (TXA)
MINIATURE
6 POSITION PLUG I
The R2424M TXA output is suitable for driving a data access
arrangement for connection to either leased lines or the public
switched telephone network. The transmitter output impedance
is 604 ohms ± 1% with an output level of + 6 dBm ± 1 dBm. To
obtain a 0 dBm output, a 600 ohm load to ground is needed.
RING (RED
Receive Analog (RXA)
+! II
TELEPHONE
CORD
w~: J t ~I:(GREEN
Figure 4.
The R2424DM TXA output is an op amp output at 0 dBm
±1 dBm.
j3j4j j
WIRE)
RJ11 Telephone Jack
ANCILLARY CIRCUITS
RXA is an input to the receiver from a data access arrangement.
The input impedance is 23. 7K ohms ± 1%. The received level at
RXA must be no greater than - 9 dBm (or - 6 dBm with the3DB
bit enabled).
Transmit Baud Clock (TBCLK) and
Received Baud Clock (RBCLK)
TBCLK and RBCLK are provided to the user at the baud rate
(600 Hz).
ANALOG SIGNALS (R2424DC)
Talk (TLK) (DIN Module Only)
Three analog signals are output by the R2424DC: LINE MONIlOR, TIP and RING.
TLK is an input which manually places the modem on-hook (relay
open, TLK = 0) or off-hook (relay closed, TLK = 1). Theon-hook
condition is referred to as TALK mode and the off-hook condition
is referred to as DATA mode. TLK is used with ORG to manually
originate or answer a call. TLK should be 0 at power-on or reset to
e!!..vent the modem from inadvertently entering the data mode.
TLK is not provided on the R2424DM.
Analog Line Monitor (LINE MONITOR)
The LINE MONllOR output is suitable for a speaker interlace. It
provides an output for all dialing signals, call progress signals,
and the carrier signals. The output impedance is 15K ohms
± 1%. The signals which appear on LINE MONllOR are approximately the same level as the signals would appear on the network (assuming a 1 dB loss attributed to the audio transformer).
Originate (ORG) (DIN Module Only)
ORG is an input which manually places the modem in the originate mode (ORG = O~e answer mode (ORG = 1). To manually originate a call, ORG = 0 and TLK = O. Dial the number
using the telephone. When the other modem answers and sends
answer tone switch the TLK input from 0 to 1 placing the modem
off-hook.
Phone Line Interface (TIP and RING)
TIP and RING are the DAA analog outputs to the public switched
telephone network. These outputs use two RJ 11 jacks in parallel
as the interface to the network (see Table 10 and Figure 4). The
R2424DC, which contains the DAA TIP and RING interface, has
been FCC Part 68 approved. The user need not apply for further
Part 68 approval. The impedance of TIP with respect to RING is
600 ohms.
To manually answer a call ORG = 1 and TLK = O. When the
phone rings switch the TLK input from 0 to 1 placing the modem
off-hook. ORG is not provided on the R2424DM.
1-83
.-
I
R2424
2400 bps Full-Duplex Modem
or write cycle from the host processor to register o. This operation is discussed in detail later· in this section.
SOFTWARE CIRCUITS
Operation of the microprocessor interface circuits was described
in the hardware section from the standpoint of timing and loadIdrive characteristics. In this section, operation of the microprocessor interface is described from a software standpoint.
Memory ~ of the 32 addressable registers in the modem
receiver (CSO) .and transmitter (CS1) interface memory are
shown in Figures 5. and 6, respectively. These registers may be
read or written on any host read or write cycle, but all eight bits of
that register are affected. In order to read a single bit or a group of
bits in a register, the host processor must mask out unwanted
data. When writing a single bit or group of bits in a register the
host processor must perform a read-modity-write operation. That
is, the entire register is read, the necessary bits are set or reset in
the accumulator of the host, then the original unmodified bits and
the modified bits are written back into the register of the interface
memory.
The modem is implemented in firmware running on two special
purpose signal processors. These signal processors share the
computing load by performing tasks that are divided into two
areas. These areas are partitioned into receiver and transmitter
devices.
INTERFACE MEMORY
Each signal processor can com~unicate with the host processor
by means of a specialized, dual-port, scratch-pad memory called
interface memory. A set of Sixteen 8-bit registers, labeled register 0 through register F, can be read from or written into by either
the host processor or signal processor. The host communicates
via the microprocessor interface lines shared between the two
signal processors. The signal processor communicates via its
internal 110 bus. Information transfer from SP RAM to interface
memory is accomplished by the signal processor logic unit moving data between the SP main bus and the SP 1/0 bus. Two of the
16 addressable interface memory registers (i.e., register 0 and
register E) have unique hardware connections to the interrupt
logic. It is possible to enable a bit in register E to cause an interrupt each time it sets. This interrupt can then be cleared by a read
Figures 7 and 8 show the registers according to the overall function they perform in the receiver and transmitter, respectively.
Figures 9 through 12 show the power on configurations of the
interface memory bits for the R24241US and the R2424/1NT versions.
Table 11 defines the individual bits in the interface memory. In the
Table 11 descriptions, bits in the interface memory are referred to
using the format Y:Z:Q. The chip number is specified by Y (0 or
1), the register number by Z (0 through F), and the bit number by
Q (0 through 7, with 0
LSB).
=
1-84
2400 bps Full-Duplex Modem
R2424
~I
7
Register
5
6
3
4
2
~
1
0
E
IRQ
ENSI NEWS
CRQ DATA AAE
RAM Access R
F
-
E
IRQ
ENSI NEWS
D
BUS
CRQ
-
C
B
-
-
-
-
A
ERDL
RDL
DL
ST
9
-
-
8
TONE
ATD
7
-
-
6
-
-
-
-
LCD
RSD
-
D
BUS
-
-
-
C
DSRA
-
-
-
AL
B
MODE
-
-
-
-
3
-
TXCLK
ERDL
RDL
-
GTS
GTE
DL
-
9
NAT'
RLSD
8
DLO
CTS
DSR
RI
-
-
7
-
-
-
-
RTRN ORG
LL
-
EF
NTS
-
-
-
-
-
-
-
4
RAM Dala YTL (YRAMTL)
3
RAM Dala XTM (XRAMTM)
0
-
2
-
-
-
-
-
-
-
-
-
-
-
RAM Dala XTL (XRAMTL)
-
1
~
Register
7
F
6
I
5
I
4
I
DIAGNOSTIC
3
I
2
I
-
-
-
-
Dial Digil Regisler
NOles
1. Nol valid before R5310·22
(-) Indicales reserved for modem use only.
Receiver (CSO) Interface Memory Map
I
-
0
Nole
(-) Indlcales reserved for modem use only.
Figure 5.
1
I
Figure 6.
~
0
Register
CONTROL
Transmitter (CS1) Interface Memory Map
7
I
F
6
I
5
I
4
I
DIAGNOSTiC
3
I
2
HANDSHAKE
E
HANDSHAKE
D
CONFIGURATION
D
CONFIGURATION
C
CONFIGURATION
C
CONFIGURATION
B
CONFIGURATION
B
CONFIGURATION
A
CONFIGURATION
A
CONFIGURATION
9
STATUS
9
CONFIGURATION
8
STATUS
8
STATUS
7
RESERVED
7
RESERVED
6
RESERVED
6
RESERVED
5
DIAGNOSTIC
5
DIAGNOSTIC
4
DI A G N OS TI C
4
DIAGNOSTIC
3
DIAGNOSTIC
3
DIAGNOSTIC
2
DIAGNOSTIC
2
DIAGNOSTIC
1
RESERVED
1
0
RESERVED
0
BII
Figure 7.
7
I
6
I
5
I
4
I
3
I
2
I
1
I
Bil
Receiver (CSO) Interface Memory Functions
Figure 8.
1-85
1
I
0
I
0
RESERVED
DIAL
~
0
I
CONTROL
E
:;0
AL
RAM Dala YTM (YRAMTM)
5
RAM Dala XRL (XRAMRL)
SSD
DLSF'
CC
RAM Dala YRL (YRAMRL)
-
DDRE
-
RAM Dala XRM (XRAMRM)
-
-
RTS
4
1
0
MODE
3
2
1
3DB DTMF
ST
-
6
-
DTR
CHAR
TX LEVEL
A
NEWC DDEI
TM
RAM Dala YRM (YRAMRM)
2
RAM Access T
-
-
4
5
F
-
SPEED
5
6
NEWC
CHAR
-
7
Register
7
I
6
I
5
DIGIT
I
4
REGISTER
I
3
I
2
I
1
Transmitter (CS1) Interface Memory Functions
2400 bps Full-Duplex Modem
R2424
~
Roglote
F
7
6
5
4
3
RAM Access R
0
0
0
0
E
IRQ
ENSI
NEWS
0
0
0
BUS
CRQ
0
0
C
B
-
-
-
-
A
ERDL
RDL
DL
ST
0
0
0
0
9
-
-
0
0
8
TONE
ATD
0
0
7
-
-
-
-
0
6
1
0
0
NEWS
0
-
C
DSRA
AL
0
B
0
0
0
0
RDL
DL
ST
1
A
ERDL
0
0
0
0
0
-
-
9
NAT
RTRN
ORG
LL
TM
RLSD
0
8
DLO
0
0
0
-
-
7
-
-
6
-
-
-
-
-
-
LCD
1
RSD
-
-
0
0
-
-
-
-
-
-
4
0
MODE
3
RAM Access T
ENSI
-
5
0
0
-
-
6
IRO
0
-
-
7
F
0
-
0
Register
E
0
0
CHAR
~
0
NEWC
1
SPEED
-
2
2
0
0
0
0
0
0
-
NEWC
DDEI
0
-
DDRE
0
BUS
CRQ
DATA
ME
DTR
0
0
0
-
-
SSD
0
3DB
DTMF
0
0
TX CLK
0
0
TX LEVEL
0
0
0
CTS
DSR
0
CHAR
1
0
GTE
GTS
0
RI
0
0
1
RTS
0
-
0
-
-
-
-
RAM Dala YTL (Random)
RAM Dala XTM (Random)
~
BII
7
6
5
4
RAM Dala XTL (Random)
2
-
-
1
-
-
-
0
3
2
1
0
~
~
7
6
5
4
3
RAM Access R
0
0
0
0
E
IRQ
ENSI
NEWS
0
0
0
0
BUS
CRO
0
0
-
-
C
-
-
1
B
-
-
A
ERDL
RDL
DL
ST
0
0
0
0
9
-
-
0
0
8
TONE
ATD
0
0
-
7
-
-
-
6
-
-
-
-
7
6
5
1
Figure 10.
0
~I
Reglste
7
6
5
0
0
0
0
0
0
0
-
-
-
E
IRQ
ENSI
0
0
NEWS
0
-
LCD
1
RSD
0
BUS
CRO
-
-
C
DSRA
0
-
-
-
-
-
-
-
-
4
3
2
0
MODE
1
0
AL
0
0
0
0
0
0
'0
DDEI
0
DATA
AAE
DTR
0
0
-
-
DDRE
0
3DB
DTMF
AL
0
0
0
0
TXCLK
0
0
TX LEVEL
0
0
0
DL
1
A
RDL
0
0
0
-
-
9
NAT
RTRN
ORG
0
0
0
TM
RLSD
8
DLO
CTS
DSR
0
0
0
-
-
7
-
-
-
-
6
-
-
-
CHAR
1
0
GTE
GTS
0
0
ST
0
1
LL
RTS
0
0
RI
0
-
-
MODE
1
0
CC
EF
1
NTS
0
-
-
-
-
RAM Data YTL (Random)
3
RAM Data XRM (Random)
3
RAM Dala XTM (Random)
BII
0
-
4
~
0
DLSF
0
5
RAM Dala YTM (Random)
RAM Dala XTL (Random)
2
-
-
-
-
-
-
1
-
-
-
-
-
-
-
0
7
6
5
4
3
2
1
0
~
0
0
SSD
0
RAM Data YRL (Random)
RAM Oala XRL (Random)
0
NEWC
RAM Dala YRM (Random)
-
1
0
ERDL
0
2
-
-
0
3
4
1
0
0
B
0
4
RAM Acces. T
5
2
t
R2424/US Transmitter (CS1) Interface Memory
Power On Configuration
NEWC
1
-
(-) Indicates reserved for modem use only.
F
CHAR
SPEED
2
-
Dial Digit Register (Wrlle-Only Register)
Bit
R2424/US Receiver (CSO) Interface Memory
Power On Configuration
F
-
-
(-) Indicates resarved for modem usa only.
Figure 9.
-
RAM Dala YTM (Random)
3
0
0
-
RAM Dala XRM (Random)
-
1
NTS
-
3
-
0
-
4
-
0
AL
-
5
RAM Data XRL (Random)
0
DLSF
-
RAM Data YRL (Random)
-
0
-
RAM Dala YRM (Random)
-
0
MODE
1
0
CC
EF
0
0
5
1
0
0
0
4
2
1
-
-
-
-
-
-
Dial Digil Register (Wrlle-Only Reglsler)
BII
(-) Indicates reserved for modem use only.
7
6
5
4
3
2
1
0
(-) Indicate, reserved for modem use only.
Figure 12.
Figure 11. R242411NT Receiver (CSO) Interface Memory
Power On Configuration
1-86
R242411NT Transmitter (CS1) Interface Memory
Power On Configuration
R2424
2400 bps Full-Duplex Modem
Table 11.
Mnemonic
AAE
Name
Auto Answer Enable
Interface Memory Definitions
Memory
Location
I:D:4
Descriptioh
When conflgurallon bit AAE IS aI, the modem will automatically answer
when a ringing signal is present on the line. When AAE is set to aI, the
modem will answer after one ring and go into data mode.
The modem goes off-hook 1 second after the on-to-off transition of the ring.
The ORG pin or ORG bit need not to be set to the answer polarity. If it is
desired to answer after more than one ring, then the user must use the
alternative answer method described under the DATA bit. The DTR pin or
the DTR bit must also be set before the modem will auto answer. Writing a 0
into the AAE bit will cause the modem to go on-hook. This will occur only
when the modem auto answers uSing the AAE bit.
AL
Analog Loopback
(O,I):B:O
When conflgurallon bits AL are aI, the modem IS in local analog loopback
(V.54 Loop 3). In this loop, the transmitter's analog output is coupled to the
receiver's analog Input at a point near the modem's telephone line interface.
An attenuator is Introduced Into the loop such that the signal level coupled
into the receive path is attenuated 14 ± 1 dBm. The modem may be placed
into analog loopback in either the idle mode or the data mode. However, in
the data mode, setting the AL bits to a 1 will terminate the connection.
Analog loopback will only function in the high speed modes (2400, 1200, or
600 bps).
The DTE may be tested when the modem is in analog loopback. Also, all
parts of the modem except the line interface are checked. If no DTE is
connected, the modem integrity may be verified by use of the self test
funcllon. When entering analog loopback, set AL in the receiver to a 1 before
setting AL In the transmitter to a 1.
When exiting analog loopback, reset AL in the transmitter to a 0 before
resetting AL in the receiver to a O.
ATD
Answer Tone Detected
BUS
Bus Select
0:8:6
When status bit ATD IS aI, It signifies that the modem receiver detected the
answer tone. The bit is 1 set 75 ms after the answer tone is first detected,
and IS cleared to a 0 when the modem goes on-hook. The user may clear
ATD manually after CTS IS active.
(0,1):D:7
When configuration bits BUS are aI, the modem is In the parallel control
mode; and when 0, the modem is in the serial control mode. BUS can be in
either state to configure the modem.
Serial Control Mode
The serial mode uses standard V.24 (RS-232-C compatible) signals to
transfer channel data. The control signals used in serial control mode are
DTR, RTS, TLK, and ORG. Outputs such as RLSD and DSR are reflected
both In the Interface memory and the V.24 interface. Once the bus bits have
been set to a 0, the state of the DTR, RTS, DATA, and ORG bits are
ignored.
Parallel Control Mode'
The modem has the capability of modem control via the microprocessor bus.
Data transfer IS maintained over the serial V.24 channel. The control bits
used in parallel control are DTR, RTS, ORG, and DATA.
The modem automatically defaults to the serial mode at power-on.
I! the parallel control mode IS to be used, It is recommended that the TLK pin
be tied to ground. A floating TLK pin will assume a logic 1 which will
immediately put the modem Into the data mode before the BUS bits are set.
In either mode, the modem is configured by the host processor via the
microprocessor bus.
'The R2424DM is only used in the parallel control mode.
1-87
•
2400 bps Full-Duplex Modem
R2424
Table 11. Interface Memory Definitions (Continued)
Mnemonic
CC
Name
Controlled Carner
Memory
Location
1'9:2
Description
When configuration bit CC is a 1, the modem operates In controlled carrier;
when 0, the modem operates in constant carrier.
Controlled carner allows the modem transmitter to be controlled by the RTS
pin or the RTS bit. Its effect may be seen in the RTS and CTS descriptions.
CHAR
Character Length Select
(0,1):C:(3,4)
These character length bits select either 8, 9, 10, or 11 bit characters
(includes data, stop, and start bits) as shown below:
Configuration Word
~
0
0
1
1
~
0
1
0
1
Configuration
8 bits
9 bits
10 bits
11 bits
It is possible to change character length during the data mode. Errors in the
data Will be expected between the changeover and the resynchronization
(which occurs on the next start bit after the change is implemented).
CRO
Call Request
(0,1):0:6
When configuration bit CRO in chip 1 (the transmitter) is a 1, it places the
transmitter in auto dial mode The data then placed In the Dial Digit Register
is treated as digits to be dialed. The format for the data should be a hex
representation of the number to be dialed (If a 9 is to be dialed then an 09 16
should be loaded in DDR). CRO in chip 1 should be a 1 for the duration of
the data mode If CRO in chip 1 is changed to a 0, the modem will go
on-hook. Also, see DDRE bit.
When conflgurallOn bit CRO in chip 0 (the receiver) is a 1, the receiver goes
into tone detect mode. Any energy above threshold and in the 345 to 635 Hz
bandwidth IS reflected by the TONE bit. CRO in chip 0 must be reset to a 0
(after the last digit was dialed and tone detection completed) before the
answer tone IS sent by the answering modem (after rlngback is detected).
CRO in chip 0 need not be used during auto dialing, but may be used to proVide call progress information as part of an intelligent auto dialing routine. An
example flowchart is given in Figure 13.
FF (hex) should be loaded into the Dial Digit Register after the last digit is
dialed and tone detection is completed. This action also puts the modem in
data mode and starts a 30 second abort timer. If the handshake has not
been completed in 30 seconds the modem will go on-hook.
CTS
Clear-to-Send
1:8:6
When status bit CTS is a 1, It indicates to the terminal equipment that the
modem will transmit any data which are present at TXD.
CTS response times from an ON or OFF condition of RTS are shown below:
CTS Transition
OFF to ON
ON to OFF
·Programmable
Constant Carrier
s2 ms
s20 ms·
Controlled Carrier
210 to 275 ms
s20 ms·
DATA
TalkiData
1:0:5
When control bit DATA is ai, the modem is in the data state (off-hook); and
when 0, the modem is in the talk state (on-hook). This bit allows the modem
to go off-hook after a programmable number of rings by counting the required
'number of RI bit transitions and then setting the DATA bit (assuming ORG = 0).
DDEI
Dial Digit Empty Interrupt
1:E:2
When handshake bit DOE I IS a 1, an interrupt will occur when the Dial Digit
Register (1'0) IS empty (DDRE = 1). This IS independent of the state of the
ENS I bit. The Interrupt Will set the IRO bit and also assert the IRO signal.
Loading the Dial Digit Register with a new digit will clear the Interrupt
condition.
1-88
R2424
2400 bps Full-Duplex Modem
Table 11.
Mnemonic
Name
DDR
Dial Digit Register
DDRE
Dial Digit Register Empty
Interface Memory Definitions (Continued)
Memory
Location
1.0:(0-7)
I:E:O
Description
DDR is used to load the digits to be dialed. Example: If a 4 IS to be dialed,
an 04 (hex) should be loaded. This action also causes the Interrupt to be
cleared The modem automatically accounts for the interdigit delay. Note:
DDR IS a wnte-only register.
When handshake bit DDRE is a I, it indicates that the dial digit register is
empty and can be loaded with a new digit to be dialed. If the DDEI bit IS set,
the IRO bit will be set when the DDRE bit is set. Also, the IRO signal will be
generated.
After the DDR is loaded, DDRE goes to a 0 and the interrupts are
automatically cleared.
DL
Digital Loopback (Manual)
(O,I).A:5
When configuration bits DL are set to a I, the modem IS manually placed In
digital loopback. DL should only be set during the data mode. The DSR and
CTS bits will be reset to a O. The local modem can then be tested from the
remote modem end by looping a remotely generated test pattern. At the
remote modem, all interface circUits behave normally as in the data mode.
At the conclusion of the test, DL must be reset to a O. The local modem will
then return to the normal data mode with control reverting to the DTEs, DTR.
DL does not function in 300 bps.
DLO
Dial Line Occupied
1'8:7
When status bit DLO IS a I, it indicates that the modem is In the auto dial
state, I e., CRO In the transmitter is a 1 and the modem is off-hook and
ready to dial.
DLSF
Disable Low Speed Fallback
I:C'O
When configurallon bit DLSF is a I, the modem will not automatically
fallback to the 300 bps operating mode if it is configured for another data
rate. This bit IS valid in onginate mode only.
DSR
Data Set Ready
1:8:5
The ON condition of the status bit DSR Indicates that the modem is in the
data transfer state The OFF condilion of DSR is an indication that the DTE
IS to disregard all signals appearing on the interchange Circuits - except RI.
DSR Will sWitch to the OFF state when in test state. The ON condition of
DSR Indicates the following:
The modem IS not In the talk state, i e., an associated telephone handset is
not in control of the line
The modem is not in the process of automatically establishing a call via
pulse or DTMF dialing.
The modem has generated an answer tone or detected answer tone.
After nng indicate goes ON, DSR waits at least two seconds before turning
ON to allow the telephone company equipment to be engaged.
DSR Will go OFF 50 msec after DTR goes OFF, or 50 msec plus a maximum
of 4 sec when the SSD bit is enabled
DSRA
Data Set Ready in Analog
Loopback
I:C:7
When configurallon bit DSRA is a I, It causes DSR to be ON during analog
loopback.
1-89
2400 bps
R2424
Full~Duplex
Modem
Table 11. Interface Memory Definitions (Continued)
Mnemonic
DTMF
Name
Touch Tones/Pulse Dialing
Memory
Location
1:B:1
Description
When configuration bit DTMF IS a 1, it tells the modem to aUlo dial uSing
tones; and when 0, the modem will dial using pulses.
The timing for the pulses and tones are as follows (power-on timing):
Pulses -
Relay open 64 ms
Relay closed 36 ms
Interdigit delay 750 ms
Tones - Tone duration 95 ms
Interdigit delay 70 ms
The DTMF bit can be changed during the dialing process to allow either tone
or pulse dialing of consecutive digits. The oUlput power level of the DTMF
tones is as follows:
± 15 dBm ± 1 measured at TXA for the R2424M
-1 dBm ± 1 measured at TIP/RING for the R2424DC
DTR
Data Terminal Ready
1:0:3
Control bit DTR must be a 1 for the modem to enter the data state, either
manually or automatically. DTR must also be a 1 in order for the modem to
automatically answer an incoming call.
During the data mode, DTR must remain at a 1, otherwise the connection will
be terminated if DTR resets to a 0 for greater than 50 ms.
EF
Enable Fitters
1:9:1
Setting CRa in the transmitter to a 1 disables the high and low band fitters
used In data mode so that call progress tone detection can be done. Setting
CRa in the receiver to a 1 inserts a passband filter in the receive path which
passes energy in the 345 Hz to 635 Hz bandwidth. The high and low band
filters must be enabled and the passband filter disabled for the answer tone
and carrier to be detected. This occurs automatically during the auto dial
process when EF is set to a O. In this case, the high and low band filters are
disabled when CRa m the transmitter is set to a 1. If tone detection is
required, CRa in the receiver should be set to a 1. After dialing and call
progress tone detection, CRa in the receiver is set to a 0 and FF is loaded
into the dial digit register. (Loading FF enables the high and low band filters).
At this time, the answer tone can be detected. To re-enable the high and low
band filters disabled by setting CRa in the transmitter, set EF to a 1. After
CRa in the transmitter and receiver is set to a 1 and tone detection is
completed, it may be necessary to detect the answer tone before loading FF
into the dial digit register (see the section on sending 1300 Hz calling tone).
At that point, EF can be set to a 1 and CRa m the receiver set to a 0 so the
answer tone can be detected (using the ATD bit) and the 1300 Hz calling
tone can stili be sent. Once the answer tone is detected, FF should be
loaded mto the dial digit register and the EF bit set to a O.
ENSI
Enable New Status Interrupt
(0,1):E:6
When handshake bit ENSI is a 1, it causes an Interrupt to occur when the
status bits in registers (0:[8,9]) and (1 :8) are changed by the modem.
(NEWS = 1). The IRa bit will be set to a 1 and the IRa signal will be
generated. The interrupt is cleared by writing a 0 into the NEWS bit.
ERDL
Enable Response to
Remote Digital Loopback
(0,1):A:7
When configuration bits ERDL are a 1, it enabtes the modem to respond to
another modem's remote digital loopback request, thus going Into loopback.
When this occurs, the modem clamps RX~ a mark; resets the CTS, DSR
and RLSD bits to a 0 and turns the CTS, DSR and RLSD signals to a logic 1.
The TM bit is set to inform the user of the test status. When the ERDL bits are
a 0, no response will be generated.
GTE
Guard Tone Enable
1:B:4
When configuration bit GTE IS a 1, it causes the spaclfied guard tone to be
transmitted (CCITI configurations only), according the state of the GTS bit. Note:
The guard tone Will only be transmitted by the answering modem.
1-90
R2424
2400 bps Full-Duplex Modem
Table 11. Interface Memory Definitions (Continuilc:l)
Mnemonic
Name
GTS
Guard Tone Select
IRQ
Interrupt
LCD
Loss of Carrier Disconnect
Memory
Location
Description
I:B:3
When configuration bit GTS is a 0, It selects the 1BOO Hz tone, when GTE IS
a 1 it selects the 550 Hz tone. The selected guard tone will be transmitted
only when GTE IS enabled.
(O,I):E:7
When status bit IRQ is a I, it Indicates that an Interrupt has been generated
The IRQ hardware signal IS generated follOWing the setting of the IRQ bit
IRQ is cleared when either the NEWS bit IS reset to a 0 or the OOR IS
loaded with a number.
0:0:2
When configuration bit LCD is a I, the modem terminates a call when a loss
of received carrier energy is detected after 400 ms After the first 40 ms of
loss of carrier, RLSO goes off. 360 ms later, If no carner IS detected, CTS
goes off, and the modem goes on-hook. If energy above threshold IS
detected during the 360 ms period, RLSO will be set to a 1 again. If further
loss of energy occurs, the 400 ms time frame IS restarted
If LCD is set to a 0, RLSO will be set to a 1 when energy is above threshold,
but will not force the modem on-hook when energy falls below threshold In
this case, n is necessary to re-enable LCD In order to put the modem on-hook
LCD is not automatically disabled In leased hne operation The user must
write a 0 into LCD bits for this to occur.
LL
Leased line
1:9:4
MODE
Mode Select
(0,1):A:(0,3)
When configuration bit LL IS a I, the modem is In leased line operation,
when 0, the modem IS in switched line operation. When LL IS set to a I, the
modem immediately goes off-hook and into data mode.
These bits select the compatibility at which the modem is to operate, as
shown below:
Configuration Word
~
0
0
0
0
0
1
1
1
1
1
1
1
1
!
!
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
0
1
1
0
0
1
1
~
0
1
0
1
0
0
1
0
1
0
1
0
1
Configuration
Bell 2400
Bell 2400
Bell 212A
Bell 212A
Bell 212A
V.22A
V.22B
V.22A
V.22B
V.22 bis
V.22 bis
V 22 bis
V.22 bls
2400 Sync
2400 Async
1200 Sync.
1200 Async
o to 300 Async
1200 Sync
1200 Async
600 Sync.
600 Async
2400 Sync.
2400 Async
1200 Sync
1200 Async
NOTE: The Mode bits in both chips should be set exclusively of all other
bHs, followed immediately by the setting of the NEWC bits. This will ensure
proper modem configuration.
Automatic Reconfiguration
The modem is capable of automatically falling back during the handshake to
the compatibilHy of a remOte modem. The modem can be in either the
answer or originate mode for this to occur. The compatibilities that the
modem are IimHed to adapt to are V.22 bis, V.22 AlB (1200 bps), Bell 212
and Bell 103. If the R2424 is to originate in a specific configuration, the
MODE bits must be set.
When the answer modem is configured for Bell 300 asynchronous and IS
called by a 1200 bps modem, the handshake will be completed at 1200 bps.
NAT
No Answer Tone
1:9:7
When configuration bit NAT is a I, the modem will not transmit the 2100 Hz
CCITT answer tone. This bit is only valid for CCITT configurations. With thiS
bit enabled in answer mode, when the modem goes off-hook it will remain
silent for 75 ms end then transmit unscrambled ones.
1-91
R2424
2400 bps Full-Duplex Modem
Table 11.
Mnemonic
Name
Interface Memory Definitions (Continued)
Memory
Location
Description
NEWC
New Configuration
(O,l):E:3
When the NEWC bit IS a 1, it tells the modem that a new configuration has
been written into the configuration registers. The modem will then read the
configuration registers and then reset NEWC to a o. NEWC must be set to a
1 after a new configuration has been written Into the following registers:
(O:[A-D]) and (1 :[9-0]). The remaining registers do not require the use of
NEWC to tell the modem that new data was written Into them.
NEWS
New Status
(O,l):E:5
When handshake bit NEWS IS a 1, it tells the user that there has been a
change of status in the status registers. The user must write a 0 into NEWS
to reset it. This action also causes the interrupt to be cleared.
NTS
No Transmitter Scrambler
1:9:0
When configuration bit NTS is a 1, when the modem IS off-hook It will
transmit all data in an unscrambled form. This bit should be disabled if the
normal modem handshake is desired.
ORG
Originate/Answer
1:9:5
When configuration bit ORG IS a 1, the modem is in originate mode; and
when a 0 the modem is in answer mode. (This is only valid in manual
Originate/answer and analog loopback). If ORG is a 1 in analog loopback, the
modem will transmit in the high band and receive in the low band. If ORG IS
a 0 in analog loopback, the modem will transmit In the low band and receive
in the high band.
(None)
RAM Access R
0:F:0-7
Contains the RAM access code used in reading RAM locations in chip 0
(receiver device).
(None)
RAM Access T
1:F:0-7
Contains the RAM access code used in reading RAM locations in chip 1
(transmitter device).
XRAMRL
RAM Data XRL
0:2:0-7
Least significant byte of 16-bit word X used in reading RAM locations In chip O.
XRAMRM
RAM Data XRM
0:3:0-7
Most significant byte of 16-bIt word X used In reading RAM locations in chip o.
XRAMTL
RAM Data XTL
1:2:0-7
Least significant byte of 16-bit word X used in reading RAM locations in chip 1.
XRAMTM
RAM Data XTM
1:3:0-7
Most significant byte of 16-bit word X used in reading RAM locations in chip 1.
YRAMRL
RAM Data YRL
0:4:0-7
Least significant byte of 16-bit word Y used In reading RAM locations In chip O.
YRAMRM
RAM Data YRM
0:5:0-7
Most significant byte of 16-bit word Y used in reading RAM locations in chip O.
YRAMTL
RAM Data YTL
1:4:0-7
Least significant byte of 16-bit word Y used in reading RAM locations in chip 1.
YRAMTM
RAM Data YTM
1:5:0-7
Most significant byte of 16-bit word Y used in reading RAM locations in chip 1.
RDL
Remote Digital Loopback
(O,l):A:6
When configuration bits RDL are a 1, It causes the modem to initiate a
request for the remote modem to So into digital loopback. RXD IS clamped to
a mark and the CTS bit and CTS signal will be reset until the loop is
established. The TM bit is not set in this case, since the local modem
initiated the request. RDL does not function in 300 bps.
RI
Ring Indicator
1:8:4
When status bit RI is a 1, it indicates that a ringing signal is being detected.
The RI bit follows the ringing signal with a 1 during the on time and a zero
during the off time coincident with the Ai signal. The following are the RI bit
response times:
RI Bit Transition
Response
OFF-to-ON"
ON-to-OFF
110 ± 50 ms (50% duty cycle)
450 ±50 ms
'The OFF-la-ON lime is duly cycle dependent. 890 ms (15%) '" lime", 50 ms (100%)
This OFF-ta-ON (or ON-la-OFF) response time is defined as the time interval
between the sudden connection (removal) of the ring signal across TIP and
AING and the subsequent transition of the AI bit.
1-92
R2424
2400 bps Full-Duplex Modem
Table 11.
Mnemonic
RLSD
Name
Received Line Signal
Detector
Interface Memory Definitions (Continued)
Memory
Location
0'8'0
Description
When status bit RLSD is a 1, It indicates that the carner has successfully
been received RLSD Will not respond to the guard tones or answer tones
RLSD response times are given below
RLSD'
OFF-to-ON
ON-to-OFF
Constant
Carrier
Controlled
Carrier
40 to 65 ms
40 to 65 ms
40 to 65 ms
40 to 65 ms
Note:
1 After handshake has occurred
RSD
Receive Space Disconnect
RTRN
Retrain (2400 bps only)
RTS
Request-to-Send
When configuration bit RSD IS a 1, the modem goes on-hook after receiving
approximately 1 6 seconds of conllnuous spaces
1.9'6
When configuration bit RTRN IS a 1, the modem sends the training sequence It resets when the training sequence from the remote modem has
successfully been received If the sequence has not been successfully received from the remote modem, CTS Will remain OFF In order to put the modem
back In the data mode, It IS necessary to write a 0 Into the RTRN bit, then
repeat the retrain sequence
When control bit RTS IS a 1, the modem transmits any data on TXD when
CTS becomes active In constant carner mode, RTS should be set the same
time as DTR and then left ON In controlled carner operallon, Independent
operallon of RTS turns the carner ON and OFF. The responses to RTS are
shown (assume the modem IS In data mode).
Leased or Dial Line'
RTS Off
RTS On
Controlled Carner
CTS OFF
Carner OFF
Carner ON
210 to 275 ms Scrambled l's
Transmitted
CTS ON
Constant Carner
CTS OFF
Carner ON
Scrambled l's
Transmitted
CTS ON
Carrier ON
Data Transmitted
Note:
1 After handshake IS complete
For ease of use In constant carner mode, RTS should be turned ON the
same time as DTR.
SPEED
Speed Indlcallon
09'(4,5)
The SPEED status bits reflect the speed at which the modem IS operating.
The SPEED bit representations are shown.
~
~
Speed
0
0
1
1
0
1
0
1
0-300
600
1200
2400
Note:
The SPEED bits are not active In analog loopback and leased line mode
1-93
R2424
2400 bps Full-Duplex Modem
Table 11. Interface Memory Definitions (Continued)
Mnemonic
Name
SSD
Send Space Disconnect
ST
Self Test
Memory
Location
1:0:0
(0.1)·A:4
Description
When configuration bit SSD is a 1. It causes the modem to transmit
approxImately 4 seconds of spaces before dIsconnecting. when DTR goes
from actIve to inactive state.
When configuration bit ST IS a 1. self test is activated. ST must be a 0 to end
the test. It is possible to perform self test In analog loopback with or without a
DTE connected. During any self test. TXD and RTS are ignored. Self test does
not test asynchronous-ta-synchronous converter circuits In either the
transmitter or receiver.
Error detection IS accomplished by monitoring the self test error counter in
the RAM. If the counter increments dUring the self test. an error was made.
The counter contents are available in the diagnostIc regIster when the RAM
access code 00 is loaded In the dIagnostic control regIster (O:F).
Self Test End-ta-End (Data Mode)
Upon activation of self test an internally generated data pattern of alternate
binary ones and zeros (reversals) at the selected bit rate are applied to the
scrambler. An error detector. capable of identifying errors In a stream of
reversals are connected to the output of the descrambler.
Self Test with Loop 3
Loop 3 IS applied to the modem as defined in Recommendation V.54. Self
test is activated and DCE operation is as in the end-to-end test. In this test
DTR is ignored.
Self Test with Loop 2 (Data Mode)
The modem is condItioned to InstIgate a loop 2 at the remote modem as
specifIed in recommendatIon V.54. Self test is activated and DCE operation
IS as in the end-to-end test.
ST does not function in 300 bps.
3DB
3 dB Loss to Receive
Signal
1:B:2
When configuratIon bit 3DB is a 1. It attenuates the received signal 3 dB.
ThIS is only used If the modem will see 0 dBm or greater line signal at the
receiver input. Insertion of the 3 dB loss will then prevent saturatIon.
TM
Test Mode
0:8:1
When status bit TM is a 1. it indicates that the modem has completed the
handshake and is on one of the follOWIng test modes: AL or RDL.
TONE
Tone Detect
0:8:7
TONE follows the energy detected in the 340 to 640 Hz frequency band. The
user must determine which tone is present on the line by determining the
duty cycle of the TONE bit. TONE is active only when CRa in chip 0 is a 1.
Detection Range: -10 to -43 dBm
Response Time:
17 ± 2 ms
TXCLK
Transmit Clock Select
1·C:(5.6)
TXCLK allows the user to designate the origin of the transmitter data clock.
as shown below:
Configuration Word
Transmit Clock
~
!
Internal
External
Slave
o
1
1
o
o
1
If external clock is chosen the user clock must be Input at XTCLK. The clock
characteristics must be the same as TDCLK. The external clock will be
reflected by TDCLK.
If slave clock is chosen the transmItter is slaved to the receive clock. This is
also reflected by TDCLK.
1-94
R2424
2400 bps Full-Duplex Modem
Table 11.
Mnemonic
Name
TX LEVEL
Interface Memory Definitions (Continued)
Memory
Location
Transmit Level
1 B'(5-7)
Description
TX LEVEL ailows the user to change the transmit level at TIP and RING
(assuming the DM has 10 dBm attenuation In the transmit path).
Configuration
Word
?
0
0
0
0
1
1
1
1
~
0
0
1
1
0
0
1
1
~
0
1
0
1
0
1
0
1
Transmit Level (:t 1.0 dBm)
(at TIP and RING)
-10
-12
-14
-16
-18
-20
-22
-24
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
Internal Modem Timing
AUTO DIAL SEQUENCE
In a microprocessor environment it is necessary to know how
long various functions last or what the response times of certain
functions are. Since the modem is a part of the microprocessor
environment its timing and response times are necessary.
Table 12 provides the timing relationships between Interiace
memory bits and modem functions.
The following flow chart defines the auto dial sequence via the
microprocessor interface memory.
Table 12.
Internal Modem Timing
Parameter
Time Interval
NEWC bit checked
Transmitter
Receiver
Once per sample 1
Once per baud 2
NEWC bit set by host until
modem action
Transmitter
Receiver
s One baud time
One baud time
Control. Conflgurallon bits read
Transmitter
Receiver
Status bits updated
Transmitter
Receiver
Status change reflected by
NEWS. IRQ
Transmitter
Receiver
Memory status reflected to
modem pin
Transmitter
Receiver
1. Sample Time
= 7200 Hz
Only after NEWC IS set
ST. RSD-every sample.
ail others after NEWC set
Once per sample
Once per baud
Figure 13. Auto Dial Sequence Flow Diagram
MIN < one sample time
MAX one sample time
MIN one sample time
MAX one baud time
Note: The modem timing for the auto dialer accounts for interdigit delay for pulses and tones.
3333 ItS
33.33I's
2 Baud Time
= 600 Hz
1-95
2400 bps Full-Duplex Modem
R2424
SP RAM location as specified by the RAM access code (82-86) in
register l:F (Table 13). Once the data is written into the RAM
access register 1:F, theXRAM registers 1:2 and 1:3 or the YRAM
registers 1:4 and 1:5, set the NEWC bit 1:E:3 to a 1, This action
causes the information to be transferred from interface memory
into SP RAM. Bit 7 of register l:F is cleared to a 0 by the modem
after the RAM is read. New data can be written into the SP RAM
after the NEWC bit is reset to a 0 by the SP.
SIGNAL PROCESSOR RAM ACCESS
RAM AND DATA ORGANIZATION
Each signal processor contains 128 words of random access
memory (RAM). Each word is 32-bits wide. Because the signal
processor is optimized for performing complex arithmetic, the
RAM words are frequently used for storing complex numbers.
Therefore, each word is organized into a real part (16-bits) and an
imaginary part (16-bits) that can be accessed independently.
The portion of the word that normally holds the real value is
referred to as XRAM. The portion that normally holds the imaginary value is referred to as YRAM. The entire contents of XRAM
and YRAM may be read by the host processor via the microprocessor interface.
Note:
Any transmitter RAM Write operation must always be preceded by a RAM read from the desired location. This is to
guarantee that the correct information is written into the 16
unchanged bits, since all transmitter RAM operations are
32 bit transfers with typically only 16 of the bits used.
Interface Memory Locations
Both the transmitter and receiver (chips 1 and 0, respectively)
allow data to be transferred from SP RAM into the interlace memory. A 0 in transmitter bit 1:F:7 enables the SP to transfer 32 bits
of data from SP RAM to the XRAM and YRAM registers (16 bits
each) in the interface memory as specified by the RAM access
code in register 1:F. A 0 in receiver bit O:F:7 enables the SP to
transfer 32 bits of data from SP RAM to the XRAM and YRAM
registers (16 bits each) in the interface memory as specified by
the access code in register O:F. To read the SP RAM in chip 1
(transmitter),load into l:F the RAM access code which identifies
the 32 bits of data to transfer to the XRAM and YRAM registers.
Next, set the NEWC bit 1:E:3 to a 1. After transferring the data
from RAM to the XRAM or YRAM registers, the NEWC bit is reset
to a 0 by the SP. Chip 0 (receiver), on the other hand, will provide
the XRAM and YRAM data one sample time following the loading of the RAM access code into register O:F, and will continue to
prOVide the same data at one sample time intervals until a new
RAM access code is loaded.
The interface memory acts as an intermediary during these host
to signal processor RAM data exchanges. Information transfer
between RAM and interface memory is accomplished by the signal processor logic unit moving data between the SP main bus
and the SP 110 bus. The SP logic unit normally transfers a word
from RAM to interface memory once each clock cycle of the SP
device. In the transmitter, a word is transferred from SP RAM to
the interface memory every sample time. In the receiver, a word is
transferred from RAM to the interlace memory every sample time
as well. Each RAM word transferred to the interface memory is
32-bits long. These bits are written by the SP logic unit into interface memory registers 5, 4, 3, and 2. Registers 3 and 2 contain
the most significant byte and least sigmficant byte, respectively,
of the XRAM data. 'Registers 5 and 4 contain the most and least
significant bytes of YRAM data, respectively.
RAM Access Codes
The SP logic unit determines the SP RAM address to read from,
or write to, by the code stored in the RAM Access bits of interface
memory register F (RAM Access R in the receiver O:F and RAM
Access T in the transmitter 1:F).
When reading from or writing into RAM, no bits are provided for
handshaking or interrupt functions. The NEWC bit can be used
as a mechanism to provide sample and baud intervals. Since the
NEWC bit is checked, once per baud in chip 0 and once per
sample in chip 1, the user can set the NEWC bit and wait for it to
be cleared. Depending on which chip the NEWC bit was set, the
time interval from the setting to the clearing of the NEWC bit will
be either one sample or one baud time. This, however, will not
guarantee that the action of reading and writing the XRAM and
YRAM Will occur in the middle of an actual sample or baud time.
Only the transmitter (chip 1) allows data to be transferred from
interface memory to SP RAM. When set to a 1, bit 1:F:7 signals
the SP logic unit to disable transfer of SP RAM data to the interface memory, and instead, to transfer data from interface memoryto SP RAM. When writing intoSP RAM, 32 bits of data in the
XRAM and YRAM registers will be written into the appropriate
1-96
R2424
2400 bps Full-Duplex Modem
Table 13.
RAM Access Codes
RAM Access Code
Node
Function
RAM Read
RAM Write
Chip
Reg. No.
1
2
3
4
5
6
7
Demodulator Output
Low Pass FiHer Output
Input Signal to Equalizer Taps
AGC Gain Word
Equalizer Tap Coefficients
Equalizer Output
Rotated Equalizer Output
(Received Point Eye Pattern)
Decision Points
(Ideal Eye Pattern)
Rotated Error
Rotation Angle
Phase Error
Self Test Error Counter
56
-
40
41-40
14
-
2, 3, 4, 5
2, 3, 4, 5
2,3,4,5
2, 3
2,3,4,5
2,3,4,5
2, 3, 4, 5
8
9
10
11
12
53
11
-
0
0
0
0
0
0
0
51
-
0
2, 3, 4, 5
52
12
10
00
-
0
0
0
0
2,3,4,5
4, 5
2,3
2, 3
02
03
82
83
03
83
84
84
85
1
1
1
1
1
1
1
1
4, 5
2, 3
4, 5
2, 3
4,5
4, 5
2,3
2, 3
-
OHIO
DTMF Tone Duration
DTMF Interdigit Delay
Pulse Interdlgit Delay
Pulse Relay Make Time
Pulse Relay Break TIme
Handshake Abort Counter
Handshake Abort Timer
CTS Off-Time
04
04
05
06
07
88
87
NOTE: 1. All the chip 1 access codes are not valid before R531D-18.
2. Access codes are hexadecimal.
3. Only chip 1 RAM can be written.
4. CTS Off-Time IS not valid before R531D-22
Table 15.
BER Summary
Data Rete
Bit Error Rate
Originate Mode
Answer Mode
2400 bps
1 x 10- 5
19.0 dB
17.3 dB
1200 bps
1 x 10- 5
8.3 dB
8.1 dB
ERROR RATES
R2424
Bit error rate (BER) is a measure of the throughput of data on the
communication channel. It is the ratio of the number of received
bits in error to the number of transmitted bits. This number
increases with decreasing signal-to-noise ratio (SNR). The type
of line disturbance and the modem configuration affect the BEA.
Table 14.
600 bps
1
10- 5
5.0 dB
5.0 dB
300 bps
1 x 10- 5
10.4 dB
7.2 dB
X
Test Condition: Signal Level = - 43 dBm,
Sync for 2400 bps, 1200 bps, 600 bps,
Async for 300 bps,
With 3002 Unconditioned Line.
Tables 14 through 16 summarize the BERs for various conditions. Figure 14 shows the BER measurement setup.
Table 16. BER Summary
BER Summary
R2424
Signal to Noise Ratio
Signal to Noise Ratio
R2424
Signal to Noise Ratio
Data Rete
Bit Error Rete
Originate Mode
Answer Mode
Data Rate
Bit Error Rate
Originate Mode
Answer Mode
2400 bps
1 x 10- 5
16.6 dB
16.2 dB
2400 bps
1 x 10- 5
17.0 dB
16.6 dB
1200 bps
1 x 10- 5
8.2 dB
7.9 dB
1200 bps
1 x 10- 5
7.7 dB
7.9 dB
600 bps
1
X
10- 5
5.0 dB
5.0 dB
600 bps
1 x 10- 5
4.6 dB
4.5 dB
300 bps
1
X
10- 5
9.2 dB
7.0 dB
300 bps
1 x 10- 5
9.3 dB
6.2 dB
=
Test Condition: Signal Level = -40 dBm,
Sync for 2400 bps, 1200 bps, 600 bps,
Async for 300 bps,
Back-To-Back.
-30 dBm,
Teat Condition: Signal Level
Sync for 2400 bps, 1200 bps, 600 bp's,
Async for 300 bps,
With 3002 Unconditioned Line.
1-97
::D
N
~
N
~
"TI
cC
c
...(;
~
~
~
f-'
"TI
5.
6c
LINE
SIMULATOR
(3002)
SEG FA-1445
..
'tI
CD
-
IMPAIRMENT
SOURCE
BRADLEY
2A AND 2B
-.
LEVEL METER
HP 3552A
ATTENUATOR
HP 350D
III
;:;:
[
cO
(Xl
::II
AI
CD
'V
CD
MODEM
TEST SET
PHOENIX
5000
MODEM
TRANSMITTER
MODEM
RECEIVER
2- TO 4-WIRE
HYBRID
2- TO 4-WIRE
HYBRID
MODEM
RECEIVER
MODEM
TRANSMITTER
MODEM
TEST SET
PHOENIX
5000
a-
3
AI
::I
()
CD
-I
CD
~
UI
!a
c
LEVEL METER
HP 3552A
ATTENUATOR
HP 350D
f-
IMPAIRMENT
SOURCE
BRADLEY
2A AND 2B
f-
LINE
SIMULATOR
(3002)
SEG FA-1445
•
'tI
..
-=
::I
tT
'0
tn
~
~o·
I\)
~
C)
C)
."
NOTE: SIGNAL AND NOISE ARE MEASURED WITH 3 KHZ FLAT WEIGHTING.
C
'i"
C
C
'0
CD
><
i:
o
Do
C'D
3
2400 bps Full-Duplex Modem
R2424
Table 17.
Modem Power Requirements
Voltage
Tolerance
Current (Typical) @ 25°C
Current (Max) @ DOC
+5 Vdc
+ 12 Vdc
-12 Vdc
±5%
±5%
±5%
390 mA
25 mA
4 mA
<455 mA
< 30 mA
< 5 mA
Note: All voltages must have ripple ,,;;0.1 volts peak-to-peak.
Table 18.
Modem Environmental Restrictions
Parameter
Specification
Temperature
Operating
Storage
Relative Humidity:
Altitude
OOC to +60°C (32°F to 140°F)
- 40°C to +80°C (- 40°F to 176°F) (Stored in heat sealed antistatic bag and shipping container)
Up to 90% noncondensing, or a wet bulb temperature up to 35°C, whichever is less.
-200 feet to + 10,000 feet
Table 19.
Modem Mechanical Considerations
Parameter
DIN Connector Version
Board Structure:
Mating Connector:
PCB Dimensions:
DC Version
Width
Length
Height
M VersIon
WIdth
Length
Height
Weight (max):
Lead Extrusion (max.):
DIP Connector Version
Board Structure
Dimensions
Width
Length
Height
Weight (max.)
Pin Length (max.)
Specification
Single PC board with a 3-row 64-pin right angle male DIN connector with rows A and C populated.
The modem can also be ordered with the following DIN connector: 64-pin DIN right angle female,
64-pin DIN vertIcal male or 64-pin DIN vertical female.
Female 3-row 54-pin DIN receptacle with rows A and C populated. Typical mating receptacle:
Winchester 96S-6043-0531-1, Burndy R196B32ROOAOOZ1, or equivalent.
3.937 in. (100 mm)
4.725 in. (120 mm)
0.75 in. (19 mm)
3.937 in. (100 mm)
3.328 in. (82 mm)
0.40 in. (10.2 mm)
0.45 Ibs. (0.20 kg.)
0.100 In. (2.54 mm)
Single PC board with a row of 30 pins and a row of 31 pins in a dual in-line pin configuration.
2.0 in. (50.8 mm)
3.5 in. (88.9 mm)
0.2 in. (5.08 mm) above, 0.13 in. (3.30 mm) below
2.6 oz. (73g)
0.53 in. (13.5 mm) above
1-99
R2424
2400 bps Full-Duplex Modem
MALE 64·PIN
DIN CONNECTOR
MALE 64-PIN
DIN CONNECTOR
-1
3.937
COMPONENT
SIDE
0.496
(12.6)
(100)
COMPONENT
0.496
(12.6)
~~~~~~~~SI=D=E==~~=t
8 un~j.l=
!t:,;,;~:::::---::'-.."J ~ ~"J
j
4.100 (83.2)
0.200 MAX
/
(104) 4.725
(120)
COMPONENT AREA
+tl5.1~-----~====~==-fDf:I]
0.062
'(11.1)
(1.6)
0.100 MAX
0.062 (5.1)
0.100 MAX
(11.1)
- (1.6)
COMPONENT AREA
(2.54)
DIN CONNECTOR VERSION
0.096 DIA (4 PL)
(2.5)
0.100
(2.54)
0.100
(2.54)
~~~~~ MAX
Q, ___
1
L
0.062
(1.6)
m
______
0.535
(13.6)
i-----~
=*
t
UNITS: INCHES
mm
UJO.130MAX]
(3.3)
DIP CONNECTOR VERSION
Figure 15. R2424 Modem Dimensions and Pin Locations
1-100
R2424
2400 bps Full-Duplex Modem
FCC RULES PART 68 REQUIREMENTS
R2424 MODEM INSTALLATION AND
MAINTENANCE
The FCC Rules Part 68 requires that the telephone interface
leads shall:
This section contains installation instructions and maintenance
procedures for the Rockwell R2424DC Modem. It also contains a
special notice from the Canadian Department of CommunIcations (DOC) for Canadian operation and from the Federal Communications Commission (FCC) for United States operation.
1. Be reasonably physically separated and restrained from; not
routed in the same cable as; nor use the same connector as
leads or metallic paths connecting to power connections.
Note
Power connections are defined as the connections
between commercial power and any transformer, power
supply rectifier, converter or other circuitry associated
with the modem. The connections of the interface pins
(includirigthe + 12 Vdc, -12 Vdcand +5 Vdc) are not
conSidered power connections.
GENERAL DESCRIPTION
The Rockwell R2424DC modem is designed to be used with the
United States or Canadian Telephone Switched Networks in
2-wirefull-duplex dial-up operation. The modem requires protective circuitry registered with the Federal Communications Commission (FCC) Part 68 which allows direct connection to the U.S.
SWitched telephone network. This circuitry also complies with
the canadian Department of Communications (DOC) Terminal
Attachment Program (TAP) which similarly defines their
SWitched telephone network requirements.
2. Be reasonably physically separated and restrained from; not
routed in the same cable as; nor use adjacent pins on the
same connector as metallic paths that lead to unregistered
equipment, when specification details provided to the FCC do
not show that the interface voltages are less than nonhazardous voltage source limits in Part 68.
The R2424DC features automatic dial and answer capabilities
along with surge suppression and hazardous voltage and longitudinal balance protection. Its maximum output signal level at the
telephone interface is set at -10 dBm ± 1 dBm (permissive
mode of operation).
Note
All the DIN connector interface voltages to the modem
have been established as non-hazardous.
ROUTING OF TELEPHONE INTERFACE LINES
Two standard telephone jack connectors (RJ11s) are mounted
side by side on one edge of the board and are Wired in parallel.
One is for connection to the telephone line network and the other
for the telephone headset connection.
In routing the telephone interface leads from the modem telephone connector jacks to the telephone line network connection,
the following precautions should be strongly considered for
safety.
1. The telephone interface routing path should be as direct and
as short as possible.
INSTALLATION AND SIGNAL ROUTING
INSTRUCTIONS
2. Any cable used in establishing this path should contain no
Signal leads other than the modem telephone interface leads.
PHYSICAL MOUNTING
The modem module may be physically incorporated into the customer's end product by utilizing the four corner 0.156" diameter
mounting holes (for the self-hooking plastic type standoffs or for
bolting it down to some rigid structure) or by installing the module
into card guides.
3. Any connector used In establishing this path shall contain not
commercial power source signal leads, and adjacent pins to
the TIP and RING (T and R) pins In any such connector shall
not be utilized by any signals other than those shown in this
document.
ELECTRICAL INTERFACING INSTRUCTIONS
The electrical interfacing is accomplished via the DIN (Euro) connector (for external power inputs and digital logic signals) and
the telco connectors (for the telephone network connection).
Note that the telephone interface connectors are phYSically separated from the modem interface control connector and extreme
care must be taken in routing the telephone interface leads from
the modem to the telephone network (line connector jack in the
wall).
MAINTENANCE PROCEDURE
Under the FCC Rules, no customer is authorized to repair
modems. In the event of a Rockwell modem malfunctioning,
return it for repair to an authorized ROCKWELL INTERNATIONAL distributor (if In canada) or send it directly to the Semiconductor Products Division, Rockwell International Corporation, EI Paso, Texas 79906.
1-101
R2424
2400 bps Full-Duplex Modem
SPECIAL INSTRUCTION TO USERS
Sample label below:
If the Rockwell modem has been registered with the Federal
Communications Commission (FCC), you must observe the 101lowing to comply with the FCC regulations:
Unit contains Registered Protective Circuitry which complies with Part 68 of FCC Rules.
FCC Registration Number: AMQ9SQ-14211-DM-E
A. All direct connections to the telephone lines shall be made
through standard plugs and telephone company provided
jacks.
Ringer Equivalence: 0.9B
Note
The Rockwell modem module has the FCC registration
number and ringer equivalence number permanently
affixed to the solder side of the PCB and any unit containing this modem shall use this Information for the
label requirements.
B. It is prohibited to connect the modem to pay telephones or
party lines.
C. You are required to notify the local telephone company of the
connection or disconnection of the modem, the FCC registration number, the ringer equivalence number, the particular line
to which the connection is made and the telephone number to
be associated with the jack.
SPECIAL NOTICE FROM THE CANADIAN
DEPARTMENT OF COMMUNICATIONS
Note
If the proper jacks are not available, you must order the
proper type of jacks to be installed by the telephone
company (VSOC RJ11 for permissive mode of operation).
The Canadian Department of Communications label identifies
certified equipment. This certification means that the equipment
meets certain telecommunications network protective, operational and safety reqUirements. The Department does not guarantee the equipment will operate to the user's satisfaction.
D. You should disconnect the modem from the telephone line if it
appears to be malfunctioning. Reconnect it only if it can be
determined that the telephone line and not the modem IS the
source of trouble. If the Rockwell modem needs repair, return
ittothe ROCKWELL INTERNATIONAL CORPORATION. This
applies to the modem whether it is in or out of warranty. Do not
attemptto repair the unit as this is a violation olthe FCC rules
and may cause danger to persons or to the telephone network.
Before installing this equipment, users should insure that it is
permiSSible to be connected to the facilities of the local telecommunications company. The equipment must also be installed
using an approved method of connection. In some cases, the
company's Inside wiring associated with a single line individual
service may be extended by means of a certified jack-plug-cord
ensemble (telephone extension cord). The customer should be
aware that the compliance With the above conditions may not
prevent degradation of service in some situations. Existing telecommunications company requirements do not permit their
equipment to be connected to customer-provided jacks except
where specified by individual telecommunications company tariffs.
TELEPHONE COMPANY RIGHTS
AND RESPONSIBILITIES
A. The Rockwell modem contains protective circuitry to prevent
harmful voltages to be transmitted to the telephone network. If
such harmful voltages do occur, then the telephone company
may temporarily discontinue service to you. In this case, the
telephone company should:
The Department of Communications requires the Certificate
Holders to identify the method of network connection in the user
literature provided With the certified terminal equipment.
1. Promptly notify you of the discontinuance.
2. Afford you the opportunity to correct the situation which
caused the discontinuance.
Repairs to certified eqUipment should be made by an authorized
Canadian maintenance facility deSignated by the supplier. Any
repairs or alterations made by the user to thiS equipment, or
equipment malfunctions may give the telecommunications company cause to request the user to disconnect the eqUipment.
3. Inform you of your right to bring a complaint to the FCC
concerning the discontinuance.
B. The telephone company may make changes in its facilities
and services which may affect the operation of your equipment. It is, however, the telephone company's responsibility to
give you adequate notice in writing to allow you to maintain
uninterrupted service.
Users should ensure for their own protection that the electrical
ground connections of the power utility, telephone lines and internal metallic water pipe system, if present, are connected
together. ThiS precaution may be particularly important in rural
areas.
LABELING REQUIREMENTS
CAUTION
A. The FCC requires that the following label be prominently displayed on the outside surface of the customer's end product
and that the size of the label should be such that all the
required information is legible without magnification.
Users should not attempt to make such connections themselves, but should contact the appropriate electric inspectIOn authority, or electrician, as appropriate.
1-102
RC2424DP/DS
Integral Modems
'1'
Rockwell
RC2424DP/DS 2400 bps Full-Duplex
Modem Data Pump Device Set
INTRODUCTION
FEATURES
The Rockwell RC2424DPIDS is a 2400 bps, full-duplex,
OEM, data pump modem device set. The RC2424DPIDS
operates over the public switched telephone network
(PSTN), as well as on pOint-to-point leased lines.
• CMOS DSP and IA devices
• 2-wire full-duplex operation
• Compatible configurations:
-CCITT V.22 bis, V.22N6
-CCITT V.21 and V.23
-BeIl212A and 103
The set consists of two CMOS VLSI components-a digital signal processor (DSP) device and an integrated
analog OA) device. The DSP is available in a 64-pin quad
in-line package (QUIP) or a 68-pin plastic leaded chip carrier (PLCC) package. The IA device is available in a 40-pin
dual in-line package (DIP) or a 44-pin PLCC package.
• Receive dynamiC range: -9 dBm to -43 dBm
• Maximum transmit level: 0.0 dBm ±1.0 dB,
programmable in 1 dB steps
• Multi-modem detection support
The RC2424DP/DS modem meets the requirements
specified in CCITT V.22 bis, V.22 NB, and V.21, as well
as Bell 212A and Bell 103.
-Programmable tone detect bandpass filters
-Zero-crossing detector
• V.22 bis fallback/fall-forward - 2400/1200 bps
Full compatibility with V.23 is realized with the addition of
an external FSK demodulator. The V.23 capability allows
asynchronous operation at 1200 bps with backward channel operation to 75 bps. RC2424DPIDS DSP firmware, in
conjunction with a fully compatible hardware interface,
directly configures and controls the V.23 FSK demodulator
device. Moreover, the centralized transmitter function in
the RC2424DPIDS allows 'clean" soft turn-offs in V.23
mode.
• Synchronous serial data
-2400, 1200, 600 bps ± 0.01 % (PSK modulation)
InternaVextemal!slave clock selection
• Parallel data both synchronous and asynchronous
-Synchronous:
Normal sync: a-bit data for transmit and receive
-SDLC/HDLC support:
Transmitter: Flag generation, 0 bit stuffing,
CCITT CRC generation
Receiver: Flag detection, 0 bit un-stuffing,
CCITT CRC checking
-Asynchronous:
5,6,7, or a data bits per character
Odd/even parity generation/checking
(or 9't1 data bit)
2400,1200,600 bps +1% or (2.3%), -2.5%
(PSK modulation)
75, 300, 600, 1200 bps (FSK modulation)
In addition, the SDLCIHDLC support eliminates the cost of
an external serial input/output (SIO) device in products incorporating error correction protocols.
• Programmable ring detect
-Min and max frequency range
• Programmable dialer
-Make/break times for pulse dialling
-DTMF on time for touch-tone dialling
-Interdigit times for both pulse and tone dialling
-DTMF Level: 0.0 dBm ± 1.0 dB (high tone level is
2.0 dB ± 0.5 dB above low tone leveO
Document No. 29200N53
Data Sheet
(Preliminary)
1-103
Order No. MD53
December 1988
2400 bps Full-Duplex Modem Device Set
RC2424DP/DS
• Diagnostics
R2424 COMPATIBILITY
-Read/write RAM
-Serial eye pattern output
-EQM value in RAM
A high performance modem engine, the RC2424DP/DS is
the functional and performance equivalent of Rockwell's
R2424DS modem with the following enhancements:
• Host bus interface memory for configuration, control,
and parallel data; compatible with either 8086 or 6502
microprocessor bus
-2-device implementation in CMOS
-V.21 and V.23 interface
-Asynchronous/synchronous parallel data transfer
over the microprocessor bus interface
-Extended 2.3% overspeed in asynchronous,
DPSKlQAM modes
-SDLC/HDLC framing in parallel data mode
-Additional configuration and control capabilities
• RS-232C (TTL compatible) interface for RTS control
and serial data
• Adaptive and fixed compromise equalization
• Test Configurations:
-Local analog loopback
-Local digitalloopback
-Remote digitalloopback
These options and enhancements, combined with a user
accessible, dual port .interface memory (RAM) in the DSP,
offer maximum flexibility in customizing the
RC2424DP/DS to meet a wide variety of functional requirements.
• Answer and originate handshake
• Leased line operation
• Power requirements:
The RC2424DP/DS device set, with the addition of a few
external filter components, interfaces easily to a data access arrangement (DM). The RC2424DP/DS general interface is illustrated in Figure 1.
-± 5 Vdc± 5%
-500 mW typical
RC2424DP/DS DEVICE SET
r - - ----,
4
I
EYE
PATTERN
'- _G~N':R~~'!..
I
I
..J
2
INTEGRATED
ANALOG
(IA)
DIGITAL
SIGNAL
PROCESSOR
(DSP)
HOST
PROCESSOR
PARALLEL
BUS
INTERFACE
ANTIALIASING
FILTER
COMPONENTS
ANCILLARY
CIRCUIT
INTERFACE
2
1-_ _ _ _ _~3:..-------"'"""~
V.23
DEMODULATOR
Figure 1. RC2424DP/DS General Interfaces
1-104
TELEPHONE
LINE
INTERFACE
2400 bps Full-Duplex Modem Device Set
RC2424DP/DS
Guard tone on/off must be controlled by the host depending on the state of the handshake sequence, i.e., the host
should enable guard tone when DSR is turned on.
TECHNICAL SPECIFICATIONS
CONFIGURATIONS, SIGNALING RATES, AND DATA
RATES
DTMF Tones: When Dial/Call Progress configuration is
selected (CONF bits = 81) and the DTMF bit is set to a 1,
dual tone multi-frequency (DTMF) tones can be
generated. The specific DTMF tone generated is specified
by the host loading the Transmitter Data Buffer (TBUFFER) with the appropriate digit code shown in Table 2.
The selectable modem configurations, along with the corresponding signaling (baud) rates and data rates, are
listed in Table 1. The modem configuration is established
by the CONF bits.
Note: Bit names refer to control bits in DSP Interface
Memory which are set or reset by the host processor (see
Software Interface Section, Figure 7 and Table 11).
User Defined Tones: When Tone Generator/Tone Detector configuration is selected (CONF bits = 80), a userdefined single or dual tone can be generated. I n this mode,
the transmitter immediately begins sending the frequencies specified in DSP RAM. The tones will remain on as
long as Tone Generator/Tone Detector configuration is
selected and the tone amplitudes are greater than zero.
Setting one of the two amplitudes to zero selects single
tone frequency.
TONE GENERATION
Answer Tone: A CCITT (2100 :I: 15 Hz) or Bell (2225 :I:
10Hz) answer tone is generated depending on the
selected configuration.
Guard Tone: A guard tone of 1800 :I: 20 Hz (GTS bit = 0)
or 550:1: 20 Hz (GTS bit = 1) can be generated (enabled
by the GTE bit). The level of transmitted power is 6:1: 1 dB
or 3 :I: 1 dB below the level of the data power in the main
channel for the 1800 Hz or 550 Hz guard tone, respectively. The total power transmitted to the line is the same
whether or not a guard tone is enabled. When a guard tone
is generated, the main channel transmit path gain is
reduced by 0.97 dB or 1.76 dB for the 1800 Hz or 550 Hz
guard tone, respectively.
Note: Frequencies from 0 to 1675 Hz can be sent when
the ORG bit is set, or frequencies from 1925 Hz to 2875
Hz can be sent when the ORG bit is cleared. 1800 Hz frequency can be sent by setting the GTE bit with GTS = 0
and ORG =0.
Table 1. Configurations, Signaling Rates and Data Rates
Transmhter Carrier
Frequency (Hz) ±0.01 %
Modulation1
Configuration
QAM
V.22 bis
V.22A/B
DPSK
Answer 2
Orlalnate2
2400
2400
2400
Data Rate
(bps)
Baud
Bits Per
Constellation
± 0.01%
ISvmbolstsec.1
Svmbol
Polnta
1200
24003
1200
1200
12003
6003
600
4
16
600
600
2
1
4
2
Be1l212A
DPSK
2400
1200
12003
600
2
4
Bell 103
FSK
2225 M
2025S
1270M
1070S
300'
300'
1
1
V.21
FSK
1650 M
1850S
980 M
1180 S
300'
300'
1
1
V.23 Forward Channel
FSK
1300M
2100S
1300M
2100S
1200'
1200'
1
1
V.23 Forward Channel
FSK
1700 M
2100S
1700 M
2100S
600'
600'
1
1
V.23 Backward Channel
FSK
390 M
450S
390M
450S
75'
75'
1
1
Notes:
1.
2.
Modulation legend: QAM
DPSK
FSK
M indicates a mark condition;
Quadrature Amplitude Modulation
Differential Phase Shift Keying
Frequency Shift Keying
S indicates a space condition.
3.
Synchronous accuracy = ±0.01 %; asynchronous accuracy = -2.5% to + 1.0% (+2.3% if extended overspeed is selected).
4.
Value is upper limit for serial (e.g., 0-300).
1-105
RC2424DPjDS
2400 bps Full-Duplex Modem Device Set
TONE DETECTION
Status Bit: TONEC
Answer Tone and Call Progress Tones: When DiaVCall
Progress configuration is selected (CON'F bits = 81), tones
can be detected as follows:
Detection level: 0 dBm to -43 dBm
Default detection level: -43 dBm
Response time: 25 :I: 2 ms
Call progress frequency range: 340 ± 5 Hz to 640 :I: 5 Hz
Tones are detected as energy above the threshold within
a digital bandpass filter. These filters are single bi-quad fiR
filters*. The pass bands can be changed by writing new
coefficients to DSP RAM. The tone detect threshold can
also be changed in the DSP RAM.
Status Bit: TONEA
Answertones (2100:1: 15 Hz or 2225:1: 10Hz) or Bell FSK
originate tone (1270 :I: 10Hz)
Detection level:O dBm to -43 dBm
*Except the filter represented by TONEA in Dial/Call
Progress configuration, which is a dual biquad fiR filter.
Default detection level: -43.dBm
Response time: 25
:I:
2 ms
Zero Crossing Detector: A zero crossing detector is always available. The detector can measure tone frequencies between 100 Hz and 3000 Hz. The zero' crossing
counter increments for both positive and negative zero
crossings.
Status Bits: ATV25, ATBELL (ORG=1), BEL 103
(ORG=O)
Tones are detected as energy above a certain threshold
within a digital bandpass filter. The pass band of the dual
bi-quad infinite impulse response (IlR) filter (Call
Progress) or the single bi-quad fiR filter (answer tone Or
Bell FSK originate) can be changed by writing new coefficients to DSP RAM. The tone detectthreshold can also be
changed in DSP RAM.
DATA ENCODING
The data encoding conforms to CCITT Recommendations
V.22 bis, V.22A/B, V.23, or V.21 , or to Bell 212A or 103,
depending on the selected configuration.
V.23 and V.21 Tones: When Tone Generator/Tone
Detector configuration is selected (CONF bits = 80), tones
can be detected as follows:
EQUALIZERS
Equalization functions are incorporated that improve performance when operating over low quality lines.
V.23 forward channel mark: 1300 :!: 10Hz
Automatic Adaptive Equalizer. A 13-tap automatic
adaptive equalizer is provided in the receiver circuit for
V.22 bis, V.22 and Be1l212A configurations. Updating of
the taps can be enabled or disabled (EQFZ). The equalizer
taps can also be reset (EQRES).
Status Bit: TONEA
V.23 backward channel mark: 390
:I:
10Hz
Status Bit: TONEB
V.21 high band mark (1650:1: 10 Hz) or low band mark
(980:1: 10 Hz)
Fixed Compromise Equalizer. A fixed compromise
equalizer is provided in the transmitter. The equalizer can
be enabled or disabled (CEQ bit).
Table 2. Dial Digits/Tone Pairs
Hex
Code
00
01
02
03
04
05
06
07
08
09
OA
08
OC
00
OE
OF
10
Dial
Digit
0
1
2
3
4
5
6
7
8
9
*
Spare (8)
Spare (C)
Spare (0)
#
Spare (F)
TRANSMITTED DATA SPECTRUM
Tone Pair
(Hz)
(Hz)
941
697
697
697
770
770
770
852
852
852
941
697
770
852
941
941
After making allowance for the nominal specified compromise equalizer characteristic, the transmitted line signal has a frequency spectrum shaped by a square root of
a 75 percent raised cosine filt~r. Similarly, the group delay
of the transmitter output is within :I: 150 microseconds over
1336
1209
1336
1477
1209
1336
1477
1209
1336
1477
1209
1633
1633
1633
1477
1633
Table 3. RTS· CTS Response Time
CTS Transition
OFF to ON
ONto OFF
Note:
1300 Hz Calling Tone
1-106
Configuration
V.22 bis
V.22
Be1l212A
V.21
Bell 103
V.23
All
Constant
Carrier
s2ms
s2ms
s2ms
2-5ms
2·5ms
5·20 ms
s2ms
Controlled
CIrrler
270ms
270ms
270ms
2·5ms
2-5ms
5·2Oms
s2ms
The eTS OFF to ON response time is host programmable
in DSP RAM for some configurations.
RC2424DP/DS
2400 bps Full-Duplex Modem Device Set
the frequency range 900 Hz to 1500 Hz (low channeQ and
2100 Hz to 2700 Hz (high channeQ.
RTS • CTS RESPONSE TIME
The response times of CTS relative to a corresponding
transition of RTS are listed in Table 3. The response time
depends on the receiver operating in either constant carrier or controlled carrier mode (CC bit).
TRANSMIT LEVEL
The default transmitter output level is -6.0 dBm :1:1.0 dB.
The output level can be selected from 0 dBm to -15 dBm
in 1 dB steps (l1.VL bits).
ASYNC/SYNC, SYNC/ASYNC CONVERSION
TRANSMIT TIMING
For parallel asynchronous data transfer, an
asynchronous-to-synchronous converter is provided in the
transmitter, and a synchronous-ta-asynchronous converter is provided in the receiver. Asynchronous or
synchronous' mode is selected by the ASYNC bit. The
asynchronous character format is 1 start bit, 5 to 8 data
bits (WDSZ bits), an optional parity bit (PARSL and PEN
bits), and 1 or 2 stop bits (STB bit). Valid character sizes,
including all bits, are 7, 8, 9, 10 or 11 bits per character.
Transmitter timing is selectable between internal
(:1:0.01%), external, or loopback (TXCLK bits). When external clock is selected, the external clock rate must equal
the desired data rate :1:0.01 % with a duty cycle of 50:1: 20%.
SCRAMBLE~DESCRAMBLER
A self-synchronizing scrambler/descrambler satisfying the
applicable CCITT recommendation or Bell specification is
incorporated. The scrambler and descrambler can be
enabled or disabled (SOlS and DDIS bits, respectively)
When the transmitter's converter is operating at the basic
signaling rate, no more than one stop bit will be deleted per
8 consecutive characters. When operating at the extended
rate, no more than one stop bit will be deleted per 4 consecutive characters.
RECEIVE LEVEL
The receiver satisfies performance requirements for
received line signals from -9 dBm to -43 dBm. The
received line signal is measured at the Receiver Analog
(RXA)input
Two ranges of signaling rates are provided (selectable by
the EXOS bit):
Basic range: +1% to -2.5%
Extended overspeed range: +2.3% to -2.5%
RECEIVER TIMING
A :I: 0.01% frequency error in the associated transmit
timing source can be tracked.
Break is handled in the transmitter and receiver as
described in V.22 bis. If the RC2424DP/DS transmitter
detects M to 2M + 3 bits of "start" polarity from the DTE,
where M is the number of bits per character, the
RC2424DPIDS will transmit 2M + 3 bits of start polarity. If
the modem detects more then 2M +3 bits of start polarity,
it will transmit all these bits as start polarity.
CARRIER RECOVERY
A :I: 7 Hz frequency offset in the received carrier can be
tracked with less than a 0.2 dB degradation in bit error rate
(BER).
CLAMPING
The RC2424DPIDS receiver will output the 2M + 3 or more
bits of start polarity on RXD and will set the BRKD bit.
Received Data (RXD) is clamped to a constant mark
whenever the Received Une Signal Detector (RLSD) output is off.
1-107
2400 bps Full-Duplex Modem Device Set
RC2424DP/DS
PIN ASSIGNMENTS
The RC2424DP/DS pin assignments are shown in
Figure 2. The pin assigments are listed by pin number in
Tables 4 and 5 for the DSP and IA devices, respectively.
N.c.
AGND
Mil
Mia
N.C.
EYECLK
RDCLK
MI6
MI5
MI4
MI3
N.C.
MI2
TDCLK
TBCLK
TXD
RBCLK'
RXD
RLSD
TIDRC
RXD
TXR1
TXR2
TRS
(3105)
(3105)
(3105)
(3105)
N.C.
N.C.
DGND
D3
D2
D1
DO
IRQ
WRITE
cs
RS3
RS2
64-PIN QUIP (DSP)
REC IN
BIAS
AGND
-5VA
Mil
.5VA
POR
T/DRC
MI2
N.C.
MI3
TRAN OUT
TLKRELAY
N.C.
OHRELAY
DSR
N.C.
RSO
RSI
RS4
MI12
REC OUT
RESET TC
Ai
READ
MI15
MI5
N.C.
N.C.
XTLD
XTLI
RESET
N.C.
EYESYNC
EYEX
EYEY
EN86
D4
MI8
DGND
N.c.
D7
AGND
AGND
DGND
XTCLK
RD
MI2
MI7
.5V
D6
D5
.5VA
MI6
MI7
CfS
RTS
MI14
N.c.
DOND
DGND
AGND
-5VA
MI4
MilO
MI13
AGND
Mill
a.
40·PIN DIP (IA)
QUIP/DIP Set
•
.. Q
• • ~ Q II) N
UaofD ... ~UUIllf5!:::!:
ziiiczz+c:l!:E
.G~O~_~~~=~I~:=~;
wJ~
dRS4
DGND
RS3
RS2
RSI
DGND
RSO
tI,l;.
DIjl!
EN8S
EYEY
EYEX
10
11
12
13
14
15
16
60
59
58
57
56
55
54
53
52
51
50
49
•
17
18
19
20
21
22
23
24
25
26
4&
47
46
45
44
RLSD
RXD
CO"'''C'')N''':S~~;~
l~h~K
MI7
AGND
DGND
MI5
-5VA
N.C.
DGND
MI8
Mil
DGND
MI6
MI5
MI4
MI3
N.C.
MI2
TDCLK
~~=gM~~~==~~=3;~~
•
T/DRC
N.C.
TLKRELAY
10
11
12
13
14
15
16
OHRELAY
17
cjocCt ... QC'fl'lltQQcj
z8~iii'jiii'j8z
ICC
44·PIN PLCC
6S·PIN PLCC
b.
PLCC Set
Figure 2. RC2424DP/DS Device Set Pin Assignments
1·108
39
38
37
36
35
34
33
32
31
30
29
N.C.
REC OUT
REC IN
BIAS
AGND
Mil
.5VA
MI2
MI3
TRAN OUT
N.C.
2400 bps Full-Duplex Modem Device Set
RC2424DP/DS
Table 5. RC2424DPIDS IA Pin Assignments
Table 4. RC2424DP/DS DSP Pin Assignments
68-Pln PLCC
Pin Number
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
64-PlnQUIP
Pin Number
1
2
-3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
-
31
32
33
-
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
-
f1i~~
1:lif~
PLCC
P number
it~
1
2
3
4
5
6
7
Mil
MI8
OGNO
N&..~K
ROCLK
RBCLK
fOOL
fiLm.
ILQElC
RTS
RXO (3105)
TXRl (3105)
TXR2 (3105)
TRS (3105)
N.C.
N.C.
OGNO
07
DB
05
D4
03
D2
01
QQ.-
100....W£lITE
~
READ
RS4
OGNO
RS3
RS2
RSI
OGNO
RSO
OA
OA
OA
OA
OA
B
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
IA
IA
IA
DB
DB
DB
INOB
INOB
INOB
INOB
INOB
INOB
INOB
INOB
OC
IA
IA
IA
IA
IA
IA
IA
IA
tiQ..
OSR
RI
EN86
EYEY
EYEX
EYESYNC
~
RESET
XTLI
XTLO
N.C.
N.C.
N.C.
+5V
DB
DB
IA
OB
OB
DB
-1
2
3
4
-5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
-
26
27
28
29
30
31
32
33
34
35
-
36
37
38
39
40
Sljnal
N me
N.C.
AGNO
MI14
MI6
MI8
N.C.
MI7
AGNO
DGNO
MI5
0
IA
IA
OA
IA
OA
OA
Notes:
MI Modem Interconnection (e.g., MI7), see Figure 3.
N.C. No Connection, leave pin disconnected (open).
I/O Type: See Table 7.
=
=
1-109
itge
-5Yf,
~TC
EQL
T/ORC
N.C.
ll.KBa8Y
OHRELAY
N.C.
OGNO
-5VA
Mit 0
Mill
AGNO
MI13
MI4
AGNO
DGNO
N.C.
N.C.
TRANOUT
MI3
MI2
+5VA
Mil
AGNO
BIAS
RECIN
RECOUT
N.C.
MI12
MI15
AGNO
+5VA
N.C.
Not••:
MI = Modem Interconnection (e.g., M17), see Figure 3.
N.C. = No Connection, leave pin disconnected (open).
I/O Type: See Tables 7 and 8.
IA
I
M!Z.
MI2
RO
XTCLK
rulliO
CTS
TXO
TBCLK
TOCLK
MI2
N.C.
MI3
MI4
MI5
MI6
OGNO
4O-Pln DIP
Pin Number
IA
INOA
IA
00
00
0(00)
I
I (DB)
(OA)
o
I
•
I
2400 bps Full-Duplex Modem Device Set
RC2424DP/DS
The RC2424DPIDS hardware functional interface signals
are shown in Figure 3. In this diagram, any point that is active low is represented by a small circle at the signal point.
a clock intended to activate logic on its falling edge (highto-low transition) is called active high (e.g., TDCLK). When
a clock input Is associated with a small circle, the input activates on a falling edge. If no circle is shown, the input activates on a rising edge.
Edge triggered inputs are denoted by a small triangle (e.g.,
TDClK). Open-Collector (open-source or open-drain) outputs are denoted by a small half-circle (e.g., IRQ). Active
low signals are overscored (e.g., POR).
The hardware interconnect signals are organized into
functional groups. These signals, along with their interface
circuit type codes, are listed in Table 6. The digital and
analog interface characteristics are defined in Tables 7
and 8, respectively.
HARDWARE INTERFACE SIGNALS
A clock intended to activate logic on its rising edge (Iowto-hightransition) is called active low (e.g., RDClK), while
RC2424DP/DS DEVICE SET
,
•
iift
f4--
11
+5V
Cft
EVEX
TXD
EVEV
TDCLK
XTCLK
EVESVNC
EVE
PATTERN
EVECLK
GENERATOR
H
RXD
V.24
INTERFACE
OSCILLOSCOPE
1
"
RDCLK
RLSD
j4--+5V
I-- -5V
TRAN OUT
DSR
ANTIALIASING
Ri'
REC OUT
EN86
,
ii!A6
RC2424DP/DS
RC2424DP/DS
DSP
IA
~
HOST
PROCESSOR
BUS
INTERFACE
RSG-RS4
DECODER
p..c
ilm
(
+5V
-A. A.
A
. y y
J
RECIN
COMPONENTS
~
~
t-
TELEPHONE
LINE
INTERFACE
OHRELAV
DATA BUS (8)
ADDRESS BUS (5)
I
FILTER
cs
~
RD
TLKRELAV
~
~FJ:.A.A.
'1 "..
ANCILLARY
CIRCUIT
INTERFACE
RBCLK
TBCLK
XTLI
CRYSTAL
XTLO
RXD
TXRl
TXR2
RESET
TCM3105
...
TRS
I
NOTE: REQUIRED EXTERNAL COMPONENTS
ARE NOT SHOWN (SEE FIGURE 9).
Figure 3. RC2424DP/DS Functlonallnterfaea
1-110
2400 bps Full-Duplex Modem Device Set
RC2424DP/DS
Table 6. RC2424DPIDS Hardware Interface Signals
(Cont'd)
Table 6. RC2424DPIDS Hardware Interface Signals
I/O
I/O
Name
Type
DSP IUId IA Overheed
AGNO
OONO
+5\1
GNO
GNO
PWR
-5V
PWR
RESET
IA
POR
INOA
FiEsETTc
IA
XlLI
I
XlLO
0
DSP/Hoet Procell8or Pararallel
07
D6
INOB
INOB
OS
INOB
D4
INOB
D3
INOB
02
INOB
01
INOB
DO
INOB
RS4
IA
RS3
IA
RS2
IA
RSI
IA
RSO
IA
OS
IA
REAO(~_
IA
WRITE(R/W)
IA
IRQ
OC
EN86
IA
DSP/TCM3105 Interface
XTCLK
TOCLK
RDCLK
Analog Ground Retum
Digital Ground Retum
+5 VoH Supply (OSP & IA)
-5 VoH SUpply (IA)
Reset (OSP)
Power·On·Reset (IA)
Reset Time Constant (IA)
Crystal In
Crvstal Out
Bus Interface
FiTs
IA
OA
OA
IA
CTS
DSR
TXO
AXD
OB
IA
OA
OA
ALSo
Ai
OA
OB
lA/Extemal Filter ComDOnen18
t
Extemal TransmH Clock
Transmitter Dete Clock
Receiver Date Clock
Request;ro-Send
Clear-To-Send
Dete Set Ready
Serial Transmit Dete
Serial Reosive Date
Reosivad Une SIgnal Detector
Rlna Indicator
IA Reosiver Op Amp Input
RECIN
DB
IA Receiver Op Amp Output
OA
RECOUT
IA Transmitter Analoa OUtcut
TRANOUT
DO
External Flher ComDonen18/Une Interface
I
Dete Bus (S-Bits)
RXA
TXA
I
~
DE
OF
Receive Analog Input
Transmit Analoa Outout
IAtUne Interface
t
I
OHRELAV
00
DSP/Anclllarv Clrcuhs
Off-Hook Relav Driver
I
OA
TBCLK
RBCLK
OA
INAnclllarv Clrculls
TranemH Baud Clock
Reosive Baud Clock
Register Select (5-Bits)
~
Chip Select
Read Enable or +2 CId by which parity is generated and
checked during the asynchronous parallel data mode (ASYNC = 1). The options are:
5
4
Parity Selected
0
0
1
1
0
1
0
1
Stuff Parity ("9th Data Bit") (see TXP, RXP)
Space Parity
Even Parity
Odd Parity
PE
OE:5
0
Parity Error. When set to a 1, status bit PE indicates that a character with bad parity was
received in the asynchronous mode, or bad CRC was detected in the SDLC/HDLC
synchronous mode. When a 0, a character with good parity was received.
PEN
06:3
0
Parity Enable. When set to a 1, control bit PEN enables parity generation and checking
during asynchronous parallel data mode. When reset to a 0, parity generation and checking
is disabled.
RA
07:1
0
Off-Hook Relay Activate. When control bit RA is set to a 1, the OHRELAY output is activated causing the relay to close (off-hook); when RA is reset to 0, the OHRELAY is turned
off causing the relay to open (on-hOOk). Note: The host has exclusive control of the
OHRELAY output through the RA bit except in pulse dial mode.
RBUFFER
00:0-7
0
Receive Data Buffer. The host obtains data from the modem receiver in the parallel data
mode by reading a data byte from the RBUFFER.
RDBF
1E:0
-
Receiver Data Buffer Full. When set to a 1, status bit RDBF signifies that the modem_
wrote valid received data into register 00 (RBUFFER). This condition can also cause IRQ to
be asserted. The host reading or writing register 00 resets the RDBF bit to O. (See RDBIE
and RDBIA.)
RDBIA
1E:6
0
Receiver Data Buffer Interrupt Active. When the receiver data buffer full interrupt is
enabled (RDBIE~ 1) and register 00 is written to by the DSP (RDBF is set to a 1), the
modem asserts IRQ and sets RDBIA to a 1 to indicate that RDBF being a 1 caused the interrupt. The host reading or writing register 00 resets the RDBF bit to a 0 and clears the interrupt request due to RDBF. (See RDBF and RDBIE.)
RDBIE
1E:2
0
Receiver Data Buffer Interrupt Enable. When control bit RDBIE is a 1 (interrupt enabled),
the modem will assert IRQ and set the RDBIA bit to a 1 when RDBF is set to a 1 by the
DSP. When RDBIE is a 0 (interrupt disabled), RDBF has no effect on IRQ or RDBIA. (See
RDBF and RDBIA.)
RDL
07:6
0
Remote Digital Loopback Request. When control bit RDL is a 1 , the modem initiates a request for the remote modem to go into digital loopback, RXD is clamped to a mark, and the
RLSD bit and RLSD signal will be reset until the loop is established. When the host resets
the RDL bit the modem sends the RDL terminating sequence.
1-123
2400 bps Full-Duplex Modem Device Set
RC2424DP/DS
Table 11. Interface Memory Bit Definitions (Cont'd)
Mnemonic
Memory
Location
Default
Value
Name/Deacrlptlon
ROLE
07:7
0
Remote Digital Loopback Reaponse Enable. When set to a 1, control bit ROLE enables
the modem to respond to the remote modem's digitalloopback request, thus going into loopback. When this occ!!!!Jhe modem clamps RXO to a mark; resets the CTS and RLSO bits
to a 0, and turns the CTS and OCO signals OFF. The TM bit is set to a 1 to inform the host
of the test ststus.
RI
OF:3
0
Ring Indicator. When set to a 1, status bit RI indicates that a valid ringing signal is being
detected. Ringing is detected if pulses are present on the RO input in the 15 Hz - 68 Hz frequency range (default frequency range). The RI bit follOW!Jhe ringing signal with a 1 during
the ON time and a 0 during the OFF time coincident with RI output signal. The minimum and
maximum valid ring frequencies are host programmable in OSP RAM. If the maximum value
is set to zero, the RI bit will go on and off with each half of the ring frequency sine Wf!Ne.
RLSO
OF:7
0
Received Une Signal Detector. When status bit RLSO is set to a 1, the carrier is being
detected and receive data is valid. When a 0, the carrier Is not being detected and RXO output is clamped to mark. Note: RXO is also clamped to mark during retrain while the RLSO
bit remains on.
RTDET
OE:7
0
Retrain Detected. When set to a 1, status bit RTOET indicates that a retrain request sequence has been detected.
RTRN
08:1
0
Retrain. When control bit RTRN set to a 1 and the modem is in data mode, the modem reo
quests retrain (or automatic rate change - see ARC) from the remote modem. RTRN Is set
to 0 when the prf!Nlous retrain Is completed. Note: If retrain Is not completed successfully,
the host must clear the RTRN bit.
Fallback from 2400 bps to 1200 bps per CCITT V.22 bls may be accomplished as follows:
1. Set the ARC bit to a 1 in both modems.
2. Set the RTRN bit to a 1 in either modem.
3. Set the NEWC bit to a 1.
Fall forward from 1200 bps to 2400 may be accomplished as follows:
1. Reset the ARC bit (with the remote modem hf!Nlng the ARC bit set).
2. Set the RTRN bit.
3. Set the NEWC bit.
If the remote modem can operate at the requested rate, the SPEED bits will be changed by
the modem to reflect the new rate after the retrain is completed.
If the remote modem cannot operate at the new rate, then no rate change will take place
during the retrain. In this case, the host must clear the RTRN bit.
RTS
08:0
0
Request to Send. When control bit RTS Is a 1 or the RTS input is ON, the CTS bit is set to
a 1 and the CTS output Is turned ON. When the RTS bit is reset to 0 and the RTS input is
OFF, the CTS bit is reset to a 0 and the CTS output is turned OFF.
RXP
01:0
0
Received Parity bit. This bit is only valid when parity is enabled (PEN = 1), and word size
Is set for 8 bits per character (WOSZ = 11). In this case, the parity bit received (or ninth data
bit) will be available at this location. The host must read this bit before reading the received
data buffer (RBUFFER).
S10ET
00:5
0
S1 Sequence Detected. Status bit S1 OET Is set to a 1 when the S1 sequence is being
detected. This bit is'reset to a 0 when the S1 sequence is not being detected.
SAOET
00:2
0
Scrambled Alternating Ones Sequence Detected. Status bit SAOET Is set to a 1 when
the Scrambled Alternating Ones sequence is being detected. This bit is reset to a 0 when
the Scrambled Alternating Ones sequence is not being detected. Note: SAOET is used to indicate the response of the remote modem to a V.22 bis rate change request or a remote
digital loopback request.
1-124
2400 bps Full-Duplex Modem Device Set
RC2424DP/DS
Table 11. Interface Memory Bit Definitions (Cont'd)
Mnemonic
Memory
Location
..
i
Default
Value
Name/Description
SCR1
OD:4
0
Scrambled Ones Sequence Detected. Status bit SCR1 is set to a 1 when Scrambled
Ones is being detected during handshake. This bit is reset to 0 when Scrambled Ones is not
being detected.
SOlS
03:2
0
Scrambler Disable. When control btt SDIS is a 1, the transmitter scrambler is disabled;
when SDIS is a 0, the scrambler is enabled.
SPEED
OE:0·2
0
Speed Indication. The SPEED status bits indicate the data rate at the completion of a hand·
shake:
2
1 0
Data Rate (bps)
0
0
0
0
0
0
1
1
300
600
1200
2400
0
1
0
1
SPLIT
03:5
0
Parallel Async Extended Overspeed TX/RX Split. When SPLIT is set to a 1 and EXOS is
set, the transmitter will transmit at the basic overspeed while the receiver receives at the ex·
tended overs peed rate.
STB
06:2
0
Stop Bit Number. When control bit STB is a 0, one stop bit is selected in asynchronous
mode; when a 1, two stop bits are selected.
SYNCD
OF:1
0
Sync Pattern Detected. When set to a 1, status bit SYNCD indicates that SDLC/HDLC
flags (7E pattern) are being detected. When reset to a 0, the 7E pattern is not being
detected.
SYNCMD
03:6,7
0
Synchronous Mode. Configuration bits SYNCMD select the synchronous mode (ASYNC =
0) from the following:
7
6
Synchronous Mode
0
0
0
1
Normal Sync
SDLC/HDLC Sync
TBUFFER
10:0·7
00
Transmitter Data Buffer. The host conveys output data to the transmitter in the parallel
mode (TPDM = 1) by writing a data byte to the TBUFFER when the TDBE bit is a 1. The
data is transmitted bit 0 first.
TDBE
1E:3
-
Transmitter Data Buffer Empty. When set to a 1, status bit TDBE signifies that the modem
has read transmit data from register 10 (TBUFFER) and the host can write new data into
register 10. This condition can also cause IRQ to be asserted. The host reading or writing
register 10 resets the TDBE bit to O. (See TDBI E and TOBIA.)
TDBIA
1E:7
0
Transmitter Data Buffer Interrupt Active. When the transmitter data buffer empty interrupt
is enabled (TDBIE is a 1) and register 10 is empty (TDBE is set to a 1). the modem asserts
IRQ and sets status bit TDBIA to a 1 to indicate that TDBE being a 1 caused the interrupt.
The host reading or writing register 10 resets the TDBIA bit to a 0 and clears the interrupt reo
quest due to TDBE. (See TDBIE and TDBE.)
TOBIE
1E:5
0
Transmitter Data Buffer Interru.E!J'nable. When control bit TDBIE is a 1 (interrupt
enabled), the modem will assert IRQ and set the TDBIA b~ to a 1 when TDBE is set to 1 by
the DSP. When TDBIE is a 0 (interrupt disabled). TDBE has no effect on IRQ or TDBIA.
(See TDBE and TDBIA.)
1-125
RC2424DP/DS
2400 bps Full-Duplex Modem Device Set
Table 11. Interface Memory Bit Definitions (Cont'd)
Mnemonic
lLVL
Memory
Location
13:4-7
Default
Value
6
Name/Description
Transmit Level Attenuation Select. The lLVL control code selects the transmnter analog
output level attenuation at the lXA pin as follows:
7
6
5
Transmit Level Attenuation
(dB ±O.5 dB)
4
0 0 0 0
o dB
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1 dB
2 dB
3 dB
4 dB
5 dB
6 dB
7 dB
8 dB
9 dB
10 dB
11 dB
12 dB
13 dB
14 dB
15 dB
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
The host can fine tune the transmit level to a value lying wnhin a 1 dB step by changing a
value in DSP RAM.
TM
OF:2
0
Test Mode. When set to a 1, status bit TM indicates that the selected test mode is active.
When TM is reset to a 0, no test mode is active.
TONEA
OB:7
0
Tone Filter A Energy Detected. When set to a 1, status bn TONEA indicates that energy
above the threshold is being detected by the Call Progress Monitor filter in the Dial Configuration (CONF =81) or that 1300 Hz FSK tone energy is being detected by the Tone A
bandpass filter in the Tone Detector configuration (CONF =80). When reset to a O. energy
is not being detected. The bandpass filter coefficients are host programmable in DSP RAM.
TONEB
OB:6
0
Tone Filter B Energy Detected. When set to a 1, status bit TONEB indicates that 390 Hz
FSK tone energy is being detected by the Tone B bandpass filter in the Tone Detector configuration (CONF =80). When reset to a O. energy is not being detected. The bandpass filter
coefficients are host programmable in DSP RAM.
TONEC
OB:5
0
Tone Filter C Energy Detected. When set to a 1, status bit TONEC indicates that enher
1650 Hz (ORG = 1) or 980 Hz (ORG 0) FSK tone energy is being detected by the Tone C
bandpass filter in the Tone Detector configuration (CONF =80). When reset to a 0, energy
is not being detected. The bandpass filter coefficients are host programmable in DSP RAM.
TPDM
08:6
0
Transmitter Parallel Data Mode. When control bit TPDM is a 1, the transmitter accepts
parallel data from the host microprocessor interface via the TBUFFER register for transmission rather than serial data from the TXD input pin. When TPDM is a 0, serial data from the
TXD input pin is accepted for transmission rather than parallel data from TBUFFER.
TRFZ
08:3
0
Timing Recovery Freeze. When control bn TRFZ is a 1, the updating of the receiver's
timing recovery algorithm is inhibited. When TRFZ is a 0, normal updating occurs.
=
1-126
2400 bps Full-Duplex Modem Device Set
RC2424DP/DS
Table 11. Interface Memory Bit Definitions (Cont'd)
Mnemonic
TXCLK
Memory
Location
13:0,1
I
Default
Value
0
Name/Description
Transmit Clock Select. The TXCLK control bits designate the origin of the transmitter data
clock:
1
0
Transmit Clock
0
0
1
1
0
1
0
1
Internal
Not Used (I nternal)
Extern'!!..N9..LK input)
Slave (RDCLK output)
When the external clock Is chosen, the host supplied clock must be connected to the
XTCLK input pin. The external clock will then be reflected at the TDCLK output pin.
When the slave clock is chosen, the transmitter clock output (TDCLK) is phase locked to
the receiver clock output (RDCLK).
TXP
11 :0
0
Transmit Parity bit. This bit is only active when parity is enabled (PEN = 1), stuff parHy is
selected (PARSL = 00) and word size is set for 8 bits per character. The host must load the
stuffed parity bit (or ninth data bH) in this location before loading the other 8 bits of data in
TBUFFER.
U1DET
00:3
0
Unscrambled Ones Detected. When set to a 1, status bH U1 DET indicates that V.22 bis
Unscrambled Ones sequence has been detected. This bH is reset to a 0 by the modem at
the end of the Unscrambled Ones sequence. (V.22 bis)
WDSZ
06:0,1
0
Data Word Size. The WDSZ control field sets the number of data bHs per character in
asynchronous mode as follows:
1
0
Data Bits/Character
0
0
1
1
0
1
0
1
6
7
8
5
XACC
10:7
0
X RAM Access Enable. When control bit XACC is a 1, the DSP accesses the X RAM associated with the address in XADD and the XCR bH. XWT determines if a read or write is
performed. The DSP resets XACC to a 0 upon RAM access completion.
XADD
1C:0-7
00
X RAM Address. XADD contains the X RAM address used to access the DSP's X Data
RAM (XCR = 0) or X Coefficient RAM (XCR = 1) via the X RAM Data LSB and MSB
registers (addresses 18 and 19, respectively). (See Table 12.)
XCR
1D:0
0
X Coefficient RAM Select. When control bit XCR is aI, XADD applies to the X Coefficient
RAM. When XCR is a 0, XADD applies to the X Data RAM. This bit must be set according
to the desired RAM address (Table 12).
XDAL
18:0-7
00
X RAM Data LSB. XDAL is the least significant byte of the 16-bit X RAM data word used in
reading or writing X RAM locations in the DSP.
XDAM
19:0-7
00
X RAM Data MSB. XDAM is the most Significant byte of the 16-bH X RAM data word used
in reading or wrHing X RAM locations in the DSP.
XWT
10:1
0
X RAM Write. When XWT is a 1 and XACC is set to aI, the DSP copies data from the X
RAM Data registers (18 and 19) into the X RAM location addressed by XADD and XCR.
When control bit XWT is a 0 and XACC is set to a 1, DSP reads X RAM at the location addressed by XADD and XCR and stores the data into the X RAM Data registers (18 and 19)
YACC
lB:7
0
Y RAM Access Enable. When control bit YACC is a 1. the DSP accesses the Y RAM associated with the address in YADD and the VCR bit. YWT determines if a read or write is
performed. The DSP resets YACC to a 0 upon RAM access completion.
1-127
--
2400 bps Full-Duplex Modem Device Set
RC2424DP/DS
Table 11. Interface Memory
Mnemonic
Memory
Location
DefauH
Value
Bit Definitions (Cont'd)
Name/Description (Cont'd)
YADD
1A:0-7
00
Y RAM Address. YADD contains the Y RAM address used to access the DSP's Y Data
RAM (yCR 0) or Y Coefficient RAM (YCR 1) via the Y RAM Data LSB and MSB
registers (adresses 16 and 17, respectively). (See Table 12.)
VCR
1B:0
0
Y Coefficient RAM Select. When control bit VCR Is a 1 , YADD applies to the DSp·s Y Coefficient RAM. When VCR is a 0, YADD applies to the Y Data RAM. This bR must be set according to the desired RAM address (Table 12).
YDAL
16:0-7
00
Y RAM Data LSB. YDAL is the least significant byte of the 16-bit Y RAM data word used in
reading or writing Y RAM locations in the DSP.
YDAM
17:0-7
00
Y RAM Data MSB. YDAM is the most significant byte of the 16-bit Y RAM data word used
in reading or writing Y RAM locations in the DSP.
YWT
1B:1
0
Y RAM Write. When YWT Is a 1 and YACC is set to a 1, the DSP copies data from the Y
RAM Data registers (16 and 17) Into the Y RAM location addressed by YADD and VCR.
When control bit YWT is a 0 and YACC Is set to a 1, the DSP reads Y RAM at the location
addressed by YADD and VCR and stores the data into the Y RAM Data registers (16 and
17).
=
=
1-128
2400 bps Full-Duplex Modem Device Set
RC2324DP/DS
tions operate at the 7200 Hz sample rate. The receiver
baud rate function operates at the 600 Hz.
DSP RAM ACCESS
The DSP contains four sections of 16-bit wide random access memory (RAM). Because the DSP is optimized for
performing complex arithmetic, the RAM is organized into
real (X RAM) and imaginary f'{ RAM) sections, as well as
data and coefficient sections. The host processor can access (read or write) the X RAM only, the Y RAM only, or
both the X RAM and the Y RAM simultaneously in either
the data or coefficient section.
Two RAM access bits (XACC and YACC) in the DSP interface memory tell the DSP to access the X RAM and/or Y
RAM. The DSP tests these bits each sample period.
HOST PROGRAMMABLE DATA
The parameters available in DSP RAM are listed in Table
12 along with the X RAM or Y RAM address and corresponding XCR or VCR bit value.
INTERFACE MEMORY ACCESS TO DSP RAM
HOST DSP READ AND WRITE PROCEDURES
The DSP interface memory acts as an intermediary during
host to DSP RAM or DSP RAM to host data exchanges.
The addresses stored in DSP interface memory RAM Address registers (i. e., XADD and YADD) by the host, in conjunction with the data or coefficient RAM bits (i. e., XCR
and VCR) determine the DSP RAM addresses for data access.
DSP RAM Write Procedure
1. Before writing to DSP interface memory, verify that
XACC and YACC are reset to O.
2. Load the RAM address into XRAM address
(XADD) and/or YRAM address f'{ADD).
3. Write the desired data to the RAM data registers
One or two 16-bit words are transferred between DSP
RAM and DSP interface memory once each internal DSP
cycle. The transmitter and the receiver sample rate func-
(XDAM, XDAL, YDAM, orYDAL).
4. Set the coressponding coefficient RAM select bits
(XCR, VCR) as necessary.
Table 12. DSP RAM Parameters (Cont'd)
Table 12. DSP RAM Parameters
XCR/
No. YCR*
X RAM YRAM
Addr
Addr
0
II
-
-
0
II
1
I
2
2
3
4
5
6
7
8
9
10
II
12
13
14
15
1
I
I
I
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
I
-
2F
30
I
30
-
-
16
-
3F
71
7C
72
7D
7E
6D
-
-
16
-
-
6D
73
6F
-
0
74
-
I
I
I
I
I
I
I
I
I
I
I
I
12
-
6F
-
-
12
14
15
-
16
-
3F
-
-
-
IF
2D
2F
15
16
3F
-
-
XCR/
No. YCR*
Parameter
1st Equalizer Tap, Real
Last Equalizer Tap. Real
1st Equalizer Tap, Imaginary
Last Equalizer Tap, Imaginary
Rotated Error. Real
Rotated Error, Imaginary
Max AGC Gain Word
Pulse Diallnterdigit Time
Tone Diallnterdigit Time
Pulse Dial Relay Make Time
Pulse Dial Relay Break Time
DTMF Duration
Tone I Angle Increment Per Sample
Tone 2 Angle Increment Per Sample
Tone I Amplitude
Tone 2 Amplitude
Max Samples Per Ring Frequency
Period
Min Samples Per Ring Frequency
Period
Real Part of Error
Imaginary Part of Error
Rotation Angle for Carrier Recovery
Rotated Equalizer Output, Real
Rotated Equalizer Output, Imaginary
lower Part of Phase Error
Upper Part of Phase Error
Upper Part of AGC Gain Word
lower Part of AGC Gain Word
Average Power
Phase Error
Tone Power (ATBEll, BElI03 or
TONEA
Tone Detect Threshold (Call
Progress Energy)
Tone Power (ATV25 or TONEB)
X RAM YRAM
Addr
Addr
31
36
-
31
32
I
I
33
I
37
-
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
0
0
38
3B
52
-
-
-
-
-
-
IC
32
-
-
31
32
33
34
35
37
38
39
3A
3B
76
77
78
79
7A
45
46
47
48
49
-
21
IC
lD
Parameter
Tone Power (TONEC)
Tone Detect Threshold (ATBEll,
BEll 03, or TONEA)
Tone Detect Threshold (ATV25 or
TONEB)
Tone Detect Threshold (TONEC)
Zero Crossing Counter
Eye Quality Monitor (EQM)
Filter I Coefficient aO
Filter I Coefficient al
Filter I Coefficient a2
Filter I Coefficient fll
Filter I Coefficient fl2
Filter 2 Coefficient aO
Filter 2 Coefficient al
Filter 2 Coefficient a2
Filter 2 Coefficient fll
Filter 2 Coefficient fl2
Filter 3 Coefficient aO
Filter 3 Coefficient al
Filter 3 Coefficient a2
Filter 3 Coefficient fll
Filter 3 Coefficient fl2
Filter 4 Coefficient aO
Filter 4 Coefficient al
Filter 4 Coefficient a2
Filter 4 Coefficient fll
Filter 4 Coefficient fl2
Tum·on Threshold (PSK)
Turn-off Threshold (PSK)
RlSD Turn-off Time (PSK)
Tum-on Threshold (FSK)
Turn-off Threshold (FSK)
·XCR if an XRAM address is listed; YCR if a YRAM
address is listed.
1-129
2400 bps Full-Duplex Modem Device Set
RC2424DP/DS
5. Setthe appropriate RAM write bits (XWT, YWT).
then sets the NEWS bit to a 1 to indicate DSP
RAM read completion.
6. Setthe appropriate RAM access bits (XACC,
7. Ifthe NSIE bit is a 1, IRQ is also asserted and
YACC).
NSIA is set to a 1'when NEWS is set to a 1. NSIA
is cleared by writing a 0 into the NEWS bit, which
also causes IRQ to return high if no other interrupt
requests are pending.
7. After the DSP has transferred the contents of the interface memory RAM data registers into DSP
RAM, the DSP resets the XACC and/or the YACC
bit to a 0, then sets the NEWS bit to a 1 indicate
DSP RAM write completion.
Note: Steps 3 and 4 can be accomplished simultaneously.
8. If the NSIE bit is a 1, IRQ is also asserted and
SOFTWARE INTERFACE CONSIDERATIONS
NSIA is set to a 1 when NEWS is set to a 1. NSIA
is cleared by writing ;i 0 into the NEWS bit, which
also causes IRQ to return high if no other interrupt
requests are pending.
INTERRUPT REQUEST HANDLING
DSP interface memory registers 00,10, 1E, and 1F have
unique hardware connections to the interrupt logic.
Register 00 is the Receive Buffer (RBUFFER) and register
10 is the Transmit Buffer (TBUFFER). Registers 1E and
1F hold interrupt flag, interrupt enable, and interrupt active
bits.
Note: Steps 4 and 5 can be accomplished simultaneously.
DSP RAM Read Procedure
1. Before reading from DSP interface memory, verify
that XACC and YACC are reset to a O.
When a condition occurs that satisfies an interrupt criteria,
the corresponding interrupt flag bit is set. This interrupt flag
can be reported to the host eitherkthe host polling the
interrupt fl~bits (i.e., not using IRQ) or by being interrupted by IRQ. When an interrupt enable bit and the corresponding interrupt flag are both set to a 1, IRQ is
asserted and the corresponding interrupt active bit set to
2. Load the RAM address into X RAM Address
(XADD) and/or Y RAM Address (YADD)
register(s).
3. Set the corresponding XCR and/or VCR bit(s) appropriately.
4. Reset XWT and/or YWT to a 0, inform the DSP that
a 1.
a RAM read will occur when XACC and/or YACC
is setto a 1.
The interrupt flag setting conditions are status changed
detected, configuration changed acknowledged, receive
buffer full and transmit buffer empty. Table 13 identifies
the interrupt conditions and bits, and describes the interrupt clearing procedures.
5. Set XACC and/or YACC to a 1 to Signal the DSP to
perform the RAM read.
6. After the DSP has transferred the contents of RAM
into the interface memory RAM data registers, the
DSP resets the XACC and/or the YACC bit to a 0,
Table 13. Interrupt Request Bits
Interrupt
Active Bit
Interrupt
Enable Bit
Interrupt
Flag Bit
Interrupt Condition Description
Interrupt Clear Procedure
NSIA
NSIE
NEWS
New status detected (NEWS transitioned from a 0 to 1) Host wrnes a 0 into NEWS
a. RAM read or RAM write occurred
(Clears NSIA to a 0)
b. Status bit changed in register OA, OB, OE, or OF
NCIA
NCIE
NEWC
New configuration acknowledged by DSP
(NEWC transitioned from a 1 to a 0)
Host wrnes a 0 into NCIE
(Clears NCIA to a 0)
TDBIA
TDBIE
TDBE
Transm itter Data Buffer is em ply and can be written
(TDBE transnioned from a 0 to a 1)
Host reads from or wrnes to
register 10 (TBUFFER)
(Clears TDBE and TDBIA to 0)
RDBIA
RDBIE
RDBF
Receiver Data Buffer is full and can be read
(RDBF transitioned from a 0 to a 1)
Host reads from or
register 00 (RBUFFER)
(Clears RDBF and RDBIA to 0)
1-130
RC2424DP/DS
2400 bps Full-Duplex Modem Device Set
DIAL PROCEDURE
The host dial procedure is the same as outputting data to
be transmitted using ~UFFER (Figure 8). The modem
timing accounts for the DTMF tone duration and
amplitude, pulse make/break ratiO, and interdigit delay.
These dialing parameters are host programmable in DSP
RAM.
The level of the high DTMF tone is 2 dB greater than the
level of the low DTMF tone.
The dialer default parameters are given in Table 14.
Table 14. Dial Default Parameters
Parameter
DTMF Tone Duration
DTMF Interdigit Delay
DTMF Total Output Power Level
DTMF Low Band Power Level
DTMF High Band Power Level
Pulse Relay Make Time
Pulse Relay Break Time
Pulse Interdigit Delay
Default Value
70ms
70ms
OdBm
-4dBm
-2dBm
40ms
60ms
750ms
OR DELAY 5 SEC
TDBE (1 E:03) = 1?
N
lAST DIGIT?
Y 1"---------;
TDBE (1 E:03) = 1?
Figure 8. Dial Sequence
1-131
RC2424DP/DS
2400 bps Full-Duplex Modem Device Set
flexibility in choosing the component values for R14 and
C11 is permissible provided that the pole of the filter is
maintained within approximately ±5% of the correct value.
When calculating the pole of the filter, component
tolerances should be carefully considered.
DESIGN CONSIDERATIONS
REQUIRED MODEM INTERFACE CIRCUIT
The RC2424DP/DS is supplied as two VLSI devices to be
designed into original equipment manufacturer (OEM)
circuit boards. The recommended modem interface circuit
(Figure 9) and parts list (Table 15) illustrate the
connections and components required to connect the
modem to the OEM electronics.
Transmit Output
An external discrete smoothing filter must be added to the
Transmit Output (TRAN OUT) signal to attenuate the high
frequency aliases generated by the integrated switched
capaCitor filters. This is necessary to meet FCC
requirements on transmitted high frequency energy. The
pole of this filter may be calculated using the same formula
as for the receiver filter, I.e.,
DAAINTERFACE
The following discussion of the interface to the integrated
analog device is presented to enable deSigners to modify
the design of the recommended line interface circuit. Also,
the designer may wish to incorporate an existing line
interface deSign with the modem device set.
Filter Pole (Hz) = 1/(211: • R16 • C12)
The components values of R16 = 68.1 Kg and C12 = 1000
pF place the pole at 2337 Hz. This may seem unusual as
the response of a smoothing filter is generally designed to
be flat in the band of interest, and then rolling off before the
sampling rate. The bandsplit filter inside the IA is
pre-distorted so that when cascaded with an external
continuous first order smoothing filter, the response
across the band is flat.
Receive Input
Receive In (REC IN) and Receive Out (REC OUT) are pins
associated with an integrated uncommitted operational
amplifier inside the IA device. In conjunction with the three
discrete components shown (R13, R14 and C11), the
amplifier forms a first order lowpass antialiasing filter. This
filter's function is to attenuate high frequency noise near
and above the effective sampling rate of the integrated
bandsplit filters (230.4 KHz).
Some flexibility in choosing the values for R16 and C12 is
permiSSible, provided some guidelines are followed. The
choice of R16 and C12 must position the filter pole within
±5% of 2337 Hz.
The design of the modem requires that the pole of the
anti-aliasing filter be .fixed at 2337 Hz. This is calculated
using the formula
The TRAN OUT integrated driver can drive a resistive load
as low as 10 Kg . This drive capability is desirable for the
FCC Part 68 defined "programmablt!" mode.
Filter Pole (Hz) = 1/(211:· R14· C11)
The recommended values of 68.1 Kg for R14 and 1000 pF
for C11 give the correct value for the filter pole. Some
1-132
:::D
+5V
~
--..---"VVv------'-'-,
~
-5V
105%,114 W
EVESVNC
EVEX
EVEV
."
C
CRl
RESET
EVEClK
-it, 1
41'
4. ,
391
I
Mi2
iD'
2
MI8
!"
::0
ID
0
0
3
3
ID
~
0ID
0-
::0
(")
-'
W
W
N
....
N
DO
Dl
D2
D3
D4
D5
D6
D7
~4
:::
RC2424DPIDS
+ SV
151
os
READ
WRITE
M
A.
A3
A2
EN86
en
RBCL.K
TBClK
3i:
DSR
0
0ID
Iii
FiCSD
RXC
3
:i
RDClK
TOCL.K
ID
XTCL.K
...
;.
0
ID
RC2424DP/DS
(QUIP)
Ul
DSP
..-..-
TXC
m
EfS
MI3
~
Mil
~
N/C
43
2a
..
"
27
20
3o'
31
RS4
RS3
~;
RS2
--=-
XTALO
XTALI
6
"
36
8
""
II
10
"
~o :~~
48
37
.,.,
44
N/C
:;~
i"
24 000 MHZ
d
+5VA
C3
18 PF 5%
-=-
MilS
47 "
RESET Te
MI12
5%
MI13
TL.KRELAV
TIoRC
TlKRElAV
All
12
TIoRC
~~
OHREL.AV
15
OHRELAV
Ro
_
POR
R13
RXA
R2
0<: R12
~~:
(DIP)
R10
27M, 5%
25
23
".
21
C
20
REC OUT
Mill
R9
35
26
N/C
C12
2~
13
NIC
10~~
40
N/C
6
17
110K 1%
BIAS
Cl
T~~e
TRAN OUT
i:
-5V
27
1 - 1_ _ _ _,
35
42
15
16
25
+12V
681K 1%
tT
"C
RXB
,..
N/C
N/C
NIC
I-!---
TC~3105
15~~K
10 COL
NIC
NIC
c
::;:
3
14 COT
8 TXO
13 RXD
12 TXRl
5
_
N/C
15
3
1%
TOlD
~
V 50V
31~~!45?1 --'--~~
R5
402K
6
OPEN~
NIC
a-
o
o
C13
8
N/C
(")
I\)
.;:.
R16
T/DRC .9
RD
(J)
MI14i-'--....- - - ,
E;
ID
~
C6
MI7
3
+5V
U~
I
TXA
6c
R18
"C
R19
RXA
4
TXR2
TRS
:~:,
W
C15
+5V
DGND
~~~
*
I
~
50Y
AGND
NOTE: UNLESS OTHERWISE SPECIFIED
1 RESISTOR VAWES ARE IN OHMS,
_ . _ - - - ' , 1 6 6 ' OSC2
TXA
11 NIC
"T1
C
_12V
(SEE
NOTE 3)
til
:t:
1%, ll1W
2 CAPACITOR VAWES ARE IN MICROFARADS, ± 20%, 5fN
3. ADJUST VAWE FOR CORRECT MAAKISPACE BIAS.
~
c.
CD
3
o
~
c;"
CD
(J)
!.
I~~_
2400 bps Full-Duplex Modem Device Set
RC2424DP/DS
PC BOARD LAYOUT GUIDELINES
Table 15. Recommended Modem Interface Circuit
Qty
1
1
1
1
1
1
1
10
1
1
1
2
2
1
1
1
1
1
1
1
1
1
1
3
1
1
1
Part Number
The following guidelines should be adhered to when laying
out a printed circuit board for the RC2424DP/DS devices.
The pin numbers reflect the DSP 64-pin QUIP and the IA
40-pin DIP packages.
Description
Rockwell RC2424DPIDS DSP
Rockwell RC2424DP/DS IA
TCM310S FSK Modulatorl
Demodulator
U4
1458 Dual Op
US
SN74LS04 Hex Inverter
Y1
24.00014 MHz Crystal
Y2
4.4336 MHz Crystal
C1, C4, C6, C7, C9, 0.10 !If, 20%, SOV
C10,C13, C1S, C16,
C23
02
39 pF, S%, SOV
C3
1B pF, S%, SOV
CS
10 "F, 5%, 50V
C11, C12
1000 pF, 5%, SOV
020,021
15 pF, 5%, SOV
R1
34.BKQ,1%,1/BW
R2
66.SKQ,1%,1/BW
RS
40.2KQ,1%,1/BW
R6
57.6KQ,1%,1/BW
R7
1 Q, S%,1/4W
R9
110KQ,1%,1/BW
R10
2.7M Q, 5%, 1/B W
R11
3KQ, S%,1/BW
R12
47KQ, 5%,1/B W
R13
23.7KQ,1%,1/BW
R14,R16,R1B
6B.1KQ,1%,1/BW
R15
42.2KQ,1%,1/BW
R19
34.0KQ,1%,1/BW
CR1
Schottky Diode, LL103B
U1
U2
U3
1.
The DSP, IA and all supporting analog circuitry, including the data access arrangement should be
located on the same area of printed circuit board.
2.
The DSP device grounds should be routed
separately from the IA device.
3.
The DSP should be located on the pin 1 side of the
IAdevice.
4.
IA digital signals (pins 3, 4, 5, 8, 10, 12,23,28,29,
and 31) should be routed directly to the DSP,
avoiding all analog components.
5.
Routing of the RC2424DP/DS signals should
provide maximum isolation between noise sources and noise senitive inputs. When layout requirements necessitate routing these Signals
together, they should be separated by neutral
signals. The DSP and IA noise source, neutral,
and noise sensitive pins are listed in Table 16.
6.
A 1.0Q/1 0 f1F RC network is needed to decouple
the +5V supply. This must be done at the IA
device to isolate it from the DSP device.
7
As a general rule, digital signals should be routed
on the component side of the PCB while the
analog signals are routed on the solder side.
The sides may be reversed to match a particular
OEM requirement.
8.
All power traces should be at least a 0.1 inch width.
9.
The analog components should be located on the
pin 40 side of the 40-pin IA device.
10. The IA AGND pins (1, 6, 21, 24, 32, and 3€!) and
the DGND pins (7 and 25) should be tied
together as ground directly under the device.
11. A 0.1 f1F ceramic capacitor ,is used to decouple
the -5V supply. This should be done in the immediate proximity of the IA device.
12.
1-134
All circuitry connected to crystal pins 44 and 45 on
the DSP device should be kept short to prevent
stray capacitance from affecting the oscillator.
2400 bps Full-Duplex Modem Device Set
RC2424DP/DS
Table 16. RC2424DP/DS Pin Noise Characteristics
Device
-
DSP
64.pin QUIP
DSP
68.pin PLCC
IA
40-Pin DIP
IA
44.pin PLCC
Function
+5V
DGND
Crystal
Centrol
Eye Pattern
V.23 Interface
Host Bus Interface
Serial Interface
IA Interface
No Cennection
+5V
DGND
Crystal
Centrol
Eye Pattern
V.23 Interface
Host Bus Interface
Seriallnteriace
IA Interface
No Cennection
+SVA
-SVA
DGND
AGND
Contrel
Analog
DSP Interface
No Connection
Neutral
Noise Source
44,45
9,38,43,52
39·40
14
t8-34
8,10,36-37,55
4,41
11·13
5·7,53,56-58
1·2, 50-51, 59, 61-64
3,15·16,35,42,46-48,60
35
1,15,19,40,51,54
30·31
27,56
63,65
39, 42-44,57-59
36-37,45,47-50, 52-53
24, 29, 38, 61
25·26
66
2·14,16-18,20,
22-23, 41, 60, 62
21, 28, 32-34, 46, 55, 67-68
30,39
9,18
7,17,25
1,6,21,24,32,38
10, 14-15
2, 19-20, 22, 26-27, 33-37
3-5, 8, 23, 28-29, 31
12
11,13,16,40
+5VA
-5VA
DGND
AGND
Centrol
Analog
DSP Interface
No Cennection
Noise Sensitive
49,
17,54
33,43
11,20
9,19,27
2, 8, 23, 26, 35, 42
12,16-17
3,21-22, 24, 29-30, 36-38,
40-41
4-5,7,10,25,31-32,34
1-135
14
1,6,13,15,18,28,39,44
•
2400 bps Full-Duplex Modem Device Set
RC2424DP/DS
GENERAL SPECIFICATIONS
Table 17. Modem Power Requirements
Voltage
Tolerance
+5VDC
-5VDC
.,5%
.,5%
Current (Typical)
@2S·C
Current (Maximum)
@O·C
85mA
20mA
130mA
40mA
Note: Input voltage ripple ",t volts peak-to-peak.
Table 18. Modem Environmental Specifications
Parameter
Temperature
Operating
Storage
Relative Humidity
AIt~ude
Specification
O·C to + 6O·C (32"F to 140· F)
- 40·C to + 80·C (-40·F to 17S°F) (Stored in heat sealed antistatic bag and shipping container)
Up to 90% noncondensing, or a wet bulb temperature up to 35·C, whichever is less.
- 200 feet to + 10,000 feet
Table 19. Crystal Specifications
Parameter
Operating Temperature
Storage Temperature
Nominal Frequency @ 25·C
Frequency Tolerance @ 25·C
Temperature Stability @ TA = O·C to SO·C
Calibration Mode
Shunt CapacHance
Load Capacitance
Drive Level
Aging, per Year Max.
Oscillation Mode
Series Resistance
Max. Frequency Variation with 1S.5 or 19.5 pF Load Capacitance
Third Lead
Sleeving
1-136
Value
O·C to SO·C
-55·C to 85·C
24.00014 MHz
.,0.0015% (.,15 PPM)
.,0.003% (.,15 PPM)
Parallel resonant
7 pF max.
18.,0.2 pF
2.5 mW max., Test at 20 nanowatts
0.0005% (5PPM)
Fundamental
25 ohms max.
+0.0035% (+35 PPM)
Required
Required
2400 bps Full-Duplex Modem Device Set
RC2424DP/DS
I
PACKAGE DIMENSIONS
l
DIM.
A
AI
M.
b
TOP VIEW
0
01
D2
03
SIDE VIEW
e
CHAM. J x 45 DEG.
h
J
a
R
Rl
CHAM.
hX450EG
3 PLCS
EJECTOR MARKS
4 PLCS BOTTOM
ONLY CTYPJ
MILLIMETERS
MIN. MAX.
INCHES
MIN. MAX.
4.14
4.39
1.47
1.37
2.31
2.46
0.457TYP
25.02 25.27
24.00 24.26
20.19 20.45
23.24 23.50
1.27 SSC
0254 TYP
1.15 TYP
45'TYP
0.163 0.173
0.054 0.058
0.091 0.097
0.018 TYP
0.985 0.995
0.945 0.955
0.795 0.805
0.915 0.925
0.050 sse
0.010TYP
0.045 TYP
4S'TYP
0.89TYP
0254 TYP
0.035 TYP
0.010TYP
SECTION A-A
BOTTOM VIEW
6S.pin PLCC
,
r
SEA liNG
"
...
DIM.
A
Al
A2
b
0
01
SIDE VIEW
02
CHAM. J x 45 DEG.
03
e
h
J
a
R
Rl
CHAM.
h X 45 DEG.
3 PLCS
EJECTOR MARKS
4 PLCS BOTTOM
ONLY (lYPJ
BOTTOM VIEW
TYP. FOR EACH AXIS
(EXCEPT FOR BEVELED EDGEl
SECTION A-A
44.pin PLCC
1-137
MILUMETERS
MIN. MAX.
INCHES
MIN. MAX.
4.14
4.39
1.37
1.47
2.31
2.46
0.457TYP
17.45 17.60
16.46 16.56
12.62 12.78
15.75 REF
1.27 sse
0.254 TYP
1.15TYP
45' TYP
0.89TYP
0.254 TYP
0.163 0.173
0.054 0.058
0.091 0.097
0.Q18 TYP
0.687 0.693
0.648 0.652
0.497 0.503
0.620 REF
0.050 sse
0.010TYP
0.045TYP
45'TYP
0.035TYP
0.010TYP
.-
RC2424DP/DS
2400 bps Full-Duplex Modem Device Set
PACKAGE DIMENSIONS
K2
MILUMETERS
MIN. MAX.
41.10 41.61
17.02 1723
3.58
4.58
0.48
0.58
19.05BSC
23.50BSC
1.27 BSC
0.33
0.18
2.92
3.18
4.83
5.34
DIM.
MILUMETERS
MIN. MAX.
INCHES
MIN. MAX.
51.82 52.32
13.48 13.97
5.08
3.58
0.38
0.53
1.02
1.52
2.54 SSC
2.16
1.85
0.30
0.20
3.05
3.58
15.24 BSC
10'
0.51
1.02
2.040 2.080
0.530 0.550
0.140 0.200
0.015 0.021
0.040 0.080
0.100 BSC
0.085 0.085
0.008 0.012
0.120 0.140
0.600 SSC
10'
0.020 0.040
DIM.
A
B
C
0
El
E2
G
J
Kl
INCHES
MIN. MAX.
1.618
0.670
0.140
0.018
0.750
0.925
0.050
0.007
0.115
0.190
1.638
0.690
0.180
0.022
BSC
SSC
SSC
0.013
0.125
0.210
64.pln Plastic QUIP
A
B
C
0
F
G
H
J
K
L
M
N
4O.pln Plastic DIP
1-138
r
r
RC2324DPjDS
Integral Modems
'1'
Rockwell
RC2324DP/DS 2400 bps Full-Duplex
Modem Data Pump Device Set
INTRODUCTION
FEATURES
The Rockwell RC2324DPIDS is a 2400 bps, full-duplex,
OEM, data pump modem device set. The RC2324DP/DS
operates over the public switched telephone network
(PSTN), as well as on point-to-point leased lines.
• CMOS DSP and IA devices
The set consists of two CMOS VLSI components-a digital signal processor (DSP) device and an integrated
analog (IA) device. The DSP is available in a 64-pin quad
in-line package (QUIP) or a 68-pin plastic leaded chip carrier (PLCC) package. The IA device is available in a 40-pin
dual in-line package (DIP) or a 44-pin PLCC package.
The RC2324DP/DS modem meets the requirements
specified in CCITI V.22 bis, V.22 AlB, and V.21 , as well
as Be1l212A and Bell 103.
In addition, the SDLC/HDLC support eliminates the cost of
an external serial input/output (SIO) device in products incorporating error correction protocols.
• 2-wire full-duplex operation
• Compatible configurations:
-CCITI V.22 bis, V.22A/B
-CCITI V.21 and V.23
-BeIl212A and 103
• Receive dynamic range: -9 dBm to -43 dBm
• Maximum transmit level: 0.0 dBm ± 1.0 dB,
programmable in 1 dB steps
• Multi-modem detection support
-Programmable tone detect bandpass filters
-Zero-crossing detector
• V.22 bis fallback/fall-forward - 2400/1200 bps
• Serial data both synchronous and asynchronous
-Synchronous:
2400,1200,600 bps ±0.01% (PSK modulation)
Internal/external/slave clock selection
-Asynchronous:
7,8,9,10, or 11 bits per character
2400,1200,600 bps +1% (or 2.3%), -2.5%
(PSK modulation)
0-75,0-300,0-1200 bps (FSK modulation)
• Parallel data both synchronous and asynchronous
-Synchronous:
Normal sync: 8-bit data for transmit and receive
-SDLCIHDLC support:
Transmitter: Flag generation, 0 bit stuffing,
CCITI CRC generation
Receiver: Flag detection, 0 bit un-stUffing,
CCITI CRC checking
-Asynchronous:
5,6,7, or 8 data bits per character
Odd/even parity generation/checking
(or 9th data bit)
2400,1200,600 bps +1% or (2.3%), -2.5%
(PSK modulation)
75,300,1200 bps (FSK modulation)
Document No. 29200N53
Data Sheet
(preliminary)
1-139
Order No. MD61
January 1989
2400 bps Full-Duplex Modem Device Set
RC2324DP/DS
• Power requirements:
• Programmable ring detect
-Min and max frequency range
-:l:5Vdc:l:5%
-500 mW typical
• Programmable dialer
R2424/RC2424 COMPATIBILITY
-Make/break times for pulse dialling
-DTMF on time for touch-tone dialling
-Interdigit times for both pulse and tone dialling
-DTMF Level: 0.0 dBm :I: 1.0 dB (high tone level is
2.0 dB :I: 0.5 dB above low tone level)
A high performance modem engine, the RC2324DP/DS is
the functional and performance equivalent of Rockwell's
R2424DS modem with the following enhancements:
-2-device implementation in CMOS
-V.21 and V.23 interface
-AsynchronouS/synchronous parallel data transfer
over the microprocessor bus interfaCe
-Extended 2.3% overspeed in asynchronous,
DPSKlQAM modes
-SDLC/HDLC framing in parallel data mode
-Additional configuration and control capabilities
• Diagnostics
-Read/write RAM
-Serial eye pattern output
-EQM value in RAM
• Host bus interface memory for configuration, control,
and parallel data; compatible with either 8086 or 6502
microprocessor bus
• RS-232C (TTL compatible) interface for RTS control
and serial data
These options and enhancements, combined with a user
accessible, dual port interface memory (RAM) in the DSP,
offer maximum flexibility in customizing the
RC2324DP/DS to meet a wide variety of functional requirements.
• Adaptive and fixed compromise equalization
• Test Configurations:
-Local analog loopback
-Local digitalloopback
-Remote digitalloopback
The RC2324DP/DS is a plug-compatible replacement for
the RC2424DP/DS.
• Answer and originate handshake
The RC2324DP/DS device set, with the addition of a few
external filter components, interfaces easily to a data access arrangement (DAA). The RC2324DP/DS general interface is illustrated in Figure 1.
• Leased line operation
RC2324DP/DS DEVICE SET
INTEGRATED
ANALOG
(IA)
DIGITAL
SIGNAL
PROCESSOR
(DSP)
HOST
PROCESSOR
PARALLEL
BUS
INTERFACE
2
ANTIALIASING
FILTER
COMPONENTS
ANCILLARY
CIRCUIT
INTERFACE
2
Figure 1. RC2324DPIDS General Interfaces
1-140
TELEPHONE
LINE
INTERFACE
2400 bps Full-Duplex Modem Device Set
RC2324DP/DS
Guard tone on/off must be controlled by the host depending on the state of the handshake sequence, i.e., the host
should enable guard tone when DSR is turned on.
TECHNICAL SPECIFICATIONS
CONFIGURATIONS, SIGNALING RATES, AND DATA
RATES
DTMF Tones: When DiaVCall Progress configuration is
selected (CONF bits = 81) and the DTMF bit is set to a 1,
dual tone multi-frequency (DTMF) tones can be
generated. The specific DTMF tone generated is specified
by the host loading the Transmitter Data Buffer (TBUFFER) with the appropriate digit code shown in Table 2.
The selectable modem configurations, along with the corresponding signaling (baud) rates and data rates, are
listed in Table 1. The modem configuration is established
by the CONF bits.
Note: Bit names refer to control bits in DSP Interface
Memory which are set or reset by the host processor (see
Software Interface Section, Figure 7 and Table 11).
User Defined Tones: When Tone Generatorrrone Detector configuration is selected (CONF bits = 80), a userdefined single or dual tone can be generated. In this mode,
the transmitter immediately begins sending the frequencies specified in DSP RAM. The tones will remain on as
long as Tone Generatorrrone Detector configuration is
selected and the tone amplitudes are greater than zero.
Setting one of the two amplitudes to zero selects Single
tone frequency.
TONE GENERATION
Answer Tone: A CCITI (2100 ± 15 Hz) or Bell (2225 ±
10Hz) answer tone is generated depending on the
selected configuration.
Guard Tone: A guard tone of 1800 ± 20 Hz (GTS bit = 0)
or 550 ± 20 Hz (GTS bit = 1) can be generated (enabled
by the GTE bit). The level of transmitted power is 6 ± 1 dB
or 3 ± 1 dB below the level of the data power in the main
channel for the 1800 Hz or 550 Hz guard tone, respectively. The total power transmitted to the line is the same
whether or not a guard tone is enabled. When a guard tone
is generated, the main channel transmit path gain is
reduced by 0.97 dB or 1.76 dB for the 1800 Hz or 550 Hz
guard tone, respectively.
Note: Frequencies from 0 to 1675 Hz can be sent when
the ORG bit is set, or frequencies from 1925 Hz to 2875
Hz can be sent when the ORG bit is cleared. 1800 Hz frequency can be sent by setting the GTE bit with GTS = 0
andORG =0.
Table 1. Configurations, Signaling Rates and Data Rates
Transmitter Carrier
Frequency (Hz) ±G.Ol %
Modulation1
Configuration
Ans_~
Orlginate2
Data Rate
(bps)
Baud
Bita Per
Constellation
±O.Ol%
(Symbolstsec.)
Symbol
Points
V.22 bls
QAM
2400
1200
24003
600
4
16
V.22A/B
DPSK
2400
2400
1200
1200
12003
6003
600
600
2
1
4
2
Be1l212A
DPSK
2400
1200
12003
600
2
4
Bell 103
FSK
2225M
2025S
1270M
1070S
300'
300'
1
1
V.21
FSK
1650M
1850S
980M
1180S
300'
300'
1
1
V.23 Forward Channel
FSK
1300M
2100S
1300M
2100S
1200'
1200'
1
1
V.23 Backward channell
FSK
390M
450S
390M
450S
75'
75'
1,
1
Notes:
1. Modulation legend: QAM
DPSK
FSK
2.
3.
Quadrature AmplRude Modulation
Differential Phase Shift Keying
Frequency Shift Keying
M Indicates a mark condRion; S indicates a space condRion.
Synchronous accuracy = ±0.01 %; asynchronous accuracy = -2.5% to +1.0% (+2.3% if extended overspeed is selected).
4. Value Is uppar IimR for serial (e.g., 0-300).
1-141
2400 bps Full-Duplex Modem Device Set
RC2324DP/DS
TONE DETECTION
Status Bit: TONEC
Answer Tone and Call Progress Tones: When DiaVCall
Progress configuration is selected (CONF bits = 81), tones
can be detected as follows:
Detection level: 0 dBm to -43 dBm
Default detection level: -43 dBm
Response time: 25
Call progress frequency range: 340 ± 5 Hz to 640 ± 5 Hz
Answertones (2100 ± 15 Hz or 2225 ± 10Hz) or Bell FSK
originate tone (1270 ± 10Hz)
Detection level:O dBm to -43 dBm
*Except the filter represented by TONEA in Dial/Call
Progress configuration, which is a dual biquad IIR filter.
Default detection level: -43 dBm
Response time: 25 ± 2 ms
Zero Crossing Detector: A zero crossing detector is always available. The detector can measure tone frequencies between 100 Hz and 3000 Hz. The zero crossing
counter increments for both positive and negative zero
crossings.
Status Bits: ATV25, ATBELL (ORG=1), BEL103
(ORG=O)
Tones are detected as energy above a certain threshold
within a digital bandpass filter. The pass band of the dual
bi-quad infinite impulse response (IIR) filter (Call
Progress) or the single bi-quad IIR filter (answer tone or
Bell FSK originate) can be changed by writing new coefficients to DSP RAM. The tone detect threshold can also be
changed in DSP RAM.
DATA ENCODING
The data encoding conforms to CCITT Recommendations
V.22 bis, V.22NB, V.23, or V.21 , or to Bell 212A or 103,
depending on the selected configuration.
V.23 and V.21 Tones: When Tone Generator/Tone
Detector configuration is selected (CONF bits = 80), tones
can be detected as follows:
EQUALIZERS
Equalization functions are incorporated that improve perfonnance when operating over low quality lines.
V.23 forward channel mark: 1300 ± 10 Hz
Automatic Adaptive Equalizer. A 17-tap automatic
adaptive equalizer is provided in the receiver circuit for
V.22 bis, V.22 and Be1l212A configurations. Updating of
the taps can be enabled or disabled (EQFZ). The equalizer
taps can also be reset (EQRES).
Status Bit: TONEA
V.23 backward channel mark: 390 ± 10 Hz
Status Bit: TONEB
V.21 high band mark (1650 ± 10 Hz) or low band mark
(980 ± 10 Hz)
Fixed Compromise Equalizer. A fixed compromise
equalizer is provided in the transmitter. The equalizer can
be enabled or disabled (CEQ bit).
Table 2. Dial Dlglts/Tone Pairs
00
01
02
03
04
05
06
07
08
09
OA
OS
Dial
Digit
0
1
2
3
4
5
6
7
8
9
*
00
Spare (8)
Spare (C)
Spare (0)
OE
OF
Spare (F)
OC
10
#
2 ms
Tones are detected as energy above the threshold within
a digital bandpass filter. These filters are single bi-quad IIR
filters*. The pass bands can be changed by writing new
coefficients to DSP RAM. The tone detect threshold can
also be changed in the DSP RAM.
Status Bit: TONEA
Hex
Code
±
TRANSMITTED DATA SPECTRUM
Tone Pair
(Hz)
(Hz)
941
697
697
697
770
770
770
852
852
852
941
697
770
852
941
941
After making allowance for the nominal specified compromise equalizer characteristic, the transmitted line signal has a frequency spectrum shaped by a square root of
a 75 percent raised cosine filter. Similarly, the group delay
of the transmitter output is within ± 150 microseconds over
1336
1209
1336
1477
1209
1336
1477
1209
1336
1477
1209
1633
1633
1633
1477
1633
Table 3. RTS - CTS Response Time
CTS Transition
OFF to ON
ONto OFF
Note:
1300 Hz Calling Tone
1-142
Configuration
V.22. bis
V.22.
Be11212A
V.21
Bell 103
V.23
All
Constant
Carrier
,;2 ms
,;2 ms
,;2 ms
2-5 ms
2-5ms
5-20 ms
52ms
Controlled
Carrier
270ms
270ms
270ms
2-5ms
2-5ms
5-20 ms
,;2 ms
The eTS OFF to ON response time is host programmable
in DSP RAM for some configurations.
RC2324DP/DS
2400 bps Full-Duplex Modem Device Set
the frequency range 900 Hz to 1500 Hz (low channel) and
2100 Hz to 2700 Hz (high channel).
RTS • CTS RESPONSE TIME
The response times of CTS relative to a corresponding
transition of RTS are listed in Table 3. The response time
depends on the receiver operating in either constant carrier or controlled carrier mode (CC bit).
TRANSMIT LEVEL
The default transmitter output level is -6.0 dBm ±1.0 dB.
The output level can be selected from 0 dBm to -15 dBm
in 1 dB steps (lLVL bits).
ASYNC/SYNC, SYNC/ASYNC CONVERSION
TRANSMIT TIMING
An asynchronous-to-synchronous converter is provided in
the transmitter, and a synchronous-to-asynchronous converter is provided in the receiver. Asynchronous or
synchronous mode is selected by the ASYNC bit. The
asynchronous character fonnat is 1 start bit, 5 to 8 data
bits (WDSZ bits), an optional parity bit (PARSL and PEN
bits), and 1 or 2 stop bits (STB bit). Valid character sizes,
including all bits, are 7,8,9,10 or 11 bits per character.
Transmitter timing is selectable between internal
(±0.01%), external, or loopback (TXCLK bits). When external clock is selected, the external clock rate must equal
the desired data rate ±0.01 % with a duty cycle of 50 ± 20%.
SCRAMBLE~DESCRAMBLER
A self-synchronizing scrambler/descrambler satisfying the
applicable CCITT recommendation or Bell specification is
incorporated. The scrambler and descrambler can be
enabled or disabled (SDIS and DDIS bits, respectively)
When the transmitter's converter is operating at the basic
signaling rate, no more than one stop bit will be deleted per
8 consecutive characters. When operating at the extended
rate, no more than one stop bit will be deleted per 4 consecutive characters.
RECEIVE LEVEL
The receiver satisfies performance requirements for
received line signals from -9 dBm to -43 dBm. The
received line signal is measured at the Receiver Analog
(RXA) input.
Two ranges of signaling rates are provided (selectable by
the EXOS bit):
Basic range: + 1% to -2.5%
Extended overspeed range: +2.3% to -2.5%
RECEIVER TIMING
Break is handled in the transmitter and receiver as
described in V.22 bis. If the RC2324DP/DS transmitter
detects M to 2M + 3 bits of "start" polarity from the DTE,
where M is the number of bits per character, the
RC2324DP/DS will transmit 2M + 3 bits of start polarity. If
the modem detects more then 2M +3 bits of start polarity,
it will transmit all these bits as start polarity.
A ± 0.01 % frequency error in the associated transmit
timing source can be tracked.
CARRIER RECOVERY
A ± 7 Hz frequency offset in the received carrier can be
tracked with less than a 0.2 dB degradation in bit error rate
(BER).
The RC2324DP/DS receiver will output the 2M + 3 or more
bits of start polarity on RXD and will set the BRKD bit.
CLAMPING
Received Data (RXD) is clamped to a constant mark
whenever the Received Line Signal Detector (RLSD) output is off.
1-143
2400 bps Full-Duplex Modem Device Set
RC2324DP/DS
PIN ASSIGNMENTS
The RC2324DP/DS pin assignments are shown in
Figure 2. The pin assigments are listed by pin number in
Tables 4 and 5 for the DSP and IA devices, respectively.
AGND
1.
MI1
MI8
N.C.
EYECLK
RDCLK
RBCLK
RXD
RLSD
TIDRe
64
63
62
61
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
RTS
N.c.
N.C.
N.C.
N.c.
N.C.
N.c.
DGND
D7
06
05
04
03
02
01
MI6
MI5
MI4
1.113
N.C.
MI2
TDCLK
TBCLK
TXD
60
21
22
23
DO
IRQ
WRiTE
cs
READ
RS4
RS3
RS2
+5VA
MI6
AGND
MI8
MI15
MI7
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
OGND
XTCLK
RD
MI2
MI7
+5V
N.C.
N.C.
N.C.
XTLO
XTLI
RESET
N.C.
EYESYNC
EYEX
EYEY
EN86
'S7
Ri
36
35
34
33
DSR
+5V
RSO
RSl
MI12
AGND
REC OUT
REC IN
DGND
CTS
64-PIN QU IP (DSP)
N.C.
MI14
BIAS
MI5
-5VA
AGND
RESET TC
MI1
+SVA
POR
TIDRC
MI2
MI3
N.C.
TRAN OUT
TLKRELAY
OHRELAY
N.C.
N.C.
8.
DGND
OGNO
AGND
-5VA
MI4
MIlO
MI13
MIll
AGND
40-PIN DIP (IA)
QUIP/DIP Set
o
co
~!!!!;~~'-!~t§;g=
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Z2::E::ECZZ+C::E:E
~~~~~"MN_m~~~"MN_
OfDIDUUOCCHDCC
•
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
RLSD
RXD
~
IIl!l<
Nle
Nle
NIC
NIC
p=
-=NOTE: UNLESS OTHERWtSE SPECIFIED
1. RESISTOR ViWJES ARE .. OHMS, t llM1. 1/flW
2. CAPAQTOR YAWES ARE IN 1IICfIOMRADS, i: . . ., 5OV'
3. ADJUST ¥AWE FOR CORRECT IIARKJBPACE BIAS.
DOH.
AGN.
==
18,
CD
13
C
~
n'
CD
en
!.
I
2400 bps Full-Duplex Modem Device Set
RC2324DP/DS
PC BOARD LAYOUT GUIDELINES
Table 15. Recommended Modem Interface Circuit
aty
1
1
1
1
1
8
1
1
1
2
1
1
1
1
1
1
1
1
2
1
1
Part Number
U1
U2
U4
US
Y1
C1, 04, ca, C7, 09,
C10,C13, C23
C2
C3
C5
C11, C12
R1
R2
R7
R9
R10
R11
R12
R13
R14, R16,
R15
CR1
The following guidelines should be adhered to when laying
out a printed circuit board for the RC2324DPIDS devices.
The pin numbers reflect the DSP 64-pin QUIP and the IA
40-pin DIP packages.
Description
Rockwell RC2424DPJDS DSP
RockwelIRC2424DPJDSIA
1458DualOp
SN74LS04 Hex Inverter
24.00014 MHz Crystal
0.10 !If, 20%,5OV
39 pF, 5%, 50V
18 pF, 5%, 50V
10 !If, 5%, 50V
1000 pF, 5%, 50V
34.8KO,1%,1/8W
66.5K 0, 1%, 1/8 W
1 0, 5%, 1/4 W
110KO,1%,1/BW
2.7M 0, 5%, 1/8 W
3K 0, 5%, 1/8 W
47K 0,5%, 1/8 W
23.7 K 0, 1%, 1/8 W
68.1KO,1%,1/8W
42.2KO,1%,1/8W
Schottky Diode, LL1O3B
1.
The DSP, IA and all supporting analog circuitry, including the data access arrangement should be
located on the sarne area of printed circuit board.
2.
The DSP device grounds should be routed
separately from the IA device.
3.
The DSP should be located on the pin 1 side of the
IAdevice.
4.
IA digital signals (pins 3, 4, 5, 8, 10, 12, 23, 28, 29,
and 31) should be routed directly to the DSP,
avoiding all analog components.
5.
Routing of the RC2324DP/DS signals should
provide maximum isolation between noise sources and noise senitive inputs. When layout requirements necessitate routing these signals
together, they should be separated by neutral
signals. The DSP and IA noise source, neutral,
and noise sensitive pins are listed in Table 16.
6.
A 1.00/10 jlF RC network is needed to decouple
the +5V supply. This must be done at the IA
device to isolate it from the DSP device.
7
As a general rule, digital signals should be routed
on the component side of the PCB while the
analog signals are routed on the solder side.
The sides may be reversed to match a particular
OEM requirement.
8.
All power traces should be at least a 0.1 inch width.
9.
The analog components should be located on the
pin 40 side of the 4O-pin IA device.
10. The IA AGND pins (1, 6, 21, 24, 32, and 38) and
the DGND pins (7 and 25) should be tied
together as ground directly under the device.
11. A 0.1 jlF ceramic capacitor is used to decouple
the -5V supply. This should be done in the immediate proximity of the IA device.
12. All circuitry connected to crystal pins 44 and 45 on
the OSP device should be kept short to prevent
stray capacitance from affecting the oscillator.
1-170
RC2324DP/DS
2400 bps Full-Duplex Modem Device Set
Table 16. RC2324DP/DS Pin Noise Characteristics
Device
DSP
64.f'inQUIP
DSP
68-Pin PLCC
IA
4O-Pin DIP
IA
44-Pin PLCC
Function
+5V
DGND
CrysteJ
Centrcl
Eye Pattern
Host Bus Interface
Seriellnterface
IA Interface
No Cennection
+5V
DGND
Crystal
Centrol
Eye Pattern
Host Bus Interface
Serial Interface
IA Interface
No Cennection
+5VA
-5VA
DGND
AGND
Centrol
Analog
DSP Interface
No Cennection
Noise Source
Neutral
44,45
9,38,43,52
39-40
18-34
8,10,36-37,55
4,41
5·7, 53, 56·58
1-2, 50-51 , 59, 61-64
3,11-16,35,42,46-48,60
35
1,15,19,40,51,54
30-31
24, 29, 38, 61
25-26
2-14,16-18,20,
22-23,41,60,62
27,56
39,42-44,57-59
36-37,45,47-50,52-53
21, 28, 32-34, 46, 55, 63-68
30,39
9,18
7,17,25
1, 6, 21, 24, 32, 38
10, 14-15
2, 19-20, 22, 26-27, 33-37
3-5, 8, 23, 28-29, 31
12
11,13,16,40
+5VA
-5VA
DGND
AGND
Centrol
Analog
DSP Interface
No Cennection
Noise Sensitive
49
17,54
33,43
11,20
9,19,27
2, 8, 23, 26, 35, 42
12,16-17
3, 21-22, 24, 29-30, 36-38,
40-41
4-5,7,10,25,31-32,34
1-171
14
1,6,13,15,18,28,39,44
•
2400 bps Full-Duplex Modem Device Set
RC2324DP/DS
Table 17. Modem Power Requirements
Voltage
+5VDC
-5VDC
Current (TypIcal)
@25°C
Tolerance
",5%
±5%
Current (Maximum)
@O°C
85mA
20mA
130mA
40mA
Note: Input voltage ripple ..1 volts peak-to-peak.
Table 18. Modem Environmental Specifications
Parameter
Temperature
Operating
Storage
Relative Humidity
Altttude
Specification
O°C to + 60°C (32°F to 140° F)
- 40°C to + 80°C (-40°F to 176"F) (Stored in heat sealed antistatic bag and shipping container)
Up to 90% noncondensing, or a wet bulb temperature up to 35°C, whichever is less.
- 200 feet to + 10,000 feet
Table 19. Crystal Specifications
Parameter
Value
O·Cto 60·C
-55·C to 85·C
24.00014 MHz
",0.0015% (",15 PPM)
",0.003% (",15 PPM)
Parallel resonant
7 pF max.
18 ",0.2 pF
2.5 mW max., Test at 20 nanowatts
0.0005% (5PPM)
Fundamental
25 ohms max.
Operating Temperature
Storage Temperature
Nominal Frequency @ 25·C
Frequency Tolerance @ 25·C
Temperature Stability @ TA = O·C to 60·C
Calibration Mode
Shunt Capacttance
Load Capacttance
Drive Level
Aging, per Year Max.
Oscillation Mode
Series Resistance
Max. Frequency Variation with 16.5 or 19.5 pF
Load Capacttance
Third Lead
Sleeving
+0.0035% (+35 PPM)
Required
Required
1-172
2400 bps Full-Duplex Modem Device Set
RC2324DPjDS
PACKAGE DIMENSIONS
DIM.
TOP VIEW
CHAM. J
K
SIDE VIEW
4.14
4.39
0.163
0.173
A1
1.37
1.47
0.054
0.058
A2
2.31
2.46
0.091
0.097
b
0.457TYP
25.02
25.27
24.00
24.26
0.985
0.945
0.995
01
02
20.19
23.24
20.45
2350
0.795
0.915
0.805
0.925
03
0.050 SSC
0.010TYP
1.15TYP
45°TYP
0.045 TYP
45°TYP
R
0.89TYP
R1
0254 TYP
0.035 TYP
0.010TYP
DIM.
MILUMETERS
MIN. MAX.
J
TYP. FOR EACH AXIS
(EXCEPT FOR BEVElED EDGE)
R
I
0.955
1.27 SSC
0254 TYP
a
EJECTOR MARKS
4 PlCS BOTTOM
ONLY [fYPJ
0.018 TYP
0
h
CHAM.
h X 45 DEG
3 PlCS
INCHES
MIN. MAX.
A
e
45 DEG.
MILLIMETERS
MIN. MAX.
t
SECTION A-A
BOTTOM VIEW
6S.pin PLCC
r
SEATING
~ '"''
A
4.14
4.39
0.163
A1
A2
1.37
1.47
0.054
0.058
2.31
2.46
0.091
0.097
b
TOP VIEW
SIDE VIEW
~i~~~
lf1tt1
CHAM.
h X 45 DEG
3 PLCS
EJECTOR MARKS
4 PLCS BOTTOM
ONLY ITYPJ
BOTTOM VIEW
I· --1-
TYP. FOR EACH AXIS
CEXCEPT FOR BEVElED EDGEl
I
R
SECTION A-A
44.pin PLCC
1-173
A2
t
INCHES
MIN. MAX.
0457 TYP
0.173
0018 TYP
0
17.45
17.60
0.687
0.693
01
16.46
16.56
0.648
0.652
02
12.62
12.78
0.497
0.503
03
15.75 REF
0.620 REF
e
1.27 SSC
0.254 TYP
0.050 SSC
0.045 TYP
a
1.15TYP
45°TYP
R
0.89TYP
0.035 TYP
R1
0254 TYP
0010 TYP
h
J
0.010TYP
45°TYP
RC2324DP/DS
2400 bps Full-Duplex Modem Device Set
PACKAGE DIMENSIONS
DIM.
MILUMETERS
MIN. MAX.
K2
41.10 41.61
17.02 17.23
3.56
4.58
0.56
0.48
19.05 SSC
23.50 BSC
1.27 BSC
0.33
0.18
2.92
3.18
4.83
5.34
DIM.
MILUMETERS
MIN. MAX.
A
B
C
D
El
E2
G
J
Kl
INCHES
MIN. MAX.
1.618
0.670
0.140
0.018
0.750
0.925
0.050
0.007
0.115
0.190
1.638
0.690
0.160
0.022
BSC
BSC
BSC
0.013
0.125
0.210
64-Pin Plastic QUIP
A
B
e
D
F
G
H
J
K
L
M
N
40-Pin Plastic DIP
1-174
51.82 52.32
13.46 13.97
3.56
5.06
0.53
0.38
1.02
1.52
2.54 Bse
1.65
2.16
0.20
0.30
3.05
3.56
15.24 Bse
7'
10'
0.51
1.02
INCHES
MIN. MAX.
2.040
0.530
0.140
0.Q15
2.060
0.550
0.200
0.021
0.060
Bse
0.085
0.012
0.040
0.100
0.065
0.006
0.120 0.140
0.600 BSe
10'
r
0.020 0.040
1-175
RC2324SME
'1'
RC2324SME System Module
Rockwell
INTRODUCTION
FEATURES
The Rockwell RC2324SME System Module is a smart
multi-mode modem on a single Eurocard module. The
hardware includes a 2400 bps full-duplex modem device
set, a microcomputer, ROM, RAM, a socket for an OEMsupplied parameter ROM, and peripheral I/O circuits. The
OEM adds a power supply, host and telephone line interfaces, indicators, switches and country dependent
parameters in a ROM to complete the modem. A back-up
battery and call progress audio monitor hardware can also
be added.
• Eurocard 2400 bps modem with integrated
microcontroller
• Enhanced AT command set
• Enhanced V.25 bis protocol for both synchronous and
asynchronous operation
Resident microcomputer firmware provides the basic
modem control including an enhanced AT command set,
V.25 bis, Call Progress, Blacklisting, and MNP protocol for
both class 4 and 5. In addition, a unique open architecture
with a convenient software structure allows for OEM customization of the product.
• OEM-supplied parameters in ROM for up to 16
countries
Call progress parameters
Blacklisting parameters
Alter AT result codes and messages
OAA configuration
Add/disable/rename AT commands
Alterable V.25 bis indicator messages
OEM configurable tone/pulse dialing parameters
• Automatic line mode/speed recognition of CCITT
modes
• Compatibilities
CCITT V.22 bis - 2400 bps
CCITT V.22A/B - 1200 and 600 bps
CCITT V.23 - 1200 bps/75 bps
CCITT V.21 - 300 bps
Bell 212A - 1200 bps
Bell 103 - 300 bps
• MNP error correcting protocol class 4 and data compression class 5
• OTE autobaud/autoparity in both AT and V.25 bis
• Synchronous and asynchronous OTE interface
• Speed buffering from 75 bps to 9600 bps
• Flow control: RTS/CTS or XON/XOFF with programmable XON/XOFF threshold and repeat margin
• Receiver dynamic range: -9 dBm to -43 dBm
• Clock selection: internal, external, or slave
• Asynchronous character format
7 or 8 data bits
1 or 2 stop bits
Odd, even, mark, space, or no parity
• Tone detection: 100 Hz -1000 Hz
•
•
•
•
•
RC2324SME Module
Document No. 29200N65
AUX OTE bus (RS-232-CN.24)
Voice data switching
Auto/manual call/answer with front panel dial support
Leased line mode
550 Hz and 1800 Hz guard tone
• 1300 Hz calling tone
Data Sheet
(Preliminary)
1-176
Order No. MD65
January 1989
System Module
RC2324SME
MODES OF OPERATION
SYSTEM OVERVIEW
HARDWARE
AT Mode
The RC2324SME card includes the following major components:
The RC2324SME AT command set is Hayes compatible.
Additional compatibility with the Dowty Quattro and
Microcom AT command set implementations, with emphasis on the European environment, is provided. The AT
command set and S-register values are listed in Table 1
and Table 2, respectively.
• R65012 Microcomputer
• 64K x 8 System ROM
• 12K x 8 OEM ROM Socket (27128 or 27256
compatible)
• 32Kx 8 RAM
V.25 bls Mode
RC2324SME supports DTE/DCE communication according to CCITT Recommendation V.25 bis. Commands are
received from the DTE (one command per input line) in
either synchronous or asynchronous formats. Each command may contain up to 60 characters of information. The
V.25 bis command set is summarized in Table 3.
• RC2324DPIDS Modem Device Set
• DAA Interface
The R65012 Microcomputer provides the modem control
processing and interfaces to the DTE. The RC2324DPIDS
Modem provides 2400 bps modem data pump functions.
The DAA interface provides signal lines for transmit and
receive data, two for telephone signal sensing, and four for
relay control. On-board ROM and RAM contain the resident firmware. Country specific parameters are userselectable and discussed in the firmware interface section.
Figure 1 shows the major system components of the
RC2324SME module.
Hayes Is a registered trademark rI Hayes Microcomputer Products, Inc.
Microcom Is a trademark of Mlcrocom.
Quattro Is a trademark cI Dowty Information Systems.
COUNTRY
~~~
l. . . . . . . . _.?==~
1,
PARAMETERS
OEM
SELECTABLE
OPTIONS
;:~:~~:...-
DAA
RC2324DP1DS
MODEM
DEVICE SET
---
R65012
MICROCONTROLLER
RESIDENT
FIRMWARE FOR
MODEM CONTROL
..........
Figure 1. RC2324SME System Interface Diagram
1-177
DTE
RC2324SME
System Module
Table 1. RC2324SME AT Command Set Summary
AT Command
AT
A
80
0
En
Fn
Hn
In
Ln
Mn
Nn
On
Pn
an
Sn
Tn
Vn
Xn
Yn
Zn
%An
%80
%Cn
%Dn
%En
%Kn?
%Mn
%Qn
%R
%Sn
&An
&Cn
&Dn
&Fn
&Gn
&In
&In
&Ln
&Mn
&On
&P
&R
&Sn
&Tn
&W
&Xn
&Z
\An
\80
\Cn
\Fn
\Gn
\Kn
\Ln
\Nn
\0
\Pn
\Qn
\S
\U
Wn
\Xn
\Y
\Z
/
Function
Attention Code
Answer Mode
BeIVCCITT Command
Dial Command
Echo Cemmand
Line Mode/Speed Preferenoe Select
On-Hook Cemmand
Product Code/Checksum Request
Speaker Volume Cemmand
Speaker On/Off Cemmand
Cemmand Slot Entry Execute
On-line Cemmand
Pulse Dial Cemmand
Quiet Cemmand
S-Register Read/Wr~e
Touch Tone Dial
Verbose Cemmand
Extended Result Cedes Enable/Disabie
Centrol Long Spaoe Disoonnect
Cenfiguration Reset command
Set Auto-Reliable Fallback Character
Print List of Blacklisted Numbars
Data Cempression (MNP5) Enable/Disable
Print List of Delayed Numbers
Auto-Retrain Enable/Disable
Auto Detect Select for MNP Link Request
Async Cemmands on Auxiliary Port; Sync DTE on Primary Port
XON/CTS ON Threshold Selection
S-Register Content Display
XOFF/CTS OFF Threshold Selection
Control Line Speed Detect
Data Carrier Detect Options
Data Terminal Ready Options
Fetch Factory Profile
Guard Tone Cemmand Set
DTE Speed Adjust
Telephone Jack Selection
Leased Line Operation
Synchronous Mode Selection
S-Register Input/Output Format
Dial Pulse Ratio
RTS/CTS Option
DSROption
Test Command Selection
Active Configuration Write
Clock Source Selection
Store Telephone Number
Maximum MNP Block Size Selection
Transmn Break-to-Remote
Auto-Detect Link Request/Fallback Select
Cemmand Directory Display
Modem-to-Modem Flow Control
Break Control
MNP Block Transfer Centrol
Operation Mode
Originate Reliable Link Manually
Cemmand Directory Store/Delete
DTE to SM3 Flow Centrol
Active Cenfiguration Display
Acoept Reliable Link Manually
MNP Result Message Enable/Disable
ON/XOFF Centrol Pass Through
Acoept Reliable Link Manually
Normal Mode Select
Execute Last Command Line
1-178
System Module
RC2324SME
Table 2. RC2324SME V.2S bls Mode Command Set Summary
V.25 bls Mode Commsnd
V.25 bls Commands
CIC
CRI
CRN
CRS
DIC
PRI
PRN
RLD
RLF
RLI
RLN
Function
Connect Incoming Call
Call Request with Number and Identification
Call Request with Number
Call Request with Stored Number
Disregard Incoming Call
StoreJDelete (Program) Identification Number
StoreJDelete (Program) Number
Request List of Delayed Numbere
Request List of Forbidden Numbere
Request List of Identification Numbers
Request List of Stored Numbers
Additional Commands
ARB*
ART
CBT"
CLP
CNA
CSP"
DLN
ECH*
ERM*
FBC*
FLO"
MBS·
OFT"
ONT"
OST
RES
SDC*
SIT"
SLF*
80M·
SPC
SPD
SPV
SRF·
STD
SRF·
STD
• Asynchronous mode only
Auto-Detect of Link RequestIFailback
Auto-Retrain Enable/Disable
MNP Block Transfer Control
Change Line Protocol
Change Number of Incoming Rings
Change DTE Speed
Dial Last Number
Echo Control
EnableiDisable Reliable Meseages
Specify MNP Auto-Fallback Charaeler
Pass Through XON/XOFF Control
Seleel Maximum MNP Block Size
Seleel XOFF (or CTS OFF) Threshold
Seleel XON (or CTS ON) Threshold
Display On-Une Stetus
Reset System
Seleel Data Compression
Set Inactivity Timer
Seleel Locsl Flow Control
Operation Mode Conlrol
Speaker Control
Set Pulse Dialing
Speaker Volume
Select Remote Flow Conlrol
Set Tone Dialing
Modem to Modem Flow Conlrol
Set DTMF Dialing
HARDWARE INTERFACE
AUXILIARY DTE BUS
The hardware interface consists of the external signals
shown in Figure 2.
Under program control, the Auxiliary DTE bus may duplicate the asynchronous functions of the Main DTE bus (except for clock and diagnostic signals).
MAIN DTEBUS
SWITCH INPUTS
The Main DTE bus provides the Signal lines described in
specifications RS-232C and V.24. The bus transmits data
and commands from the host (DTE) to the RC2324SME
module (DCE) and receives data and responses from the
DCE. The signal levels are TIL compatible. The bus also
provides the clock inputs and outputs for synChronous
DTEs and three signals for diagnostic testing per cCln
Recommendation V.54. The Main DTE bus is selected at
power-up.
Fifteen switch inputs are sampled. The four front panel
switch inputs are read continuously. The eleven internal
switch inputs are read only at power-up or reset.
Front Panel Switch Inputs
Talk/Data (TALK/DATA). The TALK/DATA switch input
selects data mode or talk mode. In addition, the SELECT
switch input selects a phone number to be dialed (V.25 bis
mode) or a command string (AT mode) to be performed
upon subsequent transitions of TALK to DATA when
SELECT is on.
1-179
RC2324SME
System Module
TID
TXO
AA"'()RGlANS
RXD
SELECT
TXCLl(
NTST
RXCLK
CLKSEL
FRONT PANEU
INTERNAL SWITCHES
EXTCLK
ASYNCISYNC
RTS
Ml-M4
CTS
DTRIOV
DSR
DSRIOV
ALSO
N/s
MAIN
DTE
BUS
DTR
V.251AT
AI
SNiLL
CDSL
DRS
RL
AAIND
TSTIND
LL
ARQIND
TSTEIA(CI42
TOIND
MIIND
INDICATORS
M21ND
ATXD
RC2324S11E
SYSTEM MODULE
ARXD
ACTS
LSIIND
LS21ND
ADSR
SELIND
ARLSO
AUX
DTE
BUS
ADTR
PDORIVE
ARTS
OPTO
ARI
LCS
ADRS
OHORIVE
-}
RDRIVE3
DAA
RDRIVE4
RJWEXT
TXA
RSEXT
RXA
EXTERNAL
BUS
EDO-ED7
DAAGND
UNEI
BATTERY-C
INPUT
EPG
SIGNALS
UNE2
BAT +
{-
+12 VDC
EYEX
-12 VDC
EYECLK
+5VDC
EYESYNC
~{
INTERFACE SIGNALS
] - - CALL PROGRESS
MONITOR
VOWME CONTROLS
DGNO
AGND
POR
DqNO
SPARE
:,AGNO
SPARE
Figure 2. RC2324SME Hardware Interface Signals
1-180
POWER
INPUTS
System Module
RC2324SME
Auto Answer (AA)/Orlglnate/Answer (ORG/ANS). The
AA-ORG/ANS switch input can be used to set or reset auto
answer (AA) mode from the front panel. The TAL!qDATA
switch input can cause the firmware to pursue a handshake in originate mode or cause the firmware to handshake in answer mode.
Auto Answer (AA)
The AA output indicates when the auto answer mode is
selected.
Test (TSTIND)
The TSTIND output indicates when a self test or Select 1
condition occurs. Select 1 shows that the user has chosen
the first of the 4 pre-stored directory numbers selectable
from the front panel.
Select (SELECT). The SELECT switch input acts like a
terminal shift key by changing the meaning of the
TAL!qDATA and AA-ORG/ANS switches.
Normal/Test (NTST). The NTST switch input selects
either normal mode of operation or test mode.
ARQ (ARQ). The ARQ output indicates when the ARQ or
the Select 2 condition occurs and when not in error correction mode. Select 2 shows that the user has chosen the
second of the four pre-stored directory numbers selectable
from the front panel.
Internal Switch Inputs
Clock Select (CLKSEL). The CLKSEL switch input determines whether the transmit clock is applied to the main
DTE Bus EXTCLK pin at the operating data rate for
synchronous operation or whether the data is
synchronized to an internal dock. In both cases, the clock
is presented to the main DTE bus TXCLK pin. This switch
input is used in conjunction with the Clock NormaVSlave
(NIS) switch.
Talk/Data Indicator (TDIND). The TDIND output indicates
when the modem goes into data mode or a Select 3 condition occurs. Select 3 shows that the user has chosen the
third of the 4 pre-stored directory numbers selectable from
the front panel.
Mode 1 (MODE1) and Mode 2 (MODE2). The MODE1
and MODE2 outputs indicate the connection protocol.
These indicator lines also show that the user has chosen
the fourth of the four pre-stored directory numbers selectable from the front panel.
Async/Sync Select SwItch. The Async/Sync Select
switch input selects asynchronous mode or synchronous
mode 3 of operation.
Mode 1, 2, 3 and 4 (M1, M2, M3, M4). The firmware reads
M1, M2 M3 and M4 switch inputs during initialization and
uses the values as defaults to set the RC2324SME
modem to recognize one or more specific modem-tomodem connection protocols and speeds.
Une Speed 1 (LS1) and Line Speed 2 (LS2). The LS1
and LS2 outputs indicate the connected speed.
Select (SEUND) Indicator. The SEUND output indicates
when the SELECT switch in on. This allows for the visual
ability to determine the current (selected or unselected)
meanings of multiple defined indicators.
DTR Override (DTRlOV). The DTR/OV switch input forces DTR ON or allows the DTE to control the state of DTR.
DTR/OV affects DTR operation on the Main DTE bus.
DAAINTERFACE
DSR OverrIde (DSRlOV). The DSR/OV switch input forces the DSR and RLSD outputs ON for both the main and
auxiliary DTE buses or it allows these Signals to act in a
normal manner.
The DAA interface provides the Signal lines for transmit
and receive data. Two lines are used for telephone signal
sensing and four for relay control.
CALL PROGRESS VOLUME CONTROLS
Clock NormaVSlave (N/S). The NIS switch input is used
in conjunction with the CLKSEL switch input.
Two output lines control the volume of a call progress
audio monitor.
V.2S biB/AT Mode Select (V251AT). The V25/AT switch
BATTERY CONNECTIONS
input selects either the AT command set or the V.25 bis
mode. This input is read by the controller firmware during
initialization and indicates which DTE command set to use.
A battery connection supplies standby power to the
RC2324SME module RAM in order to retain directory and
configuration data during power-down and intermittent
power losses. The battery must have a voltage range of
+2.3 Vdc to +5.5 Vdc. The maximum current consumption
is 51 fAA.
Switched Network/Leased Une Select (SN/LL). The
SN/ll switch input selects either switched network operation or leased line operation.
INDICATOR INTERFACE
Nine lines drive front panel indicators. Four lines are associated with momentary front panel switches to indicate
their state.
1-181
System Module
RC2324SME
OEM-supplied ROM. Jumpers on the RC2324SME card
allow selection of one of 16 sets of country dependent
parameters upon power-up reset.
COUNTRY CODE JUMPERS
Four country code jumpers select the country code. Each
jumper combination selects a set of OEM-supplied country
dependent parameters. The RC2324SME module can be
customized for up to 16 countries with no other on-board
changes.
The OEM parameters are linked to the operating system
through a set of pointers - one set for each of up to 16
countries. The pointers are:
Default AT Command String for AT Command Mode.
This pointer locates a string of AT style commands which
the OEM can preset before modem operation in the AT
command mode.
OEM ROM SOCKET
A 28-pin IC socket is provided for installation of an OEM
supplied EPROM/ROM device that occupies 12K bytes of
the RC2324SME address map. The interface is compatible with a 27C128/27C256 EPROM with an access
time of 150 ns or less.
Default Command String for V.25 bls mode. This
pointer locates a string of commands which the 0FM can
preset before modem operation in the V.25 bis mode.
MICROCOMPUTER FIRMWARE
Call Progress, Blacklisting and Dial Parameters. This
pointer locates a block of country dependent parameters
supporting dialing, call progress and blacklist operation.
Table 3 identifies the parameters that can be included.
The microcomputer firmware provides the following major
functions:
•
•
•
•
•
•
Operating system
Modem device set control and monitoring
OTE interface control and monitoring
AT command set processing
V.25 bis command set processing
OEM parameter interface
AT Mode Result Messages. This pointer locates a list of
OEM-modified AT mode messages. The default result
messages are listed in Table 4.
V.25 bis Mode Indications. This pointer locates a list of
OEM-modified V.2S bis mode indications. Table 4 lists the
default V.25 bis indications.
OEM PARAMETER INTERFACE
OEM Modified AT Commands. This pointer locates a list
of OEM modified AT commands.
The firmware provides a well-defined mechanism for the
installation and incorporation of OEM-supplied predefined OEM configuration parameters on a country basis
for up to 16 countries. The parameters are included in an
1-182
RC2324SME
System Module
Table 3. Country Dependent Parameters
Table 3. Country Dependent Para!11eters (Cont'cI)
No. Bytes
Parameters
1
Country Code
3
International Access Dial Code
1
Blacklist Size
20 Define Tone-A Fitter
20 Define Alternate Tone-A Fitter
2
Progress Tone Fitter Threshold
2
Connect Threshold Level
2
Leased Line Threshold Level
1
Transmit Level Attenuation Select
1
DTMF Tones Transmit Level
1
Leased Line Transmit Level
2
Receive Threshold for Dial Tone
2
Reserved
1
Maximum Time to Wait for Dial Tone
1
Minimum Time for Which Dial Tone Is Present
1
Maximum Allowable Time Dial Tone Loss
2
On Time for Primary Tone Cadence
Off Time for Primary Tone Cadence
2
12 Cadence Ring Parameters
12 Cadence Busy Parameters
12 Cadence Congestion Parameters
12 Cadence Unobtalnable Parameters
12 Cadence Progress Tone Parameters
5
Cadence Repetition Counts
1
Difference Maximum Time to No Ring Wait Time
1
Maximum Time to Wait for Connect
Pulse Make Time
1
Pulse Break Time
1
Pulse Dial Setup Time
1
1
Pulse Dial Clear Time
Pulse Diallnterdigit Time
1
1
Dial Pulse Code
1
Relay Control for On-Hook/Off-Hook Action
1
Relay Control for Make/Break Action
1
Relay Control for SeVClear Action
2
DTMF Tone On Time
2
DTMF Tone Interdigit Time
8
Blacklist Action Items
1
Reserved
2
Minimum Time to Delay Beween Calls
8
Blacklist Delay Parameters
6
Reserved
2
Blacklist Final Delay Time
1
Number of Times Blacklist Delay 1 is Used
1
Maximum Number of Tries to Fail
1
Maximum Number of Tries per Blacklist Period
1
Maximum Time Allowed Off-Hook
1
Option Flags Byte 1
Bit 0 Disable All Blacklisting
Bit 1 Cause Modem To Stop Originate When
Blacklist is Full
Bit 2 Disable the Operator Clearing Of Blacklist
Bit 3 Enable Blind Dialing On No Dial Tone
Bit 4 Enable Check For Busy While Dialing
Bit 5 Enable the Calling Tone
Bit 6 Disable the Return to Command ";"
Bit 7 Enable Atternate Dial Tone Fitter
No. Bytes
Parameters
1
Option Flags Byte 2
Bit 0 Enable the 1800 Hz Guard Tone
Bit 1 Enable the 550 Hz Guard Tone
Bit 2 Enable Line Current Sense Processing
Bit 3 Enable 'R' ATD modifier
Bit 4 Enable Adaptive Dialing Features
Bit 5 Enable Atternate Gain Relay
Bit 6 Enable Pulse Grounding Relay
Bit 7 Disable Monitoring for V.21 and V.23 'No
Answer Tone' Modems
Permanently Blacklisted Numbers (variable length)
Table 4. Result Codes, Messages, and Indications
AT
Code
00
01
02
03
04
05
06
07
08
09
10
12
13
14
15
16
17
18
19
20
21
22
24
25
26
27
28
29
30
31
32
33
1-183
AT Command
Message
OK
CONNECT
RING
NO CARRIER
ERROR
CONNECT 1200
NO DIAL TONE
BUSY
NO ANSWER
CONNECT 600
CONNECT 2400
RDlGRANTED
RDlDENIED
TRYING TO CONNECT
ABORT
INACTIVITY TIMEOUT
CIRCUIT BUSY
TERMINAL NOT READY
REDIAUNG
REUABLE
NOTREUABLE
N/A
DELAYEDn
V.23 CONNECT75TX/12OORX
V.23 CONNECT 12OOTX/75RX
CONNECT 75
CONNECT 110
CONNECT 150
CONNECT 4800
CONNECT 9600
BLACKUSTED
REUABLE COMPRESSED
V.25 bis Command
Indication
VAL
CNX 300
INC
CFINC
INV
CNX t200
CFIDT
CFIET
CFIRT
CNX 600
CNX 2400
RDlGRANTED
RDlDENIED
N/A
CFIAB
ITO
CFINS
CFICB
N/A
REUABLE
NOTREUABLE
EOl
DlC
CNX 75TX/12OORX
CNX 1200TX/75RX
N/A
N/A
N/A
N/A
N/A
CFIFC
REUABLE COMPRESSED
System Module
RC2324SME
GENERAL SPECIFICAtioNS
Modem Power Requirements
CUrrent (Typ.)
Voltllgr
+ S vee + S%, 4.S%
+ 12VDC",5%
-12VOC",S%
@25·e
320mA
CUrrent (MIIX.)
@O·C
4mA
535mA
SmA
43mA
SOmA
* Input voltage ripple .. 0.1 valta peak-to-peak.
Modem Mechanical Dimensions
P....m...r
Board Structure
$pacification
Single PC board with three rows 01 32
vertical pin positions, compatible with a
96111n DIN receptacle. Each row haa 31
plnslnalalled, with pins 31 a, 31 b, and
31 c removed for keying.
Dimensions
WIdth
Length
Component Height
Top (max.)
BotIDm (max.)
Weight (max.)
Pin Length (max.)
3.937 In. (100 mm)
6.378 In. (162 111m)
0.360 in. (9 mm)
0.130 In. (3.3 mm)
Soz. (140g)
0.31Sln. (8 mm)
Modem Envlronmental Specifications
Parameter
Temperature
OperatIng
Stonlge
Relative Humidity
Allilude
Speclflcetlon
O· C to + 60" C (32· F to 1400 F)
- 400 C to + 60" C (-40. F to 176· F)
(Stonld in heat ..aled antistatic bag
and shipping container.)
Up to 90% noncondenalng, or a wet bulb
temperature up 10 3S· C, whichever Is leas.
- 200 feat to + 10,000 feat
1-184
RC2324SME
System Module
DIMENSIONS
I
3.937
(100)
11
700
~
(94)
r
!
0.125 t 0.003
(3.18)
DIA(4PL)
I
...
...
...
I::
...
II:
II:
ili..- 0.025 so.
il5
m
-1 m.....
~,~_:...=====-=-==0=.1=19=~==~i~i5
(3.02)
(0.64)
~~
:1:
_
-~
t---l.I.1
1.
10
5.775 _ _
._
(146.7)
6.378 _ _ _ _ _ _-rj_.
f - - - - - - - - (162)
0.400
[~--n--n----£-:::-~
rl~
LO.062
-
--
(1.6)
UNITS: INCHES
MM
tJ
I
~~
j
(3.3) (3.18)
(8.1)
1-185
RC2324SMEIDS
'1'
Rockwell
RC2324SMEIDS
Multi-Mode Modem Device Set
INTRODUCTION
FEATURES
The Rockwell RC2324SMEJDS Is a smart multi-mode
modem device set. The device set consist of four components - a microcontroller, a digital signal processor
(DSP) device, an integrated analog QA) device, and a
ASIC gate arrBlf. The DSP, microcontroller, and ASIC gate
&rr8If are available in a 64-pin quad in-line package (QUIP)
or a 68-pin plastic leaded chip carrier (PLCC) package.
The IA device Is available in a 4O-pin dual in-line package
(DIP) or a 44-pin PLCC.package.
• Enhanced AT command set
• Enhanced V.25 bis protocol for both synchronous and
asynchronous operation
• OEM-suppiied parameters in ROM for up to 16
countries
Call progress parameters
Blacklisting parameters
Alter AT result codes and messages
OAA configuration
Add/disable/rename AT commands
Alterable V.25 bis indicator messages
OEM confIgurable tone/pulse dialing parameters
• Automatic line mode/speed recognition of CCITT
modes
• Compatibilities
CCITT V.22 bis - 2400 bps
CCITT V.22A/B - 1200 and 600 bps
CCITT V.23 - 1200 bps/75 bps
CCITT V.21 - 300 bps
Bell 212A - 1200 bps
Bell 103 - 300 bps
• MNP error correcting protocol class 4 and data compression class 5
• OTE autobaud/autoparity in both AT and V.25 bls
• Synchronous and asynchronous OTE interface
• Speed buffering from 75 bps to 9600 bps
• Flow control: RTSICTS or XON/XOFF with programmable XON/XOFF threshold and repeat margin
• Receiver dynamic range: 0 dBm to -43 dBm
• Clock selection: internal, external, or slave
• Asynchronous character format
7 or 8 data bits
1 or 2 stop bits
Odd, even, mark, space, or no parity
Resident microcomputer firmware provides the basic
modern control including an enhanced AT command set,
V.25 bls, Call Progress, Blacklisting, and MNP protocol for
both class 4 and 5. In addition, a unique open architecture
with a convenient software structure allows for OEM CUBtomization of the product.
Document No. 29800N47
Product Preview
1-186
Order No. 847
January 1889
R96QT
Integral Modems
'1'
Rockwell
R96QTTM
9600 bps QuickTurn ™ Modem
INTRODUCTION
FEATURES
The R96QT is a high-performance 2-wire 9600 bps quickturn modem designed for operation over the public
switched (PSTN). Using state-of-the-art VLSI and signal
processing technology, the R96QT combines half-duplex,
fast tum around time with a low and medium speed full.
duplex application in one package.
•
Compatibility
CCID V.29 (half-duplex), V.27 ter (half-duplex),
V.22 bis, V.22A/B
Bell 212A, 103
•
Synchronous operation
9600,7200,4800,2400,1200,600,
or 300 bps %0.01 %
Serial or parallel
Providing proprietary fast training times of 23 ms, the
R96QT is designed as an asynchronouS/synchronous
OEM data pump ideal for PC XT/AT and PS/2 applications.
The integrated features available in the R96QT
Micromodem TN • offer increased user design flexibility in a
reduced package size (3.94 in. x 2.56 in.).
•
Asynchronous operation
-
2400,1200,600, or 0-300 bps
Serial or parallel
Character length 8, 9, 10, or 11 bits
•
2-wire full-duplex or high speed psuedo full-duplex
•
Adaptive and fixed compromise equalization
•
Auto/manual dial - DTMF or pulse dial
•
Programmable tone generation and detection
•
Call progress tone detection
•
Receiver dynamic range: - 10 dBm to - 43 dBm
•
Programmable transmit level
•
Proprietary fast train of 23 ms
•
DTE interface
-
Microprocessor bus
CCITT V.24 (RS-232-C compatible)
•
Built-in diagnostiC capability
•
Full-duplex test configurations for V.22 bis, V.22A/B,
and Be1l212A
-
Local analog loopback
Local digitalloopback
Remote digital loopback
•
Power consumption: 3 W (typical)
•
Small module with dual in-line pin (DIP) connector:
-
100 mm x 64.7 mm (3.94 in. x 2.56 in.)
QT. QuickTurn, and Micromodem are trademarks of Rockwell International
R96QTModem
Document No. 29200N46
Data Sheet
(Preliminary)
1-187
Order No. MD46
Rev. 2, January 1989
R96QT
9600 bps QuickTurn Modem
Table 2. Signaling Frequencies
TECHNICA\. SPECIFICATIONS
CONFIGURA1\IONS, SIGNAUNG RATES, AND DATA
RATES
The selectable modem configurations along with the corresponding sigl\laling (baud) rates and data rates, are
listed in Table 1. Additional signaling frequencies are listed
in Table 2. The receiver and transmitter configurations are
established by th. RCONF and TCONF bits, respectively.
NOTE: Bit name$ refer to control bits in DSP interface
memory which are set or reset by the host processor (see
Software Interface Section, Figure 4, cand Table 12).
Frequency :to.01%
(HZl
Mode
C
\1'.22 bls Low Channel, Originate Modi)
V.22 Low Channel, Originate Mode
V.22 bis High Channel, Answer Mode
V.22 High Channel, Answer Mode
Bell 212A High Channel Answer Mode
Be1l212A Low Channel Originate Mode
Bell 103/113 Originating Mark
Bell 103/113 Originating Space,
Bell 103/113 Answer Mark
Bell 103/113 Answer Space
1200
1200
2400
2400
2400
1200
1270
1070
2225
2025
TONE GENERATION
Single Tone: Under control of the host processor, the
modem can generate voice band tones up to 4800 Hz with
a resolution of 0.15 Hz and an accuracy of 0.Q1 'lb. Tones
over 3000 Hz are attenuated.
into the transmitter Dial Digit Register (DDR) with the appropriate digit code shown in Table 3.
TONE DETECTION
Single Tone: In the 300 bps synchronous FSK receive
configuration, the presence of tones at preset frequencies
is indicated by bits in the DSP interface memory (FR1,
FR2, and FR3).
Call Progress Tone: When call progress configuration is
selected in the receiver, tones can be detected as follows:
Answer Tone: A cCln (2100 %15 Hz) or Bell (2225 %10
Hz) answer tone is generated depending on the selected
configuration.
Guard Tone: An 1800 Hz % 20 Hz guard tone can be
enabled (GTE bit). The power level of the transmitted
guard tone is 6 %1 dB below the level of the data power in
the main channel. The total power transmitted to the line
is the same whether or not the guard tone is enabled.
Frequency Range: 340 %5 Hz to 640 %5 Hz
Detection Level: -10 dBm to -43 dBm
Response Time: 17 %2 ms
DTMF Tones: Dual tone multi-frequency (DTMF) tones
can be generated in the Call Request mode (TCONF = 80)
when the DTMF bit is set to one. The DTMF tone
generated is specified by the hexadecimal code loaded
Table 1. Configurations, Signaling Rates and Data Rates
V.29 FT/9600
V.29 9600
V.29 FT/72OO
V.29 7200
V.29 FT/4600
V.294800
CAM
CAM
CAM
CAM
CAM
CAM
Carrier
Frequency
(Hz)
'" 0.01%
1700,1800·
1700
1700,1e002
1700
1700,18002
1700
V.27 FT/4800
V.27 4800 long
V.27 FT12400
V.27 2400 long
OPSK
OPSK
OPSK
OPSK
1800
1800
1800
1800
4800
4800
2400
2400
Sync
Sync
Sync
Sync
CAM
CAM
OQPSK
OQPSK
1200{24OO
1200{24OO
1200{24O0
12OO{24OO
2400
1200
1200
600
SynclAsync
SynclAsync
SynclAsync
SynclAsync
CAM
FSK
1200{24OO
1170{2125
1200
0-300
SynclAsync
Async
Configuration
V.22 bis 2400
V.22 bis 1200
V.221200
V.22800
Be1l212A 1200
Bell 103 0-300
Nolee:
Modulation 1
Data
Rate
(bps)
'" 0.01%
9600
9600
7200
7200
4800
4800
Baud
(Symbols!
Sec.)
Blta
per
Symbol
Sync
Sync
Sync
Sync
Sync
Sync
2400
2400
2400
2400
2400
2400
4
4
3
3
2
2
16
16
8
8
4
1800
1600
1200
1200
3
3
2
2
8
8
4
4
600
4
2
2
1
16
4
4
2
2
1
-
Sync/Async
1. Modulation legend:
800
600
600
600
300
Constellallon
Point.
CAM Quadrature Amplitude Modulation
OQPSK Differential Quadrature Phase Shift Keying
FSK Frequency Shll.t Keying
2. V.29 FT modes have an optional 1800 Hz carrier frequency available for use with a user-provided secondery channel.
1-188
4
R96QT
9600 bps QuickTurn Modem
Table 3. Dial DIglts/Tone Pairs
Hex
Code
00
01
02
03
04
05
06
07
08
09
OA
08
OC
OD
OE
OF
10
Dial
D!git
TRANSMITTED DATA SPECTRUM
When the compromise equalizer is disabled, the transmitter spectrum is shaped by the following raised cosine filter
functions:
Tone Pairs (Hz)
0
1
2
3
4
5
6
7
8
9
941
1336
697
1209
697
1336
697
1477
770
1209
770
1336
770
1477
852
1209
852
1336
852
1477
941
1209
*
Spare (8)
697
1633
Spare (C)
770
1633
Spare (D)
852
1633
#
941
1477
Spare (F)
941
1633
1300 Hz Calling Tone
V.22 bis: Square root of 75%.
V.29: Square root of 20%.
V.27 ter 1600 baud: Square root of 50%.
V.27 ter 1200 baud: Square root of 90%.
SCRAMBLER/DESCRAMBLER
A self-synchronizing scrambler/descrambler satisfying the
applicable CCITT recommendation or Bell interface is incorporated depending on the selected configuration. Both
the scrambler and the descrambler can be enabled or disabled (SOlS or DDIS bits, respectively).
TRANSMIT LEVEL
The transmitter output level is programmable with a default
value of -10 dBm ±1 dBm (measured at the TXA output
pin). Transmit output level is selectable in 2 dBm steps
from 0 dBm to -14 dBm (lLVL). The default amplitudes for
DTMF tones in the auto dial mode are -4 dBm and -6 dBm
for the high and low frequencies, respectively.
DATA ENCODING
The data encoding conforms to CCITT recommendations
V.29, V.27 ter, V.22 bis, and V.22 NB, and to Bell interfaces 212A and 103.
TRANSMIT TIMING
Transmitter timing in full-duplex modes is selectable between internal (±0.01%), external, or loopback (TXCLK).
An external clock must equal the desired data rate ±0.01 %
with a duty cycle of 50 ± 20%.
EQUALIZERS
Equalization functions are incorporated to improve performance when operating over low quality lines. Delay,
amplitude and cable equalizers support half-duplex operation only.
RECEIVE LEVEL
The receiver satisfies performance requirements for the
received line signals from -10 dBm to -43 dBm. The
received line signal is measured at the Receive Analog
(RXA) input.
Automatic Adaptive Equalizer
An automatic adaptive equalizer is provided in the receiver
circuit. The receiver is configured with a 32-tap T equalizer
for half-duplex (HDX) operation. Full-duplex (FOX) modes
operate with a 16-tap T/2 equalizer. Updating of the taps
can be enabled or disabled (FRZEQ).
RECEIVE TIMING
A frequency error up to ±0.01 % in the associated transmitting source can be tracked.
Delay Equalizer
CARRIER RECOVERY
A digital filter in the transmitter provides envelope delay
equalization for half-duplex operation. The equalizer can
be enabled or disabled (CDEQ).
A frequency offset up to ±7 Hz in the received carrier can
be tracked with less than a 0.2 dB degradation in bit error
rate (BER).
Amplitude Equalizer
CLAMPING
In V.29 modes, an amplitude compromise equalizer in the
transmitter path can be enabled or disabled (CAEQ bit).
Received Data (RXD) is clamped to a constant mark (one)
when the Received Line Signal Detector (RLSD) is off.
Link and Cable Equalizers
RECEIVER CARRIER FREQUENCY
Selectable compromise equalizers in the receiver optimize
performance over channels exhibiting severe amplitude
distortion. An equalizer may be selected (CEQSEL) that
meets the following standards: U.S. Survey Long,
Japanese 3-Link, Cable 1, Cable 2, and Cable 3. No
equalizer may also be selected. (HDX only)
The receiver demodulator carrier frequency is shown in
Table 1. In V.29FT modes, 1800 Hz or 1700 Hz may be
selected (RCF and TCF bits).
1-189
R96QT
9600 bps QuickTurn Modem
TURN-ONI TURN-OFF SEQUENCES
Table 4. High Speed RTS-CTS Response Times
V.29 and V.27 Turn-On Sequence
The selectable turn-on sequences are generated as
defined in the Table 4.
V.29 and V.27 Turn-Off Sequence
In V.29/FT, V.29, V.27/FT, and V.27 the turn-off sequence
consists of approximately 8 ms of remaining data and
scrambled ones.
V.22 and Bell 212A Turn-On!Turn-Off Sequences
RTS and CTS turn-on and 'turn-off sequences and times
for V.22 and Bell configurations are shown in Tables 5 and
6, respectively. Controlled or constant carrier operation
can be selected (CC bit).
Configuration
lifSJCTS Response Time (ms)
V.29 FT/9600
V.29 FTI7200
V.29 FT/4800
V.29 9600, 7200, or 4800
V.27 FT/4800
V.27 4800 long
V.27 FTI2400
V.27 2400 long
23
24
23
253
22
708
30
943
Note: V.29 RTS-CTS respbnse time Is 438 ms when
preceded by an echo protector.
Table 5. Medium Speed RTS Responses
ASYNC/SYNC, SYNC/ASYNC CONVERSION
An asynchronous-to-synchronous converter is provided in
the transmitter and'a synchronous-to-asynchronous converter is provided in the receiver. The asynchronous
character format is 1 start bit, 5 to 8 data bits (CHARO and
CHAR1), an optional parity bit (PARSLO, PARSL1, PENO,
and PEN1), and 1 or 2 stop bits (STBO and STB1). Valid
character size, including all bits is 8, 9, 10, or 11 bits.
RTS Transltlon*
ON to OFF
OFFtoON
When the transmitter's converter is operating at the basic
signaling rate, no more than one stop bit will be deleted per
8 consecutive characters. Break is handled in the transmitter and receiver as described in V.22 bis.
Constant
Carrier
CTS OFF,
carrier ON,
scrambled 1s
transmitted
CTSON,
carrier ON,
data transmitted
Controlled
Carrier
CTSOFF,
carrier OFF
carrier ON,
210 ms to 275 ms
scrambled 1s
transmitted,
data transmitted
• After handshake Is complete.
MODES OF OPERATION
The R96QT can operate synchronously or asynchronously, depending on the selected configuration.
Table 6. Medium Speed CTS Response Times
CONTROL MODES (FOX)
The modem can operate in serial or parallel control modes
(BUS bit) and in either serial or parallel data mode (RPDM
and TPDM bits).
CTS Transition
OFF to ON
ON to OFF
In the serial control mode, standard V.24 (RS-232 comatible) interface signals, along with the TI-K and ORG signals, control the transfer of data between the modem and
the host (V.22 bis only). The transmitter defaults to serial
control mode upon power turn-on.
Constant
Carrier
<2ms
<20ms
Controlled
Carrier
210t0275ms
20ms·
* Programmable
In the receiver serial data mode, received data is output
only to the RXD pin. In the receiver parallel data mode,
received data is output simultaneously to the Receive Data
Register (RXDATA) in interface memory and to the RXD
pin.
In the transmitter serial data mode, transmitted data is obtained from the TXD input pin. In the transmitter parallel
data mode, transmitted data is obtained from the Transmit
Data Register (TXDATA) in interface memory.
In the parallel control mode, bits in interface memory corresponding to the V.24 signals control the data transfer.
In either serial and parallel control mode, the modem is
configured by the host writing configuration/control bits to
the DSP interface memory via the microprocessor bus.
DATA MODES
In parallel asynchronous data mode, the R96QT operates
like a universal asynchronous receiver/transmitter (UARl)
except in BELL103 configuration. The length of the break
signal is determined by the BRKSO and BRKS1 bits for the
transmitter and receiver, respectively.
Serial or parallel data mode can be separately selected for
the transmitter and receiver (TPDM and RPDM bits,
respectively). In parallel data mode, channel data is transferred 8-bits at a time between the host and the modem
over the microprocessor bus.
1-190
9600 bps QuickTurn Modem
R96QT
POWER-ON-RESET
HARDWARE INTERFACE SIGNALS
When power is applied to the modem, the modem pulses
Power-On-Reset (POR) low to begin the POR sequence.
The modem is ready for use 350 ms after the low-to-high
transition of POR. The POR sequence is reinitiated any
time the +5V supply drops below +3.5V for more than 30
ms, or an external device drives POR low for at least 3 flS.
POR is not pulsed low by the modem when the POR sequence is initiated externally. The POR sequence initializes the modem interface memory (Table 12) to default
values. This action leaves the modem configured as follows:
The Functional Interconnect Diagram (Figure 1) shows the
typical modem connection in a system. In this diagram,
any point that is active low is represented by a small circle
at the signal point.
Edge triggered inputs are denoted by a small triangle (e.g.,
TOClK). Open-Collector (open-source or open-drain) outputs are denoted by a small half-circle (e.g., IRQ). Active
low signals are overscored (e.g., POR).
A clock intended to activate logic on its rising edge (Iowto-high transition) is called active low (e.g., ROClK), while
a clock intended to activate logic on its falling edge (highto-low transition) is called active high (e.g., TOClK). When
a clock input is associated with a small circle, the input activates on a falling edge. If no circle is shown, the input activates on a rising edge.
V.22 bis synchronous 2400 bps
Serial data mode
T/2 equalizer
-43 dBm receiver threshold
The functional interconnect signals shown in Figure 1 are
organized into seven functional groups: overhead,
microprocessor interface, V.24 interface, analog, line interface, ancillary and diagnostic. These signals, along with
their connector pin numbers and interface circuit types, are
listed in Table 7. The digital and analog interface characteristics are defined in Tables 8 and 9, respectively.
r-------,.
,-
I-
r
USRT
(OPTIONAL)
:
I
l.
~
---T'-
P'"
-
RTS
CTS
TXD
RDCLK
XTCLK
TDCLK
RXD
RLSD
DTR
DSR
RI
Constant carrier
Answer mode
-10 dBm transmit level
NOTE: If the modem is used in applications where the
supply voltage can drop below +4.75V but not low enough
to cause a POR sequence (i.e., <+3.5V), the host system
should generate a POR signal upon supply voltage
recovery to ensure proper modem initialization and operation.
I ~oP~:
EYEX
EYEY
EYESYNC
0
+12V
+5V
GND
READ
R960T
MODEM
DATA BUS (8)
RXA
OHRC
)
IRO
+5 J"yvv
POWER
SUPPLY
ANALOG
INTERFACE
CS(3),
POR
(
,I
-12V
TXA
REGISTER SELECT (4)
DECODER
ty
EYE
PATTERN
GENERATOR
EYECLK
WRITE
HOST
PROCESSOR
(DTE)
xt
J
RD
LINE
INTERFACE
TBCLK
RBCLK
ORG
TLK
Figure 1. R96QT Functional Interface Signals
1-191
ANCILLARY
CIRCUIT
INTERFACE
9600 bps QuickTurn Modem
R96QT
Table 7. R96QT Hardware Interface Signals
I/O
Nama
OVERHEAD
Type
DIP
Pin No.
Table 7. R96QT Hardware Interface Signals (Cont'd)
Description
GND(A)
GND(D)
AGND
DGND
+5V
PWR
~!;14, +5 Volt Supply
+12V
-12V
PWR
PWR
I BlOB
29
31
4
+12 Volt Supply
- 12 VoR supply
Power·On-Reset
IA/OA
INOA
IA/OA
INOA
INOA
INOA
INOA
INOA
IA
IA
IA
IA
IA
IA
IA
IA
IA
50
Data Bus Bit 7
Data Bus Bit 6
Data Bus Bit 5
Data Bus Bit 4
Data Bus Bit 3
Data Bus Bit 2
Data Bus Bit 1
Data Bus BHO
Regieter Select 3
Regieter Select 2
Regieter Select 1
Regleter Select 0
Chip Select Transmitter
Chip Select Receiver 1
Chip Select Receiver 2
Read Enable
Write Enable
Intarrupt Request
27,28 Analog Ground Return
51
POR
PROCESSOR
07
OS
D5
D4
D3
D2
01
DO
RS3
RS2
RSI
RSO
CSO
os;CS2
READ
WRITE
IRQ
09
49
48
47
46
45
44
43
3
58
57
40
2
42
60
61
59
1
Description
IB
OC
OC
IB
OC
IB
OC
OC
IB
OC
OC
5
6
38
10
8
11
35
37
16
13
23
External Transmit Clock
TransmH Deta Clock
Receive Data Clock
Request-To-Send
Clear-To-Send
Transmit Data
Receive Data
Receiver Line Signal Detector
Data Terminal Ready
Data Set Ready
Ring Indicator
TXA
RXA
LINE
AA
AB
26
30
Transmit Analog Output
Receiver Analog Input
RD
OHRC
ANCILLARY
IB
OC
22
18
Ring Detect
Off-Hook Relay Control
OC
7
12
Transmit Baud Clock
Receive Baud Clock
Originate
Talk
XTCLK
TDCLK
RDCLK
RTS
CTS
TXD
RXD
RLSD
, DTR
32,36, OigHai Ground Return
DIP
Pin No.
I/O
Type
Nama
V.24
DSR
Ai
ANALOG
TBCLK
RBCLK
ORG
OC
IB
IC
M
17
19
DIAGNOSTIC
OC
OC
OA
OA
EYEX
EYEY
EYECLK
EYESYNC
52
56
54
53
Eye Pattern
Eye Pattern
Eye Pattern
Eye Pattern
Signal
Data X-Axis
Data Y-AxIs
Clock
Synchronizing
NOTES:
1. Digital and analog I/O types are described in Tables 8 and 9.
2. DIP connector pins 24, 25, 33, 34, 39 and 41 are not used. Leave
these pins disconnected (I. e., open).
3. Unused inputs tied to +5V or ground require Individual 10 Kg
series resistors.
Table 8. Digital Interface Characteristics
Symbol
Parameter
VIH
Input High VoHage
VIL
Input Low Voltage
Input Leakage Current
liN
CL
Output High Voltage
Output Low VoRage
Output High Current
Output Low Current
Output Leakage Current
Pull-Up Current
(Short Circuit)
Capacitive Load
Co
Capacitive Drive
VOH
VOL
IOH
101.
IL
lpu
Circuit Type
InDut/OutDut TVDe
IC'
OA
Units
IA
IB
V
V
2.0 min.
0.8 max.
2.5 max.
2.0 min.
0.8 max.
ItA
V
3.5 min.'
3.5 min.'
V
0.4 max. 2
-0.1 max.
1.6 max.
±10max.
-240 max.
-10min.
0.4 max. 3
-0.1 max.
0.8 max
±10max.
mA
mA
ItA
-240 max.
ItA
pF
5
-10min.
20
10
TTL
TTL
CLK
pF
w/pull-up
NOTES:
1. I Load
2. I Load
3. I Load
=-100 ItA
=1.6 rnA
=0.8 mA
OB
OC
OD'
Vee -Q.5 max.
0.5 max.
11 max.
1.6 max.
-0.001 max.
0.001 max.
100
100
100
50
TTL
TTL
TTL
CLK
3-state
3-slata
3-slata
4. Input waveform must be symmetric within 20%.
5. Loads on 12 MHz and 6 MHz outputs must be balanced within 20%.
1-192
0.4 max. 2
R96QT
9600 bps QulckTurn Modem
Table 9. Analog Signal Characteristics
Name
Type
TXA
AA
RXA
AB
During a write cycle, data from the data bus is copied into
the selected DSP interface memory register, with high and
low bus levels representing one and zero bit states,
respectively.
Characteristic
The transmitter output impedance Is
604 C :1:1 % wHh an output level of
0.488 VRMS. To obtain a -1 0 dBm
output, an external 600 C load to
ground is needed.
The read/write timing waveforms are Illustrated in Figure 2
and the timing requirements are specified in Table 10.
Interrupt Request (IRQ)
The modem Interrupt Request ~RQ) output may be connected to the host processor interrupt request input in
order to interrupt host....E!...ogram execution for immediate
modem service. The IRQ output can be enabled in the
DSP interface memory to indicate immediate change of
conditions in any of the three modem DSP devices. The
use of IRQ is optional depending upon modem application.
Refer to the Software Considerations Section for a summary of the modem interrupt bits, interrupt conditions and
interrupt clearing procedures.
The receiver input impedance is
21 K C :I: 1%. The receive level at RXA
must be no greater than -10 dBm.
MICROPROCESSOR INTERFACE
Eighteen address, data, control and interrupt hardware interface signals implement an 8085 compatible parallel
microprocessor interface to a host processor.
This parallel interface allows a host processor to change
modem configuration, read or write channel and diagnostic data, and supervise modem operation by writing control
bits and reading status bits. The Significance of the control
and status bits, along with the methods of data interchange, are discussed in the Software lriterface Section.
The DSP IRQ output structure is an open-drain field-effecttransistor (FET). Each of the individual DSP IRQ output
lines is wire-ORed to form the composite modem IRQ output signal. The modem IRQ output can also be wire-ORed
with other I RQ lines in the application system. Any of these
sources can drive the host interrupt input low. The host in-
Data Lines (D(H)7)
Eight bidirectional data lines (D~7) provide parallel
transfer of data between the host and the modem. The
most significant bit is D7. Data direction is controlled by the
Read Enable (READ) and Write Enable (WRITE) signals.
READ
WRITE
Chip Select (CSO-CS2) and Register Selects
(RSO-RS3)
Three active low chip select lines (CSO-CS2) select one of
three modem digital signal processor (DSP) devices. The
four active high register select lines (RSO-RS3) address interface memory registers within the selected DSP interface memory: All seven of these lines are typically
connected to the host bus address lines; the register select
lines to the four least significant lines (AO-A3) and the chip
select lines to the next two significant lines (A4-AS)
through a decoder.
RSO-RS3
The selected DSP decodes RSO through RS3 to address
one of 16 internal interface memory registers (O-F). The
most significant address bit is RS3 while the least significant address bit is RSO. The selected register can be
read from or written into via the 8-bit parallel data bus (DO
- D7).
Do-D7
Figure 2. Microprocessor Interface Waveform~
Table 10. Microprocessor Interface Timing
Read Enable (READ) and Write Enable (WRITE)
Parameter
During a read cycle, data from the selected DSP interface
memory register is gated onto the data bus by means of
three-state drivers in each DSP. These drivers force the
data lines high for a one bit, or low for a zero bit. When not
being read, the three-state drivers assume their high-impedance (oft) state.
CSI, RSi setuptime
Data access time
Data hold time
CSi, RSi hold time
Write data setup time
Write data hold time
Write
pulse width
Strobe
1-193
Symbol
TCS
TDA
TDH
TCH
TWOS
TDHW
TWR
Min.
30
-
10
10
75
10
75
Max.
-
140
50
-
-
-
Units
ns
ns
ns
ns
ns
ns
ns
:
R96QT
.~
,
'
9600 bps QuickTurn Modem
terrupt servicing process normally continues until all interrupt requests have been serviced (i.e., all IRQ lines have
r~urned high),'
Because of the open-drain structure of IRQ, an external
pull-up resistor to +5V is required ,at some point on the IRQline. The resistor value should be small enough to pull the
IRQ line high when all IRQ drivers are off Q.e., it must overcome the leakage currents). The resistor value should be
large enough to limit the driver sink ourrent to a level acceptable to each driver. If only the modem IRQ output is
used, a resistor value of 5.6K ohms :1:20%, 0.25W, is sufficient.
the carrier ON and OFF. The responses to RTS are shown
in Table 5 (when the modem is in data mode).
Clear To Send (CTS)
Clear to Send (CTS) active indicates to the host that the
modem will transmit any data present on TXD. CTS
response times from RTS active are shown in Table 6.
Data Terminal Ready (DTR) (FOX only)
Data Terminal Ready,(DTR) active initiates the handshake
sequence when DATA =1. In answer mode, the transmitterwill immediately send answer tone. In data mode, deactivating DTR causes the transmitter to turn-off and return
to the idle state.
V.24 INTERFACE
Eleven hardware circuits provide timing, data and' control
Signals for implementing a CCITI Recommendation V.24
compatible serial interface. These signals are TIL compatible in order to drive the short wire lengths and circuits
normally found within stand-alone modem enclosures or
equipment cabinets. For driving longer cables, the voltage
levels and connector arrangement recommended by EIA
standard RS-232-C are preferred.
Data Set Ready (DSR) (FOX only)
Data Set Ready (DSR) output low indicates that the
modem is in the data transfer state. DSR OFF is an indication that the DTE is to disregard all signals appearing on
the interchange circuits-except RI. DSR will switch to the
OFF state when in test state. The ON condition of DSR indicates'the following conditions:
1. The modem is not in the talk state, i.e., an
associated telephone handset is not in control of
the line.
Most V.24 hardware interface signals have a corresponCling bit in DSP interface memory. In general, the hardware
interface Signals are complemented with res(lect to their
corresponding interface memory bits, e.g., RTS Signal
low = RTS bit set to a 1.
2. The modem is not in the process of automatically
establishing a cali via pulse or DTMF dialing.
3. The modem has generated an answer tOl)e or
detected answer tone. '
"
For full-dupl~ration, the hardware control input signals (DTR, RTS, ll.K, and ORG) are valid when the
modem is in the serial control mode (BUS = 0). Their state
is ignored when the modem is in the parallel control mode
(BUS = 1).
4. After Ring Indicator (RI) goes ON, DSR waits at
least two seconds before turning ON to allow the
telephone company equipment to be engaged.
For half-duplex operation,the modem logically ORs the
RTS input signal with the RTS interface memory bit to form
the resultant control signal regardless of the state of the
BUS bit.
DSR will go OFF 50 ms after DTR goes OFF, or 50 ms plus
a maximum of 4 seconds when the SSD bit is enabled.
Received Line Signal Detector (RLSD)
RLSD Response
Transmitted Dilta(TXD)
For Fast Train configurations, the receiver enters the training state upon detecting a significant increase in the
received signal power. If the received line Signal power is
greater than the selected threshold level at the end of the
training state, the receiver enters the data state and RLSD
is activated. If the received line signal power is less than
the threshold level at the end of the training state, the
receiver returns to the idle state and RLSD is not activated.
The modem obtains serial data to be transmitted from the
host on the Transmitted Data (TXD) input (transmitter
serial data mode) or from the Transmit Data Register
(TXDATA) register in interface memory (transmitter parallel data mode).
Received Data (RXD)
The modem presents received serial data to the host on
the Received Data (RXD) outputs in both receiver serial
and parallel data modes) and to the Receive Data Register
(RXDATA) register in interface memory in receiver parallel
data mode.
'
Also, in Fast Train configurations, the receiver initiates the
tum-off delay ,upon detecting a significant decrease in the
received signal power. If the received signal power is less
than the selected threshold at the end of the turn-off delay,
the receiver enters the idle state and RLSD is deactivated.
If the received signal power is greater than the selected
threshold at the end of the turn-off delay, the receiver
returns to the data state and RLSD is left active.
Request To Send (RTS)
Request to Send (RTS) input low causes the modem to
transmit data on TXD when CTS becomes active. In constant carrier mode, RTS can be wired tp DTR. In controlled carrier operation, independent operation' of RTS turns
"
1-194
R96QT
9600 bps QuickTurn Modem
The RLSD on-to-off response times are:
Configuration
V.29FT
V.29
V.27 FT
V.27ter
characteristics of TDCLK. The XTCLK input is then
reflected at TDClK.
Response Time
6.5:1: 1 ms
30:l:9ms
8:1: 1 ms
10:1: 5 ms
Receive Data Clock (RDClK)
The modem provides a Receive Data Clock (RDCll<) output in the form of 50:1: 1% duty cycle squarewave. The lowto-high transitions of this output coincide with the center of
received data bits. The timing recovery circuit is capable
of tracking a :1:0.01 % (relative) frequency error in the associated transmit timing source.
RLSD response times are measured with a signal at least
3 dB above the actual RLSD on threshold or at least 5 dB
below the actual RLSD off threshold.
RDCLK is provided in bo~nchronous and
synchronous communications. RDClK is not necessary in
asynchronous communications but it can be used to supply a clock for UART/USART timing. RDCLK is necessary
for synchronous communication.
RLSD Threshold
The RLSD thresholds are fixed in FDX and selectable in
HDX (see RTH bits):
Mode
FDX
HDX1
HDX2
HDX3
RlSOON
l!:-43 dBm
l!: -43 dBm
l!: -33 dBm
l!: -26 dBm
RlSO OFF
s-48dBm
s-48dBm
s-38dBm
s -31 dBm
ANALOG INTERFACE
Transient protection for TXA and RXA is recommended
when interfacing directly to a transformer. This protection
may take the form of back-to-back zener diodes or a varistor across the transformer. The characteristics of signals
TXA and RXA are summarized in Table 9.
RLSD will not respond to a guard tone or an answer tone.
For CCITT configurations, a minimum hysteresis action of
2 dB exists between the actual on-to-off transition levels.
In half-duplex modes, the threshold level and hysteresis
action are measured with an unmodulated 2100 Hz tone
applied to the Receiver Analog (RXA) input. In full-duplex
modes, regular data is used.
Transmit Analog (TXA)
The Transmit Analog (TXA) output can drive an audio
transformer or data access arrangement. TXA is a low impedance amplifier output in series with an internal 604
ohm :1:1 % resistor to match a standard telephone load of
600 ohms.
Ring Indicator (RI) (FOX only)
The modem provides a Ring Indicator (RI) output; its low
state indicates the presence of a ring signal on the line.
The low condition appears approximately coincident with
the ON segment ofthe ring cycle (during rings) on the communication channel. (The ring signal cycle is typically two
seconds ON, four seconds OFF.) The high condition of the
RI output is maintained during the OFF segment of the ring
cycle (between rings) and at all other times when ringing
is not being received. The operation of RI is not disabled
by an OFF condition on DTR.
Receive Analog (RXA)
The Receive Analog (RXA) input can originate from an
audio transformer or data access arrangement. The input
impedance is nominally 21 K ohms. The RXA input must
be shunted by an external 604 ohm :1:1% resistor in order
to match a 600 ohm source.
LINE INTERFACE
Ring Detect (RD) (FOX only)
RI will respond to ring signals applied on RD in the frequency range of 15.3 Hz to 68 Hz.
RD indicates to the modem by an ON (low) condition that
a ringing signal is present. The signal (a 4N35 optoisolator
compatible output) into the RD input should not respond to
momentary bursts of ringing less than 125 ms in duration.
The ring, if within 15 Hz to 68 Hz, is reflected on RI (if this
method of ring detection has been selected, and ringing
detection is active.)
Transmit Oata Clock (TDClK)
The modem provides a Transmit Data Clock (TDCLI<) output with the following characteristics:
Frequency. Data rate :1:0.01%.
DutyCycle. 50 :1:1%.
Off-Hook Relay Control (OHRC) (FOX only)
TDCLK is provided to the user in synchronous communications. Transmit Data (TXD) must be stable during
the one J.IS period immediately preceding and following the
rising edge of TDCLK.
The OHRC output can be used as the input to an external
relay driver to drive the Off-Hook (OH) relay when control
bit RA is set high. OHRC high indicates the OH relay is to
be closed and the modem is to be connected to the
telephone line (off-hook). OHRC low indicates the OH
relay is to be opened (on-hook).
External Transmit Clock (XTClK)
In synchronous communication, where the user needs to
supply the transmit data clock, the input XTCLK can be
used. The clock supplied at XTCLK must exhibit the same
1-195
9600 bps QulckTurn Modem
R96QT
ANCILLARY SIGNALS
Transmitter Baud Clock (TBCLK) and Receiver Baud
Clock (RBCLK)
EYESYNC
Transmitter Baud Clock (TBCLK) and Receiver Baud
Clock (RBCLK) outputs have no counterpart in the V.24 or
RS-232-C recommendations since they mark the baud interval rather than the data rate for the transmitter and
receiver, respectively. These baud clocks are useful in
identifying the order of data bits in a baud (e.g., for multiplexing data). Both signals are active high. The high-to-Iow
transition of each baud clock coincides with a high-to-Iow
transition of the respective data clock. These clocks are
held permanently high when the modem is configured for
V.21 channel 2 operation.
- - - - - j \r-----~L
EYECLKJLJ4
~
EYEX,~~
EYEY~~
MSE
LSB
Figure 3. Eye Pattern Timing
Talk (TLK) (FOX only)
1LK input low manually places the modem in idle mode.
1LK high manually initiates the handshake sequence and
places the modem in data mode.
first be converted to parallel digital form by two serial-toparallel converters and then to analog form by two digitalto-analog (D/A) converters.
Originate (ORG) (FOX only)
EYEX and EYEY outputs are 15-bit words, each with 8-bits
of significance. The 15-bit data words are shifted out most
significant bit first with the seven most significant bits equal
to zero. EYEX and EYEY are clocked by the riSing edge of
EYECLK.
ORG input manually places the modem in the originate
mode (ORG low) or the answer mode (ORG high). To
manually originate a call set ORG low and 1LK high. To
manually answer a call, set ORG high and 1LK high.
.
DIAGNOSTIC SIGNALS
EYECLK
Four signals provide the timing and data necessary to
create an oscilloscope quadrature eye pattern. The eye
pattern is simply a display of the received baseband constellation. By observing this constellation, common line
distrubances can usually be identified. Timing of these signals is illustrated in Figure 3.
EYEX and EYEY
EYECLK is a clock for use by the serial-to-parallel converters. The EYECLK output is a 288 kHz clock which is
internally divided to create the Receiver Baud Clock
(RBCLK). EYECLK is also a common multiple of all the
possible receiver data clocks. The low-to-high transitions
of RDCLK coincide with the low-to-high transitions of
EYECLK. EYECLK, therefore, can be used as a receiver
multiplexer clock.
The EYEX and EYEY outputs provide two serial bit
streams containing data for display on the oscilloscope X
axis and Yaxis, respectively. This serial digital data must
EYESYNC is a strobe for loading the DIA converters.
EYESYNC
1-196
9600 bps QuickTurn Modem
R96QT
INTERFACE MEMORY MAPS
SOFTWARE INTERFACE
Memory maps of the 16 addressable registers in the
modem transmitter (chip 0), receiver sample rate (chip 1),
and receiver baud rate (chip 2) devices are shown in
Figure 4. These a-bit registers may be read or written to
during any host read or write cycle. In order to operate on
a single bit or group of bits in a register, the host processor must read a register then mask out unwanted data.
When writing a single bit or group of bits in a register, the
host processor must perform a read-modify-write operation. That is, the host must read the entire register, set or
reset the necj3ssary bits without altering the other register
bits, then write the unaffected and modified bits back into
the interface memory register.
Modem functions are implemented in firmware executing
in three DSP devices: a transmitter device, a receiver
sample rate device, and a receiver baud rate device.
INTERFACE MEMORY
Each DSP communicates with the host processor by
means of a dual-port, interface memory. The interface
memory in each DSP contains sixteen a-bit registers,
labeled register 0 through F. Each register can be read
from, or written into, by both the host and the DSP. The
host communicates with the DSP interface memory via the
microprocessor bus shared between the three DSPs.
The host can control modem operation by writing control
bits to DSP interface memory and writing parameter
values to DSP RAM through the interface memory. The
host can monitor modem operation by reading status bits
from DSP interface memory and reading parameter values
from DSP RAM through interface memory.
INTERFACE MEMORY BIT DEFINITIONS
Table 12 defines the individual bits in the interface
memory. In the Table 12 descriptions, bits in the interface
memory are referred to using the format Y:Z:Q. The chip
number is specified by Y (0, 1 or 2), the register number
by Z (0 through F), and the bit number by Q (0 through 7,
0= LSB).
1-197
..
I
R96QT
9600 bps QuickTurn Modem
'Ransmilter Interface Memory Chip 0 (CSO)
Bit
7
5
6
4
3
1
2
0
Regl8lar
F
WRTO
E
TIA
D
-
c
-
RAM ACCESS CODE CHIP 0 (ACCO)
NSIEO NEWSO
-
NEWeO
TIE
-
-
-
-
-
-
-
-
-
-
-
-
-
-
crs
DSR
-
TCF
CDEO
DATA
DTMF
SSD
RA
A
-
9
NV25
8
BUS
-
ORG
GTE
-
-
7
RTS
TIDIS
SOlS
MHLD
EPT
TPDM
ASCR RTRN
TXCLK
TRANSMITTER CONFIGURATION (TCONF)
6
PENO PARSLO STBO BRKSO DIABT CAEO
CHARO
5
4
TBA
-
TLVL
B
-
-
ALO
RDLEO
STO
cc JAsvNCO
DLO
RDLO
DTR
X RAM DATA MSB (XDAMO)
3
X RAM DATA LSB (XDALO)
2
,
FREOMN RAM DATA MSB (YDAMO)
DDRlTXDATAIFREOUY RAM DATA LSB (yDALO)
0
Note: (-) Indicates reserved for modem uea only.
Receiver Interface Memory Chip 1 (CS1)
Bit
7
5
6
4
3
Receiver Interface Memory Chip 2 (CS2)
,
2
Bit
7
0
IIeglater
F
WRT1
RIAl
D
-
B
A
9
-
8
-
7
4
3
2
,
0
F
WR12
RBAI
E
RIA2
-
D
-
-
-
C
FR3
FR2
FRI
-
-
-
-
-
-
-
RAM ACCESS CODE CHIP 1 (ACC1)
NSIEI NEWSI
-
-
FEll
RTH
-
-
NEWCt RIEl
-
-
-
-
-
P'2DET
-
FE
DDIS
-
-
RCF
RDIS
-
-
-
-
PE
-
rnlET lONE
B
A
9
8
7
RECEIVER CONFIGURATION (RCONF)
6
5
5
4
3
2
,
0
Register
E
C
6
CHARI
-
-
PEN' PARSLI STBI
-
-
RPDM BRKS'
ASYNet
-
CEOSEL
RAM ACCESS CODE CHIP 2 (ACC2)
NSIE2 NEWS2
-
-
-
NEWC2 RIE2
-
-
-
-.
-
-
-
lONEA
TM
RI
AL2
RDLE2
ST2
RSD
LCD
6
-
5
4
-
-
-
-
-
-
RBA2
-
PNDE1
-
-
RDL2
3
X RAM DATA LSB (XDAl1)
Y RAM DAll\ MSB (YDAMl)
,
Y RAM DATA MSB (YDAM2)
RXDATAI Y RAM DAll\ LSB (YDAL1)
0
Y RAM DATA LSB (YDAL2)
DL2
X RAM DAll\ MSB (XDAM2)
2
X RAM DATA LSB (XDAL2)
Note: (-) Indlcatas reserved lor modem use only.
Figure 4. R96QT DSP Interface Memory Map
1-198
FRZEQ
-
SPEED
X RAM DATA MSB (XDAM1)
Note: (-) Ind_ reserved lor modem use only.
-
CL
R96QT
9600 bps QuickTurn Modem
Table 12. R96QT Interface Memory Bit Definitions
Mnemonic
Memory
Location
Default
Value (Hex)
Name/Description
ACCO
0:F:0-7
o
RAM Access Code Chip O. Register ACCO contains the RAM access code used in reading RAM locations in the transmitter device.
ACC1
1 :F:0-7
o
RAM Access Code Chip 1. Register ACC1 contains the RAM access code used in reading
RAM locations in the receiver sample device.
ACC2
2:F:0-7
o
RAM Access Code Chip 2. Register ACC2 contains the RAM access code used in reading
RAM locations in the receiver baud device.
ALO
0:4:7
Local Analog Loopback Chip O.
AL2
2:4:7
o
o
ASCR
0:9:6
o
Append Scrambled Ones. When ASCR is a 1, one baud of scrambled mark is included in
the V.29 FT and V.27 FT training sequence. The RTS-CTS delay is thus extended by 1
baud period when ASCR is a 1. (HDX)
ASYNCO
0:4:3
o
Asynchronous Mode Chip O. When ASYNCO is a 1, asynchronous data mode is selected
in the transmitter. When ASYNCO is a 0, synchronous data mode is selected. (FDX)
ASYNC1
1:4:3
o
Asynchronous Mode Chip 1. When ASYNC1 is a 1, asynchronous data mode is selected
in the receiver. When ASYNC1 is a 0, synchronous data mode is selected. (FDX)
BRKSO
0:5:1
o
Break Sequence Chip O. When control bit BRKSO is a 1, the modem will send continuous
space. When BRKSO is a 0, the modem will transmit data from TXDATA (TPDM = 1). (FDX)
(Asynchronous operation only)
BRKS1
1:5:1
BUS
0:8:7
Local Analog Loopback Chip 2. When both ALO and AL2 are 1, the modem will go
through an analog loopback according to recommendation V.54 loop 3. The modem may be
placed in analog loopback in either idle or data mode. However, when ALO or AL2 is a 1 in
data mode, the connection is terminated. AL2 must be set first, followed by ALO. (V.22, V.22
bis, V.22 AlB, and Bell 212A) (FOX)
Break Sequence Chip 1. When status bit BRKS1 is a 1, the modem is receiving continuous
space. When BRKS1 is a 0, the modem is receiving data and outputting the data to
RXDATA (RPTM = 1). (FDX) (Asynchronous operation only)
o
Bus Select. When control bit BUS is a 1, the modem is in the parallel control mode; when
BUS is a 0, the modem is in the serial control mode. BUS can be in either state to configure
the modem. In either mode, the modem is configured by the host writing to interface
memory via the microprocessor bus. Note that the modem automatically defaults to the
serial mode at power-on. (FDX)
Serial Control Mode
In serial control mode, standard V.24 (RS-232-C comj)atible~nals are used to control the
transfer of channel data. The control signals used are DTR, RTS, lLK, and ORG. Outputs
such as RLSD and DSR are reflected both in the interface memory and the V.24 interface.
Once the BUS bit has been set to a 0, the state of the DTR, RTS, DATA, and ORG bits are
ignored.
Parallel Control Mode
In the parallel control mode, the modem is controlled by bits written to interface memory via
the microprocessor bus. Data transfer is also over the microprocessor bus. The control bits
are DTR, RTS, ORG, and DATA.
If the parallel control mode is to be used, it is recommended that the lLK pin be tied to
ground. A floating lLK pin will assume a logic 1 Which will immediately put the modem into
the data mode before the BUS bit is set.
CAEQ
0:5:0
o
Cable Amplitude Equalizer. When CAEQ = 1, an amplitude compromise equalizer is allocated in the transmitter path. The NEWCO bn must be set after setting the CAEQ bit. (V.29
and V.29 FT modes only)
1-199
•
9600 bps QuickTurn Modem
R96QT
Table 12. R96QT Interface Memory Bit Definitions (Cont'd)
Mnemonic
CC
Memory
Location
0:4:4
Default
Value (Hex)
o
Name/Descrlptlon
Controlled Carrier. When control M CC is a 1 , the modem operates in controlled carrier;
when CC is a 0, the modem operates in constant carrier.
Controlled carrier allows the modem transmitter to be controlled by the RTS pin or the RTS
M. Its effect may be seen in the descriptions of the RTS and CTS bits. (FOX)
COEO
CEOSEL
0:9:2
o
Compromise Delay Equalizer Enable. When control bH COEO is a 1, an Infin~e Impulse
Response (II R) delay equalizer is placed in the transm itter path. (HDX)
1:9:2
o
Carrier Detector. Status bit CDET is set to a 0 when passband energy is being detected
and a training sequence is not in process.
1:4:0,1 ,2
o
Compromise Equalizer Select. CEOSEL selects the type of equalizer to be placed in the
rllCeiver path. (HDX)
Curve Matched
No Equalization
US· Long
Japanese 3-Link
Cable 1
Cable 2
Cable 3
CHARO
0:5:6,7
2
1:5:6,7
2
1
0
0
1
0
0
1
0
1
1
0 0
0 1
Character Length Select Chip O. CHARO selects eHher 8, 9, 10, or 11 bit characters (includes data, stop, and start bits) for the transmitter in asynchronous data mode
(ASYNCO = 1). The M representations are:
Bits Per Character
8 bits
9 bHs
10 bits
11 bits
CHARl
2
0
0
0
0
1
1
7
6
0
0
0
1
1
1
0
1
Character Length Select Chip 1. CHARl selects 8,9,10 or 11 bit character length (includes data, stop, and start bits) for the receiver in asynchronous data mode (ASYNCl = 1).
The bit representations are:
Bits Per Character
8 bits
9Ms
10 bits
llbHs
7 6
0 0
0 1
10
11
It is possible to change character length during the data mode. Errors in the data will be expected between change over and the resynchronization (which occurs on the next start bH
after the change is implemented).
CL
2:4:0
o
Control Line. When CL is set to a 1, the receiver goes to data mode upon detection of 270
ms of energy after a loss of carrier. A retrain may be required once the modem is back in
data mode (see RTRN bit). Before CL is set to a 1, an initial handshake must be completed.
(FOX)
CTS
O:A:l
o
Clear·ta-Send. When status bit CTS is a 1, the modem will transmit any data present at
TXD. (FDX)
OATA
0:9:1
o
Data Mode. When control bit DATA is a 0, the modem is in the idle mode and data is not
being transmitted. The modem is prevented from entering and proceeding with the handshake (start-up) sequence and will ignore all V.24 interface signals. This bit should be set to
a 1 by the host at a suitable time after completion of dialing or answering.
When control M DATA is a 1 , the modem is in the data mode. This bit allows the modem to
enter the data mode after the host counts a programmable number of rings by counting the
required number of RI bit transitions. (FDX)
1-200
R96QT
9600 bps QuickTurn Modem
Table 12. R96QT Interface Memory Bit Definitions (Cont'd)
Mnemonic
Memory
Location
Default
Value (Hex)
Name/Descrlptlon
ODR
0:0-7
DDIS
1:7:5
o
Descrambler Disable. When control bit OOIS is ai, the receiver descrambler Is disabled;
when ODIS is a 0, the descrambler is enabled. (HDX)
DIABT
0:5:1
o
Disable Abort Timer. When OIABT is set to ai, the 30 second abort timer in the modem initializing a handshake is disabled. When DIABT is set to a 0, setting the DATA bit will initialize the modem for a handshake (originating modem looks for tone or answering modem
sends tone and unscrambled 1s) for 30 seconds before it aborts the handshake. (FOX only)
OLO
0:4:1
OL2
2:4:1
o
o
Dial Digit Register. OOR is used to load the digits to be dialed when in transmitter Call Request mode (TCONF = 80). Example: If a 4 is to be dialed, a 04 (hex) should be loaded.
This action also causes the interrupt to be cleared. The modem automatically accounts for
the interdigit delay. Note: DOR Is a write-only register. (FOX)
Digital Loop Chip O.
Digital Loop Chip 2. When OLO and OL2 are both ai, the modem is manually placed In
digital loopback. OLO and OL2 should be set only during the data mode. The DSR and CTS
bits will be reset to O. The local modem can then be tested from the remote modem end by
looping a remotely generated test pattern. At the remote modem, all interface circuits behave normally (as in the data mode).
At the conclusion of the test, OLO and OL2 must be reset to O. The local modem will then
return to the normal data mode with control reverting to the OTR input. (OL2 must be set
first followed by OLO.) (V.22, V.22 bis, V.22 AlB, and Bell 212A). (FOX)
OSR
O:A:O
o
Data Set Ready. The ON condition of the status bit OSR indicates that the modem is in the
data transfer state. The OFF condition of OSR is an indication that the OTE is to disregard
all signals appearing on the interchange circuits - except RI. DSR will switch to the OFF
state when in test state. The ON condition of OSR indicates the following:
The modem is not in the talk state, i.e., an associated telephone
handset is not in control of the line.
The modem is not in the process of automatically establishing a call via
pulse or OTMF dialing.
The modem has generated or detected answer tone.
After ring indicate goes ON, OSR waits at least two seconds before turning ON to allow the
telephone company equipment to be engaged.
OSR will go OFF 50 ms after OTR goes OFF, or 50 ms plus a maximum of 4 seconds when
the SSO bit is enabled. (FDX)
OTMF
0:9:0
o
Touch Tone/Pulse Dialing. When transmitter Call Request configuration is selected
(TCONF 80) and control bit OTMF is ai, the modem will auto dial using tones. When
OTMF is a 0, the modem will dial using pulses.
=
The timing for the pulses and tones are as follows (power-on timing):
Pulses-
Relay open 64 ms
Relay closed 36 ms
Interdigit delay 750 ms
Tones-
Tone duration 95 ms
I nterdigit delay 71 ms
The OTMF bit can be changed during the dialing process to allow either tone or pulse dialing of consecutive digits. The tone pairs and corresponding dial digits are shown in Table 3.
The output power level ofthe OTMF tones is:
-1 dBm
:t
1 measured at TXA
1-201
•
R96QT
9600 bps QuickTurn Modem
T'llble 12. R96QT Interface Memory Bit Definitions (Cont'd)
Memory
Mnemonic Location
Default
Value (Hex)
Name/Descrlptlon
OTR
0:4:0
o
Data Terminal Ready. When set to,a 1, control bH OTR initiates the handshake sequence If
DATA = 1. In answer mode, the transmitter will immediately send answer tone. In the data
mode, setting the OTR bit to a 0 causes the transmitter to turn off and return to the idle
stete. (FOX)
EPT
0:7:3
o
Echo Protector Tone. When EPT ls a 1, an unmoduiated carrier Is transmitted for 185 ms
followed by 20 ms of no transmitted energy et the start of the transmiBSion. (HOX)
FE
1:8:1
o
Framing Error. When set to a 1, status bit FE indicates that more than 1 in 8 (or 1 in
4) cheracters were received without a stop bit in asynchronous mode. When FE is
reset to a 0, no framing error is detected. (FOX)
1:9:6
o
Faat Energy Detect. When FED Is a 0, energy above the threshold is present in the
passband. (HOX)
FREQL
0:1 :0-7
0:0:0-7
o
o
Frequency Number Least Significant Byte.
FREQM
Frequency Number Moat Significant Byte. The host conveys tone generetlon data to
the transmitter by writing a 16-bit data word to the FREQL and FREQM registers as
shown below (HOX):
FREQM Register (0:0)
I
Bit:
-43 dBm
> -33dBm
> -26 dBm
> -16 dBm
< -48 dBm
< -38 dBm
< -31 dBm
< -21 dBm
1
2
3
The modem presents received serial data to the local DTE on the
Received Data (RXD) output.
Request To Send (RTS)
Data Terminal Ready (DTR)
Activating Request to Send (RTS) causes the modem to transmit data on TXD when CTS becomes active. The RTS pin is
logically ORed with the RTS bit.
In V.32, V.22 bis, V.22 and Bell 212A configurations, activating Data
Terminal Ready (DTR) initiates the handshake sequence, provided
that the DATAO bit is a 1. If in answer mode, the transmitter will
immediately send answer tone.
Clear To Send (CTS)
In V.21, V.23 and Bell 103 configurations, activating DTR causes
the modem to enter the data state provided that the DATAO bit is
a 1. If in answer mode, the transmitter will immediately send
answer tone. In these modes, if controlled carrier is enabled,
carrier is controlled by Request-to-Send (RTS).
Clear to Send (CTS) active indicates to the local DTE
that the modem will transmit any data present on TXD. CTS
response times from an active condition of RTS are shown
in Table 2.
Received Line Signal Detector (RLSD)
During the data mode, deactivating DTR causes the transmitter
to turn-off and return to the idle state.
Received Line Signal Detector (RLSD) active indicates to the local
DTE that energy above the receive level threshold is present on
the receiver input, and that the energy is not a training sequence.
The DTR input and the DTR control bit in chip 0 are logically
ORed.
1-221
R9696DP
V.32 9600 bps Full-Duplex Modem
Data Set Ready (DSR)
Transmitter Multiplexer Clock (TMXCLK)
Data Set Ready (DSR) ON indicates that the modem is in the data
transfer state. The OFF condition of DSR indicates that the DTE
is to disregard all signals appearing on the interchange circuits
except Ring Indicator (Ai). DSR is OFF when the modem is in a
test mode (Le., local analog or remote digital loopback).
The Transmitter Multiplexer Clock (TMXClK) output is a 288 kHz
clock which is internally divided down to create the Transmitter
Baud Clock (TBClK). TMXClK is also a common multiple of all
the possible transmitter data clocks. The high-to-Iow transitions
of TDClK coincide with the high-to-Iow transitions of TMXClK.
The DSR status bit in chip 0 reflects the state of the DSR output.
LINE INTERFACE
The Transmitter Analog (TXA) output and Receiver Analog (RXA)
input allow modem connection to either a leased line or the public switched telephone network (PSTN) through an audio transformer or a data access arrangement. The analog signal characteristics of TXA and RXA are described in Table 7.
Ring Indicator (RI)
The Ring Indicator (Ai) output follows the ringing signal present
on the line with a low level (OVi during the ON time, and a high
level ( + 5V) during the OFF time coincident with the ringing signal.
The RI status bit in chip 2 reflects the state of the
Table 7.
Ai output.
Analog Interface Characteristics
Characteristics
The transmitter output impedance is 604 ohms ± 1%.
The receiver input impedance is 66.5K ohms.
Transmit Data Clock (TDCLK)
The modem outputs a synchronous Transmit Data Clock (TDCll<)
for USRT timing. The TDClK frequency is the data rate (± 0.01%)
with a duty cycle of 50 ± 1%.
Transmitter Analog (TXA)
Transmit Data (TXD) must be stable during the one P.s periods
immediately preceding the rising edge of TDClK and following
the rising edge of TDClK. The TDClK source can be internal,
external (input on XTCll<) or slave (to RDCll<) as selected by
bits in the transmitter interface memory.
The Transmitter Analog (TXA) output can drive an audio transformer or data access arrangement. TXA is a low impedance
amplifier output in series with an internal 604 ohm ± 1% resistor
to match a standard telephone load of 600 ohms.
External Transmit Clock (XTCLK)
The Receiver Analog (RXA) input can originate from an audio
transformer or data access arrangement. The input impedance
is nominally 66.5K ohms. The RXA input must be shunted by an
external 904 ohm ± 1010 resistor in order to match a 600 ohm
source.
Receiver Analog (RXA)
In synchronous communication, an external transmit data clock
can be connected to the modem XTClK input. The clock supplied
at XTCLK must exhibit the same characteristics as TDClK. The
XTClK input is then reflected at the TDClK output.
The maximum received signal at RXA is 0 dBm. The maximum
near-end echo at RXA that the modem can cancel in V.32 mode
is -5dBm.
Receive Data Clock (RDCLK)
Transient protection for TXA and RXA is recommended when interfacing directly to a transformer. This protection may take the form
of back-to-back zener diodes or a varistor across the transformer.
The modem outputs a synchronous Receive Data Clock (RDCll<)
for USRTtiming. The RDClKfrequency is the data rate (± 0.01%)
with a duty cycle of 50 ± 1%. The RDClK low-to-high transitions
coincide with the center of the received data bits. The timing recovery circuit can track a ± 0.01% frequency error in the associated
transmit timing source.
Ring Detect (RD)
The Ring Detect (RD) input is monitored for pulses in the range
of 15 Hz to 68 Hz. The frequency detection range may be changed
by the host in DSP RAM. The circuit driving RD should be a 4N35
optoisolator or equivalent. The circuit driving RD should not
respond to momentary bursts of ringing less than 125 ms in duration, or less than 40 VRMS (15 Hz to 68 Hz) across TIP and RING.
ANCILLARY SIGNALS
Transmitter Baud Clock (TBCLK) and
Receiver Baud Clock (RBCLK)
DATA2 bit must be setto a 0 to enable ring detection. Detected ring
signals are reflected on the R1 output.
Transmitter Baud Clock (TBClK) and Receiver Baud Clock
(RBCll<) outputs have no counterpart in the V.24 or RS-232-C
recommendations since they mark the baud interval rather than
the data rate for the transmitter and receiver, respectively. These
baud clocks are useful in identifying the order of data bits in a baud
(e.g., for multiplexing data). Both Signals are active high. The first
bit in each baud begins with the falling edge of the corresponding baud clock.
Off-Hook Relay Control (OHRC)
OHRC is an output designed to drive directly a + 5V reed relay
coil with a worst case resistance of 360 ohms having a must operate voltage of 4.0 Vdc. A clamp diode integrated in the modem
eliminates the need for a diode across the relay coil. An
1-222
R9696DP
V.32 9600 bps Full-Duplex Modem
external transistor can be used to drive heavier loads (e.g., electromechanical relays). OHCR is controlled by the host setting the
RA bit in the interface memory.
I
EYESYNC
-----.L
1-\
Line Transformer Requirements for V.32
V:32 places high requirements upon the Data Access Arrangement
(DAA) to the telephone line. V.32 uses the same bandwidth for
transmission of data in both directions. Any non·linear distortion
generated by the OM in the transmit direction (known as near·
end echo) cannot be canceled by the modem's echo canceller and
interferes with data reception. The user must therefore ensure that
the total harmonic distortion due to near-end echo at the RXA input
to the R9696DP is at least 27 dB below the minimum level of
received signal at the same point. Note that the major source of
non-linear distortion in a OM is the line transformer. When designing a OM the user should take into account a worst case subscriber line, giving very poor matching to the OM hybrid circuit
and resulting in a large near-end echo (to simulate worst case conditions it is suggested that an 1800 ohm resistor in series with a
0.47 I'F capacitor be used in place of the two wire telephone line).
~ fv-::-v--::--vJ
EYEY~~
EYEX,
MSB
Figure 3.
LSB
Eye Pattern Timing
SOFTWARE INTERFACE
Modem functions are implemented in firmware executing in
three DSPs: transmitter device, receiver sample rate device, and
receiver baud rate device.
DIAGNOSTIC SIGNALS
INTERFACE MEMORY
Four signals provide the timing and data necessary to create an
oscilloscope quadrature eye pattern. The eye pattern is simply a
display of the received baseband constellation. By observing this
constellation, common line disturbances can usually be identified.
Timing of these signals is illustrated in Figure 3.
Each DSP communicates with the host processor by means of a
dual-port, interface memory. The interface memory in each DSP
contains thirty-two 8-bit registers, labeled register 00 through 1F.
Each register can be read from, or written into, by both the host and
the DSP. The host communicates with the DSP interface memory
via the microprocessor bus shared between the three DSPs.
EYEX and EYEY
The host can control modem operation by writing control bits to
DSP interface memory and writing parameter values to DSP RAM
through the interface memory. The host can monitor modem operation by reading status bits from DSP interface memory and reading parameter values from DSP RAM through interface memory.
The EYEX and EYEY outputs provide two serial bit streams containing data for display on the oscilloscope X axis and Y axis,
respectively. This serial digital data must first be converted to
parallel digital form by two serial-to-parallel converters and then
to analog form by two digital-to-analog (D/A) converters.
INTERFACE MEMORY MAPS
EYEX and EYEY outputs are 15-bit words, each with 8-bits of significance. The 15-bit data words are shifted out most significant
bit first with the seven most significant bits equal to zero. EYEX
and EYEY are clocked by the riSing edge of EYECLK.
Memory maps of the 96 addressable registers in the modem transmitter (chip 0), receiver sample rate (chip 1), and receiver baud
rate (chip 2) devices are shown in Figure 4. These 8-bit registers
may be read or written during any host read or write cycle. In order
to operate on a single bit or a group of bits in a register, the host
processor must read a register then mask out unwanted data.
When writing a single bit or group of bits in a register, the host
processor must perform a read-modify-write operation. That is,
read the entire register, set or reset the necessary bits without
altering the other register bits, then write the unaffected and modified bits back into the interface memory.
EYECLK is a clock for use by the serial-to-parallel converters. The
EYECLK output is a 288 kHz clock which is internally divided down
to create the Receiver Baud Clock (RBCLKj. EYECLK is also a
common multiple of aU the possible receiver data clocks. The lowto-high transitions of RDCLK coincide with the low-to-high
transitions of EYECLK. EYECLK, therefore, can be used as a
receiver multiplexer clock.
INTERFACE MEMORY BIT DEFINITIONS
Table 8 defines the individual bits in the interface memory. In the
Table 8 descriptions, bits in the interface memory are referred to
using the format Y:Z:Q. The chip number is specified by
Y (0,1 or 2), the register number byZ (00 through 1F), and the bit
number by Q (0 through 7, 0 = LSB).
EYESYNC
EYESYNC is a strobe for loading the DIA converters.
1-223
V.32 9600 bps Full-Duplex Modem
R9696DP
R9696DP DSP Interlace Memory (Chip 0)
I~
7
6
5
NSIAO
NCIAO
DBIAO
-
4
3
1
2
0
Register
IF
IE
10
lC
lB
lA
19
18
-
XACCO
-
YACCO
17
16
15
14
13
12
11
10
OF
OE
00
OC
DB
OA
09
08
07
06
OS
04
03
02
01
00
-
-
-
NSIEO NEWSO NCIEO
NEWCO
DBIEO
DBAO
XCRDO XWTO XCRO
X RAM ADDRESS XADDO
YCRDO YWTO YCRO
Y RAM ADDRESS YADDO
X RAM DATA MSB XDAMO
X RAM DATA LSB XDALO
Y RAM DATA MSB YDAMO
Y RAM DATA LSB YDALO
EARCO
-
-
-
-
-
-
-
TLVL
-
-
-
TXCLK
TCONF
-
-
-
-
-
CTS
-
NV25
CC
ASYNO TPDM
RDL
EXOSO
ECFZ ECSO
-
-
-
-
-
-
DTMF
V21S0
L2ACT
-
LLO
FECSO TXSO
-
-
-
ORG
-
-
-
-
TM
-
-
-
-
DSR
-
-
DATAO
-
-
L3ACT
PENO STBO
CEO
-
-
SOlS
-
-
DTR
RTRN
RTS
RA
MHLO
WDSZO
STOFF TSPA
-
ARCO
HKABO
-
-
GTE
GTS
-
-
TSPY
TBUFFERITSPX
(-) Indicates reserved for modem use only.
R9696DP DSP Interlace Memory (Chip 1)
~
7
6
NSIAI
NCIAI
DBIAI
5
4
-
NSIEI
2
3
R9696DP Interlace Memory (Chip 2)
1
~
0
IF
IE
10
lC
lB
lA
19
18
XACCI
-
YACCI
-
-
-
17
16
15
14
13
12
11
10
OF
OE
00
OC
DB
OA
09
08
07
06
OS
04
03
02
01
00
-
-
RLSD
RTDET
FED
.-
-
-
-
-
-
-
-
-
-
-
-
_.
-
-
-
-
-
-
V21S1
ASYNI
ROLE
-
-
-
EXOSI
-
-
-
-
-
-
-
-
-
LLI
DATAl
-
-
PENI STBI
CE023
-
RLSDE ARCI
TDAE
SODIS
-
-
-
SPEED
S1DET SCRI U1DET SADET
MDET ACDET CADET CCDET SDET SNDET
TONEA TONEB TONEC ATV25 ATBEL V21
-
IF
IE
10
lC
lB
lA
19
18
17
16
15
14
13
12
11
10
OF
OE
00
OC
OB
OA
09
08
07
06
05
04
03
02
01
00
NEWSI NCIEI
NEWCl
DBIEI
DBAI
XCRDI XWTl XCRI
X RAM ADDRESS XADDI
YCRDI YWTl YCRI
Y RAM ADDRESS YADDI
X RAM DATA MSB XDAMI
X RAM DATA LSB XDAL 1
Y RAM DATA MSB YDAMI
Y RAM DATA LSB YDAL 1
- EARCI
ABCODE
RTH
RCONF
-
-
-
-
HKABI
RSEO
-
-
-
-
-
WDSZl
-
-
-
-
-
-
RSEOM
RBUFFER/RSEOL
6
5
4
3
2
NSIA2
1
0
NSIE2 NEWS2
DBIA2
XACC2
-
YACC2
-
-
-
-
-
-
-
-
-
-
-
DBIE2
XCRD2 XWT2
X RAM ADDRESS XADD2
YCRD2 YWT2
Y RAM ADDRESS YADD2
X RAM DATA MSB XDAM2
X RAM DATA LSB XDAL2
Y RAM DATA MSB CYDAM2
Y RAM DATA LSB YDAL2
-
YCR2
-
-
-
-
-
-
-
-
RI
-
-
-
-
-
-
-
-
-
-
-
-
-
EORES EQT2
-
-
DATA2
-
-
-
RSPA
EOFZ
IFIX
AMTD
RSPY
RSPX
R9696DP DSP Interface Memory Map
1-224
DBA2
XCR2
-
DDIS
-
-
-
(-) Indicates reserved for modem use only.
(-) Indicates reserved for modem use only.
Figure 4.
7
Register
Register
TOD
-
R9696DP
V.32 9600 bps Full-Duplex Modem
Table 8.
Mnemonic
Memory
Location
R9696DP Interface Memory Bit Definitions
Default
Value
AAOET
1 :C:7
-
ABCODE
1: 14:0-7
00
Name/Description
AA Detector. When set to a 1, status bit AADET indicates that a V.32 AA sequence has been
detected. This bit is reset to a 0 by the modem at the start of the CC sequence. (V.32)
Abort Code. If the V.32 handshake fails. status bit HSKAB is set to a 1 and an abort code is written
into ABCODE. This code indicates the point in the handshake where the failure occurred. The abort
code is not cleared by the modem but should be cleared by the host after it has been read.
The abort codes and their meanings are listed in the table below. Refer to CCITT Recommendation
V.32 for meanings of the signal mnemonics used. (V.32)
Abort Code
00
01
02
03
04
05
OS
07
08
09
OA
-
Reason for Aborting
No failure.
Failed to detect AC/CA transition (calling).
Failed to detect AA/CC transition (answering).
Failed to detect CAIAC transition (calling).
Not used.
Timed out waiting for signal at the start of the S sequence.
Failed to detect S sequence.
Not used.
Failed to detect Rate sequence (Rl, R2 or R3).
Failed to detect SIS transition.
Failed to detect E sequence.
Power loss during TRN or Rate sequence.
ACOET
1 :C:S
AC Detector. When set to a 1, status bit ACDET indicates that a V.32 AC sequence has been detected.
This bit is reset to a 0 by the modem when a CA sequence or an energy dropout is detected. (V.32)
AMTD
2:2:5
1
Amplitude Modulation ll'acker Disable. When control bit AMTD is a 0, an adaptive amplitude
modulation tracker is enabled in the receiver; when a 1, the tracker is disabled. (V.32, V.22 bis, V.22,
Bell 212A)
ARCO
0:3:3
1
Automatic Rate Change Enable Chip O. When control bits ARCO and ARCl are a 1, the modem will
automatically condition itself to transmit data at the highest common rate negotiated during the V.32
handshake. The host may specify the undefined bits in the rate sequence in DSP RAM. When ARCO
and ARCl are a 0, the modem cannot change from the rate it is configured to before beginning the
handshake. However, it is possible for the host to interact with the rate sequences during the
handshake and then set the transmitter configuration as desired. (See EARCO.) (V.32)
When control bit ARCO and ARCl are a 1, then setting the RTRN bit will cause the modem to send a
rate change sequence, rather than the normal retrain sequence. (V.22 bis) (See RTRN.)
ARCl
1 :3:3
1
Automatic Rate Change Enable Chip 1. See ARCO and EARCO.
ASYNO
0:8:7
0
Asynchronous/Synchronous. When configuration bit ASYNO is a 1, asynchronous mode is selected
in the transmitter; when 0, synchronous mode is selected. When the ASYNO bit changes from 0 to 1,
the transmitter's asynchronous to synchronous converter is configured according to the EXOSO,
PENO, STBO and WDSZO bits at that time. (EXOSO, PENO, STBO and WDSZO must be configured
before ASYNO changes from a 0 to a 1.) ASYNO may be used to switch between synchronous and
asynchronous modes at any time in idle or data mode. Do not set this bit in V.21, V.23 or Bell 103
modes. Asynchronous operation is not available in V.32 12000 bps. (V.32, V.22 bis, V.22, Bell 212A)
ASYNl
1 :8:7
0
Asynchronous/Synchronous. When configuration bit ASYNl is a 1, asynchronous mode is selected
in the receiver; when 0, synchronous mode is selected. When the ASYNl bit changes from 0 to 1, the
receiver's synchronous to asynchronous converter is configured according to the EXOS1, PEN1, STBl
and WDSZl bits at that time. (EXOS1, PEN1, STBl and WDSZl must be configured before ASYNl
changes from a 0 to a 1.) ASYNl may be used to switch between synchronous and asynchronous
modes at any time in idle or data mode. Do not set this bit in V.21, V.23 or Bell 103 modes.
Asynchronous operation is not available in V.32 12000 bps. (V.32, V.22 bis, V.22, Bell 212A)
ATBEL
1 :B:3
-
ATV25
1 :B:4
-
Bell Answer Tone Detector. When set to a 1, status bit ATBEL signifies that the modem receiver
detected a 2225 Hz answer tone. The bit is set to a 1 when the answer tone is detected, and is cleared
to a 0 when the tone ends. ATBEL is only active when the DATAl bit is a 0 and the modem is in
originate mode. (Bell 212A, Bell 103)
V25 Answer Tone Detector. When set to a 1, status bit ATV25 signifies that the modem receiver
detected a 2100 Hz answer tone. The bit is set to a 1 when the answer tone is detected, and is cleared
to a 0 when the tone ends. ATV25 is only active when the DATAl bit is a 0 and the modem is in
originate mode. (V.32, V.22 bis, V.22, V.23, V.21)
1-225
•
i
R9696DP
V.32 9600 bps Full-Duplex Modem
Table 8.
Mnemonic
CADET
CC
Memory
location
R9698DP Interface Memory Bit Definitions (Continued)
Default
Valua
NamalDascriptlon
"
'I:C:5
-
CA Detector. When set to a I, status bit CADET indicates that a V.32 CA sequence has basn
detected. This bit is reset to a 0 by the modem when a AC sequence is detected. (V.32)
0:9:6
0
Controlled Carrier. When control bit CC is a I, the modem operates in controlled carrier; when 0, the
modem operates in constent carrier.
Controlled carrier allows the modem transmitter to be controlle~the RTS pin or the RTS bit
(see Table 2). In V.22 bis and V.22 controlled carrier, when the RTS pin goes to a 0, or the RTS bit set
to a I, the transmitter immediately sends scrambled ones for 270 ms and then turns on th" CTS
signal and the CTS bit. At 2400 bps, it is recommended thet a retrain be sent once in the date mode
to ensure that synchronization occurs. (V.22 bis, V22, V.21, V.23, Bell 103)
CCDET
I:C:4
-
CC Detector. When set to a I, status bit CCDET indicates that a V.32 CC sequence has been
detected. This bit is reset to a 0 by the modem when an energy dropout is detected. (V.32)
CEQ
0:5:3
1
Compromise Equalizer Enable. When control bit CEQ is a I, the transmitter's digital compromise
equalizer is inserted into the transmit peth. This bandpass equalizer has host programmable taps in
DSP RAM. CEQ should be a 0 dunng local analog loopback.
CEQ23
1:5:3
0
V.23 Compromise Equalizer Enable. When control bit CEQ23 is a I, the receiver's digitel
compromise equalizer is inserted into the receive path. This equalizer can only be enabled in V.23
1200 and 600 configurations. This bandpass equalizer has host programmable teps in DSP RAM. (V.23)
CTS
0:F:5
-
Clear To Send. When set to a I, status bit CTS indicates to the DTE that the training sequence has
been completed and any data present at TXD (serial mode) or in TBUFFER (perellel mode) will be
transmitted (see TPDM). CTS response times from an RTS ON or OFF trensltion efter the modem has
completed a handshake are shown in Table 2. The CTS OFF-to-ON response time is programmable
in DSP RAM.
DATAO
0:9:2
1
Data Chip O. When control bit DATAO is a 0, the transmitter is prevented from entering and
proceeding with the handshake (start-up) sequence and will ignore all V.24 interface signals. This bit
should be set to a 1 by the host at a suitable time after completion of dialing or answering.
DATAl
1:9:2
1
Data Chip 1. When control bit DATAl is a 0, the receiver is prevented from entering and proceeding
with the handshake (start-up) sequence. If in originate mode, the answer tone detector is still active.
Also, in V.32 the AC detector is active. This bit should be set to a 1 by the host at a suitable time after
completion of dialing or answering.
Recommended procedure for originating a call in V.32 using DATAl:
Reset DATAl and DTR to a 0
Establish a call
Detect answer tqne using ATV25
After receiving answer tone for 1 second, set DtR to a 1
When ATV25 equals 0 AND ACDET equals I, set DATAl to a 1
The handshake will now proceed
DATA2
2:9:2
1
Date Chip 2. When control bit DATA2 is a 0, the ringing dl'lector Is enabled, and when a I, the
ring!!!.g detector is disabled. This bit should be set to a 1 after the modem goes off-hOOk, otherwise
the RI signal and RI bit will give spurious outputs.
DBAO
O:I'E:O
-
Data Buffer Available Chip O. When set to a I, status bit DBAO signifies that the transmitter has reed
register 0: 0 (TBUFFER), or registers 0: 1 (TSPy) and 0: 0 (TSPX), and the host can write new date
into register 0: 0, or registers 0: 1 and 0: O. This condition can also cause IRQ to be asserted. The
host writing to register 0: 0 resets the DBAO and DBIAO bits to O. (See DBIEO and DBIAO.)
DBAI
1 :IE:O
-
Data Buffer A1(allabla Chip 1. When set to a I, status bit DBAI signifies that the receiver wrote valid
,data into r8!1!!!.er 1:0 (RBUFFER), or registers 1:1 (RSEQM) and 1:0 (RSEQL). This condition can
also cause IRQ to be asserted. The host reading register 1:0 resets the DBAI and DBIAI bits to O.
(See DBIEI and DBIA1.)
DBA2
2:1E:0
-
Data Buffar Available Chip 2. When set to a I, status bit DBA2 signifies that the receiver wrote valid
data into registers 2: 1 (RSPY) and 2: 0 (RSPX). This condition can also cause IRQ to be asserted.
The host reading register 2: 0 resets the DBA2 and DBIA2 bits to O. (See DBIE2 and DBIA2.)
1-226
V.32 9600 bps Full-Duplex Modem
R9696DP
Table 8.
Mnemonic
Memory
Location
R9696DP Interface Memory Bit Definitions (Continued)
Default
Value
DBIAO
O:IE:6
-
DBIAI
1:IE:6
-
NamelDescrlptlon
Data Buffer Interrupt Active Chip O. When the transmitter data buffer interrupt is enabled (DBIEO is
a 1) and register 0:0 is empty (DBAO Is selto a I), the transmitter asserts IRQ and sets status
bit DBIAO to a 1 to indicate that DBAO going to a 1 caused the interrupt. The host writing to register
0: 0 resets the DBIAO bit to a 0 and clears the interrupt request due to DBAO. (See DBIEO and DBAO.)
Data Buffer Interrupt Active Chip 1. When the receiver chip 1 data buffer interrupt is enabled _
(DBIEI is a 1) and register 1 : 0 is written to by the DSP (DBA 1 is set to a 1), the receiver asserts IRQ
and sets DBIA1 to a 1 to indicate that DBA1 going to a 1 caused the interrupt. The host reading
register 1 : 0 resets the DBIA1 bit to a 0 and clears the interrupt request due to DBA1. (See DBA1
and DBIE1.)
DBIA2
2:1E:6
-
DBIEO
0:IE:2
0
Data Buffer Interrupt Enable Chip O. When control bit DBIEO is a 1 (interrupt enabled), the
transmitter will assert IRQ and set the DBIAO bit to a 1 when DBAO is set to 1 by the DSP. When
DBIEO is a 0 (interrupt disabled), DBAO has no effect on IRQ or DBIAO. (See DBAO and DBIAO.)
DBIEI
1:IE:2
0
Data Buffer Interrupt Enable Chip 1. When control bit DBIEI is a 1 (interrupt enabled), the receiver
will assert IRQ and selthe DBIAI bit to a 1 when DBAI is selto a 1 by the DSP. When
DB lEI is a 0 (interrupt disabled), DBA1 has no effect on IRQ or DBIA1. (See DBA1 and DBIA1.)
DBIE2
2:1E:2
0
Data Buffer Interrupt Enable Chip 2. When control bit DBIE2 is a 1 (interrupt enabled), the receiver
will assert IRQ and set the DBIA2 bit to a 1 when DBA2 is set to a 1 by the DSP. When DBIE2 is a 0
(interrupt disabled), DBA2 has no effect on IRQ or DBIA2. (See DBA2 and DBIA2.)
DDIS
2:8:4
0
Descrambler Disable. When control bit DDIS is a I, the receiver's descrambler circuit is disabled;
when a 0, the descrambler circuit is enabled.
OSR
0:F:4
-
Data Set Ready. When set to a 1 (ON), status bit DSR indicates that the modem is in the data
transfer state. When reset to a 0 (OFF), DSR indicates that the DTE is to disregard all signals
appearing on the interchange circuits-except Ai. DSR will switch to the OFF state when the modem
is in a test mode,
DTMF
0:9:5
0
DTMF Select. When the modem is configured for dialing mode, the modem will dial using DTMF
tones or pulses. When control bit DTMF is a I, the modem will dial using DTMF tones. When DTMF is
a 0, the modem will dial using pulses. The DTMF bit can be changed during the dialing process to
allow either tone or pulse dialing of consecutive digits. Dialing mode is selected by configuration code 81
in the Transmitter Configuration Register (TCONF). When in dialing mode, the data placed in the
Transmitter Data Register is treated as digits to be dialed. The number to be dialed must be
represented by two hexadecimal digits (e.g., if a 9 is to be dialed, then a 09 must be written to the
Transmitter Data Register). Also, see DBAO bit.
OTR
0:9:0
0
Data Terminal Ready. In V.32, V.22 bis, V.22 and Be1l212A modes, setting control bit DTR to a 1
initiates a handshake sequence, providing DATAO bit is a 1. If in answer mode, the transmitter will
immediately send answer tone.
Data Buffer Interrupt Active Chip 2. When the receiver chip 2 data buffer interrupt is enabled
(DBIE2 is a 1) and register 2:0 is written to by the DSP (DBA2 is set to a I), the receiver asserts IRQ
and sets DBIA2 to a 1 to indicate that DBA2 going to a 1 caused the interrupt. The host reading
register 2: 0 resets the DBIA2 bit to a 0 and clears the interrupt request due to DBA2. (See DBA2
and DBIE2.)
Dialing timing and power levels are host programmable in DSP RAM (Table 11).
In V.21, V.23 and Bell 103 modes, control bit DTR must be a 1 for the modem to enter data state
providing DATAO bit is a 1. If in answer mode, the transmitter will immediately send answer tone. In
these configurations, if controlled carrier is selected, then carrier is controlled by the RTS pin or bit
(see Table 2).
During the data mode, setting DTR to a 0 will cause the transmitter to turn off.
The DTR bit parallels the operation of the hardware DTR control input. These inputs are ORed by the
modem.
EARCO
0:15:0
0
Extended Automatic Rate Change Chip O. When control bits EARCO and EARCI are 1 (and also
ARCO and ARCI are I), then rate changes to the proprietary 12000 and 7200 TCM configurations are
allowed during the V.32 handshake. The modem will condition itself to transmit data at the highest
common rate negotiated during the V.32 handshake. These rates include the proprietary 12000 and
7200 TCM configurations, if both calling and answering modems support these configurations.
When EARCO and EARCI are 0 then rate changes are only allowed to standard CCITI V.32
configurations.
1-227
I
..
~
I
V.32 9600 bps Full-Duplex Modem
R9696DP
Table 8.
Mnemonic
Memory
Location
R9696DP Interface Memory Bit Definitions (Continued)
Default
Value
Name/Description
There are two methods for operating in the proprietary 12000 and 7200 TCM configurations. The first
is to set bits ARCO, ARC1, EARCO and EARC1 all to O. TCONF and RCONF should then be set for
the required configuration. The modem will then only be able to connect in the configuration selected.
Both calling and answering modems have to be configured the same way for a successful connection.
The second method is to set bits ARCO, ARC1, EARCO and EARC1 all to 1. TCONF and RCONF
should be set as desired, but in this case rate negotiati~n takes place during the V.32 handshake. Use
of this method allows fall-back or fall-forward retrains in 2400 bps steps from 12000 bps to 4800 bp' .
In order to accomplish rate changes to the proprietary configurations, the modem uses two bits in the V.32
16 bit rate sequence that are undefined in CCITI Recommendation V.32. These are bits B9and B10. (V.32)
EARC1
1: 15: 1
0
Extended Automatic Rate Change Chip 1. See EARCO. (V.32)
ECFZ
0:5:7
0
Echo Canceller Freeze. When control bit ECFZ is a 1, the updating of the echo canceller taps is
inhibited. (V.32)
ECSQ
0:5:6
0
Echo canceller Squelch. When control bit ECSQ is a 1, the echo canceller output is forced to zero. (V.32)
ECSQ, along with TXSQ, can be used to determine if the line has been dropped by the remote
modem. Many times due to the dropping of the line by the remote modem, a line mismatch occurs at
the near end modem's line interface. This causes a large increase in near end echo. Many errors
should be seen at this time. If this is the case, squelching both the echo canceller and the transmitter
should cause RLSO to go inactive. The host should first freeze the echo canceller (this is done in
case the line is not dropped) by setting ECFZ to a 1. Then set both ECSQ and TXSQ to a 1. If RLSO
drops, then the line was dropped by the remote modem and the near end modem should then be
disconnected from the line by the host. If RLSO does not drop, then the host should reset ECFZ,
ECSQ, and TXSQ to a 0 and issue a retrain, if applicable.
EQFZ
2:4:3
0
Equalizer Freeze. When control bit EQFZ is a 1, updating of the receiver's adaptive equalizer taps is
inhibited. (V.32, V.22 bis, V.22, Bell 212A)
EQRES
2:4:7
0
Equalizer Reset. When control bit EQRES is a 1, the receiver resets all of the adaptive equalizer's
taps to zero. When EQRES is a 0, the equalizer taps are updated normally by the receiver (chip 2).
(V.32, V.22 bis, V.22, Bell 212A)
Setting EQRES to a 1 effectively clamps the receiver. EQRES along with RLSOE can be used to
clamp the ~eceiver off and turn off the RLSO pin. An equalizer reset is automatically done for a brief
period of time at the beginning of the train·on-data state (TOO =1). Therefore, the host does not have
to manually set then clear this bit to reset the equalizer for line hits, etc., when TOO is active.
EQT2
2:4:6
0
Equalizer T/2 Spacing Select. When control bit EQT2 is a 1, the receiver's adaptive equalizer is T/2
fractionally spaced. When EQT2 is a 0, the equalizer is T spaced (T = 1 baud time). (V.32)
EXOSO
0:6:6
0
Extended Overspeed Chip O. When control bit EXOSO is a 1, Extended Overspeed mode is selected
in the transmitter async-to-sync converter. This bit must be configured appropriately before the
ASYNO bit changes from a 0 to a 1 for asynchronous mode. (V.32, V.22 bis, V.22, Bell 212A)
EXOS1
1 :6:6
0
Extended Overspeed Chip 1. When control bit EXOS1 is a 1, Extended Overspeed mode is selected
in the receiver sync-to·async converter. This bit must be configured appropriately before the ASYN1
bit changes from a 0 to a 1 for asynchronous mode. (V.32, V.22 bis, V.22, Bell 212A)
FECSQ
0:5:5
0
Far Echo canceller Squelch. When control bit FECSQ is a 1, the output of the far-end echo
canceller is forced to z!!ro; the near-end echo canceller continues to operate normally. (V.32)
Squelching the far end echo canceller should only be don" for testing purposes to manually
characterize the far end echo.
FED
1 :F:6
-
Fast Energy Detector. When status bit FED IS a 1, energy in the passband above the selected
receiver threshold has been detected (see RTH).
GTE
0:3:1
0
Guard Tone Enable. When set to a 1, control bit GTE causes the specified guard tone to be
transmitted (CCITI configurations only), according to the state of the GTS bit. Note: The guard tone
will only be transmitted by the answering modem. (V .22 bis)
GTS
0:3:0
0
Guard Tone Select. When set to a 1, control bit GTS selects the 550 Hz tone; when reset to a 0, GTE
selects the 1800 Hztone. The selected guard tone will be transmitted only when GTE is enabled. (V.22 bis)
HKABO
0:0:0
-
Handshake AbortChip O. When setto a 1 status bit HKABO indicates thatthe V.32 handshake has failed.
The transmitter remains in an abort state for 1 second after which HKABO is reset to 0 and the transmitter
returns to idle mode. While in the abort state the transmitter output is silent.
Normally this bit is set shortly after the HKAB1 bit with one exception. When the calling modem receives
rate sequence R3 (refer to CCITI Recommendation V.32) and ARCO is setto a 1, then if no common rates
are found or R3 is calling for a GSTN cleardown then HKABO will be set before HKAB1. (V.32)
1-228
V.32 9600 bps Full-Duplex Modem
R9696DP
Table 8.
Mnemonic
Memory
Location
R9696DP Interface Memory Bit Definitions (Continued)
Default
Value
Name/Description
HKABI
1:0:0
-
IFIX
2:4:2
1
Eye Fix. When control bit IFIX is ai, the serial diagnostic data at the EYEX and EYEY pins reflects
the Rotated Equalizer Output. When IFIX is a 0, the data on EYEX and EYEY is selected by the
addresses in X RAM ADDRESS and Y RAM ADDRESS registers in chip 2, respectively.
LLO
0:9:3
0
Leased Line Chip O. When control bit LLO is ai, the transmitter is in leased line operation; when 0,
the transmitter is in switched line operation. When LLO is set to a 1 and the CC bit is a 0, the modem
immediately sends scrambled ones and goes into data mode. (V.22 bis, V.22)
At 2400 bps it is recommended that a retrain be sent once in the data state to ensure that
synchronization occurs.
LLI
1 :9:3
0
Leased Line Chip 1. When control bit LL 1 is aI, the receiver is in leased line operation; when 0, the
receiver is in switched line operation. (V.22 bis, V.22)
L2ACT
0:7:5
0
Loop 2 Activate. When control bit L2ACT is ai, the receiver's digital output is connected to the
transmitter's digital input (locally activated remote digitalloopback) In accordance with CCITT
Recommendation V.54.
L3ACT
0:7:3
0
Loop 3 Activate. When control bit L3ACT is aI, the transmitter's analog output rs couplE!d to the
receiver's analog input through an attenuator (local analog loopback) in accordance with CCITT
Recommendation V.54. The modem may only be placed into analog loopback mode when in idle
mode (DTR signal is OFF and the DTR bit is 0). NEWCO and NEWCl must be set after any change in
the L3ACT bit. Set NEWCO to a 1 and wart until the modem resets it to a O. Wait 2 ms. Set the
NEWCl bit to a 1 and wart for the modem to reset it to a O. The loopback is then completed
(terminated) by setting the DTR signal ON (OFF) or the DTR bit to a 1 (0).
The transmitter's compromise equalizer should be disabled, by setting CEQ to a 0, during local
analog loopback.
MHLD
0:7:0
0
Mark Hold. When control bit MHLD is ai, the transmitter's digital input data is clamped to a mark.
When MHLD is a 0, the transmitter's input rs taken from TXD or TBUFFER (see TPDM).
NCIAO
0:IF:6
-
NCIAI
1 :IF:6
-
NEWCl Interrupt Active. When the new configuration chip 1 interrupt is enabled (NCIEI is a 1) and a
new receiver configuration is implemented (NEWCl rs reset to a 0), the DSP asserts IRQ and sets status
bit NCIA1 to a 1 to indicate that NEWCl going to a 0 caused the interrupt. NCIA1 and the interrupt
request due to NEWCl are cleared by the host writing a 0 into NCIEI. (See NEWCl and NCIE1.)
NCIEO
0:IF:2
0
NEWCO Interrupt Enable. When control bit NCIEO is a 1 (interrupt enabled), the transmitter will
assert IRQ and set NCIAO to a 1 when the NEWCO bit is reset to a 0 by the DSP. When NCIEO is a 0
(interrupt disabled), NEWCO has no effect on IRQ or NCIAO. (See NEWCO and NCIAO.)
NCIEI
1: IF:2
0
NEWCl Interrupt Enable. When control bit NCIEI is a 1 (interrupt enabled), the receiver will
assert IRQ and set NSIAI to a 1 when the NEWCl bit is reset to a 0 by the DSP. When NCIEI is a 0
(interrupt disabled), NEWCl has no effect on IRQ or NCIA1. (See NEWCl and NCIA1.)
NEWCO
O:IF:O
0
New Configuration Chip O. Control bit NEWCO must be set to a 1 by the host after the host changes
the configuration code in TCONF (0: 12), the L3ACT bit (0:7:3), the ORG bit (0:9:4) or the V21S0 bit
(0: 8: 5). This informs the transmitter to implement the new transmitter configuration. The DSP resets
the NEWCO bit to a 0 when the configuration change is implemented. A configuration change can
also cause IRQ to be asserted. (See NCIEO and NCIAO.)
NEWCl
1 :IF:O
0
New Configuration Chip 1. Control bit NEWCl must be set to a 1 by the host after the host changes
the configuration code in RCONF (1 : 12), the L3ACT bit (0: 7: 3), RTH (1 : 13: 2-3), the ORG bit (0: 9: 4)
or the V21S1 bit (1 :8:5). This informs the receiver to implement the new receiver configuration and/or
the new receiver threshold. The DSP resets the NEWCl bit to a 0 when the change is implemented. A
configuration/receiver threshold change can also cause IRQ to be asserted. (See NCIEI and NCIA1.)
NEWSO
0:IF:3
-
New Status Chip O. When set to ai, status brt NEWSO indicates that one or more status bits located
in registers OE or OF have changed state, or a DSP RAM read or write has been completed, in the
transmitter. This bit can be reset to a 0 only by the host. The host may mask the effect of individual
status bits upon NEWSO by writing a mask value to DSP RAM. When set to aI, this bit can cause
IRQ to be asserted. (See NSIEO and NSIAO.)
NEWSI
1 :IF:3
-
New Status Chip 1. When set to aI, status bit NEWSI indicates that one or more status bits located
in registers OA to OF have changed state, or a DSP RAM read or write has been completed, in
receiver DSP chip 1. This bit can be reset to a 0 only by the host. The host may mask the effect of
individual status bits upon NEWSI by Writing a mask value to DSP RAM. When set to ai, this bit can
cause IRQ to be asserted. (See NSIEI and NSIA1.)
Handshake Abort Chip 1. When set to ai, status bit HKABI indicates that the V.32 handshake has failed.
At the same time an abort code is written into ABCODE (see ABCODE). The receiver remains in an abort
state for 0.5 second after which HKABI is reset to 0 and the receiver returns to idle mode. (V.32)
NEWCO Interrupt Active. When the new configuration chip 0 interrupt is enabled (NCIEO is a 1) and
a new transmitter configuration is implemented (NEWCO is reset to a 0), the DSP asserts IRQ and sets
status bit NCIAO to a 1 to indrcate that NEWCO going to a 0 caused the interrupt. NCIAO and the interrupt
request due to NEWCO are cleared by the host writing a 0 into NCIEO. (See NEWCO and NCIEO.)
1-229
R9696DP
V.32 9600 bps Full-Duplex Modem
Table. 8.
Mnemonic
Memory
Location
R9696DP Interface Memory Bit Definitions (Continued)
Default
Value
Name/Description
NEWS2
2:1F:3
-
NSIAO
0:1F:7
-
NSIA1
1: 1F:7
-
NSIA2
2:1F:7
-
NSIEO
0:1F:4
0
NEWSO Interrupt Enable Chip O. When control bit NSIEO is a 1 (interrupt enabled), the transmitter will
assert IRQ and set NSIAO to a 1 when NEWSO is set to a 1 by the DSP. When NSIEO is a 0
(interrupt disabled), NEWSO has no effect on IRQ or NSIAO. (See NEWSO and NSIAO.)
NSIE1
1 :1F:4
0
NEWS11nterrupt Enable Chip 1. When control bit NSIE1 is a 1 (interrupt enabled), the receiver will assert
IRQ and set NSIA1 to a 1 when NEWS1 is set to a 1 by the DSP. When NSIE1 is a 0 (interrupt
disabled), NEWS1 has no effect on IRQ or NSIA1. (See NEWS1 and NSIA1.)
NSIE2
2:1F:4
0
NEWS21nterrupt Enable Chip 2. When control bit NSIE2 is a 1 (interrupt enabled), the receiver will assert
IRQ and set NSIA2 to a 1 when NEWS2 is set to a 1 by the DSP. When NSIE2
is a 0 (interrupt disabled), NEWS2 has no effect on IRQ or NSIA2. (See NEWS2 and NSIA2.)
NV25
0:9:7
0
No V.25 Answer Tone. When control bit NV25 is a 1, the modem will not transmit the 2100 Hz CCITT answer
tone when a handshake sequence is initiated and the modem is in answer mode. (V.32, V.22 bis, V.22,
V.21, V.23)
ORG
0:9:4
1
Orlglnale. When conflgurallon bit ORG IS a 1, the modem IS In originate mode; when a 0, the modem is
in answer mode. Sineethis is a configuration bit, the NEWCO and NEWC1 bits must be set after any change
in the ORG bit. Set NEWCO to a 1 and wait until the modem resets it to a O. Wait 2 ms. Set the NEWC1
bit to a 1 and wait for the modem to reset it to a O.
PENO
0:6:3
0
Parity Enable Chip O. When control bit PENO IS a 1, panty is enabled in asynchronous mode in the
transmitter. This bit must be configured appropriately before the ASYNO bit changes from a 0 to a 1 for
asynchronous mode. (V.32, V.22 bis, V.22, Bell 212A)
PEN1
1 :6:3
0
Parity Enable Chip 1. When control bit PEN1 is a 1, parity is enabled in asynchronous mode in the receiver.
This bit must be configured appropriately before the ASYN1 bit changes from a 0 to a 1 for asynchronous
mode. (V.32, V.22 bis, V.22, Bell 212A)
RA
0:7:1
0
Relay Activate. When control bit RA is a 1, the output OHRC is activated (low); when a 0, the OHRC
output is off (high).
RBUFFER
1 :0:0-7
-
Receive Buffer. The host obtains channel data from the modem receiver in the parallel data mode by reading
a data byte from the RBUFFER. The data is divided on the baud boundaries shown under TBUFFER. The
RBUFFER reflects the received data when the RSEQ bit is a O.
RCONF
1:12:0-7
74
Receiver Configuration. The RCONF control bits select one of the following receiver configurations:
New Status Chip 2. When set to a 1, status bit NEWS2 indicates that the RI status bit in register OF has
changed state, or a DSP RAM read or write has been completed, in receiver DSP chip 2 This bit can be
reset to a 0 only by the host. The host may mask the effect of the RI status bit upon NEWS2 by writing a
mask value to DSP RAM. When set to a 1, this bit can cause IRQto be asserted. (See NSIE2and NSIA2.)
NEWSO Interrupt Active Chip O. When the new status interrupt chip 0 is enabled (NSIEO is a 1) and a
change of status occurs (NEWSO is set to a 1), the transmitter asserts IRQ and sets status bit NSIAO
to a 1 to indicate that NEWSO going to a 1 caused the interrupt. NSIAO and the interrupt request due to
NEWSO are cleared when the host writes a 0 to NEWSO. (See NEWSO and NSIEO.)
NEWS1 Interrupt AClive Chip 1. When the new status Interrupt chip ~ enabled (NSIE1 is a 1) and a
change a status occurs (NEWS1 is set to a 1), the receiver asserts IRQ and sets status bit NSIA1 to
a 1 to indicate that NEWS1 going to a 1 caused the interrupt. NSIA1 and the interrupt request due to NEWS1
are cleared when the host writes a 0 to NEWS1. (See NEWS1 and NSIE1.)
NEWS2 Interrupt Active Chip 2. When the new status interrupt chip 2 is enabled (NSIE2 is a 1) and a
change of status occurs (NEWS2 is set to a 1), the receiver asserts IRQ and sets status bit
NSIA2 to a 1 to indicate that NEWS2 going to a 1 caused the interrupt. NSIA2 and the interrupt request
due to NEWS2 are cleared when the host writes a 0 to NEWS2. (See NEWS2 and NSIE2.)
,
Mode
Data Rate
RCONF(Hex)
V.32TCM
V.32TCM
V.32
V.32
V.32TCM
V.22 bis
V.22
V.22
V.21
Bell 212A
Bell 103
V.23
V.23
V.23
12000
9600
9600
4800
7200
2400
1200
600
0-300
1200
0-300
1200
600
75
72
74
75
71
78
84
52
51
AO
62
60
A4
A2
AI
1-230
V.32 9600 bps Full-Duplex Modem
R9696DP
Table 8. R9696DP Interface Memory Bit Definitions (Continued)
Mnamonlc
Memory
locatIon
Default
Value
NamelDeacriptlon
ROL
0:7:6
o
Remota Digital Loopback. When set to a 1, control bit ROL causes the modem to initiate a request
for the modem to go Into digitalloopback; RXO is clamped to a mark and the ers bit and CTS signal
will be reset until the loop is established. The TM bit is not set in this case, since the local modem
initiated the request. (V.22 bis)
ROLE
1 :7:7
1
Remote DIgital Loopbeck ReepolI88 Enable. When sat to a 1, control bit ROLE enables the modem
to respond to another modem's remote digltalloopback request, thus going into loopback. When this
occurs, the modem clamps AXO to a mark; resets the CTS, OSR and RLSO bits to a 0, and turns the
CTS, OSR and RLSO signals to a logic 1. The TM bit is set to a 1, to inform the host of the test status.
When the ROLE bit is a 0, no response will be generated. (V.22 bis)
RI
2:F:3
-
RIng Indicator. When sat to a 1, status bit RI indicates that a ringing signal is being detected.
Ringing Is detected If pulses are present on the J!ID input in the 15 Hz - 66 Hz frequency range. The
RI bit follows the ringing signal with a 1 during the ON time and a 0 during the OFF time coincident
with Ai output signal. The decision bounds are host programmable In OSP RAM.
The bit is valid only when the receiver OATA2 bit (2:9:2) is a O.
RLSO
1 :F:7
-
RLSOE
1:3:4
1
RLSD Enable. When control bit RLSOE is a 1, the RLSO pin reflects the RLSO bit. When RLSOE is
a 0, the RLSO pin is clamped to a 1 (OFF condition) regardless of the state of the RLSO bit. (V.22 bis)
RSEQ
1:C:0
0
Rata Sequence ReceiVed. When status bit RSEQ is a 1, the 16-bit rate sequence included In the
CCITT V.32 start-up procedure has been received and the 16-bit rate sequence word is available In
RSEQM (1: 1) and RSEQL (1 :0). (V.32)
RSEQL
1:0:0-7
-
Rate Sequence LSB. When the RSEQ bit is a 1, register 1 : 0 holds the least significant byte of the
16-blt V.32 rate sequence word (RSEQL) received by the modem. When the RSEQ bit is a 0, register
1:0 holds the received data (see RBUFFER). (V.32)
RSEQM
1:1:0-7
-
Rata Sequence MSB. When the RSEQ bit is a 1, register 1 : 1 holds the most significant byte of the
16-bit V.32 rate sequence word (RSEQM) received by the modem. When the RSEQ bit is a 0, register
1 :11s not used. (V.32)
RSPA
2:4:4
1
Receiver SIgnal Point Activate. When control bit RSPA is a 1, the receiver writes the received
signal point coordinates, after the decision processing, Into registers RSPY (2: 1) and RSPX (2:0).
When RSPA is a 0, RSPY and RSPX do not contain the signal point coordinates. (V.32, V.22 bls,
V.22, Bell 212A)
RSPX
2:0:0-7
Receiver Signal Point X. RSPX holds the X (in-phase) coordinate of the received signal point. RSPX
is valid only when RSPA is a 1. (See RSPA.) (V.32, V.22 bis, V.22, Bell 212A)
RSPY
2:1:0-7
Receiver Signal Point Y. RSPY holds the Y (quadrature) coordinate of the received signal pOint.
RSPY is valid only when RSPA Is a 1. (See RSPA.) (V.32, V.22 bis, V.22, Bell 212A)
RTDET
1:E:7
Retrain Detector. When set to a 1, status bit RTOET indicates that a training sequence has been
detected. (V.32 and V.22 bis) This bit parallels the operation of the following:
Racelved Una SIgnal Detector. When status bit RLSO is a 1, the receiver has finished receiving the
training sequence or has turned on due to detected energy above threshold, and is receiving data.
RLSO is a 0 when the receiver Is in the idle state and during the reception of a training sequence.
Mode
V.32 Originate
V.32 Answer
V.22 bis
RTH
1:13:2,3
o
Detector Bit
ACOET
MOET
S10ET
Receiver Threshold. The RTH control bits select the receiver energy detector threshold according to
the follOWing codes:
RLSDON
-43dBm
-33dBm
-'26 dBm
-16dBm
RTH
o
1
2
3
1-231
RLSDOFF
-4BdBm
-38dBm
-31 dBm
-21 dBm
V.32 9600 bps Full-Duplex Modem
R9696DP
Table 8. R9696DP Interface Memory Bit Definitions (Continued)
Mnemonic
RTRN
Memory
Location
0:8:1
Default
Value
0
Name/Description
Ratraln. When the modem is in V.32 orV.22 bls data mode, and control bn RTRN Is set to a I, a
retrain sequence is innlaled. RTRN resets to a 0 as soon as the Initiation Is acknowledged.
Fall-back or filII-forward retrains may be ~ccompllshed as followa:
Change the Transmitter Configuration Register (TCONF) to the required configuration code. Note that
the mode cannot be changed, only the data rate wHhin a given mode. (In other words, it is not possible
to fall-ba~k from V.32 to V.22 bls.) Do not set the NEWC bits in either the transmitter (NEWCO) or
receiver chip 1 (NEWC1) and do not change the receiver configuration register (RCONF) code.
Ensure that ARCO and ARCI bits are set to a 1. If n Is desired to fall·back or fall-forward to one of the
proprietary V.32 configurations, then aI.so ensure that EARCO and EARCI are set to a 1. Finally, set
the RTRN bit to a 1. If the remote modem can operate at the requested rate, the receiver configuration
will be changed by the modem to reflect the new rate after the retrain 18 completed. If the remote
modem cannot operate at the new rate, then no rate change will take place during the retrain and the
transmitter configuration register will automatically revert back to Hs original configuration.
If the modem reconfigures from V.22 bis 2400 bps to V.22 1200 bps during a handshake or as a result
of a retrain, the TCONF and RCONF registers will contsin the hex number 82.
RTS
0:8:0
0
When control bit RTS is a I, the modem transmits any data on TXO when CTS becomes active.
In V.2?, bis, V.22, V.23, V.21, and Bell 103 constant carrier and V.32 modes, RTS controls data
transmission and OTR controls the carrier. For ease of use, RTS can be turned ON et the same time
as OTR.
In V.22 bls controlled carrier mode, RTS Independently controls the carrier when OTR Is ON. When
RTS Is turned ON, the modem then transmits 270 ms of scrambled Is before turning CTS ON.
In V.21, V.23 and Bell 103 controlled carrier modes, RTS independently controls the carrier when
OTR Is ON. When RTS Is turned ON, CTS is t\lrned ON per Table 2.
The RTS bit parallels the operation of the RTS herdware control input. These Inputs are ORed by the
modem. (See descriptions of CTS and OTR bits)
SAOET
1:0:2
-
Scrambled Altematlng Sequence Detector. When set to a I, status bit SAOET Indicates that
scrambled aHernating data Is being received. This bH Is intended to be used for the automatic rate
change sequence. (See ARCO and ARC1.) This bit is reset to 0 at the end of the alternating
sequence. (V.22 bis)
SCRI
1:0:4
-
ScnunbIed Ones Detector. When set to a I, status bit SCRI indicates that V.22 bis scrambled Is have been
detected during handshake. This bit is reset to 0 at the end of the scrambled Is sequence. (V.22 bis)
SOET
I:C:3
-
S Detector. When set to a I, status bit SOET indicates that a V.32 S sequence hes been detected. This
bit Is reset to a 0 by the modem at the end of the S sequence. (V.32)
SOlS
0:3:2
0
Scramblsr Disable. When control bit SOlS is a I, the transmitter scrambler clrcun Is disabled; when a
0, the scrambler circuit is enabled. (V.32,V.22 bls.)
SNOET
I:C:2
-
S Negative Detector'. When set to a I, status bit SNDET indicates that a V.32
been detected. This bit Is reset to a 0 at the end of the S sequence. (V.32)
SPEED
1 :E:0-2
-
Speed Indication. The SPEED status bHs Indicate the receiver's date rate at the completion of a handshaka.
Data Rate
SPEED (Hex)
0
1
2
3
0-300
eoo
1200
2400
Data Rate
4800
9600
12000
S sequence
has
SPEED (Hex)
4
5
6
SOOIS
1:2:6
0
Squarar Disable (Tone Detector C). When control bit SOOIS is a I, the squarer in front of tone
dectector C is disabled; when a 0, the squarer is enabled.
STeo
0:6:2
0
Stop Bit Number Chip O. When control bit STBO Is a 0, one stop bit is selected in asynchronous mode In
the transmitter; when a I, two stop bits are selected. This bit must be configured appropriately before the
ASYNO bit changes from a 0 to a 1 for asynchronous mode. (V.32, V.22 bls, V.22, Bell 212A)
STBI
1:6:2
0
Stop Bit Number Chip 1. When control bit STBI is a I, one stop bit is selected in asynchronous mode
in the receiver; when a I, two stop bits are selected. This bit must be configured appropriately before the
ASYNI bit changes from a 0 to a 1 for asynchronous mode. (V.32, V.22 bis, V.22, Bell 212A)
1-232
V.32 9600 bps Full.Ouplex Modem
R96960P
Table 8.
Mnemonic
STOFF
Memory
Location
0:5: 1
R9696DP Interface Memory Bit Definitions (Continued)
Default
Value
0
S1DET
1 :D:5
-
TBUFFER
0:0:0-7
00
Name/Description
Soft Turn Off. When control bit STOFF is a 1, the transmitter sends a tone at the end of a transmission
in V.23, V.21 and Bell 103 configurations. This tone is detected as a mark frequency at the receiver.
The soft turn off tone frequencies and durations are as follows:
Configuration
Frequency
(Hz)
Duration
(mS)
V.23/1200
V210rig.
V21 Ans.
Bell 103 Orig.
Bell 103 Ans.
900
880
1550
1370
2325
7
30
30
30
30
SI Detector. When set to aI, status bit S1 DET indicates that a V.22 bis SI sequence has been
detected. This bit is reset to a 0 by the modem at the end of the SI sequence. (V.22 bis)
Transmitter BufferiTransmltter Signal Point X. The host conveys output data to the transmitter in
the parallel mode by writing a data byte to the TBUFFER. Parallel data mode is available only in
synchronous mode. The data is transmitted bit 0 first and is divided on Ihe following baud boundaries:
Bits
Configuration
7
V.32 TCM 12000
-
6
1
5
Baud 1
V.3296OO
Baud 1
Baud 3
V.32 TCM 7200
-
1
1
1
0
1 Baud 0
Baud 0
1
Baud 1
Baud 3
BaudO
Baud 2
Baud 1
1
Baud 0
1
Baud 0
8 bit data
Be1l212A 1200
74
Baud 1
Baud 1
Baud 3
1
Baud 2
V.21
0:12:0-7
1 2 1
Baud 0
Baud 0
Baud 2
1
V.22600
TCONF
3
BaudO
-I
V.22 bis 2400
V.221200
4
I - I - I
V.32 TCM 9600
V.324800
1
Baud 1
8 bit data
Transmitter Configuration. The TCONF control bits select one of the following transmitter configurations:
Mode
V.32TCM
V.32
V.32
V.32
V.32TCM
V.22 bis
V.22
V.22
V.21
Bell 212A
Bell 103
V.23
V.23
V.23
Single Tone
Dual Tone
Dialing
Data Rate
TCONF(Hex)
12000
9600
9600
4800
7200
2400
1200
600
0-300
1200
0-300
1200
600
75
72
74
75
71
78
84
52
51
AO
62
-
60
A4
A2
AI
80
83
81
When single tone or dual tone mode is selected the modem
transmits one or two tones respectively. The tone frequencies are
host programmable in DSP RAM. Single tone transmit uses the Dual
Tone 1 frequency and level.
1-233
R9696DP
V.32 9600 bps Full-Duplex Modem
Table 8. R9696DP Interface Memory Bit Definitions (Continued)
Mnemonic
Memory
Location
Default
Value
Name/Description
TDAE
1 :2:7
1
Tone Detector A Enable. When control bit TDAE is a I, tone detector A is enabled; when a 0, tone
detector A is disabled. This bit only has an effect when DATAl bit is a 1 and the receiver is in
asynchronous mode or V.32 12000 bps.
TLVL
0: 13:4-7
0
Transmit Le';el. The TLVL code selects 'the transmitter analog output level at the TXA pin as follows:
TLVL Code
(Hex)
TX Output Level
(dBm ± 0.5 dB)
0
-0.5
-1.5
1
2
-2.5
3
-3.5
4
-4.5
5
-5.5
-6.5
6
7
-7.5
8
-8.5
-9.5
9
-10.5
A
B
-11.5
C
-12.5
D
-13.5
E
-14.5
F
-15.5
The host can fine tune the transmit level to a value lying within a 1 dB step by changing a value in
DSP RAM.
TM
0:F:2
-
TOD
2:4:1
0
TONEA
1 :B:7
-
TONEB
1 :B:6
-
TONEC
1 :B:5
-
TPDM
0:8:6
0
Transmitter Parallel Data Mode. When control bit TPDM is a I, the transmitter accepts data for
transmission from the TBUFFER (0: 0) rather than the TXD input.
TSPA
0:5:0
0
Transmitter Signal Point Activate. When control bit TSPA is a I, the transmitter uses the signal
points X and Y directly from registers TSPX (0:0) and TSPY (0: 1). The transmitter data input,
TBUFFER and TXD, are ignored. When TSPA is a 0, the transmitter accepts data for transmission
from the TBUFFER or the TXD input.
TSPX
0:0:0-7
00
Transmitter Signal Point X. When TSPA is a I, register 0: 0 is used to transmit the in-phase (X)
coordinate of the transmitted signal point (TSPX). (V.32, V.22 bis, V.22, Bell 212A.)
TSPY
0: 1 :0-7
00
Transmitter Signal Point Y. When TSPA is a I, register 0: 1 is used to transmit the quadrature
(Y) coordinate of the transmitted signal point (TSPY). (V.32, V.22 bis, V.22, Bell 212A.)
TXCLK
0:13:0,1
0
Transmit Clock Select. The TXCLK control bits deSignate the origin of the transmitter data clock.
Test Mode. When set to a I, status bit TM indicates that the modem has completed the handshake
and is in the Loop 3 or RDL test mode. (V.22 bis)
Train On Data. When set to a I, control bit TOD enables the train-on..cfata algorithm to converge the
equalizer if the signal quality degrades. A BER of 10-3 for 0.5 seconds initiates the traln-on-data.
When TOD Is a I, the modem is still able to recognize an incoming training sequence. (V.32.)
Tone A Detected. When set to a I, status bit TONEA indicates that energy is present on the line
within the tone detector A passband and above its threshold. The bandpass filter coefficients are host
programmable in DSP RAM.
Tone B Detected. When set to a I, status bit TONEB indicates that energy is present on the line
within the tone detector B passband and above its threshold. The bandpass filter coefficients are host
programmable in DSP RAM.
Tone C Detected. When set to a I, status bit TONEC indicates that energy is present on the line
within the tone detector C passband and above its threshold. The bandpass filter coefficients are host
programmable in DSP RAM. The TONEC filter is preceded by a squarer in order to facilitate detection
of difference tones. This squarer may be disabled with the SODIS bit (see SODIS bit).
TXCLK
Transmit Clock
0
Internal
2
External (XTCLK)
3
Slave (RDCLK)
When the external clock is chosen. the host supplied clock must be connected to the XTCLK input
pin. The external clock will then be reflected at the TDCLK output pin.
When the slave clock is chosen, the transmitter clock (TDCLK) is phase locked to the receiver clock (RDCLK).
1-234
R9696DP
V.32 9600 bps Full-Duplex Modem
Table 8.
Mnemonic
Memory
Location
R9696DP Interface Memory Bit Definitions (Continued)
Default
Value
Name/Descrlptlon
TXSQ
0:5:4
0
Transmitter Squelch. When control bit TXSQ is a I, the transmitter analog output is squelched. All other
transmitter functions continue as normal. When TXSQ is a 0, the transmitter output functions normally.
This bit Is useful in 2-wire configurations where it is necessary to measure the spectrum and transmit
level of a transmitter. Setting the TXSQ bit to a 1 turns off the transmitter so that only one of the two
carriers Is present. After TXSQ is set to a 0, a retrain should be sent to reestablish the data transfer.
UIDET
1:0:3
-
Unscrambled ,. Detector. When set to a I, status bit UIDET indicates that V.22 bis unscrambled Is
sequence has been detected. This bit is reset to a 0 by the modem at the end of the unscrambled 1s
sequence. UIDET is not active when DATAl is a O. (V.22 bls)
V21
I:B:2
-
V.21 Mark Detector. When set to a I, status bit V21 indicates that a V.21 mark frequency was
detacted during a handshake. (V.21)
V21S1
1:8:5
·0
V21 Synchronous Chip O. When configuration bit V21S1 is a 1 and the Receiver Configuration
(RCONF) has been set for V.21, then V21 Synchronous mode Is selected in the receiver.
Synchronous data is output in both serial and parallel form. A synchronous clock is provided on the
RDCLI< pin. When V21S1 is a 0 and the Receiver Configuration (RCONF) has been set for V.21, then
V.21 Asynchronous mode is selected in the receiver. Since V21S1 is a configuration bit, then NEWCl
must be set for any changes in this bit to take effect.
V21SO
0:8:5
0
V21 Synchronous Chip 1. When configuration bit V21 SO Is a 1 and the Transmitter Configuration
(TCONF) has been set for V.21 , then V21 Synchronous mode is selected in the transmitter.
Synchronous data may be applied In either serial or parallel form. A synchronous clock is provided on
the TDCLK pin. When V21SO Is a 0 and the Transmitter Configuration (TCONF) has been set for V.21,
then V.21 Asynchronous mode is selected in the transmitter. Since V21SO is a configuration bit, then
NEWCO must be set for any changes in this bit to take effect.
WDSZO
0:6:0,1
0
Date Word Size Chip O. The WDSZO field sets the number of data bits per character in asynchronous
mode in the transmitter as follows (V.32, V.22 bis, V.22, Bell 212A):
Date Bite/Character
WDSZO(Hex)
5
0
1
6
7
2
8
3
This bit must be configured appropriately before the ASYNO bit changes from a 0 to a 1 for
asynchronous mode.
WDSZl
1 :6:0,1
0
Data Word Size Chip 1. The WDSZl field sets the number of data bits per character in asynchronous
mode in the receiver as follows (V .32, V.22 bis, V.22, Bell 212A):
Dele Bite/Character
WDSZl (Hex)
5
0
1
6
7
2
6
3
This bit must be configured appropriately bvefore the ASYNI bit changes from a 0 to a 1 for
asynchronous mode.
XACCO
0:10:7
0
X RAM Accesa Enable Chip O. When control bit XACCO is a I, DSP chip 0 accesses the X RAM
associated with the address in XADDO and the XCRO bit. XWTO determines if a read or wllte is
performed. The DSP resets XACCO to a 0 upon RAM access completion.
XACCI
1:10:7
0
X RAM Accesa Enable Chip 1. When control bit XACCI is a I, DSP chip 1 accesses the X RAM
associated with the address in XADDI and the XCRI bit. XWTl determines if a read or write is
performed. The DSP resets XACCI to a 0 upon RAM access completion.
XACC2
2:10:7
0
X RAM Acce.. Enable Chip 2. Whljln control bit XACC2 is a I, DSP Chip 2 accesses the X RAM
associated with the address in XADD2 and the XCR2 bit. XWT2 determines if a read or write is
performed. The DSP resets XACC2 to a 0 upon RAM access completion.
XADDO
0:IC:0-7
00
X RAM Addra.. Chip O. XADDO contains the X RAM address used to access DSP chip D's X Data
RAM (XCRO = 0) or X Coefficient RAM (XCRO = 1) via the X RAM Data LSB and MSB registers
(0: 18 and 0: 19, respectively) (See Table 9.)
XADDI
1:IC:0-7
00
X RAM Addre.. Chip 1. XADDI contains the X RAM address used to access DSP chip l's X Data
RAM (XCRI = 0) or X CoeffiCient RAM (XCRI = 1) via the X RAM Data LSB and MSB registers
(1: 18 and 1: 19, respactlvely) (See Table 9.).
XADD2
2:1C:0-7
00
X RAM Add..... Chip 2. XADD2 contains the X RAM address used to access DSP chip 2's X Data
RAM (XCR2 - 0) or X Coefficient RAM (XCR2 = 1) via the X RAM Data LSB and MSB registers
(2:18 and 2: 19, respectively). (See Table 9.)
1-235
V.32 9600 bps Full-Duplex Modem
R9696DP
Table 8.
Mnemonic
Memory
Location
R9696DP Interface Memory Bit Definitions (Continued)
DefauH
Value
NamelDeacrtptlon
XCRDO
0:10:2
0
X RAM Contlnuoue Reed Chip O. When comrol bH XCRDO is a 1, bits XACCO and XWTO are
overridden and an X RAM read from chip 0 is performed every sample from the location addressed by
XAODO (see OSP RAM Access).
XCR01
1:10:2
0
X RAM Continuous Read Chip 1. When comrol b~ XCR01 is a 1, bits XACC1 and XWT1 are
overridden and an X RAM read from chip 1 is performad every sample from the location addressed by
XA001 (see OSP RAM Access).
XCR02
2:10:2
0
X RAM Continuous Read Chip 2. When comrol bit XCR02 is a 1, bits XACC2 and XWT2 are
overridden and an X RAM read from chip 2 Is performed every baud from the location addressed by
XA002 (sse OSP RAM Access).
XCRO
0:10:0
0
X Coefficient RAM Select Chip O. When control bit XCRO is a 1, XAODO applies to OSP chip O's
X Coefficlem RAM. When XCRO is a 0, XAOOO applies to the X Oats RAM. This bit must be set
according to the desired RAM address (Table 9).
XCR1
1:10:0
0
X Coefficient RAM Select Chip 1. When control bit XCR1 Is a 1, XA001 applies to OSP chip 1's
X Coefficiem RAM. When XCR1 Is a 0, XA001 applies to the X Oats RAM. This bit must be set
according to the desired RAM address (Table 9).
XCR2
2:10:0
0
X Coefficient RAM Select Chip 2. When CCII)trol bit XCR2 is a 1, XA002 applies to OSP chip 2's
X Coefficient RAM. When XCR2 Is a 0, XA002 applies to the X Data RAM. This bit must be set
according to the dllllired RAM address (Table 10).
XOALO
0:18:0-7
00
X RAM DatIl LSB Chip O. XOALO is the least slgnlficam byte of the 16-blt X RAM data word ussd In
reading or writing X RAM locations In OSP chip O.
XOAL1
1:18:0-7
00
X RAM DatIl LSB Chip 1. XOAL 1 is the least significam byte of the
reading or writing X RAM locations In OSP chip 1.
XOAL2
2:18:0-7
00
X RAM DatIl LSB Chip 2. XOAL2 Is the least signlflcam byte of the 16-blt X RAM data word used in
reading or writing X RAM locations in OSP chip 2.
XOAMO
0:19:0-7
00
X RAM Dati MSB Chip O. XOAMO Is the most slgnlflcam byte of the 16-blt X RAM data word used In
reading or writing X RAM locations In OSP chip O.
XDAM1
1:19:0-7
00
X RAM DatIl MSB Chip 1. XDAM1 is the moat significant byte of the 16-bit X RAM dats word used In
reading or wr~ing X RAM locations In DSP chip 1.
XDAM2
2:19:0-7
00
X RAM DatI MSB Chip 2. XDAM2 Is the most Significant byte of the 16-blt X RAM data word used in
reading or writing X RAM locations In DSP chip 2.
XWTO
0:10:1
0
X RAM Write Chip O. When XWTO Is a 1 and XACCO Is set to a 1, DSP chip 0 copies data from the X RAM
Data registers (0: 18 and 0: 19) into the X RAM location addressed by XADDO and XCRO. When comrol
bit XWTO Is a 0 and XACCO Is set to a 1, DSP chip 0 reads X RAM at the location addressed by
XADDO and XCRO. The read data is stored imo the X RAM Data registers '(0: 18 and 0: 19).
XWT1
1:10:1
0
X RAM Wrfte Chip 1. When XWT1 Is a 1 and XACC1 Is sat to a 1, DSP chip 1 copies dats from the
X RAM Data registers (1: 18 and 1: 19) Into the X RAM location addressed by XADD1 and XCR1.
When comrol bit XWT1 Is a 0 and XACC1 Is set to a 1, DSP chip 1 rseds X RAM at the location
addressed by XADD1 and XCR1. The read data is stored into the X RAM Data registers (1 : 18
and 1 :19).
XWT2
2:10:1
0
X RAM Wrfte Chip 2.When XWT2 Is a 1 and XACC2 Is set to a 1, DSP chip 2 copies data from the
X RAM Data registers (2: 18 and 2: 19) into the X RAM location addressed by XADD2 and XCR2.
When comroJ bit XWT2ls a 0 and XACC2 is set to a 1, the DSP chip 2 readsX RAM at the location addressed
by XADD2 and XCR2. The read dats Is stored In the X RAM Data registers (2: 18 and 2: 19).
VACCO
0:1B:7
0
V RAM Acee. Enable Chip O. When control bit VACCO is a 1, DSP chip 0 accesses the V RAM
asSOCiated with the address in VADDO and the VCRO bit. YWTO determines if a read or write is
performed. The DSP resets VACCO to a 0 upon RAM access completion.
VACC1
1 :1B:7
0
V RAM Access Enabla Chip 1. When control bit VACC11s a 1, DSP chip 1 accesses the V RAM
essoclated with the address In VADD1 and the VCR1 bit. YWT1 determines If a read or write Is
performed. The DSP ressts VACC1 to a 0 upon RAM access completion.
VACC2
2:1B:7
0
Y RAM Ac_ Enable Chip 2. Wh.n comroJ bit YACC2 is a 1, DSP chip 2 accesses the V RAM
essoclated with the address In YADD2 and the YCR2 bit. YWT2 determines if a read or write is
performed. The DSP sets YACC2 to a 0 upon RAM access completion.
YADDO
0:1A:0-7
00
Y,RAM Addre. Chip O. YADDO comains the Y RAM address used to access DSP chip O's V Data
RAM (VCRO - 0) or Y Coefficient RAM (VCRO = 1) via the Y RAM Data LSB and MSB registers
(0: 16 and 0: 17, respectively). (See Table 9.)
1-236
16-b~
X RAM data word used In
V.32 9600 bps Full-Duplex Modem
R9696DP
Table 8.
R9696DP Interface Memory Bit Definitions (Continued)
Memory
Location
Default
Value
YADDI
1:IA:0-7
00
V RAM Address Chip 1. YADDI contains the Y RAM address used to access DSP chip l's Y Data
RAM (yCRI = 0) or Y Coefficient RAM (YCRI = 1) via the Y RAM Data LSB and MSB registers
(1 :16 and 1: 17, respectively). (See Table 9.)
YADD2
2:1A:0-7
00
V RAM Address Chip 2. YADD2 contains the Y RAM address used to access DSP chip 2's Y Data
RAM (yCR2 = 0) or Y Coefficient RAM (yCR2 = 1) via the Y RAM Data LSB and MSB registers
(2: 16 and 2: 17, respectively). (See Table 9.)
YCRDO
0:IB:2
0
V RAM Continuous Read Chip O. When control bit YCRDO is a I, b~s VACCO and YWTO are
overridden and a Y RAM read from chip 0 is performed every sample from the location addressed by
YADDO (see DSP RAM Access).
YCRDI
1:IB:2
0
V RAM Continuous Read Chip 1. When control bit YCRDI is a I, bits VACCI and YWTl are
overridden and a Y RAM read from chip 1 is performed every sample from the location addressed by
YADDI (see DSP RAM Access).
YCRD2
2:1B:2
0
V RAM Continuous Read Chip 2. When control bit YCRD2 is a I, bits YACC2 and YWT2 are
overridden and a Y RAM read from chip 2 is performed every baud from the location addressed by
YAOD2 (see DSP RAM Access).
YCRO
O:IB:O
0
V Coefficient RAM Select Chip O. When control bit VCRO IS a I, YADDO applies to DSP chip O's
Y Coefficient RAM. When YCRO is a 0, YADDO applies to the Y Data RAM. This bit must be set
according to the desired RAM address (fable 9).
YCRI
1:IB:O
0
V Coefficient RAM Select Chip 1. When control b~ YCRI is a I, VADDI applies to DSP chip l's
Y Coefficient RAM. When YCRI IS a 0, YADDI applies to the Y Data RAM. This bit must be set
according to the deSired RAM address (fable 9).
YCR2
2:1B:0
0
V Coefficient RAM Select Chip 2. When control bit YCR21s a I, YADD2 applies to the DSP chip 2's
Y Coefficient RAM. When YCR2 is a 0, YADD2 applies to the Y Data RAM. This bit must be set
according to the desired RAM address (fable 9).
YDALO
0:16:0-7
00
V RAM Data LSB Chip O. YDALO is the least significant byte of the 16-bIt Y RAM data word used in
reading or writing Y RAM locations in DSP chip O.
YDALI
1 :16:0-7
00
V RAM Data LSB Chip 1. YDAL 1 is the least significant byte of the 16-bit Y RAM data word used in
reading or writing Y RAM locations in DSP chip 1.
YDAL2
2:16:0-7
00
V RAM Data LSB Chip 2. YDAL2 is the least Significant byte of the 16-bit Y RAM data word used in
reading or writing Y RAM location in DSP chip 2.
YDAMO
0: 17:0-7
00
V RAM Data MSB Chip O. YDAMO is the most Significant byte of the 16-bit Y RAM data word used in
reading or writing Y RAM locations in DSP chip O.
YDAMI
1 :17:0-7
00
V RAM Data MSB Chip 1. YDAMI is the most significant byte of the 16·bit Y RAM data word used in
reading or writing Y RAM locations in DSP chip 1.
YDAM2
2:17:0-7
00
V RAM Data MSB Chip 2. YDAM2 is the most significant byte of the 16-bIt Y RAM data word used in
reading or writing Y RAM locations In DSP chip 2.
YWTO
O:IB:l
0
V RAM Write Chip O. When YWTO IS a 1 and VACca is set to a I, DSP chip 0 copies data from the Y RAM
Data registers (0: 16 and 0: 17) into the Y RAM locabon addressed by YADDO and YCRO. When control
bit YWTO is a 0 and YACCO is set to a I, DSP chip 0 reads Y RAM at the location addressed by
YADDO and YCRO. The read data is stored into the Y RAM Data registers (0: 16 and 0: 17).
YWTl
1:IB:l
0
V RAM Write Chip 1. When YWTl is a 1 and YACCI IS set to a I, DSP chip 1 copies data from the Y RAM
Data registers (1'16 and 1 : 17) into the Y RAM location addressed by YADDI and YCRI. When control
bit YWTl is a 0 and YACCI is set to a I, DSP chip 1 reads Y RAM at the location addressed by
YADDI and YCRI. The read data is stored into the Y RAM Data registers (1 : 16 and 1 : 17).
YWT2
2:1B:l
0
V RAM Write Chip 2. When YWT21s a 1 and YACC2 is set to a I, DSP chip 2 copies data from the Y RAM
Data registers (2: 16 and 2: 17) into the Y RAM location addressed byYADD2 and YCR2. When control
bit YWT2 is a 0 and YACC2 IS set to a I, DSP Chip 2 reads Y RAM at the location addressed by
YADD2 and YCR2. The read data is stored In the Y RAM Data registers (2: 16 and 2: 17).-
Mnemonic
Name/Description
1-237
---~-
- - - - - - - - - ---
V.32 9600 bps Full-Duplex Modem
R9696DP
DSP RAM ACCESS
to a 1. Load the RAM Address code into X RAM Address and/or
Y RAM address register; then set XCRO and/or YCRO appropriately. Set XACCO and/or YACCO to a 1 to signal the DSP to
perform the RAM read. When the DSP has transferred the
contents of RAM into the interface memory RAM Data registers,
the DSP sets the XACCO and/or the YACCO bit to a 0 and the
NEWSO bit to a 1 to indicate DSP RAM read completion.
GENERAL
DSP RAM Organization
Each DSP contains a 16-bit wide random access memory (RAM).
Because the DSP is optimized for performing complex arithmetic,
the RAM is organized into real (X RAM) and imaginary Cf RAM)
parts. The host processor can access (read or write) the X RAM
only, the Y RAM only, or both the X RAM and the Y RAM
simultaneousl,Y.
If the NSIEO bit is ai, IRQ is also asserted when NEWSO is set
to a 1. When IRQ is asserted, NSIAO goes to a 1 to inform the
host that setting of the NEWSO bit was the source of the interrupt. NSIAO is cleared by writing a 0 into the NEWSO bit, which
causes IRQ to return high if no other interrupt requests are
pending.
Interface Memory Access to DSP RAM
CONTINUOUS RAM READ PROCEDURE
The interface memory acts as an intermediary during host to
DSP RAM or DSP RAM to host data exchanges. The address
stored in DSP interface memory RAM Access registers by the
host, in conjunction with the data or coefficient RAM bit (e.g.,
XCRO) determines the DSP RAM address for data access.
There are several diagnostic parameters that the host may wish
to read every sample or every baud period. One example of this
is the EQM (Eye Quality Monitor) value in chip 2 (receiver baud).
The host may avoid having to set the XACC2IYACC2 bit every
baud period by using the continuous read feature. Setting
XCRD2 to a 1 overrides both XACC2 and XWT2 bits, while setting YCRD2 to a 1 overrides both YACC2 and YWT2 bits.
One or two 16-bit words are transferred between DSP RAM and
DSP interface memory once each device cycle. The transmitter
device and the receiver sample rate device operate at the
9600 Hz sample rate. The receiver baud rate device operates
at the baud rate of the selected data rate.
The RAM address registers 1A and 1C and the XCR2 and YCR2
bits must be set up as described in the general DSP RAM read
procedure, Then set XCRD2 and YCRD2 to 1. The chip 2 DSP
will then transfer data to the interface memory every baud. The
NEWS2 bit is set as described in the general DSP RAM read
procedure.
Two RAM access bits in each DSP interface memory tell the
DSP to access the X RAM and/or Y RAM. For example, the
transfer is initiated in the transmitter by the host setting the
XACCO and/or the YACCO bites). The transmitter tests these bits
each sample period. The receiver tests XACCI and YACCI each
sample period and XACC2 and YACC2 each baud period.
The transmitter (chip 0) and receiver (chip 1) can be similarly
treated, however, data will be transferred every sample by each
device.
The following procedure applies to DSP RAM access in the transmitter device. The procedure to access DSP RAM in the receiver
devices is the same with the exception of the RAM access
bit names.
Table 9 provides the RAM functions, address codes, and
registers.
DSP RAM Write Procedure (Transmitter)
SOFTWARE INTERFACE CONSIDERATIONS
Before writing to DSP interface memory, set XACCO and YACCO
to a O. Set XWTO and/or YWTO to a 1 to inform the DSP that
a RAM write will occur when XACCO and/or YACCO is set to a 1.
Load the RAM address into X RAM Address and/or Y RAM
Address registers; then set XCRO and/or YCRO appropriately.
Write the desired data into the interface memory RAM Data
registers then set XACCO and/or YACCO to a 1 to signal the DSP
to perform the RAM write. When the DSP has transferred the
contents of the interface memory RAM Data registers into RAM,
the DSP sets the XACCO and/or the YACCO bit to a 0 and the
NEWSO bit to,a 1 to indicate DSP RAM write completion.
INTERRUPT REQUEST HANDLING
DSP interface memory registers registers 00, 1E and 1F have
unique hardware connections to the interrupt logic. Register 00
is the Receive Buffer (RBUFFER)/Rate Sequence Code
LSB (RSEQL) in the receiver sample rate device and the Transmit
Buffer (TBUFFER)lTransmit Signal Point X (TSPX) in the transmitter device. Registers 1E and 1F hold interrupt flag, interrupt
enable, and interrupt active bits. When a condition occurs that
satisfies an interrupt criteria, the corresponding interrupt flag bit
is set. This interrupt flag can be reported to the host either by the
host polling the interrupt flag bits (i.e., not using IRQ) or by being
interrupted by IRQ. When an interrupt enable bit is ai, IRQ is
asserted and the appropriate interrupt active bit set to a 1 when
the corresponding interrupt condition occurs.
If the NSIEO bit is ai, IRQ is also asserted and NSIAO is set to a
1 when NEWSO is set to a 1. NSIAO is cleared by writing a 0
into the NEWSO bit, which also causes IRQ to return high if no
other interrupt requests are pending.
The basic sources fbr IRQ generation are status change detected,
configuration change implemented, receive buffer full and transmit buffer empty. Each source is individually maskable. Table 10
identifies the interrupt sources and describes the interrupt clearing
procedures.
DSP RAM Read Procedure (Transmitter)
Before reading from DSP interface memory, set XACCO and
YACCO to a O. Set XWTO and/or YWTO to a 0 to inform the DSP
that a RAM read will occur when XACCO and/or Y ACCO is set
1-238
R9696DP
V.32 9600 bps Full-Duplex Modem
Table 9.
R9696DP RAM Addresses
Address Code
Address Code
No.
Real Imaginary
Chip Part
CR
Part
No. (X)
(Y)
Bit' No.
Function
1 Transmitter Compromise Equalizer
Coefficients'
First Tap
Last Tap
2 V.33N.32 Rate Sequence
3 DTMF Tone Duration
4 DTMF Interdigit Delay
5 DTMF Low Band Power Level
6 DTMF High Band Power Level
7 Pulse Relay Make Time
8 Pulse Relay Break Time
9 Pulse Interdigit Delay
10 Transmitter Output Level Gam Constant
11 Dual Tone 1 Frequency
12 Dual Tone 2 Frequency
13 Dual Tone 1 Power Level
14 Dual Tone 2 Power Level
15 Transmitter New Status Bit (NEWSO)
Masking Register for O:E and O'F
16 Total Span of Echo Canceller
17 Echo Canceller Dlvidmg Pomt
18 Far End Echo Canceller Center
Tap Position
19 Echo Canceller Update CoeffiCient
(Training Mode)
20 Echo Canceller Update CoeffiCient
(Data Mode)
21 CTS OFF-te-ON Response Time
(RTS-CTS Delay)
22 Round Trip Far Echo Delay
23 Echo Canceller Error
24 Far End Echo Frequency Offset
25 Far End Echo Level
26 Tone Detector A Bandpass
Filter Coefficients
27 Tone Detector B Bandpass
Filter Coefficients
Note:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5B
34
93
9A
lA
19
99
9C
lC
lB
99
87
90
02
82
11
-
1
1
1
1
1
1
1
1
1
1
0
0
1
0
0
1
0
0
0
9D
AO
24
-
0
0
0
-
0
24
0
A4
-
0
10
-
1
0
0
0
0
1
9E
20
20
25
26
-
0
0
1
0
1
1
2C
-
1
1
1
Real Imaginary
Chip Part
Part
CR
No. (X)
(Y)
Bit'
Function
28 Tone Detector C Bandpass
Filter Coefficients
29 RLSD On-to-Off Threshold
30 RLDS Off-to-On Threshold
31 Receiver Chip 1 New Status Bit (NEWS1)
Maskmg Register for I:A and I:B
Masking Register for I:C and I:D
Masking Register for I:E and I:F
32 Received Signal Samples
33 Demodulator Output
34 Low Pass Filter Output
35 Average Energy
36 AGC Gain Word
37 Timmg Recovery Update
38 V.23 Receiver Compromise Equalizer
Coefficients:
Tap 1
Tap 20
Tap 21
Tap 40
39 Equalizer Input
40 Equalizer Tap Coefficients:
First Tap
Last Tap
41 Unrotated Equalizer Output
42 Rotated Equalizer Output (Received POints)
43 Decision Points (Ideal Points)
44 Equalizer Error
45 Equalizer Rotation Angle
46 Equalizer Frequency Correction
47 Eye Quality Monitor (EQM)
48 Maximum Penod of Valid Rmg Signal
49 Minimum Penod of Valid Rmg Signal
50 Receiver Chip 2 New Status Bit (NEWS2)
Masking Register for 2'E and 2:F
1
32
1
1
07
01
1
1
1
1
1
1
1
1
1
9B
9C
9D
03
04
00
02
01
25
1
1
1
1
2
76
63
F6
E3
18
2
2
2
2
2
2
2
2
2
2
2
2
18
47
01
02
02
03
87
OA
07
17
97
7E
-
-
-
84
80
-
98
98
C7
81
82
82
83
-
-
1
1
0
1
1
1
0
0
0
0
1
0
1
1
1
1
0
1
1
0
1
0
0
1
1
1
0
0
0
1. CR corresponds to XCRO, YCRO, XCR1, YCR1, XCR2, or YCR2 depend 109 on the chip number and address code.
Table 10.
Interrupt
Active Bit
Interrupt
Enable Bit
Interrupt
Flag Bit
Interrupt Request Bits
Interrupt Condition Description
Interrupt Clear Procedure
Transmitter (DSP Chip 0)
NSIAO
NSIEO
NEWSO
New status detected (NEWSO transilioned from a 0 to 1)
a. RAM read or RAM wnte occurred
b. Status bit changed 10 register OA through OF
Host wntes a 0 into NEWSO
(Clears NSIAO to a 0)
NCIAO
NCIEO
NEWCO
NeVI transmitter configuralion Implemented by DSP
(NEWCO transllioned from a 1 to a 0)
Host wntes a 0 into NCIEO
(Clears NCIAO to a 0)
DBIEO
DBAO
Transmitter Data Buffer IS empty and can be written
(DBAO transilioned from a 0 to a 1)
Host wntes to register 0:0 (TBUFFERITSPX)
(Clears DBAO and DBIAO to 0)
DBIAO
I
Receiver (DSP Chip 1)
NSIAI
NSIEI
NEWSI
New status detected (NEWSI transltioned from a 0 to a 1)
a. RAM read or RAM wnte occurred
b. Status bit changed In register OA through OF
Host writes a 0 into NEWSI
(Clears NSIA1 to a 0)
NCIAI
NCIEI
NEWCl
New receiver configuration or receiver threshold
Implemented by DSP (NEWCl transitioned from a 1 to a 0)
Host writes a 0 into NCIEI
(Clears NCIAI to a 0)
DBIAI
DBIEI
DBAI
Receiver Chip 1 Data Buffer IS full and can be read
(DBA 1 transilioned from a 0 to a 1)
Host reads register 1:0 (RBUFFER/RSEQL)
(Clears DBA 1 and DBIA 1 to 0)
Receiver (DSP Chip 2)
NSIA2
NSIE2
NEWS2
New status detected (NEWS2 transllioned from a 0 to a 1)
a RAM read or RAM write occurred
b. Status bit changed in register OF
Host writes a 0 mto N EWS2
(Clears NSIA2 to a 0)
TBIA2
DBIE2
DBA2
Receiver Chip 2 Data Buffer IS full and can be read
(DBA2 transllioned from a 0 to a 1)
Host reads register 2:0 (RSPX)
(Clears DBA2 and DBIA2 to 0)
1-239
R9696DP
V.32 9600 bps Full-Duplex.Modem
AUTO DIAL PROCEDURE
The auto dialer default parameters are given in Table 11,
The host auto dial procedure is the same as outputting data to be
transmitted. using TBUFFER (Figure 5). The modem timing
accounts for the DTMF tone duration and amplitude, pulse
make/break ratio, and interdigit delay. These dialing parameters
are host programmable in DSP RAM.
Table 11.
Auto Dialer Default Parameters
Parameter
DTMF Tone Duration
DTMF Interdigit Delay
DTMF Total Output Power Level
DTMF Low Band Power Level
DTMF High Band Power Level
The levels of the high band and low band DTMF tones may be
modified by the host in DSP RAM. The level of the high band DTMF
tone should be 2 dB greater than the level of the low band DTMF
tone.
Pulse Relay Make Time
Pulse Relay Break Time
Pulse Interd,git Delay
Dial DlgltsJTone Pairs
Hex
00
01
02
03
04
05
06
07
08
09
OA
OB
Dial
Digits
0
1
2
3
4
5
6
7
8
9
#
Tone Pairs
941
697
697
697
770
770
770
852
852
852
941
941
Figure 5.
1336
1209
1336
1477
1209
1336
1477
1209
1336
1477
1209
1477
R9696DP Auto Dial Sequence and Dial Digits
1-240
Default Value
95ms
70 ms
OdBm
-4dBm
-2dBm
36 ms
64ms
750 ms
R9696DP
V.32 9600 bps Full-Duplex Modem
PERFORMANCE
TYPICAL BIT ERROR RATES
TYPICAL BER TEST SETUP
Typical modem bit error rate (SER) curves are shown in Figure 6
for a back-ta-back connection.
The SER curves shown in Figure 6 were prepared from data
obtained using a TAS 1002 test system.
10- 3
V.3217200 TCM-
It
w
!!!.
V.32/9600
TCM
10-'
w
•321
t-- V12000TCM
V.22 BIS/2400-~
ORG
!cII:
II:
!Iii
I
I
_V.32/9600
V.32/48tO
10- 5
V.22 B12400
ANSI
10- 6
1
o
20
25
30
10
15
Signal 10 Noise Rallo (SNR) - dB
a. Typical Bil Error Rate (Back-Io-Back, - 20 dBm Receive Level,
T Equalizer, Compromise Equalizer Disabled)
5
Figure 6.
Bit Error Rate Curves
ELECTROMECHANICAL DESIGN
CONSIDERATIONS
EB~OOOOOOOOOOOOOOOOOOOO
The area outlined by the analog ground plane in Figure 7 contains
components which are sensitive to electromagnetic interference
(EM I). When deSigning the host system, do not position radiating
circuitry in the vicinity of this sensitive area. A ground plane
adjacent to the modem analog circuitry is recommended.
00
ANALOG
GROUND
PLANE
~OoOOOOOOOOO
Figure 7.
1-241
Analog Ground Plane location
R9696DP
V.32 9600 bps Full-Duplex Modem
GENERAL SPECIFICATIONS
. Table 12. R9696DP Modem Power Requirements
Voltage'
Tolerance
Current (1Ypical)
@25°C
+5VDC
+12VDC
-12 VDC
±5%
±5%
±5%
300mA
3mA
30mA
Curr~nt
(Maximum)
@ooC
585 mA
SmA
3SmA
Note: 1. Input voltage ripple sO.1 volts peak-to-peak.
Table 13. R9696DP Modem Environmental Specifications
Parameter
Temperature
Operating
Storage
Relative Humidity:
Altitude
Specification
O·C to + lOoC (32°F to 158°F)
- 40°C to -l: 80°C (- 40°F to 17S0F) (Stored in heat sealed antistatic bag and shipping container)
Up to 90% noncondensing, or a wet bulb temperature up to 35°C, whichever is less.
- 200 feet to + 10,000 feet
Table 14.
R9696DP Modem Mechanical Dimensions
Parameter
Board Structure:
Dimensions:
Width
Length
Component Height
Top (max.)
Bottom (max.)
Weight (max.):
Pin Length (max.)
Specification
Single PC board With a row of 30 pins and a row of 31 pins in a dual In-line pin configuration.
3.228 in. (82 mm)
3.937 in. (100 mm)
,
0.300 in. (7.S2 mm)
0.130 in. (3.3 mm)
3.S oz. (100 g)
0.535 ± 0.Q15 in. (13.S ± 0.4 mm), gold plated
0.433 ±0.015 in. (11.0 ±0.4 mm), gold plated
0.315 ± 0.Q15 In. (8.0 ± 0.4 mm), gold plated
0.250
(6.4)
-I
3.228
"j= .....,." '"
78.1
(2.5)
0,'tO~"00 (TYP.)o
(2.54)
0.100
(2.54)
°
I"
TO.075
0
(2.54)
3725
-'-_
3.937 _{_9_4._6)_ _..
(1.9)
(100)
SEE TABLE 14
0.025 Sa. PIN
0.300 MAX
rl,"",,''''',1";''
T~.~;;'-'-"'-'
... - -··--·"~.,30
(1.6)
Figure 7.
(3.3)
COMPONENT AREA
R9696DP Modem Dimensions and Pin Locations
1-242
SECTION 2
Leased Line Data Modems
Product Family Overview ............................... " ......................... 2-2
R208/201 4800 bps Modem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-3
R96DP 9600 bps Data Pump Modem .............................................. 2-26
R96FT 9600 bps Fast Train Modem ............................................... 2-47
R96FT/SC 9600 bps Fast Train Modem with Forward Secondary Channel ................. 2-63
R144DP V.3314.4 kbps Full-Duplex Modem ........................................ 2-78
R1496DP V.33 14.4 kbpsN,32 9600 bps Full-Duplex Modem .......................... 2-103
2-1
II
LEASED LINE DATA MODEMS
LEADING THE INDUSTRY WITH HIGH PERFORMANCE AND QUALITY
Rockwell's extensive 4800 to 14400 bps leased-line modem product line can easily be incorporated into
standalone or system level products at a minimal cost while offering your customer high performance,
quality and reliability. This line of modems uses the latest technology to provide customers with the smallest, most integrated designs available on the market.
Our high and ultra-high speed modems are designed to meet the Bell standard as well as the rigid CCITT
recommendations. Whether operating at 4800 bps or 14400 bps, transmitting data across the street or
across the world, 'customers can be assured that Rockwell modems have been designed, built and tested
to ensure world-wide connectivity.
Model
Data Speed
(bps)
Compliance
R208/201
4800,2400,1200
Bell 201 B/C, 208NB CCITT V.27 bis/ter, V.26, V.26 bis
R96DP
9600,7200,4800,2400
CCITT V.29, V.27 bis/ter
R96FT
9600,7200,4800,2400
CCITTV.29, V.27 bis/ter, V.21 Channel 2,
Proprietary Fast Train
R96FT/SC
9600,7200,4800,2400,75
CCITT V.29, V.27 bis/ter, V.21 Channel 2,
Proprietary Fast Train, Secondary Channel
R144DP
14400,12000,9600,7200,
4800,2400
CCITT V.33, V.29, V.27 bis/ler
14400,12000,9600,4800,
7200, 2400, 1200
CCITTV.33, V.32, V.29, V.22 bis
R1496DP
2-2
R208/201
Integral Modems
'1'
Rockwell
R208/201
Bell 208A/B and Bell 201 C Modem
INTRODUCTION
FEATURES
• Compatible with
- Bell 208AlB, Bell 201C
- CCITT V.27 and V.26
• Automatic Configuration during Synchronizing Sequence
• 2-Wire Half-Duplex, 4-Wire Full-Duplex
• Programmable Tone Generation
• Programmable DTMF Tone Dialer
• Call Progress Tone Detection
• Programmable RTS/CTS Delay (Bell 201 C and V.26 only)
• Dynamic Range: - 43 dBm to 0 dBm
• Equalization
- Automatic Adaptive
- Compromise Cable and Link (Selectable)
• DTE Interface
- Functional: CCITT V.24 (RS-232-C)(Data/Control) and
Microprocessor Bus (Data/Configuration/Control)
- Electrical: TTL and CMOS Compatible
• Diagnostic Capability
• Programmable Transmit Output Level
• Loopbacks
- Local and Remote Analog
- Remote Digital
• Small Size
- DIN Connector Version:
100 mm x 120 mm (3.94 in. x 4.73 in.)
- DIP Connector Version: (normal size)
82 mm x 100 mm (3.23 in. x 3.94 in.)
- Micromodem Version
65 mm x 100 mm (2.56 in. x 3.94 in.)
• Power Consumption: 3 W (Typical)
The Rockwell R208/201 is a synchronous 4800, 2400 and 1200
bits per second (bps) modem. It is designed for operation over
the public switched telephone network (PSTN) as well as leased
lines through the appropriate line termination. The R208/201
automatically senses the mode of the remote modem
(Bell 208 AlB or Bell 201C) and configures itself to operate in a
compatible mode.
The modem satisfies the telecommunications requirements
specified in Bell 208AlB, Bell 201C, CCITT V.27, and CCITT
V.26AlB. The R208/201 can operate at speeds of 4800,2400 and
1200 bps. Employing advanced signal processing techniques,
the R208/201 can transmit and receive data even under
extremely poor line conditions.
User programmable features allow the R208/201 to be tailored to
support a wide variety of functional requirements. The modem's
small size, low power consumption, and serial/parallel host interface simplify system design and allow installation in a compact
enclosure. The modem module is available with a DIN connector
for connection to a mating connector or with dual-in-line pins
(DIP) in normal or Micromodem~ size modules for direct plug-in
installation onto a host module.
Mlcromodem IS a trademark of Rockwell International
R208/201 Micromodem Version
Document No. 29200N26
R208/201 DIP Connector Version
Data Sheet
2-3
Order No. MD26
Rev. 3, January 1989
•
Bell 208A/B and Bell 201C Modem
R208/201
TECHNICAL SPECIFICATIONS
The out-of-band transmitter power limitations meet those spec'!-'
fied by Part 68 of the FCC's rules, aod tYpically exceed the
requirements of foreign telephone regulatory bodies.
TRANSMITTER CARRIER FREQUENCIES
SCRAMBLERJDESCRAMBLER
The supported transmitter carrier frequencies are listed in
Table 1.
Table 1.
The modem incorporates a self-synchronizing scrambler/
descrambler. This facility is in accordance with V.27 bislter.
Transmitter Carrier Frequencies
Function
Frequency
(Hz ±0.01%)
Bell 20BAlB and Bell 201 C
CCITI V.27 and V.26
1800
1800
RECEIVED SIGNAL FREQUENCY TOLERANCE
The modem receiver circuit can adapt to received frequency
error of up to ± 10 Hz with less than 0.2 dB degradation in BER
performance.
TONE GENERATION
RECEIVE LEVEL
Under control of the host processor, the modem can generate
voice band tones up to 4800 Hz with a resolution of 0.15 Hz and
an accuracy of 0.01 %. Tones over 3000 Hz are attenuated.
DTMF tone transmission capability is provided to allow the
modem to operate as a programmable DTMF tone dialer.
The modem receiver circuit satisfies all specified performance
requirements for received line signal levels from 0 dBm to
- 43 dBm. The received line signal level is measured at the
receiver analog input (RXA).
TRANSMIT LEVEL
SIGNALING AND DATA RATES
The transmitter output level is accurate to ± 1.0 dB and is programmable from - 1.0 dBm to - 15.0 dBm in 2 dB steps.
The supported Signaling and data rates are listed in Table 2.
Table 2.
Specification
TRAIN ON DATA
Signaling/Data Rates
When train on data is enabled, the receiver typically trains on
data in less than 3.5 seconds.
Bits
Per
Baud Rate
Data Rate
Symbol
(SymbolS/sec.) Baud (bps)(± 0.01 %) Points
Bell208A/B
CCITIV.27
CCITIV.27
V.26B/Bell201C
CCITIV.26
CCITIV.26
1600
1600
1200
1200
1200
1200
3
3
2
2
2
1
4800
4800
2400
2400
2400
1200
TURN-ON SEQUENCE
8
8
4
4
4
4
Selectable turn-on sequences can be generated for Be1l208A1B
and V.27 as defined in Table 3. V.26A1B/BeIl201C have a programmable RTS/CTS delay with a default time of 26.6 ms (see
page 18).
Table 3.
DATA ENCODING
Bell 208A1B and V.27 Turn-On Sequences
RTS-CTS Turn-On Time
The modem data encoding conforms to Bell 208A1B, Bell 201C,
CCITT V.27, and CCITT V.26.
Specification
EQUALIZERS
Bell 20BAlB Long
Bell 20BAlB Short
V.27 4800 Long
V.27 4800 Short
V.27 2400 Long
V.27 2400 Short
The modem provides equalization functions that improve performance when operating over low quality lines.
Cable Equalizers -
Selectable compromise cable equalizers in
the receiVer and transmitter are provided to optimize performance
over different lengths of non-loaded cable of 0.4 mm diameter.
For Be1l208A1B and CCITT V.27, the turn-off sequence consists
of approximately 7 ms and 10 ms, respectively, of remaining data
and scrambled ones. For V.26B/Bell 201C and CCITT V.26, the
turn-off sequence consists of approximately 6 ms of remaining
data and scrambled ones.
.
TRANSMITTED DATA SPECTRUM
If the cable equalizer is not enabled, the transmitter spectrum is
shaped by the following raised cosine filter functions:
2. 1600 Baud.
Square root of 50 percent
355
255
913
255
1148
272
TURN-OFF SEQUENCE
Automatic Adaptive Equalizer ,- An automatic adaptive equalizer is provided in the receiver cirCuil. The equalizer can be configured as either a T or a Tl2 equalizer.
Square root of 90 percent
150
50
708
50
943
67
Echo Protector
Tone Enabled'
'For short echo protector. tone, subtract 155 ms from RT8-CTS
turn·on time.
Link Equalizers - Selectable compromise link equalizers in the
receiver optimize i>erformanc~ over channels exhibiting severe
amplitude.and delay distortior:1. Two standards are provided: U.S.
survey long and Japanese 3-link.
1. 1200 Baud.
Echo Protector
Tone Disabled
CLAMPING
Received Data (RXD) is clamped to a constant mark (one) whenever the Received Line Signal Detector (RLSD) is off.
2-4
Bell 208A/B and Bell 201C Modem
R208/201
MODEM OPERATION
The interconnect signals on Figure 1 are organized into six groups
of modem operation: overhead Signals, V.24 interface Signals,
microprocessor interface signals, diagnostic signals, analog signals, and ancillary signals. Table 4 lists these groups along with
their corresponding connector pin numbers. The six groups of hardware circuits are described in the following paragraphs. Table 5 lists
the digital interface characteristics.
Because the modem is implemented in firmware executed by a
specialized computer (the signal processor), operation can best
be understood by dividing this section into hardware circuits and
software circuits. Hardware circuits include all pins on the
modem connector. Software circuits include configuration, control (soft strapping), status, and RAM access routines.
POWER-ON RESET
HARDWARE CIRCUITS
Basic modem operation can be understood most easily by beginning with the modem configured to default conditions. When the
modem is initially energized a signal called Power-an-Reset
(PaR) causes the modem to assume a valid operational state.
The modem drives pin POR to ground during the beginning of the
POR sequence. Approximately 10 ms after the low to high transition
of pin POR, the modem is ready for normal use. The POR sequence
is reinitiated anytime the + 5V supply drops below + 3.5V for more
than 30 ms, or an external device drives pin POR low for at least
3 ""s. When an external low input is applied to pin POR, the modem
is ready for normal use approximately 10 ms after the low input is
removed. Pin POR is not driven low by the modem when the POR
sequence is initiated externally. In all cases, the POR sequence
requires 50 ms to 350 ms to complete. The modem POR sequence
leaves the modem configured as follows:
The functional interconnect diagram (Figure 1) shows the
modem connected into a system. In this diagram, any point that
is active when exhibiting the relatively more negative voltage of a
two voltage system (e.g., 0 Vdc for TTL or -12 Vdc for
RS-232-C) is called low active and is represented by association
with a small circle at the signal point. The particular voltage levels used to represent the binary states do not change the logic
symbol. Two types of 1/0 pOints that may cause confusion are
edge-triggered inputs and open-collector (open-source or opendrain) outputs. These signal pOints include the additional notation of a small triangle or a small half-circle (see signal IRQ),
respectively. Active low signals are named with an overscore
(e.g., paR). In deciding whether a clock output is high active or
low active, the convention followed is to assume that the clocking
(activating) edge appropriate to the host hardware is a transition
from the clocks active to its inactive state (i.e., a trailing edge
trigger). A clock intended to activate logiC on its riSing edge is
called low active while a clock intended to activate logic on its
falling edge is called high active. When a clock input is associated with a small circle, the input activates on a falling edge. If
no circle is shown, the input activates on a rising edge.
1"'-------.,
RTS
1
CTS
I'
1.
TDCLK
•
•
•
•
•
•
•
•
Bell 208 Short
Serial channel data
Tl2 equalizer
No echo protector tone
- 43 dBm threshold
Cable and link equalizers disabled
Train-an-Data enabled
Scrambler and descrambler enabled
::
O
.
..
SCOPE
t)>---'-'-'-=-_••a
USRT
TXD
EYEX
""=1.._......:;X:..:.T-=C.::LK;.:...---i~
(OPTIONAL)
EYE
EYEY
PATTERN
~-=EY~E::.:S::...Y:..:.N~C~~GENERATOR
h
EYECLK
RLSD
RXD
RDCLK
~
TBCLK'"
....
,,)
~
R208/201
MODEM
RBCLK
+12V
+5V
POWER
SUPPLY
GND
READ OR READ
h
-12V
WRITE
" __""I-'D::.:A",T:.:.A~B::.:U::.:S::...il::
(18,--1---i~ Di
TXA
t-_+,A=D-=D~R:::ES::::S:...;B::.:U::::S:...;i11:::'41'-1 RSi
HOST
PROCESSOR
(DTE)
DECODER ......
r
(
CS (21.
RXA
CSi
POR
AUXIN
IRQ
(h..
+5
-'V"-
LINE
INTERFACE
J
Figure 1.
R208/201 Functional Interconnect Diagram
2-5
TELEPHONE
LINE
•
Bell 208A1B and Bell 201C Modem
R208/201
Table 4.
Name
R208/201 Hardware Circuits
Type'
DIN
Pin No.
DIP'
Pin No.
Micromodem
Pin No.
AGND
DGND
PWR
PWR
PWR
IIOB
31C,32C
3C,8C,5A,IOA
19C,23C,26C,30C
15A
12A
13C
30,31
29,37,53
1,45,61
32
36
2
27,28
32,36,51
9,14,55
29
31
4
50
49
48
47
46
45
44
43
Description
A. OVERHEAD:
Ground (A)
Ground (D)
+5 volts
+ 12 volts
-12 volts
paR
Analog Ground Return
Digital Ground Return
+ 5 volt supply
+ 12 volt supply
- 12 volt supply
Power·on·reset
B. MICROPROCESSOR INTERFACE:
D7
D6
D5
D4
D3
D2
DI
DO
I/OA
I/OA
I/OA
I/OA
I/OA
I/OA
I/OA
I/OA
IC
IA
2C
3A
4C
4A
5C
3
4
5
6
7
8
9
10
RS3
RS2
RSI
RSO
IA
IA
IA
IA
6C
6A
7C
7A
16
17
18
19
3
58
57
40
CSO
CSI
IA
IA
10C
9C
20
21
2
42
CS2
READ
READ
WRITE
IRQ
IA
IA
IA
IA
OB
9A
12C
13
14
Chip Select Transmitter Device
Chip Select Receiver Sample Rate
Device
Chip Select Receiver Baud Rate Device
Read Enable
Read Enable
Write Enable
Interrupt Request
2A
}
Data Bus (8 Bits)
}
Register Select
(4 Bits)
l1A
l1C
12
11
60
61
59
I
21A
23A
22A
25A
25C
24C
22C
24A
23
46
51
50
49
48
26
27
38
6
5
10
8
11
35
.37
Receive Data Clock
Transmit Data Clock
External Transmit Clock
Request-to·Send
Clear·to-Send
Transmitter Data
Receiver Data
Received Line Signal Detector
26A
27C
22
47
12
7
Receiver Baud Clock
Transmitter Baud Clock
AA
AB
AC
31A
32A
30A
34
33
26
30
-
-
Transmitter Analog Output
Receiver Analog Input
Auxiliary Analog Input
OC
OC
OA
OA
15C
14A
14C
13A
56
55
57
58
52
56
54
53
Eye
Eye
Eye
Eye
-
-
C. V.24 INTERFACE:
RDCLK
TDCLK
XTCLK
RTS
CTS
TXD
RXD
RLSD
OC
OC
IB
IB
OC
IB
OC
OC
D. ANCILLARY CIRCUITS:
RBCLK
TBCLK
OC
OC
E. ANALOG SIGNALS:
TXA
RXA
AUXIN
F. DIAGNOSTIC:
EYEX
EYEY
EYECLK
EYE SYNC
Pattern
Pattern
Pattern
Pattern
Data-X Axis
Data-Y AXIs
Clock
Synchronizing Signal
Notes:
I. Refer to Table 5 for digital circUit interface characteristics and Table 7 for analog circuit interface characteristics.
2. Pins not used on the DIP Version: 15, 24, 25, 28, 35, 38, 39, 40, 41, 42, 43, 44, 52, 54, 59, and 60.
3. Pins not used on the Micromodem: 13, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 33, 34, 39, and 41.
4. Unused inputs tied to + 5V or ground require individual 10K !l senes resistors.
2-6
R208/201
Bell 208A1B and Bell 201C Modem
Table 5.
Digital Interface Characteristics
Input/Output Typs
Symbol
VIH
Parsmeter
Units
IA
IB
IC
OA
Input Voltage. High
V
2.0 Min.
2.0 Min.
2.0 Min.
0.8 Max.
0.8 Max.
0.8 Max.
VIL
Input Voltage. Low
V
V OH
Output Voltage. High
V
VOL
Output Voltage, Low
liN
Input Current, Leakage
10H
Output Current, High
rnA
10L
Output Current, Low
rnA
IL
Output Current, Leakage
p.A
Ipu
Pull·up Current
(Short Circuit)
p.A
CL
Capacitive Load
pF
Co
Capacitive Drive
pF
Circuit Type
1. I Load
2. I Load
2.4 Min.'
0.4 Max. 2
V
p.A
DC
0.4 Max. 2
0.4 Max. 2
±2.5 Max.
1.6 Max.
±10 Max.
-240 Max. -240 Max.
-10 Min.
-10 Min.
5
110 A
I/O B
2.0 Min.
5.25 Max.
2.0 Min.
0.8 Max.
0.8 Max.
2.4 Min.3
2.4 Min.'
0.4 Max. 2
0.4 Max. 5
±2.5 Max.'
-0.1 Max.
1.6 Max.
5
TTL
w/Pull-up
1.6 Max.
-240 Max.
-10 Min.
20
100
TTL
= -100p.A
= 1.6 rnA
DB
TTL
w/Pull·up
TTL
Notes
3. I Load = -40 p.A
4. VIN = 0.4 to 2.4 Vdc, Vee
This configuration is suitable for performing high speed data
transfer using the serial data port. Individual features are discussed in subsequent paragraphs.
100
100
-260 Max.
-100 Min.
10
100
40
100
Open·Drain Open·Drain
3·State
Opsn·Drain
w/Pull-up Transceiver w/Pull-up
5. I Load = 0.36 rnA
= 5.25 Vdc
Clear To Send (CTS)
CTS ON indicates to the terminal equipment that the modem will
transmit any data which are present on TXO. CTS response times
from an ON condition of RTS are shown in Table 3.
The time between the on-to-off transition of RTS and the on-to-off
transition of CTS in data state is a maximum of 2 baud times for
all configurations.
V.24 INTERFACE
Eight hardware circuits provide timing, data, and control Signals
for implementing a serial interface compatible with CCITT Recommendation V.24. These signals interface directly with circuits
using TTL logic levels (OV, + SV). These TTL levels are suitable
for driving the short wire lengths or printed circuitry normally
found within stand-alone modem enclosures or equipment cabinets. For driving longer cables, the voltage levels and connector
arrangement recommended by EIA standard RS-232-C are
preferred.
The sequence of events leading to successful data transfer from
transmitter to receiver is:
Received Line Signal Detector (RLSD)
For Be1l208A1B and CCITT V.27, RLSO turns on at the end olthe
training sequence. If training is not detected at the receiver, the
RLSO off-to-on response time is 15 ±10 ms. For Bell201C, RLSO
turns on in 10 ± 5 ms after the detection of energy above threShold. The RLSO on-ta-off response time for Bell 208A/B, CCITT
V.27 and Bell201C is 10 ±5 ms. Response times are measured
with a signal at least 3 dB above the actual RLSO on the threshold or at least 5 dB below the actual RLSO off threshold.
1. The transmitter is activated and a training sequence is sent.
2. The receiver detects channel energy above the prescribed
threshold level and synchronizes its operation to the
transmitter.
The RLSO on-to-off response time ensures that all valid data bits
have appeared on RXO.
3. Data transfer proceeds to the end of the message.
Four threshold options are provided:
4. The transmitter turns off after insuring that all data has had
time to be recovered at the receiver output.
1. Greater than - 43 dBm (RLSO on)
Less than - 48 dBm (RLSO off)
2. Greater than - 33 dBm (RLSO on)
Less than - 38 dBm (RLSO off)
Transmitted Data (TXD)
The modem obtains serial data from the local OTE on this input.
3. Greater than - 26 dBm (RLSO on)
Less than - 31 dBm (RLSO off)
Received Data (RXD)
The modem presents received data to the local OTE on this output.
4. Greater than - 16 dBm (RLSO on)
Less than - 21 dBm (RLSO off)
Request To Send (Rf~)
NOTE
RTS ON allows the modem to transmit data on TXO when CTS
becomes active. The responses to RTS are shown in Table 3.
Performance may be at a reduced level when the
received signal is less than - 43 dBm.
2-7
..
I
Bell 208A/B and Bell 201C Modem
R208/201
A minimum hysteresis action of 2 dB exists between the actual
off-to-on and on-to-off transition levels. The threshold level and
hysteresis action are measured with an un modulated 2100 Hz
tone applied to the receiver's audio input (RXA).
Read Enable (READ) and
Write Enable (WRITE)
Reading or writing is activated by pulsing either the READ line
high (low for micromodem) or the WRITE line low. During a read
cycle, data from the selected register is gated onto the data bus
by means of three-state drivers. These drivers force the data
lines high for a one bit or low for a zero bit. When not being read,
the three-state drivers assume their off, high-impedance, state.
During a write cycle, data from the data bus is copied into the
selected register, with high and low bus levels representing one
bits and zero bits, respectively. The timing required for correct
read/write cycles is illustrated in Figure 2. Logic necessary to
convert the single Rm output from a 65XX series microprocessor to the separate READ and WRITE signals required by
the modem is shown in Figure 3.
Transmit Data Clock (TDCLK)
The modem provides a Transmit Data Clock (TDCLK) output with
the following characteristics:
1. Frequency. Selected data rate of 4800 or 2400 Hz (± 0.D1 %).
2. Duty Cycle. 50 ±1%.
TDCLK is provided to the user in synchronous communications
for USRT timing. In this case Transmit Data (TXD) must be stable
during the one "s period immediately preceding and following
the rising edge of TDCLK.
External Transmit Clock (XTCLK)
Interrupt Request (IRQ)
In synchronous communication where the user needs to supply
the transmit data clock, the input XTCLK can be used. The clock
supplied at XTCLK must exhibit the same characteristics of
TDCLK. The XTCLK input is then reflected at TDCLK.
The final ~nal on the microprocessor interface is Interrupt
Request (IRQ). This signal may be connected to the host micraprocessor interrupt request input in order to interrupt host program execution for modem service. The use of IRQ is optional
and the method of software implementation is described in a
subsequent section, Software Circuits. The IRQ output structure
is an open-drain field-effect-transistor (FET). This form of output
allows IRQ to be connected in parallel to other sources of interrupt. Any of these sources can drive the host interrupt input low,
and the interrupt servicing process continues until all interrupts
have been cleared and all IRQ sources have returned to their
!!!g!:I impedance state. Because of the open-drain structure of
IRQ, an external pull-up resistor to + 5 volts is required at some
point on the IRQ line. The resistor value should be small enough
to pull the IRQ line high when all IRQ drivers are off (i.e., it must
overcome the leakage currents). The resistor value should be
large enough to limit the driver sink current to a level acceptable
to each driver. For the case where only the modem IRQ driver is
used, a resistor value of 5.6K ohms ±20%, 0.25 watt, is
sufficient.
Receive Data Clock (RDCLK)
The modem provides a Receive Data Clock (RDCLK) output in
the form of a 50 ± 1% duty cycle squarewave. The low-ta-high
transitions of this output coincide with the center of received data
bits. RDCLK is provided to the user in synchronous communications for USRTtiming. The timing recovery circuit is capable of
tracking a ± .01 % frequency error in the associated transmit timing source.
MICROPROCESSOR INTERFACE
Eight hardware circuits provide address, data, control, and interrupt signals for implementing a parallel interface compatible with
an 8080 microprocessor. With the addition of a few external logic
gates, the interface can be made compatible with a wide variety
of microprocessors such as 6500, 6800, or 68000.
The microprocessor interface allows a host microprocessor to
change modem configuration, read or write channel data as well
as diagnostic data, and supervise modem operation by means of
soft strappable control bits and modem status bits. The significance of the control and status bits and methods of data interchange are discussed in a later section devoted to software circuits. This section describes the operation of the interface from a
hardware standpoint.
ANALOG SIGNALS
The analog signal characteristics are described in Table 6.
Table 6_
Chip Select (CSO-CS2) and
Register Selects (RSO-RS3)
The signal processor to be accessed is selected by grounding
one of three unique chip select lines, CS2, CS1 or CSO. The
selected chip decodes the four address lines, RS3 through RSO,
to select one of sixteen internal registers. The most significant
address bit (23) is RS3 while the least significant address bit (2!lj
is RSO. Once the address bits have been decoded, the selected
register can be read from or written into via an 8-bit parallel data
bus, 07 through DO. The most significant data bit (27) is 07 while
the least significant data bit (20) is DO.
2-8
Analog Interface Characteristics
Characteristics
Name
Type
TXA
AA
The transmitter output is 604 ohms ± 1%.
RXA
AB
The receiver input impedance is 60K ohms
±23%.
AUXIN
AC
The auxiliary analog input allows access to the
transmitter for the purpose of interfacing' with
user provided equipment. Because this is a
sampled data input, any signal above 4800 Hz
will cause aliasing errors. The input impedance
is 1K ohms, and the gain to transmitter output is
the TLVL setting + 0.6 dB - 1.4 dB.
R208/201
Bell 208A/B and Bell 201C Modem
WRITE
READ
CSI
(i
= 0,1)
RSI
(i
= 0-3)
•
Characteristic
CSi, RSi setup time prior
to Read or Write
Data access time after Read
Data hold time after Read
CSi, RSi hold time after
Read or Write
Write data setup time
Write data hold time
Write strobe pulse width
Figure 2.
Symbol
Min
TCS
TDA
TDH
30
TCH
TWOS
TWDH
TWR
10
75
10
75
10
Max
Units
140
50
ns
ns
ns
ns
ns
ns
ns
Microprocessor Interface Timing Diagram
x>--:----i
READ
R2081201
MODEM
~-----------~~WRITE
RNi
·MICROMODEM ONLY.
Figure 3.
RiW to READ WRITE Conversion Logic
2-9
Bell 208A/B and Bell 201C Modem
R208l201
Transmitter Analog (TXA)
ANCILLARY SIGNALS
The TXA line is an output suitable for driving an audio transformer or data access arrangement for connection to either
leased lines or the public switched telephone network. The output structure of TXA is a low impedance amplifier in series with
an internal 604 ohm ± 1% resistor to match a standard telephone load of 600 ohms.
Transmitter Baud Clock (TBCLK) and
Receiver Baud Clock (RBCLK)
Two clock signals called TBCLK and RBCLK are provided at the
modem connector. These signals have no counterpart in the V.24
or RS-232 recommendations since they mark the baud interval
for the transmitter and receiver rather than the data rate. The
baud clocks can be useful in identifying the order of data bits in a
baud (e.g., for multiplexing data, etc.). Both signals are high
active, meaning the baud boundaries occur on falling edges. The
first bit in each baud begins with the falling edge of the corresponding baud clock.
Receiver Analog (RXA)
RXA is an input to the receiver from an audio transformer or
data access arrangement. The input impedance is nominally
60K ohms but a factory select resistor allows a variance of 23%.
The RXA input must be shunted by an external resistor in order to
match a 600 ohm source. A 604 ohm ± 10lb resistor is
satisfactory.
SOFTWARE CIRCUITS
Operation of the microprocessor interface circuits was described
in the hardware section from the standpoint of timing and loadl
drive characteristics. In this section, operation of the microprocessor interface is described from a software standpoint.
Some form of transient protection for TXA and RXA is recommended when operating directly into a transformer. This protection may take the form of back-ta-back zener diodes across the
transformer or a varistor across the transformer.
The modem is implemented in firmware running on three special
purpose signal processors. These signal processors share the
computing load by performing tasks that are divided into areas.
These areas are partitioned into transmitter, baud rate, and sample rate devices.
Auxiliary Input (AUXIN)
AUXIN provides a means of inserting audio signals into the
modem output stage. Because this input is summed with the
transmitter output prior to the transmitter low pass filter and compromise equalizers, the AUXIN Signal is sampled by a compensated sample-and-hold circuit at a rate of 9600 samples-persecond. Any signal above 4800 Hz on the AUXIN line will be
aliased back into the passband as noise. The input impedance of
AUXIN is 1K ohm. The gain from AUXIN to TXA is the same as
the selected transmit level + 0.6 dB - 1.4 dB. AUXIN must be
grounded if not used.
INTERFACE MEMORY
Each signal processor can communicate with the host processor
by means of a specialized, dual-port, scratch-pad memory called
interface memory. A set of sixteen S-bit registers, labeled register 0 through register F, can be read from or written into by either
the host processor or signal processor. The host communicates
via the microprocessor interface lines shared between the two
Signal processors. The signal processor communicates via its
DIAGNOSTIC SIGNALS
EYEX, EYEY, EVECJJ<, and EYESYNC
Four card edge connections provide the timing and data necessary to create an oscilloscope quadrature eye pattern. The eye
pattern is simply a display of the received baseband constellation. By monitoring this constellation, an observer can often identify common line disturbances as well as defects in the modulationl
demodulation process.
EYESYNC
The outputs EYEX and EYEY provide two serial bit streams containing data for display on the oscilloscope X axis and Y axis,
respectively. Since this data is in serial digital form it must first be
converted to parallel digital form by two serial-ta-parallel converters and then to analog form by two D/A converters. A clock
for use by the serial-ta-parallel converters is furnished by signal
EYECLK. A strobe for loading the D/A converters is furnished by
signal EYESYNC. Timing of these signals is illustrated in Figure 4. The EYEX and EYEY outputs furnish 9-bit serial words.
Since most serial to parallel conversion logic is designed for 8-bit
words, an extra storage flip-flop is required for 9-bit resolution.
However, the ninth bit is not generally needed for eyepattern generation, and eight-bit hardware can be used if data is copied on
the rising edge of EYECLK rather than the falling edge.
EYEX,
EYEY
MSB
Figure 4.
2-10
LSB
Eye Pattern Timing
R208/201·
Bell 208A/B and Bell 201C Modem
internal 1/0 bus. Information transfer from SP RAM to interface
memory is accomplished by the signal processor logic unit moving data between the SP main bus and the SP 110 bus. Two of the
16 addressable interface memory registers (i.e., register 0 and
register E) have unique hardware connections to the interrupt
logic. It is possible to enable a bit in register E to cause an interrupt each time it sets. This interrupt can then be cleared by a read
or write cycle from the host processor to register O. This operation is discussed in detail later in this section.
normally transfers a word from RAM to interface memory once
each cycle of the device code. Each RAM word transferred to the
interface memory is 32 bits long (16 bits in the transmitter). These
bits are written by the SP logic unit into interface memory registers 3, 2, 1, and 0 in that order. Registers 3 and 2 contain the
most and least significant bytes of XRAM data, respectively,
while registers 1 and 0 contain the most and least significant
bytes of YRAM data, respectively. As previously described for
parallel data mode, the data available bits set to a one when
register 0 of the respective signal processor is written into by the
device and resets to a zero when register 0 is read from by the
host. Since the parallel data mode transmitter and receiver data
register shares register 0 with the YRAM data, chip 0 and 1 RAM
access are disabled in parallel data mode. However, chip 2 RAM
access remains active in receiver parallel data mode.
Memory maps of the 48 addressable registers in the modem are
shown in Figure 5. These registers may be read or written on any
host read or write cycle, but all eight bits of that register are
affected. In order to read a single bit or a group of bits in a register,
the host processor must mask out unwanted data. When writing
a single bit or group of bits in a register the host processor must
perform a read-modify-write operation. That is, the entire register
is read, the necessary bits are set or reset in the accumulator of
the host, then the original unmodified bits and the modified bits
are written back into the register of the interface memory.
The transmitter, sample rate device and the baud rate device
allow data to be transferred from interface memory to RAM.
When set to a one, bit SWRT (1 :7:3) signals the chip 1 SP logic
unit to suspend transfer of RAM data to the interface memory,
and instead, to transfer data from interface memory to RAM. Bit
TWRT (0:6:3) performs the same function for chip 0 RAM and bit
BWRT (1 :7:2) performs the same function for chip 2 RAM. When
writing into the RAM, 32 bits are transferred. The 16 bits written
into XRAM come from registers 3 and 2, with register 3 being the
more significant byte. The 16 bits written into YRAM come from
registers 1 and 0, with register 1 being the more significant byte.
When only 16 bits of data are to be written, FF (a dummy RAM
location) must be stored in RAM ACCESS XS or RAM ACCESS
YS to prevent writing the insignificant 16 bits of registers 1:3
through 1:0 into a valid RAM location. When the host processor
writes into register 1:0 the RSDA bit (1 :E:O) is resetto zero. When
the SP logic unit reads data from register 1:0, the RSDA bit
(1 :E:O) is setto aone.ln a similar manner, bit RBDA (2:E:0) resets
to zero when the host processor writes into register 2:0 and sets
to a one when the SP logiC unit reads data from register 2:0.
Table 7 defines the individual bits in the interface memory. In the
Table 7 descriptions, bits in the interface memory are referred to
using the format Y:Z:Q. The chip number is specified by Y (0 or
1), the register number by Z (0 through F), and the bit number by
Q (0 through 7, with 0 = LSB).
SIGNAL PROCESSOR RAM ACCESS
RAM and Data Organization
Each signal processor contains 128 words of random access
memory (RAM). Each word is 32 bits wide. Because the Signal
processor is optimized for performing complex arithmetic, the
RAM words are frequently used for storing complex numbers.
Therefore, each word is organized into a real part (16 bits) and an
imaginary part (16 bits) that can be accessed independently.
The portion of the word that normally holds the real value is
referred to as XRAM. The portion that normally holds the imaginary value is referred to as YRAM. In the sample rate and baud
rate devices the entire contents of XRAM and YRAM may be read
from or written into by the host processor via the microprocessor
interface. Access to the YRAM is possible only in the transmitter
device.
When reading from RAM, or writing into RAM, the bits in registers O:E, 1:E, 2:E can be used for handshaking or interrupt functions as in parallel data mode. When not in parallel data mode,
the bits in register 1:E perform the handshake and interrupt functions for RAM access. In both serial and parallel data modes, the
bits in register 2:E perform handshake and interrupt functions for
RAM access. When set to one, bit RBIE (2:E:2) enables RBDA to
drive the IRQ connector signal to zero volts when RBDA is a one.
Bit RBIA (2:E:7) identifies chip 2, the baud rate device, as a
source of IRQ interrupt. Bit RBIA is a one when both RBIE and
RBDA are setto one. In the eventthat other system elements may
cause IRQ to be driven low, the host must determine if modem
chip 2 is causing an interrupt by reading RBIA.
Interface Memory
The interface memory acts as an intermediary during these host
to signal processor RAM data exchanges. Information transfer
between RAM and interface memory is accomplished by the signal processor logic unit moving data between the SP main bus
and the SP 1/0 bus. The SP logic unit determines the RAM
address to read from or write into by the code stored in the RAM
ACCESS bits of interface memory registers. The SP logic unit
Table 8 provides the available RAM access functions, codes, and
registers.
2-11
2
Bell 208A/B and Bell 201C Modem
R208/201
Transmitter Interface Memory Chip 0 (CSO)
.~
"4
7
6
5
E
TlA
-
D
-
-
-
TTDIS
SOlS
1
2
3
0
Reglst
F
RAM ACCESS T
-
c
8
-
7
RTS
B
A
9
6
-
TSB
TIE
-
-
-
-
-
-
-
-
-
MHLD
EPT
-
-
TPDM
TBA
-
-
-
XCEN
SEPT
-
TRANSMITTER CONFIGURATIONITWAT (BIT 3)
-
5
4
DCEO
CEO
L3ACT L4ACT
LAEN
L4HG
LDEN
TLVL
3
A3L
D3L
L2ACT
LCEN
FREOM
2
FREOL
1
RAM DATA YTM
0
RAM DATA YTL; TRANSMITTER DATA; DDR
.~
7
5
6
4
1
2
3
0
Bit
( ) Indicates reserved lor modem use only.
Receiver Interface Memory Chip t (CSt)
~
7
F
SOH
E
RSIA
-
c
-
-
6
5
4
1
2
3
Receiver Interface Memory Chip 2 (CS2)
~
0
B
-
PNDET
A
-
9
-
FED
-
8
-
-
-
D
7
ATH
6
7
6
5
-
4
3
-
-
IFIX
DDIS
100
-
-
-
-
RSB
RSIE
-
-
-
-
lONE
-
P2DET
-
RPDM SWRT BWAT
T2
-
F
-
-
RSDA
E
RBIA
-
D
-
c
7
-
6
-
-
CDET
B
-
A
9
8
ATDIS
RECEIVER CONFIGURATION
5
RAM ACCESS XS
-
-
-
-
-
5
RAM ACCESS XB
4
RAM ACCESS YS
4
RAM ACCESS YB
3
RAM DATA XSM
3
RAM DATA XBM
2
RAM DATA XSL
2
RAM DATA XBL
1
RAM DATA YSM
1
RAM DATA YBM
0
RAM DATA YSL; RECEIVER DATA
0
RAM DATA YBL
/::
2
1
-
-
0
Reglste
Register
7
6
5
4
3
1
2
IZ
0
7
6
5
4
3
RBIE
-
2
Bit
Bit
( ) Indicates reserved for modem use only.
Figure 5.
(-) Indicates reserved lor modem use only.
Interface Memory Map
2-12
-
RBDA
-
-
-
1
0
R208/201
Bell 208A/B and Bell 201C Modem
Table 7.
Mnemonic
A3L
Name
Amplitude 3-Link
Select
R208/201 Interface Memory Definitions
Memory
Location
0:5:1
Description
A3L IS used in conJunC1ion with LAEN. When A3L is a one the Japanese 3 link
equalizer is selected and when A3L is a zero the U.S. Survey Long link equalizer is
seleC1ed.
BWRT
Baud Write
1 :7:2
When control bit BWRT is a one, the RAM write operation is enabled for Chip 2.
CEQ
Cable Equalizer
Field
0:5:(4.5)
The CEQ Control field simultaneously controls amplitude compromise equalizers in both
the transmit and receive paths. The following tables list the possible cable equalizer
seleC1ion codes and responses.
CEQ
Cable Length (0.4 mm diameter)
0
1
2
3
0.0
1.8 km
3.6 km
7.2 km
Cable Equalizer Nomlnel Gain
CEQ CODE 1
Gain Relative to 1700 Hz (dB)
Frequency
(Hz)
Transmitter
Receiver
700
1500
2000
3000
-0.99
-0.20
+0.15
+1.43
-0.94
-0.24
+0.31
+1.49
CEQ CODE 2
Gain Reletlve to 1700 Hz (dB)
Frequency
(Hz)
Transmitter
Receiver
700
1500
2000
3000
-2.39
-0.65
+0.87
+3.08
-2.67
-0.74
+1.02
+3.17'
CEQ CODE 3
Gain Relative to 1700 Hz (dB)
Frequency
(Hz)
Transmitter
Raeelver
700
1500
2000
3000
-3.93
-1.22
+1.90
+4.58
-3.98
-1.20
+1.81
+4.38
Unless a problem with training or high bit error rate is encountered, most applications
operate successfully wrth no cable equalizer seleC1ed.
CDET
Carrier DeteC10r
l:B'O
When zero, status bit CDET indicates that passband energy is being detected, and
that a training sequence is not in process. CDET goes to a zero at the start of the
data state, and returns to ~ at the end of the received signal. CDET aC1ivates
up to 1 baud time before RLSD and deaC1ivates w~hin 2 baud times after RLSD. If the
FED bit goes to a zero and no P2 sequence is deteC1ed, the CDET bit goes to zero
Within 5 to 25 ms indicating thet the receiver has entered the data state without a
training sequence.
DCEQ
Digitai Compromise
Equalizer
0'5:6
When control bit DCEQ is a one, a digital compromise equalizer is inserted in the transm~
path. (Beli 201CN 26 modes only.) Applicable to B5407-18 and subsequent.
DDIS
Descramble Disable
1.7:5
When control bit DDIS IS a one, the receiver descrambler circuit is removed from the
data path.
DDR
Dial Digrt Register
0:0:0-7
DDR is used to teli the modem which DTMF digit to transmit (see Transmitter Data).
D3L
Deiay 3-Link Select
0:5:0
D3L IS used In conjunC1ion w~h LDEN. When D3L is a one the Japanese 3 link
equalizer IS selected and when D3L is a zero the U.S. Survey Long link equalizer is seleC1ed.
2-13
•
Bell 208A1B and Bell 201C Modem
R208/201
Table 7.
Mnemonic
Name
R208/2011nterface Memory Definitions (Continued)
Memory
location
Description
EPT
Echo Protector
Tone
0:7:3
When control bit EPT is a one, an unmodulated carrier is transmitted for 185 ms
(optionally 30 ms) followed by 20 ms of no transmitted energy at the start of transmission.
FED
Fast Energy
Detector
1:9:6
When status bit FED is a zero, it indicates that energy above the receiver threshold Is
present in the passband, and the receiver is searching for the training sequence.
(None)
FREQUFREQM
0:2:0-7,
0:3:0-7
The host processor conveys tone generation data to the transmitter by writing a 1~H
data word to the FREQL and FREQM registers in the interface memory space, as
shown below:
FREQM Register (0:3)
Bit:
I
7
215
Data WOrd:,
I
I
6
214
I
I
I
I
5
213
4
212
I
I
3
211
,I
,
2
1
I
210
29
,
,
0
2B
FREQL Register (0:2)
IData
w:~~1
7
6
5
4
27
26
25
24
I
I
I
I
3
23
I
2
22
I
1
0
21
20
I
The frequency number (N) determines the frequency (F) as follows:
F = (0.146466) (N) Hz ±0.01%
Hexadecimal frequency numbers (FREQL, FREQM) for commonly generated tones are
given below:
FREQM
FREQL
Frequency (Hz)
OC
10
52
55
00
55
00
462
1100
1850
1850
2100
2C
31
38
IFIX
Eye Fix
1 :6:7
When control bit IFIX is a one, the serial data on EYEX and EYEY reflect the rotated
equalizer output and do not follow the data selected by RAM ACCESS XB and RAM
ACCESS YB
LAEN
Link Ampl~ude
Equalizer Enable
0:5:3
The link amplitude equalizer enable and select bits control an amplitude compromlsa
equalizer in the receive path according to the following table:
LAEN
A3L
Curve Metched
0
1
1
X
0
1
No Equalizer
U.S. Survey Long
Japanese 3-Llnk
The link amplitude equalizer responses are given in the following table.
Link Amplitude Equalizer
Frequency
(Hz)
Gain Relative to 1700 Hz (dB)
U.S. Survey Long
-0.27
-0.16
+0.33
+1.54
+5.96
+8.65
1000
1400
2000
2400
2600
3000
2-14
Japanele 3-Llnk
-0.13
-0.06
+0.16
+0.73
+2.61
+3.43
I
R208/201
Bell 208A/B and Bell 201C Modem
Table 7.
Mnemonic
Name
R208/2011nterface Memory Definitions (Continued)
Memory
Location
Description
LCEN
Loop Clock Enable
0:4:0
When control bit LCEN is a one, the transmitter clock tracks the receiver clock.
LDEN
Link Delay
Equalizer Enable
0:5:2
The link delay equalizer enable and select bits control a delay compromise equalizer in
the receive path according to the lollowing table:
LDEN
D3L
Curve Matched
o
X
1
1
1
No Equalizer
U.S. Survey Long
Japanese 3-Link
o
The link delay equalizer responses are given in the following table.
Link Delay Equalizer
Delay Relative to
1700 Hz (Microseconds)
Frequency
(Hz)
U.S. Survey Long
Japanese 3-Llnk
800
1200
1600
1700
2000
2400
2800
-498.1
- 188.3
-15.1
+0.0
-39.8
-423.1
-672.4
-653.1
- 398.5
-30.0
+0.0
+11.7
-117.1
-546.3
L2ACT
Remote Digital
Loopback Activate
0:4:1
When control bit L2ACT is a one, the receiver digital output is connected to the
transmitter digital input in accordance with CCITT recommendation V.54 loop 2.
L3ACT
Local Analog
Loopback Activate
0:4:7
When control bit L3ACT is a one, the transmitter analog output is coupled to the
receiver analog input through an attenuator in accordance with CCITT recommendation
V.54 loop 3.
L4ACT
Remote Analog
Loopback Activate
0:4:6
When control bit L4ACT IS a one, the receiver analog input is connected to the transmitter
analog output through a variable gain amplifier in a manner similar to recommendation
V.54 loop 4.
L4HG
Loop 4 High Gain
0:4:5
When control bit L4HG is a one, the loop 4 variable gain amplifier is set for + 16 dB,
and when at zero the gain is zero dB.
MHLD
Mark Hold
0:7:4
When control bit MHLD is a one, the transmitter input data stream is forced to all marks
(ones).
Period N Detector
1 :B:6
When status bit PNDET is a zero, it indicates a PN sequence has been detected. This
bit sets to a one at the end of the PN sequence.
Period Two
Detector
1 :8:2
When status bit P2DET is a zero, it indicates that a P2 sequence has been detected.
This bit sets to a one at the start of the PN sequence.
(None)
RAM Access T
0:F:0-7
Contains the RAM access code used in reading or writing chip 0 RAM locations via
word Y (0: 1 and 0:0).
(None)
RAM Access XB
2:5:0-7
Contains the RAM access code used in reading or writing chip 2 RAM locations via
word X (2:3 and 2:2).
(None)
RAM Access XS
1 :5:0-7
Contains the RAM access code used in reading or writing chip 1 RAM locations via
word X (1:3 and 1 :2).
(None)
RAM Access YB
2:4:0-7
Contains the RAM access code used in reading or writing chip 2 RAM locations via
word Y (2: 1 and 2:0).
2-15
•
Bell 208A/B and Bell 201C Modem
R208/201
Table 7.
Mnemonic
Name
R208/201 Interface Memory Definitions (Continued)
Memory
Location
Description
(None)
RAM Access YS
1 :4:0-7
Contains the RAM access code used in reading or writing chip 1 RAM locations via
word Y (1: 1 and 1 :0).
(None)
RAM Data XBL
2:2:0-7
Least significant byte of 16-bit word X used in reading or writing RAM locations in chip 2.
(None)
RAM Data XBM
2:3:0-7
Most significant byte of 16·bit word X used in reading or writing RAM locations in chip 2.
(None)
RAM Data XSL
1 :2:0-7
Least significant byte of 16·bit word X used in reading or writing RAM locations in chip 1.
(None)
RAM Data XSM
1 :3:0-7
Most significant byte of 16·bit word X used in reading or writing RAM locations in chip 1.
(None)
RAM Data YBL
2:0:0-7
Least significant byte of 16·bit word Y used in reading or writing RAM iocations in chip 2.
(None)
RAM Data YBM
2:1 :0-7
Most significant byte of 16·bit word Y used in reading or writing RAM locations In chip 2.
(None)
RAM Data YSL
1 :0:0-7
Least significant byte of 16-bit word Y used in reading or writing RAM locations in
chip 1. Shared by parallel data mode for presenting channel data to the host
microprocessor bus. See 'Receiver Data.'
(None)
RAM Data YSM
1:1 :0-7
Most significant byte of 16·bit word Y used in reading or writing RAM locations in chip 1.
(None)
RAM Data YTL
0:0:0-7
Least significant byte of 16-bit word Y used in reading or writing RAM locations in
chip O. It is shared by parallel data mode and DTMF dialing (see Transmitter Data).
(None)
RAM Data YTM
0:1 :0-7
Most significant byte of 16·byte word Y used in reading or writing locations in chip O.
RBDA
Receiver Baud
Data Available
2:E:0
Status bit RBDA goes to a one when the receiver writes data into register 2: O. The bit goes
to a zero when the host processor reads data from register 2: O.
RBIA
Receiver Baud
Interrupt Active
2:E:7
This status bit is a one whenever the receiver baud rate device is driving IRQ low. In
idle mode the interrupts from chip 2 occur at half the baud rate. During diagnostic access
in data mode, the interrupts occur at the baud rate.
RBIE
Receiver Baud
Interrupt Enable
2:E:2
When the host processor writes a one in the RBIE control bit, the IRQ line of the
hardware interface is driven to zero when status bit RBDA is a one.
(None)
Receiver
Configuration
1 :6:0-5
The host processor configures the receiver by writing a control code into the receiver
configuration field in the interface memory space (see RSB).
Receiver Configuration Control Codes
Control codes for the modem receiver configuration are:
Configuration Code (Hex)
Receiver Configuration
18
12
10
22
21
02
01
15
11
08
Bell 208/201 Auto Configuration·
Bell 208A1B
V.26B/Bell 201C
V.27 4800 Long
V.27 2400 Long
V.27 4800 Short
V.27 2400 Short
V.26A 2400
V.261200
Tone Detector
·When this configuration is selected, the receiver will detect a Bell 208 or
V.26B/Bell 201C handshake and configure itself accordingly.
After writing the auto configuration code 18h in RCONF, the DSP will change the code
to a 16(hex). If a Bell 208 carrier is received, the modem will auto configure itself
accordingly and the configuration code will remain a 16(hex). However, if a Bell 201
carrier is received, the modem Will auto configure Itself to Bell 201 and change the
receiver configuration code to a 14(hex).
2-16
Bell208A/B and Bell201C Modem
R208/201
Table 7.
Mnemonic
Name
R208/201 Interface Memory Definitions (Continued)
Memory
Location
Description
(None)
Receiver Data
1 :0:0-7
The host processor obtains channel data from the receiver in the parallel data mode
by reading a data byte from the receiver data register. The data is divided on baud
boundaries as is the transmitter data. When using receiver parallel data mode, the
registers 1 : 3 through 1 : 0 can not be used for reading the chip 1 RAM.
RPDM
Receiver Parallel
Data Mode
1 :7:4
When control bit RPDM is a one, the receiver supplies channel data to the receiver data
register (1 : 0) as well as to the hardware serial data output. (See Receiver Data)
RSB
Receiver Setup Bit
1 :E:3
When the host processor changes the receiver configuration or the RTH field, the host
processor must write a one in the RSB control bit. RSB goes to zero when the changes
become effective. Worst case setup time is 2 baud times.
RSDA
Receiver Sample
Data Available
1:E:0
Status bit RSDA goes to a one when the receiver writes data to register 1 : O. RSDA
goes to a zero when the host processor reads data from register 1 : O.
RSIA
Receiver Sample
Interrupt Active
1 :E:7
This status bit is a one whenever the receiver sample rate device is driving IRQ to zero.
RSIE
Receiver Sample
Interrupt Enable
1 :E:2
When the host processor writes a one in the RSIE control bit, the IRQ line of the
hardware interface is driven to zero when status bit RSDA is a one.
RTDIS
Receiver Training
Disable
1 :7:0
When control bit RTDIS is a one, the receiver is prevented from recognizing a training
sequence and entering the training state.
RTH
Receiver Thresnold
Field
1 :7:6,7
The receiver energy detector threshold is set by the RTH field according to the following
codes (see RSB):
RTH
RLSD On
0
1
2
3
> -43
>-33
>-26
> -16
dBm
dBm
dBm
dBm
RLSD Off
< -48 dBm
<-38 dBm
< -31.dBm
< -21 dBm
RTS
Request-ta-Send
0:7:7
When control bit RTS goes to a one, the modem begins a transmH sequence. It
continues to transmit until RTS is reset to zero, and the turn-off sequence has been
completed. This input bit parallels the operation of the hardware RTS control input.
These inputs are ORed by the modem.
SOlS
Scrambler Disable
0:7:5
When control bit SOlS is a one, the transmitter scrambler circuit is removed from the
data path.
SEPT
Short Echo
Protector Tone
0:7:0
When control bit SEPT is a one, the echo protector tone is 30 ms long rather than 185 ms.
SQH
Receiver Squelch
1 :F:7
When control bit SQH is set to a one, the receiver is squelched, RLSD is turned off and
RXD is clamped to all marks.
SWRT
Sample Write
1 :7:3
When control bit SWRT is a one, the RAM write operation is enabled for chip 1.
TBA
Transmitter Buffer
Available
O:E:O
This status bit resets to zero when the host processor writes data to transmitter data
register 0: O. When the transmitter empties register 0: 0, this bit sets to a one. During a
RAM access in chip 0, when TBA is a one the host can perform either a RAM read or
write depending on the state of bit 0: 6: 3 (see Transmitter Configuration).
TIA
Transmitter
Interrupt Active
0:E:7
This status bit is a one whenever the transmitter is driving IRQ to a zero.
TIE
Transmitter
Interrupt Enable
0:E:2
When the host processor writes a one in control bit TIE, the IRQ line of the hardware
interface is driven to zero when status bit TBA is at a one.
2-17
Bell 208A/B and Bell 201C Modem
R208/201
Table 7. R208/201 Interface Memory Definitions (Continued)
Mnemonic
TLVL
Name
Transmitter Level
Field
Memory
Location
0:4:2-4
Description
The transmitter analog output level is determined by eight TLVL codes, as follows:
TLVL
0
1
2
3
Transmitter Analog Output'
-1 dBm
-3dBm
-5 dBm
-7dBm
il
il
il
il
dB
dB
dB
dB
TLVL
Transmitter Anelog Output'
-9dBm
-11 dBm
-13 dBm
-15 dBm
4
5
6
7
il
il
i 1
il
dB
dB
dB
dB
'Each step above is a 2 dB change i 0.2 dB.
TOO
Train-on·Data
1 :6:6
When control bit TOO is a one, it enables the train·on-data algorithm to converge the
equalizer if the signal quality degrades sufficiently. When TOO is a one, the modem still
recognizes a training sequence and enters the force train state. A BER of approximately
10- 3 for 0.5 seconds initiates train·on·data.
TONE
Tone Detect
1 :9:2
TONE indicates with a zero the presence of energy in the 345-650 i 10 Hz frequency
range. For call progress purposes, the user may determine which tone is present by
determining the duty cycle of the TONE bIt.
TPDM
Transmitter Parallel
Data Mode
0:7:2
When control bit TPDM is a one, the transmitter accepts data for transmission from the
transmitter data register (0: 0). When TPDM is a zero channel data from the serial hardware
input TXD is accepted and the chip 0 RAM access is enabled.
(None)
Transmitter
Configuration'
0:6:0-7
The host processor configures the transmitter by writing a control byte into the transmitter
configuration register in its interface memory space. (See TSB.)
Transmitter Configuration Control Codes
Control codes for the modem transmitter configurations are:
Configuration Code (Hex)'
32
12
10
22
02
21
01
15
11
80
04
Configuration
Bell 208A1B Long
Bell 208A1B Short
V.26B/Bell 201C
V.27 4800 Long
V.27 4800 Short
V.27 2400 Long
V.27 2400 Short
V.2624OO
V.261200
Tone Transmit
DTMF Tone Transmit
'Note:
Bit 3 of the transmitter configuration register is used in the RAM access operation for
chip 0 (see bit TWRT).
Configuration Definitions
Definitions of the eight Transmitter Configurations are:
1. Bell 208. When any of the Bell 208 configurations are selected, the modem operates
as specified in the Bell 208A1B Standard.
2. V.26BIBell 201C. When V.26B/Bell 201C is selected, the modem operates as
speCified in the V.26B/Bell 201C Standard. RTS/CTS time is programmable.
3. V.27. When any of the V.27 configurations are selected, the modem operates as
specified in CCITI Recommendation V.27 ter.
4. V.26. When any of the V.26 configurations are selected, the modem operates as
specified in CCITI Recommendation V.26. RTS/CTS time is programmable.
5. Tone Transmit. In this configuration, activating signal RTS causes the modem to
transmit a tone at a single frequency specified by two registers in the host interface
memory space containing the frequency code. The most significant bits are specified
in the FREOM register (0: 3). The least significant bits are specified in the FREOL
register (0:2). The least significant bit represents 0.146486 Hz ±0.01%. The frequency
generated is: f =0.146486 (256 FREOM + FREOL) Hz iO.Ol%.
6. DTMF Tone Transmit. In this configuration, activating signal RTS causes the modem
to transmit a Dual Tone Multi-Frequency (DTMF) tone specified by the code loaded
in the Dial Digit Register (DDR, 0:0). The twelve codes, their aSS{lCiated dial digits
and tone pairs are as follows:
2-18
R20S/201
Bell 20SAlB and Bell 201C Modem
Table 7.
Mnemonic
Name
R208/201 Interface Memory Definitions (Continued)
Memory
Location
Description
Dial Digit Register (DDR)
Hexadecimal Code
Tone Pair
(Hz)
Dial Digit
00
01
02
03
04
05
06
07
08
09
OA
OB
0
1
2
3
4
5
6
7
8
9
941
697
697
697
770
770
770
852
852
852
941
941
*#
1336
1209
1336
1477
1209
1336
1477
1209
1336
1477
1209
1477
•
Figure 6 shows the utilization of the DTMF Tone TransmIt confIguratIon m an auto
dIaling application.
(None)
Transmitter; DDR;
RAM Data YTL
0:0:0-7
1. The host processor transmits data in the parallel mode by wrotlng a data byte to the
transmitter data regIster. The data IS d,v,ded on baud boundaries, as follows:
NOTE
Data is transmitted bIt zero first
Bits
I
Configuration
7
Bell 208A1B
V.2748OO
Not Used
Bell 201C, V.26,
V.2724OO
6
Baud 3
5
I
4
I
3
2
Baud 1
Baud 2
I
1
I
0
Baud 0
I
Baud 1
I
Baud 0
2. RegIster 0.0 is used to transmIt DTMF dIgIts when the transmitter is configured in
the DTMF tone transmit mode.
3. Register 0·0 is a RAM data regIster used for reading or writing the least significant
byte of the 16-bit Y word In Chip 0 when TPDM IS a zero and no tone or DTMF tone
transmIssIon IS occurring.
TSB
Transmitter Setup
Bit
0:E:3
When the host processor changes the transmitter configuration, the host must write a
one in this control bit. TSB goes to a zero when the change becomes effectIve. Worst
case setup lime is 2 baud + turnoff sequence + tramlng (if applicable).
TIDIS
Transmitter Train
Disable
0:7:6
When control bIt TIDIS is a one, the transmitter does not generate a training sequence
at the start of transmIssion. W,th trammg dIsabled, RTS/CTS delay IS less than two
baud times.
TWRT
Transmitter Write
0:6:3
When control bIt TWRT IS a one, the RAM write operation is enabled for chip o.
T2
T/2 Equalizer
1 :7:1
When control bit T2 IS a one, an adaptIve equalizer WIth two taps per baud IS used.
When T2 is a zero, the equalizer has one tap per baud. The total number of taps
remains the same for both cases.
0:7:1
When control bit XCEN is a one, the transmitter timing is established by the external
clock supplied at the hardware mput XTCLK, pIn 22A. The clock appearing at the
XTCLK input will appear at the TDCLK output.
Select
XCEN
External Clock
Enable
2-19
R208/201
Bell 208A/B and Bell 201C Modem
Table 8.
No.
RAM Access Codes
Function
1 DTMF Low Frequency
Amplitude1
2 DTMF High Frequency
Amplltude1
3 Interdign Delay1
4 DTMF Tone Duration1
5
6
7
8
9
Received Signal Samples
Demodulator Output
Low Pass Fitter Output
Average Energy
AGC Gain Word
10 Equalizer Input
11 Equalizer Tap Coefficients
12 Unrotated Equalizer
Output
13 Rotated Equalizer Output
(Received Points)
14 Decision Points
Ideal Points
15 Error
16 Rotation Angle
17 Frequency Correction
18 EQM
19 Dual Point
20 Unscrambled
Synchronizing Segment
21 Scrambled
Synchronizing Segment
Bell201C and V.26 Programmable Turn-On Sequence
XAccesa YAccesa
Code
Code
(Hex) Register
Chip (Hex)
° -° °° -
88
0,1
08
0,1
89
09
0,1
0,1
The turn-on sequence for Bell 201C and V.26 modes is composed of two segments. The first segment consists of unscrambled mark. The second sequence consists of scrambled mark.
The segments may be independently programmed for a desired
length of time.
When Bell201C or V.26 mode is chosen, the default RTS-crs
delay is 26.6 ms of unscrambled mark and no scrambled segment. If using only the unscrambled segment, OOIS and SOlS
must be set to a 1.
1
1
1
1
1
CO
03
04
DC
81
Not Used
54
Not Used
Not Used
2,3
0,1,2,3
0,1,2,3
2,3
2,3
2
2
CO
81-AO
40
01-20
0,1,2,3
0,1,2,3
Total minimum time recommended
Total maximum time .. gOO ms.
2
2
E1
A2
61
22
0,1,2,3
0,1,2,3
Turn-on word .. (time in ms I 0.833) - 1, convert to hex and
subtract from FFFF. Write this value into registers 1 & 0 of chip O.
2
E2
62
0,1,2,3
For example, for a RTS-CTS delay of 150 ms:
2
2
2
2
2
53
93
0,1,2,3
0,1
2,3
2,3
0,1,2,3
0,1
13
0,1
E3
63
Not Used
00
Not Used
AA
Not Used
A7
AE
2E
° -°
RTS-CTS delay .. (unscrambled + scrambled) baud times ± 1
baud time)
1 baud time .. 111200 = 0.833 ms
= 15 ms.
(150 I 0.833) - 1 .. 179 (decimal) .. B3 (hex), FFFF - B3
- FF4C
Write FF into register 1 and write 4C into register 0 using the
appropriate access code listed in Table 8. (See interface memory
section for RAM Write procedure.)
Note: When using both unscrambled and scrambled segments,
the unscrambled segment should be limited to 10 ms or less for
compatibility with existing V.26 modems.
Auto Dial Sequence
The Figure 6 flowchart defines the auto dial sequence via the
microprocessor interface memory. The modem timing for the
auto dialer accounts for OTMF tone duration and interdigit delay.
The default tone duration is 95 ms and the default interdigit delay
is 71 ms. The default amplitudes for the high and low frequencies
are - 4 dBm and - 6 dBm, respectively. The above four parameters can be changed by performing a RAM write.
2-20
Bell208A/B and Bell201C Modem
R208/201
•
Figure 6.
R208/201 Auto Dial Sequence
2-21
Bell 208A/B and Bell 201C Modem
R208/201
PERFORMANCE
TYPICAL PHASE JITTER
TYPICAL BIT ERROR RATES
At 2400 bps, the modem exhibits a bit error rate of 1
RTS
~
CTS
I'
USRT
(OPTIONAL)
~
,
'-
L---
JI- ::r
r •.
..
..
0'.scoPE'
• ,.
TXD
EYEX
XTCLK
EYEY
RLSD
xt
EYESYNC
ty
EYE
PATTERN
GENERATOR
EYECLK
RXD
,.
RDCLK
TBCLK'-
R96DP
MODEM
RBCLK
+12V
+5V
POWER
SUPPLY
GND
READ
h
9600 bps
Serial channel data
Tl2 equalizer
Standard echo protector tone
- 43 dBm threshold
Cable and link equalizers disabled
Train-On-Data disabled
TDCLK
~_
~
•
•
•
•
•
•
•
-12V
WRITE
~
DATA BUS (8)
HOST
PROCESSOR
(DTE)
TXA
Di
ADDRESS BUS (4)
RSI
RXA
DECODER .... cli 12t
.~
LINE
INTERFACE
CSI
POR
AUXIN
IRQ
+5
A
I
Figure 1. R96DP Functional Interconnect Diagram
2-28
TELEPHONE
LINE
R96DP
9600 bps Data Pump Modem
Table 4.
Name
Type'
DIN
Pin No.
DIP'
Pin No.
R96DP Hardware Circuits
Description
Name
A. OVERHEAD:
Ground (A)
Ground (D)
AGND
DGND
PWR
+ 12 volts
-12 volts
POR
PWR
PWR
1I0B
31C,32C
30,31
Analog Ground Return
3C,8C, 29,37,53 Digital Ground Return
5A,10A
19C,23C, 1,45,61 + 5 volt supply
26C,30C
15A
32
+ 12 volt supply
12A
36
- 12 volt supply
13C
2
Power·on·reset
B. MICROPROCESSOR INTERFACE:
1I0A
1I0A
1I0A
1I0A
1I0A
1I0A
1I0A
1I0A
lC
lA
2C
2A
3A
4C
4A
5C
3
4
5
6
7
8
9
10
RS3
RS2
RSI
RSO
IA
IA
IA
IA
6C
6A
7C
7A
16
17
18
19
CSO
IA
10C
20
CSI
IA
9C
21
CS2
IA
9A
13
IA
IA
OB
12C
11A
11C
14
12
11
READ
WRITE
IRQ
Description
C. V.24 INTERFACE:
+5 volts
07
06
05
04
D3
02
01
DO
DIN
DIP'
Type' Pin No. Pin No.
RDCLK
TDCLK
XTCLK
RTS
CTS
TXD
RXD
RLSD
)..... ,,,. ,
21A
23A
22A
25A
25C
24C
22C
24A
OC
OC
IB
IB
OC
IB
OC
OC
23
46
51
50
49
48
26
27
Receive Data Clock
Transmit Data Clock
External Transmit Clock
Request·te-Send
Clear·te-Send
Transmitter Data
Receiver Data
Received Line Signal
Detector
22
47
Receiver Baud Clock
Transmitter Baud Clock
31A
32A
30A
34
33
Transmitter Analog Output
Receiver Analog Input
Auxiliary Analog Input
15C
14A
14C
13A
56
55
57
58
D. ANCILLARY CIRCUITS:
RBCLK
TBCLK
,
OC
OC
26A
27C
E. ANALOG SIGNALS:
TXA
RXA
AUXIN
AA
AB
AC
-
F. DIAGNOSTIC:
}
Register Select
(4 Bits)
EYEX
EYEY
EYECLK
EYESYNC
Chip Select
Transmitter Device
Chip Select Receiver
Sample Rate Device
Chip Select Receiver
Baud Rate Device
Read Enable
Write Enable
Interrupt Request
Table 5.
OC
OC
OA
OA
Eye Pattern
Eye Pattern
Eye Pattern
Eye Pattern
Signal
Data-X Axis
Data-Y Axis
Clock
Synchronizing
Notes:
1. Refer to Table 5 for digital circuit interface characteristics and
Table 7 for analog circuit interface characteristics.
2. Pins not used on the DIP Version: 15, 24, 25, 28, 35, 38, 39,
40,41,42,43,44,52,54,59,60
3. Unusd inputs tied to + 5V or ground require individual 10K II
series resistors.
Digital Interface Characteristics
Input/Output Type
Symbol
Parameter
Units
IA
IB
IC
Input Voltage, High
V
2.0 Min.
2.0 Min.
2.0 Min.
Vil
Input Voltage, Low
V
0.8 Max.
0.8 Max.
0.8 Max.
VOH
Output Voltage, High
V
VOL
Output Voltage, Low
liN
Input Current, Leakage
VIH
Output Current, High
mA
-0.1 Max.
mA
1.6 Max.
Il
Output Current, Leakage
p.A
Ipu
Pull·up Current
(Short Circuit)
p.A
pF
Capacitive Drive
pF
Circuit Type
1. I Load
2. I Load
1I0B
5.25 Max.
2.0 Min.
0.8 Max.
0.8 Max.
2.4 Min.'
2.4 Min.3
0.4 Max.2
0.4 Max.-
1.6 Max.
1.6 Max.
±10 Max.
5
-240 Max.
-10 Min.
-240 Max.
-10 Min.
5
20
TIL
w/Pull-up
TIL
w/Pull-up
Notes
3. I Load = -40 p.A
4. VIN = 0.4 to 2.4 Vdc, Vee
2-29
-260 Max.
-lao Min.
-240 Max.
-10 Min.
100
100
TIL
= - 100 p.A
= 1.6 mA
0.4 Max. 2
110 A
2.0 Min.
±2.5 Max.'
Output Current, Low
Capacitive Load
0.4 Max. 2
0.4 Max. 2
IOH
Co
OC
±2.5 Max.
IOl
Cl
OB
2.4 Min.'
V
p.A
OA
TIL
100
10
40
100
100
3-State
Open-Drain
Open-Drain Open-Drain
w/Pull-up Transceiver w/Pull-up
5. I Load
= 5.25 Vdc
= 0.36 mA
•
9600 bps Data Pump Modem
R96DP
This configuration is suitable for performing high speed data
transfer using the serial data port. Individual features are discussed in subsequent paragraphs.
Received Line Signal Detector (RLSD)
For V.27 bis/ter or V.29, RLSD turns on at the end of the training
sequence. If training is not detected at the receiver, the RLSD offto-on response time is 15 ± 10 ms. The RLSD on-ta-off response
time for V.27 is 10 ± 5 ms and for V.29 is 30 ± 9 ms. Response
times are measured with a signal at least 3 dB above the actual
RLSD on the threshold or at least 5 dB below the actual RLSD off
threshold.
V.24 INTERFACE
Eight hardware circuits provide timing, data, and control signals for
implementing a serial interface compatible with CCITT Recommendation V.24. These signals interface directly with circuits using TTL
logic levels (OV, + 5V). These TTL levels are suitable for driving the
short wire lengths or printed circuitry normally found within standalone modem enclosures or equipment cabinets. For driving longer
cables, the voltage levels and connector arrangement recommended by EIA standard RS-232-C are preferred.
The RLSD on-to-off response time ensures that all valid data bits
have appeared on RXD.
Four threshold options are provided:
1. Greater than - 43 dBm (RLSD on)
Less than - 49 dBm (RLSD off)
The sequence of events leading to successful data transfer from
transmitter to receiver is:
1. The transmitter is activated and a training sequence
IS
2. Greater than - 33 dBm (RLSD on)
Less than - 38 dBm (RLSD off)
sent.
3. Greater than - 26 dBm (RLSD on)
Less than - 31 dBm (RLSD off)
2. The receiver detects channel energy above the prescribed
threshold level and synchronizes its operation to the
transmitter.
4. Greater than - 16 dBm (RLSD on)
Less than - 21 dBm (RLSD off)
3. Data transfer proceeds to the end of the message.
NOTE
4. The transmitter turns off after insuring that all data has had
time to be recovered at the receiver output.
Performance may be at a reduced level when the
received signal is less than - 43 dBm.
Transmitted Data (TXD)
A minimum hysteresis action of 2 dB exists between the actual
off-to-on and on-to-off transition levels. The threshold level and
hysteresis action are measured with an unmodulated 2400 Hz
tone applied to the receiver's audio input (RXA).
The modem obtains serial data from the local DTE on this input.
Received Data (RXD)
Transmit Data Clock (TDCLK)
The modem presents received data to the local DTE on this
output.
The modem provides a Transmit Data Clock (TDCLK) output with
the following characteristics:
Request To Send (RTS)
1. Frequency. Selected data rate of 9600, 7200, 4800, or
2400 Hz(±0.01%).
RTS ON allows the modem to transmit data on TXD when CTS
becomes active. The responses to RTS are shown in Table 6.
2. DutyCyc/e. 50 ±1%.
Clear To Send (CTS)
TDCLK is provided to the user in synchronous communications
for USRT timing. In this case Transmit Data (TXD) must be stable
during the one I's periods immediately preceding and following
the rising edge of TDCLK.
CTS ON indicates to the terminal equipment that the modem will
transmit any data which are present on TXD. CTS response times
from an ON condition of RTS are shown in Table 6.
External Transmit Clock (XTCLK)
The time between the on-to-off transition of RTS and the on-to-off
transition of crs in data state is a maximum of 2 band times for
all configurations.
Table 6.
In synchronous communication where the user needs to supply
the transmit data clock, the input XTCLK can be used. The clock
supplied at XTCLK must exhibit the same characteristics of
TDCLK. The XTCLK input is then reflected at TDCLK.
RTS-CTS Response Times
RTS-CTS Turn-On Time
Specification
V.29 (All data rates)
V.27 4800 bps long
V 27 4800 bps short
V.27 2400 bps long
V.27 2400 bps short
Echo Protector
Tone Disabled
253
708
50
943
67
ms
ms
ms
ms
ms
Receive Data Clock (RDCLK)
Echo Protector"
Tone Enabled
438
9t3
255
1148
272
The modem provides a Receive Data Clock (RDCLK) output in
the form of a 50 ± 1% duty cycle squarewave. The low-to-high
transitions ofthis output coincide with the center of received data
bits. RDCLK is provided to the user in synchronous communications for USRT timing. The timing recovery circuit is capable of
tracking a ± .01 % frequency error in the associated transmit timing source.
ms
ms
ms
ms
ms
" For short echo protector tone, subtract 155 ms from RTS-CTS
turn-on time.
2-30
R96DP
9600 bps Data Pump Modem
to pull the IRQ line high when all IRQ drivers are off (i.e., it must
overcome the leakage currents). The resistor value should be
large enough to limit the driver sink current to a level acceptable
to each driver. For the case where only the modem IRQ driver is
used, a resistor value of 5.6K ohms ± 20%, 0.25 watt, is
sufficient.
MICROPROCESSOR INTERFACE
Eight hardware circuits provide address, data, control, and interrupt signals for implementing a parallel interface compatible with
an 8080 microprocessor. With the addition of a few external logic
gates, the interface can be made compatible with a wide variety
of microprocessors such as 6500, 6800, or 68000.
ANALOG SIGNALS
The microprocessor interface allows a host microprocessor to
change modem configuration, read or write channel data as well
as diagnostic data, and supervise modem operation by means of
soft strappable control bits and modem status bits. The significance of the control and status bits and methods of data interchange are discussed in a later section devoted to software circuits. This section describes the operation of the interface from a
hardware standpoint.
The analog signal characteristics are described in Table 7.
Table 7.
Chip Select (CSO-CS2) and
Register Selects (RSO-RS3)
The signal processor to be accessed is selected by grounding
one of three unique chip select lines, CS2, CS1 or CSO. The
selected chip decodes the four address lines, RS3 through RSO,
to select one of sixteen internal registers. The most significant
address bit (~) is RS3 while the least significant address bit (20)
is RSO. Once the address bits have been decoded, the selected
register can be read from or written into via an 8-bit parallel data
bus, 07 through DO. The most significant data bit (27) is 07 while
the least significant data bit (2°) is DO.
Analog Interface Characteristics
Name
Type
TXA
AA
The transmitter output is 604 ohms ± lOA>.
Characteristics
RXA
AB
The receiver input impedance is 60K ohms
±23%.
AUXIN
AC
The auxiliary analog input allows access to the
transmitter for the purpose of interfacing with
user provided equipment. Because this is a
sampled data input, any signal above 4800 Hz
will cause aliasing errors. The input impedance
is 1K ohms, and the gain to transmitter output is
the TLVL setting + 0.6 dB -1.4 dB.
Transmitter Analog (TXA)
The TXA line is an output suitable for driving an audio transformer or data access arrangement for connection to either
leased lines or the public switched telephone network. The output structure of TXA is a low impedance amplifier in series with
an internal 604 ohm ± 1% resistor to match a standard telephone load of 600 ohms.
Read Enable (READ) and
Write Enable (WRITE)
Reading or writing is activated by pulsing either the READ line
high or the WRITE line low. During a read cycle, data from the
selected register is gated onto the data bus by means of threestate drivers. These drivers force the data lines high for a one bit
or low for a zero bit. When not being read, the three-state drivers
assume their off, high-impedance, state. During a write cycle,
data from the data bus is copied into the selected register, with
high and low bus levels representing one bits and zero bits,
respectively. The timing required for correct read/write cycles is
illustrated in Figure 2. logic necessary to convert the single RNi
output from a 65XX series microprocessor to the separate READ
and WRITE signals required by the modem is shown in Figure 3.
Receiver Analog (RXA)
RXA is an input to the receiver from an audio transformer or
data access arrangement. The input impedance is nominally
60K ohms but a factory select resistor allows a variance of 23%.
The RXA input must be shunted by an external resistor in order to
match a 600 ohm source. A 604 ohm ± 1 % resistor is
satisfactory.
Some form of transient protection for TXA and RXA is recommended when operating directly into a transformer. This protection may take the form of back-to-back zener diodes across the
transformer or a varistor across the transformer.
Interrupt Request (IRQ)
The final signal on the microprocessor interface is Interrupt
Request (IRQ). This signal may be connected to the host microprocessor interrupt request input in order to interrupt host program execution for modem service. The use of IRQ is optional
and the method of software implementation is described in a
subsequent section, Software Circuits. The IRQ output structure
is an open-drain field-effect-transistor (FET). This form of output
allows IRQ to be connected in parallel to other sources of interrupt. Any of these sources can drive the host interrupt input low,
and the interrupt servicing process continues until all interrupts
have been cleared and all IRQ sources have returned to their
high impedance state. Because of the open-drain structure of
IRQ, an external pull-up resistor to + 5 volts is required at some
point on the IRQ line. The resistor value should be small enough
Auxiliary Input (AUXIN)
AUXIN provides a means of inserting audio signals into the
modem output stage. Because this input is summed with the
transmitter output prior to the transmitter low pass filter and compromise equalizers, the AUXIN signal is sampled by a compensated sample-and-hold circuit at a rate of 9600 samples-persecond. Any signal above 4800 Hz on the AUXIN line will be
aliased back into the passband as noise. One application for
AUXIN is to inject dual-tone multifrequency (DTMF) touch-tone
signals for dialing, however, the source of these tones must be
well filtered to eliminate components above 4800 Hz. The input
impedance of AUXIN is 1 K ohm. The gain from AUXIN to TXA is
the same as the selected transmit level + 0.6 dB - 1.4 dB.
2-31
•
R96DP
9600 bps Data Pump Modem
WRITE
READ
CSi
(i
= 0,1)
RSi
(i
= 0-3)
READ
(i
=
Di
0-7)
Characteristic
CSi, RSi setup time prior
to Read or Write
Data access time after Read
Data hold time after Read
CSi, RSi hold time after
Read or Write
Write data setup time
Write data hold time
Write strobe pulse width
Figure 2.
Symbol
Min
TCS
TDA
TDH
30
TCH
TWOS
TWDH
TWR
10
75
10
75
10
Max
Units
140
50
ns
ns
ns
ns
ns
ns
ns
Microprocessor Interface Timing Diagram
~______1~2~C~
READ
R96DPMODEM
R/W
Figure 3.
R/W to READ WRITE Conversion Logic
2-32
9600 bps Data Pump Modem
R96DP
or RS-232 recommendations since they mark the baud interval
for the transmitter and receiver rather than the data rate. The
baud clocks can be useful in identifying the order of data bits in a
baud (e.g., for multiplexing data, etc.). Both signals are high
active, meaning the baud boundaries occur on falling edges. The
first bit in each baud begins with the falling edge of the corresponding baud clock.
DIAGNOSTIC SIGNALS
EYEX, EYEY, EYECLK, and EYESYNC
Four card edge connections provide the timing and data necessary to create an oscilloscope quadrature eye pattern. The eye
pattern is simply a display of the received baseband constellation. By monitoring this constellation, an observer can often identify common line disturbances as well as defects in the modulationl
demodulation process.
SOFTWARE CIRCUITS
The outputs EYEX and EYEY provide two serial bit streams containing data for display on the oscilloscope X axis and Y axis,
respectively. Since this data is in serial digital form it must first be
converted to parallel digital form by two serial-to-parallel converters and then to analog form by two D/A converters. A clock
for use by the serial-to-parallel converters is furnished by signal
EYECLK. A strobe for loading the D/A converters is furnished by
signal EYESYNC. Timing of these signals is illustrated in Figure 4. The EYEX and EYEY outputs furnish 9-bit serial words.
Since most serial to parallel conversion logic is designed for B-bit
words, an extra storage flip-flop is required for 9-bit resolution.
However, the ninth bit is not generally needed for eyepattern generation, and eight-bit hardware can be used if data is copied on
the rising edge of EYECLK rather than the falling edge.
Operation olthe microprocessor interface circuits was described
in the hardware section from the standpoint of timing and loadl
drive characteristics. In this section, operation of the microprocessor interface is described from a software standpoint.
The modem is implemented in firmware running on three speCial
purpose signal processors. These signal processors share the
computing load by performing tasks that are divided into areas.
These areas are partitioned into transmitter, baud rate,and sample rate devices.
INTERFACE MEMORY
Each signal processor can communicate with the host processor
by means of a specialized, dual-port, scratch-pad memory called
interface memory. A set of sixteen B-bit registers, labeled register 0 through register F, can be read from or written into by either
the host processor or signal processor. The host communicates
via the microprocessor interface lines shared between the two
signal processors. The signal processor communicates via its
internal 110 bus. Information transfer from SP RAM to interface
memory is accomplished by the signal processor logic unit moving data between the SP main bus and the SP 110 bus. Two of the
16 addressable interface memory registers (i.e., register 0 and
register E) have unique hardware connections to the interrupt
logic. It is possible to enable a bit in register E to cause an interrupt each time it sets. This interrupt can then be cleared by a read
or write cycle from the host processor to register O. This operation is discussed in detail later in this section.
ANCILLARY SIGNALS
Transmitter Baud Clock (TBCLK) and
Receiver Baud Clock (RBCLK)
Two clock signals called TBCLK and RBCLK are provided at the
modem connector. These signals have no counterpart in the V.24
L
EYESYNC
EYEX,
Memory maps of the 4B addressable registers in the modem are
shown in Figure 5. These registers may be read or written on any
host read or write cycle, but all eight bits of that register are
affected. In order to read a single bit or a group of bits in a register,
the host processor must mask out unwanted data. When writing
a single bit or group of bits in a register the host processor must
perform a read-modify-write operation. That is, the entire register
is read, the necessary bits are set or reset in the accumulator of
the host, then the original unmodified bits and the modified bits
are written back into the register of the interface memory.
rnv-;-v--; v--av--;-vz
EYEY~~
MSB
Figure 4.
LSB
Table B defines the individual bits in the interface memory. In the
Table 8 descriptions, bits in the interface memory are referred to
using the format Y:Z:Q. The chip number is specified by Y (0 or
1), the register number by Z (0 through F), and the bit number by
Q (0 through 7, with 0 = LSB).
Eye Pattern Timing
2-33
•
9600 bps Data Pump Modem
R96Dp·
Transmitter Interface Memory Chip 0 (CSO)
~
7
E
TIA
<'
8
5
4
3
Regl
-
A
-
9
-
8
-
7
RTS
C
B
•
·1
0
-
TBA
RAM ACCESS T
F
D
2
«
-
-
-
-
SDIS
MHLD
-
~
ITDIS
TSB
TIE
-
-
-
-
-
~
TPDM XCEN
EPT
SEPT
TRANSMIITER CONFIGURATION
-
-
5
CEQ
LAEN
L3ACT L4ACT L4HG
4
LDEN
A3L
3
D3L
L.2ACT LCEN
TLVL
FREQM
2
FREQL
1
RAM DATA YTM
0
RAM DATA YTL; TRANSMIITER DATA, DDR
V.
7
8
5
4
3
2
1
0
Bit
(-) Indicates .....rved for modem use only.
Receiver Interface Memory Chip 1 (CS1)
~
7
5
6
4
3
1
2
Receiver Interface Memory Chip 2 (CS2)
~
0
F
-
E
RSIA
-
A
-
9
-
FED
8
-
-
D
C
B
7
PNDET
ATH
IFIX
8
7
6
5
-
-
-
4
3
-
-
-
DDIS
10D
-
-
-
-
-
RSB
RSIE
-
-
-
P2DET
-
-
RPDM SWAT SWAT
-
F
RSDA
E
-
D
CDET
B
-
-
A
-
-
9
-
-
8
T2
ATDIS
7
-
RBIA
C
6
RECEIVER CONFIGURATION
-
-
-
-
-
-
-
-
-
-
5
RAM ACCESS XS
5
RAM ACCESS XB
4
RAM ACCESS YS
4
RAM ACCESS VB
3
RAM DIQJ\ XSM
3
RAM DATA XBM
2
RAM DATA XSL
2
RAM DATA XBL
1
RAM DATA YSM
1
RAM DIQJ\ VBM
0
RAM DATA YSL; RECEIVER DATA
0
RAM DATA VBL
~
2
1
0
Reglate
Reglate
7
6
5
4
3
2
1
/.
0
for modem use only.
Figure 5.
7
8
5
4
3
-
-
-
RBDA
-
-
-
-
-
-
2
Bit
Bit
( ) Indicates .._
RBIE
(-) Indica'.. reeerved for modem uee only.
Interface Memory Map
2-34
-
1
-
-
0
R96DP
9600 bps Data Pump Modem
Table 8.
Mnemonic
Name
R96DP Interface Memory Definitions
Memory
location
Description
A3l
Amplitude 3·link
Select
0:5:1
A3l IS used in conjunction with LAEN. When A3l is a one the Japanese 3 link
equalizer is selected and when A3l is a zero the U.S. Survey long link equalizer is
selected.
BWRT
Baud Write
1 :7:2
When control bit BWRT is a one, the RAM write operation IS enabled for Chip 2.
CEQ
Cable Equalizer
Field
0:5:4,5
The CEQ Control field simultaneously controls amplitude compromise equalizers in both
the transmit and receive paths. The following tables list the possible cable equalizer
selection codes and responses.
CEQ
Cable length (0.4 mm diameter)
0
1
2
3
0.0
1.8 km
3.6 km
7.2 km
Cable Equalizer Nominal Gain
CEQ CODE 1
Gain Relative to 1700 Hz (dB)
Frequency
(Hz)
Transmitter
Receiver
700
1500
2000
3000
-0.99
-0.20
+0.15
+ 1,43
-0.94
-0.24
+0.31
+ 1.49
CEQ CODE 2
Gain Relative to 1700 Hz (dB)
Frequency
(Hz)
Transmitter
Receiver
700
1500
2000
3000
-2.39
-0.65
+0.87
+3.06
-2.67
-0.74
+ 1.02
+3.17
CEQ CODE 3
Gain Relative to 1700 Hz (dB)
Frequency
(Hz)
Transmitter
Receiver
700
1500
2000
3000
-3.93
-1.22
+1.90
+4.58
-3.98
-1.20
+1.81
+4.38
Unless a problem with traming or high bit error rate is encountered, most applications
operate successfully with no cable equalizer selected.
CDET
Carrier Detector
1 :B:O
When zero, status bit CDET indicates that passband energy is being detected, and
that a training sequence is not in process. CDET goes to a zero at the start of the
data state, and returns to a one at the end of the received signal. CDET activates
up to 1 baud time before RlSD and deactivates within 2 baud times after RlSD. If the
FED bit goes to a zero and no P2 sequence is detected, the CDET bit goes to zero
within 5 to 25 ms indicating that the receiver has entered the data state without a
training sequence.
DDIS
Descramble Disable
1 :7:5
When control bit DDIS IS a one, the receiver descrambler circuit is removed from the
data path.
DDR
Dial Digit Register
0:0:0-7
DDR IS used to tell the modem which DTMF digit to transmit (see Transmitter Data).
D3l
Delay 3·Link Select
0:5:0
D3l is used In conjunction with LDEN When D3L is a one the Japanese 3 link
equalizer is selected and when D3L is a zero the U.S. Survey long link equalizer is selected.
2-35
•
9600 bps Data Pump Modem
R96DP
Table 8.
Mnemonic
Name
R96DP Interface Memory Definitions (Continued)
Memory
Location
Description
EPT
Echo Protector
Tone
0:7:3
When control bit EPT is a one, an unmodulated carrier IS transmitted for 185 ms
(optionally 30 ms) followed by 20 ms of no transmitted energy at the start of transmission.
This option is available in the V.27 and V.29 Configurations, although it is not specified
in the CCITT V 29 recommendation.
FED
Fast Energy
Detector
1 :9:6
When status bit FED is a zero, it indicates that energy above the receiver threshold is
present in the passband, and the receiver is searching for the training sequence.
(None)
FREOUFREOM
0:2:0-7,
0:3:0-7
The host processor conveys tone generation data to the transmitter by writing a 16-bit
data word to the FREOL and FREOM registers In the interface memory space, as
shown below:
FREQM Register (0:3)
Bit:
Data Word:
I
I
7
2 '5
I
I
6
214
I
I
I
I
5
2 '3
I
I
4
2'2
3
2"
I
I
2
2'0
I
I
1
29
I
I
0
28
FREQL Register (0: 2)
Bit:
Data Word:
I
I
7
27
I
I
6
26
I
I
I
I
5
25
4
24
I
I
3
23
I
I
2
22
I
I
1
2'
I
I
0
20
The frequency number (N) determines the frequency (F) as follows:
F = (0.146486) (N) Hz ±0.01%
Hexadecimal frequency numbers (FREOL, FREOM) for commonly generated tones are
given below:
FREQM
FREQL
Frequency (Hz)
OC
52
55
00
55
00
462
1100
1650
1850
2100
10
2C
31
38
IFIX
Eye Fix
1 :6:7
When control bit IFIX is a one, the senal data on EYEX and EYEY reflect the rotated
equalizer output and do not follow the data selected by RAM ACCESS XB and RAM
ACCESS VB.
LAEN
Link Amplitude
Equalizer Enable
0:5:3
The link amplitude equalizer enable and select bits control an amplitude compromise
equalizer in the receive path according to the follOWing table:
LAEN
A3L
Curve Matched
0
1
1
X
0
1
No Equalizer
U.S. Survey Long
Japanese 3-Link
The link amplitude equalizer responses are given
In
the following table.
Link Amplitude Equalizer
Frequency
(Hz)
Gain Relative to 1700 Hz (dB)
U_S. Survey Long
-0.27
-0.16
+0.33
+1.54
+5.98
+8.65
1000
1400
2000
2400
2800
3000
2-36
Japanese 3·Link
-0.13
-0.08
+0.16
+0.73
+2.61
+3.43
R96DP
9600 bps Data Pump Modem
Table 8.
Mnemonic
Name
R96DP Interface Memory Definitions (Continued)
Memory
Location
Description
LCEN
Loop Clock Enable
0:4:0
When control bit LCEN is a one, the transmitter clock tracks the receiver clock.
LDEN
Lmk Delay
Equalizer Enable
0:5:2
The link delay equalizer enable and select bits control a delay compromise equalizer in
the receive path according to the following table:
LDEN
D3L
Curve Matched
o
X
1
1
1
No Equalizer
U.S. Survey Long
Japanese 3·Link
o
The link delay equalizer responses are given m the following table.
Link Delay Equalizer
Delay Relative to
1700 Hz (Microseconds)
Frequency
(Hz)
U.S. Survey Long
Japanese 3-Link
800
1200
1600
1700
2000
2400
2800
-498.1
-188.3
-15.1
+0.0
-39.8
-423.1
-672.4
-653.1
-398.5
-30.0
+0.0
+ 11.7
-117.1
-546.3
L2ACT
Remote Digital
Loopback Activate
0:4:1
When control bit L2ACT is a one, the receiver digital output is connected to the
transmitter digital input in accordance with CCITT recommendation V.54 loop 2.
L3ACT
Local Analog
Loopback Activate
0:4'7
When control bit L3ACT is a one, the transmitter analog output is coupled to the
receiver analog mput through an attenuator In accordance with CCITT recommendation
V.54 loop 3.
L4ACT
Remote Analog
Loopback Activate
0.4:6
When control bit L4ACT IS a one, the receiver analog Input i& connected to the transmitter
analog output through a variable gain amplifier In a manner similar to recommendation
V.54 loop 4.
L4HG
Loop 4 High Gain
0:4:5
When control bit L4HG is a one, the loop 4 variable gain amplifier is set for + 16 dB,
and when at zero the gain IS zero dB.
MHLD
Mark Hold
0:7:4
When control bit MHLD is a one, the transmitter input data stream is forced to all marks
(ones).
PNDET
Period N Detector
1 :B:6
When status bit PNDET IS a zero, it indicates a PN sequence has been detected. This
bit sets to a one at the end of the PN sequence.
P2DET
Period Two
Detector
1 :8:2
When status bit P2DET is a zero, It indicates that a P2 sequence has been detected.
ThiS bit sets to a one at the start of the PN sequence.
(None)
RAM Access T
0:F:0-7
Contains the RAM access code used m readmg or writing chip 0 RAM locations via
word Y (0: 1 and 0:0).
(None)
RAM Access XB
2:5:0-7
Contains the RAM access code used in reading or writing chip 2 RAM locations via
word X (2:3 and 2:2).
(None)
RAM Access XS
1 :5:0-7
Contains the RAM access code used in reading or Writing chip 1 RAM locations via
word1< (1 : 3 and 1 : 2).
(None)
RAM Access YB
2:4:0-7
Contains the RAM access code used in reading or writing chip 2 RAM locations via
word Y (2: 1 and 2:0).
2-37
i
I,
.I
R96DP
9600 bps Data Pump Modem
Table 8. R96DP Interface Memory Definitions (Continued)
Mnemonic
Name
Memory
Location
Deacrlptlon
(None)
RAM Access YS
' 1:4:0-7
(None)
RAM DataXBl
2:2:0-7
least significant byte of HI·blt word X used in reading or writing RAM locations in
chip 2.
(None)
RAM DataXBM
2:3:0-7
Most significant byte of 16-bit word X used in reading or writing RAM locations in
chip 2.
(None)
RAM DataXSl
1 :2:0-7
least significant byte of 16-bit word X used in reading or writing RAM locetions in
chip 1.
(None)
RAM DataXSM
1 :3:0-7
Most significant byte of 16-bit word X used in reading or writing RAM locations in
chip 1.
(None)
RAM Data YBl
2:0:0-7
least significant byte of 16·blt word Y used in reading or writing RAM locations in
chip 2.
(None)
RAM Data YBM
2:1 :0-7
Most significant byte of 16-bit word Y used in reading or writing RAM locations In
chip 2.
(None)
RAM Data YSl
1 :0:0-7
least significant byte of 16-blt word Y used in reading or writing RAM locations in
chip 1. Shared by parallel data mode for presenting channel data to the host
microprocessor bus. See 'Receiver Data.'
(None)
RAM Data YSM
1:1:0-7
Most significant byte of 16-blt word Y used In reading or writing RAM locations in
chip 1.
(None)
RAM Data YTl
0:0:0-7
least significant byte of 16-blt word Y used in reading or writing RAM locations in
chip O. It is shared by parallel data mode and DTMF dialing (see Transmitter Data).
(None)
RAM Data YTM
0:1:0-7
Most significant byte of 16-byte word Y used in reading or writing locations in chip O.
RBDA
Receiver Baud
Data Available
2:E:0
Status bit RBDA goes to a one when the receiver wri1es data into register 2: O. The bit
goes to a zero when the host proceasor reads data from register 2: O.
RBIA
Receiver Baud
Interrupt AC1ive
2:E:7
This status bit is a one whenever the receiver baud rate device Is driving IRQ low. In
idle mode the interrupts from chip 2 occur at half the baud rate. During diagnostic
access in data mode, the interrupts occur at the baud rate.
RBIE
Receiver Baud
Interrupt Enable
2:E:2
When the host processor writes a one In the RBIE control bit, the IRQ line of the
hardware interface is driven to zero when status bit RBDA Is a one.
(None)
Receiver
Configuration
1:6:0-5
The host processor configures the receiver by writing a control code Into the receiver
configuration field in the interface memory space (see RSB).
Contains the RAM access code used in reading or writing chip 1 FlAM locations via
word Y (1: 1 and 1 :0).
Receiver Configuration Control Codes
Control codes for the modem receiver configuration are:
Configuration Code (Hex)
14
12
11
22
21
02
01
2-38
Receiver Configuration
V.29 9600
V.29 7200
V.29 4600
V.27 4800
V.27 2400
V.27 4800
V.2724OO
Long
Long
Short
Short
II
1
R96DP
9600 bps Data Pump Modem
TableS.
Mnemonic
Name
,1
R96DP Interface Memory Definitions (Continued)
Memory
Location
Description
(None)
Receiver Data
1 :0:0-7
The host processor obtains channel data from the receiver in the parallel data mode
by reading a data byte from the receiver data register. The data is divided on baud
boundaries as IS the transmitter data. When using receiver parallel data mode, the
registers 1: 3 through 1 ·0 can not be used for reading the chip 1 RAM.
RPDM
Receiver Parallel
Data Mode
1 :7:4
When control bit RPDM is a one, the receiver supplies channel data to the receiver data
register (1 : 0) as well as to the hardware serial data output. (See Receiver Data)
RSB
Receiver Setup Bit
1 :E:3
When the host processor changes the receiver configuration or the RTH field, the host
processor must write a one in the RSB control bit. RSB goes to zero when the changes
become effective. Worst case setup time is 2 baud times.
RSDA
Receiver Sample
Data Available
1 :E:O
Status bit RSDA goes to a one when the receiver writes data to register 1 : o. RSDA
goes to a zero when the host processor reads data from register 1 : O.
RSIA
Receiver Sample
Interrupt Active
1 :E:7
This status bit is a one whenever the receiver sample rate device is driving IRQ to zero.
RSIE
Receiver Sample
Interrupt Enable
1 :E:2
When the host processor writes a one in the RSIE control bit, the IRQ line of the
hardware interface is driven to zero when status bit RSDA is a one.
RTDIS
Receiver Training
Disable
1 :7:0
When control bit RTDIS is a one, the receiver is prevented from recognizing a training
sequence and entering the training state.
RTH
Receiver Threshold
Field
1 :7:6,7
The receiver energy detector threshold is set by the RTH field according to the following
codes (see RSB):
RTH
RLSD On
> -43
> -33
> -26
> -16
0
1
2
3
RLSD Off
< -48
<-38
< -31
< -21
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
RTS
Request·to·Send
0:7:7
When control bit RTS goes to a one, the modem begins a transmit sequence. It
continues to transmit until RTS is reset to zero, and the turn-off sequence has been
completed. This input bit parallels the operation of the hardware RTS control input.
These inputs are ORed by the modem.
SOlS
Scrambler Disable
0:7:5
When control bit SOlS
data path.
SEPT
Short Echo
Protector Tone
0:7:0
When control bit SEPT is a one, the echo protector tone is 30 ms long rather than
185 ms.
SWRT
Sample Write
1 :7:3
When control bit SWRT is a one, the RAM write operation is enabled for chip 1.
TBA
Transmitter Buffer
Available
O:E:O
This status bit resets to zero when the host processor writes data to transmitter data
register 0:0. When the transmitter empties register 0:0, this bit sets to a one. During a
RAM access in chip 0, when TBA is a one the host can perform either a RAM read or
write depending on the state of bit 0: 6: 3 (see Transmitter Configuration).
TIA
Transmitter
Interrupt Active
0:E:7
This status bit is a one whenever the transmitter
TIE
Transmitter
Interrupt Enable
0:E:2
When the host processor writes a one in control bit TIE, the IRQ line of the hardware
interface is driven to zero when status bit TBA is at a one.
2-39
IS
a one, the transmitter scrambler circuit is removed from the
IS
driving IRQ to a zero.
•
R96DP
9600 bps Data Pump Modem
Table 8.
Mnemonic
TLVL
Name
Transmitter Level
Field
R96DP Interface Memory Definitions (Continued)
Memory
Location
0:4:2-4
Description
The transmitter analog output level is determined by eight TLVL codes, as follows:
TLVL
Transmitter Analog Output'
-1
-3
-5
-7
-9
-11
-13
-15
0
1
2
3
4
5
6
7
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
± 1 dB
±I dB
±I dB
±1 dB
±I dB
± 1 dB
± 1 dB
± 1 dB
• Each step above is a 2 dB change ± 0.2 dB.
TOO
Train-on·Data
1 :6:6
When control bit TOO is a one, it enables the train·on·data algorithm to converge the
equalizer if the signal quality degrades sufficiently. When TOO is a one, the modem still
recognizes a training sequence and enters the force train state. A BER of approximately
10- 3 for 0.5 seconds initiates train·on·date.
TPDM
Transmitter Parallel
Data Mode
0:7:2
When control bit TPDM is a one, the transmitter accepts data for transmission from the
transmitter data register (0: 0). When TPDM is a zero channel data from the serial hardware
input TXD is accepted and the chip 0 RAM access is enabled.
(None)
Transmitter
Configuration'
0:6:0-7
The host processor configures the transmitter by writing a control byte into the transmitter
configuration register in its interface memory space. (See TSB.)
Transmitter Configuration Control Codes
Control codes for the modem transmitter configurations are:
Configuration Code (Hex)'
Transmitter Configuration
14
12
11
22
21
02
01
80
40
V.2996OO
V.297200
V.294800
V.27 4800 Long
V.27 2400 Long
V.27 4800 Short
V.27 2400 Short
Tone Transmit
DTMF Tone Transmit
• Note:
Beginning with the R5304·22 device, bit 3 of the transmitter configuration register is
used in the RAM access operation for chip O. When 0:6:3 is a one, a RAM write
operation will occur when TPDM is a zero, and when 0: 6: 3 is a zero, a RAM read
operation will occur when TPDM IS a zero
Configuration Definitions
Definitions of the eight Transmitter Configurations are:
I. V.29. When a V.29 configuration has been selected, the modem operates as
specified in the CCITT Recommendation V.29.
2. V.27. When a V.27 configuration has been selected, the modem operates as
specified in CCITT Recommendation V.27 ter.
3. Tone Transmit. In this configuration, activating signal RTS causes the modem to
transmit a tone at a single frequency specified by two registers in the host interface
memory space containing the frequency code. The most significant bits are specified
in the FREOM register (0: 3). The least significant bits are specified in the FREOL
register (0:2). The least significant bit represents 0.146486 Hz ±0.01%. The frequency
generated is: f = 0.146486 (256 FREOM + FREOL) Hz ± 0.01 %.
4. DTMF Tone Transmit. In this configuration when the hex value of a DTMF digit is
stored in register 0:0, a DTMF tone will be transmitted if RTS is enabled.
2·40
R96DP
9600 bps Data Pump Modem
Table 8. ReIDP Interface Memory Definitions (Continued)
Mnemonic
(None)
Name
Transmitter; DDR;
RAM Data YTL
Memory
location
0:0:0-7
Description
1. The host processor transmits data in the parallel mode by writing a data byte to the
transmitter data register. The data is divided on baud boundaries, as follows'
NOTE
Data is transmitted bit zero first.
Bits
Configuration
7
I
6
V.29 9600 bps
5
I
4
Baud 1
V.29 7200 bps
Not Used
V.29 4800 bps
Baud 3
V.274800 bps
Not Used
V.27 2400 bps
Baud 3
I
I
Baud 1
Baud 2
I
3
I
2
I
Baud I
Baud 1
Baud 2
I
1
I
0
Baud 0
Baud 0
I
Baud 0
Baud 0
I
Baud 1
I
Baud 0
2. Register 0: 0 Is used to transmit DTMF digits when the transmitter is configured in
the DTMF tone transmit mode.
3. Register 0: 0 is a RAM data register used for reading or writing the least significant
byte of the IS-bit Y word in Chip 0 when TPDM is a zero and no tone or DTMF tone
transmission is occurring.
TSB
Transmitter Setup
Bit
O:E:3
When the host processor changes the transmitter configuration, the host must wrtte a
one In this control bit. TSB goes to a zero when the change becomes effective Worst
case setup time Is 2 baud + turnoff sequence + training (if applicable).
TTDIS
Transmitter Train
Disable
0:7:6
When control bit TTDIS is a one, the transmitter does not generate a training sequence
at the start of transmission. With traintng disabled, RTSICTS delay is less than two
baud times.
T2
TI2 Equalizer
Select
1:7:1
When control bit T2 is a one, an adaptive equalizer with two taps per baud is used.
When T2 is a zero, the equalizer has one tap per baud. The total number of taps
remains the same for both cases.
XCEN
External Clock
Enable
0:7:1
When control bit XCEN is a one, the transmitter timing is established by the external
clock supplied at the hardware input XTCLK. The clock appearing at the XTCLK input
will appear at the TDCLK output.
2-41
-~~--
-
--
-
-----
R96DP
9600 bps Data Pump Modem
SIGNAL PROCESSOR RAM ACCESS
When reading from RAM, or writing into RAM, the bits in registers O:E, 1:E, 2:E can be used for handshaking or interrupt functions as in parallel data mode. When not in parallel data mode,
the bits in register 1:E perform the handshake and interrupt functions for RAM access. In both serial and parallel data modes, the
bits in register 2: E perfonn handshake and interrupt functions for
RAM access. When set to one, bit RBIE (2:E:2) enables RBDA to
drive the IRQ connector signal to zero volts when RBDA is a one.
Bit RBIA (2:E:7) identifies chip 2, the baud rate device, as a
source of IRQ interrupt. Bit RBIA is a one when both RBIE and
RBDA are set to one. In the event that other system elements may
cause IRQ to be driven low, the host must determine if modem
chip 2 is causing an interrupt by reading RBIA.
RAM and Data Organization
Each signal processor contains 128 words of random access
memory (RAM). Each word is 32 bits wide. Because the signal
processor is optimized for performing complex arithmetic, the
RAM words are frequently used for storing complex numbers.
Therefore, each word is organized into a real part (18 bits) and an
imaginary part (18 bits) that can be accessed independently.
The portion of the word that normally holds the real value is
referred to asXRAM. The portion that normally holds the imaginary value is referred to as YRAM. In the sample rete and baud
rate devices the entire contents'of XRAM and YRAM may be read
from or written into by the host processor via the microprocessor
interleee. Access to the YRAM is possible only In the trensmitter
device.
Table 9 provides the available RAM access functions, codes, and
registers.
Interface Memory
Auto Dial Sequence
The interface memory acts as an intermediary during these host
to signal processor RAM data exchanges. Information transfer
between RAM and interface memory is accomplished by the signal processor logic unit moving data between the SP main bus
and the SP 1/0 bus. The SP logic unit determines the RAM
address to read from or write into by the code stored in the RAM
ACCESS bits of interface memory registers. The SP logic unit
normally transfers a word from RAM to interface memory once
each cycle of the device code. Each RAM word transferred to the
interface memory is 32 bits long (16 bits in the transmitter). These
bits are written by the SP logic unit into interface memory registers 3, 2, 1, and 0 in that order. Registers 3 and 2 contain the
most and least significant bytes of XRAM data, respectively,
while registers 1 and 0 contain the most and least significant
bytes of YRAM data, respectively. As previously described for
parallel data mode, the data available bits set to a one when
register 0 of the respective signal processor is written into by the
device and resets to a zero when register 0 is read from by the
host. Since the parallel data mode transmitter and receiver data
register shares register 0 with the YRAM data, chip 0 and 1 RAM
access are disabled in parallel data mode. However, chip 2 RAM
access remains active in receiver parallel data mode.
The Figure 6 flowchart defines the auto dial sequence via the '
microprocessor interfece memory. The modem timing for the
auto dialer accounts for DTMF tone duration and interdiglt delay.
The default tone duration is 95 ms and the default interdigit delay
is 71 ms. The default amplitudes for the high and low frequencies
are - 4 dBm and - 6 dBm, respectively. The above four parameters can be changed by performing a RAM write.
Table 9. RAM Acee.. Codes
No.
The transmitter, sample rate device and the baud rate device
allow data to be transferred from interface memory to RAM.
When set to a one, bit SWAT (1 :7:3) signals the chip 1 SP logic
unit to suspend transfer of RAM data to the interleee memory,
and instead, to transfer data from interface memory to RAM. Bit
BWAT (1 :7:2) performs the same function for chip 2 RAM. When
writing into the RAM, 32 bits are transferred. The 16 bits written
into XRAM come from registers 3 and 2, with register 3 being the
more significant byte. The 16 bits written into YRAM come from
registers 1 and 0, with register 1 being the more significant byte.
When only 16 bits of data are to be written, FF (a dummy RAM
location) must be stored in RAM ACCESS XS or RAM ACCESS
YS to prevent writing the inSignificant 16 bits of registers 1:3
through 1:0 into a valid RAM location. When the host processor
writes into register 1:0 the RSDA bit (1 :E:O) is resetto zero. When
the SP logic unit reads data from register 1:0, the RSDA bit
(1 :E:O) is set to a one. In a Similar manner, bit RBDA (2:E:0) resets
to zero when the host processor writes into register 2:0 and sets
to a one when the SP logic unit reads data from register ;1:0.
Function
X Access YAccea
Code
Code
Chip (Hex)
(Hex)
Register
-
88
0,1
08
0,1
89
0,1
0,1
CO
C2
DC
B1
Not Used
42
54
Not Used
Not Used
2,3
0,1,2,3
0,1,2,3
2,3
2,3
2
2
CO
B1-AO
40
01-20
0,1,2,3
0,1,2,3
2
2
E1
A2
61
22
0,1,2,3
0,1,2,3
2
E2
62
0,1,2,3
2
2
2
2
2
E3
Not Used
63
0,1,2,3
0,1
2,3
2,3
0,1,2,3
1 DTMF Low Frequency
Amplttude'
2 DTMF High Frequency
Amplttude'
3 Interdlglt Delay'
4 DTMF Tone Duration'
0
Received Signal Samples
Demodulator Output
Low Pass Fitter Output
Average Energy
9 AGC Gain Word
1
1
1
1
1
10 Equalizer Input
11 Equalizer Tap Coefficients
12 Unrotated Equalizer
Output
13 Rotated Equalizer Output
(Received Points)
14 Decision Points
Ideal Points
15 Error
16 Rotelion Angle
17 Frequency Correction
1B EQM
19 Dual Point
5
6
7
B
0
0
0
D4
AA
A7
AE
Note: 1. Added In transmitter device R5304-22.
2-42
09
00
Not Used
Not Used
2E
R96DP
9600 bps Data Pump Modem
•
Figure 6.
R96DP Auto Dial Sequence
2-43
9600 bps Data Pump Modem
R96DP
PERFORMANCE
TYPICAL PHASE JITTER
At 2400 bps, the modem exhibits a bit error rate of 10.... or less
with a signal-to-noise ratio of 12.5 dB in the presence of 15°
peak-to-peak phase jitter at 150 Hz or with a signal-to-noise ratio
of 15 dB in the presence of 30° peak-to-peak phase jitter at
120 Hz (scrambler inserted).
TYPICAL BIT ERROR RATES
The Bit Error Rate (BER) performance of the modem is specified
for a test configuration conforming to that specified in CCITI
Recommendation V.56, except with regard to the placement of
the filter used to bandlimit the white nOise source. Bit error rates
are measured at a received line signal level of - 20 dBm as
illustrated.
At 4800 bps (V.27 bislter), the modem exhibits a bit error rate of
10.... or less with a signal-to-noise ratio of 19 dB in the presence of
15° peak-to-peak phase jitter at 60 Hz.
Typical BER performance is shown in Figure 7. The BER curves
shown in Figure 7 were prepared from data obtained using a
TAS 1010 system.
to-peak phase jitter at 60 Hz. The modem exhibits a bit error rate
of 1Q-<1 or less with a signal-to-noise ratio of 23 dB in the presence
of 20° peak-to-peak phase jitter at 30 Hz.
4800 BPS
V.29
7200 BPS
V.'},7
~~v~
2400 B P S : X
V.27
10- 3
At 9600 bps, the modem exhibits a bit error rate of 1~ or less
with a signal-to-noise ratio of 23 dB in the presence of 10° peak-
,
9600 BPS
V.29
10- 4
10- 4
i
W
i
fi!II:
II:
II:
Iii
Iii
10- 5
10- 5
~
\
9600 BPS
p9
If
If-
II:
II:
0
w
w
10-1
V.:\
2400 BPS
4800 BPS
V.27
V.27
10- 3
;-
7200 BPS
V.29
4800 BPS
\
0
2
4
6
8
,
10-1
10 12 14 16 18 20 22 24
,
2
4
6
Figure 7.
\
10 12 14 18 18 20 22 24 26
SIGNAL TO NOISE RATIO (dB)
SIGNAL TO NOISE RATIO (dB)
Typical BER Performance
Back-to-Back, - 20 dBm Receive Signal Level
8
Typical BER Performance
3002 Unconditioned Line, - 20 dBm Receive Signal Level
R960P BER versus SNR
2-44
R96DP
9600 bps Data Pump Modem
'j
I
!'
GENERAL SPECIFICATIONS
Table 10.
Modem Power Requirements
Voltage
Tolerance
Current (Typical) @ 25°C
Current (Max) @ DOC
+5 Vdc
+12 Vdc
-12 Vdc
±5%
±5%
±5%
550mA
5 mA
25 mA
<700 mA
< 10 mA
< 50 mA
Note: All voltages must have ripple sO 1 volts peak·to-peak.
I
Table 11.
Modem Environmental Restrictions
Specification
Parameter
Temperature
Operating
Storage
Relative Humidity'
Altitude
O°C to + 60°C (32°F to 140°F)
- 40°C to + 80°C (- 40°F to 176°F) (Stored in heat sealed antistatic bag and shipping container)
Up to 90% noncondenslng, or a wet bulb temperature up to 35°C, whichever is less.
- 200 feet to + 10,000 feet
Table 12. Modem Mechanical Considerations
Parameter
DIN Connector Version
Board Structure:
Mating Connector:
Dimensions:
Width
Length
Connector Height
Component Height
Top (max.)
Bottom (max.)
Weight (max):
Lead Extrusion (max.):
DIP Connector Version
Board Structure:
Dimensions:
Width
Length
Component Height
Top (max)
Bottom (max.)
Weight (max.):
Pin Length (max.)
SpecifIcation
Single PC board with a 3-row 64-PIn right angle male DIN connector with rows A and C populated.
The modem can also be ordered with the follOWing DIN connector' 64-pin DIN right angle female,
64-pin DIN vertical male or 64-pin DIN vertical female.
Female 3-row 64-pln DIN receptacle With rows A and C populated. Typical receptacle:
Winchester 96S-6043-0531-1, Burndy R196B32ROOAOOZ1, or equivalent.
3.937 In (100 mm)
4.725 in. (120 mm)
0437 in (11.1 mm)
0.200 in. (5.1 mm)
o 130 In. (3.3 mm)
36 oz. (100 g)
o 100 In. (2.54 mm)
Single PC board with a row of 30 pinS and a row of 31 PinS in a dual in-hne pin configuration.
3228 in. (82 mm)
3937 in. (100 mm)
0.200 in. (5 1 mm)
0.130 In. (33 mm)
3.6 oz. (100 g)
0.53 in (13.5 mm)
2-45
~
9600 bps Data Pump Modem'
R96DP
JL
!
1
0.156 :t 0.003 DIA (6 PL)
(3.96)
MALE 64-PIN
DIN CONNECTOR
-
~r'
T
3.937
)
IIi-
-~
.700
(94)
,
0.119
1
-
~
1-(
(3)1
.,~-~~
__ o. 483
(1 2.3)
4.100 (83)
4.725 (104)
•
120
~:~r"'-------------------'
~
mn nmn
rO.~~~~~~-
nnnnn~;.!~ MAX ]
COMPONENT AREA
(1.6)
DIN CONNECTOR VERSION
-.J
I
0.250
-1
....,
00 0000 0
"
I
3.228
i~
0.098 DIA (3 PL)
(2.5)
l
L
~~~~~~OO~O~~~~~
0.100~.100 (TYP.)
(2.54)
0.100
(2.54)
(2.54)
3_
725_ _
_.
3.937 (94.6)
(100) - - - - - - + I
0.53 MAX
0.025
sa. PIN
0.200 MAX
rlT":::::~~::; fC't
0.082
(1.6)
0.130
(3.3)
COMPONENT AREA
DIP CONNECTOR VERSION (PRELIMINARY)
Figure 9.
R96DP Modem Dimensions and Pin Locations
2-46
UNITS: INCHES
mm
R96FT
Integral Modems
'1'
Rockwell
R96FT
9600 bps Fast Train Modem
INTRODUCTION
FEATURES
The Rockwell R96FT is a synchronous serial 9600 bps modem
designed for multipoint and networking applications. The R96FT
allows full-duplex operation over 4-wire dedicated unconditioned
lines, or half-duplex operation over the public switched telephone
network (PSTN).
•
•
•
•
•
•
•
•
•
•
•
Proprietary fast train configurations provide training times of
23 ms for V.29FT/9600/7200/4800, 22 ms for V.27FT/4800, and
30 ms for V.27FT/2400. A 2400/4800 bps Gearshift configuration provides a training time of 10 ms. For applications requiring
operation with international standards, fallback configurations
compatible with CCITI recommendations V.29 and V.27 bis/ter
are provided. A 300 bps FSK configuration. compatible with
CCITI V.21 Channel 2, is also provided.
•
The small size and low power consumption of the R96FT offer
the user flexibility in formulating a 9600 bps modem design customized for specific packaging and functional requirements.
•
•
•
•
•
R96FT DIN Connector Version
Document No. 29200N09
Proprietary Fast Train
2400/4800 bps Gearshift
CCITI V.29, V.27 bis/ter and V.21 Channel 2 Compatible
Train on Data
2-Wire Half Duplex, 4-Wire Full Duplex
Programmable Tone Generation
DTMF Tone Dialer
Call Progress Tone Detection
Dynamic Range - 43 dBm to - 5 dBm
Diagnostic Capability
Equalization:
- Automatic Adaptive
- Compromise Cable and Link (Selectable)
DTE Interface:
- Microprocessor Bus
- CCITI V.24 (RS-232-C Compatible)
Loopbacks
- Local Analog
- Remote Analog and Digital
Small Size
- DIN Connector Version:
120 mm x 100 mm (4.73 in. x 3.94 in.)
- DIP Connector Version:
82 mm x 100 mm (3.23 in. x 3.94)
Low Power Consumption: 3W (typical)
Programmable Transmit Output Level
TIL and CMOS Compatible
R96FT DIP Connector Version
Data Sheet
2-47
Order No. MD09
Rev. 6 January 1989
2
R96FT
9600 bps Fast Train Modem
TECHNICAL SPECIFICATIONS
Cable Equalizers - Selectable compromise cable equalizers in
the receiver and transmitter are provided to optimize performance
over different lengths of non-loaded cable of 0.4 mm diameter.
TRANSMITTER CARRIER FREQUENCIES
Function
V.27 bis/ter Carrier
V.27FT Carrier
2400/4800 bps Gearshift
V.29 Carner
V.29FT Carner
V.21 Channel 2:
Mark
Space
Frequency
(Hz to.01%)
Link Equalizers - Selectable compromise link equalizers in the
receiver optimize performance over channels exhibiting sever!)
amplitude and delay distortion. Two standards are provided: U.S.
survey long and Japanese 3-link.
1800
1800
1800
1700
Automatic Adaptive Equalizer - An automatic adaptive T
equalizer is provided in the receiver circuit.
1700/1800'
1650
1850
TRANSMITTED DATA SPECTRUM
If the cable equalizer is not enabled, the transmitter spectrum
'Selectable carrier frequency
is
1.
2.
3.
TONE GENERATION
Under control of the host processor, the R96FT can generate
voice band tones up to 4800 Hz with a resolution of 0.15 Hz and
an accuracy of 0.01 %. Tones over 3000 Hz are attenuated.
The out-of-band transmitter power limitations meet those
specified by Part 68 of the FCC's rules, and typically exceed
the requirements of foreign telephone regulatory bodies.
SIGNALING AND DATA RATES
Parameter
Specification
Signaling Rate:
Data Rate:
2400
9600
7200
4800
Signaling Rate:
Data Rate:
1600 baud
4800 bps
Signaling Rate:
Data Rate:
Gearshift Data Rate:
Signaling Rate:
Data Rate:
shaped by the following raised COSine filter functions:
1200 Baud. Square root of 90 percent.
1600 Baud. Square root of 50 percent.
2400 Baud. Square root of 20 percent.
baud
bps
bps
bps
SCRAMBLER/DESCRAMBLER
The R96FT incorporates a self-synchronizing scramblerl
descrambler. This facility is in accordance with either V.27 bis/ter
or V.29 depending on the selected configuration.
The scrambler/descrambler facilities for Gearshift can be
selected to be in accordance with either V.27 bis/ter or V.29.
The scrambler/descrambler selection is made by writing the
appropriate configuration codes into the transmitter and receiver.
1200 baud
2400 bps
2400/4800 bps
300 baud
300 bps
RECEIVED SIGNAL FREQUENCY TOLERANCE
The receiver circuit of the R96FT can adapt to received
frequency error of up to ± 10Hz with less than 0.2 dB degradation in BER performance.
DATA ENCODING
At 2400 baud, the data stream is encoded per CCITT V.29. At
9600 bps, the data stream is divided in groups of four-bits (quadbits) forming a 16-point structure. At 7200 bps, the data stream
is divided into three bits (tribits) forming an 8-point structure.
At 4800 bps, the data stream is divided into two bits (dibits)
forming a 4-point structure.
During fast train polling, frequency offset must be less than
± 2 Hz for successful training.
RECEIVE LEVEL
At 1600 baud, the 4800 bps data stream is encoded into tribits
per CCITT V.27 bis/ter.
The receiver circuit of the modem satisfies all specified performance requirements for received line signal levels from -5 dBm
to -43 dBm. The received line signal level is measured at the
receiver analog inpl,lt (RXA).
At 1200 baud, the 2400 bps data stream is encoded Into dlbits
per CCITT V.27 bis/ter.
For the Gearshift configuration, the signaling rate is 1200 baud.
The 2400 bps data stream is encoded into dibits forming a 4-point
structure, and the 4800 bps data stream is encoded into quadbits forming a 16-point structure. The first 32 bauds of data are
transmitted at 2400 bps and the remaining message is transmitted at 4800 bps.
RECEIVE TIMING
At 300 baud, the 300 bps data stream is encoded per CCITT V.21
Channel 2 into a mark frequency of 1650 Hz and a space frequency of 1850 Hz.
The R96FT provides a data derived Receive Data Clock (RDCLK)
output in the form of a squarewave. The low-to-high transitions
of this output coincide with the centers of received data bits.
For the Gearshift configuration, the first 32 bauds of data are
at 2400 bps followed by 4800 bps data for the remaining
message. The timing recovery circuit is capable of tracking a
± 0.01 % frequency error in the associated transmit timing
source. RDCLK duty cycle is 50% ± 1%.
EQUALIZERS
TRANSMIT LEVEL
The R96FT provides equalization functions that improve performance when operating over low quality lines.
The transmitter output level is accurate to ± 1.0 dB and is programmable from - 1.0 dBm to - 15.0 dBm in 2 dB steps.
2-48
R96FT
9600 bps Fast Train Modem
TRANSMIT TIMING
20 ms period of no transmitted energy (V .27 bis/ter only). For
V.29 and V.29FT, the turn-off sequence consists of approximately 8 ms of remaining data and scrambled ones.
The R96FT provides a Transmit Data Clock (TDCLK) output with
the following characteristics:
1. Frequency. Selected data rate of 9600, 7200, 4800, 2400 or
300 Hz (±0.01%). For the Gearshift Configuration, TDCLK
is a 2400 Hz clock for the first 32 bauds of data, and a
4800 Hz clock for the remaining message.
2. Duty Cycle. 50% ± 1%
CLAMPING
Received Data (RXD) is clamped to a constant mark (one) when
the Received Line Signal Detector (RLSD) is off.
RESPONSE TIMES OF CLEAR TO SEND (CTS)
Input data presented on TXD is sampled by the R96FT at the
low-ta-high transition of TDCLK. Data on TXD must be stable
for at least one microsecond prior to the rising edge of TDCLK
and remain stable for at least one microsecond after the rising
edge of TDCLK.
The time between the off-to-on transition of Request To Send
(RTS) and the off-to-on transition of Clear to Send (CTS) is
dictated by the length of the training sequence and the echo
protector tone, if used. These times are given in the Turn-On
Sequences table. If training is not enabled, RTS/CTS delay
is less than 2 baud times.
EXTERNAL TRANSMIT CLOCK
The transmitter data clock (TDCLK) can be phase locked to a
signal on input XTCLK. This input signal must equal the desired
data rate ± 0.01 % with a duty cycle of 50% ± 20%.
The time between the on-to-off transition of RTS and the on-taoff transition of CTS in the data state is a maximum of 2 baud
times for all configurations.
TRAIN ON DATA
RECEIVE LINE SIGNAL DETECTOR (RLSD)
When train on data is enabled (by setting a bit in the interface
memory), the modem monitors the EOM signal. If EOM indicates
a loss of equalization (i.e., BER approximately 10- 3 for
0.5 seconds) the modem attempts to retrain on the data stream.
The time for retrain is typically 3 to 15 seconds.
Response
For Fast Train and Gearshift configurations, the receiver enters
the training state upon detecting a significant increase in the
received signal power. If the received line signal power is greater
than the selected threshold level at the end of the training state,
the receiver enters the data state and RLSD is activated. If the
received line signal power is less than the selected threshold
level at the end of the training state, the receiver returns to the
idle state and RLSD is not activated.
TURN-ON SEQUENCE
A total of 20 selectable turn-on sequences can be generated
as defined in the following table:
No.
V.29
(bps)
1 FT/9600
2 FT17200
3 FT/4800
4
5
6
7
8
9
10
11
12
13
9600
7200
4800
14
15
16
17
18
19
9600
7200
4800
20
V.27
bis/ter
(bps)
RTS-CTS
Gearshift Response Time
(milliseconds)
Comments
(bps)
FT/4800
FT/2400
23
24
23
22
30
4800
2400
4800
2400
Also, in Fast Train and Gearshift configurations, the receiver
initiates the turn-off delay upon detecting a significant decrease
in the received signal power. If the received signal power is less
than the selected threshold at the end of the turn-off delay, the
receiver enters the idle state and RLSD is deactivated. If the
received signal power is greater than the selected threshold at
the end of the turn-off delay, the receiver returns to the data state
and RLSD is left active.
Proprietary
Fast Train
253
253
253
708
943
long
long
short
short
For CCITT configurations, the receiver enters the traming
detection state when the received line signal power crosses the
selected threshold level. RLSD is activated at the end of the
training sequence. For V.21 Channel 2, a separate received line
signal detector (FRLSD) is provided. FRLSD is activated when
energy above - 43 dBm is present at the receiver'S audio input
(RXA). The FRLSD off-to-on response time is 15 ±5 ms and
the on-ta-off response time is 25 ± 5 ms.
50
2400/4800
4800 long
2400 long
4800 short
2400 short
67
10
438
438
438
913
1148
255
272
Preceded'
by Echo
Protactor
Tone for
lines using
echo
suppressors.
The RLSD on-to-off response times are:
1. For short echo protector tone, subtract 155 ms from values of
RTS-CTS response time.
2. V.21 (300 bps FSK) RTS-CTS response time IS <35 ms
TURN-OFF SEQUENCE
For V.27 bislter, V.27FT and 2400/4800 bps Gearshift
configurations, the turn-off sequence consists of approximately
10 ms of remaining data and scrambled ones followed by a
Configuration
RLSD On-To-Off
Response Time (ms)
V.29 Fast Train
'V.27 Fast Train
Gearshift
V.29
V.27 bis/ter
6.5 ± 1
8 ±1
6 ±1
30 ±9
10 ±5
RLSD response times are measured with a signal at least 3 dB
above the 'actual RLSD on threshold or at least 5 dB below the
actual RLSD off threshold.
2-49
I
I
.-
9600 bps Fast Train Modem
R96FT
-,
r
I
I
I
I
I
I
RTS
r
A...
USRT
(OPTIONAL)
I
I
I
HOST
PROCESSOR
(DTE)
":
A
r
,
L __ -
0SCOPE
CTS
TXD
TDCLK
XTCLK
RLSD
RXD
RDCLK
TBCLK
i
EYEY
EYECLK
MODEM
+12V
+5V
POWER
SUPPLY
GND
-12V
READ
WRITE
DATA BUS (8)
ADDRESS BUS (4[
IDECODER
CS (3)
iv
EYE
PATTERN
GENERATOR
EYSYNC
RBCLK
.J
xj
EYEX
TXA
Di
RXA
RSi
LINE
.... }
INTERFACE __
TELEPHONE
LINE
,
AUXIN
CSi
POR
iRa
+5~
R96FT Functional Interconnect Diagram
Threshold Options
MODE SELECTION
Four threshold options are provided:
For the transmitter, a control bit determines whether the source
of transmitted data is the V.24 interface (serial mode) or the
parallel transmitter data register (parallel mode). The transmitter
automatically defaults to the serial moae at power-on.
1. Greater than - 43 dBm (RLSO on)
Less than - 48 dBm (RLSO off)
2. Greater than - 33 dBm (RLSO on)
Less than - 38 dBm (RLSO off)
The receiver simultaneously outputs received data via the V.24
interface and the parallel receiver data register.
3. Greater than - 26 dBm (RLSO on)
Less than - 31 dBm (RLSO off)
In either parallel or serial mode, the R96FT is configured by the
host processor via the microprocessor bus.
4. Greater than - 16 dBm (RLSO on)
Less than - 21 dBm (RLSO off)
NOTE
Performance may be at a reduced level when the received
signal is less than - 43 dBm.
INTERFACE CRITERIA
The modem interface comprises both hardware and software
circuits. Hardware circuits are assigned to specific pins in a
64-pin DIN connector. Software circuits are assigned to specific
bits in a 48-byte interface memory.
For CCITT configurations, a minimum hysteresis action of 2 dB
exists between the actual off-to-on and on-to-off transition levels.
The threshold levels and hysteresis action are measured with
unmodulated 2100 Hz tone applied to the receiver's audio input
(RXA).
HARDWARE CIRCUITS
Signal names and descriptions of the hardware circuits, including
the microprocessor interface, are listed in the R96FT Hardware
Circuits table. In the table, the column titled 'Type' refers to
designations found in the Hardware Circuit Characteristics. The
microprocessor interface is designed to be directly compatible
with an 8080 microprocessor. With the addition of a few external
logic gates, it can be made compatible with 6500, 6800, or
68000 microprocessors.
MODES OF OPERATION
The R96FT is capable of being operated in either a serial or a
parallel mode of operation.
SERIAL MODE
The serial mode uses standard V.24 (RS-232-C compatible) signals to transfer channel data. An optional USRT device (shown
in the Functional Interconnect Diagram) illustrates this capability.
Eye Pattern Generation
The four hardware diagnostic circuits, identified in the following table, allow the user to generate and display an eye pattern.
Circuits EYEX and EYEY serially present eye pattern data for
the horizontal and vertical display inputs respectively. The 8-bit
data words are shifted out most significant bit first, clocked by the
PARALLEL MODE
The R96FT has the capability of transferring channel data (up
to eight bits at a time) via the microprocessor bus. .
2-50
R96FT
9600 bps Fast Train Modem
Microprocessor Timing
rising edge of the EYECLK output. The EYE SYNC output is provided for word synchronization. The falling edge of EYESYNC
may be used to transfer the 8-bit word from the shift register
to a holding register. Digital to analog conversion can then be
performed for driving the X and Y inputs of an oscilloscope.
READ
CSI
(i
R96FT Hardware Circuits
Name
Type
DIN
Pin No.
DIP
Pin No.
WRITE
= 0-2)
Description
RSi
A. OVERHEAD:
Ground (A) AGND
31C,32C
30,31
Ground (D) DGND 3C,8C,5A,10A 29,37,53
19C,23C,
+5 volts
PWR
1,45,61
26C,30C
15A
+ 12 volts PWR
32
-12 volts PWR
12A
36
POR
IIOB
13C
2
(i
Analog Ground Return
Digital Ground Return
+ 5 Vdc Supply
= 0-3)
+ 12 Vdc Supply
- 12 Vdc Supply
Power-on-reset
TWR
B. MICROPROCESSOR INTERFACE:
RS3
RS2
RSl
RSO
I/OA
I/OA
I/OA
I/OA
I/OA
I/OA
I/OA
I/OA
IA
IA
IA
IA
6C
6A
7C
7A
17
18
19
CSO
IA
10C
20
CSl
IA
9C
21
CS2
IA
9A
13
IA
IA
DB
12C
llA
llC
14
12
11
D7
D6
D5
D4
D3
D2
Dl
DO
READ
WRITE
IRQ
lC
lA
2C
2A
3A
4C
4A
5C
READ
,I}
1~
Data Bus (8 Bits)
Di
(i = 0-7) --~"
Register Select (4 Bits)
Microprocessor Interface Timing Diagram
Chip SelectTransmitter Device
Chip Select-Receiver
Sample Rate Device
Chip Select-Receiver
Baud Rate Device
Read Enable
Write Enable
Interrupt Request
Critical Timing Requirements
C. V.24 INTERFACE:
RDCLK
TDCLK
XTCLK
RTS
CTS
TXD
RXD
RLSD
DC
DC
IB
IB
DC
IB
DC
DC
21A
23A
22A
25A
25C
24C
22C
24A
23
46
51
50
49
48
26
27
Receive Data Clock
Transmit Data Clock
External Transmit Clock
Request to Send
Clear to Send
Transmitter Data
Receiver Data
Received Llnp- Signal
Detector
Receiver Baud Clock
Transmitter Baud Clock
FSK Receiver Data
(Inverted data)
FSK Received Line
Signal Detector
OC
DC
OD
26A
27C
16A
22
47
59
FRLSD
OD
17C
52
AA
31A
34
RXA
AUXIN
AB
AC
32A
30A
33
15C
14A
14C
13A
56
55
57
58
-
Transmitter Analog
Output
Receiver Analog Input
AUXiliary Analog Input
F. DIAGNOSTIC:
Eye Pattern Data-X AXIs
Eye Pattern Data-Y Axis
Eye Pattern Clock
Eye Pattern
SynchroniZing Signal
NOTES: 1. Pins not used on the DIP version: 15, 24, 25, 28, 35
38-44,54 and 60.
2. Unused inputs tied to + 5V or ground require
individual 10K 11 series resistors.
EYEX
EYEY
EYECLK
EYESYNC
DC
DC
OA
OA
CSI, RSI setup time prior
to Read or Write
TCS
30
-
nsec
Data access time after Read
TDA
-
140
nsec
Data hold time after Read
TDH
10
50
nsec
nsec
nsec
nsec
nsec
2-51
Max
TCH
10
Write data setup time
TWDS
75
Write data hold time
TWDH
10
-
TWR
75
-
Write strobe pulse Width
E. ANALOG SIGNALS:
TXA
Min
CSi, RSi hold time after
Read or Write
D. ANCILLARY CIRCUITS:
RBCLK
TBCLK
FRXD
Symbol
Characteristic
Units
R96FT
9600 bps Fast Train Modem
Digital Interface Characteristics
Digital Interface Characteristics
Input/Output Type
Symbol
V,H
Parameter
IA
IB
IC
V
2.0 Min.
2.0 Min.
2.0 Min.
0.8 Max.
0.8 Max.
0.8 Max.
Units
Input Voltage, High
V,L
Input Voltage, Low
V
VOH
Output Voltage, High
VOL
Output Voltage, Low
V
V
liN
Input Current,
Leakage
OA
0.4 Max. 2
Output Current, High
mA
-0.1 Max.
Output Current, Low
mA
1.6 Max.
IL
Output Current,
Leakage
Ipu
Pull-up Current
(Short Circuit)
pA
CL
Capacitive Load
pF
Co
Capacitive Drive
pF
= -100pA
= 1.S mA
2.2 Min. 6
0.4 Max. 2
0.4 Max 2
1.6 Max.
1.6 Max.
0.6 Max.?
pA ±2.5 Max.
IOH
Notes 1. I Load
2. I Load
00
OC
2.4 Min.'
IOL
Circuit Type
OB
pA
I/O A
I/O B
2.0 Min.
5.25 Max.
2.0 Min.
0.8 Max.
0.8 Max.
2.4 Min.' 2.4 Min.3
0.4 Max. 2 0.4 Max.s
±2.5 Max.4
±10 Max.
-240 Max. -240 Max.
-10 Min. -10 Min.
5
5
-240 Max.
-10 Min.
20
100
TTL
TTL
w/Pull-up
-260 Max.
-100 Min.
TTL
w/Pull-up
3. I Load = -40 pA
4. V'N = 0.4 to 2 4 Vdc, Vcc
TTL
= 5.25 Vdc
Analog Interface Characteristics
Name
Type
AA
The transmitter output impedance is S04 ohms ± 1%.
RXA
AB
The receiver input impedance is SOK ohms
±23%.
AUXIN
AC
The auxiliary analog input allows access to the
transmitter for the purpose of interfacing with
user provided equipment. Because this is a
sampled data input, any signal above 4800 Hz
will cause aliasing errors. The input impedance is
1K ohms, and the gain to transmitter output is
TLVL setting + O.S dB -1.4 dB. If unused, this
input must be grounded near the modem
connector. If used, it must be driven from a low
impedance source.
100
Open-Drain Open-Drain
w/Pull-up
5. I Load
6. I Load
= 0.36 mA
= -400pA
TTL
10
40
100
100
3-State Open-Drain
ransceiver w/Pull-up
7. I Load
= 2.0 mA
Status Control Bits
Analog Interface Characteristics
TXA
100
The operation of the R96FT is affected by a number of software
control inputs. These inputs are written into registers within the
interface memory via the host microprocessor bus. Modem
operation is monitored by various software flags that are read
from interface memory via the host microprocessor bus. All status
and control bits are defined in the Interface Memory table. Bits
designated by a dash (-) are reserved for modem use only and
must not be changed by the host.
Characteristics
RAM Data Access
The R96FT provides the user with access to much of the data
stored in the modem's memories. This data is useful for performing certain diagnostic functions.
Two RAM access registers in chip 2 allow user access to RAM
locations via the X word registers (2:3 and 2:2) and the Y word
register (2: 1 and 2:0). The access code stored in RAM ACCESS
X (2:5) selects the source of data for RAM DATA XM and RAM
DATA XL (2:3 and 2:2). Similarly, the access code stored in RAM
ACCESS Y (2:4) selects the source of data for RAM DATA YM
and RAM DATA YL (2:1 and 2:0).
SOFTWARE CIRCUITS
The R96FT comprises three signal processor chips. Each of
these chips contains 16 registers to which an external (host)
microprocessor has access. Although these registers are within
the modem, they may be addressed as part of the host
processor's memory space. The host may read data out of or
write data into these registers. The registers are referred to as
interface memory. Registers in chip 1 update at half the modem
sample rate (4800 bps). Registers in chip 0 and 2 update at the
selected baud rate.
Reading of diagnostic RAM data is performed by storing the
necessary access codes in 2:5 and 2:4, reading 2:0 to reset the
associated data available bit (2:E:0), then waiting for the data
available bit to return to a one. Data is now valid and may be
read from 2:3 through 2:0.
An additional diagnostic is supplied by the sample rate processor (chip 1). Registers 1:2 and 1:3 supply a 16 bit AGC Gain
Word. These two diagnostic data registers are updated at the
sample rate during the data state and may be read by the host
processor asynchronously.
When information in these registers is being discussed, the
format Y:Z:O is used. The chip is specified by Y(0-2), the register
by Z(O-F), and the bit by 0(0-7, 0 = LSB).
2-52
R96FT
9600 bps Fast Train Modem
RAM Access Codes
Transmitter Interface Memory Chip 0 (CSO)
~
The RAM access codes defined in the following table allow the
host processor to read diagnostic information within the modem.
No.
Function
1
2
3
4
5
Equalizer Input
Equalizer Tap Coefficients
Unrotated Equalizer Output
Rotated Equalizer Output
Decision Points
(Ideal Data Points)
Error Vector
Rotation Angle
Frequency Correction
Eye Quality Monitor (EQM)
6
7
8
9
X Access Y Access Register
40
2
1
0
-
-
TSB
TIE
-
TBA
7
6
5
F
-
-
TIA
0
-
-
-
E
-
-
-
-
-
-
C
-
-
-
-
-
TCF
DDEE
-
-
-
-
-
-
-
4
3
Register
Baud Rate Processor (Chip 2) RAM Access Codes
CO
81-AO
E1
E2
E8
01-20
61
62
68
0,1,2,3
0,1,2,3
0,1,2,3
0,1,2,3
0,1,2,3
E5
A7
AS
AC
65
Not Used
Not Used
Not Used
0,1,2,3
2,3
2,3
2,3
B
A
9
-
-
F'SKT ASCR
-
8
7
-
-
-
-
-
RTS TTDIS SOlS MHLD EPT TPDM XCEN SEPT
TRANSMITTER CONFIGURATION
6
-
5
-
CEQ
LAEN LDEN
L3ACT L4ACT L4HG
4
TLVL
A3L
D3L
L2ACT LCEN
FREQM
3
FREQL
2
-
1
-
-
-
-
-
-
-
DIAL DIGIT REGISTER (DDR)ITRANSMITTER DATA
0
7-
7
5
6
4
3
2
1
0
Bit
NOTE
(-) indicates reserved for modem use only.
Receiver Interface Memory Chip 1 (CS1)
~
7
6
5
4
2
3
1
Receiver Interface Memory Chip 2 (CS2)
I~
0
Register
F
-
-
-
-
E
RIA
0
-
C
A
-
-
-
B
-
-
9
-
FED
8
TONE
-
-
7
RTH
DDIS
TOO
6
7
6
5
4
3
-
-
-
-
-
-
RBIE
-
-
5
-
4
-
-
-
-
RSB
RIE
-
-
-
-
-
CDET
P2DET
-
RCF
-
RDIS
-
F
-
RDA
E
RBIA
-
0
C
8
-
7
6
-
B
-
A
9
-
RECEIVER CONFIGURATION
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
5
RAM ACCESS X
4
RAM ACCESS Y
RAM DATAXM
3
AGC GAIN WORD (MSB)
3
2
AGC GAIN WORD (LSB)
2
RAM DATA XL
1
RAM DATA YM
0
RAM DATA YL
-
1
-
-
-
-
-
-
-
RECEIVER DATA
0
7-
2
1
0
Register
7
6
5
4
3
2
1
7-
0
Bit
7
6
5
4
3
Bit
NOTE
(-) indicates reserved for modem use only.
NOTE
(-) indicates reserved for modem use only.
2-53
-
-
-
-
RBDA
-
-
-
-
-
-
-
2
1
0
I
I
I
•
!
I
9600 bps Fast Train Modem
R96FT
R96FT Interface Memory Definitions
Mnemonic
Name
Memory
Location
Description
ASCR
Append Scrambled
Ones
0:9:6
When control bit ASCR IS a one, one baud of scrambled marks is included in the
V.29FT and V.27FT training sequences The RTS-CTS delay is thus extended by one
baud period when ASCR is a one.
A3l
Amplitude 3-llnk
Select
0:5.1
See lAEN.
CDET
Carrier Detector
1 :9:2
When zero, status bit CDET indicates that passband energy IS being detected, and
that a training sequence is not in process CDET goes to a zero at the start of the
data state, and returns to a one at the end of the received signal. CDET activates up to
1 baud time before RlSD and deactivates within 2 baud times after RlSD.
CEQ
Cable Equalizer
Field
0:5:(4,5)
The CEQ Control field simultaneously controls amplitude compromise equalizers in both
the transmit and receive paths. The following table lists the possible cable equalizer
selection codes:
CEQ
Cable length (0.4 mm diameter)
o
0.0
1.8 km
3.6 km
7.2 km
1
2
3
DDEE
Digital Delay
Equalizer Enable
0:9:2
When control bit DDEE IS a one, a fourth order digital delay equalizer IS inserted in the
transmit path
DDIS
Descramble Disable
1 :7:5
When control bit DDIS is a one, the receiver descrambler circUit is removed from the
data path.
DDR
Dial Digit Register
0:0:0-7
DDR is used to tell the modem which DTMF digit to transmit (see Transmitter Data).
D3l
Delay 3-Link Select
0:5:0
See LDEN
EPT
Echo Protector
Tone
0:7:3
When control bit EPT IS a one, an unmodulated carner IS transmitted for 185 ms
(optIOnally 30 ms) followed by 20 ms of no transmitted energy at the start of
transmission. This option is available In the V.27 and V.29 configurations, although it is
not speCified in the CCITT V.29 Recommendation.
Fast Energy
Detector
1 :9:6
When status bit FED is a zero, It Indicates that energy above the receiver threshold is
present In the passband.
FREQUFREQM
0:2:0-7,
0:3:0-7
The host processor conveys tone generation data to the transmitter by writing a 16-bit
data word to the FREQl and FREQM registers in the interface memory space, as
shown below:
(None)
FREQM Register (0:3)
I
Bit:]
IData W.ord: I
7
I
6
2'5
I
2'4
I
I
2 '3
5
5
I
I
I
4
I
I
2
I
2"
2 '0
[
2
I
3
I
I
o
[
o
I
J
FREQL Register (0: 2)
[
Bit: I
7
[
6
I
[Data Word: I
27
[
26
I
I
4
[
3
[
24
[
23
[
2'
[
The frequency number (N) determines the frequency (F) as follows:
F = (0.146486) (N) Hz ± 0.01 %
Hexadecimal frequency numbers (FREQl, FREQM) for commonly generated tones are
given below:
Frequency (Hz)
462
1100
1650
1850
2100
FSKT
FSK Transmitter
Configuration
0:9:7
FREQM
OC
10
2C
31
38
FREQL
52
55
00
55
00
The V.21 Channel 2 (300 bps synchronous FSK) transmitter configuration is selected by
setllng the FSK control bit to a one (see TSB). While set to a one, this control bit
overrides the configuratIOn selected by the control code in register 0:6. The FSK data
may be transmitted in parallel mode or in senal mode (see TPDM).
2-54
[
R96FT
9600 bps Fast Train Modem
R96FT Interface Memory Definitions (Continued)
Mnemonic
LAEN
Name
Link Amplitude
Eq ualizer Enable
Memory
Location
0:5:3
Deacrlptlon
The link amplitude equalizer enable and select bits control an amplitude compromise
equalizer in the receive path according to the following table:
LAEN
o
1
1
A3L
X
0
1
Curve Matched
No Equalizer
U.S. Survey Long
Japanese 3-Link
LCEN
Loop Clock Enable
0:4:0
When control bit LCEN is a one, the transmitter clock tracks the receiver clock.
LDEN
Link Delay
Equalizer Enable
0:5:2
The link delay equalizer enable and select bits control a delay compromise equalizer in
the receive path according to the following table:
LDEN
o
D3L
X
1
0
Curve Matched
No Equalizer
U.S. Survey Long
Japanese 3-Link
~
!
L2ACT
Remote Digital
Loopback Activate
0:4:1
When control bit L2ACT is a one, the receiver digital output is connected to the
transmitter digital input in accordance with CCITT Recommendation V.54 loop 2.
L3ACT
Local Analog Loopback Activate
0:4:7
When control bit L3ACT is a one, the transmitter analog output is coupled to the
receiver analog input through an attenuator in accordance with CCITT Recommendation
V.54 loop 3.
L4ACT
Remote Analog
Loopback Activate
0:4:6
When control bit L4ACT is a one, the receiver analog input is connected to the transmitter analog output through a variable gain amplifier in a manner similar to CCITT
Recommendation V.54 loop 4.
L4HG
Loop 4 High Gain
0:4:5
When control bit L4HG is a one, the loop 4 variable gain amplifier is set for + 16 dB,
and when at zero the gain is zero dB.
MHLD
Mark Hold
0:7:4
When control bit MHLD is a one, the transmitter input data stream is forced to all
marks (ones).
P2DET
Period 2 Detector
1 :8:3
When status bit P2DET is a zero, it indicates that a period 2 sequence has been
detected. This bit sets to a one at the start of the period N sequence. This bit is only
significant for CCITT V.29 and V.27 bislter configurations.
(None)
RAM Access X
2:5:0-7
Contains the RAM access code used in reading chip 2 RAM locations via word X (2: 3
and 2:2).
(None)
RAM Access Y
2:4:0-7
Contains the RAM access code used in reading chip 2 RAM locations via word Y (2: 1
and 2:0).
(None)
RAM Data XL
2:2:0-7
Least significant byte of 16-bit word X used in reading RAM locations in chip 2.
(None)
RAM Data XM
2:3:0-7
Most significant byte of 16-bit word X used in reading RAM locations in chip 2.
(None)
RAM Data YL
2:0:0-7
Least significant byte of 16-bit word Y used in reading RAM locations in chip 2.
(None)
RAM Data YM
2:1 :0-7
Most significant byte of 16-bit word Y used in reading RAM locations in chip 2.
RBDA
Receiver Baud
Data Available
2:E:0
Status bit RBDA goes to a one when the receiver writes data into register 2: O. The bit
goes to a zero when the host processor reads data from register 2: O.
RBIA
Receiver Baud
Interrupt Active
2:E:7
This status bit is a one whenever the receiver baud rate device is driving IRQ low.
RBIE
Receiver Baud
Interrupt Enable
2:E:2
When the host processor writes a one in the RBIE control bit, the IRQ line of the hardware interface is driven to zero when status bit RBDA is a one.
RCF
Receiver Carrier
Frequency
1 :7:2
Control bit RCF selects the demodulator carrier frequency for V.29FT configurations as
follows:
RCF
Demodulator Carrier Frequency
1700 Hz
1800 Hz
o
1
2-55
R96FT
9600 bps Fast Train Modem
R96FT Interface Memory Definitlonll (Continued)
Mnemonic
(None)
Name
Receiver
Configuration
Memory
,Location
1 :6:0-6
Description
The host processor configures the receiver by writing a control code into the receiver
configuration field in the interface memory space (see RSB).
Note: The receiver must be disabled prior to changing configurations. See RDIS.
Receiver Configuration Control Codes
Control codes for the modem receiver configuration are:
Configuration
V29
V27 blalter
FT/9600
FT17200
FT/4800
FT/4800
FT/2400
9600
7200
4800
4800
2400
4800
2400
long
long
short
short
2400/4800 bps GearshiftN.29 descrambler1
2400/4800 bps GearshiftN.27 bislter descrambler1
V.21 Channel 2
Configuration Code (Hex)
lC
lA
19
OA
09
14
12
11
22
21
02
01
61
41
See Note 2
250-650 Hz Tone Detector3
31
2100 Hz Tone Detector3
33
1. The Receiver Configuration code automatically changes from a hex 61 (or hex 41)
to a hex 64 (or hex 44) when the receiver transitions from the 2400 bps data state
to the 4800 bps data state.
2. The FSK receiver is active at all times. Two ancillary hardware circuits, FRlSD
and FRXD, are supplied for FSK message reception. FRlSD is described under
the Received line Signal Detector section. FRXD provides inverted FSK received
data. Timing extraction must be performed on the FRXD signal externally as no
FSK receiver data clock is provided by the R96FT.
3. Added in B5413-11.
(None)
Receiver Data
1 :0:0-7
RDA
Receiver Data
Available
1 :E:O
RDIS
Receiver Disable
1 :7:1
RIA
Receiver Interrupt
Active
1 :E:7
RIE
Receiver Interrupt
Enable
Receiver Setup Bit
1 :E:2
RSB
RTH
Receiver Threshold
Field
1 :E:3
1 :7:6,7
The host processor obtains channel data from the receiver in the parallel data mode by
reading a data byte from· the receiver data register. The data is divided on baud
boundaries as is the transmitter data.
Status bit RDA goes to a one when the receiver writes data to register 1 : O. RDA goes
to a zero when the host processor reads data from register 1 : O.
When control bit RDIS is a one, the receiver is disabled, RlSD is turned off and RXD
is clamped to all marks. This bit can be used to squelch the receiver during half duplex
transmissions over two wires. This bit must be set to a one prior to changing the
receiver configuration.
This status bit is a one whenever the receiver sample rate device is driving IRQ to zero.
When the host processor writes a one in the RIE control bit, the IRQ line of the
hardware interface is driven to zero when status bit RDA is a one.
When the host processor changes the receiver configuration or the RTH field, the host
processor must write a one in the RSB control bit. RSB goes to zero when the changes
become effective.
The receiver energy detector threshold is set by the RTH field according to the
following codes (see RSB):
RTH
0
1
2
3
RLSD On
>-43 dBm
>-33 dBm
>-26 dBm
> -16 dBm
2-56
RLSD Off
<-48 dBm
<-38 dBm
< -31 dBm
< -21 dBm
R96FT
9600 bps Fast Train Modem
R96FT Interface Memory Definitions (Continued)
Mnemonic
Name
Memory
Location
Description
RTS
Request-to-Send
0:7:7
When control bit RTS goes to a one, the modem begins a transmit sequence. It
continues to transmit until RTS is reset to zero, and the turn-off sequence has been
completed. This input bit parallels the operation of the hardware RTS control input.
These inputs are OR'ed by the modem.
SOlS
Scrambler Disable
0:7:5
When control bit SOlS is a one, the transmitter scrambler circuit is removed from the
data path.
SEPT
Short Echo
Protector Tone
0:7:0
When control bit SEPT is a one, the echo protector disable tone is 30 ms long rather
than 185 ms. (See TSB.)
TBA
Transmitter Buffer
Available
O:E:O
This status bit resets to zero when the host processor writes data to transmitter data
register 0: O. When the transmitter empties register 0: 0, this bit sets to a one.
TCF
Transmitter Carrier
Frequency
0:9:3
Control bit TCF selects the modulator carrier frequency for V.29FT configurations as follows:
Modulator Carrier Frequency
1700 Hz
1800 Hz
TCF
0
1
TIA
Transmitter
Interrupt Active
0:E:7
This status bit is a one whenever the transmitter is driving IRQ to a zero.
TIE
Transmitter
Interrupt Enable
0:E:2
When the host processor writes a one in control bit TIE, the IRQ line of the hardware
mterface is driven to zero when status bit TBA is at a one.
TLVL
Transmitter Level
Field
0:4:2-4
The transmitter analog output level is determined by eight TLVL codes, as follows:
TLVL
0
1
2
3
4
5
6
7
'Each step above
IS
Transmitter Analog Output'
-1 dBm ±1 dB
-3dBm ±1 dB
-5dBm ±1 dB
-7 dBm ±1 dB
-9 dBm ±1 dB
-11 dBm ±1 dB
-13dBm ±1 dB
-15 dBm ±1 dB
a 2 dB change ± 0.2 dB.
TOO
Train-On-Data
1 :6:7
When control bit TOO is a one, it enables the train-on-data algorithm to converge the
equalizer if the signal quality degrades sufficiently. When TOO is a one, the modem still
recognizes a traming sequence and enters the force train state. A BER of approximately
10- 3 for 0.5 seconds initiates train-an-data.
TONE
Tone Detect
1 :8:7
TONE indicates with a zero the presence of energy in the 250-650 ± 10 Hz or
2100 ±20 Hz frequency range. For call progre:;s purposes, the user may determine
which tone is present by determining the duty cycle of the TONE bit.
TPOM
Transmitter Parallel
Data Mode
0:7:2
When control bit TPDM is a one, the transmitter accepts data for transmission from the
transmitter data register (0: 0) rather than the serial hardware data input.
2-57
•
R96FT
9600 bps Fast Train Modem
R96FT Interface Memory Defil'ition$ (Continued)
Mnemonic
(None)
Name
Transmitter
Configuration
Memory
Location
0:6:0-7
Description
<
The host processor configures the transmitter by writing a control byte into the transmitter configuration register in its interface memory space. (See TSB.)
Transmitter Configuration Control Codes
Control codes for the modem transmitter configurallons are:
Configuration
V29
V27 bis/ter
Configuration Code (Hex)
FT/2400
1C
1A
19
OA
09
4800
2400
4800
2400
14
12
11
22
21
02
01
FT/9600
FT/7200
FT/4800
FTl4800
9600
7200
4800
long
long
short
short
2400/4800 bps GearshiftN.29 Scrambler
2400/4800 bps GearshiftN.27 bis/ter Scrambler
61
41
V.21 Channel 2
See FSKT
Tone transmit
80
DTMF Tone Transmit"
81
"Note: Added in R5339-11.
(None)
Transmitter Datal
DDR
0:0:0-7
1. The host processor conveys output data to the transmitter in the parallet mode by
writing a data byte to the transmitter data register. The data is divided on baud
boundaries, as follows:
2. Register 0: 0 is used to transmit DTMF digits when the transmitter is configured in
the DTMF tone transmit mode.
<
Note: Data is transmitted bit zero first.
Bits
Configuration
V.29 9600 bps
7
I
6
5
I
4
3
J
Baud 1
V.29 7200 bps
Not Used
V.29 4800 bps
Baud 3
V.27 4800 bps
Not Used
2
.l
1
I
0
Baud 0
Baud 1
Baud 2
Baud 1
I
Baud 0
Baud 1
I
I
Baud 0
Baud 0
V.27 2400 bps
Baud 3
Baud 2
Baud 1
I
Baud 0
2400 bps Gearshift
Baud 3
Baud 2
Baud 1
I
Baud 0
4800 bps Gearshift
Baud 1
Baud 0
TSB
Transmitter Setup
Bit
0:E:3
When the host processor changes the transmitter configuration, the SEPT bit or the
FSKT bit, the host must write a one in this control bit. TSB goes to a zero when the
change becomes effective. Worst case setup time is 2 baud + turnoff sequence
+ training (if applicable).
TIDIS
Transmitter Train
Disable
0:7:6
When control bit TIDIS is a one, the transmitter does not generate a training sequence
at the start of transmission. With training disabled, RTS/CTS delay is less than two baud
times.
XCEN
External Clock
Enable
0:7:1
When control bit XCEN is a one, the transmitter timing is established by the external
clock supplied at the hardware input XTCLK.
Auto Dial Sequence
and interdigit delay. The tone duration is 95 ms and the interdigit delay is 71 ms. The amplitudes for the high and low frequencies are - 4 dBm and - 6 dBm, respectively.
The R96FT Auto Dial Sequence flowchart defines the auto dial
sequence via the microprocessor interface memory. The modem
timing for the auto dialer accounts for DTMF tone duration
2-58
9600 bps Fast Train Modem
R96FT
•
R96FT Auto Dial Sequence Flowchart
2-59
9600 bps Fast Train Modem
R96FT
POWER-ON INITIALIZATION
POLLING SUCCESS
In the 9600 bps fast train configuration the modem approaches
a 98% success rate over unconditioned 3002 lines for a signalto-noise ratio of 26 dB, With a received signal level of - 20 dBm.
When power is applied to the R96FT, a period of 50 to 350 ms
is required for power supply settling. The power-on-reset signal
(paR) remains low during this period. Approximately 10 ms after
the low to high transition of paR, the modem is 'ready to be
configured, and RTS may be activated. If the 5 Vdc power supply
drops below 3.5 Vdc for more than 30 msec, the paR cycle is
generated.
BIT ERROR RATES
The Bit Error Rate (BER) performance of the modem is specified
for a test configuration conforming to that specified in CCITI
Recommendation V.56, except with regard to the placement of
the filter used to bandlimit the white noise source. Bit error rates
are measured at a received line Signal of - 20 dBm.
At paR time the modem defaults to the following configuration:
fasttrain, V.29, 9600 bps, no echo protector tone, 1700 Hz carrier
frequency, scrambled ones segment disabled, senal data mode,
internal clock, cable equalizers disabled, transrnitter digital delay
equalizer disabled, link amplitude equalizer disabled, link delay
equalizer disabled, transmitter output level set to - 1 dBm
± 1 dB, interrupts disabled, receiver threshold set to - 43 dBm,
and train-on-data enabled.
PHASE JITTER
At 2400 bps, the modem exhibits a bit error rate of 10- 6 or less
with a signal-to-noise ratio of 12.5 dB in the presence of 15°
peak-to-peak phase jitter at 150 Hz, or with a signal-ta-noise ratio
of 15 dB in the presence of 30° peak-to-peak phase jitter at
120 Hz (scrambler inserted).
At 4800 bps (V.27 bislter), the modem exhibits a bit error rate
of 10- 6 or less with a signal-to-noise ratio of 19 dB in the
presence of 15° peak-to-peak phase jitter at 60 Hz.
paR can be connected to a user supplied power-on-reset signal
in a wire-or configuration. A low active pulse of 3!,sec or more
applied to the paR pin causes the modem to reset. The modem
is ready to be configured 10 msec after paR is removed.
At 9600 bps, the modem exhibits a bit error rate of 10 - 6 or less
with a signal-to-noise ratio of 23 dB in the presence of 10° peakto-peak phase jitter at 60 Hz. The modem exhibits a bit error
rate of 10- 5 or less with a signal-to-noise ratio of 23 dB in the
presence of 20° peak-to-peak phase jitter at 30 Hz.
PERFORMANCE
Whether functioning in V.27, V.29 or the proprietary fast train
configurations, the R96FT provides the user with high
performance.
Examples of the R96FT BER performance are shown below. The
BER curves were prepared from data obtained using a TAS10l0
test system.
,
4800 BPS
2400/4800 BPS
V.27
GEARSHIFT
AND
7200 BPS
AND
V.29
9600 BPS
300 BPS 2400 BPS 4800 BPS~
V.29
V.21
V.27
;
V.29
I
10- 3
\
10-'
\
2400/4800 BPS
300 BPS
V.21
~
oo(
a:
a:
0
a:
a:
w
10- 5
10-'
0
2
4
6
8 10 12 14 16 18
SIGNAL TO NOISE RATIO (dB)
\
w
I00(
a:
a:
0
a:
a:
w
r-
iii
10- 5
\
\
,
10- 6
V
~\
\
\
r-
iii
I
10- 3
\
w
r-
GEARSHIFT
AND
4800 BPS
V.29
7200 BPS
2400 BPS "\4800 BPS V.29
9600 BPS
V.29
V.27
V.27
20
22
,
10- 6
24
2
Typical BER Performance
Back-to-Back, - 20 dBm Receive Signal Level
4
6
\
8 10 12 14 16 18 20 22
SIGNAL TO NOISE RATIO (dB)
24
\
26
Typical BER Performance
3002 Unconditioned Line, - 20 dBm Receive Signal Level
2-60
R96FT
9600 bps Fast Train Modem
GENERAL SPECIFICATIONS
Modem Power Requirements
Voltage
Tolerance
Current (Typical) @ 25°C
+5 Vdc
+ 12 Vdc
-12 Vdc
±5%
±5%
±5%
550 mA
20 mA
50 mA
Current (Max) @ DOC
700 mA
30 mA
BO mA
Note: All voltages must have ripple '" 0.1 volts peak-to-peak.
Modem Environmental Restrictions
Parameter
Temperature
Operating
Storage
Relative Humidity:
Altitude
Specification
O°C to +60°C (32°F to 140°F)
- 40°C to + BO°C (- 40°F to 176°F) (Stored in heat sealed antistatic bag and shipping container)
Up to 90 010 noncondensing, or a wet bulb temperature up to 35°C, whichever is less.
- 200 feet to + 10,000 feet
Modem Mechanical ConSiderations
Parameter
DIN Connector Version
Board Structure:
Mating Connector:
Dimensions:
Width
Length
Height (max.)
Weight (max):
Lead Extrusion (max.):
DIP Connector Version
Board Structu re:
Dimensions:
Width
Length
Height (max.)
Weight (max.):
Pin Length (max.)
Specification
Single PC board with a 3-row 64-pin right angle male DIN connector with rows A and C populated.
The modem can also be ordered with the following DIN connector: 64-pin DIN right angle female,
64-pin DIN vertical male, or 6 64-pin DIN vertical female.
Female 3-row 64-pin DIN receptacle with rows A and C populated. Typical mating connector:
Winchester 96S-6043-0531-1, Burndy R196B32ROOAOOZ1, or equivalent.
3.937 in. (100 mm)
4.725 in. (120 mm)
0.30 in. (1.6 mm)
3.6 oz. (100 g)
0.100 in. (2.54 mm)
Single PC board with a row of 30 pins and a row of 31 pins in a dual in-line pin configuration.
3.937 in. (100 mm)
3.22B in. (B2 mm)
0.30 in. (1.6 mm) above, 0.13 in. (3.30 mm) below
3.6 oz. (100 g)
0.53 in. (13.5 mm)
2-61
•
R96FT
9600 bps Fast Train Modem
II
!
r
0.156 :1;0.003 DIA (6 PL)
(3.96)
MALE 64-PIN
DIN CONNECTOR
:r
-
T
3.937
)
II
--0.
.700
(94)
1
1
+-_
,
0.119
(3)1
-
~
.,~~
4.100 (83)
+-(
f.--
•
O. 483
(1 2.3)
4.725 (104)
120
I
0.300 MAX
-(7.6j
L, __
10'~S2
[]=£i
0.437
u
_____
u u
n
_
n n n
,
~ ~;.~~
--
- -
MAX ]
~COMPONENT
(1.6)
AREA
DIN CONNECTOR VERSION
1
0.250
iWooo=(s.4;o;soo<)-~--,
3.228
(82)
3.025
(76.8)
0.100 DIA (3 PL)
~.
l
.,\"
0
(2.54)
0.100.
(2.54)
(2.54)
l
~::~;;:o "
0.53 MAX
(2.54)
3725
-'- __
3.937 (94.6)
(100)---~
0.025
sa. PIN
0.300 MAX
ri-:"':'""",I7
---T~.~~;---------
UNITS: INCHES
------"~.130
(1.6)
(3.3)
COMPONENT AREA
DIP CONNECTOR VERSION
R96FT Modem Dimensions and Pin Locations
2-62
mm
R96FT/SC
Integral Modems
'J.'
Rockwell
R96FT/SC
9600 bps Fast Train Modem
with Forward Secondary Channel
INTRODUCTION
FEATURES
The Rockwell R96FT/SC is a synchronous serial 9600 bps modem containing a 75 bps asynchronous FSK forward channel. This
modem is designed for multipoint and networking applications.
The R96FT/SC allows full-duplex operation over 4-wire dedicated
unconditioned lines, or half-duplex operation over the general
switched telephone network.
•
•
•
•
•
•
•
•
•
•
•
Proprietary fast train configurations provide training times of
?3 ms for V.29FT/9600/7200/4800, 22 ms for V.27FT/4800, and
30 ms for V.27FT/2400. A 2400/4800 bps Gearshift configuration provides a training time of 10 ms. For applications requiring
operation with international standards, fallback configurations
compatible with CCITT Recommendations V.29 and V.27 bis/ter
are provided. A 300 bps FSK configuration, compatible with
CCITT V.21 Channel 2, is also provided.
•
The small size and low power consumption of the R96FT/SC
offer the user flexibility in formulating a 9600 bps modem design customized for specific packaging and functional requirements.
•
This data sheet corresponds to assembly number
TR96-D500-021.
•
•
•
•
Proprietary Fast Train
75 bps Forward Channel
2400/4800 bps Gearshift
User Compatibility:
- CCITT V.29, V.27 bis/ter and V.21 Channel 2
Train on Data
Full-Duplex (4-Wire)
Half-Duplex (2-Wire)
Programmable Tone Generation
Dynamic Range -43 dBm to -5 dBm
Diagnostic Capability
Equalization:
- Automatic Adaptive
- Compromise Cable (Selectable)
- Compromise Link (Selectable)
DTE Interface:
- Microprocessor Bus
- CCITT V.24 (RS-232-C Compatible)
Loopbacks
- Local Analog (V.54 Loop 3)
- Remote Analog (Locally Activated)
- Remote Digital (Locally Activated V.54 Loop 2)
Small Size
-100 mmx160 mm (3.94 in.x6.3 in.)
Low Power Consumption
- 4 watts, typical
Programmable Transmit Output Levels for Primary Channel
and Forward Channel
TTL and CMOS Compatible
R96FT/SC Modem
Document No_ 29200N13
Data Sheet
2-63
Order No. MD13
Rev_ 3, January 1989
•
R96FT/SC
9600 bps Fast Train Modem
TECHNICAL SPECIFICATIONS
link Eq,..alizers - Selectable compromise link equalizers in the
receiver optimize performance over channels exhibiting severe
amplitude and delay distortion. Two standards are provided: U.S.
survey long and Japanese 3-link.
TRANSMITTER CARRIER FREQUENCIES
Function
V.27 bislter Carrier
V.27 FT Carrier
2400/4800 bps Gearshift
V.29 Carrier
V.29 FT Carrier
V.21 Channel 2:
Mark
Space
Frequency
(Hz ±O.O1%)
Automatic Adaptive Equalizer - An .automatic adaptive T
equalizer is provided in the receiver circuit.
1800
1800
1800
1700
1700'
TRANSMITTED DATA SPECTRUM
If the cable equalizer is not enabled, the transmitter spectrum
is shaped by the following raised cosine filter functions:
1. 1200 Baud. Square root of 90 percent.
2. 1600 Baud. Square root of 50 percent.
3. 2400 Baud. Square root of 20 percent.
NOTE
When used with the 75 bps Forward Channel the
2400 Baud filter is narrower.
1650
1850
'1800 when used in conjunction with 75 bps Forward Channel.
TONE GENERATION
Under control of the host processor, the R96FT/SC can generate
voice band tones up to 4800 Hz with a resolution of 0.15 Hz and
an accuracy of 0.01 %. Tones over 3000 Hz are attenuated.
The out-of-band transmitter power limitations meet those
specified by Part 68 of the FCC's rules, and typically exceed
the requirements of foreign telephone regulatory bodies.
SIGNALING AND DATA RATES
Parameter
Signaling Rate:
Data Rate:
SCRAMBLER/DESCRAMBLER
Specification
(±O.01%)
2400
9600
7200
4800
The R96FT/SC incorporates a self-synchronizing scramblerl
descrambler. This facility is in accordance with either V.27 bislter
or V.29 depending on the selected configuration.
baud
bps,
bps,
bps
Signaling Rate:
Data Rate:
1600 baud
4800 bps
Signaling Rate:
Data Rate:
Gearshift Data Rate:
1200 baud
2400 bps
Signaling Rate:
Data Rate:
300 baud
300 bps
Signaling Rate:
Data Rate:
75 baud
75 bps
The scrambler/descrambler facilities for Gearshift can be
selected to be in accordance with either V.27 bistter or V.29.
The scrambler/descrambler selection is made by writing the
appropriate configuration codes into the transmitter and receiver.
RECEIVED SIGNAL
FREQUENCY TOLERANCE
2400/4800 bps
The receiver circuit of the R96FT/SC can adapt to received
frequency error of up to ± 10Hz with less than 0.2 dB degradation in BER performance.
OWing fast train polling, frequency offset must be less than
±2 Hz for successful training.
DATA ENCODING
RECEIVE LEVEL
At 2400 baud, the data stream is encoded per CCITT V.29. At
9600 bps, the data stream is divided in groups of four-bits (quadbits) forming a 16-point structure. At 7200 bps, the data stream
is divided into three bits (tribits) forming an 8-point structure.
At 4800 bps, the data stream is divided into two bits (dibits)
forming a 4-point structure.
The receiver circuit of the modem satisfies all specified performance requirements for received line signal levels from -5 dBm
to -43 dBm. The received line signal level is measured at the
receiver analog input (RXA).
RECEIVE TIMING (Synchronous Configurations)
At 1600 baud, the 4800 bps data stream is encoded into tribits
per CCITT V.27 bistter.
The R96FTlSC provides a data derived Receive Data Clock
(ROCll<) output in the form of a squarewave. The low-te-high
transitions of this output coincide with the centers of received
data bits. For the Gearshift Configuration, the first 32 bauds of
data are at 2400 bps followed by 4800 bps data for the remaining message. The timing recovery circuit is capable of tracking
a ± 0.01 % frequency error in the associated transmit timing
source. ROClK duty cycle is 50% ± 1%.
At 1200 baud, the 2400 bps data stream is encoded into dibits
per CCITT V.27 bis/ter.
For the Gearshift Configuration, the signaling rate is 1200 baud.
The 2400 bps data stream is encoded into dibits forming a 4-point
structure, and the 4800 bps data stream is encoded into quadbits forming a 16-point structure. The first 32 bauds of data are
transmitted at 2400 bps and the remaining message is· transmitted at 4800 bps.
TRANSMIT LEVEL
The main channel output level is accurate to ± 1.0 dB and is
programmable from - 1.0 dBm to -15.0 dBm in 2 dB steps.
At 300 baud, the 300 bps data stream is encoded per CCITT
V.21 channel 2 into a mark frequency of 1650 Hz and a space
frequency of 1850 Hz.
The forward channel transmit level is set relative to the main
channel as -6dB, -10dB, -14dB, or -18dB.
At 75 baud, the 75 bps data stream is encoded to a mark frequency of 356 Hz and a space frequency of 300 Hz.
TRANSMIT TIMING (Synchronous Configurations)
The R96FT/SC provides a Transmit Data Clock (TOClK) output with the following characteristics:
1. Frequency. Selected data rate of 9600, 7200, 4800, 2400 or
300 Hz (± 0.Q1 %). For the Gearshift Configuration, TOClK
is a 2400 Hz clock for the first 32 bauds of data, and a
4800 Hz clock for the remaining message.
2. Duty Cycle. 50% ± 1%
EQUALIZERS
The R96FT/SC provides equalization functions that improve performance when operating over low quality lines.
Cable Equalizers - Selectable compromise cable equalizers in
the receiver and transmitter are provided to optimize performance
over different lengths of non-loaded cable of 0.4 mm diameter.
2-64
R96FT/SC
9600 bps Fast Train Modem
RESPONSE TIMES OF CLEAR TO SEND (CTS)
Input data presented on TXO is sampled by the R96FTlSC at
the low-ta-high transition of TDCLK. Data on TXO must be stable
for at least one microsecond prior to the rising edge of TOCLK
and remain stable for at least one microsecond after the rising
edge of TOCLK.
EXTERNAL TRANSMIT CLOCK
The time between the off-to-on transition of Request To Send
(RTS) and the off-to-on transition of Clear to Send (CTS) is
dictated by the length of the training sequence and the echo
protector tone, if used. These times are given in the Turn-On
Sequences table. If training is not enabled, RTS/CTS delay is
less than 2 baud times.
The transmitter data clock (TOCLK) can be phase locked to a
signal on input XTCLK. This input signal must equal the desired
data rate ± 0.01 olb with a duty cycle of 50% ± 20%.
The time between the on-ta-off transition of RTS and the on-tooff transition of CTS in the data state is a maximum of 2 baud
times for all configurations.
TRAIN ON DATA
RESPONSE TIMES OF FORWARD CHANNEL
CLEAR TO SEND (SCCTS)
When train on data is enabled (by setting a bit in the interface
memory), the modem monitors the EOM signal. If EOM indicates
a loss of equalization (Le., BER approximately 10- 3 for
0.5 seconds) the modem attempts to retrain on the data stream.
The time for retrain is typically 3 to 15 seconds.
SCRTS/SCCTS response times vary according to the transmit
level set by the SCTLVL field.
TURN-ON SEQUENCE
A total of 20 selectable turn-on sequences can be generated
as defined in the following table:
No.
V.29
(bps)
V.27
blslter
(bps)
RTS-CTS
Gearshift Response Time
(bps)
(milliseconds) Comments
1 FT/9600
2 FT17200
3 FT/4800
4
FT/4800
FT/2400
5
6
7
8
9
10
11
12
13
9600
7200
4800
14
15
16
17
18
19
20
9600
7200
4800
4800
2400
4800
2400
23
24
23
22
30
long
long
short
short
2400/4800
4800 long
2400 long
4800 short
2400 short
TX Level
Relative to Primary
SCCTS Response Time
(ms)
0
1
2
3
-6 dB
-10 dB
-14dB
-18 dB
378
238
150
95
RECEIVE LINE SIGNAL DETECTOR (RLSD)
Response
For Fast Train and Gearshift configurations, the receiver enters
the training state upon detecting a significant increase in the
received signal power. If the received line signal power is greater
than the selected threshold level at the end of the training state,
the receiver enters the data state and RLSO is activated. If the
received line signal power is less than the selected threshold
level at the end of the training state, the receiver returns to the
idle state and RLSO is not activated.
Proprietary
Fast Train
253
253
253
708
943
50
67
10
438
438
438
913
1148
255
272
SCTLVL
(0:9:0-1)
Also, in Fast Train and Gearshift configurations, the receiver
initiates the turn-off delay upon detecting a significant decrease
in the received signal power. If the received signal power is less
than the selected threshold at the end of the turn-off delay, the
receiver enters the idle state and RLSO is deactivated. If the
received signal power is greater than the selected threshold at
the end of the turn-off delay, the receiver returns to the data state
and RLSO is left active.
Preceded'
by Echo
Protector
Tone for
lines uSing
echo
suppressors.
For CCITT configurations, the receiver enters the training
detection state when the received line signal power crosses the
selected threshold level. RLSO is activated at the end of the
training sequence. For V.21 Channel 2, a separate received line
signal detector (FRLSO) is provided. FRLSO is activated when
energy above -43 dBm is present at the receiver's audio input
(RXA). The FRLSO off-to-on response time is 15 ±5 ms and
the on-to-off response time is 25 ± 5 ms.
1. For short echo protector tone, subtract 155 ms from values of
RTS-CTS response time.
2. V.21 (300 bps FSK) RTS-CTS response time is < 35 ms.
3. 75 bps forward channel SCRTS-SCCTS response time is
<500 ms.
The RLSO on-to-off response times are:
TURN-OFF SEQUENCE
For V.27bislter, V.27FT and 2400/4800 bps Gearshift configurations, the turn-off sequence consists of approximately 10 ms
of remaining data and scrambled ones followed by a 20 ms
period of no transmitted energy (V.27 bis/ter only). For V.29 and
V.29FT, the turn-off sequence consists of approximately 8 ms
of remaining data and scrambled ones.
Configuration
V.29 Fast Train
V.27 Fast Train
Gearshift
V.29
V.27 bistter
CLAMPING
Response Time (ms)
6.5
8
6
30
10
±1
±1
±1
±9
±5
RLSO response times are measured with a signal at least 3 dB
above the actual RLSO on threshold or at least 5 dB below the
actual RLSO off threshold.
Received Data (RXO) is clamped to a constant mark (one) when
the Received Line Signal Detector (RLSO) is off.
2-65
•
9600 bps Fast Train Modem
R96FT/SC
Threshold Options
Threshold
Four threshold options are provided:
1. Greater than - 43 dBm (RLSO on)
Less than - 48 dBm (RLSO off)
2. Greater than - 33 dBm (RLSO on)
Less than - 38 dBm (RLSO off)
3. Greater than - 26 dBm (RLSO on)
Less than - 31 dBm (RLSO off)
4. Greater than -16 dBm (RLSO on)
Less than - 21 dBm (RLSO off)
The SCRLSO Turn-On threshold is - 54 dBm. The SCRLSO
Turn-Off threshold is - 58 dBm.
MODES OF OPERATION
The R96FT/SC is capable of being operated in either a serial
or a parallel mode of operation.
SERIAL MODE
The serial mode uses standard V.24 (RS-232-C compatible) signals to transfer channel data. An optional USRT device (shown
in the Functional Interconnect Oiagram) illustrates this capability.
NOTE
Performance may be at a reduced level when the received
signal is less than - 43 dBm.
PARALLEL MODE
The R96FT/SC has the capability of transferring channel data
(up to eight bits at a time) via the microprocessor bus.
For CCITT configurations, a minimum hysteresis action of 2 dB
exists between the actual off-to-on and on-t()-off transition levels.
The threshold levels and hysteresis action are measured with
unmodulated 2100 Hz tone applied to the receiver's audio input
(RXA).
MODE SELECTION
For the transmitter, a control bit determines whether the source
of transmitted data is the V.24 interface (serial mode) or the
parallel transmitter data register (parallel mode). The transmitter
automatically defaults to the serial mode at power-on.
FORWARD CHANNEL SIGNAL DETECTOR (SCRLSD)
Response
Signal Level
SCRLSO Turn-On (ms)
SCRLSO Turn-Off (ms)
-7dBm
140t10
800t10
-48dBm
340t 10
550t10
r-----.,
I
~
CTS
X
TDCLK
XTCLK
RLSD
RXD
RDCLK
TBCLK
RBCLK
A,.
USRT
I (OPTIONAL)
I
I
...I
I
I
r
L_--
l
.J
IDECODER !'"'
CS (3)
EVEX
xt tv
EVEV
EVSYNC
EYECLK
EVE
PATTERN
GENERATOR
+12V
READ
ADDRESS BUS {4[
t
qCOPE
MODEM
WRITE
DATA BUS (8)
HOST
PROCESSOR
(DTE)
In either parallel or serial mode the R96FT/SC is configured by
the host processor via the microprocessor bus.
RTS
.....
I
I
I
The receiver simultaneously outputs received data via the V.24
interface and the parallel receiver data register.
+5V
GND
-12V
TXA
Oi
RSi
RXA
CSi
AUXIN
POR
fRO
+5~
r
-
- .,
I
UART
I (OPTIONAL)
I
IL.
S-C-R-T-S
~~SC=C=TS~-'~
I
_
_
_
_
POWER
SUPPLY
SCTXO
SCRLSD
I~~S=CR=X=D~--U
I~-===~--~'--_ _ _ _ _...J
R96FT/SC Functional Interconnect Diagram
2-66
LINE
INTERFACE
~}
TELEPHONE
LINE
R96FT/SC
9600 bps Fast Train Modem
INTERFACE CRITERIA
R96FT/SC Hardware Circuits (Continued)
The modem interface comprises both hardware and software
circuits. Hardware circuits are assigned to specific pinS in a
64-pin DIN connector. Software circuits are assigned to specific bits in a 46-byte interface memory.
Name
HARDWARE CIRCUITS
1
Eye
Eye
Eye
Eye
Pattern Data-X AxiS
Pattern Data-Y Axis
Pattern Clock
Pattern Synchronizing Signal
Eye Pattern Generation
R96FT/SC Hardware Circuits
Microprocessor Timing
B. MICROPROCESSOR INTERFACE:
lC
D7
1I0A
D6
1I0A
lA
2C
D5
1I0A
1I0A
2A
D4
Data Bus (8 Bits)
D3
1I0A
3A
1I0A
4C
D2
Dl
1I0A
4A
DO
1I0A
5C
RS3
6C
IA
RS2
IA
6A
Register Select (4 Bits)
RSI
IA
7C
RSO
IA
7A
CSO
IA
10C
Chip SelectTransmitter Device
Chip Select-Receiver
CSI
IA
9C
Sample Rate Device
CS2
IA
9A
Chip Select-Receiver
Baud Rate Device
READ
12C
IA
Read Enable
llA
Write Enable
WRITE
IA
l1C
IRQ
Interrupt Request
OB
READ
}
WRITE
CSi
(i
}
= 0-2)
RSi
(I = 0-3)
READ
C. V.24 INTERFACE:
21A
23A
22A
25A
25C
24C
22C
24A
21C
20A
19A
20C
18A
I
15C
14A
14C
13A
Description
The four hardware diagnostic circuits, identified In the preceding
table, allow the user to generate and display an eye pattern.
Circuits EYEX and EYEY serially present eye pattern data for
the horizontal and vertical display Inputs respectively. The 8-bit
data words are shifted out most significant bit first, clocked by
the rising edge of the EYECLK output. The EYESYNC output
is provided for word synchronization. The falling edge of
EYESYNC may be used to transfer the 8-bit word from the shift
register to a holding register. Digital to analog conversion can
then be performed for driving the X and Y inputs of an
oscilloscope.
Pin No.
Description
Type I
I
r A. OVERHEAD:
31C,32C
Ground (A) AGND
Analog Ground Return
Digital Ground Return
Ground (D) DGND 3C,8C,5A, 1OA
+5 volts
PWR 19C,23C,26C,30C + 5 Vdc supply
15A
+ 12 volts PWR
+ 12 Vdc supply
-12 volts PWR
12A
- 12 Vdc supply
13C
Power-on· reset
POR
1I0B
OC
OC
IB
IB
OC
IB
OC
OC
IB
OC
IB
OD
OD
I Pin No. I
Unused inputs tied to + 5V or ground require individual 10K [)
senes resistors.
Name
RDCLK
TDCLK
XTCLK
RTS
CTS
TXD
RXD
RLSD
SCRTS
SCCTS
SCTXD
SCRLSD
SCRXD
Type
I oc
Signal names and descriptions of the hardware circuits, Including the microprocessor interface, are listed in the R96FT/SC
Hardware Circuits table. In the table, the column titled 'Type'
refers to designations found in the Hardware Circuit Characteristics. The microprocessor interface is designed to be directly compatible with an 8080 microprocessor. With the addition of a few
external logic gates, it can be made compatible with 6500, 6800,
or 68000 microprocessors.
I
I
F. DIAGNOSTIC:
OC
EYEX
EYEY
EYECLK
OA
EYESYNC
OA
Receive Data Clock
Transmit Data Clock
External Transmit Clock
Request to Send
Clear to Send
Transmitter Data
Receiver Data
Received Line Signal Detector
Forward Channel RTS
Forward Channel CTS
Forward Channel TXD
Forward Channel RLSD
Forward Channel RXD
Di
(i
= 0-7)
Microprocessor Interface Timing Diagram
Critical Timing Requirements
Characteristic
Symbol
Min
Max
Units
TCS
TDA
TDH
30
-
nsec
10
140
50
nsec
TCH
TWDS
TWDH
TWR
10
75
10
75
-
D. ANCILLARY CIRCUITS:
RBCLK
TBCLK
FRXD
OC
OC
OD
26A
27C
16A
FRLSD
OD
HC
E. ANALOG SIGNALS:
TXA
AA
31A
RXA
32A
AB
AUXIN
AC
30A
CSi, RSI setu~e prior
to Read or Write
Data access time after Read
Data hold time after Read
CSI, RSI hold time after
Read or Write
Write data setup time
Write data hold time
Write strobe pulse Width
Receiver Baud Clock
Transmitter Baud Clock
FSK Receiver Data
(Inverted data)
FSK Received Line Signal
Detector
Transmitter Analog Output
Receiver Analog Input
Auxiliary Analog Input
2-67
nsec
nsec
nsec
nsec'
nsec
•
9600 bps Fast Train Modem
R96FT/SC
Digital Interface Characteristics
Input/Output Type
~ymbo
VIH
Parameter
Input Voltage, High
Unite
IA
IB
IC
V
2.0 Min.
2.0 Min.
2.0 Min.
0.8 Max.
0.8 Max.
0.8 Max.
VIL
Input Voltage, Low
V
VOH
Output Voltage, High
V
VOL
liN
Output Voltage, Low
Input Current,
Leakage
10H
Output Current, High mA
10L
IL
Output Current, Low
Output Current,
Leakage
Pull-up Current
(Short Circuit)
lpu
OB
2.4 Min.'
0.4 Max.2
V
OC
0.4 Max. 2 0.4 Max. 2
OD
2.2 Min. 8
0.6 Max.7
,.A ±2.5 Max.
-0.1 Max.
1.6 Max.
mA
,.A
,.A
CL
Capacitive Load
pF
Co
Capacitive Drive
pF
5
TTL
Note. 1. I Load
100 ,.A
2. I Load
1.6 mA
3. I Load
-40,.A
4. V IN = 0.4 to 2.4 Vdc, Vee
1.6 Max.
±10 Max.
-240 Max. -240 Max.
-10 Min. -10 Min.
5
20
TTL
w/Pull-up
TTL
w/Pull-up
110 A
1I0B
2.0 Min.
5.25 Max.
2.0 Min.
0.8 Max.
2.4 Min.3
0.4 Max. s
0.8 Max.
2.4 Min.'
0.4 Max. 2
±2.5 Max. 4
1.6 Max.
-240 Max.
-10 Min.
100
Circuit Type
==
=
OA
TTL
100
10
100
100
Open-Drain Open-Drain
w/Pull-up
TTL
-260 Max.
-100 Min.
40
100
3-State Open-Drain
Transceiver w/Pull-up
5. I Load = 0.36 mA
6. I Load = - 400 ,.A
7. I Load = 2.0 mA
= 5.25 Vdc
Analog Interface Characteristics
When information in these registers is being discussed, the
format Y:Z:Q is used. The chip is specified by Y(O-2), the register
by Z(O-F), and the bit by 0(0-7, 0 = LSB).
Nama
Type
TXA
AA
The transmitter output impedance is 604 ohms
Characteristics
± l oAl
Status Control Bits
RXA
AB
The receiver input impedance is 60K ohms
AUXIN
AC
The auxiliary analog input allows access to the
transmitter for the purpose of interfacing with
user provided equipment. Because this is a
sampled data input, any signal above 4800 Hz
will cause aliasing errors. The input impedance
is 1K ohms, and the gain to transmitter output is
TLVL setting + 0.6 dB -1.4 dB. If unused, this
input must be grounded near the modem
connector. If used, it must be driven from a low
impedance s!lurce.
The operation of the R96FT/SC is affected by a number of software control inputs. These inputs are written into registers within
the interface memory via the host microprocessor bus. Modem
operation is monitored by various software flags that are read
from interface memory via the host microprocessor bus. All status
and control bits are defined in the Interface Memory table. Bits
designated by a dash (-) are reserved for modem use only and
must not be changed by the host.
±23%.
RAM Data Access
The R96FT/SC provides the user with access to 'mUCh of the
data stored in the modem's memories. This data Is useful for
performing certain diagnostic functions.
SOFTWARE CIRCUITS
The R96FT/SC comprises three signal processor chips. Each
of these chips contains 16 registers to which an external (host)
microprocessor has access. Although these registers are within
the modem, they may be addressed as part of the host
processor's memory space. The host may read data out of or
write data into these registers. The registers are referred to as
interface memory. Registers in chip 1 update at half the modem
sample rate (4800 bps). Registers in chip 0 and 2 update at the
selected baud rate.
Two RAM access registers in chip 2 allow user access to RAM
locations via the X word registers (2:3 and 2:2) and the Y word
register (2:1 and 2:0). The access code stored in RAM ACCESS
X (2:5) selects the source of data for RAM DATA XM and RAM
DATA XL (2:3 and 2:2). Similarly, the access code stored in RAM
ACCESS Y (2:4) selects the source of data for RAM DATA YM
and RAM DATA YL (2:1 and 2:0).
2-68
R96FT/SC
9600 bps Fast Train Modem
Transmitter Interface Memory Chip 0 (CSO)
Reading of diagnostic RAM data is performed by storing the
necessary access codes in 2:5 and 2:4, reading 2:0 to reset the
associated data available bit (2:E:0), then waiting for the data
available bit to return to a one. Data is now valid and may be
read from 2:3 through 2:0.
~
7
6
5
4
3
-
-
CF
DDEE
An additional diagnostic is supplied by the sample rate processor (chip 1). Registers 1 :2 and 1:3 supply a 16 bit AGe Gain
Word. These two diagnostic data registers are updated at the
sample rate during the data state and may be read by the host
processor asynchronously.
F
-
-
E
TIA
-
-
-
0
-
-
-
-
C
-
-
-
-
B
-
-
-
-
A
FSKT ASCR
9
RAM Access Codes
The RAM access codes defined in the following table allow the
host processor to read diagnostic information within the modem.
8
-
7
RTS
-
Function
1
2
3
4
5
Equalizer Input
Equalizer Tap Coefficients
Unrotated Equalizer Output
Rotated Equalizer Output
Decision POInts
(Ideal Data POints)
Error Vector
Rotation Angle
Frequency Correcllon
Eye Quality MOnitor (EQM)
6
7
8
9
X Access V Access Register
40
01-20
61
62
68
0.1,2,3
0,1,2,3
0,1,2,3
0.1,2.3
0,1.2,3
E5
A7
A5
AC
65
Not Used
Not Used
Not Used
0,1,2,3
2,3
2,3
2,3
-
7
6
4
5
3
2
1
0
-
-
TSB
TIE
-
TBA
-
-
-
CEQ
-
-
-
-
SCTLVL
-
EPT TPDM XCEN SEPT
A3L
D3L
L2ACT LCEN
FREQM
FREQL
-
1
-
-
-
-
-
-
-
1
0
TRANSMITTER DATA
0
Register
/s:
7
6
5
4
3
2
NOTE
(-) Indicates reserved for modem use only
Receiver Interface Memory Chip 2 (CS2)
~
0
7
6
5
-
4
3
2
1
0
-
-
-
RBIE
-
RBDA
-
Register
F
-
E
RIA
0
-
C
-
-
B
-
-
-
-
-
-
-
-
-
A
-
-
-
9
-
FED
-
-
-
CDET
-
8
-
-
-
-
-
DDIS
-
-
RTH
7
6
TOD
5
-
4
-
-
-
-
-
-
RSB
RIE
-
-
-
-
-
P2DET
-
-
SCEN RDIS
-
-
-
RDA
E
RBIA
-
-
-
-
0
-
-
-
C
-
-
-
-
-
-
-
-
B
-
-
-
-
A
-
-
-
-
-
-
9
-
-
-
-
-
-
-
8
-
-
-
-
-
7
-
6
-
-
-
-
-
-
-
2
1
F
-
RECEIVER CONFIGURATION
-
-
-
-
-
-
-
-
-
-
-
5
RAM ACCESS X
4
RAM ACCESS Y
RAM DATA XM
3
AGC GAIN WORD (MSB)
3
2
AGC GAIN WORD (LSB)
2
RAM DATA XL
1
RAM DATA YM
0
RAM DATA YL
-
-
-
-
-
-
-
-
RECEIVER DATA
0
~
-
-
TLVL
2
Register
1
-
-
LAEN LDEN
3
Receiver Interface Memory Chip 1 (CS1)
~
PCF SCRTS
L3ACT L4ACT L4HG
4
CO
B1-AO
E1
E2
E8
1
TRANSMITTER CONFIGURATION
5
Baud Rate Processor (Chip 2) RAM Access Codes
-
TTDIS SDIS MHLD
6
No.
2
Register
7
6
5
4
3
2
1
A.
0
7
6
5
4
3
Bit
Bit
NOTE
(-) Indicates reserved for modem use only.
NOTE
(-) Indicates reserved for modem use only.
2-69
-
-
0
II
9600 bps Fast Train Modem
R96FT/SC
R96FT/SC Interface Memory'Dl!finitions
Mnemonic
Name
Memory
Location
Description
ASCR
Append Scrambled
Ones
0:9:6
When control bit ASCR is a one, one baud of scrambled marks is included in the V.29FT
and V.27FT training sequences. The RTs..CTS delay is thus extended by one
baud penod when ASCR is a one
A3L
Amplitude 3--Llnk
Select
0:5:1
See LAEN
CDET
Carrier Detector
1 :9:2
When zero, status bit CDET indicates that passband energy is being detected, and
that a training sequence is not In process. CDET goes to a zero at the start of the
data state, and returns to a one at the end of the received signal. CDET activates up to
1 baud time before RLSD and deactivates within 2 baud times after RLSD.
CEO
Cable Equalizer
Field
0:5:(4,5)
The CEO Control field Simultaneously controls amplitude compromise equalizers In both
the transmit and receive paths. The follOWing table lists the possible cable equalizer
selection codes:
CEQ
Cable Length (0.4 mm diameter)
o
0.0
, 1.8 km
3.6 km
7.2 km
1
2
3
CF
Carrier Frequency
0:9:3
When control bit CF IS a one, the transmitter carrier frequency for V.29FT changes from
1700 Hz to 1800 Hz.
'
DDEE
Digital Delay
Equalizer Enable
0.9 2
When control bit DDEE is a one, a fourth order digital delay equalizer IS inserted in the
transmit path.
DDIS
Descramble Disable
1.7'5
When control bit DDIS IS a one, tM receiver descrambler Circuit IS removed from the
data path
D3L
Delay 3.. Link Select
0:5.0
See LDEN
EPT
Echo Protector
Tone
0:7:3
When control bit EPT IS a one, an unmodulated carner is transmitted for 185 ms
(optionally 30 ms) followed by 20 ms of no transmitted energy at the start of
transmiSSion. This option IS available in the V.27 and V 29 Configurations, although it is
not specified In the CCITT V 29 recommendation.
FED
Fast Energy
Detector
1'9'6
When status bit FED is a zero, It indicates that energy above the receiver threshold IS
present In the passband
(None)
FREOL/FREOM
0:2:0--7,
0.3:0--7
The host processor conveys tone generation data to the transmitter by writing a 1E1..bit
data word to the FREOL and FREOM registers In the Interface memory space, as
shown below'
FREQM Register (0:3)
Bit: I
I
IData Word: I
7
I
6
I
5
I
4
I
3
I
2
I
1
I
2'5
I
2'4
I
2'3
I
2'2
I
2"
I
2'0
I
29
I
0
28
I
2'
I
0
20
I
I
FREQL Register (0:2)
IDataw:~:1
7
6
5
3
4
27
1
2
24
22
25
23
I 28
I
I
I
I
The frequency number (N) determines the frequency (F) as follows:
F = (0.146486) (N) Hz ±0.01%
HexadeCimal frequency numbers (FREOL, FREOM) for commonly generated tones are
given below:
Frequency (Hz)
462
1100
1650
1850
FREQM
OC
10
2C
31
~oo
~
2..70
FREQL
52
55
00
55
00
I
R96FT/SC
9600 bps Fast Train Modem
R96FT/SC Interface Memory Definitions (Continued)
Mnemonic
Name
Memory
Location
Deacrlption
FSKT
FSK Transmitter
Configuration
0:9:7
The V.21 Channel 2 (300 bps synchronous FSK) transmitter configuration is selected by
setting the FSKT control bit to a one (see TSB). While set to a one, this control bn
overrides the configuration selected by the control code In register 0:6. The FSK data
may be transmitted in parallel mode or in serial mode (see TPDM).
LAEN
Link Amplitude
Equalizer Enable
0·5:3
The link amplitude equalizer enable and select bits control an amplitude compromise
equalizer in the receive path according to the following table:
LAEN
0
1
1
A3L
X
0
1
Curve Matched
No Equalizer
U.S. Survey Long
Japanese 3-Link
LCEN
Loop Clock Enable
0:4:0
When control bit LCEN IS a one, the transmitter clock tracks the receiver clock.
LDEN
Link Delay
Equalizer Enable
0:5:2
The link delay equalizer enable and select bits control a delay compromise equalizer In
the receive path according to the following table:
LDEN
0
1
1
D3L
X
0
1
Curve Matched
No Equalizer
U.S. Survey Long
Japanese 3-Link
L2ACT
Remote Digital
Loopback Activate
0:4:1
When control bit L2ACT IS a one, the receiver digital output is connected to the
transmitter digital input in accordance with cCln Recommendation V.54 loop 2.
l3ACT
Local Analog Loop·
back Activate
0:4:7
When control bit L3ACT is a one, the transmitter analog output is coupled to the
receiver analog input through an attenuator In accordance with cCln Recommendation
V.54 loop 3.
L4ACT
Remote Analog
Loopback Activate
0:4:6
When control bit L4ACT is a one, the receiver analog Input is connected to the transmitter analog output through a variable gain amplifier in a manner similar to cCln
Recommendation V.54 loop 4.
L4HG
Loop 4 High Gain
0:4:5
When control bit L4HG is a one, the loop 4 variable gain amplifier is set for + 16 dB,
and when at zero the gain is zero dB.
MHLD
Mark Hold
0:7:4
When control bit MHLD is a one, the transmitter input data stream is forced to all
marks (ones).
PCF
Primary Channel
Filter
0:9:5
When control bit PCF is a one, the 2400 baud primary channel transmitter filter is set to
a narrower bandwidth than normal.
P2DET
Period 2 Detector
1:8:3
When status bit P2DET is a zero, It indicates that a period 2 sequence has been
detected. This bit sets to a one at the start of the period N sequence. This bit is only
sigmficant for cCln V.29 and V.27 bis/ter configurations.
(None)
RAM Access X
2:5:0-7
Contains the RAM access code used in reading chip 2 RAM locations via word X (2:3
and 2:2).
(None)
RAM Access Y
2:4:0-7
Contains the RAM access code used in reading chip 2 RAM locations via word Y (2: 1
and 2:0).
(None)
RAM Data XL
2:2:0-7
Least significant byte of 16-bit word X used in reading RAM locations in chip 2.
(None)
RAM DataXM
2:3:0-7
Most significant byte of 16-bit word X used in reading RAM locations in chip 2.
(None)
RAM Data YL
2:0:0-7
Least significant byte of 16·bit word Y used In reading RAM locations in chip 2.
(None)
RAM Data YM
2·1 :0-7
Most significant byte of 16-bit word Y used in reading RAM locations in chip 2.
RBDA
Receiver Baud
Data Available
2:E:0
Status bit RBDA goes to a one when the receiver writes data into register 2: O. The bit
goes to a zero when the host processor reads data from register 2: O.
RBIA
Receiver Baud
Interrupt Active
2:E:7
ThiS status bit is a one whenever the receiver baud rate device is driving IRQ low.
RBIE
Receiver Baud
Interrupt Enable
2:E:2
When the host processor writes a one in the RBIE control bit, the IRQ line of the hard·
ware interface is driven to zero when status bit RBDA is a one.
2·71
R96FT/SC
9600 bps Fast Train Modem
R96FT/SC Interface Memory DefinitioflS (Continued)
Mnemonic
(None)
Name
Receiver
Configuration
Memory
Location
1 :6:0-6
Description
The host processor configures the receiver by writing a control code into the receiver
configuration field in the Interface memory space (see RSB).
Note: The receiver must be disabled prior to changing configurations. See RDIS.
Receiver Configuration Control Codes
Control codes for the modem receiver configuration are:
Configuration
V29
V27 bis/ter
FT/9600
FT/7200
FT/4800
Configuration Code (Hex)
lC
lA
19
OA
FT/4800
FT/2400
09
4800
2400
4800
2400
14
12
11
22
21
02
01
9600
7200
4800
long
long
short
short
2400/4600 bps GearshifW.29 descrambler
2400/4800 bps GearshiftN.27 blslter descrambler
V.21 Channel 2
61'
41'
See Note 2
1. The Receiver Configuration code automatically changes from a hex 61 (or hex 41)
to a hex 64 (or hex 44) when the receiver transitions from the 2400 bps data state
to the 4800 bps data state.
2. The FSK receiver is active at all times. Two anCillary hardware circuits, FRLSD
and FRXD, are supplied for FSK message reception. FRLSD is described under
the Received Line Signal Detector section. FRXD j:1rovides inverted FSK received
data. Timing extraction must be performed on the FRXD signal externally as no
FSK receiver data clock is provided by the R96FT/SC.
(None)
Receiver Data
1 :0:0-7
The host processor obtains channel data from the receiver In the parallel data mode by
reading a data byte from the re<;eiver data register. The data IS divided on baud boundaries as is the transmitter data
RDA
Receiver Data
Available
1 :E:O
Status bit RDA goes to a one when the receiver writes data to register 1 : O. RDA goes
to a zero when the host processor reads data from register 1 : O.
RDIS
Receiver Disable
1 '7: 1
When control bit RDIS is a one, the receiver is disabled, RLSD is turned off and RXD
is clamped to all marks. This bit can be used to squelch the receiver during half duplex
transmissions over two wires. This bit must be set to a one prior to changing the
receiver configuration.
RIA
Receiver Interrupt
Active
1 :E:7
This status bit is a one whenever the receiver sample rate device is driving IRQ to zero.
RIE
Receiver Interrupt
Enable
1 :E:2
When the host processor writes a one in the RIE control bit, the IRQ line of the
hardware interface IS driven to zero when status bit RDA is a one.
RSB
Receiver Setup Bit
1 :E:3
When the host processor changes the receiver configuration, the FSKR bit or the RTH
field, the host processor must write a one in the RSB control bit. RSB goes to zero
when the changes become effective.
RTH
Receiver Threshold
Field
1 :7:6,7
The receiver energy detector threshold is set by the RTH field according to the following codes (see RSB):
RTH
RLSO On
0
1
2
3
> -43 dBm
> -33 dBm
> -26 dBm
>-16dBm
2-72
RLSO Off
< -48
< -38
< -31
< ~21
dBm
dBm
dBm
dBm
R96FT/SC
9600 bps Fast Train Modem
R96FT/SC Interface Memory Definitions (Continued)
Mnemonic
Name
Memory
Location
Description
RTS
Request-to-Send
0:7:7
When control bit RTS goes to a one, the modem begins a transmit sequence. It continues to transmit until RTS is reset to zero, and the turn-off sequence has been completed. This input bit parallels the operation of the hardware ATS control input.
These inputs are ORed by the modem.
SCEN
Forward Channel
Enable
1 :7:2
When control bit SCEN is a one, the forward channel demodulator is enabled and the
primary channel receiver carrier frequency is changed from 1700 to 1800 Hz in V.29 FT
configurations.
SCRTS
Forward Channel
Request-to-Send
0:9:4
When control bit SCATS is a one, the modem beginS a forward channel transmit sequence. Transmission continues until SCRTS is a zero. SCRTS in the interface memory
IS ORed with signal SCRTS on the card connector
SCTlVl
Forward Channel
Transmit level
0:9:0-1
The forward channel transmit level is set relative to the main channel transmit level by
the following SCTl Vl codes:
SCTLVL
Code
0
1
2
3
Forward Channel Transmit
Level Relative to Primary Channel
-6
-10
-14
-18
dB
dB
dB
dB
SOlS
Scrambler Disable
0:7:5
When control bit SOlS is a one, the transmitter scrambler circuit is removed from the
data path.
SEPT
Short Echo
Protector Tone
0:7:0
When control bit SEPT is a one, the echo protector disable tone is 30 ms long rather
than 185 ms. (See TSB.)
TBA
Transmitter Buffer
Available
O:E:O
This status bit resets to zero when the host processor writes data to transmitter data
register O' O. When the transmitter empties register 0: 0, this bit sets to a one.
TIA
Transmitter Interrupt Active
0:E:7
This status bit is a one whenever the transmitter is driving IRQ to a zero.
TIE
Transmitter Interrupt Enable
0:E:2
When the host processor writes a one in control bit TIE, the IRQ line of the hardware
interface is driven to zero when status bit TBA is at a one.
TlVl
Transmitter level
Field
0:4:2-4
The transmitter analog output level is determined by eight TlVl codes, as follows:
TLVL
Transmitter Analog Output"
-1 dBm
0
-3 dBm
1
2
-5 dBm
-7 dBm
3
4
-9 dBm
-11 dBm
5
-13 dBm
6
-15 dBm
7
"Each step above is a 2 dB change ±0.2 dB.
±1
±1
±1
±1
±1
±1
±1
±1
dB
dB
dB
dB
dB
dB
dB
dB
TOO
Train-On-Data
1 :6:7
When control bit TOO is a one, it enables the train-an-data algorithm to converge the
equalizer if the signal quality degrades sufficiently. When TOO is a one, the modem still
recognizes a training sequence and enters the force train state. A BER of approximately
10 - 3 for 0.5 seconds Initiates train-an-data.
TPDM
Transmitter Parallel
Data Mode
0:7:2
When control bit TPDM is a one, the transmitter accepts data for transmission from the
transmitter data register (0: 0) rather than the serial hardware data input.
2-73
•
R96FT/SC
9600 bps Fast Train Modem
R96FT/SC Interface Memory Definitions (Continued)
Mnemonic
(None)
Name
Transmitter
Configuration
Memory
Location
0:6:0-7
Description
The host processor configures the transmitter by writing a control byte into the transmitter configuration register in its interface memory space. (See TSB.)
Transmitter Configuration Control Codes
Control codes for the modem transmitter configurations are:
Configuration
V27 biS/ter
V29
Configuration Code (Hex)
FT/2400
lC
lA
19
OA
09
4800
2400
4800
2400
14
12
11
22
21
02
01
FT/9600
FT/7200
FT/4800
FT/4800
9600
7200
4800
(None)
Transmitter Data
0:0:0-7
long
long
short
short
2400/4800 bps GearshiftIV.29 Scrambler
2400/4800 bps GearshiftlV.27 bis/ter Scrambler
61
41
V.21 Channel 2
See FSKT
Tone transmit
80
The host processor conveys output data to the transmitter in the parallel mode by
writing a data byte to the transmitter data register. The data is divided on baud boundaries, as follows:
Note: Data is transmitted bit zero first.
Bits
Configuration
V.29 9600 bps
7
1
6
5
14
3
1
2
Baud 1
1
1
1
0
Baud 0
V.29 7200 bps
Not Used
V.29 4800 bps
Baud 3
V.27 4800 bps
Not Used
V.27 2400 bps
Baud 3
Baud 2
1
Baud 1
1
Baud 0
2400 bps Gearshift
Baud 3
Baud 2
Baud 1
1
Baud 0
4800 bps Gearshift
Baud 1
Baud 1
Baud 2
Baud 1
1
Baud 1
Baud 0
Baud 0
1
Baud 0
Baud 0
TSB
Transmitter Setup
Bit
0:E:3
When the host processor changes the transmitter configuration, the SEPT bit or the
FSKT bit, the host must write a one In this control bit. TSB goes to a zero when the
change becomes effective. Worst case setup time is 2 baud + turnoff sequence +
training (If applicable).
TTDIS
Transmitter Train
Disable
0:7:6
When control bit TTDIS is a one, the transmitter does not generate a training sequence
at the start of transmission. With training disabled, RTS/CTS delay is less than two
baud times.
XCEN
External Clock
Enable
0:7:1
When control bit XCEN is a one, the transmitter timing is established by the external
clock supplied at the hardware mput XTCLK, pin 22A.
2-74
9600 bps Fast Train Modem
R96FT/SC
POR can be connected to a user supplied power-on-reset signal
in a wire-or configuration. A low active pulse of 3 ,.sec or more
applied to the POR pin causes the modem to reset. The modem
is ready to be configured 10 msec after POR is removed.
The following is a list of the configurations that may be used
with the forward channel and the states of the various control
bits.
Transmitter Control
Configuration
PCF
0:9:5
CF
0:9:3
PERFORMANCE
Receiver
Control
Whether functioning in V.27, V.29 or the proprietary fast train
configurations, the R96FT/SC provides the user with high
performance.
SCEN
1 :7:2
1
FTN.29/9600
1
FTN.29mOO
1
1
1
FTN.29/4800
1
X
FTN.27/4BOO
0
FTN.27/2400
0
X
"V.27/4BOO
0
X
"V.27/2400
0
X
V.21 FSK
X
X
"Both V.27 lon9 and short Irain may be used. X= Don'l
1
1
1
1
1
1
1
1
care.
POLLING SUCCESS
In the 9600 bps fast train configuration the modem approaches
a 98% success rate over unconditioned 3002 lines for a signalte-noise ratio of 26 dB, with a received signal level of - 20 dBm.
When used in conjunction with the 75 bps forward channel,
9600 bps main channel polling performance degrades by
approximately 2 dB.
BIT ERROR RATES
Note that CCITT V.29 and Gearshift configurations cannot be
used with the forward channel.
The Bit Error Rate (BER) performance of the modem is specified for a test configuration conforming to that specified in CCITT
Recommendation V.56, except with regard to the placement of
the filter used to bandlimit the white noise source. Bit error rates
are measured at a received line signal level of - 20 dBm as
illustrated.
POWER·ON INITIALIZATION
The BER curves shown were prepared from data obtained using
a TAS 1010 test system.
When power is applied to the R96FT/SC, a period of 50 to
350 ms is required for power supply settling. The power-on-reset
signal (POR) remains low during this period. Approximately
10 ms after the low to high transition of POR, the modem is ready
to be configured, and RTS may be activated. If the 5 Vdc power
supply drops below 3.5 Vdc for more than 30 msec, the POR
cycle is generated.
PHASE JITTER
At 2400 bps, the modem exhibits a bit error rate of 10- 8 or less
with a signal-te-noise ratio of 12.5 dB in the presence of 15 0
peak-te-peak phase jitter at 150 Hz, or with a signal-te-noise ratio
of 15 dB in the presence of 30° peak-te-peak phase jitter at
120 Hz (scrambler inserted).
At 4800 bps (V.27 bislter), the modem exhibits a bit error rate
of 10- 8 or less with a signal-te-noise ratio of 19 dB in the
presence of 15° peak-to-peak phase jitter at 60 Hz.
At POR time the modem defaults to the following configuration:
fast train, V.29, 9600 bps, no echo protector tone, 1700 Hz carrier frequency, scrambled ones segment disabled, serial data
mode, internal clock, cable equalizers disabled, transmitter
digital delay equalizer disabled, link amplitude equalizer disabled, link delay equalizer disabled, transmitter output level set
to -1 dBm ± 1 dB, interrupts disabled, receiver threshold set
to - 43 dBm, and train-on-data enabled.
At 9600 bps, the modem exhibits a bit error rate of 10- 8 or less
with a signal-te-noise ratio of 23 dB in the presence of 10° peakte-peak phase jitter at 60 Hz. The modem exhibits a bit error
rate of 10- 5 or less with a signal-to-noise ratio of 23 dB in the
presence of 20 0 peak-te-peak phase jitter at 30 Hz.
2-75
•
R96FT/SC
9600 bps Fast Train Modem
An example of the SER performance capabilities
following diagrams:
IS
given in the
4800 BPS
V.27
240014800 BPS
AND
7200 BPS GEARSHIFT
V.29
9600 BPS
300 BPS 2400 BPS 4800 BPS
V.29
V.21
V.27
V.29
l
10- 3
10- 3
I I
300 BPS
V.21
'"
V
10-'
2400/480 o BPS
GEARS HIFT
AND
4800 BPS
7200 BPS
V.29
V.29
9600 BPS
2400 BPS ""4800 BPS
V.27
V.27
V.29
/
1
I
10-'
L&I
L&I
~
~
~
-
HOST
PROCESSOR
(DTE)
....
....
ADDRESS BUS (5)
[1
DECODER
1....-
rl
CS(3)
t-'
Jl",AyA...
POR
RD
-
...
}
TELEPHONE
LINE
..£
RSI
TBCLK
CSI
RBCLK
IRQ
+5
r-r
J
OHRC
WRITE
DATA BUS (8)
LINE
INTERFACE
TMXCLK
ANCILLARY
CIRCUIT
INTERFACE
:c::
w
w
~
~
~
J
.r1i)
-
&
+5V
'a
+12V
-12V
AGND
POWER
SUPPLY
en
c
"
;-
DGND
C
C
'a
~
i:
oQ.
CD
Figure 1.
3
R144DP Functional Interconnect Diagram
I
R144DP
V.33 14.4 kbps Full-Duplex Modem
Table 3. R144DP Hardware Interface Signals
Name
'l\tpe'
DIN'
Pin No.
DIP'
Pin No.
Description
Name
A. OVERHEAD:
Ground (A)
Ground (D)
AGND
DGND
PWR
+12V
-12V
POR
PWR
PWR
IAlOB
31C,32C
30,31
Analog Ground Return
3C,8C,
29,37,53 Digital Ground Return
5A,10A
19C,23C, 1,45,61
+5 Volt Supply
26C,30C
15A
32
+ 12 Volt Supply
12A
-12 Volt Supply
36
Power-On-Reset
13C
2
RDCLK
TDCLK
XTCLK
RTS
Description
IAlOB
IAlOB
IAlOB
IAlOB
IAlOB
IAlOB
IAlOB
IAlOB
lC
lA
2C
2A
3A
4C
4A
5C
3
4
5
6
7
8
9
10
RS4
RS3
RS2
RSl
RSO
IA
IA
IA
IA
IA
8A
6C
8A
7C
7A
15
16
17
18
19
CSO
IA
10C
20
CSl
IA
9C
21
CS2
IA
9A
13
IA
IA
OC
12C
l1A
llC
14
12
11
},.
TXD
RXD
RLSD
OA
OA
IA
IA
OA
IA
OA
OA
21A
23A
22A
25A
25C
24C
22C
24A
23
46
51
50
49
48
26
Ai
OA
16A
25
Receive Data Clock
Transmit Data Clock
External Transmit Clock
Req uest-to-Send
Clear-ta-Send
Transmitter Data
Receiver Data
Received Line Signal
Detector
Ring Indicator
26A
27C
18C
22
47
43
Receiver Baud Clock
Transmitter Baud Clock
Transmitter M ux Clock
31A
32A
29A
27A
34
Transmitter Analog Output
Receiver Analog Input
Off-Hook Relay Control
Ring Detect
15C
14A
14C
13A
56
55
57
58
CTS
B. MICROPROCESSOR INTERFACE:
READ
WRITE
IRQ
DIP'
Pin No.
C. V.24 INTERFACE:
+5V
D7
D6
D5
D4
D3
D2
Dl
DO
DIN'
Type' Pin No.
27
D. ANCILLARY CIRCUITS:
RBCLK
TBCLK
TMXCLK
,"'''"'''
E. LINE INTERFACE:
TXA
RXA
OHRC
RD
}~-~~
AA
AB
00
IA
33
35
24
F. DIAGNOSTIC:
(5 Bits)
EYEX
EYEY
EYECLK
EYESYNC
Chip Select
Transmitter Device
Chip Select Receiver
Sample Rate Device
Chip Select Receiver
Baud Rate Device
Read Enable
Write Enable
Interrupt Request
Table 4.
OA
OA
OA
OA
OA
OA
OA
Eye Pattern Data-X Axis
Eye Pattern Data-Y Axis
Eye Pattern Clock
Eye Pattern Synchronizing
Signal
Notes:
1. Refer to Table 4 for digital circuit interface characteristics and Table 7
for analog circuit interface characteristics.
2. The following DIN pins should be left open: 17A, 17C, 18A, 20A, 20C,
28A, 28C and 30A.
3. The following DIP pins should be left open: 28, 39, 41, 44, 52, 59 and 60.
4. The following DIN pins are not used but should be connected to DGND
through individual 10 K!l series resistors: 16C, 19A, 21C and 29C.
5. The following DIP pins are not used but should be connected to DGND
through individual 10 K!l series resistors: 38, 40, 42 and 54.
6. Unused inputs tied to + 5V or ground require individual 10 K!l series
resistors.
Digital Interface Characteristics
Input/Output Type
Symbol
V IH
Parameter
Units
IA
OA
OB
OC
00
0.4 Max. 2
5.0 Max.
0.75 Typ.2
1.6 Max.
O'
15.0 Max.s
100
Open-Drain
Open-Drain
V il
Input Voltage, High
Input Voltage, Low
V
V
VOH
Output Voltage, High
V
3.5 Min.'
Val
liN
IOH
Output Voltage, Low
Input Current, Leakage
V
0.4 Max. 2
3.5 Min.'
0.4 Max. 3
Output Current, High
mA
-0.1 Max.
-0.1 Max
IOl
Il
Cl
Output Current, Low
Output Current, Leakage
mA
1.6 Max.
0.8 Max.
±10 Max.
±10 Max.
Capacitive Load
pF
Co
Capacitive Drive
pF
Circuit Type
Notes
1. I Load = -100 p.A
2. I Load = 1.6 mA
p.A
2.0 Min.
0.8 Max.
±2.5 Max.
p.A
5
TTL
3. I Load = 0.8 mA
4. p.A leakage
100
100
TTL 3-state
TTL 3-state
5. Can drive a + 5V relay with coil resistance greater than 360!l.
2-82
R144DP
V.33 14.4 kbps Full-Duplex Modem
Data Lines (00-07)
The DSP IRQ output structure is an open-drain field-effecttransistor (FET). Each of the individual DSP IRQ output lines is
wire-ORed to form the modem IRQ output signal. The modem
IRQ output can also be wire-ORed with other IRQ lines in the
application system. Any ofthese sources can drive the host interrupt input low, and the host interrupt servicing process normally
continues until all interrupt requests have been serviced (i.e., all
IRQ lines have returned high).
Eight bidirectional data lines (DO-D7) provide parallel transfer of
data between the host and the modem. The most significant bit
is D7. Data direction is controlled by the Read Enable and Write
Enable signals.
Chip Selects (CSO-CS2) and Register Selects
(RSO-RS4)
Because of the open-drain structure of IRQ, an external pull-up
resistor to + 5V is required at some point on the IRQ line. The
resistor value should be small enough to pull the IRQ line high
when all IRQ drivers are off (i.e., it must overcome the leakage
currents). The resistor value should be large enough to limit the
driver sink current to a level acceptable to each driver. If only the
modem IRQ output is used, a resistor value of 5.SK ohms ± 20%,
0.25W, is sufficient.
The three active low chip select lines (CSO-CS2) select one of
three modem digital signal processor (DSP) devices. The five
active high register select lines (RSO-RS4) address interface
memory registers within the selected DSP interface memory. All
eight of these lines are typically connected to the host bus address
lines; the register select lines to the five least significant lines
(AO-A4) and the chip select lines to the next two significant lines
(AS-AS) through a decoder.
V_24 INTERFACE
The selected DSP decodes RSO through RS4 to address one of
32 internal interface memory registers (00-1 F). The most significant address bit is RS4 while the least significant address bit is
RSO. The selected register can be read from or written into via the
8-bit parallel data bus (DO-D7).
Nine pins provide timing, data, and control signals for implementing a CCITT Recommendation V.24 compatible serial interface.
These signals are TTL compatible in order to drive the short wire
lengths and circuits normally found within stand-alone modem
enclosures or equipment cabinets. For driving longer cables,
these signals can be easily converted to RS-232-C voltage levels
using 1489 receivers and 1488 drivers, or their equivalents.
Read Enable (READ) and Write Enable (WRITE)
During a read cycle, data from the selected DSP interface memory
register is gated onto the data bus by means of three-state drivers
in each DSP. These drivers force the data lines high for a one bit,
or low for a zero bit. When not being read, the three-state drivers
assume their high-impedance (off) state.
Transmitted Data (TXD)
The modem obtains serial data to be transmitted from the local
DTE on the Transmitted Data (TXD) input.
During a write cycle, data from the data bus is copied into the
selected DSP interface memory register, with high and low bus
levels representing one and zero bit states, respectively.
Received Data (RXD)
The modem presents received serial data to the local DTE on the
Received Data (RXD) output.
The read/write cycle timing waveforms are illustrated in Figure 2
and the timing requirements are specified in Table 5.
Request To Send (RTS)
Table 5_
Microprocessor Interface Timing Parameters
Parameter
Symbol
Min.
Max.
Units
CSi Setup Time
RSi Setup Time
Data Access Time
Data Hold Time
Control Hold Time
Write Data Setup Time
Write Data Hold Time
TCS
TRS
TDA
TDHR
THC
TWDS
TDHW
0
25
-
ns
ns
ns
ns
ns
ns
ns
-
10
10
20
10
-
75
-
Activating Request to Send (RTS) causes the modem to transmit data on TXD when CTS becomes active. The RTS pin is
logically ORed with the RTS bit.
Clear To Send (CTS)
Clear to Send (CTS) active indicates to the local DTE that
the modem will transmit any data present on TXD. CTS response
times from an active condition of RTS are shown in
Table 2.
Received Line Signal Detector (RLSD)
Interrupt Request (IRQ)
Received Line Signal Detector (RLSD) active indicates to the local
DTE that energy above the receive level threshold is present on
the receiver input, and that energy is not a training sequence.
The modem Interrupt Request (IRQ) output may be connected to
the host processor interrupt request input in order to interrupt host
program execution for immediate modem service. The IRQ output can be enabled in the DSP interface memory to indicate
immediate change of conditions in any of the three modem DSP
devices. The use of IRQ is optional depending upon modem
application. Refer to the Software Considerations Section for a
summary of the modem interrupt bits, interrupt conditions and
interrupt clearing procedures.
For V.33, V.29 and V.27 bislter, RLSD goes active at the end of
the training sequence. If energy is above threshold and training
is not detected, the RLSD off-to-on response time is 15 ± 10 ms.
The RLSD on-to-off time is 40 ± 10 ms for V.33, 30 ± 9 ms for
V.29, or 10 ± 5 ms for V.27. The RLSD on-to-off time ensures that
all valid data bits have appeared on RXD.
2-83
•
V.33 14.4 kbps Full-Duplex Modem
R144DP
WRITE
READ
CSI
(1 .. 0-2)
Tes
Tes
RSI
(1=0-4)
TDHR
DI
(1=0-7)
Figure 2.
Microprocessor Interface Timing Waveforms
Receive Data Clock (RDCLK)
One of four RLSD receive level threshold options can be selected
(Table 6). A minimum hysteresis action of 2 dB exists between the
actual off-to-on and on-to-off transition levels. The threshold level
and hysteresis action are measured with a modulated signal
applied to the Receiver Analog (AXA) input. Note that performance
may be degraded when the received signal level is less than
- 43 dBm. The RLSD on and off thresholds are host programmable in DSP RAM.
The modem outputs a synchronous Receive Data Clock (RDCLK)
for USRT timing. The RDCLK frequency is the data rate (± 0.01 %)
with a duty cycle of 50 ± 1%. The RDCLK low·to·high transitions
coincide with the center of the received data bits. The timing
recovery circuit can track a ± 0.01% frequency error in the
associated transmit timing source.
Ring Indicator (RI)
Table 6. RLSO On and OFF Thresholds
The Ring Indicator (RI) output follows the ringing Signal present
on the line with a low level (OV) during the ON time, and a high
level ( + 5V) during the OFF time coincident with the ringing signal.
Receive Level
Option
RLSDOn
RLSDOff
0
1
2
3
> -43dBm
>-33dBm
>-26dBm
> -16dBm
<-48dBm
< -38dBm
< -31 dBm
< -21 dBm
The RI status bit in chip 2 reflects the state of the Ai output.
ANCILLARY SIGNALS
Transmitter Baud Clock (TBCLK) and
Receiver Baud Clock (RBCLK)
Transmit Data Clock (TDCLK)
Transmitter Baud Clock (TBCLK) and Receiver Baud Clock
(RBCLK) outputs have no counterpart in the V.24 or RS·232·C
recommendations since they mark the baud interval rather than
the data rate for the transm itter and receiver, respectively. These
baud clocks are useful in identifying the order of data bits in a baud
(e.g., for multiplexing data). Both signals are active high. The first
bit in each baud begins with the falling edge of the corresponding baud clock.
The modem outputs a synchronous Transmit Data Clock (TDCLK)
for USRT timing. The TDCLK frequency is the data rate (± 0.01%)
with a duty cycle of 50 ± 1%.
Transmit Data (TXD) must be stable during the one /LS periods
immediately preceding the rising edge of TDCLK and following
the rising edge of TDCLK. The TDCLK source can be internal,
external (input on XTCLK) or slave (to RDCLK) as selected by
bits in the transmitter interface memory.
Transmitter Multiplexer Clock (TMXCLK)
External Transmit Clock (XTCLK)
The Transmitter Multiplexer Clock (TMXCLK) output is a 288 kHz
clock which is internally divided down to create the Transmitter
Baud Clock (TBCLK). TMXCLK is also a common multiple of all
the possible transmitter data clocks. The high-to-Iow transitions
of TDCLK coincide with the high-to-Iow transitions of TMXCLK.
In synchronous communication, an external transmit data clock
can be connected to the modem XTCLK input. The clock supplied
at XTCLK must exhibit the sme characteristics of TDCl.,K. The
XTCLK input is then reflect~d at the TDCLK output.
2-84
R144DP
V.33 14.4 kbps Full-Duplex Modem
LINE INTERFACE
II
The Transmitter Analog (TXA) output and Receiver Analog (RXA)
input allow modem connection to either a leased line or the public switched telephone network (PSTN) through an audio transformer or a data access arrangement. The analog signal characteristics of TXA and RXA are described in Table 7.
Table 7. Analog Interface Characteristics
Name 'l\'pe
Characteristics
TXA AA The transmitter output impedance is 604 ohms ± 1%.
RXA
L
EYESYNC
EYEX,~~
EYEY~~
MSB
AB The receiver input impedance is 66.5K ohms.
Figure 3.
Transmitter Analog (TXA)
The Transmitter Analog (TXA) output can drive an audio transformer or data access arrangement. TXA is a low impedance
amplifier output in series with an internal 604 ohm ± 1% resistor
to match a standard telephone load of 600 ohms.
LSB
Eye Pattern Timing
EYECLK
EYECLK is a clock for use by the serial-to-parallel converters. The
EYECLK output is a 288 kHz clock which is internally divided down
to create the Receiver Baud Clock (RBCLK). EYECLK is also a
common multiple of all the possible receiver data clocks. The lowto-high transitions of RDCLK coincide with the low-ta-high
transitions of EYECLK.
Receiver Analog (RXA)
The Receiver Analog (RXA) input can originate from an audio transformer or data access arrangement. The input impedance is nominally 66.5K ohms. The RXA input must be shunted by an external
604 ohm ±1% resistor in order match a 600 ohm source.
EYESYNC
Transient protection forTXA and RXA is recommended when interfaCing directly to a transformer. This protection may take the form
of back-to-back zener diodes or a varistor across the transformer.
EYESYNC is a strobe for loading the D/A converters.
SOFTWARE INTERFACE
Ring Detect (RD)
Modem functions are implemented in firmware executing in
three DSPs: transmitter device, receiver sample rate device, and
receiver baud rate device.
The Ring Detect (RD) input is monitored for pulses in the range
of 15 Hz to 68 Hz. The frequency detection range may be changed
by the host in DSP RAM. The circuit driving RD should be a
4N35 optoisolator or equivalent. The circuit driving RD should not
respond to momentary bursts of ringing less than 125 ms in duration, or less than 40 VRMS (15 Hz to 68 Hz) across TIP and RING.
DATA2 bit must be set to a 0 to enable ring detection. Detected ring
signals are reflected on the Ai output.
INTERFACE MEMORY
Each DSP communicates with the host processor by means of a
dual-port, interface memory. The interface memory in each DSP
contains thirty-two B-bit registers, labeled register 00 through 1F.
Each register can be read from, or written into, by both the host and
the DSP. The host communicates with the DSP interface memory
via the microprocessor bus shared between the three DSPs.
The host can control modem operation by writing control bits to DSP
interface memory and writing parameter values to DSP RAM
through the interface memory. The host can monitor modem operation by reading status bits from DSP interface memory and reading parameter values from DSP RAM through interface memory.
Off-Hook Relay Control (OHRC)
OHRC Is an output designed to directly drive a + 5V relay coil with
a worst case resistance of 360 ohm having a must operate voltage
of 4.0 Vdc. A clamp diode is integrated in the modem which
eliminates the need for the diode across the relay coil. An external
transistor can be used to drive heavier loads (e.g., electromechanical relays). OHRC is controlled by the host by setting
the RA bit in the interface memory.
INTERFACE MEMORY MAPS
Memory maps of the 96 addressable registers in the modem transmitter (chip 0), receiver sample rate (chip 1), and receiver baud rate
(chip 2) devices are shown in Figure 4. These B-bit registers may
be read or written during any host read or write cycle. In order to
operate on a single bit or a group of bits in a register, the host processor must read a register then mask out unwanted data. When writing a Single bit or group of bits in a register, the host processor must
perform a read-modify-write operation. That is, read the entire
register, set or reset the necessary bits without altering the other
register bits, then write the unaffected and modified bits back into
the interface memory.
DIAGNOSTIC SIGNALS
Four signals provide the timing and data necessary to create an
oscilloscope quadrature eye pattern. The eye pattern is simply a
display ofthe received baseband constellation. By observing this
constellation, common line disturbances can usually be identified.
Timing of these signals is illustrated in Figure 3.
EYEX and EYEY
The EYEX and EYEY outputs provide two serial bit streams containing data for display on the oscilloscope X axis and Y axis,
respectively. This serial digital data must first be, converted to
parallel digital form by two serial-to-parallel converters and then
to analog form by two digital-to-analog (D/A) converters.
INTERFACE MEMORY BIT DEFINITIONS
Table 8 defines the individual bits in the interface memory. In the
Table 8 descriptions, bits in the interface memory are referred to
using the format Y:Z:Q. The chip number is specified by Y (0,1 or 2),
the register number by Z (00 through 1F), and the bit number by
Q (0 through 7, 0 = LSB).
EYEX and EYEY outputs are 15-bit words, each with B-bits of significance. The 15-bit data words are shifted out most significant
bit first with the seven most significant bits equal to zero. EYEX
and EYEY are clocked by the rising edge of EYECLK.
2-85
•
R144DP
V.33 14.4 kbps Full-Duplex Modem
R144DP DSP Interface Memory (Chip 0)
i~t
Register
IF
IE
10
IC
IB
lA
19
18
17
16
15
14
13
12
11
10
OF
OE
OD
OC
OB
OA
09
08
07
06
05
04
03
02
01
7
6
5
NSIAO NCIAO
DBIAO
XACCO
-
-
-
-
-
-
CTS
-
-
YACCO
-
-
-
-
-
-
-
-
-
00
-
0
-
-
-
--
-
-
-
-
-
-
--
-
CEQ
-
-
RTRN
RA
RTS
MHLD
-
TXCLK
DTMF
TPDM
-
I
2
TLVL
--
--
3
-
-
-
4
NSIEO NEWSO NCIEO
NEWCO
DBIEO
DBAO
XCRDO XWTO XCRO
X RAM ADDRESS XADDO
YCRDO YWTO YCRO
Y RAM ADDRESS YADDO
X RAM DATA MSB XDAMO
X RAM DATA LSB XDALO
Y RAM DATA MSB YDAMO
Y RAM DATA LSB YDALO
L2ACT
-
TCONF
-
-
-
L3ACT L4ACT
-
TXSQ
-
-
-
-
-
TIDIS
-
ARCO SDIS
SHAPO CF330
TSPY
TBUFFERlTSPX
( ) Indicates reserved for modem use only.
-
-
TSPA
-
SEPT
-
EPT
R144DP Interface Memory (Chip 2)
R144DP DSP Interface Memory (Chip 1)
~
Register
IF ~
IE
10
lC
18
lA
19
18
17
16
15
14
13
12
II
10
OF
OE
7
6
NSIAI
NCIAI
DBIAI
XACCI
YACCI
5
-
-
-
-
FED
-
-
OB
OA
09
08
07
06
05
04
03
02
01
TONEA TONEB TONEC
-
-
-
-
-
-
-
-
-
-
SPEED
DATAl
RTDIS
-
-
-
-
-
YACC2
09
08
-
-
-
-
RLSDE ARCI
SQDIS
SHAPI CF331
RSEQM
RBUFFER/RSEQL
(-) Indicates reserved for modem use only.
-
Figure 4.
-
06
05
04
03
02
01
00
-
3
-I
-
-
-
-
-
-
-
-
-
-
2
I
0
-
-
-
DBIE2
XCRD2
X RAM ADDRESS XADD2
Y RAM AD
X RAM
X RAM
YRAM
Y RAM DATA
YADD2
=00
XDAM2
XDAL2
YDAM2
YDAL2
-
XWT2
DBA2
XCR2
YWT2
YCR2
-
-
-
-
RI
-
-
-
-
-
-
-
-
DDIS
-
-
RSPA
EQFZ
EQRES EQT2
-
-
-
AMTD
-
-
DATA2
-
IFIX
-
RSPV
RSPX
(-) Indicates reserved for modem use only.
R144DP DSP Interface Memory Map
2-86
4
NSIE2 NEWS2
-
DBIA2
OA
-
07
-
5
-
~S
19
10
OF
OE
OD
OC
OB
RSEQ
6
-
XACC2
11
RLSD
-
-
RTH
7
NSIA2
Register
IF
IE
10
IA
19
18
17
16
15
14
13
12
RCONF
P2DET PNDET
-
~
0
-
-
-
1
2
3
NSIEI NEWSI NCIEI
NEWCI
DBIEI
DBAI
XCRDI XWTI XCRI
X RAM ADDRESS XADDI
YCRDI YWTI YCRI
Y RAM ADDRESS YADDI
X RAM DATA MSB XDAMI
X RAM DATA LSB XDAL1
Y RAM DATA MSB YDAMI
Y RAM DATA LSB YDALI
GO
OC
00
4
TOD
-
-
V.33 14.4 kbps Full-Duplex Modem
R144DP
Table 8.
Mnemonic
Memory
Location
R144DP Interface Memory BH Definitions
Default
Value
NamelDescriptlon
AMTD
2:2:5
1
Amplitude Modulation Tracker Disable. When control bit AMTD Is a 0, an adaptive amplitude
modulation lracker is enabled in the receiver; when a 1, the tracker is disabled, The tracker operates
only in V.33 configurations.
ARCO
0:3:3
1
Automatic Rate Change Enable Chip O. In V.33 configurations, control bit ARCO controls the
transmit data rate. When ARCO is a 1, the transmitter automatically conditions itself to transmit data
at the highest common data rate according to the received, rate sequence. When ARCO is a 0, the
host must check the rate sequence in registers RSEQM and RSEQL and sat the transmitter
configuration accordingly (see RSEQ). ARCO must be 0 for the transmitter to operate in the
proprietary TCM 9600 or TCM 7200 modes.
ARCl
1:3:3
1
Automatic Rate Change Enable Chip 1. In V.33 configurations, control bit ARCl controls the receive
data rate. When ARCl Is a 1, the receiver automatically conditions itself to receive data at the highest
common data rate according to the received rate sequence. When ARCl Is a 0, the host must check the
rate sequence in registers RSEQM and RSEQL and sat the receiver conflQuration accordingly (see RSEQ).
ARCl must be 0 for the receiver to operate in the proprietary TCM 9600 or TCM 7200 modes.
CEQ
0:5:3
1
Compromise Equalizer Enable. When control bit CEQ is a I, the transmitter's digital compromise
equalizer is inserted into the transmit path. This bandpass equalizer has host programmable taps in
DSP RAM. CEQ should be a 0 during local analog loopback.
CF330
0:2:2
0
Carrier Frequency V.33 Chip O. When control bit CF330 is a 1, the transmitter carrier frequency in V.33
configurations is 1700 Hz. When CF330 Is a 0, the carrier frequency in V.33 configurations is 1800 Hz.
The undefined bits in the rate sequence can be modified in DSP RAM.
The non-standard 1700 Hz option is provided for use with a secondary channel which is added at the
high end of the band.
CF331
1:2:2
0
Carrier Frequency V.33 Chip 1. When control bit CF331 is a 1, the receiver carrier frequency in V.33
configurations is 1700 Hz. When CF331 is a 0, the carrier frequency in V.33 configurations is 1800 Hz.
The non-standard 1700 Hz option is provided for use with a secondary channel which is added at the
high end of the band.
CTS
0:F:5
-
DATAl
1:9:2
1
Data Chip 1. When control bit DATAl is a 0, the receiver is prevented from entering the training
state. The receiver remains in idle mode. Tone detectors A, Band C are all active. When DATAl Is a 1
the receiver responds normally. Tone datectors A and B are active but tone detector C Is disabled.
DATA2
2:9:2
1
Data Chip 2. When control bit DATA2 is a 0, the ringing detector is enabled, and when a I, the
ringing detector is disabled. This bit should be set to a 1 after the modem goes off-hook, otherwise
the Ai Signal and RI bit will give spurious outputs.
DBAO
O:lE:O
-
Data Buffer Available Chip O. When sat to a 1, status bit DBAO signifies that the transmitter has read
register 0:0 (TBUFFER), or registers 0: 1 (TSPY) and 0:0 (TSPX), and the host can write new data
into register 0:0, or registers 0: 1 and 0:0. This condition can also cause IRQ to be asserted. The
host writing to register 0: 0 resets the DBAO and DBIAO bits to O. (See DBIEO and DBIAO.)
DBAl
l:lE:O
-
Date Buffer Available Chip 1. When sat to a I, status bit DBAI signifies that the receiver wrote valid
data into register 1 : 0 (RBUFFER), or registers 1 : 1 (RSEQM) and 1 : 0 (RSEQL). This condition can
also cause IRQ to be asserted. The host reading register 1:0 resets the DBAI and DBIAI bits to O.
(See DBIEl and DBIA1.)
DBA2
2:1E:0
-
Date Buffer Available Chip 2. When sat to aI, status bit DBA2 Signifies that the receiver wrote valid
data into registers 2: 1 (RSPy) and 2:0 (RSPX). This condition can also cause IRQ to be asserted.
The host reading register 2: 0 resats the DBA2 and DBIA2 bits to o. (See DBIE2 and DBIA2.)
DBIAO
0:IE:6
-
Data Buffer Interrupt Active Chip O. When the transmitter data buller interrupt is enabled (DBIEO is
a 1) and register 0: 0 is empty (DBAO is sat to a 1), the transmitter asserts IRQ and sets status
bit DBIAO to a 1 to indicate that DBAO going to a 1 caused the interrupt. The host writing to register
0: 0 resets the DBIAO bit to a 0 and clears the Interrupt request due to DBAO. (See DBIEO and DBAO.)
DBIAI
1 :lE:6
-
Data Buffer Interrupt Active Chip 1. When the receiver chip 1 data buffer Interrupt Is enabled (DBIEl
is a I) and register I : 0 is written to by the DSP (DBAI is sat to a I), the receiver asserts iRa and sets
DBIAI to a 1 to indicate that DBA1 going to a I caused the interrupt. The host reading regisler 1 : 0
resets the DBIAI billo a 0 and clears the interrupt request due to DBA1. (See DBAl and DBIE1.)
Clear To Send. When set to a 1, status bit CTS indicates to the DTE that the training sequence has
been completed and any data present at TXD (serial mode) or in TBUFFER (parallel mode) will be
transmitted (see TPDM).
2-87
•
R144DP
V.33 14.4 kbps Full-Duplex Modem
Table 8.
Mnemonic
Memory
Location
R144DP Interface Memory Bit Definitions (Continued)
Default
Value
Name/Description
DBIA2
2:1E:6
-
Data Buffer Interrupt Active Chip 2. When the receiver chip 2 data buffer Interrupt is enabled (DBIE2
is a 1) and register 2:0 is written to by the DSP (DBA2 is sello a I), the receiver asserts iRQ and sets
DBIA2 to a 1 to indicate that DBA2 going to a 1 caused the interrupt. The host reading register 2: 0
resets the DBIA2 bit to a 0 and clears the interrupt request due to DBA2. (See DBA2 and DBIE2.)
DBIEO
0:IE:2
0
Data Buffer Interrupt Enable Chip O. When control bit DBIEO is a 1 (interrupt enabled), the
transmitter will assert IRQ and set the DBIAO bit to a 1 when DBAO is set to 1 by the DSP. When
DBIEo is a 0 (interrupt disabled), DBAO has no effect on IRQ or DBIAO. (See DBAO and DBIAO.)
DBIEI
1:IE:2
0
Data Buffer Interrupt Enable Chip 1. When control bit DBIEI is a 1 (interrupt enabled), the receiver
will assert IRQ and set the DBIA 1 billo a 1 when DBA1 is sello a 1 by the DSP. When
DBIEI is a 0 (interrupt disabled), DBAI has no effect on IRQ or DBIAI. (See DBAI and DBIA1.)
DBIE2
2:1E:2
0
Data Buffer Interrupt Enable Chip 2. When control bit DBIE2 is a 1 (interrupt enabled), the receiver
will assert IRQ and set the DBIA2 bit to a 1 when DBA2 is set to a 1 by the DSP. When DBiE2 is a 0
(interrupt disabled), DBA2 has no effect on IRQ or DBIA2. (See DBA2 and DBIA2.)
DDIS
2:8:4
0
Descrambler Disable. When control bit DDIS is a I, the receiver's descrambler circuit is disabled;
when a 0, the descrambler circuit is enabled.
DTMF
0:9:5
0
DTMF Select. When the modem is configured for dialing mode, the modem will dial using DTMF
tones or pulses. When control bit DTMF is a I, the modem will dial using DTMF tones. When DTMF is
a 0, the modem will dial using pulses. The DTMF bit can be changed during the dialing process to
allow either tone or pulse dialing of consecutive digits. Dialing mode is selected by configuration
code 81 in the Transmitter Configuration Register (TCONF). When in dialing mode, the data placed in
the Transmitter Data Register is treated as digits to be dialed. The number to be dialed must be
represented by two hexadecimal digits (e.g., if a 9 is to be dialed, then a 09 must be written to the
Transmitter Data Register). Also, see DBAO bit.
Dialing timing and power levels are host programmable in DSP RAM (Table 11).
EPT
0:2:0
0
Echo Protector Tone Enable. When control bit EPT is a I, an unmodulated carrier is transmitted for
185 ms (SEPT bit = 0) or 30 ms (SEPT bit = 1) followed by 20 ms of no transmitted energy prior to
the transmission of the training sequence. When EPT is a 0, neither the echo protector tone nor the
20 ms of no energy are transmitted prior to the transmission of the training sequence.
The echo protector tone is typically used in V.27 and V.29 over dial-up lines. The tone is sent prior to
the training sequence to ensure that the echo suppressors are pointing in the correct direction.
EQFZ
2:4:3
0
Equalizer Freeze. When control bit EQFZ is a I, updating of the receiver's adaptive equalizer taps is
inhibited.
EQRES
2:4:7
0
Equalizer Reset. When control bit EQRES is a I, the receiver sets all of the adaptive equalizer's taps
to zero. When EQRES is a 0, the equalizer taps are updated normally by the receiver.
Setting EQRES to a 1 effectively clamps the receiver. EQRES along with RLSDE can be used to
clamp the receiver off and turn off the RLSD pin. An equalizer reset is automatically done for a brief
period of time at the beginning of the train-on-data state (TOD = 1). Therefore, the host does not have
to manually set then clear this bit to reset the equalizer for line hits, etc., when TOD is active.
EQT2
2:4:6
0
Equalizer T/2 Spacing Select. When control bit EQT2 is a I, the receiver's adaptive equalizer is T/2
fractionally spaced. V{hen EQT2 is a 0, the equalizer is T spaced (T = 1 baud time).
FED
1 :F:6
-
Fast Energy Detector. When status bit FED is a I, energy in the passband above the selected
receiver threshold has been detected (see RTH).
IFIX
2:4:2
1
Eye Fix. When control bit IFIX is a I, the serial diagnostic data at the EYEX and EYEY pins reflects
the Rotated Equalizer Output. When IFIX is a 0, the data on EYEX and EYEY is selected by the
addresses in X RAM Address and Y RAM Address registers, respectively.
L2ACT
0:7:5
0
Loop 2 Activate. When control bit L2ACT is a I, the receiver's digital output is connected to the
transmitter's digital input (locally activated remote digitalloopback) in accordance with CCITI
Recommendation V.54.
L3ACT
0:7.3
0
Loop 3 Activate. When control bit L3ACT is a I, the transmitter's analog output is coupled to the
receiver's analog input through an attenuator (local analog loopback) in accordance with CCITT
Recommendation V.54. The modem can be placed in loop 3 in either idle or data mode. If loop 3 is
initiated in data mode, the connection to the other modem is terminated.
The transmitter's compromise equalizer should be disabled, by setting CEQ to a 0, during local
analog loopback.
L4ACT
0:7:2
0
Loop 4 Activate. When control bit L4ACT is a I, the receiver's analog input is connected to the
transmitter's analog output (remote analog loopback) in a manner Similar to CCITI Recommendation V.54.
MHLD
0:7:0
0
Mark Hold. When control bit MHLD is a I, the transmitter's digital input data is clamped to a mark.
When MHLD is a 0, the transmitter's input is taken from TXD or TBUFFER (see TPDM).
2-88
R144DP
V.33 14.4 kbps Full-Duplex Modem
Table 8. R144DP Interface Memory Bit Definitions (Continued)
Mnemonic
Memory
Location
Default
Value
Name/Description
NCIAO
O:lF:6
-
NCIAI
1: IF:6
-
NCIEO
O:IF:2
0
NEWCO Interrupt Enable. When control bit NCIEO is a 1 (interrupt enabled), the transmitter will
assert IRQ and set NCIAO to a 1 when the NEWCO bit is reset to a 0 by the DSP. When NCIEO IS a 0
(interrupt disabled), NEWCO has no effect on IRQ or NCIAO. (See NEWCO and NCIAO.)
NCIE1
1: IF:2
0
NEWCl Interrupt Enable. When control bit NCIEI is a 1 (interrupt enabled), the receiver Will assert
IRQ and set NSIAI to a 1 when the NEWCl bit is reset to a 0 by the DSP. When NCIEI is a 0
(interrupt disabled), NEWCl has no effect on IRQ or NCIA 1. (See NEWCl and NCIA 1.)
NEWCO
O:lF:O
0
New Configuration Chip O. Control bit NEWCO must be set to a 1 by the host after the host changes
the configuration code in TCONF (0: 12) or the SHAPO bit (0:2:3). This informs the transmitter to
implement the new transmitter configuration. The DSP resets the NEWCO bit to a 0 when the
configuration change is implemented. A configuration change can also cause IRQ to be asserted.
(See NCIEO and NCIAO.)
NEWCl
1: IF:O
0
New Configuration Chip 1. Control bit NEWCl must be set to a 1 by the host after the host changes
the configuration code in RCONF (1 : 12), the SHAPI bit (1 :2:3), or RTH (1 : 13: 2·3). This informs the
receiver to implement the new receiver configuration and/or the new receiver threshold. The DSP
resets the NEWCl bit to a 0 when the change is implemented. A configuration/receiver threshold
change can also cause IRQ to be asserted. (See NCIEI and NCIA1.)
NEWSO
O:lF:3
-
New Status Chip O. When set to ai, status bit NEWSO Indicates that one or more status bits located
in registers OA to OF have changed state, or a DSP RAM read or write has been completed, In the
transmitter. This bit can be reset to a 0 only by the host. The host may mask the effect of indiVidual
status bits upon NEWSO by writing a mask value to DSP RAM. A change of status can also cause
IRQ to be asserted. (See NSIEO and NSIAO.)
NEWSI
1: 1F:3
-
NEWS2
2:1F:3
-
NSiAO
O:IF:7
-
NSIAI
1 :IF:7
-
NSIA2
2:1F:7
-
NEWS2 Interrupt Active Chip 2. When the new status interrupt chip 2 is enabled (NSIE2 IS a 1)
and a change of status occurs (NEWS2 is set to a 1), the receiver asserts IRQ and sets status bit
NSIA2 to a 1 to indicate that NEWS2 going to a 1 caused the interrupt. NSIA2 and the interrupt
request due to NEWS2 are cleared when the host writes a 0 to NEWS2. (See NEWS2 and NSIE2.)
NSIEO
O:IF:4
0
NEWSO Interrupt Enable Chip O. When control bit NSIEO is a 1 (interrupt enabled), the transmitter
will assert IRQ and set NSIAO to a 1 when NEWSO is set to a 1 by the DSP. When NSIEO is a 0
(interrupt disabled), NEWSO has no effect on IRQ or NSIAO. (See NEWSO and NSIAO.)
NSIE1
1 :IF:4
0
NEWS1 Interrupt Enabla Chip 1. When control bit NSIEI is a 1 (interrupt enabled), the receiver Will
assert IRQ and set NSIAI to a 1 when NEWSI is set to a 1 by the DSP. When NSIEI is a 0 (Interrupt
disabled), NEWSI has no effect on IRQ or NSIAI. (See NEWSI and NSIA 1.)
NEWCO Interrupt Active. When the new configuration chip 0 interrupt is enabled (NCIEO is a 1) and
a new transmitter configuration is implemented (NEWCO is reset to a 0), the DSP asserts IRQ and
sets status bit NCIAO to a 1 to indicate that NEWCO going to a 0 caused the Interrupt. NCIAO and the
interrupt request due to NEWO are cleared by the host writing a 0 into NCIEO. (See NEWCO
and NCIEO.)
NEWCllnterrupt Active. When the new configuration chip 1 interrupt is enabled (NCIEI IS a 1) and
a new receiver configuration is implemented (NEWCl is reset to a 0), the DSP asserts IRQ and sets
status bit NCIA 1 to a 1 to indicate that NEWCl going to a 0 caused the interrupt. NCIA 1 and the
interrupt request due to NEWCl are cleared by the host writing a 0 into NCIEI. (See NEWCl
and NCIE1.)
New Status Chip 1. When set to ai, status bit NEWSI Indicates that one or more status bits located
in registers OA to OF have changed state, or a DSP RAM read or write has been completed, in
receiver DSP chip 1. This bit can be reset to a 0 only by the host. The host may mask the effect of
individual status bits upon NEWSI by writing a mask value to DSP RAM. A change of status can also
cause IRQ to be asserted. (See NSIEI and NSIA1.)
New Status Chip 2. When set to ai, status bit NEWS2 indicates that a DSP RAM read or wnte has
been completed in receiver DSP chip 2. This bit can be reset to a 0 only by the host. Complellon of a
RAM read or write cycle can also cause IRQ to be asserted. (See NSIE2 and NSIA2.)
NEWSO Interrupt Active Chip O. When the new status interrupt chip 0 is enabled (NSIEO is a 1) and
a change of status occurs (NEWSO is set to a 1), the transmitter asserts IRQ and sets status bit NSIAO
to a 1 to indicate that NEWSO going to a 1 caused the interrupt. NSIAO and the interrupt request due
to NEWSO are cleared when the host writes a 0 to NEWSO. (See NEWSO and NSIEO.)
NEWSI Interrupt Active Chip 1. When the new status interrupt chip 1 is enabled (NSIEI is a 1) and
a change a status occurs (NEWSI is set to a 1), the receiver asserts IRQ and sets status bit NSIAI to
a 1 to indicate that NEWSI going to a 1 caused the interrupt. NSIA1 and the interrupt request due to
NEWSI are cleared when the host writes a 0 to NEWS1. (See NEWSI and NSIE1.)
•
V.33 14.4 kbps Full-Duplex Modem
R144DP
Table 8.
Mnemonic
Memory
Location
R144DP Interface Memory Bit Definitions (Continued)
Default
Value
Name/Description
NSIE2
2:1F:4
0
NEWS2 Interrupt Enable Chip 2. When conlrol bit NSIE2 is a 1 (interrupt enabled), the receiver will
assert IRO and set NSIA2 to a 1 when NEWS2 is set to a 1 by the OSP. When NSIE2
is a 0 (interrupt disabled), NEWS2 has no effect on IRO or NSIA2. (See NEWS2 and NSIA2.)
P20ET
1 :0:7
-
P2 Sequence Detected. When status bit P20ET is a 1, the receiver is detecting the P2 portion of the
training sequence. When P20ET is a 0, P2 is not being detected.
PNOET
1 :0:6
-
PN Sequence Detected. When status bit PNOET is a 1, the receiver is detecting the PN portion of
the training sequence. When PNOET is a 0, PN is not being detected.
RA
0:7:1
0
Relay Activate. When control bit RA is a 1, the output OHRC is activated (low); when a 0, the OHRC
output is off (high).
RBUFFER
1 :0:0-7
-
RCONF
1: 12:0-7
31
Receive Buller. The host obtains channel data from the modem receiver in the parallel data mode by
reading a data byte from the RBUFFER. The data is divided on the baud boundaries shown under
TBUFFER. The RBUFFER reflects the received data when the RATE bit is a O.
Receiver Configuration. The RCONF control bits select one of the following receiver configurations:
Mode
Data Rate
RCONF(Hex)
V.33TCM
V.33TCM
TCM
TCM
V.29
V.29
V.29
V.27
V.27
V.27
V.27
14400
12000
9600
7200
9600
7200
4800
4800 Long
2400 Long
4800 Short
2400 Short
31
32
34
38
14
12
11
22
21
02
01
RI
2:F:3
Ring Indicator. When set to a 1, status bit RI indicates that a ringing signal is being detected.
Ringing is detected if pulses are present on the RO input in the 15 Hz-68 Hz frequency range. The
RI bit follows the ringing signal with a 1 during the ON time and a 0 during the OFF time coincident
with Ai output sIgnal. The decision bounds are host programmable in OSP RAM.
RLSO
1 :F:7
-
RLSOE
1 :3:4
1
RLSD Enable. When control bit RLSOE is a 1, the RLSO pin reflects the RLSO bit. When RLSOE is
a 0, the RLSO pin is clamped to a 1 (OFF condition) regardless of the state of the RLSO bit.
RSEO
l:C:O
0
Rate Sequence Received. When status bit RSEO is a 1, the 16·bit rate sequence included in the
CCITT V.33 start-up procedure has been received and the 16-bit rate sequence word is available in
RSEOM (1: 1) and RSEOL (1 :0). (V.33)
RSEOL
1 :0:0-7
-
RSEOM
1:1 :0-7
-
RSPA
2:4:4
1
RSPX
2:0:0-7
-
RSPY
2:1 :0-7
-
The bit is valid only when the receiver OATA2 bit (2:9:2) is an O.
Received Line Signal Detector. When status bit RLSO is a 1, the receiver has finished receiving the
training sequence or has turned on due to detected energy above threshold, and is receiving data.
RLSO is a 0 when the receiver is in the idle state and during the reception of a training sequence.
Rate Sequence LSB. When the RSEO bit is a 1, register 1 : 0 holds the least significant byte of the
16-bit V.33 rate sequence word (RSEOL) received by the modem. When the RSEO bit is a 0, register
1: 0 holds the received data (see RBUFFER). (V.33)
Rate Sequence MSB. When the RSEO bit is a 1, register 1 : 1 holds the most significant byte of the
16-bit V.33 rate sequence w.ord (RSEOM) received by the modem. When the RSEO bit is a 0, register
1: 1 is not used. (V.33)
Receiver Signal Point Activate. When control bit RSPA is a 1, the receiver writes the received signal
point coordinates, after the decision processing, into registers RSPY (2: 1) and RSPX (2: 0). When
RSPA is a 0, RSPY and RSPX do not contain the signal point coordinates.
Receiver Signal Point X. RSPX holds the X (in-phase) coordinate of the received Signal point. RSPX
is valid only when RSPA is a 1.
Receiver Signal Point Y. RSPY holds the Y (quadrature) coordinate of the received signal point.
RSPY is valid only when RSPA is a 1.
2-90
R144DP
V.33 14.4 kbps Full-Duplex Modem
Table 8.
Mnemonic
Memory
Location
R144DP Interface Memory Bit Definitions (Continued)
Default
Value
Name/Description
RTDIS
1 :8:2
o
Receiver Training Disable. When control bit RTDIS is aI, the receiver is prevented from recognizing
a training sequence and entering the traming state. When RTDIS IS a 0, receiver training is enabled.
RTH
1'13'2,3
o
Receiver Threshold. The RTH control bits select the receiver energy detector threshold according to
the following codes:
RTH
0
1
2
3
RTRN
0:8:1
o
RLSDON
-43dBm
-33dBm
-26dBm
-16 dBm
RLSDOFF
-48 dBm
-38 dBm
-31 dBm
-21 dBm
Retrain. When the modem IS in data mode, and control bit RTRN is set to aI, a retrain sequence is
initiated. RTRN resets to a 0 as soon as the initiation IS acknowledged.
Fall-back or fall-forward retrains may be accomplished in V.33 mode as follows:
Change the Tran~mitter Configuration Register (TCONF) to the required configuration code. Do not
set the NEWC bits In either the transmitter (NEWCO) or receiver chip 1 (NEWC1) and do not change
the receiver configuration register (RCONF) code. Ensure that ARCO and ARC 1 bits are set to a 1.
Finally, set the RTRN bit to a 1. If the remote modem can operate at the requested rate, the receiver
configuration will be changed by the modem to reflect the new rate after the retrain is completed. If
the remote modem cannot operate at the new rate, then no rate change will take place during the
retram and the transmitter configuration register Will automatically revert back to its original
configuration.
--
RTS
0:8:0
o
Request To Send. When control bit RTS IS aI, the modem transmits the training sequence before
activating CTS. The RTS bit is ORed with the RTS pin.
SOlS
0:3:2
o
Scrambler Disable. When control bit SOlS is aI, the transmitter scrambler circuit is disabled; when
a 0, the scrambler CirCUit IS enabled
SEPT
0:2:1
o
Short Echo Protector Tone. When control bit SEPT IS aI, the echo protector tone duration is 30 ms;
when a 0, the echo protector tone duration IS 185 ms.
SHAPO
0:2:3
o
Transmitter Shaping Filter Select. When control bit SHAPO is a 0, the transmit spectrum IS shaped
by a square root of 12.5% raised cosine filter; when aI, the transmit spectrum is shaped by a square
root of 20% raised cosine filter. NEWCO must be set after changing the SHAPO bit. (V.33)
The 20% option is provided for use in the V.29 configurations when communicating with other
modems which use the 20% filter. The 12.5% option is for commuOicating over a channel which has
a known narrow bandwidth. This option should be used when a secondary channel IS added to the
modem.
SHAPI
1 :2:3
o
Receiver Shaping Filter Select. When control bit SHAPI IS a 0, the receiver low pass filter is square
root of 12.5% raised cosme; when aI, the low pass filter is square root of 20 0/0 raised cosine.
NEWCl must be set after changing the SHAPI bit. (V.33)
The 20% option is provided for use in the V.29 configurations when communicating with other
modems which use the 20 0/0 filter. The 12.50,1, option is for communicating over a channel which has
a known narrow bandwidth. This option should be used when a secondary channel is added to the
modem.
SPEED
1 :E:0-2
Speed Indication. The SPEED status bits indicate the receiver's data rate at the completion of the
traiOlng sequence for V.33 configurations.
SPEED
7
6
5
SODIS
1 2:6
o
Data Rate
V.3314400
V.3312000
V.33 9600
Squarer Disable (Tone Detector C). When control bit SODIS is aI, the squarer in front of tone
detector C is disabled; when a 0, the squarer is enabled.
2-91
II
R144DP
V.33 14.4 kbps Full-Duplex Modem
Table 8.
Mnemonic
TBUFFER
Memory
Location
0:0:0-7
R144DP Interface Memory Bit Definitions (Continued)
Default
Value
-
Name/Description
Transmitter Buffer/Transmitter Signal Point X. The host conveys output data to the transmitter in
the parallel mode by writing a data byte to the TBUFFER.
The data is transmitted bit 0 first and is divided on the following baud boundaries:
Bits
Configuration
V.3314400
V.3312000
7
6
-
-
-
V.27 2400
TCONF
0: 12:0-7
31
-
J
-
-
3
I
2
I
1
I
0
Baud 0
I
I
-
Baud 1
Baud 3
-
I
Baud 1
Baud 1
V.29 4800
V.27 4800
4
Baud 1
V.29 9600
V.29 7200
I
BaudO
-
TCM 9600
TCM 7200
5
Baud 2
-
I
Baud 1
Baud 3
Baud 2
I
BaudO
I
Baud 0
Baud 0
I
Baud 1
I
Baud 1
BaudO
I
Baud 0
Baud 0
I
BaudO
Transmitter Configuration. The TCONF control bits select one olthe following transmitter configurations:
Mode
Data Rate
TCONF(Hex)
V.33TCM
V.33TCM
TCM
TCM
V.29
V.29
V.29
V.27
V.27
V.27
V.27
Single Tone
Dual Tone
Dialing
14400
12000
9600
7200
9600
7200
4800
4800 Long
2400 Long
4800 Short
2400 Short
31
32
34
38
14
12
11
22
21
02
01
80
83
81
-
When a single tone or dual tone mode is selected, the modem transmits one
or two tones respectively. The tone frequencies are host programmable in
DSP RAM. Single tone transmit uses the Dual Tone 1 frequency and level.
TLVL
0: 13:4-7
0
Transmit Level. The TLVL code selects the transmitter analog output level at the TXA pin as follows:
TLVL Code
(Hex)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
TX Output Level
(dBm :!: 0.5 dB)
-0.5
-1.5
-2.5
-3.5
-4.5
-5.5
-6.5
-7.5
-8.5
-9.5
-10.5
-11.5
-12.5
-13.5
-14.5
-15.5
The host can fine tune the transmit level to a value lying within a 1 dB step by changing a value in
DSP RAM.
2-92
R144DP
V.33 14.4 kbps Full-Duplex Modem
Table 8.
Mnemonic
Memory
Location
R144DP Interface Memory Bit Definitions (Continued)
Default
Value
Name/Description
TaD
2:4:1
0
Train On Data. When set to aI, control bit TaD enables the train·on-data algorithm to converge the
equalizer if the signal quality degrades A BER of 10-' for 0.5 seconds initiates the train-on-data. The
receiver can typically traln-on·data in less than 15 seconds for V.33 or V.29 and less than 3.5 seconds
for V.27. When TaD is aI, the modem is still able to recognize an incoming training sequence.
TONEA
1 :B:7
-
Tone A Detected. When set to aI, status bit TONEA indicates that energy is present on the line
within the tone detector A passband and above its threshold. The bandpass filter coefficients are host
programmable in DSP RAM.
TONEB
I'B:6
-
Tone B Detected. When set to aI, status bit TONEB indicates that energy is present on the line
within the tone detector B passband and above its threshold. The bandpass filter coefficients are host
programmable in DSP RAM.
TONEC
I:B:5
-
Tone C Detected. When set to aI, status bit TONEC indicates that energy is present on the line
within the tone detector C passband and above its threshold. The bandpass filter coefficients are host
programmable In DSP RAM. The TONEC filter is preceded by a squarer in order to facilitate detection
of difference tones. The squarer may be disabled with the SODIS bit (see SODIS bit).
TPDM
0.S.6
0
Transmitter Parallel Data Mode. When control bit TPDM is aI, the transmitter accepts data for
transmission from the TBUFFER (0: 0) rather than the TXD input.
TSPA
0:5:0
0
Transmitter Signal Point Activate. When control bit TSPA is aI, the transmitter uses the signal
POints X and Y directly from registers TSPX (0.0) and TSPY (0: 1). The transmitter data input,
TBUFFER and TXD, are ignored. When TSPA is a 0, the transmitter accepts data for transmission
from the TBUFFER or the TXD Input.
TSPX
0:0'0-7
00
Transmitter Signal Point X. When TSPA is aI, register 0: 0 is used to transmit the in-phase (X)
coordinate of the transmitted Signal pOint (TSPX).
TSPY
0'1'0-7
00
Transmitter Signal Point Y. When TSPA IS aI, register 0: 1 is used to transmit the quadrature
(Y) coordinate of the transmitted signal point (TSPY).
TTDIS
0'5.2
0
Transmitter Training Disable. When control bit TTDIS IS aI, the transmitter does not generate the
training sequence at the start of transmiSSion. With training disabled, the RTS/CTS delay is less than
two baud times
TXClK
0.13:0,1
0
Transmit Clock Select. The TXClK control bits designate the origin of the transmitter data clock.
TXClK
0
2
3
Transmit Clock
Internal
External (XTClK)
Slave (RDCll<)
When the external clock IS chosen, the host supplied clock must be connected to the XTClK input
pin. The external clock Will then be reflected at the TDClK output pin.
When the slave clock IS chosen, the transmitter clock (TDCll<) IS phase locked to the receiver clock (RDCll<).
TXSO
0:5:4
0
Transmitter Squelch. When control bit TXSO IS aI, the transmitter analog output is squelched. All
other transmitter functions continue as normal. When TXSO is a 0, the transmitter output functions
normally.
ThiS bit IS useful In 2-wire configurations where It is necessary to measure the spectrum and transmit
level of a transmitter Setting the TXSO bit to a 1 turns off the transmitter so that only one of the two
carners IS present. After TXSO IS set to a 0, a retrain should be sent to reestablish the data transfer.
XACCO
0:10:7
0
X RAM Access Enable Chip O. When control bit XACCO is aI, DSP chip 0 accesses the X RAM
associated With the address In XADDO and the XCRO bit. XWTO determines if a read or write is
performed The DSP resets XACCO to a 0 upon RAM access completion.
XACCI
1.10:7
0
X RAM Access Enable Chip 1. When control bit XACCI is aI, DSP chip 1 accesses the X RAM
associated With the address In XADDI and the XCRI bit. XWTl determines if a read or write is
performed The DSP resets XACCI to a 0 upon RAM access completion.
XACC2
2:10'7
0
X RAM Access Enable Chip 2. When control bit XACC2 IS aI, DSP Chip 2 accesses the X RAM
associated with the address in XADD2 and the XCR2 bit. XWT2 determines if a read or write is
performed. The DSP resets XACC2 to a 0 upon RAM access completion.
XADDO
0'IC'0-7
00
X RAM Address Chip O. XADDO contains the X RAM address used to access DSP chip O's X Data
RAM (XCRO = 0) or X Coefficient RAM (XCRO = 1) via the X RAM Data lSB and MSB registers
(O'IS and 0'19, respectively) (See Table 9.)
2-93
•
V.33 14.4 kbps Full-Duplex Modem
R144DP
Table 8.
R144DP Interface Memory Bit Definitions (Continued)
Memory
Location
Default
Value
XADDl
1 :lC:0-7
00
X RAM Address Chip 1. XADDl contains the X RAM address used to access DSP chip 1's X Data
RAM (XCRl = O)pr X Coefficient RAM (XCRl = 1) via the X RAM Data LSB and MSB registers
(1: 18 and 1: 19, respectively) (See Table 9.)
XADD2
2: lC:0-7
00
X RAM Address Chip 2. XADD2 contains the X RAM address used to access DSP chip 2's X Data
RAM (XCR2 = 0) or X Coefficient RAM (XCR2 = 1) via the X RAM Data LSB and MSB registers
(2:18 and 2: 19, respectively). (See Table 9.)
XCRDO
0:10:2
0
X RAM Continuous Read Chip O. When control bit XCRDO IS a 1, bits XACCO and XWTO are
overridden and an X RAM read from chip 0 IS performed every sample from the locallon addressed by
XADDO (see DSP RAM Access)
XCRDl
1:1D:2
0
X RAM Continuous Read Chip 1. When control bit XCRDl IS a 1, bits XACCl and XWTl are
overridden and an X RAM read from chip 1 IS performed every sample from the location addressed by
XADDl (see DSP RAM Access).
XCRD2
2:10:2
0
X RAM Continuous Read Chip 2. When control bit XCRD2 IS a 1, bits XACC2 and XWT2 are
overridden and an X RAM read from chip 2 is performed every baud from the location addressed by
XADD2 (see DSP RAM Access)
XCRO
O:lD:O
0
X Coefficient RAM Select Chip O. When control bit XCRO IS a 1, XADDO applies to DSP chip O's
X Coefficient RAM. When XCRO is a 0, XADDO applies to the X Data RAM. This bit must be set
according to the desired RAM address (Table 10).
XCRl
1 :10:0
0
X Coefficient RAM Select Chip 1. When control bit XCRl is a 1, XADDl applies to DSP chip 1's
X Coefficient RAM. When XCRl is a 0, XADDl applies to the X Data RAM. This bit must be set
according to the deSired RAM address (Table 10).
XCR2
2:10:0
0
X Coefficient RAM Select Chip 2. When control bit XCR2 is a 1, XADD2 applies to DSP chip 2's
X Coefficient RAM. When XCR2 is a 0, XADD2 applies to the X Data RAM. This bit must be set
according to the desired RAM address (Table 10).
XDALO
0: 18:0-7
00
X RAM Data LSB Chip O. XDALO is the least significant byte of the 16·bit X RAM data word used in
reading or writing X RAM locallons in DSP chip 0,
XDALl
1 :18:0-7
00
X RAM Data LSB Chip 1. XDAL 1 is the least Significant byte of the 16·bit X RAM data word used in
reading or writing X RAM locations in DSP chip 1.
XDAL2
2: 18:0-7
00
X RAM Data LSB Chip 2. XDAL2 IS the least significant byte of the 16·bit X RAM data word used in
reading or Writing X RAM locations in DSP chip 2
XDAMO
0:19:0-7
00
X RAM Data MSB Chip O. XDAMO is the most Significant byte of the 16·bit X RAM data word used in
reading or writing X RAM locations in DSP chip O.
XDAMl
1 :19:0-7
00
X RAM Data MSB Chip 1. XDAM 1 IS the most Significant byte of the 16·blt X RAM data word used in
reading or writing X RAM locations In DSP chip 1.
XDAM2
2: 19:0-7
00
X RAM Data MSB Chip 2. XDAM2 is the most significant byte of the 16·bit X RAM data word used in
reading or writing X RAM locallons In DSP chip 2.
XWTO
0:10:1
0
X RAM Write Chip O. When XWTO IS a 1 and XACCO IS set to a 1, DSP chip 0 copies data from the
X RAM Data registers (0' 18 and 0: 19) Into the X RAM location addressed by XADDO and XCRO. When
control bit XWTO IS a 0 and XACCO IS set to a 1, DSP chip 0 reads X RAM at the location addressed
by XADDO and XCRO. The read data IS stored into the X RAM Data registers (0: 18 and 0: 19).
XWTl
1:10:1
0
X RAM Write Chip 1. When XWTl IS a 1 and XACCl is set to a 1, DSP chip 1 copies data from the
X RAM Data registers (1 : 18 and 1 : 19) into the X RAM locallon addressed by XADDl and XCR1. When
control bit XWTl IS a 0 and XACCl IS set to a 1, DSP chip 1 reads X RAM at the location addressed
by XADDl and XCR1. The read data is stored into the X RAM Data registers (1 : 18 and 1 : 19).
XWT2
2:1D:l
0
X RAM Write Chip 2.When XWT2 IS a 1 and XACC2 is set to a 1, DSP chip 2 copies data from the
X RAM Data registers (2: 18 and 2: 19) into the X RAM location addressed by XADD2 and XCR2. When
control bit XWT2 is a 0 and XACC2 IS set to a 1, the DSP chip 2 reads X RAM at the location addressed
by XADD2 and XCR2. The read data is stored In the X RAM Data registers (2: 18 and 2.19).
YACCO
0:lB:7
0
Y RAM Access Enable Chip O. When control bit YACCO is a 1, DSP chip 0 accesses the Y RAM
associated with the address in YADDO and the YCRO bit. YWTO determines If a read or write is
performed. The DSP resets YACCO to a 0 upon RAM access completion.
YACCl
1:lB:7
0
Y RAM Access Enable Chip 1. When control bit YACCl IS a 1, DSP chip 1 accesses the Y RAM
associated wlth·the address In YADDl and the YCRl bit YWTl determines If a read or write IS
performed. The DSP resets YACCl to a 0 upon RAM access complellon.
Mnemonic
Name/Description
2-94
V.33 14.4 kbps Full-Duplex Modem
R144DP
Table 8.
Mnemonic
Memory
Location
R144DP Interface Memory Bit Definitions (Continued)
Default
Value
Name/Description
YACC2
2:1B:7
a
Y RAM Access Enable Chip 2. When control bit YACC2 is a 1. DSP chip 2 accesses the Y RAM
associated with the address In YADD2 and the YCR2 bit YWT2 determines If a read or write is
performed. The DSP sets YACC2 to a a upon RAM access completion
YADDO
a
lA:0-7
00
Y RAM Address Chip O. YADDO contains the Y RAM address used to access DSP chip O's Y Data
RAM (YCRO = 0) or Y Coefficient RAM (YCRO = 1) via the Y RAM Data LSB and MSB registers
(0.16 and a 17. respectively). (See Table 9.)
YADDl
1 :lA:0-7
00
Y RAM Address Chip 1. YADDl contains the Y RAM address used to access DSP chip l's Y Data
RAM (YCRl = 0) or Y Coefficient RAM (YCRl = 1) via the Y RAM Data LSB and MSB registers
(1: 16 and 1 : 17, respectively). (See Table 9.)
YADD2
2: lA:0-7
00
Y RAM Address Chip 2. YADD2 contains the Y RAM address used to access DSP chip 2's Y Data
RAM (YCR2 = 0) or Y Coefficient RAM (YCR2 = 1) via the Y RAM Data LSB and MSB registers
(2: 16 and 2: 17. respectively). (See Table 9.)
YCRDO
0:lB:2
a
Y RAM Continuous Read Chip O. When control bit YCRDO is a 1, bits YACCO and YWTO are
overridden and a Y RAM read from chip a IS performed every sample from the location addressed by
YADDO (see DSP RAM Access)
YCRDl
1 :lB:2
a
Y RAM Continuous Read Chip 1. When control bit YCRDl IS a 1, bits YACCl and YWTl are
overridden and a Y RAM read from chip 1 IS performed every sample from the location addressed by
YADDl (see DSP RAM Access)
YCRD2
2:1B:2
a
Y RAM Continuous Read Chip 2. When control bit YCRD2 IS a 1. bits YACC2 and YWT2 are
overridden and a Y RAM read from chip 2 IS performed every baud from the location addressed by
YADD2 (see DSP RAM Access).
YCRO
O:lB:O
0
Y Coefficient RAM Select Chip O. When control bit YCRO IS a 1, YADDO applies to DSP chip O's
Y Coefficient RAM. When YCRO IS a 0, YADDO applies to the Y Data RAM. This bit must be set
according to the desired RAM address (Table 9)
YCRl
l:lB:O
0
Y Coefficient RAM Select Chip 1. When control bit YCRl IS a 1, YADDl applies to DSP chip 1's
Y CoeffiCient RAM. When YCRl IS a 0, YADDl applies to the Y Data RAM. This bit must be set
according to the deSired RAM address (Table 9).
YCR2
2:1B:0
0
Y Coefficient RAM Select Chip 2. When control bit YCR2 IS a 1, YADD2 applies to the DSP chip 2's
Y Coefficient RAM. When YCR2 IS a 0, YADD2 applies to the Y Data RAM This bit must be set
according to the deSired RAM address (Table 9).
YDALO
0.16:0-7
00
Y RAM Data LSB Chip O. YDALO IS the least Significant byte of the 16·bit Y RAM data word used in
reading or writing Y RAM locations In DSP chip O.
YDALl
1 :16:0-7
00
Y RAM Data LSB Chip 1. YDAL 1 is the least Significant byte of the 16-bit Y RAM data word used In
reading or writing Y RAM locations In DSP chip 1.
YDAL2
2:16:0-7
00
Y RAM Data LSB Chip 2. YDAL2 is the least Significant byte of the 16·bit Y RAM data word used in
reading or Writing Y RAM location in DSP chip 2.
YDAMO
0:17:0-7
00
Y RAM Data MSB Chip O. YDAMO IS the most significant byte of the 16-bit Y RAM data word used In
reading or Writing Y RAM locations in DSP chip O.
YDAMl
1 :17:0-7
00
Y RAM Data MSB Chip 1. YDAMl IS the most Significant byte of the 16-bit Y RAM data word used in
reading or Writing Y RAM locations in DSP chip 1.
YDAM2
2: 17:0-7
00
Y RAM Data MSB Chip 2. YDAM2 IS the most significant byte of the 16-bit Y RAM data word used in
reading or Writing Y RAM locations in DSP chip 2.
YWTO
O:lB:l
0
Y RAM Write Chip O. When YWTO is a 1 and YACCO is set to a 1, DSP chip 0 copies data from the
Y RAM Data registers (0'16 and 0: 17) Into the Y RAM location addressed by YADDO and YCRO.
When control bit YWTO IS a a and YACCO IS set to a 1, DSP chip 0 reads Y RAM at the location
addressed by YADDO and YCRO. The read data is stored Into the Y RAM Data registers (0: 16 and 0: 17),
YWTl
l:lB:l
0
Y RAM Write Chip 1. When YWT1 is a 1 and YACCl is set to a 1, DSP chip 1 copies data from the
Y RAM Data registers (1: 16 and 1: 17) Into the Y RAM location addressed by YADDl and YCRl
When control bit YWTl is a 0 and YACCl IS set to a 1, DSP chip 1 reads Y RAM at the location
addressed by YADDl and YCR1, The read data IS stored Into the Y RAM Data registers (1: 16 and 1: 17).
YWT2
2:1B:l
0
Y RAM Write Chip 2. When YWT2 is a 1 and YACC2 is set to a 1, DSP chip 2 copies data from the
Y RAM Data registers (2'16 and 2 17) Into the Y RAM location addressed by YADD2 and YCR2
When control bit YWT2 IS a 0 and Y ACC2 IS set to a 1, DSP chip 2 reads Y RAM at the location
addressed by YADD2 and YCR2 The read data IS stored In the Y RAM Data registers (2: 16 and 2 17)
2-95
•
V.33 14.4 kbps Full-Duplex Modem
R144DP
DSP RAM ACCESS
registers; then set XCRO and/or VCRO appropriately. Write the
desired data into the interface memory RAM Data registers then
set XACCO and/or V ACCO to a 1 to signal the DSP to perform the
RAM write. When the DSP has transferred the contents of the
interface memory RAM Data registers into RAM, the DSP sets the
XACCO and/or the VACCO bit to a 0 and the NEWSO bit to a 1 to
indicate DSP RAM write completion.
DSP RAM Organization
Each DSP contains a 16-bit wide random access memory (RAM).
Because the DSP is optimized for performing complex arithmetic,
the RAM is organized into real (X RAM) and imaginary (V RAM)
parts. The host processor can access (read or write) the X RAM only,
the V RAM only, or both the X RAM and the V RAM simultaneously.
If the NSIEO bit is a 1, IRQ is also asserted and NSIAO is set to a
1 when NEWSO is set to a 1. NSIAO is cleared by writing a 0 into
the NEWSO bit, which also causes IRQ to return high if no other
interrupt requests are pending.
Interface Memory Access to DSP RAM
The interface memory acts as an intermediary during host to
DSP RAM or DSP RAM to host data exchanges. The address
stored in DSP interface memory RAM Access registers by the host,
in conjunction with the data or coefficient RAM bit (e.g., XCRO)
determines the DSP RAM address for data access.
CONTINUOUS RAM READ PROCEDURE
There are several diagnostic parameters that the host may wish
to read every sample or every baud period. One example of this
is the EQM (Eye Quality Monitor) value in chip 2 (receiver baud).
The host may avoid having to set the XACC2IV ACC2 bit every
baud period by using the continuous read feature. Setting XCRD2
to a 1 overrides both XACC2 and XWT2 bits, while setting VCRD2
to a 1 overrides both V ACC2 and VWT2 bits.
One or two 16-bit words are transferred between DSP RAM and
DSP interface memory once each device cycle. The transmitter
device and the receiver sample rate device operate at the 9600 Hz
sample rate. The receiver baud rate device operates at the baud
rate of the selected data rate.
The RAM address registers 1A and 1C and the XCR2 and VCR2
bits must be set up as described in the general DSP RAM read
procedure. Then set XCRD2 and VCRD2 to 1. The chip 2 DSP
will then transfer data to the interface memory every baud. The
NEWS2 bit is set as described in the general DSP RAM read
procedure.
Two RAM access bits in each DSP interface memory tell the DSP
to access the X RAM and/or V RAM. For example, the transfer is
initiated in the transmitter by the host setting the XACCO and/or
the VACCO bit(s). The transmitter tests these bits each sample
period. The reeeivertests XACC1 and VACC1 each sample period
and XACC2 and VACC2 each baud period.
The transmitter (Chip 0) and receiver (chip 1) can be similarly
treated, however, data will be transferred every sample by each
device.
The following procedure applies to DSP RAM access in the transmitter device. The procedure to access DSP RAM in the receiver
devices is the same with the exception of the RAM access bit
names.
Table 9 provides the RAM functions, address codes, and
registers.
DSP RAM Read Procedure (Transmitter)
SOFTWARE INTERFACE CONSIDERATIONS
Before reading from DSP interface memory, set XACCO and
V ACCO to a O. Set XWTO and/or VWTO to a 0 to inform the DSP
that a RAM read will occur when XACCO and/or VACCO is set to
a 1. Load the RAM Address code into X RAM Address and/or
V RAM address register; then set XCRO and/or VCRO appropriately. Set XACCO and/or VACCO to a 1 to signal the DSP to
perform the RAM read. When the DSP has transferred the
contents of RAM into the interface memory RAM Data registers,
the DSP sets the XACCO and/or the V ACCO bit to a 0 and the
NEWSO bit to a 1 to indicate DSP RAM read completion.
INTERRUPT REQUEST HANDLING
DSP interface memory registers registers 00, 1E and 1 F have
unique hardware connections to the interrupt logic. Register 00
is the Receive Buffer (RBUFFER)/Rate Sequence Code
LSB (RSEQL) in the receiver sample rate device and the Transmit
Buffer (TBUFFER)iTransmit Signal Point X (TSPX) in the transmitter device. Registers 1E and 1F hold interrupt flag, interrupt
enable, and interrupt active bits. When a condition occurs that
satisfies an interrupt criteria, the corresponding interrupt flag bit
is set. This interrupt flag can be reported to the host either by the
host polling the interruptflag bits (I.e., not using IRQ) or by being
interrupted by IRQ. When an interrupt enable bit is a 1, IRQ is
asserted and the appropriate interrupt active bit set to a 1 when
the corresponding interrupt condition occurs.
If the NSIEO bit is a 1, IRQ is also asserted when NEWSO is set
to a 1. When IRQ is asserted, NSIAO goes to a 1 to inform the host
that setting of the NEWSO bit was the source of the interrupt.
NSIAO is cleared bywriting a 0 into the NEWSO bit, which causes
IRQ to return high if no other interrupt requests are pending.
DSP RAM Write Procedure (Transmitter)
The basic sources for IRQ generation are status change detected,
configuration change implemented, receive buffer full and transmit buffer empty. Each source is individually maskable. Table 10
identifies the interrupt sources and describes the interrupt clearing
procedures.
Before writing to DSP Interface memory, set XACCO and VACCO
to a O. Set XWTO and/or YWTO to a 1 to inform the DSP that a RAM
write will occur when XACCO and/or VACCO is set to a 1. Load
the RAM address into X RAM Address and/or V RAM Address
2-96
R144DP
V.33 14.4 kbps Full-Duplex Modem
Table 9.
R144DP RAM Addresses
Address Code
No.
Function
1 Transmitter Compromise Equalizer
Coefficients:
First Tap
Last Tap
2 V.33 Rate Sequence
3 DTMF Tone Duration
4 DTMF Interdigit Delay
5 DTMF Low Band Power Level
6 DTMF High Band Power Level
7 Pulse Relay Make Time
8 Pulse Relay Break Time
9 Pulse Interdiglt Delay
10 Transmitter Output Level Gain Constant
11 Dual Tone 1 Frequency
12 Dual Tone 2 Frequency
13 Dual Tone 1 Power Level
14 Dual Tone 2 Power Level
15 Transmitter New Status Bit (NEWSO)
Masking Register for O:E and O:F
16 Tone Detector A Bandpass
Filter Coefficients
17 Tone Detector B Bandpass
Filter Coefficients
18 Tone Detector C Bandpass
Filter Coefficients
19 RLSD On-to-Off Threshold
20 RLDS Off-to-On Threshold
Note:
Address Code
Real Imaginary
Chip Part
Part
CR
No. (X)
(V)
Bit' No.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5B
34
93
9A
lA
19
99
9C
lC
lB
99
87
90
02
82
11
-
1
26
-
1
-
-
1
1
1
1
1
1
1
1
1
1
0
0
1
0
0
1
1
2C
32
-
1
1
1
1
07
01
-
1
0
1
Real Imaginary
Chip Part
Part
CR
No. (X)
(V)
Bit'
Function
21 Receiver Sample New Status Bit
(NEWS1)
Masking Register for l:A and l:B
Masking Register for l:C and 1:0
Masking Register for l:E and l:F
22 Received Signal Samples
23 Demodulator Output
24 Low Pass Filter Output
25 Average Energy
26 AGC Gain Word
27 Timing Recovery Update
28 Equalizer Input
29 Equalizer Tap Coefficients:
First Tap
Last Tap
30 Un rotated Equalizer Output
31 Rotated Equalizer Output
(Received POints)
32 Decision POints (Ideal Points)
33 Equalizer Error
34 Equalizer Rotation Angle
35 Equalizer Frequency Correction
36 Eye Quality Monitor (EQM)
37 Maximum Penod of Valid Ring Signal
38 Minimum Period of Valid Ring Signal
39 Receiver Chip 2 New Status Bit (NEWS2)
Masking Register for 2:E and 2·F
-
1
1
1
1
1
1
1
1
1
2
9B
9C
90
03
04
00
02
01
25
18
84
80
98
1
1
1
0
0
0
0
1
0
0
2
2
2
2
18
47
01
02
98
C7
81
82
1
1
0
1
2
2
2
2
2
2
2
2
02
03
87
OA
07
17
97
7E
82
83
0
0
1
1
1
0
0
0
-
-
-
1. CR corresponds to XCRO, VCRO, XCR1, VCR1, XCR2, or VCR2 depending on the chip number and address code.
Table 10.
Interrupt
Active
Bit
Interrupt
Enable
Bit
Interrupt
Flag
Bit
Interrupt Request Bits
Interrupt Condition Description
Interrupt Clear Procedure
Transmitter (DSP Chip 0)
NSIAO
NSIEO
NEWSO
New status detected (NEWSO transitioned from a 0 to 1)
a. RAM read or RAM write occurred
b. Status bit changed in register OA through OF
Host writes a 0 into NEWSO
(Clears NSIAO to a 0)
NCIAO
NCIEO
NEWCO
New transmitter configuration Implemented by DSP
(NEWCO transitioned from a 1 to a 0)
Host writes a 0 into NCIEO
(Clears NCIAO to a 0)
DBIAO
DBIEO
DBAO
Transmitter Data Buffer is empty and can be wntten
(DBAO transilloned from a 0 to a 1)
Host writes to register
0:0 (TBUFFERlTSPX)
(Clears DBAO and DBIAO to 0)
Receiver (DSP Chip 1)
NSIAl
NSIEl
NEWSl
New status detected (NEWSl transitioned from a 0 to a I)
a. RAM read or RAM write occurred
b. Status bit changed in register OA through OF
Host writes a 0 into NEWSI
(Clears NSIAI to a 0)
NCIAI
NCIEl
NEWCI
New receiver configuration or receiver threshold
implemented by DSP (NEWCl transilloned from a 1 to a 0)
Host writes a 0 into NCIEI
(Clears NCIA I to a 0)
DBIAl
DBIEl
DBAl
Receiver Chip 1 Data Buffer is full and can be read
(DBA I transitioned from a 0 to a 1)
Host reads register
1:0 (RBUFFER/RSEQL)
(Clears DBA I and DBIA I to 0)
Receiver (DSP Chip 2)
NSIA2
NSIE2
NEWS2
New status detected (N EWS2 transitioned from a 0 to a I)
a. RAM read or RAM write occurred
b. Status bit changed in register OF
Host writes a 0 into NEWS2
(Clllars NSIA2 to a 0)
TBIA2
DBIE2
DBA2
Receiver Chip 2 Data Buffer IS full and can be read
(DBA2 transitioned from a 0 to a 1)
Host reads register 2:0 (RSPX)
(Clears DBA2 and DBIA2 to 0)
2-97
•
R144DP
V.33 14.4 kbps Full-Duplex Modem
AUTO DIAL PROCEDURE
The auto dialer default parameters are given In Table 11.
Table 11.
The host auto dial procedure is the same as outputting data to be
transmitted using TBUFFER (Figure 5). The modem timing
accounts for the DTMF tone duration and amplitude, pulse
make/break ratio, and interdigit delay. These dialing parameters
are host programmable in DSP RAM.
Auto Dialer Default Parameters
Parameter
DTMF Tone Duration
DTMF Interdlgit Delay
DTMF Total Output Power Level
DTMF Low Band Power Level
DTMF High Band Power Level
The levels of the high band and low band DTMF tones may be
modified by the host in DSP RAM. The level of the high band
DTMF tone should be 2 dBm greater than the level of the low band
DTMFtone.
Pulse Relay Make Time
Pulse Relay Break Time
Pulse Interdlglt Delay
Dial Digits
Hex
00
01
02
03
04
05
06
07
08
09
OA
OB
Dial
Digits
0
1
2
3
4
5
6
7
8
9
.
#
Tone Pairs
941
697
697
697
770
770
770
852
852
852
941
941
Figure 5.
1336
1209
1336
14n
1209
1336
1477
1209
1336
14n
1209
1477
R144DP Auto Dial Sequence and Dial Digits
2-98
Default Value
95ms
70ms
OdBm
-4dBm
-2dBm
36ms
64ms
750ms
R144DP
V.33 14.4 kbps Full-Duplex Modem
PERFORMANCE
TYPICAL BIT ERROR RATES
TYPICAL BER TEST SETUP
Typical modem bit error rate (SER) curves are shown in Figure 6
for a back-to-back connection.
The SER curves shown in Figure 6 were prepared from data
obtained with a TAS 1002 test system.
10- 3
\
r+ V.l3114400
TCM
-
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V.29/4800-
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V.33112000
I- TCM
~
a:
10-'
w
!!!.
.,
g
V.29/9600
.!l
a:
V.29moo
V.27/4800
w
iii
10- 5
V.27/2400 _ _
10- 6
o
5
10
15
20
25
30
Signal to Noise Ratio (SNR) - dB
a. Typical Bit Error Rate (Back-to-Back, - 20 dBm Receive Level,
T Equalizer, Compromise Equalizer Disabled)
Figure 6.
Bit Error Rate Curves
2-99
•
R144DP
V.33 14.4 kbps Full-Duplex Modem
GENERAL SPECIFICATIONS
Table 12.
R144DP Modem Power Requirements
Current (Typical)
Current (Maximum)
Voltage 1
Tolerance
@25°C
@aoc
+5VDC
+12VDC
-12VDC
±5%
±5%
±5%
170mA
3mA
30 rnA
325mA
6mA
36mA
Note: 1. Input voltage ripple sO. 1 volts peak-to-peak.
Table 13.
R144DP Modem Environmental Specifications
Parameter
Temperature
Operating
Storage
Relative Humidity:
Altitude
Specification
DoC to + 70°C (32°F to 158°F)
- 40°C to + 80°C (- 40°F to 176°F) (Stored in heat sealed antistatic bag and shipping container)
Up to 90% noncondensing, or a wet bulb temperature up to 35°C, whichever is less.
- 200 feet to + 10,000 feet
Table 14.
R144DP Modem Mechanical Dimensions
Parameter
DIN Connector Version
Board Structure:
Mating Connector:
Dimensions:
Width
Length
Connector Height
Component Height
Top (max.)
Boltom (max.)
Weight (max.):
Lead Extrusion (max.):
DIP Connector Version
Board Structure:
Dimensions:
Width
Length
Component Height
Top (max.)
Boltom (max.)
Weight (max.):
Pin Length (max.)
Specification
Single PC board with a 3-row 64-pin right angle male DIN connector with rows A and C populated. The
modem can also be ordered with the following DIN connector: 64-pin DIN right angle female, 64-pin
DIN vertical male or 54-pin DIN vertical female.
Female 3-row 64-pln DIN receptacle with rows A and C populated. Typical receptacle:
Winchester 96S-6043-0531-1, Burndy RI96B32ROOAOOZI, or equivalent.
3.937 In. (100 mm)
4.725 in. (120 mm)
0.437 In. (11.1 mm)
0.300 In. (7.62 mm)
0.130 In. (3.3 mm)
3.6 oz (100 g)
0.100 In. (2.54 mm)
Single PC board with a row of 30 pins and a row of 31 pins in a dual in-line pin configuration.
3.228 in (82 mm)
3.937 In. (100 mm)
0.300 in. (7.62 mm)
0.130 in. (3.3 mm)
3.6 oz. (100 g)
0.535 ±0.015 In. (13.6 ±0.4 mm), gold plated.
0.433 ±0.015 in (11.0 ±0.4 mm), gold plated.
0.315 ±0.015 In (8.0 ±0.4 mm), gold plated.
2-100
R144DP
V.33 14.4 kbps Full-Duplex Modem
0.156 :t 0.003 DIA (6 PL)
1/ (3.96)
! :
1
MALE 64-PIN
DIN CONNECTOR
~~
-
3.937
(100)
-~
.700
_3_
(94)
1
11
~
•
,
0.119
(3)1
-
-(
.m~
+-
4.100 (83)
O. 483
(1 2.3)
4.725 (104)
120
0.300 MAX
l:::mn_nnn_nnn ___ ~
t
to.~~: ~~~n
-
---
--
--
---
-
--- --- ---
(1.6)
0.437
-f~
~;.!~
MAX ]
COMPONENT AREA
UNITS: INCHES
DIN CONNECTOR VERSION
-I
3.228
i~~
Lo
l
MU"~J
(2.5)
00000000000000000000 0
0'100~'100 (TYP.)
(2.54)
0.100
(2.54)
(2.54)
3725
-'3.937 (94.6)
(100)-------+1
SEE TABLE 14
0.025 SQ. PIN
I
0.300 MAX
r-="':-"":,1O_;"
T~.~~;---------
----
------'1G.130
(1.6)
(3.3)
COMPONENT AREA
DIP CONNECTOR VERSION (PRELIMINARY)
Figure 7.
R144DP Modem Dimensions and Pin Locations
2-101
mm
V.33 14.4 kbps Full-Duplex Modem
R144DP
ELECTROMECHANICAL DESIGN
CONSIDERATIONS
(EMI). When designing the host system, do not position radiating
circuitry in the vicinity of this sensitive area. A ground plane
adjacent to the modem analog circuitry is recommended.
The area outlined by the analog ground plane in Figure 8 contains
components which are sensitive to electromagnetic interference
t
ANALOG
GROUND
PLANE
~
-$-
23
Figure 8.
Analog Ground Plane Location
2-102
R1496DP
Integral Modems
'1'
Rockwell
R1496DP
V.33 14.4 kbps/V.32 9600 bps
Full-Duplex Modem
INTRODUCTION
FEATURES
The Rockwell R1496DP is a 14400 bps 4-wire/9600 bps 2-wire fullduplex, synchronouslasynchronous CCITT V:33 and V:32 modem
data pump. It is designed to operate over leased lines, with dial
backup, through the appropriate line termination. It is packaged
in a small module with dual-in-line (DIP) connection for direct
installation onto a host module.
• Compatibilities
- CCITT: V:33, V.32, V.29, V:22 bis
• Parallel synchronous
• Serial synchronous/asynchronous
• 4-Wire/2-Wire Full-Duplex Operation
• Trellis-Coded Modulation (TCM) at 14400, 12000,9600 and
7200 bps
• 12000 bps data rete in V.32 (proprietary)
• Programmable Near and Far End Echo Cancellation
• Bulk Delay for Satellite Transmission
• Auto-Dial and Auto-Answer Capability
• OfE Interface
- Functional: CCITT V:24 (R8-232-C) (Data/Control) and
Microprocessor Bus (Data/Configuration/Control)
- Electrical: TTL and CMOS Compatible
• Dynamic Range: - 43 dBm to 0 dBm
• Equalization
- Compromise Equalizer in Transmitter
- Automatic Adaptive Equalizer in Receiver
• Diagnostic Capability
• Loopback
- Local Analog
- Remote Digital
- Remote Analog (V.33, V.29)
• Small Size
- 82 mm x 100 mm (3.23 in. x3.94 in.) with DIP Connection
• Low Power Consumption: 1.9 W (Typical)
The modem satisfies the telecommunications requirements specified in CCITT recommendations V.33, V.32, V.29, and V:22 bis. The
Rl496DP can operate at speeds of 14400, 12000,9600,7200, 4800.
2400. or 1200 bps.
The R1496DP is designed for use in ultra high speed data applications. User programmable features allow the modem operation
to be teilored to support a wide range offunctional requirements.
The modem's small size (less than 13 square inches), low
power consumption, serial/parallel host interface, and DIP connection simplify system development and reduce system production cost.
This data sheet applies to the R1496DP with device numbers
C5309-13, C5306-17, C5307-17, and subsequent.
R1496DP Modem
Document No. 29200N31
Data Sheet
2-103
Order No. MD31
Rev. 2, January 1989
2
V.33 14.4 kbpslV.32 9600 bps Full-Duplex Modem
R1496DP
TECHNICAL SPECIFICATIONS
RTS-CTS RESPONSE TIME
CONFIGURATIONS, SIGNALING RATES
AND DATA RATES
The response times of CTS relative to a corresponding transition
of RTS are given in Table 2.
The selectable modem configurations, along with the corresponding signaling (baud) rates and data rates, are listed in Table 1.
Table 2.
RTS·CTS Response Time
RTS-CTS Response!
TONE GENERATION
Controlled
Carrier
1393 ms2
253 ms2
Under control of the host processor, the modem can generate
single or dual voice-band tones from 0 Hz to 4800 Hz with a resolution of 0.15 Hzand an accuracy of 0.01%. Tones over 3000 Hz
are attenuated. DTMF tone generation allows the modem to operate as a programmable DTMF dialer.
Configuration
Constant
Carrier
V.33
V.29
V.32
V.22 bis
s2ms
s2ms
DATA ENCODING
Notes:
1. Times listed are CTS turn-on. CTS turn-off is less than 2 ms for
all configuration.
2. Add echo protector tone duration plus 20 ms when echo protector tone is used.
3. rurn-off sequence consists of transmission of remaining data and
scrambled ones for controlled carrier operation.
- = not applicable
The data encoding conforms to CCITT recommendations V.33,
V.32, V.29, and V.22 bis.
EQUALIZERS
Equalization functions are provided that improve performance
when operating over low quality lines.
Compromise Equalizer - A 40-tap digital finite impulse
response (FIR) filter in the transmitter provides compromise
equalization. The filter taps can be changed in DSP RAM for varying line cond~ions. The default equalizer tap coefficients compensate for half the amplitude distortion of a 3002 unconditioned line
and for half the group delay distortion of a 3002 unconditioned
line. The filter can be enabled or disabled using the CEQ bit in
the Chip 0 interface memory.
TRANSMITTER TIMING
Transmitter timing is selectable between internal (± 0.01%),
external or loopback.
SCRAMBLERIDESCRAMBLER
The modem incorporates a self·synchronizing scramblerl
descrambler in accordance with the applicable CCITT
recommendation.
When the compromise equalizer is disabled, the transmitter spectrum is shaped by raised cosine filter functions as follows;
V.3~000
The transmitter generates a 2100 Hz answer tone for 3.6 seconds
at the beginning of the answer handshake when the NV25 bit is
a zero. This is applicable to V.32 and V.22 bis. The V.32 answer
tone has 180 degree phase reversals every 0.45 seconds to
disable network echo cancellers.
Configurations, Signaling Rates and Data Rates
Carrier Frequency
Configuration
V.3314400
ANSWER TONE
Raised Cosine Filter Function
Square root of 12.5% or 20% as
selected by the SHAPO bit in the
transmitter interface memory.
Square root of 75%
Table 1.
Modulation!
rCM
rCM
rCM
rCM
rCM
TCM
QAM
QAM
rCM
QAM
QAM
QAM
QAM
QAM
-
TRANSMIT LEVEL
TRANSMITTED DATA SPECTRUM
V.22 bis
-
270ms
15ms
12ms
The transmitter output level is selectable from - 0.5 dBm to
-15.5 dBm in 1 dB steps and is accurate to ± 0.5 dB. The output
level can also be fine tuned to a value within a 1 dB step by chang·
ing a gain constant in RAM.
Automatic Adaptive Equalizer - A 48-tap automatic adaptive equalizer is provided in the receiver. The equalizer can be
configured as either a T or a T/2 equalizer using the EQT2 bit in
the Chip 2 interface memory.
Configuration
V.33, V.32, V.29
-
Turn·Off
Sequence3
(Hz)
±O.OI%
1800 or 1700.
1800 or 1700
1800 or 1700
1800 or 1700
1800
1800
1800
1800
1800
1700
1700
1700
1200/2400
1200/2400
Data Rate
(bps)
±O.OI%
14400
12000
9600
7200
12000
9600
9600
4800
7200
9600
7200
4800
2400
1200
V.33 9600 TCM2
V.33 7200 TCM2
V.32 12000 TCM2
V.32 9600 TCM
V.329600
V.324800
V.32 7200 TCM2
V.299600
V.297200
V.294800
V.22 bls 2400
V.22 bis 1200
Tone Transmit
Notes: 1. Modulation legend: TCM: Trellis-Coded Modulation
QAM: Quadrature Amplitude Modulation
FSK: Frequency Shift Keying
2·104
Baud
(Symbols/Sec.)
2400
2400
2400
2400
2400
2400
2400
2400
2400
2400
2400
2400
600
600
2. Proprietary
Bits per Symbol
Data
6
5
4
3
5
4
4
2
3
4
3
2
4
2
Constellstion
TCM
Points
1
1
1
1
1
1
0
0
1
0
0
0
0
0
128
64
32
16
64
32
16
4
16
16
8
4
16
4
R1496DP
V.33 14.4 kbps/V.32 9600 bps Full-Duplex Modem
RECEIVE LEVEL
AUTO-DIALING AND AUTO-ANSWERING CONTROL
The receiver satisfies performance requirements for received line
signal levels from 0 dBm to - 43 dBm. The received line signal
level is measured at the Receiver Analog (RXA) input.
General Description
Functions are provided to allow the host to perform autO-dialing
and auto-answering. These functions include DTMF or pulse dialing, ringing detection and a comprehensive supervisory tone
detection scheme. The major parameters of these functions are
host programmable, enabling the host to customize the modem
to work on the public switched telephone network (PSTN).
RECEIVER TIMING
The timing recovery circuit can track a ±0.01% frequency error
in the associated transmit timing source.
CARRIER RECOVERY
Supervisory Tone Detection
The carrier recovery circuit can track a ± 7 Hz frequency offset
in the received carrier with less than a 0.2 dB degradation in bit
error rate (BER).
Three parallel tone detectors (A, B, and C) are provided for supervisory tone detection. The signal path to these detectors is
separate from the main received signal path. Therefore, the tone
detect signal does not pass through the highpass section of the
analog receive bandpass filter, enabling the tone detection to be
largely independent of the receiver status. The tone detection
bandwidth depends on the configuration:
CLAMPING
Received Data (RXD) is clamped to a constant mark whenever the
Received Line Signal Detector (RLSD) is off. RLSD can be
clamped off by a bit in the receiver sample rate device interface
memory (RLSDE).
Receiver Configuration
Tone Detection Bandwidth
V.33, V.32
V.29
V.22 bis Originate
V.22 bis Answer
ECHO CANCELLER
A data echo canceller with near-end and far-end echo cancellation is included for 2-wire full duplex V.32 operation. The combined
echo span of near and far cancellers is host programmable with
a default value of 53.3 ms (53.3 ms is also the maximum programmable value). The proportion allotted to each end is host programmable with default values of 23.3 ms for near-end and 30 ms for
far-end. The delay between near-end and far-end echoes can be
up to 1.7 seconds. The canceller can compensate for ± 7 Hz frequency offset in the far-end echo.
0-3400
0-3400
0-2800
0-1700
Hz
Hz
Hz
Hz
There are, however, some restrictions depending on the receiver
configuration and status:
1. When DATAl bit (see Table 8) is a 0, all three tone detectors are
enabled.
2. When DATA1 bit is a 1 and the receiver is in synchronous mode
(except V.32 12000), tone detectors A and B are enabled and
tone detector C is disabled.
3. When DATAl bit is a 1, the receiver is in asynchronous mode
or 11.32 12000, and the TDAE bit is a 1, tone deteCtor A is enabled
and tone detectors Band C are disabled.
4. All three tone detectors are disabled during a V.32 handshake.
The echo canceller error signal may be monitored through the
transmitter DSP interface memory.
ASYNC/SYNC, SYNC/ASYNC CONVERSION
An asynchronous-to-synchronous converter is provided in the
transmitter and a synchronous-to-asynchronous converter is
provided in the receiver. The converter operates in serial mode
only. The asynchronous character format is 1 start bit, 5 to 8 data
bits, an optional parity bit, and 1 or 2 stop bits. Valid character sizes,
including all bits, are 7, 8, 9, 10 and 11 bits per character. Two ranges
of signaling rates are provided:
Each tone detector consists of two cascaded second order IIR
biquad filters. The coefficients are host programmable. Each fourth
order filter is followed by a level detector which has host programmable turn-on and turn-off thresholds allowing hysteresis. Tone
detector C is preceded by a prefilter and squarer. This circuit is
useful for detecting a tone with frequency equal to the difference
between two tones that may be simultaneously present on the line.
The squarer may be disabled by the SODIS bit in interface memory
causing tone detector C to be an eighth order filter.
• Basic range: + 1% to - 2.5%
• Extended overspeed range: + 2.3% to - 2.5%
When the transmitter's converter is operating at the basic signaling rate, no more than one stop bit will be deleted per 8 consecutive characters. When operating at the extended rate, no more than
one stop bit will be deleted per 4 consecutive characters. Break
is handled in the transmitter and receiver as described in V.22 bis.
Supervisory Tone Detectors, Default Characteristics
The default bandwidths and thresholds of the tone detectors are
as follows:
Asynchronous characters are accepted by the transmitter on the
TXD serial input and issued by the receiver on the RXD serial output. To configure the converters, the host must set up interface
memory bits EXOSO, PENO, STBO and WDSZO bits before setting
ASYNO for the transmitter and EXOS1, PEN1, STB1 and WDSZl
bits before setting ASYNI for the receiver. (See description ofthese
bits in Table &) Asynchronous data mode is not supported at data
rates greater than 9600 bps.
Tone Detector
Bandwidth
A
B
C Prefilter
C
245-650 Hz
360-440 Hz
0-500 Hz
50-110 Hz
Turn-On
Threshold
Turn-Off
Threshold
-25 dBm
-25dBm
N/A
-31 dBm
-31 dBm
N/A
,
,
'Tone Detector C will detect a difference tone within its bandwidth
when the two tones present are in the range -1 dBmto -26 dBm.
2-105
•
V.33 14.4 kbpsN~32 9600 bps Full-Duplex Modem
R1496DP
HARDWARE INTERFACE SIGNALS
to activate logic on its falling edge (high-to-Iow transition) is called
active high, (e.g., TDClK). When a clock input is associated with
a small circle, the input activates on a falling edge. If no circle is
shown, the input activates on a rising edge.
The functional interconnect diagram (Figure 1) shows the typical
modem connection in a system. In this diagram, any point that is
active low is represented by a small circle at the signal point.
Edge triggered inputs are denoted by a small triangle (e.g.,
TDCll<). Open-Collector (open-source or open-drain) outputs are
denoted by a small half-circle (e.g., IRQ). Active low signals are
overscored (e.g., POR).
The hardware interconnect signals shown in Figure 1 are
organized into six functional groups: overhead, microprocessor
interface, V.24 interface, anpillary, analog, and diagnostic. These
signals, along with their connector pin numbers and interface circuit types, are listed in Table 3. The digital interface characteristics are defined in Table 4.
A clock intended to activate logic on its rising edge (Iow-to-high
transition) is called active low (e.g., RDCll<), while a clock intended
RTS
0
CTS
TXD
t
t
TDCLK
V.24
INTERFACE
SCOPE
XTCLK
EYEX
RLSD
EYEY
RXD
EYESYNC
RDCLK
EYECLK
EYE
PATTERN
GENERATOR
DTR
, DSR
RI
RXA
TXA
R1496DP
MODEM
READ
WRITE
RD
DATA BUS (8)
ADDRESS BUS (5)
t
I
HOST
PROCESSOR
(DTE)
DECODER
LINE
INTERFACE
OHRC
CS(3)
RS,
TBCLK
CSI
RBCLK
IRQ
TMXCLK
ANCILLARY
CIRCUIT
INTERFACE
J
+5
+5V
POR
+12V
-12V
AGND
DGND
Figure 1. R1496DP FunC1ionallnterconnect Diagram
2-106
POWER
SUPPLY
--
}
TELEPHONE
LINE
R1496DP
V.33 14.4 kbpslV.32 9600 bps Full-Duplex Modem
Table 3.
Name
Pin No.-
Type'
R1496DP Hardware Interface Signals
Description
Ground (A)
Ground (D)
+5V
+12V
-12V
POR
AGND
DGND
PWR
PWR
PWR
IAlOB
30,31
29,37,53
1,45,61
32
36
2
IAIOB
IAlOB
IAlOB
IAlOB
IAlOB
IAlOB
IAlOB
IAIOB
3
4
5
6
7
8
9
10
RS4
RS3
RS2
RSI
RSO
IA
IA
IA
IA
IA
15
16
17
18
19
CSO
IA
20
CSI
IA
21
CS2
IA
13
D4
03
02
01
DO
READ
WRITE
IRQ
Pin No.2
Description
23
46
51
Receive Data Clock
Transmit Data Clock
External Transmit Clock
Request·to-Send
Clear-to-Send
Transmitter Data
Receiver Data
Received Line Signal Detector
Data Terminal Ready
Data Set Ready
Ring Indicater
C. V.24 INTERFACE:
Analog Ground Return
Digital Ground Return
+ 5 Volt Supply
+ 12 Volt Supply
- 12 Volt Supply
Power.()n·Reset
14
12
11
IA
IA
OC
OA
RDCLK
TDCLK
XTCLK
OA
IA
IA
RTS
CTS
B. MICROPROCESSOR INTERFACE:
07
06
05
~pe'
Name
A. OVERHEAD:
}
Data Bus (8 Bits)
50
49
49
OA
TXD
RXD
RLSD
orR
DSR
IA
IA
OA
Ai
OA
OA
OA
26
27
40
41
25
D. ANCILLARY CIRCUITS:
RBCLK
TBCLK
TMXCLK
}--
OA
OA
22
47
OA
43
Receiver Baud Clock
Transmitter Baud Clock
Transmitter Mux Clock
E. LINE INTERFACE:
(5 Bits)
Chip Select
Transmitter Device
Chip Select Receiver
Sample Rate Device
Chip Select Receiver
Baud Rete Device
Read Enable
Write Enable
Interrupt Request
TXA
AA
34
RXA
OHRC
RD
AB
00
IA
33
35
24
OA
OA
OA
56
55
Transmitter Analog Output
Receiver Analog Input
Off·Hook Relay Control
Ring Detect
F. DIAGNOSTIC:
EYEX
EYEY
EYECLK
EYESYNC
57
58
OA
Eye Pattern Dete-X Axis
Eye Pattern Data-Y Axis
Eye Pattern Clock
Eye Pattern Synchronizing
Signal
Notes:
1. Refer to Table 4 for digital circuij interface characteristics and
Table 7 for analog circuit interface characteristics.
2. The following pins should be left open: 28, 39, 44, 52, 59 and 60.
3. The following pins are not usad but should be connectad to
DGND through individual 10 Kil series resistors: 38, 42 and 54.
4. Unusad inputs tied to + 5V or ground require Individual 10 KIl series
resistors.
Table 4. DlgHallnterface Characteristics
Input/Output ~pe
Symbol
Parameter
Units
IA
OA
OB
V IH
Input Voltage, High
V
2.0 Min.
V IL
Input Voltage, Low
V
0.8 Max.
VOH
Output Voltage, High
V
3.5 Min.'
3.5 Min.'
VOL
Output Voltage, Low
V
0.4 Max. 2
0.4 Max. 3
liN
Input Current, Leakage
IOH
Output Current, High
mA
-0.1 Max.
-0.1 Max
IOL
Output Current, Low
mA
1.6 Max.
0.8 Max.
±10Max.
±10 Max.
,.A
IL
Output Current, Leakage
,.A
CL
Capacitive Load
pF
Capacijive Drive
pF
Co
Circuij Type
1. I Load = -100,.A
2. I Load - 1.6 mA
0.4 Max. 2
0.75 Typ.2
1.6 Max.
15.0 Max.5
5.0 Max.
()4
5
100
100
100
TTL3-state
TTL3-state
Open-Drain
Open-Drain
Notes
5. Can drive a + 5V relay with COil resistance greater thim 3801J.
3. I Load = 0.8 mA
4. ,.A leakage
2-107
--~~--
OD
±2.5 Max.
TTL
----
OC
-
-~---
•
R1496DP
V.33 14.4 kbpslV.32 9600 bps Full-Duplex Modem
POWER-ON-RESET
The selected OSP decodes RSO through RS4 to address one of
32 internal interface memory registers (OO-lF). The most significant address bit'is RS4 while the least significant address bit is
RSO. The selected register can be read from or written into via the
8-bit parallel data bus (00-07). The most significant data bit is 07
while the least significant data bit is ~O.
When power is applied to the modem, the modem pulses PowerOn-Reset (POR) low to begin the POR sequence. The modem is
ready to uS,e 350 ms after the low-to-high transition of POR.
The POR sequence is reinitiated any time the + 5V supply drops
below + 3.5V for more than 30 ms, or an external device drives
POR low for at least 3 /ls. POR is not pulsed low by the modem,
when the POR sequence is initiated externally. The POR
sequence initializes the modem interface memory to default
values (Table 8). This action leaves the modem configured as
follows:
•
•
•
•
•
•
•
•
Read Enable (READ) and Write Enable (WRITE)
During a read cycle, data from the selected OSP interface memory
register is gated onto the data bus by means of three-state drivers
in each OSP. These drivers force the data lines high for a one bit,
or low for a zero bit. When not being read, the three-state drivers
assume their high-impedance (off) state.
V.33144oo
Synchronous mode
Serial channel data
Tequalizer
-43 dBm receiver threshold
Transmitter compromise equalizer enabled
Automatic rate change enabled
Train-on-data disabled
During a write cycle, data from the data bus is copied into the
selected OSP interface memory register, with high and low bus
levels representing one and zero bit states, respectively.
The read/write cycle timing waveforms are illustrated in Figure 2
and the timing requirements are specified in Table 5.
NOTE: If the modem is used in applications where the supply
voltage can drop below +4.75V but not low enough to cause a
POR sequence (i.e., < +3.5V), the host system should generate
a POR signal upon supply voltage recovery to ensure proper
modem initialization and operation.
Table 5.
Microprocessor Interface Timing Parameters
Parameter
CSi Setup Time
RSi Setup Time
Data Access Time
Data Hold Time
Control Hold Time
Write Data Setup Time
Write Data Hold Time
MICROPROCESSOR INTERFACE
Nineteen address, data, control, and interrupt hardware interface
signals allow modem connection to an 8086 compatible
microprocessor. With the addition of external logic, the interface
can be made compatible with a wide variety of other microprocessors such as the 6502, 8086 or 68000.
Symbol
Min_
TCS
TRS
TDA
TDHR
THC
TWOS
TDHW
0
25
10
10
20
10
Max.
-
75
-
Units
ns
ns
ns
ns
ns
ns
ns
Interrupt Request (IRQ)
The modem Interrupt Request (IRQ) output may be connected to
the host processor interrupt request input in order to interrupt host
program execution for immediate modem service. The IRQ output can be enabled in the OSP interface memory to indicate
immediate change of conditions in any of the three modem OSP
devices. The use of IRQ is optional depending upon modem
application. Refer to the Software Considerations Section for a
summary of the modem interrupt bits, interrupt conditions and
interrupt clearing procedures.
The microprocessor interface allows a microprocessor to change
modem configuration, read or write channel and diagnostic data,
and supervise modem operation by writing control bits and reading status bits, The significance of the control and status bits, along
with the methods of data interchange, are discussed in the Software Interface Section.
Data Lines (00-07)
Chip Selects (CSO-CS2) and
Register Selects (RSO-RS4)
The OSP IRQ output structure is an open-drain field-effecttransistor (FET). Each of the individual OSP IRQ output lines is
wire-ORed to form the modem IRQ output signal. The modem
IRQ output can also be wire-ORed with other IRQ lines in the
application system. Any of these sources can drive the host interrupt input low, and the host interrupt servicing process normally
continues until all interrupt requests have been serviced (i.e., all
IRQ lines have returned high).
The three active low chip select lines (CSO-CS2) select one of
three modem digital signal processor (OSP) devices. The five
active high register select lines (RSO-RS4) address interface
memory registers within the selected OSP interface memory. All
eight of these lines are typically connected to the host bus address
lines; the register select lines to the five least significant lines
(AO-A4) and the chip select lines to the next two significant lines
(A5-A6) through a decoder.
Because of the open-drain structure of IRQ, an external pull-up
resistor to + 5V is required at some point on the IRQ line. The
resistor value should be small enough to pull the IRQ line high
when all IRQ drivers are off (i.e., it must overcome the leakage
currents). The resistor value should be large enough to limit the
driver sink current to a level acceptable to each driver. If only the
modem IRQ output is used, a resistor value of 5.6K ohms ± 20%,
0.25W, is sufficient.
Eight bidirectional data lines (00-07) provide parallel transfer of
data between the host and the modem. The most significant bit
is 07. Data direction is controlled by the,Read Enable and Write
Enable signals.
2-108
R1496DP
V.33 14.4 kbps/V.32 9600 bps Full-Duplex Modem
WRITE
READ
CSI
(1=0-2)
RSI
(1=0-4)
•
Oi
(1=0-7)
Figure 2.
Microprocessor Interface Timing Waveforms
V.24 INTERFACE
One of four RLSD receive level threshold options can be selected
(Table 6). A minimum hysteresis action of 2 dB exists between the
actual off-to-on and on-to-off transition levels. The threshold level
and hysteresis action are measured with a modulated signal
applied to the Receiver Analog (RXA) input. Note that performance
may be degraded when the received signal level is less than
-43 dBm. The RLSD on and off thresholds are host programmable in DSP RAM.
Eleven pins provide timing, data, and control signals for
implementing a CCITI Recommendation V.24 compatible serial
interface. These signals are TIL compatible in order to drive the
short wire lengths and circuits normally found within stand-alone
modem enclosures or equipment cabinets. For driving longer
cables, these signals can be easily converted to RS-232-C voltage
levels using 1489 receivers and 1488 drivers, or their equivalents.
Transmitted Data (TXO)
Table 6.
The modem obtains serial data to be transmitted from the local
DTE on the Transmitted Data (TXD) input.
RLSD On and OFF Thresholds
Receive Level
Received Data (RXO)
The modem presents received serial data to the local DTE on the
Received Data (RXD) output.
Request To Send (ATS)
Activating Request to Send (RTS) causes the modem to transmit data on TXD when CTS becomes active. The RTS pin is
logically ORed with the RTS bit.
Option
RLSOOn
RLSOOff
0
1
2
3
>-43dBm
> -33dBm
> -26 dBm
>-16dBm
< -48dBm
< -38dBm
<-31 dBm
<-21 dBm
Data Terminal Ready (OTR)
Clear To Send (CTS)
In V.32 and V.22 bis configurations, activating Data Terminal
Ready (DTR) initiates the handshake sequence, provided that
the DATAO bit is a 1. If in answer mode, the transmitter will
immediately send answer tone.
Clear to Send (CTS) active indicates to the local DTE
that the modem will transmit any data present on TXD. CTS
response times from an active condition of RTS are shown
in Table 2.
Received Line Signal Detector (RLSO)
During the data mode, deactivating DTR causes the transmitter
to turn-off and return to the idle state.
Received Line Signal Detector (RLSD) active indicates to the local
DTE that energy above the receive level threshold is present on
the receiver input, and that the energy is not a training sequence.
The DTR input and the DTR control bit in chip 0 are logically
ORed.
2-109
R1496DP
V.33 14.4 kbpsN.32 9600 bps Full-Duplex Modem
Data Set Ready (DSR)
Transmitter Multiplexer Clock (TMXCLK)
Data Set Ready (DSR) ON indicates that the modem is in the data
transfer state. The OFF condition of DSR indicates that the DTE
is to disregard all signals appearing on the interchange circuits
except Ring Indicator (Ai). DSR is OFF when the modem is in a
test mode (i.e., local analog or remote digitalloopback).
The Transmitter Multiplexer Clock (TMXClK) output is a 288 kHz
clock which is internally divided down to create the Transmitter
Baud Clock (TBClK). TMXClK is also a common multiple of all
the possible transmitter data clocks. The high-ta-Iow transitions
of TDClK coincide with the high-to-low transitions of TMXClK.
The DSR status bit in chip 0 reflects the state of the DSR output.
LINE INTERFACE
The Transmitter Analog (TXA) output and Receiver Analog (RXA)
input allow modem connection to either a leased line or the public switched telephone network (PSTN) through an audio transformer or a data access arrangement. The analog signal characteristics of TXA and RXA are described in Table 7.
Ring Indicator (RI)
The Ring Indicator (Ai) output follows the ringing signal present
on the line with a low level (OV) during the ON time, and a high
level ( +5V) during the OFF time coincident with the ringing signal.
Table 7.
The RI status bit in chip 2 reflects the state of the Ai output.
Analog Interface Characteristics
Name Type
Transmit Data Clock (TDCLK)
The modem outputs a synchronous Transmit Data Clock (TDClK)
for USRTtiming. The TDClK frequency is the data rate (± 0.Q1 %)
with a duty cycle of 50 ± 1%.
'
TXA
AA
RXA
AB
Characterlstlca
The transmitter output Impedance Is 604 ohms ± 1%.
The receiver input impedance is 66.5K ohms.
Transmitter Analog (TXA)
The Transmitter Analog (TXA) output can drive an audio transformer or data access arrangement. TXA is a low impedance
amplifier output in series with an internal 604 ohm ± 1% resistor
to match a standard telephone load of 600 ohms.
Transmit Data (TXD) must be stable during the one "s periods
immediately preceding the rising edge of TDClK and following
the rising edge of TDClK. The TDClK source can be internal,
external (input on XTClK) or slave (to RDClK) as selected by
bits in the transmitter interface memory.
Receiver Analog (RXA)
The Receiver Analog (RXA) input can originate from an audio
transformer or data access arrangement. The input impedance
is nominally 66.5K ohms. The RXA input must be shunted by an
external 604 ohm ± 1% resistor in order to match a 600 ohm
source.
External Transmit Clock (XTCLK)
In synchronous communication, an external transmit data clock
can be connected to the modem XTClK input. The clock supplied
at XTClK must exhibit the same characteristics as TDClK. The
XTClK input is then reflected at the TDClK output.
The maximum received signal at RXA is 0 dBm. The maximum
near-end echo at RXA that the modem can cancel in V.32 mode
is -5 dBm.
Receive Data Clock (RDCLK)
Transient protection for TXA and RXA is recommended when
interfacing directly to a transformer. This protection may take the
form of back-ta-back zener diodes or a varistor across the
transformer.
The modem outputs a synchronous Receive Data Clock (RDClK)
for USRTtiming. The RDClK frequency is the data rate (± 0.Q1 %)
with a duty cycle of 50 ± 1%. The RDClK low-la-high transitions
coincide with the center olthe received data bits. The timing recovery circuit can track a ± 0.01 % frequency error in the associated
transmit timing source.
Ring Detect (RD)
The Ring Detect (RD) input is monitored for pulses in the range
of 15 Hz to 68 Hz. The frequency detection range may be changed
by the host in DSP RAM. The circuit driving RD should be a 4N35
optoisolator or equivalent. The circuit driving RD should not
respond to momentary bursts of ringing less than 125 ms in duration, or less than 40 VRMS (15 Hz to 68 Hz) across TIP and RING.
ANCILLARY SIGNALS
Transmitter Baud Clock (TBCLK) and
Receiver Baud Clock (RBCLK)
DATA2 bit must be set to a 0 to enable ring detection. Detected
ring signals are reflected on the Ai output.
Transmitter Baud Clock (TBClK) and Receiver Baud Clock
(RBClK) outputs have no counterpart in the V.24 or RS-232-C
recommendations since they mark the baud interval rather than
the data rate for the transmitter and receiver, respectively. These
baud clocks are useful in identifying the order of data bits in a baud
(e.g., for multiplexing data). Both signals are active high. The first
bit in each baud begins with the falling edge of the corresponding baud clock.
Off-Hook Relay Control (OHRC)
OHRC is an output designed to drive directly a + 5\1 reed relay
coil 'with a worst case resistance of 360 ohms having a must operate voltage of 4.0 Vdc. A clamp diode integrated in the modem
eliminates the need for a diode across the relay coil. An
2-110
R1496DP
V.33 14.4 kbps/V.32 9600 bps Full-Duplex Modem
external transistor can be used to drive heavier loads (e.g., electromechanical relays). OHCR is controlled by the host setting the
RA bit in the interface memory.
!
EYESYNC
-----.L
1-\
Line Transformer Requirements for V_32
V32 places high requirements upon the Data Access Arrangement
(DAA) to the telephone line. V.32 uses the same bandwidth for
transmission of data in both directions. Any non-linear distortion
generated by the DAA in the transmit direction (known as nearend echo) cannot be canceled by the modem's echo canceller and
interferes with data reception. The user must therefore ensure that
the total harmonic distortion due to near-end echo at the RXA input
to the modem is at least 27 dB below the minimum level of received
signal at the same point. Note thatthe major source of non-linear
distortion in a DAA is the line transformer. When designing a DAA
the user should take into account a worst case subscriber line, giving very poor matching to the DAA hybrid circuit and resulting in
a large near-end echo (to simulate worst case conditions it is suggested that an 1800 ohm resistor in series with a 0.47 I'F capacitor be used in place of the two wire telephone line).
EYEX,~~
EYEY~~
MSB
Figure 3.
LSB
Eye Pattern Timing
SOFTWARE INTERFACE
Modem functions are implemented in firmware executing in
three DSPs: transmitter device, receiver sample rate device, and
receiver baud rate device.
DIAGNOSTIC SIGNALS
INTERFACE MEMORY
Four signals provide the timing and data necessary to create an
oscilloscope quadrature eye pattern. The eye pattern is simply a
display olthe received baseband constellation. By observing this
constellation, common line disturbances can usually be identified.
Timing of these signals is illustrated in Figure 3.
Each DSP communicates with the host processor by means of a
dual-port, interface memory. The interface memory in each DSP
contains thirty-two 8-bit registers, labeled register 00 through 1F.
Each register can be read from, or written into, by both the host and
the DSP. The host communicates with the DSP interface memory
via the microprocessor bus shared between the three DSPs.
EYEX and EYEY
The host can control modem operation by writing control bits to
DSP interface memory and writing parameter values to DSP RAM
through the interface memory. The host can monitor modem operation by reading status bits from DSP interface memory and reading parameter values from DSP RAM through interface memory.
The EYEX and EYEY outputs provide two serial bit streams containing data for display on the oscilloscope X axis and Y axis,
respectively. This serial digital data must first be converted to
parallel digital form by two serial-to-parallel converters and then
to analog form by two digital-to-analog (D/A) converters.
INTERFACE MEMORY MAPS
EYEX and EYEY outputs are 15-bit words, each with 8-bits of significance. The 15-bit data words are shifted out most significant
bit first with the seven most significant bits equal to zero. EYEX
and EYEY are clocked by the rising edge of EYECLK.
Memory maps of the 96 addressable registers in the modem transmitter (chip 0), receiver sample rate (chip 1), and receiver baud
rate (chip 2) devices are shown in Figure 4. These 8-bit registers
may be read or written during any host read or write cycle. In order
to operate on a single bit or a group of bits in a register, the host
processor must read a register then mask out unwanted data.
When writing a single bit or group of bits in a register, the host
processor must perform a read-modify-write operation. That is,
read the entire register, set or reset the necessary bits without
altering the other register bits, then write the unaffected and modified bits back into the interface memory.
EYECLK is a clock for use by the serial-to-parallel converters. The
EYECLK output is a 288 kHz clock which is internally divided down
to create the Receiver Baud Clock (RBCLI<). EYECLK is also a
common multiple of all the possible receiver data clocks. The lowto-high transitions of RDCLK coincide with the low-to-high
transitions of EYECLK. EYECLK, therefore, can be used as a
receiver multiplexer clock.
INTERFACE MEMORY BIT DEFINITIONS
Table 8 defines the individual bits in the interface memory. In the
Table 8 descriptions, bits in the interface memory are referred to
using the format Y:Z:Q. The chip number is specified by
Y (0,1 or 2), the register number byZ (00 through 1F), and the bit
number by Q (0 through 7, 0 = LSB).
EYESYNC
EYESYNC is a strobe for loading the D/A converters.
2-111
•
V.33 14.4 kbpsN.32 9600 bps Full-Duplex Modem
R1496DP
R1496DP DSP Interface Memory (Chip 0)
I~
7
5
6
NSIAO I NCIAO
DBIAO
-
IXACCO
-
IYACCOI
-
-
-
-
-
-
-
-
--
02
-
01
00
3
2
I NSIEO INEWSO
--
--
X RA I ADDF ESS(lU
-
.VL
JA;
IAT
JA·
IN
-
-
-
DSR
-
rs
TC )NF
-
0
-
INEWC
DBAO
XWTO XCRO
001 YWTO YCRO
-
I
E
-~
-
-
-
-
-
IEARC
- rxCLK-
- - IH!:llics of the CCITT V.21 Channel 2 modulation system.
Tone-The modem sends single or dual frequency tones in response to the RTS or RTSP signals.
Tone frequencies and amplitudes are controlled by RAM locations written by the host. When not
transmitting tones the Tone configuration allows detection of Single frequency tones by the TDET
bit. The tone detector frequency can be changed by the host by altering the contents of several
RAM locations.
1I.27-The modem operates as speCified in CCITT Recommendation V.27 for a 2400 bps data rate.
DDIE
DOREO
DiagnostiC Data
Interrupt Enable
E:2
When set to a one, DDIE enables an IRO Interrupt to be generated when the diagnostic data
request bit (DDREO) is a one.
. Diagnostic Data
Request
E:O
DDREO goes to a one when the modem reads from or wrotes to DDYL. ODREO goes to a zero
when the host processor reads from or writes to DDYL. Used for diagnostic data handshaking bit.
DOXL
Diagnostic Data
X Least
2:0-7
Least SignifICant byte of 16-blt word used in reading XRAM locations.
DOXM
Diagnostic Data
X Most
3:0-7
Least significant byte of 16-bit word used m reading XRAM locations.
DDYL
Diagnostic Data
Y Least
0:0-7
Least significant byte of 16-bit word used in reading YRAM locallons or writing XRAM and YRAM
locations.
DDYM
Diagnostic Data
Y Most
1:0-7
Most significant byte of 16-blt word used m reading YRAM locations or writmg XRAM and YRAM
locations.
EPT
Echo Protector
Tone
C:6
When EPT is a one, ~n unmodulated carrier is transmhted for 185 ms followed by 20 ms of no
transmitted energy at the beginning of the trammg sequence.
EOFZ
Equalizer Freeze
C:2
When EOFZ is a one, the adaptive equalizer taps stop updating and remain frozen.
EOSV
Equalizer Save
C:3
When EOSV is a one, the adaptive equalizer taps are not zeroed when reconfiguring the modem
or when entering the training state.
FED
Fast Energy
Detector
8:5,6
FED consists of a 2-bit field that indicates the level of received signal according to the following
code.
Code
Energy Level
0
1
2
3
None
Invalid
Above Turn-off Threshold
Above Turn-on Threshold
While receiving a Signal, FED normally alternates between Codes 2 and 3.
3-10
R24MFX
2400 bps MONOFAX Modem
R24MFX Interace Memory Definitions (continued)
Mnemonic
Name
Memory
Location
Description
GHIT
Gain Hit
B:4
The gain hit bit goes to one when the receiver detects a sudden increase in passband energy
faster than the AGC circuit can correct. GHIT returns to zero when the AGC output returns to
normal.
IA
Interrupt Active
E:7
IA is a one when the modem is driving the interrupt request line (IRO) to a low TIL level.
PN
Period N
8'3
PN sets to a one at the start of the received PN sequence. PN resets to zero at the start of the
receiver data state. PN does not operate when EOFZ (C:2), EOSV (C:3) or TDIS (C:4) is set to one.
RAMA
RAM Access
F:0-7
The RAMA register is written by the host when reading or writing diagnostic data. The RAMA
code determines the RAM location with which the diagnostic read or write is performed.
RAMW
RAM Write
C:O
RAMW is set to a one by the host processor when performing diagnostic writes to the modem
RAM. RAMW is set to a zero by the host when reading RAM diagnostic data.
RTSP
Request to Send
Parallel
C:7
The one state of RTSP begins a transmit sequence. The modem continues to transmit until RTSP
is turned off and the turn-off sequence has been completed. RTSP parallels the operation of the
hardware RTS control input. These inputs are ORad by the modem
RXCD
Receiver
Channel Data
5:0-7
RXCD is written to by the modem every eight bit times. This byte of channel data can be read by
the host when the receiver sets the channel data request bit (CDREO).
RX
Receive State
B:7
RX IS a one when the modem IS in the receive state (i.e., not transmitting).
SETUP
Setup
E:3
The host processor must set the SETUP bit to a one when reconfigunng the modem, I.e., when
changing CONF (D:O-7).
TOET
Tone Detected
A:7
The one state of TDET indicates reception of a tone. The filter can be retuned by means of the
diagnostic write routine.
TOIS
Training Disable
C:4
If TDIS is a one in the receive state, the modem IS prevented from entering the training phase If
TDIS is a one when RTS or RTSP go active, the generation of a training sequence is prevented at
the start of transmission.
TPDM
Transmitter
Parallel Data
Mode
C:5
When control bit TPDM IS a one, the transmitter accepts data for transmission from the TXCD
register rather than the serial hardware data input.
TXCD
Transmitter
Channel Data
4:0-7
The host processor conveys output data to the transmitter In parallel data mode by writing a data
byte to the TXCD register when the channel data request bit (CDREO) goes to a one. Data is
transmitted as Single bits in V.21 or as dibits in V.27 starting with bit 0 or dibit 0,1.
Diagnostic Data Transfer
These bits are written into interface memory registers 3, 2, 1
and 0 in that order. Registers 3 and 2 contain the most and least
significant bytes of XRAM data, respectively, while registers 1
and 0 contain the most and least significant bytes of YRAM data
respectively.
The modem contains 128 words of random access memory
(RAM). Each word is 32-bits wide. Because the modem is
optimized for performing complex arithmetic, the RAM words
are frequently used for storing complex numbers. Therefore,
each word is organized into a real part (16 bits) and an imaginary
part (16-bits) that can be accessed independently. The portion
of the word that normally holds the real value is referred to as
XRAM. The portion that normally holds the imaginary value is
referred to as YRAM. The entire contents of XRAM and YRAM
may be read by the host processor via the microprocessor
interface.
When set to a one, bit C:O (RAMW) causes the modem to
suspend transfer of RAM data to the interface memory, and
instead, to transfer data from interface memory to RAM. When
writing into the RAM, only 16 bits are transferred, not 32 bits
as for a read operation. The 16 bits written in XRAM or YRAM
come from registers 1 and 0, with register 1 being the more
significant byte. Selection of XRAM or YRAM for the destination
is by means of the code stored in the RAMA bits of register F.
When bit F:7 is set to one, the XRAM is selected. When F:7
equals zero, YRAM is selected.
The interface memory acts as an intermediary during these host
to signal processor RAM data exchanges. The RAM address
to be read from or written to is determined by the contents of
register F (RAMA). The R24MFX RAM Access Codes table lists
27 access codes for storage in register F and the corresponding
diagnostic functions. The R24MFX DiagnostiC Data Scaling table
provides scaling information for these diagnostic functions. Each
RAM word transferred to the interface memory is 32 bits long.
When the host processor reads or writes register 0, the
diagnostic data request bit E:O (DDREQ) is reset to zero. When
the modem reads or writes register 0, DDREQ is set to a one.
When set to a one by the host, bit E:2 (ODIE) enables the DDREQ
bit to cause an IRQ interrupt when set. While the IRQ line is
driven to a TTL low level by the modem, bit E:7 (IA) goes to a one.
3-11
•
R24MFX
2400 bps MONOFAX Modem
l-TPDM
l-RTSP
OR
O-RTS
N
O-CDREQ
N
DATA -
TXCD
O-CDREQ
READ RXCD
N
N
N
0 - RTSP
AND
1 - RTS
Channel Data Parallel Mode Control
3-12
2400 bps MONOFAX Modem
R24MFX
R24MFX Diagnostic Data Scaling
R24MFX RAM Access Codes
Node
Function
RAMA
Reg. No.
Node
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
AGC Gain Word
Average Power
Receiver Sensitivity
Receiver Hysteresis
Equalizer Input
Equalizer Tap Coefficients
Unrotated Equalizer Output
Rotated Equalizer Output
Decision Points
Error Vector
Rotation Angle
Frequency Correction
EQM
Alpha (a)
Beta One (13,)
Beta Two (132l
Alpha Prime (a')
Beta One Prime (13,')
Beta Two Prime (132)
Alpha Double Prime (a")
Beta Double Prime ((3")
Output Level
Tone 1 Frequency
Tone 1 Level
Tone 2 Frequency
Tone 2 Level
Checksum
Bl
F2
Fl
84
5B
lB-2A
6B
2.3
2.3
2,3
2,3
0,1,2,3
0,1,2,3
0,1,2.3
0,1,2,3
0,1,2.3
0,1,2.3
2,3
2,3
2.3
0,1
0,1
0,1
0,1
0,1
0,1
2.3
2,3
0,1
2,3
0,1
2,3
0,1
0,1
5,7-9
OA
6C
60
87
8B
BO
36
:rT
38
39
3A
3B
B6
B7
43
8E
44
8F
45
02
6
ParameteriScallng
All base-band signal point nodes (i.e., Equalizer Input,
Unrotated Equalizer Output, Rotated Equalizer Output,
and Decision Points) are 32-bit, complex, twos
y
complement numbers.
Point
X
Y
1
2
3
4
1600
EAOO
EAOO
1600
1600
1600
EAOO
EAOO
82
X
83
84
Equalizer Tap Coefficients (32-bit, complex, twos
complement)
Complex numbers with X = real part, Y = imaginary part
X and Y range: 0000 to (FFFF),s representing ± full scale
in hexadecimal twos complement.
10
Error Vector (32-bit, complex, twos complement)
Complex number with X
real part,
Y = imaginary part.
X and Y range: (8000)'6 to (7FFF),s
11
Rotstlon Angle (16-bit, signed, twos complement)
=
Rotation Angle in deg.
12
81
= (Rot. Angle Word/65,536) x 360
Frequency Correction (l6-bit signed twos complement)
Frequency correction in Hz
= (Freq. Correction Word/65,536»( Baud Rate
13
R24MFX Diagnostic Data Scaling
Node
1
ParameterlScaling
14-21
Filter Tuning Parameters (l6-bit unsigned) Alpha, Beta One,
Beta Two, Alpha Prime, Beta One Prime, Beta Two Prime,
Alpha Double Prime, and Beta Double Prime are set according
to instructions in application note 668. Use a sample rate of
7200 samples per second for all calculations.
22
Output Level (16-bit unsigned)
Output Number
27573.6 [IO( PoI2OI]
Po = output power in dBm with series 600 ohm resistor
into 600 ohm load.
Convert Output N umber to hexadecimal and store at
access code 43
AGC Gain Word (l6-bit unsigned).
AGC Gain in dB
= 50
- [(AGC Gain Word/64) x 0.098]
Range: (16CO)'6 to (7FFF)'6' For - 43 dBm Threshold
2.
3
Average Power (l6-bit unsigned)
Post-AGC Average Power in dBm
= 10 Log (Average Power Word12185)
Typical Value = (0889),6, corresponding to 0 dBm
Pre-AGC Power in dBm
= (Post-AGC Average Power-AGC Gain)
=
Receiver Sensitivity (l6-bit twos complement)
On-Number = 655.36 (52.38 + PON)
where: PON
;. Turn-on
threshold in dB
24
and
26
Tone 1 and Tone 2 Levels
Calculate the power of each tone independently by using
the equation for Output Number given at node 22.
Convert these numbers to hexadecimal then store at
access codes 44 and 45. Total power transmitted in tone
mode is the result of both tone I power and tone 2
power.
23
and
25
Tone 1 and 2 Frequency (16-bit unsigned)
N = 9.1022 (Frequency in Hz)
Convert N to hexadecimal then store at access code BE
or 8F.
27
Checksum (l6-bit unsigned)
ROM Checksum number determined by revision level.
Convert On-Number to hexadecimal and store at access
code Fl
4
Receiver HystereSiS (l6-bit twos complement)
Off-Number
where:
Range: (FCOO)'8 to (400),6 representing ± 18.75 Hz
EQM (16-bit, unsigned)
Filtered squared magnitude of error vector.
Proportionality to BER determined by particular application.
= [65.4 (lQA)]2/2
A = (POFF - PON - 0.5)120
PON
Turn-on threshold in dB
POFF = Turn-off threshold in dB
=
Convert Off-Number to hexadecimal and store at access
code 84.
3-13
•
2400 bps MONOFAX Modem
R24MFX
POWER-ON INITIALIZATION
PERFORMANCE
When power is applied to the R24MFX, a period of 50 to 350 ms
is required for power supply settling. The power-on-reset signal
(POR) remains low during this period. Approximately 10 ms after
the low to high transition of POR, the modem is ready to be
configured, and RTS may be activated. If the 5 Vdc power supply
drops below approximately 3 Vdc for more than 30 msec, the
POR cycle is repeated.
Whether functioning as a V.27 ter or V.21 type modem, the
R24MFX provides the user with unexcelled high performance.
TYPICAL BIT ERROR RATES
The Bit Error Rate (BER) performance of the modem is specified
for a test configuration conforming to that illustrated in CCITT
Recommendation V.56. Bit error rates are measured at a
received line signal level of -20 dBm.
At POR time the modem defaults to the following configuration:
RECEIVED SIGNAL FREQUENCY TOLERANCE
V.27/2400 bps, serial mode, training enabled, echo protector
The receiver' circuit of the R24MFX can adapt to received
frequency error of ± 10Hz with less than 0.2 dB degradation
in BER performance.
tone enabled, interrupts disabled, RAM access code OA,
transmitter output level set for + 5 dBm at TXA, receiver turnon threshold set for -43.5 dBm, receiver turn-off threshold set
for -47.0 dBm, tone 1 and tone 2 set for 0 Hz and 0 volts output,
and tone detector parameters zeroed.
TYPICAL PHASE JITTER
At 2400 bps, the modem exhibits a BER of 10-6 or less with a
signal-to-noise ratio of 12.5 dB in the presence of 15· peak-topeak phase jitter at 150 Hz or with a signal-to-noise ratio of 15
dB in the presence of 30· peak-to-peak phase jitter at 120 Hz
(scrambler inserted).
POR can be connected to a user supplied power-on-reset signal
in a wire-or configuration. A low active pulse of 3 ,.sec or longer
applied to the POR pin causes the modem to reset. The modem
is ready to be configured 10 msec after the low active pulse is
removed from POR.
V27,2400
,
/SK
10- 3
An example of the BER performance capabilities is given in the
following diagrams:
I
10- 3
10-'
V27,2400
FSK
10-'
w
w
l-
l-
ea::
e
0
a::
a::
0
a::
a::
I-
I-
10- 5
10- 5
a::
a::
a::
w
w
iii
iii
\
10- 6
0
5
,
10- 6
10
15
20
0
25
SIGNAL TO NOISE RATIO IN DB
5
\
10
15
20
SIGNAL TO NOISE RATIO IN DB
Typical Bit Error Rate
(Back.to·Back, Level - 20 dBm)
Typical Bit Error Rate
(Unconditioned 3002 Line, Level - 20 dBm)
3-14
25
R24MFX
2400 bps MONOFAX Modem
The BER performance test set-up is show in the following
diagram:
-
MODEM
TRANSMITTER
I--
3002
LINE
SIMULATOR
SEG FA-1445
-
IMPAIRMENT
SOURCE
BRADLEY 2A
AND 2B
'"--
ATTENUATOR
HP 3500
I
I
MODEM
TEST SET
PHOENIX
5000
LEVEL
METER
HP 3552A
MODEM
RECEIVER
I
NOTE
SIGNAL AND NOISE ARE MEASURED WITH 3 KHZ FLAT WEIGHTING_
SER Performance Test Set-up
3-15
•
2400 bps MONOFAX Modem
R24MFX
APPLICATION
5. Pin ,22 should be tied directly to pin 24 at the R24MFX
package. Pin 24 should tie directly, by a unique path, to the
common ground point for analog and digital ground.
Recommended Modem Interface Circuit
6. An analog ground plane should be supplied beneath all
analog components. The analog ground plane should
connect to pin 24 and all analog ground points shown in the
recommended circuit diagram.
The R24MFX is supplied as a 64-pin QUIP device to be designed
into original equipment manufacturer (OEM) circuit boards. The
recommended modem interface circuit and parts list illustrate
the, connections and components required to connect the modem
to the OEM electronics.
7. Pins 4, 8, 29, and 48 should tie together at the R24MFX
package. Pin 48 should tie directly, by a unique path, to the
common ground pOint for analog and digital ground.
If the auxiliary analog input (pin 26) is not used, resistors R2
and R3 can be eliminated and pin 26 must be connected to
analog ground (pin 24). When the cable equalizer controls
CABLEl and CABLE2 are connected to long leads that are
subject to picking up noise spikes, a 3k 0 series resistor should
be used on each input (Pins 32 and 33) for isolation.
8. A digital ground plane should be supplied to cover the
remaining allocated area. The digital ground plane should
connect to pin 48 and all digital ground points shown in the
recommended circuit diagram plus the crystal-can ground.
9. The R24MFX package should be oriented relative to the two
ground planes so that the end containing pin 1 IS toward the
digital ground plane and the end containing pin 32 is toward
the analog ground plane.
Resistors R4 and R9 can be used to trim the transmit level and
receive threshold to the accuracy required by the OEM
equipment. For a tolerance of ± 1 dB the 1010 resistor values
shown are correct for more than 99.8% of the units.
10. As a general rule, digital signals should be routed on the
component side of the PCB while analog signals are routed
on the solder side. The sides may be reversed to match a
particular OEM requirement.
typical Modem Interface Parts List
Component
Manufacturer's
Part Number
C3,C5,C7,C9
C2
592CX7Rl04MOSOB
N511 BY100JW
Cl
Cll
Yl
ZI
R5,R6
CI14C33OJ2G5CA
SA405C274MAA
333RI4-002
LM1458N
CML1110
TS6.6K ohm ± 1%
5MA434.0K ± 1%
5043CX3ROOOJ
5043CX2M70OJ
5043CX47KOOJ
5043CX3KOOJ
5043CX1KOOJ
ECEBEF100
SMCSOTt ROM5X12
CI24Cl02J5G5CA
IN751D
CRB '/4XF47K5
ER025QKF2370
Determined by IRQ
characteristics
R4
Rll
RIO
Rl
R7
R2,R3
Cl0
CS
C4,C6
CRI
R9
RS
R14
Manufacturer
11. Routing of R24MFX signals should provide maximum
isolation between noise sources and senSItive inputs. When
layout requirements necessitate routing these signals
together, they should be separated by neutral signals. Refer
to the table of noise characteristics for a list of pins in each
category.
Sprague
San Fernando!
Wescap
Kemet
AVX
Umden
National
Pin Noise Characteristics
Dale Electronics
Corning Electronics
Mepco Electra
Mepco Electra
Mepco Electra
Mepco Electra
Mepco Electra
Panasonic
United Chern-Con
Kemet
I.T.T
R-Ohm
Matsushita Electric
Noise Source
Low
Neutral
Low
High
1
2
5
14
15
20
21
30
3B
39
40
41
6
7
9
10
12
13
17
18
19
45
46
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
3
4
8
11
16
22
24
25
29
31
34
42
43
47
4B
26
28
32
33
23
27
35
36
37
44
PC Board Layout Considerations
1. The R24MFX and all supporting analog circuitry, including
the data access arrangement if required, should be located
on the same area of printed circuit board (PCB).
2. All power traces should be at least 0.1 inch width.
3. If power source is located more than approximately 5 inches
from the R24MFX, a decoupling capacitor of 10 microfarad
or greater should be placed in parallel with Cll near pins 11
and 48.
4. All circuitry connected to pins 9 and 10 should be kept short
to prevent stray capacitance from affecting the oscillator.
3-16
Noise Sensitive
High
:%I
N
~
s::::
~
C.
H"
PORI
3
S'IIC:OV
CABLE1
CABLEZ
CA8LE2 3'
C.
10 PF
":"
POR
PORO 32
CABLEl
5%, SOY
AUxiN
R'
:D
•
CD
g
3
3
CD
:::I
+12 VOLTS
TXA
Y2.
SERIAL
INTERFACE
Q.
co
CD
Q.
i:
~
.....
0
Q.
+5 VOLTS
l' Rcvii
FOUT
FIN
CD
3
i;.
n
CD
52
.
C!
C
1000 PF
5%, SOY
R6
-5Y
·-I
SYNCOUT
SYNCIN1
AS
SYNClN2
1458
SYNCIN3
+::.AI
v
+5VD 3;1
4
PARALLEL
INTERFACE
RXA
47.-SK 1%
Z.
,
~
•
-12 VOLTS
ca
'.0",
N
~
R24MFX
""
~--------~--T---~~C-~--~----3 O~,.
• +5 VOLTS
Cn
c.o
....
+ 10,u:
NOTES. UNLESS OTHERWISE SPECIFIED
25Y
1. RESISTOR VALUES ARE IN OHMS t5% 1/4W
2 CAPACJTOR VALUES ARE IN MICROFARADS ± 20% SOY
~
0.27 "F
o
o
0"
~
(I)
s::::
oz
o
~
><
s::::
o
Do
•
CD
3
R24MFX
2400 bps MONOFAX Modem
PACKAGE DIMENSIONS
I:
.020 TYP.
(.508 MM)
.925
(23.495 MM)
"
1
1.628
(41.35 MM)
:;;
B
g
-~--
I
680
_ _ (17.27 MM)
(1.27 MM)
TYP
I
~ ~
..
-~lr
J
-----.-'1--;·0;;;50 REF
,
(5.0!(M)
~ ~
~
I
L--==--
_I
1__
--.!.
t
.020 REF
TYP
1.50
(3.81 MM)
64-Pln QUIP
3-18
..
.750
-(19.05MM)~
-,IT"
e
g:
c.>'
I
]--I
"fi
'
I
~ ~
R24BKJ
'1'
Rockwell
R24BKJ
2400 bps V.26 bis, Bell 201B/C Modem
tNTRODUCTION
FEATURES
The R24BKJ is a synchronous, serial/parallel, 2400 bps modem
in a single 64-pin quad in-line package (QUIP). The modem is
designed for operation over the public switched telephone network with appropriate line terminations, such as a data access
arrangement, provided externally.
• Single 64-Pin QUIP
• CCITI V.26 bis Alternate A or B
•
•
•
•
•
•
•
The R24BKJ satisfies the telecommunications requirements
specified in CCITI Recommendation V.26 bis Alternate A or B
and Bell 201B/C.
The R24BKJ is optimized for use in compact original equipment
manufacturer (OEM) systems. Its small size and low power consumption offer the user flexibility in creating a 2400 bps modem
customized for specific packaging and functional requirements.
Bell 201B/C
Half-Duplex (2-Wire)
Programmable RTS/CTS Delay
Programmable Dual Tone Generation
Programmable Tone Detection
Dynamic Range: - 43 dBm to 0 dBm
Diagnostic Capability
- Provides Telephone Line Quality Monitoring Statistics
• Equalization
- Automatic Adaptive
- Compromise Cable (Selectable)
• DTE Interface: Two Alternate Ports
- Microprocessor Bus
- CCITI V.24 (RS-232-C Compatible)
• Low Power Consumption: 1W (Typical)
• Programmable Transmit Output Level
• TIL and CMOS Compatible
SVNCIN3
NC
PORI
DGND5
SVNCIN2
NC
HC
DGND3
XTU
XTLO
+5YD
RSO
RS'
RS2
RS.
WRITE
cs
READ
IRQ
DO
0'
02
RXD
D.
TXD
DAOUT
ADIN
DO
OS
D6
RCVl2
CTS
RlSO
D1
DGND2
RCVO
RTS
NC
selKO
PORO
RCI
DCLK
SYNCOUT
HC
DGND1
AGCIN
AGND
-5VA
SVNCIN1
DAIN
ADDUT
AUXI
Four
SCLKIN2
RXIN
AOUT
FIN
TXOUT
DGN04
SCLKIH1
RCVIt
+5VA
CABLE1
He =
CABLE2
NO CONNECTION
R24BKJ 2400 bps V.26 bls/Bell 201B/C Modem
R24BKJ Pin Assignments
Document No. 29200N20
Data Sheet
3-19
Order No. MD20
Rev. 2, January 1989
•
R24BKJ
2400 bps V.26 bis, Bell 201B/C Modem
TECHNICAL CHARACTERISTICS
RECEIVE LEVEL
TONE GENERATION
The receiver circuit of the R24BKJ satisfies all specified performance requirements for received line signal levels from 0 dBm
to - 43 dBm. An external input buffer and filter must be supplied between the receiver analog input (RXA) and the R24BKJ
RXIN pin. The received line signal level is measured at RXA.
Under control of the host processor, the R24BKJ can generate single or dual frequency voice band tones up to 3600 Hz
with a resolution of 0.11 Hz and an accuracy of 0.01 %. The
transmit level and frequency of each tone is independently
programmable.
RECEIVE TIMING
In the receive state, the R24BKJ provides a Data Clock (DClK)
output in the form of a square wave. The low to high transitions
of this output coincide with the centers of received data bits.
The timing recovery circuit is capable of tracking a ± 0.01 % frequency error in the associated transmit timing source. DClK
duty cycle is 50% ± 1%.
TONE DETECTION
Single frequency tones are detected by a programmable filter.
The presence of energy at the selected frequency is indicated
by a bit in the interface memory.
SIGNALING AND DATA RATES
TRANSMIT LEVEL
Signaling/Data Rates
Parameter
Specification
(±0.01%)
Signaling Rate
Data Rate
1200 Baud
2400 bps
The transmitter output level is programmable. An external output buffer and filter must be supplied between the R24BKJ
TXOUT pin and the transmitter analog output (TXA). The default
level at TXA, when sending pseudorandom data, is + 5 dBm
± 1 dB. When driving a 600 ohm load the TXA output requires
a 600 ohm series resistor to provide -1 dBm ± 1 dB to the load.
DATA ENCODING
TRANSMIT TIMING
The 2400 bps data stream is encoded into dibits per CCITT V.26
bis Alternate A or B and Bell 201 B/C.
In the transmit state, the R24BKJ provides a Data Clock (DClK)
output with the following characteristics:
1. Frequency: Data rate of 2400 Hz (±0.01%).
COMPROMISE CABLE EQUALIZERS
2. Duty Cycle: 50% ± 1%.
In addition to the adaptive equalizer, the R24BKJ provides
selectable compromise cable equalizers to optimize performance
over three different lengths of non-loaded cable of 0.4 mm
diameter (1.8 km, 3.6 km, and 7.2 km).
Transmit Data (TXD) must be stable during the 1 microsecond
periods immediately preceding and following the rising edge of
DClK.
Cable Equalizer Nominal Gain
Frequency
(Hz)
700
1500
2000
3000
SYNCHRONIZING SEQUENCE
Gain (dB) Relative t.o 1700 Hz
1.8 km
3.8 km
7.2 km
-0.99
-0.20
-to.15
+ 1.43
-2.39
-0.65
+087
+3.06
The synchronizing sequence of the R24BKJ consists of two
segments: a fixed segment of unscrambled ones, and an open
segment which may be either unscrambled or scrambled ones,
depending on the configuration selected. Both segments are programmable by allowing the synchronizing sequence to be varied
for specific applications.
-3.93
-1.22
+1.90
+4.58
TRANSMITTED DATA SPECTRUM·
TURN-OFF SEQUENCE
The transmitter spectrum is shaped by a square root of 90%
raised cosine filter.
The turn-off sequence consists of approximately 10 ms of
remaining data and scrambled or unscrambled ones at
1200 baud.
The out-of-band transmitter power limitations meet those specified by Part 68 of the FCC's Rules, and typically meet the
requirements of foreign telephone regulatory agencies.
CLAMPING
The following clamps are provided with the R24BKJ:
SCRAMBLER/DESCRAMBLER
1. Received Data (RXD). RXD is clamped to a constant mark
(1) whenever RlSD is off.
The R24BKJ incorporates a self-synchronizing scrambler/
descrambler. This facility is in accordance with CCITT V.27 ter.
The scrambler can be disabled by setting a bit in interface
memory.
2. Received Une Signal Detector (RLSD). RlSD is clamped off
(squelched) whenever RTS is on.
3-20
R24BKJ
2400 bps V.26 bls, Bell 201B/C Modem
RESPONSE TIMES OF CLEAR-TO-SEND (CTS)
A minimum hysteresis action of 2 dB exists between the actual
off-ta-on and on-to-off transition levels. The threshold levels and
hysteresis action are measured with an unmodulated 2100 Hz
tone applied to AXA.
The time between the off-ta-on transition of ATS and the off-taon transition 01 eTS is dictated by the length of the synchronizing
signal. The response time Is programmable. The choice of
response times depends upon the system applicetion: a) limited
protection against line echoes; b) protection given against line
echoes.
POWER
Current
(Max) @25°C
Voltage Tolerence
The time between the on-ta-off transition of ATS and the on-tooff transition of eTS in the data state is a maximum of 2 baud
times for all configurations.
250 mA@ 5.0 Vdc 225 rnA@ 5.0 Vdc
25 mA @ -5.0 Vdc 25 rnA @ -5.0 Vdc
Note: All voltages must have ripple sO.l volts peak-to-peak. If
+5Vdc
-5 Vdc
ALSO turns on whenever energy is detected on the line. The
RLSO off-to-on response time is 10 ±5 ms.
The RLSO on-to-off response time ensures that all valid data
bits have appeared on RXO. The on-to-off response time is
10 ± 5 ms. Aesponse times are measured with a signal at least
3 dB above the actual RLSO on threshold or at least 5 dB below
the actual ALSO off threshold.
ENVIRONMENTAL
Paremeter
I
-
TXD
I
I
DCLK
......
RLSD
r
I
L
Up to 90% noncondansing. or a wei bulb
temperature up to 35°C, whichever is less.
Relative Humidity
CTS
I-..
USRT
(OPTIONAL)
DoC to +60 oC (32°F to 140°F)
- 40°C to + 80°C ( - 40°F to 176°F) (Stored
in suitable antlststlc container).
RTS
I
I
I
$pacIfication
Temperature
Operating
Storage
Receiver threshold is programmable over the range 0 dBm to
- 50 dBm, however, performance may be at a reduced level
when the received signal is less than - 43 dBm.
---
:1:5%
:1:5%
a switching supply is chosen, user may select any frequency
between 20 kHz and 150 kHz so long as no component of the
switching frequency is present outside of the power supply with
an amplitude greater than 500 microvolts peak.
RECEIVED LINE SIGNAL DETECTOR (RLSD)
I
Current
(Max)@100C
-
RXD
CABLE 2
CABLE1
AUXI
XTLO
XTLI
o
...=r
CLOCK
CRYSTAL
J
TXOUT
R24BKJ
MODEM
READ
RXIN
WRITE
DATA BUS (8)
HOST
PROCESSOR
(DTE)
ADDRESS BUS (4)
~
CS
DECODER,_
POR
IRQ
+5
""""",J
+5V
r~
-
-5V
GND
R24BKJ Functional Interconnect Diagram
3-21
-
- } TELEPHONE
LINE
LINE
INTERFACE
•
2400 bps V.26 bis, Bell 201B/C Modem
R24BKJ
INTERFACE CHARACTERISTICS
gates, t~e interface can be made compatible with a wide variety
of microprocessors such as 65,0,0, 68,0,0, or 68,0,0,0.
The modem interface comprises both hardware and software
circuits. Hardware circuits are assigned to specific pins on the
64-pin QUIP. Software circuits are assigned to specific bits in
a 16-byte interface memory.
The microprocessor interface allows a host microprocessor to
change modem configuration, read or write channel data as well
as diagnostic data, and supervise modem operation by means
of software strappable control bits and modem status bits. The
significance of the control and status bits and methods of data
interchange are discussed in the Software Circuits section.
HARDWARE CIRCUITS
Signal names and descriptions of the hardware circuits, including the microprocessor interface, are listed in the R24BKJ Hardware Circuits table; the table column titled 'Type' refers to
designations found in the Digital and Analog Interface Characteristics tables.
V.24 Interface
Seven hardware circuits provide timing, data and control signals for implementing a serial interface compatible with CCITT
Recommendation \/.24. These signals interface directly with circuits using TTL logic levels (,0, + 5 volt). These TTL levels are
suitable for driving the short wire lengths or printed circuitry
normally found within stand-alone modem enclosures or equipment cabinets.
Microprocessor Interface
Sixteen hardware circuits provide address (RSC-RS3), data
(0,0-07), control (CS, READ and WRITE) and interrupt (IRQ)
signals for implementing a parallel interface compatible with an
8,08,0 microprocessor. (Refer to the Microprocessor Interface
Timing Waveforms figure and Microprocessor Interface Timing
Requirements table.) With the addition of a few external logic
In applications where the modem is operated in parallel data
mode only (i.e., where the V.24 signals are unused), all V.24
pins may remain unterminated.
R24BKJ Hardware Circuits
Name
Type
Pin No.
GND
GND
GND
GND
GND
GND
PWR
PWR
PWR
24
22
48
8
29
4
31
11
25
Connect
Connect
Connect
Connect
Connect
Connect
Connect
Connect
Connect
to
to
to
to
to
to
to
to
to
Analog Ground
AGND Ground
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Analog + 5V Power
Digital + 5V Power
Analog - 5V Power
B. MICROPROCESSOR INTERFACE:
07
06
05
04
03
02
01
DO
1I0A
I/OA
I/OA
I/OA
I/OA
IIOA
I/OA
I/OA
~}
50
51
52
53
54
55
56
Data Bus (8 Bits)
RS3
RS2
RSI
RSO
IA
IA
IA
IA
61
62 }
63
64
Register Select (4 Bits)
Select Reg. 0- F
CS
READ
WRITE
IRQ
IA
IA
IA
OB
59
58
60
57
Chip Select
Read Strobe
Write Strobe
Interrupt Request
19
46
17
13
12
18
Data Clock
Request-to-Send
Clear-to-Send
Transmitter Data Signal
Receiver Data Signal
Received Line Signal Detector
32
33
Cable Select 1
Cable Select 2
C. V.24 INTERFACE:
DClK
RTS
CTS
TXD
RXD
RLSD
Pin No.
Description
OC
IB
OC
IB
OC
OC
IC
IC
AA
AB
AC
28
37
26
Connect to Output Op Amp
Connect to Input Op Amp
Auxiliary Analog Input
1I0B
IIOB
R·
W
R'
W
W
W
W
W
W
W
W
W
R'
W
W
W
R'
R'
W
R'
W
43
3
10
9
47
34
16
44
30
38
36
23
14
40
39
15
27
35
20
41
5
1
42
Power-On-Reset Output
Power-On-Reset Input
Connect to Crystal CirCUit
Connect to Crystal Circuit
Receive Mode Output
Connect to RCVO
Connect to RCVO
SWitched Capacitor Clock Output
Connect to SClKO
Connect to SClKO
Smoothing Filter Output
AGC Input
DAC/AGC Data Out
Connect to DAOUT
ADC Output
Connect to ADOUT
Smoothing Filter Output
Connect to FOUT
Sample Clock Output
Connect to SYNCOUT
Connect to SYNCOUT
Connect to SYNCOUT
RC Junction for paR Time Constant
2
6
7
21
45
Do
Do
Do
Do
Do
TXOUT
RXIN
AUXI
F. OVERHEAD
-=
PORO
PORI
XTlO
XTU
RCVO
RCVll
RCVI2
SClKO
SClKINI
SClKIN2
AOUT
AGCIN
DAOUT
DAIN
ADOUT
ADIN
FOUT
FIN
SYNCOUT
SYNCINI
SYNCIN2
SYNCIN3
RCI
G.RESERVED
R'
W
W
R'
R'
D. CABLE EQUALIZER:
CABlEI
CABlE2
Type
E. ANALOG SIGNALS:
A. POWER:
AGND
DGNDI
DGND2
DGND3
DGND4
DGND5
+5 VA
+5VD
-5VA
Name
Description
Not
Not
Not
Not
Not
Connect
Connect
Connect
Connect
Connect
'R = Required overhead connection; no connection to host equipment.
Unused inputs tied to + 5V or ground require individual 10K !l series
resistors.
3-22
R24BKJ
2400 bps V.26 bis, Bell 201B/C Modem
Digital Interface Characteristics
Type
Input
Symbol
Perameter
VIH
Input Voltage, High
VIL
VOH
VOL
liN
IOH
IOL
IL
Ipu
Input Voltage, Low
Output Voltage, High
Output Voltage, Low
Input Current, Leakage
Output Current, High
Output Current, Low
Output Current, Leakage
Pull-up Current
(Short Circuit)
Capacitive Load
Capacitive Drive
Circuit Typa
CL
Co
Input/Output
Output
Unite
IA
IB
IC
OA
V
2.0 min.
2.0 min.
2.0 min
V
V
V
,.A
mA
mA
,.A
,.A
0.8 max.
0.8 max.
0.8 max.
2.4 min.'
0.4 max. 2
OB
OC
0.4 max. 2
0.4 max. 2
1.6 max.
±10 max.
1.6 max.
±2.5 max.
-0.1 max.
1.6 max.
pF
pF
5
-240 max.
-10 min.
5
-240 max.
-10 min.
20
TTL
w/Pull-up
TTL
w/Pull-up
TTL
I/OA
I/OB
2.0 min.
5.25 max.
2.0 min.
0.8 max.
2.4 min.3
0.4 max. s
0.8 max.
2.4 min.'
0.4 max. 2
±12.5 max.
-240 max.
-10 min.
100
TTL
-260 max.
-100 min.
10
40
100
100
100
100
Opan-Drain Open Drain
3 State
Opan-Drain
w/Pull-up Transceiver w/Pull-up
3. I load = -40,.A
4. VIN = 0.4 to 2.4 Vdc, Vee = 5.25 Vdc
5. I load = 0.36 mA
Note.
-100 ,.A
1. I load
2.lIoad - 1.6 mA
=
•
Analog Interface Characteristics
Analog Interface Characteristics
Name
Type
Characterlatlcs
TXOUT
AA
The transmitter output can supply a
maximum of ± 3.03 volts into a load
resistance of 10k 11 minimum. In order to
match to 600 11, an external smoothing
filter with a transfer function of
15726.431(S + 11542.44) and 604 11 series
resistor are required.
RXIN
AUXI
AB
AC
READ
The receiver input impedance is greater
than 1M 11. An external anti aliasing filter
with a transfer function of
19533.88/(S+ 11542.44) is required.
WRITE
RSi
(i
The auxiliary analog input allows aocess
to the transmitter for the purpose of
interfacing with user provided equipment.
Because this is a sampled data input,
any signal above 3600 Hz will cause
aliasing errors. The input impedance is
1 M 11, and the gain to transmitter output
(TXA) is + 5.6 dB ± 1 dB.
= 0-3)
READ
Note: Absolute maximum voltage ratings for analog inputs are:
(-5 VA - 0.3) s VIN S (+5 VA + 0.3)
Microprocessor Interface Timing Requirements
Characteristic
Symbol
Min
CS, RSi setup time prior
to READ or WRITE
TCS
30
ns
TDA
-
-
Data Aocess time after READ
140
ns
Data hold time after READ
TDH
10
50
ns
-
ns
CS, RSi hold time after
READ or WRITE
TCH
10
Write data setup time
TWOS
75
Write data hold time
TWDH
10
TWR
75
WRITE strobe pulse width
Max
(i
Units
=
Di
0-7)
ns
ns
ns
Microprocessor Interface Timing Waveforms
3-23
R24BKJ
2400 bps V.26 bis, Bell 201B/C Modem
Cable Equalizers
When information in these registers is being discussed, the format Z:Q is used. The register is specified by Z(O-F), and the bit
by 0(0-7, 0 .. LSB). A bit is considered to be "on" when set to
a one (1) and "off" when reset to a zero (0).
Modems may be connected by direct wiring, such as leased
telephonll c/!ble or through the public ,switched telephone network, by means of a data access arrangement. In either case,
the modem analog signal is carried by copper wire cabling for
at least some part of its route. The cable characteristics shape
the paSsband response so that the lower frequencies of the passband (300 Hz to 1700 Hz) are attenuated less than the higher
frequencies (1700 Hz to 3300 Hz). The longer the cable the more
pronounced, the effect.
Status/Control Bits
The operation of the R24BKJ is affected by a number of software control inputs. These inputs are written into registers within
the interlace memorY via the host microprocessor bus. Modem
operation is monitored by various software flags that are read
from interface memorY via the host microprocessor bus.
To minimize the impact of this undesired passband shaping, a
compromise equalizer with more attenuation at lower frequencies than at higher frequencies can be placed in series with the
analog signal. The modem includes three such equalizers
designed to compensate for cable distortion.
All status and control bits are defined in the R24BKJ Interface
MemorY Map lable. Bits deSignated by • - ' are reserved for
modem use only and must not be changec;l by the host.
Cable Equalizer Selection
CABLE2
CABLEI
0
0
0
0.0
1
1
1
0
1.8 km
3.6 km
7.2 km
Anyone of the registers may be read or written on any host read
or write cycle, but all eight bits of that register are affected. In
order to read a single bit or a group of bits in a register, the host
processor must mask out unwanted data. When writing a single
bit or group of bits in a register the host processor must perform
a read-modify-write operation. That is, the entire register is read,
the necessarY bits are set or reset in the accumulator of the host,
then the original unmodified bits and the modified bits are written
back into the register of the interlace memorY.
Length of O.4mm Diameter Cable
1
Analog Signals
Three analog signals provide the interface point for telephone
company audio circuits and host audio inputs. Signals TXOUT
'and RXIN require buffering and filtering to be suitable for driving
and receiving the communication channel. Signal AUXI provides
access to the transmitter for summing host audio signals with
the modem analog output.
Configuration Control
Five configurations are available in the R24BKJ modem. The
configuration is selected by writing an B-bit binarY code into the
configuration field (CONF) of the interface memorY. The configuration field consists of bits 7 through 0 of register D. The
code for these bits is shown in the following lable. All other codes
represent invalid states.
The filters required for anti-aliasing on the receiver input and
smoothing on the transmitter output have a single pole located
at 11,542 radians. Although this pole is located within the modem
passband, internal filters' compensate for ils presence and,
therefore, the pole location must not be changed. Some variation from recommended resistor and capacitor values is permitted as long as the pole is not moved, overall gain is preserved,
and the device is not required to drive a load of less than 10k O.
Configuration Codes
CONF
Notice that when reference is made to signals TXA, RXA, and
AUXIN, these signals are not electrically identical to TXOUT,
RXIN, and AUXI. The schematic of the recommended modem
interface circuit illustrates the differences.
Overhead
Scramblerl
Descrambler
Code
Configuration
04-
V.2BB
disabled
44
V.26A
disabled
84
V.26B
enabled
C4
V.26A
enabled
OC
Tone
Not applicable
-Default value at POR with 220 ms synchronizing sequence.
Except for the power-on-reset signal PORO, the overhead
signals are intendad for internal use only. Thevarlous required
Connections are illustrated in the recommended modem interface circuit schematic. No host connections should be made to
overhead signals other than PORO.
When the modem is initialized by power-on-resel, the configuration defaults to V.26B with scrambler disabled 'and 220 ms
synchronizing signal. When the host wants to change configuration, the new code is written to the configuration field and the
SETUP bit (E:3) is set to a one. Once the new configuration takes
effect, the SETUP bit is reset to zero by the modem.
SOFTWARE CIRCUITS
The R24BKJ contains 16 memorY mapped registers to which an'
external (host) microprocessor has access. The host may read
data out of or wrila data into these registers. Refer to the R24BKJ
Host Processor Interface figure.
The information in the interlace memory is serviced by the
modem at 1200 times per second.
3-24
R24BKJ
2400 bps V.26 bis, Bell 201B/C Modem
READ
WRITE
.
A
8
A
J'\
~
f4-
8
"
"
00-07
"
SP
REGISTER F
REGISTER E
··
REGISTER
SELECT
LOGIC
RSO-RS3 4/
/
110
f4-
i~LOGIC~
MAIN
UNIT
SP
BUS
BUS
h...,..
............
·· ··
~
RAM
J
REGISTER 1 j4REGISTER 0
INTERRUPT
LOGIC
IRQ
--
r-
READ
WRITE
LOGIC
I-
INTERFACE MEMORY
R24BKJ Host Processor Interface
R24BKJ Interface Memory Map
I~
7
5
6
4
3
2
1
0
ODIE
-
DDREO
To enable the transmitter parallel mode, TPOM must be set to
a 1. The modem automatically defaults to the serial mode
(TPOM = 0) at power-on. In either transmitter serial or parallel
mode, the R24BKJ is configured by the host processor via the
microprocessor bus.
Register
F
Serial Mode-The serial mode uses a standard V.24 (RS-232-C)
hardware interface (optional USRT) to transfer channel data.
Transmitter data can be sent serially only when TPOM is set to
a zero.
RAMA
IA
E
COlE CDREO
-
SETUP
0
CONF
C
RTSP
B
RX
A
TDET
7
-
6
-
9
8
-
TPDM
FED
-
1
GHIT
COET
-
-
-
5
-
EOFZ PEOF2 RAMW
-
-
-
Parallel Mode-Parallel data is transferred via two registers in
the interface memory. Register 5 (RXCO) is used for receiver
channel data, and Register 4 (TXCO) is used for transmitter channel data. Register 5 is continuously written every eight bit times
when in the receive state. Register 4 is used as the source of
channel transmitter data only when bit C:5 (TPOM) is set to a one
by the host. Otherwise the transm itter reads data from the V.24
interface. Both RTS and RTSP remain enabled, however, regardless of the state of TPOM.
RXCD
4
TXCD
3
DDXM
2
DDXL
1
DDYM
0
DDYL
~
7
6
5
4
3
2
1
When performing parallel data transfer of channel data, the host
and modem can synchronize their operations by handshaking bits
in register E. Bit E:5 (COREQ) is the channel data request bit.
This bit is set to a one by the modem when receiver data is
available in RXCO or when transmitter data is required in TXCO.
Once the host has finished reading RXCO or writing TXCO, the
host processor must reset COREQ by writing a zero to that bit
location.
0
Bit
When set to a one by the host, Bit E:6 (COlE) enables the COREQ
bit to cause an IRQ interrupt when set. While the IRQ line is
driven to a TIL low level by the modem, bit E:7 (IA) is a one.
Channel Data Transfer
Data sent to or received from the data channel may be transferred
between the modem and host processor in either serial or parallel
form. The receiver operates in both serial and parallel mode
simultaneously and requires no mode control bit selection. The
transmitter operates in either serial or parallel mode as selected
by mode control bit C:5 (TPOM).
If the host does not respond to the channel data request within
eight bit times, the RXCO register is over written or the TXCO
register is sent again.
Refer to Channel Data Parallel Mode Control flow chart for recommended software sequence.
3-25
II
2400 bps V.26 bis, Bell 201B/C Modem
R24BKJ
R24BKJ Interface Memory Definitions
Mnemonic
Name
Memory
Location
Description
CDET
Carrier Detector
8:5
The one state of CDET indicates passband energy is being detected, and a training sequence is not
present. CDET goes to one at the start of the data state, and returns to zero at the end of the
received signal. CDET activates one baud time before RLSD and deactivates one baud time after RLSD.
COlE
Channel Data
Interrupt Enable
E:6
When set to a one, COlE enables an IRO interrupt to be generated when the channel data
request bit (CDREQ) is a one.
CDREO
Channel Data
Request
E:5
Parallel data mode handshaking bit. Set to a one when the modem receiver writes data to RXCD,
or the modem transmitter reads data from TXCD. CDREQ must be reset to zero by the host
processor when data service IS complete.
CONF
Configuration
0:0-7
The B-bit field CONF controls the configuration of the modem according to the following table:
Hex Code
0444
84
C4
OC
Configuration
V.26B,
V.26A,
V.26B,
V.26A,
Tone
Bell 201B/C, Scrambler/descrambler disabled
Scrambler/descrambler disabled
Bell 201B/C, Scrambler/descrambler enabled
Scramblerldescrambler enabled
~------~------------------------------------------
-Default value at POR with 220 ms turn-on sequence.
Configuration Definitions
V.261Bell 201-The modem operates as specified in CCITT Recommendation V.26 bis Mernate A
or B, and Bell 201 B/C, at a 2400 bps data rate.
Tone-The modem sends single or dual frequency tones in response to the RTS or RTSP signals.
Tone frequencies and amplitudes are controlled by RAM locations written by the host. When not
transmitting tones the Tone configuration allows detection of single frequency tones by the TDET
bit. The tone detector frequency can be changed by the host by altering the contents of several
RAM locations.
ODIE
Diagnostic Data
Interrupt Enable
E:2
When set to a one, ODIE enables an IRO interrupt to be generated when the diagnostic data
request bit (DDREQ) is a one.
DDREO
Diagnostic Data
Request
E:O
DDREQ goes to a one when the modem reads from or writes to DDYL. DOREa goes to a zero
when the host processor reads from or writes to DDYl. Used for diagnostic data handshaking bit.
DDXL
Diagnostic Data
X Least
2:0-7
Least significant byte of 16-bit word used in reading XRAM locations.
DDXM
Diagnostic Data
X Most
3:0-7
Least significant byte of IS-bit word used in reading XRAM locations.
DDYL
Diagnostic Data
Y Least
0:0-7
Least significant byte of 16-bit word used in reading YRAM locations or writing XRAM and YRAM
locations.
DDYM
Diagnostic Data
Y Most
1:0-7
Most significant byte of 16-bit word used in reading ,YRAM locations or writing XRAM and YRAM
locations.
DEOFZ
Delayed
Equalizer Freeze
C:l
The DEQFZ bit sets the receiver's equalizer in a delayed freeze mode. If DEQFZ=I, the equalizer
will be frozen when a programmable baud count expires after carrier detection. The power-on
default value is SOO ms; a lower number is not recommended since the equalizer adapts slowly
on data.
EOFZ
Equalizer Freeze
C:2
When EQFZ is a one, the adaptive equalizer taps stop updating and remain frozen.
FED
Fast Energy
Detector
B:5,6
FED consists of a 2-bit field that indicates the level of received signal according to the following
code.
Code
o
1
2
3
Energy Level
None
Invalid
Above Turn-off Threshold
Above Turn-on Threshold
While receiving a signal, FED normally alternates between Codes 2 and 3.
3-26
2400 bps V.26 bis, Bell 201B/C Modem
R24BKJ
R24BKJ Interace Memory Definitions (continued)
Mnemonic
Name
Memory
location
Description
GHIT
Gain Hit
B:4
The gain hit bit goes to one when the receiver detects a sudden increase in passband energy
faster than the AGC CircUit can correct. GHIT returns to zero when the AGC output returns to
normal.
IA
Interrupt Active
E:7
IA is a one when the modem IS driving the interrupt request line (IRQ) to a low TIL level.
RAMA
RAM Access
F:0-7
The RAMA register is written by the host when reading or writing diagnostic data. The RAMA
code determines the RAM location with which the diagnostic read or write is performed.
RAMW
RAM Write
C:O
RAMW IS set to a one by the host processor when performing diagnostic writes to the modem
RAM. RAMW is set to a zero by the host when reading RAM diagnostic data.
RTSP
Request to Send
Parallel
C:7
The one state of RTSP beginS a transmit sequence. The modem continues to transmit until RTSP
is turned off and the turn-off sequence has been completed. RTSP parallels the operation of the
hardware RTS control input. These inputs are ORed by the modem.
AXCD
Receiver
Channel Data
5:0-7
RXCD is written to by the modem every eight bit times. ThiS byte of channel data can be read by
the host when the receiver sets the channel data request bit (CDREQ).
RX
Receive State
B:7
RX IS a one when the modem is in the receive state (i.e., not transmitting).
SETUP
Setup
E:3
The host processor must set the SETUP bit to a one when reconfiguring the modem, i.e., when
changing CONF (D·O-7).
TDET
Tone Detected
A'7
The one state of TDET indicates reception of a tone. The filter can be retuned by means of the
diagnostic write routine.
TPDM
Transmitter
Parallel Data
Mode
C:5
When control bit TPDM is a one, the transmitter accepts data for transmission from the TXCD
register rather than the senal hardware data input.
TXCD
Transmitter
Channel Data
4:0-7
The host processor conveys output data to the transmitter In parallel data mode by writing a data
byte to the TXCD register when the channel data request bit (CDREQ) goes to a one. Data is
transmitted as Single bits In V21 or as d,bits In V.27 starting with bit 0 or dibit 0,1.
Diagnostic Data Transfer
These bits are written into interface memory registers 3, 2, 1
and 0 in that order. Registers 3 and 2 contain the most and least
significant bytes of XRAM data, respectively, while registers 1
and 0 contain the most and least significant bytes of YRAM data
respectively.
The modem contains 128 words of random access memory
(RAM). Each word is 32-bits wide. Because the modem is
optimized for performing complex arithmetic, the RAM words
are frequently used for storing complex numbers. Therefore,
each word is organized into a real part (16 bits) and an imaginary
part (16-bits) that can be accessed independently. The portion
of the word that normally holds the real val ue is referred to as
XRAM. The portion that normally holds the imaginary value is
referred to as YRAM. The entire contents of XRAM and YRAM
may be read by the host processor via the microprocessor
interface.
When set to a one, bit C:O (RAMW) causes the modem to
suspend transfer of RAM data to the interface memory, and
instead, to transfer data from interface memory to RAM. When
writing into the RAM, only 16 bits are transferred, not 32 bits
as for a read operation. The 16 bits written in XRAM or YRAM
come from registers 1 and 0, with register 1 being the more
significant byte. Selection of XRAM or YRAM for the destination
is by means of the code stored in the RAMA bits of register F.
When bit F:7 is set to one, the XRAM is selected. When F:7
equals zero, YRAM is selected.
The interface memory acts as an intermediary dUring these host
to signal processor RAM data exchanges. The RAM address
to be read from or written to is determined by the contents of
register F (RAMA). The R24BKJ RAM Access Codes table lists
27 access codes for storage in register F and the corresponding
diagnostic functions. The R24BKJ Diagnostic Data Scaling table
provides scaling information for these diagnostiC functions. Each
RAM word transferred to the interface memory is 32 bits long.
When the host processor reads or writes register 0, the
diagnostic data request bit E:O (DDREQ) is reset to zero. When
the modem reads or writes register 0, DDREQ is set to a one.
When set to a on~ the host, bit E:2 (ODIE) enables the DDREQ
bit to cause an IRQ interrupt when set. While the IRQ line is
driven to a TTL low level by the modem, bit E:7 (IA) goes to a one.
3-27
•
R24BKJ
2400 bps V.26 bls, Bell 201B/C Modem
l-TPDM
l-RTSP
OR
O-RTS
N
O-CDREQ
N
DATA -
TXCD
O-CDREQ
READ RXCD
N
N
N
0 - RTSP
AND
1 -
RTS
Channel Data Parallel Mode Control
3-28
2400 bps V.26 bls, Bell 201B/C Modem
R24BKJ
R24BKJ Diagnostic Data Scaling
R24BKJ RAM Access Codes
Node
Function
RAMA
Reg. No.
Node
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
AGC Gain Word
Average Power
Receiver Sensitivity
Receiver HysteresiS
Equalizer Input
Equalizer Tap Coefficients
Unrotated Equalizer Output
Rotated Equalizer Output
Decision Points
Error Vector
Rotation Angle
Frequency Correction
EQM
Alpha (a)
Beta One ~1)
Beta Two ~2l
Alpha Prime (a')
8eta One Prime (~{)
Beta Two Prime ~2)
Alpha Double Prime (a R )
Beta Double Prime ~')
Output Level
Tone 1 Frequency
Tone 1 Level
Tone 2 Frequency
Tone 2 Level
Checksum
Fixed Synchronizing
Segment
Open Synchronizing
Segment
81
F2
F1
84
58
1B-2A
68
OA
6C
60
87
88
5,7-9
38
B6
B7
43
8E
44
8F
45
02
91
2,3
2,3
2,3
2,3
0,1,2,3
0,1,2,3
0,1,2,3
0,1,2,3
0,1,2,3
0,1,2,3
2,3
2,3
2,3
0,1
0,1
0,1
0,1
0,1
0,1
2,3
2,3
0,1
2,3
0,1
2,3
0,1
0,1
2,3
11
0,1
29
eo
36
37
38
39
3A
Point
1
2
3
4
5
6
7
8
6
10
1
ParameterlScaling
AGe Gain Word (16-bit unsigned).
AGC Gain in dB = 50 - [(AGC Gain Word/64) x 0.D98]
Range: (16COh6 to (7FFF)16' For - 43 dBm Threshold
2.
Average Power (16-bit unsigned)
Post-AGC Average Power in dBm
= 10 Log (Average Power Word12185)
Typical value - (0889)16' corresponding to 0 dBm
Pra-AGC Power In dBm
= (Post-AGC Average Power-AGC Gain)
3
Receiver Senaltlvlty (16-bit twos complement)
On-Number
where: PON
=655.36 (52.38 + PON)
-
Turn-n threshold in dB
PQFF = Turn-off threshold in d8
Convert Off-Number to hexadecimal and store at access
code 84.
3-29
•
R24BKJ
2400 bps V.26 bis, Bell 201B/C Modem
POWER·ON INITIALIZATION
PERFORMANCE
When power is applied to the R24BKJ, a period of 50 to 350 ms
is required for power supply settling. The power-on-reset signal
(POR) remains low during this period. Approximately 10 ms after
the low to high transition of POR, the modem is ready to be
configured, and RTS may be activated. If the 5 Vdc power supply
drops below approximately 3 Vdc for more than 30 msec, the
POR cycle is repeated.
The R24BKJ provides the user with unexcelled high performance.
TYPICAL BIT ERROR RATES
The Bit Error Rate (BER) performance of the modem is specified
for a test configuration conforming to that illustrated in cCln
Recommendation V.56. Bit error rates are measured at a received
line signal level of - 20 dBm.
RECEIVED SIGNAL FREQUENCY TOLERANCE
At POR time the modem defaults to the following configuration:
V.26B, scrambler disabled, serial mode, 221 ms synchronizing
signal, interrupt disabled, RAM access code OA, transmitter
output level set for + 5 dBm at TXA, receiver turn-on threshold
set for -43.5 dBm, receiver turn-off threshold set for -47.0 dBm,
tone 1 and tone 2 set for 0 Hz and 0 volts output, and tone
detector parameters zeroed.
The receiver circuit of the R24BKJ can adapt to received
frequency error of ± 10Hz with less than 0.2 dB degradation in
BER performance.
TYPICAL PHASE JITTER
The modem exhibits a BER of 10-6 or less with a signal-ta-noise
ratio of 12.5 dB in the presence of 15° peak-ta-peak phase jitter
at 150 Hz or with a signal-to-noise ratio of 15 dB in the presence
of 30° peak-ta-peak phase jitter at 120 Hz (scrambler inserted).
POR can be connected to a user supplied power-on-reset signal
in a wire-or c0!!!!ll!!ration. A low active pulse of 31'sec or longer
applied to the POR pin causes the modem to reset. The modem
is ready to be configured 10 msec after the low active pulse is
removed from POR.
An example of the BER performance capabilities is given in the
following diagrams:
V26,2400
V26,2400
I
10- 3
I
10 -3
\
10-'
10-'
....woe
w
....
oe
a:
a:
0
a:
a:
a:
a:
....
....
10- s
10- s
0
a:
a:
w
w
iii
iii
I
10- s
0
5
10
\
10- s
15
20
25
0
SIGNAL TO NOISE RATIO IN DB
5
10
15
20
SIGNAL TO NOISE RATIO IN DB
Typical Bit Error Rate
(Back-to-Back, Level - 20 dBm)
Typical Bit Error Rate
(Unconditioned 3002 Line, Level - 20 dBm)
3-30
25
2400 bps V.26 bis, Bell 201B/C Modem
R24BKJ
The BER performance test set-up is show in the following
diagram:
r-
MODEM
TRANSMITTER
----
3002
LINE
SIMULATOR
SEG FA-1445
r---
IMPAIRMENT
SOURCE
BRADLEY 2A
AND 2B
ATTENUATOR
HP 350D
-
I
I
MODEM
TEST SET
PHOENIX
5000
LEVEL
METER
HP 3552A
MODEM
RECEIVER
I
NOTE
SIGNAL AND NOISE ARE MEASURED WITH 3 KHZ FLAT WEIGHTING.
BER Performance Test Set-up
3-31
•
R24BKJ
2400 bps V.26 bis, Bell 201B/C Modem
APPLICATION
5. Pin ,22 should be tied directly to pin 24 at the R24BKJ
package, Pin 24 should tie directly, by a unique path, to the
common ground point for analog and digital ground.
Recommended Modem Interface Circuit
6. An analog ground plane should be supplied beneath all
analog components, The analog ground plane should
connect to pin 24 and all analog ground points shown in the
recommended circuit diagram.
The R24BKJ is supplied as a 64-pin QUIP device to be designed
into original equipment manufacturer (OEM) circuit boards. The
recommended modem interface circuit and parts list illustrate
the connections and components required to connect the modem
to the OEM electronics.
7. Pins 4, 8, 29, and 48 should tie together at the R24BKJ
package. Pin 48 should tie directly, by a unique path, to the
common ground point for analog and digital ground,
If the auxiliary analog input (pin 26) is not used, resistors R2
and'R3 can be eliminated and pin 26 must be connected to
analog ground (pin 24). When the cable equalizer controls
CABLE1 and CABLE2 are connected to long leads that are
subject to picking up noise spikes, a 3k n series resistor should
be used on each input (Pins 32 and 33) for isolation.
8, A digital ground plane should be supplied to cover the
remaining allocated area. The digital ground plane should
connect to pin 48 and all digital ground points shown in the
recommended circuit diagram plus the crystal-can ground.
9. The R24BKJ package should be oriented relative to the two
ground planes so that the end containing pin 1 is toward the
digital ground plane and the end containing pin 32 is toward
the analog ground plane.
Resistors R4 and R9 can be used to trim the transmit level and
receive threshold to the accuracy required by the OEM
equipment. For a tolerance of ± 1 dB the 1% resistor values
shown are correct for more than 99.8% of the units.
to. As a general rule,
digital signals should be routed on the
component side of the PCB while analog signals are routed
on the solder side, The sides may be reversed to match a
particular OEM requirement.
Typical Modem Interface Parts List
Component
Manufacturer's
Part Number
C3,C5,C7,C9
C2
592CX7Al04M050B
N511BV100JW
Cl
Cll
VI
ZI
A5,A6
C114C33OJ2G5CA
SA405C274MAA
333AI4-002
LMl458N
CML 1110
T86,6K ohm ±1%
5MA434,OK ± 1%
5043CX3AOOOJ
5043CX2M700J
5043CX47KOOJ
5043CX3KOOJ
5043CX1KOOJ
ECEBEF100
SMC50Tl AOM5X12
C124Cl02J5G5CA
IN751D
CAB '/4XF47K5
EA025QKF2370
Determined by IAQ
characteristics
A4
All
Al0
Al
A7
A2,A3
Cl0
C8
C4,C6
CAl
A9
A8
A14
Manufacturer
11. Routing of R24BKJ signals should provide maximum
isolation between noise sources and sensitive inputs, When
layout requirements necessitate routing these signals
together, they should be separated by neutral signals. Refer
to the table of noise characteristics for a list of pins in each
category.
Sprague
San Fernandol
Wescap
Kemet
AVX
Uniden
National
Pin Noise Characteristics
Dale Electronics
Corning Electronics
Mepco Electra
Mepco Electra
Mepco Electra
Mepco Electra
Mepco Electra
Panasonic
United Chern-Con
Kemet
I.T.T.
A-Ohm
Matsushita Electric
Noise Sensitive
Noise Source
High
Low
1
2
5
14
15
20
21
6
7
9
10
12
13
17
18
19
45
46
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
30
38
39
40
41
44
PC Board Layout Considerations
1. The R24BKJ and all supporting analog circuitry, including
the data access arrangement if required, should be located
on the same area of printed circuit board (PCB),
2. All power traces should be at least 0.1 inch width,
3. If power source is located more than approximately 5 inches
from the R24BKJ, a decoupling capacitor of 10 microfarad
or greater should be placed in parallel with C11 near pins 11
and 48.
4. All circuitry connected to pins 9 and 10 should be kept short
to prevent stray capacitance from affecting the oscillator.
3-32
Neutral
3
4
8
11
16
22
24
25
29
31
34
42
43
47
48
Low
High
26
28
32
33
23
27
35
36
37
::D
N
~
m
C
Cl
H"
=~
5%,50V
C2
-=-
10 PF
5%, SOV
V 24
SERIAL
INTERFACE
:::J
Q.
W
e..>
2
46
18
13
19
12
17
•
CD
C6
RXIN
1000 Pf
5%,50V
FOUT
FIN
-5V
R6
86 6K 1 GAl
SYNCOUT
SYNCIN1
SYNCIN2
SYNCIN3
3
(')
TXA
OAIN
ADOUT
+5 VOLTS
:;
+12VOLTS
01 Jl-F
DAOUT
ADIN
CD
CD
:::l.
Rl
C5
Q.
.
CABLE2
JWXiN
C3
TXOUT
RTS
RLSD
TXD
DCLK
RXD
CTS
47 RCVO
34 RCVI1
16 RCVI2
CD
Q.
s:
0
33
~
CD
e..>
CABLE2
POR
CABLE1
6
(')
3
3
32
7
21
:a
CD
0
CABLE1
R9
<16
1458
RXA
Zl
v ,
MICROPROCESSOR
PARALLEL
INTERFACE
•
-12VOLTS
C8
~
(')
N
~
47-5K 1%
o
o
0"
10,F
'a
a'
til
:c::
§;
N
011
L -_ _ _ _ _ _ _ _ _ _ _~----'''''
R24BKJ
•
3 OHM
ClO
+ 10 /iF
10%
25V
NOTES UNLESS OTHERWISE SPECIFIED
1 Rt;SISTOR VALUES ARE IN OHMS ±5% 114W
2 CAPACITOR VALUES ARE IN MICROFARADS ± 20% SOV
I
C11
027 Jl-F
+S VOLTS
0)
0"
pi"
m
~
N
o
......
~
:s:
o
Co
CD
3
II
2400 bps V.26 bis, Bell 201B/C Modem
R24BKJ
PACKAGE DIMENSIONS
1:
.020 TYP.
(.508 MM)
"
I
I
:IE
"
Z
~
.200
III
(5.08 MM)
W
~'I
:
"
f? ..~
Y. Y.
<>'
§ ~
ci
-Y.
-y.
I
~ I
==---r
J
~ .020 REF
t
'---~-~0;;'50 REF
680
_(17·27MM)
..
-,rr-I--'''~''.·=:JH
H -
1.628
(41.35 MM)
:J
925
(23.495 MM)
1-4-
(1.27 MM)
TYP
1.50
(381 MM)
64·Pin QUIP
3·34
TYP
,I
Y. Y.
R48MFX
MONOFAX'" Modems
'1'
R48MFX
4800 bps MONOFAXTM Modem
Rockwell
INTRODUCTION
FEATURES
The R48MFX MONOFAX 48 is a synchronous, serial/parallel,
4800 bps modem in a single 64-pin quad in-line package (QUIP).
The modem is designed for operation over the public switched
telephone network with appropriate line terminations, such as
a data access arrangement, provided externally.
• Single 64-Pin QUIP
• CCITT V.27 ter, T.30, V.21 Channel 2, T.4
• Group 3 Facsimile Transmission/Reception
•
•
•
•
•
The R48MFX satisfies the telecommunications requirements
specified in CCITT Recommendation V.27 ter, T.4 and the binary
signaling capabilities of Recommendation T.30.
•
The R48MFX is optimized for use in compact Group 3 facsimile
machines. Its small size and low power consumption offer the
user flexibility in creating a 4800 bps modem customized for
specific packaging and functional requirements.
"" MONOFAX
IS
a trademark
•
•
•
•
of Rockwell International
SYNCIN3
ASO
Ne
RS1
RS2
AS3
PORI
DGNOS L_
Half-Duplex (2-Wire)
Programmable Dual Tone Generation
Programmable Tone Detection
Dynamic Range: - 43 dBm to 0 dBm
Diagnostic Capability
- Provides Telephone Line Quality Monitoring Statistics
Equalization
- Automatic Adaptive
- Compromise Cable (Selectable)
DTE Interface: Two Alternate Ports
- Microprocessor Bus
- CCITT V.24 (RS-232-C Compatible)
Low Power Consumption: 1W (Typical)
Programmable Transmit Output Level
TTL and CMOS Compatible
WRITE
SVNCIN2
cs
Ne
Ne
READ
IRQ
DGND3
00
01
XTU
XYlO
+SVD
02
03
O.
OS
06
D7
AXC
TXO
DAOUT
ADIN
RCVl2
DGN02
CTS
RevO
RLSO
RTS
OCLK
Ne
SYNCOUT
Ne
selKO
PORC
DGND1
Rei
AGCIN
AGND
SVNCINl
-SVA
OAIN
AUXI
ADOUT
SCLKIN2
FOUT
RXIN
TXOUT
AQUT
FIN
RCYI1
DGND4
SCLKIN1
+SVA
CA8LE1
CABLE2
Ne = NO CONNECTION
R48MFX Pin Assignments
Document No_ 29200N19
R48MFX 4800 bps MONOFAX Modem
Data Sheet
3-35
Order No. MD19
Rev. 1, January 1989
•
4800 bps MONOFAX Modem
R48MFX
TECHNICAL CHARACTERISTICS
SCRAMBLER/DESCRAMBLER
The R48MFX incorporates a self-synchronizing scrambler/
descrambler. This facility is in accordance with CCITT V.27 ter.
The scrambler can be disabled by setting a bit in interface
memory.
TONE GENERATION
Under control of the host processor, the R48MFX can generate single or dual frequency voice band tones up to 4800 Hz
with a resolution of 0.15 Hz and an accuracy of 0.01 %. The
transmit level and frequency of each tone is independently
programmable.
RECEIVE LEVEL
The receiver circuit of the R48MFX satisfies all specified performance requirements for received line signal levels from 0 dBm
to - 43 dBm. An external input buffer and filter must be supplied between the receiver analog input (RXA) and the R48MFX
RXIN pin. The received line signal level is measured at RXA.
TONE DETECTION
Single frequency tones are detected by a programmable filter.
The presence of energy at the selected frequency is indicated
by a bit in the interface memory.
RECEIVE TIMING
In the receive state, the R48MFX provides a Data Clock (DCll<)
output in the form of a square wave. The low to high transitions
of this output coincide with the centers of received data bits.
The timing recovery circuit is capable of tracking a ± 0.01 % frequency error in the associated transmit timing source. DClK
duty cycle is 50% ± 1%.
SIGNALING AND DATA RATES
Signaling/Data Rates
Configuration
Parameter
Specification
(±0.01%)
V.27
Signaling Rate
Data Rate
Signaling Rate
Data Rate
1600 Baud
4800 bps
1200 Baud
2400 bps
Signaling Rate
Data Rate
300 Baud
300 bps
V.21
TRANSMIT LEVEL
The transmitter output level is programmable. An external output buffer and filter must be supplied between the R48MFX
TXOUT pin and the transmitter analog output (TXA). The default
level at TXA is + 5 dBm ± 1 dB. When driving a 600 ohm load
the TXA output requires a 600 ohm series resistor to provide
- 1 dBm ± 1 dB to the load.
DATA ENCODING
TRANSMIT TIMING
At 1600 baud, the 4800 bps data stream is encoded into tribits
per CCITT V.27.
In the transmit state, the R48MFX provides a Data Clock (DCll<)
output with the following characteristics:
1. Frequency: Selected data rate of 4800, 2400 or 300 Hz
(±O.Ol%).
2. Duty Cycle: 50% ± 1%.
Transmit Data (TXD) must be stable during the 1 microsecond
periods immediately preceding and following the rising edge of
DClK.
At 1200 baud, the 2400 bps data stream is encoded into dibits
per CCITT V.27 ter.
At 300 baud, the data stream is 300 bps FSK per CCITT V.21
channel 2.
COMPROMISE CABLE EQUALIZERS
In addition to the adaptive equalizer, the R48MFX provides selectable compromise cable equalizers to optimize performance over
three different lengths of non-loaded cable of 0.4 mm diameter
(1.8 km, 3.6 km, and 7.2 km).
TURN-ON SEQUENCE
Seven turn-on sequences are generated by the R48MFX, as
defined in the following table:
Turn-On Sequences'
Cable Equalizer Nominal Gain
Frequency
(Hz)
700
1500
2000
3000
Gain (dB) Relative to 1700 Hz
7.2 km
1.8 km
3.6 km
-0.99
-2.39
-3.93
-0.65
-1.22
-0.20
+0.15
+0.87
+1.90
+ 1.43
+3.06
+4.58
No.
1
Bit
Rate
(bps)
RTSOnCTS On
Time'
(ms)
Comments
300
<14
No Training Sequence, No Echo Tone
Long Train, No Echo Tone
2
2400
943
3
2400
1148
Long Train, with Echo Tone2
TRANSMITTED DATA SPECTRUM
4
2400
<10
Training Disabled
When operating at 1600 baud, the transmitter spectrum is
shaped by a square root of 50% raised cosine filter.
5
4800
708
Long Train, No Echo Tone
6
4800
913
Long Train, with Echo Tone2
When operating at 1200 baud, the transmitter spectrum is
shaped by a square root of 90% raised cosine filter.
7
4800
<10
Training Disabled
Notes:
1. Assumes the receiver is in idle; if not, add receiver turn-ofi time.
For
use
on
lines
with
protection
against talker echo.
2.
The out-of-band transmitter power limitations meet those specified by Part 68 of the FCC's Rules, and typically meet the
requirements of foreign telephone regulatory agencies.
3-36
R48MFX
4800 bps MONOFAX Modem
response time is 10 ± 5 ms. Response times are measured with
a signal at least 3 dB above the actual RLSO on threshold or
at least 5 dB below the actual RLSO off threshold.
TURN-OFF SEQUENCE
Five turn-off sequences are generated by the R48MFX:
Turn-Off Sequences
No.
Bit Rate (bps)
1
2
3
4
5
300
2400
2400
4800
4800
RTS Off-Energy Oil
Time (rna)
Silence
Time (rna)
<7
7.5
7.5-10
5.4
5.4-S.7
0
20
20
20
20
serial
parallel
serial
parallel
The RLSO on-to-off response time ensures that all valid data
bits have appeared on RXO.
Receiver threshold is programmable over the range 0 dBm to
-50 dBm, however, performance may be at a reduced level
when the received signal is less than - 43 dBm.
A minimum hysteresis action of 2 dB exists between the actual
off-to-on and on-to-off transition levels. The threshold levels and
hysteresis action are measured with an unmodulated 2100 Hz
tone applied to RXA.
CLAMPING
The following clamps are provided with the R48MFX:
1. Received Data (RXD). RXO is clamped to a constant mark
(1) whenever RLSO is off.
2. Received Line Signal Detector (RLSD). RLSO is clamped off
(squelched) whenever RTS is on.
POWER
VoltagelTolerancelCurrent (Max) @ 25°CICurrent (Max) @ 60°C
+5 Vd~1
-5 Vdc
The time between the on-ta-off transition of RTS and the on-tooff transition of eTS in the data state is a maximum of 2 baud
times for all configurations.
Parameter
Temperature
Operating
Storage
CTS
h
I
l
TXD
I
DCLK
h
RLSD
I
RXD
XTLI
R48MFX
MONOFAX
MODEM
RXIN
DATA BUS (8)
ADDRESS BUS (4)
. h CS
DECODER 1'"'_
POR
IRQ
+5
CLOCK
- . - CRYSTAL
TXOUT
WRITE
~
o
J
READ
HOST
PROCESSOR
(DTE)
Specification
CABLE1
XTLO
r
-<:5
5.0 Vdc
-5.0 Vdc
AUXI
I
L
@
@
CABLE2
,..,
~
t-'
USRT
(OPTIONAL)
I 22525 mA
mA
RTS
I
I
5.0 Vdc
-5.0 Vdc
ooe to + sooe (32°F to 140°F)
- 40 0 e to + 80 0 e (- 40°F to 176°F) (Stored
in suitable antistatic container).
Relative Humidity Up to 90% noncondensing, or a wet bulb
temperature up to 35°e, whichever is less
RLSO turns on at the end of the training sequence. If training
is not detected at the receiver, the RLSO off-to-on response time
is 801 bauds (V.27) or < 10 ms (300 bps). The RLSO on-to-off
I
@
@
ENVIRONMENTAL
RECEIVED LINE SIGNAL DETECTOR (RLSD)
---
I 25025 mA
mA
Note: All voltages must have ripple ,.;0.1 volts peak·to-peak. If
a switching supply is chosen, user may select any frequency
between 20 kHz and 150 kHz so long as no component of the
sWitching frequency IS present outside of the power supply with
an amplitude greater than 500 microvolts peak.
RESPONSE TIMES OF CLEAR-TO-SEND (CTS)
The time between the off-ta-on transition of RTS and the off-toon transition of eTS is dictated by the bit rate, the length of the
training sequence, and the presence of the echo tone. The TurnOn Sequences table on page 2 lists the eTS response times.
r
± 5%
± 5%
.Av"'v
J
+5V
-5V
5
GND
R48MFX Functional Interconnect Diagram
3-37
-
- } TELEPHONE
LINE
LINE
INTERFACE
•
4800 bps MONOFAX Modem
R48MFX
INTERFACE CHARACTERISTICS
gates, the interface can be made compatible with a wide variety
of microprocessors such as 6500, 6800, or 68000.
The modem interface comprises both hardware and software
circuits. Hardware circuits are assigned to specific pins on the
64-pin QUIP. Software circuits are assigned to specific bits in
a l6·byte interface memory.
The microprocessor interface allows a host microprocessor to
change modem configuration, read or write channel data as well
as diagnostic data, and supervise modem operation by means
of software strappable control bits and modem status bits. The
significance of the control and status bits and methods of data
interchange are discussed in the Software Circuits section.
HARDWARE CIRCUITS
Signal names and descriptions of the hardware circuits, including
the microprocessor interface, are listed in the R48MFX Hard·
ware Circuits table; the table column titled 'Type' refers to
designations found in the Digital and Analog Interface Charac·
teristics tables.
V.24 Interface
Seven hardware circuits provide timing, data and control signals
for implementing a serial interface compatible with CCITT
Recommendation V.24. These signals interface directly with cir·
cuits using TTL logic levels (0, +5 VOlt). These TTL levels,are
suitable for driving the short wire lengths or printed circuitry
normally found within stand·alone modem enclosures or equipment cabinets.
Microprocessor Interface
Sixteen hardware circuits provide address (RSO-RS3), data
(00·07), control (CS, READ and WRITE) and interrupt (IRQ)
signals for implementing a parallel interface compatible with an
8080 microprocessor. (Refer to the Microprocessor Interface
Timing Waveforms figure and Microprocessor Interface Timing
Requirements table.) With the addition of a few external logic
In applications where the modem is operated in parallel data
mode only (i.e., where the V.24 signals are unused), all V.24
pins may remain unterminated.
R48MFX Hardware Circuits
Name
Type
Pin No.
Description
A. POWER:
AGND
DGNDI
DGND2
DGND3
DGND4
DGND5
+5VA
+5VD
-5VA
GND
GND
GND
GND
GND
GND
"PWR
PWR
PWR
24
22
48
8
29
4
31
11
25
Connect
Connect
Connect
Connect
Connect
Connect
Connect
Connect
Connect
to
to
to
to
to
to
to
to
to
Analog Ground
AGND Ground
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Analog + 5V Power
Digital + 5V Power
Analog - 5V Power
B. MICROPROCESSOR INTERFACE:
D7
D6
D5
04
D3
D2
Dl
DO
RS3
RS2
RSI
RSO
CS
READ
WRITE
IRQ
1I0A
1I0A
1I0A
1I0A
1I0A
IIOA
1I0A
1I0A
IA
IA
IA
IA
IA
IA
IA
OB
:}
51
52
53
54
55
56
61 }
62
63
Data Bus (8 Bits)
Register Select (4 Bits)
Select Reg. O-F
64
59
58
60
57
ChIp Select
Read Strobe
Write Strobe
Interrupt Request
C. V.24 INTERFACE:
DCLK
RTS
CTS
TXD
RXD
RlSD
Name
OC
IB
OC
IB
OC
OC
19
CABLE2
IC
IC
AA
TXOUT
RXIN
AUXI
Pin No.
Description
AB
AC
28
37
26
Connect to Output Op Amp
Connect to Input Op Amp
AUXIliary Analog Input
43
3
10
9
47
34
16,
Power·On·Reset Output
Power·On·Reset Input
Connect to Crystal Circuit
Connect to Crystal Circuit
Receive Mode Output
Connect to RCVO
Connect to RCVO
Switched CapacItor Clock Output
Connect to SClKO
Connect to SClKO
Smoothing Fi~er Output
AGC Input
DAC/AGC Data Out
Connect to OAOUT
ADC Output
Connect to ADOUT
Smoothing Filter Output
Connect to FOUT
Sample Clock Output
Connect to SYNCOUT
Connect to SYNCOUT
Connect to SYNCOUT
RC Junction for POR Time
Constant
F.OVERHEAD
PORO
PORI
XTlO
XTLI
RCVO
RCVI1
RCVI2
SClKO
SClKINI
SClKIN2
AOUT
AGCIN
DAOUT
DAIN
ADOUT
ADIN
FOUT
FIN
SYNCOUT
SYNCINI
SYNCIN2
SYNCIN3
RCI
1I0B
1I0B
R'
R'
R'
R'
R'
R'
R'
R'
R'
R'
R'
R'
R'
R'
R'
R'
R'
R'
R'
R'
R'
44
30
3B
36
23
14
40
39
15
27
35
20
41
5
1
42
17
13
12
18
Data Clock
Request·to-Send
Clear·lo-Send
Transmitter Data Signal
Receiver Data Signal
Received Line Signal Detector
32
Cable Select 1
'R = Required overhead connection; no connection to host equipment.
Cable Select 2
Unused inputs tied to + 5V or ground require individual 1OK 0 senes
resistors
46
G.RESERVED
R'
R'
R'
R'
R'
D. CABLE EQUALIZER:
CABlEI
Type
E. ANALOG SIGNALS:
33
3·38
2
6
7
21
45
Do Not Connect
Do Not Connect
Do Not Connect
Do Not Connect
Do Not Connect
R48MFX
4800 bps MONOFAX Modem
Digital Interface Characteristics
Type
Input
Symbol
Parameter
V,H
Input Voltage, High
V,l
VOH
VOL
liN
IOH
IOl
Il
Ipu
Input Voltage, Low
Output Voltage, High
Output Voltage, Low
Input Current, Leakage
Output Current, High
Output Current, Low
Output Current, Leakage
Pull-up Current
(Short Circuit)
Capacitive Load
Capacitive Drive
Circuit Type
Cl
Co
Output
Unite
IA
IB
IC
OA
V
2.0 min.
2.0 min.
2.0 min
V
V
V
pA
mA
mA
pA
pA
0.8 max.
0.8 max.
0.8 max.
2.4 min.l
0.4 max. 2
OB
InputlOutput
OC
0.4 max. 2
0.4 max. 2
1.6 max.
±10 max.
1.6 max.
±2.5 max.
-0.1 max.
1.6 max.
pF
pF
5
-240 max.
-10 min.
5
-240 max.
-10 min.
20
TTL
w/Puil-up
TTL
w/Puil-up
TTL
Notes
1. I load = -1oopA
2. I load = 1.6 mA
IIOA
IIOB
2.0 min.
5.25 max.
2.0 min.
0.8 max.
2.4 min.3
0.4 max. 5
0.8 max.
2.4 min. 1
0.4 max. 2
±12.5 max.
-240 max.
-10 min.
100
TTL
-260 max.
-100 min.
10
40
100
100
100
100
Open-DratO Open Drain
Open-Drain
3 State
w/Puil-up Transceiver w/Puil-up
3. I load = -40 pA
4. V,N = 0.4 to 2.4 Vdc, Vee = 525 Vdc
5. I load = 0 36 mA
II
Analog Interface Characteristics
Analog Interface Characteristics
Name
lYpe
TXOUT
AA
Chal8cterlstics
The transmitter output can supply a
maximum of ± 3.03 volts into a load
resistance of 10k 0 minimum. In order to
match to 600 0, an external smoothing
filter with a transfer functIon of
15726.43/(S + 11542.44) and 604 0 series
resistor are required.
RXIN
AB
The receiver Input impedance is greater
than 1M O. An external antialiaslng filter
with a transfer function of
19533.88/(S + 11542.44) is required.
AUXI
AC
The auxiliary analog input allows access
to the transmitter for the purpose of
interlacing wrth user provided equipment.
Because this is a sampled data input, any
signal above 4800 Hz will cause aliasing
errors. The input Impedance IS 1M 0, and
the gain to transmitter output (TXA) IS
+5.6dB ±1 dB.
READ
WRITE
RSi
(I
Note: Absolute maximum voltage ratings for analog Inputs are: ( - 5
VA - 0.3) :s V,N :S (+5 VA + 0.3)
= 0-3)
READ
Microprocessor Interface Timing Requirements
Characteristic
Symbol
Min
Max
Unite
TCS
30
TDA
TDH
-
-
ns
140
10
50
ns
ns
TCH
10
75
10
75
-
ns
TWOS
TWDH
TWR
-
ns
ns
-
ns
01
(i
es,
RSI setup lime prior
to READ or WRITE
Data Access time after READ
Data hold time after READ
es, RSi hold lime after
READ or WRITE
Write data setup time
Write data hold time
WRITE strobe pulse width
= 0-7)
Microprocessor Interface Timing Waveforms
3-39
R48MFX
4800 bps MONOFAX Modem
Cable Equalizers
data out of or wnte data Into these registers. Refer to the R48MFX
Host Processor Interface figure.
Modems may be connected by direct wiring, such as leased
telephone cable or through the public sWitched telephone network, by means of a data access arrangement In either case,
the modem analog signal is carried by copper wire cabling for
at least some part of ItS route. The cable characteristics shape
the passband response so that the lower frequencies of the passband (300 Hz to 1700 Hz) are attenuated less than the higher
frequencies (1700 Hz to 3300 Hz). The longer the cable the more
pronounced the effect
When information In these registers IS being discussed, the format Z:O is used. The register IS specified by Z(O-F), and the bit
by 0(0-7, 0 = LSB). A bit is considered to be "on" when set to
a one (1) and "off" when reset to a zero (0).
Status/Control Bits
The operation of the R48MFX IS affected by a number of software control inputs. These inputs are wntten into registers Within
the interface memory via the host microprocessor bus. Modem
operation is monitored by vanous software flags that are read
from Interface memory via the host microprocessor bus.
To minimize the impact of this undesired passband shaping, a
compromise equalizer with more attenuation at lower frequencies than at higher frequencies can be placed In series with the
analog signal. The modem includes three such equalizers
designed to compensate for cable distortion.
All status and control bits are defined in the R48MFX Interface
Memory Map table. Bits deSignated by , - ' are reserved for
modem use only and must not be changed by the host.
Cable Equalizer Selection
CABLE2
CABLEl
Length of O.4mm Diameter Cable
0
0
1
1
0
1
0
1
00
18 km
36 km
72 km
Anyone of the registers may be read or written on any host read
or wnte cycle, but all eight bits of that register are affected. In
order to read a single bit or a group of bits in a register, the host
processor must mask out unwanted data. When writing a single
bit or group of bits in a register the host processor must perform
a read-modify-write operation. That is, the entire register is read,
the necessary bits are set or reset In the accumulator of the host,
then the original unmodified bits and the modified bits are written
back into the register of the interface memory.
Analog Signals
Three analog signals provide the Interface pOint for telephone
company audio circuits and host audio inputs. Signals TXOUT
and RXIN require buffering and filtering to be suitable for dnving
and receiving the communication channel. Signal AUXI provides
access to the transmitter for summing host audio signals with
the modem analog output.
Configuration Control
Four configuratIOns are available in the R48MFX modem: V.27
4800/2400 bps long train, V.21, and Tone. The configuration is
The filters required for anti-aliasing on the receiver input and
smoothing on the transmitter output have a Single pole located
at 11,542 radians. Although this pole is located within the modem
passband, internal filters compensate for its presence and,
therefore, the pole location must not be changed. Some vanation from recommended resistor and capacitor values is permitted as long as the pole is not moved, overall gain is preserved,
and the deVice is not required to drive a load of less than 10k O.
selected by wntlng an 8-bit binary code into the configuration
field (CONF) of the Interface memory. The configuration field
consists of bits 7 through 0 of register D. The code for these
bits IS shown in the following table. All other codes represent
invalid states.
Configuration Codes
CONFCode
Notice that when reference is made to signals TXA. RXA, and
AUXIN, these signals are not electncally Identical to TXOUT,
RXIN, and AUXI. The schematiC of the recommended modem
interface circuit illustrates the differences.
00
04
06'
08
Configuration
V.21
V 27, 2400 Long Tram
V 27, 4800 Long Tram
Tone Mode
, Default value at POR
Overhead
Except for the power-on-reset signal PORO, the overhead
signals are intended for Internal use only. The vanous required
connections are illustrated in the recommended modem interface circuit schematic. No host connections should be made to
overhead signals other than PORO.
When the modem is initialized by power-on-reset, the configuration defaults to V.27 4800 bps. When the host wants to change
configuration, the new code is wntten to the configuration field
and the SETUP bit (E:3) is set to a one. Once the new configuration takes effect, the SETUP bit is reset to zero by the modem.
SOFTWARE CIRCUITS
The informatIOn in the Interface memory IS serviced by the
modem at the baud rate (V.27 and V.21), 9600 times per second
(tone generator), or 1600 times per second (tone detector).
The R48MFX contains 16 memory mapped registers to which
an external (host) microprocessor has access. The host may read
3-40
4800 bps MONOFAX Modem
R48MFX
READ
WRITE
r-
READ
WRITE
LOGIC
8
~
8
.....
r
0-:-07
SP
I/O
BUS
f4REGISTER E f4-
REGISTER F
··
REGISTER
SELECT
LOGIC
RSO_RS3 4 /
/
IRQ
I
r-
A
·· ··
INTERRUPT
LOGIC
REGISTER 1
I+-
REGISTER 0
f4-
~LOGIC~
MAIN
UNIT
............
SP
BUS
~
RAM
I
--
INTERFACE MEMORY
R48MFX Host Processor Interface
To enable the transmitter parallel mode, TPDM must be set to
a 1. The modem automatically defaults to the serial mode
(TPDM = 0) at power-on. In either transmitter serial or parallel
mode, the R48MFX is configured by the host processor via the
microprocessor bus.
R48MFX Interface Memory Map
~
7
5
6
4
3
2
1
0
-
DDREQ
Register
F
Serial Mode-The serial mode uses a standard V.24 (R8-232-C)
hardware interface (optional USRT) to transfer channel data.
Transmitter data can be sent serially only when TPDM is set to
a zero.
RAMA
IA
E
COlE COREQ
-
0
SETUP ODIE
CONF
RTSP
C
B
AX
A
TDET
EPT
TPDM TOIS EQSV EQFZ SOlS RAMW
FED
-
9
-
8
-
-
7
-
-
6
-
-
GHIT
-
-
CDET
-
-
-
-
-
-
-
-
-
-
-
-
PN
-
5
AXCD
4
TXCD
3
DDXM
2
DDXl
1
DDYM
0
DDYl
V-
7
6
5
4
3
-
-
-
-
-
-
-
2
1
Parallel Mode-Parallel data is transferred via two registers in
the interface memory. Register 5 (RXCD) is used for receiver
channel data, and Register 4 (TXCD) is used for transmitter channel data. Register 5 is continuously written every eight bit times
when in the receive state. Register 4 is used as the source of
channel transmitter data only when bit C:5 (TPDM) is set to a one
by the host. Otherwise the transmitter resds data from the V.24
interface. Both RTS and RTSP remain enabled, however, regardless of the state of TPDM.
-
When performing parallel data transfer of channel data, the host
and modem can synchronize their operations by handshaking bits
in register E. Bit E:5 (COREa) is the channel data request bit.
This bit is set to a one by the modem when receiver data is
available in AXCD or when transmitter data is required in TXCO.
Once the host has finished reading AXCD or writing TXCO, the
host processor must reset COREa by writing a zero to that bit
location.
0
Bit
When set to a on~ the host, Bit E:6 (COlE) enables the COREQ
bit to cause an IRa interrupt when set. While the IRQ line is
driven to a TTL low level by the modem, bit E:7 (IA) is a one.
Channel Data Transfer
Data sent to or received from the data channel may be transferred
between the modem and host processor in either serial or parallel
form. The receiver operates in both serial and parallel mode
simultaneously and requires no mode control bit selection. The
transmitter operates in either serial or parallel mode as selected
by mode control bit C:5 (TPDM).
If the host does not respond to the channel data request within
eight bit times, the RXCD register is over written or the TXCD
register is sent again.
Refer to Channel Oata Parallel Mode Control flow chart for rec0mmended software sequence.
3-41
4800 bps MONOFAX Modem
R48MFX
R48MFX Interface Memory Definitions
Mnemonic
Name
Memory
Location
Description
CDET
Carrier Detector
8:5
The one state of CDET indicates passband energy is being detected, and a training sequence is
not present. CDET goes to one at the start of the data state, and returns to zero at the end of the
received signal. CDET activates one baud time before RLSD and deactivates one baud time after
RLSD.
COlE
Channel Data
Interrupt Enable
E:6
When set to a one, COlE enables an IRQ interrupt to be generated when the channel data
request bit (CDREQ) is a one.
CDREQ
Channel Data
Request
E:5
Parallel data mode handshaking bit. Set to a one when the modem receiver writes data to RXCD,
or the modem transmitter reads data from TXCD. CDREQ must be reset to zero by the host
processor when data service is complete.
CONF
Configuration
0:0-7
The 8-bit field CONF controls the configuration of the modem according to the following table:
Hex Code
00
04
06
08
All else
Configuration
V.21
V.27, 2400 Long Train
V.27, 4800 Long Train (Default)
Tone
Invalid
Configuration Definitions
1I.21-The modem operates as a CCITT T.30 compatible 300 bps FSK modem having
characteristics of the CCITT V.21 Channel 2 modulation system.
Tone-The modem sends single or dual frequency tones in response to the RTS or RTSP signals.
Tone frequencies and amplitudes are controlled by RAM locations written by the host. When not
transmitting tones the Tone configuration allows detection of single frequency tones by the TDET
bit. The tone detector frequency can be changed by the host by altering the contents of several
RAM locations.
1I.27-The modem is compatible with CCITT Recommendation V.27 ter.
ODIE
Diagnostic Data
Interrupt Enable
E:2
When set to a one, ODIE enables an IRQ interrupt to be generated when the diagnostic data
request bit (DDREQ) is a one.
DDREQ
Diagnostic Data
Request
E:O
DDREQ goes to a one when the modem reads from or writes to DDYL. DDREQ goes to a zero
when the host processor reads from or writes to DDYL. Used for diagnostic data handshaking bit.
DDXL
Diagnostic Data
X Least
2:0-7
Least significant byte of 16-bit word used in reading XRAM locations.
DDXM
Diagnostic Data
X Most
3:0-7
Least significant byte of 16-bit word used in reading XRAM locations.
DDYL
Diagnostic Data
Y Least
0:0-7
Least significant byte of 16-bit word used in reading YRAM locations or writing XRAM and YRAM
locations.
DDYM
Diagnostic Data
Y Most
1:0-7
Most significant byte of 16-bit word used in reading YRAM locations or writing XRAM and YRAM
locations.
EPT
Echo Protector
Tone
C:6
When EPT is a one, an unmodulated carner is transmitted for 185 ms followed by 20 ms of no
transmitted energy at the beginning of the training sequence. EPT is not active if TDIS is on.
EQFZ
Equalizer Freeze
C:2
When EQFZ is a one, the adaptive equalizer taps stop updating and remain frozen.
EQSV
Equalizer Save
C:3
When EQSV is a one, the adaptive equalizer taps are not zeroed when reconfiguring the modem
or when entering the training state. Adaptive equalizer taps are also not updated during training.
FED
Fast Energy
Detector
8:5,6
FED consists of a 2-bit field that indicates the level of received signal according to the following
code.
Code
Energy Level
o
None
1
Invalid
2
Above Turn-off Threshold
Above Turn-on Threshold
3
While receiving a signal, FED normally alternates between Codes 2 and 3.
3-42
4800 bps MONOFAX Modem
R48MFX
R48MFX Interace Memory Definitions (continued)
Mnemonic
Name
Memory
location
Description
GHIT
Gain Hit
B:4
The gain hit bit goes to one when the receiver detects a sudden Increase in passband energy
faster than the AGC circuit can correct. GHIT returns to zero when the AGC output returns to
normal.
IA
Interrupt Active
E:7
IA is a one when the modem is driving the interrupt request line (IRQ) to a low TTL level.
PN
Period N
8:3
PN sets to a one at the start of the received PN sequence. PN resets to zero at the start of the
received scrambled ones. PN does not operate when TDIS is set to a one.
RAMA
RAM Access
F:0-7
The RAMA register is written by the host when reading or writing diagnostic data. The RAMA
code determines the RAM location with which the diagnostic read or write is performed.
RAMW
RAM Write
C:O
RAMW is set to a one by the host processor when performing diagnostic writes to the modem
RAM. RAMW is set to a zero by the host when reading RAM diagnostic data.
RTSP
Request to Send
Parallel
C:7
The one state of RTSP begins a transmit sequence. The modem continues to transmit until RTSP
is turned off and the turn-off sequence has been completed. RTSP parallels the operation of the
hardware RTS control input. These inputs are ORed by the modem.
RXCD
Receiver Channel
Data
5:0-7
RXCD is written to by the modem every eight bit times. This byte of channel data can be read by
the host when the receiver sets the channel data request bit (CDREQ).
RX
Receive State
B:7
RX is a one when the modem is in the receive state (i.e., not transmitting).
SOlS
Scrambler Disable
C:l
When SOlS is a one, the scrambler/descrambler is disabled. When SOlS is a zero, the
scrambler/descrambler is enabled (default).
SETUP
Setup
E:3
The host processor must set the SETUP bit to a one when reconfiguring the modem, I.e., when
changing CONF (0:0-7).
TDET
Tone Detected
A:7
The one state of TDET indicates reception of a tone. The filter can be retuned by means of the
diagnostic write routine.
TOIS
Training Disable
C:4
If TDIS is a one in the receive state, the modem is prevented from entering the training phase. If
TDIS is a one when RTS or RTSP go active, the generation of a training sequence is prevented at
the start of transmission.
TPDM
Transmitter Parallel
Data Mode
C:5
When control bit TPDM is a one, the transmitter accepts data for transmission from the TXCD
register rather than the serial hardware data input.
TXCD
Transmitter
Channel Data
4:0-7
The host processor conveys output data to the transmitter in parallel data mode by writing a data
byte to the TXCD register when the channel data request bit (CDREQ) goes to a one. Data is
transmitted as single bits in V.21 or as dibits in V.27 starting with bit 0 or dibit 0,1.
Diagnostic Data Transfer
These bits are written into interface memory registers 3, 2, 1
and 0 in that order. Registers 3 and 2 contain the most and least
significant bytes of XRAM data, respectively, while registers 1
and 0 contain the most and least significant bytes of YRAM data
respectively.
The modem contains 128 words of random access memory
(RAM). Each word is 32-bits wide. Because the modem is
optimized for performing complex arithmetic, the RAM words
are frequently used for storing complex numbers. Therefore,
each word is organized into a real part (16 bits) and an imaginary
part (16-bits) that can be accessed independently. The portion
of the word that normally holds the real value is referred to as
XRAM. The portion that normally holds the imaginary value is
referred to as YRAM. The entire contents of XRAM and YRAM
may be read by the host processor via the microprocessor
interface.
When set to a one, bit C:O (RAMW) causes the modem to suspend transfer of RAM data to the interface memory, and instead,
to transfer data from interface memory to RAM. When writing
into the RAM, only 16 bits are transferred, not 32 bits as for a
read operation. The 16 bits written in XRAM or YRAM come from
registers 1 and 0, with register 1 being the more significant byte.
Selection of XRAM or YRAM for the destination is by means of
the code stored in the RAMA bits of register F. When bit F:7
is set to one, the XRAM is selected. When F:7 equals zero,
YRAM is selected.
The interface memory acts as an intermediary during these host
to signal processor RAM data exchanges. The RAM address to
be read from or written to is determined by the contents of
register F (RAMA). The R48MFX RAM Access Codes table lists
27 access codes for storage in register F and the corresponding
diagnostic functions. The R48MFX Diagnostic Data Scaling table
provides scaling information for these diagnostic functions. Each
RAM word transferred to the interface memory is 32 bits long.
When the host processor reads or writes register 0, the
diagnostic data request bit E:O (DDREQ) is reset to zero. When
the modem reads or writes register 0, DDREQ is set to a one.
When set to a one by the host, bit E:2 (ODIE) enables the DDREQ
bit to cause an IRQ interrupt when set. While the IRQ line is
driven to a TTL low level by the modem, bit E:7 (IA) goes to a one.
3-43
•
R48MFX
4800 bps MONOFAX Modem
l-TPDM
N
l-RTSP
OR
O-RTS
y
N
O-CDREQ
N
DATA -
TXCD
O-CDREQ
READ RXCD
N
N
N
0 - RTSP
AND
1 -
RTS
Channel Data Parallel Mode Control
3-44
R48MFX
4800 bps MONOFAX Modem
R48MFX RAM Acea.. Coda.
Node
Function
RAMA
1
2
AGC Gain Word
Average Power
Receiver Sensitivity
Receiver Hysteresis
equalizer Input
Equalizer Tap Coefficients
Unrotated Equalizer Output
Rotated Equalizer Output
Decision Points
Error Vector
Rotation Angle
Frequency Correction
EQM
Alpha (a)
Beta One (13,)
Beta 1Wo (1321
Alpha Prime (a')
Beta One Prime (13{)
Beta Two Prime (132)
Alpha Double Prime (a")
Beta Double Prime (13")
Output Level
Tone 1 Frequency
Tone 1 Level
Tone 2 Frequency
Tone 2 Level
Checksum
rrT
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
91
47
84
63
23-32
73
OA
74
75
B3
8B
89
38
39
3A
3B
3C
3D
B8
B9
43
8E
44
SF
45
02
R48MFX Diagnostic Date Scaling (Cont'd)
Reg. No.
Node
5,7-9
2,3
2,3
0,1
2,3
0,1,2,3
0,1,2,3
0,1,2,3
0,1,2,3
0,1,2,3
0.1.2,3
2,3
2,3
2,3
0,1
0,1
0,1
0,1
0,1
0,1
2,3
2,3
0,1
2,3
0,1
2,3
0,1
0,1
ParameterJScaling
All be_band slgnel point nodes (i.e., Equalizer Input,
Unrotated Equalizer Output, Rotated Equalizer Output, and
Decision Points) are 32·bit. complex, twos complement
numbers.
Value (Hex)
Point
1
2
3
4
5
6
7
8
6
X
1000
OCOO
F400
E300
E300
F400
OCOO
1000
y
Y
OCOO
1000
1000
OCOO
F400
E300
E300
F400
83
82
84
81
85
88
X
86
87
Equalizer Tap Coefficients (32·blt, complex, twos
complement)
Complex numbers with X - real part, Y - Imaginary part'
X and Y range: 0000 to (FFFF)'6 representing ± full scale
in hexadecimal twos complement.
10
Error Vector (32·bit, complex, twos complement)
Complex number with X = real part,
Y = imaginary part.
X and Y range: (6000)'6 to (7FFF)'6
11
Roletlon Angle (l6-bit, signed, twos complement)
Rotation Angle in deg. = (Rot. Angle Word/65,536) x 360
12
Frequency Correction (16·bit signed twos complement)
Frequency correction in Hz
= (Freq. Correction Word/65,536) x Baud Rate
Range: (FCOO)'6 to (400),6 representing ± la75 Hz
R48MFX Diagnostic Date Scaling
Node
1
ParameterlScellng
13
EQM (l6-bit, unsigned)
Filtered squared magnitude of error vector.
Proportionality to BER determined by particular application.
14-21
Filter liming Parameters (l6-bit unsigned) Alpha, Beta One,
Beta Two, Alpha Prime, Beta One Prime, Beta Two Prime,
Alpha Double Prime, and Beta Double Prime are set according
to instructions in application note 668.
22
Output Level (l6-bit unsigned)
Output Number = 27573.6 [10(PoI20))
Po = output power in dBm with series 600 ohm resistor
into 600 ohm load.
Convert Output Number to hexadecimal and store at
access code 43
24
and
26
Tone 1 and TOna 2 Levels
Calculate the power of each tone independently by using
the equation for Output Number given at node 22. Convert
these numbers to hexadecimal then store at access codes
44 and 45. Total power transmitted in tone mode is the
result of both tone 1 power and tone 2 power.
23
and
25
Tone 1 and 2 Frequency (l6-bit unsigned)
N = 6.82rrT (Frequency in Hz)
Convert N to hexadecimal then store at access code 8E
or 8F.
27
Checksum (l6-bit unsigned)
ROM checksum number determined by revision level.
AGe Gain Word (l6-bit unsigned).
AGC Gain in dB = 50 - [(AGC Gain Word/54) x 0.098)
Range: (16C0),6 to (7FFF)'6' For - 43 dBm Threshold
2.
Averegs Power (16-bit unsigned)
3
Post-AGC Average Power in dBm
- 10 Log (Average Power Word/2185)
Typical Value = (0889),6, corresponding to 0 dBm
Pre-AGC Power in dBm
= (Post·AGC Average Power-AGC Gain)
Receiver Sensitivity (16-bit twos complement)
On·Number =655.36 (52.38+ PON)
where: PON = Turn-on threshold in dB
Convert On·Number to hexadecimal and store at access
code tfl
4
Receiver HysteresiS (l6-blt twos complement)
Off·Number = [65.4 (1()A»)212
where:
A = (POFF - PON - 0.5)120
PON = Turn-on threshold in dB
POFF = Turn-off threshold in dB
Convert Off·Number to hexadecimal and store at access
code 84.
3·45
•
4800 bps MONOFAX Modem
R48MFX
POWER·ON INITIALIZATION
TYPICAL BIT ERROR RATES
When power is applied to the R48MFX, a period of 50 to 350 ms
is required for power supply settling. The power-on-reset signal
(POR) remains low during this period. Approximately 10 ms after
the low to high transition of POR, the modem is ready to be
configured, and RTS may be activated. If the 5 Vdc power supply
drops below approximately 3 Vdc for more than 30 msec, the
POR cycle is repeated.
The Bit Error Rate (BER) performance of the modem is specified
for a test configuration conforming to that illustrated in CCITT
Recommendation V.56. Bit error rates are measured at a
received line signal level of -20 dBm.
RECEIVED SIGNAL FREQUENCY TOLERANCE
The receiver circuit of the R48MFX can adapt to received
frequency error of ± 10Hz with less than 0.2 dB degradation
in BER performance.
At POR time the modem defaults to the following configuration:
V.27/4800 bps, serial mode, training enabled, echo protector
tone enabled, interrupts disabled, RAM access code OA,
transmitter output level set for + 5 dBm at TXA, receiver turnon threshold set for -43.5 dBm, receiver turn-off threshold set
for -47.0 dBm, tone 1 and tone 2 set for 0 Hz and 0 volts output,
and tone detector parameters zeroed.
TYPICAL PHASE JITTER
At 4800 bps, the modem exhibits a BER of 10-6 or less with a
signal-to-noise ratio of 19 dB in the presence of 15° peak-topeak phase jitter at 60 Hz.
POR can be connected to a user supplied power-on-reset signal
in a wire-or configuration. A low active pulse of 31'sec or longer
applied to the POR pin causes the modem to reset. The modem
is ready to be configured 10 msec after the low active pulse is
removed from POR.
PERFORMANCE
At 2400 bps, the modem exhibits a BER of 10-6 or less with a
signal-to-noise ratio of 12.5 dB in the presence of 15° peak-topeak phase jitter at 150 Hz or with a signal-to-noise ratio of 15 dB
in the presence of 30° peak-to-peak phase jitter at 120 Hz
(scrambler inserted).
Whether functioning as a V.27 ter or V.21 type modem, the
R48MFX provides the user with unexcelled high performance.
An example of the BER performance capabilities is given in the
following diagrams:
FSK
V.27,2400 V.27, 4800
/SK
I
10- 3
\
\
I
V.27,2400
V.27,4800
,
I
10- 3
I
\
/
\
10-'
10-'
w
w
l-
l-
a:
a:
0
a:
a:
a:
a:
0
a:
a:
w
e(
e(
1\
w
I-
I-
iii
iii
10- 5
10- 5
\
10- 6
0
\
5
10
15
20
SIGNAL TO NOISE RATIO IN DB
\
10- 6
0
25
5
\
10
15
20
SIGNAL TO NOISE RATIO IN DB
Typical Bit Error Rate
(Back-to-Back, Level - 20 dBm)
Typical Bit Error Rate
(Unconditioned 3002 Line, Level - 20 dBm)
3-46
25
4800 bps MONOFAX Modem
R48MFX
The SER performance test set-up is show in the following
diagram:
MODEM
TRANSMITTER
r--
3002
LINE
SIMULATOR
SEG FA-1445
r--
IMPAIRMENT
SOURCE
ATTENUATOR
BRADLEY 2A f - - HP 350D
AND2B
I
I
MODEM
TEST SET
PHOENIX
5000
LEVEL
METER
HP 3111A
MODEM
RECEIVER
J
NOTE
SIGNAL AND NOISE ARE MEASURED WITH 3 KHZ FLAT WEIGHTING.
BER Performance Test Set-up
3-47
•
4800 bps MONOFAX Modem
R48MFX
APPLICATION
5. Pin 22 should be tied directly to pin 24 at the R48MFX
package. Pin 24 should tie directly, by a unique path, to the
common ground point for analog and digital ground.
Recommended Modem Interface Circuit
6. An analog ground plane should be supplied beneath all
analog components. The analog ground plane should
connect to pin 24 and all analog ground points shown in the
recommended circuit diagram.
The R48Mi=)( is supplied as a 64-pin QUIP device to be designed
into original equipment manufacturer (OEM) circuit boards. The
recommended modem interface circuit and parts list illustrate
the connections and components required to connect the modem
to the OEM electronics.
7. Pins 4, 8, 29, and 48 should tie together at the R48MFX
package. Pin 48 should tie directly, by a unique path, to the
common ground pOint for analog and digital ground.
If the auxiliary analog input (pin 26) is not used, resistors R2
and R3 can be eliminated and pin 26 must be connected to
analog ground (pin 24). When the cable equalizer controls
CABLEl and CABLE2 are connected to long leads that are
subject to picking up nOise spikes, a 3k !l series resistor should
be used on each input (Pins 32 and 33) for isolation.
8. A digital ground plane should be supplied to cover the
remaining allocated area. The digital ground plane should
connect to pin 48 and all digital ground points shown in the
recommended circuit diagram plus the crystal-can ground.
9. The R48MFX package should be oriented relative to the two
ground planes so that the end containing pin 1 is toward the
digital ground plane and the end containing pin 32 is toward
the analog ground plane.
Resistors R4 and R9 can be used to trim the transmit level and
receive threshold to the accuracy required by the OEM
equipment. For a tolerance of ± 1 dB the 1°1b resistor values
shown are correct for more than 99.8% of the units.
10. As a general rule, digital signals should be routed on the
component side of the PCB while analog signals are routed
on the solder side. The sides may be reversed to match a
particular OEM requirement.
Typical Modem Interface Parts List
Component
C3,C5,C7,C9
Cl1
VI
ZI
R5,R6
R4
Rll
RIO
Rl
R7
R2,R3
Cl0
C8
C4,C6
CRI
R9
R8
R14
Manufacturer's
Part Number
592CX7Rl04M050B
SA405C274MAA
333RI4-002
LMI458N
CML 1110
T66.6K ohm ±1%
5MA434.0K ± 1%
5043CX3ROOOJ
5043CX2M700J
5043CX47KOOJ
5043CX3KOOJ
5043CXl KOOJ
ECEBEF100
SMC50TtROM5X12
C124Cl02J5G5CA
IN751 0
CRB ';'XF47K5
ER025QKF2370
Determined by IRQ
characteristics
Manufacturer
11. Routing of R48MFX signals should provide maximum
isolation between noise sources and sensitive inputs. When
layout requirements necessitate routing these signals
together, they should be separated by neutral signals. Refer
to the table of noise characteristics for a list of pins in each
category.
Spra9ue
AVX
Uniden
National
Dale Electronics
Corning Electronics
Mepco Electra
Mepco Electra
Mepco Electra
Mepco Electra
Mepco Electra
Panasonic
United Chern-Con
Kemet
I.T.T.
R-Ohm
Matsushita Electric
Pin Noise Characteristics
Noise Source
PC Board Layout Considerations
Low
Neutral
Low
High
1
2
5
14
15
20
21
30
38
39
40
41
6
7
9
10
12.
13
17
18
19
45
46
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
3
4
8
11
16
22
24
25
29
31
34
42
43
47
48
26
28
32
33
23
27
35
44
1. The R48MFX and all supporting analog circuitry, including
the data access arrangement if required, should be located
on the same area of printed circuit board (PCB).
2. All power traces should be at least 0.1 inch width.
3. If power source is located more than approximately 5 inches
from the R48MFX, a decoupling capaCitor of 10 microfarad
or greater should be placed in parallel with Cll near pins 11
and 48.
4. All circuitry connected to pins 9 and 10 should be kept short
to prevent stray capacitance from affecting the oscillator.
3-48
Noise Sensitive
High
36
37
:a
~
CO
3:
~
r
.L
c::II
T
10 XTLO
POR
PORI
Yl
11.98135
MHZ
POR0t:
CABLEl
32
CABLEl
CABLE2 33
-iiiiiN
CABLE2
AOUT
AGelN
:II
~
to
AUXI
•
TXOUT
3
3
~
:J
V 2'
DAOUT
SERIAL
INTERFACE
DAIN
ADOUT
Il.
Il.
RXIN
FOUT
FIN
;s:
....
<0
0
Il.
+5 VOLTS
3
~
0
~f
5%, SOY
R6
86 6K 1%
SYNCOUT
SYNCIN1
SVNCIN2
SYNCIN3
~
:I.
to
1000 PF
-sv
~
..
co
ADIN
~
Cf
+12VOLTS
TXA
0
R9
<16
+svoffi
MICROPROCESSOR
v
+5VA 31
Rei 42
PARALLEL
RXA
47.-SK 1%
,
., -12VOLTS
eB
~ 1.0,F
INTERFACE
c
;::;:
~
CD
Q
R11
el0
+ 10 "F
NOTES:
1.
2.
3.
Q
"..
3 OHM
R48MFX
10%
UNLESS OTHERWISE SPECIFIED
RESISTOR VALUES ARE IN OHMS ±5% 1/4W
CAPACITOR VALUES ARE IN MICROFARADS ±20% SOV
Cl AND C2 NOT USED
2SV
..
e11
J:
0.27 "F
+5 VOLTS
C"
"0
o
3:
oz
o
~
><
s::
o
Q.
(II
3
II
R48MFX
4800 bps MONOFAX Modem
PACKAGE DIMENSIONS
1:
.020 TYP.
(.508 MM)
I
-.-
1.628
(41.35 MM)
:I!
~
~
t
(5·08
,
e 5~
~ ~
i:
_£11
I
_
(1.27 MM)
TYP
J
I
~,
_I
64·Pin QUIP
3·50
1_
1.50
(3.81 MM)
M),
I
£ £
I! I 1~.020REF
-£--
------.-'1-;·0;;;50 REF
.925
(23.495 MM)
.200
e
~'
<.>'
.680
(17.27 MM)
"
I 1~(19.::OMM)-
TYP
R48PCJ
Integral Modems
'1'
Rockwell
R48PCJ
4800 bps PC Communication Modem
INTRODUCTION
FEATURES
The Rockwell R48PCJ is a synchronous 4800 bits per second
(bps) modem in a single 64-pin quad in-line package (QUIP).
It is designed for operation over the public switched telephone
network through line terminations provided by a data access
arrangement (DAA).
• Single 64-Pin QUIP
• CCITT V.27 ter, T.30, V.21 Channel 2, T.4
• Group 3 Facsimile Transmission/Reception
•
•
•
•
•
The modem satisfies the telecommunications requirements
specified in CCID recommendations V.27 ter, T.4 and the binary
signaling capabilities of T.30. The R48PCJ can operate at speeds
of 4800, 2400 and 300 bps, and includes the V.27 ter short training sequence option. Employing advanced signal processing
techniques, the R48PCJ can transmit and receive data even
under extremely poor line conditions.
• Equalization
- Automatic Adaptive
- Compromise Cable (Selectable)
User programmable features allow the modem operation to be
tailored to support a wide range of functional requirements. The
R48PCJ is optimized for incorporation into an original equipment
manufacturer (OEM) developed system. The modem's single
device package, low power consumption, and serial/parallel host
interface simplify system design and allow direct installation on
the host module.
SYNCIN3
NC
PORI
DGND5
SYNCIN2
NC
NC
DGND3
XTLI
XTLO
+SVD
RXO
TXD
DAOUT
ADIN
RCVl2
CTS
RLSD
DCLK
SYNCOUT
NC
DGND1
AGCIN
AGND
-5VA
AUXI
FOUT
TXOUT
DGND4
SCLKIN1
+5VA
CABLE1
Ne
Half-Duplex (2-Wire)
Programmable Dual Tone Generation
Programmable Tone Detection
Dynamic Range: - 43 dBm to 0 dBm
Diagnostic Capability
- Provides Telephone Line Quality Monitoring Statistics
• DTE Interface: Two Alternate Ports
- Microprocessor Bus
- CCITT V.24 (RS-232-C Compatible)
• Low Power Consumption: 1W (Typical)
• Programmable Transmit Output Level
• TTL and CMOS Compatible
RSO
RS1
RS2
RS3
WRITE
cs
READ
IRQ
00
10
11
12
13
14
15
16
17
01
02
03
04
05
D6
D7
OGN02
RCYO
RTS
NC
SClKO
PORO
RCI
SYNCIN1
DAIN
ADOUT
SCLKIN2
RXIN
AOUT
FIN
RCVl1
CABlE2
= NO CONNECTION
R48PCJ Pin Assignments
Document No. 29200N19
R48PCJ 4800 bps Modem
Data Sheet
3-51
Order No. MD21
Rev. 2, January 1989
•
R48PCJ
4800 bps PC Communication Modem
TECHNICAL CHARACTERISTICS
RECEIVE LEVEL
TONE GENERATION
The receiver circuit of the R48PCJ satisfies all specified performance requirements for received line signal levels from 0 dBm
to - 43 dBm. An external input buffer and filter must be supplied between the receiver analog input (RXA) and the R48PCJ
RXIN pin. The received line signal level is measured at RXA.
Under control of the host processor, the R48PCJ can generate single or dual frequency voice band tones up to 4800 Hz
with a resolution of 0.15 Hz and an accuracy of 0.01 %. The
transmit level and frequency of each tone is independently
programmable.
RECEIVE TIMING
TONE DETECTION
In the receive state, the R48PCJ provides a Data Clock (DCll<)
output in the form of a square wave. The low to high transitions
of this output coincide with the centers of received data bits.
The timing recovery circuit is capable of tracking a ± 0.Q1 % frequency error in the associated transmit timing source. DClK
duty cycle is 50% ± 1%.
Single frequency tones are detected by a programmable filter.
The presence of energy at the selected frequency is indicated
by a bit in the interface memory.
SIGNALING AND DATA RATES
SignalinglData Rates
Configuration
Parameter
V.27
Signaling Rate
Data Rate
Signaling Rate
Data Rate
V.21
Signaling Rate
Data Rate
TRANSMIT LEVEL
Specification
(±O.Ol%)
1600
4800
1200
2400
The transmitter output level is programmable. An external output buffer and filter must be supplied between the R48PCJ
TXOUT pin and the transmitter analog output (TXA). The default
level at TXA is + 5 dBm ± 1 dB. When driving a 600 ohm load
the TXA output requires a 600 ohm series resistor to provide
- 1 dBm ± 1 dB to the load.
Baud
bps
Baud
bps
300 Baud
300 bps
TRANSMIT TIMING
DATA ENCODING
At 300 baud, the data stream is 300 bps FSK per CCITI V.21
channel 2.
In the transmit state, the R48PCJ provides a Data Clock (DCll<)
output with the following characteristics:
1. Frequency: Selected data rate of 4800, 2400 or 300 Hz
(±0.01%).
2. Duty Cycle: 50% ± 1%.
Transmit Data (TXD) must be stable during the 1 microsecond
periods immediately preceding and following the rising edge of
DClK.
COMPROMISE CABLE EQUALIZERS
TURN-ON SEQUENCE
In addition to the adaptive equalizer, the R48PCJ provides selectable compromise cable equalizers to optimize performance over
three different lengths of non-loaded cable of 0.4 mm diameter
(1.8 km, 3.6 km, and 7.2 km).
Eleven turn-on sequences are generated by the R48PCJ, as
defined in the following table:
At 1600 baud, the 4800 bps data stream is encoded into tribits
per CCITI V.27.
At 1200 baud, the 2400 bps data stream is encoded into dibits
per CCITI V.27 ter.
Turn-On Sequences
No.
Bit
Rate
(bps)
RTSOnCTS On
Time'
(ms)
1
300
<14
Cable Equalizer Nominal Gain
Frequency
(Hz)
700
1500
2000
3000
Gain (dB) Relative to 1700 Hz
1.B km
3.6km
7.2 km
-0.99
-2.39
-3.93
-0.20
-0.65
-1.22
+0.15
+0.87
+1.90
+ 1.43
+3.06
+4.58
Comments
No Training Sequence, No Echo Tone
2
2400
66
3
2400
271
Short Train, with Echo Tone2
TRANSMITTED DATA SPECTRUM
4
2400
943
Long Train, No Echo Tone
When operating at 1600 baud, the transmitter spectrum is
shaped by a square root of 50% raised cosine filter.
5
2400
1148
Long Train, with Echo Tone2
6
2400
<10
Training Disabled
When operating at 1200 baud, the transmitter spectrum is
shaped by a square root of 90% raised cosine filter.
7
4800
50
8
4800
255
Short Train, with Echo Tone2
Long Train, No Echo Tone
The out-of-band transmitter power limitations meet those specified by Part 68 of the FCC's Rules, and typically meet the
requirements of foreign telephone regulatory agencies.
SCRAMBLER/DESCRAMBLER
Short Train, No Echo Tone
Short Train, No Echo Tone
9
4800
708
10
4800
913
Long Train, with Echo Tone2
11
4800
<10
Training Disabled
Notes:
1. Assumes the receiver is in idle; if not, add receiver turn-off time.
2. For use on lines with protection against talker echo.
The R48PCJ incorporates a self-synchronizing scramblerl
descrambler. This facility is in accordance with CCITI V.27 ter. The
scrambler can be disabled by setting a bit in interface memory.
3-52
R48PCJ
4800 bps PC Communication Modem
TURN-OFF SEQUENCE
<10 ms (300 bps). The RLSO on-to-off response time is
10 ± 5 ms. Response times are measured with a signal at least
3 dB above the actual RLSO on threshold or at least 5 dB below
the actual RLSO off threshold.
Five turn-off sequences are generated by the R48PCJ:
Turn~ffSequences
No.
Bit Rate (bps)
1
2
3
4
5
300
2400
2400
4800
4800
RTS Off-Energy Off
Time (ms)
Silence
Time (ms)
The RLSO on-to-off response time ensures that all valid data
bits have appeared on RXO.
<7
7.5
7.5-10
5.4
5.4-6.7
0
20
20
20
20
Receiver threshold is programmable over the range 0 dBm to
-50 dBm, however, performance may be at a reduced level
when the received signal is less than - 43 dBm.
serial
parallel
serial
parallel
A minimum hysteresis action of 2 dB exists between the actual
off-to-on and on-to-off transition levels. The threshold levels and
hysteresis action are measured with an unmodulated 2100 Hz
tone applied to RXA.
CLAMPING
The following clamps are provided with the R48PCJ:
1. Received Data (RXD). RXO is clamped to a constant mark
(1) whenever RLSO is off.
2. Received Line Signal Detector (RLSD). RLSO is clamped off
(squelched) whenever RTS is on.
POWER
VoltagelTolerancelCurrent (Max) @ 25°C1Current (Max) @ 60°C
I
The time between the off-to-on transition of RTS and the off-toon transition of CTS is dictated by the bit rate, the length of the
training sequence, and the presence of the echo tone. The Tuman Sequences table on page 2 lists the CTS response times.
The time between the on-to-off transition of RTS and the on-tooff transition of CTS in the data state is a maximum of 2 baud
times for all configurations.
ENVIRONMENTAL
Parameter
Temperature
Operating
Storage
RECEIVED LINE SIGNAL DETECTOR (RLSD)
RLSO turns on at the end of the training sequence. If training
is not detected at the receiver, the RLSO off-to-on response time
is 801 bauds (V.27 long train), 481 bauds (V.27 short train), or
r
---
RTS
I
I
I
I
I
I
L
Relative Humidity
~
O°C to + 60°C (32°F to 140°F)
-55°C to +150°C (-67°F to +302°F)
(Stored in suitable antistatic container)
Up to 90% noncondenslng, or a wet bulb
temperature up to 35°C, whichever IS less
CABLE2
~
CABLE 1
TXD
AUXI
USRT
(OPTIONAL)
DCLK
I
RLSD
f:>
,.,
RXD
I.
--0
XTLO
XTLI
TXOUT
RXIN
WRITE
DATA BUS (8)
ADDRESS BUS (4)
DECODER
CS
POR
IRQ
+5
o
CLOCK
---.- CRYSTAL
J
READ
~
Specification
CTS
R48PCJ
MODEM
HOST
PROCESSOR
(DTE)
I
270 rnA @ 5.0 Vdc
245 rnA @ 50 Vdc
+5 Vd~1 ±5%
-5 Vdc
±5%
25 rnA @ -5.0 Vdc
25 rnA @ -50 Vdc
Note: All voltages must have npple ,,; 0 1 volts peak-to· peak. If
a switching supply IS chosen, user may select any frequency
between 20 kHz and 150 kHz so long as no component of the
switching frequency is present outside of the power supply with
an amplitude greater than 500 microvolts peak.
RESPONSE TIMES OF CLEAR-TO-SEND (CTS)
J
+SV
=~
-SV
GND
R48PCJ Functional Interconnect Diagram
3-53
-
- } TELEPHONE
LINE
LINE
INTERFACE
•
R48PCJ
4800 bps PC Communication Modem
INTERFACE CHARACTERISTICS
gates, the interface can be made compatible with a wide variety
of microprocessors such as 6500, 6800, or 68000.
The modem interface comprises both hardware and software
circuits. Hardware circuits are assigned to specific pins on the
64-pin QUIP. Software circuits are assigned to specific bits in
a 16-byte interface memory.
The microprocessor interface allows a host microprocessor to
change modem configuration, read or write channel data as well
as diagnostic data, and supervise modem operation by means
of software strappable control bits and modem status bits. The
significance of the control and status bits and methods of data
interchange are discussed in the Software Circuits section.
HARDWARE CIRCUITS
Signal names and descriptions of the hardware circuits, including
the microprocessor interface, are listed in the R48PCJ Hardware
Circuits table; the table column titled 'Type' refers to designations found in the Digital and Analog Interface Characteristics
tables.
V.24 Interface
Seven hardware circuits provide timing, data and control signals
for implementing a serial interface compatible with CCITT
Recommendation V.24. These signals interface directly with circuits using TTL logic levels (0, + 5 volt). These TTL levels are
suitable for driving the short wire lengths or printed circuitry
normally found within stand-alone modem enclosures or equipment cabinets.
Microprocessor Interface
Sixteen hardware circuits provide address (RSO-RS3), data
(00-07), control (CS, READ and WRITE) and interrupt (IRQ)
signals for implementing a parallel interface compatible with an
8080 microprocessor. (Refer to the Microprocessor Interface
Timing Waveforms figure and Microprocessor Interface Timing
Requirements table.) With the addition of a few external logic
In applications where the modem is operated in parallel data
mode only (i.e., where the V.24 signals are unused), all V.24
pins may remain unterminated.
R48PCJ Hardware Circuits
Name
Type
Pin No.
Description
A. POWER:
AGND
DGND1
DGND2
DGND3
DGND4
DGND5
+5 VA
+5 VD
-5 VA
GND
GND
GND
GND
GND
GND
PWR
PWR
PWR
24
22
48
8
29
4
31
11
25
Connect
Connect
Connect
Connect
Connect
Connect
Connect
Connect
Connect
to
to
to
to
to
to
to
to
to
Analog Ground
AGND Ground
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Analog + 5V Power
Digital + 5V Power
Analog - 5V Power
B. MICROPROCESSOR INTERFACE:
07
06
05
04
03
02
01
DO
I/OA
I/OA
I/OA
I/OA
I/OA
I/OA
IIOA
I/OA
~}
50
51
52
53
54
55
56
Data Bus (8 Bits)
RS3
RS2
RS1
RSO
IA
IA
IA
IA
61 }
62
63
64
Register Select (4 Bits)
Select Reg. O-F
CS
READ
WRITE
IRQ
IA
IA
IA
OB
59
58
60
57
Chip Select
Read Strobe
Write Strobe
Interrupt Request
19
46
17
13
12
18
Data Clock
Request-to-Send
Clear-to-Send
Transmitter Data Signal
Receiver Data Signal
Received Line Signal Detector
C. V.24 INTERFACE:
DCLK
RTS
CTS
TXD
RXD
RlSD
Name
Type
Pin No.
Description
E. ANALOG SIGNALS:
OC
IB
OC
IB
OC
OC
TXOUT
RXIN
AUXI
AA
AB
AC
28
37
26
Connect to Output Op Amp
Connect to Input Op Amp
AUXiliary Analog Input
I/OB
I/OB
R'
R'
R'
R'
R'
R'
R'
R'
R'
R'
R'
R'
R'
R'
R'
R'
R'
R'
R'
R'
R'
43
3
10
9
47
34
16
44
30
38
36
23
14
40
39
15
27
35
20
41
5
1
42
Power-On-Reset Output
Power-On-Reset Input
Connect to Crystal Circuit
Connect to Crystal CirCUit
Receive Mode Output
Connect to RCVO
Connect to RCVO
SWitched Capacitor Clock Output
Connect to SClKO
Connect to SClKO
Smoothing Filter Output
AGC Input
DAC/AGC Data Out
Connect to DAOUT
ADC Output
Connect to ADOUT
Smoothing Filter Output
Connect to FOUT
Sample Clock Output
Connect to SYNCOUT
Connect to SYNCOUT
Connect to SYNCOUT
RC Junction for POR Time
Constant
2
6
7
21
45
Do
Do
Do
Do
Do
F.OVERHEAD
PORO
PORI
XTLO
XTU
RCVO
RCVl1
RCVI2
SClKO
SClKIN1
SClKIN2
AOUT
AGCIN
DAOUT
DAIN
ADOUT
ADIN
FOUT
FIN
SYNCOUT
SYNCIN1
SYNCIN2
SYNCIN3
RCI
G. RESERVED
R'
R'
R'
R'
R'
D. CABLE EQUALIZER:
Not
Not
Not
Not
Not
Connect
Connect
Connect
Connect
Connect
CABlE1
IC
32
Cable Select 1
• R = Required overhead connection; no connection to host equipment.
CABlE2
IC
33
Cable Select 2
Unused inputs tied to +5V or ground require individual 10K n senes
resistors.
3-54
R48PCJ
4800 bps PC Communication Modem
Digital Interface Characteristics
Type
Input
Symbol
Parameter
IA
IB
IC
V,H
Input Voltage, High
V
20 min
20 min
2.0 min
V'L
VOH
VOL
liN
IOH
IOL
IL
Ipu
Input Voltage, Low
Output Voltage, High
Output Voltage, Low
Input Current, Leakage
Output Current, High
Output Current, Low
Output Current, Leakage
Pull-up Current
(Short CirCUit)
Capacitive Load
Capacitive 0 rive
Circuit Type
V
V
V
08 max.
08 max
0.8 max.
pA
±25 max
CL
Co
Notes
1. I load
2 I load
=
=
OA
2.4 min.'
0.4 max 2
-0.1 max.
1.6 max.
rnA
rnA
pA
pA
pF
pF
5
-240 max.
-10 min
5
-240 max
-10 min.
20
TTL
w/Pull-up
TTL
w/Pull-up
TTL
3. Iload = -40 pA
4 V,N = 04 to 2.4 Vdc, Vee
5 I load = 036 rnA
-100~A
16 rnA
Input/Output
Output
Units
OB
OC
IIOA
IIOB
20 min.
525 max.
20 min.
0.8 max.
2.4 min. 3
04 max. s
,
0.4 max. 2
0.4 max. 2
1.6 max.
±10 max.
1.6 max.
08 max.
2.4 min.
0.4 max. 2
±125max.
-260 max
-100 min.
10
40
100
100
100
100
Open-Drain
Open-Drain Open Drain
3 State
w/Pull-up Transceiver w/Pull-up
-240 max
-10 min.
100
TTL
=
5.25 Vdc
II
Analog Interface Characteristics
Analog Interface Characteristics
Name
Type
Characteristics
TXOUT
AA
The transmitter output can supply a
maximum of ± 303 volts Into a load
resistance of 10k D minimum. In order to
match to 600 D, an external smoothing
filter with a transfer function of
15726 43/(S + 11542 44) and 604 D series
resistor are required
RXIN
AB
The receiver Input Impedance IS greater
than 1M D An external anllaliasln9 filter
with a transfer funcllon of
19533 88/(S+ 11542 44) IS required.
AUXI
AC
The aUXiliary analog Input allows access
to the transmitter for the purpose of
interfacing With Jser provided equipment.
Because thiS IS a sampled data Input,
any signal above 4800 Hz Will cause
aliaSing errors. The Input Impedance IS
1M D, and the gain to transmitter output
(TXA) IS + 5.6 dB ± 1 dB.
READ
(,
WRITE
READ
Note: Absolute maximum voltage ralings for analog Inputs are.
(- 5 VA - 03) ,;; V,N ,;; (+ 5 VA + 0.3)
Microprocessor Interface Timing Requirements
Symbol
Min
Max
Units
CS, RSI setup time prior
to READ or WRITE
TCS
ns
TDA
30
-
-
Data Access time after READ
140
ns
Data hold time after READ
TDH
10
50
ns
Characteristic
CS, RSI hold time after
READ or WRITE
TCH
10
TWOS
75
-
ns
Write data setup time
Wnte data hold time
TWDH
10
-
ns
TWR
75
-
ns
WRITE strobe pulse Width
WRITE
0,
(, = 0-7)
ns
Microprocessor Interface Timing Waveforms
3-55
R48PCJ
4800 bps PC Communication Modem
Cable Equalizers
When information in these registers is being discussed, the format Z:O is used. The register is specified by Z(O-F), and the bit
by 0(0-7, 0 = LSB). A bit is considered to be "on" when set to
a one (1) and "off" when reset to a zero (0).
Modems may be connected by direct wiring, such as leased
telephone cable or through the public switched telephone network, by means of a data access arrangement. In either case,
the modem analog signal is carried by copper wire cabling for
at least some part of its route. The cable characteristics shape
the passband response so that the lower frequencies of the passband (300 Hz to 1700 Hz) are attenuated less than the higher
frequencies (1700 Hz to 3300 Hz). The longer the cable the more
pronounced the effect.
Status/Control Bits
The operation of the R48PCJ is affected by a number of software control inputs. These inputs are written into registers within
the interface memory via the host microprocessor bus. Modem
operation is monitored by various software flags that are read
from interface memory via the host microprocessor bus.
To minimize the Impact of this undesired passband shaping, a
compromise equalizer with more attenuation at lower frequencies than at higher frequencies can be placed in series with the
analog signal. The modem includes three such equalizers
designed to compensate for cable distortion.
CABLE2
0
0
1
1
All status and control bits are defined in the R48PCJ Interface
Memory Map table. Bits designated by • - ' are reserved for
modem use only and must not be changed by the host.
Cable Equalizer Selection
CABLE1
Length 01 0.4mm Diameter cable
0
1
0
1
Anyone of the registers may be read or written on any host read
or write cycle, but all eight bits of that register are affected. In
order to read a single bit or a group of bits in a register, the host
processor must mask out unwanted data. When writing a single
bit or group of bits in a register the host processor must perform
a read-modify-write operation. That is, the entire register is read,
the necessary bits are set or reset in the accumulator of the host,
then the original unmodified bits and the modified bits are written
back into the register of the interface memory.
0.0
I.B km
3S km
72 km
Analog Signals
Three analog signals provide the interface point for telephone
company audio circuits and host audio inputs. Signals TXOUT
and RXIN require buffering and filtering to be suitable for driving
and receiving the communication channel. Signal AUXI provides
access to the transmitter for summing host audio signals with
the modem analog output.
Configuration Control
Six configurations are available in the R48PCJ modem: V.27
4800/2400 bps long/short train (four variations), V.21, and Tone.
The configuration Is selected by writing an 8-bit binary code into
the configuration field (CONF) olthe interface memory. The configuration field consists of bits 7 through 0 of register D. The
code for these bits is shown in the follOWing table. All other codes
represent Invalid states.
The filters required for anti-aliasing on the receiver input and
smoothing on the transmitter output have a single pole located
at 11,542 radians. Although this pole is located within the modem
passband, internal filters compensate for its presence and,
therefore, the pole location must not be changed. Some variation from recommended resistor and capacitor values is permitted as long as the pole is not moved, overall gain is preserved,
and the device is not required to drive a load of less than 10k O.
Configuration Codes
CONF Code
00
Notice that when reference is made to signals TXA, RXA, and
AUXIN, these signals are not electrically identical to TXOUT,
RXIN, and AUXI. The schematic of the recommended modem
interface circuit illustrates the differences.
04
05
OS'
07
OB
, Default value at POR.
Overhead
Except for the power-on-reset signal PORO, the overhead
signals are intended for internal use only. The various required
connections are illustrated in the recommended modem interface circuit schematic. No host connections should be made to
overhead Signals other than PORO.
Configuration
V.21
V.27, 2400 Long Train
V.27, 2400 Short Train
V.27, 4BOO Long Train
V.27, 4BOO Short Train
Tone Mode
When the modem is initialized by power-on-reset, the configuration defaults to V.27 4800 bps long train. When the host wants
to change configuration, the new code is written to the configuration field and the SETUP bit (E:3) is set to a one. Once the new
configuration takes effect, the SETUP bit is reset to zero by the
modem.
SOFTWARE CIRCUITS
The R48PCJ contains 16 memory mapped registers to which an
external (host) microprocessor has access. The host may read
data out of or write data into these registers. Refer to the R48PCJ
Host Processor Interface figure.
The information in the interface memory is serviced by the
modem at the baud rate (V.27 and V.21), 9600 times per second
(tone generator), or 1600 times per second (tone detector).
3-56
R48PCJ
4800 bps PC Communication Modem
READ
WRITE
r-
READ
WRITE
LOGIC
8
~
"-f8
"
DO-D7
I-REGISTER E I-REGISTER F
RSO-RS3
···
REGISTER
SELECT
LOGIC
~/
r---
t..
A
···
···
f-
REGISTER 0
I--
REGISTER 1
SP
1/0
I~
BUS
h......
-
INTERRUPT
LOGIC
IRQ
l
LOGIC
UNIT
k=> q
SP
MAIN
BUS
RAM
j
...............
INTERFACE MEMORY
R48PCJ Host Processor Interface
R48PCJ Interface Memory Map
I~
7
5
6
4
3
2
1
o
Register
F
1
Serial Mode-The serial mode uses a standard V.24 (RS-232-C)
hardware mterface (optional USRT) to transfer channel data.
Transmitter data can be sent serially only when TPDM is set to
a zero.
RAMA
E
IA
COlE COREQ
-
D
SETUP
OOIE
-
joOREOl
CONF
1---
r--£B
RTSP
A
TDET
EPT
RX
TPDM TDIS
FED
-
EQSV EQFZ
GHIT
SDIS RAMW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PN
-
-
-
-
-
-
-
-
-
-
9
-
-
8
-
-
7
-
-
-
-
6
-
-
! -
-
COET
5
I
I
Parallel Mode-Parallel data IS transferred via two registers in
the Interface memory. Register 5 (RXCD) IS used for receiver
channel data, and Register 4 (TXCD) is used for transmitter channel data. Register 5 IS continuously written every eight bit times
when in the receive state. Register 4 is used as the source of
channel transmitter data only when bit C:5 (TPDM) is set to a one
by the nasI. Otherwise the transmitter reads data from the V.24
Interface. Both RTS and RTSP remain enabled, however, regardless of the state of TPDM.
-
RXCD
4
TXCD
3
DDXM
2
DDXL
1
DDYM
0
DDYL
0,i
Bit
I
7
I
6
5
4
I
3
2
To enable the transmllter parallel mode, TPDM must be set to
a 1 The modem automatically defaults to the serial mode
(TPDM = 0) at power-on. In either transmitter serial or parallel
mode, the R48PCJ is configured by the host processor via the
microprocessor bus.
1
I
0
When performing parallel data transfer of channel data, the host
and modem can synchronize their operations by handshaking bits
In register E. Bit E:5 (CDREQ) IS the channel data request bil.
This bit is set to a one by the modem when receiver data IS
available In RXCD or when transmitter data is required in TXCD.
Once the host has finished reading RXCD or writing TXCD, the
host processor must reset CDREQ by writing a zero to that bit
location.
I
I~
When set to a one by the host, Bit E:6 (CDIE) enables the CDREQ
bit to cause an IRQ Interrupt when sel. While the IRQ line IS
driven to a TTL low level by the modem, bit E:7 (lA) IS a one.
Channel Data Transfer
Data sent to or received from the data channel may be transferred
between the modem and host processor In either senal or parallel
form. The receiver operates In both senal and parallel mode
Simultaneously and reqUires no mode control bit selection The
transmitter operates In either senal or parallel mode as selected
by mode control bit C 5 (TPDM).
If the host does not respond to the channel data request within
eight bit times, the RXCD register IS over written or the TXCD
register IS sent again.
Refer to Channel Data Parallel Mode Control flow chart for recommended software sequence.
3-57
•
R48PCJ
4800 bps PC Communication Modem
R48PCJ Interface Memory Definitions
Mnemonic
Name
Memory
location
Description
CDET
Carrier Detector
8:5
The one state of CDET indicates passband energy is being detected, and a training sequence is
not present. COET goes to one at the start of the data state, and returns to zero at the end of the
received signal. CDET activates one baud time before RLSO and deactivates one baud time after
RLSO.
CDIE
Channel Data
Interrupt Enable
E:6
When set to a one, CDIE enables an IRQ interrupt to be generated when the channel data
request bit (CDREQ) is a one.
CDREQ
Channel Data
Request
E:5
Parallel data mode handshaking bit. Set to a one when the modem receiver writes data to RXCD,
or the modem transmitter reads data from TXCD. CDREQ must be reset to zero by the host
processor when data service is complete.
CONF
Configuration
D:0-7
The 8-bit field CONF controls the configuration of the modem according to the following table:
Hex Code
00
04
05
06
07
08
All else
Configuration
V.21
Y.27, 2400 Long Train
Y.27, 2400 Short Train
V.27, 4800 Long Train (Default)
V.27, 4800 Short Train
Tone
Invalid
Configuration Definitions
V.21-The modem operates as a CCITT T.30 compatible 300 bps FSK modem having
characteristics of the CCITT Y.21 Channel 2 modulation system.
Tone-The modem sends single or dual frequency tones in response to the RTS or RTSP signals.
Tone frequencies and amplitudes are controlled by RAM locations written by the host. When not
transmitting tones the Tone configuration allows detection of single frequency tones by the TDET
bit. The tone detector frequency can be changed by the host by altering the contents of several
RAM locations.
V 27-The modem
IS
compatible with CCITT Recommendation V.27 ter.
DOlE
Diagnostic Data
Interrupt Enable
E:2
When set to a one, DDIE enables an IRQ interrupt to be generated when the diagnostiC data
request bit (OOREQ) is a one.
DDREQ
Diagnostic Data
Request
E:O
DDREQ goes to a one when the modem reads from or writes to DDYL. DDREQ goes to a zero
when the host processor reads from or writes to DDYL. Used for diagnostic data handshaking bit.
DDXL
Diagnostic Data
X Least
2:0·7
Least significant byte of 16·bit word used in reading XRAM locations.
DDXM
Diagnostic Data
X Most
3:0·7
Least significant byte of 16·bit word used in reading XRAM locations.
DDYL
Diagnostic Data
Y Least
0:0·7
Least significant byte of 16·bit word used in reading YRAM locations or writing XRAM and YRAM
locations.
DDYM
Diagnostic Data
Y Most
1:0·7
Most significant byte of 16·bit word used in reading YRAM locations or writing XRAM and YRAM
locations.
EPT
Echo Protector
Tone
C:6
When EPT is a one, an unmodulated carrier is transmitted for 185 ms followed by 20 ms of no
transmitted energy at the beginning of the training sequence. EPT is not active if TDIS is on.
EQFZ
Equalizer Freeze
C:2
When EQFZ is a one, the adaptive equalizer taps stop updating and remain frozen.
EQSV
Equalizer Save
C:3
When EQSV is a one, the adaptive equalizer taps are not zeroed when reconfiguring the modem
or when entering the training state. Adaptive equalizer taps are also not updated during training.
FED
Fast Energy
Detector
8:5,6
FED consists of a 2·bit field that Indicates the level of received signal according to the following
code.
Code
o
1
2
3
Energy Level
None
Invalid
Above Turn·off Threshold
Above Turn·on Threshold
While receiving a signal, FED normally alternates between Codes 2 and 3.
3·58
4800 bps PC Communication Modem
R48PCJ
R48PCJ Interace Memory Definitions (continued)
Mnemonic
Name
Memory
Location
Description
B:4
The gain hit bit goes to one when the receiver detects a sudden Increase in passband energy
faster than the AGC CIrCUIt can correct GHIT returns to zero when the AGC output returns to
normal
Interrupt Active
E7
IA IS a one when the modem IS dnvlng the Interrupt request line (IRQ) to a low TTL level
Penod N
8:3
PN sets to a one at the start of the received PN sequence PN resets to zero at the start of the
received scrambled ones. PN does not operate when TDIS IS set to a one
RAMA
RAM Access
f"0-7
The RAMA register is written by the host when reading or wntlng diagnostic data. The RAMA
code determines the RAM location With which the diagnostic read or wnte IS performed.
RAMW
RAM Wnte
C.O
RAMW IS set to a one by the host processor when performing diagnostic wntes to the modem
RAM RAMW IS set to a zero by the host when reading RAM diagnostic data
RTSP
Request to Send
Parallel
C.?
The one state of RTSP beginS a transmit sequence The modem continues to transmit until RTSP
is turned off and the turn-off sequence has been completed RTSP parallels the operation of the
hardware RTS control Input. These Inputs are ORed by the modem
RXCD
Receiver Channel
Data
50-7
RXCD IS wntten to by the modem every eight bit times This byte of channel data can be read by
the host when the receiver sets the channel data request bit (CDREQ)
RX
Receive State
B7
RX IS a one when the modem IS In the receive state (I e, not transmltllng)
SOlS
Scrambler Disable
C1
When SDIS IS a one, the scrambler/descrambler IS disabled. When SDIS IS a zero, the
scrambler/descrambler IS enabled (default)
SETUP
Setup
E'3
The host processor must set the SETUP bit to a one when reconfigunng the modem, Ie, when
changing CONF (D'O-7)
TDET
Tone Detected
A'7
GHIT
Gain Hit
IA
PN
The one state of TDET indicates reception of a tone The filter can be retuned by means of the
diagnostic write routme.
TDIS
TPDM
TXCD
Training Disable
' Transmitter Parallel
Data Mode
Transmitter
Channel Data
C'4
If TDIS IS a one In the receive state, the modem IS prevented from entering the training phase If
TDIS IS a one when RTS or RTSP go active, the generation of a training sequence IS prevented at
the start of transmission
CS
When control bit TPDM IS a one, the transmitter accepts data for transmission from the TXCD
register rather than the senal hardware data Input
40-7
The host processor conveys output data to the transmitter In parallel data mode by wntlng a data
byte to the TXCD register when the channel data request bit (CDREQ) goes to a one Data IS
transmitted as Single bits In V.21 or as dlblts In V27 starting With bit 0 or diblt 0,1.
These bits are written into interface memory registers 3, 2, 1
and 0 In that order. Registers 3 and 2 contain the most and least
slgmficant by1es of XRAM data, respectively, while registers 1
and 0 contain the most and least Significant bytes of YRAM data
respectively.
Diagnostic Data Transfer
The modem contains 128 words of random access memory
(RAM). Each word is 32-blts wide. Because the modem is
optimized for performing complex arithmetic, the RAM words
are frequently used for storing complex numbers. Therefore,
each word is organized Into a real part (16 bits) and an Imaginary
part (16-blts) that can be accessed Independently. The portion
of the word that normally holds the real value IS referred to as
XRAM. The portion that normally holds the imaginary value is
referred to as YRAM. The entire contents of XRAM and YRAM
may be read by the host processor via the microprocessor
interface.
When set to a one, bit C:O (RAMW) causes the modem to suspend transfer of RAM data to the interface memory, and Instead,
to transfer data from interface memory to RAM. When writing
Into the RAM, only 16 bits are transferred, not 32 bits as for a
read operallOn. The 16 bits written in XRAM or YRAM come from
registers 1 and 0, with register 1 being the more significant by1e.
Selection of XRAM or YRAM for the destination is by means of
the code stored In the RAMA bits of register F. When bit F:7
is set to one, the XRAM IS selected. When F:7 equals zero,
YRAM IS selected.
The interface memory acts as an Intermediary during these host
to signal processor RAM data exchanges. The RAM address to
be read from or written to is determined by the contents of
register F (RAMA). The R48PCJ RAM Access Codes table lists
27 access codes for storage In register F and the corresponding
diagnostic functions. The R48PCJ Diagnostic Data Scaling table
provides scaling information for these diagnostic functions. Each
RAM word transferred to the interface memory IS 32 bits long.
When the host processor reads or writes register 0, the
diagnostic data request bit E:O (DDREO) is reset to zero. When
the modem reads or wntes register 0, DDREO IS set to a one.
When set to a one by the host, bit E:2 (ODIE) enables the DDREO
bit to cause an IRO Interrupt when set. While the IRO line IS
driven to a TTL low level by the modem, bit E:7 (IA) goes to a one.
3-59
•
R48PCJ
4800 bps PC Communication Modem
1-TPDM
1-RTSP
OR
O-RTS
O-CDREa
N
N
DATA -
TXCD
O-CDREa
READ RXCD
N
N
N
0 - RTSP
AND
1 - RTS
Channel Data Parallel Mode Control
3-60
R48PCJ
4800 bps PC Communication Modem
R48PCJ RAM Access Codes
Node
Function
RAMA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
AGC Gain Word
Average Power
Receiver Sensitivity
Receiver Hysteresis
Equalizer Input
Equalizer Tap Coefficients
Unrotated Equalizer Output
Rotated Equalizer Output
Decision Points
Error Vector
Rotation Angle
Frequency Correction
EOM
Alpha (or)
Beta One (is,)
Beta Two (iS2)
Alpha Prime (or')
Beta One Prime (P,'}
Beta Two Prime (Pi)
Alpha Double Prime (or")
Beta Double Prime (P")
Output Level
Tone 1 Frequency
Tone 1 Level
Tone 2 Frequency
Tone 2 Level
Checksum
I!l
27
91
47
84
63
23-32
73
OA
74
75
B3
8B
89
38
39
3A
3B
3C
3D
B8
B9
43
8E
44
8F
45
02
R48PCJ Diagnostic Data Scaling (Cont'd)
Reg. No.
2.3
2.3
0,1
2,3
0,1,2.3
0,1,2.3
0,1,2,3
0,1,2,3
0,1,2,3
0,1,2,3
2,3
2.3
2.3
0,1
0,1
0,1
0,1
0,1
0,1
2.3
2,3
0,1
2,3
0,1
2,3
0,1
0,1
Node
Parameter/Scaling
5,7-9
All base-band signal point nodes (i.e., Equalizer Input,
Un rotated Equalizer Output, Rotated Equalizer Output, and
Decision Points) are 32-bit, complex, twos complement
numbers.
Value (Hex)
6
Point
X
y
1
2
3
4
5
6
7
8
1000
OCOO
F400
E300
E300
F400
OCOO
1000
OCOO
1000
1000
OCOO
F400
E300
E300
F400
y
83
82
84
81
85
88
X
86
87
Equalizer Tap Coefficients (32-bit, complex, twos
complement)
Complex numbers with X = real part, Y = imaginary part
X and Y range: 0000 to (FFFF),s representing ± full scale
in hexadecimal twos complement.
10
11
Error Vector (32-bit, complex, twos complement)
Complex number with X = real part,
Y = imaginary part.
X and Y range: (8000),s to (7FFF),s
Rotation Angle (16-bit, signed, twos complement)
Rotation Angle in deg. = (Rot. Angle Word/65,536) x 360
12
Frequency Correction (16-bit signed twos complement)
Frequency correction in Hz
= (Freq. Correction Word/65,536) x Baud Rate
Range: (FCOO),s to (400),6 representing ± 18.75 Hz
R48PCJ Diagnostic Data Scaling
Node
1
ParameterlScaling
13
EQM (16-bit, unsigned)
Filtered squared magnitude of error vector.
Proportionality to BER determined by particular application.
14--21
Filter Tuning Parameters (16-bit unsigned) Alpha, Beta One,
Beta Two, Alpha Prime, Beta One Prime, Beta Two Prime,
Alpha Double Prime, and Beta Double Prime are set according
to instructions in application note 668.
22
Output Level (16-bit unsigned)
Output Number = 27573.6 [1Q2~EAD.cp2) a!!!l
Write Enable·R/W (WRITE/R/W)
Because of the open-drain structure of IRQ, an external
pull-up resistor to +5V is required at some point on the IRQ
line. The resistor value should be small enough to pull the
IRQ line high when all IRQ drivers are off (i.e., it must overcome the leakage currents). The resistor value should be
large enough to limit the driver sink current to a level acceptable to each driver. If only the modem IRQ output is
used, a resistor value of 5.6K ohms ±20%, 0.25 W, is sufficient.
During a read cycle, data from the selected DSP interface
memory register is gated onto the data bus by means of
three-state drivers in each DSP. These drivers force the
data lines high for a one bit, or low for a zero bit. When not
being read, the three-state drivers assume their high-impedance (off) state.
During a write cycle, data from the data bus is copied into
the selected DSP interface memory register, with high and
low bus levels representing one and zero bit states,
respectively .
V.24 INTERFACE
Seven pins provide tim ing, data, and control signals for implementing a CCITT Recommendation V.24 compatible
serial interface. These signals are TTL compatible in order
to drive the short wire lengths and circuits normally found
within stand-alone modem enclosures or equipment
cabinets. For driving longer cables, these signals can be
easily converted to RS-232-C voltage levels. The transmit
and receive timing is shown in Figures 3 and 4, respectively.
The read/write cycle timing waveforms are illustrated in
Figure 2 and the timing requirements are shown in
Table 8.
Interrupt Request (IRQ)
The modem Interrupt Request (IRQ) output may be connected to the host processor interrupt request input in
order to interrupt hOs.!...E!,ogram execution for immediate
modem service. The IRQ output can be enabled in DSP
interface memory to indicate immediate ch~ of conditions in the modem DSP device. The use of IRQ is optional depending upon modem application. Refer to the
Software Considerations Section for a summary of the
modem interrupt bits, interrupt conditions and interrupt
clearing procedures.
Transmitted Data (TXO)
The modem obtains serial data to be transmitted from the
local DTE on the Transmitted Data (TXD) input.
Table 8. Microprocessor Interface Timing
Parameter
CS Setup TIme
RSi Setup Time
Data Access Time
Data Hold Time
Control Hold TIme
Write Data Setup Time
Wr~e Data Hold Time
The DSP IRQ output structure is an open-drain field-effecttransistor (FET). The modem IRQ output can be wireORed with other IRQ lines in the application system. Any
of these sources can drive the host interrupt input low, and
the host interrupt servicing process normally continues
until all interrupt requests have been serviced (i.e., all IRQ
lines have returned high).
Symbol
Min.
Max.
Units
TCS
TRS
TDA
TDHR
THC
TWOS
TDHW
0
25
-
ns
ns
ns
ns
ns
ns
ns
-
75
10
10
20
10
-
-
Table 7. Digital Interface Characteristics
Input/Output Type
Symbol
Parameter
IA
IB
IC
V
2.0 min.
2.0 min.
(See Note 3
O.S max.
O.S max.
in Fig. 9)
Units
V,H
Input High Voltage
V,L
Input Low Voltage
V
hH
Input High Current
IlA
OA
OB
hL
Input Low Current
rnA
Input Leakage Current
!lA
VOH
Output High Voltage
V
3.5 min.'
3.5 min.'
VOL
Output Low Vonage
V
0.4 max. 2
0.4 max. 3
11 max.
IOH
Output High Current
rnA
- 0.1 max.
- 0.1 max.
Output Low Current
rnA
1.6 max.
O.Smax.
±10 max.
± 10 max.
100
100
Output Leakage Current
!lA
Capacitive Load
pF
Co
Capacitive Drive
pF
Circu~Type
5
20
10
TTL
Tn.
CLK
w/pull-up
Notes:
1.ILoad=-loomA
2.1 Load = 1.6 rnA
3. I Load = O.S rnA
OE
-{).4 max.
,02.5 max.
IOL
ILO
00'
40 max.
lu
CL
OC
TTL
TTL
3-state
3-state
4. Loads on 12 MHz and 6 MHz outputs must be balanced within 20%.
3-85
2.4 min.'
0.4 max. 2
1.6 max.
0.4 max. 2
-0.001 max.
40 min.
0.001 max.
0.4 max.
100
50
Open drain
CLK
Tn.
•
R96MFX
9600 bps MONOFAX Modem
READ
WRITE
Tes
RSi
(i=0-4)
TDHR
01
(1=0-7)
a. 8085 Bus Compatible (EN85 = L)
WRITE
READ
Tes
RSi
(i=0-4)
RiW
.2 ------'I
Di
(1=0-7)
b. 6500 Bus Compatible (EN85
=H)
Figure 2. Microprocessor Interface Waveforms
3-86
9600 bps MONOFAX Modem
R96MFX
The RLSD receive level thresholds default to -43 dBm for
the off-to-on threshold and to -48 dBm for the on-to-off
threshold. A minimum hysteresis action of 2 dBm exists
between the actual off-to-on and on-to-off transition levels.
The threshold level and hysteresis action are measured
with an unmodulated 21 00 Hz tone applied to the Receiver
Analog (RXA) input. Note that performance may be
degraded when the received signal level is less than -43
dBm. The RLSD on and off thresholds are host programmable in DSP RAM.
Received Data (RXD)
The modem presents received serial data to the local DTE
on the Received Data (RXD) output.
Request To Send (RTS)
Request to Send (RTS) active allows the modem to transmit data on TXD when CTS becomes active. The responses to RTS are shown in Table 3.
Clear To Send (CTS)
Data Clock (OCLK)
Clear to Send (CTS) active indicates to the local DTE that
the modem will transmit any data presen!..Q!!. TXD. CTS
response times from an active condition of RTS are shown
in Table 4.
The modem provides a single Data Clock (DCLK) output
which performs the function of a transmitter data clock
when the modem is transmitting and a receiver data clock
when the modem is receiving.
Received Line Signal Detector (RLSO)
DCLK as the Transmit Data Clock:
For V.29 and V.27, Received Line Signal Detector (RLSD)
goes active at the end of the training sequence. If energy
is above the turn on threshold and training is not detected,
the RLSD off-to-on response time is 804 baud times. The
RLSO on-to-offtime for V.29 is 30 ± 9 ms. The V.27 RLSO
on-to-off time is 11.6 ± 5 ms. The RLSO on-to-off time ensures that all valid data bits have appeared on RXD.
RTS
~I
The modem outputs a synchronous transmit Data Clock,
for USRT timing, when the modem is transmitting. The
DCLK frequency is 9600, 7200, 4800, 2400, or 300 Hz
(±0.01%) with a duty cycle of 50 ± 1%. In Group 2, the
DCLK frequency is 10368 Hz ± 5 ppm when a precision
oscillator (Y2 in Table 12) is used.
I
I·
! ,
i-TON-j
CTS
DClK
r---;
~
·T OFF
U1flflf
----11
LI""""""'lll"""""9
TXD
FIRST DATA BIT TRANSMITTEJ
II:
-C '
,
lAST DATA BIT TRANSMITTED
r
L
TRANSMITTED ENERGY
~------------------~
Figure 3. Transmitter Signal Timing
~ R~CEIVED ENERGY
~ ~,--------------------~
~ ~~------------~
DCll<
RXD
1IlIlfif
---I;
)"
I I I I I I I II I I I II
FIRST BIT RECEIVED
----Ir
I - -_ _ _
r---------~I
1(: :II (I I II 5'
lAST BIT RECEIVED
Figure 4. Receiver Signal Timing
3-87
•
R96MFX
9600 bps MONOFAX Modem
Transmit Data (TXD) must be stable during the one fls
period immediately preceding the rising edge of DCLK and
following the rising edge of DCLK.
ANALOG SIGNALS
The Transmitter Analog Output (TXOUT) and Receiver
Analog Input (RXIN) allow modem connection to either a
leased line or the PSTN through the appropriate buffering
and an audio transformer or a data access arrangement.
The Auxiliary Input (AUXI) provides access to the transmitter for summing audio signals with the modem's transmitter analog output. The analog Signal characteristics are
described in Table 9.
DCLK as the Receive Data Clock:
The modem outputs a synchronous receive data clock, for
USRT timing, when the modem is receiving. The DCLK
frequency is 9600, 7200, 4800, 2400, or 300 Hz (± 0.01 %)
with a duty cycle of 50 ±1%.ln Group 2, the DCLKfrequency is 10368 Hz ± 5 ppm when a precision oscillator (Y2 in
Table 12) is used.
Table 9. Analog Interface Characteristics
ANCILLARY SIGNALS
Name
TXOUT
Enable 85 (EN85)
The Enable 85 (EN85) input selects the modem
microprocessor bus compatibility. When EN85 is low, the
modem can interface directly to an 8085 compatible
microprocessor bus using READ and WRITE. When EN85
is high, the modem can interface directly to a 6500 compatible microprocessor bus using <1>2 and RiW.ln the 6500
configuration, the READ input becomes <1>2 and the WRITE
input becomes RiW. This selection is performed when
power is turned on or when POR is activated.
Cable Equalizer Select 1 and 2 (CABLE1 and
CABLE2)
Modems may be connected by direct wiring, such as
leased telephone cable or through the PSTN, by means of
a data access arrangement. In either case, the modem
analog signal is carried by copper wire cabling for at least
some of its route. The cable characteristics shape the
passband response so that the lower frequencies of the
passband (300 Hz to 1700 Hz) are attenuated less than
the higher frequencies (1700 Hz to 3300 Hz). The longer
the cable, the more pronounced the effect.
RXIN
AB
AUXI
AC
Characteristic
Maximum output:
±3.03votts
Minimum load:
10K n
Smoothing fitter transfer function:
28735.63l{s + 11547.34~
Input impedance:
1M n
Anti-aliasing filter transfer function:
21551.72J'(s+ 11547.~
Maximum input frequency:
4800 Hz
Input Impedance:
1M n
Gain to TXOUT:
+5.6 dBm ±1 dBm
TXOUT can supply a maximum of ± 3.03 volts into a load
resistance of 10K ohms minimum. A 600 ohm line impedance can be matched using an external smoothing filter with a 604 ohm series resistor in its output. The
smoothing filter should have a transfer function of
28735.63/(s + 11547.34).
Receiver Analog Input (RXIN)
The RXIN input impedance is greater than 1M ohms. RXIN
requires an external anti-aliasing filter between the
modem and the line interface, with a transfer function of
21551.72/(s + 11547.34). The maximum input level into
the anti-aliasing filter should not be greater than 0 dBm.
The filters required tor anti-aliasing on the receiver input
and the smoothing filter on the transmitter output have a
single pole within the modem's passband (11,542
radians). Internal filters compensate for its presence,
therefore, the pole location must not be changed. Some
variation from the recommended reSistor and capacitor
values is permitted as long as the pole is not moved, overall gain is preserved, and the device is not required to drive
a load of less than 10K ohms (see Recommended Modem
I nterface Circuit.)
The cable length equalization is selected from the
CABLE1 and CABLE2 input lines as follows:
CABLE1
0
1
0
1
M
Transmitter Analog Output (TXOUT)
To minimize the impact of this undesired passband shaping, a compromise equalizer with more attenuation at the
lower frequencies than at the higher frequencies can be
placed in series with the analog signal. The modem includes three such equalizers designed to compensate for
cable distortion. When selected, the equalizers are inserted in the transmit path when transmitting, and in the
receive path when receiving. Table 2 shows the cable
equalization.
CABLE2
0
0
1
1
Type
Length
O.Okm
1.Skm
3.6km
7.2km
3-88
R96MFX
9600 bps MONOFAX Modem
Auxiliary Analog Input (AUXI)
AUXI allows access to the transmitter for the purpose of interfacing with user provided equipment. Because this is a
sampled input, any signal above 4800 Hz will cause aliasing errors. The input impedance is >1M ohm, and the gain
to TXOUT is +5.6 dBm ± 1 dBm.
II-I---""L
EYESYNC
EYECLK'
DIAGNOSTIC SIGNALS
Four signals provide the timing necessary to create an oscilloscope quadrature eye pattern. The eye pattern is
simply a display of the received baseband constellation.
By observing this constellation, common line disturbances
can usually be identified. Timing of these signals is illustrated in Figure 5 and an example eye pattern generation schematic is shown in Figure 6.
MSB
EYEX.
EYEY
LSB
~~
*74LS74 OUTPUT PIN 9 (FIGURE 6)
EYEX and EYEY
Figure 5. Eye Pattern Timing
The EYEX and EYEY outputs provide two serial bit
streams containing data for display on the oscilloscope X
axis and Y axis, respectively. This serial digital data must
first be converted to parallel digital form by two serial-toparallel converters and then to analog form by two digitalto-analog (D/A) converters.
EYECLK
EYECLK is a clock provided to create a clock which can
be used by the serial-to-parallel converters to shift in the
EYEX and EYEY data (see Figure 5).
EYESYNC
EYEX and EYEY outputs are 15-bit words, each with 8-bits
of significance. The 15-bit data words are shifted out most
significant bit first with the seven most significant bits set
equal to zero. EYEX and EYEY are clocked by the rising
edge of EYECLK.
EYESYNC is a strobe for loading the DIA converters.
3-89
•
R96MFX
9600 bps MONOFAX Modem
EYEX
+5 O.lI'F
14
9
A
+5V
4.7KO
74lS164
B
7
ClK
74lS74
~
ClA
5
6
10
234
10 lSB
5
6
3
4
-=
11 12
EYESYNC
PIN 17
7
.---------~~-a[E
EYEY
PIN 44
X-OUT
(SCOPE)
8
V out 20
14 REF OUT
SUM F---'--',
NE5018
13 REF IN
OFFSETj-:1.::.5_.....
R96MFX
+ 12V--------..
~O.lI'F
74lS164
2
3
10 lSB
5
6
10
4
5
6
11 12
7
V-OUT
(SCOPE)
8
~------------.Q[E
IN914B
14 REF OUT
NE5018
+ 12V--------.....
~O.lI'F
Figure 6. Eye Pattern Circuit
3-90
2KIl
9600 bps MONOFAX Modem
R96MFX
SOFTWARE INTERFACE
INTERFACE MEMORY MAPS
Modem functions are implemented in firmware executing
in a single asp.
A memory map of the 32 addressable registers in the
modem is shown in Figure 7. These a-bit registers may be
read or written during any host read or write cycle. In order
to operate on a single bit or a group of bits in a register, the
host processor must read a register and then mask out unwanted data. When writing a single bit or group of bits in a
register, the host processor must perform a read-modifywrite operation. That is, the entire register (a-bits) must
first be read, the necessary bits must be set or reset
without altering the other register bits, then the byte (a-bits)
containing both the unaltered and modified bits must be
written back into the interface memory.
INTERFACE MEMORY
The DSP communicates with the host processor by means
of a dual-port, interface memory. The Interface memory in
the asp contains thirty-two 8-bit registers, labeled register
00 through 1F. Each register can be read from or written
into, by both the host and the asp. The host ~n control
modem operation by writing control bits to asp interface
memory and writing parameter values to asp RAM
through interface memory. The host can monitor modem
operation by reading status bits from asp interface
memory and reading parameter values from asp RAM
through interface memory.
INTERFACE MEMORY BIT DEFINITIONS
Table 10 defines the individual bits in the interface
memory. In the Table 10 descriptions, bits in the interface
memory are referred to using the format Z:Q. The register
number is designated by Z (00 through 1F), and the bit
number by Q (0 through 7, 0 =LSB).
BII
Realster
IF
IE
10
7
8
5
3
4
1
2
0
SETU
!AI
1A2
1E2
BA2
lEI
HAl
lC
II
. •-
lA
1.
1.
17
I.
15
14
Ii
12
X RAM DA1l\ 2
11
1
Y RAM
OF
FED
OE
DO
DC
DB
CIA
DA1l\~
RX
PN
FR3
RTSP
FR2
TOIS
ACe1
0
IIA
08
07
B
FFER
CTSP ICOET
IG2FG
QFZ
IIA
05
CR2
I
FRI
12TH
T2'
-POM
EPT IS( EXT
CR1
RAM ADDRESS 1
D4
x RAM DA1l\ 1 MSB
02
I1t
LSB DAl1
MSB DAM1
LSB IYDAL1
IncII_ ....MId far modem .... only.
Y
Y RAM
01
00
(-I
Figure 7. R96MFX DSP Interface Memory Map
3-91
3
R96MFX
9600 bps MONOFAX Modem
Table 10. R96MFX Interface Memory Bit Definitions
Mnemonic
Memory
Location
Default
Value
Name/Description
12TH
8:4
0
Select 12th Order. The one state of 12TH operates the tone detectors as one 12th order filter (uses FR3). The zero state of 12TH operates the tone detectors as three parallel independent 4th order fitters (FR1, FR2, F~ 2TH is operable in FSK, Group 2, and tone
modes. (i.e., CONF = 20, 40, 80; with RTS off.)
ACCI
5:7
1
RAM Access 1. When control bit ACCI is a 1, the modem accesses the RAM associated
with the address in ADDI and the CRI bit. WRTI determines if a read or write is performed.
ACC2
15:7
1
RAM Access 2. When control bit ACC2 is aI, the modem accesses the RAM associated
with the address in ADD2 and the CR2 bit. WRT2 determines if a read or write is performed.
ADDI
4:0-7
17
RAM Address 1. ADD 1 contains the RAM address used to access the modem's X and Y
Data RAM (CRI = 0) or X and Y Coefficient RAM (CRI = 1) via the X RAM Data 1 LSB and
MSB words (2:0-7 and 3:0-7, respectively) and the Y RAM Data 1 LSB and MSB words (0:07 and 1 :0-7, respectively).
ADD2
14:0-7
11
RAM Address 2. ADD2 contains the RAM address used to access the modem's X and Y
Data RAM (CR2 = 0) or X and Y Coefficient RAM (CR2 = 1) via the X RAM Data 2 LSB and
MSB words (12:0-7 and 13:0-7, respectively) and the Y RAM Data 2 LSB and MSB words
(10:0-7 and 11 :0-7, respectively).
BAI
1E:0
-
Buffer Available 1. When set to aI, status bit BA 1 signifies that the modem has either written diagnostic data to, or read diagnostic data from, the Y RAM DATA 1 LSB (YDAL1)
register (0:0-7). This condition can also cause IRQ to be asserted (see IE1 and IA1). The
host writing to or reading from register 00 resets the BA 1 and IA1 bits to O. (See IE1 and
IA1.)
BA2
1E:3
-
Buffer Available 2. When set to a 1 , status bit BA2 signifies that, when the modem is in
parallel data mode, it has read register 10:0-7 (DBUFF) when transmitting (buffer becomes
empty), or it has written register 10:0-7 (DBUFF) when receiving (buffer becomes full).
When the modem is not in parallel data mode, the setting of BA2 to a 1 by the modem signifies that the modem has either written diagnostic data to, or read diagnostic data from, the
Y RAM DATA 2 LSB (YDAL2) register (10:0-7). These conditions can also cause IRQ to be
asserted (see IE2 and IA2). The host writing to or reading from register 10 resets the BA2
and 1A2 bits to O. (See IE2 and IA2.)
BR1
5:2
0
Baud Rate 1. When control bit BRI is a 1, RAM access associated with ADD1 occurs at the
modem baud rate; when BR1 is a 0, RAM access occurs at the modem sample rate. This bit
must be reset to a zero in G2. FSK, or Tone mode (CONF = 40, 20, or 80, respectively).
BR2
15:2
0
Baud Rate 2. When control bit BR2 is a 1 , RAM access associated with ADD2 occurs at the
modem baud rate; when BR2 is a 0, RAM access occurs at the modem sample rate. This bit
must be reset to a zero in G2, FSK, or Tone mode (CONF = 40, 20, or 80, respectively).
CDET
F:O
-
Carrier Detected. When status bit CDET is a 1, the receiver has finished receiving the training sequence, or has turned on due to detecting energy above threshold, and is receiving
data. When CDET is a 0, the receiver is in the idle state or in the process of training.
3-92
9600 bps MONOFAX Modem
R96MFX
Table 10. R96MFX Interface Memory Bit Definitions (Cont'd)
Mnemonic
CONF
Memory
location
Default
Value
6:0-7
14
Name/Descrlptlon
Configuration. The CONF control bits select one of the following transmitter/receiver configurations:
Configuration
CONF
V.29 9600 bps
V.29 7200 bps
V.29 4800 bps
V.27 4800 bps
V.27 2400 bps
V.21 Channel 2300 bps (FSK)
Group 2 (G2)
Tone Transm!!..ffiTS or RTSP on),
Tone Detect (RTS and RTSP oft)
14
12
11
OA
09
20
40
80
Configuration Definitions:
1. V.29. When a V.29 configuration Is selected, the modem operates as specified In
CCITT Recommendation V.29.
2. V.27. When a V.27 configuration is selected, the modem operates as specified in
CCITT Recommendation V.27.
3. V.21. Channel 2 When the V.21 Channel 2 configuration is selected, the modem
operates as specJfied in CCITT Recommendation V.21 channel 2.
4. Group 2. When the Group 2 configuration Is selected, the modem operatas as
specified In CCITT Recommendation T.3.
5. Tone Transmit. When the Tone Transmit configuration Is seleded, the modem transmits single or dual frequency tones In response to RTS or RTSP. Tone frequencias
and emplttudas are programmable In the RAM.
8. Tone Detect. When the Tone Detect configuration is seleded and 12th Is set to a 1,
the three 4th order tone deled filters are combined into a single 12th order tone
deted filter (FR3). If 12th Is not set to a 1, the three tone detect filters are placed in
parallel and are independent (FR1, FR2, and FR3). All tone detect filters are
programmable.
CR1
5:0
0
Coefficient RAM 1 Select. When control bit CR1 is a 1, ADD1 addresses Coefficient RAM.
When CR1 is a 0, ADD1 addresses Data RAM. This bit must be set according to the desired
RAM address (Table 11).
CR2
15:0
0
Coefficient RAM 2 Select. When control btt CR2 is a 1, ADD2 addressas Coefficient RAM.
When CR2 Is a 0, ADD2 addresses Data RAM. This bit must be set according to the desired
RAM address (Table 11).
CTSP
F:1
-
Clear To Send Parallel. When set to a 1, status bit CTSP indicates to the DTE that the training sequence has been completed and any data present at TXD will be transmitted. CTSP
parallels the operation of the CTS pin.
DBUFF
10:0-7
-
Data Buffer. In the parallel data mode, the host obtains received data from the modem by
reading a data byte from DBUFF; the host sends data to the modem to be transmitted by
wrtting a data byte to DBUFF. The data is received and transmitted btt 0 first.
EPT
7:3
0
Echo Protector Tone Enable. When control btt EPT is a 1, an unmodulated carrier is transmitted for 187.5 ms followed by 20 ms of no transmitted energy prior to the transmission of
the training sequence. When EPT Is a 0, neither the echo protedor tone nor the 20 ms of no
energy are transmitted prior to the transmission of the training sequence except in V.29
which transmtts 20 ms of silence at the beginning of training.
EQFZ
9:5
0
Equalizer Freeze. When control btt EQFZ is a 1, updating of the receiver's adaptive
equalizer taps is inhlbtted.
3-93
- - - - - - --- -- ---- --- -- --
•
R96MFX
9600 bps MONOFAX Modem
Table 10. R96MFX Interface Memory Bit Definitions (Cont'd)
Mnemonic
FED
Memory
Location
F:7,6
Default
Value
-
Name/Description
Fast Energy Detector. Status bits FED indicates the levei 01 the received signal according
to the following codes.
Energy Level
FED
No energy
Invalid
Above Turn-off Threshold
Above Turn-on Threshold
0
1
2
3
FRI
FR2
FR3
8:5
8:6
8:7
0
0
0
Frequency No.1. The one state of FRI indicates that energy is above tone detector l's
detected turn on threshold (defau~ detection range 2100 Hz ± 25 Hz in non-Group 2
mode). FR~perable in FSK, Group 2, and tone modes. (i.e., CONF 20, 40, 80; with
RTSP and RTS 011.)
=
=
Frequency No.2. The one state of FR2 indicates that energy is above tone detector 2's
detected turn on threshold (default detection range 1100Hz ± 30 Hz in non-Group 2
mode). FR2 is operable in FSK, Group 2, and tone modes. (i.e., CONF 20, 40, 80; with
RTSP and RTS off.)
=
=
Frequency No.3. The one state of FR3 indicates that energy is above tone detector 3's
detected turn on threshold (default detection range 462 Hz ± 14 Hz in non-Group 2 mode).
FR3 is operable in FSK, high speed, Group 2, and tone modes. (i.e., CONF 14, 12, II,
OA, 09, 20, 40, 80; with RTSP and RTS off.)
=
=
G2FGC
0:3
0
Group 2 Fast Gain Control. The one state of G2FGC selects a fast AGC rate (8.6 times
standard) in Group 2 Facsimile.
IAI
lE:6
-
Interrupt Active 1. When Interru.E!!'nable 1 is enabled (lEI is a 1) and BAI is set to a 1 by
the modem, the modem asserts IRQ and sets status bit IAI to a 1 to indicate that BAI going
to a 1 caused the interrupt. The host writing to or reading from register 0:0 resets IA 1 to a O.
(See lEI and BAI ,)
1A2
lE:7
-
Interrupt Active 2. When Interru.E!!'nable 2 is enabled (IE2 is a 1) and BA2 is set to a 1 by
the modem, the modem asserts IRQ and sets status bit IA2 to a 1 to indicate that BA2 going
to a 1 caused the interrupt. The host writing to or reading from register 10:0 resets IA2 to a
O. (See IE2 and BA2.)
lEI
lE:2
0
Interrupt Enable 1. When control bit lEI is a 1 (interrupt enabled), the modem will assert
IRQ and set IAI to a 1 when BAI is set to 1 by the DSP. When IE1 is a 0 (interrupt disabled) , BA1 has no effect on IRQ and IA 1. (See BA 1 and IA 1,)
IE2
lE:5
0
Interrupt Enable 2. When control bit IE2 is a 1 (interrupt enabled), the modem will assert
IRQ and set IA2 to a 1 when BA2 is setto 1 by the DSP, When IE2 is a 0 (interrupt disabled), BA2 has no effect on IRQ and IA2, (See BA2 and IA2,)
POM
7:5
0
Parallel Data Mode. When control bit POM is a 1 and the modem is a transmitter, it accepts
data for transmission from DBUFF (10:0-7) rather than the TXD input, When POM is a 1 and
the modem is a receiver, the modem provides the received data to the host using OBUFF
(10:0-7),
PN
0:6
-
PN Sequence Detected. When status bit PN is a I, the receiver is detecting the PN portion
of the training sequence, When PN is a 0, PN is not being detected.
RTSP
7:7
0
Request To Send Parallel, The one state of RTSP begins a transmit sequence, The
modem will continue to transmit until RTSP is turned off, and the turn-off sequence has
been completed, RTSP parallels the operation of the hardware RTSP control input. These
inputs are "ORed" by the modem,
3-94
I
9600 bps MONOFAX Modem
R96MFX
Table 10. R96MFX Interface Memory Bit Definitions (Cont'd)
Mnemonic
Memory
Location
Default
Value
Name/Description
AX
D:7
-
Receive State. When status bit AX is a 1, the modem is in the receive state and is not trans·
mitting.
SETUP
1F:0
0
Setup. Control bit SETUP bit must be set to a 1 by the host after the host writes a configura·
tion code into the CONF bits (register 6:0-7) or changes a bit in 7:0-6 (register 7 btts 0
through 6). This informs the modem to implement the configuration change. The modem
resets the SETUP bit to a 0 when the configuration change is implemented.
SQEXT
7:2
0
Squelch Extend. When control bit SQEXT is a 1, the modem's receiver is inhibited from the
reception of any signal for 140 ms after the transmitter turn·off.
T2
7:1
0
T/2 Equalizer Select. When control bit T2 is a 1, the linear section of the receiver's adaptive
equalizer is T/2 fractionally spaced. When T2 is a 0, the equalizer is T spaced (T = 1 baud
time).
TOIS
7:6
0
Training Disable. When control bit TOIS is a 1, the modem as a receiver is prevented from
recognizing a training sequence and enterin~ training state; as a transmitter the modem
will not transmit the training sequence when RTS or RTSP is activated.
WRT1
5:1
0
RAM Write 1. When control bit WRT1 is a 1 and ACC1 is set to a 1, the modem wrttes the
data from the Y RAM Data 1 registers into its internal RAM at the location addressed by
ADD1 and CR1. (When the most significant bn of ADD1 is a 0, the write is performed to the
X RAM location; when a 1, the wrtte is to the Y RAM location.) When WRT1 is a 0 and
ACC1 is set to a 1, the modem reads data from its internal RAM from the locations ad·
dressed by ADD1 and CR1 and stores n into the X RAM Data 1 registers and Y RAM Data 1
registers, respectively.
WRT2
15:1
0
RAM Write 2. When control bit WRT2 is a 1 and ACC2 is set to a 1, the modem wrnes the
data from the Y RAM Data 2 registers into its internal RAM at the location addressed by
ADD2 and CR2. (When the most significant b~ of ADD2 is a 0, the write is performed to the
X RAM location; when a 1, the write is to the Y RAM location.) When WRT2 is a 0 and
ACC2 is set to a 1, the modem reads data from its internal RAM from the locations ad·
dressed by ADD2 and CR2 and stores n into the X RAM Data 2 registers and Y RAM Data 2
registers, respectively.
XDAL1
2:0-7
-
X RAM Data 1 LSB. XDAL 1 is the least significant byte of the 16·bit X RAM 1 data word
used in reading X RAM locations.
XDAL2
12:0-7
-
X RAM Data 2 LSB. XDAL2 is the least significant byte of the 16-bit X RAM 2 data word
used in reading X RAM locations.
XDAM1
3:0-7
-
X RAM Data 1 MSB. XDAM1 is the most significant byte of the 16-bit X RAM 1 data word
used in reading X RAM locations.
XDAM2
13:0-7
-
X RAM Data 2 MSB. XDAM2 is the most significant byte of the 16-bit X RAM 2 data word
used in reading X RAM locations.
YDAL1
0:0-7
-
Y RAM Data 1 LSB. YDAL 1 is the least significant byte of the 16-bit Y RAM 1 data word
used in reading or writing Y RAM locations in the modem.
YDAL2
10:0-7
-
Y RAM Data 2 LSB. YDAL2 is the least signi1icant byte of the 16-bit Y RAM 2 data word
used in reading or writing Y RAM locations in the modem.
YDAM1
1:0-7
-
Y RAM Data 1 MSB. YDAM1 is the most significant byte of the 16-bit Y RAM 1 data word
used in reading or writing Y RAM locations in the modem.
YDAM2
11 :0-7
-
Y RAM Data 2 MSB. YDAM2 is the most significant byte of the 16-bit Y RAM 2 data word
used in reading or writing Y RAM locations in the modem.
3-9S
•
9600 bps MONOFAX Modem
R96MFX
selected by the BR1 and BR2 bits. The baud rate is determined by the selected configuration, but the sample rate is
fixed at 9600 Hz, except in Group 2 where the sample rate
is 10368 Hz.
DSP RAM ACCESS
Table 11 provides the RAM access functions, codes, and
registers.
DSP RAM Organization
Two RAM Access bits in the DSP interface memory tell the'
DSP to access the X RAM and/or Y RAM. The transfer is
initiated by the host setting the ACC1 and/or the ACC2
bit(s). The DSP tests these bits each baud or sample
period, except in G2, FSK and Tone mode where these
bits are always tested at the sample period, except in G2,
FSK or Tone mode where these bits are always tested at
the sample period.
The DSP contains 16-bit words of random access memory
(RAM). Because the DSP is optimized for performing complex arithmetic, the RAM is organized into real (X RAM)
and imaginary
RAM) parts. The host processor can
read or write both the X RAM and the Y RAM.
rr
Interface Memory Access to DSP RAM
The interface memory acts as an intermediary during host
to DSP RAM, or DSP RAM to host, data exchanges. The
address stored in DSP interface memory RAM Address
registers by the host determines the DSP RAM address for
data access.
If parallel data mode is selected, RAM access associated
with RAM Address 2 is disabled and only RAM access associated with RAM Address 1 is available.
The 16-bit words are transferred between DSP RAM and
DSP interface memory once each baud or sample time, as
Table 11. R96MFX RAM Access Codes
Function
BRx
CRx
ADDx
Read Reg. No.
Received Signal Samples
0
0
15
Received Signal Samples FSK
Demodulator Output
Lowpass Fitter Output
0
0
0
31
2,3
13
02
0,1,2,3
0,1,2,3
0
0
Average Energy
0
0
AGC Gain Word
Tone 1 Frequency
0
0
0
0
Tone 1 Level
Tone 2 Frequency
Tone 2 Level
Output Level
0
1
Equalizer Input (Real)
Equalizer Input (Imag)
1
1
0
0
1
1
0
1
0
0
0
14
15
21
22
2,3
2,3
2,3
i
2,3
2,3
22
23
2,3
2,3
2,3
21
1
1E
1E
0,1
0,1
0,1,2,3
Equalizer Tap Coefficients
Unrotated Equalizer Output
1
1
0
38 - 5F
1C
0,1,2,3
Rotated Equalizer Output (Eye Pattern)
1
1
17
0,1,2,3
Decision Points (Ideal)
1
1
0
1
17
1D
0,1,2,3
1
1
OC
0,1
1
1
0
1
1
1
18
OD
0
0
1
Error Vector
Rotation Angle
Frequency Correction
Eye Quality Monitor (EQM)
Turn-on Threshold (RLSD)
Tum-off Threshold (RLSD)
Group 2 PLL Frequency Correction
0
0
Group 2 Zero Crossing Threshold (Negative)
Group 2 Zero CrOSSing Threshold (Positive)
0
0
Group 2 AGC Slew Rate
Group 2 Black-White Threshold
0
0
1
0
Group 2 Phase Limit Value
0
Receiver Sensitivity
0
3-96
0
37
B7
OD
19
99
0,1,2,3
2,3
2,3
2,3
0,1
2,3
2,3
0,1
05
2,3
0
24
1A
2,3
2,3
1
24
2,3
9600 bps MONOFAX Modem
R96MFX
If IE1 and/or IE2 is a 1, IRQ is also asserted and IA1 and/or
1A2 is set to a 1 when BA1 and/or BA2 is set to a 1 by the
DSP. IA1 and/or 1A2 is cleared by writing into YDAL1
and/or YDAL2, which causes IRQ to return high if no other
interrupt requests are pending.
DSP RAM Read Procedure
The RAM read procedure is a 32-bit transfer from DSP
RAM to the interface memory which transfers both the X
RAM and Y RAM simultaneously. Before reading from
DSP interface memory, set ACC1 and/or ACC2 to a 0,
then reset BA1 or BA2 by reading YDAL1 or YDAL2. Set
WRT1 and/or WRT2 to a a to inform the DSP that a RAM
read will occur when ACC1 and/or ACC2 is set to a 1. Load
the RAM address into RAM Address 1 and/or RAM Address 2, then set CR1 and/or CR2 appropriately. Set
ACC1 and/or ACC2 to a 1 to signal the DSP to perform the
RAM read. When the DSP has transferred the contents of
RAM into the interface memory RAM Data registers, BA1
and/or BA2 will be set.
PERFORMANCE
lYPICAL BIT ERROR RATES
The bit error rate (BER) performance of the modem is
specified for a test configuration conforming to that
specified in cClrr Recommendation V.56. Bit error rates
are measured at a received line signal level of -20 dBm as
illustrated.
Typical BER performance is shown in Figure 8.
IflE1 and/or the IE2 is a 1, IRQ is also asserted when BA1
and/or BA2 set to a 1 by the DSP. When IRQ is asserted,
IA1 and/or 1A2 goes to a 1 to inform the host that setting of
BA1 and/or BA2 was the cause. IA1 and/or 1A2 is cleared
~he host reading YDAL1 and/or YDAL2, which causes
IRQ to return high if no other interrupt requests are pending.
The curves shown in Figure 8 were prepared from data obtained using a TAS 1000 communication test system .
lYPICAL PHASE JITTER
At 2400 bps, the modem exhibits a bit error rate of 10--6 or
less with a signal-to-noise ratio of 12.5 dB in the presence
of 15° peak-to-peak phase jitter at 150 Hz or with a signalto-noise ratio of 15 dB in the presence of 30° peak-to-noise
phase jitter at 120 Hz.
DSP RAM Write Procedure
The RAM write procedure is a 16-bit transfer from interface
memory to DSP RAM allowing the transfer of X RAM data
or Y RAM data to occur each baud or sample time. Before
writing to DSP interface memory, set ACC1 and/or ACC2
to a 0; then reset BA 1 or BA2 by reading YDAL1 or
YDAL2, respectively. Set WRT1 and/or WRT2 to a 1 to inform the DSP that a RAM write will occur when ACC1
and/or ACC2 is set to a 1. Load the RAM address into RAM
Address 1 and/or RAM Address 2, then set CR1 and/or
CR2 appropriately. Write the desired data into the interface memory RAM Data registers YDAL1 and YDAM1
and/or YDAL2 and YDAM2, then set ACC1 and/or ACC2
to a 1 to signal the DSP to perform the RAM write. When
the DSP has transferred the contents of the interface
memory RAM Data registers into RAM, BA1 or BA2 will be
set.
At 4800 bps 0/.27 ter) , the modem exhibits a bit error rate
of 10--6 or less with a signal-to-noise ratio of 19 dB in the
presence of 15° peak-to-peak phase jitter at 60 Hz.
At 7200 bps 0/.29), the modem exhibits a bit error rate of
10--6 or less with a signal-to-noise ratio of 25 dB in the
presence of 12 peak-to-peak phase jitter at 300 Hz.
At 9600 bps, the modem exhibits a bit error rate of 10--6 or
less with a signal-to-noise ratio of 23 dB in the presence of
10· peak-to-peak phase jitter at 60 Hz. The modem exhibits a bit error rate of 10-5 or less with a signal-to-noise
ratio of 23 dB in the presence of 20° peak-to-peak phase
jitter at 30 Hz.
3-97
•
R96MFX
9600 bps MONOFAX Modem
V27,2400
\
F~K
V29,4800
V27,4800
V29,7200
/V29,9600
r
10- 3
10- 3
V27,2400
V29,4800
K
V27,4800
V29,7200
V29,9800
I
\
10-'
10-'
\
1&1
i
II:
I
\\
1&1
Ii
10- 5
\
10- 8
0
5
,
\
III
!CII:
II:
iII:
\
III
Ii10-
\
5
\
\
\\
15
20
10
Signal to Noise Ratio in dB
\
10- 8
25
0
Typical Bit Error Rate
(Back.ta-Back, T Equalizer, Level - 20 dBm)
5
I
\
\
10
15
20
Signal to Noise Ratio In dB
\
25
Typical Bit Error Rate
(Unconditioned 3002 Line, T Equalizer Level - 20 dBm)
Figure 8. R96MFX Typical Bit Error Rate (BER) Curves
3·98
9600 bps MONOFAX Modem
R96MFX
APPLICATION
Table 13. TCO·706AB Oscillator SpeCifications
RECOMMENDED MODEM INTERFACE CIRCUIT
The R96MFX is supplied as a 64-pin QUIP (Quad In-line
Package) device to be designed into original equipment
manufacturer (OEM) circuit boards. The recommended
modem interface circuit (Figure 9) and parts list (Table 12)
illustrate the connections and components required to
connect the modem to the OEM electronics.
Characteristic
Frequency
Frequency Stability
vs. Temperature
VS. input Voltage
vs. Aging
Frequency Tolerance
Frequency Adjustment
by Internal Trimmer
Operating Temperature
Input Voltage
Output
Symmetry
Drive
Type
If the auxiliary analog input (pin 26) is not used, resistors
Rl0 and R16 can be eliminated and pin 26 must be connected to analog ground (pin 24). When the cable
equalizer controls CABLEl and CABLE2 are connected to
long leads that are subject to picking up noise spikes, a 3K
ohm series resistor should be used on each input (pins 32
and 33) for isolation.
Resistors R7 and R17 can be used to trim the transmit
level and receive threshold to the accuracy required by the
OEM equipment. For a tolerance of ±1 dBm, the 1% resistor values shown are correct for more that 99.8% of the
units.
Package
Value
24.00014 MHz
± 5 ppm (O"C - 60'C)
± 1 ppm at 4.75 V - 5.25 V
1 ppm/year
±2ppm
± 5 ppm min.
O'C - 60' C
5.0 V ± 0.5% (4.75 V - 5.25 V)
50% ± 10% (40% - 60%)
CL=15pF
CMOS: Low: 0.5 V,
High: Vee (4.5 V)
14-pin DIP
Table 12. Typical R96MFX Modem Interface Parts List
Component
Designation
C1t, C13
C7,C8,C9,CI2,C14
C4,C6
Cl0
C5
C2
C3
R4
R12
R10,R16
R2,R6
RI8
R7
R17
R11
R14,R15
R5
CR1
Y1
Y2
Component
Value
1000 pF ±5%, 50V
0.1 ",F ±2O%,50V
0.33 ",F ±20%, 50V
1.0 ",F ±20%, 50V
10.0 ",F ±10%, 25V
18 pF ±5%, 50V
39 pF :05%, SOV
3Q±5%,1/4W
255 Q :01%, 1/4W
1 KQ±5%, 1/4W
3 KQ ±5%, 1/4W
10 KQ ±1%.1/4W
34.8 KQ",1%, 1/4W
46.4 KQ±I%, 1/4W
36.5 KQ±1%. 1/4W
86.6 KQ±I%. 1/4W
2.7 MQ± 5%. 1/4W
-5.1 V 1%, regulator
24.00014, MHz
24.00014, MHz
Manufacturer's
Part Number
C124Cl02J5G5CA
592CX7Rl04M050B
Suggested
Manufacturer
Keme!
Sprague
SMCSOTI ROM5X12
ECEBEF100
United Chern-con
Panasonic
43CX3ROOOJ
Mepco Electra
5043CXl KOOJ
5043CX3KOOJ
Mepco Electra
Mepco Electra
CRB 1/4XF46K4
CRB 1/4XF36K5
CML 1/10T86.6KQ±1%
5043CX2M700J
lN4625D
R-Ohm
R-Ohm
Dale Electronics
Mepco Eletra
Motorola
TCO-706AB 1
Toyocom
Note: 1. See Table 13 for specifications. The TCO-706ABI is the only square w;ave generator recommended. A sine wave oscillator
may alternativly be used (See Note 3 in Figure 9).
3-99
•
9600 bps MONOFAX Modem
R96MFX
R43.0
+ 5V
-r-r---:---~--...,
C13
1000 pF
R1586.6K
~-.---r-+ 12V
Cll
1000 pF
R14 86 6K
R18
10K
CABLEl
CABLE2
AUXIN
R16
10K
NOTES:
1. NC INDICATES DO NOT CONNECT.
2. CONFIGURATION WHEN GROUP 2
NOT REQUIRED.
Y1: 24.00016 MHz
PARALLEL RESONANT
CL = 18 PF
Rs = 25!l MAX.
3. THE OSCILLATOR SPECIFIED IN TABLE 13
IS A SQUARE WAVE GENERATOR. A SINE
WAVE OSCILLATOR OF EQUAL ACCURACY
MAY BE USED, BUT THE INPUT TO PIN 6
MUST BE CAPACITIVELY COUPLED (e.g., 0.1,.1')
AND THE OSCILLATOR OUTPUT MUST BE 3.5
VOLTS PEAK-TO-PEAK :t 14% OVER THE
MODEM'S OPERATING ENVIRONMENTAL RANGE.
Figure 9_ Recommended R96MFX Modem Interface Circuit
3-100
9600 bps MONOFAX Modem
R96MFX
Table 14. Pin Noise Characteristics
PC BOARD LAYOUT CONSIDERATIONS
1. The R96MFX and all supporting analog circuitry, including the data access arrangement if required,
should be located on the same area of printed circuit
board.
Noise Source
High
Low
1
2
12
2. All power traces should be at least a 0.1 inch width.
17
3. If the power source is located more than approximately 5 inches from the modem, a decoupling capacitor
of 10 IlF or greater should be placed in parallel with
C4 near pins 10 and 49.
18
19
20
21
30
38
39
40
41
44
50
51
52
53
54
55
56
57
58
59
60
61
62
63
4. All circuitry connected to pins 6 and 7 should be kept
short to prevent stray capacitance from affecting the
oscillator.
5. Pin 22 should be tied directly to pin 24 at the modem
package. Pin 24 should tie directly, by a dedicated
path, to the common ground point for analog and digital ground.
6. An analog ground plane should be supplied beneath
all analog components. The analog ground plane
should connect to pin 24 and to all analog ground
points shown in Figure 10.
7. A digital ground plane should be supplied to cover the
remaining allocated area. The digital ground plane
should connect to pin 49 and to all digital ground
pOints shown in Figure 10, plus the crystal-can
ground.
8. The modem package should be oriented relative to
the two ground planes so that the end containing pin
1 is toward the digital ground plane and the end containing pin 32 is toward the analog ground plane.
64
9. As a general rule, digital signals should be routed on
the component side of the PCB while the analog signals are routed on the solder side. The sides may be
reversed to match a particular OEM requirement.
10. Routing of the modem signals should provide maximum isolation between noise sources and sensitive
inputs. When layout requirements necessitate routing
these signals together, they should be separated by
neutral signals. Refer to Table 14 for the noise characteristics of each modem pin.
3-101
6
7
8
9
11
14
15
16
45
46
48
Neutral
3
4
5
10
13
22
24
25
29
31
34
42
43
47
49
Noise Sensitive - Low
HJgh
23
27
32
33
35
36
37
26
28
II
9600 bps MONOFAX Modem
R96MFX
Table 14. Pin Noise Characteristics
PC BOARD LAYOUT CONSIDERATIONS
1. The R96MFX and all supporting analog circuitry, including the data access arrangement if required,
should be located on the same area of printed circuit
board.
Noise Source
High
Low
1
2
12
2. All power traces should be at least a 0.1 inch width.
17
3. If the power source is located more than approximately 5 inches from the modem, a decoupling capacitor
of 10 ftF or greater should be placed in parallel with
C4 near pins 10 and 49.
18
19
20
21
30
38
39
40
41
44
50
51
52
53
4. All circuitry connected to pins 6 and 7 should be kept
short to prevent stray capacitance from affecting the
oscillator.
5. Pin 22 should be tied directly to pin 24 at the modem
package. Pin 24 should tie directly, by a dedicated
path, to the common ground point for analog and digital ground.
6. An analog ground plane should be supplied beneath
all analog components. The analog ground plane
should connect to pin 24 and to all analog ground
points shown in Figure 10.
6
7
8
9
11
14
15
16
45
46
48
Neutral
3
4
5
10
13
22
24
25
29
31
34
42
43
47
49
Noise Sensitive
High
Low
23
27
32
33
35
36
37
26
28
54
55
56
57
58
59
60
61
62
63
64
7. A digital ground plane should be supplied to cover the
remaining allocated area. The digital ground plane
should connect to pin 49 and to all digital ground
points shown in Figure 10, plus the crystal-can
ground.
8. The modem package should be oriented relative to
the two ground planes so that the end containing pin
1 is toward the digital ground plane and the end containing pin 32 is toward the analog ground plane.
9. As a general rule, digital signals should be routed on
the component side of the PCB while the analog signals are routed on the solder side. The sides may be
reversed to match a particular OEM requirement.
10. Routing of the modem signals should provide maximum isolation between noise sources and sensitive
inputs. When layout requirements necessitate routing
these Signals together, they should be separated by
neutral Signals. Refer to Table 14 for the noise characteristics of each modem pin.
3-102
MD47·3
R96EFX
MONOFAX Modems
'1'
R96EFX 9600 bps MONOFAX® Modem
with Error Detection
Rockwell
INTRODUCTION
FEATURES
Single 64-pin QUIP
CCID V.29, V.27 ter and V.27 ter short train option,
T.30, V.21 Channel 2, T.4, T.3
Group 3 and Group 2 Facsimile Transmission/
Reception
Half-Duplex (2-Wire)
Programmable Dual Tone Generation
Programmable Tone Detection
Programmable Turn-on and Turn-off Thresholds
Programmable Transmit Output Level
HDLC Framing at All Speeds
Programmable Interface Memory Interrupt
Diagnostic Capability
Allows Telephone Line Quality Monitoring
Equalization
Automatic Adaptive
Compromise Cable (Selectable)
DTE Interface: Two Alternate Ports
Selectable Microprocessor Bus (6500 or 8085)
CCID V.24 (RS-232-C Compatible) Interface
TIL and CMOS Compatible
Low Power Consumption: 500 mW (Typical)
The Rockwell R96EFX MONOFAX is a synchronous 9600
bits per second (bps) half-duplex modem with error detection in a single 64-pin quad-in-line package (QUIP). The
R96EFX can operate over the public switched telephone
network (PSTN) through line terminations provided by a
data access arrangement (DAA).
The modem satisfies the telecommunications requirements specified in CCID recommendations V.29, V.27
ter, V.21 Channel 2, T.3, and T.4, and the binary signaling
requirements of T.30. The R96EFX can operate at speeds
of 9600,7200, 4800,2400, and 300 bps, and also includes
the V.27 ter short training sequence option. The R96EFX
can also perform HDLC framing according to T.30 at
speeds of 9600, 7200, 4800, 2400, and 300 bps.
The R96EFX is designed for use in Group 3 and Group 2
facsimile machines. The modem's small size and low
power consumption allow the design of compact system
enclosures for use in both office and home environments.
MONOFAX is a regIstered trademark of Rockwell InternatIOnal
RS2
RS3
RS'
READ·02
RS1
RSO
NC
EN85
PORI
XTLI
XTLO
CS
WRITE-R/VI
IRO
DO
12 MHz
6 MHz
+SVD
01
02
DCLKI
SYNCIN2
DGN01
CTS
TXO
OCLK
EYESYNC
EYECLK
EYEX
ADiN
03
D.
05
06
07
AGND1
AGCIN
AGND2
-SVA
DGN02
RTS
RCVO
RLSO
RXD
EYEY
PORO
RCI
SYNCIN1
DAIN
AUXI
FOUT
TXOUT
ECLKIN2
RXIN
DAOUT
AEE
ECLKIN1
+5VA
CABLE1
ADOUT
36
AOUT
35 ===:J FIN
34
ACVI
' - -_ _ _ _~33~
CABLE2
R96EFX 9600 bps MONOFAX Modem with Error
Detection
R96EFX Pin Assignments
Document No. 29200N49
Data Sheet
(Preliminary)
3-103
Order No. MD49
Rev. 2, January 1989
II
9600 bps MONOFAX Modem with Error Detection
R96EFX
TECHNICAL SPECIFICATIONS
TRANSMITTED DATA SPECTRUM
CONFIGURATIONS, SIGNALING RATES AND DATA
RATES
The transmitted data spectrum is shaped in the baseband
by an excess bandwidth finite impulse response (FIR) filter with the following characteristics:
The selectable modem configurations, along with the corresponding signaling (baud) rates and data rates, are
listed in Table 1.
When operating at 2400 baud, the transmitted spectrum is
shaped by a square root of 20% raised cosine filter. This
filter shapes the spectrum so that with continuous binary
ones applied, the resulting transmitted spectrum has a
substantially linear phase characteristic over the band of
700 Hz to 2700 Hz, and the energy density at SOO Hz and
2900 Hz is attenuated 4.S :t 2.S dBm with respect to the
maximum energy density between SOO Hz and 2900 Hz.
TONE GENERATION
Under control of the host processor, the modem can
generate voice-band single or dual tones from 0 Hz to
4800 Hz with a resolution of 0.1S Hz and an accuracy of
0.01%. Tones over 3000 Hz are attenuated. Dual tone
generation allows the modem to operate as a programmable DTMF dialer.
When operating at 1600 baud, the transmitted spectrum is
shaped by a square root of SO% raised cosine filter. This
filter shapes the spectrum so that with continuous binary
ones applied, the resulting transmitted spectrum has a
substantially linear phase characteristic, and the energy
density at 1000 Hz and 2600 Hz is attenuated 3.0 :t 2.0
dBm with respect to the maximum energy density between
1000 Hz and 2600 Hz.
DATA ENCODING
The data encoding conforms to CCITT recommendations
V.29, V.27, V.21 Channel 2, and T.3.
CABLE EQUALIZERS
Equalization functions are provided that improve performance when operating over low quality lines.
When operating at 1200 baud, the transmitted spectrum is
shaped by a square root of 90% raised cosine filter. This
filter shapes the spectrum so that with continuous binary
ones applied, the resulting transmitted spectrum has a
substantially linear phase characteristic, and the energy
density at 1200 Hz and 2400 Hz is attenuated 3.0 :t 2.0
dBm with respect to the maximum energy density between
1200 Hz and 2400 Hz.
The integrated analog section of the R96EFX has selectable cable equalizers with the characteristics shown in
Table 2. Choose specific cable equalizers by strapping
CABLE1 and CABLE2 to either +SV or GND (see
Hardware Interface). The chosen filter functions in both
transmit and receive paths depending on operating mode.
The transmit spectrum characteristics assume that the
cable equalizers are disabled.
ADAPTIVE EQUALIZER
An adaptive equalizer in V.29 and V.27 modes compensates for transmission line amplitude and group delay distortion.
Table 2. Cable Equalizer Characteristics
Gain dB Relative 10 1700 Hz
Frequency
(Hz)
700
1500
2000
3000
Confi!luration
Modulation1
V.2996OO
OAM
V.2972OO
OAM
QAM
V.29 4800
V.2748OO
DPSK
DPSK
V.27 2400
V.21300
FSK
T.3 (Group2)
VSAMPM
Single and Dual
Tone Transmit
Notes:
1. Modulation legend:
Carrier
Frequency
(Hz)
",0.01%
Data
Rate
(bps)
",0.01%
1700
1700
1700
1800
1600
1650,1850
2100
QAM
DPSK
FSK
VSAMPM
9600
7200
4800
4800
2400
300
-
for Len!lth of 0.4 mm Cable
0
0.00
0.00
0.00
0.00
Baud
(Symbols/Sec.)
2400
2400
2400
1600
1200
300
-
1.8km
-0.99
-0.20
+0.15
+1.43
Bits
per
Svmbol
4
3
2
3
2
1
-
O.adrature Amplitude Modulation
Differential Phase Shift Keying
Frequency Shift Keying
Vestigial Sideband Amplitude Modulation - Phase Modulation
3-104
3.6km
-2.39
-0.65
+0.87
+3.06
7.2km
-3.93
-1.22
+1.90
+4.58
Constellation
Points
16
8
4
8
4
-
R96EFX
9600 bps MONOFAX Modem with Error Detection
The out-of-band transmitter energy levels in the 4 kHz50 kHz frequency range are below -55.0 dBm.
The RLSD threshold levels can be programmed over the
following range:
TURN-ON SEQUENCE
Turn on: -10 dBm to -47 dBm
Turn off: -10 dBm to -52 dBm
Transmitter turn-on sequence times are shown in Table 3.
RECEIVER TIMING
TURN-OFF SEQUENCE
The timing recovery circuit can track a:t 0.01 % frequency
error in the associated transmit timing source.
For V.27 ter, the turn-off sequence consists of approximately 10 ms of remaining data and scrambled ones
at 1200 baud or approxim ately 7 ms of data and scram bled
ones at 1600 baud followed by a 20 ms period of no transmitted energy. For V.29, the turn-off sequence consists of
approximately 5 ms of remaining data and scrambled ones
followed by a 20 ms period of no transmitted energy. In
V.21, the transmitter turns off within 7 ms after RTS goes
false. In Group 2 the transmitter turns off within 200 l-Is
after RTS goes false. When operating in parallel data
mode, the turn-off sequence may be extended by 8 bit
times.
CARRIER RECOVERY
The carrier recovery circuit can track a :t 7 Hz frequency
offset in the received carrier with less than a 0.2 dBm
degradation in bit error rate (BER).
CLAMPING
Received Data (RXD) is clamped to a constant mark
whenever the Received Line Signal Detector (RLSD) is off.
TONE DETECTION
TRANSMIT LEVEL
The tone detector signal path is separate from the main
received signal path enabling tone detection to be independent of the receiver status. Tone detector 3 operates
in all receive modes.
The transmitter output level is programmable in the DSP
RAM from 0 dBm to -15.0 dBm and is accurate to :t 1.0
dBm. The output level is adjusted by the modem by digitally scaling the output to the transm itters digital-to-analog
converter.
SCRAMBLER/DESCRAMBLER
The filter coefficients of each filter are host programmable
in RAM. The output of the tone detector filter goes to an
energy detector.
The modem incorporates a self-synchronizing
scrambler/descrambler in accordance with CCITT V.29 or
V.27 recommendations, depending on the selected configuration.
The modem power and environmental requirements are
shown in Tables 4 and 5, respectively.
GENERAL SPECIFICATIONS
RECEIVE LEVEL
The receiver satisfies V.29 and V.27 performance requirements for received line signal levels from 0 dBm to -43
dBm. An external input buffer and filter must be supplied
between the Receiver Analog Input (RXA) and RXIN. The
received line signal level is measured at the RXA input.
The default turn on and turn off RLSD threshold levels are
- 43 dBm and - 48 dBm, respectively. These levels are
measured with an unmodulated 2100 Hz tone at RXA.
Table 4. Power Requirements
Voltage
+5 VDC±5%
--5VDC ±5%
Note:
Table 3. Turn-On Sequences
Current (Typ.)
@2SoC
Current (Max.)
@ooc
85mA
15mA
< 125mA
s30mA
All voltages must have ripple less then 0.1 volts peak-to·
peak. If a switching supply is chosen. the user may
select any frequency between 20 KHz and 150 KHz so
long as no component of the switching frequency is
present outside of the power supply with an amplitude
greater than 500 !-tV peak.
~BTS
Configuration
On to CTS On
Echo
Echo
Protector
Protector
Tone
Tone
Disabled
Enabled
V.29 (All Speeds)
253 ms
441 ms
V.27 4800 bps Long Train
708rns
913 ms
V.27 4800 bps Short Train
50ms
255 ms
V.27 2400 bps Long Train
943ms
1148ms
V.27 2400 bps Short Train
67ms
272 ms
V.21 300 bps
Group 2
s14ms
s14ms
s400 ""
s400 ""
Table 5. Environmental Requirements
Parameter
Temperature
Operating
Storage
SpeCification
0' C to +70' C (32 0 F to 158° F)
-40' C to +80' C (-40° F to 176° F)
(Stored in a SUITable anti-static
container)
Relative Humidity
3-105
Up to 90% noncondensing.
or a wet bulb temperature up to
35° C, whichever is less.
•
9600 bps MONOFAX Modem with Error Detection
R96EFX
The hardware interconnect signals shown in Figure 1 are
organized into eight functional groups: power,
microprocessor interface, V.24 interface, cable equalizer,
analog signals, overhead, reserved, and serial diagnostic
interface. These signals, along with their connector pin
numbers and interface circuit types, are listed in Table 6.
The digital interface characteristics are defined in Table 7.
HARDWARE INTERFACE SIGNALS
The functional interconnect diagram (Figure 1) shows the
typical modem connection in a system. In this diagram,
any point that is active when exhibiting the relatively more
negative voltage of a two-voltage system (e.g., 0 VDC for
TIL or -12 VDC for RS-232-C) is called active low and is
represented by a small circle at the signal pOint. The particular voltage levels used to represent the binary states
do not change the logic symbol.
POWER-ON-RESET
When power is applied to the modem, the modem pulses
Power-On-Reset (POR) low to begin the POR sequence.
350 ms after the low-to-high transition of POR, the modem
is ready to use. The POR sequence is reinitiated any time
the + SV supply drops below + 3.SV for more than 30 ms,
or an external device drives POR low for at least 3 j.ls. POR
is not pulsed low by the modem when the POR sequence
is initiated externally. The POR sequence initializes the
modem interface memory (Table 10) to default values.
This action leaves the modem configured as follows:
Two types of I/O points that may cause confusion are
edge-triggered inputs and open-collector (open-source or
open-drain) outputs. These signal points include the additional notation of a small triangle or a small half-circle (see
signal IRQ). Active low signals are named with an overscore (e.g., POR).
A clock intended to activate logic on its rising edge (Iowto-high transition) is called active low, while a clock intended to activate logic on its falling edge (high-to-Iow
transition) is called active high. When a clock input is associated with a small circle, the input activates on a falling
edge. If no circle is shown, the input activates on a rising
edge.
---
r
I
RTS
CABLE2
.....
I
V.29 9600 bps
Serial channel data
T Equalizer
Standard echo suppressor tone
-43 dBm receiver tum-on threshold
CTS
CABLEl
I"'"
TXD
I
USRT
(OPTIONAL)
I
I
AUXI
DCLK
I
XLTI
I
.....
RLSD
r
I
L
U~
RXD
-
J
12MHZ_
CRYSTAL
OSCILLATOR
TXOUT
R96EFX
6MHZ_
MONOFAX
RE~D
,
XTLO
(NC)
RXIN
-
- } TELEPHONE
LINE
LINE
INTERFACE
MODEM
WRITE
EYEX
EYEY
DATA BUS (8)
HOST
PROCESSOR
(OTE)
EYESYNC
EYECLK
ADDRESS BUS (5)
+5V
.1--. CS
DECODER 1
~:
_
POR
IRQ
+5
JVV\rJ
EYE
PATTERN
GENERATION
~
-5V
GND
..1..':'
EN85
Figure 1. R96EFX Functional Interconnect Diagram
3-106
..
~@
Y
.. .
••
SCOPE
I
9600 bps MONOFAX Modem with Error Detection
R96EFX
Microprocessor Interface
Chip Select (CS) and Register.Selects (RSO-RS4).
Seventeen address, data, control, and interrupt hardware
interface signals allow modem connection to an 8085 or
6500 bus compatible microprocessor. With the addition of
external logic, the interface can be made compatible with
a wide variety of other microprocessors such as the 8080
or 68000.
The microprocessor interface allows a microprocessor to
change modem configuration, read or write channel and
diagnostic data, and supervise modem operation by writing control bits and reading status bits. The Significance of
the control and status bits, along with the methods of data
interchange, are discussed in the Software Interface Section.
The Chip Select (CS) input enables the modem digital signal processor (OSP) device. The five active high register
select lines (RSO-RS4) address interface memory
registers within the selected OSP interface memory. All six
of these lines are typically connected to the host bus address lines; the register select lines to the five least significant lines (AO-A4), and the chip select line to the next
significant line (AS) through a decoder. The OSP decodes
RSO through RS4 to address one of 32 internal interface
memory registers (00-1 F). The most significant address bit
is RS4 and the least significant address bit is RSO. The
selected register can be read from, or written into, via the
8-bit parallel data bus (00-07). The most significant data
bit is 07 and the least significant data bit is 00.
Table 6. R96EFX Hardware Interface Signals
Table 6. R96EFX Hardware Interface Signals (Cont'd)
Name
Type"
Pin No.
Description
AGNOI
GNO
22
GNO
AGND2
24
OGNOI
GNO
13
OGND2
GNO
49
PWR
3t
+5VA
PWR
+5V0
10
-5VA
PWR
25
Microprocessor Interlace
07
OS
D5
D4
D3
D2
01
DO
RS4
RS3
RS2
RSI
RSO
CS
lNOB
IA/OB
IA/OB
lNOB
1A/0B
lNOB
lNOB
IA/OB
IA
IA
IA
IA
IA
IA
REAO-~_IA
WRITE-RJW IA
IRQ
OC
50
51
52
53
54
55
56
57
62
63
64
1
2
60
61
59
58
PORO
PORI
OCLKl
ECLKlNl
ECLKIN2
SYNCINI
SYNCIN2
Connect to Analog Ground
Connect to Analog Ground
Connect to Digital Ground
Connect to Digital Ground
Connect to Analog +5V Power
Connect to Digital +5V Power
Connect to Analog -5V Power
XTLI
xn.O
12 MHz
6 MHz
RCVI
RCVO
AOIN
AOOUT
OAIN
OAOUT
EN85
AEE
AGCIN
AOUT
FIN
FOUT
RCI
Date Bus Line 7
Date Bus Line 6
Date Bus Line 5
Date Bus Line 4
Date Bus Line 3
Date Bus Line 2
Date Bus Line 1
Date Bus Line 0
Register Select 4
Register Select 3
Register Select 2
Register Select 1
Register Select 0
Chip Select
Read Strobe (808X). cp~lock (65XX)
Write Strobe (808X). RJW (65XX)
Interrupt Request
IA
OA
IA
OA
OA
OA
IB
IB
R
48
14
15
45
46
16
Request to Send
Clear to Send
TransmH Date
Received Data
Received Line Signal Detacted
Transmit and Receive Data Clock
32
33
Cable Select 1
Cable Select 2
28
37
Connect to Smoothing Filter Input
Connect to Anti-aliasing Filter Output
Auxiliary Analog Input
EYEX
EYEY
OA
OA
EYECLK
OA
EYESYNC OA
AA
AB
AC
27
42
Power-On-Reset Output
Power-On-Resetlnput
Connect to OCLK
Connect to EYECLK
Connect to EYECLK
Connect to EYESYNC
Connect to EYESYNC
Connect to Crystal CircuH or Oscillator
Connect to Crystal CircuH or Float
12 MHz Output
6 MHz Output
Connect to RCVO
Mode Select Output
Connect to AOOUT
AOCOutput
Connect to OAOUT
OAC/AGC Output
Connect to Resistor for Bus Selection
Connect to Analog Ground
AGClnput
Smoothing Filter Output
Connect to FOUT
Smoothing Filler Output
RC Junction for POR Time Constant
3
Do Not Connect
43
5
11
30
38
41
t2
6
7
8
9
34
47
20
39
40
21
4
29
23
36
35
19
44
18
17
Pattern
Pattern
Pattern
Pattern
X Output
Y Output
Clock (230.4 kHz)
Strobe (9600 Hz)
OigHai signals are described in Table 7. Analog signals
are described in Table 9.
R = Required overhead connectors; no connection to host
*
equipment.
26
Serial Eye
Serial Eye
Serial Eye
Serial Eye
Notes:
Analoa Slanals
TXOUT
AXIN
AUXI
OE
IA
R
R
R
R
R
IC
R
00
00
R
R
R
R
R
R
R
R
R
R
R
R
R
Serial Diagnostic Interlace
Cable Equallar
CABLEI
CABLE2
Description
Reserved
V.24 Interlace
RTS
CTS
TXO
AXO
RLSO
DCLK
Type* Pin No.
Name
OVerhead
Power
3-107
---------
•
9600 bps MONO FAX Modem with Error Detection
R96EFX
Read Enabl,,2.iREAD.!2) and
Write Enable·RJW (WRITEJR/W)
until all interrupt requests have been serviced (i.e., all IRQ
lines have returned high).
During a read cycle, data from the selected DSP interface
memory register is gated onto the data bus by means of
three-state drivers in each DSP. These drivers force the
data lines high for a one bit, or low for a zero bit. When not
being read, the three-state drivers assume their high-impedance (oft) state.
Because of the open-drain structure of IRQ, an external
pull-up resistor to +5V is required at some point on the IRQ
line. The resistor value should be small enough to pull the
IRQ line high when all IRQ drivers are off O.e., it must overcome the leakage currents). The resistor value should be
large enough to limit the driver sink current to a level acceptable to each driver. If only the modem IRQ output is
used, a resistor value of 5.6K ohms :20%, 0.25 W, is sufficient.
During a write cycle, data from the data bus is copied into
the selected DSP interface memory register, with high and
low bus levels representing one and zero bit states,
respectively.
V.24 INTERFACE
The read/Write cycle timing waveforms are illustrated in
Figure 2 and the timing requirements are shown in
Table 8.
Seven pins provide timing, data, and control signals for implementing a CCITT Recommendation V.24 compatible
serial interface. These signals are TIL compatible in order
to drive the short wire lengths and circuits normally found
within stand-alone modem enclosures or equipment
cabinets. For driving longer cables, these signals can be
easily converted to RS-232-C voltage levels. The transmit
and receive timing is shown in Figures 3 and 4, respectively.
Interrupt Request (IRQ)
The modem Interrupt Request QRQ) output may be connected to the host processor interrupt request input in
order to interrupt hOS!.E!:.ogram execution for immediate
modem service. The IRQ output can be enabled in DSP
interface memory to indicate immediate ch~ of conditions in the modem DSP device. The use of IRQ is optional depending upon modem application. Refer to the
Software Considerations Section for a summary of the
programmable interrupt feature and modem interrupt bits,
interrupt conditions and interrupt clearing procedures.
Transmitted Data (TXD)
The modem obtains serial data to be transmitted from the
local DTE on the Transmitted Data (TXD) input.
Table 8. Microprocessor Interface Timing
The DSP IRQ output structure is an open-drain field-effecttransistor (FET). The modem IRQ output can be wireORed with other IRQ lines in the application system. Any
of these sources can drive the host interrupt input low, and
the host interrupt servicing process normally continues
Parameter
Symbol
CS Setup lime
RSi Setup lime
Data h:cess lime
Data Hold Time
Control Hold lime
Write Data Setup Time
Write Data Hold lime
TCS
TRS
TOA
TOHR
THC
TWOS
TDHW
Min.
Max.
Units
0
-
ns
ns
ns
ns
ns
ns
ns
25
-
75
-
10
10
20
10
-
Table 7. Digital Interface Characteristics
Input/Output Type
Symbol
VIH
Parameter
Input High Voltage
VIL
Input Low Voltage
V
IIH
Input High Current
pA
ill
Input Low Current
rnA
lu
Input Leakage Current
IJA
VOH
Output High Voltage
V
3.5 min.'
3.5 min.'
VOL
Output Low Voltage
V
0.4 max.2
0.4 max. 3
10H
Output High Current
mA
-0.1 max.
-0.1 max.
IOL
Output Low Current
rnA
1.8 max.
0.8 max.
!Lo
Output Leakage Current
IJA
±10max.
± lOmax.
CL
Co
Capacitive Load
Capacitive Drive
pF
100
100
Circu~Type
Unit.
V
IA
2.0 min.
0.8 max.
IB
2.0 min.
IC
(See Note 3
0.8 max.
in Fig. 9)
OB
OC
OD'
OE
40 max.
-0.4 max.
%2.5 max.
5
11 max.
20
10
TTL
CLK
pF
TTL
w/pull·up
Not..:
1. I Load=-l00mA
3. I Load = 0.8 rnA
2.1 Load = 1.6 rnA
OA
TTL
TTL
3-state
3·stete
4. Loads on 12 MHz and 6 MHz outputs must be balanced
3-108
w~in
20%.
2.4 min.'
0.4 max.2
1.6 max.
0.4 max.2
-0.001 max.
40 min.
0.001 max.
0.4 max.
100
50
Open drain
CLK
TTL
R96EFX
9600 bps MONOFAX Modem with Error Detection
READ
WRITE
TCS
RSi
(1=0-4)
•
TDHR
Di
(1=0-7)
a. 8085 Bus Compatible (EN85
=L)
WRITE
READ
TCS
RSI
(1=0-4)
TDA
TDHR
DI
(1=0-7)
b. 6500 Bus Compatible (EN85
=H)
Figure 2. Microprocessor Interface Waveforms
3-109
9600 bps MONOFAX Modem with Error Detection
R96EFX
The RLSD receive level thresholds default to -43 dBm for
the off-to-on threshold and to -48 dBm for the on-to-off
threshold. A minimum hysteresis action of 2 dBm exists
between the actual off-to-on and on-to-off transition levels.
The threshold level and hysteresis action are measured
with an unmodulated 21 00 Hz tone applied to the Receiver
Analog (RXA) input. Note that performance may be
degraded when the received signal level is less than -43
dBm. The RlSD on and off thresholds are host programmable in DSP RAM.
Received Data (RXD)
The modem presents received serial data to the local DTE
on the Received Data (RXD) output.
Request To Send (RTS)
Request to Send (RTS) active allows the modem to transmit data on TXD when CTS becomes active. The responses to RTS are shown in Table 3.
Clear To Send (CTS)
Data Clock (DClK)
Clear to Send (CTS) active indicates to the local DTE that
the modem will transmit any data presen~ TXD. CTS
response times from an active condition of RTS are shown
in Table 3.
The modem provides a single Data Clock (DClK) output
which performs the function of a transmitter data clock
when the modem is transmitting and a receiver data clock
when the modem is receiving.
Received Line Signal Detector (RlSD)
DCLK as the Transmit Data Clock:
For V.29 and V.27, Received Line Signal Detector (RlSD)
goes active at the end of the training sequence. If energy
is above the turn on threshold and training is not detected,
the RlSD off-to-on response time is 804 baud times. The
RLSD on-to-offtimeforV.29 is 30 ± 9 ms. TheV.27 RlSD
on-to-off time is 11.6 ± 5 ms. The RlSD on-to-off time ensures that all valid data bits have appeared on RXD.
RTS
l---i
I
---i
I---j
The modem outputs a synchronous transmit Data Clock,
for USRT timing, when the modem is transmitting. The
DClK frequency is 9600, 7200, 4800, 2400, or 300 Hz
(±0.01%) with a duty cycle of 50 ± 1%. In Group 2, the
DClK frequency is 10368 Hz ± 5 ppm when a precision
oscillator (Y2 in Table 12) is used.
I
I I
IE
I_TON--j
CTS
DCLK
TXD
T OFF
!O
UUlJ1J
---i I
U I I I I I I I I I I I I ,,; ; I I II I II I I I ~I
FIRST DATA BIT TRANSMITTEJ
-C
LAST DATA BIT TRANSMITTED
I I
L
~I------------~i ~i--------------~r
T!ANSMITTED ENERGY
Figure 3. Transmitter Signal Timing
-c
RLSD
DCLI<
RXD
R~CEIVED ENERGY
~I--------------------~
I---------'~
~ ~~------------~ ~------------~r
UUUlf
---l
i
)1 1111111111 \I I II II ~ : 11111 II
FIRST BIT RECEIVED
LAST BIT RECEIVED
Figure 4. Receiver Signal Timing
3-110
5'
R96EFX
9600 bps MONOFAX Modem with Error Detection
Transmit Data (TXD) must be stable during the one J1S
period immediately preceding the rising edge of DCLK and
following the rising edge of DCLK.
DCLK as the Receive Data Clock:
The modem outputs a synchronous receive data clock, for
USRT timing, when the modem is receiving. The DCLK
frequency is 9600, 7200, 4800, 2400, or 300 Hz (:t: 0.Q1 %)
with a duty cycle of 50 :t:1 %. In Group 2, the DCLK frequency is 10368 Hz :t: 5 ppm when a precision oscillator (Y2 in
Table 12) is used.
ANALOG SIGNALS
The Transmitter Analog Output (TXOUT) and Receiver
Analog Input (RXIN) allow modem connection to either a
leased line or the PSTN through the appropriate buffering
and an audio transformer or a data access arrangement.
The Auxiliary Input (AUXI) provides access to the transmitter for summing audio signals with the modem's transmitter analog output. The analog signal characteristics are
described in Table 9.
Table 9. Analog Interface Characteristics
ANCILLARY SIGNALS
Name
TXOUT
Enable 85 (EN85)
The Enable 85 (EN85) input selects the modem
microprocessor bus compatibility. When EN85 is low, the
modem can interface directly to an 8085 compatible
microprocessor bus using READ and WRITE. When EN85
is high, the modem can interface directly to a 6500 compatible microprocessor bus using 412 and
In the 6500
configuration, the READ input becomes cp2 and the WRITE
input becomes R/W. This selection is performed when
power is turned on or when POR is activated.
RiN.
Length
1.8km
3.6km
1
7.2km
1
1
AUXI
AC
Input impedance:
1M Q
Anti-aliasing filter transfer function:
21551.72/(s + 11547.34)
Maximum input frequency:
TXOUT can supply a maximum of:t: 3.03 volts into a load
resistance of 10K ohms minimum. A 600 ohm line impedance can be matched using an external smoothing filter with a 604 ohm series resistor in its output. The
smoothing filter should have a transfer function of
28735.63/(S + 11547.34).
Receiver Analog Input (RXIN)
The RXIN input impedance is greater than 1M ohms. RXIN
requires an external anti-aliasing filter between the
modem and the line interface, with a transfer function of
21551.72/(s + 11547.34). The maximum input level into
the anti-aliasing filter should not be greater than 0 dBm.
The filters required for anti-aliasing on the receiver input
and the smoothing filter on the transmitter output have a
single pole within the modem's passband (11,542
radians). Internal filters compensate for its presence,
therefore, the pole location must not be changed. Some
variation from the recommended resistor and capacitor
values is permitted as long as the pole is not moved, overall gain is preserved, and the device is not required to drive
a load of less than 10K ohms (see Recommended Modem
Interface Circuit.)
The cable length equalization is selected from the
CABLE1 and CABLE2 input lines as follows:
o
1
o
AB
Transmitter Analog Output (TXOUT)
To minimize the impact of this undesired passband shaping, a compromise equalizer with more attenuation at the
lower frequencies than at the higher frequencies can be
placed in series with the analog signal. The modem includes three such equalizers deSigned to compensate for
cable distortion. When selected, the equalizers are inserted in the transmit path when transmitting, and in the
receive path when receiving. Table 2 shows the cable
equalization.
CABLE1
RXIN
Characteristic
Maximum output:
:l:3.03voHs
Minimum load:
10K Q
Smoothing filter transfer function:
28735.63/(s+ 11547.34)
Input Impedance:
1M Q
Gain to TXOUT:
+5.6 dBm:l:1 dBm
Modems may be connected by direct wiring, such as
leased telephone cable or through the PSTN, by means of
a data access arrangement. In either case, the modem
analog signal is carried by copper wire cabling for at least
some of its route. The cable characteristics shape the
passband response so that the lower frequencies of the
passband (300 Hz to 1700 Hz) are attenuated less than
the higher frequencies (1700 Hz to 3300 Hz). The longer
the cable, the more pronounced the effect.
o
o
AA
4800Hz
Cable Equalizer Select 1 and 2 (CABLE1 and
CABLE2)
CABL..E2
Type
0.0
3-111
•
R96EFX
9600 bps MONOFAX Modem with Error Detection
Auxiliary Analog Input (AUXI)
AUXI allows access to the transm itter for the purpose of interfacing with user provided equipment. Because this is a
sampled input, any signal above 4800 Hz will cause aliasing errors. The input impedance is > 1M ohm, and the gain
to TXOUT is +5.6 dBm ± 1 dBm.
'~!---""L
EYESYNC
EYECLKO.
DIAGNOSTIC SIGNALS
Four signals provide the timing necessary to create an oscilloscope quadrature eye pattern. The eye pattern is
simply a display of the received baseband constellation.
By observing this constellation, common line disturbances
can usually be identified. Timing of these signals is illustrated in Figure 5 and an example eye pattern generation schematic is shown in Figure 6.
MSB
EYEX,
EYEY
LSB
~~
*74LS74 OUTPUT PIN 9 (FIGURE 6)
EYEX and EYEY
Figure 5. Eye Pattern Timing
The EYEX and EYEY outputs provide two serial bit
streams containing data for display on the oscilloscope X
axis and Y axis, respectively. This serial digital data must
first be converted to parallel digital form by two serial-toparallel converters and then to analog form by two digitalto-analog (D/A) converters.
EYECLK
EYECLK is a clock provided to create a clock which can
be used by the serial-to-parallel converters to shift in the
EYEX and EYEY data (see Figure 5).
EYESYNC
EYEX and EYEY outputs are 15-bit words, each with 8-bits
of significance. The 15-bit data words are shifted out most
significant bit first with the seven most significant bits set
equal to zero. EYEX and EYEY are clocked by the rising
edge of EYECLK.
EYESYNC is a strobe for loading the D/A converters,
3-112
9600 bps MONOFAX Modem with Error Detection
R96EFX
EVEX
+5 O.l.F
~
14
A
4.7Kfl
74lS164
B
7
ClK
3
74LS74
+5V
ClR
4
5
6
10
3
4
5
6
=
11 12
EVESVNC
PIN 17
7
~---------+--a[E
EVEV
14
13
PIN 44
X·OUT
(SCOPE)
8
10 lSB
V out 20
REF OUT
SUM F---.---,
NE5018
OFFSET 1-'1..:.5__--.
REF IN
12 AOJ
R96EFX
+ 12V--------..
IO.
1• F
74LS164
6
2
3
4
10
6
11 12
7
10 lSB
~----------~[E
14 REF OUT
13 REF IN
NE5018
Nc 12 ADJ
~~~--~~~~~
+ 12V-------.
~O.l.F
Figure 6. Eye Pattern Circuit
3·113
V·OUT
(SCOPE)
II
9600 bps MONOFAX Modem with Error Detection
R96EFX
INTERFACE MEMORY MAPS
SOFTWARE INTERFACE
A memory map of the 32 addressable registers in the
modem is shown in Figure 7. These 8-bit registers may be
read or written during any host read or write cyCle. In order
to operate on a Single bit or a group of bits in a register, the
host processor must read a register and then mask out unwanted data. When writing a single bit or group of bits in a
register, the host processor must perform a read-modifywrite operation. That is, the entire register (8-bits) must
first be read, the necessary bits must be set or reset
without altering the other register bits, then the by1e (8-bits)
containing both the unaltered and modified bits must be
written back into the interface memory.
Modem functions are implemented in firmware executing
in a single DSP.
INTERFACE MEMORY
The DSP communicates with the host processor by means
of a dual-port, interface memory. The interface memory in
the DSP contains thirty-two 8-bit registers, labeled register
00 through 1F. Each register can be read from, or written
into, by both the host and the DSP. The host can control
modem operation by writing control bits to DSP interface
memory and writing parameter values to DSP RAM
through interface memory. The host can monitor modem
operation by reading status bits from DSP interface
memory and reading parameter values from DSP RAM
through interface memory.
INTERFACE MEMORY BIT DEFINITIONS
Table 10 defines the individual bits in the interface
memory. In the Table 10 descriptions, bits in the interface
memory are referred to using the format Z:O. The register
number is designated by Z (00 through 1F), and the bit
number by 0 (0 through 7, 0 = LS8).
Figure 5. R96EFX Interface Memory
Bit
Register
IF
IE
10
lC
lB
lA
19
18
17
16
15
14
13
12
11
10
7
09
08
07
06
05
04
03
02
01
00
5
PIA
1A2
IAI
ACC2
IE2
4
3
PIE
PIREQ
6A2
0000
2
1
0
IE'
SETUP
BA,
BR2WRT2
CR2
x
R
Da
RAM A
DATAM A
XDAM2
X RAM DATA
XDAL2
YDAM2
Y RAM DATA
Y RAM DATA 2 LSB YDAL2ltDATA BUFFER(D~
FED
CTSP CDET
OF
OE
00
OC
OB
OA
6
RX
PN
G2FGC
ITBMSK
TRIG
IANDOR
ITADRS
IIRUN EQSV EQFZ ZEROC ABIDL EOF
CRC
FR3
FR2
FRI
12TH
RTSP TDIS
PDM SHTR EPT SQEXT T2
CONF
WATI
ACCI
0
RAM ADD
1 ADD1
X RAM DATA
XDAMI
X RAM DATA
XDAL1
Y RAM DATA
YDAMI
Y RAM DATA 1 LSB DALI
(-) Indicates reserved for modem use only.
" "I ,.
FLAG
HDLC
CRI
Figure 7. R96EFX DSP Interface Memory Map
3-114
9600 bps MONOFAX Modem with Error Detection
R96EFX
Table 10. R96EFX Interface Memory Bit Definitions
MnemonIc
12TH
Memory
locatIon
8:4
Default
Value
0
Name/Descrlptlon
Select 12th Order. The one state of 12TH operates the tone detectors as one 12th order filter (uses FR3). The zero state of 12TH operates the tone detectors as three parallel independent 4th order fmers (FR1, FR2, FR2LJ2TH is operable in FSK, Group 2, and tone
modes. (i.e., CONF 20, 40, 80; wHh RTS off.)
=
ABIDL
9:3
-
Abort/ldle. When the modem is configured as a transmitter and control/status bit ABIDL is a
1, the modem will finish sending the current DBUFF byte. The modem will then send continuous ones if ZEROC is a 0, or continuous zeros if ZEROC is a 1. When ABIDL is a 0, the
modem will not send continuous ones or zeros. If ABIDL is reset one DCLK cycle after
being set, the modem will transm~ eight continuous ones if ZEROC is a 0, or eight continuous zeros if ZEROC is a 1. ABIDL is also set by the modem when the under run condition occurs (b~ OVRUN is set) and the modem will send at least eight continuous ones (if
ZEROC is 0) or eight continuous zeros (if ZEROC Is 1). To stop continuous one or zero
transmission, ABIDL must be reset by the host. (HDLC mode only)
When the modem is configured as a receiver and status bit ABIDL is a 1, the modem has
received a minimum of seven consecutive ones. To recognize further occurrences of this
abort condition, ABIDL must be reset by the host. (HDLC mode only)
ACCl
5:7
1
RAM Access 1. When control bH ACCl is a 1, the modem accesses the RAM associated
wHh the address in ADDl and the CRl bit. WRTl determines if a read or write is performed.
ACC2
15:7
1
RAM Access 2. When controi bH ACC2 is a 1, the modem accesses the RAM associated
w~h the address in ADD2 and the CR2 bit. WRT2 determines if a read or write is performed.
ADDl
4:0-7
17
RAM Address 1. ADDl contains the RAM address used to access the modem's X and Y
Data RAM (CRl 0) or X and Y Coefficient RAM (CRl 1) via the X RAM Data 1 LSB and
MSB words (2:0-7 and 3:0-7, respectively) and the Y RAM Data 1 LSB and MSB words (0:07 and 1:0-7, respectively).
ADD2
14:0-7
11
RAM Address 2. ADD2 contains the RAM address used to access the modem's X and Y
Data RAM (CR2 0) or X and Y Coefficient RAM (CR2 1) via the X RAM Data 2 LSB and
MSB words (12:0-7 and 13:0-7, respectively) and the Y RAM Data 2 LSB and MSB words
(10:0-7 and 11 :0-7, respectively).
ANDOR
A:5
-
AND/OR Bit Mask Function. When control bit ANDOR is a 1and the programmable interrupt is enabled, the modem will assert IRQ if all the b~s in the register specified by ITADRS
and masked by ITBMSK are ones. When ANDOR Is a 0 and the programmable interrupt is
enabled, the modem will assert IRQ if anyone of the bits in the register specified by
ITADRS and masked by ITBMSK is a one.
BAl
lE:O
-
Buffer Available 1. When set to a 1, status bit BA 1 signifies that the modem has either written diagnostic data to, or read diagnostic data from, the Y RAM DATA 1 LSB (YDAL1)
register (0:0-7). This cond~ion can also cause IRQ to be asserted (see lEI and IA1). The
host writing to or reading from register 00 resets the BAl and IAl bits to O. (See lEI and
IA1.)
BA2
lE:3
-
Buffer Available 2. When set to a 1, status b~ BA2 signifies that, when the modem is in the
parallel data mode or the HDLC mode, it has read register 10:0-7 (DBUFF) when transmitting (buffer becomes empty), or it has written register 10:0-7 (DBUFF) when receiving (buffer becomes full). When the modem is not in parallel data mode, the setting of BA2 to a 1 by
the modem signifies that the modem has e~her written diagnostic data to, or read diagnostic
data frQ!!h.the Y RAM DATA 2 LSB (YDAL2) register (10:0-7). These conditions can also
cause IRQ to be asserted (see IE2 and 1A2). The host wr~ing to or reading from register 10
resets the BA2 and 1A2 bits to O. (See IE2 and IA2.)
BRl
5:2
0
Baud Rate 1. When control bit BRl Is aI, RAM access associated with ADDI occurs at the
modem baud rate; when BRl is a 0, RAM access occurs at the modem sample rate. This bit
must be reset to a zero in G2, FSK, or Tone mode (CONF 40, 20, or 80, respectively).
=
=
=
=
=
BR2
15:2
0
Baud Rate 2. When control b~ BR2 is a 1, RAM access associated with ADD2 occurs at the
modem baud rate; when BR2 is a 0, RAM access occurs at the modem sample rate. This bit
must be reset to a zero in G2, FSK, or Tone mode (CONF 40, 20, or 80, respectively).
=
3-115
•
R96EFX
9600 bps MONOFAX Modem with Error Detection
Table 10. R96EFX Interface Memory Bit Definitions (Cont'd)
,Mnemonic
Memory
location
Default
Value
Name/Descrlptlon
CDET
F:O
-
Carrier Detected. When status bit CDET Is aI, the receiver has finished receiving the trainIng sequence, or has tumed on due to detecting energy above threshold, and is receiving
data. When CDET is a 0, the receiver Is in the Idle state or in the process of training.
CONF
6:0-7
14
Configuration. The CONF control bits select one of the following transmitter/receiver configurations:
CONF
Configuration
14
12
11
OA
09
20
40
80
V.2.9 9600 bps
V.2.9 7200 bps
V.2.9 4800 bps
V.27 4800 bps
V.27 2400 bps
V.21 Channel 2300 bps (FSK)
Group 2 (G2)
Tone TransmlliTS or RTSP on),
Tone Detect (RTS and RTSP off)
Configuration Definitions:
1. V.2.9. When a V.2.9 configuration Is selected, the modem operates as specified In
CCITT Recommendation V.29.
2. V:zr. When a V.27 configuration Is selected, the modem operates as specified In
CCiTT Recommendation V.27.
3. V.21 Channel 2. When the V.21 Channei 2 configuration is selected, the modem
operates as specified in CCITT Recommendation V.21 channei 2.
4. Group 2. When the Group 2 configuration is selected, the modem operates as
specified in CCITT Recommendation T.3.
5. Tone Transmit. When the Tone Transmit configuration is selected, the modem transmits single or dual frequency tones in response to RTS or RTSP. Tone frequencies
and amplitudes are programmable in the RAM.
6. Tone Detect. ,When the Tone Detect configuration is selected and 12th Is set to a 1,
the three 4th order tone detect filters are combined into a singie 12th order tone
detect filter (FR3). If 12th is not set to a 1, the three tone detect filters are placed in
parallel and are independent (FR1, FR2, and FR3). All tone detect filters are
program mabie.
CRC
9:1
-
Cyclic Redundancy Check error. When status bit CRC is a 1 and status bit EOF is aI,
the received frame is in error. When CRC is a 0 and EOF is a 1, the received frame is correct. CRC only changes immediately before EOF is set to a 1. (HDLC mode only)
CRI
5:0
0
Coefficient RAM 1 Select. When control bit CR1 is a 1,ADD1 addresses Coefficient RAM.
When CR1 is a 0, ADDI addresses Data RAM. This bit must be set according to the desired
RAM address (Table 11).
CR2
15:0
0
Coefficient RAM 2 Select. When control bit CR2 is a 1, ADD2 addresses Coefficient RAM.
When CR2 is a 0, ADD2 addresses Data RAM. This bit must be set according to the desired
RAM address (Table 11).
CTSP
F:l
-
Clear To Send Parallel. When set to aI, status bit CTSP indicates to the DTE that the training sequence has been compieted and any data present at TXD will be transmitted. CTSP
parallels the operation of the CTS pin.
DBUFF
10:0-7
-
Data Buffer. In the parallei data mode, the host obtains received data from the modem by
reading a data byte from DBUFF; the host sends data to the modem to be transmitted by
writing a data byte to DBUFF. The data is received and transmitted bit 0 first
3-116
R96EFX
9600 bps MONOFAX Modem with Error Detection
Table 10. R96EFX Interface Memory Bit Definitions (Cont'd)
Mnemonic
EOF
Memory
Location
9:2
Default
Value
-
Name/Descrlptlon
or
End
Frame. When the modem is configured as a transmitter, the EOF bit Is a control bit.
To convey to the modem that it is time to send the FCS and ending flag of a HOLC frame,
the host must set the EOF bit after the modem has taken the last byte of data (resides in
OBUFF) of the frame (BA2 sets again). EOF will be reset by the modem after it has recognized the setting of EOF by the host. (HOLC mode only)
When the modem Is configured as a receiver and status bit EOF Is a 1, the modem has
received a frame ending flag and bit CRC Is updated. EOF must be reset by the host before
receiving the ending flag of a follOWing frame. (HOLC mode only)
EPT
7:3
0
Echo Protector Tone Enable. When control bit EPT is a 1, an unmodulated carrier Is transmitted for 187.5 ms followed by 20 ms of no transmitted energy prior to the transmission of
the training sequence. When EPT is a 0, neither the echo protector tone nor the 20 ms of no
energy are transmitted prior to the transmission of the training sequence except in V.29
which transmits 20 ms of silence at the beginning of training.
EQFZ
9:5
0
Equalizer Freeze. When control bit EQFZ is a 1, updating of the receiver's adaptive
equalizer taps is Inhibited.
EQSV
9:6
0
Equalizer Save. When control bit EQSV is a 1, the adaptive equalizer taps are not zeroed
when reconfiguring the modem or when entering the training state. Adaptive equalizer taps
are also not updated during training. This bit is used in conjunction with the SHTR bit and
must be followed by the setting of the SETUP bit.
FED
F:7,6
-
Fast Energy Detector. Status bits FED indicates the level of the received signal according
to the following codes.
FED
Energy Level
No energy
Invalid
Above Turn-off Threshold
Above Turn-on Threshold
0
1
2
3
FLAG
9:0
0
FLAG Mode. When the modem is configured as a transmitter and status bit FLAG Is a 1,
the modem is transmitting a flag sequence. (HOLC mode only)
When the modem is configured as a receiver and status bit FLAG Is a 1, the modem has
received a flag sequence. (HOLC mode only)
FR1
8:5
0
Frequency No.1. The one state of FR1 Indicates that energy Is above tone detector 1's
detected turn-on threshold (default detection range = 2100 Hz :t 25 Hz in non-Group 2
mode). FR1..!!.Pperable in FSK, Group 2, and tone modes. (i.e., CONF = 20, 40, 80; with
RTSP and RTS off.)
FR2
8:6
0
Frequency No.2. The one state of FR2 Indicates that energy is above tone detector 2's
detected turn-on threshold (default detection range = 1100 Hz :!: 30 Hz In non-Group 2
mode). FR2....!!.9perable in FSK, Group 2, and tone modes. (i.e., CONF = 20, 40, 80; with
RTSP and RTS off.)
FR3
8:7
0
Frequency No.3. The one state of FR3 indicates that energy is above tone detector 3's
detected turn-on threshold (default detection range = 462 Hz :t14 Hz In non-Group 2 mode).
FR3 is operable in FSK, high spee~oup 2, and tone modes. (I.e., CONF = 14, 12, 11,
OA, 09, 20, 40, 80; with RTSP and RTS off.)
G2FGC
0:3
0
Group 2 Fast Gain Control. The one state of G2FGC selects a fast AGC rate (8.6 times
standard) In Group 2 Facsimile.
HOLC
7:0
0
HDLC mode. When control bit HOLC Is a 1, the modem performs HOLC framing. To become active, the host must set HOLC and POM followed by the setting of SETUP. When
control bit HOLC is a 0, the modem does not perform HOLC framing provided SETUP was
set following the resetting of HOLC.
3-117
•
9600 bps MONOFAX Modem with Error Detection
R96EFX
Table 10. R96EFX Interface Memory Bit Definitions (Cont'd)
Mnemonic
Memory
location
DefauH
Value
Name/Descrlptlon
IAI
lE:6
-
Interrupt Active 1. When Inlerr4i!Enable 1 is enabled (lEI Is a 1) and BAils set to a 1 by
the modem, the modem asserts IRQ end sets status bit IAI to a 1 to Indicate that BAI going
to a 1 caused the Interrupt. The host wrHlng to or reading from register 0:0 resets IA1 to a O.
(See lEI and BAl.)
1A2
lE:7
-
Interrupt Active 2. When Interrurunable 2 is enabled (/E2 is a 1) and BA2 Is set to a 1 by
the modem, the modem asserts IRQ and sets status billA2 to a 1 to indicate that BA2 going
to a I caused the Interrupt. The host writing to or reading from register 10:0 resets 1A2 to a
O. (See IE2 and BA2.)
lEI
lE:2
' 0
Interrupt Enable 1. When control bit lEI is a 1 (interrupt enabled), the modem will assert
IRQ and set IAI to a t when BAI Is set to 1 by the OSP. When lEI is a 0 (Interrupt disabled), BAI has no effect on IRQ and lAt. (See BAt and IA1.)
IE2
lE:5
0
Interrupt Enable 2. When control bH IE2 is a 1 (interrupt enabled), the modem will assert
IRQ and set 1A2 to a 1 when BA2 is set to 1 by the OSP. When IE2 is a 0 (interrupt disabled) , BA2 has no effect on IRQ and 1A2. (See BA2 and 1A2.)
ITAORS
A:0-4
-
Interrupt Address. These 5 bHs specify the register upon which the programmable interrupt
. and ITBMSKwill take affect. The address of the byte on which the modem asserts IRQ on a
bH or bits in that byte is specified below:
Host
Host
Register
(Hex)
00
01
02
03
04
05
06
07
ITADRS
Register
(Hex)
(Hex)
00
10
01
11
02
12
10
11
12
13
14
15
16
03
13
04
14
05
15
08
09
OA
os
oc
06
00
OE
OF
16
07
17
17
18
19
lA
lB
Ie
10
IE
IF
ITADRS
(Hex)
08
18
09
19
OA
lA
OB
lB
oe
Ie
00
10
'OE
IE
OF
IF
ITBMSK
B:0-7
-
Interrupt 'BH Mask. This byte performs a bit mask on the register specified In ITADRS for
the programmable interrupt processing. A one in any position In ITBMSK will cause the
modem to assert IRQ on the corresponding bit or bits In the register specified by ITAORS according to the ANOOR bit and the TRIG bits if PIE is set by the host and PIREQ Is reset by
the host.
OVRUN
9:7
-
Overrun/Underrun. When the modem Is configured as a transmitter, and status bit OVRUN
is ai, a transmit underrun condition has occurred. If the host does not load In a new byte of
data In OBUFF within eight bit times of loading the previous byte into OBUFF. OVRUN and
ABIOL will set. The modem will then automatically send eight continuous ones. The transmission of these ones will continue until the host resets ABIOL. The modem will then finish
sending the current group of eight ones and will either start sending another frame (if BA2 is
reset) or will transmit continuous flags. The modem will reset OVRUN every time it sets
BA2. (HOLe mode only)
When the modem Is configured as a receiver and status bit OVRUN is ai, an overrun condition has occurred. To detect the next overrun condition, the host must reset this bit. (HOLe
mode only)
3-118
R96EFX
9600 bps MONOFAX Modem with Error Detection
Table 10. R96EFX Interface Memory Bit Definitions (Cont'd)
Mnemonic
Memory
Location
Default
Value
Name/Descrlptlon
POM
7:5
0
Parallel Data Mode. When control b~ POM is a 1 and the modem is a transmitter, it accepts
data for transmission from OBUFF (10:0-7) rather than the TXO input. When POM is a 1 and
the modem is a receiver, the modem provides the received data to the host using OBUFF
(10:0·7).
PIA
1F:7
-
Programmable Interrupt Active. When control bit PIE is enabled (PIE is a 1) and the interrupt cond~ion is true as specified by ITBMSK, ITADRS, TRIG, and ANDOR, the modem asserts IRQ if PIREQ has been previously reset by the host (usually after servicing the
previous interrupt). Status b~ PIA is set by the modem when the above occurs. PIA is reset
when the host resets PIREQ.
PIE
1F:4
0
Programmable Interrupt Enable. When control bit PIE is enabled (PIE is a 1) and the interrupt condHion is true as specified by ITBMSK, ITADRS, TRIG, and ANDOR, the modem asserts IRQ if PIREQ has been previously reset by the host (usually after servicing the
previous interrupt). Status bit PIA is set by the modem when the above occurs. When PI E is
~(interrupt disabled), ITBMSK,ITADRS, TRIG, ANDOR, and PIREQ have no effect on
IRQ and PIA.
PIREQ
1F:3
-
Programmable Interrupt Request. When control bit PIE is enabled (PIE is a 1) and the interrupt condition is true as specified by ITBMSK, ITADRS, TRIG, and ANDOR, the modem
asserts IRQ if control bit PIREQ has been previously reset by the host. PIREQ is set by the
modem when the programmable interrupt condition is true. The host must reset PIREQ after
servicing the interrupt since the modem does not reset PIREQ. If PIREQ is not reset when
the interrupt condition occurs again, the modem will not assert IRQ.
PN
0:6
-
PN Sequence Detected. When status bit PN is a I, the receiver is detecting the PN portion
of the training sequence. When PN is a 0, PN is not being detected.
RTSP
7:7
0
Request To Send Parallel. The one state of RTSP begins a transmit sequence. The
modem will continue to transmit until RTSP is turned off, and the turn-off sequence has
been completed. RTSP parallels the operation of the hardware RTSP control input. These
inputs are "ORed" by the modem.
AX
0:7
-
Receive State. When status bit AX is aI, the modem is in the receive state and is not transmitting.
SETUP
1F:0
0
Setup. Control bit SETUP bit must be set to a 1 by the host after the host writes a configuration code into the CONF bits (register 6:0-7) or changes a bit in 7:0-6 (register 7 bits 0
through 6). This informs the modem to implement the configuration change. The modem
resets the SETUP bit to a 0 when the configuration change is implemented.
SHTR
7:4
0
Short Train. When SHTR is a 1 and CONF is either OA or 09, the modem will perform a
V.27 ter short training sequence. A successful V.27 ter long train at the same data rate must
precede the short train. The setting of the SHTR b~, along with the setting of the EQSV bit,
must be followed by the setting of the SETUP bit.
SQEXT
7:2
0
Squelch Extend. When control bit SQEXT is a 1, the modem's receiver is inhibited from the
reception of any signal for 140 ms after the transmitter turn-off.
T2
7:1
0
T/2 Equalizer Select. When control bit T2 is a 1, the linear section of the receiver's adaptive
equalizer is T/2 fractionally spaced. When T2 is a 0, the equalizer is T spaced (T = 1 baud
time).
TOIS
7:6
0
Training Disable. When control b~ TOIS is a 1, the modem as a receiver is prevented from
recognizing a training sequence and enterin~ training state; as a transmitter the modem
will not transmit the training sequence when RTS or RTSP is activated.
3-119
•
9600 bps MONOFAX Modem with Error Detection
R96EFX
Table 10. R96EFX Interface Memory Bit Definitions
Mnemonic
TRIG
Memory
Location
Default
Value
-
A:6-7
Name/Descrlptlon
Interrupt Triggering. These two bijs select how the programmable interrupt is to occur If
this interrupt is enabled. The user has the option to be continuously interrupted whenever
the interrupt condition is true (DC triggered), to be interrupted only when the interrupt condition transitions from false to true (posijive edge triggered), to be interrupted only when the Interrupt condition transitions from true to false (negative edge triggered), or to be interrupted
when the interrupt condition transHions from false to true or from true to false (edge triggered):
TRIG
Descriplion
00
01
10
11
DC
Positive Edge
Negative Edge
Edge
WRTt
5:1
0
RAM Write 1. When control bit WRTt is a 1 and ACCI is set to ai, the modem writes the
data from the Y RAM Data 1 registers into .Its internal RAM at the location addressed by
ADDI and CRI. (When the most significant bit of ADD! is a 0, the write is performed to the
X RAM location; when ai, the write is to the Y RAM location.) When WRTI is a 0 and
ACCI is set to a I, the modem reads data from its internal RAM from the locations addressed by ADDI and CRI and stores it into the X RAM Data 1 registers and Y RAM Data 1
registers, respectively.
WRT2
15:1
0
RAM Write 2. When control bit WRT2 is a 1 and ACC2 is set to aI, the modem writes the
data from the Y RAM Data 2 registers into its internal RAM at the location addressed by
ADD2 and CR2. (When the most significant bit of ADD2 is a 0, the write is performed to the
X RAM location; when aI, the write is to the Y RAM location.) When WRT2 is a 0 and
ACC2 is set to aI, the modem reads data from its internal RAM from the locations addressed by ADD2 and CR2 and stores it into the X RAM Data 2 registers and Y RAM Data 2
registers, respectively.
XDALI
2:0-7
-
X RAM Data 1 LSB. XDAL1 is the least significant byte of the 16-bit X RAM 1 data word
used in reading X RAM locations.
XDAL2
12:0-7
-
X RAM Data 2 LSB. XDAl2 is the least significant byte of the 16-bit X RAM 2 data word
used in reading X RAM locations.
XDAMI
3:0-7
-
X RAM Data 1 MSB. XDAMI is the most significant byte of the 16-bit X RAM 1 data word
used in reading X RAM locations.
XDAM2
13:0-7
-
X RAM Data 2 MSB. XDAM2 is the most significant byte of the 16-bit X RAM 2 data word
used in reading X RAM locations.
YDAl1
0:0-7
-
Y RAM Data 1 LSB. YDAL 1 is the least significant byte of the 16-bit Y RAM 1 data word
used in reading or writing Y RAM locations in the modem.
YDAL2
10:0-7
-
Y RAM Data 2 LSB. YDAL2 is the least significant byte of the 16-bit Y RAM 2 data word
used in reading or writing Y RAM locations in the modem.
YDAMI
1 :0-7
-
Y RAM Data 1 MSB. YDAM 1 is the most significant byte of the 16-bit Y RAM 1 data word
used in reading or writing Y RAM locations in the modem.
YDAM2
11 :0-7
-
Y RAM Data 2 MSB. YDAM2 is the most significant byte of the 16-bit Y RAM 2 data word
used in reading or writing Y RAM locations in the modem.
ZEROC
9:4
0
Zero Clamp. When control bit ZEROC is a 1 and ABIDL is ai, the modem will transmit continuous zeros. When ZEROC is a 0 and ABIDL is ai, the modem will transmit continuous
ones. If ABIDL is 0, ZEROC is disabled. (HDLC mode only)
I
3-120
9600 bps MONOFAX Modem with Error Detection
R96EFX
The 16-bit words are transferred between DSP RAM and
DSP interface memory once each baud or sample time, as
selected by the BR1 and BR2 bits. The baud rate is determined by the selected configuration, but the sample rate is
fixed at 9600 Hz, except in Group 2 where the sample rate
is 10368 Hz.
DSP RAM ACCESS
Table 11 provides the RAM access functions, codes, and
registers.
DSP RAM Organization
The DSP contains 16-bit words of random access memory
(RAM). Because the DSP is optimized for performing complex arithmetic, the RAM is organized into real (X RAM)
and imaginary (Y RAM) parts. The host processor can
read or write both the X RAM and the Y RAM.
Two RAM Access bits in the DSP interface memory tell the
DSP to access the X RAM and/or Y RAM. The transfer is
initiated by the host setting the ACC1 and/or the ACC2
bit(s). The DSP tests these bits each baud or sample
period, except in G2, FSK or Tone mode where these bits
are always tested at the sample period.
Interface Memory Access to DSP RAM
The interface memory acts as an intermediary during host
to DSP RAM, or DSP RAM to host, data exchanges. The
address stored in DSP interface memory RAM Address
registers by the host determines the DSP RAM address for
data access.
If parallel data mode is selected, RAM access associated
with RAM Address 2 is disabled and only RAM access associated with RAM Address 1 is available.
•
Table 11. R96EFX RAM Access Codes
Function
Received Signal Samples
Received Signal Samples FSK
Demodulator Output
Lowpass Filter Output
Average Energy
AGC Gain Word
Tone 1 Frequency
Tone 1 Level
Tone 2 Frequency
Tone 2 Level
Output Level
Equalizer Input (Real)
Equalizer Input (Imag)
Equalizer Tap Coefficients
Unrotated Equalizer Output
Rotated Equalizer Output (Eye Pattern)
Decision Points (Ideal)
Error Vector
Rotation Angle
Frequency Correction
Eye Quality Monitor (EQM)
Turn-on Threshold (RLSD)
Turn-off Threshold (RLSD)
Group 2 PLL Frequency Correction
Group 2 Zero Crossing Threshold (Negative)
Group 2 Zero Crossing Threshold (Positive)
Group 2 AGC Slew Rate
Group 2 Black-White Threshold
Group 2 Phase Limit Value
Receiver SensHivHy
3-121
BRx
CRx
ADDx
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
1
1
0
1
0
1
1
1
1
1
1
0
0
0
1
0
0
1
15
31
13
02
14
15
21
22
22
23
21
IE
1E
38 - 5F
1C
17
17
10
OC
18
00
37
B7
00
19
99
05
24
lA
24
Read Reg. No.
2,3
2,3
0,1,2,3
0,1,2,3
2,3
2,3
2,3
2,3
2,3
2,3
2,3
0,1
0,1
0,1,2,3
0,1,2,3
0,1,2,3
0,1,2,3
0,1,2,3
0,1
2,3
2,3
2,3
0,1
2.3
2,3
0,1
2,3
2,3
2,3
2,3
R96EFX
'9600 bps MONOFAX Modem with Error Detection
DSP RAM Read Procedure
PROGRAMMABLE INTERRUPT FEATURE
The RAM read procedure is a 32-bit transfer from DSP
RAM to the interface memory which transfers both the X
RAM and Y RAM simultaneously. Before reading from
DSP interface memory, set ACC1 and/or ACC2 to a 0,
then reset BA1 or BA2 by reading YDAl1 or YDAL2. Set
WRT1 and/or WRT2 to a 0 to inform the DSP that a RAM
read will occur when ACC1 and/or ACC2 is set to a 1. load
the RAM address into RAM Address 1 and/or RAM Address 2, then set CR1 and/or CR2 appropriately. Set
ACC1 and/or ACC2 to a 1 to signal the DSP to perform the
RAM read. When the DSP has transferred the contents of
RAM into the interface memory RAM Data registers, BA1
and/or BA2 will be set.
An interface memory interrupt feature is included in the
R96EFX. This feature enables the user to select an interrupt to occur on any combination of bits within interface
memory register.
The programmable interrupt routine runs at the sample
rate in all transmitter and receiver modes. If the host sets
the Programmable Interrupt Enable bit 1F:3 (PIE), the
modem sets the Programmable Interrupt ActIve bit 1F:7
(PIA) and IRQ goes low when the interrupt condition Is
true. The Programmable Interrupt Request bit 1F:3
(PIREQ) is set by the modem whenever the Interrupt condition is true. The host must reset PlREQ after servicing
the interrupt since the modem is unable to reset this bit.
If IE1 and/or the 1E2 is a 1, IRQ is also asserted when BA1
and/or BA2 set to a 1 by the DSP. When IRQ is asserted,
IA1 and/or 1A2 goes to a 1 to inform the host that setting of
BA1 and/or BA2 was the cause. IA1 and/or 1A2 is cleared
~e host reading YDAl1 and/or YDAL2, which causes
IRQ to return high if no other interrupt requests are pending.
An interrupt may occur only within a single Interface
memory register based upon any combination of bits. For
example, the host may select register 9 and generate an
interrupt whenever bits 9:3, 9:4, and 9:7 are set, but may
not select bits 8:7 and 9:2 to generate an interrupt. The
register is selected by specifying the interrupt address A:O4 (ITADRS) (see ITADRS).
DSP RAM Write Procedure
The interrupt bit mask register B:0-7 OTBMSK) selects the
bits to be tested in the interface memory register specified
by ITADRS. For example, if ITBMSK is equal to FF all the
bits are selected; if ITBMSK is equal to OF, the four least
significant bits are selected.
The RAM write procedure is a 16-bit transfer from interface
memory to DSP RAM allowing the transfer of X RAM data
or Y RAM data to occur each baud or sample time. Before
writing to DSP interface memory, set ACC1 and/or ACC2
to a 0; then reset BA1 or BA2 by reading YDAL1 or
YDAL2, respectively. Set WRT1 and/or WRT2 to a 1 to inform the DSP that a RAM write will occur when ACC1
and/or ACC2 is set to a 1. load the RAM address into RAM
Address 1 and/or RAM Address 2, then set CR1 and/or
CR2 appropriately. Write the desired data into the interface memory RAM Data registers YOAl1 and YDAM1
and/or YDAL2 and YOAM2, then set ACC1 and/or ACC2
to a 1 to signal the DSP to perform the RAM write. When
the DSP has transferred the contents of the interface
memory RAM Data registers into RAM, BA1 and/or BA2
will beset.
There are two operating modes with each mode having
four options. The user may choose to OR the selected bits,
or to AND the selected bits. Whenever any of the selected
bits are set, the OR mode is true. The AND mode is true
whenever all the selected bits are set, and false otherwise.
When bit A:5 (ANDOR) is set to a 1, the AND mode is
chosen; when ANDOR is reset to a 0, the OR mode Is
chosen. The user has the option to be continuously Interrupted whenever the mode is true (DC triggered), to be interrupted only when the mode transitions from true to false
(negative edge triggered), to be interrupted only when the
mode transitions from false to true (positive edge trlggered), orto be interrupted when the mode transitions from
false to true and when the mode transitions from true to
false (edge triggered). The host selects one of the above
options by specifying bits A:6-7 (TRIG) (see TRIG).
IflE1 and/orlE2 is a 1, IRQ isaJso asserted and IA1 and/or
1A2 is set to a 1 when BA1 and/or BA2 Is set to a 1 by the
DSP. IA1 and/or 1A2 is cleared by writing into YDAl1
and/or YDAL2, which causes IRQ to return high if no other
interrupt requests are pending.
3-122
9600 bps MONOFAX Modem with Error Detection
R96EFX
HOLC OPERATION
PERFORMANCE
Oata and control information on an HOLC link are transmitted via frames. These frames organize the information
into a format specified by ISO that enables the transmitting
and receiving station to synchronize with each other. This
format is shown in below.
TYPICAL BIT ERROR RATES
The bit error rate (BER) performance of the modem is
specified for a test configuration conforming to that
specified in CCITT Recommendation V.56. Bit error rates
are measured at a received line signal level of -20 dBm as
illustrated.
Typical BER performance is shown in Figure 8.
IFLAG IADDR
ICONTRO~
INFORMATION
t~F~~E-S-TAAn~--~----
I'' 'BIT Fcsl
The curves shown in Figure 8 were prepared from data obtained using a TAS 1000 com munication test system.
FLAG
-----~----F~L-E-E-N~~J
TYPICAL PHASE JITTER
HOLC TRANSMITTER
At 2400 bps, the modem exhibits a bit error rate of 10--6 or
less with a signal-to-noise ratio of 12.5 dB in the presence
of 15° peak-to-peak phase jitter at 150 Hz or with a signalto-noise ratio of 15 dB in the presence of 30° peak-to-noise
phase jitter at 120 Hz.
The R96EFX HOLC transmitter works at all Group 3
speeds. The modem will automatically transmit the beginning and ending flags as well as the 16-bit Frame Check
Sequence (FCS). The host must wait until CTS or CTSP
is set by the modem before loading in the first byte of data.
When BA2 is set by the modem. the host can load in the
next byte of data. As soon as the host is finished with all
the bytes in the frame and the modem has taken the last
byte of the frame (BA2 sets). the host must set EOF to tell
the modem it is time to end the frame. When the modem
recognizes EOF being high. the modem will reset EOF and
will transmit the FCS and closing flag. Once the host sets
EOF, the host may load in the first byte of the next frame.
If the host wants to end transmission, the host must wait
for EOF to return low before turning off RTS or RTSP.
At 4800 bps (V.27 ter), the modem exhibits a bit error rate
of 10--6 or less with a signal-to-noise ratio of 19 dB in the
presence of 15° peak-to-peak phase jitter at 60 Hz.
At 7200 bps (V.29), the modem exhibits a bit error rate of
10--6 or less with a signal-to-noise ratio of 25 dB in the
presence of 12 peak-to-peak phase jitter at 300 Hz.
At 9600 bps, the modem exhibits a bit error rate of 10--6 or
less with a signal-to-noise ratio of 23 dB in the presence of
10° peak-to-peak phase jitter at 60 Hz. The modem exhibits a bit error rate of 10-5 or less with a signal-to-noise
ratio of 23 dB in the presence of 20° peak-to-peak phase
jitter at 30 Hz.
Further detail is given in the R96EFX HOLC and Programmable Interrupt Features Application Note (Order No.
826).
HOLC RECEIVER
The R96EFX HOLC receiver also works at all Group 3
speeds. The modem will automatically strip off flags and
the 16 bit FCS sequence and only present the host with
data. At the end of a frame (EOF is set), the host must
check bit CRC to determine if the frame had an error.
Thus, error detection is accomplished.
3-123
•
R96EFX
9600 bps MONOFAX Modem with Error Detection
,-----
V2.7,2400
,
\
F~K
10- 3
V29,4800
,
\
i\
10-'
V27,4800
V29,7200
/ V29,9600
/
\
~
a:
a:
\
ia:
w
...iii
10- 5
\
10- 6
0
5
1\
\
fSK
10- 3
\
\\
w
V27,2400
V29,4800
\
,
/
V29,9600
\
10-'
w
~
a:
a:
0
a:
a:
w
~
\
10-'
\
\\
15
20
10
Signal 10 Noise Ratio In dB
V27,4800
V29,7200
\
10- 6
25
0
Typical Bit Error Rate
(Back-to-Back, T Equalizer, Level -20 dBm)
5
,
\
10
15
20
Signal to Noise Ratio in dB
\
25
Typical Bit Error Rate
(Unconditioned 3002 Line, T Equalizer Level - 20 dBm)
Figure 8. R96EFX Typical Bit Error Rate (SER) Curves
3-124
9600 bps MONOFAX Modem with Error Detection
R96EFX
APPLICATION
Table 13. TCO-706AB Oscillator Specifications
RECOMMENDED MODEM INTERFACE CIRCUIT
The R96EFX is supplied as a 64-pin QUIP (Quad In-line
Package) device to be designed into original equipment
manufacturer (OEM) circuit boards. The recommended
modem interface circuit (Figure 9) and parts list (Table 12)
illustrate the connections and components required to
connect the modem to the OEM electronics.
Characteristic
Frequency
Frequency Stability
vs. Temperature
vs. Input Vo~age
vs. Aging
Frequency Tolerance
Frequency Adjustment
by Internal Trimmer
Operating Temperature
Input Voltage
Output
Symmetry
Drive
Type
If the auxiliary analog input (pin 26) is not used, resistors
R10 and R16 can be eliminated and pin 26 must be connected to analog ground (pin 24). When the cable
equalizer controls CABLE1 and CABLE2 are connected to
long leads that are subject to picking up noise spikes, a 3K
ohm series resistor should be used on each input (pins 32
and 33) for isolation.
Resistors R7 and Rl7 can be used to trim the transmit
level and receive threshold to the accuracy required by the
OEM equipment. For a tolerance of ±1 dBm, the 1% resistor values shown are correct for more that 99.8% of the
units.
Package
Value
24.00014 MHz
:t 5 ppm (O"C - 60·C)
:t 1 ppm at 4.75 V - 5.25 V
1 ppm/year
:t2ppm
±5ppm min.
O·C- GO· C
5.0 V :t 0.5% (4.75 V - 5.25 V)
50%:t 10% (40% - 60%)
CL=15pF
CMOS: Low = 0.5 V.
High = Vcc (4.5 V)
14-pin DIP
Table 12. Typical R96EFX Modem Interface Parts List
Component
DeSignation
Cl1,C13
C7,C8,C9,C12,C14
C4,C6
Component
Value
C3
1000 pF ±5%, 50V
0.1 ",F ±2O%,50V
0.33 ",F :20%, 50V
1.0 fA.f ±2O%, 50V
10.0 ",F ±10%, 25V
18 pF ±5%, 50V
39 pF ±5%, 50V
R4
R12
Rl0, R16
R2,R6
R18
R7
R17
Rll
R14, R15
R5
3 'h 5%, 1!4W
25S0±1%,1/4W
1 KQ±S%, 1/4W
3 Kg ±5%, 1/4W
10 KQ ±1%, 1/4W
34.8 KQ±l%, 1/4W
46.4 KC2±1%, 1/4W
36.S KQ±l%, 1/4W
86.6 KQ± 1%, 1/4W
2.7 MO± 5%, 1/4W
Cl0
C5
C2
Manufacturer'S
Part Number
Suggested
Manufacturer
C124Cl02J5GSCA
592CX7Rl04M050B
Kemet
Sprague
SMC50Tl ROM5X12
ECEBEF100
United Chern-con
Panasonic
43CX3ROOOJ
Mepco Electra
S043CXl KOOJ
5043CX3KOOJ
Mepco Electra
Mepco Electra
CRB 1/4XF46K4
CRB1/4XF36KS
CML 1/10T86.6 KQ ±1%
5043CX2M700J
1N4625D
R-Ohm
R-Ohm
Dale Electronics
Mepco Eletra
CRl
-5.1V 1%, regulator
Motorola
VI
24.00014, MHz
V2
24.00014, MHz
Toyocom
TCO-706AB 1
Note: 1. See Table 13 for specifications. The TC0-706AB is the only square wave generator recommended. A sine wave oscillator
may a~ernatively be used (see Note 3 in Figure 9).
3-125
•
9600 bps MONOFAX Modem with Error Detection
R96EFX
R4 3
°
C13
1000 pF
R15 86 6K
V.24
SERIAL
INTERFACE
RTS
TXOUT~2~B____~~~~
CTS
TXD
AGNDI 22
AGND2~2~4--~----~~
~-.--,-_
+ 12V
>,,-+-+_TXA
DCLK
RLSD
RXD
R14 86 6K
R17
R6
RXIN f3:.:,7____3,.,O...K_.....
464K
_<.
-12V
R98EFX
57
56
55
54
53
52
51
50
2
1
64
__ 63
DO
Dl
D2
D3
D4
D5
D6
D7
RSO
RSI
RS2
RS3
RS4
MICROPROCESSOR
BUS
INTERFACE
cs
READ
WRITE
DO
Dl
D2
D3
D4
D5
D6
D7
RSO
RSI
RS2
RS3
62
RS4
60
61
READ (¢2)
59
5B WRITE·(R/w)
IRQ
EYE
DIAGNOSTIC
INTERFACE
{""
EYESYNC
43
PDRI
CABLE1~3~2___________~C~A~B~L~El
CABLE2F3~3________________~C~A~B~L~E2
AUXIF2~6___
Rl~O~I_0K____~r-__~A~U~X~IN
---
'!-
EYECLK
ECLKINI
ECLKIN2
EYESYNC
SYNCINI
SYNCIN2
AEE
+5V
XTLI
....
7
NC
21
40
39
20
47
34
12MHz 8 S
6 MHz 9 S
DGND2 49
~~
O.l.F
29
R16
10K
- 5VA 1:;2:-:5____~=--t""""""-rDAOUT
DAIN
ADOUT
ADIN
RCVO
RCVI
See Note 2.
IV
POR
POROF5~r-----------------~~
XTLO
C3
39 pF
RIB
10K
,": 5V
19
44 EYEY
18
30
38
17
41
12
AOUT 36
AGCIN 23
cs
~~~X
EYEY
EYECLK
INC'
FOUT 27
FIN 35
CRI
-
12V
~Cl100
I,F
NOTES:
1. NC INDICATES DO NOT CONNECT.
2. CONFIGURATION WHEN GROUP 2
NOT REQUIRED.
Yl: 24.00016 MHz
PARALLEL RESONANT
CL = 18 PF
R. = 2511 MAX.
3. THE OSCILLATOR SPECIFIED IN TABLE 13
IS A SQUARE WAVE GENERATOR. A SINE
WAVE OSCILLATOR OF EQUAL ACCURACY
MAY BE USED, BUT THE INPUT TO PIN 6
MUST BE CAPACITIVELY COUPLED (e.g., 0.1",,)
AND THE OSCILLATOR OUTPUT MUST BE 3.5
VOLTS PEAK·TO·PEAK :I: 14% OVER THE
MODEM'S OPERATING ENVIRONMENTAL RANGE.
XTLO
See Note 3.
Figure 10. Recommended R96EFX Modem Interface Circuit
3-126
R96EFX
9600 bps MONOFAX Modem with Error Detection
PC BOARD LAYOUT CONSIDERATIONS
1. The R96EFX and all supporting analog circuitry, including the data access arrangement if required,
should be located on the same area of printed circuit
board.
Table 14. Pin Noise Characteristics
Noise Source
High
Low
1
2
12
17
18
19
20
21
30
38
39
40
41
2. All power traces should be at least a 0.1 inch width.
3. If the power source is located more than approximately 5 inches from the modem, a decoupling capacitor
of 10 j.4F or greater should be placed in parallel with
C4 near pins 10 and 49.
4. All circuitry connected to pins 6 and 7 should be kept
short to prevent stray capacitance from affecting the
oscillator.
5. Pin 22 should be tied directly to pin 24 at the modem
package. Pin 24 should tie directly, by a dedicated
path, to the common ground point for analog and digital ground.
44
6. An analog ground plane should be supplied beneath
all analog components. The analog ground plane
should connect to pin 24 and to all analog ground
pOints shown in Figure 10.
50
51
52
53
54
7. A digital ground plane should be supplied to coverthe
remaining allocated area. The digital ground plane
should connect to pin 49 and to all digital ground
pOints shown in Figure 10, plus the crystal-can
ground.
55
56
57
58
59
60
61
62
8. The modem package should be oriented relative to
the two ground planes so that the end containing pin
1 is toward the digital ground plane and the end containing pin 32 is toward the analog ground plane.
63
9. As a general rule, digital Signals should be routed on
the component side of the PCB while the analog signals are routed on the solder side. The sides may be
reversed to match a particular OEM requirement.
64
10. Routing of the modem signals should provide maximum isolation between noise sources and sensitive
inputs. When layout requirements necessitate routing
these Signals together, they should be separated by
neutral signals. Refer to Table 14 forthe noise characteristics of each modem pin.
3-127
6
7
8
9
11
14
15
16
45
46
48
Neutral
3
4
5
10
13
22
24
25
29
31
34
42
43
47
49
Noise Sensitive
High
Low
23
27
32
33
35
36
37
26
28
•
R96MEB
Evaluation Board
'1'
R96MEB Modem Evaluation Board
Rockwell
INTRODUCTION
FEATURES
The Rockwell R96MEB (Modem Evaluation Board) aids
the original equipment manufacturer (OEM) during the
evaluation and design in phases of product development.
The R96MEB supports the R96MFX and the R96EFX
modems. The Modem Evaluation Board contains a socket (U1) for mounting the 64-pin quad in-line package
(QUIP) of the modem, plus support circuitry to configure a
complete data pump. For operation over the public
switched telephone network (PSTN), an appropriate line
termination, such as a data access arrangement (DAA),
must be provided externally.
• Convenient evaluation method for the R96MFX and
R96EFX
The R96MEB physical and electrical interface is compatible with the Rockwell R96FI/R96MD modem. For
users ofthe R96FI or R96MD, this feature provides a rapid
means of preparing to evaluate a 64-pin QUIP modem.
• Easily integrated into a prototype system
• Cost effective for low volume production applications
(R96MEBIF only)
• Simple connection
R96MEB/F: Standard 40-pin flat ribbon connector
R96MEB/D: Direct connect dual-in-line pins
• Backward compatible with R96FI hardware
(R96MEB/F)
• Low power consumption: 845 mW (typical)
• Small size:
R96MEB/F: 100 mm x 65 mm (3.94 in. x 2.56 in.)
The R96FI version of the modem evaluation board is the
R96MEB/F. Equipment previously developed for use with
the R96FI can be converted for use with the R96MEB by
changing only the software.
R96MEB/D: 50.8 mm x 65.4 mm (2.00 in. x 2.575 in.)
The R96MD version is the R96MEB/D. The R96MEB/D
hardware is similar to the R96MD except for the addition
and use of pins 35,36,37,40, and 41. Pin 41 is used for
ground and the other pins are used for the serial eye. The
R96MD does not use these pins, therefore, the software
and hardware must be changed.
R96MEB/F
R96MEB/D
R96MEB
Document No. 29200N45
Evaluation Board
Data Sheet
3-128
Order No. MD45
October 1988
Modem Evaluation Board
R96MEB
Table 1. R96MEB Connector Interface Signals
TECHNICAL SPECIFICATION
For a description of the R96MEB characteristics with a 64pin QUIP modem installed in socket U1, refer to the
R96MFX Modem Data Sheet (Order No. MD47) or the
R96EFX Modem Data Sheet (Order No. MD49).
Name
Power
I/O
Type
MEB/F
Pin No.
MEB/D
Pin No.
Description
14,39. 17,18, Power Supply Return
41
PWR
3,4
33,34 +5 volt supply
+ 5 volts
+ 12 volt supply
+12 volts
PWR
26
21
-12 volt Supply
-12 volts
PWR
37
19
Power-On Reset
INOD 36
39
POR
Microprocessor Interface
Data Bus Line 7
INOB 7
9
D7
8
Data Bus Line 6
D6
INOB 5
INOB 9
2
Data Bus Line 5
D5
Data Bus Line 4
D4
INOB 31
3
Data Bus Line 3
D3
INOB 15
4
INOB 28
5
Data Bus Line 2
D2
6
Data Bus Line 1
Dl
INOB 23
7
Data Bus Line 0
DO
INOB 29
13
Register Select 3
RS3
IA
30
8
14
Register Select 2
RS2
IA
RSI
IA
27
15
Register Select 1
16
Register Select 0
RSO
IA
10
IA
6
11
Chip Select 0
CSO
(Registers O-F)
38
Chip Select 1
CSI
IA
18
(Registers 10-1 F)
IA
1
10
Read Enable
READ-
c
>,.
I
FAST
«
«
r--.. . .
1
i
~
l"10
1
I
1
100
Seconds to Stabilize AGC for -55 DBM to 0 DBM Step
3-166
R96FI
9600 bps Facsimile Modem
Diagnostic Data Scaling (continued)
Node
18
Parameter/Scaling
"Group 2 PLL Frequency Correction (16 bits, twos complement)
Range:
FC6A'6 to 0346'6 representing ± 140 Hz
Frequency correction in Hz = Frequency correction number (0.167)
19
"Group 2 PLL Slew Rate
Represents gain of first order term in phase locked loop.
Range:
0010'6 to 7000'6 for stable operation
Directly proportional to PLL slew rate
20
"Group 2 Black/White Threshold (16 bits, unsigned)
Default value: (7800)'6
....
I/)
a:
;)
III
6
I
I I I
5
a:
'"
<'"
.......
111(,)
~II.
4
I
(,)0
u.'"
otii
a:
Q
"'I/)
3
2
1
I
I
6
F
0
0
6
C
0
0
NOTE:
1.100 WHITE PIXELS SENT FOLLOWED BY 4 BLACK
PIXELS SENT.
2. RESULTS OBTAINED AT 0 DBM, NO COMPROMISE
EQUALIZERS IN BACK TO BACK CONNECTION.
I I I
I I
III ...
:Ii'"
;)~
ZII.
7
8
0
0
7
6
0
0
7
2
0
0
7
0
0
0
6
8
0
0
6
A
0
0
THRESHOLD VALUE (HEXADECIMAL)
21
"Group 2 Phase limit (16 bits, twos complement)
When phase error exceeds this limit, PLL updating is suspended.
Default: 5000'6 representing ± 67.5 degrees
Phase limit = 180' _ [
(Phase Limit)'6 x 180' ] .
7FFF'6
Once phasing is acquired, the limits may be narrowed to improve immunity to phase hits, etc.
"See Rockwell Application Note, R96F Modem Recommended Receive Sequence for Group 2 Facsimile (Order No. 655, Rev. 3).
3·167
II
9600 bps Facsimile Modem
R96FI
Interface Memory Chip 1 (CS1)
Interface Memory Chip 0 (CSO)
I~r
sJ±'I:TIl
2
PDM
E
lAO
-
-
-
D
.-
-
-
-
C
-
-
-
-
A
-
-
-
9
-
-
-
-
-
-
7
-
-
--
-
0
-
i~
7
6
I5 I4
F
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CDET
-
-
-
-
-
-
1
0
-
-
-
-
D
-
-
-
-
-
-
C
-
-
-
-
-
-
-
B
FR3
FR2
FR1
-
-
-
_.
-
A
-
-
-
-
-
-
-
9
-
8
-
PNDET
-
-
-
-
FED
-
-
-
-
-
-
-
-
-
-
12
7
6
TlE
RlE
J3l
4
CONFIGURATION
5
4
3
RAM DATA XSM, FREOM
3
RAM DATA XBM
2
RAM DATA XSl; FREQl
2
RAM DATA XBl
1
RAM DATA YSM
1
RAM DATA YBM
0
RAM DATA YSl; TRANSCEIVER DATA
0
RAM DATA VBl
5
RTS
7:
7
TDIS
6
5
4
Bit
- =
Reserved (modem use only)
EPT
3
SOEXT
I
I
2
1
1
lRTH
I
I
I
0
~
!
-
17-
7
I
-
6
5
- = Reserved (modem
• = Added In 5301-20
3-168
4
3
FRT' RAMW
P2DET
2
I
-
G2FGC
-
-
-
-
i
Bit
I
MDA1
-
IA1
-
-
IE1
E
-
0
-
MDAO
-
1
-
-
-
2
RAM ACCESS B
-
lEO
SETUP'
3
I
Register
RAM ACCESS S
8
6
1
I
F
B
r---
6
7
Register
use only).
I
R96FI
9600 bps Facsimile Modem
Interface Memory Definitions
Mnemonic
Name
Memory
Location
Description
CDET
Carner Detector
t:70
The zero state of CDET Indicates passband energy IS being detected, and a training sequence IS
not present. CDET goes to zero at the start of the data state, and returns to one at the end of the
received signal CDET activates up to 1 baud time before RLSD and deactivates within 2 baud
times after RLSD
(None)
Configuration
04.0-7
The host processor configures the modem by writing a control code Into the configuration register
In the Interface memory space (See SETUP)
Configuration Control Codes
Control codes for the five available modem conflgurallons are
Configuration
Configuration Code (HEX)
V 299600
V 297200
V 294800
V.274800
V.272400
FSK
Group 2
Tone Transmit
14
12
11
OA
09
20
40
80
Configuration Definitions
Definitions for the five available modem conflgurallons are:
1 V 29. When any of the V.29 configurations has been selected, the modem operates as specified
In CCITT Recommendation V.29.
2 V.27 When any of the V.27 conflgurallons has been selectea, the modem operates as specified
In CCITT Recommendation V.27 ter.
3 FSK. The modem operates as a CCITT T30 compatible 300 bps FSK modem having
characteristics of the CCITT V21 channel 2 modulallon system.
4 Group 2 The modem operates as a CCITT T3 compatible AM modem ThiS configuration
permits transmission to and reception from Group 2 faCSimile apparatus A carner frequency of
2100 Hz IS used A black signal IS transmitted as no carner. The phase of the carner
, represenllng white IS reversed after each transition through black
When In the receive state, the modem recovers the carner of the remote transmitting modem to
perform a coherent demodulallon of the Incoming signal. ThiS technique allows a baseband of
3400 Hz to be recovered The recovered baseband Signal IS available on the microprocessor
bus
I
I
The baseband Signal IS converted to black or white by comparing the received Signal level
a preset threshold number ThiS number may be changed by the user.
Wlt~
Receiver data IS presented to the RXD output at a rate of 10368 samples per second The user
shOuld strobe tne data on the rising edge of the data clock (DCLK) A logical 1 level (high
voltage) represents white A logical 0 level (low voltage) represents black.
5 Tone Transmit. In thiS configuration, activating Signal RTS causes tne modem to transmit a tone
at a single frequency speCified by the user. Two registers In the host Interface memory space
contain the frequency code The most Sl9n1flcant bits are specified In the FREQM register (0'3).
The least Significant bits are specified In the FREQL register (0:2). The least Significant bit
represents 0 146486 Hz ± 001% The frequency generated IS: f = 0.146486 (256 FREQM + FREQL)
Hz ±0.01%.
EPT
Echo Protector
Tone
FED
Fast Energy
Detector
105'3
15:6
If EPT IS a one, an unmodulated carner is transmitted for 185 ms followed by 20 ms of no
transmitted energy at the beglnnmg of the tramlng sequence. ThiS option IS available In both the
V27 and V29 conflgurallons, although It IS not specified In the CCITT V.29 Recommendation.
The zero state of FED indicates energy IS present above the receiver threshold in the passband.
FED IS not used for Group 2 faCSimile
3-169
•
R96FI
9600 bps Facsimile Modem
Interface Memory Definitions (continued)
Mnemonic
(None)
Name
FREQUFREQM
Memory
Location
0:2:0-7,
0:3:0-7
Description
The host processor conveys tone generation data to the transmitter by writing a 16-bit data word to
the FREQL and FREQM registers in the interface memory space, as shown below.
FREQM Register (0:3)
IBit:
I
IData Word: I
7
I
I
6
5
I
I
4
2'2
1
4
I
3
I
2
I
1
2'0
1
I
2
I
I
o
I
o
I
J
1
FREQL Re9ister (0:2)
IBit:
I
IData Word: I
7
27
I
I
I
6
5
I
3
1
I
20
The frequency number (N) determines the frequency (F) as follows:
F = (0.146486) (N) Hz ±0.01%.
Hexadecimal frequency numbers (FREQM, FREQL) for commonly generated tones are given below:
FRT
Freeze Taps
FRI - FR3
Frequency 1,2,3
When FRT
1:B:5,6, 7
IS
Frequency (Hz)
FREQM
462
1100
1650
1850
2100
DC
52
lD
55
00
55
2C
31
38
FREQL
00
a one, adaptive equalization taps are prevented from changing.
The one state of FR1, FR2 or FR3 indicates reception of the respective tonal frequency when the
modem is configured for FSK. The default frequencies for FR1, FR2 and FR3 are:
Bit
Frequency (Hz)
FRI
FR2
FR3
2100
1100
462
G2FGC
Group 2 Fast
Gain Control
I:C:O
The one state of G2FGC selects a fast AGC rate (8.6 times standard) in Group 2 Facsimile.
IAI
Interrupt Active
(One)
I:E:7
IAI is a one when Chip 1 is driving IRQ to zero volts.
lAO
Interrupt Active
(Zero)
O:E:7
lAO is a one when Chip 0 is driving IRQ to zero volts.
lEO
Interrupt Enable
(Zero)
O:E:2
The one state of lEO causes the IRQ output to be low when the DAD bit is a one.
lEI
Interrupt Enable
(One)
I:E:2
The one state of lEI causes the IRQ output to be low when the DAI bit is a one.
J3L
Japanese 3 Link
1:D:4
The one state of J3L selects this standard for link amplitude equalizer. The zero state of J3L
selects U.S. survey long.
LRTH
Lower Receive
Threshold
0:5:0
The one state of LATH lowers the receiver turn-on threshold from - 43 dBm to - 47 dBm. (See
SETUP)
MDAO
Modem Data
Available (Zero)
O:E:O
MDAO goes to one when the modem reads or writes register 0:0. MDAO goes to zero when the
host processor reads or writes register 0:0. MDAO Is used for parallel mode as well as for
diagnostic data retrieval.
MOAI
Modem Data
Available (One)
I:E:O
MDAI goes to one when the modem writes register 1:0. MDAI goes to zero when the host
processor reads register 1:0.
PDM
Parallel Data
Mode
0:F:7
The one state of PDM places the modem in the parallel mode and inhibits the reading of Chip 0
diagnostic data.
3-170
R96FI
9600 bps Facsimile Modem
Interface Memory Definitions (continued)
Mnemonic
Name
Memory
Location
Description
PNDET
Period 'N'
Detector
1 7:S
The zero state of PNDET indicates a PN sequence has been detected. PNDET sets to a one et the
end of the PN sequence
P2DET
Period '2'
Detector
1:4'2
The zero state of P2DET Indicates a P2 sequence has been detected. P2DET sets to a one at the
start of the PN sequence.
(None)
RAM Access B
I.F·0-7
Contains the RAM access code used In reading or wrillng RAM 10callOns In Chip 1 (baud rate
device).
(None)
RAM Access S
O'F:O-S
Contains the RAM access code used In reading RAM locations
(None)
RAM Data XBL
1.2:0-7
Least slgmflcant byte of IS-bit word x used in reading RAM locations in Chip 1 (baud rate deVice).
(None)
RAM Data XBM
1'3:0-7
Most slgmflcant byte of 16-bit word
(None)
RAM Data XSL
02'0-7
Least slgmflcant byte of IS-bit word x used
deVice)
(None)
RAM Data XSM
0'3'0-7
Most slgmflcant byte of 16-bit word x used In reading RAM locations in Chip 0 (sample rate
deVice).
(None)
RAM Data YBL
1.0'0-7
Least Significant byte of 16-bit word y used
rate deVice) See DAI
(None)
RAM Data YBM
1:1:0-7
Most sigmflcant byte of 16-blt word y used in reading or Writing RAM locations
rate deVice).
(None)
RAM Data YSL
0.0'0-7
Least significant byte of 16-bIt word y used in reading RAM locations ,n Chip 0 (sample rate
deVice) Shared by parallel data mode for presenting channel data to the host microprocessor
bus. See Transceiver Data and DAO.
(None)
RAM Data YSM
0:10-7
Most slgmflcant byte of IS-bit word y used
deVice).
RAMW
RAM Write Chip 1
(baud rate deVice)
1:0'0
RAMW is set to a one by the host processor when performing diagnostic writes to the baud rate
deVice (Chip 1). RAMW IS set to a zero by the host when reading RAM diagnostic data from Chip 1.
RLE
Receiver Link
Equalizer
1.0'5
The one state of RLE enables the link amplitude equalizer
RTS
Request-to-Send
0:5:7
The one state of RTS beginS a transmit sequence. The modem Will continue to transmit until RTS
IS turned off, and the turn-off sequence has been completed. RTS parallels the operation of the
hardware RTS control input These Inputs are "ORed" by the modem.
SETUP
Setup
o E:3
The one state of SETUP causes the modem to reconfigure to the control word in the configuration
register, and to assume the options specified for equalizer (0'5'1) and threshold (0'5:0). SETUP
returns to zero when acted on by the modem. The time reqUired for the SETUP bit to cause a
change depends on the current state of the modem. The follOWing table lists worst case delays.
Current
State
V.21
DELAY
14 ms
G2
400
p$
x used
In
In
In
In
High Speed
Receiver
2 BAUD
In
Chip 0 (sample rate deVice).
reading RAM locations in Chip 1 (baud rate device).
reading RAM locations In Chip 0 (sample rate
reading or wriling RAM locations
In
In
Chip 1 (baud
Chip 1 (baud
reading RAM locations in Chip 0 (sample rate
In
the receiver.
High Speed Transmitter
2 BAUD + TURNOFF Sequence + Training (If
applicable) + SQUELCH (If applicable)
SQEXT
Squelch Extend
0:5'2
The one state of SQEXT Inhibits reception of signals for 130 ms after the turn-off sequence.
TOIS
Training Disable
0:5:6
If TDIS IS a one In the receive state, the modem IS prevented from entering the training phase. If
TDIS is a one prior to RTS gOing on, the generation of a training sequence is prevented at the
start of transmiSSion.
TLE
Transmitter Link
Equalizer
I'D:S
The one state of TLE enables the link amplitude equalizer In the transmitter
3-171
•
R96FI
9600 bps Facsimile Modem
Interface Memory Definitions (continued)
Mnemonic
(None)
Name
Transceiver Data
Memory
Location
0:0:0-7
Description
In receive parallel data mode, the modem presents eight bits of channel data in register 0:0 for
reading by the host microprocessor. After the eight bits have been accumulated in register O:C
they are transferred to 0:0 and bit O:E:O goes to a one. When the host reads 0:0, bit O:E:O resets
to a zero. The first bit of received data is not necessarily located in bit 0:0:0. The host must frame
the received data by searching for message sync characters. Bit O:E:O sets at one eighth the bit
rate in parallel data mode rather than at the sample rate (9600 Hz) as it does when reading RAM
locations.
In transmit parallel data mode the host stores data at location 0:0. This action causes bit O:E:O to
reset to a O. When the modem transfers the data from 0:0 to 0:2 bit O:E:O sets to a 1. The data is
serially transmitted from register 0:2 least significant bit first. Received data is shifted into register
O:C from MSB toward LSB.
T2
T/2 Equalizer
Select
0:5:1
If T2 IS a one, an adaptive equalizer with two taps per baud is used. If T2 is a zero, an adaptive
equalizer with one tap per baud IS used. The number of taps remains the same for both cases.
(See SETUP)
PERFORMANCE
At 4800 bps (V.27 ter), the modem exhibits a bit error rate of
10-6 or less with a signal-ta-noise ratio of 19 dB in the presence
of 15° peak-to-peak phase jitter at 60 Hz.
Whether functioning in V.27 ter or V.29 configuration, the modem
provides the user with unexcelled high performance.
TYPICAL BIT ERROR RATES
At 7200 bps (V.29), the modem exhibits a bit error rate of 10- 6
or less with a signal-to-noise ratio of 25 dB in the presence of
12° peak-to-peak phase jitter at 300 Hz.
The Bit Error Rate (BER) performance of the modem is specified
for a test configuration conforming to that specified in CCITT
Recommendation V.56. Bit error rates are measured at a
received line signal level of -20 dBm as illustrated.
At 9600 bps, the modem exhibits a bit error rate of 10-6 or less
with a signal-to-noise ratio of 23 dB in the presence of 10° peakto-peak phase jitter at 60 Hz. The modem exhibits a bit error
rate of 10-5 or less with a signal-ta-noise ratio of 23 dB in the
presence of 20° peak-ta-peak phase jitter at 30 Hz.
TYPICAL PHASE JITTER
At 2400 bps, the modem exhibits a bit error rate of 10-6 or less
with a signal-to-noise ratio of 12.5 dB in the presence of 15°
peak-to-peak phase jitter at 150 Hz or with a signal-to-noise ratio
of 15 dB in the presence of 30° peak-to-peak phase jitter at
120 Hz (scrambler inserted).
An example of the BER performance capabilities is given in the
following diagrams:
3-172
9600 bps Facsimile Modem
R96FI
V27,2400
F~K
\
V27,4800
V29,7200
/V29,9600
V29,4800 /
r
10-'
10-'
w
~
C
II:
II:
0
II:
II:
W
i
\\
\\
\
\
10- 5
\
10- 8
0
5
\
10
K
\
\
10-'
V27,2400
V29,4800
\
w
~
C
II:
II:
0
iii
1\
10- 5
\
15
20
25
,
\
10- 8
0
5
10
~
r--
IMPAIRMENT
SOURCE
BRADLEY 2A
AND2B
-
ATTENUATOR
HP 3500
I
I
MODEM
TEST SET
PHOENIX
5000
20
\
25
Typical Bit Error Rate
(Unconditioned 3002 Line, T Equalizer Level - 20 dBm)
r--
3002
LINE
SIMULATOR
SEG FA·1445
\
15
Signal 10 Noise Ratio in dB
Typical Bit Error Rate
(Back.to·Back, T Equalizer, Level -20 dBm)
-
•
W
~
Signal 10 Noise Ralio in dB
MODEM
TRANSMITTER
V29,9600
II:
II:
\
\
I
\
10-'
\
V27,4800
V29,7200
LEVEL
METER
HP 3552A
MODEM
RECEIVER
I
NOTE
SIGNAL AN 0 NOISE ARE MEASURED WITH 3 KHZ FLAT WEIGHTING.
BER Performance Test Set·up
3·173
9600 bps Facsimile Modem
R96FI
GENERAL SPECIFICATIONS
Power
Voltage
Tolerance
Current (Typical) @ 25°C
Current (Max) @ DOC
+5 Vdc
+ 12 Vdc
-12 Vdc
±5%
±5%
±5%
400 rnA
5 rnA
30 rnA
<500 rnA
< 10 rnA
< 50 rnA
Note: All voltages must have ripple sO.1 volts peak-to-peak.
Environmental
Parameter
Specification
Temperature
Operating
R96F
R96FI
Storage
Relative Humidity
O°C to + 60°C (32°F to 140°F)
OOC to + 70°C (32°F to 158°F)
-40°C to + 80°C (-40°F to 176°F) (Stored in heat sealed antistatic bag and shipping container)
Up to 90% noncondenslng, or a wet bulb temperature up to 35°C, whichever IS less
Mechanical
Parameter
Board Structure
Dimensions
Width
Length
Height
Weight (max.)
Lead Extrusion (max.)
Specification
Single PC board with single right angle header with 40 pins. Burndy FRS 40BS8P or equivalent
mating connector.
3.94 in. (100 mm)
2.56 in. (65 mm)
040 In. (10.2 mm)
2.6 oz. (73 g)
0100 in (254 mm)
-11
3. 937
1
(1°10~.J.,5
(93.3)
11',
I
I~
I'
(25.4)
0.277
t(7'04)
2.300 ~
0.125
(58,4) 2.559
(3.18)
r---
0.400
'"'
(85)
. COMPONENT AREA
-~r)---/----n--'--I--''f t:~~;-----------" 0.100 J
0.400
L
(1.6)
(2.54)
(10.16)
RleBON CONNECTOR VERSION
R96FI Dimensions and Pin Locations
3-174
MAX
R96MD
Integral Modems
'1'
Rockwell
R96MD
9600 bps Facsimile Modem
INTRODUCTION
FEATURES
The Rockwell R96MD IS a synchronous 9600 bits per second
(bps) modem. It IS designed for operation over the public
sWitched telephone network (PSTN) through line terminations
provided by a data access arrangement (DAA).
• Compatible With:
- CCITT V.29, V.27 ter, T.30, V.21 Channel 2, T.4, T.3
• Group 3 and Group 2 Facsimile
• Half-Duplex (2-Wlre)
• Programmable Tone Detection
• Programmable Dual/Single Tone Generation
• Dynamic Range: - 47 dBm to 0 dBm
• Programmable Transmit Levels
• Diagnostic Capability
• Equalization'
- Automatic Adaptive
- Compromise Cable (Selectable)
• DTE Interface:
- Microprocessor Bus
- CCITT V.24 (RS-232-C Compatible)
• Small Size: 50.8 mm x 65.4 mm (2.0 in. x 2.575 in.)
• Low Power Consumption: 2 W (Typical)
• Transmit Output Level: + 5 dBm ± 1 dB
• TTL and CMOS Compatible
The modem satISfies the telecommUnications requirements
specified in CCITT recommendations V.29, V.27 ter, T.30, T 4
and T.3. The R96MD can operate at speeds of 9600,7200,4800,
2400 and 300 bps. Employing advanced signal processing techniques, the R96MD can transmit and receive data even under
extremely poor line conditions.
The R96MD is designed for use in Group 3 facsimile machines
and IS also compatible With Group 2 machines. User programmable features allow the modem operation to be tailored to support a wide range of functional reqUirements. The modem's small
size, low power consumption, serial/parallel host interface, and
dual in-line pin (DIP) interface simplify system design and allow
direct installation on the host module.
R96MD Modem
Document No. 29200N34
Data Sheet
3-175
Order No. MD34
Rev. 1, January 1989
•
9600 bps Facsimile Modem
R96MD
TECHNICAL SPECIFICATIONS
EQUALIZERS
TRANSMITTER TONAL SIGNALING AND CARRIER
FREQUENCIES
The modem provides the following equalization functions which
can be used to improve performance'when operating over poor
lines:
T.30 Tonal Signaling Frequencies
Cable Equalizers - Selectable compromise cable equalizers
are provided to optimize performance over different lengths of
non-loaded cable of 0,4 mm diameter.
Frequency
(Hz ±0.010/0)
Function
Calling Tone (CNG)
Answer Tone (CEO)
Group 2 Identification (CI2)
Group 2 Command (GC2)
Group 2 Confirmation (CFR2, MCF2)
Line Conditioning Signal (LCS)
End of Message (EOM)
Procedure Interrupt (PIS)
1100
2100
1850
2100
1650
1100
1100
462
Automatic Adaptive Equalizer - An automatic adaptive equalizer IS proVided in the receiver circuit for V.27 and V.29 configurations. The equalizer can be configured as either a T or a T/2
equalizer.
TRANSMITTED DATA SPECTRUM
The transmitter spectrum is shaped by the following raised
cosme filter functions:
Carrier Frequencies
1. 1200 Baud.
2. 1600 Baud.
3. 2400 Baud.
Frequency
(Hz ±0.010/0)
Function
T.3 Carner (Group 2)
V.27 ter Carner
V.29 Carrier
2100
1800
1700
Square root of 90 percent.
Square root of 50 percent.
Square root of 20 percent.
The out-of-band transmitter power limitations meet those specified by Part 68 of the FCC's Rules, and typically exceed the
requirements of foreign telephone regulatory bodies.
TONE GENERATION
SCRAMBLER/DESCRAMBLER
Under control of the host processor, the modem can generate
voice band tones up to 4800 Hz with a resolullOn of 0.15 Hz and
an accuracy of 0.01%. Tones over 3000 Hz are attenuated.
The modem incorporates a self-synchronizmg scrambler/
descrambler. This facility IS 10 accordance with either V.27 ter
or V.29 depending on the selected configuration.
RECEIVED SIGNAL FREQUENCY TOLERANCE
TONE DETECTION
The receiver circUit of the modem can adapt to received frequency error of up to ± 10Hz with less than a 0.2 dB degradation in BER performance. Group 2 carrier recovery capture range
IS 2100 ± 30 Hz. The Group 2 receiver operates properly when
the carrier is vaned by ± 16 Hz at a 0.1 Hz per second rate.
In the 300 bps FSK receive configuration, the presence of tones
at preset frequencies is indicated by bits in the interface memory.
SIGNALING AND DATA RATES
RECEIVE LEVEL
Signaling/Data Rates
SpeCification
Baud Rate
(Symbols/Sec.)
Bits Per
Baud
Data Rate
(BPS)
(±O.OlO/o)
V.29
V.29
V.27
V.27
2400
2400
1600
1200
4
3
3
2
9600
7200
4800
2400
Symbol
POints
16
8
8
4
The modem receiver Circuit satisfies all specified performance
requirements for received line signal levels from 0 dBm to
- 43 dBm. The received line signal level IS measured at the
receiver analog Input (RXA).
RECEIVE TIMING
In the receive state, the modem provides a Data Clock (DCll<)
output In the form of a square wave, The low to high transitions
of this output coinCide with the center of received data bits. The
tlmmg recovery circuit is capable of tracking a ± 0.01 % frequency error in the associated transmit timing source. DClK
duty cycle IS 50% ± 1%.
DATA ENCODING
The modem data encoding conforms to CCID recommendations V.29 and V.27 ter.
3-176
R96MD
9600 bps Facsimile Modem
TRANSMIT LEVEL
RESPONSE TIMES OF CLEAR-TO-SEND (CTS)
The transmitter output level defaults to + 5 dBm ± 1 dB at power
on, When uSing the default transmit level and dnvlng a 600 ohm
load, the TXA output reqUires a 600 ohm senes resistor to
provide - 1 dBm ± 1 dB to the load, The output level can be
programmed over a 10 dB range by performing a RAM wnte
operation
The time between the off-te-on transition of RTS and the off-toon transition of CTS IS dictated by the length of the training
sequence Response time IS 253 ms forV,29, 708 msforV,27 ter
at 4800 bps, and 943 ms for V,27 ter at 2400 bps In V,21 CTS
turns on In 14 ms or less In Group 2 CTS turns on In 400 /LS
or less,
TRANSMIT TIMING
The time between the on-to-off transition of RTS and the on-tooff transition of CTS In the data state IS a maximum of 2 baud
times for all conflgurallOns,
In the transmit state, the modem provides a Oata Clock (OCLK)
output With the follOWing charactenstlcs:
1 Frequency Selected data rate of 9600, 7200, 4800, 2400,
or 300 Hz (±O,01%), In Group 2, OCLK tracks an external
10368 Hz clock, If the external clock Input (XCLK) IS grounded
the Group 2 OCLK IS 10372,7 Hz ±O 01%
2, Duty Cycle, 50 ± 1%
RECEIVED LINE SIGNAL DETECTOR (RLSD)
Transmit Oata (TXO) must be stable dunng the 1 microsecond
penod Immediately preceding and the 1 microsecond pen ad
Immediately follOWing the rising edge of OCLK,
For either V,27 ter or V 29, RLSO turns on at the end of the trainIng sequence, If training IS not detected at the receiver, the RLSO
off-to-on response time IS 15 ± 10 ms The RLSO on-to-off
response time for V 27 IS 10 ± 5 ms and for V,29 is 30 ± 9 ms
Response times are measured With a Signal at least 3 dB above
the actual RLSO on threshold or at least 5 dB below the actual
RLSO off threshold,
TURN-ON SEQUENCE
The RLSO on-to-off response time ensures that all valid data
bits have appeared on RXO,
Two threshold options are proVided'
1 Greater than - 43 dBm (RLSO on)
Less than - 48 dBm (RLSO off)
2 Greater than - 47 dBm (RLSD on)
Less than - 52 dBm (RLSO off)
A total of ten selectable turn-on sequences can be generated
by the modem, as defined In the follOWing table'
Turn-On Sequences
RTS-CTS Turn-On Time
Specification
Echo Protector
Tone Disabled
Echo Protector
Tone Enabled
V 29
V 274800 bps
V 272400 bps
253 ms
708 ms
943 ms
438 ms
913 ms
1148 ms
V 21 300 bps
Group 2
,;;14 ms
,;;400 P.s
,;;14 ms
,;;400 p'S
NOTE
Performance may be at a reduced level when the received
Signal IS less than - 43 dBm
A minimum hysteresIs actIOn of 2 dB eXists between the actual
off-to-on and on-to-off trans IlIOn levels, The threshold levels and
hysteresIs action are measured With an unmodulated 2100 Hz
tone applied to the receiver's audiO input (RXA)
MODES OF OPERATION
TURN-OFF SEQUENCE
The modem operates In 9IIher a senal or a parallel mode,
For V 27 ter, the turn-off sequence consists of approximately
10 ms of remaining data and scrambled ones at 1200 baud or
approximately 7 ms of data and scrambled ones at 1600 baud
followed by a 20 ms penod of no transmitted energy For V,29,
the turn-off sequence consists of approximately 5 ms of remainIng data and scrambled ones followed by a 20 ms penod of no
transmitted energy, In V 21 the transmitter turns off Within 7 ms
after RTS goes false, In Group 2 the transmitter turns off Within
200 /LS after RTS goes false,
SERIAL MODE
The senal mode uses standard V 24 (RS-232-C compatible) signals to transfer channel data, An opllOnal USRT deVice (shown
In the Modem FuncllOnallnterconnect Oiagram) Illustrates thiS
capability,
PARALLEL MODE
CLAMPING
The modem can transfer channel data eight bits at a time via
the microprocessor bus,
The follOWing clamps are prOVided With the modem'
1 ReceIVed Data (RXD), RXO IS clamped to a constant mark
(1) whenever RLSO IS off,
2 Received Lme Signal Detector (RLSD), RLSO IS clamped off
(squelched) dunng the time when RTS IS on,
3 Extended Squelch. Optionally, RLSO remains clamped off for
130 ms after the turn-off sequence,
Selection of either the serial or parallel mode of operallOn IS by
means of a control bit To enable the parallel mode, the control
bit must be set to a 1, The modem automatically defaults to the
senal mode at power-on In either mode the modem IS configured
by the host processor via the microprocessor bus,
MODE SELECTION
3-177
. .
_
R96MD
9600 bps Facsimile Modem
1"--------,•
CABS2
•
i::
CTS
•
DCLK
:-
USRT
(OPTIONAL)
.-:....
CABS1
RTS
TXD
RLSD
RXD
....
•
-'
J
L---.
R96MD
MODEM
+12V
+5V
POWER
SUPPLY
GND
READ
-12V
WRITE
DATA BUS (8)
HOST
PROCESSOR
(DTE)
ADDRESS BUS (4)
I DECODER
TXA
Di
RSi
RXA
LINE
INTERFACE
TELEPHONE
LINE
I... CS (21. .... CSI
POR
IRQ
+5
..A
.A
J
1.1
Modem Functional Interconnect Diagram
INTERFACE CHARACTERISTICS
V.24 Interface
The modem interface comprises both hardware and software
circuits. Hardware circuits are assigned to specific pins in a
4O-pin dual in-line pin (DIP) connector. Software circuits are
assigned to specific bits in a 32-byte interface memory.
Seven hardware circuits provide timing, data and control signals
for implementing a serial interface compatible with CCITT
Recommendation V.24. These signals interface directly with circuits using TTL logic levels (0, + 5 volt). These TTL levels are
suitable for driving the short wire lengths or printed circuitry
normally found within stand-alone modem enclosures or equipment cabinets.
HARDWARE CIRCUITS
Signal names and descriptions of the hardware circuits, including
the microprocessor interface, are listed in the Modem Hardware
Circuits table; the table column titled 'Type' refers to designations found in the Digital or Analog Interface Characteristics.
In applications where the modem is operated in parallel data
mode only (i.e., where the V.24 signals are unused), all V.24
PinS may remain unterminated.
Microprocessor Interface
Cable Equalizers
Sixteen hardware circuits provide address (RSO-RS3), data
(DD-07), control (CS, READ and WRITE) and interrupt (IRQ)
signals for implementing a parallel interface compatible with an
8080 microprocessor. (Refer to the Microprocessor Interface
Timing Waveforms figure and Microprocessor Interface Timing
Requirements table.) With the addition of a few external logic
gates, the interface can be made compatible with a wide variety
of microprocessors such as 6500, 6800, or 68000.
Modems may be connected by direct wiring, such as leased
telephone cable or through the public switched telephone network, by means of a data access arrangement. In either case,
the modem analog signal is carried by copper wire cabling for
at least some part of its route. The cable characteristics shape
the passband response so that the lower frequencies of the passband (300 Hz to 1700 Hz) are attenuated less than the higher
frequencies (1700 Hz to 3300 Hz). The longer the cable the more
pronou nced the effect.
The microprocessor interface allows a host microprocessor to
change modem configuration, read or write channel data as well
as diagnostic data, and supervise modem operation by means
of software strappable control bits and modem status bits. The
significance of the control and status bits and methods of data
interchange are discussed in the Software Circuits section.
To minimize the impact of this undesired passband shaping, a
compromise equalizer with more attenuation at lower frequenCies than at higher frequencies can be placed in series with the
analog signal. The modem includes three such equalizers
designed to compensate for cable distortion.
3-178
R96MD
9600 bps Facsimile Modem
Cable Equalizer Selection
CABS2
CABS1
Length of O.4mm Diameter Cable
0
0
1
1
0
1
0
1
0.0
1.8 km
36 km
72 km
•
•
•
•
•
No extended squelch
Higher receive threshold
Interrupts disabled
RAM Access S: 00
RAM Access B: 22
This configuration IS suitable for performing high speed data
transfer on the PSTN with the senal data port selected as the
input and output point for data terminal equipment (DTE).
Analog Signals
Modem Hardware Circuits
Name
Two analog signals, TXA and RXA, provide the interface point
for telephone company audio circuits.
Description
Pin No.
A. OVERHEAD:
Ground
+5 volts
+12 volts
-12 volts
POR
The TXA line IS an output suitable for driving an audio
transformer or data access arrangement for connection to either
leased lines or the PSTN. The output structure of TXA IS a low
impedance amplifier. A series resistor is required in order to
match this output to a standard telephone load of 600 ohms.
GND
PWR
PWR
PWR
1I0B
17,18
33,34
21
19
39
Power Supply Return
+ 5 volt supply
+ 12 volt supply
- 12 volt supply
Power-on-reset
B. MICROPROCESSOR INTERFACE:
RXA IS an input to the receiver from an audio transformer or data
access arrangement. The input Impedance is nominally
60K ohms but a factory select resistor allows a variance of 23%.
The RXA input must be shunted by an external resistor in order
to match a 600 ohm source. A 604 ohm ± 1% resistor is
satisfactory.
D7
D6
D5
D4
D3
D2
Dl
DO
Some form of transient protection for TXA and RXA is recommended when operating directly Into a transformer. This protection may be back-to-back zener diodes across the transformer
or a varistor across the transformer.
Overhead
Except for the power-on-reset signal paR, the overhead signals
are dc power or ground points. When the modem IS initially
energized a signal called Power-an-Reset (paR) causes the
modem to assume a valid operational state. The modem drives
pin 39 to ground during the beginning of the paR sequence.
Approximately 10 ms after the low to high tranSItion of Pin 39,
the modem is ready for normal use. The POR sequence IS
reimtiated anytime the + 5V supply drops below + 3.5V for more
than 30 ms, or an external device drives pin 39 low for at least
31's. When an external low input is applied to pin 39, the modem
is ready for normal use approximately 10 ms after the low input
is removed. Pin 39 is not driven low by the modem when the
POR sequence is inillated externally. In all cases, the POR
sequence requires 50 ms to 350 ms to complete. The paR
sequence leaves the modem configures as follows:
•
•
•
•
•
Type
1I0A
1I0A
1I0A
1I0A
1I0A
1I0A
1I0A
1I0A
9
8
2
3
4
5
6
7
RS3
RS2
RSI
RSO
IA
IA
IA
IA
13
14
15
16
CSO
CSI
READ
WRITE
IRQ
IA
IA
IA
IA
OB
11
38
10
12
1
Chip Select Sample Rate Device
Chip Select Baud Rate DeVice
Read Enable
Wnte Enable
Interrupt Request
30
31
32
28
27
26
29
Data Clock
External Clock for Group 2
Request-to-Send
Clear-to-Send
Transmitter Data
Receiver Data
Received Line Signal Detector
}
Data Bus (8 Bits)
}
Register Select (4 Bits)
Select Reg 0 - F
C. V.24 INTERFACE:
DCLK
XCLK
RTS
CTS
TXD
RXD
RLSD
OC
IB
IB
OC
IB
OC
OC
D. CABLE EQUALIZER:
CABSI
CABS2
IB
IB
24
25
Cable Select 1
Cable Select 2
23
22
20
Transmitter Analog Output
Receiver Analog Input
Auxiliary Analog Input
E. ANALOG SIGNALS
TXA
RXA
AUX
V.29/9600 bps
T/2 equalizer
Serial mode
Training enabled
Echo protector tone enabled
AA
AB
AC
Notes: 1 Pin 35 IS removed for keYing connector.
2 Unused inputs tied to + 5V or ground reqUire Individual
10K !J senes resistors.
3-179
•
R96MD
9600 bps Facsimile Modem
Microprocessor Interface Timing Requirements
Characteristic
Symbol
Min
CSi, RSi setup time prior
to Read or Write
TCS
Data Access time after Read
TDA
Data hold time after Read
TDH
TCH
WRITE
READ
CSi
(i = 0,1)
CSI, RSi hold time after
Read or Write
RSI
(i = 0-3)
Write data setup time
TWOS
Write data hold time
Write strobe pulse width
TWDH
TWR
Max
Units
30
-
ns
-
ns
10
140
50
10
75
10
75
-
ns
ns
ns
ns
ns
Analog Interface Characteristics
Name
Type
Characteristics
TXA
AA
The transmitter output IS a low Impedance
operational amplifier output. In order to
match to 600 ohms, an external 604 ohm
series resistor IS required.
RXA
AB
READ
The receiver Input impedance is
60K ohms ± 23%
AUXIN
Di
(i
= 0-7)
AC
Microprocessor Interface Timing Diagram
The aUXiliary analog Input allows access to
the transmitter for the purpose of Interfacing
with user proVided equipment. Because
thiS IS a sampled data input, any signal
above 4800 Hz will cause aliasing errors
The Input Impedance is lK ohms, and the
gain to the transmitter is - 0.4 dB ± 1 dB.
Digital Interface Characteristics
Input/Output Type
Symbol
Parameter
Units
IA
18
OA
V,H
Input Voltage, High
V
2.0 min.
2.0 min.
V'L
VOH
VOL
liN
10H
10L
IL
Ipu
Input Voltage, Low
Output Voltage, High
Output Voltage, Low
Input Current, Leakage
Output Current, High
Output Current, Low
Output Current, Leakage
Pull-up Current
(Short Circuit)
Capacitive Load
Capacitive Drive
CirCUit Type
V
V
V
0.8 max.
0.8 max
pA
mA
rnA
pA
±25 max.
CL
CD
Notes
I load = -100 pA
I load = 1.6 rnA
I load = -40 pA
V,N = 0.4 to 2.4 Vdc, Vec
1.
2.
3
4.
2.4 min.'
0.4 max 2
-0.1 max.
16 max
~A
pF
pF
5
=
TTL
w/Pull-up
=
0.36 rnA
525 Vdc
3-180
OC
0.4 max. 2
0.4 max
16 max
± 10 max.
1.6 max.
-240 max.
-10 min.
5
TTL
5 I load
08
2
I/O A
I/O 8
2.0 min.
5.25 max.
20 min.
0.8 max.
2.4 min.3
04 max. 5
0.8 max.
2.4 min. '
0.4 max. 2
± 125 max.-
-240 max.
-10 min
100
100
100
TTL
Open-Drain
Open Drain
w/Pull-up
10
100
3 State
Transceiver
-260 max.
-100 min.
40
100
Open-Drain
w/Pull-up
R96MD
9600 bps Facsimile Modem
SOFTWARE CIRCUITS
These bits are written into interface memory registers 0:3, 0:2,
0:1 and 0:0, or 1:3,1:2,1:1 and 1:0, in that order. Registers 3 and
2 contain the most and least significant bytes of XRAM data,
respectively, while registers 1 and 0 contain the most and least
significant bytes of YRAM data respectively.
The modem includes two signal processor chips. Each of these
chips contains 16 registers to which an external (host) microprocessor has access. Although these registers are within the
modem, they may be addressed as part of the host processor's
memory space. The host may read data out of or write data into
these registers. The registers are referred to as interface memory.
Registers in chip 0 update at the modem sample rate (9600 bps).
Registers in chip 1 update at the selected baud rate except in
Group 2 and FSK configurations when they update at the sample
rate.
When set to a one, bit 0:5:5 (RAMWS) or bit l:D:O (RAMWB)
causes the modem to suspend transfer of RAM data to the interface memory, and instead, to transfer data from Interface memory
to RAM in chip 0 or in chip 1, respectively. When writing into
the RAM, only 16 bits are transferred, not 32 bits as for a read
operation. The 16 bits written in XRAM or YRAM come from
registers 1 and 0, with register 1 being the most significant byte.
Selection of XRAM or YRAM for the destination is by means of
the code stored in the RAM Access B bits of register l:F for
chip 1, or by means of 0:5:4 (RAE) and O:F (RAM Access S) for
chip O. When bit tF:7 or 0:5:4 is set to one, the XRAM is selected.
When 1:F:7 or 0:5:4 equals zero, YRAM is selected.
When information in these registers is being discussed, the format Y:Z:Q is used. The chip is specified by yeO or 1), the register
by Z(O-F), and the bit by Q(0-7, 0 = LSB). A bit is considered to
be "on" when set to a 1.
Status/Control Bits
When the host processor reads or writes register 0, the modem
data available bit O:E:O or l:E:O (MDAi) is reset to zero. When
the modem reads or writes register 0, MDAi is set to a one. When
setto a one by the host, bitO:E:2 or 1:E:1 (lEi) enables the MDAi
bit to cause an IRQ interrupt when set. While the IRQ line IS
driven to a TTL low level by the modem, bit 0:E:7 or 1:E:7 (IAi)
goes to a one.
Modem operation IS affected by a number of software control
inputs. These inputs are written into registers within the Interface memory via the host microprocessor bus. Modem operation is monitored by various software flags that are read from
interface memory via the host microprocessor bus. All status and
control bits are defined in the Interface Memory table. Bits
designated by a ' - ' are reserved for modem use only and must
not be changed by the host.
RAM Access Codes
The RAM access codes defined in the follOWing table allow the
host processor to read diagnostic information within the modem.
ThiS information is scaled as shown in the Diagnostic Data
Scaling table.
Anyone of the registers may be read or written on any host read
or write cycle, but all eight bits of that register are affected. In
order to read a single bit or a group of bits in a register, the host
processor must mask out unwanted data. When writing a single
bit or group of bits in a register the host processor must perform
a read-modify-write operation. That is, the entire register is read,
the necessary bits are set or reset in the accumulator of the host,
then the original unmodified bits and the modified bits are written back into the register of the interface memory.
RAM Access Codes
Node
1
2
3
4
5
6
7
8
9
10
11
12
13
14
RAM Data Access
The user can access much of the data stored in the modem's
memories. This data is a useful tool in performing certain
diagnostic functions.
The modem contains 128 words of random access memory
(RAM). Each word is 32-bits wide. Because the modem is
optimized for performing complex arithmetic, the RAM words are
frequently used for storing complex numbers. Therefore, each
word is organized into a real part (16 bits) and an imaginary part
(l6-bits) that can be accessed Independently. The portion of the
word that normally holds the real value is referred to as XRAM.
The portion that normally holds the imaginary value is referred
to as YRAM. The entire contents of XRAM and YRAM may be
read by the host processor via the microprocessor interface.
15
16
17
18
19
20
21
22
23
24
25
26
27
The interface memory acts as an intermediary during these host
to signal processor RAM data exchanges. The RAM address to
be read from or written to is determined by the contents of register
O:F (RAM ACCESS S) or tF (RAM ACCESS B). The RAM Access
Codes table lists access codes for storage in registers O:F or l:F
and the corresponding diagnostic functions. Each RAM word
transferred to the Interface memory IS 32 bits long.
Read
Function
Access RAE Chip Reg. No.
2,3
Received Signal Samples
40
X
0
0,1,2,3
Demodulator Output
42
X
0
0,1,2,3
Low Pass Filter Output
54
X
0
Average Power
5C
X
0
2,3
X
2,3
AGC Gam
3C
0
2,3
Tone 1 Frequency
71
1
0
1
2,3
Tone 1 Level
72
0
Tone 2 Frequency
71
0
0
0,1
0,1
Tone 2 Level
72
0
0
0,1
Output Level
4C
0
0
Equalizer Input
N.A
1
0,1,2,3
40
Equalizer Tap CoeffiCients
01-20 NA 1
0,1,2,3
0,1,2,3
Unrotated Equalizer Output
61
NA. 1
0,1,2,3
Rotated Equalizer Output
22
NA 1
(Received POint-Eye Pattern)
Decision Pomts (Ideal)
62
NA
1
0,1,2,3
NA. 1
0,1,2,3
Error Vector
63
N.A
1
0,1
Rotation Angle
00
Frequency Correction
N.A
1
2,3
AS
2,3
Eye Quality Momtor (EQM)
AB
NA. 1
2,3
G2 Baseband Signal
C8
NA 1
AD
NA. 1
2,3
G2AGC Gam
AA
NA 1
2,3
G2 AGC Slew Rate
G2 PLL Frequency Correcllon
C2
N.A. 1
2,3
FO
N.A
1
2,3
G2 PLL Slew Rate
G2 BlacklWhite Threshold
2A
N.A. 1
0,1
2,3
G2 Phase Limit
F2
N.A. 1
2,3
Checksum
2D
N.A. 1
RAE = X is don't care smce thiS location should only be read
from, and not written to, by the host. N.A. is not
applicable since RAE is not used m chip one.
3-181
•
R96MD
9600 bps Facsimile Modem
Diagnostic Data Scaling
Node
1
ParameterlScaling
Received Signal Samples
= AID Sample Word (signed 16 bits, twos complement)
ViNT
SIGNAL
VEXT
. -----+ IA DEVICE ~
PROCESSOR
CHANNEL
t
2,3,
11,13
14,15
V
INT
.2..
= (AID Sample Word)'6 x
Volts
(40)'6
256
VEXT = V INT
LOG,o' [ AGC
-
AGC WORD
All Baseband Signal Nodes (32 bits, complex, twos complement)
Configuration
Point
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
.
G
.
@)
V.2919600
x,Y
V.29n200
x,Y
0000,2800
2BOO, 0000
OOOO,DBOO
0800, 0000
0000,1800
1800, 1800
1800, 0000
1800, EBoo
0000, E800
E800, E800
E800, 0000
E800, 1800
0800,OBOO
0800, FBOO
F800, F800
F800, 0800
0000,2400
2400, 0000
ooOO,DCoo
DCoo, 0000
acoo, OCOO
OCOO, F400
F400, F400
F400, OCOO
.
0
G G-G).. ,
G G~
0
.
,
V.29/9600 BPS
V.29/4800 & V.27/2400
0000,
lFoo,
0000,
Eloo,
6
.
0
0
0
0
V.27/4800
x,Y
x,Y
lFOO
0000
El00
0000
0000, 1Faa
1600,1600
lFoo, 0000
1600, EAOO
0000, El00
EAOO, EAOO
El00, 0000
EAoo, 1600
,
0
,
.
-0-
.
II>
CD
Range
c(
0000'6 to 7FFF'6
'M'
7000
'"
'iii
\
\
:::I
c
3000
~
==CD
2000
iii
1000
CD
i\
\
1\
1\
::I
>
r--.~
><
CD
:r:
01
1
1
~
10
100
Seconds to Stabilize AGe for -55 OBM to 0 OBM Step
3-184
R96MD
9600 bps Facsimile Modem
Diagnostic Data Scaling (continued)
Node
23
Parameter/Scaling
'Group 2 PLL Frequency Correction (16 bits, twos complement)
Range:
FC6A'6 to 0346'6 representing ± 140 Hz
Frequency correction In Hz
24
=
Frequency correcllon number (0167)
'Group 2 PLL Slew Rate
Represents gain of first order term In phase locked loop
Range:
0010'6 to 7000'6 for stable operation
Directly proportional to PLL slew rate
25
'Group 2 Black/White Threshold (16 bits, unsigned)
Default value (7800),6
I-
(J)
a:
::>
al
a:
UJ
6
>c:1l.
uc 4
~
Zll.
I
I
I
I
6
F
0
0
6
C
0
0
6
A
0
0
NOTE:
1.100 WHITE PIXELS SENT FOLLOWED BY 4 BLACK
PIXELS SENT.
2. RESULTS OBTAINED AT 0 DBM, NO COMPROMISE
EQUALIZERS IN BACK TO BACK CONNECTION.
6
8
0
0
THRESHOLD VALUE (HEXADECIMAL)
26
'Group 2 Phase Limit (16 bits, twos complement)
When phase error exceeds thiS limit, PLL updating IS suspended.
Default. 5000'6 representing ± 675 degrees
Phase limit
=
180 0
(Phase Llmlt)'6
-
[
(7FFF)'6
x 180 0
]
Once phasmg IS acqUIred, the limits may be narrowed to Improve Immunity to phase hits.
27
Checksum (16-bit unsigned)
ROM checksum number determined by revIsion level
'See Rockwell Application Note. R96F Modem Recommended Receive Sequence for Group 2 Facsimile (Order No. 655, Rev. 3).
3-185
•
9600 bps Facsimile Modem
R96MD
Interface Memory Chip 0 (CSO)
Interface Memory Chip 1 (CS1)
[-IT:
~t
"--I~-- ---'-7~I_ ' I :-311.2I
iitt
BB-r-
IRegiS~
F=-""---">j-·---
I
I
I
--~------'---'--_j
-
F
PDM
~
I~
==
==
==
~
==
==
==
--c----
2
~
C±
RAM ACCESS S
SE~UP I~~
~~=L~~
~ ~ ~ ~~ '~ -~ I~i
6
f--5
RTS
-
-
-
TOIS RAMWS RAE
EPT
-
---[-
SQEA'T I T2
lRTH
CONFIGU.R__
AT_IO-=--N_____________ ~
4
RAM DATA XSM, FREQM
2
RAM DATA XSl; FREQl
1
RAM DATA YSM
[7:1'
- =
6
5
IAI
-
-
-
-
4
-
-
-
lEI
--
-
-
-
MDAI
FRT RAMWB
-
-
-
-
-
-
-
-
-
A
-
-
9
-
-
-
-
-
-
-
8
-
7
-
6
-
-
5
--
FED
PNDET
-~,---
-
G2FGC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
0
-
P2DET
3
RAM DATA XBM
2
RAM DATA XBl
- =
3-186
-
-
-
CDET
RAM DATA YBM
RAM DATA YBl
7
6
5
Bit
Reserved (modem use only)
0
FRI
17.
:"
1
RAM ACCESS B
1
---- 0
--
,~M :'~ ffi:M"'~rJ~jl
2
3
FR2
4
j
1
FR3
~-
3
7
IRegister '"
Reserved (modem use only)
4
I
i
3
2
R96MD
9600 bps Facsimile Modem
Interface Memory Definitions
Mnemonic
Name
Memory
location
Description
COET
Carrier Detector
1:7:0
The zero state of COET indicates passband energy is being detected, and a training sequence is
nol present. CDET goes to zero at the start of the data state, and returns to one at the end of the
received signal. CDET activates up to 1 baud time before RLSD and deactivates within 2 baud
times after RLSD,
(None)
Configuration
0:4:0-7
The host processor configures the modem by writing a control code into the configuration register
in the interface memory space. (See SETUP)
Configuration Control Codas
Control codes for the eight available modem configurations are:
Configuration
V.299600'
V.297200
V.274800
V.272400
FSK
Group 2
Tone Transmit
DTMF Transmit
Configuration Code (HEX)
14
12
OA
09
20
40
80
81
'Default at POR.
Configuration Definitions
1. V.29. When a V.29 configuration has been selected, the modem operates as specified in
CCITT Recommendation V.29.
2. V.27. When a V.27 configuration has been selected, the modem operates as specified in CCITT
Recommendation V.27 ter.
3. FSK. The modem operates as a CCITT T.30 compatible 300 bps FSK modem having
characteristics of the CCITT V.21 channel 2 modulation system.
4. Group 2. The modem operates as a CCITT T.3 compatible AM modem. This configuration
permits transmission to and reception from Group 2 facsimile apparatus. A carrier frequency of
2100 Hz is used. A black signal is transmitted as no carrier. The phase of the carrier
representing white is reversed after each transition through black.
When in the receive state, the modem recovers the carrier of the remote transmitting modem to
perform a coherent demodulation of the incoming signal. This technique allows a baseband of
3400 Hz to be recovered. The recovered baseband signal is available on the microprocessor
bus.
The baseband signal is converted to black or white by comparing the received signal level with
a preset threshold number. This number may be changed by the user.
Receiver data is presented to the RXD output at a rate of 10368 samples per second. The user
should strobe the data on the rising edge of the data clock (DCLK). A logical 1 level (high
voltage) represents white. A logical 0 level (low voltage) represents black.
5. Tone Transmit. In this configuration, activating signal RTS causes the modem to transmit a
tone at a single frequency specified by the user. Two registers in the host interface memory
space contam the frequency code. The most significant bits are specified in the FREOM
register ~0:3). The least Significant bits are specified in the FREOL register (0:2) The least
significant bit represents 0.146486 Hz ± 0.01%. The frequency generated is:
f = 0.146486 (256 FREOM + FREOL) Hz ± 0.01%.
6. DTMF Transmit. In this configuration, activatmg RTS causes the modem to transmit two tones at
frequencies and output levels specified by the user By using the RAM Data Access routines,
the user can program the tones and levels
3-187
•
9600 bps Facsimile Modem
R96MD
Interface Memory Definitions (Continued)
Mnemonic
Name
Memory
Location
Description
EPT
Echo Protector
Tone
0.5.3
If EPT IS a one, an unmodulated carrier is transmitted for 185 ms followed by 20 ms of no
transmitted energy at the begmmng of the traming sequence. This option is available in both the
V.27 and V.29 configurations, although it is not specified in the CCITT V.29 recommendation.
FED
Fast Energy
Detector
1.5:6
The zero state of FED Indicates energy IS present above the receiver threshold in the passband.
FED IS not used for Group 2 Facsimile.
(None)
FREQUFREQM
0:2:0-7,
0:30-7
The host processor conveys tone generation data to the transmitter by writing a IS-bit data word to
the FREQL and FREQM registers in the interface memory space, as shown below
FREQM Register (0:3)
IBit
I
IData Word: I
7
2 15
I
I
6
214
I
I
I
6
26
I
5
213
I
I
4
212
I
4
24
I
3
211
I
I
2
I
1
I
0
I
I
2 10
I
211
I
211
I
I
2
22
I
1
21
I
0
2.0
I
FREQL Register (0:2)
I~:~
Word:
I
7
27
5
25
I
3
23
The frequency number (N) determines the frequency (F) as follows:
F = (0.146486) (N) Hz ± O.OWo.
Hexadecimal frequency numbers (FREQM, FREQL) for commonly generated tones are given below:
FRT
Freeze Taps
FRI - FR3
Frequency 1,2,3
Frequency (Hz)
FREQM
FREQL
462
1100
1650
1850
2100
OC
10
2C
31
38
52
55
00
55
00
When FRT IS a one, adaptive equalization taps are prevented from changing.
I:B:5,6,7
The one state of FR1, FR2 or FR3 indicates recepllOn of the respective tonal frequency when the
modem IS configured for FSK. The default frequencies for FR1, FR2 and FR3 are:
Bit
Frequency (Hz)
FRI
FR2
FR3
2100
1100
462
G2FGC
Group 2 Fast
Gam Control
I:CO
The one state of G2FGC selects a fast AGC rate (8.6 times standard) m Group 2 Facsimile.
IAI
Interrupt Active
(One)
I:E'7
IAI IS a one when Chip 1 IS driVing IRQ to zero volts.
lAO
Interrupt Active
(Zero)
0:E:7
lAO IS a one when Chip 0 is driving IRQ to zero volts.
lEO
Interrupt Enable
(Zero)
0:E:2
The one state of lEO causes the IRQ output to be low when the DAO bit IS a one.
lEI
Interrupt Enable
(One)
I:E:2
The one state of lEI causes the IRQ output to be low when the DAI bit is a one.
LATH
Lower Receive
Threshold
0:50
The one state of LRTH lowers the receiver turn-on threshold from - 43 dBm to - 47 dBm (See
SETUP)
MDAO
Modem Data
Available (Zero)
O'EO
MDAO goes to one when the modem reads or writes register 0:0. MDAO goes to zero when the
host processor reads or writes register 0 O. MDAO IS used for parallel mode as well as for
diagnostic data retrieval
3-188
R96MD
9600 bps Facsimile Modem
Interface Memory Definitions (Continued)
Mnemonic
Name
Memory
location
Description
MDAI
Modem Data
Available (One)
I:E:O
MDAI goes to one when the modem writes register 1'0. MDAI goes to zero when the host
processor reads register 1:0.
PDM
Parallel Data
Mode
0:F:7
The one state of PDM places the modem in the parallel mode and inhibits the reading of Chip 0
diagnostic data.
PNDET
Period 'N'
Detector
1:7:6
The zero state of PNDET indicates a PN sequence has been detected. PNDET sets to a one at the
end of the PN sequence.
P2DET
Period '2'
Detector
1:4:2
The zero state of P2DET Indicates a P2 sequence has been detected. P2DET sets to a one at the
start of the PN sequence.
(None)
RAM Access B
I:F:0-7
Contains the RAM access code used in reading or writing RAM locations in Chip 1 (baud rate
device).
(None)
RAM Access S
0:F:0-6
Contains the RAM access code used In reading or writing RAM locations in Chip 0 (sample rate
device).
(None)
RAM Data XBl
1:2:0-7
least significant byte of 16-bit word x used in reading RAM locations in Chip 1 (baud rate device).
(None)
RAM Data XBM
1:3:0-7
Most significant byte of 16-bit word x used in reading RAM locations In Chip I (baud rate device).
(None)
RAM Data XSl
0:2:0-7
least significant byte of 16-blt word x used In reading RAM locations in Chip 0 (sample rate
device).
(None)
RAM Data XSM
0:3:0-7
Most significant byte of 16-bit word x used in reading RAM locations in Chip 0 (sample rate
device).
(None)
RAM Data YBl
1:0:0-7
Least significant byte of 16-bit word y used in reading or writing RAM locations in Chip 1 (baud
rate device). See DAI.
(None)
RAM Data YBM
1:1:0-7
Most significant byte of 16-bit word y used In reading or writing RAM locations In Chip 1 (baud
rate device).
(None)
RAM Data YSL
0:0:0-7
Least significant byte of 16-bit word y used in reading or writing RAM locations in Chip 0 (sample
rate device). Shared by parallel data mode for presenting channel data to the host microprocessor
bus. See 1tansceiver Data and DAD.
(None)
RAM Data YSM
0:1:0-7
Most significant byte of 16-bit word y used in reading or writing RAM locations in Chip 0 (sample
rate device).
RAE
RAM Address
Extension
0:5:4
This bit is an extension of RAM Access S when RAMWS is a one. During a RAM write to Chip 0,
when RAE Is a 1 the XRAM is selected and when RAE is a 0 the YRAM is selected.
RAMWB
RAM Write Chip 1
(baud rate
device)
1:0:0
RAMWB is set to a one by the host processor when performing diagnostic writes to the baud rate
device (Chip 1). RAMWB is set to a zero by the host when reading RAM diagnostic data from
Chip 1.
RAMWS
RAM Write Chip 0
(sample rate
device)
0:5:5
RAMWS is set to a one by the host processor when performing diagnostic writes to the sample
rate device (Chip 0). RAMWS is set to a zero by the host when reading RAM diagnostic data from
ChipO.
RTS
Request-to-Send
0:5:7
The one state of RTS begins a transmit sequence. The modem will continue to transmit until RTS
is tumad off, and the turn-off sequence has been completed. RTS parallels the operation of the
hardware ATS control input. These inputs are "ORed" by the modem.
SETUP
Setup
0:E:3
The one state of SETUP causes the modem to reconfigure to the control word in the configuration
register, and to assume the options specified for equalizer (0:5:1) and threshold (0:5:0). SETUP
returns to zero when acted on by the modem. The time required for the SETUP bit to cause a
change depends on the current state of the modem. The following table lists worst case delays.
Current
State
V.21
G2
High Speed
Receiver
DELAY
14 ms
400 P.s
2 BAUD
3-189
High Speed 'll'ansmltter
2 BAUD + TURNOFF Sequence + Training (if
applicable) + SQUELCH (if applicable)
II
9600 bps Facsimile Modem
R96MD
Interface Memory Definitions (Continued)
Mnemonic
Name
Memory
Location
Description
SOEXT
Squelch Extend
0.5'2
The one state of SOEXT Inhibits reception of signals for 130 ms after the turn-off sequence.
TDIS
Training Disable
0:5:6
If TDIS is a one in the receive state, the modem IS prevented from entering the training phase If
TDIS IS a one pnor to RTS gOing on, the generallon of a training sequence IS prevented at the
start of transmission.
(None)
Transceiver Data
0.00-7
In receive parallel data mode, the modem presents eight bits of channel data In register 0 0 for
reading by the host microprocessor. After the eight bits have been accumulated In register O'C
they are transferred to 00 and bit O·E.O goes to a one. When the host reads 0:0, bit O.E:O resets
to a zero The first bit of received data is not necessanly located In bit 0.0:0. The host must frame
the received data by searching for message sync characters Bit O'E:O sets at one eighth the bit
rate In parallel data mode rather than at the sample rate (9600 Hz) as it does when reading RAM
locations.
In transmit parallel data mode the host stores data at location 0:0 This acllon causes bit O:E:O to
reset to a O. When the modem transfers the data from 0'0 to 0:2 bit O:E:O sets to a 1. The data IS
senally transmitted from register 0.2 least Significant bit first. Received data is shifted into register
O'C from MSB toward LSB.
T2
TI2 Equalizer
Select
0.5'1
If T2 IS a one, an adaptive equalizer with two taps per baud IS used. If T2 IS a zero, an adaptive
I equalizer with one tap per baud is used. The number of taps remains the same for both cases
(See SETUP)
PERFORMANCE
At 4800 bps (V.27 ter), the modem exhibits a bit error rate of
10- 6 or less with a signal-to-noise ratio of 19 dB in the
presence of 15° peak-to-peak phase jitter al 60 Hz.
Whether functioning in V.27 ter or V.29 configuration, the modem
provides the user with unexcelled high performance.
TYPICAL BIT ERROR RATES
At 7200 bps (V.29), the modem exhibits a bit error rate of 10- 6
or less with a signal-to-noise ratio of 25 dB in the presence of
12° peak-to-peak phase jitter at 300 Hz.
The Bit Error Rate (BER) performance of the modem is specified
for a test configuration conforming to that specified in CCITT
Recommendation V.56. Bit error rates are measured at a
received line signal level of - 20 dBm as illustrated.
At 9600 bps, the modem exhibits a bit error rate of 10- 6 or less
with a signal-to-nolse ratio of 23 dB in the presence of 10° peakto-peak phase jitter at 60 Hz. The modem exhibits a bit error
rate of 10- 5 or less with a signal-to-noise ratio of 23 dB in the
presence of 20° peak-to-peak phase jitter at 30 Hz.
TYPICAL PHASE JITTER
At 2400 bps, the modem exhibits a bit error rate of 10- 6 or less
with a signal-to-noise ratio of 12.5 dB in the presence of 15°
peak-to-peak phase jitter at 150 Hz or with a signal-to-noise ratio
of 15 dB in the presence of 30° peak-te-peak phase jitter at
120 Hz (scrambler inserted).
The BER curves shown were prepared from data obtained using
a TAS 1000 communication test system.
3-190
R96MD
9600 bps Facsimile Modem
V27,2400
F~K
V27,4800
V29,7200
/V29,9800
V27,4800
V29,7200
V29,9800
V27,2400
f SK
10- 3
10- 3
\
10-'
10-'
\
w
i
i
W
I-
~
II:
iII:
w
Ii
10-
•
w
Ii10-
1\
5
\
10- 1
0
5
\
10
i
\
,
15
20
5
,
10- 6
25
0
Signal to Nolae Ratio In dB
5
\
10
15
I
20
\
25
Signal to Nolle Ratio In dB
~pical Bit Error Rate
(Back-to-Back, T Equalizer, Level - 20 dBm)
~plcal Bit Error Rate
(Unconditioned 3002 Line, T Equalizer, Level - 20 dBm)
3-191
R96MD
9600 bps Facsimile Modem
GENERAL SPECIFICATIONS
Power
Voltage
Tolerance
Current (Typical) @ 25°C
Current (Max) @ DoC
+5 Vdc
+ 12 Vdc
-12 Vdc
±50/o
±5%
±5%
350 mA
5 mA
30 mA
<500 rnA
< 10 mA
< 50 mA
i
Note: All voltages must have ripple sO.1 volts peak-to-peak.
Environmental
Parameter
Specification
Temperature
Operating
Storage
Relative Humidity
O°C to + 60°C (32°F to 140°F)
- 40°C to + 80°C (- 40°F to 176°F) (Stored In heat sealed antistatic bag and shipping container)
Up to 90% noncondensing, or a wet bulb temperature up to 35°C, whichever is less.
Mechanical
Specification
Parameter
Board Structure
Dimensions
Width
Length
Component Height
Weight (max.)
Pins
Length above PCB
Thickness
Plating
Single PC board with a row of 20 pinS and a row of 20 pins In a dual-in-line pin conftguratton.
Mates with Berg 65780 or eqUivalent
2 a in (50.8 mm)
2.575 in (65.4 mm)
0.30 In (76 mm) above, 0.13
2.6 oz. (73 g)
In.
(3.30 mm) below
0.300 tn. ± 0 015 in. (7.6 ± 0.38 mm), 0.433 ± 0.015
0025 In (0 64 mm) square
Gold
In.
(11 ± 0.38 mrn), 0.535 ± 0015 (13.6 ± 0.38 mm)
i----- (63
2.50
I
5) ------,
0.025 SO PINS (41 PL)
--0.100 Typi )0.64)
I
(2.54)
t
/
ooooooooooo@--'-
000000
1
I
1.850
(47)
BETWEEN
PINS
20
11.875 REF
(47.6)
I
2.000
(50.8)
!
0.(175
(1.9)
21
I
..
\ 0.063
DIA
(1:6) (2 PL)
~.575
,(65.4)
T+
I
1-I
---J
SEE MECH
[ SPECIFICATION
TABLE
inches
mm
i
i
I
oocx::@:looooooooooooo
40
~+-~
I
0.300 MAX--,
(7.6)
I
-------;~
~-- - - ~-+ f
,-----
L'_____
I
I'(1:6)
0.062 REF
L0.130
MAX
(3.3)
COMPONENT AREA
R96MD Dimensions and Pin Locations
3-192
l
R144HD
Integral Modems
'1'
Rockwell
R144HD
14400 bps Half-Duplex Modem
INTRODUCTION
FEATURES
• Compatibility:
- CCITT V.33, V.29, V.27 ter, T.30, V.21 Channel 2, T.4, T.3
- Trellis Coded Modulation (TCM) at 14400, 12000, 9600
and 7200 bps
- Short Train in TCM Configurations
• Group 3 and Group 2 Facsimile
• Half-Duplex (2·Wire)
• Programmable Tone Detection
• Programmable Dual/Single Tone Generation
• Dynamic Range: -43 dBm to 0 dBm; also available from
-43 dBm to -6 dBm
• Diagnostic Capability
• Equalization:
- Automatic Adaptive
- Compromise Cable and Link (Selectable)
• DTE Interface:
- Microprocessor Bus
- CCITT V.24 (RS-232-C Compatible)
• Transmit Output Level: + 5 dBm ± 1 dBm
• Small Size: 100 mmx82 mm (3.94 in. x 3.23 in.)
• Power Consumption: 4.2W (Typical)
• TTL and CMOS Compatible
The Rockwell R144HD is a synchronous 14400 bits per second
(bps) half-duplex modem. It is designed for operation over the
public switched telephone network (PSTN) through line terminations provided by a data access arrangement (DAA).
The modem satisfies the telecommunications requirements
specified in CCITT recommendations V.33, V.29, V.27 ter, T.30,
T.4 and T.3. The R144HD can operate at speeds of 14400,
12000,9600,7200,4800,2400 and 300 bps.
The R144HD is designed for use in Group 3 facsimile machines
and is also compatible with Group 2 machines. User programmable features allow the modem operation to be tailored to support a wide range of functional requirements. The modem's small
size, low power consumption, serial/parallel host interface, and
standard connector simplify system design and allow installation
in a compact encl(lsure. A proprietary V.33 short train feature
provides faster connection time at the high speeds required for
facsimile transmission.
R144HD Modem
Document No. 29200N33
Data Sheet
3-193
Order No. MD33
Rev. 3, January 1989
•
R144HD
14400 bps Half-Duplex Modem
TECHNICAL SPECIFICATIONS
EQUALIZERS
TRANSMITTER TONAL SIGNALING AND CARRIER
FREQUENCIES
.
The R144HD provides the following equalization functions which
can be used to improve performance when operating over poor
lines:
T.30 Tonal Signaling Frequencies
Frequency
(Hz ±D.Ol%)
Function
1100
2100
1850
2100
1650
1100
1100
462
1080
462
Calling Tone (CNG)
Answer Tone (CEO)
Group 2 Identification (GI2)
Group 2 Command (GC2)
Group 2 Confirmation (CFR2, MCF2)
Line Conditioning Signal (LCS)
End of Message (EOM)
Procedure Interrupt (PIS)
MFl Confirmation (CFR)
MFl Procedure Interrupt (PIS)
Cable Equalizers - Selectable compromise cable equalizers
are provided to optimize performance over different lengths of
non-loaded cable of 0.4 mm diameter.
Link Amplitude Equalizer - The selectable compromise
amplitude equalizer may be inserted into the transmit and/or
receive paths under control of the transmit amplitude equalizer
enable and the receive amplitude equalizer enable bits in the
interface memory. The amplitude select bit controls which of two
amplitude equalizers is selected.
Automatic Adaptive Equalizer - An automatic adaptive equalizer is provided in the receiver circuit for high speed data
configurations.
Carrier Frequencies
Frequency
(Hz :1:0.01%)
Function
T.3 (Group 2)
V.27 ter, V.33, TCM96, TCM72
V.29, (V.33, TCM96, TCM721'
2100
1800
1700
1. Selectable option
TONE GENERATION
Under control of the host processor, the RI44HD can generate
voice band tones up to 4800 Hz with a resolution of 0.15 Hz and
an accuracy of 0.01 %. Tones over 3000 Hz are attenuated.
TRANSMITTED DATA SPECTRUM
If neither the link amplitude nor cable equalizer is enabled, the
transmitter spectrum is shaped by the following raised cosine
filter fu nctions:
1. 1200 Baud. Square root of 90 percent.
2. 1600 Baud. Square root of 50 percent.
3. 2400 Baud. Square root of 20 percent.
The out-of-band transmitter power limitations meet those specified by Part 68 of the FCC's Rules, and typically exceed the
requirements of foreign telephone regulatory bodies.
SCRAMBLERIDESCRAMBLER
The R144HD incorporates a self-synchronizing scrambler/
descrambler. This facility is in accordance with either V.27 ter,
V.29, or V.33 depending on the selected configuration.
TONE DETECTION
In the 300 bps FSK receive configuration, the presence of tones
at preset frequencies is indicated by bits in the interface memory.
SIGNALING AND DATA RATES
Signaling/Data Rates
Data Rate
Specification
Baud Rate
(Symbols/Sec.)
Bits Per
Baud
(BPS)
(:1:0.01%)
Symbol
Points
V.33
V.33
TCM96
TCM72
V.29
V.29
V.29
V.27
V.27
2400
2400
2400
2400
2400
2400
2400
1600
1200
6
5
4
3
4
3
2
3
2
14400
12000
9600
7200
9600
7200
4800
4800
2400
128
64
32
16
16
8
4
8
4
DATA ENCODING
The R144HD data encoding conforms to CCIIT recommendations V.33, V.29, and V.27 ter.
RECEIVED SIGNAL FREQUENCY TOLERANCE
The receiver circuit of the R144HD can adapt to received frequency error of up to ± 10Hz with less than a 0.2 dB degradation in BER performance. Group 2 carrier recovery capture range
is 2100 ± 30 Hz. The Group 2 receiver operates properly when
the carrier is varied by :I: 16 Hz at a 0.1 Hz per second rate.
RECEIVE LEVEL
The receiver circuit of the R144HD satisfies all specified performance requirements for received line signal levels from - 0 dBm
to - 43 dBm. The received line signal level is measured at the
receiver analog input (RXA).
RECEIVE TIMING
In the receive state, the R144HD provides a Data Clock (DCLK)
output in the form of a square wave. The low to high transitions
of this output coincide with the center of received data bits. The
timing recovery circuit is capable of tracking a ± 0.01 % frequency error in the associated transmit timing source. DCLK
duty cycle is 50 ± 3°Al.
3-194
14400 bps Half-Duplex Modem
R144HD
TRANSMIT LEVEL
2. Received Line Signal Detector (RLSD). RLSD is clamped off
(squelched) during the time when RTS is on.
3. Extended Squelch. Optionally, RLSD remains clamped off for
130 ms aiter the turn-off sequence.
The transmitter output level defaults to + 5 dBm ± 1 dB at power
on. When using the default transmit level and driving a 600 ohm
load, the TXA output requires a 600 ohm series resistor to
provide - 1 dBm ± 1 dB to the load. The output level can be
programmed from -1 dBm to -10 dBm by performing a RAM
write operation.
RESPONSE TIMES OF CLEAR·TO-SEND (CTS)
The time between the off-to-on transition of RTS and the off-toon transition of CTS is dictated by the length of the training
sequence. Response time is 1393 ms for V.33 and TCM96,
253 ms for V.29, 708 ms for V.27 ter at 4800 bps, and 943 ms
for V.27 ter at 2400 bps. In V.21 CTS turns on in 14 ms or less.
In Group 2 CTS turns on in 400 "s or less.
TRANSMIT TIMING
In the transmit state, the R144HD provides a Data Clock (DCLI<)
output with the following characteristics:
1. Frequency. Selected data rate of 14400, 12000,9600,7200,
4800,2400, or 300 Hz (±0.01%). In Group 2, DCLK tracks
an external 10368 Hz clock. If the external clock input (XCLI<)
is grounded the Group 2 DCLK is 10372.7 Hz ±0.01%.
2. Duty Cycle. 50 ± 3%
The time between the on-to-off transition of RTS and the on-tooff transition of CTS in the data state is a maximum of 2 baud
times for all configurations.
Transmit Data (TXD) must be stable during the 1 microsecond
periods immediately preceding and following the rising edge of
DCLK.
RECEIVED LINE SIGNAL DETECTOR (RLSD)
For V.33, tCM96, V.29 or V.27 ter, RLSD turns on at the end of
the training sequence. If training is not detected at the receiver,
RLSD will not turn on.
TURN·ON SEQUENCE
The selectable turn-on sequences of the R144HD are defined
in the following table:
The RLSD on-to-off response time ensures that all valid data
bits have appeared on RXD. The threshold levels are:
Turn-On Sequences
Greater than -43 dBm (RLSD on)
Less than - 48 dBm (RLSD off)
RTS-CTS Turn-On Time
Specification
V.33
V.33 Short
TCM96
TCM96 Short
TCM72
TCM72 Short
V.29
V.27 4800 bps
V.27 2400 bps
V.27 4800 Short
V.27 2400 Short
Echo Protector
Tone Disabled
1393
142.5
1393
142.5
1393
142.5
253
708
943
50
67
V.21 300 bps
Group 2
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
:514 ms
:5400,,5
Echo Protector
Tone Enabled
1598
347.5
1598
347.5
1598
347.5
438
913
1148
255
272
NOTE
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
A minimum hysteresis action of 2 dB exists between the actual
off-to-on and on-to-off transition levels. The threshold levels and
hysteresis action are measured with an unmodulated 2100 Hz
tone applied to the receiver's audio input (RXA).
:514 ms
:5400,,5
The R144HD is capable of being operated in either a serial or
a parallel mode of operation.
Performance may be at a reduced level when the received
signal is less than -43 dBm.
MODES OF OPERATION
SERIAL MODE
TURN-OFF SEQUENCE
The serial mode uses standard V.24 (RS-232-C compatible) signals to transfer channel data. An optional USRT device (shown
in the R144HD Functional Interconnect Diagram) illustrates this
capability.
For V.27 ter, the turn-off sequence consists of approximately
12 ms of remaining data and scrambled ones at 1200 baud or
approximately 10 ms of data and scrambled ones at 1600 baud
followed by a 20 ms period of no transmitted energy. For V.33,
TCM96, TCM72, and V.29, the turn-off sequence consists of
approximately 8 ms of remaining data and scrambled 1's followed by a 20 ms period of no transmitted energy. In V.21 the
transmitter turns off within 7 ms aiter RTS goes false. In
Group 2 the transmitter turns off within 200 "seconds aiter RTS
goes false.
PARALLEL MODE
The R144HD has the capability of transferring channel data
eight bits at a time via the microprocessor bus.
MODE SELECTION
Selection of either the serial or parallel mode of operation is by
means of a control bit. To enable the parallel mode, the control
bit must be set to a 1. The modem automatically defaults to the
serial mode at power-on. In either mode the R144HD is configured by the host processor via the microprocessor bus.
CLAMPING
The following clamps are provided with the R144HD:
1. Received Data (RXD). RXD is clamped to a constant mark
(1) whenever RLSD is off.
3-195
•
14400 bps Half-Duplex Modem
R144HD
r-------.,,
CABS2
~
~
~
USRT
(OPTIONAL)
J
j
SCOPE
C'i'i
TXD
EYEX
I
DCLK
EYEY
~
RLSD
,L __ -.
Q
..
",:
::
CAIIS1
RTS
-
RXD
ty
xt
EYE
PATTERN
GENERATOR
EYESYNC
MCLK
i
+12V
+5V
R144HD
MODEM
POWER
SUPPLY
GND
READ
-12V
WRITE
DATA BUS (I)
HOST
PROCESSOR
(DTE)
ADDRESS BUS
....
....
iFiQ
YV
J
UNE
INTERFACE
RBI
RXA
I DECODER ~'.... POR
CS~
+5
TXA
01
(~
TELEPHONE
UNE
CSI
AUXIN
AUXIUARY
CIRCUITS
-~
I
I
R144HD Functional Interconnect Diagram
INTERFACE CRITERIA
R144HD Hardwara Circuits (Continued)
Name
The modem Interface comprises both hardware and software
circuits. Hardware circuits are assigned to specific pins in two
rows of a 4O-pin connector. Software circuits are assigned to
specific bits In a 32-byte Interface memory.
Type
Pin No.
Description
B. MICROPROCESSOR INTERFACE:
07
06
05
D4
03
02
01
DO
HARDWARE CIRCUITS
Signal names and descriptions of the hardware Circuits, including the microprocessor interface, are listed in the R144HD Hardware Circuits table; the table column titled 'Type' refers to
designations found in the Hardware Circuit Characteristics. The
microprocessor Interface is designed to be directly compatible
with an 8080 microprocessor. With the addition of a few external
logic gates, it can be made compatible with 6500, 6800, or 68000
microprocessors.
I/OA
1I0A
1I0A
1I0A
1I0A
1I0A
1I0A
1I0A
j}
15
28
23
29
Oeta Bus (8 Bhs)
RS3
RS2
RSl
RSO
IA
IA
IA
IA
~}
Register Select (4 Bits)
Setect Reg. O-F
CSO
CSl
READ
WRITE
IRQ
IA
IA
IA
IA
OB
8
11
1
2
32
Chip Select Sample Rate Device
Chip Select Baud Rete Device
Read Enabla
Write Enable
Interrupt Request
13
22
19
17
20
21
16
Oeta Clock
Extemal Clock for Group II
R&quest-to-Send
Clear-to-Send
Transmitter Oeta
Receiver Oeta
Received Line Signal Detector
10
C. V.24 INTERFACE:
DCLK
XCLK
RTS
CTS
TXO
RXO
RLSO
R144HD Hardware Supervlaory CIrCuits
Name
Typa
Pin No.
Description
A. OVERHEAD:
Ground
+5 vohs
+ 12 volts
':'12 volts
POR
GNO
PWR
PWR
PWR
1I0B
14,39
3,4
28
37
36
Power Supply Retum
+ 5 volt supply
+ 12 volt supply
- 12 volt supply
Power-on-reset
OC
IB
IB
OC'
IB
OC
OC
D. CABLE EQUAUZER:
CABSl
CABS2
3-196
IB
IB
33
34
Cable Select 1
Cable Select 2
14400 bps Half-Duplex Modem
R144HD
Critical Timing Requirements
R144HD Hardware Circuits (Continued)
Name
Type
Pin No.
Characteristic
E. ANALOG SIGNALS:
AA
AB
AC
TXA
RXA
AUXIN
38
40
35
Transmitter Analog Output
Receiver Analog Input
Auxiliary Analog Input
F. DIAGNOSTIC:
EYEX
EYEY
EYECLK
EYESYNC
OC
OC
OA
OA
24
25
11
12
Symbol
Min
CSi, RSi setu~e prior
to Read or Write
TCS
Data Access time after Read
TDA
Data hold time after Read
TDH
Description
Eye Pattern
Eye Pattern
Eye Pattern
Eye Pattern
Signal
CSi, RSi hold time after
Read or Write
Data - X Axis
Data - Y Axis
Clock
Synchronizing
Units
30
-
NS
-
140
NS
10
50
NS
-
NS
TCH
10
Write data setup time
TWOS
75
Write data hold time
TWDH
10
TWR
75
Write strobe pulse width
Note: Unused inputs tied to + 5V or ground require individual
10K 0 series resistors.
Max
NS
NS
NS
Cable Equalizer Selection
Cable Equalizer Selection
Eye Pattern Generation
The four hardware diagnostic circuits, identified in the preceding table, allow the user to generate and display an eye pattern.
Circuits EYEX and EYEY serially present eye pattern data for
the horizontal and vertical display inputs respectively. The 8-bit
data words are shifted out most significant bit first, clocked by
the rising edge of the EYECLK output. The EYESYNC output
is provided for word synchronization. The falling edge of EYESYNC may be used to transfer the S-bit word from the shift
register to a holding register. Digital to analog conversion can
then be performed for driving the X and Y inputs of an oscilloscope.
CABS 2
CABS 1
Length of O.4mm Diameter Cable
0
0
1
0
1
0
1
0.0
1.8 km
3.6 km
7.2 km
1
Digital Interface Characteristics
The digital interface characteristics are listed in the table on the
following page.
Analog Interface Characteristics
Analog Interface Characteristics
Type
Characteristics
TXA
AA
The Transmitter Analog output is a low
impedance operational amplifier output. In
order to match to 600 ohms, an external
604 ohm series resistor is required.
RXA
AB
The Receiver Analog input Impedance is
46.4K ohms ± 23% or 23.2K ohms ± 23%
for dynamic range of -43 dBm to 0 dBm
or - 43 dBm to - 6 dBm, respectively.
AUXIN
AC
The Auxiliary Analog input allows access to
the transmitter by user-provided eqUipment.
Because this signal is a sampled data
input, any signal above 4800 Hz Will cause
aliesing errors. The input impedance is
1K ohms, and the gain to transmitter
output is - 0.4 dB ± 1 dB. If not used,
this input should be grounded.
Name
Microprocessor Timing
SOFTWARE CIRCUITS
(i
The R144HD comprises three signal processor chips. Two of
these chips contain 16 registers to which an external (host) microprocessor has access. Although these registers are within the
modem, they may be addressed as part of the host processor's
memory space. The host may read data out of or write data into
these registers. The registers are referred to as interface memory.
Register in chip 0 update at the modem sample' rate (9600 bps).
Registers in chip 1 update at the selected baud rate.
= U-7j_ _ _(]
When information in these registers is being discussed, the format Y:Z:O is used. The chip is specified by Y(O or 1), the register
by Z(O-F), and the bit by 0(0-7, 0 = LSB). A bit is considered
to be "on" when set to a 1.
Microprocessor Interface Timing Diagram
3-197
•
R144HD '
14400 bps Half-Duplex Modem
Digital Interface Characteristics
Input/Output 1\tpe
Symbol
Parameter
VIH
Input Voltage, High
VIL
VOH
VOL
liN
10H
10L
IL
Ipu
Input Voltage, Low
Output Voltage, High
Output Voltage, Low
Input Current, Leakage
Output Current, High
Output Current, Low
Output Current, Leakage
Pull-up Current
(Short Circuit)
Capacitive Load
Capacitive Drive
Circuit Type
CL
Co
Notes
1. I load
-100 pA
2. I load
1.6 rnA
3. I load
-40 pA
4. VIN
0.4 to 2.4 Vdc, Vee
=
=
=
=
Units
IA
18
V
2.0 min.
2.0 min.
0.8 max ..
0.8 max.
V
V
V
pA
rnA
rnA
pA
pA
pF
pF
OA
2.4min.1
0.4 max. 2
08
OC
0.4 max.2
0.4 max.2
1.6 max.
±10 max.
1.6 max.
±2.5 max.
-0.1 max.
1.6 max.
5
TTL
5. I load
-240 max.
-10 min.
5
TTL
w/Pull-up
I/O A
I/O 8
2.0 min.
5.25 max.
2.0 min.
0.8 max.
2.4 min.3
0.4 max. S
0.8 max.
2.4 min. 1
0.4 max. 2
±12.5 max.4
-240 max.
-10 min.
100
TTL
100
Open-Drain
100
Open Drain
w/Pull-up
10
100
3 State
Transceiver
-260 max.
-100 min.
40
100
Open-Drain
w/Pull-up
= 0.36 rnA
= 5.25 Vdc
Status/Control Bits
These bits are written into interface memory registers 0:3, 0:2,
0:1 and 0:0, or 1:3, 1:2, 1:1 and 1:0, in that order. Registers 3 and
2 contain the most and least significant bytes of XRAM data,
respectively, while registers 1 and 0 contain the most and least
significant bytes of YRAM data respectively.
The operation of the R144HD is affected by a number of software control inputs. These inputs are written into registers within
the interface memory via the host microprocessor bus. Modem
operation is monitored by various software flags that are read
from interface memory via the host microprocessor bus. All status
and control bits are defined in the Interface Memory table. Bits
designated by a ' - ' are reserved for modem use only and must
not be changed by the host.
When set to a one, bit 0:5:5 (RAMWS) or bit 1:0:0 (RAMWB)
causes the modem to suspend transfer of RAM data to the interface memory, and instead, to transfer data from interface memory
to RAM in chip 0 or in chip 1, respectively. When writing into
the RAM, only 16 bits are transferred, not 32 bits as for a read
operation. The 16 bits written in XRAM or YRAM come from
registers 1 and 0, with register 1 being the most significant byte.
Selection of XRAM or YRAM for the destination is by means of
the code stored in the RAM Access B bits of register 1:F for
chip 1, or by means of 0:5:4 (RAE) for chip O. When bit 1:F:7 or
0:5:4 is set to one, the XRAM is selected. When 1:F:7 or 0:5:4
equals zero, YRAM is selected.
NOTE: The host must wait a minimum of 1 ,.s between successive writes to interface memory.
RAM Data Access
The R144HD provides the user with access to much of the data
stored in the modem's memories. This data is a useful tool in
performing certain diagnostic functions.
The modem contains 128 words of random access memory
(RAM). Each word is 32-bits wide. Because the modem is
optimized for performing complex arithmetic, the RAM words are
frequently used for storing complex numbers. Therefore, each
word is organized into a real part (16 bits) and an imaginary part
(16-bits) that can be accessed independently. The portion of the
word that normally holds the real value is referred to as XRAM.
The portion that normally holds the imaginary value is referred
to as YRAM. The entire contents of XRAM and YRAM may be
read by the host processor via the microprocessor interface.
When the host reads or writes register 0, the modem resets the
modem data available bit, O:E:O or 1:E:0 (MDAi), to a zero. When
the modem reads or writes register 0, the modem sets the MDAi
bit to a one. If an Interrupt Enable bit, 0:E:2 or 1:E:2 (lEi), is set
to a one by the host and the corresponding MDAi bit is set, the
IRQ output is asserted and the associated Interrupt Active bit,
1:E:7 or 0:E:7 (IAi), is set to a one by the modem.
NOTE: When writing to registers 1 and 0, the host must first write
to register 1, then to register O.
The interface memory acts as an intermediary during these host
to signal processor RAM data exchanges. The RAM address to
be read from or written to is determined by the contents of register
O:F (RAM ACCESS S) or 1:F (RAM ACCESS B). The R144HD
RAM Access Codes table lists access codes for storage in
registers O:F or 1:F and the corresponding diagnostic functions.
The R144HD Diagnostic Data Scaling table provides scaling
information for these diagnostic functions. Each RAM word transferred to the interface memory is 32 bits long.
The default access codes are 28 for 1:F and 00 for O:F, which
allows data in registers 1:3 and 1:1 to be presented serially on
EYEX and· EYEY, respectively.
RAM Access Codes
The RAM access codes defined in the following table allow the
host processor to read diagnostic information within the modem.
3-198
R144HD
14400 bps Half-Duplex Modem
RAM Access Codes
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Ram Access Codes (Continued)
Read
Access RAE Chip Reg. No.
Function
Received Signal Samples
Demodulator Output
Low Pass Filter Output
Average Power
AGC Gain Word
Tone 1 Frequency
Tone 1 Level
Tone 2 Frequency
Tone 2 Level
Output Level
Checksum, Chip 0
Checksum, Chip 1
Equalizer Input
Equalizer Tap Coefficients
Un rotated Equalizer Output
40
52
54
5C
3E
71
72
X
X
X
X
X
1
1
0
71
72
7F
3F
7F
40
02·27
74
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
X
Rotated Equalizer Output
(Received Point-Eye Pattern)
17 DeCISion Points (Ideal)
18 Error Vector
19 Rotation Angle
20 Frequency Correction
21 EOM
22 G2 Base Band Signal
23 G2 AGC Gain Word
24 G2 AGC Slew Rate
25 G2 PLL Frequency Correction
26 G2 PLL Slew Rate
27 G2 BlacklWhite Threshold
28 G2 Phase limit
16
2,3
0,1,2,3
0,1,2,3
2,3
2,3
2,3
2,3
0,1
0,1
0,1
6,1
0,1
0,1,2,3
0,1,2,3
0,1,2,3
RAE
=
i~
F
PDM
E
lAO
-
D
-
8
-
-
7
-
-
-
-
-
-
6
5
4
2
3
B
A
9
6
1
I~
7
6
5
MDAO
E
IAI
-
-
-
-
D
-
TLE
RLE
J3L
-
0
0,1,2,3
0,1,2,3
0,1,2,3
0,1
2,3
2,3
2,3
2,3
2,3
2,3
2,3
0,1
2,3
AA
C2
EF
6A
Fl
4
2
3
-
-
-
-
SETUP
lEO
F
-
-
-
-
EPT
SOEXT
-
-
C
-
-
-
B
FR3
FR2
FRI
A
-
-
-
9
-
8
-
7
-
PNDET
6
-
FED
5
V33S
-
-
-
-
-
lEI
-
-
-
P2DET
4
CONFIGURATION
4
RAM DATA XSM; FREOM
RAM DATAXBM
2
RAM DATA XSL; FREOL
3
2
1
RAM DATA YSM
1
RAM DATA YBM
0
RAM DATA YSL; TRANSCEIVER DATA
0
RAM DATA YBL
7
6
5
4
3
2
1
-
MDAI
7
6
5
4
Bit
-
Reserved (modem use only).
3·199
FAT RAMWB
-
G2FGC
-
-
1
0
-
CDET
RAM DATA XBL
Va:
0
Bit
- =
0
RAM ACCESS B
3
7::
1
Register
RAM ACCESS S
RTS TOIS RAMW- RAE
5
1
1
1
1
1
1
1
1
1
1
1
1
1
R144HD Interface Memory Chip 1 (CS1)
Register
C
28
68
69
00
AE
Bl
C8
AD
X is don't care since this location should only be read
from, and not written to, by the host .
R144HD Interface Memory Chip 0 (CSO)
7
Read
Access RAE Chip Reg. No.
Function
No.
= Reserved (modem use only).
3
2
•
14400 bps Half-Duplex Modem
R144HD
R144HD Interface Memory Definitions
Mnemonic
Name
Memory
Location
Description
COET
Carrier Detector
1:7:0
The zero state of COET indicates passband energy is being detected, and a training sequence is
not present. COET goes to zero at the end of a training sequence, and returns to one at the end
of the received signal. COET will not go to zero if the training sequence is not detected. COET
activates up to 1 baud time before RLSO and deactivates within 2 baud times after RLSO.
(None)
Configuration
0:4:0-7
The host processor configures the R144HO by writing a control code into the configuration
register in the interface memory space. (See SETUP)
Configuration Control Codes
Control codes for the R144HO configurations are:
Configuration
V.33 14400'
V.33 12000
TCM969600
TCM727200
V.33 14400 (1700 Hz)2
V.33 12000 (1700 Hz)2
TCM96 9600 (1700 Hz)2
TCM72 7200 (1700 Hz)2
V.29 9600
V.29 7200
V.29 4800
V.27 4800 Long
V.27 2400 Long
V.27 4800 Short
V.27 2400 Short
FSK
Group 2
Single Tone Transmit
Dual Tone
Configuration Code (HEX)
31
32
34
38
71
72
74
78
14
12
11
OA
09
8A
89
20
40
80
81
, Default at POR.
2 The 1700 Hz carrier frequency is non-standard.
Configuration Definitions
1. V.33. When a V.33 configuration has been selected, the modem operates as specified in
CCITT Recommendation V.33.
2. TCM96 and TCM72. When configuration TCM96 or TCM72 is selected, the training sequence
is defined by V.33 and the modulation trellis coded is defined by V.32 (32 or 16 point
constellation).
3. V.29. When a V.29 cOlifiguration has been selected, the modem operates as specified in CCITT
Recommendation V.29.
4. V.27. When a V.27 configuration has been selected, the modem operates as specified in CCITT
Recommendation V.27 ter.
5. FSK. The modem operates as a CCITT T.30 compatible 300 bps FSK modem having
characteristics of the CCITT V.21 channel 2 modulation system.
6. Group 2. The modem operates as a CCITT T.3 compatible AM modem: This permits transmission to and reception from Group 2 facsimile apparatus. A carrier frequency of 2100 Hz is
used. A black signal is transmitted as no carrier. The phase of the carrier representing white is
reversed after each transition through black.
When in the receive state, the R144HO recovers the carrier of the remote transmitting modem
to perform a coherent demodulation of the incoming signal. This allows a baseband of 3400 Hz
to be recovered. The recovered baseband Signal is available on the microprocessor bus.
The baseband signal is converted to black or white by comparing the received signal level with
a preset threshold number. This number may be changed by the user.
3-200
R144HD
14400 bps Half-Duplex Modem
R144HD Interface Memory Definitions (Continued)
Mnemonic
Name
Memory
Location
Description
Receiver data is presented to the RXD output at a rate of 10368 samples per second. The user
should strobe the data on the riSing edge of the data clock (DCll<). A logical 1 level (high
voltage) represents white. A logical 0 level (lOW voltage) represents black.
7. Single Tone Transmit. In this configuration, activating signal RTS causes the modem to transmit
a tone at a Single frequency specified by the user. Two registers in the host interface memory
space contain the frequency code. The most significant bits are specified in the FREOM
register (0:3). The least significant bits are specified in the FREQl register (0:2). The least
Significant bit represents 0.146486 Hz ± 0.01%. The frequency generated is: f = 0.146486
(256 FREOM + FREOl) Hz ±0.01%.
8 Dual Tone Transmit. In this configuration, activating RTS causes the modem to transmit two
tones at frequencies and output levels specified by the user. By using the RAM Data Access
routines, the user can program the tones and levels.
EPT
Echo Protector
Tone
0:5:3
If EPT is a one, an unmodulated carrier is transmitted for 185 ms followed by 20 ms of no
transmitted energy at the beginning of the training sequence. This option is available in V.33,
V.29, and V.27 configurations, although it is not specified in the CCITT V.33 or V.29
recommendations.
FED
Fast Energy
Detector
1'5:6
The zero state of FED indicates energy is present above the receiver threshold in the passband.
FED is not used for Group 2 Facsimile.
(None)
FREOUFREOM
0:2:0-7,
0:3:0-7
The host processor conveys single tone generation data to the transmitter by writing a 16-bit data
word to the FREOl and FREOM registers in the interface memory space, as shown below.
FREOM Register (0:3)
IBIt:
I
IData Word: I
7
2 '5
I
I
6
2'4
I
I
5
213
I
I
I
6
26
I
I
5
25
I
i
I
4
2'2
I
I
2"
I
2'0
4
24
I
I
3
23
I
I
2
22
3
I
2
I
I
1
29
I
I
0
28
I
I
I
1
I
I
0
2'
2D
I
I
I
FREOL Register (0:2)
IBit:
I
IData Word: I
7
27
The frequency number (N) determines the frequency (F) as follows:
F = (0146486) (N) Hz ±0.01%.
Hexadecimal frequency numbers (FREOM, FREOl) for commonly generated tones are given below:
Frequency (Hz)
462
1100
1650
1850
2100
FREQM
FREQL
OC
10
2C
31
38
52
55
00
55
00
FRT
Freeze Taps
1'0'1
When FRT IS a one, adaptive equalization taps are prevented from changing while in data mode.
FR1-FR3
Frequency 1,2,3
1'B'5,6,7
The one state of FR1, FR2 or FR3 indicates reception of the respective tonal frequency when the
modem IS configured for FSK. The default frequencies for FR1, FR2 and FR3 are:
Bit
FR1
FR2
FR3
Frequency (Hz)
2100
1100
462
G2FGC
Group 2 Fast
Gain Control
1:C:0
The one state of G2FGC selects a fast AGC rate (8.6 times standard) in Group 2 Facsimile.
IA1
Interrupt Active
(One)
1:E:7
IA1 is a one when Chip 1 is driVing IRQ to zero volts.
lAO
Interrupt Active
(Zero)
0·E.7
lAO is a one when Chip 0 is driving IRO to zero volts.
3-201
•
R144HD
14400 bps Half.Duplex Modem
R144HD Interface Memory Definitions (Continued)
Mnemonic
Name
Memory
Location
Description
lEO
Interrupt Enable
(Zero)
0:E:2
The one state of lEO causes the IRQ output to be low when the MDAO bit is a one.
lEI
Interrupt Enable
(One)
I:E:2
The one state of lEt causes the IRQ output to be low when the MDAt bit is a one.
J3L
Japanese 3 Link
I:D:4
The one state of J3L selects this standard for link amplitude equalizer. The zero state of J3L
selects U.S. survey long.
MDAO
Modem Data
Available (Zero)
O:E:O
MDAO goes to one when the modem reads or writes register 0:0. MDAO goes to zero when the
host processor reads or writes register 0:0. MDAO is used for parallel mode as well as for diagnostic data retrieval.
MDAI
Modem Data
Available (One)
I:E:O
MDAI goes to one when the modem writes register 1:0. MDAI goes to zero when the host
processor reads register 1:0.
PDM
Parallel Data
Mode
0:F:7
The one state of PDM places the modem in the parallel mode and inhibits the reading of Chip 0
diagnostic data.
PNDET
Period 'N'
Detector
1:7:6
The zero state of PNDET indicates a PN sequence has been detected. PNDET sets to a one at the
end of the PN sequence, except for V.33, TCM96 and TCM72. PNDET sets to a one at the end of
the rate sequence (PR) in these modes.
P2DET
Period '2'
Detector
1:4:2
The zero state of P2DET indicates a P2 sequence has been detected. P2DET sets to a one at the
start of the PN sequence.
(None)
RAM Access B
I:F:0-7
Contains the RAM access code used in reading or writing RAM locations in Chip I (baud rate
device).
(None)
RAM Access S
0:F:0-6
Contains the RAM access code used in reading RAM locations in Chip 0 (sample rate device).
(None)
RAM Data XBL
1:2:0-7
Least significant byte of 16-bit word x used in reading RAM locations in Chip I (baud rate device).
(None)
RAM Data XBM
1:3:0-7
Most significant byte of 16-bit word x used in reading RAM locations in Chip 1 (baud rate device).
(None)
RAM Data XSL
0:2:0-7
Least significant byte of 16-bit word x used in reading RAM locations in Chip 0 (sample rate
device).
(None)
RAM Data XSM
0:3:0-7
Most significant byte of 16-bit word x used in reading RAM locations in Chip 0 (sample rate
device).
(None)
RAM Data YBL
1:0:0-7
Least significant byte of 16-bit word y used in reading or writing RAM locations in Chip I (baud
rate device). See MDAt.
(None)
RAM Data YBM
1:1:0-7
Most significant byte of 16-bit word y used in reading or writing RAM locations in Chip I (baud
rate device).
(None)
RAM Data YSL
0:0:0-7
Least significant byte of 16-bit word y used in reading RAM locations in Chip 0 (sample rate
device). Shared by parallel data mode for presenting channel data to the host microprocessor
bus. See Transceiver Data and MDAO.
(None)
RAM Data YSM
0:1:0-7
Most significant byte of 16-bit word y used in reading RAM locations in Chip 0 (sample rate
device).
RAE
RAM Address
Extension
0:5:4
This bit is an extension of RAM Access S when RAMWS is a one. When RAE is a one, the
XRAM in Chip 0 is selected for a RAM write operate, and when a zero the YRAM is selected.
RAMWB
RAM Write Chip 1
(baud rate
device)
I:D:O
RAMWB is set to a one by the host processor when performing diagnostic writes to the baud rate
device (Chip I). RAMWB is set to a zero by the host when reading RAM diagnostic data from
Chip I.
RAMWS
RAM Write Chip 0
(sample rate
device)
0:5:5
RAMWS is set to a one by the host processor when performing diagnostic writes to the sample
rate device (Chip 0). RAMWS is set to a zero by the host when reading RAM diagnostic data from
Chip O.
RLE
Receiver Link
Equalizer
I:D:5
The one state of RLE enables the link amplitude equalizer in the receiver.
RTS
Request-to-Send
0:5:7
The one state of RTS begins a transmit sequence. The modem will continue to transmit until RTS
is turned off, and the turn-off sequence has been completed. RTS parallels the operation of the
hardware RTS control input. These inputs are "ORed" by the modem.
3-202
R144HD
14400 bps Half-Duplex Modem
R144HD Interface Memory Definitions (Continued)
Mnemonic
SETUP
Name
Setup
Memory
location
0:E:3
Description
The one state of SETUP causes the modem to reconfigure to the control word in the configuratio'n
register, and to assume the options specified for the equalizer (0:5:1). SETUP returns to zero
when acted on by the modem. The time required for the SETUP bit to cause a change depends
on the current state of the modem. The following table lists worst case delays.
Current
State
V.21
G11
High Speed
Receiver
DELAY
14 ms
400 I'S
2 BAUD
High Speed 111msmltter
2 BAUD + TURNOFF Sequence + Training (If
applicable) + SQUELCH (if applicable)
SQEXT
Squelch Extend
0:5:2
The one state of SQEXT inhibits reception of signals for 130 ms after the turn-off sequence.
TOIS
Training Disable
0:5:6
If TDIS is a one in the receive state, the modem is prevented from entering the training phase. If
TDIS is a one prior to RTS going on, the generation of a training sequence is prevented at the
start of transmIssion.
TLE
Transmitter Link
Equalizer
1:0:6
The one state of TLE enables the link amplitude equalizer in the transmitter.
V33S
V.33 Short Train
0:5:0
Setting this bit allows the modem to retrain in 142.5 ms if the modem has previously trained in
the V.33, TCM96, or TCM72 long train configurations. This bit must be reset before changing
configurations, unless the new configuration is V.33, TCM96, TCM72 or FSK.
Once the modem has long trained in V.33, TCM96 or TCM72, it can short train in any of these
configurations. Short train is also possible if the modem long trains, reconfigures 10 FSK with the
short train bit set, and then reconfigures again to V.33, TCM96, or TCM72.
(None)
Transceiver Data
0:0:0-7
In receive parallel data mode, the modem presents eight bits of channel data in register 0:0 for
reading by the host microprocessor. After the eight bits have been accumulated in register O:C
they are transferred to 0:0 and bit O:E:O goes to a one. When the host reads 0:0, bit O:E:O resets
to a zero. The first bit of received data is not necessarily located In bit 0:0:0. The host must frame
the received data by searching for message sync characters. Bit O:E:O sets at one eIghth the bit
rate in parallel data mode rather than at the sample rate (9600 Hz) as it does when reading RAM
locations.
In transmit parallel data mode the host stores data at location 0:0. This action causes bit O:E:O
(MDAO) to reset to a O. When the modem transfers the data from 0:0 to 0:2 bit O:E:O sets to a 1.
The data is serially transmitted from register 0:2 least Significant bit first. Received data is shifted
into register O:C from MSB toward LSB.
POWER-ON INITIALIZATION
When power is applied to the modem, a period of 50 to 350 ms
is required for power supply settling. The power-on-reset Signal
(POR) remains low during this period. Approximately 10 ms after
the low to high transition of POR, the modem is ready to be
configured, and RTS may be activated. If the 5 Vdc power supply
drops below 3.5 Vdc for more than 30 msec, the POR cycle is
repeated.
At POR time the modem defaults to the following configuration: V.33114400 bps, serial mode, training enabled, no echo protector tone on, no extended squelch, interrupts disabled, no link
equalizer, RAM Access B code 28.
POR can be connected to a user supplied power-on-reset signal
in a wire-or co~ration. A low active pulse of 3 !,sec or longer
applied to the POR pin causes the modem to reset. The modem
is ready to be c~ured 10 msec after the low active pulse is
removed from POR.
3-203
II
R144HD
14400 bps Half-Duplex Modem
PERFORMANCE
The Bit Error Rate (BER) performance of the modem is specified
for a test configuration conforming to that specified in CCITT
Recommendation V.56. Bit error rates are measured at a
received line signal level of - 20 dBm, except for TCM72; V.29,
FSK
4800; and V.27, which are measured at a received line signal
level of - 30 dBm.
The BER curves shown below were prepared from data obtained .
using a TAS 1000 communication test system.
V27 4800 TCM96
, V29, 7200 ,/ V.33, 12000
V29,9600 V.33,14400
10- 4 ~---t-t----~1-~~~~~~~----+-+-------4
w
~
II:
~
II:
w
t-
iii
10- 5 ~-----t------H---4-~~-1~~~--~~----~
5
lS
10
Signal 10 Noise Ralio in dB
20
Typical Bil Error Rale
(Back-Io-Back)
3-204
25
30
14400 bps Half-Duplex Modem
R144HD
GENERAL SPECIFICATIONS
Power
Voltage
Tolerance
Current (Typical) @ 25°C
Current (Max) @ O°C
+5 Vdc
+12 Vdc
-12 Vdc
±5%
±5%
±5%
750 mA
5 mA
30 mA
800 mA
10 mA
50 mA
Note: All voltages must have ripple ,,0.1 volts peak-to-peak.
Environmental
Parameter
Specification
Temperature
Operating
Storage
O°C to + 70°C (32°F to 158°F)
- 40°C to + 80°C (- 40°F to 176°F) (Stored in heat sealed antistatic bag and shipping
container)
Up to 90% noncondensing, or a wet bulb temperature up to 35°C, whichever is less.
Relative Humidity
Mechanical
Parameter
Specification
Board Structure
Single PC board with single right angle header with 40 pins. Hirose HIF3F-40PA-2 50S
(male) or HIF3HA-400A-2.540SA (female), or eqUivalent mating connector.
Dimensions
Width
Length
Component Height (max)
Connector Height
Weight (max)
3.937 m. (100 mm)
3.228 m. (82 mm)
0.300 in. (7.62 mm) above, 0.130 in. (3.3 mm) below
0.400 in. (10.16 mm)
3.6 oz. (100 g)
0.156 ± 0_003 (5 PL)
(3.96)
0.675
(17.15)
i
0.637
(16.18)
I
r--I
3.937
(100)
~~
0.512
(13)
J(931·3)~===±_!~~
2.30
3675
(58.4)
"NOTE: MALE CONNECTOR
PIN NUMBERS SHOWN
:!: ..
____ ,
~
~~
(25.4)
:
------It 0.12~ ~3~~~
2.300
(58_4) 3.228
1 - - - - - - (82)
0.300 MAX
(3.18)
UNITS: INCHES
mm
COMPONENT
AREA
~2)
----L
Tt'-------/--------0
1;_0~2
0~130 J L
/
- -
(1.6)
- -
-
(3.3)
0.400 MAX
(10.16)
R144HD Dimensions and Pin Locations
3-205
•
3-206
SECTION 4
Data Modem Application Notes
An R6500/11-R2424 Intelligent Modem Design ........................................ 4-3
Interfacing Rockwell Signal Processor-Based Modems to an Apple lie Computer . . . . . . . . . . .. 4-46
2400/1200/300 bps International Modem Design ..................................... 4-50
Quality of Received Data for Signal Processor-Based Modems ......... . . . . . . . . . . . . . . . .. 4-83
R2424 and R1212 Modems Auto Dial and Tone Detection ............................. 4-104
8088 Microprocessorto R12121R2424 Modem Interface .............................. 4-114
RC2424DP/DS Diagnostic Data Scaling ...........................................
RC2424DP/DS HDLe Features ..................................................
Data Access Arrangement (DAA) Design for the R1496MM, R9696DP, and R144DP . . . . . . ..
R1496DP, R9696DP, and R144DP Programmer's Guide .............................
4-119
4-130
4-135
4-148
R9696DP "AT" Command Set Capabilities ......................................... 4-161
II
4-1
DIGITAL NETWORKS
T-1/ISDN SOLUTIONS
Rockwell's expanding line of digital network products provide a solid foundation for integrating voice and
data. These products are the system building blocks for central office, customer premises and local area
networks equipment. Applications for Rockwell's digital devices include channel banks, multiplexers,
PBX, host computers, front-end processors and LANS gateways/bridges.
Rockwell offers systems designers of OEM equipment a total solution for the Physical and lower half of
the Unk Layer of the ISO/lSDN model. This "plug-in" solution allows OEM manufacturers the opportunity
and the affordability to be in the T-1/ISDN market. In addition, these devices offer a high level of integration to help designers build a T-1 interface rapidly with considerable space and component savings,
coupled with higher performance design and throughput.
The ROO69 Une Interface Unit (LlU) features programmable line equalization, clock recovery for slave
operation and meets AT&T Pub. 62411 specifications. The R8070 T-1/PCM-30 Transceiver offers TX and
AX functions in a single chip and meets CEPT PCM-30, T-1 04 and ESF formats with or without clear
channel. In addition, the R8070 has B8ZS and HDB3 on-board. The R8071 supports ISDN and DMI data
modes, ISDN signalling, has on-board buffer memory management and provides 32 full-duplex channels
with HDLC formatting.
Future high speed digital network devices include the R8075 which adds the CRC-4 error checking
capability that is required by CCITI for PCM-30. The RT9170 is an advanced T-1 transceiver with
microprooessor-interfaceand faGility data link capabilities. These devices are a part of Rockwell's ongoing
commitment to digital connectivity and ISDN.
Substantial support is provided to demonstrate the use of these highly integrated devices. Evaluation
boards are available for the R8069, R8070 and R8071. These boards are a platform to show the performance, capabilities and functionality of the devices either singly or together to implement a high speed
digital interface.
Rockwell's series of communication controllers provide fast execution speed and may interface with a
variety of 68000 I/O and memory devices. The R68C560/61 Multi-Protocol Communications Controller
(MPCC) operates up to 4 Mbits/sec and supports all major communications protocols. It is available to
work with either a is-bit or 8-bit bus and can be adapted to function with essentially any of today's more
common busses.
The R68C552 Dual Asynchronous Interface Adapter (DACIA) provides an easily implemented,
programmed controlled interface between 16-bit microprocessor-based systems and serial communications data sets and modems.
The R68OO2 Local Area Network Controller (LNET) is a universal CSMNCD controller which is designed
to support a variety of local network designs. The device can interface data terminal equipment to local
networks with differing performance requirements.
4-2
Application Note
'1'
Rockwell
An R6500/11 - R2424 Intelligent
Modem Design
by Ron Collins and Joseph W. Hance
Product Applications Engineers
Semiconductor Products Division, Newport Beach, California
INTRODUCTION
The PAL * generates the proper bus control signals needed to
interface the R2424DC to the R6500/11 's bus. It also allows the
R6500/11 to switch the serial data between the host and the line
to accommodate the command and on-line modes. The 1488's
(Z4, Z5) and the 1489 (Z6) provide a standard RS-232-C interface for the host computer. These devices would not be
necessary in the design of a plug-in personal computer modem.
Figure 2 shows the logic equivalent of the 16L8 PAL and Figure 3
shows the PALASM equations used to program the PAL.
The combination of single chip microcomputers and standard
modems makes possible the implementation of sophisticated and
flexible telecommunications systems. The intelligent modem has
become the standard for personal microcomputers and provides
access to many outside resources over standard telephone lines.
This application note describes the hardware and software design
of a 30011200/2400 bit-per-second (bps) modem based on the
Rockwell R2424 single board modem and the R6500111 singlechip microcomputer. The system design minimizes the number
of devices used and provides the user adequate room for special
features. The software implements the industry standard "AT"
command set so that compatibility with commercial software
packages is provided. This particular design is that of a standalone "Box Modem" but only minimal changes are needed in
the configuration for a personal computer bus compatible
modem.
SOFTWARE DESIGN
The Functional State diagram for the software is shown in
Figure 4. An assembly listing of the program is included at the
end of this application note. Notes are liberally included in the
listing to assist the understanding of program operation. (Figure 7).
Note: In the discussion of the software and operation of this
design, it is assumed the reader knows and understands the
common "AT" commands. If not, refer to any of a number of
source materials devoted to this subject.
HARDWARE DESIGN
The hardware used in this design (see the schematic in Figure 1)
consists of an R6500/11 microcomputer (Z1), an R2424DC
modem module (Z3), and a 16L8 type PAL (Z2). A complete parts
list is tabulated in Table 1.
There are five main sections to this program. In order of occurrance in the listing, they are:
Part
Part
Part
Part
Part
The R6500/11 controls the system and implements the high level
command protocol. It has an internal UARTwhich provides communications between the host computer and the modem. The
R2424DC module is addressed as a peripheral on the abbreviated bus of the R6500111. All modem configuration, dial, status,
and commands are transmitted over the data bus. The serial
interface to the R2424DC carries only the data transmitted or
received over the telephone line.
Table 1.
Part
Qly
Description
1
2
3
4
5
6
7
8
9
10
11
Pl
Rl
R2
R3
Yl
Zl
Z2
Z3
Z4
Z5
Z6
1
1
1
1
1
1
1
1
1
1
1
R8-232C Connector, Female, DB-25
4.7K Resistor, 5%
3K Resistor, 5%
3K Resistor, 5%
1.8432 MHz Crystal
R6500/11 Single-chip Microcomputer
PAL 16L8
R2424DC Modem Board
MC1488
MC1488
MCl489
Baud rate and protocol determination ($F800-$F998)
Reading in the command string
($F999-$F9E8)
Processing the command string
($F9E9-$FA1B)
Command definitions
($FB1E-$FEBA)
Interrupt Service Routine
($FF57-$FF79)
Most of the software operates in the Command Mode, responding to inputs from the host system. The Command Mode section
includes Parts 1-5, with the exception of the (Carriage
Return) command in Part 4. The remaining sections of Figure 4
lie within the definition olthe < CR > command. Figure 5 shows
the flow chart of the Command Mode section.
R6500111-R2424 Intelligent Modem Parts List
Item
1:
2:
3:
4:
5:
After initialization, the software loops in Part 1, waiting for an
attention code ("AT" or "AI") or for the phone to ring. Any
system designed to run the "AT" command set must be able
to operate at either 300 or 1200 (or, in this case, 2400) baud,
using 7 or 8 bits per word, with even, odd or no parity, switching
from one mode to another automatically. The method used to
do this is outlined on page 0004 of the software listing, Figure 7. Figure 6 diagrams the bit patterns of the characters "A",
"T" and "I" and shows how the relationship of bits 8 and 9 of
each character determine the characteristics of the serial
protocol.
*PAL and PALASM are registered trademarks of Monolithic MemOries, Inc.
Document No. 29220N69
Application Note
4-3
Order No. 669
December 1984
II
Application Note
R6500/11 • R2424 Intelligent Modem Design
In Part 2 the serial communications protocol as been established.
ASCII command characters are read in one al a ~ime and stored
in a buffer (INBUFF), excepting and non-
control characters, until a < CR > character is entered. Should
more than 40 characters be received, a flag (BUFFLG) is set,
indicating an error condition.
General notes on the software:
Liberal use was made of the avaiiable RAM for 1-bit flags and
variables, primarily because no premium is placed on RAM
space in this deSign. These could be compressed into byte-sized
entities should more space be required.
When the program recognizes a < CR > character it stops
accepting commands and goes directly to command execution
(Part 3). It processes each command in sequence until an "A",
"0", "Z" or command. "A" and "0" forces an attempt
to go on-line (examine RSLDI for carrier signal and go on-line
if present, otherwise it will go back to Command Mode.) "Z"
performs a soft reset and returns to Command Mode.
is the usual end to each command string. This is where error
conditions are reported, on-line data are handled, and a return
to Command Mode from Data Mode is made upon recognition
of a valid escape code sequence.
No attempt was made to provide status information via the S13,
S14, S15 or S17 pseudo-registers. These could be added if
necessary.
The S10 (Loss of Carrier) and S11 (Touch-Tone) delay times are
limited to 400 ms and 70 ms, respectively, due to the design
of the R2424 Modem.
The "H2" command does nothing additional to the "H1" command since the R2424 Modem does not have an auxiliary relay.
This intelligent modem will recognize that it is being called only
while it is waiting for an attention code (at label L 1). If the PAO
flag goes high at this point, indicating the phone is "ringing",
the program branches to RING then jumps to RINGNG, where
a determination is made whether to answer the phone or not.
If not ringing, it goes back to waiting for "AT" or "AI". If it is
ringing, it then bypasses Part 2 and Part 3 and attempts to go
to the Data Mode (depending on presence of a carrier signal)
by executing the "A" (Answer) command.
This program implements the concepts of modularity and structured programming as much as was practical for assembly-level
code. This allows easy customization and tailoring for a particular
application. There are deviations from this guideline, however,
so modifications should be made with this in mind.
Expansion might include detection of Dial tone, Ringing and
Busy signals using the TONE bit of RCV8. For example, if a Busy
signal is detected, the program could automatically re-dial after
a suitable delay time.
When this modem is called, an assumption is made as to the
proper baud rate and serial protocol, that the values determined
by the most recent attention code are still valid. Should a call
be received before the first attention code was entered, it defaults
to 1200 baud, 8 bits, no parity. The call is not answered in this
case, since SO was not set to a non-zero value, however, the
"RING" message is sent out to the host system at this rate.
Unlike some commercial intelligent modems, no default switches
or status LEDs were implemented in this design, nor was an
actual speaker Circuit included (though a control line for one,
SPKR-ON/, is provided) in the interests of simplicity.
Finally, this design has not been thoroughly tested to meet the
"AT" specifications. This application note is presented only as
a guide on how to control a R2424 Modem with a R6500/11
single-chip microcomputer.
Part 4 comprises the coding of each "AT" command. All but
AAA, 000, ZZZ and CR end in an RTS instruction, returning
control back to the command string processor at NXTCMD. AAA
and 000 transfer control directly to CR in an attempt to go online. CR always returns to Part 1 of the program, and ZZZ always
jumps to the Power-On-Reset address at RESET.
SERIAL INTERFACE
The modem system supports the following data rates and
asynchronous serial protocols:
Baud: 300, 1200 or 2400
No. of data bits: 7 or 8
No. of stop bits: 1 or 2
Parity: Odd, even or none
Part 5 is divided into two parts: signal processing and delay
timing (execution of one or the other is determined by the value
of the INTFLG flag). The Signal processing takes place while
waiting for an attention code, echoing (if enabled) the incoming
bits back to the host system, and is described on page 0004
of Figure 7. Delay timing is selected just before Part 2 (or if a
call is answered). The delay routine is designed to allow a
variable number of precise time delays, where the actual time
interval is determined by the routine needing the delay. For
example, the "," (comma) command tells the modem to do
nothing for S8 number of seconds, so one time interval would
be 1 second. The Carrier Detect Response time interval is 1110
second and the Escape Code Guard time interval is 20 ms, each
requiring different values for CNTR-B and DELAYT.
The baud rate is determined by the width of the start bit.
The number of data bits, the number of stop bits and parity type
are determined by examining bit 8 and, sometimes, bit 9 in two
consecutive data words comprising an "AT" or "AI" command.
Figure 6 shows the serial stream waveforms for the "AT" or "AI"
commands along with the message bits positions. Table 2 lists
the six selectable protocol configurations.
4-4
Application Note
R6500/11 • R2424 Intelligent Modem' Design
~8D36MHZ 5
+5
R1
. ..
4.7K
1
2
~21
22 XTLO XTLI VCC
NMI
PDO
P01
PD2
P03
32
P04
PB8
P05
P08
P07
PCO
PC1
PCZ
PC3
KR· N
+5 ' 9C 23C 28C 30C
1DA~
+12
12A
-12
T 31 .32
19
18
17
18
15
14
13
12
4
5
8
4
D8
07
AU
A1
A2
A3
+5
t2
.2 3
PC7 11
PCS II
PC4
PCS 10
PA8 24
PBO
12
A13
TXO
23
TXOH
PA7
HI·SpEEO 25
PAS
26
PA4
5
PAL18L8
Z2
C Lr---i
TX H~
: ~:
~
37
30
138
35
34
27
12U
Z3
i~c
1 NCWRITE
IIIW
38
R24240C
VCC~
1
EMS
+5+5
R2
3K
PB1
PAO
PB2
PB3
PB4
PA3
RES
5C
DO
4A 01
4C 02
3A
03
~A
04
2
1A 05
08
1C 07
7A
RSO
7
SA RS1
RS2
til;
RS3
03
R8500111
Z1
'"
DO
1
02
,.1R GNO
7
11A
WRITE
10
CSO
12
READ
24
TXO
RXO
CS1
CSO
18
15
14
REA[
TxDM
rtf~
~~
CiI
NC
RXOM
25C CTS
18A RI
"S
~1
20
24
11
=n
Di'fi
D§ii
mD
iRll
POR
4~
28C
1
TLK
II)
+
e~
.
IZ:~
..
"'
~i
~~
'"~...:::
II)
0
w
w
~ ] -i
Z4
18%
"'
..
","
,;"'::
t-~
"leo "'~
P11
:l:1~
~
MC1488
'"
or
~
)(IZ:
I
... t;
-I
II)
MC1488 Z5
.....
"'~
"inN CD
+
fr>
_t-
..
.....
0:-=
t-4>
MC1489 Z6
-..
"'l;:
FEMALE 08-25
Figure 1.
R6500/11·R2424 Intelligent Modem Schematic
4·5
t-Lt>
I
•
Application Note
R6500/11 • R2424 Intelligent Modem Design
r01
1.8432 MHZ
..
PDO-PD7
~
tl
AD
OO-D7
DATA BUS
Do-D7
~
AD
RSO
A1
A1
RS1
A2
A2
RS2
A3
RS3
A3
D.
RJW
,..
...
R65DDN1
R2424DC
~12
-"
+5
~
RES
RXD
'"
ali
,-
A13
.,..-
READ
...
...
TXDH
'"
WRITE
,-
,.
'"'
,..
...
'"
m
F
POR
TXD
TXDM
CTL
~
~
RXDH
-
,..
(
r-
Figure 2.
Logic for 16L8 PAL (Z2)
4-6
RXDM
Application Note
R6500/11 • R2424 Intelligent Modem Design
PAL16L8
MODEM
MODEM CONTROL CIRCUIT
JW HANCE
P2 EMS RW A12 A13 TXD RXDM CTL TXDH GND NC
ICS1 RXDH TXDM READ ICSO !WRITE NC NC VCC
IF (VCC) WRITE = P2 * IEMS * IRW
IF (VCC) IREAD = IP2 + EMS + IRW
IF (VCC) CSO = IEMS * A12 * 1A13
IF (VCC) CS1 = IEMS * IA12 * A13
IF (VCC) IRXDH = ITXD * CTL + ITXD * IRXDM + ICTL * IRXDM
IF (VCC) ITXDM = ICTL * ITXDH
*END*
Figure 3. PAL16L8 (Z2) PALASM Equations
COMMAND
MODE
-PHONE RINGS SO TIMES
-"0" (ON·LINE) COMMAND
-"A" (ANSWER) COMMAND
-"D" (DIAL) COMMAND
HANG
UP
WAIT
FOR
CARRIER
-NO CARRIER
DETECTED
-TERMINAL
KEY PRESSED
-CA RRIER DETECTED
- CARRIER LOST
DATA
MODE
-ESCAPE
CODE
ENTERED
Figure 4.
Modem Software Functional State Diagram
4·7
•
Application Note
R6500/11 • R2424 Intelligent Modem Design
ANSWER PHONE
Figure 5.
Command Mode Flowchart
4-8
R6500/11 • R2424 Intelligent Modem Design
Application Note
WAIT 2 BIT TIMES
•
Figure 5. Command Mode Flowchart (Continued)
4-9
Application Note
R6500/11 • R2424 Intelligent Modem Design
COMMAND PROCESSOR
Figure 5.
Command Mode Flowchart (Continued)
4-10
Application Note
R6500/11 • R2424 Intelligent Modem Design
D
SEND OUT A
TO OVERWRITE
CHAR ON DISPLAY
•
JUMP TO
"CR n
Figure 5. Command Mode Flowchart (Continued)
4-11
R6500/11 • R2424 Intelligent Modem Design
Application Note
NXTCMD
FETCH (NEXT) CHAR FROM
BUFFER AND COMPARE IT
TO THE VALID COMMAND
BYTES IN CMDTBL
N
PUT ADDRESS OF
CORRESPONDING
SUBROUTINE IN
JUMP VECYOR
JUMP TO
"CR"
Figure 5. Command Mode Flowchart (Continued)
4-12
Application Note
R6500/11 • R2424 Intelligent Modem Design
BIT NO.
CHAR.
A
CODe
41 (hex)
=
DATA
T
=
54 (hex)
1=
rTT------
2F (hex)
I_.L..J.. _ _ _ _ _
o
0
NO PARITY-ALWAYS 2 STOP BITS
8
9
STOP
BIT
8 DATA BITS
7 DATA BITS
8
9
STOP
BIT
STOP
BIT
STOP
BIT
II
WITH PARITY
8 DATA BITS
7 DATA BITS
Figure 6. Serial Protocol Formats Data Length
Table 2. Selectable Serial Protocol Configurations
Command
Word No.
1
2
1
2
1
2
1
2
1
2
1
2
Command
ASCII Char.
(Bits 1-7)
A
Tor I
A
T or I
A
Tor I
A
Tor I
A
Tori
A
Tori
Command Word
BH 8
Command Word
BH 9
1
-
0
0
1
1
1
0
0
0
0
0
0
1
0
0
1
1
1
4-13
Message Protocol
Odd parity, 7 data bits, 2 stop bits
Even parity, 7 data bits, 2 stop bits
No parity, 7 data bits, 2 stop bits
Odd parity, 8 data bits, 1 stop bit
Even parity, 8 data bits, 1 stop bit
No parity, 8 data bits, 2 stop bits
Application Note
R6500111 • R2424 Intelligent Modem Design
PABE.OOOI
0001
0002
0003
0004
0005
0006
0007
0008
0009
0010
0011 0000
0012
0013 0000
0014 0001
0015
0016 0002
0017
00la 0011
0019 0012
0020 0014
0021 0015
0022 0016
0023 0017
0024 0017
0025 OOla
0026 0019
0027 00111
0028
0029 0018
0030 OOlC
0031 OOlD
0032 DOlE
0033
0034 OOlF
0035
0036 0040
0037 0041
0038 0042
0039 0043
0040 0044
0041 0045
0042 0046
0043 0047
0044 004B
0045 0049
0046 004A
0047 0048
004B 004C
0049 0074
0050 0075
0051 0076
0052 0077
0053 007B
0054 0079
I THIS IS APRD6RAII FOR All R11500111 Am. AS All IIITERFIICE
I BETIlEEIl AHOST tOllPUTER IIITH ASERIAL PORT AIIIl AN R2424
I IlllDE". IT IS DESI&NED TO RUN THE "AT" tIIIIIIAHD SET.
I ••••••'II. .c .................a .......... ••__••=._u•••
~
•OPT
.OPT
LLEN·132
IVB
.·$0000
PA
P8
"'+1
"'+1
.·$11
IFR
IER
a
ICCR
SCSR
STIR
SROR
'·'+1
"'+2
..ttl
,.ttl
..ttl
'·'+1
•
STDR
tllTACL "'+1
tITAN "'+1
CNTAL "'+1
'·'+1
CNTBCL '.'+1
CNTBHC ,.ttl
ClT8HL "'+1
,
DEFPRO
BAUD
8DRATL
aDRATH
DELAYC
DELAYT
DELAYS
TESTI
ABITI
AIIT9
TllTa
T8IT9
IUUFF
REPFLB
BlfFLB
DILFLI
REYFLI
IRGFLB
ECHOFB
"'+1
,.ttl
..ttl
,.ttl
"'+1
••ttl
•• t+l
,.ttl
,.ttl
,.ttl
'.'+1
t·'+l
'·'+40
,.t+l
t-t+ 1
'·'+1
'.'+1
"'+1
"'+1
• $40
; AM VARIABLES
I DEFAIA.T SERIAL PROTOCOL FOR AUTlI-AIISIIER CO_ICATIOIIS
I IIDICATOR OF PRESENT TERNIMAL BAUD RATE , 3/12/24 I
. LIN PART OF BAUD RATE, AS DETEANINED BY CNTR-A
HIBN PART OF BAUD RATE
IRI COIIIITER: COUITS IIUIIBER OF TIMES IRQ ROIITIIE IS CALLED
SET TO THE • OF TIlES THE IRI ROUTIIE IS TO BE CALLED
SET TO TilE IllllllER OF SECDIDS TO IlAIT FOR
CONTAINS THE 7 SAllPLE 8ITI FRDI THE SERIAL-III LINE
lIKEN THE 7 BITS CLOCKED INTO "TEST8· MTCH TIE "A" CHAR,
THE MElt 2 8ITI ARE CLOCKED III AID STORED lIRE.
lIKEN THE 7 SMPLE 8ITS IN ·TEST8" "ATCH THE ·T· CHAR, THE
NElT 2 BITS ARE STORED III ·TBITB· AIIO ·Tlm·.
CONTAINS THE CIIIIIIAIIO 6TRI. AS EIITERED FRO" THE HOST IYS.
I lIKEN "AI" IS ENTERED AS COIIIIAHD, THIS FLAB 16 SET.
; THIS FLAB IS SET lIKEN TOO lAKY COMA. CHARS ARE EIITERED
I IS SET TO IIDICATE AllY FOLLOIIIIIB IlUllBERS ARE DIAL DIBITS
; IIORIIAL (s001 OR REVERSE '$801 DIAL
I $00 -) IRQ IS SERIAL-III TIlERI $80 n) IRII IS DELAY TIlER
I toO •• ) 00 NOT ECHO COMD CHARSI $80 •• ) ECHO CHARS
Figure 7. Software Assembly Listing
4-14
Application Note
_00711
00S6 007.
00S7 007C
0058 007D
_007£
0060 OOlF
0061 0080
R6500111 • R2424 Intelligent Modem Design
DIILEl
RSLlfB
SPlCRFB
aTCODE
YeODE
ICODE
MAllfB
'."1
I ECHO CHARS IIHILE IN DATA NODE ION-LINE) • D-ND, fB08YES
I $00 •• >SEND OUT RESULT PRDllPT. $80 n> DON'T SEND IT OUT.
I USED TO CONTROL THE ElTERIIAL SPEAKER
I RESULT (STATUS) CODE I 0-4,5 )
I SEND RESULT PROIIPT III twalt I $00 ) OR VERBAL I $80 ) FOR"
I ALLlII ElTEIID£D RESULT CODES 1 I $00 • 110 I $80 • YES )
I 'IiAn-FOR-CARRIER l' FLAB 10· ND I $80 • YES I
""I
'.'+1
'.'+1
'·"1
"'+1
'.'+1
PAlE 0002
0062 0081
0063 0082
0064 0083
oo.s 0084
00"
00.7
OOllS
00., 0086
0070 0087
0071 008B
00720089
0073 00811
0074 0088
007500BC
0076 008D
0077 OOSE
007800BF
0079 0090
0080 0091
0081 0092
00820093
0083 0094
0084 0095
00B5 0096
0086 0097
0087
0088 0091
0089 0098
0090 OO9D
MAITC
ESCCNT
SSElf&
SRE&P
'.'+1
'."1
'."1
'."2
;
;
;
;
INDICATES 'IIAIT-FOR-CARRIER' TINE INTERVAL HAS ELAPSED
ESCAPE CODE COUNTER
INDICATES S-RES POINTER HAS BEEN SET TO SOlIE VALlIE
CONTAIIiS THE INDIRECT POINTER TO ONE OF THE S-RESISTERS
I THE FDLLOIIINB 17 BYTES CONTAIN THE VALUES FOR TIE S-RESISTERS
SO
51
52
63
14
IS
S6
17
S8
5'
S10
511
112
S13
S14
51:!
ss.
117
""I
'·"1
'·'+1
'·"1
""I
""I
""I
"'+1
'·"1
"'+1
""I
'·'+1
'·'+1
""I
""I
'·'+1
,
I
I
;
I
""I
'.'+1
IIUII ta"3
COVEC '''+2
TE. tat+l
RIllS TO ANSIIER ON
COIIIITS THE IIU"BER DF RINSS
ESCAPE CODE CHARACTER
CARR IASE RETURN CHAR
LINE FEED CHAR
BACKSPACE CHAR
IIAlT -TI"E FDR DIAL TONE
IIAn-mE FDR CARRIER (AFTER DIALI. OR AIISIIERIIIB )
PAUSE-TIllE ( USED BY 'CIIIIIIA' CDllllAIID )
CARRIER-DETECT RESPONSE TIllE
DELAY-TIllE BETllEEII LOSS OF CARRIER AND 'HANS UP'
DURATION AND 5PAC III OF TOUCH TOIlES
ESCAPE CODE SUAR8-TIllE
UART STATUS RESISTER
OPTION REGISTER
FLAG RESISTER
I:EIITER SELF-TEST I O=STDP SELF-TEST
SENERAL SYSTEII STATUS
I MURK AREA FOR ASCII-TD-HEX AND HEX-TD-ASCll CONVERSION
I INDIRECT PDINTER TD THE NEIT CONMND TO BE EXECUTED
I TE.DRARY STDRASE BYTE
PASE 0003
0092
0093
0094
0095
0096
0097
0098
0099
0100
0101
0102
1000
RCV
OO9E
1002
1008
1009
RCY2
RCY8
IODA
lOOB
loot
lOOD
lOGE
RCY9
RCVA
RCYB
RCYC
RevD
RCVE
•
..
flOOO
I BASE ADDRESS FOR RECEIVER RESIITERS
RCYt2
""6
18"1
'·'+1
'·'+1
18"1
..t+l
'.'+1
18"1
4-15
•
Application Note.
0103 100F
0104
0105 2000
0106
0107 1010
0108 2000
0109 2002
0110 2008
0111 2009
0112 200A
0113 200B
0114 200C
0115 200D
0116 200E
0117 200F
0118
0119 0010
0120 E09C
0121 6760
0122 0001
OI23479C
0124
0125 OOBF
0126 002F
0127 0017
0128
0129 0021
R6500/11 • R2424 Intelligent Modem Design
RCYF
f.ftl
I"T
=$2000
X"TO
xm
X"T8
X"T9
X"TA
mB
X"TC
mD
I BASE ADDRESS FOR THE TRANS"ITTER REGISTERS
m
f.
f"ft2
f=1+6
f=ftl
f=ftl
f=1+1
f·'+1
'='+1
t=.tl
.=1+1
xm
xm '='+1
DLYHIB •
DLYm·
TENTHD •
ESCDLY "
ESCTI"
.10
$E09C
$6760
I
.479C
I I COUNT FDA 'ESCAPE' CODE &UARD mE ( 20"S )
BAUD3 "
BAUDI2 "
BAUD24 •
.OOBF
.002F
$0017
I CNTR-A YALUE FDA SERIAL-lID BAUD RATE OF 300 BAUD ( • 920KHz
I YALUE FOR 1200 BAUD
I YALUE FDA 2400 BAUD
NU"C"D •
33
I NU"BER OF COMANDS IN 'C"DTBL'
=
I DELAY-mE FACTOR
I ( DL YTI" • DLYHI8 • 920KHZ • 1 SEC. )
I ( TENTHD • DLYHIB t 920KHZ. 1/10 SEC. )
PAGE 0004
0131
0132
0133
0134
0135
0136
0137
0138
om
0140
0141
0142
0143
0144
0145
0146
0147
2010
'=$FIOO
FIOO
FI02
FB03
FI04
FB05
F807
A2 FF
9A
DB
78
A9 AO
85 14
F809
20 BE FA
F80C
FlOE
FBIO
FBI2
FBI4
87
17
27
1)7
E7
01
01
01
01
01
I$FF
I INITIALIZE THE R6500/11
I$AO
"CR
I SET UP "ODE RE&lSTER FOR ABBREYIATED BUS
JSR
INITSW
I INITIALIZE YARIABlES, ETC.
S"B
R"B
R"B
S"B
S"B
O,PB
I,PB
2,PS
5,PS
6,PB
I CTl "0 (TRANSm TO "om )
ICTS/=O
I DTRI = 0 (ACTlYE)
I HISPEED " 1 ( HI&H SPEED )
I DI SABLE SPEAKER
RESET lDX
TXS
ClD
SEI
lOA
STA
4-16
Application Note
i
0148
0149
0150
0151
0152
0153
0154
0155
0156
0157
0158
0159
0160
0161
0162
0163
0164
0165
0166
0167
0168
0169
0170
R6500/11 • R2424 Intelligent Modem Design
tltIfttlfttftttfttfttltlftfttffftfttftffftfftfttftfftftfttftttftftftt
FIRST CHARS ACROSS SHOULD BE 'AT' DR "AI'. ASSUIIE AN 'A'
IS THE FIRST CHAR: BY miNG THE DURATION OF THE FIRST LOll
PULSE (START BIT), THE BAUD RATE IS DETERltINED. USING THIS AS
THE IIIDTH OF ONE BIT, 7 SAIIPLES ARE !tADE OF THE SERIAL INPUT LINE
AT ONE-BIT INTERVALS, IIITH EACH 'BIT' SHIFTED INTO A TEST BUFFER
( 'TESTB' I. AFTER 7 SAIIPLES, THE TEST BUFFER IS RIGHT-JUSTIFIED
(SHIFTED RI6HT ONE IIORE mE) AND COIIPARED TO THE ASCII 'A' CHAR.
IF A IIATCH IS NOT !tADE, liE IIAlT 2 IIDRE 'BITS', TIllE THE NEXT LOll PULSE
AND CLOCK IN 7 IIoRE BITS.
IF A IIATCH IS FOUND, AN 'A' CHAR IS ASSUIlED TO HAYE BEEN READ IN
AND THE NElT Tilo BITS ARE SAYED FOR FUTURE DETERIiINATION OF
TRANSIiISSION PROTOCOL (PARITY I BITS/CHARI. THE NEXT CHAR IS
CLOCKED IN AND COIIPARED TO 'T' AND 'I'. IF A IIATCH IS FOUND THEN
• THE PROTOCOL IS DETERIiINED AND THE COIIIIAND BYTES FDR THE IIODEII
( IF ANY I ARE READ IN AND PROCESSED.
IF A !tATCH IS NOT FOUND FDR 'AT' DR 'AI' THEN liE START DYER ABAIN
LOOKIN6 FOR AN 'A' CHAR.
IIEANIIHILE, IF CHARACTER ECHOING HAS BEEN ENABLED ( AND BY DEFAULT
IT IS I, TIllER B IS 6ENERATlNB INTERRUPTS AT A FREIlUENCY SLI&HTLY
&REATER THAN TlliCE THE 2400 BAUD ( IIAXlIIUIi ALLOIIABLE BAUD RATE I FREQUENCY.
THE INTERRUPT ROUTINE SAIIPLES THE LEVEL OF THE SERIAL INPUT LINE AND SETS
THE SERIAL OUTPUT LINE TO !tATCH. THIS HAS THE EFFECT OF BLINDLY ECHOINS
INCOIiING CHARACTERS BACK TO THE HOST CDIIPUTER. THIS IIILL BE DONE UNTIL
, 'AT' DR 'AI' HAS BEEN RECO&NlZED, AT IIHICH POINT THE IRQ IS DISABLED
AND CHARACTERS ARE ECHOED BACK AS CHARACTERS, NOT AS BITS.
0171
0172
0173
0174
0175
0176
0177
0178
0179
01BO
01Bl
0182
0183
0184
0185
0186
0187
0188
0189
0190
F816
F818
F81A
F81t
F81E
F820
F822
F824
F826
F828
F82A
F82t
F82E
F831
F833
0191 F836
A9 00
85 15
85 74
85 4B
85 49
85 4A
85 48
85 47
85 76
85 80
85 75
85 70
AD 00 10
09 04
8D 00 10
20 D7 FD
RESTRT LDA
STA
STA
STA
STA
STA
STA
STA
STA
STA
STA
STA
LDA
ORA
STA
JSR
100
i DISABlE RECEIVER AND TRANS"ITTER
seeR
REPFL&
ABIT8
ABlT9
TBlTB
TBlT9
TESTB
DILFL&
IIAlTFB
BUFFLS
STCODE
RCYD
1$04
RCVD
NEIICR
i CLEAR OUT IIORKIN& VARIABlES
i PREYENT NUIIBERS FROII DIALING UNTIL 'DIAL' CDII"AND
I ASSUIIE 'OK' -- STCODE MILL BE RESET IF A PROBlE" ARISES
i SET 'LCD' BIT
I UPDATE RECEIYER RESISTER
PABE 0005
0192
0193
0194
0195
0196
0197
0198
F839
F838
F83D
F83F
F841
F844
F846
07
A9
OS
85
7F
10
03
14
14
79 OC
A9 80
85 lC
RltB
LDA
DRA
STA
8BR
lOA
STA
0, IFR-I
103
IICR
IICA
7,ECHOFS,NOIRIl
1$80
CNTBCL
i CLEAR 'RINS' FLAG BIT FROII FLAS RESISTER
i &NTR A = PULSE IIDTH TIllER
I NO ECHO IF FLAB TURNED OFF
; START TIllER B TD PERIODICALLY SAIIPLE
I THE SERIAL INPUT LINE AND ECHO BACK
4-17
•
Application Note
019'1 F848
0200 F84A
0201 F84C
0202 F84E
0203 F850
0204 F852
0205 FB53
0206 F855
0207 F857
0208 F85A
0209 F85D
0210 F85F
0211
0212 F862
0213 F863
0214 F865
0215 F867
0216 F869
0217 F86A
0218 F86e
0219 FB6E
0220 F86F
0221 F871
0222 FB73
0223 FB75
0224 F877
0225 FB79
022& F87A
0227 F87B
0228 F87D
0229 F880
0230 F882
0231 F884
0232 F885
0233 F887
0234 FBB.
0235 F88C
0236 F8BE
0237 F890
023B F8'l1
0239 Fa93
0240 F894
0241 FB96
0242F898
0243 F899
0244 F898
0245 F89D
0246 FB9E
0247 FB9F
0248 FBAI
0249 F8A4
0250 F8A7
0251
0252 FaAA
A900
85 IE
D7 12
77 78
A'IFF
A8
85 18
84 lA
8F 11 50
FF 00 FA
6700
7F 00 FD
R6500/11 • R2424 Intelligent Modem Design
LDA
STA
S"B
R"B
NOIRII LDA
TAY
STA
STY
BBS
LI
BBS
R"B
BBR
L2
100
CNTBHL
S,IER
7,IRQFL6
I$FF
; THE SAllE L06IC LEVEL ON THE OUTPUT
; LINE.
CNTACL
CNTAL
0,IFR,RIN6
7,PA,L!
6,PA
7,PA,L2
; READY CNTR A FOR PULSE-II 10TH "EASURE"ENT
;
;
;
;
;
CLI
LOA
EOR
STA
TAY
LDA
EOR
TAl
LOA
AND
STA
58
A5 19
4'IFF
8543
AS
A5 18
4'IFF
AA
A9 FC
25 14
85 14
B642
86 18
STX
STX
98
4A
85 111
4F 11
84 IA
A500
OA
66 47
A2 06
4F 11
AS 18
A500
OA
6647
eA
DO F3
A547
4A
C941
FO 10
98
OA
85 lA
4F 11
7F 00
4C 16
FD
FD
FD
FD
FB
4C lC FA
TVA
LSR
STA
BBR
L3
STY
LOA
ASl
ROR
LOX
L4
B8R
LDA
LOA
ASL
ROR
DEI
BNE
LDA
LSR
C"P
BEQ
TVA
IISL
STA
L4A
BBR
BBR
L5
602RES J"P
RING
J"P
;
;
;
;
CNTAH
UFF
BDRATH
IF PHONE IS RIN6IN6, 60 SEE IF IT'S mE TO ANSIIER IT
IIAlT FOR RECEIVE LINE TO 60 LOll
SET SERIAL-OUT LINE LOll TO "ATCH
Nail tlAlT FOR IT TO 60 BACK HI6H ( THIS SHOULD
BE THE START BIT OF 'A' )
ALLOII mER-B IRQ
6ET PULSE IIIDTH COUNT
INVERT lT
AND SAVE IT
CNTACL
I$FF
; SET CNTR A = TlftE INTERVAL COUNTER
I$FC
"eft
"CR
BDRATL
CNTACL
A
CNTAL
4,IFR,L3
CNTAL
PA
A
TESTB
106
4,IFR,L4
CNTACL
PA
A.
TESTB
,
;
;
;
;
;
;
;
SAVE LOll BYT OF COUNT
SET LOll BYTE OF BAUD mER
SET UP COUNTER FOR 1/2 BIT WIDTH, TO
PosmON SERIAL LINE SA"PLES APPROI.
IN "IDDLE OF BIT.
IIAlT FOR mER
NOlI START mER A IIITH FULL OELAY (ALSO CLEARS FLAB )
6ET VALUE OF SERIAL BIT (SHOULD BE HI6H)
ROTATE RECEIVE BIT VALUE INTO CARRY BIT
ANa ROTATE lT INTO TEST 8YTE
CLOCK IN 6 "ORE SERIAL BITS
NA lT FOR ONE BIT mE
CLEAR FLA6
SET SERIAL BIT
AND ROTATE IT INTO TESTB
; CLOCKED IN 6 BITS YET 7
; NO ... > 6ET NEXT BIT
; YES::> IS CHAR AN 'A' 7
; ( RI6HT-JUSTlFY TEST CHAR )
L4
TEST8
A
IT
A
CNTAL
4,IFR,L4A
7,PA,L5
RESTRT
;
;
;
;
;
I
;
RIN6N6
I CHECK RING COUNT.
FOUNDA
4-18
YES:-) CHECK NEXT CHAR FOR 'T' OR '/'
NO ==) MAlT 2 BIT mES
THEN JU"P TO 'RESTART'
TO READ I N ANOTHER TEST CHAR
NAIl FOR Tl"ER
THEN "AKE SURE INPUT LINE IS HI6H
... AND READ IN ANOTHER 7 BITS
IF PHONE HAS RUNS ENOU6H mes
Application Note
R6500/11 • R2424 Intelligent Modem Design
PA6E 0006
0253
0254
0255
0256
0257
0258
0259 F8AD
0260 FBBO
0261 FBB2
0262 F884
0263 F8B5
0264 F8B7
0265 F88A
0266 FBSC
0267 F8BE
0268 F88F
0269 F8CI
0270 F8C4
0271 F8C7
0272 F8C9
0273 FBeA
0274 F8CS
0275 FBCD
0276 F8DO
0217 F8D2
0278 F8D4
om F8D7
0280 F8D9
0281 F8DB
0282 F8DC
0283 F8DE
0284 FBDF
02B5 FBEI
02B6 F8E3
02B7 F8E4
0288 FBE6
02B9 F8ES
0290 FBEA
0291 FBEC
0292
0293 F8EF
0294
om F8FI
0296 FSF4
om FBF6
0298 F8F8
0299 FBF9
0300 FBFB
0301 F8FE
0302 F900
0303 F902
0304 F903
0305
( AS DETERMINED BY NEG 0 ) THEN ANSIlER IT.
OTHERWISE, 60 BACK TO 'RESTART'
j
4F II
AS lB
AS 00
OA
66 4B
4F 11
AS 18
A500
OA
6649
7F 00
FF 00
Sb 47
98
4A
B5 IA
4F II
84 IA
A2 07
4F II
AS 18
AS 00
OA
66 47
CA
DO F3
A5 47
4A
C92F
FO 07
C954
FO 05
4C 16
FD
FD
FD
FD
FD
FOUND AN 'A' CHAR. NOW SAVE NEXT TWO BITS FOR PROTOCOL CHECK,
THEN CHECK FOR 'T' OR '/' CHARS.
FOUNDA BBR
LDA
LDA
ASL
ROR
L6
BSR
LDA
LDA
ASL
ROR
L7
BSR
L8
BBS
STl
TYA
LSR
STA
L9
BBR
STY
m
FD
FB
L10
BBR
LDA
lDA
ASl
ROR
DEI
BHE
LDA
LSR
CMP
BEQ
CMP
BEQ
J"P
4,IFR,FOUNDA
CNTACL
PA
A
ABlT8
4,IFR,L6
CNTACL
PA
A
ABlT9
7,PA,L7
7,PA,LB
TESTS
A
CNTAl
4,IFR,L9
CNTAl
107
4,IFR,LlO
CNTACL
PA
A
TEST8
j WAIT ONE BIT mE
; CLEAR FLA6
; 6ET BIT
; SAVE IT AS BIT B OF 'A' ( FOR FORKAT CHECK INS LATER)
j GET BIT 9 (WAIT ONE MORE BIT mE )
; CLEAR FLAG
; AND SAVE 'A' BIT 9
; WAIT FOR RECEIVE LINE TO 60 HIGH
j NOli WAlT FOR IT TD 60 LOll ( START SIT)
; RESET 'TESTS' FOR 'T' AND '/' CHECK
; DELAY APPROX. 112 BIT lIKE
; ( DIVIDE KSB OF DELAY lIKE SY 2 )
; START mER
; WAIT FOR mER
j RESTART mER (AND CLEAR FLAG )
; CLOCK IN 7 BITS ONLY ( OF CHAR FOLLOWING 'A' )
; IIAIT FDR mER
; CLEAR FLAG
; SET BIT
FoUNDT
RESTRT
;
;
;
;
;
i
;
;
;
;
L10
TESTB
A
1'/'
FOUNDS
IT
AND SHIFT IT IN 'TESTS"
7 BITS YET?
NO ==) 6ET NEXT BIT
YES==) SEE IF THIS CHAR MATCHES 'T' DR '/'
( RIBHT-JUSTIFY CHAR)
'/' ?
YES:=) 'AI' CHARS RECEIVED --) FI6URE OUT PROTOCOL
NO ==) 'T' ?
YES==) 'AT' CHARS RECEIVED --) FIBURE OUT PROTOCOL
NO ==) START OVER .....
F7 74
FOUNDS 5MB
7,REPFLB
; INDICATE REPEAT OF LAST COMMAND STRINB
4F II FD
A5 18
A500
OA
66 4A
4F 11 FD
AS 18
A500
OA
6b 4B
FDUNDT BBR
LDA
LDA
ASL
ROR
L12
8BR
LDA
LDA
ASL
RoR
4,IFR,FDUNDT
CNTACL
fA
A
TBlTB
4,IFR,L12
CNTACL
PA
A
TBIT9
j WAlT ONE BIT TlftE
; CLEAR FLAB
; SAVE BIT 8
; IIAIT ONE LAST BIT mE
i CLEAR BIT-WIDTH FLAG
; SAVE BIT 9
4-19
II
Application Note
0306
0307
0308
0309 n05
0310 n07
0311 F909
0312 F90B
ommD
R6500/11 • R2424 Intelligent Modem Design
i BAUD RATE DETER"INED. NOM mURE OUT TRANS"ISSION PROTOCOL
I NU"BER BITS/CHAR, ODD/EVEN/NO PARITY )
2449
10 14
244B
10 16
AS 48
BIT
BPL
BIT
BPL
LDA
ABm
EVEN8
TBm
0008
ABIT8
;
;
;
;
I
IS BIT
YES==)
NO ==)
YES==)
NO ==)
9 OF 'A' = 0 ?
PROTOCOL IS B BITS/CHAR, EVEN PARITY
IS BIT 9 OF 'T' = 0 ?
PROTOCOL IS 8 BITS/CHAR, ODD PARITY
ARE EI6HTH BITS OF 'A' AND 'T'
PASE 0007
0314 F90F
0315 nil
0316 F913
0317F915
0318,F917
0319F919
0320 F91B
0321 F91D
0322 F91F
0323 F921
0324 F923
0325 F925
0326 F927
0327 F929
0328 F92B
0329 F92D
0330 F92F
0331 F931
0332 F933
OmF935
0334 F937
0335 F939
0336 F93B
0337
0338 F93D
0339 F93F
0340 F941
0341 F943
0342 F945
0343 F947
0344 mB
0345 F94A
0346 mc
0347 mE
0348 F950
0349 F9S2
0350 F954
0351 F956
0352 m8
0353 F9SA
0354 F95C
0355 F95E
0356 mo
454A
FO IC
2448
10 12
A9C6
AO 10
DO 20
A9C3
AO 18
00 IA
AH2
AO IB
DO 14
AH7
AO 10
DO OE
2448
3006
Ano
AO 10
DO 04
A9 C4
AD OB
85 15
85 40
A204
4643
66 42
CA
DO F9
AS 42
B5 18
AS 43
85 IA
57 12
A5 42
e985
9008
A203
5701
A9 04
DO 12
0007
EYEN8
ODDB
EVEN7
NOPAR
ROPARB
"DPAR7
EOR
BEQ
BIT
BPL
LDA
LDY
BHE
LOA
LDY
BHE
LOA
LDY
BHE
LDA
LOY
BNE
BIT
B"I
LDA
LOY
SNE
LOA
LDY
LABELl STA
STA
LDI
ROTATE LSR
ROR
DEI
BNE
LOA
STA
LOA
STA
R"B
LOA
C"P
BCC
B03
LOI
R"B
LDA
BME
TBIT8
NOPAR
ABIT8
EYEN7
I$C6
1$10
LABEll
I$C3
I$IB
LABELl
UC2
I$IB
LABEll
UC7
1$10
LABEll
ABlT8
~OPAR7
uco
1$10
LABEll
1$&4
1$08
SCCR
DEFPRO
104
BDRATH
BDRATL
ROTATE
BDRATL
CNTACL
BDRATH
CNTAl
5,IER
BDRATL
IBAUD3-10
moo
103
5,PB
1$04
BD2
;
;
;
;
;
;
;
THE SA"E ?
YES=:) NO PAR ITY USED
NO ==) BIT 8 OF 'A' = 0 ?
YES'-) 7 BITS, EVEN PARITY, 2 STOP BITS
NO ::) 7 BITS, ODD PARITY, 2 STOP BITS
SET VALUE FOR 'RCVC' I 10 BITS/NORD )
I BRANCH AUAYS )
; SET VALUE FOR •RCVC'
i I BRA)
I 11 BITS/1I0RD )
i SEY VALUE FOR 'RCYC'
i I BRA )
I 11 BITS/NORD )
i SET VALUE FOR 'RCVC' I 10 BlTS/MORD )
j I BRA)
i IS BIT 8 OF 'A' • I ?
; YES'=) 7 BITS, NO PARITY
; NO ==) 8 BITS, NO PARITY
; SET VALUE FOR 'RCVC' I 10 BlTS/IlORD )
; I BRA)
;. SET VALUE FOR 'RCVC'
I 9 BITS/IIORD )
; SET UP SERIAL CO""AND RE6ISTER FDR
; BAUD RATE AND PROTOCOL [SAVE PRESENT PROTOCOL 1
i DIYIDE BIT-NIDTH mE BY 16
; TO BET BAUD RATE VALUE
; SET UP BAUD RATE TI"ER
;
i
;
;
;
;
i
;
DISABLE IRQS
DETER"INE WHAT BAUD RATE WE' RE RUNNIN6 AT
IS IT GREATER THAN 300 ?
YES:=) BRANCH
NO ==) BAUD = 300
SET 'HISPEED' TO 0 I lOW SPEED I
SET R2424 '"ODE' CODE I BELL 212A ASYNC I
I BRANCH ALIIAYS )
4-20
Application Note
0357
0358
0359
0360
0361
0362
0363
0364
0365
0366
0367
0368
0369
0370
0371
0372
0373
0374
F962
F964
F966
m8
F96A
mc
mE
F970
F972
F974
F976
F979
F97B
F97D
F9BO
F983
F985
F987
C925
9008
A20C
D7 01
A903
DO 06
A2 18
D7 01
A90D
8590
AD OA
2HO
0590
80 OA
AD OA
29F0
0590
BO OA
R6500/11 • R2424 Intelligent Modem Design
moo
B12
B24
BD2
10
10
20
20
C"P
sec
LDX
S"B
LDA
8NE
LOX
S"B
LDA
STA
LDA
AND
ORA
STA
LOA
AND
ORA
STA
IBAUDI2-10
B24
112
5,PB
1m
BD2
124
5,PB
I$OD
mp
RCVA
tsFO
mp
RCVA
X"TA
UFO
TEKP
X"TA
;
;
;
;
;
j
j
IS BAUD SREATER THAN 1200 ?
YES==> "UST BE 2400
NO ==> "UST BE 1200
SET 'HISPEED' TO 1 (HIGH SPEED )
SET R2424 '"ODE" CODE (BELL 212A ASYNC )
( BRA)
2400 BAUD
SET R2424 '"DOE' CODE (V.22 BIS ASYNC )
SAVE '"DOE" CODE IN TE"PORARY LOCATION
CHANSE 'KOOE" IN R2424 "DOE" RESISTERS
- CLEAR OUT PREVIOUS "ODE
- SET NEW "ODE
j - AND PROSRA" RECE I VER
; CHANSE TRANS"ITTER BAUD RATE .. ,
- CLEAR OUT PREVIOUS "DOE
j - SET NEW "ODE
; - AND PROSRA" TRANsmTER
j
;
;
;
;
PAGE 0008
0375
0376
0377
0378
037'1
0380
0381
F98A
F98D
F990
F993
se OC
10
8e OC 20
20 CBFD
8641
STY
STY
JSR
F995
F997
F778
D7 16
AND SET "OOEM
sn
RCVC
X"TC
NEWCIR
8AUD
; UPDATE R2424 RESISTERS WITH NEW VALUES
; SAVE BAUD CODE
SKB
S"B
7,IRIlFLS
S,SCSR
; SET ISR TO PROCESS DELAY mE FOR NAIT -FOR-CARRIER
; SET 'DATA RES E"PTY' FLAB FOR 'LAST BIT OUT'
PAGE 0009
0383
0384
0385
0386
0387
03B8
0389
0390
om
0392
0393
0394
0395
om
0397
0398
0399
0400
0401
0402
0403
; BAUD RATE OETER"INED. NON IN CO""AND "DOE. READ CO"KAND
; CHARACTERS INTD BUFFER ( INBUFF ). TERKINATE ON {CR>.
F999
mc
mE
nAO
F9A2
F9A4
F9A6
F9A9
nAC
F9AE
F9BO
F9B2
F9B4
F9B6
m8
F9BA
mc
7, REPFLS, REPEAT
100
SCSR
ISOF
WAlTlN
FF
A2
A5
29
FO
74 4B
00
16
OF
FA
BBS
SETPTR LOX
IIAITlN LOA
AND
A5
7F
20
C5
FO
C9
FO
90
C9
DO
A5
20
17
79 03
51 FF
89
10
20
EA
E8
7F
05
8B
51 FF
SRDR
SETCHR LOA
7, ECHoF6, mCOD
BBR
CHRoUT
JSR
S3
CTLtoD C"P
BEQ . 60TCHR
1$20
C"P
BED WAITIN
IIAlTlN
BCC
CKP I$7F
BNE
BS
LOA
SS
CHRoUT
JSR
BEQ
; BRANCH IF 'AI' RECEIVED
; 'AT' RECEIVED --> SET BUFFER INDEX TO 0
; CHECK RECEIVER STATUS
; NO BITS SET == > NO RECE I VED CHAR, TRY ABA I N
; SET CHAR FRoK RECE I VER BUFFER
; BRANCH IF ECHO DISABLED
; ECHO CHAR BACK TO HOST CO"PUTER
; IS CHAR A {CR> ?
; YES=: > SAVE IT AND PROCEED TO 'ALLIN'
; IS INCHAR A {SP> ?
; YES==> ISNORE IT
; CHAR IS LESS THAN $20 ( CONTROL CODE ) --> 16NORE IT
; IS IT A 'DELETE' CHAR? {-- RE"DVE THESE FOUR LINES IF THE
; NO == > CHECK FOR OS>
{-- {DELETE> KEY ON THE PARTICULAR
; YES==> CHAN6E IT TO {BS>
{-- TERKINAL USED IIITH THIS DESISN
; SEND OUT {BACKSPACE>
{-- BACKSPACES THE CURSOR.
4-21
II
Application Note
0404 F9BF
0405 F9Cl
0401t F9C3
0407 F9C4
040B F9C1t
0409 F9CB
0410 F9CB
0411
04l2F9CD
0413 F9CF
0414 F9D1
0415 F9D3
om F9D4
0417 F9DIt
0418 F9D8
0419 F9DA
0420 F9D8
0421
0422 F9DD
om F9EO
0424 F9E2
0425 F9E4
om
0427 F9E7
R6500111 • R2424 Intelligent Modem Design
C5 BB
DO OA
CA
10 DB
A920
20 51 FF
30 CF
BS
C"P
BNE
DELETE DEI
BPL
LDA
JSR
B"I
95 4C
C589
FO Ott
E8
EO 29
DO Cit
F7 75
CA
DO CI
BOTCHR STA
C"P
BEQ
INI
CPI
8NE
S"B
DEI
BNE
7F 75 07
A904
857D
4C EO FD
A200
;
;
;
I
;
55
60TCHR
IIAITlN
tf20
CHROUT
SETPTR
INBUFF
S3
ALLIN
IS IT A (BACK-SPACE) ?
NO -= > ACCEPT CHAR
YESa-> OVERIIRITE PREVIOUS CHAR IN BUFFER
BRANCH IF BUFF POINTER NOT LESS THAN 0
OUTPUT A (SP)
; mIT LOIlEST
,x
141
IIAITlN
7,BUFFL6
;
;
;
;
;
;
;
;
VALUE OF POINTER TO 0 ( BRA)
SAVE CHAR IN BUFFER
IS IT A (CR) ?
YES::) ALL CHARS RECEIVED
NO ==) INC POINTER AND BET NEXT CHAR
IS BUFFER FULL?
NO =.) 6ET NEIT CHAR
YES::) SET FLA& TO INDICATE ERROR
KEEP REABIN& UNTIL (CR)
( BRA)
MAITIII
I
ALLIN 88R
LDA
STA
J"P
7,8UFFLB,REPEAT
104
STCODE
CR
; BRANCH. IF 40 OR LESS CHARS READ IN
I TOO "ANY CHARS ENTERED --} ERROR
; SET STATUS CODE TO INDICATE ERROR
; AND TEDINATE COMAND STRINS
REPEAT LDI
100
; SET COMAND STRINS POINTER TO ZERO
PA8E 0010
0429
0430
0431
0432 F9E9
0433
0434 mc
0435 F9EF
0436 F9F2
0438
0439
0440
0441
0442
0443
0444 F9F5
0445 nF7
om F9F9
0447 F9FB
0448 F9FD
0449 FAOO
0450 FA02
0451 FA03
0452 FA05
0453 FA07
0454 FA09
I ALL CO"MNDS AND PARA"ETERS HAYE BEEN RECEIVED. NOlI EXECUTE
I EACH COMAND, IN ORDER, UNTIL (CR) DR UNRECOBNIZED C~MND (ERROR) •
20 F5 F9
20 F2 F9
4C E9 F9
ItC 9B DO
NIT~D
JSR
FIIDC"D
Doce
JSR
J"P
J"P
DOC"D
NIlC"D
(~DYEC)
;
;
;
;
FIND CORRESPONDINB SUBROUTINE ADORESS AND
SET UP JU", YECTOR
EXECUTE COMAND.
FETCH NEXT COMAND
TO COMAND ROUTINE.
;m
EACH C~MND ROUTINE ASSU"ES THE I-RE6 POINTS
TO THE CHAR IN 'IIIBUFF' FOLLOIIINB THE CO"MO
CHAR, AND LEAVES X-RES POINTlNB TO THE NEIT
C~"AND CHAR. THE Y-REB IS FREE FOR USE AS
A &ENERAL SCRATCH-PAD RE&ISTER.
AO 00
B54C
C589
FO OE
D9 47 FA
FO OB
C8
CO 21
DO Fit
A9 04
B57D
FNDC"D LDY
LDA
C"P
BEQ
LDDP2 C"P
BEQ
INY
CPY
BIlE
LDA
STA
100
INBUFF ,X
S3
BOCR
UDTBL,Y
FOUND
INU~"D
LOOP2
104
STCODE
; SET UP TABLE INDEX
; FETCH COMAND BYTE
I IS IT A(CR) ?
I YES") TEDIIiATE C~MO STRING
I NO •• ) A "ATCH FOUND?
; YES=-) BET YECTOR
; NO .0) TRY NEXT TABLE ENTRY
; END OF TABLE?
; 0 as) 60 ABAIN
I YES··} ERROR ...
4·22
Application Note
0455
04"
0457
0458
0459
0460
0461
0462
0463
0464
0465
R6500111 • R2424 Intelligent Modem Design
FAOI
AO 21
lID
FAOD
FAOE
FAOF
FAIO
FAI3
FAI5
FAil
FillA
FAil
98
OA
FOUND TYA
A&L
TAY
LDA
STII
LDII
ITA
1111
RTS
AI
.. 69 FA
85 91
.. 6A FA
859&
a
60
LDY
IllUllCIID
I SET POUlTER TO (CR) COMMID
II
I COIIIMD FDIlItD. BET ASSOCIATED VECTOR
I IIILT llIDEI IY 2
VECTIL,Y
CllDYEC
VECTBL.I,Y
CIIDVEC+I
; SET VECTOR
; AlII SET II' COIIIIAIID JIIIIP
; IIIC INBUFF INDEI TO POINT TO FIRST
I BYTE FOLLDNIII& COIIIIIIIID IYTE
PABE 0011
0467
0468
0469 FAIC
0470 FA1E
0471 FA20
0472 FA22
0473 FA24
0474 FA26
0475 FA28
0476 FA2A
0477 FA2C
0478 FA2E
0479 FAlO
04&0 FAll
0481 FA34
0482 FAl7
0483 FA39
0484 FAll
0485 FAlD
0... FA3F
0487
04. FA42
0489 FA44
0490
0491
0492
0493
PHIllIE IS RINSIII&. AllSIIER IT ?
57 12
07 10
MAO
85 14
A540
85 15
A5 42
85 18
A5 43
85 IA
119 02
857D
20 £8 FE
E6 87
M 87
C486
FO 03
4C 16 Fa
RI. . RIll
RIIB
F778
20 OD Fe
AllMR SIll
JSR
LDII
STA
LDII
STA
LDII
STII
LDII
STA
LDA
STA
JSR
INC
LDY
CPY
BEll
JIIP
..
; DISABLE IRQ
I RESET PlIO liP. IS RIII&III&" I FLAB
I SET ItCR FOR SERIAL 110
5,IER
O,IFR-l
Q
DEFPRO
I SET SERIAL PRDTOCDL TO RDST RECENT VALUE
8DRATL
CNTACL
llRATH
CNTAL
1$02
I SET SERIAL CLOCK TO IIIIST RECENT VALUE
m
I SET "STCODE" TO "RIIIS" RESPONSE
STCODE
11ESP115
SI
51
SO
ABER
REBTRT
I AND OUTPUT APPRDPRIATE MSIASE
j ADD I TO RillS COUIITER
I • CHECK FOR RINS COUNT
I IS THE RINS COUIIT UP TO THE SET LlIIIT YET '1
I YES-a) &0 ANSIIER THE PHOIIE !
I NOaa) STMT OYER READINS IN CHARS FRDII HOST smEll
7,IRIIFLI
I CH_ ISH TO PROCESS DELAY TIllE FOR NAIl-FOR-CARRIER
I • &0 AllSllER PHOIIE I "Jsa" MILL PUT 2 RETURII
I ADDRESS IYTES ON THE STACK. THESE MILL BE
I DISCMDED AT THE EIID OF THE (CR) COIIIIAIID
I - AT LABLE "IIIIIAIT" -- FOLLDllED BY
A I JIIP RESTHT" I
AlIA
PAlE 0012
0496
0497 FM7
0498 FA48
0499FA54
0500 FA57
0501 FA5D
0502 FA63
0503 FA6I
2C
30
38
41
49
53
00
I
CllDTBL •BYT
.IYT
.IYT
.IYT
.BYT
.m
.IYT
,
--- THE ORDER OF THESE TIIII TABLES RUST IIATCH ----
·01234"7.... ·'
'38,'·'1'
'ACDEFH'
'IIIIIPIIR'
'STVn'
SOO
I MRKER FOR (CR) COIIIAND
4-23
•
Application Note
0504
0505
0506
0507
0508
0509
OSlO
0511
0512
FA69
FA68
FA77
FA83
FA89
FA95
FAAI
FAA8
IE FB
3C FB
3C FB
5B F8
00 FC
88FC
3UD
EO FD
R6500/11 • R2424 Intelligent Modem Design
YECT8L .NOR
.IIOR
.IIOR
•NOR
.IIOR
.IIDR
.IIOR
.IIOR
COIIIIA
DI61T ,DIBIT ,DISIT ,DIBIT ,DIBIT ,DI6lT
DI6lT ,Dl6IT ,DIBIT ,DI6lT ,Dl6IT ,DI6lT
SEll I C, EQUAL, QUESTN
AAA,CCC, DDD,EEE,FFF ,HHH
II I ,""",OOO,PPP ,QQQ,RRR
SSS,TTT ,YVY ,XIX I ZIZ
j •••• _._._) IIUST BE LAST ENTRY IN TABLE
CR
0513
0514
0515
0516
0517 FAAD
0518 FAB2
om FAB6
0520 FASA
0521 FASD
INITIAL VALUES FOR S-RESISTERS, IN ORDER FROII 0 TO 16
STBL
00
08
06
FF
00
.BYT
.m
.BYT
.BYT
.BYT
0,0,43,13, 10
8,2,30,02
6,7,70,50
$FF ,$FF ,$FF
0
PA6E 0013
0523
0524
0525
0526 FABE
0527 FACO
052B FAC2
0529 FAC4
0530 FAC7
0531 FACA
0532 FACC
0533 FACF
0534 FADI
0535 FAD4
0536 FAD7
0537 FAD9
0538 FADC
0539 FADF
0540 FAE2
0541
0542 FliES
0543 FAE7
0544 FAE9
0545 FAE8
0546 FAED
0547 FAEF
0548 FAFI
0549 FAF3
0550 FAF5
0551 FAF7
0552 FAF9
0553 FAFB
0554 FAFD
0555 FAFF
0556 FBOI
THIS ROUTINE INITIALIZES PR06RAII YARIABLES AND
CPU RE6ISTERS.
A900
B5 11
85 12
80 00
80 OB
A904
80 OD
A903
BD Oil
BD OA
11908
BD OC
80 OC
80 OE
BD OE
A900
8583
8587
857F
85 76
8578
A980
8579
85 7A
857E
B5 7C
AnF
8542
A900
85 43
20
20
10
10
20
10
20
10
20
INlTSli LOA
STA
STA
STA
SlA
LDA
STA
LOA
STA
STA
LDA
STA
STA
STA
STA
LDA
STA
STA
STA
STA
STA
LDA
STA
STA
STA
STA
LOA
STA
LOA
STA
1$00
IFR
lEft
IIlTD
mB
1$04
RCYD
1$03
RCYA
IIITA
1$08
RCYC
IIITC
RCYE
IIITE
100
SSETFB
SI
ICOOE
DILFLB
RSLTF6
1$80
ECHOF6
DUPLEX
YCODE
SPKRF6
IBAUD12
BDRATH
; 0I SABLE ALL I RDS
; SET UP R2424 TO DEFAULT VALUES
j
;
;
;
;
;
SET FLAB TO INDICATE SoRES HAS NOT BEEN SET
SET RIN6 COUNT TO 0
STANDARD 'CARRIER' RESPONSE
DISABLE DIALIN6
ENABLE RESULT RESPONSE
ENABLE ECHO
; FULL DUPLEX
; SET UP FOR YERBAL RESPONSE
; SET SPEAKER FOR 'III' COIIIIAND OPERATION
j SET DEFAULT BAUD RATE TO 1200 BAUD
4-24
R6500/11 • R2424 Intelligent Modem Design
Application Note
0557
0558
0559
0560
0561
0562
0563
0564
0565
0566
0567
0568
0569
0570
0571
FB03
FB05
FB07
F809
F808
FBOD
F80F
FBII
FB14
FB16
FB17
FB19
FB1B
FB1D
M CO
B5 40
A986
8584
A900
8585
AOU
89
91
88
10
A5
B5
60
AD FA
84
F8
89
4C
LDA
STA
LOA
STA
LOA
STA
LDY
SLOOP LOA
STA
DEY
BPl
lOA
STA
RTS
.FIlE
I$CO
DEFPRO
; SET DEFAULT SERIAL PROTOCOL TO B BITS, NO PARITY
1(50
SREBP
1>50
SRE6PH
117
STBl, Y
(SRESP), Y
; BASE POINTER FOR S-RESISTERS
SLOOP
S3
INBUFF
; SET UP HI6H-BYTE OF S-REB POINTER
; INITIALIZE S-REGS
; INITIALIZE CO""AND STRING TO [NUlLl
"D"10B
PAGE 0014
; THE FOllOIlING ARE All THE COft"AND ROUHNES TO EXECUTE THE
'AT' COftftANDS ....
0573
0574
0575
0576
0577
',' CO""AND
--- NA IT FOR ONE PAUSE mE
0578
0579
05BO
0581
0582
0583
0584
0585
0586
0587
0588
0589
0590
0591
0592
FBIE
FB20
FB22
FB24
FB26
FB28
FB2A
FB2C
FB2E
FB31
FB33
FB34
FB36
FB37
0593 FB39
om Fl3B
0595
0596
86 911
AD BE
FO 15
Anc
B5 IC
AHO
B5 IE
AO 10
SUFI!
A5 IC
88
DO F8
CA
DOF3
AD 90
60
CO"ftA STI
LOX
BEQ
lOA
STA
lOA
STA
ONESEC lDY
NAlTB BBR
LDA
OEY
BilE
DEX
BNE
.ODlAY LDX
RTS
TE"P
S8
NODlAY
I(OLYTl"
CNTBCl
I>DLYm
CNTBHl
IDLYHIB
5,IFR,NAITB
CHTBCl
IIAITB
ONESEC
TEftP
; SAVE INBUFF POINTER
; GET VALUE OF S-REG 8 ( DELAY TI"E )
; IF ZERO THEN NO DELAY
; START TlftER-B
;
;
;
;
;
I
;
IS mER B DONE YET ?
YES == > CLEAR liftER FLAG
DONE COUNTING YET ?
NO ==) KEEP 60lN6
ANY "ORE I-SEC DELAYS ?
YES::) ONE "ORE mE ....
RESTORE INBUFF POINTER
; tfftftttttttttttttttttttttttttttttttttttttftttttttttfttttttt.ttt...t.tt....ttt
0597
0598
0599
0600
0601
0602
0603
0604
0605
0606
0607
0608
0609
; DIAL A NU"BER
FB3C
FB3F
FB41
FB44
FI46
7F
A9
2C
FO
B5
76 15
01
OE 20
FB
4B
DIGIT BBR
LDA
MAITRE BIT
BEQ
LDA
7,DILFL6,016ERR
1$01
X"TE
IIAITRE
INBUFF-1,X
; IF NU"BER I S NOT TO BE DI ALEO --) ERROR
; MAlT UNTIL DIAL BUFFER EftPTY
; SET ASCII NU"BER FRO" BUFFER. IN THIS CASE, THE
CO""AND BYTE IS THE PARA"ETER. SINCE THE X-REG
HAS ALREAOY BEEN UPDATED TO POINT TO THE BYTE
FOLLONINS THIS DI61T ICO""AND, THE BASE OF THE
COft"AND BUFFER HAS TO BE SHIFTED DOliN ONE BYTE
4-25
II
Application Note
0610
0611
0612
0613
0614
0615
0610
R6500111 • R2424 Intelligent Modem Design
FB48
FB4A
FB4C
FB4E
FB50
FB53
C923
DO 02
A90E
29 OF
8D 00 20
60
CI'IP
BNE
LDA
DIG2 AND
STA
QDIGIT RTS
0618 FB54
0619 FBS6
0620 FB58
0621
0622
A9 04
8570
4C EO FD
DISERR LDA
STA
J"P
....
;
;
;
;
;
DI62
mE
I$OF
mo
TO COI'IPENSATE.
IS THE DIAL DIGIT A 't' ?
NO ==) BRANCH
YES:=) EXCHAN6E CHAR FOR R2424 'S 't' NUI'IBER
!'lAKE IT ABSOLUTE
AND DIAL •••
0617
om
; SEI'IICOLDN CDI'II'IAND
F85B
FB5E
FB60
FB62
FB65
FB67
FB69
; TERI'IINATE CO""AND STRINS PROCESSING
; fftftfffftftftftfffffffffftf""fftffftffffHtttfffftfffff*tfffffHHfftftffff
0623
0624
0625
0626
0027
0628
0629
0630
0631
0032
'ERROR'
104
sreODE
CR
7F
06
A9
2C
FO
A9
80
76 11
76
01
OE 20
FB
FF
00 20
SE"IC BBR
ASL
LDA
sm2 BIT
BEQ
LDA
STA
---
DDNE DIALING - RETURN TO CO""AND "ODE
7,DILFLG,SEI'IERR
DILFLG
.01
xm
5EI'I12
UFF
mo
;
;
;
;
;
;
BRANCH IF ';' ENTERED WHILE NOT DIALING (ERROR)
TURN OFF DIAL FLAG ( $80 --) $00 )
MAlT UNTIL DIAL RE6ISTER IS E!'IPTY
E"PTY YET?
NO ==) KEEP WA 1Tl NS
YES=-) FINISH DIALING
PAGE 0015
0/,34 FB6C
om FB6E
0636
0637
0638
om
0640
0641
0642
0643
0644
0645
064b
0047
0648
064~
0650
0651
0652
0653
0654
0655
0656
0657
0658
0659
0660
FB6F
FB7I
FB73
77 80
60
A904
857D
4C EO FD
R!'IB
RTS
mm LDA
STA
J"P
7,MAlTF6
; PREVENT (eR) CO"I'IAND FRO" 60lN6 ON-LINE (RE"AIN IN
; CO"I'IAND "ODE)
1$04
STCODE
CR
; SET STCODE FOR ERROR
; •• , AND TERmm COI'II'lAND STRING EXECUTION
; fftttftffffffffffftftffftfffffffffffff"ffffffffffffffttffttfffffffffftfffftff
; ':' CO""AND
F876
FB79
FB7B
FB7D
FB7F
F8S1
FB84
FBB6
FBSS
FBB8
FB8D
FBBF
FB91
FB93
FB96
FB98
7F 8lOB
A900
8598
8599
85911
20 8E FD
8036
859B
20 BE FD
BO 15
A4 9B
84 99
8598
20 8E FD
800A
A499
EQUAL BBR
LDA
STA
STA
STA
JSR
BCS
STA
JSR
BCS
LDY
STY
STA
JSR
BCS
LOY
---
SET S-RESISTER TO A VALUE
7,SSETF6,DI6ERR
100
NU"
NU"+I
NUII+2
smull
EQ4
NU"
GETNU"
EQ2
NUI'I
NU"+I
NUll
6ETNU"
EQ2
NUI'I+1
; IF FLAG IS CLEAR --) 'ERROR'
; CLEAR OUT TEIIP BUFFER
j SET FIRST CHAR FROII BUFFER
; IF IT IS NOT A NU"BER, THEN ASSU"E ZERO
j SAVE NU"BER IN TE"P BUFF
; IS THERE ANOTHER NUIIBER ?
; NO ==) ONES DIGIT ONLY --) BRANCH
; YES==) "DYE ONES DI6IT OVER
AND INSERT TENS DIGIT
j IS THERE A THIRD NUIIBER ( HUNDREDS DIGIT) ?
; NO ==) ALL NU"BERS FETCHED --) BRANCH
; YES==) IIOVE ONES AND TENS DISlTS
4-26
Application Note
0661
0662
0663
01164
0665
0666
0667
01168
0669
0670
0671
om
om
FB9A
mc
FB9E
FBAO
FBA2
FBA4
FBA6
FBA9
FBAB
FBAD
FBAF
FBBI
FBB4
FBB7
FBB8
F8BA
FBBC
FBBE
FBCO
FBC2
FBC4
FBC6
FBC8
FBCB
FBCE
FBDO
FBD3
FBD6
0674
0675
0676
0677
0678
0679
0680
0681
0682
0683
0684
0685
0686
06B7
068B
0689
0690 FBDB
0691 FBDA
0692 FBDD
0693 FBEO
0694 FBE2
849A
A498
8499
B598
A599
FO 07
20 EC
6598
8598
A59A
FO OB
20 EC
20 EC
18
6598
8598
A598
AO 00
91 B4
A596
DO 12
A9EF
20 OA
80 OA
A9EF
2D OA
80 OA
DO 10
FB
FB
FB
10
10
20
20
A9 10
00 OA 10
80 OA 10
A9 10
ODOA20
R6500/11 • R2424 Intelligent Modem Design
STY
LOY
STY
STA
EQ2
LOA
BEQ
JSR
ADC
STA
EQ3
LOA
BEQ
JSR
JSR
CLC
ADC
STA
EII4
LDA
LOY
STA
LDA
hE
NoSLFT LOA
AND
STA
LOA
AND
STA
BNE
NUN
NW
NUN
100
(SRE6P), Y
516
SLFTST
I$EF
RCVA
RCYII
UEF
mA
XNTA
QEQ
SLFTST LDA
ORA
STA
LOA
ORA
ISIO
RCVA
RCVA
1$10
X"TII
OVER AND INSERT HUNDREDS
DIBIl IN FRONT
NU"+2
NU"
NUN+l
NU"
NU"+1
; BET TENS DIBIT
I IBNORE IT IF IT' S ZERO
; IF ) 0 , NULTIPLY BY 10
; ADD IN ONES DIBIT
; AND SAVE TENS+DNES
I BET HUNDREDS DI6lT; IS IT = 0 ?
I YES=-) FINISHED CDNYERTINB TO HEX
; NO n) NULTlPLY HUNDREDS DIBlT BY 10
AND BY 10 ASAIN ( t 100 )
EQ3
"ULT10
NUN
NU"
NUN+2
EQ4
NULT10
"ULT10
; ADD IN TENS+ONES DI6lT
; SAVE TOTAL HEX VIILUE
I 60 TO SELF -TEST ?
I NO => STOP SELF TEST
; ND SELF TEST -- RETURN TD NOR"AL oPERATlN6
; DISABLE SELF-TEST BITS IN R2424
~DE
; ( BRANCH ALMAYS )
; START SELF-TEST
; SET SELF-TEST BITS IN R2424
PIISE 0016
0695 FBE5
0696 FBE8
0697 FBEB
0698
0699 FBEC
0700 FBEE
0701 FBEF
0702 FBFO
0703 FBF2
0704 FBF3
om
0706
0707
0708
0709
0710 FBF4
0711 FBF7
BD OA 20
20 CB FD
60
IIEII
85 90
Oil
Oil
65 'Ill
OA
60
NUL TIO STA
ASL
ASL
ADC
ASL
RTS
STA
JSR
RTS
I"TII
NEweXR
mp
A
A
Tm
A
; UPDATE R2424 SCRATCH-PAD RESISTERS
;
;
;
;
;
SAVE VALUE IN TEftP STORASE
NULTIPLY BY 2 ( t 2 )
AND BY 2 ABAIN ( t 4 )
THEN ADD IN oRISIMAL VALUE (CARRY FLA6 ALIIAYS CLEAR )
NULTIPLY BY 2 A6AlN ( t 10 )
; tttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttt
; '?' CoN"AND
20 40 FF
AO 00
QUESTN JSR
LOY
---
CRLF
100
SEND BACK CONTENTS OF S-RE6ISTER
; PREFACE OUTPUT IIlTH (CR/LF)
4-27
II
Application Note
0712 FBF9
0713 FBFB
0714 FBFE
0715 FCOO
0716 FC03
0717 FC06
0718 FC07
0719 FC09
0720 FCOC
0721
0722
0723
0724
0725
0726 FCOD
0727 FCIO
0728 FCI2
0729 FCI5
0730 FCIS
0731 FCIA
0732 FCID
0733 FC20
0734 FC23
0735 FC25
0736
0737
0738
81 S4
20 9F FD
AO 02
BHS 00
20 51 FF
SS
10 F1
20 40 FF
60
R6500/11 • R2424 Intelligent Modem Design
LDA
JSR
LDY
QUES3 LDA
JSR
DEY
BPL
JSR
RTS
(SRE6PI, Y
HI2ASC
102
MU",Y
CHROUT
I
;
;
;
6ET VALUE OF S-RES
AND CONYERT IT TO ASCII
SEND OUT 3 CHARS
6ET CHAR FRO" 'NUN' BUFFER
I LAST CHAR?
; NO s: > SEND OUT NEXT ONE
QUES3
CRLF
; YES") SEND OUT (CR/LF)
1·lfffff.. ttffffffftffttUUU..f ...ffU.....ffllff.....ffftftltftftltlftl..ttf
; 'A' CO"NAND
20 95
All 10
OD OD
SD OD
All DF
20 09
8D 09
20 CE
F7 80
4C EE
FC
AM
20
20
20
20
FD
FD
JSR
LOA
ORA
STA
LOA
AND
STA
JSR
S"8
J"P
---
SET "ODE" TO ANSIIER AN INCO"IN6 CALL
HIAN02
1$l0
; PICK UP PHONE ( 80 OFF -HOOK I
I SET R2424 TO ANBIIER NODE
I"TD
I"TO
IfDF
xm
xm
NEIICX
7,MAITFS
CR2
; SET 'OR6' BIT TO 0
;
;
I
;
UPDATE R2424 STATUS
SET FLAB TO INDICATE liE lIRE TO MAlT FOR CARRIER
AND SO DIRECTLY TO CARRIER-DETECT
-- DO NOT ACCEPT ANY NORE CO""ANDS
1··ttltltltltlttftfttlft.tflltffltltftUlltlffftf...ItUUUUfffffHtfH.ft...
om
I 'C' CONNAND
0140
0741
0742
0743
0744
0745
0746
0747
0748
om
0750
0751
0752
0753
0754
0755
FC28
FC2S
FC2D
FC2F
FC31
FC34
FC36
FC38
FC3A
FC3D
FC40
FC43
20 SE FD
BO 08
FO 09
A904
000920
DO 07
DO 05
AHB
20 09 20
SD 0920
20 CE FD
60
CCC
JSR
BCS
BEll
CCONE LOA
ORA
BNE
BHE
CCIERO LDA
AND
IICCC STA
JSR
RTS
--- TOO6LE TRANS"lTTER
6ETNU"
CCZERO
CCZERO
104
I"T9
IICCC
QCCC
UFB
X"T9
X"T9
NUCX
;
,
I
;
SET PARANETER, IF ANY
BRANCH IF NO PARA"ETER ( ASSURE ZERO I
BRANCH IF PARA"ETER = 0
PARA"ETER =1 --) TURN ON 'CC' BIT
; IN "ODE" RE6ISTER
I ( BRANCH ALWAYS I
I PARANETER =0 --) TURN OFF •CC· BIT
; UPDATE "ODEN RESISTERS
PA6E 0017
11t··f..ttt.ltlftlfl....tt..t.lttfftltftttttlttttttttttttt....ftttt ......I ..UI
0756
0757
0758
0759
0760 FC44
0761 FC46
0762 FC49
A9 20
00 09 20
80 09 20
DOD
LDA
ORA
STA
1$20
X"19
1m
; PUT "DDEN IN DRI61NATE "ODE
I AND SET TO DIAL
4-28
R6500/11 • R2424 Intelligent Modem Design
Application Note
07113
07114
0765
0766
0767
0768
0769
0770
0771
0712
0173
0774
0775
0776
0777
0718
om
0780
0781
0782
07B3
0784
0785
0786
0787
0788
0789
0790
0791
0792
0793
0794
0795
0796
0797
0798
0799
0800
0801
OB02
OB03
0804
0805
OB06
OB07
080B
0809
OBIO
0811
0812
0813
0814
0815
0816
FC4C
FC4F
FCSI
FC53
FC56
FC59
mc
FC5E
FC60
FC61
FC63
FC6S
FC68
FC69
FC6B
FC6D
FC6F
FC71
AD 00 20
29EF
0948
8D 00 20
20 CEFD
2C 08 20
10 FB
AS 8E
48
A58C
858E
20 IE FB
68
858E
F776
F7 SO
7777
60
LOA
AND
ORA
STA
JSR
IIAITDL BIT
BPl
lOA
PHA
lOA
STA
JSR
PlA
STA
SftB
SftB
RftB
RTS
IftTO
UEF
1$48
IftTD
NEMCX
XftT8
IIAnDl
58
I SET CRQal AND OTR:I
I UPDATE TRANSftlTTER RE61STERS
; itA IT UNTIL OLD-I
I DELAY '56' NUftBER OF SECONDS. USE 'CllIIftA'
CoftftAND FOR DELAY ROUTINE. TO DO THIS, liE HAVE TO
SAVE THE ORISINAl YAlUE OF 'SB' ( 1M THIS CASE ON
THE STACK ) AND THEN SUBSTITUTE THE VALUE FOR '56'
INTO '58'. THIS Mill DELAY 'SIt' SECONDS. AFTER
THE DELAY IS FINISHED, liE POP THE ORl&INAl 'SS'
; YALUE OFF THE STACK AND RETURN IT TO '58'.
; SET 'DIAL FlAS' TO DIAL SUBSEQUENT NUftBERS
; ENABLE IIAIT-FDR-CARRIER DELAY
I SET FOR NoRftAl DIAlIN6
56
S8
CoftftA
58
7,DllFLS
7,MAITFS
7,REYFl6
; ttttttttttttifififtttftttifttttttiftfttfttifttfffftfiffftfftfifftfftfftftftftf
; 'E' COMAND
FC72
FC7S
FC77
FC79
FC7B
FC7D
FC7F
208EFD
8006
FO 04
F779
DO 02
77 79
60
EEE
JSR
BCS
BEQ
EONE SftB
BNE
EZERO RftB
QECHO RTS
---
ToSSLE ECHO INS CHARS BACK TO HOST SYSTEft
6ETNUft
EZERo
EZERO
7,ECHOF6
QECHO
7,ECHOFS
;
;
;
I
;
;
6ET PARAftETER, IF ANY
BRANCH IF NO PARAftETER ( ASSUftE ZERO)
BRANCH IF PARAftETER = 0
SET ECHO FLAS
( BRA)
CLEAR ECHO FLA6 ( NO ECHO )
; ffttfftttfttttttfftffttttftfttfttttftttfftftffttftftffttttttttfftttfttttfttftf
; 'F' COftftAND
FC80
FC83
FC8S
FC87
FC89
FCBB
FC8D
208EFD
BO 06
FO 04
F77A
DO 02
77 7A
60
FFF
JSR
8CS
BEll
FONE SftB
BNE
FZERO RftB
IIFFF RTS
---
SET HALFIFULL DUPLEX
;
;
;
;
;
;
SETNUft
FZERO
FIERO
7,DUPLEI
QFFF
7,OUPlEX
6ET PARAftETER, IF ANY
IF NONE, ASSUftE ZERO
BRANCH IF = 0
SET FOR FUll DUPLE I
( BRANCH ALIIAYS )
SET FOR HALF DUPLEX
; ftfttfftlfftftftfftftftftifftftftftttftftfftiffttiftiffttftfiftftt**fifffftftt
; 'H' COftftAND
FC8E
FC91
FC93
FC95
20
80
FO
AD
BE FD
14
12
00 20
HHH
JSR
BCS
BEQ
HIAND2 lOA
FC9B
FC9A
0940
BD 00 20
ORA
STA
--6ETNUft
HHZERO
HHZERo
IftTD
1$40
IftTD
ON/OFF HOOK
;
;
;
;
;
6ET PARAftETER, IF ANY
IF NO PARAftETER, ASSUftE ZERO
BRANCH IF PARAftETER = 0
PARAftETER ftUST BE I OR 2 (ON THE R2424, THEY
FUNCTION THE SAftE)
; SET 1m CRQ = 1
4-29
•
Application Note
R6500/11 • R2424 Intelligent Modem Design
PAlE 0018
0817 FC9D
0818 FCAO
0819 FCA2
0820 FCA5
0821 FCA7
0822 FCAA
0823 FCAC
0824 FCAF
082:1 FC82
0826 FCB4
0827 FC87
0828 FC8A
0829
0830
0831
0832
0833
0834
0835 FCBB
0836 FCBE
0837 FCC I
0838 FCC3
0839 FCCS
0840 FCC7
0841 FCC9
0842 FCC8
0843 FCCE
0844
0845
0846
0847
0848
0849
0850 FCCF
0851 FCDI
0852 FCD4
0853 FCD6
0854 FCDB
08:15 FCDA
08:16 FCDC
08S7 FCDE
08:18 FCEO
0859 FCE3
0860 FCES
0861
0862
0863
0864
0865
0866
0867
0868 FCE6
CB69 FCE9
0870 FCEB
AD OD 10
09 40
aD OD 10
DO 10
AD OD 20
29 AF
8D OD 20
AD OD 10
298F
8D OD 10
20 CBFD
itO
RCYD
1$40
RCYD
HHSET
mD
ISAF
INTD
RCYD
I$8F
RCVD
NEIICIR
lOA
DRA
STA
BNE
HHZERO LOA
AND
STA
LDA
AND
STA
HHSET JSR
aHHH RTS
I SET RCY CRII • 1
I ( BRANCH ALIIAYS I
I 60 OFF-LINE (HANS UP I
; SET 1m CRII • 0
; SET RCY CRII • 0
; UPDATE NOD~'S INTERNAL RE61STERS
; tttttttttttttttttttttfffffffffffffffttttffttfffftfttftttfftftftttHtlltttttttt
; 'I' COMAND
20
20
BO
FO
AO
40 FF
BE FD
06
04
2D
DO 02
AO 31
20 33 FF
60
1Il
JSR
JSR
BCS
BEll
nONE LDY
BNE
lIZERO LDY
1111
JSR
---
RESPOND IIITH CHECKSUN DR PRODUCT CODE
CRLF
SETNUN
IIlERO
IIZERO
ICHKSUN-NS6
;
;
;
;
;
NOVE DOliN TO NEXT LINE
BET PARA~TER, IF ANY
BRANCH IF NO PARAftETER ( ASSUftE ZERO I
BRANCH IF PARANTER • 0
SEND OUT CHECKSUN
1111
mODE-",6
NS60UT
; SEND OUT PRODUCT CODE
RTS
; ttffttttftlfttftffttHtftffftffffffttftfttftffftttHfftfftttffttttfttlttffttlf
; 'ft' CDftftAND
n 7C
20
BO
FO
C9
DO
F7
67
4C
E7
60
BE FD
OD
08
01
02
7C
01
E5 FC
01
ftM
RNB
JSR
BCS
BEll
CftP
BNE
IIIIIINE SN8
MTIIO 08
JftP
MIERo 6ft8
11M" RTS
---
ENABlE/DISABLE SPEAKER
7,SPKRF6
BETNUN
""ZERO
"NZERO
101
""TIIO
7,SPKRFS
6,PB
I DISABLE SPEAKER FLAB
I' BET PARA~TER, IF ANY
; IF NDNE, ASS. ZERO
I 8RANCH IF • 0
I IS IT ONE ?
; NO •• > LEAVE SPEAKER FLAB DISABlED
; YES•• >ENABlE FLAB TO TURII SPEAKER OFF AT CARRI,"" rDIIE
I TURN ON SPEAKER
11M"
6,PB
; DISABLE SPEAKER
; ttHfttfftfttftffttfttltftlttfttttftfftftftttfttttttttHtittHHttttftftffffH
; '0' Co"ftAND
20 95 FC
F7 80
4C F6 FD
000
m
S"8
J"P
---
60 ON-LINE
HIAND2
7, IIAITFS
CARTlft
I PICK UP PHONE (60 OFF-HOOK I
I ENABLE CARRIER TEST
; AND &0 DIRECTLY TO CARRIER-DETECT •••
4-30
Application Note
0871
0872
0873
OB74
0875
08" FCEE
OB77 FCFI
R6500/11 • R2424 Intelligent Modem Design
; •••••••••tt••• Htt ••••••••••••tt•••••••• tt••tt•• tttt •• tt •••••tt ••••tttt.ttH ••
; 'P' COMAIID
AD OB 20
29 FD
PPP
LDA
AIID
---
PULSE DIAL
; SET PULSEITDIIE BIT TO 0
1m
ISFD
PASE 0019
087B
0879
0880
08BI
0882
0883
0884
0885
0886
0887
0888
0889
0890
0891
0892
0893
0894
0895
0896
0897
0898
0899
0900
0901
0902
0903
0904
0905
0906
0907
0908
0909
0910
0911
0912
0913
0914
0915
0916
0917
0918
0919
0920
0921
FCF3
FCF6
FCF9
STA
JSR
RTS
BD 08 20
20 CE FD
60
I"TB
; UPDATE TRANS"ITTER RE61STERS
NEMCl
; ••tt.ttttttt.tttttttt.tt.tttti.ttttttttttttttttt.ttitt.tttttttttttttttitttttt.
---
I 'g' CDMIIIID
FCFA
FCFD
FCFF
FOOl
FD03
FOO5
FD07
20 BE FD
DO 06
FO 04
F77B
DO 02
77 7B
60
aaa
JSR
BCS
BEll
IIIIONE S"B
BIlE
OOZERO R"B
lIa
RTS
TD&&LE SEND INS RESULT CODE/"ESSA6E
SEiNUft
gaZERO
III1ZERO
7,RSLTF6
110
7,RSLTFS
;
;
;
;
;
;
6ET PllRAftETER, IF ANY
BRANCH IF NO PARA"ETER ( ASSUftE ZERO I
BRIIIICH IF PARAftETER s 0
SET FLAS (ENABLE PRDftPTS I
( BRill
CLEAR FLAS (DISABLE PROftPTS I
; tttttttttt.tttt.ttttttttttttttttttttttttttttttttttt.ttttttt.ttttttttttttttttt.
I 'R' COMIIND
FD08
FDOB
FOOD
FDOF
7F
A5
C9
FO
76 28
41
IB
21
RRR
BBR
LDA
CftP
BEO
SET DIAL FOR REVERSE RODE
---( TO DIAL
lIN ORI6IN11TE-ONLY RODEft I
7,DILFLS,RERROR
BAUD
124
ORRR
; 8RANCH IF 'R' ENTERED IIHILE NDT DIALINS (ERRDR)
; ARE lIE RUNNIN6 AT 2400 BAUD?
; YES•• ) 'REVERSE' "ODE NDT EASILY DONE AT 2400 SINCE
'ANSIlER' TOilE SOES AWAY AFTER 3 SECONDS.
; NO •• >30011200 --) DISABLE FURTHER DIALINS
; SET FLII& TO INDICATE REVERSE DIALINS
; SET 'DRS' BIT TO 1
;
FDII
FD13
FD15
F017
FD1A
FOlD
FDIF
FD22
FDlS
FD27
FD2A
mc
FD2F
FD32
77 76
F777
A920
OD 09
80 09
A98F
2D OD
80 00
At BF
2D OD
09 20
8D OD
20 C8
60
FD33
FD35
FD37
A904
857D
4C EO FD
20
20
10
10
20
20
FD
IIRRR
RRB
SR8
LOA
ORA
STA
LDA
AND
srA
LDA
AND
ORA
STA
JSR
RTS
RERROR LDA
STA
J"P
7,DILFLS
7,REYFLS
1.20
1"19
I"T9
I$8F
RCVD
RCVD
I.IF
1m
1$20
I"TD
NEWCIR
1$04
STCODE
CR
; SET RECEIYER' S 'CRO' BIT TO 0
; SET TRANSRITTER'S 'CRa' BIT TO 0
;
AND 'DATA' BIT TD I
; UPDATE RESISTERS
I AND RETURN .....
; SET STCDDE FOR ERROR
AND TmlNATE CO""AND STRIN6 EXECUTION
4-31
•
Application Note
R6500/11 • R2424 Intelligent Modem Design
0922
om
0924
0925
0926
0927
0928
0929
0930
0931
0932
0933
0934
0935
0936
0937
0938
; •••tt.H.tt.fttt.U....U.fU••U ••ttftttttf.ftftUUttfttt........ftffftftf ..
; 'S' COMAND
FD3A
me
FD3E
FD41
FD43
FD45
FD47
FD4A
FD4C
FD4E
FD50
FD52
A986
8584
208EFD
BO 14
FO 12
B5 98
208EFD
BO 04
69 OA
859B
AS 9B
18
SSS
SS2
LDA
STA
JSR
BCS
BEg
STA
JSR
BCS
ADC
STA
LDA
CLC
---
IDENTIFY S-REGISTER FOR FUTURE ACCESS
1<50
SRESP
GETNU"
9SSS
9SSS
NU"
GETNU"
SS2
110
NU"
NUK
; START IIITH BASE ADDRESS
;
I
;
i
;
;
;
GET NU"BER OF S-REGI STER
BRANCH IF NO PARA"ETER FOUND
BRANCH IF PARA"ETER = 0 ( ALREADY SET UP )
SAVE VALUE
BET DNES DIGIT, IF ANY
BRANCH IF ONLY ONE DIGIT
TENS DIGIT COULD ONLY BE A 't'
PASE 0020
0939
0940
0941
0942
0943
FDS3
FDS5
FD57
FDS9
6584
8584
F783
60
om
0945
0940
0947
0948
0949
0950
0951
0952
0953
0954
0955
0956
0957
0958
0959
0960
0961
0962
0963
0964
0965
0966
0967
0968
0969
0970
0971
0972
9SSS
ADC
STA
SRB
RTS
SRE6P
SREGP
7,SSETF6
I ADD IN BASE ADDRESS
; AND STORE IN POINTER
; SET FLAG TO INDICATE AN S-REG HAS BEEN SET
; .....ftfftftfftftft.....ftfftftftf.ft...ttft.tt..ttftftftfffft.ftft.ftft.ftfft
; •T' CO"KAND
FD5A
FD5D
FDSF
FDa2
FD65
AD OB 20
0902
8D OB 20
20 CEFD
60
TTT
LOA
ORA
STA
.SR
RTS
---
TOUCH-TONE DIAL
1m
; SET PULSE/TONE BIT TO 1
1$02
IRTB
NEIICI
; UPDATE TRANSKlTTER REGISTERS
; fttfft ..fftftftU....fft.ftftf..fftftftfftfUUf.ftUftf.ffftftfft.ft.ttft....
; 'V' CORKAND
FD66
FD69
FD6B
FD6D
FD6F
FD71
FD73
208EFD
BO 06
FO 04
F77E
DO 02
77 7E
60
YVV
JSR
BCS
BEQ
VONE SKB
BNE
VZERO RKB
9VVY RTS
---
SET VERBAL/NUKERIC RESPONSE
6ETNU"
VZERO
VIERO
7,YCODE
gyyy
7,VCODE
I
;
;
;
;
;
BET PARAKETER, IF ANY
IF NONE, ASSU"E ZERO
BRANCH IF = 0
SET FOR VERBAL RESPONSE
( BRANCH ALIIAYS I
SET FOR NUKERIC RESPONSE
; fftttfffftttftffftHfftftfftfftttffftUUttfftttfftftftftttttftttttffttftftfft
I •I' CDR RAND
FD74
FD77
FD79
20 8E FD
BO 06
FO 04
xxx
JSR
BCS
BEg
--GETNU"
XZERD
IZERa
ENABLE/DISABLE EXTENDED RESPONSE CODES
; SET PARA"ETER, IF ANY
j ASSUKE ZERO, IF NONE
; BRANCH IF = 0
4-32
R6500/11 • R2424 Intelligent Modem Design
Application Note
0973
0974
0975
0976
0977
0978
0979
O9BO
0981
O9B2
09B3
O9B4
0985
FD71
FD7D
FD7F
Foal
F77F
DO 02
7F
60
n
IDNE
SNI
7,ICODE
8IE
11111
IZERO RNB
RTS
; SET FOR EXTENDED CODES
7,ICoDE
gm
; SET FOR NoRNAL CODES
,IIHlftltftltttttfttttttttlltttttttttttttttttfttttttttlftttttttttttlttttftttft
; 'Z' CoNNAND
Foa2
Foa5
FOBB
FDBB
20
20
7F
4C
EB FE
.oFF
IHD
00 F8
zzz
JSR
JSR
ZZllAllBBR
JNP
---
SOFTIIARE RESET
RESPNS
CRLF
7,SCSR,ZZllAll
RESET
; SEND OUT RESPONSE, IF ENABLED
; IlAll UNTIL ALL CHARS HAYE BEEN SENT OUT
, THEN RESTART
PASE 0021
O9B7
0988
0989
0990
0991
0992 FD8E
0993 FD90
0994 FD92
0995 FD94
0996 FD96
0997 FD9B
0998 FD99
0999 FD9B
1000 FD9D
1001 FD9E
1002
1003
1004
1005
1006 FD9F
lD07 FDAI
IDOS FDA3
1009 FDAS
1010 FDA7
1011 FDAB
1012 FDAA
1013 FDAD
1014 FDAF
1015 FDBI
1016 FDI3
1017 FD85
10lB FDB7
1019 FD88
1020 FDBA
1021 FOlD
1022 FDBF
1023 FOCI
1024 FDC3
1025
, CHECK THE NEXT CHAR IN 'INBUFF', IF IT IS AN ASCII NUNBER (0-91,
FETCH IT, NASK OFF NSII, INCRENENT CONNAND BTRINS POINTER (RES-II,
CLEAR CARRY AND RETURN,
I
I IF CHAR IS NOT A NUNBER, SET CARRY AND RETURN,
B54C
C930
90 09
C9 3A
eo 06
EB
29 OF
90 01
3B
60
eETNU" LOA
CNP
acc
CNP
acs
HI2ASC LOY
HI2
CNP
BeC
CS
INY
BIlE
SOTHUN JSR
STY
LOY
HI3
CNP
CS
DO F7
20 CHD
8499
09 30
8598
60
;
I
;
;
I
;
I
;
,
I
SET CHAR FRO" BUFFER
IS IT LESS THAN '0' ?
YES==) IIUIl
NO :a) IS IT SREArER THAN '9' ?
YESes) IIUIl
NO .11) INCREIlENT INBUFF POINTER
NASK OFF TOP-NOST 4 BITS
AND RETURN
INDICATE CHAR IS NOT AN ASCII HUNBER
AND RETURN
INI
AND
'$OF
BeC
IlBET"
NOTNIIN SEC
IIsm RTS
I ttttttHHtttttttttftttttftttttHlffttfftftttttfftttttttftttfttttfttlfftfftttt
I ROUTINE TO CONVERT FRoN HEI BYTE TO 3-DISIT ASCII DECINAL
( PABE 154 '6502 SoFTIiARE DESISN' I ,
I
10 00
C9 64
9005
E9 64
DO F7
20 CHD
B4 9A
1000
C9 OA
9005
E90A
INBUFF,I
"0'
NOTHUN
''9'+1
116ET"
sac
act
SBC
IllY
BIlE
SOTTEN JSR
STY
DRA
STA
RTS
.00
.100
BoTHUIi
.100
HI2
HCONY
NUN+2
100
.10
BOTTEN
.10
HI3
HCONY
IIU"+I
..30
NU"
•
I FIND NUNBER OF HUNDREDS
; CONYERT TO ASCII
I AND SAVE IT
; FIND NUNBER OF TENS
I CONVERT TO ASC II
I SAVE TENS DI&IT
; SAVE ONES DI&IT
4-33
/
Application Note
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1031
1038
1039
1040
1041
1042
1043
1044
FDt4
FDCS
FDC6
FDCS
FDC"
FDCA
48
'18
OIl 30
AS
6B
60
R6500111 • R2424 Intelligent Modem Design
HCDNV PHA
TVA
DRA
TAV
PLA
RTS
1$30
; CONVERT ABSOLUTE NUI1BER TO ASCII
; tttttttttttttnfttttttfttttltttftftftttnflttttftftftftttltttttttlttttltlltfft
FDCB
20D7FD
NEIICIR JSR
NEIICR
; UPDATE BOTH RECE I VER AND TRANsmTER REGS
FDCE
FOOO
FOO3
FOD6
A908
00 OE 20
80 OE 20
&0
NEIICX LDA
ORA
STA
RTS
I$OB
XftTE
I"TE
; UPDATE MODEM'S TRANS"ITTER REGISTERS
FOO7
FOD9
FOOC
FDDF
A908
00 OE 10
80 OE 10
60
NEIICR LDA
ORA
STA
RTS
I$OB
RCYE
RCVE
I UPDATE MODEft'S RECEIVER RESISTERS
PAGE 0022
1046
1041
1048
104'1
1050
1051
1052
1053
1054
1055
105&
1057
1058
1059
1060
1061
1062
10&3
10&4
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
; tttttttltttftftfltttttttttttltfttttffttttttfttltttfttltltfttfttttttUfUtttftf
; '(CR)' COMAND
FOEO
FDE2
FOE4
FDE7
FOE9
FDEC
FDEE
AS 7D
DO 31
7F 80 2E
A9 01
2C OE 20
FO F8
FF7705
LDA
BNE
BBR
LOA
IIAIlOB BIT
BEQ
CR2
BBS
FDFI
FDF3
A9FF
80 00 20
LDA
STA
CR
CARRIAGE RETURN: SEND OUT RESPONSE MESSAGE
DR 60 INTO DATA "ODE IF REQUESTEO AND
IF CARRIER SIGNAL ACTIVE.
STeDDE
HOP
7,WAlTFG,HOP
1$01
IftTE
IIAITDB
7,REVFL6,CARTlft
;
;
;
;
;
;
;
UFF
X"TO
CHECK STATUS OF PREVIOUS COMMANDS
BRANCH IF NOT 'OK'
BRANCH IF WE ARE NOT TO WAIT FOR A CARRIER SIGNAL
IIAlT UNTIL DIAL RESISTER IS EftPTV
E"PTV YET?
NO ==) CHECK AGAIN •••
YES'=} CHECK FOR 'REVERSE' DIAL --) BRANCH IF
WE ARE REVERSE DIALlN6 ( DON'T CLOSE OUT DIALIN6
"UST BE 2400 OR NOR"AL 30011200 BAUD DIAL.
--) CLOSE DIAL IIODE AND GO TO DATA IIDDE.
IF liE IIERE AT 300 BAUD AND DIALING 'REVERSE'
"ODE THEN WE IIOULD HAVE TO WAIT FOR A CARRIER
SI6NAL BEFORE REVERSING THE IIODE" TO 'ANSWER'
IIODE. THEN liE IIRITE AN $FF TO 'XftTO' TO CLOSE
OUT THE DIAL SEQUENCE.
FDF6
FDF9
FDFB
FDFD
FEOO
FE03
FE06
20D3FE
AS eo
85 46
4F 01 18
BF 1& 03
7F 81 F7
57 12
CARlllI
~SR
LDA
STA
"CARIR BBR
BBS
8BR
NOCARR RIIB
STRTB3
57
DELAYS
4,PB,60TCAR
0, SCSR, NOCARR
7,IIAlTC,IICARIR
5, IER
; START CNTR-B FOR SECONDS-LONG TI"E INTERYAL
; SET UP SECONDS COUNTER ( SET BY 'COMMA' COIIIIAND I
;
;
;
;
BRANCH IF CARRIER DETECTED
BRANCH (EXm IF A kEY HAS BEEN TYPED
BRANCH IF IIAIT Tm HAS NOT EXPIRED
DISABLE mER 8 IRQ
4-34
~UST
YEll
Application Note
1075 FE08
1076 FEOA
1077 FEOC
1078 FEOE
1079 FEIO
1080 FEI2
1081 FEI5
1082
1083 FEI8
1084 FEIA
1085 FElC
1086 FEIF
1087 FE21
1088 FE23
1089 FE26
1090 FE2B
1091 mB
1092 FE20
1093 FE2F
1094 FE31
1095 FE34
1096 FE37
1097 FE3A
1098 mc
1099 FE3E
1100 FE41
1101 FE44
1102 FE46
1103 FE48
1104 FHA
1105 mc
1106 FE4E
A5
77
87
A9
85
20
4C
IC
80
01
03
7D
A7 FC
AF FE
57 12
A9FF
80 00 20
A9 01
8570
7F 7C 02
E7 01
20 E8 FE
07 01
A9 00
85 82
20 BB FE
4F 01 II
20 CHE
A5 90
B546
FF 81 C5
CF 01 fA
A5 16
57 12
A5 16
29 OF
FO E6
4A
HOP
R6500111 • R2424 Intelligent Modem Design
LOA
RnB
snB
LOA
STA
JSR
J"P
BOT CAR RnB
LDA
STA
LOA
STA
BBR
snB
GOTCRI JSR
R"B
GOTCR2 LOA
STA
60TCR3 JSR
INCHAR BBR
JSR
LOA
STA
CARCK2 BBS
BBS
LOA
RnB
INCHR2 LOA
AND
BEQ
CHKCHR LSR
CNTBCL
7,WAITFB
O,PS
1$03
sreODE
HHZERO
NOWAIT
5,IER
UFF
I"TO
1$01
sreODE
7,SPKRFS,60TCRI
6,PB
RESPNS
O,PB
100
ESCCNT
STRTBI
4,PB,INCHR2
STRTB2
510
DELAYS
7, MA ITC, NOCARR
4, PB, CARCK2
SCSR
5,IER
SCSR
I$OF
I NCHAR
A
; AND CLEAR CNTB FLAB
; TURN OFF WA IT FLAB
; DIRECT ALL OUTPUT TO HOST SYSTEn
; INDICATE "NO CARRIER'
; HANB UP THE PHONE ••••
; AND RETURN TO 'RESTRT'
; BOT A CARRIER --} DISABLE mER B IRQ
; FINISH UP DIALING tIN CASE OF REVERSE DIAL>
; INDICATE CARRIER DETECTED
;
;
;
;
;
LEAVE SPEAKER ALONE IF FLAG IS NOT SET
CARRIER DETECTED --) TURN SPEAKER OFF
AND OUTPUT ' CONNECT' "ESSAGE, IF ENABLED
THEN DIRECT ALL OUTPUT TO nODE"
RESET ESCAPE CODE COUNTER
; START mER-B FOR GUARD-mE COUNTER
; BRANCH IF CARRIER STILL DETECTED
; CARRIER LOST --) WAIT fOR 510 TENTHS-Of-SECONDS
FOR CARRIER TO RETURN -- OTHERWISE INDICATE
; LOSS Of CARR I ER AND RETURN TO CO"nAND MODE
; BRANCH IF THE mE-OUT FLAG GOES TRUE
; BRANCH IF CARRIER STILL LOST
; CARRIER DETECTED AGAIN BEFORE mE-OUT--)CLEAR SERIAL FLAGS
; DISABLE IRG
; MAlT FOR RECEIVED CHAR FRO" HOST conpUTER
; CHAR RECEIVED ?
; NO --> CHECK AGAIN
; YES-- > CHECK FOR PROPER RECEPTION
PAGE 0023
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
FE4F
FESI
FE53
FE55
BO
A9
as
DO
06
04
70
58
FE57
FE59
FESC
FESF
FEci
FEc4
FE67
AS 17
20 51
FF 7A
8701
20 51
6F 16
07 01
BCS
LDA
STA
BHE
FF
OA
FF
FD
CHKOK LOA
JSR
BBS
SIIB
JSR
IIAllDP BBR
Rna
CHKOK
104
STCODE
NOWAIT
SRDR
CHROUT
7, DUPLEX, ESCCHK
O,PB
CHROUT
6,SCSR,WAITDP
O,PB
; BRANCH IF CHAR OK
; CHAR NOT OK --) ERROR ....
; INDICATE ERROR AND START OVER ( BRA)
; CHAR OK --) FETCH IT
; AND SEND IT TO 1I0DEII
;
;
;
;
BRANCH IF CHAR IS NOT TO BE ECHOED BACK
ECHO --> DIRECT OUTPUT TO HOST conpUTER
ECHO CHAR BACK
IlAIT UNTIL CHAR IS SENT OUT
; AND REDIRECT OUTPUT 8ACK TO MODEn
; NON CHECK FOR POSSIBLE ESCAPE CODE SEQUENCE ••••
FE69
FE6B
FE6D
FE6F
C588
DO C4
AS 82
FO 06
ESCCHK cnp
BNE
LDA
BEQ
S2
GOTCR3
ESCCNT
ESCHK2
;
;
;
;
liAS CHAR AN 'ESCAPE' CHAR ?
NO -- > GET NEXT CHAR
YES--> IS IT THE FIRST 'ESCAPE' CHAR?
VES--> CHECK FOR ELAPSED mE SINCE PREY CHAR
4-35
•
Application Note
112I1FE71
1127 FEn
112B FE7S
1129 FE77
1130 FE7A
1131 mc
1132 FE7E
1133 FE80
1134 FE82
1135 FEBS
11311
1137 FEBB
1138 FE8B
1139 FE8D
1140 FE8F
1141 FE92
1142 FE9S
1143 FE97
1144 Fm
1145
11411 FE98
1147 FE9D
114B FE9F
1149 FEAl
1150
1151
1152
1153
1154 FEA4
1155 FEA6
1156 FEA9
1157
1158
1159 FEAB
11110 FEAD
1161 FEAF
1162 FEBO
1163 FEBI
1164 FEB4
1165 FE86
1166 FEB8
1167
R6500/11 • R2424 Intelligent Modem Design
BIT
24 81
30 B8
1003
7F 81 87
Ell 82
A582
C903
DO AF
20 BB FE
4F 01 13
Bill
BPL
ESCHK2 8BR
ESCHKl INC
LDA
CliP
BRE
JSR
LSTCHK BBR
MAITC
GOTCR2
ESCHK3
7, MAlTC, 60TCRl
ESCCNT
ESCCNT
103
SOTCR3
STRTBI
4, PB, LSTCK2
20
AS
B5
FF
CF
A5
S7
DO
CHE
90
411
81 AC
01 FA
16
12
92
JSR
LDA
STA
CAIICK3 BBS
BBS
LDA
RIIB
BNE
STRTB2
S10
DELAYS
7,NAlTC,CARCK2
4,PB,CARCK3
SCSR
S,IER
60TCR2
AS
2'1
DO
7F
16
OF
BC
BI EI
LSTCK2 LOA
AND
BME
BBR
SCSR
UOF
BOTCR2
7,IIAITC,LSTCHK
57 12
6F 16 FD
87 01
ESCAPE RIIB
ESC2 BBR
SIIB
S,IER
6,SCSR,ESC2
O,PB
; STOP TIllER B IRII
; WAIT UNTIL ALL CHARS ARE TRANSIIITTED OUT
; THEN DIRECT OUTPUT TO HOST COIIPUTER
A9 00
B57D
68
68
20 E8 FE
A900
8587
4C 16 FB
LDA
STA
NOIII\IT PLA
PLA
JSR
LOA
STA
J"P
100
STCODE
; RESET RESULT CODE TO 'OK'
RESPNS
100
SI
RESTRT
;
;
;
;
;
;
HAS BUAIID TIllE ELAPSED ?
YES::) MAITED TOO LONG; ESCAPE NO LONGER VALlD
NO ==) ADD 1 TO ESCAPE COUNT ( BRANCH ALNAYS I
BRANCH IF GUARD mE HAS NOT ELAPSED
I NCREmT ESCAPE CODE COUNTER
IS THIS THE THIRD SEQUENTIAL 'ESCAPE' CODE ?
; NO ==) GET NEXT CHAII
; YES==) RESTART 6UARD-TIIIER
NOli NAIT FOR 1 GUARD-TIllE INTERVAL FOR A CHARACTER
( BRANCH IF CARRIER IS OK )
CARRIER LOST --) NAIT FOR SIO TENTHS-OF-SECONDS
FOR CARRIER TO RETURN -- OTHERlllSE INDICATE
LOSS OF CARRIER AND RETURN TO COMAND IIODE
BRANCH IF THE TIllE-OUT FLA6 60ES TRUE
BRANCH IF CARRIER STILL LOST
CARRIER DETECTED ABAIM BEFORE T1I1E-OUT--)CLEAR SERIAL FLA6S
DISABLE IRII
LOSS OF CARRIER ABORTS ESCAPE SEIlUENCE --) BRANCH ALWAYS
;
;
;
;
;
;
I F A CHARACTER HAS BEEN ENTERED BEFORE
THE BUARD-TIllE INTERVAL HAS ELAPSED, THEN THE ESCAPE
SEQUENCE IS ABORTED AND CHAR IS HANDLED IN THE
USUAL FASHION ( AT 'CHKCHR' ). IF TIllER HAS
ELAPSED THEN ESCAPE SEQUENCE IS COIIPLETED MITH A
RETURN TO COIIIIAND IIODE.
; SET RID OF RETURN ADDRESS FROII 'JSR DOCIID'
; ( OR 'JSR AAA' AT LABLE 'ANSWER' I
; SEND OUT RESPONSE, I F ENABLED
j RESET RIN6 COUNTER TO ZERO
I AND START ALL OYER ABAlN
PA6E 0024
1168
1169
1170
1171
1172
1173
1174
1175
1176
; Itttfttttttttttlttttltllfttlftltlltttftttttttttttttttltttttttttttltttlttttttl
1/50 SEC (20"S) DELAY
FEBB
FEBD
FEBF
FECI
FEe3
A592
85 46
57 12
Ani
A29C
STRT81 LDA
STA
RIIB
LOA
LDX
512
DELAYS
S,IER
IESCDLY
IESCTIH
STRm
; •• , AND START mER •••
1110 SEC DELAY
FEC9
FECB
FECD
FECF
FED1
57
A9
A2
AO
DO
12
10
60
67
08
STRT82 RI'IB
LDA
LDX
LDY
BHE
S,IER
tDLYHIB
'TENTHD
STRTIH
; DISABLE IRQ
; SET UP DELAY PARAI'IETERS FOR 1110 SEC
; ••• AND START mER •••
( BRA)
1 SECOND DELAY
FED3
FED5
FED7
FED9
FEDB
FEDD
FEDF
FEEl
FEE3
FEE5
FEE7
57
A9
A2
AO
86
84
85
85
77
D7
60
12
10
9C
EO
IC
IE
44
45
81
12
STRTB3 m
LDA
LDX
LDY
STRm STX
STY
STA
STA
RI'IB
SI'IB
RTS
5,IER
IDLYHIB
I(DLYTlI'I
t>DLYTlI'I
CNTBCL
CNTBHL
DELAYC
DELAYT
7,WAlTC
5,IER
; DISABLE IRQ
; SET UP DELAY PARAI'IETERS FOR 1 SEC. DELAY
; LOAD CDUNTER-B
; SET IRQ COUNTER
; SET mE-OUT flAG FALSE
; ENABLE CNTR-B IRQ
PAGE 0025
1202 FEES
1203 FEEB
1204 FEEE
1205 FEFO
1206 FEF2
1207 FEF4
1208 FEF7
1209 FEF9
1210 FEFB
1211 FEFD
1212 FEFF
1213 FF01
1214 FF04
1215 FF06
1216 FF09
1217 FFOC
1218
1219 FFOD
1220 FFOF
1221 FFII
1222 FFI2
1223 FF14
1224 FFI5
1225 FFI7
1226 FFIB
1227 FFlA
1228 FFIB
20 40 FF
FF 7B IE
AS 7D
C9 01
DO OD
7F 7F OA
AHI
CO 03
FO 04
A9 05
85 7D
FF 7E 09
09 30
20 51 FF
20 40FF
60
RESPNS JSR
BBS
LDA
C"P
BNE
BBR
LDY
CPY
BEQ
LOA
STA
RSP2 BSS
NU"ERC ORA
JSR
JSR
QRSP RTS
CRLF
7,RSL TF6, QRSP
STCODE
1$01
RSP2
7,XCODE,RSP2
BAUD
1$03
RSP2
1$05
STeODE
7, VCODE, VERBAL
1$30
CHROUT
CRLF
A4
FO
88
FO
88
FO
8e
FO
ee
FO
VERBAL LDY
8EQ
DEY
8EQ
DEY
BEQ
DEY
BEQ
DEY
BEQ
STCDDE
RSPOK
; DETERI'IINE WHICH I'IESSA6E TO SEND OUT
; 0 ==> 'OK"
RSPCAR
; 1 ==> 'CARRIER'
RSPRNS
; 2 •• > 'RINS'
RSPNC
; 3 =-> 'NO CARRIER'
RSPERR
; 4 ==> 'ERROR'
7D
20
19
12
OB
04
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
BRANCH IF STATUS RESPONSE IS DISABLED
GET CODE VALUE
IF 'CARRIER' RESPONSE, CHECK FOR EXTENDED CODE
NOT 'CARRIER' --> BRANCH ...
BRANCH IF EXTENDED CODE SET IS NOT TO BE USED
IS SYSTE" RUNNING AT 1200 BAUD?
NO == > BRANCH ...
YES--> INDICATE 1200/2400 BAUD CARRIER
AND SAVE IT
BRANCH IF RESPONSE IS TO 8E VERBAL
CONVERT RESPONSE CODE TO ASCII
AND SEND IT OUT
FOLLOWED BY (CR/lF>
RETURN
4-37
II
Application Note
1229
1230 FF1D
1231 FF1F
1232 FF21
1233 FF23
1234 FF25
1235 FF27
1236 FF29
1237 FF2B
1238 FF2D
1239 FF2F
1240 FF31
1241
1242 FF33
1243 FF36
1244 FF37
1245 FF38
1246 FF3A
1247 FF3D
124B FF3E
1249 FF40
1250 FF42
1251 FF45
1252 FF4B
1253 FF4A
1254 FF4D
1255 FF50
1256
1257 FFSI
125B FFS4
1259 FF56
AO
DO
AO
DO
AO
DO
AO
DO
AO
DO
AO
lC
12
17
OE
00
OA
09
06
02
02
00
B9 7A
48
CB
29 7F
20 51
68
10 F3
A589
20 51
7F 7E
A58A
20 51
7F 16
60
FF
FF
FF
05
FF
FD
6F 16 FD
85 17
60
R6500111 • R2424 Intelligent Modem Design
RSPC12 LDY
BNE
RSPERR LOY
BNE
RSPNC LDY
BNE
RSPRN6 LDY
BNE
RSPCAR LOY
BNE
RSPOK LOY
ICONI211-IISB
IISBOUT
tERRIISS-IISS
"saOUT
tNOCARII-IISB
IISBOUT
tRN6I1S6-IISS
IISBOUT
ICARIISS-IISS
IISS0UT
tOKIISS-IISS
; 5 ::) 'CONNECT 1200/2400'
IISGOUT LOA
PHA
IHY
AND
JSR
PLA
BPL
CRLF LDA
JSR
BBR
LOA
JSR
ItAITLF BBR
RTS
IISB, Y
;
;
;
;
;
;
;
;
;
;
;
;
;
;
CHROUT BBft
STA
RTS
I$7F
CHROUT
"SBDUT
S3
CHROUT
7,VCODE,WAITLF
S4
CHROUT
7,SCSR,IIAITlF
6, SCSR, CHROUT
STDR
GET CHAR FROII IIESSA6E TABLE
SAVE CHARACTER
PO I NT TO NEXT CHAR
flASK OFF 115B
AND SEND OUT CHAR
RESTORE SI6N BIT
BRANCH IF IIORE CHARS TO BE SENT
I S3 CONTAINS CURRENT (eR) )
SEND OUT (CR)
BYPASS (LF> IF NUflERIC RESPONSE SELECTED
I S4 CONTAINS CURRENT (LF) )
OUTPUT (LF>
IIAlT UNTIL (LF) IS FINISHED
THEN RETURN
; WAlT TILL TRANSIIITTER BUFFER IS EIIPTY
; THEN SEND OUT CHAR
PABE 0026
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
; INTERRUPT SERVICE ROUTINE
FF57
FFS8
FF5A
FF5D
FF5F
FF60
FF62
FF64
FF66
FF6B
48
AS lC
FF 78 OD
AS 00
OA
9004
E700
BO 12
67 00
90 OE
FF6A
Co 44
DO OA
AS 45
mc
FF6E
ISR
SET!
SETO
PHA
LOA
BBS
LDA
ASL
BCC
SIIB
Bes
RIIB
BCC
CARIER DEC
SNE
LDA
CNTSCl
7,IRQFL6,CARIER
PA
A
SETO
a,PA
91SR
6,PA
GISR
; CLEAR mER S FLAB
; BRANCH IF IRQ IS FOR WAIT -FOR-CARRIER DELAY
; ECHO SERIAL IN TO SERIAL OUT
DELAYC
QISR
DElAY!
; IS TIllER COUNTER : 0 ?
; NO :: > RETURN
; YES:: > RESET IT
(BRANCH ALWAYS)
(BRANCH ALWAYS)
4-38
Application Note
1278
1279
1280
1281
1282
1283
FF70
FF72
FF74
FF7&
FF78
FF79
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1m
1297
1298
1299
1300
1301
1302
1303
FHA
85
C6
DO
F7
68
40
44
46
02
81
R6500111 • R2424 Intelligent Modem Design
STA
DEC
BNE
S"B
9lSR PLA
N"lRTN RT!
"S6
.SBY
.SBY
.SBY
.SBY
.SBY
.SBY
FHA
FF7C
FF83
FFB7
FF91
FF96
4F
43
52
4E
45
43
OK"S6
CAR"S6
RH6M6
NOCAR"
ERR"S6
CON12"
FFA7
FFAB
2A
36
CHKSU" .SBY
PCDDE .SBY
; IS SECONDS COUNTER - 0 ?
; NO
RETURN
; YES'-> SET mE-OUT FLAG
._>
'OK'
'CONNECT'
'RINS'
'NO CARRIER'
'ERROR'
'CONNECT 1200/2400'
'tfft'
'6500'
t·$FFFA
FFAF
FFFA
FFFC
FFFE
DELAYC
DELAYS
9ISR
7,MAlTC
79FF
00 F8
57FF
•NOR
.1I0R
.1I0R
HmTH
RESET
ISR
•END
"D"10A
•
ERRORS - 0000 (0000 >
PASE 0027
smOL TABLE
AAA
ABlT8
ABlT9
ALLIN
A"SIIER
BAUD
BAUDI2
BAUD24
BAUD3
BDRATH
BDRATL
BD2
BS
BUFFL6
B03
BI2
B24
CARCK2
CARCK3
CARIER
CAR"S6
FCOD
0048
0049
F9DD
FA42
0041
002F
0017
OOBF
0043
om
F974
F9BF
0075
F95A
F9b6
mE
FE3E
FE8F
FF6A
FF1C
0489
10044
10045
0414
0485
10037
10126
10127
.0125
.0039
10038
0356
0401
.0050
.0353
10359
0358
.1099
.1140
1266
1238
0509
0179
0180
10422
10488
0378
0357
0351
0215
0223
0362
.0404
0186
10m
0263 0313 0316 0330
0268 0309
0900 1208
0553 0555
0341 0347 0477 • 0556
0342 0345 0350 0475 0554
.0366
0418 0422
.0363
1100 1140
1141
.1275
I12B8
4-39
Application Note
CART!"
CCC
eCOIiE
CCIERO
CHKCHR
CHkOk
CHKSU"
CHROUT
FDF6
m8
FC2F
m8
FE4E
FES7
FFA7
FF51
C"DTBL FA47
mVEC 0098
CNTACL 0018
CNTAH
CNTAL
CHTBCL
CNTBHC
CNTBHL
CO""A
CON12"
CR
CRLF
CR2
CTLCOD
DDD
DEFPRO
DELAYC
DELAYS
DELAYT
DELETE
DISERR
DIGIT
D162
DILFLS
DLVHIB
DLvm
DOCMD
DUPLEX
ECHOFG
0019
OOIA
OOIC
001D
001E
FBIE
FF96
FDEO
FF40
FDEE
mc
FC44
0040
0044
0046
0045
F9C3
FB54
FB3C
FB4E
0076
0010
E09C
F9F2
007A
0079
0870 1057
050910143
10740
0744 om
11106
1107 11112
0839 11294
0394 0403
11257 1257
0448 10497
10089 0436
10025 0205
0346 0476
10026 0213
10027 0206
10030 0198
10031
10032 0200
0505 10579
1230 11292
0425 0512
0710 0719
0735 11057
om 10395
0509 10760
10036 0339
10040 1196
10042 1070
10041 1197
10406
0601 10618
0506 0507
0612 10614
10051 01B4
10119 0586
10120 0582
0434 10436
10055 0550
10054 0196
R6500/11 • R2424 Intelligent Modem Design
11068
10750
0409 0716 1113 1116 1215 1246 1250 1253
0461 0463
0217 0224 0235 0260 0265 0279 0296 0301
0227 0229 0247 0274 0276 0348 0478
0583 OS88 1075 1194 1265
0585 119S
0774
0620 om 0921 11051
0835 0983 1202 1216 11249
0473 0558
1275 127B
109B 1139 1173 1279
1277
0645
10601
0546 0601 0627 0628 0777 0899 0904
1183 1191
0584 1192 l193
0801 0803 1114
0393 0549 0789 0791
PASE 0028
SYMBOL TABLE
EEE
EONE
EQUAL
EQ2
EQ3
EQ4
ERR"SG
ESCAPE
ESCCHK
ESCCNT
ESCDLY
FC72
FC79
FB76
FBA2
FBAD
FB8C
FF91
FEA4
FE69
0082
0001
0509
10789
0508
0654
0666
0651
1232
11154
1114
10063
10122
10786
10645
0659 t0665
10670
0671 10677
11291
11122
1093 1124 1130 1131
1175
4-40
Application Note
ESCHK2 FE77
ESCHK3 FE7A
Escm mc
ESC2
EVEN7
EVEN8
EZERO
FFF
FNDC~D
FONE
FOUND
FOUNDA
FOUNDS
FOUNDT
FIERO
BETCHR
emu"
SOCR
60TCAR
SOTCHR
SOTCRI
GOTCR2
SOTCR3
SOT HUN
SOTTEN
S02RES
FEA6
F929
F91D
FC7D
FCBO
F9F5
FCB7
FAOD
FSAD
FBEF
FBFI
FCBS
F9A4
FDBE
FAOS
FE1e
HCONY
HHH
HHSET
HHZERO
HOP
HX2
HX2ASC
HX3
HIAND2
IER
F9CD
FE2B
FE2D
FE31
FDAA
FDSA
FBA7
F962
FDC4
FCBE
FCB7
FCA7
FEI5
FOAl
FD9F
FDBI
FC95
0012
IFR
0011
III
FceB
moo
HONE FCCS
lllERO FCC9
INBUFF 004C
INCHAR
INCHR2
INlTSN
lRQFLG
FE34
mB
FABE
007B
1125 11129
112B 11130
10m 1170 1177
11155 1155
0317 10327
0310 10321
07B7 07BB 10m
0509 10798
0432 10444
10BOI
0449 10457
0244 10259 0259
02BB 10293
0290 10295 0295
0799 OBOO IOB03
10392
0650 0653 065B
0929 0933 095B
0447 10455
1071 110B3
0396 0405 10412
10BB 11090
11092 1127 1144
11094 1123 1129
100B 11012
1016 11020
10250
0352 10357
1012 1020 11026
0509 #OB10
0820 10827
OB11 OBI2 IOB21
1052 1053 11081
11007 lOll
0713 mOb
11015 1019
0726 10813 0868
10019 0201 0349
1174 1182 1190
100lB 0192 0207
0295 0300 0470
0510 10835
10839
0837 OB38 tOB41
1004B 0412 0445
81095 1105
1095 11103
0140 40526
10053 0202 0380
R6500/11 • R2424 Intelligent Modem Design
om
0786 0798 OB10 OB36 OB51
0970 10992
OB86
1148
1133
II
lOBO
0469 0528 1074 1083 1102 1143 1154
1199
0228 0234 0248 0259 0264 0275 0278
0527 0587
0569 0605 0992
0488 1266
4-41
Application Note
R6500/11 • R2424 Intelligent Modem Design
PAGE 0029
SYMBOL TABLE
ISR
LABEll
LOOP2
LSTCHK
LSTCK2
L1
L10
Ll2
L2
L3
L4
L4A
L5
Lo
L7
L8
L9
NCR
"""
"NONE
""1110
""IERO
"58
"S60UT
"ULTIO
NEIICR
NENeI
NENCIR
N"IRTN
NOCAR"
NOCARR
NOOLAY
NOIRQ
NOPAR
NOPAR7
NOPARS
NOSLFT
NOTNU"
NOIIAIT
NUM
NU"CMD
NUNERC
NXTC"D
DDD7
0008
OK"S6
ONESEC
FF57
F93D
F9FD
FE8S
FE9B
F857
F8D4
F8FB
F85F
F87D
F889
F8AI
FBA4
FBB7
F8CI
F8C4
F8CD
0014
FCCF
FCDC
FCDE
FCE3
FF7A
FF33
FBEe
FDD7
FOCE
FDCB
FF79
FFS7
FE06
F839
F850
F92F
F939
F933
FBC6
FD9D
FEAF
0098
PA
0021
FF04
F9E9
F917
F923
FF7A
F82C
FCE6
0000
PB
0001
000
11264 1301
0320 0323 032& 0329 0334 10338
10448 0452
11135 1149
1135 11140
10207 0208
10278 0278 0284
10300 0300
10210 0210
10228 0228
10234 0234 0240
10248 0248
10249 0249
10204 0204
10m om
10270 0270
10275 0275
10020 0138 0194 0195 0221 0222
0510 10850
10856
0855 10857
0852 0853 10859
0839 0841 1230 1232 1234 1236
0842 1231 1233 1235 1237 1239
0667 0672 0673 10m
0191 1034 11041
0733 0753 0767 0879 0951 11030
0377 0696 0827 0916 11034
11283 12"
1234 11290
1072 11074 1099
05BI 10593
0196 10203
0315 10330
0331 10335
10332
10682
0994 11000
1081 1110 11161
10088 0647 0048 0649 0652 0655
0662 0063 0664 0065 0668 0669
0715 0932 0936 0937 1013 1021
10129 0451 0455
11214
10432 0435
10318
0312 10324
1240 11287
10586 0592
0510 10868
10013 0208 0209 0210 0230 0236
0270 0280 0297 0302 1267 1270
10014 0142 0143 0144 0145 0146
0859 1071 1077 1089 1091 1095
0472
1238 1240 1242 11285
11242 1248
0656 0057 0660 0661
0670 0675 0676 0077
1023
0249 0261 0266 om
1272
0354 0300 0364 0857
1100 1115 IllS 1135
4-42
Application Note
penOE FFAB
PPP
FCEE
\lCCC FC3D
ODISIT FB53
QECHO FC7F
1141
0841
0510
0748
10616
R6500/11 • R2424 Intelligent Modem Design
1156
11295
10876
om 10752
om 10m
PAGE 0030
SYMBOL TABLE
IIEQ
QFFF
GSETN
QHHH
1111
915R
II"""
IIQ
FBEB
FCBD
F09E
FCBA
FCCB
FF78
FCES
F007
GIIONE FOOl
IIQII
FCFA
Gil ZERO FOOS
GRRR F032
9RSP FFOC
9SSS FD57
QUESTN FBF4
IIUES3 FCOO
IIYVY FD73
QXXX FOBI
RCY
1000
RCYA 100A
RCYB 100B
RCYC 100C
RCVO 1000
RCVE 100E
RCVF 100F
RCV2 1002
RCVS 100B
RCV9 1009
REPEAT F9E7
REPFL6 0074
RERROR F033
RESET FBOO
RESPNS FEES
RESTRT F816
REVFLG 0077
RINS FSAA
RINGNG FAIC
RNG"S6 FF83
ROTATE F943
RRR
FOOB
RSLTFS 0078
RSPCAR FF2D
RSPC12 FF10
RSPERR FF21
068810096
0802 10804
om 0999
10828
OB40 10842
1271 1273
OB58 IOB60
0890 10892
10889
0510 10886
OBB7 OBBB
0902 10917
1203 11217
0930 0931
0508 10710
11001
1276 1280 11282
10891
10941
10m 0718
om 10964
0974
10092
10098
10099
10 I 00
10101
10102
10976
0094
0367 0370 0534 0683 0684 0691 0692
0375 0537
0188 0190 0532 0817 0819 0824 OB26 0910 0911
0539 1042 1043
10103
10095
10096
10097
0386 0422 10427
10049 0178 0293 0386
0899 10919
10133
0481
10176
10052
0207
0252
1236
10341
0510
10056
1222
11230
1228
09B5 1300
0982 1090 1163 11202
0250 0291 0486 1166
om 0905 1057
10252
10469
11289
0344
10899
0547 0889 0891 1203
11238
tl232
4-43
•
Application Note
RSPNC
R5POK
RSPRNS
RSP2
SCCR
SCSR
FF25
FF31
FF29
FFOI
0015
0016
SE"ERR
SEftlC
SE"12
SETPTR
5ETO
SET!
5LFTST
5LDDP
SPKRFS
FBilF
FB58
FBil2
F99t
FFil6
FFil2
FBD8
FBlI
007e
1226
1220
1224
1206
10021
10022
1155
om
11234
11240
11236
1207
0177
0381
1254
10637
10m
0631
0410
tl212
R6500/11 • R2424 Intelligent Modem Design
1210 11213
om 0474
0388 0984 1072 1101 1103 1117 1142 1146
1257
0508
10630
10387
1269
11270
0681 10690
10564 0567
10057 0552 0850 0856 1088
PAGE 0031
SY"BDL TABLE
5RDR
SREGP
ssmB
5SS
SS2
STBL
STCODE
0017
0084
0083
FD3A
FD50
FAAD
0070
STDR
STRTBI
STRTB2
STRTB3
STRm
SO
51
S10
Sl1
S12
S13
SI4
SIS
SI6
S17
52
53
54
S5
56
S7
58
S9
T8IT8
TBm
TEKP
0017
FEBB
FEC9
FED3
FEDD
0086
0087
0090
0091
0092
0093
0094
0095
0096
0097
00B8
0089
008A
0088
008t
0080
OOBE
OOBF
004A
0048
009D
10024 0392
10065 0560
10064 0543
0511 10m
093410931
10517 0564
100S8 0187
1087 1109
10023 0024
1094 1134
1096 1137
1068 11190
1178 llB6
10069 0484
10070 0482
10m 1097
10080
t0081 1172
10082
10083
10084
10085 06BO
10086
10071 1122
10072 0395
10m 1252
10074 0402
10m 0772
10076 1069
10077 0580
10078
10046 0181
10047 0182
10090 0366
1112
0562 0565 om 0712 0928 0939 0940
0645 0941
0424 0454 0480 0619 0638 0920 1051 1079
1160 1204 1212 1219
1258
11172
11182
11194
0559 0561 0927
0483 0544 1165
1138
0413 0446 0568 1249
0404
0770 0773
om
0299 0314
0304 0311
0369 0373 0579 0593 0699 0702
4-44
Application Note
TENTHD
TESTB
TTl
VCDDE
VECTBI.
VERBAL
VDNE
WV
VZERD
MAITB
IIAITC
IlAlTDB
IlAITDL
IlAITDP
IlAITfB
IlAlTl"
IlAlTLf
IlAlTRE
IICARIR
leoDE
I"T
I"TA
1m
I"TC
1m
6760
0047
FD5A
007E
FA69
FFOD
f06D
FD66
fD71
f82E
OOBI
fDE9
fCS9
fE64
0080
f99E
Ff4D
fB4I
fDfO
007f
2000
200A
200B
200C
200D
10121
10043
0511
10059
0460
1213
10961
0511
0959
10587
10062
11055
10768
11117
10061
10388
1251
101103
11071
10060
10105
10112
10113
10114
10WI
0913
1184
0183
10948
0551
0462
11219
10958
0960
0587
1073
1056
0769
1117
0185
0390
11254
0604
1073
0545
0107
0371
0530
0376
0529
0915
R6500111 • R2424 Intelligent Modem Design
1185
0232 0238 0241 0271 0282 0285
0961 0963 1213 1251
10505
10963
0590
1099 1126 1129 1140 1149 1198 1281
om
0734 0778 08119 1053 1076
0398 0399 0407 0417 0420
1254
0973 0975 1207
0374 0535 01lB6 06B7 0694 0695
08711 OB7B 0948 0950
0538
0728 0729 0763 07116 0813 08lD 0821 0823
PA6E 0032
SYMOL TABLE
200E
200f
2000
2002
200B
2009
fD7B
fD74
III
lZERD FD7f
ZIIiAlT fDBB
zzz fD82
.MARB Itlt
1m
I"Tf
I"TO
1m
I"TB
1"19
IOIlE
101111
10117
10108
10109
10110
10111
10973
0511
0971
10984
0511
0540 01103 01130 1037 1038 1055
0615
om
lObO 10B5
0768
0731 0732 0747 0751 0752 0761 07112 0907 0908
10970
0972 10975
0984
I09B2
END Of ASSE"BLY
4-45
•
Application Note
'1'
Interfacing Rockwell Signal
Processor-Based Modems
To An Apple lie Computer
Rockwell
by Carlos A. Laiz, Product Applications Engineer
Semiconductor Products Division, Newport Beach, California
INTRODUCTION
USART. 110 SELECT is active during 00 clock when the microprocessor references page $Cn, where n is a peripheral
slot number (1-7) in the Apple.
This application note describes the electrical design of a module
that interfaces an Apple lie' computer to a Rockwell Signal
Processor (SP)-based modem. The design incorporates an
USART (8251A) for asynchronous/synchronous serial data
transfer and control, and two digital-to-analog converters (DACs)
for quadrature eye pattern generation. Memory mapped
input/output (I/O) allows easy access to the modem interface
memory for parallel control and data transfer. The interface
module connects directly to the following modems with minor
software differences required to switch between them:
• R1212M or R1212DC
• R2424M or R2424DC
• R48DP
The data lines are buffered by U2 and routed to multiple destinations (U1, U8, U9 and the interfacing modem). U2 is enabled
by I/O SELECT and the data direction is controlled by READ.
Address lines A4-A6 are decoded (U3) into eight chip select
signals ($CnOR-$Cn3R and $Cn4X-$Cn7X). Addresses
$CnOR-$Cn3R correspond to the modem chip select inputs
(CSO-CS3). Writing to address $Cn4X triggers U4 to generate
a low level pulse (4 P.s min.) causing the modem to initiate a
Power On Reset (POR) cycle. Addresses $Cn5X and $Cn6X
are used to write eye pattern data into the X-DAC and Y-DAC,
respectively.
• R96DP
• R96FT
Two assembly listings of sample software subroutines for
R12121R2424 automatic dialing and R48DP/R96DP eye pattern
generation are also included.
The USART's input line ControllData (CiD) is controlled by the
address line A7. Address $Cn7X (A7 = 0) is used to write to the
transmitter register or to read the receiver register in the USART.
Address $CnFX (A7 = 1) is used to write to the USART Control
register or to read its status register. The USART is supplied
with 01 clock directly from the Apple bus.
HARDWARE DESIGN
The interface module schematic (Figure 1) shows the routing
of signals between an Apple lie peripheral slot, the USART, and
the modem. The modem can phYSically be located outside the
Apple lie and connected by a short 64-conductor ribbon cable
to a 64-pin DIN connector (with the same pin assignments)
installed on the interface module.
The I/O addresses and their functions are summarized in
Table 1.
Table 1.
The major devices on the interface module are the 8251A
Universal Synchronous/Asynchronous ReceiverlTransmitter
(USART) and two NE5018 DACs. The USART (U1) allows the
microprocessor to transfer data and control to the modem via
the serial interface. This USART supports both asynchronous
and synchronous data transfer modes. The two DACs, US and
U9, generate the analog voltages to drive the eye pattern X-OUT
and V-OUT signals, respectively.
Address lines AO-A3 are directly connected to the modem
register select inputs RSO-RS3. The Apple's partially decoded
110 SELECT (pin 1 in the Apple peripheral connector) is used
to gate RiW to produce two separate READ and WRITE signals
with the proper timing as required by the modem and the
* Apple
Interface Module Memory Map
Address
Device Addressed/Function Performed
$CnOR
$CnlR
$Cn2R
$Cn3R
$Cn4X
$Cn5X
$Cn6X
$Cn7X
$CnFX
Chip Select 0 (CSO)
Chip Select 1 (CS1)
Chip Select 2 (CS2)
Chip Select 3 (CS3)
POR (Power-On-Reset)
X-DAC Latch Enable (XLE)
Y-DAC Latch Enable (YLE)
USART Chip Select (C/O = A7=!b)
USART Chip Select (C/O=A7=1)
Notes:
n = Apple lie peripheral slot number (1-7)
R = Modem register number (O-F)
X = Irrelevant
and Apple /Ie are registered trademarks of Apple Computer, Inc.
Document No. 29220N73
Application Note
4-46
Order No. 673
February 1985
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MODEM
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R1212
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By
R48DP
R96DP
R96FT
AS 19
CD
G
ri°
I'
IR
GND
vee
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CS-L-I~I~
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+SV 141 51 9
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A
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b,;s:;;cn::;s;::x'-_ _ _ _ _....J
7
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I
8
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(Ul)
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N~15
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TxRDY
NC 18 TxE
NC 14 RxROY
NC 16 SYNC/BRK
21 RESET
1
91•
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ALL CAPACITOR VALUES IN /tF
UNLESS OTHERWISE SPECIFIED
~ 1/4W
*
~O.5%
-rJ, 114 ..
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it
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Figure 1.
Apple lie to Rockwell SP Modem Interface Schematic
II
CD
Application Note
Rockwell SP·Based Modem to Apple lie Interface
SOFTWARE CONSIDERATIONS
R1212 and R2424 data sheets. The subroutine, as shown, starts
at address $6000 but can be easily relocated. As written, it
assumes that the interface module is installed in Apple lie
peripheral slot 4. The number to be dialed should be stored at
$6100 and terminated with an $FF character.
Application software can easily control the modem, the USART
and the two DACs via the addresses decoded on the interface
module (Table 1). The location of bits and registers as well as
diagnostic access codes vary between modems. Refer to the
appropriate data sheet for specific bit and register locations and
access codes.
The Eye Pattern Generator subroutine for the R48DP/R96DP
(Figure 3) generates a continuous eye pattern in loop 3 (local
analog loopback) by reading a signal point once per baud. The
subroutine starts at $0300 and can also be easily relocated.
Execution is halted and control returned to the calling routine
when a key is pressed. The comments in the listing describe
the detail operation.
Two example software subroutines are included in this application note for interfacing to an SP-based modem. These routines
are written in 6502 assembly language.
The Automatic Dialer subroutine for the R12121R2424 (Figure 2)
implements the same function described and flowcharted in the
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4-48
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*
jII.jI;
Rockwell SP-8ased Modem to Apple lie Interface
Application Note
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Application Note
2400/1200/300 bps International Modem Design
Table 2. International Modem 1/0 Addresses
Address (Hex)
SCC has two 1/0 channels (A and B). Channel A is used for all
full duplex modes; channel B is used in a V.23 half duplex mode
where a secondary channel is used.
Register Description
200
201
202
203
204
205
206
207
208
209
20A
20B
20C
200
20E
20F
R2424
R2424
R2424
R2424
R2424
R2424
R2424
R2424
R2424
R2424
R2424
R2424
R2424
R2424
R2424
R2424
Receiver
Receiver
Receiver
Receiver
Receiver
Receiver
Receiver
Receiver
Receiver
Receiver
Receiver
Receiver
Receiver
Receiver
Receiver
Receiver
Reserved
Reserved
Diagnostic 1
Diagnostic 2
Diagnostic 3
Diagnostic 4
Reserved
Reserved
Status 1
Status 2
Configuration 1
Configuration 2
Configuration 3
Configuration 4
Handshake
Diagnostic Control
210
211
212
213
214
215
216
217
218
219
21A
21B
21C
210
21E
21F
R2424
R2424
R2424
R2424
R2424
R2424
R2424
R2424
R2424
R2424
R2424
R2424
R2424
R2424
R2424
R2424
Transmitter
Transmitter
Transmitter
Transmitter
Transmitter
Transmitter
Transmitter
Transmitter
Transmitter
Transmitter
Transmitter
Transmitter
Transmitter
Transmitter
Transmitter
Transmitter
220
221
222
223
22422F
230
231
232
233
23423F
Z8S30 Channel B Command
Z8S30 Channel B Data
Z8S30 Channel A Command
Z8S30 Channel A Data
Not Used
Not Used
82CS5 Port A
82C55 Port B
82CS5 Port C
82CS5 Control Register
Not Used
Not Used
OutgOing data (TXO) written from the host computer is serialized and formatted by the 28530 SCC (U6). It is then output on
the TXOA or TXOB pin in serial form.
Incoming data (RXO) from the modem is input to the SCC on
the RXOA or RXOB pin and is read via the data bus from the
SCC data register. The data is then routed to the PC display
(application note software). or it may be routed to a different
destination (user-provided software).
The SCC AlB input selects channel A or B. The SCC CIO input
determines if control or data information is being accessed. The
WR and RO inputs determine if data is being written to or read
from the SCC. respectively. The CE input is low at address
220-223 to enable the SCC.
Dial Digit Register
Reserved
Diagnostic 1
Diagnostic 2
Diagnostic 3
Diagnostic 4
Reserved
Reserved
Status 1
Configuration 1
Configuration 2
Configuration 3
Configuration 4
Configuration 5
Handshake
Diagnostic Control
R2424 Modem
The R2424 is mapped into the PC 1/0 addresses 200H-21 FH.
The R2424 receiver is enabled by CSO (200H-20FH) and the
transmitter is enabled by CS1 (210H-21 FH). This enables access
to the 32 locations required by the receiver and transmitter
interface memories. Host computer address lines AO-A3 are
routed to R2424 register select inputs RO-R3. respectively. to
access the required interface memory location.
For more information on the R2424 refer to the R2424 Data
Sheet (Order No. M011) and Section 4 (R1212/R2424 Modem
Functional Characteristics) in the Modem Interface Guide (Order
No. 685). both available from Rockwell International.
Am7910 Modem
Operation of the Am7910 modem is controlled by five configuration inputs (MCO-MC4). Table 3 lists the available modes and
identifies the modes used in this application note. The Am7910
configuration signals are controlled by PPI (U7) ports PAO-PA4
since there is no direct host computer bus interface.
The V.24 control signals are routed from the 28530 SCC (U6).
The primary channel (used for all full duplex modes) is routed
to the SCC channel A and the Am791 0 secondary channel (used
for the 1200 half duplex mode) is routed to the SCC channel B.
All data between the host computer and the modem is transferred over the bidirectional data bus (00-07). The data bus
carries data to be transmitted to the modem (TXO) and to be
received from the modem (RXO) via the 28530 SCC. as well as
controllstatus signals to/from the R2424 modem. the 28530 SCC
and the 82C55 PPI. U13b. U13c and U13d enable data bus buffer U3 when an 1/0 read or 1/0 write occurs in a valid address
range. The direction of the data bus buffer is controlled by the
host computer I/O read line (lOR) gated with the valid I/O
address signal appearing at U13d/11.
Z8530
The clock for the Am791 0 is provided by the SCC output TRxCA.
V.24 Interface
TTL V.24 signals are routed to/from the R2424/Am7910 modems
as selected by U9 and U10. The RLSO. CTS and RXO outputs
from either the R2424 or the Am791 0 are switched through U9
to 28530 SCC (U6) channel A inputs DCOA. CTSA and RXOA.
respectively. PPI PAS output high selects Am791 0 signals; PPI
PAS output low selects R2424 Signals.
The TXD input to both the R2424 and the Am7910 is routed
directly from the SCC TXOA output. The RTS input to the R2424
andlor the Am791 0 is routed from the SCC RTSA output through
U10. The RTS input to the R2424 is enabled through U10 by
PPI PA6 output low. The RTS input to the Am7910 is enabled
through U10 by PPI PA7 output low.
see
The 28530 SCC (U6) transfers the data from the modems to the
data bus and converts the data from parallel to serial and serial
to parallel between the host computer and the modem devices
and provides asynchronous formatting and unformatting. The
4-53
•
2400/1200/300 bps International Modem Design
Application Note
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1 uF
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International Modem Schematic
4-54
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ACCT. 78
.•
Application Note
2400/1200/300 bps International Modem Design
•.11 A2424M
=====================================~~~~~~~~iO~
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Screen # 71
o ( V21/V23 MODEM
1 DECIMAL
( IRQ4 )
( IRQ3 )
27/1/86 MBW )
INTERRUPT HANDLER
2
3 2VARIABLE LINKS
4 VARIABLE X VARIABLE V
5
6
7
8
9
10
11
12
13
FIX-VOC-LINKS
@V
VOC-LINK DUP X!
BEGIN
V @
WHILE
V @ HERE U<
IF
V @X @
ELSE V @ @ V
REPEAT
V @X
THEN
X @ @ V
14
15 -->
Figure 14.
International Modem FORTH Screens
4-67
Application Note
2400/1200/300 bps International Modem Design
Screen # 7,2
o (
1
2
3
V21/V23 MODEM INTERRUPT HANDLER
BEGIN-MOD
1 ?DEPTH HERE LINKS
LATEST NAME> LINKS 4+ !
LIMIT 500 - SWAP - DP ! ;
27/1/86 MBW )
4
5
6
7
8
9
10
END-MOD
LINKS @ DP ! ;
FORGET-MOD
LINKS 4+ @
SHR4
LINKS @ 32 0 SKIP DROP
N>LINK W! FIX-VOC-LINKS
11
12
13
14
15 -->
Screen # 73
o ( V21/V23 MODEM
INTERRUPT HANDLER
27/1/86 MBW )
1
2 DECIMAL
17000 BEGIN-MOD
ASM86
END-MOD
3
4 HEX
5
6 2000 CONSTANT ASC BUF SIZE
7
8 CREATE
9
ASC BUF
ASC=BUF
ASC BUF SIZE ALLOT
ASC=BUF=SIZE ERASE
10
11 VARIABLE ASC IN
12 VARIABLE ASC-OUT
13
14
15 -->
Screen # 74
o ( V21/V23 MODEM INTERRUPT HANDLER
1
2 0 INT_# 4
*
2CONSTANT INT-VEC
3
4 2VARIABLE PREV_ASC_VEC
5
6
7
8
9
10
11
12
13
14
15 -->
Figure 14.
International Modem FORTH Screens (Continued)
4-68
27/1/86 MBW )
240011200/300 bps International Modem Design
Application Note
Screen # 75
o ( V21/V23 MODEM
1
2
3
INCR PTR
4
5
6
7
8
9
INTERRUPT
27/1/86 MBW )
HAt~~)l:'::R
ROT
2 PICK @ +
2DUP <=
IF
SWAPELSE SWAP DROP
THEN SWAP! :
+ASC IN
ASC IN ASC BUF SIZE INCR PTR
+ASC-OUT
10
ASC-OUT ASC=BUF=SIZE INCR-PTR
11
12
13
14
15 -->
Screen # 76
o ( V21/V23 MODEM INTERRUPT HANDLER
1
2
3
4
5
?ASC
ASC_IN @ ASC_OUT @ <>
@ASC
BEGIN ?ASC
UNTIL ASC_OUT @ ASC BUF + C@
27/1/86 MBW )
1 +ASC OUT
6
7
#ASC
8
9
ASC OUT @ ASC IN @ 2DUP U>
IF - ASC BUF-SIZE +
THEN
- NEGATE
10
11
12
13
14
15 -->
Screen # 77
o ( V21/V23 MODEM INTERRUPT HANDLER
1 HEX
2 CREATE ASC INT ASSEMBLER
3
STl
AX PUSH BX PUSH
4
DX PUSH DS PUSH
5
AX, CS MOV DS, AX MOV
6
DX, # ASC PORT MOV
7
AL, DX IN8
9
CLI
BX, ASC IN 2+ MOV
10
ASC_BUF-[BX), AL MOV
11
12
13
14
15 -->
Figure 14.
International Modem FORTH Screens (Continued)
4-69
27/1/86 MBW )
•
Application Note
240011200/300 bps International Modem Design
Screen 41 78
o ( V21/V23 MODEM
1
2
3
4
5
6
INTERRUPT
HAND~ER
27/1/86 MBW )
BX INC
BX, 41 ASC BUF SIZE CMP
1$ JNZ
BX, BX XOR
ASC IN 2+ , BX MOV
STIAL, 41 20 MOV
41 20 , AL OUT
DS POP DX POP
BX POP AX POP
IRET
1$:
7
8
9
10
11
12
13 FORTH
14
15 -->
Screen 41 79
o ( V21/V23 MODEM INTERRUPT HANDLER
1 HEX
PREV ASC VEC 2@ OR 0=
2 : ASC-TRAP
IF -INT=VEC @L
3
INT-VEC 2+ @L
4
PREV_ASC_VEC 2!
5
6
THEN
?CS: INT-VEC 2+ !L
7
ASC INT INT-VEC !L
8
27/1/86 MBW )
9
10
11
12
13
14
15 -->
Screen 41 80
o ( V21/V23 MODEM
INTERRUPT HANDLER
1
2 : ASC-RELEASE
3
4
5
6
7
8
9
PREV ASC VEC 2@
INT-VEC 2+ !L
INT-VEC !L ,
10
11
12
13
14
15 -->
Figure 14. International Modem FORTH Screens (Continued)
4-70
27/1/86 MBW )
Application Note
2400/1200/300 bps International Modem Design
Screen It 81
o ( V21/V23 MODEM
INTERRUPT HANDLER
27/1/86 MBW )
1 HEX
2 : ASC-ENB
21 PC@
INT MASK NOT
21 PC!
3
4
5
6
7
8
9
AND
ASC IN OFF ASC OUT OFF
ASC:BUF ASC_BUF_SIZE ERASE
10
11
12
13
14
15 -->
Screen It 82
o ( V21/V23 MODEM
INTERRUPT HANDLER
27/1/86 MBW )
1 HEX
2
21 PC@
INT MASK OR
21 PC! :
3 : ASC-DSB
4
5
6
•
7
8
9
10
11
12
13
14
15 -->
Screen It 83
o ( V21/V23 MODEM
INTERRUPT HANDLER
1
2
ASC-ON
ASC-TRAP
ASC-ENB
ASC-OFF
ASC-DSB
ASC-RELEASE
3
4
5
6
7
8
9
10
11
12
13
14
15 -->
Figure 14. International Modem FORTH Screens (Continued)
4-71
27/1/86 MBW )
2400/1200/300 bps International Modem Design
Application Note
Screen # 84
o ( V21/V23 MODEM
1 HEX
INTERRUPT
HANDLE~
27/1/86 MBW )
2
3
4
ASC TX WAIT
BEGIN ASC PORT 1 UNTIL;
-
!ASC
ASC_TX_WAIT
PC@
40 AND
5
6
ASC_PORT PC!
7
8
9
10
11
12
13
14
15 -->
Screen # 85
o ( V21/V23 MODEM
INTERRUPT HANDLER
27/1/86 MBW )
1
2 HEX HERE OFFFO U>
3
4 .IF
5
6
7
8
9
10
11 .THEN
12 -->
13
14
15
CR
CR
CR
CR
FORGET COM1?
DECIMAL
." ERROR .... MUST BE LOADED BELOW FFFO ..
FORGET-MOD
Screen # 86
o ( V21/V23 MODEM DUMB TERMINAL
1 FORTH DEFINITIONS DECIMAL
2 HEX
3
( --- )
4 : TALK
5
6
27/1/86 MBW )
BEGIN
7
8
9
10
11
12
13
14
AGAIN
15 DECIMAL -->
CR ." TERMINAL ON LINE • .
?ASC
IF
@ASC 7F AND EMIT
THEN
?TERMINAL
IF
KEY DUP 27 =
IF
DROP CLS QUIT
ELSE !ASC
THEN
THEN
Figure 14.
.. CR CR ASC-ON
International Modem FORTH Screens (Continued)
4-72
Application Note
240011200/300 bps International Modem Design
Screen # 87
o ( V21/V23 MODEM TIMERS
1 DECIMAL
2
ALL;
3
MS
4
0 DO 22 0 DO LOOP LOOP
5
SEC
6
1000 * MS
27/1/86 MBW )
7
8
9
10
11
12
13
14 DECIMAL
15 -->
Screen # 88
o ( V21/V23 MODEM
INITIALISATION
27/1/86 MBW
1 HEX
2
INIT.8255
81 233 PC! ; ( 2 1/2 OUTPUT PORTS 1/2 INPUT
3 : RESET.MODEMS
231 PC@ DUP DF AND
SET PB5 TO 0 )
4
231 PC!
5
20 MS
6
20 OR 231 PC!
SET PB5 TO 1
7
50 MS I
8
RESET. 8530
231 PC@ DUP EF AND
SET PB4 TO 0
9
231 PC!
10
20 MS
11
10 OR 231 PC!
12
20 MS ;
13 : INIT
INIT.8255 RESET.MODEMS RESET.8530
( EVERYTHING )
14 DECIMAL
15 -->
*
Screen
89
0 ( V21/V23 MODEM
ENABLES/DISABLES
1 HEX
2
EN.RCCT/OH.M
230 PC@ BF AND
3
80 OR 230 PC!
4
EN. RCCT/OH.79 230 PC@ 7F AND
5
40 OR 230 PC!
6
EN.V24.79
230 PC@ 20 OR 230 PC!
7
EN.V24.M
230 PC@ DF "AND 230 PC!
8
EN.ANALOG.M
231 PC@ 03 OR
9
F3 AND 231 PC!
10
EN. ANALOG. 7;)
231 PC@ OC OR
11
FC AND 231 PC!
12
ENABLE. INT. 8530
1 222 PC! 10 222 PC!
13
9 222 PC! OA 222 PC!
14 DECIMAL
15 -->
Figure 14.
27/1/86 MBW
(
(
(
(
(
(
(
(
(
(
(
(
MAKE PA6=0
MAKE PA7=1
MAKE PA7=0
MAKE PA6=1
MAKE PA5=1
MAKE PA5=0
PBO/ PB1=1
PB2/ PB3=0
PBO/ PB1=0
PB2/ PB3=1
SET INT ON
MIE
International Modem FORTH Screens (Continued)
4-73
)
)
)
)
)
)
)
)
)
)
RX
•
Application Note
2400/1200/300 bps International Modem Design
Screen # 90
o ( V21jV23 MODEM
ENABLES/DISABLES
1 HEX
EN.RCCT/OH.M EN.V24.M EN.ANALOG.M
2
EN.M
( ENABLE ALL R2424 SIGNALS ) ;
3
4
5
6
7
8
EN. 79
27/1/86 MBW )
EN.RCCT/OH.79 EN.V24.79 EN.ANALOG.79
( ENABLE ALL 7910 SIGNALS ) ;
9
10
NEWC.R
11
12
NEWC.T
13
14 DECIMAL
15 -->
20E PC@ 08 OR
BEGIN 20E PC@
21E PC@ 08 OR
BEGIN 21E PC@
20E
8 =
21E
8 =
PC!
NOT UNTIL
PC!
NOT UNTIL
Screen # 91
o ( V21/V23 MODEM
R2424 BIT SETTING 1 OF 2
1 HEX
2
NOW
( FLAG REGISTER MASK -3
SWAP DUP 2SWAP SWAP ROT ROT
ROT 0 = IF
4
FF SWAP - SWAP DUP PC@
5
ROT AND SWAP PC!
6
ELSE
7
8
SWAP DUP PC@ ROT
OR SWAP PC!
9
10
THEN
27/1/86 MBW )
11
12
13
14
15 -->
Screen # 92
o ( V21/V23 MODEM
R2424 BIT SETTING 2 OF 2
27/1/86 MBW )
1
DUP 20A >= IF
2
DUP 20D <= IF
3
NEWC.R ELSE
4
DUP 219 >= IF
5
DUP 21D <= IF
6
NEWC.T
7
THEN
8
THEN
THEN
9
10
THEN DROP
11
12
13
14
15 -->
Figure 14.
International Modem FORTH Screens (Continued)
4-74
Application Note
2400/1200/300 bps International Modem Design
Screen # 93
o ( V21/V23 MODEM
R2424 cIT t·H,!::':.i<;r~,';
1 HEX
2
IS
(REGISTER MASK -- BIT VALUE
27/1/86 MBW )
3
4
SWAP PC@ AND IF 1 ELSE 0 THEN
~
5
6
7
8
9
10
11
12
13
14 DECIMAL
15 -->
Screen # 94
o ( V21/V23 MODEM
R2424 RECEIVER BIT MASKS
1 HEX
2
BUS.R
20D 80
3
CRQ.R
20D 40
4
LCD
20D 04
5
AL.R
20B 01
6
ERDL.R
20A 80
7
RDL.R
20A 40
8
DL.R
20A 20
9
ST.R
20A 20
10
TONE
208 80
11
ATD
208 40
12
TM
208 02
13
RLSD
208 01
14 DECIMAL
27/1/86 MBW )
•
15 -->
Screen # 95
o ( V21/V23 MODEM
R2424 TRANSMITTER BIT MASKS
1 HEX
2
DDRE
21E 01
3
BUS.T
21D 80
4
CRQ.T
21D 40
DATA
5
21D 20
6
AAE
21D 10
7
DTR
21D 08
8
DSRA
21C 80
9
GTE
21B 10
10
GTS
21B 08
11
3DB
21B 04
12
DTMF
21B 02
13
AL.T
21B 01
14 DECIMAL
15 -->
Figure 14.
International Modem FORTH Screens (Continued)
4-75
27/1/86 MBW )
i·
Application Note
2400/1200/300 bps International Modem Design
Screen # 96
R2424 TRANSMITTER BIT MASKS
o ( V21/V23 MODEM
1 HEX
21A 80
2
ERDL.T
3
RDL.T
21A 40
21A 20
4
DL.T
21A 10
5
ST.T
6
RTRN
219 40
219 20
7
ORG
219 10
8
LL
219 08
9
RTS
219 04
10
CC
219 02
11
EF
218 80
12
DLO
218 40
13
CTS
14 DECIMAL
15 -->
27/1/86 MBW )
Screen # 97
o ( V21/V23 MODEM
R2424 TRANSMITTER BIT MASKS
1 HEX
2
DSR
218 20 ;
3 : RI
218 10 ;
27/1/86 MBW )
4
5
6
7
8
9
10
11
12
13 DECIMAL
14 -->
15
Screen # 98
0 ( V21/V23 MODEM
R2424 MULTIPLE BITS
1 HEX
2 : V.22/1200
20A PC@ F9 AND 09 OR 20A
3
NEWC.R
4
21A PC@ F9 AND 09 OR 21A
5
NEWC.T ;
6
V.22/2400
20A PC@ FD AND OD OR 20A
7
NEWC.R
8
21A PC@ FD AND OD OR 21A
9
NEWC.T ;
10
SPEED?
209 PC@ 10 / DUP 4 / 4 *
11
12
13
14 DECIMAL
15 -->
Figure 14.
27/1/86 MBW )
PC!
SET RX MODE BITS
PC!
SET TX MODE BITS
PC!
PC!
-
( -- VALUE OF BITS )
International Modem FORTH Screens (Continued)
4-76
Application Note
240011200/300 bps International Modem Design
Screen # 99
o ( V21/V23 MODEM R2424 TRANSMIT LEVEL
27/1/86 MBW )
1 HEX
ODB
21B PC@ OF AND 00 OR 21B PC! NEWC.T
2
3
-2DB
21B PC@ 3F AND 20 OR 21B PC! NEWC.T
21B PC@ 5F AND 40 OR 21B PC! NEWC.T
4
-4DB
5
-6DB
21B PC@ 7F AND 60 OR 21B PC! NEWC.T
21B PC@ 9F AND 80 OR 21B PC! NEWC.T
6
-8DB
-10DB 21B PC@ BF AND AO OR 21B PCI NEWC.T
7
8
-12DB 21B PC@ OF AND CO OR 21B PCI NEWC.T
9
-14DB 21B PC@ FF AND EO OR 21B PC! NEWC.T
10
11
12
13
14 DECIMAL
15 -->
Screen # 100
o ( V21/V23 MODEM 8530 SETUP
27/1/86 MBW )
)
1 ( THIS DEFAULT SETTING CONFIGURES THE 8530 FOR 8 BIT DATA,
2 ( 1 STOPBIT, ENABLES THE TRANSMITTER & RECEIVER, SETS DTR, RTS)
3 ( SETS THE CLOCKS, XTAL I/P,AND THE BIT RATE GENERATOR FOR 2400)
4 HEX
5
DEFAULT. 8530
ENABLE. INT. 8530
6
4 222 PCI 44 222 PCI ( SET RX 8 BITS X16 CLOCK
7
3 222 PC! CO 222 PC! ( 1 STOPBIT
8
5 222 PCI 60 222 PC! ( SET TX 8 BITS
9
B 222 PC! 04 222 PC! ( CLOCK OPTIONS
10
C 222 PC! lE 222 PC! ( BAUD RATE GEN LOW FOR 2400
11
0 222 PC! 00 222 PC! ( BAUD RATE GEN HI FOR ALL
12
E 222 PC! 01 222 PC! ( ENABLE BIT RATE GEN
)
13
3 222 PCI C1 222 PCI ( ENABLE RX
)
14
5 222 PC! 68 222 PC! ( ENABLE TX
)
15 DECIMAL -->
Screen # 101
o ( V21/V23 MODEM CHANGE 8530 PARAMETERS
27/1/86 MBW )
1 HEX
2
RX.ENABLE
3 222 PCI C1 222 PC!
3
RX.DISABLE
3 222 PC! CO 222 PC!
RTS.8530.0N
4
5 222 PC! EA 222 PC!
RTS.8530.0FF
5 222 PC! E8 222 PC!
5
300BPS.8530
6
C 222 PC! FE 222 PCI
7
1200BPS.8530
C 222 PC! 3E 222 PC!
2400BPS.8530
C 222 PC! 1E 222 PC!
8
DTR/RTS.8530.0FF 5 222 PC! 68 222 PC!
9
10
DTR.8530.0N
5 222 PC! E8 222 PCI
11
12
13
14 DECIMAL
15 -->
Figure 14. International Modem FORTH Screens (Continued)
4-n
•
2400/1200/300 bps International Modem Design
Application. Note
Screen # 102
o ( V21/V23 MODEM DAA CONTROL MASKS
1 HEX
FLAG
232 04
2
CCT
FLAG
232 08
3
OH
FLAG
4
RCCT.79 232 20
FLAG
232 40
5
OH.79
27/1/86 MBW )
6
7
8
9
10
11
12
13
14 DECIMAL
15 -->
Screen # 103
o ( V21/V23 MODEM R2424 BASIC MODEM SETUP
1 HEX
2
DEFAULT. 2424
3
INIT
4
EN.M
V.22/2400
5
6
1 BUS.R NOW 1 BUS.T NOW
7
1 DTR NOW
8
1 RTS NOW
9
1 AAE NOW
10
ODB
( NO ATTENUATION BEFORE DAA )
11
DEFAULT. 8530
12
13
14 DECIMAL
15 -->
Screen # 104
o ( V21/V23 MODEM 8530
1 HEX
2
RXREADY?
BEGIN 222
3 : TXREADY?
BEGIN 222
4 : DCD.8530? BEGIN 222
5
STATUS
27/1/86 MBW )
27/1/86 MBW )
PC@ 1 AND 1 = UNTIL ;
PC@ 4 AND 4 = UNTIL ;
PC@ 08 AND 08 - UNTIL
6
7
8
9
10
11
12
13
14 DECIMAL
15 -->
Figure 14. International Modem FORTH Screens (Continued)
4-78
Application Note
240011200/300 bps International Modem Design
Screen # 105
o ( V21/V23 MODEM PHONE NUMBER ENTERING
1 HEX
2 0 VARIABLE PHONE. NUMBER 20 ALLOT
3
PHONE.NUMBER.PROMPT
4
." ENTER PHONE NUMBER ..
27/1/86 MBW )
5
6
7
READY. TO. DIAL?
BEGIN DDRE IS UNTIL :
8
9
10
11
12
13
14 DECIMAL
15 -->
Screen # 106
27/1/86 MBW )
o ( V21/V23 MODEM DIALER
1 HEX
2
DIAL PHONE.NUMBER.PROMPT
3
PHONE.NUMBER 20 EXPECT CR
4
1 DTMF NOW 1 CRQ. T NOW ." DIALING # .. 1 SEC PHONE.NUMBER
5
BEGIN DUP 1+ SWAP C@ DUP DUP 0=
6
IF
7
DROP DROP 1
ELSE DUP 44 - IF
8
2 SEC DROP DROP 0
9
ELSE READY.TO.DIAL?
10
OF AND 210 PCI EMIT 0
11
THEN
12
13 THEN
14 UNTIL DROP READY.TO.DIAL? FF 210 PC! -14DB CLS
15 DECIMAL -->
Screen # 107
27/1/86 MBW )
o ( V21/V23 MODEM 7910 CONFIGURATION
1 HEX
230 PC@ EO AND 05 OR 230 PC!
2
V21.ANS.7910
230 PC@ EO AND 04 OR 230 PCI
'3
V21.0RG.7910
230 PC@ EO AND 06 OR 230 PC!
V23.7910
4
230 PC@ EO AND 07 OR 230 PC!
5
V23.EQU.7910
6
7
8
9
10
11
12
13
14 DECIMAL
15 -->
Figure 14, International Modem FORTH Screens (Continued)
4-79
•
Application Note
, 2400/1200/300 bps International Modem Design
Screen # 108
o ( V21jV23 MODEM 7910 CONNECT V.21
1 HEX
2
CONNECT.V21.0RG
3
CLS." V.21 300BPS MODE" CR
4
DEFAULT. 2424
V21.0RG.7910
5
6
DIAL
7
1 RCCT.79 NOW 1 OH.79 NOW EN.79
0 CRQ.T NOW
8
9
DTR.8530.0N
DCD.8530?" CARRIER DETECTED • • • ON LINE"
10
11
RTS.8530.0N
12
300BPS.8530 TALK
13
14 DECIMAL
15 -->
Screen # 109
o ( V21/V23 MODEM 7910 CONNECT V.23
1 HEX
2
CONNECT.V23.0RG
3
CLS." V.23 1200BPS MODE" CR
4
DEFAULT. 2424
V23.7910
5
6
DIAL
7
1 RCCT.79 NOW 1 OH.79 NOW EN.79
8
0 CRQ.T NOW
9
DTR.8530.0N
10
DCD.8530?" CARRIER DETECTED • • • ON LINE"
11
RTS.8530.0N
1200BPS.8530
12
TALK
13
14 DECIMAL
15 -->
Screen # 110
o ( V21/V23 MODEM 2424 CONNECT V.22
1 HEX
2
CONNECT.V22.0RG
3
CLS." V.22 1200BPS MODE" CR
4
DEFAULT. 2424 V.22/1200 1200BPS.8530
5
DIAL
6
BEGIN CTS IS 1 = UNTIL
"CARRIER DETECTED
7
CR CR TALK
;
CONNECT.V22.2400
8
9
CLS." V.22 2400BPS MODE" CR
10
DEFAULT. 2424
DIAL
11
12
BEGIN CTS IS 1 = UNTIL
"CARRIER DETECTED
13
CR CR TALK
14 DECIMAL
15 -->
CR CR
27/1/86 MBW )
CR CR
27/1/86 MBW )
• • • ON LINE "
• • • ON LINE "
Figure 14. International Modem FORTH Screens (Continued)
4-80
27/1/86 MBW )
Application Note
2400/1200/300 bps International Modem Design
*
Screen
111
o ( V21/V23 MODEM V.22 ANSWER MODE CONNECTIONS
27/1/86 MBW )
1 HEX
2
V22BIS.CONNECTION
." CONNECTED TO V.22 BIS MODEM AT 2400 BPS" CR CR
3
4
TALK
5
6
7
8
9
V22.CONNECTION
." CONNECTED TO V.22 MODEM AT 1200 BPS ..
1200BPS.8530
TALK
CR CR
10
II
12
13
14 DECIMAL
15 -->
Screen # 112
o ( V21/V23 MODEM V.21/V.23 ANSWER MODE CONNECTIONS 27/1/86 MBW )
1 HEX
2
V21.CONNECTION
3
." CONNECTED TO V.21 MODEM AT 300BPS .. CR CR
4
V21.ANS.7910
5
1 RCCT.79 NOW 1 OH.79 NOW EN.79
6
DTR.8530.0N RTS.8530.0N
7
300BPS.8530
8
TALK
7
9
V23.CONNECTION
10
." CONNECTED TO V.23 MODEM AT 1200BPS" CR CR
II
V23.7910
12
1 RCCT.79 NOW 1 OH.79 NOW EN.79
13
DTR.8530.0N
14
1200BPS.8530
15
TALK
DECIMAL -->
Screen # 113
o ( V21/V23 MODEM AUTO ANSWER MODE 1 OF 2
1 HEX
2
AUTO. ANSWER
3
DEFAULT. 2424
4
CLS." UNIVERSAL ANSWER MODE" CR
5
." WAITING TO BE CALLED .. CR
6
BEGIN RI IS UNTIL
7
." RING DETECTED •
.. CR
8
BEGIN DSR IS UNTIL
9
.. DATA SET READY ON
.. CR
10
1 SEC
II
12
13
14 DECIMAL
15 -->
Figure t 4.
International Modem FORTH Screens (Continued)
4-81
27/1/86 MBW )
II
Application Note
2400/1200/300 bps International, Modem Design
Screen # 114
O( V21/V23 MODEM
AUTO ANSWER MODE 2 OF 2
27/1/86 MBW )
1 HEX
2
SPEED? DUP 3 = IF V22BIS.CONNECTION ELSE
3
DUP 2 = IF V22.CONNECTION
ELSE
4
THEN THEN DROP
5
RLSD IS IF V23.CONNECTION ELSE V21.CONNECTION THEN
6
7
8
9
10
11
12
13
14 DECIMAL
15 -->
Screen # 115
o ( V21/V23 MODEM MENU SCREEN
27/1/86 MBW )
1 HEX
2
MENU INIT BEGIN
CLS A 3 GOTOXY
3
" ROCKWELL INTERNATIONAL'S
" CR
4
CR
A SPACES
" INTERNATIONAL MODEM ••.•
" CR
5
CR CR A SPACES
"Fl V.21 ORIGINATE
" CR
6
A SPACES
"F2 V.22 ORIGINATE 1200
" CR
7
A SPACES
"F3 V.22 ORIGINATE 2400
" CR
8
A SPACES
"F4 V.23 ORIGINATE
" CR
9
A SPACES
"F5 AUTO ANSWER/CONFIGURE " CR
10 PCKEY DROP DUP 3B
IF CONNECT.V21.0RG ELSE
11
DUP 3C = IF CONNECT.V22.0RG ELSE
12
DUP 3D
IF CONNECT.V22.2400 ELSE
13
DUP 3E
IF CONNECT.V23.0RG ELSE
14
DUP 3F
IF AUTO. ANSWER
15 THEN THEN THEN THEN THEN SWAP DROP UNTIL ; MENU DECIMAL --> "
Screen # 116
o
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Figure 14.
International Modem FORTH Screens (Continued) ,
4-82
Application Note
'1'
Quality of Received Data
for Signal Processor-Based Modems
Rockwell
by Carlos A. Laiz, Product Applications Engineer
Semiconductor Products Division, Newport Beach, California
INTRODUCTION
block diagrams that relate the RAM access codes to specific
functions are shown in Figures 1 through 4. Refer to the applicable modem data sheet for specific details regarding an
individual modem.
This application note provides the modem design engineer
with detailed information on the generation and interpretation of diagnostic data featured in Rockwell's signal processor
(SP)-based modems.
Rockwell's plug-compatible SP-based modems can generate a
variety of diagnostic data. This data is extremely useful in the
evaluation of modem performance and line conditions. A microprocessor interface can readily access diagnostic data and other
useful signals via the SP interface memory.
EYE PATTERN
A quadrature eye pattern is an extremely useful diagnostic tool.
The visual display of an eye pattern can be monitored to identify common line disturbances, as well as defects in the
modulation/demodulation processes.
The diagnostic capabilities of specific Rockwell modems are
summarized in Table 1.
The ideal eye patterns or signal constellations for the various
encoding methods are illustrated in Figures 5 through 10. By
performing digital-to-analog (D/A) conversion of the received
signal point data (refer Table 2, Node 9), an eye pattern can be
displayed on an oscilloscope. Two methods of eye pattern
generation are available:
ACCESSING DIAGNOSTIC DAT4
Diagnostic data can be readily accessed via the microprocessor
interface. The host processor must store the access code corresponding to the desired data in the RAM access register (See
Table 2). The signal processor then stores the desired data in
diagnostic data registers. The data available flag (R48DP,
R96DP, R96FT and R96FAX only) in the respective interface
memory sets when the signal processor writes data into
diagnostic register zero and resets when the host reads data
from register zero and is used to handshake with the diagnostic
data registers. Diagnostic data is generated in 16-bit double
precision form, although for most applications only the most
significant byte of data is necessary. The RAM access codes
for the SP-based modems are shown in Table 2. Functional
1. The microprocessor can read the received signal points and
then write this data into two memory mapped D/A converters.
Figure 11 shows a typical microprocessor interface eye pattern generator. A typical parallel eye pattern algorithm is
shown in Figure 12.
2. High speed modems (4800 bps and above) can generate
diagnostic data serially through hardware pins in the modem
connector.
Table 1. Summary of Diagnostic Capabilities for SP-8ased Modems
Eye Pattern
Error
Vector
Phase
Error
Access to
SP RAM
Space'
Parallel MPU Bus
EQM
Value
R1212M
R1212DC
X
X
1
1
X
X
X
X
X
X
R2424M
R2424DC
X
X
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Modem
R48DP
R96DP
R96FT
R96FAX
Serial
X
X
X
X
X
X
X
X
Notes:
1. EQM may be computed by the host processor from the error vector data.
2. See RAM access codes (Table 2) and block diagrams (Figures 1-4).
Document No. 29220N71
Application Note
4-83
Order No. 671
February 1985
•
'
Application Note
Signal Processor-Based Modems
Table 2.
R1212M/DC
R2424M/DC
Node
No.
Function
1
Received Signal
Samples (and Output)
Access Chip
Code. No.
RAM Access Codes
R48DP/R96DP
Reg.
No.
RAM
X
CO
Access Chip
Y
No.
R96FT
Reg.
No.
-
1
2,3
RAM
X
DC
R96FAX
Access Chip
Y
No.
Reg.
RAM Chip
No. Access No.
Reg.
No.
-
1
2,3
CO
0
2,3
2
Demodulator Output
56
0
2,3,4,5
C2
42
1
0,1,2,3
CO
40
1
0,1,2,3
42
0
0,1,2,3
3
Low Pass FiRer Output
40
0
2,3,4,5
D4
54
1
0,1,2,3
DD
5D
1
0,1,2,3
54
0
0,1,2,3
4
Average Energy
-
04
1
0,1
-
32
1
0,1
DC
0
2,3
5
AGC Gain Word
81
-
1
2,3
2E
1
2,3
81
0
2,3
6
Equalizer Input
CO
40
2
0,1,2,3
40
2
0,1,2,3
40
1
0,1,2,3
01-20
2
0,1,2,3 81-AO
01-20
2
0,1,2,3 01-20
1
0,1,2,3
El
61
2
0,1,2,3
El
61
2
0,1,2,3
61
1
0,1,2,3
7
Equalizer Taps
8
Unrotated Equalizer
Output
9
Rotated Equalizer
Output (Received
Point Eye Pattern)
11
0
2,3,4,5
A2
22
2
0,1,2,3
E2
62
2
0,1,2,3
22
1
0,1,2,3
10
Decision Points (Ideal
Eye Pattern Points)
51
0
2,3,4,5
E2
62
2
0,1,2,3
E8
68
2
0,1,2,3
62
1
0,1,2,3
11
Error Vector
(Rotated Error)
52
0
2,3,4,5
E3
63
2
0,1,2,3
E5
65
2
0,1,2,3
63
1
0,1,2,3
12
Rotation Angle
12
0
4,5
-
00
2
0,1
A7
2
2,3
00
1
0,1
13
Frequency Correction
-
-
2
2,3
A8
1
2,3
14
EOM
AB
1
2,3
15
Dual Point
16
Group " Baseband
Signal
C8
1
2,3
17
Group" AGC
Gain Word
AD
1
2,3
18
Group" AGC
Slew Rate
AA
1
2,3
19
Group" PLL
Frequency Correction
C2
1
2,3
20
Group"
PLL Slew Rate
FO
1
2,3
21
Group"
BlacklWhite Level
2A
1
0,1
22
Self Test
Error Counter
00
0
2,3,4,5
23
Phase Error
10
0
2,3
24
Input Signal to
Equalizer Taps
41-40
0
2,3,4,5
25
Equalizer Output
53
0
2,3,4,5
01-OD
0
2,3,4,5 81-AO
CO
.
AA
A7
-
2
2,3
AE
2E
2
0,1,2,3
AC
Note: • EQM value may be computed by the host processor from error vector data, node 11.
4-84
-
2
2,3
-
Application Note
Signal Processor-Based Modems
TONE
&
FSK
DETECTOR
r-------IA
I
CARRIER
DETECTOR
l
I....--J--..., ....-""'-----,
I TRAINING
TIMING
I
I
RXSP
RECEIVER
CONFIGURATION
RECOVERY
DETECTOR
STATUS
I
I
I
I
DATA
OUTPUT
I
L
-
-
-
-
1 L....--r-----J
I
DESCRAMBLER
SYNC
TO
ASYNC
CONVERTER
TXSP
ASYNC
TO
SYNC
CONVERTER
INPUT
~;rA
r-
~ SCRAMBLER
~
,1
r+
.
DATA
ENCODER
•
,[
LOW PASS
FILTER
t
~
cow,
...
FILTER
FSK
GENERATOR
DATA CLOCK
& TIMING
t
COMPROMISE
EQUALIZER
DIGITAL TO
ANALOG
CONVERTER
t
t
SIGNAL
POINT
ROM
BAND
SPLIT
FILTER
~f
t
SELF TEST
PATTERN
GENERATOR
DATA
CLK
l4
r - - - - --'-,
COS (wt)
SIGNAL
STRUCTURE
CONTROL
~
SIN (wt)
t
-
LOW PASS
FILTER
I
L _____
fDTMF
GENERATOR
EXTERNAL
CLOCK
TRACKER
f--+
REFERENCE
Figure 1. R1212/R2424 Processing Flow Diagram
4-85
LINE
r+- INTERFACE
(DAA)
PASSBAN D
LINE
SIGNAL
--1
•
Application Note
,
Signal Processor-Based Modems
II
s
s
..--t
Ii
I
4-86
~
"0
"2-
n
a
o·
::::s
z
o
S'
IA DEVICE-TRANSMlnER
IA DEVICE-RECEIVER
~
en
RECEIVER
cO'
::::s
!.
DATA
a
"n
C1)
til
til
o
7
UJ
I»
til
C1)
Q.
5:
oQ.
C1)
Figure 3.
R96FAX (Group 2) Processing Flow Diagram
I
3
til
)"0
"2C;"
-
II)
C)"
::::s
Z
o
;TRANSMITTER
DATA
1850 Hz
£
IA DEVICE-TRANSMITTER
IA DEVICE-RECEIVER
VI
cO'
::::s
!!.
RECEIVER
DATA
"U
a
(')
CD
~";'
r
:a..
i:
o
Figure 4.
R96FAX FSK Processing Flow Diagram
a..
CD
3
(I)
Application Note
Signal Processor·Based Modems
BOUNDAfllES
•
3
•
·3j2
Q3
0
0
1
0°
0
0
0
45°
0
1
0
90·
0
1
1
135·
j2
•1
1
180°
•
5
3
0°
•
•
•
Q4
PHASE
CHANGE
Q2
1
1
1
180°
1
1
0
225°
1
0
0
270·
1
0
1
315°
ABSOLUTE
PHASE
Q1
RELATIVE
AMPLITUDE
0
3
1
5
0
j2
1
3j2
0°,90 0 ,
180°, 270·
45°,135°,
225°, 315·
Figure 5. Ideal Eye Pattern-V.29/9600 bps
90°
3
BOUNDARIES
•
180°
•
1
•1
TRIBIT ENCODING:
j2
3
•
0°
IN V.29n200 BPS FALLBACK MODE, DATA IS ENCODED IN
GROUPS OF 3 BITS OR TRIBITS. THE ENCODING IS AS FOR
V.29/9600 BPS ABOVE EXCEPT THAT: THE FIRST DATA BIT IN
TIME DETERMINES Q2 OF THE MODULATOR QUADBIT. THE
SECOND AND THIRD BITS IN TIME DETERMINE Q3 AND Q4,
RESPECTIVELY. Q1
0 FOR ALL EIGHT SIGNAL ELEMENTS.
=
270°
Figure 6.
Ideal Eye Pattern-V.29/7200 bps
4-89
•
Application Note
Signal Processor·Based Modems
90·
DIBIT ENCODING:
DATA BITS
180'
PHASE
CHANGE
00
o·
01
90·
11
180·
10
270·
RELATIVE
AMPLITUDE
CONSTANT
270·
Figure 7.
Ideal Eye Pattern-V.29/4800 bps and V.27/BIS/TER/2400 bps
90'
TRIBIT ENCODING:
TRIBIT
VALUE
o·
180·
0 0 1
0°
0 0 0
45°
0 1 0
90·
0 1 1
135·
1 1 1
180·
1 1 0
225·
1 0 0
270·
1 0 1
315·
270°
Figure 8.
V.27 BIS/TER/4800 bps
4-90
PHASE
CHANGE
RELATIVE
AMPLITUDE
CONSTANT
Application Note
Signal Processor-Based Modems
90°
•
180°
0°
DIBIT
VALUES (1200)
BIT VALUES
(600 BPS)
00
o
PHASE
CHANGE
+90°
01
11
+270°
10
+180°
270°
Figure 9.
V.22 A/B 1200 bps/SOO bps
90°
PHASE QUAD. 2
11
•
BOUNDARlls 10
180°
01
•
10
•
11
•
•
•
00
01
•
00
•
00
10
11
10
01
11
•
•
•
•
•
PHASE
QUADRANT CHANGE
1 2 -
00
2
3
3- 4
4- 1
90·
01
1- 1
2- 2
3- 3
4- 4
O·
11
1- 4
2- 1
3- 2
4- 3
270·
100
3
1 2- 4
3- 1
4- 2
180·
01
00
•
FIRST TWO BITS IN
QUADBIT [2400 BIT(S))
OR DIBIT VALUES
[1200 BIT(S))
PHASE QUADRANT 1
0°
•
•
PHASE QUAD. 3
270°
DATA IS ENCODED IN QUADBITS. THE FIRST TWO BITS OR
DIBIT SELECT ONE OF FOUR QUADRANTS. THE SECOND DIBIT
SELECTS ONE OF FOUR POINTS IN THAT QUADRANT, AS
SHOWN BELOW.
Figure 10.
V.22 BIS/4800 bps
4-91
•
Signal Processor-Based Modems
Application Note
+12Y
-12Y
°i~
FULLY
DECODED
MEMORY
LOCATION
1 ,I,~"
.. 161
LE
2
DO
X-OUT
(SCOPE)
LSB
3
D1
You!
4
D2
BUFFERED'
"PROCESSOR
DATA BUS
r0'~11"F
17J
5
D3
NES018
X-DAC
6
D4
SUM
7
D5
OFFSET
8
D6
9
D7
74LS04
... ~8
U(
.~
100pF
MSB
.a
ACOMP
IN914
~
-::j.-
1q
0.1i~r-12Y
-=0.1" 19 17J
FULLY
DECODED
MEMORY
LOCATION
:>21<0
-I.4~
II
";
O.~~"F 116
LE
Y-o UT
(SCOPE)
LSB
Yout
NE501B
Y-DAC
SUM
~21 CLK
_,.....L-.../
3
EYEY
The eye pattern consists of dots or received Signal points. Each
point represents the location of a received Signal element in the
4
5
6
10
234
10 lSB
5
6
II 12
_+----,
7
8
X-OUT
1-'-"------.....- - 0 (SCOPE)
~---4~-+-dlE
14
REF OUT
NE5018
13 REF IN
0.01"
-12V
I A
2 B
8
741164
ClK
3
4
5
6
10
11 12
2345678
10 lSB
~-------aLE
Y-OUT
r----IN-9-1-4B-.....- - O (SCOPE)
14 REF OUT
13 REF IN
NE50lB
Nc 12 ADJ
0.01"
-12V
+ 1 2 V - - - -.....
*,O.I"F
Figure 13,
Serial Eye Pattern Generator
4-94
Application Note
Signal Processor-Based Modems
t.....__.....1
EyESyNClL_ _ _ _ _....
MSB
NOTE: BITS 9 AND 10 ARE IGNORED
Figure 14.
Serial Eye Pattern Signal Timing
ERROR VECTOR AND EQM VALUES
baseband signal plane. In polar coordinates each point
represents a magnitude and differential phase shift. Eye pattern
data is updated at the baud rate so the oscilloscope display
appears to be a continuous signal constellation.
Transient phenomena are difficult to observe in a quadrature
eye pattern. Also, the proper interpretation of the eye pattern
is a function of the observer's training and requires constant
attention. Rockwell's signal processor modems generate error
vector and Eye Quality Monitor (EQM) data that are more suitable
for microprocessor manipulation and interpretation.
For a DPSK (Differential Phase Shift Keyed) modem, the phase
shift from one signal element to the next is decoded to recover
data. For a QAM (Quadrature Amplitude Modulation) modem,
both amplitude and differential phase shift are decoded to
recover data.
The error vector is defined as the angle and magnitude difference
between an actual received signal point and its ideal location
in the baseband signal plane (refer to Figure 16). Error vectors
are represented as complex numbers whose real and imaginary
components may be read out of the modem's diagnostiC
registers once per baud. An EQM value may be obtained by processing the error vector data to obtain a positive hexadecimal
value whose magnitude is an indicator of the quality of the
received signal or probability of error of received Signal points.
In the case of high speed modems (R48DP, R96DP, R96FT, and
R96FAX), the error vector is processed by the SP devices and
the EQM value is available through the diagnostic data registers.
For medium speed modems (R1212 and R2424), the EQM value
may be computed by the host processor using the error vector
data. An algorithm for computing EQM values is given below.
Assume a V.2211200 bps configuration (R1212 modem), and that
initially a dot is displayed at paint 1 of Figure 9. If the first dibit
received is 10, the paint displayed will be point 2, corresponding to a 1800 shift in phase. If the second dibit is a 00 (90°),
point 3 will be displayed. In this fashion a continuous stream
of random data produces the display of Figure 9.
TYPICAL LINE DISTURBANCES
Actual received signal points are distorted by one or more types
of line disturbances such as noise, phase or amplitude hits,
phase or amplitude jitter, harmonic distortion and drop-outs.
White noise produces a smearing of each signal constellation
point around its ideal location (see Figure 15A).
It is desirable to have a quantity whose magnitude is proportional to the time average of the error vector magnitude. The
error vector magnitude may be approximated by its squared
magnitude eliminating the computation of a square root:
Phase jitter produces periodic phase smearing with little or no
amplitude effect (see Figure 158).
Harmonic distortion produces a non-periodic amplitude smearing with little phase effect (see Figure 15C).
Amplitude jitter produces an effect similar to harmonic distortion, but in this case the disturbance is periodic.
Re (ERROR)2 + 1m (ERROR)2
An amplitude (or phase) hit is associated with an instantaneous
high error in the amplitude (or phase) signal component.
The squared magnitude may then be averaged by a digital filter
of transfer function (see Figure 17):
The degree of smearing in the eye pattern is proportional to the
severity of the particular disturbance. These disturbances may
occur in combination producing more complex smearing of the
eye pattern.
H(Z) =
1 _ <>~Z-l
(Eq. 1)
(Eq.2)
The coeffiCients <> and ~ may be computed by a Z-domain
approximation to an RC network of transfer function
(see Figure 18):
A point falling within the signal space delimited by boundaries
is decoded by the modem as if it were located at the ideal point
within that space. When a line disturbance causes the signal
point to cross a decision boundary, the received signal pOint is
incorrectly decoded.
H(s) =
4-95
(Eq.3)
II
Signal Processor-Based Modems
Application Note
-------------------------------------------------------------------------------,
.·..:i.. ::'.
...
....
.
-:.~:.
... ...
:;
..
:~
~
~
~:
~
::....-:*:
B. PHASE JITTER
A. WHITE NOISE
..........
".:.'
C. HARMONIC DISTORTION
(NON-PERIODIC) AMPLITUDE
JITTER (PERIODIC)
Figure 15. Typical Line Disturbancas
4-96
Signal Processor-Based Modems
Application Note
Re(ERROR)2
RESULTANT
ERROR VECTOR
ERROR
MAGNI-
INPUT
Figure 17.
IMAGINARY
ERROR COMPONENT
180·
+
AVERAGE
ERROR
MAGNITUDE
Im(ERROR)2
EQM
) - - - - _ - 0 OUTPUT
Digital Energy Averaging Filter
R
v:T~
:~'#/'"
:~IDEAL
POINT
270·
Figure 16.
Figure 18.
Error Vector Phase Error/EQM
The EOM value is the filtered squared magnitude of the error
vector. These values represent the probability of error and can
be used to implement a discrete Data Signal Ouality Detector
circuit (circuit 110 of CCITT recommendation V.24 or circuit CG
of RS-232-C recommendation) by comparing the EOM value
against an experimentally obtained criteria (refer to Figures 19
and 20).
Substituting variables (first backward difference approximation) S = 1 - Z-'IT yields a and (3 (7 = RC, T = sampling
period 11T = 7200 Hz for R12121R2424):
a =
+71T
+ 72007
71T
(3 =
1 +71T
1
+ 72007
(Eq. 4)
(Eq.5)
Bit Error Rate (BER) curves as a function of the signal-ta-noise
ratio (SNR) are used to establish a criteria for determining the
acceptance of EOM values. Figure 20 is a typical BER curve
showing the meaning of a given EOM value in terms of BER
and SNA. From an EOM value, the host processor can determine an approximate BER value. If the BER is found to be
unacceptable, the host may cause the modem to fall-back to
a lower speed to improve BEA.
Rs-writing the transfer function H(Z) (Equation 1) as a difference
equation:
yin)
=
au(n) + (3y(n -1)
Equivalent Analog RC-Network
(Eq.6)
It should be noted that the meaning of EOM varies with the type
of line disturbance present on the line and with the various configurations. A given magnitude of EOM in V.29/9600 does not
represent the same BER as in V.29/4B00. The former configuration has 16 signal points that are more closely spaced than the
four signal points in the latter, resulting in a greater probability
of error for a given level of noise or jitter. Also, the type of disturbance has a significant bearing on the EOM value. For example,
white noise produces an evenly distributed smearing of the eye
pattern with about equal magnitude and phase error while phase
jitter produces phase error with little error in magnitude.
Letting the input sequence u(n) = Re (ERROR (n»)" + 1m
(ERROR (n»)2 and the output yin) = EOM(n) we obtain:
EOM(n) = a IRe(ERROR(n»)" + Im(ERROR(n»)"] + (3EOM(n-1)
(Eq.7)
where: EOM(n)
EOM(n-1)
= Current EOM value.
= EOM value delayed by one sample
period.
Re (ERROR (n)l = Real component of the error vector.
Re (ERROR (n) = Imaginary component of the error
vector.
Recalling that EOM is an average of the squared magnitude of
the error vector, it can be seen that the correspondence of EOM
to SNR (and hence BER) is dependent upon the signal structure of the modulation being used and the type of line disturbance present.
If we choose 7 = 0.1 seconds and 11T = 7200 Hz then, a =
0.001386962 and {3 = 0.998613037. Note that a + (3 = 1 and
a «{3 < 1.
~-97
•
Application Note
Signal Processor-Based Modems
37
EQM VS. SNR
UNCONDITIONED 3002 LINE
T EQUALIZER
- 20 DBM SIGNAL LEVEL
3 KHZ FLAT WEIGHTING
32
20
28
23
)(
~
1E
:IE
fa
19
14
OF
0/.
05
0
0
5
10
15
50
25
55
60
65
SNR (dB)
Figure 19.
Typical Eye-Quality Versus Signal-To-Noise Ratio for V.29/9600 (R96FAX)
4-98
70
Application Note
Signal Processor-Based Modems
4800 BPS V.27 TER
2400 BPS V.27 TER
~
9600 B\ V.29
1o-3r-------------------T-------~~------,----~---------~,-T----------------T-~--------------,
10-'
w
l-
e
a:
a:
~
a:
w
Ii
•
10-"
'00
10-6LO-------------------L5------------------1~0--~~---------~15~----~~--~---~-L---~~~25
SIGNAL TO NOISE RATIO (dB)
• EQM VALUE
UNCONDITIONED 3002 LINE, T-EQUALIZER, -20 dBm SIGNAL LEVEL, 3 kHz FLAT WEIGHTING
Figure 20.
Typical Bit Error Rate Versus SNR and EQM
SCALING OF SP SIGNALS (R48DP, R96DP,
R96FT, AND R96FAX)
AGe Gain in dB
The following list of formulas can be used to obtain diagnostic
data in engineering units. Typical values or ranges for the data
are also given.
=
50 _ AGC Gain Word x 0.097 dB
(100)8
2. Average Power Word (16 bltsl-Node 4
Typical value: 42116 = 0889'6 (corresponding to 0 dBm)
CONVERSION FORMULAS, RANGES AND
TYPICAL VAWES FOR R48Dp, R96DP AND
R96FAX MODEMS
1. AGe Gain Word (16 bits unslgned)-Node 5
Range:
OFOO'6 - 7FFF'6 for LRTH = 0 (- 43 dBm Threshold)
0640'6 - 7FFF'6 for LRTH = 1 (- 47 dBm Threshold)
Post-AGe Average
Power in dBm
= 10 Log (Average Power Word) dBm
(889)'6
Pre-AGe Average
Power in dBm
(Post AGe Avg. Power in dBm
= - AGC gain in dB) dBm
3. AID Sample Word (16 bits two's complement)-Node 1
(Refer to Figure 21 for the location of V1NT and VEXT signals)
4-99
Application Note
Signal Processor-Based Modems
4. Rotation Angle Word (16 bits two's complement)Node 12
VeXT
CHANNEL
Range: -180 0
V,NT SIGNAL
IA DEVICE r-----~PROCESSOR
+ 180 0
-
Rotation Angle in degrees = Rot. Angle Word x 180 0
2'6
5. Frequency Correction Word (16 bits two's complement)Node 13 (Deviation from carrier in Hz)
AGC WORD
Range: FC01'6 - 0400'6 (±37.5Hz)
Figure 21.
Freq. Correction in Hz = (Freg . Correction word)
External and Internal Voltages
2'6
x (Baud Rate in Hz) Hz
6. Error Vector Real (16 bits two's complement) and
V,NT = Signed, two's complement 16-bit AID Word
(100)8
x ..l...Volts
256
Imaginary (16 bits two's complement) Words
(Refer to Table 3.)
7. Scaled Signal Points (16 bits two's complement)
(V.29 to V.27)
(Refer to Figure 22 and Table 4.)
Table 3.
Configuration
V.29
V.29
V.29
V.27
V.27
Error Vector Maximum Values
Magnitude
Bit Rate
(BPS)
Real Error
Imag. Error
VRe2 + 1m2
9600
7200
4800
4800
2400
""2-n
a
0"
250msDELAY
-I
TONE BIT
IDEAL RINGBACK
TONE BIT
IDEAL BUSY TONE
~r-------------------~I
250 ms
500 ms
DELAY
DELAY
....-----,j..
-.J
:::s
I-
16 SAMPLES, COUNTER = 0
IIIIII~I
OJ:
Z
-l
500ms
I- ON
1111111111111111 OFF
L
+111111
~
ON
OFF
16 SAMPLES, COUNTER '" 8
-150 ms DELAr-
:!:
TONE BIT
FAST RINGBACK
.------------~
--l
500ms
I-
ON
1111111111111111
~
OFF
0l:Io
N
0l:Io
16 SAMPLES, COUNTER = 0
-+j
750 ms BETWEEN ON TIMES
r-
1
.---_____..;
~i~~TRINGBACK-.J
--l
I
•
:a
.....
N
.....
N
I--
250 ms DELAY
500 ms
I--
ON
11111 111111111111
~
OFF
o
c
16 SAMPLES, COUNTER", 0
i"
,;; 250 ms BETWEEN ON TIMES
,;;250 ms DELAY
~_-I...;
~~i~TRINGBACK-.J
I
f--
--l
I
soo ms
IoN
1'111 III 11111 II II OFF
I»
:::s
0.
c}
:::s
16 SAMPLES
COUNTER = 0
CD
i
sa
0"
Figure 6.
Timing for Call Progress Tone Detection Routine
II
:::s
R2424-R1212 Auto Dial and Tone Detection
Application Note
(
)
START
t
,
I
SET BUS BITS TO 1
I
I
SETORG
I
TOO
t
I
SET DTR TO 1
I
SET RTS TO 1
I
I
I
I
I
~
RESET CRa BITS TO 0
y
,
I
I
1 SECOND DELAY
I SET DTMF TO 0 OR 1 I
t
I ENTER TELEPHONE NUMBER I
t
I
I
SET CRa TO 1 IN TX
t
I
L..!i..(
I
150 ms DELAY
I
DLO AND TONE
=1 ?
Y
-t
~
/
,Y
I
GET DIGIT
<
I
Y
= DELAY CHARACTER
'N
LOAD DIAL DIGIT
REGISTER WITH DIGIT
t
/
"
I
J
I
DIGIT
N
"
DDRE=1?
DELAY
I
LAST DIGIT?
IY
RESET CRa IN TX TO 0
WAIT 300uS
I
,
I
,
I
SET DATA TO 1
,
I MODEM SENDS. ANSWERTONE I
(
DATA MODE
Figure 7.
)
R1212 and R2424 Reverse Auto·Dial Routine
4·112
1
Application Note
R2424eR1212 Auto Dial and Tone Detection
Figure 8.
R1212 and R2424 Reverse Auto Answer
4-113
•
Application Note
'1'
8088 Microprocessor to R1212/R2424
Modem Interface
Rockwell
INTRODUCTION
The R1212/R2424 modem is mapped into the memory space
allocated for the prototype board in the IBM PC inpuVoutput map.
The chip select logic places the modem in the following address
space:
This application note details the connections and circuitry
needed to interface a Rockwell R1212 1200 BPS or R2424 2400
BPS Full-Duplex Modem to an 8088 microprocessor-based
system. Also included is an assembly language level computer
program that performs an auto dialer function.
I
Chip Select Line
Address Range
CSO
CSI
$30o-$30F
$310-$31F
I
8088 INTERFACE
The INS8250 UART provides the asynchronous communications
between the R1212/R2424 modem and the 8-bit microprocessor
data bus.
The basic interface signals between an R12121R2424 and an
8088-based system are summarized in Figure 1. A schematic
detailing the components and connections necessary to interface an R1212/R2424 modem to an expansion slot in an IBM
PC (or equivalent) personal computer is shown in Figure 2. This
particular circuit was used with a COMPAQ Personal Computer
but should be able to be used with an IBM PC or other compatible computer with little or no modification.
A
K:
DATA ....
DATA
BUS
BUFFERS
8
r
~
AUTO DIALER SOFTWARE
The 8088 assembly language instructions (and assembled
hmachine code that performs an auto dialer function is listed
starting on page 3.
A
~
.
IRQ
-"
DATA
8
~...
TRANSMIT DATA
& CONTROL
/2
/
8250
USART
RESET
8088
MICROPROCESSOR
SYSTEM
BUS
/5
f
RECEIVE DATA
& CONTROL
/5
/
.
/
ADDRESS
CONTROL
.A
K:
13
~
...
...)
ADDRESS
BUS
BUFFERS
/2
13/
/
I
Document No. 29220N72
READ, WRITE
CHIP
SELECT
DECODE
CS1,CS2
or
MODEM
I 2
I
I
/8,
Figure 1.
READI
WRITE
CONTROL
R1212
R2424
/4
REGISTER SELECT
&
)
r
J 2
I
IBM PC to R1212/R2424 Modem Interface
Application Note
4-114
Order No_ 672
January 1985
»
IRQ4
B24
A9
A8
DATAl
DATA2 A7
A6
2
3
4
5
6
7
DATAO
DATA3
DATA4 AS
CATAS
A4
."
74LS245
U1
8
9
OATA6 A3
,g'
e
Cil
DATA7 A2
-DBEN
D1
02
03
04
05
06
B2
"
0
13
15
17
!.....
01
7
5
3
~
Cl"
~
-'-'
:!1
~
~
ADS
22
DISTR
19
G
74LS244
U2
r*
13
~
35
AD
A1
A2
28
27
26
r-ff
~ f~ f-
....
B13
814
I\)
....
-lOW
-lOR
Tc
U4
~06
ADDRESS·
3F8-3FF
~07
21C ~
DTR 33
RClK
BAUD OUT
CSO
CS1
CS2
MR
AO
A1
A2
24C
SIN
__
ALSO
OSR
22C RXD
10
38
37
36
24A RLSO
20A - 25C OSR
c~ 39
·h~·
:n
6
5
U10
OISTR
4
3
U10
470
R3
rL f-
lOR
2
1
U10
I
470
R4
20,:.:F
-7A ASO
7C RS1
6A RS2
12C READ
Co
CD
n
::r
..g.
CD
3
+5V
+5V
AEN
lh
12
9
U3
7
5
j
3
4 7!!::.S3~
1 74LSOO
5USY2ua3
US
-
5
U5y-~
~~
U7
r-fi
9
74LS04
U5.U6.
U7.U8,U 01"F
C11-C16
r
U7
2K
+5V
'---
•
8
13
12
us
~sRdTE
GROUND
+5V
+ 12V
-12V
-
+~
33K
2ac
74LS30
c:
o
::n
.....
I\)
.....
I\)
--"
6
-DBEN
1
y
Lt> "'"
7
4
5
6
11
12
~~
U9,
GNO+5V+12V-12V-
1
2
U7
U10
TRANSMITTER
310-31f
"tI
'---
~ 4 AEN
+5V
TC3
GNO
GNO B01Te1
GNO ~.04~.04~ ~
GNO 810
+12V
+12V 89
-12V
-12V 87
c4[ cSf
A3
A4
AS
A6
A7
Aa
A9
,.
F
B03
isiil~ O,F:::!::047:::!: 047
18
16
74LS244
co
o
co
co
3:
ADDRESS
RECEIVER
300-30F
2 U9}!6C
2
4
6
8
11
13
15
17
I
I
0'
R2424
MODEM
C10
llA
A28
A27
A26
A25
A24
A23
A22
A11
R1212
o 74O.
XTAL116
0
3
ers
18A
!!:
III
~~~
SOUT 11
DOSTA
16
18
( I)
04
fA 05
~71O
4
2
o
~03
p~
lJ
I\)
Z
~D1
~D2
INS8250
1
~
::::I
,*DO
COSTA
1
2
3
4
5
6
7
8
T
RESET
A31
A30
A29
a0"
30 INTRPT
07
~ G
OIR
iii
C:;"
III
DO
18
17
16
15
14
13
12
11
!'>
!!:
"
"2-
I
CONPAQ EXPANSION
SLOT CONNECTOR
a
9C
11
1OC
::n
I\)
.j::o,
I\)
.j::o,
TLK/DATA
ORG/ANSW
3:
o
CS1
Co
(I)
CSO
I
3
-;.
::::I
( I)
n
(I)
8088 MPU to R1212/R2424 Modem Interface
Application Note
8088 AUTO DIALER ASSEMBLY LISTING
TITLE
8088 AUTO DIALER
WIALLASM)
COMMENT*
Rockwell Applu:atlcns Lab 5/15/84
Th15 1$ wrltten as an eKample of an auto-dlalltr in 80a6
Assembly Language.
I t was wrltten uSlng the Hlcoscft
Macro Assembler Whlc:h runs under the IBM Du;k Operatlng
System.
The hardware used places the interface memory Bank 0
and Bank 1 at locations 300-30F and 310-31F respectively_
ThlS 15 the space allocated for the Protot.ype Card 1n the
,
,
IBM 1/0 Address Map.
;Mac:ro pseudo-op for use
10
sett1ng req bits 1n the interface memory
;The address and blt to be set/reset 15 sent to the Macro.
; The Macro then gets the appropr1ate byte from the R1224.
; Th1 s byte 1 s ORed W1 th the b1 t to be set to change onl y that
;biL
The byte lS then sent back to the R1224.
~ET
MACRO
MOV
IN
OR
OUT
ENDM
ADDR,BIT
DX,ADDR
AL,DX
AL,BIT
DX,AL
;
STACK
0000
0000
0100 [
SEGMENT STACK
DB
256
DUP
0100
STACK
0000
DATA
BUF
SEGMENT
DB
20,21 DUP(O)
45 52
4E 45
42 45
MSG
DB
41 4C
24 20
(?)
ENDS
;
0000
14 15 [
; Set up a buffer for the phone number
00
0016
002<:
20
20
20
52
20
49
45
SO
4E
3A
20
4E
4E
48
55
24
44
47
54
4F
40
20
49
20
MES1
DB
0038
DATA
ENDS
0000
CODE
START
ENTER PHONE NUMBER:"
DIALING $
;
0000
SEGMENT
PROC
FAR
;
;Standard Program Prologue
0000
1E
0001
0004
88 0000
0005
oooa
SO
BB
---- R
BE DB
ooOA
E8 aoOE R
0000
CD
ooOE
ASSUME
PUSH
MOV
PUSH
MeV
MOV
CALL
CS= CODE,DS: DATA,SS: STACK
DS
AX,O
AX
BX,DATA JGet data segment base address
DS,BX
MAIN
RET
START
ENDP
4-116
Application Note
8088 MPU to R1212/R2424 Modem Interface
8088 AUTO DIALER ASSEMBLY LISTING (Continued)
;
,MAIN
OOOE
PROC NEAR
;Olal set-up
OOOE
0011
0012
0014
0015
0018
0019
0018
BA 031E
EC
OC 08
EE
OOIC
OOIF
0020
0022
SA 0'30D
EC
OC 80
EE
0023
0026
0027
0029
002A
oo2D
002E
SET
MOV
BA 0310
EC
OC 00
EE
+
+
0030
0031
0034
0035
0037
SA 030D
EC
OC 40
EE
oo::;e
BA 031D
0038
003C
003E
EC
OC 40
31DH,OOH
DX,31DH
AL,DX
OR
OUT
SET
MeV
31EH,08H
DX,31EH
IN
OR
OUT
BA 0310
EC
OC 80
EE
SA 0318
EC
OC 02
EE
IN
,
EE
AL,OOH
DX,AL
.Set NEWC
AL.,DX
AL,OBH
DX,AL
SET
MOV
30DH,80H
OX,30DH
IN
AL,DX
AL,BOH
OR
OUT
DX.,AL
SET
MOV
31DH,80H
DX,31DH
IN
AL,DK
OR
OUT
DXtAL
SET
MOIl
IN
+
+
;Assure that DTR 15 a a
;Set thli!' BUS bit, receiver-
;6et the BUS bit, transmi tt.er
AL,80H
31BH,02H
DX,31BH
;Set DTMF for tone dlahng
AL,DX
AL,02H
OR
OUT
DX,AL
SET
MOV
30DH,40H
DX,30DH
IN
AL,DX
OR
OUT
DX,AL
BET
MeV
31DH,40H
DX,31DH
IN
AL,DX
OR
OUT
DX,AL
,Set eRG bl t., rec:el ver
AL,40H
;Set CRO bit, transml tter
AL,40H
;Walt .at least 50 msec: betNeen reset and !Set of DTR
003F
0041
0043
0046
83
FE
80
75
0048
004B
OO4C
004E
BA 031D
EC
OC OB
EE
004F
00!52
EC
00S3
00155
EE
•
FF
CB
FB 00
F9
TIME1:
MOV
DEC
CMf'
JNZ
SET
I10V
IN
OR
OUT
SET
MOIl
IN
OR
OUT
BA 030E
OC OS
OOSlo
BA 031E
00S9
OOSA
EC
OC OS
~
EE
OOSD
+
+
BA 0318
0060
EC
0061
0063
006S
24 SO
3C SO
75 Flo
SET
+
+
•
MOIl
IN
OR
CUT
BL,OFFH
BL
BL,OOH
Tlt1El
31DH,.OSH
DX,31DH
AL.,.DX
,Set DTR
AL,OBH
DX,AL
3OEH,.08H
DX,3OEH
;Set NEWe, ReC&1v.,..
AL,DX
AL,OBH
DX,AL
31EH,oat
DI,31EH
,Set. NEWC blt, Tran5llit.t.r
AL,nX
AL,OBH
DX,AL
,Check t.h.t. . . .r . cff-hoak .,.d r ••dy t.o di.l
I
WAIT.
MQV
DX,318H
IN
AL,DX
AL,So..
AND
ICheck t.o _
i f DLD i . sat.
ClIP
AL,BOH
JNZ
WAIT
I l f no1:, IM1t. far it.
4·117
•
Application Note
8088 MPU to R1212/R2424 Modem Interface
8088 AUTO DIALER ASSEMBLY LISTING (Continued)
;Wa1t for dlal-tone on the I1na
MOV
IN
AND
DX,30BH
AL,DX
AL,BOH
CMP
AL,BOH
JNZ
WAIT
0067
006A
0068
0060
006F
SA 0308
EC
2480
3C 80
75 EC
0071
0073
0076
8409
SA 0016 R
CD 21
0078
007A
007D
84 OA
SA 0000 R
CD 21
MOV
MOV
OX ,OFFSET aUF
INT
21H
007F
820A
8402
CD 21
MOV
MOV
MOV
AH,9
MOV
INT
DX ,OFFSET MSG
21H
; Print prompt for phone. input
Rli!ad the number and dl spl ay it.
OOBl
0083
00B5
0087
008A
INT
8409
SA 002e R
CD 21
AH,OAH
;Buffered Keyboard Input
DL,OAH
;Llne feed
AH,02
21H
;Display function
;DOS call
MOV
AH,9
MOV
OX ,OFFSET MESl
INT
21H
;Prlnt DIALING message
Loop and redl spl ay tel sphene number as I t is dialed
0092
0096
BE
89
8A
SA
009A
52
aOBe
OOBF
0000
0000
OE 0001 R
94 0002 R
MDV
MOV
MQV
81,0
CX,O
CL,BUF+l
;Get number of digits read
PAD:
MOV
DL,BUFCSI+2J
;DL now contains thet d1al digit
PUSH
OX
;Preserve t.he dial digit on the stack
;
;Check to see that the dial digit reglloter is empty
0098
009E
SA 031E
EC
009F
24 01
3C 01
75 Fb
aOAl
OOA3
FULL1:
MOV
DX,31EH
IN
AL,DX
AND
CMP
AL,OlH
JNZ
FULL1
AL,OlH
;
;6st the dial d1glt off the stack
OOA5
5A
POP
OX
;
;Chec:k to see If It·S a carriage return
OOAb
aOA9
80 FA 00
74 10
CMP
DL,ODH
JZ
DONE
; If
It
IS,
end the dialing sequence
;
;Feedback for dlallng
eOAB
OOAD
B402
CD 21
MOV
INT
AH,2
21H
; Prl nt the di gi ts as they are di.1 ad
;Sand the dial digit tl;) the R1224
OOAF
OOB2
0094
OOB7
00B8
00B9
DL,OFH
AL,DL
80 E2 OF
SA C2
SA 0310
MOV
MOV
EE
46
OUT
INC
OX,310H
DX,AL
51
LOOP
PAD
AND
E2 DB
;Dlal Digit must be in AL to be sent
;tc the 1/0 port
;Send 1t
;Polnt to the next digit
;60 here to end the dlal sequence by putting FF
oose
COBE
DOBF
OOCl
OOC3
SA 031E
EC
24 01
SA 0310
90 FF
OOCA
EE
aocs
C3
aoce
coce
JNZ
AL,01H
AL,OlH
DONE
MOV
MOV
OUT
DX,310H
AL,OFFH
DX,AL
AND
CMP
3C 01
75 F6
ooca
OOCS
;lntc the dlal dlglt reglster
;
; Assure DDRE empty agal n
;
DONE:
MOV
DX,3IEH
IN
AL,DX
RET
MAIN
CODE
END
ENDP
ENDS
START
4-118
Application Note
'1'
Rockwell
RC2424DP/DS
Diagnostic Data Scaling
INTRODUCTION
DSP RAM ACCESS
This application note is a supplement to the
RC24240P/OS data sheet. It provides information on
parameters accessible in OSP RAM shown in Table 1, and
on Checksum verfication available after Power-on or
Reset.
DSP RAM ORGANIZATION
The OSP contains four sections of 16-bit wide random access memory (RAM). Because the OSP is optimized for
performing complex arithmetic, the RAM is organized into
real (X RAM) and imaginary (Y RAM) sections, as well as
data and coefficient sections. The host processor can access (read or write) the X RAM only, the Y RAM only, or
both the X RAM and the Y RAM simultaneously in either
the data or coefficient section.
POWER.ON/RESET DSP TEST MODE
After Power-on or Reset, the RC24240PIDS OSP enters
into a test mode and calculates Checksum on ROM. The
result of the Checksum V$rification is written into Host Interface memory bytes 15 and 14. The valid checksum is a
constant $412B. At the same time, ASCII values for the
"part number" are written into Host Interface memory bytes
13 and 12, and ASCII values for the "code revision lettter"
are written into Host Interface memory bytes 11 and 1O.
INTERFACE MEMORY ACCESS TO DSP RAM
The OSP interface memory acts as an intermediary during
host to OSP RAM or OSP RAM to host data exchanges.
The addresses stored in OSP interface memory RAM Address registers (i.e., XAOO and YAOO) by the host, in conjunction with the data or coefficient RAM bits (Le., XCR
and VCR) determine the OSP RAM addresses for data access.
For example, on the C5308-15 "0" code, the number "08"
is the part number and "0" is the code revision letter. The
values written into Host Interface memory would be as follows:
Register Value
$41
15
14
$2B
13
$30
12
$38
11
$20
$44
10
One or two 16-bit words are transferred between OSP
RAM and OSP interface memory once each internal OSP
cycle. The transmitter and the receiver sample rate functions operate at the 7200 Hz sample rate. The receiver
baud rate functions operate at 600 Hz.
Contents
Checksum Upper word
Checksum Lower word
ASCII value of '0"
ASCII value of "8 •
ASCII value of ••
ASCII value of "0"
Two RAM access bits (XACC and YACC) in the OSP interface memory tell the OSP to access the X RAM and/or Y
RAM. The RAM tests these bits each sample period (139
microseconds).
After the OSP writes to byte 10, the TOBE bit will be set.
This indicates to the host that the self-test information can
be read. The OSP will wait 20 ms or until the host reads or
writes Host Interface Memory byte 10. After this, the OSP
will execute the Initialization sequence.
Document No. 29200N835
READING AND WRITING THE OSP RAM
The procedure for reading and writing the OSP RAM is
described in the RC24240PIDS data sheet (Order No.
M053). The parameters shown in Table 1 are described
on the following pages. The format for all parameters is 16
bits, twos complement.
Application Note
4-119
Order No. 835
January 1988
•
RC2424DP/DS Diagnostic Data Scaling
Application Note
Table 1. DSP RAM Parameter. (Cont'd)
Table1. DSP RAM Parameter.
XCR/ XRAM YRAM
Addr Addr
No. VCR"
0
C
1
2
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
16
0
17
18
19
20
21
22
23
24
25
26
27
0
C
12
12
14
6C
60
60
60
6E
6F
6F
71
71
74
74
OE
OE
10
11
11
12
12
14
14
10
2A
XCR/ XRAM YRAM
Addr Addr
No. YCR"
28
1
PIIrameter
1111 equalizer Tap, Real
lalli Equalizer Tap, Real
1111 equalizer Tap, Imaginary
lalli Equalizer Tap, Imaginary
Rolated Error, Real
Ro1ated Error, Imaginary
Max AGO GaIn Word
Pulse Dlallntardiglt Time
Tone Dlallntardigit Time
' Pulse Dial Relay Make Time
Pulse Dial Relay Break Time
OTMF Duration
Tone 1 Angle Increment Per Sample
Tone 2 Angle Increment Per Sample
Tone 1 Amplitude
Tone 2 Amplitude
Max Samplee Per Ring Frequency
Period
Min Samples Per Ring Frequency
Period
Real Part of Error
Imaginary Part of Error
Rolation Angle for Carrier Recovery
Ro1ated Equalizer OuIput Real
RoIated Equalizer Output Imaginary
lower Pert of Phase Error
Upper Part of Phase Error
Upper Part of AGO GaIn Word
Lower Part of AGO Gain Word
Average Power
Phase Error
20
-
29
1
-
20
30
1
1
1
20
2E
33
-
31
32
33
1
34
34
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
35
36
52
-
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
66
-
--
-
-
-
-
2E
2F
30
31
32
34
35
36
37
36
3A
3B
3C
3D
3E
45
46
47
46
49
Parameter
Tone " - (ATBELL, BEL1030r
TONEA)
Tone Detect Threshold (Call Progress
Energy)
Tone Power (ATV25 or TONEB)
Tone Power (TONEC)
Tone Detect Threshold (ATBELL,
BEL103, or TONEA)
Tone Detect Threshold (AlV25 or
TONEB)
Tone Detect Threshold (TONEC)
Zero Crossing Counter
Eye Quality Monitor (EQM)
Filter 1 Coefficient aD
Filter 1 Coefftcient al
Filter 1 Coefficient a2
Filter 1 Coefficient III
Filter 1 Coefficient jl2
Filter 2 CoeffIcient aD
Filter 2 Coefficient al
Filler 2 Coefficient a2
Filter 2 Coefficient III
Filter 2 Coefficient 112
Filter 3 Coefficient aD
Filter 3 Coefficient a 1
Filter 3 Coefficient a2
Filter 3 Coefficient 111
Filter 3 Coefficient 112
Filter 4 Coefficient aD
Filter 4 Coefficient a 1
Filter 4 Coefficient a2
Filter 4 Coefficient 111
Filter 4 CoeffIcient 112
"XOR if an XRAM address Is listed; VOR if a YRAM
address is listed.
4-120
RC2424DP/DS Diagnostic Data Scaling
Application Note
XCR:
No. 1 • Equalizer Tap Coefficients, Real
1
)(RAM
Addr:
o·c
The adaptive equalizer is a transversal filter (Figure 1). The filter is tuned by varying the weighting coefficients, Co through
CN. The RC2424DPJDS has 13 taps. Since the baseband signal is complex it requires bOth X and Y coefficients for each tap.
The delay between taps is 1/2 baud time. The adaptive process attempts to adjust all coefficients to minimize the mean
squared error.
INPUT
Co
Figure 1. Equalizer Structure
No. 2 • Equalizer Tap CoeffiCients, Imaginary
VCR:
1
YRAM Addr:
o·C
These values represent the imaginary component of the equalizer tap coefficients. (See above.)
No.3· Rotated Error, Real
XCR:
0
XRAM Addr:
12
The Rotated Error vector is the angle and magnitude difference between an actual received signal point (P2) and the nearest
ideal point (P1) in the baseband signal plane (Figure 2). The real and imaginary components are calculated once per baud
time. See Real Part of Error (No. 17) and Imaginary Part of Error (No. 19).
/
,."
I
BOUNDARY
P,
I
"
I
I
P, =
Xl
P2 -
X2
P2
-
+
+
Iy,
iY2
(x2- X,) + i(Y2 - y,)
- REAL ERROR + IMAGINARY ERROR
P, =
01234517"1011
Figure 2. Rotated Error
4-121
•
Application Note
RC2424DP/DS Diagnostic Data Scaling
VCR:
No.4· Rotated ,Error, Imaginary
0
YRAM Addr: •
12
These values represent the imaginary component of the Rotated Error vector. (See No.3.)
No.5· Max AGC Gain Word'
Default: $2500 (31.95 dB)
VCR:
0
YRAM Addr:
14
XCR:
0
XRAM Addr:
6C
This value represents the maximum AGC gain, and can be varied by the host.
Formula:
Max AGC Gain Word = (46.4 - Max AGC Gain (dB» x 32768/50
Convert value to hex to store in RAM.
No.6· Pulse Dial Interdlglt Time
Default: $1518 (750 ms)
This value represents the amount of delay in samples between digits dialed when in pulse dial mode (DTMF
=0).
Formula:
Interdigit time (samples) = Interdigit time (sec) x 7200 (samples/sec)
Convert sample value to hex to store in RAM.
No.7· Tone Olallnterdlglt Time
Default: $01 F8 (70 ms)
VCR:
0
YRAM Addr:
This value represents the amount of delay in samples between digits dialed when in tone dial mode (DTMF
6C
=1).
Formula:
Interdigit Time (samples)
=Interdigit Time (sec) x 7200 (samples/sec)
Convert sample value to hex to store in RAM.
No.8· Pulse Dial Relay Make Time
Default: $0120 (40 ms)
XCR:
0
XRAM Addr:
60
This value represents the time (in number of samples) that the OHRELAY will close for each digit dialed.
Formula:
Pulse Make Time (samples) = Pulse Make Time (sec) x 7200 (samples/sec)
Convert sample value to hex to store in RAM.
No.9· Pulse Dial Relay Break Time
Default: $01 BO (60 ms)
VCR:
0
YRAM Addr:
This value represents the time (in number of samples) that the OHRELAY will open for each digit dialed.
Formula:
Pulse Break Time (samples)
=Pulse Break Time (sec) x 7200 (samples/sec)
Convert sample value to hex to store in RAM.
4-122
60
Application Note
RC2424DP/DS Diagnostic Data Scaling
No. 10· DTMF Duration
Default: $01 F8 (70 ms)
VCR:
0
VRAM Addr:
SE
XCR:
VCR:
0
0
XRAM Addr:
YRAM Addr:
SF
SF
This value represents the time duration of each DTMF digit dialed.
Formula:
DTMF duration (samples) = DTMF duration (sec) x 7200 (samples/sec)
Convert value to hex to store In RAM.
No. 11· Tone 1 Angle Increment per Sample
No. 12 • Tone 2 Angle Increment per Sample
Default: $00
When the host enters Tone Generatioll/Detection mode (CONF = 80), the transmitter immediately begins sending the dual
tone frequencies specified by addresses XRAM 6F and VRAM 6F, with amplitudes specified by >-_..-.:2::;:08:.(J2_52 RXA
R2
15A 20K 1% 20K 1%
1S.4K 1%
+12V J 2 - 1 5 ) - - - - - - - - -_ _ _ _ _ _ _......J
C2
.1
+_-..J
-12V J2_12r12~A_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
GND
150V
R4
J2-96~
20K 1%
II
NOTE- UNLESS OTHERWISE SPECIFIED
1. RESISTOR VAWES ARE IN OHMS, 1/4W
2. CAPACITOR VAWES ARE IN MICROFARADS. ± 20%
Figure 10. Hybrid Schematic
Table 9. Hybrid Parts List
Designation
C1,C2
CR1,CR2
J1
J2
R1
R2
R3
R4,R5,R6
T1
U1
Quantity
2
2
1
1
1
1
1
3
1
1
Type
Capacitor
Zener diode
Telephone jack
Connector
Resistor
Resistor
Resistor
Resistor
Transformer
IC
4-145
Description
0.1 I'F ",20% 50V, Z5U Ceramic
1N753A
RJ11 C, 6-position, R/A
DIN, 96-pin, plug
536Q",1% 1/4W
15.4KQ",1% 1/4W
8.66KQ ",1% 1/4W
20.0KQ ",1% 1/4W
Midcom #671-1538
LM1458,Dual operational amplifier
Application Note
DAA Design for R1496MM,
R9696DP~
•
•
[(1
II
II
II
II
II
II
II
II
II
II
II
II
II
II
T1
CR2
D
Cl
c:::::J
R5
lIu1
~
II
R4
II
II
C2
R2
[=:1
[=:1
c:::::J
c:::::J
D
c:::::J
CRl
]
c:::::J
~un
R3
J1
C
c:::::J
Rl
II
II
II
II
II
J2
~::dJ
•
•
SERIRL NO 0LI_ _ _- '
RSSY NO
°
TT04-D630-
•
•
L I_ _ _- '
Figure 11. Hybrid Module Silkscreen
•
•
•
::
••
•
•
•••
•••
•••
•••
•••
•••
•••
•••
•••
•••
•••
•••
•
•
Figure 12. Hybrid Module Component Side Layout
4-146
and R144DP
Application Note
DAA Design for R1496MM, R9696DP, and R144DP
•
•••
•••
•••
•••
•••
•••
•••
•••
•••
•••
•••
•••
•••
•••
•••
•••
•••
•••
•••
•••
•••
•••
•••
•••
•••
•••
•••
•••
•••
•••
•••
•••
•
••
•
•
• •••
••• •••
•
•
••
•
••
••
•
•
•
•
•
•
••
•
••••
••
•
•
•
•
•
Figure 13. Hybrid Module Padmaster Layout
•
•
•
•
TT04-D635-003
SOLDER SIDE
•
•
Figure 14. Hybrid Module Solder Side Layout
4-147
•
Application Note
'1'
R1496DP, R9696DP, and R144DP
Programmer's Guide
Rockwell
INTRODUCTION
DSP RAM ADDRESS INFORMATION
This programmer's guide is a supplement to the R144DP,
R9696DP, and R1496DP data sheets. The information
provided in this guide will aid the programmer in the design
of an end product using the Rockwell ultra high speed
modem products.
The DSP RAM addresses are listed in Table 1.
Table 1 a superset of the RAM information within the three
ultra high speed modems. Consult the appropriate data
sheet for the addresses which apply to the modem being
used.
The following information is provided:
DSP RAM Address Information
Handshake Timeout Timers
V.22bisN.32Interworking
Retrain and Automatic Rate Change Procedures
Reading Device Revision Information
READING AND WRITING THE DSP RAM
The procedure for reading and writing the DSP RAM is
described in the R1496DP, R9696DP, and R144DP data
sheets.
Table 1. DSP RAM Addresses
Address
Code
I
No.
Function
1 Transmitter Compromise Equalizer
Coefficients
First Tap
Last Tap
2 V 33/V 32 Rate Sequence
3 DTMF Tone Duration
4 DTMF Interdlglt Delay
5 DTMF Low Band Power Level
6 DTMF High Band Power Level
7 Pulse Relay Make Time
8 Pulse Relay Break Time
9 Pulse Interdlglt Delay
10 Transmitter Output Level Gain Constant
11 Tone Transmit Frequency
12 Transmitter New Status Bit (NEWSO)
Masking Register for 0 E and 0 F
13 Total Span of Echo Canceller
14 Echo Canceller DIviding POint
15 Far End Echo Canceller Center
Tap Position
16 Echo Canceller Update Coefficient
(Training Mode)
17 Echo Canceller Update Coefficient
(Data Mode)
18 CTS OFF-to-ON Response Time
(RTS-CTS Delay)
19 Round Tnp Far Echo Delay
20 Echo Canceller Error
21 Far End Echo Frequency Offset
22 Far End Echo Level
23 Tone Detector A Bandpass
Filter Coefficients
Note:
Address
Code
Real Imaginary
Part
CR
!ChiP Part
No. (X)
(V)
Bit' No.
0
0
0
0
0
0
0
0
0
0
0
0
0
5B
34
93
9A
lA
19
99
9C
lC
18
99
87
11
-
1
1
1
1
1
1
1
1
1
1
0
0
1
0
0
0
90
AO
24
-
0
0
0
0
24
-
1
0
A4
-
1
0
10
-
1
0
0
0
0
1
9E
20
20
25
26
-
0
0
1
0
1
-
Function
24 Tone Detector B Bandpass
Filter Coefficients
25 Tone Detector C Bandpass
Filter Coefficients
26 RLSD On-to-Off Threshold
27 RLDS Off-to-On Threshold
28 Receiver Chip 1 New Status Bit (NEWS1)
Masking Register for 1 A and 1 B
Masking Register for 1 C and 1 0
Masking Register for 1 E and 1 F
29 Received Signal Samples
30 Demodulator Output
31 Low Pass Filter Output
32 Average Energy
33 AGC Gain Word
34 Timing Recovery Update
35 Equalizer Input
Equalizer Tap Coefficients
36
First Tap
1
Last Tap
37 Unrotated Equalizer Output
38 Rotated Equalizer Output
(Received POints)
39 DecIsion POints (Ideal POints)
40 Equalizer Error
41 Equalizer Rotation Angle
42 Equalizer Frequency Correction
43 Eye Quality MOnitor (EQM)
44 Maximum Penod of Valid Ring Signal
45 Minimum Penod of Valid Ring Signal
46 Receiver Chip 2 New Status Bit (NEWS2)
Masking Register for 0 E and 0 F
Real Imaginary
Chip Part
Part
CR
No. (X)
(V)
Bit'
1
2C
-
1
1
32
-
1
1
1
07
01
-
1
0
1
1
1
1
1
1
1
1
1
2
9B
9C
90
03
04
00
02
01
25
18
84
80
98
1
1
1
0
0
0
0
1
0
0
2
2
2
2
18
47
01
02
98
C7
81
82
1
1
0
1
2
2
2
2
2
2
2
2
02
03
87
OA
07
17
97
7E
82
83
0
0
1
1
1
0
0
0
-
-~
-
1 CR corresponds to XCRO. YCRO. XCRI. VCRI. XCR2. or YCR2 depending on the chip number and address code
Document No. 29800N831
Application Note
4-148
Order No. 831
August 1988
Application Note
R1496DP, R9696DP, R144DP Programmer's Guide
CCITT defines the V.33 rate sequence bits as follows:
RAM addresses which are specified as having a real (or X)
part only, can be loaded in the YRAM Address register as
well. The RAM address specifies whether or not the OSP
should do an X access or a Y access, not the register in
which the address is stored. This allows two different RAM
accesses to occur when the result is not a complex number.
B~
BIT
DATA
BIT
DATA
2
3
4
5
6
1
8
B9-B14
6
7
8
9 10 11 12 13 14 15
0111
for synchronizing on the rate sequence
not defined
not defined
not defined
a 1 denotes the ability to receive at 12000 bps
a 1 denotes the ability to receive at 14400 bps
0
1
2
3
4
5
6
I 0 I 0 I 0 I 0 I x I xI x I
7
8
11
xI xI xI
9 10 11 12 13 14 15
11
xI xI
11 11
The 16-bit rate sequence word in the modem's RAM corresponds exactly to the 16-bit rate sequences defined in
V.32 and V.33. The MSB of the word in RAM is BO of the
rate sequence and the LSB is B15 of the rate sequence.
9 10 11 12 13 14 15
xl xl xiii xl xl xl 1/ xl xl xiii
Modem
Configuration
V.32T/9600
V.32/9600
V.32/7200
V.32/4BOO
BO= MSB; B15 = LSB
BO-B3,
B7, Bll, B15
B4
B5
B6
B4-B6
B8
5
xl xl xiii xl xl xiii xl xl
The V.32 and V.33 rate sequences contain undefined
codes and/or bits. The user can use these bits to convey
information to the remote modem during training (e.g.,
remote configuration, multiplexer configuration, test mode
configuration, etc). This section discusses how to use
these bits.
CCITT defines the V.32 rate sequence bits as follows:
1
4
BO-B3,
B7, Bl1, B15 for synchronizing on the rate sequence
a 00 denotes that 86, Bl0, 812, and 813 define
B4,B5
multiplexer configuration selection
a 1 denotes the ability to transmit and receive
B8
at 12000 bps
a 1 denotes the ability to transmit and receive
B9
at 14400 bps
•
B6, Bl0,
B12,813
multiplexer configuration selection (see the V.33
specification for multiplexer configurations)
Function 2: Rate Sequence
01 01 01 01
3
BO= MSB; B15 = LSB
The transmitter compromise equalizer can be
programmed by the user. The equalizer is a 40-tap finite
impulse response (FIR) digital filter. The first tap is at address $5B ($ denotes a hexadecimal number) and the last
tap is at $34. The sampling rate for the filter is 9600 Hz (except V.21 which has a 7680 Hz sampling rate). New coefficients should be loaded while the modem is in idle mode
before turning on OTR (2-wire full duplex modes) or RTS
(4-wire full duplex modes). The coefficients have to be
loaded only once. They are re-initialized only if a POR occurs. The user should ensure that the overall gain of any
filter designed is 1. The coefficients are 16-bit 2s complement numbers.
0
2
Bit 14= 1:
Function 1: Transmitter Compromise Equalizer
Coefficients
I
1
01 01 01 01
BO-B3,
B7,Bl1,B15
B4-B6
Bl0, 612
B13
B8
B9
If the user wants to read the pulse relay make and break
times simultaneously, the RAM address for the make time
can be stored in the XRAMO Address register and the RAM
address for the break time can be stored in the YRAMO Address register. Both the XCRO and YCRO bits should be
set to a 1. The XWTO and the YWTO bits should be reset
to a O. The XACCO and YACCO bits should then be set to
a 1. When they are reset to a 0 by the OSP, the pulse make
time data will be in the XOAMO and XOALO registers and
the pulse break time data will be in the YDAMO and YOALO
registers.
DATA
0
I
BO = MSB; B15 = LSB
Example:
BIT
14 =0:
for synchronizing on the rate sequence
a 1 denotes the ability to receive at 2400 bps
a 1 denotes the ability to receive at 4800 bps
a 1 denotes the ability to receive at 9600 bps
o 0 0 calls for a GSTN cleardown
a 1 denotes the ability of trellis encoding and
decoding at the highest data rate indicated in
B3-B6.
o 0 1 0 0 0 denotes absence of special
operational modes.
V.33/14400
V.33/12000
V.33/9600
V.33/7200
4-149
Rate
Sequence (Hex)
0791
0711
0711
0591
0101
0191
0111
0111
Application Note
R1496DP, R9696DP, R144DP Programmer's Guide
V.32 Rate Sequence
Function 3·9: Dialing Parameters
In the V.32 rate sequence, bits 89,810,812,813 and 814
are not used by the Rockwell modems. (Note thatthe V.32
specification says that if 89-B14 = 001000, then this
"denotes absence of special operational modes".) These
bits are initialized to 0 by the modem. To use these bits, a
read-modify-write ofthe rate sequence RAM location must
be performed while the modem is in idle mode (OTR inactive). Do not alter any of the defined bits in the rate sequence (80-88, 811, or 815). The bits can be read out of
the interface memory at the receiving modem. The rate sequence is available in RSEQM (1:1 :0-7) and RSEQL
(1 :0:0-7) during the handshake when status bit RSEQ
(1 :C:O) is a 1. RSEQM contains 80-87 (1: 1:7 = 80) and
RSEQL contains 88-815 (1 :0:0 = 815).
The dialing parameters are listed in Table 2.
. Table 2•. Function 3 - 9 Dialing Parameters
Function
Parameter
DTMF Tone Duration
3
DTMF Interdigit Delay
4
DTMF Low Band Power
5
Level
6
DTMF High Band Power
Level
Pulse Relay Make Time
7
Pulse Relay Break Time
8
Pulse Interdigit Delay
9
To use bits 89, 810, 812, 813 and 814 during a retrain,
the rate sequence must be modified after initiating a retrain
(with the RTRN bit), since the rate sequence is initialized
at the start of a retrain. The rate sequence can be modified
any time after detecting the first part of the retrain handshake (ACDET in originate mode, AAOET in answer
mode) and before sending the rate sequence (R2 in
originate mode, R1 in answer mode).
Default Value
(Hex) (Dec) Units
$0390
95
ms
$02A9 71
ms
$1F70
-4
dBm
$2650
$0159
$0266
$1C20
-2
36
64
750
dBm
ms
ms
ms
For Functions 3, 4, 7, 8, and 9, the time T ~n seconds) is
calculated as follows:
N =Tx9600
where:
N is the decimal equivalent of the hex number
that should be written into RAM.
For Function 5, the OTMF low band power level (L) in dBm
is calculated as follows:
V.33 Rate Sequence
N = log-1[(L + 4)/20] x 8048
In the V.33 rate sequence, bits 84, B5, 86, 810, 812, 813
and 814 are not used by the Rockwell modems. These bits
are initialized to 0 by the modem. Note that the modem
does not support the multiplexer configuration codes
defined in Table 48 of the V.33 specification (when
B14= 1). It is left for the user to implement this feature. To
use bits 89, B1 0,812,813, or B14, a read-modify-write of
the rate sequence RAM location must be performed while
the modem is in idle mode (RTS inactive). Do not alter any
of the defined bits in the rate sequence (BO-B3, B7 -139,
B11, and B15). The bits can be read out of the interface
memory at the receiving modem. The rate sequence is
available in RSEQM (1:1 :0-7) and RSEQL (1 :0:0-7) during
the training sequence when status bit RSEQ (1 :C:O) is a 1.
RSEQM contains BO-B7 (1:1:7 = BO) and RSEQL contains
B8-B15 (1 :0:0 = 815 ).
where:
L (dBm)
+6
+5
+4
+3
+2
+1
0
-1
-2
-3
-4
-5
-6
To use bits 89, B10, B12, B13, and 814 during a retrain,
the rate sequence must be modified after initiating a retrain
(with the RTRN bit), since the rate sequence is initialized
at the start of a retrain. The rate sequence can be modified
any time after detecting the first part of the retrain sequence (P2DET) and before sending the rate sequence.
N is the decimal equivalent of the hex number
that should be written in RAM.
N (decimal)
25450
22682
20216
18017
16058
14312
12755
11368
10132
9030
8048
7173
6393
N (hex)
636A
589A
4EF8
4661
3EBA
37E8
3103
2C68
2794
2346
1F70
1C05
18F9
For Function 6, the OTMF high band power level (H) in
dBm is calculated as follows:
N = log-1[(H + 2)/20] x 9808
where:
4-150
N is the decimal equivalent of the hex number
that should be written in RAM.
R1496DP, R9696DP, R144DP Programmer's Guide
Application Note
H (dBm)
+6
+5
+4
+3
+2
+1
o
-1
-2
-3
-4
-5
-6
N (decimal)
24637
21957
19570
17441
15545
13854
12348
11005
9808
8741
7791
6944
6188
Function 11: Tone Transmit Frequency
N (hex)
6030
55C5
4C72
4421
3CB9
361E
303C
2A50
2650
2225
1E6F
1B2O
182C
Frequency F (in Hz) is calculated as follows:
N =F / 0.146486
where:
N is the decimal equivalent ofthe hex number
which should be written into RAM.
N (decimal)
2048
2731
3038
4096
8192
12288
14336
15360
16384
20480
24576
27306
F (Hz)
300
400
445
600
1200
1800
2100
2250
2400
3000
3600
4000
NOTE:
The compromise equalizer should be off (CEQ = 0) to output the correct OTMF levels. The transmit level bits [ILVL)
also affect the OTMF levels. The transmit level bit attenuate the OTMF tones an additional amount to that
specified by Functions 5 and 6.
N (hex)
800
AAB
BOE
1000
2000
3000
3800
3COO
4000
5000
6000
6AAA
Transmission of a single tone is accomplished by writing
an $80 into the TCONF register. programming the tone
transmit location in RAM. and then activating RTS. The
tone will be transmitted as long as RTS is active.
Function 10: Transmitter Output Level Gain Constant
The transmitter output level gain constant (G) in dBm is
calculated as follows:
N = 10g-1 [G /20] x 32767 (G " 0)
Function 12: Transmitter NEWSO Masking Register
where:
Writing a 1 in the bit location corresponding to the desired
bit will cause NEWSO to go active when a status change
occurs for the selected bit. All bits default to 0 at power-onreset. Figure 1 shows the applicable masking register bits.
status bits.
G (dBm)
o
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
N is the decimal equivalent of the hex number
that should be written in RAM.
N (decimal)
32767
32392
32021
31655
31292
30934
30580
30230
29884
29542
The default gain is 0 (N
N (hex)
7FFF
7E88
7015
7BA7
7A3C
7806
7774
7616
74BC
7366
Functions 13 ·17 and 19 ·22: Echo Canceliatlon
The echo canceller has a total span of 53.3 ms (128
bauds). This is divided between near-end and far-end cancellers. The default value for the dividing point is 56 bauds
(Function 14 ). giving a near-end canceller of 23.3 ms and
a far-end canceller of 30 ms.
The transmitter output level gain constant directly controls
the output level of all configurations. It is used for fine
tuning the output level which is controlled by the lLVL bits.
Therefore.
Output Level = lLVL Setting + Transmitter Output
Gain in dBm
Modem
Register
O:OF
O:OE
NT =
NN + NF = Total span of echo canceller in
number of bauds (Function 13)
NN
=
Echo canceller dividing point in number of
bauds (Function 14). NN is also the span of
the near-end canceller in number of bauds.
NF
=
NT - NN =Span of far-end canceller in numberof bauds
NC
=
Far end echo canceller center tap position in
number of bauds (Function 15)
=$7FFF).
7
6
-
-
5
CTS
-
Bit
4
DSR
-
3
-
2
TM
-
Figure 1. NEWSO Masking Register
4-151
1
-
0
-
RAM
Register
DAMO
DALO
•
ApplicatlonN,ote
R1496DP, R9696DP, R144DP Programmer's Guide
Ifthe total span is reduced by a significant amountfrom the
default value. it may be necessary to change the Echo
Canceller Update Coefficients. Functions 15 and 16.
However. unless the total span is reduced to 30 ms or less.
this should not be ~ecessary.
The Echo Canceller Dividing Point
A common requirement is,to shorten the span of the nearend canceller (NN). The default span is quite large. This
was mainly chosen to help deal with the effects of intermediate echo in the United States. However, if during the
V.32 handshake the round-trip delay is found to be less
than the span of the near-end canceller, the far-end canceller simply concatenates with the near-end canceller. In
other words, part, or all, of the impulse response ofthefarend echo falls within the span of the near-end canceller.
Table 3 lists the echo canceller parameters.
Table 3. Function 13·17 Parameters
Default Value
Function
This could be a problem in Europe. The near-end canceller
is unable to deal with frequency offset (phase roll) on the
echo. However, this type of impairment is common in
European networks. Round-trip delays' will also be fairly
short. Hence if a significant far-end echo is present which
is impaired by frequency offset and'the round-trip delay is
less than the span of the near-end canceller, there will be
a performance degradation. Note that if there is no frequency offset then there is no problem with the near-end
canceller, cancelling far-end echos.
13
14
15
16 '
17
The span of the near-end canceller is changed by
prograinm ing Function 14, the E9hO Canceller Dividing
Point. A more useful span for Europe may be in the range
10 ms - 15ms. For example, if a 12.5 ms near-end canceller is required, then the Echo Canceller Dividing Point
should be set to $001 E.
Parameter
Total Span oftha Echo
Canceller
Echo Canceller Dividing
Point
Far End Echo Canceller
Center Tap Position
Echo Canceller Update
Coefficient (Training)
Echo Canceller Update
Coefficient (Data)
Hex
Dec.
Units
$0080
53.3
ms
$0038
23.3
ms
$0024
$0004
$0000
When to change echo canceller 'functlons:
Functions 13.14. and 15 should only be changed when the
modem is in idle mode before turning on DTR. The
parameters have to be written into RAM only once. They
will be altered only if a power-on-reset to the modem occurs.
Far End Canceller Center Tap Position
Changing the Echo Canceller Dividing Point also affects
the span of the far-end canceller. For example, ifthe dividing point is changed to $001 E, then the span of the nearend canceller is 12.5 ms and the span of the far-end
canceller is 40.8 ms (assuming the default total span of
53.3 ms). It is recommended that if the dividing point is
changed, then Function 15, the Far End Canceller Center
Tap Position, should also be changed.
Restrictions on echo canceller parameters:
There are some restrictions on the values of Functions 13
and 14 (NT and NN).
NT value restrictions:
value must be even
minimum value = (NN + 6) if there is a far-end
canceller
minimum value = NN if no far-end canceller is
required
maximum value = 128 ($0080)
The Center T6ap, NC, should be set as follows:
NC = ( NT - NN ) /2
Total Span of Echo Canceller
NN value restrictions:
Even more flexibility is available by allowing the user to
reduce the Total Span of the Echo Canceller (NT), Function 13.
value must be even
minimum value = 6 ifthere is a near-end
canceller
minimum value = 0 if no near-end canceller is
required
maximum value = NT
For example, if a 12.5 ms near-end canceller and a 30 ms
far-end canceller are required, parameters NT. NN and NC
should be set as follows:
NT = $0066 (42.5 ms)
Note that it is possible to make the canceller completely
near-end (NN = NT) or completely far-end (NN =0).
NN = $001 E (12.5 ms)
NC =$0024
4-152
R1496DP, R9696DP, R144DP Programmer's Guide
Application Note
modem, or rate sequence R2 is detected in the answer
modem.
Function 13: Total Span ofthe Echo Canceller
NT
=
where:
Total Span of Echo Canceller x 2.4 ms
Function 22: Far End Echo Level
NT is the decimal equivalent of the hex number which should be written into RAM.
Function 22 provides the far-end echo power level at RXA
in V.32 configurations.
(Note: programmable function is not available in B code)
Function
NN
=
where:
Far End Echo Level
14: Echo Canceller Dividing Point
where:
Echo Canceller Dividing Point x 2.4 ms
NN is the decimal equivalent of the hex number which should be written into RAM.
=-83.7 + 20 x log N dBm
N is the decimal equivalent of the hex number
which should be read from RAM.
Function 19: Round Trip Far Echo Delay
Function 22 is not valid until rate sequence R3 is detected
in the originate modem or rate sequence R2 is detected in
the answer modem.
Function 19 provides the value of the round-trip delay
measured during the V.32 handshake.
Function 18: CTS OFF·to·ON Response Time
(RTS·CTS Delay)
Round Trip Far Echo Delay
where:
=RTx 0.416667 ms
Function 18 determines the CTS off-to-on response time
in 2-wire full-duplex configurations. The response time
equation varies according to the configuration selected.
N is the decimal equivalent of the hex number
which should be read from RAM.
Configuration
Response time equation
V.32
N = (Response time x 2.4 ms) -1
V.22 bis, V.22,gell 212A N = (Response time x 0.6 ms) -1
V.23,gell 103
N = Response time x 9.6 ms
V.21
N Response time x 7.68 ms
This parameter can be read any time after the completion
of the first part of the V.32 handshake for measuring the
round-trip delay (see the V.32 specification).
=
Function 20: Echo Canceller Error
where:
Function 20 is the input to the receiver before the AGC in
V.32 configurations. It is a 9600 Hz sampled Signal. Note
that it is sampled at the transmitter timing and not receiver
timing. The parameter is a 16-bit 2s complement number.
N is the decimal equivalent of the hex number
which should be written into RAM.
The default values are listed in Table 4.
Function 21: Far End Echo Frequency Offset
Function 21 provides the far-end echo frequency offset
(FO), sometimes known as phase roll, in V.32 configurations.
Table 4. Function 18 Parameters (RTS·CTS Delay)
Default Value
Function
Far End Echo Frequency Offset = FO/1749 Hz
where:
Configuration
Hex.
Dec.
Units
V.32
V.22bis,V.22,gell 212A
V.23,gell 103
V.21
$0000
$0000
$07EO
$OFOO
0.4
1.6
210
500
ms
ms
ms
ms
18
N is the decimal equivalent of the hex number
which should be read from RAM.
Function 21 is a 16-bit 2s complement number. It is not
valid until rate sequence R3 is detected in the originate
Table 5. DSP RAM Address for TONEA, TONEB, and TONEC
TONEA
Biquad1
Blquad2
A3
A2
A1
92
91
LPF9K
LPGAIN
THRESHU
THRESHL
A7
A8
A9
27
28
29
2A
29
AA
A9
A6
26
23
A3
TONEB
Blquad1
Blquad2
2D
2E
2F
30
31
AD
AE
AF
90
91
AC
2C
24
A4
TONEC
Blquad1
Biquad2
33
34
35
36
37
93
94
95
96
97
92
32
25
A5
4-153
Prefilter
Biquad1
Blquad2
38
39
3A
39
3C
98
99
9A
99
9C
•
Application Note
R1496DP, R9696DP, R144DP Programmer's Guide
of filter characteristics to the synthesized. The only lim itation on these user-definable shapes is that their gain
should be around unity at the pass frequencies to avoid
problems of saturation at one extreme (gain too high) and
digital noise at the other (gain too low). Computation of the
filter coefficients can be performed by any infinite impulse
response (IIR) filter design program which outputs the
coefficients in cascaded second-order sections.
Function 23 through 25: Tone Detector Filter Tuning
A block diagram of the three tone detectors is shown in
Figure 2. Tone detector C is preceded by a prefilter and a
squarer. The purpose of the low pass filter (LPF) and
squarer is to allow the user to detect dual tones while
rejecting the main channel energy. The user would
program TONEC to detect a difference frequency
generated by the squarer for detection of, for example,
350 Hz and 440 Hz. The prefilter would be designed to
reject the energy in the 600 to 3000 Hz band. If the dual
tone pair of 350 and 440 Hz appeared (or unfortunately
any other frequency pair in the range of 300 to 600 Hz with
a difference of 90 Hz) TONEC would turn on.
For tone detectors A and B, there is a rule of thumb for
choosing the gain of a user-designed filter. If the user
wishes to use the default threshold value and designs the
filter for 0 dB gain in the passband, then the absolute turnon threshold will be -30 dBm. Therefore, to get a turn-on
threshold of -43 dBm, the filter should have a gain of 13
dB in the passband.
A control bit has been added in D code. This bit, called
SODIS (1 :2:6), allows the squarer in front of tone detector
C to be disabled. If the squarer is disabled then tone detector C will have four cascaded biquads (since there is a
prefilter consisting of two biquads), forming an eight order
IIR filter with user programmable coefficients.
The level detector in each of the tone detectors flags the
detection of a tone if it is in the tone detector passband and
if it is above a certain threshold defined by THRESHU. The
tone detected flag will remain set until, or unless, the tone
falls below a lower threshold defined by THRESHL.
The implementation of the filters in the ultra high speed
modems allows user definition of the characteristics of the
prefilter and the three tone detectors. Table 5 provides the
DSP RAM Address codes for the filter coefficients.
Figure 3 shows that the prefilter and the main filter sections of the tone detectors are fourth order (two-second
order biquads in cascade), thereby allowing a wide variety
The first-order low pass filter in each level detector,
defined by the coefficients LPGAIN and LPFBK, controls
the response time of each tone detector. Normally, these
coefficients will not require alteration but if, for example, a
rapid cadence must be detected on a tone, then the 3dB
BIQUAD 1
BIQUAD 2 L--_.,-_-'
TONEC BIT
TONEB BIT
Figure 2. Tone Detectors
4-154
TONEA BIT
R1496DP, R9696DP, R144DP Programmer's Guide
Application Note
design are greater than one. This is because the biquad
sections have been implemented as shown in Figure 3.
The modified values are, therefore:
cutoff is the on-time or off-time of the tone, whichever is
shorter. The gain of the filter should be set to unity.
Example:
A1'
A call-progress tone detector is required for the U.S.
telephone network and should detect the appropriate
tones only if the exceed -25 dBm.
The requirement can be met by detecting tones in the
range 250 Hz-650 Hz. A bandpass filter with a passband
of 245 Hz-650 Hz must be designed. Any filter up to fourth
order can be implemented and, normally, it is best to
choose the highest order available, especially for
bandpass designs. A design package such as FILSYN
could carry out this function by defining the passband frequencies, the filter order, the filter gain (chose unity) and
the filter sampling rate (9600 Hz). An example of suitable
coefficients is:
A1
A2
A3
-0.0437
0.0874
B1
B2
1.7369
1.8145
-0.8836
-0.8556
A3'
-0.0219
0.0437
B1'
B2'
0.8684
0.9072
-0.4418
-0.4278
The last step is to convert the above numbers to fractional 2s complement numbers, in this case:
Solution:
Biquad 1 0.0436
0
Biquad 2 0.0874 -0.1242
A2'
Biquad 1 0.0219
0
Biquad 2 0.0437 -0.0621
Blquad 1
Biquad 2
A1"
02CC
0598
A2"
0
F80C
A3"
FD34
0598
B1"
82"
6F28
741F
C774
C93E
The second part of the requirement is to detect tones only
if they exceed -25 dBm. The values of THRESHU and the
corresponding tone level detected are:
THRESHU
$1000
$0800
$0400
$0220
$0090
Tone Level Detected (dBm)
+3
-3
-10
-15
-25
THRESHU should be $90. If no hysteresis is required in
the tone detector, then set THRESHL to $90. If 6 dB of
hysteresis is required, set THRESHL to $48 (-31 dB). This
value represents half of THRESHU. Many other values of
THRESHU and THRESHL are allowable, but, normally,
The first modification to make to these values is to divide
them by two because coefficients greater than one are unrealized in the actual filter implementation. This division
should be done even if none of the coefficients in the
A1
NOTE: THE PREFILTER IS THE SAME EXCEPT FOR THE X 2 SECTION.
a. Biquad Filter
LPFBK
b. Level Detector
Figure 3. Biquad Filter and Level Detector
4-155
•
R1496DP, R9696DP, R144DP Programmer's Guide
Application Note
THRESHU =THRESHL for reliable operation. Other filter
designs may require different values to those shown
above.
Y
(after 0 code)
int( X ) is the truncated integer part of
expression X.
Table 6 shows the filter coefficient values for specific filters.
N is the decimal equivalent of the hex number
which should be written into RAM.
Function 26: RLSO On-to-Off Threshold
The number calculated for Function 26 may not give an accurate threshold. The threshold will vary from configuration to configuration and the number may need fine tuning
by trial and error to achieve the desired threshold. The
number should only be written into RAM when the modem
is in data mode with RLSO on.
Example:
If is desired to set the RLSO Off-to-On threshold to -43.5
dBm.
Then:
X = (47 - 43.5)/1.5 =3.5/1.5
=10g-1[(TOFF - TON)/10] x 1946 (B and 0 code)
N =10g-1[(TOFF - TON)/l0] x 1735 (after 0 code)
N
int( X) = 2
Y
where:
=47.5 + TON - (1.5 x int(X»
TON is the desired threshold in dBm
TOFF is the RLSO On-to-Off threshold
= 47 - 43.5 - (2 x 1.5) = 0.5
Therefore:
TON is the RLSO Off-to-On threshold in dBm.
Y = (1024 x 2) + 6456.3 (1 - 10E(-1/40»
N is the decimal equivalent of the hex number
which should be written into RAM.
Y
=2048 + 361 = 2409 = $0969
Function 27: RLSO Off-to-On Threshold
Function 28: Receiver NEWS1 Masking Register
The number calculated for Function 27 may not'9ive an accurate threshold. The threshold will vary from configuration to configuration and the num ber may need fine tuning
by trial and error to achieve the desired threshold. The
number should be written into RAM every time the modem
is in idle mode.
Writing a 1 in the bit location corresponding to the desired
bit will cause NEWS1 to go active when a status change
occurs for the selected bit. Function 28 defaults to $0000.
Figure 4 shows the applicable NEWSl masking register
bits.
Function 32: Average Energy
=[1024 x int(X)] + [6456.3 (1 - 1OE(- Y/20»]
where: X = (47 + TON)/1.5 (B and 0 code)
X = (47.5 + TON)/1.5 (after 0 code)
N
Function 32 provides the post-AGC power level. If the
receive level is above the RLSO on-to-off threshold this
value should be fairly constant and will be in the region of
$079A (8 and 0 code) or $06C7 (after 0 code). This cor-
Y = 47 + TON - (1.5 x int(X» (B and 0 code)
Table 6. OSP RAM Filter Coefficients
I
Filter
A3
1800 Hz
2250 Hz
245-650HZI
360-440 Hz,
Modem
Register
1:0F
1:0E
1:0D
1:0C
1:0B
1:0A
0372
0119
FD34
01AA
A2
FEA6
FE72
0000
FEBC
Blquadl
Al
Blquad2
Al
B2
Bl
A3
A2
0372
0130
02CC
01AA
C063
C063
C774
C7CD
30D6
OC82
6F28
7438
00C4
02D9
0630
FF5C
FFDA
FEE3
F018
0000
5
4
3
2
1
0
-
-
-
SPEED
--
U1DET
SDET
SADET
SNDET
-
-
00C4
02D9
0630
00A4
Bit
7
6
RLSD
RTDET
P2DET
AADET
TONEA
FED
-
-
-
PNDET
ACDET
TONES
S1DET
CADET
TONEC
SCR1
CCDET
ATV25
-
-
-
-
-
-
Figure 4. NEWS1 Status Bits
4-156
-
-
-
RSEQ
-
-
B2
B1
COO3
C063
C93E
C148
30D6
0C82
741F
7AGS
RAM
Register
DAMO
DALO
DAMO
DALO
DAMO
DALO
Application Note
R1496DP, R9696DP, R144DP Programmer's Guide
responds to a level of -0.5 dBm (B and D code) or -1 dBm
(after D code). If the receive level is below the RLSD offto-on threshold then this parameter indicates how far
below the threshold the receive level is.
Receive level
where:
The EQM value for the non-trellis configurations is the filtered squared magnitude of the error vector and represents the average signal power contained in the error
component. The power is directly proportional to the probability of errors occurring in the received data and can be
used to implement a discrete Data Signal Quality Detector
circuit (circuit 110 of CCITT Recommendation V.24 or circuit CG of the RS-232-C standard) by comparing the EQM
value against experimentally determined criteria (Bit Error
Rate curves). Figure 6 illustrates the relationship of the
EQM number to an eye pattern created by a four point signal structure (e.g. V.29/4800 bps) in the presence of high
level white noise. The EQM value is proportional to the
square of the radius of the disk around any ideal point. The
radius increases when signal to noise ratio (SNR)
decreases. As the radius approaches the ideal point'S
boundary values, the bit error rate (BER) increases. Curves of BER as a function of the SNR are used to establish
a criteria for determining the acceptability of EQM values.
Therefore, from an EQM value, the host processor can
determine an approximate BER value. If the BER is found
to be unacceptable, the host may cause the modem to
fallback to a lower speed to improve BER.
=TON + 10 x log (N/1946) dBm
TON is the RLSD off-to-on threshold in dBm.
N is the decimal equivalent of the hex number
which should be read from RAM.
Function 33: AGC Gain Word
Function 33 is useful for determining the receive level at
the Receive Analog (RXA) input. The number in RAM is
related to the receive level as follows:
Receive level =
(1.5 x Y - 47) - 20 * log10(1 - «N - Y x 1024)/6456.3)) dBm
(B and D code)
Receive level
=
(1.5xY - 47.5) - 20x IOg10(1 - «X- Yx 1024)/6456.3)} dBm
(after D code)
where:
Y
=int (N/1024)
It should be noted that the meaning of EQM varies with the
type of line disturbance present on the line and with the
various configurations. A given magnitude of EQM in
V.29/9600 does not represent the same BER as in
V.27/4800. The former configuration has 16 points that are
more closely spaced than the four signal points in the latter, resulting in a greater probability of error for a given
N is the decimal equivalent of the hex number
which should be read from RAM.
This formula is only valid if the receive level is above the
RLSD off-to-on threshold. If the receive level is below the
RLSD off-to-on threshold then the formula given under
Average Energy (see function 32) must be used for calculating the receive level.
If the receive level is only required to be known within 1.5
dB then just the first part of this expression (1.5 x Y - 47)
can be used.
Function 43: Eye Quality Monitor
In V.32 4800 bps, V.29, V.27, V.22bis, V.22 and Be1l212A
modes, EQM is the filtered squared magnitude of the error
vector. However, for all TCM modes (V.33 modes and
V.32 9600 and 7200 bps modes), EQM is the filtered minimum trellis path length (or metric). This gives a better indication of signal quality for trellis modes.
EQM MAGNITUDE
The error vector formed by the decision logic can be used
to indicate relative signal quality. As signal quality
deteriorates, the average error vector increases in magnitude. By calculating the magnitude of the error vector
and filter the results, a number inversely proportional to
signal quality is derived. This number is called the eye
quality monitor (EQM). Because of the filter time constant,
EQM should be allowed to stabilize for approximately 700
baud times following RLSD going active.
'. ~
.
Figure 6. Relationship of EQM to Eye Pattern
4-157
•
•
R1496DP, R9696DP, R144DP Programmer's Guide
Application Note
level of noise or jitter. Also, the type of line disturbance has
a significant bearing on the EOM value. For example,
white noise produces an evenly distributed smearing of the
eye pattern with about equal magnitude and phase error
while phase jitter produces phase error with little error in
magnitude.
HANDSHAKE TIMEOUT TIMERS
The modem has time-outs on each successive state of the
V.32 handshake. Unfortunately, the B code has one missing which could cause a lock-up of the AA/AC sequence.
It should be possible to clear this by turning off DTR and
then setting both the NEWCO and NEWCl bits. This has
been corrected in 0 code.
Since EOM is dependent upon the signal structure of the
modulation being used and the type of line disturbance,
EOM must therefore be determined empirically in each application.
If the modem fails to detect any part of the handshake it
will timeout and abort the handshake. The transmitter will
immediately stop sending the training sequence. Also,
Chip 1 when it times out loads an error code into the interface memory that indicates that point in the handshake the
time-out occurred. This code is put into register 14. The
code is not cleared even if the modem immediately goes
into a new handshake after aoorting. The user can observe
this register during the handshake to determine if an abort
occurred.
Function 44 and 45: Ring Detection Parameters
The ring detector measures the period of pulses on the
ring detect input and determines whether the pulses are
within the frequency range specified by the Maximum and
Minimum Period of Valid Ring Signal functions. Since
maximum period corresponds to minimum frequency, the
formula for calculating these functions is given in terms of
frequency.
It is a good idea for the user to successively observe the
handshake detector bits (AADET, ACDET, CCDET, etc.).
This will tell him how the handshake is progreSSing. The
user can be interrupted then for each step of the handshake to be certain of its progression.
Frequency F (in Hz) is calculated as follows:
N = 9600/F
where:
N is the decimal equivalent of the hex
number that should be written into RAM.
The V.32 Handshake Error codes and their meanings are:
Table 7 lists the Function 44 and 45 parameters.
Error Code Reason For Aborting (TIme-out)
o
No error
1
Failed to detect AC/CA transition
(calling)
2
Failed to detect AA/CC transition
(answering)
3
not used
4
Timed out waiting for power to come up
at the start of the S sequence.
5
Failed to detect the S sequence
6
not used
7
Failed to detect the Rate Sequence
(Rl,R2, or R3)
8
F ailed to detect S/S\ transition
9
F ailed to detect E sequence
A
Power loss during TRN of Rate Sequence
Table 7. Function 44 and 45 Parameters
Function
44
45
Default Value
Hex.
Dec. Units
Parameter
Maximum Period of Valid
Ring3ignal
$0280
Minimum Period of Valid
Ring Signal
$0080
15
Hz
68
Hz
Function 46 Receiver NEWS2 Masking Register
Writing a 1 in the bit location corresponding to the desired
bit will cause NEWS2 to go active when a status change
occurs for the selected bit. Function 46 defaults to $0000.
Figure 5 shows the applicable NEWS2 masking register
bits.
Modem
Register
2:0F
2:0E
7
6
5
4
-
-
-
-
-
-
Bit
3
RI
-
2
-
Figure 5. NEWS2 Status Bits
4-158
I
I
I
1
I
-
I
0
-
RAM
Register
DAMO
DALO
Application Note
R1496DP, R9696DP, R144DP Programmer's Guide
to operate during a V.22 bis handshake and TONEA
is not set by a V.22 bis calling signal at any time so if
1800 Hz is detected after the start of the V.22 bis unscrambled ones sequence, then It should still be possible to reconfigure to V.32.
V.22BISN.32 INTERWORKING
Suggestions for a possible Interworklng scheme.
Answer Modem
1. (a) Configure for V.22 bis.
(b) Set up TONEA for 1800 Hz detection,
-43 dBm threshold.
Calling Modem
1. (a) Configure V.32.
(b) Set up TONEA for 2250 Hz detection,
-43 dBm threshold.
1800 Hz Tone Detection
RAM Address
RAM Data
2250 Hz Tone Detect/on
0372
FEA6
0372
2A
C063
2B
3006
A7
OOC4
A8
FFOA
A9
00C4
AA
C063
AB
3006
2. Upon going off hook and initiating the handshake,
monitor TONEA. Note that the billing delay has to be
Implemented by the user. The R14960P/R96960P
will start to send answer tone as soon as OTR and
OATAO are both valid.
If a V.32 modem is calling, it should send an 1800 Hz
carrier at least 1 second after detecting answer tone.
If this is the case TONEA should be on. If 1800 Hz is
not detected by the end of the answer tone, then assume the calling modem is V.22 bis and set OATA1
to a 1 and allow the handshake to proceed. If 1800
Hz is detected, then immediately after the answer
tone ends (answer tone is sent for 2.7 seconds),
reconfigure to V.32, set NV25 to a 1 to ensure that
the answer tone is not sent again, and start the V.32
handshake. In this case, the user will have to implement the 75 ms silence period follOWing the answer
tone.
27
28
29
RAM Address
RAM Data
2B
A7
A8
A9
0119
FE72
0130
C063
OC82
0209
FEE3
0209'
AA
C063
27
28
29
2A
AB
OC82
2. Upon detecting answer tone using the ATV25 bit initiate a V.32 handshake in the normal manner according to V.32. After the answer tone ends and the
answering modem handshake signal begins then
monitor ACOET and TONEA for 215 ms (the time
limit is necessary because TONEA can be falsely set
when random data is sent by a V.32 answer modem,
so it should only be tested up to the end of the first S
segment in the answer handshake). If ACOET
comes on during this time then a V.32 modem is
answering. If TONEA comes on then a V.22 bis unscrambled ones sequence has been detected, so
reconfigure to V.22 bis and start the handshake.
Coefficient Values for TONEA
This scheme would have problems if the calling modem
delays in sending 1800 Hz, for instance, if thete is a
manual calling modem. However, TONEA continues
4-159
The default threshold detect values are correct for detection of signals =-43 dBm using the above coefficients.
•
Application Note
R1496DP, R9696DP, R144DP Programmer's Guide
3. Set the RTRN bit to a 1.
RETRAIN AND AUTOMATIC RATE CHANGE
The modem will then send the retrain sequence at the correct operating speed as selected in the configuration
registers. The rate sequence is automatically changed in
the training sequence to tell the other modem what speed
to operate at. When the modem detects the retrain, it will
retrain and then it will respond with retrain. This will then
retrain the modem which initiated the retrain procedure.
The status bits will change as mentioned above and the
retrain bit will be reset to a 0 when the retrain sequence is
completed.
Both V.33 and V.32 define retrain and automatic rate
change. This section explains how to perform the retrain
and rate change.
RETRAIN WITHOUT A RATE CHANGE
V.33 Configurations
When the RTRN bit is set to a 1 and the automatic rate
change bits are set to a 0, the modem will send the training sequence. The modem for which the retrain is intended
will detect the training sequence and will retrain. This can
be monitored at the transmitter by watching the state of
CTS (CTS off means going through training sequence)
and at the receiver by watching the RLSO, P20ET, and
PNOET bits. Once the retrain is completed, the process is
complete. The modem which was retrained does not
respond with a retrain. It is up to the user to set the retrain
bit for this to occur.
READING DEVICE INFORMATION FROM
THE INTERFACE MEMORY
Each OSP provides, at a specific time, the ROM checksum, device number, and revision number. This information is available (when bit N:1 E:3 is a 1) for a maximum of
5 ms after the low-to-high edge of power-on-reset. The information is located in the following registers. Register
N: 10:0-7 should be the last register read to obtain the correct information.
V.32 and V.22 bis Configurations
Register
When the RTRN bit is set to a 1, the modem will initiate the
retrain sequence. The modem which detects the retrain
sequence will respond with training, and both modems will
proceed with the proper training sequence. The retrain
process can be monitored by observing the appropriate
status bits in the transmitter and receiver.
N:15:0-7
N:14:0-7
N:13:0-7
N:12:0-7
N:11:0-7
N:10:0-7
Retrain with a Rate Change (V.33, V.32, and V.22 Bis)
where:
To obtain a rate change (V.33 and V.32) along with a
retrain the following procedure should be followed. The
rate change only occurs with CCITTV.33 and V.32 defined
configurations and not with the proprietary configurations.
N
Information
ROM Checksum MSB
ROM Checksum LSB
Device Number MSB
Device Number LSB
Revision Number MSB
Revision Number LSB
=0, 1, or 2
The information is formatted in ASCII.
The ROM checksum will remain a constant from device to
device and from revision to revision. Its value is 412B.
Steps 1 and 2 are do not apply to V.22bis
An example of a typical device number is 3036. This represents a device number of 06.
1. Set the automatic rate change bits to a 1 (ARCO,
ARC1).
An example of a typical revision number is 2042. This represents a revision of B (space B or B Code).
2. Store the desired configuration in the TCONF and
RCONF registers
NOTE: Do not set the NEWC bits.
4-160
Application Note
'1'
Rockwell
R9696DP AT' Command Set
Capabilities
II
INTRODUCTION
AT COMMAND SET DETAIL
The "AT" command set is a popular method to control a
modem which has an asynchronous interface. The interface can be serial or over a microprocessor bus through
an 8250/16450-type UART. This application note identifies
the "AT" commands used in the Hayes Smartmodem
2400. 1200 (the original 1200). and the Hayes V-series
Smartmodem 9600. and compares these commands to
the capabilities of the Rockwell R9696DP V.32/V.22 bis
Full-Duplex Modem.
Table 3 describes the AT commands. The following fields
are used to describe each of the commands and how they
should be implemented:
Consult the R9696DP Data Sheet (Order No. MD30) and
the R1496DP. R9696DP. and R144DP Programmer's
Guide Application Note (Order No. 831) for detailed
modem information.
R9696DP?: If the AT command is a modem function. can the R9696DP perform the
command?
Command: Identifies and names the AT
command.
Modifier:
Identifies and describes the command
modifiers.
Function:
Is the command a microprocessor or
modem (R9696DP) function?
Details:
AT COMMAND SET SUMMARY
S REGISTERS DETAIL
Table 1 summarizes the AT commands. If the Micro and/or
R9696 column contains a C or an M. respectively. the
command is implemented by the microprocessor (Controller) and/or R9696 (Modem). If an S is in a Smartmodem
column. then that particular modem has the command implemented. If the command modifiers for a particular command are not listed. then all of the modifiers associated
with that command are implemented for the various
modems.
The S registers provide special access to the system configurations. The registers offer flexibility in the system to
tailor it to the user's system.
Table 4 describes the S registers. The following fields are
used to describe each of the S registers and how they
should be implemented:
S REGISTER SUMMARY
Table 2 summarizes the S registers. If the Micro and/or
R9696 column contains a C or an M. respectively. the S
register is implemented by the microprocessor (Controller)
and/or R9696 (Modem). If an S is in a Smartmodem
column. then that particular modem has the S register implemented.
Register:
Identifies and names the S register.
Range:
Provides the operational range of the
function.
Default:
Provides the default range of the S
Register
Function:
Is the command a microprocessor or
modem function?
R9696DP?: If the S register is a modem function,
can the R9696DP perform it?
Details:
Document No. 29800N833
Describes the implementation details.
Application Note
4-161
Describes the implementation details.
Order No. 833
October 1988
•
R9696DP "AT" Command Capabilities
Application Note
Table 2. S Registers Summary
Table 1. AT Command Summary
AT
AI
A
B
CO
C1
0
E
FO
F1
H
I
L
M
N
0
QO
Q1
Q2
Sr=n
Sr?
V
W
X
y
Z
ZO
Zl
&C
&0
&F
&G
&J
&K
&L
&M
&P
&Q
&R
&S
&T
&V
&W
&WO
&W1
Micro R9696
C
C
C
C
C
C
M
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
+++
M
M
M
M
M
M
M
M
M
M
M
1200
2400
9600
S
s
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
M
C
C
C
C
C
C
C
C
C
M
M
M
M
M
M
M
S
S
S
S
S
S
S
M
C
C
C
C
S
S
S
S
S
S
S
S
S
C
C
&X
&y
&Zn
&Zn=x
M
M
M
M
M
S
S Register
SO
Sl
82
S3
84
85
S6
87
S8
S9
810
Sll
S12
S13
S14
815
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
827
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
8
Smartmodem
Implemented by
Smartmodem
Implemented by
AT Command
S
8
4-162
Micro R9696
C
C
C
C
C
C
C
C
C
C
C
M
M
M
M
M
M
C
C
C
C
M
C
C
C
M
M
1200
2400
9600
S
8
8
8
8
S
8
S
S
S
8
S
S
S
S
S
S
S
S
S
8
8
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
8
S
8
S
S
8
S
S
8
S
S
S
S
S
S
8
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
R9696DP "AT" Command Capabilities
Application Note
Table 3. AT Commands
Command:
Modifier:
Function:
R9696DP?:
Details:
AT
Command:
Modifier:
Function:
R9696DP?:
Details:
AI
Repeat Last Command Line
none
Microprocessor
N/A
Repeats the last command.
Command:
Modifier:
Function:
R9696DP?:
Details:
A
Answer Immediately
none
Modem
Yes
The relay driver of the modem is controlled using the RA bit. When DTR and RA
are set to a 1 and ORG is reset to a 0 the modem will answer immediately.
Command:
Modifier:
B
Various commands
Microprocessor
N/A
Signals the beginning of a command flow. Used for auto speed and character
format determination.
BO
CCITT configuration
B1
Bell configuration
Modem
Yes
The following are the configurations in the R9696DP:
CCITT
Bell
V.32
Bell 212A
V.22 bis
Bell 103
V.22
V.23
V.21
Function:
R9696DP?
Details:
Command:
Modifier:
Function:
R9696DP?:
Details:
C
Transmitter Carrier Signal
CO
Transmit carrier off
C1
Transmit carrier on
Modem
Yes
If the modem is in V.22, leased-line, controlled carrier, then RTS controls
carrier turn-on and turn-off. Otherwise, the transmitter is off when the TXSQ bit is
a 1, or the transmitter is on when TXSQ is a O.
4-163
--
•
R9696DP "AT" Command Capabilities
Application Note
Table 3. AT Commands (Cont'd)
Command:
Modifier:
0
Dial
0,1,2,3,4,5,6,7,8, 9..*,A,B, C,D Dial Digits
T
Tone dial
P
Pulse dial
R
Reverse dial
S
Dial stored number
Wait for dial tone
W
@
Quiet answer
,
Pause
I
Flash
;
Return to command state
Microprocessor and modem
Yes
The modem can dial 0-9, #, and *
When the DTMF bit is a 1, the modem dials with DTMF tones; when DTMF is a 0,
the mode dials with pulses. Reverse dial is accomplished by resetting the ORG
bit to a 0 so the modem answers after it dials. Dial a stored number is a
microprocessor function. Tone detect filter A can be used to detect dial tone and
for waiting for 5 seconds of quiet. Pause is implemented by the microprocessor.
Flash can be performed by resetting, delaying, and then setting the RA bit.
Return to command state is a microprocessor function.
E
Character Echo
EO
Disables command state character echo
E1
Enables command state character echo
Microprocessor
N/A
This option determines if the terminal is to echo or if the modem does the
echoing.
F
Duplex
FO
Full-duplex
F1
Half-duplex
Microprocessor
N/A
This function provides for the echoing or not echoing of commands
depending on the terminal configuration.
H
Hang-up
HO
Hangs the modem up (puts the modem on-hOOk)
H1
Places the modem off-hook
Modem
Yes
Disconnecting/connecting the modem from the line can be accomplished using
the RA bit.
Function:
R9696DP?:
Details:
Command:
Modifier:
Function:
R9696DP?:
Details:
Command:
Modifier:
Function:
R9696DP?:
Details:
Command:
Modifier:
Function:
R9696DP?:
Details:
4-164
R9696DP "AT" Command Capabilities
Application Note
Table 3. AT Commands (Cont'd)
Command:
Modifier:
I
Testing Internal Memory
10
Product Code
11
Firmware Checksum
12
Firmware Checksum compared to a stored number; a result code of OK or
ERROR is retumed.
Microprocessor
N/A
This function determines if the system ROM is functional.
L
Speaker Volume
LO
Low volume
L1
Low volume
Medium volume
L2
L3
High volume
Microprocessor
N/A
The microprocessor controls the volume of the line monitor speaker.
M
Speaker Control
MO
Always off
M1
On until carrier detected
On continuously
M2
M3
On after dialing until carrier detected
Microprocessor and modem
Yes
The microprocessor controls the squelching and the unsquelching of the speaker.
The RLSD bit in the modem can be used to detect carrier.
Function:
R9696DP?:
Details:
Command:
Modifier:
Function:
R9696DP?:
Details:
Command:
Modifier:
Function:
R9696DP?:
Details:
Command:
Modifier:
N
Modulation Handshake
NO
Speed of the connection is determined by S37. If S37 = 0, then the speed must
match the speed of the last AT command.
N1
Speed is determined by the DCE speed supported by both modems.
Microprocessor and modem
Yes
The microprocessor performs the speed detection from the AT command.
The modem can be set to many configurations by setting the TCONF and
RCONF bits appropriately.
0
On-line
00
Returns modem from command state to on-line state.
01
Returns modem from command state to on-line state and initiates a modem
retrain (2400 bps and higher).
Microprocessor and modem
Yes
The microprocessor handles switching from command state to on-line state.
Setting the RTRN bit in the modem to a 1 causes a retrain to be initiated.
Function:
R9696DP?:
Details:
Command:
Modifier:
Function:
R9696DP?:
Details:
4-165
•
R9696DP II AT" Command Capabilities
Application Note
Table 3. AT Command8 (Cont'd)
Command:
Modifier:
Q
Function:
R9696DP?:
Details:
Command:
Modifier:
Re8ult Code DI8play
Results codes
No result codes
Result codes in originate mode only
Microprocessor
N/A
This command determines if results codes are sent to the terminal.
00
01
02
Sr=n
Change an S Regl8ter Value
r = S register number,
n = S register value
Microprocessor and modem
Yes
Some of the S registers deal with microprocessor functions and some with
modem functions. See Table 4 for the S register functions.
Command:
Modifier:
Function:
R9696DP?:
Details:
Sr?
Reading an S Register Value
r = S register number
Microprocessor and modem
Yes
Some of the S registers deal with microprocessor functions and some with modem
functions. See Table 4 for the S register functions.
Command:
Modifier:
V
Function:
R9696DP?:
Details:
Function:
R9696DP?:
Details:
Command:
Modifier:
Function:
R9696DP?:
Details:
Result Code Form
Result codes displayed in numeric form
Result codes displayed in English form
Microprocessor
N/A
V1 is usually selected if the modem is to be used with a terminal; VO is usually used
if the modem is used with a software package on a computer.
VO
V1
W
Negotiating Progress Reporting
Error-control call progress not reported
Error-control call progress reported
Microprocessor
N/A
If selected the microprocessor returns the protocol used.
WO
W1
4-166
Application Note
R9696DP "AT" Command Capabilities
Table 3. AT Commands (Cont'd)
Command:
Modifier:
x
Function:
R9696DP?:
Details:
Result Codes and Dialing Capability
XO
Codes 0·4 enabled, blind dialing
X1
Codes 0-5,10-12,14 enabled, blind dialing
X2 Codes 0-6,10-12,14 enabled, dial tone detected
X3
Codes 0-5,7,10-12,14 enabled, busy tone detected
X4
Codes 0-7,10-12,14 enabled, dial and busy tone detected
Microprocessor and modem
Yes
The microprocessor sends the result codes. The modem can detect the call
progress tones by using TONEA. The protocol is performed by the microprocessor. 19200 bps is possible if compression is used by the microprocessor.
Result code definitions:
Numeric
0
1
2
3
4
5
6
7
8
10
11
12
14
40
46
47
48
50
70
71
72
73
Command:
Modifier:
Function:
R9696DP?:
Details:
Y
Verbose
OK
CONNECT
RING
NO CARRIER
ERROR
CONNECT 1200
NODIALTONE
BUSY
NO ANSWER
CONNECT 2400
CONNECT 4800
CONNECT 9600
CONNECT 19200
CARRIER 300
CARRIER 1200
CARRI ER 2400
CARRI ER 4800
CARRI ER 9600
PROTOCOL:NONE
PROTOCOL:ERRORCONTROULAP-B
PROTOCOL:ERROR-BUSY
CONTROULAP-B/HDX
PROTOCOL:ERROR-CONTROL./AFT
Description
Command executed
Connection at 0-300 bps
Ring detected
Carrier nol detected or lost
Invalid command etc.
Connection at 1200 bps
No dial tone detected
Busy signal detected
No answer at remote modem
Connection et 2400 bps
Connection at 4800 bps
Connection at 9600 bps
Connection at 19200 bps
Carrier detected at 300 bps
Carrier detected at 1200 bps
Carrier detected at 2400 bps
Carrier detected at 4800 bps
Carrier detected at 9600 bps
Asynchronous mode
Error-control with LAP-B
Busy signal detected
Error-control with LAP-B HDX
Error-control with AFT
Long Space Disconnect
YO
No recognition or respond to a long space disconnect
Y1
Recognize and respond to a long space disconnect
Microprocessor and modem
No long space disconnect function but can implement
The transmission of a long space disconnect sequence can be accomplished by sending
a long break sequence or by reconfiguring the modem to synchronous mode and
send spaces. If the microprocessor detects the long space sequence, it should
clamp the RXD Signal to the terminal to a space and then disconnect the modem
from the line.
4-167
•
R9696DP "AT" Command Capabilities
Application Note
Table 3. AT Commands (Cont'd)
Command:
Modifier:
Z
Recalling a Stored User Profile
ZO
Resets the modem and recalls user profile 0
Z1
Resets the modem and recalls user profile 1
Microprocessor and modem
Yes
The microprocessor must drive the paR input low then high to reset the modem, and
then get the profile and reconfigure the system.
&c
Carrier Detect Option
&CO Carrier detect to the terminal is always active
&C1 Carrier detect of the modem is provided to the term inal
Microprocessor and modem
Yes
The two methods are possible for implementing this function. The microprocessor can
drive the DCD pin of the RS-232 connector directly so that it can clamp the line
active if that option is selected. The microprocessor, however, will have to
monitor the RLSD bit in the modem and drive the RS-232 line ~riately when
the bit goes active and inactive. Another method is to gate the RLSO hardware
signal with a microprocessor output. The microprocessor output can drive the
input of the gate to one polarity to cause DCO to always be active and it can
drive the output the other direction to allow OCO to follow the modem's RLSO output.
&D
Data
&00
&01
&02
Terminal Ready Option
DTR from the terminal is ignored
DTR going on-to-off causes modem to enter command state
OTR going on-to-off causes modem to enter command state, hang-up, and disable
auto answer
&03 OTR going on-to-off causes modem to enter command state and reset the modem
Microprocessor and modem
Yes
The microprocessor controls the entering and exiting of the command state as well as
implementing the auto answer routine. The microprocessor must control the DTR
input of the modem (this can be the bit or the pin) since OTR is the mechanism
by which the modem is told to start or terminate a handshake. A modem reset is
performed by toggling the paR input.
&F
Retrieving The Factory Configuration
none
Microprocessor
N/A
This command recalls the factory configuration stored in ROM and completely replaces
the current configuration.
Function:
R9696DP?:
Details:
Command:
Modifier:
Function:
R9696DP?:
Details:
Command:
Modifier:
Function:
R9696DP?:
Details:
Command:
Modifier:
Function:
R9696DP?:
Details:
4-168
R9696DP "AT" Command Capabilities
Application Note
Table 3. AT Commands (Cont'd)
Command:
Modifier:
&G
Guard Tone Selection
&GO No guard tones
&G1 550 Hz guard tone
&G2 1800 Hz guard tone
Modem
Yes
The modem bit GTE, when set to a 1, enables guard tones. When GTS is a 1, 550 Hz
guard tone is selected; when GTS is a 0, 1800 Hz guard tone is selected.
&J
Telephone Jack Selection
&JO RJ11, RJ41S, or RJ45S type
&J1 RJ12 or RJ13 type
Microprocessor
N/A
Option &JO is for typical use. Option &J1 is for key telephone systems.
&K
DTE Flow Control
&KO Local flow control disabled
&K1 Reserved
&K2 Reserved
&K3 RTS/CTS local flow control
&K4 XON/XOFF flow control
&K5 Transparent XON/XOFF flow control
Microprocessor
N/A
This option is used for error control.
Function:
R9696DP?:
Details:
Command:
Modifier:
Function:
R9696DP?:
Details:
Command:
Modifier:
Function:
R9696DP?:
Details:
Command:
Modifier:
&L
Line Type
&LO Dial-up line
&L1 Leased line
Modem
Yes
The R9696DP provides a leased-line controlled carrier operation for the V.22 and
V.22 bis configurations. Setting the LLn, and CCn bits to a 1 will accomplish this.
RTS will then control the state of the carrier whether it is on of off. All the other
configurations operate the same whether the modem is in a leased line or dial-up
line environment.
&M
Communications Mode
&MO Asynchronous mode
&M1 Asynchronous command mode, synchronous data mode
&M2 Synchronous mode, dial a stored number
&M3 Synchronous mode, manual dial with talk/data switch
Microprocessor and modem
Yes
Synchronous modem is selected by resetting the ASYNn bits to a O. Setting the ASYNn
bits to a 1 configures the modem for asynchronous mode. WDSZn, STBn,
PENn, and EXOSn configure the modem for the correct word size, stop bit number, number of parity bits used, and extended overspeed, respectively.
Function:
R9696DP?:
Details:
Command:
Modifier:
Function:
R9696DP?:
Details:
4-169
•
R9696DP "AT" Command Capabilities
Application Note
Table 3. AT Commands (Cont'd)
~-~C~0-m-m--an-d7:----&~P--------=P-u~ls-e~D~i~a71~P-a-ra-m--~~e-rs-----------------------------------------------'
Modifier:
&PO 39%/61% make/break ratio
&P1 33%/67% make/break ratio
Modem
Yes
The R9696DP defaults to 36%/64% make/break time. The make and break times for the
autodialer can be changed via the RAM write facility of the modem.
RAM Data = Time (sec) * 9600
Function
RAM Address
CRO bit
Time
Data
Make time
$9C
1
33%
$013D
Make time
$9C
1
39%
$0176
Break time
$1 C
1
61 %
$024A
Break time
$1 C
1
67%
$0283
The pulse dialer in the D code version of the R9696DP does not function. The
microprocessor, in this case, will have to pulse the off-hook relay directly using
the RA bit.
Function:
R9696DP?:
Details:
Command:
Modifier:
&0
Communications Mode and Error Control
&00 Asynchronous mode
&01 Asynchronous command mode, synchronous data mode
&02 Synchronous mode, dial a stored number
&03 Synchronous mode, manual dial with talk/data switch
&04 AutoSync
&05 Error Control
Microprocessor and modem
Yes
Synchronous modem is selected by resetting the ASYNn bits to a O. Setting the
ASYNn bits to a 1 configures the modem for asynchronous mode. WDSZn,
STBn, PENn, and EXOSn configure the modem for the correct word size, stop bit
number, number of parity bits used, and extended overspeed respectively.
&R
RTS/CTS Option
&RO Command state-RTS ignored, On-line CTS follows RTS
&R1 RTS is ignored and CTS is alway active
Microprocessor and modem
Yes
The two methods are possible for implementing this function. The microprocessor can
drive the CTS pin of the RS-232 connector directly so that it can clamp the line
active if that option is selected. The microprocessor, however, will have to
monitor the CTS bit in the modem and drive the RS-232 line a~riately when
the bit goes active and inactive. Another method is to gate the CTS hardware signal with a microprocessor output. The microprocessor output can drive the input
of the gate to one polarity to cause CTS to always be active and it can drive the
output the other direction to allow CTS to follow the modem's CTS output.
Function:
R9696DP?:
Details:
Command:
Modifier:
Function:
R9696DP?:
Details:
4-170
Application Note
R9696DP "AT" Command Capabilities
Table 3. AT Commands (Cont'd)
Command:
Modifier:
&5
D5R Options
&SO DSR always active
$81 DSR operates according to the appropriate specification
Microprocessor and modem
Yes
The two methods are possible for implementing this function. The microprocessor can
drive the DSR pin of the RS-232 connector directly so that it can clamp the line
active if that option is selected. The microprocessor, however, will have to
monitor the DSR bit in the modem and drive the RS-232 line a~riately when
the bit goes active and inactive. Another method is to gate the DSR hardware signal with a microprocessor output. The microprocessor output can drive the input
of the gate to one polarity to cause DSR to always be active and it can drive the
output the other direction to allow DSR to follow the modem's DSR output.
&T
Tests
&TO Terminate a test in progress
&T1 Local analog loopback
&T3 Local digitalloopback
, &T4 Grant remote digitalloopback request from remote modem
&T5 Deny remote digitalloopback request from remote modem
&T6 Remote digitalloopback
&T7 Remote digitalloopback with self test
&T8 Local analog loopback with self test
Microprocessor and modem
Yes
The R9696DP does not generate and test a self test pattern. This function must be
performed in the microprocessor. Local digitalloopback must also be performed
by the microprocessor. The tests are established and terminated using the following bits.
Bit
Function
L2ACT
Locally activated remote digitalloopback
L3ACT
Local analog loopback
RDL
Remote digitalloopback
ROLE
Remote digitalloopback enable
V.22, V.22 bis, and Bell 212A are the only configurations which support the RDL bit. To
obtain a remotely activated digital loopback for the remaining configuration, a signalling scheme must be developed between the modems. In this case, the
L2ACT bit would be used.
Function:
R9696DP?:
Details:
Command:
Modifier:
Function:
R9696DP?:
Details:
Command:
Modifier:
Function:
R9696DP?:
Details:
&V
View Active Configuration and User Profiles
none
Microprocessor
N/A
The microprocessor must display the active configuration, user profiles 0 and 1, and
stored telephone numbers.
4-171
•
R9696DP "AT" Command Capabilities
Application Note
Table 3. AT Commands (Cont'd)
Command:
Modifier:
&W
Function:
R9696DP?:
Details:
Command:
Modifier:
N/A
Saves the active configuration of the system.
&X
Transmit Clock Source
&XO Modem generates the transmit clock
&X1 Terminal generates the transmit clock
&X2 Modem uses the receive clock as the transmit clock
Modem
Yes
Tl1e TXCLK bits in the R9696DP can be used for this command.
Function
TXCLK
Modem generates the transmit clock
0
2
Terminal provides the transmit clock
Modem uses the receive clock as the transmit clock
3
&y
Designating The Default User Profile
&YO Profile 0 is designated as the default profile
&Y1 Profile 1 is designated as the default profile
Microprocessor
Function:
R9696DP?:
Details:
Command:
Modifier:
Function:
R9696DP?:
Details:
Command:
Modifier:
Write a Profile to Memory
&WO Write the storable parameters of the active configuration to profile 0
&W1 Write the storable parameters of the active configuration to profile 1
Microprocessor
N/A
The microprocessor must use the selected profile on power-up.
&Zn=x
Function:
R9696DP?:
Details:
Store Telephone Number
number location (0-3)
n=
telephone number
x=
Microprocessor
N/A
This command allows the storage of up to four telephone numbers.
Command:
Modifier:
Function:
R9696DP?:
Details:
+++
Command:
Modifier:
Function:
R9696DP?:
Details:
Escape Code
none
Microprocessor
N/A
Used to exit from on-line mode to command mode.
Carrage Return
none
Microprocessor
N/A
Used to terminate a command line
4-172
R9696DP "AT" Command Capabilities
Application Note
Table 4. S Registers
Register:
Range:
Default:
Function:
R9696DP?:
Details:
SO
Rings to Answer On
0- 255 rings
0
Microprocessor and modem
Yes
The R9696DP has a ring detector which can be monitored by the microprocessor.
When the desired amount of rings are detected, the microprocessor can place
the modem off-hook by setting the RA bit in the modem. When SO is 0, auto
answer is disabled.
Register:
Range:
Default:
Function:
R9696DP?:
Details:
S1
Ring Count
0- 255 rings
0
Microprocessor and modem
Yes
The R9696DP has a ring detector which can be monitored by the microprocessor.
When the rings are detected, the microprocessor can increment the S1 location.
Register:
Range:
Default:
Function:
R9696DP?:
Details:
S2
Escape Sequence Character
0-127 ASCII
43 (+)
Microprocessor
N/A
Used to exit from on-line mode to command mode. A value greater than 127 disables
the escape sequence preventing the modem from returning to the command
state.
Register:
Range:
Default:
Function:
R9696DP?:
Details:
S3
Carriage Return Character
0-127 ASCII
13
Microprocessor
N/A
Used to terminate a command line.
Register:
Range:
Default:
Function:
R9696DP?:
Details:
S4
Line Feed Character
0-127 ASCII
10
Microprocessor
N/A
Used to terminate a command line.
Register:
Range:
Default:
Function:
R9696DP?:
Details:
S5
Backspace Character
0- 32,127 ASCII
8
Microprocessor
N/A
Used to delete characters in the command line.
4-173
•
R9696DP "AT" Command Capabilities
Application Note
Table 4. 8 Registers (Cont'd)
Register:
Range:
Default:
Function:
R9696DP?:
Details:
86
Walt Time Before Blind Dialing
2 - 255 seconds
2 seconds
Microprocessor
N/A
After the off-hook relay is closed, a delay specified by S6 should be performed before
dialing the first digit. This delay is to ensure that dial tone is present on the line
before dialing the first digit.
Register:
Range:
Default:
Function:
R9696DP?:
Details:
87
Walt Time for Carrier/Dial Tone
1 - 255 seconds
30 seconds
Microprocessor and modem
Yes
S7 determines the wait time between dialing and responding to an incoming carrier
signal. S7 also is used for the W dial modifier as the time the dialer will wait for
the detection of dial tone.
RLSD can be used for carrier detection and TONEA is preprogrammed for the bandwidth
which contains the dial tone frequencies.
Register:
Range:
Default:
Function:
R9696DP?:
Details:
S8
Register:
Range:
Default:
Function:
R9696DP?:
Details:
S9
Carrier Detect Response Time
1 - 255 1/10 seconds
6 seconds
Microprocessor and modem
No
S9 determines how many seconds a carrier must be present before the modem will
recognize it as a carrier. The user can monitor FED and RLSD and can make a
determination whether or not the OeD signal should be activated or not. The
RLSD response time can not be changed in the R9696DP.
Register:
Range:
Default:
Function:
R9696DP?:
Details:
S10
Delay Between Carrier Loss and Hang-up
1 - 255 1/10 seconds
1.4 seconds
Microprocessor and modem
Yes
S10 specifies the delay between the loss of the remote carrier and the local modem
disconnecting from the line. This can be done by monitoring RLSD. When RLSD
goes inactive, delay the amount of time specified in S10 and check RLSD again.
If RLSD is still inactive, write a 0 into RA to open the off-hook relay. Setting 810
to 255 causes the modem to ignore the actual carrier status and assume the carrier is always present.
Duration of Comma DIal Modifier
o - 255 seconds
2 seconds
Microprocessor
N/A
This is the delay time used for the comma dial modifier.
4-174
Application Note
R9696DP "AT" Command Capabilities
Table 4. S Register. (Cont'd)
Register:
Range:
Default:
Function:
R9696DP?:
Details:
S11
Register:
Range:
Default:
Function:
R9696DP?:
Details:
S12
Register:
Range:
Default:
Function:
R9696DP?:
Details:
S13· S17
Register:
Range:
Default:
Function:
R9696DP?:
Details:
S18
Register:
Range:
Default:
Function:
R9696DP?:
Details:
S19·S24
DTMF Tone Duration and Interdlglt Delay
50 - 255 milliseconds
95 milliseconds
Modem
Yes
The DTMF tone duration and interdigit delay can be programmed via the RAM write
facility in the R9696DP. The default duration is 95 ms and the default interdigit
delay is 70 ms.
RAM Data = Duration (sec) * 9600
Function
RAM Addreas CRO bit Duration
Data
95ms
DTMF Duration
$9A
$0390
1
Interdigit Delay
$1A
$0390
1
95ms
Escape Sequence Guard TIme
0-2551/50 seconds
1 second
Microprocessor
N/A
S12 holds the delay required prior to and following the escape sequence.
•
none
N/A
N/A
N/A
Reserved
Modem Teat Timer
o - 255 seconds
0
Microprocessor
N/A
This register establishes the length of the modem tests.
none
N/A
N/A
N/A
Reserved
4-175
R9696DP II A Til Command Capabilities
Application Note
Table 4. S Registers (Cont'd)
Register:
Range:
Default:
Function:
R9696DP?:
Detaiis:
S25
DTR Detection
0- 2551/100 seconds
5 seconds
Microprocessor
N/A
In synchronous mode 1 and 4, the time specified by this register is the amount of time
DrR from the terminal is ignored after a connection is established. During this
time the units are seconds, not 1/100 seconds. This allqws the user to disconnect an asynchronous terminal and connect a synchronous terminal to the
modem. Once the connection is made (this applies to the other modes as well)
the units are 1/100. Any change of DTR which is shorter than the time specified
by S25 is ignored.
Register:
Range:
Default:
Function:
R9696DP?:
Details:
S26
RTS to CTS Interval
0- 2551/100 seconds
.01 seconds
Microprocessor and modem
Yes
S26 is used to specify the RTS active to CTS active delay. This value takes effect when
the &RO command has been executed. This applies to synchronous mode 1,2,
and 3 only.
The RTS to CTS delay can be programmed via the RAM write facility of the R9696DP.
Function
RAM Address
CRO Bit
RTS/CTS delay
$10
Response Time Equations
Configuration
V.32
V.22 bis, V.22, Be1l212A
V.23, Bell 103
V.21
Response Time Values
Configuration
V.32
V.22 bis, V.22, Be1l212A
V.23, Bell 103
V.21
Equation
N=(time*2.4)ms -1
N=(time*0.6)ms -1
N=time*9.6 ms
N=time*7.68
Default
(Dec.)
0.4 ms
1.6 ms
210 ms
500 ms
Value
(Hex.)
$0000
$0000
$07EO
$OFOO
Min.
(Dec.)
0.4 ms
1.6 ms
Oms
Oms
Value
(Hex.)
$0000
$0000
$0000
$0000
To obtain the minimum time specified by S26, the RTS to CTS delay seen at the
RS-232 connector must be controlled by the microprocessor instead of the
R9696DP for those configurations which do not have a minimum RTS to CTS
response time of 0 ms.
4-176
R9696DP "AT" Command Capabilities
Application Note
Table 4. S Registers (Cont'd)
Register:
Range:
Default:
Function:
R9696DP?:
Details:
S27 - S35
Register:
Range:
Default:
Function:
R9696DP?:
Details:
S36
Negotiation Failure Treatment
0,1
1
Microprocessor
N/A
This register tells the modem how to respond if an error correction connection fails.
Register:
Range:
Default:
Function:
R9696DP?:
Details:
S37
DCE Line Speed
0-9
0
Microprocessor and modem
Yes
The modem attempts to connect with a remote modem at the highest supported
DCE data rate that does not exceed the value specified by 837.
0 = Connect at speed of last AT command
1-3 = Connect at 300 bps
4
= Reserved
5
= Connect at 1200 bps
6
= Connect at 2400 bps
7
= Connect at 4800 bps
8 = Reserved
9
= Connect at 9600 bps
The R9696DP can automatically fallback and fall forward in V.32. The modem
also can fallback and fall forward from V.22bis to V.22. Any other interworking
must be performed manually by the microprocessor detecting what the remote
modem is. This can be done by programming the tone detectors to recognize
the beginning of various handshakes. After a handshake is recognized the
microprocessor can reconfigure the modem.
Register:
Range:
Default:
Function:
R9696DP?:
Details:
538
none
N/A
N/A
N/A
Reserved
Delay Before Forced Hang-up
o - 255 seconds
20 seconds
Microprocessor and modem
Yes
838 specifies the delay between a command to hang-up (or the on-to-off transistion
of DTR if programmed) and the actual disconnection of the line. This is useful in
the error correction configuration to ensure that all the data in the transmit buffer
is transmitted.
If the value in 838 is 255, the modem does not timeout and will continue to transmit
until the connection is lost.
4·177
•
4-178
SECTION 5
Image Modem Application Notes
R96FI/R96MD Modem Tone Detector Filter Tuning .................................... 5-3
R96FI/R96MD Modem Recommended Receive Sequence for Group 2 Facsimile ............. 5-9
DTMF Dialing Using the R96MD Modem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-12
DTMF Dialing for R24MFX, R48MFX, R24BKJ, or R48BKJ ............................. 5-19
R96MFX Modem Recommended Receive Sequence for Group 2 Facsimile ................ 5-27
R96EFX HDLC Operation ....................................................... 5-30
R144HD DSP Programming Guide for the Host Computer .............................. 5-38
•
5-1
5-2
Application Note
'1'
R96FI/R96MD Modem
Tone Detector Filter Tuning
Rockwell
INTRODUCTION
The energy averaging filter has a transfer function:
The Rockwell R96FI and R96MD modems include three
independent tone detectors (FR1, FR2 and FR3). These
tone detectors are operational when the modem is configured for V.21 FSK, and are centered upon power-up to
2100 Hz (FR1), 1100 Hz (FR2), and 462 Hz (FR3). This
application note presents a method of tuning these detectors to any desired frequency in the 400 Hz - 3 kHz band.
2a'
(Eq.3)
The output of the energy averager is fed to a threshold
comparator which sets, or resets, the appropriate bit (FR1,
FR2 and FR3) in the signal processor (SP) scratch pad
memory if the energy output is equal to or greater than 1/8,
or less than 1/8, respectively.
COMPUTATION OF TONE DETECTOR
COEFFICIENTS
Filters 1 and 2 have a typical frequency response as
shown in Figure 2. When cascaded, they form a bandpass
filter with a narrow bandwidth as shown in Figure 3.
Each tone detector consists of two second-order filters in
cascade, an energy averaging filter, and a threshold comparator. A diagram of the tone detector is shown in
Figure 1.
Given the transfer functions H1 (Z) and H2(Z), an analytical
method is required to compute their coefficients for any
desired frequency in the 400 Hz - 3 kHz band. First, consider H1 (Z). This transfer function can be rewritten as:
Filter 1 has a transfer function:
2ar
2a
(Eq.1)
H1(Z) =
Filter 2 has a transfer function:
which has a conjugate pair of poles:
2a'
=111 + j v'(111 2 + 2112)
P2 =111 - j v'(111 2 + 21\2)
P1
(Eq.2)
a(1)
2
(Eq.4)
0<'(4)
2
0<"(7)
It--i..xr-1.
INPUT
}-----...-OUTPUT
TO THRESHOLD
COMPARATOR
FRn
FRn
1ST BI-QUAD FILTER
2ND
BI.QUAD FILTER
=1 IF OUTPUT .. 118
=0 IF OUTPUT < 1/8
ENERGY AVERAGING
NOTE: NUMBERS IN ( ) REFER TO NODE NUMBERS IN TABLE 2.
Figure 1. Tone Detector Diagram
Document No. 29800N68
Application Note
5-3
Order No. 668
Rev.2,January1989
•
Application Note
R96FI/R96MD Modem Tone Detector Filter Tuning
These poles lie on a circle of radius 0.994030884 on the
Z-plane. The radius of the tone detector circle was chosen
so that each filter has a high Q without being unstable (Le.,
poles must lie inside the unit circle for stability). Figure 4
shows a Z-plane pole-zero diagram for an arbitrary conjugate pole pair on the tone detector circle. The angle e =
360· x fo/fs, where fo is the desired center frequency and
fs isthe sampling rate (fs = 9600 Hz). The following equations are derived from the angle and magnitude of the position vector pointing to a pole pair located at the desired
angle:
cos-1(131/r) = e = 360· x fo/fs
1100 "
a = a'=
(Eq.8)
a" =
1 + 9600t
(Eq. 13)
13"=
(1 + 1/960Ot)
(Eq.14)
Upon power-up, a" and 13" are set for 't = 0.1 seconds. Unless different tone detector response times are required,
these coefficients need not be changed.
In deriving these equations, only H1 (Z) was considered.
However, the tone detector consists of two identical filters
in cascade. Referring to figure 5, shifting filter 1 and filter
2 above and below the desired center frequency, a
response with the desired bandwidth is achieved. Furthermore, since a controls the amplitude response, one may
set a = a' to uniformly raise or lower the overall cascade
response.
Table 1 contains the computed values of the filter coefficients, including those of default frequencies 462 Hz, 1100
Hz, and 2100 Hz. The value 32767 (hex 7FFF) is full scale
in the SP's machine untis (Le., 32767 = unity). Coefficients
may range from -1 to +1 (or FFFF to 7FFF in machine
units).
WRITING NEW COEFFICIENTS INTO THE
SIGNAL PROCESSOR (SP) RAM
From Equation 8, we see that:
132 = 13'2 = - ~/2 = -0.494048699
The RAM ACCESS B register (1 :F) allows the host processor to specify an access code for RAM data registers. The
access code specifies the RAM location being written.
Table 2 contains the RAM access codes for all filter coefficients.
Rewriting Equation 7 in terms of the offsets fA and f' A :
131 = r cos [360· (fo - fA)/fs]
(Eq.9)
13'1 = r cos [360· (fo + f'A)/fs]
(Eq. 10)
The frequency offset is approximately 72% of B/2 (half the
bandwidth) :
f'A'" 0.72 (B/2)
The proper procedure for writing new coefficients into the
SP RAM is as follows:
(Eq. 11)
1. Store the desired access code into register 1:F.
The value of fA should be equal to f'A. However, fA may
be chosen 1% smaller than f' A to compensate for the fact
that the overall cascade response is not prefectly symmetrical (see Figure 5).
2. Read Register 1:0 to reset MOA1.
3. Wait for bit MOA1 (1 :E:O) to be a 1.
4. Set the RAM write bit (1 :0:0)
The values for the coefficient a and a' that set I H(fo)1 =
odB in equations 1 and 2 were measured and plotted versus center frequency fo as shown in Figure 6.
5. Write the two halves of the 16-bit coefficient into
registers 1:1 and 1:0. (Register 1:1 is the MSB.)
Three equations corresponding to three linear approximations result:
,
a = a =
a = a'=
6. Wait for bit MOA1 (1 :E:O) to be a 1.
7. If more data is to be written, change RAM access
code and go to step 5.
(104/319)(0-78.62
32767
400"fo,,1100Hz
(Eq.12c)
The coefficients of the energy averaging filter are determined by a Z-domain approximation to an RC circuit of
transfer function: H(S) = 1/1 + S't.
Solving for 131 and 132:
f32 = - ~/2
(Eq.12b)
ENERGY AVERAGING FILTER
(Eq. 5)
(Eq.7)
1650 Hz
1650" fo" 3000 Hz
v'J:1312 + (-131 2 - 2(32)]= r = 0.994030884 (Eq. 6)
131 = r cos (360· x fo/fs)
fo "
(4/45)(0 + 221
32767
8. Reset RAM write bit (1 :0:0).
(Eq. 12a)
Writing to Register 1:0 resets MOA1 (1:E:O) to a 0 and
starts the write cycle, which ends by MOA1 returning to a
1. The RAM write bit (1 :0:0) must remain set until the end
ofthe cycle.
(44/275)fo + 104
32767
5-4
Application Note
R96FI/R96MD Modem Tone Detector Filter Tuning
500
2000
3000
FREQUENCY (Hz)
Figure 2. Typical Single Filter Response
•
500
1000
2000
FREQUENCY (Hz)
Figure 3. Typical Cascade Filter Response
5-5
Application Note
R96FI/R96MD Modem Tone Detector Filter Tuning
ImZ
90· 2400 Hz
UNIT CIRCLE r = 1
180·
4800 Hz
-1
+11
,
360·
9600 Hz
\
\
\
\
,,
" .....
-
-11
270· 7200 Hz
Figure 4. Z-Plane Pole·Zero Diagram
5·6
Re Z
R96FI/R96MD Modem Tone Detector Filter Tuning
Application Note
I
I
1
I /
I
I
1/
I
/
/1
/
/
/
/
,
./
,;'
fo - fA
fo
fo + fA
FREQUENCY (Hz)
Figure 5. Bandwidth and Offset Frequencies
Ea.12b"'\. / .
yEa.12C
500
",
",
450
",
",
400
",
350
.......... 300
N
M
x
oct
250
:t:
Go
-'
oct
100
50
0
0
1000
FREaUEN~Y
(Hz)
Figure 6. Alpha-zero Center Frequency
5-7
•
Application Note
R96FI/R96MD Modem Tone Detector Filter Tuning
Table 1. Calculated Coefficient Values
Coefficient Value
Frequency Detected
2100 Hz ±25 Hz
Coefficient Name
0.=0.'
~1
W1
fA-18Hz
~2 = W2
1850 Hz ±24 Hz
0.=0.'
~1
W1
fA _18 Hz
~2 = W2
1650 Hz ±23 Hz
a=a'
~1
fl'1
fA .18 Hz
132 = fl'2
1100 Hz ±30 Hz
a=a'
~1
W1
fA-19 Hz
132 = W2
462 Hz ±14 Hz
0.=0.'
131
fl'1
fA" 10 Hz
~2 = W2
Table 2. Filter Coefficients Access Codes
Node
No. (n)
Name
Access Code (Hex)
FR1
FR2
FR3
1
a
2E
34
3A
2
~1
2F
35
3B
3
~2
30
36
3C
4
a'
2B
31
37
5
fl'1
2C
32
38
33
39
6
W2
20
7
a"
B7
B9
BB
8
~"
B8
BA
Be
5-8
Hex
0198
1A4A
175A
COC4
0180
2E37
2B69
COC4
0170
3048
3AA6
COC4
0118
60BE
5E9C
COC4
0048
79F3
7974
C083
Decimal
408/32767
6730/32767
5978/32767
-16188/32767
384/32767
11831/32767
11113/32767
-16188/32767
368/32767
15688/32767
15014/32767
-16188/32767
280/32767
24754/32767
24220/32767
-16188/32767
72/32767
31219/32767
31092/32767
-16253/32767
Application Note
'1'
R96FI/R96MD
Modem Recommended Receive Sequence
for Group 2 Facsimile
Rockwell
b. Reset control bit G2FGC (1 :C:O) to a zero to select
slow AGC state. This action changes the Group 2
PLL characteristics to match reduced AGC
response.
INTRODUCTION
The R96FI and R96MD include a transmit and receive
configuration that is compatible with the transmission
scheme of Group 2 facsimile equipment. In order to
achieve the best results with Group 2 reception, the following procedure is recommended. The step numbers are
keyed to points in Figure 1. Refer to the respective data
sheets, R96FI (MD06) and R96MD (MD34) for details on
how to configure the modem and write modem data to chip
one.
c. Read and save the 16-bit value from registers 1:3
and 1:2 using access code C2. This value represents the frequency error term from the Group 2
PLL.
d. Verify that phasing signal is still being received.
This action guarantees that AGC value was
frozen during phasing signal.
METHOD
e. If step d above determines that phasing signal is
present, allow transmission of CFR. If phasing
signal is not present, suppress CFR.
IGC
I
3. Exit Group 2 configuration.
2100 Hz
2
3
4
4. At completion of CFR transmission, re-enter Group 2
configuration and wait 5 milliseconds to complete initialization. Then:
5 6
Figure 1. Group 2 Facsimile Sequence
a. Repeat step 1.b.
1. Enter Group 2 configuration and wait 5 milliseconds to
complete initialization. Then:
b. Repeat step 2.a.
c. Add hex 0038 to the value saved in step 2.c above
and write the sum using access code C2. This action forces a 9 Hz error as in step 1.a.
a. Write hex 0038 using access code C2. This action
sets the Group 2 phase-locked-loop (PLL) for a
frequency correction of 9 Hz, causing the phase
term to drift rapidly to overcome any tendency to
slow phase recovery.
5. Wait for start of Group 2 message transmission. Then:
a. Write hex 0400 using access code AA. This action
restores the AGC slew rate to the default value.
b. Write hex 4000 using access code F1, and hex
7FFF using access code 71. This action allows
the Group 2 PLL to accept the greatest number of
samples for carrier recovery during phasing.
b. After 2 lines, write the value saved in step 2.c
using access code C2. This action removes the 9
Hz forced frequency error without waiting for the
phase-locked-loop to complete the correction.
This step is optional as the correction will eventually be completed, but, depending on the percentage of white in the document being sent, the
correction may take from 4 to 16 lines (100 ms of
white required).
c. Write hex 2000 using access code AA. This action
sets the AGC slew rate for very fast acquisition.
d. Set control bit G2FGC (1 :C:O) to a one to select
fast AGC state.
2. After phasing is detected, wait approximately 2
seconds for the AGC circuit to settle. Then:
a. Write hex 0000 using access code AA. This action
stops AGC tracking in order to preserve the
present AGC setting.
Document No. 29600N55
Application Note
Order No. 655
Re~3,January1989
5-9
•
R96FI/R96MD Modem
Application Note
a. Write hex 6100 using access code F1, and hex
0600 using access code 71. This action places
narrow limits on the received Signal used for carrier recovery during message reception and
reduces the chance of errors caused by repeated
patterns in the message.
The magnitude of 1A 1 + 1B 1 is directly proportional to
the slope of line segment AB and is, therefore, an indicator of frequency. If H represents the value stored at
F1 and L represents the value at 71, then 1 - [lAI +
1B 11 + H must be less than positive full scale or the frequency is excluded for being too low. Also, 1 - [I AI +
1Bl1 + H + L must be greater than positive full scale or
the frequency is excluded for being too high.
b. Synchronize the modem's Group 2 PLL to the facsimile machine's blanking signal as follows:
(1) Freeze the phase-locked-loop during data by:
The average value for 1 - [I A 1 + 1B 11 with an all white
transmission and back-to-back connection is hex 19A1
± 0543.
6. After approximately 6 to 10 seconds of message
reception, perform either step a or step b below:
(a)
Writing hex 7FFF using access code F1.
(b)
Writing hex 0000 using access code 71.
5. Access code hex 00F2 in chip 1 allows host control of
the limits placed on phase error correction. When the
phase error exceeds the limit set by F2, PLL updating is suspended. The default value of 5000 corresponds to a limit of ± 67.5 degrees. A zero in F2
causes the PLL to update for any phase error. By
resetting F2 to a zero, it may be unnecessary to
force a frequency offset in the receive sequence.
(2) Enable the phase-locked-loop during the
white margins by:
(a)
Writing hex 4000 using access code F1.
(b)
Writing hex 7FFF using access code 71.
(c)
The sequence of writing in step 6.b is
important and must be performed as
described. Option 6.b requires more
action by the host processor, but it
eliminates the possibility of data patterns
affecting carrier recovery.
For systems using step 6.a in the receive sequence,
reception of messages containing a large amount of
black may be improved by setting F2 to zero. F2 scaling is:
Phase limit = 180· - [(F2 value/7FFF) x 1801
PARAMETER SCALING
Once phaSing is acquired, the limits may be narrowed
to improve immunity to phase hits, etc.
1. Access code C2 represents frequency error, i.e., the
deviation of received carrier from 2100 Hz.
BLACK/WHITE THRESHOLD
LSB = 0.167 Hz; Range = ± 140 Hz
The R96FI/R96MD receives a Group 2 baseband signal
that contains density (gray scale) information in the
amplitude modulation. In order for this information to be
used on a Group 3 facsimile machine, the modem converts the gray scale to black/white baseband form. The
threshold at which the black/white decision is made determine the density of the received page.
2. Access code FO represents the Group 2 PLL slew
rate for the first order term. The num ber is directly
proportional to slew rate. The range of stable operating values is 0010 to 7000 in hexadecimal.
3. Access code AA represents the AGC slew rate.
Range = 0000 to 7FFF in hexadecimal
Scaling: See Figure 2.
Access code 2A represents the Group 2 black/white
threshold. This location defaults to hex 7800 at POR time.
The number may be increased or decreased by the host
to achieve a page weighted more toward white or toward
black, respectively.
4. Access codes F1 and 71 represent limits on acceptable zero crossing for use by the carrier recovery
loop. The carrier recovery loop uses several nonlinear controls in attempting to lock the zero crossing
of the local carrier to those of the transmitter. Since
Group 2 facsimile uses VSB transmisSion, it is necessary to either reconstruct the upper sideband or exclude those zero crossings that represent
frequencies other than 2100 Hz. The modem excludes unwanted zero crossings by testing the effective slope of the waveform as it crosses zero. In
Figure 3, points A and B represent samples taken
about a zero crossing over a sample period T, where
T = 1/10,368 seconds.
A
o----~----~~-------B
T
Figure 3. Samples of Zero Crossing
5-10
Application Note
R96FI/R96MD Modem
0
~
,
a.
...w
1
I
::E
III
C
0
~
~
a:
~
/
II
--" ~
...
~
o
o
o
"'
g
g
.
M
o
o
o
N
HEX VALUE WRITTEN USING ACCESS CODE AA
Figure 2. AGe Slew Gain
5-11
1
CJ
<
w
:::;
N
iii
~
...<
0
...
w
en
<
LL
g
LL
C
Z
./
~
0
.2
./
~
~
"'"'I
I
L.-
V
B
::E
o
o
o
•
Application Note
'1'
DTMF Dialing Using the
R96MD Modem
Rockwell
frequency power and -1 dBm of steady state low frequency power in order to meet all of the listed conditions. Since
+0.5 dBm is the maximum undistorted power level for individual tones generated by the modem, the user may
need to add gain in front of the DAA during DTMF dialing.
INTRODUCTION
The R96MD modem includes tunable oscillators that can
be used to perform dual-tone multi-frequency (DTMF) dialing. The frequency and amplitude of each oscillator output
is under host control. A programmable tone detector can
also be usecYIn e&1I establishment to recognize an answer
tone.
The required duration of the DTMF pulse is 50 ms minimum. By experience, a pulse duration of approximately
95 ms is more reliable. The required interval between
DTMF pulses is 45 ms minimum and 3 seconds maximum.
Again, by experience, an interdigit delay of approximately
70 ms is preferred.
This application note describes the method of oscillator
and filter tuning by the host processor and provides an example of an autodialer routine that may be programmed
into the host.
The remaining requirements of RS-496, relative to DTMF
dialing, are not influenced by the host processor. These requirements are all met by the modem's oscillators.
DTMF REQUIREMENTS
EIA Standard RS-496, paragraph 4.3.2, specifies requirements that ensure proper DTMF signaling through the
public switched telephone network (PSTN). These tones
consist of two sinusoidal signals, one from a high group of
three frequencies and one from a low group of four frequencies, that represent each of the standard pushbutton
telephone characters shown in Table 1.
SETTING OSCILLATOR PARAMETERS
The oscillator frequency and output power are set by the
host computer in DSP RAM using the microprocessor bus
and diagnostic data routine. For a description of the
microprocessor bus and other interface considerations,
refer to the R96MD modem data sheet (Order Number
MD34).
Table 1. DTMF Signals
Low
1209 Hz
High Frequenc
1336 Hz
1417 Hz
697 Hz
1
2
3
770 Hz
4
5
6
852 Hz
.
8
9
0
#
Frequency
941 Hz
7
When setting the frequency of tone 1, the host must write
a 16-bit hexadecimal number into RAM using RAM access
code 71 with bit RAE = 1. When setting the frequency of
tone 2, a 16-bit hexadecimal number must be written into
RAM using RAM access code 71 with bit RAE = O. The
power levels of tone 1 and tone 2 are set by writing i6-bit
hexadecimal numbers into RAM using RAM access code
72 with bit RAE 1, and with RAE 0, respectively. The
hexadecimal numbers written into these RAM locations
are scaled as follows:
=
Signal power is defined for the com bined tones as well as
for the individual tones. Both maximum and minimum
power requirements are functions of loop current. By combining the various requirements of RS-496, compromise
power levels can be determined that meet the power
specifiCation for all U.S. lines (when driving the PSTN from
a 600 ohm resistive source). The high frequency tone
should be at a higher power level than the low frequency
tone by approximately 2 dB. The maximum combined
power, averaged over the pulse duration, should not exceev + 1 dBm. The minim um steady state power ofthe high
fr~ency tone should not be less than -8 dBm. When
connecting the modem circuit to the PSTN by means of a
data access arrangement (DAA) set for permissive mode,
the DAA gain is -9 dB. The modem circuit must, therefore,drive the DAA input with +1 dBm of steady state high
Document No. 29300N16
=
Frequency number = 6.8267 (desired frequency in Hz)
Power number = 15360 [10(Po/20)j
Where Po = output power in dBm with a series 600
ohm resistor into a 600 ohm load.
These decimal numbers must be converted to
hexadecimal form then stored in RAM by following the
RAM data write routine illustrated by Figure 1. Hex 3FFF
is the maximum value of Power level number without harmonic distortion.
Application Note
5-12
Order No. 816
Rev. 1, September 1988
Application Note
DTMF Dialing Using the R96MD Modem
STORE RELEVANT ACCESS CODE
IN RAM ACCESS S (0:F:0-7)
OF INTERFACE MEMORY
DATA (MSB) -
RAM DATA YSM (0:1:0-7)
DATA (LSB) -
RAM DATA YSL (0:0:0-7)
CHANGE RAM ACCESS S (O:F:o-7)
NOTE: TO ASSURE CORRECT OPERATION, MAXIMUM
ALLOWABLE TIME FROM MDAO = 1 TO WRITING DATA INTO
RAM DATA YSM AND RAM DATA YSLIS 80 MICROSEC.
Figure 1. RAM Data Write Routine
5-13
•
DTMF Dialing Using the R96MD Modem
Application Note
Hexadecimal numbers for DTMF generation are listed in
Table 2. Power levels are selected to give the desired output power for each tone (0 dBm for the high frequency tone
and -2 dBm for the low frequency tone) while compensating for modem filter characteristics.
DETECTING ANSWER TONE
Frequency detector bit FR1 (1 :B:5) can be used to detect
a 2100 Hz answer tone when connection to the remote
modem is successful. Bit FR1 goes active (one) when
energy above the turn-on threshold is present at 2100 Hz
±25 Hz. At the end of the answer tone, FR1 returns to zero
and data transmission can begin.
Table 2. DTMF Parameters
Digit
0
1
2
3
4
5
6
7
8
9
RAM Access S
RAE
Value (Hex)
71
71
72
72
1
0
1
0
1918
23AO
326E
3F6E
71
71
72
1
0
1
0
1296
2030
32F1
3FFF
71
71
72
72
1
0
1
0
1296
23AO
32F1
3F6E
71
71
72
72
1
0
1
0
1296
2763
32F1
3F6C
71
71
72
72
1
0
1
0
1488
2030
3327
3FFF
71
71
72
72
1
0
1
0
1488
23AO
3327
3F6E
71
71
72
72
1
0
1
0
1488
2763
3327
3F6C
71
71
72
72
1
0
1
0
1668
2030
3306
3FFF
71
71
72
72
1
0
1
0
1668
23AO
3306
3F6E
71
71
72
72
1
0
1
0
1668
2763
3306
3F6C
72
COMPLETE CALLING SEQUENCE
A complete calling sequence consists of several steps including modem configuration, telephone number selection, DTMF transmission, and answer tone detection. A
sample flow chart for implementing an auto-dialer in host
software is illustrated in Figure 2.
The auto-dialer routine may be entered at one of two
points; either AUTO DIAL or REDIAL. When entering at
AUTO DIAL, the host prompts the user to enter a phone
number, which is then stored in the phone number buffer.
When entering at REDIAL, the routine dials the number
previously stored in the phone number buffer and does not
issue a user prompt.
Interrupts not required during dialing are disabled to
prevent errors in real time delays. Interrupt status is saved
to allow restoring these interrupts when dialing is complete. The current modem configuration is saved prior to
selecting the DTMF Transmit configuration, then restored
at the completion of the auto-dialer routine to allow data
transfer.
The commands for off-hook and request coupler cut
through are typical of signals required by data access arrangements that may be connected to the modem for
switched network operation.
Since the number to be dialed varies in length depending
on the requirements of various PBX equipment, domestic
telephone companies, and foreign PTTs, the number buffer must allow for numbers of different length. The method
used in Figure 2 to determine the end of valid bytes in the
buffer is zero recognition. After the last digit is entered, the
carriage return must place a hexadecimal 00 (ASCII NUL
character) in the buffer. All other bytes must be non-NUL
ASCII characters. Only numeric characters (ASCII 30
through 39) are printed and dialed. Non-numeric characters are tested for comma and NUL. Comma causes a 2second pause in dialing to allow for known delays in the
telephone network or PBX. NUL ends the dialing portion of
the routine and begins the answer tone detection portion.
All other characters are ignored.
5-14
Application Note
DTMF Dialing Using the R96MD Modem
REQUEST PHONE NUMBER
FROM INPUT DEVICE
AND LOAD NUMBER BUFFER
GO TO REDIAL ROUTINE
SAVE INTERRUPT STATUS
AND DISABLE INTERRUPTS
SAVE MODEM'S CURRENT CONFIGURATION
AND SELECT DTMF TRANSMIT CONFIGURATION
SET DATA ACCESS ARRANGEMENT
(DAA) TO OFF·HOOK
REQUEST COUPLER CUT
THROUGH FROM DAA
START 3 SECOND TIMER
N
PRINT "NO COUPLER CUT THROUGH"
AND SET DAA TO ON·HOOK
PRINT "DIALING"
FIgure 2. Autodialer Flow Chart
5-15
•
Application Note
DTMF Dialing Using the R96MD Modem
SELECT ONE SET OF FOUR
COEFFICIENTS FROM TABLE 2
BASED ON VALUE OF BYTE
STORE FOUR COEFFICIENTS
IN RAM USING RAM WRITE
ROUTINE OF FIGURE 1
Figure 2. Autodialer Flow Chart (Cont'd)
5-16
Application Note
DTMF Dialing Using the R96MD Modem
N
•
Figure 2. Autodialer Flow Chart (Cont'd)
5-17
Applicati.on Note.
DTMF Dialing Using the R96MD Modem
The answer tone detection logic allows 30 seconds for
2100 Hz recognition. If answer tone is not recognized
within this time limit, the call is aborted. If answer tone is
recognized, the routine jumps to the data handling
software.
Table 3. 2100 Hz Answer Tone Parameters
SINGLE TONE GENERATION
I n OEM equipment that combines the features of a modem
with those of a telephone handset, the tone genefators
may be used to generate a caller reassurance tone (or
even music) while the caller is kept on hold. To generate
a single tone, set one of the oscillators to zero frequency
or zero amplitude while the other oscillator is keyed on by
the RTS bit. This technique is also applicable for generating a 2100 Hz answer tone when the modem is used to
automatically answer a call. The parameters for 2100 Hz
answer tone generation are listed in Table 3.
5-18
Frequency
RAMAccessS
RAE
Value
2100Hz
71
71
72
72
1
0
1
0
3800
0000
5FFF
5FFF
Application Note
'1'
DTMF Dialing Using the R24MFX, R24BKJ,
R48M FX, or R48PCJ Modem
Rockwell
INTRODUCTION
power and -1 dBm of steady state iow frequency power in
order to meet all of the listed conditions.
The R24MFX, R24BKJ, R48MFX, and R4BPCJ modems
include tunable oscillators that can be used to perform
dual-tone multi-frequency (DTMF) dialing. The frequency
and amplitude of each oscillator output is under host control. A programmable tone detector can also be used in
call establishment to recognize an answer tone.
The required duration of the DTMF pulse is 50 ms minimum. By experience, a pulse duration of approximately
95 ms is more reliable. The required interval between
DTMF pulses is 45 ms minimum and 3 seconds maximum.
Again by experience, an Interdiglt deiay of approximately
70 ms is preferred.
This application note describes the method of oscillator
and filter tuning by the host processor and provides an
example of an auto-dialer routine that may be programmed into the host.
The remaining requirements of RS-496, relative to DTMF
dialing, are not influenced by the host processor. These
requirements are all met by the modem's oscillators.
DTMF REQUIREMENTS
SETTING OSCILLATOR PARAMETERS
EIA Standard RS-496, paragraph 4.3.2, specifies requirements that ensure proper DTMF signaling through the
public switched telephone network (PSTN). These tones
consist of two sinusoidal Signals, one from a high group
of three frequencies and one from a low group of four frequencies, that represent each of the standard pushbutton
telephone characters shown in Table 1.
The oscillator frequency and output power are set by the
host computer using the microprocessor bus and diagnostic data routine. For a description of the microprocessor
bus and other Interface considerations, refer to the
R24/4BMEB modem evaluation board data sheet and the
relevant modem data sheet listed in Table 2.
Table 1
~
Table 2.
DTMF Signals
requancy
1208 Hz
1338 Hz
1477 Hz
:;:uency
697 Hz
770 Hz
1
2
3
4
5
652 Hz
7
.
8
0
6
9
941 Hz
Data Sheet Order Numbers
Tille
Order Number
R24/48MEB Data Sheet
R24MFX Data Sheet
R24BKJ Data Sheet
R48MFX Data Sheet
R48PCJ Data Sheet
MD22
MD17
MD20
MD19
MD21
When setting the frequency of tone 1, the host must write
a 16-bit hexadecimal number into RAM using RAMA code
BE. When setting the frequency of tone 2, a 16-bit hexadecimal number must be written into RAM using RAMA
code BF. The power levels of tone 1 and tone 2 are set by
writing 16-bit hexadecimal numbers into RAM using
RAMA codes 44 and 45, respectively. The hexadecimal
numbers written into these RAM locations are scaled as
follows:
#
Signal power is defined for the combined tones as well as
for the individual tones. Both maximum and minimum
power requirements are functions of loop current. By combining the various requirements of RS-496, compromise
power levels can be determined that meet the power specification for all U.S. lines (when driving the PSTN from a
600 ohm resistive source). The high frequency tone should
be at a higher power level than the low frequency tone by
approximately 2 dB. The maximum combined power, averaged over the puise duration, should not exceed + 1 dBm.
The minimum steady state power of the high frequency
tone should not be less than -B dBm. When connecting
the modem circuit to the PSTN by means of a data access
arrangement (DAA) set for permissive mode, the DAA gain
is -9 dB. The modem circuit must, therefore, drive the
DAA input with + 1 dBm of steady state high frequency
R24MFX AND R24BKJ
Frequency number
= 9.1022 (desired frequency in Hz).
R48MFX AND R48PCJ
Frequency number = 6.8267 (desired frequency in Hz).
R24MFX, R24BKJ, R48MFX, AND R48PCJ
Power number = 27573.6 [10IPo/20)]
Document No_ 29300N03
5-19
Order No. 813
Rev.1, January 1989
•
Application Note
DTM F Dialing Using the R24XXX or R48XXX Modem
DETECTING ANSWER TONE
Where Po = output power in dBm with a series 600 ohm
resistor into a 600 ohm load.
The modem tone detect bit, TDET (A:7), can be used to
detect the presence of answer tone when connection to
the remote modem Is successful. Bit TDET goes active
(one) when energy is detected by the associated tone
detect filter. This filter is Illustrated in Figure 2.
These decimal numbers must be converted to hexadecImal form then stored In RAM by following the RAM data
write routine illustrated by Figure 1.
Hexadecimal numbers for DTMF generation on the
R24MFX and R48MFX are listed in Table 3. These numbers
are also suitable for use with the R24BKJ and R48PCJ.
Numbers used for setting the frequency of tone 1 and tone
2 are larger in the 2400 bps products than In the 2400/4800
bps products. This variation is due to the sample rate difference between these modems. Power levels are selected
to give the desired output power for each tone while compensating for modem filter characteristics.
Table 3_
COMPLETE CALLING SEQUENCE
RAMA
R24XXX
R48XXX
0
8E
8F
44
45
2174
2F80
6184
7A80
1918
23AO
6184
7ABO
1
8E
8F
44
45
18C8
2AFC
61E8
7AFC
1296
2030
61E8
7AFC
2
8E
8F
44
45
18C8
2F80
61E8
7A80
1296
23AO
61E8
7A80
3
8E
8F
44
45
18CS
3483
61E8
79E3
1296
2763
61E8
79E3
4
8E
8F
44
45
1860
2AFC
6250
7AFC
1488
2030
6250
7AFC
8E
8F
45
lB60
2F80
6250
7ABO
1488
23AO
6250
7A80
6
8E
8F
44
45
lBBO
3483
6250
79E3
1488
2763
6250
79E3
7
8E
8F
44
45
lE4A
2AFC
621A
7AFC
16B8
2030
621A
7AFC
8E
8F
45
lE4A
2F80
621A
7A80
16B8
23AO
621A
7A80
8E
8F
44
45
lE4A
3483
621A
79E3
18B8
2783
621A
79E3
8
9
44
44
Once TDET turns on, the calling modem knows the call
has been answered. At the end of the answer tone, TDET
returns to zero and data transmission can begin.
DTMF Parameters
Digit
5
A set of eight coefficients determines the filter response.
Table 2 lists the RAM access codes and filter coefficient
values to be written using the RAM Data Write routine of
Figure 1. These values tune the filter to detect 2100 Hz
± 25 Hz.
A complete calling sequence consists of several steps
including modem configuration, telephone number selection, DTMF transmission, and answer tone detection. A
sample flow chart for implementing an auto-dialer In host
software Is illustrated in Figure 3.
The auto-dialer routine may be entered at one of two
points; either AUTO DIAL or REDIAL. When entering at
AUTO DIAL, the host prompts the user to enter a phone
number, which Is then stored in the phone number buffer.
When entering at REDIAL, the routine dials the number
previously stored In the phone number buffer and does not
Issue a user prompt.
Interrupts not required during dialing are disabled to prevent errors in real time delays. Interrupt status Is saved to
allow restoring these interrupts when dialing is complete.
The current modem configuration Is saved prior to selectIng the tone configuration, then restored at the completion of the auto-dialer routine to allow data transfer.
The commands for off-hook and request coupler cut
through are typical of signals required by data access
arrangements that may be connected to the modem for
switched network operation.
Since the number to be dialed varies in length depending
on the requirements of various PBX equipment, domestic
telephone companies, and foreign PTTs, the number
buffer must allow' for numbers of different length. The
method used in Figure 3 to determine the end of valid
bytes In the buffer is zero recognltl,on. After the last digit
is entered, the carriage return must place a hexadecimal
00 (nul character) in the buffer. All other bytes must be
non-zero ASCII characters. Only numeric -characters
(ASCII 30 through 39) are printed and dialed. Non-numeric
characters are tested for comma and nul. Comma causes
a 2-second pause in dialing to allow for known delays In
the telephone network or PBX. Nul ends the dialing portion of the routine and begins the answer tone detection
portion. All other characters are Ignored.
5-20
Application Note
DTMF Dialing Using the R24XXX or R48XXX Modem
START
DATA (MSB) -DDYM (1:0-7)
DATA (LSB) - DDYL (0:0-7)
•
CHANGE RAMA (F:O-7)
Figure 1.
RAM Data Write Routine
5-21
Application Note
DTMF Dialing Using the R24XXX or R48XXX Modem
2
a(l)
2
a'(4)
INPUT--'~""""
~---....
1ST BI·QUAD FILTER
2ND BI.QUAD FILTER
OUTPUT
TO THRESHOLD
COMPARATOR
TDET
=
TDET
= 0 IF OUTPUT <
1 IF OUTPUT;,: 1/8
1/8
ENERGY AVERAGING
NOTE: NUMBERS IN ( ) REFER TO NODE NUMBERS IN TABLE 4.
Figure 2.
Table 4.
Tone Detector Coefficients for 2100 Hz
R24XX
Node
1
2
3
4
5
6
7
8
Coefficient
Name
a
~,
P2
a'
~1
~2
a"
~"
Tone Detector Diagram
tone detector can monitor call progress for dial tone, busy
signal or ringback tone. The detector filter must be
returned to detect different frequencies used in call prog·
ress signaling. Table 5 lists tones for various lines in the
Bell network. These call progress signals vary according
to the telephone networks of each country. For details on
tuning the tone detector for other frequencies, refer to
Application Note Order No. 668. That note refers to the
R96F filters but is also applicable to R24XXX and R48XXX
modems for coefficient calculation. When applying Appli·
cation Note 668 to R24XXX modems, the sample rate used
should be 7200 samples per second rather than 9600 sam·
pies per second.
R48XX
RAMA
Coefficient
Value
RAM A
Coefficient
Value
36
37
38
39
3A
3B
B6
B7
0198
EOF4
COG5
0198
0033
GOG5
0020
7F01
38
39
3A
3B
3G
30
B8
B9
0198
1A4A
COC5
0198
175A
COG5
0022
7FOG
The answer tone detection logic allows 30 seconds for
2100 Hz recognition. If answer tone is not recognized
within this time limit, the call is aborted. If answer tone
is recognized, the routine jumps to the data handling
software.
In OEM equipment that combines the features of a
modem with those of a telephone handset, the tone gener·
ators may be used to generate a caller reassurance tone
(or even music) while the caller is kept on hold. To gener·
ate a single tone, set one of the oscillators to zero fre·
quency or zero amplitude while the other oscillator is
keyed on by the RTSP bit. This technique is also applica·
ble for generating a 2100 Hz answer tone when the modem
is used to automatically answer a call. The parameters for
2100 Hz answer tone generation are listed in Table 6.
ADDED FEATURES
The appl ication of modem tone generation and detection
to DTMF dialing and answer tone recognition can be
extended to include additional features. For example, the
5·22
Application Note
DTMF Dialing Using the R24XXX or R48XXX Modem
REQUEST PHONE NUMBER
FROM INPUT DEVICE
AND lDAD NUMBER BUFFER
GO TO REDIAL ROUTINE
SAVE INTERRUPT STATUS
AND DISABLE INTERRUPTS
SAVE MODEll'S CURRENT CONFIGURATION
AND SELECT TONE CONFIGURATION
SET TONE DETECT FILTER
COEFFICIENTS FOR 2100 Hz
SET DATA ACCESS ARRANGEMENT
(DAA) TO OFF· HOOK
REQUEST COUPLER CUT
THROUGH FROM DAA
3TART 3 SECOND TIMER
N
PRINT "NO COUPLER CUT THROUGH"
AND SET DAA TO ON·HOOK
PRINT "DIALING"
Figure 3. Autodialer Flow Chart
5-23
•
Application Note
DTMF Dialing Using the R24XXX or R48XXX Modem
SELECT ONE SET OF FOUR
COEFFICIENTS FROM TABLE 3
BASED ON VALUE OF BYTE
STORE FOUR COEFFICIENTS
IN RAM USING RAM WRITE
ROUTINE OF FIGURE 1
Figure 3.
Autodialer Flow Chart (Cont'd)
5-24
Application Note
DTMF Dialing Using the R24XXX or R48XXX Modem
(
ANS.DET
)
N
•
Figure 3.
Autodialer Flow Chart (Cont'd)
5-25
DTMF Dialing Using the R24XXX or R48XXX Modem
Application Note
Table 5.
Call Progress Signals
Tone
Frequency (Hz)·
Precision Dial Tone
350
+440
Continuous
Dialing may commence
600
+ 120 or 133. and
Continuous
Dialing may commence
480
+620
05 Sec. On
0.5 Sec. Off
Called line busy
600
+ 120
0.5 Sec. On
0.5 Sec. Off
Called line busy
480
+620
03 Sec. On }
0.2 Sec Off
0.2 Sec. On }
0.3 Sec. Off
0.25 Sec. On }
0.25 Sec. Off
r------
Old Dial Tones
f--------
Use
Interruption Rates
other combinations
F,-'' ""'"'
I -:~...."'.,...
Old Busy
I
Old Reorder
600
+120
I
PreciSion Audible
Ringing
_.
r
~
Old Audible
Ringing
1
I
--
I
Precision Rece!ver
Off·Hook (ROH)
Precision H rgh Tone
Old High Tone
Recorder
2 Sec. On
4 Sec. Off
To calling customer
420
+ 40, and other
2 Sec. On
4 Sec. Off
To calling customer
- - - - - - - - r - - - - - - - - - - - -..-
440
1400
+2060
+2450
+2600
0.3 Sec On
Call waiting service; an
incoming call IS waiting
On and Off 5 Times
To cause off·hook
per Sec
customers to go
on-hook
----
480
Continuous
To cause off-hook
customers to go
On 05 Sec. Every 15
To indicate call is being
recorded by distant
customer
480, 400 or 540
on-hook
1400
Seconds
Connector Tone
I
*A
All local switching paths
busy, all trunks busy, all
paths or trunks busy
440
+480
combinatIOns
Call Waiting
Local
Reorder
Toll
Reorder
Toll
Local
"+" sign indicates eIther superposition (precision tones) or modulation (old tones).
Table 6. 2100 Hz Answer Tone Parameters
Frequency
RAMA
R24XXX
R48XXX
2100 Hz
8E
8F
44
45
4AAA
0000
5FFF
5FFF
3800
0000
5FFF
5FFF
5-26
Application Note
'1'
Rockwell
R96MFX Modem Recommended
Receive Sequence for Group 2 Facsimile
phase-locked-loop characteristics to match
reduced AGC response.
INTRODUCTION
The R96MFX includes a transmit and receive configuration
that Is compatible with the transmission scheme of
Group 2 facsimile equipment. In order to achieve the best
results with Group 2 reception, the following procedure is
recommended. The step numbers are keyed to points in
Figure 1. Refer to Data Sheet MD47 for details on how to
configure the modem and write modem data.
c. Read and save the 16-bit value from registers 3 and
2 using access code 00, CRx = O. This value represents the frequency error term from the Group 2
phase-locked-loop.
d. Verify that phasing signal is still being received. This
action guarantees that AGC value was frozen during
phasing signal.
e. If step d above determines that phasing signal is
present, allow transmission of CFR. If phasing signal is not present, suppress CFR.
3. Exit Group 2 configuration.
4. At completion of CFR transmission, re-enter Group 2
configuration and wait 5 milliseconds to complete initialization. Then:
Figure 1. Group 2 Facsimile Sequence
METHOD
a. Repeat step 1.b.
1. Enter Group 2 configuration and wait 5 milliseconds to
complete initialization. Then:
b. Repeat step 2.a.
c. Add hex 0038 to the value saved in step 2.c above
and write the sum using access code 00, CRx = O.
This action forces a 9 Hz error as in step 1.a.
a. Write hex 0038 using access code 00, CRx = O.
This action sets the Group 2 phase-locked-loop for
a frequency correction of 9 Hz, causing the phase
term to drift rapidly to overcome any tendency to
slow phase recovery.
5. Wait for start of Group 2 message transmission. Then:
a. Write hex 0400 using access code 05, CRx = 1. This
action restores the AGC slew rate to the default
value.
b. Write hex 4000 using access code 19, CRx = 0, and
hex 7FFF using access code 99, CRx = O. This action allows the Group 2 phase locked-loop to accept
the greatest number of samples for carrier recovery
during phasing.
b. After 2 lines, write the value saved in step 2.c using
access code 00 CRx = O. This action removes the
9 Hz forced frequency error without waiting for the
phase-locked-loop to complete the correction. This
step is optional as the correction will eventually be
completed, but, depending on the percentage of
white in the document being sent, the correction
may take from 4 to 6 lines (100 ms of white required).
c. Write hex 2000 using access code 05, CRx = 1. This
action sets the AGC slew rate for very fast acquisition.
d. Select fast AGC state by setting control bit G2FGC
(00:3) to a one.
2. After phasing is detected, wait approximately 2 seconds
for the AGC circuit to settle. Then:
6. After approximately 6 to 10 seconds of message reception, perform either step a or step b below:
a. Write hex 0000 using access code 05, CRx = 1. This
action stops AGC tracking in order to preserve the
present AGC setting.
a. Write hex 6100 using access code 19, CRx = 0 and
hex 0600 using access code 99, CRx = O. This action places narrow limits on the received signal used
for carrier recovery during message reception and
b. Reset control bit G2FGC (00:3) to a zero to select
slow AGC rate. This action changes the Group 2
Document No. 29300N 19
Application Note
5-27
Order No. 819
October 1988
•
R96MFX Modem
Application Note
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Modem with
Error Detection uses the SDLC eight-bit octet format.
1. The Broadcast Address
2. The Null Address
11111111
00000000
CONTROL FIELD
The control field defines the function of the frame. It may
contain a command or response. The control field might
also contain send or/and receive sequence numbers. This
field can be in one of the following formats:
A programmable interface memory interrupt is featured in
the R96EFX. This feature allows the user to select an interrupt to occur on any combination of bits within the interface memory registers.
1. I nformation Transfer Format
2. Supervisory Format
3. Unnumbered Format
HDLCFRAMES
Data and control information on a HDLC link are transmitted via frames. These frames organize the information
into a format specified by an ISO standard that enables the
transm itting and receiving station to synchronize with each
other. This format is shown in Figure 1.
This field is normally 8 bits in length. However, certain
protocols allow for an "extended" control field. For example, it is 16 bits in length for modulo 128 operation of
the LAP and LAPB procedures.
FLAGS
The R96EFX treats the address field, the control field, and
any other transmitted data, except for the flags and the
Frame Check Sequence, as the information field. The information field does not have a set length; however, this
field follows the SDLC protocol in being in the format of
eight bit bytes.
[ FLAG[ ADDR [ CONTROL [
L
INFORMATION FIELD
INFORMATION
FRAME ENDS
FRAME STARTS
_1
ZERO INSERTION
Figure 1. HDLC Frame
Since flags mark the beginning and ending of a frame,
some method must be implemented to inhibit or alter the
transmission of data that appear as flags. The method
used is called "zero insertion". HDLC procedures require
that a zero be transmitted following any succession of five
continuous ones. This includes all data in the address,
control, information and Frame Check Sequence fields.
Use of zero insertion denies any pattern of 01111110 to
ever be transmitted between beginning and ending flags.
All frames start and end with a flag sequence. The beginning flag and the ending flag are defined by the bit pattern
01111110 (7E). The ending flag for one frame can also
serve as the beginning flag for the following frame. If
separate ending and beginning flags are used, the final
zero in the ending flag of one frame may also serve as the
first zero of the beginning flag in the following frame. This
process is known as "zero-sharing". The zero-sharing bit
pattern is 011111101111110.
ZERO DELETION
ADDRESS FIELD
When transmitting flags, zero insertion is disabled. During
reception of data, after testing for flag recognition, the
receiver removes a zero that immediately follows five continuous ones. This is termed "zero deletion". A one that follows five continuous ones signifies either a frame abort
(Le., at least seven ones with no zero insertion) or a flag
(Le., 01111110). The sixth one is, therefore, not removed.
The address field informs the receiver where the information is to go (if the primary station is transmitting) or where
the message originated (if a secondary station is transmitting). This field is eight bits in length for the "basic" format.
Document No. 29800N826
Application Note
5-30
Order No. 826
January 1989
R96EFX HOLe and Programmable Interrupt Features
Application Note
FRAME CHECK SEQUENCE
IMPLEMENTATION
The purpose of the Frame Check Sequence (FCS) is to
give a shorthand representation of the entire transmitted
information field and to compare it to the identically
generated shorthand representation of the received sequence. If any difference occurs, the received frame was
in error and should be re-transmitted.
A representation of the HOLC process is shown in Figure
3. The events are numbered in order of occurrence from
one to four.
1. The beginning flag is transmitted. The receiver
sees the flag and now becomes aligned with the
transmitter. Both the receive and the transmitter
FCS registers are preset to FFFF (hex).
The FCS computation is done on all fields within the frame
but does not include the flags. Cyclic Redundancy Check
(CRC) is the method used. The polynomial is specified in
CCITT T.30 and X.25 as follows:
2. The information field is transmitted. The data is
also run through the FCS register before zero insertion. At the receive end, after the zero deletion
algorithm, the data is presented to the user and
then run through the FCS register.
x 16 + x 12 + x 5 + 1
The polynomial is implemented as shown in Figure 2.
The Frame Check Sequence is sent as two bytes of data
immediately preceding the ending flag of the frame. The
FCS register is first preset to all binary ones. The register
is then modified by shifting in the data (no flags) contained
in the address, control, and information fields. Following
the last bit of data, the ones complement of the FCS
register is transmitted as the 16-bit FCS. The FCS is transmitted with the highest order bit (X1~ first.
3. The FCS is inverted and then transmitted. The
transmitted FCS is passed through the receiver's
FCS register. The shift register will contain
1111000010111000 if the frame has been
received correctly.
4. The ending flag is transmitted.
The signal timing is illustrated in Figure 4.
TRANSMITTER AND RECEIVER IMPLEMENTATION
FRAME ABORTION, FRAME IDLE, AND TIME FILL
In order to use HOLC in the R96EFX, the host processor
must:
Frame abortion prematurely finishes transmission of a
frame. This occurs by sending at least seven consecutive
ones with no zero insertion. This abort pattern terminates
a frame immediately and does not require a FCS or an ending flag.
1. Set up the modem configuration.
2. Set the parallel data mode bit (POM).
3. Set the HOLC mode bit.
An abort pattern followed by a minimum of eight additional consecutive ones idles the data link. Thus, seven to
fourteen ones establish the abort pattern; fifteen or more
ones constitute an idle pattern.
RAM Access 1 (using A001) remains available while RAM
Access 2 (using A002) is unusable in the parallel data
mode. HOLC transmission cannot be performed using the
serial interface.
Interframe time fill is accomplished by transmitting continuous flags without zero-sharing between flags. Therefore, the transmitter must be capable of sending multiple
flags to maintain the active state in the receiver if any time
fill is required.
The format of the data input to the R96EFX is in groups of
eight bit bytes. As in the parallel data mode, the least significant bit of the byte is transmitted first.
MONOFAX IS
a regIstered trademark of Rockwell InternatIOnal
Figure 2. CRC Polynominallnplementation
5-31
•
Application Note
R96EFX HOLe and Programmable Interrupt Features
TRANSMISSION AND RECEPTION RATE
TRANSMITTER AND RECEIVER INITIALIZATION
The HDLC as implemented in the R96EFX runs under the
following transmitter and receiver modes:
The HDLC transmitter and receiver is initialized differently
than other modes upon power-up, reconfiguration, or turning on RTS input or RTSP bit. Table 1 shows the states of
the interface memory bits for HDLC initialization.
V.29, 9600 bps
V.29, 7200 bps
V.29, 4800 bps
V.27, 4800 bps
V.27, 2400 bps
V.21 , 300 bps
Table 1. Transmitter and Receiver Initialization
In addition to the above configurations, the programmable
interrupt runs under the following transmitter and receiver
configurations:
Transm itter
Group 2
Tone Detect
Dual Tone Transmitter
Note: In the high speed modes, any data patterns referred
to in this application note are transmitted scrambled and
received descrambled.
RECEIVING LINK STATION
Receiver
ABIDL=
o (Note 2)
ABIDL=
o (Note 2)
BA2 Not Initialized
1
BA2=
o (Note 1, 2)
CRC=
o (Note 2)
CRC=
o (Note 2)
EOF=
EOF=
o (Note 2)
0
FLAG =
FLAG =
0
o (Note 2)
ZEROC=
ZEROC=
o (Note 2,3
Notes:
1. Not applicable in the transmitter.
2. Zeroed only upon power-up; unchanged elsewhere.
3. Not applicable in the receiver.
END
BEGIN
I
I
TRANSMITTING LINK STATION
r---------,
(1) TRANSMIT FLAGS (4)
r_--------~~------------4_~FLAGr_--------------~
(2) TRANSMIT MESSAGE
GENERATING POLYNOMIAL
PRESET TO ALL 1S
1111000010111000
GENERATING POLYNOMIAL
PRESET TO ALL 1S
INVERT
r-L
(3) TRANSMIT FCS
ZERO DELETE r+_-------------+-l ZERO INSERTf.+-----~
CONTENTS OF SHIFT REGISTER
AT END OF FRAME.
WHEN ENTIRE FRAME TRANSMITTED, FCS
REGISTER CONTAINS REMAINDER OF
MESSAGE POLYNOMIAL
SHIFT REGISTER CONTAINS ABOVE VALUE
AT END OF FRAME IF TRANSMISSION IS
ERROR FREE.
GENERATION POLYNOMIAL
THE QUOTIENT IS DISCARDED.
Figure 3. HDLC Process
5-32
R96EFX HOLe and Programmable Interrupt Features
Application Note
RTSP
8
~
CTSP
~
RX
I
so
SCR1'S
BA'
IRQP
EOF
~~
~
0
ABIDL
=oJ
__________~n~____-=______~n~____~____~nL_______
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0
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___________ _
L -_ _ _ _ _ _ _ _ _ _ _ _
51
OVRN
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~__________________________________~~L__________
FLAG
Transmitter Mode Conlrol
1. Upon setting RTSP, the host should initialize EOF, ABIDL, ZEROC, and OVRUN 10 Ihe desired values.
2. BA2 is forced high 0.7 "" before RX(OD:7) goes low.
3. The host can send multiple flags by either waiting to load data into DBUFF or by doing a diagnostics writa to RAM (see 'Flag
Transmission and Reception' Section). The host can then load the first byte when RX goes low for the first frame or after
setting EOF for subsequent frames.
4. Load the first byte of the next frame after setting EOF.
5. The host sets and resets ABI DL here.
6. A transmit underrun occurs here. The modem sets ABIDL. The host must reset ABIDL.
a. Transmitter
•
SD
IAOP
BA'
0)
CDEr
-.J
EOF
I
CRC
I
ABIOL
I
OVRUN
I
n
n...n..n
n
n
n
L -_ _~~L-_ _ _ _ _ __ _
0
ruI
n
FLAG
Receiver Noles
1. EOF, ABIDL, and OVRUN should be a known value before Ihe data appears on RD.
2. The host resets ABIDL in the middle of receiving an abortlidle sequence.
3. A receive overrun condition has occurred.
4. Jl, J2 are junk Onvalid) data.
5. CRC seta and EOF sets in response to the junk data between flags.
6. ABIDL remains high due to the incoming scrambled 1's turnoff sequence for high speed modes.
b. Receiver
Figure 4. HDLC Signal Timing Diagrams
5-33
o
Application Note
R96EFX HOLe and Programmable Interrupt Features
to load new data into OBUFF, where N is the number of
flags. The host then has seven bit times in which to load
new data and thus prevent another flag from being sent.
For example, if three flags are desired between frames,
the host must wait at least 16 bit times and not more than
23 bit times after FLAG is set by the modem.
FLAG TRANSMISSION AND RECEPTION
The A96EFX transmitter sends at least one flag as the
opening flag of the first frame. As long as the user does not
load the 8-bit transmit data register, OBUFF (register 10),
with data, the modem sends continuous flags with no zerosharing (Le., 0111111001111...). This facilitates transmission of the preamble as specified in T.30. Thus, the
transmitter defaults to transmitting time-fill and, therefore,
keeps the receiving link station active.
To assist the user in transmitting more than one flag between frames or at the end of the final frame, a counter can
be accessed through modem diagnostics. This counter is
decremented directly in the signal processor's RAM. This
means that the number written will only last for one group
of flags. For example, FSK should have at least two beginning flags for the first frame and at least two ending flags
for the final frame. However, frames between these two require only one flag. This is why the counter is decremented
directly and one flag is transmitted as a default. Diagnostics should be setup as shown below:
AOD1=
85
BAh
0
CA1=
1
WATl = 1
As the default condition, the A96EFX receiver continually
searches for the flag data pattern. When one or more flags
are detected, the interface memory status bit FLAG (09:0)
is set. The flags themselves are not presented to the host
through the DBUFF register. Therefore, as soon as a flag
is observed, the modem examines the next byte of
received data. If it is a flag, an abort/idle sequence, or a
FCS, it is not given to the user. Instead, the appropriate
status bits are set or reset.
The A96EFX also has the capability to detect consecutive
flags with zero-sharing.
INFORMATION FIELD TRANSMISSION AND
RECEPTION
For information field transmission, the host should wait for
CTSP (OF:l) to transition high. The host must then load the
data into DBUFF and then wait for the data available bit
BA2 (1 E:3) to be set by the modem before loading in the
next byte of data. If the next byte is not loaded into OBUFF
within the next eight bit times, the modem will set OVAUN
(09:7), indicating an underrun condition has occurred. To
tell the modem that the host wants to end the frame, the
host must set EOF as soon as the modem has taken the
last byte of the frame (BA2 sets). When the modem recognizes EOF being high, the modem will reset EOF and will
transmit the FCS and clOSing flag. Once the host sets
EOF, the host may load in the first byte of data of the next
frame into DBUFF. If the host wants to end transmission,
the host must wait for EOF to return low before turning off
ATS orATSP.
In the receiver, only the information field data between
flags is passed to the user through the DBUFF register by
the use of the handshaking bit BA2. The user must wait for
BA2 to be set by the modem and then take the data. If the
host does not read the data within eight bit times, OVAUN
will set indicating an overrun condition, and the data in
DBUFF will be overwritten by the next byte.
The value to write into YDAM1 and YDAL1 should be 1
less than the number of flags desired. This value can be
written anytime after the AX bit returns to zero and before
FLAG is set by the modem.
Using the FSK example above, assume three flags are to
be transmitted at the beginning of the first frame and at the
end of the final frame.
1. Turn on ATS.
2. Wait until the AX bit is reset by the modem.
3. Disable diagnostics 1 (reset ACC1).
4. Setup diagnostics 1 as above, write 00 into
YDAM1, and write 02 into YDAL1.
5. Enable diagnostics 1 (set ACC1).
6. Wait until BAlis set before resetting WAT1.
7. For the ending flag of the final frame, immediately
after loading in the final byte of data or after setting EOF, again setup diagnostics 1 as above,
write 00 into YDAM 1, and write 02 into YDAL1.
Furthermore, no flags, abort/idle sequence, or FCSs are
given to the user via the DBUFF register. Since these
fields are not presented to the user, there is at least a 16bit time delay in the reception of data when receiving these
fields. This allows the FCS and ending flag, continuous
flags, or the abort/idle sequence to be flushed out of the
internal buffers.
Another method exists for sending extra flags. The host
must simply do nothing since flags are transmitted as the
default condition. In other words, after the final zero in a
flag is transmitted, the modem looks to see if the host has
loaded new data into DBUFF (BA2 is reset). If no new data
is loaded before this time, another flag is sent. Therefore,
if more than one flag is desired, the host must wait N-l
multiples of eight bit times after FLAG is set by the modem
5-34
Application Note
R96EFX HOLe and Programmable Interrupt Features
FCS AND ENDING FLAG TRANSMISSION AND
RECEPTION
reset), the modem sends a beginning flag and then the
data in OBUFF.
The host ends a frame by loading in his last byte of data
into OBUFF, waiting until the modem has taken it (BA2
sets), and then setting EOF. After setting EOF, the host
may load in the first byte of data of the next frame into
OBUFF. When the modem recognizes that the host wants
to end the frame, the modem will reset EOF. To terminate
data transmission, the host may turnoff RTS or RTSP
when the modem resets EOF. After resetting EOF, the
modem will automatically transmit the 16-bit FCS and at
least one flag that signifies the end of the current frame
and, if another frame follows, the beginning of the next
frame.
The R96EFX in HOLC mode not only continually searches
for flags, but also continually searches for an abort/idle sequence. When the receive modem encounters this data
pattern, it sets the abort/idle receive bit ABIOL. It is left up
to the host to reset this bit. However, receiver processing
will continue unaffected by the state of this bit.
The reception of data immediately following the abort/idle
sequence is treated as invalid and is not presented to the
user. Therefore, to re-establish transmitter and receiver
synchronization, the receiver must see at least one flag. At
least one flag and three bytes of data must be received following the abort sequence before any data is given to the
host.
Upon the receipt of an ending flag in the current frame
(which may also be the beginning flag of the next frame),
the modem examines the data in the FCS register and
compares it to the remainder. If the FCS register
remainder is correct, CRC (09:1) is reset. Conversely, if
the remainder is incorrect, the CRC bit is set. This is the
only time CRC is updated (except upon power-up). Following this determination, the modem sets EOF. Thus, once
the modem sets EOF, the host can examine CRC to determine whether or not an erred frame was received. It is left
to the host to reset the EOF bit. If the user does not reset
EOF before the end of the next frame, the host will not get
any indication that the following frame has ended.
UNDERRUN AND OVERRUN CONDITIONS
A bit in the interface memory OVRUN (09:7) is used to indicate to the host processor that a transmit underrun condition has occurred. Ifthe host does not load in a new byte
of data within eight bit times, OVRUN and ABIOL will be
set by the modem and the modem will automatically send
a minimum of eight continuous ones. This abort sequence
will continue until the host resets ABIOL. After the host
resets ABIOL, the modem will finish sending the current
byte of ones and will then send a flag. At the end of sending a flag, if BA2 is reset, the modem will interpret the data
in OBUFF as being the first byte of the next frame. After
uploading this data for the first byte of the frame, the
modem will reset OVRUN. The modem will always reset
OVRUN every time it sets BA2, except upon transmitter
HOLC initialization.
ABORT/IDLE SEQUENCE TRANSMISSION AND
RECEPTION
An abort/idle sequence can be sent by the host setting the
bit ABIOL (09:3) in the interface memory. This stops any
normal frame transmission, as well as continuous flag
transmission, and sends continuous ones. Afterthe setting
of ABI OL is detected, the modem first completes the transmission of the current byte of data. Immediately after this
transmission, the modem sends eight consecutive ones.
After these eight bit times, if ABIOL is still set, eight ones
are sent again. To discontinue this sequence, ABIOL must
be reset. Then, if no new data is loaded into OBUFF, continuous flags are sent. If new data is loaded into OBUFF
(BA2 is reset), the modem sends a beginning flag and then
the data in OBUFF. The modem will also recognize the setting of ABIOL while transmitting the FCS, thereby allowing
the receiver to recognize that the transmitted frame should
be discarded.
In the receiver, the OVRUN bit will inform the host that an
overrun condition occurred. The overrun condition takes
place when the receiver fails to take the byte of data in
OBUFF within eight bit times. The modem will thus overwrite the data in OBUFF and, if the host has not taken the
data (BA2 is not reset), the modem will set OVRUN. To
detect further overrun occurrences, the host must reset
this bit.
TRANSMIT MODE CONTROL
After power-up, reconfiguration, or turning RTS input or
RTSP bit on, the host must wait for CTS output or CTSP
bit to turn on before starting frame transmission.
There are two ways in which the user can signal the
modem to exit current HOLC execution. The first way is by
setting the SETUP bit which tells the modem that a new
configuration is desired. The second way is by turning off
RTS input or by resetting the RTSP bit in the interface
memory. In both cases, the following events will occur:
The R96EFX also has the ability to send continuous zeros.
To accomplish this, ABIOL and ZEROC (09:4) must be set.
The modem completes the transmission of the current
byte and then sends eight consecutive zeros. After this
time, if ABIOL remains set, eight zeros are sent again. To
discontinue this sequence, ABIOL must be reset or, if continuous ones are deSired, ZEROC only must be reset.
However, if no new data is loaded in OBUFF and ABIOL is
reset, continuous flags are sent regardless of the state of
ZEROC. Then, if new data is loaded into OBUFF (BA2 is
1. If exiting after making sure the modem took the
data in OBUFF and then setting EOF, the
modem sends the last byte of data followed by
the 16-bit FCS sequence and a closing flag. The
5-35
•
Application Note
R96EFX HOLe and Programmable Interrupt Features
modem then either goes through the turn-off sequence (if RTS output or RTSP bit is turned off),
or sets up the new configuration (if SETUP is set).
Table 2. Interrupt Register Addresses
Host
Register
Register
ITADRS
ITADRS
Host
2. If exiting during the transmission of an abort
sequence, the modem finishes sending the last
byte of the abort sequence, then either goes
through the turn-off routine or sets up to a new
configuration.
(Hex)
(Hex)
(Hex)
(Hax)
00
00
08
01
02
03
10
01
11
04
02
05
08
03
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
10
1E
1F
INTERRUPT PROCESSING
Since the R96EFX will be used in an interrupt driven system, a very flexible scratch pad interrupt feature is
provided. This feature enables the user to select an interrupt to occur on any combination of bits within an interface
memory register.
07
13
08
04
09
14
05
15
OA
OB
OC
00
OE
OF
Interrupt Bits
The programmable interrupt routine runs at the sample
rate in all transmitter and receiver modes (9600 Hz). The
programmable interrupt request bit, PIREQ (1F:3), is set
by the modem whenever the interrupt condition is true. If
the programmable interrupt enable bit, PIE (1 F:4), is set,
the modem sets the programmable interrupt active bit PIA
(1 F:7). The IRQ output pin then goes low when the PIA bit
is set. The host must reset PIREQ after servicing the interrupt.
An interrupt may occur only within a Single interface
memory register based upon any combination of bits. For
example, the host may select register 08 and generate an
interrupt whenever bits 08:5, 08:6, and 08:7 are set, but
may not select 08:5 and 09:2 to generate an interrupt. The
register is selected by specifying the interrupt address
ITADRS (OA:4 to OA:O) as shown in Table 2.
TRIG
00
01
10
11
12
08
16
07
17
18
09
19
OA
1A
OB
1B
OC
1C
00
10
OE
1E
OF
1F
Table 3. Interrupt oJptlons
De.crlptlon
DC Level Triggered
Positive Edge Triggered
Negative Edge Triggered
Positive or Negative Edge Triggered
AN EXAMPLE IMPLEMENTATION
Refer to R96EFX data sheet (Order No. MD49) for a
description of the bits associated with the HDLC and
Programmable Interrupt functions.
The interrupt bit mask register ITBMSK (OB) selects the
bits to be tested in the interface memory register specified
by ITADRS. For example, if ITBMSK is equal to FF, all the
bits are selected; if ITBMSK is equal to OF, the four least
significant bits are selected.
Transmitter Example
1. Set the modem configuration to the desired speed
for transmitting, enable HDLC, parallel data
mode, and RTSP.
2. Wait until CTSP goes low and returns to a high
level.
3. Place the first byte of data into DBUFF. The
modem transmits a flag followed by this byte of
data.
4. As soon as BA2 is set, load in the next byte of
data. This must occur within eight bit times of BA2
being set.
Operating Modes
There are two operating modes with each mode having
four options. The user may choose to OR the selected bits,
or to AND the selected bits. Whenever any of the selected
bits are set, the OR mode is true, else it is false. The AND
mode is true whenever all the selected bits are set, and
false otherwise. When bit ANDOR (OA:5) is set, the AND
mode is chosen; when it is reset, the OR mode is chosen.
The user has the option to be continuously interrupted
whenever the mode is true (DC triggered), to be interrupted only when the mode transitions from true to false
(negative edge triggered), to be interrupted only when the
mode transitions from false to true (positive edge triggered), orto be interrupted when the mode transitions from
either false to true or true to false (edge triggered). The
host selects one of the options by specifying the TRI G bits
(OA:7 and OA:6) as shown in Table 3.
5. After all information but the last byte is given to the
modem, load in the last byte of data in the frame
as in step 4.
6. To end the frame, the host must load in the last
byte of data into DBUFF, wait for BA2 to be set,
and then set EOF.
7. Repeat steps 3 through 6 for all frames to be transmitted.
5-36
Application Note
R96EFX HOLe and Programmable Interrupt Features
8. When the last byte of the final frame is loaded into
register OBUFF, wait for BA2 to return high. Then
set EOF and wait for EOF to return low before
resetting RTSP. The modem transm its the last
byte followed by the 16-bit FCS and at least one
closing flag, depending upon if diagnostics was
used to write into the flag counter RAM location
as mentioned previously. The modem then goes
through its normal turn-off routine.
3. Wait until the modem has properly configured.
4. Monitor, through interrupts, the EOF, ABIDL, and
BA2 bits in the interface memory.
5. Wait for an interrupt. If it is caused by BA2 being
set, read the data in OBUFF. This indicates that
the first byte of the first frame is ready for host
reading. If the interrupt is caused by EOF being
set, check CRC to determine if the current frame
is in error and reset EOF. If the interrupt is caused
by ABIDL, the modem is receiving the abort/idle
sequence. The current frame that was aborted is
invalid. The R96EFX does not set the CRC bit or
the EOF bit in this case since no FCS checking is
done.
Receiver Example
The steps to perform a typical HOLC reception are:
1. Set the modem configuration to the desired speed
for receiving, enable HOLC, and parallel data
mode.
6. Continue waiting for interrupts and take appropriate
action when the interrupts are received .
2. Perform a dummy read of DBUFF to reset BA2.
•
5-37
Application Note
'1'
Rockwell
R144HD DSP Programming Guide
for the Host Computer
When the host reads or writes register 1:0 or 0:0, the
modem resets the modem data available bit ,O:E:O or 1:E:O
(MOAi), to a zero. When the modem reads or writes
register 0, the modem sets the MDAi bit to a one. If an Interrupt Enable bit, 0:E:2 or 1:E:2 (lEi), is set to a one by the
host and the corresponding MOAi bit is set, the IRQ output
is asserted and the associated Interrupt Active bit, 1:E:7 or
0:E:7 (IAi), is set to a one by the modem.
There are software parameters located in the R144HD
modem digital signal processor (DSP) that can be accessed and altered by the host computer. These
parameters, also referred to as diagnostic data, are accessible via the microprocessor bus. This application note
describes information about the DSP parameters in the following catagories:
1. Diagnostic data accessing and scaling
2. DTMF dialing using the dual tone generation
configuration
The default access codes are 28 for 1:F and 00 for O:F,
which allow the received pOint eye pattern to be presented
serially on EYEX and EYEY, respectively.
3. Tone detector filtertuning
READING FROM DSP RAM
4. Recommended receive sequence for Group 2
When bit 0:5:5 (RAMWS) or bit 1:0:0 (RAMWB) is reset to
a zero, data is transferred from OSP RAM onto the
microprocessor bus through the OSP interface memory.
Each word transferred from OSP RAM to the interface
memory is 32 bits long. The 32 bits are written into interface memory registers 0:3,0:2,0:1 and 0:0, or 1 :3, 1:2, 1:1
and 1:0, in that order. Registers 3 and 2 contain the most
and least significant bytes of XRAM data, respectively,
while registers 1 and 0 contain the most and least significant bytes of YRAM data, respectively.
5. Filter characteristics
Referto the R144HD Data Sheet (Order No. MD33) for additional modem information.
DIAGNOSTIC DATA ACCESSING AND
SCALING
DSP RAM DATA ACCESS
The modem contains 256 words of accessible random access memory (RAM). Each word is 32-bits wide. Because
the modem is optimized for performing complex arithmetic, the RAM words are frequently used for storing complex numbers. Therefore, each word is organized into a
16-bit real part and a 16-bit imaginary part. Each part can
be accessed independently. The portion of the word that
normally holds the real value is referred to as XRAM. The
portion that normally holds the imaginary value is referred
to as YRAM. The contents of XRAM and YRAM may be
read or written by the host processor via the microprocessor interface.
WRITING TO DSP RAM
When set to a one, bit 0:5:5 (RAMWS) or bit 1 :0:0
(RAMWB) causes the modem to transfer data from interface memory to RAM in chip 0 or in chip 1, respectively.
When writing into the RAM, only 16 bits are transferred,
not 32 bits as for a read operation. The 16 bits written in
XRAM or YRAM come from registers 1 and 0, with register
1 being the most significant byte. Selection of XRAM or
YRAM for the destination is by means of the code stored
in the RAM Access B bits of register 1:F for chip 1, or by
means of 0:5:4 (RAE) for chip O. When bit 1 :F:7 or 0:5:4 is
set to a one, the XRAM is selected. When bit 1 :F:7 or 0:5:4
equals zero, YRAM is selected.
The DSP interface memory acts as an intermediary during
these host to DSP RAM data exchanges. The RAM address to be read from or written to is determined by the
contents of register O:F (RAM ACCESS S) or 1:F (RAM
ACCESS B).
NOTE: When writing to registers 1 and 0, the host must
first write to register 1, then to register O.
DSP RAM is accessed at internal locations specified by
OSP RAM addresses (called access codes) written to
OSP interface memory registers O:F and 1:F. The OSP
RAM parameters and their corresponding access codes
are listed in Table 1.
Document No. 29800N25
Application Note
5-38
Order No. 825
January 1989
R144HD Diagnostic Data Scaling
Application Note
Note: To assure correct operation, the maximum allowable
time from MDAi (i = 0 or 1) = 1 to writing data into RAM is
80 microseconds.
Writing to Register 0 resets MDAi to a 0 and starts the write
cycle, which ends by MDAi returning to a 1. The RAM
Write Bit must remain set until the end ofthe cycle. A flowchart showing the RAM Write procedure for Chip 0 is
shown in Figure 1. The RAM Write procedure for Chip 1 is
similar.
DIAGNOSTIC DATA SCALING
Table 2 describes the scaling of the modem diagnostic
data.
Table 1. R144HD Modem Access Codes
Ref.
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Function
Access
Received Signal Samples
40
52
Demodulator Output
Low Pass Filter Output
54
5C
Average Power
AGC Gain Word
3E
Tone 1 Frequency
71
Tone 1 Power Level
72
Tone 2 Frequency
71
Tone 2 Power Level
72
Output Level
7F
Checksum, Chip 0
3F
Checksum, Chip 1
7F
Equalizer Input
40
Equalizer Tap Coefficients
02-27
Unrotated Equalizer Output
74
28
Rotated Equalizer Output (Received Point-Eye Pattern)
Decision Points (ldeaO
68
Error Vector
69
Rotation Angle
00
Frequency Correction
AE
Eye Equaiity Monitor (EQM)
Bl
G2 Baseband Signai
C8
G2 AGC Gain Word
AD
G2 AGC Slew Rate
AA
G2 PLL Frequency Correction
C2
G2 PLL Slew Rate
EF
G2 Black/Whlte Threshold
SA
G2 Phase Umlt
Fl
RAE
Chip
Read
Reg. No.
X
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2,3
0,1, 2,3
0,1, 2,3
2,3
2,3
2,3
2,3
0,1
0, 1
0, 1
0, 1
0,1
0,1, 2,3
0,1, 2,3
0,1, 2,3
0,1, 2,3
0,1, 2,3
0,1, 2,3
0,1
2,3
2,3
2,3
2,3
2,3
2,3
2,3
0,1
2,3
X
X
X
X
1
1
0
0
0
X
RAE = X is don't care since this location should only be read from,and not written to, by the host.
5-39
•
R144HD Diagnostic Data Scaling
Application Note
STORE REI.EVANT ACCESC: CODE
IN RAM ACCESS S (O:F:O·7)
OF INTERFACE MEMORY
DATA (MSB) -
RAM DATA YSM (0:1:0-7)
DATA (LSB) -
RAM DATA YSL (0:0:0-7)
CHANGE RAM ACCESS S (O:F:0-7)
Figure 1. RAM Data Write Routine for DSP Chip 0
5-40
R144HD Diagnostic Data Scaling
Application Note
Table 2. Diagnostic Data Scaling
No.1 - Received Signal Samples = AID Sample Word
Format:
16 bits, signed, twos complement
Equation:
VINT
VEXT
(Volts)= [(NO Sample Wordh6l401S] x (3/256)
=
VINT
+ LOG10-1 [AGe Gain (d8)/20]
VEXT
V1NT SIGNAL
PROCESSOR
IA DEVICE
CHANNEL
AGC WORD
No.2, 3, 13, 15, 16, and 17 - All Baseband Signal Nodes
Format:
32 bits, complex, twos complement
Ideal Baseband Signal Points
Configuration
V.29/9600
Point
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
x
(Hex)
0000
2800
0000
0800
0000
1800
1800
1800
0000
E800
E800
E800
0800
0800
F800
F800
y
(Hex)
2800
0000
0800
0000
1800
1800
0000
E800
E800
E800
0000
1800
0800
F800
F800
0800
V.29/7200
V.29/4800 & V.27/2400
V.27/4800
x
y
(Hex) (Hex)
x
y
(Hex) (Hex)
x
y
(Hex) (Hex)
0000
2400
0000
DCOO
OCOO
OCOO
F400
F400
2400
0000
DCOO
0000
OCOO
F400
F400
OCOO
0000
1COO
0000
E400
1COO
0000
E400
0000
0000
1400
1COO
1400
0000
ECOO
E400
ECOO
1COO
1400
0000
ECOO
E400
ECOO
0000
1400
NOTE: V.33 14400, V.33 12000, TCM9600, and TCM7200 constellations are not Included.
o
o
V.29/9600 BPS
o
o
o
o
0
0
V.2917200 BPS
V.29/4800 BPS and
V.2712400 BPS
5-41
V.27/4800 BPS
•
R144HD Diagnostic Data Scaling
Application Note
Table 2. Diagnostic Data Scaling (Cont'd)
No.4 - Average Power
Format:
Equation:
16 bits, unsigned
Post-AGC Average Power (dBm) = 10 Log [(Average Power Word)16!088916J
Pre-AGC Average Power (dBm) = Post-AGC Average Power -AGC Gain
Typical value:
088916 (corresponding to 0 dBm;
No.5 - AGC Gain
Format:
i6-bits, unsigned
Equation:
AGC Gain (dB) = 50 - [(AGC Gain Word)16!004016 x 0.098J
Range:
OFC016 to 7FFF16 for - 43 dBm Threshold
No.6 and 8 - Tone 1 and Tone 2 Frequency
Format:
16 bits, unsigned
Equation:
N = 6.8267 x (Frequent.)' in Hz)
Convert N to hexadecimal then store in RAM.
No.7 and 9 - Tone 1 and Tone 2 Power Level
Calculate the power of each tone independently. The total power transmitted in tone configuration is the
result of both tone 1 power and tone 2 power.
Format:
16 bits, unsigned
Equation:
Output Number = 15033 [10 (Po/20)J
Where:
Po = output power in dBm with series 600 ohm resistor into a 600 ohm load.
Convert Output Number to hexadecimal and store in RAM.
No. 10 - Output Level
Format:
16-bits, unsigned
Equation:
Output Number = 36765 [10(Po/20)J
Where:
Po = output power in dBm with series 600 ohm resistor into a 600 ohm load.
Convert Output Number to hexadecimal and store in RAM.
No. 11 and 12 - Checksum
ROM checksum number determined by revision level.
Format:
i6-bits, unsigned
Example:
Chip 0
Chip 1
B5410-17:
B5411-16:
Checksum = 69CF
Checksum = 9FF9
5-42
R144HD Diagnostic Data Scaling
Application Note
Table 2. Diagnostic Data Scaling (Cont'd)
No. 14 - Equalizer Taps
No. 14 is a set of RAM locations containing adaptive equalizer tap coefficients.
The equalizer tap access codes can be useful for restoring modem operation after loss of equalization
without requesting a training sequence from the transmitter. Since the equalizer tap coefficients are complex
numbers they require two write operations per tap, one for the real part and one for the imaginary part. When
writing or reading the tap coefficients, follow the table below.
Registers 1:1 and 1:0 hold the most and least significant bytes, respectively, of the 16 bits during a write
operation.
Format:
32 bits, complex, twos complement
Configuration
V.33
Read
Acceas Codes
Number of Equalizer Taps
02-27
02-27
02-11
38
38
16
V.29
V.27
WrHe Access Codes
X Access
82-A7
82-A7
82-91
Y Access
02-27
02-27
02-11
No. 18 - Error Vector
Represents the difference between the received point (P2) and the nearest ideal point (PI).
Format:
32 bits, complex, twos complement
Error Vector Maximum Values
Configuration
Bit Rate
(bps)
V.29
V.29
V.29
V.27
9600
7200
4800
4800
Imaginary Error
Registers1 and 0
Real Error
Registers 3 and 2
Magnitude
v(Re2 + Im~
(Hex)
(Hex)
(Hex)
4000
·iii
::I
"
~
..
'"
..
~
3000
\
1\
2000
\
ii
> 1000
:I:
\
........
01
.1
1
r--..
100
10
Seconds to Stabilize AGC lor -55 DBM to 0 DBM Step
No. 25 - Group 2 PLL Frequency Correction
Format:
16 bits, twos complement
Range:
FCBA16 to 034616 representing :1:140 Hz
Equation:
Frequency correction (Hz)
=Frequency correction number x (0.167)
No. 26 - Group 2 PLL Slew Rate
Represents gain of first order term in phase locked loop. Directly proportional to PLL slew rate
Range:
001016 to 700016 for stable operation
...
No. 27 - Group 2 Black/Whlte Threshold
Format:
16 bits, unsigned
Default value:
780016
Graph Notes:
1. 100 white pixels sent followed by 4 black
pixels sent.
2. Results obtained at 0 dBm, no compromise
equalizers in back-to-back connection.
8!::I
•
6
III
a: 5
I I
I I
W
:.;:IL
~1il4
ii!~3
I
11. ...
oW2
a: C
WUl
!!! ul 1
::I~
ZIL
I
7
8
0
0
7
6
0
0
7
2
0
0
7
0
0
0
6
6
6
6
F
C
A
8
0
0
0
0
0
0
0
0
THRESHOLD VALUE (HEXADECIMAL)
No. 28 - Group 2 Phase Limit
When phase error exceeds this limit, PLL updating is suspended. Once phasing is acquired, the limits may
be narrowed to improve immunity to phase hits.
Format:
16 bits, twos complement
Default value:
500016 representing :1:27.34·
Equation:
Phase Limit =360· x (2100/10366) x [7FFF - (Phase Limit)16:V7FFF
5-45
Application Note
R144HD DTMF Dialing
The remaining requirements of RS-496, relative to DTMF
dialing, are not influenced by the host processor. These requirements are all met by the modem's oscillators.
DTMF DIALING
The R144HD includes tunable oscillators that can be used
to perform dual-tone multi-frequency (DTMF) dialing. The
frequency and amplitude of each oscillator output is under
host control. A programmable tone detector can also be
used in call establishment to recognize an answer tone.
SETTING OSCILLATOR PARAMETERS
The oscillator frequency and output power are set by the
host computer in DSP RAM using the microprocessor bus
and diagnostic data routine.
This section describes the method of oscillator and filter
tuning by the host processor and provides an example of
an autodialer routine that may be programmed in the host.
When setting the frequency of tone 1, the host must write
a 16-bit hexadecimal number into RAM using RAM access
code 71 with bit RAE = 1. When setting the frequency of
tone 2, a 16-bit hexadecimal number must be written into
RAM using RAM access code 71 with bit RAE = O. The
power levels of tone 1 and tone 2 are set by writing 16-bit
hexadecimal numbers into RAM using RAM access code
72 with bit RAE = 1, and with RAE = 0, respectively. The
hexadecimal numbers written into these RAM locations
are scaled as shown for nodes 6 through 9 in Table 2.
DTMF REQUIREMENTS
EIA Standard RS-496, paragraph 4.3.2, specifies requirements that ensure proper DTMF signaling through the
public switched telephone network (PSTN). These tones
consist of two sinusoidal Signals, one from a high group of
three frequencies and one from a low group of four frequencies, that represent each of the standard pushbutton
telephone characters shown in Table 3.
These decimal numbers must be converted to
hexadecimal form then stored in RAM by following the
RAM data write routine illustrated by Figure 1. Hex 3FFF
is the maximum value of power level number without harmonic distortion.
Signal power is defined for the combined tones as well as
for the individual tones. Both maximum and minimum
Table 3. DTMF Signals
Low
Frequency
1209 Hz
Hlllh Fre!luenc~
1336 Hz
1447 Hz
697Hz
1
2
3
770Hz
4
5
6
852Hz
7
8
9
941 Hz
*
0
1#
Hexadecimal numbers for DTMF generation are listed in
Table 4. Power levels are selected to give the desired output power for each tone (0 dBm for the high frequency tone
and -2 dBm for the low frequency tone) while compensating for modem filter characteristics.
DETECTING ANSWER TONE
Frequency detector bit FR1 (1 :B:5) can be used to detect
a 2100 Hz answer tone when connection to the remote
modem is successful. Bit FR1 goes active (one) when
energy above the turn-on threshold is present at 2100Hz
:1:25 Hz. At the end of the answer tone, FR1 returns to zero
and data transmission can begin.
power requirements are functions of loop current. By combining the various requirements of RS-496, compromise
power levels can be determined that meet the power
specification for all U.S. lines (when driving the PSTN from
a 600 ohm resistive source). The high frequency tone
should be at a higher power level than the low frequency
tone by approximately 2 dB. The maximum combined
power, averaged over the pulse duration, should not exceed +1 dBm. The minimum steady state power ofthe high
frequency tone should not be less than -8 dBm. When
connecting the modem circuit to the PSTN by means of a
data access arrangement (DAA) set for permissive mode,
the DAA gain is -9 dB. The modem circuit must, therefore,
drive the DAA input with +1 dBm of steady state high frequency power and -1 dBm of steady state low frequency
power in order to meet all of the .listed conditions.
COMPLETE CALLING SEQUENCE
A complete calling sequence consists of several steps including modem configuration, telephone number selection, DTMF transmission, and answer tone detection. A
sample flow chart for implementing an auto-dialer in host
software is illustrated in Figure 2.
The autO-dialer routine may be entered at one of two
points; either AUTO DIAL or REDIAL. When entering at
AUTO DIAL, the host prompts the user to enter a phone
number, which is then stored in the phone number buffer.
When entering at REDIAL, the routine dials the number
The required duration of the DTMF pulse is 50 ms minimum. By experience, a pulse duration of approximately 95
ms is more reliable. The required interval between DTMF
pulses is 45 ms minimum and 3 seconds maximum. Again,
by experience, an interdigit delay of approximately 70 ms
is preferred.
previously stored in the phone number buffer and does not
issue a user prompt.
5-46
R144HD DTMF Dialing
Application Note
Table 4. DTMF
Digit
0
1
2
3
4
5
6
7
8
9
RAMAcceasS
71
71
72
72
#
1
0
1
0
0
72
0
71
71
72
72
1
1
1
0
1
0
1
0
1
0
71
71
72
0
72
0
71
71
72
72
71
71
72
72
71
71
72
72
71
71
72
72
71
71
72
72
71
71
*
Parameter.
RAE Value (Hex)
71
71
72
71
71
72
72
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
72
1
72
0
71
71
72
72
Interrupts not required during dialing are disabled to
prevent errors in real time delays. Interrupt status is saved
to allow restoring these interrupts when dialing is complete. The current modem configuration is saved prior to
selecting the DTMF Transmit configuration, then restored
at the completion of the auto-dialer routine to allow data
transfer.
1
0
1
0
1918
23AO
2046
3900
The commands for off-hook and request coupler cut
through are typical of signals required by data access arrangements that may be connected to the modem for
switched network operation.
1296
2030
2046
3900
Since the number to be dialed varies in length depending
on the requirements of various PBX equipment, domestic
telephone companies, and foreign PTTs, the number buffer must allow for numbers of different length. The method
used in Figure 2 to determine the end of valid bytes in the
buffer is zero recognition. After the last digit is entered, the
carriage return must place a hexadecimal 00 (ASCII NUL
character) in the buffer. All other bytes must be non-NUL
ASCII characters. Only numeric characters (ASCII 30
through 39) are printed and dialed. Non-numeric characters are tested for comma and NUL. Comma causes a 2second pause in dialing to allow for known delays in the
telephone network or PBX. NUL ends the dialing portion of
the routine and begins the answer tone detection portion.
All other characters are ignored.
1296
23AO
2046
3900
1296
2763
2046
3900
1488
2030
2046
3900
1488
23AO
2046
3900
The answer tone detection logic allows 30 seconds for
2100 Hz recognition. If answer tone is not recognized
within this time limit, the call is aborted. If answer tone is
recognized, the routine jumps to the data handling
software.
1488
2763
2046
3900
1688
2030
2046
3900
1688
23AO
2046
3900
1688
2763
2046
3900
1918
2030
2046
3900
1918
2763
2046
3900
5-47
•
R144HD DTMF Dialing
Application Note
REQUEST PHONE NUMBER
FROM INPUT DEVICE
AND LOAD NUMBER BUFFER
GO TO REDIAL ROUTINE
SAVE INTERRUPT STATUS
AND DISABLE INTERRUPTS
SAVE MODEM'S CURRENT CONFIGURATION
AND SELECT DTMF TRANSMIT CONFIGURATION
SET DATA ACCESS ARRANGEMENT
(DAA) TO OFF·HOOK
REQUEST COUPLER CUT
THROUGH FROM DAA
START 3 SECOND TIMER
N
N
PRINT "NO COUPLER CUT THROUGH"
AND SET DAA TO ON·HOOK
PRINT "DIALING"
Figure 2. Autodialer Flow Chart
5-48
R144HD DTMF Dialing
Application Note
SELECT ONE SET OF FOUR
COEFFICIENTS FROM TABLE 2
BASED ON VAlliE OF BYTE
N
STORE FOUR COEFFICIENTS
IN RAM USING RAM WRITE
ROUTINE OF FIGURE 1
FIgure 2. Autodialer Flow Chart (Cont'd)
5-49
•
Application Note
R144HD DTMF Dialing
N
Figure 2. Autodialer Flow Chart (Cont'd)
5-50
R144HD DTMF Dialing
Application Note
ADDED FEATURES
Single Tone Generation
The application of modem tone generation and detection
to DTMF dialing and answer tone recognition can be extended to include additional features.
In OEM equipmentthat combines the features of a modem
with those of a telephone handset, the tone generators
may be used to generate a caller reassurance tone (or
even music) while the caller is kept on hold. To generate
a single tone, set one of the oscillators to zero frequency
or zero amplitude while the other oscillator is keyed on by
the RTS bit. This technique is also applicable for generating a 2100 Hz answer tone when the modem is used to
automatically answer a call. The parameters for 2100 Hz
answer tone generation are listed in Table 6.
Call Progress Monitoring
The tone detector can monitor call progress for dial tone,
busy signal or ringback tone. The detector filter must be
retuned to detect different frequencies used in call
progress signaling. Table 5 lists tones for various lines in
the Bell network. These call progress signals vary according to the telephone networks of each country.
Table 6. 2100 Hz Answer Tone Parameters
Frequency
RAM Access S
RAE
Value
2100 Hz
71
71
72
72
1
0
3800
0000
1
3456
0
0000
Table 5. Call Progress Signals
Tone
Frequency (Hz)"
Precision Dial Tone
350
+440
Continuous
Dialing may commence
Old Dial Tones
600
+ 120 or 133, and
other combinations
Continuous
Dialing may commence
Precision Busy
480
+620
0.5 Sec. On
05 Sec. Off
Called line busy
Old Busy
600
+ 120
0.5 Sec. On
0.5 Sec. Off
Called line busy
Precision Reorder
480
+620
Old Reorder
600
+ 120
0.3 Sec. On }
0.2 Sec. Off
02 Sec. On }
0.3 Sec Off
25 Sec On }
25 Sec Off
Precision Audible
Ringing
Old Audible
Ringing
Call Waiting
Precision Receiver
Off-Hook (ROH)
Precision High Tone
Old High Tone
Recorder
Connector Tone
Interruption Rates
}
o
o
Local
Reorder
Toll
Reorder
Toll
Local
Use
All local switching paths
busy, all trunks busy, all
paths or trunks busy
440
+480
2 Sec. On
4 Sec. Off
To calling customer
420
+ 40, and other
combinations
2 Sec. On
4 Sec. Off
To calling customer
0.3 Sec. On
Call waiting service; an
incoming call IS waltmg
On and Off 5 Times
per Sec
To cause off-hook
customers to go
on-hook
Continuous
To cause off-hook
customers to go
on-hook
On 0 5 Sec Every 15
Seconds
To indicate call is being
recorded by distant
customer
440
1400
+2060
+2450
+2600
480
480, 400 or 540
1400
• A "+ " sign indicates either superposition (precision tones) or modulation (old tones).
5-51
•
R144HD Tone Detector Filter Tuning
Application Note
H3(Z)
TONE DETECTOR FILTER TUN'ING
The R144HD modem includes three Independent tone
detectors (F1, F2, and F3). These tone detectors are
operational when the modem is configured for V.21 FSK,
and are centered, upon power-up, to 2100 Hz (F1),
1100Hz (F2), and 462 Hz (F3). This section presents a
method of tuning these detectors to any desired frequency in the 400 Hz - 3 kHz band.
Filters 1 and 2 have a typical frequency response as
shown in Figure 4. When cascaded, they form a bandpass
filter with a narrow bandwidth as shown in Figure 5.
Given the transfer functions Hl (Z) and H2(Z), an analytical
method is required to compute their coefficients for any
desired frequency in the 300 Hz - 3 kHz band. First, consider Hl (Z). This transfer function can be rewritten as:
COMPUTAnON OF TONE DETECTOR
COEFFICIENTS
Hl (Z)
Filter 1 has a transfer function:
2a
(Eq.2)
a'(4)
2
-
2az2
z2 _ 2Pl Z-2P2
a"(7)
~-c)()-o{
)----p_o_OUTPUT
TO THRESHOLD
COMPARATOR
Fn
Fn
1ST BI-QUAD FILTER
(Eq. 4)
These poles lie on a circle of radius 0.994030884 on the
Z-plane. The radius of the tone detector circle was chosen
so that each filter has a high Q without being unstable Q.e.,
poles must lie inside the unit circle for stability). Figure 4
shows a Z-plane pole-zero diagram for an arbitrary conjugate pole pair on the tone detector circle. The angle a =
360· x fOifs. where fo is the desired center frequency and
fs is the sampling rate (fs = 9600 Hz). The following equations are derived from the angle and magnitude of the pasl-
The energy averaging filter has a transfer function:
a"
2
=
which has a conjugate pair of poles:
Pl =Pl + j v'(P1 2 + 2P2)
and
P2 = Pl - j v'(P1 2 + 2P2)
Each tone detector consists of two second-order filters in
cascade, an energy averaging filter and a threshold comparator. A diagram of a tone detector is shown In Figure 3.
a(l)
(Eq.3)
The output of the energy averager is fed to a threshold
comparator which sets or resets the appropriate bit in interface memory (FR1, FR2, or FR3) if the energy output is
equal to or greater than 1/8, or less than 1/8, respectively.
NOTE: F1, F2 and F3 should not be used as dual
tone detectors (I.e., during call progress tone
detection). Detecting one of the two tones is
the preferred method for call progress
monitoring.
Filter 2 has a transfer function:
2a'
H2(Z) = 1 _ 2P'lZ -1 _ 2P'2Z -2
=
2ND
BI-QUAD FILTER
NOTE: NUMBERS IN ( ) REFER TO NODE NUMBERS IN TABLE 7.
Figure 3. R144HD Tone Detector Diagram
5-52
=1 IF OUTPUT it 118
=0
IF OUTPUT
ENERGY AVERAGING
< 1/8
R144HD Tone Detector Filter Tuning
Application Note
tion vector pointing to a pole pair located at the desired
angle:
cos- 1(1I1/r) = 9 = 360· x folfs
The values for the coefficients a and u' that set IH(fo) I =
o dB in equations 1 and 2 were measured and plotted versus center frequency fo as shown in Figure 8. Three equations corresponding to three linear approxim ations result:
(Eq. 5)
v(fl1 2 + (-111 2 - 2112)]= r = 0.994030884 (Eq. 6)
solving for III and
,
u = u =
1\2:
III = r cos (360· x folfS)
112 = - (2/2
400 s fo s 1100 Hz
(Eq.7)
,
(Eq.8)
(Eq. 9)
(Eq. 10)
(Eq. 12b)
(4/45) fo + 221
32767
1650 s fo s 3000 Hz
(Eq. 12c)
ENERGY AVERAGING FILTER
The coefficients of the energy averaging filter are determined by a Z-domain approximation to an RC circuit of
transfer function H(S) = 1/1 + ST:
1
From Equation 8, we see that:
112 = 11'2 = - (2/2 = -0.494048699
Rewriting Equation 7 in terms of the offsets fA and fA we
obtain:
III = r cos [360· (fo - fA)/fs]
32767
1100sfo s 1650 Hz
a = a'=
(Eq.12a)
(44/275)fo + 104
u = u =
In deriving these equations, only Hl (Z) was considered.
However, the tone detector consists of two identical filters
in cascade. Referring to Figure 5, shifting filter 1 and filter
2 above and below the desired center frequency, a
response with the desired bandwidth is achieved. Furthermore, since a controls the amplitude response, one may
set a = a' to uniformly raise or lower the overall cascade
response.
11'1 = r cos [360· (fo + fA)/fS]
(104/319)[0 -78.62
32767
a" =
1 + 9600.
(Eq. 13)
1
13"=
(1 + 1/9600.)
(Eq. 14)
Upon power-up, u" and W' are set for T = 0.1 seconds. Unless different tone detector response times are required,
these coefficients need not be changed.
The frequency offset is approximately 72% of B/2 (half the
bandwidth):
fA .. 0.72 (B/2)
(Eq. 11)
FILTER COEFFICIENTS
The value of fA should be equal to fA. However, fA may
be chosen 1% smaller than fA to compensate for the fact
that the overall cascade response is not prefectly symmetrical (see Figure 7).
Table 6 contains the computed values of the filter coeffiCients, including those of default frequencies 462 Hz,
1100 Hz, and 2100 Hz. The value 32767 (Hex 7FFF) is full
scale in the SP's machine units (i.e., 32767 = unity). Coefficients may range from -1 to +1 (FFFFto 7FFF in machine
units).
NOTE: Default coefficents are loaded into the DSP RAM
each time the modem enters into Tone Detection mode
(V.21 FSK Receiving mode). The procedure to load new
coefficients after entering Tone Detection mode is:
1. Wait for the SETUP bit to be reset.
2. Wait a minimum of 1 ms.
3. Write new coefficients into DSP RAM.
The host should set the SETUP bit when changing from
FSK transmitting mode to Tone Detection mode, as well
as when reconfiguring the modem.
5-53
•
R144HD Tone Detect.or Filter Tuning
Application Note
2000
3000
3500
FREQUENCY (Hz)
Figure 4. Typical Single Filter Response
500
2000
3000
FREQUENCY (Hz)
Figure 5. Typical Cascade Filter Response
5-54
3500
Application Note
R144HD Tone Detector Filter Tuning
1m Z
90 0
UNIT CIRCLE r = 1
2400 Hz
+j1
'"
TONE DETECTOR
CIRCLE r = 0.994030884
180 0
4800 Hz
360 0
-1
9600 Hz
\
DOUBLE
ZERO
\
\
\
\
,
" .... ......
-
•
-j1
270 0
Re Z
7200 Hz
Figure 6. Z-Plane Pole-Zero Diagram
5-55
R144HD Tone Detector Filter Tuning
Application Note
I
1
,
I /
I '
V'
/
/1
/
/
/
""
,/
"
fo - fA
fo
fo + fA
FREQUENCY (Hz)
Figure 7. Bandwidth and Offset Frequencies
EQ.12b',.
Y
500
./
./
450
./
400
./
./
350
...
...
CD
300
'"
C')
x
180
SEQUENTIAL
CLOCK
(SCLK)
XXX---------II-\ ______1
NS~
HOLD> 0
Sequential Counter Reset Setup and Hold Timing
~
~(TSL)-340
/
NS MAX
_I
WV________ - - - - - W'J/
r..HA
_
OLD DATA
NEW DATA ....
OUTPUTS ________________~~~~~____________________L~~~~__________________________
NOTE: RANDOM WRITE ALWAYS AFFECTS RANDOM READ OUTPUTS; SEQUENTIAL WRITE ALWAYS AFFECTS SEQUENTIAL
READ OUTPUTS. EITHER WRITE WILL AFFECT THE OPPOSITE READ OUTPUT, IF, AND ONLY IF, THE RANDOM
ADDRESS AND SEQUENTIAL ADDRESS ARE EQUAL.
Read Outputs at Same Location as Write (All Other Inputs Stable)
6-4
R8040
T-1 Tri-Port Memory
~~':SEL = 1):..Jn....
WIDTH> 220 NS
~
..) \ \ \ WIDTH> 220 NS
"I
SETUP> 300 NS
::~~~T--WV
--j
I
~
(WSEL)
lIJOIl//7I//
I--
HOLD> 0
fN'L
~
------------
1
l---I
--I f-~~::L=O) ____~)(X)(~~I~_______________~~~I~~-~-----------_-_-_-___I----J
--j I-SETUP> 280 NS
HOLD> 0
SETUP> 250 NS
WRITE DATE
(A-H)
--------
HOLD> 0
- - - - - - - -'fti
I
WE
I
I--
SETUP
~ HOLD
> 150 NS
I > 100 NS
xxx- -----I
f---
--.-;j'--------
--------------.~- WIDTH
~ > 170 NS ---l
Write Setup and Hold Timing
RANDOM
ADDRESS
(R01-R32) ___
X
I..
X
~~N~SHOLD --i r-
J..pl- - - - - - - - - - - - - - - - - - - - - - - - - - . L 7 ' 1'-----
~~~~~
-I
xxx- -'- ---------XXX
xxx--
(TRA) 380 NS MAX.
(RA-RH) DATA _ _-J._..lL..lI.,.;I--_ _ _ _ _ _ _ _ _-'-_..l£..:\L....l._ _ _ _ _ _ _ _ _ _ _-'-_-"'-l£.....l____
Random Read (RRE = 0, WE = 1)
~~~~~NTIAL
(SCLK)
--1
\\\-----
-\~\
t-.....- - - - - (TSA) 430 NS
~~~~~~T~~~A
(SA-SH)
j
1
20 NS
MIN. HOLD
MAX.~
xxx- -------------'lfX
-
.....II I--
--I
I
JX>(- -
-
Sequential Read (SRE = 0, WE = 1)
\
READ ENABLE
(RRE OR SRE)
r-
::j
I----i~~(t~«~~f-r~--------,,).1)
. . . . . 0'""ID
80 NS MAX.
~R~~~HO~~P~;.SH) _ _ _ _HI__
-Z
--1
j
(TPE)
Read Port Enable/Disable (Address Stable, WE
6-5
». .
(TPD)
= 1)
100 NS MAX.
HI-Z
•
T-1 Tri-Port Memory
R8040
Propagation Delays
Parameter
Random Read Access Time
Sequential Read Access Time
Read Port Disable (to HI-Z)
Read Port Enable
Same-Location Read After Write
Symbol
Min
Max
Unit
tRA
tSA
tpo
tpE
tSl
0
0
0
0
0
380
430
n.
ns
n.
ns
ns
100
-80
340
A -WRITE OATAB
e
o
E
F
G
R32 RANDOM ADDRESS INPUTS
Rl.
RO
10FB4
READ
RANDOM
ADDRESS
DECODER
R04
R02
ROl
RANDOM
READ PORT
WRITE
ADDRESS
WSEl
"0"= RANDOM
SELECTOR
SeQUENTIAL
ADDRESS COUNTER
t
selK
>-'=::---~ elK
SEQUENTIAL
READ PORT
832
10F64
SOB~=~+===1
SEQUENTIAL
ADDRESS
',6
SO'tSOl
S02
READ
DECODER
Trl-Port Memory Block Diagram
6-6
R8040
T-1 Tri-Port Memory
MAXIMUM RATINGS·
Symbol
Value
Unit
Supply Voltage
Parameter
Voo
+4.75 to +5.25
V
Operaling Temperature
Top
010 +70
·C
Storage Temperature
TSTG
-55 to +150
·C
• NOTE: Stresses above those listed may cause permanent
damage to the device. This is a strass rating only and functional
operation of the device at these or any other conditions above
those indicated in other sections of this document is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Voo = +5V ±5%, Vss = OV TA = 25°C)
Parameter
Symbol
Min
Max
Unit
V
Input Logic "1" Voltage
V1H
Input Logic "0" Voltage
V1l
Input Logic "1" Voltage
VOL
Output logic "0" Voltage
VOL
Output Source Current
10H
-100
Output Sink Current
10l
400
Input Capacitance
C1
Output Capacitance
Co
25
pF
Power Dissipation (at 25·C)
Poss
300
mW
2.0
0.8
2.4
V
V
0.4
V
p.A
p.A
5
pF
•
6-7
T -1 Tri-Port Memory
R8040
PACKAGE DIMENSIONS
!
.550
TaO
'T1-n-rrTTTTTTTTTTTTTTTTTTTTTTTTTTTT"1~~
=J~~~~i a
I
.160
~
(51.3MM)
•
1:i40
~
1-~---1
1,-.590 ---.1
·o's
-:ooa
I---~
.600
NOTE: PIN NO.1 IS IN LOWER LEFT CORNER WHEN SYMBOLIZATION IS IN NORMAL ORIENTATION
6-8
R8050
T- f PCM Devices
'1'
R8050
T-1 SERIAL TRANSMITTER
Rockwell
DESCRIPTION
The Rockwell T-1 Serial Transmitter formats data to be
serially transmitted according to T-1 02 or T-1 03 specifications, inserting framing and signalling bits along with 24
channels of 8-bit channel data. The T -1 Serial Transmitter
also provides for alarm reporting via the Bit 2 inhibit method
or, with minimal external logic, via the multiframe alignment
signal (Fs) modification method.
B70PTN
TEST
FRSYNe
SBIT
CCIS
SSTB
UNPLRA
UNPLRB
GND
BINOUT
SYNOUT
LOOP
SYNCIN
BCH
Figure 1 is a functional block diagram of the T-1 Serial Transmitter. The Mod 193 counter is driven by the clock at 1.544
MHz and is either synchronized to the driving system by input
signal SYNCIN or provides synchronization via output signal
SYNOUT. Input signal FRSYNC applies synchronization to
a Mod 12 counter, which identifies the frame of the 12-frame
multiframe being processed.
The input data register latches data during each bit period,
when the 8th bit of a channel sample is being transmitted.
The data selector outputs the proper sequence of bits, as
controlled by a bit count and frame count.
1.
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
28
25
24
23
22
21
20
19
18
17
16
15
INH
BIT3
CHCLK
BIT4
BIT2
BITS
Bin
BIT6
BIT7
VDD
CLOCK
ALARM
BITa
ACH
Pin Configuration
The zero channel monitor function causes Bit 8 or Bit 7 to
be transmitted as a "one" if the channel data sample is all
"zeros." Input INH provides a means to inhibit the zero
channel monitor function. Input B70PTN controls the particulars of the insertion method.
FEATURES
• Single 5V supply, low power Schottky TTL compatible.
• Accepts 8 bits of parallel data as input.
• Generates output as 193 bit serial data stream in T-1, 02, 03
or 04 Mode 3 data format.
• Provides a channel and frame timing signal.
• Provides alternate control for alarm reporting and Signalling.
• Provides automatic bit insertion for all-zero channel samples.
Two types of transmit formats are provided, a binary output
and a paired unipolar output. The unipolar pair provides a
means to externally create a single bipolar output with minimallogic.
FRSYNC
r - - - - - . r - - - - - + - - - - - -..... CHCLKF
SYNCIN
>-~---r.;;-::;;;;;"I
~~>_~--_L~~
,VDC)-+
GND)-+
r-++-!--''--++++-----......
SYNOUT
r-----~SST8
BIT.
BIT 2
BIT 3
BIT.
BIT 5
BITS
BIT'
BINOUT
UNPl.RA
UNPt.RB
BIT.
ALARM
ACH
OCH
OOS>====::1
salT).-
Figure 1. T-t Serial Transmitter
Document No. R8050D
6-9
Data Sheet Order No. 307
Rev. 4, June 1984
•
T-1 Serial Transmitter
R8050
T-1 TRANSMITTER INPUTS
BCH: "B" CHANNEL HIGHWAY SIGNALLING
Any input :s0.8V = logic 0, low. Any input :2: 2.0V = logic 1,
high. The transition from a low level to a high level is called a
rising edge, while the converse is defined as a falling edge.
BCH allows the user to transmit one bit of signalling per chaf)nel
as Bit 8 of each channel data sample in Frame 12 only. BCH
is clocked into the input register by the falling edge of CHCLKF.
Refer to Table 1 and Figure 4 . ' .
i
FRSYNC: FRAME SYNCHRONIZATION
Frame sync allows external synchronization of the transmitter's
internal frame counter. When FRSYNC becomes high, the frame
counter is directly set to frame 1, the first of the twelve frames.
If FRYSYNC is held high and does not return to zero before a
rising edge of CLOCK, the subsequent states of BINOUT,
UNPLRA and UNPLRB are high, high and low, respectively,
regardless of the ,states of any other inputs. The latter
mechanism is useful for device and/or board testing only and
will cause bit errors and/or bipolar violations if used during field
operations. See Figures 6 and 7.
SYNCIN: SYNCHRONIZATION INPUT
SYNCIN allows external synchronization of the internal Modulo
193 bit/channel counter. When SYNCIN becomes high, the
Modulo 193 counter is directly set to the state corresponding
to the output of the framing (FT or Fs) bit. The 'first bit of channel one will be output on BINOUT (and UNPLRA or UNPLRB)
as a result of the first rising edge of CLOCK following the return
of SYNCIN to logic O. See Figures 5 and 7.
TEST: ROCKWELL DEVICE TEST INPUT
Used only for Rockwell device testing. Keep this input
grounded.
CLOCK: T-1 CLOCK
Maximum frequency = 1.6 MHz
Minimum pulse width = 275 ns
The T-1 bit period is bounded by the rising edges of this input.
INH: INHIBIT ZERO CHANNEL MONITOR
If INH is high, the zero channel monitor function is disabled, and
Bits 7 and 8 are transmitted per corresponding inputs received.
See Table 1.
For channels in signalling frames (6 or 12) in which the first six
data bits and the signalling highway are all "zero," BIT 7 will
be forced to one if INH is low. For any frame except a signalling
frame Bit 8 or Bit 7 as selected by B70PTN will be transmitted
as a "one" if the channel input data is "zero" and INH is low.
BITS 1-8: PARALLEL CHANNEL DATA INPUTS
Bit 1, the sign bit, will be serially transmitted first, followed by
Bits 2 through 8. The falling edge of CHCLKF indicates input
channel data has been clocked into the input register and always
occurs during the transmission of the final bit (Bit 8) of each channel data sample.
ACH: "A" CHANNEL HIGHWAY SIGNALLING
ACH allows the user to transmit one bit of signalling per channel as Bit 8 of each channel data sample in Frame 6 only. ACH
is clocked into the input register by the falling edge of CHCLKF.
Refer to Table 1 and Figure 4.
S-BIT: MUL TIFRAME SIGNALLING BIT
SBIT, in conjunction with CCIS, provides an alternate way to
control the multiframe signalling bit (Fs) transmission. The S-Bit
input is transmitted as the multiframe signalling bit (Fs) if CCIS
is held high. Refer to Table 2.
ALARM: LOCAL ALARM
Used for reporting alarm conditions. If the ALARM signal is high,
Bit 2 (the most-significant bit) of every channel data sample of
every frame is transmitting as a zero. This is commonly called
remote alarm signalling. ALARM is clocked into the input register
at the falling edge of CHCLKF. Refer to Table 1 and Figure 4.
LOOP: LOOP STRAP
Provided to aid testing of user applications. When enabled to
a high level, LOOP forces the unipolar outputs to transmit alternating ones and zeros, regardless of input conditions, while
BINOUT continues to provide normal data outputs. Refer to
Figure 3.
CCIS: COMMON CHANNEL INTEROFFICE
SIGNALLING STRAP
Provides optional control for replacing the automatic Fs pattern
with a 4-kilobit common channel signalling path. When CCIS
is high, the SBIT input replaces the Fs pattern and the insertion of ACH and BCH is suspended. The CCIS input may also
be used to provide the alternate method of alarm reporting. See
Figure 4.
B70PTN: BIT 7 OPTION
Provides Bit 7 as an alternate bit position for "one" stUffing, as
programmed by the zero channel monitor function. Refer to
Table 1.
VSS, VDO: GROUND AND POWER
VD D = +5 ±0.25 Vdc
Vss = Ground, 0 Vdc
T-1 TRANSMITTER OUTPUTS
Low power TIL Schottky compatible. "1" :2: 2.4 Vdc, "0" :s
0.4 Vdc, CMOS - 12Kll pullup to VDD required.
SSTB: 4 kHz SIGNALLING CHANNEL STROBE
SSTB is the least-significant bit of the frame counter. Unless
it is directly set by FRSYNC, SSTB will go high as each framing
bit (FT) is serially transmitted, and will return low as each
multiframe alignment signal (Fs) is transmitted. Refer to
Figure 2.
SYNOUT: CHANNEL SYNC OUTPUT
SYNOUT provides a means to synchronize to the internal bit
counter (Mod 193). SYNOUT is high for one bit time, beginning
just prior to the first data bit of a frame being serially transmitted.
Refer to Figure 7. ~YNOUT is the only output determined by
the falling edge of CLOCK.
T·1 Serial Transmitter
R8050
UNPLRA, UNPLRB: T·1 SERIAL DATA UNIPOLAR
OUTPUTS
CHCLKF: CHANNEL CLOCK FALSE
The falling edge of CHCLKF, occurring as Bit 8 of any channel
is being serially transmitted, indicates input data has been
clocked into the input register. With the exception of an extra
bit period extending the low level duration at frame bit time,
CHCLKF is a divide-by-eight of CLOCK. Refer to Figure 2.
Two paired unipolar outputs are provided for the purpose of
creating a single serial data output transmission in bipolar format. The unipolar output register toggles for each "one" bit to
be serially transmitted. UNPLRA and UNPLRB are transmitted
as complements for "one" data bits and as low levels for "zero"
data bits. See Figure 3.
BINOUT: SERIAL DATA OUTPUT, BINARY
FORMATTED
The input signal LOOP, if high, forces the umpolar outputs to
toggle every bit time, regardless of Input data.
BINOUT is the binary formatted serial conversion of the parallel
input data. The programmed format of BINOUT follows Tables 1
and· 2.
FRSYNC perturbs the current bits being transmitted by UNPLRA
and UNPLRB. If FRSYNC remains high during the rising edge
of CLOCK, UNPLRA will be transmitted as a high level and
UNPLRB will be low. Refer to Figures 6 and 7.
BINOUT is synchronously transmitted as a high level if FRSYNC
remains high during the rising edge of CLOCK. Refer to
Figures 6 and 7.
Table 1. Serial Channel Sample Output Data Truth Table
Inputs X
z
::;;
II:
~
= don't care
J::
Ii:0
...
~
l-
0(
i!:
III
iii
'"
I::
III
...
M
III
~
I::
II)
I::
'" I-...
l-
III
iii
iii
IX)
I-
iii
J::
u
0(
J::
Current
Frame
Number
u
III
Blnout
Serial Output
Notes
Channal
Bit Position
,
2
3
4
5
6
7
8
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
1
0
X
X
P
Q
R
S
T
U
V
X
A
X
6
P
Q
R
S
T
U
V
A
2
X
X
B
12
P
Q
R
S
T
U
V
B
2
Y
P
Q
R
S
T
U
V
W
2,3
0
0
0
0
0
A
1
0
X
X
P
Q
R
S
T
U
V
0
X
X
P
Q
R
S
T
U
V
W
X
X
0
1
X
0
0
0
0
0
0
0
X
A
X
6
0
0
0
1
X
0
0
0
0
0
0
0
X
X
B
12
0
0
0
0
0
0
0
B
0
1
X
0
0
0
0
0
0
0
W
X
X
Y
0
0
0
0
0
0
0
W
0
0
X
0
0
0
0
0
0
0
X
0
X
6
0
0
0
0
0
0
1
0
0
0
X
0
0
0
0
0
0
0
X
X
0
12
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
X
X
Y
0
0
0
0
0
0
1
0
3
0
0
0
0
0
0
0
0
0
0
0
X
X
Y
0
0
0
0
0
0
0
1
3
NOTES (1) ALARM = 1 has the same effect as BIT 2 = 0
(2) P, Q, R, S, T, U and V may not Simultaneously be zero, unles A, B or W IS I
(3) Y IS any frame
6 and f 12 with eels = 0, or all frames with eels = I
r
6-11
3
II
R8050
T·1 Serial Transmitter
Table 2. Framing Bit (FT & Fs) Output Data
Frame
Number
Blnout
Proce888d
Bh
CCIS = 1
CCIS = 0
1
FT
1
1
2
F.
0
S81T
3
FT
0
0
4
F.
0
S81T
5
FT
1
1
6
F.
1
S81T
..
7
FT
0
8
F.
1
9
FT
1
1
F.
1
S81T
10
11
FT
0
12
F.
o (NOTE 1)
0
S81T
0
S81T
Notes: (1) Alternate remote alarm reporting may be accomplished by holding S81T and CCIS both high just prior
to initiation of Frame 12.
(2) FT bit insertion is automatic and no optional control is provided.
CLOCK
(1.544 MHz)
8
X
6
8
2
3
5
6
8
CHCLKF
--wb--SAMPLE CH.1
---l
F,
OR
F,
1
3
-a~~_A-~A-~A-~A-~A-~A-'~A-~A-~A-~A-~A-~A-~A-~A-~A-~~~~~
. . CH. 24
F
2
BINOUT =
BIT NO.
o
/nJ--------------nVr::SAMPLE CH. 2
I""..t - - - - -
CHANNEL 1
CHANNEL 2
J
(horizontal seele change)
o
F, = 0
FRAME NUMBER
F, = 1
o
o
o
1
See Fig. 7
SSTB
SYNOUT
FRSYNC"
~
______________________________________________________
SYNCIN"
"POSSIBLE POSITIONS TO RE-INFORCE INTERNAL SYNCHRONIZATION.
Figure 2. Transmitter Input-Output Signal Relationships
6-12
~~
_________
R8050
T -1 Serial Transmitter
CLOCK
LOOP
BINOUT
UNPLRA
UNPLRB
----'
Figure 3. Transmitter Binary, Unipolar Outputs
;;:~ - --~ ---J----\ ----~=k-,:\ ----~
::~~~~
~7~PTN
I
I
ALARM
X
-xt
X
61h
13s
X
7th
81h
X
F or 1st
X
-jtX- I: _________________ _
---l
Figure 4 (a). Channel Input Timing
CLOCK
LOOP
xxx
XXX
Figure 4 (b). LOOP Input Timing
CLOCK
~
\
/
\~~\
SSTB
SBIT
BINOUT
CCIS
------------~ ~
X
CH 24, BIT7
X
J
/
\
r
-J\\\\\\\\
ft------------------
CH 24, BIT 8
X
~SEENOTE)
Fs
X
CH1,BITl
NOTE: eCls WAVEFORM SHOWN FOR ALTERNATE ALARM REPORTING METHOD. CCIS SHOULD BE
ACTIVE JUST PRIOR TO FRAME 12. UNDER THESE CONDIl10NS, SBIT HIGH WOULD REPORT
THE REMOTE ALARM.
Figure 4 (e). Control Input Timing
6-13
X
•
R8050
T-1 Serial Transmitter
CLOCK
\,--~I
,..11;';
0
X
SYNCIN
BINOUT
x
ANY BIT
CH 1, BIT 1
\'-----11
X
CH1,BIT2
x
Figure 5. SYNCIN Timing Relationship
r==
-.1\=4\
CLOCK
/--
FRSYNC
\
/
~_I'H
I"
/
\
il7
SSTB
BINOUT
XYY
iZ7
\\S
XXX
UNPLRA
xxz
01
\\\
III
UNPLRB
XXX
SS~
liZ
XXX
Figure 6. Non-return-to-zero FRSYNC Timing
CLOCK
FRSYNC
(Return to zero)
SYNCIN
(1 PULSE PER 2316 CLOCKS)
_____un
~~t~N~~T~
DATA
IN
..
BINOUT
SYNOUT
IIIII - - - - - - - - - - - - - - - - - - - - J..~
t-
may change
..
I
CH 23
FRAME 12
CHANNEL 1 FRAME 1
7888F818283848s86
////1
SSTB
CHCLKF
(1 PULSE PER 193 CLOCKS, MAX)
\~"\\
~h~Wff
///II
~~~~~_______________
Figure 7. Transmitter External Synchronization (Return-to-zero FRSYNC)
6-14
R8050
T-1 Serial Transmitter
Table 3. Input Timing
Symbol
Parameter
tIS
Buffered Data Setup Time
tlH
Min
Max
Unit
450
ns
Buffered Data Hold Time
a
ns
~
Control Input Setup Time
400
ns
I:!H
Control Input Hold Time
20
ns
~
Asynchronous Control Input Setup Time
350
ns
t3H
Asynchronous Control Input Hold Time
20
ns
~
SYNCIN Setup Time
200
ns
t.H
SYNCIN Hold Time
20
ns
SYNCIN Pulse Width
100
ns
Iss
Frame Sync Setup Time (Return to Zero)
250
ns
isH
Frame Sync Hold Time (Return to Zero)
20
ns
Frame Sync Pulse Width
200
ns
Iss
Frame Sync Setup Time (Non· Return to Zero)
525
ns
t5H
Frame Sync Hold Time (Non·Return to Zero)
20
ns
Table 4. Output Propagation Delay, Worst Case
(Measured from Rising Edge of Clock Unless Stated Otherwise)
Output
Max Delay
Unit
SSTB
SYNOUT
Ref from Failing
Edge of Clock
CHCLKF
BINOUT
UNPLRA
UNPLRB
500
500
ns
ns
500
500
500
500
ns
ns
ns
ns
MAXIMUM RATINGS*
Parameter
Symbol
Value
Unit
Supply Voltage
Voo
+475 to +5.25
Vdc
Operating Temperature
Top
a to 70
·C
Storage Temperature
TSTG
-55 to + 150
·C
"NOTE: Stresses above those listed may cause permanent
damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above
those indicated in other sections of this document is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Voo = 5.0
±5%)
Symbol
Min
Max
Unit
Logical "1" Input Voltage
VOH
2.0
Vao + 03
V
Logicical "0" Input Voltage
V,l
-0.3
0.8
V
Logicical "1" Output Voltage
VOH
2.4
-
V
Logic "a" Output Voltage
VOL
-
04
V
Output Source Current
10H
-100
~
Output Sink Current
400
Capacitance Load (any output)
IOl
C
25
pF
Input Capacitance (any input)
C'N
-
5
pF
-
1.6
MHz
-
250
mW
Parameter
Clock Frequency
Power Dissipation
Po
6·15
~
II
R80S0
T-1 Serial Transmitter
PACKAGE DIMENSIONS
~
(.530)
'-r-r-n-1rTTTT'T"TTTTTTTTTT"T'TTT"T"I"TT""
~
~
UII
(.085)
(.065)
~1-lij~~rIT1-~
jlt1: j t:~,"; 1\: t:~~l ~
(.015)
(.090)
6-16
(.125)
(.020)
R8060
T-1 PCM Devices
'1'
Rockwell
R8060
T-1 SERIAL RECEIVER
DESCRIPTION
SIGFR
SBCLK
TOATA
TCLK
VOO (+5)
W1HBT
B2ALRM
TESTI
FRALRM
CHCLK
MAXCNT
CHSYNC
SYNCEN
MR
GNO
CALRM
SBALRM
The Rockwell T-1 Receiver processes senal unipolar data of a
T-1 ,02 or T-1 ,03 line from which data and a 1.544 MHz clock
have been extracted
Frame synchronization IS accomplished by locating the frame
bit (FT) alternating every 386 bits. loss of frame sync IS indicated
If a frame bit error occurs within two to four F-Blt frames since
the prevIous frame bit error
A loss of carrier is indicated if 31 consecutive bit times Yield
"zeros" at the Input Carner loss IS reset and frame sync search
begins when a "one" reappears at the TDATA input
COB7 }
COBB
COB6
COBS
COB4
COB3
COB2
COB1
COINH
SBIT
TESTO
Signaling bits, which occur 193 bit positions after a framing bit,
are monitored to detect signaling frames. The signaling frame
output, SIGFR, Identifies the present frame as a signaling frame.
and the S-Bit output at that time Identifies which signaling frame
IS being processed.
CHANNEL
DATA
BITS
Pin Configuration
Remote alarm reporting IS detected by monitoring the second
received bit of every channel sample of every frame. An alarm
IS indicated if 255 consecutive Bit 2 zeros are received.
Channel data bits are output by an eight-bit parallel register. The
rising edge of the signal called channel clock (CHCll<) indicates
the extraction of new output channel data.
VD0>--C:>
vss
Several signals developed from a MOD 386 counter are provided
to aid In the external processing and storage of channel data.
Signals are provided to Increment counters, synchronize
counters, strobe data Into memOries, etc.
_sv
>----C:> IGND}
P2
P12
,
, .
rrr~~~~1!!8 "
7
5
2
COINH
2
8
CHANNEL
"
~~~A
"
~'2!"--------r--'-~!:t:~~
The Rockwell T-1 Receiver chip operates on a single 5 volt supply
and directly Interfaces to the low power TIL Schottky logic family.
The Receiver is packaged in a 28 pin dual In-line (DIP).
•
Timing relationships are given in figures 3 through 5.
FEATURES
•
Synchronizes serial T-1 ,02 or T-1 ,03 signals in less than 5 ms.
•
Extracts 8-bit parallel channel data
•
Provides timing signals to capture and synchronize channel
and frame information
SVNCEN~'IT'tO===llf=~~~~~~~L.
MR
11
CHCLK
WIHBT
CHsYNC
•
MAxCNT
Monitors and detects
-
C~====::;;:;~
Errors in signaling bit pattern
loss of frame sync
loss of carrier
Remote alarm reporting
TESTl~
SBCLK
salT
Si"G'Fii
(LEAVE OPEN)
B2AlRM
• Single 5V supply
•
lSTTl Schottky compatible
Figure 1.
R8060 Block Diagram
Data Sheet Order No. 308
Rev. 4, June 1984
Document No. R8060D
6-17
T-1 Serial Receiver
R8060
T-1 RECEIVER INPUTS
CDB (l-S): CHANNEL DATA BIT 1 THROUGH 8
Any input sO.SV = LOGIC 0, LOW, ZERO. Any input "'=2.0V =
LOGIC 1, HIGH, ONE. A transition from a low level to a high
level is called a rising edge, while the converse is true for the
falling edge.
Bit 1 is the sign bit, Bit 2 is the most significant bit and Bit S
is the least significant bit. If CDINH is low, new parallel channel
data becomes valid within 200 ns after the rising edge of CHCLK
and remains valid until the next rising edge of CHCLK. If CDINH
is high, channel data Bits 1 through 7 are forced to a high level.
Bit S, the least significant bit, is not controlled by CDINH. Channel data Bits 1 through 7 are enabled or disabled within 300 ns
(RS060) or 150 ns (RS060A) by CDINH. Refer to Figures 3
through 5.
TDATA: UNIPOLAR T-l-D2, T-l-D3 SERIAL DATA INPUT
Unipolar T-l Data is clocked in on the falling edge of TCLK.
Thereafter, TDATA is processed on the rising edge of TCLK.
TDATA must be stable 100 ns before and remain stable 100 ns
after the falling edge of TCLK.
CHCLK -
CHANNEL CLOCK
The rising edge of CHCLK indicates a change of parallel output
channel data. CHCLK is four TCLKS high then four TCLKS low
except for when an "F" or "S" bit is received. Then CHCLK
stretches to five TCLKS high and four TCLKS low. Refer to
Figures 3 and 4.
TCLK: T-l CLOCK
Typical clock frequency is 1.544 MHz. Maximum clock frequency
is 1.S5 MHz. The T-l bit period is bounded by the rising edges
of TCLK. Input levels must be >2.4 volts for LOGIC 1 and
~O.S volts for LOGIC O.
SYNCEN: FRAME SYNCHRONIZATION ENABLE
CHSYNC:CHANNELSYNC
Provides a means to disable the automatic resync search initiated by a FRAME ALARM condition. If the SYNCEN signal is
low, with synchronization function is inhibited and remains inhibited until SYNCEN transitions high. SYNCEN must be stable
200 ns before the rising edge of FRALRM, in order to inhibit the
synchronization function.
Channel Sync occurs one time in a 24 channel period, making
it suitable for synchronizing external counters to the T-t Frame
rate. CHSYNC goes low one TCLK period before the falling edge
of CHCLK at channel 24 date sample time. CHSYNC returns
high t TCLK period after the next rising edge of CHCLK. Refer
to Figures 3 through 5.
MR: MASTER RESET
TESTO: ROCKWELL DEVICE TEST OUTPUT
Master Reset, when low performs an initialization clear of the
T-l Receiver; SBALRM and CALRM are reset to low levels while
FRALRM, CHCLK, WIHBT and CHSYNC are set to high levels.
Frame synchronization search begins on the rising edge of MR
provided that SYNCEN signal has been high for 200 ns.
Minimum pulse width is one T-l clock period.
Designed to aid in Rockwell device testing. No connection
required for normal operation.
WIHBT: WRITE INHIBIT
WIHBT covers the parallel channel data transition period. WIHBT
is suitable for clocking or strobing channel data into external
memories. WIHBT is high for two TCLK periods, beginning one
TCLK period before the rising edge of CHCLK. Refer to Figures
3 and 4.
CDINH: CHANNEL DATA INHIBIT
Provides a means to disable channel data bit outputs. When at
a high level, CDINH forces channel data Bits 1 through 7 high.
Bit S, the least significant channel data bit, is not controlled by
CDINH.
MAXCNT: MAXIMUM COUNT OF 386 MODULUS
TESTI: ROCKWELL DEVICE TEST INPUT
MAXCNT is low for one TCLK period, marking the completion
of a two-frame period corresponding to the expected receipt of
an F-bit at the TDATA input. Refer to Figures 4 and 5.
Used only for Rockwell device testing, no connection to TESTI
is required for normal operation.
SBCLK: S-BIT CLOCK
SBCLK will be high during the S-Bit frame and low during the
F-bit frame. The transitions will occur within 300 ns after the rising edge of TCLK as channel 24 data is being transferred to the
parallel channel outputs. Refer to Figures 3 through 5.
VSS, VDD: GROUND AND POWER
VDD = + 5.0 ± 0.25 VDC
VSS = Ground, 0 VDC
S-BIT: SIGNALING BIT OUTPUT
T-1 RECEIVER OUTPUTS
The S-Bit output will have the same digital level as the previous
S-Bit received which occurred two frames before the receipt of
the current S-Bi!. An S-Bit output transition occurs one TCLK
period after the rising edge of SBCLK.
Low Power TIL Schottky - compatible
"1" "'= 2.4 Vdc; "0" s 0.4 Vdc
CMOS - 12 K n pullup to VDD required.
6-18
R8060
T-1 Serial Receiver
During a signaling frame (SIGFR IS low), frame 6 or "A" highway
signaling is identified by S-Bit output being low If S-Bit is high
during a signaling frame, frame 12 or "B" highway signaling
is identified. Refer to Figures 3 through 5.
FRALRM is set high and frame sync search begins when the
first TDATA high level is received.
FRALRM: FRAME ERROR ALARM
SIGFR: SIGNALING FRAME
FRALRM detects an out-of-frame condition FRALRM goes high
If:
SIGFR Identifies frame 6 or 12 when low. If the sequence of five
consecutive received S-Blts IS either 0111 X or 1X001 (left to nght,
as received), SIGFR shall go low after the nSlng edge, but at
least 375 ns before the falling edge of WIHBT corresponding
to channel 1 data sample time. SIGFR returns high one frame
later (193 bits). Refer to Figures 3 through 5.
A)
B)
C)
D)
SBALRM: S-BIT ALARM
The framing synchronization function IS in progress.
Within 250 ns after the falling edge of MR.
An F-Bit IS received which is not the inverse of the last
F-Bit and the same condition also occurred two or three
or four F-Bit frames earlier.
Within 250 ns after the falling edge of CALRM, (CALRM
being reset by high level TDATA bit).
FRALRM goes low upon completion of the synchrOnization function or within 250 ns after the rising edge of CALRM. (Carrier
loss condition dUring frame synchronization function).
SBALRM goes high If the sequence of the five S-Bits received
contains four consecutive ones (01111), and remains high until
three consecutive "zero" bits are preceded and followed by a
"one" S-Blt (10001). The actual transition of SBALRM output
occurs after the rising edge, but at least 375 ns before the failing edge of WIHBT corresponding to channel 1 data sample
time.
OUTPUT CLOCK SIGNALS DURING FRAME
SYNCHRONIZATION FUNCTION
Following the Declaration of Frame Sync loss (FRALRM goes
high), output signals will continue. normally for a two-frame period
With the exception of CHSYNC, which has the above mentioned
second frame sync pulse inhibited. Following the two-frame
period CHCLK, CHSYNC, and WIHBT are held high until frame
sync has been located, as indicated by the falling edge of
FRALRM. With typical data patterns, frame synchronization
takes less than five milliseconds. See Figure 2.
B2ALRM: BIT 2 ALARM
B2ALRM goes high, detecting a remote alarm condition, If 255
consecutive chan nel data samples are received with Bit 2 low.
B2ALRM returns low upon the receipt of any channel sample
with Bit 2 high.
CALRM: CARRIER LOSS ALARM
A carrier loss IS detected and CALRM is set high If 31 consecutive low level TDATA bits are received. CALRM IS reset low,
/FRAMESVNC
FRALRM------lr------------------------------------------iLl________________
-t/
- - - - - 2 FRAME PERIOO-----.I__
t-1_ _ _
CHCLK~~
WIHBT
Figure 2.
Signal Relationship During Frame Alarm and Search for Resynchronization
6-19
•
T -1 Serial Receiver
R8060
_ F BIT FRAME
CH24
I
S BIT FRAME_
CHl
r-----A.----~
A~_ _ _ _~
~~~~A~ATA I' f± 1.. 132 1,.1. I-I 2I: IB~Tf ± 1"1 32 1'.1 .1 _I 21, 'I ±·I .. I32
CLOCKED DATA 1'1 ±H32I'·I·I-12I'IB~TI ± H32H .1_1 21'1 H
±
TCLK (1.54 MHZ)
CHCLK
-.--J
I
WIHBT
I
CHSYNC
SBCLK
X
SBIT
c=-
SIGFR
X
CHANNEL DATA--y CH23 OUTPUT DATA
PARALLEL
--fI
..
Figure 3.
CH24 OUTPUT DATA
~
~
Signal Relationships at Beginning of FS Frame (S-BIT)
I
- S BIT FRAME F BIT FRAME--CH24
CHI
r-----A.----~
A
~~~~;ATA I' f± 1"1 32 1,.1.1-1 21: 1.~Tf ± 1"1321'.1.1_121, 'I ±1.. 132
CLOCKED DATA I' I ± 1
.. 1'.1.1_ 121, IB~TI H32 H ·1_ 121' I H
132
±
±
TCLK (1.544 MHZ)
CHCLK
-.--J
I
WIHBT
I
CHSYNC
SBCLK
NO CHANGE
SBIT
SIGFR
MAXCNT
U
X
CHANNEL DATA --y CH23 OUTPUT DATA
PARALLEL
--fI
..
Figure 4.
CH24 OUTPUT DATA
~
~
Signal Relationship at Beginning of FT Frame (F-BIT)
6-20
T-1 Serial Receiver
R8060
FRAME SYNCHRONIZATION
BIT (F BIT) PATTERN
SBCLK
SBIT
~"'_ _ _ _ _ _ _ _ _ _ _--'
(OUTPUT)
L....J
SIGFR
u
u
u
=
u
=
u
=
FRAME
24 TIME SLOTS
193 BITS
125!,S
TIME SLOT = 5.18!,S ONE BIT = 648 NS
MULTIFRAME = 12 FRAMES = 1.5 MS.
F BIT (FT) ALIGNMENT SIGNAL
(ODD-NUMBERED FRAMES)
S BIT (Fs) MULTIFRAME ALIGNMENT SIGNAL
(EVEN-NUMBERED FRAMES)
FRAME
FIRST BIT
FRAME
FIRST BIT
1
3
5
1
0
0
0
7
0
1
0
2
4
6
8
10
12
9
11
Figure 5.
1
1
0
Multiframe Signal Relationships
Table 1. Output Propagation Delay
Worst Case, From Rising Edge of TCLK
I
( 550)
OUTPUT
MAX DELAY (NS)
CHCLK
CHSYNC
WIHBT
MAXCNT
SBCLK
SBIT
SIGFR
SBALRM
B2ALRM
CALRM
FRALRM
COB (1-8)
300
300
300
300
400
400
475
475
450
300
900
400
( 530)
~rTTTTTTTTTT"I"TTTT"I"TTTTTrr'~
Packaging Diagram
6-21
•
T-1 Serial Receiver
R8060
MAXIMUM RATINGS·
Parameter
Supply Voltage
Symbol
Value
Unit
Voo
+4.75 to +5.25
V
Operating Temperature Range
Top
Storage Temperature Range
TSTG
o to
+70
-55 to + 150
• NOTE: Stresses above those listed may cause permanent
damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above
those indicated in other sections of this document is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
·C
·C
ELECTRICAL CHARACTERISTICS
(Voo = +5V ±5%, TA = 25·C)
Parameter
Symbol
Min
Input LogIC "1" Voltage
V ,H
2.0
Input LogIc "0" Voltage
V,l
-03
Output Logic "1" Voltage
VOH
Output Logic "0" Voltage
VOL
Output Source Current
IOH
-100
Output Sink Current
IOl
400
Clock Frequency
TClK
Max
Unit
Voo + 0.3
V
0.8
V
V
2.4
0.4
V
p.A
p.A
185
MHz
pF
Input CapacItance
C,
5
Output CapacItance
Co
25
pF
Power DIssipation
Poss
550
mW
6-22
R8069
'1'
Rockwell
R8069
Line Interface Unit (LlU)
INTRODUCTION
FEATURES
The Rockwell R8069 Line Interface Unit (LIU) is a single
chip CMOS device that interfaces the Rockwell R8070
T1/CEPT PCM Transceiver to the physical T-1/CEPT
PCM30 transmission medium.
•
Compatible with T-1 and PCM30 (1.544 Mbit/s and
2.048 Mbit/s)
•
Selectable T-1 and PCM30 clock rates
•
Implements ISDN primary rate interface
The R8069 LlU device contains analog and digital circuits
which are based on CMOS technology to implement the
line interface function required in ISDN primary rate transmission. The R8069 provides capabilities for 4-wire transmission of image, voice, or data signals; clock extraction;
line equalization; bipolar violation detection; jitter accommodation; and AIS (Blue Alarm) generation and detection.
In addition, the device operates at 1.544 or 2.048 Mbit/s
and meets pulse shape and jitter specifications which are
in accordance with T-1 and PCM30 standards.
•
Directly compatible with Rockwell R8070 T-1/CEPT
PCM Transceiver and R8071 ISDN/DMI Link Layer
Controller devices
•
Independent transmit and receive sections
The R8069 is ideally suited for image, voice, or data transmission required in ISDN primary rate applications. The
device is highly integrated and requires virtually no external components.
Internal LlU functions allow system designers to minimize their development cost and easily implement a
T-1/PCM30 physical interface to primary rate lines without
concern about most of the complex details normally associated with such a design. The R8069 also provides a
high level of integration which increases system reliability,
reduces space and achieves higher levels of performance
and quality.
Document No. 29300N36
•
Phase locked loop for loop timing applications
•
Satisfies T-1 (AT&T Technical AdviSOry No. 34) and
PCM30 (CCITT G.703)
•
Provides line equalization for up to 655 feet of 22gauge plastic insulated (ABAM) cable for T-1 applications
•
Transmission/reception of data for up to 1600 feet of
cable
•
Accomodates pulse shape requirements for 75
120 Q lines in PCM30 application
•
Meets or surpasses jitter requirements specified by
T-1 (AT&T Publication 62411, October 1985) and
PCM30 (CCITT G.823)
and
•
Intrinsic jitter under 0.05 UI
•
Jitter attenuation starts at 2 Hz
•
Jitter tolerance above 0.4 UI for jitter frequency up to
100 kHz
•
32-bit elastic store for jitter control and attenuation
•
Elastic store bypass provisions
•
Master/slave timing option
•
Local and remote loop operation
•
AIS (Blue Alarm) generation and detection
•
On-chip line drivers
•
Bipolar violation detector
•
Analog CMOS technology
•
Operates from a single +5V supply
•
28-pin plastic dual in-line package (DIP)
•
TTL!CMOS I/O compatible
Data Sheet
6-23
Q
Order No. 336
Rev. 2, January 1989
Line Interface Unit (LlU)
R8069
ORDERING INFORMATION
t
INTERFACE SIGNAL DESCRIPTION
The R8069 interfaces directly to the R8070 and R8071 on
one side and the DSX-1 or PCM30 demarcation point on
the other, through transmit and receive transformers located external to the LlU device. The R8069 LlU interface
signals are functionally grouped in Figure 1. Figure 2
shows the R8069 pin assignments. The R8069 interface
signals are described in Table 1.
Part Number:
R8069
Temperature
Blank = O'C to + 70'C
--Package
P = 2S-Pin Plastic DIP
1: 1
RX
3111E
T1 LINES
2 :1
~3111EI
R8069
LINE
INTERFACE
UNIT
(LlU)
1.544 MHZ (Tl)
2.048 MHZ (PCM 30)
R8069 LlU Functional Interface
6-24
R8070
Tl/CEPT
PCM
TRANSCEIVER
Line Interface Unit (LlU)
R8069
R8070
T1/CEPT
PCM TRANSCEIVER
R8071
ISDN/OM I
LLC
{
SCLK
2
EQUALIZER LINE AND 3
CLOCK RATE SELECT
TXOUTP
TXOUTN
RXINP
RXINN
TCLK
RCLK
CB
RPOS
RNEG
ESO
TPOS
TNEG
ES1
TX OUTPUTS
RXINPUTS
CENTER/BYPASS
ELASTIC STORE
}
ELS1·ELS3
EXCLK
ERROR STATUS
EXTERNAL CLOCK
LOOP/NORMAL OPERATION
LOOP
BPV
LOCAL/REMOTE (LOOP OPERATION) OR
MASTER/SLAVE (NORMAL OPERATION)
MODE
RESET
XTALA
TVCC
+5V
XTALB
RVCC
+5V
RGND
GND
CRYSTAL
{
GND - - - - TGND
BIPOLAR VIOLATION
RESET
Figure 1. R8069 LlU Interface Signals
AVCC
1
28
TCLK
SCLK
2
27
RCLK
EXCLK
3
26
ELS3
XTALA
4
XTALB
5
25
24
ELS2
ELS1
TXOUTP
6
23
CB
TGND
7
22
RGND
TVCC
8
21
RXINN
TXOUTN
9
20
RXINP
10
11
19
18
ES1
LOOP
MODE
12
17
RNEG
TPOS
13
16
RPOS
TNEG
14
15
BPV
RESET
ESO
28·PIN DIP
Figure 2. R8069 LlU Pin Assignments
6·25
•
Line Interface Unit (UU)
R8069
Table 1. R8069 Interface Signal Descriptions
Pin
I/O
RXINP, RXINN
Symbol
20,21
I
Receive Data Input P, Receive Data Input N. Receive bipolar data from transmission line.
A 1:1 transformer Is required on these input lines.
RPOS,RNEG
16,17
0
Receive Unipolar Positive, Receive Unipolar Negative. RPOS and RNEG are the out·
puts of the received data recovered from RXINP and RXINN AMI line pulses. RPOS and
RNEG have TTL levels and are In NRZ format. (These lines can be directly connected to
R8070's RPOS and RNEG inputs.) RPOS and RNEG are clocked out at the falling edge of
TCLK (when elastic store bypass is enabled) or RCLK (when elastic store bypass is
disabled).
RCLK
27
0
Recovered Clock. RCLK is the recovered clock output which is locked to the carrier frequency and phase of the incoming data.
EXCLK
3
I
External Clock. EXCLK Is a TTL level input. The clock frequency should be 1.544 MHz %32
ppm for T·l applications and 2.048 MHz ,.50 ppm for PCM30 applications.
CB
23
I
Center/Bypass Elastic Store. Elastic store is centered on the rising edge of CB. Elastic
store is bypassed when CB is high. (Minimum pulse width is one clock cycle.)
BPV
15
0
Bipolar Violation Detection. Whenever a bipolar violation on the input bus is detected, the
BPV generates a posHive pulse of one unH interval at the falling edge of TCLK (CB low) or
RCLK (CB high).
ESO, ESl
18,19
0
Error Status. The Error Status is continuously updated on the rising edge of TCLK.
Name/Function
ESO
ESl
0
0
0
1
1
0
1
1
AIS Detected. AIS is activated by detection of a string of 2316 ones
with no more than two zeros. AIS is deactivated when three or
more zeros are found after the AIS detection.
Loss of Signal. Activated when the input signal level drops
below 0.5 vo~s; deactivated when the input signal level rises
above 1.0 vo~s.
Elastic Buffer Limit. Indicates an overrun/underrun on the
elastic store. It will be negated when CB or RESET is activated.
Normal Operation.
TPOS,TNEG
13,14
I
Transmit Unipolar Positive, Transmit Unipolar Negative. TPOS and TNEG are the
"unipolar paired" input for transmitted data. TPOS and TNEG must have TTL levels and
must be in NRZ format. (rhese lines can be directly connected to R8070 TPOS and TNEG
outputs.) They are clocked in at the falling edge of TCLK. There are only three valid states
for TPOS/TNEG (10, 01,00); state 11 is not allowed.
TXOUTP,
TXOUTN
6,9
0
Transmit Data Output P, Transmit Data Output N. Transmit bipolar data to transmission
line. A 1 :2 step up transformer is needed at the output.
TCLK
28
0
Transmit CJock. TCLK is the transmitter clock output which is either the smoothed clock
provided through EXCLK, or the smoothed clock extracted from the input data when in the
slave mode. TPOS and TNEG are clocked in on the falling edge of TCLK. The receive data
is also clocked out on the falling edge of TCLK, except when in the elastic store bypass
mode (CB high). (rCLK output provides the proper clock signal to the R8070's and R8071 's
TCLK and/or RCLK.)
SCLK
2
0
System Clock. SCLK runs at two times the clock rate of TCLK, which is required by the
R8071.
ELS1·ELS3
24,25,
26
I
Equalizer Line and Clock Rate Select. Selectable strap inputs that allow selection of T·l
cable length equalization or the PCM30 line load impedance selection.
6·26
Line Interface Unit (lIU)
R8069
Table 1. R8069 Interface Signal Descriptions (Cont'd)
Pin
I/O
LOOP
11
I
Loop Operation Select. LOOP low selects normal operation (MODE selects master or
slave timing). LOOP high selects loop operation (MODE selects local or remote loop).
MODE
12
I
Mode Select. In normal operation (LOOP low), MODE low selects master timing and
MODE high selects slave timing. In loop operation (LOOP high), MODE low selects local
loop and MODE high selects remote loop.
RESET
10
I
Reset. Recenters the elastic store and trains the VCO to lock to EXCLK when RESET Is
high.
XTALA, XTALB
4,5
I
XTAL Input pins. An external parallel resonant 6.176 MHz or 8.192 MHz crystal is needed
for T-l or PCM30, respectively.
RVCC
1
I
Receive Power. +5V power supply for the receive section.
RGND
22
I
Receive Ground. Ground for the receive section.
TYCC
8
I
Transmit Power. +5V power supply for the transmit section.
TGND
7
I
Transmit Ground. Ground for the transmit section.
Symbol
Name/Function
conforms to the DSX-l pulse template for T-1 (Figure 4
and Table 3) and PCM30 (Figure 5).
FUNCTIONAL DESCRIPTION
The R8069 LlU contains both analog and digital circuitry
to independently process transmit and receive primary
rate voice or data information. Circuitry to provide local
loop, remote loop and master/slave timing is also included.
A simplified block diagram of the Rockwell R8069 Line Interface Unit (LlU) is depicted in Figure 3.
RECEIVE SECTION
On the receive side, bipolar input data (RXINN and
RXINP) is converted to a unipolar signal from which a
clock can be extracted. A phase locked loop circuit (PLL1),
which is based on an internal oscillator Circuit, extracts the
clock from the incoming data. The PLL1 clock recovery circuit derives the Recovered Clock (RCLK) from this
unipolar Signal, unless Loss of Signal occurs. Should Loss
of Signal occur, PLL1 derives RCLK from the External
Clock (EXCLK) input.
TRANSMIT SECTION
Transmit data (TPOS and TNEG) are provided to the
R8069 from the R8070 for the generation of Alternate Mark
Inversion (AMI) data on output pins TXOUTP and
TXOUTN. The input data are provided to a transmit compromise line equalizer for pulse shaping and conditioning.
The equalizer is capable of equalizing for up to 655 feet of
ABAM cable (22-gauge plastic insulated cable with
characteristics specified in Appendix B of the AT&T Technical Reference Number 34, Sept 1983). The recommended cable is AT&T part no. 606-6/22 R6900.
Depending on the loop and timing mode selection, phase
locked loop circuit PLL2 smooths the clock signal
(1.544 MHz or 2.048 MHz) provided by the EXCLK input
or the RCLK output of PLL1. Jitter-free TCLK and SCLK
clocks are then generated by PLL2. PLL2 is based on the
crystal oscillator input at XTALA and XTALB. TCLK represents the base clock frequency (1.544 MHz or 2.048 MHz)
and SCLK is twice the base frequency. TCLK and SCLK
are used as transmit clocks by the R8070 and R8071,
respectively.
Three encoded inputs, ELS1-ELS3, allow selection of
cable length equalization and clock rates (Table 2).
Equalization for cable lengths of 0-660 feet in increments
of 110 feet are selectable for a T-1 line. Loading impedance of 75 Q (for coaxial cable) or 120 Q (for twistedpair cable) is selectable for a PCM30 line.
ELS3
The equalized data are then provided to a line driver. In
T-1 environment with a modulation rate of 1.544 Mbps, this
driver can drive a twisted pair cable up to 655 feet in
length, and still meet the Isolated Pulse Template at the
end of the cable (at DSX-1) as specified by AT&T Technical Advisory No. 34. In PCM30 mode, the LlU provides a
pulse shape which, when measured at the output of the
transmit transformer, meets the requirements of CCITT
Recommendation G.703. The typical output pulse shape
L
L
L
L
H
H
H
H
Table2. ELS1 - ELS3 E nco d'1n9.
Cable LengttV
Clock Rate·
ELS1
Line Impedance
ELS2
o -110ft
T-l
L
L
110-220ft
T-l
L
H
220-330ft
T-l
H
L
H
330-440ft
T-l
H
440- 550ft
T-l
L
L
550 - 660ft
T-l
L
H
H
L
1200
PCM30
750
PCM30
H
H
* T-l = 1.544 MHz; PCM30 = 2.048 MHz
6-27
iii
I
::D
~
en
ELS1-ELS3
"
/
,1-
3
CO
\.
~
LOOPBACK
CIRCUIT
(
I
--""
:;5
TX
DRIVER
TX EQUALIZER
1---+
/
~
V
Tr
1}
L
.K
"TI
,g"
c
"'/
.J
iil
~
r
:0
co
0
en
CO
C
c:
9'
I\)
(Xl
!l
0"
::s
e!to
0"
n
~
~
•
""-
<
~
~
LOOP TEST
AND TIMING
CONTROLLER
J
J
{
;
C
iii"
CE!
DI
3
r-
CLOCK
RECOVERY
PLLl
J
"TI
C
::s
TCLK/SCLK
PLL2
LOOPBACK
CIRCUIT
;
-
,
<
,.
J
~
5OO~s.
Error Status· TCLK Relation Waveforms
6-40
R8069
Line Interface Unit (LlU)
SWITCHING CHARACTERISTICS - WAVEFORMS (CONT'D)
TCLK/RCLK
RPOS
RNEG
BPV
_ _ _ _·'tt
Receive Timing Waveforms
TPOS
•
TNEG
TCLK
TXOUTP - - - - + \
TXOUTN
Transmit Timing Waveforms
6-41
Line Interface Unit (LlU)
R8069
SWITCHING CHARACTERISTICS - TIMING
(Vee = 5.0 Vdc ± 5%, Vss = 0, Vdc TA=
o·c to 70·C, unless otherwise specified)
Min.
Max.
Units
Notes
tCR, tCF
tSCR tsCF
-
20
10
ns
ns
1
2
Rise and Fall time,
TPOS,TNEG RPOS RNEG,BPV, ESO, ES1
tPR, tpF
-
60
ns
Delay Time
TCLK (or RCLK) to RPOS, RNEG, BPV
SCLKtoTCLK
TCLK to Error Status VALID
to
tSTD
tesD
0
0
0
80
50
80
ns
ns
ns
RESET Pulse Width
tRMIN
244
-
ns
Parameter
Rise and Fall time
RCLK, TCLK
SCLK
Symbol
T-1
Pulse Width,
Pulse Width,
Pulse Width,
Pulse Width
TCLK or RCLK Low
TCLK or RCLK High
SCLK Low
SCLK High
tPWL
tPWH
tswL
tSWH
315
315
155
155
335
335
165
165
ns
ns
ns
ns
3
3
4
4
PCM30
Pulse Width,
Pulse Width,
Pulse Width,
Pulse Width,
TCLK or RCLK Low
TCLK or RCLK High
SCLK or SCLK Low
SCLK or SCLK High
tPWL
tPWH
tswL
tswH
235
235
115
115
255
255
135
135
ns
ns
ns
ns
3
3
4
4
Notes:
1. TCLK and RCLK rise and fail times are defined as TIL levels from 0.4 Vdc to 2.4 Vdc at ILOAD = 1.6 rnA and CL = 50 pF.
2. SCLK rise and fail times are defined as TIL levels from 0.4 Vdc to 2.4 Vdc at ILOAD = 1.6 mA and CL = 30 pF.
3. The summation of tpWL and tPWH must meet the frequency specifications listed in the Interface Requirements table.
4. The summation of tSWL and tSWH must be exactly one-half the summation oftPWL and tPWH.
6-42
Line Interface Unit (LlU)
R8069
INTERFACE REQUIREMENTS
Characteristic
Operation
Value
4-wire full-duplex on primary rate lines (T-1 or PCM30)
Transmn Pulse Requirements
Transmit level
1.544 Mbps (T-1)
2.048 Mbps (PCM30)
Transmit Pulse width
1.544 Mbps (AT&T & CCITT)
2.048 Mbps (CCITT)
Transmn Clock Accuracy
AT&T
CCITT
CCITT
Receive Clock Accuracy
AT&T
CCITT
CCITT
I nput Jitter Tolerance
3V (nominal). Fits the pulse shape templates in DSX-1 Interconnection
Specification (T-1) and CCITT Recommendation G.703
3V (nominal). Fits the pulse shape templates in CCITT Recommendation G.703
324 ns (nominal)
244 ns (nominal)
1.544 Mbps %32 ppm
1.544 Mbps %50 ppm
2.048 Mbps ±50 ppm
1.544 Mbps %130 ppm
1.544 Mbps %50 ppm
2.048 Mbps %50 ppm
Receiver Sensitivity
28 Ulpp
10 db below DSX-1 or G. 703 specification
Diagnostics
On-chip loop test circuit (local and remote)
Transmitter Transformer Test load Impedance
1.544 Mbps (AT&T & CCITT)
2.048 Mbps (CCITT)
100 Q resistive
120 Q /75 Q resistive
I nterface to R8070/R8071
level
Clock timing
Data from R8070
Data to R8070
Clocks to R8070/R8071
Recovered Clock
Transmn clock
System Clock
CMOS/TTL compatible
Meets R8070/R8071 timing specifications
Unipolar data to be transmitted on primary rate lines (TPOS and TNEG)
Unipolar data received from primary rate lines (RPOS and RNEG)
RClK
TClK
SClK (= 2 x TClK)
•
6-43
R8069
Line Interface Unit (LlU)
*NOTE: Stresses above those listed may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other
conditions above those indicated in the other sections of
this document is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
ABSOLUTE MAXIMUM RATINGS*
Parameter
Symbol
Supply Voltage
Input Voltage
Operating Temperature
Storage Temperature
Vee
VIN
TA
TSTG
Value
Units
-0.3 to +7.0
Vdc
-0.3 to Vee + 0.3 Vdc
·C
Oto+ 70
·C
-55 to + 150
ELECTRICAL CHARACTERISTICS1
~cc
=5.0 Vde :1:5%, Vss =0 Vdc, TA =O'C to 70'C unless otherwise specified)
Parameter
Symbol
Min.
Typ.
Max.
Units
Input Low Voltage
VIL
-0.3
+0.8
V
Input High Voltage
VIH
+2.0
VCC+0.3
V
Output Low Voltage
VOL
-
-
0.4
V
ILOAC = 1.6 mA
VOH
2.4
-
-
-
ILOAC = -100!IA
-
3.5
-
-
-
IOL
+1.6
-
mA
VOL=0.4V
Output High Current
10H
-100
-
!IA
VOH =3.5V
Input Capacitance
CIN
-
-
5
pF
Power Dissipation2
T-l Mode
Random Data
330ft.
655ft.
All Ones
330ft.
655ft.
PCM3OMode
Random Data
All Ones
Po
Power Consumption2
T-l Mode
Random Data
330ft.
655ft.
All Ones
330ft.
655ft.
PCM30Mode
Random Data
All Ones
Pc
Test Condition
Output High Voltage
TIL
CMOS
Output Low Current
mW
-
-
270
280
305
360
-
350
410
430
480
-
240
310
280
360
-
mW
-
300
340
375
410
-
420
SOO
500
570
260
350
300
400
-
-
Notes: 1. Applies to all signals except TXOUTP, TXOUTN, RXINP and RXINN.
2. Power Consumption = Power dissipated
as heat and power used to drive cable.
6-44
ILOAD
= -IOO!IA
Line Interface Unit (UU)
R8069
RECOMMENDED CRYSTAL SPECIFICATION
Parameter
Value
Frequency @ 25'C ±2'C
T-1
PCM30
6.176 MHz
8.192 MHz
Frequency Tolerance @ 25'C
±0.001%
Temperature Stability (O"C - 70'C)
±0.003%
Load CapaCitance
13.5 pF
Equivalent Series resistance (Max.)
50n
Motional Capacitance (Min.)
T-1 (@ 6.176 MHz)
PCM30 (@8.192MHz)
0.022 pF
0.025 pF
Recommended Aging
2 ppm/year
Shunt Capacitance (Max.)
T-1 (@6.176MHz)
PCM30 (@8.192MHz)
6 pF
6 pF
Mode of Operation
Fundamental
Drive Level (Max.)
2.5mW
Resonance Mode
Parallel
PACKAGE DIMENSIONS
MILLIMETERS
MIN.
MAX.
MIN.
A
36.32
37.34
1.430
MAX.
1.470
B
13.46
13.97
0.530
0.550
e
3.56
5.08
0.140
0.200
0
0.38
0.53
0.015
0.021
F
1.02
1.52
0.040
0.060
G
H
2.54 BSe
1.65
0.100 BSe
2.16
0.065
0.085
J
0.20
0.30
0.008
0.012
K
3.05
3.56
0.120
0.140
L
M
N
6-45
INCHES
DIM.
15.24 BSe
7"
10"
0.51
1.02
0600 BSe
7"
10'
0.020
0.040
II
R8069A
'1'
Rockwell
R8069A
Enhanced T-1/PCM-30
Line Interface Unit (LlU)
INTRODUCTION
FEATURES
The Rockwell R8069A Line Interface Unit (L/U) is a single
chip CMOS device that interfaces the Rockwell R8070
T1/CEPT PCM Transceiver to the physical T-1/CEPT
PCM30 transmission medium.
•
Compatible with T-1 (1.544 Mbit/s) and PCM30 (2.048
Mbit/s)
•
Selectable T-1 and PCM30 clock rates
•
Implements ISDN primary rate interface
The R8069A L/U device contains analog and digital circuits which are based on CMOS technology to implement
the line interface function required in ISDN primary rate
transmission. The R8069A provides capabilities for 4-wire
transmission of image, voice, or data signals; clock extraction; line equalization; bipolar violation detection; jitter accommodation; and AIS (Blue Alarm) generation and
detection. In addition, the device operates at 1.544 or
2.048 Mbit/s and meets pulse shape and jitter requirements specified by T-1 or PCM30 standards, respectively.
•
Directly compatible with Rockwell R8070 T-1/CEPT
PCM Transceiver and R8071 ISDN/DMI Link Layer
Controller devices
•
Independent transmit and receive sections
The R8069A is ideally suited for image, voice, or data
transmission required in ISDN primary rate applications.
The device is highly integrated and requires virtually no external components.
Internal L/U functions allow system designers to minimize their development cost and easily implement a
T-1/PCM30 phYSical interface to primary rate lines without
concern about most of the complex details normally associated with such a design. The R8069A also provides a
high level of integration which increases system reliability,
reduces space and achieves higher levels of performance
and quality.
NEW FEATURES INCLUDE:
•
•
44-Bit Receive Elastic Store for Up to 40 UI Jitter Accommodation
Exceeds Latest CEPT Requirement
•
Phase locked loop for loop timing applications
•
Satisfies T-1 (AT&T Technical AdviSOry No. 34) and
PCM30 (CCITT G.703)
•
Provides line equalization for up to 655 feet of 22gauge plastic insulated (ABAM) cable for T-1
•
Transmission/reception of data for up to 1600 feet of
cable
•
Accommodates pulse shape requirements for 75
and 120 Q lines in PCM30 application
•
Meets jitter requirements specified by T-1 (AT&T Publication 62411, Oct. 1985) and PCM30 (CCITT G.823)
•
Intrinsic jitter under 0.05 UI
•
Jitter attenuation starts at 2 Hz
•
Jitter tolerance above 0.4 UI for jitter frequency from
20 kHz to 100 kHz
•
8-bit TX elastic store for jitter control and attenuation
•
44-bit RX elastic store for jitter control and attenuation
•
Provision to bypass RX elastic store
•
Master/slave timing option
•
Local and remote loop operation
•
AIS (Blue Alarm) generation and detection
•
Transmit Elastic Store for Alignment of Transmit Data
with System Clock
•
Bipolar violation detector
•
Standby Mode for Transmitter
•
EXCLK activity detector
•
Mode Independent Loopbacks
•
On-chip line drivers
•
Self Generation of Line Rate Clock for Elimination of
External Clock Generator or Fall Back if External Clock
Lost
•
Analog CMOS technology
•
CMOS/TTL compatible inputs and outputs
•
Automatic RCLK Source Selection
•
Improved Pulse Shape for Added Margin from
Template
Document No. 29300N52
•
Operates from a single +5V supply
•
28-pin plastic dual in-line package (DIP)
Product Preview
6-46
Q
Order No. 352
January 1989
R8070
'1'
R8070
T1/CEPT PCM Transceiver
Rockwell
INTRODUCTION
FEATURES
The Rockwell R8070 T1/CEPT PCM Transceiver is a monolithic
silicon gate CMOS device designed to implement PCM transmitter and receiver functions applied in primary-rate digital carrier
systems worldwide. Both the transmitter and receiver contain
appropriate circuitry for synchronization, channel monitoring and
signaling extraction.
• Implements primary-rate PCM formats:
- T-carrier T1 (04), T1 (ESF) and 1/2 T1C synchronous
- CEPT PCM-3D
• Meets CCITT G.732 (2.048 Mbps), G.733 (1.544 Mbps) and
applicable sections of G.7D3
• Supports AT&T technical advisories on Extended Superframe
Format and Clear Channel operation with B8ZS coding
The R8D70 supports CCITT recommendations G.732, G.733 and
applicable sections of G.7D3, as well as AT&T technical
advisories on clear channel capability and Extended Superframe
Format (ESF). This device provides the interfaces between the
multiplexed digital signals of the subscriber loop and the PCM
highway in a digital telephone switching system. The device
operates from a single power supply of 5 volts and a sampling
clock of 1.544 to 2.048 MHz, depending on the mode of
operation.
• Supports SLC-96 applications
• Single chip receiver and transmitter
• Selectable serial or parallel data interface
• Reframe time less than 10 ms
• Interfaces directly with Rockwell R8D71 ISON/OMI Link
Controller
• Available in 64-pin quad in-line (QUIP) and 68-pin plastic
leaded chip carrier (PLCC) packages
Packaged in a 64-pin QUIP (quad in-line package) or a 68-pin
PLCC (plastic leaded chip carrier), the R8D70 requires less realestate and provides added flexibility in system integration and
manufacturing. With eleven modes of operation and a serial or
parallel data interface, the R8D7D finds worldwide application
in diverse areas of voice/data communications.
LINE
INTERFACE
UNIT
(LIU)
T1/CEPT
PHYSICAL
INTERFACE
• Operates from a single + 5 Vdc supply
• CMOSmL compatible inputs and outputs
• Low power CMOS technology
R8070
MICROPROCESSOR-BASED OR
NON-MICROPROCESSOR-BASED
EQUIPMENT
T1/CEPT
PCM
TRANSCEIVER
PARALLEL
OR
SERIAL
INTERFACE
T1/CEPT
SERIAL
INTERFACE
R8070 Functional Interface
Document No. 29300N14
Data Sheet
6-47
Order No. 314
Rev. 1, June 1986
II
T1/CEPT PCM Transceiver
R8070
ORDERING INFORMATION
For inc.reased flexibility and lower e'Xternal part count (no
parallel/senal conversion required), a parallel (PIS high) or serial
(PIS low) interface may be selected. The parallel interface may
be chosen to match a byte-wide microprocessor bus; the serial
interface may be preferred to match an existing interface.
Part Number:
RB07D
L
T
I
Temperature
~
Blank =
DOC to + 70°C
E = -40°C to +B5°C
DATA SHEET STRUCTURE
The Ra070 pin assignment, general interface and functional
block diagrams that apply to both Tl and CEPT formats are
shown In the front of the data sheet. The electncal and switching
characteristics and packaging information are Included in a short
common section at the end of this document.
Package
P = 64-Pln Plastic QUIP
S = 64-P,n Cerpac QUIP
J = 68-PIn Plastic Leaded Chip
Carner (PLCC)
JC = 68-Pln Ceramic Leaded
Chip Carner (CLCC)
The PCM formats, the Ra070 Interface signals and Ra070 operation in Tl and CEPT environments are described separately to
simplify the use of this data sheet. These two major sections
are structured similarly and include four subsections:
R8070 OPERATING MODE AND
INTERFACE SELECTION
• The Overview provides an Introduction to PCM formats and
terminology, and a gUide to mode selection.
The Ra070 has eleven modes of operation covering Tl (Dl D,
D2, D3 and D4), Tl (Extended Superframe Format), TIC, and
CEPT PCM-30 formats. Nine modes support T1 formats and two
.modes support CEPT formats. The mode is selected using
Ml-M4 to match the required PCM format. Modes may be
chosen with or without signaling, and with a choice of zero
suppression technique.
PSI2
PSII
TFSYNC
TMSYNC
IA
IB
10
TYEL
TCLK
TMAX
Ml
M2
M3
M4
TIDLE
TLOOP
TNEG
TPOS
TNRZ
OJ
OH
OE
PS09
PS010
PSOll
PS012
PS013
RVLL
00
OC
OB
PIS
I
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Vcc
PSI3
PSI4
PSIS
PSI6
PSI7
PSI8
IC
RCLK
RPOS
RNEG
RIDLE
RMW
RYEL
RSER
PSOI
PS02
PS03
PS04
PS05
PS06
PS07
PS08
RSRCH
RMRST
PUP
RRED
RSYNC
OG
OF
OA
Vss
• The Functional Description gives an overView of the Ra070
operation and groups the signals associated with each aspect
of PCM transceiver design: channel data, signaling, alarm
indication, error reporting, timing and synchronization.
Uu
Zz
~~:::~o~~!!?!!!:::~
~~Q~~~~~~~~~~~~~~
Ld
TCLK
TMAX
Ml
M2
M3
M4
TIDLE
TLOOP
TNEG
TPOS
TNRZ
OJ
OH
OE
PS09
PS010
NC
0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
PIN 1
INDICATOR
NC
RCLK
RPOS
RNEG
RIDLE
RMW
RYEL
RSER
PSOI
PS02
PS03
PS04
PS05
PS06
PS07
PS08
RSRCH
-NM~QU~0·~~~UQ~~U
oooSooo~~ooozw~~z
~~~~
~~~~
~
R8070J
R8070P and R8070S
R8070 Pin Assignments
6-48
~
NC= No Internal Connection
R8070
T1/CEPT PCM Transceiver
• The Interface Description is arranged so that, having chosen
an operating mode (PCM format) and data interface (parallel
or serial), the designer can clearly identify the signals available in that configuration. Pin assignments and pin definitions are separately listed with applicable Interface and mode.
Within each table, the R8070 signals are arranged in three
groups:
1. Dedicated signals whose function is fixed.
2. Parallel/serial interface dependent signals.
3. Framing mode dependent signals.
• The Waveforms show major signaling or frame level signals
fOllowed by channel/bit level signals.
For more detailed information, see the R8070 T1/CEPT PCM
Transceiver DeSigner's Guide (Order No. 313).
R8070 Operating Mode Selection and Characteristics
Mode
Data Rate
(Mbps)
Mode Select Lines
Signaling
Bits/Frame
Frames/Multiframe
Yes
Yes
No
No
Zero Suppression
M2
M3
M4
B8ZS
B7
B8ZS
B7
1
0
1
0
0
0
1
1
1
1
1
1
0
0
0
0
TI (D4)
Extended
Superframe
Format (ESF)
1935
1935
193N
193N
1.544
193
12
12
4
4
193E
193E
193F
1.544
193
24
24
24
Yes
Yes
SpeCial
B8ZS
B7
B8ZS
1
0
1
1
1
0
1
1
1
1
1
1
1975
197N
1.576
197
12
4
Yes
No
Transparent
Transparent
1
1
0
1
0
0
0
256
16
2
Yes
No
HDB3
HDB3
0
0
0
1
0
0
0
0
256S
256N
2.048
Notes: B7:
Bit 7 is forced to a 1 (stuffed) on an otherwise all zero channel.
B8ZS: Bipolar 8-zero substitution.
FRAMING MODE SELECT
0
TIC
CEPT
PCM-30
HDB3:
High DenSity Bipolar 3-zero maximum.
Transparent: No zero suppression or substituMn.
Ml-M4
FRAMING MODE }
DEPENDENT INPUTS
IA-ID
PARALLEL/SERIAL
INTERFACE SELECT
PARALLEL/SERIAL INTERFACE }
DEPENDENT INPUTS
PCM Format
M1
9
OA-OJ
13
PS01-PSOI3
{
FRAMING MODE
DEPENDENT OUTPUTS
PIS
PS
It-PSIS
{
PARALLEL/SERIAL INTERFACE
DEPENDENT OUTPUTS
RSER
RSYNC
RVLL
RB070
RYEL
RRED
TNRZ
TPOS
TNEG
TMAX
R8070 Interface Signals -
6-49
General
}
DEDICATED
RECEIVE
OUTPUTS
}
DEDICATED
TRANSMIT
OUTPUTS
•
T1/CEPT PCM Transceiver
R8070
R8070 OVERVIEW (Cont'd)
PIS MODE
SELECT
FRAME MODE
SE LECT
•
•
•
•
DISPATCHING
CIRCUIT
SIGNALING
IDLE CODE
ALARM
BIT CONTROL
GENERATOR
~
TRANSMIT
COUNTER
LOGIC
TIMING
SELECT
~
TIMING
TRANSMIT
OUTPUTS
TRANSMIT CLOCK
t
PARALLEL
INPUT
DATA
"~
S-BIT
LATCH
I
I
OUTPUT
REGISTER
I
SERIAL TRANSMIT INPUT
----------- f - - - - - - - l
CHANNEL
TRANSLATOR
Transmit Section
~
I
SINGLE AND
PAIRED UNIPOLAR
OUTPUTS
I
I
r--t--
SEQUENCE CODE
I
r---------------------------~
I RCV
CLOCK
J
I
I
RECEI VEDl
DATA
~
RECEIVED
DATA
INPUT
REGISTER
~~
RIDLE
SIP
CONVERTER
--
RMW
RECEIVE
SERIAL DATA
~
• M/F SYNC
• SIGNALING
• DATA LINK
• ALARM
EXTRACTION
CIRCUIT
+
t
~
PIS MODE SELECT
FRAME FORMAT
MODE SELECT
RECEIVED
PARALLEL
DATA
RECEIVE
COUNTER
CONTROL
LOGIC
t
RECEIVE
DISPATCHING
CIRCUITRY
Receive Section
R8070 Functional Block Diagram
6-50
RECEIVER
STATUS
SIGNALS
SYNCHRONIZER
LOGIC
r----
EXTERNAL
SYNC SIGNALS
,.
010/02
CHANNEL
TRANSLATOR
SYNC STATUS
r----
SEQUENCE
CODE
FRAMING MODE
OUTPUT SIGNALS
R8070
T1/CEPT PCM Transceiver
T10VERVIEW
This structure of frames and multlframes is defined by the F-bit
pattern. The F-bit is designated alternately as an Ft bit (terminal
framing bit) or Fs bit (signaling framing bit). The Ft bit carries
a pattern of alternating Os and 1s (101010) that defines the frame
boundaries so that one channel may be distinguished from
another. The Fs bit carries a pattern of 001110 and defines the
multiframe boundaries so that one frame may be distinguished
from another, in particular, frame 6 and frame 12 may be identified for the recovery of signaling bits.
T1 is a PCM format for time-division multiplexing 24 voice
(telephone) or data circuits onto a single transmission path. This
path is normally a dual twisted-pair cable with digital repeaters
at intervals of 6000 feet.
T1 presently has two major formats; the older D4 format and
the emerging Extended Superframe Format (ESF). The major
differences between them are in the signaling format and the
definition of the F-bit pattern. Both formats, as well as their
derivatives, are supported by the R8070.
Alarms and Error Conditions. In addition to voice and signaling data, T1 defines several alarm and error conditions that must
be monitored and reported. The principal alarms are:
In addition, there is a hierarchy of PCM formats within the
T-carrier system that defines further time-division multiplexing
of multiple T1 lines, to produce T1 C (two T1 lines), T2 (four T1
lines), and so on. These higher level formats are used for longhaul transmission via satellite or microwave links. The R8070
provides specific support of the Tl C format, in addition to T1.
1. Red Alarm
2. Yellow Alarm
A Red Alarm is produced by a receiver to indicate that it has
lost frame alignment. A Yellow Alarm is returned to the transmitting terminal to report a loss of frame alignment at the
receiving terminal. Normally, a T1 lerminal will use the receiver's
Red Alarm to request that a Yellow Alarm be transmitted.
T1 FORMATS
Basic T1 (04)
The principal error conditions are:
Prior to transmission, each voice circuit is sampled at 8 kHz using
an 8-bit ,..-Iaw companding analog-to-digital converter. The
resulting 64 kbps (8 bits x 8 kHz) signal is time-division multiplexed with 23 other sampled channels to produce a frame of
192 bits (24 channels x 8 bits). An extra bit (193rd bit or F-bit)
is inserted at the beginning of each frame to define the frame
boundaries. Since each voice circuit is sampled at 8 kHz, the
frame rate is 125 /ls. To transmit 193 bits in 125 /ls requires a
bit rate of 1.544 Mbps, hence the standard T1 clock frequency
of 1.544 MHz.
1.
2.
3.
4.
Loss of carrier
Bipolar violation
Fs bit error
Ft bit error
A loss of carrier means that received data was zero for 31 consecutive bits. A bipolar violation is a failure to meet the Alternate Mark Inversion (AMI) line code of T1. AMI dictates that 1s
(marks) are transmitted alternately as positive or negative pulses;
zeros are transmitted as zero volts.
Signaling Data. Signaling data, such as on-hook and off-hook
conditions, dialing digits, call progress, etc., associated with each
voice circuit is transmitted within the voice channel itself. This
is known as associative signaling, as opposed to common
channel signaling, where a single (common) channel is dedicated
to carry the signaling data for all the voice circuits within a T1
link, for example.
Clock Recovery. In order to guarantee adequate clock recovery
from the received data, a minimum "ones density" must be
observed. One of two methods may be used; B8ZS or bit-7
stuffing. B8ZS represents a group of 8 zeros by a predefined code
that includes intentional bipolar violations. At the receiver, the
code is recognized and the original 8 zeros are restored. The
older method of bit-7 stuffing forces bit 7 to a 1 in an otherwise
all zero channel. This forced 1 is not coded as a bipolar violation and the original data cannot be recovered by the receiver.
The signaling data, known as A- and B-bits, is conveyed in the
8th bit position (least significant bit) of each channel within
frames 6 (A-bit) and 12 (B-bit). This signaling method is also
known as "robbed-bit" signaling since the A- and B-bits actually
displace the original LSB of the voice signal, causing a slight,
but insignificant, error in the received signal.
The R8070 supports all major requirements of the T1 system,
including channel data recovery, signaling, alarm indication, error
reporting and both methods of zero suppression to satisfy the
ones density requirement.
The requirement for associated signaling in frames 6 and 12 dictates that the frames be distinguishable. This leads to a
multiframe structure consisting of 12 frames.
Extended Superframe Format (ESF)
In Extended Superframe Format, the multiframe structure is
extended to 24 frames from the 12 frames used in D4. The frame
and channel structure is the same in both formats. Robbed-bit
signaling is accommodated in frame 6 (A-bit), frame 12 (B-bit),
frame 18 (C-bit), and frame 24 (D-bit).
To recap, the PCM structure consists of: a multiframe of
12 frames; a frame of 24 channels, plus an F-bit; and 8 bits to
per channel, where a channel is equivalent to one voice circuit
or one 64 kbps data circuit.
6-51
•
T1/CEPT PCM Transceiver
R8070
T1 OVERVIEW (Cont'd)
193N Mode. The 193N mode Implements standard T1 PCM
format at 1.544 Mbps With 4 frames per multiframe. Robbed-bit
Signaling is omitted. There are 193 bits per frame.
The F-bit pattern of ESF contains three functions:
1. Framing Pattern Sequence (FPS) which defines the frame
and multiframe boundaries.
The transmitter generates the Ft pattern but not the Fs pattern,
which may be externally supplied. The receiver does not use
the Fs pattern for synchronization but reports the Fs data
2. Facility Data Link (FDL) which allows data such as error perlink
formance to be passed within the
n
3. Cyclic Redundancy Check (CRC) which allows error performance to be mOnitored and enhances the reliability of the
receiver's framing algOrithm
This mode may be used In point-to-polnt commUnications where
no robbed-bit Signaling is required and the standard Fs pattern
cannot be used If the standard Fs pattern can be used, then
1935 mode prOVides more reliable synchrOnization.
The RB070 supports all major reqUirements of ESF, Including
channel data recovery, Signaling, alarm Indication, error reportIng and both methods of zero suppression to satisfy the ones
density reqUirement.
To satiSfy the "ones density" reqUIrement, either BBZS or bit-7
stuffing techniques can be selected. Zero suppression may be
disabled to allow transparent operation.
T1C Mode 1 Synchronous
Extended Superframe Format T1 Modes
The frame structure of n C IS the same as basic T1 but 4 extra
(link) bits are included In each of the two multiplexed T1 lines
at the end of channel 6, 12, 1B and 24 (where the link bit follows
the F-bit). The bit rate of T1 C IS 3.152 Mbps. Two RB070s can
be used, each clocked at 1.576 MHz, to configure a T1C
multiplexer/demultiplexer.
193E Mode. The 193E mode Implements the Extended Superframe Format of T1 at 1.544 Mbps With 24 frames per multiframe,
sometimes referred to as ESF or Fe. A, B, C and D robbed-bit
Signaling is Implemented. There are 193 bits per frame.
The transmitter generates the Framing Pattern Sequence (FPS),
computes the Cyclic Redundancy Check (CRC) checksum, and
accepts the Facility Data Link (FDL) bitS, then combines them
Into the F-blt stream. The receiver recovers the FPS to establish
framing, checks the CRC against the data (reporting any errors),
and presents the FDL data bits.
Summary
The three major T1 formats supported by RB070 are:
Format
Modes
1. Basic T1 (D4)
1935, 193N
2. Extended Superframe Format (ESF)
193E,193F
3. T1C Mode 1 Synchronous
1975, 197N
To satisfy the "ones density" requirement, either BBZS or bit-7
stuffing techniques can be selected. Zero suppression may be
disabled to allow transparent operation.
193F Mode. The 193F mode is Identical to 193E mode, but
robbed-bit signaling IS omitted. This mode is convenient for common channel Signaling, and some additional timing signals are
prOVided for thiS purpose. There are 193 bits per frame.
T1 MODES DESCRIPTION
The RB070 T1 ol1erating mode IS selected by configuring the four
encoded Mode Select input lines (M1-M4) to one of nine
T1 modes (see T1 Mode Selection Table).
The zero suppression technique IS pre-selected as BSZS but may
be disabled to allow transparent operation.
Standard T1 (04) Modes
T1C Modes
1935 Mode. The 1935 mode implements the standard T1 PCM
format at 1.544 Mbps with 12 frames per multlframe, sometimes
referred to as D4 (channel bank designation). A and B robbedbit signaling is included. The pseudo-random channel numbering
of D1 D and D2 IS supported, as well as the sequential numbering
of D3 and D4. There are 193 bits per frame.
1975 Mode. The 1975 mode implements one-half of the T1C
PCM format at 1.576 Mbps With 12 frames per multiframe. Two
RB070s can be used with additional logic to provide T1 C, mode
1 synchronous, multiplex and demultiplex functions. A and B
robbed-bit Signaling is supported. 1975 framing is identical to
that of 1935, but 4 link bits per frame are added. There are
197 bits per frame
The Ft and Fs bit patterns are generated by the RB070 transmitter and recovered by the receiver. The Fs pattern IS included
in the receiver synchronization algorithm for improved immUnity
against Ft-imitatlng signals such as digital milliwatt. Robbed-bit
Signaling can be disabled to allow the use of the 1935 mode
in nonsignaling applications and thus retain Its superior framing
properties.
No zero suppression IS used In 1975 (transparent).
nc
197N Mode. The 197N mode implements one-half of the
PCM format at 1.576 Mbps with 4 frames per multiframe. Two
RB070s can be used with additional logiC to provide
mode
1 synchronous, multiplex and demultiplex functions. Robbedbit signaling is omitted. 197N framing is identical to that of 193N,
but 4 link bits per frame are added. There are 197 bits per frame.
nc,
To satisfy the "ones density" requirement, either BBZS or blt-7
stuffing techniques can be selected. Zero suppression may be
disabled to allow transparent operation.
No zero suppression is used in 197N (transparent).
6-52
R8070
T1/CEPT PCM Transceiver
T1 OVERVIEW (Cont'd)
8 BITS/CHANNEL
_
FRAMES OTHER THAN 6 AND 12
-
FRAME 6j BIT 8 CONVEYS
...L--==--=:,.J- FRAME 12
......:::-_..L.-_ _-'-_ _-1._ _--1_ _--II-_ _.l-_ _
SIGNALING INFORMATION'
24 CHANNELS/FRAME
FRAME
=
193 BITS
MULTI FRAME'
NOTES 1: A multllrame has 12 frames (04) or 24 frame. (ESF)
2: In addillon, ESF ha. a Cobilin frame 18 and a Oobilin frame 24.
T1 PCM Format
T·Carrier Hierarchy
F·blt Assignment-Extended Superframe Format
Digital
Signal
Number
Number
of Voice
Circuits
Bit Rate
(Mbps)
OS-l
OS-lC
OS-2
OS-3
OS-4
24
48
96
672
4032
1.544
3.152
6.312
44.736
274.176
F·bit Assignment-D4 Format
Frame
Number
Bit
Number
1
2
3
0
193
386
579
772
965
1158
1351
1544
1737
1930
2123
4
5
6
7
8
9
10
11
12
F·Bit
Fs
-
0
0
1
1
1
0
Ft
1
0
1
0
1
0
-
ESF
Frame
Number
ESF
Bit
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
0
193
386
579
772
965
1158
1351
1544
1737
1930
2123
2316
2509
2702
2895
3088
3281
3474
3667
3860
4053
4246
4439
F·Bit
Assignment
FPS
FDL
-
m
0
0
1
0
-
m
m
m
m
m
m
m
m
m
1
-
-
m
-
1
-
m
-
CRC
-
CBl
CB2
-
-
CB3
CB4
CBS
-
-
CB6
FP8--Framing Pattern Sequence (... 001011 ... )
FOL-4 kbps Facility Data Link (message bits m)
CRC-CRC-6 Cyclic Redundancy Check (check bits CB1-CB6)
Fs = Signaling Framing (Sequence ... 001110 ...)
Fl=Terminal Framing (Sequence ... 101010 ...)
6·53
T1/CEPT PCM Transceiver
R8070
Idle Code. Idle code (01111111) may be substituted in place of
the normal channel data, on a channel-by-channel basis, using
TIDLE.
T1 FUNCTIONAL DESCRIPTION
TRANSMIT SECTION
The transmij section of the R8070 provides the data formatting,
signaling and alarm indication fUnctions required for PCM
transmission according to CCITT G.733 and applicable sections
of G. 703. The AT&T technical advisories on Clear Channel and
Extended Superframe Format are also supported.
B8ZS Encoding and B7 Stuffing. BSZS encoding is handled
automatically by the R8070. The entire data stream, including
F (and L) bits, is scanned for an occurrence of 8 consecutive
zeros. Any such occurrence is replaced by the appropriate BSZS
code. The BSZS encoder may be disabled by connecting RPOS
to RNEG (and using an NRZ form of input data). This invokes
the transparent mode where zeros are transmitted as zeros,
regardless of the 1s density. This may be used for testing or for
systems that guarantee 1s density by other means. BSZS
encoding applies only to the TPOS and TNEG outputs; TNRZ
is unaffected.
PCM Channel Data
Data Input. Data is clocked into the transmitter either senally
(via TSER) or in parallel form (via Tl-T8), on the rising edge of
the transmitter clock (TCLK). The externally provided TCLK
normally has a rate of 1.544 MHz forTI and 1.576 MHzforT1C.
For a serial data interface, Transmit Sequence signals
(TSQ1-TSQ5) specify the binary value of the next channel to be
sampled. These signals, which can be used for control of channel
banks, may be advanced by one bit time using Transmit
Sequence Advance (TSA). The sequence of channel codes may
be selected to meet D1D (1,13,2,14,3, etc.), D2 (12,13,1,
·17, 5, etc.) or D3 and D4 (1, 2, 3, 4, 5, etc.), using D1 D and
D2 inputs.
In B7 stuffing, bit 7, the next least significant bit, is forced to a
1 if the channel data would otherwise be all Os. No extra bit is
"stuffed". The F and L bits are unaffected. B7 stuffing is applied
to outputs TPOSITNEG and TNRZ.
Frame and Multiframe Formatting
The transmitter contains frame and multiframe counters which
maintain the correct PCM format by inserting Ft and Fs bits (T1
modes with signaling; 1938, 1975), Ft (T1 nonsignaling modes;
193N, 197N) and Framing Pattern Sequence (FPS), Facility Data
Link (FDL) bits and Cyclic Redundancy Check (CRC) bits
(Extended Superframe Format).
For a parallel data Interface, timing signals are output at the
channel rate (TCHCLK) and at the frame rate (TCHSYNC) for
clocking data interface cirCUits.
Data Output. The serial PCM data IS clocked out of the transmitter on the rising edge of TCLK and is available on two outputs
simultaneously (TNRZ, TPOS and TNEG). TNRZ provides a
standard, nonreturn-to-zero (NRZ) TTL level version of the data.
TPOS and TNEG carry the same NRZ TTL level data as TNRZ
except that the 1s are routed alternately to TPOS and TNEG.
This facilitates the translation into the Alternate Mark Inversion
(AMI) line code, where 1s are represented alternately as positive
and negative pulses.
The required F-bit is generated by the R8070 and output on
TFGEN. The input TFSIG is sampled to obtain the F-bi!.
Normally, TFGEN would be connected directly to TFSIG, but
extemally supplied F-bit pattems may be multiplexed into TFSIG,
if required.
The frame counter may be reset to bit 1, channel 1 (TFSYNC
high), and the multiframe counter may be reset to frame 1
(TMSYNC high).
Loopback. The outputs TPOS and TNEG may be internally connected to RPOS and RNEG (TLOOP high) for loopback testing.
During loopback, the external TPOS and TNEG carry a continuous stream of 1s; TNRZ is unaffected.
Tl Operating Mode Selection and Characteristics
Mode
1935
1935
193N
193N
193E
193E
193F
1975
197N
Notes:
Data Rate
(Mbps)
BitsiFrame
FramesiMultlframe
Signaling
Zero Suppreasion
12
Yes
B8ZS
12
Yes
B7
1.544
193
4
No
B8ZS
No
4
B7
24
Yes
BSZS
1.544
193
24
Yes
B7
24
Special
BSZS
12
Yes
Transparent
1576
197
4
No
Transparent
B7. Bit 7 IS forced to a 1 (stuffed) on an otherwise all zero channel.
B8ZS· Bipolar 8-zero substitution.
Transparent. No zero suppression or substitution.
6-54
Mode Select Lines
M4
M2
Ml
M3
1
0
1
0
1
0
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
1
1
1
1
0
0
PCM Format
0
0
0
0
Tl (04)
1
1
1
Extended
Superframe
Format (ESF)
0
0
TIC
R8070
T1/CEPT PCM Transceiver
T1 FUNCTIONAL DESCRIPTION (Cont'd)
Clocks
Signaling and Link Data
The RB070 provides clock signals at the bit, channel, frame and
multiframe rate to facilitate data clocking and timing of external
Circuitry.
Robbed-bit Signaling
1935 and 1975 Modes. The RB070 implements robbed bit
signaling by inserting an A signaling bit into bit B of each channel in frame 6, and a B signaling bit into bit B of each channel
in frame 12. These bits replace the original LSB of the channel
data. The A and B signaling bits are input via TA and TB or via
TSER (selected by TSIGMD). RObbed-bit signaling may be
defeated, if not required, by connecting TA and TB to TB for the
Parallel Interface, or by selecting TSER as the source (and not
inserting signaling bits) for the Serial Interface.
193N and 197N Modes. No signaling is used in this mode. The
standard Fs bit pattern is not generated, but an external Fs
pattern may be used, e.g., for SLC-96 applications. See S-bit
signaling.
Rate
Clock
Description
Bit
TCLK
Same period as bit time. Rising edge
clocks all inputs and outputs.
Channel
TCHCLK
T1-TB sampled at the rising edge.
Frame
TCHSYNC
TLCLK
TSBCLK
High for sampling of channel 24.
Indicates TLiNK sampling.
Indicates TSBIT sampling.
Multiframe TMAX
TFR24
193E Mode. The RB070 implements robbed-bit signaling by
inserting an A signaling bit into bit B of every channel in frame 6,
B-bits in frame 12, C-bits in frame 1B and D-bits in frame 24.
These bits replace the original LSB of the channel data. The
A- and C-bits are input via TA(C); the B- and D-bits are input
via TB(D). TSIGSEL or TSIGSQ may be used to gate the appropriate bits to the signaling inputs.
High for sampling of the next to last
bit in multiframe.
High for sampling of frame 24 (193F).
RECEIVE SECTION
The receive section of the RB070 provides the synchronization,
signaling and alarm indication functions required for reception
of PCM data formatted according to cCln G.733 and applicable
sections of G.703. The AT&T technical advisories on Clear
Channel and Extended Superframe Format are also supported.
193F Mode. ABCD signaling is not used. Instead, this mode is
suitable for common channel signaling schemes where one
channel (e.g., channel 24) is dedicated for interoffice signaling.
PCM Channel Data
Link Data
Data Input. Received unipolar data on RPOS, derived from the
received positive pulses, and RNEG, derived from the received
negative pulses, is clocked into the receiver on the rising edge
of RCLK.
193E and 193F Modes. In Extended Superframe Format, half
of the F-bits are allocated for a Facility Data Link at 4 kbps. TLiNK
is the input for link data, which may be clocked externally by
TLCLK.
Data Output. The received data is clocked out on the rising edge
of RCLK and is available in serial form on RSER and also, if a
Parallel Interface is selected, in parallel (B·bit channel) form on
R1-RB. The parallel output R8 is also available for the Serial Interface, so that robbed signaling bits may be recovered.
197N and 1975 Modes. In the T1C modes there are 4 link bits
(L-bits) in addition to the normal 193 bits in a T1 frame, making
a total of 197 bits. These L.bits follow channels 6, 12, 1Band
24 (the L-bit follows the F-bit). The L-bits are input via TLlNK,
using TLCLK to clock external Circuitry. The input data rate is
32 kbps. The link data reappears on TFGEN after being sampled
at TLlNK, and is then input to TFSIG. If TFGEN is not connected
directly to TFSIG, then the link data must be multiplexed into
TFSIG by the user, rather than input via TLiNK.
For a serial data interface, Receive Sequence signals
(RSQ1-RSQ5) specify the binary value of the current channel.
The sequence may be retarded by one bit-time using Receive
Sequence Retard (RSR). If RSHIFT is high, the sequence is
"shifted" (upper bank and lower bank channel numbers are interchanged), so that channel 1 becomes 13, 2 becomes 14, and
so on. F-bit and L-bit codes remain the same.
S-Sit Signaling
193N and 197N Modes. In 193N and 197N modes, the RB070
does not provide the standard Fs bit pattern. Instead, Fs (S-bit)
may be externally supplied via TSBIT using TSBCLK to clock
external circuits. The Fs bit will be inserted into the data stream
at the appropriate time, but does not appear on TFGEN.
For a parallel data interface, timing signals are provided at the
channel rate (RCHCLK) and the frame rate (RCHSYNC) for clocking data interface circuits. RWIHBT is high for 2 bit times to
"cover" the change of data on R1-R8. This may be used to inhibit
the write signal for external memory.
Alarms
Loopback. Under control of TLOOP, the normal external inputs
on RPOS and RNEG may be replaced with an internalloopback
to the internal TPOS and TNEG. When switching in and out of
loopback, resynchronization will usually take place because the
two signals will not normally have identical framing.
A Yellow Alarm is transmitted, with a format appropriate to the
selected mode, when requested by TYEL. In 1935 mode, two
formats are supported (bit 2 = 0 or S-bit of frame 12 = 1). These
are selected by YELMD for both the transmitter and receiver.
6-55
•
I
R8070 .
T1/CEPT PCM Transceiver
T1 FUNCTIONAL DESCRIPTION (Cont'd)
193E Mode. The A, B, C and D signaling bits may be recovered
from the parallel output RS, which is always available, regardless
of whether a Serial or Parallel Interface is selected. RSIG is high
for the duration of frames 6, 12, IS and 24, which contain the
A-, B-, C- and D-blts, respectively. These bits may be distin·
guished by examining RSIGBD and RSIGCD. RSBCLK occurs
one bit time after these s)gnals and thus provides a convenient
clock.
Idle and Digital Milliwatt Codes. The normal received data may
be replaced, on a channel-by-channel basis, either with Idle code
(using RIDLE) or with digital milliwatt (using RMW).
B8ZS Decoding and B7 Stuffing. BSZS decoding is handled
automatically by the RS07O. The incoming data stream is scanned
for occurrences of the BSZS code. These are replaced with S
zeros, thus restoring the original data. Both serial (RSER) and
parallel (Rl-RS) data outputs include BSZS corrections.
193F Mode. Robbed-bit signaling is not used in this mode. If
common channel signaling is employed, the signaling information IS contained In a data channel and is recovered In the same
way as the channel data.
Bit 7 stuffing produces a forced error (which is acceptable for
a voice channel, but not data), so the receiver cannot recover
the original data.
Link Data
Synchronization
193E and 193F Modes. The 4 kbps Facility Data link bits, contained within the F-bit structure of the Extended Superframe
Format, are recovered at RLiNK using RLCLK as a clock.
The serial bit stream at RPOS and RNEG is examined by the
synchronizer, and the framing pattern IS located through a fivestage process that eliminates erroneous bit candidates.
'Synchronization is achieved in less than 10 ms.
197N and, 1975 Modes. The four link bits per frame of the T1 C
mode are recovered at RLiNK With RLCLK as, a clock.
S-bit Signaling
A generalized form of the synchronizallOn algorithm is described
in the'RS07O DeSigner's GUide (Order No. 313). After a power-up
reset (PUP low for at least 16 cycles), the receiver begins to
search for frame and multlframe alignment. When synchronization is achieved, the receiver monitors the frame and multiframe
alignment signals for errors. A Red Alarm is generated (RRED
high) if frame alignment is lost. The criterion for lOSS of frame
alignment in all T-carrier modes is "2 out of 5" errors in the Ft
pattern.
193N and 197N Modes. In 193N and 197N modes, the user·
supplied S-blts (Fs) are recovered at RSBIT with RSBCLK as a
clock. In SLC-96 applications, which use the Fs bit for signalIng, an input RS96E IS provided which locks the currently
received Fs pattern, thus maintaining Fs dependent signals such
as RSIG, RSIGSO and RSBCLK.
Alarms
Alarm Indication
Name
Mode
DID and D2 high prevents resynchronization after loss of frame
alignment. The sequential channel assignment of D4'is assumed
for RS01-RS05 and TS01-TS05. This mode of operation may
be used during testing.
RRED
RYEL
ERR
FERR
CKERR
SERR
RVLL
Loss of frame alignment.
All
Yellow Alarm.
All
FPS (Framing) or CRC error.
193E
All but 193E Frame alignment error.
CRC error.
193F
1935, 1978 S-blt error.
Bipolar Violation, Loss of carrier.
All
Signaling arid Link Data
Clocks
Robbed-bit Signaling
The RS070 provides clock signals at the bit, channel, frame and
multiframe rate to facilitate data clocking and timing of external
circuitry.
The receiver can be forced to restart a synchronization search
(RMRST high) or to skip a bit while synchronized (RSRCH low).
1935 and 1975 Modes. The A and B signaling bits may be
recovered from the parallel output RS, which is always available
regardless of whether a Serial or Parallel Interface is selected.
RSIG is high for the duration of frame 6 and frame 12, which
contain tne A- and B-bits, respectively. In addition, RSIGSO
rising edge indicates the start of frame 6, and the lailing edge
indicates the start of frame 12. These two timing signals allow
the external circuitry to recover the A and B signaling bits. RSBIT
takes the value of the last received Fs (S-blt). RSBCLK rising
edge provides a convenient clock for RSBIT and RSIGSO, as
it succeeds them by one bit time.
193N and 197N Modes. No robbed-bit signaling is used in these
modes. See S-bit signaling.
6-56
Rate
Clock
Description
Bit
RCLK
Same period as bit time. Rising
edge clocks all Inputs and outPlJts.
Channel
RCHCLK
RWIHBT
Rl-RS changes at the riSing edge.
Memory-write inhibit at Rl-RS
change.
Frame
RCHSYNC
RLCLK
High for output of channel 24:
Indicates RLiNK data bit ready.
Multiframe
RSYNC
RMFA
High for first F-bit of multiframe.
High during frame 24 (193F).
R8070
T1/CEPT PCM Transceiver
T1 INTERFACE DESCRIPTION
TA/TA(C)/TSBIT
TB/TB(D)
TLiNKlYELMD
TFSIG
TSBCLKlTSIGSELI
TFR24
TLCLK
TFGEN
TNRZ
TMAX
TFSYNC
TMSYNC
TLOOP
TlDLE
TYEL
RANSMITTE
(IA)
(IB)
(IC)
(10)
(OE)
FRAMING
MODE·
DEPENDENT
TRANSMIT
INTERFACE
(OH)
(OJ)
DEDICATED
TRANSMIT
INTERFACE
TSQ1-TSQ5
TCHCLK
TCHSYNC
DEDICATED { TCLK
TRANSMIT
TPOS
INTERFACE
TNEG
TO LlU
8
(PS09)}
(PS010)
PARALLEL
TRANSMIT
INTERFACE
11-T8 (PSI1-PSI8)
Rl-R8 (PS01-PS08)
DEDICATED {
RECEIVE
RCLK
INTERFACE
RPOS
TO LlU RNEG
RCHCLK
RCHSYNC
RWIHBT
RECEIVER
PUP
Vee
Vss
}
(PSOll)
(PS012)
(PS013)
RSER
RVLL
RYEL
RRED
RSYNC
RMRST
RSRCH
RIDLE
RMW
RS96E1YELMD
RSIGIRMFA
RSBIT/RSIGBD
RSBCLK/CKERRI
RSIGCD
FERR/ERR
SERR
RLlNKlMSl
RLCLKlMS2
(00)
(OE)
(OF)
(OG)
PARALLEL
RECEIVE
INTERFACE
(PS09_PS013)}
TSA
(PS06)
(PSll)
(PSI2)
(PSI3)
(PSI4)
010
02
(PSI6)
(PSI?)
}
RSHIFT
RSR
(PSIS)
(PSI8)
}
TSIGSQ
TSER
TSIGMD
RSQ1-RSQ5 (PS01-PSOS)
RSIGSQ
R8
}
(IC)
(OA)
(OB)
(OC)
5
SERIAL
TRANSMIT
INTERFACE
SERIAL
COMMON
INTERFACE
SERIAL
RECEIVE
INTERFACE
(PS07)
(PS08)
DEDICATED
RECEIVE
INTERFACE
•
FRAMING
MODEDEPENDENT
RECEIVE
INTERFACE
Ml-M4
·TIE TO Vss FOR
SERIAL INT[;RFACE
PIS
R8070 Input/Output Signals - T1 Modes
6-57
T1/CEPT PCM Transceiver
R8070
T1 INTERFACE DESCRIPTION (Cont'd)
Pin Assignments-Dedicated Signals
Pin No.
Pin Name/Symbol
i/O
TCLK
TFSYNC
TMSYNC
TLOOP
TIDLE
TYEL
I
I
I
I
I
I
TPOS
TNEG
TNRZ
TMAX
0
0
QUIP
!
PLCC
Signal Name
16
15
8
10
3
4
17
16
8
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
Clock
Frame Sync
Multl/rame Sync
Loop
Idle
Yellow Alarm
19
18
20
11
Transmit
Transmit
Transmit
Transmit
Unipolar Positive
Unipolar Negative
Non·Return·to·Zero
Maximum
9
3
4
0
18
17
19
10
RCLK
RPOS
RNEG
RIDLE
RMW
RMRST
RSRCH
I
I
I
I
I
I
I
56
55
54
53
52
40
41
59
58
57
56
55
42
44
Receive
Receive
Receive
Receive
Receive
Receive
Receive
Clock
Unipolar Positive
Unipolar Negative
Idle
Milliwatt
Master Reset
Search
RSER
RSYNC
RVLL
RYEL
RRED
0
0
0
0
0
50
37
28
53
39
30
54
40
Receive
Receive
Receive
Receive
Receive
Senal Data
Sync
Bipolar Vlolallon. Loss of Carner
Yellow Alarm
Red Alarm
M1
M2
M3
M4
PIS
I
I
I
I
I
11
12
13
14
32
12
13
14
15
34
Framing Mode Select 1
Framing Mode Select 2
Framing Mode Select 3
Framing Mode Select 4
Parallel/Serial Interface Select
PUP
Vce
Vss
I
I
I
39
64
33
41
68
35
Power·Up
+5V Power
Ground
0
51
38
Pin Assignments-Parallel/Serial Interface-Dependent Signals
Parallel Interface (P/S = High)
Pin No.
Pin Name
110
QUIP
PLCC
PSl1
PSI2
PSI3
PSI4
PSI5
PSI6
PSI7
PSI8
I
I
I
I
I
I
I
I
2
1
63
62
61
60
59
58
2
1
67
66
65
64
63
62
PS01
PS02
PS03
PS04
PS05
PS06
PS07
PS08
PS09
PS010
PS011
PS012
PS013
0
0
0
0
0
0
0
0
0
0
0
0
0
49
48
47
46
45
44
43
42
23
24
25
26
27
52
51
50
49
48
47
46
45
24
25
27
28
29
Symbol
Signal Name
TSER
TSIGMD
T2
"}
Transmit Channel Data Bits 1-8
T8
R2
R3
R4
R5
R6
R7
R8
TCHCLK
TCHSYNC
RCHCLK
RCHSYNC
RWIHBT
"'I
Receive Channel Data Bits 1-8
Transmit Channel Clock
Transmit Channel Sync
Receive Channel Clock
Receive Channel Sync
Receive Wnte Inhibit
Notes:
1. Not applicable to T1 modes; tie to GND
2. Different signal than CEPT modes
6-58
Signal Name
TSA
RSHIFT
OlD
02
RSR
Transmit Senal
Transmit Signaling Mode
See Note 1
Transmit Sequence Advance
Receive Shift
OlD Channel Sequence Select
02 Channel Sequence Select
Receiver Sequence Retard
"$>}
Receive Sequence Code Bits 1-5
-
T3
T4
T5
T6
T7
Serial Interface (P/S = Low)
Symbol
RS02
RS03
RS04
RS05
TSIGS02
RSIGS02
R8 2
~Q'
TS02 }
TS03
TS04
TS05
Transmit Signaling Square Wave
Receive Signaling Square Wave
Receive Data Bit 8
Transmit Sequence Code Bits 1-5
R8070
T1/CEPT PCM Transceiver
11 INTERFACE DESCRIPTION (Cont'd)
Pin Assignments-Framing Mode-Dependent Signals
Pin No.
1935 Mode
193N Mode
Pin Name
1/0
QUIP
PLCC
IA
IB
IC
ID
I
I
I
I
5
6
57
7
5
6
61
7
OA
OB
OC
OD
OE
OF
OG
OH
OJ
0
0
0
0
0
0
0
0
0
34
31
30
29
22
35
36
21
20
36
33
32
31
23
Pin Name
I/O
QUIP
PLCC
IA
IB
IC
ID
I
I
I
I
5
6
57
7
5
6
61
7
OA
OB
OC
OD
OE
OF
OG
OH
OJ
0
0
0
0
0
0
0
0
0
34
31
30
36
33
32
31
23
Pin Name
I/O
QUIP
PLCC
IA
IB
IC
ID
I
I
I
I
5
6
57
7
5
6
61
7
TSBIT
OA
OB
OC
OD
OE
OF
OG
OH
OJ
0
0
0
0
0
0
0
0
0
34
31
30
29
22
35
36
21
20
36
33
32
31
23
Symbol
TSBIT
RS96E
TFSIG
RSIG
RSBIT
RSBCLK
FERR
TSBCLK
MSI
MS2
37
38
22
21
-
TFGEN
Pin No.
29
22
35
36
21
20
Signal Name
Symbol
TA
TB
YELMD
TFSIG
Transmit A Signaling
Transmit B Signaling
Yellow Alarm Mode
Framing-Bit Signal
Receive Signaling Frame
Receive S-Brt
Receive S-Blt Clock
Framing Error
Transmit 8-Blt Clock
Master State Sequence Code. Bit 1
Master State Sequence Code. Bit 2
See Note 2
Framing-Bit Generator
RSIG
RSBIT
RSBCLK
FERR
SERR
MSI
MS2
Receive Signaling Frame
Receive S-Bit
Receive S-Bit Clock
Framing Error
S-Bit Errors
Master State Sequence Code. Bit 1
Master State Sequence Code. Bit 2
See Note 2
Framing-Bit Generator
TFGEN
193F Mode
37
38
22
21
Symbol
TLINK
TFSIG
RMFA
CKERR
FERR
TFR24
RLiNK
RLCLK
TLCLK
TFGEN
Pin No.
Signal Name
193E Mode
Symbol
37
38
22
21
Signal Name
See Note 1
See Note 1
Transmit Link
Framing-Bit Signal
TA(C)
TB(D)
TLiNK
TFSIG
Transmit A(C) Signaling
Transmit B(D) Signaling
ll'ansmlt Link
Framing-Bit Signal
Receive Multlframe Alignment
See Note 2
Cyclic Redundancy Check Bit Error
Framing Error
Transmit Frame 24
Receive Data Link
Receive Link Clock
Transmit Link Clock
Framing-Bit Generator
RSIG
RSIGBD
RSIGCD
ERR
TSIGSEL
RLINK
RLCLK
TLCLK
TFGEN
Receive Signaling Frame
Receive Signaling B or D
Receive Signaling C or D
Framing or CRC Error
Transmit Signaling Select
Receive Data Link
Receive Link Clock
Transmit Link Clock
Framing-Bit Generator
197N Mode
Symbol
Signal Name
Transmit S-Bit
See Note 1
Receive SLC-96 Enable
Framing-Bit Signal
Signal Name
1975 Mode
Symbol
Signal Name
TLiNK
TFSIG
Transmit S-Bit
See Note 1
Transmit Link
Framing-Bit Signal
TA
TB
TLiNK
TFSIG
Transmit A Signaling
Transmit B Signaling
Transmit Link
Fram lng-Bit Signal
RSIG
RSBIT
RSBCLK
FERR
TSBCLK
RLiNK
RLCLK
TLCLK
TFGEN
Receive Signaling Frame
Receive S-Blt
Receive 8-Blt Clock
Framing Error
Transmit S-Bit Clock
Receive Data link
Receive Link Clock
Transmit Link Clock
Framing-Bit Generator
RSIG
RSBIT
RSBCLK
FERR
SERR
RLiNK
RLCLK
TLCLK
TFGEN
Receive Signaling Frame
Receive 8-Blt
Receive S-Bit Clock
Framing Error
S-Bit Errors
Receive Data Link
Receive Link Clock
Transmit Link Clock
Framing-Bit Generator
-
Notes:
1 Test Input, !Ie to a high level
2. Test output, leave open (unconnected)
6-59
•
T1/CEPT PCM Transceiver
R8070
T1 INTERFACE DESCRIPTION (Cont'd)
Signal Definitions Pin Name/
Symbol
I/O
Dedicated Signals
Signal Name/Description
TCLK
I
Transmit Clock. TCLK is the transmitter clock Input and must be present for normal transceiver (transmitter or
receiver) operation. TCLK must be in the range 100 kHz - 3.1 MHz and will normally be 1.544 MHz for Tl and
1.576 MHz for 1/2 TIC. All inputs and outputs are clocked on the rising edge of TCLK.
TFSYNC
I
Transmit Frame Sync. TFSYNC high resets the bit counter to the beginning of a frame. The counter restarts on the
first rising edge of TCLK after TFSYNC goes low TFSYNC should be synchronous with TCLK to ensure setup and
hold times. TFSYNC need only be applied to change the transmitter frame alignment.
TMSYNC
I
Transmit Multiframe Sync. TMSYNC high resets the frame counter to frame 1. TMSYNC low enables the frame
counter. TMSYNC need only be applied to change the transmitter multiframe alignment. TFSYNC is normally
applied with TMSYNC to align to the first bit of the multiframe.
TLOOP
I
Transmit LOOp. TLOOP high Invokes loopback mode, where TPOS and TNEG are internally routed to RPOS and
RNEG, respectively. TPOS and TNEG external signals carry alternate Is representing a continuous stream of IS.
TLOOP does not affect TNRZ. This Internal looping has one bit time less delay than an equivalent external looping.
TIDLE
I
Transmit Idle. TIDLE high causes the idle code (01111111) to be transmitted In the next channel, in place of the
normal data. This substitutton continues for each channel In which TIDLE IS high.
TYEL
I
Transmit Yellow Alarm. TYEL high causes transmission of a Yellow Alarm in the following formats:
Mode
193N, 1935 (YELMD =0), 197N, 1975
1935 (VELMD =1)
193F, 193E
Format
Bit 2 =0 In all data channels
S-blt high In frame 12
8 Os, 8 Is pattern on data link
TPOS, TNEG
0
Transmit Unipolar Positive, Unipolar Negative. TPOS and TNEG are the "unipolar-paired" TTL, NRZ outputs for
transmitted data Binary 0 is coded as a low (0) level on both outputs Binary 1 IS coded as a high (1) level on
TPOS or TNEG, alternately. TPOS and TNEG allow the direct generatton of AMI line code in which a 1 (mark) is
alternately represented as a positive or negative pulse. There IS an 8-bit throughput delay between the TSER input
and the TPOSITNEG outputs.
TNRZ
0
Transmit Non-Return-to-Zero. TNRZ is the TTL, NRZ output for transmitted data. This output is unaffected by
TLOOP or by B8ZS zero suppression coding. There is an 8-bit throughput delay between the TSER input and the
TNRZ output.
TMAX
0
Transmit Maximum. TMAX is high for one bit time per multlframe coincident With the sampling of bit 7 of channel
24 of the last frame (2 bit times before sampling the first F-bit of a multiframe).
RCLK
I
Receive Clock. RCLK is the receiver clock input and must be present for normal transceiver operation. All inputs
and outputs are clocked on the riSing edge of RCLK. RCLK must be in the range 100 kHz - 3.1 MHz and will
normally be 1.544 MHz for Tl and 1.576 MHz for 1/2 TIC.
RPOS, RNEG
I
Receive Unipolar Positive, Unipolar Negative. RPOS and RNEG are the inputs for received data recovered from
the positive and negative AMI line pulses. RPOS and RNEG should have TTL levels and may be of either NRZ or
RZ form. If RPOS is strapped to RNEG (and given composite RPOS/RNEG data) the first occurrence of a 1 will
Invoke the transparent mode in which B8ZS zero suppression is disabled in both the receiver and the transmitter.
RIDLE
I
Receive Idle. RIDLE high causes data in the next received channel to be substituted with the idle code (01111111).
The substitution continues for each channel In which RIDLE is high. RIDLE and RMW should not be high
simultaneously.
RMW
I
Receive Milliwatt. RMW high causes data in the next received channel to be substituted with the digital milliwatt
code; a repeating pattern of eight 8-bit bytes that translate into a 1 kHz signal at a level of 1 mW. The substitution is
performed for each channel in which RMW is high. RMW and RIDLE should not be high simultaneously.
RMRST
I
Receive Master Reset. RMRST high resets the master state sequencer in the synchronizer to its initial (WAIT) state.
RMRST low allows synchronization to proceed.
RSRCH
I
Receive Search. RSRCH low prevents the master state sequencer in the synchronizer from proceeding out of the
WAIT state. It does not force the synchronizer to the WAIT state (see RMRST). If RSRCH is low while the receiver is
in frame alignment (RRED low), bit 5 of channell, frame 1 is skipped. This allows recentering of elastic stores.
6-60
R8070
T1/CEPT PCM Transceiver
T1 INTERFACE DESCRIPTION (Cont'd)
Signal Definitions - Dedicated Signals (Cont'd)
Pin Namel
Symbol
Signal NamelDescription
1/0
RSER
0
Receive Serial Data. RSER is the senal data output Including F-blts and L-blts and after B8ZS decoding, If
applicable. The throughput delay from RPOS/RNEG to RSER is 14 cycles of RCLK. RSER is always valid,
regardless of the synchronizer state.
RSYNC
0
Receive Sync. RSYNC
RVLL
0
Receive Bipolar Violation, Loss of Carrier. RVLL high Indicates that the 1 currently at RSER resulted from a
bipolar violation. RVLL also goes high after 31 consecutive Os at RSER, to indicate "loss of carrier". The first
received 1 (If non-bipolar violation) resets RVLL. These two Signals are distinguished by the level on RSER.
RYEL
0
Receive Yellow Alarm. RYEL high indicates a received Yellow Alarm for the follOWing conditions:
IS
high dunng the first F-blt of each multlframe while the receiver is synchronized.
Mode
193N, 1935 (YELMD=O), 197N, 1975
1935 (YELMD = 1)
193F, 193E
RRED
Ml-M4
o
Condition
Bit 2 = 0 for 255 consecutive channels
S-bit high In frame 12
16 ± 1 sets of 8 Os, 8 Is on data link
Receive Red Alarm. RRED high indicates loss of frame alignment. RRED low indicates correct frame alignment.
Multlframe alignment IS separately Indicated.
Framing Mode Select. Ml-M4 select the framing mode as follows (See the Tl Mode Selection Table tor additional
mode information):
Ml
I
0
I
0
I
0
I
I
I
M2
0
0
I
I
I
I
0
0
I
M3
I
I
I
I
I
I
I
0
0
M4
0
0
0
0
I
I
I
0
0
Tl Mode
1935
1935
193N
193N
193E
193E
193F
1975
197N
Zero Suppression
B8ZS
B7
B8ZS
B7
B8ZS
B7
BSZS
Transparent
Transparent
PIS
Parallel/Serial Interface Select. PIS selects parallel (PIS high) or serial (PIS low) operation of the PSII-PSI8 and
PSOI-PSOI3 pinS
PUP
Power-up. PUP Inillal,zes the R8070 transmitter and receiver It Includes TFSYNC, TMSYNC and RMRST reset
functions. PUP sets all outputs, except OJ. to a high-Impedance state, to facilitate testing of penpheral CirCUitry.
Vcc
+5V Power. +5 VDC power
Vss
Ground. Power and signal ground
II
6-61
T1/CEPT PCM Transceiver
R8070
T1 INTERFACE DESCRIPTION (Cont'd)
Signal Definitions a. Parallel Interlace
Pin Name/
Symbol
(piS
110
Parallel/Serial Interface-Dependent Signals
High)
Signal Name/Description
Symbol
PSI1-PSI8
I
T1-T8
Transmit Channel Data Bits 1-8. TI-TS are the parallel inputs for channel data. They are clocked
into the transmitter at the rising edge of TCHCLK, by the rising edge of TCLK. The falling edge of
TCHCLK may be used to present the next channel data at TI-TS.
PS01-PS08
0
R1-R8
Receive Channel Data Bits 1-8. RI-R8 are the parallel outputs for channel data. F-bits and L-bits
are excluded; "robbed" signaling bits are included on R8. The channel data is available for a
complete channel time and is updated at the rising edge of RCHCLK. The falling edge of RCHCLK
may be used to clock this data into external buffers. RI-R8 are only valid while the receiver is
synchronized; RSER, the serial data output, is always available and always valid.
PS09
0
TCHCLK
Transmit Channel Clock. TCHCLK is a channel-rate clock whose rising edge indicates that parallel
data on TI-TS IS being sampled The falling edge is used to present the next channel's data on
T1-T8. TCHCLK IS low for 4 bit times.
PS010
0
TCHSYNC
Transmit Channel Sync. TCHSYNC is a frame-rate signal which is high for 8 bit times, prior to the
sampling of channel I. The rising edge precedes channel 24 sampling by one bit time; the falling
edge precedes channell sampling by one bit time.
PS011
0
RCHCLK
Receive Channel Clock. RCHCLK is a channel-rate clock whose rising edge indicates that new
channel data has been output to RI-RB. The falling edge may be used to clock this data into
external buffers. RCHCLK IS high for 4 bit times.
PS012
0
RCHSYNC
Receive Channel Sync. RCHSYNC is a frame-rate signal which is high for 9 (193) or 10 (197) bit
times. The rising edge occurs one bit time after the output of channel 24 data on R1-R8. The falling
edge occurs one bit time after the output of channell data on RI-RB.
PS013
0
RWIHBT
Receive Write Inhibit. RWIHBT is a channel-rate signal, 2 bit times high, which "covers" the
change of parallel data on RI-RB. RWIHBT is high for one bit time before and after the rising edge
of RCHCLK.
6-62
T1/CEPT PCM Transceiver
R8070
11 INTERFACE DESCRIPTION (Cont'd)
Signal Definitions b. Serial Interface (P/S
Pin Name/
Symbol
110
Parallel/Serial Interface-Dependent Signals
Low)
Symbol
Signal Name/Description
PSI 1
I
TSER
Transmit Serial. TSER IS the serral Input for the channel data and, optionally, signaling data
PSI2
I
TSIGMD
Transmit Signaling Mode. TSIGMD selects the source for "robbed" signaling bits. If low, TA and
TB (193S and 1975) or TA(C) and TB(D) (193E) are the source. If high, TSER is the source.
PSI3
I
PSI4
I
TSA
Transmit Sequence Advance. TSA high advances the standard timing of TSQ1-TSQ5 and TSIGSQ
by one bit time
PSIS
I
RSHIFT
Receive Shift. RSHIFT high shifts the RSQ1-RSQ5 sequence of channel numbers from 1 to 13, 2
. 12 to 24 The F-blt and L-blt codes are unaffected
to 14,
PSI6, PSI?
I
DID, D2
Channel Sequence Select. DID and 02 select the sequence of channel numbers according to
OlD, 02, D3 or D4 channel assignments.
PSI3. Not applicable to Tl modes, tie to ground
02
0
0
1
1
PSI8
I
Channel Assignment
D3, D4
OlD
02
03, D4 plus synchronization lock
(inhibits resync after loss of frame alignment)
DID
0
1
0
1
RSR
Receive Sequence Retard. RSR high delays the standard timing of RSQ1-RSQ5 and RSIGSQ by
one bit time
PS01-PSOS
0
RSQ1-RSQ5
Receive Sequence Code Bits 1-5. RSQ1-RSQ5 is the binary value of the channel number (1-24)
currently emerging from RSER. The sequence is selected by OlD and 02 to match DID, 02, D3 or
04 channel assignments The code for F-blt IS 00000 The codes for L-blt (19? modes) are' 11100
(following channel 24), 11101 (channel 6), 11110 (channel 12) and 11111 (channel IS).
PS06
0
TSIGSQ
Transmit Signaling Square Wave. TSIGSQ IS a 2/3 kHz square wave which is high for
frames 6-11 (193S) or frames 6-11, IS-23 (193E) and low for other frames. TSIGSQ allows certain
per-channel codecs to Insert A and B signaling bits Into TSER.
PS07
0
RSIGSQ
Receive Signaling Square Wave. RSIGSQ is identical In form to TSIGSQ The rrslng edge
precedes frames carrying A(C) signaling bitS, the failing edge precedes frames carrying B(D)
signaling bits
PSOS
0
RS
Receive Data Bit 8. RS carnes bit S parallel channel data and IS available for the complete
channel time. RS allows extraction of the "robbed" signaling bitS, which are located In bit S
PS09-PSOI3
0
TSQ1-TSOS
Transmit Sequence Code Bits 1-5. TSQ1-TSQS IS the binary value of the channel number (1-24)
currently being sampled at TSER. The channel assignment and codes for F-bit and L-blt are
identical to those In RSQ1-RSQS.
6-63
II
T1/CEPT PCM Transceiver
R8070
T1 INTERFACE DESCRIPTION (Cont'd)
Signal Definitions Pin
Name
I/O
IA
I
IB
IC
I
I
Signal
Symbol
TSBIT
TA(C)
-
TB
-
TB(D)
-
RS96E
·
YELMO
-
TLiNK
-
TFSIG
OA
0
RSIG
OC
00
0
0
0
0
-
-
·
-
-
-
-
·
-
-
-
-
-
-
·
·
- I-
-
-
-
-
-
Receive SLC-96 Enable. RS96E selects the method for Fs recovery. If low, Fs is
extracted from the incoming data. If high, the current Fs pattern IS recirculated.
·
-
-
-
-
Yellow Alarm Mode. YELMO selects the method for transmission and detection of
Yellow Alarm. If low, Yellow Alarm is transmitted as bit 2 = 0 in all data channels. If
high. Yellow Alarm is transmitted as a 1 In the S·bit of frame 12.
-
·
·
-
-
-
Transmit S-Bit. TSBIT is the S·bit (Fs) input.
·
Transmit A Signaling. TA is the A·bit input for robbed·bit signaling.
··· ·
······
·· ·· ·
-
-
-
RMFA
-
RSBIT
··
-
-
-
-
·
-
-
· ·
-
Transmit B Signaling. TB is the B·bit input for robbed·bit signaling.
Transmit B(D) Signaling. TB(D) is the B·bit (TSIGSEL low) or O-bit (TSIGSEL high)
input for robbed·bit signaling.
Transmit Link. TLINK is the serial data link input. The data rate is 4 kbps (193E,
193F) or 32 kbps (197N, 1975).
Framing-Bit Signal. TFSIG is the IOput for Ft and Fs bits and is sampled coincident
with channell parallel data. Connect to TFGEN for internally generated framing bits.
Receive Signaling Frame. RSIG is high during the receipt of signaling frames, low
for non-signaling frames. RSIG is held low for recent Ft or Fs errors.
Receive Multiframe Alignment. RMFA is high during frame 24. Transitions coincide
with the emergence of the F-bit at RSER.
Receive S-Bit. RSBIT IS the output of the last received S-bit.
-
RSBCLK
··
-
-
· ·
CKERR
-
-
·
-
-
-
Cyclic Redundancy Check Bit Error. CKERR high indicates an error in the current
CRC bit at RSER.
RSIGCD
-
-
-
·
-
-
Receive Signaling C or D. RSIGCO is a 1/3 kHz square wave which is low for Aand B-bit signaling frames, and high for C- and D-bit signaling frames. (See
RSIGBD.)
FERR
-
·
li'ansmit A(C) Signaling. TA(C) is the A·bit (TSIGSEL low) or C·bit (TSIGSEL high)
input for robbed·blt signaling.
RSIGBD
ERR
OE
·
-
I
OB
Signal Name/Description
193N 1938 193F 193E 197N 1978
TA
10
Framing Mode-Dependent Signals
Mode
· · · · -·
- - -
·
-
Receive Signaling B or O. RSIGBO is a 2 kHz square wave which is low for A- and
C-bit signaling frames, and high for B- and O-bit signaling frames. RSIGBO.
RSIGCD and RSIG are used to decode A, B, C and D signaling bits. (See RSIGCD.)
Receive S-Bit Clock. RSBCLK is a 4 kHz square wave with a rising edge 1 bit time
after the emergence of an S-bit (Fs) at RSER.
Framing Error. FERR high indicates an error in the current framing bit at RSER.
Framing or CRC Error. ERR high indicates an error in the current framing bit
(RSIGBD high) or checksum bit (RSIGBO low) at RSER.
TSBCLK
·
-
-
-
·
-
SERR
-
·
-
-
-
·
S-Blt Errors. SERR high indicates one or more errors in the last five S-bits. SERR
will remain high until the last five S-bits are correct.
TFR24
-
-
-
-
-
Transmit Frame 24. TFR24 is high during frame 24.
TSIGSEL
-
-
·
-
·
-
-
Transmit Signaling Select. TSIGSEL is low for frames 2-13 (A- and B-bit sampling).
and high for frames 14-24 and 1 (C- and O-bit sampling). Transitions coincide with
F-bit sampling.
li'ansmit S-Bit Clock. TSBCLK is a 4 kHz square wave whose rising edge occurs
2 bit times after the sampling of TSBIT.
6-64
T1/CEPT PCM Transceiver
R8070
T1 INTERFACE DESCRIPTION (Cont'd)
Signal Definitions Pin
Name
110
OF
0
Signal
Symbol
MSI
Framing Mode-Dependent Signals (Cont'd)
Mode
Signal Name/Description
193N 1938 193F 1193E 197N 1978
··
-
-
-
-
Master State Sequence Code, Bit 1. MSI IS the least significant bit (bit 1) of master
state sequence code MS1, MS2 and MS3 indicate the binary value of the current
state of the receiver's synchronizer MS3 IS the Inverse of RRED
(RRED)
MS3
a
a
a
a
1
1
1
1
RLiNK
OG
0
MS2
-
-
·I ·
··
·l.
-
-!-
-
I
RLCLK
-I- · · · ·
-
I
OH
0
TLCLK
OJ
0
TFGEN
I- · · · ·
· · · · · ·
i
I
I
I
MS2
MSI
a
a
a
1
1
1
a
a
a
a
1
1
1
1
a
1
Master State
Walt
Imtlallze
Search
Demons
Proving State 1 (PI)
Proving State 2 (P2)
Proving State 3 (P3)
Multlframe Synchronization
Receive Data Link, RLiNK IS the serial data link output The data rate matches that
of TLiNK 4 kbps (193E, 193F) or 32 kbps (197N, 1975)
Master State Sequence Code, Bit 2. MS2 IS bit 2 of the master state sequence
code (See MSI )
Receive Link Clock. RLCLK IS a square wave whose rising edge occurs 2 bit times
(193E, 193F) or 1 bit time (197N, 1975) after the received data on RLiNK
Transmit Link Clock. TLCLK IS a square wave whose rising edge occurs 4 bit times
after the sampling of TLiNK
Framing-Bit Generator. TFGEN IS the output of the framing pattern generator It
Includes the Ft and Fs bit (193S, 1975) , Ft bit (193N, 197N) and framing, data link
and CRC check bits (193E, 193F)
I
•
6-65
R8070
T1/CEPT PCM Transceiver
T1 WAVEFORMS
/.
MULTIFRAME
M
FT=l
t
FRAME NO.,
rt
1
0
Fs
1
2
0
3
0
1
1
1
0
1
0
t t t t t t t t t
4
5
6
7
8
9
10
11
____________________________
TMAX
~
TFGEN
~'-____"""
TFSIG'
~'__ _ _---'r------.LJ.-------,'____
LJ
12
~n,~
__________
'--__. . .Il'-____. . .r
r
__'Il
TSIGSQ'
NOTE: 1. Serial Interface selected.
2. TFSIG shown connectd to TFGEN.
Transmit Signaling-Mode 1935 and 1975
I·
+------------------0
MULTIFRAME
M
I
----------------------_.1-001----o
o
MUL TIFRAME
M
+ 1
---
o
FRAME NO.
~
____________________
~n~
________
RSYNC
Jl
RSIG
l '--__________......r__l'-________________~r__l'______________
RSBCLK
RSBIT
RSIGSQ'
NOTE: 1. Serial Interface selected
Receive Signaling-Modes 1935 and 1975
6-66
!
I
R8070
T1/CEPT PCM Transceiver
T1 WAVEFORMS (Cont'd)
~ -~ "'' "...,~~+- "m"".' "., .~.",m'"' •.,--+ :"m"".' ••,-11
'''."0 T'T, I,!. I, , Ll. j j, LI · I ' j, LL
111
n
TMAX
J1
TSBCLK
~
TSBIT
---.J
TFGEN
~
I
TFSIG'
II
I
NO"". " . . . .
ILl
n
~
~
I
______
~r~~
______
~~~
~
,,~ W""~" ro
______
~
~~~
______
~r
r·
II
,,"'N.
L
Transmit Signaling-Mode 193N and 197N
1-----
--------------~
I
~
I
MULTI FRAME M
o
FS2= 1
I
FRAME NO.
2
1
I
---I--
MULTI FRAME M + 1
-I--
MULTI FRAME M + 2
1
0
1 t 1
2
3
3
0
t
4
I
2
~
I
________~n
RSYNC
J
RSIG
~------'~
n~
---+--
RSBCLK
RSBIT
RSIGSQ'
NOTES:
1. Serial Interface selected
2. Standard S-Bit input shown
Receive Signaling-Mode 193N and 197N
6-67
MULTI FRAME M + 3
1
0
0
0
1
t t t
4
--I
1
0
2
~
I
n
1
3
t
4
~
I
I
II
•
T1/CEPT PCM Transceiver
R8070
T1 WAVEFORMS (Cont'd)
1112131415161718191101111121131141151161171181191201211221231241112131415161718191101111121131141151161
FRAME NO.
J~
TMAX
______________________
~n~
________________
TSIGSQ'
IL..________~
TSIGSEL
NOTES:
1.
~
__________~r___
Serial Interface selected
Transmit Signaling-Mode 193E
t-
!.----MULTIFRAME M
I
RSYNC
RSIG
Jl
l
A B C
n
n
n
0
n
n
RSIGBD
RSIGCD
l
Receive Signaling-Mode 193E
6-68
MULTI FRAME M + 1
A
B
n
n
R8070
T1/CEPT PCM Transceiver
T1 WAVEFORMS (Cont'd)
FRAME N' OF
FRAME 1 OF
- - - - - - - - - - - - M U L T I F R A M E M----------J.~---- MULTIFRAME M+l - - - - +
- - - - - - + 1 - - - - CHANNEL 24
----J......:...-I-----
TCLK
I I
I
T1·Te
TCHCLK
I I I
~
II
1
1
TMAXa
TFSIG
TFGEN
Iii
1
I I I
I
I
----'1
TCHSVNC _ _ _ _
TFSVNC
TMSVNC
I
ftt'lSJ'N~'ltli WX'tJYXttlJ,XX'l'tlttf.XXXx~H'tf.,xYJ,Xi,XXx'tf.,xmX'tttf.Xmc2HXXX>
~
-"---I- - - - - -
L-j
______________________
r---,
~I
I~~
_ _ _ _ _ _ _ _ _ _ _ _ ___
hiI
--------------------~I
~F~
----------------------~*~------------------NOTES: 1. N = 4 FOR MODE 193N, 12 FOR MODE 1935 & 24 FOR MODES 193E & 193F
2. END OF MULTIFRAME ONL V
Parallel Interface-Transmit Signals-Modes 193N, S, E & F
RCLK
Rl·R8
•
RSER
RCHCLK
-.J
RCHSVNC _ _ _ _ _ _ _ _ _ _ _.;-_---'
RSVNC
NOTES: 1. N = 4 FOR MODE 193N, 12 FOR MODE 1935 & 24 for MODES 193E & 193F
Parallel Interface-Receive Signal_Modes 193N, S, E & F
6-69
T1/CEPT PCM Transceiver
R8070
T1 WAVEFORMS (Cont'd)
-------------
r
' ----CHANNEL 23
8
::~~:R:~~FM----------;.f------MU~~~:!~EO=+1-----
---~·+I----CHANNEL 24 ----+.......1+-----CHANNEL 1 - - - - - - - 1
1
8
1
4
5
6
7
8
11
TCLK
TSER
'V'LJ"'-C""'--fVl~J'VLJVL-:JVl.3
4
5
TSa1·---C-H-2-3-S-Ea-C-O-DE-----.
TSa5' _ _ _ _ _ _ _ _ _
~L-
rl
6
F·BIT SEa CODE
7 V'LJVL..fV'---1'''-C''''LJV'L "J'V'LJVL.JVLJV'--'V'-J
CH _
24 _
SEa
____
_CODE
_ _ _ _ _~
~
SEa
_ _ _ _ CH1
__
_CODE
_____
j~~~
J~
_ _ _ _ __
I ___________________
TMAX _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~r--lL
TFGEN_________________________________________--JX~
___________________________________
NOTES; 1. N = 4 FOR MODE 193N, 12 FOR MODE 1935 & 24 FOR MODES 193E & 193F
2. D1D, 02 & TSA = LOW
Serial Interface-Transmit Signals-Modes 193N, S, E & F
RCLK
RSER
F·BIT SEa CODE
Rsa1·
CH 23 SEa CODE
CH 24 SEa CODE
RSa5· _ _~_ _ _~~~~~~_ _ _~_ _ _~~~==~==
___
CH 1 SEa CODE
~-L-------------'\-
I
MyNC _____________________________________________~~L_______________________
NOTES; 1. N = 4 FOR MODE 193N, 12 FOR MODE 1935 & 24 FOR MODES 193E & 193F
2. D1D, D2, RSHIFT & RSR = LOW
Serial Interface-Receive Signals-Modes 193N, S, E & F
6-70
T1/CEPT PCM Transceiver
R8070
11 WAVEFORMS (Cont'd)
FRAME Nt OF
FRAME 1 OF
- - - - - - - - - - - MULTIFRAME M - - - - - - - - - - - > t - - - - - - MULTI FRAME M + l - - - ---~---
CHANNEL
24-----t~;._=->1+--CHANNEL
1--------1
TCLK
I
n·Ta
TCHCLK
~
I I I
I
I
II i
~
i
I
TCHSVNC _ _ _ _
~~~~~~
I I
('ti.X'fJ'tifXYJX'!,Y,XX'!J.Xi'lXixtttl ~rXX'tiXfXfYy.Xi,YJ..xxxm'ti.~HYJ..xxmXXXXXYXi$.'ttf.Xti.'fXf.X'/J.cr X>
I I
I
----'1
I
-'-I- - - - - -
' - - I
n
--------------------~h ~I--------------
TMAX 2
I
I
TFSIG
TFGEN
NOTES: 1. N = 4 FOR MODE 193N. 12 FOR MODE 1975
2. END OF MULTIFRAME ONL V
Parallel Interface-Transmit Signals-Modes 197N & S
RCLK
Rl·RB
II
RSER
RCHCLK
-.J
RCHSVNC _ _ _ _ _ _ _ _ _ _--7_ _..J
I
_IHBT
- - ,I~._________~I, - - - - ,I~___________~~
RSVNC
________________________________ I __________________
~rl~
NOTES: 1. N = 4 FOR MODE 197N & 12 FOR MODE 1973
Parallel Interface-Receive Signals-Modes 197N & S
6-71
T1/CEPT PCM Transceiver
R8070
T1 WAVEFORMS (Cont'd)
FRAME 1 OF
MULTIFRAME M + 1
FRAME N' OF
MULTIFRAME M
i------CHANNEL 2 3 - - - - - - 1 - - - - - CHANNEL 24 ----+~1-':...t_~--TCLK
F-BIT SEQ CODE
~~~;
m
345678FLl
TSER
TMAX ______________________________________
TFGEN
L-BiT SEQ CODE
CH 23 SEQ CODE
r----C-H-2-4-S-E-Q-C-O-D-E-----\
------------~
~----C-H-l-SE-Q-C-O-D-E---~
I
~~L------------------------------
I
I
-----------------------------~
NOTES: 1. N = 4 FOR MODE 187N & 12 FOR MODE 1875
2. D1D, D2 & TSA '" LOW
Serial Interface-Transmit Signals-Modes 197N & S
RCLK
RSER
~~~~Cj'~/~_J~J~~~_',~~_J~
::~~r---~CH~23~SE~Q~C~O~D~E~---.r-----=~-=~~=---,
RSYNC
-------------------------------------------~
NOTES: 1. N = 4 FOR MODE 197N & 12 FOR MODE 1975
2. Dl D, 02, RSHIFT & RSR = LOW
Serial Interface-Receive Signals-Modes 197N & S
6-72
~-----
R8070
T1/CEPT PCM Transceiver
CEPT PCM-30 OVERVIEW
The principal error conditions are:
CEPT PCM-30 FORMAT
1. Bipolar violation
2. Frame alignment error
3. Multiframe alignment error
CEPT PCM-30 is a PCM format for time-division multiplexing
30 voice (telephone) or data circuits onto a single transmission
path. This path is normally a dual tWisted-pair cable with digital
repeaters. There is a hierarchy of PCM formats within the CEPT
PCM system that defines further time-division multiplexing of
multiple PCM-30 lines.
A bipolar violation is a failure to meet the Alternate Mark Inversion (AMI) line code of CEPT PCM-30. AMI dictates that 1s
(marks) are transmitted alternately as positive or negative pulses;
zeros are transmitted as zero volts.
Prior to transmission, each voice circuit is sampled at 8 kHz using
an 8-bit A-law companding analog-to-digital converter. The
resulting 64 kbps (8 bits x 8 kHz) signal is time-division multiplexed with 29 other sampled channels, plus 2 channels of alignment and signaling bits, to produce a frame of 256 bits
(32 channels x 8 bits). Since each voice circuit is sampled at
8 kHz, the frame rate is 1251's. To transmit 256 bits in 1251's
requires a bit rate of 2.048 Mbps, hence the standard CEPT
PCM-30 clock frequency of 2.048 MHz.
Clock Recovery. In order to guarantee adequate clock recovery
from the received data, a minimum "ones density" must be
observed. HDB3 represents a group of 4 zeros by a predefined
code that includes an intentional bipolar violation. At the receiver,
the code is recognized and the original 4 zeros are restored.
The R8070 supports all major requirements of the CEPT PCM-30
system, including channel data recovery, signaling, alarm indication, error reporting, and zero suppression to satisfy the ones
density requirement.
Signaling Data. Signaling data, such as on-hook and off-hook
conditions, dialing digits, call progress, etc., associated with each
voice circuit is transmitted within time slot 16. This is known as
common channel signaling since a single (common) channel is
dedicated for the signaling data of all voice circuits within the
PCM link.
CEPT MODES DESCRIPTION
One of the two CEPT modes can be selected by configuring the
M1-M4 lines as shown in the CEPT Mode Selection Table.
In order for each channel to be distinguished at the receiver,
a frame alignment signal (0011011) is transmitted in bits 2-8
of time slot 0 in alternating frames. The remaining bit 1 of time
slot 0 carries the International bit. In frames not containing the
frame alignment signal, bit 2 is fixed at 1 to avoid imitation of
that signal. The remaining bits carry National and International
signaling and alarm indication for loss of frame alignment.
256S Mode. The 256S mode implements CEPT PCM-30 format
at 2.048 Mbps with 16 frames per multiframe and 32 time slots
per frame. ABCD common channel signaling is supported in time
slot 16. There are 256 bits per frame.
The frame alignment signal (in time slot 0) and the multiframe
alignment signal (in time slot 16) are generated by the R8070
transmitter and recovered by the receiver.
In order for each frame to be distinguished at the receiver (for
recovery of ABCD signaling data), a multiframe alignment signal
is transmitted in bits 1-4 of time slot 16 of frame O. Bit 6 of the
same time slot indicates loss of multiframe alignment. Bits 5,
7 and 8 carry Extra-bit signaling.
National-bit (time slot 0), International-bit (time slot 0) and Extrabit (time slot 16) signaling is provided.
HDB3 zero suppression is standard but may be disabled for
transparent operation.
To recap, the PCM structure consists of: a multiframe of
16 frames; a frame of 32 time slots (30 voice channels plus 2
alignment and signaling time slots); and 8 bits per time slot.
256N Mode. The 256N mode also implements CEPT PCM-30
format at 2.048 Mbps but without ABCD common channel signaling. There are 2 frames per multiframe and 32 time slots per
frame. A data link channel is implemented via time slot 16, in
place of ABCD signaling. There are 256 bits per frame.
Alarms and Error Conditions. In addition to channel and signaling data, CEPT defines several alarm and error conditions that
must be monitored and reported. The principal alarms are:
1.
2.
3.
4.
Red Alarm
Yellow Alarm
Multiframe Red Alarm
Multiframe Yellow Alarm
The frame alignment signal in time slot 0 is generated by the
transmitter and recovered by the receiver. There is no multiframe
alignment signal and so the multiframe structure degenerates
to 2 frames, which are distinguished by time slot 0 content.
A Red Alarm is produced by a receiver to indicate that it has
lost frame alignment. A Yellow Alarm is returned to the transmitting terminal to report a loss of frame alignment at the
receiving terminal. Normally, a CEPT terminal will use the
receiver's Red Alarm to request that a Yellow Alarm be transmitted. The multiframe alarms refer to loss of multiframe
alignment.
National-bit and International-bit signaling is provided in time
slot O. There is no Extra-bit signaling as time slot 16 is dedicated
to the data link.
HDB3 zero suppression is standard but may be disabled for
transparent operation.
6-73
II
T1/CEPT PCM Transceiver
R8070
CEPT PCM-30 OVERVIEW (Cont'd)
.
__. _ - - - - - - - - - - - ,
TIME SLOT 16
TIME SLOT 0
a. EVEN FRAMES (0,2,4-14)
a. FRAME
TIME SLOTS 1-15, 17-31
0
II I I I, II I II I, I
0
0
0
T
l
J
FAS
CHANNEL DATA
b. FRAMES 1-15
b. ODD FRAMES (1,3,5-15)
8 BITS/
TIME SLOT
32 TIME SLOTS/FRAME
NOTES:
I
N
A
FAS
ABCD
X
Y
MAS
International Bit
National Bit
Alarm Indication Signal (Loss of Frame Alignment-Red Alarm)
Frame Alignment Signal, occupies alternate
(but not necessar,lly even) frames
ABCD Signaling Bits
Extra Bit
Loss of Multlfrarne Alignment
Multiframe Alignment Signal
----.---------'
-------~-----------------------.-- ..
CEPT PCM-30 Format
E
ve,
Nu_m~ _b_e_r
CEPT PCM-30 Time Slot and Channel Numbering
CEPT PCM-30 Hierarchy
Number of
__--'___v_O_ic_e_;_i_ic_uits
Bit Rate
Time Slot
-'~---'(':--1'-i-'~'-i--I
1920
139264
7680 --.-l~5 148 _
J
~"' "
Chann~
FAS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
10
11
12
14
15
NOTES FAS
Time Slot
Channel
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
MAS
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
I
Frame Alignment Signal, International and
Nallonal Bits, and Alarm Indication Signal (loss
of frame alignment)
MAS Multlframe Alignment Signal, ABeD Signaling,
Extra Bits, and Loss of Multlframe Alignment
6-74
R8070
T1/CEPT PCM Transceiver
CEPT FUNCTIONAL DESCRIPTION
for systems that guarantee Is density by other means. HDB3
encoding applies only to the TPOS and TNEG outputs; TNRZ
is unaffected.
TRANSMIT SECTION
The transmit section of the R8070 provides the data formatting,
signaling and alarm indication functions required for PCM
transmission according to CCITT G.732 and applicable sections
of G.703.
Frame and Multiframe Formatting
The transmitter contains frame and multiframe counters which
maintain the correct PCM format by inserting the frame alignment signal into time slot 0, and the multiframe alignment signal
into time slot 16. The frame counter may be reset to bit I, time
slot 0 (TFSYNC high), and the multiframe counter may be reset
to frame 0 (TMSYNC high).
PCM Channel Data
Data Input. Data is clocked into the transmitter either serially
(via TSER) or in parallel form (via Tl-T8), on the rising edge
of the transmitter clock (TCLI<). The externally provided TCLK
normally has a rate of 2.048 MHz.
Signaling
ABCD/Link Signaling. In 256S mode, the 8 bits of time slot 16
of frames 1-15 contain two sets of ABCD signaling bits for
channels 1-30. The ABCD signaling bits for transmission in time
slot 16 are input via TABCD or TSER-selected by TSIGMD(Serial Interface) or Tl-T8 (Parallel Interface). TTS16 may be
used to gate or clock in ABCD bits from external circuits. "All
Is" may be transmitted in time slot 16 (TDAT1S high).
For a serial data interface, Transmit Sequence signals
(TSQ1-TSQ5) specify the binary value of the next channel to
be sampled. These signals, which can be used for control of
channel banks, may be advanced by one bit time using Transmit
Sequence Advance (TSA).
For a parallel data interface, timing signals are provided at the
channel rate (TCHCLI<) and at the frame rate (TCHSYNC) for
clocking data interface circuits.
In 256N mode, there are 2 frames per multiframe and no
multiframe alignment signal. Both time slots 16 carry data link
information. If TSIGMD low, link bits are input via TSER
(TLNKMD high, Serial Interface), T1-T8 (TLNKMD high, Parallel
Interface) or TLINK (TLNKMD lOW). If TSIGMD high, the data
link bits are set to 1. TTS16 may be used to clock link data to
the TSER or Tl-T8 inputs. TLCLK may be used to clock link
data to the TLINK input.
Data Output. The serial PCM data is clocked out of the transmitter on the rising edge of TCLK and is available on two outputs
simultaneously (TNRZ, TPOS and TNEG). TNRZ provides a
standard, nonreturn-to-zero (NRZ) TTL level version olthe data.
TPOS and TNEG carry the same NRZ TTL level data as TNRZ
except that the Is are routed alternately to TPOS and TNEG.
This facilitates the translation into the Alternate Mark Inversion
(AMI) line code, where 1s are represented alternately as positive
and negative pulses.
Natlonal-, Intemational- and Extra-Bit Signaling. The National
bits are located in bits 4-8 of time slot 0 of nonframe-alignment
frames. The International bit is located in bit 1 of time slot O.
The Extra bits are located in bits 5, 7 and 8 of time slot 16,
frameO.
Loopback. The outputs TPOS and TNEG may be internally
connected to RPOS and RNEG (TLOOP high) for loopback
testing. During loopback, the external TPOS and TNEG carry
a continuous stream of Is; TNRZ is unaffected.
These bits are input to the transmitter via TNBITS, TIBITS and
TXBITS. For the Serial Interface, these inputs are sampled
instead of TSER at the appropriate bit sampling time. TNSYNC
may be used to gate the National bits to either TNBITS or TSER.
For the Parallel Interface, these inputs are sampled and OR'd
with the equivalent bit on the parallel inputs T1-T8. This allows
either T1-T8 or TNBITSITIBITSfTXBITS to be the source.
Idle Code. Idle code (01010100) may be substituted in place
of the normal channel data, on a channel-by-<:hannel basis, using
TIOLE.
HDB3 Encoding. HDB3 encoding is handled automatically by
the R8070. The entire data stream, including time slots 0 and
16, is scanned for an occurrence of four consecutive zeros. Any
such occurrence is replaced by the appropriate HOB3 code. The
HOB3 encoder may be disabled by connecting RPOS to RNEG
(and using an NRZ form of input data). This invokes the
transparent mode where zeros are transmitted as zeros,
regardless of the 1s denSity. This may be used for testing or
In 256N mode, the Extra bits are not available, as both time slots
16 carry link data.
Alarms
A Yellow Alarm is transmitted (bit 3 = 1 in time slot 0 of
nonframe-alignment frames) when requested by TYEL.
CEPT Operating Mode Selection and Characteristics
Mode
2568
256N
Data Rate
(Mbps)
Mode Select Linea
Bits/Frame
FrameslMultlframe
16
2
Notes: HDB3: High Density Bipolar 3·zero maximum
2.048
256
Signaling
Yes
No
Zero Suppression
HDB3
HDB3
6-75
Ml1M21M31M4
0
0
0
0
1
0
0
0
I
I
I
PCM Format
CEPT
PCM-30
•
T1/CEPT PCM Transceiver
R8070
Loopback. Under control of TLOOP, the normal external inputs
on RPOS and RNEG may be replaced With an internalloopback
to the internal TPOS and TNEG. When switching in and out of
loopback, resynchronization will usually take place because the
two signals will not normally have identical framing.
CEPT FUNCTIONAL DESCRIPTION (Cont'd)
A Multiframe Yellow Alarm (bit 6 = 1 in time slot 16, frame 0)
IS automatically transmitted if an error occurs In two consecutive
multiframe alignment signals, or all time slot 16 bits are 0 for
at least one multiframe.
Idle and Digital Milliwatt Codes. The normal received data may
be replaced, on a channel-by-channel basIs, either with Idle code
(using RIDLE) or with digital milliwatt (using RMW).
Clocks
The R8070 provides clock signals at the bit. channel, frame and
multiframe rate to facilitate data clocking and timing of external
circuitry.
Rate
Clock
Description
Bit
TCLK
Same period as bit time. Rising edge
clocks all inputs and outputs.
Channel
TCHCLK
T1-T8 sampled at the rising edge.
Frame
TCHSYNC
TTS16
TLCLK
TNSYNC
High for sampling of time slot a
High for sampling of time slot 16.
Indicates TLiNK sampling.
High for sampling of TNBITS.
TMAX
High for sampling of the next to last
bit In mulliframe.
TMFA
High lor sampling of frame O.
Multiframe
HDB3 Decoding. HDB3 decoding is handled automatically by
the R8070. The Incommg data stream IS scanned for occurrences of the HDB3 code. These are replaced with four zeros,
thus restoring the original data. Both senal (RSER) and parallel
(R1-R8) data outputs include HDB3 corrections.
Synchronization
The serial bit stream at RPOS and RNEG IS examined by the
synchronizer, and the framing pattern is located through a flvestage process that eliminates erroneous bit candidates.
Synchrollization IS achieved in less than 10 ms.
A generalized form of the synchronization algorithm is descnbed
in the R80?O Designer's GUide (Order No. 313). After a power-up
reset (PUP low for at least 16 cycles), the receiver begins to
search for frame and multlframe alignment. When synchronization is achieved, the receiver monitors the frame and multlframe
alignment signals for errors. A Red Alarm is generated (RRED
high) if frame alignment IS lost; a Multiframe Red Alarm is
generated (RMRED high) if multiframe alignment is lost. The
criterion for loss of frame alignment is "4 out of 5" errors in the
frame alignment Signal or "3 out of 5" errors plus a multiframe
alignment signal error. The critenon for loss of multlframe alignment is 2 consecutive errors In the multiframe alignment signal.
RECEIVE SECTION
The receive section of the R8070 provides the synchronization,
signaling and alarm indication functions reqUired for reception
of PCM data formatted according to CCIlT G.732 and applicable
sections of G. 703.
The receiver can be forced to restart a synchrOnization search
(RMRST high) or to skip a bit while synchronized (RSRCH low).
PCM Channel Data
Data Input. Received Unipolar data on RPOS, denved from the
received positive pulses, and RNEG, denved from the received
negative pulses, IS clocked IOta the receiver on the rising edge
of RCLK.
D1 D and D2 high prevents resynchronization after loss of frame
alignment. This mode of operation may be used during testing.
Signaling
Data Output. The received data IS clocked out on the rising edge
of RCLK and is available in senal form on RSER and, If a Parallel
Interface is selected. In parallel (8-bit channel) form on R1-R8.
ABCD/Link Signaling. In 256S mode, with a Senal Interface,
the ABCD Signaling bits, contained Within time slot 16 of
frames 1-15 are output on RABCD. The 8-bit senal data on
RABCD contains the ABCD bits In bit positions 1-4 and repeated
in bit positions 5-8, aligned With the corresponding channel currently emergmg from RSER. During time slot 0, RABCD contains the multlframe alignment Signal (0000) In bit positions 1-4,
repeated in bit positions 5-8. Dunng time slot 16, RABCD is not
defined and should not be used.
For a senal data IIlterface. Receive Sequence signals
(RSQ1-RSQ5) specify the bmary value of the current channel
The sequence may be retarded by one bit-time usmg Receive
Sequence Retard (RSR). If RSHIFT IS high. the sequence IS
"shifted" (upper bank and lower bank channel numbers are interChanged), so that channel time slot 1 becomes 16, 2 becomes
17, and so on. Time slot 0 and time slot 16 codes remain the
same.
In 256S mode, with a Parallel Interface, time slot 16 data is
available m parallel on R1-R8 With the normal channel timing.
External circuitry IS normally used to recover the ABCD bits for
each channel. Each time slot 16 (of frames 1-15) contains four
signalmg bits (ABCD) for each of a pair of channels. The 30 PCM
channels are grouped into 15 pairs as follows: Channel 1 of the
current frame With channel 16 of the prevIous frame; channel 2
of the current frame With channel1? of the prevIous frame, etc.
For a parallel data Interface, timing signals are provided at the
channel rate (RCHCLK) and the frame rate (RCHSYNC) for
clocking data Interface Circuits. RWIHBT IS high for 2 bit times
to "cover" the change of data on R1-R8. This may be used to
inhibit the wnte signal for external memory
6-76
T1/CEPT PCM Transceiver
R8070
CEPT FUNCTIONAL DESCRIPTION (Cont'd)
Clocks
The A8070 provides clock signals at the bit, channel, frame and
multiframe rate to facilitate data clocking and timing of external
circuitry.
Note
The CCITT numbering scheme for the 32 time slots per
frame is time slot 0 through time slot 31; 30 of these time
slots (1-15 and 17-31) are occupied by 30 PCM channels,
referred to as channel time slots 1-15 and 16-30.
Aate
ATS16 high indicates time slot 16 is currently available at A1-A8
or ASEA.
In 256N mode, there is no multiframe alignment signal or ABCD
signaling bits. Time slot 16 provides a 64 kbps data link. Link
data is output in serial form on ALINK in association with the
clock, ALCLK at the same continuous 64 kbps rate as the input
TLINK.
Description
Bit
ACLK
Same period as bit time. Aising edge
clocks all inputs and outputs.
Channel
ACHCLK
AWIHBT
A1-A8 changes at the rising edge.
Memory-write inhibit at A1-A8
change.
Frame
ACHSYNC
ATS16
ALCLK
ANBITS
AIBITS
AXBITS
High for output of time slot O.
High for output of time slot 16.
Indicates ALINK data bit ready.
High for output of National bits.
High for output of International bits.
High for output of Extra bits.
Multiframe
ASYNC
AMFA
High for first bit of multiframe.
High during frame O.
ALINK1 high indicates reception of 255 consecutive 1s in the
data link channel (time slot 16).
Natlonal-, International- and Extra-Bit Signaling. AN BITS,
AIBITS AND AXBITS are timing signals which indicate when
the respective N-, I- and X-bits are available on ASER. See the
CEPT Transmit Section for bit locations.
Clock
In 256N mode, the Extra bits are not available, as both time
slots 16 carry link data.
Alarms
Name
AAED
AMRED
AYEL
AMYEL
FEAR
FMEAA
AVLL
Mode
(N or S)
N,S
S
N,S
S
N
S
N,S
Alarm Indication
Loss of frame alignment.
Loss of multiframe alignment.
Yellow Alarm.
Multiframe Yellow Alarm.
Frame alignment error.
Frame, multiframe alignment error.
Bipolar violation.
•
6-77
R8070
T1/CEPT PCM Transceiver
CEPT INTERFACE DESCRIPTION
TIBITS
TNBITS
TLINKlTDAT1S
TLNKMDITXBITS
TLCLKlTMFA
TTS16
(IA) }
(IB)
(IC)
(10)
(OH)
(OJ)
TNRZ
TMAX
RANSMITTER
FRAMING
MODEDEPENDENT
TRANSMIT
INTERFACE
}
--~-----!'~~---------------TSQ1-TSQ5
TCHCLK
TCHSYNC
DEDICATED { TCLK
TRANSMIT
INTERFACE
TPOS
TO LIU
TNEG
8
(PS09)}
(PS010)
PARALLEL
TRANSMIT
INTERFACE
T1-T8 (PSI1-PSI8)
R1-R8 (PS01-PS08)
DEDICATED {
RECEIVE
RCLK
INTERFACE
RPOS
TO LIU
RNEG
RCHCLK
RCHSYNC
RWIHBT
RECEIVER
PUP
Vee
V••
RSER
RVLL
RYEL
RRED
RSYNC
RMRST
RSRCH
RIDLE
RMW
RTS16
RIBITS/RMFA
RLINK1/RMRED
FERRlFMERR
RNBITS
RLINKIRMYEL
RLCLKlRXBITS
}
(PS011)
(PS012)
(PS013)
5
PARALLEL
RECEIVE
INTERFACE
(OB)
(OA)}
(OC)
(00)
(OE)
(OF)
(OG)
DEDICATED
RECEIVE
INTERFACE
FRAMING
MODEDEPENDEN T
RECEIVE
INTERFACE
Ml-M4
PIS
R8070 Input/Output Signals - CEPT Modes
6-78
(PS06)
(PSll)
(PSI2)
(PSI3)
(PSI4)
010
02
(PSI6)
(PSI7)
}
RSHIFT
RSR
(PSIS)
(PSI8)
}
RSQ1-RSQS (PS01-PSOS)
RIBITS
RABCD
}
(PS09_PS013)}
TNSYNC
TSER
TSIGMD
TABCD
TSA
(PS07)
(PS08)
SERIAL
TRANSMIT
INTERFACE
SERIAL
COMMON
INTERFACE
SERIAL
RECEIVE
INTERFACE
T1/CEPT PCM Transceiver
R8070
CEPT INTERFACE DESCRIPTION (Cont'd)
Pin Assignments-Dedicated Signals
Pin No.
Pin NameJSymbol
1/0
QUIP
PLeC
TCLK
TFSYNC
TMSYNC
TLOOP
TIDLE
TYEL
I
I
I
I
I
I
9
3
4
16
15
8
10
3
4
17
16
8
Transmit
Transmit
Transmrt
Transmit
Transmit
Transmit
Clock
Frame Sync
Multiframe Sync
Loop
Idle
Yellow Alarm
TPOS
TNEG
TNRZ
TMAX
0
0
0
0
18
17
19
10
19
18
20
11
Transmit
Transmit
Transmit
Transmit
Unipolar Positive
Unipolar Negative
Non·Return·to-Zero
Maximum
RCLK
RPOS
RNEG
RIDLE
RMW
RMRST
RSRCH
I
I
I
I
I
I
I
56
55
59
58
57
56
55
42
44
Receive
Receive
Receive
Receive
Receive
Receive
Receive
Clock
Unipoiar Positive
Unipolar Negative
Idle
Milliwatt
Master Reset
Search
RSER
RSYNC
RVLL
RYEL
RRED
0
0
0
0
0
37
53
39
28
51
38
54
40
Receive
Receive
Receive
Receive
Receive
Serial Data
Sync
Bipolar Violation
Yellow Alarm
Red Alarm
PIS
I
I
I
I
I
11
12
13
14
32
12
13
14
15
34
Framing Mode Select 1
Framing Mode Select 2
Framing Mode Select 3
Framing Mode Select 4
Parallel/Senal Interface Select
PUP
Vcc
Vss
I
I
I
39
64
41
68
35
Power·Up
+5V Power
Ground
Ml
M2
M3
M4
54
53
52
40
41
50
33
30
Signal Name
Pin Assignments-ParaliellSerial Interface.Dependent Signals
Pin No.
Parallel Interface (PIS
Pin Name
110
PSll
PSI2
PSI3
PSI4
PSI5
PSI6
PSI7
PSIS
I
I
I
I
I
I
I
I
2
1
2
1
63
67
62
61
60
59
58
66
65
T4
T5
64
63
62
T6
T7
T8
PSOl
PS02
PS03
PS04
PS05
PS06
PS07
PS08
PS09
PS010
PSOll
PS012
PS013
0
0
0
49
48
47
0
46
0
0
0
0
0
0
0
0
0
45
44
52
51
50
49
48
47
46
45
24
25
27
28
29
R2
R3
R4
RS
R6
R7
R8
TCHCLK
TCHSYNC
RCHCLK
RCHSYNC
RWIHBT
QUIP
43
42
23
24
25
26
27
PLeC
Symbol
~}
m}
=High)
Signal Name
Serial Interface.J.P1S
Symbol
RSHIFT
D1D
D2
RSR
Transmit Senal
Transmit Signaling Mode
Transmit Signaling Input
Transmit Sequence Advance
Receive Shift
D1D Channel Sequence Select
D2 Channel Sequence Select
Receiver Sequence Retard
~}
Receive Sequence Code Bits 1-5
TSER
TSIGMD
TABCD
Transmit Channel Data Bits 1-8
Receive Channel Data Bits 1-8
Transmit Channel Clock
Transmit Channel Sync
Receive Channel Clock
Receive Channel Sync
Receive Wnte Inhibit
Notes:
1. Different signal than T1 modes.
6-79
=Low)
Signal Name
TSA
RS02
RS03
RS04
RS05
TNSYNC'
RIBITS'
RABCD'
~}
TS02
TS03
TS04
TS05
Transmit National Bit Sync
Receive International Bits
Receive Signaling Output
Transmit Sequence Code Bits 1-5
•
R8070
T1/CEPT PCM Transceiver
CEPT INTERFACE DESCRIPTION (Cont'd)
Framing Mode-Dependent Signals
Pin No.
256N Mode
256S Mode
Pin Name
1/0
QUIP
PLCC
Symbol
IA
IB
IC
I
I
I
I
5
5
6
57
7
6
61
7
TIBITS
TNBITS
TLiNK
TLNKMD
Transmit
Transmit
Transmit
Transmit
International Bits
National Bits
Link
Link Mode
TIBITS
TNBITS
TDATIS
TXBITS
Transmit
Transmit
Transmit
Transmit
0
0
0
0
0
0
0
0
0
34
31
30
29
22
35
36
21
20
36
33
32
31
23
37
38
22
21
RTS16
RIBITS
RLlNKl
FERR
RNBITS
RLiNK
RLCLK
TLCLK
TIS16
Receive Time Slot 16
Receive I nternatlonal Bits
Receive Link 1
Framing Error
Receive National Bits
Receive Data Link
Receive Link Clock
Transmit Link Clock
Transmit Time Slot 16
RTS16
RMFA
RMRED
FMERR
RNBITS
RMYEL
RXBITS
TMFA
TIS16
Receive Time Slot 16
Receive Multiframe Alignment
Receive Mulliframe Red
Frame or Multiframe Error
Receive National Bits
Receive Multiframe Yellow
Receive Extra Bits
Transmit Multlframe Alignment
Transmit Time Slot 16
10
OA
OB
OC
00
OE
OF
OG
OH
OJ
Signal Name
6-80
Symbol
Signal Name
International Bits
National Bits
Data Ones
Extra Bits
R8070
T1/CEPT PCM Transceiver
CEPT INTERFACE DESCRIPTION (Cont'd)
Signal Definition - Dedicated Signals
Pin Namel
Symbol
I/O
Signal Name/Description
TCLK
I
Transmit Clock. TCLK is the transmitter clock input and must be present for normal transceiver (transmitter or
receiver) operation. TCLK must be in the range 100 kHz - 3.1 MHz and will normally be 2.048 MHz for CEPT
format. All inputs and outputs are clocked on the rising edge of TCLK.
TFSYNC
I
Transmit Frame Sync. TFSYNC high resets the bit counter to the beginning of a frame. The counter restarts on the
first rising edge of TCLK after TFSYNC goes low. TFSYNC should be synchronous with TCLK to ensure setup and
hold times. TFSYNC need only be applied to change the transmitter frame alignment.
TMSYNC
I
Transmit Multiframe Sync. TMSYNC high resets the frame counter to frame O. TMSYNC low enables the frame
counter. TMSYNC need only be applied to change the transmitter multiframe alignment. TFSYNC is normally
applied with TMSYNC to align to the first bit of the multiframe.
TLOOP
I
Transmit Loop. TLOOP high Invokes loopback mode. where TPOS and TNEG are internally routed to RPOS and
RNEG, respectively. TPOS and TNEG external signals carry alternate 1s representing a continuous stream of 1s.
TLOOP does not affect TNRZ. ThiS Internal looping has one bit time less delay than an equivalent external looping.
TIDLE
I
Transmit Idle. TIDLE high causes the idle code (01010100) to be transmitted in the next channel, In place of the
normal data. This substitution continues for each channel In which TIDLE is high.
TYEL
I
Transmit Yellow Alarm. TYEL high causes transmission of a Yellow Alarm' Bit 3 -1 In time slot 0 of nonframe·
alignment frames.
TPOS, TNEG
0
Transmit Unipolar Positive, Unipolar Negative. TPOS and TNEG are the "unlpolar·paired" TTL, NRZ outputs for
transmitted data. Binary 0 IS coded as a low (0) level on both outputs Binary 1 IS coded as a high (1) level on
TPOS or TNEG, alternately. TPOS and TNEG allow the direct generation of AMI line code in which a 1 (mark) IS
alternately represented as a positive or negative pulse. There IS an 8·bIt throughput delay between the TSER Input
and the TPOSITNEG outputs.
TNRZ
0
Transmit Non-Return-to-Zero. TNRZ is the TTL, NRZ output for transmitted data. This output IS unaffected by
TLOOP or by HDB3 zero suppression coding. There is an B-bit throughput delay between the TSER Input and the
TNRZ output.
TMAX
0
Transmit Maximum. TMAX is high for one bit time per multl/rame cOincident with the sampling of the next to last
serial bit of a multiframe.
RCLK
I
Receive Clock. RCLK is the receiver clock input and must be present for normal transceiver operation. All Inputs
and outputs are clocked on the rising edge of RCLK RCLK must be In the range 100 kHz - 31 MHz and will
normally be 2.048 MHz for CEPT format
RPOS,RNEG
I
Receive Unipolar Positive, Unipolar Negative. RPOS and RNEG are the Inputs for received data recovered from
the positive and negative AMI hne pulses. RPOS and RNEG should have TTL levels and may be of either NRZ or
RZ form. If RPOS is strapped to RNEG (and given composite RPOS/RNEG data) the first occurrence of a 1 will
Invoke the transparent mode in which HDB3 zero suppression IS disabled In both the receiver and the transmitter.
RIDLE
I
Receive Idle. RIDLE high causes data In the next received channel to be substituted With the idle code (01010100).
The substituliOn continues for each channel In which RIDLE IS high RIDLE and RMW should not be high
simultaneously.
RMW
I
Receive Milliwatt. RMW high causes data in the next received channel to be substituted with the digital milliwatt
code; a repeating pattern of eight 8·blt bytes that translate Into a 1 kHz signal at a level of 1 mW The substituliOn is
performed for each channel In which RMW IS high. RMW and RIDLE should not be high Simultaneously
RMRST
I
Receive Master Reset. RMRST high resets the master state sequencer In the synchronizer to ItS Inllial (WAIT) state.
RMRST low allows synchronization to proceed.
RSRCH
I
Receive Search. RSRCH low prevents the master state sequencer In the synchronizer from proceeding out of the
WAIT state. It does not force the synchronizer to the WAIT state (see RMRST). If RSRCH IS low while the receiver IS
In frame alignment (RRED low), bit 5 of time slot 0, frame 0 IS skipped ThiS allows recenterlng of elastic stores.
6-81
•
T1/CEPT PCM Transceiver
R8070
CEPT INTERFACE DESCRIPTION (Cont'd)
Signal Definition - Dedicated Signals (Cont'd)
Pin Namel
Symbol
1/0
Signal NamelDescriptlon
RSER
0
Receive Serial Data. RSER IS the serial data output including HDB3 decoding. The throughput delay from
RPOS/RNEG to RSER IS 14 cycles of RCLK. RSER IS always valid, regardless of the synchronizer state.
RSYNC
0
Receive Sync. RSYNC IS high during the first bit of each multiframe while the receiver is synchronized
RVLL
0
Bipolar Violation. RVLL high indicates that the 1 currently at RSER resulted from a bipolar violation.
RYEL
0
Receive Yellow Alarm. RYEL high Indicates a received Yellow Alarm. Bit 3=1 in time slot 0 of nonframe·
alignment frames.
RRED
0
Receive Red Alarm. RRED high Indicates loss of frame alignment. RRED low indicates correct frame alignment.
Multlframe alignment is separately indicated by RMRED.
M1-M4
I
Framing Mode Select. M1-M4 select the framing mode as follows (See CEPT Mode Selection Table for additional
mode information)'
M1
o
o
M2
o
1
M3
o
o
M4
CEPT Mode
256S
256N
o
o
PIS
Parallel/Serial Interface Select. PIS selects parallel (PIS high) or senal (PIS low) operation of the PSI1-PSIS and
PS01-PS013 pins.
PUP
Power-up. PUP initializes the RS070 transmitter and receiver. It Includes TFSYNC, TMSYNC and RMRST reset
functions. PUP sets all outputs, except OJ, to a high-Impedance state, to faCIlitate tesllng of peripheral CirCUitry.
Vee
+5V Power. +5 VDC power
Ground. Power and signal ground.
6-82
T1/CEPT PCM Transceiver
R8070
CEPT INTERFACE DESCRIPTION (Cont'd)
Signal Definition a. Parallel Interface (PIS
Pin Name/
Symbol
I/O
Parallel/Serial Interface-Dependent Signals
High)
Signal Name/Description
Symbol
PSI1-PSI8
I
Tl-TS
Transmit Channel Data Bits 1-8. Tl-TS are the parallel Inputs for channel data and, optionally, link
data They are clocked Into the transmitter at the rising edge of TCHCLK, by the rrslng edge of
TCLK. The fallong edge of TCHCLK may be used to present the next channel data at Tl-TS
PS01-PS08
0
Rl-R8
Receive Channel Data Bits 1-8. Rl-R8 are the parallel outputs for channel data. The channel data
IS available for a complete channel time and IS updated at the rrslng edge of RCHCLK The failing
edge of RCHCLK may be used to clock this data Into external buffers Rl-R8 are only valid while
the receiver IS synchronized; RSER, the serral data output, IS always available and always valid
PS09
0
TCHCLK
Transmit Channel Clock. TCHCLK IS a channel-rate clock whose rrslng edge Indicates that parallel
data on Tl-T8 IS being sampled The lailing edge IS used to present the next channel's data on
Tl-T8. TCHCLK IS low for 4 bit times
PSOIO
0
TCHSYNC
Transmit Channel Sync. TCHSYNC IS a frame-rate Signal which IS high for 8 blilimes The rrslng
edge precedes the sampling of time slot a by one' bit time. The failing edge precedes time slot 1
sampling by one bit time
PS011
0
RCHCLK
Receive Channel Clock. RCHCLK IS a channel-rate clock where rrsrng edge Indicates that new
channel data has been output to Rl-R8. The falling edge may be used to clock this data Into
external buffers. RCHCLK IS low for 4 bit times
PS012
0
RCHSYNC
Receive Channel Sync. RCHSYNC IS a frame-rate Signal which IS high for 8 bit times The rrslng
edge occurs one bit time after the output time slot a of data on Rl-R8 The failing edge occurs one
bit time after the output time slot 1 of nata on Rl-R8
PS013
0
RWIHBT
Receive Write Inhibit. RWIHBT IS a channel-rate Signal, 2 bit times high, which "covers" the
change of parallel data on Rl-R8 RWIHBT IS high for one bit time before and after the rrslng edge
of RCHCLK
•
6-83
R8070
T1/CEPT PCM Transceiver
CEPT INTERFACE DESCRIPTION (Cont'd)
Signal Definition - Parallel/Serial Interface-Dependent Signals (Cont'd)
b. Serial Interface (PIS = Low)
Pin Name/
Symbol
I/O
Signal Name/Description
Symbol
PSII
I
TSER
Transmit Serial. TSER is the serial input for the channel data and, optionally, signaling data.
PSI2
I
TSIGMD
Transmit Signaling Mode. In mode 256S: TSIGMD low selects TABCD as the source for ABCD
signaling bits of time slot 16, TSIGMD high selects TSER as the source. In mode 256N: TSIGMD
low specifies TLNKMD as the selector for the source of time slot 16 data link signaling, TSIGMD
high causes all Is to be transmitted in time slot 16.
PSI3
I
TABCD
Transmit Signaling Input. TABCD is the input for ABCD signaling in time slot 16.
PSI4
I
TSA
Transmit Sequence Advance. TSA high advances the standard timing of TSQ1-TSQ5 and
TSIGSQ by one bit time.
PSI5
I
RSHIFT
Receive Shift. RSHIFT high shifts the RSQ1-RSQ5 sequence of channel numbers from 1 to 16,
2 to 17, ... 15 to 30. Time slot 0 remains as 00000, time slot 16 remains as 11111.
PSI6, PSI?
I
DID, D2
Channel Sequence Select. Dl D and 02 channel assignments are not required for CEPT; set to
0,0 for normal operation; set to 1,1 for synchronization lock which inhibits resynchronization after
loss of frame alignment.
PSI8
I
RSR
Receive Sequence Retard. RSR high delays the standard timing of RSQ1-RSQ5 and RSIGSQ
by one bit time.
PS01-PS05
0
RSQ1-RSQ5
Receive Sequence Code Bits 1-5. RSQ1-RSQ5 is the binary value of the currently received
channel (1-30), plus time slot 0 (00000) and time slot 16 (11111).
PS06
0
TN SYNC
Transmit National Bit Sync. TNSYNC goes high to indicate sampling of the National bits
(bits 4-8 of time slot 0 of nonframe-alignment frames). TN SYNC rising edge coincides with the
sampling of bit 3; the falling edge coincides with the sampling of bit 8, of the above time slot.
PS07
0
RIBITS
Receive International Bits. RIBITS high indicates that the International bit (bit 1, time slot 0) is
present at RSER.
PSOB
0
RABCD
Receive Signaling Output. RABCD IS the output of the received ABCD signaling bits for the
channel currently emerging from RSER.
PS09-PSOI3
0
TSQ1-TSQ5
Transmit Sequence Code Bits 1-5. TSQ1-TSQ5 is the binary value of the currently sampled
channel (1-30), plus time slot 0 (00000) and time slot 16 (11111).
6-84
T1/CEPT PCM Transceiver
R8070
CEPT INTERFACE DESCRIPTION (Cont'd)
Signal Definitions Pin
Name
110
Signal
Symbol
IA
I
TIBITS
IB
I
TNBITS
IC
I
TLiNK
TDAT1S
ID
I
TLNKMD
TXBITS
OA
0
RTS16
OB
0
RIBITS
RMFA
OC
OD
0
0
RLlNKl
OF
0
RLiNK
RMYEL
RLCLK
RXBITS
OJ
0
0
·
TLCLK
I
-
I
I
·
· ·
·
·
·
·
-
-
-
-
·
RNBITS
OH
-
FERR
0
0
· ·
··
·
- ·
-
OE
OG
Signal Name/Description
256N 2568
RMRED
FMERR
Framing Mode-Dependent Signals
Mode
-
Transmit International Bits. TIBITS IS the I-bit Input for International-bit signaling
Transmit National Bils. TN BITS IS the N-bIt Input for Nallonal-blt signaling
Transmit Link. TLiNK IS the senal data link Input The data rate IS 64 kbps.
Transmit Data Ones. TDAT1S high selects "all 1s" transmission In time slot 16
Transmit Link Mode. TLNKMD selects the source for time slot 16 signaling If low. TLiNK IS the Input
for time slot 16 signaling. If high, Tl-T8 (parallel Interface) or TSER (senal Interface) IS the Input for time
slot 16 Signaling
Transmit Extra Bits. TXBITS IS the X-bit Input for Extra-bit Signaling In time slot 16
Receive Time Slot 16. RTS16 IS high dunng time slot 16
Receive International Bits. RIBITS high indicates that the International bit (bit 1, time slot 0) IS present at RSER
Receive Multiframe Alignment. RMFA IS high dunng frame 0, which contains the multlframe alignment
Signal
Receive Link 1. RLlNKl high IndlcRtes the recepllon of 255 consecutive 1s In time slot 16
Receive Multiframe Red. RMRED high indicates 2 consecutive multlframe alignment errors or "all
time slot 16 bits low" for at least one multlframe. When RMRED IS high, a Multlframe Yellow Alarm IS
automatically transmitted as bit 6 = 1 In time slot 16, frame 0
-
Framing Error. FERR high indicates an error In the current framing bit at RSER
·
Frame or Multlframe Error. FMERR high In bit 1, time slot 0 indicates a frame error, high In bit 1, time
slot 16 indicates a multlframe error
· ·
·
·
·
·
·-
-
-
-
·
TMFA
-
TTS16
· ·
Receive National Bits. RNBITS high indicates that a Nallonal bit IS present at RSER (bits 4--8 of a
nonframe-ahgnment time slot 0)
Receive Data Link. RLiNK IS the senal data link output The data rate matches that of TLiNK (64 kbps).
Receive Multiframe Yellow. RMYEL IS the received Multlframe Yellow Alarm Signal, bit 6 of time slot
16, frame 0 RMYEL high indicates a Multiframe Yellow Alarm
Receive Link Clock. RLCLK IS a square wave whose nSlng edge occurs 2 bit times aiter the received
data on RLiNK
Receive Extra Bits. RXBITS high Indicates an Extra bit IS present at RSER (bits 5, 7 and 8 of time
slot 16, frame 0)
Transmit Link Clock. TLCLK IS a square wave whose rising edge occurs 4 bit times aiter the sampling
of TLiNK.
Transmit Multiframe Alignment. TMFA IS high dunng the data sampling of frame 0, which contains the
mult!irame alignment Signal.
Transmit Time Slot 16. TTS16 is high dUring the sampling of time slot 16.
6-85
•
T1/CEPT PCM Transceiver
R8070
CEPT WAVEFORMS
·r
MULTIFRAME M
MULTIFRAME - M +
1
FRAME NO. 1 0 1 1 1 2
1 3 1 4 1 5 1 6 1 7 1 8 1 9 110 111 112 113 114 115 1 0 1 1 I 2 1 3 1
TMAX
JI
~
14
n
rI
TMFA
Transmlt·Multlframe-Mode 256S
r
I 0 I 1I 2I 3 I 4I 5I
FRAME NO.
MULTIFRAME M
6
I7 I
8
I
9
I 10 I 11 112 I 13 I
t
14 115
I
MULTIFRAME - M +
1
0
RSYNC
jI
n
RMFA
II
n
I 1I
2
I 3I
Recelve·Multlframe-Mode 256S
I--MULTIFRAME
I
M
FRAME NO.
I
TMAX
n~
0
I
tI
0
I
1
______ ______
~n,~
I
~
Transmlt·Multlframe-Mode 256N
t-
I
I
MULTIFRAME
FRAME NO.
I
0
RSYNC
n~
I
M + 1
M
I~
MULTIFRAME-.I
______
~nl~
MULTIFRAME--I
M + 1
I
I
I
0
_________
Recelve·Multlframe-Mode 256N
6-86
T1/CEPT PCM Transceiver
R8070
CEPT WAVEFORMS (Cont'd)
FRAME N' OF
FRAME 0 OF
-----------MULTFRAME M - - - - - - - - - - + / 4 - - - - - M U L T I F R A M E M + 1 - - - -
I---11
2
3
TIME SLOT 30
4
5
6
------II~.---TIME SLOT 31 - - - - - - t - - - - T l M E SLOT 0 - - - - I
7
B
11
TCLK
1
I
I I I
I I I I I I
- -TRISTATE
-----<
EXCEPT OJ
Output Data Delay Time
Minimum Reset Time
REFRAME TIMING
Mode
Minimum
Average
Maximum
Unit
193N
197N
15
15
27
27
38
38
ms
ms
1935
1975
10
10
16
16
22
22
ms
ms
193E
193F
45
45
67
67
85
85
ms
ms
256N
256S
3
3
13
13
ms
ms
60
60
6-89
•
T1/CEPT PCM Transceiver
R8070
ABSOLUTE MAXIMUM RATINGS *
Symbol
Value
Unit
Supply Voltage
Parameter
Vee
+4.75 to 5.25
Vde
Operating Temperature
Commercial
Industrial
TA
o to +70
-40 to +85
°C
Storage Temperature
TSTG
-55 to + 150
°C
* NOTE: Stresses above those listed may cause permanent
damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above
those indicated in the other sections of this document is not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
OPERATING CONDITIONS
Symbol
Value
Unit
Supply Voltage
Parameter
Vee
+4.75 to 5 25
Vdc
Temperature Range
Commercial
Industrial
TA
°C
o to +70
-40 to +85
ELECTRICAL CHARACTERISTICS
Parameter
Min
Max
Unit
V,L
-03
0.8
V
Input High Voltage
V,H
20
Vee + 0.3
V
Output Low Voltage
VOL
-
04
V
Input Low Voltage
Symbol
Test Condition
ILOAD = +1.6 rnA
V
Output High Voltage
TTL
CMOS
VOH
Output Low Current
Output High Current
2.4
3.5
-
10L
+16
-
rnA
VOL = O.4V
10H
-100
-
~A
VOH = 3.5V
ILOAD = -100,,1\
ILOAD = -100~A
-
Input Capacitance
C'N
-
5
Output Capacitance
COUT
50
pF
Power Dissipation
PWD
-
100
mW
REFERENCE DATA
For detail information refer to the R8D7D T1/CEPT PCM
Transceiver Designer's Guide (Order Number 313).
6-90
pF
T1/CEPT PCM Transceiver
R8070
PACKAGE DIMENSIONS
64-PIN PLASTIC QUAD IN-LINE PACKAGE (QUIP)
J1JlJn~'~'~'~n~,u~,n,n,n,n,n
..
T
.1
MILLIMETERS
B
,0
DIM
A
B
C
D
El
E2
G
J
Kl
K2
~~~~~
wtJ-ji-~;~i\J;
~
INCHES
MIN
MAX
MIN
41 10
4161
17 23
458
056
1618
1702
356
048
1905 sse
2350 ase
127 sse
018
033
292
318
483
534
MAX
1638
0690
0180
0022
0670
0140
0018
0750
0925
0050
0007
0115
sse
sse
sse
0013
0125
0210
D 190
IT
64-PIN CERPAC QUAD IN-LINE PACKAGE (QUIP)
DIM
A
B
'~n~n ~n~ n~'~n~' ~ Jn~ JJJn~n~n~
64
P
01
0
C
D
E1
E2
G
J
K1
ti
33
Q
K2
MILLIMETERS
MIN
MAX
4128
4077
1727
1676
458
356
048
056
19 05 ase
2350 Bse
127 sse
030
020
292
318
534
483
INCHES
MIN
1605
0660
MAX
1625
0680
0140
0180
0018
0022
0750 sse
0925 SSC
0050
0008
0115
D 190
ase
0012
0125
0210
i
B
I
32~
'~T~"~" ~T~ Tn"U" ~:~~~
-~~D
G~ 1-
r------- A
t
~
~
c
t
6-91
~~~
K1 K2
-11-J
Tf
•
T1/CEPT PCM Transceiver
R8070
PACKAGE DIMENSIONS (Confd)
68-PIN PLASTIC LEADED CHIP CARRIER (PLCC)
V SEATING
I
TOP VIEW
PLANE
CHAM.J x 45°
SIDE VIEW
17 PINS
CHAM.
h x 45° PER SIDE
3 PLCS EQUALLY
SPACES
EJECTOR PIN MARKS
4 PLCS BOTTOM OF
PACKAGE ONLY
(TYPICAL)
BOTTOM VIEW
R
DIM
A
A1
A2
SECTION A-A
TYP FOR BOTH AXIS (EXCEPT FOR BEVELED EDGE)
b
0
01
02
03
2502
24 00
2019
2324
2527
2426
2045
2350
sse
e
1 27
h
J
025 TYP
"
45 0 TYP
089 TYP
025 TYP
R
R1
6-92
MILLIMETERS
MIN
MAX
414
439
137
147
231
246
0457 TYP
115 TYP
INCHES
MAX
0173
MIN
0163
0054
0091
0058
0097
0181YP
985
995
945
955
795
805
915
925
050 BSC
010 TYP
045 TYP
45 c TYP
035 TYP
010 TYP
R8070A
'1'
R8070A
T1/CEPT PCM Transceiver
Rockwell
INTRODUCTION
FUNCTIONAL DESCRIPTION
This data sheet addendum describes the enhanced framing procedure implemented in the R8070A version of the
R8070 T-1/PCM-30 Transceiver device. This enhancement is only applicable to the 193E and 193F modes associated with the North American Extended Superframe
(ESF) standard.
The R8070A is functionally and electrically identical to the
R8070 except for the frame synchronization procedure
when the device is configured in an Extended Superframe
mode (193E or 193F). An extended CRC-6 check interval
on the order of 8 - 12 multiframes has been added to the
master state sequence. This extended period starts at the
beginning of the "SYNC" state.
The improvements incorporated in the R8070A are
transparent to the user. as well as interfacing hardware
and software. All designs using the R8070 can use the
R8070A to improve reliability.
The extended CRC-6 check interval causes the R8070A
to reframe if two consecutive CRC-6 block errors are
detected.
These enhancements ensure extremely robust framing
operation against false framing on data patterns that constantly mimic the ESF frame pattern.
II
LINE
INTERFACE
UNIT
(UU)
T1/CEPT
PHYSICAL
INTERFACE
R8070A
T1/CEPT
PCM
TRANSCEIVER
MICROPROCESSOR-BASED OR
NON-MICROPROCESSOR-BASED
EQUIPMENT
PARALLEL
OR
SERIAL
INTERFACE
T1/CEPT
SERIAL
INTERFACE
R8070A Functional Interface
Document No. 29300N14A
Data Sheet Addendum
6-93
Order No. 314A
March 1988
R8071
'1'
R8071
ISDN/DMI Link Layer Controller
Rockwell
APPLICATIONS
ISDN
DMI
• PRIMARY RATE INTERFACES
• BASIC RATE D-CHANNEL CONTROLLER
• HOST INTERFACE
• PBX TRUNKSIDE ADAPTERS
INTRODUCTION
FEATURES
The Rockwell R8071 ISDN/DMI Link Layer Controller device multiplexes/demultiplexes up to 32 high speed data channels to support implementation of the Digital Multiplexed interface (DMI)
between a digital PBX and a host computer (Figure 1). The
R8071 operates at layer 2 (data link protocol level) of the Open
Systems Interconnection (OSI) reference model recommended
by the International Organization for Standardization (ISO) and
resides between the R8070 Tl/CEPT PCM Transceiver and a
buffer memory shared with one or more host processors.
•
- T1/CEPT provides the link beyond the central office or PBX
- ISDN provides the phonelterminal to the central office or
PBX basic access link
- DMI provides the computer to computer, and computer
to PBX, link
•
The R8071 processes transmit and receive data on a Tl communications medium with DSI signaling at 1.544 Mbps in the
D4 framing format or the Fe extended framing format, or at
2.048 Mbps in the CEPT PCM 30 carrier format. The device provides HDLC formatting functions for synchronous data and
manages buffer memory for each of the active data channels,
including the common signaling Channel, using simple linkedlist structures.
R8071 single chip CMOS monolithic device simplifies
ISDN/DMI implementation
• Provides up to 32 full duplex channels with HDLC/SDLC protocol formatting
• Supports all four DMI B channel data options:
- Mode 0 (clear channel 64 kbps synchronous)
- Mode 1 (56 kbps synchronous data without or with HDLC
protocol)
- Mode 2 (up to 19.2 kbps synchronous or asynchronous)
- Mode 3 (64 kbps virtual circUit service)
The R8071 is compatible with the Integrated Services Digital
Network (ISDN) speCified by the International Telegraph and
Telephone Consultative Committee (CCITT) and supports connections of computers to the ISDN at the primary rate. It also
supports modes 0, 1,2 and 3 of the DMI protocol for clear channel transmission of data at 64 kbps, 56 kbps synchronous,
standard data rates up to 19.2 kbps, and 64 kbps virtual circuit
protocol using LAPD, respectively.
• Supports both DMI D channel signaling options
-
Bit-oriented signaling (BOS)
Message-oriented signaling (MOS)
• Compatible with 1.544 Mbps T1 D4 and extended framing
format as well as 2.048 Mbps CEPT PCM 30 carrier format
• Supports both flag stuffing (1.462, DMI mode 2) and RA2
intermediate rate adaption (1.460, X.30, V.110 or ECMA-102)
The R8071 device provides additional functions which support
X.30 and X.31 rate adaption as well as ISDN hyperchannels.
The device is also compatible with HDLC, SNA SDLC, X.25,
X.75, LAPB and LAPD protocols. These features allow the use
of the R8071 in applications that go beyond the host-end DMI
interface.
•
Provides ISDN standard hyperchannel options (CCITT 1.412):
-
In T1: HO (384 kbps)
H11 (1.536 Mbps)
-
In CEPT PCM 30: H12 (1.920 Mbps)
• Compatible with HDLC, SNA SDLC, X.25, X.75, LAPB and
LAPD protocols
The R8071 complements the Rockwell R8070 T1/CEPT PCM
Transceiver, which operates at layer 1 (physical interface level)
of the OSI reference model, and provides basIc T1 framing and
maintenance functions of the DMI link.
• On-board buffer memory management function
• On-board CRC-16 generation and checking, automatic flag
detection and transmission, and zero-bit insertion and
deletion
The R8071 finds applications in widely diverse areas of telecommunications (including TDM machines, Central Office
switches, and PBX), as well as the basic host computer-PBX
DMI links. In ISDN switching applications, the R8071 can
function as a multiplexed controller for as many as 32 ISDN basic
access "D" channels, and can substantially off-load LAPD processing from the SWitch Central Control.
Document No. 29300N18
DMI implementation, SOlidly based on Tl and CEPT primary
rate carrier with designed-in compatibility with ISDN, is the
key to world-wide networking
• Simple interface to Rockwell R8070 T1/CEPT PCM
Transceiver
• Available in 64-pin quad In-line (QUIP) and 68-pln plastic
leaded chip carrier (PLCC) packages
• Operates from a single + 5 Vdc supply
Data Sheet
6-94
Order No. 318
Rev. 2, December 1988
R8071
ISDN/OM I Link Layer Controller
ORDERING INFORMATION
INTERFACE
The R8071 ISDN/OM I Link Layer Controller transmits data to, and
receives data from, an R8070 T1/CEPT PMC Transceiver (or com·
patible framer device) in ISDN/OM I rate and formats as illustrated
in Figure 1. It transfers the data in 8·bit parallel form to and from
an external buffer memory shared by a host computer system.
(The external buffer memory IS referred to as shared memory
and the host computer system is referred to as the host.) The
R8071 interface signals are functionally grouped in Figure 2. The
R8071 pin assignments are shown in Figure 3 and the R8071
interface signals are defined in Table 1.
Part Number:
R8071
iL
LTemperature
Blank
=
O°C to + 70°C
Package
P = 64·PIn Plasllc QUIP
S = 64-Pln Cerpac QUIP
J = 68·Pin Plastic Leaded Chip
Carner (PLCC)
JC = 68·PIn Ceramic Leaded
Chip Carner (CLCC)
G = 68·PIn Pin Gnd Array (PGA)
II
EXTERNAL
SHARED
MEMORY
L.._ _ _. . TO/FROM HIGHER LAYERS
Figure 1.
Functional Architecture for Host ISON/OMI Primary Rate Access, PBX ISON/OMI Trunkside Adapter
6-95
ISDN/OM I Link Layer Controller
R8071
GND
SYSCLK
TCLK
LINE
INTERFACE
UNIT (LIU)
SERIAL
INTERFACE
~
RCLK
AO-A1S
TSER
TMAX
DMND
RSER
TO
<
J-..
8
16
>
~-
RRED
WRITE
READ
RESET
ATACK
HOST
PROCESSOR
SHARED
AS
RSYNC
R8070
00-07
MEMORY
ATTN
2
)
HCS1-HCSO
-
STRAP
INPUTS
SYSACC
~-
INTR
"-
TlICEPT
TSEREN
SIS
CHO-CH4
RX/TX
MDFS
UAEN
VCC
Figure 2.
R8071 Interface Signals
6-96
5
--
}~""'
OUTPUT
SIGNAL
ISDN/OM I Link Layer Controller
R8071
NC
TMAX
SIS
RESET
Tl/CEPT
HCSO
HCSl
CHO
CHl
CH2
CH3
CH4
RX/TX
TCLK
SYSCLK
TSER
Vee
GNO
DO
01
02
03
04
05
06
07
AO
A1
A2
A3
A4
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
AS
TSEREN
RCLK
RSYNC
RRED
RSER
NC
GNO
GNO
NC
INTR
AS
ATTN
SYSACC
GNO
GNO
Vee
WRITE
READ
ATACK
OMNO
MOFS
UAEN
A15
A14
A13
A12
All
Al0
A9
A8
A7
A6
I~
,...o~tu
><
z~~~ca:
cc
00000000 ~
~~>~~
o~oo~~~~oooooo~ooozz
zo~~~~oo~z~~~~~z~~
CHl
CH2
CH3
CH4
RX/TX
TCLK
SYSCLK
TSER
Vee
GNO
GND
DO
01
D2
03
04
05
0
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
PIN 1
NC
INTR
AS
ATTN
SYSACC
GNO
GND
GNO
Vee
WRITE
READ
ATACK
OMNO
MOFS
UAEN
A15
A14
~=mO""NM~~~~mmO""NM
NNNMMMMMMMMMM~~~~
~~~<~~~~~~~~~~~~~
64-Pin QUIP
68-Pin PLCC
Back View of Pin Grid Array
11
10
@ @ @ @ @ @ @ @ @
@ @ @ @ @ @ @ @ @ @ @
9
@ @
8
@ @
@ @
@ @
7
@@
@@
6
@ @
@@
5
@@
@@
4
@ @
@@
3
@@
~@ @
2
@@@@@@@@
~@ @
@@@@@@@ @@
LKJHGF EOCBA\
INDEX
MARK~
PIN
SIGNAL
PIN
SIGNAL
PIN
SIGNAL
PIN
SIGNAL
A2
A3
A4
AS
A6
A7
A8
A9
Al0
Bl
B2
B3
B4
B5
B6
B7
B8
NC
INTR
ATTN
BMRT
GNO
Vee
READ
DMNO
UAEN
GNO
GNO
AS
SYSACC
GNO
Vee
WRITE
ATACK
B9
Bl0
Bl1
Cl
C2
Cl0
Cl1
01
02
010
011
El
E2
El0
Ell
Fl
F2
MOFS
A15
A14
RSER
NC
A12
A13
RSYNC
RREO
Al0
All
TSEREN
RCLK
A8
A9
TMAX
NC
FlO
Fl1
Gl
G2
Gl0
Gl1
Hl
H2
Hl0
Hl1
Jl
J2
Jl0
Jll
Kl
K2
K3
A6
A7
RESET
SIS
A4
A5
HCSO
T1/CEPT
A2
K4
K5
K6
K7
K8
K9
Kl0
Kll
L2
L3
L4
TCLK
TSER
Vee
GNO
01
03
06
07
CH3
RX/TX
SYSCLK
Vee
GNO
DO
02
04
05
A3
CHO
HCSl
AO
Al
CHl
CH2
CH4
L5
L6
L7
L8
L9
Ll0
(ON TOP SIDE)
68-Pin PGA
NC = NO CONNECTION TO BE MADE TO THIS PIN.
Figure 3.
R8071 Pin Assignments
6-97
•
R8071
ISDN/OM I Link Layer Controller
Table 1.
Symbol
R8071 Interface Signal Definitions
Signal NamelDescription
I/O
Memory Interface
00-07
1/0
Memory Data Lines. Bidirectional 8-btl memory data bus between the R8071 and the shared
memory 00 IS the LSB and 07 IS the MSB
AO-A15
0
Memory Address Lines. Output lines to the shared memory AD IS the LSB and A15 IS the MSB
OMNO
0
Memory Demand. Active high output to shared memory The R8071 accesses shared memory
Within one TCLK penod after assertion (nsmg edge) of OMNO DMNO IS negated at completion
of the memory access cycle
AS
0
Memory Address Strobe. A valid memory address IS present on the memory address lines at
the falling edge of the active low AS
WRITE
0
Memory Write. Active low output to the shared memory to perform a wnte cycle
READ
0
Memory Read. Active low output to the shared memory to perform a read cycle Data from
memory IS latched In the R8071 pnor to the negation of READ
ATTN
I
Attention. Active high Input that commands attention from the R8071 to shared memory locations which contain updates to status, modes, and/or buffer start address of a specified channel
A sequence of memory accesses are performed soon after ATTN IS asserted ATTN IS negated
m response to ATACK
ATACK
0
Attention Acknowledge. Active high output asserted when the sequence of memory accesses
(in response to ATTN) IS complete ATACK IS negated In response to negation of ATTN
SYSACC
0
System Access. Active high output asserted to Indicate the R8071 IS accessmg one of the 129
system memory locations (Channel Activation Byte or Channel Buffer POinters)
LlU Interface
SYSCLK
I
System Clock. Square wave Input from the LlU clock generator for Internal use In the R8071
Nommally, 3088 MHz for T1 and 4096 MHz for CEPT PCM 30
TCLK
I
Transmit Clock, Square wave Input from the LlU clock generator proViding the master timing
source for the transmit function The frequency IS one-half that of the SYSCLK
RCLK
I
Received Clock. Input from the external LlU/Clock recovery for the R8071 to sample RSER, the
received senal data Nominally, 1 544 MHz for T1 and 2048 MHz for CEPT PCM 30
TSER
0
Transmitter Serial Data. Output from the R80l1 to the Ra070 T1iCEPT PCM Transceiver
representing the transmit senal data bit stream
TMAX
I
Transmit Multiframe Sync, Active high Input pulse from the R8070 T1/CEPT PCM Transceiver
Serial Interface
Indicating the begmnlng of a multlframe
RSER
I
Received Serial Data. Input from the R8070 T1/CEPT PCM Transceiver representmg the
received senal data bit stream
RSYNC
I
Receive Synchronization. Active high Input level or pulse from the R8GlO T1/CEPT PCM Transceiver for frame synchronlzatlon reference
RRED
I
Receive Red Alarm, Active high Input from the R80l0 T1/CEPT PCM Transceiver mdlcatlng a
failure to frame on the T1 or CEPT PCM 30 time-divIsion multiplexed (TOM) signals Low
mdlcates that frame alignment has been found
6-98
ISDN/DMI Link Layer Controller
R8071
Table 1.
R8071 Interface Signal Definitions (Continued)
110
Signal Name/Description
Tl/CEPT
I
T1 or CEPT Framing Select. High selects the Tl framing mode Low selects the CEPT PCM 30
framing mode
HCS1, HCSO
I
Hyperchannel Select. Encoded Inputs select the Tl/CEPT PCM 30 hyperchannels (See
Figure 5.)
Symbol
Strap Option Inputs
T1/CEPT
HCSl
HCSO
X
Low
Low
High
High
Low
Four channels of 384 Kbps (HO)'
High
Low
High
Single channel of 1.536 Mbps (Hll)l
Low
High
Low
X
High
High
Single channel of 1 92 Mbps (H12)2,
time slots 0 and 16 are 64 kbps
Reserved
Low
Low
High
Reserved
Channel Selection
All channels are 64 Kbps
Notes: "X" denotes "Don't Care"
1. Valid for Tl only.
2. Valid for CEPT only
TSEREN
I
TSER Enable. Active high Input that works In conjunction with the FILUMASK bit as follows:
FILL/MASK Bit
O·
1
High
Send a 1 on TSER
Send data on TSER
Low
High impedance
output on TSER
Send data on TSER
TSEREN
• or any F bit, or any bit dUring RESET, R8071 Inillalizatlon, and until a channel IS
activated.
SIS
I
Serial Interface Select. High level Identifies an R8070 compatible serial interface. Low level
Identifies AT&T compatible Interface.
MOFS
I
Memory Data Format Select. High indicates that the most and least Significant bytes of next
buffer start address, buffer size and data length In shared memory reSide at even and odd
addresses, respectively (68000 MPU word addreSSing compatible). Low indicates that the least
and most Significant bytes of next buffer start address, buffer size and data length reSide at
even and odd addresses, respectively (8086 MPU word addressing compatible).
UAEN
I
Upper Address Enable. High level Input causes the upper address bus lines (AS-A15) to be In
the high Impedance state dUring system shared memory access (when SYACC IS asserted). Low
input causes the upper address outputs to be forced low by the R8071 when SYACC IS asserted
INTR
0
Interrupt. Active low output pulse of one SYSCLK period to the host system to indicate that the
buffer status IS being updated.
CHO-CH4
0
Channel Number (0-4). Encoded output indicating the channel number being served. CHO IS
LSB and CH4 IS MSB.
RXITX
0
ReceiveJTransmit Channel. Output used In conjunction With the channel number (CHO-CH4).
High indicates a receive channel and low indicates a transmit channel.
I
Reset. Active high Input that initializes all R8071 functions. Reset causes the R8071 to default to
HOLC mode, causes all Os In the FILUMASK, and deactivates all channels Inactive transmit
channels output all ls. R8071 initialization IS complete Within 90 SYSCLK periods after RESET
returns low.
Status Outputs
Reset and Power
RESET
VCC
Power Supply Voltage. +5 Vdc With respect to VSS
VSS
Ground. Ground reference voltage
6-99
II
ISON/OMI Link Layer Controller
R8071
FUNCTIONAL DESCRIPTION
A number (specified In the shared memory) of HOLC flags are
appended to the end of an HOLC frame as time fill sequences.
The R8071 mOnitors the number of intentionally Inserted zeroes
(which may be viewed as non-data Intra-frame time fill bits). The
programmed number of flags are adjusted based on the number of zeroes Inserted. Reset activates the HOLC mode for all
channels.
The R8071 fetches the data to be transmitted from the shared
memory, processes the data for up to 32 channels, channel-bychannel, by performing protocol formatting and rate adaptlon,
and transmits It to the transceiver In serial form. Similarly, the
R8071 processes, on a channel-by-channel basIs, the received
serial data on up to 32 channels by performing protocol deformalting and rate adapllOn, and stores the data Into the shared
memory.
Logical Inversion
Logical Inversion of data, as well as abort, flag and FCS bitS,
before transmission is programmable. Reset activates Inversion
for all channels
Each channel IS processed depending on the operallOnal mode
specified by the host as set up In the shared memory For any
channel, the transmitter and the receiver operating modes may
be specified independently of each other.
Loop Mode
The internal functions of the R8071 are partitioned logically In
to five major blocks (Figure 4):
Loop mode for both the transmit and receive channels IS also
programmable In shared memory. For a channel In the near-end
loop mode, the R8071 stores the data transmitted during the
channel period In an Intermediate buffer. Such data is to be taken
by the receive data channel programmed In the loop mode and
eventually sent back to the shared memory. Only a single transmit channel and a single receive channel may be placed In the
loop mode at one time for proper operation. Note that loop mode
does not support HO hyperchannel operation Reset deactivates
the loop mode for all channels.
• Transmit Bit-Level Processor
• Receive Bit-Level Processor
•
Buffer Memory Manager
•
Oevlce Mode Controller
•
System MOnitor
TRANSMIT BIT-LEVEL PROCESSOR
Signaling
HOLC and Non-HOLC Modes
Bit-Oriented signaling and LAPO-based message-oriented signaling channels are directed to the non-HOLC processing
elements, without any speCial consideration.
The Transmit Bit-Level Processor performs basIc HOLC* protocol
formatting (OM I data modes 2 and 3, ISON LAPO and IBM SNA)
or other non-protocol transmit functions (OMI data modes 0 and
1, and bit-oriented signaling mode) for each channel independently of any another channel
ISDN Hyperchannels
The 64 kbps channels (or time slots) are grouped Into the ISON
standard hyperchannels (Figure 6). The actual hyperchannel
grouping IS specified by the HCS1 and HCSO Inputs (see Table 1,
Strap Input OpllOns). Reset deactivates signaling mode for all
channels
In the HOLe mode, It generates flags, abort and Idle codes,
Inserts zeroes for bit transparency, computes the HOLC frame
check sequence (FCS) and composes HOLC frames from the
data provided In the shared memory.
Transmit Interface
In the non-HOLC data mode, the data from the shared memory
IS not framed
The Transmit Bit-Level Processor Interfaces directly to an R8070
T1/CEPT PCM Transceiver without any external cirCUitry. All the
channel counter functions are bUilt-in The Transmit Serial Oata
(TSER) output IS driven with the transmit serial data bit stream
acqUired from the shared memory The Transmit Clock (TCLK)
Input IS the timing reference for TSER The Transmit Multlframe
Sync (TMAX) Input IS the starting reference for the TOM frame.
In either mode, the R8071 performs rate adaptlon of sub-64 kbps
data rates of the form
n x 8 kbps (n = 1 through 8)
to the standard 64 kbps bearer rate (1.460, second stage RA2).
An 8-blt FILL/MASK sequence (speCified In In shared memory)
IS applied to the HOLC-formatted or non-HOLC data on a blt-bybit baSIS (see FILL/MASK deSCription on page 26). The resultIng 8-blt sequence, consisting of the actual data bits and any
'time fill' bits (always a one) based on the FILL/MASK sequence,
IS then transmitted over the channel Figure Sa Illustrates thiS
process.
TSER IS placed In the high Impedance (trl-state) mode whenever
the TSEREN Input IS low and the FILL/MASK bit IS zero (see
Table 1, Strap Input OpllOns) ThiS enables the TSER outputs
of up to eight R8071s to be connected together and allows the
R8071s to be programmed with mutually exclusive FILL/MASK
sequences In order to accomplish subrate time-diVISion multiplexing over a 64 kbps channel
In the HOLC mode, the R8071 adapts the standard sub-64 kbps
data rates (CCITT X 1 or OMI mode 2, but not necessarily
n x 8 kbps) directly to the 64 kbps bearer rate (1.462 and OMI).
In summary, each channel may be programmed by the host system Independently of any other channel by speCifYing HOLC
mode, FILL/MASK, data inVerSiOn, and loop mode options. Both
the rate adaptlon recommendation, namely HOLC flag insertion
and the second stage intermediate rate adaptlon, are
implemented. In addition, various other HOLC formatted rates
of the form n x 8 kbps (n = 1 through 8) are also adapted to the
64 kbps bearer rate.
*The R8071 does not distingUish between the the High Level
Oata Link Control (HOLC) and the Synchronous Oata Link
Control (SOLC) protocols but Implements the common link-layer
functions for both Reference to HOLC In thiS document also
Implies SOLC unless otherWise stated.
6-100
ISDN/OM I Link Layer Controller
R8071
r---------------,
RSER
RCLK
RRED
RSYNC
,I
,I
I
AD
I
,I
I
A2
I
RECEIVE
BIT·LEVEL
PROCESSOR
I
I
I
I
J
I
I
I
I
Vee
RESET
SYSCLK
SIS
Tl/CEPT
HCSO
HCSl
I
I
I
I
I
I
I
I
I
-,
DEVICE
MODE
CONTROLLER
BUFFER
MEMORY
MANAGER
I
I
Vss
TSER
TSEREN
TCLK
TMAX
ATTN
UAEN
MDFS
II
I
I
I
I
-,
I
I
I
I
I
____-.:~:--_tI____________
SY_S_T_EM
__
M_ON_I_ro_R__________
R8071 ISON/OMI Link Layer Controller Functional Block Diagram
6·101
A13
A14
01
03
MEMORY
DATA
05
06
07
OM NO
READ
WRITE
AS
INTR
RX/TX
~ }~
CHO
CHl
CH3
CH4
~~~:----~:~::::~C
L ______________ -1
Figure 4.
All
A12
04
I
TRANSMIT
BIT·LEVEL
PROCESSOR
Al0
I
I
MEMORY
ADDRESS
A9
02
I
J
A8
'-
I
..,
'"'
A7
DO
I
~I
A5
A6
1
I
I
A4
A15
,
I
A3
I
I
J
Al
...a
•
ISDN/DMI Link Layer Controller
R8071
MSB
LSB
i
i
C D E F G
IJ
HI
DATA BYTES
K L M N 0 P 01
FILL/MASK PATTERN
O=A FILL BIT OF "1" OR HIGH Z (SEE TSEREN)
11
FILL/MASK
0 1 1 1 0 0 01
{
1 = INSERT BIT OF DATA BYTE
STARTING WITH LSB
..
T1 OR CEPT PCM 30 SERIAL OUTPUT
, FRAMEn
,,
FRAMEn+1
FRAMEn+2
1111HGF1E
1 1 1 D C B 1 A
1110PO
•••
f
LSB
a. Single Transmit Channel
T1 OR CEPT PCM 30 SERIAL INPUT
~
,,
,
FRAMEn
,,,
E 1 F G H 1 1 1
I
FRAME n+1
IA 1 BCD 1 1
11
o
1 1 1 0 0 01
fA B C D E F G HI
•
+
MSB
RECEIVED DATA
FILUMASK
ASSEMBLED DATA BYTE
LSB
b. Single Receive Channel
Figure 5.
32 kbps Subrate Operation
6-102
ISON/OMI Link Layer Controller
Ra071
CEPT PCM 30 MODES
TSO
CH 00000
TS 31
CH 11111
TS 16
+ - - - - - C H 10000
1920 kbps
F 1
TS 1
CH 00001
T1 MODES
64 kbps
CH 00001-'-4
1536 kbps
NOTE: GROUPING OF 64 KBPS CHANNELS INTO HYPER CHANNELS IS FIXED AS SHOWN. CHANNEL ASSIGNMENTS
CANNOT BE CHANGED.
Figure 6. R8071 Hyperchannel Provisions
•
6-103
R8071
ISON/OMI Link Layer Controller
RECEIVE BIT-LEVEL PROCESSOR
Processor and the Transmit Bit-Level Processor eXChange data
With the shared memory over a single data bus. In order to handle
contention for the data bus, an elastiC buffer is used In the
Receive Bit-Level Processor.
HOLC and Non-HOLC Modes
The Receive Bit-Level Processor performs basIc HOLC/SOLC
protocol deformattmg (OM I data modes 2 and 3, IS ON LAPO,
and IBM SNA) or other non-protocol receive functions (OM I data
modes 0 and 1, and bit-oriented signaling channels) for each
channel Independently of .my other channel.
The elastic buffer input is clocked by the Receive Data Clock
(RCLK) and the output isre-timed uSing the Transmit Data Clock
(TCLK). Thus the TCLK IS used as a reference for both the transmit and the re-timed receive data. As a result, the shared memory
access is sirpple and predictable. Note that the looped data
bypasses the elastiC buffer. Also, any overflow or underflow of
the elastic buffer IS reported to the shared memory for all the
channels. The elastic buffer also protects the shared memory
against underflow or overflow in the remote loopback (I.e., echo)
mode.
In the HOLC mode, the R8071 detects flags, aborts and Inserted
zeroes, and also Checks the Frame Check Sequence (FCS), It
also filters out any time fill patterns received by applying the 8-bit
FILL/MASK sequence specified In the shared memory, The
resulting senal data, Including the HOLC header (loS" address
and control fields), is then assembled into bytes for storage in
the shared memory (Figure 5b), The validity of every HOLC frame
IS checked and reported to the shared memory appropriately,
Reset activates HOLC mode for all channels,
Receive Interface
In the non-HOLC data mode, any time fill patterns received are
also filtered out based on the 8-bit FILL/MASK sequence, The
resulting senal data IS simply grouped into bytes for transfer to
the shared memory,
. .
The Receive Bit-Level Processor interfaces directly to the R8070
Without any need for additional logic. All the needed channel
counters are supplied internally. ReCeived senal data is extracted
from the Received Serial Data (RSER) Input bit stream on the
falling edge of the Receive Clock (RCLK) input. (R8070 mode,
see SIS input.)
Logical Inversion
Logical inverSion of all the received serial data is programmable in the external shared memory, Reset activates inversion for
all channels,
The Receive Synchronlzallon (RSYNC) input provides a frame
synchronization reference, The RRED Input is monitored for loss
of T1 or CEPT PCM 30 frame synchronization and reported to
the shared memory.
Loop Mode
Loop mode for receive channels is also programmable in shared
memory, For a channel in the near-end loop mode, the input data
is taken from an internal buffer rather than from the external data.
The internal buffer presumably has been filled with data from
a transmit channel In the loop mode, Thereafter, the looped data
is processed according to the specified mode of operation, Reset
deactivates loop mode for all channels,
BUFFER MEMORY MANAGER
The Buffer Memory Manager controls the flow of data between
the Transmit Bit-Level Processor/Receive Bit-Level Processor and
the data buffers in external shared memory. Shared memory is
allocated for each transmit or receive channel as a linked list
of buffers which are set up by the host. The shared memory is
managed with minimal intervention from the host. The host
simply has to allocate enough memory in the buffers such that
the real-time operation of transmission and reception can take
place without any data underrun or overrun, respectively.
Non-HOLC Signaling Mode
In the non-HOLC signaling channel mode, the R8071 detects the
multiframe (or extended superframe) alignment sequence for
DMI bit-oriented signaling (G]32 and DMI).II a valid multiframe
alignment is found, the received data is transferred to shared
memory. If the multiframe alignment sequence is found to be
in error, transfer of signaling data to the shared memory IS suspended until a valid multiframe is detected (G,732 and DMI). Loss
of multiframe is reported to the shared memory. Note that any
channel(s) can be specified to receive bit-oriented signaling. This
feature is very useful in central office switching applications.
Reset deactivates signaling for all channels.
The buffers contain information such as operational modes,
buffer or HDLC frame completion status, size of the buffer, number of transmit or receive data bytes, link to the next buffer, and
the transmit or receive data bytes,
The R807i updates the status of each channel butfer as each
individual buffer or HOLe frames are completed and simUltaneously asserts the Interrupt Indication (INTR) output to the
host.
ISDN Hyperchannels
The 84 kbps channels are grouped into the ISDN standard hyperchannels (Figure 6) based on the input strap pinS HCSO and
HCS1 (see Table 1, Strap Input Options).
During transmission, the Empty (MPTY), Command (CMND), and
Complete Frame/Partial Data Buffer (CFip'j bits are monitored
in the transmit status by1e (see External Shared Memory Organl·
zation and Definition). The MPTY, Invalid Buffer Address (IVBA),
and Underrun (UNDR) bits In the transmit status byte in shared
memory are updated.
Elastic Buffer
The received serial data from a T1 or CEPT PCM 30 multiframe,
in general, has no relationship to the transmit data multiframe
in terms of frame beginning, Both the Receive Bit-Level
6-104
ISON/OMI Link Layer Controller
R8071
can drive the AS-AI5 lines to any logic level. As soon as the RB071
completes the ATTN command processing, the Attention
Acknowledgement (ATACK) output is asserted. The falling edge
of ATTN causes ATACK to return low.
During reception, the Empty (MPTY), Command,(CMND), and
Complete Frame/Partial Data Buffer (CFiP) bits are monitored
in the receive status byte. The MPTY, Invalid Buffer Address
(IVSA), and CFip bits in the receive status byte in shared memory
are updated. Three encoded error reporting bits in the receive
status byte, Abort (ABRT), Frame Check Error (FCER) and Short
HDLC Frame Error (SHER), are also updated to report conditions such as invalid HDLC frame, frame check error, abort code
received, loss of T1 or CEPT PCM 30 frame synchronization, loss
of T1 or CEPT PCM 30 signaling channel multiframe alignment,
and elastic buffer underrun or overrun.
In addition, the relative locations of the upper (most significant)
and the lower (least significant) bytes of certain 16-bit words (i.e.,
next buffer address, buffer size and data length) In the shared
memory are determined based on the Memory Data Format
Select (MDFS) input (see Table I, Strap Input Options).
SERIAL INTERFACE TO R8070 T1/CEPT
PCM TRANSCEIVER (SIS = HIGH)
Operational modes, loop, and invert commands as well as the
FILUMASK patterns are extracted from the transmit and receive
command buffers and passed to the Transmit Bit-Level Processor and the Receive Bit-Level Processor, respectively. The modes
are decoded from the HDLC Mode Select (HDLC) and Signaling Mode Select (SIG) bits. Loop and invert commands are pulled
from the LOOP and INV bits, respectively.
TRANSMIT
T1 Mode (T1/CEPT input high). The serial data output (TSER)
from the RB071 changes in response to the falling edge of the
TCLK as shown in Figure 7. Setup and hold time periods for TSER
are such that TSER can be sampled reliably at the next rising
edge of the TCLK inside the RB070 T1/CEPT PCM Transceiver
device. TSER is a tri-state output. Its actual logic level and
impedance level over any bit period are determined by the combination of the corresponding FILUMASK bit and the TSEREN
input.
The Buffer Memory Manager responds to host processor-initiated
changes in the operational modes of a channel or relocation of
the allocated buffers without affecting the operation of the other
channels.
The Channel Number (CHO-CH4) and ReceivelTransmit Channel (RXlTX) outputs are updated to reflect to the channel being
served.
Transmit synchronous operation between the RB070 and the
RB071 is attained by TMAX application.
The Buffer Memory Manager also causes mode changes in the
Transmit Bit-Level Processor and the Receive Bit-Level Processor in response to the host processor-initiated mode changes.
When TMAX is synchronously asserted, the RB071 will be transmitting the last bit of a frame. TMAX may be applied
synchronously as frequently as a frame rate, or as seldom as
when a system needs to reinitiate synchronism.
DeVICE MODE CONTROLLER
When TMAX IS applied to initiate synchronism, the transmitter
completes the processing of the current channel, fills the interim
time with 1s (or goes high impedance - see TSEREN) and
begins transmitting the first bit of time slot 1 which will occur
nine or ten (CEPTIT1) bit times after TMAX.
The Device Mode Controller provides the central device timing
and control for the other device functions. General and memory
interface internal timing is derived from the System Clock
(SYSCLK) input. Device reset to the other functions is distributed
based on the Reset (RESET) input.
CEPT PCM 30 Mode (T1/CEPT input low). TSER from the RB071
changes in response to the falling edge of the TCLK as shown
in Figure B. Setup and hold time periods for TSER are such that
TSER can be sampled reliably at the next rising edge of the TCLK
by the RB07O. TSER IS a tri-state output. Its actual logic level and
impedance level over any bit period are determined by the combination of the corresponding FILUMASK bit and the TSEREN
input.
The selected carrier and framing format based on the T1/CEPT
PCM 30 Carrier Select (T1/CEPT) input and the encoded Hyperchannel Select inputs (HCSO and HCS1), are passed to the Transmit Bit-Level Processor and the Receive Bit-Level Processor. The
transceiver interface specified by the Serial Interface Select (SIS)
input is also routed to those functions. (See Table 1, Strap Input
Options.)
SYSTEM MONITOR
RECEIVE
The System Monitor informs the Buffer Memory Manager of a
host-initiated Attention (ATTN) command. Prior to asserting ATTN,
the host will have set up, in shared memory. the actual channel
number that needs the RB071's attention, its mode of operation
and the start address of the linked list of buffers.
T1 Mode (T1/CEPT input high). The receive data (RSER) is
processed serially and sampled at the negative edge of RCLK
at a rate of 1.544 MHz. The RB070 accomplishes multiframe
synchronization at the third assertion of RSYNC after RRED
(internally delayed) goes low. RSYNC is synchronous with the
rising edge of RCLK and the first "F" bit of a multlframe. Figure 9
illustrates the timing.
Whenever the RB071 accesses the Channel Activation Byte or
Channel Buffer Pointers in shared memory, the System Access
(SYSACC) output is asserted indicating that system memory is
being accessed. At that time, the upper order address lines
(A8-A15) are placed in the high impedance state or driven low
depending on whether the Upper Address Enable (UAEN) Input
is high or low, respectively. In the high impedance state, the host
CEPT PCM 30 Mode (T1/CEPT input lOW). RSER is processed
serially and sampled by the negative edge of RCLK at a rate of
2.04B MHz. RSYNC is synchronous with the rising edge of RCLK
'and bit I' in time slot zero of the first frame of a multiframe.
Figure 10 illustrates the timing.
6-105
•
ISDN/DMI Link Layer Controller
R8071
CHANNEL
BIT 7
I
241
BIT
81
BIT F
CHANNELl
I BIT 1
BIT 2
I
BIT 3
I
BIT 4
I
BIT 5
I
BIT 6
I
BIT 7
I
TCLK
TMAX
r----l ____________________________________________
----~I
I~
~_--,Il,--
FILUMASK'
___
TSEREN(LOW) _____________________________________________________________
HIGH Z
TSER _.J...~~----1
TSEREN (HIGH)
TSER
__.......J'--__- '
, THE F BIT TIME IS PROCESSED AS IF THE FILUMASK
Figure 7.
Transmit Frame Synchronization Timing-T1 Mode (RS070 Interface)
TIME SLOT 31
BIT 7
t
= o. HOWEVER, THIS ACTUAL FILL/MASK DOES NOT APPLY TO THE F BIT.
BIT 8
TIME SLOt 0
BIT 1
BIT 2
I
BIT 3
I
BIT 4
BIT 5
I
BIT 6
I
BIT 7
'I
BIT 8
I
TCLK
TMAX ____~~L-____________________________________________
FILL/MASK
\I...-_-----J
TSEREN(LOW) ____________________________________________________________
TSER
TSEREN (HIGH)
TSER
Figure S.
Transmit Frame Synchronization Tlming-CEPT PCM 30 Mode (RS070 Interface)
6-'106
ISON/OMI Link Layer Controller
R8071
RRED
II
RSYNC~~~
PROVING
PERIOD 1
(LESS THAN OR
EQUAL TO ONE
FULL MULTIFRAME)
PROVING
PERIOD 2
(ONE FULL
MULTIFRAME)
1\
rl
~ y~ L -
PROVING
(ONE FULL
PERIOD 3
MUL TIFRAME)
(ONE FULL
MULTIFRAME)
I- FROM THIS POINT, FULLY
MULTIFRAME·SYNCHRONIZED
UNTIL RRED GOES HIGH
NOTE: ABOVE FIGURE NOT TO SCALE
RCLK
RRED
24'l
r
RSYNC __________~r---l~
CHANNEL
LAST FRAME
OF A
MULTIFRAME
Figure 9.
____________________________________
CHANNEL 1,
FIRST FRAME
OF THE NEXT
MUL TIFRAME
Receive Frame Synchronization Timlng-T1 Mode (RS07O Interface)
RRED~lr-------~lll--------~lilr-------~l.~l--------PROVING
PERIOD 1
(LESS THAN
OR EQUAL TO
-ONE FULL
MULTIFRAME)
PROVING
PERIOD 2
(ONE FULL
MULTIFRAME)
J
PROVING
(ONE FULL
PERIOD 3
MULTlFRAME)
(ONE FULL
MULTIFRAME)
I
_
NOTE: ABOVE FIGURE NOT TO SCALE
FROM THIS POINT, FULLY
MULTIFRAM E·SYNCHRONIZED
UNTIL RRED GOES HIGH
RCLK
RRED
RSYNC ____________~r---l~
TIME SLOT 31"
LAST FRAME
OF A
MULTIFRAME
Figure 10.
_______________________________
TIME SLOT 0,
FIRST FRAME
OF THE NEXT
MULTIFRAME
Receive Frame Synchronization-CEPT PCM 30 Mode (RS070 Interface)
6·107
•
ISON/OMI Link Layer Controller
R8071
EXTERNAL SHARED MEMORY
ORGANIZATION AND DEFINITION
The upper address lines (AS-A15) are placed in the high
impedance state by the R8071 during the System memory
accesses (i. e., while the Channel Activation Byte or Channel
Buffer Pointers are being accessed) when the UAEN input is
high.
GENERAL STRUCTURE
Transmit data, received data, channel commands and channel
pointers are organized In the external memory shared by the host
and R80n.
CHANNEL DATA BUFFERS
A buffer is a group of contiguous memory locations for each
meaningful group of ordered data. The number of memory locations In a buffer depends on memory availability and user data
frame size, If any. For example, a group of contiguous memory
locations may be assigned to the data that has to be framed
according to HDLC protocol. The data has to be grouped into
an 8-bit entity, also referred to as octet or byte. If necessary, one
octet IS read from or written to the data buffer by the R8071 during
a single memory access.
For each transmit and receive channel, the host must allocate
shared memory for a channel activation byte, channel buffer
pointers, and a set of channel data buffers. Figure 11 illustrates
an arrangement of shared buffer memory within the host computer main memory.
The Channel Activation Byte and the Channel Buffer Pointers
are located in a 256-byte address space referred to as system
memory (Figure 12). The Channel Activation Byte is located at
address j followed by 127 unassigned bytes. The Channel Buffer
Pointers are located at addresses j + 128 through j + 255. The
Channel Data Buffers are located at starting addresses specified by the channel pOinters. The length of the data buffers IS
specified in data descriptors included within the data buffer.
The Ch!lnnel Data Buffers (also referred to as the data buffers)
may reside anywhere in the memory within the addressing range
of the Channel Buffer Pointers. Any number of data buffers may
be assigned for any channel and their starting addresses may
be changed at any time. A set of data buffers are usually assigned
for each active channel for storing the data to be transmitted and
another set for the received data.
CHANNEL ACTIVATION BYTE
TRANSMIT DATA/COMMAND BUFFER ORGANIZATION
The Channel Activation Byte (Figure 12) contains a command
to activate or deactivate the channel number identified within
the byte. The direction of data travel is also specified. The
individual bits are defined as follows:
A general organization of data within a buffer and the linking of
buffers are Illustrated In Figure 13. The detail contents of a
Transmit Data Buffer are shown in Figure 14. The contents of
a Transmit Command Buffer are shown in Figure 15. Information
Within the buffer is organized into two groups: descriptors and
data.
ACTIVE-Activate Channel. When set by the host, the Indicated
channel (CHANNEL number) is activated. When reset by the
host, the channel is deactivated.
The first group of seven bytes contains the buffer descriptors,
Le., Information such as the link (pointer) to the next transmit
data buffer, buffer size, the number of data bytes in the buffer
and buffer status. This group of information is mandatory for each
buffer.
RX/TX-Receive/Transmit. When set by the host, the indicated
channel is a receive channel. When reset by the host, the
channel is a transmit channel.
The second group contains k-bytes of information, k being a variable number. This group contains user data (including any
header) that has to be framed according to HDLC, data to be
transmitted unframed, or channel mode and fill/mask information.
CHANNEL-Channel Number. Set by the host to select the number of the channel:
Bit
432
o
Channel Number
00000
0
1
31
1
1
TRANSMIT CHANNEL DESCRIPTORS
The breakdown and the ordering of the seven bytes of descriptors appears in Figure 14. The first six bytes contain the next
buffer address, the buffer size and the data length-each consisti ng of two bytes. The relative locations of the upper and the
lower bytes are Interchangeable by the use of the input strap
pin MDFS. The seventh byte contains the status of the current
transmit buffer as well as the status of the transmit channel. A
byte not used by the R80n, and free to be used by the host,
will proceed or follOW the status byte as determined by MDFS
(Figure 14).
CHANNEL BUFFER POINTERS
The Channel Buffer POinters specify the start addresses for the
Channel Data Buffers. The pOinters must be stored by the host
in 128 contiguous bytes beginning at j + 128. For each channel,
the buffer start address IS to be specified as a 16-bit (2-byte) word.
The relative location of the upper and lower bytes of the 16-blt
word IS determined by the MDFS input (Figure 12). Pointers for
up to 32 transmit and 32 receive channels can be specified.
Next Buffer Start Address
Bytes 0 and 1 contain the 16-bit start address of the next buffer.
The next buffer start address can be the same as that of the current buffer. Such a buffer is referred to as a recirculating buffer.
6-108
ISDN/OM I Link Layer Controller
R8071
BYTE
ADDRESS
(DECIMAL)
CONTENTS
I
7
0
2
3
6
5
4
3
2
o
"'"
CHANNEL ACTIVATION BYTE
j + 128
j + 255
"'"
P
P + 1
P + n - 1
"'"
•
x
x+n- 1
r2222I
SHARED MEMORY FOR SYSTEM INITIALIZATION
~
SHARED MEMORY CHANNEL·SPECIFIC DATA AND COMMAND BUFFERS
Figure 11.
External Shared Memory Map-Top Level
6-109
ISDN/OM I Link Layer Controller
R8071
WORD
ADDRESS
(HEX)
BYTE
ADDRESS
(HEX)
7
XXXOO
XXXOO
ACTIVE
CONTENTS
6
5
4
I
3
REMARKS
o
2
CHANNEL NUMBER
CHANNEL ACTIVATION BYTE
XXX01
==
BYTE ADDRESSES XX01 THROUGH XX7F ARE NOT USED BY RB071
==
XXX7F
XXX40
xxX 4 1
XXXBO
TRANSMITTER CHANNEL 0 START ADDRESS (HIGH ORDER BYTE)
XXX B1
TRANSMITTER CHANNEL 0 START ADDRESS (LOW ORDER BYTE)
XXX82
TRANSMITTER CHANNEL 1 START ADDRESS (HIGH ORDER BYTE)
XXXB3
TRANSMITTER CHANNEL 1 START ADDRESS (LOW ORDER BYTE)
==
XXX5F
==
TRANSMITTER CHANNELS 2 TO 30 START ADDRESSES
XXXBE
TRANSMITTER CHANNEL 31 START ADDRESS (HIGH ORDER BYTE)
XXXBF
TRANSMITTER CHANNEL 31 START ADDRESS (LOW ORDER BYTE)
XXXCO
RECEIVER CHANNEL 0 START ADDRESS (HIGH ORDER BYTE)
XXXC1
RECEIVER CHANNEL 0 START ADDRESS (LOW ORDER BYTE)
CHANNEL BUFFER POINTERS
XXX60
RECEIVER CHANNELS 1 TO 30 START ADDRESSES
xxX 7 F
XXXFE
RECEIVER CHANNEL 31 START ADDRESS (HIGH ORDER BYTE)
XXXFF
RECEIVER CHANNEL 31 START ADDRESS (LOW ORDER BYTE)
a.
WORD
ADDRESS
(HEX)
BYTE
ADDRESS
(HEX)
7
XXXOO
XXXOO
ACTIVE
X
MDFS; HIGH (6S000-BASED)
CONTENTS
xx0 1
==
I
4
6
5
x
I RX/TX I
3
REMARKS
2
o
CHANNEL NUMBER
BYTE ADDRESSES XX01 THROUGH XX7F ARE NOT USED BY R8071
CHANNEL ACTIVATION BYTE
==
XXX7F
XXX40
xxX 4 1
XXXBO
TRANSMITTER CHANNEL 0 START ADDRESS (LOW ORDER BYTE)
XXXB1
TRANSMITTER CHANNEL 0 START ADDRESS (HIGH ORDER BYTE)
XXXB2
TRANSMITTER CHANNEL 1 START ADDRESS (LOW ORDER BYTE)
XXXB3
TRANSMITTER CHANNEL 1 START ADDRESS (HIGH ORDER BYTE)
TRANSMITTER CHANNELS 2 TO 30 START ADDRESSES
XXX5F
XXXBE
TRANSMITTER CHANNEL 31 START ADDRESS (LOW ORDER BYTE)
XXXBF
TRANSMITTER CHANNEL 31 START ADDRESS (HIGH ORDER BYTE)
CHANNEL BUFFER POINTERS
XXX60
XXXCO
RECEIVER CHANNEL 0 START ADDRESS (LOW ORDER BYTE)
XXXC1
RECEIVER CHANNEL 0 START ADDRESS (HIGH ORDER BYTE)
RECEIVER CHANNELS 1 TO 30 START ADDRESSES
XXX7F
XXXFE
RECEIVER CHANNEL 31 START ADDRESS (LOW ORDER BYTE)
XXXFF
RECEIVER CHANNEL 31 START ADDRESS (HIGH ORDER BYTE)
b.
Figure 12.
MDFS ; LOW (iAPX 86-BASED)
System Memory Map Locations
6-110
==
ISON/OMI Link Layer Controller
R8071
BYTE
ADDRESS
BUFFER 1
7
0
NEXT BUFFER START ADDRESS
7 BYTES OF BUFFER DESCRIPTORS
i+7
(i+7)+1
k BYTES OF DATA TO BE TRANSMITTED
(TRANSMIT DATA BUFFER)
OR
2 BYTES OF CHANNEL MODE
AND RATE DEFINITION DATA
(TRANSMIT COMMAND BUFFER)
"'"
"'"
~
(i+7)+k
BUFFER 2
7
m
0
NEXT BUFFER START ADDRESS
7 BYTES OF BUFFER DESCRIPTORS
m+7
(m + 7) + 1
n BYTES OF DATA TO BE TRANSMITTED
(TRANSMIT DATA BUFFER)
OR
2 BYTES OF CHANNEL MODE
AND RATE DEFINITION DATA
(TRANSMIT COMMAND BUFFER)
"'"
"'"
(m+7)+n
BUFFER N
7
0
NEXT BUFFER START ADDRESS
P
7 BYTES OF BUFFER DESCRIPTORS
p+7
(p+7)+1
"'"
r BYTES OF DATA TO BE TRANSMITTED
(TRANSNIIT DATA BUFFER)
OR
2 BYTES OF CHANNEL MODE
AND RATE DEFINITION DATA
(TRANSMIT COMMAND BUFFER)
"'"
(p+7)+r
Figure 13.
Organization and Linking of Transmit Buffers.
6-111
•
ISDN/OM I Link Layer Controller
R8071
BYTE
ADDRESS
i
CONTENTS
7
msb
I
I
6
I
4
X
X
FC
I
3
2
I
I
1
I
Isb
UNDR IVBA
X
X
msb
i+5
i+6
_
(0)
CF/P CMND MPTY
X
i+l
I
6
I
5
I
4
X
FC
I
3
I
2
I
X
X
X
I
FO
I x
X
UNDR IVBA
I
I
X
i+7
NOT USED BY RB071
(1+7)+1
FIRST DATA BYTE
(i+7)+2
SECOND DATA BYTE
(i+7)+2
SECOND DATA BYTE
(i+7)+j
LAST DATA BYTE
(i + 7)+)
LAST DATA BYTE
(i+7)+j+l
FLAG COUNT (OPTIONAL)
(i+7)+j+l
FLAG COUNT (OPTIONAL)
(i+7)+k
LAST LOCATION IN BUFFER
(i + 7) + k
LAST LOCATION IN BUFFER
= High
b.
Figure 14.
BYTE
ADDRESS
i
I
6
I
5
I
4
I
I
3
2
I
NEXT BUFFER ADDRESS (i)
i+l
i+2
1
I
0
Isb
CONTENTS
BYTE
ADDRESS
i
7
i+l
msb
I
6
I
5
I
4
I
3
I
2
I
NEXT BUFFER ADDRESS (i)
NOT USED BY R8071
NOT USED BY RB071
i+3
i+4
NOT USED BY R8071
1
I
0
Isb
i+
NOT USED BY RB071
i+6
(i+7)+l
Low
i+2
i+5
i+7
=
NOT USED BY RB071
i+3
i+4
MDFS
Transmit Data Buffer Contents
CONTENTS
7
msb
0
Isb
DATA LENGTH 0) Isb
msb
STATUS
_
(0)
X
CF/P CMND MPTY
X
FIRST DATA BYTE
MDFS
I
BUFFER SIZE (k) Isb
msb
(i+7)+l
8.
1
NEXT BUFFER ADDRESS
i+4
NOT USED BY RB071
STATUS
7
i+3
Isb
i+6
CONTENTS
BYTE
ADDRESS
1
i+2
x I msbDATA LENGTH 0)
I x
FO
Isb
i+5
i+7
0
x I mSbBUFFER SIZE (k)
X
i+3
i+4
I
NEXT BUFFER ADDRESS
i+l
i+2
5
STATUS
UNDR IVBA I
x
x
i+6
(1)
I CF/P ICMNDI MPTY
x
0
0
o
(i+7)+1
I INV ILOOpl SIG IHDLC
FILL/MASK
(i+7)+2
8.
0
x
I CF/P
IC~~DI MPTY
I INV I LOOP I SIG IHDLC
FILL/MASK
b.
Transmit Command Buffer Contents
o
0
(i + 7) + 2
6-112
x
MODES
0
MDFS = High
Figure 15.
x
NOT USED BY R8071
i+7
MODES
0
STATUS
UNDR IVBA I
MDFS
= Low
ISDN/OM I Link layer Controller
R8071
Buffer Size
ThiS flag control feature IS very useful In rate adapliOn of
sub-64 kbps data rates to the 64 kbps bearer channel rate and also
as a timer The R8071 automatically goes to the next buffer after
sending the speCified number of flags.
Bytes 2 and 3 contain the 12-bIt BUFFER SIZE, k The BUFFER
SIZE specifies the total number of memory bytes allocated by the
host processor for storing the data to be transmitted The four
most Significant bits are not used by the R8071
In the non-HOLe data mode, the R8071 sends the speCified
number of all ones octets after the last data byte.
The R8071 reads the buffer size only If the status Indicates that
the data buffer contains partial data and then Interprets the buffer
size to be the actual number of data bytes In thiS buffer The R8071
does not read thiS word when the data buffer IS a command buffer
For the non-HOLC Signaling channel, buffers need to be specIfied to be partial data buffers for meaningful operation. In such
a case, FC Will not be read
Data Length
When FC IS reset, no additional flags are transmitted The R8071
does not process the FC bit In a command buffer.
Bytes 4 and 5 contain the 12-blt DATA LENGTH field and a 2-blt
field containing host processor options for rate adaptation and
timer functions The remaining 2-blt field IS not used by the R8071
Transmit Buffer Status
The Transmit Buffer STATUS byte contains the status of the current
transmit buffer as well as Ule status of the transmit channel
(Figure 14) The indiVidual bits are defined as follows
Data Length-DATA LENGTH, J, specifies the ac[ual number of
data bytes In the buffer to be transmitted. The R8071 reads DATA
LENGTH only If the status indicates that the buffer contains the
last byte of an HOLC frame or non-HOLC data (CF/P ~ 1).
MPTY-Empty. ThiS bit IS set by the host to Inform the R8071 that
the data buffer IS empty, I e., data IS not ready for transmiSSion
The host resets thiS bit when the buffer contains valid data ready
for transmiSSion. When the buffer IS empty, the R8071 keeps
polling thiS bit until It IS non-empty
FO-Flag Offset Control. ThiS bit IS meaningful only when FC
IS set. When Fa IS set by the host, the transmitter of the specific
channel counts the total number of HOLC zeroes intentionally
Inserted over the data and the CRC fields for the entire duration
of transmission. At the end of each HOLC frame, It diVides the
accumulated number by eight and retains the remainder. The
quotient IS known as the flag count offset. The quotient represents
the number of bytes of non-data entities transmitted and can be
Viewed as the HOLC Intra-frame fill. The R8071 subtracts the flag
count offset from the FLAG COUNT which was speCified Without
the knowledge of the Inserted zeroes The resultant count equals
the actual number of addlliOnal flags that are transmitted by the
R8071. ThiS IS extremely useful In synchronous data rate-adaptlon
applications.
ThiS bit IS set by the R8071 to Inform the host that the R8071 has
completed transmiSSion of all the data In thiS buffer or completed
processing a command buffer
CMND-Command. ThiS bit IS set by the host to Inform the R8071
that thiS buffer IS a command buffer. A command buffer contains
channel-specific mode definition and FILL/MASK information
ThiS bit IS reset by the host to indicate thatthe buffer IS a data buffer
which contains transmit data Upon writing status, the R8071 Will
update the CMNO bit according to the buffer type Just processed
The flag count offset can be any number from zero through three,
ImplYing that HOLC frames long enough to cause up to 24 zero
insertions can be monitored by the transmitter Without any overflow of the Internal2-blt flag count offset If the resultantflag count
after subtracting the offset IS zero or negative, no additional flags
are transmitted
CF/P-Complete Frame/Partial Data Buffer. ThiS bit IS set by
the host to indicate that thiS buffer contains the last byte of a
sequence of bytes to be formatted according to HOLC The R8071
automatically appends CRe and flag to the data before looking
for more data In the next buffer The actual number of data bytes
IS speCified by the 12 bit DATA LENGTH words
When FC IS a 0, the FLAG COUNT IS not adjusted. For appllcaliOns such as LAPO which require an opening flag and a separate
clOSing flag, FC should be set, Fa reset, and FLAG COUNT set
to 1
In non-HOLC appllcaliOns, thiS bit must be reset to indicate
continuous data transmiSSion, otherwise the all ones octet pattern
Will be transmitted after the last byte of data In a buffer.
ThiS bit IS reset by the host to Indicate that thiS buffer contains only
a part of the data to be transmitted; the rest perhaps IS In one or
more succeeding buffers. Such a buffer IS referred to as a partial
data buffer In thiS case, the R8071 transmits all the data In thiS
buffer and then automatically transmits any data In the next buffer.
The actual number of data bytes IS speCified by the 12-blt BUFFER
SIZE word.
In a non-HOLC mode, the flag count offset Will always be zero. The
state of Fa does not matter.
FC-Flag Control. When set by the host, thiS bit speCifies that
the corresponding HOLC channel transmitter contains a certain
number of HOLC flags after the CRC. A minimum of one FLAG
that plays the dual role of the clOSing FLAG of the current frame
and the opening FLAG of the next frame IS sent regardless of Fe
The actual number of addlliOnal flags to be transmitted when FC
IS a 1 IS dependent on the opliOnal FLAG COUNT byte shown In
Figure 14
The R8071 does not read the CF/P bit In a command buffer It
Will, however, set the CF/P bit when reporting status for a
processed command buffer The CF/P bit Will also be set upon
completion of the first Signaling (partial) buffers
6-113
II
ISON/OMI Link Layer Controller
R8071
Non-HDLe Signaling Channel Mode. The channel carries bit-
IVSA-Invalld Buffer Address. This bit is set by the A8071 if it
encounters an invalid next buffer address, i.e., a next buffer
address with a starting address of 16 zeroes or hexadecimal FFFX
(X don't care). In this case, the specific transmit channel of the
A8071 enters the inactive state and continuously transmits octets
of all ones until a channel is reactivated by the host.
oriented signaling data without an HOLC format. The A8071 treats
this channel without any special consideration to signaling.
However, the A8071 assumes that only one, or at the most two,
linked data buffers are assigned to the signaling channel by the
host. Additionally, the last data buffer (even if it is the only buffer)
is assumed to be a recirculating buffer.
=
UNOR-Underrun. This bit is set by the A8071 when its transmit
channel runs out of data. Such is the case when the A8071
encounters either an invalid buffer address, an empty data buffer,
or a command buffer following a partial data buffer. In HOLC mode,
the transmitter of the specific channel automatically transmits an
ABORT code, followed by FLAGs until the condition is cleared.
In all cases of underrun, the non-HOLC transmit channel sends
the all ones octet pattern repeatedly until a valid non-empty data
buffer is set up by the host. The remaining bits in the status byte
will not be read by the A8071, however, they will be reset upon a
status update.
Non-HDLe Data Channel Mode. The channel is a non-HOLC data
channel. In OMI applications, data modes 0 and 1 may be specified by this combination. The CFip bit of the status byte
of the allocated data buffers must be reset for uninterrupted data
transmission, otherwise, the A8071 will transmit the all ones octet
pattern repeatedly after the last byte as many times as is dictated
by FC, FLAG COUNT and the availability of the data in the next
buffer. The channel time fill and the idle codes are one and the
same.
HDLe Data Channel Mode. The channel is an HOLC data channel
or a LAPO message-oriented HOLC signaling channel. No distinction is made between an HOLC data channel and a LAPO channel. No special handling is done on the header, i.e., address and
control fields of the HOLC frame. The information field is assumed
to be an integer number of octets or bytes. The 16-bit CAC-CCITT
generatorpolynomlal,X'6 + X" + X5 + 1 IS used for calculating
the FCS. The transmitted ABORT sequence has 14 consecutive
ones to satisfy SOLC and HOLC requirements.
TRANSMIT DATA BUFFER
A transmit data buffer contains actual data to be transmitted and
optional FLAG COUNT byte for rate adaption (Figure 14).
TRANSMIT COMMAND BUFFER
A transmit command buffer contains exactly two bytes of data following the seven bytes of descriptors (Figure 15).
INV-Invert Data. When set by the host, the A8071 inverts the data
priorto transmission whenever the channel is active. When reset
by the host, the A8071 sends the data non-inverted, I.e., as It IS
read from the transmit buffer. With INV bit set by the host (when
the channel IS idle), an octet of eight zeroes (Os) is sent for HOLC
or non-HOLC channels. However, when INV is not set, an octet
of eight ones (ls) is sent for idle code. All other data including HOLC
flag and ABORT is conditioned by the INV bit.
The first byte (MODE) defines the channel modes of operationspecifically HOLC, Signaling, data inversion and loop back. The
second byte (FILL/MASK) defines the data rate. The breakdown
and the ordering of bytes within the command buffer are illustrated
in Figure 15.
For a command buffer, the A8071 will not process the bytes at
addresses [i + 2, i + 3] and [i + 4, i + 5] as the data length is presumed to be exactly 2 bytes. However, the A8071 will read the next
buffer address at locations i and i + 1 as part of processing the command buffer. As mentioned before, the relative locations of the
upper and the lower bytes of the next buffer address are interchangeable by means of MOFS. The mode and FILL/MASK bytes
locations are not interchangeable by MFOS.
Note that the combination of the HOLC procedure and data inversion guarantee that there will not be more than five consecutive
zero bits In any primary rate channel during data transmission or
seven consecutive zero bits dUring ABOAT transmission.
LOOP-Loop Mode. When set by the host, the associated transmit channel data is stored internally in A8071 in addition to being
transmitted. If the LOOP bit for the corresponding receive channel is also set, the previously stored transmit channel data can be
looped back to the shared memory through the receive channel.
MODES
The MODES byte specifies the operational modes of the given
channel-specifically, HOLC or non-HOLC, signaling channel or
not, data to be inverted bit-by-bit prior to transmission or not and
channel transmit data to be looped back via the receiver to the
host shared memory or not (Figure 14).
Only one channel can be placed In LOOP mode at any time for
reliable loop operation. But the loop channel number, the
FILL/MASK and its mode can be specified independently for any
transmit and receive channel and need not be identical. Such a
provision makes possible powerful software-based diagnostics
routines.
SIG and HOLe- Mode Select. These two bits select the A8071
framing mode.
SIG
HOLC
1
0
0
1
0
0
1
1
Mode Selected
Note that the loop mode operation will fall without the host being
informed if the host programs only a transmit channel in the loop
mode without programming a receive channel. However, the host
shared memory will still be filled with the external serial data of
the channel, if the ehannel is active.
Non-HOLC Signaling Channel Mode
Non-HOLC Data Channel Mode
HOLC Data Channel Mode
Aeserved
6-114
ISDN/OM I Link Layer Controller
R8071
FILL/MASK
The second byte of a command buffer contams the FILL/MASK
pattern. It IS used as a masking pattern on the HDLC-formatted
(mcludmg FLAG, header, data, CRC and ABORT code) or nonHDLC data to adapt subrates that are multiples of 8 kbps to the
64 kbps rate
buffer address, the buffer size and the data length-each
consisting of two bytes. The relative locations of the upper and the
lower bytes are Interchangeable by the use of the Input strap Pin
MDFS The seventh byte contains the status of the current receive
buffer as well as the status of the receive transmit channel A byte
not used by the R80?1, and free to be used by the host, Will proceed or follow the status byte as determined by MDFS (Figure 14)
TRANSMIT CONSIDERATIONS
Minimum Number of Data Bytes in a Buffer
Next Buffer Start Address
There IS a minimum number of data bytes required m each buffer
In order for the R80?1 to perform the buffer maintenance and stili
effect a smooth transition to the next buffer. The minimum number of bytes depends on the type of the buffer and that of the follOWing buffer. Table 2 gives a summary.
Bytes 0 and 1 contain the 16-blt NEXT BUFFER ADDRESS Written by the host The meaning of Invalid and recirculating buffers
are the same as those for the transmit buffer.
Maximum Number of Data Bytes in a Buffer
Bytes 2 and 3 contain the 12-bIt BUFFER SIZE, k, written by the
host The BUFFER SIZE speCifies the total number of memory
bytes allocated by the host for storing the data to be received The
four most Significant bits are not used by the R80?1
Buffer Size
The number of data bytes In a complete frame buffer, as specIfied by the DATA LENGTH word, should not exceed 4095 (2'2_1)
ThiS does not Include the optional one-byte FLAG COUNT The
number of data bytes In a partial data buffer, as speCified by the
BUFFER SIZE word, should not exceed 4095 (2'2-1)
The R80?1 reads It and stores It for a!1 except command buffers
If the last byte of a receive HDLC frame IS not received before the
buffer IS completely filled, the R80?1 automatically searches for
the availability of the next buffer speCified.
RECEIVE DATA BUFFER/COMMAND ORGANIZATION
A general organization of data Within a buffer and the Ilnkmg of
receive buffers IS Illustrated In Figure 16 The detail content of a
Receive Data Buffer IS shown In Figure I? The content of a
Receive Command Buffer IS shown In Figure 18. Information Within
the buffer IS organized In to two groups' deSCriptors and data.
Data Length
Bytes 4 and 5 contain the 12-blt DATA LENGTH field, j, written by
the R80?1. DATA LENGTH speCifies the actual number of received
data bytes transferred to the receive data buffer by the R80?1 The
four most significant bits are not used. (The R80?1 clears these
bits to zeroes.)
The first group of bytes contains the buffer deSCrIptors, I.e , information such as the link to the next buffer, buffer Size, the number
of data bytes In the buffer and buffer status. ThiS group of information IS mandatory for each buffer.
DATA LENGTH IS written by the R80?1 after It receives the last byte
of an HDLC frame, receives the HDLC ABORT code, or upon the
loss of multlframe alignment error from a non-HDLC Signaling
chan nel. DATA LENGTH IS not written If the end of the allocated
buffer IS reached before the last byte IS received (data frame length
greater than buffer size) In such a case, the data length IS equal
to the given buffer size. Also, data length may not be written If the
ATTN Input IS asserted, resulting In the deactivatiOn or reactivation of an active channel. DATA LENGTH Will not exceed the
programmed buffer size DATA LENGTH IS not meaningful In a
command buffer.
The second group contains k-bytes of mformatlon, k being a variable number They may be the received data (mcludmg any
header) after processing by R80?1 (If necessary), or channel mode
and data rate definitiOn information as speCified by the host
processor.
RECEIVE CHANNEL DESCRIPTORS
The breakdown and the ordering of the seven bytes of deSCriptors IS shown m In Figure I? The first SIX bytes contain the next
Table 2.
-Current Buffer Status
as Set Up by Host
,------~
II
Minimum Number of Data Bytes
~
Next Buffer Status
as Set Up by Host
CMND
MPTY
CF/P
CMND
MPTY
CF/P
Min. No. of
Data Bytes in
Next Buffer'
1
a
x
a
a
1
2
1
a
x
a
a
a
5
X
a
X
a
X
1
1
a
a
a
X
0
2
5
O
a
1
0
a
1
II
2
I
a
a
0
a
a
1
3
a
a
a
a
a
0
6
Remarks
Complete frame buffer follOWing a
command buffer
Partial data bufffer follOWing a com·
mand buffer
Command buffer follOWing any buffer
Partial data buffer follOWing a complete frame buffer
I
'omo'~
'.m,
'O,,~'""
~
complete frame buffer
'0'"
Complete frame buffer follOWing a
parllal data buffer
Parllal data buffer follOWing a parllal
data buffer
'Data byte refers only to the actual header data or IIlformatlon or mode but not the buffer deSCriptors or the optional flag count
6-115
ISDN/OM I Link Layer Controller
R8071
BYTE
ADDRESS
BUFFER 1
7
0
NEXT BUFFER START ADDRESS
7 BYTES OF BUFFER DESCRIPTORS
i+7
(i+7)+1
k BYTES FOR RECEIVED DATA
(RECEIVE DATA BUFFER)
OR
2 BYTES OF CHANNEL MODE
AND RATE DEFINITION DATA
(RECEIVE COMMAND BUFFER)
""
""
(i+7)+k
BUFFER 2
7
m
0
NEXT BUFFER START ADDRESS
7 BYTES OF BUFFER DESCRIPTORS
m+7
(m+7)+1
n BYTES FOR RECEIVED DATA
(RECEIVE DATA BUFFER)
OR
2 BYTES OF CHANNEL MODE
AND RATE DEFINITION DATA
(RECEIVE COMMAND BUFFER)
""
""
(m+7)+n
BUFFER N
7
0
NEXT BUFFER START ADDRESS
P
7 BYTES OF BUFFER DESCRIPTORS
p+7
(p+7)+l
""
r BYTES FOR RECEIVED DATA
(RECEIVE DATA BUFFER)
OR
2 BYTES OF CHANNEL MODE
AND RATE DEFINITION DATA
(RECEIVE COMMAND BUFFER)
""
(p+7)+r
Figure 16.
Organization and Linking of Receive Data Buffers
6-116
ISDN/OM I Link Layer Controller
R8071
CONTENTS
BYTE
ADDRESS
7
I
msb
I
6
I
5
4
I
2
131
I
1
1+1
I
Isb
mSbBUFFER SIZE (k)
1+3
1+4
X
I
X
I
X
X
I
mSb DATA LENGTH (J)
1+5
I
6
1+1
5
I
4
I
Isb
msb
I
1+3
1+4
Isb
1+5
1+6
STATUS
3
I
I
2
Nor USED BY R8071
(1+7)+1
FIRST DATA BYTE
(1+7)+1
FIRST DATA BYTE
(1+ 7)+2
SECOND DATA BYTE
(1+7)+2
SECOND DATA BYTE
LAST LOCATION IN BUFFER
(1+7)+k
B.
MDFS
7
I
msb
1 6 JSl413L 21
NEXT BUFFER ADDRESS (I)
1+1
1+2
1+4
10
Isb
STATUS
OVER IVBA
X
1X
X
X
X
X
I INV I
8.
MDFS
1
S
CONTENTS
BYTE
ADDRESS
I
7
1+1
msb
1
6
1+6
(1)
CFip ICMNDI MPTY
1+7
LOopl SIG JHDLC
(1+7)+1
2
I
1
I
0
Isb
Nor USED BY R8071
STATUS
OVER IVBA 1 X
X
X
I CFip
IC~~DIMPTY
Nor USED BY R8071
X
X
FILUMASK
b.
Receive Command Buffer Contents
MODES /1
'/
/1
X 1 INV LOOP SIG HDLC
X
(1+7)+2
6-117
131
Nor USED BY R8071
= High
Figure 18.
4
I
NEXT BUFFER ADDRESS (I)
1+5
FILUMASK
(1+7)+2
MDFS = Low
1+3
1
X
MODES
b.
1+4
Nor USED BY R8071
1+7
:
LAST LOCATION IN BUFFER
1+2
Nor USED BY R8071
1+5
(1+7)+1
1
:
Receive Data Buffer Contents
Nor USED BY R8071
1+3
:
= High
CONTENTS
BYTE
ADDRESS
:
(1+7)+k
Figure 17.
1+6
I (1+ 7)+j
:
:
0
Isb
1
1X 1X
1+7
:
I
DATA LENGTH (J) Isb
X
msb
STATUS
(0)
OVER IVBA ABRT FCER SHER CFip CMND MPTY
X
(0)
OVER IVBA ABRT FCER SHER CFip CMND MPTY
:
1
BUFFER SIZE (k) Isb
msb
1+7
(1+7)+1
I
NEXT BUFFER ADDRESS
1+2
Nor USED BY R8071
1+6
CONTENTS
7
I
NEXT BUFFER ADDRESS
1+2
BYTE
ADDRESS
0
I
MDFS
= Low
•
ISDN/OM I Link Layer Controller
R8071
Receive Buffer Status
is written as part of the status of the just completed buffer. Also
note that no overrun Will be reported for non-HOLC signaling
channel data buffers. New data will be written in place of any
earlier received Signaling data.
The Receive Buffer STATUS byte specifies the status of the
current receive buffer as well as the status of the receive channel. The individual bits are defined as follows.
MPTY-Empty. This bit is set by the host to inform the RB071
that the buffer is empty, i.e., available for storing the received
data. When the bit is reset, the buffer is not empty , i. e., not
available to store the received data. The RB071 polls this bit until
it is empty before it writes the received data.
Table 3.
This bit is reset by the RB071 whenever it updates the buffer
status. This is the case even if the RB071 writes only a single
byte and then is forced to update the buffer status because of
abnormal conditions.
CMNO-Command. This bit is set by the host to inform the
RB071 that this buffer is a command buffer. The command buffer
contains channel-specific mode definition and FILUMASK infor·
mation at the next two bytes following the STATUS byte. This bit
is reset by the host to indicate that this buffer is a data buffer
meant to store received data.
Receive Buffer Status-Error Table
ABRT
FCER
SHER
Description
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
No errors detected
Short or Non-integer HDLC Frame Error
CRC Error
CRC Error & Non-Integer Error
HDLC ABORT Code Received
Non-HDLC Multiframe Alignment Lost
Elastic Buffer Error & RSYNC Error
RRED Alarm
RECEIVE COMMAND BUFFER
A receive command buffer IS identical to the transmit command
buffer in that it contains exactly two-bytes of data following the
STATUS byte for defining the channel modes and data rate.
CF/P-Complete Frame/Partial Data Buffer. This bit may be
reset by the host at buffer initialization. This bit is set by the RB071
to Indicate that this buffer contains the last byte of an HOLC
frame. The RB071 automatically verifies the CRC and the starts
the next HOLC frame before writing the data of the next HOLC
frame in the next available buffer. In HOLC and Non-HOLC
modes, if the reception of data is truncated by a resync condi·
tion asserted by an ABORT, RSYNC. TMAX or RREO, the RB071
sets the CF/P bit and writes the OATA LENGTH of the truncated
buffer. In signalling Channel Mode, when two consecutive signalling synchronization errors are encountered, the RB071 will
also set the CF/P bit.
The first byte (MOOE) defines the channel modes of operationspecifically HOLC. signaling. data inversion and loop back. The
second byte (FILUMASK) defines the data rate. A data buffer
contains the actual data received after processing by the RB071.
The breakdown and the ordering of bytes within the command
buffer are illustrated in Figure lB.
For a command buffer, the RB071 does not process the bytes
at addresses [i + 2. i + 3] and [i + 4, i + 5] as the data length is
presumed to be exactly two bytes. However, the RB071 reads the
next buffer address at locations I and i + 1 as part of processing
the command buffer. As mentioned before, the relative locations
of the upper and the lower bytes of the next buffer address are
interchangeable by means of the MOFS input. The mode and
FILUMASK bytes locations are not interchangeable by MOFS.
This bit is reset by the RB071 to indicate that this buffer contains
only a part of the received data and that more data is expected
to be placed in one or more succeeding buffers. In HOLC mode,
it implies that the last byte of the HOLC frame is not in this buffer.
For non-HOLe data and signaling channels, this bit will be invari·
ably reset after the buffer is filled. The RB071 does not read the
CF/P bit in a command buffer. Note that the host can detect
whether a received HOLC frame size exceeded the maximum
anticipated buffer size by simply checking for CF/P to be set in
the starting buffer of the HOLC frame.
MODES
The MOOES byte is the first byte following the status byte and
specifies the operational modes of the given channelspeCifically, HOLC or non-HOLC, signaling channel or not, data
to be inverted bit-by-bit prior to receiver processing or not and
channel receive data source to be the loop register or not.
ABRT-Abort. This bit is written by the RB071 and, in conjunction within the FCER and SHER bits, reports abnormal conditions detected by the RB071 (see Table 3).
FCER-Frame Check Error. This bit is written by the RB071 and,
in conjunction within the ABRT and SHER bits, reports abnormal
conditions detected by the RB071 (see Table 3).
SIG
HOLC
1
o
o
o
o
SHER-Short HOLC Frame Error. This bit is written by the RB071
and, in conjunction within the ABRT and FCER bits. reports
abnormal conditions detected by the RB071 (see Table 3).
IVBA-Invalid Buffer Address. This bit is set by the RB071 if
it encounters an invalid next buffer address. In this case, the
specific receive channel enters the idle state and will not receive
more data until re·activated by the host.
1
Mode
Non-HOLC Signaling Channel Mode
Non·HOLC Oata Channel Mode
HOLC Oata Channel Mode
Reserved
Non·HOLe Signaling Channel Mode. The RB071 processes the
received bit-oriented Signaling data without the HOLC format
(G.732 or OMI). The RB071 arranges the received signaling data
as in Figure 19 for easy association of the channel number and
its signaling bits. In addition, errors in multiframe alignment
sequence will be detected and any resulting loss of multiframe
alignment will be reported in the STATUS byte.
OVER-Overrun. This bit is set by the RB071 after its receive
channel has no next data buffer available for received data. Note
that a command buffer is not available for data. The OVER bit
6·118
ISDN/DMI Link Layer Controller
R8071
BYTE
ADDRESS
CONTENTS
7
I
6
i
5
141
3
I
2
I
1
I
i+2
7
I
6
I
•
1+2
1+7
I
5
I
4
2
131
I
1
I
0
NEXT BUFFER AOORESS = i or j
1+1
,~
REST OF THE OESCRJPlORS
i+7
CONTENTS
BYTE
ADDRESS
0
NEXT BUFFER AOORESS = I or J
i+1
"
I
=
,~
REST OF THE OESCRIPlORS
(i+7)+1
X
1
X
X
X
B1
A1
A13
(1+7)+1
017
C17
B17
A17
01
C1
B1
A1
(i+7)+2
X
1
X
X
X
B2
A2
A14
(1+7)+2
018
C18
B18'
A18
02
C2
B2
A2
(i+7)+3
X
1
X
X
X
B3
A3
A15
(1+7)+3
019
C19
819
A19
03
C3
83
A3
C27
B27
A27
011
C11
B11
A11
"
,~
(i+7)+11
X
1
(i+7)+12
X
1
(i+7)+13
X
1
(1+ 7)+14
X
1
X
X
X
B11
A11
A23
(i+7)+11
027
X
X
X
B12
A12
A1
(1+7)+12
028
C28
B28
A28
012
C12
B12
A12
X
X
X
B13
A13
A1
(1+ 7)+13
029
C29
B29
A29
013
C13
B13
A13
X
X
X
B14
A14
A2
(i+7)+14
030
C30
B30
A30
014
C14
B14
A14
(1+ 7)+15
X
1
X
X
X
B15
A15
A3
(1+7)+15
031
C31
B31
A31
015
C15
B15
A15
(i+7)+16
X
1
X
X
X
B16
A16
A4
(1+7)+16
1
1
Ys
1
0
0
0
0
(i + 7)+ 17
X
1
X
X
X
B17
A17
AS
"
(i+7)+23
(1+7)+24
"
*
,=
X
1
X
X
X
B23
A23
A11
1
0
Ys
0
1
1
1
A12
a.
Figure 19.
b.
T1 Mode
CEPT PCM 30 Mode
Receive Buffer Data Arrangement for Non-HOLC Bit-Oriented Signaling Channel
Non-HOLe Data Channel Mode. The channel is a non-HOLC
LOOP-Loop Mode. When set by the host, the R8071 selects
as its input the serial output data from the internal loop data
buffer, as opposed to the externally supplied serial data. If an
identically numbered transmit channel was also programmed to
be in the loop mode earlier, data from that channel is looped
back to the shared memory through the receive channel. The
loop channel number, FILUMASK, and its mode can be specified Independently for any transmit and receive channel and need
not be identical. If no transmit channel has loop activated, the
R80n processes the channel as if a receiver RREO condition
were active for that channel duration.
data channel that can support OMI data modes 0 or 1,
As soon as a channel receiver is activated with mode, the R8071
checks the availability of the allocated buffer and starts placing
the received data in the buffer. After filling a buffer, it updates
the status of the just completed buffer, simultaneously asserting INTR. It then moves on to the next allocated buffer. Since nonHOLC data has no frame boundary, this process Will continue
forever unless the host interrupts by an AnN or the system runs
out of allocated buffers.
FILL/MASK
HOLe Data Channel Mode. The channel is to receive HOLCformatted data. It can imply an HOLC-formatted data channel,
such as the ones in OMI mode 2 or 3 or X.2S LAPB, or a
message-oriented signaling channel as in LAPB. The R8071
treats each one of them the same way and deformats the data.
No special handling is performed on the header, i.e., the address
and control fields of the HOLC frame. The information field is
assumed to be an integer number of octets or bytes. The 16-bit
CRC-CCln generator polynomial, X'. + X'2 + X5 + 1 is used
for recomputing the FCS. Abort and flag characters are recognized as are intentionally inserted zeroes.
The second byte of a command buffer contains the FILUMASK
pattern. It IS used as a masking pattern on the HOLC-formatted
(Including flag, header, data, CRC, and ABORT code) or nonHOLC data to adapt subrates that are multiples of 8 kbps to the
64 kbps rate.
Table 4 shows the data rates of the form n x 8 kbps (n = 1,
2, ... , 8) and several examples of codes for the FILUMASK to
adapt the subrates to the 64 kbps rate. The actual data bit is
transmitted on TSER output as long as the FILUMASK is a 1
at the corresponding bit position. If the FILUMASK = D, a FILL
bit of 1 is transmitted in place of the data bit on TSER as long
as TSEREN = 1. The data bit that is held in favor of the FILL
bit is buffered internally until all the FILL bits have been transmitted corresponding to the FILUMASK bits equalling O.
INV-Invert Data. When set by the host, the R8071 inverts the
received data prior to processing. When INV is reset by the host,
the R8071 does not invert the received data. The INV bit is applied
to every received bit.
6-119
•
ISDN/OM I Link Layer Controller
R8071
,Table 4.
Examples of FILL/MASK Options
BII
Option
No.
Data
Rale
7
(MSB)
6
O·
o Kbps
0
0
0
0
0
0
0
0
1
8 K,bps
0
2
3
4
5
16 Kbps
24 Kbps
32 Kbps
40 Kbps
5
3
4
2
0
1
(LSB)
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
Remarks
No data will be sent. A time FILL of eight Is will be sent
provided TSEREN = 1.
Arbitrary-user defined. A 1 in anyone bit poslllOn but only
one 1.
User defined patterns, a 1 In any 2 bit positions but only
two 1s
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
0
1
0
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
1
A total of five Is anywhere as defined by user.
A total of three IS anywhere as defined by user
A total of four Is anywhere as defined by user
6
48 Kbps
0
0
1
1
1
1
1
1
A total of SIX Is anywhere as defined by user.
7
56 Kbps
0
1
1
1
1
1
1
1
Standard rate In Digital Data Service. restricted version of
64 Kbps.
1
1
1
1.
1
1
1
0
A total of seven Is anywhere as defined by user.
S
64 Kbps
1
1
1
1
1
1
1
1
'Special purpose mode, transmitter operates as if at 64 Kbps Including fetching data from shared memory, even though no data IS transmitted
When the FILL/MASK bit becomes a 1 again, the buffered data
bit is transmitted on a first in-first out basis (Figure 7.)
channel will carry 1111 1111 as long as the channel is IDLE. Any
remote receiver will not be able to achieve signaling channel
multiframe alignment if 1111 1111 IS received continuously.
Thus, there IS a one-ta-one correspondence between the
FILL/MASK bit and the T1 or CEPT PCM 30 channel serial data
associated with the FILL/MASK bit position.
RECEIVE CONSIDERATIONS
When the FILL/MASK bit is 0, TSEREN determines what is to
be transmitted on TSER:
Data Bit
FILL/MASK Bit
TSEREN
1
1
X
X
1
0
0
X
X
Minimum Buffer Size
TSER (Output)
The data bit may be the same as, or logical complement (inverted
version), of the actual data.
There IS a minimum number of memory locations that have to
be allocated in each buffer for the R8071 to perform the buffer
maintenance and still effect a smooth transition to the next buffer
without losing data. The minimum buffer allocations for data must
allow SIX data bytes in addition to the seven bytes of descriptors. Command buffers have exactly two bytes and are processed
without regard for the BUFFER SIZE word.
A bit-oriented 64 kbps signaling channel should be programmed
with 1111 1111 as the FILL/MASK. The R8071 will not override
any other user-supplied FILL/MASK pattern even if it is erroneous, i.e., not equal to 1111 1111. An IDLE bit-oriented signaling
Note: The minimum HDLC frame received can have as few as
two bytes of data and the R8071 will still function properly;
however, It is essential that a buffer size of six must be allocated
as a minimum since the received frame size is not known apriori.
o
1
o
1
o
1
High Z
6-120
ISON/OMI link Layer Controller
R8071
SHARED MEMORY ACCESS
At AS falling edge, the memory address on the AO-A15 lines is
valid. Simultaneously, when the memory address changes, the
output SYSACC is asserted provided the system memory is being
addressed. Moreover, the R8071 will selectively tri-state the high
order memory address lines (AB-A15) during the system memory
accesses when specified so by UAEN.
The R8071 accesses shared memory for buffer maintenance,
command data, information and also for channel activation. It
manages the buffer memory for up to 64 channels (32 transmit
and 32 receive).
Following AS, the R8071 asserts the READ or WRITE output
strobe for read or write operation, respectively. The data on the
data bus (DO-D7) is latched by R8071 just prior to the riSing edge
of READ during a read operation. Data placed on the data bus
is written to the memory during the period that WRITE is low.
The T1 or CEPT PCM 30 data throughput requirements demand
that one octet of data be supplied to the transmitter and one octet
of data be taken from the receiver in a single channel period
(8 TCLK periods). The host and the R8071 must work cooperatively to meet the data throughput requirements. The R8071 uses
a memory access scheme that simplifies the system design In
achieving the required data throughput.
Address setup time, address hold time, data setup time, and data
hold time are specified such that a wide variety of off-the-shelf
RAM deVices may be used. The READ output from R8071
may be used as an Output Enable (OE) input to the RAM devices.
Since the R8071 uses its SYSCLK Input to generate the various
strobes for memory access, the access time requirements are
automatically scaled depending on the T1 or CEPT PCM 30
application.
The R8071 processes the memory reqUirements of up to 32 channels in the same order In which they are multiplexed in a T1 or
CEPT PCM 30 carrier system. Typically, during TX channel m
(for example), the R8071 fetches a single data byte from memory
for the transmitter so that it can transmit it over channel m at
the next appropnate T1 or CEPT PCM 30 frame. Similarly, the
last data byte received by channel j IS written to the memory by
the R8071 during the next appropnate receive channel j. Then
it services TX channel (m + 1) and RX channel 0 + 1) and so on.
Once the R8071 makes the first memory access, it assumes that
continued access to the memory IS guaranteed as long as DMND
is active. It no longer waits for one TCLK period before the actual
memory access. At the most, there may be two more memory
accesses. Such a case is illustrated in Figure 20. After completing
the needed memory accesses, the R8071 negates the DMND
output Indicating that it no longer needs access to memory. It
also negates the SYSACC output as long as it does not access
system memory locations.
The R8071 divides a channel period in to two halves, each for
a duration of 4 TCLK periods. Dunng the first half-channel period,
it accesses the shared memory for channel command information, buffer descriptors, and/or transmit buffer data (Including
mode definition data) for a transmit channel. Dunng the second
half-channel period, it accesses the shared memory for channel command information, buffer descnptors (including mode
definition data), and/or received data for a receive channel. Since
the transmit and the receive channel boundaries are generally
unrelated, an elastic buffer is used to synchronize the receive
channel boundary to that of the transmit channel. Hence, no contention exists between a transmit channel and receive channel
for the shared memory.
The mimmum one TCLK latency (two TCLK periods with ATTN
inactiVity) between DMND and the actual memory access is considered to be sufficient for an external arbitration logic to release
the memory bus to the R8071. Failure to do so may cause loss
of data and unpredictable operation. The time between DMND
gOing low and the start of the first memory access by RB071 is
considered to be sufficiently long either for a Single complete
memory bus cycle by the host or for the completion of a pendIng host memory bus cycle. Since the R8071 does not wait for
a memory acknowledgement, DMA-like operation using a single external shared address and a data bus cannot be
guaranteed.
In each half-channel period, under normal Circumstances, the
R8071 accesses shared memory once for data. If descriptor
information is also to be updated, It accesses shared memory
a second time. Additionally, if system memory access is also
required (as determined by assertion of the ATTN input),' it
accesses shared memory a third time. In summary, different
states of buffer processing will cause anywhere from zero to three
accesses to shared memory for an active channel during a halfchannel period.
Examples of the R8071 to shared memory interface waveforms
are shown in Figure 20.
MEMORY ADDRESS EXTENSION
The 16-bit memory address output by the R8071 may be
extended to more than 16 bits by the use of the channel number (CHO-CH4) and RXITX bits. These six bits may be used
directly as higher order address bits for a 22-bit address, or they
can be mapped by an external look-up table to another set of
n bits (where n is specified by the host). Since the channel number and RXlTX are output by the R8071 well In advance of the
16-bit address, address translation time is not of any concern.
At the start of every half-channel period, the R8071 outputs the
binary code for the 5-bit channel number (CHO-CH4) being
served. It also specifies whether It is the receive or transmit channel via the RXlTX output. About one-half TCLK penod later, the
R8071 asserts the Memory Demand (DMND) output. DMND
rising edge informs any external shared memory arbitration logiC
that the R8071 needs unconditional access to the shared memory
within one TCLK period from DMND rising edge. Note that the
R8071 will not wait for a memory acknowledge to start memory
access. Thus there is an implied memory acknowledge after one
TCLK. See Figure 20 for timing. Prior to asserting READ or
WRITE strobes, the R8071 asserts Memory Address Strobe (AS).
Address selection for the system memory locations can be
achieved by the host by using the SYSACC output and the UAEN
input. External hardware can jam any address on the upper eight
bits of the R8071 memory address, I.e., AS-A15, since the R8071
tn-states them (if UAEN IS active dunng SYSACC.)
6-121
II
ISDN/OM I Link Layer Controller
R8071
MEMORY ADDRESS RESTRICTIONS
The R8071 checks the start address of the first buffer of any channel for an Invalid address. It does the above check Immediately
after It reads the 2-byte start address from the system memory,
as part of servicing the ATTN Interrupt from the host If an invalid
start address is detected for any channel, that channel IS forced
inactive automatically.
In addition to capturing the channel number and buffer status,
external hardware can also capture the actual memory address
of the status byte In another FIFO queue. By reading such a
queue, the host system can reallocate the completed buffers In
any way It sees fit and also cross-check against ItS own list of
linked buffer addresses If all the buffer start addresses are
diVisible exactly by eight, they can be derived from the STATUS
byte addresses In the FIFO queue by simply setting the three
LSB addresses to zero
Data Buffer Memory Addresses
DEVICE INITIALIZATION
The R8071 checks the next buffer address for an Invalid address
for all the channels. If It IS an Invalid address, It forces the corresponding channel to an inactive state and also sets the IVBA
status bit. Recovery from an Idle state to an active state IS possible
only if the host system asserts the ATTN Input to the R8071 In
host systems uSing more than 16 bits for shared memory address,
an Invalid address, as Interpreted by the R8071 , refers to all
addresses divIsible exactly by 65,536 or an address of the form
n x 2 16 x (1111 1111 1111 XXXX), where n IS a power of 2 Within
each 64 kbyte address block, only addresses 0001-FFEF (hex)
are valid
Upon reset, all the transmit channels are forced to the Inactive
state All the transmit channels are Initialized to the HDLC INV,
NON-SIG data mode With a FILU MASK byte of eight Os. No data
IS transferred from memory. All the receive channels are forced
to the Idle state They are Initialized to the HDLC data mode With
a FILUMASK byte of eight Os No data IS written to the shared
memory. The Input strap pinS define the TDM format, I e., Tl or
CEPT PCM 30, and also the hyperchannel grouping. The modes
bits are assumed to be (lNV = 1, LOOP = 0, SIG = 0) In addlllOn
to HDLC=l for each channel.
System Memory Address
The Transmit Multlframe Sync (TMAX) pulse IS assumed to be
valid for the purpose of generating an Internal channel number.
The Receive Multlframe Sync (RSYNC) pulse and the RRED
Input are mOnitored by the R8071 to ascertain the receiver
framing synchronization
The R8071 BMM Internal adder calculates the absolute memory
address from the given buffer start address and any offset
needed to locate either the bookkeeping information or the data
byte. The maximum address within a buffer for a given channel
IS the address of the last byte of the buffer Since It IS always
represented by a 16-blt binary number, It is restricted to 65,535
(decimal) In other words, It IS reduced to modulo 65,536. Hence,
the following bound,
16-blt address of the last byte
CHANNEL INITIALIZATION
The host may activate any transmit or receive channel to any
mode, by pOinting It to a command buffer. It does so In a simple
and systematic manner as Illustrated In Figure 21.
16-bit buffer start address
It chooses a starting address for a command buffer and writes
the 2-byte starting address as the data at the system memory
location dedicated to the channel to be Initialized It then prepares a command buffer at the above starting address by specifyIng the deSCriptor Information and the mode of operation. A linked
list of data buffers IS set up by the host following the command
buffer. ThiS completes the preparallOn for activating a channel.
+ 610 (for bookkeeping)
-
12-bit data length or
buffer size
:5 65,535 (decimal) or FFFF
(hexadecimal)
should be strictly adhered to when programming the buffer start
address and the Data Length/Buffer Size; otherwise, the R8071
will access memory locations not Intended for that channel
As the last step, the host writes to Channel ActlvallOn Byte
containing the the channel number, channel direction and the
activation command then asserts the ATTN Input to the R8071
It IS to be emphaSized that the R8071 does check for buffer start
addresses in the range FFFO through FFFF and declares them
as Invalid addresses. For systems uSing more than 65,535 byte
addresses, all shared memory addresses must be Within one
64 kbyte page or bank.
INTERRUPT INDICATION
If ATTN IS asserted, the R8071 first reads the Channel ActlvalIOn Byte. Based on the channel number, it then reads the startIng address of the first buffer from the Channel Buffers POinters,
one byte at a lime It stores the starting buffer address Internally
and acknowledges the task completion by asserting ATACK The
host system must respond to ATACK negating ATTN.
The R8071 asserts the Interrupt Indication (INTR) output anytime
the status of any buffer IS updated (written) by the R8071. See
Figure 20 for timing Illustration. The active period of INTR IS onehalf TCLK period At the rising edge of INTR, the channel number
(including RXlTX) and ItS current buffer status placed on the data
bus are guaranteed to be valid so that they can be captured In
an external FIFO queue. The R8071 does not queue the interrupts and their causes Internally nor does It walt for an Interrupt
acknowledge from the host before removing the interrupting
channel number and ItS buffer status. The R8071 processes a
channel only for a half-channel period and then moves on to the
next channel
The negation of ATTN causes ATACK output to be negated. Thus
the channellnillalizatlon process IS complete. ThiS process can
be repeated for each channel that needs to be Initialized. DUring
each system memory access the R8071 asserts the SYSACC
output. It needs to make three system memory accesses to complete the channel ATTN processing The worst case time delay
from·ATTN assertion to ATACK asserllOn is three Tl or CEPT
PCM 30 channel periods The earliest IS 11/2 channel periods
Since thiS IS guaranteed, the host need not be polling the ATACK
output blindly nor need It service the ATACK as an Interrupt.
Sample channel Initialization sequences are shown In Figures 22
and 23.
6-122
ISDN/OM I Link Layer Controller
R8071
SYSCLK
r------
OMNO
AO-A1S
00-07
--------------~==========}--------------------------------------
----------------~c:========~-----------------------------------
RX/TX ___'--_____________________________--'____.......____......._______________
CHO-CH4
lACTIVATEO BY STATUS WRITE ONLY.
a.
Single Write Memory Access
SYSCLK
OMNO
'---___----'nl-____~
AO-A1S
--------~==~xC==~---------------
u
u
INTRl
00-07
RX/TX
i
--..J
I
L. ___ .J
CHO-CH4
b.
Figure 20.
Double Write Memory Access
RB071 Shared Memory Example Interface Waveforms
6-123
•
ISDN/OM I Link Layer Controller
R8071
SYSCLK
DMND
r -- ---
AS ________________,
AO-MS
--------------<::::::::::)------------------------------------L-.J
GH[J~---------------------
00-07
RX/TX __
~
CHO-CH4 __
_______________________________
~
~
______________________________
c.
____L __ _
~
~~
__
~~
__
~
_ _ _ _ _ _ _ _ _ __ _ _
_______________
Single Read Memory Access
SYSCLK
r
DMND _______...J
I
- ----
L....-_----InL..._ _ _ _....J
AO-A1S
WRITE
00-07
---------------C====::JxC=====}-------------------------
L--..l
------------------------------,L-j
----------------~~=====>----------------------
L-J
INTR'
RXlTX
CHO-CH4 __
~
________________________________- L_____ L_ _ _ _
~
_ _ _ _ _ _ _ _ _ ____
'ACTIVATED BY STATUS WRITE ONLY.
d.
Figure 20.
Read/Write Double Memory Access
R8071 Shared Memory Example Interface Waveforms (Continued)
6-124
R8071
ISON/OMI Link Layer Controller
SYSCLK
OM NO
n . . .__. . .
AS
AO-A1S
'--_--I
-----C==~xC===r---------
READ
u
WRITE
00-07
------~c====r~~~~----------
INTR
RX/TX
CHO-CH4
.-J
i
I
L.. ___ .J
e.
Write/Read Double Memory Access
SYSCLK
n------
OMNO _ _ _-oJ
II
AO-A1S--------c:::::::::)------------------
L-J
00-07 ---------i6HO:ttt<>--------------RXnX_.J-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _-L.._ _
CHO-CH4 _.J-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _-L.._ _
~_~
~_~
_ _ _ _ _ __
_ _ _ _ _ ___
SYSACC
f.
Figure 20.
Single System Read Memory Access
R8071 Shared Memory Example Interface Waveforms (Continued)
6-125
•
ISDN/OM I Link Layer Controller
R8071
SYSCLK
....
OMND _ _ _ _~
I
------
L - - _ - - - I n L . ._ _...J
X
AO-A15
U
L..J
WRITE
00-07
-----------c====~~~~--------------
RX/TX --r----------------------------,----,----~------------CHO-CH4 __
~
________________________________
~
_____L_ _ _ _
~
_ _ _ _ _ _ _ _ _ _ _ _ _ __
SYSACC ________________________-...J
'ACTIVATED BY STATUS WRITE ONLY.
g.
Single Write Memory Access Plus a Single System Read Access
SYSCLK
.... ------
OMND _ _ _ _ _.....
-----------------C====}---~E
RX/TX __
CHO-CH4 __
____________________________________________
~~
__________________________________________
SYSACC ________________________-...J
,
_______________
~
00-07
---------------C====::J
~
AO-A15
~
_______________
'-----....
'ACTIVATED BY STATUS WRITE ONLY.
h. Single Write Memory Access Plus a Double System Read Access
Figure 20.
R8071 Shared Memory Example Interface Waveforms (Continued)
6-126
ISDN/OM I Link Layer Controller
R8071
SYSCLK
DMND _ _ _ _....
~
AO-A15
-----C==::JxC==:xX==::::J----L-.l
READ
WRITE
DO-D7
__~rl~____~rl~____....
u
---------1mo-<===>---1«K:Jm~--L...J
R~X
CHO-CH4
__
~
__________________________________________L -______________
_~~
_________________________________________
SYSACC _________________________________
~
_______________
~
1ACTIVATED BY STATUS WRITE ONLY.
i.
Write/Read Double Memory Access Plus Single System Read Access
Figure 20.
R8071 Shared Memory Example Interface Waveforms (Continued)
ORDER OF DATA
Reception
It'ansmlsslon
The Re071 writes received data bytes In the external shared
memory in the same order in which they are received in time. The
fi rst received byte is written at byte m, the second received at byte
address m + 1, and so on as long as the buffer is not complately
filled or an end-of-frame is not reached. After the end of the frame
or the end of the buffer (whichever occurs first) Is detected, the
Reon writes the next received data byte at the first allocated
address of the next available buffer. The transition to the next buffer
is transparent to the host and maintains the flow olthe actual data.
The R8071 transmits data bytes in the same time sequence as they
are arranged in ascending addresses in the external buffers. The
data at byte address m is transmitted first, the one at address m + 1
is transmitted next, and so on as long as the data bytes are in the
same buffer. After the data in a single buffer is exhausted, the
R8071 starts to transmit the next byte from the next buffer whose
address Is specified in the current buffer. The transition to the next
buffer Is transparent to the host while maintaining the flow of actual
data.
The Reon writes the first received data bit of an octet at the LSB
(~O) position of the external buffer byte; the second received data
bit at the next to LSB position and so on. The last (eighth) received
data bit of an octet is written at the MSB (07) position of the data
byte.
The Reon transmits the LSB (~O) of a data byte first; the next LSB
is transmitted second; the MSB (07) is transmitted last. The only
exception is that the MSB of the HOLC FCS (CRC-CCITT) is transmitted first; the LSB is transmitted last.
6-127
----~-
------~
•
ISON/OMI Link Layer Controller
R8071
SHARED
MEMORY
FIRST ACCESS
CD
ATTN
®
CD
R8071
---,
I
®ATACK
o
CHANNEL ACTIVATION
BYTE FOR
CHANNEL #m
I
I
HOST
SYSTEM
CD
CD
CD
CD
0
LOGIC AND
STORAGE
HOST PREPARES DATA BUFFERS FOR A CHANNEL, ASSERTS ATTN.
CH. #m FIRST
BUFFER START
ADDRESS
..-
R8071 SENSES ATTN, READS CHANNEL NO. IN CHANNEL ACTIVATION BYTE.
R8071 ADDRESSES THE MEMORY LOCATION DEDICATED FOR THE SPECIFIC CHANNEL.
R8071 READS AND STORES THE START ADDRESS OF THE FIRST BUFFER ALLOCATED
FOR THE CHANNEL.
R8071 ACKNOWLEDGES TASK COMPLETION BY ASSERTING ATACK.
Figure 21.
Channel Initialization
6-128
ISDN/OM I Link Layer Controller
R8071
XXOO
SYSTEM
+- 0:
XX80
XX81
TXCHO
+- Addresses XX80 and XX81
XX82
XX83
TXCH 1
XXBE
XXBF
TX CH 31
R8071 Sees ATTN go high.
1: R8071 reads during system access (XXOO)
(reads active transmit channel number).
(and XXB2 through XXBF) are not used in T1 modes.
.:~~===::;------ 2: R8071 reads the first buffer's starting address (Command or
Data), then sets ATACK, and begins processing that buffer.
3: ATACK Is reset by the R8071 after ATTN goes low.
4: R8071 continues processing command or data buffers as
controlled by the status of each.
NEXT
COMMAND
MODES
FILLMASK
NEXT
DATA
LENGTH
MPTY = 0
CF/P = 1
NEXT
DATA
LENGTH
MPTY
0
CF/P = 1
COMMAND BUFFER
DATA BUFFER #1
DATA BUFFER #2
NEXT
BUFFER
SIZE
MPTY = 0
CF/P = 0
NEXT
BUFFER
SIZE
MPTY = 0
CF/P = 0
NEXT
DATA
LENGTH
MPTY = 0
CF/P = 1
DATA BUFFER #3
DATA BUFFER #4
DATA BUFFER #5
Figure 22.
A Typical Linked Buffer Transmit Sequence
6-129
=
•
ISDN/OM I Link Layer Controller
R8071
XXOO
SYSTEM
~
0: R8071 sees ATTN go high.
1: R8071 reads during system access (XXOO)
(reads active receive channel number).
XXCO
XXC1
RXCH 0
~
(Addresses XXC1 and XXF2 through XXFF are not used in T1 modes.)
XXC2
XXC3
RXCH 1
+---------- 2: R8071 reads Command or Data then sets ATACK, and begins
XXFE
XXFF
RXCH 31
processing that buffer.
3: ATACK is reset by the R8071 after ATTN goes low.
4: R8071 continues processing command or data buffers
as controlled by the status of each.
NEXT
COMMAND
MODES
FILLMASK
NEXT
SIZE
LENGTH
MPTY = 1
NEXT
SIZE
LENGTH
MPTY = 1
COMMAND BUFFER
DATA BUFFER #1
DATA BUFFER #2
~--------------------------------------------------------~
Figure 23.
A Typical Linked Buffer Receiver Activity
6-130
ISDN/OM I Link Layer Controller
R8071
SWITCHING CHARACTERISTICS
R8070 INTERFACE-R8071 TRANSMIT FRAME SYNCHRONIZATION TIMING
TCLK
TMAX
(FROM RI07O)
X
TSER
(FROM RI071)
a.
BIT 8, CH 24
7
Transmit Serial Output-Tl Mode, TSEREN
,
TCLK
tMSU
=
~H1
F BIT
1
IMH
TMAX
(FROM RI07O)
X
TSER
(FROM RI071)
b.
BIT 8, CH 24
li"ansmit Serial Output-T1 Mode, TSEREN
,
TCLK
I MSU
)
F BIT
(
BIT 1, CH 1
=0
IMH
~
TMAX
(FROM RI07O)
B_T ~_TS
TSER
(FROM RI071) _______ __ __3_1____
c.
__J)(~_____BI_T_~_TS__3_1____J)(~____B_IT__1,_TS__O_____~
li"ansmlt Serial Output-CEPT PCM 30 Mode, TSEREN
= 1 or 0
Ra071 Transmit Frame Snchronization Waveforms
Ra071 Transmit Frame Synchronization Timing
Symbol
Parameter
Min.
Max.
Units
tMSu
tMH
TMAX Setup time
TMAX Hold time
60
60
-
ns
ns
6-131
•
ISDN/DMI Link Layer Controller
R8071
SWITCHING CHARACTERISTICS (Cont'd.)
R8070 INTERFACE
,
RCLK
tRBU
~HU
,
RSYNC
(FROM R8070)
~
X
RSER
(FROM 8070)
X
FBIT
BIT 1, CH 1
a. Receiver Serial Input-T1 Mode
,
RCLK
~
RSYNC
RSER
t RHU
~
X
b.
X
BIT 1 TSO
X
BIT 2 TSO
Receiver Serial Input-CEPT PCM 30 Mode
R8071 Receive Frame Synchronization Waveforms
R8071 Rescue Frame Synchronization Timing
Symbol
Parameter
Min.
Max.
Unlta
tRBU
tRHU
RSYNC Setup time
RSYNC Hold time
50
50
-
ns
ns
6-132
R8071
ISON/OMI Link Layer Controller
SWITCHING CHARACTERISTICS (Cont'd.)
SHARED MEMORY INTERFACE
1.5
SYSCLK
I ASO
AS
0.4
-+
ADDRESS
tAD
2.4
0.4
lAD
READ
00-07
Read Cycle Waveforms
Read Cycle Timing
Parameter
Max.
Symbol
Min.
Address Strobe Delay
tASo
10
75
ns
Address Delay
tAD
10
90
ns
Address Float Delay
tAF
10
90
ns
Read Enable Delay
tRD
10
75
ns
Read Data Access Time
tRDA
-
Note 1
ns
Read Data Hold Time
tRDH
Note 2
ns
0
Notes:
1. Read Data Access time for shared memory = tsep - 125 ns.
2. Data Drive to Data Bus Float = tscpw - 65 ns
6-133
Units
ISDN/DMI Link Layer Controller
R8071
SWITCHING CHARACTERISTICS (Cont'd.)
SHARED MEMORY INTERFACE (Cont'd.)
SYSCLK
1.5
tAO
ADDRESS
__~2~.4~--+-----~----+-----~~__~_______________
0.4 "F--I----~------I-------~
---.!
t WD
00-07
_ _ _ _ _ F-_ _ _ _ _ _ _ _ _
~D--~-AT-H
_ __
Write Cycle Waveforms
Write Cycle Timing
Parameter
Symbol
Min.
Address Strobe Delay
tASD
10
75
ns
Address Delay
tAD
10
90
ns
Address Float Delay
tAF
10
90
ns
Write Delay
two
10
75
ns
Write Pulse Width
twp
80
-
ns
Interrupt Delay
tiD
10
75
ns
Write Data Delay
tDATD
10
90
ns
WrHe Data Hold Time'
tDmi
10
90
ns
Nota:
1 Data Drive to Data Bus Float time
6-134
Max.
Units
.
ISON/OMI Link Layer Controller
R8071
SWITCHING CHARACTERISTICS (Cont'd.)
LlU INTERFACE
SYSCLK
TCLK
1+-----tTcPW-----t
R8071 Clock Waveforms
R8071 Clock Timing
Parameter
MIn.
Symbol
0
TCLK Delay
IreD
SYSCLK Pulse Widlh
Iscpw
110
TCLK Pulse Width
lrepw
200
SYSCLK Period
Iscp
240
Rise, Fall Time
1,,1,
-
6-135
Max.
Units
50
ns
-
ns
ns
10,000
ns
5
ns
•
ISON/OMI Link Layer Controller
R8071
SWITCHING CHARACTERISTICS (Cont'd.)
LIU INTERFACE (Cont'd.)
TCLK
RCLK
0.8
1 - - - - t RCPW
R8071 TCLK -
Parameter
---~
RCLK Relationship Waveforms
R8071 TCLK -
RCLK Relationship Timing
Symbol
Min.
Max.
Units
Rise, Fall Time
t"tf
-
10
ns
RCLK Pulse Width
tRCPW
190
-
ns
TCLK, RCLK Difference
tTRCO
-
Note 1
ns
Note:
1. RCLK is to be centered around TCLK. The summation of RCLK and TCLK periodic differences over any duration of time must
never exceed 14 TCLK periods.
6-136
R8071
ISON/OMI Link Layer Controller
SWITCHING CHARACTERISTICS (Cont'd.)
CHANNEL ACTIVATION/DEACTIVATION
/I
ATTN
ATACK
Channel Activation/Deactivation Waveforms
Channel Activation/Deactivation Timing
Parameter
Symbol
Min.
Max.
Units
ATTN to ATACK Response Time
t ATNS
20
48
SYSCLKS
ATTN Hold time
tATNH
0
-
ns
ATACK Reset Delay
tATKR
2
4
SYSCLKS
•
6-137
ISDN/OM I Link Layer Controller
R8071
R8071 INPUT AC ELECTRICAL CHARACTERISTICS
Reference Signal
Edge 1
Setup (Min.)
Hold (Min.)
Units
SYSCLK
PE
50
50
ns
RESET
TCLK
NE
60
60
ns
00-07
READ
NE/PE
50
0
ns
TMAX (SIS = I)
TCLK
NE
60
60
ns
TMAX (SIS = 0)
TCLK
PE
60
60
ns
RSER (SIS = I)
RCLK
NE
50
50
ns
RSER (SIS = 0)
RCLK
PE
50
50
ns
RRED (SIS = I)
RCLK
NE
50
50
ns
RRED (SIS = 0)
RCLK
PE
50
50
ns
RSYNC (SIS = I)
RCLK
NE
50
50
ns
RSYNC (SIS = 0)
RCLK
PE
50
50
ns
Signal Name
ATTN
Notes:
1. PE = positive edge; NE = negative edge.
2. All input AC Timing measurements are referenced to the 0.8 and 2.0 Vdc logic levels
R8071 OUTPUT AC ELECTRICAL CHARACTERISTICS
Reference Signal
Edge 1
Max.
DELAY
Min.
HOLD
Units
DMND
SYSCLK
PE
75
10
ns
AS
SYSCLK
PEINE
75
10
ns
AO-A15
SYSCLK
PE
90
10
ns
SYSACC
SYSCLK
PE
75
10
ns
READ
SYSCLK
PE
75
10
ns
WRITE
SYSCLK
PEINE
75
10
ns
00-07
SYSCLK
NE
90
10
ns
INTR
SYSCLK
NE
75
10
ns
CHO-CH4
SYSCLK
PE
140
10
ns
RXITX
SYSCLK
PE
140
10
ns
ATACK
SYSCLK
PE
75
10
ns
TSER
TCLK
NE
75
10
ns
Signal Name
Notes:
1. PE = positive edge; NE = negative edge.
2. All output AC Timing measurements are referenced to the 04 and 24 Vdc logic levels.
6-138
ISON/OMI Link Layer Controller
R8071
ABSOLUTE MAXIMUM RATINGS*
Symbol
Value
Unit
Supply Voltage
Parameter
Vee
-0.3 to 7.0
Vdc
Operating Temperature
TA
Oto+70
·C
Storage Temperature
TSTG
-55 to + 150
• NOTE: Stresses above those listed may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the other sections of this document
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
·C
DC ELECTRICAL CHARACTERISTICS
(Vcc=5 Vdc ±5%, Vss= 0 Vdc, TA = 0 to + 70 o e, unless otherwise noted)
Parameter
Input Low Voltage
Symbol
VIL
Input High Voltage
VIH
Output Low Voltage
VOL
Output High Voltage
CMOS
VOH
Output Low Current
CHO-CH4,Rxnx,TSER
Others
10L
Output High Current
CHO-CH4, RXfTX, TSER
Others
10H
Min
Max
Unit
-0.3
0.8
V
Vee + 0.3
V
20
-
+3.2
+1.6
-200
-100
Input Capacitance
CIN
COUT
Power DIssipation
PWD
V
ILOAD = + 1.6 mA
V
3.5
Output Capacitance (Load)
TSER
All Others
0.4
Test Condition
-
-
ILOAD = + 100 pA
-
mA
VOL = O.4V
pA
VOH = 3.5V
-
5
pF
-
100
50
pF
pF
-
250
mW
•
6-139
ISON/OMI Link Layer Controller
R8071
PACKAGE DIMENSIONS
33-r
B
~?rnmmmmmmmmmmmmmmm~32~-
DIM.
~.~
~----,+ tF, :)~~
T~~
J.+-
~~K1K2
TT
MILUMETERS
MIN. MAX.
INCHES
MIN. MAX.
A
41.10
4161
1.618
1.638
B
17.02
17.23
0.670
0.690
C
3.56
4.58
0.140
0.180
0
0.48
0.58
0018
0.022
El
E2
J
19.05 Bse
2350 Bse
127 Bse
0.18
0.33
0.750
0.925
0.050
0.007
Bse
BSC
Bse
0.013
Kl
292
3.18
0.115
0.125
K2
4.83
5.34
0.190
0210
G
64-Pin Plastic Quad In-Llne Package (QUIP)
DIM.
•..n. n. nJ. n. ~.". ~ J.". ~. ~. n. n.". ~
D
0,
D
»T
Q
B
.. ~
~:~
W
r! -+-J~='T
K1K2
tT
64-Pm Cerpac Quad In-Line Package (QUIP)
6-140
MILUMETERS
MIN. MAX.
INCHES
MIN. MAX.
A
4077
4128
1605
1625
B
1676
1727
0.660
0.680
e
3.56
4.58
0.140
0.180
0
0.48
0.56
0.018
0.022
El
E2
19.05 Bse
23.50 Bse
G
J
127 Bse
020
030
0.050 Bse
0.008 0012
K1
292
3.18
0.115
0.125
K2
4.83
534
0.190
0210
0.750 Bse
0.925 Bse
R8071
ISON/OMI Link Layer Controller
PACKAGE DIMENSIONS
DIM.
D D1 D2
~43
TOP VIEW
4.14
4.39
0163
0.173
A1
1.37
147
0.054
0.058
A2
2.31
2.46
0.091
0.097
0.457lYP
25.02 2527
0.018lYP
0.985 0.995
01
24.00
24.26
0.945
0.955
D2
20.19
20.45
0.795
0805
D3
23.24
23.50
0.915 0925
0.050 sse
0.010lYP
O.045lYP
45"lYP
O.035lYP
0.010lYP
0
SIDE VIEW
e
h
J
a
R
R1
CHAM.
hX4SDEG
3 PlCS
INCHES
MIN. MAX.
A
b
lID"""""",,,,,,8
MILLIMETERS
MIN. MAX.
127 sse
0254lYP
1.15lYP
45"lYP
O.89lYP
0.254lYP
EJECTOR MARKS
4 PlCS BOTTON
ONlY [TYP.I
SECTION A-A
BOTTOM VIEW
6S-Pin Plastic Leaded Chip Carrier (PLCC)
•
6-141
ISDN/DMI Link Layer Controller
R8071
PACKAGE DIMENSIONS
DIM.
1.83
0.072
0.088
A1
A2
0
REF
REF
25.65
24.51
0.095
0.035
0.970
0.940
REF
REF
1.010
01
2.41
0.89
24.64
23.88
D2
23.11
24.13
0.910
0.950
03
20.20
20.45
0.795 0.805
h
J
-Ij-b
•
rA1~
I;-II--bl D3
I R .2
6S-Pln Ceramic Leaded Chip Carrier (CLCC)
6-142
2.24
INCHES
MIN. MAX.
A
e
.L
MILLIMETERS
MIN. MAX.
1.27TYP
1.02 REF
0.51 REF
0.965
0.050TYP
0.010TYP
0.020 REF
R8071
ISON/OMI Link Layer Controller
PACKAGE DIMENSIONS
I
b
~----------Dl --------------~
I •
11109
4
~~
INDEX
MARK TO A2 PIN
CONNECTED
654321
$-$-$-$~$-$~' £)
Jy-t~$-$-$-~l-$
C
G
~- ;
.0=$-
EXTRA
PIN../
~
4J-461-$
dJ-E&
1
4-61
61-$
+
4-9
4··4
4-4
$J>-$1
H
l
41-1&
-
DIM.
MILLIMETERS
MIN. MAX.
INCHES
MIN. MAX.
A
1.70
2.11
0.067
Al
4.45
4.70
0.175
0.185
A2
1.19
1.35
0.047
0.053
MJ
0.20 REF
0.41
0.51
0.016
b
bl
0.083
0.008 REF
0.020
1.19
1.35
0.047
0.053
0
27.58
28.19
1.086
1.110
01
25.15
25.65
0.990
1.010
e
2.41
2.67
0.095
0.105
h
0.51 REF
0.020 REF
-r--@-ED-$-$-EB-$-$-$-$-$
EB-ED-9-EB-94-94-4J.
I.
.1
ICI INDEX MARK
•
CHAM. H • 45 DEG. 4 PlCS
68-1'In Grid Array (PGA)
6-143
8075
'1'
R8075 CRC-4 Encoder/Decoder
Rockwell
INTRODUCTION
FEATURES
CRC-4 transmit and receive as per CCITT
Recommendation G.704
The Rockwell R8075 CRC-4 Encoder/Decoder is a support device to the R8070/R8070A T-1/CEPT PCM
Transceiver and the R8069 Line Interface Unit. Used with
the R8070 and the Ra069, the R8075 implements transmit
and receive functions in accordance with CCITT Recommendation G.704 for PCM30 using CRC-4. Operation of
the R8075 is entirely transparent other than error detection/reporting and handling of the Sppre Bits. The R8075
can be set in either enable or disable mode, for systems
which handle both data encoded with CRC-4 and without
CRC-4.
Insertion and extraction of Spare Bits (SP1 and SP2)
Independent error detection and reporting of CRC-4
and multiframe alignment errors
CRC-4 enable/disable capability
Enhanced HDB3 encode/decode section, includes
reporting of bipolar violations
Read/Write access to International Bits in CRC-4
disable mode (through R8070)
Transmit functions compute the CRC-4 polynomial and insert the proper alignment timing and Spare Bits (SP1,
SP2) into the transmit data stream. HDB3 encoding is also
handled by the R8075.
Supports 256N and 256S modes
Receive functions are independent error detection of
CRC-4 and multiframe alignment, extraction of the spare
bits, and HDB3 decoding (including reporting of bipolar
violations).
Package Options
Bit, Channel and Frame timing available to system
Low power CMOS technology
Operates from single +5V supply
24-pin plastic DIP
24-pin CERDIP
28-pin PLCC
The Bit, Channel and Frame timing signals are available
to the system for both the transmit and receive sections.
The R8075 can support ISDN applications using the
R8070 256N mode and PCM30 signalling modes using the
256S mode.
=
c
ORDERING INFORMATION
Part Number:
R807S
Temperature
Blank = O·C to 70·C
E = -40·C to +8S·C
Package
P = 24-pin DI P
S = 24-pin CERDIP
J = 28-pin PLCC
Document No. 29300N343
Data Sheet
(preliminary)
6-144
Order No. 343
October 1988
CRC-4 Encoder/Decoder
R8075
2 shows the signals grouped by interface. The R8075 interface signals are listed by pin number in Figure 3 and
shown graphically in Figure 4.
INTERFACE SIGNALS DESCRIPTION
The R8075 interfaces to the R8070 T1/CEPT PCM
Transceiver, the R8069 Line Interface Unit, and to the system. The functional interface is shown in Figure 1. Figure
RCLK
RPOS
RNEG
RPOS
h
RX
RNRZ
RNEG
RCLK
RSP1
RSVNC
RX
RX
RSP2
RMASVN
CRCERR
1---
R8070 -
MFAERR
LOOP
--
CRCEN
r -
BPV
-
R8069
-
R8075
TMAX
TMASVN
TNRZ
TSP1
TX
TSP2
TPOS
TX
TCLK
TX
TNEG
TNRZO
TCLK
o
SYSTEM INPUTS OR OUTPUTS
Figure 1. R8075 Functional Interface
RPOS
RNEG
RSP1
RSP2
TPOS
TNEG
RMASYN
TO
SYSTEM
CRCERR
R8069
LINE
INTERFACE
UNIT
MFAERR
BPV
TMASYN
R8075
TCLK
RCLK
TNRZO
RSYNC
AW"{
SYSTEM
LOOP
TMAX
CRCEN
TNRZ
TSP1
RNRZ
TSP2
Figure 2. R8075 Interface Signals
6-145
t~
T1/CEPT
PCM
TRANSCEIVER
•
CRC-4 Encoder/Decoder
R8075
Table 1. R8075 Pin Assignments
Symbol
LOOP
TNEG
TPOS
N.C.
TNRZ
TNRZO
BPV
VDD
CRCERR
RSP2
N.C.
RSYNC
CRCEN
RNRZ
RCLK
RPOS
RNEG
N.C.
MFAERR
TSP1
TSP2
VSS
TCLK
TMAX
N.C.
RSP1
RMASYN
TMASYN
24-Pin
DIP
28-Pin
PLCC
1
2
3
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
17
20
18
19
22
4
5
6
7
8
9
10
11
12
13
14
15
-
20
21
22
23
24
Signal Name
21
23
24
25
26
27
28
I
0
0
I
0
0
I
I
I
I
I
0
RSP1
TNRZ
TMAX
I
I
System
System
System
Ground
R8069
R8070
0
0
0
System
System
System
I
I
-
RMASVN
TPOS
R8070
System
R8070
R8069
R8069
R8069
0
0:
owO
TNEG
R8070
System
System
Power Supply
System
System
-
Oc.zo
Z t- t- ....I
TMASVN
System
R8069
R8069
0
0
",,,,0.
LOOP
Source/ Destination
I/O
Loopback Mode
Transmit Unipolar Negative
Transmit Unipolar Positive
No Connect
Transmit NRZ Data (IN)
Transmit NRZ Data (OUT)
Bipolar Violation
+5VDCPower
CRC-4 Error
Receive Spare Bit 2
No Connect
Receive Sync
CRC-4 Enable
Receive NRZ Data
Recovered (Receive) Clock
Receive Unipolar Positive
Receive Unipolar Negative
No Connect
Multiframe Alignment Error
Transmit Spare Bit 1
Transmit Spare Bit 2
Ground
Transmit Clock
Transmit Maximum
No Connect
Receive Spare Bit 2
Receive MF Alignment Sync
Transmit MF Alignment Sync
~ M N
....
•
TNRZ
'"a:
re
~
~
25
NC
PIN 1
2.
TMAX
INDICATOR
23
TCLK
TNRZO
TCLK
TNRZO
BPV
Vss
TSP2
BPV
Voo
22
Vss
TSP1
CRCERR
21
TSP2
Voo
CRCERR
RSP2
MFAERR
RSVNC
RNEG
CRCEN
RPOS
RNRZ
RCLK
RSP2
10
NC
11
co
................ ,... ........
N
M
'Of
It)
CD
,...
OZN¥CI)(!liO
w II: ...J 0 W Z
z
> U Z 0 a. z
a:: II: II: a: II:
a: 0
U')
R8075P AND R8075S
R8075J
Figure 3. R8075 Pin Assignments
6-146
20
T$P1
19
MFAERR
R8075
CRC-4 Encoder/Decoder
Table 2. R8075 Interface Signal Definitions
DIP
Mnemonic Pin No.
PLCC
PinNa.
Name/Descrlptlon
INPUTS FROM R8069 (LINE INTERFACE UNI11
RCLK
13
15
Recovered (Receive) Clock. From R8069 Output Pin 27. RCLK is the recovered clock output
which is locked to the frequency and phase of the Incoming data. RPOS and RNEG are clocked out of the RB069 at the falling edge of RCLK in the elastic store bypass mode (CB high). This
signal is also input to the RB070 as the receiver clock input, pin 56 of the QUI P (pin 59 of the
PLCC).
TCLK
20
23
Transmit Clock. From RB069 Output Pin 2B. Transmitter clock output which is either the
smoothed clock provided through EXCLK (EXternal CLocK Reference, RB069 pin 3) or the
smoothed clock extracted from the input data. The receive data is also clocked out on the falling
edge of TCLK, except in elastic store bypass mode (CB high). This signal is also input to the
R8070 as the transmitter clock input, pin 9 (QUIP) ! pin 10 (PLCC).
RPOS
RNEG
14
15
16
17
Receive Unipolar Positive, Negative. From RB069 Output Pins 16, 17. RPOS and RNEG are
the outputs of the received data recovered from RXINP and RXINN AMI line pulses. RPOS and
RNEG have TTL levels and are in NRZ format. These are directly connected to the ROO75. RPOS
and RNEG are clocked out of the ROO69 althe falling edge of RCLK (elastic store bypass mode
or TCLK in (elastic store enable mode), and clocked into the RB075 at the rising edge of RCLK.
INPUTS FROM R8070 (pCM30 TRANCEIVER)
RSYNC
10
12
Receive Sync. From RB070 Output Pin 37 (QUIP)!Pin 39 (PLCC). While the receiver is
synchronized, RSYNC is high during the first bH of each multiframe.
TMAX
21
24
Transmit Maximum. From RB070 Output Pin 10 (QUIP)/Pin 11 (PLCC). TMAX is high for one
btt time per muttiframe coincident with the sampling of the next to last serial bit of a multiframe.
TNRZ
4
5
Transmit NRZ Data. From RB070 Output Pin 19 (QUIP)!Pin 20 (PLCC). NRZ (Non-Return-toZero) output for transmitted data. This output is unaffected by LOOP or by HDB3 zero-suppression coding. There is an B-bH throughput delay between the TSER input and the TNRZ output.
INPUTS FROM THE SYSTEM
CRCEN
11
13
CRC-4 Enable. Control Input which enables the R8075 when CRCEN is high. When CRCEN is
low, the RB075 is disabled, providing full transparent operation; in this mode, the user has control of the international bits through the nBITS. The RB075 receiver functions always operate;
only the transmH functions are disabled when CRCEN is low.
LOOP
1
1
Loopback Mode. Control input placing the RB070 plus RB075 in loopback mode. In this mode,
TPOS and TNEG are routed internally to RPOS, RNEG (respectively). This function is identical
to the equivalent function of the RB070. It replaces the RB070 loopback function. CRCEN does
not affect this function.
TSP1
TSP2
17
1B
20
21
Transmit Spare Bits 1, 2. Input to RB075 which allows insertion of the spare international Ms.
When the RB075 is enabled, the user may update the TSP1, TSP2 inputs at the occurrence of
TMASYN (RB075 output). These bits are reserved for future international applications, and for
now, they should be fixed at 1 on digital paths crossing international borders. If CRCEN is low
(R8075 disabled), the user may access the international bit through the IA pin (TIBIl) on the
RB070, pin 5 (QUIP and PLCC).
OUTPUTS TO R8069 (UNE INTERFACE UNIT)
TPOS
TNEG
3
2
3
2
Transmit Unipolar Positive, Unipolar Negative R8069lnput Pins 13,14. TPOS and TNEG
are the 'unipolar paired' Input for transmitted data. They must have TTL levels and be In NRZ
format. These outputs from the RB075 replace those which would ordinarily come from the
RB070. They are clocked in at the falling edge of TCLK. The state TPOS, TNEG 1 Is not valid,
all other combinations are valid. The RB075 never generates the invalid combination.
=
6-147
•
CRC-4 Encoder/Decoder
R8075
Table 2. R8075 Interface Signal Definitions (Cont'd)
DIP
Mnemonic Pin No.
PLCC
Pin No.
Name/Description
OUTPUTS TO R8070 (PCM30 TRANSCEIVER)
RNRZ
12
14
Receive NRZ Data. R8070 Input Pins 54, 55 (QUIP) / pins 57,58 (PLCC) This lead is connected
to both the RNEG and RPOS pins of the R8070. It must remain stable for 60 ns before and after
the rising edge of RCLK. When connected in this manner, the HDB3 encoder and decoder along
wnh the Bipolar Violation Detector in the R8070 are disabled. These functions are supplied by
the R8075.
OUTPUTS TO THE SYSTEM
CRCERR
8
9
CRC-4 Error. At the end of every SMF (sub-multiframe, 8 frames each), the current frame CRC
resuK is clocked into a temporary holding register. During the following SMF, the incoming CRC
bns on RSER are compared with the contents of the holding register. If a mismatch occurs, the
CRC-4 error signal, CRCERR, is generated. This condition can result from a loss of frame alignment or by an incidental data error. This signal is valid after the falling edge of the second RCLK
in the SMF and remains valid for the entire SMF, resetting at the end of the SMF.
MFAERR
16
19
Multiframe Alignment Error. The Multiframe Alignment Error signal is generated when there is
a miss in the CRC-4 alignment bits (sequence of ... 001011 ... ). It indicates each instance of multiframe alignment and is valid during each MF. It is reset when the CRC-4 alignment is regained.
This signal can be used by the system to improve the frame alarm handling.
TNRZO
5
6
Transmit NRZ Data. Serial transmit NRZ data. Derived by the R8075 (from the TNRZ input to
the R8075 from the R8070, n is regenerated, aligned with the timebase of the TPOS/TNEG outputs of the R8075.
RMASYN
23
27
CRC-4 Receive Multiframe Alignment Sync. Derived signal generated by the R8075 indicating the beginning of the received CRC-4 multiframe. It is a positive pulse of one RCLK in duration.
TMASYN
24
28
CRC-4 Transmit Multiframe Alignment Sync. This signal indicates the beginning of the transmitted CRC-4 multiframe. It is a positive pulse of one TCLK period in duration.
BPV
6
7
Bipolar Violation. This signat indicates that a Bipolar Violation has occurred. It replaces the
equivalent signal RVLL from the R8070, which indicates a Bipolar Violation.
RSPI
RSP2
22
9
26
10
Receive Spare International Bits. The receive logic extracts these spare international bits and
makes them available to the system at the beginning of each multiframe (RMASYN).
POWER AND GROUND
+ 5V DC power.
VDD'
7
8
Power.
Vss
19
22
Ground. Power and signal ground.
NC
4, 11 No Connect. These are pins on the PLCC which are not to be connected.
18,25
6-148
CRC-4 Encoder/Decoder
R8075
through the R8075. In this condition, the CRC-4 is not implemented.
FUNCTIONAL DESCRIPTION
The R8075 is used with the R8070 Transceiver and the
R8069 Une Interface Unit to provide CRC-4 capability for
PCM30 systems. There are two basic sections to the
R8075: the Transmit section and the Receive section.
The output of the Transmit Logic section to the system is
TNRZO, the Transmit NRZ Data which has been CRC-4
encoded and has Spare Bits inserted at the proper time (if
CRCEN is HIGH). This is a regenerated signal derived
from the TNRZ signal from the R8070, which is unchanged
if CRCEN is LOW. This Signal, regardless of whether the
R8075 is enabled or disabled is used to replace the R8070
TNRZ signal as an output to the system. TNRZO also is
an input to the HDB3 Encoder, which generates the Transmit Bipolar Data, TPOS and TNEG.
Signals connected to either the R8069 or R8070 are
described in the pin definitions (Table 2). For more information, please refer to the functional and interface
desCriptions of the data sheets for the R8069 and R8070.
TRANSMIT SECTION
The transmit section computes the CRC-4 polynomial, inserts alignment timing signals and spare bits into the transmit data stream, and encodes the bipolar transmit data
using HDB3.
CRC-4 ENCODER
This section calculates the CRC-4 polynomial and
provides the CRC-4 bits for insertion into the transmitted
bit stream. This insertion is performed at the proper time
by the Transmit Logic (see above). The CRC-4 Encoder
may be disabled for transparent operation without CRC-4
computation by CRCEN set LOW.
The six R8075 transmit section inputs are from the system
(TSP1, TSP2, CRCEN), from the R8069 (TCLK), and from
the R8070 (TNRZ). The four R8075 transmit section outputs go to the system (TNRZO and TMASYN) and to the
R8069 (TPOS and TNEG).
The data inputs to the CRC-4 Encoder section is the TNRZ
(Non Return-ta-Zero) output for transmitted data from the
R8070. The R8069 provides TCLK (Transmit Clock) to the
CRC-4 Encoder section as a timing input. Control and
timing inputs to the CRC-4 Encoder are also provided by
the Transmit Bit/Frame/ Multiframe Control (Transmit
Timing ControO to determine the proper insertion points for
the CRC-4 bits if CRCEN is HIGH. This information is
generated using TMAX (from R8070) to derive multiframe
timing and CRCEN (from system) to decide whether to
compute CRC-4.
The R8075 transmit section is divided into four blocks:
1. Transmit Logic
2. CRC-4 Encoder
3. HDB3 Encoder
4. Transmit Bit/Frame/Multiframe Control
(Transmit Timing ControO
TRANSMIT LOGIC
The Transmit Logic section provides the TNRZO (Transmit NRZ Data) output to the system. This signal has the
CRC-4 bits and the Spare Bits inserted at the proper time,
as appropriate.
The output of the CRC-4 Encoder section goes through a
holding register into the Transmit Logic for insertion of the
CRC-4 bits (if CRCEN is HIGH) into the Transmit bit
stream.
Data inputs to the Transmit Logic section are the NRZ
(Non Return-to-Zero) output for transmitted data from the
R8070 (TNRZ) and the Transmit Spare Bits from the system (TSP1, TSP2). When the CRC-4 encoder is enabled
(CRCEN
HIGH) the CRC-4 Encoder section provides
CRC-4 data to the Transmit Logic section for insertion into
the transmitted bit stream. When CRCEN LOW, CRC-4
is not being implemented, and access to the international
bit for each frame is provided through the R8070!70A. In
this case, the R8075 passes the international bit
transparently.
HDB3 ENCODER
This section takes the Transmit NRZ data provided by the
Transmit Logic and provides HDB3 encoding. The resulting output is the two unipolar signals TPOS and TNEG
which go to the R8069 for transmission onto the PCM-30
line.
=
=
Data input to the HDB3 Encoder is the TNRZO output of
the Transmit Logic section of the R8075. This signal already has CRC-4 and Spare Bits inserted as appropriate.
The TNRZO data is converted to a set of bipolar signals
(TPOS, TNEG) using HDB3 encoding for bipolar PCM-30
data. The TCLK input to the HDB3 Encoder comes directly from the R8069.
Control and timing inputs to the Transmit Logic are
provided by the Transmit Bit/ Frame/Multiframe Control
(Transmit Timing ControQ to determine the proper insertion points for the CRC-4 bits if CRCEN is HIGH. The
Transmit Timing Control also properly times insertion of
the Spare Bits. If CRCEN is LOW, there will be no insertion of CRC-4 bits into the transmitted bit stream, and the
Spare Bits are accessed through the R8070 instead of
The output of the HDB3 Encoder section is the set of
Unipolar Transmit Signals, TPOS and TNEG. These signals go directly to the R8069 for transmission onto the
6-149
II
CRC-4 Encoder/Decoder
R8075
TSP1
TRANSMIT
LOGIC
TSP2
1 - - -.....- - - - . , . . - - - - - - f J
TNRZO
TNRZ
TPOS
CRC-4
ENCODER
TNEG
:.:
TCLK
CRCEN
TMAX
I~
TRANSMIT BITIFRAMEIMULTIFRAME CONTROL
(TRANSMIT TIMING CONTROL)
TMASYN
TRANSMIT
RECEIVE
RCLK
Ul
....2
LOOP
51
....z
RPOS
HDB3
DECODER
RNRZ
BPV
RSYNC
RECEIVE BITIFRAMEIMULTIFRAME CONTROL
(RECEIVE TIMING CONTROL)
RSP1
RSP2
RMASYN
ALIGNMENT AND
ERROR CONTROL
MFAERR
CRCERR
Figure 4. R8075 Functional Block Diagram
6-150
RNEG
CRC-4 Encoder/Decoder
R8075
\
PCM-30 line. These signals also are provided to the HOB3
decoder section.
The seven outputs from the R8075 receive section are:
RNRZ (receive NRZ data) to the R8070, and the R8075
outputs to the system. These are: CRCERR (CRC-4
Error), MFAERR (Multiframe Alignment Error), RMASYN
(Receive Multiframe Alignment Sync), BPV (Bipolar Violation), RSP1 and RSP2 (Receive Spare Bits).
Transmit Blt/Frame/Multlframe Control (Transmit
Timing Control)
Transmit timing is provided by this section to properly
handle insertion of the CRC-4 bits and the Spare Bits into
the outgoing transmit bit stream. This section provides
timing and control to the CRC-4 Encoder and Transmit
Logic sections. It also provides the Transmit Multiframe
Alignment Sync signal to the system, so the system can
align properly on multiframe boundaries.
The receive section has the following functional blocks:
1. Internal RCLK Regenerator
2. HOB3 Decoder
3. CRC-4 Decoder
4. Alignment and Error Control
5. Receive Bit/Frame/Multiframe Control
(Receive Timing Control)
Inputs to this section are TCLK (from R8069), TMAX (from
R8070) and CRCEN (from system). If CRCEN is high, the
control is provided to the Transmit Logic to implant the
CRC-4 and Spare Bits into the transmit bit stream. TCLK
is used to derive the bit timing; TMAX is used to derive the
frame and multiframe timing.
Internal RCLK Generator
This section takes the RLCK and TCLK from the R8069,
along with the LOOP control from the system and
produces the internal RCLK timing. This RCLK provides
master bit timing for the other blocks of the receive section
of the R8075.
The CRC-4 bits are inserted in the even frames, in the bit
1 position of these frames. There are four CRC-4 bits in
each 8-frame Sub-MultiFrame (SMF). In odd frames, bit 1
of the first six frames of each 16-frame MultiFrame (MF)
c~ntains the CRC multiframe alignment signal (001011).
Bit 1 of the last two odd frames of the multiframe (frame
13, 15) contain the Spare Bits. Access to the International
Bit (bit 1 of each frame) is provided through the R8070
when the R8075 is in CRC-4 disable mode.
HDB3 Decoder
This section takes the RPOS and RNEG from the R8069
and generates the RNRZ output to the R8070 and identifies bipolar violations (BPV) for output to the system.
Inputs to this section are the RPOS and RNEG (from
R8069), TPOS and TNEG (from R8075 HOB3 encoder
blOCk), the LOOP control (from system), and the internal
RCLK (from internal RCLK). Using the LOOP and
TPOS/TNEG Signals, if the loopback mode is enabled
(LOOP = HIGH), the TPOS and TNEG signals generated
in the R8075 HOB3 encoder are routed to the
RPOSIRNEG inputs of the HOB3 decoder. This function is
identical to and replaces the equivalent R8070 function.
Outputs from this section are the timing and controls
described above, and the Transmit Multiframe Alignment
Sync (TMASYN) signal. TMASYN is an output to the system which indicates the beginning of the transmitted CRC4 multiframe. It is a positive pulse of one TCLK period in
duration.
RECEIVE SECTION
HDB3 Decoder (continued)
The receive section provides independent error detection/reporting of the CRC-4 and Multiframe Alignment errors, extraction of the Spare Bits, and HOB3 decoding with
reporting of bipolar violations. The R8075 receive section
also provides RNRZ (Receive NRZ Data) to the R8070,
connected to the R8070 RPOS, RNEG inputs. This connection will bypass the HOB3 encoder and decoder sections of the R8070, along with the R8070 bipolar violations
detector. These functions are supplied by the Transmit
and Receive sections of the R8075.
Outputs from this section are RNRZ (to the R8070) and
BPV (to system). The RNRZ is generated according to the
HOB3 format, and sent to the R8070 RPOS/RNEG inputs,
bypassing the R8070's HOB3 encode and decode functions. According to the HOB3 algorithm, bipolar violations
are detected and reported through the BPV (system output). After HOB3 decoding of the receive data, it is also
passed to the CRC-4 Decoder and the Alignment/Error
Control blocks. Note that tying RPOS and RNEG together
will bypass the HDB3 decode section. This function is
identical in the R8070 and R8075, bypassing the respective HDB3 decode logic in each device used in this manner.
The four inputs to the R8075 receive section are: RPOS
and RNEG (unipolar receive data) from the R8069,
RSYNC (receive sync) from the R8070, and LOOP (Loopback Mode) from the system.
6-151
•
CRC-4 Encoder/Decoder
R8075
While the CRCERR and MFAERR are closely related.
they are independently generated. CRCERR is generated
upon a mismatch between the il)coming CRe bits from
RSER and the previous SMF's CRC result frO!11 the previous SMF. found in the holding register. This can occur
due to an incide~al data error or by a loss of frame alignment. This signal is valid for the entire SMF. resetting at
the. end of each SMF. MFAERR is generated when there
is a miss in the CRC·4 alignment bits. indicating each instance of multiframe alignment error. It Is valid during each
MF. and is reset when the.CRC-4 alignment is regained.
This signal is useful to the system for implementing alarm
handling.
CRC"" Decoder
The RNAl output of the HDB3 decoder section. the internal RClI<. and the RSYNC timing are inputs to the CRC4 decoder. At the end of every SMF. the current frame
CRC-4 result computed by the bRC-4. decoder block is
clocked into a temporary holding register. During the following SMF. the incoming CRC-4 bits on RSER are compared with the contents of the holding register. If a
mismatch occurs. the CRC-4 error signal (CRCERR) is
generated in the A1ignment/Error control block. Timing is
generated by the receive bit/frame/MF control block.
A1lgnmentJError Control
AIIgnment/Error Control (continued)
This block generates the receive multiframe alignment
sync signal output to the system (RMASYN). outputs the
Receive Spare Bits (RSP1. RSP2). and generates the
error signals MFAERR (Multiframe Alignment Error) and
CRCERR (CRC-4 error) output to the system.
RMASYN is derived from the RCLK It is a positive pulse
of one RClI< period in length. and indicates the beginning
of the received CRC-4 multiframe. This section also extracts the Spare Bits (RSP1 and RSP2). making them
available to the system at the beginning of each multiframe
(at RMASYN).
Handling of the errors is a system function to be done in
accordance with CCITT Standard G70X and Recommendation 1.431.
Receive Blt/Frarne/MF Control (Recelve'Timlng
Control)
.
Inputs to the Alignment/Error Control block are the internally generated RCLI<, the RNRZ data from the HDB3
decoder block. the contents of the CRC-4 holding register.
and timing signals from the Receive Bit/Frame/MF control
block.
This section takes RSYNC from the R8070. the internally .
generated RCLK. and a sync valid signal generated by the
Alignment/Error control block to generate timing for the
CRC-4 Decoder and the bit timing for the Alignment/Error
control blocks. This block generates internal timing. It has
no off-chip outputs.
6-152
:xl
~
_ F R A M E 15
I-------FRAME 0
•
TLCK
TMAX
."
.
~
r----l~------------------------------
c
CD
PI
TPOS
::D
g
~
(11
Co)
.....
(/I
.
TNEG
-4
DO
~
IIJ
3
;:;:
:!
3
5'
CI2
TMASYN
----~!I~-------------------------------_
TSP1. TSP2
I V A : INSERTION OF TSP1. TSP2 BITS
""7%0"""~r7~'"T~""'~>'""7~"""~r7~
/kH~ f o h T 9 { O } H 1 N H I ( S / / / / / / / / / / / / / / / / //// / ,
CRCEN
(HIGH)
o:xl
~
TNRZ
m
::J
TNRZO
(')
SPARE
BIT
OR
CAe BIT
OR
CAe ALIGNMENT BIT
o
Q.
CI)
a
~
o
•
..
Q.
CI)
:xl
~
.....
U1
.
FRAME 15
.I~
FRAMEO----------------------------------------------------------------------~
RCLK
r---lL-_____________________________________________________________
MfflC
RPOS. RNEG J'------..J'L---J
"II
aII:
RNHZ
iiJ
s»
~
~
I
ii
tS
BPV .J'------..J'LCRCEN
~
R~YN
RSP1.RSP2
r--l~
_________________________________________________________________
?W/$/W~~$/Wfi0/ff//dffffi'ffi7/////ff&
YALID
CRCERR
~D~LY) W$,.$/
~
r-
- - - - - - - - - -...'
X
11F CAe ERROR; VALID FOR ENTIRE SMF; RESET IIr END OFSMF
n
:xl
~
SET ON
ClDD FRAMES ONLY
IF AN AUGNMENT ERROR
OCCUM.
"
------- --"
~\.-----------
RESET WHEN CfIC.4 ALIGNMENT
IS REGAINED.
m
::::J
()
o
Q.
CD
%
~
o
Q.
...CD
:D
~
Cit
TCLK
fl
TNRZ
Cil
~
0
~
UI
UI
CRCEN--.l
::a
0
•
TNRZO
0
5.
5.
"0
::!
3
S-
INVALID
CRC-4 Brr.;
I..
•
1 MILLISECOND
VALID
CRC-4 BITS
•
1
ID
MINIMUM nME REQUIRED FOR R8075
TO OUTPUT VALID CRC-4 BITS
o
:D
~
m
::J
o
o
Do
CD
~o
o
..
Do
CD
II
CRC-4 Encoder/Decoder
R8075
I~
FRAME NO.
~I~
eRe' UIIITII'"RAME M
I4
6
1 5
I7
1 8 1 9 1 10
I 11
112
1 13
eRe
MULTIFRAME _
M + 1
14 115 1 0
1
1
2 1 3 1
Figure S. Transmit CRC Multiframe • RS070 Mode 2565
I~
FRAME NO.
-I-
eRe MULTI FRAME M
6
1 7 1 8 1 9
1 10 1 11 1 12 1 13 1 14 1 15 1 0 1 1
Figure 9. Receive CRC Multiframe • R8070 Mode 2565
6-156
eRe
MULTIFRAME _
M + 1
2 1 3
1
CRC·4 Encoder/Decoder
R8075
r
- f - - - - - - - - - - C R C MULTIFRAME M
..
----------,l.~I -MUL;.~~AME
M + 1
Figure 10. Transmit CRC Multiframe - R8070 Mode 256N
I~
FRAME NO.
CRC MULTI FRAME M
0
I
1
2
I
3
I
4
I
5
6
I
7
I
8
I
9
CRC
MULTIFRAME _
M + 1
~I"
I 10 I 11 I 12 I 13 I 14 I 15 I
0
I
1
2
I
3
I
II
Figure 11. Receive CRC Multlframe - R8070 Mode 256N
6-157
CRC-4 Encoder/Decoder
R8075
R8075 Timing Diagram
RCLK,
TCLK
ALL
OUTPUTS
RCLK,
TCLK
ALL
OUTPUTS
Figure 12. Input Timing
Figure 13. Output Timing
Table 3. Input and Output Timing
Parameter
Symbol
Clock Pulse Width High, Low tPWH, tPWl
Input Setup Time
ts
Input Hold Time
tH
Output Delay Time
too
6-158
Min.
Typ.
244
-
60
60
-
Max.
-
-
60
Units
ns
ns
ns
ns
CRC-4 Encoder/Decoder
R8075
*NOTE: Stresses above those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the other sections of this document is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
ABSOLUTE MAXIMUM RATINGS·
Parameter
Supply Voltage
Input Voltage
Operating Temperature
Storage Temperature
Symbol
Vee
VIN
TA
TSTG
Value
Units
-0.3 to +7.0
Vdc
-0.3 to Vee + 0.3 Vdc
·C
Oto + 70
·C
-55 to + 150
ELECTRICAL CHARACTERISTICS
!Yee = 5.0 Vdc :1:5%. Vss = 0 Vdc. TA = o·C to 70·C.
unless otherwise specified)
Parameter
Symbol
Min.
Typ.
Input Low Voltage
VIL
-0.3
Input High Voltage
VIH
+2.0
Output Low Voltage
VOL
-
-
Output High Voltage
TIL
CMOS
VOH
+2.4
-
VOH
+3.5
-
Output Low Current
IOL
-1.6
Output High Current
IOH
-100
Input Capacitance
CIN
-
Power Dissipation
Po
-
Units
Max.
Test Condition
+0.8
V
VCC+0.3
V
+0.4
V
-
V
ILOAD = -1oo!AA
V
ILOAD= 0
5
100
ILOAD = 1.6 mA
mA
VOL= 0.4V
fAA
VOH = 2.4V
pF
mW
•
6-159
CRC-4 Encoder/Decoder
R8075
PACKAGE DIMENSIONS
28-PIN PLASTIC LEADED CHIP CARRIER (PLCC)
MILLIMETERS
INDEX
i4--_.. D~ ---.
VSEATING PLANE
CORNER,
'.
I
'-'"
r-~g~ ~1.
I
i
A
L~
I
~r?l'~~~B
i I 02
I '
l
i
INDICATOR
.1__
11
'
SIDE VIEW
TOP VIEW
EJECTOR PIN MARKS
4 PLCS BOTTOM OF
PACKAGE ONLY
(TYPICAL)
b·IH r
CHAM.
hx45°
3 PLCS
e
A ~~8!.!!Y= A
-tj~. U 1!10 ;"U
---=-- ~ ---::::
c: 2i 9-;"
5
~~~.
P
MIN
A
414
BOTTOM VIEW
6-160
INCHES
MIN
MAX
439
0163
0173
137
147
0054
0058
A2
231
246
0091
0097
0457 TYP
1252
0018 TYP
D
1237
D1
114311153
045010454
D2
754 1 770
0297 1 0303
D3
1067 REF
•h
127
J
025 TYP
sse
"5 TYP
0487
0493
0420 REF
0050
esc
0045 TYP
0.Q10 TYP
a
45" TYP
45° TYP
R
089 TYP
0035 TVP
R1
025 TYP
0010 TYP
iA
~
SECTION A-A
TYP FOR BOTH AXIS (EXCEPT FOR BEVELED EDGE)
-CHAM.Jx45°
MAX
A1
b
18
.yL_
DIM
R8075
CRC-4 Encoder/Decoder
PACKAGE DIMENSIONS (CONT'D)
24-PIN CERDIP
-----------Tf~~
F
lU
'~~~~~
......
uL.l1
1 250 :t 0025 - - - - - . . . .
(3200 ±034)
l
lW1iY\MlmW "T'
0160 ±002
J: ~'~ ::9 ~ k":.,, ,1.~'\l"~'
r
~10~~ ~ ~ ~g)
(0 45 ± 0 05)
DIMENSIONS IN INCHES AND (MILLIMETERS)
24-PIN PLASTIC DIP
~~,,[ ~~~ ~~~ ~ ~~ ~]J
I
1260
1230
I
0050
~~i"1
MAX
-'-0065 - ADO +-+-+-+--
AD7
ALE
II
CS
RSER
RSYNC
RRED
RT9170
MPU
'W'R
RD
]
Receive
LlU
r""mi< [
Facility
Transmit
[
+--
TPITNRZ . - TN/TMX +-TCLK
TSER
..-.. TSITMX
----.
RLCLK
RliNK
TlCLK
EXDATA
PUP
Yee
Yss
Figure 2. RT9170 Interface Signals
6-163
]
Transmit
]
Facility
Receive
Intelligent T-1 Controller
RT9170
Transceiver and Off·Llne Framer Functions
General
The RT9170 has fully independent transmit and receive
sections. A robust framing algorithm which prevents
synchronization on patterns which mimic the framing bits
is implemented for ESF mode. An Off-line Framer mode
is provided. In this mode, the Receiver Sync signals are
derived from the Off-line Framer timing, which also
provides bit, frame, and multiframe timing for receiving
Trunk and Signal Conditioning. Transceiver functions also
include zero suppression, alarm generation and detection,
and loopback modes.
The RT9170 supports the T1 C1.2 technical subcommittee
draft, CCITT Recommendation G.733, applicable sections
of G.703, and AT&T technical advisories on cleqr·channel
capability and Extended SuperFrame format (ESF). The
following modes of T-1 PCM operation are supported:
1938, 193E, 193N, 193F.
The RT9170 is a low power CMOS device which operates
from a single +5 volt power supply and a sampling clock of
1.544 MHz. Packaged in a 40-pin plastic DIP or a 44-pin
PLCC, the RT9170 requires less real-estate and offers increased functionality than previous devices. The flexibility
and power of the RT9170 supports use in diverse areas of
voice and data communications.
6-164
R6551
'1'
Rockwell
R6551
Asynchronous Communications
Interface Adapter (ACIA)
DESCRIPTION
FEATURES
The Rockwell R6551 Asynchronous Communications Interface
Adapter (ACIA) provides an easily implemented, program controlled interface between 8-bit microprocessor-based systems
and serial communication data sets and modems.
•
•
•
•
Compatible with 8-bn microprocessors
Full duplex operation wnh buffered receiver and transmitter
Data set/modem control functions
Internal baud rate generator wnh 15 programmable baud
rates (50 to 19,200)
• Program-selectable internally or externally controlled receiver
rate
• Programmable word lengths, number of stop bits, and parity
bit generation and detection
• Programmable interrupt control
The ACIA has an internal baud rate generator. This feature eliminates the need for mu~iple component support circuns, a crystal
being the only other part required. The Transmitter baud rate
can be selected under program control to be enher 1 of 15 different rates from 50 to 19,200 baud, or at '/'6 times an external
clock rate. The Receiver baud rate may be selected under program control to be either the Transmitter rate, or at '/'6 times
an external clock rate. The ACIA has programmable word
lengths of 5, 6, 7, or 8 bits; even, odd, or no parity; 1, 1'12, or
2 stop bits.
•
•
•
•
•
•
•
•
The ACIA is designed for maximum programmed control from
the microprocessor (MPU), to simplify hardware implementation. Three separate registers permn the MPU to easily select
the R6551's operating modes and data checking parameters
and determine operational status.
Program reset
Program-selectable serial echo mode
Two chip selects
2 or 1 MHz operation
5.0 Vdc ± 5% supply requirements
28-pin plastic or ceramic DIP
Full TTL compatibility
Compatible wnh R6500, R6500r and R6SCOO microprocessors
The Command Register controls parny, receiver echo mode,
transmitter interrupt control, the state of the RTS line, receiver
interrupt control, and the state of the DTR line.
The Control Register controls the number of stop bits, word
length, receiver clock source, and baud rate.
VSS
CSO
ffi
RES
RxC
The Status Register indicates the states of the IRQ, DSR, and
DCD lines, Transmitter and Receiver Data Registers, and
Overrun, Framing, and Parity Error conditions.
The Transmitter and Receiver Data Registers are used for temporary data storage by the ACIA Transmit and Receiver Circuits.
XTLI
XTLO
RTS
CTS
TxO
OTR
RxO
RSO
RS1
ORDERING INFORMATION
Part No.: R6551 __ _
[
Temperature Range (T L to T Hl:
Blank = O"C to + 70·C
E = -40"C to +85·C
Frequency Range:
1=IMHz
2 = 2 MHz
,
~
Frequency Range.
No Letter = 1 MHz
A = 2MHz
Document No. 29651N90
1
2
3
M
4
07
5
6
D6
OS
R/W
'2
10
11
12
13
04
03
02
01
00
OSR
DCD
14
vee
7
B
9
21
Figure 1. R6551 ACIA Pi" Configuration
Product Description
6-165
Order No. 284
Rev. 4, June 1987
•
R6551
Asynchronous Communications Interface Adapter (ACIA)
CfS
T,D
00-07
oeD
iRQ
DSR
"IW
R,e
eso
)tfL!
CSi
XTLO
"SO
liflI
RS1
R'fS
;,
R,O
RES
Figure 2.
ACIA Internal Organization
FUNCTIONAL DESCRIPTION
TIMING AND CONTROL
A block diagram of the ACIA is presented in Figure 2. A description of each functional element of the device follows.
The Timing and Control logic controls the timing of data transfers
on the internal data bus, the registers, the Data Bus Buffer, the
microprocessor data bus, and the hardware reset.
DATA BUS BUFFERS
Timing is controlled by the system 1/)2 clock input. The chip will
perform data transfers to or from the microcomputer data bus during the 1/)2 high period when selected.
The Data Bus Buffer interfaces the system data lines to the internal data bus. The Data Bus Buffer is bi-directional. When the
Rm line is low and the chip is selected, the Data Bus Buffer
writes the data from the system data lines to the ACIA internal
data bus. When the Rm line is high and the chip is selected,
the Data Bus Buffer drives the data from the internal data bus
to the system data bus.
All registers will be initialized by the Timing and Control Logic
when the Reset (RES) line goes low. See the individual register
description for the state of the registers following a hardware
reset.
INTERRUPT LOGIC
The Interrupt Logic will cause the IRQ line to the microprocessor
to go low when conditions are met that require the attention of
the microprocessor. The conditions which can cause an interrupt will set bit 7 and the appropriate bit of bits 3 through 6 in
the Status Register, if enabled. Bits 5 and 6 correspond to the
Data Carrier Detect (DCD) logic and the Data Set Ready (DSR)
logic. Bits 3 and 4 correspond to the Receiver Data Register full
and the Transmitter Data Register empty conditions. These conditions can cause an interrupt request if enabled by the Command Register.
TRANSMITTER AND RECEIVER DATA REGISTERS
These registers are used as temporary data storage for the
ACIA Transmit and Receive Circuits. Both the Transmitter and
Receiver are selected by a Register Select 0 (RSO) and Register
Select 1 (RS1) low condition. The Read/Write (RlW) line determines which actually uses the internal data bus; the Transmitter
Data Register is write only and the Receiver Data Register IS
read only.
Bit 0 is the first bit to be transmitted from the Transmitter Data
Register (least significant bit first). The higher order bits follow
in order. Unused b~s in this register are "don't care".
110 CONTROL
The 1/0 Control Logic controls the selection of internal registers
for a data transfer on the internal data bus and the direction of the
transfer to or from the register.
The Receiver Data Register holds the first received data bit in
bit 0 (least significant bit first). Unused high-order bits are "0".
Parity bits are not contained in the Receiver Data Register. They
are stripped off after being used for par~y checking.
The registers are selected by the Register Select (RS1, RSO) and
Read/Write (Rm) lines as described later in Table 1.
6-166
R6551
Asynchronous Communications Interface Adapter (ACIA)
STATUS REGISTER
Parity Error (Bit 0), Framing Error (Bit 1), and
Overrun (Bit 2)
The Status Register indicates the state of interrupt conditions and
other non-interrupt status information. The interrupt conditions are
Data Set Ready and Data Carrier Detect transitions, Transmitter
Data Register Empty and Receiver Data Register Full as reported
in bits 6 through 3, respectively. If any of these bits are set, the
Interrupt (IRO) indicator (bit 7) is also set. Overrun, Framing Error,
and Parity Error are also reported (bits 2 through 0 respectively).
7
6
5
4
3
2
None of these bits causes a processor interrupt to occur, but they
are normally checked at the time the Receiver Data Register is
read so that the validity of the data can be verified. These bits are
self clearing (i.e., they are automatically cleared after a read ofthe
Receiver Data Register).
o
Receiver Data Register Full (Bit 3)
PE
This bit goes to a 1 when the ACIA transfers data from the Receiver
Shift Register to the Receiver Data Register, and goes to a 0 (is
cleared) when the processor reads the Receiver Data Register.
Bit 7
0
1
Interrupt (IRQ)
No interrupt
Interrupt has occurred
Bit 6
0
1
Data Set Ready (DSR)
DSR low (ready)
I:iSR high (not ready)
This bit goes to a 1 when the ACIA transfers data from the Transmitter Data Register to the Transmitter Shift Register, and goes
to a 0 (is cleared) when the processor writes new data onto the
Transmitter Data Register.
Bit 5
0
1
Data Carrier Detect (DCD)
iJCI) low (detected)
DC!:) high (not detected)
NOTE: There is a delay of approximately:;', of a bit time after
TOR becomes empty/full before this flag is updated.
Bit 4
0
Transmitter Data Register Empty
Not empty
Empty
Data Carrier Detect (Bit 5) and Data Set Ready
(Bit 6)
Bit 3
0
1
Receiver Data Register Full
Not full
Full
bit 2
0
1
Overrun'
No overrun
Overrun has occurred
Bit 1
0
1
Framing Error'
No framing error
Framing error detected
Bit 0
Parity Error'
No parity error
Parity error detected
0
1
Transmitter Data Register Empty (Bit 4)
These bits reflect the levels of the DCD and DSR inputs to the
ACIA. A 0 indicates a low level (true condition) and a 1 indicates
a high level (false). Whenever either of these inputs change state,
an immediate processor interrupt (IRO) occurs. When the interruptoccurs, the status bits indicate the levels of the inputs immediately after the change of state occurred. Subsequent level changes
will not affect the status bits until after the Status Register has been
interrogated by the processor. At that time, another interrupt will
immediately occur and the status bits will reflect the new input
levels. These bits are not automatically cleared (or reset) by an
internal operation.
Interrupt (Bit 7)
This bit goes to a 1 whenever an interrupt condition occurs and
goes to a 0 (is cleared) when the Status Register is read.
"No interrupt occurs for these conditions
Reset Initialization
Hardware reset
Program reset
6-167
•
Asynchronous Communications Interface Adapter (ACIA)
R6551
CONTROL REGISTER
Selected Baud Rate (Bits 0, 1, 2, 3)
The Control Register selects the desired baud rate, frequency
source, word length, and the number of stop bits.
These bits select the Transmitter baud rate, which can be at
'/,6 an external clock rate or one of 15 other rates controlled by
the internal baud rate generator.
If the Receiver clock uses the same baud rate as the transmitter,
then RxC becomes an output and can be used to slave other
circuits to the ACIA. Figure 3 shows the Transmitter and Receiver
layout.
Bit 7
Stop Bit Number (SBN)
1 Stop bit
2 Stop bits
1'12 Stop bits
For WL ~ 5 and no parity
1 Stop bit
For WL ~ 8 and parity
o
1
1
Bits ()-5
~~
o
o
0
1
0
1
1
1
Bit 4
1
Bits 3-0
~
1-
1
1
Word Length (WL)
No. Bits
8
7
....-RxD
~~""""""""""""""~RxC
6
5
Receiver Clock Source (RCS)
External receiver clock
Baud rate
o
o
o
o
o
o
o
o
o
. .-
0
0
0
0
1
0
0
o
o
1
Selected Baud Rate (SBR)
..1. ..Q.. Baud
16x External Clock
0
0
0
1
50
0
75
1
1
109.92
134.58
0
0
0
1
150
1
300
0
1
1
600
1200
0
0
1
1800
0
2400
1
0
1
1
3600
0
4800
0
0
7200
0
9600
1
19,200
.....- ........ TxD
Figure 3.
Transmitter/Receiver Clock Circuits
Receiver Clock Source (Bit 4)
This bit controls the clock source to the Receiver. A 0 causes
the Receiver to operate at a baud rate of '/,6 an external clock.
A 1 causes the Receiver to operate at the same baud rate as
is selected for the transmitter.
Word Length (Bits 5, 6)
Reset Initialization
These bits determine the word length to be used (5, 6, 7 or 8
bits).
76543210
I~I~I~I~I~I~I~I~I Program reset
Hardware reset (RES)
Stop Bit Number (Bit 7)
This bit determines the number of stop bits used. A 0 always
indicates one stop bit. A 1 Indicates 1V2 stop bits if the word
length is 5 with no parity selected, 1 stop bit if the word length
is 8 with parity selected, or 2 stop bits in all other configurations.
6-168
Asynchronous Communications Interface Adapter (ACIA)
R6551
COMMAND REGISTER
Data Terminal Ready (Bit 0)
The Command Register controls specific modes and functions.
This bit enables all selected interrupts and controls the state of
the Oata Terminal Ready (OTR) line. A 0 indicates the microcomputer system is not ready by setting the OTR line high. A
1 Indicates the microcomputer system is ready by setting the
OTR line low. DTR also enables and disables the transmitter
and receiver.
Bits 7-6
7
6
o
1
1
0
0' 0
Bit 5
o
Bit 4
o
1
Bits 3-2
3
Receiver Interrupt Control (Bit 1)
Parity Mode Control (PMC)
This bit disables the Receiver from generating an interrupt when
set to a 1. The Receiver interrupt is enabled when this bit is set
to a 0 and Bit 0 is set to a 1.
Odd parity transmitted/received
Even parity transmitted/received
Mark parity bit transmitted
Parity check disabled
Space parity bit transmitted
Parity check disabled
Transmitter Interrupt Control (Bits 2, 3)
These bits control the state of the Ready to Send (RTS) line and
the Transmitter interrupt.
Parity Mode Enabled (PME)
Parity mode disabled
No parity bit generated
Parity check disabled
Parity mode enabled
Receiver Echo Mode (Bit 4)
A 1 enables the Receiver Echo Mode and a 0 disables the
Receiver Echo Mode. When bit 4 is a 1 bits 2 and 3 must be
O. In the Receiver Echo Mode, the Transmitter returns each
transmission received by the Receiver delayed by one-half bit
time.
Receiver Echo Mode (REM)
Receiver normal mode
Receiver echo mode
Bits 2 and 3 must also be zero for receiver
echo mode, RTS will be low.
Parity Mode Enable (Bit 5)
This bit enables parity bit generation and checking. A 0 disables
parity bit generation by the Transmitter and parity bit checking
by the Receiver. A 1 bit enables generation and checking of
parity bits.
Transmitter Interrupt Control (TIC)
2
o
0'
1
1
0
1
o
1
Bit 1
o
1
Bit 0
o
1
RTS =
RTS =
RTS =
RTS =
High, transmitter disabled'
Low, transmit interrupt enabled
Low, tansmit interrupt disabled
Low, transmit interrupt disabled,
transmit break on TxO"
Parity Mode Control (Bits 6, 7)
These bits determine the type of parity generated by the Transmitter, (even, odd, mark or space) and the type of parity check
done by the Receiver (even, odd, or no check).
Receiver Interrupt Request Disabled (IRD)
IRQ enabled (receiver)
IRQ disabled (receiver)
Reset Initialization
765 432 1 0
Data Terminal Ready (DTR)
Oata terminal not ready (OTR high)'
Oata terminal ready (OTR low)
10 I 0 I 0 I 0 1 0 10 10 1 0 1 Hardware reset (RES)
1-.-.-. o. o. o. o. O .. Program reset
NOTES
'The transmitter is disabled Immediately. The receiver is
disabled but will first complete receiving a byte in process of
being received.
" A break is transmitted only after the end of a character stream.
lithe Transmit Oata Register contains a character, the break is
not transmitted.
6-169
•
Asynchronous Communications Interface Adapter (ACIA)
R6551
INTERFACE SIGNALS
Read/Write (R/W)
Figure 4 shows the ACIA interface signals associated with the
microprocessor and the modem.
The RIW input, generated by the microprocessor controls the
direction of data transfers. A high on the Rtw pin allows the
processor to read the data supplied by the ACIA, a low allows a
write to the ACIA.
Interrupt Request (IRQ)
CTS
The IRQ pin is an interrupt outputfrom the interrupt control logic.
It is an open drain output, permitting several devices to be connected to the commmon IRQ microprocessor input. Normally a
high level, IRQ goes low when an interrupt occurs.
TxD
IRQ
DCD
RiW
CSO
DSA
CS1
RxC
RSO
XTLI
RS1
XTLO
Data Bus (DO-07)
The eight data line (DO-D7) pins transfer data between the processor and the ACIA. These lines are bi-directional and are normally high-impedance except during Read cycles when the ACIA
is selected.
_2
DTR
RES
Chip Selects (CSO, CS1)
RTS
vcc
The two chip select inputs are normally connected to the processor address lines either directly or through decoders. The ACIA
is selected when CSO is high and CS1 is low. When the ACIA
is selected, the internal registers are addressed in accordance with
the register select lines (RSO, RS1).
RxD
VSS
Register Selects (RSO, RS1)
Figure 4. ACIA Interface Diagram
The two register select lines are norrnally connected to the processor address lines to allow the processor to select the various
ACIA internal registers. Table 1 shows the internal register select
decoding.
MICROPROCESSOR INTERFACE
Table 1. ACIA Register Selection
Reset (RES)
Register Operation
During system initialization a low on the RES IOput causes a
hardware resetto occur. Upon reset, the Command Register and
the Control Register are cleared (all bits set to 0). The Status
Register is cleared with the exception of the indications of Data
Set Ready and Data Carrier Detect, which are externally controlled
by the DSR and DCD lines, and the transrnitter Empty bit,
which is set. RES must be held low for one 1/)2 clock cycle for a
reset to occu r.
Input Clock ($2)
= Low
= High
RS1
RSO
L
L
Write Transmit Data
Register
Read Receiver
Data Register
L
H
Programmed Reset
(Data IS "Don't
Care")
Read Status
Register
H
L
Write Command
Register
Read Command
Register
H
H
Write Control
Register
Read Control
Register
R/W
RIW
Only the Command and Control registers can be both read and
written. The programmed Reset operation does not cause any data
transfer, but IS used to clear bits 4 through 0 in the Command
register and bit 2 10 the Status Register. The Control Register is
unchanged by a programmed Reset. It should be noted that the
p.!Qillammed Reset is slightly different from the hardware Reset
(RES); refer to the register description.
The input clock is the system 1/)2 clock and clocks all data transfers between the system microprocessl r and the ACIA.
NOTE: The specified maximum cycle time for the signal on this
input is 40 ,,5. This specification must be observed to prevent loss
of data.
6-170
Asynchronous Communications Interface Adapter (ACIA)
R6551
ACIA/MODEM INTERFACE
Clear to Send (CTS)
Crystal Pins (XTLI, XTLO)
The CTS input pin controls the transmitter operation. The enable
state is wijh CTS low. The transmitter IS automatICally disabled
if CTS is high.
These pins are normally directly connected to a series mode
external crystal (1.8432 MHz) to derive the various baud rates.
Alternatively, an externally generated clock can drive the XTLI pin,
in which case the XTLO pin must float. XTLI is the input pin for
the transmit clock.
Data Terminal Ready (DTR)
This output pin indicates the status of the ACIA to the modem.
A low on DTR indicates the ACIA is enabled, a high Indicates
it IS disabled. The processor controls this pin via bit 0 of the
Command Register.
Transmit Data (TxD)
Data Set Ready (DSR)
The TxD output line transfers serial nonreturn-to-zero (NRZ) data
to the modem. The least significant bit (LSB) olthe Transmit Data
Register is the first data bit transmitted and the rate of data transmission is determined by the baud rate selected or by an external
clock. This selection is made by programming the Control Register.
The DSR input pin Indicates to the ACIA the status of the
modem. A low indicates the "ready" state and a high, "nolready."
Data Carrier Detect (DCD)
The DCD input pin indicates to the ACIA the status of the carrierdetect output of the modem. A low indicates that the modem
carrier signal is present and a high, that it is not.
Receive Data (RxD)
The RxD input line transfers serial NRZ data into the ACIA from
the modem, LSB first. The receiver data rate is determined by the
programmed baud rate or by an externally generated receiver
clock. The selection is made by programming the Control Register.
TRANSMITTER AND RECEIVER
OPERATION
Receive Clock (RxC)
Continuous Data Transmit
RxC is a bi-directional pin which is either the receiver 16x clock
input or the receiver 16x clock output. The latter mode results if
the internal baud rate generator is selected for receiver data
clocking.
In the normal operating mode, the interrupt request output (IRQ)
signals when the ACIA is ready to accept the next data word to
be transmitted. This interrupt occurs at the beginning of the Start
Bit. When the processor reads the Status Register of the ACIA,
the interrupt is cleared.
Request to Send (RTS)
The processor must then identify that the Transmit Data Register is ready to be loaded and must then load it with the next
data word. This must occur before the end of the Stop Bit, otherwise a continuous "MARK" will be transmitted. Figure 5 shows
the continuous Data Transmit timing relationship.
The RTS output ~ controls the modem from the processor.
The state of the RTS pin is determined by the contents of the
Command Register.
CHAR#n
TxD
CHAR .ttn+2
CHAR #n+1
~/
~/
CHAR#n+3
~/
~
ls,",trn ~ ~ ruStop!St"trn~ ~ ruStopISt"'5JBJ ~ ~ ruStoplStartrn ~ ~ ruStopL
/
I
I
I
I
IROLJI]
I
/
PROCESSOR
INTERRUPT
(TRANSMIT DATA
REGISTER EMPTY)
I
:
Lllr
'-'\
/LllJ
~
PROCESSOR READS STATUS
REGISTER, CAUSES IRQ
TO CLEAR
Figure 5.
PROCESSOR MUST
LOAD NEW DATA
IN THIS TIME
INTERVAL, OTHERWISE,
CONTINUOUS "MARK"
IS TRANSMITTED
Continuous Data Transmit
6-171
I
:
I
LllJ
L
•
R6551
Asynchronous Communications Interface Adapter (ACIA)
Continuous Data Receive
Similar to the Continuous Data Transmit case, the normal
operation of this mode is to assert IRQ when the ACIA has
received a full data word. This occurs at about 9/,6 point through
the Stop BIt. The processor must read the Status Register and
CHAR#n
CHAR#Il+1
/
RxO
read the data word before the next interrupt, otherwise the
Overrun condition occurs. Figure 6 shows the continuous Data
Receive Timing Relationship.
CHAR#n+3
CHAR#n+2
'-./
'-./
'-./
""
lSt..t5JB1J ~ ~ ~ Stopl Stort5JB1J ~ ~ liE] Stopl St..trs:EJ ~ ~ liI:JStopISta,,5JB1J ~ ~ liI:JStopL
I
I
I
I
I
I
PROCESSOR
INTERRUPT OCCURS
~:~~i6;,6BII~:O
)
PARITY, OVERRUN,
AND FRAMING ERROR
ALSO. UPDATED
~
'-'\
PROCESSOR READS STATUS
~~~I~;!:,. CAUSES IRQ
Figure 6.
L
Lm
UI'll"===::::;::=:::7J'U
~~~~~~~~~~:~:~~~
TIME INTERVAL, OTHERWISE,
OVERRUN OCCURS
Continuous Data Receive
Transmit Data Register Not Loaded by Processor
If the processor is unable to load the Transmit Data Register In
the allocated time, then the TxD line goes to the "MARK" condition until the data IS loaded. IRQ interrupts continue to occur
at the same rate as previously, except no data is transmitted.
When the processor finally loads new data, a Start Bit immediately occurs, the data word transmission is started, and another
interrupt is initiated, signaling for the next data word. Figure 7
shows the timing relationship for this mode of operation.
CONTINUOUS "MARK"
CHAR#n
CHAR #n+1
I
TxO
I
.----.--,-_'-.-'-----
/
F1Start[%EJ~ ~ ~Stopi
I-
I
LJIJ'
PRocLoR
CHARACTER_I
TIME
'LJIJ--
\
~
L..J
'"
INTERRUPT
FOR DATA
REGISTER
/
INTERRUPTS
CONTINUE AT
CHARACTER RATE,
EMPTY
PROCESSOR
EVEN THOUGH
READS
NO DATA IS
TRANSMITTED
STATUS
REGISTER
Figure 7.
WHEN PROCESSOR FINALLY LOADS
NEW DATA, TRANSMISSION STARTS
IMMEDIATELY AND INTERRUPT
OCCURS, INDICATING TRANSMIT
DATA REGISTER EMPTY
Transmit Data Register Not Loaded by Processor
6-172
CHAR#n+2
Asynchronous Communications Interface Adapter (ACIA)
R6551
CTS is the Clear-to-Send Signal generated by the modem. It is
normally low (true state) but may go high in the event of some
modem problems. When this occurs, the TxD line immediately
goes to the "MARK" condition. Interrupts continue at the same
rate, but the Status Register does not indicate that the Transmit
Data Register is empty. Since there is no status bit for CTS, the
processor must deduce that ers has gone to the FALSE (high)
state. ers is a transmit control line only, and has no effect on
the R6551 Receiver Operation. Figure 8 shows the timing relationship for this operation.
CHAR#n+1
CHAR#n
CONTINUOUS "MARK"
/~
TxD
B~
______________IL-__________
'-../
G::JStopls..rtfili~~-..- ...........-+---'...........
-~
I
I.-- CHARACTER ----.l
I
TIME
I
NOT CLEAR-TO·SEND
CLEAR·TO-SENO
AT NORMAL
START BIT
PROCESSOR READS
STATUS REGISTER.
SINCE DATA REGISTER
IS NOT EMPTY, PROCESSOR
MUST DEDUCE THAT
Ci'S IS SOURCE OF
TIME
INTERRUPT (THIS IS
NEXT
PROCESSOR
INTERRUPT
maOESHIOH,
INDICATING MODEM
IS NOT READY TO
RECEIVE DATA. TxD
COVERED ELSEWHERE
IN THIS NOTE).
IMMEDIATELY GOES
TO "MARK" CONDJTlON
Figure 8.
Effect of CTS on Transmitter
Effect of Overrun on Receiver
Overrun status bit is set. Thus, the Data Register will contain the
last valid data word received and all following data is lost. Figure 9
shows the timing relationship for this mode.
If the processor does not read the Receiver data Register in the
allocated time. then, when the next interrupt occurs. the new data
word is not transferred to the Receiver Data Register, but the
CHAR#n+1
CHAR#n
PROCESSOR
INTERRUPT
FOR RECEiVER
DATA REGISTER
FULL
CHAR#n+2
~
PROCESSOR
READS
STATUS
REGISTER
RECEIVER DATA REGISTER
NOT UPDATED, BECAUSE
PRoceSSOR DID NOT READ
PREVIOUS DATA, OVERRUN
BIT SET IN STATUS
REGISTER
'-...~~/~
OVERRUN BIT SET IN
STATUS REGISTER
Figure 9.
Effect of Overrun on Receiver
6-173
CHAR#n+3
II
Asynchronous Communications Interface Adapter (ACIA)
R6551
Echo Mode Timing
In Echo Mode, the TxD line re·transmits the data on the RxD
line, delayed by Y2 of the bit time, as shown in Figure 10.
Figure 10.
Echo Mode Timing
Effect of CTS on Echo Mode Operation
In Echo Mode, the Receiver operation is unaffected by CTS,
however, the Transmitter is affected when CTS goes high, i.e.,
the TxD line immediately goes to a continuous "MARK" con·
dition. In this case, however, the Status Request indicates that
CHAR#n
~/
RxD
iRa
I
the Receiver Data Register is full in response to an IRQ, so the
processor has no way of knowing that the Transmitter has
ceased to echo. See Figure 11 for the timing relationship of this
mode.
CHAR#n+1
,/
CHAR#n+2
I
,/
CHAR#n+3
I
,/
I
Rs...t~ ~ ~ liEJStopls...trs:E] ~ ~ liEJsto+a{q"Bl] ~ ~ ffiStopISt."rs:E] ~ ~ EI
I
I
I
I
LJlJ
Llll
un
LllJ
NOT ..cLEAR·TO..$END
I
CTS
I
CONTINUOUS "MARK" UNTIL
ffi
GOES LOW
r---+-----------~-----1--------------,~
TxD
~ ~~~ Stopl Start I So 18 , 182 11
L
TS GOES TO)
I
"FALSE" CONDITION
NORMAL
RECEIVER DATA
' - - - - - - - - - - - - - - - - REGISTER FULL ------------~
INTERRUPTS
Figure 11.
Effect of CTS on Echo Mode
6·174
R6551
Asynchronous Communications Interface Adapter (ACIA)
Overrun in Echo Mode
If Overrun occurs in Echo Mode, the Receiver is affected the
same way as a normal overrun in Receive Mode. For the retransmitted data, when overrun occurs, the TxD line goes to the
"MARK" condition until the first Start Bit after the Receiver Data
Register is read by the processor. Figure 12 shows the timing
relationship for this mode.
CHAR#.
CHAR#n
CHAR-1Fx+1
LllJ
LJI)
. . . . . ._-'---' ==Er
T.O
I
1
PROCESSOR
PROCESSOR FINALLY
TKO DATA
INTERRUPT
READS RECEIVER
DATA REGISTER,
RESUMES
FOR RECEIVER
DATA REGISTER
LAST VALID
CHARACTER (#nl
FULL
PROCESSOR
READS
STATUS
AEGISTER
PROCESSOR
INTERRUPT
FORCHAR#x
OVERRUN OCCURS
TIIO GOES TO
"MARK"
IN RECEIVER
DATA REGISTER
CONDITION
Figure 12. Overrun In Echo Mode
Framing Error
Framing Error is caused by the absence of Stop Bit(s) on received
data. A Framing Error is indicated by the setting of bit 1 in the
Status Register at the same time the Receiver Data Register Full
bit is' set, also in the Status Register. In response to IRQ,
generated by RDRF, the Status Register can also be checked for
the Framing Error. Subsequent data words are tested for Framing
Error separately, so the status bit will always reflect the last data
word received. See Figure 13 for Framing Error timing relationship.
R.O
(EXPECTEDI ......I_...&..........
•
R.D
(ACTUALI ......I_...&.........
PROCESSOR
INTERRUPT,
FRAMING
eRROR
BtTSET
NOTES: 1. FRAMING ERROR DOES NOT
INHIBIT RECEIVER OPERATION.
2. IF NEXT DATA WORD IS OK.
FRAMING ERROR IS CLEARED.
Figure 13. Framing Error
6-175
Asynchronous Communications Interface Adapter (ACIA)
R6551
Effect of
oeD on Receiver
DCD is a modem output indicating the status of the carrier-frequency-detection circuit of the modem. This line goes high for
a loss of carrier. Normally, when this occurs, the modem will
stop transmitting data some time later. The ACIA asserts IRQ
whenever DCD changes state and indicates this condition via
bit 5 in the Status Register.
Once such a change of state occurs, subsequent transitions will
not cause interrupts or changes in the Status Register until the
first interrupt is serviced. When the Status Register is read by
the processor, the ACIA automatically checks the level of the
DCD line, and if it has changed, another IRQ occurs (see Figure
14).
CONTINUOUS "MARK"
I
III
L_ ........
NORMAL
PROCESSOR
INTERRUPT
r
NO INTERRUPT
WILL OCCUR
AS LONG AS
i5C5 IS HIGH,
PROCESSOR
INTERRUPT
FOR 6C6
GOING HIGH
Figure 14.
NO FURTHER
INTERRUPTS
FOR RECEIVER
WILL OCCUR
PROCESSOR
INTERRUPT
FOR oeD
GOING LOW
HERE, SINCE
RECEIVER IS NOT
ENABLED UNTIL
FIRST START BIT
DETECTED
PROCESSOR /
INTERRUPT
FOR
RECEIVER
DATA
Effect of OeD on Receiver
Timing with 1Y2 Stop Bits
tl is possible to select 1V2 Stop Bits, but this occurs only for
5-bit data words wtth no parity bit. In this case, the IRQ asserted
for Receiver Data Register Full occurs hallway through the
trailing half-Stop Bit. Figure 15 shows the timing relationship for
this mode.
CHAR#n
CHAR:f:in+1
RxD
PROCESSOR INTERRUPT
OCCURS HALFWAY
THROUGHT THE 1/2
STOP BIT
Figure 15.
Timing with 1'h Stop Bits
6-176
R6551
Asynchronous Communications Interface Adapter (ACIA)
Transmit Continuous "BREAK"
Note
This mode is selected via the ACIA Command Register and
causes the Transmitter to send continuous "BREAK" characters, beginning with the next character transmitted. At least one
full "BREAK" character will be transmitted, even if the processor
quickly re-programs the Command Register transmit mode.
Later, when the Command Register is programmed back to
normal transmit mode, an immediate Stop Bit will be generated
and transmission will resume. Figure 16 shows the timing relationship for this mode.
If, while operating In the Transmit Continuous "BREAK"
mode, the CTS should go to a high, the TxD Will be
overridden by the CTS and will go to continuous "MARK"
at the beginning of the next character transmitted after the
CTS goes high.
,,/
/
Stop
I
';
~_Fl~:I~[]il:JStopls",t5"E1
f--+--ll
I
~,
PERIOD DURING
I-------~_ ~EH~~~:sROCESSOR
CONTINUOUS
"BREAK" MODE
NORMAL
INTERRUPT
POINT AT WHICH
PROCESSOR
SELECTS
NORMAL
PROCESSOR
INTERRUPT
TO LOAD
TRANSMIT
TRANSMIT
DATA
MODE
Figure 16. Transmit Continuous "BREAK"
Receive Continuous "BREAK"
In the event the modem transmits continuous "BREAK" characters, the ACIA will terminate receiving. Reception will resume
only after a SlOp Bit is encountered by the ACIA. Figure 17
R.O
--------"
shows the timing
characters.
CONTINUOUS "BREAK"
relationship
for
continuous "BREAK"
,,/'----]:~I]iEJTISt,."..tl-B-O-I-B-,--'-B-N--P-I-Itl-!..!.1_-,-~~St.rt~I]~±JTls""1 BO IB, I
)u
/
~ NMOO'~ER ~ NO INTERRUPT
r
SINCE RECEIVER
PROCESSOR
PROCESSOR INTERRUPT WITH INTERRUPTS
INTERRUPT
FOR
A~t.;EIVER
FRAMING ERROR BIT SET,
,;::U~,TA REGISTER
FULL
~:~:~~~~;I~IL
EVEN PARITY CHECK WILL ALSO
GIVE A PARITY ERROR BECAUSE
ALL ZEROS (CONTINUOUS BREAK)
REPRESENT EVEN PAAITY.
Figure 17.
Receive Continuous "BREAK"
6-177
NORMAL
RECIEVER
INTERRUPT
•
R6551
Asynchronous Communications Interface Adapter (ACIA)
STATUS REGISTER OPERATION
3. Receiver and transmitter interrupts are disabled Immediately.
If IRQ is low when the reset occurs, it stays low until serviced,
unless interrupt was caused by OCD or DSR transition.
Because of the special functions of the various status bits, there
is a suggested sequence for checking them. When an interrupt
occurs, the ACIA should be interrogated, as follows:
4. DCD and DSR interrupts are disabled immediately. If IRQ
IS low and was caused by OCD or DSR, then it goes high,
also OCD and DSR status bits subsequently will follow the
input lines, although no interrupt will occur.
1. Read Status Register
This operation automati~ clears Bit 7 (IRQ). Subsequent
transitions on OSR and OCO will cause another interrupt.
5. Overrun cleared, if set.
2. Check IRQ (Bit 7) in the data read from the Status Register
MISCELLANEOUS
If not set, the interrupt source is not the ACIA.
3. Check OCO and OSR
1. If Echo Mode is selected, RTS goes low.
These must be compared to their previous levels, which must
have been saved by the processor. If they are both 0 (modem
"on-line") and they are unchanged then the remaining bits must
be checked.
2. If Bit 0 of Command Register (DTR) is 0 (disabled), then:
a)
.
b)
cj
4. Check RDRF (Bit 3)
All interrupts are disabled, including those caused by
DCD and DSR transitions.
Transmitter is disabled immediately.
Receiver is disabled, but a character currently being
received will be completed first.
Check for Receiver Data Register Full.
3. Odd parity occurs when the sum of all the 1 bits in the data word
(including the parity bit) is odd.
5. Check Parity, Overrun, and Framing Error (Bits 0-2) if the
Receiver Data Register is full.
4. In the receive mode, the received parity bit does not go into the
Receiver Data Register, but generates parity error or no parity
error for the Status Register.
6. Check TORE (Bit 4)
Check for Transmitter Data Register Empty.
5. Transmitter and Receiver may be in full operation simultaneously. This is "full-duplex" mode.
7. If none of the above conditions exist, then CTS must have
gone to the false (high) state.
6. lithe RxD line inadvertently goes low and then high right after
a Stop Bit, the ACIA does not interpret this as a Start Bit, but
samples the line again halfway into the bit time to determine
if it is a true Start Bit or a false one. For false Start Bit detection, the ACIA does not begin to receive data, instead, only a
true Start Bit initiates receiver operation.
PROGRAM RESET OPERATION
A program reset occurs when the processor performs a write operation to the ACIA with RSO low and RS1 high. The program reset
operates somewhat different from the hardware reset (RES pin)
and is described as follows:
7. DCD andd DSR transitions, although causing immediate
processor interrupts, have no affect on transmitter operation.
Data will continue to be sent, unless the processor forces transmitter to turn off. Since these are high-impedance Inputs, they
must not be permitted to float (un-connected). If unused, they
must be terminated to GNO.
1. Internal registers are not completely cleared. Check register
formats for the effect of a program reset on Internal registers.
2. The DTR line goes high immediately.
6-178
Asynchronous Communications Interface Adapter (ACIA)
R6551
CRYSTAL/CLOCK CONSIDERATIONS
CLOCK OSCILLATOR
EXTERNAL CLOCK
The on-chip oscillator is designed for a series resonant crystal connected between XTLI and XTLO pins (Figure 18).
The XTLI input may be used as an external clock input (Figure 19).
For this implementation, a times 16 clock is input on XTLI and
XTLO is left open.
A series resonant crystal is specified by the series resistance (Rs)
at its series resonant frequency. For proper oscillator operation,
the selected series resonant crystal should have a series
resistance less than 400 ohms.
EXTERNAL
TRANSMITTER
CLOCK
XTLI
R6551
XTLO
NO CONNECTION
Figure 18. Internal Clock Connection
R6551
XTLO
Figure 19. External Clock Connection
GENERATING NON-STANDARD BAUD RATES
BAUD RATE GENERATION
By using a different crystal, non-standard baud rates may be
generated. These can be determined by:
DIVISORS
Baud Rate
The internal counter/divider circuit generates appropriate
divisors to produce standard baud rates when a 1.8432 MHz crystal
is connected between XTLI and XTLO. Control Register bits 0-3
select the divisor for a particular bit rate as shown in Table 2.
Crystal Frequency
= --''----'-----'DIVisor
Furthermore, it is possible to drive the ACIA with an off-chip
oscillator to achieve other baud rates. In this case, XTALI (pin 6)
must be the clock input and XTALO (pin 7) must be a no-connect.
Table 2. Divisor Selection
Control
Register
Bits
Divisor Selected
For The
Internal Counter
Baud Rate Generated
With 1.8432 MHz
Crystal
Baud Rate Generated
With a Crystal
of Frequency (F)
16 x External Clock at Pin RxC
16 x External Clock at Pin RxC
3
2 1 0
0
0
0
0
No Divisor Selected
0
0
0
1
36,864
1 8432 x 10' / 36,864
= 50
F / 36,864
0
0
1 0
24,576
1 8432 x 10' / 24,576
= 75
F /24,576
0
0
1
1
16,769
18432 x 10'/16,769
F /16,769
0
1 0 0
13,704
1.8432 x 10'/13,704
= 109.92
= 13451
0
1 0
12,288
1.8432 x 10'/12,288
= 150
F /12,288
= 300
= 600
= 1,200
= 1,800
F /6,144
1
F/13,704
0
1
1 0
6,144
1.8432 x 10'/6,144
0
1
1
1
3,072
1 8432 x 10' / 3,072
1 0 0
0
1,536
1.8432 x 10'/1,536
1 0
0
1
1,024
1.8432 x 10' / 1,024
1 0
1 0
768
1.8432 x 10' / 768
F /768
1 0
1
1
512
1.8432 x
F /512
1
1 0
0
384
1 8432 x
1
1 0
1
256
1.8432 x
1
1 1 0
192
1.8432 x
1
1
96
18432 x
1
1
6-179
= 2,400
10'/512 = 3,600
10' / 384 = 4,800
10'/256 = 7,200
10'/192 = 9,600
10'/96 = 19,200
F /3,072
F /1,536
F /1,024
F /384
F /256
F /192
F /96
•
Asynchronous Communications Interface Adapter (ACIA)
R6551
DIAGNOSTIC LOOP-BACK
OPERATING MODES
3. Connects transmitter outputs to respective receiver inputs (i.e.
TxD to RxD, DTR to DCD, RTS to CTS).
A simplified block diagram for a system incorporating an ACIA is
shown in Figure 20.
LLB may be tied to a peripheral control pin (from an R6520 or
R6522, for example) to provide processor control of local loop-back
operation. In this way, the processor can easily perform local loopback diagnostic testing.
It may be desirable to include in the system a facility for local loopback testing.
In loop-back testing from the point of view of the processor, the
Modem and Data Link must be effectively disconnected and the
ACIA transmitter connected back to its own receiver, so that the
processor can perform diagnostic checks on the system, excluding
the actual data channel.
The ACIA does not contain automatic loop-back operating modes,
but they may be implemented with the addition of a small amount
of external circuitry. Figure 21 indicates the necessary logic to be
used with the ACIA. The LLB line is the positive-true signal to
enable local loop-back operation. Essentially, LLB = high does
the following:
TO DATA LINK
1. Disables outputs TxD, DTR, and RTS (to Modem).
Figure 20.
2. Disables outputs RxD, DCD, CTS, DSR (from Modem).
I
Simplified System Diagram
R6551
mOTR TxD
R xO
ll8
;~~
SEl
I
3V
4V
STS
*
fiCO ill DsR
74157
IS
lA
28
2A
3A
38
4A
*48
RxD
DCD
CTS
DSR
MODEM
F
+5
t=:-
SEl
TxD
IV
i5'fii
2V
ST8
RTS
3V
4V
i-----
74157
18
lA
28
2A
3B
3A
48
4A ~
NOTES
1. HIGH ON LLB SELECTS LOCAL LOOP·BACK MODE.
2. HIGH ON 74157 SELECT INPUT GATES "S" INPUTS
TO "Y" OUTPUTS; lOW GATES "A" TO "Y",
'---
Figure 21.
Loop-Back Circuit Schematic
6-180
R6551
Asynchronous Communications Interface Adapter (ACIA)
READ TIMING DIAGRAM
1-----ICCy---~
Timing diagrams for transmit with external clock, receive with
external clock, and IRQ generation are shown in Figures 22, 23
and 24, respectively. The corresponding timing characteristics are
listed in the Table 3.
Table 3.
Transmit/Receive Characteristics
1 MHz
Characteristic
2 MHz
TxO
Symbol
Min
Max
Min
Max
Unit
Transmit/Receive
Clock Rate
IccY
400*
-
400*
-
ns
Transmit/Receive
Clock High Time
tCH
175
-
175
ns
Transmit/Receive
Clock Low Time
tel
175
-
175
-
XTLIlo TxD
Propagation Delay
too
500
ns
RTS Propagation
Delay
tOlY
-
IRQ Propagation
Delay (Clear)
IIAQ
Load CapaCitance
DTR,RTS
TxD
Cl
Notes:
(tA, tF
XTLI
(TRANSMIT
CLOCK INPUT';')_ _- J
500
-
NOTE: TxO rat. is 1/16 TxC ral.
Figure 22.
ns
500
-
500
ns
-
500
-
500
ns
-
130
30
-
130
30
pF
pF
RxC
(INPUT!
Transmit Timing with External Clock
-----\j""~
?''"-~
L
'(
i-ICL-'
NOTE: RxO rate is 1/16 RxC rate
Figure 23.
Receive External Clock Timing
= 10 to 30 ns)
*The baud rate with external clocking is: Baud Rate
= __,_
16 x Iccy
1 )
i
iRa
(CLEAR)
Figure 24.
r--
--
~'''Q)Interrupt and Output Timing
•
6-181
R6551
Asynchronous Communications Interface Adapter (ACIA)
AC CHARACTERISTICS
= 5.0V ± 5%, Vss = 0, T A = T l
to T H, unless otherwise noted)
(Vcc
1 MHz
Parameler
Symbol
2 MHz
Min
Cycle Time
tCYC
(62 Pulse Width
tc
400
Address Set-Up Time
tACW' tACR
120
Address Hold Time
tCAH' tCAR
0
R/W Set-Up Time
twcw, tWCR
R/W Hold Time
Min
Max
1.0
40
Max
0.5
40
Unit
/LS
120
-
ns
70
-
0
-
ns
70
-
tCWH
0
-
0
-
ns
ns
Data Bus Set-Up Time
toew
150
-
60
-
ns
Data Bus Hold TIme
tHw
20
-
20
-
ns
Read Access Time (Valid Data)
tCOR
-
200
-
150
ns
Read Hold Time
tHR
20
20
ns
Bus Active Time (Invalid Data)
tcoA
40
-
200
-
40
ns
ns
Notes: 1. tR and tF = 10 to 30 ns.
2. DO-D7load capacitance = 130 pF.
3. Timing measurements are referenced tolfrom a low of 0.8 volts and a high of 2.0 volts.
IR -
,
ICjC
_IF
IC
~
I
"" -leAH-
I-IACWcso, CS1, RSO, RS1
I-Iwcw-
-ICWH-I.
\
R/W
!
rL__
VIH
VIL
ID_C_W
_ _ _ _ _I _ H _ W _ - . l _ V I H
DATABUS_
_ _
~----------'f
VIL
Write Timing Diagram
\
/
I-IACR-
I-ICAR·
CSO, CS1, RSO, RS1
/
_IWCR_ICDR-tCDA-~
DATA BUS
~
Read Timing Diagram
6-182
I-IHR-
R6551
Asynchronous Communications Interface Adapter (ACIA)
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Supply \bltage
Vee
Input \bRage
V,N
-0.3 to Vee
Vde
Output \bRage
VOUT
-0.3 to Vee
Vde
Operating Temperature
TA
Storage Temperature
T STG
Value
Unit
-0.3 to +7.0
• NOTE: Stresses above those listed may cause permanent
damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above
those indicated in other sections of this document is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect deVice reliability.
Vdc
·C
Oto+70
-S5 to +IS0
·C
OPERATING CONDITIONS
Parameter
Symbol
Value
Supply Voltage
Vcc
SV ±S%
Temperature Range
Commercial
Industrial
TA
O· to 70·C
- 40·C to + 8S·C
DC CHARACTERISTICS
(Vcc = 5.0V ± 5%, Vss = 0, TA = Tl to T H, unless otherwise noted)
Parameter
Symbol
Input High \bRage
Except XTLI and XTLO
XTLI and XTLO
V,H
Input Low VoRage
Except XTLI and XTLO
XTLI and XTLO
V'l
Min
Typ
Max
Test Conditions
Unit
V
2.0
2.4
-
Vee
Vee
V
liN
-
-
Input Leakage Current for High Impedance (Three State Off)
DO-07
ITSI
-
-
Output High \bRage _ _
00-07, TxO, AxC, RTS, OTR
VOH
2.4.
-
Output Low VoRage _ _ _
00-07, TxO, RxC, RTS, OTR, IRQ
Val
-
-
Output High Current ~rc~
00-07, TxO, AxC, RTS, OTR
10H
-100
-
-
fJoA
VOH = 2.4V
Output Low Current ~inL _
00-07, TxO, AxC, RTS, OTR, IRQ
10l
1.6
-
-
rnA
Val = O.4V
Output Leakage Current (off state)
iOFF
-
-
10.0
JJ.A
VOUT
Clock Capacitance
(\12)
CelK
-
-
20
pF
Input Capacitance
except 02, XTLI, XTLO
C 'N
-
-
10
pF
Output CapaeHance
COUT
-
-
10
pF
V ,N = OV
f = 1 MHz
TA = 25'C
Power Oissipation
Po
-
170
300
rnW
TA
Input Le~a~urrent
\12, R/W, RES, CSO, CS1, RSO, RS1, CTS, RxO, OCO,
IRQ
Vss
Vss
5SFi
6-183
0.8
0.4
2.S
fJoA
V,N = OVto 5V
Vee = OV
±10.0
JJ.A
V,N = O.4V to 2.4V
Vee = 5.2SV
V
ILOAD = -100 fJoA
Vee = 475V
V
Vee = 4.75V
ILOAD = 1.6 rnA
0.4
= SV
Ve~ = SV
= O·C
R6551
Asynchronous Communications Interface Adapter (ACIA)
PACKAGE DIMENSIONS
28-PIN CERAMIC DIP
28-PIN PLASTIC DIP
I
(,5501
1.5301
L.M-nTTTrrrrTTTTT"lTTTTT"l.,.,.....,.....~
::=:--'~';R' ,." ~It+--~.Itr=:iT:1-,.,.
jt
~T L
(.1151
(~I
114701
-(1_1-·
1.11011
I I L'.!!'! ~:::::--l
---I 1--(....1
( 1651 (.0051
I-I
(.0861
-
I I
~
(....1
-1 I~I .032AEF ~
( 0861
( 0151
(.1211 (.0151
6-184
( 0901
\ "\
(.1501 (0601
(1211 (0201
(.7001 .. __ -'
(.6OO1-------,
(0081
R65C51
'1'
R65C51
Asynchronous Communications
Interface Adapter (ACIA)
Rockwell
DESCRIPTION
FEATURES
The Rockwell CMOS R65C51 Asynchronous Communications
Interface Adapter (ACIA) provides an easily implemented, program controlled interface between 8-bit microprocessor-based
systems and serial communication data sets and modems.
•
•
•
•
•
•
The ACIA has an internal baud rate generator. This feature
eliminates the need for multiple component support cirCUits, a
crystal being the only other part reqUired. The Transmitter baud
rate can be selected under program control to be anyone of
15 different rates from 50 to 19,200 baud, or '1,6 times an external clock rate. The Receiver baud rate may be selected under
program control to be either the Transmitter rate, or at '1,6 times
an external clock rate. The ACIA has programmable word
lengths of 5, 6, 7, or 8 bits; even, odd, or no parity; 1, 11'2, or
2 stop bits.
•
•
•
•
•
•
•
•
The ACIA is designed for maximum programmed control from
the microprocessor (MPU), to simplify hardware Implementation.
Three separate registers permit the MPU to easily select the
R65C51 's operating modes and data checking parameters and
determine operational status.
vss
AIW
cso
02
IAQ
07
CS1
AES
AxC
06
XTLI
D5
D4
XTLO
RTS
•
lrill;;;
~ ~I~ 1°
a:oo>a:o!5
00
¢
XTLI
XTLO
DO
OSR
ASO
RS1
OCD
CD .... to
II
NOON
PIN 1
INDICATOA
25
24
07
D6
23
22
D5
CTS
21
TxD
DTA
20
D2
19
D1
~~;!!2~t:=
co .... (.)1°10:: 0
~~~~g~o
28-PIN PLCC
28-PIN DIP
Document No. 29651 N60
....
0
D4
D3
Vee
Figure 1.
C'\I
ATS
01
DTR
AxD
C")
AxC
D3
D2
CTS
TxD
Low power CMOS N-well silicon gate technology
Replacement for NMOS R6551 ACIA
Full duplex operation with buffered receiver and transmitter
Data sel/modem control functions
Internal baud rate generator with 15 programmable baud
rates (50 to 19,200)
Program-selectable internally or externally controlled receiver
rate
Programmable word lengths, number of stop bits, and parity
bit generation and detection
Programmable Interrupt control
Program reset
Program-selectable serial echo mode
Two chip selects
1 or 2 MHz operation
5.0 Vdc ± 5% supply reqUirements
Wide range of packages available
- 28-pin ceramic or plastic DIP
- 28-pm plastic leaded chip carner (PLCC)
Full TTL compatibility
Compatible With R6500, R6500" and R65COO microprocessors
R6SCS1 ACIA Pin Assignments
Product Description
6-185
Order No. 2157
Rev_ 5, June 1987
R65C51
Asynchronous Communications Interface Adapter (ACIA)
ORDERING INFORMATION
Data Bus (00-07)
The eight data line (00-07) pins transfer data between the
processor and the ACIA. These lines are bi-directional and are
normally high-impedance except during Read cycles when the
ACIA is selected.
Part Number:
R65C51
L
Chip Selects (CSO, CS1)
Frequency
1 = 1 MHz
2 = 2 MHz
The two chip select inputs are normally connected to the processor address lines either directly or through decoders. The ACIA
is selected when CSO is high and CS1 is low. When the
ACIA is selected, the internal registers are addressed in
accordance with the register select lines (RSO, RS1).
Package
C = 28-Pin Ceramic DIP
P = 28-Pm Plastic DIP
J = 28-Pin Plastic Leaded
Chip Carrier (PLCC)
Register Selects (RSO, RS1)
The two register select lines are normally connected to the processor address lines to allow the processor to select the various
ACIA internal registers. Table 1 shows the internal register select
decoding.
INTERFACE SIGNALS
Figure 1 (front page) shows the RS5C51 ACIA pin assignments
and Figure 2 groups the signals by functional Interface_
Table 1.
ACIA Register Selection
Register Operation
MICROPROCESSOR INTERFACE
RS1
RSO
RIW = Low
L
L
Wnte Transmit Data
Register
Read Receiver
Data Register
L
H
Programmed Reset
(Data IS "Don't
Care")
Read Status
Register
H
L
Write Command
Register
Read Command
Register
H
H
Write Control
Register
Read Control
Register
Reset (RES)
During system initialization, a low on the RES input causes a
hardware Reset to occur. Upon Reset, the Command Register
and the Control Register are cleared (all bits set to 0). The Status Register is cleared with the exception of the indications of
Data Set Ready and Data Carrier Detect, which are externally
controlled by the DSR and DCD lines, and the Transmitter Empty
bit, which is set. RES must be held low for one 02 clock cycle
for a reset to occur.
RIW = High
The Command Register controls parity, receiver echo mode,
transmitter interrupt control, the state of the RTS line, receiver
interrupt control, and the state of the DTR line,
Input Clock (02)
The input clock is the system 02 clock and clocks all data transfers between the system microprocessor and the ACIA.
The Control Register controls the number of stop bits, word
length, receiver clock source, and baud rate,
Read/Write (R/W)
The Status Register indicates the states of the IRQ, DSR, and
DCD lines, Transmitter and Receiver Data Registers, and Overrun, Framing, and Parity Error conditions,
The Rm input, generated by the microprocessor controls the
direction of data transfers. A high on the Rm pin allows the
processor to read the data supplied by the ACIA, a low allows
a write to the ACIA.
The Transmitter and Receiver Data Registers are used for
temporary data storage by the ACIA Transmit and Receive
circuits,
Only the Command and Control registers can be both read and
written, The programmed Reset operation does not cause any
data transfer, but is used to clear bits 4 through 0 in the Command register and bit 2 in the Status Register, The control
Register is unchanged by a programmed Reset. It should be
noted that the programmed Reset is slightly different from the
hardware Reset (RES); refer to the register description,
Interrupt Request (IRQ)
The IRQ pin is an interrupt output from the interrupt control logic
It is an open drain output, permitting several devices to be connected to the common IRQ microprocessor input. Normally a
high level, IRQ goes low when an interrupt occurs.
6-186
R65C51
Asynchronous Communications Interface Adapter (ACIA)
CTS
TxD
IRQ
MICROPROCESSOR
INTERFACE
RtW
DCD
CSO
DSR
CSl
RxC
RSO
XTLI
RSl
XTLO
MODEM
INTERFACE
112
DTR
RES
RTS
VCC
RxD
VSS
Figure 2.
ACIA Interface Diagram
ACIA/MOOEM INTERFACE
mode results If the internal baud rate generator is selected for
receiver data clocking.
Crystal Pins (XTU, XTLO)
Request to Send (RTS)
These pins are normally directly connected to a parallel mode
external crystal (1.8432 MHz) to derive the various baud rates.
Note that capacitors are required from XTU to ground and from
XTLO to ground. Alternatively, an externally generated clock can
drive the XTU pin, in which case the XTLO pin must float.
The RTS output Pin controls the modem from the processor.
The state of the RTS Pin is determined by the contents of the
Command Register.
Clear to Send (CTS)
Transmit Data (TxO)
The CTS input pin controls the transmitter operation. The enable
state is with CTS low. The transmitter is automatically disabled
if CTS is high.
The TxD output line transfers serial non-return-to-zero (NRZ) data
to the modem. The least significant bit (LSB) of the Transmit
Data Register is the first data bit transmitted and the rate of data
transmission is determined by the baud rate selected or by an
external transmitter clock. This selection is made by programming the Control Register.
Data Terminal Ready (OTR)
ThiS output pin indicates the status of the ACIA to the modem.
A Iowan DTR indicates the ACIA is enabled, a high indicates
It IS disabled. The processor controls this pin via bit 0 of the Command Register.
Receive Data (RxO)
The RxD Input line transfers serial NRZ data into the ACIA from
the modem, LSB first. The receiver data rate IS determined by
the programmed baud rate or by an externally generated receiver
clock. The selection is made by programming the Control
Register.
Data Set Ready (OSR)
The DSR input pin indicates to the ACIA the status of the modem.
A low indicates the "ready" state and a high, "not-ready."
Data Carrier Detect (OCD)
Receive Clock (RxC)
The DCD Input pin indicates to the ACIA the status of the carrierdetect output of the modem. A low indicates that the modem
carner signal is present and a high, that it is not.
RxC IS a bi-directional pin which is either the external receiver
clock input or a clock output of 16x the baud rate. The latter
6-187
•
Asynchronous Communications Interface Adapter (ACIA)
R65C51
FUNCTIONAL DESCRIPTION
TIMING AND CONTROL
A block diagram of the R65C51 ACIA IS presented in Figure 3.
A description of each functional element of the device follows.
The Timing and Control logic controls the timing of data transfers on the internal data bus, the registers, the Data Bus Buffer,
the microprocessor data bus, and the hardware reset.
DATA BUS BUFFERS
Timing is controlled by the system 02 clock input. The chip will
perform data transfers to or from the microcomputer data bus
durmg the 02 high period when selected.
The Data Bus Buffer Interfaces the system dala lines 10 the
internal data bus. The Data Bus Buffer IS bi-directlonal. When
the RIW line is low and the chip is selected, the Data Bus Buffer
writes the data from the system data lines to the ACIA internal
data bus. When the Riw line IS high and the chip is selected,
the Data Bus Buffer drives the data from the internal data bus
to the system data bus.
All registers Will be initialized by the Tlmmg and Control Logic
when the Reset (RES) line goes low. See the individual register
deSCription for the state of the registers following a hardware
reset.
INTERRUPT LOGIC
The Interrupt Logic will cause the IRQ line to the microprocessor
to go low when conditions are met that require the attention of
the microprocessor. The conditions which can cause an interrupt will set bit 7 and the appropriate bit of bits 3 through 6 m
the Status Register, if enabled. Bits 5 and 6 correspond to the
Data Carrier Detect (DCD) logic and the Data Set Ready (DSR)
logic. Bits 3 and 4 correspond to the Receive Data Register full
and the Transmitter Data Register empty conditions. These con·
ditions can cause an interrupt request if enabled by the Com·
mand Register.
TRANSMITTER AND RECEIVER DATA REGISTERS
These registers are used as temporary data storage for the ACIA
Transmit and Receive circuits. Both the Transmitter and
Receiver are selected by a Register Select 0 (RSO) and Register
Select 1 (RS1) low condition. The Read/Write (RIW) line determines which actually uses the internal data bus; the Transmitter
Data Register is write only and the Receiver Data Register is
read only.
Bit 0 is the first bit to be transmitted from the Transmitter Data
Register (least significant bit first). The higher order bits follow
m order. Unused bits in this register are "don't care" bits.
1/0 CONTROL
The I/O Control Logic controls the selection of internal registers
for a data transfer on the internal data bus and the direction of
the transfer to or from the register.
The Receiver Data Register holds the first received data bit in
bit 0 (least significant bit first). Unused high-order bits are "0".
Parity bits are not contained in the Receiver Data Register. They
are stripped off after being used for parity checking.
The registers are selected by the Register Select (RS1, RSO)
and ReadlWrite (RIW) lines as shown in Table 1.
00·07
<:::::::::::>1
TxO
IRQ---I
Riw
--_;=====,
CSO--_..f
CS1 - - - . /
RSO--+i
-====:J=;,:::~==~
RS1
(12 RES
RxO
---I'1...::"=:':':::..J
Figure 3.
R65C51 ACIA Block Diagram
6-188
Asynchronous Communications Interface Adapter (ACIA)
R65C51
Parity Error (Bit 0). Framing Error (Bit 1).
and Overrun (Bit 2)
STATUS REGISTER
The Status Register indicates the state of interrupt conditions
and other non-interrupt status information. The interrupt conditions are Data Set Ready and Data Carrier Detect translllOns,
Transmitter Data Register Empty and Receiver Data Register Full
as reported in bits 6 through 3, respectively. If any of these bits
are set, the Interrupt (IRQ) Indicator (bit 7) is also set. Overrun,
Framing Error, and Panty Error are also reported (bits 2 through
0, respectively).
7
6
5
4
3
2
None of these bits causes a processor interrupt to occur, but they
are normally checked at the time the Receiver Data Register IS
read so that the validity of the data can be verified. These bits
are self clearing (I.e., they are automatically cleared after a read
of the Receiver Data Register.)
Receiver Data Register Full (Bit 3)
o
This bit goes to a 1 when the ACIA transfers data from the
Receiver Shift Register to the Receiver Data Register, and goes
to a 0 (is cleared) when the processor reads the Receiver Data
Register.
PE
Bit 7
0
1
Interrupt (IRQ)
No interrupt
Interrupt has occurred
Bit 6
0
1
Data Set Ready (DSR)
DSR low (ready)
DSR high (not ready)
Bit 5
0
1
Data Carrier Detect (DCD)
DCD low (detected)
DCD high (not detected)
Bit 4
0
Transmitter Data Register Empty
Not empty
Empty
Bit 3
0
1
Receiver Data Register Full
Not full
Full
Bit 2
0
1
Overrun"
No overrun
Overrun has occurred
Bit 1
0
1
Framing Error"
No framing error
Framing error detected
Bit 0
0
1
Parity Error"
No parity error
Parity error detected
Transmitter Data Register Empty (Bit 4)
This bit goes to a 1 when the ACIA transfers data from the Transmitter Data Register to the Transmitter Shift Register, and goes
to a 0 (is cleared) when the processor writes new data onto the
Transmitter Data Register.
NOTE: There is a delay of approximately )1" of a bit time after
the TOR becomes emptylfull before this flag is updated.
Data Carrier Detect (Bit 5) and Data Set Ready (Bit 6)
These bits reflect the levels of the DCD and DSR inputs to the
ACIA. A 0 indicates a low level (true condition) and a 1 indicates
a high level (false). Whenever either of these inputs change state,
an Immediate processor interrupt (IRQ) occurs, unless bit 1 of
the Command Register (IRD) is set to a 1 to disable IRQ.
When the interrupt occurs, the status bits indicate the levels of
the inputs immediately after the change of state occurred. Subsequent level changes will not affect the status bits until after
the Status Register has been interrogated by the processor. At
that time, another interrupt will immediately occur and the status bits will reflect the new state. These bits are not automatically cleared (or reset) by an internal operation.
Interrupt (Bit 7)
* No interrupt occurs for these conditions
This bit goes to a 1 whenever an interrupt condition occurs and.
goes to a 0 (is cleared) when the Status Register is read.
Reset Initialization
6-189
•
Asynchronous Communications Interface Adapter (ACIA)
R65C51
CONTROL REGISTER
Selected Baud Rate (Bits 0, 1, 2, 3)
The Control Register selects the desired baud rate, frequency
source, word length, and the number of stop bits.
These bits select the Transmitter baud rate, which can be at y"
an external transmitter clock rate or one of 15 other rates controlled by the internal baud rate generator.
8
7
5
43210
If the Receiver clock uses the same baud rate as the transmitter(bit4-1), then RxC becomes an output (at 16xthe baud rate)
and can be used to slave other circuits to the ACIA. Figure 4
shows the Transmitter and Receiver layout.
WL
SBN
I WLO
WLl
Bit 7
o
1
1
Stop Bit Number (SBN)
1 Stop bit
2 Stop bits
1X. Stop bits
For WL - 5 and no parity
1 Stop bit
For WL
8 and parity
i4-..--RxD
=
Bits 6-5
Word Length (WL)
.!.~
No. Bits
0
0
1
1
0
1
0
1
Bit 4
0
1
8
7
6
5
XTLI*"-;"----"
Receiver Clock Source (RCS)
External receiver clock
Baud rate
XTLO
Bits 3-0
Selected Beud Rate (SBR)
~.£ ..!. ..Q.. Baud
0
0 o 0 TxC rate + 16*
1 50
0
0
1 0 75
0
0
0
0
1
1 109.92
0 1 o 0 134.58
1 o 1 150
0
1 1 0 300
0
0
1 1
1 600
1 0 O· 0 1200
1 0 o 1 1600
1 0
1
0 2400
1 0
1
1 3600
1
1
0 4800
1
1 o 1 7200
1
1
1 0 9600
1
1
1
1 19,200
o
* AND EXTERNAL TRANSMITTER CLOCK INPUT (TxC)
Figure 4.
Receiver Clock Source (Bit 4)
This bit controls the clock source to the Receiver. A 0 causes
the Receiver to operate at a baud rate of y" the external receiver
clock on pin RxC. A 1 causes the Receiver to operate at the
same baud rate as is selected for the transmitter.
o
Word Length (Bits 5, 6)
These bits determine the word length to be used (5, 6, 7 or 8 bits).
*XTLI is the input for the External Transmitter Clock (TxC)
Stop Bit Number (Bit 7)
Reset Initialization
76543210
I~I~I~I~I~I~I~I~I
TransmltterlRecelver Clock Circuits
::::,.,.::,
This bit determines the number of stop bits used. A 0 always
indicates one stop bit. A 1 indicates 1Y2 stop bits If the word length
is 5 with no parity selected, 1 stop bit if the word length is 8 with
parity selected, and 2 stop bits in all other configurations.
(RES)
6-190
Asynchronous Communications Interface Adapter (ACIA)
R65C51
COMMAND REGISTER
Data Terminal Ready (Bit 0)
The Command Register controls specific modes and functions.
This bit enables all selected interrupts and controls the state
of the Data Terminal Ready (OTR) line. A 0 indicates the
microcomputer system is not ready by setting the OTR line
high. A 1 indicates the microcomputer system is ready by setting the OTR line low. OTR also enables and disables the transm itter and receiver.
Bits 7-6
1. .§..
o
o
0
1
o
BitS
o
Bit 4
o
1
Bits 3-2
3
2
o
1
1
0
1
1
"0 "0
Bit 1
o
1
Bit 0
o
1
Receiver Interrupt Control (Bit 1)
Parity Mode Control (PMC)
This bif disables the Receiver DCD and OSR from generating an interrupt when set to a 1. The Receiver DCO and OSR
interrupts are enabled when this bit is set to a 0 and Bit 0 is
set to a 1.
Odd parity transmitted/received
Even parity transmitted/received
Mark parity bit transmitted
Parity check disabled
Space parity bit transmitted
Parity check disabled
Transmitter Interrupt Control (Bits 2, 3)
These bits control the state of the Ready to Send (RTS) line and
the Transmitter interrupt.
Parity Mode Enabled (PME)
Parity mode disabled
No parity bit generated
Parity check disabled
Parity mode enabled
Receiver Echo Mode (Bit 4)
A 1 enables the Receiver Echo Mode and a 0 disables the
Receiver Echo Mode. When bit 4 is a 1 bits 2 and 3 must be
O. In the Receiver Echo Mode. the Transmitter returns each
transmission received by the Receiver delayed by one-half bit
time.
Receiver Echo Mode (REM)
Receiver normal mode
Receiver echo mode
Bits 2 and 3 must also be zero for receiver echo
mode, RTS will be low.
Parity Mode Enable (Bit 5)
This bit enables parity bit generation and checking. A 0 disables
parity bit generation by the Transmitter and parity bit checking
by the Receiver. A 1 bit enables generation and checking of
parity bits.
Transmitter Interrupt Control (TIC)
RTS
RTS
RTS
RTS
=
=
=
=
High, transmitter disabled'
Low, transmit interrupt enabled
Low, transmit interrupt disabled
Low, transmit interrupt disabled,
transmit break on TxO"
Parity Mode Control (Bits 6, 7)
These bits determine the type of parity generated by the Transmitter. (even, odd, mark or space) and the type of parity check
done by the Receiver (even, odd, or no check).
Receiver Interrupt Request Disabled (IRD)
IRQ enabled (receiver)
IRQ disabled (receiver)
Reset Initialization
76543210
Data Terminal Ready (Dlli.
Data terminal not ready (OTR high)'
Data terminal ready (OTR low)
1~l!J~1 ~ I~ I~ I~ I~ I:~~:~=~::t (RES)
NOTE
'The transmitter is disabled immediately. The receiver
is disabled but will first complete receiving a byte in
process of being received.
"A "BREAK" is transmitted only after the end of a
character stream. If the Transmitter Data Register contains a character, the "BREAK" is not transmitted.
6-191
•
R65C51
Asynchronous Communications Interface Adapter (ACIA)
STATUS REGISTER OPERATION
Reset operates somewhat differently from the hardware Reset
(RES pin) and is described as follows:
Because of the special functions of the various status bits, there
is a suggested sequence for checking them. When an interrupt
occurs, the ACIA should be interrogated, as follows:
1. Internal registers are not completely cleared. Check register
formats for the effect of a program Reset on internal registers.
1. Read Status Register
2. The DTR line goes high immediately.
This operation automatic!!!l2lears Bit 7 (IRO). Subsequent
transitions on DSR and DCD will cause another interrupt.
3. Receiver and transmitter interrupts are disabled immediately.
2. Check IRO (Bit 7).in the data read from the Status Register
If IRO is low when the reset occurs,it stays low until serviced,
unless interrupt was caused by DCD or DSR transition.
If not set, the interrupt source is not the ACIA.
4. DCD and DSR interrupts are disabled immediately. If IRO is
low and was caused by DCD or DSR, then it goes high, also
DCD and DSR status bits subsequently will follow the input
lines, although no interrupt will occur.
3. Check DCD and DSR
These must be compared to their previous levels, which must
have been saved by the processor. If they are both 0 (modem,
"on-line") and they are unchanged, then the remaining bits
must be checked.
5. Overrun cleared, If set.
TRANSMITTER AND RECEIVER OPERATION
4. Check RDRF (Bit 3)
Check for Receiver Data Register Full.
Continuous Data Transmit
In the normal operating mode, the interrupt request output (IRO)
signals when the ACIA is ready to accept the next data word
to be transmitted. ThiS interrupt occurs at the beginning of the
Start BIt. When the processor reads the Status Register of the
ACIA, the interrupt is cleared.
5. Check Parity, Overrun, and Framing Error (Bits 0-2) if the
Receiver Data Register is full.
6. Check TORE (Bit 4)
Check for Transmitter Data Register Empty.
The processor must then identify that the Transmit Data Register
is ready to be loaded and must then load it with the next data
word. This must occur before the end of the Stop Bit, otherwise
a continuous "MARK" will b~ transmitted. Figure 5 shows the
continuous Data Transmit timing relationship.
PROGRAM RESET OPERATION
A program Reset occurs when the processor performs a write
operation to the ACIA with RSO low and RS1 high. The program
CHAR#n+1
CHAR#n
t·
TxD
CHAR#n+3
CHAR#n+2
,,/
,,/
,,/
I
I
I
I
,I
I
I
I
/
"
lSt'''5"Gl~~ISEStopISt~t5"Gl~~ISE&Opl&'''5"Gl~~ISEStopls''''5"Gl~~EGStopL
Lru
iiffiU
Figure 5.
Continuous Data Transmit
6-192
I
l
R65C51
Asynchronous Communications Interface Adapter (ACIA)
Continuous Data Receive
Similar to the Continuous Data Transmit case, the normal
operation of this mode is to assert IRQ when the ACIA has
received a full data word. This occurs at about 9/,6 point through
the Stop Bit. The processor must read the Status Register and
CHAR#n+1
CHAR#n
iRa
CHAR#n+3
CHAR#n+2
'-/
'-/
"-
I
I
I
I
I
I
I
1
Lw
L
'-/
/
RxD
read the data word before the next interrupt, otherwise the
Overrun condition occurs. Figure 6 shows the continuous Data
Receive Timing Relationship.
ls.".5F] ~ ~ hl:Js.+"rt5F] ~ ~ [ill s.oiSto"[%fRi] ~ ~ ~ ~ ~ lilO:.}opL
~
)
PROCESSOR
INTERRUPT OCCURS
ABOUT 9/16 INTO
LAST STOP BIT.
PARITY, OVERRUN,
AND FRAMING ERROR
Ulr
l
"-'\
'LID
~
PROCESSOR MUST READ
RECEIVER DATA IN THIS
TIME INTERVAL, OTHERWISE,
OVERRUN OCCURS
PROCESSOR READS ~TUS
~g~I~~!~. CAUSES IRQ
ALSO,UPDATED
Figure 6.
Continuous Data Receive
Transmit Data Register Not Loaded by Processor
If the processor is unable to load the Transmit Data Register in
the allocated time, then the TxD line goes to the "MARK" condition until the data is loaded. IRQ interrupts contlnLe to occur
at the same rate as previously, except no data is transmitted.
CONTINUOUS "MARK"
CHAR#n
CHAR#n+1
CHAR#n+2
I
~~-,--'-~-------
Rs..rt5Fl~ ~ 5l:J s,opl
/
TxD
When the processor finally loads new data, a Start Bit immediately occurs, the data word transmission is started, and another
interrupt is initiated, signaling for the next data word. Figure 7
shows the timing relationship for this mode of operation.
I
I_CHARACTER_I
TIME
---uI]'
'LlIJ--
\
~
PRoeLoR '-'
'"
INTERRUPT
FOR DATA
REGISTER
EMPTY
/
INTERRUPTS
CONTINUE AT
CHARACTER RATE,
EVEN THOUGH
NO DATA IS
TRANSMITTED
PROCESSOR
READS
STATUS
REGISTER
Figure 7.
WHEN PROCESSOR FINALLY LOADS
NEW DATA, TRANSMISSION STARTS
iMMEDIATELY AND INTERRUPT
OCCURS, INDICATING TRANSMIT
DATA REGISTER EMPTY
Transmit Data Register Not Loaded by Processor
6-193
II
Asynchronous Communications Interface Adapter (ACIA)
R65C51
Effect of CTS on Transmitter
bit. Then TxD goes Immediately to a "MARK" condition. Bit 4 in
the Status Register indicates that the Transmitter Data Register
is not empty and IRQ is not asserted. CTS is a transmit control line
only, and has no effect on the ACIA ReceiverOperation. Figure 8
shows the timing relationship for this mode of operation.
CTS is the Clear-to-Send signal generated by the modem. It is normally low (true state) but may go high in the event of some modem problems. When this occurs, the TxD line goes to the "MARK"
condition after the entire last character (including parity and stop
bit) has been transmitted, unless CTS goes high during the start
CHAR#.
CHAR#n+1
CONTINUOUS "MARK"
TxD
/
1IRliS NOT ASSERTED
AGAIN UNTIL
NOT CLEAR-TO-SEND
m
GOES lOW
CLEAR·TO-5END
CTS GOES HIGH, INDICATING MODEM IS NOT READY TO RECEIVE DATA. TxD GOES
TO "MARK" CONDITION AFTER COMPLETE CHARACTER IS TRANSMITTED.
Figure 8.
Effect of CTS on Transmitter
Effect of Overrun on Receiver
If the processor does not read the Receiver Data Register in the
allocated time, when the next interrupt occurs, the new data word
is not transferred to the Receiver Data Register, but the Overrun
CHAR#n
---...",/
RxP
I
status bit IS set. Thus, the Data Register will contain the last valid
data word received and all following data is lost. Figure 9 shows
the timing relationship for thiS mode.
CHAR#n+1
,,/
I
CHAR#n+2
,,/
'
CHAR#n+3
,,/
'
~~.{0~~ ~rnStipISt.rt5Fl~ ~ rnStlpl~.rtru~~ rnSti+M1REl~~ ~
~
PROCESSOR
INTERRUPT
FOR RECEIVER
DATA REOISTER
FULL
PROCESSOR
READS
STATUS
REGISTER
RECEIVER DATA REGISTER
NOT UPDATED, BECAUSE
PROCESSOR DID NOT READ
PREVIOUS DATA, OVERRUN
BIT SET IN STATUS
REGISTER
"---------.-~/~
OVERRUN BIT seT IN
STATUS REGISTER
Figure 9.
Effect of Overrun on Receiver
6-194
Asynchronous Communications Interface Adapter (ACIA)
R65C51
Echo Mode Timing
In Echo Mode, the TxD line re-transmits the data on the RxD
line, delayed by V2 of the bH time, as shown in Figure 10.
Figure 10. Echo Mode Timing
Effect of CTS on Echo Mode Operation
the Receiver Data Register is full in response to an IRQ, so the
processor has no way of knowing that the Transmitter has
ceased to echo. See Figure 11 for the timing relationship of this
mode.
In Echo Mode, the Receiver operation is unaffected by CTS,
however, the Transmitter is affected when CTS goes high, Le.,
the TxD line immediately goes to a continuous "MARK" condHion. In this case, however, the Status Request indicates that
CHAR#n
CHAR#n+1
CHAR#n+2
CHAR#n+3
NOT -CLEAR-TO-SEND
CONTINUOUS "MARK" UNTIL
~~
TxO
ffi
GOES LOW
~~TSGOESTO)
"FALSE" CONDITION
I
NORMAL
RECEIVER DATA
' - - - - - - - - - - - - - - - - REGISTER FULL - - - - - - - - - - - - - - '
INTERRUPTS
Figure 11. Effect of CTS on Echo Mode
6-195
•
R65C51
Asynchronous Communications Interface Adapter (ACIA)
Overrun in Echo Mode
~ Overrun occurs in Echo Mode, the Receiver IS affected the
same way as a normal overrun in Receive Mode. For the retransmitted data, when overrun occurs, the TxD line goes to the
"MARK" condition until the first Start Bit after the Receiver Data
Register is read by the processor. Figure 12 shows the timing
relationship for this mode.
CHARtt'x+1
CHAR#x
IB, If
)-L----L---'
\ jr-------'LJI]
LJlJ
TxD
.....---1._.......- - '
!
I
TxD DATA
PROCESSOR FINALLY
RESUMES
READS RECEIVER
DATA REGISTER,
LAST VALID
CHARACTER (#n)
PROCESSOR
INTERRUPT
FOR CHAR#x
IN RECEIVER
DATA REGISTER
PROCESSOR
INTERRUPT
FOR RECEIVER
DATA REGISTER
FULL
PROCESSOR
READS
OVERRUN OCCURS
TxD GOES TO
"MARK"
CONDITION
STATUS
REGISTER
~~~
Figure 12.
Overrun in Echo Mode
Framing Error
Framing Error is caused by the absence of Stop Sitts) on
received data. A Framing Error is indicated by the setting of bit 1
in the Status Register at the same time the Receiver Data
Re~er Full bit is set, also in the Status Register. In response
to IRQ, generated by RDRF, the Status Register can also be
checked for the Framing Error. Subsequent data words are
tested for Framing Error separately, so the status bit will always
reflect the last data word received. See Figure 13 for Framing
Error timing relationship.
RxD
IEXPECTEDI - ' ' -....._
...
RxD
(ACTUAL)
NOTES
PROCESSOR
INTERRUPT,
FRAMING
ERROR
BIT seT
1. FRAMING ERROR DOES NOT
INHIBIT RECEIVER OPERATION.
2. IF NEXT DATA WORD IS OK,
FRAMING ERROR IS CLEARED.
Figure 13.
Framing Error
6-196
R65C51
Asynchronous Communications Interface Adapter (ACIA)
Effect of DCD on Receiver
DCD is a modem output indicating the status 01 the carrier-Irequency-detection circuit 01 the modem. This line goes high lor
a loss 01 carrier. Normally, when this occurs, the modem will
stop transmitting data some time later. The ACIA asserts IRQ
whenever DCD changes state and indicates this condition via
bit 5 in the Status Register.
Once such a change 01 state occurs, subsequent transitions will
not cause interrupts or changes in the Status Register until the
lirst interrupt is serviced. When the DCD input is high. the
receiver is disabled (see Figure 14).
CONTINUOUS "MAAK"
t
NORMAL
PROCESSOR
INTERRUPT
PROCESSOR
INTERRUPT
FOR 6Co
GOING HIGH
AS LONG AS
DCDISHIGH.
NO FURTHER
INTERRUPTS
FOR RECEIVER
WILL OCCUR
NO INTERRUPT
PROCESSOR
WILL OCCUR
HERE. SINCE
INTERRUPT
RECEIVER IS NOT
FORDCD
GOING LOW
ENABLED UNTIL
FIRST START BIT
DETECTED
PROCESSOR /
INTERRUPT
FOR
RECEIVER
DATA
Figure 14. Effect of DeD on Receiver
Timing with 1112 Stop Bits
R is possible to select 1V2 Stop Bits, but this occurs only for
5-bit data words with no parity bit. In this case, the IRQ asserted
lor Receiver Data Register Full occurs halfway through the
trailing hall-Stop Bit. Figure 15 shows the timing relationship lor
this mode.
CHAR#n
•
CHAR#n+'
RxD
UJ
t
PROCESSOR INTERRUPT
OCCURS HALFWAY
THROUGHT THE 1/2
STOP BIT
Figure 15. Timing with 1'12 Stop Bits
6-197
L
Asynchronous Communications Interface Adapter (ACIA)
R65C51
Transmit Continuous "BREAK"
NOTE
This mode is selected via the ACIA Command Register and
causes the Transmitter to send continuous "BRE'AK" characters, beginning with the next character transmitted. At least one
full "BREAK" character will be transmitted, even if the processor
quickly re-programs the Command Register transmit mode.
Later, when the Command Register is programmed back to
normal transmit mode, an immediate Stop Bit will be generated
and transmission will resume. Figure 16 shows the timing relationship for this mode.
If, while operating in the Transmit Continuous "BREAK"
mode, the CTS should go to a high, the TxD will be
overridden by the CTS and will go to continuous "MARK"
at the beginning of the next character transmitted after the
CTS goes high.
,St.
P,
"'-/
/
~ r'-_A=6I]S:EJSt.+.~5I5l
1--+-;1
I
~
PERIOD DURING
I-------~-j_ ~EH~~~:sROCESSOR
CONTINUOUS
"BREAK" MODE
POINT AT WHICH
PROCESSOR
SELECTS
NORMAL
TRANSMIT
NORMAL
INTERRUPT
PROCESSOR
INTERRUPT
TO LOAD
TRANSMIT
DATA
/
MODE
Figure 16. Transmit Continuous "BREAK"
Receive Continuous" BREAK"
shows the timing
characters.
In the event the modem transmits continuous "BREAK" characters, the ACIA will terminate receiving. Reception will resume
only after a Stop Bit is encountered by the ACIA. Figure 17
-------~"
RxD
--1..:J __ L:.L....J
.,
CONTINUOUS "BREAK"
-r;:1- -I BNIPI StoplSt8l1
I'
a,
BO
I
I
BN
'-'
U
,
/
Stop
'I' (( I ( '
!T!
__
PROCESSOR INTERRUPT WITH
FRAMING ERROR SET. EVEN
RECEIVER
DATA REGISTER
FULL
ZEROS (CONTINUOUS BREAK)
REPRESENT EVEN PARITY.
INTERRUPTS
DISABLED UNTIL
FIRST STOP BIT
~:!:~:;:O:'~~S~ '::~
Figure 17.
Receive Continuous "BREAK"
6-198
,,/~----
I I
B,
~ L:.L...J 1- - - -
f-tJ:n
~~RE ~ :~~:e~~~R
~~TRERRUPT
for continuous "BREAK"
OStart~- -I BNIPI Stop Is.-,. I 8 0
1
1
PROCESSOR
P
relationship
U
!
:~:~
INTERRUPT
Asynchronous Communications Interface Adapter (ACIA)
R65C51
CRYSTAUCLOCK CONSIDERATIONS
CLOCK OSCILLATOR
The on-chip oscillator is designed for a parallel resonant crystal connected between XTLI and XTLO pins. The equivalent
oscillator circuit is shown in Figure 18.
To select a parallel resonant crystal for the oscillator, first select
the load capacitance from a crystal manufecturer's cetalog. Next,
calculate R..... based on F and CL. The selected crystal must
have a R. less than the R.max•
For example, if CL = 13 pF for a 1.8432 MHz parallel resonant
crystal, then
C = (2x13) - 2 = 18pF
The series resistance of the crystal must be less than
XTLI
1--4--~
2 pF
1
-l,; ~,
' -__
Rom.,. =
2 x 1()6
(1.8432 x 13)2
;: 3.3K ohms
EXTERNAL CLOCK MODES
The XTLI input may be used as an external clock input (Figure 19). For this implementation, a times 16 clock is input on
XTLI and XTLO is left open.
Figure 18. Internal Clock
EXTERNAL
TRANSMITTER
A parallel resonant crystal is specified by its load capacitance
and series resonant resistance. For proper oscillator oparation,
the load capacitance (CLl, series resistance (R.) and the crystal resonant frequency (F) must meet the following two relations:
CLOCK
N5CS1
NO CONNECTION
2 x 1()6
R. s R.max = (FCd2
Figure 19. External Clock
where: F is in MHz; C and CL are in pF; R is in ohms.
6-199
•
Asynchronous Communications Interface Adapter (ACIA)
R65C51
GENERATION OF NON·STANDARD BAUD RATES
Generating Non·Standard Baud Rates
Divisors
By using a different crystal, non-standard baud rates may be
generated. These can be determined by:
Baud Rate = Crystal Frequency
Divisor
The internal counter/divider circuit generates appropriate divisors to produce standard baud rates when a 1.8432 MHz crystal is connected between XTU and XTLO. Control Register bits
0-3 select the divisor for a particular baud rate as shown in
Table 2.
Table 2.
Control
Register
Bits
Baud Rate Generated
With 1.8432 MHz
Crystal
External Transmitter Clock Rate .;. 16
2
1
0
0
0
0
0
16
0
0
0
1
36,664
1
0
0
Divisor Selection
Divisor Selected
For The
Internal Counter
3
0
Furthermore, it is possible to drive the ACIA with an off-chip oscillator to achieve other baud rates. In this case, XTAU (pin 6) must
be the clock input and XTALO (pin 7) must be a no-connect.
0
1
Baud Rate Generated
With a Crystal
of Frequency (F)
External Transmitter Clock Rate _ 16
F
1.6432 x 10'
24,576
36,664
50
---
·75
---
36,664
F
1.6432 x 10·
24,576
0
,
24,576
F
1.8432 x lOS
1
16,769
109.92
-16,769
--
134.51
---
150
-12,288
--
300
-6,144
--
600
---
1,200
---
1,800
---
2,400
-768
--
3,600
-512
--
4,600
F
-364
-
7,200
-256
--
9,600
---
16,769
0
0
1
1
1.8432 x lOS
0
0
13,704
0
1
12,288
F
13,704
13,704
F
1.8432 x 10·
12,288
0
0
1
1
1
1
0
0
1
1
F
1.8432 x lOS
0
6,144
1
3,072
6,144
1.8432 x lOS
3,072
F
3,072
F
1.8432 x 10.
0
0
0
1,536
1
1,024
1,536
1,536
F
1.8432 x lOS
1,024
1,024
F
1.8432 x 10·
1
1
1
0
0
1
1
0
768
1
512
768
F
1.8432 x 10·
1
512
1.8432 x lOS
0
0
364
384
1
1
0
F
1.6432 x lOS
1
256
256
1
1
1
F
1.8432 x 10'
0
192
192
192
1
1
F
1.8432 x lOS
1
1
19,200
96
,
96
6-200
,
--96
Asynchronous Communications Interface Adapter (ACIA)
R65C51
DIAGNOSTIC LOOP-BACK OPERATING MODES
LLB may be tied to a peripheral control pin (from an R65C21
or R65C24, for example) to provide processor control of local
loop-back operation. In this way, the processor can easily perform local loop-back diagnostic testing.
It may be desirable to include in the system a facility for local
loop-back testing.
MISCELLANEOUS
In local loop-back testing, the Modem and Data Link must be
effectively disconnected and the ACIA transmitter connected
back to its own receiver, so that the processor can perform diagnostic checks on the system, excluding the actual data
channel.
1. If Echo Mode is selected, RTS goes low.
2. If Bit 0 of Command Register (DTR) is 0 (disabled), then:
a) All interrupts are disabled, including those caused by DCD
and DSR transitions.
The ACIA does not contain automatic loop-back operating
modes, but they may be implemented with the addition of a small
amount of external circuitry. Figure 20 indicates the necessary
logic to be used with the ACIA. The LLB line is the positive-true
signal to enable local loop-back operation. Essentially, LLB
high does the following:
b) Transmitter is disabled immediately.
c) Receiver is disabled, but a character currently being
received will be completed first.
=
3. Odd parity occurs when the sum of all the 1 bits in the data
word (including the parity bit) is odd.
1. Disables outputs TxD, DTR, and RTS (to Modem).
4. In the receive mode, the received parity bit does not go into
the Receiver Data Register, but generates parity error or no
parity error for the Status Register.
2. Disables inputs RxD, DCD, CTS, DSR (from Modem).
5. Transmitter and Receiver may be in full operation simultaneously. This is "full-duplex" mode.
3. Connects transmitter outputs to respective received inputs
(i.e., TxD to RxD, DTR to DCD, RTS to CTS).
I
A85C51
ATS DTATxD
LLB
AxDDCD CTS DSA
SEL
1YW
2Y
3Y
74157 4Y
I
I
STB
*
1B
2B
3B
*4B
' - - - BEL
.r
+5
t
-
STB
1A
2A
3A
4A
AxD
DCD
CTS
DSA
MODEM
TxD
1Y
2Y
3Y
D"i1i
iffiI
r-
74157 4Y
1B
1A
2B
2A
3B
3A
4B
4A f-
NOTES: 1. HIGH ON LLB SELECTS LOCAL LOOP·BACK MODE_
2_ HIGH ON 74157 SELECT INPUT GATES "B" INPUTS
TO "Y" OUTPUTS; LOW GATES "A" TO "Y".
Figure 20.
Loop·Back Circuit Schematic
6-201
•
Asynchronous Communications Interface Adapter (ACIA)
R65C51
6. If the RxD line inadvertently goes low and then high right after
a Stop Bit, the ACIA does not interpret this as a Start Bit,
but samples the line again halfway into the bit time to determine if it is a true Start Bit or a false one. For false Start Bit
detection, the ACIA does not begin to receive data, instead,
only a true Start Bit initiates receiver operation.
XTLI
(TRANSMIT
CLOCK INPUT)
7. DCD and DSR transitions, although causing immediate
processor interrupts, have no affect on transmitter operation.
Data will continue to be sent, unless the processor forces the
transmitter to turn off. Since these are high-impedance inputs,
they must not be permitted to float (un-connected). If unused,
they must be tied to GND.
TxO
----------------~
NOTE: TxO RATE IS 1/16 TxC RATE
Figure 21.
S. If TDRE is checked by polling (rather than by interrupt), a
period of at least y,. Baud clock should be allowed after loading Tx Data Buffer to ensure that TDRE is valid.
Transmit Timing with External Clock
1-
READ TIMING DIAGRAM
Timing diagrams for transmit with external clock, receive with
external clock, and IRQ generation are shown in Figures 21, 22
and 23, respectively. The corresponding timing characteristics
are listed in Table 3.
Table 3.
\
RxC
----.."
(INPUT)
_
1 MHz
L
NOTE: RxO RATE IS 1/16 RxC RATE
2 MHz
Figure 22.
Symbol
Min
Max
Min
Max
Unit
Transmit/Receive
Clock Rale
Iccy
400'
-
400'
-
ns
Transmit/Receive
Clock High Time
ICH
175
-
175
-
ns
Transmit/Receive
Clock Low Time
ICL
175
-
175
-
ns
XTLI 10 TxD
Propagation Delay
100
-
-
500
ns
RTS. DTR
Propagalion Delay
t OLY
IRQ Propagation
Delay (Clear)
t lRa
500
rl--'""i
!-tCL-:
Transmit/Receive Characteristics
Characteristic
tCCY-~-i
-
500
-
500
ns
-
500
-
500
ns
Receive External Clock Timing
\
\ir-jI
OTR, RTS
----------------~--j~
-_'t_IR~Qf_
IRQ
_ __________________
(CLEAR)
Noles:
(IR. IF = 1010 30 ns)
'The baud rale wilh external clocking
IS:
Baud Rale
=
1
Figure 23.
16 x Iccy
6-202
Interrupt and Output Timing
Asynchronous Communications Interface Adapter (ACIA)
R65C51
SWITCHING CHARACTERISTICS
= 5.0 Vdc ± 5%. Vss = O. TA = TL to TH.
(Vee
unless otherwise noted)
1 MHz
Parameter
Symbol
2 MHz
Min
Max
Min
Max
Unit
1000
-
500
-
ns
-
ns
02 Cycle Time
tCYC
02 Pulse Width
tc
400
Address Set-Up Time
tACW ' tACR
120
Address Hold Time
teAH' teAR
RIW Set-Up Time
twcw • t WCR
0
120
RIW Hold Time
tCWH
0
Data Bus Set-Up Time
tocw
150
Data Bus Hold Time
tHW
20
-
60
10
Read Access Time (Valid Data)
tcoR
-
200
-
170
ns
Read Hold Time
tHR
20
40
20
-
ns
tCOA
-
10
Bus Active Time (Invalid Data)
200
60
60
0
Notes:
1. tR and tF = 10 to 30 ns.
2. Timing measurements are referenced tolfrom a low of 0.8 volts and a high of 2.0
tR te
cfo2
ns
-
0
-
ns
ns
ns
ns
ns
ns
vo~s.
tc~c
+-tF
~
~
J
-tCAH-
-tACW-
twcw-
YIH
I-tcWH-1
I
.L~ ===:Y:':L
r-''''''
"'"
'r---.1
DATABUS~~--------------------~
I.
Write Timing Diagram
\
/
cfo2
,..-----yH
-tACRCSo• CS,. RSo• RS,
_C=t====t=-~~YIH
YIL
J-----r-------------~-----------------------YIH
R/W
l
/
~
DATABUS-----------tW-c-R-~~~-~tC~D~A~:~~~~DR~~~.~~lr_-_-_-_-_-_--~'t~H~R~:jJp------------------
~
----------------------------------------------------------------------~
Read Timing Diagram
6-203
•
R65C51
Asynchronous Communications Interface Adapter (ACIA)
ABSOWTE MAXIMUM RATINGS·
Parameter
Value
Unit
Supply Voltage
Vee
-0.3 to + 7.0
Vdc
Input Voltage
V'N
VOUT
-0.3 to Vee +0.3
Vdc
-0.3 to Vee +0.3
Vdc
Output Voltage
Symbol
Operating Temperature
Commercial
TA
Storage Temperature
TSTG
o to
·NOTE: Stresses above those listed may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in other sections of this document is not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
°C
+70
-55 to + 150
°C
OPERATING CONDITIONS
Parameter
Supply Voltage
Symbol
Value
Vee
5Vdc ±5%
TA
TL to TH
0° to 70°C
Temperature Range
Commercial
ELECTRICAL CHARACTERISTICS
(Vee = 5.0 Vdc ±5%, Vss = 0, TA = TL to TH ,
unless otherwise noted)
Parameter
Symbol
Input High Voltage
Except XTLI
XTLI
V'H
Input Low Voltage
Except XTLI
XTLI
V'L
Input Leakage Current:
02. RAN, RES,CSO. CS1, RSO, RS1,CTS, RxO, OCO, OSR
Min
Typ
Max
Unit
Test Conditions
V
2.0
2.8
-
Vee
Vee
-0.3
-0.3
-
+0.8
+004
I'N
-
±1
±2.5
pA
V'N = OV to Vee
Vee = 5.25V
Input Leakage Current (Three State Ofl)
00-07
ITS'
-
±2
±10
pA
V'N = OAV to 2.4V
Vee = 5.25V
Output High Voltage: _ _
00-07, TxO, RxC, RTS, OTR
VOH
204
-
-
V
Vee = 4.75V
ILOAD = -100 pA
Output Low Voltage:
00-07, TxO, RxC, RTS, DfR, IRQ
VOL
-
-
004
V
Vee = 4.75V
'LOAD = 1.6 mA
Output High Current (Sourcing):
00-07, TxO, RxC, RTS, DfR
IOH
-100
-400
-
~A
VOH = 2.4V
Output Low Current (Sinking):
00-07, TxO, RxC, RTS, OTR, IRQ
IOL
1.6
Output Leakage Current (off state): IRQ
IOFF
Power Dissipation
PD
-
Input Capacitance
02
All except 02
CeLK
C'N
-
Output Capacitance
COUT
-
V
Notes:
1. All units are direct current (dc) except for capacitance.
2. Negative sign indicates outward current flow, positive indicates inward flow.
3. Typical values are shown lor Vee = 5.0V and TA = 25°C.
6-204
-
-
mA
VOL = OAV
10
pA
VOUT = 5.0V
7
10
mW/MHz
-
-
20
10
pF
pF
-
10
pF
Vee = 5.0V
V'N = OV
1= 2 MHz
TA = 25°C
Asynchronous Communications Interface Adapter (ACIA)
R65C51
PACKAGE DIMENSIONS
28-PIN CERAMIC DIP
[
I-
D JTI
MILLIMETERS
14~
H~~D
MAX
A
35 05
G-ll-
K _J
M-j
..
A
•
--1Gf--
F
0
1420
1588
C
254
41.
D 100
0625
0165
038
053
0015
0021
F
076
127
0030
1S11
254
esc
K
esc
076
178
0030
0070
J
020
033
0008
K
254
41.
D 100
0013
0165
L
1460
O·
1537
10·
0575
M
O·
0605
10·
N
051
152
0020
0060
INCHES
DIM
MIN
MAX
MIN
MAX
A
36 32
3734
1430
1470
B
1346
1397
0530
0550
C
356
508
0140
0200
D
038
053
0015
0021
F
102
152
0040
H
M
0050
0100
H
G
cili
~f~
-+
~I-
1380
MILLIMETERS
I
[VVVVVVVOVOOO
MAX
3607
D
28-PIN PLASTIC DIP
rnn=OOOOOO]J
INCHES
MIN
0595
G
~n
iF
MIN
B
·1
A
DIM
254
esc
165
216
0065
J
020
330
030
432
0008
K
L
1524
esc
OOBO
0100
esc
0085
0012
0170
0130
0600
asc
M
7·
10"
7·
10"
N
051
102
0020
0040
28-PIN PLASTIC LEADED CHIP CARRIER (PLCC)
MILLIMETERS
re 1J
-'--- r""n'G ,. . .
~m
g
CORNER~ :cr=:,,~ I
INDEX
rrr~
1L
4
c
25
INo':~~+OR
Of02
11
1,8
SIDE VIEW
TOP VIEW
EJECTOR PIN MARKS
4 PlCS BOTTOM OF
PACKAGE ONLY
(TYPICAL)
t
CHAM.
hx45°
3 PlCS
b+IH re
~r81£!r=
','0~
=
~-:--=
E~"'
~ ~A
MIN
MAX
MIN
MAX
A
414
43.
0173
0097
Al
137
147
0163
0054
A2
231
246
0091
b
;2i50~
loln'n'n=
1237
1252
0487
114311153
0450
6-205
I 0493
I 0454
I 0303
02
754
D.
e
1067 REF
a 420 REF
asc
0050 SSC
h
'15 TYP
0045 TYP
J
025 TYP
0010 TYP
«
45° TYP
45° TYP
R
089 TYP
0035 TYP
Rl
025 TYP
0010 TYP
SECTION A-A
TYP FOR BOTH AXIS (EXCEPT FOR BEVELED EDGE)
CHAM.Jx45'
0058
0018 TYP
0
R •
BOTTOM VIEW
0457 TYP
01
~
~
INCHES
DIM
127
770
0297
•
R65C52
'1'
Rockwell
R65C52
Dual Asynchronous Communications
Interface Adapter (DACIA)
DESCRIPTION
FEATURES
The Rockwell CMOS R65C52 Dual Asynchronous CommunIcations Interface Adapter (DACIA) provides an easily implemented,
program controlled two-channel interface between 8-bit
microprocessor-based systems and serial communication data
sets and modems.
• Low power CMOS N-well silicon gate technology
The DACIA is designed for maximum programmed control from
the microprocessor (MPU) to simplify hardwere implementation.
Dual seta of registers allow independent control and monitoring
of each channel.
1tansmitter and Receiver bit rates may be controlled by an internal baud rate generator or external times 16 clocks. The baud rate
generator accepts either a crystal or a clock input, and provides
15 programmable baud rates. When a 3.6864 MHz crystal is used,
the baud rates range from 50 bps to 38,400 bps.
The DACIA may be programmed to transmit and receive frames
having word lengths of 5, 6, 7 or 8 bits; even, odd, space, mark
or no parity; and 1 or 2 stop bits.
A Compara Register, and the ability to detect address frames, facilitate address recognition in a multidrop mode.
• Two Independent full duplex channels with buffered receivers
and transmitters.
• Data setlmodem control functions
• Internal baud rate generator with 15 programmable baud rates
(50 bps to 38,400 bps)
• Program-selectable Internally or externally controlled receiver
and transmitter bit' rates
• Programmable word lengths, number of stop bits, and parity
bit generation and detection
• Programmable interrupt control
• Edge detect for DCD, DSR, and CTS
• Program-selectable echo mode for each channel
• Compare Register
• AddresslData frame recognition
• 5.0 Wc ± 5% supply requirements
• 4O-pin plastic or ceramic DIP or 44-pin PLCC
• Full TTL or CMOS inputloutput compatibility
• Compatible with R6500 and R65COO microprocessors and
R65OOJ* microcomputers
ORDERING INFORMATION
Plrt Number:
R85C52
L
'---
Temperature Range (TL to TH):
Blank ..
O°C to + 70°C
E .. -40°C to +85°C
Frequency Range:
1 .. 1 MHz
2 = 2MHz
3 = 3MHz
Package
C .. 40-Pln Ceramic DIP
P .. 4O-Pin Plastic DIP
J .. 44-Pin Plastic Leaded
Chip Carrier (PLCC)
Document No. 68650N09
Product DeSCription
Order No. 2165
Rev. 6, January 1989
6-206
R65C52
Dual Asynchronous Communications Interface Adapter (DACIA)
INTERFACE SIGNALS
The DACIA is available in a 40-pin DIP or a 44-pin PLCC. Figure 1
shows the pin assignments for each package. The DACIA interface signals are shown in Figure 2. Table 1 contains a description
of each signal.
RES
NC
Vee
8iSSS~::~IS!ti~
cs
XTALI
RNi
RS2
XTAlO
ClK OUT
NC
CO"' ....
RS1
RSo
OSR2
NC
DSR1
DCD2
CTS2
RTS2
0
39
TxC
PIN 1
INDICATOR
38
37
Tx02
DTR2
10
11
36
35
IRQ2
em
12
13
34
RTS2
CTS2
DCD1
DSR1
15
33
32
31
30
29
DTR1
RxDl
DCD1
CTS1
RTS1
IRQ1
IRQ2
IRQ1
RTS1
RxD2
DTR2
RxD1
TxD2
DTR1
NC
TxC
Tx01
RxC
DO
D1
D2
D3
RSo
D7
D6
D5
D4
Vss
C")N_:::::~;~
AxC
Tx01
14
16
17
RxD2
DCD2
DSR2
NC
ClK OUT
aaCftO_Nf')..,"'CO .... CD
__ NNNNNNNNN
- NI;tlfl
~ I ~
<>UI"' U:J 0 U
~z
I! z
~ ~
)(
Z
)(
44-PIN PLCC
4G-PIN DIP
NC = NO CONNECTION. NO SIGNAL SHOULD BE CONNECTED TO THIS PIN.
Figure 1.
~
IRQ1
RIW
CS
RES
R6500
BUS
ACIA1
REGISTERS
AND
CONTROL
LOGIC
ACIA1
INTERRUPT
LOGIC
<....
A.
DATA
BUS
BUFFERS
.......
00-07)
.....
~
CLOCK
LOGIC
I
DATA
I/O
MUX
I
ACIA2
INTERRUPT
LOGIC
Figure 2.
CTS1
DCD1
DSR1
Rx01
Tx01
DTR1
RTS1
}
ACIA
CHANNEL 1
•
ACIA1 BAUD
RATE SELECT
I/O CONTROL
AND
REGISTER
SELECT
LOGIC
RSO
RS1
RS2
IRQ2
R65C52 Pin Assignments
ACIA2 BAUD
RATE SELECT
ACIA2
REGISTERS
AND
CONTROL
LOGIC
R65C52 DACIA Interface Signals
6-207
RxC
XTALI
CLKOUT
XTALO
TxC
RTS2
OTR2
Tx02
Rx02
DSR2
DC02
CTS2
}
ACIA
CHANNEL 2
Dual Asynchronous Communications Interface Adapter (DACIA)
R65C52
Tilble 1. DACIA Interface Signal Definitions
PinNa.
Signal
DIP
PLCC
I/O
Name/Description
Host Interface
RES
1
24
I
Re..t. Active low input controlling the reset function. This signal must be driven low for a minimum of
4 p.S for a valid reset to occur. It is driven high during normal operation.
Rm
38
20
I
Re.dIWrlte. Input controlling the direction of data transfer. It is driven low during write cycles, and Is
driven high at all other times.
CS
38
21
I
Chip Selset. Active low input enabling dl!!! transfers between the host CPU and the DACIA. The
DACIA latches register selects and the RIW input on the falling edge of CS. It latches Input data on
the rising edge of CS.
RSO-RS3
35-37
17-19
I
Reglatar Selset. Three inputs controlling access to the DACIA internal registers. Table 3 lists the
coding for each register.
00-03
04-07
24-21
19-16
6-3
44-41
I/O
Data Bus. Eight bidirectional lines used to transfer data between the host and the DACIA. These lines
output data during READ cycles when CS is low. At all other times, they are in the high impedance
state.
29
11
35
0
11
Interrupt Request. Two active low, open-drain outputs from the Interrupt control logic. These outputs
are normally high. An IRQ line goes low when one of the flags of the associated ISR is set if the
corresponding enable b~ is set in the IER.
XTALI
XTALO
3
4
26
27
I
0
Cryatallnput/Output. One input and one output through which the reference signal for the internal
clock oscillator is supplied. A parallel resonant crystal may be connected acroas the pins or a clock
may be input at XTALI. When a clock Is used, XTALO must be left open.
CLKOUT
5
29
0
Clock Out. A buffered output from the Internal clock oscillator which is in phase with XTALI. This
output may be used to drive the XTALI input of another DACIA. Therefore, several DACIA chips may
be driven with one crystal.
RxC
25
7
I
Receiver Clock. Input for external 16x receiver clock.
TxC
15
39
I
lIansmllter Clock. Input for external16x transmitter clock.
IRQl
IRQ2
Clock Interface
Serial Chllnnellnterface
DTRI
DTR2
27
13
9
37
0
Data llIrmlnel Ready. Two general purpose outputs which are set high upon reset. The output
level is programmed by setting the appropriate b.!!..!!! the associated Format Register (FR) high or
low. The state of each DTR line is reflected by the DTR LVL bit In the associated Control Status Register
(CSR).
DSRI
DSR2
33
15
31
I
7
Date Set Ready. Two general purpose inputs. An active transition sets the DSRT bH In the Interrupt
Status Register (ISR). The DSR LVL bit in the associated CSR reflects the current state of a DSR line.
RTSI
RTS2
30
10
12
34
0
Request To Send. Two general purpose outputs which are set high upon reset. The output level is
programmed by setting the appropriate bit In the associated FR high or low. The stata of an RTS line is
reflected by the RTS LVL bit in the associated CSR.
CTSI
CTS2
31
9
13
I
33
Clear To Send. The CTS control line inputs allow handshaking by the transmitters. When CTS Is low,
the data is transmitted continuously. When CTS is high, the Transmit Data Register Empty bit (TORE)
in the associated ISR is not set. The word presently in the Transmit Shift Register is sent normally.
Any active transition on a CTS line sets the CTST bH In the appropriate ISR. The CTS LVL bit in the
associated CSR reflects the current state of CTS.
TxDl
TxD2
26
14
8
38
0
lIanamlt Data. The TxD outputs transfer serial non-nsturn to zero (NRZ) data to the data communications
equipment (DCE). The data Is transferred, LSB first, at a rste determined by the baud rate generator
or extern8J clock.
DCDI
DCD2
32
8
14
32
I
Data Carrier Detect. Two general purpose inputs. An active transHion sets the DCDT bit In the
appropriate ISR. The DCD LVL bit in the associated CSR reflects the current state of a DCD line.
RxDl
RxD2
28
12
10
38
I
Receive Data. The RxD inputs transfer serial NRZ data into the DACIA from the DCE, LSB first. The
receiver baud rate is determined by the baud rate generator or external clock.
VCC
40
22
I
DC Power Input. 5.OV ± 5%.
VSS
20
1
I
Power and Signal Reference.
Power
6-208
R65C52
Dual Asynchronous Communications Interface Adapter (DACIA)
FUNCTIONAL DESCRIPTION
Figure 3 is a block diagram of the DACIA which consists of two
asynchronous communications interface adapters with common
microprocessor interface control logic and data bus buffers. The
individual functional elements of the DACIA are described in the
following paragraphs.
RESET LOGIC
The Reset Logic sets various intarnal registers, status bits and control lines to a known state. The RES input must be driven low
for a minimum of 4 fl5 for a valid reset to occur. At this time, the
IERs are set to $80, the RDRs and ACRs are cleared, and the compare mode is disabled. Also, the DTR and RTS outputs are
driven high and the CTS, DCD and DSR transition detect flags
are cleared. No other bits are affected.
DATA BUS BUFFER
The Data Bus Buffer is a bidirectional interface between the data
lines and the internal data bus. The state of the Data Bus Buffer
is controlled by the 110 Control Logic and the Interrupt Logic.
Table 2 summarizes the Data Bus Buffer states.
is transferred from the internal data bus to the data lines. When
CS is high, the DACIA is deselected and the data lines are
tri-stated.
INTERRUPT LOGIC
The interrupt logic causes the IRQ lines (IRQ1 or IRQ2) to go
low when conditions are met that require the attention of the MPU.
There are two registers (the Interrupt Enable Register and the Interrupt Status Register) involved in the control of interrupts in the
DACIA. An IRQ will be asserted on the transition of one of the flags
in an ISR from 0 to 1 ifthe corresponding bit in the associated IER
is set. The IRQ line is negated when the ISR is read or when the
interrupting condition is cleared. CAUTION: When the interrupt
is generated by TORE, 1116 of a bit time must elapse before IRQ
can be cleared by reading the ISR.
CLOCK OSCILLATOR LOGIC
The internal clock oscillator supplies the time base for the baud
rate generator. The oscillator can be driven by a crystal or an external clock.
The baud rate generator may be disabled by connecting XTALI
to ground and leaving XTALO open. When this is done, a transmitter times 16 clock must be input at TxC, a receiver times 16 clock
must be input at RxC and the Control Registers must be
programmed to select TxC and RxC clocks.
Table 2.
1/0 CONTROL LOGIC
Data Bus Buffer Summary
Control Signals
RiW
CS
The 1/0 Control Logic controls data transfers between the Internal Registers and the Data Bus Buffer. Internal Register selection
is determined by the Register Select inputs as shown in Table 3.
When RIW is high and CS is low, data from the selected register
H
L
L
X
L
H
Dsta Bus Buffer Slate
Write Mode - Tri-State
Read Mode - Output Data
Deselected - Tn State
II
6-209
Dual Asynchronous Communications Interface Adapter (DACIA)
R65C52
TxOl
..0--------;
i'FiQ1'"
INTERRUPT
LOGIC
1-=
'------'-
ACIA CHANNEL 1
~~~Fl====----
OTRt
~~~~r-------- ~Sl
AKDt
DATA
hC
XTALI
ClKOUT
XTALO
R,C
RxD2
Pc~~~l_------. . . . ~
~~~~C===:~--""""~
ffi02 ...o-_ _ _ _~
RTS2
DTR2
ACIA CHANNEL 2
r~~~rt:=~:l~========CTS2
=
L.:::::::;:'::::"'j4---4~---- DCD2
LEGEND
-
= COMMON LOGIC
~~
= CONTROL LINES
~
t::) '"
Tx02
8·BIT DATA LINES
MUL 11·81T
Cg~TROL LINES
Figure 3.
DACIA Block Diagram
6-210
R65C52
Dual Asynchronous Communications Interface Adapter (DACIA)
Table 3.
Register Accessed
Register Select
Lines
HEX
RS2
RS1
Write
RSO
0
L
L
L
1
L
L
H
2
L
H
DACIA Register Selection
Read
Symbol
Name
IER1
Interrupt Enable
RegIster 1
CR1
Control
RegIster l'
FR1
Format
Register l '
CDR1
Compare Data
Register 13
ACR1
AUXIliary Control
RegIster 14
L
Symbol
Name
ISR1
Interrupt Status
Register 1
CSR1
Control Status
Register 1
Not Used
3
L
H
H
TDR1
TransmIt Data
RegIster 1
RDR1
ReceIve Data
Register 1
4
H
L
L
IER2
Interrupt Enable
RegIster 2
ISR2
Interrupt Status
RegIster 2
CR2
5
H
L
H
Control
RegIster 2'
CSR2
Control Status
RegIster 2
FR2
Format
RegIster 2'
CDR2
Compare Data
Register 23
ACR2
AUXIliary Control
RegIster 24
TDR2
TransmIt Data
RegIster 2
6
7
H
H
H
H
L
H
Not Used
RDR2
ReceIve Data
RegIster 2
Notes:
1. D7 must be set low to write to the Control RegIsters.
2. D7 must be set hIgh to write to the Format Registers.
3 Control Register bit 6 must be set to 0 to access the Compare RegIster.
4. Control Register bit 6 must be set to 1 to access the AUXIliary Control RegIster
II
6-211
Dual Asynchronous Communications Interface Adapter (DACIA)
R65C52
SERIAL DATA CHANNELS
is high and the Transmit Shift Register is empty, the transmitter
(except for Echo Mode) is inhibited. When CTS is low, the
transmitter is enabled.
Two independent serial data channels are available for the full
duplex (simultaneous transmit and receive) transfer of asynchronous frames. Separate internal registers are provided for each
channel for the selection of frame parameters (number of bits per
character, parity options, etc.), status flags, interrupt control and
handshake. The asynchronous frame format is shown in Figure 4.
----., - - , - --r---1---r
L j --T----tlN ______
I
START
Transmit data from the host system is loaded into the Transmit Data
Register. From there, it is transferred to the Transmit Shift Register
where it is shifted, LSB first, onto the TxD line. All transmissions
begin with a start bit and end with the user selected number of
stop bits. A parity bit is transmitted before the stop bites) if parity
is enabled.
J.I ___ lI __ -'I
I
I
LSB
\ ...
5 TO 8 BITS
Figure 4.
MSB
I
PARITY
(OPT)
IL __ J.._
I
STOP
I (1 OR 2 BITS)
I
-------+-1
Asynchronous Frame Format
INTERNAL REGISTERS
Receive data is shifted into the Receive Shift Register from the
associated RxD line. Start and stop bits are stripped from the frame
and the data is transferred to the Receive Data Register. Parity bits
may be discarded or stored in the ISR.
The DACIA contains ten control registers and four status registers
in addition to the transmit and receive registers. The Control
Registers provide for control of frame parameters, baud rate, interrupt generation, handshake lines, transmission and reception. The
status registers provide status information on transmit and receive
registers, error conditions and interrupt sources. Table 4 summarizes the bit definitions of these registers. A detailed description
follows.
Five I/O lines are provided for each channel for handshake with
the data communications equipment (DCE). Four of these signals
(ATS, DTR, DSR and DCD) are general purpose inputs or outputs.
The fifth signal, CTS, enables/disables the transmitter. When CTS
Table 4.
I ___ L
I ____
I
Register Formats
Reset
Value
76543210
Register
Select
(Hex)
Register
R/W
0
4
ISR1
ISR2
R
0
4
IER1
IER2
W
1
5
CSR1
CSR2
R
CR1
CR2
W
5
1
5
FR1
FR2
W
2
6
CDR1
CDR2
(CR6
2
6
ACR1
ACR2
(CR6
3
7
RDR1
RDR2
R
R~CEIVE DAfA REGIST~R
00000000
3
7
TDR1
TDR2
W
TR~NSMIT D+A REGIS~ER
--------
Bit
7
6
4
5
2
3
0
1 - 00000-
- 0000000
1 - -. - 011
0
CDRI
ACR
STOP
BITS
ECHO
DATA BITS
W
= 0)
W
= 1)
O· -. - - --
BITR+ESEL
I
1-------
PARSEL
COMPA~E DATA
I
UN~SED
6-212
------.TRNS
BRK
I
PAR
ERRIST.
- - - - - - 00
R65C52
Dual Asynchronous Communications Interface Adapter (DACIA)
INTERRUPT STATUS REGISTERS (ISR1, ISR2)
INTERRUPT ENABLE REGISTERS (IER1, IER2)
The Interrupt Status Registers are read-only registers indicating
the status of each interrupt source. Bits 6 through 0 are set when
the indicated IRQ condition has occurred. Bit 7 is setto a 1 when
any IRQ source bit is set, or if Echo Mode is disabled, when CTS
is high.
The Interrupt Enable Registers are write-only registers that
enable/disable the IRQ sources. IRQ sources are enabled by
writing to an IER with bit 7 set to a 1 and the bitfor every IRQ source
to be enabled set to a 1. IRQ sources are disabled by writing to
an IER with bit 7 reset to a 0 and the bit for every source to be disabled set to a 1. Any source bit reset to 0 is unaffected and remains
in its original state. Thus, writing $7F to an IER disables all of that
channel's interrupts and writing an $FF to an IER enables all of
that channel's interrllpts.
7
6
5
4
3
2
ANY
BIT
SET
TDRE
erST
DCDT
DSRT
PAR
Address
= 0,4
Bit 7
1
o
1
0
FIOIB RDRF
Reset Value
= 1 - 00000 -
Any Bit Set
Any bit (6 through 0) has been set to a 1 or ers
is high with echo disabled
No bits have been set to a 1 or echo is enabled
BitS
1
o
Transmit Data Register Empty (TORE)
Transmit Data Register is empty and ers is low
Transmit Data Register is full or ers is high
Bit 5
1
Transition On ers Line (CTST)
A positive or negative transition has occurred on
o
Bit 4
1
o
7
6
5
4
3
2
1
0
SET
BITS
TDRE
IE
erST
IE
DCDT
IE
DSRT
IE
PAR
IE
FIOIB
IE
RDRF
IE
Address = 0,4
Bit 7
1
o
1
o
Bit 2
1
o
1
Select for enable/disable
No change
o
CONTROL STATUS REGISTERS (CSR1, CSR2)
The Control Status Registers are read-only registers that provide
I/O status and error condition information. A CSR is normally read
after an IRQ has occurred to determine the exact cause of the
interrupt condition.
ers
No transition has occurred on CTS, or ISR has
been Read
Transition On DCD Line (DCDT)
A positive or negative transition has occurred on
DCD
No transition has occurred on DCD, or ISR has
been Read
7
6
5
4
3
2
1
0
FE
TUR
ers
LVL
DCD
LVL
DSR
LVL
BRK
DTR
LVL
RTS
LVL
Address
= 1,5
1
Transition On DSR Line (DSRT)
A positive or negative transition has occurred on
DSR
No transition has occurred on DSR, or ISR has
been Read
o
• Bit S
1
o
Bit 5
1
Parity Status (PAR)
ACRbitO
0
A parity error has occurred in received data
No parity error has occurred, or the Receive Data
Register (RDR) has been Read
ACR bit 0
1
Parity bit = 1
Parity bit = 0
=
o
1
Bit 1
1
o
Bit 0
1
o
CTS line is low
DSR Level (OSR LVL)
DSR line is high
DSR line is low
Bit 2
1
Receive Break (BRK)
A Receive Break has occurred
No Receive Break occurred, or RDR was read
Bit 1
1
OTR Level (DTR LVL)
DTR line is high
DTR line is low
Bit 0
1
RTS Level (RTS LVL)
RTS line is high
RTS line is low
o
o
6-213
ers Level (CTS LVL)
ers line is high
Bit 3
1
o
Receive Data Register Full (RDRF)
Receive Data Register is full
Receive Data Register is empty
Transmitter Underrun (TUR)
Transmit Shift Register is empty and TDRE is set
Transmitter Shift Register is not empty
OCD Level (DCD LVL)
DCD line is high
DCD line is low
o
Frame Error, Overrun, Break
A framing error, receive overrun, or receive break
has occurred or has been detected
No error, overrun, break has occurred or RDR
has been Read
Reset Value = 1 - - - - 011
Framing Error (FE)
A framing error occurred in receive data
No framing error occurred, orthe RDR was read
Bit 4
1
o
=
o
= - 0000000
Bits O-S
Bit 7
Bit 3
Reset Value
Enable/Disable
Enable selected IRQ source
Disable selected IRQ source
•
R65C52.
Dual Asynchronous Communications Interface Adapter (DACIA)
CONTROL REGISTERS (CR1, CR2)
FORMAT REGISTERS (FR1, FR2)
The Control Registers are write-only registers. They control access
to the Auxiliary Control Register and the Compare Data Register.
They select the number of stop bits. control Echo Mode, and select
the data rate.
The Format Registers are write-only registers. They select the
number of data bits per character and parity generation/checking
options. They also control RTS and DTR.
(Accessed when Bit 7 = 0)
7
o
20
CDR/ACR
Address
3
0
0
0
0
0
0
0
0
1
1
=
I~~; I
ECHO
I
1,5
BAUD RATE SEL
Control or Format Register
Access Control Register
Bit 6
1
0
COR/ACR
Access the Auxiliary Control Register (ACR)
Access the Compare Data Register (CDR)
Bit 5
1
0
Number of Stop Bits Per Character
Two stop bits
One stop bit
Bit 4
1
0
Echo Mode Selection
Echo Mode enabled
Echo Mode disabled
0
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
7
1
I
5
6
DATA
BITS
1
4
Bit 7
1
Bits 6-5
6 5
o 0
o
1
o
Bits 4-3
=1)
2
1
0
PAR
EN
DTR
CNTL
RTS
CNTL
3
PAR
SEL
Address = 1,5
Reset Value = 0 - - - - - --
Bit 7
0
Bits 3-0
2 1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
0 0
0 0
0 1
0 1
1 0
0
(Accessed when Bit 7
Reset Value = 1 - - - - - - -
Control or Format Register
Access Format Register
Number of Data Bits Per Character
5
6
7
8
Parity Mode Selection
4 3
o
o
Baud Rate Selection
(bits per second with 3.6864 MHz crystal)
50
109.2
134.58
150
300
600
1200
1800
2400
3600
4800
7200
9600
19200
38400
External TxC and RxC X16 Clocks
0
1
o
1
Bit 2
1
Parity Enable
Parity as specified by bits 4-3
No Parity
Bit 1
OTR Control
Set DTR high
Set DTR low
o
1
o
Bit 0
1
o
6-214
Odd Parity
Even Parity
Mark in Parity bit
Space in Parity bit
RTS Control
Set RTS high
Set RTS low
Dual Asynchronous Communications Interface Adapter (DACIA)
R65C52
OPERATION
COMPARE DATA REGISTERS (CDR1, CDR2)
The Compare Data Registers are write-only registers which can
be accessed when CR bit6 = o. By writing a value into the CDR,
the DACIA is put in the compare mode. In this mode, setting ofthe
RDRF bit is inhibited until a character is received which matches
the value in the CDR. The next character is then received and the
RDRF bit is set. The raceiver will now operate normally until the
CDR is again loaded.
(Control Register bit 6
7
6
5
4
TERMINATION OF UNUSED INPUTS
Noise on floating inputs can affect chip operation. All unused
inputs must be terminated. Ifthe baud rate generator is bypassed,
XTALI must be connected to ground (XTALO is an output and
must be left open). If the external clock mode is not used, RxC
and TxC may be tied either to + 5V or to ground. If the handshake
inputs are not needed, the CTS Inputs should be tied low to
enable the transmitters. The DCD and DSR inputs may either be
tied high or low.
= 0)
3
o
2
COMPARE DATA
Address
= 2,6
Reset value = - - - - - - - -
RESET INITIALIZATION
AUXILIARY CONTROL REGISTERS (ACR1, ACR2)
The Auxiliary Control Registers are write-only registers. Bits 7-2
are unused. Bit 1 causes the transmitter to transmit a BREAK. Brt 0
determines whether parity error or the parity bit is displayed in ISR
bit 2.
(Control Register bit 6
7
6
5
3
4
=1)
2
NOT USED
Address = 2,6
During power on initialization, all readable registers should be read
to assure that the status registers are initialized. Specifically, the
RDRF bit of the Interrupt Status Registers is not initialized by reset.
The Receiver Data Registers must be read to clear this bit.
1
0
TRNS
BRK
PAR
ERRIST
TORE IRQ is generated only on the transition of the corresponding
TOR from full to empty. Initialization software must account for this
occurrence.
Reset Value - ------00
BAUD RATE CLOCK OPTIONS
Not Used
Bits 7·2
Bit 1
1
lhmsmlt Break (TRNS BRK)
The receiver and transmitter clocks may be supplied either by the
internal Baud Rate Generator or by user supplied external clocks.
Both channels may use the same clock source or one may use
the Baud Rate Generator and the other channel external clocks.
If both channels use the Baud Rate Generator, each channel may
have a different bit rate. The options are shown in Figure 5.
Transmit continuous Break
Normal transmission
o
Bit 0
Parity Error/State (PAR ERR/ST)
Send value of parity bit to ISR bit 2 (Address
Recognition mode)
Send Parity Error status to ISR bit 2
1
o
An internal clock oscillator supplies the time base for the Baud
Rate Generator. The oscillator can be driven by a crystal or an
external clock.
RECEIVE DATA REGISTERS (RDR1, RDR2)
The Receive Data Registers are read-only registers which are
loaded with the received data character of each frame. Start bits,
stop bits and parity bits are stripped off of incoming frames before
the deta is transferred from the Receive Shift Register to the
Receive Data Register. For characters of less than eight bits, the
unused bits are the high order bits which are set to o.
MSB
7
If the on-chip oscillator is driven by a crystal, a parallel resonant
crystal is connected between the XTALI and XTAlO pins. The
equivalent oscillator circuit is shown in Figure 6.
A parallel resonant crystal is specified by its load capacitance and
series resonant resistance. For proper oscillator operation, the load
capacitance (Ct.), series resistance (Rs) and the crystal resonant
frequency (F) must meet the follOWing two relations:
LSB
6
5
432
o
RECEIVE DATA
Address = 3,7
Reset Value = 00000000
(C + 2)
TRANSMIT DATA REGISTERS (TDR1, TDR2)
The Transmit Data Registers are write-only registers which are
loaded from the CPU with data to be transmitted. For data characters of less than eight bits, the unused bits are the high order bits
which are "don't care".
MSB
7
= 2C L
or
C
= 2CL
-
2
2x1OS
Rs :s Rsmax = - (FOc)2
where: F is in MHz; C and CL are in pF; R is in ohms.
LSB
6
5
4
3
2
To select a parallel resonant crystal for the oscillator, first select
the load capacitance from a crystal manufacturer's catalog. Next,
calculate Rsmax based on F and CL• The selected crystal must
have a R. less than the R.max.
o
TRANSMIT DATA
Address = 3,7
Reset value = - - - - - - - -
6·215
•
Dual Asynchronous Communications Interface Adapter (DACIA)
R65C52
CLOCK INPUT
r--~.-----iXTALI
o
t---4>----~
• Baud rate determined by XTALI frequency and 1 of 15 divisors selected in
CRl and CR2. CRl and CR2 must not be
set to all ones.
U1JUlfL
OPEN CIRCUIT
XTALO
XTALO
• Channel 1 baud rate may be different
from channel 2 baud rate.
• Receiver baud rate muat be the same as
transmitter baud rate.
A. Both Channels Use Internal Baud Rate Generator'
16 x llc BAUD RATE
• Transmitter baud rate 1116 TxC input
frequency.
rLfUlJL
lJU1J1J
• Receiver baud rate 1116 RxC input
frequency.
16 x Rx BAUD RATE
XTALI
INTERNAL CLOCK
OSCILLATOR DISABLED
• Channel 1 baud rate Is the same as
channel 2 baud rate.
• Receiver baud rate may be different from
transmitter baud rate.
XTALO
• Bits 3-~ of CRl and CR2 must be set to
all ones.
B. Both Channels Use External Clocks
1:
_
CLOCK INPUT
f - -.....>----~ XTALI
lJU1f
CJ
OPEN CIRCUIT
XTALO
• Channel 1 baud rate may be different
from channel 2 baud rate.
• Transmitter baud rate may be different
from receiver baud rate on channel
using external clock.
16 x llc BAUD RATE
16 x Tx BAUD RATE
lJUlJ
1JUl
16 x Rx BAUD RATE
lJlJl
16 x Rx BAUD RATE
lJ1JL
C. One Channel Uses Internal Baud Rate Generator;
One Channel Uses External Clocks
Figure 5.
Baud Rate Clock Options
6-216
Dual Asynchronous Communications Interface Adapter (DACIA)
R65C52
The series resistance of the crystal must be less than
R.ma• =
C:l:5%
XTLI
2pF
lt~
-=
1~
= 304 ohms
If the on-chip oscillator is driven by an external clock, the clock
is input at XTALI and XTALO is left open.
~t-::l
XTLO
2pF-::-
C:l:5%
2x106
(3.6864 x 22)2
An internal counter/divider circuit divides the frequency input at
XTALI by the divisor selected in bits 3 through 0 of the Control
Registers. Table 5 lists the divisors that may be selected and shows
the bit rates generated with a 3.6864 MHz crystal or clock input.
Other bit rates may be generated by changing the clock or crystal frequency. However, the input frequency must not exceed
4 MHz.
Figure 6.
For external clock operation, a transmitter times 16 clock must be
supplied atTxC and a receiver times 16 clock must be input at RxC.
Since there are separate receiver and transmitter clock inputs, the
receiver data rate may be different from the transmitter data rate.
For example, if CL = 22 pF for a 3.6864 MHz parallel resonant
crystal, then
C = (2 x 22) - 2 = 42 pF (use standard value of 43 pF)
Table 5.
Control
Register
Bits
Baud Rate Generator Divisor Selection
Baud Rate Generated
With 3.6864 MHz
Crystal or Clock
Baud Rate Generated·
With a Crystal or Clock
of Frequency (f)
3
2
1
0
Divisor Selected
ForThe
Internal Counter
0
0
0
(3.6864 x 10')173,728 = 50
fl73,728
0
0
0
1
73,728
0
33,538
(3.6864 x 10')/33,538 = 109.92
1133,538
0
0
1
0
27,408
(3 6864 x 10')/27,408 = 134 58
1127,408
0
0
1
1
24,576
(3.6864 x 10')/24,576 = 150
1124,576
0
1
0
0
12,288
(3.6864 x 10')/12,288 = 300
1112,288
0
1
1
6,144
(3.6864 x 10')/6,144 = 600
1/6,144
0
1
0
1
0
3,072
(3.6864 x 10')/3,072 = 1,200
113,072
0
1
1
1
2,048
(3.6864 x 10')/2,048 = 1,800
112,048
1
0
0
0
1,536
(3.6864 x 10')/1,536 = 2,400
111,536
1
0
0
1
1,024
(3.6864 x 10')/1,024 = 3,600
111,024
1
1
(3.6864 x 10')/768 = 4,800
11768
1
0
1
768
1
0
0
512
(3.6864 x 10')/512 = 7,200
11512
1
1
0
0
384
(3.6864 x 10')/384 = 9,600
11384
1
1
0
1
192
(3 6864 x 10')/192 = 19,200
11192
1
1
1
0
96
(3 6864 x 10')196 = 38,400
1
1
1
1
16
'Baud Rate =
Transmitter Baud Rate = TxC/16
Frequency
Divisor
6-217
1196
Receiver Baud Rate = RxC/16
II
R65C52
Dual Asynchronous Communications Interface Adapter (DACIA)
CONTINUOUS DATA TRANSMIT
to the TDR the TDRE bit is cleared. In order to maintain continu
ous transmission the TDR must be loaded before the stop bit(s;
are ended. 1/16 of a bit time after IRQ goes low, the IRQ line may
be reset by reading the ISR. IRQ will always reset when data is
written to the TDR. Figure 7 shows the relationship between IRQ
and TxD for the Continuous Data Transmit mode.
In the normal operating mode, the TDRE bit in the ISR signals the
MPU that the DACIA is ready to accept the next data word. An IRQ
occurs on the transition of the TDR from full to empty if the corresponding TDRE IRQ enable bit is set in the IER. The TDRE bit
is set at the beginning of the start bit. When the MPU writes a word
CHAR #n + 1
CHAR #n
/
I
,/
I
CHAR #n + 2
~/
CHAR #n + 3
J
' /
I
,
TX~ t [B:E]~]~I~TtlJE~E;I ~ GEJ t I t [B~J--S:[ ~ GEJ t I t roJB7[ ~ ~
: START
STOP:START
STOP: START
Ulr
IR~
-.ssoR /
INTERRUPT
(TRANSMIT DATA
REGISTER EMPTY)
.L, ~ f=:'~'
READS
ISR, CAUSES
IRQ TO CLEAR
TxD
l
(TUR) IS set. This condition persists until the TDR IS loaded with
a new word. Figure 8 shows the relation between IRQ and TxD for
the Transmit Underrun Condition.
CONTINUOUS "MARK"
CHAR #n + 1
CHAR #n + 2
~/
/
TtlI t GEl ~ GEJ t 1
------,1I t [S:]"i\[ ]~;r~ t II t [BJB2J ~]~
1~____----;-------71LJlJ
LJlJr-n--t
/
/
~WHEN
STOP START
IRQ
L
Continuous Data Transmit
lithe MPU is unable to load the TDR before the last stop bit is sent,
the TxD line goes to the MARK condition and the underrun flag
"
t
STOP:
INTERVAL OTHERWISE,
CONTINUOUS "MARK"
IS TRANSMITTED
TRANSMIT UNDERRUN CONDITION
/
Lm
/lJ]
Figure 7.
CHAR #n
I
STOP: START
PROCESSOR
INTERRUPT
FOR DATA
EMPTY
STOP
UNDERRUN BIT
SET
Figure 8.
START
PROCESSOR READS
ISR, CLEARS IRQ
PROCESSOR FINALLY LOADS
NEW DATA, TRANSMISSION STARTS
IMMEDIATELY AND INTERRUPT
OCCURS, INDICATING TRANSMIT
DATA REGISTER EMPTY
Transmit Underrun Condition Relationship
6-218
STOP START
R65C52
Dual Asynchronous Communications Interface Adapter (DACIA)
one character time to assure that a proper BREAK is transmitted.
If the Transmit Break bit is cleared before one character time of
BREAK has been transmitted, the BREAK will be terminated after
one character time has elapsed. If the Transmit Break bit is cleared
after one character time of BREAK has been transmitted, the
BREAK will be terminated immediately. Figure 9 shows the relationship of TxD, IRQ and ACR bit 1 for various BREAK options.
TRANSMIT BREAK CHARACTER
A BREAK may be transmitted by setting bit 1 of the ACR (Transmit Break bit) to a 1. The BREAK is transmitted after the character in the Transmit Shift Register is sent. If there is a character in
the Transmit Data Register, it will be transmitted after the BREAK
is terminated. The Transmit Break bit must remain set for at least
STOP START
1lcD
STOP START
STOP START
STOP START
~~~ *1' [SOJit[ 1SB tit [iOJitJ=I£il ; 1t [iolit[~
ACR
BIT 1
"'T 'TT- nTrT1
"
I • .I,I
I I . . _______________________________________________________
ul~I~I~'
TORE~i
I
I
IRQ
U'
I
J
LIJI
LlJ
i II
I
J
i
J
i
J
a. Transmit Break bit cleared before BREAK begins-BREAK Is Ignored
STOP START
1lcO
ACR
BIT 1
STOP
STOP START
STOP START
~=@!E] til--'--'--.BR_E
. . . .....AK--'--'-.....rtl. @OJi~[§!B t 1.1iO"[B1J=~~=
1- '--r-,
i-r-I
i :
, , __ J._'"
i
I
i
I
I
L_J._
'
I
,
TORE~i
IRQ
'
I
I
LIT
i
J
L1J'
I
I
J
I
J
b. Transmit Break bit cleared during first character time of BREAK-BREAK terminates after one character time
STOP START
1lcO
STOP
~~~
STOP START
*\1-_____B_R_EA_K_ _ _ _----'rtl t [iO[81J= l!J!J
ACR
rTT-rl--------------------------------~
BIT 1 _____~:...:-,-:...
' -_________________
TORE
IRQ
~rri-------------------.UJr-,
I
I
I
I
J
J
c. Thmsmit Break bit cleared after first character time of BREAK-BREAK tennlnates Immediately
Figure 9.
ll'ansmit BREAK
EFFECTS OF CTS ON TRANSMITTER
The CTS control line controls the transmission of data or the handshaking of data to a "busy" device (such as a printer). When the
CTS line is low, the transmitter operates normally. A high condition inhibits the TORE bit in the ISR from becoming set. Transmission of the word currently in the shift register is completed but any
word in the TOR is held until ers goes low.
TxD
CHAR Nn
CHAR Nn + 1
I
I
~-,-_r-".,/
"
EC~ t
I t [%F[-IBNI
STOP START
LJ1]
Any transition on CTS sets bit 5 (CTSn of the ISA. A high on CTS
forces bit 6 QQBE) of the ISR to a O. Bit 7 of the ISR also goes
to a 1 when CTS is high, if Echo Mode is disabled. Thus, when
the ISR is $80, it means that CTS is high and no interrupt source
requires service. A processor interrupt will not be generated under
these circumstances, but an ISR polling routine should accommodate this.
CONTINUOUS MARK
NEXT CHARACTER IS SENT IMMEDIATELY
UPON CTS GOING LOW IF PROCESSOR
HAS ALREADY LOADED NEW DATA,
OTHERWISE IT WAITS FOR NEW DATA.
UU
pit
I'NEXT
STOP
CHARACTER
IS NOT SENT
TORE IS NOT SET
MPU
CLEARS
IRQ AGAIN
t
I
I 8 0 I 8, I ':,
START
WHEN PROCESSOR
FINALLY LOADS
NEW DATA,
TRANSMISSION STARTS
CTSJ--------------------'Il...in ~MEDIATELY
~
IRQ
C~L=E~A~R.~T~O~.S=E~N~D______~I
MPU
CLEARS
CTS _________
IRQ
Figure 10. Effects of CTS on Transmitter
6-219
AND
'\
INTERRUPT OCCURS,
CTS
INDICATING TRANSMIT
IRQ
DATA REGISTER EMPTY
' -_______________
_
I
6
Dual Asynchronous Communications Interface Adapter (DACIA)
R65C52
ECHO MODE TIMING
In the Echo Mode, the TxD line re-transmits the data received on
the RxD line, delayed by 1/2 of a bit time. An internal underrun
mode must occur before Echo Mode will start transmitting. In nor·
mal transmit mode if TDRE occurs (indicating end of data) an
STOP
RxD
TxD
START
STOP
underflow flag would be set and continuous Mark transmitted. If
Echo is initiated, the underflow flag will not be set at end of data
and continuous Mark will not be transmitted. Figure 11 shows the
relationship of RxD and TxD for Echo Mode.
START
STOP
END OF
DATA
J1l +~FII~EJ +1t [-S;EI~ ~ + 11-/__
\1 \ \ \ \ \ \ \ \ \ \ \ _________ ;O:ci~N~gHu~;~~:
W t ~==~ t 1t ~==~ t 1=====
STOP START
STOP~
STOP START
IF ECHO MODE,
NO UNDERFLOW,
THEREFORE NO
CONTINUOUS MARK
Figure 11.
Echo Mode Timing
CONTINUOUS DATA RECEIVE
The normal receive mode sets the RDRF bit in the ISR when the
DACIA channel has received a full data word. This occurs at about
the 9116 point through the stop bit. The processor must read the
CHAR In
/
'
RDR before the next stop bit, or an overrun error occurs. Figure 12
shows the relationship between IRQ and RxD for the continuous
Data Receive mode.
CHAR In + 1
'-/
I
CHAR In + 2
'-/
CHAR In + 3
'
'-/
I
"-
RX~ t [i;rB1I~~/1 t [i;JBt]~=~/1 t ffi~]giJ! 1t ~=~~I L
START
STOP: START
nT----------~~'
STOP:
IR~
I
IRQ PROCESSOR
INTERRUPT OCCURS
ABOUT 9/16 INTO
LAST STOP BIT
PARITY OVERRUN,
AND FRAMING ERROR
UPDATED ALSO
LlU'
)
START
ILJI]
\ ~
PROCESSOR READS
ISR,CAUSES
IRQ TO CLEAR
START
,
LJlJ
PROCESSOR MUST READ
RECEIVER DATA IN THIS
TIME INTERVAL, OTHERWISE
OVERRUN OCCURS
Figure 12. Continuous Data Receive
6·220.
STOP:
STOP:
,
L
Dual Asynchronous Communications Interface Adapter (DACIA)
R65C52
EFFECTS OF OVERRUN ON RECEIVER
contains the last word not read by the MPU and all following data
is lost. The receiver will return to normal operation when the ADR
is read. Figure 13 shows the relationship of IRQ and RxD when
overrun occu rs.
If the processor does not read the RDR before the stop bit of the
next word, an overrun error occurs, the overrun bit is set in the ISR,
and the new data word is not transferred to the ADA. The ADR
~
/
CHAR In
'
CHAR In + 1
"/
'
CHAR lin + 2
, /
CHAR Itn + 3
'
" /,-___--1'___
JIll
[i0l ~ ]~JiJ! I t [i0l ~ ]~;r~J! I t [BOJBJ~]gi] I I t [i0l ~~ ~
I
I
I
I I
RxD
STOP
IRQ
S1ART
STOP
--u
START
STOP
I
START
STOP
1lL-~___
t
MPU READS
I
PROCESSOR /
INTERRUPT
FOR RECEIVER
DATA REGISTER
FULL
START
MPU DOES
NOT READ
RDR. OVERRUN
BIT SET
ISR
CLEARS IRQ
'CHAR lin + 2
IRQ.
CHAR Itn + 1
IS LOST
Figure 13. Effects of Overrun on Receiver
RECEIVE BREAK CHARACTER
normally. Figure 14 shows the relationship of IRQ and RxD for a
Receive Break Character.
When a Break character is received, the Break bit is set. The
receiver does not set the RDRF bit and remains in this state until
a stop bit is received. At this time the next character is received
--------..,
'RxD
]~~I~~~II t
CONTINUOUS "BREAK"
IBOIB11 __
STOP START
U
----i
f
PROCESSoR
INTERRUPT
FOR
RECEIVER
DATA REGISTER
FULL
'~1
PI"
STOP
I
Ifl'
i rrI
L...lJ
1~
PROCESSOR
m
l t [B01"8~[=~~11 tlBoI
STOP /
START
STOP
START
I"
Bl
l
rr---
L_...1J
NO- ' " NO INTERRUPT
MORE
SINCE RECEIVER.
INTERRUPTS
DISABLED UNTIL
INTERRUPT
FIRST START BIT
WITH BREAK AND FRAMING ERROR BIT SET.
EVEN PARITY CHECK WILL ALSO GIVE A PARITY
ERROR BECAUSE ALL ZEROS (CONTINUOUS
BREAK) REPRESENT EVEN PARITY.
Figure 14. Receive Break Charecter
6-221
"/,-----
1
NORMAL
RECEIVER
INTERRUPT
•
Dual Asynchronous Communications Interface Adapter (DACIA)
R65C552
FRAMING ERROR
Framing error is caused by the absence of stop bit(s) on received
data. The framing error bit is set when the RDRF bit is set. Subsequent data words are tested separately, so the status bit always
I
I I
reflects the last data word received. Figure 15 shows.the relationship of IRQ and RxD when a framing error occurs.
STOP STOP START
RxD
(EXPECTED)
1
2
p"""TI"'T"\"T"'I-hI
-r1-a.'T""1
STOP STOP START
1
Bo
2
/
I B, I B21 B31 B.I Bsl B81 P I" I I II [BOT
STOP
STOP
ISTOP START
~~--r-~'--r-r_p~1~_~2IfBe
1
RxD
(ACTUAL)
IPROCESSOR
NOTES: 1. FRAMING ERROR DOES NOT
INHIBIT RECEIVER OPERATION.
INTERRUPT,
FRAMING
ERROR
BIT SET
2. IF NEXT DATA WORD IS OK,
FRAMING ERROR IS CLEARED.
Figure 15. Framing Error
PARITY ERROR DETECT/ADDRESS
FRAME RECOGNITION
this type of operation, bit 0 of the ACR is set to a 1 and bits 2, 3
and 40lthe FR select a parity checking mode. Then, ISR bit 2 will
be set to a 1 by incoming address frames and it will be a 0 on data
frames.
The Parity Status bit (ISR bit 2) may be programmed to indicate
parity errors (ACR bit 0 = 0) or to display the parity bit received
(ACR bit 0 = 1).
COMPARE MODE
In applications where parity checking is used, one of the parity
checking modes is enabled by setting bits 2, 3 and 4 of the Format Register to the desired option and bit 0 of the Auxiliary Control Register Is reset to O. Then, when the RDRF bit (bit 0) is set
in the ISR, the PAR bit (bit 2) will be, set when a parity error is
detected.
The Compare Mode is automatically enabled, i.e., the channel is
put to sleep, whenever data is written to the Compare Data'
Register. NOTE: Bit 6 of the Control Register must be set to 0 to
enable access to the Compare Data Register. When the channel
is in the compare mode, the RDRF bit (bit 0 of the ISR) is forced
to a O. Upon receipt of a matching character, normal receiveroperation resumes and the RDRF bit (bit 0 of the ISR) will be set upon
receipt of the next character.
In multi-drop applications, the parity bit is Used as an addressldata
flag. It is set to 1 for address frames and is 0 on data frames. For
6-222
R65C52
Dual Asynchronous Communications Interface Adapter (DACIA)
SPECIFICATIONS
DACIA READIWRITE WAVEFORMS
1-8
.
CD
-8
CD
RSO-RS2
~
.
.
CD
-0-t
00-07
CD
t--
~03
Jr----
0
•
@~
~1·-------REAOCYCLE------·t--I·-----WRITECYCLE-----+I·1
NOTE: TIMING MEASUREMENTS ARE REFERENCED TO AND FROM A LOW VOLTAGE OF 0.8V AND A
HIGH VOLTAGE OF 2.0V, UNLESS OTHERWISE NOTED.
DACIA READ/WRITE CYCLE TIMING
(Vee = 5 Vdc
±5%, Vss
= 0 Vdc, TA = T L to T H, unless otherwise noted)
1 MHz
Number
Characteristic
Symbol
Min.
3 MHz
2 MHz
Max.
Min.
Max.
Min.
45
45
340
-
210
-
ns
290
-
170
ns
50
ns
TASU
2
CS Low to RIW, RSO-RS2 Invalid (Hold)
TAH
45
3
CS Pulse Width
Tcp
410
-
6
CS Low to Data Valid (Read)
TCDV
-
360
8
CS High to Data Invalid (Read)
TCDA
10
50
10
50
10
9
Data Valid to CS High (Write, Setup)
TDSU
30
-
30
30
10
CS High to Data Invalid (Write Hold)
TCDW
10
-
10
-
6-223
Unit
-
RIW, RSO-RS2 Valid to CS Low (Setup)
5
Max.
-
1
5
-
5
10
-
ns
ns
ns
ns
•
Dual Asynchronous Communications Interface Adapter (DACIA)
R65C52
DACIA TRANSMIT/RECEIVER WAVEFORMS
TxC, RxC
1iI:D
CTS, DCD, DSR
CS
RTS,DTS
---------t-""f"
b@-
-----1:'-.- - - - + -
if
---~:.j@~
----------------------------------
NOTE: IRQ WILL NOT CHANGE STATE WHEN CS IS LOW. NOTE: TIMING MEASUREMENTS ARE REFERENCED TO AND FROM
A LOW VOLTAGE OF O.W AND A HIGH VOLTAGE OF 2.OV,
UNLESS OTHERWISE NOTED.
TRANSMIT/RECEIVE AND INTERRUPT ACKNOWLEDGE TIMING
(Vee
= 5 Vdc
Number
± 5%, Vss
= 0 Vdc. TA = T l to TH. unless otherwise noted)
Characteristic
Symbol
Min.
Max.
Unit
TRANSMIT/RECEIVE TIMING
12
Transmit/Receive Clock Rate
125
-
ns
Transmit/Receive Clock High
Icy
tcH
300
13
14
Transmit/Receive Clock Low
tel
125
-
ns
15
TxC, RxC to TxD Propagation Delay
too
-
285
ns
16
TxC, RxC to IRQ Propagation Delay
tOI
-
285
ns
17
CTS, DCD, DSR Valid to IRQ Low
tCTI
150
ns
18
IRQ Propagation Delay (Clear)
tiRO
-
150
ns
19
RTS, DTR Propagation Delay
t OlY
-
150
ns
6-224
ns
Dual Asynchronous Communications Interface Adapter (DACIA)
R65C52
ABSOWTE MAXIMUM RATINGS·
Parameter
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Commercial
Industrial
Symbol
Value
Unit
Vee
-0.3 to + 7.0
Vdc
VIN
- 0.3 to Vee + 0.3
Vdc
VOUT
-0.3 to Vee + 0.3
Vde
"NOTE: Stresses above those listed may cause permanent
damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above
those indicated in other sections of this document is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
°C
TA
Oto +70
-4Oto +85
Storage Temperature
Tsro
-55 to +150
°C
OPERATING CONDITIONS
Parameter
Supply Voltage
Temperature Range
Commercial
Industrial
Symbol
Value
Vec
5V±5%
TA
o
to 7Q°C
-40°C to +85°C
DC CHARACTERISTICS
(Vee =
5.0 V ±5%, Vss
= 0, TA = TL to T H, unless otherwise noted)
Parameter
Symbol
Input High Voltage
Except XTALI
XTALI
VIH
Input low Voltage
Except XTALI
XTALI
VIL
Input leakage Current
RiW, RES, RSO, RS1, RS2, RxO, CTS, OCO, OSR, RxC,
TxC, CS
Min
lYP
Max
Unit
Test Conditions
V
+2.0
+3.0
-
Vee + 0.3
Vee + 0.3
-0.3
-0.3
-
-
+0.8
+0.4
liN
-
10
50
"A
VIN = OV to 5.0V
Vee = 5.25V
Input leakage Current lor Three-State Off
00-07
ITSI
-
±2
10
~A
VIN = 0.4V to 2.4V
Vee = 5.25V
Output High Voltage
00-07, TxO, ClK OUT, RTS, DTR
V OH
-
-
V
Vce = 4.75V
ILOAD = -100"A
Output low Voltage
00-07, TxD, ClK OUT, RTS, DTR
VOL
-
-
+0.4
V
Vee = 4.75V
ILOAD = 1.6 rnA
Output leakage Current (Off State)
IRQ
IOFF
-
±2
± 10
"A
Vee = 5.25V
VOUT = 0 to 2.4V
Power Oissipation
Po
-
-
10
mW/MHz
Input Capacitance
Except XTAll
XTALI
CIN
-
-
5
10
pF
pF
10
pF
Output Capacitance
V
+2.4
-
COUT
Notes:
1. All units are direct current (de) except lor capacitance.
2. Negative sign indicates outward current flow, positive indicates inward Ilow.
3. Typical values are shown lor Vee = 5.OV and TA = 25°C.
6-225
-
Vee = 5.0V
VIN = OV
1= 2 MHz
TA = 25°C
II
Dual Asynchronous Communications Interface Adapter (DACIA)
R65C52
PACKAGE DIMENSIONS
40·PIN CERAMIC DIP
MILLIMETERS
[ D ]JJ
I-
-I
A
ibtin
r~::::::: ~::::::: ::PrLI
t
iF
H~tlD
G
-II-
K ---J
M-j
INCHES
DIM
MIN
MAX
MIN
MAX
A
5029
5131
1980
2020
B
1511
0825
254
1588
419
0595
C
0100
0185
D
038
053
127
0015
0021
0030
0050
F
078
G
H
254BSC
076
178
o 100SSC
0030 0070
J
020
033
0008
0013
K
254
419
0100
0185
L
M
1460
O·
1537
10·
0575
O·
0605
10·
N
051
152
0020
0080
40·PIN PLASTIC DIP
MILLIMETERS
MIN
MAX
MIN
MAX
A
5182
2040
2080
B
1348
5232
1397
0530
0550
C
356
508
0140
0200
D
038
102
053
152
0015
0040
0021
0080
F
~~
INCHES
DIM
G
254BSC
H
185 1 216
0085
0100 BSC
J
020 1 030
K
33Ol432
0008 0012
o 13O-T 0 170
L
M
1524 esc
7·
10"
r
0800 BSC
7·
10·
N
051 1 102
0020 1 0040
r0085
I
T
44-PIN PLASTIC LEADED CHIP CARRIER (PLCC)
~tt=~~jl
DIr~' ?
38-
~
~
~,
INDICATOR
L-17
/
MIUlMETERS
~~
~i
~~
21
~
SIDE VIEW
TOP VIEW
CHAM.J x 45"
~~urm
~038
'0;::
~
~
§
~i~
+
~28~
i.ruJ. ilruJiij'i
-l
j.c.
CHAM.
11 PINS
h x 45" PER SIDE
3PLCS EQUALLY
SPACES
SEATING PLANE
-If-b
~~"'
,
AlA
R
SECTION A-A
TYP FOR BOTH AXIS (EXCEPT FOR BEVELED EDGE)
EJECTOR PIN MARKS
4 PLCS BOTTOM OF
PACKAGE ONLY
(TYPICAL)
BOTTOM VIEW
6-226
INCHES
DIM
MIN
MAX
MIN
MAX
A
414
439
0183
0173
Al
137
147
0054
0058
A2
231
248
0091
0097
b
a 457TYP
0018TYP
088710693
D
1745 11760
Dl
1648 1 1656
0648 1 0652
D2
126211278
049710503
D3
1575 REF
0620 REF
•h
127BSC
115TYP
o050 BSC
J
o 25TYP
o 010TYP
45°TYP
45°TYP
R
o 88TYP
o 25TYP
0035 TYP
.
Rl
0045TYP
0010 TYP
R68C552
'1'
Rockwell
R68C552
Dual Asynchronous Communications
Interface Adapter (DACIA)
DESCRIPTION
FEATURES
The Rockwell CMOS R68C552 Dual Asynchronous Communications Interface Adapter (DACIA) provides an easily implemented,
program controlled two-channel interface between 16-bit
microprocessor-based systems and serial communication data
sets and modems.
• Low power CMOS N-well silicon gate technoiogy
The DACIA is designed for maximum programmed control from
the microprocessor (MPU) to simplify hardware implementation.
Dual sets of registers allow independent control and monitoring
of each channel.
Transmitter and Receiver bit rates may be controlled by an internal baud rate generator or external times 16 clocks. The baud rate
generator accepts either a crystal or a clock input, and provides
15 programmable baud rates. When a 3.6864 MHz crystal is used,
the baud rates range from 50 bps to 38,400 bps.
The DACIA may be programmed to transmit and receive frames
having word lengths of 5, 6, 7 or 8 bits; even, odd, space, mark
or no parity; and 1 or 2 stop bits.
A Compare Register, and the ability to detect address frames, facilitate address recognition in a multidrop mode.
• Two independent full duplex channels with buffered receivers
and transmitters.
•
Data set/modem control functions
• Internal baud rate generator with 15 programmable baud rates
(50 bps to 38,400 bps)
•
Program-selectable internally or externally controlled receiver
and transmitter bit rates
•
Programmable word lengths, number of stop bits, and parity
bit generation and detection
• Programmable interrupt control
•
Edge detect for DCD, DSR, and CTS
•
Program-selectable echo mode for each channel
• Compare Register
• Address/Data frame recognition
•
5.0 Vdc ± 5% supply requirements
•
40-pin plastic or ceramic DIP or 44-pin PLCC
•
Full TIL or CMOS input/output compatibility
• Compatible with R68000 microprocessors
ORDERING INFORMATION
1LT'mpe",,"~
Part Number:
R68C552
R_ (T,
~ T'"
Blank =
O°C to + 70°C
E = -40°C to + 85°C
Package:
C = 40-Pin Ceramic DIP
P = 40-Pin Plastic DIP
J = 44-Pin Plastic Leaded
Chip Carrier (PLCC)
Document No. 68650N09
Product Description
6-227
Order No. 708
Rev. 4, February, 1988
•
Dual Asynchronous Communications Interface Adapter (DACIA)
R68C552
INTERFACE SIGNALS
The DACIA is available in a 4O-pin DIP or a 44-pin PLCC. Figure 1
shows the pin assignments for each package. The DACIA interface signals are shown in Figure 2. Table 1 contains a description
of each signal.
m
Vee
cs
l!'fACK
RIW
RU
ASI
XTAU
XTALO
CLKOUT
~
........ N-:IJ\l!;ti
RSo
TxOl
OTRI
RxOl
IRQl
RTSI
CTSI
DCOI
DSRI
IACKl
RSO
iM:Ki
DSR2
DC02
DSRI
OCOI
CTSI
AlSl
IRQl
RxOl
OTRI
TxOl
RxC
CTS2
AlU
iRQi
Rx02
OTR2
Tx02
TxC
07
DS
OS
04
o
38
TxC
PIN I
INDICATOR
38
37
Tx02
RxC
lffiii
35
34
Rx02
IRQ2
RTS2
33
CTi2
38
32
IiCiii
31
30
iACK2
28
CLKOUT
DSR2
DO
01
02
03
V..
44-P1N PLCC
4O-PIN DIP
Figure 1. R68C552 Pin Assignments
I
I
IACK1
IACK1
LOGIC
AClA1
REGISTERS
AND
CONTROL
LOGIC
ACIA1
INTERRUPT
LOGIC
IRQ1
RES
RIW
RSO
R68000
BUS
RS1
RS2
DTACK
LOGIC
DTACK
.A
<...-DO-D7
T
IRQ2
I
DATA
I/O
MUX
~ INTERRUPT
ACIA2
IACK2
I
Axe
ACIA2 BAUD
RATE SELECT
ACIA2
REGISTERS
AND
CONTROL
LOGIC
LOGIC
IACK2
LOGIC
CLOCK
LOGIC
XTALI
XTALO
CLKOUT
TxC
DATA
BUS
BUFFERS
~
}
ACIA
CHANNEL 1
ACIA1 BAUD
RATE SELECT
I/O CONTROL
AND
REGISTER
SELECT
LOGIC
CS
DTR1
DSR1
RTS1
CTS1
TxD1
DCD1
RxD1
I
Figure 2. R68C552 DACIA Interface Signals
6-228
DTR2
DSR2
RTS2
CTS2
TxD2
DCD2
RxD2
}
ACIA
CHANNEL 2
R68C552
Dual Asynchronous Communications Interface Adapter (DACIA)
Table 1.
DACIA Interface Signal Definitions
PinNa.
DIP
Signal
PLCC
110
Name/Description
Host Interface
RES
1
24
I
Reset. Active low input controlling the reset function. This signal must be driven low for a minimum of
4 ~s for a valid reset to occur. It is driven high during normal operation.
RNi
38
20
I
ReadlWrite. Input controlling the direction of data transfer. It is driven low during write cycles, and is
driven high at all other times.
CS
39
21
I
Chip Select. Active low input enabling data transfers between the host CPU and the DACIA. The
DACIA latches register selects and the RNi'lnput on the falling edge of es. It latches input data on the
rising edge of es.
RSO-RS3
35-37
17-19
I
Register Select. Three inputs contrOlling access to the DACIA internal registers. Table 3 lists the coding for each register.
DO-D3
D4-D7
24-21
19-16
6-3
44-41
I/O
Data Bus. Eight bidirectional lines used to transfer data between the host and the DACIA. These lines
output data during READ cycles when CS is low and they output the interrupt vector during INTERRUPT ACKNOWLEDGE cycles when IACKI or IACK2 is low. At all other times, they are in the high
impedence state.
2
25
0
Data Ti'ansfer Acknowledge. Active low open drain output generated in response to CS, IACKI and
IACK2 during asynchronous data transfers. DTACK goes to the high impedence state when CS, IACKI
and IACK2 are high.
IRQl
IRQ2
29
11
11
35
0
Interrupt Request. Two active low, open-drain outputs from the interrupt control logic. These outputs
are normally high. An IRQ line goes low when one of the flags of the associated ISR is set if the
corresponding enable bit IS set in the lEA.
IACKI
IACK2
34
6
16
30
I
Interrupt Acknowledge. Two active low inputs indicating that an INTERRUPT ACKNOWLEDGE cycle
is in progress. When an lACK goes low, the DACIA places the interrupt vector for the associated
channel on the data bus and issues DTACK.
.
XTALI
XTALO
3
4
26
27
I
0
Crystal Input/Output. One Input and one output through which the reference signal for the internal
clock oscillator IS supplied. A parallel resonant crystal may be connected across the pins or a clock
may be input at XTALI. When a clock is used, XTALO must be left open.
eLK OUT
5
29
0
DTACK
Clock Interface
Clock Out. A buffered output from the Internal clock oscillator which is in phase with XTALI. This out·
put may be used to drive the XTALI Input of another DACIA. Therefore, several DACIA chips may be
driven with one crystal.
RxC
25
7
I
Receiver Clock. Input for external 16x receiver clock
TxC
15
39
I
Transmitter Clock. Input for external 16x transmitter clock.
Serial Channel Interface
DTRI
DTR2
27
13
9
37
0
DSRI
DSR2
33
15
31
I
7
Data Set Ready. Two general purpose inputs. An active transition sets the DSRT bit in the Interrupt
Status Register (ISR). The DSR LVL bit in the associated CSR reflects the current state of a DSR line.
RTSI
RTS2
30
10
12
34
0
Request To Send. Two general purpose outputs which are set high upon reset. The output level is
programmed by setting the appropriate bit in the associated FR high 01' low. The state of an RTS line is
reflected by the RTS LVL bit in the associated CSR.
CTSI
CTS2
31
9
13
33
I
Clear To Send. The CTS control line Inputs allow handshaking by the transmitters. When CTS is low,
the data is transmitted continuously. When CTS IS high, the Transmit Data Register Empty bit (TDRE) in
the associated ISR is not set. The word presently in the Transmit Shift Register is sent normally. Any
active transition on a CTS line sets the CTST bit in the appropriate ISR. The CTS LVL bit in the
associated eSR reflects the current state of CTS.
TxDI
TxD2
26
14
8
38
0
Transmit Data. The TxD outputs transfer serial non-return to zero (NRZ) data to the data communications equipment (DCE). The data is transferred, LSB first, at ~ rate determined by the baud rate generator or external clock.
DCDI
DCD2
32
14
32
I
8
Data Carrier Detect. Two general purpose inputs. An active transition sets the DCDT bit in the
appropriate ISR. The DeD LVL bit in the associated CSR reflects the current state of a DCD line.
28
12
10
36
I
Receive Data. The RxD Inputs transfer serial NRZ data into the DACIA from the DCE, LSB first. The
receiver baud rate is determined by the baud rate generator or external clock.
VCC
40
22
I
DC Power Input. 5.0V ± 5%.
VSS
20
1
I
Power and Signal Reference.
RxDI
RxD2
I
Data Terminal Ready. Two general purpose outputs which are set high upon reset. The output level is
programmed by setting the appropriate bit in the associated Format Register (FR) high or low. The state
of each DTR line IS reflected by the DTR LVL bit In the associated Control Status Register (CSR).
Power
6-229
II
Dual Asynchronous Communications Interface Adapter (DACIA)
R68C552
FUNCTIONAL DESCRIPTION
the interrupting condition is cleared. CAUTION: When the interrupt is generated by TORE, 1/16 of a bit time must elapse before
IRQ can be cleared by reading the ISA.
When an lACK input goes low in response to an IRQ, the follOWing
occurs if CS and RIW are high: DO goes low ifthe IRQ is generated
by TOR empty or RDR full. DO goes high for all other interrupt
sources. TORE and RDRF interrupts have priority over all other
interrupt sources. 01 goes low when the interrupt request is from
Channell. It goes high if the IRQ is from Channel 2. 02 through
07 outputs the Interrupt Vector Number stored in bits 2 through
7 of the Auxiliary Control Register. DTACK is asserted.
Figure 3 is a block diagram of the DACIA which consists of two
asynchronous communications interface adapters with common
microprocessor interface control logic and data bus butters. The
individual functional elements of the DACIA are described in the
following paragraphs.
RESET LOGIC
The Reset Logic sets various internal registers, status bits and control lines to a known state. The RES input must be driven low
for a minimum of 4 ,.s for a valid reset to occur. At this time, the
IERs are set to $80, the RDRs and ACR$ are cleared, and the compare mode is disabled. Also, the DTR and RTS outputs are
driven high and the CTS, DCD and DSR transition detect flags
are cleared. No other bits are affe,cted.
CLOCK OSCILLATOR LOGIC
The internal clock oscillator supplies the time base for the baud
rate generator. The oscillator can be driven by a crystal or an external clock.
DATA BUS BUFFER
The baud rate generator may be disabled by connecting XTALI
to ground and leaving XTALO open. When this is done, a transmittertimes 16 clock must be input at TxC, a receiver times 16 clock
must be input at RxC and the Control Registers must be
programmed to select TxC and RxC clocks.
The Data Bus Buffer is a bidirectional interface between the data
lines and the internal data bus. The state of the Data Bus Buffer
is controlled by the I/O Control Logic and the Interrupt Logic.
Table 2 summarizes the Data Bus Buffer states.
1/0 CONTROL LOGIC
Table 2. Data Bus Buffer Summary
The I/O Control Logic controls data transfers between the Internal Registers and the Data Bus Buffer. Internal Register selection
is determ~ed by the R~ter Select inputs as shown in Table 3.
When RIW is high and CS is low, data from the selected register
is transferred from the internal data bus to the data lines and
DTACK is asserted. When CS is high, the DACIA is deselected if
the lACK inputs are high and the data lines are tri-stated.
ri
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
INTERRUPT LOGIC
The interrupt logic causes the IRQ lines (IRQl or IRQ2) to go low
when conditions are met that require the attention of the MPU.
There are two registers (the Interrupt Enable Register and the Interrupt Status Register) involved in the control of interrupts in the
DACIA. An IRQ will be asserted on the transition of one of the
flags in an ISR from 0 to 1 if the corresponding bit in the associated
IER is set. The IRQ line is negated when the ISR is read or when
Data Line
Output
7
I6 I5
4
I3 I2
IRQ VECTOR NUMBER
Control Signals
CS IACKl IACK2
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
Data Bus Buffer State
Illegal Mode - Tri-Stale
Illegal Mode - Tri-State
Illegal Mode - Tri-State
Write Mode - Tri-State
Illegal Mode - Tri-State
Illegal Mode - Tri-State
Illegal Mode - Tri-State
Tri-State
Illegal Mode - Output $OF
Illegal Mode - Output $OF
Illegal Mode - Output $OF
Read Mode - Output Data
Illegal Mode - Output $OF
Output IRQ Vector 1
Output IRQ Vector 2
Tri-Stale
0
IRQ
CHANNEL
IRQ
SOURCE
L
•
0
TDRE,RDRF
CTST, DCDT, DSRT
PAR, FIOIB
0
CHANNELl
CHANNEL 2
INTERRUPT VECTOR NUMBER
FROMACR
6-230
Dual Asynchronous Communications Interface Adapter (DACIA)
R68C552
Tx01
[~~~J::~~f====
INTERRUPT
LOGIC
OSR.
DCOl
CTS1
ACIA CHANNEL 1
~~~~l====-------4~
[=}~~~=t--------
OTRl
RTSl
RxDl
DATA
T,C
XTALI
CLKOUT
XTALO
R,C
RKD2
IRQ2~.~------i
INTERRUPT
LOGIC
ACIA CHANNEL 2
II
LEGEND
= COMMON LOGIC
...........,.......... = CONTROL LINES
1x02
~t::::> = 8-BtTDATALINES
MUL11-BIT C&:TROL LINES
Figure 3.
DACIA Block Diagram
6-231
Dual Asynchronous Communications Interface Adapter (DACIA)
R68C552
Table 3.
Register Accessed
Register Select
Lines
HEX
RS2
RSl
RSO
L
L
L
1
L
L
H
L
H
Read
Write
0
2
DACIA Register Selection
Symbol
Name
IERl
Interrupt Enable
Register 1
CRl
Control
Register l'
FRl
Format
Register 1"
CDRl
Compare Data
Register 13
ACRl
Auxiliary Control
Register l'
L
Symbol
Nama
ISRl
Interrupt Status
Register 1
CSRl
Control Status
Register 1
Not Used
3
L
H
H
TDRl
Transmit Data
Register 1
RDRl
Receive Data
Register 1
4
H
L
L
IER2
Interrupt Enable
Register 2
ISR2
Interrupt Status
Register 2
CR2
5
H
L
H
Control
Register 2'
CSR2
FR2
Format
Register 2"
Control Status
Register 2
CDR2
Compare Data
Register 23
ACR2
Auxiliary Control
Register 24
TDR2
Transmit Data
Register 2
6
7
H
H
H
H
L
H
Notes:
1. D7 must be set low to write to the Control Registers.
2. D7 must be set high to write to the Format Registers.
3. Control Register bit 6 must be set to 0 to access the Compare Register.
4. Control Register bit 6 must be set to 1 to access the Auxiliary Control Register.
6-232
Not Used
RDR2
Receive Data
Register 2
Dual Asynchronous Communications Interface Adapter (DACIA)
R68C552
SERIAL DATA CHANNELS
is high and the Transmit Shift Register is empty, the transmitter
(except for Echo Mode) is inhibited. When CTS is low, the
transmitter IS enabled.
Two independent serial data channels are available for the full
duplex (simultaneous transmit and receive) transfer of asynchronous frames. Separate internal registers are provided for each
channel for the selection of frame parameters (number of bits per
character, parity options, etc.), status flags, interrupt control and
handshake. The asynchronous frame format is shown in Figure 4.
I
;--T ----ii- ----, - - , - -,--,---r
L-l--_~- __ -N---- __ l ___ L_J
~ __ L
I I I
START
Transmit data from the host system is loaded into the Transmit Data
Register. From there, it is transferred to the Transmit Shift Register
where it is shifted, LSB first, onto the TxD line. All transmissions
begin with a start bit and end with the user selected number of
stop bits. A parity bit is transmitted before the stop bites) if panty
is enabled.
Register
RJW
0
4
ISRI
ISR2
R
0
4
IERI
IER2
W
1
5
CSRI
CSR2
R
1
5
CRI
CR2
W
1
5
FRI
FR2
W
2
6
CDRI
CDR2
(CR6
2
6
ACRI
ACR2
(CR6
3
7
RDRI
RDR2
R
3
7
TDRI
TDR2
W
Asynchronous Frame Format
INTERNAL REGISTERS
The DACIA contains ten control registers and four status registers
in addition to the transmit and receive registers. The Control
Registers provide for control of frame parameters, baud rate, interrupt generation, handshake lines, transmission and reception. The
status registers provide status information on transmit and receive
registers, error conditions and interrupt sources. Table 4 summarizes the bit definitions of these registers. A detailed description
follows.
Register Formats
Bit
W
= 0)
7
5
6
I
5T08BITS~
Figure 4.
Five I/O lines are provided for each channel for handshake with
the data communications equipment (DCE). Four of these signals
(ATS, DTR, DSR and DCD) are general purpose Inputs or outputs.
The fifth signal, CTS, enables/disables the transmitter. When CTS
Register
Select
(Hex)
PARITY I STOP
(OPT)
(1 OR 2 BITS)
MSB
[.
Receive data is shifted into the Receive Shift Register from the
associated RxD line. Start and stop bits are stripped from the frame
and the data is transferred to the Receive Data Register. Parity bits
may be discarded or stored in the ISA.
Table 4.
I I
LSB
4
3
2
0
Reset
Value
76543210
1 - 00000 -
- 0000000
1 - - - - 011
o
CDRI
ACR
I
.
STOP
BITS
ECHO
DATA BITS
I
PAR SEL
BIT R+ESEL
0- - - - - --
1-------
COMPA~E DATA
W
= 1)
00000000
6-233
II
R68C552
Dual Asynchronous Communications Interface Adapter (DACIA)
INTERRUPT STATUS REGISTERS (ISR1, ISR2)
INTERRUPT ENABLE REGISTERS (IER1, IER2)
The Interrupt Status Registers are read-only registers indicating
the status of each interrupt source. Bits 6 through 0 are set when
the indicated IRQ condition has occurred. Bit 7 is set to a 1 when
any IRQ source bit is set, or if Echo Mode is disabled, when CTS
is high.
The Interrupt Enable Registers are write-only registers that enable/disable the IRQ sources. IRQ sources are enabled by
writing to an IER with bit 7 set to a 1 and the bit for every IRQ source
to be enabled set to a 1. IRQ sources are disabled by writing to
an IER with bit 7 reset to a 0 and the bit for every source to be disabled setto a 1. Any source bit resetto 0 is unaffected and remains
in its original state. Thus, writing $7F to an IER disables all of that
channel's interrupts and writing an $FF to an IER enables all of
that channel's interrupts.
7
6
5
4
3
2
ANY
BIT
SET
TDRE
CTST
DCDT
DSRT
PAR
Address = 0,4
Bit 7
1
o
1
0
FIOIB RDRF
Reset Value
=
1 - 00000 -
Any Bit Set
Any bit (6 through 0) has been set to a 1 or CTS
is high with echo disabled
No bits have been set to a 1 or echo is enabled
Bit 6
1
Transmit Data Register Empty (TDRE)
Transmit Data Register is empty and CTS is low
Transmit Data Register is full or CTS is high
Bit 5
1
Transition On CTS Line (CTST)
A positive or negative transition has occurred on
CTS
No transition has occurred on CTS, or ISR has
been Read
o
7
6
5
4
3
2
1
0
SET
BITS
lORE
IE
CTST
IE
DCDT
IE
DSRT
IE
PAR
IE
FIOIB
RDRF
IE
Address = 0,4
IE
Reset Value = - 0000000
Enable/Disable
Enable selected IRQ source
Disable selected IRQ source
Bit 7
1
o
Bits 0-6
1
Select for enable/disable
No c~ange
o
CONTROL STATU:; REGISTERS (CSR1, CSR2)
o
Bit 4
1
o
Bit 3
1
o
Bit 2
1
o
1
o
Bit 1
1
o
Bit 0
1
o
The Control Status Registers are read-only registers that provide
I/O status and error condition information. A CSR is normally read
after an IRQ has occurred to determine the exact cause of the
interrupt condition.
7
Transition On DCD Line (DCDT)
A positive or negative transition has occurred on
FE
DeD
No transition has occurred on DCD, or ISR has
been Read
Address
A positive or negative transition has occurred on
o
DSR
No transition has occurred on DSR, or ISR has
been Read
Bit 6
1
o
Bit 5
1
Parity Status (PAR)
ACR bit 0
0
A parity error has occurred in received data
No parity error has occurred, orthe Receive Data
Register (RDR) has been Read
ACR bit 0 = 1
Parity bit = 1
Parity bit = 0
=
o
TUR
o
o
Bit 0
1
o
1
0
BRK
DTR
LVL
RTS
LVL
Reset Value
= 1 - - - - 011
Transmitter Underrun (TUR)
Transmit Shift Register is empty and TDRE is set
Transmitter Shift Register is not empty
CTS Level (CTS LVL)
CTS line is high
CTS line is low
DSR Level (DSR LVL)
DSR line is high
DSR line is low
Bit 1
1
2
Framing Error (FE)
A framing error occurred in receive data
No framing error occurred, orthe RDR was read
Bit 3
1
o
6-234
3
DSR
LVL
DCD Level (DCD LVL)
DCD line is high
DCD line is low
Bit 2
1
Receive Data Register Full (RDRF)
Receive Data Register is full
Receive Data Register is empty
4
DCD
LVL
Bit 4
1
o
Frame Error, Overrun, Break
A framing error, receive overrun, or receive break
has occurred or has been detected
No error, overrun, break has occurred or RDR
has been Read
5
CTS
LVL
= 1,5
Bit 7
1
Transition On DSR Line (DSRT)
6
Receive Break (BRK)
A Receive Break has occurred
No Receive Break occurred, or RDR was read
DTR Level (DTR LVL)
DTR line is high
DTR line is low
ATS Level (ATS LVL)
RTS line is high
RTS line is low
R68C552
Dual Asynchronous Communications Interface Adapter (DACIA)
CONTROL REGISTERS (CR1, CR2)
FORMAT REGISTERS (FR1, FR2)
The Control Registers are write-only registers. They control access
to the Auxiliary Control Register and the Compare Data Register.
They select the number of stop bits, control Echo Mode, and select
the data rate.
The Format Registers are write-only registers. They select the
number of data bits per character and parity generation/checking
options. They also control RTS and DTR.
(Accessed when Bit 7
7
3
(Accessed when Bit 7
2
Address = 1,5
Reset Value
Control or Format Register
Access Control Register
Bit 6
1
0
CDR/ACR
Access the Auxiliary Control Register (ACR)
Access the Compare Data Register (CDR)
Bit 5
1
0
Number of Stop Bits Per Character
Two stop bits
One stop bit
Bit 4
1
0
Echo Mode Selection
Echo Mode enabled
Echo Mode disabled
f
1
1
0
0
0
0
3-0
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
5
6
DATA
BITS
1
Address
= 0 -------
Bit 7
0
Bits
2
0
0
0
0
1
7
0
BAUD RATE SEL
0
3
0
0
0
0
0
0
0
0
= 0)
4
3
PAR
SEL
2
1
0
PAR
EN
DTR
CNTL
RTS
CNTL
= 1,5
Bit 7
1
Bits 6-5
= 1)
Reset Value = 1 - - - - - - -
Control or Format Register
Access Format Register
Number of Data Bits Per Character
6 5
o
o
0
5
o
6
7
8
Bits 4-3
4 3
o 0
Baud Rate Selection
(bits per second with 3.6864 MHz crystal)
50
109.2
134.58
150
300
600
1200
1800
2400
3600
4800
7200
9600
19200
38400
External TxC and RxC X16 Clocks
o
1
o
Odd Parity
Even Parity
Mark in Panty bit
Space in Parity bit
Bit 2
1
Parity Enable
Parity as specified by bits 4-3
No Parity
Bit 1
DTR Control
Set DTR high
Set DTR low
o
1
o
Bit 0
1
o
6-235
Parity Mode Selection
RTS Control
Set RTS high
Set RTS low
II
Dual Asynchronous Communications Interface Adapter (DACIA)
R68C552
OPERATION
COMPARE DATA REGISTERS (CDR1, CDR2)
The Compare Data Registers are write-only registers which can
be accessed when CR bit 6 = O. By writing a value into the CDR,
the DACIA is put in the compare mode. In this mode, setting of the
RDRF bit is inhibited until a character is received which matches
the value in the CDR. The next character is then received and the
RDRF bit is set. The receiver will now operate normally until the
CDR is again loaded.
(Control Register bit 6
=
TERMINATION OF UNUSED INPUTS
Noise on floating inputs can affect chip operation. All unused
inputs must be terminated. If unused, IACK1 and IACK2 must be
tied high. If the baud rate generator is bypassed, XTALI must be
connected to ground (XTALO is an output and must be left open).
If the external clock mode is not used, RxC and TxC may be tied
either to + 5V or to ground. If the handshake inputs are not
needed, the CTS inputs should be tied low to enable the transmitters. The DCD and DSR inputs may either be tied high or low.
0)
r-_7_____6_____5______
4 ______3_____2_______ ~
COMPARE DATA
.----------J
Address = 2,6
Reset Value = - - - - - - - -
TERMINATION OF DTACK
AUXILIARY CONTROL REGISTERS (ACR1, ACR2)
A current limiting resistor with a minimum value of 3.6 KG should
be connected between DTACK and + 5V.
The Auxiliary Control Registers are write-only registers. Bits 7-2
hold the user selected interrupt vector number to be output on data
lines 7-2 dUring interrupt acknowledge. Bit 1 causes the transmitter
to transmit a BREAK. Bit 0 determines whether parity error or the
parity bit is displayed in ISR bit 2.
(Control Register bit 6
7
6
5
4
= 1)
2
3
IRQ VECTOR ADDRESS
Address = 2.6
Bits 7-2
RESET INITIALIZATION
1
0
TRNS
BRK
PAR
ERR/ST
Reset Value
During power on initialization, all readable registers should be read
to assure that the status registers are initialized. Specifically, the
RDRF bit of the Interrupt Status Registers is not initialized by reset.
The Receiver Data Registers must be read to clear this bit.
TDRE IRQ is generated only on the transition of the corresponding
TDR from full to empty. Initialization software must account for this
occurrence.
= -- -- - - 00
IRQ Vector Address
Bit 1
1
Transmit Break (TRNS BRK)
Transmit continuous Break
Normal transmission
o
Bit 0
1
BAUD RATE CLOCK OPTIONS
The receiver and transmitter clocks may be supplied either by the
internal Baud Rate Generator or by user supplied external clocks.
Both channels may use the same clock source or one may use
the Baud Rate Generator and the other channel external clocks.
If both channels use the Baud Rate Generator, each channel may
have a different bit rate. The options are shown in Figure 5.
Parity Error/State (PAR ERR/ST)
Send value of parity bit to ISR bit 2 (Address
Recognition mode)
Send Parity Error status to ISR bit 2
o
RECEIVE DATA REGISTERS (RDR1, RDR2)
An internal clock oscillator supplies the time base for the Baud
Rate Generator. The oscillator can be driven by a crystal or an
external clock.
The Receive Data Registers are read-only registers which are
loaded with the received data character of each frame. Start bits,
stop bits and parity bits are stripped off of incoming frames before
the data is transferred from the Receive Shift Register to the
Receive Data Register. For characters of less than eight bits, the
unused bits are the high order bits which are set to O.
MSB
7
If the on-chip oscillator is driven by a crystal, a parallel resonant
crystal is connected between the XTALI and XTALO pins. The
equivalent oscillator circuit is shown In Figure 6.
LSB
6
5
4
3
2
A parallel resonant crystal is specified by its load capacitance and
series resonant resistance. For proper oscillator operation, the load
capacitance (C L), series resistance (Rs) and the crystal resonant
frequency (F) must meet the following two relations:
o
RECEIVE DATA
Address
= 3,7
Reset Value = 00000000
TRANSMIT DATA REGISTERS (TDR1, TDR2)
(C + 2) = 2C L
The Transmit Data Registers are write-only registers which are
loaded from the CPU with data to be transmitted. For data characters of less than eight bits, the unused bits are the high order bits
which are "don't care".
MSB
C = 2C L
-
2
Rs :5 Rsmax = 2 X 106
(FCd 2
where: F is in MHz; C and C L are in pF; R is in ohms.
LSB
7
5
4
3
2
To select a parallel resonant crystal for the oscillator, first select
the load capacitance from a crystal manufacturer's catalog. Next,
calculate Rsmax based on F and C L• The selected crystal must
have a Rs less than the Rsmax.
o
TRANSMIT DATA
Address
or
= 3,7
Reset Value = - - - - - - - -
6-236
R68C552
Dual Asynchronous Communications Interface Adapter (DACIA)
CLOCK INPUT
I----<.----i XTALI
o
LJlMfl
OPEN CIRCUIT
XTALI
XTALO
I - - -....- - - i XTALO
TxC
• Baud rate determined by XTALI frequency and 1 of 15 divisors selected in
CRI and CR2. CRI and CR2 must not be
set to all ones.
• Channel 1 baud rate may be different
from channel 2 baud rate.
• Receiver baud rate must be the same as
transmitter baud rate.
RxC
A. Both Channels Use Internal Baud Rate Generator
16 x Tx BAUD RATE
• Transmitter baud rate 1116 TxC input
frequency.
nIlJlJl
• Receiver baud rate 1116 RxC Input
frequency.
16 x Rx BAUD RATE
~
INTERNAL CLOCK
OSCILLATOR DISABLED
• Channell baud rate is the same as
channel 2 baud rate.
• Receiver baud rate may be different from
transmitter baud rate.
XTALO
• Bits 3-0 of CRI and CR2 must be set to
all ones.
B. Both Channels Use External Clocks
r
CLOCK INPUT
1----+-----10 XTALI
B
• Channell baud rate may be different
from channel 2 baud rate.
OPEN CIRCUIT
XTALO
• Transmitter baud rate may be different
from receiver baud rate on channel
using external clock.
16 x Tx BAUD RATE
lJUl
TxC
TxC
16 x Rx BAUD RATE
1JlJL
16 x Rx BAUD RATE
lJUl
XTALI
XTALO
16 x Tx BAUD RATE
1J1Jlf
UlJlf
RxC
RxC
C. One Channel Uses Internal Baud Rate Generator;
One Channel Uses External Clocks
Figure 5.
Baud Rate Clock Options
6-237
II
Dual Asynchronous Communications Interface Adapter (DACIA)
R68C552
The series resistance of the crystal must be less than
R,max =
C±5%
XTLI
2 pF
t--+---i f---+------1
XTLO
I
H
2 pF
2x106
(3.6864 x 22)2
= 304 ohms
If the on-chip oscillator is driven by an external clock, the clock
is input at XTALI and XTALO is left open.
R68C552
An internal counter/divider circuit divides the frequency input at
XTALI by the divisor selected in bits 3 through 0 of the Control
Registers. Table 5 lists the divisors that may be selected and shows
the bit rates generated with a 3.6864 MHz crystal or clock input.
Other bit rates may be generated by changing the clock or crystal frequency. However, the input frequency must not exceed
4 MHz.
-=-
Figure 6.
For example, if C L
crystal, then
For external clock operation, a transmitter times 16 clock must be
supplied at TxC and a receiver times 16 clock must be input at RxC.
Since there are separate receiver and transmitter clock inputs, the
receiver data rate may be different from the transmitter data rate.
= 22 pF for a 3.6864 MHz parallel resonant
C = (2 x 22) - 2 = 42 pF (use standard value of 43 pF)
Table 5.
Control
Register
Bits
Baud Rate Generator Divisor Selection
3
2
1
0
Divisor Selected
For The
Internal Counter
0
0
0
0
73,728
0
0
0
1
33,538
0
0
1
0
27,408
0
0
1
1
24,576
0
1
0
0
12,288
0
1
0
1
6,144
0
1
1
0
3,072
0
1
1
1
2,048
1
0
0
0
1,536
1
0
0
1
1,024
1
0
1
0
768
1
0
1
1
512
1
1
0
0
384
1
1
0
1
192
1
1
1
0
96
1
1
1
1
16
'Baud Rate
=
Baud Rate Generated
With 3.6864 MHz
Crystal or Clock
Baud Rate Generated'
With a Crystal or Clock
of Frequency (f)
(3.6864 x 10')/73,728
= 50
= 109.92
(3.6864 x 10')/27,408 = 134.58
(3.6864 x 10')/24,576 = 150
(3.6864 x 10')/12,288 = 300
(3.6864 x 10')/6,144 = 600
(3.6864 x 10')/3,072 = 1,200
1/73,728
(3.6864 x 10')/33,538
1133,538
(3.6864 x 10')/2,048
= 1,800
= 2,400
(3.6864 x 10')/1,024 = 3,600
(3.6864 x 10')1768 = 4,800
(3.6864 x 10')/512 = 7,200
(3.6864 x 10')/384 = 9,600
(3.6864 x 10')/192 = 19,200
(3.6864 x 10')/96 = 38,400
Transmitter Baud Rate = TxC/16
(3.6864 x 10')/1 ,536
Frequency
Divisor
6-238
1/27,408
1124,576
1112,288
116,144
113,072
112,048
1/1,536
1/1,024
fl768
1/512
1/364
11192
1/96
Receiver Baud Rate
= RxC/16
Dual Asynchronous Communications Interface Adapter (DACIA)
R68C552
CONTINUOUS DATA TRANSMIT
word to the TOR the TORE bit is cleared. In order to maintain continuous transmission the TOR must be loaded before the stop bit(s)
are ended. 1/16 of a bit time after IRQ goes low, the IRQ line may
be reset by reading the IRS. IRQ will always reset when data is
written to the TOR. Figure 7 shows the relationship between IRQ
and TxO for the Continuous Oata Transmit mode.
In the normal operating mode, the TORE bit in the ISR signals the
MPU that the OACIA is ready to accept the next data word. An IRQ
occurs on the transition of the TOR from full to empty if the corresponding TORE IRQ enable bit is set in the lEA. The TORE bit
is set at the beginning of the start bit. When the MPU writes a
CHAR #n + 1
CHAR #n
1
CHAR #n + 2
I
/
CHAR #n + 3
I
'J
I
"-/
I
,./
"-
TX~ t rs;a~]~]iJ t t fBOFl~~ GEl t I t ["B:"r~I~ GEl t I t rqs:]~]~]iJ t L
lSTART
STOP ,START
IRU
lJ]'
STOP: START
tJlJ
Lw
~
'-'\
/
PROCESSOR
INTERRUPT
(TRANSMIT DATA
REGISTER EMPTY)
STOP: START
PROCESSOR
READS
ISR, CAUSES
IRQ TO CLEAR
Figure 7.
TxD
IRQ
r--"'T"--r-,:..-----
/
STOP
UNDERRUN BIT
SET
Figure 8.
I
CHAR#n + 2
\ /
I
II tffi~]~liJ t II t rqs:]~~~
StART
ILlD
f' -----/....,.---/---..'
PROCESSOR
INTERRUPT
FOR DATA
EMPTY
CHAR #n + 1
CONTINUOUS "MARK"
TtlI t rs:FJ~~GEl t I
I
STOP START
PROCESSOR MUST
LOAD NEW DATA
IN THIS TIME
INTERVAL OTHERWISE,
CONTINUOUS "MARK"
IS TRANSMITTED
(TUR) is set. This condition persists until the TOR is loaded with
a new word. Figure 8 shows the relation between IRQ and TxO for
the Transmit Underrun Condition.
Ifthe MPU is unable to load the TOR before the last stop bit is sent,
the TxO line goes to the MARK condition and the underrun flag
/
l
Continuous Data Ti'ansmit
TRANSMIT UNDERRUN CONDITION
CHAR #n
I
STOP:
PROCESSOR READS
ISR, CLEARS IRQ
UJrrr---
~WHEN PROCESSOR FINALLY LOADS
NEW DATA, TRANSMISSION STARTS
IMMEDIATELY AND INTERRUPT
OCCURS, INDICATING TRANSMIT
DATA REGISTER EMPTY
Transmit Underrun Condition Relationship
6-239
STOP START
•
R68C552
Dual Asynchronous Communications Interface Adapter (DACIA)
one character time to assure that a proper BREAK is transmitted.
If the Transmit Break bit is cleared before one character time of
BREAK has been transmitted, the BREAK will be terminated after
one character time has elapsed. If the Transmit Break bit is cleared
after one character time of BREAK has been transmitted, the
BREAK will be terminated immediately. Figure 9 shows the relationship of TxO, IRQ and ACR bit 1 for various BREAK options.
TRANSMIT BREAK CHARACTER
A BREAK may be transmitted by setting bit 1 of the ACR (Transmit Break bit) to a 1. The BREAK is transmitted after the character in the Transmit Shift Register is sent. If there is a character in
the Transmit Data Register, it will be transmitted after the BREAK
is terminated. The Transmit Break bit must remain set for at least
STOP START
TxD
ACR
BIT 1
STOP START
STOP START
STOP START
~]~B r 1t rs;§[~ *1 t ~=~; 1t [igB~[~
r"T,.T-n TrT1
I" I
. . II _______________________________________________________
I
I II
UI~I~'~'
TDRE~'
I I
IRQ
J
Ll]'
I
LIJ'
I
I
J
UJ'
I
I
J
I
J
a. li"ansmlt Break bit cleared before BREAK begins-BREAK is ignored
STOP START
STOP
STOP START
STOP START
~= IS0 t .....L....-'-B'-R....JEA_K-'--~rtl t [BOJi!I]~d£J tit @!§[~~=
ACR
1-'--'--'
:--r-, : :
BIT 1
TxD
,-I
I
I
__
II
I
I
L_J._
.L_.J
I
'
I
,
TDRE~'
IRQ
I
J
I
,
W'
I
L1J'
,
J
'
I
J
b. Transmit Break bit cleared during first character time of BREAK-BREAK terminates after one character time
STOP START
rxD
ACR
BIT 1
TDRE
IRQ
STOP
STOP START
---irtl t (SOfS1J= &I!J
~~ §i] t IL.._ _ _ _ _BR_E_A_K_ _ _ _
________ rTT-,-I--------------------------------------, ___________________
~:~:_L:~
~
I
I
~'
J
W'
I
I
J
c. Transmit Break bit cleared after first charscter time of BREAK-BREAK terminates immediately
Figure 9.
"IhInsmlt BREAK
EFFECTS OF CTS ON TRANSMITTER
Any transition on CTS sets bit 5 (CTST) of the ISR. A high on CTS
forces bit 6 C!QBE) of the ISR to a O. Bit 7 of the ISR also goes
to a 1 when CTS is high, if Echo Mode is disabled. Thus, when
the ISR is $80, it means that CTS is high and no interrupt source
requires service. A processor interrupt will not be generated under
these circumstances, but an ISR polling routine should accommodate thiS.
The CTS control line controls the transmission of data or the handshaking of data to a "busy" device (such as a printer). When the
CTS line is low, the transmitter operates normally. A high condition inhibits the TORE bit in the ISR from becoming set. Transmission of the word currently in the shift register is completed but any
word in the TOR is held until CTS goes low.
CHAR #n + 1
CHAR #n
TxD
-----'I---~"
/
I
"
B.]~~EJ t I t [BJBJ~ IBN Ipit
STOP START
LJI]
STOP
f
CONTINUOUS MARK
LLI t IBolB,1
NEXT
CHARACTER
IS NOT SENT
TORE IS NOT SET
CTSJ_________________
IRQ
START
WHEN PROCESSOR
FINALLY LOADS
NEW DATA,
TRANSMISSION STARTS
'\
CTS
iRQ
INTERRUPT OCCURS,
INDICATING TRANSMIT
DATA REGISTER EMPTY
-'~.~MEDIATELY AND
MPU
CLEARS
IRQ
Effects of CTS on Transmitter
6-240
':=
MPU
CLEARS
IRQ AGAIN
\
C~L_E~A~R._T~O~.S~E~N~D_______'I
CTS _________
Figure 10.
NEXT CHARACTER IS SENT IMMEDIATELY
UPON CTS GOING LOW IF PROCESSOR
HAS ALREADY LOADED NEW DATA,
OTHERWISE IT WAITS FOR NEW DATA
I
Dual Asynchronous Communications Interface Adapter (DACIA)
R68C552
ECHO MODE TIMING
underflow flag would be set and continuous Mark transmitted. If
Echo is initiated, the underflow flag will not be set at end of data
and continuous Mark will not be transmitted. Figure 11 shows the
relatIOnship of RxD and TxD for Echo Mode.
In the Echo Mode, the TxD line re-transmits the data received on
the RxD line, delayed by 1/2 of a bit time. An internal underrun
mode must occur before Echo Mode will start transmitting. In normal transmit mode if TORE occurs (indicating end of data) an
STOP
RxD
TxD
START
STOP
START
STOP
~~]~EJ
END OF
DATA
tit ~~]~~0 ~
\1 \ \ \ \ \ \ \ \ \ \ \ _________ ~O:6~~gH~ ::~~:
~:rTLJE;r~~[ =EEl t I t ~[S:I I~JiJ t [= ===
STOP START
L - I/ _ _ _
STOP ~
STOP START
IF ECHO MODE,
NO UNDERFLOW,
THEREFORE NO
CONTINUOUS MARK
Figure 11.
Echo Mode Timing
CONTINUOUS DATA RECEIVE
RDR before the next stop bit, or an overrun error occurs. Figure 12
shows the relationship between IRQ and RxD for the continuous
Data Receive mode.
The normal receive mode sets the RDRF bit in the ISR when the
DACIA channel has received a full data word. This occurs at about
the 9116 pOint through the stop bit. The processor must read the
CHAR #n
/
CHAR #n + 1
I
"-./
I
CHAR #n + 2
"-./
CHAR #n + 3
I
'-.../
I
"-
RX~ t [80FT ~ EEl II t [iOFJ ~ =EElII t r:FJ~ ]~JiJI I t fSOIBJ~ ]~d~J I
START
STOP: START
STOP: START
I
I
/LJ]
IR~nT"----;LJD'
IRQ PROCESSOR
INTERRUPT OCCURS
ABOUT 9116 INTO
LAST STOP BIT
PARITY OVERRUN,
AND FRAMING ERROR
UPDATED ALSO
)
\ ~
PROCESSOR READS
ISR, CAUSES
IRQ TO CLEAR
Figure 12.
START
un
I
PROCESSOR MUST READ
RECEIVER DATA IN THIS
TIME INTERVAL, OTHERWISE
OVERRUN OCCURS
Continuous Data Receive
6-241
STOP:
L
L
STOP:
I
•
Dual Asynchronous Communications Interface Adapter (DACIA)
R68C552
contains the last word not read by the MPU and all following data
is lost. The receiver will return to normal operation when the RDR
is read. Figure 13 shows the relationship of IRQ and RxD when
overrun occurs.
EFFECTS OF OVERRUN ON RECEIVER
If the processor does not read the RDR before the stop bit of the
next word, an overrun error occurs, the overrun bit is set in the ISR,
and the new data word is not transferred to the RDR. The RDR
CHAR #n + 1
CHAR #n
---...../
I
CHAR #n + 2
CHAR #n + 3
I
I
!
'-./
'-./
'-./
[BOJBJ~~GE! I t [BOJBJ~~GE/I t rn~~GE/I t [BOJBJ~~~
STOP I START
STOP I START
ISTOP I START
RXDJ/ll
STOP
ART
I s1
IRQ
-un
nL.-....:::--___
I
I t '
PROCESSOR /
INTERRUPT
FOR RECEIVER
DATA REGISTER
FULL
MPU DOES
NOT READ
RDR. OVERRUN
BIT SET
Figure 13.
MPU READS
ISR
CLEARS IRQ
CHAR #n + 2
IRQ.
CHAR#n + 1
IS LOST
Effects of Overrun on Receiver
RECEIVE BREAK CHARACTER
When a Break character is received, the Break bit is set. The
receiver does not set the RDRF bit and remains in this state until
a stop bit is received. At this time the next character is received
--------.....'-.
RxD
18,'--IBNJP II
normally. Figure 14 shows the relationship of IRQ and RxD for
a Receive Break Character.
CONTINUOUS "BREAK"
It
..l.2J--~tl STA~T
Bo
B.
I
BN
1--1
I ST01 1 (II
;L.JJrri
U
1 ~
f
PROCESSOR
INTERRUPT
FOR
RECEIVER
DATA REGISTER
FULL
m
t ~_-_-IBNJP
I SiA~
~~I
STOP /
.
I
t
IBoIB.1
START'
NO-- ' " NO INTERRUPT
MORE
SINCE RECEIVER.
INTERRUPTS
DISABLED UNTIL
FIRST START BIT
.
n----
II
Receive Break Character
6-242
I
l..._...1.1
PROCESSOR
INTERRUPT
WITH BREAK AND FRAMING ERROR BIT SET.
EVEN PARITY CHECK WILL ALSO GIVE A PARITY
ERROR BECAUSE ALL ZEROS (CONTINUOUS
BREAK) REPRESENT EVEN PARITY.
Figure 14.
,,/~----
II
P
r
NORMAL
RECEIVER
INTERRUPT
Dual Asynchronous Communications Interface Adapter (DACIA)
R68C552
FRAMING ERROR
reflects the last data word received. Figure 15 shows the relationship of IRQ and RxD when a framing error occurs.
Framing error is caused by the absence of stop bit(s) on received
data. The framing error bit is set when the RDRF bit is set. Subsequent data words are tested separately, so the status bit always
STOP STOP
RxD
(EXPECTED)
2
-,---.---,...11'"-r""-F-r
I B61 P I
~
STOP
1
RxD
(ACTUAL)
I ; I
START
I
STOP STOP START
1
I Bo I B, I B2 I B31 B.I Bsl Bol P I \
1 I 2/r
STOP
STOP START
1121
B o I B, I B21 B3 \ B.I Bsl Bol P
I
7 I 5[
2
I
I~
STOP START
1-11 R
I
I
NOTES: 1. FRAMING ERROR DOES NOT
INHIBIT RECEIVER OPERATION.
PROCESSOR
INTERRUPT,
FRAMING
ERROR
BIT SET
2. IF NEXT DATA WORD IS OK,
FRAMING ERROR IS CLEARED.
Figure 15.
Framing Error
PARITY ERROR DETECT/ADDRESS
FRAME RECOGNITION
this type of operation, bit 0 of the ACR is set to a 1 and bits 2, 3
and 4 olthe FR select a parity checking mode. Then, ISR bit 2 will
be set to a 1 by incoming address frames and it will be a 0 on data
frames.
The Parity Status bit (ISR bit 2) may be programmed to indicate
parity errors (ACR bit 0 = 0) or to display the parity bit received
(ACR bit 0 = 1).
COMPARE MODE
In applications where parity checking is used, one of the parity
checking modes is enabled by setting bits 2, 3 and 4 of the Format Register to the desired option and bit 0 of the Auxiliary Control Register is reset to O. Then, when the RDRF bit (bit 0) is set
in the ISR, the PAR bit (bit 2) will be set when a parity error is
detected.
The Compare Mode is automatically enabled, i.e., the channel is
put to sleep, whenever data is written to the Compare Data
Register. NOTE: Bit 6 of the Control Register must be set to 0 to
enable access to the Compare Data Register. When the channel
is in the compare mode, the RDRF bit (bit 0 of the ISR) is forced
to a O. Upon receipt of a matching character, normal receiver operation resumes and the RDRF bit (bit 0 of the ISR) will be set upon
receipt of the next character.
In multi-drop applications, the parity bit is used as an address/data
flag. It is set to 1 for address frames and is 0 on data frames. For
6-243
•
I
Dual Asynchronows Communications Interface Adapter (DACIA)
R68C552
SPECIFICATIONS
DACIA READ/WRITE WAVEFORMS
~CD
I
-CD~ I-----~®
®
RSO-RS2
\\' \\' \\'
R/W (lfflifff)
-=:I@ I -
{-,) r--
/
'l.
0)
r--0~
( / / / / ) (/1
.
/
0)
r--
·01
1----0
~0~1
00-07
I
-ev-t-~0
levi
-0f:::
;;r
-0---
I
~------ READ C Y C L E - - - - - - l + \ . - - - - - W R I T E C Y C L E - - - !
NOTE: TIMING MEASUREMENTS ARE REFERENCED TO AND FROM A LOW VOLTAGE OF O.BV AND A HIGH VOLTAGE OF 20V,
UNLESS OTHERWISE NOTED.
DACIA READ/WRITE CYCLE TIMING
(Vee
= 5 Vdc ± 5%, Vss = 0 Vdc, TA = T L to T H, unless otherwise noted)
Number
Characteristic
Symbol
Min.
Max.
Unit
-
ns
55
ns
170
ns
170
ns
110
ns
10
50
ns
Tosu
30
-
ns
CS High to Data Invalid (Write Hold)
Teow
10
-
ns
DS Low to CS Low (Delay for CS
derived from Data Strobe)
Tose
1
RIW, RSO·RS2 Valid to CS Low (Setup)
TRSU
2
CS Low to RIW, RSO·RS21nvalid (Hold)
TRH
45
3
CS Pulse Width
Tep
210
4
CS Low to DTACK Low
TeTL
-
5
CS High to DTACK High
TeTH
6
CS Low to Data Valid (Read)
Teov
7
DTACK Low to Data Valid (Read)
Trov
S
CS High to Data Invalid (Read)
TeoR
9
Data Valid to CS High (Write, Setup)
10
11
6-244
Typ.
5
0
-
20
ns
ns
ns
Dual Asynchronous Communications Interface Adapter (DACIA)
R68C552
DACIA TRANSMIT/RECEIVER WAVEFORMS
'IlIc, RxC
'IlID
----:+~
NOTE: TIMING MEASURE·
MENTS ARE REFERENCED
10 AND FROM A LOW
VOLTAGE OF OJN AND A
HIGH VOLTAGE OF 2.0V,
UNLESS OTHERWISE
NOTED.
RTS, DTS _ _ _ _ _ _ _ _ _ _ __
DACIA INTERRUPT ACKNOWLEDGE WAVEFORMS
NOTE: TIMING MEASURE·
MENTS ARE REFERENCED
10 AND FROM A LOW
VOLTAGE OF O.BV AND A
HIGH VOLTAGE OF 2.(N,
UNLESS OTHERWISE
NOTED.
NOTE: CS MUST BE HIGH
DURING lACK CYCLE.
TRANSMIT/RECEIVE AND INTERRUPT ACKNOWLEDGE TIMING
(Vcc
= 5 Vdc
Number
± 5%, Vss
= 0 Vdc, TA = Tl to T H' unless otherwise noted)
Characteristic
Symbol
Min.
Max.
Unit
-
ns
285
ns
285
ns
TRANSMIT/RECEIVE TIMING
12
Transmit/Receive Clock Rate
lev
300
13
Transmit/Receive Clock High
tCH
125
14
Transmit/Receive Clock Low
tCl
125
15
TxC, RxC to TxD Propagation Delay
100
16
TxC, RxC to iRQ Propagation Delay
to!
17
crs, oeo, DSR Valid to IRQ Low
ten
18
iRa Propagation Delay (Clear)
tiRO
19
R"fS,
IolY
DTR Propagation Delay
-
ns
ns
150
ns
150
ns
150
ns
INTERRUPT ACKNOWLEDGE TIMING
22
iACK High to DTACK High
tlTH
-
23
iACK High to Data Invalid
t lOZ
10
20
iACK Low to Data Valid
tlOV
21
lACK Low to DTACK Low
tlTl
6-245
170
ns
62
ns
170
ns
40
ns
•
R68C552
Dual Asynchronous Communications Interface Adapter (DACIA)
ABSOLUTE MAXIMUM RATINGS*
Parameter
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Commercial
Industrial
Storage Temperature
Symbol
Value
Unit
Vee
-0.3 to +7.0
Vdc
VIN
- 0.3 to Vee + 0.3
Vdc
VOUT
-0.3 to Vee +0.3
Vdc
• NOTE:
Stresses above those listed may cause permanent
damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above
those indicated in other sections ofthis document is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
°C
TA
o to +70
-40 to +85
TSTG
- 55 to +150
°C
OPERATING CONDITIONS
Parameter
Symbol
Value
Supply Voltage
Vee
5V±5%
Temperature Range
Commercial
Industrial
TA
o to ?OoC
- 40°C to + 85°C
DC CHARACTERISTICS
(Vee = 5.0 V ±5%, Vss = 0, TA = TL to T H, unless otherwise noted)
Parameter
Symbol
Input High Voltage
Except XTALI
XTALI
VIH
Input low Voltage
Except XTALI
XTALI
VIL
Input leakage Current
RiW, RES, RSO, RS1, RS2, RxD, CTS, DCD, DSR, RxC,
TxC, CS. lACK
liN
Input leakage Current for Three-State Off
DO-D7
ITSI
Output High Voltage
DO-D7, TxD, ClK OUT, RTS, DTR
VOH
Output low Voltage
DO-D7, TxD, CLK OUT, RTS, DTR
Min
+2.0
+3.0
'iYP
-
Max
Unit
Test Conditions
V
-
Vee + 0.3
Vee + 0.3
-
+0.8
+0.4
-
10
50
~A
VIN
OV to 5.OV
Vee = 5.2SV
-
±2
10
~A
VIN = 0.4V to 2.4V
Vee
5.2SV
+2.4
-
-
V
Vee
4.7SV
ILOAO = -100 ~
VOL
-
-
+0.4
V
Vee
'LOAD
Output leakage Current (Off State)
IRQ, DTACK
IOFF
-
±2
±10
~
Power Dissipation
PD
-
-
10
mW/MHz
Input Capacitance
Except XTALI
XTALI
CIN
-
-
S
10
pF
pF
10
pF
Output Capacitance
-0.3
-0.3
-
COUT
Nolee
1. All units are direct current (dc) except for capacitance.
2. Negative sign indicates outward current flow, positive indicates inward flow.
3. Typical values are shown for Vee = 5.0V and TA = 25°C.
6-246
V
=
=
=
= 4.7SV
= 1.6 mA
Vec = S.2SV
VOUT = 0 to 2.4V
-
Vee = S.OV
VIN - OV
f = 2MHz
TA
2SoC
=
Dual Asynchronous Communications Interface Adapter (DACIA)
R88C552
PACKAGE DIMENSIONS
4O-PIN CERAMIC DIP
[ D,. ::I]
I·
DIM
A
•
C
D
F
·1
~F
Q
+
H
~n
M-l
H~li.D
0-11-
J
K
L
II
N
K- J
--jof.
F ..... D
K
MAX
Q
H
J
K
L
II
N
44-PIN PLASTIC LEADED CHIP CARRIER (PLCC)
~:;;u
iT'
Dr
flt±
01
L
I
~,
0
31-
21
CHAM.J • 45"
lli~u JU~~~
'O~
J
~~
l~
[fiJirL
~ 100.
:ir
AI
b
D
Dl
OJ
D3
•h
J
~~.
R
~'l
SECTION A-,.
TYP FOR BOTH AXIS (EXCEPT FOR BEVELED EDGE)
~I-b
EJECTOR PIN MARKS
4 PLCS aonOM OF
PACKAGE ONLY
(TYPICAL)
uul
CHAM.
11 PINS
11.45" PER SIDE
3PLCS
~
+
~I'~
SIDE VIEW
TOP VIEW
20·
~
A
Al
i..
INDICATOR
-17
~ SEATING PLANE
EQUALLY
SPACES
BOnOMvlEW
6-247
INCHIS
- -
A
8
C
D
F
M
IlLUIIETDS
IIAX
5182 52.32
13.48 13.97
358
508
0.38
0.53
1.02
1.52
2.54BSC
1.86
216
0.20
0.30
330
4.32
15.24BSC
7'
10'
0.51
1.02
MAX
DIll
*~~
INCHES
IIAX
1980 2.020
0.595 0.825
0.100 0.186
0.015 0.021
0Q3Q 0050
O.lOOBSC
0.Q3Q 0Q7Q
0.008 0013
0.100 0.185
0.575 0.805
10'
0'
0020 0080
--
4O-PIN PLASTIC DIP
[:::::::~:::::::::p rei
-
IIIWMETERS
IIIN
MAX
60.29 5131
15.11
15.88
2.54
4.19
0.38
053
0.78
1.27
254BSC
0.78
1.78
020
0.33
254
4.19
14.80 15.37
10'
0'
0.51
152
·
R
R1
IIIUI!IETEM
IIIN
MAX
414
4.39
1.37
147
2.31
248
0.487TVP
1748 17.80
16.48 1658
12.62 1278
15.78 REF
1.27BSC
115TVP
O.25TVP
4S 0 TYP
089TVP
025TVP
2.040 2.080
0.530 0.560
0.140 0.2DD
0.015 0.021
0.040 0.080
o looBSC
0085 0085
0.006 0.012
0.130 0170
O.8QQBSC
10'
7'
0020 0.04Q
_IS
0.183 0.173
0.054 0.058
0.091 0.097
0.018TVP
0887 I 0893
0648 I 0.862
0497 I 0.503
o 820 REF
O.05OBSC
o 045 TVP
0010TVP
45°TYP
OQ35TVP
0.010TVP
•
R68560 • R68561
'1'
Rockwell
R68560, R68561
Multi-Protocol Communications
Controller (MPCC)
DESCRIPTION
FEATURES
The R68560, R68561 Multi-Protocol Communications Controller
(MPCC) interfaces a single serial communications channel to
a 68008/68000 microcomputer-based system using either asynchronous or synchronous protocol. High speed bit rate, automatic formatting, low overhead programming, eight character
buffering, two channel DMA interface and three separate interrupt vector numbers optimize MPCC performance to take full
advantage of the 68008/68000 processing capabilities and
asynchronous bus structure.
• Full duplex synchronous/asynchronous receiver and transmitter
• Implements IBM Binary Synchronous Communications (BSC)
in two coding formats: ASCII and EBCDIC
• Supports other synchronous character-oriented protocols
(COP), such as six-bit BSC, X3.28k, ISO IS1745, ECMA-16, etc.
• Supports synchronous bit oriented protocols (BOP), such as
SDLC, HDLC, X.25, etc.
• Asynchronous and isochronous modes
• Modem handshake interface
• High speed serial data rate (DC to 4 MHz)
• Internal oscillator and baud rate generator with programmable data rate
In synchronous operation, the MPCC supports bit-oriented
protocols (BOP), such as SDLC/HDLC, and character-oriented
protocols (COP), such as IBM Bisync (BSC) in either ASCII or
EBCDIC coding. Formatting, synchronizing, validation and error
detection is performed automatically in accordance with protocol
requirements and selected options. Asynchronous (ASYNC) and
isochronous (ISOC) modes are also supported. In addition,
modem interface handshake signals are available for general
use.
•
Crystal or TTL level clock input and buffered clock output
(8 MHz)
•
•
Direct interface to 68008/68000 asynchronous bus
Eight-character receiver and transmitter buffer registers
• 22 directly addressable registers for flexible option selection,
complete status reporting, and data transfer
Control, status and data are transferred between the MPCC and
the microcomputer bus via 22 directly addressable registers and
a DMA interface. Two first-in first-out (FIFO) registers, addressable through separate receiver and transmitter data registers,
each buffer up to eight characters at a time to allow more MPU
processing time to service data received or to be transmitted
and to maximize bus throughput, especially during DMA operation. The two-channel Direct Memory Access (DMA) interface
operates with the MC68440/MC68450 DMA Controllers. Three
prioritized interrupt vector numbers separately support receiver,
transmitter and modem interface operation.
• Three separate programmable interrupt vector numbers for
receiver, transmitter and serial interface
An on-chip oscillator drives the internal baud rate generator
(BRG) and an external clock output with an 8 MHz input crystal
or clock frequency. The BRG, in conjunction with two selectable prescalers and 16-bit programmable divisor, provides a data
bit rate of DC to 4 MHz.
• Selectable parity (enable, odd, even) and CRC (control field
enable, CRC-16, CCITT V.41, VAC/LRC)
•
Maskable interrupt conditions for receiver, transmitter and
serial interface
•
Programmable microprocessor bus data transfer; polled, interrupt and two-channel DMA transfer compatible with
MC684401MC68450
• Clock control register for receiver clock divisor and receiver
and transmitter clock routing
• Selectable full/half duplex, autoecho and local loop-back
modes
ORDERING INFORMATION
Part Number
The 48-pin R68561 supports word-length (l6-bit) operation when
connected to the 68000 16-bit asynchronous bus, as well as bytelength (8-bit) operation when connected to the 68008 8-bit bus.
The 4O-pin R68560 supports byte-length operation on the 68008
bus.
R6856
TI
L
Frequency
Temperature Range
ooe to 70 e
0
Package: :M=H:eramic
P
= Plastic
Number of pins: 0 = 40
1 - 48
Document No. 68650N06
Product Description
6-248
Order No. 705
Rev. 6. June 1987
Multi-Protocol Communications Controller (MPCC)
R68560, R68561
·cc_
~_ _ _ _ _ _
OND_
TxD
TO RIC LOGIC
(TEST MODE)
12K
IIICROPROCESSOR
BUS
INTERFACE,
DC>D7'
Il0-l)'Ci'
iliiCK
IIIW
iliiiiii'
CONTROL
REGISTERS
AND
STATUS
REGISTERS
'"
~~~~
CiS
6CD
iiSiI
BAUD RATE GENERATOR
iiiiilAO'
iiiiEi'
1-----------t------TxC
RxAFOREAD
r----.BCLK
TxFlFOWRtTE
EXTAL
XTAL
TDiA
iiDSR
DiCK
DiC
lRINE
I----f-------
DMA
INTERFACE
AxC
RxFIFOREAD
TO rx LOGIC
(ECHDMODE)
1+-_ _ _....._ _
AxD
NOTES:
1. R68560 ONLY.
2. R68561 ONLY.
3. UDS ON R68561 All ON R68560
4. LDS ON R68561 DS ON R88560
Figure 1.
MPCC Block Diagram
PIN DESCRIPTION
Al-A4-Acldress Lines. A1-M are active high inputs used in
conjunction with the CS input to access the internal registers.
The address map for these registers is shown in Table 1.
Throughout the document, signals are presented using the terms
active and inactive or asserted and negated independently of
whether the signal is active in the high-voltage state or low·
voltage state. (The active state of each logic pin is described
below.) Active low signals are denoted by a superscript bar. For
example, Rm indicates write is active low and read is active
high.
00-015-0ata Lines. The bidirectional data lines transfer data
between the MPCC and the MPU, memory or other peripheral
device. 00-015 are used when connected to the 16-bit 68000
bus and operating in the MPCC word mode. 00-07 are used
when connected to the 16-bit 68000 bus or the 8-bit 68008 bus
and operating in the MPCC byte mode. -; ne data bus is threestated when CS is inactive. (See exceptions in OMA mode.)
Note: The R68561 interface is described for word mode opera·
tion only and the R68560 interface is described for byte
mode operation only.
6-249
•
Multi-Protocol Communications Controller (MPCC)
R68560, R68561
CS-Chip Select. CS low selects the MPCC for programmed
transfers with the host. The MPCC is deselected when the CS
input is inactive in non-DMA mode. CS must be decoded from
the address bus and gated with address strobe (AS).
UDS-Upper Data Strobe (R6856l). When interfacing to a
16-bit data bus system such as the 68000, a low on control bus
signal UOS enables access to the upper data byte on 08-D15.
A high on UOS disables access to D8-D15. Oata is latched and
enabled in conjunction with LDS.
R/VV-ReadlWrite. RiW controls the direction of data flow
through the bidirectional data bus by indicating that the current
bus cycle is a read (high) or write (low) cycle.
IRQ-Interrupt Request. The active low IRQ output requests
interrupt service by the MPU. IRQ is driven high after assertion
prior to being tri-stated.
DTACK-Data Transfer Acknowledge. DTACK is an active
low output that signals the completion of the bus cycle. During
read or interrupt acknowledge cycles, DTACK is asserted by
the MPCC after data has been provided on the data bus; during
write cycles it is asserted after data has been accepted at the
data bus. OTACK is driven high after assertion prior to being
tri-stated. A holding resistor is required to maintain DTACK high
between bus cycles.
lACK-Interrupt Acknowledge. The active low lACK input
indicates that the current bus cycle is an interrupt acknowledge
cycle. When lACK is asserted the MPCC places an interrupt
vector on the lower byte (DO-D7) of the data bus.
TDSR-Transmitter Data Service Request. When Transmitter OMA mode is active, the low TDSR output requests DMA
service.
OS-Data Strobe (R68560). During a write (R/W low), the
DS positive transition latches data on data bus lines 00-D7
into the MPCC. During a read (RiW high), OS low enables data
from the MPCC to data bus lines DO-07.
RDSR-Receiver Data Service Request. When receiver DMA
mode is active, the low RDSR output requests DMA service.
DACK-DMA Acknowledge. The DACK low input indicates
that the data bus has been acquired by the DMAC and that the
requested bus cycle is beginning.
LOS-Lower Data Strobe (R6856l). During a write (RiW low),
the positive transition latches data on the data bus lines 00-D7
(and on D8-D15 if UDS is low) into the MPCC. During a read
(RiW high), LDS low enables data from the MPCC to DO-D7
(and to 08-D15 if UDS is low).
DTC-Data Transfer Complete. On a 68000 bus, the DTC low
input indicates that a DMA data transfer was completed with no
bus conflicts. OTC in response to a RDSR indicates that the data
has been successfully stored in memory. DTC in response to
a TDSR indicates that the data is present on the data bus for
strobing into the MPCC. If not used, this input should be connected to ground.
AO-Address Line AD (R68560). When interfacing to an 8-bit
data bus system such as the 68008, address line AO is used
to access an internal register. AO = 0 defines an even register
and AO = 1 defines an odd register. See Table lb.
DATA
BUS
ADDRESS
BUS
<
A1-A4
UDS/AO
LOS/OS
ASYNCHRONOUS
BUS
CONTROL
CS
RIW
DMA
CONTROL
OIl
INTERRUPT
CONTROL
00-015
{
DTACK
RESET
TDSR
RDSR
DACK
DONE
DTC
IRQ
lACK
Figure 2.
R68S60/
R68S6l
MPCC
..
RTS
CTS
DTR
DSR
DCD
}
TxD
TxC
} TRANSMITTER
INTERFACE
MODEM
INTERFACE
RxD
RxC
RECEIVER
} INTERFACE
CLOCK
} INTERFACE
EXTAL
XTAL
BCLK
..
Vee
GND
..
MPCC Input and Output Signals
6-250
R68560, R68561
Multi-Protocol Communications Controller (MPCC)
DONE-Done. DONE is a bidirectional active low signal. The
DONE signal is asserted by the DMAC when the DMA transfer
count is exhausted and there IS no more data to be transferred.
or asserted by the MPCC when the status byte following the last
character of a frame (block) is being transferred in response to
a RDSA. The DONE signal asserted by the DMAC in response
to a TDSR will be stored to track with the data byte (lower
byte for word transfer) through the TxFIFO.
DCD-Data Carrier Detect. The DCD active low input positive
transition and level are reported in the DCDT and DCDLVL bits
in the the SISR, respectively.
TxD-Transmitted Data. The MPCC transmits serial data on the
TxD output. The TxD output changes on the negative going edge
of TxC.
RxD-Received Data. The MPCC receives serial data on the RxD
input. The RxD input is shifted into the receiver with the nega·
tive going edge of RxC.
RESET-Reset. RESET is an active low, high impedance
input that initializes all MPCC functions. RESET must be
asserted for at least 500 ns to initialize the MPCC.
TxC-Transmitter Clock. TxC can be programmed to be an input
or an output. When TxC is selected to be an input, the transmitter
clock must be provided externally. When TxC is programmed to
be an output, a clock is generated by the MPCC's internal baud
rate generator.
DTR-Data Terminal Ready. The DTR active low output is
general purpose in nature, and IS controlled by the DTRLVL bit
in the Serial Interface Control Register (SICR).
RxC-Receiver Clock. RxC provides the MPCC receiver with
received data timing Information.
EXTAL-CrystallExternal Clock Input.
XTAL Crystal Return. EXTAL and XTAL connect a 20 kHz to
8.064 MHz parallel resonant external crystal to the MPCC inter·
nal oscillator (see CLOCK OSCILLATOR). The pin EXTAL may
also be used as a TIL level Input to supply DC to 8 MHz ref·
erence timing from an external clock source. XTAL must be tied
to ground when applying an external clock to the EXTAL input.
RTS-Request to Send. The RTS active low output is general
purpose in nature, and is controlled by the RTSLVL bit in the
SICR.
CTS-Clear to Send. The CTS active low input positive transi·
tion and level are reported in the eTST and CTSLVL bits in the
Serial Interface Status Register (SISR), respectively.
BCLK-Buffered Clock. BCLK is the internal oscillator buffered
output available to other MPCC devices eliminating the need for
additional crystals.
DSR-Data Set Ready. The DSR active low input negative
transition and level are reported in the DSRT and DSRLVL bits
in the SISR, respectively. DSR is also an output for RSYN.
UOS
OTACK
RxO
010
OTR
OSR
OCO
011
ROSR
Al
GNO
A4
A2
A3
RxC
012
TxC
BCLK
EXTAL
XTAL
013
RIW
IRQ
RTS
2
3
4
5
6
7
8
9
10
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Vee-Power.5V ±5%.
GND-Ground. Ground (Vss).
lACK
LOS
OTC
09
CS
OACK
GNO
00
08
01
02
03
04
05
06
015
07
RESET
CTS
AD
OTACK
RxO
OTR
OSR
OCO
ROSR
Al
GNO
A4
A2
A3
RXC
TxC
BCLK
EXTAL
XTAL
Vee
014
OONE
TxO
TOSR
RIW
IRQ
RTS
R6856l
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
R68560
Pin Configuration
6·251
lACK
OS
OTC
CS
OACK
GNO
00
01
02
03
04
05
D6
07
RESET
CTS
Vee
DONE
TxO
TDSR
•
R68560, R68561
Multi-Protocol Communications Controller (MPCC)
MPCC REGISTERS
Twenty-two registers control and monitor the MPCC operation.
The registers and their addresses are identified in Table 1a
(R68561 operation in word mode) and in Table 1b (R68560 operation in byte mode). When the R68S61 is operated in the word
mode, two registers are read or written at a time starting at an
even boundary. When the R68560 is operated in the byte mode,
each register is explicitly addressed based on AO.
Table la.
Table 2 summarizes the MPCC register bit assignments and their
access. A read from an unassigned location results in a read
from a "null register." A null register returns all ones for data
and results in a normal bus cycle. Unused bits of a defined
register are read as zeros unless otherwise noted.
R68561 Accessible Registers (Word Mode)
Reglsler(s)
15
(Odd Registers)
Receiver Control Register (RCR)
8
7
RIW
Addr
Address Lines
(Hex.)
A4 A3 A2 Al
0
(Even Registers)
Receiver Status Register (RSR)
Receiver Data Register (RDR)-16 bits1
RIW
00
0
0
0
R
02
0
0
0
0
1
04
0
0
1
0
0
Receiver Interrupt Enable Register (RIER)
Receiver Interrupt Vector Number Register (RIVNR)
RIW
Transmitter Control Register (TCR)
Transmitter Status Register (TSR)
RIW
06
0
1
0
W
OA
0
1
0
1
Transmitter Data Register (TDR)-16 bits2
Transmitter Interrupt Enable Register (TIER)
Transmitter Interrupt Vector Number Register (TIVNR)
RIW
OC
0
1
1
0
Serial Interface Control Register (SICR)
Serial Interface Status Register (SISR)
RIW
10
1
0
0
0
RIW
12
1
0
0
1
Serial Interrupt Vector Number Register (SIVNR)
RIW
14
1
0
1
0
0
Reserved3
Serial Interrupt Enable Register (SIER)
Reserved3
Protocol Select Register 2 (PSR2)
Protocol Select Register (PSR1)
RIW
18
1
1
0
Address Register 2 (AR2)
Address Register 1 (AR 1)
1A
1
1
0
1
Baud Rate Divider Register 2 (BRDR2)
Baud Rate Divider Register 1 (BRDR1)
RIW
RIW
1C
1
1
1
0
Error Control Register (ECR)
Clock Control Register (CCR)
RIW
1E
1
1
1
1
Notes:
1. Accessible register of the four word RxFIFO. The data is not initialized, however, RES resets the RxFIFO pointer to the start of the first word.
2. Accessible register of the four word TxFIFO. The data is not initialized, however, RES resets the TxFIFO pOinter to the start of the first word.
3. Reserved registers may contain random bit values.
CLOCK OSCILLATOR
C1 = 2CL - 12 pF
An on-chip oscillator is designed for a parallel resonant crystal
connected between XTLI and XTLO pins. The equivalent oscillator circuit is shown in the figure below.
C2 =2CL - 33 pF
2x lOS
R. / R. max = - (FCd2
where: F is in MHz; C and CL are in pF; R is in ohms.
To select a parallel resonant crystal for the oscillator, first select
the load capacitance from a crystal manufacturer's catalog. Next,
calculate R.max based on F and CL. The selected crystal must
have a R. less than the Asmax.
For example, if CL .. 20 pF for an 8.064 MHz parallel resonant
crystal, then
C1 = 40 - 12
C2 =
= 28 pF (Use standard value of 27 pF.)
40 - 33 = 7 pF (Use standard value of 6.8 pF.)
Note: Cx = Total Shunt CapaCitance including that due to
board layout.
A parallel resonant crystal is specified by its load capacitance
and series resonant resistance. For proper oscillator operation,
the load capacitance (CJ, series resistance (Rs) and the crystal resonant frequency (F) must meet the following two relations:
The series resistance of the crystal must be less than
D
nomax
6-252
=
2xlOS
= 77 ohms
(8.064 X 20)2
R68560, R68561
Multi-Protocol Communications Controller (MPCC)
Table 1b.
R68560 Accessible Registers (Byte Mode)
Reglster(s)
A4
Address Lines
A3
A2
A1
o
7
Receiver Status Register (RSR)
RIW
00
0
0
0
0
Receiver Control Register (RCR)
RIW
01
0
0
0
0
1
R
02
0
0
0
1
0
Receiver Data Register (RDR)-8 bits'
Reserved3
0
03
0
0
0
1
1
Receiver Interrupt Vector Number Register (RIVNR)
RIW
04
0
0
1
0
0
Receiver Interrupt Enable Register (RIER)
RIW
05
0
0
1
0
1
Transmitter Status Register (TSR)
RIW
08
0
1
0
0
0
Transmitter Control Register (TeR)
RIW
09
0
1
0
0
1
W
OA
0
1
0
1
0
Transmitter Data Register (TDR)2-8 bits
Reserved3
OB
0
1
0
1
1
Transmitter Interrupt Vector Number Register (TIVNR)
RIW
OC
0
1
1
0
0
Transmitter Interrupt Enable Register (TIER)
RIW
00
0
1
1
0
1
Serial Interface Status Register (SISR)
RIW
10
1
0
0
0
0
Serial Interface Control Register (SICR)
RIW
11
1
0
0
0
1
12
1
0
0
1
0
Reserved3
13
1
0
0
1
1
Serial Interrupt Vector Number Register (SIVNR)
Reserved 3
RIW
14
1
0
1
0
0
Serial Interrupt Enable Register (SIER)
RIW
15
1
0
1
0
1
0
Protocol Select Register 1 (PSR1)
RIW
18
1
1
0
0
Protocol Select Register 2 (PSR2)
RIW
19
1
1
0
0
1
Address Register 1 (AR1)
RIW
lA
1
1
0
1
0
Address Register 2 (AR2)
RIW
lB
1
1
0
1
1
Baud Rate Divider Register 1 (BRDR1)
RIW
Ie
1
1
1
0
0
Baud Rate Divider Register 2 (BRDR2)
RIW
10
1
1
1
0
1
Clock Control Register (CCR)
RIW
IE
1
1
1
1
0
Error Control Register (ECR)
RNi
IF
1
1
1
1
1
Noles:
1. Accessible register of the eight byte RxFIFO. The data is not initialized, however, RES resets the RxFIFO pointer to the start of the first byte.
2. Accessible register of the eight byte TxFIFO. The data is not initialized, however, RES resets the TxFIFO pointer to the start of the first byte.
3. Reserved registers may contain random bit values.
6-253
•
Multi-Protocol Communications Controller (MPCC)
R68560, R68561
Table 2.
MPCC Register Bit Assignments
Bit Number
Accese
7
6
5
4
3
2
1
0
Reset(1)
Value
RIW
RDA
EOF
0
C/PERR
FRERR
ROVRN
RAtB
RIDLE
00
Receiver Status
RegiSier (RSR)
RIW
0
RDSREN
DONEEN
RSYNEN
STRSYN
0
RABTEN
RRES
01
Receiver Control
RegiSier (RCR)
RIW
R
RECEIVER DATA (RxFIFO)2
--
RIW
RECEIVER INTERRUPT VECTOR NUMRER (RIVN)
OF
Receiver Interrupt Vector
Number RegiSier (RIVNR)
Receiver Data
Register (RDR)
RIW
RDA
IE
EOF
IE
0
C/PERR
IE
FRERR
IE
ROVRN
IE
RAtB
IE
0
00
Receiver Interrupt Enable
Register (RIER)
RIW
TDRA
TFC
0
0
0
TUNRN
TFERR
0
80
Transmitter Status
RegiSier (TSR)
RIW
TEN
TDSREN
TICS
THW
TLAST
TSYN
TABT
TRES
01
Transmitter Control
RegiSier (TCR)
Transmitter Data
RegiSier (TOR)
W
TRANSMITTER DATA (TxFIFO)2
--
RIW
TRANSMITTER INTERRUPT VECTOR NUMBER (lIVN)
OF
Transmitter Interrupt Vector
Number RegiSier (lIVNR)
RIW
TDRA
IE
TFC
IE
0
0
0
TUNRN
IE
TFERR
IE
0
00
Transmitter Interrupt Enable
Register (TIER)
RIW
CTST
DSRT
DCDT
CTSLVL
DSRLVL
DCDLVL
0
0
00
Serial Interface Status
Register (SISR)
RIW
RTSLVL
DTRLVL
0
0
0
ECHO
TEST
0
00
Serial Interface Control
RegiSier (SICR)
RIW
RANDOM BIT VALUES
(reserved)
RANDOM BIT VALUES
(reserved)
SERIAL INTERRUPT VECTOR NUMBER (SIVN)
RIW
CTS
IE
DSR
IE
DCD
IE
0
0
0
0
RIW
0
0
0
0
0
0
CTLEX
RIW
WD/BYT
STOP BIT SEL
SB2
I
SBl
CHAR LEN SEL
Cl2
0
I ADDEX
PROTOCOL SEL
CLl
PS3
PS2
I
PSl
OF
Serial Interrupt Vector
Number RegiSier (SIVNR)
00
Serial Interrupt Enable
Register (SIER)
00
Protocol Select
RegiSier 1 (PSR1)
00
Protocol Select
Register 2 (PSR2)
RIW
BOP ADDRESs/BSC & COP PAD
00
Address Register 1 (AR1)
RIW
BOP ADDRESs/BSC & COP SYN
00
Address Register 2 (AR2)
RIW
BAUD RATE DIVIDER (LSH)
01
Baud Rate Divider
RegiSier 1 (BRDR1)
RIW
BAUD RATE DIVIDER (MSH)
00
Baud Rate Divider
Register 2 (BRDR2)
00
Clock Control
RegiSier (CCR)
04
Error Control
RegiSier (ECR)
RIW
0
0
0
PSCDIV
TCLKO
RCLKIN
RIW
PAREN
ODDPAR
0
0
CFCRC
CRCPRE
Notes:
1. RESET = RegiSier contents upon power up or RESET.
2. 16·blts for R68561 (word mode); 8-bits for R68560 (byte mode).
6·254
CLK DIV
CK2
I
CKl
CRC SEL
CR2
I
CRl
R68560, R68561
Multi-Protocol Communications Controller (MPCC)
REGISTER DEFINITIONS
RSR
4 C/PERR -CRC/Parlty Error.
-0No CRC or parity error detected.
1
CRC error detected (BOP, BSC) or parity error
detected (ASYNC, ISOC and COP). The C/PERR bit
is loaded into the RxFIFO with the negative-going RxC
edge, along with the byte or word with which it is
associated. For ASYNC, ISOCH or COP protocols, this
is with the byte/word containing a parity error. For BOP
or BSC, it is loaded to RxFIFO (after the CRC check)
with the FSB. C/PERR is loaded into the RSR and the
interrupt issued (when the read pOinter is positioned
at the FSB) with the trailing edge of LOS.
RECEIVER REGISTERS
Receiver Status Register (RSR)
Address = 00
Reset Value = $00
The Receiver Status Register (RSR) contains the status of the
receiver including error conditions. Status bits are cleared by
writing a 1 into respective positions, by writing a 1 into the RCR
RRES bit or by RESET. If an EOF, C/PERR, or FRERR is set
in the RSR, the data reflecting the error (the next byte or word
in the RxFIFO) must be read prior to resetting the corresponding status bit in the RSR. The IRQ output is asserted if any
of the conditions reported by the status bits occur and the corresponding interrupt enable bit in the RIER is set.
C/PERR Reset - The byte/word containing the FSB must be
read from the RxFIFO before resetting the C/PERR bit. Then
it may be reset by writing a 1 to RSR4.
RSR
_3_ FRERR
o
1
The RSR format is the same as the frame status format (see
below) except as noted.
-Frame Error.
No frame error detected.
FRERR is set for receiver overrun, flag detected off
boundary (BOP), or frame error (ASYNC, ISOCH). For
receiver overrun, the FRERR bit is set in the RxFIFO
with the last byte when the overrun is detected.
RSR
~
o
For BOP, a minimum message size is an opening flag,
one address byte and one control byte. If the closing
flag is detected before the control byte is sent, a short
frame is indicated and a frame error results. For
address extension, multi-address bytes may be
received before the control byte is expected. The
FRERR bit is latched in RxFIFO with the negative-going
edge of RxC with the last address byte received upon
detection of the flag off boundary. FRERR is loaded
into the RSR and the interrupt issued when the read
pointer is positioned at the FSB with the trailing edge
of LOS.
RDA
-Receiver Data Available. (RSR only).
The FxFIFO is empty (Le., no received data is
available).
ROA is set and an interrupt issued (if enabled) when
the RxFIFO has 1 to 8 bytes, or 1 to 4 words, of data
in it.
ROA Reset - ROA cannot be cleared or reset in software. It
is initialized to 0 upon hardware reset and remains 0 if no data
has been received. It is set to a 1 and an interrupt issued when
a data byte/word is loaded to the RxFIFO with the negative edge
of RxC coincident with the first bit of the next byte transmitted. It is automatically reset to 0 when the last byte/word is
read from the RxFIFO by the host through ROR.
In ASYNC or ISOCH, a FRERR bit set indicates that
the stop bit was detected off boundary (too early or too
late for the number of bits expected by the setting of
PSR2-3 and PSR2-4) or it was not the correct width
(as expected by the setting of PSR2-6 and PSR2-5).
RSR
_6_ EOF
o
1
-End of Frame. (BOP and BSC)
No end of frame has been detected.
The closing flag (BOP) or pad (BSC) has been
detected. EOF is loaded in the RxFIFO along with the
FSB with which it is associated. The EOF is loaded into
the RSR and the interrupt issued, if enabled, (when
the RxFIFO read pointer is positioned at the FSB) with
the trailing edge of LOS.
FRERR Reset - The byte/word containing the FSB must be
read from the RxFIFO before resetting the C/PERR bit. The
C/PERR bit may then be reset by writing a 1 to RSR3.
RSR
_2_ ROVRN
o
EOF Reset - The byte/word containing the FSB must be read
from the RxFIFO before resetting the EOF bit. Then EOF may
be reset by writing a 1 to RSR6.
1
RSR
_5_ RHW
-Receive Half Word. (Frame Status only)*
o
The last word of the frame contains data on the upper
half (08-015) and frame status on the lower half
(00-07) of the data bus.
The lower half of the data bus (00-07) contains the
frame status but the upper half (08-015) is blank or
invalid.
-Receiver Overrun.
No receiver overrun detected.
Receiver overrun detected. Oata is loaded into the
RxFIFO on byte boundaries with the negative-going
edge of RxC coincident with the first bit of the subsequent data being received. When the eighth byte, or
fourth word, of data has been written into RxFIFO
without any data being read out, the RxFIFO is full and
the incremented write pointer "catches up" with the
read pointer. The next attempt to write data to RxFIFO
causes ROVRN bit to be loaded to the RSR and the
interrupt issued (if enabled). The data in the RxFIFO
is not affected, but new received data is lost.
ROVRN Reset - The ROVRN bit is not self-clearing when data
is read from the RxFIFO, but may be reset by writing a 1 to RSR2 .
• See Frame Status (RSR) on next page.
6-255
•
Multi-Protocol Communications Controller (MPCC)
R68560, R68561
RlR
1
""""0"
1
tents, the frame status byte has a RHW status In bit 5 which
indicates either an even or odd boundary (applicable to word
mode only).
RAIB
-Receiver Abort/Break.
Normal Operation.
(BOP) When an ABORT (seven 1s) is detected after
the opening flag, the RAlB bit is set in the RSR and
an Interrupt Issued (if enabled). This bit is latched with
the negative edge of RxC after the seventh 1 bit is
detected. (NOTE: Because the previous byte can end
in zero to five 1 bits, the abort could be recognized in
the next byte as early as two to seven 1 bits.)
If the MPCC is in word mode and the last data byte was on an
even byte boundary (i.e., there was an even number of bytes
in the message), a blank byte will be loaded Into the RxFIFO
prior to loading the frame status byte in order to force the "frame
status" byte and the next frame to be on an even boundary.
When RHW = 0, the last word of the frame contains data on
the upper half and status on the lower half of the data bus. If
RHW
1, the lower half of the bus contains stetus but the upper
half is a blank or invalid byte.
=
(BSC) When ENQ is detected in a block of text data,
the RAlB bit is set in the RSR and the interrupt issued
(if enabled) with the next negative edge of the RxC
clock.
RAlB Reset -
In the byte mode, the status byte will always immediately follow
the last data byte of the blocklframe (see Figure 3). The EOF
status in the RSR is then set when the byteJword containing the
frame status is the next bytelword to be read from the RxFIFO.
The RAiB bit is reset by writing a 1 to RSR1.
In the receiver DMA mode, when the EOF status in the RSR
is set, DONE is asserted to the DMAC. Thus the last byte
accessed by the DMAC Is always a status byte, which the
processor may read to check the validity of entire frame.
RSR
.JL
o
1
RIDLE
-Receiver Idle. (BOP only).
Receiver is not idle.
15 or more 1s have been detected. The RIDLE bit is
set in RSR with the negative edge of the next RxC after
15 consecutive 1s have been detected.
Receiver Control Register (RCR)
RIDLE Reset - The RIDLE is reset by writing a 1 to RSRO.
(NOTE: The RIDLE bit will set again in 15 clock cycles If RxD
is still in the idle condition.)
Address - 01
* Frame Status (RSR)
The Receiver Control Register (RCR) selects receiver control
options.
I~ IE~F I I
R:W
CIP:RR
I
IRO~RN I ~B I: I
FR:RR
Reset value - $01
RCR
....L
For the BSC and BOP protocols which have defined message
blocks or frames, a "frame status" byte will be loaded into the
RxFIFO following the last data byte of each block. The frame
stetus contains all the status contained within the RSR with the
exception of RDA and RIDLE. But, in addition to the RSR con·
-Not used •
RCR
~ RDSREN
o
1
-Receiver Data Service Request Enable.
Disable receiver DMA mode.
Enable receiver DMA mode.
ODD NUMBER OF BYTES
WORD
WORD
MODE
D15
N
N + 1
D8 D7
EVEN NUMBER OF BYTES
DO
WORD
DATA
STATUS
N
NEXT
FRAME
(RHW - 0)
D15
D8 D7
DATA
N + 1
BLANK
STATUS
N + 2
NEXT
FRAME
(RHW = 1)
BYTE
D7
M
BYTE
MODE
DO
BYTE
DATA
D7
M
DO
DATA
M + 1
STATUS
M + 1
STATUS
11+2
NEXT FRAME
M+2
NEXT FRAME
Figure 3. BSCIBOP Block/Freme Status location
6·256
DO
DATA
R68560, R68561
Multi-Protocol Communications Controller (MPCC)
RCR
_5_ DONE EN -DONE Output Enable.
o
Disable DONE output.
Enable DONE output. (When the receiver is in the DMA
mode, i.e., RDSREN = 1).
Receiver Interrupt Vector Number Register (RIVNR)
Address = 04
If a receiver Interrupt condition occurs (as reported by status
bits in the RSR that correspond to interrupt enable bits in the
RIER) and the corresponding bit is set in the RIER, IRQ output
is asserted to request MPU receiver interrupt service. When the
lACK input is asserted from the bus, the Receiver Interrupt Vector Number (RIVN) from the Receiver Interrupt Vector Number
Register (RIVNR) is placed on the data bus.
RCR
_4_ RSYNEN
o
1
-RSYNEN Output Enable. Selects the
DSR signal input or the RSYN SYNC
signal output on the DSR pin.
Input DSR on DSR.
Output RSYN on DSR.
RCR
_3_ STRSYN -Strip SYN Character (COP only).
o
Do not strip SYN character.
Strip SYN character.
Receiver Interrupt Enable Register (RIER)
RCR
_2_ MUST BE ZERO
Address
o
=
Reset value = $00
05
The Receiver Interrupt Enable Register (RIER) contains Interrupt enable bits for the Receiver Status Register (RSR). When
enabled, the IRQ output is asserted when the corresponding
condition is detected and reported in the RSR.
RCR
_1_ RABTEN -Receiver Abort Enable (BOP only).
o
Do not abort frame upon error detection.
1
Abort frame upon RxFIFO overrun (ROVRN bit = 1 in
the RSR) or CFCRC error detection (C/PERR bit = 1
in the RSR). If either error occurs, the MPCC ignores
the remainder of the current frame and searches for
the beginning of the next frame. (EOF is set upon
abort).
RIER
_7_ RDA IE
o
-Receiver Data Available Interrupt
Enable.
Disable RDA Interrupt.
Enable RDA Interrupt.
RIER
_6_ EOF IE
-End of Frame Interrupt Enable.
o
Disable EOF Interrupt.
Enable EOF Interrupt.
RCR
_0_ RRES
o
Reset value = $OF
-Receiver Reset Command.
Enable normal receiver operation.
Reset receiver. Resets the receiver section including
the RxFIFO and the RSR (but not the RCR). RRES is
set by RESET or by writing a 1 into this bit and must
be cleared by writing a 0 into this bit. RRES requires
clearing after RESET.
RIER
_5_
-Not used.
RIER
_4_ C/PERR IE -CRC/Parity E:rror Interrupt Enable.
o
Disable C/PERR Interrupt.
Enable C/PERR Interrupt.
Receiver Data Register (RDR)
RIER
_3_ FRERR IE -Frame Error Interrupt Enable.
o
Disable FRERR Interrupt.
Enable FRERR Interrupt.
R68560 (Byte Mode)
RIER
_2_ ROVRN IE -Receiver Overrun Interrupt Enable.
o
Disable ROVRN Interrupt.
Enable ROVRN Interrupt.
o
Byte 0
Address
LSB
= 02
RIER
_1_ RA/B IE
-Receiver Abort/Break Interrupt Enable.
o
Disable RNB Interrupt.
Enable RNB Interrupt.
The receiver has an 8·byte (or 4·word) First In First Out (FIFO)
register file (RxFIFO) where received data are stored before
being transferred to the bus. The received data IS transferred
out of the RxFIFO via the RDR in 8-bit bytes or 16-bit words depending on the WD/BYT bit setting in PSR2. When the RxFIFO
has a data byte/word ready to be transferred, the RDA status
bit in the RSR IS set to 1.
RIER
_0_
6-257
-Not used.
•
R68560, R68561
Multi-Protocol Communications Controller (MPCC)
TRANSMITTER REGISTERS
The TUNRN bit is set in TSR2 and the interrupt issued
with the positive edge of the TxC coincident with the
eighth bit of data prior to the ABORT in BOP or to SYN
in BSC or COP.
Transmitter Status Register (TSR)
2
TUNRN
Address = 08
TUNRN Reset - One full cycle of the serial clock (TxC) must
elapse before the TUNRN bit can be reset by writing a 1 to TSR2.
TFERR
Reset value = $80
The Transmitter Status Register (TSR) contains the transmitter
status including error condition!>. The transmitter status bits are
cleared by writing a 1 into their respective positions, by writing
a 1 into the TCR TRES bit, or by RESET. The IRQ output is
asserted if any of the conditions reported by the status bits occur
and the corresponding interrupt enable bit in the TIER is set.
TSR
_1_ TFERR
-Transmit Frame Error (BOP only).
o
No frame error has occurred.
A short frame condition exists in that no control field
is transmitted. (TLAST was issued early with an
address byte.) TFERR bit is set and the interrupt issued
with the positive edge of TxC coincident with the end
of the last bit of the byte causing the error.
TSR
~
o
1
TDRA
-Transmitter Data Register Available.
The TxFIFO is full.
The TxFIFO is available to be loaded via the TDR
(1 to 8 bytes, or 1 to 4 words).
TFERR Reset - One full cycle of the serial clock (TxC)
must elapse before TFERR bit can be reset by writing
a 1 to TSR1.
TDRA Reset - TDRA cannot be reset by the host in normal
operation. It initializes to a 1 upon hardware or software reset
of the MPCC. TDRA is not dependent on the serial clock.
Transmitter Control Register (TCR)
TSR
_6_ TFC
Address = 09
o
1
-Transmitted Frame Complete. (BOP, BSC
and COP only).
(All) Frame not complete.
(BOP) Closing flag or ABORT has been transmitted.
The TFC bit is set and the interrupt issued (if enabled)
with the negative edge of TxC coincident with the end
of the last bit of the flag. When TABT is set in TCR1,
an ABORT is transmitted immediately but TFC is not
issued until after the closing flag or 8 bits of the MARK
idle condition after the TxFIFO is flushed of all current
data bytes.
The Transmitter Control Register (TCR) selects transmitter control function.
TCR
~
o
--L
(COP) Last byte has been transmitted (TLAST set in
TCR3). TFC bit set and/or interrupt issued with negative edge of the TxC coincident with the end of the last
bit of the last byte.
1
o
-Transmitter Data Service Request
Enable.
Disable transmitter DMA mode.
Enable transmitter DMA mode.
TCR
o
TSR
-Not used .
TSR
_2_ TUNRN
1
TDSREN
_5_ TICS
TFC Reset - One full cycle of the serial clock (TxC) must elapse
before the TFC bit can be reset by writing a 1 to TSR6.
o
TEN
-Transmitter Enable.
Disable transmitter. TxD output is idled. The TxFIFO
may be loaded while the transmitter is disabled.
Enable transmitter.
TCR
(BSC) Trailing pad has been transmitted. TFC bit set
and/or interrupt issued with negative edge of TxC coincident with the end of the last bit of the trailing pad.
.H..
Reset value = $01
-Transmitter Idle Character Select. Selects
the idle character to be transmitted when
the transmitter is in an active idle mode
(transmitter enabled or disabled).
Mark Idle (TxD output is held high).
Content of AR2 (BSC and COP), BREAK condition
(ASYNC and ISOC), or FLAG character (BOP).
TCR
-Transmitter Underrun (BOP, BSC and
COP only).
No TxFIFO underrun has occurred.
An empty TxFIFO was accessed for data.
(BOP) Underrun is treated as an ABORT in that eight
consecutive 1s are transmitted followed by the idle
condition of MARK or FLAG.
.....L
(BSC, COP) Underrun causes SYN characters to be
transmitted until new data is available in the TxFIFO.
o
1
6-258
-Transmit Half Word. (R68561, word mode
only). This bit is used when the frame or
block ends on an odd boundary in conjunction with the TLAST bit and indicates that
the last word in the TxFIFO contains valid
data in the upper byte only. This bit must
always be 0 in byte mode (R68560).
Transmit full word (16 bits) from the TxFIFO.
Transmit upper byte (8 bits) from the TxFIFO.
THW
Multi-Protocol Communications Controller (MPCC)
R68560, R68561
TCR
_3_ TLAST
Transmitter Interrupt Vector Number Register (TIVNR)
-Transmit Last Character (BOP, BSC and
COP only).
The next character is not the last character In a frame
or block.
The next character to be written Into the TDR is the
last character of the message. The TLAST bit automatically returns to a 0 when the associated word/byte
is written to the TxFIFO. If the transmitter DMA mode
is enabled, TLAST is set to a 1 by DON E from the
DMAC. In this case the character written into the TDR
in the current cycle IS the last character.
o
Address
7
6
5
4
3
2
1
0
TFC
IE
0
0
0
TUNRN
IE
TFERR
IE
-
o
1
Reset value
=
$00
-Transmitter Data Register (TOR) Available Interrupt Enable.
Disable TDRA Interrupt.
Enable TDRA Interrupt.
TIER
_6_ TFC IE
o
-Transmit Frame Complete (TFC) Interrupt
Enable.
Disable TFC Interrupt.
Enable TFC Interrupt.
TIER
5-3
-Not used.
TIER
_2_ TUNRN IE -Transmitter Underrun (TUNRN) Interrupt
o
1
Enable.
Disable TUNRN Interrupt.
Enable TUNRN Interrupt.
•
I
TIER
_1_ TFERR IE -Transmit Frame Error (TFERR) Interrupt
Enable.
Disable TFERR Interrupt.
o
Enable TFERR Interrupt.
OA
R68560 (Byte Mode)
4
Address
00
TIER
_7_ TORA IE
Transmit Data Register (TOR)
LMSB
=
The Transmitter Interrupt Enable Register (TIER) contains
interrupt enable bits for the Transmitter Status Register. When
enabled, the IRQ output is asserted when the corresponding
condition IS detected and reported in the TSR.
TCR
_1I_ TRES
-Transmitter Reset Command.
o
Enable normal transmitter operation.
Reset transmitter. Clears the transmitter section
Including the TxFIFO and the TSR (but not the TCR).
The TxD output IS held in "Mark" condition. TRES IS
set by RESET or by writing a 1 Into this bit and IS
cleared by writing a 0 Into this bit. TRES reqUires clearIng after RESET.
=
$OF
TDRA
IE
Address
TABT
-Transmit ABORT (BOP only).
Enable normal transmitter operation.
Causes an abort by sending eight consecutive 1'so A
data word/byte must be loaded into the TxFIFO after
setting this bit in order to complete the command. The
TABT bit clears automatically when the subsequent
data word/byte IS loaded Into the TxFIFO.
Address
=
Transmitter Interrupt Enable Register (TIER)
TCR
o
Reset value
OC
If a transmitter interrupt condition occurs (as reported by status
bits in the TSR that correspond to interrupt enable bits in the
TIER) and the corresponding bit in the TIER is set, the IRQ
output is asserted to request MPU transmitter interrupt service.
When the lACK input IS asserted from the bus, the Transmitter
Interrupt Vector Number (TIVN) from the Transmitter Interrupt
Vector Number Register (TIVNR) is placed on the data bus.
TCR
_2_ TSYN
- Transmit SYN (BSC and COP only)
o
Do not transmit SYN characters.
Transmit SYN characters. Causes a pair of SYN
characters to be transmitted Immediately following the
current character. If BSC transparent mode is active,
a DLE SYN sequence IS transmitted. The TSYN bit
automatically returns to a 0 when the SYN character
is loaded Into the Transmitter Shift Register.
_L
=
3
Byte 0
2
TIER
_0_
LSB
= OA
-Not used.
SERIAL INTERFACE REGISTERS
The transmitter has an 8-byte (or 4-word) FIFO register file
(TxFIFO). Data to be transmitted IS transferred from the bus into
the TxFIFO via the TDR in 8-bit bytes or l6-blt words depending on the WD/BYT bit setting in PSR2. The TDRA status bit
in the TSR'is set to 1 when the TxFIFO IS ready to accept another
data word/byte.
Serial Interface Status Register (SISR)
Address
6-259
= 10
Reset value
= $00
R68560, R68561
Multi-Protocol Communications Controller (MPCC)
The Serial Interface Status Register (SISR) contains the serial
interface status information. The transition status bits (CTST,
DSRT and DCDT) are cleared by writing a 1 into their respective positions, or by RESET. The level status bits (CTSLVL,
DSRLVL and DCDLVL) reflect the state of their respective inputs
and cannot be cleared internally. The IRQ output is asserted
if any of the conditions reported by the transition status bits occur
and the corresponding interrupt enable bit in the SIER is set.
SISR
_2_ DCDLVL -Data Carrier Detect Level.
o
The input on DCD is negated (high, inactive).
1
The input on DCD is asserted (low, active).
DCDLVL Reset - The DCDLVL bit in SISR2 follows the state
of the input to DCD and cannot be reset internally.
SISR
1-0
SISR
_7_ CTST
-Clear to Send Transition Status.
o
The input on CTS has not transitioned positive.
The input on CTS has transitioned positive from active
1
to inactive. To detect this transition, RTS must be
active (low) and the transmitter must be enabled
(TRES in TCRO = 0). The CTST bit is set in SISR7 and
an interrupt issued (if enabled) with the negative edge
of TxC.
-Not used.
Serial Interface Control Register (SICR)
TEST
Address = 11
Reset value = $00
The Serial Interface Control Register (SICR) controls various
serial interface signals and test functions.
SICR
_7_ RTSLVL -Request to Send Level.
o
Negate RTS output (high).
1
Assert RTS output (low).
CTST Reset - A negative transition of the serial clock (TxC)
must occur after the CTS input goes high before the CTST bit
can be reset by writing a 1 to SISR7.
SISR
_6_ DSRT
-Data Set Ready Transition Status.
o
The input on DSR has not transitioned negative.
1
The input on DSR has transitioned negative from
inactive to active. The DSRT bit is set in SISR7 and
an interrupt issued (if enabled) with the negative edge
of RxC. The receiver must be enabled (RRES in
RCRO=O).
NOTE
In BOP, BSC, or COP, when the RTSLVL bit is cleared
in the middle of data transmission, the RTS outputremains asserted until the end of the current frame
or block has been transmitted. In ASYNC or ISOC, the
RTS output is negated when the TxFIFO is empty. If
the transmitter is idling when the RTSLVL bit is reset,
the RTS output is negated within two bit times.
DSRT Reset - A negative transition of the serial clock (RxC)
must occur after the DSR input goes high before the DSRT
bit can be reset by writing a 1 to SISR6.
SICR
_6_ DTRLVL -Data Terminal Ready Level.
o
Negate DTR output (high).
1
Assert DTR output (low).
SISR
_5_ DCDT
-Data Carrier Detect Transition Status.
o
The input on DCD has not transitioned positive.
The input on DCD has transitioned positive from active
1
to inactive. The DCDT bit is set in SISR5 and an interrupt issued (if enabled) with the negative edge of RxC.
The receiver must be enabled (RRES in RCRO = 0).
SICR
5-3
-Not used. These bits are initialized to 0 by
RESET and must not be set to 1.
SICR
_2_ ECHO
-Echo Mode Enable.
o
Disable Echo mode (enable normal operation).
Enable Echo mode. Received data (RxD) is routed
back through the transmitter to TxD. The contents of
the TxFIFO is undisturbed. This mode may be used
for remote test purposes.
DCDT Reset - A ne~e transition of the serial clock (RxC)
must occur after the DCD input goes high before the DCDT bit
can be reset by writing a 1 to SISR5.
SISR
_4_ CTSLVL -Clear to Send Level.
o
The input on CTS is negated (high, inactive).
The input on CTS is asserted (low, active).
1
SICR
_1_ TEST
-Self-test Enable.
o
Disable self-test (enable normal operation).
1
Enable self-test. The transmitted data (TxD) and clock
(TxC) are routed back through to the receiver through
RxD and RxC, respectively (DCD and CTS are
ignored). This "Ioopback" self-test may be used for
all protocols. RxC is external and CCR bits 2 and 3
must be a 1.
CRSLVL Reset - The CTSLVL bit in SISR4 follows the state
of the input to CTS and cannot be reset internally.
SISR
_3_ DSRLVL -Data Set Ready Level.
o
The input on DSR is negated (high, inactive).
1
The input on DSR is asserted (low, active).
SICR
_0_ MUST BE ZERO
DSRLVL Reset - The DSRLVL bit in SISR3 follows the state
of the input to DSR and cannot be reset internally.
o
6-260
R68560, R68561
Multi-Protocol Communications Controller (MPCC)
Serial Interrupt Vector Number Register (SIVNR)
Protocol Select Register 1 (PSR1)
I
Address = 14
~ I~ I~ I~ I~ I~
Address
Reset value = $OF
=
o
ADDEX
CTLEX
18
Reset value = $00
Protocol Select Register 1 (PSR 1) selects BOP protocol related
options.
If a serial interface interrupt condition occurs (as reported by
status bits in the SISR that correspond to interrupt enable bits
in the SIER) and the corresponding bit in the SIER is set, the
IRQ output is asserted to request MPU serial interface interrupt
service. When the lACK input is asserted from the bus, the Serial
Interrupt Vector Number (SIVN) from the Serial Interrupt Vector
Number Register (SIVNR) is placed on the data bus.
PSR1
7-2
-Not used.
PSR1
_1_ CTLEX
-Control Field Extend (BOP only).
o
Select 8-bit control field.
1
Select 16-bit control field.
Serial Interrupt Enable Register (SIER)
7
6
5
4
3
2
1
0
CTS
IE
DSR
IE
DCD
IE
0
0
0
0
0
Address = 15
PSR1
_0_ ADDEX
-Address Extend (BOP only).
o
Disable address extension. All eight bits of the
address byte are utilized for addreSSing.
Enable address extension. When bit 0 in the address
byte is a 0 the address field is extended by one byte.
An exception to the address field extension occurs
when the first address byte is all O's (null address).
Reset value = $00
The Serial Interrupt Enable Register (SIER) contains interrupt
enable bits for the Serial Interface Status Register. When an
interrupt enable bit is set, the IRQ output is asserted when the
corresponding condition occurs as reported in the SISR.
Protocol Select Register 2 (PSR2)
7
6
WD/BYT
SB2
SIER
_7_ CTS IE
-Clear to Send (CTS) Interrupt Enable.
o
Disable CTS Interrupt.
1
Enable CTS Interrupt.
Address
SIER
4-0
I
3
I SB1
CL2
I
2
I Cl1
1
I
0
PROTOCOL SEL
PS3
I PS2 I PS1
Reset value = $00
19
PSR2
_7_ WD/BYT -Data Bus Word/Byte Mode.
o
Select byte mode. Selects the number of data bits to
be transferred from the RxFIFO and the registers to
the data bus and to be transferred from the data bus
to the TxFIFO and the registers. The MPCC is initialized by RESET to the byte mode.
Select word mode. For operation with the 16-bit bus,
select the word mode by sending $80 on 07-00 to
address $19 prior to transferring subsequent data
between the MPCC and the data bus.
SIER
_5_ DCD IE
1
4
5
Protocol Select Register 2 (PSR2) selects protocols, character
size, the number of stop bits, and word/byte mode.
SIER
_6_ DSR IE
-Data Set Ready (DSR) Interrupt Enable.
o
Disable DSR Interrupt.
Enable DSR Interrupt.
1
o
=
I
STOP BIT SEL CHAR LEN SEL
-Data Carrier Detect (DCD) Interrupt
Enable.
Disable DCD Interrupt.
Enable DCD Interrupt.
PSR2
6-5 STOP BIT SEL
-Not used.
-Number of Stop Bits Select.
Selects the number of stop bits
transmitted at the end of the data
bits in ASYNC and ISOC modes.
No. of Stop Bits
GLOBAL REGISTERS
6
SB2
The global registers contain command information applying to
different modes of operation and protocols. After changing global
register data, TRES in the TCR and RRES in the RCR should
be set then cleared prior to performing normal mode proceSSing.
0
0
1
6-261
5
SB1
0
1
0
ASYNC
1
1-112
2
ISOC
1
2
2
•
Multi-Protocol Communications Controller (MPCC)
R68560, R68561.
Baud Ride Divider Register 1 (BRDR1)
PSR2
4-3 CHAR lEN SEl -Character length Select. Selects
the character length except in BOP
and BSC where the character length
is always eight bits. Parity is not
included in the character length. '
4
3
CL2
0
0
1
Cll
Character leng!h
0
1
0
1
5 bits
1
1 7 1 8 1 5 1 4 1
1 7 1 8 1 5 1 4 1 3 1 2 1
1
o
PS2
PSI
Protocol
o
o
o
o
o
o
o
BOP (Primary)
BOP (Secondary)
Reserved
COP
BSC EBCDIC
BSCASCII
ASYNC
ISOC
1
o
o
o
1
o
1
1
1
Reset value
Address - 10
2
1
1
1
1
o
1
BAUD RATE DIVIDER (MSH)
PS3
1
Reset value - $01
Baud Rate Divider Register 2 (BRDR2)
PSR2
2-0 PROTOCOL SEl-Protocol Select. Selects protocol
and defines the protocol dependent
control bits.
o
o
1 2
Address - 1C
6 bits
7 bits
8 bits
1
1
3
BAUD RATE DIVIDER (lSH)
a
$00
The two B-bit Baud Rate Divider Registers (BRDRI and BRDR2)
hold the divisor of the Baud Rate Divider circuit. BRDRI contains the least significant half (LSH) and BRDR2 contains the
most significant half (MSH), With an 8.064 MHz EXTAL input,
standard bit rates can be selected using the combination of
Prescaler Divider (in the CCR) and Baud Rate Divider values
shown in Table 3. For isochronous or synchronous protocols,
the Baud Rate Divider value must be multiplied by two for the
same Prescaler Divider value.
The Baud Rate Divider (BRD) value can be computed for other
crystal frequency, prescaler divider and desired baud rate values
as follows:
BRD =
Crystal Frequency
(Presealer Divider) (Baud Rate) (I<)
Address Register 1 (AR1) Addrass
1 7 1 8 1 5 1 4 1
3
o
1 2
where:
K .. 1 for isochronous or synchronous
2 for asynchronous
BOP ADDRESs/BSC & COP PAD
Reset value = $00
Address = 1A
Clock Control Register (CCR)
Address Register 2 (AR2)
7
8
5
4
3
2
171815141312
0
0
0
PSCDIV
TClKO
RClKIN
10
Address = 1B
0
I CK1
Reset value = $00
Address - IE
Reset value .. $00
I
ClK DIV
CK2
BSC & COP SYN
.
1
The CCR selects various clock options.
The protocol selected in PSR2 (BOP. BSC and COP only) determines the function of the two 8-bit Address Registers (ARI and
AR2). As a secondary station in BOP. the contents of ARI is
used for address matching. In
and COP. ARI and AR2 contain programmable leading PAD and programmable SYN
characters. respectively.
CCR
.I:!.
esc
BOP
BOP
,BSC
BSC
COP
(Primary)
(Secondary)
EBCDIC
ASCII
ARI
X
Address
leading PAD
leading PAD
leading PAD
ueed.
CCR
..L
Address Register (AR) Contents
Protocol Selected
-Not
AR2
o
X
X
SYN
SYN
SYN
1
PSCDIV
-Prasealer Divider. The Prescaler Divider
network reduces the external/oscillator frequency to a value for use by the internal
Baud Rate Generator.
Divide by 2.
Divide by 3.
CCR
_3_ TCL.KO
-Transmitter Clock Output Select.
Select TxC to be an input.
Select TxC to be an output. (IX clock)
1
o
'X = Not used
6-262
R68560, R68561
Multi-Protocol Communications Controller (MPCC)
Table 3.
Standard Baud Selection (8.064 MHz Crystal)
Baud Rate Divider
Prescaler Divider
Isochronous and Synchronous
Asynchronous
Hexadecimal Value
Hexadecimal Value
Desired
Baud Rate
(Bit Rate)
Decimal
Value
PSCDIV
(0 to 1)
Decimal
Value
BRDR2
(MSH)
BRDR1
(LSH)
Decimal
Value
BRDR2
(MSH)
BRDR1
(LSH)
50
75
110
135
150
300
1200
1800
2400
3600
4800
7200
9600
19200
38400
3
2
3
2
3
2
3
2
2
2
3
2
3
3
3
1
0
1
0
1
0
1
0
0
0
1
0
1
1
1
26,880
26,880
12,218
14,933
8,960
6,720
1,120
1,120
840
560
280
280
140
70
35
69
69
2F
3A
23
1A
04
04
03
02
01
01
00
00
00
00
00
SA
55
00
40
60
60
48
30
18
18
8C
46
23
53,760
53,760
24,436
29,866
17,920
13,440
2,240
2,240
1,680
1,120
560
560
280
140
70
02
02
SF
74
46
34
08
08
06
04
02
02
01
00
00
00
00
74
AA
00
80
CO
CO
90
60
30
30
18
8C
46
CCR
_2_ RClKIN
ECR
--.!L
-Receiver Clock Internal Select (ASYNC
only).
Select External RxC.
Select Internal RxC.
o
1
o
1
OODPAR -Odd/Even Parity Select (Effective only
when PAREN = 1).
Generate/check even parity.
Generate/check odd parity.
ECR
H.. ClK DIV -External Receiver Clock Divider. Selects
ECR
_3_ CFCRC
-Control Field CRC Enable. (BOP Only)
o
Disable control field CRC.
1
Enables an intermediate CRC remainder to be
appended after the address/control field in transmitted
SOP frames and checked in received frames. The CRC
generator is reset after control field CRC calculation.
the divider of the external RxC to determine
the receiver data rate.
CK2
CKl
o
o
o
Divider
1
1!}(ISOc)
1
32
64
o
1
1
(ASYNC)
only
ECR
.-L
7
6
5
4
3
2
PAREN
ODOPAR
-
-
CFCRC
CRCPRE
1
I
CRCSEL
ECR
J.:Q.. CRCSEl
Reset value = $04
The Error Control Register (ECR) selects the error detection
method used by the MPCC.
ECR
o
-CRC Generator Preset Select.
(BOP, BSC Only)
Preset CRC Generator to O. (For esC)
Preset CRC Generator to 1 and transmit the 1's complement of the resulting remainder. (For SOP)
1
0
CR21 CR1
Address = IF
CRCPRE
o
Error Control Register (ECR)
-.:.L
-Not used .
..H..
CCR
PAREN
-Parity Enable. (ASYNC, ISOC and COP
only).
Disable parity generation/checking.
Enable parity generation/checking.
-CRC Polynomial Select_ Selects one of the
RC polynominals.
1
CR2
0
CRl
o
o
0
1
X16 +X 12 +XS +
x 16 + XIS + x2 +
1
0
x8 + 1
Polynominal
1 (CCITT V.41) (SOP)
1 (CRC-16) (SSC)
(VRC/lRC)" (SSC,
ASCII, non-transparent)
Not used.
"VRC: Odd-parity check is performed on each
character including the LRC character.
6-263
II
R68560, R68561
Multi-Protocol Communications Controller (MPCC)
INPUT/OUTPUT FUNCTIONS
and the OMAC is accomplished by a two-signal request!
acknowledge handshake. Since the MPCC has only one
acknowledge input (OACK) for its two OMA request lines, an
external OR function must be provided to combine the two OMA
acknowledge signals. The MPCC uses the R/W input to
distinguish between the Transmitter Oata Service Request (TOSR
acknowledge and the Receiver Oata Service Request (ROSR)
acknowledge.
MPU INTERFACE
Transfer of data between the MPCCand the system bus involves
the following signals:
R68561
R68560
AO-A4
A1-A4
Address Lines
Oata Lines
00-015
00-07
RiW
R/W
Read/Write
Oata Transfer Acknowledge
OTACK
OTACK
Chip Select
CS
CS
Oata Strobes
·UOS and LOS
OS
Receiver DMA Mode
The receiver OMA mode is enabled when the ROSREN bit in the
RCR is set to 1. When data is available in the RxFIFO, Receiver
Oata Service Request (ROSR) is asserted for one receiver clock
period (BOP and BSC) to initiate the MPCC to memory OMA transfer. For asynchronous operation, ROSR is asserted for 2-3
periods of the system clock depending on prescale factor. The
next ROSR cycle may be initiated as soon as the current ROSR
cycle is completed (i.e., a full sequence of OACK, OS, and OTC).
Figures 10 and 11 show typical interface connections.
ReadlWrite Operation
The RiW input controls the direction of data flow on the data bus.
CS (Chip Select) enables the MPCC for access to the internal
registers and other operations. When CS IS asserted, the data
I/O buffer acts as an output driver during a read operation and
as an input buffer during a write operation. CS must be decoded
from the address bus and gated with address strobe (AS).
In response to ROSR assertion, the OMAC sets the R/W line to
write, asserts the memory address, address strobe, and OMA
acknowledge. The MPCC outputs data from the RxFIFO to the
data bus and the OMAC asserts the data strobes. The memory
latches the data and asserts OTACK to complete the data transfer.
The OMAC asserts OTC to indicate to the MPCC that data transfer
is complete. Figure 14 shows the timing relationships for the
receiver OMA mode.
When the R68561 is connected to the 16-bit bus for operation
in the word mode (WO/BYT = 1 in the PSR2), address lines
A 1-A4 select the internal register(s) (the 8-bit control/status
registers are accesed two at a time and the 16-bit data registers
are accessed on even address boundaries). When the MPCC is
selected (CS low) during a read (RiW high), 16 bits of register
data are placed on the data bus when the data strobes (LOS and
UOS) are asserted. LOS strobes the eight data bits from the even
numbered registers to the lower data bus lines (00-07) and UOS
strobes the eight data bits from the odd numbered registers to
the upper data bus lines (08-015). The MPCC asserts Oata
Transfer Acknowledge (OTACK) prior to placing data on the data
bus. Conversely, when the MPCC is selected (CS low) during
a write (RiW low) LOS and UOS strobe data from the 00-07
and 08-015 data bus lines Into the addressed even and odd numbered registers, respectively, and the MPCC asserts OTACK.
OTACK is negated when CS is negated. Figures 12 and 13
show the read and write timing relationships.
ROSR is inhibited when either ROSREN is reset to 0 or RRES
is set to 1 (both in the RCR), or when RESET is asserted.
Transmitter DMA Mode
The transmitter OMA mode is enabled when the TOSREN bit in
the TCR is set to 1. When the TxFIFO is available, Transmitter
Oata Service Request (TOSR) is asserted for one transmitter clock
period to initiate the memory to MPCC OMA transfer. For asynchronous operation, TOSR is asserted for a period of one-half
the transmitter baud rate. The next TOSR cycle may be initiated
as soon as the current TOSR cycle is completed.
In the transmitter OMA mode, the TxFIFO Is implicitly addressed.
That IS, when the transfer is from memory to the TxFIFO, only
the memory is addressed. In response to TOSR assertion, the
OMAC sets the RiW line to read, asserts the memory address,
the address strobe, the data strobes and OMA acknowledge. The
memory places data on the data bus and asserts OTACK. Oata
is valid at this time and will remain valid until the data strobes
are negated. The OMAC asserts OTC to indicate to the MPCC
that data is available. The MPCC loads the data into the TxFIFO
on the negation (rising edge) of OS and the transfer is complete.
When a TxFIFO underrun occurs, the TUNRN bit is set In TSR2,
the interrupt is issued, and the ABORT sequence is entered (eight
consecutive 1s are transmitted). The next word/byte In TxFIFO
clears the ABORT bit and the idle mode is entered. When a transmission is aborted, it is expected that the interrupt will allow the
host system to decide the next course of action; probably to reset
the DMAC and retransmit the message. A timing diagram for the
transmitter OMA Mode is shown in Figure 15.
When the R68560 is connected to the 8-bit bus for operation in
the byte mode (WO/BYT = 0 in the PSR2), address lines AO-A4
select one internal 8-bit register. When the MPCC is selected (CS
low) during a read (RiW high), eight bits of register data are placed
on data bus lines 00-07 when the data strobe (OS) is asserted.
When the MPCC is selected (CS low) for a write (RiW low), OS
strobes data from the 00-07 data lines into the selected register.
DMA INTERFACE
The MPCC is capable of providing OMA data transfers at up to
2 Mbytes per second when used with the MC68440 or MC68450
OMAC in the single address mode. Based on 4 Mb/s serial data
rate and 5 bits/character, the maximum OMA required transfer
rate is 800 Kbytes per second.
The MPCC has separate OMA enable bits for the transmitter and
receiver, each of which requires a OMA channel. Both the transmitter and receiver data are implicitly addressed (TOR or ROR)
therefore addreSSing of the data register is not required. before
data may be transferred. Communication between the MPCC
TDSR is inhibited when either TOSREN is reset to 0 or TRES
is set to 1 (both in the TCR), or when RESET is asserted.
6-264
R68560, R68561
Multi-Protocol Communications Controller (MPCC)
DONE Signal
Vector
When the DMA transfer count is exhausted in transmitter DMA
mode, the DMAC asserts DONE which sets the TLAST bit in the
TCR to indicate that the last word/byte has been transferred.
In the receiver DMA mode of operation, DONE is issued by the
MPCC on an MPCC-to-memory transfer when the last byte/word
is being transferred from the RxFIFO to the data bus (if DONEEN
bit is set in RCR5). In the byte mode, this is the Frame Status
Byte (FSB). In the word mode, this is the last data byte and FSB
(for an odd number of data byte transfers) or FSB and blank (for
an even number of data byte transfers).
Vector Value
(Hex)
Vector Value
(Binary)
44
01000100
4C
01001100
5C
01011100
Receiver Interrupt
Vector Number
(RIVN)
Transmitter Interrupt
Vector Number
(TIVN)
Serial Interrupt
Vector Number
(SIVN)
!!
tU
A timing diagram for the interrupt acknowledge sequence is
shown in Figure 16.
DONE is asserted as a result of the FSB being transferred and
not as a result of the error conditions. The EOF, C/PERR and
FRERR are addendum bits in the RxFIFO which are written to
FIFO when they occur and follow the data through the FIFO.
The frame is aborted upon overrun or error detection if RCR1 = 1.
SERIAL INTERFACE
The MPCC is a high speed, high performance device supporting
the more popular bit and character oriented data protocols. The
lower speed asynchronous (ASYNC) and isochronous (ISOCH)
modes are also supported. An on-Chip clock oscillator and baud
rate generator provide an output data clock at a frequency of DC
to a 4 MHz .. The clock can also be used in the ASYNC mode to
provide a receive clock for the incoming data. The serial interface consists of the following signals:
CAUTION
DONE is reasserted with each occurrence of DACK
until EOF is cleared in the RSR.
INTERRUPTS
RTS (Request to Send) Output
If an interrupt generating status occurs and the interrupt is
enabled, the MPCC asserts the IRQ output. Upon receiving lACK
for the pending interrupt request, the MPCC places an interrupt
vector on DO-D7 data bus and asserts DTACK.
The RTS output to the DCE is controlled by the RTSLVL bit in
the SICR inn conjunction with the state of the transmitter section.
When the RTSLVL bit is set to 1, the RTS output is asserted.
When the RTSLVL bit is reset to 0 (no sooner than one full cycle
of TxC after transmission has started), the RTS output remains
asserted until the TxFIFO becomes empty, or the end of the
message (or frame), complete with CRC code (if any), clOSing
flag, and one full cycle of idle has been transmitted. RTS also is
negated when the RTSLVL bit is reset during transmitter idle,
or when the RESET input is asserted.
The MPCC has three vector registers: Receiver Interrupt Vector
Number Register (RIVNR), Transmitter Interrupt Vector Number
Register (TIVN), and Serial Interrupt Vector Number Register
(SIVNR). The receiver interrupt has priority over the transmitter
interrupt, and the transmitter interrupt has priority over the
serial interface interrupt. For example, if a pending interrupt
request has been generated simultaneously by the receiver and
the transmitter, the Receiver Interrupt Vector Number (RIVN)
is placed on 00-D7 when acknowledged by the MPU. Upon completion of the first interrupt request cycle (which clears the
receiver interrupt), IRQ will remain low to start the transmitter
interrupt cycle. IRQ is negated by clearing all bits set in a
status register that could have caused the interrupt.
CTS (Clear to Send) Input
The CTS input signal is normally generated by the DCE to indicate whether or not the data set is ready to receive data. The
CTST bit in the SISR reflects the transition status of the CTS
input while the CTSLVL bit in the SISR reflects the current level.
A positive transition on the eTS pin asserts IRQ if the eTS IE bit
in the SIER is set. The CTS input in an inactive state disables
the start of transmission of each frame.
CAUTION
DCD (Data Carrier Detect) Input
A higher priority interrupt occuring while lACK is low during
transfer of a lower priority interrupt vector to the MPU will
cause the lower priority interrupt vector on the data bus
to be invalid if there are any 1's in the higher priority interrupt vector in the same bit poositions as any O's in the
lower priority interrupt vector. To prevent this problem from
occuring, ensure that the higher priority interrupt vectors
contain 1's only in bit positions where there are 1's in the
lower priority interrupt vectors, e.g.:
The DCD input signal is normally gnerated by the DeE and indicates that the DeE is receiving a data carrier Signal suitable for
demodulation. The DCDT bit in the SISR reports the transition
status of the DCD input while the DCDLVL bit in the SISR contains the current level. A positive transition on the DCD pin
asserts the IRQ output if the DCD IE bit in the SIER is set. A
negated DCD input disables the start of the receiver but does
not stop the operation of an incoming message already in
progress.
6-265
•
I
R68560, R68561
Multi-Protocol Communications Controller (MPCC)
DSR (Data Set Ready) Input/RSYN Output
For low speed operation between the MPCC and a modem or
RS-232C Data Communications Equipment (DCE), an inverter
can be used in the TxC output lines as shown in Figure 17.
RS-232 and RS-423 (covering senal data interface up to
lOOK baud) reqUIre that data be centered ± 25% about the
negative-going edge of the RxC. This criteria is met for frequencies up to 1.25 MHz using the inverter. Use of the inverter
also allows MPCC to MPCC operation up to 2.17 MHz.
The DSRT input from the DCE Indicates the status of the local
set. The DSRT bit in the SISR contains the transition status of
the DSR input while the DSRLVL bit In the SISR reports the
current level. A negative transition on the DSR pin asserts the
IRQ output If the DSR IE bit In the SIER is set.
The DSR pin IS used as an output for RSYN when enabled by
a 1 in RSR4 (RSYNEN = 1). DSR output low Indicates detection
of a SYN (non-transparent) In BSC or COP protocols or DLESYN pair (transparent) in BSC protocol. It IS asserted as a
negative-going pulse one-bit time after the end of the SYN byte
and lasts for one full serial clock cycle before being reset.
SERIAL COMMUNICATION MODES
AND PROTOCOLS
In BOP protocol. RSYN is asserted as a result of address match
at the beginning of a frame. It IS asserted one bit time after the
end of the address byte(s) if an address match is made. and
lasts for one full serial clock cycle.
ASYNCHRONOUS AND ISOCHRONOUS MODES
Asynchronous and isochronous data are transferred In frames.
Each frame consists of a start bit, 5 to 8 data bits plus optional
even or odd panty, and 1, 1 '/2, or 2 stop bits. The data character IS transmitted with the least significant bit (LSB) first. The data
line IS normally held high (MARK) between frames, however, a
BREAK (minimum of one frame length for which the line is held
low) IS used for control purposes. Figure 4 illustrates the frame
format supported by the MPCC.
DTR (Data Terminal Ready) Output
The DTR output is general purpose in nature and can be used
to control sWitching of the DCE. The DTR output is controlled by
the DTRLVL bit In the SICR.
TxC (Transmitter Clock) Input/Output
Asynchronous Receive
The transmitter clock (TxC) may be programmed to be input or
an output. When the TCLKO control bit In the CCR is set to a
1, the TxC pin becomes an output and provides the DCE with
a clock whose frequency is determined by the internal baud rate
generator. When the TCKLO control bit is reset, TxC IS an input
and the transmitter shift timing must be prOVided exernally. The
TxD output changes state on the negative-going edge of the
transmitter clock. In the asynchronous mode when TCLKO = 0
in the CCR, the TxC Input frequency must be two times the
deSired baud rate.
In the asynchronous (ASYNC) mode, data recepllOn on RxD
occurs In three phases: (1) detecllOn of the start bit and bit
synchronization, (2) character assembly and optional parity check,
and (3) stop bit detection. The receiver bit stream may be synchronized by the Internal baud rate generator clock or by an external
clock on RxC. When RCLKIN in the CCR is set to 0, an external
clock with a frequency of 16, 32, or 64 times the data rate establishes the data bit midpoint and maintainS bit synchronization.
The character assembly process does not start If the start bit is
less than one-half bit time. Framing and parity errors are
detected and buffered along with the character on which errors
occurred. They are passed on to the RxFIFO and set appropriate
status bits in the RSR when the character with an error reaches
the last RxFIFO register where it IS ready to be transferred onto
the data bus via the RDR.
TxD (Transmitted Data) Output
The serial data transmitted from the MPCC is coded in NRZ data
format. The first byte of a message transmitted out of the R68561
MPCC is the even byte of the 68000 bus (D8-DI5). It IS transmitted least significant bit (LSB) first.
Isochronous Receive
RxC (Receiver Clock) Input
In the isochronous (ISOC) mode, a times 1 clock on RxC IS
required with the data on RxD and the serial data bit is latched
on the falling edge of each clock pulse. The requirement for the
detection of a valid start bit, or the beginning of a break, is satisfied by the detection of a high-to-Iow transition on the serial data
Input line. Error detection and status indication are the same as
the asynchronous mode.
The receiver latches data on the negative transition of the RxC.
RxD (Received Data) Input
The serial data received by the MPCC IS in NRZ data format.
The first byte received In the MPCC RXFIFO is output to the
68000 bus on (D8-DI5).
Serial Interface Timing
Asynchronous and Isochronous Transmit
The timing for the serialmterface clock and data lines is shown
in Figure 18. The MPCC supports high speed synchronous operation. As shown, the TxD output changes with the negative-gOing
edge of TxC and the received data on RxD is latChed on the
negative edge of RxC. This assures high speed two-way operation between two MPCCs connected as shown In Figure 17.
In asynchronous and isochronous transmit modes, output data
transmission on TxD begins with the start bit. This is followed
by the data character which is transmitted LSB first. If parity generation is enabled, the panty bit IS transmitted after the MSB of the
character. Each frame IS terminated with 1, 1'1, or 2 stop bits as
selected by PSR2 bits 5 and 6.
6-266
Multi-Protocol Communications Controller (MPCC)
R68560, R68561
I
ASYNCHRONOUS FRAME FORMAT
r--T----r~----,--"'T--
LJ_L_
1___L___ -r~-----l---L--J
DATA
I
START
I
lBS
I
I
~
MSB
1 PARITY 1 STOP
(OPT)
(1, 1'A1, OR 2 BITS)
1 -
.1
5T08BITS
ISOCHRONOUS FRAME FORMAT
ClK
DATA
I
I
t-._
I -Ii--I----(~----l--l-- II
I
L_....J._
1 -_
- - -Tr----.J...--..L--.J
STOP
lBS
MSB
~C::~:Y (lOR
2 BITS)
I
I
........
START
14
I
address field can be extended by selling the ADDEX bit to a 1
in PSR1. In this case, the address field Will be extended until the
occurrence of an address byte with a 1 in bit o. The first byte
of the address field is automatically checked when the MPCC is
programmed to be a secondary station in BOP. An automatic
check for global (11111111) or null (00000000) address is also
made. The control field of one or two bytes is transparent to the
MPCC and sent directly to the host without interpretation.
In synchronous modes, a times one clock is provided along with
the data. Serial output data is shifted out and input data is latched
on the falling edge of the clock.
BIT ORIENTED PROTOCOLS (BOP)
In bit oriented protocols (BOP), messages (data) are transmitted
and received in frames. Each frame contains an opening flag,
address field, control field, frame check sequence, and a closing
flag. A frame may also contain an information field. (See Figure 5).
The optional information field consists of 8-bit characters. Cyclic
redundancy checking is used for error detection and the CRC
remainder resulting from the calculation is transmitted as the
frame check sequence field. For BOP, the polynomial X16 + X12
+ X5 + 1 (CRC-CCITT) should be used, i.e., selected in the
CRC SEL bits in the ECR. The registers representing the
CRC-CCITI polynomial are generally preset to allls, and the ls
complement of the resulting remainder is transmitted. (See
X.25 Recommendation.)
The opening flag is a special character whose bit pallern is
01111110. It marks the frame boundaries and is the Interframe
fill character. The address field of a frame contains the address
of the secondary station which is receiving or responding to a
command. The address field may be one or more bytes long. The
FLAG
ADDRESS
lOR N
BYTES
CONTROL
lOR
2 BYTES
Figure 5.
I
Asynchronous and Isochronous Frame Format
SYNCHRONOUS MODES
01111110
1
.1
5 TO 8 BITS
Figure 4.
I
INFORMATION
N BYTES
(OPTIONAL)
Bit Oriented Protocol (BOP) Frame Format
6-267
FCS
FLAG
2 BYTES
01111110
•
Multi-Protocol Communications Controller (MPCC)
R68560, R68561
For the control field, one or two bytes are assembled and passed
on to the RxFIFO depending on the state of the extended control field bit.
Zero insertion/deletion IS employed to prevent valid frame data
from being confused with the special characters. A 0 is Inserted
by the transmitter after every fifth consecutive 1 in the data
stream. These inserted zeros are removed by the receiver to
restore the data to Its onglnal form. The inserted zeros are not
included In the CRC calculation.
If the CFCRC bit in the ECR is set to 1, an intermediate CRC
check will be made after the address and control field. The Frame
Check Sequence is stili calculated over the remainder of the
frame.
The end of the frame is determined by the detection of the closing
Flag special character which IS the same is the opening Flag.
With the control options offered by the MPCC, commonly used
bit onented protocols such as SOLC, HDLC and X.25 standards
can be supported. Figure 6 compares the requirements of these
options.
BOP Transmitter Operation
In BOP, the TxFIFO can be preloaded through the TOR while
the transmitter IS disabled (TEN = 0 In the TCR). When the transmitter is enabled (TEN = 1 In the TCR), the leading Flag is automatically sent prior to transmitllng data from the TxFIFO. The
TORA bit is set to 1 In the TSR as long as TxFIFO is not full.
If an underrun occurs, the TUNRN bit In the TSR is set to a 1
and an Abort (11111111) is transmitted followed by continuous
Flags or marks until a new sequence is initiated.
BOP Receiver Operation
In BOP, the receiver starts assembling characters and accumulallng CRC immediately after the detection of a Flag. The receiver
also continues to search for additional Flag, or Abort, characters on a bit-by-blt basIs. Zero deletion is Implemented in the
Receiver Shift Register after the Flag detection logic and before
the CRC circuitry. The receiver recognizes the shared flag (the
clOSing flag for one frame serves as the opening flag for the next
frame) and the shared zero (the ending 0 of a closing flag serves
as the beginning 0 of an opening flag forming the pattern
"011111101111110."
The TLAST bit In the TCR must be set prior to loading the last
character of the message to signal the transmitter to append
the two-byte Frame Check Sequence (FCS) follOWing the last
character. If the transmitter DMA mode is selected (the TDSREN
bit set to 1 In the TCR) the TLAST bit is set by the DONE signal
from the OMAC.
Character assembly and CRC accumulation are stopped when
a closing Flag or Abort IS detected. The CRC accumulation
includes all the characters between the opening Flag and the
clOSing Flag. The contents of the CRC register are checked at
the close of a frame and the C/PERR bit In the RSR IS updated.
The FCS and the Flag are not passed on to the RxFIFO.
A message may be terminated at any time by setting the TABT
bit In the. TCR to 1. ThiS causes the transmitter to send an Abort
character followed by the remainder of the current frame data
In the TxFIFO.
If the Flag is a clOSing flag, checks for short frame (no control
field) and CRC error conditions are made and the appropriate
status is updated. When an Abort (seven IS) is detected, the
remaining frame IS discarded and the RAJB bit is set In the RSR.
When a link Idle (15 or more consecutive Is) is detected, the
RIOLE status bit IS set In the RSR. The zeros that have been
inserted to diSlingUish data from speCial characters are detected
and deleted from the data stream before characters are assembled. The MPCC programmed as a secondary station provides
automatic address matching of the first byte. If there IS no
address match, or If null address is received, the receiver ignores
the remainder of the frame by searching for the Flag. If there
is a match, the address bytes are transferred to the RxFIFO as
they are assembled.
The senal data from the Transmitter Shift Register is continuously monitored for five consecutive 1s, and a 0 is inserted in
the data stream each time this condition occurs (excluding Flag
and Abort characters).
CRC accumulation begins with the first non-Flag character and
includes all subsequent characters. The CRC remainder is transmitted as the FCS following the last data character. If the
CTLCRC bit in the ECR IS set to 1, an Intermediate CRC
remainder IS appended after the Address and Control field. The
final Frame Check Sequence IS calculated over the balance of
the frame.
IBM SOLC FRAME FORMAT
FLAG
01111110
ADDRESS
1 BYTE
CONTROL
1 BYTE
INFORMATION
N BYTES
FCS
2 BYTES
01111110
FLAG
ADDRESS
N BYTES
CONTROL
lOR
2 BYTES
INFORMATION
N BYTES
FCS
2 BYTES
FLAG
01111110
HDLC FRAME FORMAT
FLAG
01111110
Figure 6.
------
Bit Oriented Protocols
6-268
R68560, R68561
LEADING PAD
1 BYTE
(AR1)
Multi-Protocol Communications Controller (MPCC)
SYN
1 BYTE
(AR2)
SYN
1 BYTE
(AR2)
BODY
BCC
TRAILING
PAD
11111111
Figure 7. BSC Block Format
BISYNC (BSC)
ETB followed by the BCC. Only the first SOH or STX in a transmission block following a line turnaround causes the BCC to
reset. All succeeding STX or SOH characters are included in
the BCC. This permits the entire transmission (excluding the first
SOH or STX) to be block-checked.
The structure of messages utilizing the IBM Binary Synchronous
Communications (BSC) protocol, commonly called Bisync, is
shown in Figure 7. The MPCC can process both transparent and
nontransparent messages using either the EBCDIC or the ASCII
codes. The CRC-16 polynomial should be selected by setting
the appropriate CRCSEL bits in the ECR for both transparent
and non-transparent EBCDIC and for transparent ASCII coded
messages. VRC/LRC should be selected for non-transparent
ASCII coded messages. BSC messages are formatted using
defined data-link control characters. Data-link control characters
generated and recognized by the MPCC are listed in Table 4.
Table 4.
BSC Control Sequences-Inclusion
In CRC Accumulation
ASCII
Command
SYN
SOH
STX
ETB
ETX
ENO
DLE
ITB
EOT
ACK N"
NAK
WACK
RVI
The text data is transmitted in complete units called messages,
which are initiated by STX and concluded with ETX. A message
can be subdivided into smaller blocks for ease in processing
and more efficient error control. Each block starts with STX and
ends with ETB (except for the last block of a message, which
ends with ETX). A single transmission can contain any number
of blocks (ending with ETB) or messages (ending with ETX). An
EOT following the last ETX block indicates a normal end of transmission. Message blocking without line turnaround can be
accomplished by using ITB (see the Additional Data Link Capabilities section, IBM GA 27-3004-2).
~e1
Byte 2
16"
01
02
17
03
05
10
1F
04
10
15
10
10
-
30-37
-
3B
3C
Command
SYN
SOH
STX
EOB (ETB)
ETX
ENO
DLE
ITB
EOT
ACKO
ACK 1
NAK
WACK
RVI
EBCOIC
EI}'te 1
32"
01
02
26
03
2D
10
1F
37
10
10
3D
10
10
~e2
Two modes of data transfers are used in BSC. In non-transparent
mode, data link control characters may not appear as text data.
In transparent mode, each control character is preceded by a
data link escape (OLE) character to differentiate it from the text
data. Table 5 indicates which control characters are excluded
in the CRC generation. All characters not shown in the table are
included in the CRC generation. Figure 8 shows various formats
for Control/Response Blocks and Heading and Text Blocks.
-
-
-
70
61
-
Table 5.
Transparent Mode BSC Control Sequences Inclusion In CRC Accumulation
Included in CRC Accumulation
Character of Sequence
Yes
No
TSYN
DLESYN
TSOH
DLESOH
TSTX"
DLESTX
TETB
ETB
DLE
TETX
ETX
DLE
TDLE
(DLE)DLE
DLE(DLE)
"If not preceded within the same block by transparent heading
information.
6B
7C
Note: "Programmable
-
A heading is a block of data starting with an SOH and containing one or more characters that are used for message control
(e.g., message identification, routing, and priority). The SOH initiates the block-check-character (BCC) accumulation, but is not
included in the accumulation. The heading is terminated by STX
when it is part of a block containing both heading and text. A
block containing only a heading is terminated with an ITB or an
6-269
•
Multi-Protocol Communications Controller (MPCC)
R68560, R68561
CONTROL/RESPONSE BLOCKS:
ADDRESS
NEGATIVE ACKNOWLEDGEMENT
HEADING AND TEXT BLOCKS:
RESET BCC
SYN
I
-1. .------NCLUDED
SOH
'HE~:'NG
I
IN Bec
--------1-1
I
I
ETB
BCC
I
IFOLLOW-I
ING PAD
HEADING ONLY
~INCLUDED IN BCC"---I
SYN
I
::
IDLE"
TRANSPARENT TEXT
Figure 8.
esc Message Format Examples
6-270
I
ETX
I
BCC
I FOLLOW-I
ING PAD
"DLE EXCLUDED FROM BCC CALCULATION
Multi-Protocol Communications Controller (MPCC)
R68560, R68561
SSC Receiver Operation
CHARACTER ORIENTED PROTOCOLS
Character length defaults to eight bits in SSC mode. When ASC"
is selected, the eighth bit is used for parity provided that
VRC/LRC polynomial is selected. Character assembly starts after
the receipt of two consecutive SYN characters. Serial data bits
are shifted through the Receiver Shift Register into the Serialto-Parallel Register and transferred to the RxFIFO. The ROA status bit in the RSR is set to 1 each time data is transferred to
the RxFIFO. The SYN character pairs in non-transparent mode
and OLE-SYN pairs in transparent mode are discarded.
The character oriented protocol (COP) option uses the format
shown in Figure 9. It may be used for various character oriented
protocols with 5-8 bit character sizes and optional parity checking. The input data is checked on a bit-by-bit basis for a pair
of consecutive SYN characters to establish character
synchronization. These SYN characters are discarded after
detection. The PAO and SYN characters may be 5-8 bits long
and are user programmable as stored in AR1 and AR2,
respectively.
The receiver starts each block in the non-transparent mode. It
switches to transparent mode if a block begins with a OLE-SOH
or OLE-STX pair. The receiver remains in transparent mode until
a OLE-ITS, OLE-ETS, OLE-ETX or OLE-ENQ pair is received.
SCC accumulation begins after an opening SOH, STX, or OLESTX. SYN characters in non-transparent mode or OLE-5YN pairs
in transparent mode are excluded from the SCC accumulation.
The first OLE of a OLE-OLE sequence is not included in the SCC
accumulation and is discarded. The SCC is checked after receipt
of an ITS, ETS, or ETX in non-transparent mode or OLE-ITS,
OLE-ETS, OLE-ETX in transparent mode. If a CRC error is
detected, the C/PERR and EOF bits in the RSR are set to 1.
If no error is detected only the EOF bit is set. If the closing
character was an ITS, SCC accumulation and character assembly starts again on the first character following the SCC.
If parity checking is enabled the characters assembled after
character sync are checked for parity errors. If STRSYN is set
in the RCR, all SYN characters detected within the message
wi" be discarded and will not be passed on to the RxFIFO. If
STRSYN is reset, SYNs detected within the message will be
treated as data.
DMA CONSIDERATIONS
When the R68561 , in the word mode, is used with a OMAC, high
throughput of bit-oriented protocols is achieved. However, problems can arise when trying to OMA byte-oriented data in the word
mode.
SOP and SSC have well-defined message boundaries and the
MPCC can detect the end of message, determine if there is an
odd (Single) byte at the end of a message, and so inform the
host MPU by setting the Received Half Word (RHW) bit in the
Frame Status byte.
SSC Transmitter Operation
BSC transmission begins with the sending of an opening pad
(PAO) and two sync (SYN) characters. These characters are
programmable and stored in AR1(PAO) and AR2(SYN). The first
SOH or STX initiates the block-check-character (SCC) accumulation. An initial SOH or STX is not included in the SCC accumulation. Should an underrun condition occur, the content of AR2
(normally SYN character) is transmitted until new characters
become available. The message is terminated by the transmission of the SCC followed by a closing pad when an ETB, ITS,
or ETX is fetched from the TxFIFO. The closing PAO is generated by the MPCC.
In byte-oriented protocols (such as ASYNC and COP) there is
no defined message length. In the word mode, received bytes
are grouped in pairs. In the byte mode, each byte is available
through the RxFIFO as it is received. Thus, the MPCC in the
word mode has no way of knowing when an odd (single) byte
has been received at an end of a transmission to be passed onto
the host MPU. In the word mode received bytes are grouped
in pairs. In the byte mode each byte is available through the FIFO
as it is received.
In transparent mode, the SCC accumulation is initiated by OLESTX and is terminated by the sequences OLE-ETX, OLE-ETS,
or OLE-ITS. See Table 5 for character sequence and inclusion
in CRC accumulation. If an underrun occurs, OLE-SYN characters will be transmitted until new characters are available in the
TxFIFO. ETS, ETX, ITS, or ENQ with a TLAST tag is treated
as a control character and the MPCC automatically inserts a OLE
immediately preceding these characters. OLE-ETS, OLE-ETX,
OLE-ITS, or OLE-ENQ terminates a block of transparent text,
and returns the data link to normal mode. SCC generation is
not used for messages beginning with characters other than
SOH, STX, OLE-SOH, or OLE-STX. On all message types, if the
TSYN bit is set to 1 in the TCR, a SYN-SYN (OLE-SYN sequence
on transparent messages) sequence is transmitted before the
next character is fetched from the TxFIFO.
LEADING PAD
5-8 BITS
(AR1)
SYN
5-8 BITS
(AR2)
SYN
5-8 BITS
(AR2)
For transmission of data by the MPCC in the word mode, the
MPCC provides a Transmit Half Word (THW) bit in the Transmit Control Register. When set, this bit informs the MPCC that
the last word in the TxFIFO (marked by setting the TLAST bit
with OONE) contains only the upper byte as valid data. However,
the currently available OMACs have no method to inform the
MPCC that the last word of the message contains a single byte
and MPU intervention is necessary.
To handle byte-oriented protocols with OMAC, an R68561 in the
byte mode or the R68560 (byte mode only) should be used.
1+-------
MESSAGE
5-8 BIT CHARACTERS
Figure 9. Character Oriented Protocol Format
6-271
--------.j
•
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01
~\
AEQO
TDSR
REa,
=
0
OJ
C?
~
(I)
ROSA
ACKl
1-~I
DTC
R6856l
MPCC
~1!2
=1
'" '"
-I
"'U
~
o
o
3
c
3
__
IRQ
~
~
C:;"
'----
OSC
,"
2.
-
t-t-----------------------------~----------~S~Y~==E~M~C~LO~C~K~~
CLOCK
:!:
;..
()
ACKO~DACK
MC6844Q
DONE
~
5:
c
;:;
u.
2
0
CI rl ~
;! ~ ~ ~I
~
'r'"
>
~
r~~~~~~L-~~------~~~.-______~~~lL~~~~~
DMAC
A2
JO--++------,..qG2A
GATED
I;h~1~
+5V
i't
,..---
......!Q...
r
~~~ ~:to
CV CD III C ;0. C r
MEMORY
~....§-
74LS138
BoO ,./
~
m!
aS"
~
(I)
~
-a.
]
~
CD
-
NOTE: UDS MAY BE TIED LOW (GROUND).
5:
"'U
Figure 10.
Typical Interface to 68000-Based System
g
-
:u
CJ)
CD
U'I
CJ)
5='
:u
CJ)
AO-A19
CD
U'I
IA
00-07
I'
RIW
-H>
-I · ~t
DTACK
I....
iR
r
f-----
.---
I"14
"LO
IPL1
0
~
~
r
74lS148-+
~
-1-
r.c2
I
E1
;!
~I
IROS
~
r--2---
~
l
~t~ ~ ~
r'~~I~'
C> C>
1;
"
ltJ
J
~llJBUS
~
~I~I
..7
'"
W
~
~I
o.-
"
~I
~
~
r---
AJ
C
A2
A
74LSl38
G2A
Lc
.
r-v2
B
A1
YO
~
G28
1K
+5V~Gl
L..--
~
~
~
VB
"
01::IJ
3:
c
0
en ~l ~
&!I
MC68440
AeKO
DMAC
ACKl
~->.
A68560
MPCC
"
"U
:
~
f4
IRQ
RTS ..
~
(')
2-
g
3
3
c
lACKS
lAC':..,.
IACKa
~
14 ~~_
ROSA
DACK
~ ~I
~I
;::;
1
rDSR
DONE
I~I ~o
~ ~
I~r-'
'1
REal
MEMORY
~~~
~°1
REOO
OJ
-.J
~, ""l!l
~v."
8G
BGACK
~
-
AS
MC68008
MPV
....
r--
r--
OS
CJ)
,---
r
::l
rYL
c;"
SYSTEM CLOCK
~l~
!!
c)"
::l
(I)
I ~OCK J
oo
-a...
::l
CD
3:
"U
Figure ". Typical Interface to 6800B-Based System
II
.8
R68560, R68561
Multi·Protocol Communications Controller (MPCC)
SOURCE
MPU
A1-A4
AO'
MPU
BUS
CS
MPU
LDSIDS
UDS2
MPU
rWi
MPCC
DTACK
MPCC
Do-D15
~----~4r-----~
NOTES:
1. BYTE MODE WHEN CONNECTED TO AD ON 68008 BUS.
2. WORD MODE WHEN CONNECTED TO UDS ON 68000 BUS.
3. TIMING MEASUREMENTS ARE REFERENCED TO AND FROM A LOW VOLTAGE OF 0.8 VOLTS AND A HIGH VOLTAGE
OF 2.0 VOLTS, UNLESS OTHERWISE NOTED.
4. SEE ADDITIONAL NOTES ON PAGE 32.
Figure 12. MPCC Read Cycle Timing
SOURCE
MPU
A1-A4
AO'
MPU
BUS
CS
MPU
LDSIDS
UDS2
MPU
R/W
MPCC
DTACK
14----(11}------..j....-{1
MPU
OO-D15
DATA IN
NOTES:
1. BYTE MODE WHEN CONNECTED TO AD ON 68008 BUS.
2. WORD MODE WHEN CONNECTED TO UDS ON 68000 BUS.
3. TIMING MEASUREMENTS ARE REFERENCED TO AND FROM A LOW VOLTAGE OF 0.8 VOLTS AND A HIGH VOLTAGE
OF 2.0 VOLTS, UNLESS OTHERWISE NOTED.
4. SEE ADDITIONAL NOTES ON PAGE 32.
Figure 13. MPCC Write Cycle Timing
6-274
R68560, R68561
Multi-Protocol Communications Controller (MPCC)
SOURCE
INTERNAL
RECEIVER
CLOCK
(BAUD RATE)
MPCC
RDSR
DMAC
DACK
DMAC
LOS/OS
UDS/AO'
MPCC
00-015
DMAC
R/W
MPCC
DONE
DMAC
DTC
\
I
\
~
@
~
I
NOTES:
1. TIMING MEASUREMENTS ARE REFERENCED TO AND FROM A LOW VOLTAGE OF 0.8 VOLTS AND A HIGH VOLTAGE
OF 2.0 VOLTS UNLESS OTHERWISE NOTED.
2. WORD MODE ONLY.
3. SEE ADDITIONAL NOTES ON PAGE 32.
Figure 14.
MPCC to Memory DMA Transfer Cycle Timing (Receiver DMA Mode)
•
6-275
R68560, R68561
Multi-Protocol Communications Controller (MPCC)
SOURCE
INTERNAL
TRANSMITTER
CLOCK
(BAUD RATE)
MPCC
TDSR
DMAC
DACK
DMAC
LDS/DS
UDS/A02
MEMORY
00-D15
DMAC
RIW
DMAC
DONE
DMAC
DTC
\
/
t
@
\
I
1
I
\
NOTES:
1. TIMING MEASUREMENTS ARE REFERENCED TO AND FROM A LOW VOLTAGE OF 0.8 VOLTS AND A HIGH VOLTAGE
OF 2.0 VOLTS UNLESS OTHERWISE NOTED.
2. WORD MODE ONLY.
3. SEE ADDITIONAL NOTES ON PAGE 32.
Figure 15. Memory to MPCC DMA Transfer Cycle Timing (Transmitter DMA Mode)
6-276
R68560, R68561
Multi-Protocol Communications Controller (MPCC)
SOURCE
MPCC
MPU
IRQ
~
!
'-
lACK
MPCC
OTACK
MPU
LOS/OS
26
MPCC
00-07
INTERRUPT VECTOR
NOTES:
1. TIMING MEASUREMENTS ARE REFERENCED TO AND FROM A LOW VOLTAGE OF 0.8 VOLTS AND A HIGH
VOLTAGE OF 2.0 VOLTS, UNLESS OTHERWISE NOTED.
2. IRQ IS NEGATED WHEN ALL BITS IN STATUS REGISTERS THAT COULD HAVE CAUSED THE INTERRUPT
ARE CLEARED.
3. SEE ADDITIONIONAL NOTES ON PAGE 32.
Figure 16.
Interrupt Request Cycle Timing
MDCCl
MPCC2
MPCC 1
TxC
RxC
TxC
TxD
RxD
TxD
Rx DATA (BB)
RxC
TxC
RxC
Tx TIMING (DA)
RxD
TxD
RxD
Tx DATA (BA)
HIGH SPEED INTERFACE
MODEM/DCE
...
Rx TIMING (DO)
LOW SPEED (RS-232) It.iTERFACE
Figure 17. Serial Interface
6-277
•
R68560, R68561
Multi-Protocol Communications Controller (MPCC)
HIGH SPEED APPLICATION
. .- - - - - ( 3 0 ) - - - - -.....
TxC/RxC
TxD/RxD
LOW SPEED APPLICATION (RS·232 COMPATIBLE)
TxC
TxD
DATA A
RxC (TxC)
Figure 18. Serlallnterfaee Timing
RxD
TxD
__________________________________
"
JJ~
__________
NOTE:
TIMING MEASUREMENTS ARE REFERENCED TO AND FROM A LOW VOLTAGE OF 0.8 VOLTS AND A HIGH VOLTAGE
OF 2.0 VOLTS, UNLESS OTHERWISE NOTED.
Figure 19. Serlallnterfaee Eeho Mode Timing
6·278
Multi-Protocol Communications Controller (MPCC)
R68560, R68561
AC CHARACTERISTICS
(Vcc
oz
5.0 Vdc ±5%, Vss = 0 Vdc, TA = OOC to 70°C)
Max
Unit
ns
30
-
ICLDAL
0
60
ns
CS, OS Low 10 Oala Valid
IsLOV
0
140
ns
5
OS High 10 Dala Invalid
IsHoXR
10
150
ns
6
OS High to DTACK High
ISHOAT
0
40
ns
7
OS High 10 Address Invalid
ISHA!
20
ns
8
CS, OS High 10 RIW Low
ISHRL
20
-
9
RIW Low 10 CS, OS Low
IRLSL
0
CS High, OS High 10 RIW High
ISHRH
20
Number
Parameter
Symbol
Min
1
RIW High to CS, OS Low
IRHSL
0
2
Addrass Valid 10 CS, OS Low
IAVSL
31
CS Low 10 OTACK Low
41
10
ns
ns
-
ns
60
-
ns
0
-
ns
60
-
ns
ns
11
Date Valid 10 CS, OS High
IOVSH
12
CS, OS High 10 Date Invalid
I SHOXW
17
DTC Low 10 OS High
!cLSH
18
DACK Low to Dala Valid, DONE Low
IALOV
0
140
ns
19
OS High 10 Dala Invalid
ISHOXOR
10
150
ns
21
Data Valid 10 OS High
IOVSH
60
OS High 10 Dala Invalid
ISHOXDW
0
-
ns
22
25
lACK Low 10 DTACK Low
I'ALAL
0
40
ns
26
lACK, OS Low 10 Date Valid
I,ALOV
0
140
ns
27
OS High 10 Data Invalid
t'SHOI
10
150
ns
0
40
ns
-
ns
28
lACK High to DTACK High
t'AHOAT
30
RxC and TxC Period
!cP
248
ns
31
TxC Low to TxD Dalay
tTCLTD
0
200
ns
32
AxC Low to RxD Transition (Hold)
tRCLRO
0
ns
33
AxD Transition to AxC Low (Satup)
t RORCL
30
-
34
RxD to TxD Dalay (Echo Mode)
tRoTO
-
200
ns
35
RIW Low to DACK Low (Satup)
tRLAL
0
ns
38
DACK High to DONE High
t AHoH
0
-
372. 3
RDSR Pulse Width
tRPW
1
ciock period
31)2.4
TDSR Pulse Width
tTPW
1
-
ns
ns
ciock period
Nota8:
1. For read cycle timing, the MPCC asserts DTACK within the MPU S4 clock low setup lime requirement and establishes
valid date (Data In) within the MPU S6 clock low setup time requirement.
2. For synchronous protocols, Ih.!!..!!.2ne full serial clock period of RxC for RDSR and TxC for TDSR.
3. For asynchronous protocols, RDSR is asserted for two system clock periods for a prescale factor of 2 and for three system clock
periods for a prescale factor of 3.
4. For asynchronous protocols, TDSR is asserted for a period of one-half the baud rate.
-NOTES TO FIGURES 12-16.
(tsHDXR. item 5) will remain valid for 0-150 ns after the negation of
CS or LOS. whichever is negated first.
Address. LOS. UOS and RiW are signals generated by the
68000 MPU and Its bus timing prevails. CS is derived with
external~ic from the address bus and generally an Address
Strobe (AS) signal from the MPU. It will naturally be delayed
somewhat from the AS signal. The active read or write cycle
timing in the MPCC Is during the summation of the active signal time, i.e.• the laat active signal starts the timing sequence.
For an MPCC read cycle, for example. the data out parameter
(fsLov. item 4) will be available 0 to 140 ns from the falling edge
of CS or LOS whichever Is active laat. The data out parameter
The minimum pulse widths for CS, LOS. UOS, OACK. lACK and
ore are not specified since they are system dependent and relate
to system clock timing. For example, it is apparent that the minimum active time for "AND" condition of CS and LOS is 140 ns
(tsLOV, ite~ plus the setup time of the Data In to the receiving
device if LOS high is used to strobe the data in. These same factors hold true for UOS, OACK and lACK. If DTC is used it must be
true a minimum of 60 ns before the rising edge of LOS and thus
this is the minimum pulse width. It may be connected to ground.
6-279
•
Multi-Protocol Communications Controller (MPCC)
R68560, R68561
ABSOWTE MAXIMUM RATINGS*
Symbol
Value
Unit
Supply Voltage
Parameter
Vee
-0.3 to + 7.0
V
Input Voltage
VIN
-0.3 to + 7.0
V
Operating Temperature Range
TA
o to +70
·C
Storage Temperature
TSTG
-55 to +150
·C
"NOTE: Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in other
sections of this document is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS
Parameter
Symbol
Thermal Resistance
Ceramic
Plastic
8JA
Value
Rating
·CIW
50
68
DC CHARACTERISTICS
(Vee
= 5.0 Vdc
±5%, Vss
= 0 Vdc,
TA
= O°C to 70·C
unless otherwise noted)
Symbol
Min
Max
Unit
Input High Voltage
All Inputs
VIH
2.0
Vee
V
Input Low Voltage
All Inputs
VIL
-0.3
+0.8
V
Inpu!.-Leakage C.l!!:!.ent
RIW, RESET, CS, A1-A4
liN
-
10.0
pA
VIN = 0 to 5.25V
Vce = 5.25V
Three-State (Off State) Input Current
IRQ, OTACK, 00-015
TTSI
-
10.0
pA
VIN = 0.4 to 2.4V
Vee = 5.25V
Output High Voltage _ _
ROSR, TDSR, IRQ, OTACK, 00-015, OSR, OTR, RTS,
TxO, TxC
VOH
Vss + 2.4
-
V
VOH
Vss + 2.4
-
V
VOL
-
0.5
V
VOL
-
0.5
V
Vee = 4.75V
ILOAD = 8.8 rnA
-
1
W
TA
13
pF
VIN = OV
TA = 25°C
f = 1 MHz
Parameter
BCLK
Output Low Voltage
ROSR, TDSR, IRQ, OTACK 00-015, OSR, OTR, RTS,
TxO, TxC, BCLK,
OONE
Internal Power Oissipation
Input Capacitance
PINT
CIN
6-280
Test Conditions
Vee = 4.75V
ILOAD = - 400 pA
CLOAD = 130 pF
Vee = 4.75V
ILOAD = 0
CLOAD = 30 pF
Vec = 4.75V
ILOAD = 3.2 rnA
= 25·C
Multi-Protocol Communications Controller (MPCC)
R68560, R68561
PACKAGE DIMENSIONS -
40-PIN DIP
40-PIN CERAMIC DIP
[::J:::I:::::JJ
I
A
I
F==1l
ll~~-I~ L -=I~\\-.--M
--!G~
~ ---.l
"
-ILD
!
c
MILLIMETERS
DIM MIN
MAX
A 50 29 5131
B 1473 1524
C
330
432
D
038
053
F
102
152
254 sse
G
J
020
030
K
254
406
L 1499 1549
M
100
0"
N
102
152
INCHES
MIN MAX
1980 2020
0580 0600
0130 0170
0015 0021
0040 0060
0100 ase
0008 0012
0100 0160
0590 0610
10"
0"
0040 0060
40-PIN PLASTIC DIP
MILLIMETERS
INCHES
DIM MIN
MAX MIN MAX
A 5182 5232 2040 2060
B 1372 1422 0540 0560
C
406
508 0160 0200
D
038
053 0015 0021
F
140 0045 0055
114
G
254 Bse
0100 sse
H
140
191 0055 0075
J
020
030 0008 0012
K
432 0130 0170
330
L
1448 1600 0570 0630
M
100
0"
10"
0"
N
102 0020 0040
051
II
6-281
R68560, R68561
Multi-Protocol Communications Controller (MPCC)
PACKAGE DIMENSIONS -
48-PIN DIP
48·PIN CERAMIC DIP
[::::::[]:::::::::u
I
A
DIM
MilLIMETERS
INCHES
MAX MIN MAX
MIN
A
B
C
D
F
I
~FI
~
-L,
j.L '1:'- , -=l~'
6035 6157
1473 1524
330 432
036 053
102 152
254BSC
G
J
020 030
K
254 406
l
1499 1549
M
O·
10·
N
102 152
2.376 2424
0560 0600
0130 0170
0015 0021
0040 0060
0100 esc
0006 0012
0100 0160
0590 0610
O·
10·
0040 0060
48·PIN PLASTIC DIP
DIM
A
[:::::::::::::::::::::u
I
I
B
ce =:]
l
~~~
A
6-282
C
D
F
G
H
J
K
L
M
N
MilLIMETERS
INCHES
MIN
MAX MIN MAX
6063 6195
1372 1422
406 506
036 053
114
140
254 BSC
140 191
020 030
330 432
1448 1600
O·
10·
051
102
2395 2435
0540 0560
0160 0200
0016 0021
0045 0055
0100 BSC
0055 0075
0006 0012
0130 0170
0570 0630
O·
10·
0020 0040
R68802
'1'
Rockwell
R68802
LOCAL NETWORK CONTROLLER (LNET)
DESCRIPTION
FEATURES
The R68802 Local Network Controller (LNET) Implements the
IEEE 802.3 CSMA/CD Access Method local network standard.
This device supports Ethernet' (10BASE5), Cheapernet
(10BASE2) and StarLAN (lBASE5) implementations of this
standard.
•
•
•
•
•
The basIc function of the LNET IS to execute the CSMAlCD
algorithm, perform parallel-to-serial and senal-to-parallel converSions for data streams up to 10 Mbps, and assemble and disassemble the packet format. In addition, the LNET provides an 8-bit
or 16-bit processor Interface, the reqUired DMA Interfaces, and the
proper interface to the Manchester Code Converter (MCG) used
to connect the LNET to an IEEE 802.3 defined Media Attachment
Unit (MAU).
•
•
•
•
•
•
•
•
•
•
•
•
The controller can Interface data terminal eqUipment to local networks with diffenng performance reqUirements. At the high end,
the R68802 meets the IEEE 802.310 Mbps specificallOn and supports the implementation of ISO reference model layers one and
two. For low cost networks, the controller can be run at greatly
reduced data rates and inexpensive system components (drivers,
cables, etc.) may be selected (e.g., Cheapernet and StarLAN).
The LNET controller Implements a protocol known as Carner
Sense Multiple Access with Collision Detection (CSMAlCD), which
allows multiple Data Terminal Equipment to share the same commUnication medium without the need for a central arbiter of
medium utilization.
Meets the IEEE 802.3 specifications for local networks
(e.g., Ethernet', Cheapernet and StarLAN)
Serial data rates as high as 10 Mbps
Compatible with a variety of 8- or 16-bit processors and DMA
controllers
Interfaces to a vanety of manchester code converters
Programmable interframe wait times for smaller topologies and
lower data rates
CSMA/CD algorithm:
-Wait before transmit
-Jam on collision
-Binary exponential backoff
Programmable 2- or 6-byte address recognition
Supports loopback self-test
Extensive network management capabilities
Programmable disable on reception
Programmable collision handling minimizes CPU intervention
32-bit CRC generation and reception
Broadband applications
32-byte FIFO on both transmitter and receiver
TTL compatible 1/0
40-pin DIP
Single 5V power supply
*Ethernet IS a trademark of the Xerox CorporatIon
IEEE 802.3 nodes needing to transmit wait a specific multiple of
transmit clock penods before transmitting data to provide recovery time for other controllers and the cable Itself. If a collision with
another station is detected, the transmission is aborted and ajam
signal transmitted to alert other nodes. Following a jam, the station walts a random amount of time based on a Binary Exponenlial Back-off algonthm before retransmitting. Repeated collisions
result in repeated retnes and an increase In the randomly selected
time Interval to improve trafficking
VCC
R/W
RESET
DO
01
02
03
04
05
06
07
08
09
ORDERING INFORMATION
Part Number
R68802
I
OlD
011
012
013
014
015
~.,.
C
P
CS
= Ceramic
= Plastic
Document No. 68650N07
MAUREQ
MAUAVAIL
ISOLATE
TXCLK
TXOATA
TXEN
SIGQUAL
SENSE
RXCLK
RXOATA
MILOOP
TXREQ
RXREQ
OACK
DONE
IRQ
DTACK
OS
lACK
GNO
R68802 Pin Assignments
Product Description
6-283
Order No. 706
Rev. 3, August 1987
II
::D
iAQ
lACK
en
PARALLELTo.SERIAL
REGISTER
INTERRUPT
INTERFACE
~
CO
CO
TRANSMIT
CRC
GENERATOR
Q
N
I
TRANSMIT
MUX
U
I
TRANSMIT
CONTROL
RiW
f'.
os
CS
~
0>
...
DACK
RxReQ
PAD
GENERATOR
PREAMBLE &
DELIMITER
GENERATOR
JAM
GENERATOR
INTERFRAME
DELAY
COUNTER
BINARY
EXPONENTIAL
SACK-OFF
COUNTER
CSMA/CD
CONTROL
i
TXDATA
TXCLK
r---
I+-
l+-
TXEN
SIGQUAL
SENSE
INTERNAL DATA BUS
C
K
TXREQ
DONE
t
TRANSMIT
LENGTH
COUNTER
BUS
CONTROL
DTACK
06-015
INTERNAL
TRANSMITTER
CLOCK
1
\1
32-BYTE
TRANSMIT
AFO
(TXAFO)
f---
EXTERNAL
DMAC
INTERFACE
~
1\
A
r-
~l
!
\J
1
:J2..BVTE
RECEIVE
CONTROL
RECEIVE
FIFO
(RXFIFO)
/
ADDRESS
RECOGNmON
{
v
RECEIVE
LENGTH
COUNTER
0
f
(")
INTERRUPT
/MODE
STATUS
{
COMMAND
~
f---
MAUREQ
Mii:OOP
iSOLATE
M.WAvAii
++-
V
SERIAL-TO.
PARALLEL
REGISTER
!!.
V
INTERNAL
RECEIVER
CLOCK
l+-
RXCLK
-:...e
Z
CD
0
~
I~
::l
~
RECEIVE
CRC
DELIMITER
RECOGNITION
RXDATA
-
I~
r-
zm
Figure 1. LNET Block Diagram
-t
R68802
Local Network Controller (LNET)
PIN DESCRIPTION
lACK-Interrupt Acknowledge. The active low lACK input indicates that the current bus cycle is an interrupt acknowledge cycle.
When lACK is asserted the LNET places an interrupt vector on
the lower byte (00-07) of the data bus.
Throughout the document, signals are presented using the terms
active and inactive, or asserted and negated, independent of
whether the signal is active in the high-voltage state or low-voltage
state. (The active state of each logic pin is described below.) Active
low signals are denoted by a superscript bar, RiW indicates a write
is active low and a read active high.
DACK-DMA Acknowledge. The DACK low input Indicates that
the data bus has been acquired by the DMAC and that the
requested bus cycle is beginning.
DONE-Done. DONE is a bidirectional active low signal. The
DONE Signal is asserted by the DMAC when the DMA transfer
count is exhausted and there is no more data to be transferred,
or is asserted by the LNETwhen either the last byte of receive data
is transferred or a collision is detected during a transmission or
reception. This line is open drain and shmJld be tied high with a
pull-up resistor.
{
DATA
BUS
ASYNCHRONOUS
BUS
CONTROL
{
R68802
LHET
OMA
CONTROL
INTERRUPT
CONTROL
MANCHESTER
INTERFACE
RESET-Reset. The active low, high impedance RESET input
initializes all LNET functions. RESET must be asserted for at least
10 TXCLKs to initialize the LNET.
f
{
IRQ
lAcK
--~"L-
RXREQ-Receive DMA Request. When receive data becomes
available in the RXFIFO, RXREQ output is asserted and held low
for 8 or 16 (single address burst mode) DMAC cycles (8 or 16
sequential DACK pulses) or until the end of the receive block.
When the last data byte of the receive block is transferred, DONE
is asserted by the LNETwith the last DACK strobe and the negation of RXREQ.
V"
_ _ _ _- - - G N O
Figure 2. LNET Input and Output Signals
DO-D15-Data Lines. The bidirectional data lines transfer data
between the LNET and the MPU, memory or other peripheral
device. 00-015 are used when connected to a 16-bit bus and operating in the word mode. 00-07 are used when operating in the
byte mode. The data bus is tri-stated when CS is inactive. (See
exceptions in DMA mode.)
TXREQ-Transmit DMA Request. When the Transmitter Enable
bit is set In the Command Register, TXREQ output is asserted and
held low for 8 or 16 (single address burst mode) DMAC cycles (8 or
16 sequential DACK pulses) or until the end of the transmit data
block as Signaled by the DMAC's assertion of DONE.
CS-Chip Select. CS low input selects the LNET for
programmed transfers with the host. The LNET is deselected
when the CS input is inactive in non-DMA mode. CS must be
decoded from the address bus and gated with address strobe (AS).
MILOOP-MI Loopback. With an active MILOOP output, the
MCC shunts its LNET data-in path to its LNET data-out path, effectively routing the LNET TXDATA output into the LNET RXDATA
input.
RIW-Read/Write. RNV input controls the direction of data flow
through the bidirectional data bus by indicating that the current
bus cycle is a read (high) or write (low) cycle.
RXDATA-Receive Data. The LNET receives serial data via the
RXDATA input. The RXDATA input is shifted into the receiver on
the positive going edge of RXCLK.
DTACK-Data Transfer Acknowledge. DTACK is an active low
output that signals the completion of the bus cycle. DUring read
or interrupt acknowledge cycles, DTACK is asserted by the LNET
after data has been provided on the data bus; dUring write cycles
it is asserted after data has been accepted at the data bus. A pull
up resistor is required to maintain DTACK high between bus cycles.
This line is an open drain output.
RXCLK-Receive Clock. The free-running Receive Clock input
provides the LNET with receive data timing information.
SENSE-Carrier Sense. The active high SENSE input indicates
the presence of data on the RXDATA serial input line.
OS-Data Strobe. During a write (RiW low), the OS input positive transition latches data from the external data bus lines into
the LNET During a read (RNV high), OS low enables data from
the LNET onto data bus lines.
SIGQUAL-Signal Quality. The assertion of the active high
SIGQUAL input by the MCC indicates an error condition on the
medium. During the transmission mode the LNET interprets this
as a collision.
IRQ-Interrupt Request. The active low IRQ output requests
interrupt service by the MPU. This line is open drain and should
be tied high with a pull-up resistor.
TXEN-Transmit Enable. The active high TXEN output indicates
to the MCC that data is present on the TXDATA output.
6-285
II
Local Network Controller (LNET)
R68802
INITIALIZATION REGISTERS
TXDATA-Transmlt Data. The LNET transmits serial data on the
TXOATA line. The TXOATA output changes on the negative going
edge of TXCLK.
The initialization registers contain command information to configure the LNET for normal operation. The registers are the onebyte Mode Register (MR), the one-byte Interrupt Vector Number
Register (IVNR) and the two- or six-byte Station Address Register
(SAR). These registers must be loaded upon RESET (either
caused by power up or initiated during normal operation) or upon
setting of the RESET bit in the Command Register. Any of these
conditions reset the LNET by clearing the Mode Register, Station
Address Register, Command Registers and Status Registers.
TXCLK-Transmit Clock. The Transmit Clock input is a freerunning clock supplied by the MCC that provides both a system
clock and a means of shifting out serial data bit on the TXOATA
output line.
ISOLATE-Isolate MAU. The active low ISOLATE output is
asserted when the Isolate bit in the Command Register is set to
1. This pin can be used to isolate the MAU from the media. As long
as ISOLATE is low, the MAU is unable to transmit or receive on
the medium.
All initialization registers must be written to by the MPU instruction sequence immediately after a reset in the manner described
below even if no data is changed in a register. The number of bytes
written depends upon the number of bytes in the Station Address
as selected in bit 4 of the Mode Register.
MAUAVAIL-MAU Available. When the active low MAUAVAIL
input is asserted, the transmission algorithm can proceed.
MAUREQ-MAU Request. The active low MAUREQ output is
asserted prior to transmission if MAUAVAIL is not asserted.
After the proper number of write cycles have been completed, the
LNET is initialized and further MPU writes to the LNETwili address
only the Command Register. All MPU reads of the LNET after
initialization is complete will access only Status Register 1 or 2.
Vcc-Power.5V ±5%.
GND-Ground. Ground.
Initialization Procedure for 16·Bit MPU Bus
LNET REGISTERS
Write cycle 1-write the Mode byte on the lower byte of the data
bus 00-07. The upper byte is not used and can contain any data.
The LNET contains three groups of registers accessible from the
MPU bus which initialize the LNET, control and monitor LNET
operation, and transfer data between the LNET and the MPU bus.
These register groups, specific registers within each group, and
the size, access and mode of each register are listed in Table 1.
Write cycle 2-write the Interrupt Vector Number on the lower byte
of the data bus 00-07. The upper byte is not used and can contain any data.
Write cycle 3 or write cycles 3 through 5-write the one- or threeword Station Address (depending on the Station Address Size
loaded into the Mode Register) on the data bus (00-015). The first
word of the Station Address Register will be compared to the first
word in the destination address field of an incoming packet.
All registers, except the Mode Register, may be accessed either
in the word or byte mode, depending on the MPU data bus length
(S-bit or 16-bit) and the Word/Byte mode selected in bit 4 of the
Mode Register during initialization.
Table 1. LNET MPU Bus Accessible Registers
Register Group
Initialization
Registers
Register Name
Data
Buffers
Access
Mode Register (MR)
1
OS
Interrupt Vector Number Register (IVNR)
1
OS
Station Address Register (SAR)
Operating
Registers
Size
(No. Bytes)
2 or6
Command Register (CR)
1
Status Register 1 (SRI)
Status Register 2 (SR2)
1
1
Transmit FIFO Register File (TXFIFO)
32
Receive FIFO Register File (RXFIFO)
32
Note:
1. Upper byte in word mode Ignored.
6-286
= L, CS = L, RIW = L (write one byte')
= L, CS = L, RIW = L (write one byte')
= L, CS = L, RIW = L
OS
(write 1 or 3 sequential words or 2 or 6
sequential bytes)
Mode
MPUWrite
OS
= L, CS = L, RIW = L
MPUWrite
OS
= L, CS = L, Rm = H
MPU Read
= L, OS = L, OACK = L
RXREO = L, OS = L, OACK = L
TXREO
OMAWrite
OMARead
R68802
Local Network Controller (LNET)
Initialization Procedure for 8-Bit MPU Bus
Interrupt Vector Number Register (IVNR)
Write cycle 1-write the Mode byte on the data bus (00-07).
Write cycle 2-write the Interrupt Vector Number of the data bus
(00-07).
Write cycles 3 through 4 or 3 through 8-write the two- or six-byte
Station Address (depending on the Station Address Size loaded
into the Mode Register). The first byte of the Station Address
Register will be compared to the first byte in the destination field
of an incoming packet.
If an interrupt condition occurs (as reported by bits in Status
Register 1 and Status Register 2), IRQ is asserted to request MPU
interrupt service. Upon lACK input assertion, the Interrupt
Vector Number (IVN) from the Interrupt Vector Number Register
(IVNR) is placed on the data bus (00-07). The IVN must be the
second byte initialized during LNET initialization.
Mode Register (MR)
Station Address Register (SAR)
7
6
5
IFWT
7
6
5
4
3
2
o
Station Address
The Mode Register sets conditions during initialization for use
during normal operations. It must be the first byte written during
initialization. All mode bits are active high, i.e., = 1.
MR
7-5
IFWT -Interframe Wait Time
No_ of TXCLKs (Wait Time)
000
001
010
011
100
101
110
111
16
32
48
64
80
96
112
128
The Station Address Register holds the Station Address for the
Receiver Address Recognition cirCUitry. The Station Address bytes
must be written to the LNET following the Interrupt Vector Number
during the initialization sequence. Either two or six bytes must be
written, least significant bytes first, depending on the Station
Address Size loaded into the Mode Register.
OPERATING REGISTERS
The command or status registers are addressed during an MPU
write or read, respectively, after initialization is complete. In word
mode, the Command Register is written during one write cycle.
The Command Register receives the lower byte of the word.
Likewise, while reading the status registers in word mode, Status
Register 1 occupies the lower byte of the word.
MR
4
o
1
BYTE -Data Bus Byte Mode
Select word mode (for use with 16-bit MPU bus).
Select byte mode (for use with 8-bit MPU bus).
MR
3
INTCOL-Interrupt on Collision
o
Assert only DONE on collision.
Assert IRQ on collision.
1
COMMAND REGISTER
Command Register (CR)
MR
~
o
1
The Command Register controls the operation of the LNET. All
command bits are active high (i.e., = 1).
DISRX -Disable Receiver
Enable receiver after each packet reception.
Disable receiver after each addressed packet
reception if CR-6 is not set.
Note: See Table 2.
MR
1
o
1
NOLC -No Length Count
Use length count in packet format.
Do not use length count in packet format.
CR
7
o
1
MR
!!
o
1
SAS -Station Address Size
6-byte station address.
2-byte station address.
RESET -Reset
Enable LNET operation.
Reset LNET.
Note: The RESET bit is automatically cleared to 0 upon
the completion of the reset sequence. This bit is
unaffected by the RESET pin level.
6-287
•
Local Network Controller (LNET)
R68802
STATUS REGISTERS
CR
6
RXEN -Receiver Enable
Disable receiver.
Enable receiver. This bit must be set after each packet is
received to enable reception of the next packet only if bit 2
in the Mode Register is set at initialization. Reception of
the packet clears this bit if CR-5 is not set.
The two interrupt driven status registers report the status of the
LNET receiver and transmitter operations. Status registers can
be read upon interrupt service by the MPU. Status is reported in
either discrete or encoded bits. All discrete (or non-encoded) status bits are active high (i.e. = 1).
Note: This bit is not used if bit MR2 is not set at initialization.
See Table 2.
A change in any of these status bits causes IRQ to be asserted
(except as noted). In the byte mode, both status registers must be
read in consecutive read cycles.
o
CR
5
RXALL -Receive All Packets '
Receive only addressed packets. The address must correspond to the Station Address loaded into the Station
Address Register upon Initialization.
Receive all packets (regardless of address), only if bit 2
in the mode Register is not set at initialization.
o
Status Register 1 (SR1)
7
ODD
o
2
RXSTAT
7 Not Used
SR1
6-4 TXSTAT -Transmitter Status
000
001
010
CR
MILOOP-Manchester Interface Loopback Test
Negate MILOOP to command MI normal operation.
Assert MILOOP to command MI loopback operation.
1
3
4
SR1
CR
4 NOISOL-No Isolate
o Assert ISOLATE to request that the MAU isolate itself
from the medium.
Negate ISOLATE to request that the MAU connect itself
to the medium.
o
5
TXSTAT
Note: See Table 2.
3
6
011
CR
2 Reserved
Bit must be set to zero.
100
101
CR
1 OOONO-Odd Number of Bytes
o Transmit even number of bytes In a block.
1
Transmit odd number of bytes on block.
110
111
Transmitter idle.
Transmit successful.
ColliSion (Assertion of SIGQUAL within the forst 512 bit
times causes DONE, or DONE and IRQ, to be
asserted depending on the state of MR bit 3).
Signal Quality error (SIGQUAL asserted after the first
512 bit times).
Transmit retry count exceeded.
Transmit buffer underflow dUring transmission (indicates
the TXFIFO emptied between the 16th data byte delivered
for transmission and the assertion of DONE).
Transmit In progress (indicates the real time activity of
TXDATA pin. This state does not set the IRQ bit in SR2
nor cause IRQ to be asserted. This bit pattern is not
reset to the transmitter idle pattern upon reading SR1.
MAUAVAIL changed state dUring transmission.
CR
Q
TXCMO -Transmit Command
Disable transmission.
Start transmission. Asserts TXREQ and MAUREQ. Clears
automatically after packet transmission.
o
1
SR1
3
o
1
Table 2.
000 -Odd Number of Receive Bytes
Even number of bytes In the receive packet.
Odd number of bytes in the receive packet.
Receive Operation
Bit
MR2
CR-S
CR-6
Operation
0
0
X
Receive addressed packets continuously
0
1
X
Receive all packets (regardless of
address) continuously
1
0
0
Disable receiver
1
0
1
Receive only one addressed packet
1
1
0
Disable receiver
1
1
1
Receive addressed packets continuously
SR1
2-0 RXSTAT-Receiver Status
000
Reserved.
001
Receive successful.
Minimum packet Size error.
010
011
Receive buffer overflow.
100 Frame terminated on a non-byte boundary error.
101
Frame Check Sequence (FCS) error.
110 Reserved.
111
Reserved.
6-288
Local Network Controller (LNET)
R68802
transmitting buffer empties before the loading buffer is fully
loaded, IRQ IS asserted and the transmitter buffer underflow bit
pattern (101) is set In Status Register 1.
Status Register 2 (SR2)
2
7
SR2
7
o
1
COLCNT
IRQ
IRQ
The time required to load half the transmitter buffer under OMAC
control must be less than the time it takes to serialize out the
transmlttlllg half on TXOATA. From the assertion of TXREQ to
the end of the 16th OMAC bus cycle (byte mode) or the 8th OMAC
bus cycle (word mode), no more than 128 TXCLKs can elapse.
-Interrupt Request
An interrupt condition has not occurred and IRQ has not
been asserted.
An interrupt condition has occurred and IRQ has been
asserted.
RECEIVE DATA BUFFER (RXFIFO)
The Receive data buffer is a 32-byte FIFO register file (RXFIFO)
which can be read only during OMA service. One half of the
RXFIFO IS a receiving buffer for the data from the Serial-to-Parallel
Register; the other half is a reading buffer for the data ready to
be transferred to the MPU bus. As soon as the receiving buffer
is full, these two halves switch roles. lithe receiving buffer is fully
loaded before the reading buffer is empty, IRQ is asserted
and the receive buffer overflow bit pattern (011) is set in Status
Register 1.
Note: This bit is cleared when SR2 is read and there IS no
pending Interrupt condition.
SR2
6
-Not Used
The time It takes to unload the reading buffer under DMAC control must be less than the time it takes to load the receiving buffer
from RXOATA. The loading time is 128 RXCLKs.
SR2
5
-Not Used
SR2
!
o
INPUT/OUTPUT FUNCTIONS
MAUAVAIL-MAU Available
MAU is not available.
MAU is available.
TYPical LN ET interface connections to a 16-bit data bus or an 8-bit
data bus are shown in Figure 4 and Figure 5, respectively.
Note: This bit is not cleared when SR2 IS read.
MPU INTERFACE
SR2
3-0 COLCNT -Collision Count
0000
Zero
1111
Fifteen
Transfer of data between the LNET and the system bus involves
the following signals: Data Bus DO through 015 and control signals consisting of R/W, OTACK, CS, lACK, and OS.
16-8il MPU Interface
Bit 4 in the Mode Register, left at its default value of 0 during initialization, selects the word mode. In the word mode, a read of both
status registers performed with one word read cycle transfers Status Register 1 on 00-07 and Status Register 2 on D8-015. A write
to the 8-bit Command Register is also accomplished in one cycle
on OO-D7.
Note: Reset to zero when the TXCMO bit (CR-O) is set. If
Mode Register bit 3 is negated the changing count
does not generate IRQ Interrupts. IRQ is asserted
when maximum collision count is reached.
TRANSMIT DATA BUFFER (TXFIFO)
a-Bit MPU Interface
The Transmit data buffer is a 32-byte FIFO register file (TXFIFO)
which can be loaded only by OMA service. One half of the TXFIFO
loads data for transmission via the OMAC; the other half holds data
currently being transmitted out serially on TXOATA. When the
transmitting half is empty it becomes the loading half and the
current loading buffer becomes the transmitting half. If the
Bit 4 of the Mode Register, set to 1 during initialization, selects the
byte mode. In the byte mode, reading of the status registers is performed with two consecutive byte read cycles to enable first Status Register 1 and then Status Register 2 onto 00-07. Writing to
the Command Register requires one cycle.
6-289
•
Local Network Controller (LNET)
R68802
Read/Write Operation
MANCHESTER INTERFACE SIGNALS
The R/IN input controls the direction of data flow on the data bus.
CS (Chip Select) enables the LNET for access to the internal
registers and other operations. When CS is asserted the data 1/0
buffer acts as an output driver during a read operation, and as an
input buffer during a write operation.
The abbreviation MCC refers to the Manchester Code Converter
necessary to interface the LNET to an IEEE 802.3 specified Media
Access Unit (MAU).
SENSE (Sense Carrier) Input
If the LNET is selected (CS = low) for a read (RIW = high),
data is placed on the data bus from the status register when DS
is asserted. The LNET asserts Data Transfer Acknowledge
(DTACK) concurrent with the output data.
The MCC asserts SENSE when it has detected a change in Carrier Sense from no carrier present to carrier present. SENSE stays
active as long as carner is present and IS negated when the carner disappears.
If the LNET is selected (CS = low) for a write (RIW = low), DS
strobes data into the selected register and the LNET asserts
DTACK immediately after DS is asserted.
ISOLATE (Isolate Message Request) Output
DMA INTERFACE
The LNET asserts ISOLATE to direct the MCC to send an Isolate
message to the MAU. When ISOLATE is negated, the MCC sends
a Normal message to the MAU unless the LNET requires that the
MAU request message be sent to permit data output.
During receiving or transmitting data from the MPU bus, the LNET
asserts a receive or transmit request (RXREQ or TXREQ) to the
DMAC. A DMA acknowledge (DACK) signal IS asserted In
response to RXREQ or TXREQ when the DMAC is ready to service the request. Both receive request and transmit request share
the same DACK pin; therefore, in the case of DMAC devices with
a DACK for each channel, they must be ORed together externally.
MAUREQ (MAU Request) Output
The LNET asserts MAUREQ when CR bit 0 IS active. MAUREQ
stays active and a MAU request message is sent until the end of
a packet transmission.
Transmit DMA Request
In servicing the TXREQ, the DMAC writes to the TXFIFO a byte
or a word at a time. The TXFIFO input pointer (TIP) is advanced
and data latches on the rising edge of DS.
MAUAVAIL (MAU Available) Input
The MCC asserts MAUAVAIL when an MAU available message
from the MAU IS received. MAUAVAIL IS negated when an MAU
not available message IS received from the MAU.
Receive DMA Request
In servicing the RXREQ, the DMAC reads from the RXFIFO a byte
or word atatime. Data is enabled out on the falling edge of DACK
and the RXFIFO output pointer (ROP) is advanced on the rising
edge of DACK. The data lines are tri-stated following the rising
edge of DACK.
SIGQUAL (Signal Quality) Input
SIGQUAL is asserted by the MCC when a Signal Quality Error
Message is received from the MAU.
DONE
TXEN (Transmission Enable) Output
DONE is a bidirectional signal line to or from the DMAC and indicates one of three conditions:
The LNET starts a transmission by asserting TXEN and outputs
serial data on TXDATA which is Manchester encoded by the MCC.
TXEN IS active until the end of the transmission.
1. Asan inputtothe R68802, DONE tells the LNETthat no more
data bytes will be transmitted.
2. As an output from the R68802, DONE Indicates the last byte
of received data is being loaded onto the data bus.
RXCLK (Receive Clock) Input
RXCLK shifts receive data into the LNET and
10 MHz, or slower.
3. As an output from the R68802, DONE also indicates premature end of transmission or reception resulting from a collision.
Examine SR2-3 to SR2-0 (Collision Count) to determine valid
or invalid data transfer.
IS
free running at
TXCLK (Transmitter Clock) Input
INTERRUPTS
The TXCLK is a free running 10 MHz, or slower, clock used to clock
data Into the MCC and perform operations in the transmitter.
The IRQ output asserts when there IS status information available after the completion of a transmit or receive transaction, or
an error condition exists. The MPU grants the interrupt by asserting an interrupt acknowledge (lACK) signal and reads the interrupt vector when the LN ET asserts data transfer acknowledge
(DTACK). The subsequent negation of lACK and IRQ precede MPU
interrupt processing.
MILOOP (MI Loopback) Output
The MILOOP output signals the MCC that the current data IS a test
frame and it is to be "looped back" to the LNET instead of being
sent to the MAU.
6-290
R68802
Local Network Controller (LNET)
LNET FUNCTIONAL DESCRIPTION
In the absence of serial input data from the network bus, the
SENSE input from the MCC is inactive. The Receive Clock
(RXCLK) is free running and the Receiver front end is idling.
The LNET transmits and receives serial data on an IEEE 802.3
CSMAlCD Access Method defined communications medium and
transfers parallel data to and from a host system under program
or DMA control according to the IEEE 802.3 data link specification.
The assertion of SENSE defines the beginning of a frame. The
rising edge of RXCLK enables SENSE and, concurrently, the first
Preamble bit on RXDATA to the LNET. The falling edge of RXCLK
shifts the first bit of the Preamble into the Delimiter Recognition
logic and SENSE into the SENSE Detection logic. Delimiter
Recognition is deferred for eight RXCLKS after the assertion of
SENSE, to give the MCC unit time to synchronize on the Preamble.
Frame Format
Serial data transfers synchronously between the LNET and the
MCC within the frame structure for data communications using
local area network media access control (MAC) procedures. Each
MAC frame, or packet, consists of eight fields: Preamble, Start
Field Delimiter (SFD), Destination Address, Source Address,
Length Count, Data, Pad and Frame Check Sequence (FSC).
Figure 3 illustrates the frame format.
If sequential zeros are detected during the time the LNET is
searching for the double ones delimiter, the packet's reception is
aborted.
The Preamble consists of seven bytes of alternating 1's and O's,
I.e., 1010 ... 1010.
The Preamble bits are shifted through the Delimiter Recognition
logiC without result. As the last bit of the Delimiter is shifted in, an
internal signal is asserted.
The Start Field Delimiter (SFD) consists of one byte of bit pattern
10101011 immediately following the Preamble pattern which indicates the start of a valid frame.
The data is then routed to the Receive CRC and the Serial-toParallel Register. The Byte Alignment and Odd/Even byte monitor is initialized, and a Byte Counter is started.
The Destination and Source Addresses are either two or six bytes
in length. Addresses may be anyone of the follOWing three types:
Station Address, Logical Group, or Broadcast. Logical Group and
Broadcast Addresses are identified by a 1 in the first bit position
received. The first bit of a Station Address is O.
At the appropriate byte count, the first byte of Destination Address
is converted to parallel data, compared with the first byte of Station Address, and loaded into the RXFIFO.
The Length Count field is two bytes in length and specifies the Data
field length (in an Ethernet application this field is the Type field
and the Length Count field in the Mode Register must be initialized appropriately).
The RXFIFO Input Pointer (RIP) is then advanced by one. The next
byte(s) of destination and source addresses are loaded in the same
manner. As the two length count bytes are sent to the RXFIFO they
are also loaded into the Length Counter. If this field is non-zero
it is decremented on each succeeding byte of the packet.
The Data field can have a variable number of bytes. If the Data
field is less than 46 bytes (in a six-byte address mode), or less than
54 bytes (in a twO-byte address mode), pad bytes are added to the
frame on transmission to bring the overall packet size up to the
minimum size of 72 bytes. The maximum Data field length must
be programmed into the DMAC operating with the LNET.
The remainder of the first 16 bytes of the packet are loaded into
the RXFIFO (unless the Length Counter reaches its terminal count
or the packet terminates).
With 16 bytes buffered, the RXFIFO is half full. RXREQ is now
asserted. The receiving half of the buffer becomes the reading
half, and the first 16 bytes of receive data are unloaded byadvancing the RXFIFO Output Pointer (ROP) as a function of the DMAC's
DACK and OS signals. The first and second bytes of the received
packet are read out of the RXFIFO on 00-07 and 08-015, respectively, in word mode. The first byte out of the RXFIFO is the destination address. Meanwhile the empty, receiVing half of the RXFIFO
continues to fill.
The Frame Check Sequence (FCS) field is four bytes in length.
Frame Reception
The Receiver consists of the following sections: Delimiter Recognition, Receive CRC, Serial-to-Parallel Register, Receive Length
Counter, Address Recognition, and a 32-byte FIFO register file
(RXFIFO). These registers are all driven or loaded by RXCLK or
a derivative.
LS BIT FIRST
PREAMBLE
.
START
FIELD
DELIMITER
(SFD)
10101010
10101011
7
1
BYTES
BYTE
DESTINATION
ADDRESS
SOURCE
ADDRESS
LENGTH
COUNT
20R6
BYTES
20R6
BYTES
2
BYTES
72 BYTES MINIMUM
Figure 3.
MAC Frame Format
6-291
.. ..
DATA
~
PAD
(IF
REQUIRED)
.. ..
VARIABLE NO.
OF BYTES
MSBITFIRST
FRAME
CHECK
SEQUENCE
4
BYTES
•
-
R68802
Local Network Controller (LNET)
As the 32nd byte of received data IS loaded, RXREQ is asserted
again and RIP proceeds to the just emptied reading buffer while
DMA bus cycles unload the new reading buffer.
As the TXFIFO Output Pointer (TOP) advances to the first byte of
the most recently filled half of the buffer, TXREQ is again asserted
to reload the half just emptied.
The RXFIFO continues to load and unload in this mannerthroughout the duration of the packet's Data field.
Upon the assertion of the DONE input by the DMAC (at the time
of the last byte or word transfer), the transmitter finishes serializing the last bytes out, zeros the TXFIFO Input Pointer (TIP) and
serializes the contents of the eRC Register out on TXDATA.
The position of RIP indicates when the load the Length Counter
from the data stream, when to check for a valid address, and when
to assert or negate RXREQ and to flag an overrun of the receive
DMA service.
If SIGQUAL is asserted by the MCC during the first 512 TXCLKs,
the LNET assumes there has been a collision between its own
transmission and that of another node in the network. The
response of the LNET at its MCC interface is to abort the frame
transmission after appending a Jam signal consisting of alternating zeros and ones to it. Internally the LNET enters the Binary
Exponential Backott Algorithm. The Jam signal is sent whenever
the LNET has successfully contended for the medium and then
has been interrupted in its transmission during the collision
window.
The two-byte Length Counter is located either four ortwelve bytes
(depending on the address mode) after Valid Delimiter. The Length
Counter is decremented every eight RXCLKs. When the Length
Counter equals zero, indicating the end of the Data field, RIP is
disabled and RXREQ asserts long enough to unload the
last bytes.
In the case of a normal termination olthe packet, after the last bytes
are unloaded, the LNET asserts DONE concurrently with the last
DACK strobe and negates RXREQ. The CRC Register continues
to calculate over the Pad and Frame Check Sequence fields and
the Byte Alignment Checker continues to run until packet end. The
state of the Odd/Even byte checker is latched at the time of the
Length Counter's terminal count.
DMA TRANSFER MODES
The response of the LNET at its MPU/DMAC Interface to a collision is programmable to one of two modes in the Mode Register
at initialization.
ThiS allows for the LNETto be used With DMACs of differing capabilities. SpeCifically, some DMACs need to be reinitialized by the
MPU if they are to restart a block transfer that has been aborted
by a peripheral's assertion of a DONE and an IRQ. Others are
capable of automatically re-starting a block by themselves if a
DONE is detected during a transfer.
The end of the packet is recognized as follows. The last FCS bit
is latched into the LNET when RXCLK goes high In the normal
manner. Two RXCLKs later the negated value of SENSE is
detected. At the next rising edge of RXCLK, the CRC syndrome
is compared and the result is posted to Status Register 1 and IRQ
is asserted.
Mode One: Assert IRQ On Collision.
Frame Transmission
Assertion of SIGQUAL during the first 512 TXCLKs after transmission begins sets the collison code (010) in the encoded Transmitter
Status field in Status Register 1 and increments the Collision Count
field in Status Register 2 by one. Next, IRQ is asserted, and the
Interrupt Vector Number from the Interrupt Vector Number
Register is output on the data bus when lACK is asserted.
The Transmitter consists of the following: Parallel-to-Serial
Register, Transmit Length Counter, 32-byte Transmitter FIFO
register file (TXFIFO), Transmit CRC Generator, Preamble and
Delimiter Generator, Jam Generator, Interframe Delay Counter,
and the Binary Exponential Back-Off Counter. These sections are
all driven by TXCLK or a derivation.
The MPU processes the interrupt by reading the status registers
to determine the cause of the interrupt and to clear the interrupt.
The MPU then reinitializes the DMAC and gives the transmit command to the LNET to reload the first 16 bytes of the aborted data
packet into the TXFIFO. Meanwhile the LNET IS sending the Jam
signal followed by a delay interval determined by the Binary
Exponential Back-off Counter. At the end of this time interval the
LNET begins to transmit the preamble and delimiter again if the
TXFIFO has been reloaded with the first 16 bytes of the packet.
If the TXFIFO has not been reloaded by the time the Jam signal
and the back-off delay interval are over, the LNETwill wait for data.
Frame transmission commences with a MPU write to Command
Register 1 setting the Enable Transmission bit (CR-O). The LNET
responds by asserting Transmit DMA Request (TXREQ). Under
DMA control, 16 bytes are loaded from the MPU bus into the
TXFIFO by advancing the TXFIFO Input Pointer (TIP) as a function
of DACK and DS. The LNET then negates TXREQ until the first
byte of this data has been serialized out. In word mode thiS corresponds to data loaded into the TXFIFO on data bus DO-D7.
While the first 16 bytes are being loaded into the TXFIFO, the LNET
is monitoring the SENSE input. Upon SENSE negation, the Transmitterwaits 96 TXCLKs (strict IEEE 802.3 or Ethernet application,
otherwise the delay follows whatever is programmed into Mode
Register bits 5-7) and then serializes out the first byte of data on
TXDATA if the TXFIFO IS half full (if it is not half full yet, the LNET
returns to monitoring SENSE). If SENSE is active the LNETwaits
until it is negated and then starts the Interframe Delay Counter.
Mode Two: Assert DONE On Collision.
Upon the assertion of SIGQUAL during the first 512 TXCLKs, the
LNET zeros the TXFIFO Input Pointer (TIP), asserts DONE to the
DMAC concurrently with the next DACK signal, increments the
retry count and remains in the transmit mode (TXREQ asserted,
etc.), the JAM is sent, and the Back-off delay is observed. In the
meantime, 16 bytes of data are loaded into the TXFIFO by the
DMAC. The packet IS then transmitted as before.
At the terminal count of the Interframe Delay Counter, the first
preamble bits are shifted out under TXCLK control and the transmitter begins to monitor the SIGQUAL input. At the same time,
TXREQ is asserted again and another 16-byte data burst IS transferred into the empty half of the TXFIFO.
If the MCC asserts SIGQUAL after the first 512 TXCLKs, IRQ is
asserted and the Transmitter Status field in Status Register 2 is
set to 011
6-292
::D
Q)
CD
CD
o
N
ADDRESS
r--
00-015
~==================~
~
AM
~~~
r---
M
r--- 5~~--~-----------t-r1
~
=-
E
'
r-'
•
~
01.
~ 0'PI
~ III1 i~I ~r
~
IRQ (OMA)
~
<0
~
~
IRQ (lNETI
lACK (OMA)
c.:>
~
m -
"/ d
1;
=
21
~
~I 1;'I ~I
ID
~
~
~
GATED
01:1'1
(h
il
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In
:ill ~I "
U2
O::J:I
0
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UI
"'~I
nl
MEMORY
REOO
UREa
RE01
AiiiEQ
ACKO
ACK1
DMAC
...
_ __
~
~
- )o'ITn
::J:I
DACK
I-
....
DONE
DONE:2
"I
TXCLK
TXOATA
lXEN
SlGQUAL
m
1--
l~~~~~~~~~~~~~~~~O~~~~'I=~!===========~~~~============~m-~Q~1
SYSTEM CLOCK
....a
MAUAVAll
ISOLATE
lACK
l
nl
0
..AUREa
-
~~
~I
~
i~
e~I
~
Ill.
0
BUS
- -
lACK (tNETI
~I
~Bi
OTACK
SENSE
RXDATA
r-RXCLK
~ MllooP
1~1
......
{;'
n
!.
Z
i..
JII;'"
~CK
oo
::J
..-~
Ci'
•
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m
Figure 4.
"TYpical Interface to a 16-Bit Data Bus CPU
-I
:a
en
QC)
§
~
I"
oo:D7
RM
~
AS
DTACK
a·BIT
DATA
BUS
CPU
r :ACK
M{DMA)
Ol
l~
OR
~IIII
I
~I I~I~II~
I~II~I 1511~1~
tll
iiRi(LNET)
~
MAUREQ
iAllK(DMA)
~8
,3s
iAa((LNET)
e1;1
REOO
1TXREO
I.
5Aci
Act(O
""""
MEMORY
AC'"
""""I.
~f
MAUAVAIL
REQj~"X"EO
~~fe
;1
_I
DONE
ISOLATE
U IET
iiIiI
~
.!!!!!!!
~
~
~
~
~~
iiCll
"LOOP
;1
SYSrEM CLOCI<
--....
6"
n
!!.
-...
-...
Z
CD
~
~
I~ I
0
0
:::I
a
i"
-.z..
-
m
Figure 5.
~plcallnterface
to an 8-BIt Data au. CPU
-f
R68802
Local Network Controller (LNET)
~-------n----------~
CS
IN
OS
IN
RM
IN
_T4
DTACK
OUT
015-00
OUT
NOTES: CS AND OS LOW STARTS THE TIMING FOR T2, T4 AND T6.
CS OR OS HIGH STARTS THE TIMING FOR T3, T5 AND T7.
TIMING MEASUREMENTS ARE REFERENCED TO AND FROM A LOW VOLTAGE OF 0.8 VOLTS AND A HIGH VOLTAGE OF 2.0 VOLTS,
UNLESS OTHERWISE NOTED.
Figure 6.
LNET Read Timing
•
6-295
Local Network Controller (LNET)
R68802
T1
CS
IN
\
DS
IN
\
I
J
- -
-
t"
T2
RJW
IN
\
~T4_
"
DTACK
OUT
~
.., /
T3
-TS
I
D1S-DO
IN
NOTES: CS AND DS LOW STARTS THE TIMING FOR T2 AND T4.
CS OR DS HIGH STARTS THE TIMING FOR T3, TS, T8 AND T9.
TIMING MEASUREMENTS ARE REFERENCED TO AND FROM A LOW VOLTAGE OF 0.8 VOLTS AND A HIGH VOLTAGE OF 2.0 VOLTS,
UNLESS OTHERWISE NOTED.
Figure 7.
LNET Write Timing
6-296
Local Network Controller (LNET)
R68802
TXREQ
OUT
DACK
IN
J
\
J
I
_T10-=! _ T 1 1 _
DS
IN
\
-
!---T12_
\
J
J
'T14 ~
-+
D15-DO
IN
T13
..-
'\
/
I
..-T15
I
\-T13_
DONE
(TOLNET)
-- t
T17
DONE
(FROMLNET)
T16_
7
~T18
NOTES: 1. TIMING MEASUREMENTS ARE REFERENCED TO AND FROM A LOW VOLTAGE OF 0.8 VOLTS AND A HIGH VOLTAGE OF 2.0 VOLTS,
UNLESS OTHERWISE NOTED.
2. WORD MODE ONLY.
Figure 8.
DMA Timing: Memory to LNET
•
6-297
Local Network Controller (LNET)
R68802
RXREQ
OUT
DACK' - - - - IN
DS
IN
D15-oo
OUT
DONE
(FROMLNET)
___________________ ~-----n~.~--------
NOTES: 1. TIMING MEASUREMENTS ARE REFERENCED TO AND FROM A LOW VOLTAGE OF 0.8 VOLTS AND A HIGH VOLTAGE OF 2.0 VOLTS,
UNLESS OTHERWISE NOTED.
2. WORD MODE ONLY.
Figure 9. DMA Timing: LNET to Memory
T22
I.
/I
IRQ
OUT
_n
lACK
IN
\
I
l
DS
IN
"
J
~T23+
DTACK
OUT
\
~T25
"-T24
it
~T26
D15-DO
OUT
NOTE: TIMING MEASUREMENTS ARE REFERENCED TO AND FROM A LOW VOLTAGE OF 0.8 VOLTS AND A HIGH VOLTAGE OF 2.0 VOLTS,
UNLESS OTHERWISE NOTED.
Figure 10. Interrupt Timing
6-298
R68802
Local Network Controller (LNET)
.....- - T 2 7 - - - - l . j
TXCLK
TXDATA
TXEN
MAUAVAIL
SIGOUAL
ISOLATE
MAUREO
MILOOP
____~m[---------------
NOTES: TIMING MEASUREMENTS ARE REFERENCED TO AND FROM A LOW VOLTAGE OF 0.8 VOLTS AND A HIGH VOLTAGE OF 2.0 VOLTS,
UNLESS OTHERWISE NOTED.
Figure 11.
Serial Interface Timing: Transmitter
~--T27--~~
•
RXCLK
RXDATA
SENSE
NOTE: TIMING MEASUREMENTS ARE REFERENCED TO AND FROM A LOW VOLTAGE OF 0.8 VOLTS AND A HIGH VOLTAGE OF 2.0 VOLTS,
UNLESS OTHERWISE NOTED.
Figure 12.
Serial Interface Timing: Receiver
6-299
Local Network Controller (LNET)
R68802
SPECIFICATIONS
AC ELECTRICAL CHARACTERISTICS
(Vee
= 5.0Vdc
±5%, vss
= OVdc, TA = Oto70°C)
~p
Max
Unit
Notea
-
ns
1
ns
1
20
-
ns
1
CS or OS Low to DTACK Low
20
40
80
ns
1
T5
CS or OS High to DTACK High
20
40
100
ns
1
T6
CS or OS Low to DATA Valid
0
-
320
ns
1
T7
DATA Float After CS or OS High
0
40
ns
1
T8
DATA Setup to CS or OS High
ns
1
ns
1
Symbol
Parameter
Min
T1
CS or OS Pulse Width
SO
T2
RIW Setup to CS or OS Low
25
T3
RIW Hold After CS or OS High
T4
-
T9
DATA Hold to CS or OS High
30
-
Tl0
OS or DACK Low Pulse Width
80
-
Til
OS or DACK Higl, Pulse Width
210
-
230
240
T12
OS or DACK High to TXREO High
-
-
T13
DATA or DONE Setup to OS or DACK High
65
-
T14
DATA Hold to CS or DACK High
35
-
T15
DONE Low Pulse Width
70
-
T16
DONE Low to TXREO High
-
T17
DACK or OS Low to DONE Low
-
ns
1
ns
1
ns
1
ns
1
ns
1
ns
1
T18
DACK or OS High to DONE High
T19
OS or DACK High to RXREO High
-
T20
OS or DACK Low to DATA Valid
-
T21
DATA Float After OS or DACK High
T22
lACK or OS High to IRO High
-
-
T23
lACK or OS Low to DTACK Low
20
40
80
ns
1
T24
lACK or OS High to DTACK High
20
40
100
ns
1
0
-
320
ns
1
50
ns
1
2000
ns
2
ns
2
ns
2
ns
1
ns
1
ns
1
0
T25
lACK or OS Low to DATA Valid
T26
DATA Float After lACK or OS High
-
T27
TXCLK or RXCLK Period
100
+ 300
3(T27)
ns
1
-
100
ns
1
-
80
ns
1
370
ns
1
70
ns
1
40
ns
1
ns
1
T28
TXCLK or RXCLK Low Time
50
T29
TXCLK or RXCLK High Time
50
-
T30
TXCLK Low to TXDATA or TXEN Valid
-
-
T31
MAUAVAIL or SIGOUAL Setup to TXCLK
100
T32
TXCLK Low to MAUREO, MILOOP, ISOLATE Active
-
T33
RXDATA Hold to RXCLK High
20
T34
RXDATA, SENSE, Setup to RXCLK High
30
T35
SENSE Hold to RXCLK Low
30
-
70
-
-
+ 380
3(T27)
90
-
ns
1
-
ns
1
ns
1
Notes:
1. Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted
2. Measured at 1 5V.
6-300
R68802
Local Network Controller (LNET)
MAXIMUM RATINGS
Symbol
Value
NOTE: This device contains circuitry to protect the inputs against
Supply Voltage
Vee
- 0.3 to + 7.0V
Input Voltage
Y'N
- 0.3 to + 7.0V
Operating Temperatures
TA
Storage Temperature
TSTG
damage due to high static voltages or electric fields; however,
normal precautions should be taken to avoid application of any
voltage higher than maximum-rated voltages to this highimpedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (e.g., either
Vss or Vee).
Characteristics
o to 70·C
-55 to + 150·C
THERMAL CHARACTERISTICS
Characteristics
Symbol
Thermal Resistance
Ceramic
Plastic
Value
Rating
50
68
°C/W
°C/W
6JA
DC ELECTRICAL CHARACTERISTICS
(Vee
= 5.0 Vdc ± 5%, Vss = 0 Vdc, TA = 0 to 70 0 e unless otherwise noted)
Characteristics
Symbol
Min.
Max.
Unit
Input High Voltage
V,H
+2.0
Vee
V
-0.3
+0.8
V
Input Low Voltage
V,L
Input Leakage Current
SIGOUAL, TXCLK, MAUAVAIL, RiW, RESET, CS,
IACK,DS,DACK,RXCLK,SENSE,RXDATA
liN
Input Leakage Current for Three State (Off)
DO-DIS
ITSI
Output High Voltage
RXREO, TXREQ, DTACK,
DO-DIS, MILOOP, MAUREO, ISOLATE
TXEN, TXDATA
VOH
Output Low Voltage
RXREO,TXREO,TXEN,TXDATA,DTACK,DO-DI5
MILOOP, MAUREO, ISOLATE
IRO, DONE
VOL
Power Dissipation
P'NT
Input Capacitance
C,N
-
10
Test Conditions
Y'N = 0 to 5.25V
pA
pA
Y,N = 0.4 to 2.4V
Vee = OV
-
V
V
V
Vee = 4.75 V
ILOAD = - 400 ",A, C LOAD = 130 pF
ILOAD = -400 pA, C LOAD = 32 pF
ILOAD = 0, C LOAD = 30 pF
-
0.5
V
Vee = 4.75V
ILOAD = 3.2 mA
-
0.5
V
ILOAD = 8.8 mA
1.0
W
TA = 25°C
13
pF
Vee = 5.0V
Y'N = OV
f = 1 MHz
TA = 25°C
10
+2.4
+2.4
+2.4
6-301
-
•
R68802
Local Network Controller (LNET)
PACKAGE DIMENSIONS
40-PIN CERAMIC DIP
MILLIMETERS
DIM
A
B
C
o
F
G
H
J
K
L
M
N
MIN
MAX
INCHES
MIN
MAX
5029 5131 19802020
1511 158805950625
254
419 0100 0.165
038 053 00150021
076
14000300055
254BSC
0100BSC
076
178 0030 0070
020
033 00080013
254 419 0100 0165
1460 1537 0575 0.605
0°
10°
0°
10°
051
152 0020 0060
4G-PIN PLASTIC DIP
MILLIMETERS
DIM
A
B
C
o
F
G
H
J
K
6-302
MIN
MAX
INCHES
MIN
MAX
5128 52322040 2060
1372 1422 05400560
355
5080140 0200
036
051 00140020
102
1.5200400060
254BSC
0100BSC
l
1 65
2 16 0065 0085
020
030 0.008 0012
330
432 01300170
1524 sse
a 600 esc
M
N
7°
051
10°
7°
10°
1 02 0020 0.040
SECTION 7
Digital Network Products Evaluation Tools
R8069 Evaluation Board ......................................................... 7-3
R8070 Evaluation Board ......................................................... 7-4
R8071 Evaluation Board ......................................................... 7-5
•
7-1
7-2
R8069EB
'1'
Rockwell
R8069EB
R8069 Evaluation Board
SUMMARY
FEATURES
To aid you in understanding how the R8069 Line Interface
Unit (UU) connects to the physical T-1/CEPT PCM 30
transmission medium, Rockwell offers the R8069 Evaluation Board (R8069EB). The R8069EB exercises all the
modes of operation of the R8069. You can also interface
the Rockwell R8070 T-1 /PCM 30 transceiver to this board
to perform various system tests.
6" x 8" card on stand-offs for easy access to all pins
Requires only a single +5 Vdc power supply
On-board receive/transmit transformer alows direct
connection to T-1/PCM 30 lines
Provides test access to R8069 device
Four LED indicate error status
The R8069EB comes complete with a kit containing one
R8069 UU, two crystals, two transformers, status LEOs,
selection switches, peripherial logic, unipolar and bipolar
input/output banana plugs, and a comprehensive, easy-tofollow user's manual.
•
R8069EB Evaluation Board
Document No. 29300N47
Product Summary
7-3
Order No. 347
January 1989
R8070EB
'1'
Rockwell
R8070EB
R8070 Test/Evaluation Board
SUMMARY
FEATURES
To aid you in understanding the T-1 carrier and the R8070
PCM30 formats, an R8070 Test/Evaluation Board
(R8070EB) has been developed by Rockwell. This useful
board also clarifies the operational differences between
modes, allows R8070 check-out against a known good
device and allows interface to the R8071 ISONIDMI Link
Layer Controller and the R8069 Line Interface Unit with
additional hardware.
8" x 12' card on stand-ofts for easy access to all pins
The R8070 Test/Evaluation Board comes complete with a
kit containing one R8070, peripheral logic, selection
switches, status LEOS that allow the user to view most
functions of the R8070 T-1/CEPT PCM30 Transceiver
within each mode of operation. Also included is a comprehensive, easy-to-follow user's manual.
Plated-through holes for R6500/12 CPU
Uses single +5 Vdc supply at 400 to 650 mA
Zero insertion force quad in-line socket for the
R8070
Plated-through holes interconnected for 68-pin chip
carrier "J" socket
Two working spaces to add user-defined circuitry
R8070EB Evaluation Board
Document No. 29300N39
Product Summary
7-4
Order No. 339
January 1989
R8071EB
'1'
Rockwell
R8071EB
R8071 Evaluation Board
SUMMARY
face Unit, R8070 T1/CEPT PCM Transceiver, and R8071
ISDN/OM I Link Layer Controller), RS-232-C and
peripheral logic, Status LEOs, and a Reset switch. A comprehensive, easy-to-follow user's manual guides you
through a series of tests and procedures to familiarize you
with complete board operation.
To aid you in the design of ISDN Primary Rate (T-1/PCM30) communications systems, Rockwell offers the R8071
Evaluation Board (R8071 EB). This board allows you to increase your understanding of the Physical Layer and the
Link Layer of the ISDN protocol. The R8071 EB provides a
menu-driven, user-friendly interface program accessible
from a terminal or personal computer equipped with an
RS-232-C interface. The software allows for easy system
configuration, acceptance of input data from the keyboard,
and display of transmitted data and data link condition on
the terminal/PC monitor. The transmit and receive data is
automatically formatted and unformatted, respectively, according to ISDN, OMI, T-1, and PCM30 standards with
minimal user effort. The board also allows functional
check-out of the R8071 , and provides test access to the
R8069 and R8070 devices.
FEATURES
10" x 12" multi-layer printed circuit board (PCB) on
stand-offs for easy access to all pins
Allows R8071 to be evaluated in all possible configurations
Provides test access to R8069 and R8070
Uses single +5 Vdc power supply
Accessible via terminal/or personal computer with
the use of RS-232-C interface
On-board coupling transformers allow direct connection to T-1 or PCM30 links fjumper selectable)
The R8071 Evaluation Board comes assembled and includes three communication devices (R8069 Line Inter-
User-friendly menu-driven program
•
R8071 EB Evaluation Board
Document No. 29300N37
Product Summary
7-5
Order No. 337
January 1989
7-6
SECTION 8
Digital Network Products Application Notes
R8069 Interface Transformer Specifications and Connections ............................ 8-3
Which Mode for Data Transmission? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-6
Monitoring and Controlling the Synchronization State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-8
Bipolar Violation!Loss of Carrier (RVLL) Signal Separation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-10
Producing AMI Code from TPOS and TNEG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-11
Zero Suppression Methods (B7, B8ZS and HDB3) .................................... 8-13
Finding the F-Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-16
D4/ESF Conversion Using the R8070 ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-19
Loopback Testing with the R8070 ......................................... . . . . . . .. 8-23
Reporting Error Conditions in the R8070 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Receiver Synchronization in the R8070 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
R8070 Test! Evaluation Board ...................................................
Independent Channel Control for the R8070 .........................................
Idle Code Generation ...........................................................
8-28
8-32
8-42
8-53
8-59
Alarm Handling in the R8070 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
An Off-Line Framer for the R8070 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Signaling Freeze with the R8070 ..................................................
Programming the R8071 ISDN/DMI Link Layer Controller's Buffers .......................
8-63
8-66
8-71
8-78
•
8-1
8-2
R8069/R8069A
Application Note
'1'
R8069/R8069A Interface Transformer
Specifications and Connections
Rockwell
INTRODUCTION
TYPICAL CONNECTIONS
The R8069 Une Interface Unit (LlU) and R8069A LlU interface to a T-1/PCM-30 carrier line through transmit and
receive coupling transformers. This application note
specifies the electrical characteristics of these coupling (or
interface) transformers. In addition, R8069/R8069A connections to typical transformers are shown.
Transformers are available from numerous manufacturers
that meet the required transmit and receive transformer's
specifications.
As an example, this application note uses the following
Pulse Engineering's FALCON series transformers:
Part Number
PE-64943
PE-64934
PE-64954
TRANSFORMER SPECIFICATIONS
The transformers must meet the follOWing specifications:
Transmit Transformer:
Tum Ratio:
Rise/Fall Time:
Serial Resistance:
Primary Inductance:
Isolation Voltage:
Insulation Resistance:
Average Power Rating:
Leakage Inductance:
Name
FALCON 27.1
FALCON 28.0
FALCON 31.1
1CT:2CT
22 ns maximum
0.7 Q maximum
1.0 mH minimum
1500 Vrms
10,000 MQ minimum
500mW
0.30 I4H minimum
0.55 I4H maximum
Receive Transformer:
Tum Ratio:
Rise/Fall Time:
Serial Resistance:
Primary Inductance:
Isolation Voltage:
Insulation Resistance:
Average Power Rating:
Leakage Inductance:
Document No. 29300N40
1 :1
22 ns maximum
0.7 Q maximum
1.0 mH minimum
1SOOVrms
10,000 MQ minimum
SOOmW
0.55 I4H maximum
Application Note
8-3
Order No. 340
Rev. 1, January 1989
•
Application Note
R8069/R8069A Interface Transformer
CASE 1 • Interface to T·1 Lines Using Separately
Packaged Transmit and Receive Transformers
Figure 1 illustrates how to interface the RB069 to T-1 lines
through separately packaged transmit and receive transformers. The transmit transformer is a FALCON 27.1 and
the receive transformer is a FALCON 2B.0.
Tl
TXOUTP
6
1
3
TXOUTN
9
I5
O.l flF:!::+
±10%
·~II~·
2
4
N/C
TOTX
T-l LINES
6
FALCON 27.1
R8069/R8069A
LlU
T2
RXINP
RXINN
20
1
21
t,Rl
10~
.~II~·
5
TORX
T-1 LINES
6
FALCON 28.0
Figure 1. Separate Transformer Connections
8-4
Application Note
R8069/R8069A Interface Transformer
CASE 3 • Interface to CEPT PCM 30 Lines
CASE 2 • Interface to T·1 Lines Using an Integrated
Transmit and Receive Transformer
The interface configurations that are illustrated in Case 1
and Case 2 can be applied to a CEPT PCM 30 line simply by installing a 75 Q or 120 Q resistor for R1 depending
on the application.
Figure 2 illustrates how to interface the R8069 to T-1 lines
through a FALCON 31.1, which contains both the transmit
transformer and the receive transformer in a single package.
For driving a twisted-pair cable to a digital cross connect,
the terminating resistor should be 120 Q. In this case, the
R8069 line equalization should be set to select 120 Q
(ELS3 =1, ELS2 =1, ELS1 =0).
The terminating resistor should be 75 Q and R8069 line
equalization set to 75 Q (ELS3 = 1, ELS2 = 1, ELS1 =1)
for driving a coaxial cable.
T1
TXOUTP 6
1
2
TXOUTN
R8069/R8069A
LlU
RXINP
9
0.11!F
",10%
20
I3
~+
5
~1R1
100
21
7
RXINN
·~II~·
.~II~·
14
13
12
N/C
TOTX
T-1 LINES
10
8
TORX
T-1 LINES
FALCON 31.1
Figure 2. Integrated Transformer Connections
8-5
•
T1/CEPT PCM 30
Application Note
'l'
Which Mode For
Data Transmission?
Rockwell
INTRODUCTION
15 consecutive zeros. The RB070 implements several forms of
zero suppression to accommodate the requirements of each
transmission standard.
The T1 digital transmission system was developed as a means
for increasing cable capacity, originally for voice transmission.
Twenty four multiplexed, PCM encoded voice channels plus
associated signaling can be simultaneously transmitted over a
single twisted-pair cable at 1.544 Mbps.
B7 BIT-7 STUFFING
If the eight data bits in a channel would otherwise be all zeros,
bit 7 is forced to a "1". Do not confuse this term with the method
of adjusting clock timing-no extra bits are "stuffed" in zero
suppression.
The T1 system may, however, also be used for the direct transmission of digital information. When selecting a suitable mode for
data transmission, the following subjects should be considered.
Since a bit which is forced to "1" looks like a valid "1", it is not
possible for the receiver to recover the original data. This technique is therefore not suitable for data transmission. (The error
is insignificant in voice transmission.)
• R8070 Mode
• Zero Suppression
• Signaling
B8ZS BIPOLAR 8-ZERO SUBSTITUTION
• Synchronization
This method uses a special code to represent the occurrence
of eight consecutive zeros. Note that these eight zeros may
include the Terminal Framing (Ft) bits, Signaling Framing (Fs)
bits, or Link bits; they are not restricted to the eight channel-bits
as they are in the B7 method.
R8070 MODE
The R8070 T1/CEPT PCM Transceiver has eleven operating
modes covering the standard data formats, with or without signaling, of both the North American T1 and European CEPT PCM
30 transmission standards. These modes are summarized in
Table 1.
Since the special 8-zero code includes intentional bipolar violations in a predetermined sequence, the receiver can recover the
original data pattern. This technique is therefore suitable for data
transmission.
Each mode is characterized by the number of bits per frame
(193, 197, or 256), the availability of signaling (N, S, E or F) and
the method of zero-suppression (BSZS, B7 or HDB3).
HDB3 HIGH DENSITY BIPOLAR 3-ZERO
This method is similar to B8ZS but allows only three consecutive
zeros before applying zero suppression. This is required by the
European CEPT PCM 30 standard. Intentional bipolar violations
are used to allow recovery of the original data. This technique
is suitable for data transmission.
ZERO SUPPRESSION
To maintain the D.C. line voltage near zero and to facilitate clock
recovery, the transmitted T1 signal must contain no more than
R8070 Operating Mode Selection and Characteristics
Mode
Data Rate
(Mbps)
Mode Select Lines
BitsiFrame
FramesiMultiframe
Yes
Yes
No
No
Signaling
Zero Suppression
M1
M2
M3
M4
68ZS
67
68ZS
67
1
0
1
0
0
0
1
1
1
1
1
1
PCM Format
1935
1935
193N
193N
1.544
193
12
12
4
4
193E
193E
193F
1.544
193
24
24
24
Yes
Yes
Special
68ZS
67
68ZS
1
0
1
1
1
0
1
1
1
0
0
0
0
1
1
1
1975
197N
1.576
197
12
4
Yes
No
Transparent
Transparent
1
1
0
1
0
0
0
0
TIC
256
16
2
Yes
No
HD63
H063
0
0
0
1
0
0
0
0
CEPT
PCM 30
256S
256N
2.048
Notes: 67:
61t 7 IS forced to a 1 (stuffed) on an otherwise all zero channel.
88ZS. Bipolar 8-zero substitution.
Document No. 29300N19
T1 (D4)
Extended
Superframe
Format (ESF)
High Density Bipolar 3-zero maximum.
HD63:
Transparent: No zero suppression or substituMn.
Order No. 319
8-6
September 1986
Application Note
TRANSPARENT
No zero suppression takes place, the zeros are transmitted intact.
The transparent mode is used in the 197 modes which are
intended for nc applications. It may also be invoked at any time,
by connecting RPOS to RNEG, to facilitate testing.
When connecting RPOS to RNEG, do not leave them connected
to TPOS and TNEG as this would short circuit the transmitter
outputs. In a local test of the transmitter and receiver of an RS07O,
it is convenient to connect TNRZ to RPOS and RNEG. If TPOS
and TNEG are from a remote source, they should be OR'd and
connected to RPOS/RNEG to invoke the transparent mode. If
it is desired not to have the receiver operate, connect RPOS to
RNEG to logic O. This avoids RPOS = RNEG = 1 which would
invoke the transparent mode thus disabling the BSZS or HDB3
zero suppression. Under no circumstances should RPOS and
RNEG be left floating.
SIGNALING
In the European CEPT PCM 30 standard, a separate channel
(time slot 16) is allocated for signaling so there is no interference
with the data channels, which may convey data or voice information without restriction.
In the North American T1 standard, the signaling information is
conveyed within the data channel by replacing data bit S with
a signaling bit A (for each channel in frame 6) and a signaling
bit B (for each channel in frame 12). For voice communication
this loss of information is not important, but in data communication it produces unacceptable errors and should be avoided.
In the non-Signaling modes, the A and B signaling bits are not
inserted. At first this appears to be satisfactory for data transmission, but see the notes on synchronization below.
In the signaling modes it is possible to avoid the insertion of the
signaling bits:
SERIAL DATA INTERFACE TO THE
TRANSMITTER - TSER
If TSIGMD = 0, the signaling bits are input via IA and lB.
If TSIGMD = 1, the signaling bits are input via TSER.
If TSIGMD is set to "1" the serial data input is correctly
transmitted because the signaling bits are assumed to be contained within the data stream.
Which Mode For Data Transmission?
PARALLEL DATA INTERFACE TO THE
TRANSMITTER - T1·Ta
In this case, A and B Signaling bits must be supplied via IA
and lB. To preserve correct data transmiSSion, IA and IB may
be tied together and connected to Ta. Thus the signaling bits
take the same value as the data bits they replaced.
SYNCHRONIZATION
The RS070 uses the received Ft and the Fs pattern to establish
and maintain synchronization with the frame and multiframe
structure. Ft is simply an alternating sequence of "O"s and "1 "s
which can usually be distinguished from ·the random pattern of
digitalized voice contained in the channels. However, this simple
pattern is more readily imitated by data Signals, which may be
less random in nature. Thus it may be more difficult to preserve
synchronization when data is transmitted.
Those modes which include signaling usually have more frames
per multiframe and carry a longer, more easily identified framing pattern. This facilitates synchronization in the presence of
data signals.
The longer F bit sequences in the Extended Framing modes
(193E and 193F) provide even greater assurance of correct synchronization. In addition, they include a 6-bit cyclic redundancy
checksum (CRC bits) that allows detection of 9S.4 percent of errorcontaining frames.
SUMMARY
When conSidering a suitable mode for data transmission:
1. Don't use B7 zero suppression-it forces data errors; use
BSZS or HDB3.
2. Avoid "robbed" Signaling bits that overwrite data bit S. For
parallel data input, tie IA to IB to Ta. For serial data input, select
TSIGMD=1.
3. Signaling modes may facilitate synchronization in the
presence of "Ft imitating" data.
4. The Extended Framing modes provide a cyclic redundancy
check for detection of 9S.4% of error-containing frames.
•
8-7
T1/CEPT PCM 30
Application Note
'1'
Rockwell
Monitoring and Controlling
the Synchronization State
INTRODUCTION
Alternatively, by applYing De Morgan's theorem to the logiC
function for M.
This note descnbes the signals that allow the R8070 synchronizer
state to be mOnitored and controlled.
PIN NAME SIGNAL
35
OF
Figure 4-1 on page 4-3 of the R8070 Designer's GUide (Order
No. 313, Rev 1) shows the various states through which the
Master State Controller passes as It gains or loses synchronization Each of the eight states IS represented by a three-bit number
MS3, MS2 and MS1, where MS3 IS the most significant bit.
36
OG
38 RRED
The current synchronization state may be mOnitored and controlled by vanous status outputs and control Inputs Further
Information may be derived by logical combinations of the
available signals See the referenced paragraph In the R8070
Designer's GUide for additiOnal information
M = MS1.MS2.MS3
M
1 FOR LOSS OF MULTI FRAME SYNC.
MS1, MS2, MS3 - MASTER STATE
SEQUENCE CODE (PARA. 5.3.7.1)
ThiS output may be decoded to provide an Indication of the sync
state It IS useful In modes other than 193N and 1935 that do
not have MS1 and MS2 available.
In all modes, RRED (Red Alarm) IS the same as "Inverse MS3"
RRED goes high to Indicate a loss of frame sync (In states Wall,
Init, Search, and Demons), and goes low to Indicate correct frame
sync (In states P1, P2, P3 and "In Sync") The "In Sync" state
indicates that both the frame and multlframe are aligned
(synchronized).
RSYNC also proVides a useful marker pulse occurring at the first
F-bit of each multllrame. ThiS pulse IS only valid If the receiver
IS multllrame aligned (I.e., In the "In Sync" state of the synchronizer sequence).
RMRST - RECEIVER MASTER
RESTART (PARA. 5.3.1.3)
To produce a separate logiC function for Multlframe sync, the
following CirCUit may be used.
ThiS Input may be set to a "1" at any time to force the synchronizer back to the "Walt" state and thereby begin the synchronization process again. The "Wait" state IS held as long as
RMRST IS high
PIN NAME SIGNAL
38 RRED
=
= MS3
= 1 FOR LOSS OF FRAME SYNC.
RSYNC - RECEIVER SYNCHRONIZATION
STATE (PARA. 5.3.2.3)
In 193N and 1935 modes, MS1 and MS2 are available at pin 35
(OF) and Pin 36 (OG), respectively These Signals are not
available In other modes
OF
OG
MS3
F
F
F
35
36
.~~
MS2
MS1D£M
MS2
RSRCH - RECEIVE SEARCH
CONTROL (PARA. 5.3.1.4)
__
If, while In the "Walt" state, RSRCH goes low, the synchrOnizer
remains In the "Walt" state. RSRCH does not, however, force
the synchrOnizer to the "Walt" state, as RMRST does.
F
MS3-------~~--------
The normal use of thiS input IS dunng correct frame alignment
(I.e., when RRED = 0). If RSRCH is set to a "0", bit 5 IS skipped
In the first channel of the first frame of the next multlframe ThiS
bit sliPPing allows elastiC stores to recenter, which IS necessary
II transmit and receive clock frequencies are marginally different.
=
M
MS1.MS2 + MS3
M = 1 FOR LOSS OF MULTIFRAME SYNC.
F = MS3
F = 1 FOR LOSS OF FRAME SYNC.
Document No_ 29300N20
Order No. 320
September 1986
8-8
Application Note
Monitoring and Controlling the Synchronization State
=
010 = 02 1 - SYNCHRONIZATION
LOCK (PARA. 5.2.1.1)
be selected by 010 and 02 for compatibility with 010 or 02 channel banks, or to be in normal numerical sequence according to
the CCITI convention.
When a serial data interface to R8070 is used, RSQ1-RSQ5
(Receive Sequence Code) and TSQ1.:rSQ5 (Transmit Sequence
Code) indicate which channel has been received or is to be
transmitted. These codes equal the five-bit binary value of the
channel number. The order in which the codes are produced can
In addition, if 010=02=1 then the normal CCITT numbering
sequence is used, and, once in synchronization, the receiver is
locked in that state and will not attempt to resynchronize, even
if frame errors occur.
8-9
•
T1/CEPT PCM 30
Application Note
'1'
Rockwell
Bipolar Violation/Loss of
Carrier (RVLL) Signal Separation
INTRODUCTION
The circuit shown in Figure 1 separates these two signals on
this basis.
The signal RVLL is available in all modes and provides a combined indication of "Bipolar Violation" and "Loss of Carrier" for
T1 modes. This note describes a method to separate the two
signals. (For CEPT PCM 30 modes, RVLL indicates only Bipolar
Violation, so no separation is required.)
RSER
RVLL
~ BIPOLAR VIOLATION
~C
BIPOLAR VIOLATION
A bipolar violation of the Alternate Mark Inversion (AMI) code,
where "1 "s are represented alternately as positive and negative
pulses, is an occurrence of a pulse of the wrong polarity. To
indicate a bipolar violation, RVLL goes high coincident with the
emergence of the accused bit at RSER.
RVLL
RSER
LOSS OF CARRIER
.---..,_,2
_ _- - '
n
1 ~I~I--"Tlr----'
1..--'
---~~
r-,2
BP
LOSS OF CARRIER
------------~I~I-----TI~
LC
A loss of carrier means that no pulses are detected of either
polarity; in other words, continuous zeros are received. To
indicate loss of carrier, RVLL goes high coincident with the
emergence of the 31st zero at RSER. RVLL will return to zero
when a "1" is received that is not a bipolar violation.
I'
NOTES: 1. A RECEIVED VALID PULSE CAUSES RVLL TO
GO LOW.
2. RVLL REMAINS HIGH IF THE RECEIVED PULSE
IS A BIPOLAR VIOLATION.
The term "loss of carner" is rather confusing since there is no
carrier in a T1 system. The channel data at 64 kbps is timedivision multiplexed to a higher data rate of 1.544 Mbps but not
modulated, hence there is no carrier.
Figure 1.
The clock is not actually "recovered" from the data, rather, a
local clock is synchronized to the incoming data rate. Hence a
loss of pulses on the line does not stop the Receive Clock,
although the clock may drift out of synchronization. A lack of
data pulses indicates a transmitter or transmission fault and this
is indicated by the "Loss of Carrier" signal.
Bipolar Violation/Loss of Carrier
Separation Circuit
Nominally, RSER and RVLL transition simultaneously but a slight
timing difference could result in a glitch at the outputs of this
circuit. To overcome this glitch, the outputs BP and LC should
be latched on the falling edge of RCLK to avoid the transitions
on the rising edge of RCLK (Figure 2).
SIGNAL SEPARATION
BP
These two signals may be distinguised by examining the logic
value of RSER.
RCLK
1. A bipolar violation can only be caused by a received pulse
(of the wrong polarity). This pulse represents a binary 1, so
RSER will be "1".
LC
2. A loss of carrier implies the reception of consecutive zeros,
so RSER will be "0".
Figure 2.
Document No. 29300N21
8-10
BP and LC Latch Circuit
Order No. 321
September 1986
T1/CEPT PCM 30
Application Note
'1'
Producing AMI Code from
TPOS and TNEG
Rockwell
INTRODUCTION
NRZ-NON-RETURN-TO-ZERO
AMI-ALTERNATE MARK INVERSION
A logic level that is maintained for the complete bit time. In the
T1 system the clock rate is 1.544 Mbps so the bit time is thus
648 ns.
AMI is a transmission code where binary zeros are represented
by zero volts and binary ones are represented alternately as
positive or negative pulses. In the T1 system, the pulses are about
3 volts in amplitude with a pulse shape conforming to the pulse
"mask" described in the CCITT Recommendation G.703. A Line
Interface Unit (LlU) must be used to convert the RB070 TTL
signals to AMI format and provide the required pulse shaping.
RZ-RETURN-TO-ZERO
A logic level that is maintained for part (usually half) of a bit time.
This is used in the AMI code.
TNRZ-TTL LEVEL NON-RETURN-TO-ZERO
AMI code is used for several reasons:
A standard TTL-level, Non-Return-To-Zero, binary output.
1. It's a bipolar code having an equal number of positive and
negative pulses with a resultant D.C. voltage of zero. This A.C.
signal allows the use of transformers to couple the LlU to the
T1 line, thus facilitating the design of protection devices (e.g.,
for lightning protection).
TPOS,TNEG
A pair of R8070 outputs both of which are NRZ, positive voltage,
TTL-level signals. They assist in producing an AMI coded version of the standard TTL binary output from TNRZ. They are not,
themselves, in AMI format.
2. The signal frequency is effectively halved. The maximum
frequency occurs for the transmission of an alternating
sequence of zeros and ones. Intuitively, if alternate ones are
represented by negative pulses, the period between adjacent
positive impulses is twice as long. Hence, the bandwidth
required to transmit data in bipolar AMI format is half that
required for the original unipolar data.
UNIPOLAR TO BIPOLAR AMI CONVERSION
The circuit in Figure 1 shows a typical method of converting from
the paired, unipolar NRZ outputs, TPOS and TNEG, to an RZ
AMI code suitable for transmission over a T1 line.
Data outputs TPOS and TNEG are first gated with the inverse
of TCLK. This selects the second half of each bit-wide data pulse
producing RZ versions, TPOS(RZ) and TNEG(RZ). The second
half is chosen because it is stable; the first half includes the transition of the leading edge.
3. Any noise on the line which is large enough to be mistaken
for a data pulse can be rejected as a bipolar violation if it has
the same polarity as the previous pulse. AMI therefore allows
some error protection to be provided.
TNRZ
TPOS (RZ)
TPOS
TPOS
[~
----;-1'
TNEG -----"'1-7--\
n
JI
n
TNEG
TCLK
n
TPOS (RZ)--1l
n
TNEG (RZ)
TCLK
IL
rL
TNEG (RZ)
AMI LINE
A.
CIRCUIT
B.
WAVEFORMS
Figure 1. Typical AMI Line Interface and Waveforms
Document No. 29300N22
8-11
Order No. 322
September 1986
•
Application Note
Producing AMI Code from TPOS and TNEG
This is not intended to be a detailed, circuit schematic; it describes
only the concept of AMI conversi.on. '
These RZ pulses are applied to a pair of push-pull driver
transistors, producing positive pulses from TPOS(RZ) and
negative pulses from TNEG(RZ) which are coupled to the line
by a pulse transformer.
\.
8-12
T1/CEPT PCM 30
Application Note
'1'
Zero Suppression Methods
(B7, B8ZS and HDB3)
Rockwell
INTRODUCTION
ZERO SUPPRESSION METHODS
This note explains how the B7, B8ZS and HOB3 zero suppression methods are implemented in the R8070 and describes
typical waveforms at the R8070 transmitter outputs TNRZ, TPOS
and TNEG.
B7-BIT-7 STUFFING (ZERO CODE SUPPRESSION)
The incoming channel data to the R8070 transmitter is monitored
for an all zero condition. If all eight bits are zero, bit-7 is forced
to a "1" and the resulting 00000010 pattern is transmitted in
place of 00000000, with the "1" correctly output on TPOS or
TNEG (i.e., not a bipolar violatIOn). The "1" IS also output on
TNRZ. An alternative name for this method IS Zero Code
Suppression.
ALTERNATE MARK INVERSION (AMI) CODE
Figure 1 reviews the basic Alternate Mark Inversion (AMI) code.
Inverse TCLK is gated with TPOS and TNEG to produce the
return-to-zero, alternating bipolar pulse of AMI.
At the receiver, the "stuffed 1" cannot be distinguished from
a normal" 1", so the original data cannot be recovered.
A bipolar violation (BV) is a pulse of the same polarity as that
which precedes it. Figure 1 illustrates an example of a bipolar
violation caused by noise on the transmission line..
Note that zero monitoring is performed on a channel basis and
also excludes the F-bit. It is possible for more than eight consecutive zeros to be transmitted. For example, if only bit 1 of
channel N is "1" and channel N + 1 is all zero, then channel
N + 1 would have have bit 7 forced to "1" and there would be
13 consecutive zeros (bits 2-8 of channel Nand bits 1-6 of channel N + 1). The standard requires that no more than 15 consecutive zeros be transmitted.
The R8070 will decode a BV to a "1" and present it at RSER
with a coincident pulse on RVLL to indicate a violation. The R8070
does not internally suppress bipolar violations; that is left as an
option for the user to implement externally, using the RVLL signal.
However, if the R8070 detects a zero sub§titution pattern of BVs,
then the received "l"s are replaced by "O"s to recover the original
data. In this case RVLL remains low.
Figure 2 shows typical B7 waveforms. Channel 23 contains
arbitrary data "1 "s at bits 6 and 7 which are transmitted normally.
Channel 24 is all zero so bit 7 is forced to a "1" on TNRZ and
output as a valid "1" on TPOSITNEG. The F-bit is transmitted
normally. Channell is all zero and so bit 7 is forced to "1"
Both the North American Tl system and the European CEPT
PCM 30 system require AMI line code. Also, they both require
a minimum "ones density", so the number of consecutive zeros
must be limited using a method of zero suppression. The Tl
system uses either B7 or B8ZS; the CEPT PCM 30 system uses
HOB3.
B8ZS-BIPOLAR 8-ZERO SUBSTITUTION
The data stream to be transmitted, including F-bits, is mOnitored
for any group of eight consecutive zeros. These eight zeros do
TCLK
TNRZ
TPOS . - - - , . - - - ,
I~
~I
I~
I
TNEG
__
______~I. - - - ,I
____~I. - - - ,I~____~I. - - - ,I~________
AMI
I
I
I
I
.. _--
Figure 1.
BV = BIPOLAR VIOLATION
Alternate Mark Inversion (AMI)
Order No. 323
September 1986
Document No. 29300N23
8-13
•
Zero Suppression Methods (B7, B8ZS and HDB3)
Application Note
not have to fall in the same channel, they may overlap the channel boundaries or include a zero valued F-bit. An 8-zero group
(octet) is replaced with a B8ZS code, shown below.
B8ZS Codes:
Code
Code
Two different codes are required to ensure that the BV pulses
from adjacent 4-zero groups are of opposite polarity. Code a is
used if there is an odd number of "1 "s after the last BV; code
b is used If there IS an even number.
1 2 3 4 5 6 7 8 (bit position in octet)
a
b
BV
BV
000+-0-+
000-+0+-
HOB3 coding is similar to B8ZS and produces similar data patterns, partiCUlarly on all-zero channels.
Figure 4 shows typical HOB3 waveforms. The CEPT PCM 30
standard refers to time slots (TS) In the context of the allocated
frame space, rather than channels. The data on TNRZ was
chosen to illustrate various occurrences of the 4-zero pattern.
Where:
o
data "0"
data "1" output on TPOS, to produce a positive AM I
pulse
data "1" output on TNEG, to produce a negative AMI
pulse
bipolar violation
+
BV
Bit 1 of TS1 is a "1" and IS transmitted normally. The 4-zero group
of bits 2-5 of TS1 are replaced With an HOB3 code. Code a is
arbitrarily chosen In this example, as the polarity of the previous
BV is not shown. Bits 6 and 7 of TS1 are transmitted as normal
"1"s.
Code a is used if the preceding "1" pulse was positive. Code
b is used if the preceding "1" pulse was negative.
This ensures that adjacent BVs alternate in polarity to preserve
a O.C. line voltage of zero.
The next 4-zero group consists of bit 8 of TS1 and bits 1-3 of
TS2 and is replaced by an HOB3 code. In this case, code b IS
used because an even number of "1"s were transmitted after
the last BV. Bits 4 and 5 of TS2 are transmitted as normal "1 "s.
The search for another 4-zero group begins at bit 6 (TS2) but
is interrupted by the "1" in bit 8 of TS2; these bits are all transmitted normally.
In both codes, bits 4 and 7 are bipolar violations, bits 5 and 8
are normal "1 "s and bits 1, 2, 3 and 6 are "O"s. These codes
are recognized by the R8070 receiver and the original data is
reconstructed.
.
Figure 3 shows typical B8ZS waveforms. Channel 23 contains
arbitrary data "1"s at bits 6 and 7 which are transmitted normally.
The next eight bits are zero (bit 8 In channel 23 and bits 1-7 in
channel 24) and these eight zeros (not the complete channel
24) are replaced with a BSZS code. In this case, code a is used
because the last pulse was on TPOS.
Bits 1-4 of TS3 form a 4-zero group and are replaced With HOB3
code a because there was an odd number of "1 "s after the last
BV. Bits 5-8 of TS3 form another 4-zero group which is replaced
by HOB3 code b as there were an even number (zero) of "1"s
transmitted after the last BV.
The search for another 8-zero group begins at bit 8 in Channel
24, and is interrupted by a "1'!valued F-bit, which IS transmitted
as normal. The search for eight zeros begins again at bit 1, channel 1. Since all eight bits of channel 1 are zero, these are replaced
by a B8ZS code. In this case, code b is used because the last
pulse was on TNEG.
SUMMARY
• B7 - Bit 7 Stuffing
- Applicable to T1
- Bit 7 is forced in "1" In an all-zero channel
- Applied to channel data on Iy - not F bits
- Forced errors unrecoverable at receiver
- "Stuffed 1" appears on TNRZ
TNRZ is unaffected by B8ZS coding.
HDB3-HIGH DENSITY BIPOLAR 3-ZERO MAXIMUM
The data stream to be transmitted, including F-bits, is monitored
for any group of four consecutive zeros (a maximum of three is
allowed). A 4-zero group is replaced with an HOB3 code, shown
below.
HOB3 Codes
_ ~
2
~
•
(bit position in 4-zero group)
CodeaOOOBV
CodebPOOBV
B8ZS - Bipolar 8-Zero Substitution
- Applicable to T1
- Any 8-zero group replaced With 00011011
- Bipolar violations (BV) allow data recovery
- TNRZ not affected
• HOB3 - High Oensity Bipolar 3-Zero Maximum
- Applicable to CEPT PCM 30
- Any 4-zero group replaced With 0001
- Bipolar violation (BV) allows data recovery
- First bit (P) may be "1" to ensure alternate BV polarity
- TNRZ not affected
Where:
o
= data "0"
BV = data "1" transmitted as a bipolar violation
P = valid "1" pulse (Le., not a violation)
8-14
Zero Suppression Methods (87, B8ZS and HDB3)
Application Note
I·
BIT
CHANNEL 23 ----+t--CHANNEL 24 - I F I·
·1·
2
3
4
6
5
7
CHANNEL 1 -------I-CH 2 -
345678F
2
8
23456781234
TCLK
I I~--------~~
~~-----n~____________~Gl~___________________
TNRZ
TPOS
n~----------~~~------------~~~-------
TNEG
ALL ZERO CHANNEL
ALL ZERO CHANNEL
BIt-7 Stuffing (Zero Code Suppression)
I.·.
---CHANNEL 23-11-'---CHANNEL 24 - I F I··---CHANNEL 1------...1- CH 2 - '
BIT
TCLK
TNRZ
TPOS
TNEG
234567812345678
F12
345678
2
3
4
____~r_l~____________~Gl~__________________
______~rl~__~~~__~rl~________~________
____~rl~______~~____~~
n~____
8 CONSECUTIVE ZEROS
B8ZS CODES:
0
0
8 CONSECUTIVE ZEROS
o
+
0
+
A. FOR PREVIOUS PULSE
POSITIVE
Figure 3.
TIME SLOT
I·
BIT
TCLK
TNRZ
TPOS
1
2
3
4
5
7
8
B. FOR PREVIOUS PULSE
NEGATIVE
TIME SLOT 2
1
2
n
n
n
1
+
Bipolar S-Zero Substitution BSZS
1~1.
6
0
+
000
3
4
5
6
-----I.
7
TIME SLOT 3 - 1
1
8
2
3
4
5
6
7
8
ILJl
n
R.Jl
n
Fl
TNEG
HDB3
CODES
4 ZEROS
o
0
0 BY
A. FOR ODD NO. PULSES
AFTER LAST 4 ZEROS
Figure 4.
4 ZEROS
4 ZEROS
P 0
0 BV
B. FOR EVEN NO. PULSES
AFTER LAST 4 ZEROS
o o
0
High Density Bipolar 3-Zero Maximum HDB3'
8-15
4 ZEROS
BVPOOBV
1
T1/CEPT PCM 30
Application Not.
'1'
Finding the F-Bit
Rockwell
INTRODUCTION
Apply this method, or a variation of it, to the R8070 transmitter
and receiver for both a parallel and serial data interface.
In the North American T1 modes (193 and 197), a framing bit
is transmitted at the start of every frame. The sequence of "O"s
and "1"s transmitted via this bit position provides frame align·
ment (Ft), multiframe alignment and identification of signaling
frames (Fs), and, in the Extended Superframe Format, a data
link and cyclic redundancy check.
TRANSMITTER-PARALLEL DATA INTERFACE
The signal TCHSYNC has the required PRF, but the pulse is too
wide and occurs too early. Depending on the application, this
signal may be used in its present form to load an external F·bit
into the R8070.
The basic framing bits may either be inserted by the user via
TFSIG, or generated automatically by the R8070 by connecting
TFGEN to TFSIG. In either case, a common requirement is a
timing pulse which coincides with the bit interval in which the
F·bit is sampled at the transmitter. At the receiver, an equivalent
pulse coincident with the F·bit output may also be required.
To produce a one·bit wide pulse that covers the sampling instant
of the Fobit, TCHSYNC may be mOdified as shown in the Figure 2
circuit and the Figure 3 waveforms.
The falling·edge of TCHSYNC clocks a "I" into Ul. On the next
falling·edge of TCLK, U2 accepts the "I" from Ul. The next high
level of TCHCLK resets Ul, so that on the subsequent falling·
edge of TCLK U2 accepts a "0" from Ul.
DERIVING TIMING PULSES
Which signals are available from the R8070 depends on the data
interface used; parallel or serial. But the general method of pulse
derivation remains the same, as described below and by the
Figure 1:
The resulting output is a one·bit wide pulse, aligned on a falling
clock edge, that covers the instant of the F·bit sampling.
TRANSMITTER-SERIAL DATA INTERFACE
1. Find an R8070 output signal with a pulse repetition frequency
(PRF) equal to the frame rate (8 kHz). This may involve
decoding several outputs.
TCHCLK and TCHSYNC are not available in the serial mode.
Instead, TS01:r505 may be used. TS01·TS05 is the binary value
of the next channel to be loaded into the R8070. These outputs
change two bit-times before the sampling of bit 1 on TSER, thus
allowing the user to select the data for the next channel to be
sampled. See the Figure 4 circuit and the Figure 3 waveforms.
2. If necessary, delay the leading edge of the pulse to coincide
with the start of the required F·bit time.
3. Stretch or truncate the trailing edge at the end of the required
F·bit time. The resulting pulse may then be further gated,
stretched or realigned with either a rising or falling clock edge.
To indicate the time for F·bit sampling, the TS01:rS05 outputs
are set to 00000 for one bit interval, two bit·times before the F·bit
is sampled. The occurrence of all zeros on TS01:r505 may be
.,
~1'~------------------IFRAME--------------------~~
rL
------~rl~------------~u~--------------
1-1
.J
REQUIRED PULSE
BIT
~~-'----------------------~ll~----------~n
CANDIDATE PULSE
------~r--l~----------~l~l--------------~I L
______~rl~____________~I~I----
__
--------~
rL
DELAY LEADING EDGE
TRUNCATE
TRAILING EDGE
Figure 1. General Method for Deriving Timing Pulses
Document No. 29300N24
Order No. 324
September 1986
8·16
Finding the F-Bit
Application Note
decoded and then shifted by 1'12 bit-times to provide the required
F-bit timing pulse. The attached diagrams show the circuit and
waveforms.
RECEIVER-PARALLEL DATA INTERFACE
RCHSYNC has the required PRF. RWIHBT and RCHCLK transition at the start and end of the required F-bit time interval. These
three signals may be gated to provide the required timing pulse.
See the Figure 5 circuit and the Figure 6 waveforms.
Ul is a 5-input NOR gate that provides a high level when
TSQ1.:rsQ5 are all zero. Because the "all zero" condition could
momentarily occur during TSQ output changes, the Ul output
may contain invalid high levels which do not represent the true
"all zero" condition. To remove these glitches, and also to delay
the pulse to the required point in time, the Ul output is clocked
on the falling-edge of TCLK by two consecutive "O-type"
flip-flops.
RECEIVER-SERIAL DATA INTERFACE
RSQ1-RSQ5 are similar in function to TSQ1.:rsQ5. They are
00000 for exactly one bit-time while the F-bit is output at RSER.
These outputs may be decoded to produce the required F-bit
timing interval. The decoder may contain glitches, but these can
be removed by "O:J'ype" latches which would commonly be used
to clock the F-bit from RSER. See the Figure 7 circuit and the
Figure 5 waveforms.
5V
Ul
U2
U2
QI------fD
TCHSYNC
Q
F-SIT
TSQ1-TSQ5
Ct
Ct
U3
Q
Ct
R
o
Q
ct
TCLK
TCHCLK.-----'
TCLK
Figure 2.
1tansrnitter-Parallel Data Interface
Figure 4.
ltansmitter-Serlal Data Interface
TCLK
TSER
r-}
TCHSYNC ~
TCHCLK
-----.J
U1Q
------------------~~
I'-BIT
__________________
PARALLEL
~IIL-
TSQ5
TSQ4
TSQ3
TSQ2
SERIAL
TSQl
U2D
U2Q
U3Q
I'-BIT
_______________
~r-l~
_____
----------------~~
____________________
Figure 3.
~IIL-
ltansmltter-Parallel and Serial Waveforms
8-17
I'-BIT
Application Note
U1
=~?j
Finding the F-Blt
U2
}-
RSQ1-ASOS ---rsD--F-BlT
Figure 5. Recelver-Parenel Data Interfece
Figure 7. Receiver-Serial Data Interface
RCLK
RSER
RCHCLK
---1
L
RCHSYNC
SERIAL
RWIHBT
f.BIT
__________________________
~r_l~
_____
RSQS
RSQ4
RSQ3
RSQ2
RSQ1
---1
-,
PARALLEL
"\
-,
Figure 6. Recelver-Parellel and Serial Waveforms
8-18
T1/CEPT PCM 30
Application Note
'1'
D4/ESF Conversion Using
the R8010
Rockwell
SYSTEM OVERVIEW
3. F-BIT STRUCTURE
04 is the currently implemented version of T1 in Nonh America,
with 03 and 04 being the most common type of channel bank.
But the new Extended Superframe Format (ESF) is beginning
to replace it. Since the Rockwe" R8070 TlICEPT PCM Transceiver can handle both PCM formats, it is ideally suited to both
types of equipment. This application note examines the
differences in these two formats and suggests a method for
convening between them using the R8070.
The major structural difference between 04 and ESF is in the
definition of the F-bits. The larger multiframe of ESF has 24 F-bits,
one preceding each frame (as in 04). These 24 bits are allocated
to one of three functions:
DIFFERENCES BETWEEN D4 AND ESF
1. 12/24 FRAMES PER MULTIFRAME
The fundamental difference between 04 and ESF is the number
of frames which define a multiframe. 04 has 12 frames; ESF
has 24 frames. This larger multiframe provides more signaling
bits, and, more imponantly, more framing bits (F-bits). It is the
definition of these framing bits that characterizes ESF, providing
new features and improved performance over the earlier 04.
2. ABIABCD SIGNALING
1. A 6-bit Framing Pattern Sequence (FPS) of 001011 which per·
forms the same frame- and multiframe-defining functions as
the Ft and Fs bits of 04.
2. A 6-bit Cyclic Redundancy Checksum (CRC) which provides
a block check on the integrity of the previous multiframe.
3. A 12-bit Data Link Facility which gives a 4 kHz link for alarm
monitoring, signaling, error reporting, etc. The latest Be"core
specification for ESF allocates certain of these link bits for
specific error and alarm purposes.
D4/ESF CONVERSION
Figure 1 illustrates a simplified form of a O4/ESF converter. Looking to the left is a 04 facility, looking to the right, ESF. The
elementary requirements of the converter are:
1. To reformat the F-bits, preserving multiframe alignment.
Robbed-bit signaling in 04 provides two signaling bits (an A·bit
in frame 6, and a B-bit in frame 12) per channel, per multiframe.
Since ESF has 24 frames per multiframe, an additional two
signaling bits can be provided without robbing more bits from
the channel data. These are: a C-bit in frame 18, and a O·bit
in frame 24.
The same number of bits are stolen per channel in ESF as in
04, so the rate of signaling remains the same. However, because
the robbed-bit signaling method uses Simple combinations of
the bits (e.g., A=O, B= 1), rather than a code, to represent on
hook/off hook conditions, the four signaling bits of ESF allow
an increase in the number of signaling combinations.
2. To correctly pass data for each of the 24 channels.
3. To convey signaling information.
4. To generate and check CRC bits.
Most of these functions are carried out automatically by the
R8070. Two R8070s are required; one is configured for the 04
format, the other for ESF.
MULTIFRAME ALIGNMENT
In order to correctly generate the F-bits for each PCM format,
each transmitter must have the same multiframe alignment as
the receiver in the other R8070. When dealing with TXlRX
R8070
R8070
TX
RX
ESF
D4
TX
RX
Figure 1. D4/ESF Conversion Using Two R8070s
Document No. 29300N26
8-19
Order No. 326
December 1986
Application Note
D4/ESF Conversion Using the R8070
(Order No. 313). To avoid spurious RSYNC pulses (while the
receiver is resynchronizing) from affecting the transmitter,
RSYNC may be additionally gated with inverse RRED. If the
receiver loses frame alignment, RRED will go high (inverse
RRED will go low) and TMSYNC will receive no further pulses
until frame alignment is re-established. The transmitter would
therefore maintain Its previous frame and multiframe alignment
during the receiver's resync period.
connections in the same PCM format (e.g., for loopback testing),
alignment is achieved by simply connecting RSYNC to TMSYNC
and TFSYNC. This is also the case with a D4IESF converter,
but with the added complication of the different multiframe
lengths.
Figure 2 compares the multiframe lengths of D4 and ESF. When
the R8070 receiver is correctly synchronized, RSYNC produces
one pulse per multiframe coincident with the F-bit of frame 1
on RSER. The ESF format will result in one pulse every
24 frames; 04 results in one pulse every 12 frames.
ESF to D4
In the return direction from ESF to D4 the opposite is true: the
ESF receiver produces only half the number of expected pulses
at TMSYNC. This is not a problem because TMSYNCfTFSYNC
only need one pulse to set the frame and multiframe alignment.
If no pulses are applied to thase transmitter inputs, the previous
alignment is assumed to continue - the internal bit- and framecounters auto-reset. A direct connection between RSYNC and
TMSYNCfTFSYNC can therefore be used (see Figure 3).
D4 to ESF
Put simply, D4 has twice es many RSYNC pulses as the ESF
transmitter needs on TMSYNC. A means of selecting alternate
RSYNC pulses is required. TSIGSEL from the ESF transmitter
is suitable as a gating signal. TSIGSEL is constantly generated
by the transmitter according to the last received alignment or
synchronizing signal on TMSYNC. TSIGSEL is low for 12 frames
and high for 12 frames (see Figure 2).
To prevent spurious RSYNC pulses (during receiver resynchronlzation) from affecting the D4 transmitter, RSYNC may be
gated with inverse RRED (see 04 to ESF).
Figure 3 shows the gating arrangement. When the transmitter
and reciever are correctly aligned, TSIGSEL will allow alternate
RSYNC pulses to reach TMSYNCfTFSYNC.
THE DATA CONNECTION
If the receiver loses synchronization with Its incoming signal,
RSYNC will no longer have the normal multlframe period. For
the exact operation of RSYNC, see the R8070 Designer's Guide
I~
The interconnection of channel data between the receiver and
the transmitter follows the same pattern as for loopback testing.
Figure 4 shows the serial and parallel data connections.
-I
ESF MULTIFRAME
FRAME
RSYNe
TSIGSEL
Jl
l
IFRAME
RSYNC
rL
L
D4 MULTIFRAME
-I
I . 121 31415 1 1 I I .1 10 111 1121 I 2I 31 4I 51 I I I .1 10 111 11211 I
6
7
6
8
n
11
Figure 2. RSYNC Alignment In D4 and ESF
8-20
7
8
rL
Application Note
D4/ESF Conversion Using the R8070
R8070
R8070
TSIGSEL
RRED
RSYNC 1--11_--1
........._ ....-1
TMSYNC
TFSYNC
~:~:~ ~~---I-------f ~
SJ
ESF
D4
Figure 3. Tran8miHer end Receiver Alignment
R8mo
e>TX
D4
Ramo
0
RSER
0
RCLK
8.
TSER
c>
ESF
RCLK
SERIAL DATA INTERFACE
R8070
D4
R8070
[~J4
/8
7
b. PARALLEL DATA INTERFACE
Figure 4. The Data Connection
8-21
n~[~J
ESF
D4/ESF Conversion Using the R8070
Application Note
Serial Path
the D4 transmitter in the converter correctly passed all the signaling bits. This is because the shorter D4 multiframe does not
permit all four bits to be distinguished; the A and C bits occupy
the same frame relative to the RSYNC pulse, so do the Band
D bits.
The serial path requires D-type flip-flops to meet the setup time
for TSER and provide one bit delay for correct synchronization
between the transmitter and receiver. The serial technique has
the advantage that data is always correctly recovered by the
receiver even if it loses synchronization, although it would, of
course, be subject to failure for a complete data loss. RSER contains the same data as the inputs, RPOS and RNEG. This would
be important if the transmitter must maintain its present alignment during periods of resynchronization.
The easiest solution is to permit only A and B signaling on the
ESF side. A more ambitious solution might attempt to code the
ABCD bits, but this would involve decoding at the final D4
destination in equipment over which there is no control.
Facility Data Link
Parallel Path
As with the enhanced signaling capability, the link channel
afforded by the extra F-bits of ESF is not available in D4.
However, one of the 24 data channels could be assigned for
signaling and link data purposes.
The parallel path is simply a direct connection between R1-R8
and T1-TB. The parallel technique has the advantage of
requiring no external circuits, but its data is subject to correct
frame alignment. R1-R8 is gated to zero when frame alignment
is lost.
HANDLING CRC
CRC is only required on the ESF side and is handled
automatically by the R8070. CRC is often used to monitor the
performance of the PCM link but in this case CRC will not travel
the complete link. However, details such as number of errored
multiframes could be computed by the converter and transmitted
back on the ESF side using the Facility Data Link.
SIGNALING
"Robbed" Bits
Figure 5 compares the different signaling arrangements of D4
and ESF. The basic signaling technique is the same in both
formats; the least significant bit from each channel is "robbed"
in every sixth frame. The robbed bits are replaced with signaling bits denoted A-bits in frame 6, B-bits in frame 12, and (for
ESF) C-bits in frame 18 and D-bits in frame 24.
TRANSMITTER AND RECEIVER CLOCKING
As with any receiver to transmitter connection, care must be
taken to observe setup and hold times (see application note
entitled, "Loopback Testing with the R8070," Order No. 327).
The clock for each receiver would normally be recovered from
or synchronized to the line data rate. The transmitters could take
the same clock as the receiver from which they get data, but
to ensure the specified setup times are met, it is convenient to
make the transmitter's clock the inverse of the receiver's. This
applies to both directions of the format conversion.
In the D4 to ESF direction the position of the C- and D-bits would
be taken by the A- and B-bits, respectively, as there is no other
information to be sent.
The problem arises in the ESF to D4 direction. The capacity of
the signaling channels is the same in both formats. But if ABCD
signaling was transmitted from the ESF side, it could not be correctly extracted by the D4 receiver at the far end, even though
1----------------.
ESF MULTIFRAME
----------------.!-I
,-1
r--~ ""'''ffi..
A
B
Figure 5.
04 and ESF Signaling
8-22
A
B
T1/CEPT PCM 30
Application Note
'1'
Loopback Testing with
the R8070
Rockwell
SYSTEM OVERVIEW
TYPES OF LOOPBACK
Figure 1 shows a typical T1 link or span between two central
offices (COS) which for reference are termed the near-end and
far-end offices. The T1 span consists typically of two twisted·
pair wires; one pair for transmit, one pair for receive. Digital
repeaters are placed at one mile Intervals to maintain the quality
of the PCM signal. A Rockwell R8070 T1ICEPT PCM Transceiver
at each end of the link Implements the transmit and receiver
functions.
1. Loopback is local if the signal Is looped at the near end. This
Is a transmitter·to-recelver loop, shown as Loop 1 In Figure 1.
This type of loopback Is provided internally by the R6070.
2. Loopback is remote If the signal Is looped at the far end. This
Is a receiver·to-transmitter loop, shown as Loop 4 in Figure 1.
This type of loopback is performed by a simple interconnec·
tion externally to the R8070.
Loopback can also be made at the line Interface, shown as
Loop 2 and Loop 3 In Figure 1. This type of loopback Is
independent of the R6070.
LOOPBACK TESTING
Loopback is a form of testing in which the transmit and receive
paths are connected so as to route the signal from the near end
(or far end) back to Itself. Figure 1 shows four possible positions
for the loopback connection. By applying loopback in stsges,
progreaslvely further from either end of the link, a faulty section
can be located. This is termed Failure Sectionalization
(Paragraph 6.6, Section A, Bell Publication 43801).
LOCAL LOOPBACK WITH THE R8070
When TLOOP is high, transmitter data on TPOS and TNEG Is
internally connected to the receiver Inputs in place of RPOS and
RNEG (Figure 2). When TLOOP is low, the transmitter and
receiver signals are Independent.
NEAR·END
CENTRAL OFFICE
FAR-END
CENTRAL OFFICE
TX
AX
AX
TX
R8070
R8070
o
LOOPBACK
Figure 1. Typical T1 Span and Loopback Configurations
Document No. 29300N27
8·23
Order No. 327
December 1986
Application Note
Loopback Testing with the R8070
During loopback, the external TPOS and TNEG pins carry a
pattern of continuous 1s, according to Paragraph 6.6.2, Section A, Bell Publication 43801. This continuous 1s pattern
includes the F-bits and is referred to as "unframed 1s." The
external RPOS and RNEG signals are ignored by the R8070.
TNRZ is unaffected by loopback and carries the normal transmit
data.
Under Joopback conditions, RSER is routed to TSER for
retransmission back to the near end. A pair of Ootype flip-flops
adds a 1-bit delay to this path so that when RSYNC is directly
connected to TMSYNC and TFSYNC, the transmitter's framing
will coincide with the receiver's. Two flip-flops are used to ensure
the setup and hold times are met, both for the Ootype and the
TSER inputs. Notice that each input (O-type 1, Ootype 2, and
TSER) is clocked on the opposite edge from the preceding
output. This would not be possible with only one flip-flop.
While in loopback, the data received on RSER (serial) or R1-R8
(parallel) is identical (apart from throughput delay) to that data
input to the transmitter on TSER (serial) or T1-T8 (parallel). The
combined throughput delay of the looped data is one bit time
less than the sum of the transmitter (8 bit times) and receiver
(14 bit times) throughout delays. This is due to the internal
loop back connection.
As for localloopback, consideration must be given to the clock
sources. The receiver will always clock from the line data rate,
the transmitter may have a separate clOCk or be timed from
receive data as well. During remote loopback, the transmitter
must be locked to the receiver data rate. Figure 5 shows a simple
circuit for switching the source of TClK. The signal EXlOOP
controls the remote loop back function and could be manually
applied at the far end or remotely controlled from the near end.
Clock Switching for Local Loopback
Under normal line operation, the R8070 receiver clock, RClK,
is synchronously recovered from the received data. During loopback, the receiver's clock must be synchronized to the looped
transmitter data, which is clocked by TClK. All R8070 outputs
and inputs are clocked on the rising edge of the clock. So, to
ensure that setup and hold times are met in loopback, the
receiver clock must be offset from the transmitter clock. It is convenient to make RClK equal to inverse TClK during loop back.
The circuit in Figure 3 shows the standard method of clock selection. When TlOOP is high, inverse TClK is connected to the
receiver clock input. When TlOOP is low, RClK from the line
interface becomes the receiver clock.
To meet the setup and hold time at the transmitter inputs, inverse
RClK is applied to TClK.
For clarity, the R8070 is shown in Figure 4 as hardwired for
remote loopback. This connection WOUld, or course, normally
be switchable using a gating arrangement similar to that of
Figure 5.
REMOTE LOOPBACK WITH THE R8070
REMOTE LOOPBACK WITH A
PARALLEL DATA INTERFACE
Figure 4 shows the external connection for remote (far-end) loopback with the R8070. Data from the line is received as normal
on RPOS and RNEG, having been conditioned by the line interface unit (lIU), which also extracts a synchronous clock, RClK,
for the receiver. Serial data is output from the receiver at RSER.
A connection for remote loopback can also be made for a parallel
data interface. RSYNC is connected to TMSYNC and TFSYNC
as before, and R1-R8 is connected to T1-T8. No delay is
required on the data lines. A clock switching circuit similar to
Figure 5 should also be used.
LINE INTERFACE
TX
RCLK
TNRZ
TPOS
TSER
OR
T1-T8
TNEG
RCLK
TO
R8070
GATE
TLOOP
TCLK
RSER
OR
R1-R8
RPOS
RNEG
NON R8070 SIGNAL
RCLK: R8070 SIGNAL
RCLK:
GATE
Figure 2.
Internal local loopback in the R8070
Figure 3.
8-24
Clock Switching for local Loopback
Application Note
Loopback Testing with the R8070
TIMING DIAGRAMS
Figure 7 shows the equivalent CEPT PCM 30 timing for serial
data transfer during remote loopback. This is the same as for
T1 except for the F·bit. The same 1·bit delay is required in the
serial data line so that on the falling edge of the clocked RSYNC
pulse bit 1 of time slot 0 is sampled at TSER.
Figure 6 shows the timing diagrams relating to the circuit of
Figure 5. Data in RSER is delayed by one·half bit time at 01,
and again at 02. The RSYNC pulse is clocked Into TMSYNC
and TFSYNC on the falling edge of RCLK. On the falling edge
of this clocked RSYNC pulse, data is acquired at TSER, and
this is the F·bit position. Note that although the F·bit is present
at this time on RSER, the transmitter does not sample TSER
for the F·bit, this is obtained from the TFSIG input. However,
it is convenient to describe the synchronization based on the
F·blt position because if this is correctly sampled, all the subse·
quent bits will be correctly sampled too.
Figure 8 and Figure 9 describe the remote loopback timing for
a parallel interface for T1 and CEPT PCM 30, respectively. No
delay is required in the data line because data is valid for longer
than a single bH time. Data is sampled by the transmitter on T1-T8
on the rising edge of TCHCLK. Notice in the T1 waveforms that
this edge occurs in different places for channel 1 and channel 2
due to the F·bit location. But data is still correctly sampled.
R8070
~
RPOS
RSER
V
RNEG
RSYNC
TMSYNC
TFSYNC
...
........
0
I
0
01
C
RCLK
0
I
02
Or--
C
RCLK
,./
TPOS
<
TNEG
TSER
TX""""""
Figure 4.
External Remote Loopback in the R8070
TCLK-----------------r--~
EXLOOP -
.....--1
TCLK
TO
R8070
RCLK----I
NON R8070 SIGNAL
RCLK: R8070 SIGNAL
EXLOOP:
Figure 5.
Clock Switching for Remote Loopback
8·25
•
Application Note
Loopback Testing with the R8070
RCLK
X
RSER
01
F
X
X
F
RSYNC
X
X
02, TSER
X
X
X
F
X
~
RCLK
TMSYNC
X
DATA CLOCKED IN AT TSER
Figure 6.
F
~
X
Remote Loopback - Serial Data Timing - T1
RCLK
X
RSER
X
01
2
X
X
02, TSER
RSYNC
X
X
2
X
BIT N, TIME SLOT 0
X
2
X
~
RCLK
TMSYNC
X
DATA CLOCKED IN AT TSER
Figure 7.
1
~
X
Remote Loopback - Serial Data Timing - CEPT
8-26
Application Note
Loopback Testing with the R8070
RCLK
RSER
R1-R8
RSYNC
TMSYNC
TCHCLK
~
X~
__________________C_H_1____________________~)(~___C_H_2____
11
~
----II
I
t
L - -_ _ _
.Jt
L..----------PARALLEL DATA SAMPLED AT T1-T8 _ _ _ _ _ _ _
Figure 8.
Remote Loopback - Parallel Data Timing - T1
RCLK
R1-R8
___~)(~___________________C_H_1____________________-,)(~__C_H_2_ _
RSYNC
~_______________________________________________________
TMSYNC
~____________________________________________________
TCHCLK
I
t'--_____
Figure 9.
I
-It
PARALLEL DATA SAMPLED AT T1-T8 ________
Remote Loopback - Parallel Data Timing - CEPT
8-27
•
T1/CEPT PCM 30
Application Note
'1'
Reporting Error Conditions
in the R8070
Rockwell
T1 04, T1C
If two or more Ft errors occur in any five consecutive Ft bits,
then a frame alarm Is declared, RRED goes high and the receiver
attempts to reframe. The "out of frame alignment" condition
disables FERR which reports no further errors until multiframe
alignment is again achieved.
Fa (S-BIT) ERRORS
In the 1935 and 1975 modes, when the receiver is multiframe
aligned, the S-bits are extracted from the incoming F-bit stream
and compared with the standard multiframe-clefining pattern
(001110). Any error in the last received 5 bits of the pattern
causes SERR to go high. SERR returns low when the last
received 5 bits are correct.
Example 1.
10101011010
Because of the 5-bit window used for S-bit errors, it is not
possible to tell which individual S-bits are in error; except for
the first bit, that caused SERR to go high, and the last bit, which
allowed SERR to go low (5 S-bits later).
1 . . . 1_ _ _ _
A single Ft error causes a single,
bit-wide pulse on FERR.
Example 2.
1010101110101
L
However, the circuit shown in Figure 1 provides an external
check on the S-bits. The latest received S-bit, available on
RSBIT, is compared with the correct pattern, produced by a
divide-by-6 counter on the RSBCLK output. At the start of each
multiframe, the counter is reloaded with 001 by RSYNC. This
provides the required 001110 pattern from the most significant
bit of the counter in synchronization with the multiframe.
Second Ft non-reversal treated as
possible continuation of previous
pattern. No error pulse on FERR.
First Ft error causes a single, bitwide pulse on FERR.
Example 3.
101010111110101
Dlvide-by-6 Counter Sequence
Binary Decimal
000 0
000
010
010
011
100
101
110
1
2
2
3
4
5
6
II
+-- Reloaded with 001
at the start of a
multiframe
+-- Resets to 001
000_." """" U"
error. "2 out of 5" criterion is met,
RRED goes high and FERR is
inhibited.
Second non-reversal is considered
a possible continuation of the
previous pattern. Ther is no error
pulse on FERR.
after
count of 6
111 7
CD 3-bit
Normal range of
counter
Th;ro
' - - - - - - First non-reversal causes a single,
bit-wide pulse on FERR.
® ofRestricted
range
divide-by-6
Note: In Example 1, the alternating pattern after the error is the
reverse of the pattern before the error.
counter
S-Bit Comparator Timing
A single error in the Ft pattern, although not sufficient to cause
an "out of frame" condition, does have some impact on the
framing algorithm. A single Ft error, also known as a slip, causes
the framing algorithm to return to the P1 proving period. This
does not affect the multiframe alignment.
Figure 2 shows the timing associated with the S-bit comparator.
The counter is preloaded with 001 by the RSYNC pulse at the
start of the multiframe. The counter is incremented by each rising
edge of RSBCLK, giving a sequence of 001110 from the most
significant bit. This standard S-bit sequence is compared with
the received S-bit on RSBIT by the exclusive OR gate. The comparator output is high for a frame period if the S-bit for that frame
is in error.
T1, ESF
FRAMING PATTERN SEQUENCE (FPS) ERRORS
In the 193F mode, and when the receiver is multiframe aligned,
the FPS is extracted from the incoming F-bits and compared
with the correct pattern (001011). Any single error in the received
sequence is indicated by FERR high coincident with the errored
F·bit on RSER. The FERR pulse in one bit wide.
Ft ERRORS
In modes 1935, 193N, 1975, and 197N, FERR high indicates
that the current Ft bit at RSER failed to maintain its alternating
pattern (010101).
Document No. 29300N28
8·28
Order No. 328
December 1986
Reporting Error Conditions in the R8070
Application Note
0
0
1
I I I
PARALLEL
INPUTS
LOAD
RSYNC -
RSBCLK -
+ 6
UP
)D-S-BIT
ERROR
-7
COUNTER
COMPARATOR
RSBIT
Figure 1. External S-Sit Comparator
I·
I
FRAME
RSYNC
RSIG
·1
MULTIFRAME
2
3
4
5
6
7
8
9
10
11
12
I
rL
11
n
l
IL
RSBCLK
RSBIT
(+ 6)
Figure 2.
External S-Sit Comparator Timing
8-29
•
Reporting Error Conditions in the R8070
Application Note
CYCLIC REDUNDANCY CHECKSUM (CRC) ERRORS
In the 193F mode, the 6-bit CRC checksum transmitted in the
F-bit stream of multiframe N is compared with the locally
computed checksum from the received data of multiframe N-1,
i.e., the previous multiframe. For the purposes of computing
CRC, the F-blts are set to 1. Any discrepancy between the
computed and received checksum bits is indicated by CKERR
high coincident with the errored CRC bit.
MULTIFRAME (MF)
ERROR
A typical application of ESF requires a signal for an errored
multiframe rather than an errored CRC bit. The circuit of
Figure 3 provides such a signal. The first occurrence of a CRC
error (pulse high on CKERR) clocks a 1 into the Ootype flip-flop
and the
output goes high.
remains high until reset by
RSYNC at the start of the next multiframe. CKERR is gated with
inverse RCLK to avoid latching any glitches. A counter attached
to the output of the flip-flop provides a count of errored
multiframes.
a
CKERR
a
a
Figure 3. Counting Errored Multlframes from CRC Errors
..
14--------------MULTIFRAME
RSYNC
CKERR
MF
ERROR
coo"'" 1
I
RSYNC--------------~
Figure 4 shows the timing associated with this circuit. The dotted
lines indicate that the output (MF Error) may be clocked high
by any of the CKERR pulses.
is reset by RSYNC.
a
~:.I
RCLK~
---------------...,~~I
~~-----------------~
~~
__~n~__~n~__~n~__~n~__~n~__
r---- -:- -- -- -:-- - --l- - - - - T- - - -"'----'L
Figure 4.
Errored Multlframe Timing
8-30
Application Note
Reporting Error Conditions in the R8070
FPS, CRe ERRORS
CEPT PCM 30
In 193E mode, the functions of FPS error and CRC error are
multiplexed onto a single output, ERR. See the above description of these functions. The circuit of Figure 5 may be used to
separate these two signals. The separation is performed on the
basis of RSIGBD. If RSIGBD is high, ERR indicates an FPS error.
If RSIGBD is low, ERR indicates a CRC error.
FRAME ALIGNMENT SIGNAL (FAS) ERRORS
(MODE 256N)
The 7-bit Frame Alignment Signal (0011011) is contained in time
slot 0 of alternate frames. If any of these received bits is in error,
FERR is high for bit 1 of that time slot O.
FAS AND MULTIFRAME ALIGNMENT SIGNAL (MAS)
ERRORS (MODE 256S)
ERR-.--------~~---~
RSIGBD -f--.---------I
FERR
The Multiframe Alignment Signal (0000) is contained in bits 1-4
of time slot 16 of frame O. An error in this received signal is
indicated by FMERR high for bit 1 of time slot 16.
1
~~~",.A~~~T
In addition, the FAS error signal (see mode 256N) is multiplexed
onto this output.
SIGNALS
CKERR
Figure 5.
These two signals may be readily distinguished using the circuit of Figure 6. The separation is performed on the basis of
RTS16. A pulse on FMERR during time slot 0 (RTS16 low)
indicates a FAS error, while a pulse during time slot 16 (RST16
high) indicates a MAS error.
Demultiplexing the 193E Mode ERR Signal
DEMULTIPLEXED
ERROR SIGNALS
FMERR
FMERR
RTS16
FERR
Figure 6.
(MUL TIFRAME)
1
(FRAME)
Demultiplexing the 256S Mode FMERR Signal
8-31
T1/CEPT PCM 30
Application Note
,'1'
Receiver Synchronization
in the R8070
Rockwell
ter and receiver are multiframe aligned, TMAX and RSYNC
are synchronized and would appear to be coincident on an
oscilloscope display. They are not quite coincident
because of the transceiver's throughput delay.
INTRODUCTION-THE NEED FOR
SYNCHRONIZATION
Synchronization is one of the major functions of the PCM
receiver. To enable the correct recovery at the receiver of
each telephone channel and its associated signaling, the
primary rate PCM signal Is given a frame and multlframe
structure. This structure is defined by the transmitter,
which places framing bits or framing patterns at certain
positions within the serial bit stream. The task of the
receiver's synchronizer is to locate these patterns, pro·
duce a set of timing waveforms from them, and report any
errors or deviations from the standard pattern.
These functions appear to be trivially Simple, a false
Impression created, partly, by the simplicity of the standard "data sheet" representation of the bit stream, In
which the known framing pattern Is clearly recognizable.
But the receiver sees only a random stream of 1s and Os
arriving at 1.5 Mbps to 2 Mbps, some of which may be In
error or, worse stili, may be Imitations of the real framing
pattern.
The synchronizer is required to frame quickly and reliably
on the PCM signal, to be tolerant of bit errors, and to provide sufficient information to the system about framing
status, errors and timing.
Figure 1 represents the concept of alignment. The transmitter inserts the appropriate alignment patterns for the
mode (e.g., for T1 an alternating 101010 pattern in the first
bit of alternate frames) into the outgoing PCM Signal,
thereby defining the frame and multiframe structure to
which its telephone channels and signaling conform. The
transmitter also produces a timing signal, TMAX, at the
multiframe rate.
These notes describe:
1. The frame and multlframe structure of each PCM
format.
2. The synchronization process-the framing algorithm.
3. Controlling the synchronizer.
4. Synchronization dependent outputs.
5. The reframe criterion for each RB070 mode.
6. Monitoring the synchronization state.
At the receiver, these alignment patterns are recovered
from the channel data and used to synchronize frame and
multiframe counters, from which all other timing signals
are derived. In particular, the receiver produces a timing
signal, RSYNC, at the multiframe rate. When the transmit-
PCM LINK
RX
FRAMES
TX
FRAMES
INSERTS
ALIGNMENT
PATTERNS
oil(
TMAX
11
11
Figure 1.
RECOVERS
ALIGNMENT
PATTERNS
MULTIFRAME
COINCIDENT TXlRX MF TIMING
•
Il
fl
RSYNC
Multilrame Alignment of Receiver and li'ansmitter
Document No. 29300N29
8-32
Order No. 329
January 1987
Application Note
Receiver Synchronization in the R8070
Table 2.
F·blt Assignment-Extended Superframe
Format
F·blt
ESF
ESF
Assignment
Bit
Signaling
Frame
FPS
Bits
Number
Number
FDL
CRC
0
m
1
193
CBl
2
3
386
m
4
579
0
5
772
m
965
CB2
A·blts
6
1158
7
m
1351
8
0
9
1544
m
10
1737
CB3
11
1930
m
12
2123
1
B·blts
13
2316
m
14
2509
CB4
15
2702
m
16
0
2895
17
3088
m
CBS
C·bits
18
3281
19
3474
m
20
3667
1
m
21
3860
CB6
22
4053
23
4246
m
1
D·bits
24
4439
FPS - Framing Pallern Sequence (...001011 ...)
FDL - 4 Kbps Facility Data Link (message bits m)
CRC - CRC·6 Cyclic Redundancy Check (check bits
CBI-CB6)
THE FRAME AND MULTIFRAME
STRUCTURE
T1 04
Each of 24 telephone channels is sampled at a kHz, with a
resolution of a bits. The a·bit samples from each channel
are transmitted serially, most significant bit (bit 1) first.
The transmission of one sample from each channel pro·
duces a group of 192 bits (24 channels x a bits), called a
frame.
-
In order to identify the frame boundaries, an extra bit,
called a framing bit or F·bit, is appended to the start of the
frame. This makes a total of 193 bits per frame. The fram·
ing bit is sometimes called the 193rd bit, but it always
occurs at the start of the frame, not at the end.
-
The method of "robbed·bit" signaling (where the least sig·
nlficant bit of each channel is replaced by a signaling bit
during every sixth frame) requires that signaling frames be
identifiable. Since every sixth frame contains one of two
signaling bits (A or B), a multlframe (or superframe) con·
sisting of 12 frames is defined. The A·bits are contained in
frame 6; the B·bits in frame 12.
The F·bit position carries two interleaved patterns; the Ft
pattern (101010) and the Fs pattern (001110). These two
patterns occupy alternate F·bit positions and define the
frame and multiframe boundaries, respectively. See
Table 1.
Table 1.
Frame
Numbar
1
2
3
4
5
6
7
8
9
10
11
12
F·bit Assignment-D4 Format
Bit
Number
0
193
386
579
772
965
1156
1351
1544
1737
1930
2123
F·blt
Fs
-
Ft
1
0
-
0
-
1
-
-
-
1
1
0
-
-
-
-
-
-
-
-
-
CEPT PCM 30
Signaling
Bits
A·blts
Each of 30 telephone channels is sampled at a kHz, with a
resolution of a bits. The a·bit samples from each channel
are transmitted serially, most significant bit (bit 1) first. A
frame is defined as 32, a·bit time slots. Each time slot (TS)
contains the a·bit sample from one of the 30 telephone
channels (Table 3). The two spare time slots (0 and 16) con·
tain signaling, alarm, and alignment information.
B·bits
In order to identify the frame boundaries, a Frame Align·
ment Signal (FAS), 0011011, is provided in time slot 0 of
alternate frames. This allows the receiver to delineate the
a bits of each channel, as well as determine which is
channell.
0
1
0
-
1
-
0
-
The ABCD signaling method allocates 4 signaling bits per
channel, transmitted in time slot 16 (TS16). Since there are
30 channels, each requiring 4 signaling bits, and there are
a bits in each time slot 16, then 15 "time slot 16s" are
required to transmit a set of signaling bits for each
channel:
T1 ESF
The Extended Superframe Format (ESF) has the same channel
structure and frame structure as 04, but the superframe (or
multiframe) is extended from 12 to 24 frames (Table 2). The F·
bit position now carries three types of information:
(30 channels x 4 signaling bits
1. Framing Pattern Sequence (FPS) which defines the
frame and multiframe boundaries.
2. Facility Data Link (FDL) which allows data such as error
rates, and alarms to be transmitted over the T1 link.
3. Cyclic Redundancy Check (CRC) which allows the link
error rate to be monitored, and enhances the reliability
of the receiver's framing algorithm.
=
15 TS16s x a bits)
This implies a multiframe grouping of 15 frames which,
together with an additional time slot 16 for alarm and
alignment, leads to the standard multiframe length of 16
frames. The multiframe boundary is defined by a Multi·
frame Alignment Signal (MAS), 0000, situated in bits 1-4 of
time slot 16, frame 0 (the first frame of the multiframe).
8-33
~
I
I
Application Note
Table 3.
Receiver Synchronization in the R8070
CEPT PCM 30 Time Slot and Channel
Numbering
Time
Slot
Channel
Number
Time
Slot
Channel
Number
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
FAS
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
MAS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
RRED HIGH
OUT OF FRAME
ALIGNMENT
Notes: FAS: Frame Alignment Signal, Alarm bits
MAS: Multiframe Alignment Signal, ABeD
signaling, alarm
SYNCHRONIZER OPERATION
RREDLOW
IN FRAME
ALIGNMENT
OVERVIEW
The incoming serial bit stream is first stored in a shift·
register and then examined in a serial·parallel fashion to
locate first, the framing bit or framing pattern, then the
multiframe pattern. When fully multiframe aligned, the
synchronizer produces a set of timing waveforms at the
channel·, frame·, and multiframe·rate. These allow the
extraction of the channel data, its associated signaling
bits, and any transmitted alarms. At the same time, the
synchronizer monitors the bit stream for errors in the
received alignment signals. Single errors are reported in
an appropriate format, and multiple errors which exceed a
certain criterion cause the present alignment to be aban·
doned and the synchronization process to be repeated.
)
Figure 2.
MULTI FRAME
ALIGNED
Synchronization States
SYNCHRONIZER STATES-SUMMARY
The R8070's synchronizer (or framing algorithm) can be
viewed as a state machine having eight major states
(Figure 2). Each state is referenced by a name and a binary
number (Table 4).
Table 4
Synchronizer States
Binary
In principle, the synchronizer begins at the Wait state and
proceeds, in sequence if there are no errors, through each
state as it determines and then verifies first, frame align·
ment, then multiframe alignment; finally reaching the
Sync state, where it is fully multiframe aligned. At this
point, the framing pattern is continuously monitored for
errors.
8-34
Dec
State
MS3
MS2
MS1
0
1
2
3
4
5
6
7
Wait
Init
Search
Demons
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
P1
P2
P3
Sync
Application Note
Receiver Synchronization in the R8070
4. P1 State
THE PROCESS OF SYNCHRONIZATION-STATE
DESCRIPTIONS
In the P1 state, the multi frame boundary Is determined by
examining the multlframe alignment signal as appropriate
to the mode. This alignment Is verified for a period of two
multi frames. The previously established frame alignment
is also rechecked.
O. Wait State
The search for frame alignment begins at the Wait state.
There are four means by which the synchronizer might
reach, or be held at, the Wait state:
1.
2.
3.
4.
5. P2 State
Power up reset, PUP.
User request for reframe, RMRST.
User delay of reframe, RSRCH.
Frame errors, causing auto·reframe.
In the P2 state, a further two multlframes are checked for
correct frame- and multiframe-alignment. In modes 1935
and 1975, both the Fs and Ft pattern are monitored for
errors, thus providing additional security against imitative
data patterns. The error criterion for framing is gradually
relaxed as the synchronizer proceeds through the proving
states.
The first three of these are "holding" conditions. If any of
them Is active, the receiver remains in the Wait state.
When none is active, the receiver proceeds to the second
state, Init.
6. P3 State
The last condition (frame errors) is not invoked by a user
input, but is part of the receiver's Inherent resynchronlza·
tion strategy. In this case, the return to the Wait state is
followed Immediately by an entry into the Inlt state.
A final check on alignment is made over a further period of
two multiframes. Even in the non-signaling (nonmultiframed) modes (193N, 197N, and 256N) the proving
periods still apply, but only the Ft bits (T1) or the FAS
(CEPn is checked.
1. Init State
In the ESF modes, 193E and 193F, the CRC is also checked
during the P3 period. If CRC shows any errors then the
present alignment is abandoned and the synchronizer
returns to the Wait state.
During the Initialization state, a bank of shift registers col·
lects a sample of the incoming serial data-usually about
4 frames, but this is mode·dependent. No checks are
made on the data at this stage and so the synchronizer
proceeds directly to the Search state.
During the proving periods for modes 1935 and 1975 (and
for the Sync state below), a single Ft error, called a slip,
does not cause a complete reframe from the Wait state
(two errors are required to cause this). Instead, the syn·
chronizer returns only as far as the P1 state and performs
the multiframe alignment process again.
2. Search State
This Is where the basic search for frame alignment takes
place. In the T1 modes, this means locating the framing
bit; in the CEPT PCM 30 modes, the framing pattern.
A parallel·serial search technique Is used for a shorter
reframe time. A group of bits, appropriate to the mode, is
examined as a candidate for the framing bit or pattern. A
failure to follow the prescribed pattern rules out that bit
group as a candidate. All possible framing candidates are
evaluated repeatedly until all but one is eliminated. If
more than one candidate persists, one of them is chosen
and further tests on it are made to determine its validity.
Random data can mimic the framing pattern for a short
period; continuous test tones can imitate it indefinitely.
Ultimately, if only one framing candidate remains, it is
declared to represent the true frame alignment, and the
synchronizer moves on to the next state.
7. Sync State
Finally, the Sync state is achieved, indicating full multiframe alignment. The receiver continues to monitor the
alignment patterns and reports any errors.
CONTROLLING SYNCHRONIZATION-THE
SYNCHRONIZER INPUTS
The synchronizer is almost entirely controlled internally,
based upon the selected mode of operation and the
incoming data. The algorithm seeks to maintain full multi·
frame alignment until forced to abandon it when the criterion for loss of frame alignment, as defined In the relevant
cCln standards, is met. When this occurs, an immediate
reframe is automatically implemented.
3. Demons State
The Demons state is only entered in modes 193N and
193F. It is a special part of the algorithm which discards
false framing candidates (demons). This is particularly
valuable in the 193N mode where the Fs pattern is not
examined as no multiframe is assumed to exist.
However, the user does have some external control with
the following inputs:
1.
2.
3.
4.
In all other modes, the Demon state is by-passed and the
P1 state is entered.
8-35
RSRCH, receive search control
RMRST, receive master restart
PUp, power-up reset
01 D and 02, synchronization lock
~
I
I
I
Application Note
Receiver Synchronization in the R8070
010 and 02 can also be used to control the synchronizer.
If 010 and 02 are both high, the "synchronization lock"
mode is entered. The synchronizer aligns in the normal
way but, having achieved multiframe alignment, it remains
in the Sync state, regardless of any framing errors.
1. RSRCH
When RSRCH is low (this signal is active LOW), the syn·
chronizer is prevented from continuing to the lnit state
from the Wait state. Note that RSRCH does not force a
return to the Wait state (compare to RMRST below).
This input may be used to hold off reframe, for example to
allow two receivers to be synchronized.
This feature may be useful if the Signal will temporarily be
removed or contain errors, and subsequently will recover
without affecting the frame alignment.
Another function of RSRCH is to slip a bit within the multi·
frame. If at any time RREO = RSRCH = 0, i.e., RSRCH is
active during frame alignment, then bit 5 of the first time
slot of the next multiframe is skipped.
RMRST will override the application of 010 and 02, forc·
ing the receiver to reframe. If 010 and 02 remain high, the
synchronizer will again lock in the Sync state.
SYNCHRONIZATION DEPENDENT OUTPUTS
2. RMRST
Almost all outputs from the receiver are dependent on the
synchronizer for their timing. Each major function of the
receiver: data and signaling recovery, alarm Indication,
and error reporting, requires knowledge of the location of
the channel, frame or multiframe boundaries.
When RMRST is high the synchronizer is forced to return
to the Wait state. If RMRST is then held high, the receiver
will remain in the Wait state.
This signal may be used to force the receiver to reframe if
an error has been detected. Some errors, such as Fs or
CRC, are reported by the R8070 but do not cause a
reframe. This is left for the user to implement and simply
involves feeding back the SERR or CKERR error signal to
RMRST.
Only two outputs are always available and always valid:
RSER and RVLL. These are related directly to the serial bit
stream and are not dependent on the channel position.
Tables 5 and 6 describe the effect of the synchronization
state on each receiver output for the T1 and PCM 30
modes, respectively.
The signal may also be used to ensure that the receiver
reframes after switching from one source of PCM signal to
another, such as would occur with protection switchingswitching to a spare PCM link if the original falls. When
this happens in a T1 04 link, the new signal may happen to
have the same Ft bit alignment but not the same multi·
frame alignment. The receiver would not automatically
reframe because the Ft bits are correct.
3. PUP
When PUP is held low for at least 16 clock cycles, the
receiver (and transmitter) are completely reset. This is
equivalent to applying a RMRST to the receiver and forces
the synchronizer to the Wait state. When PUP is released,
the synchronizer proceeds to the lnit state and attempts
to frame align on the incoming signal in the usual way.
PUP is normally only applied once, at power up, or to
restart the transceiver after a system failure. It should also
be applied after switching modes unless the user can
guarantee that mode switching will not disturb the receiv·
er's timing.
4. D1D and D2
010 and 02 are normally used in T1 modes with a serial
interface. They are used to select the sequence of the
binary channel numbers provided at RS01-RS05 and
TS01-TS05 to match the 010 or 02 channel banks. These
inputs are not used for the same purpose in CEPT PCM 30
modes, as the channels are always sequentially num·
bered: They should normally be set to 0, O.
8-36
Application Note
Receiver Synchronization in the R8070
Table 5.
Synchronization State Dependent Signals - T1 Modes
Synchronization State
W
I
S
D
P1
P2
P3
H
L
L
L
L
!
1
L
L
..
2
L
L
L
L
!
3
L
3
L
3
L
!
2
L
L
L
L
!
L
L
L
!
L
L
L
!
L
L
L
!
L
L
L
!
L
L
L
!
H
L
H
L
H
L
H
L
L
L
L
L
L
L
!
L
L
!
!
!
!
L
L
!
!
!
!
L
L
!
!
!
!
L
L
!
!
!
!
L
L
!
!
!
!
L
L
!
!
!
!
L
L
!
!
!
H
L
H
L
H
L
H
L
H
L
H
H
L
L
L
L
L
·
L
L
L
L
L
H
L
L
L
H
L
H
H
L
L
L
H
H
L
H
L
H
H
··
··
··
··
··
··
·
L
L
L
!
L
·
!
·
Signal
Name
Sy
··
··
··
··
··
·
··
·
L
··
··
·
·
H
H
H
RSYNC
RMFA
RCHSYNC
RCHCLK
RWIHBT
RSQ1-RSQ5
ERRl
FERR
CKERR
SERR
RRED
RYEL
RSBIT
RSBCLK
RSIG
RSIGBD
RSIGCD
RSIGSQ
Alarms
S·bit, signaling
Rl - RS
Parallel data
MS1
MS2
RREDI
Synchronizer state
Gated Low
Gated High
Invalid, Indeterminate
Valid
RSYNC:
1. Single pulse on the last bit.
2. Single pulse indicates candidate.
3. Single pulse at end of each state, coincident with the F·bit output on RSER.
Notes:
1. ERR is a multiplexed version of FERR and CKERR; its validity is the composite of theirs.
8-37
Errors
Link bits
Key:
=
=
=
=
Clocks
RLINK
RLCLK
Sync state: W = Walt, I = Inlt, S = Search, D = Demons
Pl, P2, P3 = Proving periods, Sy = Sync
Condition: L
H
!
•
Signal Type
Application Note
Receiver Synchronization in the R8070
Table 6.
Synchronization State Dependent Signals - CEPT Modes
Synchronization State
W
I
5
D
H
L
L
L
L
!
1
L
L
-
..
!
2
L
L
L
L
!
L
L
L
L
I
···
L
!
L
!
L
!
L
!
L
L
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
L
L
H
L
L
L
H
L
!
!
!
!
!
!
!
!
!
!
!
!
··
L
L
H
L
!
!
!
!
!
!
!
!
!
!
H
L
L
H
L
L
H
L
L
H
L
L
H
L
Key:
P1
P2
P3
3
L
3
L
3
L
·
·
!
·
·
···
·
··
·
·
H
···
··
··
·
·
··
·
·
··
·
··
··
·
H
··
··
·
·
···
·
!
!
Sy
L
L
Signal
Name
RSYNC1
RMFA
RCHSYNC
RCHCLK
RWIHBT
RSQ1-RSQ5
FERR
FMERR2
RRED
RYEL
RMRED
RMYEL
RIBITS
RNBITS
RXBITS
RTS16
RABCD
RLINK
RLCLK
RLlNK1
Signal Type
Clocks
Errors
Alarms
I, N, X bits
ABCD signaling
Link bits
Sync state: W = Wait, I = Inlt, S = Search, 0 = Demons
P1, P2, P3 = Proving periods, Sy = Sync
= Gated Low
= Gated High
= Invalid, Indeterminate
• = Valid
Condition:
L
H
!
RSYNC:
1. Single pulse on the first bit.
2. Single pulse indicates candidate.
3. Single pulse at start of each state, coincident with the first bit of multiframe output on RSER.
Notes:
1. FMERR reports frame and multi frame alignment errors. The frame error portion of these is valid only In the Sync
state, as FERR.
2. No Demons state in CEPT PCM 30.
8-38
Application Note
Receiver Synchronization in the R8070
REFRAME CRITERION-WHAT THE STANDARDS
SAY
CEPT PCM 30 Modes
256N mode: "4 out of 5" errors in the composite framing
pattern (the 7-bit FAS in TSO of alternate
frames plus bit 2 of TSO of frames not containing the FAS).
The R8070 satisfies the reframe criterion stipulated in Bell
Pub 43801 for n, and in CCITT G.732 for CEPT PCM 30.
Bell Pub 43801
256S mode: as for 256N but if the Multiframe Alignment
Signal is in error then the reframe criterion is
reduced to "3 out of 5" errors in the composite framing pattern.
2.2 Out·of Frame Detection
2.2.1 A reframe procedure must start when the frac·
tion of the framing bits in error is in the range 2
out of 5 to 2 out of 4.
Multiframe Error Criterion -
CCITT G.732
CEPT PCM 30
In addition to the reframe criterion, CEPT PCM 30 also has
a multiframe criterion. If this is met, the synchronizer
returns to the P1 state to repeat the multiframe alignment
process. The "Loss of Multiframe Alignment" bit (bit 6 of
time slot 16, frame 0) is automatically set to 1 in the transmitter's output. The frame alignment is not affected.
3. Loss and Recovery of Frame Alignment
Frame alignment will be assumed to have been lost
when three or four consecutive frame alignment signals have been received with an error. Frame alignment will be assumed to have been recovered when
the following sequence is detected:
Multiframe alignment criterion:
for the first time, the presence of the correct
frame alignment signal;
256S mode: Two consecutive errors in the Multiframe
Alignment Signal.
the absence of the frame alignment signal in the
following frame detected by verifying that bit 2 in
channel time-slot 0 is a 1;
MONITORING THE SYNCHRONIZER STATE
Figure 2 and Table 4 show the 8 states of the synchronizer.
Each state has a three-bit binary number; MS1, MS2, and
MS3, where MS3 is the most significant bit. The Red
Alarm output, RRED, is the inverse of MS3.
for the second time, the presence of the correct
frame alignment signal in the next frame.
In Modes 1935 and 193N, the Master State numbers; MS1,
MS2, and MS3 (RRED) are readily available on outputs OF,
OG, and RRED. In other modes, monitoring the synchronizer involves decoding its various state-dependent signals. In this case, it may not be possible to determine the
exact state; all that is normally required is whether the
receiver is fully frame- and multiframe-aligned.
Note- To avoid the possibility of a state in which no
frame alignment can be achieved due to the presence of an imitative frame alignment signal the following procedure may be used:
When a valid frame alignment signal is detected in
frame n, a check should be made to ensure that a
frame alignment signal does not exist in frame
n + 1, and also that a frame alignment signal exists
in frame n + 2. Failure to meet one or both 01 these
requirements should cause a new search to be initiated in frame n + 2.
The following notes suggest how this basic framing information can be obtained in each mode.
REFRAME CRITERION IN THE R8070
The relrame criterion implemented in the R8070 is
described below. When the criterion is met, the synchronizer is forced to the Wait state to repeat the framing process.
I
~
T1 Modes
All modes: "2 out of 5" errors in the framing bit (Ft for T1
D4, FPS for n ESF).
8-39
Application Note
Receiver Synchronization in the R8070
T1 MODES
1935 and 193N Modes
P2, P3
All three Master State numbers are available and can be
read directly from the R8070 or decoded to il)dicate a specific state. For example, the circuit of Figure 3 decodes
the inverse of the Sync state to give an alarm for "loss of
multiframe alignment".
D
AND
Q I - - - SYNC
STATES
RLCLK
C
1975 and 197N Modes
In Figure 4, RSBCLK activity is used to indicate the Sync
state and hence produce a "loss of multiframe alignment"
alarm.
FERR
RRED -
___
Figure 5.
---r£>o
L
RRED
P2, P3, and Sync States
Additionally, in Figure 5 the RLCLK activity in P2, P3 and
Sync states produces more information on the intervening
states between frame alignment and multiframe alignment.
MS1=cYMS2
M
F
193E Mode
If RSIG replaces RSBCLK in Figure 4, the circuit produces
a similar indication of the Sync state. RSBCLK is not available in 193E mode. The circuit of Figure 5 may also be
used.
=
LOSS OF MULTI FRAME ALIGNMENT
= MS1.MS2.MS3
F = LOSS OF FRAME ALIGNMENT
= RRED
M
NOTE: MS3 = RRED
193F Mode
Figure 3_
If RMFA replaces RSBCLK in Figure 4, the Sync state is
indicated. RSBCLI< is not available In 193F. The circuit of
Figure 5 may also be used.
Decoding MS1, MS2, MS3
CEPT PCM 30 MODES
256N Mode
D
RSBCLK
Q
There is no convenient signal in 256N mode which is only
active in the Sync state. Since there is no multiframe
structure in ,256N there may be no need to know when the
Sync state has been reached, although this is useful for
testing.
SYNC
STATE
The circuit of Figure 6 uses the behavior of RSYNC during
framing to determjne the start of the P1, P2, P3, and Sync
states. RSYNC produces a pulse at the start of each of
these states. These pulses are counted after the falling
edge of RRED.
C
FERR
2565 Mode
RRED
This mode already has an indicator of multiframe alignment, RMRED, the multiframe equivalent of RRED. However, some of the circuits described above could be used
to provide further detail of the synchronization state.
Figure 4_
Sync State from RSBCLK
8-40
Application Note
Receiver Synchronization in the R8070
B
A
I-"'----ID
Q
1--'----1 D
D
C
QI-...L..---ID
RSYNC
C
R
..........,..---'
RRED ______
~
____________
~
SHIFT
REGISTER
___________ L_ _ _ _ _ _ _ _ _ _
~
o
A
P1
B
P2
C
P3
r--
D
Figure 6.
SYNC STATE--.
Counting RSYNC Pulses to Find Sync State
8-41
•
T1/CEPT PCM 30
Application Note
'1'
Rockwell
Independent Channel Control for the
R8070
DERIVING THE CHANNEL CONTROL SIGNAL
SYSTEM OVERVIEW
The method used to derive the channel control signal
depends on the form in which the information is initially
represented. This form may range from the hardware
extreme of one line (or wire) per channel, where the logic
level indicates idle code required, to the software extreme
of coded messages indicating idle channel numbers.
Between these extremes lies a "bit per channel"
representation in memory of channels requiring idle code.
It is this form which is assumed for this application note. If
the signal is already in a hardware form then it can easily
be converted to an appropriate control signal. If the
information is in high level software form then it can be
translated to the bit-per-channel form.
The operation of a PCM link requires that functions such as
idle code and digital milliwatt test signals are selectable on
a channel-by-channel basis. On the R8070 this is achieved
by switching the relevant control signal on and off at the
appropriate channel boundaries. This application note
examines various methods for deriving such control
signals.
CHANNEL CONTROL IN THE R8070
Figure 1 illustrates the principle of channel control in the
R8070 T1/CEPT PCM Transceiver. The figure takes TIDLE,
the control for transmission of idle code, as an example;
RIDLE and RMW work in a similar fashion. The T1 format of
24 channels per frame is shown, but CEPT PCM 30
operation is identical except for the channel numbers.
CHECKING THE TIMING CONSTRAINTS
Could the channel control signal be derived entirely by
microprocessor means? This may depend on the type of
microprocessor and the other tasks it must simultaneously
perform. As a quick check, look at the time scale of a PCM
signal:
The schematic at the top of Figure 1 represents the
concept of idle code control. Data on either TSER or T1-T8
normally passes through the transmitter (with an 8-bit
throughput delay) and, after formatting for the appropriate
PCM standard, emerges at TNRZ and at the AMI pair,
TPOS and TNEG. When TIDLE is low, the input data is
transmitted normally. When TIDLE is high, the data is
replaced with idle code.
T1
Clock rate
Clock period
Channel period
Frame period
Channel-by-channel control of idle code insertion is
affected by switching the TIDLE signal on and off at the
boundaries of the required channels. TIDLE is sampled at
the same time as bit 8 of a given channel at TSER for
implementation in the next channel. This is shown in the
top two traces of Figure 1. For example, if TIDLE is high for
channels 3, 7, 8, and 19, then TNRZ replaces the normal
data for these channels with idle code.
CEPTPCM 30
Clock rate
Clock period
Channel period
Frame period
The detailed timing requirements for TIDLE are shown in
the lower traces of Figure 1. An expansion of the time scale
at the boundary of channels 2 and 3 shows the point of
sampling of TIDLE. TCHCLK may be used to gate the
control signal for TIDLE to ensure its stability at sampling.
Document No. 29300N31
1.544 MHz
648ns
5.211-s
2511-s
Application Note
8-42
2.048 MHz
488ns
3.911-s
12511-s
Order No. 331
October 1987
R8070
Independent Channel Control for the R8070
R8070
T1-T8
OR
TSER
TNRZ
TIDLE
TNEG
TPOS
ICH
FRAME
7
3
8
l. . J~:~:~~:~ ~ .: :.! :
TNRZ -L-.............r.:[.::,::![::I.,!:
-1-'L-E..... oD
....
TIDLE
CHANNEL NO.
A
I--'--~""'--..LI:""'::::::I.,J
1
-...1-....1........1--'--"-
E
....
D........--I..-...I.-...I-....I........
r-l~
7
24
19
__________________~rl~________
8
19
TCHCLK
5
6
7
2
8
3
4
5
TCLK
SAMPLING OF BIT ~ ~ ~ ~AMPLING OF BIT 1
~
TSER
xff)(
AMPLING OF PARALLEL DATA
1-8
T1-T8
POSSIBLE GATING OF
TIDLE AT TCHCLK
FALLING EDGE
TIDLE
"IGNORING THROUGHPUT DELAY
"TNRZ
CHANNEL 2 NORMAL DATA
-I'
CHANNEL 3 IDLE CODE
Figure1. Channel-by-Channel Control - TIDLE
The approach assumed here is that a microprocessor
system is used but it does not produce the control signals
directly itself. Instead, a suitable hardware interface
between the microcontroller and the R8070 provides a
correctly timed control signal from the binary numbers
downloaded from memory.
A microcontroller could be used to set the appropriate
logic levels for TIDLE, RIDLE, and RMW, but it would need
to update these values once every 5.2 J.Ls for T1 or every
3.9 J.Ls for CEPT PCM 30. These times are too fast for
normal programmed output, even for a fast
microcontroller. Special output techniques such as direct
memory access (DMA) could be used.
8-43
Independent Channel Control for the R8070
R8070
be used for a 32 channel system, but see also method 4).
The registers are connected end-to-end to form a 24-bit
shift register. Each register may be loaded in parallel from
the 8-bit microprocessor bus. Under control of the timing
circuits, the 24 bits shift in the direction of the arrows
towards the final serial output which becomes the control
signal. The serial output is recirculated back to the serial
input to avoid reloading the registers at the end of every
frame. This reduces the load on the microprocessor.
Additional control signals are required to handshake with
the microprocessor to facilitate the data transfer.
THE INTERFACE AND ITS REQUIREMENTS
Figure 2 outlines one form that the interface might take.
The essential elements are: storage, parallel-to-serial
conversion, a microprocessor-compatible bus, timing, and
control. These elements are embodied within the shi!t
registers and their associated control logic. Additional
buffers might be necessary to avoid timing conflicts when
the registers are loaded. The timing logic takes clocks from
the microprocessor and from the R8070 and generates the
necessary timing and control pulses for the buffers, shift
registers and microprocessor. Various versions of a shift
register-based interface are examined.
The timing for this circuit is shown in Figure 4 for the Tl
format. RCHSYNC, which occurs at the end of every frame,
controls the loading of the shift registers. The signal is first
gated with RWIHBT so as not to mask a rising edge of
RCHCLK, which shifts the registers. RIDLE is sampled as
bit 7 emerges from RSER and is implemented in the next
channel. At the start of the next channel, on the rising edge
of RCHCLK, the shift register is shifted in preparation for
the next sampling. Thus the shift register, when parallel
loaded, contains a 1 in each bit position for every channel
in which idle code, for example, is required. The control bit
for channell is loaded into the far right position of register
3 so that it emerges first from the register. On loading, the
bit for channel 1 is available at the serial output. The first
shift brings the control bit for channel 2 to the serial output.
THE SHIFT REGISTER APPROACHES
Various different configurations of shift registers and
buffers are possible, each offering its own advantages. The
different methods are shown in Figures 3 through 7.
SHIFT REGISTER METHOD 1
Figure 3 shows one method by which shift registers can be
used to produce channel-by-channel control signals for,
for example, RIDLE. Three 8-bit shift registers (e.g.,
74LS 166) are required for a 24 channel system (four would
PARALLEL
DATA BUS
SHIFT REGISTERS
24/32 BIT
PARALLEL
BUSTO
MICRO·
PROCESSOR
BUFFERS
SHIFT
REGISTERS
TlDlE
2
24/32 BIT
RIDLE
IDLE
RMW
RECIRCULATE
SHIFT/LOAD
t
ClR
ClK
t
t
CLKINH )
t
TO EACH
REGISTER
TIMING AND CONTROL
t
RB070 CLOCKS
TO MICROCONTROllER
Figure 3. Shift Register Method 1
Figure 2. Channel Controller Shift Register (Outline)
8-44
R8070
Independent Channel Control for the R8070
RCLK
RCHCLK
J
RCHSYNC _ _ _ _ _ _ _ _ _ _--',
L..I_ _ _ _ _ _ _ _ _ _
RWIHBT - - ,
.---,
IL-._ _ _---II. - - - ,IL.-_ _ _ _- ' I L1-_ _ _--'1. -
DATED __________________________
RCHSYNC
SHIFT
t
~
LOAD REGISTER
t
t
t
SAMPLE RIDLE
t
t
t
2
FOR CHANNEL 24
Figure 4. Timing Shift Register Method 1
It would be possible to incorporate a control signal that
overrides the register load if the current pattern of idle
channels is to be maintained. In which case the 24-bit
pattern would continue to recirculate. In addition, it is
necessary to set up the handshake signals for the
microprocessor. RCHSYNC might be used to interrupt the
processor at the end of every frame so that the registers
could be loaded. One problem with this scheme is that the
processor has very little time to make three loads to the
registers (and three more to each of the other control
signals).
8·BIT BUFFERS
8·BIT SHIFT REGISTERS
2
3
There are several solutions to the problem of the processor
data interface and these are addressed in the other
methods discussed below. For this method, though, the
problem of data transfer might be alleviated by arranging
that only one of the registers is loaded each frame. A coded
number system (address) for each register determines
which register is to be loaded.
TIDLE
PARALLEL
BUSTO
MICROPROCESSOR
RECIRCULATE
LOAD BUFFER SHIFT CLR CLK CLK INH )
t t t t t
SHIFT REGISTER METHOD 2
TO EACH
REGISTER
TIMING AND CONTROL
An alternative to the first method of shift register
implementation is described in Figure 5. The same three
8-bit registers are used but, instead of being loaded
directly from the bus, are loaded from buffers which are
loaded by the rnicroprocessor. These buffers allow the
binary data to be downloaded at any convenient time,
although it might be prudent to avoid the moment when the
t
R8070 CLOCKS
Figure 5. Shift Register Method 2
8-45
•
R8070
Independent Channel Control for the R8070
buffer to register transfer takes place. The 24-bit data could
be recirculated as before, or the buffers could be
retransferred to the registers at the end of each frame. The
timing and control requirements for this version are similar
to the previous one.
PARALLEL
BUSTO
MICROPROCESSOR
SHIFT REGISTER METHOD 3
Variation of the above method where only one 8-bit buffer
and register Is used is shown in Figure 6. This reduces the
hardware requirement but increases the burden of data
loading on the microprocessor. Recirculation is not
possible and It Is necessary to make a one-byte data
transfer every 8 channels (41 ....s for T1, 31 .... s for CEPT
PCM 30).
TIDLE
SHIFT REGISTER METHOD 4
Figure 7 shows a variation of the first method with 16-bit
registers (e.g., 74LS674) instead of 8-bit registers. This
reduces the hardware and interconnect requirements but
is really only suitable for the CEPT PCM 30 standard
because the spare capacity with only 24 channels to be
controlled would complicate recirculation. The circuit is
illustrated with a 16-blt microprocessor bus which
simplifies the parallel loading of the registers. Buffers could
be added if required as in method 2. In the CEPT PCM 30
system, idle code cannot be transmitted in time slots 0 or
16, so the control bits related to these time slots would
normally be set to O.
CLOCK, SHIFT, LOAD, CHANNEL NO.
Figure 6. Shift Register Method 3
RAM Is a normal microprocessor peripheral and is
commonly available In a single package, as opposed to the
multiple shift register solution. Indeed, the R8040 triport
memory could be used. However, the generation of timing
signals to control the RAM is more complex and, more
importantly, it would be more difficult to deal with the
independent timing requirements of transmit and receive
timing (TCLK and RCLK are not always synchronized). This
approach is not pursued in this application note.
ALTERNATIVE APPROACH
Figure 8 outlines an alternative approach to the
implementation of the interface. In this case a single, 32 x
4 random access memory (RAM) contains the binary
information on the channels required to contain idle code
and digital milliwatt. The RAM locations are sequentially
accessed to produce the required logic control signals for
TIDLE, etc. The approach is initially attractive because the
8-46
R8070
Independent Channel Control for the R8070
16·BIT PARALLEL DATA BUS TO MICROPROCESSOR
1-_"'TlDLE
RECIRCULATE
SHIFT, LOAD, AND CLOCK
CLOCKS
TO .....
----1
MICRO
t
t
t
TIMING AND CONTROL
r-
CLOCKS
FROM
RS070
~----------------~
Figure 7. Shift Register Method 4
PARALLEL
DATA BUS
BUFFERS
TIDLE
RAM (32 X 4)
1111111111111111111111111111111
1111111111111111111111111111111
1111111111111111111111111111111
1111111111111111111111111111111
RIDLE
RMW
CLOCKS
FROM
RS070
TO MICROCONTROLLER
•
Figure 8. Outline of Channel Controller - RAM
8-47
T1/CEPT PCM 30
Application Note
'1'
Rockwell
Idle Code Generation
i
Figure 1 illustrates the insertion of idle code at the
transmitter. The first two traces represent the insertion of
idle code on channels 3, 7, 8, and 19. To achieve this,
TIDLE Is taken high just prior to the sampling of these
channels at the transmitter input, T1-T8.
INTRODUCTION
A fully occupied T1 link contains 24 channels, CEPT PCM
30 has 30 channels. But a PCM link may not be fully
occupied, i.e., may have less than 24 or 30 active channels.
The unoccupied channels usually contain idle code. Idle
code is generally the PCM code word that corresponds to
zero or near zero volts as an analog signal.
The exact timing requirements of TIDLE are shown in the
lower traces, on an expanded scale, for the case of
channel 3. The rising edge of TCHCLK indicates the
sampling of data on T1-T8. At this time, bit 1 would be
sampled from TSER if a serial data interface were selected
(although TCHCLK is not available in serial mode).
The R8070 implements idle code insertion both at the
transmitter (to be sent over the PCM link) and at the
receiver (to be inserted in place of the received channel
data).
Conventionally, cycles of TCLK are numbered as per the
currently sampled data bit on TSER. TIDLE is sampled at
bit 8. Sampling is shown in the figure by a transition of the
signal before and after the sampling instant. Typically,
TIDLE might be gated by TCHCLK so as to be stable when
sampled. TIDLE is shown transitioning at the falling edge
of TCHCLK. Note that TNRZ is shown without the effect of
transmitter throughput delay (8 cycles of TCLI<). The idle
code would normally emerge 8 bit times (1 channel time)
after being requested.
This note describes how other idle codes - or test
patterns - may be inserted into the received or
transmitted data channels.
IDLE CODES
The idle code for T1 modes is 01111111. The idle code for
CEPT PCM 30 modes is 01010101. The actual PCM codes
(after allowing for inversion of all bits in the T1 system, or
of even bits in CEPT PCM 30) are 10000000 and 00000000,
respectively, which correspond to zero volts or near zero
volts analog signal.
RECEIVER - RIDLE
When RIDLE is high, the next channel data to be presented
at the receiver output is replaced with idle code. RIDLE is
sampled on the rising edge of RCLK at the emergence of
bit 7 on RSER. Idle code is inserted in the next channel. if
RIDLE is modulated (turned on and off) at the appropriate
channel boundaries, then channel-by-channel control of
idle code insertion is obtained. Idle code appears on RSER
and R1-R8 but not on R8 during a signaling bit. RIDLE is
only operative when the receiver is in "Sync" because
knowledge of the channel boundaries is required.
INTERNAL GENERATION OF IDLE CODE
BY THE R8070
TRANSMITTER - TIDLE
When TIDLE is high, the next channel data to be
transmitted is replaced with idle code. TIDLE is sampled at
bit 8 of each channel for implementation in the next
channel. If TIDLE is modulated (turned on and off) at the
appropriate channel boundaries, then channel-by-channel
control of idle code insertion is obtained. Idle code
appears on all transmitter outputs; TNRZ, TPOS, and
TNEG. Idle code does not replace signaling bits in T1
modes, or time slot 0 (framing) and time slot 16 (signaling)
in CEPT PCM 30 modes.
Document No. 29300N32
Figure 2 illustrates idle code insertion at the receiver. The
first two traces show at the frame level how modulation of
RIDLE allows insertion of idle code into selected channels.
The lower traces show the timing requirements of RIDLE at
the channel 2/3 boundary.
Application Note
8-48
Order No. 332
October 1987
R8070
Idle Code Generation
R8070
11-T8
OR
TSER
TNRZ
TIDLE
TNEG
TPOS
I-
---------------+].1
FRAME
24
19
~~
TIDLE
CHANNEL NO.
7
____________~rl~______
8
19
TCHCLK
5
6
7
2
8
3
4
5
TCLK
SAMPLING OF BIT ~ ~
,...c::-
~AMPLING OF BIT 1
~
TSER
xffX
AMPLING OF PARALLEL DATA
1-8
T1-T8
TIDLE
"IGNORING THROUGHPUT DELAY
~MPLING
POSSIBLE GATING OF
TIDLE AT TCHCLK
FALLING EDGE
OF TIDLE
"TNRZ
.j.
CHANNEL 2 NORMAL DATA
CHANNEL 3 IDLE CODE
Figure 1. Generation of Idle Code - Transmitter
between normal and idle data. XTIDLE could transition at
the falling edge of TCHCLK (as might the channel data
itself) to ensure stability during sampling of T1-T8 at the
rising edge of TCHCLK.
EXTERNAL GENERATION OF IDLE CODE
TRANSMittER
If an idle code other than the standard provided by the
R8070 is required then this may be applied externally with
appropriate timing in the same way as normal channel
data. Figures 3 and 4 illustrate how this might be done for
a parallel or serial data interface, respectively.
In Figure 4 the external idle code is first serialized using a
shift register before being multiplexed with the normal
serial channel data under the control of ZTIDLE. ZTIDLE
should be aligned to the channel boundaries for correct
switching of the multiplexer. The shift register is clocked by
the falling edge of TCLK to avoid shifting data during the
sampling of TSER.
In Figure 3 the external idle code is multiplexed with the
normal channel data. A control signal, XTIDLE, selects
8-49
II
:
Idle Code Generation
R8070
RB070
RSER
OR
R1-R8
RPOS
RNEG
RIDLE
~I'----------------------------CH
RSER
3
7
FRAME
----------------------------~·I
24
19
B
1 I 1:: : : : : : : :1
t"'' ' 1
t::E!::::::
~__~~t~'"r'''~''__• __~~~'''~'''~''''~'''~'''~__~~~__~~~__~~~~~~~'''~'''~'.__~~~__~~
IDLE CODE INSERTED
RIDLE
CHANNEL NO.
~
r-l~
7
_________________~rl~_______
B
19
RCHCLK
5
6
7
2
8
3
4
5
RCLK
POSSIBLE GATING
OF RIDLE AT RCHCLK
F~LLING EDGE
RIDLE
---II
'i'1
,
~- SAMPLING OF RIDLE
RSER,
R1-R8
CHANNEL 2 NORMAL DATA
---<,"'1---
CHANNEL 3 IDLE CODE
Figure 2. Generation of Idle Code· Receiver
RECEIVER
MODULATION OF RIDLE AND TIDLE
An alternative idle code may be substituted at the receiver
output using a multiplexer. This may be done for either the
serial or parallel data interface as shown in Figure 5. Both
XRIDLE and ZRIDLE should transition at the rising edge of
RCHCLK.
The modulated signals for RIDLE and TIDLE may be
produced by gating the control signal with an appropriate
clock. (See Application Note, "Independent Channel
Control" Order No. 331.)
8-50
R8070
Idle Code Generation
XTIDLE - - - . . ,
R8070
RS070
IDLE CODE
PARALLEL
CHANNEL
DATA
Tl-TS
ZTIDLE
TNRZ
TNRZ
TPOS
TPOS
TNEG
TNEG
IDLE CODE
MULTIPLEXER
Figure 3. External Idle Code - Parallel
Figure 4. External Idle Code - Serial
XRIDLE
RS070
MULTIPLEXER
RSER
SHIFT REGISTER
SERIAL
DATA
RCLK
RPOS
RX
IDLE CODE
RNEG
S
PARALLEL
DATA
Rl-RS
ZRIDLE
Figure 5. External Idle Code at the Receiver
8-51
•
T1/CEPT PCM30
Application Note
'1'
Alarm Handling with the R8070
Rockwell
In CEPT terminology, the Blue Alarm Is analogous to an
Alarm Indication Signal (AIS). The Red Alarm is a Service
Alarm Indication or Prompt Maintenance Alarm. The
Yellow Alarm is an "alarm indication to the remote end".
SYSTEM OVERVIEW
Figure 1 shows a typical PCM link between central offices
(local exchanges). The central offices (COs) may be up to
100 miles apart and the link may include test monitors or
central office repeaters along the route. Digital repeaters
spaced at 1-mile intervals regenerate the digital pulses.
Under normal operating conditions, 24 time-division
multiplexed, PCM encoded channels, each carrying a
voice or data signal, are transmitted in each direction (30
channels for CEPT PCM 30).
The alarm requirements for T1 are described in CCITT
Recommendation G.733 and in Bell Pub 43801 , Section A,
Paragraph 6. The alarm requirements for CEPT PCM 30 are
described in CCITT G.732.
RED ALARM WITH THE R8070
When the R8070 loses frame alignment (synchronization),
Receive Red Alarm (RRED) goes high (following the F-bit
on RSER whose error caused "loss of sync"). The R8070
will immediately attempt to reframe. If there are many
errors on the line, RRED may be seen to pulse high and low
as synchronization is partially recovered and then lost.
External circuitry may be used to apply "hysteresis" to
RRED so that it conforms to the minimum time
requirements for the Red Alarm defined by Bell Pub 43801.
If there are no errors on the line, the R8070 will reframe
within the specified maximum reframe time.
GENERATION OF ALARMS
Suppose that a line fault causes a loss of signal, or severe
errors (see Figure 1). The monitor will lose synchronization
and will generate a local Red Alarm. In addition, the
monitor will transmit a Blue Alarm onward to the far-end
office. The Blue Alarm's "continuous 1s" pattern maintains
the clock recovery operation in the subsequent digital
repeaters. The monitor will also transmit a Yellow Alarm
backwards to the near-end office to indicate the loss of
alignment.
NEAR END
CENTRAL OFFICE
FAR END
CENTRAL OFFICE
MONITOR OR
CENTRAL OFFICE
REPEATER
TX
RX
C>
C>
SERIAL
DATA
------twl
STOP
Figure 1. System Initialization Flowchart (Cont'd)
8-71
~
I
I
Application Note
Programming the R8071 Buffers
POINTERS are located between memory location XXXCO
-XXXFF.
CONFIGURING SYSTEM BUFFER
The SYSTEM BUFFER consists of the CHANNEL ACTIVATION BYTE and the CHANNEL BUFFER
POINTERS.
The ACTIVE bit (Bit 7) in the CHANNEL ACTIVATION
BYTE determines whether the channel to be serviced is to
be activated or deactivated. Setting the ACTIVE bit to "1"
would activate the channel, while resetting the bit to "0"
would deactivate the channel. Deactivating one side of a
channel can also be accomplished by loading the NEXT
BUFFER ADDRESS with an invalid buffer address (for
more detail see the section entitled, "Configuring Transmit Command Buffer").
Load Bit 0-4 of the CHANNEL ACTIVATION BYTE (located at address XXXOO) with the binary number of the
channel that is to be serviced. Bit 4 is the MSB and bit 0 is
the LSB. In a T-1 system environment, valid channels are
those between 1 - 24, while in a CEPT system the valid
channels (time slots) are those between 0 - 31. In an application which is neither a T-1 nor CEPT system application, all 32 channels (0 - 31) are valid.
The actual activation or deactivation process begins only
when the ATTN input line to the R8071 is asserted. The
data contained in both the CHANNEL ACTIVATION BYTE
and the CHANNEL BUFFER POINTERS at the time the
ATTN input is asserted determines the actual channel that
is to be serviced. Once a particular channel has been serviced (Le., activated or deactivated) and the ATTN input to
the R8071 is no longer asserted, modifying the data in the
CHANNEL ACTIVATION BYTE and the CHANNEL BUFFER POINTER will not change the operating mode of the
previous serviced channel. This allows the R8071 to have
more than one channel active at a time.
The R8071 can only activate or deactivate one side of a
channel at a time. This requires that the R8071 be told
which side ofthe channel is to be serviced (Le., the receive
or the transmit side). The bit that determines which side of
the channel is to be serviced is the RXITX (Bit 5). Setting
bit 5 to a "1" selects the receive side as the side of the
channel in question to be serviced. Resetting bit 5 to a "0"
selects the transmit side as the side of the channel to be
serviced.
The CHANNEL BUFFER POINTERS contains 64 2-byte
words which are the addresses of the first buffers for each
side of the 32 channels. The CHANNEL BUFFER
POI NTERS are divided between the receive and the transmit sections. The transmit side CHANNEL BUFFER
POINTERS are located between memory location XXX80
- XXXBF, with the transmitter channel 0 starting address
located at XXX80 and 81, and transmitter channel 1 start
address located at XXX82 and 83. Similar to the transmit
side portion, the receive side CHANNEL BUFFER
This is accomplished in the R8071 by activating one channel (Le., initiate the ATTN and ATACK handshake). Upon
completion of the ATTN and ATACK handshake, the information for the next channel to be activated can then be
loaded into the ACTIVATION BYTE and the CHANNEL
BUFFER POINTER. Upon completion of the next ATTN
and ATACK handshake, two channels are now active. To
have additional channels activated, the whole process is
repeated.
8-72
Programming the R8071 Buffers
Application Note
Load BIt Q.4 of the
CHANNEL ACTIVATION
BYTE with a number to
specify the channel
to be serviced.
YES
Reset RX/TX (Bit 5) In
the
CHANNEL
ACTIVATION
BYTE to a '0'
Set RX/TX (Bit 5) In
Load the starting
address of the first
buffer of the channel
that is to be serviced
into the specified
CHANNEL BUFFER
POINTERS location.
The address is a
2-bytes long address.
For Transmit channel
the memory area is
defined to be betwee
XXX80-BF
Load the starting
address of the first
buffer of the channel
that is to be serviced
Into the specified
CHANNEL BUFFER
POINTERS location.
The address Is a
2-bytes long address.
For Receive Channel
the memory area Is
defined to be betwee
XXX -FF.
the
CHANNEL
ACTIVATION
BYTE to a '1'
Figure 2. Configuring System Buffer Flowchart
8-73
•
Application Note
Programming the R8071 Buffers
YES
Reset ACTIVE ( Bit 7 ) In
the
CHANNEL
ACTIVATION
BYTE to 0'0'
Set ACTIVE ( Bit 7 ) in
the
CHANNEl
ACTIVATION
BYTE to a '1'
Figure 2. Conftgurlng Syatem Buffer Flowchart (Cont'd)
8-74
Application Note
Programming the R8071 Buffers
is set up for loop mode (i.e., with LOOP bit set to a "1").
When both the receive and transmit sides are set up for
LOOP mode, the R8071 can perform a Local (Near-end)
Loop-back. Loop·back can be done only one channel at a
time.
CONFIGURING TRANSMIT COMMAND
BUFFER
Set the CMND bit (Bit 1) in the STATUS BYTE to "1". This
will ensure that the R8071 will be able to distinguish the
difference between a DATA BUFFER and a COMMAND
BUFFER. A DATA BUFFER would have this bit reset to
SIG (Bit 1) and HDLC (Bit 0) together define operational
mode of the specified channel.
"0".
SIG
1
Load the NEXT BUFFER ADDRESS with the address of
the next buffer to be processed upon completion of this
buffer. Typically, the next buffer after a COMMAND BUFF·
ER is a DATA BUFFER. However, the NEXT BUFFER AD·
DRESS could contain the current buffer's address, or an
Invalid buffer address. Pointing to an Invalid buffer address
(any address between FFFO • 0000) will deactivate the
channel which the current buffer Is part of. The channel will
be deactivated only after the completion of the current buff·
er.
o
o
HDLC
0
0
1
1
1
MODES
Non·HDLC Signaling Channel
Non·HDLC Data Channel
HDLC Data Channel
Reserved
Non-HDLC Data Channel
DMI application modes 0 and 1 may be specified by this
mode. In this mode, as soon as the channel transmitter is
activated and on completion of this buffer, an all ones is
transmitted until data from the TRANSMIT DATA BUFFER
(location of the first data buffer is determined by the NEXT
BUFFER ADDRESS) Is transmitted. To ensure that
uninterrupted data transmission the CFiP bit in the linked
data is reset to ·0".
The STATUS byte in the TRANSMIT COMMAND BUFF·
ER contains the UNDR, IVBA, CFiP, CMND, and MPTY
bits. UNDR (underrun) and IVBA Qnvalid buffer address)
are bits normally set by R8071 , which the host would read
and reset when appropriate. The CFiP (complete/partial
buffer) In a COMMAND BUFFER is read by the host arid
set by the R8071 when it reports status for the processed
COMMAND BUFFER and CMND (command) bits are only
set by the host and read by R8071. In a TRANSMIT COM·
MAND BUFFER the MPTY (empty) bits is reset by the host
and set by R8071.
Non·HDLC Signalling Channel
When a channel is configured In Non·HDLC Signalling
Channel mode, the channel carries bit·oriented Signalling
data without an HDLC format. Figure 9 of the R8071 Data
Sheet specifies the format used to maintain the received
data integrity. In this mode the R8071 assumes that there
is only a maximum of 2 linked data buffers, with the last
data buffer a recirculating buffer (i.e., a buffer with it's
NEXT DATA BUFFER pointing to itself). To maintain con·
tinuous data transmission, the last data buffer MPTY bit is
never set to a "1" by the R8071.
UNDR (underrun), this bit is set by the R8071 when its
transmit channel runs out of data. When this condition 0ccurs the transmit channel sends an all ones pattern until
additional data are available to be transmitted. The exception to this occurs when the transmit channel is in HDLC
mode. In HDLC mode the specific transmit channel
automatically transmit an HDLC abort code (14 consecu·
tive ones) followed by lIags.
HDLC Data Channel
When a channel is set up to be a HDLC Data Channel it is
capable of handling data in either a HDLC data format or
a LAPD channel.
IVBA Qnvalld Buffer Address). This bit is set by the R8071
If it encounters an invalid buffer (all addresses between
FFFO • 0000). When this condition occurs, the specific
transmit channel will automatically be deactivated.
The 16 bit CRC·CCITT generator polynomial is:
X 16
The MODES byte specifies the operational mode of the
given channel. It is critical that the operational mode
specified for the near and far end of a transmission be the
same.
+ X12 + X5 +1
The FILLJMASK byte is an 8-bit byte which allows the
R8071 to perform rate adaption of sub-64 kbps data rates
in the form of
n X 8 Kbps (n = 1 to 8)
Setting LOOP (bit 2) to "1" would select the associated
receive channel to retrieve data stored internally in the
R8071, and present it to the shared memory. The data
stored In the R8071 is provided by the transmitter when it
to the standard 64 Kbps bearer rate. More detailed ex·
planations are available If figure 5 and table 4 of the data
sheet.
8-75
I
I
~
Programming the R8071 Buffers
Application Note
Load Byte 0 & 1 (Also
knOWn as Next Buffer
Address) with the
address of the next
buffer ( 2-Byte Word)
to be accessed
upon completion of
this buffer.
.
Reset UNDR ( Bit7 ).
I\IBJ\!.Bit6). and
the CF/P (Bit 2) In the
STATUS Byte to "0'
Figure 3. Configuring Transmit Command Buffer
8-76
Programming the R8071 Buffers
Application Note
YES
Reset INV( Bit 3 ) In
the MODES Byte to
Set INV( Bit 3 ) In
the MODES Byte to
YES
Reset LOOP ( Bit 2 ) In
the MODES Byte to
'0'
Set LOOP ( Bit 2 ) In
the MODES Byte to
'1'
Figure 3. Configuring Transmit Command Buffer (Cont'd)
8-n
•
Programming the R8071 Buffers
Application Note
YES
>--....c
Program MODES Byte'
SIG ( Bit 1 ) to "0" and
HDLC (BitO)to '0'
YES
Program MODES Byte'
C>--I~ SIG(Bit 1 )to"l"and
HDLC ( Bit 0 ) to "0"
Program MODES Byte'
SIG ( Bit 1 ) to "0" and
HDLC (BitO)to "1'
YES
Load $FF into the
FILL/MASK Byte
Load the FILL/MASK
Byte with the required
m k
m.
Figure 3. Configuring Transmit Command Buffer (Cont'd)
8-78
Application Note
Programming the R8071 Buffers
bits are for data length information), would select that the
Flag Stuffing feature be enabled. FC allows the R8071 to
automatically append a certain number of flags to the end
of a data string.
CONFIGURING TRANSMIT DATA BUFFER
Reset the CMND bit (Bit 1) in the STATUS BYTE to "a".
This would ensure that the R8071 will be able to distinguish the difference between a DATA BUFFER and a
COMMAND BUFFER. If this buffer was a COMMAND
BUFFER the host would have this bit set to "1".
The flags that are appended will vary depending on the
mode of the transmitting channel. In HDLC mode, HDLC
flags ($7E in hexadecimal) are transmitted. In Non-HDLC
data mode, the flags are all ones octets. In a Non-HDLC
signalling mode this feature is not available.
.
Load the NEXT BUFFER ADDRESS with the address of
the next buffer to be processed upon completion of this
buffer. The next buffer after a DATA BUFFER could either
be a DATA BUFFER or a COMMAND BUFFER. Linking to
a COMMAND BUFFER maybe desired if the operating
mode of the channel need to be changed. The address
contained in the NEXT BUFFER ADDRESS could be
pointing to the current buffer's address, or an invalid buffer address. If the NEXT BUFFER ADDRESS contains an
invalid buffer address (any address between FFFO - 0000),
the channel which the current buffer is part of will be deactivated. Deactivation will occur only upon the completion of
the current buffer.
The FLAG COUNT byte determines the number of flags to
be transmitted. This byte is located after the last data byte
in the d~a buffer. The maximum number of additional flags
that can be appended after the last valid data byte is 255.
The FO (Flag Offset, bit 6) in the most significant byte of
the DATA LENGTH (2-byte word) is meaningful only if FC
is set and the channel is in HDLC Data mode. When FO is
set by the host, the R8071 will count the total number of
HDLC zeros intentionally inserted among the data during
the entire duration of transmission. At the end of each
HDLC frame, it divides the accumulated number by eight
and retains the remainder. The remainder is known as the
Flag Count Offset. The R8071 would then subtract the
Flag Count Offset (which is available internally to the
R8071 only) from the FLAG COUNT byte. The resultant is
the additional number of HDLC flags transmitted.
The CFiP bit (Bit 2) in the STATUS BYTE is set by the host
to indicate that this buffer contains the last byte of a sequence of bytes to be formatted according the HDLC. With
CF/P set, the R8071 automatically recognizes that the
CRC needs to be calculated and appended at the end of
the data. The R8071 performs this task before looking for
more data in the next buffer.
Reset other status bits in the STATUS Byte in preparation
for transmission.
In the current data buffer is a partial buffer (CF/P = 0) the
R8071 will only look at the BUFFER SIZE, but if the data
buffer is a complete buffer the R8071 will look at the DATA
LENGTH instead. These sizes are used by the R8071 in
determining when to start looking for another data buffer
or command buffer, and to determine the location of the
last data byte in the current buffer.
The data to be transmitted can now be loaded. Include the
FLAG COUNT Byte if additional flags are to be appended
after the last valid data byte.
Reset the MPTV (Bit 0) in the STATUS Byte to "00, since
the buffer is now full with information that the R8071 has
not processed.
Setting FC (Flag Control, bit 7) in the Most Signific.ant Byte
of the DATA LENGTH (2-Byte word, but actually only 12
•
8-79
Programming the R8071 Buffers
Application Note
Load Byte 0 & 1 (Also
known as NEXT BUFFER
ADDRESS) with the
address of the next
buffer ( 2-Bytes Word)
to be accessed
upon completion of
this buffer.
NO
Set CFjP( Bit 2) in
the STATUS Byte to
. 1•
Reset CF/P( Bit 2) In
the STATUS Byte to
"0'
Load byte 4 & 5 ( Also
known as DATA
LENGTH) with the size
of the actual number
of data bytes to be
transmitted. (This
Information is read
only If the buffer is a
complete buffer.
M xl' I n
Load Byte 2 & 3 ( Also
known as BUFFER SIZE )
with the size of the
memory bytes
allocated by the host
for storing the data to
be transmitted.
( this information is vall
If the buffer is a partial
buffer; Max 12 bit long)
Figure 4. Configuring Transmit Data Buffer
8-80
Application Note
Programming the R8071 Buffers
NO
Reset FC ( Bit 7) in
the MSB portion of th
DATA LENGTH Bytes
to '0'. Also known as
The Flo Control
Set FC ( Bit 7) in
the MSB portion of the
DATA LENGTH Bytes
to "1". Also known as
The Flo Control
Load the number of
flags in to the FLAG
COUNT Byte.
(Located after the
last data byte in
the buffer)
NO
Reset FO ( Bit6) in
the MSB portion of th
DATA LENGTH Bytes
to '0". Also known as
The Flag Offset
II
Figure 4.. Configuring Transmit Data Buffer (Cont'd)
8-81
Application Note
Programming the R8071 Buffers
Set FO ( Blt6) In
the MSB portion of the
DATA LENGTH Bytes
to '1'. Also known as
The Flag Control
Reset UNDR ( Blt7 )
IVBA ( B1t6) In the
STATUS Byte to '0'
Load the data to be
transmitted Into the
DATA BYTES location
STOP
Figure 4. Configuring Transmit Data Buffer (Cont'd)
8-82
Programming the R8071 Buffers
Application Note
stored in the R8071 is provided by the transmitter when it
is set up for loop mode (i.e., with LOOP bit set to a "1").
When both the receive and transmit sides are set up for
LOOP mode, the R8071 can perform a Local (Near-end)
Loop-back. Loop back can be done only one channel at a
time.
CONFIGURING RECEIVE COMMAND
BUFFER
Set the CMND bit (Bit 1) in the STATUS BYTE to "1". This
would ensure that the R8071 will be able to distinguish the
difference between a DATA BUFFER and a COMMAND
BUFFER. A DATA BUFFER would have this bit reset to
aal.
SIG (Bit 1) and HDLC (Bit 0) together define operational
mode of the specified channel.
Load the NEXT BUFFER ADDRESS with the address of
the next buffer to be processed upon completing this buffer. Typically, the next buffer after a COMMAND BUFFER
is a DATA BUFFER. The NEXT BUFFER ADDRESS could
be the current buffer's address, or an invalid buffer address. If the contents of the NEXT BUFFER ADDRESS
point to an invalid buffer address (any address between
FFFO - 0000), the channel which the current buffer is part
of will be deactivated upon completion of the current buffer. If the address was to point to the current buffer's address, it would be called a recirculating buffer.
SIG
1
HDLC
0
o
0
1
1
1
o
MODES
Non-HDLC Signaling Channel
Non-HDLC Data Channel
HDLC Data Channel
Reserved
Non-HDLC Data Channel
DMI application modes 0 and 1 may be specified by this
mode. In this mode, as soon as the channel receiver is activated it will check the allocated buffer and start placing
the received data into the buffer. After filling a buffer, it updates the status of the just completed buffer, simultaneously asserting INTR. It then moves on to the next
buffer and repeats the process again until it is interrupted
by ATTN or runs out of buffers.
The STATUS byte in the RECEIVE COMMAND BUFFER
contains the OVER, IVBA, CF/P, CMND, and MPTY bits.
OVER (overrun) and IVBA (invalid buffer address) are bits
normally set by R8071, which the host would read and
reset when appropriate. The CF/P (complete/partial buffer) in a COMMAND BUFFER is read by the host and set
by the R8071 when it reports status for the processed
COMMAND BUFFER and CMND (command) bits are set
only by the host and read by the R8071. In a RECEIVE
COMMAND BUFFER the MPTY (empty) bit is reset by the
host and set by the R8071.
Non-HDLC SIgnaling Channel
When a channel is configured in Non-HDLC Signaling
Channel mode, the channel carries bit-oriented signaling
data without an HDLC format. The format used in order to
ensure that the receive channel receives the data properly is specified in Figure 19 of the R8071 Data Sheet. I n this
mode the R8071 assumes that there is only a maximum of
2 linked data buffers, with the last data buffer a recirculating buffer.
OVER (overrun) bit is set by the R8071 when its receive
channel has no next data buffer (all addresses between
FFO • 0000). When this condition occurs, the specific
receive channel will automatically be deactivated.
HDLC Data Channel
The MODES byte specifies the operational mode of the
given channel. It is critical that the operational modes
specified for the near and far end of a transmission be the
same.
In this mode the R8071 is capable of operating as either
an HDLC data channel or a LAPD channel. The 16 bit
CRC-CCITT generator polynomial used by the R8071 to
generate the CRC-16 is
Setting INV (bit 3) to "1" would select all data received are
to be inverted prior to writing the information to the shared
memory. This would be set only if the data were initially inverted prior to their transmission at the far end. All other
non-data information such as HDLC flag, CRC, and
ABORT are also inverted after being received.
The FILLIMASK byte is an 8-bit byte which allows the
R8071 to perform rate adaption of sub-64 kbps data rates
in the form of
Setting LOOP (bit 2) to "1" would select that the associated
receive channel retrieve data stored internally in the
R8071, and present it to the shared memory. The data
to the standard 64 Kbps bearer rate. A more detailed explanation is available in figure 5 and table 4 of the data
sheet.
X16 + X12 + X5 +1
n x 8 Kbps (n=1 to 8)
8-83
Programming the R8071 Buffers
Application Note
load Byte 0 & 1 (Also
known as Next Buffer
Address) with the
address of the next
buffer ( 2-Byte Word)
to be accessed
upon completion of
this buffer.
Reset OVER ( Bit7 ).
IVBA!..Pit6). and the
CF/P( Bit2) In the
STATUS Byte to '0'
Figure 5. Configuring Receive Command Buffer
8-84
Programming the R8071 Buffers
Application Note
YES
Set INV( Bit 3 ) in
the MODES Byte to
Reset INV( Bit 3 ) in
the MODES Byte to
" 1"
'0"
YES
Reset LOOP ( Bit 2 ) in
the MODES Byte to
'0'
Set LOOP ( Bit 2 ) in
the MODES Byte to
"1 '
Figure 5. Configuring Receive Command Buffer (Cont'd)
8-85
•
I
Programming the R8071 Buffers
Application Note
YES
Program MODES Byte'
">--~ SIG ( Bit 1 ) to "0" and
HDLC ( Bit 0 ) to "0"
YES
C.'>---t~
Program MODES Byte'
SIG ( Bit 1 ) to "1· and
HDLC ( Bit 0 ) to "0'
Program MODES Byte'
SIG ( Bit 1 ) to "0· and
HDLC (Bit O)to "1"
YES
Load $FF into the
FILL/MASK Byte
Load the FILL/MASK
Byte with the required
m k
m.
C__
S_TO_P_)
Figure 5. Configuring Receive Command Buffer (Cont'd)
8-86
Application Note
Programming the R8071 Buffers
In preparation to receive data, initialize all the status bits
in the STATUS BYTE. Reset OVER (overrun, bit 7), IVBA
(invalid buffer address, bit 6), ABRT (Abort, bit 5), FCER
(Frame check error, Bit 4), SHER (Short HDLC Frame
Error, bit 3), and CFjp (Complete Frame/Partial Frame
received, bit 2) to a "0". These bits are reset to ensure that
upon completion of the data reception the host will be able
to determine if any error conditions may have occurred.
The various error conditions that may occur are decoded
from the condition of the bits in the STATUS BYTE. (For
more information on the different error conditions, please
refer to Table 3 in the R8071 Data Sheet). The information
that can be derived from the STATUS BYTE would assist
the host to determine the validity of the data received.
CONFIGURING RECEIVE DATA BUFFER
Reset the CMND bit (Bit 1) in the STATUS BYTE
This would ensure that the R8071 will be able to
guish the difference between a DATA BUFFER
COMMAND BUFFER. A COMMAND BUFFER
have this bit set to "1".
to "0".
distinand a
would
Load NEXT BUFFER ADDRESS with the address of the
next buffer to be processed upon completion of this buffer. Typically, the next buffer after a COMMAND BUFFER
is a DATA BUFFER. However, the NEXT BUFFER ADDRESS need not necessarily point to a DATA buffer, it
could pOint to the current buffer's address, or to an invalid
buffer address. If the address was an invalid buffer address (any address between FFFO - 000), upon completing the current buffer, the channel, which the current buffer
is part of will automatically be deactivated.
In preparation for the received data, the host should set the
MPTY (Empty, bit 0) bit in the STATUS BYTE to "0". This
is to inform the R8071 that this RECEIVED DATA BUFFER is empty and ready to receive data.
The BUFFER SIZE determines how much memory is allocated for the received data. The actual received data size
will be written by the R8071 into the DATA LENGTH Byte.
•
8-87
I
Programming the R8071 Buffers
Application Note
Load Byte 0 & 1 (Also
known as NEXT BUFFER
ADDRESS) with the
address of the next
buffer ( 2-Bytes Word)
to be accessed
upon completion of
this buffer.
Load Byte 2 & 3 ( Also
known as BUFFER SIZE)
with the size of the
memory bytes
allocated by the host
for storing the data to
be received.
( this information is vali
if the buffer is a partial
buffer; Max 12 bit long)
Reset OVER ( Bit7 ),
IVBA ( Bit6 ),ABRT (BitS),
FCER (Bit4 ),SHER (Bit3),
CFjP (Bit2) in the
STATUS Byte to "0"
( STOP)
Figure 6. Configuring Receive Data Buffer
8-88
ROCKWELL SEMICONDUCTOR PRODUCTS SALES OFFICES
REGIONAL SALES OFFICE/ROCKWELL SEMICONDUCTOR PRODUCTS
Headquarters
0104
Semiconductor Products Division
Rockwell International
4311 Jamboree Road
P.O. Box C, MS 501·300
Newport Beach, CA 92658-8902
(714) 833-4600
TWX: 910-591·1698
FAX: (714) 833-4078 or (714) 833-4391
TLX: 170653
0102
Semiconductor Products Division
Rockwell International
10700 West HigginS Rd., Ste. 102
Rosemont, illinois 60018
(312) 297-8862
FAX: (312) 297·3230
United States/Canada
0105
Semiconductor Products D,VIsion
Rockwell International
5000 Birch, Sle. 400
Newport Beach, CA 92660
(714) 833-4655
FAX: (714) 833-6898
0103
Semiconductor Products DiVision
Rockwell International
5001 B Greentree
Executive Campus, Rt. 73
Marlton, New Jersey 08053
(609) 596-0090
MCI: 6502229511
FAX (609) 596-5681
0106
Semiconductor Products DiviSion
Rockwell International
3375 Scott Blvd., Ste. 410
Santa Clara, California 95054
(408) 980-1900
TWX: 650 260-6750
FAX: (408) 980-0744
0109
Semiconductor Products DiviSion
Rockwell International
3081 Holcomb Bridge Rd., Ste. A·1
Norcross, Georgia 30071
(404) 448-7414
FAX: (404) 446-7598
Westcom 1288
0101
Semiconductor Products Division
Rockwell International
2001 N. Collins Blvd., Ste. 103
Richardson, Texas 75080
(214) 996-6500
TLX 650227·9516
FAX: (214) 996·7812
Japan
0240
Semiconductor Products DIVISion
Rockwell International Japan Co. Ltd.
Overseas Corporation
Sogo Hanzomon Bldg., 8F
7, Kojimachi 1-<:home
Chlyoda·ku, Tokyo Japan 102
(81-3) 265·8808
TLX. J22198
FAX: (81·3) 263.()639
Asia Pacific
0263
Rockwell International Ltd.
514 Bank Centre
636 Nathan Road
Kowloon Hong Kong
(852) 3·7109129
FAX: (852) 3-7109220
0107
Semiconductor Products DIVision
Rockwell International
239 Littleton Rd., Suite 1B
Westford, Massachusetts 01886
(508) 692·7660
FAX: (508) 692·8185
TLX (MCI) 6502512464
Europe
0201
Semiconductor Products Division
Rockwell International GmbH
Fraunhoferstrasse 11
0--8033 Muenchen-Martinsried
West Germany
(49-89) 857·6016
TLX: 521·2650 rimd d
FAX: (089) 8.57.57.93
0111
Semiconductor Products Division
Rockwell International
55 Town Center Court, Sle. 700
Scarborough, Ontario
"Canada M1P 4X4
(416) 296-1644/1645
TLX: 06525235
FAX: (416) 296·1690
0202
Semiconductor Products Division
Rockwell International Limited
Central House
3, Lampton Road
Hounslow, Middlesex
TW3 1HY England
(44-1) 577·1034
FAX: 44-1·577·2257
TLX: 265871
MONREF G.REF.DUC001
0210
Semiconductor Products DiviSion
Rockwell International GmbH
Isafjordsgatan 11
163 40 Spanga
Sweden
(48-8) 751-5000
TLX: 122442
0246
Semiconductor Products
Rockwell-Colhns Italiana S.P.A.
Via Boccacclo, 23
20123 Milano, Italy
(39-2) 498·7479
TLX: 316562 RCIMIL 1
FAX: (39·2) 498·1450
0278
Semiconductor Products Division
Rockwell International
Immeuble de Bureaux Evry 2
523, Place des Terrasses
91034 Evry Cedex, France
(33-16) 497·2828
TLX: 690-328
FAX: (33-16) 078-2888
South America/Central America/India
0110
Semiconductor Products Division
Rockwell International
4311 Jamboree Road
P.O. Box C, MS 501-303
(714) 833-6212
FAX: (714) 833-4078 or (714) 833-6375
TWX: (910) 5911698
Mexico
0112
Semiconductor Products Division
Rockwell International
5000 Binch, Sle. 400
Newport BeaCh, California 92660
(714) 833-4655
FAX: (714) 833-8898
SALES REPRESENTATIVES-UNITED STATES/CANADA
For applications aSSistance, price quotations or technical literature. call your local Rockwell Semiconductor and Telecommunication Products DIViSion sales office.
ALABAMA
Robert O. Whitesell " Associates
2227 Drake Ave., P.O. Box 1797,
Suite 10-F
Huntsville, AL 35907
(205) 883-5110
FAX: (205) 882·9826
CALIFORNIA
2033
Centaur Corporation
18006 Skypark Circle, Ste. 106
Irvine, CA 92714
(714) 261·2123
TWX: 910 595·2887
FAX: (714) 261·2905
ARIZONA
2071
BSE, Inc.
7500 E. Buthereus, Suite K
Scottsdale, AZ 85290
(602) 483'()373
FAX: (902) 463-0383
2037
Centaur Corporation
23901 Calabasas Rd., Ste. 1063
Calabasas, CA 91302
(818) 704-1655
TWX: 910-493-2304
FAX: 818·704-7479
ARKANSAS
2026
Norcom Inc.
4450 Sigma Rd. Ste. 135
Dallas, TX 75234
(214) 386-4888
FA)(: 214-386-4907
Centaur Corporation
9420 Farnham, Ste. 201A
San Diego, CA 92123
(619) 278-4950
FAX: (619) 278-0649
TWX: 910-380·8723
2000
2045
A-1
2060
Criterion Sales Inc,
3350 Scott Blvd. Bldg. #44
Santa Clara, CA 95054-3126
(408) 988-6300
FAX: (408) 986·9039
TLX: 62111550
COLORADO
2072
Simpson" Assoc.
1500 W. Canal Court
Bldg. B, SUite 300
Littleton, CO. 80120
(303) 794-8381
FAX: 303·794-2409
CONNECTICUT
2004
Kitchen" Kutchin
. 23 Peck Street
North Haven, CT 06473
(203) 239-0212
TWX: 910474-0011
FAX: 203·234-9108
DELAWARE
2003
Beacon North
103-F Carpenter Dr.
Sterling, VA 22170
(703) 478-2480
FAX: 703-435-7115
FLORIDA
2005
Currie, Peak & Frazier, Inc.
7335 Lake Ellenor Dr.
Orlando Central Park, Orlando, FL
32808·6219
(407) 855-0843
FAX: (305) 851·1464
GEORGIA
2002
Currie, Peak and Frazier, Inc.
2888 Buford Hwy.
Duluth, GA 30136
(404) 497·9404
FAX: (404) 497·9412
SALES REPRESENTATIVE-UNITED STATES/CANADA (cont'd)
2030
Norcom, Inc.
4450 Sigma Rd., Ste. 135
Dallas, TX 75234
(214) 386-4888
FAX: (214) 386-4907
2032
Norcom, Inc.
9100 S.W. Freeway, Sulle 218
Houston, TX 77074
(713) 778-0392
FAX: 713-778-0433
UTAH
2073
Quorum 3
7427 Parkcrest Ct.
Salt Lake City, UT 84121
(801) 943-9227
FAX: (801) 943-3755
VERMONT
Kitchen • Kutchln, Inc.
(See Burlington, Massachusetts)
VIRGINIA
2034
Beacon North, Inc.
103-F Carpenter Dr.
Sterling, VA 22170
(703) 478-2480
FAX: (703) 435-7115
WASHINGTON
2078
Westerberg Auoc., Inc.
12505 N.E. Bel-Red Rd., Ste. 112
Bellevue, WA 98005
(206) 453-8881
TWX: 910 240-1599
FAX: (206) 453-8758
WASHINGTON, D.C.
2076
Beacon North
103-F Carpenter Drive
Sterling, VA 22170
(703) 478-2480
FAX: (703)435-7115
WYOMING
Simpson. Auoc., Inc.
(See Colorado)
CANADA
2036
Renmark Electronics Umlted
110 West Beaver Creek Road, Ste. 7
Richmond Hili, Ontario
Canada, L4B lJ9
(416) 881-8844
FAX: {416) 881-8848
2047
WEST VIRGINIA
Robert O. Whlteaall • Aaaoclates
(See Indlanapoli., Ind.)
Renmark Electronics Limited
1445 Woodruffe Avenue
Ottawa, Ontario
Canada, K2G lWl
(613) 727'()320
FAX: (613) 727-5527
BRAZIL
Hesdquartsrs:
Colgllinc.
249 E. 48th SI. Suite #60
New York, NY 10017
(212) 932-1340
FAX: (212) 828-3623
TX: 820660 CHEMEX UD
2007
Crlstech Tech. Ltda.
AYenida Paulista, 2001
8 Andar, Salas
Sao Paulo, Brazil
(55-11) 285-4031
FAX: 55-11-285-4446
AUSTRALIA
2046
VSI Electronics Ply. Limited
WISCONSIN
2058
Larsen Aaaoclates Inc.
10855 W. Potter Road
Wauwatosa, WI 53226
(414) 256'()529
FAX: (414) 258-9655
16 Dickson Avenue
Marmon, NSW
2064 Australia
(02) 439-4655
TLX: AA22846
FAX: (02) 439-8435
NEW ZEALAND
2050
VSI Electronlea, Ltd. (N.Z.)
Private Bag, Newmarket, 7 Beasley Ave.
Penrose Auckland, New Zealand
(9) 599150
TLX: NZ60340
FAX: (9) 593894
INDUSTRIAL DISTRIBUTORS-UNITED STATES/CANADA
ALABAMA
1000
Hamllton/Avnet Electronlea
555 Discovery
Huntsville, AL 35805-2809
(205) 937-7210
TWX: 810 726-2182
1188
Marshall Industries
3313 Memorial Parkway South
Huntsville, AL 35801
(205) 881-9235
ARIZONA
1002
Hamllton/Avnet Electronics
30 S. McKemy Ave.
Chandler, AZ 85228
(6fr2) 901-6400
1155
Hamilton Electro Sales
1381-B West 190th Street
Gardena, CA 90248
(213) 217-8700
CAUFORNIA
1179
Image Electronics
5310 Darry Ave., Unit X
Agoura, CA 91301
(818) 707'()911
1190
Marshall Industries
1 Morgan Avenue
Irvine, CA 92710
(714) 859-5050
1158
Marshall Industries
9710 De Soto Avenue
Chatsworth, CA 91311
(818) 407-4100
1145
Hamllton/AYnet
9650 De Soto Avenue
Chatsworth, CA 91311
(818) 700-6500
1194
Marshall Industries
336 Los Coche. Street
Milpitas, CA 95035
(408) 942-4600
1004
AYnet Electronics
350 McCormick
Costa Mesa, CA 92626
(714) 754-8111
TWX: 910 595-2638
1198
Hamllton/AYnet Electronlea
3002 East G. Street
Ontario, CA 91764
(714) 989-4802
1005
1172
Marshall Industries
3039 Kilgore Avenue, #140
Rancho Cordova, CA 95670
(916) 635-9700
Hamilton Electro Sales
3170 Pullman Street
Costa Mesa, CA 92626
(714) 641-4100
1167
Marshall Industries
9930 So. 51st Street
Ste. B121
Phoenix, AZ 85044
(602) 498-0290
San Diego, CA 92123
(619) 571-7510
TWX: 910 335-1216
1173
Marshall Industries
10105 Carroll Canyon Rd.
San Diego, CA 92131
(619) 578-9600
1178
Western Mlcrotechnology Inc.
12900 Saratoga Avenue
Saratoga, CA 95070
(408) 725-1660
FAX: (408) 255-6491
TWX: 910 338-0013
1008
TWX: 910 950-0077
FAX: (602) 981-4555
1007
Hamllton/Aynet Electronlea
4545 Viewridge Avenue
1159
Marshall Induatrles
9874 Telstar Avenue
EI Monte, CA 91731
(818) 459-5500
1092
Hamllton/AYnet Electronlea
4103 Northgate Blvd.
Sacramento, CA 95834
(916) 925-2216
A-2
1175 Bordeaux Drive
Sunnyvale, CA 94086
(408) 743-3355
TWX: 910 339-9332
1152
Imege Electronics
1342 Bell Avenue
Tustin, CA 92880
(714) 259'()900
SALES REPRESENTATIVE-UNITED STATES/CANADA (cont'd)
IDAHO
Quorum 3
(See Salt Lake City, Utah)
ILLINOIS
2006
LTD Technologies Inc.
810 Arlington Heights Rd.
Itasca, IL 60143
(312) n3-2900
TWX: 332415
FAX: (312) n3-0358
INDIANA
MASSACHUSETTS
2012
Kitchen & Kutchln, Inc.
87 Cambridge St.
Burlington, MA 01803
(617) 229-2660
FAX: (617) 273-5895
NEVADA
Criterion Sales Inc.
(See Santa Clara, California)
NEW HAMPSHIRE
Kitchen & Kutchln, Inc.
(See Bu~ington, Massachusetts)
MICHIGAN
2011
R.O. Whitesell & Associates
8332 Office Park Dr., Ste. A
Grand Blanc, MI 48439-2035
(313) 695-0770
NEW JERSEY (NORTH)
2043
PAF Associates
508 Main Street
Boonton, NJ 07005
(201) 335-0660
2008
Robert O. Whitesell & Associates
6691 E. Washington Street
P.O. Box 19904
Indianapolis, IN 46219-0904
(317) 359-9283
TWX: 810 341-3320
FAX: (317) 359·2091
ESL: 62818996
2009
Robert O. Whltesall & Associates
1800 S. Plate, Ste. A
Kokomo, IN 46902-5730
(317) 457-9127
FAX: (317) 456-1234
IOWA
2070
Dy-Tronlx Inc.
23 Twixt Town Rd. N.E., Ste. 201
Cedar Rapids, IA 52402-3297
(319) 3n-8275
FAX: (319) 3n-9163
KANSAS
2081
Dy-Tronlx Inc.
1999 Amidon, Ste. 322
Wichita, KS 67203-2124
(316) 838-0684
ESL: 62914257
KENTUCKY
2082
Robert O. Whltesall & Associates
313 Lagrange Rd., Ste. 201
P.O. Box 797
Pewee Valley, KY 40056-9999
(502) 241-1441
LOUISIANA
Norcom. Inc.
(See Dallas, TX)
MAINE
Kltchen & Kutchln, Inc.
(See Burlington, Massachusetts)
MARYLAND
Beacon North
(See Ste~lng, Virginia)
2013
Robert O. Whlte..11 & Asaoclates
688 Cascade West Parkway S.E.
Grand Rapids, MI 49506-2187
(616) 942-5420
2014
Robert O. Whitesell & Associates
18444 W. 10 Mile Rd.
Southfield, MI 48075-2858
(313) 559-5454
TWX: 510601-2458
FAX: 313-559-9643
2015
R.O. Whitesell & Assoclatea
1822 Hilltop Rd.
St. Joseph, MI 49085-2307
(616) 993-7337
NEW JERSEY (SOUTH)
2017
Naudaln Assocletes
The PaVIlions at Greentree
Route 73, Ste. 307
Marlton, NJ 06053
(609) 983-5300
FAX: (609) 596-5367
NEW MEXICO
2018
Rap New Tec
9219 Lagrima De Oro Rd., N.E.
Albuquerque, NM 87111
(505) 293-2582
2023
Robert O. Whltesall & Asaoclates
6000 West Creak Rd., Ste. 21
Cleveland, OH 44131-2139
(216) 447-9020
TWX: 810 427-2211
FAX: 216-447-0280
2024
Robert O. Whitesell & _ _
6161 Busch Blvd., Ste. 304
Columbus, OH 43229-2589
(614) 868-9396
FAX: 614-886-8792
2025
Robert O. Whltesall & Asaoclates
4133 South Dixie Avenue
Dayton, OH 45439-2192
(513) 299-9546
TWX: 510801-2416
FAX: (513) 298-2568
OREGON
2079
Weeterberg Asaoc., Inc.
7185 S.W. Fir Loop
Portland, OR 97223
(503) 620-1931
FAX: (503) 684-5376
PENNSYLVANIA (EAST)
Neudeln Asaoclates
(See Marlton, New Jersey)
NEW YORK
2048
Ossman Aaaoc.
6666 Old Coliamer Rd.
East Syracuse, NY 13057
(315) 437-7052
FAX: (315) 437-2332
MINNESOTA
20n
Electronic Innovators, Inc.
9727 Valley View Rd.
Eden Prairie, MN 55344
(612) 941-0830
FAX: (612) 941-6193
MISSISSIPPI
Robert O. Whlte..11 & Asaoclates
(See Huntsvilie, Alabama)
MISSOURI
2088
Dy-Tronlx Inc.
2020
PAF Associate.
120 W. Main Street
Smithtown, NY 11787
(516) 360-0940
FAX: 516-979-8506
NORTH CAROLINA
2021
Quantum Marketing, Inc.
6608 Six Forks Road, Ste. 203
Raleigh, NC 27615
FAX: 919-847-6271
(919) 846-5728
3407 Bridgeland Drive
Bridgeton, MO 63044
(314) 291-4777
FAX: (314) 291-3861
MONTANA
2067
NORTH DAKOTA
Electronic Innovators
(See Eden Prairie, Mn)
Simpson & Assoc., Inc.
2552 Ridge Rd. #200
Littleton, CO 80120
(303) 466-7777
FAX: 303-460-0628
OHIO
2022
Robert O. Whitesell & Asaoclates
1172 West Galbraith
Cincinnati. OH 45231-5687
(513) 521-2290
FAX: 513-521-6016
NEBRASKA
Dy.Tronlx Inc.
(See Cedar Rapids, Iowa)
(See Bridgeton, Missouri)
A-3
PENNSYLVANIA (WEST)
R.O. Wh_II & Assoc.
(Sea Indianapolis, Ind.)
2019
Beacon North
637 B~dge Street
Collegeville, PA 19426
(703) 478-2480
2028
Robert O. Whltesall & _etes
1360 Old Freeport Rd., Ste. l-B
Pittsburgh, PA 15236-3183
(412) 963-6161
RHODE ISLAND
Kitchen & Kutchln, Inc.
(See Bu~ington, Massachusetts)
SOUTH DAKOTA
Electronic Innovators
(See Eden Prairie. Mn.)
TENNESSEE
2029
Robert O. Whitesell & Assocletes
9208 Kingston Pike
Knoxville, TN 37022-2317
(615) 694-9476
FAX: 615-691-9693
TEXAS
2031
Norcom, Inc.
8705 Shoal Creek Blvd., $te. 109
AusUn, TX 78758
(512) 451-2757
FAX: 512 451-8031
INDUSTRIAL DISTRIBUTORS-UNITED STATES/CANADA (continued)
COLORADO
1185
Marshall Industries
12351 N. Grant
Thornton, CO 80241
(303) 451-8444
FAX: (303) 457·2899
1009
Hamllton/Avnet Electronics
9605 Maroon Cr., Suite 200
Englewood, CO 80112
(303) 799-7814
TWX: 910 935·0787
CONNECTICUT
1011
HamlRon/Avnet Electronics
Commerce Industrial Park
Commerce Drive
Danbury, CT 06810
(203) 797·2800
TWX: 710 456-9974
1012
J. V. Electronics
690 Main Street
East Haven, CT 06512
(203) 469-2321
1182
Marshall Industries
20 Sterling Drive
Barnes Ind. Park, N.
Post Office Box 200
Wallingford, CT 06492
(203) 265·3622
1026
Alma ElectronicS
31 Village Street
Wallingford, CT 06492
(203) 269-6801
FLORIDA
1013
Hamllton/Avnet ElectroniCS
6801 N.W. 15th Way
Fort Lauderdale, FL 33309
(305) 971·2900
TWX: 510 956-3097
1186
Marshall Industries
2700 W. Cypress Creek, Ste. Cl06
FI. Lauderdale, FL ;,a309
(305) 977-4880
1087
Reptron
3~20 N.W. 53-rei $tr$$f:
FI. Lauderdale, FL 33309
(305) 735-1112
FAX: (305) 735·1121
1165
Marshall Industries
360 S. Northlake Blvd., #1024
AIIamonte SPG, FL 32701-5260
(305) 841·1878
1014
Hamllton/Avnet ElectroniCS
3197 Tech Dr. North
SI. Petersburg, FL 33702
(813) 229·7010
TWX: 810663·0374
INDIANA
1036
HamlRon/Avnet Electronics
485 Gradle Drive
Carmel, IN 46032
(317) 844·9333
TWX: 810 260-3966
MASSACHUSETTS
1109
Alma Electronics
60 Shawmut Rd.
Canton, MA 02021·1410
(617) 821·1420
1018
1035
Marshall Industries
Advent Electronics
2840 Scherer Dr., Ste. 410
SI. Petersburg, FL 33702
(813) 576·1399
8446 Moller Road
Indianapolis, IN 46268
(317) 872-4910
1019
Reptron
14501 McCormick Drive
Tampa, FL 33625
(813) 855-4656
1189
Marshall Industries
6990 Corporate Drive
IndianapOliS, IN 46278
(317) 297·0483
1146
HamlRon/Avnet Electronics
6947 UniversIty Blvd.
Winter Park, FL 32792
(305) 628-3868
IOWA
1086
Advent Electronics
682 58th Avenue, CT S. W.
Cedar Rapids, IA 52404
(319) 363-0221
GEORGIA
1015
Hamllton/Avnet Electronics
58250 Peachtree Corner E.
Norcross, GA 30092
(404) 447·7500
TWX: 810 776·0432
1065
1115
Hamllton/Avnst
1().O Centennial Or.
Peabody, MA 01960
(617) 531·7430
1084
Future Electronics
133 Flanders Rd.
Westboro, MA 01581
(617) 366·2400
1116
Marshall Industries
33 Upton Dr.
Wilmington, MA 01887
(617) 658-0810
Hamilton/Avnet
915 33rd Ave., S.W.
Cedar Rapids, IA 52404
(319) 362-4757
KANSAS
1191
Marshall Industries
8321 Melrose Dnve
Lenexa, KS 68214
(913) 492-3121
1176
Marshall Industries
5300 Oakbrook Pkwy., #140
Norcross, GA 30093
(404) 923-5750
FAX: (404) 923-2743
1037
HamlltonJAvnet Electronics
1174
Quality Components
6145 Northbelt Pkwy., Ste. B
Norcross, GA 30071
(404) 449-9506
FAX: (404) 449·0275
9219 Quivira Road
OvMand, KS 66215
(913) 888-8900
TWX: 910 743·0005
MARYLAND
1039
Hamllton/Avnet Electronics
6822 Oak Hall Lane
ColumbIa, MD 21045
(301) 995·3500
FAX: 301·995-3593
ILLINOIS
1016
Advent Electronics
7110·16 N. Lyndon Street
Rosemont, IL 60018
(312) 296-4210
1017
HamlRon/Avnet Electronics
1130 Thorndale Avenue
Bensenviiie, iL 60108
(312) 860-8522
TWX: 910 227-0060
1180
Marshall Industries
1261 Wiley Road #F
Schaumburg, IL 60195
(312) 490-0155
A-4
MICHIGAN
1043
Advent Electronics
24713 Crestview CI.
Farmington HIlls, MI. 48018
(313) 477·1650
1077
Hamllton/Avnet
2215 29th St., S.E. A·5
Grand Rapids, M149508
(616) 243-8805
TWX: 810 273-6921
1044
Hamilton/Avnet Electronics
41650 Gardenbrook, Suite 100
Novi, MI 46050
(313) 347-4270
FAX: (313) 347-4021
1161
Marshall Induetrles
2221 Broadblfch Dr., SUIte G
Silver Springs, MD 20904
FAX: (301) 622-0451
(301) 622·1118
1162
Marshall Industries
31067 Schoolcraft
Livonia, MI 48150
(313) 525·5550
1075
Alma Electronics Corp.
Electronics
8309B Sherwick Court
Jessup, MD 20794
(301) 953-2568
FAX: 301·953-0039
1021
Reptron
34403 Glendale Rd.
Post Office Box 2768
Livonia, MI 48150
(313) 525·2700
INDUSTRIAL DISTRIBUTORS-UNITED STA TES/CANADA (continued)
MINNESOTA
1127
VOYllller Electronics Ccrp.
5201 E. River Rd .• Suite 303
Fridley, MN 55421
(612) 571·7766
1166
Marshall Industries
158 Gaither Dr.
MI. Laurel, NJ 08054
(609) 234·9100
FAX. 609·778·1819
1171
Marshall Industries
1250 Scottsville Rd.
Rochester, NY 14624
(716) 235·7620
FAX: 716·235.()O52
1047
HamlHon/Avnet Electronics
12400 Whitewater Drive
Minnetonka, MN 55343-9421
(612) 932-0600
TWX: 910 576-2720
1126
General Components Inc.
245·D Clifton Ave.
West Berlin, NJ 08091
(609) 768-6767
FAX: 609-768-3649
103 TWin Oaks Dr.
Syracuse, NY 13206
(315) 437-2641
FAX: 315-432-0740
1163
Marshall Industries
3955 Annapolis Ln.
Minneapolis, MN 55447
(612) 559-2211
NEW MEXICO
1175
1023
Hamllton/Avnet Electronics
NORTH CAROLINA
1027
Hamllton/Avnet Electronics
3510 Spring Forest Rd.
Raleigh, NC 27604
(919) 878.()610
TWX: 510928-1836
Hamllton/Avnet Electronics
2524 Baylor Dr. S.E.
Albuquerque, NM 87106
(505) 765-1500
TWX: 910 989.()614
MISSOURI
1046
HamlHon/Avnet Electronics
13743 Shoreline Ct.
Earth City, MO 63045
(314) 344-1200
TWX: 910 762-0664
NEW HAMPSHIRE
1049
HamlHon/Avnet Electronics
444 E. Industrial Park Dr.
Manchester, NH 03103
(603) 624-9400
TWX: 910 762.()664
NEW JERSEY
1020
HamlRon/Avnet ElectroniCS
1 Keystone Ave., Bldg. 36
Cherry Hill, NJ 08003
(609) 424-0110
FAX: 609-751-2552
1079
Almo
12 Ccnnerty Court
East Brunswick, New Jersey 08816-1633
(201) 613-0200
(800) 523-3155
FAX: 201-613-9689
1170
Marshall Industries
5221 North Blvd
Raleigh, NC 27604
(919) 878-9882
NEW YORK
1114
Semlspeclallsts of America
105 Baylis Rd.
Melville, NY 11747
(516) 293-2710
FAX: (516) 293-2707
1201
Quality Ccmponents
2940-15 Trawick Rd.
Raleigh, NC 27604
(919) 876-7767
1025
Hamilton/Avnet Electronics
933 Motor Parkway
Hauppauge, LI, NY 11788
(516) 231-9600
FAX: 516-434-7426
OHIO
1028
Hamllton/Avnet Electronics
30325 Bainbridge Rd., Bldg. A
Cleveland, OH 44139
(216) 631-3500
TWX: 810427-9452
1192
Marshall Industries
275 Oser Ave
Hauppauge, LI, NY 11788
(516) 273-2424
FAX. 516-434-4775
1029
Hamilton/Avnet Electronics
954 Senate Dr.
Dayton, OH 45459
(513) 439-6700
TWX: 810450-2531
1193
Marshall Industries
129 Brown 51.
Johnson City, NY 13790
(607) 798-1611
FAX: 607-797-7031
1184
Marshall Industries
3520 Park Center Drive
Dayton, OH 45414-2573
(513) 236-6088
1024
1078
HamlHon/Avnet Electronlca
10 Industrial Rd.
Fairfield, NJ 07006
(201) 575-3390
FAX: 201-575-5639
1164
Marshall Industrle.
101 Fairfield Rd. Fairfield,
(201) 862-0320
FAX: 201-882-0095
NJ 07006
Hamliton/Avnet Electronics
2060 Town Line Road
Rochester, NY 14623
(716) 475-9140
FAX' 718-475-9119
1181
Marshall Industries
30325 Bainbridge Rd., Bldg. A
Solon, OH 44139
(216) 349-5100
1175
Future Electronics
7453 Morgan Road
Liverpool, NY 13090
(315) 451-2371
FAX: 315-451-7258
1133
Hamllton/Avnet Electronics
777 Brooksedge Blvd.
Westerville, OH 43081
(614) 882-7004
A-S
OKLAHOMA
1117
Hamilton/Avnet Electronlca
12121 E. 51st Street
Ste.l02A
Tulsa, OK 74146
(918) 252·7297
1113
Quality Components, Inc.
3158 So. 108th East Ave.
Ste.274
Tulsa, OK 74146
(918) 664-8812
OREGON
1150
Western Micro Technology
13770 S.W. 24th
Beaverton, Or 97005
(503) 629-2082
1169
Marshall Industries
9705 SW Gemini Dr.
Beaverton, OR 97005
(503) 644-5050
1032
Hamllton/Avnet Electronics
6024 S.W. Jean Rd.
Bldg. C, Ste. 10
Lake Oswego, OR 97034
(503) 635-6157
TWX: 910 455-6179
PENNSYLVANIA
1034
Almo Electronics
9615 Roosevelt Blvd.
Philadelphia, PA 19114
(215) 696-4000
FAX: (215) 969-6768
1157
Hamllton/Avnet
2800 Liberty Ave., Bldg. E
PiUsburgh, PA 15222
(412) 281-4150
1168
Marshall Industries
701 Alpha Dr., Ste. 240
PiUsburgh, PA 15236
(412) 963-0441
TEXAS
1110
Quality Components Inc.
Electronics
4257 Kellway Circle
Addison, TX 75001
(214) 733-4300
TWX: 910 960-5459
1050
Hamllton/Avnet Electronics
1807-AW. Braker Lane
Austin, TX 78758
(512) 837-8911
TWX: 910 874-1319
INDUSTRIAL DISTRIBUTORS-UNITED STATES/CANADA (continued)
1177
Marshall Industrtes
8504 Cross Park Dr
Austin, TX 78754
(512) 837-1991
1112
Quality Components, Inc.
2120-M Baker Ln.
Austin, TX 78758
(512) 835-0220
TLX: 324930
WISCONSIN
1061
Hamllton/Avnet Electronics
20875 Crossroads Circle, SUite 400
Waukesha, WI 53186
(414) 7844510
TWX: 910 262-1182
UTAH
1059
Hamilton/Avnet Electronics
1585 West 2100 South
Salt Lake City, UT 84119
(B01) 972-2800
TWX: 910 9254017
1062
Marshall Industries
20900 Swenson
Waukesha, WI 53186
1058
Marshall Industries
466 Lardale Dr., Ste. C
Sail La e City, UT 84115
(801) 4 5-1551
Mississauga, Ontano
Canada L4V lR2
(416) 677-7432
1064
HamlHon/Avnet Electronics
190 Colonnade Rd.
Nepean,Ontairo
canada K2E 7J5
(613) 226-1700
TWX: 0534971
1066
CANADA
Hamilton Avnet
2550 Boundary Rd., #115
1183
Marshall Industries
2045 Chenault
Carrollton, TX 75006
(214) 233-5200
Burnaby, Bntish Columbia
Canada V5M 3Z3
604-437-6667
WASHINGTON
1060
Hamllton/Avnet Electronics
17761 NE 78th PI
Redmond, WA 98005
(206) 881-6697
1091
Hamilton/Avnet ElectroniCS
2816 21sl. N.E.
Calgary, Alberta
Canada T2E 6Z2
(403) 250-3566
TWX: 03-827642
1187
Marshall Industries
7250 Langtry
Houston, TX 77040
(713) 895-9200
1052
Hamllton/Avnet Electronics
2111 W. Walnut HIli Ln.
Irving (Dallas), TX 75062
(214) 550-7755
TWX: 910 860-5929
1063
Hamllton/Avnet Electronics
6845 Rexwood Rd., Units 3-5
1175
Marshall Industr1es
11715 N. Creek r
Parkway South #112
Bothwell, WA 98011
(206) 486-5747
FAX: (206) 486-6964
1072
Future Electronics Inc.
1695 Boundary Rd
Vancouver, British Columbia
Canada V5K 4X7
(604) 294-1166
TLX. 04-354744
FAX: (604) 294-1206
1070
Future Electronics Inc.
Baxter Center
1050 Baxter Rd.
Ottawa, Ontario
Canada K2C 3P2
(613) 820-8313
TWX: 610 563-1697
FAX: (613) 820-3271
1080
Future Electronics Inc.
237 Hymus Blvd.
POinte Claire, Quebec
Canada H9R 5C7
(514) 694-7710
FAX: (514) 695-3707
TLX: 05-823554
1081
1053
Hamilton/Avent Electonlcs
4850 Wright Rd.
Stafford, TX 77477
(713) 240-7898
1149
Western Micro Technology Inc.
14636 N.E 95th Street
Redmond, WA 98052
(206) 881-6737
A-6
Future Electronics Inc.
82 Saint Regis Crescent North
Downsvlew, Ontario
Canada M3J 1Z3
(416) 6384771
TWX: 610491-1470
FAX: (416) 638-2936
1065
Hamilton/Avnet Electronics
2795 Halpern
SI. Laurent
Montreal, Quebec
Canada H4S 1P8
(514) 335-1000
ROCKWELL SEMICONDUCTOR PRODUCTS SALES OFFICES-INTERNATIONAL
You can obtain expert applications assistance, price quotations and delivery data from the Distributors and Sales Representatives
listed below for Rockwell semiconductor and telecommunication products. If there is no Rockwell distributor convenient to your
country, pleese consider HamiitonlAvnet Intemational listed below.
EUROPE AND IIIDDLE EAST
Africa
0208
South Continental DevI_
(PTY) Ltd.
P.O. Sox 56420
Plnegowklg 2123. South Africa
or:
0209
Soulh ContInental DevI_
5th Floor. RandoVer House
Dove Street
Randburg. South Africa
AustrIa
0228
W, 11_ GEI.II,B,H.
Lsmezan_l0
1232 Wlen
Austria
(43) 0222-61062
TLX: 0135701 moor a
FAX: 43-0222-61062151
Bllglum
0272
III_ron
Generaal Dewittelaan 7,
2600 Mechelen
Belgium 2600
(32) 15-21-2223
TLX: 846-22806 mltron b
Denmark
0244
Mlcronor API
Torvet 1
6800 Slikeborg
Denmark
(45-6) 815510
TLX: 63245 MICRONOR DK
Finland
0252
Set! Electronics OV
AiaporttI IC
02210 Espoo
Finland
(358) 0-7555133
TLX: 124670 ELDVN SF
France
0222
SyetamCo_
88, Avenue du G~ de Gaulle
67200 Eckbolehelm
France
Phone: (33) 88782089
TLX: 690268 SYBCO
0223
Alfatronlc
Z.I. DeCourtaboeuf
7, Av. Du Canada
B.P.310
F-91958 Lea Ulis Cad..
France
(33-1) 47917400
TLX: ALFA812 790F
FAX: (33-1) 47939774
Holland
2087
Alcom Electronic. BY
Esse Baan 1
Pcstbus 358. 2908 AJ
Capelle NO Ijssel
HoIlsnd
(31-10) 4519-533
TLX: 26160
India
4088
Semiconductor Comp.... Limited
Phsse VIII. S.A.S., NAGAR-I60059
(near Chsndlgarh)
Punjab, India
87265, 87809, 87585
TLX: 395270 LSI
11. .1
0255
Bynet DatI Communlc8Uone
II-Hanechoshet St.
Ramat-Hachayal
Tel-Aviv 69710, Israel
TLX: 342132
FAX: (972) 3-475933
Italy
0280
lIurata Elettronlca
Via Melchlorra GiOia, 69
T-20125 Milano, Italy
(39-2) 807-3798
(39-2) 888-'1833
TWX: 330385
0246
Dolt, lng, Gluseppa De IlIeo S,P.A,
Via Vittorio, Veneto 8,
20080 Cassina
De 'Pecchi
Italy
(39-2) 952-0551
TLX: 330889
FAX: (38-2) 952-2227
Norway
0271
BIt Elektronlkk A.S:
Poatboks 38
3401 Ller, Norway
(03) 84-70-99
FAX: (03) 84-55-10
Spain
0238
Comella SA,
EmIlio Munoz 41
ESC I, Planta I, Nave 1-1-2
Madrid 17, Spain
(34-1) 754-3001
TLX: 42007 CETA E
FAX: (341) 754-2151
~
0235
Setoma Component AS
Box 1279
17124 Solna, Sweden
(411-8) 8200
FAX: (411-8) 734-8200
0236
Setome Compo_ A.B,
Norra Gubberogatan 32
41882 Gothenburg
Sweden
(46-31) 646450
FAX: (46-31) 215125
A-7
SwItzarIand
02Z1
Aumann. Co. loG
Foerrllbuckslr. 150
CH-8037 Zurich
Switzerland
(41-1) 443-300
TLX: 822 966
U_KlrvJ0258
R.C.S. IIlcroaystam. Ltd.
141 Uxbridge Rd.
Hampton Hili, Middlesex
lW12 1BL, England
(01) 979-2204
TLX: 8951470 RCS MICG
FAX: 01-979-6910
0280
Abacul Electronics PLC
Abacus House
Bone Lsne, Newbury
Berkshlra, RG14 5SF, England
(0635) 306BO
TLX: 849343
West Germany
0250
BIt-Electronic loG
DlngoJIingerstr. 6
D-6OOO Muenchen BO, Germany
(49-89) 41 8007-0
TLX: 5212931 bit d
0238
Kontron Halblelta.
AIfatron GmbH
Schlelsshelmer Street 87
6046 Garching, Germany
(069) 32-90-99-0
TLX: 5216935
FAX: (069) 32-90-99-59
0245
Unltronlc GmbH
Munateralr. 338
P.O. Box 330 429
4000 Dusseldorf 30, W. Germany
(46-211) 626384-67
TLX: 8588434 unld d
0237
_nlc GlnbH
Winzeratr 47d.
8000 Muenchen 40
Munich, W. Germany
(49-69) 309031
TLX: 5216187 aatrd
FAR EAST AND ASIA PACIFIC
AuetraIIaIN. . Zeeland
4054
VSI EIectronIca
Ply. Ltd. (Australia)
16 Dickson Avenue
Artarmon, NSW 2084 Australia
(61-2) 439-<4655
FAX: (81-2) 439-6435
TLX: AA-22646
0281
VSI Electronics Ltd, (N,Z,)
Private Bag, New Market,
7 Beasley Ave.
Penrose.
Auckland, New Z8a1and
(84-9) 599150
FAX: (84-9) 693884
TLX:NZ80340
Hong KlIng
208S
Telecomp Electronics Ltd.
1702 Bank Cen1ra
l13li Nathan Rd.
Kowloon, Hong Kong
(852-3) 880629
TLX: 38513 TEKHL
FAX: (852-3) 7805871 or 7109220
0265
Gr8ndeu. Trading Company
4IF, Cheong Tal Fly. Bldg.
16 Tal Vau Street
Kowloon, Hong Kong
Japan
0269
Kanematau Semlc_. Corp.
6-1 Shintoml 1 choma
ChucH
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