1989_SGS_Modem_Databook_and_Applications 1989 SGS Modem Databook And Applications
User Manual: 1989_SGS_Modem_Databook_and_Applications
Open the PDF directly: View PDF 
.
Page Count: 802
| Download | |
| Open PDF In Browser | View PDF |
11
~
INTEGRATED
TECHNICAL
SALES
I
2620 Augustine Drive,
Suite 210
Santa Clara, CA 95054
(408) 727 -3406
Fax: (408) 727-5717
MODEM
DATABOOK & APPLICATIONS
1st EDITION
MAY 1989
USE IN LIFE SUPPORT MUST BE EXPRESSLY AUTHORIZED
SGS-THOMSON' PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF SGS-THOMSON
Microelectronics. As used herein:
1. Life support devices to systems are devices or systems
which, are intended for surgical implant into the body
to support or sustain life, and whose failure to perform,
when properly used in accordance with instructions for
use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be
reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
TABLE OF CONTENTS
INTRODUCTION
Page
4
ALPHANUMERICAL INDEX
6
PRODUCT SELECTOR
8
MODEM DATASHEETS
11
MODEM APPLICATION SUPPORT
379
POWER SUPPLY MODULE
545
DSP DATASHEETS
551
DSP APPLICATION SUPPORT
723
3
INTRODUCTION
SGS-THOMSON MODEM ICs:
A COMMITMENT TO EXCELLENCE
SGS-THOMSON Microelectronics has
been a key player in the modem IC market for a long time, accumulating expertise in developing public telephone
network modems - V.23, V.22bis, V.32
and others - and exploiting strong manufacturing resources to produce them
in quantity.
For this market the company employs
technologies that are ideally suited to mixed analog/digital circuits, from a 3 micron double poly to 1.2 micron double
metal CMOS processes allowing switched capacitor filtering and high density
logic.
Active in a broad spectrum of telecom
applications, SGS-THOMSON's design
and manufacturing engineers have experience in leading-edge circuits such as
the ISDN echo canceller and S Interface transceivers. Moreover, the company
is unique in combining expertise in analog conversion and filtering circuits exemplified by the Analog Front Ends and in digital signal processing techniques such as automatic adaptive equalization, digital filter carrier recovery and
echo cancellation.
In addition to Modem ICs, this databook
includes a family of general purpose
DSPs that are used in modem datapump
design and other telecom applications.
4
v. 32 - With the SGS-THOMSON TS7532 kit you
can build a V. 32 datapump with less than 10 chips.
The Kit consist of three DSPs and three Analog
Front End ICs.
To simplify application software development the DSP family is supported by powerful development tools, including
emulators, EPROM modules, cross assemblers simulators, and even a C compiler. Thanks to this set of tools, the users
may adapt the SGS-THOMSON application software to suit their own specific
needs.
INTRODUCTION
YOUR PARTNER FOR CUSTOMIZED
MODEM ICs
SGS-THOMSON Microelectronics has a
long history of close cooperation with
major customers in the development of
modem les, putting the company in an
enviable situation for the definition of
new dedicated or custom products for
this market. This capability is further enhanced by the combination of analog and
digital functions on the same chip that is
permitted by new generation technologies.
This databook may contains the solution
you are looking for, but if you have new
ideas or a highly specific application contact SGS-THOMSON to discuss customized solutions.
Development support - SGS-THOMSON's: Digital Signal Processor (DSP) family is supported by a com• prehensive range of hardware and software development tools.
5
ALPHANUMERICAL INDEX
Function
Page
Number
EF791 0
V.21N.23 FSK Modem .............................. .
13
EFRMAFE
TS6895C/51/52 Evaluation Board ..................... .
381
GS-MS1212
Modem Board Power Supply ......................... .
547
ST18930EMU
Emulation Development Board ........................ .
725
ST18930EPR
EPROM Emulator .................................. .
729
ST18930HDS
Hardware Development System ....................... .
731
ST18930LlB
Software Routine Library ............................ .
735
ST18930SP
Software Package .................................. .
737
ST18930SPC
C Compilar Package ................................ .
743
ST18930/31
Digital Signal Processor ............................. .
553
ST18940/41
Digital Signal Processor ............................. .
619
TS7513
Single Chip Asynchronous FSK Modem ................ .
45
TS7514
Programmable V.23 Modem with DTMF ................ .
61
TS7514EVA
TS7514 Evaluation Board ............................ .
385
TS7515
Single Chip DPSK and FSK Modem ................... .
83
TS7515EVA
TS7515 Evaluation Board ............................ .
387
TS7524
V.22bis, V.22, Bell 212, V.21, V.22, Bell 103 Modem Chipset
101
TS7524EVA
V.22bis Evaluation Board ............................ .
389
. V.32 Modem Chipset ............................... .
137
TS7532DEMO
V.32 Demo Board .................................. .
391
TS7532DPUMP
V.32 Data Pump ................................... .
393
TS7542
Multimode Modem Analog Front End .................. .
181
TS7542EVA
Modem Analog Front and Evaluation Board ............. .
395
TS75C25
V.22bis, V.22, Bell 212, V.21, V.22, Bell 103 Modem Chipset
217
TS75C32
V.32,V.22bis,V.22,V.23,V.21 ,Bell 212,Bell 103 Modem Chipset
255
TS68930EMU
Emulation Development Board ........................ .
745
TS68930EPR
EPROM Emulator .................................. .
749
Type
Number
TS7532
6
ALPHANUMERICAL INDEX
Function
Page
Number
TS68930HDS
Hardware Development System ........................
753
TS68930LlB
Software Routine Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
757
TS68930SP
Software Package ...................................
759
TS68930SPC
C Compiler Package .................................
765
TS68930/31
Digital Signal Processor ..............................
669
TS68950
Modem Transmit Analog Interface ......................
301
TS68951
Modem Receive Analog Interface ......................
319
TS68952
Modem Transmit/Receive Clock Generator ...............
349
TS75320
Digital Echo Canceller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
367
Type
Number
7
PRODUCT SELECTOR
HIGH SPEED MODEMS
Type
Number
TS75C32
TS7532
TS75320
TS75C25
TS7524
Description
Page
V.32, V.22bis, V.22, V.23, V.21, Bell 212, Bell 103 Modem chipset
V.32 Modem Chipset ........................................
255
137
Digital Echo Canceller .......................................
V.22bis, V.22, Bell 212, V.21, V.22, Bell 103 Modem Chipset .......
V.22bis, V.22, Bell 212, V.21, V.22, Bell 103 Modem Chipset .......
367
217
101
ANALOG FRONT ENDS
Type
Number
TS7542
TS68950
TS68951
TS68952
Description
Page
Multimode Modem Analog Front End ...........................
Modem Transmit Analog Interface .............................
Modem Receive Analog Interface ...............................
Modem Transmit/Receive Clock Generator ......................
181
301
319
349
SINGLE CHIP MODEMS
Type
Number
TS7515
TS7514
TS7513
EF7910
Description
Page
Single Chip DPSK and FSK Modem ............................
Programmable V.23 Modem with DTMF .........................
Single Chip Asynchronous FSK Modem .........................
V.21IV.23 FSK Modem .......................................
83
61
45
13
MODEM APPLICATIONS SUPPORT
Type
Number
Description
Page
TS7532DEMO
TS7532DPUMP
TS7524EVA
TS7542EVA
TS7515EVA
TS7514EVA
EFRMAFE
V.32 Demo Board ............................................
V.32 Data Pump ............................................
V.22bis Evaluation Board .....................................
Modem Analog Front and Evaluation Board ......................
TS7515 Evaluation Board .....................................
TS7514 Evaluation Board .....................................
TS68950/51/52 Evaluation Board ..............................
391
393
389
395
387
385
381
Using the TS75320 Echo Canceller in V.32 Modems (AN341)
Interfacing the TS7524 Modem Chipset to a Communication Control Processor (AN342)
Using TS7515 Single Chip V.22/BeIl212A Modem Around 80C51 Microcontroller (AN343)
How to Establish a Connection with an Unknown Modem Using CCITT V.22 Modem (AN344)
Application Guide to the Use of the TS7515 Single Chip FSK and DPSK Modem (AN345)
TS7513 V.23 Modem Principle and Applications (AN346)
A very low cost and powerful solution for V.23 application: TS7514 (AN349)
8
397
427
443
447
451
515
533
PRODUCT SELECTOR
POWER SUPPLY MODULE
Type
Number
GS-M51212
Description
Page
13W Triple Output DC-DC Converter Module .....................
547
DIGITAL SIGNAL PROCESSORS
Type
Number
ST18940/41
ST18930/31
TS68930/31
Description
Page
Digital Signal Processor ......................................
Digital Signal Processor ......................................
Digital Signal Processor ......................................
553
669
619
DSP APPLICATIONS SUPPORT
Type
Number
ST18930HDS
ST18930EMU
ST18930EPR
ST18930SPC
ST18930SP
ST18930LlB
TS68930HDS
TS68930EMU
TS68930EPR
TS68930SPC
TS68930SP
TS68930LlB
Description
Page
Hardware Development System ...............................
Emulation Development Board ................................
EPROM Emulator ...........................................
C Compiler Package .........................................
Software Package ...........................................
Software Routine Library .....................................
Hardware Development System ...............................
Emulation Development Board ................................
EPROM Emulator ...........................................
C Compiler Package .........................................
Software Package ...........................................
Software Routine Library .....................................
731
725
729
743
737
735
753
745
749
765
759
757
Interfacing SGS-THOMSON DSP with Analog Front Ends (AN347)
Application Notes Summary (AN348)
767
797
9
MODEM DAT ASHEETS
11
EF7910
V.21 / V.23 FSK MODEM
• COMPLETE FSK MODEM - JUST ADD LINE
INTERFACE
• COMPATIBLE WITH BELL 103/113/108, BELL
202, CCITI V.21 , CCITI V.23 SPECIFICATIONS
• NO EXTERNAL FILTERING REQUIRED
• ALL DIGITAL SIGNAL PROCESSING, DIGITAL
FILTERS AND ADCIDAC INCLUDED ON-CHIP
• INCLUDES ESSENTIAL RS-232/CCITI V.24
HANDSHAKE SIGNALS
• AUTO-ANSWER CAPABILITY
• LOCAL COPYITEST MODES
• 1200 BPS FULL DUPLEX ON 4-WIRE LINE
• PIN-PROGRAMMABLE MODE SECTION
P
DIP28
(Plastic Package)
J
DESCRIPTION
The EF7910 is a single-chip asynchronous Frequency Shift Keying (FSK) voiceband modem. It is
pin selectable for baud rates of 300, 600, or 1200
bits per second and is compatible with the applicable Bell and CCITI recommended standards for
103/113/108,202, V.21 and V.23 type modems.
Five mode control lines select a desired modem
configuration.
Digital signal processing techniques are employed
in the EF791 0 to perform all major functions such
as modulation, demodulation and filtering. The
EF791 0 contains on-chip analog-to-digital and dig ital-to-analog converter circuits to minimize the external components in a system. This device includes
the essential RS-232/CCITI V.24 terminal control
signals with TIL levels.
CERDIP28
(Cerdip Package)
(Ordering Information at the end of the data-sheet)
PIN CONNECTIONS
DIP/CERDIP28
Clocking can be generated by attaching a crystal to
drive the internal crystal oscillator or by applying an
external clock signal.
A data access arrangement (DAA) or acoustic coupler must provide the phone line interface externally.
The EF791 0 is fabricated using HMOS technology.
All the digital input and output signals (except the
external clock signal) are TIL compatible. Power
supply requirements are ± 5 volts.
January 1989
M88EF7910-01
1/31
13
~
.j>.
~
ID
m
o(')
......
r
~
n n
TRANSMITTED
18
.-J L.J L-.
DATA
<>sAC;
'" TRANSMITTED
8
TRANSMmER
CARRIER
JVVL
"c
:;
G)
::0
»
s:
CAP,
JVVL
~6
7
CAP 2
RECEIVER
5
RECEIVED
CARRIER
~
I~
~o
i!il:
..
en
13~ REQUEST TO SEND }
MCz 02!-.
25
MC4
DATA TERMINAL
READY
~
CLEAR TO SEND
11 ...
~
14~
INTERFACE CONTROL
21
~
CARRIER DETECT
1",
~
o
2
0
24
XTAL,/CLK
23
XTAL2
~
MAIN
REQUEST TO SEND
CLEAR TO SEND
27
0-::-
m
"T1
L--
CARRIER DETECT
3~
s:
n
MCO
MC3
IJlIi
~
n
.-J L.J
12",
02?MC, ~
""en
@.
~i!
26
,MAINO
5 RECEIVED
DATA
TIMING
CONTROL
0
0
0
RING
RESET
20 +5V Vee
4
9
22
0 -5V Vee
0 AGND
0
DGND
} BACK
"T1
...oco
EF7910
INTERFACE SIGNAL DESCRIPTION
MCo - MC4 (control inputs)
CARRIER DETECT (CD)
These five inputs select one of thirty-two modem
configurations according to the Bell or CCITT specifications listed in table 1. Only 19 of these 32
modes are actually available to the user.
A LOW on this output indicates that a valid carrier
signal is present at the receiver and has been present for at least a time, tCDON, where tCDON depends
upon the selected modem configuration (Table 3b).
A HIGH on this output signifies that no valid carrier
is being received and has not been received for a
time, .!cooFF. CARRIER DETECT remains HIGH
when DTR is HIGH. Values fortcDoN and tcDOFF are
configuration dependent and are listed in table 3b.
Modes 0-8 are the normal operation modes. The
1200 Baud modes can be selected with or without
a compromise equalizer.
Modes 16-25 permit loop back of the EF791 0 transmitter and receiver. No internal connection is made.
The user must externally connect the TRANSMITTED CARRIER pin (figure 1) to the RECEIVED
CARRIER pin if analog loopback is required. For digital loopback, external connection of RECEIVED
DATA and TRANSMITTED DATA is required. Whenever a mode in this group is selected, the effect is
to set all transmit and receive filters to the same
channel frequency band so that loopback can be
performed.
Modes 9-15 and 26-31 are reserved and should not
be used.
DATA TERMINAL READY (DTR)
A LOW level on this input indicates the data terminal desires to send and/or receive data via the modem. This signal is gated with all other TTL inputs
and outputs so that a low level enables all these signals as well as the internal control. logic to fun?tion.
A HIGH level disables all TTL I/O pinS and the Internallogic.
REQUEST TO SEND (RTS)
A LOW level on this input instructs the modem to
enter transmit mode. This input must remain LOW
for the duration of data transmission. The signal has
no effect if DATA TERMINAL READY is HIGH (disabled). A HIGH level on this input turns off the
trans mitter.
CLEAR TO SEND (CTS)
This output goes LOW at the end of a delay initiated when REQUEST TO SEND goes LOW. Actual
data to be transmitted should not be presented to
the TRANSMITTED DATA input until a LOW is indicated on the CLEAR TO SEND output. Normally
the user should force the TD input HIGH whenever
CTS is off (HIGH). This signal never goes LOW as
long as DTR is HIGH (disabled). CLEAR TO SEND
goes HIGH at the end of a delay initiated when REQUEST TO SEND goes HIGH.
TRANSMITTED DATA (TD)
Data bits to be transmitted are presented on this input serially; HIGH (mark) corresponds to logic 1 and
LOW (space) corresponds to logic O. This data determines which frequency appears at any instant at
the TRANSMITTED CARRIER output pin (table 3a).
No signal appears at the TRANSMITTED CARRIER
output unless DTR is LOW and RTS is LOW.
RECEIVED DATA (RD)
Data bits demodulated from the RECEIVED CARRIER input are available serially at this output. HIGH
(mark) indicates logic 1 and LOW (space) indicates
logic O. Under the following conditions this output is
forced to logic 1 because the data may be invalid:
1. When CARRIER DETECT is HIGH
2. During the internal squelch delay at half-duplex
line turn around (202N.23 modes only)
3. During soft carrier turnoff at half-duplex line turn
around (202 mode only)
4. When DTR is HIGH _ _
5. When RTS ON and BRTS OFF in V.23/202
rnodes only
6. During auto-answer sequence
BACK REQUEST TO SEND (BRTS)
Since the 1200 bps modem configurations, Bell 202
and CCITT V.23, permit only half duplex operation
over two-wire lines, a low baud rate "backward"
channel is provided for transmission from the main
channel receiver to the main channel transmitter.
This input signal (BRTS) is equivalent to REQUEST
TO SEND for the main channel, except it belongs to
the backward channel. Note that since the EF791 0
contains a single transmitter, RTS and BRTS should
not be asserted simultaneously. BRTS is meaningful only when a 202 or V.23 mode is selected by
MCo-MC4. In all other modes it is ignored.
3/31
15
EF7910
For V.23 mode the frequency appearing at the transmitted carrier (TC) output pin is determined-ID'-a
MARK or SPACE at the back transmitted data (BTD)
input (table 3a).
5. When BRTS ON and RTS OFF in V.23 modes
only
For 202 mode a frequency of 387 Hz appears at TC
when BRTS is LOW and BTD is HIGH. No energy
(0.0 Volt) appears at TC when BRTS is LOW and
BTD is HIGH. No energy (0.0 volt) appears at TC
when BRTS is HIGH. BTD should be fixed HIGH for
202 back channel transmission. The signal, BRTS,
then is equivalentto the signal, Secondary Requestto-Send, for 202 SIT modems, or Supervisory
Transmitted Data for 202 C/D modems.
This analog output is the modulated carrier to be
conditioned and sent over the phone line.
TRANSMITTED CARRIER (TC)
RECEIVED CARRIER (RC)
This input is the analog signal received from the
phone line. The modem extracts the information
contained in this modulated carrier and converts it
into a serial data stream for presentation at the RECEIVED DATA (BACK RECEIVED DATA) output.
BACK CLEAR TO SEND (BCTS)
RING
This line is equivalent to CLEAR TO SEND for the
main channel, except it belongs to the back channel. BCTS is meaningful only when a V.23 mode is
selected by MCo-MC4. This signal is not used in Bell
202 back mode.
This input signal permits auto-answer capability by
responding to a ringing signal from a data access
arrangement. If a ringing signal is detected (RING
LOW) and DTR is LOW, the modem begins a sequence to generate an answer tone at the TC output.
------
BACK CARRIER DETECT (BCD)
---=~-===-=
This line is equivalent to CARRIER DETECT for the
main channel, except it belongs to the backward
channel. BCD is meaningful only when a 202 or V.23
mode is selected by MCo-MC4. For V.23 back channel mode, BCD turns on when either the MARK or
SPACE frequency appears with sufficient level at
the received carrier (RC) input.
For 202 back channel mode, BCD turns on in response to a 387 Hz tone of sufficient level at the RC
input. In this case BCD is equivalent to the signal,
Secondary Received Line Signal Detector, for 202
SIT modems, or Supervisory Received Data for 202
C/D modems.
BACK TRANSMITTED DATA (BTD)
This line is equivalent to TRANSMITTED DATA for
the main channel, except it belongs to the back
channel. BTD is meaningful only when a 202 or V.23
mode is selected by MCo-MC4. For 202 back transmission of on/off keying, BTD should be fixed at a
HIGH level.
BACK RECEIVED DATA (BRD)
This line is equivalentto RECEIVED DATA (except
clamping) for the main channel, except it belongs to
the back channel. BRD is meaningful only when a
V.23 mode is selected by MCo-MC4. Underthe following conditions this output is forced HIGH:
1.
2.
3.
4.
BRD HIGH
DTR HIGH
V.21 /1 03 mode
During auto-answer
4/31
16
XTAL1, XTAL2
Master timing of the modem is provided by either a
crystal connected to these two inputs or an external
clock inserted into XTAL1. The value of the crystal
or the external clock frequency must be
2.4576 MHz ± 01 %.
Vcc
+ 5 volt power supply (± 5 %)
VBB
- 5 volt power supply (± 5 %).
DGND
Digital signal ground pin.
AGND
Analog signal ground pin (for TRANSMITTED CARRIER and RECEIVED CARRIER).
CAP1, CAP2
Connection points of external capacitor/resistor required for proper operation of on-chip analog-to-digital converter.
Recommended values are: C = 2 nF ± 10 %,
R = 100 n ± 10 %.
RESET
This input signal is for a reset circuit which operates
in either of two modes. It automatically resets when
power is applied to the device, or it can be activated
by application of an external active low TTL pulse.
EF7910
Table 1.
MC4
MC3
MC2
MC1
MC a
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
Bell 103 Originate 300 bps Full Duplex
Bell 103 Answer 300 bps Full Duplex
Bell 202 1200 bps Half Duplex
Bell 202 with Equalizer 1200 bps Half Duplex
CCITT V.21 Orig 300 bps Full Duplex
CCITT V.21 Ans 300 bps Full Duplex
CCITT V.23 Mode 21200 bps Half Duplex
CCITT V.23 Mode 2 with Equalizer 1200 bps Half Duplex
CCITT V.23 Mode 1600 bps Half Duplex
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
Reserved
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
Bell 103 Orig Loopback
Bell 103 Ans Loopback
Bell 202 Main Loopback
Bell 202 with Equalizer Loopback
CCITT V.21 Orig Loopback
CCITT V.21 Ans Loopback
CCITT V.23 Mode 2 Main Loopback
CCITT V.23 Mode 2 with Equalizer Loopback
CCITT V.23 Mode 1 Main Loopback
CCITT V.23 Back Loopback
1
1
0
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
0
1
Reserved
1
1
Figure 1 : Loopback Configurations.
EF7910
[----,
r-----:""
.......~
I
DATA
TERMINAL
~1-',
LOOPBACK
~
TRANSMITTER
I
I[~
TC
ANAL';" 0 Tx
PHONE
UNE
~
L:_:=_~
Rx
M88EF7910·Q3
5/31
17
EF7910
THEORY OF OPERATION
The EF7910 MODEM consists of three main sections, shown in the block diagram - Transmitter, Receiver, and Interface Control.
TRANSMITTER (modulator)
The transmitter, shown in figure 2 receives binary
digital data from a source such as a UART and
converts the data to an analog signal using frequency shift keying (FSK) modulation. This analog signal
is applied to the phone line through a DM or acoustic coupler. FSK is a modulation technique which
encodes one bit per baud. A logic one applied to the
TRANSMITTED DATA (TD) input causes a sine
wave at a given frequency to appear at the analog
TRANSMITTED CARRIER (TC) output. A logic zero applied to input TD causes a sine wave of a different frequency to appear at the TC output. As the
data at the TD input switches between logical one
and zero, the TC output switches between the two
frequencies. In the EF791 0 this switching between
frequencies is phase continuous. The frequencies
themselves are digitally synthesized sine functions.
The frequencies for each modem configuration
available in the EF7910 are listed in table 3a.
The process of switching between two frequencies
as in FSK generates energy at many more frequencies than the two used in the modulation. All the
transmitted information can be recovered from a frequency band B Hz wide, where B is the bit rate or
maximum rate of change of the digital data at the
TD input. This band is centered about a frequency,
fc,
where fc = f1 + (f2 - f1)/2
(f1 = lower of two FSK frequencies)
(f2 = higher of two FSK frequencies)
In addition to this primary information band, there
exist side bands containing redundant information.
It is desirable to attenuate these bands for two reasons:
1. The phone companies have specifications on the
amount of energy allowed in certain frequency
bands on the line.
2. If two independent information channels are present simultaneously on the line (e.g. 300 bps full
duplex or 1200 bps half duplex with back), the redundant transmitter components may fall in the
frequency band of the local receiver chan nel and
interfere with detection. In the EF791 0 these redundant and undesirable components are attenuated by digital bandpass filters.
Following the digital bandpass filters, the filtered
FSK signal is converted to an analog signal by an
on-chip DAC operating at a high sample rate. This
analog FSK signal is finally smoothed by a simple
on-chip analog low pass filter.
RECEIVER (demodulator)
A simplified block diagram of the EF7910 FSK receiver is shown in Figure 3. Data transmitted from a
remote site modem over the phone line is an FSKmodulated analog carrier. This carrier is applied to
the RECEIVED CARRIER (RC) pin via a DM or
acoustic coupler. The first stage of the demodulator
is a simple on-chip analog low pass anti-alias filter.
The output of this is converted into digital form and
filtered by digital bandpass filters to improve the signal to noise ratio and reject other independent
channel frequencies associated with the phone line
in the case of full duplex configuration. The bandpass filtered output is digitally demodulated to recover the binary data. A carrier detect signal is also digitally extracted from the received line carrier to indicate valid data.
Figure 2: Transmitter Block Diagram.
...J1SL
FROM
UART
TO
SINE
SYN'T)tESIZER
DIGITAL
BANDPASS
FILTERS
TC
I)JW'
TDDAA
OR
ACOUSnc
COUPLER
M88EF791 0-04
6/31
18
EF7910
Figure 3 : Receiver Block Diagram.
'WV'
RC
ANALOG
PREFILTER
DIGITAL
BANDPASS
FILTERS
ADC
DIGITAL
DEMODULATION
RD
TO UART
FROMOAA
OR
ACOUSTIC COUPLER
M88EF7910·05
INTERFACE CONTROL
This section controls the handshaking between the
modem and the local terminal. It consists primarily
of delay generation counters, two state machines
for controlling transmission and reception, and
mode control decode logic for selecting proper
transmit frequencies and transmit and receive filters
according to the selected modem type. Inputs and
outputs from this section are as follows:
REQUEST TO SEND (Main and Back)
CLEAR TO SEND (Main and Back)
CARRIER DETECT (Main and Back)
RING
MCO-MC4
DATA TERMINAL READY
Internal logic clamps protocol signals to different levels under certain conditions (e.g., initial conditions).
When Bell 103/113 and V.21 modem configurations
are selected, the back channel signals are non-functional.
Figures 6 and 7 depict the sequencing of the two
state machines. State machine 1 implements main
or back channel transmission and the auto-answer
sequence. State machine 2 implements reception
on main or back channel.
The state machine powers on to the state labelled
INITIAL CONDITIONS. Handsha~e signals are set
to or assumed to be the levels listed in table 2. The
machine then waits for DATA TERMINAL READY
(DTR) to be turned on. Whenever DTR is turned to
the OFF state from an ON condition, each state machine and external signals return to the initial conditions within 25 microseconds. After DTR is turned
6..,I
~
ON the EF7910 becomes operational as a modem
and the state machines proceed as depicted in the
flowcharts.
The definitions of the terms Full Duplex and Half Duplex used in these flowcharts are depicted below
(figs. 4 and 5). "Full Duplex" applies to all 103/113,
V.21 modes. "Hall Duplex" applies to 202 and V.23,
both forward and backward channel.
Full Duplex: Data can be transmitted and received
simultaneously at a rate of 300 baud. Two independent 300 Hz channels are frequency multiplexed
into the 3000 Hz bandwidth of the phone line. The
EF7910 configurations for the Bell 103/113 and
CCITT V.21 can be operated full duplex.
Half Duplex: In half duplex with back channel, the
modem may transmit at 1200/600 baud and receive
at 5/75 baud. Alternatively it may transmit at 5/75
baud and receive at 1200/600 baud. Examples are
Bell 202 and CCITT V.23.
Table 2 : Initial Conditions
Data Terminal Re~DTR)
Request to SenQJBTS)
Clear to Send (CTS)
Transmitted Data (TO)
__
Back Channel Request to Send (BRTS)
Back Channel Clear to Send (BCTS)
Back Channel Transmitted Data (BTD)
_
Ring (RING)
Carrier Detect (CD)
Received Data (RD)
_
Back Channel Carrier Detect (BCD)
Back Channel Received Data (BRD)
SGS·1HOMSON
OFF
OFF
OFF
Ignored
OFF
OFF
Ignored
OFF
OFF
MARK
OFF
MARK
7/31
~llIGLII@I
m
-"
~
~
--J
MAIN
LINE
BACK
2 S~r-4 "c~--e sec
. "ft
,uv
~A~
rvw I
n~ i= hnnlc
I-ar s ce
mgt
sr
I
s ce
ata cs e to cs
In
I'
0-------;
~
tone I
I
S~UELCH
, Markl
--I
space
Back channel data
called to calling
~~~
Back channel data
calling to called
' I
/
/
I
m
."
......
<0
.....
0
EF7910
The 202 and V.23 main loopback modes allow use
in a 4-wire configuration at 1200 bps.
resonance type, and its value must be 2.4576 MHz
± 0.01 %. A list of crystal suppliers is shown below.
EXTERNAL CLOCK
CLOCK GENERATION
Master timing of the modem is provided by either a
crystal connected to the XTAL 1 and XTAl2 inputs or
an external clock applied to the XTALI input.
CRYSTAL.
When a crystal is used it should be connected as
shown in figure 11. The crystal should be a parallel
This clock signal could be derived from one of several crystal-driven baud rate generators. It should
be connected to the XTALI input and the XTAL2 input must be left floating. The timing parameters required of this clock are shown in figure 11 and the
values are listed in table 4.
Figure 11 : Clock Generation.
Crystal Information (fc = 2.4576 MHz)
Manufacturer
M-Tron
Monitor Products
Note: Rise time of Vee must be greater than 5 msec to insure
proper crystal oscillator start-up.
I
I
":~::
.----_---i lCTAL,
~---lXTAL2
I
I
M88EF7910-18
M88EF7910-19
Capacitors values vary with different crystal manufacturers.
(b)
M88EF7910-20
Table 4 : Clock Parameters.
Symbol
Parameter
Min.
Typ.
Max.
406.86
406.9
406.94
Unit
tCY
Clock Period
tCH
Clock High Time
165
tCl
Clock Low Time
165
tCR
Clock Rise Time
20
ns
tCF
Clock Fall Time
20
ns
ns
ns
ns
23/31
35
EF7910
POWER ON RESET
The reset circuit operates in either of two modes.
AUTOMATIC RESET
In this mode an internal reset sequence is automatically entered when power is applied to the device.
One resistor and one capacitor must be connected
externally as shown in Figure 12. Values shown will
work with most power supplies. Power supply (Vcc)
rise time should be less than one half the RC time
constant.
Figure 12 : Automatic Reset.
Vcc
EF7910
R
1MEGn (±20%)
RESET
cT
DGND
M88EF7910·21
EXTERNAL RESET
In this mode the device may be forced into the reset sequence by application of an active LOW pulse
applied to the RESET input. The reset must not be
applied until the Vee supply has reached at least
3.5 V. Timing is diagrammed in figure 13.
Figure 13: External Reset.
TIMING DIAGRAMS
toR = delay from the time Vee reaches 3.5 V and the falling edge of RESET signal (> 1 ~)
tRL = RESET LOW duration time (> !MeK =406 ns)
24131
36
M88EF7910-22
EF7910
NOMINAL PERFORMANCE SPECIFICATIONS
TRANSMITTER (all modem types)
Input Data Format: Serial, asynchronous, standard
TTL levels Modulation Technique:
Binary, phase-coherent Frequency Shift Keying
(FSK)
TC Output Level: - 3 dBm into 600 (2
Frequency Accuracy:
± 0.4 Hz all modems except Bell 202 (mark)
+ 1.0 Hz Bell 202 (mark)
Harmonics: - 45 dB from fundamental for single
tones
Delay uncertainty for TO logic input change to TC
frequency change: ::; 8.3 /.IS
Out-of-band energy: see figure 14
RECEIVER
Output Data Format: Serial, asynchronous, TTL levels Demodulation Technique: Differential FM Detection
Sensitivity at Receiver Input: 0 dBm to - 48 dBm
Frequency Deviation Tolerance: ± 16 Hz
Carrier Detect Threshold:
ON
OFF
Hysteresis
> - 40 dBm
< - 43 dBm
> 2.5 dB
± 1 dB
± 1 dB
TEST MEASUREMENT SETUP
EF791 0 performance is characterized using the test
equipment setup shown in Figure 15. The HP1645A
data error analyzer is used to generate 511-bit pseudo random binary sequences (PRBS) at DouT for
testing the modem. The 1645A also receives and
analyzes the 511-bit digital pattern at DIN after it has
progressed around the test loop. A reference transmitter converts the digital sequence generated by
the HP1645A into an FSK signal. The FSK signal is
typically adjusted to different levels from - 12 to
- 45 dBm. The level-adjusted FSK signal or incident
signal then passes through three pieces of equipment which comprise the telephone line simulator.
The Wandel and Golterman TLN-1 and DLZ-4 simulate amplitude and group delay characteristics typical of a wide variety of phone lines. Line perturbations, such as amplitude hits and phase hits, may
be injected by the Bradley 2N2B.
The summing amplifier which drives the modem under test has three inputs. One of these inputs is the
incident FSK signal which has been passed through
a simulated phone line. The second input is from an
optionally filtered noise source in order to simulate
noise conditions which may be encountered on
phone lines. The third input is from the transmitter
of the EF791 0 under test. This third input simulates
the adjacent channel signal seen at the input of the
EF7910 receiver due to the duplexer used on 2-wire
lines. If 4-wire testing is being performed, the adjacent channel would not normally be included.
The HP3551A or HP3552A Transmission Test Set
is used for measuring various levels which the modem under test is to receive. The levels of each of
the three inputs to the summing amplifier should be
measured independently of the other two inputs. For
instance, the incident signal level should be measured by the transmission test set with no adjacent
channel or noise present. The dashed line from the
noise generator shows that the noise mayor may
not be measured at the output of the noise generator, depending on whether or not an optional filter
is used, or on the characteristics of the filter.
Figure 14 : Out-of-band Transmitter Energy.
3.4
;-_.;.---+-.--_-;:...-_.....:;:-_~-~64-~-.!:;_
KH,
-20
-40
-60
dB
M88EF7910-23
25/31
37
EF7910
Figure 15: SER and Distorsion Measurement Test Setup.
TRANSMITTED
BINARY
SEQUENCE
HPI645A DATA
ERROR ANALYZER DOUT ~-----I
REFERENCE
TRANSMITTER
AND PATTERN GEN
LEVEL
ADJUST
,-------,
LEVEL·ADJUSTED
FSKSIGNAL
(INCIDENT SIGNAL)
511·BIT PRas
GENERATOR
(ADJACENT CHANNEll
RD
I
TO
EF7910
UNDER
TEST
TC
RC
LEVEL
ADJUST
~!~:~~~~:NEL
~
SIGNAL
Y
I
I
I
I
I
I
I
I
I
II
BRADLEY 2A/2B
JITTER AND HIT
SYNTHESIZER
II
WANDEL AND
GOLTERMAN
TLN-I
~~~~~;:~
DLZ-4
l;- - - -U~~E ------ J
LEPHONE
SIMULATOR
L-~~~~--~------~+~------~-----------~
SUMMING AMPLIFIER
1--·--1
HP355IA OR 3552A
TRAIiiSMISSION
TEST SET
I
I
L_. _.
opnONAL
FILTER
-.1
NOISE
GENERATOR
M88EF791 0-24
26131
38
I
I
I
II
I
I
I
II
EF7910
STANDARD LOAD CIRCUIT
TEST
Vee
POINT
FROM
D,
~~Il ~ 1"110
O~~~~o-____~~--1---~~--~
TEST
Rl
48K
~
1"110
MBBEF7910-25
Notes: 1. C, = 50 pF including stray and wiring capacitance.
2. All diodes are 1N3064 or equivalent.
3. All resistors are 1/B walt.
4. Vee = 5 votts± 1 %.
APPLICATIONS
~igure
17 depicts a stand-alone EF7910 configuration. An op amp and three resistors provide a duplexor function to put the transmitter output into the
line while receiving adjacent channel data from the
line. Connection to the line is via a Data Access Arrangement (DM). Note the lack of external analog
filters. The TTL handshake signals may be level
~nverted .to RS-232, RS-422, or V.24 using appropriate devices. Mode control lines are hardwired or
connected to switches.
Figure 18 depicts an application of the EF791 0 with
the SGS-THOMSON Microelectronics EF6805CT
microcomputer. The duplexor/line interface is identical to the above configuration. However, the
handshake signals interface directly with the UART
included inside the EF6805CT. The mode control
lines might also be controlled by the MCU while keeping the address and data bus of the EF6805CT
available for customer applications. The main features of the EF6805CT are given at the end of this
data sheet.
Gi
SGS·ntOMSON
~/IliJDICIlI@IiIl.~OCIII
27/31
39
<'5
I\l
ClO
"
m
........
CD
cC·
~
,
Am26l.S32
....
I
I
I
2
iil
I
l~
4
c
,
2.21'F
I
rv....
I
~OLS
I +sv
RTS
TC
TO
RC
I
~.
:V
~ £_-1
....
i
I
I
I
:~~
5
S·
~
I
I
I
I
I
I
I
I
~;!
I
t-----
!O
XTAL,
CAP,
I
~i!I
~fg
L ______
7~
Am26LS29
f-
J
DLO
ALB
CAP2
MC4
RESET
T
m
.5V
0
u
"Q.
o·
o·
!!l.
?
C2+
~
12000pF
Vee
+5V
VOO
-5V
"7
1 kn
+5V
+5V-5V-
~
DGND
Mea
on.:; T.
'<-l>---
Me2
~
~
'Mnl
RING
Me,
AGNO
-&
~ ·See Figure 12.
OLB = DIGITAL LOOPBACI<
ALB = ANALOG LoOP8ACK LOCAL COpy
0"
".....~
e,"
Me3
~
::J
:i>
::J
CD
loon
BRD
f!!
Sl>
a.
RING
.SV
,-
&l
. - RINGING
~
ocl 2.4576 MHz
OCD
I
I
~Z
P. NE
LI HE
DAA
»
I
I
1
f-
EF7910
-~
I
XTAL2
BCTS
I
i~
ALS
CTS
I
I
r-
TIP
DR
22 kn
~
CI)
I
I
>1:0
@~
~.
DT
I
UTO
RD
22 kn
I
I
I
I
I
I
3
1
BRTS
L______ JI
r------,
I
_oL!>
!
r _
DTA
I
~
POWER
SUPPLY
'T1
......
.....
0
"11
......
cS·
c:
1/0 timer available for other applications
(1)
E
NMI
IRQ
Intenupt
In1errupt
R"""
E
BO
NMI
Bl
74<:08
CD
IRQ
RST
IX)
Clear to send
«
lL
II:
w
t~
0
===
Data bus or
Add....../Data b ...
B4
RiWo.-oSC
"
0
AS or 105
II:
or ISC
~
0
...0
~~
@.
1/00<
Add ......
II:
~:i!
0
,;.
@cn
EF6805CT
Al
}~
A"1
«
~O
A3
A4
A6
for RAM
VOC STB
»
-0
"2-
EF7910
o·
A7
X
0
O
>
0
Z
Cl
;!
xw
ao·
DTR
Request to send
Back request to :send
Mode control 0
RST
RTS
BRTS
MCO
CAPI
Mode control 1
MCI
Mode control 2
Mode control 3
Mode control 4
Reset
2nF
?
.,0nF
~,~U
MC2
MC3
MC4
..J
..J
«
t-
Q
o·
Data terminal ready
~
Voc standby
RING
~
A5
~Z
C"l
CD
(J)
(J)
-0
RC
::E
~O
a
'<
"-
AO
U
II:
PHONE
LINE
a
-0
-I
TO
BTD
gj
w
!1:cn
OT
O
II:
0
OAA
RD
BRD
Transmit data
s::
o·
OR
TC
CTS
BCTS
Receive data
B3
'1/0 or
RI
68 nF
B2
5
w
(X)
TIP
BCD
"0
RI
RING
U
0
ID
ED
> >
0
Z
CJ
0
a
Z
CJ
«
;::
&l
2.4576 MHz
m
~
m
o
:::
'"
~
~
• Depending on work mode.
."
-...I
(0
.....
o
EF7910
ABSOLUTE MAXIMUM RATINGS
Symbol
Value
Parameter
Unit
- 65 to + 125
°C
a to + 70
°C
T 8tg
Storage Temperature
Tamb
Ambient Temperature under Bias
Vee
Vee with Respect to VOGNO
+ 6 1- 0.4
V
VBB
VBB with Respect to VOGNO
- 6 1 + 0.4
V
±5
V
All Signal Voltages with Respect to VOGNO
The products described by this specification include
internal circuitry designed to protect input devices
from damaging accumulations of charge. It is suggested, nevertheless, that conventional precautions
be observed during storage, handling and use in order to avoid exposure to excessive voltages.
Stresses above those listed under "Absolute Maxi-
mum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended
periods may affect device reliability.
ELECTRICAL DC CHARACTERISTICS over operating range, referred to V DGND
70 °C~e = + 5.0 V±5%,~-5.0 V±5%, VAGND = 0 V±50 mY, VDGND = OV
o 'C ~TA ~+
Digital Inputs: TO, RTS, MQ.o.::MC 4 , DTR, RING, BTD, BRTS
Digital Outputs: RD, CTS, CD, BRD, BCTS, BCD
Symbol
Parameter
=- 50 ~A, CLD = 50 pF)
= + 2 mA, ClO = 50 pF)
Min.
Typ.
Max.
Unit
0.4
V
V
2.4
VOH
Output HIGH Voltage (loH
Val
Output LOW Voltage (Iol
VIH
Input HIGH Voltage
2.0
Vec
V
Vil
Input LOW Voltage
- 0.5
+ 0.8
V
VIHe
External Clock Input HIGH (XTAL t )
3.8
Vce
V
- 0.5
0.8
V
V
VllC
External Clock Input LOW (XTALll
VIHR
External Reset Input HIGH (RESET)
3.8
Vec
VILR
External Reset Input LOW (RESET)
- 0.5
0.8
V
IlL
Digital Input Leakage Current (0 ,,; VIN ,,; Vce)
-10
+ 10
Icc
Vec Supply Current
125
~
mA
IBB
VBB Supply Current
COUT
CIN
Output Capacitance (fe
= 1.0
MHz)
Input Capacitance (fe = 1.0 MHz)
25
mA
5
15
pF
5
15
pF
ANALOG INPUT (RC) :
kO
Input Resistance (- 1.6 V < VRC < + 1.6 V)
Operating Input Signal
- 1.6
+ 1.6
V
Allowed DC Input Offset (REF VAGNO)
- 30
+ 30
mV
VRCOS
ANALOG OUTPUT (TC) :
Output Voltage (RL = 600 0)
Output DC Offset
30/31
42
50
RIN
VRe
EF7910
ORDERING INFORMATION
Part Number
Temperature Range
Package
o to 70°C
o to 70°C
DIP 28
CERDIP28
EF7910PL
EF7910JL
PACKAGE MECHANICAL DATA
28 PINS - PLASTIC PACKAGE
4.57max.
15.24
(2)
Dotum
(11 Nominal dimension
(2) True geometrical position
Or
14
14
(11
38.1 max.
~
~"I
SGS·THOMSON
2BPins
31/31
I1OtlO©IliI@IlU©'ITIliI@OOO©@
43
TS7513
SINGLE CHIP ASYNCHRONOUS FSK MODEM
• MONOLITHIC DEVICE INCLUDING BOTH
TRANSMIT AND RECEIVE FILTER
• PROGRAMMABLE MODES:
_ 75 BDS TRANSMIT / 1200 BDS RECEIVE
_ 1200 BDS TRANSMIT /75 BDS RECEIVE
1200 BDS FULL DUPLEX ON 4 WIRE LINE
_ ANALOG LOOPBACK
• FIXED COMPROMISE LINE EQUALIZER
• RECEIVE AND TRANSMIT CLOCKS FOR
UART
• STANDARD
LOW
COST
CRYSTAL
(3.579 MHz)
• ± 5 % POWER SUPPLIES ( + 5 V, - 5 V)
• DTMF FILTER AND TAX REJECTION NOTCHFILTER (kit with EFG7189 DTMF)
• 3.579 MHz CLOCK OUTPUT AVAILABLE
P
DIP22
(Plastic Package)
(Ordering Information at the end of the datasheet)
PIN CONNECTIONS
TEST
MC/Be
RTS
TxD
GNDD
elK
v+
RxClK
RFO
TxClK
ATO
XtaiiN
V
DESCRIPTION
The TS7513 is a single chip asynchronous frequency shift keying voice-band modem. Operating at
rates up to 75, 1200 bit per second, it is compatible
with the applicable CCITT recommended standards
for V.23 type modems. This device provides the essential CCITT V.24, V.25 and V.54 terminal control
signals at TTL levels.
XtalOUT
DTMF
ROI
RAI
OCD
GNDA
RxO
RSA
VREF
M88TS7513-01
ABSOLUTE MAXIMUM RATINGS
Symbol
V+
Value
Unit
Supply Voltage
+7V
V
V-
Supply Voltage
-7V
V
Yin
Analog Input Range
V- S VIN S V+
V
VI
Digital Input Range
GNDD S VI S V+
V
TA
Operating Temperature Range
o to 70
T stg
Storage Temperature Range
°C
°C
OC
Parameter
Pin Temperature (soldering, 10 s)
- 55 to + 125
260
Stresses above those listed under "Absolute Maximum Ratings· may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other cond~ions beyond those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliabil~. Standard CMOS handling procedures should be employed to avoid possible damage to device.
December 1988
1/15
45
TS7513
BLOCK DIAGRAM
M88TS7513-02
ELECTRICAL CHARACTERISTICS
Symbol
V+
Min.
Nom.
Max.
Unit
Positive Supply Voltage
4.75
5.0
5.25
V
V-
Negative Supply Voltage
- 5.25
- 5.0
-4.75
V
Icc
V+ Operating Current
-
-
20
mA
Iss
V- Operating Current
-15
-
-
rnA
2/15
46
Parameter
Gi
SGS·THOMSON
~I [ljJO©IiI@~D.R'ii'1iI@1ll01:$
TS7513
D.C. AND OPERATING CHARACTERISTICS
(TA = 0 °C to + 70°C, V+ = + 5 V ± 5 %, V - = - 5 V ± 5 %, GNDA = 0 V, GNDD = 0 V, unless otherwise
noted).
DIGITAL INTERFACE (TEST, RTS, DCD, RxD, TxCLK, RxCLK, CLK, TxD, MC/BC)
Symbol
II
Parameter
Input Current (VIL min" VI " VIH max)
Min.
Typ. (1)
Max.
-
-
10
f!A
1.6
-
-
mA
Unit
IOL
Output Low Level Current (VOL = 0.4 V)
IOH
Output High Level Current (VOH = 2.8 V)
-
-
- 250
f!A
VIL
Input Low Voltage
GNDD
-
V
VIH
Input High Voltage
2.4
-
0.8
V+
Unit
V
ANALOG INTERFACE, RECEIVE FILTER (DTMF, RAI, RFO)
Symbol
Min.
Typ. (1)
Max.
IBRI
Input Leakage Current, (- 3 V < VIN < 3 V)
Parameter
DTMF, RAI
-
± 1
±3
f!A
RIRI
Input Resistance,
DTMF, RAI
1
3
-
MQ
mV
Output Offset Voltage,
RFO
-
-
± 300
VORl
Output Voltage Swing, (RL ;" 10 kQ)
RFO
-
-
± 3
V
CLRI
Load Capacitance,
RFO
-
20
pF
RLRI
Load Resistance,
RFO
10
-
kQ
VIRI
Input Voltage Swing,
RAI
-2
+2
V
VIO
Input Voltage Swing
DTMF
-3
-
+3
V
Signal Frequency Distortion Products at
Maximum Signal Level
RFO
-
- 40
-
dB
VOGSR
COPR
ANALOG INTERFACE RECEIVE DEMODULATOR INPUT (RDI)
Symbol
Min.
Typ. (1)
Max.
Unit
Input Current
-1
-
1
f!A
N1
Maximum Detection Level to Valid DCD Output
1.2
1.4
1.6
Vp
N2
Minimum Detection Level to Valid DCD Output
-
1.0
-
Vp
2.3
3
4
dB
lin
N1/N2
Parameter
Hysteresis Effect
ANALOG INTERFACE, RECEIVE SLICER ADJUST (RSA)
Symbol
Min.
Typ. (1)
Max.
Unit
lin
Input Current
Parameter
- 1
-
+ 1
f!A
VI
Input Voltage
VREF
VREF/2
GNDA
V
(1) Typical values are for TA = 25°C and nominal power supply values.
3/15
47
TS7513
D.C. AND OPERATING CHARACTERISTICS (continued)
ANALOG INTERFACE, TRANSMIT OUTPUT (ATO)
Symbol
Parameter
Min.
Typ. (1)
Max.
Unit
-
± 250
mV
Load Capacitance
-
-
20
pF
RL
Load Resistance
10
-
kQ
Vo
Output Voltage Swing
(RL = 10 kQ, CL = 20 pF)
2.8
-
3.6
Vpp
Vos
OU1put DC Offset, (RTS connected to V+)
CL
390 Hz
-
450 Hz/390 Hz Amp!. Ratio
Vo
1300 Hz
-
-
2100 Hz/1300 Hz Amp!. Ratio
RTS Attenuation Ratio Efficiency
0
-
1
dB
2.8
-
3.6
Vpp
0
-
1
dB
55
-
dB
Unit
ANALOG INTERFACE, REGULATED VOLTAGE (VREF)
Symbol
Parameter
Min.
Typ. (1)
Max.
- 2.6
- 2.2
- 1.8
V
Load Resistance
10
-
kQ
Load Capacitance
-
-
20
pF
Min.
Typ.
Max.
Unit
0.9
1.5
2.6
dB
-
- 60
- 50
dB
-
- 60
- 48
dB
2.8
3.1
4
dB
- 30
-
- 17
dB
-
- 45
- 40
dB
0.9
1.5
2.6
dB
1
1.5
2
dB
- 30
-
20
dB
-
- 50
- 48
dB
-
~
55
- 50
dB
-
- 45
- 40
dB
Min.
Typ.
Max.
Unit
-
0
-
dB
VOR
Output Voltage
RLR
CLR
( 1) Typical values for T A ~ 25 °C and nominal power supply values.
DYNAMIC CHARACTERISTICS
RECEIVE FILTER TRANSFER CHARACTERISTICS
Symbol
Parameter
GAR
Absolute Passband Gain at 1300 Hz
GRR
Gain Relative to Gain at 1300 Hz
(maximum input signal) (2)
GAR
Absolute Passband Gain at 390 Hz
GRR
Gain Relative to Gain at 390 Hz
(maximum input signal)
(VRFO, RL
= =)
390 Hz
450 Hz
2100 Hz
2900 Hz
12000 Hz
(VRFO, RL
= =)
450 Hz
800 Hz
1300 Hz
2100 Hz
12000 Hz
DTMF FILTER TRANSFER CHARACTERISTICS
Symbol
Parameter
GAR
Absolute Passband Gain at 100 Hz
G RR
Gain Relative to Gain at 100 Hz
4/15
48
1000 Hz
- 1
0
+ 1
dB
3400 Hz
-
-3
-2
dB
10000 Hz
-
-
- 20
dB
TS7513
DYNAMIC CHARACTERISTICS (continued)
DIGITAL INTERFACE
Symbol
Min.
Typ. (1)
Max.
Unit
Capacitance
-
-
10
pF
tTHL, tTLH
Input Rise-time, Fall-time, measured between 0.8 V and 2.4 V
-
-
100
ns
tTHL, tTLH
Output Rise-time, Fall-time between 0.4 V and 2.8 V (3)
-
50
-
ns
CIB
Parameter
(1) Typical values are for TA ~ 25'C and nominal power supply values
(2) This value refers to the integrated receive filter only, measured at RFO. The rejection value for the complete reception part must take into
account the band-pass filter of the peak limiter (refer to CALCULATION OF CIRCUIT ELEMENTS). In this case the maximum gain relative to
gain at 1300 Hz is - 60 dB at 16 kHz.
(3) Driving one 74L or 74LS TTL load plus 30 pF.
PIN DESCRIPTION
COMMON SECTION
4
7
Name
V+
V-
Positive Power Supply
Negative Power Supply
10
GNDA
Analog Ground
Pin 10 serves as the ground return for the analog circuits of
the transmit and receive section. The analog ground is not
internally connected to the digital ground. The digital and
analog grounds should be tied together as close as
possible to the system supply ground.
3
GNDD
Digital Ground
Pin 3 serves as the digital ground return for the internal
clock. The digital ground is not internally connected to the
analog ground. The digital and analog grounds should be
tied together as close as possible to the system supply
ground.
17
XtaiiN
Oscillator Input
This pin corresponds to the input of the inverter of the
oscillator. It is normally connected to an external crystal, but
may also be connected to a pulse generator. The nominal
frequency of the oscillator is 3.579 MHz.
16
XtalOUT
Oscillator Output
12
VREF
Regulated Voltage
20
ClK
Clock
This output delivers a clock signal, the frequency of which is
3.579 MHz.
22
MC/BC
Main Channel/Back
Channel
This input selects transmission on the main channel or back
channel and defines the modulation rate according to the
European standards. (refer to functional description).
N°
Function
Description
+5V
-5V
This pin corresponds to the output of an inverter with
sufficient loop gain to start and maintain the crystal
oscillating.
This output carries an internally regulated voltage. By
means of an external potentiometer connected between
VREF and GNDA, an adjustable reference voltage may be
applied to RSA. The adjustment of RSA is to optimize the
discrimination of high anf low frequencies of the same
channel. The voltage applied to RSA is approximately
VREF/2.
5/15
49
TS7513
PIN DESCRIPTION (continued)
TRANSMIT SECTION
N°
Name
Function
Description
2
RTS
Request to Send
When a low state is present on input RTS, the TS75t3
delivers on output ATO a sinusoidal signal at a frequency
which de~s on input TxD. When a high state is present
on input RTS, output ATO is connected to DTMF filter.
21
TxD
Transmit Data
This input selects the high frequency or low frequency at
the Analog transmit output pin (A TO) :
• a high state selects the low frequency,
• a low state selects the high frequency.
18
TxCLK
Transmit Clock
This output delivers a clock signal, the frequency of which is
16 times the modulation rate (± 1 %). The logic state
duration is compatible to the UART clock specification.
6
ATO
Analog Transmit Output
When a low state is present on RTS, the TS7513 delivers
on output ATO a sinusoidal signal centered on the analog
ground.
RECEIVE SECTION
N°
Name
Function
Description
1
TEST
Loop Back Mode
When high, the demodulator is tuned on the transmission
modulation rate to the loop back mode or to the 4 wires full
duplex operation mode. When TEST is low, the modem is in
normal operating mode.
5
RFO
Receiver Filter Output
This analog output must be connected to a high-pass filter
and slicer, with sufficient gain to satisfy the level detection
conditions.
8
DTMF
Dual Tone Multifrequency
Input
Analog input receiving a signal from a dual tone
multifrequency generator. Transmitted spectrum of DTMF
Signal matches the gauge in Annex III.
9
RAI
Receive Analog Input
Input for modulated analog signal of amplitude lower than
4 V peak to peak and centered on analog ground.
15
RDI
11
RSA
Receive Slicer Adjust
14
DCD
Data Carrier Detect
This output is low when TS7513 receives on input RDI a
signal with amplitude higher than N1
This output is high when the TS7513 receives on input RDI
a sinusoidal signal with amplitude lower than N2. Within the
N1 - N2 range, the detection system presents an
hysteresis.
13
RxD
Receive Data
This output is low when a high frequency signal is present
on input RDI, and high when a low frequency signal is
present on input RDI. Without carrier on pin RAI, this output
is high.
19
RxCLK
Receive Clock
This output delivers a clock signal, the frequency of which is
16 times the demodulation rate (± 1 %). The logic state
duration is compatible to the UART clock specification.
6/15
50
Receive Demodulator Input This is input of the demodulator. The analog signals are
passed through level detection comparators and zero
crossing detector.
Input of the decision comparator optimizing discrimination
between high and low frequencies.
TS7513
FUNCTIONAL DESCRIPTION
CLOCK GENERATION
Crystal: NYMPH, NYP 035A - 18
I
I
I
3.579 MHz
.---_-----jXt.IIN
C~j
9
XI.IOUT
c.l.·
CMOSCLOCK---1 XI.IIN
N . C . - - - 1 Xt.1 OUT
T
I
I
I
I
"Capacitor values vary with different crystal manufacturers; typical value: 12 pF
With a minimum number of external components,
the TS7513 performs all the functions of modulation,
demodulation and filtering necessary to meet the requirements of CCID Recommandation V.23.
This circuit is in five parts:
•
•
•
•
•
a modulator
a demodulator
a clock generator
a reference voltage generator
a DTMF filter.
Note: The description of the demodulator also covers a subsystem, external to the circuit proper and
having the following functions (refer to paragraph
CALCULATION OF CIRCUIT ELEMENTS).
• Band-pass filter
• amplification
• slicer.
MODULATOR
When input RTS is low, outputATO delivers a sinusoidal signal, the frequency of which depends on
MCIBC and TxD.
M88TS7513-03
DEMODULATOR
When the analog signal on RDI conforms to certain
criteria, output DCD detects it and output RxD delivers a digital signal, the logic state of which depends
on the analog signal frequency.
CLOCK GENERATOR
This part of the circuit generates from a 3.579 MHz
crystal all the internal clocks necessary to the correct performance of the TS7513 : the clocks for the
switched capacitor filters as well as those for the sinewave generator. The circuit delivers on RxCLK
and TxCLK, the transmit and receive clocks for the
UART. It also delivers on CLK a buffered clock at
3.579 MHz.
REFERENCE VOLTAGE GENERATOR
This part of the circuit generates a regulated voltage
on VREF which is used to adjust detection thresholds. It is independent of power supply values.
DTMF FILTER
This part of the circuit receives a signal from a dual
tone multi-frequency generator and transmit
through ATO a filtered signal when RTS is high.
7/15
51
T57513
FUNCTIONAL CHARACTERISTICS
MODULATOR
• Modulation Conditions:
RTS
ATO
"L"
FSK Modulated Signal
"H"
DTMF Signal
• Transmitted Frequencies :
(for details of frequency selection see PIN DESCRIPTION - ATO)
-
MCIBC
Modulation
Rate
TxD
R.35 and V.23
Recommandations (Hz)
GNDD
V+
75 Bauds
"H"
"L"
390 ± 2
450 ± 2
389.52
450.20
- 0.48
+ 0.20
1200 Bauds
"If'
1300 ±10
2100 ± 10
1299.70
2097.40
- 0.34
- 2.61
"I.:'
Frequency Generated from
Error (Hz)
a 3.579 MHz Crystal
DEMODULATOR
• Frequencies Receive on RDI
Analog signals centered on analog ground are received on input RDI.
RECEIVE DEMODULATION RATE
The receive Demodulation Rate Depends on MCIBC and TEST Input as Follows:
MCIBC
TEST
Demodulation Rate
Frequencies (recommendation V 23)
H
H
1200
1300 ± 16
2100±16
L
H
75
390
450
H
L
75
390
450
L
L
1200
1300 ± 16
2100±16
• Level detection conditions
Input RD I drives a signal detector the output of which
(DCD) is at logic "0" if the level of signal RDI is hi- .
gher than N1. The output of this detector is at logic
"1" if the level of the signal RDI is lower than N2.
This detector has an hysteresis effect: N1/N2.
• Timing detection conditions
The timing performance of the level detector (DCD)
conforms to CCITT Recommendation V.23.
Under normal working conditions, output DCD is :
• low if signal RDI conforms to the level detection
condition,
• high if signal RDI does not conform to the level detection conditions.
8/15
52
Output DCD goes from high to low when signal RDI
conforms to the level detection conditions for 15 ms
or more~ectively 15 ms for 75 bauds).
Output DCD does not go from high to low when signal RDI conforms to the level detection conditions
for 10 ms or less (respectively 10 ms for 75 bauds).
Output DCD goes from low to high when signal RDI
does not conform to the level detection conditions
for 15 ms or more (respectively 30 ms for 75 bauds).
Output DCD does not go from low to high when signal RDI does not conform to the level detection
conditions for 10 ms or less (respectively 20 ms for
75 bauds).
Note: Each transition on the MC/BC input sets the
DCD output to the logical high level and initiate the
detection timing.
TS7513
cr--- ----- - -- ............
,!
Nl
RDI
I
I
I
Jlf
"U
Innnnnr
~UULJ"
I
I
I
I
.....
.....
-
---- -- -'"
IN2
ov
J
.....
T2
TI
RxD
1-----'
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
LL ____ L
M88TS7513-04
Modu~ation
DCD Transition
Rate
~
1200 bds
1
~2
~
75 bds
1
~2
Min.
Typ. (1)
Max.
Unit
10
10
12
12
15
15
ms
ms
10
20
15
30
20
40
ms
ms
(1) TYPical values for TA= 250C and nominal power supply values.
• Demodulated Signal
Under Normal Working Conditions, signal RxD Conforms to the Following Table:
Frequency Received on
RAI (Hz)
Level Received on
RDI
DCD
1200 bds
> N1
> N1
< N2
"L"
"L"
"H"
1300
2100
75 bds
> N1
> N1
< N2
"L"
"L"
"H"
390
450
Demodulation Rate
"X"
"X"
RxD
"H"
"L"
"H"
"H"
"L"
"H"
9/15
53
T57513
REFERENCE VOLTAGE GENERATOR
The VREF output carries a regulated reference voltage.
An external potentiometer, connected between
VREF and GNDA, can supply a regulated voltage
to input RSA.
Adjustement of RSA optimizes the discrimination
between the high and low frequencies.
CALCULATION OF CIRCUIT ELEMENTS
The following factors must be considered in calculating the external components in the TS7513 application:
o
Signal amplification introduced by the receive filter is 1.5 dB/1300 Hz.
The maximum permissible level at RAI input is 4
Vpp (+ 5 dBm).
Note : the reference frequencies are 1300 and 390
Hz.
o
A 2.5 dB hysteresis is introduced within the two signal detection level N 1 and N2, in accordance with
CCID Recommendation V.23.
To be centered, the two limit values of the CARRIER
DETECT signal are therefore:
_ Upper: - 43.dBm, or 15.5 mVpp
_ Lower: - 48 dBm, or 8.7 mVpp
o
A = 43 - 6 -1.5 + 2.1 = 37.6 dB (a ratio of 76).
Note: The peak-limiting filter gain must be adjusted
according to the minimum level on line. With a minimum level of :
_ 38 dBm, A = 32.6 dB
_ 33 dBm, A = 27.6 dB
Typical Peak-limiting Filter Configuration
r------------------~
I
2x1N4148
220pF
For a correct operation of the TS7513 signal detector, the peak-limiting filter must remain linear up
to - 43 dBm on line.
o At input RDI, the upper threshold level N1 of the
signal detector is 2.8 VPP (2.1 dBm), and must
'correspond to the minimum signal level received
from the line transformer. With a duplexer reception gain of + 6 dB, the peak-limiting filter gain is
defined by:
120Kn
o
RFO
M88TS7513·05
ENVIRONMENTAL FUNCTIONAL DESCRIPTION (refer to typical application)
Transmit section
Peak-limiting filter
The transmit section comprises a single operational
amplifier capable of driving a load of 600n , which
can also be used to adjust the transmit level.
This section is made of two operational amplifiers
and performs three functions:
o peak-limiting amplifier, designed to meet the signal detector levels according to the signal received from the phone line.
o High-pass filter (12 dB per octave) to overcome
the DC component of the signal to be demodulated.
o Low-pass filter to protect against the inherent
noise of the receive filter.
Duplexer
This amplifier provides the 2 wire/4 wire separation
function and enables a low cost standard non differential transformer (ratio 1:1) to be used. The duplexer principlze provides a gain of 6 dB for the received signal.
10/15
54
TS7513
TY~CALPERFORMANCES
These typical performances are achieved with the measuring equipment described in Annex I.
• Transmitted spectrum
On output ATO, the transmitted out of band signal
energy must conform to the following specification:
conform to the french CCETT specifications for videotext applications. The characteristics of CCETT
lines used for measurements are given in Annex II.
M88TS7513-06
Odb
~
_ _""
25db
f(kHzl
55db
3.4
1200 bds
Reception
75 bds
Reception
Line 1 (flat)
10 %
4%
Line 2
12 %
4%
Line 3
18%
6%
Line 4
12 %
6%
Line
4
16
200
BIT ERROR RATE
The typical bit error rates versus white noise are as
follows.
• Receiver
Measurement conditions
Local transmit level: - 10 dBm.
Receive level: - 25 dBm, with 511 bit pseudo-random test pattern.
Isochronous distortion
Table below shows the typical isochronous distortion values obtained with the TS7513, which
1200 bds
Reception
SIN
75 bds Reception
SIN
on Line 1
6 dB
BER
2.10- 3
- 1 dB
BER
7.10- 4
on Line 2
7 dB
5.10- 4
-1 dB
7.10- 4
on Line 3
9 dB
5.10- 4
5.10- 4
on Line 4
8 dB
2.10- 4
o dB
o dB
5.10- 4
11/15
55
(J1
O'l
-I
en
-..j
I~
...
c.n
U1
W
r------,
ATOlo
.
I
600 n
I
Transmftleyel~
adjustment
I
J
22 kn
I
I
I
I
;;:
n
::c
!1 ..
o~
:t
i
&
~
..,:2
m
!!lUI
;:
©~
,~,,-~"
+71
i(;;o
11'
I-IT'·~'
Level max:
+ 5 dBm
or ISC
GOUPLEXER : + 6 dB
I/O or
Address
/~"'-Il
\~
IT
T
TS7&13
m
!O
,.1:
@UI
Vee s[andby
fOr RAM
~o
Ilz
• DependIng on WOrk mode.
;;:
OJ
~
~
~
"
I
I
I
L _______ JI
R/Wor_esc
ASar ros
:>
n
~.
li!";!
I
ov
-I
'<
"0
O·
~
»
"0
~
O·
~.
0
"
-I
en
.....
U1
....
W
TS7513
ORDERING INFORMATION
Part Number
Temperature Range
Package
TS7513CP
o to + 70°C
DIP 22
TS75131P
- 40 to + 85°C
DIP 22
PACKAGE MECHANICAL DATA
22 PINS - PLASTIC DIP
mm
0.38
0.508
3,1
3.9
22
Datum
(1)
(2)
Nominal dirrension
True geometrical position
Or
30
mox.
9.4
(11
22 pins
13/15
57
(J1
CD
'ic.n
I
s::
»
"'C
"'C
m m
» Zc
(J)
C
JJ
r - - - - -I
•
,
:
..
I
I
1
:
T87513
Transmit
I
:~
:
I
·
'-t-I.
I
I
~
I '
I
I
I
,
©r"I
~~
----.
,-
: Program '"able : I
I
1
I
I Power supplies I 1
1
I I
15xO.20V 2A I 1
I SODILEC
: :
~;!
Multimeter
~.
~IS
IJiz
INTERFACE
:s::
~
~
't'
IE
1
I
1
I
y'-l
Modems
Emitter
EF7510
TRT LSI1211
:
I _
Generator
Analyser
of Data
for Modem
]
J -=r------]
ii
BUS IEEE = HPIB, GPIB
"
::
Printer
I
I
GADEM·
Application board
Line
Simulator
AEA
S3
1
z
-;
_ _ _ Analog signal
(J)
-<
(J)
•••••• Digital signal
-;
m
s::
'I
t
r :........:
4' I.
FLUKE
8502
Graphic
Plotter
HP 74 OA
I
~I
-r-
ContrOller!
HP 98165
I
750 Ko. RAM:
I
1
..------'-"----',~"
,
!o
--~I_---
' I
:
I
I
Receive:
=
~cn
m
m
s::
I
i
,I
_
Salective
Voltmeter
1
1
Sinus
I
Generator
:
1 ,
I
HP 3586
I 1
HP 3336
,
: 20 Hz· 30 MHz: 1'0 Hz· 21 MHz:
]
• SGS·THOMSON Micrceleclronics DEVELOPMENT
_L
X
-I
CJ)
.....
Ul
.....
(0)
TS7513
APPENDIX 2
CHARACTERISTICS OF TEST LINES
CCETT Line' (Flat!
dB
Z 10
o
ms
H'-t-++++-t-H'-t-++++-HH-I 2
~
o
~
~
0
~
m
~
5
~
Z
o
0
~
~
~
~
~
~
CI
C
~
~
ms
0
~
o
CCETT Line 2 (10 %1
dB
0
A
t~~
:-::.: .:.- : ~ -= -=.:. ~ :=. : ~ - - -
I
J
o
0
T
0
I
1000
~
o
Hz
3000
2000
~
1000
2000
M88TS7513-11
CCETT Lina 3 (90 %1
dB
~
o
!ij
o
,
2
2000
Q
~
~ 5
:II
Z
(5
l=~
Hz
3000
15
~
010
z
o z
1000
o
~
~
o
~
~
~
o
ms
4
z
o
m
!i
o
A
CCETT Line 4 (50 %1
dB
CI
3
Hz
M88TS7513-12
ms
,
3000
UJ
0
A
o
1000
2000
M88TS7513-11
3000
Hz
M88TS7513-12
SPECTRUM OF DTMF SIGNAL
-JOdBm
Il.
1\
t\.....
-70 dBm
- 80 dBin
2
4
68
, kHz
468
·'0 kHz
2468
K17 CCITT specification for telephone set gauge
M88TS7513-13
15/15
59
TS7514
PROGRAMMABLE V.23 MODEM WITH DTMF
ADVANCE DATA
• PROGRAMMABLE MODES:
Modem 75 bps transmit, 1200 bps receive
_ Modem 1200 bps transmit, 75 bps receive
_ DTMF dialing
_ Call status tone detection
_ Auxiliary analog transmit input
_ Analog test loopback
• PROGRAMMABLE FUNCTIONS:
_ Transmission level
_ Hysteresis and detection level
_ Filters (reception and transmission)
_ Line monitoring and buzzer
_ DTMF frequencies
• FIXED COMPROMISE LINE EQUALIZER
• AUTOMATIC BIAS ADJUSTMENT
• INTEGRATED DUPLEXER
• STANDARD LOW COST CRYSTAL
(3.579 MHZ)
• TAX TONE REJECTION
• POWER-UP INITIALIZATION OF REGISTERS
• OPERATES FROM ± 5 VOLTS
P
DIP24
(Plastic Package)
FN
PLCC28
(Plastic Package)
PIN CONNECTIONS
MOD/DTMF
MC/Be
RTS
ENP
DGND
TxD
PRO
X1aliN
c::
c::
c::
c::
C
C
c::
c::
1
24
ATxl
2
23
WLO
3
22
ATO
4
21
v+
5
20
AGND
6
19
v-
7
18
RA01
8
17
RAI1
16
RAI2
15
RA02
14
RFO
13
RDI
XtalOUT
DCD
10
MelBe MOO/DMTF
DESCRIPTION
The TS7514 is an FSK modem which can be programmed for asynchronous half-duplex voice-band
communications on a 2-wire line or full duplex on a
4-wire line. Its programming concept makes it the
ideal component to design low-cost intelligent modems, featuring auto dialing and auto answering.
The TS7514 conforms to CCITT V.23 recommendation.
4
3
2
1
28
M88TS7514·01
WLO
27
26
ENP
DGND
TXD
PRD
Nle
XtaiiN
XtalOUT
The chip incorporates DTMF dialing, line monitoring, tone and dialing detection.
January 1989
1/21
ThiS IS advance information on a new product now in development or undergoing evaluation Details are subject to change without notice
61
TS7514
ARCHITECTURE
Figure 1 : Simplified Block Diagram.
V+
ATxl
DGND
V-
AGND
---0- -0- -0- -0 ----Tx DATA
TxD
CARRIERITONE
FREQUENCY
ATTENUATOR
ATO
ATTENUATOR
WLO
FILTER
GENERATOR
DMTF DATA
INPUT SHIFT
REGISTER
PRD
TS 7514
ENP
RTS
TO
CONTROL
PROGRAMMABLE
FONCTIONS
MC/Be
BUZZER
REGISTERS
MOD/DTMF
CARRIERITONE
DCD
LEVEL DETECTOR
RX
RAil
DATA
RAOI
FSK
RxD
DUPLEXER
DEMODULATOR
RAI2
RA02
ZCO
XlalOUT
XlaiiN
RDI
RFO
M88TS7514-03
2/21
62
T57514
PIN DESCRIPTION
P DIP
Pin n°
PLCC
MOD/DMTF
1
1
MODEM or DMTF Operating Mode Selection
-Also con1l:l2ls write operations to control registers (if MOD/DMTF = 0
and MCIBC = 0).
MCIBC
2
3
Digital Control Input. In MODEM mode, it sets transmission mode to
main or back channel. It also permits selection of dialing or control
registers programming.
RTS
3
4
Reques1.1Q Send
When RTS = 0, the circuit sends an analog signal to the ATO output.
The signal depends on the operating mode selected.
When RTS = 1, the signal
ATO is supp.ressed afterJ1Uirst
zero crossing. When MOD/DMTF = 0 and MCIBC = 0, the RTS pin
acts as a clock for serial data loading into the input register.
Name
Pin n°
Description
sanuo
ENP
4
5
Serial Register Write Select Input. When ENP = 0, the serial register
input is connected to TxD. When ENP = 1, the register input is"
connected to PRD.
DGND
5
6
Digital Ground = OV. All digital signals are referenced to this pin.
TxD
6
7
Digital Input for Transmit or Control Data
PRD
7
8
Digital Input for Control Data. Selected through ENP
XtaliN
8
10
Crystal Oscillator Input. Can be tied to an external clock generator.
F quartz = 3.579 MHz.
XtalOUT
9
11
Crystal Oscillator Output
DCD
10
13
Data Carrier Detect Output
RxD
11
14
Digital Receive Data Output
ZCO
12
15
Zero Crossing Rx Digital Output (ringing detection)
RDI
13
16
Analog Output for the Receive Signal after Filtering or Analog Input
for the Amplifier-limiter.
RFO
14
17
Analog Receive Filter Output
RA02
15
18
A2 Amplifier Output
RAI2
16
20
A2 Amplifier Inverting Input
RAI1
17
21
Al Amplifier Inverting Input
RAOI
18
22
Al Amplifier Output
V-
19
AGND
20
23
24 .
Analog Ground = 0 V. Reference Pin for Analog Signals
Negative Supply Voltage: - 5 V
±5 %
±5 %
V+
21
25
Positive Supply Voltage: + 5 V
ATO
22
26
Analog Transmit Output
WLO
23
27
Analog Output for Line Monitoring and Buzzer
ATxl
24.
28
Direct.Analog Input Transmit Filter
3/21
63
TS7514
FUNCTIONAL DESCRIPTION
The TS7514 circuit is an FSK modem for half-duplex, voice-band asynchronous transmissions on a
2-wire line according to CCID recommendation
V.23 or full duplex on 4 wire-line.
The circuit features DTMF dialing, call status tone
detection and line monitoring in both dialing and
automatic answer modes. A signalling frequency is
available at the line monitoring output (buzzer).
Ring detection is possible by using the signal detection function and bypassing the receive filter. The
receive signal at ZCO output can be filtered in the
associated microprocessor.
The TRANSMIT channel (Tx) includes:
• two programmable frequency generators
• one switched capacitor filter (SCF) with low-pass
or bandpassconfiguration and its associated propagation delay corrector.
• one continuous time low-pass smoothing filter
• one attenuator, programmable from 0 to + 13 dB
by 1 dB steps
• one programmable analog input
The RECEIVE channel (Rx) includes:
• two operational amplifiers for duplexer implementation
• one continuous time low-pass anti-aliasing filter
• one programmable gain amplifier
• one linear compromise equalizer
• one switched capacitor band pass filter (can be set
to either main or back channel)
• one continuous time low pass smoothing filter
• one limiting amplifier
• one correlation demodulator
• one programmable level signal detector
The LINE MONITORING channel includes:
• one buzzer
• one 3-channel multiplexer to select beetwen
_ transmit channel monitoring
_ receive channel monitoring
_ buzzer
• one programmable attenuator
INTERNAL CONTROL
Power up initialization
The TS7514 includes power-up initialization of
control registers. This system sets the ATO transmission output to an infinite attenuation position,
leaving time for the microprocessor to set up the
RPROG input on power up. Control registers are also initialized when V+ is lower than 3 V or V - greater than - 3 V.
Registers
Write access to the DTMF data register and to other
control registers is achi~ved in serial mode through
TxD input or PRD input. Addressing of these 4 bit
registers is indirect. They are accessed through an
8 bit shift~ister addressed when MOD/DTMF = 0
and MC/BC = O. Data sent to the TxD input is strobed on the RTS signal trailing edge.
Serial data is sent to the TxD input, with Least Significant Bit (LSB) first. The 4 Most Significant Bits
(MSB) contain the control register address while the
4 LSB contain associated data.
Data transfer from the input register to the control
register (addressed by the MSB's) is started by the
operati~ode (MODEM or DTMF) selection
(MOD/DTMF = 1 or MC/BC = 1).
• N.B. PRD input can be used instead of TxD (when ENP
~
1).
Figure 2 : Internal Control Register.
MC/BC
\~~~~~~~~~~~~~~~~/
TxD
or
PRO
DATA
ADDRESS
TIME
4/21
64
M88TS7514-04
!!
C
CD
Z
0
w
(5
0
Z
:too
c::
CD
ATxl
~.
ro
0ATO
TxD
I
I
I
1--1
f----j r \
J
h----J r V
I
f-----I
1------1
1---1 '" I
I
I
AC
ATT
I
"
.
CQ
OJ
-I
r
0
m
W
0
0"
::0
A
-I
()
0
=ti
iii· (5
Z
PAD
CQ
ill n0
ENP
3
~.
::J
~
C
CD
Eo
WLO
!!lUI
~~
@.
<)--,
CARRIER
~:i!
,---I . I RAil
DCo
"0
~I:
@UI
RAO!
~O
~Z
MODE
RAI2
A,D
RA02
ZCO
ROt
s::
~
~
Ol
CJ1
~
f-
g
RFO
XtalOUT
XtaiiN
v+
AGND
OGNO
V-
M88TS7514·05
-I
en
....
UI
......
"""
TS7514
OPERATING MODES
The various operating modes are defined by Me/Be
and MOO/OTMF inputs, and by the content of a
control register RPROG.
The TS7514 includes 8 control registers. Access to
each control register is achieved through an au xilliary 8 bit shift register (input register). The input of
that shift register is connected either to TxO or PRO,
depending upon the status of the ENP control pin
(ie when ENP = and ENP = 1 respectively). In both
cases, the RTS input receives the shift clock and sequentialy transfer is controlleQJ>y setting simultaneously MOO/OTMF and Me/Be to 0. The previous
°
internal status and data are memorized during loading of the input register so that transmission continues properly. That feature allows the user to modify transmission level or line monitoring selection
during transmission. The transmit channel operating mode (Modem main or back channel, OTMF)
can only be modified when RTS = 1. When RTS =
0, the ATO transmit output is enabled and the preselected operating mode is activated. When RTS
returns to 1, Modem or DTMF transmission is inhibited after the first zero crossing of the generated
signal.
Transmission (ATO)
Reception (RxD, DCD)
MOD/DTMF
MC/BC
1
1
MODEM, Main Channel
MODEM, Back Channel
1
0
MODEM, Back Channel
MODEM, Main Channel
0
1
DTMF
DCD = Active Tone Detection
lITQ. -500 I:!&Jf RTS = 1 ...
DCD = 1 if RTS = 0
0
0
If RTS = 0 when that configuration occurs, transmission and reception are not
modified.
If RTS = 1 (no signal sent on the line), transmission is not modified and reception
is set up to detect 2100 Hz tone (note 1).
Note1: The decision threshold of the demodulator output is shifted. so that RxD changes from 0 to 1 at 1950 Hz instead of 1700 Hz.
MODEM TRANSMISSION FREQUENCIES
Modulation
Rate
TxD
75 bps
1
0
1200 bps
1
0
CCITT R35 AND V.23
Recommendations (Hz)
390
450
Frequency Generated with
Xtal at 3.579 MHz (Hz)
Error
(Hz)
390.09
450.45
+ 0.09
+ 0.45
1299.76
2099.12
- 0.24
- 0.88
±2
±2
1300 + 10
2100 ± 10
DTMF TRANSMISSION FREQUENCIES
f1
f2
f3
f4
15
f6
17
18
6/21
66
Specifications
DTMF (Hz)
Frequency Generated with
Xtal at 3.579 MHz (Hz)
Dividing
Ratio
Error
(%)
697 ± 1.8 %
770 ± 1.8 %
852 ± 1.8 %
941 ± 1.8 %
1209 ± 1.8 %
1336 ± 1.8 %
1477 ± 1.8 %
1633 ± 1.8 %
699.13
771.45
853.90
940.01
1209.31
1335.65
1479.15
1627.07
5120
4640
4192
3808
2960
2680
2420
2200
+ 0.31
+ 0.19
+ 0.22
- 0.10
+ 0.03
- 0.03
+ 0.15
+ 0.36
T57514
CARRIER LEVEL DETECTOR
_ Output Level Detection conditions
The DCD signal detector output is set to logic state
o if the RMS value of the demodulator input signal
is greater than N1. The DCD output has logic state
1 if the RMS value is less than N2.
The detector has an hysteresis effect: N1 - N2.
_ Timing Detection Requirements
Signal detection time constants at the DCD output
comply with CCID Recommendation V.23.
Modulation
Ratio
DCD
Transition
CCITT V.23
(min)
Min.
Max.
CCITT V.23
(max)
Unit
1200 bps
11
12
10
5
10
5
20
15
20
15
ms
ms
75 bps *
11
12
0
15
15
15
40
40
80
80
ms
ms
• Wide band Rx filter used (Fig 4c.)
Figure 4 : Signal Detection Time Out.
"....... ------ --.. ...... .......
!
.....
I
I
N1
.
I
LINE
,(1
'It
nnnn,.
JULJLJ~
I
I
N2
ov
I
I
I
......
D CD
--- ----- --
11
.., j
12
M88TS7514·06
Note: When delays are bypassed (see RPRX register programming) response time ranges from 0 to 5 ms in receive mode at 1200 bps, and
from 0 to 10 ms at 75 bps.
7/21
67
TS7514
PROGRAMMING REGISTER
RPROG
Address
Data
D7
D6
D5
D4
D3
D2
D1
DO
X
0
0
0
0
0
0
1
0
1
0
X
X
X
X
0
The most significant bit (D 7) is not used when decoding control
register addresses.
0
1
Control register addressing is enabled when D 7 = 0 (see note 2).
1
0
Control register addressing is enabled when D 7 = 1 (see note 2).
0
X
X
Reception positioned.in tha..Qhannel opposite to the transmission
channel controlled by MC/BC
0
1
X
X
Reception positioned in the same channel as transmission
(see note 3).
1
X
X
X
Programming inhibited in normal operating mode. This mode is
used for testing purposes.
0
Note:
Selected Mode (note 1)
1. RPROG is set to 0000 on power-up.
2. Excepted for RPROG register whose address is always 000. regardless of DO and D1.
3. This mode allows either full duplex operation on a 4-wire line, or circuit testing with external TxlRx loopback.
DTMF DIALING DATA REGISTER
RDTMF REGISTER
Tone Frequency (Hz)
Data
Address
D7
D6
D5
D4
D3
D2
D1
DO
LOW
HIGH
P
0
0
1
X
X
X
X
X
X
X
X
0
0
697
0
1
770
1
0
852
1
1
941
X
X
X
X
0
0
0
1
1
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
Nole:
X:
P:
8/21
68
This register is not initialized on power up.
Don't care value.
1,0 or X depending upon RPROG content.
1209
1336
1477
1633
TS7514
DATA REGISTER FOR THE TRANSlIIIlSSION ATTENUATOR
RATE REGISTER
Address
Data
07
06
05
04
P
0
1
0
03
02
Attenuation
01
00
(dB)
Output Transmit
Level (dBm)
On Line Level (dBm)
Coupler Gain (- 6dB)
0
0
0
0
0
+4
-2
0
0
0
1
1
+3
-3
0
0
1
0
2
+2
-4
0
0
1
1
3
+ 1
-5
0
1
0
0
4
0
-6
0
1
0
1
5
- 1
-7
0
1
1
0
6
-2
-8
0
1
1
1
7
-3
-9
1
0
0
0
8
-4
-10
1
0
0
1
9
-5
-11
1
0
1
0
10
-6
- 12
1
0
1
1
11
-7
-13
1
1
0
0
12
1
0
1
13
-8
-9
-14
1
1
1
1
0
Infinite
< - 64
< -70
1
1
1
1
Infinite'
< - 64'
<-70 '
-15
, Power - up configuration.
9/21
69
TS7514
LINE MONITORING PROGRAMMING REGISTER
RWLO REGISTER
Address
Data
Line Monitoring
In Transmit Mode
Relative Level
Line Monitoring
In Receive Mode
Relative Level
(dB)
D7
D6
D5
D4
D3
D2
D1
DO
(dB)
p
0
1
1
0
0
0
0
-10
Signalling
Frequency
Absolute Level (V pp )
Relative Level (dB)
(see note)
0
0
0
1
- 20
0
0
1
0
- 31
0
0
1
1
- 42
0
1
0
0
0
0
1
0
1
- 10
0
1
1
0
- 20
0
1
1
1
- 31
1
0
0
0
0.42 V pp
1
0
0
1
- 10 dB
1
0
1
0
- 20 dB
1
0
1
1
- 31 dB
1
1
X
X
< - 60 dB'
* Power - up configuration
Note: Signalling frequency is a square wave signal at 2982 Hz.
RECEIVE FILTER SELECTION AND GAIN PROGRAMMING REGISTER
RPRF REGISTER
Address
Data
Reception Gain (dB)
(note 1)
Comments
D7
D6
D5
D4
D3
D2
D1
DO
p
1
0
1
X
X
0
0
0
X
X
0
1
+6 '
X
X
1
0
+12
X
X
1
1
0
Rx Channel Band = Tx Channel
Band
Tx to Rx Loopback
- 33 dBm s; Rx Level S; -40dBm
X
0
X
X
X
Receive Fi Iter Selected
X
1
X
X
X
Receive Fi Iter Desabled
1
X
X
X
X
Receive Filter Disconnected from
RDI Output and from
Demodulator. Offset Disabled.
, Power - up configuration.
Notel: Depending on the line length. the received signal can be amplified. Programmable reception gain allows setting a level close to
+ 3dBm at the filter input to take benefit of the maximum filter dynamic range (5/ N ratio). The following requirement must be met:
Max line level + prog. gain ~ + 3 dBm.
10/21
70
TS7514
TRANSMISSION FILTER PROGRAMMING REGISTER
RPTF REGISTER
Address
D7
p
Data
ATO Transmission
D6
D5
D4
D3
D2
D1
DO
1
0
0
0
0
0
0
MODEM or DTMF Signal'
0
0
0
1
ATxl via Smoothing Filter and Attenuator
0
0
1
0
ATxl via Low-pass Filter and Attenuator
0
0
1
1
ATxl via Band-pass Filter and Attenuator
0
1
0
0
In DTMF Mode, Transmision of High Tone Frequency
1
0
0
0
In DTMF Mode, Transmission of Low Tone Frequency
* Power - up configuration.
HYSTERESIS AND SIGNAL DETECTION LEVEL PROGRAMMING REGISTER
RHDL REGISTER
Address
Data
D7
D6
D5
D4
D3
D2
D1
DO
N2 (dBm) (note 1)
See Figure 4
P
1
1
0
X
X
X
X
X
X
X
X
0
0
0
- 43'
0
0
1
- 41
0
1
0
- 39
0
1
1
- 37
1
0
0
- 35
1
0
1
- 33
1
1
0
- 31
1
1
1
- 29
0
X
X
X
X
X
X
X
X
1
N1/N2 (dB)
X
X
X
X
X
X
X
X
3'
3.5
* Power - up configuration.
Note1: Detection low level measured at the demodulator input. The line signal detection level is obtained by reducing the gain ate the filter
input.
RECEIVE CHANNEL PROGRAMMING REGISTER
RPRX REGISTER
Address
Data
Configuration
D7
D6
D5
D4
D3
D2
D1
DO
P
1
1
1
X
X
X
X
X
X
X
X
0
X
X
Low Frequency Wide Band Selected (fig. 4b)'
0
Carrier Level Detector Delay Enabled'
1
X
X
Low Frequency Narrow Band Selected (fig. 4c)
Carrier Level Detector Delay Disabled.
1
Note: In active tone detection mode (MOD/DTMF = 0, Me/Be = 1. RTS = 1 see op. modes). The low frequency wide band IS automatically
selected for the receive channel, whatever the RPRX regis~rogramming value.
After a switch back to modem mode (MOD/DTMF = 1, MelBe = 0 or 1) the RPRX register indicates again the value programmed before the active tone detection mode.
11/21
71
TS7514
ABSOLUTE MAXIMUM RATINGS
Symbol
DGND
Value
Unit
- 0.3 to + 0.3
V
Parameter
DGND (digital ground) to AGND (analog ground)
V+
Supply Voltage V+ to DGND ro AGND
- 0.3 to + 7
V
V-
Supply Voltage V- to DGND or AGND
- 7 to + 0.3
V
VI
Voltage at any Digital Input
DGND - 0.3 to V+ + 0.3
V
Vin
Voltage at any Analog Input
V- 0.3 to V + + 0.3
V
10
Current at any Digital Output
- 20 to + 20
mA
lout
Current at any Analog Output
- 10 to + 10
mA
500
mW
Ptot
Power Dissipation
Top
Operating Temperature Range
Tstg
Storage Temperature Range
Tlead
Lead Temperature (soldering, 10 s)
o to 70
'C
- 65 to + 150
°C
+ 260
°C
If the Maximum Ratings are exceeded, permanent damage may be caused to the device. This is a stress rating only, and functional operation of
the device under these or any other conditions for extended periods may affect device reliability. Standard CMOS handling procedures should be
employed to avoid possible damage to the device.
ELECTRIC OPERATING CHARACTERISTICS
Min_
Typ.
Max.
Unit
V+
Positive Supply Voltage
4.75
5
5.25
V
V-
Negative Supply Voltage
- 5.25
- 5.0
- 4.75
V
1+
V+ Operating Current
-
10
15
mA
I-
V- Operating Current
- 15
-10
-
mA
Symbol
Characteristic
DC AND OPERATING CHARACTERISTICS
Electrical characteristics are guaranteed over the complete temperature range, with typical load except where
otherwise indicated. Typical values are given for:
V+ = +5V, V- = -5V and room temperature
= 25°C
DIGITAL INTERFACE (MOD / OTMF, RTS, OCO, RxO, lCO, TxO, MC / BC, ENP, PRO)
Symbol
Characteristic
Min.
VI L
Input Voltage, Low Level
-
VI H
Input Voltage, High Level
- 2.2
IlL
Input Current, Low Level
DGND < Vi < VIL (max)
II H
Input Current, High Level
VIH (min) < VI < V+
IOL
Output Current Low, Level
IOH
Output Current, High Level
Typ.
-
Max.
Unit
0.8
V
-
-
- 10
-
10
~
- 10
-
10
VOL = 0.4 V
1.6
-
~
mA
VO H =2.8 V
-
-
- 250
~
Unit
ANALOG INTERFACE-PROGRAMMABLE (ATxl)
Symbol
Min.
Typ.
Max.
Yin
Input Voltage Range
- 1.8
-
+ 1.8
V
lin
Input Current (filter output selected)
- 10
-
+ 10
Cin
Input Capacitance (ATT output selected)
-
20
Rin
Input Resistance (ATT output selected)
-
~
pF
-
kn
12/21
72
Characteristic
100
TS7514
ANALOG INTERFACE - TRANSMIT OUTPUT (ATO) (load conditions
RL
= 560 n, C L = 100 pF)
Min.
Typ.
Max.
Unit.
- 250
-
+ 250
mV
Load Capacitance
-
-
100
pF
Load Resistance
-
560
-
Q
- 1.8
-
+ 1.8
V
Symbol
Characteristic
Vos
Output Offset Voltage
CL
RL
Vout
Output Voltage Swing
Rout
Output Resistance
10
-
25
Q
ATO Attenuation Ratio when RTS = 1
70
-
-
dB
-
ANALOG INTERFACE - LINE MONITORING (WLO) (load conditions,
Symbol
Characteristic
RL
= 10 kn, C L = 50 pF)
Min.
Typ.
Max.
Unit
- 250
-
+ 250
mV
Load Capacitance
-
-
100
pF
Load Resistance
10
-
-
kQ
- 1.8
+ 1.8
V
15
Q
Vos
Output Offset Voltage
CL
RL
VOU!
Output Voltage Swing
Rout
Output Resistance
-
-
WLO Attenuation Ratio
70
-
-
dB
Min.
Typ.
Max.
Unit
-2
+2
V
+ 10
-
-
10
~
pF
- 20
-
+ 20
mV
- 1.8
- 0.9
-
+1.8
+ 0.9
V
V
-
-
100
pF
-
-
ANALOG INTERFACE - DUPLEXER (RAI +, RAI -, RAO)
Symbol
Yin
lin
Characteristic
Input Voltage Range RAI+, RAI-
~10
Input Current RAI+, RAI-
Gin
Input Capacitance RAI+, RAI-
Voff
Input Offset Voltage RAI+, RAI-
V out
Output Voltage Swing, RAO
CL = 100 pF, RL = 600 Q
RL = 300 Q
CL
Load Capacitance RA01
RL
Load Resistance RA01
G
DC Voltage Gain in Large Signals, RA91
CL = 100 P F
300
RL = 300 Q
CL=100pF
60
CMRR
Common Mode Rejection Ratio, RA01, RA02
60
PSRR
Supply Voltage Rejection Ratio, RA01, RA02
60
V out
Output Voltage Swing, RA02
CL = 50 pF, RL = 10 kQ
- 2.5
-
CL
Load Capacitance, RA02
RL
Load Resistance, RA02
10
DC Voltage Gain in Large Signals, RA02
60
AVo
-
-
Q
-
dB
-
dB
dB
2.5
V
50
pF
-
kQ
-
dB
13/21
73
TS7514
ANALOG INTERFACE-RECEIVE FILTER OUTPUT (RFO)
AMPLIFIER LIMITER INPt)T (ROI)
Min.
Typ.
Max.
Vin
Input Voltage Range
RPRF = 1 xxx
- 2.2
+ 2.2
V
Rin
Input Resistance
RPRF = 1 xxx
1.5
-
-
kQ
Cin
Input Capacitance
RPRF = 1 xxx
CL
Load Capacitance
RPRF = 1 xxx
-
RL
Load Resistance
Characteristic
Symbol
VOU!
Output Voltage Swing
Rou!
Output Resistance
-
20
pF
50
pF
-
kQ
- 1.8
-
+ 1.8
V
-
-
15
Q
1.5
RL = 1.5 kQ
RL = 50 pF
Unit
DYNAMIC CHARACTERISTICS FOR PROGRAMMING REGISTER ACCESS
N°
Symbo.1
Min.
Max.
Unit
1
tCYC
Cycle Time
600
ns
2
Pwel
Pulse Width, RTS Low
300
-
3
P Weh
Pulse Width, RTS High
300
-
ns
4
t r , tf
RTS Rise and Fall Times
-
50
ns
5
tHCE
Control Input Holding Time
100
ns
6
tseE
Control Input Setup Time
300
7
tsol
TxD or PRO Input Setup Time
200
-
8
tHOI
TxO or PRO Input Hold Time
100
-
ns
9
tww
TWW Input Writing Inpulsion Width (high level)
300
ns
10
tso
TxD Input Setup Time
100
11
tHO
TxD Input Hold Time
100
-
14/21
74
Characteristic
ns
ns
ns
ns
ns
TS7514
INPUT SHIFT REGISTER ACCESS
1 st Case: Programmation without Data Transmission.
2
3
RTS
6
9
4
Me/Be
AND
MOD/DTMF
TxD
OR
PRO
' - -_ _.-1
L-D-1-------j~~-----M88TS7514.07
2st Case: Programmation with TXD During Data Transmission.
RTS
6
5
Me/Be
AND
MOD/DMTF
10
11
M88TS7514-08
15/21
75
TS7514
TRANSMIT FILTER TRANSFER FUNCTION (load conditions: RL
Symbol
Parameter
GAR
Absolute Gain at 2100 Hz
GHH
Gain Relative to Gain at 1700 Hz
Band-pass
< 390
= 390
= 450
= 1100
1100 Hz to 2300
3300
5800
> 16000
Band-pass or Low-pass
DAR
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Group Delay: (modem transmission)
Main Channel: from 380 to 460 Hz
Back Channel: from 1100 to 2300 Hz
= 560 n,
CL
= 100
pF)
Min.
Typ.
Max.
Unit
-
0
-
dB
-
-
- 30
- 35
- 35
+ 0.5
+ 0.5
-3
-
-
-15
- 35
dB
dB
dB
dB
dB
dB
dB
dB
90
1.04
-
110
1.
lis
ms
0.3
0
- 0.5
- 0.5
-
-
-
-
ATTENUATOR TRANSFER FUNCTION
ATT
Absolute Gain for 0 dB Programmed
RAT
Attenuation Relative to Programmed Value
RLT
- 0.5
Attenuation for Programmed Value = =
70
Relative Attenuation between two Consecutive Steps
0.8
0.3
dB
+ 0.5
dB
1.2
dB
dB
TRANSMIT GENERAL CHARACTERISTICS
Modem Amplitude (Att = 0 dB)
390
450
1300
2100
Hz
Hz
Hz
Hz
DTMF Amplitude (Att = 0 dB)
Low Frequency Group
DTMFAmplitude (Att = 0 dB)
Low Frequency Group Versus Low Frequency Group
Psophometric Noise
+
+
+
+
3.5
3.5
3.5
3.5
-
-
+
+
+
+
4.5
4.5
4.5
4.5
dBm
dBm
dBm
dBm
-3
-
-1.5
dBm
+ 1.5
-
+ 2.5
dB
-
250
IlV
- 0.5
-
+ 0.5
dB
-
- 60
- 50
0.5
2.3
2.7
- 50
- 60
dB
dB
dB
dB
dB
dB
dB
RECEIVE FILTER TRANSFER FUNCTION
GAR
Absolute Gain at 1100 Hz - Main Channel
(0 dB programmed)
G RR
Gain Relative to the Gain at 1300 Hz
(0 dB programmed)
< 150 Hz
150 Hz to 450 Hz
1300 Hz
2100 Hz
2300 Hz
5500 Hz to 10000 Hz
> 10000 Hz
16/21
76
-
-
- 0.5
1.1
1.8
-
-
-
-
-
-
TS7514
RECEIVE FILTER TRANSFER FUNCTION (continued)
Symbol
Parameter
Min.
Typ.
Max.
Unit
GAR
Absolute Gain at 420 Hz (back channel - narrow
band)
(0 dB programmed)
0.5
-
+ 0.5
dB
GR R
Gain Relative to Gain at 420 Hz
(0 dB programmed)
-
-
+
+
+
-
50
0.5
0.5
0.5
50
60
dB
dB
dB
dB
dB
dB
-
+ 0.5
dB
-
+
+
+
-
dB
dB
dB
dB
dB
dB
< 150
380
400 Hz to 440
460
1100 Hz to 10000
> 10000
Hz
Hz
Hz
Hz
Hz
Hz
GAR
Absolute Gain at 425 Hz (tone detection or back
channel wide band)
(0 dB programmed)
GRR
Gain Relative to Gain at 425 Hz
(0 dB programmed)
< 112
275
300 Hz to 525
575
1375 to 10 000
> 10 000
Hz
Hz
Hz
Hz
Hz
Hz
- 0.5
-
- 0.5
-
-0.5
-
-
Psophometric Noise
-
50
0.5
0.5
0.5
50
60
300
~V
dB
dB
dB
dB
RECEIVE TRANSFER - GENERAL CHARACTERISTICS
Absolute Filter Gain for:
dB programmed
6 dB programmed
12 dB programmed
a
- 0.5
+ 5.5
+ 11.5
-
+ 0.5
+ 6.5
12.5
- 0.5
-
+ 0.5
Ros
Signal Detection Level Relative to Programmed
Value
RHy
Hysteresis Value
-2
-
-
dB
Signal Level (loop 3) at Reception Input
- 40
- 35
- 33
dBm
LINE MONITORING - GENERAL CHARACTERISTICS (load conditions:
RL
= 10 kQ, C L = 50
pF)
An
Absolute Gain for
-
a
-
RAT
Attenuation Relative to Programmed Value
- 1
-
+ 1
Attenuation for Programmed Value
70
-
Buzzer Signalling Frequency
-
2982
-
Hz
0.38
0.42
0.46
Vpp
FS
a dB Programmed
Signalling Frequency Amplitude at :
0.42 Vpp Programmed
dB
dB
dB
17/21
77
TS7514
Figure 4 : Receive Filter Transfer Characteristics.
FREQUENCY (kH.d
.2
20
1.)
'/.
U//
-10
a,
Z
;;:
CJ
f-
\~
-20
:9-
r
1\
-30
~
-40
/ / . '/, /,
-50
1:1
-EO
V
,/
/ / / , /,
/
-70
a : Main channel
M88TS7514-09
FREQUENCY (kHz)
.2
10
~
-10
+
---
50
-
100
-
f-- - -
-
1
-30
--50
--
;1
-20
-40
- --
T'
20
:: I
~
--liD
I
~,/,
I
1//
-70
b : Back channel· Narrow band
M88TS7514-10
FREQUENCY (kHz)
.2
.1
10
.5
20
50
100
~
f:::i
-10
'{
-20
fiji
}I
-30
·-40
-50
-60
-70
~/
l
V
l0-
~
~
1\
~,~
\
c : BaSIC channel :;: Wide band and tone detection
M88TS7514-11
18/21
78
TS7514
Transmission spectum
Isochronous distortion
At the ATO output, the out-of-band signal power
conforms to the following specifications:
The following table shows typical isochronous distortion obtained with the TS 7514 circuit:
o dB
Line
Reception (1200)
Line 1 (fiat)
10 %
Reception (75)
4%
Line 2
12 %
4%
Line 3
18 %
6%
Line 4
14 %
6 %
25dB
Bit error rate
Typical bit error rates versus white noise are as follows (noise and signal levels are measured without
weighting on the 3001 3400 Hz band) :
!l5dB
3.4
4
16
200
Reception
(1200 bds)
M88TS7514-12
Receiver
Measurement conditions
Local transmit level : -10 dBm on lower chan nel at
75 bps.
Receive level: -25 dBm, with 511 bit pseudo-random test pattern.
Test equipment: TRT sematest.
SIN
Reception
(75 bds)
BER
SIN
BER
Line 1
6 dB
2.10
-3
- 3 dB
2.10
-3
Line 2
7 dB
2.10
-3
- 3 dB
2.10
-3
Line 3
8 dB
2.10
-3
- 3 dB
2.10
-3
Line 4
7 dB
2.10
-3
- 3 dB
2.10
-3
CHARACTERISTICS OF TEST LINES
CCETT LINE (FLAT)
dB
1000
2000
ms
3000
CCETT LINE 2 (10%)
dB
o
Hz
1000
2000
M88TS7514-13
dB
3000
Hz
M88TS7514-14
dB
CCETT LINE 3 (90%)
CCETT LINE 4 t50%)
4
20
z
z
o
3~
15
o
3
15
2 ;:;
>-
2 ;:;
10
>-
«
...J
j
1
w
w
1 0
c.
c.
::l
o
o
::l
o
o
o :3
o
1000
2000
of-
UJ
fUJ
10
o
~
3000 Hz
M88TS751 4-15
1000
2000
3000
:3
Hz
M88TS7514-16
19/21
79
TS7514
TYPICAL APPLICATION INFORMATIONS
+
5V
EXTERNAL
SIGNAL - - - - - ,
L II
-......,---.........~.<)TPHI
ATxl
RAOIr--~"T"""""",
TxD
U.A.R.T.
e
RAil
TPA 270A 18)
1---..----4---+---'
~~C=J"T"""--+--.<) L2
PRO
o
M.c.U.
TRISIL
5600
RxD
ATO
TS
'--"",--<> T PH2
7514
N
MUOC
T
MOD/DTMF
R
ENP
RA02
o
DCD
WLO
RAI2
H..------'
12 K
100 nF 39 K
zeo
~
6.8K
2.2
S
EXT AL ,..--,-----v-....
TO
LOUDSPEAKER
AMPLIFIER
~F
XtalOUT
1-----+-1
OK
2N2222
(*): REGULATION REQUIRED IN FRANCE ONLY
M88TS7514-17
POWER SUPPLIES DECOUPLING AND LAYOUT CONSIDERATIONS
Power supplies to digital systems may contain high
amplitude spikes and other noise. To optimize performances of the TS7514 operating in close proximity to digital systems, supply and ground noise
should be minimized. This involves attention to power supply design and circuit board layout.
operation. These capacitors should be located close
to the TS7514. The electrolytic type capacitors
should be bypassed with ceramic capacitors for improved high frequency performance.
Power supplies connections should be short and direct. Ground loops should be avoided.
The power supplies should be bypassed with tantalu m or electrolytic capacitors to obtain noise free
ORDER CODES
Part Number
TS7514CP
TS7514CFN
20/21
80
Temperature Range
Package
o to + 70°C
o to + 70°C
PLCC 28
DIP 24
TS7514
PACKAGE MECHANICAL DATA
24 PINS - PLASTIC DIP
e = 2,54(2)
4.57mox.
I.
16,1 max.
..!
0.51 mtn
r---~r---,~
0,38
0,508
3,1
3,9
15,24
(2)
IJ
24
Dotum
(1) Nominal dimension
(2) True geometrical position
12
32,6 max.
14
(1)
24
Pins
28 PINS - PLASTIC LEADLESS CHIP CARRIER
11 430
~
0661
0,812
~
min.
28
Pins
0331
0,533
21/21
81
TS7515
SINGLE CHIP DPSK AND FSK MODEM
• MONOLITHIC DEVICE (includes both transmit
and receive filters)
• MIXING ANALOG AND DIGITAL TECHNICS
LOW
COST
CRYSTAL
• STANDARD
(4.9152 MHz)
• AVAILABLE CLOCK FOR MICROPROCESSOR AT 4.9152 MHZ
• LOW POWER DISSIPATION
(CMOS technology)
• SHARP ADJACENT CHANNEL REJECTION
• FIXED COMPROMIZE EQUALIZATION IN
TRANSMITTER AND RECEIVER
• TEST LOOPS. (local analog, local digital and remote digitalloopbacks)
• CARRIER DETECTION OUTPUT
• CCITT AND BELL SIGNALING TONE
• 1200 BPS AND 600 BPS BIT SYNCHRONOUS
FORMAT IN DPSK
• 1200 BPS AND 600 BPS + 1 %, - 2.5 % OR
+ 2.3 %, - 2.5 % CHARACTER ASYNCHRONOUS FORMAT (8, 9, 10 or 11 bits) IN DPSK
• 0 TO 300 BPS IN FSK
• AUTOMATIC DIAL LINE MONITORING CAPABILITY
• BREAK SIGNAL SUPERVISION
• EXTERNAL VOICE BAND TONE FILTERING
AVAILABLE (i.e. 550 Hz or DTMF)
• CMOS AND TTL COMPATIBLE
• DIRECT INTERFACE TO STANDARD MICROPROCESSOR FAMILIES
FORMAT MODE
• OVERSPEED SELECTION IN CHARACTER
ASYNCHRONOUS FORMAT MODE
• SCRAMBLER SELECTION
• 1800 Hz GUARD TONE SELECTION IN V.22
• TEST LOOP SELECTION (DIGITALIANALOG)
P
DIP28
(Plastic Package)
(Ordering Information at the end of the Datasheet)
PIN CONNECTION
DESCRIPTION
The TS7515 is a single chip DPSK and FSK voiceband modem, compatible with the BELL 103, 212A
and CCITT V.22 AlB recommended standards.
MAIN OPERATING MODES
• STANDARD SELECTION (BELL 212A1BELL
103N22)
•
•
•
•
ANSWER TONE SELECTION (21 00 or 2225 Hz)
LOW SPEED MODE SELECTION
CHANNEL SELECTION (answer/originate)
SYNCHRONOUS/ASYNCHRONOUS MODE
SELECTION
• 8 BITS TO 11 BITS WORD LENGTH SELECTION IN CHARACTER ASYNCHRONOUS
December 1988
M88TS7515-01
1/18
83
TS7515
BLOCK DIAGRAM
EXI
TRANSMIT FilTER
WITH FIXED
COMPROMISE
EQUALIZATION
TxD
ATO
TxSClK
RAI
TxClK
RFO
RDI
CARRIER DETECTION
RxD
FSK DEMODULATOR
RxCLK
v+
GND
v~
ClK
2/18
84
RTS
BRS
AiO
n:
ATE
CIB
AIS
ClS
OSE
M88TS7515-02
TS7515
PIN DESCRIPTION
COMMON SECTION (supply, clock, handshaking and mode selection)
Name
Pin
Type
V+
I
1
Positive Power Supply
+5V
V
I
15
Negative Power Supply
-5V
GND
I
20
Ground
XIN
I
27
Oscillator Input
XOUT
a
28
Oscillator Output
ClK
a
26
Clock
This pin delivers a clock signal, the frequency of which is
the crystal frequency. It may be used as a buffered clock
a microcontroller.
C/B
I
3
CCITT/BEll Selection
This three-state input selects the features corresponding
to CCITT or BEll recommandation.
AlS
I
4
Synchronousl
Asynchronous Selection
This three-state input selects the synchronous bit format
or the asynchronous character format mode in DPSK
transmission. This input allows also character length
selection (refer to table 8).
ClS
I
12
Character length
OSE
I
6
Over-speed Selection
This input selects the over-speed in asynchronous
character format mode required by CCITT
recommandation (refer to table 8).
BRS
I
7
Binary Rate Selection
A logic "0" on this input turns chip on1200 bps rate. A
logic "1" turns.Jhe chip on 600 bps or 0-300 bps
according to C/B selection.
AlO
I
19
Answ./Orig. Selection
A logic "0" on this input turns the chip on answer mode.
A logic "1" turns the chip on originate mode.
Tl
I
5
Test loop Selection
This three-state input, selects the test loops mode (refer
to table 6).
N°
Function
Description
OV
This pin corresponds to the input of the oscillator. It is
normally connected to an external crystal but may also
be connected to a pulse generator. The nominal
frequency of the oscillator is 4.9152 MHz.
This pin corresponds to the output of an inverter with
sufficient loop gain to start and maintain the crystal
oscillating.
This JDput selects the character length in conjunction
with AlS input (refer to table 8).
3/18
85
TS7515
PIN DESCRIPTION (continued)
TRANSMIT SECTION
Name
Pin
Type
N°
Function
Description
TxD
I
23
Transmit Data
Data bits to be transmitted are serially presented on this
input. A mark corresponds to a logic "1" and a space to
a logic "0". This data determines which phase or
frequency appears at any instant at the ATO pin in
DPSK or FSK modes.
ATO
0
16
Analog Transmit Output
The analog output is the modulated carrier or the
answer tone to be condition ned and sent over the phone
line mixed with the filtered signal from EXI.
EXI
I
17
External Tone Input
This analog input allows external tone to be filtered by
an interna~-pass filter. Filtered signal appears at ATO
whatever RTS.
ATE
I
2
Answer Tone Enable
A logic "0" on this input instructl?...lhe chip to enter answer
signaling tone mode according CIS selection. A logic "1"
turns the chip on transmit data mode (refer to table 9).
SEI
I
21
Scrambler Enable Input
A logic "0" on this input enables the internal scrambler.
A logic "1" instructs the chip to bypass the scrambler.
TxCLK
0
24
Transmit Clock from
Modem
This output delivers a transmit bit clock generated by
chip in synchronous mode. When TxSCLK is used.
TxCLK is locked on TxSCLK. This output generates a
logic "1" in asynchronous mode.
TxSCLK
I
25
Transmit Clock from
Terminal
This input receives a bit clock supplied by the DTE. This
clock synchronizes the internal transmit clock of the Chip.
In line monitoring mode this input receives the filters
clock.
RTS
I
22
Request to Send Terminal
When a logic "0" is. present on this input. the Chip
delivers on ATO a modulated signal or a signaling tone
and the filtered signal from EXI. When a logic "1" is
present on this input, ATO delivers only the filtered
signal from EXI. When a logic "- 1" is present on this
input, the receive section may be used for line
monitoring and ATO delivers only the filtered signal from
EXI.
4/18
86
TS7515
PIN DESCRIPTION (continued)
RECEIVE SECTION
Name
Pin
Type
N°
Function
Description
RAI
I
18
Receive Analog Input
This input receives the analog signal from the hybrid. It
corresponds to the input of the receive filters.
RFO
0
14
Receive Filter Output
This analog output is the signal received on RAI once
filtered. The receive filter also equalizes the signal for
adaptation to most existing lines. This output must be
connected to RDI through a capacitor to meet the level
detection conditions.
RDI
I
13
DCD
0
11
Data Carrier Detect
RxD
0
8
Receive Data
Data bits demodulated are available serially at this
output.
RxCLK
0
9
Receive Clock
This output delivers a receive bit clock generated by the
chip. In asynchronous mode this clock is 16 times the
modulation rate. In synchronous mode the clock is equal
to the bit rate.
TEST
0
10
Test
Receive Demodulator Input This pin is the input of the carrier detection logic and of
the demodulator
The TS7515 is a general purpose monolithic DPSK
and FSK modem implemented with double poly
CMOS process. It is capable of generating and receiving phase modulated signals at data rates of
1200 bps or 600 bps as well as frequency modulated signals at data rates up to 300 bps on voicegrade telephone lines. It is offered in a 28 or 44 in
plastic package and is able to operate in full-duplex
mode according to three pin selectable standards:
• CCITT V22 A-B.
• Bell 212A with its low speed mode;
• Bell 103.
A logic "0" on this output indicates that a valid carrier
signal is present on RAI. A logic "1" means that no valid
signal is being received. The hysteresis meet standards
recommendation.
This output is an intermediate demodulator output
intented for handshake and test purposes.
All filtering functions required for frequency generation, out-of-band noise rejection and demodulation
are pertormed by on-chip switched capacitor filters.
In phase modulation the modem provides all data
buffering and scrambling functions necessary for bit
synchronous format and asynchronous character
format modes of operation. Internal frequencies are
generated from a 4.9152 MHz crystal reference.
DEVICE OPERATION
TRANSMITTER
The transmitter consists of two analog signal generators followed by switched capacitor and continuous filters. In phase modulation operation mode
the DPSK signal generator is preceded by a selectable scrambler and an asynchronous to synchronous converter is included in character asynchronous format mode.
Tone allocation: the modem on the end of the line
which initiates the call is called the originate modem.
In normal transmission operation it transmits in low
channel and receives in high channel. The other modem is the answer modem which transmits in high
channel and receives in low channel-.
MODULATORS
DPSK modulator: the phase modulation type is differential quadrature four phase shift keying (see table 1). The 1200 bps data stream to be transmitted
is converted into two 300 dibits per second streams
which modulate alternatively two independant carriers. Consequently the base band shaping is included is a 5 bit address ROM which generates samples for a 8 bit switched capacitor DAC at a frequency equals to 8 times the carrier frequency.
5/18
87
T57515
and filter such tones as DTMF signals or special
guard tones (550 Hz) to the transmitted signal.
Table 1 : DPSK Modulation.
BRS
0
TxD
n - 1
0
1
1
Phase
Shift
n
Xl')
0
+ 90
1
0
0
0
1
+ 270
0
+ 180
0
+ 90
1
+ 270
0
0
0
0
n x : don't care.
FKS modulator and tone generator: a frequency
synthesizer provides accurate clocks to a switched
capacitor sine wave generator (see table 2). Phase
continuity is maintained when a frequency shift occurs.
Table 2 : FSK Modulation (BELL 103).
-
A/O
TxD
Standard
frequency
0
0
2025 Hz
1
2225 Hz
0
1070 Hz
1
1270 Hz
1
SCRAMBLER
The scrambler used during phase modulation ensures the transmission of a continuously changing
pattern. This avoids the receiving modem to drop
out of lock on certain continuous repetitious data
patterns.
This scrambler may be disabled during handshaking procedures. In V.22 a special unlocking sequence is performed on 64 spaces pattern at scrambler output.
ASYNCHRONOUS TO SYNCHRONOUS
CONVERTER
The DPSK signal is synchronous in nature but the
modem has both an asynchronous as well as a synchronous mode of operation in DPSK. So a data
buffer is necessary to convert variable rate asynchronous character data to an equivalent bit oriented synchronous data stream. This is done by inserting or deleting stop bits. If serial input data contains
a break signal through one character (including start
and stop bits). One break will be extended to at least
2, M + 3 bits long (where N is the number of transmitted bit/character).
Figure 1 : Transmitted Signal Template.
TRANSMIT FILTERS
To avoid unwanted frequency components to be
echoed by the hybrid in the reception path, to maintain the level of spurious out-of-band signals transmitted to the telephone line below the limits specified by administrations (see figure 1) and to complete statistical amplitude and phase equalization,
the analog signals are processed by ten poles sharp
pass-band switched capacitor filters. The response
of these filters depends on the selected channel
(Answer/Originate) and the selected standard
(BELL 212 - V.22 BELL 103). A continuous filter eliminates parasitic sampling effects. An additional
low-pass filter input is provided. This allows to mix
6/18
88
dBm
o
-23
-L/
~50
I
I
I
I
I
----~-~-----------------
3.4 4.3
16
f (kHz)
M88TS7515·03
TS7515
Table 3 : Output Frequency Deviation.
Standard
Frequency
1070 Hz
Frequency
using 4.91 MHz
1066.7 Hz
% Deviation
from Standard
- 0.3 %
1200 Hz
1270 Hz
1200 Hz
1269.4 Hz
- 0.05 %
1800 Hz
2025 Hz
2100 Hz
1807.1 Hz
+ 0.4 %
Guard Tone V22
2021 Hz
2104. 1 Hz
- 0.2 %
BELL 103 Answer
+ 0.2 %
Answer Tone CCITT
2225 Hz
2226. 1 Hz
+ 0.05 %
2400 Hz
2400 Hz
BELL 103
Answer or Answer Tone BELL
BELL 212A or V22, Answer
Mode
BELL 103 Originate
BELL 212A or V22, Originate
BELL 103 Originate
RECEIVER
The receiver includes two band-pass filters followed
by an amplifier and a hard limiter. Depending on selected standard, the detector output is passed
through a DPSK demodulator or a FSK demodulator. The DPSK demodulator is followed by a descram bier and a selectable synchronous to asynchronous converter. In addition a carrier detector
monitors the level of the received signal.
Tone allocation: in normal transmission operation
the originate modem receives in high channel and
transmits in low channel. The answer modem receives in low channel and transmits in high channel.
RECEIVE FILTERS
The signal delivered by the hybrid to the receive
analog input is a mixture of transmitted signal, received signal and noise with a level in the range from
- 48 dBm to - 0 dBm. Depending on the operating
mode and the selected standard the 20 poles receive switched capacitor band-pass filter selects the
frequency band of the low channel orthe high channel. A ratio of 14/15 is applied on the sampling clock
frequency between FSK and DPSK in the same
operating mode (Answer/Originate). These filter reject out-of-band transmission noise components
and undesirable adjacent channel echo signals
which can be fed from the transmit section into the
receive section. Fixed equalization is included in order to assure low error rate.
AMPLIFIER AND HARD LIMITER
Once filtered the received signal is amplified and fed
to the carrier detector. In order to limit analog parts
in the design all the demodulator techniques used
in the TS7515 are based on zero crossing detection.
So the received signal is just limited before entering
demodulator.
DEMODULATORS
DPSK demodulator: a DPLL is used to recover the
carrier signal. This DPLL has a lock range of ± 2 Hz
but as the incoming carrier may present an offset of
± 7 Hz a second loop allows the first DPLL to lock
on the exact frequency of the carrier with an accuracy of ± 1 Hz and to follow its slow variations in
1200 bands mode only. Then the limited received
signal is mixed through exclusive-Or with the recovered carrier and with the 90 degrees phase shifted
recovered carrier. The results are processed
through four poles Bessel filters wich provide a good
amplitude propagation time compromise. The received sampling clock recovered from these base and
data with a simple DPLL. The received data are
sampled by this clock and then converted into a serial synchronous bit stream.
FSK demodulator: the zero crossing detector output is passed through a shift register whose length
depends on the operating mode (Answer/Originate). The output of the shift register and the detector are mixed into an exlusive Or. Then they are processed through a four poles Bessel filter and a slicer.
TEST OUTPUT
Once demodulated DPSK data are generally processed (cf next paragraph) but during call set-up
procedures or data set testing it is of importante to
monitor the demodulator output. So in DPSK mode
demodulated data are available on TEST pin.
DESCRAMBLER AND SYNCHRONOUS TO
ASYNCHRONOUS CONVERTER
Data coming from the DPSK demodulator are unscrambled. In V.22 the unlocking sequence is detected at descrambler input and the original data are
7/18
89
TS7515
decoded before descrambling. In asynchronous
character format mode of operation a data buffer is
able to detect missing stop bits and reinsert them.
The converter is able to recognize the break signal
and transmits it without modification.
,,
RAJ
ov
)
CARRIER DETECTOR
Whenever valid signals are being received at the input of the demodulator and are acceptable for demodulation, carrier detect output is pulled down. A
delay is timed out before the carrier received or carrier lost signal changes carrier detect output to provide immunity against noise bursts. The modem also provides at least 2 dB of hysteresis between the
carrier ON and the carrier OFF thresholds (see diagram below).
M88TS7515·04
In DPSK mode 105 ms';11 ';205 ms 10 ms';12';24 ms
In FSK mode 105 ms $11,; 205 ms 25 ms $12'; 75 ms
LOOP TEST
lOOP 3
CLOCKS
This loop is called the analog loop. When it is selected the receive filters and the modulators are configured to process the same channel as the transmit
section. The transmit carrier has to be looped back
externally to the receive analog input. This loop allows the user or the DTE to check the satisfactory
working of the local DCE.
In synchronous mode of operation TxClK, TxSClK
and RxClK are respectively working as the V.24 circuits C114, C13 and C15. In asynchronous mode
of operation RxClK can be used as baud rate clock
to synchronize the transmit and the receive sections
of a UART (see table 4).
lOOP 2
This loop is called the digital loop. When it is selected received data, receive clock and data carrier detect signals are respectively and internally looped
back on transmit data, transmit clock from terminal
and request to send. This loop allows the user or
the DTE to check the satisfactory working of the line
and the remote DCE.
OSCilLATOR OUTPUT
The buffered master clock (4.9152 MHz) is made
available at output ClK. It can be use.d as a clock
for a microcontroller.
VOLTAGE REFERENCE
A temperature compensated voltage reference
build with a zener is included in the chip. This voltage is used to calibrate transmit levels and to generate the carrier detection thresholds.
Table 4 : Clock Operation.
AIS
CIB
BRS
TxCLK
RxCLK
Mode
-1
ou 0
- 1
ou 0
0
1
19.2 kHz
1
1
9.6 kHz
V.22
Asynchronous
1
0
1
19.2 kHz
1
1
4.8 kHz
- 1
ou 0
0
1200 Hz
1200 Hz
1
600 Hz
600 Hz
1
0
1200 Hz
1200 Hz
1
1
4.8 kHz
1
8/18
90
BELL 212A
Asynchronous and BELL 103
V.22
Synchronous
,
BELL 212A
Synchronous and BELL 103
TS7515
LINE MONITORING
A special mode has been included in the TS7515 to
monitor the line duJ1ng an automatic call. When this
mode is selected (AiS = 0, RTS = - 1) receive filters
clock is directly derived from TxSCLK which allows
the user to precisely observe broad frequency
bands. Furthermore the DCD performs a fast carrier
detection equivalent to an envelope detection. As
the center frequency of the receive filters is proportional to TxSCLK frequency in this mode it is possible to tune the passband according to the frequency to be detected (see table 5).
TxSCLK: must be created from the TS7515 master
clock (4.9152 MHz).
Table 5.
TxSCLK
210kHz
Originate (A/O
=1)
Answer (A/O
=0)
Center
Frequency
Passband
at 3 dB
Center
Frequency
Passband
at 3 dB
2400 Hz
± 400 Hz
1200 Hz
± 400 Hz
510 Hz
± 85 Hz
Voice
Detection
440 Hz
Detection
45 kHz
76.8 kHz
Application
260 Hz
± 85 Hz
440 Hz
± 150 Hz
330 Hz
Detection
Dial Tone and
Busy Tone
Detection
APPLICATION INFORMATION
In a typical application a microcontroller provides
control and interface to the Data Terminal Equipment (DTE), and a Direct Access Arrangement provides connection to the telephone line. Then the
TS7515 can communicate with the most popular
modems (BELL 103 and BELL 212A) in countries
under BELL standards and popular modems (V.22)
in countries under CCITT recommendations.
POWER SUPPLIES DECOUPLING AND
LAYOUT CONSIDERATIONS
Coupling between analog inputs and digital lines
should be minimized by careful layout. The RDI input (pin 13) is extremely sensitive to noise.
The connection between this point and RFO (pin 14)
through a ceramic type capacitor should be as short
as possible and coupling between this connection
and digital signals should be minimized by careful
layout.
CARRIER RECOVERY LOOP
Power supplies to digital systems may contain high
amplitude spikes and other noise. To optimize performances of the TS7515 operating in close proximity to digital systems, supply and ground noise
should be minimized. This involves attention to power supply design and circuit board layout.
The power supplies should be bypassed with tantalum or electrolytic capacitors to obtain noise free
operation. These capacitors should be located close
to the TS7515. The electrolytic type capacitors
should be bypassed with ceramic capacitors for improved high frequency performance.
Power supplies connections should be short and direct. Ground loops should be avoided.
~
...,I
The carrier recovery loop utilizes a digital phase lock
loop. Performances of the TS7515 depend directly
on this DPLL which needs to be resetted before receiving a DPSK carrier.
Three ways of resetting the DPLL exist on the
TS7515 :
• A trailing edge on DCD .
• Changing FSK mode to DPSK mode or reversely.
• Changing receive channel.
These three ways of resetting the DPLL should be
used in the software included in the microcontroller
to perform the various set-up procedures and
handshakes.
SCiS-THOMSON
[l'jJU~IliI@rn~rn©'irIlil@IlIU~@
9/18
91
TS7515
EXAMPLES
o
V.22-V.25 received signals in Originate mode.
Line - - () () () - - [2100 H z ] - - [unscrambled marks 2400 Hz] [data...
oeD
~_~r---l~
__________
The DPLL is automatically resetted
@
Bell 212A received signals in Originate mode.
Line - - () () () --[2225 Hz] [scrambled marks 2400 Hz] [ data...
u
TL
This transition to "1" is needed to reset the DPLL
TYPICAL PERFORMANCES
The typical performances listed below are achieved
with the environment described in the previous paragraph.
o Dynamic range: 0 dBm to - 45 dBm.
o BER performances :
Conditions:
Xmit level =- 10 dBm,
Rec level = - 25 dBm,
Message 511 bits
on CCETT lines 1, 2, 3, 4
and CNET lines aN and 3 VHF
and US lines C4, C2, and CO.
1200 bps operation
BER 10-3 for a 7 dB SNR
BER 10 -6 for a 11 dB SNR
300 bps operation
10/18
92
o
BER 10.3 for a 3 dB SNR
BER 10-6 for a 8 dB SNR
Specific DPSK performances
Phase hits sensitivity
Phase Jitter
Amplitude hits sensitivity
Offset carrier sensitivity
1800 Hz guard tone
sensitivity
: 25 degree} BER 10 -6
: 35 degree
<
: ± 10 dB
: SNR increase
< + 1 dB
: SNR increase
<+2dB
o Specific FSK performances
Bias Distortion : less than 5 %
Jitter: less than 12 %
~
__1_- ____________
III
m
r
r
...
I\)
OV
-5V
I\)
»
»
"C
10~F
113
L..J .... hJl
114
~....,L-J
0\1
100 nF
"\I
V-
"C
""'""1 TxD
!:
TxSCLK
~
115
<1 I------J
JElIE"
,-- I
10M
~I>b
105
LINE
+
I TxCLK
SEI
»
-I
(5
TIP
LINE
T IBRS
'::1
~<1H-::'1r
104
0
I RxD
RxCLK
':: I
LINE -
RING
Cil
TEST
103
~
106
i2§
125
II:
112
I
~
I
.............. <.I I
RDL
AuTO
• Typical v.lues (crystal: 4.9152 MHz parallel type)
::J
B3
"(3::r
Ri +
::J
0
RTS
ATE
c:
CJl
~
AID
DCD
1
BRS T h
AJO
p IDATA
'<
TS7515
RAI
PD7
PD6
PD5
PD4
142
!O
00
PA7
PA6
PA5
PA4
107
Ii!
co
EF6801
109
~rn
w
pca
106
e»i:
n:
Z
•
1
1 47 nt-"""--'I II""t" ...
5V
68 pF
B2
-I
tJ)
....
UI
......
UI
I ~~
co I~
~
.p.
00
~
~
-5V OV
~
-5V
o
10 ~F
::;
lOCnF
V+
I
TxD
II
~
~
104
PC4
PC3
PC2
SEI
BRS
TEST
103
PCl
PCO
TL
m
106
PA7
PA6
0
~
TS7515
~;!
107
PA5
P05
142
PA3
P03
~Z
lOB
PA2
PAl
PAO
P021---.
POl
POO
II!:
~
125
~
15V~ CLS
L i n ";",,,j AIS
IRa
ADI
L..T l~F
I
(non polarized)
Xtsl
V24
s:
i
~
m
III "lll
Tph/DATA
AID ROL
Auto
83
B2
"0
~
L1
!':RA
RTS
ATE
iliiil
~O
!!'
5V
I\J
EF6801
109
~~
~cn
@.
\J
PB2
I ~~---t-+------l ee.
II
--
n
g
RxD
5V
1'1 \ I
o
~ ~ ~ ~:~
PC7
105
0
::::I
g
IGNOlv-
• Typical values (crystal: 4.9152 MHZ parallel type)
_ LINE
~
......
...
~
~
TS7515
SELECTION MODE TABLES
SYNTHESIS OF DIFFERENT MODES FOR RECEIVE SECTION
Table 6.
C/B
BRS
TL
AID
-1
au 0
X
-1
0
DPSK Originate Loop 3
1
DPSK Answer Loop 3
0
0
DPSK Answer Loop 2
1
DPSK Originate Loop 2
0
DPSK Answer
1
DPSK Originate
0
DPSK Originate Loop 3
1
DPSK Answer Loop 3
0
DPSK Answer Loop 2
1
DPSK Originate Loop 2
0
DPSK Answer
1
1
0
-1
0
1
1
1
DPSK Originate
-1
0
FSK Originate Loop 3
1
FSK Answer Loop 3
0
0
FSK Answer Loop 2
1
FSK Originate Loop 2
1
Answer
Originate
Loop 3
Loop 2
Receive
0
FSK Answer
1
FSK Originate
Mode
v.
22
BELL 212 A
Including
BELL 103
Receive in low channel
Receive in high channel
Analog loop
Digital loop
13/18
95
T57515
SELECTION MODE TABLES (continued)
SYNTHESIS OF DIFFERENT MODES FOR TRANSMIT SECTION
Table 7.
ATE
C/B
BRS
AlO
0
-1
ou 0
X
X
Mode
2100 Hz
1
Answer Tone
2225 Hz
-1
1
Transmit
0
DPSK 1200 bps Answer
1
DPSK 1200 bps Originate
1
0
DPSK 600 bps Answer
1
DPSK 600 bps Originate
0
0
DPSK 1200 bps Answer
1
DPSK 1200 bps Originate
0
DPSK 600 bps Answer
1
DPSK 600 bps Originate
0
DPSK 1200 bps Answer
0
0
1
1
0
1
1
DPSK 1200 bps Originate
0
FSK 0-300 bps Answer
1
FSK 0-300 bps Originate
V.22 without
Guard Tone
V.22 with
1800 Hz Guard
Tone
BELL 212A
Answer : Transmit in high channel
Originate : Transmit in low channel
MODE SELECTION IN PHASE MODULATION TRANSMISSION
Table 8.
-
AlS
CLS
OSE
-1
0
0
Transmission
Mode
8
1
1
0
1
0
0
11
0
9
0
10
1
1
14118
96
0
0
Synchronous
~
SGS·THOMSON
.." I ~UI::II@~LIiI:ii"IiI@OOUCii
Over-speed
+ 1 %, - 2.5 %
+ 2.3 %, - 2.5 %
+ 1 %, - 2.5 %
+ 2.3 %, - 2.5 %
Asynchronous
1
1
Length
+ 1 %, - 2.5 %
+ 2.3 %, - 2.5 %
+ 1 %, - 2.5 %
+ 2.3 %, - 2.5 %
TS7515
SELECTION MODE TABLES (continued)
TEST PIN
Table 9.
ATE
CIS
SRS
0
- 1
ou 0
0
1
0
1
2100 Hz
1
2225 Hz
Test
000
000
000
V.22 DPSK 600 bps
V.22 DPSK 1200 bps
BELL 212A DPSK 1200 bps
1
BELL 103 FSK 0-300 bps
HLO
- 1
0
V.22 without Guard Tone DPSK 1200 bps
1
V.22 without Guard Tone DPSK 600 bps
0
0
V.22 with Guard Tone DPSK 1200 bps
1
V.22 with Guard Tone DPSK 600 bps
0
BELL 212A DPSK 1200 bps
000
000
000
000
000
1
BELL 103 FSK 0-300 bps
HLO
1
000
HLO
Receive
Transmit
: DPSK demodulator output
: Hard limiter output
ABSOLUTE MAXIMUM RATINGS
Symbol
V+
Value
Unit
Supply Voltage
+7
V
V-
Supply Voltage
-7
V
Yin
Analog Input Range
V- 10 kQ)
Ol
Load Capacitance
Rl
Load Resistance
10
0
Signal Distortion
-
kQ
-40
dB
ANALOG INTERFACE, TRANSMIT OUTPUT (ATO) EXI Connected to GND
Symbol
VOF
Parameter
Output Offset Voltage
Typ .•
max.
Unit
-
+ 500
mV
-
-
Output Voltage Swing (Rl/10 kn, Cl = 20 pF)
Vo
Carriers
Vo
Guard Tone 1800 Hz/Data Signal
AT
Min.
- 500
RTS Attenuation
2.2
Vpp
-7
-6
-5
dB
55
-
-
dB
Min.
Typ .•
Max.
Unit
+1
1
J
-
-
5.5
IlF
mVrms
3.1
-
-
mVrms
5
dB
ANALOG INTERFACE, RECEIVE DEMODULATOR INPUT (RDI)
Symbol
Clink ••
NI
N2
N1/N2
Parameter
Serial Capacitor from RFO
Maximum Detection Level to Valid OeD Output
minimum Detection Level to Valid DCD Output
Hysteresis Effect
2
• Typical values are for TA = 25 'C and nominal power supply values .
• • This capacttor must be unpolarized type capacitor
16/18
98
~
SGS·THOMSON
~.,I IiilUlmmE'IIIliI@OOUi:$
TS7515
DYNAMIC CHARACTERISTICS
RECEIVE FILTER TRANSFER CHARACTERISTICS IN DPSK
Low Channel
Symbol
Parameter
Min.
GA
Absolute Passband Gain at
1200 Hz
GR
Relative Gain to GA at
600 Hz
900 Hz
1500 Hz
-
Typ.
.
-
+ 0.8
-
Max.
Unit
-
dB
dB
dB
dB
dB
1800 Hz
-
- 50
2400 Hz
-
- 65
Parameter
Min.
GA
Absolute Passband Gain at
2400 Hz
GR
Relative Gain to GA at
2100 Hz
2700 Hz
1800 Hz
1200 Hz
-
Unit
-
- 0.5
-45
High Channel
Symbol
Max.
dB
dB
dB
dB
dB
dB
+ 9.5
Typ.
.
+ 9.5
- 0.2
-
+ 0.7
- 25
- 68
-
RECEIVE FILTER TRANSFER CHARACTERISTICS IN FSK
In FSK the receive filter is the same as in DPSK but the sampling frequency is multiplied by a 14/15 ratio (Le.
2400 Hz in DPSK becomes 2240 Hz in FSK).
Low Channel
Parameter
Absolute Passband Gain at
1120 Hz
High Channel
Parameter
Absolute Passband Gain at
• Typical values are for TA
~
2240 Hz
25"C and nommal power supply values.
17/18
99
T57515
SUMMARY OF THE DIFFERENCES BETWEEN BELL 212A AND V.22 A-B
Table 10.
Feature
Low Speed Mode
BELL 212A
V.22
0-300 bps FSK
600 bps DPSK
1800 Hz Optional •
Guard Tone
No
Answer Tone
2225 Hz
2100 Hz
Character Length is Asynchronous Mode in DPSK
9,10 bits
8, 9, 10, 11 bits ••
Over Speed Mode in Asynchronous Mode in DPSK
No
Yes **
64 Spaces Detection
No
Yes
• 550 Hz may be externally generated and added to the transmtt signal through EXI.
•• Features of V.22 are available in BELL 212A on the chip.
All these differences are taken into consideration inside the T87515.
ORDERING INFORMATION
Temperature
Range
Package
Oto+70°C
-25 to + 85°C
PLASTIC 28 DIL
PLASTIC 28 DIL
Part Number
TS7515CP
TS75151P
PACKAGE MECHANICAL DATA
28 PINS - PLASTIC DIP
nun
4.S7 ......
3.1
3.9
038
O.SOB
L77mox.
Datum
01 Nominilll dimensioo
(21 Trur ~tm:aI position
Or
38.1 max.
,.
u
(I)
18/18
100
Gi
SGS-ntOMSON
~I ~U©II@mn.Ii©'Il'DiI@OOU©i!I
TS7524
V.22 BIS, V.22, BELL 212, V.21
V.23, BELL 103 MODEM CHIP SET
ADVANCE DATA
• CCITT V.22 BIS COMPATIBLE MODEM CHIP
SET
• CCITT V.21, V.22 AND V.23 COMPATIBLE
MODEM CHIP SET
• BELL 103 AND 212 COMPATIBLE MODEM
CHIPSET
• DIGITAL SIGNAL PROCESSING (TS75240)
AND ANALOG FRONT-END (TS68950/51/52)
IMPLEMENTATION
• QAM, DPSK AND FSK MODULATION AND
DEMODULATION
• DATA TRANSMISSION SPEED:
_ 2400 bps in QAM
_ 1200 or 600 bps in DPSK
_ 1200 or 300 or 75 bps in FSK
• ADAPTIVE EQUALIZATION
• TRANSMIT AND RECEIVE FILTERING
• SHARP ADJACENT CKANNEL REJECTION
• PROGRAMMABLE TRANSMIT OUTPUT
LEVELS
• ON-CHIP 4/2-WIRE HYBRID CAPABILITY
• ANSWER TONE DETECTION AND GENERATION FOR CCITT (2100 Hz), BELL (2225 Hz),
AND TRANS PAC (1650 Hz) RECOMMENDATIONS
• 550 Hz AND 1800 Hz GUARD TONE GENERATION
• DTMF TONE GENERATION
• CALL PROGRESS TONE DETECTION
• SELECTABLE SCRAMBLER AND DESCRAMBLER
• DYNAMIC RECEIVE RANGE 0 TO - 48 dBm
• TYPICAL 10-4 B.E.R. ACHIEVED WITH A 13 dB
SIN RATIO (V.22 BIS)
• ± 10 Hz FREQUENCY OFFSET CAPABILITY
• SUPPLYVOLTAGE:±5V
of modems complying with CCITT V.21, V.22, V.23,
and BELL 103, 212 recommendations. The modem
hardware consists of a DSP chip and a 3-chip analog front end (MAFE). The modem signal processing functions are implemented on a TS68930 programmable digital signal processor, namely
TS75240. The three analog front end chips
(TS68950/51 152) are respective Iy the transm it inte rface, the receive interface and the clock generator.
DESCRIPTION
The SGS-THOMSON Microelectronics multi-standard V.22 bis chip set is a high performance modem
engine, which can operate up to 2400 bps in full duplex over public switched telephone network or leased lines. The TS7524 also allows implementation
DIP28
(Plastic Package)
P
DIP48
(Plastic Package)
T575240
P
DIP24
(Plastic Package)
T568950
P
T568951/2
TS68950/51 152 available in PLCC Packages
(Ordering Information at the end of the datasheet)
December 1988
1/36
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice
101
TS7524
TABLE OF CONTENTS
1.
PIN
1.1.
1.2.
1.3.
2.
FUNCTIONAL DESCRIPTION
2.1. SYSTEM ARCHITECTURE
2.2. PROCESSOR AND ANALOG FRONT END ARRANGEMENT
2.3. OPERATION
2.3.1. ANALOG FRONT END DESCRIPTION
2.3.2. OPERATING MODES
2.3.3. TRANSMIT
2.3.4. RECEIVE
2.4. TS7524 INTERFACE
2.4.1. TS7524 ANALOG INTERFACE
2.4.2. TS7524 DIGITAL INTERFACE
2.4.3. MAILBOX DESCRIPTION
5
5
6
7
7
8
8
9
9
9
9
11
USER INTERFACE
12
12
12
12
14
15
16
17
17
18
20
3.
3.1.
3.2.
3.3.
4.
DESCRIPTION
SYSTEM INTERFACE
ANALOG INTERFACE
CLOCK INTERFACE
COMMAND AND STATUS WORDS
TRANSMIT AND RECEIVE COMMAND WORDS
3.2.1. TRANSMIT COMMAND WORD
DTMF MODE
ANSWER TONE GENERATION
3.2.2. RECEIVE COMMAND WORD
TRANSMIT AND RECEIVE STATUS WORDS
3.3.1. TRANSMIT STATUS WORD
3.3.2. RECEIVE STATUS WORD
CALL PROGRESS AND ANSWER TONE DETECTION
ELECTRICAL SPECIFICATION
4.1. MAXIMUM RATINGS
4.2. DC ELECTRICAL CHARACTERISTICS
4.3. AC ELECTRICAL SPECIFICATIONS
4.3.1. CLOCK AND CONTROL PINS TIMING
4.3.2. CLOCK GENERATOR
4.3.3. LOCAL BUS TIMING (TS75240 AND TS68950/51/52)
4.3.4. SYSTEM BUS TIMING (TS75240 AND CONTROL PROCESSOR)
4.3.5. DAA INTERFACE (DAA AND TS68950/51)
4
4
4
4
20
20
21
22
22
24
25
26
27
5.
PIN CONNECTIONS
27
6.
ORDERING INFORMATION
32
7.
PACKAGE MECHANICAL DATA
33
TABLE OF APPENDICES
2/36
102
A.
TRANSMIT/RECEIVE COMMAND WORDS PROGRAMMING MODEL
35
B.
TRANSMIT/RECEIVE STATUS WORDS PROGRAMMING MODEL
36
TS7524
LIST OF ILLUSTRATIONS
"'!
Figure
Title
Page
TS7524 BLOCK DIAGRAM ............................................................................ 6
2
INTERCONNECTION BETWEEN ANALOG FRONT END
AND DIGITAL SIGNAL PROCESSOR ........................................................... 7
3
MAFE BLOCK DIAGRAM .............................................................................. 8
4
TRANSMIT BLOCK DIAGRAM ..................................................................... 10
5
RECEIVE BLOCK DIAGRAM ........................................................................ 11
6
FUNCTIONAL INTERCONNECT DIAGRAM ................................................. 12
7
FSK TRANSMIT MODE ................................................................................ 15
8
FSK RECEIVE MODE ................................................................................... 20
9
CLOCK AND CONTROL PINS TIMING ........................................................ 23
10
CLOCK GENERATOR ...............................................................................: .. 25
11
LOCAL BUS TIMING DIAGRAM ................................................................... 26
12
SYSTEM BUS TIMING DIAGRAM ................................................................ 27
13
TYPICAL STAND-ALONE APPLICATION ..................................................... 35
LIST OF TABLES
Table
Title
Page
TS7524 OPERATING MODES ....................................................................... 9
2
DIGITAL INTERFACE SiGNALS ................................................................... 11
3
TRANSMIT COMMAND WORD FORMAT .................................................... 13
4
DTMF (dual or single tone programmation) ................................................... 16
5
TONE ENCODING ........................................................................................ 16
6
ANSWER TONE GENERATION ................................................................... 17
7
RECEIVE COMMAND WORD FORMAT ...................................................... 17
8
TRANSMIT STATUS WORD FORMAT ......................................................... 18
9
RECEIVE STATUS WORD FORMAT ........................................................... 19
10
CALL PROCESS AND ANSWER TONE
DETECTION PROGRAMMING MODEL ....................................................... 21
3/36
103
TS7524
1. PIN DESCRIPTION
1.1. SYSTEM INTERFACE
TS75240 (DSP)
Name
ADO.AD7
-
CS
-
RS
-SDS
SRIW
-
IRQ
--RESET
N°
Description
Type
27.34
I/O
System Data Bus: these lines are used for transfer between the TS7524
mailbox and the control processor.
21
I
Chip Select: this input is asserted when the TS7524 is to be accessed by
the control processor.
22
I
Register Select: this signal is used to control the data transfers between
the control processor and the TS7524 mailbox.
20
I
System Data Strobe: synchronizes the transfer between the TS7524
mailbox and the control processor.
19
I
System Read/Write: Control Signal for the TS7524 Mailbox Operation
24
0
Interrupt Request: signal sent to the control processsor to access the
TS7524 mailbox.
23
I
Reset of the TS7524. Must be maintened for a minimum of five clocks
cycles.
1.2. ANALOG INTERFACE
TS68950 (analog front end transmitter)
Description
Analog Transmit Output
TS68951 (analog front end receiver)
Description
Name
N°
Type
RAI
16
I
Receive Analog Input
LEI
17
I
Local Echo Input. This signal is subtracted from signal RAI.
1.3. CLOCK INTERFACE
TS68952 (clock generator)
Name
N°
Type
TxCLK
23
TxRCLK
16
TxCCLK
24
TxMCLK
18
RxCLK
22
RxRCLK
20
RxCCLK
21
RxMCLK
19
0
0
0
0
0
0
0
0
TxSCLK
11
I
4/36
104
Description
Transmit Bit Clock
Transmit Baud Clock
Transmit Conversion Clock
Additional Transmit Clock
Receive Bit Clock
Receive Baud Clock
Receive Conversion Clock
Additional Receive Clock
Transmit Synchro Clock: can be used to synchronize the transmitter on an
external bit clock provided by the RS232C (or V 24) junction.
TS7524
2. FUNCTIONAL DESCRIPTION
2.1 . SYSTEM ARCH ITECTURE
The SGS-THOMSON V.22 bis chip set is a highly
integrated modem engine which provides the functionality and performance requirements for full-duplex 2400 bps modem solutions at a low cost with
excellent performance due to digital signal processing technology. On top of the V.22 bis, the TS7524
chip set also implements the CCITT V.21, V.22,
V.23 and BELL 103, 212 requirements.
The TS75240 is a programmable digital signal processor which implements the complete signal processing functions required to send and receive data according to the standard requirement and utilities such as call progress tone detection, auto-answer tone detection and tone generation.
The TS68950/51/52 MAFE (modem analog front
end) is designed to meet the requirements of the
whole range of voiceband modems.
The MAFE incorporates all the required programmable gain control and clock circuitry, and signal filtering (band-limiting, anti-aliasing and smoothing filters).
Interfacing the TS7524 chip set to a control processor is very straightforward and requires no external
interface circuitry.
The T87524 chip set along with a data access arrangement (DAA), a control processor and a
V.24/RS232 interface and/or an UART, is particularly well-suited for high-performance modern.
The modem supervision is insured by a control processor which implements the handshake monitoring, the auto/manual answer and dialing modes,
the test modes and fall back capability and the
async/sync and sync/async conversion.
Figure 1 : TS7524 Block Diagram.
~--+--t
MAFE
CLKOUT
TS?5240
SYSTEM
BUS
TS68950
1\ ADO-AD?
V
I-->----I-~-
ATO
I
C
-----1-"-1 RESET
-----1-"-1 CS
-----1-"-1 RS
-----1-"-1 SR/W
-----1-"-1 SDS
:
1)- ~~
l\r : iY
f--'---I--- LEI
TS68951
f-->----I---RAI
a
~~
-----y
TS68952
~---+-1IRQ
Terminal clock (TxSCLK)
~---+----,====-----------'L-=-=-:J-t-I
------
Tx and Rx clocks
(TxCLK/TxMCLK)(RxCLK/RxMCLK)
M88TS7524-01
5/36
105
TS7524
2.2. PROCESSOR AND MAFE CHIPS ARRANGEMENT
The TS75240 is connected to the analog front end
chips through its local bus where 08 through 015
are the 8-bit data bus and A8 through A 11 are four
address lines used to address directly the three analog front end chips.
Data-Strobe (OS) is used.1Q. synchronize the transfer of data. Read/Write (RIW) indicates the direction
of data. Four Branch-on-External-Condition signals
(BE3 to BE6) are connected to the different clock signals issued from the clock generator intertace
(TS68952). They are used by the TS75240 to perform its real-time task scheduling.
Figure 2 : Interconnections between the Analog Front End Chips and the Digital Signal
Processor TS75240.
l'
f
l
i YT 'I
T't~Er4
V 58 X TAL
DGND
EX TAL DS
V CC
RI'W
R/IN
Ala
Al1
A9
GSO
<=
To control
-
processor
-
--v'
11-
AD7
015
ADO
08
cs
Rs
--A
ATO
1--,- - - - --
-
reset
BE4
BE3
BE5
BE6
o
DO
EXI
TEST
ZLiNE
f---t>
ClK
DGND
07
v+
X TAL1
Dl
R
R/W
GSO
T868952
R
-
RxCCLK
-"
ClK
CSI
RSD
RSI
RxRCLK
TxRCLK
-
~
~
~
...J~::'::0d
gdd~::?
~~ct~ct
III
r--
------;
~
TxCCLK RxCCLK elK
07
~E
lEI
Receive
Analog
-
Input
DO
EEl
R/W
eso
TxCL K
-
TxSC lK
(Termin al clock)
Notes:
6/36
106
DO non connected on the TS68952
D8 (T575240) connected to DO (MAFE)
D15 (TS75240) connected to D7 (MAFE)~
T568951
CSI
R,C lK
T,M ClK
R,M ClK
-,,
,
07
~E
--
=
SDS
IRQ
-
output
T568950
_ _1_ +r CLrOUTI2
CLCKOUT
SRNi
-
Analog
transmit
RSI
---.1\
-
AGND
CSI
RSO
A8
T875240
v+
v~
TxCCLK
E
RFO
V~
,1 j
~5V
1----
- -
--
P~
V+ AGND
.L ~
M88TS7524-02
TS7524
2.3. OPERATION
•
•
•
•
2.3.1. ANALOG FRONT END DESCRIPTION. The
MAFE (TS68950/1/2) is a modem analog front end
designed in three chips which performs the following
functions controlled by the TS75240 digital signal
processor according to the selected modem standard.
Band-pass programmable filter.
Back channel rejection filter.
Smoothing filter.
0 to 46.5 dB gain amplifier.
Clock Generation Interface (TS68952) :
• Transmit time base with programmable synchronization on data terminal equipment clock or extracted receive clock.
• Programmable receive time base DPLL.
• Four programmable plesiochronous transmit and
receive clocks (rate, sampling, bit and additional
clocks).
Transmit Analog Interface (TS68950) :
• 12-bit DIA converter synchronized with the sampling transmit clock.
• Low-pass and smoothing continuous-time filters
• 0 to 22 dB (or infinite) programmable attenuation.
Receive analog Interface (TS68951) :
• 12-bit ND converter synchronized with the sampling receive clock.
Figure 3 : MAFE Block Diagram.
elK OUT/2
elK
Terminal clock
TxSCLK
j
I
~
Tx 5i nal
DAC
filter
Analog Transmit Output
attenuator
f----
TxRClK
T575240
SIH
Tx-DPLl
RxACLK
acd
RxCCLK
Rx-DPLl
TxCCLK
clock
Local Echo Input
",..Ilrfp;.~<, r
1111
TxCLK
TxMCLK
y~
band pass
and rejection
filter
~l.
{R
R
Z
line
Receive Anolog Input
anti aliasing
tilter
J
C=NE
V
AxCLK
RxMCLK
M88TS7524·03
7/36
107
TS7524
16 standard dual tones coded by a combination of
two frequencies. For specific applications where single tone is required, the DTMF generator provides
the possibility to select either the high frequency or
the low frequency of the standard dual tones.
2.3.2. OPERATING MODES. The modem implementation is fully compatible with different CCITT
and BELL recommendations as listed in table 1. It
may operate at different bit rates, from 75 bps to
2400 bps.
In case of switching from any mode to another, a reset must be applied to the TS75240 reset pin, except during the V.22 bis handshaking (the V.22 bis
and V.22/BELL 212 software modules implemented
in the TS75240 are compatible).
A tone detector and a carrier detector respectively
recognize the different answer tones (CCITT 2100
Hz, BELL 2225 Hz and Transpac 1650 Hz) and call
progress tones (300 Hz to 700 Hz), as well as the
presence or the absence of the on-line carrier signal
(both for PSTN and leased lines).
A DTMF tone generator is provided to output one of
Table 1 : TS7524 Operating Modes.
Bauds
BPS
Duplex
Answer
Orig
V. 22 BIS
600
2400
Full
Yes
Yes
QAM (quadribit)
V. 22
BELL 212
V. 22
600
600
600
1200
1200
600
Full
Full
Full
Yes
Yes
Yes
Yes
Yes
Yes
DPSK (dibit)
DPSK (dibit)
DPSK (bit)
V.21
BELL 103
V. 23
300
300
1200/75
300
300
75/1200
Full
Full
Full
Yes
Yes
Yes
Yes
Yes
Yes
FSK
FSK
FSK
Recommendation
Modulation
2.3.3. TRANSMIT (fig. 4) :
- V.2S, V.21 and BELL 10S
- V.22 bis, V.22 and BELL 212. QAM or DPSK modulation is used to send four (V.22 bis) or two (V.22
and BELL 212) or one (V.22) bit (s) of information
at 600 bauds modulation rate.
The FSK modulation is used to send one bit of information at 1200 or 75 baud (V.23) or 300 bauds
(V.21 and Bell 103).
The scrambler can be bypassed, as user's option
usually during the handshake procedure. After coding, a raised cosine filter (roll-off factor 0.75) performs pulse shaping and provides a 45 dB rejection
between the channels so as to comply with V.22 bis,
V.22 and BELL 212 standard requirements. When
required, a 1800 Hz or 550 Hz guard tone can be
added to the transmitted signal.
The DTMF generator outputs one of 16 standard
dual tones synthetized by the TS75240 and selected by a 4-bit binary value as described later. Each
tone is coded by a combination of two frequencies.
The DTMF generator may be programmed to generate one tone at a time.
The transmit attenuation level is programmable over
a 23 dB dynamic range by 1 dB steps.
8/36
108
-OTMF
ru
SCS·THOMSON
':'11 [jij]OI!:IiiI©~~~I!:1iIiil©IIlDI!:®
T57524
Figure 4 : TS7524 Transmit Block Diagram.
-_'_1
,-----ATTENUATION - - - - - - - - - - - - - - - - - - - - __
TxCCLK
_ _ _ _
_ _ _ _
J_ ___
TxRCLK - - - - - - - - - - - - - - - - - - - - - , _
___
,
DPSK
QAM
command
interface
FSK
: QAM : V.22 Bis
DTMF
: DPSK: V.22. Bell 212
,
I FSK : V.23. V.21. Beil103
,
~ ~~~~ - -
-
-:
-------M88TS7524-04
2.3.4. RECEIVE (fig. 5) :
2.4. TS7524 INTERFACE (fig. 6)
- V.22 bis, V.22 and BELL 212.
2.4.1. TS7524 ANALOG INTERFACE. The transmit
signal at the line interface (output ATO) is programmable over a 23 dB dynamic range by 1 dB steps
through the TS75240 mailbox.
QAM or DPSK demodulation is used to receive four
(V.22 bis) or two (V.22 and BELL 212) or one (V.22)
bit (s) of information at 600 bauds.
- V.23, V.21 and BELL 103
The FSK demodulation is used to receive one bit of
information at 1200 or 75 bauds (V.23) or 300 bauds
(V.21 and BELL 103).
- Tone Detection
The receive signal at the line interface (input RAI)
can have a dynamic range from 0 to - 48 dBm.
With a simple circuit using a minimum of external
components, the TS7524 can transmit with a level
of - 12 dBm on line and provide the adequate rejection of the transmit signal on the receive channel.
The TS7524 recognizes the following tones:
- 2100 Hz and 2225 Hz answer tone detection
, - 1650 Hz V.21 Transpac answer tone detection
. - 300 to 700 Hz call progress tone detection
!
Adaptive equalization, DPLL and AGC compensate
for line impairments, frequency offset, group delay
and amplitude distorsions.
Efficient rythm recovery algorithms provides accurate sampling on the receive signal with a variation
upto±2.10.
2.4.2. TS7524 DIGITAL INTERFACE. The interface
between the TS7524 chip set and the control processor is managed by the TS75240 via its system
bus and internal mailbox. The mailbox allows the
control processor to read/write three consecutive
data-bytes through ADO-AD7 bus. The mailbox exchanges follows the protocol described in fig. 2.4.3.
The TS75240 digital interface signals, and their definition are listed in table 2.
Decoded data are provided in scrambled or descram bled format.
9/36
109
TS7524
Figure 5 : TS7524 : Receive Block Diagram.
RXCCLK ________________________________________~======================~l
RxRCLK
------1
,_
, ,,
-J----
~LEI
loss discrimination
:~-RAI
discriminator
QAM
DPSK
FSK
: V.22 Bis
: V. 22 Bell 212
: V. 23, V. 21, Bell 103.
M88TS7524·05
Table 2 : Digital Interface Signals.
Interface
Signals
Inputloutput
1/0
ADO
AD1
AD2
AD3
AD4
AD5
AD6
AD7
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
SR/W
SDS
IRQ
CS
RS
Reset
I
I
TxMCLK *
RxMCLK *
TxCLK
RxCLK
TxSCLK
*
a
I
I
I
a
a
a
a
I
Signal Definition
Data-Bus (LSB)
Data-Bus
Data-Bus
Data-Bus
Data-Bus
Data-Bus
Data-Bus
Data-Bus (MSB)
Readlwrite Signal
Data Strobe
Mailbox Handshake
TS75240 Chip Select
Register Select
TS75240 Reset
Additional Transmit (2400 Hz) Clock
Additional Receive (2400 Hz) Clock
Transmit Bit Rate Clock
Receive Bit Rate Clock
Transmit Terminal Clock
These additional clocks may be used for specific applications.
10/36
110
TS7524
Figure 6 : Functional Interconnect Diagram.
TS7524
TxMCLK
RxMCLK
ATO
LEI
RAI
v.24 interface
I· .
!---------
Line
Interface
~
Telephone
Line
,-113
114
115
TxSCLK
TxCLK
RxCLK
j j
data
ADO·AD?
103
104
109
Control
Ctrl
Processor
CS
RS
SDS
SR/W
~
IRO
CLKOUT
+5VA
·5VA
AGND
+5
DGND
1-:-
1-
I~
Power
Supply
rnmil
M88TS7524-06
2.4.3. MAILBOX DESCRIPTION. The TS75240 requires the attention of the control processor at regular intervals in orderto perform properly. The control
processor must interact with the modem chip set in
a timely manner to avoid improper operation.
To initialize communication exchanges between the
TS7524 and the control processor, the TS7524 RESET pin must be maintained in its active (low) state
during at least 870 ns (5 clock cycles) by the microprocessor. At the end of reset, the 75240 gives the
mailbox control to the processor.
It is also recommended to maintain the RESET in
its active state until the exchanges can start.
Following a reset the status word read from the mailbox is not significant, and the content of the command word is ignored. So, the first mailbox exchange is a dummy exchange.
The mailbox located intemally to the TS75240 DSP
contains 3-bytes input and 3-bytes output shift registers. The TS75240 has an internal flag which indicates whether the TS75240 or the control processor has access to the mailbox. The TS75240 can
relinquish its accessability to the mailbox by setting
this internal flag, but it can no longer regain access
to the mailbox as the flag is reset only after the
control processor relinquishes its accessability to
the mailbox.
The access protocol and system bus transfers are
controlled by an internal I/O sequencer within the
TS75240 which operates as follows:
1/ The mailbox is made available to the control Q!Q.::
cessor by the TS75240 which drives the IRQ
mailbox handshake signal to the active (low)
state.
2/ The control processor detects IRQ active and
dummy reads the mailbox by forcing the
TS75240 chip select (CS) and registe.L.select
(RS) low along with the write signal (SRIW) high.
The activated data strobe signal (SDS = 0) validates the above signals.
3/ The TS75240 detects the dummy read of its mailbox via the control signals mentioned in step 2
and negates IRQ mailbox handshake signal after 1 fLS (at least 5 clock cycles).
4/ The control processor detects the negation of IRQ
indicating that the TS75240 mailbox is available
for data transfers. The control processor reads
three bytes (one status word) and then writes
three byteS (one command word) in the mailbox.
If the status word is a transmit status word, then
a transmit command word must be written into
the mailbox. Else, a receive command word must
be written into the mailbox.
5/ The control processor ends the exchange protocol performing a dummy read of the mailbox as
in step 2 but with RS in the high state.
The TS75240 then owns the mailbox and can make
it available again to the control processor as in
step 1.
11/36
111
TS7524
3. USER INTERFACE
3.1 . COMMAND AN D STATUS WORDS
The TS7524 chip set functionalities and status reporting are managed by the control processor
through the TS75240 mailbox, according to the protocol outlined earlier.
The command words are issued by the control processor and received by the TS75240.
3.2. TRANSMIT
WORDS
AND
RECEIVE COMMAND
Both the transmit and receive command words are
built on the same programming model, but have to
be programmed completely independently.
3.2.1. TRANSMIT COMMAND WORD. The table 3
shows the transmit command word (three bytes)
programmation and transmit functionalities.
The command words provide the necessary functional control of the TS7524 chip set.
The status words are issued by the TS75240 and
delivered to the control processor.
The status words provide the status reporting.
Each command and status word of both the transmit and receive part comprises three bytes as described in the following sections.
The control processor must be able to handle:
• one mailbox transfer per transmit baud period
and,
• one mailbox transfer per receive baud period.
• these transfers are plesiochronous. (Tx and Rx
clocks have the same nominal frequency but can
shift of ± 1.10-4 , so the phase relation between
Tx and Rx is time varying).
The first byte of the transmit command word permits
the choice of the DTM F mode or the selection of the
requested CCITT (with or without guard tone) or
BELL standards.
The second byte contains the transmit parameters
information register.
The third byte is the transmit data register of DTMF
tone selection register. In this byte is also included
the transmit enable bit which instructs the TS7524
to transmit (or not) data to the line.
To manage the TS7524 in an efficient way, it is recommended to work with a table stored in the control
processor memory space. This table will reflect the
three bytes of the transmit command word and will
be sent from the control processor to the TS7524 at
Table 3 : Transmit Command Word Format.
BIT
First Byte
0
Transmit Mode Selection
1
f--2
f---
0000 : Modem Disabled
0001 : V.22 Bis
0010: V.22 0011 : B212
0100 : V.23 0101 : V.21
0110: Bell 103
0111 : D.T.M.F.
-
3
4
Transmit Signalling
5
01 : 550 Hz
11 : 1800 Hz
Transmit (0)
DO
f---
Transmit
Attenuation
7
--
Scrambler (ON/OFF)
Reserved
Reserved
ANSW/ORIG or DTMF
V.22 Binary Rate Select
orDTMF
Note: All the "RESERVED" bits must be cleared to "0" by the user.
12/36
112
D1
D
P
S
Q
A
M
K
F
S
D
T
M
F
D2
0
D3
0
D4
0
0
0
D5
0
0
0
-
f--- 00 : Signalling Disabled
6
Third Byte
Second Byte
K
-
Transmit Enable
r---
TS7524
"1
each transmit baud. In this table, the different fields
could be programmed according to the CCITT or
BELL standard needed taking into account the
transmit parameters. Once the contents of the first
and second byte have been determined for the
whole transmission, only the transmit data field in
the third byte has to be updated in the table. So, at
each transmit baud, the TS75240 will receive the
complete three bytes, will check them and send the
data.
FIRST BYTE:
Bit 3, 2, 1 and 0 : Transmit mode selection
These bits select the standard to use or the DTMF
mode
0000
0001 to0110
0111
: Modem disabled
: Transmit mode selection
: DTMF.ln this mode, the number
which may be dialed is given by
the proper binary combination of
bits 4,3,2 and 1 in the third byte.
Refer to paragraph "DTMFmode"
for detailed information.
• in QAM (V.22 bis) and DPSK (V.22 and BELL
212) modes
- 5 dBm when transmission on low channel
- 4 dBm when transmission on high channel
with guard tone composed by :
- 5 dBm (signal)
- 12 dBm (guard tone)
- 5 dBm when transmission on high channel
without guard tone
• - 4 dBm in DTMF mode composed by
- 5 dBm (high frequency)
- 7 dBm (low frequency)
These are maximum levels which can be decreased
by programming the transmit attenuation, with attenuation levels falling within 0 dB (00000) and 23 dB
(10111) range, selectable in 1 dB steps.
Selection within 11000 to 11111 correspond to an
infinite attenuation.
At power-on, or after a reset applied on the reset pin
of the TS75240, an infinite attenuation is automatically programmed.
Bit 5 : Scrambler
Bit 5 and 4 : Transmit Signalling
The TS7524 incorporates an auto-synchronized
scrambler/descrambler in accordance with CCITT
V.22 bis and V.22 and BELL 212 recommendation.
These bits represent the tone to send regarding the
requested functionalities.
The scrambler is enabled (1) or disabled (0) by programming the bit 5.
00
01 or 11
When the scrambler is enabled, the input data is
scrambled by dividing the data by a generating polynomial as defined in the V.22 bis and V.22 recommendations.
Other bit codes are reserved.
10
: Signalling disabled
: Guard tone 550 Hz or 1800 Hz which
can be added to the modulated signal.
: Reserved
Bit 6 : Reserved
When the scrambler is disabled, the input data is
routed around the scrambler in the transmit path.
Bit 7: ANSWER / ORIGINA TE or DTMF
Bit 6 : Reserved
This bit has two main functions. Its first function is
to select the answer or originate mode. The second
function is used in DTMF mode as explained in details in paragraph "DTMF mode".
Bit 7: V.22 binary rate selection or DTMF
In ANSWER/ORIGINATE mode, the bit 7 cleared to
zero selects the answer mode (transmit in high
channel). The bit 7 set to one selects the originate
mode (transmit in low channel).
This bit has two main functions. Its first function allows the possibility to select the lowest binary rate
(V.22 at 600 bps) when set to one, or the highest binary rate (V.22 at 1200 bps) when cleared to zero.
The second function is used in DTMF mode as explained in details in paragraph "DTMF mode".
THIRD BYTE:
SECOND BYTE:
Bit 0 : Transmit
Bit 4, 3, 2, 1, and 0 : Transmit attenuation
The transmit levels without attenuation at the transmit interface output (ATO) on 600 ohms are as follows:
• in FSK modes (V.23, V.21 and BELL 103)
-OdBm
This bit indicates the nature of the command word.
It must be cleared to zero by the control processor
to indicate to the TS7524 that the command word is
a transmit command word, and that the 3-bytes written in the mailbox contain transmit information .
13/36
113
TS7524
Bit 6 Thru 1 : Transmitted data or DTMF tone selection. These bits have two main functions. The first
function is to represent the data which will be sent
according to the appropriate mode. The second
function, used in DTMF mode, is to select by programming the bits 4, 3, 2, and 1 the generated tone
which will be used to dial the proper number as
shown in paragraph "DTMF mode" in table 5.
In these modes, the mailbox exchanges are executed at the rate of 600 exchanges per second.
In FSK modes (V.21, V.23, and BELL 103) all the 6
bits (bit 6 thru 1) are used to represent the binary
value of six samples of the transmitted signal. In
these modes, the mailbox exchanges are executed
at the rate of 1200 exchanges per second. Consequently, to perform a serial to parallel conversion the
control processor has to sample the 103 circuit of
the V.24/RS232 junction at 7.2 kHz which is the
sampling clock frequency (TxCCLK).
In QAM (V.22 bis) or DPSK (V.22 or BELL 212)
modes, the bits 4, 3, 2, and 1 represent the data sent
by the TS7524. According to the selected mode, up
to 4 bits will be used:
The bit 1 (which correspond to DO) is the first sample of the signal transmitted over the line as shown
in figure 7.
_ In V.22 bis, each symbol (baud) is coded by
4 bits (quadribit)
_ In V.22 at 1200 bps and BELL 212 modes,
each symbol is coded by 2 bits (dibit)
_ In V.22 at 600 bps, each symbol is coded by
only one bit.
Bit 7 : transmit enable
This bit low instructs the TS7524 to send data.
Figure 7 : FSK Mode.
TRjlNSMITTED
TO
~
(1/1200)8
SIGNAL ON THE
103 CIRCUIT
TO
((
,
,
)J
,
,
,
((
,
,
,
,
,
:
,,, :,
,
:
,
,
,
,
t~=(1/7200)s-----+-----1
,
,
I
I
,
,
,
,
,,
,
,
,
,
,
((
I
I
t
J)
I
11 11 10 10 10 10 1-- LOADED IN THE MAILBOX
DO
05
BY THE CONTROL PROCESSOR
M88TS7524·07
DTMFMODE
The DTMF generator outputs one of 16 standard
dual-tones. For specific applications where single
tone is required, the DTMF generator provides the
possibility to select either the high frequency or the
low frequency of the standard dual tones.
All the bytes used to program the DTMF mode and
mentioned in this section are those of the transmit
command word.
The DTMF mode is selected by programming bits 3
to 0 in the first byte.
Choosing the dual-tone mode, which is the normal
operating mode, is done with bit 7 in the second byte
cleared to zero. The DTMF generator then outputs
one of the sixteen standard dual tones selected
14/36
114
through bits 4 to 1 in the third byte as shown in table 5.
The single-tone mode is selected by setting to 1 the
bit 7 in the second byte. This mode is used in specific cases where one frequency is to be generated.
After one frequency pair is selected through bits 4
to 1 in the third byte as shown in table 5, the choice
of the higher or lower frequency is made through bit
7 of the first byte. When bit 7 is set to 1 (respectively 0), the lower (respectively higher) frequency is generated.
In DTMF mode, the mailbox exchanges are executed at the rate of 1200 exchanges per second.
The programming of DTMF mode is summarized in
table 4.
TS7524
Table 4: DTMF (dual or single tone) Programmation.
DTMF
First Byte
Bits 3, 2, 1, 0
2nd Byte
Bit 7
0111
0
Dual-tone
Single-tone
Bit 7
First Byte
Bits 3, 2, 1, 0
Third Byte
Bits 4, 3, 2, 1
4-bit Binary Value
Coding one of 16
Dual Tone
2nd Byte
Bit 7
Third Byte
Bits 4, 3, 2, 1
High Frequency
Selected
0
0111
1
4-bit Binary Value
Coding one of 16
Dual Tone (high)
Low Frequency
Selected
1
0111
1
4-bit Binary Value
Coding one of 16
Dual Tone (low)
In DTMF mode the transmit levels at the analog
transmit interface output (ATO) are respectively
-5 dBmforthe high group frequencies, and-7 dBm
for the low group frequencies. These are maximum
levels and can be decreased by programming the
transmit attenuation in the second byte.
Table 5 : Tone Encoding.
Number
to Dial
0
1
2
3
4
5
6
7
8
9
A
B
C
D
.
#
DTM F Code in Third Byte Generated Tones (Hz)
Bit4
Bit3
Bit2
Bit1
Low
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
941
697
697
697
770
770
770
852
852
852
697
770
852
941
941
941
High
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
1336
1209
1336
1477
1209
1336
1477
1209
1336
1477
1633
1633
1633
1633
1209
1477
The accuracy of the frequencies is ± 10.4
The harmonic rejection level is at - 65 dB.
ANSWER TONE GENERATION
The TS7524 chip set may generate four different
standard frequencies which represent the usual
auto answer tones.
_ 1300 Hz : V.23 Automatic connection tone
_ 1650 Hz : V.21 Transpac specific answer tone
_ 2100 Hz : CCITT V.22 bis, V.22, V.23 and
V.21 answer tone
_ 2225 Hz : BELL 212 and BELL 103 answer
tone
For answer tone generation, mailbox exchanges are
executed at the rate of 1200 exchanges/second.
15/36
115
TS7524
Table 6 : Answer Tone Generation.
FSK Mode
to Use
Tone
1300
1650
2100
2225
Hz
Hz
Hz
Hz
V. 23
V. 21
V. 23
B103
Bit 7
Answer
Answer
Answer
Answer
First Byte
Bits 3, 2, 1 , 0
0100
0101
0100
0110
0
0
0
0
3.2.2. RECEIVE COMMAND WORD. In the receive
command word, the first byte permits the choice of
the call progress and answer tone detection modes
or the selection of the requested CCITT or BELL
standards.
The second byte defines additional receive parameters.
The third byte informs the TS7524 that the command word is a receive command word.
Third Byte
Bits 6, 5, 4, 3, 2, 1
111
111
000
111
111
111
000
111
processor memory space. This table will reflect the
three bytes of the receive command word and will
be sent from the memory by the control processor
to the TS7524 at each receive baud. In this table,
the different fields could be programmed according
to the CCITT or BELL standard needed taking into
account the receive parameters. At each receive
baud, the TS75240 will receive and processes the
complete three bytes.
To manage the TS7524 in an efficient way, it is recommended to work with a table stored in the control
Table 7 : Receive Command Word Format.
First Byte
BIT
0
Second Byte
Receive Mode Selection
Third Byte
Receive (1)
f--
0000 : Modem Disabled
1 0001 : V.22 Bis
f-- 0010:V.220011 :B212
2
0100: V.23 0101 : V.21
f - - 0110 : Bell 103
3
0111 : Call Prog. 1 Answer Tone
4
Reserved
Reserved
Answer Tone Selection
5
Tx Synchronization
6
Carrier Detect Level
Descrambler (ON/OFF)
Reserved
7
Answer/originate
V.22 Binary Rate Select
Note: All the "RESERVED" bits must be cleared to "0" by the user.
FIRST BYTE:
Bit 4 : Answer tone selection
Bit 3, 2, 1, and 0 : Receive mode selection
This bit defines the answer tone to be detected. It
selects either 1650 Hz (Transpac) or 21 00/2225 Hz
answer tone. When high, the detect answer tone is
1650 Hz. When low, the detect answer tone is
2100/2225 Hz.
These bits select the standard to use or the call progress and answer tone detection mode.
0000
0001 to 0110
0111
: Modem disabled
: Receive mode selection
: Call progress and answer tone
detection. mode. In this mode the
TS7524 recognizes different tones
as explained in paragraph "call progress and answer tone detection"
Other bit codes are reserved.
16/36
116
Bit 5: Tx synchronization signal programming
This bit allows synchronization of all transmit clocks
on a selected source. When bit 5 is set to 1 , all the
TS7524 transmit clocks (TxCLK, TxCCLK,
TxRCLK, TxMCLK) are synchronized on TxSCLK
input (typically a terminal clock signal coming from
TS7524
the V.24/RS232 interface). This avoids overspeed
and maintains a complete synchronization during
the transmission. If there is no signal on TxSCLK
coming from the terminal clock. the transmit clocks
are free-running at their nominal frequencies.
When the bit 5 is set to 0, the TS7524 transmit clocks
are synchronized on the receive clocks. This possibility may be used for remote digitalloopback.
Bit 6 : Carrier detection level
The TS7524 can be used both on the public switched telephone network (PSTN) and with leased
lines.
When the bit 6 is set to 0, the carrier detection threshold are:
- 43 and - 48 dBm (PSTN).
When the bit 6 is set to 1, the carrier detection threshold are:
- 33 and - 38 dBm (leased lines).
scrambler/descrambler in accordance with CCITT
V.22 bis and V.22 and BELL 212 recommendation.
The descrambler is enabled when bit 5 is set to 1,
or disabled when bit 5 is set to O.
When the descrambler is enabled, the data stream
is multiplied by the same polynomial that divided the
data at the scrambler in the transmission path.
When the descrambler is disabled, the data stream
is routed around the descrambler in the receive
path.
Bit 6 : Reserved (must be cleared to 0)
Bit 7 : V.22 binary rate select
This bit allows the possibility to select the lowest binary rate (V.22 at 600 bps) when set to one, or the
highest binary rate (V.22 at 1200 bps) when set to
zero.
THIRD BYTE:
Bit 7 : Answer I originate
Bit 0 : Receive
The bit 7 cleared to zero selects the answer mode
(receive in low channel). The bit 7 set to one selects
the originate mode (receive in high channel).
This bit indicatE1s the nature of the command word.
It must be set to one to indicate to the TS7524 that
the command word is a receive command word.
This involves that the 3-bytes written in the mailbox
by the control processor to the TS7524 contain receive command information.
SECOND BYTE:
Bit 4,3,2, 1, and 0: Reserved (must be cleared
to 0)
Bit 7 Thru 1 : Reserved (must be cleared to 0)
Bit 5 : Descrambler
The TS7524 incorporates an auto-synchronized
3.3. TRANSMIT AND RECEIVE STATUS WORD
The status words are issued by the TS75240 and provide the status reporting to the control processor.
3.3.1. TRANSMIT STATUS WORD
Table 8 : Transmit Status Word Format.
BIT
First Byte
0
Transmit (0)
-
-
-
Second Byte
Third Byte
Reserved
Reserved
1
2
3
4
Reserved
5
6
7
17/36
117
TS7524
FIRST BYTE:
SECOND BYTE:
Bit 0 : Transmit
Bit 7 Thru 0 : Reserved
This bit when low informs the control processor that
the status word issued by the TS7524 is a transmit
status word.
THIRD BYTE:
Bit 7 Thru 0 : Reserved
Bit 7 Thru 1 : Reserved
3.3.2. RECEIVE STATUS WORD
Table 9 : Receive Status Word Format.
BIT
First Byte
0
Receive (1)
1
DO
Data Before
2
3
D1
Descrambling
4
D3
D2
Second Byte
Third Byte
Reserved
Reserved
-
(QAM. , D.P.S.K.)
DO
Data
D1
After
D2
Descr.
Equalization Status
D3
Reserved
Signal Quality
1
6
S1 Sequence
Carrier Detect
1
7
S 1 Seguence 0 r
Call Progress Tone Detection
Reserved
5
(QAM.,
D.P.SK)
DO
t-D1
r-D2
r-D3
r-D4
r-D5
Data
(F.S.K.)
Answer Tone Detection
Note: In QAM and DPSK modes, both for the data after and before descrambling, the unused bits are set to "1" by the TS7524.
FIRST BYTE:
Bit 0 : Receive
This bit set to one by the TS7524 indicates to the
control processor that the current status word is a
receive status word.
Bit 4, 3, 2, and 1 : Data before descrambling
Used only in QAM and DPSK modes, these four bits
represent the data received before descrambling,
i.e., after the demodulator and before the descrambier. Data is coded on four bits (03, 02, 01, DO) in
V.22 bis, on two bits (01, DO) in V.22 .at 1200 bps
and BELL 212, on only one bit (DO) in V.22 at 600
bps. The unused bits are set to 1 by the TS7524.
tion) of values "10" and "01" on bit 7 and 6, the "S1"
sequence is present in reception. Else, this means
its absence.
Bit 7 : Call progress tone detection (call progress/answer tone mode).
This bit low indicates detection of energy in the band 300 - 700 Hz with a detection threshold of - 43 dBm. This bit high means there is no
energy detected. (see paragraph call progress and
answer tone detection).
SECOND BYTE
Bit 3, 2, 1, and 0: Reserved
Bit 4 : Equalization status
The mailbox exchange rate between the TS75240
and the control processor is done at 600 exchanges
per second. Both for QAM and DPSK modes, DO
(which correspond to the bit 1) is the first bit received.
This bit will go high (1) in case of equalization loss
(retrain sequence initialization or fallback mode).
Bit 5 : Reserved
This bit will go high (1) when the quality of the received signal is too low for a good transmission.
Bit 7 and 6 : S1 handshake sequence (V.22 bis)
mode
During the V.22 bis handshake sequence, these two
bits indicate the presence orthe absence of the "S1"
sequence detected by the TS7524. If the TS7524
gives an alternance (at each baud period in recep-
18/36
118
Bit 5 : Signal quality
Bit 6 : Carrier detect
This bit indicates the presence orthe absence of the
on-line signal as follows:
_ This bit will go low (0) if the signal level is higher than - 43 dBm on PSTN or - 33 dBm on
TS7524
i
leased lines
_ This bit will go high (1) if the signal level is lower than - 48 dBm on PSTN or - 38 dBm on
leased lines
bling.
The data is encoded on four bits (03, D2, 01 ,
~O) in V.22Bis, on two bits (01, ~O), in V.22
at 1200 bps and Bell 212, on only one bit (~O)
in V.22 at 600 bps. The unused bits are set to
one by the TS7524.
The mailbox exchange rate between the
TS75240 and the control processor is done at
600 exchanges per second. For both GAM
and OPSK modes, DO (which correspond to
bit 1) is the fi rst bit received.
_ In FSK modes (V.21 , V.23, and BELL 103) all
the six bits are used to represent the digital
value of six samples of the received signal. In
these modes, the mailbox exchange must be
executed at the rate of 1200 exchanges per
second. Consequently to perform a parallel to
serial conversion the control processor has to
resend these bits on the 104 circuit of the
V.24/RS232 junction at 7.2 kHz.
Bit 1 (which correspond to ~O) is the first sample of the incoming signal received over the
line as shown in figure 8.
The minimum hysteresis level is 2 dB.
The information on the on-line signal may be used
by the control processor to manage the 109 signal
of the V.24 junction.
Bit 7: Reserved
THIRD BYTE:
Bit 0 : Reserved
Bit 6 Thru 1 : Data received or data after descrambling.
These six bits contain the received data and have
to be processed by the control processor according
to the selected standards:
_ In GAM and OPSK modes, bit 4 thru 1 represent the data received after descrambling, if
the descrambler is enabled. Otherwise, they
represent the data received without descram-
Figure 8 : FSK Receive Mode.
RECEIVED
TO
~
(1/1200)8
SIGNAL ON THE
104 CIRCUIT
TO
((
JJ
((
((
T1) ~ (1/7200)8 ~11
'I'
1
0---,1_0~1-----,0105-
DO ,-,--'-,-----'-1_0" - I
))
LOADED IN THE MAILBOX
BY THE TS75240
M88TS7524-08
Bit 7 : Answer tone detection
Used in answer tone detection mode, this bit when
low (0), indicates the presence of the answer tone
(CCITT 2100 Hz, BELL 2225 Hz or Transpac 1650
Hz) sent by the far-end modem. When high (1), it
means no detection of answer tone. Refer to paragraph "call progress and answer tone detection" for
further details.
19/36
119
TS7524
CALL PROGRESS AND ANSWER TONE DETECTION
_ 1650 Hz : Transpac V.21 answer tone
The TS7524 call progress detection part is activated by detection of energy in the 300 to 700 Hz call
progress tone bandwidth. The call progress mode
must be selected in the first byte (bit 3 thru 0) of the
receive command word.
The answer tone mode must be selected in the first
byte (bit 3 thru 0) of the receive command word and
the answer tone selection (1650 Hz or 2100/2225
Hz) with the bit 4.
Then the bit 7 of the first byte of the receive status
word indicates to the control processor that the call
progress tone is detected (bit 7 = 0) or not (Bit 7 = 1).
Then bit 7 in the third byte of the receive status word
indicates to the control processor that the answer
tone is detected (bit 7 = 0) or not (bit 7 = 1).
In answer tone mode, the TS7524 may recognize
three different standard frequencies which represent the usual answer tones sent by the far-end modem as described hereunder:
_ 2100 Hz : CCITT modes answer tone V.21
and V.23
_ 2225 Hz : BELL answer tones
The table 10 shows the programmation of the re-
ceive command word, and the status reporting
contained in the receive status word.
DTMF mode and transmit enable = 1 must be selected in the transmit command word.
Table 10 : Call Progress and Answer Tone Detection Programming Model.
Receive Command Word
First Byte
Bit 3, 2, 1 , 0,
Call Progress
Mode and
2100/2225
0111
Bit 4
0
Receive Status Word
First Byte
Bit 7
1
0
0111
1
1
0
Third Byte
Bit 7
No Call Progress Tone Detected
Presence of Call Progress Tone
I
Answer Tone
Call Progress
Mode and
1650 Hz
Answer Tone
1
0
1
2100/2225 Hz Detected
No Detection
No Call Progress Tone Detected
Presence of Call Progress Tone
I
0
1
1650 HZ Detected
No Detection
4. ELECTRICAL SPECIFICATIONS
4.1. MAXIMUM RATINGS
T575240
Value
Unit
Supply Voltage
- 0.3 to 7.0
V
Input Voltage
- 0.3 to 7.0
V
o to 70
°C
- 55 to 150
°C
Symbol
Vcc *
Vin
*
Parameter
TA
Operating Temperature Range
T stg
Storage Temperature Range
• With respect to vss.
Stresses above those hereby listed may cause permanent damage to the device. The ratings are stress ones only and functional operation of the device at these or any conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Standard MOS circuits handling procedure should
be used to avoid possible damage to the device.
20/36
120
TS7524
TS68950/1/2
Symbol
Value
Unit
Supply Voltage between V+ and AGND or DGND
Parameter
- 0.3 to + 7
V
Supply Voltage between V+ and AGND or DGND
- 7 to + 0.3
V
- 0.3 to + 0.3
V
Digital Input Voltage
DGND - 0.3 to Vee+ + 0.3
V
Digital Output Voltage
DGND - 0.3 to Vee+ + 0.3
V
Digital Output Current
- 20 to + 20
mA
V
Voltage between AGND and DGND
Analog Input Voltage
Vee- - 0.3 to Vee+ + 0.3
Analog Output Voltage
Vee- - 0.3 to Vee+ + 0.3
V
Analog Output Current
- 10 to + 10
mA
Power Dissipation
Toper
T stg
Storage Temperature
4.2. DC ELECTRICAL CHARACTERISTICS
Digital Supply
Vee
500
mW
o to + 70
°C
- 65 to + 150
°C
Operating Temperature Range
= 5.0V ± 5%,
Vss
= 0,
TA
= 0 to
Symbol
DGND = AGND = 0 V
+ 70°C (unless otherwise specified)
Min.
Typ.
Max.
Unit
Vee
Supply Voltage
Parameter
4.75
5
5.25
V
V,L
Input Low Voltage
- 0.3
0.8
V
V,H
Input High Voltage. All inputs except RESET
24
Vee
V
2.8
Vee
V
Ii
Input Extal Current
- 50
+ 50
!lA
lin
!!t.2ut Lea~e Current BSO, BS1, BS2, BE3, BE4,
RS, SDS, CS,SRW, RESET
-10
+ 10
!lA
V,H
RESET Input High Voltage
VOH
Output High Voltage (l'oad = - 300!lA). All Outputs Exeept DTACK
VOL
Output Low voltage (l'oad = 3.2mA). All Outputs
Cin
Input Capacitance
ITs l
Three State (off state) Input Current @ 2AVIOAV
DTACK, BA, DO-D15, ADO-AD7
- 20
TA
Operating Free-air Temperature (notes 1 and 2)
0
lee
Supply Current TS75240 T A = 25°C
2.7
V
0.5
10
+ 20
T e = 100°C
lec
V
pF
!lA
70
°C
480
mA
420
mA
Noles: 1. Case temperature Tc must be maintained below 100'C.
2. RaJA 39'C/walts Side-brazed ceramic DIL·48.
28'C/watts PDIL-48 heath spreader.
Analog Supply
Symbol
V+
Max.
Unit
Positive Power Supply
Parameter
Min.
4.75
5.25
V
V-
Negative Power Supply
- 5.25
- 4.75
V
1+
Positive Supply Current
35
mA
1-
Negative Supply Current
- 35
Typ.
mA
21/36
121
TS7524
4.3. AC ELECTRICAL SPECIFICATIONS
4.3.1. CLOCK AND CONTROL PINS TIMING (Vcc = 5.0 V ± 5 %, TA = 0 °C to + 70 °C, see figure 9)
OUTPUT LOAD = 50 pF + DC characteristics I load
Reference Levels: VIL : 0 V VIH : 2.4 V
VOL: 1.5 V V OH : 1.5 V
Symbol
tr, tf
:0;
5 ns for Input Signals
Parameter
tcex
External Clock Cycle Time
Ifex
External Clock Fall Time
t rex
External Clock Rise Time
teoh
EXTAL to CLKOUT High Delay
teol
EXTAL to CLKOUT Low Delay
teor
CLKOUT Rise Time
teof
CLKOUT Fall Time
tdle
CLKOUT to Control Output Low (IRQ, BA)
tdhe
CLKOUT to Control Output High (IRQ, BA)
tdsl
CLKOUT to DS, RD, WR Low
tdsh
CLKOUT to DS, RP, WR High
tse
Control Inputs Set-up Time (BSO ... BE6, RESET)
the
Control Inputs Hold Time (BSO ... BE6, RESET)
Min.
Typ.
Max.
5
5
25
25
5
5
20
10
---
DS,RD,WR-----i---------------,
the
BS/BE
RESET
M88TS7524-09
22/36
122
ns
ns
ns
ns
ns
ns
CLKOUT
Notes: 1. tc ~ Instruction cycle time = 4 x tcex.
2. BE3 ........ BE6 min low level duration = tc.
ns
ns
EXTAL
tse
ns
ns
10
10
50
50
lGeX
---
ns
ns
Figure 9 : Clock and Control Pins Timing.
---
Unit
ns
43.4
TS7524
A.C. TESTING LOAD CIRCUIT
A.C. TESTING INPUT, OUTPUT WAVEFORM
INPUT-OUTPUT
2.4V=X
1.5V -
1<=
DEVICE
UNDER
TEST POINTS ~ 1.5V
TEST
1
',c',»
OV
--
AC TESTING INPUTS ARE DRIVEN AT 2,4V FOR A LOGIC 1
AND OV FOR A LOGIC 0 TIMING MEASUREMENTS ARE
MADE AT 1.5V FOR BOTH A LOGIC 1 AND O.
tr, If ,; 5ns for input signals
CL INCLUDES JIG CAPACITANCE
INTERNAL CLOCK OPTION
Then the 5.76 MHz required by the Analog Front
End can be easily obtained.
A crystal oscillator can be connected across XTAL
and EXTAL. The frequency of CLKOUT is half the
crystal fundamental frequency, and can be used by
the control processor.
, - - - - - - - - - - - - - 11.520 MHz
C
r------r---l ~
C typical value
~
10 pF
M88TS7524-10
Crystal nominal parameters:
Parallel resonance fundamental mode - AT CUT
Rs
= 10 Q
C1 = 0.018 pF
Co = 3.5 pF
Q>30K
Co
M88TS7524-11
23/36
123
TS7524
4.3.2. TS68952 : CLOCK GENERATOR
Crystal Oscillator Interface
Symbol
Parameter
Test Conditions
V,L
Input Low Level Voltage
V,H
Input High Voltage
I'L
Input Low Level Current
DGND os; V,
OS;
V,Lmax
I'H
Input High Level Current
V,H min
OS;
V+
OS;
V,
Min.
Typ.
Max.
Unit
1.5
V
3.5
V
-15
~
15
~
Max.
Unit
CLOCK WAVE FORMS
Symbol
PC
Parameter
Test Conditions
Min.
Typ.
Main Clock Period
XTALI Input
tWCL
Main Clock Low Level Width
XTALI Input
50
tWCH
Main Clock High Level Width
XTALI Input
50
tRC
Main Clock Rise Time
XTALI Input
50
ns
tFC
Main Clock Fall Time
XTALI Input
50
ns
toe
Clock Output Delay Time
All Clock Outputs CL = 50 pF
500
ns
Ire
Clock Output Transition Time
All Clock Outputs CL = 50 pF
100
ns
173.6
ns
ns
ns
Unless otherwise noted. electrical characteristics are specified over the operating range. TYPical values are given for V' = 5.0 V and
T,mb = 25 'C.
Figure 10 : Clock Generator.
pc
'WCH
,
1/ 35 V
INPUT
XTAL 1
1.5 V
J
I
-
'RC- f-
'WCL
~
tFC
1/
/
..J
I\.
tDC
,
CLOCK OUTPUTS
(9 CLOCKSI
..
J
If 2.2 V
X
I\. 0.8 V
-
I--
'TC
M88TS7524-12
24/36
124
TS7524
4.3.3. LOCAL BU8 TIMING (T875240 and T868950/51 152)
(V cc = 5.0 V ± 5 %, T A = 0° to + 70°C, see figure 11)
Symbol
Parameter
Min.
Max.
Unit
1/2 tc - 15
1/2 tc
ns
tpw
RD, WR, DS Pulse Width
tAH
Address Hold Time
10
ns
tosw
Data Set-up Time, Write Cycle
25
ns
tOHW
Data Hold Time, Write Cycle
10
ns
tOSR
Data Set-up Time, Read Cycle
20
ns
tOHR
Data Hold Time, Read Cycle
5
ns
tARW
Address Valid to WR, DS, RD Low
tozw
DS High to Data High Impedance, Write Cycle
1/2 tc - 40
ns
40
ns
Figure 11 : Local Bus Timing Diagram.
ADDRESSES
14'
»»») )<
tpw
RD,wR,DS
\
/
tAH
tpw
R/W
\
tdzw
tARW
00-015
DATA OUT
tosw
IIII
\\\\
DATA OUT
tOSR
00-D15
DATA IN
DATA IN
tDHW
m7
tDHR
1>--M88TS7524·13
25/36
125
TS7524
4.3.4. SYSTEM BUS TIMING (TS75240 and control processor)
Vcc = 5.0 V ± 5 %, T A = 00 to + 70 'C
Symbol
Parameter
tspw
SDS Pulse Width
tSAW
SR/W, CS, RS Set-up Time
tSAH
SR/W, CS, RS Hold after SDS High
tSOSR
Data Set-up Time, Read Cycle
tSOHR
Data Hold Time, Read Cycle
Min.
Unit
ns
ns
ns
ns
ns
35
tpsosw
Data Propagation Delay, Write Cycle
tSOHW
Data Hold Time, Write Cycle
tsozw
SDS High to Data High Impedance, Write Cycle
tOSLOT
SDS Low to DTACK Low
tOSHOT
SDS High to DTACK High·
• DTACK is an open drain output test load include Rl
Max.
60
20
5
20
5
ns
10
=
ns
40
50
50
ns
ns
ns
820 Q at Vee.
Figure 12 : System Bus Timing Diagram.
SOS
\
II
~
'SAW
SRiw.cs
RS
~
K
'SDSR
ADO-AD?
DATA IN
/
'SDHR
DATA IN
I~
"
'SDZW
~
'PSOSW
ADO-AD?
DATA OUT
~«<
'DSLOT
DTACK
DATA OUT
k>
>
"',~
'OSHDT
\
Ir--
/
M88TS7524-14
26/36
126
TS7524
4.3.5. OM INTERFACE (OAA and T868950 and T868951)
Analog Transmit Output (ATO)
V+ = 5 V ± 5 %,0 'C :s; Tamb :s; + 70 'C V(unless otherwise specified)
Symbol
=-
5V
± 5 %,0 'C :s; Tamb :s; + 70 'C
Parameter
Vos
Output OC Offset
CL
load Capacitance
RL
load Resistance
Min.
Typ.
- 2S0
Max.
Unit
+ 2S0
mV
SO
pF
kQ
1.2
V out
Output Voltage Swing
(RL > 1.2 kQ C L < SO pF)
Rout
Output Resistance
(read cycle)
- 2.5
+ 2.S
V
S
Q
Receive Analog Input (RAI).
Symbol
Max.
Unit
Vin
Input Voltage
Parameter
- 2.S
Min.
+ 2.S
V
lin
Input Current
(write cycle)
-1
+ 1
J.1A
Typ.
5. PIN CONNECTIONS
TS75240
04
05
06
07
DB
09
010
011
012
013
014
010;
VSS
XTAL
EXTAL.
CL.KOUT
~
R/W
S.R/W
SOs
cs
fiS
AEsE'f
iRa"
•,
,•
,.
I
TS68950
"..
...
'"
'2
..
]I
]I
"'2
31
13
]I
'I
)<
.
'.
",t
,"
X>
Xl
»
20
3'
30
2t
2'
22
2t
21
23
26
"
"
02
01
DO
BE3
BE4
BSO
BSl
BS2
All
vec
Ala
A9
AB
A07
A06
AD5
AD4
AD3
A02
ADl
ADO
BE5
BE6
M88TS7524·15
05
04
06
03
07
02
E
01
RNi
DO
Gsa
TxGGlK
GS1
GlK
RSO
v+
RS1
EEO
OGNO
ATO
TEST
EXI
V-
AGNO
M88TS7524·16
27/36
127
TS7524
PIN CONNECTIONS (continued)
TS68952
TS68951
D5
D4
D5
04
D6
D3
06
D3
D7
D2
07
02
D1
E
DD
R/Vi
TxCCLK
E
R/W
01
eso
TxCClK
esa
TxCLK
eS1
RxCCLK
eS1
AxCLK
RSO
eLK
Rsa
RxCCLK
RSl
v+
RS1
RxRCLK
TO
RxMCLK
TxSCLK
TxMCLK
OGNU
AGe2
CDl
RfO
V -
LEI
DGND
RAI
XTALl
TxRCLK
AGND
XTAL2
eLK
M88TS7524-17
V
M88TS7524-18
TS75240
MAFE Interface
Name
Pin
Function
DO thru 015
I/O
Local Data Bus
A8 thru A11
0
Local Address Bus
OS
0
Data Strobe
R/W
0
Read/Write
Description
Only 08 thru 015 lines are used for data transfer between the
TS75240 and MAFE Kit.
DO thru 07 are not used and are left unconnected.
Address Lines to the MAFE Kit.
This signal synchronizes the transfer between the TS75240 and
the MAFE Kit.
Indicates the current bus cycle state.
CLKOUT
0
Clock Output
This signal generated by the TS75240 is at half the frequency of
the crystal. It can be divided by 2 to provide the 5.76 MHz clock
for the MAFE Kit.
BE3 thru BE6
I
Receive and
Transmit Clocks
These four inputs are connected to the receive and transmit
clocks generated by the clock generator circuit (TS68952) of the
MAFE Kit.
28/36
128
TS7524
TS75240
System Interface.
Name
Pin
Function
ADO thru AD7
I/O
System Data Bus
CS
I
Chip Select
RS
I
Register Select
-
Description
• These bi·directional lines are used for data transfer between the
TS75240 mailbox and a system processor.
This active low input is asserted when the TS75240 is to be
accessed by the system processor.
This signal is used with CS to control the data transfer between
the system processor and the TS75240 mailbox.
SDS
I
System Data Strobe
Synchronizes the transfer on the system bus.
SR/W
I
System Read/Write
Indicates the current system bus cycle state.
IRQ
0
Interrupt Request
Handshake signal sent to the master to gain access to the
mailbox.
Others Pins.
Name
Pin
Function
BSO thru BS2
I
Branch on State
Description
EXTAL
I
Clock
Crystal Input for Internal Oscillator or Input Pin for External
Oscillator.
XTAL
I
Clock
Together with EXTAL this pin is used for the external 23.040 MHz
crystal.
Vcc
Supply
Power Supply
Vss
Supply
Ground
RESET
I
Reset
These three inputs are not used and must be grounded.
29/36
129
TS7524
TS68950
N°
Description
05-07
1-3
8 bit data bus inputs giving access to Tx estimated echo, control and address registers.
(same for pins 20-24).
E
4
Enable Input. Oata are strobed on the positive transitions of this input.
5
Read/Write Selection. Internal registers can be written when R/W = O. Read mode is not
used.
Name
-
R/W
CSO-CS1
6-7
Chip Select Inputs. The chip set is selected when CSO = 0 and CS1 = 1.
RSO-RS1
8-9
Register Select Inputs. Used to select O/A input registers or control/address registers in
the write mode.
OGNO
10
Oigital Ground = 0 V. All digital signals are referenced to this pin.
TEST
11
Test Input. Used for test purposes.
This pin must be grounded in all applications
V-
12
Negative Supply Voltage = - 5 V ± 5 %
AGNO
13
Analog Ground = 0 V.
EXI
14
Programmable analog input tied to filter or attenuator input according to the RC4
register content.
ATO
15
Analog Transmit Output.
EEO
16
Analog Echo Cancelling Output.
V+
17
Positive Power Supply Voltage = + 5 V ±5 %
ClK
18
Master Clock Input. Nominal Frequency 1.44 MHz
TxCClK
19
Transmit Conversion Clock Input.
00-04
20-24
30/36
130
See description of 05-07 (pins1-3) given above.
TS7524
TS68951
Name
N°
D5-D7
1-3
-
E
-
R/W
Description
Data Bus.
4
Enable Input. Enables Selection Inputs.
Active on a low level for read operation.
Active on a positive level for write operation.
5
ReadIWrite Selection Input. Read operation is selected on a high level.
Write operation is selected on a low level.
~
0 and CS1
~
CSO-CS1
6-7
Chip Select Inputs. The chip set is selected when CSO
RSO-RS1
8-9
Register Select Inputs. Select the register involved in a read or write operation.
1.
DGND
10
Digital Ground. All digital signals are referenced to this pin.
EEl
11
Estimated Echo Input. When operating in echo cancelling mode, this signal is added to
the reception band-pass filter output.
AGC1
12
Analog Input of the Automatic Gain Control Amplifier and of the Carrier level Dectector.
RFO
13
Reception Filter Analog Output. Designed to be connected to AGC1 input through
a 1 ~F non polarized capacitor.
V-
14
Negative Supply Voltage
AGND
15
Analog Ground. All analog signals are referenced to this pin.
RAI
16
Receive Analog Input. Analog input tied to the transmission line.
lEI
17
local Echo Input. Analog input subtracted from the receive anti-aliasing filter output.
CD1
18
This pin must be connected to the analog ground trough a 1 ~F non polarized
capacitor, in order to cancel the offset voltage of the carrier level detector amplifier.
AGC2
19
This pin must be connected to the analog ground trough a 1 ~F non polarized
capacitor, in order to cancel the offset voltage of the offset AGC amplifier.
~
- 5 V±5%
V·
20
Positive Supply Voltage
ClK
21
Master Clock Input. Nominal Frequency 1.44 MHz.
~
+5 V±5%
RxCClK
22
Receive Conversion Clock.
TxCClK
23
Transmit Conversion Clock.
DO-D4
24-28
Data Bus.
31/36
131
TS7524
TS68952
Name
ND
D5-D7
1-3
Description
Data Bus Inputs to Internal Registers
4
Enable Input. Data are strobed on the positive transitions of this input.
RIW
5
Read/Write Selection Input. Internal registers can be written when R/W
is only used for Rx front-end-chip.
CSO-CS1
6-7
Chip Select Inputs. The chip set is selected when CSO
RSO-RS1
8-9
Register Select Inputs. Used to select address or control registers
TO
10
Test Output. Must be left open in all applications.
TxSCLK
11
Transmit Synchronizing Clock Input. Normally tied to an external clock terminal. When
this pin is tied to a permanent logical level, transmit DPLL free-runs or can be
synchronized to the receive clock system.
E
-
= O. Read mode
= 0 and CS1 = 1.
= 0 Y. All digital signals are referenced to this pin.
DGND
12
Digital Ground
XTAL1
13
Crystal Oscillator or Pulse Generator Input.
XTAL2
14
Crystal Oscillator Output.
CLK
15
1.44 MHz Clock Output. Useful for TS68950/51.
TxRCLK
16
Transmit Baud Rate Clock Output
Y+
17
Positive Supply Yoltage
TxMCLK
18
Transmit Multiplexing Clock Output
=+ 5 Y ± 5 %
RxMCLK
19
Receive Multiplexing Clock Output
RxRCLK
20
Receive Baud Rate Clock Output
RxCCLK
21
Receive Conversion Clock Output
RxCLK
22
Receive Bit Rate Clock Output
TxCLK
23
Transmit Bit Rate Clock Output
TxCCLK
24
Transmit Conversion Clock Output
D1-D4
25-28
Data Bus Inputs to Internal Registers (DO is not used)
6.0RDERING INFORMATION
The TS7524 corresponds to four different components which must be ordered separately.
available for a fast characterization improvement of
the TS7524 in a real application.
Furthermore, a stand-alone evaluation board is
Part Number
TS75240CP/XX
TS68950CP
TS68951CP
TS68952CP
TS7524EYA'
Temp Range
Package
o DC to 70 DC
o DC to 70°C
o °C to 70°C
o °C to 70 DC
DIP-48
DIP-24
DIP-28
DIP-28
N. A
• Contact your SGS-THOMSON representative.
32/36
132
Device
Y. 22Bis Masked DSP
Transmit Analog Interface
Receive Analog Interface
Clock Generator Interface
Stand Alone Evaluation Board
TS7524
7. PACKAGE MECHANICAL DATA
TS75240
48 Pins - Plastic Dip.
25
48
Datum
i/
.------!--._._.
(11 Nominal dimension
(2l True geometrical position
/1
24
63.5ma •.
14
48
Pins
TS68950
24 Pins - Plastic Dip.
e = 2.54
4.57max.
I.
16.1 max.
..I
0.51 min.
r---~r---~~
0.38
0.508
3.1
3.9
15.24
13
24
Datum
(1)
(2)
Nominal dimension
True geometrical position
12
32.6mox.
14
24
PINS
33/36
133
TS7524
TS68951/TS68952
28 Pins - Plastic Dip.
4.57max.
(21
15
18
Datum
(1) Nominal dimension
(2) True geometrical position
Or
3B.lmox.
14
III
ELECTRICAL CONSIDERATIONS
To avoid possible high frequency problems, the following precautions should be considered for PC
board layout design:
• A ground plane on the component side connected to analog ground of the TS68950/51
• Analog and Digital ground tracks corresponding
to different signals, e.g. clocks, input signals, references, ... shou Id be adequately separated and
terminated at a single point.
34/36
134
28
Pins
• Optimal distribution of power supplies and
ground links using star-connection.
• Adequate decoupling capacitor mounted as
close as possible to each device, and connected
to analog ground.
• DSP and MAFE power supplies should be separated.
TS7524
APPENDIX A
TRANSMIT/RECEIVE COMMAND WORDS
Transmit Command Word.
BIT
0
First Byte
Second Byte
Third Byte
Transmit Mode Selection
Transmit (0)
t---
0000 : Modem Disabled
0001 : V.22 Bis
0010: V.22 0011 : B212
2
0100 : V.23 0101 : V.21
t--0110 : Bell 103
3
0111 : D.T.M.F.
1
DO
t---
Transmit Signalling
4
I - - 00 : Signalling Disabled
01 :550 Hz
5
11 : 1800 Hz
Transmit
Attenuation
t--D1
D
P
S
K
Q
A
M
D
T
M
F
D2
0
D3
0
Scrambler (ON/OFF)
D4
0
0
t---0
D5
0
0
0
-
--
6
Reserved
Reserved
7
ANSW/ORIG or DTMF
V.22 Binary Rate Select
or DTMF
I------
Transmit Enable
Note: All the "RESERVED" bits must be cleared to "0" by the user.
Receive Command Word.
BIT
0
-
1
2
-
3
4
First Byte
Second Byte
Receive. Mode Selection
0000 : Modem Disabled
0001 : V.22 Bis
0010: V.22 0011 : B212
0100 : V.23 0101 : V.21
011 0 : Bell 103
0111 : Call Prog / Answer Tone
Third Byte
Receive (1)
Reserved
Reserved
Answer Tone Selection
5
Tx Synchronization
6
Carrier Detect Level
Reserved
7
Answer/originate
V.22 Binary Rate Select
Descrambler (ON/OFF)
Nole : All the "RESERVED" bits must be cleared to "0" by the user.
35/36
135
TS7524
APPENDIX B
TRANSMIT/RECEIVE STATUS WORDS
Transmit Status Word.
BIT
First Byte
0
Transmit (0)
Second Byte
Third Byte
Reserved
Reserved
Second Byte
Third Byte
1
r-2
r-3
Reserved
f---
4
f---
5
f---
6
f---
7
Receive Status Word.
BIT
First Byte
0
Receive (1)
1
DO
Data Before
2
D1
Descrambling
3
D2
4
D3
Reserved
Reserved
(QAM. , D.P.SK)
DO
r-D1
r-D2
Equalization Status
D3
5
Reserved
Signal Quality
1
6
7
S1 Sequence
Carrier Detection
1
S1 Seguence or
Call Progress Tone Detection
Reserved
Data
After
Descr.
(QAM.,
D.P.S.K.)
DO
r-D1
r-D2
r-D3
r--
Data
(F. S. K.)
D4
f---
D5
Answer Tone Detection
Note: In QAM and DP8K modes, both for the data after and before descrambling, the unused bits are set to "1" by the T87524.
36/36
136
T57532
v. 32 MODEM CHIP SET
ADVANCE DATA
• CCITT V.32 COMPATIBLE MODEM CHIP
SET [see ref 1 of Appendix OJ
• INTEGRATED IMPLEMENTATION ON THREE
DSP AND THREE MAFE CHIPS
• FULL DUPLEX OPERATION AT 9600 AND
4800 BPS
• FULL IMPLEMENTATION OF THE V.32 HANDSHAKE
• DYNAMIC RANGE: 43 dB
• TWO SATELLITE HOPS AND FREQUENCY
OFFSET CAPABILITIES (10 Hz) FOR THE FAR
END ECHO CANCELLER
• TRELLIS ENCODING AND VITERBI DECODING
• 12.5 % ROLL-OFF RAISED COSINE TRANSMITTER PULSE SHAPING
• HIGH PERFORMANCE PASSBAND FRACTIONALLY SPACED ADAPTIVE EQUALIZER
• SIGNAL QUALITY MONITORING
• PARALLEL INTERFACE TO STANDARD
MICROPROCESSORS
• BIT RATE DATA CLOCKS PROVIDED FOR
SYNCHRONOUS DATA TRANSFER
• FULL DIAGNOSTIC CAPABILITY
• DTMF GENERATION
• CALL PROGRESS TONE DETECTION
• FUTURE UPGRADE TO INCLUDE V.22 BIS,
V.22, B212AAND FSK (TOTALLY PIN-COMPATIBLE)
• SOFTWARE LICENSE AND DEVELOPMENT
TOOLS AVAILABLE FOR EASY CUSTOMIZATION
P
DIP48
(Plastic Package)
TS75320/1/2
P
DIP24
(Plastic Package)
TS68950
DESCRIPTION
The SGS-THOMSON Microelectronics V.32 chip
set is a highly integrated modem engine, which can
operate in full duplex at 9600 and 4800 bps. The
modem hardware consists of three analog front end
(MAFE) chips, three DSP processor chips and additional memory chips.
The three SGS-THOMSON analog front end chips
(TS68950/1/2) are the transmit interface, the receive
interface and the clock generator respectively.
The modem signal processing functions are implemented on three TS68930 programmable digital signal processors. TS75320 supports the echo canceller, TS75321 the transmitter, handshake and
user's interface and TS75322 the receiver.
P
DIP28
(Plastic Package)
TS68951 12
(Ordering information at the end of the datasheet)
December 1988
1/44
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice
137
TS7532
TABLE OF CONTENTS
1.
PIN DESCRIPTION
1 .1. System Interface
1.2. Analog Interface
1.3. Clock Interface
3
3
3
3
2.
FUNCTIONAL DESCRIPTION
2.1. System Architecture
2.2. Processor and MAFE Chips Arrangement
2.3. Operation
2.4. Modem Interface
4
4
4
5
8
3.
USER INTERFACE - COMMAND SET
3.1. Command Summary
3.2. Status Reporting
3.3. Command List
9
10
11
12
4.
ELECTRICAL SPECIFICATION
4.1. Maximum Ratings
4.2. DC Electrical Characteristics
4.3. AC Electrical Characteristics
14
14
15
16
5.
PIN CONNECTIONS
20
6.
ORDERING INFORMATION
21
7.
PACKAGE MECHANICAL DATA
21
A.
COMMAND SET DESCRIPTION
23
B.
STATUS REPORTING DESCRIPTION
36
C.
INTERCONNECTION
37
D.
REFERENCES
42
TABLE OF APPENDICES
2/44
138
TS7532
1. PIN DESCRIPTION
1.1. SYSTEM INTERFACE
TS75321 (DSP#1 Transmitter and Handshake)
Pin
Name
Pin
N°
Type
Signal
Name
ADO.AD7
27.34
1/0
DOH.D7H
CS
21
I
CSL
Chip Select: this input is asserted when the TS7532 is to be
accessed by the host processor.
RS
22
I
RSL
Register Select: this signal is used to control the data transfers
between the host processor and the TS7532 mailbox.
SDS
20
I
DSL
System Data Strobe: synchronizes the transfer between the
TS7532 mailbox and the host processor.
SR/W
19
I
RWL
System ReadIWrite : control signal for the TS7532 mailbox
operation.
IRQ
24
0
INTL
Interrupt Request: signal sent to the host processor to accElss the
TS7532 mailbox.
RESET
23
I
RSTL1
Description
System Data Bus: these lines are used for data transfer between
the TS7532 mailbox and the host processor.
Master Reset of DSP#1
1.2. ANALOG INTERFACE
TS68950 (Analog Front End Transmitter)
Pin
Name
Pin
N°
Type
Signal
Name
ATO
15
ATO
ATO
Description
Analog Transmit Output
TS68951 (Analog Front End Receiver)
Pin
Name
Pin
N°
Type
Signal
Name
RAI
LEI
16
I
RAI
Receive Analog Input
17
I
LEI
Local Echo Input. This signal is subtracted from signal RAI.
Description
1.3. CLOCK INTERFACE
TS68952 (Clock Generator)
Pin
Name
Pin
N°
TxCLK
23
TxRCLK
16
TxCCLK
24
TxMCLK
18
RxCLK
22
RxRCLK
20
RxCCLK
21
RxMCLK
19
0
0
0
0
0
0
0
0
TxSCLK
11
I
Type
Signal
Name
TxCLK
Description
Transmit Bit Clock
TxRCLK
Transmit Baud Clock
TxCCLK
Transmit Conversion Clock
TxMCLK
Transmit Multiplex Clock
RxCLK
Receive Bit Clock
RxRCLK
Receive Baud Clock
RxCCLK
Receive Conversion Clock
RxMCLK
Receive Multiplex Clock
TxSCLK
Transmit Synchro Clock: can be used to synchronize the transmitter on an external bit clock provided by the RS232C (or V.24)
junction.
3/44
139
TS7532
2. FUNCTIONAL DESCRIPTION
2.1. SYSTEM ARCHITECTURE
The SGS-THOMSON V.32 chip set is a highly integrated modem engine which provides the functionality and performance requirements for full-duplex
9600 bps modem solutions at a low cost and with a
small circuit area. At the heart of the modem engine
are three SGS-THOMSON DSPs which implement
the complete signal processing and control functions.
The analog front end of the modem engine consists
of the SGS-THOMSON MAFE three-chip set which
is designed to meet the requirements of high-speed
modem applications and particularly V.32 modems.
The only other components in the modem engine are
the external RAM chips used for the far-end echo
canceller delay line and the Viterbi decoder.
2.2 PROCESSOR AND MAFE CHIPS ARRANGEMENT
Figure 1 shows the interconnections between the
MAFE and signal processors.
Figure 1 : Hardware Architecture.
,-------------------------------------------------------------,
DOH-Drn
o\OO--ADT
To
Control
Processor
,
______________________________________________________ -
4/44
140
______ 1
TS7532
i
~
DSP 1 communicates with the control processor
through its system bus, ADO-AD7. It is also connected to the two other DSPs through its DO-D7 and D8D15 data buses to transfer data, to pass a control
command to the DSPs and to get the modem operation status and then pass it to the control processor. The transmitter, V.32 handshake and part of the
receiver algorithms are implemented in this processor. DSP 0 implements the echo cancellation function. 4Kx16 of RAM are connected to this processor
to implement the data delay line for the far end echo
cancellation. DSP 2 implements most of the receiver functions. 2Kx16 of RAM are attached to it due
to the requirements of the Viterbi decoder.
The transmitter interface chip, TS68950 [see ref 5
of Appendix Dj, is connected to the 8 MSB's of the
DSP 1 data bus. The echo replica is sent from DSP 1
to TS68950 then to the receiver interface chip,
TS68951 [see ref 6 of Appendix Dj, after conversion
to analog format. This chip and the clock generator
chip, TS68952 [see ref 7 of Appendix DJ, are
connected to the 8 MSB's of the DSP 2 data bus.
The clock generator chip generates the AID and D/A
sampling clocks and the data bit and baud rate
clocks.
2.3. OPERATION
2.3.1. MODES. The modem implementation is fully
compatible with the CCITT recommendation V.32.
It operates at two different bit rates, 9600 and 4800
bps. In the 9600 bps mode, the trellis encoder and
the Viterbi decoder can be switched in or out. Both
the bit rate and trellis options are determined during
the initial modem handshake sequence.
Figure 2 : Functional Block Diagram.
,------------------.. - ..- ..-------------.. --.. -------------------------_ . _.. _.0-:---_----------------------------1
TS75321
1
!
i
i
i
i
TS68950
1
!
i
Alter
:ATO
!
!
!
!
.................................................................................
i
.............................................................................. ~ ................ ·····.. ·······························i
TS75322
:
.LEI
~
TS88951
!
i
i
i
i
i
!RAI
!
TxClocks RxClocks
L--+--------t-------l'...-......•••••••.••.••.•.••••.•.•••••••••.•.•••.•••.•.
-J
l .. _ .... ___________ .. __ .. ____ .. ___ .:... _________________ .. ____ .. _____ .. __ ._.. __ ._.. __ 1_.... _•• _•• _. __ •____ ...
!
!
!!
!
!
!
!
.. ___ •__ j
TxSClk - - - - - '
5/44
141
TS7532
2.3.2. SIGNAL SPECTRUM SHAPING. A square
root of 12.5 percent roll-off raised cosine filter is implemented in the transmitter to properly shape the
transmit signal pulse. This filter is chosen based on
a compromise of two considerations. First, the signal should have a narrow spectrum to avoid severe
distortion on the telephone line. Second, the signal
spectrum should be made as wide as possible to facilitate timing recovery in receiver.
CCITT rec. The ND output samples are sent to the
adaptive equalizer and the signal energy estimator
for the gain control. The adaptive equalizer outputs
a complex number every baud interval, which is then
phase corrected by the carrier recovery loop. The
Viterbi decoder makes hard decisions on the phase
corrected samples for the adaptation of the equalizer and carrier recovery. It also makes soft decisions
with an optimum decoding depth.
2.3.3. ECHO CANCELLATION. The echo canceller
is implemented on a single DSP [see ref 8 of Appendix D] with its associated external RAM. It cancels
both near-end and far-end echoes even in the presence of frequency offset in the far-end echo path.
The near-end echo cancellation is better than 55 dB
and the residual near-end echo is smaller than - 65
dBm with a near-end echo level of - 10 dBm at the
receiver input and a far-end signal level of - 43 dBm.
2.3.5. EQUALIZATION. The modem receiver has a
passband T/3 fractionally spaced automatic adaptive equalizer which can compensate for the signal
degradation caused by low quality line conditions.
The combined near-end and far-end echo cancellers maintain the residual echo level 24 dB below
the received signal even if the far-end echo signal
path introduces up to 10Hz of frequency offset. This
level of cancellation is achieved when the far-end
echo is 8 dB below the received far-end signal.
2.3.4. RECEIVER DESCRIPTION. The incoming signal is sent to the receiver interface chip to have the
echo removed before being sent to DSP 2. The timing recovery algorithm takes the signal after the
echo cancellation to derive the timing errorto control
the sampling phase of the ND. It is able to c.?,pe with
distant modem frequency drifts up to ± 2.1 0 as per
2.3.6. SYNCHRONOUS AND ASYNCHRONOUS
DATA TRANSFER. The V. 32 modem engine provides the control processor and the DTE with both
the transmit and the receive bit clocks (Figure 3).
These clocks are generated by the TS68952 and
are independent of each other. The receive clock
(RxCLK) is derived from the received data signal.
The transmit clock (TxCLK) is free-running at the nominal bit rate (9600 or 4800 bps) except during Digital Loopback Mode when it is synchronous to the
RxCLK. If the transmit clock is free-running and an
external bit clock signal from the terminal is connected to point TxSCLK then the transmit bit clock will
be synchronized to that signal. The baud clocks
(TxRCLK and RxRCLK) are also available to the
control processor. If the TxSCLK pin is not used, it
should be tied to a fixed logic level.
Figure 3 : Clock Signals for Synchronous Transmission.
,----------TxDATA
8 Bit Bus
Control Processor
and
Serial 10 Parallel
RxDATA
TxCLK
RxCLK
Inlerlace
TxRCLK
I
I
TS 7532
I
I
I
I
I
I
TxRCLK
I
I
I
I
I
I
I
I
I
I
TS68952
TxCLK
I
I
RxCLK
I
TxSCLK
I
I
TxSCLK
/
6/44
142
---------,
TS7532
The control processor interface is synchronous with
the transmit baud clock. Eight bits of data are transferred from the control processor to DSP 1 for each
information exchange. At 9600 bps. the data is
transmitted every 2 bauds and the data is transmitted every 4 bauds for 4800 bps. The received bits
are also nominally transferred from DSP 1 to the
control processor once every two transmit baud intervals. When the transmitter is not synchronized
with the receiver. however. the receive baud interval may be slightly shorter or longer than the transmit baud interval. If it is shorter. it is necessary to periodically pass 16 received bits from DSP 1 to the
control processor. If it is longer. then periodically.
there will be no data transmitted from DSP 1 to the
control processor. Since the received bits are being
passed to the DTE at a fixed rate equal to the
RxCLK. some buffering is necessary in the control
processor.
For asynchronous transmission. the clocks are not
required by the DTE. But since the control processor to DSP 1 interface is still synchronous with respect to the transmit baud clock. the control processor must implement the asynchronous to synchronous conversion (as specified in the V. 22 bis recommendation. for example). This will consist of inserting or deleting stop bits as required. to ensure
that the transmitted bit rate is within 0.01 % of the
nominal rate (9600 or4800 bps).
i
2.3.7. TONE GENERATOR. The V.32 Engine has
thirteen tone commands to quickly program the tone
generators to generate the 2100 Hz Answer Tone
(ANSWR) and the tone pairs for DTMF digits
(DTMFO •...• DTMF9. DTMF*. DTMF#). Silence. i.e.
termination of tone generation. is accomplished by
the use of a fourteenth command. SLNTS. These
commands provide the tones and control required
for normal operation of the mod~m.
Some circumstances might arise where additional
tones are desired. For such cases. the V.32 Engine
provides the user with the ability to generate such
additional tones. This special feature is achieved
through use of the tone control commands.
!
The V.32 Engine maintains a pair of locations which
are reserved for tone generation parameters. These
locations are denoted as TONE1 and TONE2.
These locations may be programmed by the use of
the define tone commands. DEFT1 and DEFT2.
These commands provide the two tone generators
with the phase increment of the tone to be generated with respect to the 7200 Hz sample rate.
The normal tone commands automatically program
the tone generators. The DEFT1 and DEFT2 commands do not change the enabled or disabled state
of the tone generators. If a tone is being generated
when the DEFT command is received. the new tone
will be generated without further action on the part
of the user. If tone generation was not in progress it
is not started.
Enabling the tone generators is accomplished by
the tone control commands TGENO. TGEN1.
TGEN2. and TGEN12. Each of these commands affects both tone generators. TGENO disables both
tone generators and TGEN12 enables both tone
generators. To enable tone generator 1 and disable
tone generator 2 the TGEN1 command is used. For
the reverse condition. with generator 1 disabled and
generator 2 enabled. the TGEN2 command is employed. if both tone generators are enabled. one of
the tone levels can be scaled as specified by the
control processor.
Refer to the command in appendix A for more detailed information.
Generation of special user tones is not part of the
normal data communications operations of the modem. Use of this feature may interfere with data
transfer operations. It is the responsability of the
user to insure that the tone generators are used at
a time when such interference will not occur and to
disable both tone generators when the tone generation operations have been completed.
2.3.8. TEST MODES.The modem can be configured in two test modes. namely analog loop back and
digital loop back modes. These loop back modes
conform to the test loops 3 and 2 respectively defined in CCITT recommendation V.54.
In the local analog loop back mode. the transmitter
signal is directly fed back into the local receiver input with the echo canceller enabled. The user is responsible for supplying a switch. which is controllable by the control processor. to enable or disable
the analog loop back mode. The receiver descrambier is set as the inverse of the transmitter scrambler so that the receiver detects correct bits.
If the modem is configured in the digital.loop back
mode. the transmitter clock is locked to the receiver
clock and the received bits are used as the transmitter input.
2.3.9. POWER ON INITIALIZATION. When the power is turned on. the transmitter interface sets the
output signal attenuation to infinite. This avoids undesirable signal transmission on the telephone line
[see ref 5 of Appendix DJ. The gain of the AGC in the
receive interface is set at the lowest level to avoid signal clipping during the initial handshake. The clock
generator is programmed to generate all the necessary clocks for the 9600 bps mode. The clocks include the 7200 Hz sampling clock. the 2400 Hz baud
rate clocks and the 9600 bps bit rate clocks. The
7/44
143
TS7532
transmit clocks are free running when the TxSClk pin
is tied to a fixed logic level. Otherwise, the transmit
bit clock is synchronized to the frequency present at
the TxSClk pin. DSP 1 is configured properly to receive commands from the control processor.
2.4. MODEM INTERFACE [Figure 4]
2.4.1. ANALOG INTERFACE. The transmit signal
at the tip and ring is programmable over a 22 dB dynamic range by 2 dB steps in TS68950. The signal
level can be further scaled to any value by setting a
scaling factor in the DSP. The nominal Transmit level, at the ATO pin is - 5.7 dBm.
2.4.2. DIGITAL INTERFACE. The DSP and control
processor interface complies with the system bus
interface of the TS68930. The interface to the
control processor is managed by DSP 1 as shown
in Figure 1. The DSP signals which are presented
to the interface, and a brief definition of the signals
are tabulated in table 1.
Table 1 : Digital Interface Signals.
Interface Signals
Signal Definition
DOH
DIH
D2H
D3H
D4H
D5H
D6H
D7H
Data Bus (LSB)
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus (MSB)
RWL
DSL
INTL
CSL
RSL
Write Signal
Data Strobe
Mailbox Handshake
DSP Select
Register Select
TxRCLK
RxRCLK
TxCLK
RxCLK
TxMCLK
RxMCLK
TxSCLK
Transmit baud rate clock
Receive baud rate clock
Transmit bit rate clock
Receive bit rate clock
Transmit multiplex clock
Receive multiplex clock
Transmit terminal clock
All infonmation exchanges across this interface
conform to the three byte mailbox structure [see ref 4
of Appendix 0] and protocol of the DSP. As may be
seen in the table, the DSP generates a control signal,
INTL, which defines the mailbox handshake operation.
2.4.3. CONTROL PROCESSORJDSP INTERFACE. As seen by the software in the user provided
control processor, DSP 1 is a synchronous machine.
It requires the attention of the control processor at
regular intervals in order to perform properly. Any
failure of the control processor to interact with the
8/44
144
modem engine in a timely manner will result in reduced performance or improper operation.
Each interaction begins when the control processor
sends a three byte command to the mailbox. Once
the command has been written to the mailbox, the
ownership of the mailbox is relinquished by the
control processor. Upon acquisition of the mailbox,
DSP 1 reads the command bytes and then sends a
three byte response to the mailbox. Then, DSP 1 relinquishes the ownership of the mailbox back to the
control processor. The received command is then
decoded and the embedded data and/or operational parameters are extracted and acted upon as appropriate. The modem status information will be collected for the next mailbox exchange. The control
processor handles the returned information as soon
as it regains the ownership of the mailbox.
Because the control processor owns the mailbox initially, it may store a command at any time before it
is required by DSP 1. After this, the mailbox becomes available to DSP 1 and can be read by it when
required.
2.4.4. MAILBOX DESCRIPTION.The mailbox located internally to the DSP contains 3-byte input (RIN)
and 3-byte output (ROUT) shift registers. The DSP
has an intemal flag RDYOIN which indicates whether the DSP (RDYOIN = 0) or control processor
(RDYOIN = 1) has access to the mailbox. The DSP
can relinquish its accessability to the mailbox by setting RDYOIN but it can no longer regain access to
the mailbox as RDYOIN is reset only after the control
processor relinquishes its accessability to the mailbox. The access protocol and system bus transfers
are controlled by an internal I/O sequencer within
the DSP described as follows:
1. The mailbox is made available to the control processor by the DSP program which sets RDYOIN
flag to 1. This action will cause INTL mailbox
handshake signal to switch to the active (low)
state.
2. The control processor detects INTL active and
dummy reads the mailbox by forcing DSP Select
(CSL) and Register Select (RSL) low along with
write signal (RWL) high. The activated Data
Strobe signal (DSL = 0) validates the above sigmils.
3. The DSP detects the dummy read of its mailbox
via the control signals mentioned in 2 and negates
INTL mailbox handshake signal within 800 ns.
4. The control processor detects the negation of
INTL indicating that the DSP mailbox is available
for data transfers. The control processor writes
TS7532
three a-bit bytes and/or reads three a-bit bytes in
the mailbox shift registers RIN, ROUT respectively.
5. The exchange protocol described above is terminated by the control processor performing a dummy read of the mailbox as in 2 but with RSL in the
high state.
6. The RDYOIN flag within the DSP is cleared to 0
by the dummy read of the mailbox in step 5 and
the DSP now has access to RIN and ROUT registers within the mailbox.
Figure 4 : Functional Interconnect Diagram.
T$7532
-~~
TxRCLK
RxRCLK
TxMCLK
RxMCLK
RAI
V.24 Inlllrlace
-
113
114
115
103
104
Clrl
ATO
I
~ ~
Unll
InlllrfllclI
----
Tlliephone
Une
TxSCLK
TxCLK
RxCLK
DOH •. D7H
HOBI
Proce88or
-
CSL
RSL
DSL
RWL
INTL
+5VA
-5VA
AGND
+5
DGND
RSTLO •• 2
Power
Supply
I
3. USER INTERFACE - COMMAND SET
The command set has the following attractive features:
_ user friendly with easy to remember mnemonics
_ allows straightforward expansion with new commands to suit specific customization requirements
_ fully compatible with other SGS-THOMSON
DSP-based modem products.
The command set has been designed to provide the
necessary functional control of the V.32 Engine.
Each command falls into one of several groups, based on function and the presence or absence of parameters. The length of the OP code varies with instruction type, but in all cases, a command consists
of three bytes.
The commands which pass parameters or data to
DSP 1 have a short OP code format. Byte 0 forms
the OP code portion of the command. Bytes 1 and
2 are data and/or parameters associated with each
OP code. The meaning of the last two bytes is dependent on the specific instruction.
Other instructions command the V.32 Engine to perform certain specific tasks. These do not pass parameters or data to the V.32 Engine. These commands have an OP code which is a full 24 bits in
length.
The command set of the V.32 Engine is summarized below. The descriptions are of the form:
MNEMONIC (OPCODE) : DESCRIPTION.
For detailed information and data format specifics
of each command, please refer to appendix A.
9/44
145
TS7532
3.1. COMMAND SUMMARY
3.1.1. OPERATIONAL CONTROL COMMANDS.
FREZ (14): Freeze adaptive processes. Freeze the
adaptive processes as specified by the data in bits
o and 1 of byte 1. Bit 0 of byte 1 controls the adaptive equalizer. Freeze the equalizer if bit 0 of byte 1
is 1. A 0 in this bit will unfreeze the equalizer. Echo
canceller adaptation is controlled by bit 1 of byte 1.
if bit 1 is 1, the echo canceller adaptation is frozen.
The echo canceller adaptation is unfrozen by a 0 in
bit 1.
HSHK (040000) : Handshake. Begin the handshake
sequence. The V.32 modem engine carries out all
the steps defined in the CCITT r(3commendation.
The status reported to the control processor will indicate the success or failure of the process and its
progress.
INIT (0600CO) : Initialize. Initialize the V.32 modem
engine. Set all parameters to default values and wait
for commands for the control processor.
JMP (06) : Force code execution at address. Force
the selected processor of the V.32 Engine to begin
execution at the address specified.
NOP (000000) : No Operation. No new operation is
commanded. The state of the V.32 engine remains
unaltered and a previously'invoked multi-baud command (such as HSHK) continues.
RTRA (050000) : Retrain. Start sending the retrain
sequence as defined in the CCITT recommendation.
SETGN (02) : Set Gain. This command sets a global gain factor, which will be multiplied by all transmit samples before being sent to the TS68950.
Bytes 1 and 2 store the gain factor.
3.1.2. DATA COMMUNICATIONS COMMANDS.
XMIT (03) : Transmit data. Transmit data to far end
modem. The data is provided in byte 1 of the command, where the least significant bit is the first bit to
be transmitted. The third byte of the command must
be provided, but is not used. Hence, any value may
be supplied.
XMITI (01 ) : Transmit data and Initiate additional cycle. Transmit data and inform the DSP to accept
another command at the next transmit baud. If the
next command requires an answer from DSP 1, the
control processor has to keep issuing this command
followed by a command which does not requires an
answer until the answer has been received.
3.1.3. MEMORY. MANIPULATION COMMANDS.
SPAC (13) : Store Parameter And Count. Store parameter in addressed memory and increment the
pointer. This command passes data in bytes 1 and
2, least significant byte in byte 1. It is used to write
10/44
146
an arbitrary 16-bit value into the writable memory location currently specified by the Memory Address
Register. The contents of the Memory Address Register are incremented by 1 at the completion of this
command.
SPAM (12) : Store parameter in Addressed Memory. This command passes data in bytes 1 and 2,
least significant byte in byte 1. It is used to write an
arbitrary 16-bit value into the writable momory location currently specified by the Memory Address Register.
WARP (10) : Write Address and Return Parameter.
This command allows the controller to read any of
the XRAM, YRAM, ERAM or CROM of any of the
three modem DSPs without interrupting the processors. The address to the V.32 modem engine is provided in bytes 1 and 2 of the command (least significant byte first). DSP 1 stores the address in the Memory Address Register and returns the contents of
the addressed location.
WARPX (11) : Write Address and Return Parameter Complex. The address to the V.32 modem engine is provided in bytes 1 and 2 of the command
(least significant byte first). DSP 1 stores the address in the Memory Address Register. The most significant bytes of the real and imaginary parts of a
complex number are returned. The 8 most significant bits of the data addressed by the Memory Address Register are returned to the control processor
through byte 1. Byte 2 stores the 8 most significant
bits of the data at the location immediately higher.
The Memory Address Register retains the address
provided. (i.e. it is not incremented.)
3.1 .4. CON FIGU RATION CONTROL COMMAN OS
CV32 (20) : Configure modem for V.32. Configure
the modem as Originate 1 Answer, 9600/4800, Viterbi 1 No-Viterbi, Analog Loopback, Digital Loopback.
CV29 (21) 1 CV27T (22) 1 CV26T (23) 1 CV23 (24)
1CV22B (25) 1CV21 (26) 1CB212 (27) 1CB 103 (28)
1 CGRP2 (29) : Configure the modem to the basic
operating mode specified, as well as Originate/Answer, 9600/4800, Analog Loopback, Digital Loopback. These commands are not supported by the
V.32 Engine. They are listed here only for reference
(i.e. for future upgrade or other product).
3.1.5. MAFE MANIPULATION COMMANDS.
CMAFE (07) : Configure MAFE. The following two
bytes of this command are written directly to the
MAFE chip set (TS68950/1/2). This allows the
control processor to configure parameters, such as
the transmit level, the receiver analog front end, and
the transmit and receive clocks.
RRR1 (080000) : Read Register 1. Causes the V.32
TS7532
Engine to read and immediately return the 12 bit
contents of the MAFE register RR1.
RRR2 (090000) : Read Register 2. Causes the V.32
Engine to read and immediately return the 12 bit
contents of the MAFE register RR2.
WTR1 (OA) : Write Register 1. Causes the V.32 Engine to write the supplied data to the MAFE register
TR1.
WTR2 (OB) : Write Register 2. Causes the V.32 Engine to write the supplied data to the MAFE register
TR2.
3.1.6. TONE SELECT COMMANDS.
TONE (OC) : Select Tone. Program the tone generator(s) for the desired toners). Examples include:
- ANSWR (OC 1000) : Program the tone generator
for the 2100 Hz answer tone.
- DTMF (see appendix) : Program the tone generators for the tone pair which forms the specified
DTMF digit.
This command selects the tones to be transmitted,
but does not enable the tone generators. To transmit the tones, the tone control commands must be
issued.
3.1.7. TONE CONTROL COMMANDS
DEFT1 (OE) : Define Tone 1. Define tone 1 as specified by the parameter provided. The two data bytes
following the opcode are used to program, but not
enable, tone generator 1. The data for the tone is
represented as a phase offset per sample. Byte 1
stores the least significant byte of the phase increment.
DEFT2 (OF) : Define Tone 2. Define tone 2 as specified by the parameter provided. The two data bytes
following the opcode are used to program, but not
enable, tone generator 2. The data for the tone is
represented as a phase offset per sample. Byte 1
stores the least significant byte of the phase increment.
SLNT (000000) : Silence the tone generators. Discontinue tone transmissions by disabling the tone
generators.
TGEN (00) : Tone Generator control. Enable or disable tone generator 1 and tone generator 2 according to parameter provided. If both tone generators
are enabled, the level of tone 2 is 2 dB higher than
that of tone 1. However, the user can change the relative levels by modifying the amplitude level of both
tone generators.
3.2. STATUS REPORTING
Whenever DSP 1 owns the mailbox, it transmits the
modem status to the control processor. The status
consists of three bytes of information which are stored by DSP 1 in its ROUT register for access by the
control processor. These three bytes may consist of
received bits and modem status or they may contain
the answers to the previous command, such as
WARP and RRR1/2.
Data bits have higher priority than the answer to the
previous command. If both data byte and command
answer are ready to be sent, the data will be sent.
Byte 0 contains status flags. Refer to appendix B for
the detailed format of the status response. The four
most significant bits, FOO, F01, F10 and F11, indicate various conditions during the call establishment, handshaking and the data modes. They have
different meanings in different modes. The flag
DAV1 and DAV2 are used to indicate the type of information contained in bytes 1 and 2. Bit H is used
to indicate the condition of the handshake and bit
107 informs the control processor whether the 107
flag has to be set.
DAV1 and DAV2. If both DAV1 and DAV2 are set
to 1, bytes 1 and 2 contain the data in response to
the previous command. Refer to the relevant commands in appendix A to get the detailed information
on the interpretation of the data in bytes 1 and 2.
Otherwise, they contain either the received data bits
or the handshake detection status or both.
If both bits are set to 0, both byte 1 and byte 2 contain
the data bits, where the bits in byte 1 are received
earlier in time. The least significant bit is the first bit
received. The data bits are stored in byte 1 and the
modem status is stored in byte 2 when DAV2 is 1
and DAV1 is O. When DAV1 is 1 and DAV2 is 0, the
control processor should ignore the data in byte 1
and get the detection status from byte 2.
During handshake operations the V.32 Engine reports the detection status regularly. When the rate
sequence is received, it will be transferred in byte 1
of the response. Each bit in byte 2 indicates the detection of a specific event in the training sequence.
It has different meanings for call and answer modems. For detailed information, refer to appendix B.
During the data mode, byte 2 is always provided,
but is used only when there are two bytes of data to
transmit. This occurs occasionally when the receiver clock is running faster than the transmitter clock.
11/44
147
TS7532
FOO-F11 bits. During the call establishment operation, the V.32 Engine reports call progress tones
through the F01 and FOO flags. FOO is set to 1 when
the signal energy in frequency band 1 is above the
threshold level. F01 is set to 1 when the signal energy in band 2 is above the threshold level. Detection of the 2100 Hz answertone is indicated by setting the F1 0 flag to a 1.
During handshake operations, all four bits are used
to indicate the line condition and some detection results. FOO is set to 0 if the line quality is good and 1
if it is bad. F01 is set to 1 if any segment in the training sequence is not detected within a time out. This
bit can be used to indicate a non V.32 detection if
either AA is not detected in the answer modem or
the AC is not detected in the call modem. Both FOO
and FO 1 are set to 1 when an illegal mode or a GSTN
cleardown is received in the rate sequence.
The detection of the rate sequence is reported in the
flags F11 and F10. When the modem is operating
at 9600 bps without trellis coding, these bits are both
set to O. With trellis coding at 9600 bps, F11 is set
to 1 and F10 is cleared to O. For 4800 bps, 0 and 1
will be placed in F11 and F10, respectively. When
both F11 and F10 are set to 1, the modem has ne-
gotiated with the far end modem and determined
that the maximum negotiated operating speed is
2400 bps.
During data mode, the perceived line quality is reported in the flags F01 and FOO. The line conditions
are reported as either good (code 00), poor (code
01), or terrible (code 10). The code 10 should be interpreted as a local modem retrain request. Upon
receipt of this code, the controller can issue the
RTRA command to begin the retrain procedure. The
code 11 is used when the remote modem begins a
retrain sequence. The control processor is then responsible for manipulating the appropriate data communications interface signals.
Hand 107 bits. When the V.32 Engine is commanded to perform the CCITT handshake sequence, the
H bit will be set to 1 for the duration of the handshake
operation. At the successful completion of the handshake operation the H flag will go to 0 and the control
processor is then responsible for manipulating the
appropriate data communications interface signals.
e.g. 106 and 109. The 107 flag is set to a 1 to indicate that the controller should assert signal 107 on
the data communications interface.
3.3. COMMAND LIST
OPERATIONAL CONTROL COMMANDS
Command
Mnemonic
uFzec
Frezq
Frezc
uFzeq
hshk
initt
jmpt
nop
rtra
setgnt
OP Code
(HEX)
170000
1BOOOO
160000
1COOOO
040000
0600CO
06
000000
050000
02
Description
Unfreeze Echo Canceller
Freeze the Equalizer Adaptation
Freeze the Echo Canceller Adaptation
Unfreeze Equalizer
Handshake with Other Modem
Initialize Modem
Force Code Execution
No Operation
Retrain
Set the Scaling Factor for the Transmitter
DATA COMMUNICATIONS COMMANDS
Command
Mnemonic
xmit
xmitit
t
OP Code
(HEX)
03
01
Future enhancement or other product reference.
12/44
148
Description
Transmit Data
Transmit Data and Initiate Additional Transfer
TS7532
.
MAFE MANIPULATION COMMANDS
Command
Mnemonic
cmafet
rrr1 t
rrr2t
wtr1t
wtr2t
OP Code
(HEX)
07
080000
090000
OA
OB
Description
Configure MAFE Chipset
Read MAFE Reg RR1
Read MAFE Reg RR2
Write MAFE Reg TR1
Write MAFE Reg TR2
TONE SELECT COMMANDS
Command
Mnemonic
answ
dtmf 0
dtmf 1
dtmf 2
dtmf 3
dtmf 4
dtmf 5
dtmf 6
dtmf 7
dtmf 8
dtmf 9
dtmf *
dtmf #
tone
I
OP Code
(HEX)
OC1000
OCOOOO
OC0100
OC0200
OC0300
OC0400
OC0500
OC0600
OC0700
OC0800
OC0900
OCOEOO
OCOFOO
OC
Description
Select 2100 Hz Answer Tone
Select DTMF Digit 0
Select DTMF Digit 1
Select DTMF Digit 2
Select DTMF Digit 3
Select DTMF Digit 4
Select DTMF Digit 5
Select DTMF Digit 6
Select DTMF Digit 7
Select DTMF Digit 8
Select DTMF Digit 9
Select DTMF Digit *
Select DTMF Digit #
Select Tone (s)
CONFIGURATION CONTROL COMMANDS
Command
Mnemonic
cv32
cv29t
cv27tt
cv26tt
cv23t
cv22Bt
cv21t
cb212t
cb103t
cgrp2t
OP Code
(HEX)
20
21
22
23
24
25
26
27
28
29
Description
Configure Modem for V.32
t Configure Modem for V.29
t Configure Modem for V.27t
t Configure Modem for V.26t
t Configure Modem for V.23
t Configure Modem for V.22 / V.22 bis
t Configure Modem for V.21
t Configure Modem for Bell 212
t Configure Modem for Bell 103
t Configure Modem for Group 2 Fax
MEMORY MANIPULATION COMMANDS
Command
Mnemonic
spact
spamt
warpt
warpxt
OP Code
(HEX)
13
12
10
11
Description
Write
Write
Write
Write
MEM and Increment MEM Pointer
MEM
MEM Pointer & Read MEM
MEM Pointer & Read MEM & MEM + 1
I
t Future enhancement or other product reference.
13/44
149
TS7532
TONE CONTROL COMMANDS
Command
Mnemonic
deft1t
deft2t
slnt
tgen 0
tgen 1t
tgen 2t
tgen 3
OP Code
(HEX)
Description
Define Tone 1
Define Tone 2
Transmit no Tone
Tone Generators Disabled
Tone Generator 1 Enabled
Tone Generator 2 Enabled
Tone Generators 1 & 2 Enabled
OE
OF
ODOOOO
ODOOOO
OD0100
OD0200
OD0300
4. ELECTRICAL SPECIFICATIONS
4.1. MAXIMUM RATINGS:
TS75320/1/2
Value
Unit
Vee'
Supply Voltage
Parameter
- 0.3 to 7.0
V
Vin*
Input Voltage
- 0.3 to 7.0
V
o to 70
°C
- 55 to 150
°C
Symbol
TA
T stg
Operating Temperature Range
Storage Temperature Range
• With respect to V ss.
Stresses above those hereby listed may cause permanent damage to the device. The ratings are stress ones only and functional operation
of the device at these or any conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to
maximum rating conditions for extended periods may affect device reliability. Standard MOS circuits handling procedure should be used to
avoid possible damage to the device.
TS68950/1/2
Parameter
Value
Supply Voltage between V + and AGND or DGND
- 0.3 to + 7
V
Supply Voltage between V - and AGND or DGND
- 7 to + 0.3
V
Symbol
Voltage between AGND and DGND
- 0.3 to + 0.3
V
Digital Input Voltage
DGND - 0.3 to Vee+ + 0.3
V
Digital Output Voltage
DGND - 0.3 to Vee+ + 0.3
V
Digital Output Current
- 20 to + 20
mA
V
Analog Input Voltage
Vee - 0.3 to Vee+ + 0.3
Analog Output Voltage
Vee - 0.3 to Vee+ + 0.3
Analog Output Current
- 10 to + 10
Power Dissipation
Toper
T stg
14/44
150
Unit
Operating Temperature
Storage Temperature
V
mA-
500
mW
o to + 70
°C
- 65 to + 150
°C
TS7532
4.2. DC ELECTRICAL CHARACTERISTICS
DGND = AGND = 0 V
Digital Supply
Vcc = 5.0 V ± 5 %, Vss = 0, TA = 0 to + 70'C (Unless otherwise specified)
Symbol
Min.
Typ.
Max.
Unit
Vee
Supply Voltage
Parameter
4.75
5
5.25
V
V,L
Input Low Voltage
- 0.3
0.8
V
V,H
Input High Voltage
2.4
Vee
V
Ii
Input Extal Current
- 50
+ 50
lin
Input Leakage Current
-10
10
!1A
!1A
VOH
Output High Voltage (I'oad
except DTAC~
=-
VOL
Output Low Voltage (I'oad
= 3.2
PD
300 !lA)
2.7
V
mAl
4.5
Total Power Dissipation
0.5
V
6.6
W
- 20
!lA
DC
10
Cin
Input Capacitance
ITs l
Three State (off state) Input Current (0.4 V - 2.4 V)
Tamb
Operating Temperature (note 1)
R BJA
Thermal Resistance Junction-ambient
- 20
0
pF
70
28
°C/W
Note1: Case temperature Tc must be maintained below 100 C.
Analog Supply
Symbol
Max.
Unit
V+
Positive Power Supply
Parameter
Min.
4.75
Typ.
5.25
V
V-
Negative Power Supply
- 5.25
- 4.75
V
I+
Positive Supply Current
35
mA
1-
Negative Supply Current
- 35
15/44
151
TS7532
4.3. AC ELECTRICAL SPECIFICATIONS
4.3.1. CLOCK AND CONTROL PINS TIMING
(Vcc = 5.0 V ± 5 %, TA = O· to + 70'C, see figure 5)
OUTPUT LOAD = 50 pF + DC characteristics I load
REFERENCE LEVELS:
AC TESTING INPUTS ARE DRIVEN AT 2.4 V FOR A LOGIC "1" AND 0.4 V
FOR A LOGIC "O".TIMING MEASUREMENTS ARE MADE AT 1.5 V FOR
BOTH A LOGIC "1" AND "0".
tr, tf $ 5 ns for input signal
Parameter
Symbol
External Clock Cycle Time
tfex
External Clock Fall Time
t rex
External Clock Rise Time
teoh
EXTAL to CLKOUT High Delay
teal
EXTAL to CLKOUT Low Delay
tear
CLKOUT Rise Time
teof
CLKOUT Fall Time
tdle
CLKOUT to Control Output Low (INTL)
tdhe
CLKOUT to Control High
EXTAL
CLKOUT
INTL
16/44
152
Typ.
Max.
(INTL)
Unit
ns
5
5
Figure 5 : Clock and Control Pins Timing.
tcex
Min.
40
tcex
25
25
ns
ns
ns
ns
10
10
50
50
ns
ns
ns
ns
TS7532
4.3.2. TS68952 : Clock Generator
CLRYSTAL OSCILLATOR INTERFACE
Symbol
Parameter
VIL
Input Low Level Voltage
Conditions
VIH
Input High Level Voltage
IlL
Input Low Level Current
IIH
Input High Level Current VIH min"; VI ,,; V+
Min.
DGND ,,; VI ,,; VIL max
Typ.
Max.
Unit
1.5
V
3.5
V
-15
IlA
15
IlA
CLOCK WAVE FORMS
Symbol
Min.
Typ.
Main Clock Period
XTAL1 Input
150
173.6
tWCL
Main Clock Low Level
Width
XTAL1 Input
50
ns
tWCH
Main Clock High Level
Width
XTAL1 Input
50
ns
tRC
Main Clock Rise Time
XTAL1 Input
50
ns
tFC
Main Clock Fall Time
XTALI Input
50
ns
tDe
Clock Output Delay
Time
All Clock Outputs CL=50 pF
500
ns
he
Clock Output Transition
Time
All Clock Outputs CL=50 pF
100
ns
PC
Parameter
Conditions
Max.
Unit
ns
Unless otherwise noted, electrical characteristics are specified over the operating range. Typical values are given for V· = 5.0 V
and t amb = 25 'C.
Figure 6 : Clock Generator.
PC
'WCH
'WCL
.-
1.5 V
~
I
tRC-- f--
.-
'FC
-=-1
V
13.5 V
MAIN CLOCK
INPUT
XTAL 1
1
toe
\
CLOCK OUTPUTS
19 CLOCKS)
J
~
If 2.2
V
O.S
v
1\
tTC
17/44
153
TS7532
4.3.3.LOCAL BUS TIMING
(Vee = 5.0 V ± 5 %, TA = 0' to + 70'C, see figure 7)
Parameter
Symbol
Min.
Max.
Unit
1/2tc-15
112 tc
ns
tpw
RD, WR, DS Pulse Width
tAH
Address Hold Time
10
ns
tDsw
Data Set-up Time, Write Cycle
25
ns
tDHW
Data Hold Time, Write Cycle
10
tDZW
DS High to Data High Impedance, Write Cycle
tDSR
Data Set-up Time, Read Cycle
tDHR
Data Hold Time, Read Cycle
tARW
Address Valid to WR, DS, RD Low
ns
40
ns
20
ns
5
ns
1/2 tc- 40
ns
Figure 7 : Local Bus Timing Diagram .
.
I AH
~
ADDRESSES
A8-A 11 ,ADO-AD?
._-_._-_._-
-~
K=
IpW
I---------------~
---
RD.DS,WR
\
R/W
--_.-
I Ap,'I{
/
-
;-._---
r----~
I
DATA IN
18/44
154
j
1'-------·
ARW
««(I'
DO-DIS
DATA OUT
DO-DIS
IpW
I----------------.-~
----
I DSW
'---------
IDH! I DZWI
.
DATA OUT
,~"
~.
f ","==M
\\
III
TS7532
4.3.4. SYSTEM BUS TIMING
(Vee = 5.0 V ± 5 %, TA = 0° to + 70°C, see figure 8)
Symbol
Parameter
Max.
Min.
Unit
tspw
SDS Pulse Width
60
ns
tSAW
SR 1 W, CS, RS Set-up Time
20
ns
tSAH
SR 1 W, CS, RS Hold After SDS High
5
ns
tSDSR
Data Set-up Time, Read Cycle
20
ns
tSDHR
Data Hold Time, Read Cycle
5
tSDSW
Data Set-up Time, Write Cycle
tSDHW
Data Hold Time, Write Cycle
tDSHIR
SDS High to IRQ High
tSDZW
SDS High to Data High Impedance, Write Cycle
ns
ns
35
10
50
ns
800
ns
40
ns
Figure 8 : System Bus Timing Diagram.
tspw
SDS
\
SR;W.CS
RS
[RWL.CSL.RSL]
J
/
tSAW
tSAH
~
K
+
t SDSR
ADO·AD7
DATA IN
[DOH·D7H]
/
"
+
DATA IN
~
:< «<
DATA OUT
[> >~tDSHDT
t DSLDT
DTACK
'"
tSDZW
tpSDSW
ADO·AD7
DATA OUT
t SDfiR
\
;--
/
tDSHIR
IRQ
;1
+ Note: Signal names on Host Processor Interface.
19/44
155
TS7532
5. PIN CONNECTIONS
TS75320 - TS75321 - TS75322
04
05
06
07
08
09
010
011
012
013
014
D15
VSS
XTAl
EXTAl
ClKOUT
AD
Lf
..
"
.,
.,
~~
'5
'6
"
"
SR/W
,g
X
SOS
CS
RS
RESET
20
2'!
IRQ
BSO
BSl
I3S2
VCC
Al0
'8
WH
03
02
01
DO
lG
";1
"
"
02
<3
,.
jj
,.
"
"
"
TS68950
AS
A07
AD6
AD5
AD4
AD3
AD2
ADl
ADO
BE5
BE6
03
07
02
E
01
DO
CSO
TxCCL"
CS1
CLr
RSO
RS1
EECl
OGNO
ATO
TEST
;'XI
,
\'
V
.
4G'JD
TS68952
04
04
05
06
03
06
03
07
02
07
02
E
Dl
E
R/w
DO
R/Vi
TxCCLK
CSO
TxCClK
CSO
TxCLK
CSl
RxCClK
CSl
RxClK
RSO
ClK
RxCCLK
RSl
v+
RSO
RSl
RxRClK
OGNO
EEl
AGC2
lEI
RFO
RAJ
V-
AGNO
20/44
01
RxMCLK
CDl
AGCI
156
01
RNJ
TS68951
05
OS
06
TxMClK
+
XTAL1
V
TxRClK
ClK
TS7532
6. ORDERING INFORMATION
Part Number
Package
Temperature Range
o DC to + 70 DC
o DC to + 70 DC
o DC to + 70 DC
o DC to + 70 DC
o DC to + 70 DC
o DC to + 70 DC
TS75320CP
TS75321CP
TS75322CP
TS68950CP
TS68951CP
TS68952CP
DIP48
DIP48
DIP48
DIP24
DIP28
DIP28
7.PACKAGE MECHANICAL DATA
TS75320/TS75321/TS75322
48 Pins - Plastic Dip.
4.57max
16.lmax.
0.51 min
-;
/
0.2
0.3
25
Z4
63.5max.
14
48
PINS
21/44
157
TS7532
TS68950
24 Pins - Plastic Dip.
" = 2.54
4.57max.
16.1 max .
I..
.. !
0.51 min.
I
I
I
I
\
0.38
0.508
3.1
3.9
\
O~\
0.2
0.3
115~
I
15.24
13
24
Dotum
(1 J
Nominal dimension
(2)
True geometrical position
12
32.6 max.
14
24
PINS
TS68951/TS68952
28 Pins - Plastic Dip.
"=2.54
4,57max.
Datum
Or
o
14
6
22/44
158
28
PINS
TS7532
APPENDIX A
COMMAND SET DESCRIPTION
cmafet -
configure the TS68950/1/2
components of the V.32 Engine
INSTRUCTION TYPE
MAFE manipulation command
OPCODE
07
SYNOPSIS
cmafe address register code data
DESCRIPTION
cmafe is used to directly manipulate the operating
parameters of the TS68950/1/2 components of the
V.32 Engine. This is a low level command which allows the controller to alter such things as the transmit level, transmit timing, receive timing, and receiver parameters, etc. The command consists of asingle byte OPcode followed by a byte containing the
address code for the desired register and a data
byte for the addressed register. The data bytes will
be transferred in the order received and interpreted
by the addressed device. Refer to the data sheets
of the TS68950, TS68951, and TS68952 for programming specifics.
BYTE 0 DEFINITION (OP CODE)
1
~~B-~------,---------1
·-'--------1-'----1 J
BYTE 1 DEFINITION
REG CODE (Refer to TS68950 Data Sheet).
BYTE 2 DEFINITION
DATA BYTE (Refer to TS68950 Data Sheet).
23/44
159
TS7532
APPENDIX A
cv32 - configure the V.32 Engine
INSTRUCTION TYPE
BYTE 2 DEFINITION
configuration control command
E3[ AT~~~~r~~r~~T~~VJ~;-[
OPCODE
20
FLAG
DLt
SYNOPSIS
ATN3-0t
cv32 speed ec orig atn al dl fc
DESCRIPTION
RSV
cv32 is used to alter the operating parameters of the
V.32 Engine. The passed parameters provide a two
bit speed code which selects the desired baud rate.
Another parameter explicitly turns on or off the echo
canceller. If the V.32 Engine is to operate in the originate mode, the orig parameter must be set. When
this parameter is not set, the V.32 Engine is configured as an answer mode device. The al and dl parameters allow the user to select between the analog and digital loopback test conditions, respectively. The transmit attenuation level is selected by the
atn parameter. etc.
BYTE 0 DEFINITION (OP CODE)
[0]-0I
o-T-oJ 0
- [1
[
0
[~
BYTE 1 DEFINITION
EL RS~.[
FC [ EC [ AL [ SP1 [
SP~J~RI;]
SPEED CODE
SP1-0
00: 9600 bps
01 : 4800 bps
11 : 2400 bps
FLAG
FC
ECt
ORIG
ALt
RSV
24/44
160
BIT
0/1
0/1
0/1
0/1
DEFINITION
Do notlDo force cleardown
Echo Canceller offlon
Answer mode I Originate mode
Analog Loopback test disabled I
enabled
Reserved
BIT
0/1
DEFINITION
Digital Loopback test disabledl
enabled
Transmit attenuation
dB to 22 dB : codes 0000 to 1011
in 2 dB steps
Infinite: codes 1100 to 1111
Reserved
o
TS7532
APPENDIX A
deft 1t - define tone 1
deft2t - define tone 2
INSTRUCTION TYPE
tone control command
INSTRUCTION TYPE
tone control command
OPCODE
OPCODE
OE
OF
SYNOPSIS
deft tone descriptor
SYNOPSIS
deft tone descriptor
DESCRIPTION
deft1 is a command which used to program tone
generator 1. The 16 bit value provided is used as
the phase offset per sample for the generator. The
deft1 command does not enable the tone generator.
See also tgen.
DESCRIPTION
deft2 is a command which used to program tone
generator 2. The 16 bit value provided is used as
the phase offset per sample for the generator. The
deft2 command does not enable the tone generator.
See also tgen.
BYTE 0 DEFINITION (OP CODE)
BYTE 0 DEFINITION (OP CODE)
I 01
T
01 0 1 01 1 1 11 1 0 1 1 01 0 1 0 1
BYTE 1 DEFINITION
oJ 1 11 11
11 1
BYTE 1 DEFINITION
1 P7 1 P6 1 P5 I P4 1 P3 1 P2 1~_~0]
L±1P5 1P4 1 P3 1P2 1 P1EJ
LOW BYTE OF OESCRIPTOR.
LOW BYTE OF DESCRIPTOR.
BYTE 2 DEFINITION
BYTE 2 DEFINITION
[ P15 1P141 P131 P121 P11 1P10 1 pg I::~
l_~151 P141 P1~__~~~11~10 1 pg I_~~
HI BYTE OF DESCRIPTOR.
HI BYTE OF DESCRIPTOR.
25/44
----------------------
161
TS7532
APPENDIX A
frzc - Freeze the echo canceller adapta-
frezq - Freeze the equalizer adaptation
tion
INSTRUCTION TYPE
INSTRUCTION TYPE
operational control command
operational control command
OPCODE
160000
OPCODE
180000
SYNOPSIS
SYNOPSIS
frzec
frzezq
DESCRIPTION
DESCRIPTION
frzec causes the V.32 Engine to enable or disable
the adaptation of the echo canceller, to the current
parameter.
frzezq causes the V.32 Engine to disable the adaptation of the equalizer.
BYTE 1 DEFINITION
BYTE 1 DEFINITION
BYTE 2 DEFINITION
BYTE 2 DEFINITION
lolololoJololojiJ ~Joioioioioioiol
26/44
162
TS7532
APPENDIX A
hshk - begin handshake sequence
INSTRUCTION TYPE
operational control command
OPCODE
040000
SYNOPSIS
hshk
DESCRIPTION
hshk is used to command the V.32 Engine to begin
the handshake sequence processing. The progress
of the handshake is reported to the control processor along with the data bits. For detailed information, refer to appendix B.
BYTE 0 DEFINITION (OP CODE)
lil I 0 I 0 I 01 I 0 1 0 I
o
1
BYTE 1 DEFINITION (OP CODE)
BYTE 2 DEFINITION (OP CODE)
li I 0 1.0 I 0 I_~J~-]
~
~""
SCiS-THOMSON
~U!:IllI@~~[M;1i'IllI@IIlU~@
27/44
163
TS7532
APPENDIX A
in itt - Initialize the V.32 Engine
jmpt - force code execution at address
INSTRUCTION TYPE
INSTRUCTION TYPE
operational control command
operational control command
OPCODE
OPCODE
0600CO
06
SYNOPSIS
init
jmp processor code address
DESCRIPTION
init forces the V.32 Engine to reset all parameters
to their default conditions and restart operations.
jmp forces the selected processor of the V.32 Engine to begin execution at the address specified.
BYTE 0 DEFINITION (OP CODE)
BYTE 0 DEFINITION (OP CODE)
[0]
SYNOPSIS
a
1 0
1 0
I
~I
aI
°I1--,------1
BYTE 1 DEFINITION (OP CODE)
DESCRIPTION
[il o
1 0 I
aLi]
1
11I~
BYTE 1 DEFINITION
6
A6
I I I I I G
A5
A4
A3
A2
A1
ADDRESS LOW.
BYTE 2 DEFINITION (OP CODE)
1111
I alii
0i'-_[~
BYTE 2 DEFINITION (OP CODE)
S po I aI aI aI I~~--]
A10
PROCCODE
ADDRESS HI
P1-0
A10-A8
00
01
10
11
28/44
164
Master
Receiver
Echo Cancel
All
TS7532
APPENDIX A
nop - no operation is specified
rrr1 t - Read MAFE register RR1
INSTRUCTION TYPE
INSTRUCTION TYPE
operational control command
MAFE manipulation command
OPCODE
OPCODE
080000
000000
SYNOPSIS
SYNOPSIS
rrr1
nop
DESCRIPTION
DESCRIPTION
nop is used when communications with the V.32 Engine are required but no action is desired.
BYTE 0 DEFINITION (OP CODE)
rrr1 causes the V.32 Engine to read the 12 bit
contents of the MAFE chipset register RR1. The data is retumed in a standard three byte format. The
least significant data byte is returned in byte 1, followed by the most significant data byte. Byte 0 is the
standard response format (refer to appendix B) with
DAV1 and DAV2 bits setto 1. Consult the data sheet
of the TS68951 for the specifics of the returned data.
BYTE 0 DEFINITION (OP CODE)
1010101010101010110101010111010101
BYTE 1 DEFINITION (OP CODE)
I
0
I
0
I
0
I
0
I
0
I
0
BYTE 1 DEFINITION (OP CODE)
I
0
I
0
I'
I
0
I
.
0
0
I
I
0
I
0
I
0
BYTE 2 DEFINITION (OP CODE)
BYTE 2 DEFINITION (OP CODE)
1010101010101 0 1 0 1
191 0
I
.
0
I
0
I
0
I
0
I
I
0
I
0
I
0 10 1
29/44
165
TS7532
APPENDIX A
rrr2t - Read MAFE register RR2
rtra -force a retrain of the V.32 Engine
INSTRUCTION TYPE
INSTRUCTION TYPE
MAFE manipulation command
operational control command
OPCODE
OPCODE
090000
050000
SYNOPSIS
SYNOPSIS
rrr2
rtra
DESCRIPTION
DESCRIPTION
rrr2 causes the V.32 Engine to read the 12 bit
contents of the MAFE chipset register RR2. The data is returned in a standard three byte format. The
least significant data byte is returned in byte 1, followed by the most significant data byte. Byte 0 is the
standard response format (refer to appendix B) with
DAV1 and DAV2 bits set to 1. Consult the data sheet
of the TS68951 for the specifics of the retumed data.
rtra is used to force the V.32 Engine to initiate a retrain sequence on the channel.
BYTE 0 DEFINITION (OP CODE)
BYTE 0 DEFINITION (OP CODE)
1010101011101011110101010101110111
BYTE 1 DEFINITION (OP CODE)
0
0
BYTE 1 DEFINITION (OP CODE)
0----,----10----,----1---,-01------,-01----,01-----,01 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
, - - - - - I- " - - - I- - , - - - - I
BYTE 2 DEFINITION (OP CODE)
BYTE 2 DEFINITION (OP CODE)
1010101010101010110101010101010101
30/44
166
TS7532
APPENDIX A
setg nt - set global gain factor
sl nt - Disable tone generators
INSTRUCTION TYPE
operational control command
tone command
OPCODE
INSTRUCTION TYPE
02
OPCOOE
ODOOOO
SYNOPSIS
stegn gain value
SYNOPSIS
slnt
DESCRIPTION
DESCRIPTION
setgn is a command which used to scale the transmit samples. The 16 bit value provided is used as
the multiplicative constant to be multiplied with each
transmit sample.
slnt causes the V.32 Engine to disable the tone generators, thus stopping the tone output (i.e. send silence).
BYTE 0 DEFINITION (OP CODE)
BYTE 0 DEFINITION (OP CODE)
10101010101011101801010111110111
BYTE 1 DEFINITION
BYTE 1 DEFINITION
1 G7 1 G6 1 GS 1G4 1 G3 1G2 1G1 1GO 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
LOW BYTE OF GAIN VALUE.
BYTE 2 DEFINITION
!
BYTE 2 DEFINITION (OP CODE)
1G1S1 G141 G131 G121 G11 1G10 1 G9 1G8 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
HI BYTE OF GAIN VALUE.
31/44
-----------------------
167
TS7532
APPENDIX A
spac t - Store
Parameter And Count
spamt - Store Parameter in Addressea Memory
INSTRUCTION TYPE
INSTRUCTION TYPE
memory manipulation command
memory manipulation command
OPCODE
OPCODE
13
12
SYNOPSIS
SYNOPSIS
spac lo-byte hi-byte
spam lo-byte hi-byte
DESCRIPTION
DESCRIPTION
spac is a command which used to write an arbitrary 16 bit value into the writable memory location currently specified by the Memory Address Register.
The content of the Memory Address Register is incremented by 1 at the completion of command execution. See also WARP.
spam is a command which used to write an arbitrary 16 bit value into the writable memory location currently specified by the Memory Address Register.
See also WARP.
BYTE 0 DEFINITION (OP CODE)
BYTE 0 DEFINITION (OP CODE)
~]~~_11
10101 18 [YI olol1l olol
BYTE 1 DEFINITION
BYTE 1 DEFINITION
[~~]~~]~~~J[~4 r~;~~~J~~~~:I~J [~;~[~6-:r~~]~~~~~:E-~~
LOW BYTE OF DATA.
LOW BYTE OF DATA.
BYTE 2 DEFINITION
BYTE 2 DEFINITION
~~~I
~~~I~~~~1~1~_~2_'I-_O-_-11-_'E-0-1-~1-'---~9-__ -J"-~_-~-8J
0141~~12J~_11J_~10~~1~~]
HI BYTE OF DATA.
32/44
._---
168
HI BYTE OF DATA.
_
TS7532
APPENDIX A
tge n - Enable and disable tone
tone - Select and transmit tone (s)
generators
INSTRUCTION TYPE
tone control command
INSTRUCTION TYPE
tone select and command
OPCODE
OPCODE
00
OC
SYNOPSIS
tgen tg code
SYNOPSIS
tone tone code
DESCRIPTION
tgen causes the V.32 Engine to enable or disable
tone generator 1 and tone generator 2, according to
the parameter provided. Either tone generator 1 or
tone generator 2 can be scaled by the parameter
provided in byte 2. If neither is scaled and both tone
generators are enabled, tone 2 has a level 2 dB higher than tone 1. The user cannot scale both tone
generators. If both generators are selected to be
scaled, tone generator 1 has higher priority.
DESCRIPTION
tone causes the V.32 Engine to program the tone
generators forthe specified tone ortones. The tones
are defined by the tone code parameter passed in
the second byte of the command. See also tonetab
for the predefined single and double tones, and the
commands deft and tgen for user definable tones
and tone generator conirol.
BYTE 0 DEFINITION (OP CODE)
BYTE 0 DEFINITION (OP CODE)
I~o~Ia ~I 0~1
1
BYTE 1 DEFINITION (TONE CODE)
BYTE 1 DEFINITION (TONE CODE)
°---L--I
1
a I a
1
a I a
TG CODE
TGC2-1
00
01 t
10t
11
------,---I-----L1
1-------,01_11
ITGN21TGN11
TONE GEN 1
a
1
a
1
TONE GEN 2
disabled
enabled
disabled
enabled
1
a
1
a
1
0
1
disabled
disabled
enabled
enabled
a
1
a
1 T7
1
1 T6
1 0
1
a
1 0
1 T5
1
a
1
I
1
1 T4 1 T31 T2
1
a
1 T1
1
a
1
a
j
a
1
a I a
1
a
Tone Code
Tone Parameters
a
DTMF a (941 & 1336 Hz)
DTMF 1 (697 & 1209 Hz)
DTMF 2 (697 & 1336 Hz)
DTMF 3 (697 & 1477 Hz)
DTMF 4 (770 & 1209 Hz)
DTMF 5 (770 & 1336 Hz)
DTMF 6 (770 & 1477 Hz)
DTMF 7 (852 & 1209 Hz)
DTMF 8 (852 & 1336 Hz)
DTMF 9 (852 & 1477 Hz)
(697 & 1633 Hz)
(770 & 1633 Hz)
(852 & 1633 Hz)
(941 &1633Hz)
DTMF' (941 & 1209 Hz)
DTMF # (941 & 1477 Hz)
Answer tone (2100 Hz)
1
2
1
a I a
1
a
1
1 TO 1
BYTE 2 DEFINITION (OP CODE)
BYTE 2 DEFINITION (OP CODE)
1 0
a
3
4
5
6
7
8
9
A
B
C
D
E
F
10
1 0
1
33/44
169
TS7532
APPENDIX A
ufzec - Unfreeze the echo canceller
ufzeq - Unfreeze the equalizer adapta-
adaptation
tion
INSTRUCTION TYPE
INSTRUCTION TYPE
operational control command
operational control command
OPCODE
170000
OPCODE
1COOOO
SYPNOSIS
ufzec
SYPNOSIS
ufzeq
DESCRIPTION
Ufzec causes the V.32 Engine to enable the adaptation of the echo cance lIer.
Ufzeq causes the V.32 Engine to enable the adaptation of the equalizer.
BYTE 0 DEFINITION (OP CODE)
BYTE 0 DEFINITION (OP CODE)
0
0
0----,---11-----1--1---,--0
1-----L11_----'11-------,1
, - - - - - I--,--------I- - - , - - - I
BYTE 1 DEFINITION (OP CODE)
I
DESCRIPTION
10
I
0 10 11 1 1 11
I
0
I
~
BYTE 2 DEFINITION (OP CODE)
101010101010101011010101010101010J
BYTE 2 DEFINITION (OP CODE)
BYTE 3 DEFINITION
1 0 1 0 1 0 1 0 1 01 0 1 0 1 0 1 1 0 1 01 0 1 0 1 0
34/44
170
1
0 1 0 10 1
TS7532
APPENDIX A
warpt - Write Address & Return Para-
warpxt - Write Address & Return Pa-
meter
rameter Complex
INSTRUCTION TYPE
INSTRUCTION TYPE
memory manipulation command
memory manipulation command
OPCODE
10
OPCODE
SYNOPSIS
SYNOPSIS
warp address
warpx address
11
DESCRIPTION
DESCRIPTION
warp is a command which is used to write the Memory Address Register of the V.32 Engine. The V.32
Engine responds with the contents of the addressed
location. The data is returned in a standard three
byte transfer. The least significant data byte is returned in the byte 1, followed by the most significant
data byte. Byte 0 is the standard response format
(refer to appendix B) with DAV1 and DAV2 bits set
to 1.
warpx is a command which is used to write the Memory Address Register of the V.32 Engine. The V.32
Engine responds with the contents of the most significant bytes of the addressed location and the addressed location + 1. The data is retumed in astandard three byte transfer. Byte 0 is the standard response format (refer to appendix B) with DAV1 and
DAV2 bits set to 1. Byte 1 is used to return the 8
most significant bits contained in the addressed location. The 8 most significant bits of the addressed
location + 1 are returned in byte 2.
BYTE 0 DEFINITION (OP CODE)
BYTE 0 DEFINITION (OP CODE)
1,----0~I
a ---'----.1
a---1--11----,---1-----,---0
1--------La1-----,01-----,01 [0 1
BYTE 1 DEFINITION
a
1a 11 1a
1
I a I a I
BYTE 1 DEFINITION
1 A7 1 A6 1 A5 1 A4 1 A3 1 A2 1 A1 1AO 1
G
A6 1 AS 1 A4 1 A3 1A2 1 A1 1AO 1
LOW BYTE OF DATA.
LOW BYTE OF DATA.
BYTE 2 DEFINITION
BYTE 2 DEFINITION
P1 1 po 1 M1 1 MO 1A11 1A10 1 A9 1A8 1 1 P1 1 po 1M1 1MO 1A11 1A10 1 A9 1A8 1
PROCCODE
MEM CODE
P1-0
M1-0
00 Master
00 XRAM
10 Receiver
01 YRAM
01 Echo Canceller 10 EMEM
11 CROM
ADDRESS HI
A11·A8
35/44
-------------------------
171
TS7532
APPENDIX A
wtr1 t_ Write MAFE register TR1
wtr2t- Write MAFE register TR2
INSTRUCTION TYPE
MAFE manipulation command
INSTRUCTION TYPE
MAFE manipulation command
OPCODE
OPCODE
OA
08
SYNOPSIS
wtr1
wtr2
SYNOPSIS
DESCRIPTION
DESCRIPTION
wtr1 causes the V.32 Engine to take the two supplied data bytes and write them in sequence to the
MAFE chipset register TR1.
wtr2 causes the V.32 Engine to take the two supplied data bytes and write them in sequence to the
MAFE chipset register TR2.
BYTE 0 DEFINITION (OP CODE)
BYTE 0 DEFINITION (OP CODE)
1010101011ETYl~
[~TDloI01liI117J
BYTE 1 DEFINITION (DATA)
BYTE 1 DEFINITION (DATA)
I 03 I 02 I 01 I 00 I 0 I 0 I 0 I 0 I I 03 I 02] 01 I 00 I 0 I 0 IYI!l
BYTE 2 DEFINITION (DATA)
I D11 I 010 I 09 I 08 I 07 I 06 I 05 R
36/44
172
BYTE 2 DEFINITION (DATA)
I 011 I 010 I 09 I D8 I 07 I 06 I 05
8
TS7532
APPENDIX A
xm it - transmit data to other modem
j
I
xm itit-
transmit data to other modem
and initiate additional cycle
INSTRUCTION TYPE
data communications command
INSTRUCTION TYPE
data communications command
OPCODE
01
OPCODE
SYNOPSIS
xmitdata
SYNOPSIS
xmitdata
DESCRIPTION
xmit is used to command the V.32 Engine to send
data. The OP code for the xmit command is a single byte. The data bits to be transmitted are stored
in the second byte, where DO is the first bit to be
transmitted.
DESCRIPTION
xmit is used to command the V.32 Engine to send
data. The OP code for the xmit command is a single byte. The data bits to be transmitted are stored
in the second byte, where DO is the first bit to be
transmitted.
BYTE 0 DEFINITION (OP CODE)
BYTE 0 DEFINITION (OP CODE)
03
~I0 ~I
,--------I
0
~O1--,01_0
°-----L---I-0- - - L
I-
-,-------I
1 ]
I
0
I
0
I
0
I
0
BYTE 1 DEFINITION
BYTE 1 DEFINITION
00·07 DATA BITS
00-07 DATA BITS
BYTE 2 DEFINITION
BYTE 2 DEFINITION
I
0
I
0
I
1
37/44
173
TS7532
APPENDIX B
STATUS REPORTING DESCRIPTION
BYTE 0 DEFINITION
[i11
I 1
F10
------
FLAG CODE
F01-00
00
01
10
11
F11-10
00
01
10
11
---
F01
_ _ _L-_F_OO
DAV2
J_~~~_H
I
__
107
J
CALL
ESTAB
no tones
Band 1 detected
Band 2 detected
Both bands detected
DATA XFER
HANDSHAKE
OPERATIONS
OPERATIONS
line quality is good
line quality is good
line terrible (local retrain req.) line quality is poor
line terrible (local retrain req.)
time out
remote retrain sequence detected
line cleardown
reserved
Answer tone
AC detected
reserved
9600
4800
9600
2400
reserved
reserved
reserved
reserved
bps no trellis
bps
bps trellis
bps
DAV1
0
0
1
1
DAV2
0
1
0
1
DEFINITION
Data is in byte 1 and 2.
Data is in byte 1 and status word in byte 2.
No data bits and status word is in byte 2.
Answer to the last command is in bytes 1 and 2.
FLAG
H
107
BIT
0/1
0/1
DEFINITION
Handshake is not/is in progress
Set circuit 107 off/on
BYTE 1 DEFINITION
BYTE 1 DEFINITIONt
Bit
ST7
ST6
ST5
ST4
ST3
ST2
ST1
STO
38/44
174
Call Modem.
",
..
AC detected
AC-CA detected
CA-AC detected
S detected
S-S/detected
R1 detected
. R3 detected
E detected
Answer Modem
.. ..- --" .. _ . _ - - - - - - - - - - - - - - - ...
---,--.--------.--------~-
AA detected
AA-CC detected
Silence detected
S detected
S-S 1 detected
R2 detected
N/A
E detected
,
--------------------
TS7532
APPENDIX C
This appendix describes the interconnection between the different chips.
SYSTEM INTERFACE
Signal Name
ChiplPin
DOH .. D7H
TS75321127 .. 34
CSL
TS75321/21
Chip Select: connect to host processor.
RSL
TS75321/22
Register Select: connect to host processor.
DSL
TS75321/20
Data Strobe: connect to host.
RWL
TS75321/19
ReadlWrite : connect to host.
INTL
TS75321 124
Interrupt Request: connect to host processor
RSTL1
RSTL2
RSTLO
TS75321 123
TS75322/23
Reset: connect to host processor.
Reset
Reset
TS75320/23
Description
System Data Bus: connect to host processor.
CLOCK SIGNAL
Signal Name
ChiplPin
TxRCLK
TS68952/16
TS75321 126
Transmit baud clock.
TxCCLK
TS68952/24
TS75321 144
Transmit conversion clock.
Description
TS68950/19
TS68951 123
RxRCLK
TS68952/20
TS75321 143
Receive baud clock.
TS75322/44
RxCCLK
TS68952/21
TS75321 125
TS75322/43
TS68951 122
Receive conversion clock.
TxSCLK
TS68952/11
If not used must be grounded.
XTL1
TS68952/13
External crystal input: must be connected via a 5.76 MHz crystal
to XTL2.
XTL2
TS68952/14
External Crystal Input
CLK
TS68952/15
Main analog clock' this output, in accordance with the XTL 1/2
crystal, must be 1.4 MHz (+ - 7Hz).
TS68950/18
TS68951/21
25 MHz
TS75320/15
Main digital clock: connect to a 25 MHz oscillator.
TS75321/15
TS75322/15
TxCCLK
RxCCLK
TS68952/23
TS68952/22
Transmit bit clock.
Receive bit clock.
39/44
175
TS7532
APPENDIX C
ANALOG SIGNALS
Description
Signal Name
Chip/pin
ATO
TS68950/15
Analog Transmit Output: connect to OAA.
EEOT
TS68950/16
TS68951/11
Analog echo cancelling estimation.
local Echo Input: connect to OM.
lEI
TS68951/17
RAI
TS68951/16
Receive Analog Input: connect to OM.
RFO
TS68951/13
This pin must be connected throught a 1 J.lF nonpolarised capacitor
to AGC1 input.
AGC1
TS68951/12
AGC2
TS68951/19
Connect to the analog loop back signal (see schematic).
C01
TS68951/18
Connect to the analog ground through a 1 J.l F nonpolarised
capacitor
Caution: T The connection between EEO (TS68950/16) and EEl (TS68951/11) must be as close as possible to avoid parasitics on echo esti·
mate signal.
INTER DSP AND EXTERNAL MEMORY CONNECTION
Signal Name
Chip/Pin
000 .. 0015
TS75320/45 .. 48,1 .. 12
Description
Data Bus
RAMO/I00 .. 1015
108 .. 1015
TS75321/5 .. 12
TS75320/27 .. 34
Data and Address Buses
RAMO/AOO .. A07
TS68950/20 .. 24, 1.. 3
100.. 107
TS75321/45 .. 48, 1 . .4
TS75322/27 .. 34
Data and Address Buses
RAM2/AOO .. A07
209 .. 2015
TS75322/6 .. 12
TS68951/25 .. 28, 1 .. 3
TS68952/25 .. 28, 1 .. 3
Data Bus
RAM2/109 .. 1015
208
TS75322/5
Data Pin
TS68951 124
RAM2/108
2DO .. 2D7
TS75322/45 .. 48, 1 .. 4
Data Bus
RAM2/100 .. 107
1A11
TS75321 139
TS75320/21
TS75322/21
TS68950/7
Address Line
1Al0
TS75321/37
TS68950/6
Adress Line
lA9
TS75321 136
Address Line
TS68950/9
TS75320/22
Note:
40/44
176
RAMO Refer to DSPO 4Kx16 External memory.
RAM2 Refer to DSP2 2Kx16 External memory.
Where: 10
bidirectional data bus
AD
address line
WEl Write Enable (active low)
CEl Chip Select (active low)
TS7532
APPENDIX C
INTER DSP AND EXTERNAL MEMORY CONNECTION (continued)
Signal Name
ChiplPin
1A8
T875321 135
T868950/8
T875322/22
Address Line
1RWL
T875321118
T875320/19
T875322/19
T868950/5
Control Line
1D8L
T875321/17
T875320/20
T875322/20
T868950/4
Control Line
OA8 .. 0A11
T875320/35 .. 37,39
RAMO/AD8 .. AD11
Address Line
OD8L
T875320/17
RAMO/CEL
Control Line
ORWL
T875320/18
RAMO/WEL
Control Line
2A8 .. 2A11
T875322/35 .. 37,39
T868951/8,9,6,7
T868952/8,9,6,7
RAM2/A8 .. A10,CEL
Address Line
2D8L
T875322/17
T868951/4
T868952/4
RAM2/0EL
Control Line
2RWL
T875322/18
T868951/5
T868952/5
RAM2/WEL
Control Line
OIROL
T875320/24
T875321 142
8ynchro Line
21ROL
T875322/24
T875321/41
8ynchro Line
Note:
Description
RAMO Refer to D8PO 4Kx16 External memory.
RAM2 Refer to D8P2 2Kx16 External memory.
Where: 10
AD
WEL
CEL
OEL
bidirectional data bus
address line
Write Enable (active low)
Chip 8elect (active low)
Output Enable (active low)
41/44
177
TS7532
APPENDIX C
POWER SUPPLY AND MISCELLANEOUS
Signal Name
ChiplPin
+ 5VA
T868951 120
T868950/17
Positive Analog Power 8upply
- 5VA
T868951114
T868950/12
Negative Analog Power 8upply
AGND
T868950/13
T868951115
Analog Ground
VCC
T875320/38
T875321 138
T875322/38
T868952/17
Main Digital Power 8upply
DGND
T875320/13
T875321/13
T875322/13
T868950/10
T868951/10
T868952/12
Digital Ground Power 8upply
xtal
T875320/14
T875321/14
T875322/14
Not Connected (must be left open)
Clkout
T875320/16
T875321116
T875322/16
Not Connected (25 MHz/4)
42/44
178
Description
TO
T868952/10
Not Connected (must be left open)
AGND
T868950/14
Auxiliary Input
DGND
T875321/40
T875320/40 ..44
T875320/25 .. 26
T875322/40..42
T875322/25 .. 26
T868950/11
Not Used
TS7532
APPENDIX C
Figure 9 : Analog Path.
60011.
B
~NE
TS
68950
ATO
EEO
~
I
[j
s
68951
~~II
~
27pF
Rx level adlUS!
..LR!!:!A'-I_ _ _ _ _ _+-~Cl
Gr-
C
C)
:II
>
s::
TERMINAL
CLOCK
TxSCLK
,
DEX'
~
!~
~.
;g
",I:
uC
c:::=::= ~
DSP
ii
I I
r--~,..2£IAI
;-------,
n' '\../ r----1
'~V
r---'I.~tTT"'\../~
[:E
TS68930131
OR
ST18930131
I~CS1
----QRSO I
v.-LJ
s:
'"'"--i
~
~
~
'"
n
~~O
RS1
~,
I:
liAr!
AMPLIFIER
MASTER CLOCK ~
t
TS 7542
-I
en
-...I
en
'"
N
TS7542
PIN CONNECTIONS
PLCC44
DIP40
04
ClKINI 06
04
03
OGNO
03
01
NC
02
00
01
4 3
6 5
2 1 44 43 42 41 40
RIW
RSO
RS1
E
vv+
10
11
14
15
lAO
NC
TxSClK
XTAL1
37
36
XTAL2
35
34
12
13
RFO
39
38
33
32
00
TxSClK
CS1
TxCClK
RxClK
RxRClK
TxClK
RS1
E
31
RxCCLK
16
30
EXI
vv+
17
29
NC
RFO
18 19 20 21 22 23 24 25 26 27 28
ATO
RAI
AGC1
NC AGNO
V+
XTAl1
XTAL2
TxClK
TxRClK
TxRClK
TxCClK
RxClK
RxRClK
RxCClK
lAO
EXI
Oxl
ATO
RAI
v+
v-
AGC2
AGC1
C01
M88TS7542-02
AGNO
v+
M88TS7542-01
PIN DESCRIPTION
N°
Name
1-4
D4-D7
Bidirectional Data Bus
5
ClKINI
Clock Initialization Input. Must be tied to V+ during normal operation.
6
RJW
Description
ReadlWrite Selection Input. This input indicates whether the current bus
cycle is a read (high) or write (low) cycle.
7-8
CS1-CSO
Chip Select Inputs. The chip is selected when CSO = 0 and CS1 = 1.
9-10
RSO-RS1
Register Select Inputs. Select the register involved in a read or write
operation.
11
E
12
V-
Negative Supply Voltage. V - = - 5 V
13
V+
Positive Supply Voltage. V + = + 5 V
14
RFO
Receive Filter Analog Output. Designed to be connected to AGC1 input
through a 1j.lF non polarized capacitor.
15
LAO
Line Attenuator Output. Duplexer analog output useful for line monitoring
during call progress.
16
Dxl
Duplexer Input. Signal on that analog input will be subtracted from the
receive anti-aliasing filter output to implement duplexer function.
Enable Input. Enables selection inputs.
Active on a low level for read operation.
Active on a positive-going edge for write operation.
±5 %
±5 %
17
RAI
18
AGC2
This pin must be connected to the analog ground through a 1j.lF non
polarized capacitor, in order to cancel the offset voltage of the AGC
amplifier.
19
AGC1
Analog input of the AGC amplifier and of the carrier level detector.
Receive Analog Input. Analog input tied to the transmission line.
3/35
183
TS7542
PIN DESCRIPTION (continued)
20
CD1
This pin must be connected to the analog ground through a 111F non
polarized capacitor, in order to remove the offset voltage of the carrier
level detector amplifier.
21
V+
22
23
AGND
V-
24
V+
25
ATO
26
EXI
27
RxCCLK
Receive Conversion Clock Output
28
RxRCLK
Receive Baud Rate Clock Output
29
RxCLK
30
TxCCLK
Transmit Conversion Clock Output
Transmit Baud Rate Clock Output
Positive Power Supply Voltage
Analog Ground. All analog signals are referenced to this pin.
Negative Supply Voltage
Positive Supply Voltage
Analog Transmit Output. Capable of driving 1200 Q load with 5 V peak to
peak amplitude.
External Transmit Input. Can be programmed to be connected to the
transmit filter or to the transmit attenuator input.
Receive Bit Rate Clock Output
31
TxRCLK
32
TxCLK
Transmit Bit Rate Clock Output
33
XTAL2
Crystal Oscillator Output. Nominal Frequency
34
XTAL1
Crystal Oscillator or External Master Clock Input
35
TxSCLK
36-39
DO-D3
Bidirectional Data Bus
40
DGND
Digital Ground. All digital signals are referenced to this pin.
5.76 MHz.
Transmit Synchronization Clock Input. Can be connected to an external
terminal clock to phase lock the internal transmit clocks. When this pin is
tied to a permanent logical level the transmit DPLL free-runs or can be
phase locked on the receive clock system.
FUN~TIONAL DESCRIPTION
The TS7542 is generally used in conjunction with a
DSP to realize the "data-pump" function of a highspeed modem. The circuit communicates with the
DSP via an 8-bit bidirectional bus and mainly includes the following functions:
_ the transmit analog channel with the D/A
Converter. the transmit filter and the transmit
attenuator.
_ the receive analog channel with the local echo
subtractor, the receive filter, the AGC amplifier,
the AID converter and the carrier level detector.
_ the two independent transmit and receive clock
generators using Digital Phase Locked Loops
(DPLL).
_ the 15 registers used to store the 12-bit transmit and receive digital samples, digital information for the DSP like the clock and the carrier
level detector status, and the data needed to
control the programmable functions or to synchronize the DPLLS.
4/35
~
TRANSMIT CHANNEL
The transmit channel converts the digital transmit
signal coming from the DSP into the analog signal
to be transmitted on the phone line. It includes a
12 bit digital to analog converter (DAC) operating at
7200,8000 or 9600 samples per second according
to the supported standard and the signal processing
compromises made in the DSP. The maximum analog output signal amplitude is 5 V peak to peak, defined by the internal ± 2.5 V voltage reference. The
DAC is monotonic and provides a guaranteed integral linearity better than 9 bit.
The transmit filter is a 6 th order low-pass switched
capacitor filter (SCF) sampled at 288 kHz, whose
cut-off frequency is 3.2 kHz. As the Sin xix correction depends on the DAC sampling frequency, it has
not been included in the tansmit filter and must be
performed by the DSP. The transmit filter is followed
by a second order, continuous time low-pass filter
TS7542
that removes the residual high frequency parasitic
signals.
The transmit attenuator allows the transmit signal
gain to be programmed from 0 dB to - 22 dB with
2 dB steps. Infinite attenuation is also programmable. The output amplifier can directly drive a 1200 Q
load. For special applications, the EXI input can be
programmed to give access to the input of the transmit filter or to the input of the attenuator.
RECEIVE CHANNEL
The receive channel begins with a second order
continuous time anti- aliasing filter followed by a
subtractor used to implement the two-wire to fourwire conversion with few external components. The
receive signal is then directed to the receive filter input and also, after programmable attenuation, to the
LAO output for line monitoring purpose during call
progress. Attenuation can be 0 dB, 6 dB, 12 dB or
infinite.The receive switched capacitor bandpass filter is composed of three programmable sections:
A 5 th order low-pass section, a 4 th order optional
1800 Hz notch section and a 6 th order high-pass
section. It also includes an input pre-filtering gain
programmable from 0 dB to 9 dB with 3 dB steps.
This feature is useful to optimize the dynamic range
of the signal by setting the maximum receive level
value close to 5 V peak to peak. The transfer function of the receive low-pass and high-pass filter sections can be translated by changing their sampling
clock frequencies to support different communication standards. Ten modes are programmable to
comply with CCITT V.21 , V.22, V.22 bis, V.23, V.26,
V.27, V.29 or V.33 as well as BELL 103, 202 or
212A. The typical curves obtained are given in the
TRANSMISSION CHARACTERISTICS section of
the data sheet. The receive filter output is smoothed
in a continuous time low-pass filter and then directed to the automatic gain control (AGC) amplifier
programmable from 0 dB to 46.5 dB with 1.5 dB
steps. The same signal is also connected to the carrier level detector input. Three external capacitors
are needed to eliminate the offset voltage as indicated in Fig.1 . The residual DC level at the analog to
digital converter (ADC) input is kept low and independent of the selected gain.
The carrier level detector performs the comparison
between the full wave rectified receive signal and
programmable threshold voltage nominally equivalent to - 45.5 dBm, - 34.4 dBm or -28.6dBm with a
2.5 dB hysteresis. The binary result of the comparison can be read by the DSP. The nominal response
time of the carrier level detector to a signal settlement or removal is 1.78 ms. The receive signal delivered by the AGC amplifier is sampled and converted from analog to digital by a 12-bit monotonic AID
converter whose integral linearity is guaranteed better than 9 bit. The sampling frequency is the same
as that programmed for the transmit DAC i.e. 7200,
8000,or 9600 samples per second.
CLOCK GENERATION
The 5.76 MHz master clock is obtained from either
a crystal tied between XTAL 1 and XTAL2 pins or an
extemal generator connected to the XTAL 1 pin. In
the latter case the XTAL2 pin should be left open.
Figure 1 : AGC and Carrier Level Detector Amplifier Structure.
CARRIER
LEVEL
DECTECTOR
1uF
Rx
ANDRC
RFO-1
FILTERS
~GC-1---"---.JWVW~--
~D1
T
1UF
to AJD Converter
1
analog ground
~AGC2
T
1UF
M88TS7542·04
5/35
185
TS7542
To meet the CCITT recommandation, the frequency tolerance requirement of the master clock must
be better than ± 100 ppm. The different transmit (Tx)
and receive (Rx) clocks are derived from the master clock via two independent digital phase locked
loops (DPll).
TRANSMIT CLOCKS
As shown in Fig.2 the transmit DPll operates by
adding or subtracting pulses to a 2.88 MHz internal
clock at a rate of 600 Hz. Consequently the frequency capture range equals ± 600 Hz/2.88 MHz, i.e.
± 208 ppm, a value consistent with the worst case
synchronization of two independent signals having
± 100 ppm of frequency accuracy. When V.27
clocks are selected, the DPll up-dating rate is increased to 800 Hz which is a submultiple of the
1600 baud rate of that particular mode. In this case
the frequency capture range is ± 278 ppm.
The transmit DPll can be synchronized on an external terminal clock connected to the TxSClK input or on the receive bit clock R x ClK internally generated from the receive DPll. It can also free-run
without any phase shift.
The TS7542 delivers three synchronous transmit
clocks:
_ a bit clockT x ClK whose frequency equals the
bit rate of the MODEM
_ a baud clock T x RClK whose frequency equals
the baud rate of the MODEM
_ a conversion clock T x CClK that gives the
samplinfrequency of the transmit D/A converter
The frequencies of these three clocks are programmable to support the different MODEM modes.
Their duty cycle is exactly 1 : 2. These clocks are
available on three dedicated pins. Their status can
also be read by the DSP from an intemal register,
TCR. Resetting of all the transmit clock generator
counters on the next negative transition of T x SClK
or R x ClK can be controlled from the data bus.
RECEIVE CLOCKS
The receive DPll phase shifts are performed in two
ways:
_ a coarse phase lag is obtained by suppressing
several 5.76 MHz master clock pulses from the
input of the receive clock generator under the
control of the DSP. The number of suppressed
pulses is programmable from 20 to 4800 with a
step value of 20 or 300. That feature will be
used to quickly synchronize the receive DPll
on the recovered receive rate.
_ a fine phase lead or lag is obtained by adding
or suppressing two master clock pulses from
the receive clock generator input, like for the
transmit DPll. But in that case the shifts are
controlled by the DSP that also implements the
phase comparator of the phase locked loop.
The TS7542 delivers three receive clocks with the
same nominal frequency values as their transmit
cou nterparts :
_ a bit clock R x CClK
_ a baud clock R x RClK
_ a conversion clock R x CClK
The status of these clocks can also be read from an
internal register, RCR.
The receive and transmit clocks are plesiochronous.
INTERNAL REGISTERS
The 8-bit bidirectional data bus allows to access 15
internal registers as detailed in Fig.3. The data
transfers are controlled by the six following signals:
_ two chip select inputs CSO and CS1 that must
be put respectively to 0 and 1 to allow a data
transfer.
_ The read/write input R/VVthatdefines the transfer direction
_ Two register select input that address one out
of four registers for a read or a write operation.
Actually indirect addressing is used to extend
to eight the number of the control registers.
Figure 2 : DPll lead and lag.
INTERNAL
2.88 MHz CLOCK
DPLL OUTPUT
LEAD
LAG
M88TS68952·04
6/35
186
TS7542
_ The enable input E that strobes on its positive
going transition the data to be written, or that
enables on its low level state the output buffers
when a data is to be read from a register.
The timing diagram of the data transfers is given in
the TIMING SPECIFICATIONS section of the data
sheet.
The four registers only accessible in a write operation are:
TR1 a that stores the 8 most significant bit
(MSB) of the 12-bit transmit signal digital samples.
_ TR1 b that stores the 4 least significant bit (LSB)
of the transmit signal digital samples.
_ ARC that stores the 3-bit address of one out of
eight control registers.
_ The control register whose address is stored in
the ARC register. The content of ARC is automatically incremented after each access to a
control register. This allows cyclical access to
these registers.
The four registers only accessible in a read operation are:
_ RR1 a that stores the 8 MSB of the 12-bit receive signal digital samples
RR 1b that stores the 4 LSB of the 12-bit receive
signal digital samples
_ RCR that stores the receive clock and the carrier level detector status
_ TC R that stores the transm it clock status
Figure 3 : Internal Registers Configuration.
TS 7542
DIA
CONVERTER
Tx CLOCKS
~ ~
DSP
...•.••.•.•.••.•.••.•
CS1
AID
RSO
CONVERTER
CONTROL
REGISTERS
RS>
M88TS7542-05
7/35
187
TS7542
The addresses of the internal registers are given in
table 1. Table 2 shows the formats used for the digital signal samples stored in the TR1 alb registers,
the RR 1alb registers and for the status data stored
in the TCR and RCR registers. Table 3 summarizes
the address and data format of the 8 control registers whose function is detailed in the PROGRAMMABLE FUNCTIONS section.
Table 1.
R/W
RSO
RS1
AccessedRegister
0
0
0
TRlb
0
0
1
TRla
0
1
0
ARC
Comment
Write Only Registers
0
1
1
The Control Register Addressed by ARC
1
0
0
RRlb
1
0
1
RR1a
1
1
0
RCR
1
1
1
TCR
Read Only Registers
Table 2.
Register Conten( note 1)
Register
Name
07
06
TRla
Txll
TRlb
Tx3
RRla
Rxll
RRlb
Rx3
TCR
X
TxRCLK TxCCLK TxCLK
RCR
COL
RxRCLK RxCCLK RxCLK
x
Comment
05
04
03
02
01
00
Txl0
Tx9
Tx8
Tx7
Tx6
Tx5
Tx4
Tx2
Txl
TxO
X
X
X
X
Rxl0
Rx9
Rx8
Rx7
Rx6
Rx5
Rx4
Rx2
Rxl
RxO
0
0
0
0
X
X
X
X
X
X
X
X
COL = 1 if Rx signal is
greater than the
programmed level.
= Oon't care.
Notel:00 to 07 refer to the data bus pins and gives the bit position in the read or written data.
8/35
188
TS7542
Table 3.
Control
Register
Name
ARC Content
(address) (note 1)
Register Content (note 2)
Programmed
Function
07
06
05
07
06
05
04
03
02
01
DO
RCI
0
0
0
HB3
HB2
HBI
HR2
HRI
X
X
X
Bit/Baud Rate for Tx and
Rx Clocks
RC2
0
0
1
X
X
X
HS2
HSI
X
Conversion Frequency.
Tx Synchronization
Selection
RC3
0
1
0
RF3
RF2
RFI
REJ
RC4
0
1
1
ATT4 ATT3 ATT2 ATTI
RC5
1
0
0
RG5
RC6
1
0
1
RC7
1
1
0
SP5
SP4
RC8
1
1
1
MPE
SPR AVRE
RG4
RG3
CDG2 CDGI CDH
SP3
HTHR FCLK
RFG2 RFGl LAT2 LATI
Rx Filter and 1800Hz
Notch. LAO Attenuation
X
EM2
EMI
X
Tx Attenuation. EXI Input.
RG2
RGI
X
X
X
AGC Amplifier Gain
X
X
X
X
X
Carrier Level Detector
Gain and Hysteresis
SP2
SPI
X
X
X
RxDPLL Coarse Phase
Shift
VAL
X
X
X
X
TxDPLL Reset. Rx DPLL
Fine Phase Shifts.
x
~ Don't care value.
Nole 2 : DO to D7 refers to the data bus pins and gives the bit position in the foaded address or data.
9/35
189
TS7542
POWER-ON INITIALIZATION
Internal power-on circuitry (Fig.4) automatically resets the DPll and the clock generators counters,
and initializes the RC1 to RCS control registers. The
initial status of these registers are given in the PROGRAMMABLE FUNCTIONS section. The transmit
attenuator is initialized to an infinite attenuation in
order to avoid the transmission of indesirable signals on the phone line.
Access to the control registers is desabled during
power-on reset until the clock oscillator starting. The
reset time duration' can be increased by connecting
the ClKINI input to an external RC timer as indicated in Fig.4. That feature will prevent, in particular
applications, possible problems due to incontrolled
signals coming from the DSP during power-on. In
normal operation the ClKINI input can be used to
reset the DPll and Clock generator counters and
the RCS control register. When that pin as not used,
it must be tied to V+
Figure 4 : Power-on Initialization Circuitry.
5.76 MHz
D
XTALl
XTAL2
MASTER
CLOCK
v+
R
C
J
'
,,,
,,
Tx & Rx DPLL
& CLOCK GENERATORS
+2
,
'
General reset
~
,
;J;
o
i
D
Q
Set
R
RC8
TS 7542
CONTROL REGISTERS
M88TS7542·06
10/35
190
TS7542
PROGRESSION OF SIGNAL SAMPLES
Fig.5 shows the progression in the TS7542 of the
digital and analog signal samples. It appears that
the transfers of the data representing the transmit
and the receive signals have to be synchronized on
the TxCCLK or the RxCCLK conversion clock, respectively. This is the reason why the DSP needs to
receive these clock signals or to read their status
from the dedicated registers.
Figure 5 : Digital and Analog Samples Progress.
TxCCLK
DATA
BUS
(')
WRITE OPERATION
TxS4
Tx SAMPLE",TxS3
(INPUT)
TxS6
TxS5
TR1
REGISTER
TR
DIGITAL Tx SAMPLE
REGISTER
TxS2
TxS3
TxS4
TxS5
: CCONVER;ION
DIA
ANALOG Tx SAMPLE
CONVERTER
TxS2
OUTPUT
I
RxCCLK
TxS3
TxS4
TxS5
,----
AID
CONVERTER
RR
___-c-__
REGISTER
~X~D_IG_'T,AL-:-:-::-M-PL-E~'X~-_.__R-XS-2--X~_---,_R_X_S_3-~C
RR1
REGISTER
DATA
BUS
(')
(OUTPUT)
M88TS7542-07
Notes:
(')
Txi = ith analog or digital sample of the Tx signal.
Rxi = ith analog or digital sample of the Rx signal.
Data can be written (read) six master clock periods after the T x CCLK (R x CCLK) negative-jJoing transition respectively
11/35
191
TS7542
PROGRAMMABLE FUNCTIONS
Table 4 : Bit Clock Frequency Programming (Tx and Rx).
RC1 Register
PIO
TxCLK or RxCLK
Bit Clock Nominal
Frequency (Hz)
Communication
Standard
07
06
05
04
03
02
01
00
HB3
HB2
HB1
HR2
HR1
-
-
-
0
0
0
9600
V.29
0
0
1
4800
V.27
0
1
0
2400
V.22 bis, V.26
0
1
1
1200
V.22, BELL 212A
V.22 Fall-back
1
0
0
600
1
0
1
600
1
1
0
2400
V.22 bis, V.26
1
1
1
1200
V.22, BELL 212A
TxRCLK or RxBCLK
Baud Rate
Clock Nominal
Frequency(Hz)
Communication
Standard (note 3)
PIO . Power on status.
Table 5 : Baud Rate Clock Frequency Programming (Tx and Rx).
RC1 Register
07
06
05
04
03
02
01
00
HB3
HB2
HB1
HR2
HR1
-
-
-
0
0
2400
V.29, V.33
0
1
1600'
V.27'
1
0
1200
V.26
1
1
600
V.22, V.22 Bis,
BELL 212A
PIO
Note 3: The phase shift frequency of the transmit DPLL
600 Hz, excepted for (') 800 Hz.
IS
Table 6 : Conversion Clock Frequency Programming (Tx and Rx).
RC2 Register
TxCCLK or RxCCLK
Conversion
(sampling) Clock
Nominal
Frequency(Hz)
07
06
05
04
03
-
-
-
HS2
HS1
0
0
0
1
8000
1
0
7200
1
1
7200
PIO
02
01
HTHR FCLK
00
-
Communication
Standard
9600
V.27
Table 7 : Tx Synchronization Signal Programming.
RC2 Register
PIO
07
06
05
04
03
-
-
-
HS2
HS1
02
01
HTHR FCLK
00
-
0
0
RxCLK
1
0
TxSCLK (note 4)
X
1
Transmit DPLL free-runs
Note 4 : The Tx DPLL free runs if there is no transistion on this pin in that case.
X = Don't care value.
12/35
192
Selected Synchronisation Signal
TS7542
Table 8 : Tx Clock General Reset.
Rca Register(note 5)
07
06
05
04
03
02
01
00
MPE
SPR
AVRE
VAL
-
-
-
-
1
0
0
0
ResellingTransition
Next Negative-going Transition
of Synchronizing Signal
Note 5 : RCB register is cleared after the programmed control operation is completed and on power-on.
Table 9 : Rx Clock Phase Shift Programming.
Rca Register(note 5)
07
06
05
04
03
02
01
MPE
SPR
AVRE
VAL
-
-
-
Actionon RxOPLL
0
1
0
0
0
0
0
1
Phase Lag of Two 5.76 MHz Master Clock Periods
0
0
1
1
Phase Lead of Two 5.76 MHz Master Clock Periods
Note 5 : RCB register
IS
Phase Lag of Programmed Amplitude
cleared after the programmed control operation
IS
completed and on power-on.
Table 10 : Rx Clock Phase Shift Amplitude Programming.
RC7 Register
-
P/O
07
06
05
04
03
02
01
SP5
SP4
SP3
SP2
SP1
-
-
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
.1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Phase Shift in Oegrees
1200 Bauds'
1600 Bauds
1.5
3
4.5
6
7.5
9
10.5
12
13.5
15
16.5
18
19.5
21
22.5
24
22.5
45
67.5
90
112.5
135
157.5
180
202.5
225
247.5
270
292.5
315
337.5
360
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
30
60
90
120
150
180
210
240
270
300
330
360
Numberof Master
Clock Pulses
Suppressed
20
40
60
80
100
120
140
160
180
200
220
240
260
280
300
320
300
600
900
1200
1500
1800
2100
2400
2700
3000
3300
3600
3900
4200
4500
4800
(') 2400 bauds: multiply by two. 600 bauds: divide by two.
13/35
193
TS7542
Table 11 : Tx Attenuator Programming.
RC4 Register
07
06
05
04
ATT4 ATT3 ATT2 ATTl
P/O
03
02
01
DO
-
EM2
EMl
-
Attenuation (dB)
0
0
0
0
0
0
0
0
1
2
0
0
1
0
4
0
0
1
1
6
0
1
0
0
8
0
1
0
1
10
0
1
1
0
12
0
1
1
1
14
1
0
0
0
16
1
0
0
1
18
1
0
1
0
20
1
0
1
1
22
1
1
X
X
Infinite
x = Don·! care value.
Table 12 : EXI and AGel Inputs Programming.
RC4 Register
07
06
05
04
ATT4 ATT3 ATT2 ATT1
P/O
14/35
194
03
-
02
01
EM2 EMl
DO
EXI Input Status
AGel Input Status
Tied to AGe Amplifier Input
-
0
0
Disabled
0
1
Tied to Tx Filter Input
1
0
Tied to Tx Attenuator Input
1
1
Disabled
Tied to AIDC Input
TS7542
Table 13 : Rx Filter Programming.
RC3 Register
Sampling (Fs) and Cut-off (Fc)
Frequencies (note 6)
Communication
Standard
See
Figure W
1820
V.22, V.22 bis, BELL
212A
and BELL 103 High
Channels
7
115.2
1456
V.21 High Channel
8
82.3
1040
V.27 ter 2400 bps
9
3200
72
910
V.27 ter 4800 bps,
V.23, V.26
and BELL 202
10
144
1600
64
809
V.22, V.22 bis, ,BELL
212A
and BELL 103 Low
Channels
11
1
144
1600
64
809
V.22, V.22 bis Low
Channels
with 1800 Hz Tone
Rejection
12
115.2
1280
64
809
V.21 Low Channel
13
288
3200
36
455
V.29, V.33
14
1
X
X
X
288
3200
18
228
Full Channel
Bandwidth
15
1
X
48
533
27.4
347
75 bps Back
Channel
16
07
06
05
04
RF3
RF2
RF1
RFO
Fs(kHz)
Fc(Hz)
Fs(kHz)
Fc(Hz)
0
0
0
X
288
3200
144
0
0
1
2133
1
0
288
3200
0
1
1
X
X
X
192
0
288
1
0
0
0
1
0
0
1
0
1
1
1
0
1
1
1
1
Pia
Low Pass Section High Pass Section
n
n In this mode the 1800 Hz notch filter section is enabled.
X = Oon't care values. The notch section is disabled in all these cases.
Note 6 : The sampling clocks used by the Rx switched capacitor filters are straightly derived from the crystal oscillator.
The Tx switched capacitor filter is driven from the Tx OPLL.
Table 14.
RC3 Register
07
06
05
RF3
RF2
FR1
04
03
02
01
DO
Rx Filter Gain (dB)
RFO RFG2 RFG1 LAT2 LAT1
Pia
0
0
0
0
1
3
1
0
6
1
1
9
Table 15 : Line Output Attenuator Programming.
RC3 Register
Pia
07
06
05
RF3
RF2
RF1
04
03
02
01
DO
LAO Output Attenuation (dB)
RFO RFG2 RFG1 LAT2 LAT1
.0
0
Infinite
0
1
0
1
0
6
1
1
12
15/35
195
TS7542
Table 16 : Carrier Level Detector Programming.
RC6 Register
07
06
COG2 COG1
PIO
05
04
03
02
01
00
COH
-
-
-
-
-
Carrier Level Oetector
Threshold(dBm) (note 7)
0
0
0
- 29.85
0
0
1
- 27.35
0
1
0
- 36.65
0
1
1
- 34.15
1
0
0
- 46.75
1
0
1
- 44.25
1
1
0
- 46.75
1
1
1
- 44.25
Note 7 : These values applies when the total Rx gain from the phone line to the Rx filter output is 0 dB.
16/35
196
TS7542
Table 17 : AGe Amplifier Gain Programming.
RC5 Register
P/O
AGC AmplifierGain (dB)
07
06
05
04
03
RG5
RG4
RG3
RG2
RG1
AGC1 Input
AGC21nput
0
0
0
0
0
0
-=
0
0
0
0
1
-=
0
0
0
1
0
3
- =
0
0
0
1
1
4.5
- =
0
0
1
0
0
6
- =
0
0
1
0
1
7.5
- =
0
0
1
1
0
9
- =
0
0
1
1
1
10.5
1.5
- =
0
1
0
0
0
12
-=
0
1
0
0
1
13.5
-=
0
1
0
1
0
15
-=
0
1
0
1
1
16.5
- =
0
1
1
0
0
18
- =
0
1
1
0
1
19.5
- =
0
1
1
1
0
21
- =
0
1
1
1
1
22.5
- =
1
0
0
0
0
24
- 14.5
1
0
0
0
1
25.5
- 7.7
1
0
0
1
0
27
-3.4
1
0
0
1
1
28.5
0
1
0
1
0
0
30
2.7
1
0
1
0
1
31.5
5.2
1
0
1
1
0
33
7.4
1
0
1
1
1
34.5
9.5
1
1
0
0
0
36
11.4
1
1
0
0
1
37.5
13.3
1
1
0
1
0
39
15.1
1
1
0
1
1
40.5
16.8
1
1
1
0
0
42
18.5
1
1
1
0
1
43.5
20.2
1
1
1
1
0
45
21.8
1
1
1
1
1
46.5
17/35
197
TS7542
ELECTRICAL SPECIFICATIONS
Unless otherwise noted, electrical characteristics are specified over the operating range. Typical values are
given for V+ = + 5 V, V- = - 5 V and tamb = 25 'C.
ABSOLUTE MAXIMUM RATINGS
Symbol
V,
I,
Value
Unit
DGND Digital Ground to AGND Analog Ground
Parameter
- 0.3 to + 0.3
V
V+ Supply Voltage to DGND or AGND Ground
- 0.3 to + 7
V
V- Supply Voltage to DGND or AGND Ground
- 7 to + 0.3
V
DGND - 0.3 to V+ + 0.3
V
- 20 to + 20
mA
Voltage at any Digital Input or Output
Digital Output Current
Vin
Voltage at any Input or Output
lout
Analog Output Current
Ptot
Power Dissipation
tamb
Operating Temperature Range
t stot
Storage Temperature Range
tsold
Pin Temperature (soldering 10 s.)
V- - 0.3 to V+ -I- 0.3
V
- 10 to + 10
mA
500
mW
o to
+ 70
'C
- 65 to + 150
'C
+ 260
'C
POWER SUPPLIES
DGND = AGND = 0 V
Symbol
Max.
Unit
V+
Positive Power Supply
Parameter
Min.
4.75
Typ.
5.25
V
V-
Negative Power Supply
- 5.25
- 4.75
V
1+
Positive Supply Current (receive signal level 0 dBm)
35
mA
1-
Negative Supply Current (receive Signal level 0 dBm)
- 35
mA
DIGITAL INTERFACE
Control Inputs, Data Bus and Clock Outputs. Voltages referenced to DGND = 0 V
Symbol
Parameter
Min.
V,L
Low Level Input Voltage
V,H
High Level Input Voltage
I'L
Low Level Input Current
DGND < V, < 0.8 V
-10
I'H
High Level Input Current
2.2 V < V, < V+
-10
VOL
VOH
loz
Typ.
Max.
Unit
0.8
V
10
j.tA
10
IlA
0.4
V
2.2
= 2.5 mA)
High Level Output Voltage (loH = - 2.5 mA)
Low Level Output Voltage (lOL
High In:!Pedance Output Current
(when E is high and DGND < Va < V+)
V
2.4
- 50
V
50
j.tA
1.5
V
Crystal Oscillator Interface (XTAL 1 input)
V,L
Low Level Input Voltage
V'H
High Level Input Voltage
I'L
Low Level Input current
DGND s; V, S;V,Lmax
I'H
High Level Input Current
V,Hmin s; V, s; V+
18/35
198
3.5
V
-15
j.tA
15
IlA
TS7542
ELECTRICAL SPECIFICATIONS (continued)
ANALOG INTERFACE All voltages referenced to AGND = 0 V
Parameter
Symbol
Min.
Input Voltage EXI. Dxl, RAI
Vin
Input Current EXI, Dxl, RAI (- 2.5 V < V in < 2.5 V)
lin
V
1
~
kQ
Input Resistance AGC1, AGC2
1.5
Input Resistance CD1
0.7
RL = 1 kQ, CL = 50 pF
Rout
Output Resistance
ATO
LAO
RFO
RL
Load Resistance ATO, RFO
CL
Load Capacitance ATO, RFO
RL
Load Resistance LAO
CL
Load Capacitance LAO
Unit
- 1
Rin
Output Voltage ATO, LAO, RFO
Max.
2.5
Rin
Vout
Typ.
- 2.5
kQ
- 2.5
2.5
V
4
50
15
Q
kQ
1
50
10
pF
kQ
20
pF
Max.
Unit
TIMING SPECIFICATIONS
TIMING SPECIFICATIONS Clock Timing Characteristics (XTAL 1 input)
Symbol
Min.
Parameter
Master Clock Period
PC
Typ.
173.6
tWCL
Master Clock Width Low Level
50
tWCH
Master Clock Width High Level
50
ns
ns
ns
tRC
Master Clock Rise Time
50
ns
tFC
Master Clock Fall Time
50
ns
tDC
Clock Output Delay Time
CL = 50 pF
500
ns
tTC
Clock Output Transition Time
CL = 50 pF
100
ns
PC
tWCH
MASTER CLOCK
INPUT
XTAL 1
1.5 V
tWCL
3.5 V
t RC-'--r-
II
\
/
t DC
t FC
\
II
2.2V
CLOCK OUTPUTS
(6 CLOCKS)
I
X1\
O.B
v
M88TS7542-0B
19/35
199
TS7542
ELECTRICAL SPECIFICATIONS (continued)
BUS TIMING CHARACTERISTICS (see foot notes 1 and 2 on timing diagrams)
Symbol
Min.
Parameter
Typ.
Max.
Unit
tCYC
Cycle Time
(1 )
320
ns
tWEL
Pulse Width E Low Level
(2)
180
ns
tWEH
Pulse Width E High Level
(3)
100
t f • tg
Clock Rise and Fall Time
(4)
tHCE
Control Signal Hold Time
(5)
10
ns
tSCE
Control Signal Set-up Time
(6)
40
ns
tSOI
Input Data Set-up Time
(7)
120
ns
tHOI
Input Data Hold Time
(8)
10
tsoo
Output Data Set-up Time (1 TTL load and CL
td,
= 50 pF)
Output High Impedance Delay Time
(1 TTL load and CL = 50 pF)
ns
20
ns
ns
(9)
150
ns
(10)
80
ns
WRITE OPERATION
_Gl
CD
\
(6)
CSO-CSl
RSO-RSl
HIW
0
G
~~
(i)
DO-D7
~
V
0
K
®
I
\
M88TS68950-06
Note 1 : Voltage levels shown are VIL < 0.4 V, VIH > 2.4 V, unless otherwise specified.
Note 2 : Measurement points shown are 0.8 V and 2.2 V, unless otherwise specified.
20/35
200
TS7542
READ OPERATION
(i)
CD
G)
/
\
RIW
CV
0
@
CSO-CSl
KSU-KSl
...
~~
®
K
@
i--=--
@
I
\
00·-07
M88TS68951-05
Note1: Voltage levels shown are VIL < 0.4 V, VIH > 2.4 V, unless otherwise specified.
Note 2 : Measurement points shown are 0.8 V and 2.2 V, unless otherwise specified.
TRANSMISSION CHARACTERISTICS
PERFORMANCES OF THE WHOLE TRANSMISSION CHAIN (Input TR1, Output ATO)
Symbol
Gabs
N
Parameter
ATO Absolute Gain at 1 kHz
Min,
Typ,
Max,
- 0.5
0
0.5
dB
100
IlV
ATO Psophometric Noise
Unit
PSRW
ATO Positive Power Supply Rejection Ratio
Vac ~ 200 mVpp
f ~ 1 kHz
40
dB
PSRR-
ATO Negative Power Supply Rejection Ratio
Vac ~ 200 mVpp
f ~ 1 kHz
40
dB
THD
Total Harmonic Distortion
- 54
dB
Max,
Unit
DAC TRANSFER CHARACTERISTICS
Symbol
Parameter
Min,
Typ,
Converter Resolution
12
Nominal Output Peak to Peak Amplitude
5,0
V
Least Significant Bit Amplitude
1.2
mV
Eil
Integral Linearity Error Relative to Best Fit Line
±4
Edl
Differential Linearity Error
Vout(max)
LSB
Bit
±8
LSB
± 0,7
LSB
21/35
201
TS7542
TRANSMISSION CHARACTERISTICS
TRANSMIT FILTER TRANSFER CHARACTERISTICS (input EXI, output ATO)
(see figure 6)
Symbol
Parameter
Gabs
Absolute Gain at 1 kHz
Grel
Gain Relative to Gabs without Sin xix Correction 01 DAC
Sampling
Below 31 00 Hz
3200 Hz
4000 Hz
5000 Hz to 12000 Hz
12000 Hz and Above
Min.
Typ.
Max.
Unit
- 0.3
0
0.3
dB
0.3
dB
dB
dB
dB
dB
- 0.4
-3
- 36
- 46
- 50
T gp
Group Propagation Delay Time (I = 1800 Hz)
250
T gpd
Group Propagation Delay Time Distortion
(600 Hz < 1 < 3000 Hz)
430
~s
Tx ATTENUATOR TRANSFER CHARACTERISTICS
Symbol
Parameter
Min.
Typ.
Max.
Unit
ATabs
Absolute Attenuation at 0 dB Nominal Value
- 0.3
0
0.3
dB
ATrel
Attenuation Relative to Nominal Value
- 0.5
0.5
dB
AT max
Maximum Attenuation
dB
50
RECEPTION CHARACTERISTICS
PERFORMANCE OF THE WHOLE RECEPTION CHAIN (input RAI or Oxl, output RR1)
Symbol
Parameter
Min.
Typ.
Max.
Unit
- 0.5
0
1.5
dB
Gabs
Absolute Gain
(AGC gain = 0 dB, RxCCLK = 9600 Hz. Vin = 775 mVrms,
1 = 2000 Hz)
HDT
Total Harmonic Distortion
(AGC gain = 0 dB, RxCCLK = 9600 Hz, Vin = 775 mVrms,
1 = 2000 Hz, programmed band = 475 Hz - 3200 Hz)
- 54
dB
Equivalent RMS Noise (see note)
(AGC gain = 0 dB, RAI, Dxl tied to AGND, Irequency
band = 228 Hz - 3200 Hz)
800
~Vrms
N
Note. NOise depends on AGe gain value.
22/35
202
TS7542
RECEPTION CHARACTERISTICS (continued)
RECEIVE BAND-PASS FILTER AND REJECTION FILTER (input RAI or Dxl, output RFO)
The characteristics and specifications (templates) of the ten programmable transfer functions are given on
figures 7 to 16.
RECEIVE FILTER INPUT GAIN CHARACTERISTICS
Parameter
Relative Gain to Programmed Gain
LINE MONITORING ATTENUATOR CHARACTERISTICS
Symbol
Parameter
Min.
Typ.
Max.
Unit
ATabs
Absolute Attenuation at 0 dB Nominal Value
- 0.3
0
0.3
dB
AT rel
Attenuation Relative to Nominal Value (2 dB s; AT s; 22 dB)
- 0.5
AT max
Maximum Attenuation (AT = =)
0.5
dB
dB
50
AGC AMPLIFIER AND NO CONVERTER (input AGC1, output RR1)
Symbol
Grel
Vas
Parameter
Relative Gain to Programmed Gain
o dB s; AGC s; 24 dB
25.5 s; AGC s; 46.5 dB
Offset Voltage
Min.
Typ.
Max.
Unit
- 0.5
- 1
0.5
1
dB
dB
- 70
70
LSB
Max.
Unit
0.5
1
0.5
1
dB
dB
2
3
dB
- 1
-2
-3
1
2
3
mV
mV
mV
1
3
ms
Max.
Unit
CARRIER LEVEL DETECTOR (input AGC1, output CDR)
Symbol
Trel
Parameter
Relative Threshold to Programmed Value T
- 36.65 < T s; - 27.35 dBm
- 46.75 s; T s; - 36.65 dBm
Hyst
Hysteresis
Vas
Input Offset Voltage
1st Threshold Pair (see table 16 and fig. 2)
2nd Threshold Pair
3rd Threshold Pair
T dd
Detection Delay Time
mVrms Transition or 775 mVrms to 0 mVrms
Transition
o mVrms to 775
Min.
Typ.
PERFORMANCE OF THE NO CONVERTER (input AGC1, output RR1)
Symbol
Parameter
Min.
Typ.
Input Voltage (peak to peak)
5
V
Resh
AID Converter Resolution
12
Bit
LSB
Analog Increment
1.2
Integral Linearity Error Relative to Best Fit Line
±4
±8
LSB
Vin(max)
Eil
Edl
Differential Linearity Error
Vas
Offset Voltage
- 100
mV
± 0.7
LSB
100
LSB
23/35
203
TS7542
Figure 6 : Tx Filter Frequency Response.
REF LEVEL
O.OOOdS
/OIV
lO.OOOdS
~~~ ~
. / 1/--:::::
~
-::: ~
./
/
~
~
~~
~~
./
\
MARKER 1 OOO.OOOHz
MAG (UDF)
-0. l50dS
~ 1/
~ ~~
\ ~ ~ t/
~
~ V/ ~ :/'/ ~
~ V~ V~ V~ V/
/
./
/
"
./
f
/
V
\(
~
~
~
~
START O.OOOHz
AMPTO 50. 1 U~mV
REF LEVEL
-0. 150dB
400.00jSEC
\
STOP 10 OOO.OOOHz
/OIV
MARKER 1 OOO.OOOHz
1.000dB
MAG (UDF)
-0. 157dB
100.00jSEC MARKER 1 OOO.OOOHz
DELAY (A/R) 205.BOjSEC
»
/ / ~ [/j: ~ ~ 0
~ "'//
/ / V/ V/ / / / /V/ / / ",,>. ~V/
L0
v/ / / / / / /v/ / / V
I~ 0 ~ ~ '/:[/; ~ ~
/
"/
" t::1
/
~
V
START O.OOOHz
AMPTD 50. 111ii1mV
~
0
..,,- ~-:: ~
./
"
/
,/
~
~
\
\
\
\'...
~
STOP 4 OOO.OOOHz
DELAY APER 20.00Hz
M88TS7542-09
24/35
204
TS7542
Figure 7 : Rx Filter Frequency Response for V.22, V.22bis, BELL212A and BELL 103 High Channels
(see table 13).
i
I
REF LEVEL
O.OOOdB
~
/;
I~
i~
I~
/DIV
lO.OOOdB
MARKER 2 400.000Hz
MAG (A/R)
O.117dB
/;
'/;
~ 1\
I~ \
I
»
~
~
.~L
~v
~v
\
\f\
U
" '\
\
~
/':
~
V./ V_
\ / / '"/ /V / / /
\
~
/ ~
"-
V
~
~
START O.OOOHz
AMPTD 199.5:3mV
REF LEVEL
O.129dB
1. 1:350mSEC
./
~
'\.
"
STOP 10 OOO.OOOHz
/DIV
1.000d8
lOO.OO~EC
1// y~ V/ / /
MARKER 2400.000Hz
MAG (A/R)
O.1:38dB
MARKER 2 400.000Hz
DELAV(A/R)
675.20~EC
V/ y/ / /V/ V/ :/'"
. / . / 1/./1 . / . / . / . / . / . / . / . / . / . / . / . / . / . / . /
./ . / . / ././ ././ ././ ./
I
~
Y
L l2t
i VV t/\
v/
/ / 1//
V
V
l~
~
V [/'
V
V
/
/'
r;
V
r::: \
~~
\
~~~ \
I
V
I~;
"\
-, ,
START 1 500.000Hz
AMPTD lOO.OOmV
'~
r::
~~
~~
.,,/' ~ ~ ~
STOP :3 500.000Hz
II
\
\
\
M88TS7542·10
25/35
205
TS7542
Figure 8 : Rx Filter Frequency Response for V,21 High Channel (see table 13),
REF LEVEL
O.OOOdB
/DIV
10.000dB
~ ~
~
,
~'
\
~ I~
1/
~ ./
/
~ ./
~ ~
lLL
\
~
,-;
~,' ~i
MARKER 1 BOO.OOOHz
MAGCA/R)
0.079dB
\
~
~
~
\
\
\ :/;1/--,",", ~ V./ V/ y/
\ / /V / V/ V/ V/ / /
It'···"
-j,
-j,
!
I
\.
---
l~
'IIY
'/
STOP 10 OOO.OOOHz
START O.OOOHz
AMPTD 199.53mV
/DIV
1.000dB
REF LEVEL
0.100dB
1.6000mSEC
lOO.OO~EC
0 V2 ~ ~ 0
MARKER 1 aOO.OOOHz
MAGCA/R)
O.105dB
MARKER 1 aOO.OOOHz
1.1l09mSEC
DELAYCA/R)
~0 ~~~
V / V / '/L / / / , / / / / / / / / / / /
II
I
~
""
i\
~~~~~
"'
.
\
~
~
.I / ~ ~
~ ~V \
~v
J I C~
r
t:: /;
~
~
/
\
/
/'
/
;'
/'
;'
I
I
\
"
VV ...
~~
START 1 300.000Hz
AMPTD 100.00mV
/
"" ~
~"
..Jj;J
v~
~ ~~
~
\
\
STOP 2 300.000Hz
M88TS7542-11
26/35
206
TS7542
Figure 9: Rx Filter Frequency Response for V.27ter 2400bps (see table 13).
REF LEVEL
O.OOOdS
/DIV
lO.OOOdS
MARKER 2 lDO.OOOHz
MAGCA/R)
o.seSdS
~
~ ~ ~ 1\
~ ~ '// \
~ ~~
~ ~~
:2 ~ ~
[L..
"-\
_\
~// // //
\ ////////
~~
~~
\
~~
~~
~~
/v
/ ~
V
,
START O.OOOHz
AMPTD 199.5SmV
REF LEVEL
o.seOdS
970.00fSEC
'//
'//
'//
~
""" '-
STOP 10 OOO.OOOHz
/DIV
MARKER 2 100.000Hz
1.000dS
MAGCA/R)
O.seldS
lOD.OOfSEC MARKER 2 100.000Hz
DELAYCA/R) 497.19fSEC
/
// //
/~
// // // // //
L/ / / / / / / /
..
----.
-
~
//////// //
v~ ; / ~ ~ ~ '/:
~
/
~
t/:::'r\
~V
START 800.0ODHz
AMPTD 100.00mV
'\.
~
~\
\
~ ~\
/~
/' ~ \
;, ~ \
k ~~ \
,,~
(~
»
---.
"""STOP
. / V~
'/ \\
S 8OD.DOOHz
M88TS7542·12
27/35
207
TS7542
Figure 10: Rx Filter Frequency Response for V.27ter 4800bps, V.23, V.26 and BELL202 (see table 13).
REF LEVEL
O.OOOdB
/DIV
10.000dB
~ ~h
r\.
MARKER 2 lDO.OOOHz
MAGCA/R)
0.S09dB
~~
~ [:%:: ~ \
1,\
~ ~~
\
~ ~~
t/ ~ ~
- ~~
\ru ~ ~
~~
,
~~
~~
V
/' V
/DIV
1.COOdB.
100.00~C
t:J ~ V
",/ V
",
~
~
~ :// / / / /
\ \ V/ V/ / / / /
1\ /' ~
\f,
~
'\1
STOP 10 OOO.OOOHz
START O.OOOHz
AMPTD 199.S3mV
REF LEVEL
O.4BOdB
9S0.00,.,sEC
0/
MARKER 2 100.000Hz
MAGCA/R)
0.49SdB
MARKER 2 100.000Hz
DELAYCA/R) 471.00,.,sEC
~~~ ~ ~ ~ ~
/ L L / ././ / . /
---..
,....Y r-
~V
~
~ 1~ :-.\
/ / ./ ./ V / / / / /
V/ V/ V / //, :/;
~
./
,\
\,
,
~ ~\
/./~
'"~ t/
~ .\
/5- :::\
£, C/ '\ \
// "- .....
, / ""--: ~ I~
~~
V
START eOO.OOOHz
STOP 3 eOO.OOOHz
./
/
AMPTD lOO.OOmV
M88TS7542·13
28/35
208
TS7542
Figure 11 : Rx Filter Frequency Response for V.22, V.22bis, BELL212A and BELL 103 Low Channel (see
table 13).
REF LEVEL
O.OOOdS
~
~
~
~
r
L
I~
/OIV
10.000dS
MARKER 1 200.000Hz
MAGCA/R)
0.220dS
~v
VI\
V\
:/ \
~ Vv
~ Vv
/. \ ~~
/. \ V/
~ ~/V/ V/ ~/ ~/ / /
V/ V / V/ V/ V/ V/
/
/
r
~
~
'\ ~
/.
V
"
~
START O.OOOHz
AMPTD 199.53mV
STOP 10 OOO.OOOHz
/OIV
1. OOOdS.
REF LEVEL
0.2S0dB
1.5BOOmSEC
100.00~EC
MARKER 1 200.000Hz
MAG CA/R)
o. 2S2dB
MARKER 1 200.000Hz
1 OB05mSEC
OELAYCA/R)
.
~~~
~ ~ ~V; 0 ~ Z
V/ / / / / / / / / / / / / LL
/'/' /'
1\
,,-- \"
F
LA" /
/ / V/ V/ V/ / /
II /' ty V-0 V/ V/ V0 ~
,/
/'
,/
~~
~ 1/
~
,
,-
\
/
'//v
~
./
v\
V"
/
1\
,-
I,.
"\,
.~
0
0
'\
\
~
» \\
/~
~ \
~ ~
Ii 0
I\J.
J
V:
,-~
STOP 1 700.000Hz
DELAY APER 5.000Hz
START 700.000Hz
AMPTO lOO.OOmV
~
1It..""f1
SCS·ntOMSON
\.
M88TS7542·14
29/35
~~©IiI@~~~IiI@Il~©$
209
TS7542
Figure 12: Rx Filter Frequency Response for V.22 and V.22bis Low Channels with 1800Hz Tone Rejection (see table 13).
REF LEVEL
O.OOOdS
/DIV
10. DODdS
r;: :2
r::
~
~
~
~.
1\
'/ \
c:: '/
-
r~
'/
'/
\
MARKER 1 200.000Hz
MAGCA/R)
0.42SdS
~I'
~
~ 1..~v
~ ~/ V/ "/'> / /V/ /./
\ / / / . / V./ V./ V./ V./ V/
,
r
'/
'/
1\..
V
~
STOP 10 OOO.OOOHz
START O.OOOHz
AMPTD 199.SSmV
/DIV
1. DODdS
REF LEVEL
0.430dS
1. 6250mSEC
, --
lJ'
100.00~EC
MARKER 1 200.000Hz
MAGCA/R)
0.4S9dB
MARKER 1 200.000Hz
DELAYCA/R)
1 lBB7mSEC
.
vr.::::: :/; ~ '// ~ ~ ~ ~ ~ ~
--
,.L ~~
F-
I
-
V
V
~
--.-
/ /V / ' / / / / / /
V
//,V/ , / / /~
:\
./
./
./
~ ~\
v:::: r;.
~~
~ /'
V
/
START 700. DOOHz
AMPTD 100.00mV
r-...
~
/
~ •.&11 l~
, ~ I/; \
.~
I~ -:0
t
~
\
\,
"'I,
~ ~
~ l...
.sf
.-
-:0
~
STOP 1 700.000Hz
M88TS7542-15
30135
210
TS7542
Figure 12 (continued) : Rx Filter Frequency Response for V.22 and V.22bis Low Channels with 1800Hz
Tone Rejection (see table 13).
REF LEVEL
-30.000dB
/OIV
2.000dB
\
\
\
\
MARKER 1 eOO.OOOHz
MAG (A/R)
-31. 540dB
~ y;
~~
/
V
/
~~
~~
I
/
/
!Ita
II
f\"
II
\
START 1 750.000Hz
AMPTO 199.53mV
\ I
STOP 1 B50.000Hz
31/35
211
TS7542
Figure 13: Rx Filter Frequency Response for V.21 Low Channel (see table 13).
REF LEVEL
O.DOOdB
r/
p
-
t'
/DIV
10.DOOdB
MARKER 1 OOO.ODOHz
MAGCA/R)
-O.OSSdB
~' /
~
'/ "\
~ " \ ~~
\
~ :/
~ "
~ " \ ~ ~/ / / / / / / / / / / / /
.~
V V./ / . / / . / V/ / . / V./ / /
~ ..,.~ \ II
i-"
-
1
l
fl "
~
~
V
STOP 10 OOO.OOOHz
START O.OOOHz
AMPTD 199.5SmV
REF LEVEL
O.ODOdB
2. 1250mSEC
/DIV
1.000dB
100.00~C
~ ,/' /
/
MARKER 1 DOO.OOOHz
MAG (A/R)
0.004dB
MARKER 1 DOO.OOOHz
DELAY (A/R)
1 9949mSEC
/ ;/' / / / /
/'
/'
/'
/'
/
/
/
/
~
/
./'
/ / V
/
,/'
,/'
,/'
/ ~
/'
/:
,.
.
/.
START 790.0DOHz
AMPTD lDO.OOmV
/'
'\ \.
/
'\\
/
:Jc,/' ,./
/
\
/' ./
/'V
.....
,
./
.,. /
,I
,...
~
L
"
~
riff
.11 alii
~r
"/
.;'
/
STOP 1 290.000Hz
M88TS7542·16
32/35
212
T57542
Figure 14 : Rx Filter Frequency Response for V.29 and V.33 (see table 13).
REF LEVEL
O.OOOdB
/DIV
10.000d~
START O.OOOHz
AMPTD 199.53mV
REF LEVEL
0.725dB
895.00JASEC
MARKER 1 700.000Hz
0.749dB
MAG 30K
24/37
240
Co
M88TS75C25-11
TS75C25
4.3.2. TS7542 : CLOCK GENERATOR
CLOCK WAVE FORMS
Symbol
Min.
Typ.
Main Clock Period
XTAL1 Input
150
173.6
tWCL
Main Clock Low Level Width
XTAL1 Input
50
tWCH
50
PC
Parameter
Test Conditions
Max.
Unit
ns
ns
Main Clock High Level Width
XTAL 1 Input
tRC
Main Clock Rise Time
XTAL1 Input
50
ns
ns
tFC
Main Clock Fall Time
XTAL1 Input
50
ns
tDC
Clock Output Delay Time
All Clock Outputs CL
500
ns
tTC
Clock Output Transition Time
All Clock Outputs CL
= 50pF
= 50pF
100
Unless otherwise noted. electrical characteristics are specified over the operating range. Typical values are given for V'
Tamb = 25°C.
ns
=
5.0V and
Figure 10 : Clock Generator.
PC
tWCH
tWCL
35V
INPUT
XTAL 1
1.5 V
tRC __
/
-
V
\
-
tFC
J
'DC
,
CLOCK OUTPUTS
(9 CLOCKSI
j
~
-
'I 2.2 V
1\
0.8
v
I--I- tTC
M88TS75C25 12
25/37
241
TS75C25
4.3.3. LOCAL BUS TIMING (TS75C250 and TS7542)
(V cc = 5.0V ± 10%, T A = 0° to + 70°C, see figure 11)
Symbol
tpw
tARW
tAH
Min.
Max.
Unit
RD, WR, AS Pulse Width
Parameter
1/2te-10
1/2 te
ns
Address Valid to WR, AS, RD Low
1/2 tc - 25
ns
5
ns
1/2 tc- 25
ns
ns
Address Hold Time
tDSW
Data Set-up Time, Write Cycle
tDHw
Data Hold Time, Write Cycle
5
tDSR
Data Set-up Time, Read Cycle
15
ns
tDHR
Data Hold Time, Read Cycle
5
ns
Figure 11 : Local Bus Timing Diagram.
ADDRESSES
cJ
»»»»
tpw
RD.WR.DS
\
-
/
tARW
1-
1pW
\
' ARW
/
tpw
/
' ARW
' DSW
DO·D15
DATA OUT
LJ
DATA OUT
I
t DSR
DO-D15
DATA IN
»HI
tDHR
I
I
if
\l
I
' DHW
DATA IN
I
M88TS7524-13
Note: In multicycle exchanges, tpw. tdsw. duration is extended by 1, 2 or 3 machine cycle lenghts (tc).
26/37
242
TS75C25
4.3.4. SYSTEM BUS TIMING (TS75C250 and control processor)
(Vcc = 5.0V ± 10%, TA = 0° to + 70°C)
Symbol
Parameter
tspw
SDS Pulse Width
tSAW
SRIW, CS, RS Set-up Time
tSAH
SRIW, CS, RS Hold after SDS High
tSDSR
Data Set-up Time, Read Cycle
tSDHR
Data Hold Time, Read Cycle
tSDSW
Data Set-up Time, Write Cycle
tSDHW
Data Hold Time, Write Cycle
tDSLDT
SDS Low to DTACK Low
tDSHDT
SDS High to DTACK High
• DTACK is an open drain output test load include RL
Min.
Max.
ns
ns
ns
ns
ns
30
30
30
40
5
=
Unit
50
20
5
20
5
820
n
ns
ns
ns
ns
at Vee.
Figure 12: System Bus Timing Diagram.
tspw
-
SDS
SRD
SWR
\
-
/
tSAW
--
SR/W.CS
RS
-tSAH
~
f--
ADO-AD7
DATA IN
/
"
.
tSDliR
DATA IN
~< «<
t DSLDT
DTACK
V
tSDZW
~
tpSDSW
ADO-AD7
DATA OUT
-
DATA OUT
[>
>
;~~
tDSHDT
M88TS75C25-13
27/37
243
TS75C25
4.3.5. DM INTERFACE (DAA and T87542)
Analog Transmit Output (ATO)
V+ = 5V ± 5%, O°C $ Tamb $ + 70°C V- = - 5V ± 5%, O°C $ Tamb $ + 70°C
(unless otherwise specified)
Symbol
Parameter
Vos
Output DC Offset
CL
Load Capacitance
RL
Load Resistance
Min.
Typ.
- 250
Max.
Unit
+ 250
mV
50
pF
kQ
1.2
V out
Output Voltage Swing
(RL > 1.2kQ CL < 50pF)
Rout
Output Resistance
(read cycle)
- 2.5
+ 2.5
V
5
Q
Max.
Unit
Receive Analog Input (RAI).
Symbol
Vin
lin
Parameter
Min.
Input Voltage
Input Current (write cycle)
Typ.
- 2.5
+ 2.5
V
- 1
+ 1
J.lA
5. PIN CONNECTIONS
TS75C250
TS7542
04
03
05
02
06
01
07
DO
08
BE3
09
BE4
010
SSO
011
BS1 or ITl
orITo
012
BS2 or
013
A11
D14
V DD
015
Ala
Vss
A9
XTAL
A8
E
V·
EXTAL
AD7
CLKOUT
AD6
AD or DS
AD5
WRarA/IN
AD4
SWR or SRM [
AD3
SRD arSDS [
AD'
CS[
ADl
FiS[
ADO
RESET [
iT20r LP
BE5 or BA
IRQ [
04
05
06
07
CLKINI
R!W
CS1
CSO
RSO
RSt
BE6
oGNo
03
02
01
DO
TxSCLK
XTALt
XTAL2
TxCLK
TxRCLK
TxCCLK
RxCLK
V+
RxRCLK
RFO
LAO
Oxl
RAI
AGC2
AGC1
C01
RxCCLK
EXI
ATO
v+
V·
AGNo
v+
or DT ACK
'--------'
M88TS75C25 ·15
28/37
244
M88TS75C25·16
TS75C25
PIN CONNECTIONS (continued)
T57542
T575C250
8
~
:3
~
3 3 S
"
g
~
~ ~
Dl0
BSOIiTO
D11
881m
D12
882m
D13
All
D14
V cc
V cc
D15
R/W[
CSl
CSO
RSO
RSl
Vss
Vss
Al0
A9
E
XTAl
A8
vv+
EXTAL
AD?
CLKOUT
AD6
RDIDS
AD5
WRIR/Vi!
AD'
1* I~
~
iQ
I~w a~
~
Illffi
g~
I~ ~ >t2
§ ~
0
~
~
RFO
LAO
NC
7
8
9
10
11
12
13
14
15
16
17
18 19 20 21 22 23 2425 2627 28
Tv+ Tv-
T ATO
NC AGNO
v+
0,1 TAGC2T COl
~
RAI AGe,
M88TS75C25-17
M88TS75C25-18
TS75C250
TS7542 Interface
Name
Pin
Function
DO thru 015
I/O
Local Data Bus
A8 thru A11
0
Local Add ress Bus
OS
0
Data Strobe
R/W
0
Read/Write
-
CLKOUT
0
Clock Output
BE3 thru BE6
I
Receive and
Transmit Clocks
Description
Only 08 thru 015 lines are used for data transfer between the
TS75C250 and TS7542.
DO thru 07 are. not used and are left unconnected.
Address Lines to the TS7542
This signal synchronizes the transfer between the TS75C250 and
the TS7542.
Indicates the current bus cycle state.
This signal generated by the TS75240 is at half the frequency of
the crystal. It can be divided by 2 to provide the 5.76MHz clock for
the TS7542.
These two inputs are connected to the receive and transmit
clocks generated by the TS7542.
29/37
245
TS75C25
TS75C250
System Interface.
Name
Function
Description
1/0
System Data Bus
These bi-directional lines are used for data transfer between the
TS75C250 mailbox and a control processor.
I
Chip Select
I
Register Select
SDS
I
System Data Strobe
Synchronizes the transfer on the system bus.
SRIW
I
System ReadlWrite
Indicates the current system bus cycle state.
0
Interrupt Request
ADO thru AD7
-
CS
-
RS
-
IRQ
Pin
This active low input is asserted when the TS75C250 is to be
accessed by the control processor.
This signal is used with CS to control the data transfer between
the control processor and the TS75C250 mailbox.
Handshake signal sent to the master to gain access to the
mailbox.
Others Pins.
Name
Pin
Function
BSO thru BS2
I
Branch on State
EXTAL
I
Clock
Crystal Input for Internal Oscillator or Input Pin for External
Oscillator.
XTAL
I
Clock
Together with EXTAL this pin is used for the external 23.040MHz
crystal.
Vec
Supply
Power Supply
Vss
Supply
Ground
RESET
I
Reset
BE3 thru BE4
I
Branch a n Edge
30/37
246
Description
These three inputs are not used and must be grounded.
These two inputs are not used and must be grounded.
TS75C25
PIN DESCRIPTION TS7542
N°
Name
1-4
D4-D7
Bidirectional Data Bus.
5
ClKINI
Clock Initialization Input. Must be tied to V+ during normal operation.
6
RIW
Description
Read/Write Selection Input. This input indicates whether the current bus cycle is a read
(high) or write (low) cycle.
7-8
CS1-CSO
Chip Select Input. The chip is selected when CSO = 0 and CS1= 1.
9-10
RSO-RS1
Register Select Input. Select the register involved in a read or write operation.
11
E
Enable Input. Enables Selection Inputs
Active on a low level for read operation.
Active on a positive-going edge for write operation.
Negative Supply Voltage. V- = - 5V ± 5%
12
V-
13
V+
14
RFO
Receive Filter Analog Output. Designed to be connected to AGC1 input through a 1 J.lF
non polarized capacitor.
15
lAO
Line Attenuator Output. Duplexer analog output usefull for line monitoring during call
progress.
16
Dxl
Duplexer Input. Analog input subtracted from the receive anti-aliasing filter output to
implement duplexer function.
17
RAI
18
AGC2
19
AGC1
20
CD1
21
V+
22
Positive Supply Voltage. V+ = + 5V ± 5%
Receive Analog Input. Analog input tied to the transmission line.
This pin must be connected to the analog ground through a 1 J.lF non polarized
capacitor, in order to cancel the offset voltage of the AGC amplifier.
Analog input of the AGC amplifier and of the carrier level detector.
This pin must be connected to the analog ground through a 1J.lF non polarized
capacitor, in order to remove the offset voltage of the carrier level detector amplifier.
Positive Power Supply Voltage
23
AGND
V-
24
V+
25
ATO
26
EXI
27
RxCClK
Receive Conversion Clock Output
28
RxRClK
Receive Baud Rate Clock Output
29
RxClK
30
TxCClK
Analog Ground. All analog signals are referenced to this pin.
Negative Supply Voltage
Positive Supply Voltage
Analog Transmit Output. Capable of driving 12000 load with 5V peak to peak
amplitude.
External Transmit Input. Can be programmmed to be connected to the transmit filter or
to the transmit attenuator input.
Receive Bit Rate Clock Output
Transmit Conversion Clock Output
31
TxRClK
32
TxCLK
Transmit Bit Rate Clock Output
Transmit Baud Rate Clock Output
33
XTAL2
Crystal Oscillator Output. Nominal Frequency = 5.76MHz
34
XTAl1
Crystal Oscillator or External Master Clock Input
35
TxSCLK
Transmit Synchronization Clock Input. Can be connected to an external terminal clock
to phase lock the internal transmit clocks. When this pin is tied to a permanent logical
level the transmit DPlL free-rises or can be phase locked on the receive clock system.
36-39
DO-D23
Bidirectional Data Bus.
40
DGND
Digital Ground. All digital signals are referenced to this wire.
31/37
247
TS75C25
ORDERING INFORMATION
The TS75C25 corresponds to two different components which must be ordered separately.
available for a fast characterization improvement of
the TS75C25 in a real application.
Furthermore. a stand-alone evaluation board is
Part Number
TS75C250CP
TS7542CP
TS75C250CFN
TS7542CFN
32/37
248
Temp Range
Package
o DC to 70 DC
o DC to 70 DC
o DC to 70°C
o 'C to 70°C
DIP-48
DIP-40
PLCC-52
PLCC-44
Device
V. 22Bis Masked DSP
Analog Front End
V. 22Bis Masked DSP
Analog Frond End
TS75C25
7. PACKAGE MECHANICAL DATA
TS75C250
48 Pins - Plastic Dip.
25
(1) Nominal dimension
(2) True geometrical position
14
63.Smax.
14
48
Pins
TS75C250
52 Pins - Plastic Leaded Chip Carrier.
Pin 1 identification
1753
18,54
I
-[- - - _ . ---13--
I
0661
0,812
~
min.
52
Pins
0331
0,533
33/37
249
TS75C25
TS7542
40 Pins - Plastic Dip.
(2)
11). Nominal dimension
(2)
True geometrical pO'iition
14
(1)
40 pins
TS7542
44 Pins - Plastic Leadless Chip Carrier
16.5
3.95
4.15
28
~
-EtJ -~""1"'3-lOutputrP-l
18
17.2
17.5
44 Outputs
34/37
250
TS75C25
ELECTRICAL CONSIDERATIONS
ferences, ... should be adequately separated and
terminated at a single point.
• Optimal distribution of power supplies and
ground links using star-connection
• Adequate decoupling capacitor mounted as
close as possible to each device, and connected
to analog ground
• DSP and MAFE power supplies should be separated
To avoid possible high frequency problems, the following precautions should be considered for PC
board layout design:
• A ground plane on the component side connected to analog ground of the TS7542
• Analog and Digital ground tracks corresponding
to different signals, e.g. clocks, input signals, re-
APPENDIX A
TRANSMIT/RECEIVE COMMAND WORDS
Transmit Command Word
BIT
0
-
1
2
3
4
5
First Byte
Third Byte
Second Byte
Transmit Mode Selection
0000 : Modem Disabled
0001 : V.22 Bis
0010: V.22 0011 : B212
0100: V.23 0101 : V.21
0110:Be1l103
0111 : D.T.M.F.
Transmit Signalling
00 : Signalling Disabled
01 : 550Hz
11 : 1800Hz
Transmit (0)
01
0
P
S
K
02
0
DO
Transmit
-
Attenuation
Q
A
M
c---
--
Scrambler (ON/OFF)
--
6
Reserved
64 x 1(ON/OFF)
7
ANSW/ORIG or DTMFl
V.22 Binary Rate Select
or DTMF2
F
S
K
0
T
M
F
03
0
04
0
0
0
05
0
0
0
-
r---
Transmit Enable
Notes: All the "RESERVED" bits must be cleared to "0" by the user.
1 : DTMF : Higher/lower tone selection.
2 : DTMF : DUAUsingle tone.
Receive Command Word
BIT
0
1
2
-
3
4
First Byte
Second Byte
0000 : Modem Disabled
0001 : V.22 Bis
0010 :V.22 0011: B212
0100: V.23 0101 : V.21
0110: Bell 103
0111 : Call Progress Tone
Third Byte
Receive (1)
Receive Mode Selection
Line output Level
Reserved
Reserved
Additional Clocks
Answer Tone Selection
Descrambler (ON/OFF)
5
Tx Synchronization
6
Carrier Detect Level
64 x 1 (ON/OFF)
7
Answer/originate
V.22 Binary Rate Select
Note: All the "RESERVED" bits must be cleared to "0" by the user.
35/37
251
TS75C25
APPENDIX B
TRANSMIT/RECEIVE ST.ATUS WORDS
TRANSMIT STATUS WORD FORMAT
BIT
First Byte
0
Transmit (0)
Second Byte
Third Byte
Reserved
Reserved
Second Byte
Third Byte
1
,..--
2
r--
3
f-4
'-5
r-6
f-7
Reserved
RECEIVE STATUS WORD FORMAT
BIT
First Byte
0
Receive (1)
1
DO
Data Before
2
D1
Descrambling
3
D2
4
D3
Reserved
Reserved
-
(QAM. , D.P.S.K.)
DO
Data
D1
After
D2
Descr.
Equalization Status
D3
5
Reserved
Signal Quality
1
6
S1 Sequence
Carrier Detect
1
7
S1 Seguence or
Call Progress Tone Detection
Reserved
(QAM.,
D.P.S.K.)
DO
r---D1
r-D2
r-D3
r-D4
r-D5
Data
(F.S.K.)
Answer Tone Detection
Nole : In QAM and DPSK modes, both for the data after and before descrambling, the unused bits are set to "1" by the TS75C25.
36/37
252
-I
en
-...I
UI
o
~3.0" MHZ T
10 pF_
_::=::,_ 0 DF
N
UI
o
:J:
AL
CLKDUT/2
c
0
II
T
II
0
L
0
'"
'"
T
II
U
s
..
.&l
II
D
C
~rn
E
S
S
II
0
II
i~
C
0
N
T
R
0
L
s
OS
04
D3
D9
011
DO
LEI
RAI
02
01
LA
51
RlW
AIO
All
A9
At!
I'
RJVi
t:§
ClI
RIO
D
-I
It
A
S
P
K
•
TS75G
TS75C29
"men
ATO
07
D6
015
01"
013
012
011
010
EXI
:to
""m
Z
Ral
c
><
o
11£6
liE!
·sv
..
It
D
y
2
4
c.>
I\)
C11
c.>
I~
c.>
-.J
11: :
113
-I
en
.....
UI
0
N
UI
I
I
I
I
I
I
I
i
I
I
I
I
I
I
TS75C32
V.32, V.22BIS, V.22, V.23,
V.21, BELL212A, BELL 103 MODEM CHIP SET
ADVANCE DATA
• CCITT V.32, V22bis, V.22, V.21 ,V.23, Bell 212A,
Bell 103 COMPATIBLE MODEM CHIP SET
• INTEGRATED IMPLEMENTATION ON THREE
DSP AND THREE MAFE CHIPS
• FULL DUPLEX OPERATION FROM 9600 TO
300 BPS
• FULL IMPLEMENTATION OF THE V.32 AND
V.22BIS HANDSHAKE
• DYNAMIC RANGE: 43 dB
• TWO SATELLITE HOPS AND FREQUENCY
OFFSET CAPABILITIES (10Hz) FOR THE FAR
END ECHO CANCELLER IN V.32 MODE
• TRELLIS ENCODING AND VITERBI DECODING
• 12.5 % ROLL-OFF RAISED COSINE TRANSMITTER PULSE SHAPING
• HIGH PERFORMANCE PASSBAND FRACTIONALLY SPACED ADAPTIVE EQUALIZER
• SIGNAL QUALITY MONITORING
• PARALLEL INTERFACE TO STANDARD
MICROPROCESSORS
• BIT RATE DATA CLOCKS PROVIDED FOR
SYNCHRONOUS DATA TRANSFER
• FULL DIAGNOSTIC CAPABILITY
• DTMF GENERATION
• CALL PROGRESS TONE DETECTION
• SOFTWARE LICENSE AND DEVELOPMENT
TOOLS AVAILABLE FOR EASY CUSTOMIZATION
• TOTAL POWER CONSUMPTION BELOW 2W
P
FN
DIP48
(Plastic Package)
TS75C320/1/2
PlCC52
(Plastic Leaded Chip Carrier)
TS75C320/1/2
P
FN
DIP24
(Plastic Package)
TS68950
PlCC28
(Plastic Leaded Chip Carrier)
TS68950
DESCRIPTION
The SGS-THOMSON Microelectronics TS75C32
chip set is a highly integrated modem engine, which
can operate in full duplex from 9600 to 300 bps. The
modem hardware consists of three analog front end
(MAFE) chips, three DSP processor chips and add.itional memory chips.
P
FN
DIP28
(Plastic Package)
TS68951/52
PlCC28
(Plastic Leaded Chip Carrier)
TS68951/52
The three SGS-THOMSON analog front end chips
(TS68950/1/2) are the transmit interface, the receive
interface and the clock generator respectively.
The modem signal processing functions are implemented on three ST18930 programmable digital signal processors.
(Ordering Information at the end of the datasheet)
January 1989
1/45
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice
255
TS75C32
TABLE OF CONTENTS
1.
PIN DESCRIPTION
1.1. System Interface
1.2. Analog Interface
1.3. Clock Interface
3
3
3
3
2.
FUNCTIONAL DESCRIPTION
2.1. System Architecture
2.2. Processor and MAFE Chips Arrangement
2.3. Operation
2.4. Modem Interface
4
4
4
5
8
3.
USER INTERFACE - COMMAND SET
3.f. Comrnand Summary
3.2. Status Reporting
3.3. Command List
10
10
11
12
4.
ELECTRICAL SPECIFICATION
4.1. Maximum Ratings
4.2. DC Electrical Characteristics
4.3. AC Electrical Characteristics
14
14
15
16
5.
PIN CONNECTIONS
20
6.
ORDERING INFORMATION
22
7.
PACKAGE MECHANICAL DATA
22
A.
COMMAND SET DESCRIPTION
25
TABLE OF APPENDICES
2/45
B.
STATUS REPORTING DESCRIPTION
40
C.
INTERCONNECTION
41
D.
REFERENCES
45
~
. .. , /
256
SGS-THOMSON
Ii>lU©Ul@I<~~Ul@IIIlU©iI\
TS75C32
1. PIN DESCRIPTION
1.1. SYSTEM INTERFACE
TS75C321 (DSP#1 Transmitter and Handshake)
Pin
Name
Type
Signal
Name
ADO.AD7
110
DOH.D7H
CS
I
CSL
Chip Select: this input is asserted when the TS75C32 is to be accessed by
the host processor.
RS
I
RSL
Register Select: this signal is used to control the data transfers between the
host processor and the TS75C32 mailbox.
SDS
I
DSL
System Data Strobe: synchronizes the transfer between the TS75C32
mailbox and the host processor.
Description
System Data Bus: these lines are used for data transfer between the
TS75C32 mailbox and the host processor.
SRIW
I
RWL
System Read/Write: control signal for the TS75C32 mailbox operation.
IRQ
0
INTL
Interrupt Request: signal sent to the host processor to access the TS75C32
mailbox.
RESET
I
RSTLI
Master Reset of DSP#1
1.2. ANALOG INTERFACE
TS68950 (Analog Front End Transmitter)
Pin
Name
Type
Signal
Name
ATO
0
ATO
Description
. Analog Transmit Output
TS68951 (Analog Front End Receiver)
Pin
Name
Type
Signal
Name
RAI
I
RAI
Receive Analog Input
LEI
I
LEI
Local Echo Input. Must be grounded.
Description
1.3. CLOCK INTERFACE
TS68952 (Clock Generator)
Pin
Name
TxCLK
Type
RxMCLK
0
0
0
0
0
0
0
0
TxSCLK
I
TxRCLK
TxCCLK
TxMCLK
RxCLK
RxRCLK
RxCCLK
Signal
Name
TxCLK
TxRCLK
Description
Transmit Bit Clock
Transmit Baud Clock
TxCCLK
Transmit Conversion Clock
TxMCLK
Transmit Multiplex Clock
RxCLK
Receive Bit Clock
RxRCLK
Receive Baud Clock
RxCCLK
Receive Conversion Clock
RxMCLK
Receive Multiplex Clock
TxSCLK
Transmit Synchro Clock: can be used to synchronize the transmitter on an external bit clock provided by the RS232C (or V.24) junction.
3/45
257
TS75C32
2. FUNCTIONAL DESCRIPTION
2.1. SYSTEM ARCHITECTURE
The SGS-THOMSON TS75C32 chip set is a highly
integrated modem engine which provides the functionality and performance requirements for full-duplex 9600 bps modem solutions at a low cost and
with a small circuit area. At the heart of the modem
engine are three SGS-THOMSON DSPs which implement the complete signal processing and control
functions. The analog front end of the modem engine
consists of the SGS-THOMSON MAFE three-chip
set which is designed to meet the requirements of
high-speed modem applications and particularly
V.32 modems. The only other components in the modem engine are the extemal RAM chips used for the
far-end echo canceller delay line and the Viterbi decoder.
2.2 PROCESSOR AND MAFE CHIPS ARRANGEMENT
Figure 1 shows the interconnections between the
MAFE and signal processors.
Figure 1 : Hardware Architecture.
--------------------------------------------------------,
I
IlOH-D7H I AIJO.AD7
To
:
Control I
Processorl
M88TS75C32-01
4/45
258
TS75C32
DSP 1 communicates with the control processor
through its system bus, ADO-AD7. It is also connected to the two other DSPs through its DO-D7 and D8D15 data buses to transfer data, to pass a control
command to the DSPs and to get the modem operation status and then pass it to the control processor. The transmitter, V.32 handshake and partofthe
receiver algorithms are implemented in this processor. DSP 0 implements the echo cancellation function. 4Kx16 of RAM are connected to this processor
to implement the data delay line for the far end echo
cancellation. DSP 2 implements most of the receiver functions. 2Kx16 of RAM are attached to it due
to the requirements of the Viterbi decoder.
The transmitter interface chip, TS68950 [see ref 5
of Appendix OJ, is connected to the 8 MSB's of the
DSP 1 data bus. The echo replica is sent from DSP 1
to TS68950 then to the receiver interface chip,
TS68951 [see ref 6 of Appendix OJ, after conversion
to analog format. This chip and the clock generator
chip, TS68952 [see ref 7 of Appendix DJ, are
connected to the 8 MSB's of the DSP 2 data bus.
The clock generator chip generates the AID and DfA
sampling clocks and the data bit and baud rate
clocks.
2.3. OPERATION
2.3.1. MODES. The modem implementation is fully
compatible with many CCITT and Bell recommendation. It operates at different bit rates from 9600 to
300 bps. In the 9600 bps mode, the trellis encoder
and the Viterbi decoder can be switched in or out.
Both the bit rate and trellis options are determined
during the initial modem handshake sequence.
During FSK Modes (Bell 103, V.21 and V.23) a byte
of information is exchanged with the Data Pump.
This byte is a sampling image (7.2 /
IpW
\
K=
/
tARW
tpw
RiW
\
/
tARW
t DSW
DO-DIS
IIIII
\\\\\
DATA OUT
tDH W
1)-----
DATA OUT
t DSR
tDHR
DO-DIS
1>--
DATA IN
DATA IN
tpw
SDS
\
tARW
/
tAH
~
RIW
r--
\\\\\\\\
M88TS7532-07
18/45
272
Gi
SGS-THOMSON
~I IiilU©DiI@J
CO
r-
00
0
C
Q
::a
)00
iii:
r------~y~
I
XI
I
I
~
EEO
00:01
~~
if!'
ilIi
..~
LOCAL BUS
IISP
~
~
E
RiW
...
8 BIT DATA BUS
CTRL
csotCS.
TS .....
ST18930
CONTRDL
REGISTER
RC4
RSO/RS.
ADDRESS
I
I
ADDRESS REGISTER
ARC
I
L_ - - - -
IIL _ _ _- - '
--6- -& -G- -6-Y-
s:
I
~
DGNO
AGND
V+
__ ~~_.J
en
0)
01)
c.n
0
TS68950
PIN DESCRIPTION
Name
D5-D7
E
RIW
Function
8 bit data bus inputs giving access to Tx, estimated echo, control and address
registers.
Enable Input. Datas are strobed on the positive transitions of this input.
Read/Write Selection Input. Internal registers can be written when RIW = O. Read
mode is not used.
CSO-CS1
Chip Select Inputs. The chip set is selected when CSO = 0 and CS1 = 1
RSO-RS1
Register Select Inputs. Used to select D/A input registers or control/address registers
in the write mode.
DGND
Digital Ground = 0 V. All digital signals are referenced to this pin.
TEST
Test Input. Used to reduce testing time.
This Pin must be connected to DGND in all applications.
VAGND
EXI
Negative Power Supply Voltage = - 5 V ± 5 %
Analog Ground = 0 V.
Reference point for analog signals.
Programmable analog input tied to filter or attenuator input according to the RC4
register content.
ATO
Analog Transmit Output
EEO
Analog Echo Cancelling Output (estimated echo)
V+
Positive Power Supply Voltage: + 5 V ± 5 %
ClK
1.44 MHz Clock Input. Used for internal sequencing.
TxCClK
DO-D4
Transmit Conversion Clock Input. Must be derived from ClK.
See pins D5-D7.
DEVICE OPERATION
The TS68950 is a transmit analog interface circuit
dedicated to voice-grade MODEMs, telephony and
speech applications. The TS68950, the TS68951
(receive analog front-end circuit) and the TS68952
(clock generator) constitute an analog front-end chip
set useful for implementation of synchronous modems operating on two or four wires according to
the CCITTV.26, V.26bis, V.27, V.27bis, V.27terand
V.29 recommandations or BELL 208 and 209 standards, or on two wires full-duplex according to CCITT
V.22, V.22 bis or BELL 212A (split band) and CCITT
V.26 ter and V.32 (echo cancelling). The chipset can
also be used for asynchronous recommendations
such as V.21, V.23, Bell 103.
By receiving digital samples from a DSP like the ST
8930/31, the TS68950 delivers two analog signals:
the transmitted (Tx) signal that will be sent on the
line and the estimated echo signal that will be subtracted from the received (Rx) signal on the
TS68951 Rx chip.
The digital Tx and estimated echo samples are
converted to analog during the low state and the
high state of the TxCCLK clock, respectively.
MAIN FUNCTIONS (see block diagram)
• 12 bit digital to analog converter multiplexed on
two channels.
• Tx signal sample and hold running with Tx sampling frequency TxCCLK.
• Tx low-pass filter with continuous-time smoothing.
• Programmable attenuator from 0 to -22 dB with
2 dB steps.
• Estimated echo sample and hold running with Tx
sampling frequency TxCCLK.
DSP INTERFACE SIGNALS
The TS68950 interfaces to the signal processor via
an 8 bit data bus (only used in writing mode), two
chip select lines, two register select lines, a
read/write line and an enable line.
Data bus (00-07) - The write only data lines allow
the transfer of data from the DSP to the TS68950.
Input buffers are high-impedance devices.
Enable (E) - The enable pulse (E) is the basic timing
signal that is supplied to the TS68950. All the other
3/18
303
TS68950
signals are r~erenced to the leading and trailing
edges of the E pulse.
To run properly the TxCClK clock must be a submultiple of ClKl5:
Read/Write (R/W) - This signal is generated by the
DSP to control the direction of data transfers on the
data bus. A low level state on the TS68950
read/write line enables the input buffers and data ~
transferred from the DSP to the TS68950 on the E
signal if the circuit has been selected. The device is
unselected when a high level signal is applied to the
RIWpin.
TxCClK x 5 x N = ClK (with N integer) : This is ensured when using the TS68952 clock generator.
Chip Select (CSO, CS 1) - These two input signals
are used to select the chip. CSO must be low and
CS1 must be high for selection of the device. Data
transfers are then performed under the control of the
enable and R!W signals. The chlP select lines must
be stable for the duration of the E pulse.
Register Select (RSO, RS1) - The two register select lines are used to access the different registers
inside the chip. For instance these two lines are
used in conjunction with the internal control register
ARC to select a particular register RC4. Ihe register select lines must be stable when the E signal is
low.
The sampling clock of the switched capacitor filter
section is obtained by dividing the ClK frequency
by five and performing intemal synchronization on
the leading edges of TxCClK.
The Tx samples are converted from digital to analog during the low state of TxCClK. The estimated
echo samples are converted during the high state
of TxCClK.
INTERNAL CONTROLS
POWER-ON: The chip contains internal power-on
reset logic to initialize the RC4 control register in order to avoid undesirable signal transmission on the
telephone line with infinite attenuation.
INTERNAL ADDRESSING
RSO
RS1
Write Cycle
Number
Access
0
0
TR1 Transmitted
Sample Register
2
CLOCK INTERFACE BETWEEN TS68950 AND
TS68952
0
1
TR2 Estimated Echo
Sample Register
2
The TS68950 receives two clock lines from the clock
generator TS68952.
1
0
ARC Address Register
1
1
1
RC4 Control Register
(if addressed by ARC)
1
MASTER CLOCK SEQUENCING (ClK) : The typical frequency is 1.44 MHz but the recurrence frequency must be an exact multiple of the terminal
clock frequency. The TxDPll included in the clock
generator circuit (TS68952) operates by adding or
subtracting pulses to a 2.88 MHz internal clock. This
corresponds to phase leads or phase lags of about
350 ns duration. To ensure correct device operation,
clock synchronization must be done immediately after the negative-going transition of TxCClK clock.
SAMPLE REGISTERS (TR1 AND TR2): TR1 is the
transmitted sample register and TR2 the estimated
echo sample register. TR1 and TR2 store two's
complement 12 bit data (DACO to DAC11). As indicated below, writing each sample requires two cycles.
First Cycle
07
06
05
04
03
02
01
00
TXCCLK-....._ _ _ _ _ _ __
x
NORMAL
CLK
LEAD
Second Cycle
LAG
M88TS68950·04
TRANSMIT CONVERSION CLOCK (TxCClK) :
The conversion clock TxCClK must be derived from
the master clock ClK. Three nominal values are
possible: 9.6 kHz, 8 kHz and 7.2 kHz. 9.6 kHz is the
highest allowable frequency.
4/18
304
An internal flip-flop is used to select the first or the
second byte. It adv.§.nces one count on the positivegoing edge of the~lse when the sample registers are selected (CSO = 0, CS1 = 1 and RSO = 0).
When the samQ!e registers are disabled, the latch
is reset on any E positive-going edge.
TS68950
Both TR1 and TR2 registers are sampled by the
DAC on the falling edge of TxCCLK. Therefore their
contents must remain stable during this edge.
be connected to the filter input or to the transmit attenuator input.
CONTROL REGISTER (RC4) : The RC4 control register has two different functions. Its four most significant bits give the transmit attenuator gain following
the table below.
RC4 REGISTER
07 06 05 04 03 02 01 00
ATT ATT ATT ATT
EM EM
4
3
2
1
-
RC4 REGISTER
07 06 05 04 03 02 01 00
ATT ATT ATT ATT
EM EM
Attenuation
3
2
1
0
0
0
0
0
0
0
0
0
0
1
1
1
2
4
6
0
0
1
0
1
0
1
0
0
8
0
1
0
1
10
0
0
1
1
1
1
0
1
12
14
16
1
0
0
0
1
0
0
1
18
1
0
1
0
20
1
0
1
1
1
22
0
0
Infinite
1
EXI INPUT
1
0
0
0
1
1
0
Transmit
Attenuator
Input
1
1
Disabled
Disabled
Transmit Filter
Input
(dB)
4
2
-
2
Following power-up, all RC4 bits are preset at one:
EXI input is disabled and the transmit signal is cancelled.
DO and D3 bits are not used in the RC4 register.
ADDRESS REGISTER (ARC) : The address register stores 3 bits (D5, D6 and D7). Among the 8 possible addresses, only one is used inside the
TS68950 (RC4 address).
RC4
07
06
05
04
03
02
01
00
x
1
1
0
1
Infinite
X : don't care
1
1
1
0
Infinite
1
1
1
1
Infinite
The address of the ARC register is automatically increased by one each time the control register is accessed. This allows indirect or cyclical addressing
to RC4.
Depending on the EM1 and EM2 states in the RC4
register, the programmable analog input (EXI) can
EEO OUTPUT WAVEFORM
CLK
L..fL __ _
o
1
~--TxCCLK
•
Off.et Voltage
EEO
5118
305
TS68950
The EEO output is not valid during StH sampling.
The output presents at this time the StH offset voltage.
This offset voltage appears at the 24th ClK period
after rise transition of TxCClK and disappears at
the 31th.
ABSOLUTE MAXIMUM RATINGS
Symbol
Value
Unit
DGND Digital Ground to AGND Analog Ground
Parameter
- 0.3 to + 0.3
V
V + Supply Voltage to DGND or AGND Ground
- 0.3 to + 7
V
V - Supply Voltage to DGND or AGND Ground
-7 to + 0.3
V
DGND - 0.3 to V' + 0.3
V- - 0.3 to V + + 0.3
V
-10to+10
mA
VI
Voltage at any Digital Input or Output
Yin
Voltage at any Analog Input or Output
lout
Analog Output Current
Pial
Power Dissipation
tamb
Operating Temperature Range
tstot
Storage Temperature Range
tsold
Pin Temperature (soldering 10 s.)
V
500
mW
o to + 70
°C
- 65 to + 150
°C
+ 260
°C
Stresses above those listed under "Maximum Ratings" may cause permanent damage to the deVice. This IS a stress rating only and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied.
Exposure to maximum rating conditions for extended periods may affect device reliability. Standard CMOS handling procedures should be employed to avoid possible damage to device.
ELECTRICAL CHARACTERISTICS
Symbol
V+
Min.
Typ.
Max.
Unit
Positive Supply Voltage
4.75
5
5.25
V
V-
Negative Supply Voltage
- 5.25
-5.0
- 4.75
V
15
mA
Parameter
I'
V' Operating Current
I
V
Operating Current
-15
mA
D.C. AND OPERATING CHARACTERISTICS
Unless otherwise noted, electrical characteristics are specified over the operating range. Typical values are
given for V + = +5V, V - = -5V and T amb = 25 ·C.
DIGITAL INTERFACE
Symbol
Parameter
Min.
Max.
Unit
0.8
V
-10
10
IJ.A
-10
10
IJ.A
VIL
Input Low Level Voltage
VIH
Input High Level Voltage
2.2
IlL
Input Low Level Current
DGND < VI < VIL max
IIH
Input High Level Current
VIH min < VI < V+
6/18
306
Typ.
V
TS68950
ANALOG INTERFACE, EXI PROGRAMMABLE INPUT
Symbol
Vin
lin
Cin
Rin
Parameter
Min.
Typ.
Max.
Unit
Input Voltage Swing
- 2.5
+ 2.5
V
Input Current (input Tx lilter selected)
-10
+ 10
j.tA
50
20
pF
pF
Input Capacitance (input ATT selected)
1< 50 kHz
I> 50 kHz
Input Resistance (input ATT selected)
20
kn
ANALOG INTERFACE, ATO TRANSMIT OUTPUT
Symbol
Parameter
Min.
Vas
Output DC Offset
CL
Load Capacitance
RL
Load Resistance
1200
V out
Output Voltage Swing
RL > 1200 Q and
CL < 50 pF
- 2.5
Rout
Output Resistance
Typ.
- 250
Max.
Unit
+ 250
mV
50
pF
n
+ 2.5
V
5
n
ANALOG INTERFACE, EEO ESTIMATED ECHO OUTPUT
Symbol
Parameter
Vas
Output DC Ollset
CL
Load Capacitance
RL
Load Resistance
V out
Output Voltage Swing
RL > 10 kQ and
CL < 50 pF
Rout
Output Resistance
Min.
Typ.
- 100
Max.
Unit
+ 100
mV
50
pF
kQ
10
- 2.5
+ 2.5
V
350
500
650
Q
Min.
Typ.
Max.
Unit
DAC TRANSFER CHARACTERISTICS
Symbol
Vout(max)
LSB
Parameter
Converter Resolution
12
Nominal Output Peak to Peak Amplitude
5.0
V
Least Signi,licant Bit Amplitude
1.2
mV
Integral Linearity Error
Differential Linearity Error
Bit
-1
+ 1
LSB
- 0.7
+ 0.7
LSB
7/18
307
TS68950
TRANSMIT FILTER TRANSFER CHARACTERISTICS (see appendix 1)
Symbol
Parameter
GAR
Absolute Passband Gain at 1 kHz
GRR
Gain Relative to Gain at 1 kHz without Sin
DAC Sampling
Below 3100
3200
4000
5000
DAR
Min.
Typ.
Max.
0
Unit
dB
xix Correction 01
Hz
Hz
Hz
Hz to 12000 Hz
Absolute Group Delay
600 Hz to 3000 Hz
- 0.5
-3
0.2
160
- 36
- 46
dB
dB
dB
dB
680
J.lS
Max.
Unit
ATTENUATOR TRANSFER CHARACTERISTICS
Symbol
Parameter
ATT
Absolute Gain at 0 dB Nominal Value
RAT
Attenuation Relative to Nominal Value
BAT
Maximum Attenuation
Min.
Typ.
dB
0
- 0.5
+ 0.5
40
dB
dB
GENERAL TRANSFER CHARACTERISTICS (from DATA BUS to ATO)
Symbol
GEX
Parameter
ATO Absolute Gain at 1 kHz
Min.
Typ.
Max.
Unit
- 0.5
0
+ 0.5
dB
A TO Psophometric Noise
200
J.lV
ATO Positive Power Supply Rejection Ratio
Vac =200 mVpp
1 = 1 kHz
40
dB
ATO Negative Power Supply Rejection Ratio
Vac =200 mVpp
1 = 1 kHz
40
dB
Signal to Harmonic Distorsion Ratio (psophometric band)
60
dB
GENERAL TRANSFER CHARACTERISTICS (from DATA BUS to EEO)
Symbol
GAX
Parameter
EEO Absolute Gain at 1 kHz
Min.
Typ.
Max.
Unit
- 0.5
0
+ 0.5
dB
EEO Psophometric Noise
8/18
308
200
J.lV
EEO Positive Power Supply Rejection Ratio
Vac = 200 mVpp
f = 1 kHz
40
dB
EEO Negative Power Supply Rejection Ratio
Vac = 200 mVpp
1 = 1 kHz
40
dB
TS68950
BUS TIMING CHARACTERISTICS (see notes 1 and 2)
Parameter
Symbol
Min.
Max.
Unit
tcyc (1)
Cycle Time
320
tWEL (2)
Pulse Width, E Low Level
180
ns
ns
tWEH (3)
Pulse Width, E High Level
100
ns
t r , tf (4)
Clock Rise and Fall Time
tHCE (5)
Control Signal Hold Time
10
ns
tSCE (6)
Control Signal Set-up Time
40
ns
tSOI (7)
Input Data Set-up Time
120
ns
.tHOI (8)
Input Data Hold Time
10
ns
20
ns
Figure 1 : Bus Timing.
CD
Q)
I
1\
@
CSO~l
RSO-RSl
RIW
0
G
X
-
DO-07
®.
K
®
0)
,
J
...
\.
I
M88TS68950-06
Notes:
1. Voltage levels shown are VL< 0.4 V. VH > 2.4 V, unless otherwise specified.
2. Measurement points shown are 0.8 V and 2.2 V, unless otherwise specified.
9/18
309
TS68950
CLOCK TIMING CHARACTERISTICS
Symbol
Min.
Parameter
Typ.
Max.
Unit
Pc (1)
ClK Clock Period
695
ns
PCl (2)
ClK During Phase lead on DPll
348
ns
tWCl (3)
ClK low level Width
150
tWCH (4)
ClK High level Width
150
ns
ns
tRC, tFC (5)
ClK Rise and Fall Time
100
ns
tRT. tFT (6)
TxCClK Rise and Fall Time
100
ns
130
ns
toc (7)
TxCClK Delay Time
20
Figure 2 : Clock Timing.
CD®
CD
@)
V
\
ClK
®
®
CD
X
TxCC LK
®
M88TS68950-07
Notes:
10/18
310
1. Voltage levels are VL < 0.4 V, VH > 2.4 V, unless otherwise specified.
2. Measurement po',nts shown are 0.8 V and 2.2 V, unless otherwise specified.
»
"'D
"'D
r
(;
Estimated echo
r
--------------,I
I
I
I
I
I
I
I
EXI
I
----,
Control
I
i~
~O
~!I
I
»
EEl
LEI
AAI
o
Z
TS68951
I
MODEM
Rx analog
interface
I
I
I
______ .JI
I
~I!:
IiZz
-I
I
I
I
~;!
I
I
I
I
I
""UI
Z
I
I
I
I
registers
Z
(J)
o
:0
s:
I
I
»
-I
o
."
I
I
I
I
I
I
@.
Ax signal
TS68950
I
~
l!nt1 Line
600
Tx signal
I
I
L...,-----!!ffhK
...._ _ _
,
Clock
MCU
Digital
signal
processor
a·bit bus
11
TxCCLK. RxCCLK
TxACLK. RxRCLK
ST 18930/31
;::
~
i
~
co
T
Terminal clock
CTAL = csa. CS1. Asa. RS1.
E:
R/iN
MODEM
Tx and Rx clock
generator
TS68952
-I
en
Q)
Q)
CD
~
U1
co
o
TS68950
ORDERING INFORMATION
Part Number
Temperature Range
Package
o to + 70 "C
o to + 70 "C
PLCC 28
TS68950CP
TS68950CFN
DIP 24
PACKAGE MECHANICAL DATA
24 PINS - PLASTIC DIP
• = 2.54(2)
4.57max .
I.
16.1 max . • /
1r-__~.-__
,t51mln·1
0.2
0.3
15.24
12)
Datum
(1) Nominal dimension
(2) True geometrical position
14
OJ
24
28 PINS - PLASTIC LEADLESS CHIP CARRIER
11430
11:582
I
28 Outputs
~
min.
12/18
- 312
Pins
TS68950
APPENDIX 1
TRANSMIT LOW-PASS FILTER TYPICAL RESPONSE AND LIMITS CHART
FREQUENCY
O.
.5
(kHz)
2.
1.
4.
O.
-.5
-1
iii
:!'! -1.5
z
«
-2
"
-2.5
-3
-3.5
M88TS68950·10
TRANSMIT LOW-PASS FILTER TYPICAL RESPONSE AND LIMITS CHART
FREQUENCY
O.
5.
10.
(kHz)
15.
20.
10.
0
-10.
iD -20.
:!'!
z -30.
;{
"
- 40.
-50.
-60.
-70.
-80
M88TS68950-11
TRANSMIT LOW-PASS FILTER TYPICAL GROUP DELAY AND LIMITS CHART
FREQUENCY (kHz)
O.
1.
2.
O.
3.
4.
-0.2
~
>«
...l
w
-0.4
-0.6
0
"- -0.8
:::l
0
a:
"
-1.
-1.2
M88TS68950-12
liii
SCiS·1lI0MSON
~I ililDI:GlI@rn~I<©1rIil@~DI:O'!
13/18
313
T568950
APPENDIX 2
INTERFACE BETWEEN DSP AND MODEM ANALOG FRONT-END (TS68950/51/52)
Tx SAMPLING AND RATE CLOCKS
~--------------------------------------------------------~
: Flags
_L,
Tx signal
estimated
echo
CSO
DSP
_-------'I\~----~
CS1
RSO
RS1
RIW
residual
signal
Rx signal
from carrier level detector
:- -Rx- CLoCKS- -1
ST18930/31
TS68930/31
MAFE
68950-51-52
~------T------...!
,
,
"r'
Flags :
Rx SAMPLING AND RATE CLOCKS
M88TS68950-13
14/18
314
TS68950
APPENDIX 3
DETAILED INPUT/ OUTPUT REGISTERS DIAGRAM
Tx signal
Estimated
echo
DSP
Residual
signal
Rx signal
From carrier level detector
M88TS68950-14
RSO
RS1
Register Accessed
Writing
0
0
0
0
0
0
1
1
0
1
TR1
TR2
ARC
Control Register Addressed by ARC
Reading
1
1
1
1
0
0
1
1
R/W
0
1
0
1
0
1
RR1
RR2
CDR
Not Used
15/18
315
TS68950
APPENDIX 4
CONTROL REGISTERS PROGRAMMING
Register
Name
Circuit
Including
this Register
RC1
RC2
RC3
RC4
RC5
RC6
RC7
RC8
68952
68952
68951
68950
68951
68951
68952
68952
16/18
316
ARC Content
(register address)
Register Content
07
06
05
04
HB4 HB3
HB2 HB1
HM3 HM2 HM1
HS2
HP2 HP1
LP2
LP1
ATE4 ATE3 ATE2 ATE1
GR5 GR4 GR3 GR2
GDS2 GDS1 HDS
SP5
SP4
SP3 SP2
MPE SPR AVRE VAL
03
HR3
HS1
REJ
GR1
SP1
INIT
01
02
HR2 HR1
HTHR
S/A REC
EM2 EM1
DO
07
0
0
0
0
1
1
1
1
06
0
0
1
1
0
0
1
1
05
0
1
0
1
0
1
0
1
TS68950
APPENDIX 5
PROGRESSION OF THE DIGITAL AND ANALOG SAMPLES IN THE MAFE
1ST PERIOD
2ND PERIOD
3RD PERIOD
Tx4
EE4
Tx5
EE5
I
Tx SAMPLING
CLOCK
(Tx CCLK)
BUS
TIME AVAILABLE FOA THE
(INPUT)
ONE ESTIMATED ECHO SAMPLE EE3
DSP TO WRITE ONE
WRITING
Tx SIGNAL SAMPLE IT,3) AND
WRITING
,
))'r--------«( (+) ))'r--------«(
ll'r--------f/1
W--------<~~
TR1
REGISTER
(E~4)
TT2
(EE3)
WRITING
Tx6
EE6
(Tf5)
))'r--------
(E~5)
2';;---
(EE4)
REGISTER
TR
REGISTER
D/AC
S/H4
(Tx sample)
(Tx4)
(Tx3)
S/H3
ANOlQG SAMPLE VALID
(estimated echo)_~_--,(",E=E,-,1)_----!,
:
(EE2)
(EE3)
(EE4)
S/H2
n
(residual signal) _-:-,_ _----''-='-'---_ _--'
Rx SAMPLING
CLOCK
(Rx CCLK)
S/H1
(Rx sample)
'
:
:
I
I
'-----'
~,:',
)----K
(Rx1)
~L.---'='--'
,
'
I
(Rx2)
)
AlDC
RT2
REGISTER
RT1
REGISTER
RR2
REGISTER
BUS
(OUTPUT)
RR1
REGISTER
BUS
(OUTPUT)
M88TS68950-15
17/18
317
TS68950
APPENDIX 6
FURTHER REFERENCES
1/MAFE CHARACTERIZATION REPORT
This report gives the results of the measurements
performed on the TS68950/51/52 Modem Analog
Front-End (MAFE) chip set.
Chapter 1 describes the configuration and the method used for these measurements.
Chapter 2 comments the results obtained on the two
signal paths of the transmit (Tx) analog front-end
TS68950, i.e. the echo path and the Tx signal path
Similarly chapter 3 gives the results obtained on the
echo path and the receive (Rx) signal path of the Rx
analog front-end TS68951
Performances obtained on the TS68951 when
using plesiochronous clocks are given in chapter 4.
In this case, the TS68952 clock generator delivers
the main clock and the two sampling clocks to the
Rx analog interface
2/MAFE EVALUATION BOARD
The MAFE evaluation board is a complete unit for
evaluation of the TS68950/51/52 MAFE chip set.
18/18
318
The MAFE evaluation board is equipped with the
TS68950/51/52 chip set and phone line interface facilities.
It can be directly connectable to an external Digital
Signal Processor through a 50-pin connector or can
be linked to the SGS-THOMSOM family of digital signal processors emulation-evaluation tools. In this
case, along with the software tools (MACROASSEMBLER, SIMULATOR and LINKER), it provides
a ready-to-use Digital Signal Processor System Interface well adapted to the analog word and high
speed modems development.
3/APPLICATION NOTE
This Application Note describes the development of
Real-Time Algorithms using the SGS-THOMSON
Digital Signal Processor TS68930 and the MAFE
chip set.
TS68951
MODEM RECEIVE ANALOG INTERFACE
• TWO CHANNEL 12-BIT ANALOG TO DIGITAL
CONVERTER FOR RECEPTION OF DIGITAL
DATA FROM THE TELEPHONE LINE AND
ECHO CANCELLATION (with asynchronous
multiplexing of 2 plesiochronous channels)
• PROGRAMMABLE SWITCHED CAPACITOR
BAND-PASS FILTER
• PROGRAMMABLE GAIN AMPLIFIER FROM 0
TO 46.5 dB WITH 1.5 dB STEPS
• PROGRAMMABLE BACK CHANNEL REJECTION AND RECONSTRUCTION FILTER
• CARRIER LEVEL DETECTOR WITH PROGRAMMABLE THRESHOLD
• DIRECT INTERFACE WITH STANDARD MPU
8-BIT BUS
• LOW POWER CMOS TECHNOLOGY
• AVAILABLE IN DIL OR SURFACE MOUNT
PACKAGE
The TS68951 meets all the CCITT recommendations from V.22 to V.33 including full-duplex recommendations with echo-cancellation (V.32) thanks to
its multiplexed 2nd channel.
Used in conjunction with the TS68950 Transmit (Tx)
Analog Front-End circuit and the TS68952 clock
generator', it provides a very cheap and efficient interface to digital signal processing functions in high
speed modems or telephony applications.
'The interconnection between the 3 chips of the Modem Analog
Front End (MAFE) is decribed p16/30.
P
FN
DIP28
PLCC28
(Plastic package)
(Plastic package)
DESCRIPTION
The TS68951 is a Receive (Rx) Analog Front-End
circuit designed to implement the analog to digital
conversion and filtering required by high-speed
voice-band modems or speech coding applications
using digital signal processing technology.
(Ordering Information at the end of the datasheet)
PIN CONNECTIONS
DIP28
PLCC28
05
04
06
03
07
02
E
E
D6
D5
D4
D3
RNI
02
D1
01
eso
DO
R/W
DO
eS1
TxCClK
CSD
TxCClK
RSO
RxCCLK
CS1
RxCClK
RS1
ClK
AS1
OGNO
EEl
eLK
v,
DGND
v+
AGC2
EEl
AGC2
eD1
AGC1
lEI
RFO
RAI
v-
AGNO
AGel
RFO
M88TS68951·01
January 1989
D7
AGND
LEI
M88TS68951·02
1/30
319
W
IU
o
m
r
§
o
o
o
"
:;
EEl
LEI
RSO
TxCCLK
G')
ASl
:II
~
s:
RAI
ASYNC
MUX
12 BIT
ADC
~
I
I
I
I
O1:CII
r-------.l.-----------4
©~
ill.
I
I
I
~i!
!O
ill",CII
I:
DATA
BUS
~O
~Z
SCF
AC:~C5 k~=====1
: Switched-capacitor filter
CTF
: Continuous-time filter
SCFl
: Rx band-pass filter
SCF2
: Back-channel rejection filter
SCF3 : Reconstruction filter
I
~
8
CTFl
: Anti-aliasing Rx I;:)w-pass filter
CTF2
: Smoothing low-pass filter
CONTROLk~::::::::::::::::::::::::~
:~
REGISTERS
AGC2
RFO
RxCCLK
T
T
-I
CJ)
0')
CO
CO
C1I
.....
TS68951
PIN DESCRIPTION
Name
D5-D7
E
RIW
Description
Data Bus
Enable Input. Enables Selection Inputs.
Active On a low level for Read Operation.
Active On a Positive Edge for Write Operation.
Read/write Selection Input. Read operation is selected on a high level.
Write operation is selected on a low level.
~
Chip Select Inputs. The chip set is selected when CSO
RSO-RS1
Register Select Inputs. Select the register involved in a read or write operation.
DGND
EEl
AGC1
RFO
VAGND
RAI
0 and CS1
~
CSO-CS1
1.
Digital Ground. All digital signals are referenced to this pin.
Estimated Echo Input. When operating in echo cancelling mode, this signal is added to the
reception bandpass filter output.
Analog input of the automatic gain control amplifier and of the carrier level detector.
Reception Filter Analog Output. Designed to be connected to AGC1 input through a 1 ~F non
polarised capacitor.
Negative Power Supply. V-
~
- 5V
± 5 %.
Analog Ground. All analog signals are referenced to this pin.
Receive Analog Input. Analog input tied to the transmission line.
lEI
local Echo Input. Analog input substracted from the receive anti-aliasing filter output.
CD1
This pin must be connected to the analog ground through a 1 ~F non polarised capacitor, in
order to cancel the offset voltage of the carrier level detector amplifier.
AGC2
This pin must be connected to the analog ground through a 1 ~F non polarised capacitor, in
order to cancel the offset voltage of the AGC amplifier.
V+
ClK
Positive Power Supply V+
~
RxCClK
Receive Conversion Clock.
TxCClK
Transmit Conversion Clock.
DO-D4
+ 5 V ± 5 %.
Master Clock Input. Nominal Frequency 1.44 MHz.
Data Bus.
FUNCTIONAL DESCRIPTION
The TS6895i is a received analog interface for
voice-band MODEM. It is able to perform the receive
interface function for three types of synchronous
MODEM:
• Four-wire or two-wire half duplex MODEM
• Two-wire full duplex band-split MODEM
• Two-wire full duplex echo cancelling MODEM
FOURITWO WIRE HALF DUPLEX MODEM
TWO WIRE BAND SPLIT MODEM
In these modes of operation, EEl input must be tied
to the analog ground. The analog signal treatment
of receive input is shown in figure 3 pi7/30.
Programming requirements:
• Band-pass filter cut-off frequencies
• Back channel rejection filter (presence or absence according to the application)
• SCFi or SCF2 output as input of CTF2
• AGC gain
• Carrier level detector threshold
The receive samples are coded at RxCCLK rate and
can be read from receive register (RRi)
TWO WIRE ECHO CANCELLING MODEM
This mode of operation uses the full capabilities of
the TS6895i. The analog treatment of receive input
is shown in figure 4 pi8/30. The echo cancelling
operation is achieved by means of subtraction of the
LEI signal from the output of CTFi duplexer and addition of the EEl signal to the output of SCi.
3/30
321
TS68951
After the local echo reduction by the duplexer the
resultant signal consists of the receive signal plus
the echo signal generated by the transmission line
mismatch: this undesirable signal is then cancelled
at the output of the Rx band-pass filter.
Programming requirements:
• Band-pass filter cut-off frequencies
• SCF1 output as input of S/H2
• Output of S/H2 as input of SCF3 and output of
SCF3 as input of CTF2.
• AGC gain
• Carrier level detector threshold
Residual signal samples from S/H2 output are coded at TxCCLK rate and can be read from receive
register 2 (RR2), hence the signal processor may
correlate them with the transmit samples to update
the coefficients of the filter that generates the estimated echo.
The receive signal samples are coded at RxCCLK
rate and can be read from receive register 1 (RR1).
FUNCTIONAL SPECIFICATIONS
BUS AND REGISTERS CONTROL
WRITE OPERATION
For any operation involving bus and registers, the
c.!:!l2...select bits CSO and CS1 must be active
(CSO = 0 and CS1 = 1)
There are three control registers (RC3, RC5, RC6)
and one address register (ARC) which can be written; but only ARC can be directly addressed.
The seven internal registers are divided into four
write only registers and three read-only registers
The control registers are indirectly addressed by the
word contained in ARC according to table 1.
Table 1.
Addressed Control Register
Word Contained in ARC
07
06
05
04
03
02
01
00
RC3
0
1
0
X
X
X
X
X
RC5
1
0
0
X
X
X
X
X
RC6
1
0
1
X
X
X
X
X
x:
don·t care.
When a write operation is selected (refer to table 3)
the data present on the bus are strobed on a positive edge of E and the content of ARC is incremented
When the RMS value of CTF2 output is greater than
the programmed threshold, bit 7 of CDR is set. The
nominal response time of the carrier detector to a
signal settlement or removal is 1.78 ms.
Note : Addresses of RC3 and RC5 are separated
by two increments
When a read operation is selected (refer to table 3)
the data are sent to the bus on a low level of E ; a
high level on E sets the output bus drivers in a high
impedance state
.
READ OPERATION
There are two 12-bit receive registers (RR1, RR2)
and a 1-bit carrier detector register (CDR)
RR2 contains the coded samples of the residual signal and RR1 the coded samples of the receive signal
As the data bus has only 8 bits, the contents of RR 1
or RR2 must be read in two cycles. The four less significant bits are transferred in the first cycle and the
eight most significant bits are transferred in the second cycle according to the format, table 2.
The active bit of CDR is D7:00 to D6 are forced to 0
Table 2.
-
DO
07
06
05
04
03
02
01
First Cycle
RRx3
RRx2
RRx1
RRxO
0
0
0
0
Second Cycle
RRx11
RRx10
RRx9
RRx8
RRx7
RRx6
RRx5
RRx4
4/30
322
TS68951
An internal latch selects the first or the second byte
and is automatically incremented on a positive edge
ofE when one of the receive registers is addressed.
This latch is not reset at power-on, so it needs to be
reset before the first read operation : reset occurs
on any positive edge of E for any operation, provided none of the receive registers is addressed; the
first byte is selected when reset.
RR1 AND RR2 OUTPUT CODE:
The output code is a 2's complement delivering values from - 2048 up to + 2047. Since the converter
. codes voltage between - V reI and + V reI, the theo-
retical decision voltage corresponding to code C can
be computed as follows:
2C + 1
Vc = 4095 Vrel
where Vrel is the reference voltage of the NO
converter, Vrel nominal value is 2.5 V and C is the
algebraic value of code C.
Example:
Assume the output code is the hexadecimal value
$8B1 ; the algebraic value of this code C = - 1871
therefore Vc = - 2.283 V.
Table 3.
R/W
RSO
RS1
0
1
1
Write Control Register Addressed by ARC
Operation
0
1
0
Write Address Register (ARC)
1
0
1
Read Receive Register 2 (RR2) (residual signal sample)
1
0
0
Read Receive Register 1 (RR1) (receive signal sample)
1
1
0
Read Carrier Detector Register (CDR)
CONTROL· REGISTERS DESCRIPTION
POWER-ON
The control registers are not initialised at power-on;
they must be initialised before reading any word
from the output registers.
REGISTER RC3
The contents of RC3 sets the- 3 dB cut-offfrequencies of SCF1 receive band-pass filter, determines
the presence or the absence of SCF2 back channel
rejection filter and of SCF3 reconstruction filter, and
selects receive signal path to the second filtering
section; without echo-cancelling the output of SCF1
or SCF2 is selected; with echo-cancelling the output of S/H2 is selected.
The band-pass filter consists of a 5th-order elliptic
low-pass filter and of a 2nd order high-pass filter
whose cut-off frequencies can be programmed by
(LP 1,LP2) and (H P1, H P2) respective Iy, (refer table 4).
The rejection filter is present when REJ bit is high.
The reconstruction filter is present when REC bit is
high.
S/H2 output is selected when S/A bit is high.
5/30
323
TS68951
Table 4.
07 06
HP2 HP1
05 04
LP2 LP1
03 02 01
REJ S/A REC
00
RC3 Register
Low-pass Filter
0
0
1
1
Sampling Frequency Fs
(kHz)
- 3 dB Cut-off Frequency
(Hz)
72
144
288
288
800
1600
3200
3200
x
x
x
x
0
1
0
1
High-pass Filter
0
1
1
x
0
1
Sampling Frequency Fs
(kHz)
- 3 dB Cut-off Frequency
(Hz)
36
72
144
250
500
1600
x
x
x
0
0
0
High-pass and Rejection Filter
1
1
0
1
1
1
Sampling
Frequency
(kHz)
- 3 dB Cut-off
Frequency (Hz)
Rejected Band
(Hz)
x
x
72
144
800
2200
370-470
800-1600
x
x
Deselected
Selected
x
x
Deselected
Selected
S/H2 Selection
0
1
Reconstruction Filter Selection
0
1
X: don't care.
6/30
324
(sampling frequency Fs = 288 kHz)
TS68951
REGISTER Re5
The content of Re5 sets the gain of the AGe amplifier between 0 dB and 46.5 dB with 1.5 dB steps.
Note: The AGe loop control is performed by the signal processor.
Table 5.
07
06
05
04
03
02
01
00
RC5
AGC Gain (dB)
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
1
0
0
1
0
1
0
0
0
1
1
1
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
0
1
1
1
1
1
0
0
0
0
1
0
0
0
1
1
0
0
1
0
1
0
0
1
1
1
0
1
0
0
1
0
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
0
0
0
1
1
0
0
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
1.5
3
4.5
6
7.5
9
10.5
12
13.5
15
16.5
18
19.5
21
22.5
24
25.5
27
28.5
30
31.5
33
34.5
36
37.5
39
40.5
42
43.5
45
46.5
X: donl care.
7/30
325
TS68951
REGISTER RC6
The content of RC6 sets the carrier level detector
threshold. (Refer to table 6).
The threshold values are grouped by pair; values
belonging to each pair have 2.5 dB separation which
allows the signal processor to perform software hysteresis.
Table 6.
07
06
05
04
03
02
01
00
Re6
Threshold (dBm)
x:
0
0
0
x
x
x
x
x
- 29.85
0
0
1
x
x
x
x
x
- 27.35
0
1
0
x
x
x
x
- 36.65
0
1
1
x
x
x
1
0
0
x
x
x
x
- 46.75
1
0
1
x
- 44.25
1
0
1
1
x
x
- 46.75
1
x
x
x
x
1
x
x
x
x
x
x
x
x
x
x
x
x
- 34.15
- 44.25
don't care.
CLOCK
The master clock CLK, the receive conversion clock
(RxCCLK) and the transmit conversion clock
(TxCCLK) are generated in the TS68952 clock generator. There are three possible frequencies for the
conversion clocks: 7.2 kHz, 8 kHz and 9.6 kHz.
put voltage ranges from - 2.5 V to + 2.5 V ; and the
conversion time is better than 50 Ils.
ASYNCHRONOUS MULTIPLEXING
The nominal values of the RxCCLK and TxCCLK
clocks must be identicals (these clocks are plesiochronous and real values within ± 100 ppm according to CCITT recommandations).
Samples on the output of S/H1 and S/H2 are converted respectively at RxCCLK frequency and TxCCLK
frequency. Since RxCCLK and TxCCLK are plesiochronous, the order of conversion is determined by
an asynchronous logic. The output register RR1 and
RR2 are respectively loaded on the negative edge
of RxCCLK and TxCCLK.
The frequency of RxCCLK and TxCCLK is controlled by two independant Digital Phase Locked Loops
(DPLL). TxCCLK can be synchronised on an external Terminal Clock (TxSCLK) or on the Rx bit rate
clock; in these cases 350 ns discrete phase shifts
occurs on CLK and TxCCLK synchronously with
TxCCLK negative edge with a repetition rate of 600
Hz, 800 Hz or 1 000 Hz according to the programmation of RC1 control register in the TS68952.
The AGC consists of two cascaded amplifiers A 1
and A2 (see fig.1) AC coupling is obtained from C1
and C2 external capacitors. C2 can be used as an
auxiliary input for performing an analog loop located
after echo cancellation. The carrier level detector
(CLD) amplifier A3 also needs an external capacitor C3.
NO CONVERSION
The NO converter is a 12 bit resolution, 8 bit minimum integral linearity, monotonic converter. The in-
8/30
326
AGC AND CLD AMPLIFIERS
TS68951
Figure 1 : Rx Amplifiers Schematic.
to carrier
level
detector
COl
RFO
Rx
AGC1
Filter
to AID
~
analog ground
M88TS68951·04
ELECTRICAL SPECIFICATIONS
The electrical specifications are given for operating temperature range (0 DC, 70°C).
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
Supply Voltage between V + and AGND or DGND
- 0.3 to + 7
V
Supply Voltage between V- and AGND or DGND
- 7 to + 0.3
V
Voltage between AGND and DGND
- 0.3 to + 0.3
V
Digital Input Voltage
DGND - 0.3 to V+ + 0.3
V
Digital Output Voltage
DGND - 0.3 to V+ + 0.3
V
Digital Output Current
- 20 to + 20
mA
V
Analog Input Voltage
V--0.3toV++0.3
Analog Output Voltage
V - - 0.3 to V + + 0.3
V
Analog Output Current
- 10 to + 10
mA
Power Dissipation
Toper
Operating Temperature
T stg
Storage Temperature
500
mW
o to + 70
°C
-65to+150
°C
9/30
327
TS68951
POWER SUPPLIES
DGND = AGND = 0 V
Symbol
Parameter
Value
Min.
Typ.
Max.
Unit
V+
Positive Power Supply
4.75
5.25
V-
Negative Power Supply
- 5.25
- 4.75
V
1+
Positive Supply Current (receive signal level 0 dBm)
20
mA
1-
Negative Supply Current (receive signal level 0 dBm)
- 20
V
mA
DIGITAL INTERFACE
Control Inputs.
Voltages Referenced to DGND = 0 V
Symbol
Parameter
VIL
Low Level Input Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Current DGND < VI < 0.8 V
VIH
High Level Input Current 2.2 V < VI < V +
DATA BUS
Voltages Referenced to DGND
Parameter
Low Level Input Voltage
VIH
High Level Input Voltage
VOL
Low Level Output Voltage (loL
VOH
High Level Output Voltage
loz
High IllJPedance Output Current
(when E is high and DGND < VI < V+)
ANALOG INTERFACE
All Voltages Referenced to AGND
Symbol
Unit
0.8
V
-10
10
~A
-10
10
~A
V
Value
Min.
= 2.5 mAl
(lOL = 2.5 mAl
2.4
V
V
- 50
50
Value
Min.
~
V
1
~
kQ
1.5
Input Resistance CD1
0.7
Rou!
Output Resistance RFO
Unit
2.5
Input Resistance AGC1, AGC2
Output Voltage RFO CL = 50 pF, RL = 1 kQ
Max.
-1
Rin
YOU!
Typ.
-2.5
Rin
Load Capacitance RFO
V
V
0.4
Input Current EEl, LEI, RAI (- 2.5 V < Yin < 2.5 V)
Load Resistance RFO
Unit
=0 V
Input Voltage EEl, LEI, RAI
RL
Max.
0.8
Parameter
CL
Typ.
2.2
li~
328
Max.
=0V
VIL
10/30
Typ.
2.2
Symbol
Vin
Value
Min.
-2.5
kQ
2.5
V
2
Q
kQ
1
50
pF
TS68951
BUS TIMING CHARACTERISTICS
(see foot notes 1 and 2 on timing diagrams)
Symbol
Value
Parameter
Min.
Typ.
Max.
Unit
tCYC
Cycle Time
(1)
320
ns
tWEL
Pulse Width E Low Level
(2)
180
ns
tWEH
Pulse Width E High Level
(3)
100
t r , tf
Clock Rise and Fall Time
(4)
tHCE
Control Signal Hold Time
(5)
10
ns
tSCE
Control Signal Set-up Time
(6)
40
ns
tSOI
Input Data Set-up Time
(7)
120
ns
tHOI
Input Data Hold Time
(8)
1
ns
tsoo
Output Data Set-up Time
(1 TTL load and CL = 50 pF)
(9)
toz
Output High Impedance Delay Time
(1 TTL load and CL = 50 pF)
ns
20
ns
150
ns
80
ns
(10)
RECEPTION CHARACTERISTICS
PERFORMANCE OF THE WHOLE RECEPTION CHAIN (input RAI or LEI, output RR1)
Symbol
G
TO
Value
Param.eter
Gain
(AGC gain = 0 dB, RxCCLK
f = 2000 Hz)
Min.
Typ.
- 0.5
Max.
Unit
- 0.5
dB
- 58
dB
= 9600 Hz, Vin = 775 mVeff,
Total Non Harmonic Distortion
(AGC gain = 0 dB, RxCCLK = 9600 Hz, Vin
f = 2000 Hz)
= 775 mVeff,
PERFORMANCE OF THE RECEPTION SUB-CHAIN (from RAI input to S/H2 input)
Symbol
TD
Parameter
Total Distortion
(RxCCLK = 9600 Hz, Vin
Value
Min.
Typ.
Max.
-72
Unit
dB
= 1.6 V eff, f = 2000 Hz)
11/30
329
TS68951
WRITE OPERATION
(3)
@
/
\
0
@
CSO--CSl
RSO-RSl
RNi
®
G
X.
K
®
0)
,
J
00-07
!\
1/
M88TS68950-06
READ OPERATION
CD
G)
~
V
f\
@
CSO-CSl
RSO-RSl
RtW
...l
G
G)
®
)
K
@
@
~
00-07
Notes:
12/30
330
J
'-
I\.
r
1. Voltage levels.shown are VIL < 0.4 V. V,H > 2.4 V, unless otherwise specified.
2. Measurement points shown are 0.8 V and 2.2 V, unless otherwise specified.
M88TS68951-05
TS68951
RECEIVE BAND-PASS FILTER AND REJECTION FILTER (input RAI, output RFO)
Symbol
Value
Parameter
Min.
Low-pass Filter (Fs
Gref
Grel
Typ.
Unit
Max.
= 288 kHz)
Reference Gain
(V in = 775 mVeft. f
= 1800
- 0.5
0.5
dB
- 0.4
-3
0.3
0.3
- 60
dB
dB
dB
Hz)
Relative Gain to G ref
Hz
f = 3200 Hz
f > 6250 Hz
o Hz < f < 3000
T gp
Group Propagation Delay Time
(f = 1800 Hz)
300
~s
T gpd
Group Propagation Delay Time Distortion
(600 Hz < f < 3000 Hz)
360
~s
- 0.5
0.5
dB
- 0.4
-3
0.3
0.5
- 25
dB
dB
dB
50
~s
450
~s
0
dB
25
27
30
27
0
dB
dB
dB
dB
dB
High-pass Filter (Fs
Gref
Grel
= 72 kHz)
Reference Gain
(V in = 775 mVeff , f
= 1800
Hz)
Relative Gain to G ref
500 Hz < f s 3000 Hz
f = 500 Hz
f < 100 Hz
T gp
Group Propagation Delay Time
(f = 1800 Hz)
T gpd
Group Propagation Delay Time Distortion
(600 Hz < f < 3000 Hz)
High-pass Filter and Rejection Filter (Fs
Gref
Grel
Reference Gain
(Vin = 775 mVeff, f
= 72 kHz)
- 1
= 1800
Hz)
Relative Gain to Gref
f = 100 Hz
f = 370 Hz
390 Hz < f < 450 Hz
f = 470 Hz
f = 900 Hz
T gp
Group Propagation Delay Time
(f = 1800 Hz)
T gpd
Group Propagation Delay Time Distortion
(600 Hz < f < 3000 Hz)
-
75
~s
1400
~s
Note: The measurement frequencies are integer sub-multiples of filters sampling frequencies.
13/30
331
TS68951
RECONSTRUCTION FILTER
Symbol
Value
Parameter
Min.
Reconstruction Filter (Fs
Grel
Grel
Typ.
Unit
Max.
=288 kHz)
Reference Gain
(V in = 775 mV ell , f = 2000 Hz)
- 0.3
0.3
dB
- 0.4
-3
0.3
0.3
- 60
dB
dB
dB
Relative Gain to Grel
o Hz < f < 2900 Hz
f=3100Hz
f > 6000 Hz
T gp
Group Propagation Delay Time
(f = 1800 Hz)
300
/ls
Tgpd
Group Propagation Delay Time Distortion
(600 Hz < f < 3000 Hz)
440
/ls
0.5
dB
350
/lVell
Whole Reception Filtering Chain (input RAI or LEI, output RFO)
Grel
Reference Gain
(V in = 775 mVelf. 1=2000 Hz, RC3 = $AO)
Nrfo
Noise on RFO
(RAI, LEI, EEl tied to AGND 250 Hz < I < 3200 Hz)
- 0.5
PERFORMANCE OF RESIDUAL SIGNAL CHANNEL AND AID CONVERTER
(input EEl, output RR2)
Parameter
Symbol
Value
Min.
Typ.
Max.
Unit
Input Voltage (peak to peak)
5
V
Resh
ND Converter Resolution
12
Bit
LSB
Analog Increment
16
LSB
Vin
Eil
1.2
-16
Integral Linearity Error
mV
Edl
Differential Linearity Error
- 0.7
0.7
LSB
Vos
Offset Voltage
- 100
100
LSB
AGC AMPLIFIER AND AID CONVERTER (input AGC1, output RR1)
Symbol
Grel
Vos
N
14/30
332
Parameter
yalue
Min.
Typ.
Max.
Unit
Relative Gain to Programmed Gain
o dB ,;; AGC ,;; 24 dB
25.5 dB ,;; AGC ,;; 46.5 dB
- 0.5
-1
Oflset Voltage
-70
Equivalent RMS Noise
(AGC gain = 0 dB, RAI, LEI, EEl tied to AGND)
0.5
1
dB
dB
70
LSB
1.2
mV el1
TS68951
CARRIER LEVEL DETECTOR (input AGC1, output CDR)
Parameter
Symbol
Trel
Relative Threshold to Programmed Threshold
Hyst
Hysteresis
Vos
Input Offset Voltage
1st Threshold Pair
2nd Threshold pair
3rd Threshold Pair
T dd
Detection Delay Time
o mVeff to 775 mVeff Transition
Value
Min.
Typ.
Max.
Unit
-1
1
dB
2
3
dB
-1
-2
-3
1
2
3
mV
mV
mV
1
3
ms
or 775 mVel1 to 0 Veff Transition
Gi
SGS·11tOMSON
~I [lI,iJD©b'iI@l-----t
:t
CTF1
~
·1
~
::;;::
SCF1
~
S/H2
:l:
h
1
~.
I
m
0
:::r
0
()
III
::l
0
ASYNC.
~
5"
MUX
to
12 BIT
l>
ADC
::l
III
0"
~
to
(Jl
cO"
~cn
::l
!O
iii
~
3
e!.
@~
~.
~;!
--I
"'!Ii
@cn
-
-.4
<{
..J
w
-.5
0
a.
::J
-.6
0::
-.7
0
OJ
-.8
-.9
-1.
20/30
338
M88TS68951·11
TS68951
Rx HIGH-PASS FILTER TYPICAL RESPONSE AND LIMITS CHART (Fs = 72 kHz).
FREQUENCY (kHz)
.25
O.
.75
.5
1.
5.
O.
-5.
a;
~
z
;;:
'"
-10.
-15.
-20.
-25.
-30.
-35.
M88TS68951-12
Rx HIGH-PASS FILTER TYPICAL GROUP DELAY TIME AND LIMITS CHART (Fs
= 72 kHz).
FREQUENCY (kHz)
.8
3.2
2.4
1.6
4
M88TS68951-13
Rx BAND-PASS FILTER TYPICAL RESPONSE AND LIMITS CHART (HP : Fs = 72 kHz, LP : Fs =288 kHz).
FREOUENCY (kHz)
O.
1.
2.
3.
4.
.5
O.
-.5
a;
-1.
:!:!
z
;;:
'"
-2.
-3.
M88TS68951-14
21/30
339
TS68951
Rx BAND-PASS FILTER TYPICAL GROUP DELAY TIME AND LIMITS CHART
(HP : Fs = 72 kHz, LP : Fs = 288 kHz).
FREQUENCY (kHz)
-.1
-.2
-.3
i
>-
-.4
-'
w
-.5
ex:
-.7
«
0
"::l
0
-.6
"
-.8
-.9
-1.
M88TS68951-15
Rx BAND-PASS AND REJECTION FILTER TYPICAL RESPONSE AND LIMITS CHART
(HP and REJ. : Fs = 72 kHz, LP : Fs = 288 kHz).
FREQUENCY (kHz)
a.
2.
1.
3.
4.
2.
A.
-2.
m
-4.
~
z
«
"
~.
~.
-12.
M88TS68951-16
Rx BAND-PASS AND REJECTION FILTER TYPICAL RESPONSE AND LIMITS CHART
(HP and REJ. : Fs = 72 kHz, LP : Fs = 288 kHz).
1.
5.
fREQUENCY (kHz)
2.
3.
4.
crnr~"""TTTT~
A.
-5.
M88TS68951-17
22/30
340
TS68951
Rx BAND-PASS AND REJECTION FILTER TYPICAL GROUP DELAY TIME AND LIMITS CHART (HP and
REJ. : Fs = 72 kHz, LP : Fs = 288 kHz).
FREQUENCY (kHz)
o.
O.
2.
1.
3.
4.
--0.
]
-1.
><(
...J
w
-1.4
a
"-
::J
-1.8
a
a:
C)
-2.2
-2.6
-3.
M88TS68951-18
Rx HIGH-PASS AND REJECTION FILTER TYPICAL RESPONSE AND LIMITS CHART (Fs = 72 kHz).
FREQUENCY (kHz)
.5
.75
1.
5.
O.
-5.
a;
-10.
:!!
z
-15.
C)
-20.
<
-25.
-30.
-35.
M88TS68951-19
Rx BAND-PASS FILTER TYPICAL RESPONSE FOR V22 MODE (Low Channel)
(HP: Fs = 72 kHz, LP: Fs = 144 kHz).
FREQUENCY (kHz)
o.
2.
1.
3.
4.
5.
O.
-5.
-10.
-15.
-20.
-25.
-30.
-35.
M88TS68951-20
mI SCiS·1HOMSON
~
iJljJ~!:oorn~I<©~WJ@Lll~!:$
23/30
341
TS68951
Rx BAND-PASS FILTER TYPICAL GROUP DELAY TIME FOR V.22 MODE (Low Channel)
(HP : Fs = 72 kHz, LP : Fs = 144 kHz).
FREQUENCY (kHZ)
o.
1.
2.
3.
4.
O.
-.2
-.4
!
-.6
>
«
-.8
-'
w
e
-1.
":>
-1.2
0
II:
Cl
-1.4
-1.6
-1.8
-2.
M88TS68951·21
Rx BAND-PASS FILTER TYPICAL RESPONSE FOR V.22 MODE (High Channel)
(HP and REJ. : Is = 144 kHz, LP : Is = 288 kHz).
FREQUENCY (kHz)
5.
2.
1.
O.
O.
-5.
iii
-10.
~
-15.
Cl
-20.
:=!
«
-25.
-30.
-35.
M88TS68951-22
Rx BAND-PASS FILTER TYPICAL GROUP DELAY TIME FOR V.22 MODE (High Channel)
(HP and REJ. : Fs = 144 kHz, LP : Fs = .288 kHz).
FREQUENCY (kHz)
o.
O.
1.
2.
3.
4.
-.2
-.4
!,.
-.6
-'
w
-1.
«
-.8
0
":>
0
0:
-1.2
-1.4
Cl
-1.6
-1.8
-2.
24/30
342
M88TS68951·23
TS68951
RECONSTRUCTION FILTER TYPICAL RESPONSE AND LIMITS CHART.
FREQUENCY (kHz)
2.
1.
O.
4.
J.
.5
.0
-.5
-1.
iii
:s
-1.5
«
-2.
z
Cl
-2.5
-3.
-3.5
M88TS68951·24
RECONSTRUCTION FILTER TYPICAL RESPONSE AND LIMITS CHART.
FREQUENCY (kHz)
O.
5.
10.
15.
20.
25.
10.
O.
-10.
-20.
iii
2
z
«
Cl
-30.
~.
-so.
-60.
-70.
-80.
M88TS6B951-25
RECONSTRUCTION FILTER TYPICAL GROUP DELAY TIME AND LIMITS CHART.
FREQUENCY (kHz)
o.
1.
4.
O.
-.1
-.2
!
-.3
«
-.4
>
.J
..
w
0
:>
0
a:
f««{««««{({«««<;1
-.5
-.6
-.7
Cl
-.8
-.9
-1.
M88TS6B951-26
25130
343
TS6B951
APPENDIX 2
INTERFACE BETWEEN DSP AND MODEM ANALOG FRONT-END (TS68950/1/2)
Tx SAMPLING AND RATE CLOCKS
Flags
I-------L------
Tx CLOCKS
Tx signal
estimated
echo
CSO
DSP
__________~A~__________~
CSI
RSO
RSI
RfW
residual
signal
Rx signal
from carrier level detector
:
ST18930/31
TS68930/31
,
RxCLOCKS
1 _____ -
_____ _
MAFE
68950-51-52
Flags
Rx SAMPLING AND RATE CLOCKS
M88TS68951-13
26/30
344
TS68951
APPENDIX 3
DETAILED INPUT/OUTPUT REGISTERS DIAGRAM
Tx signal
Estimated
echo
DSP
Residual
signal
Rx signal
From carrier level detector
M88TS68951-14
R/W
RSO
RS1
Register Accessed
0
0
0
Writing
0
0
0
0
1
1
0
TR1
TR2
ARC
Control Register Addressed by ARC
0
0
0
Reading
1
1
1
1
1
1
0
1
1
1
1
RR1
RR2
CDR
Not Used
27/30
345
TS68951
APPENDIX 4
CONTROL REGISTERS PROGRAMMING
Register
Name
Circuit
Including this
Register
07
RC1
RC2
RC3
RC4
RC5
RC6
RC7
RC8
68952
68952
68051
68950
68951
68951
68952
68952
HB4
HM3
HP2
ATE4
GR5
GDS2
SP5
MPE
28/30
346
Arc Content
(register address)
Register Content
04
03
02
01
HB3 HB2 HB1
HM2 HM1 HS2
HP1
LP2
LP1
ATE3 ATE2 ATE1
GR4 GR3 GR2
GDS1 HDS
SP4 SP3 SP2
SPR AVRE VAL
HR3
HS1
REJ
HR2
HTHR
S/A
EM2
HR1
06
05
GR1
SP1
INIT
REC
EM1
00
07
06
05
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
TS68951
APPENDIX 5
PROGRESSION OF THE DIGITAL AND ANALOG SAMPLES IN THE MAFE
Tx SAMPLING
CLOCK
(Tx CCLK)
l
1ST PERIOD
TR1
REGISTER
TR2
REGISTER
3RD PERIOD
,
f------'
TIME AVAILABLE FOR THE
BUS
(INPUT)
2ND PERIOD
OSP TO WRITE ONE
Tx4
EE4
WRITING
Tx SIGNAL SAMPLE {Tx3) AND
1
ONE ESTIMATED ECHO SAMPLE EE3
3 --------- \~(
(
-(((
))j
-------~ (E~3) »j ---------«<
(T~3)
----"..LJ
~-
(T~4)
(E~4)
cU---!-----'-~
DIGITAL SAMPLE VALID
(EE2)
TT2
--
WRITING
TxS
EES
m---------(\\
(T~5)
,
Tx6
EE6
))j--------
--«< (E~S) »r--------,
)>>---
(EE3)
WRITING
(EE4)
(EES)
REGISTER
TR
REGISTER
D/AC
S/H4
(Tx sample)
S/H3
(estimated echo)
(EE1)
(EE3)
(EE4)
S/H2
(residual signal)
~~~~ING
Rx
(Rx CCLK)
-c-,__~(R",S'C1,-)_ _--1
n
,
!
I
c-,- - - - - - " .
S/H1_-+-,'
'i:
(Rx sample) ~
)
(Rx1)
.
(RS3)
I
c-'- - - - - - " .
Ii:'
)>--------<~
:,' 'i:
~L---,(",RX",2L)~.
(Rx3)
(RS4)
I
j
)
~
: '
I
:(RX4)
)-
A/DC
RT2
REGISTER
,,
RT1
REGISTER
(Rx3)
,(RS1)
I
(RX4)
RR2
REGISTER
(RS1)
BUS
(RS1)
(OUTPUT)
RR1
REGISTER
(Rxl)
BUS
TIME AVAILABLE FOR
(OUTPUT)
AxO SAMPLE (Rx signal)
THE DSP TO READ
(Rxl)
M88TS68950-15
29/30
347
TS68951
APPENDIX 6
FURTHER REFERENCES
1/MAFE CHARACTERIZATION REPORT
This report gives the results of the measurements
performed on the TS68950-51-52 Modem Analog
Front-End (MAFE) chip set.
Chapter 1 describes the configuration and the method used for these measurements.
Chapter 2 comments the results obtained on the two
signal paths of the transmit (Tx) analog front-end
TS68950. i.e the echo path and the Tx signal path.
Similarly chapter 3 gives the results obtained on the
echo path and the receive (Rx) signal path of the Rx
analog front-end TS68951.
Performances obtained on the TS68951 when
using plesiochronous clocks are given in chapter 4.
In this case, the TS68952 clock generator delivers
the main clock and the two sampling clocks to the
Rx analog interface.
2/MAFE EVALUATION BOARD
The MAFE evaluation board is a complete unit for
evaluation of the TS68950/51/52 MAFE chip set.
30/30
348
The MAFE evaluation board is equipped with the
TS68950/51 152 chip set and a phone line interface
facilities.
It can be directly connectable to an external Digital
Signal Processor through a 50-pins connector or
can be linked to the SGS-THOMSON family of digital signal processors emulation-evaluation tools. In
this case, along with the software tools (MACROASSEMBLER, SIMULATOR and LINKER), it provides
a ready-to-use Digital Signal Processor System Interface well adapted to the analog word and high
speed modems development.
3/APPLICATION NOTE
This application note describes the development of
Real-Time Algorithms using the SGS-THOMSON
Digital Signal Processor TS68930 and the MAFE
chip set.
TS68952
MODEM TRANSMIT/RECEIVE CLOCK GENERATOR
• INDEPENDANT TRANSMIT AND RECEIVE
CLOCK GENERATORS WITH DIGITAL PHASE
LOCKED LOOPS
• TRANSMIT DPLL SYNCHRONIZATION ON
EXTERNAL TERMINAL CLOCK OR INTERNAL
RECEIVE CLOCK
• RECEIVE DPLL SYNCHRONIZATION CONTROLLED FROM THE BUS
• FOUR EXTERNAL CLOCKS AVAILABLE, PLESIOCHRONOUS ON TRANSMIT AND RECEIVE CHANNELS:
_ BIT RATE CLOCK
_ BAUD RATE CLOCK
_ SAMPLING CLOCK
_ MULTIPLEXING CLOCK
• DIRECT INTERFACE WITH STANDARD MPU
8-BIT BUS
• LOW POWER CMOS TECHNOLOGY
• AVAILABLE IN DIL OR SURFACE MOUNT
PACKAGE
DESCRIPTION
The TS68952 is a Clock Generator circuit designed
to generate all the necessary clocks frequencies
needed by high-speed modems applications.
The TS68952 copes with all the CCITT recommendations from V.22 to V.33 including full-duplex recommendations. Used in conjunction with the
TS68950 Transmit (Tx) Analog Front-End circuit
and the TS68951 Receive Analog Front-End', it provides a very cheap and efficient interface to digital
signal processing functions in high speed modems.
• The interconnection between the 3 chips of the Modem Analog
Front·end (MAFE) and a DSP is decribed page 11/17.
P
DIP 28
FN
PLCC 28
(Plastic Package)
(Plastic Package)
(Ordering information at the end of the data sheet.)
PIN CONNECTIONS
DIP 28
PLCC 28
D7
D5
D4
D6
D3
D7
D2
D6
D5
D4
D3
D2
D1
E
TxCCLK
E
RiW
D1
R/W
TxCCLK
cso
RxCLK
esa
TxCLK
CS1
RxCCLK
eS1
RxCLK
TxCLK
RSO
RxRCLK
Rsa
AxCCLK
RS1
RxRCLK
RS1
RxMCLK
TO
RxMClK
TO
TxMCLK
TxSCLK
TxMCLK
OGNO
V
+
V+
XTAL1
TxRCLK
XTAL2
elK
M88TS68952·01
November 1988
DGND
XTAL2
TxRCLK
M88TS68952·02
1/17
349
TS68952
BLOCK DIAGRAM
TERMINAL CLOCK
cue
ANALOG
FRONT.eNO~-----I
TxCLK
Tx RCLK
Tx ccue
DSP
CONTROL REGISTERS
RCI - RC2 - RC1 - Rca
RIW
CSI
RSOIRSI
T868930/31
RxCLK
RxRCue
Ax CCLK
OR
R. MCue
8T18930/31
Ax
OPLL
I
I
I
L___ ~_~ ______ ~~ ______ J
OGND
V+
M88TS68952-03
2/17
350
TS68952
PIN FUNCTIONS
Name
01-07
E
Function
Data Bus Inputs to Internal Registers. (DO is not used)
Enable Input. Data are strobed on the positive transitions of this input.
RIW
Read/Write Selection Input. Internal registers can be written when RIW =
mode is only used for Rx analog front-end chip.
CSO-CS1
Chip Select Inputs. The chip set is selected when CSO = 0 and CS1 = 1
RSO-RS1
TO
TxSCLK
Register Select Inputs. Used to select address or control registers.
Transmit Synchronizing Clock Input. Normally tied to an external terminal clock.
When this pin is tied to a permanent logical level, transmit DPLL free-runs or can be
synchronized to the receive clock system.
DGND
Digital Ground = 0 V All digital signals are referenced to this pin.
Crystal Oscillator or Pulse Generator Input
XTAL2
Crystal Oscillator Output
TxRCLK
V+
1.44 MHz Clock output useful for Tx and Rx analog front-end chips.
Transmit Baud Rate Clock Output
Positive Power Supply Voltage = + 5 V ± 5 %
TxMCLK
Transmit Multiplexing Clock Output
RxMCLK
Receive Multiplexing Clock Output
RxRCLK
Receive Baud Rade Clock Output
RxCCLK
RxCLK
TxCLK
TxCCLK
Reading
Test Output. Must be left open.
XTAL1
CLK
o.
Receive Conversion Clock Output
Receive Bit Rate Clock Output
Transmit Bit Rate Clock Output
Transmit Conversion Clock Output
FUNCTIONAL DESCRIPTION
The TS68952 is a digital circuit that synthesises all
the frequencies required to implement synchronous
voice-grade MODEMs from 1200 bps to 19200 bps.
It consists of two clock generators using Digital
Phase Locked Loops (DPLLs). Frequency programming and DPLL updating can be obtained through
four control registers accessed by indirect or cyclical addressing (see p 8117).
analog interface and the TS68951 receive analog
interface.
POWER-UP INITIAL CONDITIONS
Following power-up, the eight transmit and receive
clock outputs are undefined and may deliver any frequencies. Control registers RC1 and RC2 must be
properly programmed to obtain the requested operation.
This circuit is a part of a three chip Modem Analog
Front-End that also includes the TS68950 transmit
Figure 1 : DPLL Lead and Lag.
INTERNAL
2.88 MHz CLOCK
DPLLOUTPUT
LEAD
LAG
M88TS68952-04
3/17
351
TS68952
CLOCK GENERATION
Master clock is obtained from either a crystal tied
between XTAL 1 and XTAL2 pins or an external signal connected to the XTAL 1 pin; in this case, the
XTAL2 pin should be left open. Clock frequency nominal value is 5.76 MHz, but 5.12 MHz and
5.40 MHz frequencies are also specified for particular applications.
The different transmit (Tx) and receive (Rx) clocks
are obtained by frequency division in several counters and output selection through digital mUltiplexers. They can be synchronized on external signal via two independent digital phase locked loops
(DPLL).
TRANSMIT DPLL
As shown figure 1, the TxDPLL operates by adding
or subtracting pulses to a 2.88 MHz internal clock,
with a reference frequency that is a submultiple of
the programmed "rate clock" frequency. This corresponds to phase leads or phase lags of about 350
ns duration, more precisely, two master clock periods.
The TxDPLL can be synchronized on an external
terminal clock tied to TxSCLK pin or on the receive
bit clock RxCLK internally generated from the
RxDPLL. It can also free-run without any phase shift,
when the TxSCLK input is tied to a fixed logical level.
TRANSMIT CLOCKS
The TS68952 delivers four synchronous Tx clocks:
• a bit clock, TxCLK, whose frequency equals the
bit rate ot the modem,
• a baud clock, TxRCLK, whose frequency equals
the baud rate of the modem,
• a conversion clock, TxCCLK, that gives the sampling frequency of the Tx converter (also used by
the Rx converter in echo cancelling applications)
• a multiplexing clock, TxMCLK, usable when several terminals are multiplexed on a single physicallink.
The frequencies of these four clocks are programmable through RC1 and RC2 control registers. Their
cyclical ratio is exactly 1 : 2, except for the 16.8 kHz
4/17
352
frequency whose cyclical ratio is slightly modulated
around 1 : 2, and their relative phase locking is ensured without user intervention, by periodic reset of
the counters.
Immediate phasing of these clocks on the synchronizing external TxSCLK or internal RxCLK clock can
be obtained through bit 7 or RC8 register. The
content of this register is automatically cleared after
phasing completion.
The TS68952 also delivers, on pin CLK, a 1.44 MHz
clock that is synchronous with the Tx clock system
and will be used as the main clock to the
TS68950/51 analog interface circuits.
RECEIVE DPLL
RxDPLL phase shifts are performed by addition and
subtraction of pulses from an internal 1.44 MHz
clock under the control of RC8 register. Two modes
of operation are provided :
• a coarse phase lag whose amplitude has been
loaded into RC7 register, can be controlled by
one bit of RC8 register. This mode is useful for a
fast synchronization of the RxDPLL. The phase
lag is obtained by suppressing a variable number of pulses at the input of the counters,
• a fine phase shift with lead or lag amplitude equal
to two master clock periods, can be controlled by
two bits of RC8. This mode corresponds to normal operation. The phase shifts are obtained by
addition or suppression of pulses as indicated in
figure 1.
RC8 register is automatically cleared when the programmed phase shift is completed. Simultaneous
programming of Tx and Rx control bits of this register has to be avoided.
RECEIVE CLOCKS
The TS68952 delivers four Rx clocks with the same
nominal frequency values as their Tx counterparts:
• a bit clock RxCLK,
• a baud clock RxRCLK,
• a conversion clock RxCCLK,
• a multiplexing clock RxMCLK.
The Rx and Tx output clocks are plesiochronous.
TS68952
BIT CLOCK FREQUENCY PROGRAMMING (Tx and Rx)
RC1 Register
Output Frequency (kHZ)
07
06
05
04
03
02
01
HB4
HB3
HB2
HB1
HR3
HR2
HR1
0
0
0
0
19.2
0
0
0
1
16.8
0
0
1
0
14.4
0
0
1
1
12.0
0
1
0
0
9.6
0
1
0
1
7.2
0
1
1
0
6.4
6.0
Fa =5.76MHz
0
1
1
1
1
0
0
0
4.8
1
0
0
1
3.2
1
0
1
0
2.4
1
0
1
1
1.2
1
1
0
0
0.6
1
1
0
1
0.6
1
1
1
0
0.6
1
1
1
1
0.6
Fa =5.40MHz
Fa = 5.12 MHz
6.4
3.0
Fo ~ crystal oscillator frequency.
RATE CLOCK FREQUENCY PROGRAMMING (Tx and Rx)
RC1 Register
Output Frequency (kHZ)
07
06
05
04
03
02
01
HB4
HB3
HB2
HB1
HR3
HR2
HR1
Fa =5.76MHz
0
0
0
2.4
0
0
1
2.0*
0
1
0
1.6**
0
1
1
1.2
1
0
0
0.6
1
0
1
0.6
1
1
0
0.6
1
1
1
0.6
Fa = 5.40 MHz
Fa = 5.12 MHz
2.133
1.5
Nole: Phase shift frequency of TxDPLL is 600 Hz excepted for (*) 1000 Hz and for (**) 800 Hz.
5/17
353
TS68952
CONVERSION CLOCK FREQUENCY PROGRAMMING (Tx and Rx)
RC2 Register
07
06
05
04
HM3
HM2
HM1
HS2
03
02
HS1 HTHR
Output Frequency (kHZ)
01
-
Fa
=5.76 MHz
Fa
=5.40 MHz
a
a
a
9.6
9.0
1
8.0
7.5
1
a
7.2
1
1
7.2
Fa
=5.12 MHz
8.533
MULTIPLEXING CLOCK FREQUENCY PROGRAMMING (Tx and Rx)
RC2 Register
Output Frequency (kHz)
07
06
05
04
HM3
HM2
HM1
HS2
a
a
a
a
a
a
a
1
a
1
1
1
a
a
a
1
1
4.8
1
1
a
2.4
1
1
1
1.2
03
02
HS1 HTHR
01
-
Fa
c
1
=5.76 MHz
1440
288
12
.
9.6
7.2
Tx SYNCHRONIZATION SIGNAL PROGRAMMING
RC2 Register
07
06
05
04
HM3
HM2
HM1
HS2
03
02
HS1 HTHR
01
Synchronization Signal
-
a
RxCLK
TxSCLK (note 1)
1
Note : 1. TxDPLL free-runs if there is no transition on this input.
TxCLOCK GENERAL RESET
Rca Register (notes 2, 3)
07
MPE
1
06
05
SPR AVRE
a
a
04
03
02
01
VAL
INIT
-
-
a
a
The Tx counters are resetted on the first negative-going
transition of the synchronization signal following MPE
programming to 1.
Next Negative-Going Transition on Synchronization Signal.
Notes: 2. RCB register is cleared after the programmed control operation is completed.
3. INIT bit is only used for test purpose.
6/17
354
TS68952
RxCLOCK PHASE SHIFT PROGRAMMING
RCS Register (note 2)
07
MPE
a
a
a
06
03
02
01
SPR AVRE VAL
INIT
-
a
a
a
1
1
a
a
a
-
1
a
a
05
04
1
Action on RxOPLL
Phase Lag of Programmed Amplitude
Phase Lag of Two 5.76 MHz Master Clock Periods
Phase Lead of Two 5.76 MHz Master Clock Periods
RxCLOCK PHASE SHIFT AMPLITUDE PROGRAMMING
RC7 Register
07
06
05
04
03
02
01
SP5
SP4
SP3
SP2
SP1
-
-
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
0
a
a
a
a
0
0
a
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
a
0
a
0
0
a
a
a
1
1
1
1
1
1
1
1
1
1
1
1
a
a
a
a
1
1
1
1
a
a
a
0
1
1
1
1
0
a
a
a
1
1
1
1
1
1
a
a
1
a
1
a
1
1
1
0
a
1
1
0
a
1
1
0
a
1
1
a
a
a
a
a
a
1
1
a
a
1
1
0
a
1
1
1
a
1
1
a
1
1
a
1
1
0
1
0
1
a
1
0
1
0
1
a
1
Phase Shift in Degrees
Number of Master Clock
Pulses Suppressed
1200 Bauds' 1600 Bauds
1.5
3
4.5
6
7.5
9
10.5
12
13.5
15
16.5
18
19.5
21
22.5
24
22.5
45
67.5
90
112.5
135
157.5
180
202.5
225
247.5
270
292.5
315
337.5
360
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
30
60
90
120
150
180
210
240
270
300
330
360
20
40
60
80
100
120
140
160
180
200
220
240
260
280
300
320
300
600
900
1200
1500
1800
2100
2400
2700
3000
3300
3600
3900
4200
4500
4800
C) 2400 bauds: multiply by two. 600 bauds: divide by two.
7/17
355
TS68952
DATA BUS CONTROL
Six signals control the access from the bus to the internal registers according to the table and the timing
diagram given below. Control registers are written
using an indirect addressing mode where the interR/W
CSO
CS1
RSO
RS1
0
0
1
1
0
0
0
1
1
1
E
S
_I
nal address is stored in the 3 bit ARC register. After
each write operation to a control register, the ARC
register value is automatically increased by one.
This allows cyclical addressing of the eight registers
of the MODEM chip set.
Accessed Register
Address Register ARC
Control Register whose Address is in ARC
BUS TIMING DIAGRAM
~~~: ~_~_.
-Jx. .__________________~X. ____
CS_l_ _
DATA BUS
01 :07
ENABLE
E
DATA STROBING
M88TS68952-05
DATA FORMAT
Oata Loaded in ARC
Addressed Register
07
06
05
ARC3
ARC2
ARC1
0
0
0
RCI
0
0
1
RC2
1
1
0
RC7
1
1
1
RCa
ABSOLUTE MAXIMUM RATINGS
Parameter
V· Supply Voltage to DGND Ground
Voltage at any Input or Output
Current at any Output
Min.
Max.
Unit
- 0.3
7
V
DGND - 0.3
V· + 0.3
V
- 20
20
mA
Power Dissipation
Operating Temperature Range
Storage Temperature Range
8/17
356
500
mW
0
70
- 65
+ 150
°c
°c
TS68952
OPERATING RANGE
V·
Ambient Temperature
+ 5.0 V ± 5 %
ELECTRICAL OPERATING CHARACTERISTICS
Unless otherwise noted, electrical characteristics are specified over the operating range. Typical values
are given for V· = 5.0 V and T amb = 25 'C
Symbol
Parameter
Value
Test Conditions
Min.
Typ.
Max.
Unit
Power Dissipation
1+
Positive Supply Current
5.0
mA
Digital Interface
VIL
Input Low Level Voltage
VIH
Input High Level Voltage
0.8
2.2
IlL
Input Low Level Current
DGND:;; VI :;; VIL
IIH
Input High Level Current
VIH
VOL
Output Low Level Current
10
=
VOH
Output High Level Current
10
=-
min:;;
max
VI :;; V+
-10
10
~
-10
10
~A
2.5 mA
0.4
2.5 mA
V
V
2.4
V
V
Crystal Oscillator Interface
VIL
Input Low Level Voltage
VIH
Input High Level Voltage
IlL
Input Low Level Curent
DGND :;; VI :;; VIL
IIH
Input High Level Current
VIH
1.5
3.5
min:;;
V
. 15
max
V
~
VI:;; V+
15
~
TIMING CHARACTERISTICS
Symbol
Parameter
Value
Test Conditions
Min.
Typ.
Max.
Unit
Data Bus Access
tSCE
Control Signals Set· up Time
CSO, CS1, RSO, RS1, R/W to E
40
ns
tHCE
Control Signals Hold Time
CSO, CS1, RSO, RS1, R/W to E
10
ns
tSOI
Data-in Set·up Time
D1 : D7 to E
120
ns
tHOI
Data·in Hold Time
D1 : 07 to E
10
tWE
Enable Signal Low Level Width
E
ns
180
ns
Clock Wave forms
Main Clock Period
XTAL1 Input
150
tWCL
PC
Main Clock Low Level Width
XTAL1 Input
50
tWCH
50
173.6
ns
ns
Main Clock High Level Width
XTAL1 Input
tRC
Main Clock Rise Time
XTAL1 Input
50
ns
tFC
Main Clock Fall Time
XTAL1 Input
50
ns
toc
Clock Output Delay Time
All Clock Outputs CL
pF
500
ns
tTC
Clock Output Transition Time
All Clock Outputs
pF
100
ns
= 50
CL = 50
ns
9/17
357
TS68952
2.2 V
CONTROL SIGNALS
CSO.CSI
RSO,RSI
RiW
O.B V
tSCE
2.2 V
ENABLE SIGNAL
E
l-_t.=S=.OI--I
-t----t..
tHDI
2.2 V
INPUT
DATA
VALID
DATA BUS
01: D7
O.B V
M88TS68952-06
PC
tWCH
,
V 3.5V
MAIN CLOCK
INPUT
XTAL 1
1.5 V
J
CLOCK OUTPUTS
19 CLOCKS}
~
/
tRC- t-
t-
tWCL
tFC
II
V
~
J
tDC
,V
~
J
-
f--.
1\
2.2V
0.8 V
t--
tTC
M88TS68952-07
10/17
358
TS68952
APPLICATIONS INFORMATIONS
MODEM ANALOG FRONT-END CHIP SET (TS38950/51/52).
Tx ANALOG INTERFACE ~A.:..T:..::O,--_..,
TS68950
EEO
CTRL
DSP
8 BITS
T. AND Rx
CLOCKS
TS68930/31
ST18930/31
TS68952
o
TS68951
LEI
~
TXANDRXI~~~~~~~__~~~~===3~~
L-....,r----....,r--~ CLOCKS L.:
MBBTS68951-06
Notes:
1.m, Digijal ground.
.¢.
Analog ground.
2. In some cases, external-user circuitry may induce power-up sequency latch-up problems that can be efficiently avoided using
ST BAT43 schottky small signal diodes as follow:
vee
ORDERING INFORMATION
BAT43
GND
Part Number
BAT43
VBB
TS68952CP
TS68952CFN
Temperature
Range
Package
o to + 70°C
o to + 70°C
DIP28
PLCC28
M88TS68951-09
11/17
359
TS68952
PACKAGE MECHANICAL DATA
CB-132 - 28 PIN - PLASTIC DIP
e=2.54
4.57max.
16,1 max.
~
.k
..
!-
0.3
I
,.
Datum
..!
(11
..
15.24
(2)
:
Nominal dimension
(2) True geometrical position
14
28
PINS
CB-520 - 28 PIN - PLASTIC LEADLESS CHIP CARRIER
11430
~
0661
0,812
...Q...QL
min.
12/17
360
0331
0,533
28 Outputs
TS68952
APPENDIX 1
INTERFACE BETWEEN DSP AND MODEM ANALOG FRONT-END (TS68950/51/52)
Tx SAMPLING AND RATE CLOCKS
Flags
I-------L------~
Tx CLOCKS
Txn
Tx signal
estimated
echo
CSO
DSP
CS1
RSO
RS1
RIW
residual
signal
Rx signal
from carrier level detector
RxCLOCKS
ST18930/31
TS68930/31
MAFE
68950-51-52
Flags
Rx SAMPLING AND RATE CLOCKS
M88TS68950-13
13/17
361
TS68952
APPENDIX 2
DETAILED INPUT/OUTPUT REGISTERS DIAGRAM
Tx signal
Estimated
echo
DSP
Residual
signal
Rx signal
From carrier level detector
M88TS68950-14
RIW
RSO
RS1
Register Accessed
0
0
0
Writing
0
0
0
0
1
1
0
TR1
TR2
ARC
Control Register Addressed by ARC
0
0
0
Reading
1
1
1
1
1
1
0
14117
362
1
1
1
1
RR1
RR2
CDR
Not Used
TS68952
APPENDIX 3
CONTROL REGISTERS PROGRAMMING
Register
Name
Circuit
Including
this Register
ARC Content
(register address)
07
06
05
04
03
02
01
RC1
68952
HB4
HB3
HB2
HB1
HR3
HR2
HR1
RC2
68952
HM3
HM2
HM1
HS2
HS1
HTHR
RC3
68951
HP2
HP1
LP2
LP1
REJ
S/A
RC4
68950
ATE4
ATE3
ATE2
ATE1
EM2
RC5
68951
GR5
GR4
GR3
GR2
GR1
RC6
68951
GDS2 GDS1
HDS
RC7
68952
SP5
SP4
SP3
SP2
SP1
RC8
68952
MPE
SPR
AVRE
VAL
INIT
Register Content
DO
07
06
05
0
0
0
0
0
1
REC
0
1
0
EM1
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
15/17
363
TS68952
APPENDIX 4
PROGRESSION OF THE DIGITAL AND ANALOG SAMPLES IN THE MAFE
Tx SAMPLING
CLOCK
(Tx CCLK)
l
1ST PERIOD
2ND PERIOD
c
1-----
BUS
(INPUT)
RE~~~ER
RE~I~~ER
3RD PERIOD
WRITING
3-......... «!,
3· .... \\\
Tx4
EE4
WRITING
WRITING
,
))'r
,
Tx5
EE5
(Ti5)
//'r
Tx6
EE6
»t .. --...
»t
TT2
REGISTER
TR
REGISTER
D/AC
S/H4
(Tx sample)
S/H3
(estimated echO)_~_-,(",EE",1CL)_-!. ' -_ _~'-,(",EEC"2".)_ _ _.J
S/H2
(residual signal)
:
(RS2)
~
L--J
(RXS~~:Ple) ~
(Rx1)
(EE3)
(EE4)
,NOLOG SAMPLE VALID
(RS1)
RX~~~~NG~
(Rx CCLK)
==;\,
AZ
(RS3)
J
ji
: L-
)~
(Rx2)
j
I
-l~ri-(R-X-3)-)-----l~'~[(-RX-4-)~)---I
f 7 c- - -
)-_ _ _
(RS4)
f.-c- - ; - - - - - - '
A/DC
RT2
REGISTER
RT1
REGISTER
(Rx4)
RR2
REGISTER
(RS3)
BUS
(RS3)
(OUTPUT)
RR1
REGISTER
BUS
TIME AVAILABLE FOR
(OUTPUT)
RxO SAMPLE (Ax signal)
THE DSP TO READ
M88TS68950·15
16/17
364
TS68952
APPENDIX 5
FURTHER REFERENCES
1/MAFE CHARACTERIZATION REPORT
This report gives the results of the measurements
performed on the TS68950-51-52 Modem Analog
Front-End (MAFE) chip set.
Chapter 1 describes the configuration and the method used for these measurements.
Chapter 2 comments the results obtained on the two
signal paths of the transmit (Tx) analog front-end
TS68950. i.e the echo path and the Tx signal path.
Similarly chapter 3 gives the results obtained on the
echo path and the receive (Rx) signal path of the Rx
analog front-end TS68951.
Performances obtained on the TS68951 when
using plesiochronous clocks are given in chapter 4.
In this case, the TS68952 clock generator delivers
the main clock and the two sampling clocks to the
Rx analog interface.
The MAFE evaluation board is equipped with the
TS68950/51 152 chip set and phone line interface facilities.
It can be directly connectable to an external Digital
Signal Processor through a 50-pins connector or
can be linked to the SGS-THOMSON family of digital signal processors emulation-evaluation tools. In
this case, along with the software tools (MACROASSEMBLER, SIMULATOR and LINKER), it provides
a ready-to-use Digital Signal Processor System Interface well adapted to the analog word and high
speed modems development.
3/APPLICATION NOTE
This application note describes the development of
Real-Time Algorithms using the SGS-THOMSON
Digital Signal Processor TS68930 and the MAFE
chip set.
2/MAFE EVALUATION BOARD (EFRMAFE)
The MAFE evaluation board is a complete unit for
evaluation of the TS68950/51/52 MAFE chip set.
17/17
365
TS75320
DIGITAL ECHO CANCELLER
• SIMPLIFIED INTERFACE CIRCUITRY FOR
FLEXIBLE ADAPTION TO A WIDE RANGE OF
V.32 CONFIGURATIONS
• DOVETAILED HARDWARE AND FIRMWARE
CONNECTION WITH TS68950/1/2 MODEM
ANALOG FRONT-END CHIP SET
• KEY COMPONENT IN THE ADVANCED
TS7532 V.32 MODEM
• 16 msec OF ECHO PATH IMPULSE
RESPONSE IN THE NEAR END AND IN THE
FAR-END CANCELLERS
• 1.14 SEC OF CHANNEL DELAY (two satellite
hops) IN FAR-END ECHO CANCELLER.
• 10Hz OF FREQUENCY OFFSET IN FAR-END
ECHO PATH
• MEETS OR EXCEEDS THE REQUIREMENTS
OF CCITT RECOMMENDATION V.32
P
DIP-48
(Plastic Package)
(Ordering Information at the end of the datasheet)
PIN CONNECTIONS
04
03
05
02
06
01
DO
07
08
09
010
011
012
BE3
BE4
BSO
BSI
BS2
6
9
39
DESCRIPTION
VCC
015
AID
The TS75320 is a high performance voiceband data modem echo canceller implemented on a single
chip using advanced digital signal processing technology. Using sophisticated adaptive algorithms,
the TS75320 realizes the high precision cancellation of near-end and far-end echoes, even in the presence of frequency offset in the far end echo.
CLKOUT
The residual cancellation levels and convergence
rates of the TS75320 meet or exceed the demanding requirements of high performance V.32 modems.
RS
The TS75320 is ideally suited for high performance
low-cost integrated V.32 solutions.
August 1988
All
014
VSS
XTAL
EXTAL
Ri5
WR
14
34
A06
A05
17
A04
AD3
SRIW
SiSS
CS
REm
IRQ
A9
A8
A07
A02
AOI
27
ADO
BE5/BA
BE6/0TACK
M88TS75320-01
1/12
367
TS75320
BLOCK DIAGRAM
Figure 1 : Shows a Configuration for a V.32 Modem utilizing the TS75320 with the
TS68950/51/52 MAFE Chip Set.
1 - - - -__
TO DAA
....- - - - FROM DAA
(\
M88TS75320-02
2/12
368
~ SGS·1HOMSON
At..,
I fiIIilUICOOI!I!.ma:vGl@ImU©1l!
T575320
PIN DESCRIPTION
LOCAL INTERFACE
Pin
Name
Pin
D (0:15)
Type
Function
45-48
1-11
1/0
Data
Bus
A (8:11)
35.37.39
0
Address
Bus
0
0
0
N°
RD
17
WR
18
CLKOUT
16
Read
Write
Clock
Output
Description
D(0:15) Data Bus
High Order Addresses for Local Interface
Transfer Data Read
Transfer Data Write
The frequency of CLKOUT is one half the frequency of the input
clock or crystal.
SYSTEM INTERFACE
Pin
Name
Pin
AD (0:7)
Type
Function
Description
27-34
110
System Data Bus
or Local Address
Bus
The data exchanges between the processor and a master
via a mailbox is the function of this bus. It is also used to
generate the addresses of an external RAM.
CS
21
I
Chip Select
Used by a Master to Gain Access to the Mailbox and
Systern Bus
RS
22
I
Register Select
Used by a Master to Gain Access to the Mailbox and
System Bus
SDS
20
I
System Data
Strobe
Synchronizes the Transfer on the System Bus
SRIW
19
I
System
ReadlWrite
Indicates the Current System Bus Cycle State
DTACK
25
0
Data Transfer
Acknowledge
Indicates that the processor has recognized it is being
accessed.
BA
26
Indicates Availability of System Bus to Master
24
0
0
Bus Available
IRQ
N°
Interrupt Request
Handshake signal sent to the master gain access to the
mailbox.
OTHER PINS
Pin
Name
Pin
EXTAL
Description
Type
Function
15
I
Clock
Crystal Input Pin for Internal Oscillator or Input Pin for External
Oscillator
XTAL
14
I
Clock
Together with EXTAL it is used for the external 25 MHz crystal.
VCC
38
I
Power
Supply
VSS
13
I
Ground
RESET
23
I
Reset
N°
3/12
369
TS75320
FUNCTIONAL DESCRIPTION
PERFORMANCE SUMMARY
The TS75320 performance figures below are obtained with analog front-end D/A converters with integral linearity of 12 bits or better, such as the
TS68950.
• Near-end echo cancellation: > 55 dB
With a near-end echo level of - 10 dBm at the receiver input, in the absence of a far-end signal
and of a far-end echo, the residual echo level is
below - 65 dBm.
• Combined near-end and far-end echo cancellers:
For a typical receive level of -20 dBm and far-end
echo smaller than -28 dBm the received signal
to residual echo ratio is better than 24 dB even in
the presence of up to 10Hz of frequency offset in
the far-end echo.
• The signal to residual echo ratio is better than 21
dB even for receive levels as small as -40 dBm,
provided that the far-end echo is 8 dB below the
received far-end signal.
• The far-end echo channel delay can be as large
as1.14s.
• Convergence Time : meets or exceeds CCITT
V.32 handshake requirements.
ECHO CANCELLER OPERATION
The principal task of the echo canceller is the determination by means of adaptive algorithms, of the
coefficients of digital filters and phasing processors
that will generate a modem receiver input free of
near-end or far-end echoes. The signals processed
by the echo canceller are the cancellation error at
the receiver input and the V.32 date sequence being
transmitted. These signals will normally be available in the appropriate format in a digitally realized
modem.
4/12
HARDWARE INTERFACE
The TS75320 echo canceller is configured as an essentially self-contained digital peripheral interfaced
to a host microcontroller or to a host digital signal
processor through an 8-bit system bus. The bus interface dovetails with the control bus of the TS68930
digital signal processor. Straightforward interconnection to other processors or to peripheral circuits
is realized by wirtue of an asynchronous mailbox
that is readily controlled by means of a flexible
handshake protocol.
The system bus is also used for addressing the echo
canceller external RAM, during which time it is not
available to the host controller. Data transfer to the
echo canceller's RAM is effected through the 16-bit
data bus.
The timing of all communications with the host is determined by the echo canceller.
Data for transmission to the host is loaded into the
TS75320 three-byte wide ROUT shift register. The
communication process is effected by means of the
mailbox transfer protocol. Data for transmission
from the host is stored in the TS75320 RIN register,
which is also three bytes wide.
The operation of the mailbox transfer protocol is
described schematically in the flow chart in Figure
2.
,'9,/ SGS·ntOMSON
"],
370
The echo canceller hardware and firmware have
been designed for ease of interface with a general
purpose DSP or microprocessor and require minimal interaction with the modem. In this section we
describe the hardware and software interfaces to
the TS75320.
fiIiIU©IR@~IiI@OOUIli!
TS75320
Figure 2 : Mailbox Handshake Protocol.
TS75320
HOST
MAILBOX IS AVAILABLE
Asserts IRO. RDYOIN
I
a
Detects IRQ =
(one of its external test conditions I
Applies CS =0,
AS = 0, sRiii= 1, S6S =0
I
detects
CS = 0
t_
RS = 0
!.The processor is put in Halt state
~nd releases the system bus
+TR5
Negates
I
Detects IRO
MAILBOX ACCESS
(3 reads and 3 writes maximuml
END OF MAILBOX ACCESS
Applies CS = 0, RS = 1
t
If pseudo-slave [
Internal Halt disappears. The processor
resumes program and
takes back control of the bus
+
negates RDYOIN
While the mailbox protocol is in IKQgress only, the
host may deselect the TS75320 (CS = 1) to use the
system bus to communicate with other peripherals.
At all othertimes, the system bus is under the control
of the TS75320 and it is therefore essential that the
connection of the bus to the host be tri-state at those
times.
5/12
371
TS75320
FIRMWARE INTERFACE
The echo canceller firmware is designed in the first
instance for V.32 modem applications, and therefore operates at a Baud rate of 2400 symbols per
second. The sampling rate is 7200 per second, i.e.
three samples per Baud interval.
In the period of one Baud interval, the echo canceller generates three echo estimates, one for each of
the three receiver samples, and it requires the input
of the three corresponding echo cancellation errors.
The echo estimates and the cancellation errors are
both 16 bit quantities. The echo canceller requires
also the input of the complex-valued V.32 format
current symbol from the transmitter, this is the reference signal for the computation of the echo estimates. By virtue of the V.32 constellation
requirements, three bits are sufficient for the representation of the real and imaginary parts, respectively. Hence, the transfer of this signal is effected
with a single byte (the four MSBs for the real part,
the four LSBs for the imaginary part).
and for the cancellation errors except that there is
no need for the transmitted symbol to be transferred more than once per baud interval.
Particular care must be taken, however, to ensure
that the modem does not hold the echo canceller
during the mailbox transfer for more than the time
required for the data transfer. Otherwise problems
relating to cycle duration may arise.
INITIALIZATION
The echo canceller is initialized by first asserting the
reset signal (RESET = 0) for at least 640 ns. The
TS75320 will then automatically clear its internal
status and filter coefficients. It will then wait for a
mailbox transfer consisting of the following three
hexadecimal bytes: AA AA 00. This will indicate the
beginning of echo canceller configuration.
Three mailbox exchanges are required per Baud interval to transfer the data. Once an echo estimate
has been computed, it is stored in the TS75320
ROUT register (3-byte wide). The LSB and MSB are
stored in the first and second bytes, respectively.
The first mailbox transfer after the configuration
bytes must contain the far-end echo round trip delay expressed in number of Baud periods. This number must be smaller than 3000 (1.25 seconds). The
echo canceller will interpret the first two bytes in its
RIN register as the round trip delay, LSBs followed
by MSBs, right justified. If the third byte is 0, the farend echo canceller is disabled. If it is 1, the far-end
canceller is enabled.
The TS75320 then initiates a mailbox transfer during which the host reads the echo estimate (LSBs
followed by MSBs) and stores the two bytes for the
transmitted symbol. The mailbox transfer operation
is identical for the second and third echo estimates.
The near-end echo canceller convergence is enabled by the following 3 bytes in the RIN register of
the TS75320 : AA AA 01. If the far-end echo canceller is enabled it wil,1 start adapting automatically
once the near-end echo canceller has converged.
ABSOLUTE MAXIMUM RATINGS
.
Symbol
Vee
Vin*
Value
Unit
Supply Voltage
Parameter
- 0.3 to 7.0
V
Input Voltage
- 0.3 to 7.0
V
o to 70
°C
°c
TA
Operating Temperature Range
T stg
Storag'e Temperature Range
- 55 to 150
• Witl1 respect to Vss.
Stresses above tI10se hereby listed may cause permanent damage to the device. The ratings are stress ones only and functional operation of
the device at these or any conditions beyond those indicated in the operational sections of tI1is specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Standard MOS circuits handling procedure should be used to avoid
possible damage to the device.
6/12
372
Gi
SGS·THOMSON
~I Ii!iIB©IIIl@[;J!.I<@'ii'IIIl©OO1I©1!!
TS75320
DC ELECTRICAL OPERATING - CHARACTERISTICS
Vcc = 5.0 V ± 5 %, Vss = 0, Tamb = 0 to + 70 'C (unless otherwise specified)
Symbol
Min.
Typ.
Max.
Unit
Vee
Supply Voltage
Parameter
4.75
5
5.25
V
VIL
Input Low Voltage
- 0.3
-
0.8
V
VIH
I nput High Voltage
2.4
-
Vee
V
lin
I nput Leakage Current Except EXTAL
-10
-
10
IJA
Ii
Input EXTAL Current
- 50
50
IlA
V
VOH
Output High Voltage (iload = - 300 IlA)
2.7
-
VOL
Output Low Voltage (iload = 3.2 mAl
-
-
0.5
V
Power Dissipation
-
1.5
-
W
-
10
-
pF
- 20
-
20
IJA
Max.
Unit
160
ns
PD
Gin
Input Capacitance
ITSI
Three State (off state) Input Current
-
AC ELECTRICAL SPECIFICATIONS - CLOCK AND CONTROL PINS TIMING
(Vee
=
5.0V ± 5%, Tamb
=
O' to +70'C ; see figure 3)
Output load = 50 pF + De characteristics load
Reference levels:
VIL : 0.45 V
VIH : 2.4 V
VOL: 0.45 V
VOH: 2.4 V
Symbol
Parameter
tr, tf s 5 ns for input signals
Min.
Typ.
tcex
External Clock Cycle Time
tfex
External Clock Fall Time
5
ns
t rex
External Clock Rise Time
5
ns
tcoh
EXTAL to CLKOUT High Delay
25
teol
EXTAL to CLKOUT Low Delay
25
t reD
CLKOUT Rise Time
10
ns
tfco
CLKOUT Fall Time
10
ns
tdsl
CLKOUT to DS, RD, WR Low
5
ns
tdsh
CLKOUT to DS, RD, WR High
5
ns
tse
Control Inputs Set-up Ti~ _
(BSO ... BS2, BE3 ... BE6, Reset, Halt)
20
ns
the
Control Inputs Hold Time_ _ _ _
(BSO ... BS2, BE3... BE6, Reset, Halt)
10
ns
tdle
CLKOUT to Control Output Low (IRQ, BA)
50
ns
tdhe
CLKOUT to Control Output High (BA, IRQ)
50
ns
40
ns
ns
7/12
373
TS75320
Figure 3 : Clock and Control Pins Timing.
tcex
EXTAL
CLKOUT
INTL
M88TS75320-03
Notel: t, ~ Instruction cycle time ~ 410".
INTERNAL CLOCK OPTION
A crystal oscillator can be connected across XTAL and EXTAL. The frequency of CLKOUT : tc/2 is half the
crystal fundamental frequency.
Figure 4.
C1
EXTAL
TS75320
1:1----1
=
T :1---4
C1. C2 lypical value = 10 pF
C2
XTAL
M88TS75320-{)4
8/12
374
TS75320
ELECTRICAL CHARACTERISTICS - LOCAL BUS TIMING
(Vee = 5.0 V ± 5 %, Tamb = 0 'C to + 70 'C ; see figure 5)
Min.
Max.
Unit
1/5tc-15
1/2 tc
ns
Address Hold Time
10
Data Set-up Time, Write Cycle
25
-
ns
tDHW
Data Hold Time, Write Cycle
10
-
ns
tDZW
SDS High to Data High Impedance, Write Cycle
-
40
ns
tDSR
Data Set-up Time, Read Cycle
20
ns
tDHR
Data Hold Time, Read Cycle
tARW
Address Valid to WR, SDS, RD Low
-
Symbol
Parameter
tpw
RD, WR, SDS, Pulse Width
tAH
tDSW
5
1/2tc-40
ns
ns
ns
Figure 5 : Local Bus Timing Diagram.
ADDRESSES
A8·A 11 .ADO-AD?
____~~______________-+~c
RD,DS,WR
\
I
ARW
I
ARW
RNY
DO-D15
DATA OUT
/
\I~------------~/
IDH." 1 DZ":"I
IIIII
\\\\\
DO·D15
DATA IN
DATA OUT
\\~
III
DATA IN
M88TS75320-05
Gi
SGS·ntOMSON
~I ~U©IiI@~~IEii'II@11!]U©$
9/12
375
TS75320
AC ELECTRICAL SPECIFICATIONS. SYSTEM BUS TIMING
01 cc = 5.0 V ± 5 %, Tamb = 0 "C to + 70 "C ; see figure 6)
Symbol
Min.
Max.
Unit
tspw
SDS Pulse Width
60
ns
tSAw
SRIW, CS, RS Set-up Time
20
tSAH
SRIW, CS, RS Hold after SDS High
5
-
tSDSR
Data Set-up Time, Read Cycle
20
-
ns
tSDHR
Data Hold Time, Read Cycle
5
-
ns
tSDSW
Data Set-up Time, Write Cycle
-
35
ns
tSDHW
Data Hold Time, Write Cycle
10
50
ns
tDSLDT
SDS Low to DTACK Low
50
ns
tDSHDT
SDS High to DTACK High'
-
50
ns
tDSHIR
SOS High to IRQ High
-
50
ns
tSDZW
SDS High to Data High Impedance, Write Cycle
-
40
ns
Parameter
ns
ns
• DTACK is an open drain output test load include Rl ~ 890l< at Vee.
Figure 6 : System Bus Timing Diagram.
tspw
SDS
\
tSAW
SRIW,CS
RS
IRWL,GSL.RSL]
~
J
t SDSR
ADO-AD?
DATA IN
[DOH-D7H]
/
DATA OUT
tSDZW
~<
I tSDH.:'
<<<
t DSLDT
DTACK
tSD)-lR
DATA IN
'-.,
tpSDSW
ADO-AD?
r--
DATA OUT
t>
>'>~
tDSHDT
;--
\
1\
/
tDSHIR
IRQ
M88TS7532o-06
10/12
376
TS75320
TYPICAL PERFORMANCE
T875320 : Residual Echo without Far-end Signal.
- 70
Residual Echo (dBm).
/"
- 60
- --
V-
r 0 far en echo
/
- 50
/
- 40
- 20
- 30
- 50
- 40
- 60
Far End Echo (dBm).
M88TS7532()-07
T875320 : Residual Echo versus Far End Signal (with far-end echo level 8dB below far-end
signal).
Residual Echo (dBm).
-70
, .. .. .¥'
,
#~
_40
_30
I~"--
... .~~.p
. '.~
.-:'-;;'/
; ....
.;
-
_20
-30
Far End Signal (dBm).
-40
M88TS7532()-08
11/12
377
TS75320
ORDERING INFORMATION
Part Number
Temperature RAnge
Package
TS75320CP
o °C to + 70°C
48 Pin Plastic Dil
PACKAGE MECHANICAL DATA
48 PINS - PLASTIC DIP
(2)
15
(1)
Nominal dimension
(2) True geometrical position
63.Smax.
12/12
378
14
(1)
Gi
SGS·T1IOMSON
~I IliiU©!fJ@oo!'l<©"ii"!fJ©OOO©:;
48
Pins
MODEM APPLICATION SUPPORT
379
EFRMAFE
TS68950/51/52
MODEM ANALOG FRONT END EVALUATION BOARD
• EVALUATION BOARD FOR TS68950/51/52
MAFE.
_ 34 TEST POINTS AVAILABLE
• EASY TO USE FOR HIGH SPEED MODEM DEVELOPMENT UP TO 19200 BPS
_ THREE USER MODES AVAILABLE
_ DIRECTLY CONNECTABLE TO THE SGS
THOMSON MICROELECTRONICS DSP
HARDWARE TOOLS WITH A 84-PGA EMULATION PROBE
_ DIRECTLY CONNECTABLE TO AN EXTERNAL PROCESSOR THROUGH A 50-PIN
CONNECTOR
• MASTER CLOCK (5.76MHz) PROVIDED BY AN
ON-BOARD CRYSTAL WHICH CAN BE REPLACED BY AN EXTERNAL CLOCK.
• MODEM LINE INTERFACE OR GENERAL
PURPOSE WIRE WRAPPING AREA AVAILABLE
The simple analog loop mode loops the transmitted
signal output on the received signal input after an
attenuation of the transmitted signal. It permits auto
test of the local reception.
DESCRIPTION
+ 5V ± 5% (0.5A). Additional
The double analog loop mode loops the transmitted
signal output on both the received signal input and
the analog gain amplifier 2 input. It allows the test
of the reception while the modem receive analog interface eliminates the transmitted signal by filtering
(split band modem) or echo cancelling (modem with
echo canceller).
MASTER CLOCK
The on-board Q1 (5.76MHz) is needed by the
TS68952 to generate the different clocks by frequency division. It can be replaced by an external
clock.
POWER REQUIREMENTS
The EFRMAFE is a modem analog front end board
equipped with the TS68950/51/52 MAFE chip set
(ADC, DAC, filters, AGC amplifier, clock generator)
and the phone line interface circuitry.
It offers a very simple and straightforward means of
interfacing the SGS THOMSON DSP to analog signals. It is especially well suited for development
and debugging of modem applications designed to
meet CCITT V.22, V.26, V.27, V.29, V.32, and V.33
recommendations as well as the Bell 212A, 208 and
209 standards. The EFRMAFE can be linked to the
SGS THOMSON DSP tools. Along with the software
library, it provides a ready to use digital signal processing system interface well adapted to the analog
world.
± 12V is required only
if the operational amplifier (IC6) is included in the
transmission chain between the TS68950 and the
TS68951 devices.
ORDER CODES
EFRMAFE
Note : The EFRMAFE board is delivered with the
following documentation:
- TS68950/51 152 Data Sheet
- EFRMAFE user's manual
- Application note AN076 (development of Real
Time Algorithm using the TS68930/31 DSP and the
MAFE)
- Characterization report (MAFE)
FUNCTIONAL DESCRIPTION
In normal mode the EFRMAFE is a real modem analog front end.
December 1988
·1/4
381
r
(,)
I~
'"
~
»
S4
<
0
c:
S1
S2
-I
-12V
»
z
TR1
c
en
IJ
S3
~
D~
tJ<~"~
FOR
TS 68931
EVALUATION
PROBE
14
I::;
......
..
~CI)
TP2
Ii!
~o
~!I
~o
llz
I
D~'
S/R4
TP3
oDOW
+/-5V
Power
Supply
C13
N
g;
:g
(fJ
r-
WRAPPING
AREA
IC3
c::::=:::J
C17
;;:
CD
CD
160mm
,.,m
JJ
;;:
,.,»
S8
TP6
I
o
S7
M88EFRMAFE-Ol
m
STRAPS CONFIGURATION
JJ
»
0
0
m
en
en
"'
Cl.
r-
S/R2
@CI)
+5VO
-I
»
"tJ
en
RESISTOR
~
ovO
~I:'I
lines
SUPPORT
';;;" gil ,Q:n 6 [J
~CI)
Phone
m
"T1
:c
s:
J>
"T1
m
EFRMAFE
TEST POINTS
34 test-points are available on the board. According to the layout, they have been divided in 9 groups:
DESIGNATION
TESTED POINTS
TP1
2 Test-points:
1: V-.
TS68951
2: EEl
TP2
1 Test-point:
1 : V+
TS68952
TP3
1 Test-point:
1: DGND
TS68951
TP4
6 Test-point:
1 : V+
2: AGC2
3: CD1
TS68951
4: LEI
5: RAI
6:AGND
TP5
2 Test-points:
1: DGND
TS68950
2: V-
TP6
3 Test-points:
1 :TO
2 : TxSCLK TS68952
3:DGND
TP7
5 Test-points:
1 : V+
2: EEO
3: ATO
TS68950
4: EXI
5:AGND
TP8
9 Test-points:
1 : D5
2: D6
Data
3: D7
4:E 5: R/W
Control
6: CSO
7: CS1
8 :RSO
9: RS1
TP9
5 Test-points:
1 : D4
2: D3
3: D2
Data
4: D1
5: DO
COMMENTS
Analog Part of the TS68951
Analog Part of the TS68950
N.B. These test-points have been chosen to observe the supply voltages at the terminals of each MAFE circuit, control
and data buses, and analog inputs/outputs.
3/4
383
EFRMAFE
POWER SUPPLIES
The board requires the following power supplies:
+5V
OV
-5V
J5 connector
+12V
OV
-12V
J3 connector
N.B. The ± 12V supplies are required only if the IC6 operational amplifier is included in the transmission chain between the
TS68950 and the T868951 circuits. The grounds of the + 5V and + 12V are separated. If using IC6, connect them together.
4/4
384
Gi
SCiS·nlOMSON
~I IillU©OOIU©'ii'Iii!@OOU©$
TS7514EVA
TS7514 EVALUATION BOARD
• V.23 STANDARD OPERATION
• SELECTABLE 75/1200 OR 1200/75 bps (half
duplex on 2 wire)
• DTMF DIALLING CAPABILITY
• ANALOG TEST LOOP CAPABILITY
• TONE RING GENERATION AND DETECTION
• TWO PROGRAMMING WAYS:
MANUAL (switches)
AUTOMATIC (V.24/RS232 junction)
• ALL PROGRAMMABLE FUNCTIONS:
_ TRANSMIT/RECEIVE LEVELS
_ RECEIVE FILTER GAIN
_ HYSTERESIS AND DETECTION LEVELS
_ LINE MONITORING LEVEL
_ SIGNALLING FREQUENCY (2982Hz)
DESCRIPTION
The TS7514EVA is an evaluation board which allows a very convenient evaluation of the single chip
modem TS7514 (V.23 operation).
The TS7514EVA performs 2-wire 1200/75 bps half
duplex modem operation in accordance with V.23
CCITT requirements.
The board is controlled by a microcontroller.
A loudspeaker is provided to monitor the line during
the call/handshake procedure.
It provides a direct interface to a V.24 junction
through a 25-pin female connector and a direct interface to the telephone line.
TS7514EVA EVALUATION BOARD
December 1988
1/1
385
TS7515EVA
T87515 EVALUATION BOARD
• V.22NB AND BELL 212/BELL 103 STANDARDS OPERATION
• SYNCHRONOUS/ASYNCHRONOUS MODE
SELECTION
• CHARACTER LENGTH SELECTION IN ASYNCHRONOUS MODE
• GUARD TONE SELECTION/ENABLE
• SCRAMBLER SELECTION/ENABLE
• ANSWER TONE SELECTION/ENABLE
• ANSWER/ORIGINATE MODE SELECTION
• TRANSMIT/RECEIVE ADJUSTABLE LEVELS
• BINARY RATE SELECTION
• LOOP 21 LOOP 31 REMOTE DIGITAL LOOP
SELECTION
• COMPLETE V.24/RS232C AND TELEPHONE
LINE INTERFACE
December 1988
DESCRIPTION
The TS7515EVA is an evaluation board which allows a very convenient evaluation of the single chip
modem TS7515 (V.22, Bell212 and Bell1 03 operations).
The TS7515EVA performs 2-wire 1200 bps full duplex modem operation in accordance with V.22 AlB
CCITT requirements.
1/1
387
I
I
I
I
TS7524EVA
V.22 BIS EVALUATION BOARD
•
•
•
•
•
•
•
•
•
•
•
CCITT V.22BIS EVALUATION MODEM
CCITTV.21, V.22, V.23 EVALUATION MODEM
BELL 103 AND 212 EVALUATION MODEM
FAST EVALUATION OF TS7524 CHIP SET
CALL MODE INCLUDING AUTOMATIC DIALING THROUGH PSTN (DTMF AND PULSE
MODES)
AUTOMATIC ANSWER MODE
DIGITAL AND ANALOG LOOPBACK MODES
DATA TRANSFER MODE FROM 2400BPS TO
75BPS
CALL PROGRESS TONE AND ANSWER TONE
MONITORING
ASYNCHRONOUS OR SYNCHRONOUS SERIAL LINE FORTERMINALOR HOST COMPUTER
PHONE LINE INTERFACE FOR IMMEDIATE
CONNECTION ON PSTN OR PBX
HAYES COMMANDS COMPATIBLE
Switched Telephone Network. It also allows evaluation of V.21, V.22, V.23 and Bell 103, 212 recommendations.
The TS7524EVA furnishes many of the capabilities
of a multi-mode stand-alone modem to provide a
fast evaluation and performance demonstration of
the TS7524 chip set such as calling another modem,
answering, performing necessary handshaking
operations, as well as passing data.
A terminal or host computer must be connected to
the board allowing the user to see the messages
printed on the screen or to enter and receive data
from a far end modem. The TS7524EVA operates
under Hayes 'AT' commands.
The TS7524EVA can also be connected to a modem test station for performance measurements.
DESCRIPTION
A loudspeaker and associated circuitry enables the
possibility to monitor the call progress tone, the answer tone and the handshaking during a connection
with a far-end modem.
The TS7524EVA is a V.22BIS evaluation board
which directly supports the TS7524 chip set. It can
operate up to 2400bps in full duplex over Public
TS7524EVA
•
February 1989
ORDER CODE
1/1
389
TS7532DEMO
V.32 DEMO BOARD
• FAST EVALUATION OF TS7532 CHIP SET
• COMPLEMENTARY TOOL FOR TS7532
DPUMP
• PROVIDES MANY FEATURES OF A CCITT
V.32 STAND-ALONE MODEM
• HANDSHAKE AND RETRAIN SEQUENCE
• CALL MODE INCLUDING AUTOMATIC DIALING THROUGH PSTN
• ANSWER MODE
• DATA TRANSFER MODE AT 9600BPS WITH
OR WITHOUT TREILLIS CODING MODULATION, OR 4800BPS
• CONSTELLATION VIEWING
• CALL PROGRESS TONE AND ANSWER TONE
MONITORING
• SYNCHRONOUS SERIAL LINE FOR OPTIONAL TERMINAL OR HOST COMPUTER
• PHONE LINE INTERFACE FOR IMMEDIATE
CONNECTION ON PSTN OR PBX
DESCRIPTION
The TS7532DEMO is a V.32 demonstration board
which directly supports the TS7532DPUMP (V.32
data pump). It is the ideal complementary tool for
the V.32 data pump. The TS7532DEMO furnishes
many of the capabilities of a V.32 stand-alone mo-
February 1989
dem to provide a fast evaluation and performance
demonstration of the TS7532 chip set such as calling another modem, answering, performing necessary handshaking and retraining operations, as well
as passing data. An optional terminal or personnal
computer may be connected to the board through a
synchronous serial line, allowing the user to see the
messages printed on the screen or to enter and receive data from a far end modem.
The TS7532DEMO can also be connected to a modem test station for performance measurements.
The TS7532DEMO also includes the ability to watch
the constellation on an X-Y oscilloscope screen.
The TS7532DEMO has switches to select the right
number to dial through the Public Switched Telephone Network, and establish a connection in the
call mode.
A loudspeaker and associated circuitry provides the
possibility to monitor the call progress tone, the answer tone and the handshaking during a connection
with a far-end modem.
ORDER CODE
TS7532DEMO
1/1
391
TS7532DPUMP
V.32 DATA PUMP
• CCITT V.32 COMPATIBLE MODEM DATA
PUMP BOARD
• FULL DUPLEX OPERATION AT 9600BPS AND
4800BPS
• FULL IMPLEMENTATION OF CCITT V.32
HANDSHAKE
• SIMPLIFY V.32 PRODUCT DEVELOPMENT
• CANCELLATION OF BOTH NEAR AND FAREND ECHOES WITH UP TO 10HZ OF FREQUENCY OFFSET FOR FAR-END ECHO
• TWO SATELLITE HOPS
• TREILLIS ENCODING AND VITERBI DECODING
• 12.5% ROLL-OFF RAISED COSINE TRANSMIT PULSE SHAPPING
• HIGH PERFORMANCE PASSBAND FRACTIONALLY SPACED ADAPTIVE EQUALIZER
• SIGNAL QUALITY MONITORING
• DTMF GENERATION
• CALL PROGRESS TONE DETECTION
• PARALLEL INTERFACE TO STANDARD
MICROPROCESSORS
• SINGLE BOARD WITH TWO INTERFACE
CONNECTORS FOR ANALOG AND DIGITAL
SIGNALS TO DAA AND HOST MICROCONTROLLER
• IMPLEMENTATION WITH THREE DSPS,
THREE MAFE CHIPS AND STATIC MEMORY
Figure 1 : TS7532DPUMP.
DESCRIPTION
The TS7532DPUMP is a V.32 modem data pump
board. It comes with preprogrammed Digital Signal
Processors for immediate evaluation or performance demonstration of the TS7532 chip set. The
TS7532DPUMP contains three DSPs (TS75320,
TS75321 and T875322), three Modem Analog
Front End chips (TS68950, T868951 and
T868952), four 4kx 4 of static RAM for far-end echo
canceller and two 2k x 8 of static RAM for the Viterbi decoder.
The TS7532DPUMP has two I/O connectors. The
first one is used for all digital and control lines. The
second connector is used for the analog signals to
and from the Data Access Arrangement of the telephone interface.
February 1989
The TS7532DPUMP could be directly connected to
a user controller board through an 8-bit parallel interface or can be used with the TS7532DEMO which
contains DAA, microcontroller, dial switches, and
D/A converters for constellation monitoring.
The TS7532DPUMP greatly reduces and simplifies
V.32 product development.
Moreover, by buying a V.32 software license, modification or extension of the V.32 modem product can
be done with the T87532DPUMP using the company's DSP development tools.
ORDER CODE
TS7532DPUMP
1/1
393
TS7542EVA
T87542 MODEM ANALOG FRONT END EVALUATION BOARD
• EVALUATION BOARD FOR TS7542 AND
TS68950/51/52 MAFE
• PERFORM THE EVALUATION OF MODEM
USING THE FOLLOWING STANDARDS (both
with TS7542 or TS68950/51/52) :
_ CCITT V.21, V.22, V.22bis, V.23, V.26, V.27,
V.29
_ BELL 103,208,209, AND 212A
_ CCITT V.32 WITH TS68950/51/52
• 48- PIN DIL SOCKET COMPATIBLE WITH
SGS-THOMSON MICROELECTRONICS DSP
TOOLS (emulator and/or hardware development
system) OR WITH SGS-THOMSON DSP
EPROM
MODULES
(TS68930EPR
ST18930EPR)
• MASTER CLOCK (5.76MHz) PROVIDED BY AN
ON-BOARD CRYSTAL OR BY THE DSP
CLOCK OUTPUT
• EXTERNAL 2k x 16 BIT DSP MEMORY
• 2 WIRE-WRAPPING AREAS:
_ ONE FOR USER'S LINE INTERFACE
_ ONE FOR CONNECTION OF A MICROCOMPUTER
• +/- 5V ± 5% POWER SUPPLY
December 1988
DESCRIPTION
The TS7542EVA is a Modem Analog Front End
Evaluation Board equipped with the monochip
MAFE TS 7542 or with the chipset MAFE
TS68950/51/52.
It offers a very simple and straightforward means of
interfacing DSP to analog signals.
It is especially well suited for development and debugging of modem applications designed to meet
CCITT and Bell recommendations.
The TS7542EVA can be managed under the control
of the TS68930 or ST18930 DSP.
It can be linked to the SGS-THOMSON DSP tools
and provide a ready-to-use digital processing system well adapted to the analog world.
The TS7542EVA can be used in stand-alone Modem Evaluation Board when under control of a SGSTHOMSON DSP Eprom module, or under control of
a SGS-THOMSON Programmed DSP (V.22bis applications).
ORDER CODE
TS7542EVA
1/1
395
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
APPLICATION NOTE
USING THE TS75320 ECHO CANCELLER IN V.32 MODEMS
By F.B. Oruilhe, W.O. Glass, R. Radzyner
INTRODUCTION
The SGS-THOMSON Microelectronics TS75320 is
a high performance voiceband echo canceller implemented with one SGS-THOMSON TS68930 single-chip VLSI digital signal processor. The T875320
is intended in the first instance for applications with
CCITT V.32 modems for bi-directional full duplex
data transmission at rates up to 9.6 kb/s on switched
telephone network two-wire circuits.
With the echo cancellation approach the whole
bandwidth of the line is available for transmission in
both directions simultaneously; i.e. it is not necessary to splitthe band (e.g. as is done forV.22bis modems) or to time-share between terminals using
burst transmissions. With echo cancellation the effective channel capacity is doubled in comparison
with conventional alternatives.
The task of the echo canceller is to ensure the signal presented to the modem receiver is free of
components emanating from its own transmitter.
The TS75320 is implemented as a passband echo
canceller, i.e. for operation directly with the modulated (line) signal. With this method the echo canceller uses the cancellation error as it appears at the
receiver input. Hence, the only interaction needed
with the host modem is the transfer of the V.32 format rotated data symbols and initialization data during the call set-up procedure.
By virtue of its highly flexible asynchronous parallel
input/output port with its associated mailbox protocol, interfacing the T875320 to a host processor is
very straightforward. Virtually no external interface
AN341 10489
circuitry is required where the modem is implemented with SGS-THOMSON TS68930 digital signal
processors. The TS75320 requires 4 K x 16-bit of
external RAM, used mostly as a delay line (see Section 2.2).
Moreover, the use of the SGS-THOMSON
TS68950/951/952 digitally programmable modem
analog front end (MAFE) chip set is particularly well
suited to this approach (Fig. 2.7). The SGS-THOM80N MAFE provides all the necessary analog interface circuitry for voiceband modem applications, including dedicated circuitry for the subtraction of the
estimated echo. The MAFE is especially convenient
as it incorporates all the required programmable
gain control and clock circuitry, and interface filters
(bandlimiting, anti-aliasing and smoothing filters,
realized with switched-capacitor technology and tunable according to sampling rate requirements).
The TS75320 meets or exceeds all the requirements of CCITT Recommendation V.32. It is designed for operation in circuits with up to two satellite
hops of far-end echo delay (1.14 seconds), and up
to 10Hz of frequency offset in the far-end echo path.
The TS75320 is a key component in the advanced
SGS-THOMSON TS7532 V.32 modem.
This application guide introduces the TS75320 digital echo canceller in the context of V.32 modem applications (Sections 1.2 - 1.3), and provides the details of the operation of the interface circuitry and of
the procedures forthe input and output of data (Section 2). Results of performance measurements are
given in Section 3.
1/30
397
APPLICATION NOTE
CONTENTS
INTRODUCTION
1
LIST OF FIGURES
3
1. GENERAL CONSIDERATIONS
1.1 . Echo Cancellation in Voiceband Modems
1.2. Cancellation Performance Requirements
4
4
4
2. INTERFACING THE TS75320 TO A MODEM
2.1. Introduction
2.2. Interface Circuitry Overview
2.3. Data Exchange Interface with Host Processor (System Bus)
2.4. Data Exchange Interface with External RAM (Local Bus)
2.5. Mailbox and System Bus Protocol
System bus control transfer protocol
Data transfer protocol
5
5
5
5
6
6
6
7
2.6. Operating Procedure: Overview
2.7. Operating Procedure: Initialization and Data Formatting
2/30
398
7
8
3. PERFORMANCE VALIDATION
3.1 . General
3.2. Test System
3.3. Near-end echo algorithm with no far-end signal
3.4. Near-end echo and far-end echo algorithms with no far-end signal
3.5. Near-end echo and far-end echo algorithms with far-end signal
3.6. Performance summary
10
10
10
10
11
11
11
REFERENCES
11
APPLICATION NOTE
LIST OF FIGURES
Figure 1.1
: Near-end and far-end echo paths in conventional telephone network connections
Figure 1.2
: Simplified model of echo suppression in hybrid transformers
Figure 1.3
: Block diagram showing modem and echo canceller connection to the telephone network
Figure 1.4
: Block diagram showing the connection of the near-end and far-end echo cancellers
to the modem and telephone network
Figure 2.1
: Block schematic diagram of TS75320 hardware interface showing connection to
host via the system bus and RAM access via the local bus
Figure 2.2
: Local bus hardware interface
Figure 2.3 A : Local bus timing
Figure 2.3 B : System bus timing
Figure 2.4
: Timing diagram for system bus data transfers
Figure 2.5
: (a) Flowchart of mailbox handshake protocol
Figure 2.6
: Block diagram showing implementations of a digital passband echo canceller using
(b) Schematic description of mailbox handshake protocol
(a) analog subtraction and (b) digital subtraction
Figure 2.7
: (a) Block schematic representation of the TS68950/951 1952 showing functionnal
components and the connection to a host system
(b) V.32 echo canceller analog loop using SGS-THOMSON TS68950/51/52
modem analog front end
Figure 2.8
: Flow chart of TS75320 echo canceller start-up sequence
Figure 2.9
: Flow chart of TS75320 echo canceller master synchronization procedure
Figure 2.10
: (a) Transmit sample timing example (implementation with a TS68950/51 152
analog front end)
(b) simplified block diagram representation showing delay relationship between echo
estimate and echo error
Figure 2.11
: V.32 signal space constellation after trellis coding
Figure 2.12
: Sequence of interface exchanges in relation to echo canceller internal processes
Figure 3.1
: Block diagram of modem and line emulation unit
Figure 3.2
: Impulse response of far-end echo path emulation (excluding bulk delay)
Figure 3.3
: Convergence of near-end echo algorithm
Figure 3.4
: Residual echo versus far-end echo level with far-end signal absent
Figure 3.5
: Residual echo versus far-end signal level for various far-end echo levels
3/30
399
APPLICATION NOTE
1. GENERAL CONSIDERATION
1.1. ECHO CANCELLATION IN VOICEBAND
MODEMS
The basic components making up a typical dialled
modem connection are shown in Fig. 1.1. The functional blocks labelled "H" represent the "hybrid"
transformer (Fig. 1.2) normally found at the junction
of conventional two-wire and four-wire telephone
circuits. The hybrid transformer realizes a rudimentary echo cancellation function that provides a minimal degree of separation between the two directions
of transmission. The separation ratio is normally not
better than 20 dB, and, though adequate generally
for analog voice purposes, this is well short of the
performance needed for data transmission.
The essentials of the data modem echo cancellation system are shown in Fig. 1.3. The task of the
echo canceller "EC" is to provide an emulation of the
characteristics of the echo path, including level
changes (gain/attenuation), delays, frequency
shifts, distortion processes, such that a high degree
of echo suppression results when the estimated
echo is subtracted from the incoming echo. The
overall echo cancellation system consists of a channel emulator and of an adaptive procedure (algorithm) for the determination of optimum emulator parameters (coefficients). The echo canceller may be
considered as an adaptive filter whose transfer function models that of the echo path.
e
For the purposes of echo cancellation in telephone
networks-ilis- necessary 10 distinguish between
_ the near-end echo, due to feedthrough in the
local hybrid transformer,
and,
_ the far-end echo, due to feedthrough and reflections at the remote terminal.
This is shown in Fig. 1.1 .
The far-end echo is generated in the hybrid at the
junction of the far end two-wire local loop with the
four-wire circuit, and will appear at the receiver input after some delay, corresponding to the round trip
to and from the remote hybrid. Since this path may
include satellite links, the delay may be large in comparison to the duration of the impulse response of
the system. Provision has been made for a far-end
echo delay of up to 1.14 second, corresponding to
the delay incurred with two satellite links. CCITT recommendation V.32 includes a provision for measuring this delay during the modem handshake procedure.
Owing to the large delays possible between the
near-end and far-end echo contributions it is necessary to use a separate echo estimation process for
4/30
400
each, as shown in Fig. 1.4. The requirements of the
near-end and far-end cancellers differ significantly.
As discussed in Section 1.3, below, the echo suppression performance requirement for the near-end
canceller is considerably greater than for far-end
canceller. However, the far-end canceller must be
capable of functioning in the presence of nontrivial
frequency offset.
Both near-end and far-end echo cancellers in the
TS75320 accomodate up to 16 ms of echo path impulse response.
1.2. ECHO CANCELLATION PERFORMANCE
REQUIREMENTS
For a V.32 receiver operating in additive white gaussian noise, the minimum signal-to-noise ratio for a
bit error rate of 10-5 is 18 dB, on a mean power basis [Ref. 2, Fig. 5.58, p. 186]. Supposing channel
noise and residual echo contributions of similar magnitudes, the minimum signal-to-residual-echo ratio
requirement is 21 dB. Again, with approximately
equal near-end and far-end residual echo contributions the minimum signal-to-residual-echo ratio is
24 dB for each of these contributions.
The near-end echo level is typically 10 to 20 dB below that of the transmitted signal. The level of the
received signal may occasionally fall as low as 30
to 40 dB below that of the transmitted signal. Hence,
under certain line conditions, the near-end echo level could be 30 dB above that of the received signal.
To obtain a signal-to-residual-echo ratio better than
24dB atthereceiver input, near-end echo suppression better than around 54 to 55 dB is necessary.
This is a stringent performance requirement met by
the TS75320.
The far-end echo is subject to attenuation twice in
the local loop and in the network, and is also attenuated in the far-end hybrid. Hence, its level is normally several decibels below that of the received signal, about 10 dB typically; the worst-case figure
for system design purposes is 8 dB. To obtain a minimum signal to residual echo ratio of 24 dB for the
far-end echo contribution it follows the suppression
ratio for the far-end echo canceller must be around
14 dB under typical operating conditions and not below 16 dB under adverse conditions.
While this is considerably less than the requirement
for the near-end echo canceller, it is important to
note that the far-end echo canceller must be capable of maintaining this level of performance in the
presence of nontrivial frequency offsets. The current
version of the TS75320 meets this requirement in
the presence of frequency offsets of 10Hz' in the
far-end echo.
APPLICATION NOTE
Convergence requirements are 1.5 second for the
near-end echo algorithm, and 6.9 seconds for the
near-end and far-end echo algorithms combined.
The results of TS75320 performance measurements are documented in Section 3.
2. INTERFACING THE TS75320 TO A MODEM
2.1. INTRODUCTION
The purpose of this section is to provide in detail the
essential information required for the trouble-free
operation of the TS75320. This includes pin by pin
and bit by bit descriptions of hardware connections,
signal format and timing requirements, and data exchange protocols.
The TS75320 echo canceller is implemented with
the SGS-THOMSON TS68930 monolithic digital signal processor (Ref. 4). In this application guide no
previous experience with the TS68930 is assumed.
All the essential details for the embedding of the
TS75320 in a CCITT V.32 modem environment will
be found herein; reference to TS68930 documentation should not be required under normal circumstances.
The description is divided into three parts:
(a) Interface circuitry
the detailed description of the data, address and
control buses available for the connection of the
echo canceller to a host or to other processors
(Sections 2.2 - 2.4).
(b) Data exchange protocols
the mechanics of the operation and sequencing
of the control signals for the management of data
transfers to and from the TS75320 (Section 2.5).
(c) Organization and formatting of data
the definition of the input and output data signals,
and of the initialization timing and formatting requirements (Sections 2.6 - 2.7).
2.2. INTERFACE CIRCUITRY OVERVIEW
Two buses are used for the exchange of data with
the TS75320 :
_ The local bus (16 data lines DO-D15), which
is a transparent extension of the internal bus
structure
_ The system bus (8 data lines ADO-AD7)
which provides an asynchronous data transfer mechanism by means of a mailbox protocol.
These buses are not independent: the eight lines
ADO-AD7 which constitute the data lines of the system bus also serve as address lines on the local bus.
The TS75320 uses the local bus to access the 4 K
x 16-bit of external RAM needed for the symbol bulk
delay and other data workspace requirements. The
system bus is used for communication with the host
processor.
A schematic representation of the interface circuitry
is shown in Fig. 2.1.
2.3. DATA EXCHANGE INTERFACE WITH
HOST PROCESSOR (System Bus)
Data exchanges between the TS75320 and the host
system take place by means of a "mailbox" within
the TS75320, accessible externally through the system bus. These data transfers are asynchronous,
i.e. their timing in independent of the TS75320 clock.
The mailbox consists of two shift registers, the "RIN" register for data input, and the "R-OUT" register
for data output; each of these is 3-byte wide. The
system bus has eight data lines ADO-AD7. Hence,
to effect a complete 24-bit data exchange via the
system bus, three sequential 8-bit transfers are required.
The system bus consists of three basic sections:
_ the data bus :
ADO-AD7 (bidirectional, 8-bit wide)
(these lines are also used as address lines
on the local bus)
the address bus :
CS chip select (input)
RS register select (input)
the control bus :
SRIW system read/write (input)
SDS system data strobe (input)
IRQ interrupt request (output)
.
DTACK data transfer acknowledge (output)
BA bus available (output)
The operation of these buses (data transfer protocol) is described in detail in Section 2.5.
An important aspect of system bus operation is that
processing within the TS75320 halts when control
of the bus is released to the host. (This occurs because the local bus is disabled owing to the unavailability of lines ADO-AD7, needed to address the external RAM). Hence careful attention must be paid
to the management of the system bus by the host
processor. The total occupation time of the system
bus by the host must be less than 10 Ils during any
mailbox access as described in Fig. 2.12.
Prior to the release of the system bus to the host
and the initiation of the echo canceller HALT state,
the current program instruction will be completed. In
the HALT state
_ the program counter is not incremented
5/30
401
APPLICATION NOTE
_ no address is generated on the system bus
_ on the local bus, DO-D15 and AS-A 11 are
switched to the high impedance state.
The description of the organization, sequencing and
formatting of the data exchanges is given in Sections 2.6 and 2.?
2.4. DATA EXCHANGE INTERFACE WITH EXTERNAL RAM (Local Bus)
Data exchanges between the TS?5320 and its external RAM take place via the local bus (Figs. 2.1,
2.2). This bus operates as a direct extension of the
internal 16-bit bus structure. As such, it is under the
total (synchronous) control of the TS?5320.
The local bus consists of three basic sections:
_ the data bus :
16 lines: DO-D15
the address bus:
12 lines:
four dedicated: AS-A 11
eight shared with system bus: ADOAD?
the control bus :
2 lines: (Motorola protocol)
Rm : write strobe signal
DS : read strobe signal
The eight address lines ADO-AD? also serve as the
data lines of the system bus. These may be isolated from the host side of the system bus by means
of a bus transceiver (such as a ?4F245) using the
sys1em bus control lineBA (bus· avattable) or its
complement to provide the switching signal, as
shown in Figs. 2.1 and 2.2 (refer to Section 2.5). As
noted in the previous section, program execution within the TS?5320 halts when control of the system
bus is relinquished, i.e. when the lines ADO-AD? are
not available for local bus operation.
The timing diagrams and requirements for READ
and WRITE operations on the local bus are displayed in Fig. 2.3. For normal full speed operation
(25 MHz master clock), the maximum access time
is 45 ns for data transfer from memory (READ cycle). The maximum access time for data transfer to
memory is 35 ns (WRITE cycle).
The CLKOUT line provides access to a clock signal
at half the crystal frequency, i.e. SO ns cycle period.
This is a useful timing reference when monitoring
the operation of the interface circuitry. The period of
a TS?5320 unit operation is twice the period of the
CLCKOUT signal, i.e. 160 ns.
2.5. MAILBOX AND SYSTEM BUS PROTOCOL
To best understand the mailbox data exchange mechanism it is important to recall the following consi6/30
402
derations :
(a) External access to the mailbox (system bus)
provides eight data lines, i.e. transfers must be
effected in units of one byte.
(b) The mailbox consists of one input and one output shift register (R-IN and R-OUT, respectively),
each able to store a string of three S-bit words.
(c) The eight data lines on the system bus (ADOAD?) are shared with the local bus.
(d) TS75320 processing ceases while lines (A~O
AD?) are not available for local bus operation
(processor HALT state).
(e) Data transfers between the mailbox and t~e
TS?5320 internal buses cannot take place while
the mailbox and the system bus are under external control.
On the basis of the foregoing, two key points
emerge:
(a) One full transfer into the mailbox (R-IN register) and one full transfer out of the mailbo~ (ROUT register) are possible per external mailbox
access, i.e. three byte-wide WRITE operations,
and three byte-wide READ operations.
(b) New data exchanges with the host cannot be
effected until the host relinquishes control of the
mailbox and of the system bus to allow reading
and reloading within the TS?5320.
Thus, it is evident that effective management of data transfers to and from the host will hinge on the timely hand,over 01 mailbox and system bus control ..
between TS?5320 and host. It is important to note
that this control mechanism operates on the "possession" principle; i.e. the processor in possession
of the bus and mailbox retains control of data transfer until such time as it initiates its release'.
It follows the data input/output procedure may be
described in terms ,of two distinct phases:
(a) Bus control transfer protocol:
A dialogue for the management of the successive transfers of control of the mailbox
and bus between TS?5320 and host.
(b) Data transfer protocol:
A dialogue for the management of the successive transfers of data bytes between
mailbox and host in each control phase.
The system bus timing diagrams and associated tolerance specifications are given in Fig. 6, p. 10 in the
TS?5320 data sheet and in fig. 2.4.
System bus control transfer protocol
The description below refers to figures 2.1 , 2.4 and
2.5.
APPLICATION NOTE
To signal readiness for data exchanges with the
host, the TS75320 transmits an interrupt request,
IRQ\ = o. To signal acceptance of the request the
host responds (when ready) by sending CS\ = 0,
RS\ = 0 ("address" signals), SR/w\ = 1, i.e. READ
signal : it is important that a WRITE signal is not
sent at this stage, as local bus operations using
lines ADO-AD7 may still be in progress.
Following validation (SDS\ = 0 data strobe pulse),
the TS75320 detects the host response (after 3-5
operation cycles) and completes the mailbox and
system bus handover protocol by setting the bus
available signal BA = 1, and resetting IRQ\ = 1.
The system bus and mailbox are now available to
the host, and processing within the TS75320 has
been halted.
• REMARK: The TS75320 is said to be pseudoslave. It is not totally slave, in the sense that it remains independent of the host while it retains control
of the system bus. When control of the system bus
is handed over to the host, the TS75320 becomes
a slave (in particular, processing halts). It should be
noted that the converse is not true, i.e. when control
of the system bus is with the TS75320, the host remains independent (albeit not master over the
TS75320).
The TS75320 will have sent a data transfer acknowledge pulse, DTACK\ = 0 within 50 ns of receiving
the data strobe SDS\ = O.
The host may now proceed with one sequence of
up to three byte-wide mailbox READ operations (ROUT register) and/or one sequence of up to three
byte-wide mailbox WRITE operations (R-IN register). The data read/write procedure is described in
the next subsection "Data transfer protocol".
At the end of the data transfer operations, the host
initiates the release of the mailbox and system bus
with CS\ = 0, RS\ = 1, SR/w\ = 1.
These signals become effective with the transmission of the strobe pulse, SDS\ = 0, whereupon the
TS75320 will initiate internal procedure for the resumption of processing. It will respond extemally
with a DTACK\ = 0 pulse within 50 ns of the leading
edge of the SDS\ LOW pulse, and with the resetting
of the bus available line (BA = O) within 100 ns of
the reset of the strobe pulse (SDS\ = 1). The.
TS75320 internal HALT state ceases one processing cycle (nominally 160 ns) after the resetting of
the BA signal. The lines ADO-AD7 are not accessed
for local bus operations until after that time.
As indicated in Section 2.4, the BA signal is useful
to switch local bus isolation circuitry forthe data lines
ADO-AD7. The use of the DTACK\ signals is option-
~
~.,I
nal, subject to the requirements of the host processor.
Data transfer protocol
As in the foregoing subsection, the description below refers to Figures 2.1 , 2.4 and 2.5.
The host is able to proceed with mailbox data transfer operations as soon as the handover of the system bus control is completed. This corresponds to
the detectiol1 by the host of the reset of the interrupt
request line, IRQ\ = 1.
A mailbox READ operation is carried out as follows:
When ready, the host sets CS\ = 0, RS\ = 0,
SR/w\ = 1, and transmits the data strobe after a
minimum set-up time of 5 ns (tSAW). Data becomes available to the bus within 35 ns (tSDRS)
after the end of the data strobe (SDS\) leading
edge, and remains held fortsDRs ns after the completion of SDS\ reset (10 < tSDRS < 50).
After the completion of each READ operation, the
next byte is shifted into the interface buffer. As indicated earlier, up to three READ operations may
be executed usefully in any exchange period. After that, new data will not be available in the buffer until the TS75320 has been given the opportunity to reload the R-OUT shift register.
The mailbox WRITE procedure follows the same
pattern, with the main difference that the read/write
signal SR/W\ is LOW:
The data must be valid for a minimum period
tSDSW = 20 ns before the completion of SDS\ reset, and held not less than tsDHW = 5 ns after that
reference time. After the completion of each write
operation, the input byte is shifted to the next location in the TS75320 R-IN register to vacate the
input for the next byte. As before, up to three
WRITE operations may be effected usefully per
exchange. Before further useful WRITE operations are effected, control of the mailbox must be
released to the TS75320 so it can proceed with
the retrieval of the new data in the R-IN register.
2.6. OPERATING PROCEDURE: OVERVIEW
The TS75320 is designed to provide an echo cancellation function for V.32 modems in the first instance. As such, a V.32 format rotated symbol is expected at the rate of 2400 Baud, and the incoming
line signal is processed at the rate of 7200 samples
per second, i.e. three samples per Baud interval.
The output of the echo canceller is an estimated
echo. To cancel the unwanted echo, the echo estimate is subtracted from the incoming V.32 line signal.
SGS·1HOMSON
7/30
ililD~IIII@rn~I<©\fIlil@IllD~®
403
APPLICATION NOTE
This subtraction is external to the TS75320 and may
be realized digitally (e.g. in one of the other processors of the modem), or in the analog domain as discussed below (see Fig. 2.6).
It is important to note that the polarity ofthe TS75320
estimated echo output value is such that the "subtraction" operation must be realized as a physical
addition.
Implementation of the subtraction in the analog domain may be carried out with the SGS-THOMSON
TS68950/951/952 modem analog front-end
(MAFE) chip set (see Fig. 2.7). This approach is attractive since the SGS-THOMSON MAFE circuitry
is designed with features aimed specifically for this
class of applications, and incorporates a dedicated
signal path for the estimated echo, with an in-built
analogue adder for the "subtraction" operation.
The echo estimate samples are output via the mailbox R-OUT register at the rate of three per Baud interval, i.e. 7200 per second.
The TS75320 expects the input of an error signal
(residual echo) and of a reference signal, i.e. the line
output of the local transmitter.
The error signal is the difference between the V.32
incoming line signal and the estimated echo. As
shown in Figs. 1.3, 1.4 and 2.6, this signal is the
echo-free V.32 signal required at the modem receiver input. Under normal operating conditions both
the far-end signal and the residual echo will be present. However, as part of the normal procedure for
setting upa cCilibetween two modems it is necessary to provide an initialization period for the echo
cancellers at each terminal. So, to allow rapid
convergence of the adaptive algorithm, the far-end
signal is not transmitted during this period, i.e. the
modem receives only the echo of its own transmission while the initialization of the algorithm is in progress. It should be noted that the far-end signal is
seen as noise by the echo canceller algorithm.
Error signal samples are required atthe rate of 7200
per second. The rotated reference symbols are required at the Baud rate only (i.e. 2400 per second),
since they remain unchanged over one Baud interval.
The convergence of the adaptive algorithm proceeds in two phases: first the near-end cancellation
algorithm is brought into operation on its own.
Convergence of this process is normally completed
within around 500 ms ; a period of 3500 Baud intervals (i.e. 1.46 seconds) is provided for the completion of this phase.
After this time has elapsed, operation of the far-end
cancellation algorithm is commenced (including fre8/30
404
quency offset correction). The total time provided for
the convergence of both near-end and far-end algorithms is 16656 Baud intervals, i.e. 6.9 seconds.
The TS75320 has been developped for compatibility with CCITT V.32 handshake protocol using a
particular sequence for echo canceller adaptation
before segment 1 consisting of 8192 bauds of
scrambled I's. The TS75320 then uses the segment 1 to estimate the frequency offset of the farend echo. The sequence TRN consisting of scrambled I's at 4800 bits/sec during 8192 bauds to terminate the far-end and near-end echo canceller
convergence.
After the completion of the initialization processes
at each end, full duplex data transmission may proceed. The algorithm continues to track and to adaptively adjust coefficient values beyond the initialization period, for the duration of the transmission. At
the beginning of the initialization process, the
TS75320 requires the input of the two-way far-end
echo bulk delay.
A walkthrough description of the operation of the
echo canceller is given in the next section. This includes the initialization processes and the details for
formatting and for the selection of the appropriate
order for the input and output of the data samples.
2.7. OPERATING PROCEDURE: INITIALIZATION AND DATA FORMATTING
The description below refers to flowcharts and sequencediagrams in Figures 2.8to 2.12.
The initialization of the TS75320 is invoked by asserting the RESET signal (RESETILOW, minimum
duration 640 ns). This is the "booting" process during which the echo canceller workspace memory is
cleared (coefficients, delay lines, operating variables) and the necessary parameters for the operation of all internal and interface processes are configured. The initialization sequence conforms to the
requirements of CCITT Recommendation V.32 and
is operated for starting upfrom cold, and also in case
of retrains.
The first mailbox exchange after a RESET does
not conform to the standard protocol described in
Section 2.5. This is because the RESET generates
an IRQ\LOW level well before the mailbox becomes
available. Hence, for the first data transfer, and
IRQ\triggered protocol cannot be used. Instead, the
host must wait a minimum of 2 ms after the activation of the RESETI signal, and then may proceed
with the transfer of the three bytes AA, AA, 00
(hexadecimal) into the mailbox R-IN register, using
the mailbox data WRITE procedure as described in
Section 2.5. This initiates the operation of the echo
APPLICATION NOTE
canceller algorithm. The IRQ\ line is then restored
to the RESET state (IRQ\ HIGH), and will thereafter
be available for use in accordance with the normal
protocol.
A mailbox exchange request will follow (second
mailbox exchange), this time conforming to the
normal (IRQ\ triggered) procedure as described in
Section 2.5. In response the host is required to
transfer the far-end round trip delay as a hexadecimal number using units of Baud periods. This number must be smaller than 3000 (decimal), i.e.
1.25 seconds. CCITT Recommendation V.32 includes a provision for measuring this delay during
the modem handshake procedure.
The TS75320 will interpret the first two bytes in the
R-IN register as the round trip delay, LSBs followed
by MSBs, right justified. This delay must be greater
than o. The third byte must be 01 for normal operation, i.e. with far-end echo canceller enabled. If the
third byte is 00, the far-end echo canceller is inhibited.
Example:
To enter a delay of (decimal) 2751
Baud periods, i.e. hexadecimal OABF, the following three bytes must be transferred : first BF,
then OA, then 01. The third byte 01 is to enable
the far-end echo canceller.
In response to a third mailbox exchange request
the host enters a confirmation signal: AA, AA, 01 ;
this triggers the onset of the near-end cancellation
algorithm. This confirmation must be sent at the start
of the particu lar CC ITT echo canceller adaptable sequence as an intemal baud counter within the
TS75320 will begin to increment at each baud interval. Two additional mailbox exchanges requests will
occur which must be handled as dummy exchanges
by the host. The host must perform at least 2 real
operations per exchange-one to initiate the protocol
and one to terminate the protocol as described in
Section 2.5. Mailbox exchanges after this will be for
the input of the rotated data symbols and of the cancellation error and for the output of the estimated
echo.
During the first transfer the host transfers the cancellation error (first two bytes), followed by the rotated transmitted data symbol (third byte: a new rotated data symbol is input every third mailbox exchange). In the second mailbox exchange the estimated echo is transferred to the host using the same
data format as for the cancellation error (details below). It should be noted that the first cancellation error and the first estimated echo will not represent
meaningful data, but will serve as starting values.
Also, the EC is frozen is the cancelling error is zero.
Thereafter, input and output data transfers will continue to alternate following the pattern detailed
above, with the difference that, in the second and
third input exchanges of the Baud interval, a new
transmitted symbol is not transferred; on those occasions the transfer of a CCI command as described in Fig. 2.9. must nevertheless be carried out.
The timing of these data transfers is determined by
the modem transmitter sampling clock. Sample
timing relationships are shown in Fig. 2.10.
Fig. 2.10(a) illustrates the timing sequence for an
implementation with a TS68950/51 152 analog front
end. Fig. 2.10(b) shows the delay relationship between echo estimate and echo error.
The cancellation error and estimated echo are represented as 16-bit two's complement sample values. The least significant byte must be transferred
first. The level of these signals will be determined by
the level of the incoming line signal.
A question that arises at this point is whether there
should be any scaling of the cancellation error before it is loaded in the echo canceller, in particular in
the case of very low levels. The answer is that this
signal must not be scaled. All that is required is that
the incoming line signal at the point of substraction
of the estimated echo should be at a level appropriate for the requirements of the analogue-digital
interface circuitry, i.e. it should not be so high as to
produce excessively frequent converter overflows,
nor so low as to resu It in the waste of converter dynamic range. Within the TS75320, processing takes
places in 32-bit arithmetic (corresponding to a range
of 192 dB from quantization noise floorto saturation
ceiling). This provides an adequate margin against
erosion of numerical accuracy.
The data symbol is a complex-valued rotated trelliscoded V.32 encoder output (x, y), such that
_ x and yare 4-bit two's complement integers
in the range -4 to +4 (Fig. 2.11)
_ the symbol must be rotated due to the effect
of the modulation. The end result is to mUltiply the symbol by (-jt where n = baud number being sent. This is seen as a.-90 0 phase
shift per baud interval.
Example: Consider the trellis-coded symbol
10010 in the V.32 signal constellation (see
Fig. 2.11). The corresponding co-ordinates
are x = - 2, Y = - 3. If n = 9, (- j)n = - j, and
the rotated coordinates become x = - 3,
Y = -2.
_ the real part x is located in the four most significant bits, the imaginary part y in the four
least significant bits
9/30
405
APPLICATION NOTE;
For the example above the real part is hexadecimaiD, and the imaginary part is 2 in two's complement representation. Hence, the data byte to
be transferred for this symbol is 02.
A new rotated data symbol is transferred only once
per Baud interval, Le. every third input sample transfer.
Fig. 2.12 displays the overall sequence of interface
exchanges in relation to echo canceller internal processes. As indicated in the previous section, only
the near-end algorittLm operates in the first phase of
adaptation. After S-S transition, the near-end algorithm will have converged, and the far-end algorithm
is set into operation automatically (subject to the value of the third byte in the bulk delay data transfer,
see above). In this phase both the near-end and farend algorithms operate together.
After 16656 Baud intervals, transmission is interrupted to allow the other terminal set up its echo canceller. Full duplex data transmission may begin once
both echo canceller algorithms have converged,
and the modem handshakes completed.
3. PERFORMANCE VALIDATION
3.1. GENERAL
The minimum signal-to-residual-echo ratio and cancellation algorithm convergence rate requirements
for V.32 modems are given in Section 1.3. Measurements procedures to obtain benchmark indicators
-of the pertOl"mance ot.tl1e TS75320 are desGribed
below. The test procedures and benchmark results
are intended to provide reference conditions for application development and trouble shooting. The results obtained using these test procedures meet or
exceed the requirements of CCITT Recommendation V.32.
The tests consist of the measurement of convergence times and residual echo levels under various
conditions of operation as follows :
(a) near-end echo algorithm operating alone, with
far-end signal absent
. (b) near-end echo and far-end echo algorithms
both in operation, with far-end signal absent, with
and without frequency offset
(c) near-end and far-end echo algorithms both in
operation, over a range of far-end signal levels,
with and without frequency offset.
The tests are carried out using the normal initialization procedures (as described in Section 2.6), Le.
tests in category (b) require prior convergence of the
near-end echo algorithm under condition (a), and,
similarly, tests in category (c) require prior conver-
10/30
~
~.,I
406
gence of the combined near-end echo and far-end
echo algorithms under conditions (a) and (b), respectively. For this reason, convergence times are
relevant only for tests in categories (a) and (b).
3.2. TEST SYSTEM
A block schematic diagram of the test system is
shown in Fig. 3.1.
TS68931 digital signal processors and a
TS68950/951/952 modem analog front-end
(MAFE) chip set are used to generate the near-end
and far-end signals, and to emulate the transmission conditions for the far-end echo, including frequency offset and bulk delay. The integral linearity
of the TS68950 Modem Transmit Analog Interface
D/A converters is 11 bits, as needed to realize the
required cancellation performance.
The line characteristics for the near-end echo are
generated using a Wilcom line simulator model
T240 (Wilcom Products Inc., Laconia, N.H., U.S.A.).
The following artificial line module types are included:
(a) compromise network with 600/900 Ohm switch
(b) 6000fV22gauge, 83nF/mile
(c) 88mH module with 3-position switch for normal, no-load or half-load operation
The impulse response of the far-end echo path is
given in Fig. 3.2 (excluding the bulk delay).
3.3. NEAR-END ECHO ALGORITHM WITH NO
FAR-END SlGNAL
The conditions for these tests correspond to the first
phase of the initialization procedure, Le. the far-end
modem is not transmitting, and the far-end echo algorithm is not enabled.
The Wilcom line simulator is set up with six modules
in circuit, as follows:
(i)
6000fV22g
(ii)
88mH/half load
(iii)
6000fV22g
(iv)
88mH/no load
(v)
compromise networkl6000hm
(vi)
6000fV22g
The V.32 transmitter output is - 2.2 dBm. The nearend echo level at the canceller input is - 9.2 dBm,
Le. 7 dB below the transmitted V.32 signal. It should
be noted this represents a highly peSSimistic condition (see Section 1.3).
A typical oscilloscope trace of the residual echo versus time is shown in Fig. 3.3. The convergence time
for this test is 360 ms (cf. 1.5 second maximum allowed). Similar convergence characteristics are ob-
SGS·THOMSON
Ii!ilD©OO~~w:1i"IiiI@IlJD©®
APPLICATION NOTE
tained for this test over a wide range of line conditions.
3.4. NEAR-END ECHO AND FAR-END ECHO
ALGORITHMS WITH NO FAR-END SIGNAL
In these tests the convergence of both the near-end
echo and the far-end echo algorithms are measured. The test conditions for the results documented
are as follows :
_ Wilcom line simulator as in Section 3.3
_ bulk delay 570 ms
_ frequency offset 0.5 Hz
_ far-end echo level - 16 dBm
A typical oscilloscope trace of the residual echo versus time is shown in Fig. 3.3. The overall convergence time for the two algorith ms is less than 6.9 seconds.
Similar convergence characteristics are obtained for
this test without frequency offset, and over a wide
range of line conditions.
The steady-state residual echo level versus far-end
echo level is displayed in graphical form in Fig. 3.4.
3.5. NEAR-END ECHO AND FAR-END ALGORITHMS WITH FAR-END SIGNAL
In this test the steady-state residual echo level is
measured as a function of the far-end signal level,
for various levels of far-end echo. The test conditions are the same as in Section 3.4.
3.6. PERFORMANCE SUMMARY
The TS75320 achieves the suppression ratios and
convergence speeds required for high performance
V.32 modems. With an appropriate choice of analog front-end (such as the SG8-THOMSON
TS68950/951/952 MAFE chip set) the near-end
echo canceller yields a suppression ratio better than
55 dB. In the absence of far-end signal and far-end
echo, the residual echo level is below - 65 dBm for
a near-end echo level of - 10 dBm at the receiver input.
For operation with combined near-end and far-end
cancellers, the signal-to-residual-echo ratio achieved at the receiver input is better than 24 dB for typical receive levels around - 20 dBm. This performance is maintained in the presence of 10Hz of frequency offset in the far-end echo. The signal-to-residual-echo ratio remains better than 21 dB for receive levels as low as - 40 dBm, provided the farend echo is at least 8 dB below the level of the received far-end signal.
The convergence time for the near-end echo canceller is typically around 0.5 second, and not greater than 1.5 seconds. The overall convergence time
for near-end and far-end cancellers combined is not
greater than 6.9 seconds (16656 Baud intervals),
without or with frequency offset, conforming to the
handshake requirements in CCITT Recommendation V.32.
The results are displayed in Fig. 3.5. Similar performance is obtained in the absence of frequency offset.
REFERENCES
1.
D.G. Messerschmitt, Echo Cancellation in Speech and Data transmission; Chapter 4 in K. FEHER,
Advanced Digital Communications: Systems and Signal Processing Techniques, Prentice-Hall 1987.
2.
M. Stein, Les Modems pour Transmission de Donnees, Masson 1987, see Section 6.5 (pp. 227-239).
3.
SGS-THOMSON Data Sheet: TS75320 Digital Echo Canceller.
4.
SGS-THOMSON Data Sheet: TS68930/931 Programmable Signal Processor.
5.
SGS-THOMSON Data Sheet: TS68950 Modem Transmit Analog Interface.
6.
SGS-THOMSON Data Sheet: TS68951 Modem Receive Analog Interface.
7.
SGS-THOMSON Data Sheet: TS68952 Modem Transmit/Receive Clock Generator.
8.
SGS-THOMSON: Development of Real-time Algorithms Using the Thomson Digital Signal Processor
TS68930 and the Thomson Analog Front-end TS68950/1/2; Thomson Semiconducteurs, Application Note AN-076.
11/30
APPLICATION NOTE
Figure 1.1 : Near-end and Far-end Echo Paths in Conventional Telephone Network Connections (blocks
labelled "H" are hybrid transformers, shown in figure 1.2).
FourMwire Carrier Circuit
M88AN2-01
Figure 1.2: Simplified Model of Echo Suppression in Hybrid Transformers.
Transmitter
I;
z
G
~e
Receiver
t..------------+-f------------"
~-----~
+
I,
M88AN2-02
12/30
408
APPLICATION NOTE
Figure 1.3 : Block Diagram Showing Modem and Echo Canceller Connection to the Telephone Network.
Transmitter
L~
____________,-____________~E
H
I
EC
Hybrid
LINE
e(\)
Receiver
If--____-+-_ _ _
'----------
E(\)
+ __+
--'e"-'-'O!L-l---------e
F
M88AN2-03
Figure 1.4 : Block Diagram Showing the Connection of the Near-end and Far-end Echo Cancellers to
the Modem and Telephone Network_
DATA IN
TRANSMITTER
BULK
Near Echo
DELAY
LINE
Two-wire
Loop
Far Echo
Far Signal
L.-----------------f _____ ~----------------J
~~~~---L--+t
__
------~
RECEIVER
-
I
Gi
':11 SGS·ntOMSON
iliIO©OO~~rn©"ii'1iI@1II0©~
M88AN2-04
13/30
409
APPLICATION NOTE
Figure 2.1 : Blocks Schem~tic Diagram of TS75320 Hardware Interface Showing Connection to Host Via
the System Bus and RAM Access Via the Local Bus.
BA
~
[>
DO·D7
ADO·AD7
8
DATA
16
TS
HOST
~
> '}
~
\
/
tARW
tpw
~
\
/
tARW
tDSW
00-015
DATA OUT
///iI
tDSR
DATA IN
tozw
t DKI
DATA IN
MBBAN2-07
15/30
411
APPLICATION NOTE
AC ELECTRICAL SPECIFICATIONS. SYSTEM BUS TIMING
(Vee = 5.0V ± 5%, Tamb = O°C to + 70°C; see figure 6)
Symbol
Parameter
Min.
Max.
Unit
tspw
SDS, Pulse Width
60
ns
tSAW
SRIW, CS, RS Set-up Time
10
ns
tSAH
SRIW, CS, RS Hold after SDS High
5
ns
tSDSR
Data Set-up Time, Read Cycle
20
ns
tSDHR
Data Hold Time, Read Cycle
5
tSDSW
Data Set-up Time, Write Cycle
tSDHW
Data Hold Time, Write Cycle
tDSLDT
ns
35
ns
50
ns
SDS Low To DTACK Low
50
ns
tDSHDT
SDS High to DTACK High'
50
ns
tDSHIR
SDS High to IRQ High
50
ns
tSDZW
SDS High to Data High Impedance, Write Cycle
40
ns
10
, DTACK is an open drain output first load include RL = 890
Q
at Vee.
Figure 2.3 B : System Bus Timing Diagram.
tspw
\
'SAH
~
tSAW
_§Biw, CS.
RS
J]}
tSDSR
/
ADO-A07
DATA IN
'\
tSDHR
DATA IN
t SCfl!N
~
tSDSW
ADO-AD7
DATA OUT
V!IJl
««
DATA OUT
tDSLDT
»»>-
lOS HOT
\
~
I
tDSHIR
~
16/30
412
APPLICATION NOTE
Figure 2.4 : Functional Timing Diagram for System Bus Data Transfers.
11
internal instruction clock
f- -
,
,
tc
period of
CLKOUT signal
,
--l
~
,
,
,,
,,'
~
CS
-R-s--~---1/~
SRW
----------LrI
f-r-----~------j/If-1
,,
~
-S-Ds--~---1/~
,
,
/I
DTACK
II
'
,
,
,
,
"
,
,,,
------,U
II/-I
U
(3-5)
~
cycles
mailbox
mailbox
ready
request
mailbox exchange
- - -
end of
- - - - -1- -
exchange
/I
~II
1/
IH
IH
/I
SA
-----r-----------
II
~~~
/I
Ii
...
~
...........
~
................
~~----,,
local bus addresses
system bus exchanges
(Iba)
internal halt
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Iba
,
-I
M88AN2-08
~
"'''11
SGS·11I0MSON
~O©IU@l
=f
:::T:::T
(0 (0
: OPTIONAL
°3
01»
ATTENUATOR
:::J !::!".
:JO
TxCCLK
~:o
TxRCLK
<'". (0
0-0
Tx CCLK
;:m
0(0
I» :J
~
Ilii
0<'".
DIGITAL
MCU
!1l~
~fn
SIGNAL
PROCESSOR
I
i
I
i
I
E.
(flO
~:J
UlO
'<
(fl~
@,
~:::T
TS68930/31
----.------
~~
~Ii:
RxCCLK
-0
RxRCLK
",fn
~z
(0(0
?--i
600 f i
Ul
cr>
OJ
------.
V-
I--- r-
I
I
I
1"I I.r ~
I
I
e:::~
I
/
V
-40
-30
-50
-60
Far End Echo (dBml.
M88AN2-24
29/30
425
APPLICATION NOTE
Figure 3.5 : Residual Echo Versus Far-end Signal Level for Various Far-end Echo Levels.
TEST CONDITIONS
1. Far-end Echo Delay of 570 ms
2. Wilcom Line Simulator 6000 Ft. ; 1/2 Load, 88 mH ; 6000 88 mH, no Load; Compromise
Network = 600 Q ; 6000 F.
Far-end Signal
Far-end Echo
-
15dBm
21
27
32
39
30/30
426
- 8dBm
.0, .5HZ
-
22,
25,
26,
25,
25,
-
24
25
25
25
25
- 14
.0, .5HZ
-
X
24, 27, 25, 24, -
24
27
25
24
- 20
.0, .5 HZ
- 26
.0, .5HZ
- 32
.0, .5HZ
X
X
- 24, - 25
- 25, - 25
- 25, - 25
X
X
X
- 24, - 25
- 25, - 25
X
X
X
X
- 22, - 23
APPLICATION NOTE
INTERFACING THE TS7524 MODEM CHIP-SET
TO A COMMUNICATION CONTROL PROCESSOR
By O. LEEHNARDT (applications laboratory)
The S.G.S.-THOMSON Microelectronics T57524 is
a high performance voiceband multi-standard modem chip set covering all C.C.I.T.T. and BELL
standards from 300 to 2400 bps full-duplex over public switched telephone network or leased lines. The
chip set consists of the T575240 Digital Signal Processor and the T568950/51/52 Modem Analog
Front End.
This application note details the basic interface principle between the TS7524 and the communication
control processor. Also included are architecture
examples as well as programming examples.
1. HARDWARE INTERFACE
The basic interface signals between the TS7524
and the control processor are summarized in figure
1. Data exchange between the TS75240 and the
control processor take place by means of a "mailbox" within the TS75240, accessible externally
through the 8-bit bidirectional system data bus of the
TS75240.
1.1 THE SYSTEM BUS
Its consists of three basic sections:
These two registers are each splitted in a 3-byte
word, each word being of two types: transmit and
receive.
Note: The general description of these different
status and command words (transmit and
receive) is given in appendix E. For any additional information, please refer to the
TS7524 data sheet.
1.3. INTERFACE SIGNALS
From a hardware point of view, the different resources of the control processor required to perform
the functional interface with the TS7524 are the following:
_ 1 output port line to reset the TS75240,
_ 1 external active low interrupt input (IRQ1),
_ 4 output lines for address and control (output
port or bus control signals),
_ 8 bidirectional data lines ADO/AD7 (I/O port or
bus). ADO is the least significant bit of the data bus.
1.4. RESET OF TS 75240
_ Data bus: ADO/AD7 (8 bidirectional lines)
After power-up, the first mailbox transfer will occur
only after reset of TS75240.
_ Address bus: CS Chip Select
RS Register Select
The minimum duration of the reset is 870 nsec. (5
cycles of 174 nsec. with a 23.04 MHz crystal).
_ Control bus: SR/Vii System Read/Write
SDS System Data Strobe
IRQ Interrupt Request
It is also absolutely required to reset the T575240
before changing the operational mode of the
modem (except during the V.22 bis handshake
where changing the two command words are sufficient when switching from V.22 to V.22 bis).
Note: The RESET pin, not included in the control
bus, rnust be used when interfacing the
TS7524 and the control processor (see
1.3.).
1.2. THE MAILBOX
The mailbox, located internally to the TS75240,
consists of two shift registers, each of these is 24 bit
wide:
_ the "R-IN" register, or command register, for
the data written by the control processor into
the TS75240 (data input),
_ the "R-OUT" register, or status register, for
the data written by the TS75240 into the
control processo r (data output).
AN342/0489
After all reset of TS75240, the only thing to do for
the control processor is to wait for activation of IRQ
signal by the TS75240. This activation is the first action which occurs, from the TS75240, immediately
after setting the reset signal issued by the control
processor.
During the first mailbox transfer following each reset of TS75240, all the bits of the status word (three
bytes) are not significant. The TS75240 waits forthe
first command word (three bytes) before sending significant bits in the status word during the next following mailbox transfer.
1/15
427
APPLICATION NOTE
Figure 1.
EXTAL
ICLKOUT
•
OUT. IJORT
CONTROL
PROCESSOR
RESET
.... RSCS-
OUT. PORT
or BU"
IRQt
(*)
--
~
..
TS 75240
SR/W
SDS
-
....
IRQ
INP.lOUT. PORT ,.~~~tnM~l
or BUS
(DATA
..
ADO
AD7
~-I~ I
~I ~-OLf I
~I
M88AN5·01
(') The TS75240 provides on its CLKOUT pin a clock signal at 11.52 MHz (23.04 MHz/2) which can be used by the control processor.
2. SOFTWARE INTERFACE
2.1. TRANSFER MECHANISM
Information exchange between the control processor and the TS75240 is made by enslaving the mailbox exchange to the differend Baud period (* *)
(transmit and receive) of the TS75240. The control
processor will have to be able to manage:
_ one mailbox transfer at each transmit Baud
period allowing exchange of :
one status word from the TS75240 to the
control processor,
one command word from the control processor to the TS75240 (the transmit data
belong to these bytes).
_ one mailbox transfer at each receive Baud period allowing exchange of :
one status word from the TS75240 to the
control processor (the receive data belong
to these bytes),
one command word from the control processor to the TS75240.
(* *) : Baud period corresponds to 600 Hz in Q.A.M.
(V.22 bis) and D.P.SK (V.22 and BELL 212)
2/15
428
and 1200 Hz in F.S.K. (V.21, V.23 and BELL
103).
Note: Either "RESERVED" or without change
(see appendix E), two words must be transferred at each mailbox transfer: one status
word (transmit or receive) and one command word (transmit or receive).
2.2. MAILBOX TRANSFER PROTOCOL
This section describes the functional mailbox transfer protocol. System bus timing characteristics are
given in appendix D.
Each mailbox transfer is driven by the control processor but controlled through a sequencer included in the TS75240 by means of an internal flag
(RDYOIN) and an external interrupt request signal
(IRQ).
The internal flag RDYOIN indicates whether the
TS75240 (RDYOIN = 0) or the control processor
(RDYOIN = 1) has access to the mailbox.
The external IRQ interrupt request signal is used by
the control processor to gain access to the mailbox:
This sequencer is shown figure 2.
_ The mailbox is made available to the control
APPLICATION NOTE
processor by the TS75240 program which
sets RDYOIN flag to 1.
_ IRQ is asserted (*) (IRQ = 0) by the TS75240
to indicate the availability of the mailbox (at
the same time as RDYOIN = 1),
(*) : IRQ is asserted by the TS75240 immediately
after each reset of TS75240.
_ After detecting IRQ assertion, the control processor knows that it can access the mailbox
but does not know if it has access to the bus.
It requests the bus by generating the address
CS = RS = 0 and the control signal SR/W = 1 .
A dummy read is performed by the TS75240.
_ After detecting the dummy read of its mailbox,
the TS75240 internal 1/0 sequencer answers
back by negating IRQ (IRQ = 1). The control
processor detects the negation of IRQ indicating that the mailbox is available for data
transfers.
It has now full control of the bus and the mailbox. The data exchange can be performed.
The control processor reads one status word
(SRiW = 1) and writes one command word
(SRiW = 0) in the mailbox shift registers ROUT and R-IN respectively.
After each read or write, the data is automatically shifted to allow read or write of the following byte.
_ The exchange protocol described above is
terminated by the control processor~rfor
rninfLa dummy read of the mailbox (CS = 0,
SRIW = 1) but with RS in the high state.
_ The RDYOIN flag within the TS75240 is clea-
red to 0 by this dummy read of the mailbox
and the TS75240 now has access to R-IN and
R-OUT registers within the mailbox.
_ The control processor gives the bus back to
the TS75240 by negating CS (CS = 1).
The same type of exchanges must be implernented for each transmit and receive Baud
period.
Notes: 1. Processings of the two different words
exchanged during each rnailbox transfer
must be performed after a complete mailbox transfer is implemented (Le. the mailbox transfer must be performed as fast
as possible so as to respect the real-time
task scheduling of the TS75240).
2. The internal RDYOIN flag indicates the
property of the mailbox:
for the TS75240,
1 for the control processor.
As this flag can be set only by the
TS75240 and reset only by the control
processor, this means that one of
these two devices gives the control of
the mailbox back to the other when it
finishes to use it. The control processor and the TS75240 can not request the mailbox at the same time,
but can only wait for the other to give
it back.
o
3/15
429
APPLICATION NOTE
Figure 2.
CONTROL PROCESSOR
(MASTER)
TS 75240
(SLAVE)
+
MAILBOX AVAILABLE
tisserts : IRQ (IRQ =0)
RDVOIN (ROVOIN:: J)
~--------------~+
t_
detects: IRQ
t
=0
applies : C5 =RS =0
SR/W = 1
t
..
detects: CS :: RS
+
+
=0
negates: IRQ (I RQ
~
,jetects : IRQ
t
= 1)
=1
t1AILBOX ACCESS
3 reads
(fJrst, second ood third stotus bytes)
applies: SR/W:: 0
3 writes
(first. second ood third commond bytes)
r
END OF MAILBOX ACCESS
,,,Ii,,
t
~ o. jg ~ SRiW ~ I
applies : CS = RS = SRlW =1
..
detects: CS =0, RS
+
=1
negates: RDVOIN (RDVOIN
=0)
NOTE: For proper timings, refer to the TS 7524 dahl sheet
M88ANS·02
4/15
430
APPLICATION NOTE
3. ARCHITECTURE EXAMPLES
3.1. WITH THE ADDRESS/DATA BUS·
The TS75240 asynchronous parallel port with its associated mailbox transfer allows the TS7524 chipset to be interfaced to a control processor straightforwardly and with a minimum of interface circuitry.
Examples of this type of architecture are given figure
3 (with the ST9030 microcontroller) and figure 4
(with the INTEL 8032 microcontroller).
Figure 3.
EXT AL 1.....1 - - - - - - - - - - - - - - ; CLKOUT
OUT.
PORTI-------------~·
RESET
IROI .......~------------i IRQ
ST
.. SR/W
-
-
R/W
9030
P1.7
AIS
[)
RS
..
SOS
~'-"'~"~"\N\..'"\N\..'~"\N\..'"\N\..'"\N\..~
ADO
I
AD7
OS
po.o
I
PO.7
-
• CS
....
P1.6 AI4
DO
07
DATA
TS
75240
-
M88AN5·03
5/15
431
APPLICATION NOTE
Figure 4.
XTALI
CLKOUT
OUT. PORT
RESET
IRQI
IRQ
---.-------.
LATCH ~AI
PO. I ADI
LS171:
SR/W
__ - - - __ - - - - 0°
P2.7 AIS
INTEl
PSEN
CS
8032
TS
75240
ALE
,-------------.
PO.O ADO: LATCH :AO
RS
: LSJ7J :
WR
SOS
RD
PO.D
I
PO. 7
ADO
DATA
.~¥,"""'''''''''''''''''''''''''''''''''''''+"
AD7
ADO
I
AD7
M88AN5·04
Note: An assembly program example is given in appendix C.
6/15
432
APPLICATION NOTE
. 3.2. WITH A GENERAL PURPOSE 1/0 PORT
Example of this type of architecture is given figure
5 with the HITACHI 63701 microcontrolier.
4. PROGRAMMING EXAMPLES
4.1. TRANSMIT THE 1800 Hz GUARD TONE IN
V.22 WITH 0 dB ATTENUATION
1st transmit command byte: $32 (1800
Hz, V.22)
2nd transmit command byte : $00 (0 dB
attenuation, answer)
3rd transmit command byte : $00 (transmit enabled).
4.2. TRANSMIT THE 550 Hz GUARD TONE IN
V.22 BIS WITH 10 dB ATTENUATION
1st transmit command byte: $11 (550 Hz,
V.22 bis)
2nd transmit command byte: $OA (10 dB
attenuation, answer)
3rd transmit command byte: $00 (transmit enabled).
Figure 5.
EXTAL I4r-~----------- CLKOUT
OUTPUT~P~7~O~--------------------------~IR~E~S~E-T
PORT
IRQ1
PSO
I......
~------------t
HITACHI
63701
OUTPUT
PORT
(PORT 7)
./ P74
P73
P72
'- P71
--
IRQ
TS
75240
.. RS--
CS
-
SR/W
...... SOS
M88AN5·05
Nole : A flowchart and an assembly program example are given in appendix A and B.
7/15
433
APPLICATION NOTE
APPENDIX A
MAILBOX EXCHANGE INTERRUPT ROUTINE FLOWCHART (with 1/0 port architecture)
INIT, CONTROLS: CS=R5=O, SR/W=SDS= I
CONTROL PROCESSOR
'" , I , , , '']
ADO
AD7
TS 75240
T575240
1
READ 2nd TRANS. STATUS Bm
CONTROL
PROCESSOR
READ 3rd TRANS, ST ATUS BYTE
M88AN6-06
8/15
434
APPLICATION NOTE
MAILBOX EXCHANGE INTERRUPT ROUTINE FLOWCHART (continued)
WRITE 1st TRANS. COMMAND BYTE
WRITE 1st REC. COI't1AND BYTE
CONTROL
PROCESSOR
1
WRITE 2nd TRANS. COMMAND BYTE
1575240
M88AN5-06
9/15
435
APPLICATION NOTE
APPENDIX B
This programming example in 63?01 Assembler language is related to the circuit shown in figure 5 and gives
an example of mailbox exchange interrupt subroutine.
IRQ1
LDD
STM
STAB
STAA
STAB
LDM
LSRA
#$E?E5
PORT?
PORT?
PORT?
PORT?
PORT3
IR RESULT IS e
(eS = RS = 0, SDS = SR/W = 1)
(dummy
(SDS = 0)
read)
(SDS = 1)
(SDS = 0)
("0" if transmit, "1" if receive)
LDAA
STAA
LDAA
STAA
STAB
LDAA
STAA
LDAA
STAA
STAB
LDAA
STM
LDM
STM
PORT3
STARE1
#$E?
PORT?
PORT?
PORT3
STARE2
#$E?
PORT?
PORT?
PORT3
STARE3
#$E?
PORT?
LDAB
STAB
LDM
STAA
LDAB
STAB
#$E3
PORT?
#$FF
P3DDR
#$E1
PORT?
LDAA
STAA
LDAA
STAA
STAB
LDAA
STAA
LDAA
STM
STAB
LDAA
STAA
eOMRE1
PORT3
#$E3
PORT?
PORT?
eOMRE2
PORT3
#$E3
PORT?
PORT?
eOMRE3
PORT3
(write 1st receive
command byte)
LDM
STM
LDM
STAA
STAB
LDAA
STM
PORT3
STATR1
#$E?
PORT?
PORT?
PORT3
STATR2
(read 1st transmit
status byte)
(read 1st receive
status byte)
(SDS= 1)
(SDS= 0)
(read 2nd receive
status byte)
(SDS = 1)
(SDS= 0)
(read 3rd receive
status Byte)
(SDS = 1)
(SRIW= 0)
(PORT3 = OUTPUT)
(SDS= 0)
(SDS= 1)
(SDS = 0)
(write 2nd receive
command byte)
(SDS= 1)
(SDS= 0)
(write 3rd receive
command byte)
ELSE
10/15
436
(SDS= 1)
(SDS = 0)
(read 2nd transmit
status byte)
Gi
SGS·ntOMSON
~I IN:ilU©~~IiI@IllU©i11
APPLICATION NOTE
APPENDIX 8(continued)
LOAA
STAA
STAB
LOAA
STAA
LOAA
STAA
#$E?
LOAB
STAB
LOAA
STAA
LDAB
STAB
#$E3
PORT?
(SOS = 0)
LOAA
STAA
LOAA
STAA
STAB
LOAA
STAA
LOAA
STAA
STAB
LOAA
STAA
COMTR1
PORT3
(write 1st transmit
command byte)
PORT?
PORT?
PORT3
STATR3
(SOS = 1)
(SOS = 0)
(read 3rd transmit
status byte
#$E?
PORT?
PORT?
(SOS = 1)
(SR/W= 0)
#$FF
P300R
(PORT3 = OUTPUT)
#$E1
#$E3
PORT?
PORT?
COMTR2
PORT3
(SOS = 1)
(SOS = 0)
(write 2nd transmit
command byte)
#$E3
PORT?
PORT?
COMTR3
PORT3
(SOS = 1)
(SOS= 0)
(write 3rd transmit
command byte)
ENDS
LOO
STAA
STAB
LOO
STAA
STAB
STAA
LOAA
STAA
RTI
Note:
#$E300
PORT?
P300R
(SOS = SRIW = 1)
(PORT3 = INPUT) .
#$F?F5
PORT?
PORT?
PORT?
(RS = 1)
(SOS = 0)
(SOS = 1)
#$FF
PORT?
(CS
= 1)
See note appendix C.
11/15
43?
APPLICATION NOTE
APPENDIX C
This programming example in 8032 Assembler language is related to the circuit shown in figure 4 and gives
an example of mailbox exchange interrupt subroutine.
The TS75240 is accessed at three address locations:
IR01
IR011
IR012
Note:
12/15
438
DSPREA
DSPWRI
DSPEND
EOU
EOU
EOU
8002W
8000H
8003H
Read address with RS = 0
Write address (RS ::..ill
Read address with RS = 1
MOV
DPTR,#DSPREA
(read of TS75240)
CLR
MOVX
MOVX
RRC
EA
A,@DPTR
A,@DPTR
A
(interrupt disabled)
(dummy read)
(read the first status byte)
JNC
IR011
Uump if "0" (transmit))
RLC
MOV
MOVX
MOV
MOVX
MOV
MOV
MOV
MOVX
A
STARE1, A
A,@DPTR
STARE2, A
A,@DPTR
STARE3, A
DPTR, #DSPWRI
A, COMRE1
@DPTR,A
MOV
MOVX
MOV
MOVX
A, COMRE2
@DPTR,A
A, COMRE3
@DPTR,A
(read 1st rec. status byte)
(read 2nd rec. status byte)
(read 3rd rec. status byte)
(write of TS75240)
(write 1st rec. command byte)
(write 2nd rec. command byte)
(write 3rd rec. command byte)
JMP
IR012
RLC
MOV
MOVX
MOV
MOVX
MOV
A
STATR1, A
A,@DPTR
STATR2, A
A,@DPTR)
STATR3, A
MOV
DPTR, #DSPWRI
(write of TS75240)
MOV
MOVX
MOV
MOVX
MOV
MOVX
A, COMTR1
@DPTR,A
A, COMTR2
@DPTR,A
A, COMTR3
@DPTR,A
(write 1st tra. command byte)
MOV
MOVX
SETB
RETI
DPTR, #DSPEND
A,@DPTR
EA
(RS = 1)
(dummy read)
(interrupt enabled)
(read 1sttra. status byte)
(read 2nd tra. status byte)
(read 3rd tra. status byte)
(write 2nd tra. command byte)
(write 3rd tra. command byte)
STARE1, STARE2 and STARE3 (resp. STATR1, STATR2, STATR3) are microcontroller RAM locations used to save the receive (resp. transmit) status bytes read from the TS75240.
COMRE1, COMRE2 and COMRE3 (resp. COMTR1, COMTR2. COMTR3) are microcontroller RAM locations which contains
the receive (resp. transmit) command bytes to be written into the TS75240,
APPLICATION NOTE
APPENDIX D
SYSTEM BUS TIMING CHARACTERISTICS
ClKOUT
tSPW
50s
S~IW l!lJ
~
tSAw
~
~
--.
RS
...
ADO
t SDSR
flj / / III, '1/1/,'/
~IlI;lR
DATA IN
I
AD7
tpSDSW•
ADO
~
I
«««(
...
!SIl7W..
.....
DATA OUT
AD7
...
~
1» )_
'SOHW ~
3-5
...CVClE~
~
~
/p
IRQ
M88T57254-14
Symbol
Parameter
Min.
Max.
Unit
tspw
SDS Pulse Width
60
ns
tSAW
SRIW, CS, RS Set-up Time
20
ns
tSAH
SRIW, CS, RS Hold After SDS High
5
ns
tSDSR
Data Set-up Time, Read Cycle
20
ns
tSDHR
Data Hold Time, Read Cycle
tpSDSW
Data Propagation Delay, Write Cycle
tSDHW
Data Hold Time, Write Cycle
tSDzW
SDS High to Data High Impedance, Write Cycle
Vee
ns
5
35
10
ns
ns
40
ns
= + 5 V ± 5 %, 0 °C < Tamb < + 70°C unless otherwise specified.
13/15
APPLICATION NOTE
APPENDIX E
TRANSMIT/RECEIVE STATUS WORDS
TRANSMIT STATUS WORD
BIT
STATR1
0
Transmit (0)
STATR2
STATR3
Reserved
Reserved
1
-
2
3
-
Reserved
4
-
-
5
6
7
RECEIVE STATUS WORD
BIT
STARE1
0
Receive (1)
1
DO
Data Before
2
D1
Descrambling
3
D2
STARE2
STARE3
Reserved
Reserved
(QAM. , D.P.S.K.)
DO
Data
D2
Descr.
r-D1 After
r--
Equalization Status
D3
Reserved
Signal Quality
6
S1 Sequence
Carrier Detect
1
1
7
S1 Seguence or
Call Progress Tone Det
Reserved
4
5
Note:
14/15
440
D3
(Q.A.M.,
D.P.S.K.)
DO
r-D1
r-D2
r-D3
r-D4
r-D5
Data
(F .S.K.)
Answer Tone Detect
In QAM and DP8K modes, both for the data after and before descrambling, the unused bits are set to "1" by the T87524.
APPLICATION NOTE
APPENDIX E (continued)
TRANSMIT COMMAND WORD
BIT
0
1
2
3
4
5
6
7
Note:
COMTR1
COMTR2
COMTR3
Trans. Mode Selection
0000 : Modem Disabled
0001 : V.22 Bis
0010:V.220011 :B212
0100 : V.23 0101 : V.21
0110: Bell 103
0111 : D.T.M.F.
Transmit Signalling
00 : Signalling Dis.
01 : 550 Hz
11 : 1800 Hz
Reserved
--
answ/ori or DTMF
Transmit (0)
D
P
S
K
Q
D2
0
A
M
D3
0
Scrambler (ON/OFF)
D4
0
0
0
Reserved
D5
0
0
0
DO
Transmit
Attenuation
D1
-
V.22 Binary Rate Select
or DTMF
I--
F
S
K
D
T
M
F
f--
Transmit Enable
All the "RESERVED" bits must be cleared to "0" by the user.
RECEIVE COMMAND WORD
BIT
0
COMRE1
r-1
r--
0000 : Modem Disable
0001 : V.22 Bis
0010:V.220011 :B212
2
0100 : V.23 0101 : V.21
f--- 0110: Bell 103
3 0111 : CALUPROG. Tone
4
COMRE2
REC. Mode Selection
Reserved
Reserved
Answer Tone Selection
5
Tx Synchronization
6
Carrier Detect Level
Reserved
7
Answer/originate
V.22 Binary Rate Select
Note:
COMRE3
Receive (1)
Descrambler (ON/OFF)
All the "RESERVED" bits must be cleared to "0" by the user.
15/15
441
APPLICATION NOTE
USING A TS7515 SINGLE CHIP V.22/BELL
212A MODEM AROUND 80C51 MICROCONTROLLER
1. INTRODUCTION
This application note must be used in addition with
the TS7515 data sheet to show the way to use this
single chip V.22/8ell 212A modem around the
80C51 microcontroller. The goal of this note is not
to explain the block diagram of a complete modem
board but rather to give some indications about
using and interfacing the TS7515 and the 80C51 in
the best way.
2. DESCRIPTION
In these typical applications, the TS7515 is used in
conjonction with a 80C51 microcontroller and an
EF6850 U.A.R.T.
TxSCLK is the filter sampling clock (in Hz).
In this mode, the DCD pin behaves like a fast carrier detect and the filter bandwith so programmed is
the initial bandwith of receive filter ( 400 Hs in answer or originate mode) multiplied by the clock ratio.
The D.T.M.F. dialing is performed through the
TS7515 external pin (EXI) via the EFG7189
D.T.M.F. dialer.
Example: To detect the 440 Hz dialing invite tone,
the TS7515 will have to be programmed in answer
mode (Ala = 0) and the sampling clock to be applied to it will be :
210 x 440
= 76.8 kHz
TxSCLK =
1200
The CMOS 4024 circuit is used to generate the different clocks required for the "call progress" mode.
In this mode, by programming the RTS pin to 5 V
and the A/S pin to 0 V, the TS7515 behaves like a
clock programmable receive filter whose center frequency can be calculated through the following formula:
Fm x TxSCLK
Fc= - - - - 210
Which is the crystal frequency (4,9152 MHz) divided
by 64 (26 ).
In this case the filter bandwith will be: 145 Hz
440
(400 x 1200 )
Where: Fc is the filter center frequency (in Hz)
Fm is the carrier frequency (in Hz)ln modem mode
(i.e 1200 or 2400 Hz according to Ala pin: Answer
or Originate)
The three states of the TS7515 RTS and TL pins
are performed through a dual general purpose operational amplifier according to following way:
15 K
10 K
PIN
12
>--------------~
+
M88AN4-01
11
12
OV
OV
+5V
+5V
OV
+5V
OV
+5V
AN343/0489
Pin
OV
+5V
-5V
Undefined
1/3
443
t I'"w
OJ
.j::.
?';
Q
g
~
BELL 212 A ASYNCHRONOUS 10 BITS
'"'c:"
WITH D.T.M.F. DIALING
"'3
ro
c:
:J
Vss
()
""'ro-
"-
'<
!i5U1
~:i!
!lIO
1llli:
",UI
Ili
Vee
EN
'"
'"
"0
()
~
W HTout
~
0
:I:
I GNO
OC
~~;6
f.?
§
:tJ
OV
00 ADO
0
1Q
:~
6;
30
A2
03 AD3
~4Q~A/O
40
4Q
A3
04
~g ~ ~6
~:
"
v"
ov
.5V
OJ
-I
en
::iE
=i
:I:
C
-I
CLS
5V
i>
cz
~
CiB
OV
RxD
0
."
47pF f 4 9152 MH147PF
D7
en
OV
elK
f-J"'"'---
C
~
~l
H~R
eTS
OCD
AD1
;g;
elK
R~~
A13 CS2
TEST
DCD
TxSCLK
r
Tvss
1.,F
RDI
RxSCLK
To
RFO
0
....
\L2
OV
OV
~I-WRI--
TPh
/Tph
DAA
eE
GND,
k
ATOf------
PSEN
~~~~~~
I\,)
I'--OSCout
f2
3D
~g!
....
»
»
en
I\,)
m OSCin
~
70 ISA
PO:3
ADS
PO.6 AD6
o
o
-.=
5V
V-
PO"2 AD2
~~:~
0-
!'lin
",UI
@.
EA ALE
=g~ ~g~
g
~
I
YT T
Vee
v+
m
rr-
40 0
pm
:;
0-
OV
10 A
2Q B
30 C
<0
o
+5V
C
C>
»
'tI
'tI
r
()
»
-I
o
Z
Z
o-I
m
<
N
OV
"5V
~
N
»
CJ)
Q
"
10
20
30
40
70
c
~
V.22 ASYNCHRONOUS 10 BITS
'"
~
WITH D.T.M.F. DIALING
-<
z
o
:I:
:tJ
3
o
:>
'"C;
0-
m
c
:>
5V
OV
5V
V"
V"
ADO
PO.D
AD1
PO.l
'""-CD
PO.2
PO.3
rr
POA
PO.S
'<
PO.6
PO.l
0
0
~
~~
~;!
@.
~O
""I:
@UI
~O
1=
AD2
AD3
AD4
ADS
AD6
AD7
OC
EN
40 ~4Q
'= 1
--,.------------,
CIRCUIT "DATA SET READY" ACTIVATED
,
--.------------I
DFTECTION OF UNSCRAMBLEO 1
155 ± 50 ms OR
DETECTION TONE 2225 Hz
~
TEST TEST -DURING 1551:50 ms?
I
I
TEST ANSWER ruNE 2225 Hz?
OR
---1-----1
,
I
---t----rRANSMISSION
SCRAM8l.ED1
DETECTION
SCRAM8lE01
2701:40 ms
1
I RTS=SB.o
I CTx D.l)
--------
-,-, ----I
I
1
TESTRxD.1
DURING 270 ± 40 ms?
_1 _ _ _ _ _ _ -
I
I CIRCUIT "CARRIER DETECT" ACTIVATED
I
1
--.----------------I
I
__ L ________________ _
I
CflcUIT-ct£ARTOSENO"ACTlVATED
I
1
-+----------------I
I
lHANSFERID"OATA" MODE
Note: Assumed to be in 1200bps, asynchronous, 10 bits, with maximum overspeed authorized and not in test loop mode.
2/3
448
APPLICATION NOTE
Figure 2: Handshake Sequence in V.22 (Automatic Answer Mode).
INITIAlISATION (SEE NOTE)
CthBRS~AIo_ Ats.o
RTS- ReATE =CLS-OSE -SEI-1
AND
SILENCE 2150 ± 350 ms
_1- _ _ _ _ _ _ _ _ _
_ ______ _
1
r-------~-------,
TRANSMISSION
I
ANSWER TONE (2100 Hz)
I
3300± 700 ms
I
-1-------
CIRCUIT-DATA SET READY" ACTIVAlID
I
I
-,------I
RTS.OTx D .. 1
OR
RTS" _
ATE- _0
TESTf\D.l
TRANSMISSION
UNSCRAMBLED
DURING
270±40ms?
CIa- _1
DETECllON
1 AND 1800 Hz OR
I
I
I
ANSWER TONE (222S Hz)
SCRAMBLED 1
270±40 ens
2225Hz
-'------J
I
SEI-Tx D-1
TRANSMISSION SCRAt.eLED
1 AND 1800Hz
765± 10 ms
(Cis-O ATE .. 1 IF)
----
-~------
CIRCUIT "ClEAR TO SEND"
AND -cARRIER DETEC1" ACTII/ATED
-'------J
I
J I ______ _
I
TFlANSFER TO "DATA" MODE
I
I
Note: Assumed to be in 1200bps. asynchronous, 10 bits, with maximum overspeed authorized and not in test loop mode.
3/3
449
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
i
I
I
i
I
I
I
I
!
I
I
I
I
I
i
I
I
I
i
I
I
I
I
I
!
I
i
I
I
I
I
I
I
I
I
I
I
I
APPLICATION GUIDE
APPLICATION GUIDE TO THE USE OF THE TS7515
SINGLE CHIP MULTI-STANDARD DPSK AND FSK MODEM
INTRODUCTION
This application note is a complete guide to the realization of a multi-standard modem by using the
TS7515 FSK and DPSK monochip from SGSTHOMSON Microelectronics.
The note successively describes the main characteristics of the TS7515 and its functional operation.
AN345/0489
Then a detailed background of V.22, Bell 212A and
Bell 103 standards is given before pating in application the advanced features of the device. The microprocessor software modules necessary to a
complete application are also provided with general
precautions hints.
1/63
451
TS7515
TABLE OF CONTENTS
Pages
1 - MAIN CHARACTERISTICS OF TS7515
5
1.1 - General Features
5
1.2 - Pin Configuration
5
1.3 - Description of Pins
6
1.4 - General Description & Block Diagram
7
1.5 - Functional Description
8
1.5.1 - TRANSMIT SECTION
8
1 .5.2 - RECEIVE SECTION
8
1.5.3 - COMMON UNITS
9
1.6 - Functional Characteristics
9
1.6.1 - ASYNCHRONOUS TO SYNCHRONOUS CONVERTER
9
1.6.2 - SYNCHRONOUS TO ASYNCHRONOUS CONVERTER
10
1.6.3 - SCRAMBLER & DESCRAMBLER
11
1.6.4 - CARRIER & TONE GENERATORS
14
1.6.5 - TRANSMITTED SPECTRUM
14
1.6.6 - FILTERS
1.6.6.1 - Transmit Filter
1.6.6.2 - Receive Filter
15
15
15
1.6.7 - LEVEL DETECTOR
15
1.6.8 - SYNCHRONOUS DEMODULATOR
1.6.8.1 - Demodulator Block Diagram
16
16
1.6.9 - SUMMARY TABLES OF OPERATING MODES
1.6.9.1 - Synthesis of different modes for Receive Section
1.6.9.2 - Synthesis of different modes for Transmit Section
1.6.9.3 - Mode selection in Phase modulation transmission
1.6.9.4 - Test pin
16
16
17
17
17
2 - DETAILED DESCRIPTION OF V.22 & BELL 212A STANDARDS
18
2.1 - Foreword
18
2.2 - V.22 Standard
18
2.2.1 - GENERAL DESCRIPTION
2.2.1.1 - Variant A
2.2.1.2 - Variant B
2/63
452
18
18
18
TS7515
2.2.2 - ON-LINE SIGNALS
2.2.2.1 - Carrier frequency and guard tone
2.2.2.2 - Levels of transmitted data signals & Guard Tone
Pages
18
18
18
2.2.3 - FIXED DELAY COMPROMISE EQUALIZER
18
2.2.4 - SPECTRUM & GROUP PROPAGATION TIMES
18
2.2.5 - MODULATION
2.2.5.1 - Bit Rate
2.2.5.2 - Data Bits Coding
19
19
19
2.2.6 - FREQUENCY TOLERANCE OF THE RECEIVED SIGNAL
20
2.2.7 - CONNECTOR PINS
2.2.7.1 - Summary of pins
2.2.7.2 - Thresholds of Pin 109
2.2.7.3 - Pin 111 & Bit Rate Control
2.2.7.4 - Electrical characteristics of connector pins
2.2.7.5 - Error conditions of connector pins
20
20
20
20
20
21
2.2.8 - DTE/DCE INTERFACE MODES OF OPERATION
2.2.8.1 - Variant A
2.2.8.2 - Variant B
21
21
21
2.2.9 - TRANSMITTER
21
2.2.10 - FUNDAMENTAL BIT RATE
21
2.2.11 - BREAK SIGNAL
21
2.2.12 - RECEIVER
21
2.2.13 - SCRAMBLER & DESCRAMBLER
2.2.13.1 - Scrambler
2.2.13.2 - Descrambler
22
22
22
2.2.14 - SEQUENCE OF OPERATION
2.2.14.1 - Channel & Operating Mode Selection
2.2.14.2 - Operation on switched telephone lines
2.2.14.3 - Modem in Originate Mode
2.2.14.4 - Modem in Answer Mode
24
24
24
26
26
2.2.15 - MEASUREMENT FACILITIES (MAINTENANCE)
2.2.15.1 - Type 2 loopback establishment
2.2.15.2 - Suppression of type 2 loopback
26
26
26
2.3 - BELL 212A Standard Description
3 - TS7515 APPLICATIONS
26
34
3.1 - Introduction
34
3.2 - Application Diagram
34
3/63
453
TS7515
3.3 - Modem Configuration Switches
Pages
35
3.4 - Terminal Interface
37
3.5 - Line Interface
38
38
39
39
39
39
3.5.1 - 4-WIREl2-WIRE CONVERSION
3.5.2 - GALVANIC ISOLATION
3.5.3 - LINE CURRENT REGULATION
3.5.4 - RING DETECTION
3.5.5 - PULSE DIALING
4 - DESCRIPTION OF SOFTWARE
4.1 - Definition of Software Modules
42
42
4.1.1 -IDLE STATE MANAGEMENT MODULE
42
4.1.2 - CCITT HANDSHAKE MODULE
42
4.1.3 - BELL HANDSHAKE MODULE
42
4.1.4 - CCITT TRANSM ISSION. MODULE
42
4.1.5 - BELL TRANSMISSION MODULE
42
4.1.6 - RDL HANDSHAKE MODULE
42
4.1.7 - LOOP 2 RECEIVE HANDSHAKE MODULE
42
APPENDIX A - TS7515 HANDLING PRECAUTIONS
58
A.1 - Power supplies decoupling & layout considerations
58
A.2 - Carrier Recovery Loop
58
A.3 - Frequency Precision of Crystal Oscillator
58
APPENDIX B - GLOSSARY OF TERMS
59
APPENDIX C - BIBLIOGRAPHY
62
4/63
454
TS7515
1 - MAIN CHARACTERISTICS
OF TS7515
1.1 - General Features
The TS7515 is a single chip voice-band modem
compatible with BELL 212A, CCITT V.22 A and B
standard requirements.
• Includes both Receive and Transmit Filters.
• Designed using analog and digital techniques.
• Requires standard 4.9152 MHz crystal oscillator.
• Buffered clock output for microprocessor-based
applications.
• Low power consumption - CMOS technology.
• High adjacent channel signal rejection.
• Fixed equalization in transmission and reception.
• Maintenance loop: type 2 and 3.
• Carrier detect output.
• CCITT and BELL answer tones.
• 1200 and 600 bps synchronous operation in
DPSK mode.
• 1200 and 600 bps + 1 %, - 2.5 % or + 2.3 %,
- 2.5 % asynchronous operation in DPSK mode.
• 8-, 9-, 10-, 11-bit character format in asynchronous mode of operation.
• 0 to 300 bps data rate in FSK operation.
• Break signal supervision.
• Special line monitoring facilities.
Main Operating Modes
• BELL 212NBELL 103N.22 Standard Selection.
•
•
•
•
•
•
•
•
•
Answer tone selection.
Fallback Mode selection.
Originate/Answer Channel Selection.
Synchronous/Asynchronous Mode Selection.
Character length selection in asynchronous
mode.
Overspeed Selection.
Scrambler Selection.
Guard tone selection in V.22 mode.
Analog/Digital test loop Selection.
1.2 - Pin Configuration
v+
XtalOUT
ATE
XtaiiN
CIB
ClK
AIS
TxSClK
Tl
OSE
TxClK
TxD
BRS
RTS
RxD
SEI
RxCLK
TEST
DCD
ClS
GND
A/O
RAI
EXI
RDI
ATO
RFO
vM88TS7515-01
5/63
455
TS7515
1.3 - Description of Pins
Pin 1 : V+
Positive power supply: 5 V ± 5 %
Pin 2 : ATE (Answer Tone Enable)
This pin allows to configure the device in either modem mode or as a transmitter of pure frequency
(answer tone).
_ A logic low (0) signal applied to this pin causes
the device to output through ATO (Analog Transmit Output) pin a pure sinewave whose frequ~n
c~ends on the programming of C/B
(CCITT/BELL) pin.
_
_ Inversely, a logic high (1) on ATE pin will configure the device in modem mode.
Pin 3 : C/S (CCITT/BELL)
This three-state input selects one of CCITT V.22
and BELL 212A standards.
Pin 4 : A/S (Asynchronous/Synchronous)
In DPSK mode, this three-state input selects Asynchronous or Synchronous mode of operation. In
asynchronous operation, it also provides the character length selection.
rate 16 times faster than modem's modulation
rate.
Pin 10 : TEST
The output signal is available on this pin before passing through the descrambler. This pin is intended
for "handshake" and "remote loop request" purposes.
Pin 11 : DCD (Data Carrier Detect)
This pin will go low when device receives a signal
level higher than - 43 dBm on RDI (Receive Demodulator Input) pin and goes high if the signal level is
lower than - 48 dBm. The - 43 dBm to - 48 dBm
range provides a 5 dB hysteresis for the initiation of
DCD function.
Pin 12 : CLS (Character Length Selection)
In conjunction with A/S pin, this input selects the
character length.
Pin 13 : RDI (Receive Demodulator Input)
This input receives analog signals and directs them
to comparators associated with demodulator and signal detector. The signal is also applied to various
demodulation circuitry.
Pin 5 : TL (Test Loop)
Three-state input pin for the selection of Test loop 2
or Test loop 3.
Pin 6 : OSE (Over Speed Enable)
In asynchronous mode, this input selects one of two
possible over speed configurations available in
CCITT standard recommendations.
Pin 7 : BRS (Binary Rate Selection)
This pin is used for the selection of binary rate as
follows:
_ a logic low (0) signal on this input configures the
device to receive and transmit data at 1200 bps,
_ a logic high (1) signal applied to this input enables
the circuit to receive and transmit data at 600 bps
in CCITT mode or 300 bps in BELL 212A mode.
Pin 8 : RxD (Receive Data)
This output provides binary data provided by the demodulator.
Pin 14 : RFO (Receive Filter Output)
The analog signal first goes through various bandpass and equalization filters and is then available at
this output pin.
Access to this pin simplifies in particular the device
test procedures.
While designing an application, and as far as possible, the P.C. Board layout must be so arranged that
RFO output could be coupled to RDI input terminal
through a single capacitor as close as possible to
the device.
Pin15:V·
Negative power supply: - 5 V ± 5 %
Pin 16 : ATO (Analog Transmit Output)
In conjunction with analog applied to ATE (Answer
Tone Enable) terminal, this output delivers either a
modulated carrier or an answer tone.
Pin 9 : RxCLK (Receive Clock)
Pin 17 : EXI (External Tone Input)
This output corresponds to Modem's receive bit
clock.
_ In synchronous mode, the clock is synchronized
with data output through RxD pin.
_ In asynchronous mode, this pin delivers a clock
With RTS (Request To Send) terminal at logic "1 ",
this analog input accepts an external tone which will
be first filtered and then routed to ATO (Analog
Transmit Output) terminal.
6/63
456
TS7515
Pin 18 : RAI (Receive Analog Input)
This is input terminal to the receive filter. Signals received via line are applied to this pin.
Pin 19 : A/O (Answer/Originate)
Signal level applied to this pin selects modem's operating mode (Answer or Originate) as follows:
A "0" applied to this pin selects Answer mode.
A "1" applied to this pin selects Originate mode.
Note: In answer modem, upper channel (2400 Hz)
and guard tone (1800 Hz) may be transmitted simultaneously, provided that the guard
tone power level is 6 dB less than that of modulated 2400 Hz signal. Transmission of this
guard tone is enabled through C/B terminal.
Pin 20 : GND
This is the ground terminal common to all digital and
analog sections of TS 7515.
Pin 21 : SEI (Scrambler Enable Input)
This input enables the scrambler operation.
A "0" applied to this input enables the scrambler.
A "1" applied to this input disables the scrambler.
Pin 22 : RTS (Request To Send)
With a logic level "1" applied to this pin, the device
outputs through ATO pin the signal delivered by EXI
terminal.
With a logic level "0" on this pin, the circuit delivers
through ATO terminal asignal whose characteristics
are determined by the state of ATE terminal.
With this pin at logic level "-1 ", the TS 7515 is configured as a programmable filter. That is, TxSCLK input becomes a clock input' running at a frequency
equal to twice the sampling frequency ofthe receive
filter, that may be assigned to upper or lower channel, in accordance with signal level applied to AlO
terminal. In this configuration of RTS, the signal originated through DCD terminal is the exact representation of the tone envelope detected via line.
Pin 23 : TxD (Transmit Data)
This input receives the data transmitted by terminal.
In DPSK and FSK operating modes, these data bits
(1 and 0) determine the phase (for DPSK) orthe frequency (for FSK) of the signal output through ATO
pin.
Pin 24 : TxClK (Transmit Clock [Generated by Modem])
In the absence of TxSCLK, this output delivers the
bit clock transmitted by the modem for the synchronization of data output through TxD terminal.
BRS selects the frequency as follows:
BRS = 0 ---7 TxCLK = 1200 Hz
BRS = 1 ---7 TxCLK = 600 Hz
Pin 25 : TxSCLK (Transmit Clock [Generated by Terminal])
This input corresponds to bit clock generated by the
terminal whose frequency is 1200 Hz if BRS = 0 and
600 Hz if BRS = 1. This clock allows to lock the modem's internal clock on the clock generated by terminal, thus providing synchronization between
these two clocks.
Pin 26 : ClK (Clock)
This is buffered output of the clock running at
4.9152 MHz.
Pin 27 : Xtal in (Oscillator Input)
This pin corresponds to the oscillator's input inverter. It is normally connected to an external crystal
but may also be fed by a pulse generator. The crystal frequency must correspond to standard frequency of 4.9152 MHz.
Pin 28 : Xtal out (Oscillator Output)
This pin corresponds to the output of an inverter with
sufficient loop gain to trigger and maintain the crystal oscillation.
1.4 - General Description & Block Diagram
TS 7515 is an integrated circuit manufactured in silicon gate CMOS technology. Device includes major modem functions required for simultaneous
bidirectional transmission of asynchronous or synchronous data in accordance with the following
standard requirements:
_ CCITT V.22 variants A & B.
_ BELL 212A DPSK operation.
_ BELL 103 FSK.
This modem operates using channel multiplexing
techniques by frequency allocation of 600 bauds for
modulations rate and 1200 bits/s (600 bits/s in fallback mode) for transmission rate.
Transmission mode for each channel is Differential
Phase Shift Keying (DPSK) modulation combined
with on-line synchronous transmission. This feature
is entirely reversible, i.e. operation is possible in either of Originate or Answer modes.
When used in combination with appropriate line and
controller circuits, this device can operate on both
2-wire switched telephone network and all point-topoint leased lines.
7/63
457
TS7515
Figure 1 : TS7515 Block Diagram.
EXI
SEI
TRANSMIT FilTER
WITH FIXED
COMPROMISE
EOUALIZA TlON
hD
ATO
RECEIVE FilTER
WITH FIXED
COMPROMISE EDUALIZATIO"l
TxSClK
REFERENCE VOLTAGES
TxCLK
RAI
RFO
RDI
DCD
AMPLIFIER AND
LlMllloH
CARRIER DETECTION
RxD
FSK DEMODULATOR
TEST
RxClK
V+
X tal IN
GND
X tal OUT
ClK
n::
ATE
CIS
AiS
CLS
OSE
M88TS7515-03
8/63
458
TS7515
1.5 - Functional Description
The device is organized in 3 distinct sections:
_ Transmit section.
_ Receive section.
_ Common units.
1.5.1 - TRANSMIT SECTION
This section comprises:
_ An asynchronous to synchronous converter
whose duty is to accept chain of asynchronous
characters and to convert it to a form suitable for
1200 bits/s or 600 bits/s + 0.01 % synchronous
transmission.
This converter meets in all respects CCITT
standard requirements defined in Chapter"4.2.1"
of V.22 recommendations.
In synchronous mode of operation, the converter
is disabled.
A variable ratio divider used for the generation of
eight different frequencies:
1200 Hz± 0.5 Hz DPSK lower channel (Originate
Mode)
1800 Hz ± 20 Hz Guard tone transmitted optionally with upper channel
2100 Hz± 16 Hz Answer tone (CCITT Standards)
2400 Hz ± 1 Hz DPSK upper channel (Answer
Mode)
2225 Hz ± 16 Hz Answer tone (BELL Standards)
or FSK upper channel
2025 Hz ± 10Hz FSK upper channel
1270 Hz ± 5 Hz FSK lower channel
1070 Hz ± 5 Hz FSK lower channel
A transmit clock generator using a phase-locked
loop circuit in order to lock the transmission clock
onto either the clock generated by data terminal
or the receive clock.
A data scrambler in accordance with CCITT
standard requirements as defined in "Chapter
5.1" of V .22 recommendations.
A buffer circuit that stores the last phase of the
carrier and generates appropriate phase shift
thus providing the new phase shift to be applied
to the carrier.
A carrier generator that uses two sub-carriers
over modulated in amplitude, to synthesize the
DPSKsignal.
A transmit filter whose frequency response is determined by selected mode of operation (Originate or Answer).
A non switched smoothing filter that removes
clock transients and rejects out-of-band frequencies.
1.5.2 - RECEIVE SECTION
This section includes:
_ An anti-aliasing filter
_ A band-pass receive filter whose frequency response depends on the selected mode of operation.
_ A compromise equalizer filter that provides appropriate functional performance on a variety of
lines.
_ A phase-locked loop for the recovery of carrier signal frequency so as to perform a coherent differential phase demodulation on received signal.
_ A demodulator.
_ Two low-pass digital filters for the extraction of
Eges Pattern.
_ A decision making module that converts the eyes
pattern into logic signals, stores them, detects the
phase shift and performs identification of the received data.
_ A synchronization unit that recovers the modulation time base and delivers RxCLK (Receive signal Clock) to the data terminal.
_ A delayed hysteresis level detector that meets
CCITT standard requirements of connector pin
109 as defined in "Chapter 3.3" of V.22 recommendations.
_ A data descrambler in accordance with CCITT
V.22 recommendations.
_ A synchronous to asynchronous converter
whose duty is as follows :
- Accept chain of characters originated from a
V.22-type asynchronous modem operating in
transmit mode, demodulated by a V.22-type synchronous demodulator.
- Recoverthe initial character chain applied to the
asynchronous to synchronous converter of the
transmitting modem.
This synchronous to asynchronous converter
meets in all respects the CCITT standard requirements as defined in"Chapter 4.2.2" of V.22 recommendations.
The converter is disabled in synchronous mode
of operation.
1.5.3 - COMMON UNITS
This section includes:
A time base generator that uses a standard
4.9152 MHz crystal oscillator to derive all internal clock frequencies required for modulator and
demodulator operation.
_ A reference voltage generator delivering an internal reference voltage for:
- Amplitude clamping of the transmitted signal.
- Definition of demodulator's two threshold detection levels.
9/63
459
TS7515
1.6 - Functional Characteristics
Asynchronous/Synchronous & Synchronous/Asynchronous Converters
Operating principles of these converters are covered in Sections 4.2.1 and 4.2.2 of CCITT V.22 recommendations.
1.6.1
ASYNCHRONOUS/SYNCHRONOUS
CONVERTER
a) If data to be transmitted is generated at a rate lower than 1200 bits/s (but within the over speed
selection limits imposed by OSE), the converter
will insert the necessary stop elements as illustrated by timing diagram below.
These converters are employed only in the case of
variant B configuration.
OTE transfers to the converter the data to be
transmitted at a rate lower than 1200 bitS/s
~
______~IIL~______~IIL~______~
:::f1~______~1 L'~
______
~
_ _---JI LC
~I LI~______~I
l.C
t
t
Converter transfers to the modulator the data to
be transmitted at 1200 bitsls
Stop element inierted by
converter
M88AN64 T-01
b) If data to be transmitted is generated at a rate higher than 1200 bits/s (but within over speed selection limits imposed by OSE), the converter will
suppress the stop elements as shown in timing
diagram below.
DTE transfers to the conwrter the data to be
transmitted at a rate than 1200 bin/s
II
:::::nL..l.____..Jf I I
JI I
r:=
---III r==
.....IIIL ......._ _.......11
L.I.._ _ _
f IL.If______.....J-L
I I _ _ _..Jf.L ..L.-_ _ _ _
t
Cooverter transfer. to the lodu,ator the dat;;-;;;-be tran,milled 3t1200 bits/'
~
Stop element suppressed
by converter
10/63
460
M88AN64T-02
T87515
c) Break Signal
Breaksignal contains M to 2 M + 3 bits, all of which
maintain their initial state. M represents number
of bits per character corresponding to selected
format. Upon detection of such signal, the converter automatically generates 2 M + 3 bits all having
their initial polarity. Timing diagram below illustrates this procedure.
Break Signal generated
by DTE
i ., .
,.__________
M=B
B <10 <19
::Jl~~_-_-_-_-_-_-~~LI
::::n~
__-,
Min 12
~I
I.~--------------------~~~~----~
19
.1
Break Signal generated by Converter
M88AN64T-03
1.6.2 - SYNCHRONOUS TO ASYNCHRONOUS
CONVERTER
In receive mode, this converter must be capable of
recovering the data transmitted by distant OTE while
respecting the break signal generated by asynchronous to synchronous converter of the distant modem.
a) If the converter detects a missing stop element
within the demodulated signal:
- It will regenerate this missing element, and
- In order to resynchronize the demodulated signal, it will reduce the duration of stop elements
by as much as necessary but within over speed
selection limits of OSE.
This procedure is illustrated in timing diagram given below.
Demodulator provides the converter with Demodulated Data
::::n I
Stop element suppr
II
-~d
by transmitter converter
==n
I
p
II
t
II
Camp
'-$ ~
t
II
II
u::=
II
II
LC::
1
t
Stop Elements generated by Receiver Converter
M88AN64T-04
---------------------
11/63
461
TS7515
b) The converter detects the missing stop elements
at the end of break signal character, and trans-
fers this signal in its entirety to the OTE as shown
in timing diagram below.
Break Signal Received from Line
~_________' ________~r--l~~I____~1 I r===
Signal transmitted in its entirety to the OTE
=:Tl......._ .......II...._ _ _ _, _ _ _.......r-1_'---_-I.
I
c=
M88AN64T-05
1.6.3 - SCRAMBLER & OESCRAMBLER
Operating principles of the scrambler and the descrambler are discussed in "Chapter 5.1 and 5.2" of
CCITT V.22 recommendations.
The scrambler allows to recover, at receiver, the
clock rate associated with the received data so as
to perform a coherent demodulation and also to provide the OTE with a clock whose phase is synchronized with the received data.
Figure 2 illustrates the "scrambling fundamentals".
As shown, the scrambler includes a pseudo-random
sequence generator composed of :
_ A single-input, single-output shift-register.
_ In general, a single interconnection point.
_ An Exclusive OR gate.
If the interconnection point is appropriately located
and if N represents the number of shift-register
stages, then the generated bit sequence representing a pseudo-random character will have a periodof2N-1.
Note that the number of identical bits of this sequence will not exceed N.
The shift-register is driven by the transmit clock. The
pseudo-random sequence so generated is applied
to one of the inputs of the "Exclusive OR" whose
other input is loaded with the data to be scrambled.
Thus, data bits are inverted whenever they coincide
with a high level (1) of the sequence.
12/63
462
Inverse procedure is performed in receive mode arid
requires the pseudo-random generator to operate
in synchronization with the pseudo-random sequence generator used at transmission end. In order to avoid this constraint, it is generally preferable
to emply a self-synchronizing scrambler similar to
the one depicted in Figure 3.
Operation is identical to that given in Figure 2. However, in this case the scrambled data is applied to
the transmit register and similarly, after transmission, the scrambled data is applied to the input of
the receive register. It is clear that at the end of first
N-bit transmission, the receive register will be in the
same state as the transmit register - taking into
consideration the propagation delay time inherent
to the transmission line.
. In both types of the scrambler, data recovery procedure is accomplished thanks to reversible property
of the Exclusive Or gate.
If
a EB b =c [where EB represents modul0-2 sum]
then a =b EB c
The self-synchronizing scrambler has the disadvantage of multiplying the number of errors by a factor
of 3. In fact, when an isolated error appears at the
input of the receive register, it causes a first error in
the recovered bit sequence - then a second error
occurs as it reaches the level of interconnection
point - and finally a third error is generated at the
last stage of the register.
TS7515
Figure 2 : Scrambler Block Diagram.
T
R
A
Shift Register
Initial Data
N
a
S
M
I
T
Scrambled Data
I
I
I
R
E
C
Shift Register
E
I
V
E
c
Recovered Data
M88AN64T-06
13/63
463
TS7515
Figure 3 : Self-synchronizing Scrambler.
T
R
A
N
b
S
Data to be
Scrambled
M
I
Shilt Register
a
T
Scrambled Data
Shilt Register
R
E
C
E
I
V
E
c
b
Recovered Data
M88AN64T·07
14/63
L.'1
SGS·ntOMSON
'1,
iKjJnC~IiI@II!]a
464
TS7515
by CCITT, the modulated signal comprises sum of
two carriers alternately modulated at a master rate
of 600 bauds and overmodulated by a partial sinewave, as shown in timing diagram below.
1.6.4 - CARRIER & TONE GENERATORS
The DPSK signal generation is achieved using a
ROM containing 32 x 8-bit states and an 8-bit C-2C
converter circuit.
1.6.5 - TRANSMITTED SPECTRUM
In order to respect the limits of ampitude and distortion due to propagation delay time recommended
Tran5lllitted Signal = Sum of two DPSK signals modulated at 300 bauds, owrmodulated
by a partial sinew ave, and 5hifted by :
,
I
~t=--s
600
I
I
I
Cos
Ix
+
3
"'::--i
2"
I
I
+~f\
-v
Channel'
I
I
I
o"
I
Cos
3
+ ~I
Ix
2
I
I
1\ C\ I
V\J.\J
UI
I
~I~
:1
I
I
--~~----rl----~--------~------_r---------------~----~I------
I
I
+A
Cos
I
I
x
I
Cos
Ix
I
I
+ .. 1
I
I
1-t---I-{\-+--+(1-T1 -f-f\----'---f.f\---I-___
O----t--f(H-iI ..-V IV V
I
I1
~~
o .c::1~
i·
I
V\T\V
Channel 2 ........
4--
-A
I
I
I
I
I
I
I_
I
I
II
I
I.
I
I
I
I
I
I
Gradual change from
Channel 2 to Channel'
.1_
3" /2 phase shift
t=
1
3" 12 phase shift
I
_,_ s
600
I
I
,
t=
I
I
I
I
I
I
Gradual change from
Channel' to Channel 2
I
I
I
I
·1
300
s
..
I
M88AN64T-08
15/63
465
TS7515
1.6.6 - FILTERS
1.6.6.1 - Transmit Filter
In combination with the modulation effects, the
transmit filter allows to meet performance characteristics recommended by CCITT. A compromise
equalizer compensates partially for line irregularities.
This is a 12th order switched-capacitor filter.
1.6.6.2 - Receive Filter
The receive filter allows to recover a maximum
amount of energy in receive channel while it offers
an efficient rejection of the transmission channel
and the guard tones. A fixed compromise equalizer
compensates partially for irregularities due to line
characteristics.
ECOMP
a) Lower Channel
This is 20th order filter implemented by cascading
a 14th order amplitude clamping module and a
6th order all-pass module providing propagation
delay time correction.
b) Upper Channel
This is 14th order filter implemented by cascading
a 10th order amplitude clamping unit and a 4th
order all-pass unit providing propagation delay
time correction.
1.6.7 - LEVEL DETECTOR
RDI input connected to a signal detection circuit that
discriminates between two positive levels N1 and
N2. Output of the detector is delayed so as to provide hysteresis effects between N1 and N2. See timing diagram given next.
Nt
I
I
I
I
I
I
I
~
DPSK 105 ms:O;1: 1 :0;205 ms
FSK 105 ms :0; 1: 1 :0; 205 ms
16/63
466
M88TS7515·05
DPSK 10 ms :0; 1: 2 :0; 24 ms
FSK 25 ms :0; 1: 2 :0; 75 ms
TS7515
1.6.8 - SYNCHRONOUS DEMODULATOR
The signal received on line is first filtered and clamped at appropriate level and then applied to this syn-
chronous modulator which will deliver demodulated
data synchronized on receive clock.
1.6.8.1 - Demodulator Block Diagram
Received Signal
IFiltered & Clamped)
Post-DemoduJation
Test
DECISION
Filters
«EYES. Pattern
RxCLK
M88AN64 T -09
1.6.9 - SUMMARY TABLES OF OPERATING MODES
1.6.9.1 - Synthesis of different Modes for Receive Section
Receive
C/B
BRS
TL
A/O
- 1 or 0
X
- 1
0
DPSK Originate Loop 3
1
DPSK Answer Loop 3
0
0
DPSK Answer Loop 2
1
DPSK Originate Loop 2
0
DPSK Answer
1
DPSK Originate
1
1
0
-1
0
1
1
0
DPSK Originate Loop 3
1
DPSK Answer Loop 3
0
DPSK Answer Loop 2
1
DPSK Originate Loop 2
0
DPSK Answer
1
DPSK Originate
- 1
0
FSK Originate Loop 3
1
FSK Answer Loop 3
0
0
FSK Answer Loop 2
1
FSK Originate Loop 2
0
FSK Answer
1
FSK Originate
1
Answer
Receive in Lower Channel
Originate: Receive in Upper Channel
Mode
V.22
BELL 212A
Including
BELL 103
Loop 3: Analog Loop
Loop 2: Digital Loop
17/63
467
TS7515
1.6.9.2 - Synthesis of different Modes for Transmit Section
ATE
CIB
0
- 1 or 0
2100 Hz
1
2225 Hz
1
BRS
- 1
Answer Tone
DPSK 1200 bps Answer
1
DPSK 1200 bps Originate
V.22 without
0
DPSK 600 bps Answer
Guard Tone
1
DPSK 600 bps Originate
0
DPSK 1200 bps Answer
1
DPSK 1200 bps Originate
1
0
DPSK 600 bps Answer
1
DPSK 600 bps Originate
0
0
DPSK 1200 bps Answer
1
DPSK 1200 bps Originate
1
0
FSK 0 - 300 bps Answer
1
FSK 0 - 300 bps Originate
1
0
1
Mode
0
0
0
Transmit
AlO
V.22 with
1800 Hz
Guard Tone
BELL 212A
Answer : Transmit in Upper Channel
Originate: Transmit in Lower Channel
1.6.9.3 - Mode Selection in Phase Modulation Transmission
-
AIS
CLS
OSE
-1
0
0
Transmission
Mode
Character
Length
8
0
11
0
1
0
0
Asynchronous
9
10
0
0
0
+ 1 %, - 2.5 %
+ 2.3 %, - 2.5 %
1
1
+ 1 %, - 2.5 %
+ 2.3 %, - 2.5 %
1
1
+ 1 %, - 2.5 %
+ 2.3 %, - 2.5 %
1
1
Overspeed
+ 1 %, - 2.5 %
+ 2.3 %, - 2.5 %
Synchronous
1.6.9.4 - Test pin
ATE
CIB
BRS
0
- 1 or 0
0
1
18/63
468
Test
DDO
1
V.22 DPSK 1200 bps
DDO
0
BELL 212A DPSK 1200 bps
DDO
2100 Hz
2225 Hz
BELL 103 FSK 0 - 300 bps
HLO
-1
0
0
1
V.22 with Guard Tone DPSK 600 bps
DDO
0
BELL 212A DPSK 1200 bps
DDO
1
BELL 103 FSK 0 - 300 bps
HLO
1
DDO
HLO
Receive
V.22 DPSK 600 bps
1
1
Transmit
: DPSK Demodulator Output
Hard Limiter Output
V.22 without Guard Tone DPSK 1200 bps
DDO
1
V.22 without Guard Tone DPSK 600 bps
DDO
0
V.22 with Guard Tone DPSK 1200 bps
DDO
TS7515
2 - DETAILED DESCRIPTION OF V.22
& BELL 212A STANDARDS
2.1 - Foreword
Due to the fact that the present application note is
primarily intended for technicians not possessing an
in-depth knowledge of this "advanced" field of telecommunications, it seemed appropriate to include
an overview of the most recent publications covering specifications of the V.22 and BELL 212A
standard requirements.
We shall also discuss line interface characteristics
and requirements which together with modulator,
demodulator, carrier detection, user interface (V.24,
RS-232C) must be appropriately employed -or else,
equipment of different manufacture will be unable to
communicate with each other.
On the other hand, if standard requirements and
rules are properly observed, then a system implemented in Japan and another in France, will be able
to communicate without any difficulty.
2.2 - V.22 Standard
Modem operating at 1200 bits/s in full duplex.
2.2.1 .2 - Variant B
1200 bits/s synchronous } Variant A
600 bits/s synchronous
+
1200 bits/s Asynchronous
600 bits/s Asynchronous
2.2.2 - ON-LINE SIGNALS
2.2.2.1 - Carrier frequency and Guard Tone.
Frequencies of the operation are respectively 1200
Hz ± 0.5 Hz for lower channel and 2400 Hz ± 1 Hz
for upper channel. A 1800 Hz ± 20 Hz Guard Tone
is transmitted continuously whenever modem transmits in upper channel. This guard tone must be disabled when modem transmits in lower channel.
An additional 550 Hz guard tone may be transmitted for national applications.
2.2.2.2 - Levels of transmitted Data Signals &
Guard Tone
The 1800 Hz guard tone must be 6 ± 1 dB below power level of data Signals transmitted in upper channel.
Normalized for operation on general switched telephone lines and leased networks.
Total power of signal transmitted on-line must meet
specifications defined by V.2 recommendations:
2.2.1 - GENERAL DESCRIPTION
Total power drawn from line by subscriber
equipment must not exceed 1 mW, whatever the operating frequency.
This Modem is intended for operation on switched
telephone networks and point-to-point leased lines.
Main characteristics are as follows:
_ Duplex operation on switched 2-wire telephone
and point-to-point leased lines.
_ Frequency division channel assignment.
_ Differential Phase Modulation for each channel
with on-line synchronous transmission at 600
bauds.
_ Scrambler availability.
_ Measurement facilities.
Since the application coverage is wide, V.22 recommendations provide for 3 possible configuration variants. As far as we are concerned, we shall limit our
discussion to two of these variants.
Note that this power must be identical in both directions (go & return).
Due to the presence of the guard tone, power level
of upper channel signals is approximately 1 dB below that of the lower channel signals.
2.2.3 - FIXED DELAY COMPROMISE EQUALIZER
This on-chip compromise equalizer is commonly
shared by both transmit and receive sections.
Note: This equalizer is mainly intended to compensate for transmission line irregularities caused by signal amplitude attenuation and
group propagation delay time d!dOl.
Characteristics of these variants are as follows:
2.2.1.1 - Variant A
2.2.4 - SPECTRUM & GROUP PROPAGATION
TIMES
1200 bits/s synchronous
600 bits/s synchronous
Signal transmitted on the line must conform to characteristics depicted in the following Figure.
19/63
469
TS7515
Figure 7: Amplitude Limits of Signal Transmitted On-line (without equalization).
0.75
o
,.-
-0.75
-2
-4
"
-5
............
./'
--.....
............. ~
./. /
......
~~
//
-9
-10
-15
/
-20
v/
1\
~
~
-25
-600
:-500 :-4501
1
1
-300
125
-200 -125
200
300
400 450:
I
-550 -475 -400
SOO
l 600
1
1
475
550
CARRIER FREQUENCY (Hz)
M88AN64T -10
The group propagation time of transmitter output signals must fall within ± 100 iJS limits in frequency
range of 800 Hz to 1600 Hz (lower channel) and
2000 Hz to 2800 Hz (upper channel).
The on-line transmission bit rate must be either
1200 bits/s or 600 bits/s ± 0.01 % with a modulation
rate of 600 bauds ± 0.01 %.
2.2.5.2 - Data bits coding
2.2.5 - MODULATION
Data stream to be transmitted is split into groups of
consecutive 2 bits called dibits. Each dibit is encoded by considering the relative phase change with
respect to previous phase element of the signal (see
table below).
2.2.5.1 - Bit Rate
As mentioned earlier, we shall only discuss variants
A and B of V.22.
Dibit Value
Bit Value
(at 1200 bits/s)
(at 600 bits/s)
00
01
11
10
a
1
Phase Change
90°
0°
+ 270°
+ 180°
+
Note: The phase change is the actual phase shift on-line within signal transition area situated between the
middle of a signal element and the mid point of the following element.
Upon receipt, dibits are decoded and recovered bits arranged in correct order. The left number of the
dibit appears first within the data streams as they enter modem's demodulator section located following the scam bier.
20/63
470
TS7515
The foregoing applies to bit rate of 1200 bits/so In
the case of 600 bits/s, each bit is coded by a phase
change with respect to the preceding phase of the
signal element.
2.2.6 - FREQUENCY TOLERANCE OF THE RECEIVED SIGNAL
The transmitter carrier frequency tolerance is at
maximum ± 1 Hz and allowing a drift of ± 6 Hz due
to transmission line characteristics, the receiver
must therefore be capable of accepting errors at
± 7 Hz tolerance on received frequencies.
2.2.7 - CONNECTOR PINS
The following table gives a list of indispensable and
optional connector pins used for DTE/DCE Interface.
2.2.7.1 - Summary of Connector Pins
Pin Number
102
102 a
102 b
103
104
105
106
107
108/1
108/2
109
111
113
114
115
125
140
141
142
Notes: 1.
2.
3.
4.
Function
Signal Ground or Common Return Line
DTE Common Return Line
DCE Common Return Line
Transmitted Data
Received Data
Request to Send
Clear to Send
Data Set Ready
Connect Data Set to Line
Data Terminal Ready
Received Line Signal (carrier detector)
Bit Rate Selection (DTE originated)
Transmit Signal Element Timing (DTE source)
Transmit Signal Element Timing (DCE source)
Receive Signal Element Timing (DCE source)
Ring/Calling Indicator
Test/Diagnostic Loop
Local Loop
Test Indicator
Note
1
2
3
3
4
This pin is optional.
Signals on this pin are ignored when modem not operating in synchronous mode.
This pin is locked on OFF state when modem does not operate in synchronous mode.
Used only when modem is connected to public switched telephone lines.
2.2.7.2 - Thresholds of Pin 109
Thresholds of pin 109 are specified at modem input
terminals, ignoring effects produced by compromise
equalizer.
This pin must not react to 1800 Hz Guard Tone and
2100 Hz Answer Tone transmitted during call establishment sequence.
Upper Channel threshold
Higher than - 43 dBm ~ Pin 109 ON
Lower than - 48 dBm ~ Pin 109 OFF
Lower Channel threshold
Higher than - 43 dBm
~
Pin 109 ON
Lower than - 48 dBm ~ Pin 109 OFF
The intermediate state of pin 109 between ON and
OFF levels is not specified. However, the signal le-
vel detector must exibit a hysteresis higher than 2
dB.
2.2.7.3 - Pin 111 & Bit Rate Control
The bit rate is selected by :
_ Appropriate strap or switch settings on Modem
Board.
.
_ Using connector pin 111.
_ Or, combination of both.
If used, pin 111 will in ON state enable 1200 bits/s
operation, and 600 bits/s in Off condition.
2.2.7.4 - Electrical Characteristics of Connector
Pins
It is advised to respect electrical characteristics specified in V.28 recomendations. Applicable connector and pin spacing requirements are defined in ISO
2110 publication.
21/63
471
TS7515
2.2.7.5 - Error Condtions of Connector Pins
Some applications require detection of failure conditions on connector pins, a summary of which is given next.
1) Lack of connection between DTE and DCE
2) Open-circuited interconnecting cable
3) Short-circuited interconnecting cable
Type 1 error: Data pins are all at logic level "1".
Control and timing pins are in OFF state.
The DTE must consider an error on pin 107 as being
in OFF state.
Similarly, failure conditions on pins 105 and 108, are
considered as OFF states by DCE.,
2.2.8 - DTE/DCE INTERFACE MODES OF
OPERATION
2.2.8.1 - Variant A
The Modem may be configured for the following
modes of operation:
_ 1200 bits/s ± 0.01 % synchronous
_ 600 bits/s ± 0.01 % synchronous
In these modes, the modem monitors pin 113 or pin
114 and accepts through pin 103 the synchronous
data originated from DTE. These data are then
scrambled and forwarded to the modulator for coding.
In addition to normal transmit timing element, the
modem must provide the possibility of deriving the
transmit signal element timing from receive signal
element timing.
2.2.8.2 - Variant B
_ 1200bits/s±0.01 % synchronous
_ 1200 bits/s asynchronous, 8-, 9-, 10-, 11-bit characters
_ 600 bits/s ± 0.01 % synchronous
_ 600 bits/s asynchmous, 8-, 9-, 10-, 11-bit characters
Synchronous modes are identical to those outlined
for variant A.
2.2.9 - TRANSMITTER
In asynchronous modes, modem accepts asynchronous data stream issued by DTE at a nominal rate
of 1200 or 600 bps.
Asynchronous data are converted into suitable format for synchronous transmission at 1200 or
600 bps ± 0.01 %, then scrambled and sent to the
modulator for encoding.
The converter must be configured to accept the following character formats:
22/63
472
a) One start bit, followed by seven data bits and one
stop bit (9-bit character).
b) One start bit, followed by eight data bits and one
stop bit (1 O-bit character).
c) One start bit, followed by nine data bits and one
stop bit (11-bit character).
d) One start bit, followed by six data bits and one
stop bit (8-bit character).
2.2.10 - FUNDAMENTAL BIT RATE
The intercharacter binary bit rate (including start and
information bits) generated by DTE or provided
through pin 103, must be 1200 or 600 bits/s with tolerance falling within + 1 % to - 25 % limits.
When the character bit rate falls within the limits of
theoretical values (1200 or 600 bits/s) and the maximum value (+ 1 %), the asynchronous to synchronous converter implemented in the transmitter
section must suppress, whenever necessary, the
stop bits of the input characters.
Within 8 consecutive characters, at most one stop
element may be eliminated.
On the other hand, if the character bit rate falls within the limits of theoretical values (1200 or 600
bits/s) and the minimum value (- 2.5 %), then the
asynchronous to synchronous converter will provide
more bits per second than DTE is generating. As a
consequence, the converter will insert additional
stop elements within the transmitted characters.
Some Data Terminal Equipment and Multiplexors
exceed the + 1 % bit rate tolerance. The modem
must therefore be capable of accepting data provided by DTE at 1200 or 600 bits/s, tolerance between
+ 2.3 % and - 2.5 % and consequently suppress at
most one stop element per 4 consecutive characters.
2.2.11 - BREAK SIGNAL
If the converter detects M to 2 M + 3 bits all of which
have the polarity of start bit, where M is the number
of bits per character in selected format, it will transmit 2 M + 3 bits all with start polarity. However, if
more than 2 M + 3 bits of start polarity are detected,
the converter will transmit them all with start polarity.
2.2.12 - RECEIVER
Intercharacter bit rate delivered to DTE through pin
104 must have a value between 1200 and
1221 bits/so
For all characters, start and data elements should
be of identical nominal length. The width of the stop
TS7515
element should not be reduced by more than 12.5 %
for fundamental bit rates so as to allow detection of
any excessive bit rate caused by transmission terminal equipment.
Received 2 M + 3 bits (or more) with start polarity
sent by originating modem are supplied to pin 104.
The modem detects the transition from stop polarity to start polarity in order to regenerate character
synchronization.
2.2.13 - SCRAMBLER & OESCRAMBLER
2.2.13.1 - Scrambler
The modem includes a self-synchronizing scrambier that implements 1 + X· 14 + X· 17 polynomial generator. This scrambler is integrated inside the
transmitter section of the modem.
The data message sequence applied to the scrambler are divided by the polynomial generator. The
resultant quotient coefficients, arranged in decreasing order, represent the data sequence to appear
at scrambler output.
The scrambler output data sequence is given by the
following expression.
Os
= Oi (B OS . x- 14 (B OS . x- 17
Where:
Os : Data sequence at Scrambler Output
Oi : Data sequence applied to Scrambler Input
(B : Modul0-2 Sum
"." : Binary multiplication
The following Figure illustrates Scrambler functional
configuration.
D
_14
s··
D
Data
input
_17
s··
M88AN64T-11
Note1: In order to avoid scrambler blocking to cause occasional and unpredicted occurrence of type-2100pback, 64 consecutive binary "1"s must be first detected on scrambler output (Os) and only then, the
next signal applied to scrambler input (Oi) will be inverted. This function must be disabled during
both call establishment and type-2 loop back sequences.
2.2.13.2 - Descrambler
Modem's receiver integrates a self-synchronizing
descrambler implementing the 1 + x- 1 + x- 17 polynomial. The data sequence obtained after demodulation must be multiplied by 1 + X- 14 + x- 17 polynomial
generator so as to obtain the descrambled mes-
sage. Coefficients of the regenerated message, arranged in decreasing order, represent the data sequence on Do output. This sequence is defined by
the following expression:
Do
= Os (1
(B X- 14 (B
x- 17)
23/63
473
TS7515
Figure below gives Descrambler functional diagram.
O
s·x
-14
Data
output
M88AN64T-12
24/63
474
TS7515
2.2.14 - SEQUENCE OF OPERATION (Permanent
Carrier)
2.2.14.1 - Channel & Operating mode Selection
In public switched telephone lines, the called modem receives data in lower channel and transmits
in upper channel.
2.2.14.2 - Operation on switched telephone lines
Timing diagram below illustrates how initial synchronization is established between originating and answering
modem
communicating
through
international switched telephone networks.
Silent
Signal
transmitted
on~ine
Interval
Data
> 400"m;;o'+_-i_ _
155
50 m5
MODEM IN
Connection to line
Detection
Interval of
210:t- 40 ms
non scrambled
Detection
Interval of
binary 1
76S±10ms
Walt
5Crambled
ORIGINATE MODE
binary~ ~
104
Locked onto
binary'
IB,"",
«1.1
\0"
I
Data
II I
Non $Crambled
binary 1 and
1800 Hz
Signal
transmitted
Ofl"line
Data at 1800 Hl
Wail
MODEM
IN
ANSWER
MODE
Connection to line
Detection
Interval of
scrambled
binary 0 or 1
Note :
Binary 0 is
originated from
variant C
~
104 locked onto binary
I
,1
Binilry 1
r-o::-
81 Anumes that connettor pin 105 has been switched to ON state.
M88AN64T·13
25/63
475
TS7515
The following timing diagram depicts the call establishment sequence without auto-answer capability, as defined in V.25 recommendations.
, I2iI
d
~&-rn-mb-,oo~~----~---------T---D.-,a-
Signal
Transmitted
on-line
Connection to line
B;na,v 1
270 ±4Q ms
Detection
Interval of
non-scrambled
MODEM IN
ORIGINATE
MODE
yb;na 402 msl
Carrier
lONG SPACE
TRANSMIT
BY CARRIER FAil
DISCONNECT
J
~
L
t - - - - ' - - - - - - - - il
M88AN64T-19
33/63
483
TS7515
EIA CONNECTOR PIN CONNECTIONS
N°
Name
Direction
1
2
3
4
5
6
7
8
9
10
11
12
13
14
-
-
BA
to Data Set
BB
from Data Set
-
-
CB
from Data Set
CC
from Data Set
AB
-
Received Data
NC
Clear to Send
Data Set Ready
Signal Ground
CF
from Data Set
Received Line Signal Detector
from Data Set
Testing Voltage
-p
from Data Set
Testing Voltage
-
-
CI"
from Data Set
-
-
NC
-
-
NC
15
DB"
from Data Set
16
-
-
NC
Speed Mode Indication
Transmit Signal Element Timing
(data communication equipment source)
NC
Received Signal Element Timing
(data communication equipment source)
17
DD"
from Data Set
18
19
20
21
22
23
CN"
to Data Set
-
-
CD
to Data Set
RL**
to Data Set
CE
from Data Set
CH**
to Data Set
Speed Select - Originate
DA
to Data Set
Transmit Signal Element Timing-data
(terminal equipment source)
CN"
to Data Set
Make Busy/Analog Loop
25
Make Busy/Analog Loop
NC
Data Terminal Ready
Remote Digital Loop
Ring Indicator
or
TM"
from Data Set
" Protective Ground is provided on a screw terminal.
** May be disconnected from interface via options.
484
Transmitted Data
+ P
24
34/63
Function
No Connection (NC)*
Test Mode
TS7515
3 - TS7515 APPLICATIONS
Since the selected mode of 6805 CT operation
uses the available C and D ports for Data and Address Bus, it was a consequence necessary to
add 5 bi-directional ports within the area reserved for this function. This explains the presence
of 74LS244 and 74LS377 devices.
_ Interface to the telephone lines is implemented
by "IRC 2000" of LTT whose characteristics will
be detailed later.
3.1 - Introduction
This chapter describes a TS7515 based application
implemented in SGS-THOMSON Microelectronics
application laboratories.
This is stand-alone application for both V.22 and
BELL 212A standard requirements.
Following modes of operation are available:
_ Manual call mode.
_ Manual answer mode.
_ Automatic answer mode.
Additional details concerning the application diagram
In order to develop a pratical configuration in conjuction with the sub-section called line interface (will be
explained in detail later), the interface used was deliberately selected among those currently approuved by telecommunications authorities.
3.2 - Application Diagram
The complete application diagram is given at the
end of this chapter.
_ Modulation - Demodulation, Transmission-Reception Filtering. Asynchronous-Synchronous
Conversion, Scrambling-Descrambling Carrier
Detection functions are accomplished' by TS
7515.
- A 6805 CT single-chip microcomputer, configured in type 2 open mode, executes the modem
management functions.
The program memory is a 2732-type PROM
containing the object code.
_ MUX 1 multiplexor: allows transmission of messages issued by the microcomputer during
connection establishment or loop back answer
sequences.
(description of software, chapter 4, explains the
occurrence of these events).
_ OR Gate connected to Pin 104: Some particular sequences defined by V.22 and BELL 212A
recommendations require the connector pin 104
to go to logic "1" in response to the state of V.24
connector pin 109.
_ MUX 2, MUX 3, MUX 4 Multiplexors: Some of
TS7515 terminals have been designed to accept
three-state input signals to perform 3 different
functions.
Suitable translation of these three-state signals
is obtained by applying the two logic outputs to
an analog multiplexor. Various solutions, two of
which are outlined next, are possible.
1 - Using a "4000" series CMOS multiplexor (e.g. MC 14052 B) as shown below (example of type 2 and
type 3 loops).
+5V
ov
To
TL Terminal
-5V
+5V
01
02
Port Address : S 20
M88AN64T-20
This solution has the disadvantage of requiring one MC 14052 B circuit or equivalent for each 3-state input.
35/63
"485
TS7515
2 - Using a transistor array as shown below.
+5V
+5V
A
~
______________
~~c
A
+5V
OV
+5V
OV
B
C
+5V
+5V
OV
OV
-5V
OV
+5V
+5V
-5V
M88AN64T·21
This alternative offers the advantage of using currently available resistor and transistor arrays thereby achieving component count reduction.
_ Purpose of adjustable resistors for on-line signal transmission/reception
Telecommunications authorities have established maximum admissible on-line power level
transmitted by any device. In order to comply with
these strict limits, a combination of fixed and adjustable resistors is used to achieve signal level
adjustment.
Resistor bridge on receive channel allows adjustment of complete loop gain so as to enable the
carrier detection circuit (internal to TS7515) to
meet the requirements of V.22 and BELL 212A
standards:
High level: - 43 dBm on-line
Low level: - 48 dBm on-line
3.3 - Modem Configuration Switches
16 programming switches are available - some of
them are used for the selection of modem's operational status (data format, channel selection, ... ) and
the others for monitoring purposes such as maintenance loop, remote loop request, ...
A summary description of these switches is given
next.
SWO : BRS (Binary Rate Selection)
Selects Data Transfer Rate as follows:
36/63
486
SWO Setting
Binary Rate
1
1200 bits/s
0
600 bits/s (CCITT)
300 bits/s - FSK BELL
SW1 : L2 (Loop 2)
Configures the modem fortype-2 maintenance loop
operation.
Type-2 loop is intended to enable the station or the
network to monitor the error-free operation of both
the line (or a section of the line) and the distant modem.
SWI Setting
Loop 3
1
Deselected
0
Selected
SW3 : L3 (Loop 3)
Configures the modem for type-3 maintenance loop
operation.
This is a local analog loop used to test modem's correct operation. It should be as close to the line as
possible.
In the case of our application, this loop is implemented by disconnecting the modem from line which will
cause an imbalance of 4-wire/2-wire converter. (further details are given later in this chapter).
SW1 Setting
Loop 3
1
Deselected
0
Selected
TS7515
SW3: C/B
Configures the modem for operation in accordance
with CCITT V.22 or BELL 212A standards.
channel (lower/upper), other channel being automatically assigned to reception.
SW7 : ATE (Answer Tone Enable)
In CCITT V.22 mode of operation, enables or disables the transmission of 1800 Hz guard tone.
This switch enables the transmission of the answer
tone.
Employed for debug mode only.
When SW3 is switched to "1" level, a 1800 ± 20 Hz
guard tone is continuously transmitted while modem
is sending in upper channel.
Allows to switch between telephone line (TPH) and
Modem (DATA) connections.
This guard tone is disabled when modem transmits
in lower channel.
SW9 : ROL (Remote Digital Loop)
SW4 : GT (Guard Tone)
SW3 Setting
1
0
Transmit Channel
Lower
Upper
Without
With
1800 Hz
1800 Hz
Without
Without
1800 Hz
1800 Hz
SW5: SEI
SW8 : 1'/0 (Telephone/Data)
Used to send loop 2 request to remote modem. This
request initiates the loopback handshake sequence.
Signals used for type-2 loopback establishment
may be transmitted only after the conclusion of
contact initiation procedure of synchronization.
When a type-2 loopback sequence is terminated
and when RDL switch returns to "0", the modem
sends a loopback suppression instruction.
Scrambler Enable/Disable. Employed for debug
mode only.
SW10 : AA (Auto Answer)
SW6 : A/O (Answer/Originate)
Enables or disables modem configuration for auto
answer capability to incoming calls.
Selection of Answer or Originate mode. This switch
affects directly the selection of the transmission
r------------~I.I~'------------'I_
RDL
1~.~N-O-I~--P~--Ck-;'~.~I••----------Lo-o-~-ac-k--------~.~
[ Type 2 L~P~Ck]
Handshake
Suppression]
[Loopback
Handshake
M88AN64T·22
SW11 : S1/A
SW12 : S2/A
Synchronous/Asynchronous Mode Selection
SW13: CLS
SW14: OSE
In asynchronous mode, selects the character length and configures the modem for
overspeed function.
Table next page gives all possible configurations.
37/63
487
TS7515
SlIA
S2/A
CLS
OSE
0
X
0
0
Synchronous
1
1
1
1
0
0
0
1
Asyn 9 bits (+ 1 %, - 2.5 %)
Asyn 9 bits (+ 2.3 %, - 2.5 %)
1
1
1
1
1
1
0
1
Asyn 10 bits (+ 1 %, -2.5 %)
Asyn 10 bits (+ 2.3 %, - 2.5 %)
1
1
0
0
0
0
0
1
Asyn 8 bits (+ 1 %, - 2.5 %)
Asyn 8 bits (+ 2.3 %, - 2.5 %)
1
1
0
0
1
1
0
1
Asyn 11 bits (+ 1 %, -2.5 %)
Asyn 11 bits (+ 2.3 %, - 2.5 %)
Mode of Operation
x : Don't care.
Remarks concerning the above table
SW15: RTS
1 - When the application boards is configured for
synchronous operation, it is strictly forbidden
to set CLS and OSE switches to any state other
than "0". Any other setting will configure the
TS7515 for factory test configurations.
In chapter 4 (Description of Software) the inclusion of this illegal configurations is illustrated.
Disables the data transmission. Employed for debug mode only.
3.4 - Terminal Interface
Terminal to Application board interconnection is implemented via a 25-pin connector (ISO 2110 standards) mounted on the Printed Circuit Board.
This interface meets both CCITT V.24N.28 and EIA
RS-232C specifications.
CCITT : Comite Consultatif International Telegraphique et Telephonique.
EIA : Electronic Industries Association.
The following table gives a list of interface connector pins.
2 - Note that the following configurations are not
available in either asynchronous or BELL 212A
modes of operation :
- CLS = 8 bits & CLS = 11 bits
- OSE = + 2.3 %, - 2.5 %
The integrated firmware will alert the user of any illegal configuration.
Pin
Number
CCITT
Circuit Number
French
Designation
American
DeSignation
2
3
4
5
6
7
8
12
15
17
20
22
24
25
103
104
105
106
107
102
109
112
114
115
108
125
113
142
EO
RD
OPE
PAE
POP
TS
OS
BA
BB
38/63
488
HEM
HRM
CPO
IA
HET
IE
CB
CC
AB
CF
CI
DB
00
CO
CE
OA
TM
Signal Direction
Terminal
Modem
->
<->
<
<->
<-
o
TS7515
3.5 - Line Interface
3.5.1 - 4-WIRE/2-WIRE CONVERSION
This is a hybrid device inserted between TS7515
and the telephone line.
In general, it performs the following functions:
_ 4-wire/2-wire conversion.
_ Line current regulation.
_ Overvoltage protection.
_ Ring detection.
_ Pulse dialing.
_ Telephone/Data switching.
_ Galvanic Isolation.
This configuration employs an operational amplifier
- whose duty is to route signals issued by the modulator towards the telephone line - while preventing, by as much as possible, the signal reinjection
into the demodulator.
Inversely, it routes the signal received via line towards the demodulator with minimal attenuation.
Figure below illustrates the arrangement of a popular 4-wire/2-wire converter.
From
Buffer _-----~~~
Output
TBlephone Lin..
R4
line
Impedance
To Bandpass Filter
M88AN64 T -23
The gain between the on-line signal and modulator's output is :
R4
A1 = R3 + R4
Where R4 is the Line Impedance theoretically considered as 600 Q resistive.
If the line is properly matched, R3 must be equal to R4 :
i.e. R3 = R4 = 600 Q
therefore: A 1 = 0.5
The gain between the modulator and the demodulator (bandpass filter) is given by the following expression:
R2 (
R2) (
R4
A2 =-Rj+ 1 +RT
R3 + R4)
To obtain a null signal reinjection: A2 = 0
.
R2
R21
l.e.0=-Rj+1 (+R1)2
after simplification: R2 = R1
The gain between the demodulator and the line:
A3 = 1 +j=g
R1
therefore : A3 = 2
39/63
489
TS7515
It is obviously clear that these calculations are purely theoretical. In practice, the line impedance has
a complex component whose value varies as a function of the frequency. However, the 4-wire/2-wire
converter is considered as acceptable if the Gain
"A2" is approximately - 10 dB.
Further discussion on this topic is beyond the scope
of the present application note. The interested reade r is advised to refer to specialized text books for
a full coverage of this subject.
3.5.2 - GALVANIC ISOLATION
This isolation is achieved by a transformer whose
rating should be high~r than 4500 volts.
3.5.3 - LINE CURRENT REGULATION
The on-chip regulation circuitry maintain the line current within two limits, which vary from country to
country according to specifications in force.
40/63
490
Line Interface
Device
Max. Current
(rnA)
Min. Current
(rnA)
IRC 2000
50
20
3.5.4 - RING DETECTION
In general, this output delivers a logic signal corresponding to ring signal envelope.
3.5.5 - PULSE DIALING
In the case of IRC 2000, this pin delivers loop disconnect pulses for dialing and modem connection.
In addition, it offers the possiblity of telephone
connection/disconnection.
TS7515
I I
M88AN64T-24
~~~~~~~::=
-------------------41/63
491
TS7515
11-
~
00
r------t"
01
0'~---+-,
7
1
:!
11'~h
sf-l!=J
I'l----F!
IW:
r
12.!.--
'---1!:I hD
'------if'
DCD
UX . 4
l'or- --
L..----1!.I' 0"
'--------1!J. AUI
'---------cJ C/o
L---f------£!J' 5<,
'---+-----t!!I' NO
r----I.!J' .,.
[]:
',t"
~-t---4-ta-
rl
.'"
XUIIIN
XtMOUT
I---[!]' A'
1---f!!lAB
AS
,~
,
"'"
.,.,
,
'--
~
~
l
M88AN64T-25
42/63
492
TS7515
4 - DESCRIPTION OF SOFTWARE
4.1 - Definition of software modules
Each individual module given in this chapter is intended for a particular function. They cover the occurence of events sequentially from the time of
modem's initial power on until the completion of online information transfer.
4.1.1 - IDLE STATE MANAGEMENT MODULE
_
_
_
_
Microcomputer configuration.
V.24 connector initialization.
Interface disconnection from line.
Read the settings of programming switches, monitor absence of error and configure the TS7515
according to switch settings.
_ Loop 3 management.
_ Wait for an event causing connection to line.
300 Originate handshake.
_ Answer handshake.
4.1.4 - CCITT TRANSMISSION MODULE
_ Telephone line monitoring
(appearance of special sequences).
_ V.24 connector management.
_ Monitoring several switch settings.
_ Monitoring DCD terminal of TS7515.
4.1.5 - BELL TRANSMISSION MODULE
Identical to preceding CCITT module. In addition, it
provides for the identification of "Long Space" for
line disconnection.
4.1.6 - RDL HANDSHAKE MODULE
Protocol used for the initiation of remote loop sequence.
4.1.2 - CCITT HANDSHAKE MODULE.
4.1.7 - LOOP 2 RECEIVE HANDSHAKE MODULE
_ V.25 sequence.
_ Answer handshake.
_ Originate handshake.
Protocol for the reception of type-2100pback request
initiated by distant modem.
4.1.3 - BELL HANDSHAKE MODULE
_ 1200 Originate handshake.
43/63
493
TS7515
IDLE STATE MANAGEMENT MODULE
V.24 Connector initialization
TSG 7515 Transmission Disable
I RC 2000 Disconnection
All microcomputer operation registers Reset
Impossible to configure Answer
Mode, jf pin 108 is nut available
Remote Loop Request is not
allowed in this module
Loop 2 is not allowed in this module
Processing of BELL
illegal
Configurations
M88AN64T-26
44/63
494
TS7515
IDLE STATE MANAGEMENT MODULE (continued)
TS 7515
Configuration as
defined by keys
YES
NO
Processing of ringing ·Strokes·
in Auto Answer Mode
• RIA is microcomputer's
Register within which, Ringing
Strokes are stored
TSG 7515 answer mode
configuration
Connection to Line
M88AN64T-27
45/63
495
TS7515
CCITT HANDSHAKE MODULE
o
YES
NO
END
M88AN64T-28
This flowchart illustrates clearly the sequence of events. In the case of manual answer, the software will
ignore the V.25 module.
46/63
496
T57515
V.25 SEQUENCE
BEGIN
2150 ms Silent Interval
Answer Tone transmission for 3300 ms
Stop answer tone Transmission
Absence of carrier transmission for 75 ms
Connector Signal "Data Set Ready"
at active level
M88AN64 T-29
Comment: Writing this sequence meets no difficulty.
Only, CCITT recommendations must be carefully observed.
47/63
497
TS7515
ANSWER HANDSHAKE SEQUENCE
Transmission of non scrambled "I" s
Detection of
"l"son RxD
for
270ms
Detection of scrambled is issued by the distant
Modem for a period of at least 270 ms
Scramber Enabled
Delay
Connector pins cond~ioned
M88AN64T-30
Comments: Detection of scrambled "1" on RxD terminal for an interval of 270 ms is performed as follows:
The sequence begins within a loop searching to detect a logic "1" on RxD terminal while simultaneously, a 15-second "time out" is initiated. If within the loop a logic "0" is detected on RxD
pin, 270 ms count is reset but the "time out" continues. The sofware sequence will return to the
starting point (i.e. idle state management), if at the end of 15-second interval a sequence of
continuous "1 "s for a 270 ms duration has not been found.
48/63
TS7515
ORIGINATE HANDSHAKE
1070N
Detection of
"1" s on TEST
Terminal for
155 ms
This interval corresponds to the period during which
the distant Modem transm~s non scrambled "1" s
Delay
Transmission of scrambled "1" s
Detection of
"1" on RxD
for
270ms
Detection of scrambled "1" s issued by distant Modem
Recopy
109
Detection of scrambled "1" s issued by distant Modem
Watt
765 ms
Delay
Connector pin 106 conditioned
M88AN64T-31
49/63
499
TS7515
BELL HANDSHAKE MODULE
A
a
M88AN64T-32
50/63
500
T57515
1200 ORIGINATE HANDSHAKE
Change to FSK mode
Test to detect presence of 2225 Hz
Delay
Transmission of scrambled "1" s
Change to DPSK mode
Detection of scrambled "1" s sequence originaled
by distant modem
Connector configuration
Delay
Connector configuration
M88AN64T-33
51/63
501
TS7515
Important: Sequence of events in BELL Answer Mode differs slightly from equivalent CCITI sequence as
follows:
There is no transistion between the transmission of Answer Tone and Scrambled "1"s Sequence.
In the case of TS7515 and upon the appearance of scrambled "1 "s sequence, this may result
in "Carrier DPLL" locking on an incorrect frequency.
An efficient solution to overcome this problem would be to program the TS7515, for a short interval, in loop 3 configuration.
The following flowchart illustrates this recommended solution.
EXIT
YES
YES
NEXT
52/63
502
M88AN64T·34
TS7515
300 ORIGINATE HANDSHAKE
(
BEGIN
I
1070N
BRS=l
Change to FSK mode
I
Test [)CD
RecopyDCD
I
Detection of
"1"on RxD
for
50ms
Detection of 2225 Hz
I
Wait
456ms
Delay
I
-RTS=O
TxOUT= 1
Transmission of 1270 Hz
I
Wa~
309ms
Delay
I
10S0N
Connector configuration
I
END
M88AN64T-35
53/63
503
T57515
ANSWER HANDSHAKE
2 secondes Silent Interval
Answer Tone Transmission
Change to FSK mode
Check for the presence of carrier
Test the speed of the calling station
Connection to FSK or DPSK
Answer Module
M88AN64T-36
54/63
504
TS7515
CCITT TRANSMISSION MODULE
Recopy 105 to
106&to
RTS terminal
ofTSG 7515
RETURN
"1"
yes
Counter
Reset
Loop 2
Receive
Handshake
NO
M88AN64T-37
The duty of this module is to monitor either the user
connector to detect a line disconnect sequence, or
to monitor the telephone line since programming
switch settings may cause occurence of special online sequences.
55/63
505
TS7515
BELL TRANSMISSION MODULE
YES
RETURN
M88AN64T-38
56/63
506
TS7515
RDL HANDSHAKE MODULE
106 OFF
109 OFF
1420N
Transmission of
non scrambled
"1" s
Detection of
anemate 1 s &
son RxD
for 270 ms
o
Configuration of the user connector
Transmission of RDL Request Sequence
Detection of answer to this Request
End of RDL Request Signal
and transmission of scrambled "1" s
Detection of signal "echoed" by distant
Modem on RxD terminal
Configuration of the user connector
RDLend
Monitor
Mon~opring
of RDL key
Transmission of loopback suppression sequence
M88AN64T-39
57/63
507
TS7515
LOOP 2 RECEIVE HANDSHAKE MODULE
Transmission of
alternate 1 s&
Os at 1200 bps
or 600 bps
Answer to Loopback Request
End of nonscrambled 1 s
detection
Dectection of trigger signal loss
Loop 2
Loop 2 programming of TS 7515
DCD
Monitor
A waiting Loop 2 end
Relurn 10
Main
Program
M88AN64T-40
58/63
508
TS7515
APPENDIX A - TS7515 HANDLING
PRECAUTIONS
A.1 - Power supplies decoupling and
layout considerations
Power supplies to digital systems may contain high
amplitude spikes and other noise. To optimize per·
formances of the TS7515, operating in close proxi·
mity to digital systems, supply and ground noise
should be minimized. This involves attention to po·
wer supply design and circuit board layout.
The power supplies should be bypassed with tantalum or electrolytic type capacitors to obtain noisefree operation. These capacitors should be located
close to the TS7515. The electrolytic type capacitors should be bypassed with ceramic capacitors for
improved high frequency performance.
Power supply connections should be short and direct. Ground loops should be avoided.
Coupling between analog inputs and digital lines
should be minimized by careful layout. The RDI input (pin 13) is extremely sensitive to noise. The
connection between this point and RFO (pin 4) throu
a ceramic type capacitor should be as short as possible and coupling between this connection and digital signals should be minimized by careful layout.
directly on this DPLL which needs to be reset prior
to the reception of a DPSK carrier.
TS7515 offers three possibilities of resetting this
DPLL:
_ A trailing edge on DCD terminal.
_ Switching from FSK mode to DPSK mode.
_ Changing the receive channel.
These three possibilities of resetting the DPLL
should be integrated within the microcontroller so as
to provide for various set-up and handshake procedures.
Timing diagrams given in chapter 2 illustrate examples of V.22N.25 and BELL 212A received signals
in originate mode.
A.3 - Frequency Precision of Crystal
Oscillator
In orderto meet the frequency precision of the transmission baud rate required by V.22 and BELL 212A
specifications, it is recommended to use a crystal
oscillator whose series resonance frequency precision is better than 0.01 % with respect to the theoretical frequency of 4.9152 MHz.
Such precision would be feasible by optimizing the
capacitance values spread around the quartz oscillator.
A.2 - Carrier Recovery Loop
This carrier recovery loop utilizes a digital phaselocked loop. Performances of the TS7515 depend
59/63
509
TS7515
APPENDIX B - GLOSSARY OF TERMS
Acoustic Coupler: A device that permits the use
of a telephone handset as a connection to dial-up
telephone lines (rather than a direct connection
using DAA interface) for data transmission by
means of sound transducers: Usually implemented
for call origination, and is frequently used with portable terminals.
Analog Loopback : A diagnostic mode whereby
the transmitted analog output is internally connected to the analog received signal input in a single
band (determined by NO pin) so that the device's
entire signal path is under test.
Answer Tone: A tone returned by the answering
modem to the originating modem and the network.
ASCII: American Standard Code for Information Interchange. This is a seven-bit-plus-parity code established by the American National Standards
Institute (Formerly American Standards Association) to achieve compatibility between data services.
Also called USASCII.
Attenuation: The difference between transmitted
and received power due to transmission loss
through equipment, lines or other communications
devices.
Asynchronous Transmission: A data transmission scheme that handles data on a character-bycharacter basis (without synchronization by a
clocking signal). Time intervals between transmitted
characters may be of unequal length. The character code includes a "start" bit to identify the beginning of a data character, a "stop" bit (or bits) to
identify the end of the data character and a "parity"
bit to check for errors in transmission. Also called
"Start-Stop" transmission.
Auto-Answer : A circuit in a modem system that
can automatically make a connection on the switched telephone system when its number is dialed.
Automatic Dialer: A device which will automatically dial telephone numbers on the switched telephone network. An automatic dialer can be easily
incorporated into a TS7515 - based modem system.
Bandpass Filter: A filter circuit that passes a single band of frequencies and filters out, or excludes,
all others.
Bandwidth: The range of frequencies assigned to
a channel or system; the difference expressed in
Hertz (Hz) between the highest and lowest frequencies of a band.
Baud: A unit of signalling speed equal to the number of modulations or signal events per second. In
FSK synchronous transmission, the unit of signal60/63
510
ling speed corresponding to one unit interval per second ; that is, if the duration of the unit interval is
20 milliseconds, the signalling speed is 50 baud.
Baud is the same as "bits per second" only if each
signal event represents exactly one bit, as in the frequency-shift keyed TS7515 modem.
As used in the TS7515 four-phase PSK transmission, every two bits of digital data are encoded into
dibits (1 dibit = two bits) for translation or modulation into phase shift information. In PSK the baud
rate is one-half the bit rate.
Bit Error Rate (BER) : A measurement of the average number of bits transmitted before an error occurs. Usually expressed as the reciprocal of the
average.
Bit Rate: For modems using voicegrade telephone
lines, the bit rate equals the data rate. The baud rate
is the actual number of times per second that the
transmited carrier is modulated or changes state.
Each modulation may represent multiple bits.
Carrier: An analog signal fixed in amplitude and
frequency that can be combined in a modulation
process with a second information-bearing signal to
produce a signal for transmission.
CCITT (Comite Consultatif International de Telegraphie et Telephonie) : An international committee established by the United Nations to recommend
international telecommunications standards of
transmission within the International Telecommunications Union (ITU).
Channel: A communications path providing signal
transfer in a single direction at a time.
Circuit Grade: The grades of circuits are broadband, voice, sub-voice and telegraph. Circuits are
graded on the basic line speed expressed in characters per second, bits per second, or words per
second.
Coherent Detection: A method of phase-shift detection, used in the TS7515 PSK modem, in which
the received modulated signal is compared with a
purified and locallygenerated reference frequency,
instead of using the instantaneous value of the received carrier frequency (which is often distorted).
Common Carrier: A company which dedicates its
facilities to a public offering universal communications services and which is subject to public utility
regulations.
DAA (Data Access Arrangement) : Originally this
term was used to define a device, provided by the
telephone company, which was used to connect privately owned or customer provided equipment (data sets) to the switched telephone network.
TS7515
dB (Decibel) : The decibel is defined by the ratio of
output pignal power to input signal power as
dB = 10 Log 10 (Output Power).
Note that if the output power is less than the input
power, the logarithmic result is negative. In this case
the line is said to have a loss of that many dB.
dBm : Input and output signal powers may be related to a specific level called adBm for reference purposes. Zero dBm (log 1 = 0) equals 1 mW dissipated
in 600 Q impedance. The reference frequency used
in most circuits in 1000 Hz. Measurements relative
to reference frequency are expressed in decibels relative to 1 mW as follows:
dBm = lO'log 10 (Signal Power in mW/1 mW)
Thus, zero dBm means 1 mW and absolute power
levels may be expressed as so many dBm.
dBSPL : In acoustics, the unit commonly utilized to
measure sound pressure level or dBSPL. The zero
reference for this measurement is 0.0002 dynes per
square centimeter.
dBv : Microphone sensitivities are commonly related to a specific level called a dBv for reference purposes. Zero dBv (log 1 = 0) represents one mW
dissipated in 1000 Q impedance. The unit dBv is expressed in terms of the peak voltage of a signal reference to one volt.
dBv = 20'log 10 (Peak Voltage of Signal/1 volt)
DCE (Data Communications Equipment) : Consists
of the modem and any other equipment related to
the transmission or reception of analog signals over
the telephone lines, such as the FCC-approved Registered Protective Circuit.
Data Set:
_ A modem.
. _ A collection of similar and related data records.
DTE (Data Terminal Equipment) : The digital equipment to which a data communications path begins
or ends.
Demodulator: A component of a modem which recovers data from received analog signals and
converts them to a form suitable for the DTE.
Descrambler : A device or circuit that transposes
or decodes a demodulated signal to restore the original data prior to transmission by the remote transmitter and scrambler.
Digital Loopback : A means of routing data from
the transmit path back to the received data path by
switches, as a means of testing a modem.
Equalization: Compensation for the increase of attenuation with frequency. Its purpose is to produce
a flat frequency response.
FSK (Frequency Shift Keying) : A method of frequency modulation which varies the carrierfrequency at significant instants by smooth as well as abrupt
transitions.
Full Duplex: Simultaneous two-way independent
transmission in both directions on a communications channel. Also called Duplex.
Cross Distortion: Distortion is an undisred change
in a signal or data transmission. The primary
sources of distortion in modem communication are
in speed differences between the Data Terminal
Equipment (DTE) and the modem, and circuit variations and noise. The maximum gross (total) distortion in modem communication is 45 %, as defined
by EIA standards RS-404.
Half Duplex: A circuit designed for transmission in
either direction, but not in both directions simultaneously. A modem in half-duplex mode will be either transmitting or receiving, but not both at the
same time.
Handshaking: An exchange of predetermined signals when a connection is established between
two modems.
Host Computer: A computer attached to a network
providing primary services such as computation, data base access, special programs, or programming
languages.
Information Bit: A bit generated by the data source
which is not used fo error control.
Impulse Noise or Surge: A type of high-amplitude
short-duration interference on communications
lines caused by events such as lightning, electrical
sparking action, make/break action of switching devices, or electrostatic discharge. A registered protective network is required to protect the modem
from such voltages which occur on communications
lines.
Mark: A logic one, or the presence of current or carrier on a digital communications channel in the idle
condition. Compare with space.
Parity Check : Addition of non-information bits to
data, making the number of ones in each group either always even (for even parity) or odd (for odd
parity).
This permits single error detection in each group.
Phase Locked Loop: An electronic servo system
controlling an oscillator so that it maintains a
constant phase angle relative to a reference signal
source.
PSK (Phase-Shift Keying) : A type of phase modulation in which the modulation function shifts the
instantaneous phase of the modulated wave between predetermined discrete values.
61/63
511
TS7515
Protocol : A procedure used to control the orderly
communications between stations on a data link.
Examples of protocols are HOLC, SOLC, and Synchronous Bit-Oriented protocols.
QAM (Quadrature Amplitude Modulation) : One
form of-4-level differential Phase-Shift Keying.
Reference Clock: A clock of high stability and accuracy used to govern the frequency of a network
of mutually synchronized clocks of lesser stability.
RDL (Remote Digital Loopback) : A type of test in
which a signal is transmitted from a local modem to
a remote modem, or other device or switch, to loop
the remote received data back to the sending modem to measure or test the modem, communications line, remote modem or device, or the entire
circuit.
Scrambler: A device or circuit that encodes a data signal at the transmitting modem, to make it unitelligible for data security purposes (at a receiver not
equipped with an appropriate descrambler), and to
maintain carrier detect lock during idle or slow data
rate input.
Serial Transmission: A method of transmission in
which each bit of information is sent sequentially on
a single channel, rather than simultaneously on several channels, as in parallel transmission.
SNR (Signal-to-Noise Ratio) : The ratio of the signal power to the noise power on a communications
line, expressed in dB.
Space : A logic zero, or the absence of current or
62/63
512
carrier on a digital communications channel. Compare with Mark.
Start Element : In character synchronous (startstop) transmission, the first element in each character, which serves to prepare the receiving
equipment for the reception and registration of the
character.
Start-Stop Transmission : Asynchronous transmission in which a group of code elements are preceded by a start element (or bit) and ended with a
stop element (or bit).
Statistical Equalizer: A modem compensation circuit which provides equalization of a communications line based on the average switched telephone
line circuit distortion.
Stop Element: In character asynchronous (startstop) transmission, the last element in each character, to which is assigned a minimum duration, during
which the receiving equipment is returned to its rest
(idle) condition in preparation for receiving the next
character.
Switched Line: A communications link for which
the physical path may vary each time it is used, as
in the dial-up (switched) public telephone network.
Synchronous Transmission: A data transmission
scheme in which the data characters and bits are
transmitted at a fixed rate with the transmitter and
receiver synchronized. This eliminates the need for
start-stop elements, thus providing greater efficiency.
TS7515
APPENDIX C - BIBLIOGRAPHY
_ American Telephone and Telegraph Company
Bell System Reference Data Set 212A Interface Specifications
PUB 41214 - January 1978
_ Comite Consultatif International Telegraphique
et Telephonique
Communications de Donnees sur Ie Reseau Telephonique
_ SGS-THOMSON Microelectronics
TS7515 Data Sheet
_ Electronic Industries Association
EIA Standard : RS-232C Interface between Data Terminal Equipment and Data
Communication
Equipment
Employing Serial Binary Data Interchange
August 1969
Avis de la serie V - Geneve - Novembre 1980
63/63
513
APPLICATION NOTE
TS7513 V.23 MODEM PRINCIPLE AND APPLICATIONS
ABSTRACT
The present Application Note outlines the basic application principles of TS7513 circuit. A typical ap-
plication and its performances are also discussed.
INTRODUCTION
TS7513 circuit of SGS-THOMSON Microelectronics
offers a low cost solution with a minimum of external components to achieve MODEM applications
compatible with the applicable CCITT recommended standard for V.23 type modems. In fact, this circuit provides all modulation, demodulation, and fil-
tering functions required for FSK modulated data
transmission via either public switched telephone
networks or leased data links. Control signal are
compatible with CCITT recommended standard for
V.24 junction.
FUNDAMENTAL PRINCIPLES
One of the most important applications is to connect
a terminal via telephone network to a central computerfor data acquisition or information retrieval purposes.
Public switched telephone network is generally designed for voice transmission and as a consequence,
have a frequency band of 300 Hz to 3400 Hz.
Consequently, the data transmission must be performed via a modem circuit which will convert the binary data into analog signals falling within the voicefrequency band.
Using public switched telephone network is an economic solution since the required installation already exists on customer location. Nevertheless, telephone lines impose an important restriction which is
data transmission rate. This is directly due to the
channel bandwidth of the transmission lines. As a
result, a bidirectional simultaneous transmission is
only possible if the two transmission channels are
adequately separated and fall within the frequency
band authorized by the channel.
For a system employing the V.23 CCITT standard,
the TS7513 allows for a simultaneous data exchange, as indicated below:
• On main channel, with a 1200-baud modulation
rate. The two frequencies used are fo = 2100 Hz
and f1 = 1300 Hz.
AN346/0489
• On back channel, with a 75-baud modulation
rate. The two frequencies used are fo =450 Hz
and f1 = 390 Hz.
For the situation where TS7513 is used to link a remote terminal to a host computer, the data transfer
from the host computer to the terminal is done on
the main channel and takes place at a much higher
rate than in the opposite direction. The back channel is used by the remote tenninal to communicate
with the host computer. In general, these communications are short and consist of, for example, typed
messages entered via a keyboard.
The function of a MODEM is to allow via public switched telephone network or leased data links, a bidirectional data transfer between two distant computer-based systems.
Figure 1 illustrates an example where a computer
and a terminal are linked via two modems.
Operating principles are quite simple. The modem
receives the data to be transmitted in digital form,
converts it to analog signal (MODULATION) suitable for transmission over telephone lines. Inversely,
it receives analog signals transmitted from distant
station, converts them back to digital form (DEMODULATION) suitable for the computer .
1/17
515
APPLICATION NOTE
Figure 1 : Computer to Terminal Link Via Modems.
MODEM
COMPUTER
V24
"
MODEM
TEL::HONE
NETWORK OR
LEASED LINK
One of the most commonly employed techniques in
digital signal transmission is FSK (Frequency Shift
Keying) modulation. In this system, 2 frequencies fa
and f1 are used to represent digital levels "0" and "1"
respectively.
In transmit mode, the modem receives binary data
supplied for example by a microcomputer or by an
UART (Universal Asynchronous Receiver Transmitter). When a logic "0" is detected the modem outputs a sinewave signal of frequency fa. Likewise, for
a logic "1" the modulator outputs a sinewave signal
of frequency f1.
v 24
TERMINAL
M88AN58T -01
Binary digital data are so converted by the modem
to analog signal containing 2 different frequencies
of fa and f1 with of course, a continuity in phase (see
figure 2). The analog signal so obtained, must be
correctly filtered in order to eliminate the transmission of frequencies other than fa and f1.
Inversely, the demodulator receives via telephone
line, a FSK modulated analog signal. This signal is
first applied to a band-pass filter which removes all
frequencies outside the modem reception band.
The signal is then converted to digital form and applied to the computer system.
Figure 2 : FSK Modulation.
M88AN58T -02
With a minimum of extemal components, the
TS7513 performs all of the functions just described.
In addition to modulation and demodulation of signals, this circuit contains all necessary filtering for
2/17
516
reception and transmission, while signals compatible with CCITT V.24 recommendation are also provided.
APPLICATION NOTE
BLOCK DIAGRAM
«
+
>
oZ
CJ
°°
Z
CJ
I~a::
r-
t
>
i----y-i-,-1---- ~=-----,
ATO
DTMF
oeD
RxD
L---------------------~RAI
I
I
I
---------- ______ 1
«en
"'-0
WOLL
a:: a::
a::
>
a;
M88TS7513-02
FUNCTIONAL DESCRIPTION
CLOCK GENERATOR
TS7513 master clock can be generated either from
a quartz oscillator with a standard 3.579545 MHz
frequency connected across pins XtaliN and XtalOUT, or from an external CMOS clock connected
to pin XtaliN. The clock generator generates:
• The internal clocks required to operate the modulator, demodulator and the various filters.
• The external clocks (ClK, TxClK, RxClK) required to operate the following related circuits:
_ ClK: oscillating at the same frequency as the
crystal 3.579545 MHz, the clock is used to
control the DTMF frequency generator: the
EFG7189 circuit (see application).
_ TxClKlRxClK : used to control the UART
(Universal Asynchronous Receiver Transmitter), these two variable frequency clocks are
equal to 16 times the transmission (TxClK)
and reception (RxClK) modulation rate .
Pin
Modulation
Demodulation
Frequency
elK
x
x
3.579545 MHz
75 Bauds
1200 Bauds
X
X
19200 Hz
X
X
75 Bauds
1200 Hz
1200 Bauds
19200 Hz
Tx elK
R x elK
L'W'I
'1<
SCiS-THOMSON
1200 Hz
3/17
iIiIU©lI©rnI!.E!l'HII@OOUi:$
517
APPLICATION NOTE
REFERENCE VOLTAGE REGULATOR
The reference voltage generator generates an internal reference voltage with a 1.5 V nominal value
used to calibrate the amplitude of the signal transmitted and to define the two demodulator detection
thresholds. After amplification, the reference voltage output goes out to VREF pin (VREF =.:.. 2.4 V).
With an external potentiometer a fraction of this voltage is applied to RSA input pin in order to adjust
the bias distortion (see application).
3.4 kHz LOW PASS FILTER
This filter with the input connected to DTMF input
pin is used to modify the DTMF transmission spectrum.
• A digital/analog converter used to synthesize the
sinewave signals.
• A transmission filter with the response depending
of the modulation rate. A smoothing filter is added to this transmission filter in order to eliminate
the noise generated by the transmission filter
switching capacitors.
The modulator is controlled by three digital inputs
(RTS, MC/BC, TxD) and transmits a signal to ATO
pin.
When RTS pin is low, ATO pin sends a signal from
the modulator. When RTS pin is high, ATO pin
sends a signal from DTMF input. With no DTMF frequency generator connected, DTMF pin on TS7513
should be set to 0 V.
The filter output is connected to a multiplexer controlled by RTS logic signal. The DTMF frequency
couple is sent to a smoothing filter and transmitted
toATO pin.
MODULATOR
The modulator receives binary data from a source
such as an UART or a V.24 junction and converts
them into an analog signal using frequency modulation (FSK).
This signal is transmitted over the telephone network via an appropriate interface.
RTS
ATO
"L"
FSK Modulated Signal
"H"
DTMF Signal
The signal applied to MC/BC (Main Channel/Back
Channel) pin selects the frequency couple to be
transmitted. Each couple consists of a high frequency (fo) and a low freque...!l£Y (fl). With respect to the
couple selected on MC/BC pin and with RTS pin low,
the modulator outputs a high frequency (fo) if TxD
(Transmit Data) input is low ("0"), and a low frequency (fl) if TxD input is high ("1 ").
The modulator comprises the following:
• A variable rank divider generating the four transmission frequencies, i.e. 390 Hz, 450 Hz,
1300 Hz, 21 00 Hz.
-
MCIBC
Modulation Rate
TxD
R .35 and V .23
Recommandations (Hz)
GNDD
75 Bauds
"H"
"L"
390 ±2
450 ±2
V+
1200 Bauds
"H"
"L"
1300 ± 10
2100 ± 10
For transmission spectrum optlmlzaton, frequency sWitching IS established With phase conlinuity.
4/17
518
APPLICATION NOTE
DEMODULATOR
The band-pass filter attenuates down to the maximum the frequency bands outside the demodulator
receiver band. Figure 3 shows receive filter typical
frequency response. In addition figure 3 shows that
while the modem is receiving at a rate of 1200 bauds
the 1300 Hz and 2100 Hz frequencies and is transmitting simultaneously on the back channel with the
390 Hz and 450 Hz frequencies, then, the frequencies of 390 Hz and 450 Hz are rejected in order to
improve the performance of the demodulator.
The demodulator receives on RAI pin via a line interface a frequency modulated analog signal from
the telephone network and converts this signal into
binary data. The binary data is transmitted via RxD
pin over a V.24 junction to a computer or a terminal.
The demodulator consists of the following:
• A receive filter with 2 parts :
_ a 12 kHz rejector to eliminate taxation frequency at 1200 bauds or 75 bauds,
_ a band-pass filter with a response related to
the frequency couple received.
• A frequency-voltage converter or frequency discriminator with self correlation capable of demodulating at 75 bauds or 1200 bauds.
• A time-delayed hysteresis level detector where
the time delay is related to the frequency couple
received.
Another important characteristic associated with the
receive filter is the gain difference of 3 dB between
1300 Hz and 2100 Hz signal frequencies.
In fact, during the transmission of analog signals via
telephone network, high frequency signals are more
attenuated than the low frequency signals. The receive filter provides a fixed compromise equalizer in
order to correct this attenuation difference.
Figure 3 : Received Filter Typical Frequency Response.
(dB)
o
4
8
I
12
-20
-40
-....
-60
102
2
V"
I
4
6
8 103
Receive filter outputs a signal to RFO pin. An external shaping stage is required for the following:
• Eliminate the noise generated by the receive filter clocks.
• Eliminate the continuous component of the signal
due to the receive filter.
• Amplify this signal with a fixed gain up to 1.4 V
peak to peak and clip it symmetrically above
1.4 V.
~
~l
~
'\ II
,.....
2
4
6 8 104 (Hz)
M88AN58T-03
The detector output is time delayed and used in order to present an hysteresis effect between levels
N1 and N2levels. The typical hysteresis value is 2.9
dB. When detection conditions are met, the DCD
detection Signal switches to logic "0" : binary data is
output to RxD pin.
The application gives an example at an external
shaping stage.
RDI input drives a signal detector the DCD output
of which is at logic "0" if the level of RDI signal is higher than N1. The output of this detector is at logic
"1" if the level of RDI signal is lower than N2. This
detector has an hysteresis effect : N 1/N2.
The shaping stage drives (via RDI input pin) a signal
detector capable of discriminating two levels (N1 =
1.4 V, N2 = 1 V).
Timing detection conditions. The timing performance of the level detector (DCD) conforms to
CCITT V.23 recommendation.
5/17
519
APPLICATION NOTE
.r---t-------.. . . . . . . .,
~~------~~II-
Nl
I
4H-f'fi-------..-
:
iN2
RDI~~~,~~~~-I---4----------~~Hff~n~ffnl~nl~n'~t~ov
-~l
:
UU
V -
I
I
......
........
--.
- - - - --..-"
..-"
J
DeD
Tl
RxD
1-----1
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
U-- ___ L
M88TS7513-04
Under normal working conditions, OeD output is :
• low if RDI signal conforms to level detection
condition,
• high if RDI signal does not conform to the level
detection conditions.
signal conforms to the level detection conditions for
10 ms or less (respectively 10 for 75 bauds) .
OeD output goes from high to low when RDI signal
conforms to the level detection conditions for 10 ms
or more (respectively 10 ms for 75 bauds).
oeD output does not go from low to high when RDI
signal does not conform to the level detection conditions for 10 ms or less (respectively 20 ms for 75
bauds).
oeD output does not go from high to low when RDI
oeD output goes from low to high when RDI signal
does not conform to the level detection conditions
for 10 ms or more (respectively 20 ms for 75 bauds).
Modulation Rate
DeD Transition
Min.
Typ. (1)
Max.
Unit
1200 bds
11
12
10
10
12
12
15
15
ms
ms
75 bds
11
12
10
20
15
30
20
40
ms
ms
6/17
r== SCS.ntOMSON
.... , / IijJDil::IiiI@[iU1:lllll@I!lDil::iil
520
APPLICATION NOTE
APPLICATION
In the example of T87513 application presented below, T87513 circuit is in a system configuration. The
figure below shows an application block diagram
with its differents sections:
• Transmit amplifier with the duplexer and line interface.
• T87513 circuit with its shaping stage.
• EFG7189 circuit generator of DTMFfrequencies.
• EF6801 microcomputer used as an interface between the terminal and T87513 circuit.
• The bias distortion adjustment.
An example of T87513 circuit application is shown
on the following page with an EF6850 UART .
APPLICATION BLOCK DIAGRAM
EFG
1189
PQR T 1
A B, C D ISA
NMI
IRQ
TS
RESET
PORT
PORT 2 [
4f--_-=MC"'/B.!!C"-'-',T"'E""ST"',"'R.!.:TS'--_--,/
V'-::--::-:-::-:::-::-:-::--::--::-"",,,....--"\J T, 0
T x elK. R x eLK; R x 0
TELEPHONE
DCD
LINE
EF
BIAS
6301 V
RSAi-------i
Xt.11
DISTORTION
ADJUSTMENT
M88AN58T ·04
7/17
521
APPLICATION NOTE
APPLICATION BLOCK DIAGRAM
r--
"
A; B ; C ; 0 ; ISA
EFG 7189
V
!MFDUT
t
OSCIN
~
tDTMF
MAIN OR BACK CHANNEL·
I",
Me/Be
ATO TRANSMIT
-AMPLIFIER
TEST
U)
:oJ
'"a:
0
gj
w
0
g:
0
a:
T.D
1DDRESS..
RAI
DUPLEXER
0
RTS
-y
'"
IS 7513
:E
A
DATA
..
t
EF6850
UART
'"
TxCLK
SHAPING
Y
STAGE
RxCLK
RxD
RDI
DCD
RSA
10NTROL ..
- '"
a
RFO
0
LINE
INTERFACE
I---- TELEPHONE
~
LINE
I
BIAS
V
DISTORTION
ADJUSTMENT
M88AN58T -05
TRANSMIT AMPLIFIER AND DUPLEXER WITH LINE INTERFACE
TRANSMIT AMPLIFIER.
The TS7513 ATO pin can transmit two~s of analog signals according to the status of RTS logic input.
• If RTS is low, ATO pin sends a frequency modulated signal. The frequencies transmitted are the
following:
• fo = 2100 Hz fl = 1300 Hz (modulation rate = .
1200 bauds).
8/17
522
• fo = 450 Hz f1 = 390 Hz (modulation rate =
75 bauds).
• If RTS is high, ATO pin sends a pair of DTMF frequencies.
• The input of the transmit amplifier is connected
to ATO pin. The amplifier must present two possi?le gains depending on whether ATO pin transmits a frequency modulated signal or a pair of
DTMF frequencies.
ru
SCiS·nlOMSON
:"JI [i1jJO©OO~I<©~Iil@ll]O©®
APPLICATION NOTE
The following diagram shows an example of an amplifier with variable gain controlled by RTS signal.
Rb
lod!
ATO
M88AN58T·06
When RTS is high, the transistor is OFF, R3 resistor does not control gain calculation. The gain value
depends on R1, R2, R4.
When RTS is low, the transistor is ON, the gain value depends on R1, R2, R3, R4.
DEMODULATOR
RTS
ATO
0
FSK Modulated Signal
1
DTMF Signal
TRANSMIT GAIN
Gain
-
R3.R4
R1 .R2 + R2 .R3 + R3 .R1
-
R4
R1 + R2
• properly terminate the transmission line.
TS7513 reception performance is directly related to
duplexerquality. The duplexer is intended to provide
an interface between the TS7513 and the telephone
system. Since data flow is bidirectional on the telephone line, the duplexer must allow:
• the received signal to pass on the RAI input,
• properly couple the transmitted signal into the
line,
• minimize the local transmitted level towards the
receiver,
The duplexer consists of the following:
• an A input (transmission),
• a B output (reception),
• a C input/output (transmission/reception).
Transmission and reception signals are grouped on
a single wire on Input/output C.
TRANSMITTER-RECEIVER BLOCK DIAGRAM
ATO
TRANSMIT
A
C
-
AMPLIFIER
w
ovl-DUPLEXER
RAI
z
INTERFACE
Ow
itw
LINE
...
B
~
-'
W
I-
ovt--
ov
t--
M88AN58T-07
9/17
523
APPLICATION NOTE
There are three different gains on the duplexer :
• Gain from point A to point C : GT. This gain must
be constant for the frequencies transmitted (from
390 Hz to 2100 Hz).
• Gain from point A to point B : GD. This gain must
be lower than - 10 dBm in order to reject most of
the signal transmitted over point A.
• Gain from point C to point B : GR. This gain must
be constant for the frequencies received (from
390 Hz to 2100 Hz).
Solution proposed:
DUPLEXER BLOCK DIAGRAM
ov
c
ZL
M88AN58T·08
ZL stands for the line interface impedance loaded by
the telephone line (600 Q).
• The gain from point A to point C is :
GT=
ZL
ZL + R1
With R1 = 330 Q and if telephone line impedance is
600 Q gain GT = - 3.8 dB (a ratio of 0.65).
• The gain desired from point A to point B is GD = 0
GD
=-
R3
R2
+(1 +~) (
R2
ZL
)
R1 + ZL
If R2 = 12 kQ and R3 = 22 kQ, gain GD
tion is almost perfect).
10/17
524
~
0 (rejec-
Since all impedances (except the line impedance
ZL) can be accurately controlled, the duplexer rejection performance depends directly on ZL. In practice, due to the variations of the line impedance
which is not in reality a pure resistive load, an attenuation of around - 10 dB is assumed to be provided by the duplexer.
• The gain from point C to point B is :
GR=1 +
~
R2
With R2 = 12 kQ and R3 = 22 kQ, gain GR = + 9 dB
(a ratio of 2.8).
APPLICATION NOTE
LINE INTERFACE.
Duplexer connection to the telephone line via a line interface is given below.
TRl
Rl
TELEPHONE LINE
ov
TR1
RT1
Line transformer LTT220963L
Thermistor with positive temperature coefficient for current regulation of telephone
line CTP67090003.
The diagram above shows the following specific features :
• For transmission, the gain from duplexer point C
to telephone line is - 1.5 dB .
• For reception, the gain from telephone line to duplexer point C is - 4.5 dB (different from transmission).
The gain introduced by duplexer is + 9 dB. Therefore the gain introduced by the duplexer line interface unit is + 4.5 dB.
R1
C1
C2
Resistor 680 Q 3 w.
Capacitor 2.2 ~F 250 V.
Capacitor 10 nF 50 V.
M88AN58T-09
phone network (line impedance = ZL = 600 Q). If
TS 7513 circuit was used on a different telephone
network the duplexer line interface unit would
have to be changed.
Shaping stage. TS7513 reception performance is
directly related to duplexer quality and shaping
stage. The shaping stage is positioned across RFO
pin, the receive filter output, and RDI pin, the demodulator input.
Note: The duplexer line interface unit presented
above is designed to operate on the French tele-
11/17
525
APPLICATION NOTE
The shaping stage must perform the following functions:
• Eliminate the noise generated by the receive filter clock .
• Eliminate the continuous component of the signal
from the receive filter.
• Amplify this signal with a fixed gain up to 1.4 V
peak to peak and clip it symmetrically above
1.4 V.
DEMODULATION CONDITION
L1
------,t-ft-tH++++-------7'-tt--+t-tt-/k-----,-;t'--++-+--J-
SIGNAL ENVELOPE
2dB=-.......-RDI
ov
M88AN58T-12
• In the 1st stage, the gain is 21.6 dB (ratio of 12).
• In the 2nd stage, the gain is 16.6 dB (ratio of 6.8).
Therefore, the shaping stage presents a gain of
38.2 dB (ratio of 81.6).
• C1 eliminates any possible offset generated by
TS7513 receive filter.
• C2 eliminates switching peaks generated by receive filter clock.
• The diodes clip the signal at-0.7 Vor+0.7V.
In order to obtain a symmetrical clipping of the
stage in relation to 0 V, the unit R3C3 performs
a high pass filter (fc = 7.2 Hz) to eliminate the offset generated by the operational amplifier.
CIRCUIT EFG7189 : GENERATOR OF DTMF FREQUENCIES
The TS7513 has a DTMF input pin capable of receiving a signal from the DTMF frequency generator
EFG7189. When RTS is high, the signal is then filtered in a low-pass filter (fc = 3.4 kHz) and sent to
ATOpin.
The EFG7189 is a CMOS circuit. It operates with a
single voltage (+ 5 V) and uses a standard 3.579545
MHz crystal. It can generate eight different frequencies:
Four "low" frequencies: f1
f2
f3
f4
Four "high" frequencies: f5
f6
f7
f8
697 Hz
770 Hz
852 Hz
941 Hz
1209 Hz
1336 Hz
=1477 Hz
=1633 Hz
=
=
=
=
=
=
The signal transmitted is sent on MFOUT pin. It
consists of a "low" frequency and a "high" frequency. It is therefore possible to obtain 24 i.e. 16 pairs
of different DTMF frequencies. The frequency pair
is selected by four bits.
The acquisition of these 4 bits is parallel via A, B, C,
D pins, when H logic input is high.
The acquisition of these 4 bits is serial via A pin when
H logic input is low.
The ISA pin inhibits MFOUT analog output.
When ISA is high, MFOUT output is inactive and
connected to 0 V.
When ISA is low, MFOUT output is active and sends
a DTMF signal.
Validation of the hexadecimal code consisting of 4
bits occurs on a falling edge of ISA signal.
EFG7189 - TS7513 CONNECTION
The DTMF frequency generator EFG7189 uses a
crystal similar to that used by TS7513. To avoid
using two crystals, ClK pin on TS7513 delivers a
clock signal at a frequency of 3.579545 MHz which
is connected to the OSCIN pin on the EFG7189.
MFOUT pin on EFG7189 is directly connected to
DTMF pin on TS7513.
13/17
527
APPLICATION NOTE
CIRCUIT EFG 7189
Keyboard
Code
X
1
2
3
4
5
6
7
8
9
0
.
A
B
C
D
Hexadecimal Code
ISA
A
X
B
C
0
X
X
X
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1....
1....
1....
1....
1....
1....
1....
1....
1....
1....
1....
1....
1....
1....
1....
1....
Generated Frequencies
f(Hz)
f(Hz)
697
697
697
770
770
770
852
852
852
941
941
941
697
770
852
941
1209
1336
1477
1209
1336
1477
1209
1336
1477
1331
1209
1477
1633
1633
1633
1633
FREQUENCIES TRANSMITTED WITH RESPECT TO HEXADECIMAL CODE
HW$AAI
~
~
A~
~
~
B~
~
~
c~
mmm
~
:mmma
~
~
o
ISA
MFOUT
A
.--
n
t
770 + 1477
~
A
697+1209
~
EXAMPLE OF PARALLEL OPERATING MODE
H
ISA
-----------:11 ________
t~
~r__t~
MF OUT _ _ _ _ _ _ _ _....J1A_ _7....:70_+....:1...;..47...;..7_~L_.J
EXAMPLE OF SERIAL OPERATING MODE
14/17
528
____~r___
697 + 1209
LM88AN58T-13
G)-t
m-<
Z"tl
m-
JJO
~~
QJ--f 0 V
-tl"""
O~
JJ"tI
"tI
I"""
o
TRl lTT 220 963 L
~
-t
(5
Z
"zJ
~
~
~
~
o"T1
-t
CJ)
.....
.....
U1
W
s:
o
o
~(II
,,~
m
",,(II
@.
s:
!lI O
-t
~i!
CJ)
~
""I:
@(II
Z
+5V
~O
o
!7lz
~
lN4148
I"""
lN414B
100 pF
oZ
m
::lE
120 ki2
::::j
c:
»
"tJ
o
C
:I:
o
-t
-t
s:
"T1
5:
'"'"»
z
'"'"
()1
I\)
co
l~
I
~
..,.
-l S V
"tJ
o
»
::!
o
z
Z
o-I
m
APPLICATION NOTE
TELEGRAPHIC PERFORMANCE MEASUREMENT
GENERAL SPECIFICATIONS
Filter
Transmission line simulator 300 to 3400 Hz controlled characteristics :
It's used to measure the amplitude and group delay/versus frequency of :
• Output level (signal).
• Output level (noise).
• Group delay/HF - MF - BF.
• Amplitude filter HF - BF.
Gadem - logic system specially manufactured by
SGS-THOMSON Microelectronics.
• Filter.
• Modem output.
• Line simulator.
• Maximum transmission rate 19200 bits/sec.
• Generate normalized patterns.
_ Pseudo random 511 bits.
_ 1.0 ... with synchro.
_ Specific sequence.
• Clock recovery by DPLL.
• Bias distortion.
• Data transition statistics (distribution).
• Error counting.
• Error rates.
• Delay measurements between command and
status register.
MEASUREMENT PROGRAMS (EXTENDED
BASIC HP)
Menu
It's an interactive program to create a specific sequence of measurements.
Modem's measurements
It's the main program to control the execution of the
measurements (only one, for all modem's measurements).
Trace
Result treatment, graphic output.
16/17
530
MEASUREMENTS
Bias distortion
• Sequence 1.0 ...
• Gap between the mean of the time of the "1" and
the mean of the time of the "0".
• Expressed in percentage of clock period.
Telegraphic distortion
• Sequence pseudo random 511 bits.
• Gap between the theoretical transitions of the received signal (defined by the clock recovery by
DPLL) and the real position.
• Expressed in percentage of the clock period.
• More than 50 % of telegraphic distortion made
errors.
• Measurement may be :
_ Peak to peak.
_ Standard deviation.
_ Weighted (ex. value at 10 %).
Bit error rate
•
•
•
•
Sequence pseudo random 511 bits.
Line ...
White noise in the band 300 - 3400 Hz.
Ration ofthe number of false received bits to the
number of emitted bits, as a function of signal to
noise ratio.
APPLICATION NOTE
APPENDIX
CHARACTERISTICS OF CCETT LINES
CCETT Line 1 (Flatt
dB
ms
CCETT Line 2 (10
dB
%.
ms
Z 10
2 g
o
:II
i=
o
a:
o
C
oZ 5
o
,
"
A
:::l
~
Z
~
o
Hz
3000
2000
,
~:'~
-
~ 0
1000
, ,
,
~,
i=
CCETT Line 3 (90
%.
<
c
iii
-1
,
o
o ~
....
2000
3000
(5
Z
T
Hz
M88TS7513-10
M88TS7513-09
dB
m
V
'-"'"
1000
C
-
en
o
...
...»
-
I-
ms
CCETT Line 4 (50
dB
%.
ms
4
Z20
o
T -_
~ 15
3
,,
I-
!Ii
Q
!ij
C
~
2 <
c
Z10
o
iii
5
1
1=
"
:II
m
C
Z
w
Z
o
i=
~
:::l
g
0
o
A
o
1000
2000
3000
Hz
6
-1
oZ
:II
g
:II
T -_
li: 15
3
o
C
I-
m
en
2 ~
Q 10
<
Z
o
C
i=
~ 5
1
Z
w
1=
"
g
...
!:o
,.
:::!
0
o~
A
o
1000
2000
3000
Hz
M88TS7513-12
M88TS7513-11
~
~.,I
SGS·ntOMSON
17/17
~Oa::IlB@W~IiI:'ii'IlB@1ll0a::$
531
APPLICATION NOTE
A VERY LOW COST AND POWERFUL
SOLUTION FOR V.23 APPLICATION: TS7514
by O. Leenhardt - R. Girard
1. INTRODUCTION
The TS7514 is a single chip F.S.K. voiceband modem offering a real low cost powerful solution for all
C.C.I.T.T. V.23 recommended standard applications.
Indeed, TS7514 integrates many possibilities and
functionalities by requiring only very few external
components. Its block diagram is shown figure 1.
The TS7514 main features are:
ADDITIONAL FEATURES:
PROGRAMMABLE MODES:
• INTEGRATED DUPLEXER,
• AUXILIARY ANALOG SIGNAL TRANSMISSION (voiceband),
• AUTOMATIC BIAS DISTORTION ADJUSTMENT,
• TAX REJECTION FILTER (12 and 16 kHz),
• FIXED COMPROMISE EQUALIZATION,
LOW
COST
CRYSTAL
• STANDARD
(3.579 MHz),
• C.M.O.S. TECHNOLOGY,
• LESS THAN 100 mW POWER DISSIPATION,
• ± 5 VOLTS SUPPLIES,
• 24 PIN PACKAGE.
• MODEM 75/1200 or 1200/75 bps (full duplex on
2 wire line),
• MODEM 75/75 or 1200/1200 bps (full duplex on
4 wire line),
• D.T.M.F. DIALING,
• ANALOG TEST LOOP,
• TONE DETECTION (ring, dialing, ... ),
PROGRAMMABLE FUNCTIONS:
•
•
•
•
•
TRANSMIT/RECEIVE LEVELS,
RECEIVE FILTER GAIN,
HYSTERESIS AND DETECTION LEVELS,
LINE MONITORING LEVEL,
SIGNALLING FREQUENCY (2982 Hz) LEVEL,
AN349/0489
1/12
533
c.n
~
~
"TI
c'
c
..
i\)
CD
»
1:1
1:1
I"'"
o
»
-I
ATxl
o
Z
ATO
T,D
z
o-I
m
?RD
EN?
RTS
MCJBC
~
MOO/DTMF
@m
WlO
lUI'
Ii!
RAil
~O
.. Ii:
DCD
I!:
~.
RAOI
RAI2
""0
RA02
zcc
;::
00
~
6
'"
RDI
RFO
XtalOUT
XtailN
V+
AGND
DGND
v-
!!
.
(Q
c
(I)
+ SV
I\)
EXTERNAL
SIGNAL - - - - - - - - - ,
GNDA
VRAO 1
TxD
I
0
~
~CII
~;!
!lI O
~I
~O
M.C.U.
I I
~Z
RAil I
TS
MOD/OTMF
R
ENP
RA02
0
oeD
VvLO
zeo
RFO
(*). REGULATIO~~ REQUIRED IN FRANCE ONLY
01
'"
TRISIL
TPA 270A 18)
•
I
L..-..+<""""i_+__<> L2
U18.-J
K I J12K
\"
.....
9
12K
12
I=:::
0
TPH2
',>
RAI2 f--+--
100 nF 39 K
EXTAL
01
7514
T
S
'" I~~
ATO
RTS
Me/BC
L
•
Ll1
TPH 1
PRO
N
~t;:
@.
0
5600
RxO
C
• ,
1-.' •
i
TO
:
~ LOUDSPEAK
6 , _K
~
AMPLI
mJ'
R:j---r22 IJ.F
lN~.sv
»
"tI
"tI
!:
(')
»
::::!
o
z
z
o
-I
m
APPLICATION NOTE
This application note describes some of the TS7514 most important features detailed before from a typical
and simplified application scheme shown figure 2 (more informations are given in the following sheets).
2. PROGRAMMABLE MODE
2.1. WITH WHAT TO PROGRAM?
The TS7514 contains 8 control registers.
The programming used is serial where data input is
TxD or PRD and clock input RTS.
From now, it is important to point out that during programming, the RTS (Request To Send) signal and
the TxD (Transmit Data) signal to be transmitted
from the local terminal over the telephone line are
internally safeguarded in order to not modify the
transmission.
_ By using TxD either to program or transmit data,
only one signal has to be managed. In this case,
you must take in care to program the TS7514 out
of the transitions between two successive data
bits and during a maximum duration equal to a
"bit time" (833.3 llSec. in 1200 bps) to avoid
transmission errors.
_ By using PRD to program the TS7514 allows to
use TxD only for data to be transmitted and
avoids the preceeding cautions but requires the
management of these two signals.
The choice will depend on the application (microcontroller used, number of 1/0 ports, ... ).
TxD is selected by ENP = "0"; PRD by ENP = "1".
2.2. HOW TO PROGRAM?
The programming is indirect via an 8 bit shif1 register, called input register, least significant bits first.
The 4 M.S.B.'s of the input register are the address
of the control register to program; the 4 L.S.B.'s the
data.
The ~ut register is selected by MOD/DTMF =
Me/Be = "0".
Then, RTS (Request To Send) and TxD (Transmit
Data) signals are internally safeguarded and the
corresponding pins must be used as clock (RTS)
and data to be programmed (TxD).
The RTS clock, active on the falling edge, shif1s the
programming data available on TxD or PRO.
The transfer of programming data to the control register previously addressed is made by rising
MOD/DTMF or Me/Be.
From now, the RTS signal comes back to its previous functioning mode: Request To Send.
There are 2 cases of end of programming:
_ At the end of programming of all the control registers, exce~d RDTMF, MOD/DTMF rises to
"1" while Me/Be indicates the channels used for
transmission before programming ("0" for low
channel transmission, "1" for high channel transmission).
At the end of programming of RDTMF register
only, Me/Be rises to "1" while MOD/DTMF and
RTS are "0" during all the time of D.T.M.F. signal
programmed transmission.
2.3. TIMING DIAGRAMS
Programming without Transmission.
TxO or
PRO
___
MC/BC_~
__~____________________________________________~r==
M88AN3-02
4/12
536
APPLICATION NOTE
Programming during Transmission.
RT5
MOD/~L__~====~==~====~==~~==~==~~==~==~~
TxD
3
MClSt\
M88AN3·03
DTMF Programming and Transmission.
Programming
~4 Transmission ~
l
M88AN3·04
3. THE TS7514 REGISTERS
We are going to describe now the most important points to know about these eight control registers.
Notes ~n the following, all the bits described are the data bits of the control registers (X = don't care).
For additional informations on these registers, refer to the TS7514 corresponding data sheet.
3.1. MODE REGISTER: RPROG
This control register allows to choose the functioning
mode of the TS7514 : either two different or the
same channels for transmit and receive.
The most used mode (power-up initialization) is the
receive channel prog rammed in the op...QQ.site way to
the transmit channel controlled by MC/BC pin. In this
. case, bits 2 and 3 must be programmed to "0".
If bit 3 is programmed to "0" while bit 2 is programmed to "1", then transmit and receive channels are
the sameJ.!:!lgh channel if MC/BC is "1", low channel if MCIBC is "0").
This last mode can be used for the full duplex on 4
wire line modem functioning or for the test with an
external analog loop between transmit and receive
sections (this last mode is not a loop 3 (see RPRF
register)) .
5/12
537
APPLICATION NOTE
3.2. D.T.M.F. REGISTER: RDTMF
This register is not initialized at the power-up.
This control register allows the D.T.M.F. dialing from
the TS7514.
The following table give the correspondance between the digit to be dialed and the data to be programmed.
Bits 0 and 1 program the 4 low frequencies of the
D.T.M.F. signal, bits 2 and 3 the 4 high frequencies.
DIGIT
D3
D2
D1
DO
0
1
2
3
4
5
6
7
0
0
0
1
0
1
0
0
1
0
0
1
0
1
1
1
1
0
0
1
0
0
0
1
0
0
0
1
1
1
0
0
0
0
8
9
A
B
C
D
1
0
0
1
0
0
1
1
1
1
1
.
0
#
1
3.3. TRANSMIT ATTENUATION REGISTER:
RATTE
This control register allows to program a transmit attenuation from 0 (0000) to 13 dB (1101), with 1 dB
step.
With such values, the analog transmit output level
on ATO pin varies from + 4 (0000) to - 9 dBm
(1101 ).
0
0
0
1
1
1
0
0
1
1
1
1
1
0
1
1
1
Low Fre.
(Hz)
High Fre.
(Hz)
941
697
697
697
770
770
770
852
852
852
697
770
852
941
941
941
1336
1209
1336
1477
1209
1336
1477
1209
1336
1477
1633
1633
1633
1633
1209
1477
of the hybrid (typically 20 dB) and thanks to the
TS7514 internal architecture (see figure 1), the receive signal monitoring being implemented before
the receive filter.
3.5. TRANSMIT FILTER register: RPTF
Such attenuation is automatically programmed at
the power-up initialization. So, a different attenuation will have to be programmed to transmit data (typically 0 dBm (0100) on ATO pin).
This control register allows to transmit on ATO pin
one of the following signals:
_ normal (power-up initialization) modem or
D.T.M.F. signals (0000),
_ extemal voiceband analog signal through:
• smoothing filter and attenuator
(0001),
• low-pass filter and attenuator
(0010),
• band-pass filter and attenuator
(0011),
_ low frequency only (0100) in D.T.M.F. mode,
_ high frequency only (1000) in D.T.M.F. mode.
3.4. LINE MONITORING REGISTER: RWLO
3.6. RECEIVE FILTER register: RPRF
This control register allows:
_ to monitor the transmit signal from - 10 (0000)
to - 40 dB (0011) with 10 dB step,
_ to monitor the receive signal from 0 (0100) to
- 30 dB (0111) with 10 dB step,
_ to send a square wave signalling frequency
(2982 Hz) with a level comprised between - 4
(1000) and-34dBm (1011).
This register is initialized to 11 XX (neither monitoring nor signalling transmission) at the power-up.
This control register allows to program different
configurations for the receive filter:
_ receive filter gain of 0 (XXOO), 6 (XX01) or 12 dB
(XXi 0),
_ receive channel looped back on the transmit
channel with a - 35 dBm level and a 0 dB gain
(XXii) for analog test loop (loop 3),
_ receive filter bypassed (Xi XX) or not (XOXX),
_ extemal connection (1 XXX) via a 2.2 j.tF non-polarized capacitor between RFO and RDI pins.
If a receive signal monitoring is programmed, it is
possible to monitor also simultaneously the transmit
signal on account of the non infinite rejection ratio
The extemal connection (bit 3 programmed to "1")
with the capacitor is the most used mode to connect
the receive filter output to the demodulator input.
Two programming values (1110 and 1111) allows
an infinite attenuation.
6/12
538
APPLICATION NOTE
Nevertheless, if an internal connection is used, bit 3
has to be programmed to "0" and external capacitor and connection between RFO and RDI pins have
to be suppressed.
This register is initialized to X001 (receive filter enabled with 6 dB gain) at the power-up.
3.7. DETECTION LEVEL AND HYSTERESIS REGISTER : RHCD
This register allows to control:
_ the loss carrier detection level between - 41
(XOOO) and - 27 dBm (X111) with 2 dB step,
_ the hysteresis between carrier detect on and off
: 2.5 (OXXX) or 3.25 (1XXX) dB.
Be careful that the loss carrier detection level value
(N2) is given related to the demodulator input (RDI).
The on-line loss carrier detection level (NL) is obtained by substracting from N2 the receive filter and
the hybrid gain values.
4. THE 4/2 WIRE CONVERSION: THE HYBRID
The TS7514 integrates two operational amplifiers.
So, the hybrid implementation consists of selecting
only 5 resistors in order to obtain the best adaptation and rejection possible.
In consequence, the on-line detection level is obtained by adding to NL the hysteresis value.
This register is initialized to 0000 ( - 41 dBm for loss
carrier detection level with a 2.5 dB hysteresis) at
the power-up.
3.8. RECEIVE CHANNEL REGISTER: RPRX
This control register allows to program different
configurations for the receive channel:
_ to use a wide (for data and tone detection)
(XXOX) or a narrow (for data only) (XX1 X) band
filter for the receive low channel,
_ to suppress (XXX1) or not (XXXO) the carrier detection delays for a "fast" carrier detection (DCD
digital signal following the receive carrier signal
level variations).
This register is initialized to XXOO (wide band filter
and carrier detection delays) at the power-up.
With 5 % resistors and a transformer 600Q/600n
respecting the local agreement conditions, the hybrid so designed offers an ATO/RA02 rejection ratio upper than 20 dB.
Figure 3.
RAO I 1------.-_-,
RAil t-...------_t--'
ATO
RAI2 1--+-----'
RA02
M88AN3·05
7/12
539
APPLICATION NOTE
5. THE D.T.M.F. DIALING
To dial a digit (0, ... , 9, A, S, e, D,*,#) in D.T.M.F.
consists of programming the RDTMF control register like an other register but leavin9......9l.the end of
programming, the MOD/DTMF and RTS signals to
"0" during all the time desired (in practise, the time
of pressing key on a dialer).
No external component is required for this dialing.
6. RING DETECTION
Thanks to zeo output, it is possible to obtain in a digital way the analog zero crossing signal available
on the RA02 pin of the TS7514. Then, by not totally insulating the modem from the telephone line (L 1,
L2) and bypassing the receive filter, zeo can deliver the digital form of the ringing signal that may be
then processed by the microcontroller.
With the scheme given figure 4, we avoid to use opto-coupler and other external associated components to detect ring, the only external components
required being a resistor and a capacitor.
Figure 4.
=-_ _ _ _ _ _ _-{) TPH 1
~~---~----oLl
TPA 270P. 18
(SGS THOMSON)
= - - ! - - - - - + - - - o TPH2
CNT
~
0>------------
7K
1~_41+~g~,~
2N2222
. ""'\
+5V
(*): REGULATION REQUIRED IN FRANCE ONLY
M88AN3-06
When the modem is connected to the telephone line
(L 1, L2), the components are bypassed (see relay)
and the telephone set (TPH 1, TPH2) disconnected.
Do not forget during the detection to bypass the receive filter in the RPRF register (bit 2 programmed
to "1 ").
The ringing signal (50 Hz alternative voltage superimposed to the 50 V telephone line voltage), is so
attenuated by the resistor but the level is sufficient
to be detected by the TS7514.
So programmed, the TS7514 output on zeo pin a
50 Hz digital signal and on DeD pin the ring "enveloppe" (figure 5).
8/12
540
APPLICATION NOTE
Figure 5.
1.5 S
••
,-------,I
< - - I_
_
M88AN3-07
7. TONE TRANSMISISON AND DETECTION
7.1. 2100Hz TRANSMISSION
To send the 2100 Hz answer tone over the telephone line, the TS7514 must be programmed as follows:
_
_
_
_
MOD/DTMF = "1" (modem),
MC/BC = "1" (main Channel),
TxD = "0" (2100 Hz),
RTS = "0" (transmission).
/
\~\~
/
M88AN3-08
7.2.2100 Hz DETECTION
To detect the 2100 Hz answer tone sended by the
far-end modem, the TS7514 must be programmed
as follows:
_ RTS = "1" (no transmission),
_ MODIDTMF = "0" (tone detection),
_ MC/BC = "0" (back channel).
So programmed, the TS7514 detects the 2100 Hz
answer tone on line if DCD = "0" (carrier detection)
and RxD = "0" (2100 Hz).
9/12
541
APPLICATION NOTE
\'-------MC/BC
LINE
\C--_----'/
RxD
DCD-~\\
/r-"r;- - M88AN3-09
7_3_ LOW FREQUENCY TONE DETECTION
To detect low frequency tones (typically the 440 Hz
dialing tone in France) ; the TS7514 must be programmed as follows:
_ RTS = "1" (no transmission),
RTS
/
-----'
_ MODIDTMF = "0" (tone detection),
_ MCIBC = "1" (main channel),
Then, such tones are present on line if DCD
(carrier detection).
= "0"
\'----
MOD/DTMF
MCIBC
LINE
DCD
M88AN3-10
Note: In lhis mode, the RPRX register is automatically programmed to wide band filter for the receive low channel.
8_ LINE MONITORING
To monitor the different signals present on the telephone line, figures 6 and 7 give two typical loudspeaker amplifier application schemes.
10/12
542
Thanks to RWLO monitoring level programming register, no external potentiometer is required to adjust the volume.
APPLICATION NOTE
Figure 6.
+5V~------~--------------------~
(80)
7
3
WLO O--------------j
(TS 7514)
LOU.SPEAKER
TeA 820M
47UF~
I
+5V 100nF
100nF
M88AN3-11
Figure 7.
+5 VID------.---...-------,~
Il00nF
470uF
WLO
(TS 7514)
4
TDA 7231
LOUDSPEAKER
3
(80)
5 8
.L
M88AN3-12
9. OTHER FEATURES
_ by ATxl, it is possible to send a voiceband signal over the telephone line,
_ the XtalOUT may be used to implement via a
buffer, the external clock of the microcontroller,
_ the lay-out implementation must be as clean
as possible in order to obtain the best electrical performances:
• separation between analog and digital parts and
tracks of the board,
• analog and digital grounds separated and
connected in a single point,
• a ground plane for the component side,
• a star distributed power supplies (idem for
ground) to avoid any possible loop,
• a maximum capacitive uncoupling as close as
possible to the device,
• a connection as short as possible between RFO
and RDI via the external capacitor.
11/12
543
APPLICATION NOTE
10. CONCLUSION
We just saw, with this application note, the different
functions and internal possibilities included in the
TS7514 among which D.T.M.F. dialing, integrated
duplexer, tone and ring detection and transmit and
receive channel programmings are the most interesting.
For these features and all the others, only about 20
external passive components (resistors, capaci-
12112
544
tors, ... ) are required (out of microcontroller interface) to implement a complete V.23 modem.
The TS7514 is a real low cost and powerful solution
for all C.C.I.T.T. V.23 recommended standard applications.
POWER SUPPLY MODULE
545
GS-MS1212
13W TRIPLE OUTPUT DC-DC CONVERTER MODULE
unit can be supplied either with a center tapped
transformer secondary winding or a DC voltage.
• MTBF IN EXCESS OF 200.000 HOURS
• 2A OUTPUT CURRENT @ 5V
• ± 12V/0.125A OUTPUTS
• WIDE INPUT VOLTAGE RANGE
• 75% EFFICIENCY
• PROTECTED AGAINS SHORT CIRCUITS
• VERY LOW RIPPLE AND NOISE
Two unregulated outputs (± 12V @ 125mA) useful
for LED lamps or relay supply are also available.
DESCRIPTION
The unit is characterized by a .65 inches maximum
height to allow a 1 inch board spacing.
These outputs are not short circuit protected and an
input fuse on the input retum is recommended.
The GS-M51212 is a versatile triple output module
specifically designed for modem boards supply. The
MAIN CHARACTERISTICS
Output Voltage
(V)
V1
V2
V3
V4
V5
+ 5.1
+ 12.0
- 12.0
+ 12.0
- 12.0
± 4%
± 5%
± 5%
unr.
unr.
Output Cu rrent
(A)
Input Voltage
(V)
Output Ripple
(mVpp)
Eff.
(%)
2.000
0.125
0.125
0.125
0.125
±12Vdc ± 25%
or
9 + 9Vac ± 25%
50
20
20
1600
1600
75
ELECTRICAL CHARACTERISTICS
(T amb = 25°C and V in = 9 + 9V ae ± 12V de unless otherwise specified)
Symbol
Parameter
Input Data
Maximum DC Input Voltage
Maximum AC Input Voltage
Output Data
Minimum Load Current (5V output)
Current Limitation Intervention
Environmental Data
Operating Temperature Range
Storage Temperature Range
March 1989
Value
Unit
±15
11,25 + 11,25
V
V
200
<3
mA
A
o to + 70
- 40 to + 85
°C
°C
1/4
547
GS-MS1212
USER NOTES
INPUT VOLTAGE
The recommended operating maximum DC input
voltage is ± 15V inclusive of the ripple voltage.
The recommended operating maximum AC input
voltage is 11,25 + 11 ,25V derived by a transformer
center tapped secondary.
MODULE PROTECTIONS
The module is protected against occasional and
permanent short circuits of the regulated output pins
to ground, as well as output current overload. The
two unregulated outputs are not protected versus
short circuit.
THERMAL MANAGEMENT
The module is rated for correct operation up to an
ambient temperature of 70·C assuming a sufficient
air volume in the surrounding is provided to allow
normal correction.
Figure 1 : GS-M51212 Block Diagram.
<> + 12V
+12Vdc
9 Vac
o
9
0
,..
,...
Vat
RECTIFIER
,..
..... +5V/2A
r-SWITCHING
() + 12v/0.125A
REGULATOR
() -12V/O.125A
AND
FILTER
Unr/0.125A
r--
,..
-12Vdc
GND
J
<> -12V
2/4
548
Unr/0.125A
GS-MS1212
Figure 2 : GS-M51212 Typical Application.
Relays &
LEO Supply
-12 unr 1+12 unr
+~v
"T
A~
Lin~
~
>
+'~v
GS-MS1212
~
~
MODEM BOARD
-12V
"I
IG~
PIN CONNECTION
Pin
1
Function
VacNDC IN
2, 3, 4 Ground in
Description
AC Input Voltage. Recommended voltage is 9 VDC or 12 VDC.
Return for Input AC/DC voltage. The transformer center tap must be connected to this
pin. This pin is also the return path.
5
VacNDC IN
Input Voltage. Recommended voltage is 9V or 12VDc.
6
- 12Vunr
Unregulated - 12V output
7
+ 12Vunr
Unregulated + 12V output
+ 5V
Regulated 5V output
10
Ground out
Return path for regulated outputs. Connected to pin 2/314.
11
- 12V
Regulated - 12V output
12
+ 12V
Regulated + 12V output
13
Enable
Hardware Enable Pin.
This pin must be tied to pin 11 to operate the unit.
14
En. return
Return path for the Enable.
8, 9
~
""1' SCiS·ntOMSON
IiliiG©OO~~DiI@I!'JG©iIl
3/4
549
GS-MS1212
MECHANICAL DRAWING
46.99
r--I
'"d
"
...on '"d
I
I
12t
...on
1':=N
I
j
I
N
.\~.
~.
8
~
14
I
COMPONENT
SIDE
'"c;
~
I
'"'"
c.~
"!
f--
1..
7
2.54..~iJO.16
50.8
4/4
550
'".non
....
r-1.9
I
DSP OAT ASHEETS
I .
551
5T18930/31
DIGITAL SIGNAL PROCESSOR
• 80 ns INSTRUCTION CYCLE TIME * (1.2 ~
CMOS technology)
• PARALLEL HARVARD ARCHITECTURE
• SEPARATED PROGRAM AND DATA BUSES
• THREE DATA BUSES STRUCTURE
• DUAL EXTERNAL BUSES
• ONE CYCLE 16-BIT RfW OPERATION ON EXTERNAL DATA MEMORY
• THREE DATA TYPES: 16-BIT REAL, 32-BIT
REAL, 16 + 16-BIT COMPLEX
• HARDWARE MASKABLE INTERRUPT
• COMPLEX MULTIPLIER
• 320 x 16-BIT INTERNAL RAMs, 512 x 16-BIT INTERNAL COEFFICIENT ROM
• 3 K x 32-BIT WORDS OF INTERNAL PROGRAM ROM
• LOW POWER MODE
• REALTIME EMULATION OF ST18930 ROM
VERSION WITH ST18931 ROM LESS VERSION
up to 64Kx32-bit external instruction memory and
allows a total realtime emulation of the ST18930.
It is also particularly well adapted for applications
where large program memory is required or for
low quantities.
DEVELOPMENT SYSTEMS
The ST18930 is supported by a complete set of
hardware and software tools for applications development. Software packages include assembler, linker and simulator on VAX and PC as well as a high
level "C" compiler and optimizer.
Hardware tools include a stand-alone emulator,
eprom emulation module and a powerful multiprocessor development station.
DESCRIPTION
The ST18930/31 HCMOS digital signal processors
are members of SGS-THOMSON family of general
purpose DSP's fully software and hardware compatible with previous members of the family.
By virtue of their highly parallel architecture, these
digital signal processors are well suited to a wide
range of applications including those requiring operations on complex numbers.
Typical examples are found in telecommunications,
modems, image and speech processing, high
speed control, digital filtering, sonar and radar applications.
They are able to execute simultaneously within
100 ns an ALU function, a Multiplication, two Read
and one Write operations with associated address
calculation.
The on-chip large memory resources and multiprocessor direct interface allows the development
at the lowest cosVcomplexity of high performance
applications. The ST18931 is the ROMless version of the ST18930. In addition of the ST18930
features, it provides the capability of addressing
December 1988
ST18930
P
DIP 48
(Plastic Package)
ST18930
FN
PLCC52
(Plastic Leaded Chip Carrier)
ST18931
R
PGA121
(Pin Grid Array Ceramic)
For pin connections and order codes,
please see inside
1/66
• Also available 100 and 160 ns cycle time versions.
553
ST18930/31
TABLE OF CONTENTS
Page
1.
BLOCK DIAGRAM
5
2.
PIN DESCRIPTION
6
3.
FUNCTIONAL DESCRIPTION
8
3.1
General architecture concept
8
3.2
Operating unit
9
3.3
Data memories
12
3.4
Sequencer block
13
3.5
Inputs / Outputs
15
3.6
Other resources
23
4.
TYPICAL APPLICATION CONFIGURATIONS
25
5.
INSTRUCTION SET
29
6.
ELECTRICAL SPECIFICATIONS
42
7.
PIN CONNECTIONS
57
8.
ORDER CODES
58
9.
PACKAGE MECHANICAL DATA
58
TABLE OF APPENDICES
2/66
554
A.
BENCHMARKS
60
B.
DEVELOPMENT PROCESS
61
C.
MASKING INFORMATION
62
D.
SUMMARY OF RESOURCES/FUNCTION
64
ST18930/31
TABLE OF FIGURES
Page
Figure 1 : Pin description.
6
Figure 2: ALU block diagram.
10
Figure 3 : Multiplier efficiency.
10
Figure 4 : Data memory blocks.
13
Figure 5 : Interrupt inputs and conditions.
15
Figure 6 : Dual bus interface - system configuration.
16
Figure 7 : Local bus description.
17
Figure 8 : 8eparate local buses.
17
Figure 9 : 8ystem bus description.
18
Figure 10: Mailbox connection.
19
Figure 11.A : Mailbox exchange - example 1.
20
Figure 11.B : Mailbox exchange - example 2.
21
Figure 12 : Reset timing.
24
Figure 13 : Configuration example 8T18930 + RAM + MAFE.
25
Figure 14: Configuration example 8T18930 + RAM.
26
Figure 15: Configuration example 8T18930 + RAM + MAFE.
27
Figure 16: Interfacing CROM. IRAM to 8T18931.
28
Figure 17 : OPIN calculation instruction with indirect addressing.
31
Figure 18 : OPOI calculation instruction with direct addressing.
32
Figure 19 : OPIM calculation instruction with immediate operand.
33
Figure 20 : ASR, LSL, LSR, ROR shift instructions.
34
Figure 21 : BRI immediate branch instructions.
35
Figure 22 : BRC computed branch instructions.
36
3/66
555
ST18930/31
Page
Figure 23 : SVR data transfer instructions.
37
Figure 24 : INI initialization and control instruction.
38
Figure 25 : Clock and control pins timing for Extal .,. 2 mode (80 and
100 ns cycle time).
42
Figure 26 : Clock and control pins timing for Extal .,. 4 mode (160 ns and
TS68930/31 compability).
Figure 27: Reset timing for intemal machine cycle Tc
= 2· EXTAL.
43
43
Figure 28 : Local bus timing diagram.
45
Figure 29 : System bus timing diagram for transfer of one byte.
46
Figure 30 : Instruction interface timing diagram (ST18931 only).
48
Figure 31 : Timing diagram for intemal machine cycle Tc = 4 x leex
(ST18931 only).
49
Figure 32 : CLKOUT output period.
50
Figure 33 : Local bus "Motorola" write cycle timing diagram.
51
Figure 34 : Local bus "Motorola" read cycle timing diagram.
51
Figure 35 : Local bus "Intel" write cycle timing diagram.
52
Figure 36 : Local bus "Intel" read cycle timing diagram.
52
Figure 37 : Multicycles exchange exemple on local bus,
"Motorola" write cycle.
53
Figure 38 : Multicycles exchange exemple on local bus
"Motorola" read cycle.
4/66
556
53
Figure 39 : System bus, "Motorola" write cycle timing diagram.
54
Figure 40 : System bus, "Motorola" read cycle timing diagram.
54
Figure 41 : System bus, "Intel" write cycle timing diagram.
55
Figure 42 : System bus, "Intel" read cycle timing diagram.
55
ST18930/31
1. BLOCK DIAGRAM (ST18930)
L-BUS
,
,--'M~'-IN~
16
R·BUS
~
RIN
MULT.
_
Jl~'7 I~
,-_~_~,RO~UT~
X RAM
192 x 16
Y RAM
I
C ROM
128 x 16
I
512 x 16
XO
YO
X1
Y1
~
Y-
B
7
Z-BUS
8
12
CA~
~
l! l!
l~~
n
---,
CO
~
l~
~
"'
I
Control
I--Loo--f-t+---t--==-
MAILBOX
,----
ADO-AD7
f:
4 Address
2 Control
EO
00-015
C1~
16
12
I·BUS
LC
SEO
EXTAL
•I •L
XTAL
Clockout
Reset
7 branch Inputs
M88ST18930-02
3 Interrupts
DEFINITION OF ACRONYMS
L-bus
: Left data bus
CRaM
R-bus
: Right data bus
XO, X1, X : Addressing registers XRAM
: Coefficient ROM
M
: Multiplier input register
YO, Y1, Y : Addressing registers YRAM
N
: Mu Itiplier input reg ister
CO, C1
: Addressing registers CRaM
P
: Multiplier output register
EO, E1
: Addressing registers ERAM
BS
: Barrel Shifter
XACU
: Address calculation unit XRAM
ALU
: Arithmetic and Logic Unit
YACU
: Address calculation unit YRAM
D
: ALU output register
ECACU
: Address calculation unit CRaM & ERAM
RC
: Replace Code register
RIN
: Input register of mailbox
STA
: Status register
ROUT
: Output register of mailbox
FIFO
: ALU output FIFO
AMR
: Access mode register
A
: ALU accumulator
IR
: Instruction register
B
: ALU accumulator
PC
: Program counter
z- bus
: Result data bus
RAS
: Retu m address stack
T
: Transfer register
SEQ
: Sequencer
XRAM
: X Data RAM
LC
: Loop Counter
YRAM
: Y Data RAM
IROM
: Instruction ROM
5/66
557
ST18930/31
2. PIN DESCRIPTION
Figure 1 : Input/Output Pins.
1- -
-
-
-
-
-
-
-
-
-- -
-
-
-
-
-
-
-
-
-
-
-
-
-
--
11--------------------------l 1
,, ''
4 "1 1 - - - - - ADO·AD7
AO-A?
*
A8·A1l
16
CS---
DO:015 or <===)
=
RS
SYSTEM
control
& handshake
BUS
00-07
08·015
SR/WorSWR
SDSor SRD
LOCAL
R/WorWR
IRQ
DTACK
BUS
(11
SA
DS or RD
(1
control
8T 18931
CLKOUT
BSO or ITO
BS1 or IT1
BRANCH
CONDITIONS
VDD
BS2 or IT2 or LP
VSS
BE3
EXTAL
BE4
XTAL
&
INTERRUPTS
BE5 (1)
BE6
(1)
:---HALT
CC
Me
CSDL
INCYCLE
CAO.CA9 (21
8T 18931
CSDH
100·1031
NOP
IAO·IA1S
LP
M88ST18930-01
Notes: 1. these pins are shared and software programmable: BE5/DTACK, BE6/BA
2. AO·A? and ADO-AD? may be multiplexed.
6/66
558
ST18930/31
LOCAL INTERFACE
Name
Pin
Type
Function
Description
DO-DI5
I/O
Data Bus
AS-All
Address Bus
High order addresses for local interface (RAM).
Data Strobe/Read
Synchronizes the transfer on local bus/read cycle.
Read/write/Write
Indicates the current bus cycle state/write cycle.
CLKOUT
0
0
0
0
Clock Output
Frequency programmable from EXTAL ... 2 to EXTAL ... 16.
AO-A7
I/O
Address Bus
Low order addresses for local interface (RAM).
DS or RD
R/WorWR
Can be concatenated or separate D (0 : 7), D (S : 15).
SYSTEM INTERFACE
Name
Pin
Type
ADO-AD7
I/O
Function
System Data Bus
Description
System data bus for exchanges between the processor and a hosl via
the mailbox.
CS
I
Chip Select
Used by a host to gain access to the mailbox and system bus.
RS
I
Register Select
Used by a host to gain access to the mailbox and system bus.
SDL
or SRD
I
Data Strobe/read
Synchronizes the transfer on the system bus/read cycle.
SRIW
or SWR
I
Read/write/Write
Indicates the current system bus cycle state/write cycle.
DTACK
0
Data Transfer
Acknowledge
Indicates that the processor has recognized the access data transfer.
BA
0
0
IRQ
Bus Available
Indicates the availability of the sytem bus to the host.
Interrupt Request
Handshake signal sent to the host 10 gain access to the mailbox.
EXTERNAL BRANCH CONDITIONS AND INTERRUPT
Name
Pin
Type
BSO-B~
Function
Description
or ITO-IT2
I
I
Branch on State
Interrupt
External Branch Conditions.
(low power mode through BS2 see 3, 6, 4) Interrup Input Pins
BE3-BE6*
I
Branch on Edge
External conditions. Falling edge is memorised and reset when tested.
* BE5 shares pin with ~
BE6 shares pin with DTACK
OTHER PINS
Name
EXTAL
XTAL
Pin
Type
Function
I
Clock
0
Clock
Voo
I
Power Supply
VSS
I
Ground
RESET
I
Reset
LP
I
Low Power
Description
Are used for crystal oscillator; if crystal oscillator is not used, pin XTAL
is not connected.
Active at high state. Freezes the circuit operation.
7/66
559
ST18930/31
INSTRUCTION INTERFACE AND SYSTEM CONTROL INTERFACE (ST18931 only)
Name
100-1031
IAO-IA15
CAO-CA9
Pin
Type
I
0
0
Function
Description
Instruction Data
Instruction Address
Coel. ROM Address
or External RAM
Address
Instruction Data Bus
Instruction Address Bus
External coefficient ROM address 10 bit
(9-bit address - output enable signal)
or
External RAM address
(8-bit address)
HALT
I
Halt Signal
Halts the processor. This signal freezes the program and loop
counters
INCYCLE
0
Instruction
Cycle Clock
A transition from low to high indicates that a new instruction is
processed
Hardware NOP
Force NOP instruction for development system.
Bus Low Z Control
DO - 07 (CSOL) and 08 - 015 (CSOH) are data valid control pins for
external buffers
NOP
I
CSOL
CSOH
0
CC
I
MC
0
Clock Cycle Control
Machine cycle = 2 Tc (EXTAL) or 4 Tc (EXTAL)
Master clock
EXTAL
+
2 Output
3. FUNCTIONAL DESCRIPTION
3.1. GENERAL ARCHITECTURE
· Execute a multiplication
The ST18930/31 architecture is based upon the innovative architectural concepts already proven in
the previous members of SGS-THOMSON digital signal processors family.
· Perform an ALU operation
Therefore, the compatibility is kept at object code level with the TS68930/31.
· Store data into the transfer register
The ST18930/31 confirm the efficiency of a highly
parallel and pipelined operation using a true Harvard
memory space and bus structure. This efficiency is
there improved by the advanced 1.2 f.l HCMOS technology providing 80 ns instruction cycle.
The block diagram shows four main blocks:
· The sequencer block
· The operating unit (ALU, Multiplier and Barrel Shifter)
· The data memories
· The inputsloutputs
These four blocks can be considered as four independent units working in parallel and communicating through a network of 16/32 - bit buses.
By taking advantage of the 32 - bit wide instruction
bus, the ST18930/31 are able to execute simultaneously the following operations during each 80 ns
machine cycle:
· Read two operands from internal or external memory
8/66
560
· Write a result into internal or external memory
· Post modify three pointers independently
In addition, data exchanges through mailbox occur
concurrently and independently of internal operations.
All instructions are executed in a single cycle time
except branch instructions.
Some additional features give the ST18930/31 extremely powerful performances. They provide three
operating modes (real, complex and double precision) dynamically set by software and user transparent.
In complex mode, the hardware multiplier provides
(16 + 16 - bit) results from 2 x (16 + 16 - bit) inputs
each machine cycle.
(25 - million multiplications per second).
The ALU, reinforced by a barrel shifter, provides 30
basic arithmetic and logic functions.
Three dedicated calculation units control the four
data memory spaces.
A large 3Kx32 (96Kbits) program ROM (for the
ST18930) enlarge the usual digital signal processor
applications possibilities, using the efficiency of the
ST18930/31
code and architecture. The following sections will
detail all the hardware blocks of the ST18930/31
and demonstrate its software performances provided by the high level of parallelism in the operations.
The high degree of parallelism of the ST18930/31
processor allows more combinations than previous
generation DSP devices which require a more complex instruction set.
3.2. OPERATING UNIT
The complete list of ALU codes and description is
given in 3.8.2.
One of the most useful features of the ST18930/31
is to provide the user three operating modes which
can be dynamically set by software.
These three modes are:
· REAL 16 - bit
· COM PLEX 16 - bit real + 16 - bit imaginary
· DOUBLE PRECISION 32 - bit
Thus, the DSP is seen by the user as a standard
16 - bit real or complex machine or a 32 - bit real
machine. All operating units and working registers
are automatically adjusted by the processor to the
right length. In real mode, all instructions are executed in a single machine cycle. In complex and
double precision mode, the instruction time is doubled.
In all modes, the number representation used is signed 2's complement.
3.2.1.16/32 - Bit ALUIAccumulator (fig. 2). The
ALU can be seen eith er as a 16 or 32 - bit ALU. The
ALU is loaded on the right side by the R - bus or by
the A or B accumulators.
On the left side, the operands always access the
ALU through the barrel shifter, coming either for the
L (left) - bus or the hardware multiplier output register P.
The result of an ALU operation is automatically written in the D register and, if required into the Accumulator or FIFO. The ALU provides a range of 30
codes for operations which execute in a single machine cycle. They include arithmetic and logic operations, shift and rotate operations.
3.2.2. Barrel Shifter. The 16 - bit barrel shifter located on the left side of the ALU performs all logic/arithmetic shifts and rotations. It is used for normalization and formatting of data in floating point
operations and bit or byte manipulations. Two types
of operations are allowed in the barrel shifter.
_ Operations defined by ALU codes (shifts of 1 or
8 bits) see 3.8.2
_ Operations defined by specific dedicated instructions:
ASR (0 -715) arithmetic shift right by N (0 < N ~ 15)
LSR (0
-7
15) logical shift right by N (0 < N ~ 15)
LSL (0 -7 15) logical shift left by N (0
~
N ~ 15)
ROR(O -715) rotation right by N (0 < N ~ 15)
In complex mode, the barrel shifter performs the
same operations on complex and imaginary part.
3.2.3. Multiplier. The multiplier executes a 16 x 16bit multiplication with a 32-bit result at each machine
cycle. The operands are loaded into the M and N registers and the result of a previous multiplication is
written in the P register during the same cycle.
The pipeline structure makes the multiplication result available with a delay of two instruction cycles.
The multiplier provides a multiplier overflow flag
OVFM which is memorized in the status register in
complex mode only (see 3.2.4).
The efficiency of the parallel pipeline operation of
the multiplier is shown in fig. 3.
9/66
561
ST18930/31
Figure 2 : Alu Block Diagram,
L-BUS
R·BUS
• 4 Inputs
giving access to 10 possible sources;
XRAM, YRAM,CROM, ERAM,
P, T, RIN, A, B, FIFO
• 5 Destinations; A, B, D, FIFO, Z BUS
• R side by Accumulators
L side by T registers
• 30 operations; including Arithmetic,
Logic, Shifts,
With 3 modes of execution;
Real
Complex
Double precision
• Saturation mode to prevent overflow
• The status register gives information
on the results of operations,
• The Replace Code Register allows dynamically
changing the ALU operation code with a data,
MULT
The ALU formats are; 16-bit in Real mode
16 + 16-bit in Complex mode
32-bit in Double Precision mode
M88ST18930-03
Figure 3: Multiplier Efficiency,
L-BUS
R-BUS
11
~~
MIN
Multiplier
Jl
~
X
~
y
---..9.L
C
X2
X1
R
R
A
C2
C1
R
0
xo
M
Y2
Y1
YO
M
co
M
A
BSIALU
II
Z-BUS
_X",O,---~.!'X,,-1_----'X"'2~r -
~C",O,--_C"-1,--_,,,C2'--+i -
If --~
If --~
_",PO'----;--"P-'-1--;..---"P2,,----.;.: -
-If _~
If- -~
e----'Y"-O--+---'Y-'-1-----<\_Y"'2'-+1 5
I
I
I
6
7
8
All components are always busy
10/66
562
X (instruction number)
M88ST18930-04
ST18930/31
3.2.4. Associated registers.
Status register (STA).
Registers A, B.
This register provides a status of the ALU, operating
and addressing modes, and multiplier. It is divided
into two sub-registers:
A and B store the results from the ALU. They are sized according to the mode of operation. They also
provide capability to feedback the ALU for a new
operation with the ALU result of a previous operation.
CCR (Condition Code Register)
STR (State Register)
A detailed description of this register is given in
Register FIFO.
Ii 5.4.
The 4 x 16-bit FI FO is used for intermediate storages.lnitialization of the FIFO (empty FIFO) can be
made by an INI instruction.
Transfer register T.
A result loaded in FIFO at instruction N is available
at least at instruction N+2 in real mode and N+ 1 in
complex and double precision modes.
Register RC (Replace Code register).
This register can dynamically load an ALU code to
be executed by the processor from the data memories.
This register is 6-bit wide and is loaded by the 6 MSB
of L-bus :
_5~__~~__~__~0~[
RC
L[
The transfer register provides a direct transfer capability between L-bus and Z-bus.
It can either be source or destination for the two
buses.
Its various uses include:
* Loop back to the multiplier in one cycle
* Temporary register between memory and ALU
* Temporary register between memory and multi-
plier
* Operation between two accumulators in the same
instruction
L-BUS
[15
14
13
12
11
10
I-BUS
17
18
19
20
21
22
* Memory to memory transfer
* Saving program counter (in a branch instruction)
Bit 1 to 5 contain the executable ALU code corresponding to the bits 121-117. Bit 0 allows the choice
of ALU output destination (A or B register).
Its contents is defined by three ALU codes: (see 5.2.)
ALU
Code
Function
RCR
Load ALU control code in register RC
RCE
Execute ALU code contained in register RC
RCER
Execute ALU code contained in RC and
load new ALU code in RC
11/66
563
ST18930/31
The status register content can be saved using instruction SVR.
The condition code register CCR can be read in
OPIN instruction and it can be loaded via L-bus (ALU
code LCCR).
The state register STR can be programmed by an
INI instruction or an SVR instruction (except EF bit).
Register D.
This is an intermediate register which is loaded with
ALU result at each machine cycle.
3.3. DATA MEMORY BLOCKS.
3.3.1. Available spaces. The ST18930/31 provides
four separated memory spaces (see fig. 4)
· two internal RAMs of respectively 192 x 16-bit
(XRAM) and 128 x 16-bit (YRAM)
· one internal data ROM (independent from the program ROM) of 512 x 16-bit (CROM) (ST18930 only)
· one optional external memory (ERAM) of 4 K x
16-bit accessible in 1 single instruction cycle in
exactly the same way as internal memories.
This external memory is controlled by an Intel or Motorola type control interface and offers full speed, fully transparent, Read and Write operations.
However slower external memories or peripherals
can be accessed by using slow exchanges mode.
The powerful instruction set and the Harvard architecture allows many combinations of simultaneous
memory accesses. The only forbidden situations
are:
_ read and write access is the same RAM within the
same instruction
_ simultaneous access to CROM and ERAM
3.3.2. Address Calculation Units. Three different
Addresses Calculation Units are available.
XACU is associated with XRAM
YACU is associated with YRAM
3.3.3. Addressing modes. The ST18930/31 provides four addressing modes:
_ Direct addressing
_ Immediate operand
_ Indirect addressing with or without post modification of the pointers
_ Circular addressing (also called virtual shift
mode) for XACU and VACUo
The circular addressing mode is of particular interest in digital signal processing typical operations
like convolution algorithms used in FIR filters. It has
the same function as a shift register but does not
move the data stored.
For this feature, three pointers are used in the memory space chosen (X or V). The current address is
given by a specific X pointer shifting repetitively between two limits XO and X1 (respectively Y, YO and
Y1).
The circular mode is declared in the status register
STA (see 3.2.4) by an INI instruction.
3.3.4. Pointers. The ST18930/31 offers a large
number of address pointers for each memory space
_ XO,
_ YO,
_ CO,
_ EO,
X1
Y1
C1
E1
and X for XRAM
and Y for YRAM
for CROM
for ERAM
The pointers Xi, Vi, Ci and Ei can be independently
incremented, decremented or maintained. The two
pointers X and Yare specific to the circular addressing mode. The pointers can be loaded with new addresses (constant or computed values) through Zbus. In this case, the value of unused Z-bus MSBs
are irrelevant. The unused bits are set to 1.
3.3.5 Odd/Even addresses. In complex and double precision modes, the processor automatically
generates the two addresses necessary to store
one data word (even first, then odd addresses).
The user can reverse this order by setting to 1 the
ADOF bit with the INI instruction (referto OPCODE).
This feature is available independently for XRAM
and YRAM.
ECACU is associated with the ERAM and the
CROM
COMPLEX WORD
DOUBLE PR. WORD
Even Address
Real Part
Lower Part
Odd Address
Imaginary Part
Upper Part
12/66
564
ST18930/31
Figure 4 : Data Memory Blocks.
full speed, and
fully transparent
read and write
operations
M88ST18930·05
3.4. SEQUENCER BLOCKS
Z
Zero
3.4.1. Sequencer. The purpose of the sequencer is
to generate the next instruction address. .
OVF
Overflow
The sequencer takes into account the current operating mode of the ST18930/31 to execute this task.
The instruction is executed in one cycle time in real
mode and two cycles time in complex or double precision mode.
The linear address program generation may be interrupted by several means hereunder described.
A. Execution of a branch instruction
_ unconditional branch always.
_ seven ALU conditions flagged from the status
register:
SR
Sign real
SI
Sign Imaginary
CR
Carry Real
CI
Carry Imaginary
MOVF Memorized overflow MOVF
is reset when tested by
branch instruction.
_ three external conditions on state of pins BSO,
BS1, BS2 (the pins BSO, BS1, BS2 can also
be used as interrupt pins if enable interrupt is
programmed).
_ four edge sensitive external conditions on pins
BE3, BE4, BE5, BE6. The falling edges of
BE3-BE6 are memorized internally and reset
when tested by the branch instruction. The external test conditions are used to synchronize
different processes.
_ The mailbox flag RDYOIN indicating mailbox
availability.
All the branch conditions can be tested on true or
false conditions.
13/66
565
ST18930/31
B. Subroutine call
C. Loop execution
One of the most powerful features of the
ST18930/31 is its ability to repeat the execution
of several instructions with very straightforward
commands. The loop execution is set with the
instructions: REPEAT, BEGIN, END which respectively define the number of loops, the beginning of loop and its end. The DSP will then manage all the necessary pointers to execute the
loop with no overhead time (see 3.4.4.).
D. Execution of an interrupt routine
When the Enable Interrupt bit (EI) of the status
register (STA) is set, a low level on any of ITO,
IT1 and IT2 inputs forces the PC content at
$ 0001. Mailbox interrupts can be enabled separately from IT inputs interrupt; it occurs when
a mailbox exchange has been completed (see
& 3.5.6). During interrupt routines execution,
the program counter is saved in the Return Address Stack (RAS).
3.4.2. Instruction ROM. The ST18930 instruction
ROM has a capacity of 3072 words of 32-bit available for the user. The ROM code is defined following
the user's information (see appendix C for masking
information). The ST18931 does not provide an onchip ROM memory, but can address an external
64 K program memory space in a single cycle.
3.4.3. Program Counter. The program counter is a
16-bit wide Register ; 12 bits are used in the
ST18930 (ROM version).
12
11
3.4.4. Loop Counter. The loop counter does considerably increase the efficiency of the processor in
repeated calculations, very commonly used in digital signal processing.
Three counters define a hardware loop:
_ LCI Instruction Loop Counter (4-bit). Counts the
number of instructions to be executed in the loop.
_ LCR Repeat Loop Counter (8-bit). Gives the number of times the loop will be repeated (can be loaded by a calculated value).
_ LCD Delay Loop Counter (3-bit). Gives the delay
between the declaration and the start of a loop.
The loop counter content can be saved (SVR instruction) with the format shown in table below:
The loop counter is set by the three pseudo-instructions Begin, Repeat and End in the Macroassembier.
The loop counter is frozen during an interrupt routine.
On the ST18931, a HALT freezes the state of the
loop counter. A RESET signal resets the loop counter.
3.4.5. Return Address Stack. The JSR instruction
allows one level of subroutine nesting with automatic saving of the PC on to the Return Address Stack.
Multiple Level of subroutine nesting can beimplemented in RAM using either of the two pointers as
stack pointer.
10
Lei
LCD
LeR
LOOP
COUNTER
14
13
12
11
10
M88ST18930-06
14/66
566
ST18930/31
3.5. INPUTS/OUTPUTS
A very important feature of a signal processor is its
ability to be inserted in a complete system including
memories, other processes, analog interface circuits.
To interface with a host, the ST18930/31 uses its
system bus and interrupt/branch capabilities.
However, the local and system bus configuration is
flexible and allows many combinations for the architecture of a system based around a ST18930/31 .
3.5.1. Interrupt branches. Several sources of inter-
Basically, the external world seen by a ST18930/31
can be divided in two main sections: communications with its own local resources (peripheral, memories, converters) and communications with
control processor, either microcontroller or master
DSP in a multiprocessor application.
rupt and branch conditions are accepted by the
ST18930/31. Depending on the initialization (INI)
the ST18930/31 can accept interrupts from pins,
ITO, IT1, IT2. It can also and independently accept
software interrupts transmitted through the mailbox.
To communicate with its local resources, the
ST18930/31 uses its local bus.
The various sources/conditions of interrupts are
summarized in fig. 5 :
Figure 5 : Interrupt Inputs and Conditions.
Access
Mode
Register
EIMBbit
Interrupt
Routine
(~--------r-~----------------IT2
------~--+--+----------------m
---.--+--+--+----------------ITO
Status
Register
Branch conditions
Bit EI
M88ST18930·06
15/66
567
ST18930/31
3.5.2. Dual bus interface. In order to provide the
maximum flexibility, the 8T18930/31 provides two
buses. One is called the system bus and is found on
pins ADO-AD?, the other one called local bus is situated on pins DO-DI5. The system bus provides a
very straightforward interface to a host controlier,
while the local bus allows the 8T18930/31 to make
an efficient use of external resources such as memories, analog interface circuits etc ... This dual bus
structure allows many combinations of circuits
where the 8T18930/31 can act in different ways:
Fig. 6B as a processor with its associated memory
Fig. 6C as an intelligent peripheral having its own
extemal memory and connected to a microprocessor.
It must be emphasized that, in most configurations,
the connections are absolutely direct and do not use
any external additional logic.
Fig. 6A as a microprocessor peripheral
Furthermore, thanks to the dual bus structure, several 8T18930/31 can be very simply combined together in multiprocessor applications, thereby directly increasing the processing power.
Figure 6 A : H08T/8T18930.
Figure 6 B : 8T18930/RAM.
00-07
ADO·AD?
DATA
DO-D15
DATA
8
--
CS.RS
or SRD,SR/W or SWR
80S
ST18930
ST18930
16
4Kx16
os or R5 R/W or WR
RAM
HOST
ST18930
SYSTEM BUS
HOST
(FULL MASTER)
A8-A11
ADO-AD?
IRQ.DTACK.BA
LOCAL BUS
(SLAVE)
ST18930
RAM
M88ST18930-07
M88ST18930-08
Figure 6 C : H08T/8T18930/RAM.
SA
.--L-
¢
~
00-07
ADO"AD7
HOST
8
~
16
DATA
8T18930
OS or RD,RIW or WR
RAM
5DS or SRD,SR/W or SWR,CS,RS
AS·All
IRQ,DTACK
~
~
HOST
(TEMPORARY MASTER)
SYSTEM BUS
5T18930
(PSEUDO SLAVE)
ADO-AD?
~
I
LOCAL BUS
8T18930
RAM
M88ST18930-09
3.5.3. Host/slave configuration. The processor
acts as a host on its local bus and as a slave on its
system bus.
In configurations in which the 8T18930 accesses
external RAM8 on its local bus, pins ADO-AD? can
be used to provide 8 L8B addresses, while A8-A11
provides 4 M8B addresses to the RAM.
In this case, the 8T18930/31 prevents the host from
using the system bus and is then called a pseudoslave.
16/66
568
8ince the host can only temporarily access the system bus it is defined as a temporary master. That
mode of operation is software controlled through the
Access Mode Register (AMR) (see 3.5.?).
On the 8T18931 the pins CAO-CA?, which present
the least significant bits of external ERAM/CROM
addresses can be connected to that RAM in place
of system bus pins ADO-AD?
ST18930/31
3.5.4. Local bus. The local bus uses two software
programmable signals to control the data on 00015.
OS : Data Strobe. Synchronizes the transfer on local bus.
RD : Read. Read clock pulse.
WR : Write. Write clock pulse.
These signals are used for Intel-like bus compatibility.
RlW : Read/Write. Indicates the direction of the data.
A8-A11 : Address bits (4)
These signals are used for Motorola-like bus compatibility.
ADO-AD7 : Optional additional address bits (8)
Figure 7 : Local Bus Pin Description.
1-----
00·0?
1------
08·015
J
f----
A8·A11
]
16 bi1 data bus can be concatenated or separate
ST18930
4 address bits
f - - - - 58 or REi
J
f----
]
f - - - - RNV or WR
Control bits. Can be chosen among 2 sets
AOO·AO?
Additional adress bits (in pseudo-slave mode)
M88ST18930-10
The four address bits of the local bus are usually
sufficient to address peripherals. When an access
to external RAM is necessary with the ST18930/31 ,
the address bus can then be extended by using the
ADO-AD7 pins of the system bus as address lines.
If an external peripheral or external memories are
too slow to answer in one machine cycle, the
ST18930/31 can be programmed to execute an external access in several cycles (2, 3 or 4) using the
bits ESO and ES1 of Access Mode Register (see
3.5.7.).
This mode is particularly useful for peripherals such
as data converters, or dedicated interface like the
MAFE chip set (Modem Analog Front End) from
SGS-THOMSON.
The local data bus can also be splitted into two independent 8-bit buses. This is used in a multiprocessor architecture when a pseudo-slave uses the
system bus to transfer its own RAM addresses on
00-07 (fig. 8). By dividing its local bus, the temporary master can remain a full-master on bus 08-015
and does not require a bus transceiver on DO-D7.
The selection between the two buses is then made
by the addresses A1 0-A11 as indicated in Fig. 8.
Figure 8 : Separate Local Buses.
08-015
ST18930
MASTER
ADO-AD7
f
"-----r
O D7
'
•8
~
L.. ,-------ST18930
PSEUDO
SLAVE
I--DATA
M88ST18930-11
17/66
569
ST18930/31
3.5.5. System Bus: The system bus uses two software programmable signals to control the data on
ADO-AD?
The system bus mode of operation (Intel or Motorola) is set by asserting the SIM Flag using an INI instruction).
SRIW and SDS signals are used for Motorola-like
bus compatibility.
SWR and SRD signals are used for Intel-like compatibility.
CSIRS
Mailbox control signal. Also used by a host to gain access to the bus.
SRIW or SWR
SDS or SRD
System ReadlWrite
System Data Strobe
IRQ
Handshake Signal (see 3.5.6)
DTACK
Data Transfer Acknowledge. Compatibility with 68000 family. Is programmed by Access
Mode Register.
BA
Bus Available. The ST18930/31 is not currently using the system data bus to generate
addresses. BA is also programmable by the Access Mode Register.
l
Generated by an external processor (host)
Figure 9 : System Bus Description.
8 bit data bus
cs
Control pins
Can be chosen
among 2 sets
RS
SR/W or SWR
ST18930
SDS or SRD
DTACK
[ SA
IRQ
M88ST1893D·12
3.5.6. Mailbox. The mailbox is a set of registers
which interface with the system data bus. The mailbox is divided in two parts:
_ RIN (3 x 8 bit register) : This register is read internally by the ST18930/31 on the upper byte of Lbus (L8-L 15) and written externally from the system bus. After each write or read operation the
data is shifted by one byte.
_ ROUT (3 x 8 bit register) : This register is written
intemally with the upper byte of the Z-bus (Z8Z15) and read externally on the system bus. After each operation (read or write), the data is shifted by one byte.
b.
IRQ.
Handshake signal enabling the host to gain access
to the mailbox.
a.
IRQ is asserted low by the DSP to indicate the
availability of the mailbox (at the same time as
RDYOIN).
b.
The host after testing IRQ, knows that it can access the mailbox. The access to the bus (which
can be currently used by the DSP as a local address bus) must be requested by reading the
address CS = 0, RS = O.
c.
The DSP then answers back by asserting IRQ
high. (In pseudo-slave mode, the DSP is halted). The host now has full control of the bus
and mailbox.
protocol signal description.
RDYOIN.
Intemal flag indicating the status of the mailbox
o = DSP has access to the mailbox
1 = host has access to the mailbox
a.
RDYOIN is set by the DSP and reset by the host.
That means that the DSP gives the mailbox to
the host when it finishes using it and vice-versa. In no case can the host or the DSP take possession of the mailbox, it can only wait for the
other to give it back.
18/66
5?0
The ST18930/31 sees RDYOIN as a flag:
_ tested by a branch instruction
_ set to 1 by an initialization instruction in order
to give the availability of the mailbox to the
host.
When the host has completed the exchange it
generates the address CS = 0, RS = 1 and the
DSP resets RDYOIN.
ST18930/31
HALT (internal).
The internal halt has the following effect on the circuit:
_ the prograrn is stopped at the end of the current instruction, the program and loop counter are frozen
_ a NOP is executed
_ no more addresses are generated on the system
bus
MAILBOX INTERRUPT.
Enabled by initializing the bit EIMB of Access Mode
Register (AMR). When RDYOIN is reset, the PC is
forced to address $ 0001.
Refer to figures 11.A and 11 B for timing detail of
mailbox protocol.
Figure 10 : Mailbox Connection and Protocol.
D O " D 1 5 i - - - - - - - - - - - - - j ADO-AD?
~L.BUS
1
RNi I - - - - - - - - - - - - - . j SRIWorSWR
D : O S 3 1 - - - - - - - - - - j ;SIDsDS orSRD
A81----------~~CS
RIN
ROUT
f-
Z-BUS
MAILBOX
A91-----------IRsRS
example
SSO I - - - - - - - - - - I = I R Q
5T 18930
ST18930
SLAVE
HOST
M88ST18930·13
sns RDYOIN, IMPLIES IRQ = 0
MAILBOX IS AVAILABLE TO HOST
I
DetectsIRQ=O
one of its external test conditions
!
Applies CS '" 0, RS", 0
I
detects
..
Cs=O,Rs=o
II pseudo-slave [The processor is put in Halt state
and releases the system bus
Asserts IRQ high
I
DetectsiRQ_l
MAn.BOX ACCESS
(3 reads and 3 writes maximum)
END OF MAILBOX ACCESS
Applies CS =0, RS = 1
I
detects
~
CS",O,Rs='
+
Internal Hall Disppears The processor
If pseudo-slave [
resumes program and
takes back control of the bus
~
ClearsRDYOIN
Mallbox IS aVailable to ltJe SLAVI:;
This protocol is hardwired on the slave side and programmed on the host side. The mailbox is included
in the slave. The two slave address pins (CS, RS)
are directly connected to two host address lines.
Therefore, the slave is seen as two external memory locations by the host which will address it by ge-
M88ST18930·14
nerating an external address directly or indirectly
(pointer EOor E1).
fuulddressing the location 00 the host echoes the
IRQ to the slave and accesses the mailbox.
By addressing the location 01 the host releases the
bus.
19/66
571
ST18930/31
Figure 11.A : ST18930/31 Mailbox Exchange, Slave Mode.
rc --j
(Machine cycle clock)
~~;-fULfYfl--I1--I~
,
I
I
I
,
I
,
-'----,/~~~~
-cs
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
_~/f--,~~~L-J~M
,. L-J~I
,/
AS
/,
_ _ _ _"-~I /
":
I
I
I
/ !:: ::
:
7I
SRW
:
7I
:
I
I
I
,
I
I
::
I
j
I
I
If-Lj: I ' j.1-----~---~
I
I
,
/~:~:LJ~~
" : UrL---!~:
:"
-------'------,/~:
j
~j:
: ~:
: ~:
:
sos
I
I
DTACK
/
' :
I
: :
mailbox
ready
I
I
I
:
I
:
2 machines cycles
:
,
+ 2 instruction cycles
,
,
,
I
I
I
I
-
I
:
I
I
I
I
,
end of
mailbox exchange
mailbox
request
exchal1ge
r---~---,//j.I-------I//
~~/j.-------~/
'I
.l;-J
-B-A-.,----~/~j.I--------~7~j.I--------,/~j.I-----~/~jl----~-----
,--/1j.1_ _ _ _ _ _ _~//j.I_ _ _ _ _----,/I/-I_ _ _ _---j/I/-I_ _ _~
I,
' - - -_ _ __
(internal signal)
------------------~(
ADO-AD?
DATA OUT
H
slave executes programs with no internal halt during mailbox
exchanges but never has of AD bus for local addresses
M88ST18930-15
• Up to three consecutive read/write operations may take place.
20/66
572
ST18930/31
Figure 11.8 : ST18930/31 Mailbox Exchange, Pseudo Slave Mode.
/~~~~
CS
,
RS
SRW
,
,
,
'
I
I
I
I
I
I
I
-=--'c--i/~:
~:
:~:
:
~:
:
sos
/
:
I
I
I
I
I
: :
I
I :
I
I
I
~D=TA=C=K-~--!/~
~~
~;-l,U r--I~
~
,
:u:
",
U"
"
:u:
:
"
,-:_
~
mailbox
mailbox
ready
request
--:
'
mailbox exchange
end of
exchange
I '
I'-------j/;-I------_(//-/------~-~
'---(/1----------1/~
, I"------j/~I-/-------(J~I-/----,
-B-A----,//I-I---------I/~
L-_~_ _
-- _____-II!-_;--____-(I!-______-!I!-___-,
~!I
II
JI
II
AOYOIN
L - _ , - -_ _
(internal signal)
~t==x==x==7Lj-<
----:
local bus addresses
DATA OUT
>-I L<:JD~AI!TA\lI;;:N:::>---------~
~~::::I ~~~t exchanges ~___________
Iba
M88ST18930-16
21/66
573
ST18930/31
3.5.7. Access Mode Register (AMR). The AMR is
a 9-bit register which defines the processor external
access modes.
18
19
17
16
It is loaded by an INI or SVR instruction and saved
by an SVR instruction. Its fields are defined as follows:
15
14
13
12
I-BUS
Z-BUS
Bits a and 7 - SEa, SE1 .
Bit 3 : I ntel/Motorola type local bus
These two bits define the number of cycles fixed by
the user to access external resources. If the user defines a multicycle exchange (i.e. for access to slow
memories), internal wait states are automatically inserted allowing the processor to wait for the completion of the external exchanges. The instruction executes once with the number of cycles chosen by the
programmer.
a = Control pulses Read (RD) and Write (WR) are
generated. This is the case with an Intel type peripheral or a standard byte-wide RAM.
1 =~ontrol pulses data strobe (OS) and Read/Write
(R/W) are generated.
Multicycles exchanges can be programmed in any
operating mode (real, complex or double precision).
SE1 SED
Number of machine cycles
for external access
a
a
a
1
1
2
1
a
3
1
1
4
Bit 1 : SUPS.
a = Slave.
1 = Pseudo-slave.
This bit defines the behaviour of the ST18930/31 regarding the system bus (ADO-AD7). In slave mode,
the processor will never use the system bus as local bus address.
In pseudo-slave, the processor uses address bus
(ADO-AD7) for local resources. These bits are concatenated with A8-A 11 to form a 12-bit address bus.
Bit 2 : SB/CB.
a = Separated bus.
1 = Concatenated bus.
This bit indicates whether the local bus is used as a
16-bit concatenated bus or as 2 independent 8-bit
buses.
(see 3.5,40 - local bus description).
22/66
574
This is the case for exchanges with a slave processor, a Motorola type peripheral, a data converter
such as the TS7542 or the MAF.E. chip set
(TS68950/51 /52).
Bit 4 : DTACKlBE6.
a = DTACK function. The ST18930/31 does acknowledge correct access by generation of a
DTACK output.
1 = BE6. An external test condition is available on
pin BE6.
Bit 5 : BAlBE5.
a = Configurates the pin (BA)5 as bus available output indicating the availability of the system bus.
1 = Pin BE5 is used for external test conditions.
Bit 6: MASK (ST18931 only).
a = An external Halt applied to the processor will not
change the values in the AMR register.
1 = During external Halt applied to the processor the
AMR register is forced to following configuration:
one QITle exchange, pseudo-slave, concatenated
bus, RD and WR control pulses.
This bit can be modified by the programmer even
while the HALT is asserted.
Bit 8: EIMB.
Enables interrupt rnailbox. When set to 1, this bit validates the start of an interrupt when RDYOIN internal flag goes low.
This bit is programmed with an INI instruction.
ST18930/31
3.5.8. Instruction interface and system control
(5T18931 only). On the 8T18931, the coefficient
ROM and the instruction ROM (CROM & IROM) are
external. The device provides the necessary buses
to access these data. Instructions are read on 100 :
1031 using IAO-IA15 for addressing. Coefficients are
read on local address bus 00-015 using CAO-CA8
for addressing. CA9 is at low level for address validation. CAO-CA7 also contains external RAM addresses (if necessary) associated with a high level
forCA9.
80, for the 8T18931, there is no need of a pseudo
slave mode as AOO-A07 remain available for data
transfer on the system bus. Clock signals are also
provided for interfacinQ..J2illQ9ses (3.6.1.). Controls
signals on C80L and C80H indicates data transfers on 00-07 and 08-015 respectively when at a
low level. A NOP control input is also provided on
8T18931 to allow hardware simplification of development systems. This input forces a NOP instruction when low and forces all addresses in high impedance state.
TAL period and the value of CRR register programmed by INI instruction.
CRR (3; 0)
CLKOUT/EXTAL RATIO
1
2
2
3
....
....
15
16
The INCYCLE output is equal to instruction cycle.
The MC output period is equal to half of EXTAL period.
3.6. OTHER RE80URCE8
3.6.2. Reset. The reset signal acts on several processors blocks as follows :
_ 8equencer: the program counter (PC) and
the loop counter (LC) are cleared to zero. The
instruction register is loaded with NOP instruction.
8tatus register: set in real mode, no saturation, empty FIFO (EF = 1), overflows (MOVF =
AOVF = OVFM = 0), interrupt disabled
(EI = 0), and XRAM and YRAM in non circular addressing mode.
Access Mode Register (AMR): set for one cycle externa~chan~slave mode, concatenated bus, RO and WR, BE5 and BE6.
Motorola mode is set on system bus.
Mailbox control is disabled.
3.6.1. Clock generators. Three different clock outputs are available on the 8T18931 and one on the
8T18930.
The reset signal must be maintained for a minimum
of 16 cycles of EXTAL signal (see fig. 12 fortiming).
If machine cycle = EXTAL.,. 2.
3.5.9. Halt (5T18931 only). The external HALT signal will freeze the program counter, the loop counter and the multiplier. The instruction register can
then be loaded from an external source. This signal
is used for system development.
CLKOUT : available on 8T18930 and 8T18931.
INCYCLE and MC (master clock) : available on
8T18931 only.
The internal processor cycle is equal to the frequency of the EXTAL input divided by 2 or 4. The choice
of the dividing factor is done by option at the masking level for the 8T18930 and by control of CC input on the 8T18931. If CC = 1 then the dividing factor is 2, if CC = 0 it becomes 4 for T868930/31 compatibility.
3.6.3. Watchdog capability (8T18930 only). The
watchdog prevents the processor from staying
locked in an undesired state or internal loop caused
by adverse conditions. The circuitry does include a
2-bit counter which is incremented by each falling
edge on BE3 input and reset by software testing of
the BE3 condition. If three falling edges of BE3 input occurs without a test of the condition, the
8T18930 is reset by the watchdog circuit. This capability is a mask option of the 8T18930.
The CLKOUT output period is function of the EX-
23/66
575
ST18930/31
Figure 12 : Reset Timing.
.,
16 EXTAL cycles
:---
elk generator reset
.: .
internal register initialization
-----:
,
,
~
EXTAL
L-----------------------~------------~7~~/----------------
---------~~
machine cycle clock correspond at
mask programmed EXTAL!2 or CC=1
,
,
Ie
machine cycle
M88ST18930·17
3.6.4. Low power mode. The low power mode
freezes the circuit operation and divide by 16 the internal clock generator frequency (see masking options).
In this mode, the DSP will use typically less than
5mA.
For the ST18930 in 48 pin package, the BS2 pin can
be configurated by a mask option as a low power
mode input pin. In this case, if the bit EI of the status register is set to 1, BS2 pin will work as low power control pin, and
If EI = 0, BS2 will work as a branch condition pin.
_ Software mode :
The access to this mode can be done by software
or hardware.
_ Hardware mode:
The low power mode is activated by an INI instruction.
On the ST18931 and the ST18930 in PLCC 52
package the LP pin forces the low power mode.
The return from low power mode is obtained with a
reset or an interrupt.
24/66
576
ST18930/31
4. TYPICAL APPLICATION CONFIGURATIONS
Figure 13: Configuration Example with ST18930 + RAM + MAFE*.
l
I
BE6
BE5
08-015
r
00-07
r
~
~
V
RXGGJ
00-07
TxGG
~
-RAI
~
MAFE
ST18930
A11
A10
A9
A8
-
"-
r--
-
OS Dr R5 -
R!w orWR -
-
~
'---
'---
~
AOO-A07
,('>.
~AT
GS1
GSO
RSO
RS1
~
8
GS
EO
RIW
OE
WE
o
V
00-015
~
Towards
general purpose
microprocessor
8
-V
3
8
~
11
V
AO-A10
RAM
2K
x 16
(2 x 2K x 8)
Al1
A10
Ag
As
1
0
0
X
X
X
X
X
MAFE
RAM
• MAFE is the TS68950/51/52 Modem Analog Front - End Chip Set.
M88ST18930-18
25/66
577
ST18930/31
Figure 14 : Configuration Example: 3 8T18930 + RAM.
j
BSO
I
I
BSI
IRQ
08"015
00-07
ST18930
A8-All
i-----V
ADO-AD?
~
ST18930
~l
2
-
CS,RS
ADO-AD?
">
Towards
general purpose
microprocessor
58 or RD
RiW or WR
A9-Al1
(I)
§5S or SR/W
2
2
~
SOS or SRIW
~
r-------v
IRQ
r---
ADO-AD7
CS,RS
AS-A1l
ST18930
121
~.----~-RAM1Kx16
~
08-015
00-07
ADO-AD?
AO-A9
AIO
-V
AO-A9
OS DE
1
All
Al0
Ag
0
1
0/1
1
ST18930 (1)
0
1
1
0/1
ST18930 (2)
1
0
X
X
RAM
WE
_J
As
M88ST18930·19
26/66
S78
ST18930/31
Figure 15: Configuration Example 4 8T18930 + MAFE + RAM.
,eo i - - - - - - - - - - - - - j T ' C C
ST18930
BSO
BSI
BS2
"Q
I
~
ADO·AD?
,
ST18930
(2)
CS,RS
AI',A6
,
'"
SRIW
"iAci
'--------j -
T
-
"00-015
ADD-AD?
V
~
ST18930
CS,RS
(3)
AI1.AID
,
SDSorSR!W
If
AS-All
,
)------
.::J
A8-A"~
1
_ _ _ _ _~/
AD-A?
00·015
K,,----"
"M
~".~'"
All
Al o
Ag
1
0
X
As
X
MAFE
0
1
0/1
1
ST18930 (1)
0
1
1
0/1
ST18930 (2)
0
0/1
1
1
ST18930 (3)
M88ST18930-20
27/66
579
ST18930/31
Figure 16: Interfacing CRaM, IROM to 8T18931.
local bus A8-A 11
V/~---D--b-US--DO--D-15--------~'
I~~--~
TO OTHER
PERIPHERALS
16
CA9
(OECROM)
CROM
ERAM
512x16
1L
COEFFICIENT ADDRESS BUS
(also used for local bus addresses)
I /1'--------_ _ _ _---,
ST18931
V "
~
INSTRUCTION DATA BUS
,,------------1
I '-J
IDO·ID31
INSTRUCTION
ROM
IROM
(64KX32)
INSTRUCTION ADDRESS BUS
IAO-IA15
M88ST18930-21
28/66
580
ST18930/31
5. INSTRUCTION SET
Number of Cycles
Symbol
Type
Operation
REAL
CPLX
OBPR
OPIN
Calculation Instruction with Indirect
Addressing
This instruction refers to operands
indirectly addressed.
1
2
OPDI
Calculation Instruction with Direct
Addressing
The operand sourcing the L-BUS is
directly addressed.
1
2
OPIM
Calculation Instruction with Immediate An immediate operand is read on
R-BUS.
Operand
1
2
ASR
ASL
LSR
ROR
General Shift Instruction
The operand sourcing the L-BUS can
be shifted/rotated by a -> 15 bits.
1
2
BRI
Immediat Branch Instruction
Conditional/unconditionnal branch to
direct address.
2
2
BRC
Computed Branch Instruction
Conditional/unconditional branch to
computed address.
2
2
SVR
TFR
Data Transfer Instruction
This instruction is used to save
register contents in external or
internal RAM.
1
2
INI
Initialization and Control Instruction
Pointers, acces mode register, loop
counter, mode initialization, interrupts.
1
2
29/66
581
ST18930/31
INSTRUCTION SET LANGUAGE DEFINITIONS.
LDT
R SRC
LSRC
Load L-BUS source into Transfer Register T
R-BUS Source
L-BUS Source
SL
ALU Input Selection Left Side
SR
ALU Input Selection Right Side
ALU DST
ALU CODE
ALU Output Destination
ALU Codes
LDM
Load L-BUS Source into Multiplier Input M
LDN
Load R-BUS Source into Multiplier Input N
ZSRC
Z-BUS SOURCE
Z DST
Z-BUS DESTINATION
ZT
ACE
AY
AX
BRA
FT
Load Z-BUS into Transfer Register T
Post Incrementation Pointers CROM or ERAM
Post Incrementation Pointers YRAM
Post Incrementation Pointers XRAM
Branch Address Sou rce
False/True Condition
SVPC
Save Program Counter
JDST
Destination Register for J Constant
KDST
Destination Register for K Constant
MODE
Operating Mode
SAT
Saturation Flag
ADOF
Even/odd Flag
J Constant
8-bit Constant used to initialize registers
K Constant
12-bit constant used to initialize registers
30/66
582
Gi
:"fI SCiS·THOMSON
ffiIiln©I'iI@~~~©'ifIiil@OOn©@
ST18930/31
5.1 OPERATING CODE FORMATS
Fig. 17 : OPIN : Calculation Instruction with Indirect Addressing.
Bit
Field
31
30
OP CODE
00
29
LDT
a-NO LOAD, 1-LBUS
28
27
R SRC
00
[XO]
01
[EO]
10
[YO]
11
[Yl]
26
25
24
L SRC
000
[XO]
001
[XI]
010
[YO]
all
RIN
23
SL
O-LBUS I 1-P
22
SR
O-RBUS I I-AlB (refer to ALU DST)
21
20
19
18
17
ALU CODE
ct.
16
15
ALU DST
00
D
01
F
10
A
11
B
14
13
12
Z SRC
000
D
001
F
010
A
011
B
11
LDM
a-NO LOAD I I·LBUS
---7
M
10
LDN
a-NO LOAD I 1-RBUS
---7
N
ACE
00
+ a
01
+ 1
10
7
6
AY
00
+ a
01
+ 1
10
5
4
AX
00
+ a
01
+ 1
10
3
2
1
Z DST
a
ZT
9
8
Operations and Codes
---7
T
100
T
101
[El]
110
[CO]
111
[Cl]
101
CCR
110
111
-
-
101
[El]
110
[XO]
111
[XI]
Special Table
-
-
000
001 010
NONE ROUT [YO]
100
T
11
-1
11
-1
11
-1
011
[Yl]
a-NO LOAD I 1 ZBUS
---7
100
[EO]
T
31/66
583
ST18930/31
Fig. 18 : OPDI : Calculation Instruction with Direct Addressing.
Bit
Field
31
30
29
OP CODE
010
28
27
RSRC
00
[XO]
01
[EO]
10
[YO]
11
[Y1]
26
25
24
L SRC
000
X
001
010
Y
011
RIN
23
Z SRC
O-D / 1-F
22
SR
O-RBUS / 1-A
21
20
19
18
17
ALU CODE
d. Special Table
16
ALU DST
O-F / 1-A
15
14
13
12
11
10
9
8
7
6
5
4
Operations and Codes
-
100
T
101
E
110
-
111
C
MSB
LBUS
DIRECT
ADDRESS
LSB
3
2
0000 0010 0100
NONE ROUT [YO]
0110
[Y1]
1000
[EO]
1010
[E1]
1100
[XO]
1110
LCR
0101
YO
0111
Y1
1001
EO
1011
E1
1101
CO
1111
C1
Z DST
1
0
32/66
0001
XO
0011
X1
L.'1 SGS·ntOMSON
• Jj
584
fiIilBC~IIiI@lill1IC$
ST18930/31
Fig. 19 : OPIM : Calculation Instruction with Immediate Operand.
Operations and Codes
Bit
Field
31
30
29
28
27
OP CODE
01110
26
25
24
L SRC
000
[XO]
001
[X1]
010
[YO]
23
SL
O-LBUS / 1-P
22
SR
O-RBUS / 1-A
21
20
19
18
17
ALU CODE
ct.
16
ALU DST
O-F / 1-A
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
011
RIN
100
T
101
[E1]
110
[CO]
111
[C1]
Special Table
MSB
IMMEDIATE
VALUE
(R-BUS)
LSB
33/66
585
ST18930/31
Fig. 20 : ASR, LSL, LSR, ROR, Shift Instructions.
Bit
Field
31
30
29
28
27
OP CODE
26
25
24
LSRC
23
SL
O-LBUS / 1-P
22
21
ALU CODE
00
ASR
20
19
18
17
SHIFT
VALUE
0000 0001
0
1
16
ALU DST
O-F / 1-A
15
14
13
12
11
10
9
8
7
Operations and Codes
01111
000
001
X
-
MSB
LBUS
DIRECT
ADDRESS
6
5
4
3
2
1
0
34/66
586
LSB
01
LSL
010
y
011
RIN
100
T
101
E
110
-
111
C
10
11
LSR ROR
.....
.....
1111
15
NOTE: When LSR, ASR, ROR
shift value is complemented to 2.
ST18930/31
Fig. 21 : BRI : Branch Immediate Instruction.
Bit
Field
31
30
29
OP CODE
100
Operations and Codes
28
BRA
0·IR,1-RAS
27
FT
0-FALSE,1-TRUE
26
25
24
23
COND
CF Special Table
22
SVPC
O-NO SVPC, 1-PC
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
-7
RAS*
MSB
BRANCH
ADDRESS
LSB
5
4
AX
3
2
1
Z DST
a
ZT
00
+0
01
+ 1
000 001
NONE -
o NO LOAD,
10
-
11
-1
010
[YO]
011
[Y1]
1-ZBUS
-7
100
101
-
-
110
[XO]
111
[X1]
T
* The PC write operation in X or Y RAM (defined by Z DST) is realized if the branching is really executed.
35/66
587
ST18930/31
Fig. 22 : BRC : Branch Computed Instruction.
Bit
Field
31
30
29
28
Operations and Codes
OP CODE
1010
27
FT
O-FALSE, 1-TRUE
26
25
24
23
COND
CF Special Table
22
SVPC
O-NO SVPC, 1-PC --7 RAS'
RTI
O-NO RTI, 1-RAS
21
20
19
--7
PC
18
17
16
15
14
13
12
BRANCH
SOURCE
000 001
NONE F
010
A
011
B
01
+ 1
10
-
11
-1
010
[YO]
011
[Y1]
100
T
101
110
111
-
-
-
100
101
-
-
110
[XO]
111
[X1]
11
10
9
8
7
6
5
4
AX
3
2
1
Z DST
0
ZT
• See BRI.
36/66
588
00
+0
000 0001
NONE -
O-NO LOAD, 1-ZBUS
--7
T
ST18930/31
Fig. 23 : SVR : Data Transfer Instruction.
Bit
Field
31
30
29
28
27
26
Operations and Codes
OP CODE
011000
25
24
23
22
ZSRC
0000 0001 0010 0011 0100 0101 0110 0111
XO
X1
YO
Y1
EO
E1
CO
C1
1000 1001 1010 1011 1100 1101 1110 1111
AMR LC
A
F
D
STA
B
-
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
ZBUS
DIRECT
ADDRESS
3
2
1
Z DST
001 010 011
000
NONE ROUT Y AMR
0
ZT
O-NO LOAD, 1-ZBUS --t T
MSB
LSB
100
E
101
STR
110
X
111
-
37/66
589
ST18930/31
Fig. 24 : INI : Initialization and Control Instruction.
Field
Bit
Operations and Codes
31'
30
OP CODE
11
29
28
27
J DST
010 011
100 101
000 001
AMR LCD YO(3) Y1(3) CRR EN(1)
26
25
24
K DST
000 001
010
011 100 101
XO X1 LCI-LCR NONE EO E1
23
22
MODE
-
21
SAT
20
ADOF
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
00
110 111
EFNONE(2)
110
CO
111
C1
01
10
11
REAL DBPR CPLX
a NO SATURATION MODE
a NO INVERSION
1 SATURATION MODE
1 INVERSION LSB ADDRESS X/y RAM
J7
IIJDEST = EN
see table below.
J CONSTANT
JO
K11
II KDEST = XO or KDEST = X1 and
K7 = a then XRAM Normal Mode
K7 = 1 then XRAM Circular Addressing Mode
K CONSTANT
KO
• EN (Enable) code (101) is a multi-function condition permitting independant programming of RDYOIN and SIM flags, and STA register bit EI in J field of the INI instruction.
Notes:
1) If JDST = EN and:
J7 J6
o X ElMS = no change
1 0 ElMS = 0
1 1 ElMS 1
I
J5 J4
OX: EI
1 0 : EI
1 1 : EI
= no change
=
=
0
1
2) If JDST = NONE and J7 = 1 then low Power mode.
3) If JDST = YO or JDST = Y1 and
J7
o : Y RAM normal mode
1
: Y RAM circular addressing mode.
38/66
590
J1
X
o
1
JO
: SIM = no change
: SIM = 0 system bus Intel
: SIM = 1 system bus Motorol
I o : RDYON = no change
1. RDYON
=
1
ST18930/31
5.2
ALU CODES
MNEMO
Function
ADD
A+B
AD DC
A+B+ CARRY
ADDS
B + AJ16
ADDX
B + A' (COMPLEX CONJUGATE)
AND
A·B
ASL
CARRY
D--i
d
ASR
CLR
CLEAR
COM
COMPLEMENT A
COM
COMPLEMENT B
LCCR
LBUS -> CCR
LSL
CARRY
LSLB
LSL BYTE
LSR
0
LSRB
LSR BYTE
ff-O
0
CARRY
D--i
-1
ff--D
OR
A,B
RCE
EXECUTE RC
RCER
EXECUTE RC 1 LOAD NEW CODE
RCR
LOAD RC
ri
SBC
A + B + CARRY
SBCR
A + B + CARRY
SET
SUB
MO
VF
AO Code
VF (117-121)
*
*
*
*
*
* * *
*
*
*
*0
*
*
*
*
*
*
*
*
*
*
00010
* * * * *
0
*
01111
1
0
0
10011
* 0
*
*
*
* * * *
* 0
*
*
* 0
* 0
*
0
*
*
* 0
*
* * * *
* * * *
10110
51
CR
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*0
0
0
CARRY
NOP
ROR
F
5R
A+B+1
SUBR
A+B+1
TRA
TRANSFER A
TRA
TRANSFER B
XOR
AEBB
SUBS
B + A/16 + 1
tr-D
CARRY
*
*
*
*
*
*
*
*
*
*
CI
Z
*
*
*
*0
0
0
0
*
*
*
*
*
*
*
*
*
*
0
0
0
0
*
*
*
*
*
*
*
*
*
*
0
0
* *
* *
OV
*
0
Notes: 1. A B refer to ALU inputs (respectively LSI DE, RSIDE) not to accumulators AlB.
2. In ASL the OVF bit is equivalent to exclusive OR of bit 14 and 15.
01011
11000
01001
11011
11001
00111
11010
00000
01101
10001
10000
10010
00101
*
*0
*
*0
*
*0
*
*
*
0
0
*
0
0
*
* * *
01110
*
*0
*
*
*
0
*
0
*
* * *
*
*1
*
*
*
*
*
*
*
*0
*
*0
01010
10111
0
*
*0
*
*0
00001
*
* * * * *
*
*1
*
*
*
*
*
*
00011
*
*
*
*
01000
11100
00100
00110
10100
10101
01100
11101
39/66
591
ST18930/31
5. 3. TEST CONDITIONS
True Condition
False Condition
Code
BE3
No BE3
0100
BE4
No BE4
0010
BE5
No BE5
0011
BE6
No BE6
0001
Branch Always
Branch Never
0000
BSO
No BSO
1100
BS1
No BS1
1101
BS2
No BS2
1110
CI
No CI
1010
CR
No CR
0110
MOVF
No MOVF
1011
OVF
No OVF
0111
RDYOIN
No RDYOIN
1111
SI
No SI
1001
SR
No SR
0101
Z
No Z
1000
5.4. AMR AND STA REGISTERS
AMR (Access Mode Register)
8
7
6
5
4
STA (Status Register)
40/66
592
3
2
o
ST18930/31
CONDITION CODE REGISTER (CCR)
Name
Function
Description
SR
Sign Real
Set if the MSB of the ALU result is 1. Cleared otherwise.
SI
Sign Imaginary
Set if the MSB of the ALU imaginary result is 1 (in complex mode). Cleared
otherwise.
CR
Carry Real
Set if a carry is generated out of the MSB of the result for arithmetic and shift
operations. Cleared otherwise.
CI
Carry Imaginary
Set if a carry is generated out of the MSB of the imaginary part of the result
for complex arithmetic and shift operations. Cleared otherwise.
Z
Zero
Set if the ALU result equals zero. In complex mode it is set if both real and
imaginary parts are equal to zero.
OVF
Overflow
Set if there was an arithmetic overflow. This implies that the result cannot be
represented in the operand size. In complex mode it is set for an overflow of
either real or imaginary part. Cleared otherwise.
MOVF
Memorized
Overflow
Set in the same conditions as overflow. Is cleared only when tested by a
branch instruction.
AOVF
Advanced Overflow
Exclusive OR of bit 14 and 15 of the ALU. If there was an arithmetic overflow
on half capacity (15 bits in real/complex mode, 31 bits in double precision
mode). Is memorized and cleared by LCCR ALU instruction.
OVFM
Overflow Multiplier
Set if the multiplier has overflowed. Only meaningful for complex multiplication.
Is memorized and cleared by LCCR ALU instruction.
STATE REGISTER (STR)
Name
EF
Function
Empty FIFO
Description
Set if FIFO is empty. Cleared otherwise.
SAT mode Saturation Flag
Set if the ST18930 is programmed in saturation mode. In this configuration,
the processor will behave as follows:
Positive overflow: ALU result forced to 7FFF
Negative overflow: ALU result forced to 8000
This feature does not apply to double precision mode. This bit is cleared
otherwise.
MODE
(2bits)
Operating Mode
Define a real (01), complex (11) or double precision (10) mode.
XC
XRAM Circular
Circular addressing mode flag for XRAM. (see 3.3.3)
YC
YRAM Circular
Circular addressing mode flag for YRAM. (see 3.3.3)
EI
Enable Interrupt
Enable interrupt flag (ITO, IT1, IT2).
41/66
593
ST18930/31
6. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Value
Unit
Vee
Supply Voltage
Parameter
- 0.3 to 7.0
V
Vln
Input Voltage
- 0.3 to 7.0
V
TA
Operating Temperature Range
o to 70'
°C
Symbol
T stg
Storage Temperature Range
- 55 to 150
°C
P Omax
Maximum Power Dissipation
0.8
W
Stresses above those hereby listed may cause permanent damage to the device. The ratings are stress ones only and functional ope·
ration of the device at these or any conditions beyond those indicated in the operational sections of this specification is not implied.
Exposure to maximum rating conditions for extended periods may affect device reliability Standard MaS circuits handling procedure
should be used to avoid possible damage to the device.
With respect to VSS .
• Other temperature ranges also available on request.
DC CHARACTERISTICS
Vee
= 5.0 V± 10 %, Vss = 0 V, TA = Oto + 70 OC (unless otherwise specified)
Symbol
Parameter
Vee
Supply Voltage
VIL
Input Low Voltage
VIH
Input High Voltage (all inputs except EXTAL)
VIHE
lin
Input High Voltage EXTAL
Input Leakage Current (1) - (3)
IlnEX
Input Leakage Current on EXTAL (3)
VOH
Output High Voltage (lioad
VOL
Output Low Voltage (iload
=- 300
= 2 mAl
llA, except DTACK)
Po
Power Dissipation
Ppd
Gin
ITSI
Three State (off state) Input Current (2)
594
Typ.
Max.
Unit
4.5
5
5.5
V
-0.3
0.8
V
2.4
Vee
V
2.7
Vee
V
-10
+ 10
~
V
2.7
0.5
V
0.35
W
Power Dissipation Low Power Mode
10
mW
Input Capacitance
10
Notes: 1. 100·1031, RESET, BE3, BE4, BE5 and HALT, Nap, CC (for ST18931).
2. 00-D15, ADO-AD?, BE5, BE6 and IAO-IA15, CAD-CAB (for ST18931).
3. Test conditions: Vic = 0.4 V and Vic = VOD.
42/66
Min.
- 20
pF
+ 20
llA
ST18930/31
AC ELECTRICAL SPECIFICATIONS - CLOCK AND CONTROL PINS TIMING (ST18931 only)
(Vcc = 5.0 V± 10 %. TA = Oto +70 DC, see figure 9.1.)
OUTPUT LOAD = 50 pF, DC Characteristics [load
REFERENCE LEVELS
V IL = 0.8 V V IH = 2.4 V t r , tf :s; 5 ns for inputs signals
VOL = 0.8 V V OH = 2.4 V
N° Symbol
1
2
3
4
5
6
7
8
9
Tc
tcex2
tcex4
tcext
tcexw
trst
trstd
tcod
tcot
10
11
12
tdsl
tdsh
tsc
13
thc
14
15
16
tdlc
tdhc
Tc = 80 ns Tc=100ns T c =160ns
Unit
Min. Max. Min. Max. Min. Max.
400
80
320
100
160
640
ns
50
200
ns
40
160
ns
5
5
ns
5
16
24
20
30
ns
16
24
20
20
20
ns
8
8
8
Tc
25
25
25
ns
2
5
2
5
2
5
ns
Parameter
Machine Clock Cycle Time
External Clock Cycle Time (T c = 2 x tcex)
External Clock Cycle Time (T c = 4 x tcex)
External Clock Fall and Rise Time
EXTAL High or Low
RESET to EXTAL Low Set-up and Hold Time
RESET Width Low
EXTAL to CLKOUT Low and High Delay
CLKOUT, MC, OS. RD. WR. R/W Fall and Rise
Time
CLKOUT, High to OS, RO, WR Low
CLKOUT, High to OS, RO, WR High
Control Input Set-up Time
(BSO-BS2, ITO-IT2, BE3-BE6)
Control Input Hold Time
(BSO-BS2, BE3-BE6, ITO-IT2)
CLKOUT High to Control Output Low (IRQ,BA)
CLKOUT High to Control Output High (BA)
RO, WR, OS Pulse Width
-3
-3
20
3
3
10
EXTAL
25
25
32
70
ns
ns
ns
= 2 x External Clock Cycle Time
'I
,
4
L
~8
I I
-,
DS.RD.WR
13
2:
:
:-:
~
14
SA
14
______~r-, I
~-----~~~
10
IRQ
ns
25
25
42
I
~~
BSn or ITn,BEn
10
ns
ns
ns
. ' : - - - - - - - - - : - - - - : ::----'~
--;------------
MC.CLKQUT
5
5
25
25
~'----~/r----~\'---------')
8
-5
-5
20
3
3
10
Figure 25 : Clock and Control Pins Timing for Internal Machine Cycle Tc
(tcex) and frequency of CLKOUT equal EXTAL freq 12.
4
-3
-3
20
-
___'r--
9
\-__~r16
: ':((===================
15
-,
\
~
' - - - - - ' - - - - - 71;//'-------
7?
\,--------~~----------
M88ST18930-22
43/66
595
ST18930/31
Figure 26 : Clock and Control Pins Timing for Intemal Machine Cycle Tc = 4 . lcex4.
EXTAL
MC.CLKQUT(l )
DS.RD.WR
BSn or ITn,BEn
SA
14
IRQ
14
M88ST18930-23
Figure 27: Reset Timing for Internal Machine Cycle Tc = 2 . EXTAL.
EXTAL
~
,
'
6 -::-
,
_I
,
~6
,
RESET
MC CLKOUT
INCYCLE(1)
~
IAO-IA15
IDD-ID31(1)
@O
@O'
@1'
@2
12
M88ST18930-23B
Note: 1. INCYCLE and IDO-ID31 are ST18931 signals.
44/66
596
ST18930/31
INTERNAL CLOCK OPTION
A crystal can be connected across XTAL and EXTAL functioning in the parallel resonant fundamental
mode, AT--cut.
TYPICAL CRYSTAL EQUIVALENT CIRCUIT
11
EXTAL
1
T
ST18930
~
I
=
XTAL
C2
C2
~
M88ST18930-24
Cl, C2 typical value
=
10pF.
M88ST18930-24A
Typical values. Rs = 10 Q
Cl = 0.02 pF
C2 = 4 pF
Q> 30 K
AC MEASUREMENT LOADS
TO All
DTACK
+1.5V
OUTPUTS
OUTPUT
EXCEPT DT ACK
.r
1
50PF
I
M88ST18930-24C
IOW300,uA
M88ST18930-24B
AC TESTING INPUT, OUTPUT WAVEFORM
INPUT/OUTPUT
'''=X
O.4V
2.0V
--
1.0V
2.0V
TEST POINTS
-~
1.0V
x=
A.C. TESTING: Inputs are driven at 2AV for a logic "1" and OAV for a logic "0" timing measurements are made
at 2V for a logic "1" and at 1.0V for a logic "0".
45/66
597
ST18930/31
AC ELECTRICAL SPECIFICATIONS - LOCAL BUS TIMING
(Vee = 5.0 V± 10 %, TA = 010 +70 DC)
N° Symbol
Parameter
Tc = 80 ns T c = 100 ns Tc = 160 ns
Min.
Max.
Min.
Max.
Min.
Max.
Unit
16
tpw
RD, WR, DS Pulse Width
32
42
70
17
tARW
Address Valid to WR, DS, RD Low
20
30
55
18
tAH
Address and RIW Hold Time
5
5
5
19
toow
Data Delay Time, Write Cycle
2'-,)
25
30
ns
20
tOHW
Data Hold Time, Write Cycle
5
5
5
ns
21
tOSR
Data Set-up Time, Read Cycle
22
tOHR
Data Hold Time, Read Cycle
23
tooz
Data Valid to Z State
15
15
ns
ns
20
20
ns
ns
5
5
ns
20
20
ns
Figure 28 : Local Bus Timing Diagram.
Me
'11
-:
ADDRESSES
DS.RD~R
1---
)))) mx:==--:~__ =--===______-,X=
--~--'7~L-- --~~= y--, 18 ,'
,....-,
RrW
---~
,
23
,
:-------1
19
00-015
WRITE CYCLE
: 20
-----_r-~-::o:-1--.
21
00"015
,r---~'
.., - - - ( II
READ CYCLE
: 22
DATA I N ,
'
--
M88ST18930-25
Note: In multicycle exchanges, t pw duration is extended by 1,2, or 3 machine cycle lenghts,
46/66
598
ST18930/31
AC ELECTRICAL SPECIFICATIONS - SYSTEM BUS TIMING
(V cc = 5.0 V ± 10 %, T A = 0 to +70 0C)
N° Symbol
Tc = 80 ns Tc=100ns Tc=160ns
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
24
tspw
SDS, SRD, SWR Pulse Width
30
40
60
ns
25
tSAW
SRIW, CS, RS Set·up Time
15
15
15
ns
26
tSAH
SRIW, CS, RS Hold after SDS High
5
5
5
ns
27
tSDSW
Data Set-up Time, Write Cycle
15
15
15
28
tSDHW
Data Hold Time, Write Cycle
5
5
5
ns
29
tSDDR
Data Delay Time, Read Cycle
25
30
30
ns
30
tSDHR
Data Hold Time, Read Cycle
31
tSDZR
SDS, SRD High to Z State
25
25
30
ns
32
tDSLDT
SDS Low to DTACK Low
20
20
20
ns
33
tDSHDT
SDS High to DTACK Desactivated (1)
20
20
20
ns
5
5
ns
5
ns
Figure 29 : System Bus Timing Diagram for Tranfer of 1 Byte.
24
SDS,SRO,SWR
25
26_ ,
1_ _
:
,
, - -_ _ _ _ _
27_ _ _ _ _:
ADO-AD?
28
I~
I
-----------~-----~<:------D-AT-A-,-N---~~:>~----
WRITE CYCLE
I
29
ADO-AD?
31
DATA OUT
READ CYCLE
32
\
,
DTACK
30
,--~'----,
I
I
,
33
r
~-----------~----~
IRQ
M88ST18930-26
Notes: 1. DTACK is an open drain outpu1. Test load includes RL ~ 820 Q to Vee.
2. This delay depends on programming mode. Its maximum value is 2 . Tc +2 instruction cycles (see user's manual).
47/66
599
ST18930/31
AC ELECTRICAL SPECIFICATIONS - INSTRUCTION INTERFACE TIMING (ST18931 only)
(Vee = 5.0 V± 10 %, TA = Oto +70 ec)
N° Symbol
Parameter
Tc=80ns Tc=100ns Tc=160ns
Min.
Max.
Min.
Max.
Min.
Max.
Unit
34
tlNCH
MC High to INCYCLE High Time
-5
+5
-5
+5
-5
+5
ns
35
tlNCL
MC High or Low to INCYCLE Low Time
-5
+5
-5
+5
-5
+5
ns
36
tlAD
Instruction Address Delay Time
30
ns
37
tlAH
Instruction Address Hold Time
5
5
5
ns
38
tlDS
Instruction Data Set· up Time
30
30
40
ns
39
tlDH
Instruction Data Hold Time
5
5
5
40
tCAD
External CROM Address Delay Time
4t
tCAH
External CROM Address Hold Time
5
5
5
ns
42
tCDS
External CROM Data Set-up Time
t5
15
20
ns
43
tCDH
External CROM Data Hold Time
5
5
5
ns
44
tHS
HALT Set-up Time
20
20
20
ns
45
tHH
HALT Hold Time
10
46
tCSD
MC High to Data Bus
47
tCSH
MC High to Data Bus
48/66
600
20
20
25
25
10
20
5
10
30
5
ns
30
ns
40
5
ns
ns
ns
ST18930/31
Figure 30: 8T18931 Timing Diagram for Internal Machine Cycle Tc = 2 ·lcex2.
i-----TC ------1
EXTAL
34
-
\
I
\
MC
- -
35
I-
\
INCYCLE
36
37
"'K
)<
IAO-IA15
38
100-1031
~V
In
~
39
"'~
In+1
~
40
41
\
CAO-CA9
}
I
42
00-015
Read cycle
44
HALT,NOP
=>v
V
'-,
~
/
45
/K
47
46
CSOL,CSOH
43
\
M88ST18930-27
49/66
601
ST18930/31
Figure 31 : 8T18931 Timing Diagram for Internal Machine Cycle Tc = 4· 1cex4.
EXTAL
MC
INCYCLE
IAO-IA15
50/66
602
ST18930/31
Figure 32 : CLKOUT Output Period Function of the CRR Register Value.
EXTAL
CLKOUT
WITH:
CRR=1
CRR=13 ~
CRR=14 ~
CRR=15 ~
51/66
603
ST18930/31
Figure 33 : Local Bus "Motorola" Write Cycle Timing Diagram.
11
ADO-AD?
addresses
16
1?
18
DS - - - - - - - - - ,
RIW
23
19
20
DO-D15
write cycle
-------------~t__-D-AT-A-O-U-T-~fLI
Figure 34 : Local Bus "Motorola" Read Cycle Timing Diagram.
,
ADO-AD?
addresses
~
~
1?
DS
16
18
}~
\
18
r--R/W
21
DO-D15
write cycle
22
I
1
DATA IN
M88ST18930-25
52/66
604
ST18930/31
Figure 35 : Local Bus "Intel" Write Cycle Timing Diagram.
Me
ADO·AD7
addresses
18
17
RD
16
WR
23
19
20
DO·D15
DATA OUT
write cycle
Figure 36 : Local Bus "Intel" Read Cycle Timing Diagram.
MC-,~_ _
j
ADO-AD?
addresses
11
r-
C
~
1?
16
18
IRD
WR
\
~
21
DO-D15
write cycle
DATA IN
22
1>--
53/66
605
ST18930/31
Figure 37 : Multicycles Exchange Exemple on Local Bus, "Motorola" Write Cycle (one wait state programmed).
TC
MC
10
-
ADO·AD7
addresses
11
i"--
i"--
~
f
17
16 +TC
18
t~
\
18
rR/W
r----
\
23
20
~
00-015
\'\1
write cycle
f-----
r-
-
DX
DATA OUT
~
Figure 38 : Multicycle Exchange Exemple on Local Bus, "Motorola" Read Cycle (one wait state programmed.
-
\'-----j -
11
ADO-AD7
addresses
C
>
16 +TC
17
18
~
os
R/W
\
/
21
00-015
write cycle
54/66
606
22
I
If
\j, DATA IN
ST18930/31
Figure 39 : System Bus: "Motorola" Write Cycle Timing Diagram.
24
SDS
SRIW
~
\
b-------
\
/
26
25
RS,CS
-
C
~
28
2?
ADO·AD?
I
write cycle
<1
DATA IN
~
32
~
DTACK
Figure 40 : System Bus: "Motorola" Read Cycle Timing Diagram.
24
SDS
SR/W
25
26
RS,CS
31
29
30
ADO-AD?
read cycle --------t----<'-"-"--"~'_____D_A_TA_O_U_T_I_----".LL/
32
DTACK - - - - - - - - - - - - ,
IRQ - - - - - - - - - - - - - - - - - - - 1
~ SGS·THOMSON
~"I ~D©rnJ@rn~rnJ@Il'lO©®
55/66
607
ST18930/31
Figure 41 : System Bus: "Intel" Write Cycle Timing Diagram.
24
SWR
26
25
RS,CS
28
2?
ADO·AD?
write cycle
------t-------<
DATA IN
~------+~
33
32
DTACK - - - - - - - - - - - ,
Figure 42 : System Bus: "Intel" Read Cycle Timing Diagram.
24
SRD
SWR
~
\
~
~
25
I
--
RS,CS
31
29
ADO-AD?
read cycle
I
~««<1
32
DTACK
IRQ
56/66
608
1
DATA OUT
~
1>»)-
IJJ
I
ST18930/31
7. PIN CONNECTIONS
48 - Pin Dual - in - Line Package (top view)
D'
1
52 - Pin Plastic Leaded Chip Carrier (top view)
D3
DS
D2
D6
D1
D7
DO
D8
BE3
Dl0
D9
BE'
D11
BSOoriTIi
BSl arm
D10
BSO or TfO
D12
BS2 or Tf2 or LP
D11
BSlorlTl
013
All
D12
BS2
D13
A11
D14
V DD
015
or ill or LP
-
Voo
V DD
D15
VSS
A10
A10
~
M
VSS
A9
XTAL
AS
XTAL
A8
EXTAL
AD7
ClKOUT
AD6
RD or DS
WR or RrW
ADS
SWA or SR/W
AD3
SRDorSDS
AD2
CS
AD1
RS
ADO
EXTAL
AD7
_
CLKOUT
AD6
m.~
-.~
AD'
BE50rBA
RESET
iRa
BE6 or DTACK
M88ST18930-28
M88ST18930-29
1. ST18930 (top view)
4
2
6
7
8
9
10
11
12
13
A
1028
1031
IA15
IA12
lAW
IA7
IA6
lAS
1A2
lAO
BE4
SSo
HAlT
B
1025
1026
1029
IA14
IA11
lAB
VSS
1M
IA1
BE5IBA
BE3
SS1
CAO
c
1022
1023
ID27
1030
IA13
1A9
VOO
1A3
BE6
DTACK
GA9
BS2
NOP
CA1
o
1D19
1021
ID24
RESET
CA2
CM
1017
1018
1020
CA3
CAS
CA6
1014
1015
1016
CA7
CA8
As
1013
VSS
VOO
VOO
VSS
A9
G
ST 18931
PGA 121
H
K
ID12
1011
fOlD
ADO
A11
A10
109
lOB
106
A04
A02
A01
107
IDS
102
NlC
AS
A05
A03
104
101
DO
03
07
011
VSS
CSDH
Me
EXTAL
SOS
A07
AD6
CC
SAIW
cs
LP
XTAL
IRQ
M
103
01
04
06
D9
012
VSS
CSOL
AIW
IN
CYCLE
N
100
02
05
08
010
013
014
015
liS
CLKOUT
M88ST18930-30
57/66
609
ST18930/31
ORDERING INFORMATION
Part Number
Temperature Range'
Package
o to 70°C
o to 70°C
o to 70°C
48 Pin Plastic DIL
52 Pin Plastic LCC
121 Pin Grid Array
ST18930CP/PXXX"
ST18930CFN/PXXX"
ST18931CR
• For extended temp. range, please consult your sales office.
• • XXX is the specific number associated to a customer code.
• The 8T18930/31 is available in 80 ns, 100 ns cycle time versions. Please consult your sales office.
SOFTWARE TOOLS
ST18930 SP-PC
Software Package for PC Including
Macroassembler
Functionnal Stimulator
Linker
ST18930 SP-VMS
Same Software Package for VAX Machines under VMS
ST18930 SPC-PC
Same Software with C-compiler for PC
ST18930 $PC-VMS
Same Software with C-compiler for VAX
HARDWARE TOOLS
ST18930 EMU
Stand-alone Emulator
ST18930 HDS-1
Hardware Development System 110 V Power Supply
ST18930 HDS-O
Hardware Development System 220 V Power Supply
ST18930 EPR48
EPROM Simulation Module for ST18930 in 48 Pins DIP
ST18930 EPR52'
EPROM Simulation Module for ST18930 in PLCC52
• Consult your sales office for availability.
9. PACKAGE MECHANICAL DATA
48 PINS - PLASTIC DIP
16,lmax.
0,51 min
-,
/
0,2
0,3
15.24
25
~8
Datum
if
.~-.-.-.
(11 Nominal dimension
(2) True geometrical position
/I
24
63.5max.
14
48 Pins
58/66
610
ST18930/31
52 PINS - PLASTIC LEADED CHIP CARRIER
Pin 1 identification
19050
19,202
46
I
--~-------+--------E~
I
0661
0,812
~
min.
52
PINS
0331
0,533
121 PINS - PIN GRID ARRAY CERAMIC
,.....
oo,·OQl
~
.~-~
59/66
611
ST18930/31
APPENDIX A
BENCHMARK
Execution Time
(nsec)
Memory Size
(words)
Prgm + coef
Number of
Clock
Cycles
Clock
Freq.
(MHz)
Word
Size
(bits)
Coefficient
Size (bits)
Result
Size
(bits)
20 Tap FIR
Filter
2400
6 + 20
24
10
32
16
16
64 Tap FIR
Filter
6800
6 + 64
68
10
32
16
16
67 Tap FIR
Filter
7100
6 + 67
71
10
32
16
16
8 Pole
Cascaded
Canonic Biquad
IIR Filter (4X)
2800
13 + 20
23
10
32
16
16
8 Pole
Cascaded
Canonic Biquad
II R Filter (5X)
2400
13 + 20
23
10
32
16
16
8 Pole
Cascaded
Transpose
Biquad IIR
Filter
3300
15 + 20
33
10
32
16
16
Dot Product
600
6
6
10
32
16
16
Matrix Mult 2X2
Times 2X2
1400
14
14
10
30
16
16
Matrix Mult 3X3
Times 3X1
1500
15
15
10
32
16
16
M-to-M FFT 64
Point
121300
203 + 388
1213
10
32
16
16
..757300
349 + 764
7573
10
32
16
16
256 Point
60/66
612
ST18930/31
APPENDIX B
DEVELOPMENT TOOLS
DEVELOPMENT PROCESS
The development process of a digital signal processing application using the ST18930 or ST18931 is
supported by a complete range of dedicated software and hardware tools which includes macroassembler, linker, simulator, C compiler and optimizer
(respectively ST18930SP or ST18930SPC), standalone emulation card ST18930EMU, multiprocessor hardware development system ST18930HDS,
EPROM emulation module, ST18930EPROM.
SOFTWARE TOOLS
All the development softwares run on the most common computers, such as IBM-PC® or AT®, under
MS-DOS® or VAX®, VMS®, UNIX® or UL TRIX®
operating systems.
The macroassembler supports conditional assembly, high level language facilities for loop definition
and generates all the files for simulation, emulation
and PROM programming.
The functional simulator provides step by step execution, break on address and data values, access
to all intemal registers and interface to I/O files
(ADC, DAC, test inputs).
The linker provides modular programming facilities.
The library consists of macros, basic DSP routines
etc ... and provides additional help to user's for their
applications.
The C language compiler offers high-level language
facilities which meets the advanced requirements
(parallelism, pipe-line, three computation modes,
32-bit instruction set) of the ST18930/31.
HARDWARE TOOLS
All the hardware tools are designed to provide ease
of use and minimum learning time by utilizing menu
driven and DSP specific emulation features.
ST18930 EMU and ST18930 HDS have in common:
_ Full speed emulation of ST18930 and ST18931
_ Use of internal, external or application clock
_ 20 breakpoints (stops at defined addresses)
_ 8 complex breakpoints (stop after N address X
and M address Y)
_ Realtime trace of internal resources
_ Emulation probes (for ST18930 or ST18931)
_ Menu driven operation (about 100 commands)
_ Resident Assembler/Disassembler with full
screen editor
_ Symbolic debbuging
_ Direct link with PROM programmers
Emulator specific features.
The ST18930EMU is a low cost, stand-alone emulator providing advanced emulation features such
as real-time trace. It can be driven via a RS232C
link by a terminal or an IBM-PC R and offers:
_ 8 K program memory (expandable to 64 K)
_ 2 K x 16-bit data RAM
_ A wire-wrapping area
_ Full speed 100 ns cycle emulation
_ 2 RS232C serial ports
_ Complex conditions break-points
Hardware development station features:
The ST18930 H OS is a hardware development station, aimed at the development of multiprocessor
applications. Up to four pairs of emulator boards,
and logic analyser boards can be combined to
match exactly the user needs:
_ CMOS memory for backup of configuration
_ 64 K x 32 program memory
_ 4 K x 16 data RAM
_ A logic analyser with:
* 2 K x 19 bit for trace of ST18930/31 bus and 15
extemal inputs
* Synchronous analyzer on program and local buses
* Asynchronous analyzer on system bus or extemal
inputs
* Triggering conditions (Address bus with count, data bus external branch inputs, mailbox exchanges,
extemal inputs).
EPROM module.
The ST18930EPROM is a small-sized module
which uses the perfect compatibility between
ST18930 and ST18931. The module uses a
ST18931 and fast EPROM memories to emulate in
real time a ROM masked SR18930 during prototyping or field tests to minimize hardware developments. The module is plug and function compatible
with ST18930 pin out.
61/66
613
ST18930/31
APPENDIX C
MASKING INFORMATION
The information required by SGS-THOMSON
Microelectronics to realize a customer masked version of the ST18930 are provided below.
The files for masking must include program ROM
content and coefficient ROM content. They can be
transferred on EPROMS, 5" 1/4 floppy disks, magnetic tapes (VAXNMS format) or by link to SGSTHOMSON Microelectronics. This must be done in
conjunction with your local sales office or representative indications.
VERIFICATION MEDIA
All original pattern media are filed for contractual
purpose and are not returned. A computer listing of
the ROM content code will be generated and returned to the customer with a listing verification form.
The listing should be carefully checked and the ap-
proval form completed, signed and returned to SGSTHOMSON. The returned verification form is the
contractual agreement for generation of the customer masks and batch manufacturing.
VERIFICATION UNITS
Ten engineering samples containing the customer
ROM patterns will be sent for program verification.
62/66
614
These samples will be engineering samples and
must be kept by user as reference parts.
ST18930/31
DIGITAL SIGNAL PROCESSOR
CUSTOMER ORDERING SHEET
COMMERCIAL REFERENCE'
COMPANY
CUSTOMER'S MARKING
ADDRESS
PHONE
PATTERN MEDIAS
o
EPROMS
o
5 1/4" FLOPPY
o
o
OPTION
o
WATCHDOG
MAGNETIC TYPE
o
LOW POWER ON BS2 PIN
OTHER*
o
DIVISION OF CLOCK IN
LOW POWER MODE
o
DIVISION OF EXTAL
0+2
0+4
YEARLY QUANTITY FORECASTED:
START OF PRODUCTION DATE
FOR A SHIPMENT PERIOD OF
Customer Contact Name
Date
Signature
• See your local sales office the different options.
63/66
615
ST18930/31
APPENDIX D
SUMMARY OF RESOURCES PER FUNCTION
OPERATING MODES
Symbol
MODE
Function
2-bit register defining the operating mode
(real/complex/double precision)
Resource
Paragraph
Nb
Access Mode Register
3.2
Resource
Paragraph
Nb
OPERATING UNIT
Symbol
Function
ALU
2 Port 16-bit Arithmetic Logic Unit.
5 Possible Sources. 4 Possible Destinations. 30 ALU Codes
Works on 32-bit. Data in 2 Machines Cycles.
Arithmetic Logic Unit
3.2. 1
Variable 0 - 15-bit right shift, left shift, right rotation barrel
shifter.
Barrel Shifter
3. 2. 2
MULT
16 X 16 ...... 32 parallel pipeline multiplier + 16-bit
adder/substractor , used in complex Multiplications.
Pipeline Multiplier
3. 2. 3
M,N
2 X 16-bit registers containing multiplier operands.
D
BS
P
ALU Output Register
2 X 16-bit register containing multiplier result.
STA
16-bit register containing status of ALU, mode, status of
address calculation units,enable interrupt flag.
Status
3. 2. 4
STR
7-bit register included in STA.
Status
3. 2. 4
CCR
9-bit register included in STA.
Status
3. 2. 4
A
2 x 16-bit accumulator.
Accumulators
3. 2. 4
B
2 x 16-bit accumulator.
F
3. 2. 4
4 x 16-bit first in first out register.
Fifo
EF
Flag. Indicates that the Fifo is empty; can be set by software.
Empty Fifo
RC
6-bit register allowing replacement of ALU operation code by
a data coming from L-BUS.
Replace Code Register
3. 2. 4
2 x 16-bit register providing direct transfer between L-BUS
and Z-BUS.
Transfer Register
3. 2. -4
Flag indicates saturation mode.
Saturation
3. 2. 4
T
SAT
64/66
616
8T18930/31
DATA MEMORY BLOCK
Symbol
Function
Resource
Paragraph
Nb
XRAM
YRAM
192 x 16-bit (X) and 128 x 16-bit (Y) Random Access
Memories
Data RAMs
CRaM
512 x 16-bit read only memory containing coefficients or
constants.
Data ROM
XACU
YACU
Arithmetic units providing address incrementation, decrementation and automatic loop.
XACU is dedicated to XRAM. (8 bits)
YACU is dedicated to YRAM. (7 bits)
Address Calculation Units
3.3.2
ECACU
3.3. 1
12-bit arithmetic unit providing incrementation,
decrementation of address.
Shared by CRaM and ERAM (external RAM).
XC
YC
Flag indicates the circular addressing mode for XRAM.
Flag indicates the circular addressing mode for YRAM.
XRAM Circular Flag
YRAM Circular Flag
3.3.3
XO, X1
X
2 x 8-bit registers used for indirect addressing of XRAM
Supplementary register used for circular addressing.
Pointers
3.3.4
YO, Y1
Y
2 x 7-bit registers used for indirect addressing for YRAM.
Supplementary register used for circular addressing.
CO, C1
2 x 9-bit register used for indirect addressing of CRaM.
EO, E1
2 x 12-bit registers used for indirect addressing of ERAM.
CONTROL BLOCK
Symbol
IROM
Function
Resource
Paragraph
Nb
Instruction ROM
IR
3072 x 32-bit word read-only-memory containing program
code and immediate data for ST18930 (ref section 6. 6 for
ST18931)
32-bit register containing instruction.
PC
Register containing address of program memory.
Program Counter
3.4.3
SEQ
The sequencer can test directly 16 conditions programmed
on a high or low state and the sequencer controls next
program address' defined by BRANCH, subroutine call, next
instructions or interrupt.
Sequencer
3.4.1
RAS
2 x 16-bit register for saving programm counter in case of
subroutine call or interrupt.
Return Address Stack
3.4.1
LC
15-bit register containing a control word for automatic loop. It
is divided into the following sub-registers.
Loop Counter
3.4.4
LCI
4-bit register containing the number of instructions to be
executed in the loop.
8-bit register containing the number of loops.
3-bit register containing the number of instructions between
declaration and start of the loop.
Watchdog Circuit
3.6.3
Low Power Mode
3.6.4
LCR
LCD
Prevents locked states for ST18930 only.
LP
. Freezes the circuit operation.
3. 4. 2
Instruction Register
65/66
617
ST18930/31
INPUT/OUTPUT BLOCK
Symbol
IT
AMR
RIN
ROUT
Function
Ressource
Paragraph
Nb
Interrupt routine start.
Interrupts
3.5.1
8-bit register defining the access mode on the 2 external
buses (local and system).
Access Mode Register
3. 5. 7
3 x 8-bit shift registers.
Mailbox input.
3 x 8-bit shift registers.
Mailbox output.
Input Registers
3. 5. 6
Output Registers
RDYOIN
Flag used in the protocol to indicate witch processor has
access to the mailbox.
Read Out Internal
3. 5. 5
CRR
4-bit register defining EXTAL to CLKOUT frequency ratio.
CLK Rate Register
3.6.1
SIM
Flag used to define access mode on system bus.
System Intel Motorola
3. 5. 7
66/66
618
ST18940/41
DIGITAL SIGNAL PROCESSOR
MAIN FEATURES
• 100ns MACHINE CYCLE TIME (1.2 CMOS
Technology)
• PARALLEL HARVARD ARCHITECTURE
• TRIPLE DATA BUSES STRUCTURE
• 3 DATA MODES. SINGLE PRECISION
. DOUBLE PRECISION
. COMPLEX
• 32-BIT INSTRUCTION
• MULTIPLIER 16 x 16-> 32, SIGNED AND UNSIGNED
• 32-BIT BARREL SHIFTER, 32-BIT ALU
• PROVISION FOR FLOATING POINT
• FOUR 32-BIT ACCUMULATORS, FOUR LEVEL 32-BIT FIFO
• IMMEDIATE AND COMPUTED BRANCH
• 8-LEVEL STACK
• 9- EXTERNAL AND 3 INTERNAL INTERRUPTS
• AUTOMATIC LOOP, UP TO 256 TIMES 32
INSTRUCTIONS
• 2 INDEPENDENT PARALLEL BUSES; LOCAL
AND SYSTEM
• FULL SPEED ACCESS TO EXTERNAL 64K x
16-BIT MEMORY ON THE LOCAL BUS
• HARDWARE AND/OR SOFTWARE WAIT
STATES MODE TO ACCESS SLOWER EXTERNAL MEMORIES/PERIPHERALS, DMA
CHANNEL
• 2 x 16 BYTES FIFO ON THE SYSTEM BUS
• SERIAL CHANNEL FOR DIRECT INTERFACE
WITH CODEC, ISDN IC's ...
• GENERAL PURPOSE PARALLEL PORT
• ON CHIP DATA RAM 2 x 256 x 16-bit
• FOUR INDEPENDENT ADDRESS CALCULATION UNITS
• ADDRESSING MODES: IMMEDIATE, DIRECT,
INDIRECT WITH POST MODIFICATION, CIRCULAR, BIT REVERSED
• 2 VERSIONS: - ST18940 (PLCC/PGA 84) CLOSED VERSION WITH 3K x 32-BIT ON-CHIP
PROGRAM ROM AND 512 x 16-BIT COEFFICIENT ROM
- ST18941 (PGA 144) OPEN
VERSION WITH 64K x 32-BIT OFF-CHIP PROGRAM ROM AND 128 x 16 BIT ON-CHIP COEFFICIENT RAM
• POWER DOWN MODE
• TYPICAL CONSUMPTION O.5W
March 1989
DEVELOPMENT SYSTEM
The ST18940-41 is supported by a complete set of
hardware and software tools for system development. The software package includes an assembler/linker, a simulator, and a "C" compiler and
optimizer which run under several VAX and PC operating systems. Hardware tools include a standalone emulator, an EPROM emulation module, a
multiprocessor development station and an evaluation module (PC compatible).
8T18941 - PIN GRID ARRAY - 144-pin
8T18940 - PLA8TIC LEADED CHIP CARRIER - 84-pin
8T18940 - PIN GRID ARRAY - 84-pin
1/50
619
ST18940/41
DESCRIPTION
The ST18940/41 Digital Signal Processor is a member of SGS-THOMSON Microelectronics ST18 family.
The ST18 family comprises 3 products covering a
wide spectrum of DSP applications. Complete development tools (hardware and software) are available as aids to efficient system designs.
The first processor in the ST18 family is the
TS68930/31 (NMOS) with a 160ns machine cycle
time. The second member of the family, the
ST18930/31, is a CMOS version of the TS68930
with a faster instruction cycle time (80ns) and the inclusion of additional hardware and software features (The ST18930 is pin compatible with the
TS68930).
The ST18940/41, which is described in this datasheet, is the third member in the family. It is upward
compatible with the other members of the family, but
provides enhanced arithmetic capabilities, addressing modes and additional I/O functions.
2/50
620
It is an advanced HCMOS single chip general purpose DSP designed for fast arithmetic intensive
applications in the areas of telecommunications,
modems, speech processing, graphic/image processing spectrum analysis, audio processing, digital filtering, high speed control, instrumentation,
numeric processing ...
The ST18940 structure is based on a triple 16-bit
data bus, a 16 x 16 multiplier, a 32-bit ALU. The powerful parallel and seriallnputlOutput interfaces and
the DMA channel contribute to the flexibility of the
system interface with external environment.
Two versions are available:
_ the ST18940 includes 3K x 32-bit program
ROM and 512 x 16-bit coefficient ROM.
_ the ST18941 microprocessor version can address up to 64K of program memory on a dedicated bus, thus providing true real-time
emulation of the ST18940 ROM version. In
addition to the two internal RAMs (X and V),
a 128 x 16-bit coefficient RAM is included for
coefficient memory emulation.
ST18940/41
TABLE OF CONTENTS
TITLE
Page
PIN DESCRIPTION
6
1.1. LOCAL BUS
7
1.2. SYSTEM BUS
7
1.3. DMAISERIAL I/O INTERFACE
7
1.4. PARALLEUINTERRUPT INTERFACE
8
1.5. POWER SUPPLY/CLOCK
9
1.6. OTHER PINS
9
1.7. SPECIFIC PINS TO THE ST18941
9
2.
ARCHITECTURE
9
3.
BLOCK DIAGRAM
10
FUNCTIONAL DESCRIPTION
10
1.
4.
5.
6.
4.1. INTRODUCTION
10
4.2 PROGRAM CONTROLLER
10
4.3. DATA ARITHMETIC UNIT
12
4.4. DATA STORAGE UNIT
16
4.5. INPUT/OUTPUT
18
SYSTEM CONFIGURATION
22
5.1. MINIMUM APPLICATION (ST18940)
22
5.2. BUS EXTENSION
24
5.3. SPECIFIC APPLICATION WITH THE ST18941
25
SOFTWARE
26
6.1. INSTRUCTION FORMAT
26
6.2. INSTRUCTION SET
27
6.3. PROGRAMMING EXAMPLE
29
3/50
621
ST18940/41
Page
TITLE
7.
ELECTRICAL SPECIFICATIONS
30
7.2.
30
DC ELECTRICAL CHARACTERISTICS
7.3. CLOCK CHARACTERISTICS
31
7.5.
32
EXTERNAL CLOCK OPTION
7.6. SYSTEM BUS TIMING
33
34
LOCAL BUS TIMING
7.8. INTERRUPT TIMING
36
7.9.
37
--
--
HOLD, LP, HALT TIMING
7.10. P-PORT TIM ING
9.
30
7.4. AC MEASUREMENTS CONDITIONS
7.7.
8.
30
7.1. ABSOLUTE MAXIMUM RATINGS
38
7.11. DMA TIMING
39
7.12. SERIAL CHANNEL TIMING
40
7.13. INSTRUCTION BUS TIMING ST18941
43
PIN CONNECTIONS
44
8.1. ST18941 - OPEN VERSION
44
8.2. ST18940 - MASKED VERSION
45
ORDERING INFORMATION
46
9.1.
46
DEVICE
9.2. SOFTWARE TOOLS
46
HARDWARE TOOLS
46
9.3.
10.
MECHANICAL DATA
47
11.
DEVELOPMENT TOOLS
48
TABLE OF APPENDICES
4/50
622
A.BENCHMARK
49
B. MASKING INFORMATION
50
ST18940/41
TITLE
Page
TABLE OF FIGURES
Figure 1 : Input/output pins.
Figure 2 : ST18940-41 Block diagram.
6
10
Figure 3 : ST18940-41 Program controller.
11
Figure 4 : Interrupt-enable Register.
Figure 6 : Data Storage unit block diagram.
12
13
17
Figure 7 : Input/Output functions.
19
Figure 5 : Data Arithmetic unit block diagram.
5/50
623
ST18940/41
1. PIN DESCRIPTION
Figure 1 : Input/Output Pins.
MASKED VERSION ST18940
3K X 32 PROGRAM ROM
512 X 16COEF. ROM
32BIT
(/)
:::J
I
ALU
BARREL SHIFTER
4 ACCU
FIFO
m
~
l-
(/)
ADDRESS
"--'DATA
~ADDRESS
w
(16,16) X (16,16)--> (32,32) MULTIPLIER
>(/)
. . - - . CONTROL
2X256X16RAM
INTERRUPT
PARALLEL PORT
SUPPL YICLOCK
DMNSERIAL PORT
INTERRUPT
. . - - . PARALLEL PORT
.....-... DMNSERIAL PORT
MAILBOX
~ADDRESS
::<
+--DATA
Cl
<{
128 X 16 COEF. RAM
OPEN VERSION ST18941
6/50
624
""'-"'CONTROL
a:
oa:
(L
ST18940/41
1.1. LOCAL BUS
Name
Pins
Type
DO-D15
I/O
Local Data Bus
16-Bit Data Bus~h impedance when exchanges are not
active or when RESET, HOLD, HALT or LP are active.
AO-A15
a
Local Address Bus
16-Bit Address Bus for Local Data. In high impedance
when HOLD, HALT or LP are active.
DS/RD
a
a
Data Strobe/read
Synchronizes the transfer on local bus/read cycle.
R/W / WR
Read/write/write
Indicates the current bus cycle state/write cycle.
DTACK
I
BR
a
HOLD
I
HOLDACK
a
Function
Description
Data Transfer Acknowledge
Indicates exchange acknowledgement.
Bus Request
Active at each exchange on the local bus. In combination
with DTACK, can be used to address resources shared by
several processors.
Hold Data
Used to free local bus in shared memory application. To
HALT state if an access is attempted.
Hold Acknowledge
Indicates that the processor is in hold state.
1.2. SYSTEM BUS
Name
Pins
Type
SDO-SD7
I/O
CS
RS
SDS/SRD
Function
Description
System Data Bus
8-Bit data bus used for exchanges between the processor
and a host via the mailbox.
I
Chip Select
Selection of the system bus interface.
I
Register Select
Address to select data FIFO or status register (MBS).
I
Data Strobe/read
Synchronizes the transfer on the system bus/read cycle.
SRIW/SWR
I
Read/write/write
Indicates the current system bus cycle/write cycle.
SDTACK
0
System Data Transfer
Acknowledge
Indicates data exchange is acknowledged. Open drain.
IRQ
0
Interrupt Request
Signal sent to the host to signal readiness for mailbox data
exchange.
1.3 DMNSERIAL 1/0 INTERFACE: DUAL PURPOSE INTERFACE
Internally the DMA channel and serial 110 are irnplernented as fully independent separate blocks, al-
though externally they are share 4 dual purpose 1/0
pins.
- DMA CHANNEL
Name
Pins
Type
DMARQ
I
DMACK
DMAEND
DSDMA
Function
Description
DMA Request
Activated by the device requesting the DMA. Can be a pulse
("single" mode) or a level ("burst" mode) (DPIO).
a
a
DMA Acknowledge
Indicates that the request for DMA is acknowledged (DPI1).
DMA End
Indicates the end of the DMA exchange. Active as long as
the channel is not reinitialized (DPI2).
a
Data Strobe DMA
Synchronizes the DMA exchange (DPI3).
- - - - - - - - - - - - - - -,
~ SGS·THOMSON
~"'!I l!Alij!:Gl@rn~rn!mGl@l!'lij!:~
7/50
625
ST18940/41
- SERIAL INPUT/OUTPUT INTERFACE
Name
Pins
Type
FSR
1/0
Frame
Synchronization
Receive
Synchronizes the receive, Can be generated or received by
the processor (DPIO),
BClKR
1/0
Bit Clock
Receive
Receive bit clock, Can be generated or received by the
processor (DPI1),
DA
1/0
Data A
Input or Output of Data A (DPI2),
DB
1/0
Data B
Input or Output of Data B (DPI3),
FSX
1/0
Frame
Synchronization
Transmit
Synchronizes the transmit. Can be generated or received by
the processor (DPI4),
BClKX
1/0
Bit Clock
Transmit
Transmit bit clock, Can be generated or received by the
processor (DPI5),
Function
Description
------Note: DMARQ/FSR, DMACK/BCKLR, DMAEND/DA, DSDMA/DB are multiplexed,
1.4 PARRALLEUINTERRUPT INTERFACE
This 8-bit port can be configured either as an interrupt controller or as a parallel input/output port,
- INTERRUPT CONTROLLER
Name
Pins
Type
PO-P3
I
Maskable
Interrupt
Request
A negative transition on these input pins will initiate an
interrupt sequence,
P4-P7
I
Maskable
Interrupt
Request
A low level on these input pins will initiate an interrupt
sequence,
Function
Description
- PARALLEL INTERFACE
Name
Pins
Type
PO-P7
1/0
8/50
626
Function
Parallel Port
Description
8-Bit parallel port with each bit programmable individually
as input or output. Can be used as test conditions in branch
instructions; four bits are edge sensitive, four are level
sensitive,
ST18940/41
1.5. POWER SUPPLY - CLOCK
Name
Pins
Type
XTAl
0
EXTALI
ClKIN
I
CLKOUT
0
Function
Description
Crystal Output
Internal oscillator output for crystal. Not connected if the
internal oscillator is not used.
Crystal Input
Internal oscillator input. External clock input. when the
internal oscillator is not used. Oscillator frequency is twice
the machine frequency.
Clock Out
Internal clock output (oscillator frequency
Vee
5 Volts
Power Supply.
Vss
Ground
Connected to Ground.
+
2).
1.6. OTHER PINS
Name
Pins
Type
Function
Description
INT
I
Interrupt
Maskable interrupt request. Active Low
RESET
I
Reset
Program counter is loaded with Hex. 0 and a NOP instruction
is executed. Clock generator is resynchronized.
LP
I
Low Power
Stops the processor at the end of the current cycle, forces
the NOP instruction and puts the processor in the powerdown
mode. The internal processor state is conserved.
HT2
0
Clock
Reserved for test.
1.7. SPECIFIC PINS TO THE 18941 (open version)
Name
Pins
Type
IAO-IA15
0
100-1031
NMI
Function
Description
Instruction Address Bus
16-Bit address bus for external program memory. In high
impedance if HALT is active or during a OMA exchange.
I
Instruction Data Bus
32-Bit data bus from external program memory.
I
Non Maskable Interrupt
Interrupt input edge sensitive. Program counter is loaded with
Hex. A.
HALT
I
Halt
Stops the processor at the end of the current instruction.
Local bus and instruction address buses are in high
impedance.
ECR
0
Enable CROM
Indicates that the AO-AS addresses are used for the external
emulation of the CROM.
INCYClE
0
Instruction Clock
A falling edge indicates the start of a new instruction cycle.
2. ARCHITECTURE
The architecture is HARVARD like with separate
instruction bus and data buses. The block diagram
shows four main blocks (see fig. 2) :
- the program controller
- the data arithmetic unit
(ALU, multiplier and barrel shifter)
- the data storage unit
- the inputs/outputs
These four blocks can be considered as four independent processors working in parallel and commu-
nicating via three 16-bit data buses.
Within a single machine cycle the processor is able
to execute all of the following operations:
- read two operands in internal or external memory
- execute a multiplication
- execute an ALU operation
- write a result to internal or external memory
- modify three address pointers
- in addition, I/O operations with on-chip peripherals
may take place concurrently with internal operations.
9/50
627
ST18940/41
3. BLOCK DIAGRAM
Figure 2: ST18940/41 Block Diagram.
L
1S
- 8US
EXTE RNAL
R - BUS
1S ,
U
1
XAAM
DATA
ARITHM ET1C
D
~
F~
VRAM
258 x 10
258 x 18
XACU
VACU
ARITH.
ARITH.
512 x 18
UNIT
16
x
BS
18.32
DATA
LOCAL
SWITCH
.....
ADORES S
CRAM
UNIT
UNIT
7 REG.
7 REG.
ARITH.
CACU
UNIT
ARITH.
7 REG.
UNIT
DMA CHANNEL
r
~
-
"-------1B
Z
92
1- BUS
16
r---'
92 BIT
REGISTERS
BUS
EACU ~
128 x 16
82 BIT
ALU
1<
BUS
LOCAL
DATA
BUS
REG.
CONTROLLER
I
BUS
1
ON CHIP PERIPHERALS
110
.............-.
MAIL BOX
PARALLEL PORT
SERIAL PORT
--
~ROGRA"
PROGRAM
R 0 ..
CONTROLLER
:
3K x 32
16 .
/
10
INTERRUPTS CLOCK
•
t
INSTRUCTION
INSTRUCTION
ADDRESS
DATA
BUS
4. FUNCTIONAL DESCRIPTION
4.1. INTRODUCTION
One of the key features of the ST1840141 is that all
hardware resources have been designed to support
the following three data types:
- simple precision: 16-bit data
- double precision: 32-bit data
- complex: 16-bit real and 16-bit imaginary
Anyone of the above three arithmetic modes can
be dynamically selected by means of a single program instruction. Once the mode has been selected,
all resources (such as ALU, memories, registers,
multiplier) are automatically configured for the appropriate operations. The same assembler instructions are used in all three modes. In
double-precision and complex modes the data are
10/50
628
stored in two contiguous memory locations, with an
automatic adjustment of the address calculation
unit. Two's complement representation is used
throughout. In real mode, all instructions except
branch are executed in one cycle time. In complex
and double precision modes, all instructions are executed in two cycle times.
4.2. PROGRAM CONTROLLER
4.2.1. PROGRAM CONTROLLER (see figure 3).
The purpose of the program controller is to generate the next instruction address to be executed, this
instruction being in external memory for the
ST18941 (64Kwordof32-bit) orin the masked ROM
for the ST18940 (3K word of 32-bit). The program
controller takes into account the current mode to
execute the instruction; one cycle per instruction in
ST18940/41
real mode, two cycles per instruction in double precision and complex mode. The HALT, HOLD, LP
and the "WAIT STATES" suspend the sequencer
cycle.
Programming model for loop execution
LOOP: Loop Register
It is used to automatically control the execution of a
loop. This 16-bit register is divided in to 3 fields, LCI,
LCR, LCD.
Exceptions in linear program address generation
are the following:
- Execution of a branch instruction
- Call and return of a subroutine
- Execution of an interrupt routine: 2 types of hardware interrupt sources are possible : external
interrupt [I NT + P PORT + NMI (ST18941 only)], internal interrupt (Mailbox, serial port). The EI register
enables or disables these interrupt sources.
LCI (Loop Count Instruction) defines the number of
instructions to be executed in a loop; the maximum
is 32 (5-bit).
LCR (Loop Count Register) defines the repeat count
of the loop; the maximum is 256 (8-bit).
LCD (Delay) defines, in terms of the number of
instructions, the delay between the loop declaration
and the beginning of the loop execution. The maximum is 7 (3-bit).
- An 8-level stack is used to save and restore the PC
in case of interrupts or subroutines.
This "repeat of instruction blocks" feature provides
code compaction and time efficient execution for
vector and array processing frequently used in DSP
algorithms. It is set at the macroassembler level by
using a simple REPE-BEGIN-END construct.
- Loop execution: Automatic loop execution is possible by means of the loop register. This register defines the numberof loops to be executed (max. 256),
and the number of instructions in the loop (max. 32).
Figure 3 : ST18940/41 Program Controller.
8
Z - BUS
-
COUNTERS
I
I
,---
L,L
L A R
I
+ 1
t--;;w
"
:>
0
)(
.
W
BRANCH
~
..... EDIATE BRANCH
0
1-------0
~
I
I
REGISTER
CONTROL
T
BRANCH
J I
T
PP~RT SERIAL 110
INT
NMI
"
'-"-
~
INTERRUPT
16 Bi t INsTRUCTION
ADDRESS
0
"
l
ENABLE INTERRUPT
"<
"
"
~
:>
INTERRUPT VECTOR
---
~
'"w
COMPUTED
I
BUS
lOOP
STACK
I
I
16
11
11
x 16
32
MAILBOX
CONTROL
i
I
T
CCR
PPORT MAILBOX
DMA
11/50
629
ST18940/41
4.2.2. INTERRUPT CONTROL
* There are two types of hardware interrupt sources
on the ST18940/41 : internal and external.
-The intemal sources include chip peripheral de'
vices: Mailbox (input/output)
Serial port (1 for transmit, 1 for Receive)
-The external interrupts include RESET, INT, NMI
(ST18941 only) and the P Port (8 pins)
RESET, INT, P..1..l'5, P6, P7 are low level sensitive
interrupts and NMI, PO, PI, P2, P3 are falling edge
sensitive.
* The EI (enable interrupt) register is an 8-bit wide
enable interrupt register. It controls the following interrupt sources: Mailbox, INT, P Port (see figure 4).
Figure 4 : ST18940/41 Enable Interrupt Register
XEI, REI part of SSR Register (see page 21).
turn from interrupt) instruction is processed. The
content of the top location in the stack is popped into the PC.
Table 1 : Interrupt Vectors.
Address
0
1
2
3
4
5
6
7
8
9
10
Interrupt Sources
RESET
INT
R INT (serial 1/0 receive)
X INT (serial 1/0 Transmit)
B INT (mailbox)
P4, P5, P6, P7
PO
P1
P2
~
NMI (ST18941 only)
4.3. DATA ARITHMETIC UNIT (figure 5)
One of the most useful features of the ST18940-41
is to provide the user with three operating modes
which can be dynamically set by software.
These three modes represent different data types:
INT
-REAL 16-bit data
MAILBOX
-Complex (CPLX) 16-bit real + 16-bit imaginary data
P4.P5,P6,P7
-Double-precision (DBPR) 32-bit data.
PO
'--------+--l.-?--P1
P2
-~.---------+=~--"
;
~
XEI
--------+---V.---
XINT
=
REI
---------1.--;>-
RINT
E
~
* Software interrupt can be implemented using PPort.
* When an interrupt is acknowledged, the current
program counter is pushed on the stack and the interrupt vector corresponding to the interrupt source
(see table 1) is loaded into the program counter
(PC). Upon completion of interrupt routine, a RTI (re-
12/50
630
In double precision mode, data moves from and to
memories are performed on 32 bits. This is especially useful in adaptive processing to keep track of
L.S.B. updated coefficients.
Thus the DSP is seen by the user as a standard
16-bit real or complex machine or a 32-bit real machine. All operating units are automatically adjusted
by the processor to the right length.
In all modes, the number representation used is signed 2's complement.
'
4.3.1. MULTIPLIER. In real and double-precision
modes, the multiplier executes a 16xl6-bit ->
32-bit signed or unsigned multiplication every instruction cycle.
-The operands are loaded into the M and N registers and the result of a previous multiplication is written in the P register during the same cycle.
ST18940/41
-In complex mode the multiplier executes acomplex
multiplication every instruction cycle (2 x machine
cycles) ie:
(a + jb) x (c + jd) = (ac - bd) + j(ad + bc).
In this case the registers M and N are 2 x 16-bit and
the P register is 2 x 32-bit.
-The pipeline structure makes the multiplication result available 2 instruction cycles later in all 3 modes.
The status bits relating to the multiplier are in STA
(Status register) and the multiplier overflow (complex mode only) is updated in the Code Condition
Register.
4.3.2. 32-BitALU/ACCUMULATOR. The 32-bitALU
is loaded on the right side by the R bus, by the RBD
register or by the accumulators (A, B). On the left
side, the operands always access the ALU through
the barrel shifter, coming either from the L (left) bus
or from the multiplier output register P.
The result of an ALU operation is automatically written in the 0 register and, if required, into the accu-
mulators or FIFO.
The ALU performs 32 different operations. These
include the usual arithmetic, logical and shift operations e.g. ADD, SUB and AND. Additional special
operations are also implemented. These include
ADDS or SUBS (addition and subtraction with automatic prescaling of the left-side ALU input), and ABSolute value and EDGE operations (used for first significant bit detection and exponent adjustment).
The complete list of ALU codes and description is
given in table 2 - P 27.
4.3.3. BARREL SHIFTER. The 32-bit barrel shifter
located on the left side of the ALU performs all logic/arithmetic shifts and rotations. The shift value
comes from the ALU code or from the BSC (Barrel
Shift Control) register loaded by the Z bus. This feature combined with EDGE (Alu Code) allows easy,
efficient and dynamic normalization used in floating
point and dynamic scaling operations.
Figure 5 : Data Arithmetic Unit Block Diagram.
L - BUS (16/24)X
R-BUS (16)
MU l TlPLIER
P(Zx32)
I-I
I
I
I
FrDm
I
1-8US_~_
A.LU.
Z-8US
(16/24) x
• See Note Page 15/58.
13/50
631
ST18940/41
4.3.4. PROGRAMMING MODEL
Name
Function
Description
M
16 - Bit Register
2x16 - Bit (complex mode)
Left side operand of multiplier loaded via L bus.
N
16 - Bit Register
2x16 - Bit (complex mode)
Right side operand of multiplier loaded via R bus.
p
32 - Bit Register
2x32 - Bit Register (complex)
Multiplication Result
0
32 - Bit Register
ALU Result
A1, A2
2x32 - Bit Registers
Accumulators A1 and A2 are selected by ACS bit 2 of STA
register in real and double precision modes.
B1, B2
2x32 - Bit Registers
Accumulators B1 and B2 are selected by ACS bit 2 of STA
register in real and double precision modes.
FIFO
4x32 - Bit Registers
FIFO loaded by ALU.
T
2x24 - Bit Registers
Bidirectional register between L bus and Z bus.
RBD
2x16 - Bit Registers
Right bus delay, this register is used as a buffer on the ALU
right side.
STA
16 - Bit Register
Status register defining the state of the data arithmetic unit.
CCR
16 - Bit Register
Condition code register containing the flags generated by the
data arithmetic unit. Every bit can be tested as a branch
condition.
RC
7 - Bit Register
This register, directly connected to the ALU control unit, can
be dynamically loaded by the L bus.
BSC
5 - Bit Register
Barrel shift control register is loaded by the Z bus and
contains the shift value for the barrel shifter.
14/50
632
ST18940/41
CONDITION CODE REGISTER (CCR)
Name
Bit #
SR
15
Sign Real
Set if the MSB of the ALU result is 1. Cleared Otherwise.
SI
14
Sign Imaginary
Set if the MSB of the ALU imaginary result is 1 (in complex
mode). Cleared Otherwise.
CR
13
Carry Real
Set if carry is genera1ed out of the MSB of the result for
arithmetic and shift operations. Cleared Otherwise.
CI
12
Carry Imaginary
Set if a carry is generated out of the MSB of the imaginary
part of the result for complex arithmetic and shift operations.
Cleared Otherwise.
Z
11
Zero
Set if the ALU result equals zero. In complex mode it is set if
both real and imaginary parts are equal to zero.
OVF
10
Overflow
Set if an arithmetic overflow occurs. This implies that the
result cannot be represented in the operand size. In complex
mode it is set for an overflow of either the real or imaginary
part. Cleared Otherwise.
MOVF
09
Memorized Overflow
Set under the same conditions as overflow. Cleared when
tested by a branch instruction.
AOVF
08
Advanced Overflow
Exclusive OR of bits 30 and 31 of the ALU. Set and
memorized if arithmetic overflow occurs on half capacity.
Cleared when tested by a branch instruction.
OVFM
07
Overflow Multiplier
Set and memorized if the multiplier has overflowed in
complex mode. Cleared by LCCR ALU instruction.
06
Empty FIFO
Set if FIFO is empty. Cleared Otherwise.
EF
Function
05-.00
Description
Reserved
STATUS REGISTER (STA)
Description
Name
Bit #
EPI
15
Function
EPR
14
Enable Real Product
Real product enable under interrupt.
SE
13
Smallest Exponent
Conditional Load of BSC
Enable Imaginary Product
12
Reserved
11
Reserved
10
Reserved
Imaginary product enable under interrupt.
MODE
09/08
EMI
07
Enable Multiplier Input
Multiplier enable under interrupt.
Real /CPLX/DBPR
TCM
06
Two's Complement M
M signed/unsigned.
TCN
05
Two's Complement N
N signed/unsigned.
CPR
04
Conjugate Product Result
M x N conjugate.
ALU Saturation
SAT
03
SATuration
ACS
02
ACcumultator Selection
A1 or A2 and B1 or B2
FORM
01
FORMat * see note 1.
24 MSB/16 LSB Selection
RBDS
00
Right Bus Delay Selection
RBD Register Selection
Note: The data buses and the T register are 24 bits wide enabling 24-bit wide ALU results to be fed back to the left ALU
input.
15/50
633
ST18940/41
4.4. DATA STORAGE UNIT (figure 6)
The ST18940/41 provides four different data memories within two categories: the data memories and
the coefficient memory. The coefficient memory in
the ST18940 is a 512 x 16-bit masked ROM
(CROM). For emulation of the ST18940 CROM, a
128x16 internal CRAM is provided in addition to the
external 512x16 CRAM. Internal CRAM is usefull
when coefficients are to be used in conjunction with
external data in the same instruction. For both versions the internal data memories consist of two
256x16 bit RAM's denoted XRAM and YRAM. The
external addressing space is of size 64k x 16-bit
(ERAM) and is accessible via the local bus using a
single instruction as for the internal memories.
Each memory is controlled by a dedicated Address
Calculation Unit called XACU for the XRAM, YACU
for the YRAM, CACU for the CRAM or CROM and
EACU for the ERAM.
4.4.1. ADDRESSING MODES. The addresses are
generated by each ACU according to the four addressing modes:
- Immediate addressing:
the data is in the instruction
- Direct addressing:
the address is in the instruction
- Indirect addressing:
the address is in one of the ACU registers
16/50
634
- Circular addressing:
also called virtual shift mode
Bit reversed mode
4.4.2. ADDRESS CALCULATION UNITS (ACU).
The dedicated ACU's are independent and contain
7 registers: two banks of dual pointers selected by
a bit in the ASTA register, one current pointer used
in the circular addressing mode, and, two post-incrementing/decrementing registers. The register
structure of XACU is given below:
XOA, X1 A : dual pointer bank A
XOB, X1 B : dual pointer bank B
X2 : current pointer in circular addressing
K, L : two post-incrementing/decrementing registers
The CACU is the only ACU with a single pointer
bank.
The circular addressing mode uses the A bank pointer for the minimum and maximum limits and the curent pointer for the current address.
Each ACU (with the exception of CACU) supports
bit reversed addressing as required for the FFT algorithms.
For the external data memory in direct addressing
mode, the 16-bit address is obtained by concatenating the 13 bits contained in the instruction (LSB) to
the 3 bits of the page register (MSB).
ST18940/41
Figure 6 : 8T18940/41 - Data Memories Block Diagram.
L - BUS
R - BUS
/
1B
./ 1.
1B
r-----
YACU
ptACL
XRAM
258 •
18
rXOA
-rXIA
-r--
r--E-
YRAM
~
XI8
:::8
VIB
r-I
:~:
-~
LV
::
1B
EOA
(ST19940)
512 x 18
~
co
1----·--
: CRAM ~
: (5T18841) ~
I 1 fax 1G
--,-I
I
1B
I.
LOCAL BUS ADDRESS
E A C U r-----------,L..---+
ACU
r-:
258 x 1B
CROM
,f,.
I
I
LC
r--
EIA
E2
EOB
EIB
I
A ST A---,
(See 4.4.3)
KE
LE
,.
Z - BUS
ST18941 ONLY
17/50
635
ST18940/41
4.4.3. ASTA REGISTER - ADDRESS STATUS REGISTER
Name
Bit #
RBX
15
Register Bank Selection
RAM X
Function
RBY
14
Register Bank Selection
RAMY
Select Bank A or B
RBE
13
Register Bank Selection
ERAM
for X, Y or ERAM
11
External Coefficient
ST18941 only, Internal or External CRAM Selection
BRX
10
Bit reversed RAMX.
BRY
09
Bit reversed RAMY.
BRE
08
Bit reversed ERAM.
XC
07
Circular RAM X
YC
..
06
Circular RAMY
EC
05
Circular ERAM
CC
04
Circular CROM
Reserved.
12
EC
Description
Set bit reversed mode.
Set circular addressing mode.
ADOFX
03
ADOF RAMX
ADOFY
02
ADOF RAMY
Force the 1st address in complex or double.
ADOFE
01
ADOF ERAM
Precision mode to be odd or even.
ADOFC
00
ADOF CROM
4.5.
The
-the
-the
-the
-the
INPUT/OUTPUT
ST18940/41 provides four 1/0 interfaces:
system bus
local bus
parallel port
serial interface
4.5.1. THE SYSTEM BUS. For asynchronous
exchanges between the ST18940/41 and a host
(general purpose MCU andlor other ST18940/41
processors), the ST18940/41 is provided with a
"mailbox mechanism" comprising a double 16-byte
FIFO, one for input (RIN), one for output (ROUT).
18/50
636
A 6-bit status register MBS is accessible to both the
ST18940/41 and the host. Internally RIN is connected to the L bus and ROUT to the Z bus. Externally
SDO-SD? gives access to RIN and ROUT.
The CS input selects the mail box (RIN, ROUT,
MBS) in the host system addressing space while t1J..e
RS input selects RIN-ROUT or MBS. The (SR/W,
SWR) and (SDS, SRD) inputs synchronize and
control the exchanges on the system bus. These signals are programmable (AMR bit ?) in order to be
directly compatible with MOTOROLA or INTEL
hosts.
ST18940/41
-
-
MBS REGISTER· MAILBOX STATUS REGISTER (6 BIT RIW)
Description
Name
Bit #
Function
RIE
5
Register Input Empty
Input FIFO Empty
RIF
4
Register Input Full
Input FIFO Full
RISH
3
Register Input DSP/host
Input to processor/host indicates to which input mailbox
belongs to.
ROE
2
Register Output Empty
Output FIFO Empty
ROF
1
Register Output Full
Output FIFO Full
ROSH
0
Register Output DSP/host
Output to processor/host indicates to which mailbox belongs to.
Figure 7: InpuVoutput Functions.
LOCAL BUS
OO-DIS
LBUS
RBUS
ZBUS
----------------------
os
!SAD)
~!S_
!!!L..-.
DTACK
AMR
HOIJ)
HOLDACK
EOA
EIA
EOB
E1B
E2
KE
Po-P7
LE
EACU
____________
ADDRESS BUS
..J
I
r--s:":OUT=-"'---.J
:==S;X~~~l..J
SIN
i
I
!I
I
I
___ IL _______ _
DPICHi
Ao-A15
DMA
COHTI'IOI..
ADMA
CDMA
ST 18940-41
1/0 UNIT
NOn:: MAILBOX. SeHIAL I/O
PPORT. CAN GENERATE
INTERRUPTS
19/50
637
ST18940/41
4.5.2. LOCAL BUS. On this 16-bit bus (16-bit data,
16-bit address) the ST18940/41 can access external memories or peripherals. To access slow devices, the DSP can stretch its external memory cycle by the insertion of wait states. This can be achieved using either of the two following methods:
-Hardware mechanism : the external memory or peripherals generates a DTACK pulse to signal the
end of the exchange
-Programmable multicycle exchanges·: the exchange lasts for the number of cycles programmed
by the ESO and ES1 bits of the Access Mode Register. Easy implementation of multiprocessor application using the local bus is allowed by mean of the
HOLD function. External devices can take control of
the local bus by using the HOLD and HOLDA pins.
-AMR REGISTER: ACCESS MODE REGISTER (8 - BIT, RfW)
Name
Bit #
I/M
7
MASK
6
Description
Functions
Intel/MOTOROLA Format
System Bus
Must be...§et according to the host control: (RD, WR) or
(SDS, SWiRl
When this bit is set, an interrupt will reset the AMR bits: ESO,
ES1, DTACKEN, CSSO, CSS1 (at the end of the interrupt
routine, previous AMR state is automatically restored).
DPIF
5
Dual Purpose Interface
DPI Function Selection (serial I/O or DMA)
CSS1
CSSO
4
Control Signal Selection
Select one of the three possible sets of control signals on the
local bus.
DTACKEN
2
ES1
ESO
1
0
3
DTACK Enable
DTACK Validation
Exchange speed (1 to 4 cycles)
4.5.3. PARALLEL INTERFACE. The P port is a general purpose 8-bit port, where each bit is programmable as input or as output by means of the DDR
8-bit register. In addition each bit can be used as an
external test condition in a branch instruction or as
an interrupt source. Four bits (PO-P3) are edge sensitive and four bits (P4-P7) are level sensitive.
4.5.4. DMA CHANNEL. The DMA channel controls
transparent exchanges on the local bus between internal XRAM, YRAM or ERAM and an external device.
Single and burst modes are provided. In single
mode, the exchange is processed word by word and
synchronized by the DMARQ signal (edge sensitive). In burst mode, the exchange is carried out on
a block basis with the number of words to be transferred stored in CDMA (13-bit register). In this case
the DMARQ is level sensitive and the end of the exchange is indicated by the assertion of the DMAEND
signal. The DMA channel is accessed through four
pins of DPI port (Dual Purpose interface) and is programmed by the three following registers:
-SOMA REGISTER: STATUS DMA (6 - BIT-R/W)
Name
Bit #
DMEND
5
End of DMA
0/1
4
DMA as Input or Output
E
3
DMA with ERAM
Y
2
DMA with YRAM
X
1
DMA with XRAM
B/S
0
Burst/single Mode
20/50
638
Functions
Description
ST18940/41
ADMA Register (13-bit-R/w) : contains the DMA address
-Transmitted and received words can be programmed to 8 orlo 16 bits (XWL-RWL).
TDMA Register (16-bit-R/W) : DMA data buffer
-In one frame several words can be transmitted or
received. XSO-XS5 (resp. RSO-RS5) indicate the
starting time slot forthe transmit (resp. receive) part,
XEO-XE5 (resp. REO-RE5) indicate the ending time
slot for the transmit (resp. receive) part.
4.5.5. SERIAL 1/0. This serial port provides 2 bidirectional lines DA and DB programmable as input
or output to give access to the receive orto the transmit part of the port.
Four pins are dedicated to clock and synchronization:
-BCLKX and BCLKR : Transmit and Receive Clocks
Frequency equals to single or double the data rate.
-FSX and FSR : Frame synchro pulse.
These four signals can be internally or externally generated.
-The serial port shares 4 pins with the DMA channel controller.
-Direct interfacing with serial devices (such as CODEC, ISDN ... ) is provided.
-SIN - Serial Input Register (8 - 16-bit - Read)
-SOUT - Serial output Register (8 - 16-bit - Write).
SSR - SERIAL STATUS REGISTER (16-bit - R/W)
Functions
Name
Bit #
XEI
15
Transmit· Interrupt Enable
XRE
14
Transmit - Interrupt (SOUT empty)
XER
13
Transmit - Underspeed Error
XEN
12
Transmit - Enable
XWL
11
Transmit - Word Length (8 or 16)
XF
10
Transmit - Frequency
XDL
09
Transmit - Delay Synchro
XCS
08
Transmit - Internal Clock
REI
07
Receive - Interrupt Enable
RRF
06
Receive - Interrupt (SIN full)
RER
05
Receive - Overspeed Error
REN
04
Receive - Enable
RWL
03
Receive - World Length (8 or 16)
RF
02
Receive - Frequency
RDL
01
Receive - Delay Synchro
RCS
00
Receive - External Clock
XCR - TRANSMIT CONTROL REGISTER (15-bit - R/W)
Name
Bit #
XZ
14
Level 1 High Impedance
Functions
x:v
13
Output Buffer Enable
X AlB
12
Transmit on DA or DB
XEO·XE5
06-11
Time Slot # End of Transmit
XSO-XS5
00-05
Time Slot # Start of Transmit
21/50
639
5T18940/41
RCR - RECEIVE CONTROL REGISTER (13-bit - R/W)
Name
Bit #
RNB
12
REO-RES
06-11
Time Slot # End of Receive
RSO-RS5
00-05
Time Slot # Start of Receive
Functions
Receive on DA or DB
CRC - CLOCK CONTROL REGISTER(16-bit - R/W)
Name
Bit #
Reserved
15
TO-T5
09-14
PSC
08
COO-CD?
OO-O?
Funct10ns
Reserved
Frame Synchro Frequency
Prescaler 1/8
Internal Clock Division Range
5. SYSTEM CONFIGURATIONS
5.1. MINIMUM APPLICATION (ST18940 + peripherals)
The ST18940/41 input/output architecture has been
designed to support a wide variety of peripherals
types, speeds, and organizations without the use of
additional circuit chips (glue chip). A minimum application consists of one processor connected to one
peripheral.
The following examples show the method to interface several types of peripherals with the ST18940.
5.1.1. PERIPHERAL ON LOCAL BUS.
DATA
OO-D15 4
AO-A15
R!W
ADDRESS
•
CONTROL
DS
PO
-INT
P1
ST18940
INTACK
The peripheral can be AID converter, parallel CODEC ...
Exchange can be initialized by interrupt or polling
(branch condition).
22/50
640
PERIPHERAL
* (R/W, DS) can be changed to (RD, WR) signals.
ST18940/41
5.1.2. PERIPHERAL ON DMA CHANNEL, DPI PORT.
OATA
00-015 4
~
OMARQ
--
OMACK
--
OMAENO
--
OSOMA
5T18940
PERIPHERAL
5.1.3. PERIPHERAL ON SERIAL PORT (TYPICAL APPLICATION - SERIAL CODEC)
OA
FSX
BClKX
,
3/
OB
FSR
BClKR
5T18940
3/
I
t'
CONTROL J
PERIPHERAL
Several peripherals can be connected, assuming they use different time - slots (up to 64)
23/50
641
ST18940/41
5.1.4. PERIPHERAL ON PARALLEL PORT.
PO-P7
-INT
ST18940
PERIPHERAL
5.2. BUS EXTENSION
The external double-bus architecture is well suited
for connections to rnernory extensions or to a host
cornputer. The system bus/mailbox is intended for
cornrnunication with other procesors while the local
bus is designed for flexible straightforward memory
extension interfacing.
5.2.1. EXTENSION ON LOCAL BUS.
AO·A15
DO-D15
,
16/
16/
or
*
D
@
RAM
CSWECiE
DS/RD
RiW/WR
ST18940
24/50
642
+t t
I
*
@
D
ROM
cs
DE
+ t
*
D
@
PERIPH.
CSDSRAV
+t
ST18940/41
5.2.2. HOST PROCESSOR INTERFACE ON SYSTEM BUS.
8
7
DATA 4
"
2.,
ADDRESS
•
SDD-SD?
-
CS, RS
7
2.,
CONTROL
-
-
SDS ,SFVW
-
-
IRQ
IRQ
--
SDTACK
HOST
ST18940
SYSTEM BUS
• (SDS, SR/W) can be changed to (SRS, SWR) signals.
5.3. SPECIFIC APPLICATION WITH ST18941
(ROM LESS VERSION)
bus to access 64K x 32-bit of external program memory without any additional logical glue.
The ST18941 (open version) provides a dedicated
PROGRAM MEMORY INTERFACE
HALT
...--32
D
100-ID31
IAD-IA15
ST18941
16
@
RAM/ROM
25/50
643
ST18940/41
6. SOFTWARE
6.1. INSTRUCTION FORMAT
The instruction set is divided into 5 instruction
* calculation instruction
OPIM
OPIN
OPDI
* shift instruction
SHIFT
TFR
* transfer instruction
BRI
* branch instruction
BRC
* Initialization instruction
PIN I
RINI
types:
with immediate addressing
with indirect addressing
with direct addressing
with direct addressing
with direct addressing
Immediate branch
Computed branch
Pointer initialization
Register initialization
By virtue of the parallel architecture, each instruction controls a number of concurrent operations.
The instruction format is divided into a number of
fields, which can be used to specify source and destination and operation type for the 4 resources .
Zbus, Lbus, Rbus and ALU.
Typical field:
, and < sources>,
and
Typical instruction format:
All instructions (except control instructions) are executed in 1 machine cycle (100ns) in REAL mode. All
instructions are executed in 2 machine cycles
(200ns) in complex and double-precision modes.
, , < bus field>,
,
In all three modes, every instruction occupies 1 single word (32-bit) of program memory.
26/50
644
ST18940/41
6,2, INSTRUCTION SET
6,2,1, ALU CODES, The ALU code is used with calculation instructions (section 6,3,2), Enhanced shift
operations are available with the shift instruction
(section 6,3,3),
Table 2 : List of Alu Codes,
Type
Mnemonic
ADD
ADD
ADDC
ADDS
ADDX
Addition
Addition with Carry
Addition with L side operand shifted by N bits.
Add the complex conjugate of L-side.
Function
SUB
SBC
SBCR
SUB
SUBR
SUBS
Substract
Reversed
Substract
Substract
Substract
LOGIC
AND
COM Lor R
XOR
OR
SHIFT
ASL
ASR
LSL
LSLB
LSR
LSRB
ROR
Arithmetic Shift Left
Arithmetic Shift Right
Logical Shift Left
Logical Shift Left of 8 Positions
Logical Shift Right
Logical Shift Right of 8 Positions
Rotate
RC
RCE
RCER
RCR
Execute RC
Execute and replace RC.
Load RC
MISCELLANEOUS
ABS
CLR
NOP
SET
LCCR
TRA L or R
EDGE
with Carry
substract with carry (Rside - Lside),
Lside - Rside
R side - L side
with L side operand shifted by N bits.
Logical AND
Complement R side or L side
Exclusive OR
Inclusive OR
Absolute Value
Clear
no Operation
Set to One
Load L Bus into CCR Register
Transfer operation from L side or R side.
Edge Transition for Binary Point Detection
6,2.2. CALCULATION INSTRUCTION. The three
instruction types OPIM, OPDI, OPIN have the same
structure but differ in terms of addressing mode.
OPIM is for use with immediate addressing on R
source operands. OPDI is for use with direct addressing on L source operands, OPIN is for use with
indirect addressing on all operands, With the
exception of some shift operations, the calculation
instructions are the only instructions providing access to the ALU codes,
Instruction structures are given below for each
class.
Detailed information is provided in the user's manual and in the programming reference card,
27/50
645
ST18940/41
Z Field
OPIN
Source
I
I
(1)
L Field
Des!.
Source
Indirect
Indirect
I
I
ALU
Code
Source
Des!.
R Field
Des!.
Source
(2)
Indirect
I
Des!.
I
(2)
Most of the tYPical DSP algorithms are implemented on the ST18940-4t system using OPIN class instructions.
Z Field
OPDI
L Field
I
Des!.
Source
I
Des!.
Source
(1)
I
Indirect
Direct
I
(2)
Indirect
Des!.
Source
(2)
Value
Z Field
OPIM
L Field
Source
NOT
AVAILABLE
Indirect
I
I
ALU
Code
Source
Des!.
R Field
Source
I
Des!.
I
(2)
ALU
Code
Source
Des!.
R Field
I
I
Des!.
(2)
(1) Sources of the Z field are typically selected from the set of options: ALU output (0 register), accumulators AI, Bl, A2, B2
and FIFO.
(2) Destinations of the Lbus and Rbus are typically the multiplier input registers and the ALU inputs (which are not latched).
6.2.3. SHIFT INSTRUCTIONS. The shift instruction
allows access to barrel shifter operations with pro-
grammable shift values.
L Bus
SHIFT
CODE
SHIFT
VALUE
Source
Direct
6.2.4. TRANSFER INSTRUCTION. The transfer instruction TFR is used to move data through the Z
I
I
Z Bus
oEST.
Source
(2)
(1)
I
I
DEST.
Indirect
bus. All internal registers can be accessed in read
and write through the Z bus.
Z Bus
TFR
Source
Register
I
I
DESTINATION 1
Register
6.2.5. BRANCH INSTRUCTION. The branch address for conditional branch operations may be immediate or computed. In the latter case the new PC
value may be loaded from accumulators A, B, FIFO
Branch
BRANCH
Conditions
I
DESTINATION 2
J
Direct
orthe T register. Twenty three conditions can betested (Condition Code Register, mailbox and DMA
flags, and PPORT).
Branch Address
Immediate
or
Computed
PC ~ave Operations
Z Bus
Source
PC
I
I
DESTINATION
Indirect
The "PC save" field allows stack extension in data memory (either internal or external) with a minimum execution time overhead.
28/50
646
ST18940/41
6.2.6. INITIALIZATION INSTRUCTIONS. The PINI
instruction is used for pointer initialization.
In addition to mode setting, PIN I instruction provides
initialization of 2 address pointers in one cycle.
Field 1
PINI
Immediate
Value
Mode
I
. ..
The RINI instruction IS used to initialize Index address registers, DMA registers, loop counters as
RINI
Field 2
Register
or
Resource
Immediate
Value
I
Register
or
Resource
well as the bits of the status (STA register) .
Value
Register
Register
Dest. 1
Dest. 2
Note: Two registers cannot be initialized in the same RINI instruction. Only one register of class 1 or 2 can be initialized
thin a single instruction.
wi~
6.3. PROGRAMMING EXAMPLE
OPIN ST B [EO] + K ; LDL [XO] + L M ; LDR [YO] - K N ; ADDS P A, AI
OPIN
Instruction type
ST B [EO] + K
Z field: B is stored into ERAM location addressed
by EO. The next EO value will be EO + KE
LDL [XO] + L M
L field: XRAM location addressed by XO is transferredvia the LBUS and stored inthe MULTIPLIER
input M. The next XO value will be XO + LX
LOR [YO]- K N
R field: YRAM location addressed by YO is transferred via the RBUS and stored in the MULTIPLiER input N. The next YO value will be YO - KY
ADDS PA, A
ALU field: product scaled by BARREL SHIFTER
(shift value given by BSC) is added to previous value of A, result is stored into A.
29/50
647
ST18940/41
7. ELECTRICAL SPECIFICATIONS
7.1. DC ABSOLUTE MAXIMUM RATINGS
Symbol
Value
Unit
Vee *
Supply Voltage
Parameter
- 0.3 to 7.0
V
Vin*
Input Voltage
- 0.3 to 7.0
o to 70
V
DC
Operating Temperature Range
TA
T stg
Storage Temperature Range
- 55 to 150
'C
PDmax
Maximum Power Dissipation
0.8
W
• With respect to Vss.
Stresses above those hereby listed may cause permanent damage to the device. The ratings are stress ones only and functional operation of the device at these or any conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Standard
MOS circuits handling procedure should be used to avoid possible damage to the device.
7.2. DC ELECTRICAL CHARACTERISTICS
Conditions: Vec ± 10%, Ambient Temperatures
Symbol
= O°Cto 70°C
Parameter
Vee
Power Supply
Vil
Input Low Level
VIH
Input High Level
lin
Input Leakage Current
VOH
Output High Level (IOH
VOL
Output Low Level (Iol
= 300~A)
= 2mA)
Min.
Typ.
Max.
Unit
4.5
5
5.5
V
- 0.3
0.8
V
2.4
Vee+0.3
V
-10
10
~A
2.7
Power Dissipation
Po
V
0.5
V
W
0.5
7.3. CLOCK CHARACTERISTICS
Symbol
Fx
Parameter
Frequency
Min.
Typ.
5
C1, C2
10
Max.
Unit
20
Mhz
pF
The CKLOUT frequency is half the crystal operating frequency.
INTERNAL CLOCK OPTION
Acrystal can be connected across XTAL and EXTAL functioning in the parallel resonant fundamental mode,
AT - cut.
TYPICAL CRYSTAL EQUIVALENT CIRCUIT
EXTALf-_ _.--_ _
-tC~
XTAL~--~--~C~
ST18940/41
C1, C2 TYPICAL VALUE
30/50
648
= 10 PF
TYPICAL VALUES:
RS = 10 OHMS C2 = 4 PF
C1 = 0.02 PF
Q > 30 K
ST18940/41
7.4. AC MEASUREMENT CONDITIONS
OUTPUT LOAD
10L
VDD
TO OUTPUT
except SDTACK o----,--~
+ 15
v
SDTACK
IOH
AC TESTING INPUT, OUTPUT WAVEFORM
2 . 4 V = X 2.0V
0.4 V
~ TEST POINTS"
10 V '
2.0V
X
'1.0 V
~
_ _ __
AC TESTING INPUTS ARE DRIVEN AT 2.4V FOR A LOGIC "1" AND O.4V FOR A LOGIC "0".
TIMING MEASUREMENTS ARE MADE AT 2V FOR A LOGIC "1" AND AT 1.0V FOR A LOGIC "0".
31/50
649
ST18940/41
7.5. EXTERNAL CLOCK OPTION
Num.
TX
Parameter
Max.
Unit
Period
Min.
50
200
ns
Duty Cycle
40
60
%
5
ns
5
ns
+5
ns
+5
ns
Typ.
Rise Time
Fall Time
Tc
CLKOUT Period
1
OS Low to CLKOUT Delay
-5
2
OS High to CLKOUT Delay
-5
3
OS, RD, WR, DSDMA Low Level
4, 5
Conditions: Vee = 5.0V ± - 10%, Vss = OV, TA = 0 to 70 C.
CLKOUT
---.¥
4
32/50
650
Tc /2
15
RESET Set up
RESET
ns
2xTx
ns
ns
ST18940/41
7.6. SYSTEM BUS TIMING
Num.
Parameter
2
1
SOS. SRO. SWR Pulse Width
3
Address to SOS Hold
5
4
R/W to SOS Setup
SR/W to SOS Hold
?
Data in to SWR. SOS Setup
Min.
Address to SOS Setup
6
Data in to SWR. SOS Hold
8
Data out to SRO. SOS Delay
9
Data out to SRO. SOS Hold
11
10
SOTACK to SRO. SWR, SOS Delay
~
S.OV ± 10%, Vss
~
OV, TA
~
Unit
ns
ns
ns
ns
ns
ns
ns
25
25
25
50
5
5
SOTACK to SRO, SWR, SOS Hold
Conditions: Vee
Max.
40
15
5
15
5
15
5
ns
ns
ns
ns
a to 70·C.
SYSTEM BUS TIMINGS
1
CS,RS
2
".
SOS
~
K
)
5
RIW
~
--~
I
?
SOD-SO?
DATA IN
6
~
DATA IN
8
9
SOD-SOl
DATA OUT
>---
DATA OUT
11
10
SDTACK'
"
V-
Note: SDTACK is an open drain output.
33/50
651
ST18940/41
7.7. LOCAL BUS TIMING
Num.
Min.
Max.-
Unit
1
DS, RD, WR Pulse Width
Parameter
Tc/2-1O
Tc /2
ns
2
Address to DS, RD, WR Delay
T c/2-25
ns
3
Address to DS, RD, WR Hold
5
ns
4
DATA to DS, WR Delay Write
Tc/2-25
5
DATA to DS, WR Hold Write
5
6
DATA to DS, RD Setup Read
15
ns
7
DATA to DS, RD Hold Read
5
ns
8
DTACK to CLKOUT Delay
15
ns
9
DTACK to CLKOUT Hold
15
ns
7.7.1. LOCAL BUS TIMING WITHOUT WAIT STATE
CLKOUT
DS,RD,WR
ADDRESSES
RiW,BR
00-015
DATA OUT
00-015
DATA IN
34/50
ru'l
SGS·THOMSON
'J,
fiIIilnCII@~I!l@ll'la
652
ns
25
ns
ST18940/41
7.7.2. LOCAL BUS TIMING WITH WAIT - STATE
WAIT-STATE
CLKOUT
DS,RD,WR
2
3
ADDRESSES,
IWi,BR
DO-D15
DATA OUT
OUT
DO-D15
DATA IN
DTACK
35150
653
ST18940/41
7.S. INTERRUPT TIMING
Num.
Parameter
Min.
Max.
Unit
1
INT. P4-P7 to CLKOUT Setup
2
INT. P4-P7 to CLKOUT Hold
5
ns
4
NMI. PO-P3 to CLKOUT Setup
15
ns
3
NMI, PO-P3 to CLKOUT Hold
10
ns
Conditions: Vee
~
5.0 V ± 10%. Vss
~
a V.
TA
ns
20
~
a to
lO'C.
CLKOUT
INT, P4-P?
NMI, PO-P3
PC
INSTRUCT.
36/50
654
N
X. . __
__I_n_-1_____
ln_____XBRANCH INTERRUP. VECTOR
X . . ___
I_v_ _
ST18940/41
7.9. HOLD, LP, HALT TIMING
Num.
Parameter
Min.
5
HOLO to CLKOUT Setup
20
6
HOLO to CLKOUT Hold
5
Max.
Unit
30
ns
ns
ns
ns
ns
7
CLKOUT High to HOLOACK Low
8
CLKOUT High to HI-Z
5
30
9
CLKOUT High to Valid
0
5
Conditions: Vee
=
5.0 V ± 10%, Vss
=
a V,
TA
=
a to
70'C.
CLKOUT
HOLO,
HALT, LP
PC
NIl
INSTRUCT.
NOP
7
HOLDACK
AO-A15, IAO-IA~, QQ-0.12. }
100-1031, OS, RIW, BR, ECR
AO-A1S, 00-015, OS,
RiW,
BR
HALT
HOLD
37/50
655
ST18940/41
7.10. P-PORT TIMING
Num.
1
Parameter
Min.
CLKOUT to High to PO:? Valid
2, 4
PO:P? to CKLOUT Setup
3, 5
PO:P? to CKLOUT Hold
Conditions: Vee = 5.0 V ± 10%, Vss =
a V, TA = a to
70'C.
CLKOUT
P DATA
OUTPUT
PDATA
INPUT
CLKOUT
P-PORT
BRANCH CONDITION
INSTRUCllON
PROGRAM COUNTER
38/50
~
SIiS-THOMSON
~""'!I UIilU©Ul@~~~©~Ul@IllU©~
656
Max.
Unit
30
ns
20
ns
5
ns
ST18940/41
7.11. DMA TIMING
Num.
Parameter
6
OMARa to CLKOUT Setup
7
OMARa to CLKOUT Hold
8
OMACK to CLKOUT Oelay
9
CLKOUT High to OMAENO Valid
10
11
OMARa to CLKOUT Setup
Min.
Max.
20
5
ns
ns
30
30
40
10
OMARa Pulse Width
Unit
ns
ns
ns
ns
Conditions: Vee = 5.0 V ± 10%, Vss = 0 V, TA = 0 to 70'C.
CLKOUT
DMARQ
t-
DMACK
OO
a:
::J
~
«
:::;:
0
DSDMA
~
DMAEND
10
DMARQ
lu
-'
CJ
z
DMACK
0
«
:::;:
0
DSDMA
\
/
'--I
39/50
657
ST18940/41
7.12. SERIAL CHANNEL TIMING
Num.
Parameter
Min.
Max.
Unit
1
BCLKR, BCLKX Period
200
ns
2
BCLKR, BCLKX Width Low
80
ns
3
BCLKR, BCLKX Width High
80
4
BCLKR, BCLKX Rise Time
30
ns
5
BCLKR, BCLKX Fall Time
30
ns
6
FSR, FSX to BCLKX, BCLKR Setup
30
ns
7
FSR, FSX to BCLKX, BCLKR Hold
0
ns
8
DA, DB to BCLKR Setup
20
ns
9
DA, DB to BCLKR Hold
10
BCLKX High to DA, DB Valid
30
ns
11
FSX High to DA, DB Valid
30
ns
12
BCLKX High to DA, DB-Z
30
ns
ns
ns
0
0
Serial Channel Timing. Non Delayed Data Mode.
Conditions: Vee = 5.0 V ± 10%, Vss = a V, TA = a to lO'C.
SERIAL CHANNEL TIMING: NON DELAYED DATA MODE
2
RECEIVE
4
3
5
BCLKR
FSR
3
DNDB
TRANSMIT
BCLKX
FSX
DNDB
10
40/50
658
N
X'--___
5T18940/41
Parameter
Num.
1
2
3
4
5
BClKR, BClKX Period
6
FSR, FSX to BClKR, BClKX Setup
7
FSR, FSX to BClKR, BClKX Hold
8
DA, DB to BClKR Setup
9
DA, DB to BClKR Hold
10
12
BClKX High to DA, DB Valid
Internal Clock
External Clock
Min.
Min.
BClKR, BClKX Width High
BClKR, BClKX Fall Time
ns
ns
ns
ns
30
0
20
30
0
20
0
ns
ns
ns
30
30
30
30
30
Unit
ns
10
10
30
30
BClKR, BClKX Rise Time
Max.
125
50
50
200
80
80
BClKR, BClKX Width low
BClKX High to DA, DB-Z
..
ConditIOns: Vee = 5.0 V ± t 0%, Vss = 0 V, TA
Max.
ns
ns
ns
= 0 to 70 C .
SERIAL CHANNEL TIMING: DELAYED DATA MODE
2
RECEIVE
3
4
5
BelKR
FSR
8
9
P
DAiDB
TRANSMIT
2
3
N
5
BClKX
FSX
DAiDB
41/50
659
ST18940/41
Num.
Parameter
Internal Clock
External Clock
Min.
Min.
Max.
Max.
Unit
1
BCLKR, BCLKX Period
200
125
ns
2
BCLKR, BCLKX Width Low
80
50
ns
3
BCLKR, BCLKX Width High
80
50
4
BCLKR, BCLKX Rise Time
30
10
ns
5
BCLKR, BCLKX Fall Time
30
10
ns
6
FSR, FSX to BCLKR, BCLKX Setup
30
30
ns
7
FSR, FSX to BCLKR, BCLKX Hold
0
0
ns
8
DA, DB to BCLKR Setup
20
20
9
DA, DB to BCLKR Hold
10
BCLKX High to DA, DB Valid
11
12
ns
ns
30
ns
30
30
ns
FSX High to DA, DB Valid
30
30
ns
BCLKX High to DA, DB-Z
30
30
ns
Conditions: Vee
=
0
5.0 V ± 10%, Vss = 0 V, TA = 0 to 70'C.
SERIAL CHANNEL TIMING: ISDN GCI MODE
2
RECEIVE
4
3
5
BCLKR
7
FSR
B
9
DNDB
2
4
TRANSMIT
BCLKX
FSX
DNDB
11
42/50
660
5
ST18940/41
7.13. INSTRUCTION BUS TIMING ST 18941
Num.
Parameter
Min.
Max.
Unit
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
CLKOUT High to Address Valid
2
Data to CLKOUT Setup
40
3
Data to CLKOUT Hold
5
4
CLKOUT High to ECR Valid
5
ECR to CLKOUT Hold
5
6
Data to CLKOUT Setup
15
7
Data to CKLOUT Hold
8
CLKOUT High to HI Low Delay
-5
+5
9
CLKOUT Low to HI High Delay
-5
+5
Conditions: Vee
=
5.0 V ± 10%. Vss
30
5
=
0 V. TA
=
0 to 70·C.
INSTRUCTION BUS TIMING
CLKOUT
IAo-IA15
IDo-ID31
ECR
DATA
43/50
661
ST18940/41
8. PIN CONNECTIONS
8.1 ST18941 : OPEN VERSION
144-pin Pin Grid Array Ceramic Package
000000000000000
p 000000000000000
N 000000000000000
000
M 000
000
L 000
000
K 000
000
J 000
H 000
000
G 000
000
F 000
000
E 000
000
0 0000
000
C 000000000000000
B 000000000000000
A 000000000000000
Q
BOTTOM VIEW
1 2 3 4 5 6 7 8 91011 12131415
ST18941 PIN GRIO ARRAY 144-PIN
P
N
P
I
A
I
N
M
N
E
A1
SO?
C7
A2
SD3
C8
CS _ _ _
A3
C9
C10
A4
SBNVLSWR
SOS/SRO
A5
C11
VOO
C12
A6
A7
VOO
C13
A8
VSS
C14
A9
014
C15
A10
013
01
010
02
A11
07
03
A12
A13
05
013
A14
02
014
00
015
A15
B1
P6
E1
S06
E2
B2
B3
S02
E3
E13
B4
SOO
B5
~
E14
IRQ
E15
B6
B7
VOO
F1
B8
015
F2
B9
011
F3
B10
09
F13
B11
06
F14
B12
03
F15
B13
01
G1
B14
A15
G2
B15
A12
G3
C1
P3
G13
C2
P7
G14
C3
S05
G15
S04
H1
C4
H2
C5
~
SOTACK
C6
H3
44/50
662
N
A
M
E
VOO
VSS
012
08
04
VOO
A14
A11
A8
P1
P5
VSS
A13
A9
A7
IA1
P2
P4
A10
A6
A5
1A4
lAO
PO
A4
A3
A1
IA5
IA2
IA3
VOO
A2
AO
IA7
IA6
VSS
P
I
N
H13
H14
H15
J1
J2
J3
J13
J14
J15
K1
K2
K3
K13
K14
K15
l1
L2
L3
L13
l14
l15
M1
M2
M3
M13
M14
M15
N1
N2
N3
N4
N5
N6
N7
N8
N9
N
A
M
E
VSS
OPI1
OPIO
IA8
IAlO
VOO
OPI4
OPI5
OPI2
IA9
IA11
VSS
CUillUT
OTACK
OPI3
VSS
VSS
lA15_
OS/RO
XIAL
BR
IA12
lA14
NMI
VSS _
R/W/WR
EXTAL
HALT
INCYCLE
VSS
1028
1024
1020
VOO
VSS
l.A1;L
P
I
N
N10
N11
N12
N13
N14
N15
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
Q14
Q15
N
A
M
E
1011
105
102
101
~
1:lQL0A
~
RESET
1031
1029
1026
1023
1021
1017
1013
1012
109
106
104
JruL
ECR
LP
1030
1027
1025
1022
1019
1018
1016
1015
1014
1010
108
107
~
HOLO
ST18940/41
8.2. ST18940 : MASKED VERSION
84-pin Pin Grid Array Ceramic Package
ST18940 PLCC 84-PIN
PIN NAME
PIN NAME
B11 LP
Ai A9
A2 A7
C1 A13
C2 A11
A3 A6
A4 A4
C5 A3
A5 Ai
C6 VDD
A6 AO
C7 XIAL
A7 CLKOUT
C10~
C11 RESET
A8 ~
D1 A15
A9 l:lOLM.
A10 DS/RD
D2 AJA.
A11 HT2
D10 INT
D11 P7
B1 A12
E1 D2
B2 A10
B3 A8
E2 D1
B4 A5
E3 DO
B5 A2
E9 P6
E10 P5
B6 VSS
E11 P4
B7 EXIAL
B8 DTACL
F1 D3
B9 R/W/WR
F2 VDD
B10 VDD
F3 VSS
PIN
F9
F10
F11
G1
G2
G3
G9
G10
G11
Hi
H2
H10
H11
J1
J2
J5
J6
J7
J10
J11
K1
NAME
VSS
VDD
P3
D4
D5
D6
PO
Pi
P2
D7
D8
SD6
SD7
D9
D.11.
SDS
VDD
DPI2
SD3
SD5
D10
PIN
L11
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
LOOOOOOOOOOO
KOOOOOOOOOOO
JOO
000
00
H 0 0
00
GOOo
000
Fooo
000
EOOO
000
000
00
COOO
000
00
Booooooooooo
Aooooooooooo
NAME
SD2
VSS
D13
IRQ
RS
VSS
DPI1
DPI4
SD1
VSS
SD4
D12
D14
1 2 3 4 5 6 7 8 91011
BOTTOM VIEW
~
SDTAC~
SBlW /SWR
CS
DPIO
DPI3
DPI5
SDO
84-pin Plastic Leaded Chip Carrier
,. 000000000000000000000"
8~: R~;;:R~mli:i18:g;g!6~;;;~m~;;,~tll~B
On
0"
om
o~
0"
0"
0"
OM
ST18940 PLCC 84-PIN
P N
P
A A
A
D M
D
E
22
1 VDD
2 AO
23
24
3 Ai
4 A2
25
A3
26
5
6 A4
27
7 A5
28
8 A6
29
30
9 A7
10 A8
31
11 A9
32
12 A10
33
34
13 A11
14 A12
35
15 A13
36
37
16 A14
17 A15
38
18 DO
39
40
19 D1
41
20 D2
42
21 VDD
=,
ST18940
""
D'
N
A
M
E
VSS
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
VSS
D13
D14
D15
lBO.-
SDIACJL
SDS/SRD
RS _ _ _
SRIW/SWR
VSS
P
A
D
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
N
A
M
E
P
A
D
~D
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
CS
DPIO
DPI1
DPI2
DPI3
DPI4
DPI5
SDO
SD1
SD2
VSS
SD3
SD4
SD5
SD6
SD7
PO
Pi
P2
VDD
N
A
M
E
VSS
P3
P4
P5
P6
0<
0>
0'
0,
0-
»0
"'0
.,0
"'0
"0
""0
"0
.... 0
"'0
"0
"0
"'0
"0
"0
"0
"0
"0
"0
D>
ow
~DDD66D~~&b5MBM88M[j~
TOP VIEW
f'L
~
RESET
HOLD
HT2
VOD _
BlWLJl-.lR
~
DS1BD
l::iOLllA
DIACK
BR
XTAL
EXTAL
CLKOUT
VSS
45/50
663
ST18940/41
9. ORDERING INFORMATION
9.1. DEVICE TYPE
Part Number
Operating Temperature Range'
ST 18940 CR/PXXX"
o to + 70°C
o to + 70°C
o to + 70°C
ST 18940 CFN/PXXX
ST 18941 CR
Package Type
84 - pin Ceramic Pin Grid Array
84 - pin Plastic Leaded Chip Carrier
144 - pin Ceramic Pin Grid Array
.. XXX is the specific number associated to the customer code.
, for extended temperature range, please consult 8T sales offices.
9.2. SOFTWARE TOOLS
ST 18940 SP-PC
Software Package Including
Macroassembler
Functionnal Stimulator
Linker for PC
ST 18940 SP-VM
Same Software Package for VAX Machines
ST 18940 SPC-PC
Same Software with C-compiler for PC
ST 18940 SPC-VM
Same Software Package with C - Compiler for VAX
9.3. HARDWARE TOOLS
ST 18940 EMU
Stand - Alone Emulator
ST 18940 HDS-110
Hardware Development System 11 OV Power Supply
ST 18940 HDS-220
Hardware Development System 220V Power Supply
ST 18940 EPROM
EPROM Simulation Module for ST 18940
ST 18940-PC
PC Compatible Emulation Board
46/50
664
ST18940/41
10. MECHANICAL DATA
Pin Grid Array 144-pin - 8T18941
r-
-------"9-~---~--l
Q
i
r
-
M
1
I
PIN 1
lfuiiim
7 8,
1.27
lj,i i ~ i
Ag - Cu ALLOY
KOVAR
2.03
IB i f~,,-
_ .. ____.-'3:.--5"".5C"6~~~~
Note All dimensions in"mm"
V000541
Pin Grid Array 84-pin - 8T18940
I
T
PIN 1
Note, All dimensions in "mm"
VQ00540
m
~I
SGS·1lI0MSON
UIIlll©HiI@~~Il©1i'HiI@illl©i!l
47/50
665
ST18940/41
11. DEVELOPMENT TOOLS
11.1. DESIGN PROCEDURE
The design of a digital signal processing application
using the ST18940/41 is supported by a complete
range of dedicated software and hardware tools including macroassembler, linker, high-level simulator and a C compiler and optimizer.
Additional hardware design tools include:
1 - stand alone emulation card ST18940-EMU
2 - multiprocessor hardware development
system ST18940-HDS
3 - EPROM emulation module ST18940EPROM
4 - PC compatible card ST18940-PC.
11.2. SOFTWARE TOOLS
All the development softwares run on the most common computers, such as IBM-PC XT, AT, under MSDOS, VAXR under VMS, UNIXR or ULTRIX operating systems.
The macroassembler supports conditional assembly, high level language facilities for loop definition
and generates all the files for simulation, emulation
and PROM programming.
The functional simulator provides step by step execution, break on address and data values, access
to all intemal registers and interface to I/O files
(ADC, DAC, test inputs).
The linker provides modular programming facilities.
The library consists of macros, basic DSP routines
etc ... and provides additional help to user's for their
applications.
The C language compiler offers high-level language
facilities which meets the advanced requirements
(parallelism, pipe-line, three computation modes,
32-bit instruction set) to the ST18940.
11.3. HARDWARE TOOLS
All the hardware tools are designed to provide ease
of use and minimum learning time by means of a
menu driven interface and DSP specific emulation
features.
ST18940 EMU and ST18940 HDS have in common:
_ Full speed emulation of ST18940 and
ST18941
_ Use of internal or external clock
_ 28 breakpoints (stops at defined addresses)
_ 8 conditional breakpoints (stop after N ad-
48/50
666
dress X and M address Y)
_ Realtime trace of internal resources
_ Emulation probes (for ST18940 - 41)
_ Menu driven operation (about 100 commands)
_ Resident Assembler/Disassembler with full
screen editor
_ Symbolic debugging
_ Direct link with PROM programmers
_ Direct link with host (KERMIT protocol)
Emulator specific features:
The ST18940 EMU is a low cost, stand-alone emulator providing advanced emulation features such
as real-time trace. It can be driven via a RS232C
link by a terminal or an IBM-PC R and offers:
_ 3K program memory
_ 4K x 16-bit data RAM
_ A wire-wrapping area
_ Full speed 100 ns cycle emulation
_ 2 RS232C serial ports
_ Complex conditions break-points
Hardware development station features:
The ST18941 HDS is a hardware development station, aimed at the development of multiprocessor
applications. Up to four pairs of emulator board/logic analyzer board can be combined to match exactly the user's needs:
_ CMOS memory for backup of configuration
_ 64K x 32 program memory
_ 64K x 16 data RAM (mapping on a word basis)
_ A logic analyser with:
'2K x 119 bits for trace of ST18940-41 bus and 15
external inputs
'Synchronous analyser on program and local buses
'Asynchronous analyser on system bus or external
inputs
'Triggering conditions (Address bus with count, data bus external branch inputs, mailbox exchanges,
external inputs).
EPROM module:
The ST18940 EPROM is a small-sized module
which uses the perfect compatibility between
ST18940 and ST18941. The module uses a
ST18941 and fast EPROM memories to emulate in
real time a ROM masked ST18940 during prototyping or field tests to minimize hardware developments. The module is plug - and function-compatible with ST18940.
ST18940/41
APPENDIX A - BENCHMARKS
Execution Time
1 DOns Instruction
Cycle
Memory Size
(words)
Prgm + coef.
20 Tap FIR Filter
2.4~s
6 + 20
64 Tap FIR Filter
6.8~s
6 + 64
67 Tap FIR Filter
7.1~s
6 + 67
20 Tap Double Precision FIR Filter
7.6~s
26 + 40
3x3 Bidimentional FIR Filter
8.5~s
8+9
20 Tap Adaptive FIR Filter
4.6~s
12
8 Pole Cascaded Canonic Biqual IIR Filter (4x)
2.4~s
13 + 20
8 Pole Cascaded Canonic Biqual IIR Filter (5x)
2.8~s
13 + 20
8 Pole Cascaded Transpose Biqual IIR Filter
3.3~s
15 + 20
Dot Product 2 x 2
0.6~s
6
Matrix Mult (2x2) Times (2x2)
1.4~s
14
Matrix Mult (3x3) Times (3x1)
FFT 64 pts
1.5~s
15
90.3~s
45 + 64
FFT 256 pts
500.1~s
177 + 256
FFT 1024 pts
3.15ms
234 + 512
8x8 Discrete Cosine Transform
4.75ms
650 + 12
49/50
ST18940/41
APPENDIX B
MASKING INFORMATION
The information required by SGS-THOMSON
Microelectronics to realize a customer masked version of the ST18940 must include program ROM
content and coefficient ROM content. They can be
transferred on EPROMS, 5" 1/4 floppy disks, magnetic tapes (VAXIVMS format) or by link to SGSTHOMSON Microelectronics. This must be done in
conjunction with your local sales office or representative indications.
the ROM content code will be generated and returned to the customer with a listing verification form.
The listing should be carefully checked and the approval form completed, signed and returned to SGSTHOMSON. The returned verification form is the
contractual agreement for generation of the customer masks and batch manufacturing.
VERIFICATION MEDIA
All original pattern media are filled for contractual
purpose and are not returned. A computer listing of
These samples will be engineering samples and
must be kept by user as reference parts.
50/50
668
VERIFICATION UNITS
Ten engineering samples containing the customer
ROM patterns will be sent for program verification.
TS68930/31
DIGITAL SIGNAL PROCESSOR
•
•
•
•
•
•
•
•
•
•
•
•
160ns INSTRUCTION CYCLE TIME
PARALLEL HARVARD ARCHITECTURE
SEPARATED PROGRAM AND DATA BUSES
THREE DATA BUSES STRUCTURE
DUAL EXTERNAL BUSES
ONE CYCLE 16-BIT R/W OPERATION ON EXTERNAL DATA MEMORY
THREE DATA TYPES: 16-BIT REAL, 32-BIT
REAL, 16 + 16-BIT COMPLEX
EXTERNAL MASKABLE INTERRUPT
COMPLEX MULTIPLIER
256 x 16-BIT INTERNAL RAMs, 512 x 16-BIT INTERNAL COEFFICIENT ROM
1.28K x 32-BIT WORDS OF INTERNAL PROGRAM ROM
NO FUNCTIONAL DIFFERENCES BETWEEN
TS68930 ROM VERSION AND TS68931 ROMLESS VERSION
32 external instruction memory and allows a total
realtime emulation of the TS68930. It is also particularly well adapted for applications where large
program is required or for low quantities.
DEVELOPMENT SYSTEMS
The TS68930 is supported by a complete set of
hardware and software tools for applications development. Software packages include assembler, linker and simulator on VAX and PC as well as a high
level "C" compiler and optimizer.
Hardware tools include a stand-alone emulator,
eprom emulation module and a powerful multiprocessor development station.
DESCRIPTION
The TS68930/31 HMOS digital signal processors
are members of SGS-THOMSON family of general
purpose DSP's fully software and hardware compatible with other members of the family.
TS68930
P
DIP 48
(Plastic Package)
By virtue of their highly parallel architecture, these
digital signal processors are well suited to a wide
range of applications including those requiring operations on complex numbers.
Typical examples are found in telecommunications,
modems, image and speech processing, high
speed control, digital filtering, sonar and radar applications.
They are able to execute simultaneously within 160
ns an ALU function, a Multiplication, two Read and
one Write operations with associated address calculation.
The on-chip large memory resources and mUltiprocessor direct interface allows the development at
the lowest cost/complexity of high performance applications. The TS68931 is the ROM less version of
the TS68930. In addition of the TS68930 features,
it provides the capability of addressing up to 64K x
March 1989
TS68931
R
PGA84
(Pin Grid Array Ceramic)
For pin connections and order codes,
please see inside
1/53
669
TS68930/31
TABLE OF CONTENTS
Page
1.
BLOCK DIAGRAM
5
2.
PIN DESCRIPTION
6
FUNCTIONAL DESCRIPTION
8
3.1
8
3.
General architecture
3.2 Operating unit
8
3.3 Data memory blocks
12
3.4 Sequencer block
13
3.5 Inputs I Outputs
14
3.6 Other resources
22
4.
TYPICAL APPLICATION CONFIGURATIONS
24
5.
INSTRUCTION SET
28
6.
ELECTRICAL SPECIFICATIONS
42
7.
PIN CONNECTIONS
47
8.
ORDERING INFORMATION
48
9.
PACKAGE MECHANICAL DATA
48
TABLE OF APPENDICES
Page
2/53
, 670
A.
DEVELOPMENT TOOLS
49
B.
MASKING INFORMATION
50
C.
SUMMARY OF RESSOURCES/FUNCTION
52
TS68930/31
TABLE OF FIGURES
Page
Figure 1 : Input/output pins.
6
Figure 2 : ALU block diagram.
10
Figure 3 : Multiplier efficiency.
10
Figure 4 : Data memory blocks.
13
Figure 6 : Dual bus interface - system configuration.
15
Figure 7 : Local bus description.
16
Figure 8 : Separate local buses.
16
Figure 9 : System bus description.
17
Figure 10 : Mailbox connection.
18
Figure 11.A : Mailbox exchange - Example 1.
19
Figure 11.B : Mailbox exchange - Example 2.
20
Figure 12 : Reset timing.
23
Figure 13: Configuration example TS68930 + RAM + MAFE.
24
Figure 14 : Configuration example TS68930 + RAM.
25
Figure 15: Configuration example TS68930 + RAM + MAFE.
26
Figure 16 : Interfacing CROM, IRAM to TS68931.
27
Figure 17 : OPIN calculation instruction with indirect addressing.
30
Figure 18: OPOI calculation instruction with direct addressing.
31
Figure 19 : OPIM calculation instruction with immediate operand.
32
Figure 20 : ASR, LSL, LSR, ROR shift instructions.
33
Figure 21 : BRI immediate branch instructions.
34
Figure 22 : BRC computed branch instructions.
35
3/53
671
TS68930/31
Page
4/53
672
Figure 23 : SVR data transfer instructions.
36
Figure 24 : INI initialization and control instruction.
37
Figure 25 : Clock and control pins timing for internal machine cycle.
42
Figure 26 : Local bus timing diagram
43
Figure 27 : System bus timing diagram.
44
Figure 28 : Instruction interface timing diagram.
45
TS68930/31
1. BLOCK DIAGRAM (TS68930)
L-BUS
16
R·BUS
~CJ
16
I-----f+-J.- CS
16
16
16
:1---+H-FfS
l---+H_SR/W
16
I----f+-j.-
SYSTEM
BUS
SOs
......=+-r-f-t-++ ADO-AD7
1-"'l--H_4+-
~M1J
~~~~-4+-~~
~--~~~
LOCAL
8US
DO-015
16
BRANCH CONDITIONS
M88TS68930-01
DEFINITION OF ACRONYMS
L-bus
: Left data bus
CROM
R-bus
: Right data bus
XO, X1 , X : Addressing registers XRAM
: Coefficient ROM
M
: Multiplier input register
YO, Y1, Y : Addressing registers YRAM
N
: Multiplier input register
CO, C1
: Addressing registers CROM
P
: Multiplier output register
EO, E1
: Addressing registers ERAM
BS
: Barrel Shifte r
XACU
: Address calculation unit XRAM
ALU
: Arithmetic and Logic Unit
YACU
: Address calculation unit YRAM
D
: ALU output register
ECACU
: Address calculation unit CROM & ERAM
RC
: Replace Code register
RIN
: Input register of mailbox
STA
: Status register
ROUT
: Output register of mailbox
FIFO
: ALU output FIFO
AMR
: Access mode register
A
: ALU accumulator
IR
: Instruction register
B
: ALU accumulator
PC
: Program counter
Z- bus
: Result data bus
RAR
: Return address register
T
: Transfer register
SEQ
: Sequencer
XRAM
: X Data RAM
LC
: Loop Counter
YRAM
: Y Data RAM
IROM
: Instruction ROM
5/53
673
TS68930/31
2. PIN DESCRIPTION
Figure 1 : Input/Output Pins.
1----I
----------------
r------ -------------
AO-A7 *
AoO·Ao?
SYSTEM
control
& handshake
BUS
AS-An
CS
00-0?
RS
OS-015
SR/W
SoS
oTACK (I)
BA (1
LOCAL
RIW orWR
IRO
os or Fill
BUS
control
TS68930
RESET - - - - - - j
CLKOUT
BSO
BRANCH
CONDITIONS
BS1
Voo
BS2
VSS
BE3
EXTAL
BE4
XTAL
&
INTERRUPTS
BE5 (1)
BE6 (I)
------1
,
HALT
INCYCLE
CC
MC
CAO-CA9
TS68930
100-1031
IAO-IA15
,
--
______ 1
M88TS68930-01
Notes: 1. these pins are shared and software programmable: BE5/DTACK, BE6/BA
2. AO-A? and ADO-AD? may be multiplexed.
6/53
674
TS68930/31
LOCAL INTERFACE
Name
Pin
Type
Function
Description
D (0:15)
I/O
Data Bus
A (8:11)
0
Address Bus
Can be concatenated or separate D (0:7), D (8:15).
High order addresses for local interface.
DS/RD
0
Data Strobe/read
Synchronizes the transfer on local bus/read cycle.
R/W/WR
0
Read/write/write
Indicates the current bus cycle state/write cycle.
CLKOUT
0
Clock Output
CLKOUT Frequency is half input clock frequency.
SYSTEM INTERFACE
Name
Pin
Type
AD (0:7)
I/O
Function
Description
System Data Bus
or Local Address
Bus
System data bus for exchanges between the processor and a host via
an internal mailbox or local address bus for external RAM.
CS
I
Chip Select
Used by a host to gain access to the mailbox and system bus.
RS
I
Register Select
Used by a host to gain access to the mailbox and system bus.
SDS
I
Data Strobe
Synchronizes the transfer on the system bus.
SR/W
I
Read/write
Indicates the current system bus cycle state.
Indicates that the processor has recognized it is being accessed.
DTACK
0
Data Transfer
Acknowledge
BA
0
Bus Available
Indicates availability of the sytem bus to host.
IRQ
0
Interrupt Request
Handshake signal sent to the master to gain access to the mailbox.
EXTERNAL BRANCH CONDITIONS
Name
Pin
Type
Function
Description
BS (0:2)
I
Branch on State
External Conditions
BE (3:4)
I
I
1/0
1/0
Branch on Edge
External Conditions. Falling edge is memorised and reset when tested.
BE5/BA
BE6/DTACK
BE5 shares pin with ~
BE6 shares pin with DTACK.
OTHER PINS
Name
Pin
Type
EXTAL
I
Clock
Crystal input pin for internal oscillator or input pin for external
oscillator.
XTAL
I
Clock
Together with EXTAL it is used for crystal oscillator. If external
oscillator is used, pin XTAL is not connected.
Voo
I
Power Supply
Vss
I
Ground
RESET
I
Reset
Function
Description
7/53
675
TS68930/31
INSTRUCTION INTERFACE AND SYSTEM CONTROL INTERFACE (ST18931 only)
Name
ID (0:31)
IA (0:15)
CA (0:9)
HALT
INCYCLE
Pin
Type
I/O
0
0
I
0
Function
Description
Instruction Data
Instruction Address
Coef. ROM Address
or External RAM
Address
Instruction Bus. 32 Bit Data
Instruction Address
External Coefficient ROM Address 10 Bit OR External RAM Address
(9-bit address - output enable signal)
(8-bit address)
Halt Signal
Halts the processor. This signal freezes the program and loop
counters.
Instruction Cycle
Clock
A transition from low to high indicates that a new instruction is
processed.
3. FUNCTIONAL DESCRIPTION
3.1. GENERAL ARCHITECTURE
The TS68930/31 architecture is based on an innovative architectural concep developped by SGSTHOMSON Microelectronics.
The TS68930 is compatible with the ST18930 and
ST18940 other members of SGS-THOMSON digital signal processors family.
The TS68930 confirms the efficiency of a highly parallel and pipelined operation using a true Harvard
memory space and bus structure.
The block diagram shows four main blocks:
· The sequencer block
· The operating unit (ALU, Multiplier and Barrel Shifter)
· The data memories
· The inputs/outputs
These four blocks can be considered as four independent units working in parallel and communicating through a network of 16/32 - bit buses.
By taking advantage of the 32, - bit wide instruction
bus, the TS68930/31 are able to execute simultaneously the following operations during each machine cycle:
· Read two operands from internal or external
memory
All instructions are executed in a single cycle time
except branch instructions.
Some additional features give the TS68930/31 extremely powerful performances. They provide three
operating modes (real, complex and double precision) dynamically set by software and user transparent.
In complex mode, the hardware multiplier provides
(16 + 16 - bit) results from 2 x (16 + 16 - bit) inputs
each machine cycle.
(12.5 - million multiplications per second).
The ALU, reinforced by a barrel shifter, provides 27
basic arithmetic and .Iogic functions.
Three dedicated calculation units control the four
data memory spaces.
A 1.28K x 32 program ROM (for the TS68930) allows most of digital signal processor applications
possibilities, using the efficiency of the code and
architecture. The following sections will detail all the
hardware blocks of the TS68930/31 and demonstrate its software performances provided by the high
level of parallelism in the operations.
3.2. OPERATING UNIT
One of the most useful features of the TS68930 is
to provide the user three operating modes which can
be dynamically set by software.
These three modes are:
· Execute a multiplication
· REAL 16-bit
· Perform an ALU operation
· COMPLEX 16-bit real + 16-bit imaginary
· Write a result into internal or external memory
· DOUBLE PRECISION 32-bit
· Post modify three pointers independently
Thus, the DSP is seen by the user as a sta~dard
16 - bit real or complex machine or a 32-bit real machine. All operating units and working registers are
automatically adjusted by the processor to the right
length. In real mode, all instructions are executed in
· Store data into the transfer register
In addition, data exchanges through mailbox occur
concurrently and independently of internal operations.
8/53
676
TS68930/31
a single machine cycle. In complex and double precision mode, the instruction time is doubled.
In all modes, the number representation used is signed 2's complement.
3.2.1. 16/32 - Bit ALUIAccumulator (fig. 2). The
ALU can be seen either as a 16 or 32 - bit ALU. The
ALU is loaded on the right side by the R - bus or by
the A or B accumulators.
On the left side, the operands always access the
ALU through the barrel shifter, coming either for the
L (left) - bus or the hardware multiplier output register P.
The result of an ALU operation is automatically written in the 0 register and, if required into the Accumulator or FIFO. The ALU provides a range of 27
codes for operations which execute in a single machine cycle. They include arithmetic and logic operations, shift and rotate operations.
The high degree of parallelism of the TS68930/31
processor allows more combinations than previous
generation DSP devices which require a more complex instruction set.
The complete list of ALU codes and description is
given in 3.8.2.
3.2.2. Barrel Shifter. The 16-bit barrel shifter located on the left side of the ALU performs alilogic/arithmetic shifts and rotations. It is used for
normalization and formatting of data in floating point
operations and bit or byte manipulations. Two types
of operations are allowed in the barrel shifter.
_ Operations defined by ALU codes (shifts of 1 or
8 bits) see 3.8.2
_ Operations defined by specific dedicated instructions:
ASR (0 -715) arithmetic shift right by N (0 < N:<:: 15)
LSR (0 -715) logical shift right by N (0 < N:<:: 15)
LSL (0 -715) logical shift left by N (0:<:: N:<:: 15)
ROR (0 -7 15) rotation right by N (0 < N :<: 15)
These codes allow all types of shifts from 0 to 15
bits.
3.2.3. Multiplier. The multiplier executes a 16 x 16bit multiplication with a 32-bit result at each machine
cycle. The operands are loaded into the M and N registers and the result of a previous multiplication is
written in the P register during the same cycle.
The pipeline structure makes the multiplication result available with a delay of two instruction cycles.
The multiplier provides a multiplier overflow flag
OVFM which is memorized in the status register in
complex mode only (see 3.2.4).
The efficiency of the parallel pipeline operation of
the multiplier is shown in fig. 3.
3.2.4. Associated registers. Registers A and B
store the results from the ALU. They are sized according to the mode of operation. They also provide
capability to feedback the ALU for a new operation
with the ALU result of a previous operation.
Register FIFO.
The 4 x 16-bit FIFO is used for intermediate storages. Initialization of the FIFO (empty FIFO) can be
made by an INI instruction.
A result loaded in FIFO at instruction N is available
at least at instruction N+2 in real mode and N+ 1 in
complex and double precision modes.
Register RC (Replace Code register).
This register can dynamically load an ALU code to
be executed by the processor from the data memories. It allows data control program sequencing without the use of a systematic test instruction. For instance, in FFT calculation, scanning mayor may not
be necessary during a pass.
9/53
677
TS68930/31
Figure 2 : Alu Block Diagram.
L-BUS
A-BUS
• 4 Inputs
giving access to 10 possible sources:
XRAM. YRAM.CROM. ERAM.
P, T, RIN, A, B, FIFO
• 5 Destinations: A, B, D, FIFO, Z BUS
• R side by Accumulators
L side by T registers
• 27 operations: including Arithmetic,
Logic, Shifts,
With 3 modes of execution:
Real
Complex
Double precision
• Saturation mode to prevent overflow
• The status register gives information
on the results of operations.
• The Replace Code Register allows dynamically
changing the ALU operation code with a data.
MULT
The ALU formats are: 16-bit in Real mode
16 + 16-bit in Complex mode
32-bit in Double Precision mode
Figure 3: Multiplier Efficiency.
L~BUS
R~BUS
11
I).
MIN
X
c---ll-
Y
X2
R
X1
XO
A
Y2
Y1
YO
A
~
Multiplier
_il
M
-"'C2
C1
CO
R
M
C
R
0
M
BS/ALU
II
Z~BUS
--"X",O~--"X,,-1~--"X=-2~ -
---,C",O,--~-",C"-1~---,c",2--+i -
{f __ ~
If --~
,
~!:!PO,---;-'--,P:01--;--,P,,,2,--~ - -
JJ--,-------EL---,
~~Y~O-+--,Y~1~~Y~2~:, -{J--~
,
,
5
6
7
8
All components are always busy
10/53
678
X (instruction number)
M88TS68930-04
TS68930/31
This register is 6-bit wide and is loaded by the 6 MSB
of L-bus :
I
RC
o
5
L-BUS
15
14
13
12
11
10
I-BUS
17
18
19
20
21
22
I
Transfer register T.
The transfer register provides a direct transfer capability between L-bus and Z-bus.
It can either be source or destination for the two
buses.
Its various uses include:
* Loop back to the multiplier in one cycle
Bit 1 to 5 contain the executable ALU code corresponding to the bits 121-117. Bit 0 allows the choice of
ALU output destination (A or B register).
Its contents is defined by three ALU codes: (see 5.2.)
ALU
Function
Code
RCR
RCE
RCER
Load ALU control code in register RC.
* Temporary register between memory and ALU
* Temporary register between memory and multiplier
* Operati()n between two accumulators in the same
instruction
* Memory to memory transfer
* Saving program counter (in a branch instruction)
Execute ALU code contained in register RC.
Execute ALU code contained in RC and
load new ALU code in RC.
Status register (STA).
This register provides a status of the ALU, operating
and addressing modes, and multiplier. It is divided
into two sub-registers:
CCR (Condition Code Register)
STR (State Register)
A detailed description of this register is given in
85.4.
11/53
679
TS68930/31
The status register content can be saved using instruction SVR.
The condition code register CCR can be read in
OPIN instruction and itcan be loaded via L-bus (ALU
code LCCR).
The state register STR can be programmed by an
INI instruction or an SVR instruction (except EF bit).
3.3. DATA MEMORY BLOCKS.
3.3.1. Available spaces. The TS68930 provides
four separated memory spaces (see fig. 4)
· two internal RAMs of 128 x 16-bit (YRAM and
XRAM)
· one internal data ROM (independent from the program ROM) of 512 x 16-bit (CROM) (ST18930 only)
· one optional external memory (ERAM) of 4K x 16bit accessible in one single instruction cycle in exactly the same way as internal memories.
This external memory is controlled by an Intel or Motorola type control interface and offers full speed, fully transparent, Read and Write operations.
Slower external memories or peripherals can be accessed by using slow exchanges modes.
However slower external memories or peripherals
can be accessed by using slow exchanges mode.
The powerful instruction set and the Harvard architecture allows many combinations of simultaneous
memory accesses. The only forbidden situations
are:
_ read and write access is the same RAM within the
same instruction
_ simultaneous access to CROM and ERAM
3.3.2. Address Calculation Units. Three different
Addresses Calculation Units are available.
XACU is associated with XRAM
YACU is associated with YRAM
ECACU is associated with the ERAM and the
CROM
3.3.3. Addressing modes. The TS68930 provides
four addressing modes:
_ Direct addressing
_ Immediate operand
_ Indirect addressing with or without post modification of the pointers
_ Circular addressing (also called virtual shift
mode) for XACU and VACUo
The circular addressing mode is of particular interest in digital signal processing typical operations
like convolution algorithms used in FIR filters. It has
the same function as a shift register but does not
move the data stored.
For this feature, three pointers are used in the memory space chosen (X or V). The current address is
given by a specific X pointer shifting repetitively between two limits XO and X1 (respectively Y, YO and
Y1).
The circular mode is declared in the status register
STA (see 3.2.4) by an INI instruction.
3.3.4. Pointers. The TS68930 offers a large number of address pointers for each memory space:
_ XO, X1 and X for XRAM
_ YO, Y1 and Y for YRAM
_ CO, C1 for CROM
_ EO, E1 for ERAM
The pointers Xi, Vi, Ci and Ei can be independently
incremented, decremented or maintained. The two
pointers X and Yare specific to the circular addressing mode. The pointers can be loaded with new addresses (constant or computed values) through
Z -bus. In this case, the value of unused Z-bus MSBs
are irrelevant. The unused bits are set to 1.
3.3.5 Odd/Even addresses. In complex and double precision modes, the processor automatically
generates the two addresses necessary to store
one data word (even first, then odd addresses).
The user can reverse this order by setting to 1 the
ADOF bit with the INI instruction (referto OPCODE).
This feature is available independently for XRAM
and YRAM.
COMPLEX WORD
DOUBLE PRo WORD
Even Address
Real Part
Lower Part
Odd Address
Imaginary Part
Upper Part
12/53
680
TS68930/31
Figure 4 : Data Memory Blocks.
full speed, and
fully transparent
read and write
operations
M88TS68930·05
3.4. SEQUENCER BLOCKS
Z
Zero
3.4.1. Sequencer. The purpose of the sequencer is
to generate the next instruction address.
OVF
Overflow
The sequencer takes into account the current operating mode of the TS68930/31 to execute this task.
The instruction is executed in one cycle time in real
mode and two cycles time in complex or double precision mode.
The linear address program generation may be interrupted by several means hereunder described.
A. Execution of a branch instruction
_ unconditional branch always.
_ seven ALU conditions flagged from the status
register:
SR
Sign real
SI
Sign Imaginary
CR
Carry Real
CI
Carry Imaginary
MOVF Memorized overflow MOVF
is reset when tested by
branch instruction.
_ three external conditions on state of pins BSO,
BS1, BS2 (the pins BSO, BS1, BS2 can also
be used as interrupt pins if enable interrupt is
programmed).
_ four edge sensitive external conditions on pins
BE3, BE4, BE5, BE6. The falling edges of
BE3-BE6 are memorized internally and reset
when tested by the branch instruction. The external test conditions are used to synchronize
different processes.
_ The mailbox flag RDYOIN indicating mailbox
availability.
All the branch conditions can be tested on true or
false conditions.
13/53
681
TS68930/31
B.
Subroutine call
C. Loop execution
One of the most powerfu I featu res of the
TS68930/31 is its ability to repeat the execution
of several instructions with very straightforward
commands. The loop execution is set with the
instructions: REPEAT, BEGIN, END which respectively define the number of loops, the beginning of loop and its end. The DSP will then
manage all the necessary pointers to execute
the loop with no overhead time (see 3.4.4.).
3.4.2. Instruction ROM. The TS68930 instruction
ROM has a capacity of 1280 words of 32-bit available for the user. The ROM code is defined following
the user's information (see appendix C for masking
information). The TS68931 does not provide an onchip ROM memory, but can address an external64K
program memory space in a single cycle.
3.4.3. Program Counter. The program counter is a
16-bit wide Register ; 12 bits are used in the
TS68930 (ROM version).
3.4.4. Loop Counter. The loop counter does considerably increase the efficiency of the processor in
repeated calculations, very commonly used in digital signal processing.
14
13
12
11
Three counters define a hardware loop:
_ LCI Instruction Loop Counter (4-bit). Counts the
number of instructions to be executed in the loop.
_ LCR Repeat Loop Counter (8-bit). Gives the number of times the loop will be repeated (can be loaded by a calculated value).
_ LCD Delay Loop Counter (3-bit). Gives the delay
between the declaration and the start of a loop.
The loop counter content can be saved (SVR instruction) with the format shown in table below:
The loop counter is set by the three pseudo-instructions Begin, Repeat and End in the Macroassembier.
The loop counter is frozen during an interrupt routine.
On the TS68931, a HALT freezes the state of the
loop counter. A RESET signal resets the loop counter.
3.4.5. Return Address Register. The JSR instruction allows one level of subroutine nesting with automatic saving of the PC on to the Return Address
Register. Multiple Level of subroutine nesting can
be implemented in RAM using either of the two pointers as stack pointer.
10
Lei
LCD
LeR
LOOP
COUNTER
14
13
12
11
10
M88TS68930-06
3.5.INPUTS/OUTPUTS
A very important feature of a signal processor is its
ability to be inserted in a complete system including
memories, other processes, analog interface circuits.
Basically, the external world seen by a TS68930/31
can be divided in two main sections: communications with its own local resources (peripheral, memories, converters) and communications with
14/53
682
control processor, either microcontroller or master
DSP in a multiprocessor application.
To communicate with its local resources, the
TS68930/31 uses its local bus.
To interface with a host, the TS68930/31 uses its
system bus and branch capabilities.
However, the local and system bus configuration is
flexible and allows many combinations forthe architecture of a system based around a TS68930/31.
TS68930/31
3.5.2. Dual bus interface. In order to provide the
maximum flexibility, the TS68930/31 provides two
buses. One is called the system bus and is found on
pins ADO-AD?, the other one called local bus is situated on pins DO-D15. The system bus provides a
very straightforward interface to a host controller,
while the local bus allows the TS68930/31 to make
an efficient use of external resources such as memories, analog interface circuits etc ... This dual bus
structure allows many combinations of circuits
where the TS68930/31 can act in different ways:
Fig. 6B as a processor with its associated memory
Fig. 6C as an intelligent peripheral having its own
external memory and connected to a microprocessor.
It must be emphasized that, in most configurations,
the connections are absolutely direct and do not use
any external additional logic.
Fig. 6A as a microprocessor peripheral
Furthermore, thanks to the dual bus structure, several TS68930/31 can be very simply combined together in multiprocessor applications, thereby
directly increasing the processing power.
Figure 6 A : HOSTITS68930.
Figure 6 B : TS68930/RAM.
00-07
ADO-AD?
DATA
00·015
DATA
8
--
16
4Kx16
CS.RS
TS68930
TS68930
50S or SRD,SRIW or SWR
OS or R1S RJW or WR
RAM
A8-A11
HOST
ADO·AD?
IRO.DTACK.BA
TS68930
SYSTEM BUS
HOST
(FULL MASTER)
LOCAL BUS
(SLAVE)
RAM
TS68930
M88TS68930-07
M88TS68930-08
Figure 6 C : HOSTITS68930/RAM.
BA
~
DO-D7
-~
,--L--ADO-AD?
HOST
,DATA
8
T868930
16
os or RD,RtW or WR
SDS or SAD,SRIW or SWR,CS,RS
IRQ,DTACK
'------
~
HOST
(TEMPORARY MASTER)
SYSTEM BUS
RAM
AS-All
T868930
(PSEUDO SLAVE)
I
ADO-AD?
~
LOCAL BUS
T868930
RAM
M88TS68930-09
3.5.3. Host/slave configuration. The processor
acts as a host on its local bus and as a slave on its
system bus.
In configurations in which the TS68930 accesses
external RAMS on its local bus, pins ADO-AD? can
be used to provide 8 LSB addresses, while A8-A 11
provides 4 MSB addresses to the RAM.
In this case, the TS68930/31 prevents the host from
using the system bus and is then called a pseudoslave.
Since the host can only temporarily access the system bus it is defined as a temporary master. That
mode of operation is software controlled through the
Access Mode Register (AMR) (see 3.5.?).
On the TS68931 the pins CAO-CA?, which present
the least significant bits of external ERAM/CROM
addresses can be connected to that RAM in place
of system bus pins ADO-AD?
15/53
683
TS68930/31
3.5.4. Local bus. The local bus uses two software
programmable signals to control the data on 00015.
OS : Data Strobe. Synchronizes the transfer on local bus.
RlW: Read/Write. Indicates the direction of the data.
These signals are used for Motorola-like bus compatibility.
RD : Read. Read clock pulse.
WR : Write. Write clock pulse.
These signals are used for Intel-like bus compatibility.
A8-A11 : Address bits (4)
ADO-AD7 : Optional additional address bits (8)
Figure 7 : Local Bus Pin Description.
1 - - - - - - 00-07
J
16 bit data bus can be concatenated or separate
1-------
08-015
1 - - - - - A8-A11
T868930
1 - - - - - RNi or WR
]
4 address bits
J
Control bits. Can be chosen among 2 sets
1 - - - - - - OS or R5
1------
ADO-A07
]
Additional adress bits (in pseudo-slave mode)
M88TS68930-10
The four address bits of the local bus are usually
sufficient to address peripherals. When an access
to external RAM is necessary with the TS68930/31 ,
the address bus can then be extended by using the
ADO-AD7 pins of the system bus as address lines.
If an external peripheral or external memories are
too slow to answer in one machine cycle, the
TS68930/31 can be programmed to execute an external access in 2 cycles using the bits ESO and ES1
of Access Mode Register (see 3.5.7.).
This mode is particularly useful for peripherals such
as data converters, or dedicated interface like the
MAFE chip set (Modem Analog Front End) from
SGS-THOMSON.
The local data bus can also be splitted into two independent 8-bit buses. This is used in a mUltiprocessor architecture when a pseudo-slave uses the
system bus to transfer its own RAM addresses on
00-07 (fig. 8). By dividing its local bus, the temporary master can remain a full-master on bus 08-015
and does not require a bus transceiver on 00-07.
The selection between the two buses is then made
by the addresses A 1O-A 11 as indicated in fig. 8.
Figure 8 : Separate Local Buses.
~
TO OTHER
Do - D7
TS68930
MASTER
A10
0
0
Selection
High Impedance
0
1
High Impedance
Selection
1
0
High Impedance
Selection
1
1
High Impedance
Selection
-L.
ADO-AD?
.-----------TS68930
RAM
PSEUDO
SLAVE
'------
16/53
684
D8 - D15
A11
SLAVES
D8-015
DATA
'------
M88TS68930-11
TS68930/31
3.5.5. System Bus: The system bus uses two signals to control the data on ADO-AD?
The system bus mode of operation is Motorola like.
CS/RS
Mailbox Control Signal. Also used by a host to gain access to the bus.
SR/W
SDS
System ReadlWrite
System Data Strobe
IRQ
Handshake Signal (see 3.5.6)
DTACK
Data Transfer Acknowledge. Compatibility with 68000 family. Is programmed by Access
Mode Register.
BA
Bus Available. The TS68930/31 is not currently using the system data bus to generate
addresses. SA is also programmable by the Access Mode Register.
l
Generated by an external processor (host).
Figure 9 : System Bus Description.
8 bit data bus
[ ADO·AD7
cs
AS
SRIW
Control pins
TS68930
SDS
DTACK
BA
IRQ
M 88TS68930-12
RDYOIN).
protocol signal description.
RDYOIN.
Intemal flag indicating the status of the mailbox
= DSP has access to the mailbox
1 = host has access to the mailbox
b.
The host after testing IRQ, knows that it can access the mailbox. The access to the bus (which
can be currently used by the DSP as a local address bu.§lmust be requested by reading the
address CS = 0, RS = O.
c.
The DSP then answers back by asserting IRQ
high. (In pseudo-slave mode, the DSP is halted). The host now has full control of the bus
and mailbox.
o
a.
b.
RDYOIN is set by the DSPand reset by the host.
That means that the DSP gives the mailbox to
the host when it finishes using it and vice-versa.ln no case can the hostorthe DSPtake possession of the mailbox, it can only wait for the
other to give it back.
The TS68930/31 sees RDYOIN as a flag:
_ tested by a branch instruction
_ set to 1 by an initialization instruction in order
to give the availability of the mailbox to the
host.
IRQ.
Handshake signal enabling the host to gain access
to the mailbox.
a.
IRQ is asserted low by the DSP to indicate the
availability of the mailbox (at the same time as
When the host has corlJ.QLeted the exchange it
generates the address CS = 0, RS = 1 and the
DSP resets RDYOIN.
HALT (internal).
The internal halt has the following effect on the circuit:
_ the program is stopped at the end of the current instruction, the program and loop counter are frozen
_ a NOP is executed
_ no more addresses are generated on the system
bus
17/53
685
TS68930/31
3.5.6. Mailbox. The mailbox is a set of registers
which interface with the system data bus. The mailbox is divided in two parts:
_ RIN (3 x 8 bit register) : This register is read internally by the TS68930/31 on the upper byte of Lbus (L8-L 15) and written externally from the system bus. After each write or read operation the
data is shifted by one byte.
_ ROUT (3 x 8 bit register) : This register is written
internally with the upper byte of the Z-bus (Z8Z15) and read externally on the system bus. After each operation (read or write), the data is shifted by one byte.
Figure 10: Mailbox Connection and Protocol.
DO-D15i----------iADO-AD7
DS
-L·BUS
1
RIWf---------iSRNJ
SDS
RIN
ROlIT
- - - Z-BUS
MAILBOX
TS68930
SLAVE
HOST
SETS RDYON,IMPLIES
M88TS68930-13
100= 0
MAIlBOX IS AVAilABlE TO HOST
I
Detect!lIOO .. O
one of its external test conditions
l
Ap""'1=O, iiS=
0
detoclS
•
CS .. O,'RS",o
[The
If pseudo-slave
processor is put in Halt state
and releases the system bus
Asserts IRO high
I
Detects iRQ_I
MALBOXACCESS
(3 read~ and 3 writes maximum)
EN) OF MAILBOX ACCESS
AppIiesCs=O,RS",,1
I
detects
~
CS=O,RS",'
~
If pseudo-slave [
Internal Halt Disppears The processor
resumes program and
takes back control of the bus
~
ClearsRDYOIN
MUboX IS avalable 10 Itle SlAVI::
This protocol is hardwired on the slave side and programmed on the host side. The mailbox is included
in the slave. The two slave address pins (CS, RS)
are directly connected to two host address lines.
Therefore, the slave is seen as two external memory locations by the host which will address it by ge18/53
nerating an external address directly or indirectly
(pointer EO or E1).
§yjlddressing the location 00 the host echoes the
IRQ to the slave and accesses the mailbox.
By addressing the location 01 the host releases the
bus ..
W'I
SGS·11I0MSON
•J
rnIilD©mJl!I!.l--!.
slave executes programs with no internal halt during mailbox
exchanges but never has of AD bus for local addresses
M88TS68930-15
• Up to three consecutive readlwrite operations may take place,
19/53
687
TS68930/31
Figure 11.8: TS68930/31 Mailbox Exchange, Pseudo Slave Mode.
r- ----j
.
~~;--hJLi~~
(Machine cycle clock)
te
I
,
,
,
CS
I
I
I
/~~~~
,
,
,,
/~~~/
,
,
RS
,
-S-Rw=--~--I//~I----~~---;/I/-I---;----+i----j/~/
:______
I
mailbox
mailbox
ready
request
mailbox exchange
end of
exchange
,-----//I/-I-------,/I~I---------c--
IRQ
I
I
~
1~---------;71;__:
'I
.. Ir-----/7~rl----------jI~~I----,
-B-A-----I/1/-1- - - - - - - - - ; /f-j
~-~-,
,
,
,------/I~I----------i/f----i.------;//'-I
~"
---------1//
(internal signal)
,
A~~~ ~DruA\TTAAiNIN_;,-------__;----<,
local bus addresses
- - - - '_ _ _ system bus exchanges
Ib,
, - - - - internal halt
M88TS68930-16
20/53
688
TS68930/31
3.5.7. Access Mode Register (AMR). The AMR is
a? -bit register which defines the processor external
access modes.
19
1B
17
It is loaded by an INI or SVR instruction and saved
by an SVR instruction. Its fields are defined as follows:
16
15
14
13
I-BUS
Z-BUS
Bit 0: FEiSE
o = Separated bus.
This bit defines Fast Exchange in one cycle to access external resources when low. Or slow exchange in two cycles when high. The slow exchange
mode can only be used in the real mode. The circuit
automatically repeats the instruction which defines
the external transfer. The control of the multiplier,
ALU, ACU, loop counter is the responsibility of the
programmer who must take into account the repetition of the instruction.
1 = Concatenated bus.
This bit indicates whether the local bus is used as a
1S-bit concatenated bus or as 2 independent 8-bit
buses.
(see 3.5.4. - local bus description).
Bit 1 : SUPS.
0= Slave.
1 = Pseudo-slave.
This bit defines the behaviour of the TSS8930/31 regarding the system bus (ADO-AD?}. In slave mode,
the processor will never use the system bus as local bus address.
In pseudo-slave, the processor uses address bus
(ADO-AD?) for local resources. These bits will be
concatenated with A8-A 11 bits of the local bus to
form a 12-bit address bus for larger external memory spaces. The pseudo-slave will then address an external RAM with LSB's address on ADO-AD? and
MSB's on A8-A11. After an exchange the TSS8930
in pseudo-slave mode must relinquish the master
(see 3.5.3. - Master/slave configuration).
Bit 2 : S8ICB.
Bit 3: I/M.
o = Control pulses Read (RD) and Write (WR) are
generated. This is the case with an Intel type peripheral or a standard byte-wide RAM.
1 =..Qontrol pulses data strobe (OS) and Read/Write
(RIW) are generated.
This is the case for exchanges with a slave processor, a S8000 type peripheral, a data converter such
as TS?542 or the
M.A.F.E.
chip
set
(TSS8950/51/52).
Bit 4: DTACK/BES.
The TSS8930 does acknowledge correct access by
generation of a DTACKoutput. In this case, the BES
pin is not available for an external test condition.
Bit 5 : BNBE5.
This bit low configurates the pin BAlBE5 as bus available output (BA) indicating to the master that the
pseudo-slave is not using the system bus for generating addresses on the local bus. When high, it is
used as an external test condition (BE5).
21/53
689
TS68930/31
Bit 6 : MASK (TS68931 only).
CLKOUT : available on TS68930 and TS68931.
When this bit is low, an external Halt applied to the
processor will not change the values in the ARM register. When high, an external Halt applied to the
processor will reset the ARM register with following
configuration:
The CLKOUT output period is function of the EXTAL period and is half the frequency of the input
clock.
ONE CYCLE EXCHANGE, PSEUDO-SLAVE,
CONCATENATED BUS, RD AND WR CONTROL
PULSES.
This bit can be modified by the programmer even
while the HALT is asserted.
3.5.S. Instruction interface and system control
(TS68931 only). On the TS68931, the coefficient
ROM and the instruction ROM (CROM & IROM) are
external. The device provides the necessary buses
to access these data. Instructions are read on IDO :
ID31 using IAO-IA 15 for addressing. Coefficients are
read on local address bus DO-D15 using CAO-CA8
for addressing. CA9 is at low level for address validation. CAO : CA7 also contains external RAM addresses (if necessary) associated with a high level
for CA9.
So, for the TS68931, there is no need of a pseudo
slave mode as ADO:AD7 remain available for data
transfer on the system bus. Clock signals are also
provided for interfacing purposes (3.6.1.).
3.5.9. Halt (T868931 only). The external HALT signal will freeze the program counter, the loop counter. The instruction register can then be loaded from
an external source. This signal is used for system
development. If the MASK bit = 1 then it will force
the AMR into the following configuration:
ONE CYCLE EXCHANGE, PSEUDO SLAVE, SEPARATE BUS, RD AND WR CONTROL PULSES.
3.6. OTHER RESOURCES
3.6.1. Clock generators. Different clock outputs
are available on the TS68931 and on the TS68930.
22/53
690
INCYCLE : available on TS68931 only.
The INCYCLE output is equal to machine cycle in
real mode and half of machine cycle in complex and
double precision mode.
3.6.2. Reset. The reset signal acts on several processors blocks as follows:
_ Sequencer: the program counter (PC) and
the loop counter (LC) are cleared to zero. The
instruction register is loaded with NOP instruction.
Status register: set in real mode, no satu ration, empty FIFO (EF = 1), memorized overflows (MOVF = 0), and XRAM and YRAM in
non circular addressing mode.
Access Melde Register (AMR) : set for one cycle external exchange, slave mode, concatenated bus, RD and WR, BE5 and BE6, SDS
and SRiW.
The reset signal must be maintained for a minimum
of 16 cycles of EXTAL signal.
3.6.3. Watchdog capability. The watchdog prevents the processor from staying locked in an undesired state or internal loop caused by adverse conditions such as high-voltage transients. The circuitry
includes a 2-bit counter which is incremented by
each falling edge on BE3 input and reset by software testing of any of the BE3 conditions. If three
falling edges of BE3 input occurs without a test of
the condition, the TS68930 is reset by the watchdog
circuit. This capability is a mask option of the
TS68930 which is chosen (or not) by the user.
TS68930/31
Figure 12 : Reset Timing.
16 EXT AL cycles
:--
elk generator reset
I: .
internal register initialization
EXTAL
L-------------------------~----------------__!7~~(------------------~
machine cycle clock correspond at
mask programmed EXTAU2 or CC=1
te
machine cycle
M88TS68930·17
23/53
691
TS68930/31
4. TYPICAL APPLICATION CONFIGURATIONS
Figure 13: Configuration Example with TS68930 + RAM + MAFE*.
I
I
BE6
BE5
D8·D15
DO-D7
VC
I'''f
Vt
~
-V
RxeeJ
DO·07
Txee
~RAI
rv----
MAFE
TS68930
A11
A10
A9
A8
OS or R5 I--------- -
RlWorWR I---------
~AT
-
"-
-
eS1
eso
RSO
RS1
,(~
E
RNi
OE
WE
-
~
ADO-AD7
-
8
cs
-V
00-015
~
Towards
8
general purpose
microprocessor
3
8
~
11
A11
A 10
A9
As
1
0
X
X
MAFE
0
X
X
X
RAM
• MAFE is the TS68950/51/52 Modem Analog Front - End Chip Set.
24/53
692
-V
-V
AO-A10
RAM
2K x 16
(2x2Kx8)
M88TS68930-18
o
TS68930/31
Figure 14 : Configuration Example: 3 TS68930 + RAM.
j
I
BSO
IRQ
BS1
-----v
08-015
ADO-AD?
00·07
T868930
T868930
AS-All
\r--
L
2
-
CS,RS
OS or AD
ADO-AD?
A9·Al1
RfWorWR
(1}
S5S or SR/W
2
I
2
I
Towards
general purpose
microprocessor
SOS or SRIW
4
~
-----v
IRQ
-
ADO-AD?
CS,RS
AS-A11
T868930
(2}
RAM1Kx16
~
-V
-V
08-015
00-07
AO-A9
ADO-AD?
I
AO-A9
AlO
All
Al0
Ag
0
1
0/1
1
TS68930 (1)
0
1
1
0/1
TS68930 (2)
1
0
X
X
RAM
CS
OE
WE
1
1
As
M88T868930·19
25/53
693
TS68930/31
Figure 15 : Configuration Example 4 T868930 + MAFE + RAM,
",i--------------jAXCC
,co i - - - - - - - - - - - - - - j T x C C
08-015
K",-----, ,---v)
MAFE
00-07
bJr'----=7'·'·
"fl~~O;'
ni
TS68930
,-,1'--
SSC
BSI
)
ADO-AD7
V
:,
v
II
TS68930
~CS'RS
BS2
Lr-
(1)
SDS_
Al1.A9
~~!~
IRQ
I
"'" ADD·AD?
L -_ _
~;/
All,A8
TS68930
(2)
CS.RS
F===~I:0-
L---"~r-Q- - - - '
,------v)
AOO-AD?
2
f=====::i"o;,,",",
00-015
K.v---~
TS68930
(3)
f=====~i'~DsorsRfW
I
A8·AI'
f-----
"~~
AS_AliI/---
L - - - - - -lA
AO-A7
DO-DI5
K",---~
1"----"'-------,"
26/53
694
A11
A10
A9
As
1
0
X
X
MAFE
0
1
0/1
1
TS68930 (1)
0
1
1
0/1
TS68930 (2)
0
0/1
1
1
TS68930 (3)
ru
':"fl SGS·11I0MSON
iltJD©IRI@rn~rn©'U'IRI@I'lD©$
M88TS68930-20
TS68930/31
Figure 16: Interfacing CRaM, IROM to ST18931.
local bus A8-A 11
TO OTHER
PERIPHERALS
~,-____D~'~bU~S~D~0~'D_1~5-,
16
CA9
(OECROM)
CROM
ERAM
512x16
COEFFICIENT ADDRESS BUS
(also used for local bus addresses)
H-
/1_ _ _ _ __
TS68931
/
~
INSTRUCTION DATA BUS
" ' .c - - - - - ,
"J
IDO-ID31
INSTRUCTION
ROM
IROM
(64KX32)
r-____________IN~S_TR~U~C~T~IO~N~A~D~D~R=E~SS~BU~S~______________ ____
IAO-IA15
M88TS68930-21
27/53
695
TS68930/31
5. INSTRUCTION SET
Number of Cycles
Symbol
Type
Operation
REAL
CPLX
OSPR
OPIN
Calculation Instruction with Indirect
Addressing
This instruction refers to operands
indirectly addressed.
1
2
OPDI
Calculation Instruction with Direct
Addressing
The operand sourcing the L-BUS is
directly addressed.
1
2
OPIM
Calculation Instruction with
Immediate Operand
An immediate operand is read on
R-BUS.
1
2
ASR
ASL
LSR
ROR
General Shift Instruction
The operand sourcing the L-BUS
can be shifted/rotated by 0 --? 15
bits.
1
2
BRI
Immediate Branch Instruction
Conditional/unconditionnal branch to
direct address.
2
2
BRC
Computed Branch Instruction
Conditional/unconditional branch to
computed address.
2
2
SVR
TFR
Data Transfer Instruction
This instruction is used to save
register contents in external or
internal RAM.
1
2
INI
Initialization and Control Instruction
Pointers, acces mode register, loop
counter, mode initialization.
1
2
28/53
696
TS68930/31
INSTRUCTION SET LANGUAGE DEFINITIONS
LOT
R SRC
L SRC
Load L-BUS source into Transfer Register T
R-BUS Source
L-BUS Source
SL
ALU Input Selection Left Side
SR
ALU Input Selection Right Side
ALU DST
ALU CODE
LDM
LON
ALU Output Destination
ALU Codes
Load L-BUS Source into Multiplier Input M
Load R-BUS Source into Multiplier Input N
Z SRC
Z-BUS SOURCE
Z DST
Z-BUS DESTINATION
ZT
ACE
AY
AX
BRA
FT
Load Z-BUS into Transfer Register T
Post Incrementation Pointers CROM or ERAM
Post Incrementation Pointers YRAM
Post Incrementation Pointers XRAM
Branch Address Source
False/true Condition
SVPC
Save Program Counter
JDST
Destination Register for J Constant
KDST
Destination Register for K Constant
MODE
Operating Mode
SAT
Saturation Flag
ADOF
Ever add Flag
J Constant
8-bit Constant used to initialize registers
K Constant
12-bit constant used to initialize registers
29/53
697
TS68930/315.1 OPERATING CODE FORMATS
Fig. 17 : OPIN : Calculation Instruction with Indirect Addressing.
Bit
Field
31
30
Operations and Codes
OP CODE
00
29
LDT
O-NO LOAD, 1-LBUS --> T
28
27
R SRC
00
(XO)
01
(EO)
10
(YO)
11
(Y1)
26
25
24
L SRC
000
(XO)
001
(X1)
010
(YO)
011
RIN
23
SL
O-LBUS / 1-P
22
SR
O-RBUS / 1-AlB (refer to ALU DST)
21
20
19
18
17
ALU CODE
ct.
16
15
ALU DST
00
D
01
14
13
12
Z SRC
000
D
001
100
T
F
F
10
A
11
B
010
A
011
B
100
T
11
LDM
O-NO LOAD / 1-LBUS --> M
LDN
O-NO LOAD / 1-RBUS --> N
9
8
ACE
00
+0
01
+ 1
10
7
6
AY
00
+0
01
+ 1
10
5
4
AX
00
+0
01
+ 1
10
3
2
1
Z DST
0
ZT
698
110
(CO)
111
(C1)
101
CCR
110
111
-
-
101
(E1)
110
(XO)
111
(X1)
Special Table
10
30/53
101
(E1)
-
-
000 001 010
NONE ROUT (YO)
11
- 1
11
-1
11
-1
011
(Y1)
100
(EO)
O-NO LOAD / 1 ZBUS --> T
TS68930/31
Fig. 18 : OPDI : Calculation Instruction with Direct Addressing.
Bit
Field
31
30
29
Operations and Codes
OP CODE
010
28
27
R SRC
00
(XO)
01
(EO)
10
(YO)
11
(Y1)
26
25
24
L SRC
000
X
001
010
Y
011
RIN
-
23
Z SRC
O-D / 1-F
22
SR
O-RBUS / 1-A
21
20
19
18
17
ALU CODE
ct. Special Table
16
ALU DST
O-F / 1-A
15
14
13
12
11
10
9
8
7
6
5
4
100
T
101
E
110
-
111
C
MSB
LBUS
DIRECT
ADDRESS
LSB
3
2
0000 0010 0100
NONE ROUT (YO)
0110
(Y1)
1000
(EO)
1010
(E1)
1100
(XO)
1110
LCR
0001
XO
0111
Y1
1001
EO
1011
E1
1101
CO
1111
C1
Z DST
1
0
0011
X1
0101
YO
31/53
699
TS68930/31
Fig. 19 : OPIM : Calculation Instruction with Immediate Operand.
Bit
Field
31
30
29
28
27
Operations and Codes
OP CODE
01110
26
25
24
L SRC
000
(XO)
001
(X1)
010
(YO)
23
SL
O-LBUS / 1-P
22
SR
O-RBUS / 1-A
21
20
19
18
17
ALU CODE
ct.
16
ALU DST
O-F / 1-A
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
32/53
700
Special Table
MSB
IMMEDIATE
VALUE
LSB
011
RIN
100
T
101
(E1)
110
(CO)
111
(C1)
TS68930/31
Fig. 20 : ASR, LSL, LSR, ROR, Shift Instructions.
Field
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Operations and Codes
OP CODE
01111
L SRC
000
X
SL
O-LBUS 11-P
ALU CODE
001
-
00
01
ASR
LSL
SHIFT
VALUE
0000 0001
a
1
ALU DST
O-F 11-A
010
Y
10
all
100
101
110
111
RIN
T
E
-
C
11
LSR ROR
.....
.....
1111
15
NOTE: When LSR, ASR, ROR
shift value is complemented to 2.
MSB
LBUS
DIRECT
ADDRESS
LSB
a
33/53
701
TS68930/31
Fig. 21 : BRI : Branch Immediate Instruction.
Bit
Field
31
30
29
OP CODE
100
28
BRA
O-IR, 1-RAS
27
FT
O-FALSE, 1-TRUE
26
25
24
23
COND
CF Special Table
22
SVPC
O-NO SVPC, 1-PC -> RAS'
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
Operations and Codes
MSB
BRANCH
ADDRESS
LSB
5
4
AX
3
2
1
Z DST
0
ZT
00
+0
01
+ 1
10
-
11
-1
000 001
NONE -
010
[YOl
011
[Y1]
o NO
100
101
-
-
110 111
[XO] [X1]
LOAD, 1-ZBUS -> T
* The PC write operation in X or YRAM (defined by Z OST) is realized if the branching is really executed.
34/53
702
TS68930/31
Fig. 22 : BRC : Branch Computed Instruction.
Bit
Field
31
30
29
28
OP CODE
1010
27
FT
O-FALSE, 1-TRUE
26
25
24
23
COND
CF Special Table
22
SVPC
O-NO SVPC, 1-PC -> RAS'
RTI
O-NO RTI, 1-RAS -> PC
Operations and Codes
21
20
19
18
17
16
15
14
13
12
BRANCH
SOURCE
000 001
NONE F
010
A
011
B
01
+ 1
10
11
-1
100
T
101
110
111
-
-
-
100
101
-
-
110
[XO]
111
[X1]
11
10
9
8
7
6
5
4
AX
3
2
1
Z DST
0
ZT
00
+0
-
000 0001 010
NONE [YO]
011
[Y1]
O-NO LOAD, 1-ZBUS -> T
* See BRI.
35/53
703
TS68930/31
Fig. 23 : SVR : Data Transfer Instruction.
Operations and Codes
Bit
Field
31
30
29
28
27
26
OP CODE
011000
25
24
23
22
Z SRC
0000 0001 0010 0011 0100 0101 01100111
Y1
E1
C1
XO
X1
YO
EO
CO
1000 1001 1010 1011 1100 1101 1110 1111
AMR LC
A
F
D
STA
B
-
21
20
19
18
17
16
MSB
15
14
13
12
11
10
9
8
7
6
5
4
ZBUS
DIRECT
ADDRESS
3
2
1
Z DST
001 010 011
000
NONE ROUT Y AMR
100
E
0
ZT
O-NO LOAD, 1-ZBUS
T
36/53
704
LSB
--7
101
STR
110
X
111
-
TS68930/31
Fig. 24 : INI : Initialization and Control Instruction.
Field
Bit
Operations and Codes
31
30
OP CODE
11
29
28
27
J DST
000 001
AMR LCD
26
25
24
K DST
000 001
010
011 100 101
XO X1 LCI-LCR NONE EO E1
23
22
MODE
00
21
SAT
20
ADOF
-
010
YO
011
Y1
100 101
CRR EN'
o NO SATURATION MODE
o NO INVERSION
J7 J7 0 YRAM NORMAL MODE
18
17
16
15
14
13
12
J6
J5
J4 (if EN)
J3
J2 (if EN)
J1 (if EN)
JO
11
10
9
8
7
6
5
4
3
2
1
0
110
CO
111
C1
01
10
11
REAL DBPR CPLX
19
J CONSTANT
110 111
EF NONE
OX EI = NIC
10 EI = 0
11 EI = 1
1 SATURATION MODE
1 INVERSION LSB ADDRESS XIY RAM
1 YRAM CIRCULAR ADDRESSING MODE
OX SIM = NIC
10 SIM = 0 (INTEL)
11 SM = 1 (MOTOROLA)
o RDY OIN
= NIC
1 RDY OIN = 1
K11
K7 0 XRAM Normal Mode
1 XRAM Circular Addressing Mode
K CONSTANT
KO
• EN (Enable) code (101) is a multi-function condition permitting independant programming of RDYOIN and SIM flags, and STA register bit EI in J field of the INI instruction.
37/53
705
TS68930/31
5.2
ALU CODES
MNEMO
Function
ADD
A+B
ADDC
A+B+ CARRY
ADDS
B + A/16
ADDX
B + A' (COMPLEX CONJUGATE)
AND
A-B
ASL
CARRY
[J--[
d
ASR
CLR
CLEAR
COM
COMPLEMENT A
COM
COMPLEMENT B
LCCR
LBUS -> CCR
LSL
CARRY
LSLB
LSL BYTE
LSR
0
LSRB
LSR BYTE
f~
0
CARRY
-1
f--D
0
CARRY
NOP
OR
A,B
RCE
EXECUTE RC
RCER
EXECUTE RC 1 LOAD NEW CODE
RCR
LOAD RC
r1
ROR
MO
VF
*
*
*
*
*
* * *
*
*
*
*0
*
*
*
*
* * * * *
1
SI
CR
CI
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*0
*
*
*
*0
0
o-----c=:::::J-
SBC
A + B + CARRY
SBCR
A + B + CARRY
SET
SUB
A+B+1
SUBR
A+B+1
TRA
TRANSFER A
TRA
TRANSFER B
XOR
AEBB
SUBS
B + Al16 + 1
tr-D
CARRY
*
*
*
*
*
*
*
*
*
*
0
0
0
*
*
*
*
*
*
*
*
*
*
0
0
0
0
*
*
*
*
*
*
*
*
*
*
0
0
* *
* *
706
Z
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*0
*
*0
*
*0
*
*0
AO Code
VF (117-121)
*
*
*
*
*
*
00010
0
*
01111
0
0
10011
* 0
*
*
*
* * * *
* 0
*
* 0
*
* 0
*
0
*
*
* 0
*
* * * *
* * * *
10110
* * * * *
*
*0
*
*
*
0
0
*
0
0
*
* * *
Notes: 1. A B refer to ALU inputs (respectively LSI DE, RSIDE) not to accumulators AlB.
2. In ASL the OVF bit is equivalent!o exclusive OR of bit 14 and 15.
38/53
OV
F
SR
*
0
0
00011
00001
01010
01110
01011
11000
01001
11011
11001
00111
11010
00000
01101
10001
10000
10010
*
10111
*
*0
00101
*
*
*
0
*
0
*
* * *
00100
*
*0
*
*0
*
*
*
*
01000
11100
00110
10100
10101
01100
11101
TS68930/31
5.3. TEST CONDITIONS
True Condition
False Condition
Code
BE3
No BE3
0100
BE4
No BE4
0010
BE5
No BE5
0011
BE6
No BE6
0001
Branch Always
Branch Never
0000
BSO
No BSO
1100
BS1
No BS1
1101
BS2
No BS2
1110
CI
No CI
1010
CR
No CR
0110
MOVF
No MOVF
1011
OVF
No OVF
0111
RDYOIN
No RDYOIN
1111
SI
No SI
1001
SR
No SR
0101
Z
No Z
1000
5.4. AMR AND STA REGISTERS
AMR (Access Mode Register)
6
5
4
3
2
MASK
BA
BE5
DTACK
BE6
T
M
SB
CB
o
SL
PS
SEO
STA (Status Register)
7
39/53
707
TS68930/31
CONDITION CODE REGISTER (CCR)
Name
Function
Description
SR
Sign Real
Set if the MSB of the ALU result is 1. Cleared otherwise.
SI
Sign Imaginary
Set if the MSB of the ALU imaginary result is 1 (in complex mode). Cleared
otherwise.
CR
Carry Real
Set if a carry is generated out of the MSB of the result for arithmetic and shift
operations. Cleared otherwise.
CI
Carry Imaginary
Set if a carry is generated out of the MSB of the imaginary part of the result
for complex arithmetic and shift operations. Cleared otherwise.
Z
Zero
Set if the ALU result equals zero. In complex mode it is set if both real and
imaginary parts are equal to zero.
OVF
Overflow
Set if there was an arithmetic overflow. This implies that the result cannot be
represented in the operand size. In complex mode it is set for an overflow of
either real or imaginary part. Cleared otherwise.
MOVF
Memorized
Overflow
Set in the same conditions as overflow. Is cleared only when tested by a
branch instruction.
AOVF
Advanced Overflow
Exclusive OR of bit 14 and 15 of the ALU. If there was an arithmetic overflow
on half capacity (15 bits in real/complex mode, 31 bits in double precision
mode). Is memorized and cleared by LCCR ALU instruction.
OVFM
Overflow Multiplier
Set if the multiplier has overflowed. Only meaningful for complex multiplication.
Is memorized and cleared by LCCR ALU instruction.
STATE REGISTER (STR)
Name
Function
Description
EF
Empty FIFO
Set if FIFO is empty. Cleared otherwise.
SAT
Saturation Flag
Set if the TS68930 is programmed in saturation mode. In this configuration,
the processor will behave as follows:
Positive overflow: ALU result forced to 7FFF.
Negative overflow: ALU result forced to 8000.
This feature does not apply to double preCision mode. This bit is cleared
otherwise.
MODE
(2bits)
Operating Mode
Define a real (01), complex (11) or double precision (10) mode.
XC
XRAM Circular
Circular addreSSing mode flag for XRAM. (see 3.3.3)
YC
YRAM Circular
Circular addressing mode flag for YRAM. (see 3.3.3)
40/53
708
TS68930/31
6. ELECTRICAL SPECIFICATIONS
6.1. ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
.
.
Value
Unit
Vee
Supply Voltage
- 0.3 to 7.0
V
Vin
Input Voltage
- 0.3 to 7.0
V
TA
Operating Temperature Range
o to 70
°C
T stg
Storage Temperature Range
- 55 to 150
°C
Pomax
Maximum Power Dissipation
3
W
With respect to Vss
Stresses above those hereby listed may cause permanent damage to the device. The ratings are stress ones only and functional operation of the
device at these or any conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Standard MOS circuits handling procedure should be used to avoid possible damage to the device.
6.2. DC ELECTRICAL CHARACTERISTICS
Vee = 5.0 V ± 5 %, Vss = 0, TA = 0 'C to + 70 'C (unless otherwise specified)
Symbol
Parameter
Min.
Typ.
Max.
Unit
4.75
5
5.25
V
Vee
Supply Voltage
VIL
Input Low Voltage
- 0.3
0.8
V
VIH
Input High Voltage
2.4
Vee
V
10
J.LA
0.5
V
lin
Input Leakage Current
VOH
Output High Voltage (lioad = - 300 ~A)
VOL
Output Low Voltage (lioad = 3.2 mAl
2.7
V
PD
Power Dissipation
1.5
W
Gin
Input Capacitance
10
pF
ITSI
Three State (off state) Input Current
10
~A
41/53
l:V ~~~~~~r::~~l: .-----------~709
TS68930/31
6.3. AC ELECTRICAL SPECIFICATIONS - CLOCK AND CONTROL PINS TIMING
(V cc = 5.0 V ± 5 %, T A = 0 'C to + 70°C, see figure 6.1.)
OUTPUT LOAD = 50 pF + DC Characteristics I load
REFERENCE LEVELS:
V IL : 0.8 V
V IH : 2.4 V
VOL:0.8V
V oH :2.4V
tr, tf
:0;
5 ns for input signals
Max.
Unit
160
ns
External Clock Fall Time
5
ns
trex
External Clock Rise Time
5
ns
teoh
EXTAL to CLKOUT High Delay
25
teol
EXTAL to CLKOUT Low Delay
25
teor
CLKOUT Rise Time
10
ns
teof
CLKOUT Fall Time
10
ns
tdsl
CLKOUT to DS. RD, WR Low
5
ns
tdsh
CLKOUT to DS, RD, WR High
5
ns
Symbol
Parameter
teex
External Clock Cycle Time
tfex .
Min.
Typ.
40
ns
ns
tse
Control Inputs Set-up Time (BSO ... BS2, BE3 ... BE6, Reset, halt)
20
the
Control Inputs Hold Time (BSO ... BS2, BE3 ... BE6, Reset, halt)
10
tdle
CLKOUT to Control Output Low (IRQ, BA)
50
ns
tdhe
CLKOUT to Control Output High (BA)
50
ns
Figure 25 : Clock and Control Pins Timing.
EXTAL
CLKOl!T
BS/BE
RESET, HALT
IRQ,BA
42/53
710
ns
ns
TS68930/31
INTERNAL CLOCK OPTION
A crystal oscillator can be connected across XTAL and EXTAL. The frequency of CLKOUT : tc/2 is half the
crystal fundamental frequency.
1 :1-___
T:a---.
Cl
EXTAL
TS68930
~
C2
XTAL
C1 ,C2 typical value = 10pF
6.4. AC ELECTRICAL SPECIFICATIONS - LOCAL BUS TIMING
(Vee = 5,0 V ± 5 %, TA = 0 'C to + 70 'C ; see figure 6.2.)
Symbol
Min.
Max.
Unit
1/2 tc - 15
1/2 tc
ns
Parameter
tpw
RD, WR, AS Pulse Width
tAH
Address Hold Time
10
ns
tosw
Data Set-up Time, Write Cycle
25
ns
tOHw
Data Hold Time, Write Cycle
10
ns
tOSR
Data Set-up Time, Read Cycle
20
ns
tOHR
Data Hold Time, Read Cycle
5
ns
tARW
Address Valid to WR, AS, RD Low
112 tc - 40
ns
Figure 26 : Local Bus Timing Diagram
~
ADDRfSSES
»2»»
K
tpw
55
}
tARW
-
r-
~r
R/W
\\\\\\\\\
tpw
jfij
\
/
tARW
tpw
WR
/
tARW
tosw
OO-D15
DATA OUT
r-
\' &\l
tOHW
DATA OUT
I
tasR
00-.Q15
DATA IN
DATA IN
IOHB
J43/53
711
TS68930/31
6.5. AC ELECTRICAL SPECIFICATIONS - SYSTEM BUS TIMING
(Vee
= 5.0 V ± 5 %,
TA
= 0 CC to + 70 CC
Symbol
; see figure 6.3.)
Parameter
tspw
SDS Pulse Width
tSAV;
SRIW, CS, RS Set·up Time
tSAH
SR/W, CS, RS Hold after SDS High
tSOSR
Data Set-up Time, Read Cycle
tSOHR
Data Hold Time, Read Cycle
tsosw
Data Set-up Time, Write Cycle
tsoHW
Data Hold Time, Write Cycle
tOSLOT
SDS Low to DTACK Low
tOSHOT
SDS High to DTACK High"
tOSHIR
SDS High to IRQ High
Max.
Min.
Unit
60
20
5
20
5
ns
ns
ns
ns
ns
35
50
50
50
50
10
ns
ns
ns
ns
ns
• DTACK is an open drain output test load include RL = 8200 at Vee
Figure 27 : System Bus Timing Diagram.
tspw
\
V
tSAW
.2f!/W. CS.
RS
tSAH
~
7Jj.
fill /
tSDSR
ADO-A07
DATA IN
DATA IN
I~SDH~
tSDSW
ADO-AD7
DATA DUT
tSD~R
««
DATA OUT
tDSLDT
tDSHDT
\
1\
J
V--
iOSHIR
;f
44/53
712
TS68930/31
6.6. AC ELECTRICAL SPECIFICATIONS - INSTRUCTION BUS TIMING
(V cc
= 5.0 V ± 5 %, T A = 0 'C to + 70 'C ; see figure 6. 4.)
Symbol
Parameter
Min.
Max.
Unit
tlNCH
CLKOUT High to INCYCLE High
5
15
ns
tlNCL
CLKOUT Low to INCYCLE Low
5
15
ns
tlASW
CLKOUT High to Address Valid
40
ns
tlAHW
I-BUS Address Hold
20
40
ns
tliSR
Instruction Valid
20
ns
tllHR
Instruction Hold
10
ns
tOSR
CROM Data Set-up Time
tOHR
CROM Data Hold Time
tc/2 - 40
ns
5
ns
Figure 28: Bus Timing Diagram.
tel2
CLKOUT
INCYCLE
10131
\
/
~
tel2
~IINCH
~
~
/r-
\
j'f
1---1"- tlNCL
\
IIASW
«««<
IIAHW
ADDRESSES
/
tliSR
""-
/
IIIHR
DATA Instruction
IROM
CROM
it"
IDSR
OO-D15
DATACROM
~ SCiS·THOMSON
..
.,I IiIIilU©DiI@~~rn©1i'DiI@IllU©l!l
r-
I DHR
>-
45/53
713
TS68930/31
7. PIN CONNECTIONS
48 - Pin Dual- in - Line Package (top view)
03
02
Dl
DO
BE3
BE4
BSO
BS1
BS2
013
014
015
A11
vec
11
A10
A9
VSS
XTAL
EXTAL
CLKOUT
os
R/iN
SR/W
SOS
cs
AS
RESET
IRQ
'------'
A8
AD7
AD6
AD5
AD4
AD3
AD2
ADI
ADO
BE5/BA
BE6/DTACK
M88TS68930-28
84 Pin Grid Array Ceramic(top view)
1022
1020
1019
1017
1014
VOO
1012
109
107
106
BE3
1025
1023
1021
1018
1015
IDlO
IDll
ID8
INCYCLE
HALT
B50
ID26
ID24
ID16
VSS
1013
BE4
BSl
ID28
ID27
BS2
All
ID31
ID30
1029
Al0
A9
A8
105
IDO
IDl
BE6
DTACK
A04
BES
BA
ID3
104
ID2
AD7
ADS
AD6
DO
01
A02
AD3
D2
D4
D3
D6
D5
46/53
714
D8
D7
D9
Dl0
Dll
D12
VSS
VDD
D13
D15
EXTAL
014
CLKOUT
XTAL
-
IRQ
R/W
-
DS
-
CS
-RESET
-
SR/W
SDS
ADl
ADO
-
RS
TS68930/31
8. ORDERING INFORMATION
Part Number
Temperature Range'
Package
o to 70°C
o to 70°C
48 Pin Plastic OIL
84 Pin Grid Array
TS68930CP/PXXX"
TS68931 CR
• For extended temp. range. please consult your sales office .
• • XXX is the specific number associated to a customer code.
SOFTWARE TOOLS
TS68930 SP-PC
Software Package Including
Macroassembler
Functionnal Stimulator
Linker for PC
TS68930 SP-VMS
Same Software Package for VAX Machines
TS68930 SPC-PC
Same Software with C-compiler for PC
TS68930 SPC-VMS
Same Software Package with C-compiler for VAX
HARDWARE TOOLS
TS68930 EMU
Stand-alone Emulator
TS68930 HDS-1
Hardware Development System 110 V Power Supply
TS68930 HDS-O
Hardware Development System 220 V Power Supply
TS68930 EPR
EPROM Simulation Module for TS68930
9. PACKAGE MECHANICAL DATA
48 PINS - PLASTIC DIP
25
{11 Nominal dimension
(2J True geometrical position
63.5max.
14
48 Pins
47/53
715
TS68930/31
APPENDIX A
DEVELOPMENT TOOLS
- Emulation probes (for TS68930 or TS68931)
DEVELOPMENT PROCESS
- Menu driven operation (about 100 commands)
The development process of a digital signal processing application using the TS68930 or TS68931 is
supported by a complete range of dedicated software and hardware tools which includes macroassembler, linker, simulator, C compiler and optimizer
(respectively TS68930SP or TS68930SPC), standalone emulation card TS68930EMU, multiprocessor hardware development system TS68930HDS,
EPROM emulation module, TS68930EPR.
- Resident AssemblerlDisassembler with full screen
editor
SOFTWARE TOOLS
All the development softwares run on the most common computers, such as IBM-PC or AT® , under
MS-DOS® or VAX® , VMS® , UNIX® or UL TRIX
operatinq systems.
- Symbolic debbuging
- Direct link with PROM programmers
Emulator specific features.
The TS68930EMU is a low cost, stand-alone emulator providing advanced emulation features such
as real-time trace. It can be driven via a RS232C
link by a terminal or an IBM-PC R and offers:
- 8K program memory (expandable to 64K)
- 2K x 16-bit data RAM
- A wire-wrapping area
- Full speed 100ns cycle emulation
The macroassembler supports conditional assembly, high level language facilities for loop definition
and generates all the files for simulation, emulation
and PROM programming.
- Complex conditions break-points
The functional simulator provides step by step execution, break on address and data values, access
to all intemal registers and interface to 1/0 files
(ADX, DAC, test inputs).
The TS68930 HDS is a hardware development station, aimed at the development of multiprocessor
applications. Up to four pairs of emulator boards,
and logic analyser boards can be combined to
match exactly the user needs:
The linker provides mod,ular programming facilities.
The library consists of macros, basic DSP routines
etc ... and provides additional help to user's for their
applications.
The C language compiler offers high-level language
facilities which meets the advanced requirements
(parallelism, pipe-line, three computation modes,
32-bit instruction set) of the TS68930/31.
HARDWARE TOOLS
All the hardware tools are designed to provide ease
of use and minimum learning time by utilizing menu
driven and DSP specific emulation features.
TS68930 EMU and TS68930 HDS have in common:
- Full speed emulation of TS68930 and TS68931
- Use of internal, external or application clock
- 20 breakpoints (stops at defined addresses)
- 8 complex breakpoints (stop after N address X and
M address Y)
- Realtime trace of internal resources
48/53
716
- 2RS232C serial ports
Hardware development station features:
- CMOS memory for backup of configuration
- 64K x 32 program memory
- 4K x 16 data RAM
- A logic analyser with:
* 2K x 19 bit for trace of TS68930/31 bus and 15 external inputs
* Synchronous analyzer on program and local buses
* Asynchronous analyzer on system bus or external
inputs
* Triggering conditions (Address bus with count, data bus external branch inputs, mailbox exchanges,
extemal inputs).
EPROM module.
The TS68930EPR is a small-sized module which
uses the perfect compatibility between TS68930
andTS68931. The module uses a TS68931 and fast
EPROM memories to emulate in real time a ROM
masked TS68930 during prototyping or field tests to
minimize hardware developments. The module is
plug and function compatible with TS68930 pin out.
TS68930/31
APPENDIX B
MASKING INFORMATION
The information required by SGS-THOMSON to
realize a customer masked version of the TS68930
are provided below.
The files for masking must include program ROM
content and coefficient ROM content. They can be
VERIFICATION MEDIA
All original pattern media are filed for contractual
purpose and are not returned. A computer listing of
the ROM content code will be generated and returned to the customer with a listing verification form.
The listing should be carefully checked and the ap-
transferred on EPROMS, 5" 1/4 floppy disks, magnetic tapes (VAXNMS format) or by link to SGSTHOMSON Microelectronics. This must be done in
conjunction with your local sales office or representative indications.
proval form completed, signed and returned to SGSTHOMSON Microelectronics. The returned verification form is the contractual agreement for generation of the customer masks and batch manufacturing.
VERIFICATION UNITS
Ten engineering samples containing the customer
ROM patterns will be sent for program verification.
These samples will be engineering samples and
must be kept by user as reference parts.
49/53
717
TS68930/31
DIGITAL SIGNAL PROCESSOR
CUSTOMER ORDERING SHEET
COMMERCIAL REFERENCE'
: .TS68930CP/XXX ...
COMPANY
ADDRESS
CUSTOMER'S MARKING
PHONE
PATTERN MEDIAS
o
EPROMS
o
51/4" FLOPPY
o
MAGNETIC TYPE-
o
OTHER'
OPTION
o
WATCHDOG
YEARLY QUANTITY FORECASTED:
START OF PRODUCTION DATE
FOR A SHIPMENT PERIOD OF
Customer Contact Name
50/53
718
Date
Signature
TS68930/31
APPENDIX C
SUMMARY OF RESOURCES PER FUNCTION
OPERATING MODES
Symbol
MODE
Function
2-bit register defining the operating mode
(real/complex/double precision)
Resource
Paragraph
Nb
Access Mode Register
OPERATING UNIT
Symbol
Function
ALU
2 Port 16-bit Arithmetic Logic Unit
5 Possible Sources. 4 Possible Destinations. 30 ALU Codes
Works on 32-bit. Data in 2 Machines Cycles.
Resource
Paragraph
Nb
Arithmetic Logic Unit
3.2. 1
Variable 0 - 15-bit right shift, left shift, right rotation barrel
shifter.
Barrel Shifter
3.2.2
16 x 16 ...., 32 parallel pipeline multiplier + 16-bit
adder/substractor, used in complex Multiplications.
Pipeline Multiplier
3.2.3
16-bit register containing status of ALU, mode, status of
address calculation units,enable interrupt flag.
Status
3. 2. 4
A
2 x 16-bit accumulator.
Accumulators
3. 2. 4
B
2 x 16-bit accumulator.
F
3. 2. 4
D
BS
MULT
M,N
P
STA
ALU Output Register
2 x 16-bit registers containing multiplier operands.
2 x 16-bit register containing multiplier result.
4 x 16-bit first in first out register.
Fifo
EF
Flag. Indicates that the Fifo is empty; can be set by software.
Empty Fifo
RC
6-bit register allowing replacement of ALU operation code by
a data coming from L-BUS.
Replace Code Register
3. 2. 4
2 x 16-bit register providing direct transfer between L-BUS
and Z-BUS.
Transfer Register
3. 2. 4
Flag indicates saturation mode.
Saturation
3. 2. 4
T
SAT
51/53
719
TS68930/31
DATA MEMORY BLOCK
Symbol
Function
Resource
Paragraph
Nb
XRAM
YRAM
128 x 16-bit Random Access Memories
Data RAMs
CRaM
512 x 16-bit read only memory containing coefficients or
constants.
Data ROM
XACU
YACU
Arithmetic units providing address incrementation. decrementation and automatic loop.
XACU is dedicated to XRAM. (8 bits)
YACU is dedicated to YRAM. (7 bits)
Address Calculation Units
3. 3. 2
ECACU
3. 3. 1
12-bit arithmetic unit providing incrementation.
decrementation of address.
Shared by CRaM and ERAM (external RAM).
XC
YC
Flag indicates the circular addressing mode for XRAM.
Flag indicates the circular addressing mode for YRAM.
XRAM Circular Flag
YRAM Circular Flag
3. 3. 3
XO. Xl
X
2 x 8-bit registers used for indirect addressing of XRAM
Supplementary register used for circular addressing.
Pointers
3. 3. 4
YO. Yl
Y
2 x 7-bit registers used for indirect addressing for YRAM.
Supplementary register used for circular addressing.
CO. Cl
2 x 9-bit register used for indirect addressing of CRaM.
EO. El
2 x 12-bit registers used for indirect addressing of ERAM.
CONTROL BLOCK
Symbol
IROM
Function
Resource
IR
1280 x 32-bit word read-only-memory containing program
code and immediate data for TS68930 (ref section 6. 6 for
TS68931 )
32-bit register' containing instruction.
PC
Register containing address of program memory.
Program Counter
3. 4. 3
SEQ
The sequencer can test directly 16 conditions programmed
on a high or low state and the sequencer controls next
program address defined by BRANCH, subroutine call, next
instructions.
Sequencer
3.4. 1
RAS
2 x 16-bit register for saving programm counter in case of
subroutine call or interrupt.
Return Address Stack
LC
15-bit register containing a control word for automatic loop. It
is divided into the following sub-registers.
Loop Counter
3. 4. 4
LCI
4-bit register containing
executed in the loop.
8-bit register containing
3-bit register containing
declaration and start of
Watchdog Circuit
3. 6. 3
LCR
LCD
720
3. 4. 2
Instruction Register
the number of instructions to be
the number of loops.
the number of instructions between
the loop.
Prevents locked states for TS68930 only.
52/53
Instruction ROM
Paragraph
Nb
TS68930/31
INPUT/OUTPUT BLOCK
Symbol
AMR
RIN
ROUT
RDYOIN
Function
Ressource
Paragraph
Nb
8-bit register defining the access mode on the local bus.
Access Mode Register
3.5.7
3 x 8-bit shift register.
Mailbox input.
3 x 8-bit shift register.
Mailbox output.
Input Register
3.5.6
Flag used in the protocol to indicate witch processor has
access to the mailbox.
Output Register
Read Out Internal
3.5.5
53/53
721
ell DSP APPLICATION SUPPORT
_ <-__ :>,::-,'
;,;c~:;:>
:;:'_'"; '-:'>'':.':{:;J>-''':--,- - .<;.'.-'
"n,;"
>
><:: ': -"-'-'>i<~<-~:";' ~--~!yo,-"'::t:'-;-~<:~',;:-~-:_,--:~;;f~'::!->;-
723
ST18930EMU
8T18930/31 D8P EMULATION BOARD
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
FULL SPEED ST18930/31 EMULATION
USER FRIENDLY MENU
STEP BY STEP EXECUTION
BREAKPOINTS ON PC OR DATA VALUES
TS68000 BASED MONITOR
FULL SCREEN SYMBOLIC ASSEMBLER AND
DISASSEMBLER EDITOR
CONTROLLED BY STANDARD TERMINAL OR
IBM-PC HOSTED
PROGRAM DOWN-LOADING FROM VAX, IBM
PC-XT/AT (under kermit)
PRINTER ECHO
PROGRAM RAM OF 4K X 32-BIT
COEFFICIENT RAM OF 512 X 16-BIT
READ AND MODIFY ALL INTERNAL REGISTERS AND MEMORIES
EXTERNAL DSP RAM OF 2K X 16-BIT
TWO RS232 SERIAL LINKS FOR TERMINAL,
HOST, PRINTER OR PROM PROGRAMMER
CONFIGURATION SAVED ON POWER OFF
MULTIPROCESSING REAL TIME EMULATION
ALLOWED
Figure 1 : ST18930EMU.
DESCRIPTION
The ST18930EMU is a powerful stand-alone development tool intended for the emulation of the
ST18930/31 DSP, The ST18930EMU board has
been designed to be compatible with the "c" Compiler, Macro-Assembler, Functional Simulator and
Hardware Development System (HDS) tools. The
ST18930EMU allows full real-time application development.
The TS68000 based interactive monitor features a
menu-driven display and also supports a full Screen
Symbolic Assembler and Disassembler as well as
Communication Software enabling Uplink/Downlink
with VAX and IBM PC.
All software required for operation of the
ST18930EMU is resident within four on-board
EPROMs.
January 1989
The ST18930EMU board offers three probes for
connection to the target application:
_ One 120-pin PGA probe for ST18931 emulation
_ One 48-pin DIP probe for ST18930 emulation
_ One 52-pin PLCC probe for ST18930 emulation
A 32K x 16 battery backed-up CMOS RAM allows
an automatic saving of configuration (user program
and data).
The ST18930EMU board is a powerful low-cost tool
for software development, debugging, and real-time
emulation of the ST18930/31.
ORDER CODES
ST18930EMU
1/3
725
ST18930EMU
Figure 2: ST18930EMU Complete configuration.
HOST COMPUTER
OR
PRINTER OR PROM PROGRAMMER
\
I
R5·232C
ST18930EMU
I
"l
/
r
SERIAL PORT Pl
DEBUGGER,
DOWNLOAD/
UPLOAD,
II
32k
x 16 BATTERY
BACKED UP CMOS RAM
I
T568000
POWER SUPPLY
DISASSEMBLER
I
I
WIRE"
ASSEMBLEURI
EXTERNAL
SERIAL PORT P2
II
I
WRAPPING
Sn8g"
I
AREA
TARGET PROBE
APPLICATION UNDER
EMULATION
E88·TS68930·EMU·01
2/3
726
, - - - - - - - - - - - - - - - - - - - - - " ] "11
'0'~ ,
~mi
°1 ~ ~ ~ ~> ~>! ~> ~> ~> ~> ~> ~. ~> ~ ~r ~~ ~ i""rn~
,::!~.'~o;;~
~,
O~ .'0 .'~~ .'0""
o·u
:m ~ ~.'t~:..'I'~O~ t.'m "7~;- ::~ ~!~1
.'~o: .'rno~, .'rn'~· ro:P
,
!
DSP
RESET
~
~cn
§ g:
II
@o
.2
EX~C~~~L
'"'~'"
~
JIIIK. ."
~.g:~
~
~
0H
9
D~
~
~
~
IlJUJU1
S
lLI
~
~
ru
~
,
,
of'
~
w
eft
of
'I
~
of'
I
~
ITJ/ .'~o~. '0'0~, "0°~' .'0~· .'0'~· ~~
~
~
of'
G
of
.'0°- "000.
~
~
..f
~
-~
~
~
33:IJ:3'3:I33
UI
5He93~
of
I
~
::
-F
~
of'
~
rn
lli
~
~
of
.'0°':
~
W
~
TS5e~"m
t;lS
ffi
t
ft
of'
CaT
~" :~tj!
~
m
,
~
'00°:' .'00°'"
!
~
~
~
~
~
~
.
~
~
z
-.J
m
~
Ii I
~
151
~
~
~
~
~
~
ru
~
::J
~
OJ
;:
i
I
Ts58000
~3
CD
"", ,
l.D
;11
:1
~
111"
"e~;:," '~ID~ '~~~~l~~~ lm'~l~:~,'~ 'Q '8'I~(2, ro~;
I
I'"'"
~
of'
.~; .'~'~ .'~o; "rno~, ..~o~ .'00°; 700'; .'~'~ "O o.~ .'rn'~· "00'; .'rn'; ';~'i~
"~w~ uww~w W~W,ill~ ~t 0_0 ~ ,~ ".,:, ' . ~ ,'~I\)
-.J
L,J
~.
-.. - :-'-" - ... '0 '0 '0 '0 '0 '0 ~
t
1
I " "
TARGeT CONNECTOR
r
I'
II!
TARGn CONNECTOR
~
.. ,
I
~
11
~
."
~
"
m
'7l
~
ffi
~
SGS THOMSON
G~ D~ Wm 0
m
ST~893~EMU
,,+ -
(J)
-I
......
Q:)
<0
W
o
m
:s:
c
ST18930EPR
8T18930/31 D8P EPROM MODULE
• FULL SPEED ST18930 EMULATION
• PLUG AND FUNCTION COMPATIBLE WITH
ST18930 DSP CHIP
• INCLUDES PROGRAM AND COEFFICIENT
EPROMS
• VERTICAL AND HORIZONTAL PLUG-IN VERSIONS
• MULTIPROCESSOR CONFIGURATION ALLOWED
• USEFUL DURING PROTOTYPING AND FIELD
APPLICATIONS
• LARGE PROGRAM CAPACITY ALLOWED (up
to 8k x 32 bit)
• DELIVERED WITH SIX BLANK EPROMS (2k x
8 bit)
• COMPLEMENTARY TOOL FOR ST18930 DSP
FAMILY
Figure 1 : ST18930EPR.
DESCRIPTION
The 8T18930EPR module is a board which permits
the replacement of the 8T18930 (DSP in ROM version) by the ST18931 (DSP in ROMLESS version)
with external coefficient and program Eprom memories. The ST18930EPR is the ideal and complementary tool for debugging an application at the prototype level or when the program length exceeds the
3k of the 8T18930 ROM Program capacity. Another
advantage provided by the ST18930EPR is to manufacture compact prototypes before ordering the
final 8T18930 masked version, or to develop lowquantity applications, eliminating masking cost. The
ST18930EPR is designed to physically fit in the
same board surface as the ST18930 device.
It allows a complete full speed emulation of the
ST18930 even in multi-DSP configurations. Fast
buffers are added on the data-bus and may be re'
moved depending of the multiprocessing architecture.
The module is delivered with six blank EPROMs (2k
x 8 bit). Suggested references are CYPRESS
CY7C291-35WC or any compatible memories. The
capacity of the program EPROM memory is 2k x 32
bit, or optionnally can be 8k x 32 bit as compared
with 3k x 32 bit for the ST18930. The capacity of the
coefficient EPROM memory is 512 x 16 bit. The
ST18930EPR is compatible with the use of a crystalon the input pins EXTAL and XTAL, or with an
January 1989
external clock on the input pin EXTAL. The 5 volts
power supply can be provided on the socket of the
target application, or by an external power supply.
ORDER CODES
ST18930EPR-H horizontal version (surface requirement : 60 x 81 mm, height: 15mm)
ST18930EPR-V vertical version (surface requirement : OIL 48 socket, height = 78mm)
NOTE: Several options are possible for the Eprom
module (high quantity without memories or with
Prom or OTP memories, or with 8k x 8 bit Eproms,
or with 52-PLCC socket). Please contact your local
SGS-THOMSON sales office and/or distributor.
PROGRAMMING
Using the ST18930 EMUlator or HDS monitor with
"PROG" menu, the program and coefficients are
down-loaded to the Prom-Programer in byte-wide
sections. An EPROM is programmed wiih each
byte-wide section. Six EPROMs are required; 4 for
the 32-bit wide Program memory and 2 for the 16bit wide coefficient memory. The programmed
EPROMs are then inserted in the EPROM-sockets
according to the module layout.
1/2
729
ST18930EPR
Figure 2 : ST18930EPR Module Layout.
COEFF I ClENT
MEMORIES
v
.
PROGRAM
ME MORIES
v
v
ru
ru
ru
X
ill
X
ill
~7
L.-.CB-
o
....-I
Q)
co
(,.)
o
en
"tJ
I.put
commands
~
File
~
!!1m
~,;:
@.
E:i!
~o
~!I
a;;;m
-0
~z
Al~
i
e
i D a t a files, read or written by the DSP d .
simulation
unng
s
I
File
for
Simulator
.SIM
(RNI)
tHeo
)
I Bus
lAD
DSP
SIMULATOR
TERMINAL
ECHO
File
I
I
I
I
I
I
I
I
I
I
I
I
I
I
File
y
M
s
A
T
.RIN
~
.ROUT
E
l
M
B
0
B
x
u
s
I
I
I
l
i
(copy)
0
(£JUMP)
.. ........
~~
(Set £JAC)
Files
c
DAC
A
l
Files
Input
echo
File
rWritecom)
III
M'~::';"
X,Y,C,E
S
ADC
B
u
s
ST18930SP
On-line help with the simulator commands is available by entering a simple HELP command.
ORDER CODES
Part Number
ST18930SP-PC Software Package on PC for
ST18930/31
ST18930SP-VMS Software Package on VAX VMS
for ST18930/31
5/5
741
ST18930SPC
8T18930/31 D8P "C" COMPILER
• UPGRADED KERNIGHAM AND RITCHIE "C"
DEFINITION, I.E. RESPECT OF ANSI X3J11
STANDARD
• RUNS ON PC OR COMPATIBLE UNDER MSDOS 3.1 OR LATER
• RUNS ON VAX UNDER VMS OPERATING
SYSTEM (for UNIX or ULTRIX operating system
contact your sales office)
• "FLOAT" IN RESPECT OF IEEE 754 STANDARD, "DOUBLE" AND "INTEGER" TYPES ALLOWED
• MANY FUNCTIONS IMPLEMENTED : CHARACTER AND STRING HANDLING, MEMORY
MANAGEMENT, CONVERSION, MATHEMATICAL, 110 ROUTINES
• SPECIFIC RUN-TIME FOR ACCESS TO PERIPHERALS (mail-box, A/D and D/A converter ... )
• SOURCE ASSEMBLER
INCLUSION
IN
SOURCE "C" PROGRAM CAPABILITY
• INTERRUPT HANDLING
• INCLUDES PREPROCESSOR, MACROASSEMBLER AND LINKER-LOADER
• PRODUCES LOADABLE AND RUNNABLE BINARY OBJECT FILES
• HIGH LEVEL SYMBOLIC DEBUGGER
DESCRIPTION
The SGS-THOMSON Microelectronics "C" compiler used with the assembler/linker (included with the
compiler) allows the possibility to write "C" source
code and produces object code running on the
ST18930/31 Digital Signal Processor. It takes into
account all the advanced features of the
ST18930/31 (parallelism, pipe-line, double precision, complex mode and 32-bit instruction set).
December 1988
The high level language "C" compiler has been designed to provide the greatest flexibility of use.
User can either run the complete software with only one simple command, or ru n separately each software included in the package: "C" compiler, optimizer, assembler and linker.
STANDARD
THE SGS-THOMSON "C" compiler is an implementation of the ANSI X3J11 standard, which includes
and exceeds Kernigham and Ritchie specification.
New possibility for the processor and new class for
data are allowed. For example, "CONST" allows
ROM implementation for constant data.
LICENSE
The SGS-THOMSON "C" compiler is delivered under license for one user only. Upgrades of new releases will be done to each registered user, free of
charge, for a duration of 12 months starting from the
purchase date.
ORDER CODES
The ST18930SPC "C" compiler includes in the
same commercial software-package the "C" compiler software plus the standard ST18930SP software
(macroassembler, linker and functional simulator).
Part Number
- ST18930SPC-PC "C" compiler for ST18930/31 on
PC/MS DOS
- ST18930SPC-VMS "C" compiler for ST18930/31
on VAX VMS.
1/2
743
-..J
.j>.
.j>.
en
~
...co
-I
co
Co)
ST 1 8930/1
C COMPILER
,
"C" macro modules
~
t
t
o
en
/
"'\J
o
I
·C· user source code
OSP assembly source file
i'lSen
",en
@.
",n
Specific OSP optimizer
E;!
~o
1l!J1:
~en
~O
!;lz
Manual modification
allowed if necessary
E
macro - assembler
(
Library module
1
... ~Other assembled files
_object_ fil~
......
rl-O--S-p--i-n-c-r-e-m-e-n-t-a-I-------,
evaluation module
or
hardware development station
TS68930EMU
TS68930/31 DSP EMULATION BOARD
• FULL SPEED TS68930/31
EMULATION
(25MHz)
• USER FRIENDLY MENU
• STEP BY STEP EXECUTION
• SIMPLE AND HIGH LEVEL BREAKPOINTS
• TS68000 BASED MONITOR
• FULL SCREEN SYMBOLIC ASSEMBLER AND
DISASSEMBLER EDITOR
• PROGRAM DOWN-LOADING FROM VAX, IBM
PC-XT/AT
• PRINTER ECHO
• PROGRAM RAM OF 2K x 32-BIT
• COEFFICIENT RAM OF 512 x 16-BIT
• READ AND MODIFY ALL INTERNAL REGISTERS AND MEMORIES
• EXTERNAL DSP RAM OF 2K x 16-BIT
• TWO RS232 SERIAL LINKS FOR TERMINAL,
HOST, PRINTER OR PROM PROGRAMMER
• MULTIPROCESSING REAL-TIME EMULATION ALLOWED
DESCRIPTION
The TS68930EMU Emulation Board is a powerful
stand-alone development tool intended for the emulation of the TS68930/31 DSP. The TS68930EMU
board has been designed to be compatible with the
"C" Compiler, Macro-Assembler, Functional Simu-
January 1989
lator and Hardware Development System (HDS)
tools. The TS68930EMU allows full real-time application development and implementation.
The TS68000 based interactive monitor features a
menu-driven display and also supports a full Screen
Symbolic Assembler and Disassembler as well as
Communication Software enabling Uplink/Downlink
with VAX, IBM PC configured as host.
All software required for operation of the
TS68930EMU is resident within four on-board
EPROMs.
The TS68930EMU board offers two probes for
connection to the target application:
• One 84-pin PGA probe for TS68931 emUlation
• One 48-pin DIP probe for TS68930 emulation
A 2K x 16 battery backed-up CMOS RAM expansion board is also supplied for use with the
TS68930EMU to facilitate uploading of Program
and Coefficient Memory.
The TS68930EMU board is an excellent low-cost
tool for software development, debugging, and realtime emulation fo the TS68930/31.
ORDER CODE
TS68930EMU
1/3
745
TS68930EMU
Figure 2 : Complete Configuration.
HOST COMPUTER
(2dJ
\
PRINTER OR
PROM PROGRAMMER
I
TS68930EMU
l
\
II
SERIAL PORT P2
BACKED UP CMOS RAM
I
DEBUGGER,
I
I
2kx 16 BATTERY
SERIAL PORT P1
DOWNLOADI
TS68000
WIRE-
ASSEMBLEURI
WRAPPING
DISASSEMBLER
EXTERNAL
I
PQWER SUPPLY
I
T868000 EXPANSION
CONNECTOR
I
I
UPLOAD,
I
II
TS68931
I
AREA
J
APPLICATION UNDER
EMULATION
Power requirements:
On board DC/DC converter which provides ± 12V
+ SV ± S%/SA
Physical Specifications
290mm x 230mm
Temperature range
Storage: - 40·C to 80·C
Operating: + S·C to SS·C
2/3
746
"11
cO'
,
-
j'
.,
,
~ GG ,I
,-"" '"".~~ ~.~
1 ~ 00 ~
[TIm
~ ~~~ ~ ~ ~
m' ':' ',' , ,
00 00'
00
••,,"" ~,,~, ~! rJ ~ ~ -- i~ rJ! rJ
~6.=- ,1 i;
w~ ~ ~ ! ~ ~ ~ ~ ~~ LJ~g i 00
I
60'
0
~':~~~jr·"m ~' ~' ~' ~' ~' ~' ~' ~' 0' @' 0 0 @~ 00 rut '~,
~L ,m ",.\m
,m 'J~,~c~.. ,~c..~ ~·. ,~c:. ~'" ,~c:.~·. ~c" ~"'~'~oo~".~~ .~::~~:,~c. ~::m~'mri:~
.......
.. r;r
H
~
l:
(;
(,.)
-I
g;
OJ
"
~
."T.Cl._a~,,·
~
0
TARGET CONNECTOR
•
1·'0:'~: ~~ ~: ~~ ~: ~; ~~ ~~
I.'
.
~
~
•
...J
...J
•
•
...J
...J
•
•
...J
•
.J
•
ll-
•
•
'0:~ .
"00=
~ '00=
~ 'm~"'" '0~':'"
•
•
•
•
•
ro·~ t:
[!]
iii : "B"'" IL::J
ABORT
'I:
. : : :1
~
'J9
W
a
!.E
C
~ I~
EXTERNAL CLOCK
L----I
~ _ _ _ _ _ _ _ _ _ _------'
-I
CJ)
OJ
CO
CD
W
o
m
3:
c
TS68930EPR
TS68930/31 DSP EPROM MODULE
• FULL SPEED TS68930 EMULATION
• PLUG AND FUNCTION COMPATIBLE TO
TS68930
• INCLUDES PROGRAM AND COEFFICIENT
EPROM's
• VERTICAL AND HORIZONTAL PLUG-IN VERSIONS
• MULTIPROCESSOR CONFIGURATION ALLOWED
• USEFUL DURING PROTOTYPING AND FIELD
APPLICATION
• LARGE PROGRAM CAPACITY ALLOWED (up
to 8k x 32 bit)
• DELIVERED WITH SIX BLANK EPROMS (2k x
8 bit)
• COMPLEMENTARY TOOL FOR TS68930 DSP
FAMILY
DESCRIPTION
The TS68930EPR EPROM module is a high performance board which permits the replacement of the
TS68930 (DSP in ROM version) by the TS68931
(DSP in ROMLESS version) with external coefficient
and program Eprom memories. The TS68930EPR
is the ideal and complementary tool for debugging
an application at the prototype level or when the pro-
January 1989
gram length exceeds the 1.3k of the TS68930 ROM
Program capacity. Another advantage provided by
the TS68930EPR is to manufacture compact prototypes before ordering the final TS68930 masked
version, or to develop low-quantity applications eliminating masking cost. The TS68930EPR is designed to physically fit in the same board surface as
the TS68930 device.
It allows a complete full speed emulation of the
TS68930 even in multi-DSP configurations. Fast
buffers are added on the data-bus and may be removed depending of the multiprocessing architecture.
The module is delivered with six blank EPROMs (2k
x 8 bit). Suggested references are CYPRESS
CY7C291-35WC or any compatible memories. The
capacity of the program EPROM memory is 2k x 32
bit, or 8k x 32 bit as compared with 1.3 x 32 bit for
the TS68930. The capacity of the coefficient
EPROM memory is 512 x 16 bit. The TS68930 is
compatible with the use of a crystal on the input pins
EXTAL and XTAL, or with an external clock on the
input pin EXTAL. The 5 volts power supply can be
provided on the DIL-48 socket of the target application, or by an external power supply.
1/4
749
TS68930EPR
MODULE LAYOUT
TOP VIEW
MODULE LAYOUT
'9-;-;:;-:--'-=""--------' ~
74ALS373
<;----.::.c..:.==--------, ~
74ALS373
program memory size
selector (2k or 8k)
EEJ
IC18
74F245
coefficient memory
EXTERNAL POWER SUPPLY
PADS AND SELECTION
Separated or concatened
bus selector
PROGRAM MEMORY
PROGRAM WORD MEMORY
IC5
I
IC6
D31
I
D15
IC3
I
COEFFICIENT WORD MEMORY
I
IC1
DO
D15
IC14
IC15
I
DO
M88TS68930EPR-01
Nole : The module is delivered with 6 blank EPROMs (2k X 8).
Suggested references: CYPRESS CY7C291-35WC or any compatible memories.
ORDER CODES
PROGRAMMATION
TS68930EPR-H horizontal version (surface requirement : 60 x 81 mm, height: 15 mm)
Using the TS68930Emuiator or HDS monitor with
"PROG" menu, the program and coefficients are
down-loaded to the Prom-Programmer in byte-wide
sections. An EPROM is programmed with each
byte-wide section. Six EPROMs are required; 4 for
the 32-bit wide Program memory and 2 for the 16bit wide coefficient memory. The programmed
EPROMs are then inserted in the EPROM-sockets
according to the module layout.
TS68930EPR-V vertical version (surface requirement : DIL 48 socket, height: 78 mm)
Nota: For high quantity without memories, or with
Prom or OTP memories, please contact your local
SGS-THOMSON sales office and/or distributor.
214
750
TS68930EPR
BLOCK DIAGRAM
.-/1
/1
BUS DO-D15
V
-~
--V
"
1
~
=;Y----I
EPROM
COEFFICIENT
I
L-
~
c--
~
~
These two buffers
added on D-bus may
be removed depending
of the multiprocessing
architecture
"
512 x16
I
I
LATCH
~
SUSIE
L
TS68931
DIL48
'"
SOCKET
)'
I
COMPATIBLE
WITH
I
LATCH
TS68930
EPROM
PROGRAM
I
I
2 Kx 32
~
BLOCK
I
CONTROL
I
CLCKOUT
F
CLKQUT
INCYCLE
ADDRESS BUS
SIGNAL CONTROL BUS
V ss
Vee
"
~
-V
V SS
I
Vee
+ 5 V EXTERNAL POWER SUPPLY (600mA)
M88TS68930EPR-02
3/4
751
TS68930EPR
DIMENSION OF THE TS68930EPR MODULE
1) Vertical Module
60 mm
T868931
M88TS68930EPR-03
2) Horizontal Module
applic. mother board
M88TS68930EPR-04
• If the TS68930EPR module is plugged into a OlL48 socket increase these value with the height of the OIL
socket (3 or 4 mm).
4/4
752
TS68930HDS
TS68930/31 DSP HARDWARE DEVELOPMENT STATION
• EMULATION/LOGIC ANALYSIS FOR
_ TS68930 MCU VERSION
_ TS68931 MPU VERSION
• MULTIPROCESSING
_ UP TO FOUR EMULATOR BOARDS AND
FOUR OPTIONAL DEDICATED LOGICAL
ANALYZER BOARDS
• USER-FRIENDLY INTERFACE
_ REDUCED LEARN-TIME
_ MENU DRIVEN
_ SYMBOLIC DEBUGGING
_ RESIDENT ASSEMBLER WITH FULL
SCREEN EDITOR
_ CONTROLLED BY STANDARD TERMINALS OR IBM-PC HOSTED
_ DIRECT LINK TO PROM PROGRAMMER
_ CMOS BATTERY BACKUP OF CONFIGURATION (breakpoints, mode ... )
_ UPLOAD-DOWNLOAD KERMIT PROTOCOL WITH HOST (VAX, IBM-PC)
• EMULATION FEATURES
_ FULL SPEED
(cycle time = 160ns)
_ 64K PROGRAM MEMORY (32 bit wide)
_ 4K EXTERNAL DATA MEMORY, MAPPING
ON A WORD BASIS
_ 30 SIMPLE BREAKPOINTS (break at ADDRESS 1)
_ 8 COMPLEX BREAKPOINTS (break after N
ADDR. 1 followed by M ADDR.2)
_ SYNCHRO SIGNAL GENERATION AT SELECTED ADDRESSES OR RANGE
December 1988
_ PSEUDO REAL TIME TRACE OF INTERNAL REGISTERS WITHOUT SLOWING
DOWN EXECUTION
• LOGIC ANALYZER
_ REAL-TIME TRACE (2k depth, 95 bits)
_ SYNCHRONOUS ON DSP BUSES
_ ASYNCHRONOUS ON DSP SYSTEM BUS
AND ON 15 EXTERNAL INPUTS
_ MIXED MODE SYNCHRONOUS-ASYNCHRONOUS
_ TRIGGERING CONDITIONS
IN
• ON
PROGRAM
ADDRESS
CONJUNCTION WITH MANY DIVERSIFI ED CON DITIONS (N times Addr. 1 followed by M times Addr. 2)
• ON LOCAL DATA BUS VALUE
• ON EXTERNAL BRANCH DSP INPUTS
CONDITIONS
• ON START OF MAILBOX EXCHANGE
_ BEFORE, AFTER AND WINDOW TRIGGERING
_ TIME MEASUREMENT FUNCTION
_ BREAKPOINT GENERATION ON LOCAL
BUS VALUE
DESCRIPTION
The TS68930HDS is mainly intended for real-time
multi-DSP applications. It has a menu-driven user
interface so no learn time is required to completely
and easily use all the system efficiency.
1/3
753
TS68930HDS
The designer can add emulator and logic analyzer
boards to meet exactly his requirement. The
TS68930HDS enhances the large range of development tools for the SGS-THOMSON DSP family.
1. GENERAL PRESENTATION OF THE
TS68930HDS
The TS68930HDS (Hardware Development Station) is a real-time multiprocessors (up to 4) emulation system which provides a simple but extremely
powerful user interface due to its interactive menudriven organization.
The TS68930HDS is a modular system consisting
of :
- a rack with power supplies, fans and standard double-Eurocard 9 slots VMEBUS back-plane
- a 68010 VME bus controller board
- up to four real-time emulator boards with 64k x 32
of program memory
- up to four logic analyzer boards with 2k x 95 bit
trace memory associated with each emulator board.
These analyzer boards are optional and can be used
or not according to the application.
The TS68930HDS includes four programmable
RS232C serial ports for connection either to a terminal, printer, Prom or Eprom programmer, or host
computer such as Vax or IBM-PC.
2/3
754
This multi-task capability is managed by the 68010
CPU board. In case of power failure or when switching off the system, a large 64k x 8 CMOS RAM
with battery back-up permits automatic saving system configuration and user programs and data.
The connector P2 on the VME bus is normally not
used by the TS68930HDS boards. But it is always
possible on the emulation board and by wire-wrapping to send DSP signals on connector P2. This possibility enables the user to use these signals on a
double-Eurocard format application. One possible
example is a D/A and ND conversion board.
All the software management of the TS68930HDS
is written in "C" language modules.
2. ORDER CODES
The basic configuration of the TS68930HDS includes one emulation board with its set of two probes
(48-pin for TS68930 and 84-pin for TS68931), and
one logic analyzer board with its set of probes.
The TS68930HDS is available in two versions (220V
or 11 OV). The emulation board and logic analyzer
boards with their respective probes are also available as separate items to fully use the system efficiency'.
Power supply
Part Number
TS68930HDS-0
220V
TS68930H DS-l
110V
H D S
B IH.
U
Logical analyzer
4
Emulator
4
Logical analyzer
Emulator
3
3
Logical analyzer
2
Emulator
2
Logical analyzer
1
Emulator
1
USER'S
-------1
1
APPLICATION
1
1
1
S
~
v
@.
~:i!
~o
~o
Terminal or IBM - PC
!:lz
M
E
*
s::
co
co
--l
(f)
0>
I'"i\';
-I
(J)
I
TS68930/1-
,
C COMPILER
en
0)
2.4V, unless otherwise specified.
2. Measurement paints shown are O.8V and 2.2V, unless otherwise specified.
APPLICATION NOTE
4.4. BLOCK DIAGRAM
T
~
I'-~
~
lp'
GNO
COl
f---!Hov
AGC2
f-~rHOV
01
06
O'
07
~
~
"-----
D6
D5
TxCClK
hell':::
~D4
D4
RxCLK
OJ
~
""cc'" f-f - f -
OJ
01
02
01
RxRCLK
TxMCLK
~ Rjii
CLK
CKL
GND
RSI
RSO
~
RxMCLK
TxRClK
CSI
~DO
ov.1--
f-
CSii
~
~
HI
"..."
XTALl
r-
XTAL2
~.v
Iov
T568951
GND
~ r:soRJW
E
-
v'
~O'
RSI
RSO
~Iov
10kU
LEI
RAI
v-
CSI
AGel
R'O
E
SIGNAL IN
~-.v
Iov
S'P'
T,CC
EEl
f--
nSI
EEO
'--
nso
CSI
ATO
CSii
v'
R.cc
'IHI---<
r1
~
CRYSTAL
6.76 MHz
~ ANi
tc:
R,CC
T.R
R.R
TxCC
lBEB
'--
BE.
BE3
L - BES
AB
~
M
Al1
AID
~
os
TS68931
DIS
01'
013
012
011
010
SOCKET
84- pin
DO
08
~
~
~
~
~
E
07 """"""'
06
SIGNALGlIT
'--1
~.v
Iov
E
eLK
TxCC
~
-
EXI
GND
'---i ov
OS
04
OJ
02
01
DD
V-~5V
IOV
~
~
~
~
~
/
M BBAN 76T-02
5. THE COMMAND LANGUAGE
The command language has been developed with
the DSP macro-assembler available on VAX-VMS
and MS-DOS.
This command language is used in order to simplify the programmation of the MAFE. In this way the
programmation is reduced to a series of commands
(ex: TXSO = transmit signal out) instead of having
to remember register numbers, bit numbers or specific details.
This command language is one possible command
language among many and the user can (and is advised to) use the DSP macro-assembler to create
his own language as needed.
The command language is given in program (cf. appendix B.2.).
11/29
777
APPLICATION NOTE
DEFINITIONS OF PARAMETERS
_ ADDIR: direct address in internal memory or register T
_ K, BIT, BAUD, MUX, FS, HPF, LPF : hexadecimal value (with reference to tables of paragraph 3.3.)
_ RSR: binary value (Example: 101 = rejection filter ON, sample & hold OFF, reconstruction filter ON).
5.1. THE ROUTINES
SIGNAL TRANSFER
Address
Bits
Syntax
800
900
15 - 8
15 - 8
TXSO ADDIR
TXEE ADDIR
800
900
AOO
15 - 8
15 - 8
15
RXSI ADDIR
RXRES ADDIR
CD ADDIR
Address
Bits
Syntax
0000
RC1 BIT, BAUD\
2000
15 - 12
11 - 9
15 - 13
12 - 11
10
0000
15 - 11
RC2 SYNC MUX,
FS, K\
RXPSA K\
EOOO
14 - 12
RXDPLL K\
6000
6000
15 - 12
10 - 9
SET_ATT K\
SET_EXI K\
4000
15 - 12
11,10,9
RC3 HPF, LPF, RSR\
8000
AOOO
15 - 11
15 - 13
SET_AGC K\
SET_CDth KI
TRANSMIT
1 - Signal
2 - Estimated echo
RECEIVE
1 - Signal
2 - Residual Signal
3 - Carrier Detect
PARAMETER SETTING
TIME BASE
1 Bit Rate,
Baud Rate,
2 - Mux,
Sample Clock
3 - Mux, Sample Clock, Sync
4 - RX Phase Shift
Amplitude
5 - RX Phase Shift
Programming
2000
RC2 MUX, FS\
TRANSMIT
1 - Attenuation
2 - Exi Input
RECEIVE
1 - HPF, LPF,
REJ, SH2,
Reconst.
2 - AGC Gain
3 - CD Threshold
5.2. SIGNAL TRANSFER: NOTES AND COMMENTS
All routines are between a memory location (directly addressed) in the DSP and the wanted MAFE register.
The points to keep in mind are that:
_ it takes 2 accesses to read or write a sample,
12/29
778
_ the DSP has 16-bit registers and the 12-bit
samples are aligned on the left (bit 11 of the
sample corresponds to bit 15 of the register),
_ the transfer is made on the 8 most significant
bits of the bus,
_ in slow exchange mode the DSP repeats any
instruction only when referring to an external address.
APPLICATION NOTE
An example is given for receiving signals.
Instruction 1 : First read access
RXSI 10.X (get receive signal and transfer in location 10.x).
OPDI ; LDL $800.E ; ; LSRB L A\
15 14 13 12 11
10
9
8
7
6
5
4
3
2
1
0
I b31 b21 b1 I bO I X Ix Ix Ix Ix Ix Ix Ix Ix Ix Ix Ix
I
DSP DATA BUS DO-D15
15 14 13 12 11 10
9
8
7
6
4
5
3
2
1
0
I 0 I 0 I 0 I 0 I 0 I 0 I 0 I 0 I b31 b21 b1 I bO I X I X I X Ix
I
DSP ACCUMULATOR A
Instruction 2 : Second read access
quently the ALU result is right and must be used (it
is done in instruction 3). The FIFO is only used in
order not to disturb the accumulator A. If accumulator A was used as ALU destination it would be loaded with a wrong value in the first cycle therefore
the OR operation would give a bad result in the second cycle.
OPDI ; LDL $800.E ;; OR L A F\
WARNING: this instruction is repeated twice (external access in slow access mode). The first time the
data on the bus is wrong; consequently the ALU result is wrong and must be ignored.
The second time the data on the bus is right; conse-
15 14 13 12 11 10
9
8
7
~11~1OIb9Ib8Ib7Ib6Ib51b4lx
6
5
4
3
2
1
0
Ix Ix Ix Ix Ix Ix Ix
I
DSP DATA BUS DO-D15
15 14 13 12 11 10
9
8
~11 ~101 b91 b81 b71 b61 b51 b41
7
6
5
4
3
2
1
0
0 I 0 I 0 I 0 I 0 I 0 I 0 I 0
I
DSP INTERNAL DATA BUS LO-L 15
15 14 13 12 11 10
9
8
7
6
5
4
3
~11~1OIb9Ib8Ib7Ib6Ib51b4lb3Ib2Ib1IbOlx
2
1
0
Ix Ix Ix
I
DSP ALU O/P REGISTER D
Instruction 3 :
SVR D 10.X\
15 14 13 12 11 10
9
8
7
6
5
~11~1OIb9Ib8Ib7Ib6Ib51b4lb3Ib2Ibl
4
3
2
1
0
IbO I X Ix Ix Ix
I
DSP XRAM LOCATION 10
5.3. PARAMETER SETTING: NOTES AND
COMMENTS
The commands refer to a register and not a parameter. As most registers include 1 or several correlated parameters it does not create any problems;
however there are cases when 2 parameters are totally uncorrelated but are in the same register; so
when changing a parameter, the other parameter of
the register can get inadvertently changed.
13/29
779
APPLICATION NOTE
The user must be careful in the following cases:
_ command RC2 will put tx sync to zero
_ command SET_ATT will put exi to zero
_ command SET_EXI will put attenuation to zero.
6. EXAMPLE: THE PROGRAM MAFTEST2
To develop the program MAFTEST2, macros from
3 different libraries have been used:
• the command language MAFCOM (cf. appendix
B.2) just described in part 3
• PSIL 1 : (ct. appendix B.3) it is a microprocessor
type language. In this way programs are quicker
to write and more readable than with the DSP assembler language; the disadvantage however is
that it does not make use of the parallelism of the
DSP.
PSIL 1 is used for:
_ modules which do not require speed (initialization),
_ developing test programs.
• PSIUTIL: (ct. appendix B. 4) collection of utilities;
for the present time it is made of memory fill and
timers.
6.1. DESCRIPTION
The program is divided in 4 small modules:
INITIALIZATION
• clear the rams
• move the sinewave from the CROM into the
XRAM
• initialize the DSP with the MAFE access parameters
• initialize the XRAM and YRAM in circular addressing mode
14/29
780
• initialize the MAFE registers.
TRANSMITTER TEST
• WAIT1 : wait for an external clock edge.
On the negative edge of the transmit sampling
clock the program will do the transmit task.
On the negative edge of the receive sampling
clock the program will do the receive task.
• TXMIT : the sinewave stored in the YRAM is read
and the samples sent to the signal olp and echo
o/p.
• RECEIVE: the receive signal (ATO being looped
back on pin RAI) is stored in the XRAM ; the residual signal (EEO being looped back on pin EEl)
is stored in the XRAM.
Note that the estimated echo output is not smoothed and goes to zero for a small time (8 clock cycles = 1/1.44mHz/8 = 5.55~s).
RECEIVER TEST
The 2 signals stored in stage 1 in XRAM are displayed therefore giving the quality of the receiver
path.
The receive signal (ATO being looped back on pin
RAI) is added to the estimated echo and is stored
in the YRAM;
the residual signal (EEO being looped back on pin
EEl) is stored in the YRAM.
ECHO CANCELLING
The 2 signals stored in stage 2 in YRAM are displayed therefore giving the receiver quality when added with the estimated echo.
Note: Addition and substraction of echo only differs
by a 180 degree phase shift.
APPLICATION NOTE
APPENDIX A - PROGRAMMING THE
ACCESS MODE REGISTER (AMR)
To access the MAFE the AMR must be programmed as follows
The AMR is a 6-bit register (TS68930) 7-bit
(TS68931) indicating the circuit 1/0 configuration.
INI REAL SAT; AMR % 1111011\
BIT MEANING:
bit 0 -0 : Fast Exchange
1 : Slow Exchange
: external access in 160ns
: external access in 320ns
bit 1 -0: Slave
1 : Pseudo-Slave
: slave mode on the system bus
: pseudo-slave mode
bit 2 -0 : Separate Bus
1 : Concatenated Bus
: the local bus is separated into two 8-bit buses DO-D7 and D8-D15
: the local bus is 16-bit wide
bit 3 -0 : memory byte-wide
1 : Motorola
: 1 RD pin, 1 WR pin_
: 1 Data Strobe, 1 R/W
bit 4 - 0: DTACK
: BE6 is redefined in DTACK signal for exchanges with a MCU belonging
to TS68000 family
: this pin can be used to test external signals
: BE5 is redefined as BA
: this pin can be used to test external signals
1 : BE6
bit 5 -0 : Bus Available
1 : BE5
bit 6
-
-
MASK (TS68931 only)
o : AMR not masked
1 : AMR masked
: AMR contents not restored to its initial state
: AMR contents restored to its initial state.
When an external HALT is applied, the AMR is forced into a predetermined configuration:
• bit 0 = 0 cycle 160ns
• bit 1 = 1 pseudo-slave mode
• bit 2 = 1 local bus concatenated
• bit 3 = 0 memory byte-wide protocol.
When the external HALT is no longer applied, the
AMR contents is restored to its initial state only if bit
6 has been set to 1.
BIT 0
=
1 (SLOW EXCHANGE MODE) :
The MAFE being a slow peripheral it is accessed by
the DSP in slow exchange mode.
All control signals start at the same ti me as in the standard read or write but they last an additional 160ns. In
read cycle, the bus is sampled 160ns later.
It must be noted that it is purely an external exchange mode, since
• the TS68930 must be in REAL mode,
• the circuit automatically repeats the instruction
where the exchange takes place,
• during this exchange, management of the addresses, of the processing block, of the loop counters are under the responsibility of the
programmer who has to take into account the repetition of the instruction.
When the DSP is programmed as pseudo-slave it
will have 12 bits of external address (A8-A 11 + ADOAD7) ; the system data bus (ADO-AD7) is then used
to supply the lower address lines of the local bus.
BIT 2
= 0 (SEPARATE BUSES)
This feature is useful when accessing an 8-bit device such as the MAFE since:
• when reading, the 8 unused read bits are puts to
zero,
• when writing, the 8 unused written bits are put in
tri-state.
The bus is selected by the address lines
[A 1O-A 11] according to the following table:
A10
A11
0
0
Selected Bus Non Selected Bus
00-07
08-015
0
1
08-015
00·07
1
0
08·015
00-07
1
1
08-015
00-07
BIT 3 = 1 (MOTOROLA TYPE SIGNAL R/W & DS)
= 1 (BE6 is used to test TX conversion clock)
BIT 5 = 1 (BE5 is used to test RX conversion clock)
BIT 4
BIT 6 = 1 (for emulation purpose only).
BIT 1 = 1 (PSEUDO SLAVE)
When the DSP is programmed as slave it can only
have 4 bits of external address (A8-A 11).
15/29
781
APPLICATION NOTE
APPENDIX 8 - PROGRAM LISTINGS
The test program MAFTEST 2
B1 -
"#####################################################################
###################
###################
HERE IS THE TEST PROGRAM MAITEST2
###############~
VI.3 OlNOV86
#############################
AUTHOR: F.M.J RA YMONDOU ##########################
###################
######################################################################
FUNCTION: TEST THE 4 SIGNALS'
A TO (TX SIGNAL)
RAI (RECEIVE SIGNAL),
EEO (ESTIMATED ECHO)
EEl (RESIDUAL SIGNAL)
TEST THE CLOCK GENERA TOR
TEST ATTENUATION ON TRANSMITER & AMPLIFICATION ON RECEIVER
TEST ECHO CANCELLING PATH
HOW? : - GENERATION OF A SINEW A VE IN THE PSI
STAGE!:
- SEND IT TO THE 2 TX REGISTERS
- OUTPUT ATO (WITH ATTENUATION 6DB)
- OUTPUT EEO (NO ATTENUATION POSSIBLE)
---> CHECK EEO & ATO ON SCOPE: IT IS THE SAME SINEWAVE, ONE SAMPLED (EEO), THE
OTHER FILTERED & ATTENUATED BY 6 DB (ATO)
-
LOOP BACK ATO TO THE RX INPUT RAI THROUGH A DIVIDER BRIDGE 27 DB
AND AMPLIFY INTIRNALL Y OF 33DB
LOOP BACK EEO TO THE RX INPUT EEl
STORE THE RX REGISTERS IN THE PSI XRAM
STAGE2:
(NO MORE ATTENUATION NOR AMPLIFICATION BUT ECHO CANCELLING PATH)
- SEND THE 2 STORED SIGNALS IN XRAM TO THE 2 TX REGISTERS
- OUTPUT A TO ( NO ATTENUATION)
- OUTPUT EEO
---->CHECK ATO & EEO: ATO AFTER 6+27 ATTENUATION & 33DB AMPLIFICATION
HAS THE SAME AMPLITUDE THAN EEO
-
LOOP BACK ATO TO THE RX INPUT RAI THROUGH A DIVIDER BRIDGE 27 DB
LOOP BACK EEO TO THE RX INPUT EEl
INTERNALLY EEO + ATO/27DB == EEO
RECEIVE SIGNAL = SMOOTHED EEO
RESIDUAL SIGNAL = EEO
STORE THE RX REGISTERS IN THE PSI YRAM
STAGE3:
- SEND THEM TO THE TX REGISTERS
---->CHECK ATO & EEO: ATO = SMOOTHED EEO OF THE FORMER STAGE
EEO = EEO OF THE FORMER STAGE
16/29
782
APPLICATION NOTE
THEN THE PROGRAM LOOPS ON THIS THREE STAGES
NOTE=ALSO IT CAN BE CHECKED:
- THt GtNtKATtU CLOCKS
- AGCI RECEIVER PIN (RECEIVED SIGNAL BEFORE AMPLIFICATION)
- EEl & RAI INPUTS
ATO
PSI
.....---------1-1
TX
EEOI----.;
EE I
.-----1
RX
RAI
~~------~
#####################################################################n
.SIMUL
.MOTOROLA
" DEFINING A 16-POINT SINUSOID"
.MEMORY HEXA
CROM($50)= 0000
CF04
A57E
89BE
8000
89BE
A57E
CF04
0000
30FC
5A82
7642
7FFF
7642
5A82
30FC \
.ENDMEM
ASG RCI = $0000
.ASG RC2 = $2000
.ASG RC3 = $4000
.ASG RC4 = $6000
.ASG RC5 = $8000
.ASG RC6 ~ $AOOO
.ASG RC7 = $COOO
.ASG RC8 = $EOOO
.ASG SAMPLES = 9 "address of timer: number of samples"
.ASG ACQTIME = 10 "address of timer :acquisition before display "
17/29
783
APPLICATION NOTE
"- - --- - - -- - ------- --INITIALISA TIONS- - - - -- - -- - - - - -- - - -- - - - - - - - -"
XRAMCLR \
YRAMCLR \
START: BLCKMOV $50,16,$10, YO \
INIMAFE \
INI REAL, SAT ;YI $IF ;XI $2F \
INI REAL,SAT ;YO C $10 ;XO C $10 \
INI REAL,SAT ;YO-C $10 ;XO-C $10 \
RCI A,4 \· .............. BIT=2.4KHZ-;BAUD=.6KHZ ..... "
RC2 4,0 \" .............. MUX=7.2KHZ ,FS=9.6KHZ ...... "
RC3 2,1,0 \" ............ BANDPASS .5--1.6KHZ ....... '·
SET AGC 16 \" ......... .33 DB AMPLIFICATION ....... ."
SET-AlT 3 \" ............ 6 DB ATTENUATION ..........."
INITIMER SAMPLES.X ,16 \
INITIMER ACQTIME.X , 2400 \"4 S waiting"
,,----------- TRANSMITTER TEST ---------------------------------"
WAITI: IFTXC TXMIT \
IFRXC RECEIVE \
BRANCH WAIT 1 \
TXMIT: OPIN; LDL [YO]+ , T \
TXSO T \
• .... .TX SINEWAVE ON SIGNAL O/P ............ "
TXEE T \
"..... TX SINEWAVE ON ECHO O/P ............. "
DECTIMER SAMPLES.X \ ' one sample less to transmit"
IFNOZERO WAITI\
INITIMER SAMPLES.X , 16 \
DECTIMER ACQTIME.X \
IFNOZERO WAIT! \
SET AGC 0 \" ........ NO AMPLIFICATION .................. "
RC32,1,01l \" ......SET-UP ECHO CANCELLING ............ "
SET ATT 0\
INITIMER ACQTIME.x , 2400 \
INI REAL,SAT; YI_C $2F \
GOTO WAIT2 \
RECEIVE:RXSI T \ • ..... RX A TO ON RAI by a divider bridge .....
ST T , LXOj+ \ "and store it in XRAM"
RXRES T \ ".... RX EEO ON EEI... ....................... "
ST T , [XO]+ \ "and store it in XRAM"
GOTO WAIT! \
"---------------- RECEIVER TEST ------------------------ "
WAIT2: IFTXC TX2 \
IFRXC RX2 \
BRANCH WAIT2 \
TX2:
OPIN; LDL [XO]+ , T \
TXSO T \ ".... TX RRI ON ATO ...... "
OPIN; LDL [XO]+ , T \
TXEE T \ "....TX RR2 ON EEO ......"
DECTIMER SAMPLES.X \
IFNOZERO WAIT2 \
INITIMER SAMPLES.x , 16 \
18/29
784
APPLICATION NOTE
DECTIMER ACQTIME.X \
IFNOZERO WAIT2 \
INmMER ACQTIME.X,2400 \
GOTO WAIT3 \
RX2:
RXSI T \ ....... RX
ST T , [YO)+ \ "and
RXRES T \ "....RX
ST T , [YO]+ \ "and
GOTO WAIT2 \
ATO ON RAI by a divider bridge ..... ..
store it in YRAM"
EEO ON EEL ....................... ..
store it in YRAM"
_ _ _ _ _ _ _ _ _ _ _ _ECHO CANCELLING
WAIT3: IFTXC TX3 \
BRANCH WAITJ \
TX3:
OPIN; LDL [YO)+ , T \
TXSO T \
OPIN; LDL IYO]+ • T \
TXEE T \
DECTIMER SAMPLES.x \
IFNOZERO WAITJ \
INITIMER SAMPLES.X, 16 \
DECTIMER ACQTIME.x \
IFNOZERO WAIT3 \
GOTO START \
.END
19/29
785
APPLICATION NOTE
B.2 -
The command language MAFCOM
"###############################################################
###### HERE IS DEFINED THE MAFE COMMAND LANGUAGE MAFCOM ########
######################
VI.S
jan87
####################
#### AUTHOR: D.F MARTIN
#############
################################################################
FUNCTION: THIS LANGUAGE IS USED TO COMMAND THE MAFE KIT WITH THE
TSM'J30 PSl.
SjW DEVELOPMENT TOOLS:- TS68930 MACRO-ASSEMBLER (PSIMAC) ON V AX- VMS.
- MACRO LIBRARY :PSILI
- MACRO LIBRARY :PSIUTIL
S/W DEVELOPMENT TIME: I DAY.
TEST TOOLS:- TS68930 REAL-TIME EMULATOR/EVALUATION BOARD (EVA-PSI)
- MAFE EVALUATION BOARD (EVM-MAFE)
TEST TIME: I WEEK
###############################################################"
.CROSS
.MAP
,,**** SIGNAL REGISTER ADDRESSES *******************************"
.ASG
.ASG
.ASG
.ASG
.ASG
11****
.ASG
.ASG
.ASG
.ASG
.ASG
.ASG
.ASG
.ASG
Tx ~ $800
Rx = $800
EE ~ $900
RES = $900
CD ~ $AOO
CONTROL REGISTER ADDRESSES ******.************************n
RCI = $0000
RC2 = $2000
RC3 = $4000
RC4 = $6000
RCS = $8000
RC6 = $AOOO
RC7 = $COOO
RC8 = $EOOO
"**** READING
& WRITING SIGNAL SAMPLES
************ .. *.***************"
.LIBRARY TXSO ADDIR \
LSL 8 "ADDIR" A \
SVR A $800.E \
LDA "ADDIR" \
SVR A $800.E \
.ENDMAC
.LIBRARY RXSI ADDIR \
OPDI ;LDL $800.E;;LSRB L A \
OPDI ;LDL $800.E;;OR L A,F \ WARNING: FIFO becomes useless
SVR D "ADDIR" \
.ENDMAC
.LIBRARY TXEE ADDIR \
LSL 8 "ADDIR" A \
SVR A $900.E \
LDA "ADUlR" \
SVR A $900.£ \
.ENDMAC
20/29
786
APPLICATION NOTE
.LIBRARY RXRES ADDIR \
OPDI ;LDL $900.E ;;LSRB L A \
OPDI ;LDL $900.E ;;OR L A,F \ WARNING: FIFO becomes llseless
SVR D "ADDIR"\
.ENDMAC
n**** CARRIER DETECT *******************************11
.LIBRARY CD ADDIR\
OPDI ;LDL $AOO.E ;;TRA L A \
SVR A "ADDIR" \
.ENDMAC
"**** CLOCK CONTROL *******************************11
.LIBRARY ReI BIT, BAUD \
OPIM ;LDR RCI,N ; TRA R A \
SVR A $AOO.E \
OPIM ;LDR ( ($"BIr * (2 ** 12 » + ("BAUD" * (2 ** 9» ), N ; TRA R A \
SVR A $BOO.E \
.ENDMAC
.LIBRARY RC2 MUX , FS \ ATTENTION TX SYNC HAS BEEN PUT TO ZERO
OPIM ;LDR RC2,N ; TRA R A \
SVR A $AOO.E \
OPIM ;LDR ( ("MUX'*(2**I3))+('FS'*(2**1l)) ),N; TRA R A \
SVR A $BOO.E \
.ENDMAC
.LIBRAR Y RC2SYNC MUX , FS , K \
OPIM ;LDR RC2,N ; TRA R A \
SVR A $AOO.E \
OPIM ;LDR «"MUX"*(2**I3))+("FS"*(2** 11»+("K"*(2**9))),N; TRA R A \
SVR A $BOO.E \
.ENDMAC
.LIBRARY RXPSA K\
OPIM ;LDR RC7,N ; TRA R A \
SVR A $AOO.E \
OPIM ;LDR ($"K" * (2 ** II)), N; TRA R A \
SVR A $BOO.E \
.ENDMAC
.LIBRARY RXDPLL K\
OPIM ;LDR RC8,N ; TRA R A \
SVR A $AOO.E \
OPIM ;LDR ("K" * (2 ** 12», N; TRA R A \
SVR A $BOO.E \
.ENDMAC
"**** TRANSMITTER CONTROL *******************************11
.LIBRARY SET ATT K\ ATTENTION EXI HAS BEEN PUT TO ZERO
OPIM ;LDR ROi,N ; TRA R A \
SVR A $AOO.E \
OPIM ;LDR ($"K" * (2 ** 12», N ; TRA R A \
SVR A $BOO.E \
.ENDMAC
21/29
787
APPLICATION NOTE
.LIBRARY SET_EXI K\ ATTENTION ATT HAS BEEN PUT TO ZERO
OPIM ;LDR RC4,N ; TRA R A \
SVR A $AOO.E \
OPIM ;LDR ("K" * (2 ** 9», N; TRA R A \
SVR A $BOO.E\
.ENDMAC
"**** RECEIVER CONTROL *******************************"
.LIBRARY RC3 HPF,LPF,RSR\
OPIM ;LDR RC3,N ; TRA R A \
SVR A $AOO.E \
OPIM ;LDR ("HPF" *(2**14)+"LPF"*(2**12)+(%"RSR" (<<) 9) ), N; TRA R A \
SVR A $BOO.E \
.ENDMAC
.LIBRARY SET_AGC K\
OPIM ;LDR RC5,N; TRA R A \
SVR A $AOO.E \
OPIM ;LDR ($"K" * (2 ** 11», N; TRA R A \
SVR A $BOO.E \
.ENDMAC
.LIBRAR Y SET_ CDth K \
OPIM ;LDR RC6,N ; TRA R A \
SVR A $AOO.E \
OPIM ;LDR ($"K" * (2 ** l3», N; TRA R A \
SVR A $BOO.E \
.ENDMAC
INITIALIZATION ############################"
.LIBRARY INIMAFE \
LDK 0 \
ST A $OAOO.E \
INI REAL,SAT ;AMR %1111011\
REPEAT 16 TIMES; REAL,SAT \
BEGIN:
ST A $OBOO.E \
END:
.ENDMAC
"###########
CLOCK TEST ##########################"
.LIBRAR Y IFTXC PC ADDIR \
.
BRANCH BE6;.:pC ADDIR" \
.ENDMAC
-
"############
.LIBRARY IFRXC PC_ADDIR \
BRANCH BE5 "PC_ ADDIR" \
.ENDMAC
22/29
788
APPLICATION NOTE
B.3 -
The library PSIl1
"###############################################################
###### HERE IS DEFINED THE GENERAL LANGUAGE PSILI ##############
######################
V2.21 OCT 86 #####################
#### AUTHOR: D.F MARTIN (33) 76 49 36 00 X3823 #############
################################################################"
.CROSS
.MAP
"**** OPERATION ON ACCUMULATOR A *******************************
** LOA, STA , ADD, SUB, MSUB ,ADDC, AND, OR, XOR, LDK ,COM
ASRA , LSRA , RORA , LSLA "
**
. LIBRARY LDA ADDIR \
OPDI ;LDL "ADDIR";; TRA L A \
.ENDMAC
.LIBRARY STA ADDIR \
SVR A AADDIRA\
.ENDMAC
.LIBRARY ADD ADDIR \
OPDI ;LDL "ADDIRA;; ADD L A A \
.ENDMAC
.LIBRARY SUB ADDIR \
OPDI ;LDL "ADDIRA;; SUBR L A A \
.ENDMAC
.LIBRARY MSUB ADDIR \
OPDI ;LDL 'ADDIRA ;; SUB L A A \
.ENDMAC
.LIBRARY ADvC AVVIK \
OPDI ;LDL "ADDIRA ;; ADDC L A A \
.ENDMAC
.LIBRAR Y AND ADDIR \
OPDI ;LDL AADDIRA ;; AND L A A \
.ENDMAC
.LIBRAR Y OR ADDIR \
OPDI ;LDL "ADDIRA ;; OR L A A \
.ENDMAC
.LIBRAR Y XOR ADDIR \
OPDI ;LDL 'ADDIR" ;; XOR L A A \
.ENDMAC
.LIBRAR Y LDK CONSTANT \
OPIM ;LDR "CONSTANT" ,N; TRA R A \
.ENDMAC
.LIBRARY COM ADDIR \
OPDI ;LDL "ADDIRA;; COM L A \
.ENDMAC
.LIBRAR Y ASRA NN \
OPIN ST A, T\
ASR ANNA T A\
.ENDMAC
~
""1' SCS·1lI0MSON
Ii1AlU~Il1@IiU~Il1@[i\I]U~®
23/29
789
APPLICATION NOTE
.LIDRAR Y LSRA NN \
OPIN ST A, T\
LSR !'NN" T A\
.ENDMAC
.LIBRARY RORA NN \
OPIN ST A, T\
ROR "NN" T A\
.ENDMAC
.LIBRARY LSLA NN \
OPIN ST A, T\
LSL "NN" T A\
.ENDMAC
"•••• OPERATION BETWEEN ACCUMULATORS
.**.** ••********* •• *********
.LIBRAR Y HIDE\
OPIN ST A, T; LDL T;; TRA L,B\
.ENDMAC
.LIBRARY SEEK\
OPIN ST B, T; LDL T;; TRA L,A \
.ENDMAC
"*n* OPERATION WITHOUT MODIFYING ACCUMULATOR
****************************
•• LDD , STD , ADDD , SUBD , MSUBD , ADDCD , ANDD , ORD , XORD , LDKD'
. LIBRARY LDD ADDIR \
OPDI ;LDL "ADDIR" ;; TRA L F \
.ENDMAC
.LIBRARY STD ADDIR \
SVR D "ADDIR"\
.ENDMAC
.LIBRAR Y ADDD ADDIR \
OPDI ;LDL "ADDIRA;; ADD L A F \
.ENDMAC
.LIBRAR Y SUBD ADDIR \
OPDI ;LDL "ADDIRA ;; SUBR L A F \
.ENDMAC
.LIBRARY MSUBD ADDIR \
OPDI ;LDL 'ADDIR" ;; SUB L A F \
.ENDMAC
.LIBRAR Y ANDD ADDIR \
OPDI ;LDL AADDIR";; AND L A F \
.ENDMAC
.LIBRAR Y ORD ADDIR \
OPDI ;LDL "ADDIR" ;; OR LA F \
.ENDMAC
.LIBRARY XORD ADDIR \
OPDI ;LDL AADDIRA ;; XOR LA F \
.ENDMAC
24/29
790
APPLICATION NOTE
.LIBRARY LDKD CONSTANT \
OPIM ;LDR "CONSTANP ,N; TRA R F \
.ENDMAC
"**** OPERATION MEMORY TO MEMORY ****************************
** MOVE, MOVK*
. LIBRARY MOVE SRCADDIR , DSTADDIR \
OPDI ;LDL "SRCADDIR" ;; TRA L F \
SVR D "DSTADDIR"\
.ENDMAC
.LIBRARY MOVK CONSTANT, DSTADDIR\
OPIM ;LDR "CONSTANT" ,N ; TRA R F \
SVR D "DSTADDIR"\
.ENDMAC
"**** OPERATIONS WITH INDIRECT ADDRESSING ***********************
** LD ,ST ,MASK *******.*****************************************n
. LIBRARY LD INDIRADR , REG \
.IF «('AINDIRADR 2 3 "'(=)'EO') (+) ('AINDIRADR 2 3 "'(=)'YI'))
OPIN;
;LDR "INDIRADR" ; TRA R "REG" \
.ELSE
OPIN ;LDL "INDIRADR" ;
; TRA L "REG" \
.ENDIF
.ENDMAC
.LIBRARY ST REG, INDIRADR \
OPIN ST "REG" "INDIRADR"\
.ENDMAC
.LIBRARY MASK INDIRADR , CaNST ANT \
OPIM LDL AINDIRADR" ,M ;LDR "CONSTANP ,N; AND L R A \
.ENDMAC
"ATfENTION: NOT OPERATIONAL WITH POINTERS EO,YI"
,,**** OPERATION ON POINTERS ************** ••• *.****.***.***
****** LDP , INCP , DECP , ADDP , INIP **************
.LffiRAR Y LDP POINTER \
OPDI ST D "POINTER" ;;;\
.ENDMAC
.LIBRARY INCP POINTER \
.IF ( (,"POINTER I 2 "'(=)'EO') (+) (,"POINTER] 2 "'H'YI') )
OPIN ;;LDR [APOINTERA]+ ; \
.ELSE
OPIN ;LDL ["POINTERA]+;; \
.ENDIF
.ENDMAC
.LIBRARY DECP POINTER \
.IF ( ('APOINTER I 2 A'(=)'EO') (+) ('A POINTER I 2 MH'Y]') )
OPIN ;;LDR ["POINTERA]- ; \
.ELSE
OPIN ;LDL [ApOINTERA]- ;; \
.ENDIF
.ENDMAC
25/29
791
APPLICATION NOTE
.LIBRAR Y ADDP POINTER ,NN \
SVR APOINTERA T\
OPIM LDL T M ;LDR ANN" N; ADD L R F\
OPDI ST D "POINTER" \
.ENDMAC
. LIBRARY INIP POINTER ,VALUE \
.IF ( ('''POINTER'''(=)'YO') (+) ("'POINTER"'(=)'Yl') )
INI REAL SAT; "POINTER" "VALUE" ; \
.ELSE
INI REAL SAT;; "POINTER" "VALUE"
.ENDIF
.ENDMAC
"**** OPERATION ON PROGRAM SEQUENCE ***.***************************
*****GOTO ,IFPOS ,IFNEG ,IFCARRY ,IFZERO ,IFNOZERO ,CALLA, PUSHX,
PULLX , WAIT ***************************************************"
.LIBRAR Y GOTO PC_ ADDR \
BRANCH "PC ADDR"\
.ENDMAC
.LIBRAR Y IFPOS PC_ADDR \
BRANCH NOSR ApC ADDRA \
.ENDMAC
.LIBRAR Y IFNEG PC ADDR \
BRANCH SR APC_ADDRA \
.ENDMAC
.LIBRARY IFCARRY PC_ADDR \
BRANCH CR "PC_ADDR" \
.ENDMAC
.LIBRAR Y IFZERO PC ADDR \
BRANCH Z APC_ADDRA \
.ENDMAC
.LIBRAR Y IFNOZERO PC ADDR \
BRANCH NOZ "PC ADDRA \
.ENDMAC
.LIBRARY CALLA \
BRANCH A ; SVPC RAR \
.ENDMAC
.LIBRARY PUSHX PC ADDR\
BRANCH ApC ADDRA; SVPC [Xl]-\
.ENDMAC
.LIBRAR Y PULLX\
INCP XI\
LD [Xl] , A\
BRANCH A\
.ENDMAC
.LIBRARY WAIT COND \
WAIT&: BRANCH NO"COND" WAIT& \
.ENDMAC
26/29
792
APPLICATION NOTE
"••••• DO\ENDO··""'·
.LIBRAR Y DO N \
LDKD AW \
DOBEG&: OPIN ST D T\
.ENDMAC
.LIBRARY ENDO \
OPIM LDL T ;LDR 1 ;SUB L R F \
IFNOZERO (DOBEG& + 1)\
.ENDMAC
"**** OPERATIONS ON AMR *******************************
***.** AMRSLOW , AMRFAST •••• *.********
.LIBRARY AMRSLOW \
INI REAL SAT ;AMR $7F ;\
.ENDMAC
.LIBRARY AMRFAST \
INI REAL SAT ;AMR $7E ;\
.ENDMAC
"****
INITIALIZE MODE *******************************
•••••• REAL, CMPLX , DBPR ••••••••••••••
.LIBRAR Y REAL \
INI REAL SAT \
.ENDMAC
.LIBRARY CMPLX \
INI CMPLX SAT \
.ENDMAC
.LIBRARY DBPR \
INI DBPR NOSA T \
.ENDMAC
"•••• OPERATION ON FLAGS •••••••••••••••• *.*** ••••• *****
•••••• EMPTYFIF , RDYOIN •••• **** ••••••
.LIBRARY EMPTYFIF \
INI REAL SAT ;EF 1 ;\
.ENDMAC
.LIBRARY RDYOINI \
INI REAL SAT ;RDYOIN 1 ;\
.ENDMAC
.END
27/29
793
APPLICATION NOTE
B.4 -
The library PSIUTIL
i'###########################################################
################### HERE ARE THE PSI UTILITIES :PSIUTIL ##############
############################ V2.3
7/10/86 ##########################
###################### authorS: D.F.MARTIN , F.RA YMONDOU ###########
######################################################################*"
CLEAR XRAM ######################"
.LIBRARY XRAMCLR \
REPEAT 128 TIMES ;REAL SAT\
INI REAL SAT;
; XO $00 \
LDK 0\
BEGIN:
OPIN ST A [XO]+\
END:
.ENDMAC
"###############
CLEAR YRAM ######################"
.LlBRAR Y YRAMCLR \
REPEAT 128 TIMES ;REAL SAT\
INI REAL SAT;YO $00
; \
LDK 0\
BEGIN:
OPIN ST A [YO]+\
END:
.ENDMAC
"###############
CLEAR ERAM FIRST 128 ONLY
.LIBRAR Y ERAMCLR \
REPEAT 128 TIMES ;REAL SAT\
INI REAL SAT;
; EO $00 \
LDK 0\
BEGIN:
OPIN ST A [EO]+\
END:
.ENDMAC
"###############
############"
BLOCK MOVE CROM -----> RAM ###########"
.LlBRARY BLCKMOV SRC, LENGTIl, DEST ,POINTER \
LDK "SRCA \
LDP CO \
LDK "DESTA \
LDP "POINTER" \
REPEAT ("LENGTH" - 1) TIMES;REAL,SAT \
"LOOP; PIPELINE OF 1 "
OPIN ; LDL [CO]+ ;; TRA L A \
BEGIN:
OPIN ST A ["POINTER"]+; L'DL [CO]+ ;; TRA L A\
END:
OPIN ST A ["POINTER"]+ \
.ENDMAC
"#########
"#####################################"
.LlBRAR Y TIMEOUT K \
LDK AKA \
LZOOP&: Sr A 1 \
OPIM LDL T , M; LDR 1 ,N ; SUB L R A \
IFNOZERO LZOOP& \
.ENDMAC
28/29
794
APPLICATION NOTE
TIME OUT from 0 to I hour #########################
X T2 ) X 800ns (5 cycles)
2 ** 32 x 800ns ~~~ 3200 s
"###############
######## real: ( Tl
MAX
~
########################################################################"
.LIBRARY TIMEOUTO Tl ,T2 \
LOK ATl A \
OPIN ST AT; LOL T ;;TRA L B\
LOK AT2A \
LZXOOP&:ST A T \
NOP\ for ease of counting cycles
OPIM LDL T , M; LOR I ,N ; SUB L R A \
IFNOZERO LZXOOP& \
ST B T \
OPIM LDL T , M; LOR I ,N ; SUB L R B \
IFNOZERO (LZXOOP& - I )\
.ENOMAC
"#####################################"
.LIBRAR Y INITlMER AODIR , K \
LOK AKA\
STA AADOIR"\
.ENDMAC
"#####################################"
.LIBRARY OECTIMER ADDIR\
LDK 1\
MSUB AADDIRA\
STA "ADDIR"\
.ENDMAC
"######################################"
.LIBRARY INICTR ADDIR \
LDK 0\
STA "ADDIRA \
.ENDMAC
"#######################################"
.LIBRARY INCCTR ADDIR \
LDK I \
ADD "ADDIRA \
STA AADDIRA \
.ENDMAC
29/29
795
DSP APPLICATION NOTE SUMMARY
This summary is the list of all available application notes around SGS-THOMSON digital signal processors
family. These application notes will not be printed in the data-book for space reasons, but are listed here for
convenience.
_ Interfacing the TS68930/31 with D/A converters AM6012, DAC808.
_ Interfacing the TS68930/31 with 8031/51 Intel family of processors.
_ Examples of mailbox communications between two TS68930 and a Modem Analog Front End (MAFE)
chip set.
_ Interfacing the TS68930/31 to analog signals.
_ Lattice filter implementation with SGS-THOMSON DSP's.
_ TS68931 instruction bus optimized interface.
_ Sine and cosine implementation with TS68930/31 routines.
_ TS68930/31 extended data memory applications schematic.
_ Interface schematic for 8086
ho~t
processor to the ST18930/31 digital signal processors.
_ Digital IIR filter development and evaluation programs for the TS68930/31 digital signal processors.
_ Development of real time algorithms using the TS68930/31 DSP and the MAFE chip set.
1/1
797
SALES OFFICES
EUROPE
DENMARK
ITALY
2730 HER LEV
Herlev Torv, 4
Tel. (45-42) 94.85.33
Telex: 35411
Telefax: (45-42) 948694
20090 ASSAGO (MI)
Vie Milanofiori - Strada 4 - Palazzo N4/A
Tel. (39-2) 89213.1 (10 linee)
Telex: 330131 - 330141 SGSAGR
Telefax: (39-2) 8250449
FINLAND
40033 CASALECCHIO 01 RENO (BO)
Via R. Fucini, 12
Tel. (39-51) 591914
Telex: 512442
Telefax: (39-51) 591305
LOHJA SF~08150
Karjalankatu,2
Tel. 12.155.11
Telefax. 12.155.66
FRANCE
94253 GENTILLY Cedex
7 - avenue Gallieni - BP. 93
Tel.: (33-1) 47.40.75.75
Telex: 632570 STMHQ
Telefax: (33-1) 47.40.79.10
67000 STRASBOURG
20, Place des Hailes
Tel. (33) 88.75.50.66
Telex: 870001 F
Telefax: (33) 88.22.29.32
GERMANY
6000 FRANKFURT
G uti eutstrasse 322
Tel. (49-69) 237492
Telex: 176997689
Telefax: (49-69) 231957
Teletex: 6997689~STVBP
8011 GRASBRUNN
Bretonischer Ring 4
Neukeferloh Technopark
Tel.: (49-89) 46006-0
Telex: 528211
Telefax: (49-89) 4605454
Teletex: 8971 07~STDISTR
3000 HANNOVER 1
Eckenerstrasse 5
Tel. (49-511) 634191
Telex 175118418
Teletex: 5118418 csfbeh
Telefax: (49-511) 633552
8500 NORNBERG 20
Erlenstegenstrasse, 72
Tel.: (49-911)59893-0
Telex: 626243
Telefax: (49-911) 5980701
5200SIEGBURG
Frankfurter Str. 22a
Tel. (49-2241) 660 84-86
Telex: 889510
Telefax: (49-2241) 67584
7000 STUTTGART
Oberer Kirchhaldenweg 135
Tel. (49-711) 692041
Telex: 721718
Telefax: (49-711) 691408
00161 ROMA
Via A. Torlon'la, 15
Tel. (39-6) 8443341
Telex: 62Q653 SGSATE I
Telefax: (39-6) 8444474
NETHERLANDS
5652 AR EINDHOVEN
Meerenakkerweg 1
Tel. (31-40) 550015
Telex: 51186
Telefax: (31-40) 528835
SPAIN
08021 BARCELfi?NA
Calle Platon, 64' Floor, 5~ Door
Tel. (34-3) 4143300-4143361
Telefax: (34-3) 2021461
28027 MADRID
Calle Albacete, 5
Tel. (34-1) 4051615
Telex: 27060 TCCEE
Telefax: (34-1) 4031134
SWEDEN
5-16421 KISTA
Borgarfjordsgatan, 13 - Box 1094
Tel.: (46-8) 7939220
Telex: 12078 THSWS
Telefax: (46-8) 7504950
SWITZERLAND
1218 GRAND-SACONNEX (GENEVA)
Chemin Francois-Lehmann, 18/A
Tel. (41-22) 7986462
Telex: 415493 STM CH
Telefax: (41-22) 7984869
UNITED KINGDOM and EIRE
MARLOW, BUCKS
Planar House, Parkway
Globe Park
Tel.: (44-628) 890800
Telex: 847458
Telefax: (44-628) 890391
SALES OFFICES
AMERICAS
ASIA / PACIFIC
JAPAN
BRAZIL
AUSTRALIA
05413 sAo PAULO
R. Henrique Schaumann 286-CJ33
Tel. (55-11) 883-5455
Telex: (391 )11-37988 "UMBR BR"
Telefax: 11-551-128-22367
NSW 2027 EDGECLIFF
Suite 211, Edgecliff centre
203-233, New South Head Road
Tel. (61-2) 327.39.22
Telex: 071 126911 TCAUS
Telefax: (61-2) 327.61.76
TOKYO 108
Nisseki - Takanawa Bid. 4F
2-18-1 0 Takanawa
Minato-Ku
Tel. (81-3) 3280-4121
Telefax: (81-3) 3280-4131
CANADA
BRAMPTON, ONTARIO
341 Main S1. North
Tel. (416) 455-0505
Telefax: 416-455-2606
U.S.A.
NORTH & SOUTH AMERICAN
MARKETING HEADQUARTERS
1000 East Bell Road
Phoenix, AZ 85022
(1)-(602) 867-6100
CHINA
BEIJING
Liason Office
Beijing NO.5 Semiconductor
Device Factory
14 Wu Lu Tong Road
Da Sheng Man Wai
Tel. (861) 2024378
Telex 222722 STM CH
HONG KONG
ALABAMA
Huntsville - (205) 533-5995
WANCHAI
22nd Floor - Hopewell centre
183 Queen's Road East
Tel. (852-5) 8615788
Telex: 60955 ESGIES HX
Telefax: (852-5) 8656589
ARIZONA
Phoenix - (602) 867-6340
INDIA
SALES COVERAGE BY STATE
CALIFORNIA
Santa Ana - (714) 957-6018
San Jose - (408) 452-8585
COLORADO
Boulder (303) 449-9000
ILLINOIS
Schaumburg - (708) 517-1890
INDIANA
Kokomo - (317) 459-4700
MASSACHUSETTS
Lincoln - (617) 259-0300
MICHIGAN
Livonia - (313) 462-4030
NEW JERSEY
Voorhees - (609) 772-6222
NEW YORK
Poughkeepsie - (914) 454-8813
NORTH CAROLINA
Raleigh - (919) 787-6555
TEXAS
Carrollton - (214) 466-8844
FOR RF AND MICROWAVE
POWER TRANSISTORS CONTACT
THE FOLLOWING REGIONAL
OFFICE IN THE U.S.A.
PENNSYLVANIA
Montgomeryville - (215) 362-8500
NEW DELHI 110001
LiasonOffice
62, Upper Ground Floor
World Trade Centre
Barakhamba Lane
Tel. 3715191
Telex: 031-66816 STMIIN
Telefax: 3715192
MALAYSIA
PULAU PINANG 10400
4th Floor - Suite 4-03
Bangunan FOP-123D Jalan Anson
Tel. (04) 379735
Telefax (04) 379816
KOREA
SEOUL 121
8th floor Shinwon Building
823-14, Yuksam-Dong
Kang-Nam-Gu
Tel. (82-2) 553-0399
Telex: SGSKOR K29998
Telefax: (82-2) 552-1051
SINGAPORE
SINGAPORE 2056
28 Ang Mo Kia - Industrial Park 2
Tel. (65) 4821411
Telex: RS 55201 ESGIES
Telefax: (65) 4820240
TAIWAN
TAIPEI
12th Floor
.
571, Tun Hua South Road
Tel. (886-2) 755-4111
Telex: 10310 ESGIE TW
Telefax: (886-2) 755-4008
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for
the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces ali information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems
without express written approval of SGS-THOMSON Microelectronics.
Cover design by Keith & Koppel, Segrate, Italy
Type setting and layout on Desk Top Publishing
by AZIMUT, Henin St., France
© 1991 SGS-THOMSON Microelectronics-All Rights Reserved
Printed by Garzanti, Cernusco SIN, Italy
SGS-THOMSON Microelectronics GROUP OF COMPANIES
Australia - Brazil - China - France Germany - Hong Kong - Italy Japan - Korea - Malaysia - Malta - Morocco - The NetherlandsSingapore - Spain - Sweden - Switzerland - Taiwan - United Kingdom - U.S.A.
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No XMP Toolkit : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37 Create Date : 2013:06:04 12:13:39-08:00 Modify Date : 2013:06:04 12:38:37-07:00 Metadata Date : 2013:06:04 12:38:37-07:00 Producer : Adobe Acrobat 9.55 Paper Capture Plug-in Format : application/pdf Document ID : uuid:3757e603-0004-7f48-8173-bb424dc69d18 Instance ID : uuid:1bd5e23b-3110-1143-8140-64866816ead1 Page Layout : SinglePage Page Mode : UseNone Page Count : 802EXIF Metadata provided by EXIF.tools