1989_Samsung_MOS_Products_Data_Book 1989 Samsung MOS Products Data Book
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c8 SAMSUNG
MOS Products
Data Book
1989
IEC/INTEGRATED ELECTRONICS CORP.
2360 Qume Drive
SUite F
San Jose, California 95131
Phone (408) 435-1000 .
FA)( (408) 435-8709
Q-_ -Jim-Reese,
J
Oln~~~;:.:;,,~____
QUALITY and RELIABILITY
2.1 RELIABILITY TESTS
Samsung has established a comprehensive reliability program to monitor and ensure the ongoing reliability of the
MOS IC family. This program involves not only reliability data collection and analysis on existing parts, but also
rigorous in·line quality controls for all products.
Listed below are details of tests performed to ensure that manufactured product continues to meet Samsung's
stringent quality standards. In line quality controls are reviewed extensively in later sections.
The tests run by the quality department are accelerated tests, serving to model "real world" applications through
boosted temperature, voltage, and/or humidities. Accelerated conditions are used to derive device knowledge through
means quicker than that of typical application situtations. These accelerated conditions are then used to assess
differing failure rate mechanisms that correlate directly with ambient conditions. Following are summaries of
major stresses (and their conditions) run by Samsung on MOS IC products.
HIGH TEMPERATURE OPERATING LIFE TEST (HOPL)
(Tj=125·C, Vee = Vee max, static)
High temperature operating life test is performed to measure actual field reliability. Life tests of 1000HR to 2000HR
durations are used to accelerate failure mechanisms by operating the device at an elevated ambient temperature
(12S·C). Data obtained from this test are used to predict product infant mortality, early life, and random failure
rates. Data are translated to standard operating temperatures via failure analysis to determine the activation
energy of each of the observed failures, using the Arrhenius relationship as previously discussed.
WET HIGH TEMPERATURE OPERATING LIFE TEST (WHOPL)
(Ta=8S·C, R.H.=85%, Vee = Vee opt, static)
Wet high temperature operating life test is performed to evaluate the moisture resistance oharacteristics of plastic
encapsulated components. Long time testing is performed under static bias conditions at 8S·C/85 percent relative
humidity with nominal voltages. To maximize metal corrosion, the biasing configuration utilizes low power levels.
HIGH TEMPERATURE STORAGE TEST (HTS)
(Ta= 125·C, UNBIASED)
High temperature storage is a test in which devices are subjected to elevated temperatures with no applied bias.
The test is used to detect mechanical instabilities such as bond integrity, and process wearout mechanisms.
PRESSURE COOKER TEST (PCT)
(121·C, 15PSIG, 100% R.H., UNBIASED)
The pressure cooker test checks for resistance to moisture penetration. A highly pressurized vessel is used to
force water (thereby promoting corrosion) into packaged devices located within the vessel.
TEMPERATURE CYCLING (TIC)
(- 65·C to + 150·C, AIR, UNBIASED)
This stess uses a chamber with alternating temperatures of - 65·C and + 150·C (air ambient) to thermally cycle
devices within it. No bias is applied. The cycling checks for mechanical integrity of the packaged device, in
particular bond wires and die attach, along with metal/polysilicon microcracks.
THERMAL SHOCK (TIS)
(-65·C to + 1S0·C, LIQUID, UNBIASED)
'This stress uses a chamber with alternting temperatures of -65·C to + 150·C (liquid ambient) to thermally cycle
devices within it. No bias is applied. The cycling is very rapid, and primarily checks for die/package compatibility.
c8SAMSUNG
15
II
QUALITY and RELIABILITY
Table 1. Reliability Test Items for MOS Product
No.
Test Item
1
Visual Inspection
Critical
Major
Minor
2
Electrical Test
Critical
Major
Minor
Test Condition
Qualification
Product ReI. Monitor
Corrective
Test Method Sample LTPD Acceptance Sample LTPD Acceptance
Size
NBR
Size
NBR
Outgoing Visual Spec
116
116
116
2
3
5
0
1
2
116
116
116
2
3
5
0
1
2
Outgoing Test Spec
116
116
116
2
3
5
0
1
2
116
116
116
2
3
5
0
1
2
0
50
-
-
0
45
10
1
1
45
10
1
3 Dimension
VIS/MECH Criteria
50
4 Packing Inspection
Outgoing Packing
Criteria
Each Lot
5 Operating Life Test
Ta=25'C
Vee = Vee (max)
1000 HRS
MIL·STD·883
1005
45
10
1
MIL·STD·883
1005
45
10
Each Lot
6
High Temperature
OPL
Ta= 125'C Static
Vce = Vee (max)
1000 HRS
7
Low Temperature
Storage
Ta= -55°C
1000 HRS
45
10
1
45
10
1
8
High Temperature
Storage
Ta= 125'C
1000 HRS
45
10
1
45
10
1
45
10
1
45
10
1
MIL·STD·883
1011
45
10
1
45
10
1
MIL·STD·883
1010
45
10
1
45
10
1
260'C±5°C
10±1 Sec
Once without FI ux
45
10
.
I
45
10
1
Ta=121'C±2'C
RH=1oo%
9 Pressu re Cooker Test
15 PSIG
168 HRS
10
Liquid
Thermal Shock Test
-55°C~150°C
5 min, <10 Sec, 5 min
200 Cycles
-65°C~25°C~150°C
11 Temperature Cycle
12 Solder Heat Resist
10 min, 5 min, 10 min
200 Cycles
13
Wet High Temp.
Storage
Ta=85'C, RH=85%
1000 HRS
45
10
1
45
10
1
14
Wet High Tem·
perature OPL
Ta=85'C, RH =85%
Vec=Vee (TYP)
1000 HRS
45
10
1
45
10
1
=8SAMSUNG
16
QUALITY and RELIABILITY
Table 1. Reliability Test Items for MOS Product (Continued)
No.
Test Item
Qualification
Product Rei. Monitor
Corrective
Sample
Acceptance
Sample
Acceptance
Test Method
LTPD
LTPD
Size
NBR
Size
NBR
Test Condition
15 Moisture Resistance
9O-98%/65'C 3 HRS
80- 98%/25'C 8 HRS
90-98%/65'C 3 HRS
MIL·STD·883
10004
45
10
1
45
10
1
16 Lead Integrity
1) Wire Lead
0.229 ± 0.0144kg
for Three
90 ± 5' Arcs on
each Leads
Bending Cycle:
2 5 Sec
2) Dial·in·lines
MIL·STD·883
2004
32
7
0
32
7
0
17 Solderability
260'C± 10'C
Preconditioning
1 HRS.
MIL·STD·883
2003
22
10
0
22
10
0
Marking
18
Permanancy
Rub Marking with Ten
Stokes of a Cotton
Cloth Damped with
Solvents
22
10
0
22
10
0
MIL·STD·883
2002
32
7
0
32
7
0
_ ...
19 Mechanical Shock
Pulse Duration:
0.1 1m Sec
Shock Pulse: 0.5
3kg
-"
20 Vibration Fatique
20G·3 Axis
Orientations
f = 20 to 2000 CPS
for 4 Minute Cycle
MIL·STD·883
3007A
32
7
0
32
7
0
Constant
Acceleration
20000G
X, Y, Z Axis
1 min for each Axis
MIL·STD·883
2001
32
7
0
32
7
0
Nacl
Ta=35'C, 24 HRS
MIL·STD·883
1009A
45
10
1
45
10
1
-
32
7
0
32
7
0
0
5
0
32
21
22 Salt Atmosphere
-
23 Set Aging
1-- c----'-'
24 ESD
C=200pF
R = 1.5K
Su Ifide Corrosion
25
Test
Ta=25±2'C
Humidity: 75% R/H
S02: 10±2ppm
Velocity: 0.006
0.007m/s
c8SAMSUNG
..
MIL·STD·883
3015
DOD·HDBK·263
5
DIN 40046
32
-
7
-
0
7
0
17
II
QUALITY and RELIABILITY
Table 2. Failure Criteria for MOS Product
Parameter
Output Drive Current (P·CH)
Output Drive Current (N·CH)
Output High Voltage
Output Low Voltage
Input Cu rrent
Quiescent Current
Voltage Margin
AC Characteristic Open/Short
Gross/Fine Leak Visual
Color Disturbance Soldering
Marking Disturbance
Symbol
IDP
IDN
VOH
VOL
liN
IL
Life End Limit
Unit
Min
Max
LSLXO.9
LSLXO.9
LSLXO.9
USLX1.1
USLX1.1
A
A
USLX1.1
USLX2.0
USLX2.0
O.95XUSL
+O.05XLSL
USLX1.1
V
V
A
-
-
O.05XUSL
+O.95XLSL
LSLXO.9
V
Sec
Individual Spec
Note: LSL: Lower Specification limit
USL: Upper Specification Limit
c8SAMSUNG
18
QUALITY and RELIABILITY
II
2.2 METHODOLOGY OF RELIABILITY TEST
RELIABILITY
Reliability can be loosely characterized as long term product quality.
There are two types of reliability tests: those performed during design and development, and those carried out
in production. The first type is usually performed on a limited sample, but for long periods or under very accelerated
conditions to investigate wearout mechanisms and determine tolerances and limits in the design process. The
second type of tests is performed periodically during production to check, maintain, and improve the assured quality
and reliability levels. All reliability tests performed by Samsung are under conditions more severe than those
encountered in the field, and although accelerated, are chosen to simulate stresses that devices will be subjected
to in actual operation. Care is taken to ensure that the failure modes and mechanisms are unchanged.
FUNDAMENTALS
A semiconductor device is very dependent on its conditions of use (e.g., junction temperature, ambient tempera·
ture, voltage, current, etc.). Therefore, to predict failure rates, accelerated reliability testing is generally used. In
accelerated testing, special stress conditions are considered as parametrically related to actual failure modes.
Actual operating life time is predicted using this method. Through accelerated stresses, component failure rates
are ascertained in terms 'of how many devices (In percent) are expected to fail for every 1000 hours of operation.
A typical failure rate versus time of activity graph is shown below (the so-called "bath tub curve")
(t)
Reduction. due to
-----..."...-------"t/C---.--preventive maintenance
m=1
Failure I--.....l.....
rate
SemicondUct
- - . . . .. -.- __
(m :::: 0 5
. -
Specified
Failure Rate
oor DeVIces
.95)
Initial
Random Failure period
Failure period
Wear-Out Failure period
Figure 3. Failure Rate Curve ("Bath Tub Curve")
During their initial time period, products are affected by "infant mortality," intrinsic to all semiconductor technologies.
End users are very sensitive to this parameter, which causes early assembly/operation failures in their own
system. Periodically, Samsung reviews and publishes life time results. The goal is a steady shift of the limits as
shown below.
~:~~re
\*'' '--T''""-----:"''
i
I
16t
6: failure rate
/
I
--TIME
Figure 4. Failure Rate
c8SAMSUNG
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QUALITY and RELIABILITY
ACCELERATED HUMIDITY TESTS
To evaluate the reliability of products assembled in plastiC packages, Samsung performs accelerated humidity
Test (WHOPL).
stressing, such as the Pressure Cooker Test (PCT) and Wet High Temperature Operating
Life
Figure 5 shows some results obtained with these tests, which illustrate the improvements in recent years. These
improvements result mainly from the introduction of purer molding resins, new process methods, and improved
cleanliness.
10-'L25~-40-:':---:eo:--~80:--1=OO:--1:::25::--:1::50:--1eo=-=200::-::T=I(C)
Figure 5. improvement in Humidity Reliability
ACCELERATED TEMPERATURE TESTS
Accelerated temperature tests are carried out at temperatures ranging from 75·C to 200·C for up to 2000 hours.
These tests allow Samsung to evaluate reliability rapidly and economically, as failure rates are strongly dependent
on temperature.
The validity of these tests is demonstrated by the good correlation between data collected in the field and laboratory
results obtained using the Arrhenius model. Figure 6 shows the relationship between failure rates and temperatures
obtained with this model.
1980
,
99.9
99
,
80
II!
3
70
50
1982
--------------------~
I:
w
5
5
I
1985
1988
I
/
I{
~./.
,
/
1
0.5
O. 1
10
102
HOURS
Figure 6. Failure Rate Versus Temperature
c8SAMSUNG
20
QUALITY and RELIABILITY
2.3 FUNDAMENTAL THEORY FOR ACCELERATED TESTING
Accelerated life testing is powerful because of its strong relation to failure physics. The Arrhenius model, which
is generally used for failure modelling, is explained below.
Arrhenius model
This model can be applied to accelerated Operating Life Tests and uses absolute (Kelvin) temperatures.
L=A+EalK·Tj
L : Lifetime
A : Constant
Ea : Activation Energy
K : Boltzman's constant
Tj : Absolute Junction temperature
If Lifetimes L1 and L2 correspond to Temperatures T1 and T2,
L1 = L2 exp
[~a (T11
-
T~ D
,/
L1
Lifetime(L)
T2
Temperature 11T (0 K -1)
Actual junction temperature should always be used, and can be computed using the following relationship.
Tj=Ta+(Px (jja)
Where Tj = Junction temperature
Ta = Ambient temperature
P = Actual power consumption
ja=Junction to Ambient thermal resistance (typically 100 degrees celsius/watt for a 16·Pin DIP).
e
Activation Energy Estimate
Clearly the choice of an appropriate activation energy, Ea, is of paramount importance. The different mechanisms
which could lead to circuit failure are characterized by specific activation energies whose values are published
in the literature. The Arrhenius equation describes the rate of many processes responsible for the degradation
and failure of electronic components. It follows that the transition of an item from an initially stable condition to
a defined degraded state occurs by a thermally activated mechanism. The time for this transition is given by an
equation of the form:
MTBF = B EXP (EalKT)
MTBF = Mean time between failures
B
= Temperature·independent constant
MTBF can be defined as the time to suffer a device degradation. The dramatic effect of the choice of the Ea value
can be seen by plotting the MTBF equation. The acceleration effect for a 125°C device junction stress with respect
to 70°C actual device junction operation is equal to 1000 for Ea= 1eV and 7 for Ea=0.3eV.
c8
SAMSUNG
21
II
QUALITY and RELIABILITY
Some words of caution are needed about published values of Ea:
A. They are often related to high-temp tests where a single Ea (with high value) mechanism has become dominant.
B. They are specifically related to the devices produced by that supplier (and to its technology) for a given period
of time
C. They could be modified by the mutual action of other stresses (voltage, mechanical, etc.)
D. Field device-application condition(s) should be considered.
Table 3. Activation energy for each failure mode
THE CORRECT PROCEDURE
Failure Mechanism
Ea
Contamination
Polarization
Aluminum Migration
Trapping
Oxide Breakdown
Silicon Defects
1 -1.4 eV
1 eV
0.5 -1 eV
1 eV
0.3 eV
0.3-0.5 eV
ACCELERATED TEST
I
CALCULATED AT TEST CONDITIONS
AND WITH A CERTAIN CONFIDENCE
LEVEL
FAILURE ANALYSIS
I
CHOICE OF Ea---CALCULATED AT OTHER
TEMPERATURES
Time
1.4ey r---1 eV
106
~
1()5
B
/
1;l 10'
0.8e~
/
./
LL
c:
0.5~
0
~
"
«"
"
a;
./
103
J /
102
/. ' /
1QL
100
./
..",- . "
O.4e~
./
."..,..,
0.3 eV-
,.-
~
250
200 175 150 125
100
75
50
Junction Temperature
Figure 7_ Acceleration Factor vs Activation Energy
c8SAMSUNG
22
QUALITY and RELIABILITY
2.4 Failure Rate Prediction
Accelerated testing defines the failure rate of products. By derating the data at different conditions, the life
expectancy at actual operating conditions can be predicted. In its simplest form the failure rate (at a given temperature)
is:
N
FR=OH
Where FR= Failure Rate
N =. Number of failures
D = Number of components
H = Number of testing hours
If we intend to determine the FR at different temperatures, an acceleration factor must be considered. Some failure
modes are accelerated via temperature stressing based upon the accelerations of the Arrhenius Law.
For two different temperatures:
Ea
1
1
FR (T1) = FR (T2) exp [ K (T2 - T1
)J,l
FR (T1) is a point estimate, but to evaluate this data for an interval estimate, we generally use alA:'" (chi square)
distribution. An example follows:
Failure Rate Elaluation
Unit: %/1000HR
Dev. x Hours
at 125°C
Fail
1.7x106
2
Failure Rate at 60% Confidence Level
Point Estimate
1
85°C
I
70°C
I
55°C
0.18
I
0.0068
I
0.0018
I
0.00036
The activation energy, from analysis, was chosen as 1.0 eV based upon test results. The failure rate at the lower
operating temperature can be extrapolated by an Arrhenius plot.
c8SAMSUNG
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II
QUALITY and RELIABILITY
Process Monitor (Continued)
Spec. Limit
Control Item
Process
Thin Film
• Cooling Water Temp.
o Thickness
CVD
o
o
Diffusion
o
o
o
o
o
o
Pin Hole
Thickness
o
Tube Temp.
C·V Plot Run
Tube
Sheet Resistance
Thickness
o
o
o
o
o
o
Insp. Frequency
26±3°C
Individual Spec.
Once/Shift
Once/Shift
Individual Spec.
Individual Spec.
Once/Shift
Once/Shift
Individual
Individual
Individual
Individual
Individual
Once/Shift
Once/Shift
Once/10days
Once/Shift
Once/Shift
Spec.
Spec.
Spec.
Spec.
Spec.
Raw Material Incoming Inspection
1. Mask Inspection
Defect Detection
Pinhole & Clear·extension
Opaque Projections &
Spots
o Scratch/Particle/Stain
o Substrate Crack/Glass·chip
• Others
o
All Masks
o
o
o
Registration
o
Run.out
(X·Y Coordinate)
Orthogonality
Drop·in Accuracy
Die Fit/Rotation
o
Critical Dimension
o
o
o
Critical
Dimension
Defect Size::s; 1.S).tm
Defect Density
::s;0.124EA/cm2
±0.7S).tm
20%
o
±0.7S).tm
±O.SO).tm
±O.SO).tm
All New Masks
Purchasing Spec.
All Masks
• Instrument
o Auto mask inspection system for defect·detection (NJS SMD·44)
o Comparator for registration (MVG 7X7)
o Automatic linewidth measuring system for CD (MPV·CD)
2. Wafer Inspection
Purpose
Insp. Items
Sample
Remarks
Structural
o
Crystallographic Defect
All Lots
o
Sirtl Etch
Electrical
o
Resistivity
Conductivity
All Lots
o
Monitor Water
o
-Dimensional
---
Visual
---Thickness---o Diameter
o Orientation
o Flatness
o
o
Surface Quality
Cleanliness
---
-----
----All lots
--- --
TTV, NT'v, EpFfhickness-
TIR (FPD)
Local Slope
All Lots
Purchasing Spec.
• Instrument
o 4 paint probe for resistivity (Kokusai VR·40A, Tencor sonogage, ASM AFPP)
o Flatness measuring system (Siltec)
o Epi. layer thickness gauge (Digilab FTG·12, Qualimatic S·100)
o Automatic Surface Insp. System (Aeronca Wis·1S0)
o Non·contact thickness gauge (ADE6034)
c8SAMSUNG
24
QUALITY and RELIABILITY
3. PROCESS CONTROL
GENERAL PROCESS CONTROL
The general process flow in Samsung is shown in Figure 8. This illustration contains the standard process flow
from incoming parts and materials to customer shipment.
Acceptance inspection (according to acceptance inspection plan)
Process quality control
• Check of each condition by process quality control procedures
• Process inspection
• Lot control
• Equipment calibration and maintenance
100% Electrical Die Sorting
Process Quality Control and screening of infant mortality defects
• Mechanical screen
• Thermal shock
• Burn-in
100% package sorting of electrical characteristics and marking
Reliability monitoring
1. Product reI. monitor I.
2. Product rei. monitor II.
• High Temperature Operating Life Test
• Environmental test
• Life Test
Finished Goods
Incoming
Inspection
Sampling Inspection
• Dimensions
• Visual
• Electrical characteristics
• Periodic calibration of measuring equipment
Stock control
• Age control
Sampling Inspection (when applicable)
Shipment
Figure 8. General Process Flow Chart
c8SAMSUNG
25
II
QUALITY and RELIABILITY
3.1 WAFER FABRICATION
Process Controls
The Quality Control program utilizes the following methods of control to achieve its previously stated objectives:
process audits, environmental monitors, process monitors, lot acceptance inspections, and process integrity audits.
Definitions
The essential method of the Quality Control Program is defined as follows:
1. Process Audit-Performed on all operations critical to product quality and reliability.
2. Environmental Monitor-Monitors concerning the process environment, i.e., water purity, temperature, humidity,
particle counts.
3. Process Monitor-Periodic inspection at designated process steps for verification of manufacturing inspection
and maintenance of process average. These inspections provide both attribute and variable data.
4. Lot Acceptance-Lot-by-Iot sampling. This sampling method is reserved for those operations deemed as critical,
and require special attention.
Environmental Monitor
Process
Control Item
Clean Room
•
•
•
•
D.1. Water
• Particle
• Bacteria
• Resistivity
Temperature
Humidity
Particle
Air Velocity
Spec. Limit
•
•
•
•
Individual
Individual
Individual
Individual
Insp. Frequency
24
24
24
24
Spec.
Spec.
Spec.
Spec.
Hrs.
Hrs.
Hrs.
Hrs.
24 Hrs.
Weekly
24 Hrs.
• 5 ea/50ml (O.BIL)
• 50 colonies/100ml (0.45IL)
• Main (Line): More than
16 Mohm-cm
• Using point: More than
14 Mohm-cm
24 Hrs.
* Instruments
•
•
•
•
•
•
FMS (Facility Monitoring System) HIAC/ROYCO
CPM (Central Particle Monitoring System-Dan Scientific)
Liquid Dust Counter Etch Rate
Filtration System for Bacterial check
Air Particle counter
Air Velocity meter
Process Monitor
Process
Photo
---- - - - -
------
Etch
c8SAMSUNG
Control Item
• Aligner N2 Flow Rate
• Aligner Vacuum
----------·-AI i g nerAr f• Aligner Pressure
• Aligner Intensity
o Coater Soft Bake
Temperature
Vacuum
• Etchant Temp.
• Etch Rate
• Spin Dryer N2 Flow
RPM
• Hard Bake Temp.
N2 Flow
Spec. Limit
• Individual Spec.
• Individual Spec.
---'--rndividliarSpec.
• Individual Spec.
o Individual Spec.
o Individual Spec.
o Individual Spec.
o Individual Spec.
o
o
o
o
o
o
Individual
Individual
Individual
Individual
Individual
Individual
Spec.
Spec.
Spec.
Spec.
Spec.
Spec.
Insp. Frequency
---
Once/Shift
Once/Shift
--- Once/Shift
Once/Shift
Once/Shift
Once/Shift
Once/Shift
Once/Shift
-------
Once/Shift
Once/Shift
Once/Shift
Once/Shift
Once/Shift
Once/Shift
26
QUALITY and RELIABILITY
II
In·Process Quality Inspection (FA B)
1. Manufacturing Section
Process Step
Process Control Insp.
Frequency
Oxidation
Oxide Thickness
All Lots
Di'ffusion
Oxide Thickness
Sheet Resistance
Visual
All Lots
All Lots
All Lots
Photo
Critical Dimension
Visual
Mask Clean Inspection
All Lots (MOS)
All Lots
All Masks with Spot Light (MOS)
or Microscope (BIP)
Etch
Critical Dimension
Visual
All Lots
All Wafers
Thin Film
Metal Thickness
Visual
All Lots
All Lots
Ion Implant
Sheet Resistance
All Lots (Test Wafer)
Low Temp.
Oxide
Thickness
All Lots
Visual
All Lots
E·Test
Electrical Characteristics
All Lots
Fab. Out
Visual
All Wafers
2. FAB, QC Monitor/Gate
Process Step
FAB, QC Insp.
Frequency
Oxidation
Oxide Thickness
C·V Test on Tubes
Visual
Once/Shift
Once/10 Days and After CLN
Once/Shift
Diffusion
Oxide Thickness
C-V Test on Tubes
Visual
Once/Shift
Once/10 Days and After CLN
Once/Shift
Photo
Critical Dimension
Visual
Mask CLN Inspection
All Lots (MOS)
Once/Shift
All Masks After 10 Times Use
Etch
Critical Dimension
Visual
All Lots (MOS)
All Lots
Thin Film
C-V Test on Tubes
on Lots
Reflectivity
Once/10 Days and After CLN
Once/Shift
Once/Shift
Low Temp.
Oxide
Refractive Index,
Wt% of Phosphorus
Visual
1 Test Wafer/Lot
1 Test Wafer/Lot
1 Test Wafer/Lot
E·Test
Measuring Data
All Lots
Calibration
Instrument for Thickness
and C.D. Measuring
Once/week
c8SAMSUNG
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QUALITY and RELIABILITY
3. Photo/Etch process quality control
Process Flow
Proces·s Step
MFG. Control Item
QC Monitor/Gate
Prebake
Oven PM, Temperature
Time
Photo Resist (PR)
-spin
Thickness Machine PM
Soft Bake
Oven PM, Temperature
Time
Temp. N2 Flow Rate
Align/Expose
Light Uniformity
Alignment, Focus Test
Mask Clean Inspection
Mask Clean Exposure
Light Intensity
Light Intensity
Mask Clean Insp.
Develop
Equipment PM
Solution Control
Vacuum
Develop
Check
PR/C.D.'S Alignment
Particles
Mask and Resist Defects
QC Inspection
Oven Particle Temp.
N2 Flow Rate
Critical Dimension (CD)
Hard Bake
Oven PM, Temperature
Time
Temp.
N2 Flow Rate
Etch
Etch rate, Equipment
PM & Settings, Etch
Time to Clear
Etchant Temp.
Etch Rate
Inspection
Ov'er/Under
PR Strip
Machine·PM
Final Check
C.D.'S Over and under
Etch, Particles,
PR Residue, Defects,
Scratches
QC Inspection
Same as Final Check,
However, More Intense
on limited Sample
Basis. (AQL 6.5%)
Note: PM-FepFesents PreveFttive-Malntenance-----4. Reliability·related Interlayer Dielectric, Metallization, and Passivation Process Quality Control Monitor
Item
Wt% Phosphorus Content of the Dielectric Glass
Frequency
1/Shift
Metallization Interconnect
1/Month
AI Step Coverage
1/Month
Metallization Reflectivity
1/Shift
Passivation Thickness and Composition
1/Shift
Thin Film Defect Density
1/Shift
c8SAMSUNG
28
QUALITY and RELIABILITY
II
Figure 9. General Wafer Fabrication Flow
Process Flow
Process Step
Major Control Item
Wafer and Mask
Input
Starting Material
Incoming Inspection
Mask: (See mask Inspection)
Wafer: (See wafer Inspection)
Wafer Sorting and
Labelling
Resistivity
Initial Oxidation
Oxide Thickness
Photo
• (See manufacturing section)
• (See FAB, QC Monitor/gate)
I
I
Inspection
• Critical Dimension
• Visual/Mech - Major: AQL 1.0%
- Minor: AQL 6.5%
QC Gate
• Critical Dimension
Etch
• (See manufacturing section)
• (See FAB, QC Monitor/gate)
Inspection
• Critical Dimension
• Visual/Mech - Major: AQL 1.0%
- Minor: AQL 6.5%
QC Gate
• Critical Dimension
• Visual/Mech
Diffusion
Metalization
• (See in·process Quality Inspection)
E·test
• Electrical Characteristics
Ditt'n
Metal
6
y
c8SAMSUNG
29
QUALITY and RELIABILITY
Figure 9. General Wafer Fabrication Flow (Continued)
Process Flow
Process Step
<>
Major Control Item
QC Gate
• Electrical Characteristics
Back-Lap
• Thickness
Back Side Evaporation
• Thickness, Time
Evaporation Rate
Final Inspection
• All Wafers Screened
(Visual/Mech)
QC Fab. Final Gate
• Visual/Mech.
- Major: AQL 1.0%
- Minor: AQL 6.5%
EDS
(Electrical Die Sorting)
QC Gate
• Function Monitor
Sawing
---
----
---
--
--
----
,--
--
-----
--
----
---
'
-,
Inspection
• Chip Screen
QC Final Inspection
•
•
•
•
----
----
-,
--- -
AQL 1.0%
Fab. Defect
Test Defect
Sawing Defect
Die Attach
c8SAMSUNG
30
QUALITY and RELIABILITY
3.2 ASSEMBLY
The process control and inspection pOints of the assembly operation are explained and listed below:
1. Die Inspection:
Following 100% inspection by manufacturing, in-process Quality Control samples each lot according to internal
or customer specifications and standards.
2. Die Attach Inspection:
Visual inspection of samples is done periodically on a machine/operator basis. Die Attach techniques are monitored
and temperatures are verified.
3. Die Shear Strength:
Following Die Attach, Die Shear Strength testing is performed periodically on a machine/operator basis. Either
manual or automatic die attach is used.
DIE ADHESIVE THICKNESS MONITOR RESULTS. (JEOL SEM, JSM IC845)
4. Wire Bond Inspection:
Visual inspection of samples is complemented by a wire pull test done periodically during each shift. These
checks are also done on a machine/operator basis and XR data is maintained.
5. Pre-Seal/Pre-Encapsulation Inspection:
Following 100% inspection of each lot, samples are taken on a lot acceptance basis and are inspected
according to internal or customer criteria.
WIRE LOOP MONITOR RESULTS.
c8SAMSUNG
CROSS SECTION INSPECTION FOR BALL BOND.
31
QUALITY and RELIABILITY
6. Seal Inspection:
Periodic monitoring of the sealing operation checks the critical temperature profile of the sealing oven for both
glass and metal seals.
7. Post·Seal Inspection:
Subsequent to a 100% visual inspection, In·Process Quality Control samples each for conformance to visual
criteria.
X·RAY MONITOR RESULT. (PHILIPS MG161)
8. General Assembly Flow is shown in Figure 11.
Sampling Plans
1. Sampling plans are based on an AQL (Acceptable Quality Level) concept and are determined by internal or by
customer specifications.
2. Raw Material Incoming Inspection. (confinued)
Inspection Item
Material
1)
2)
3)
4)
Lead Frame
--Wafer-
--
----
AulAI
Wire
--
Visual Inspection
Dimension Inspection
Function Test
Work Test
IfViSuannspecff6n
1) Visual inspection
2) Bond Pull Strength Test
3) Bondability Test
4) Chemical Composition Analysis
1) Visual Inspection
2) Moldability Test
Molding Compound
3) Chemical Composition Analysis
c8SAMSUNG
Acceptable Quality Level
LTPD
LTPD
LTPD
LTPD
-
10%,
20%,
20%,
20%,
C=2
C=O
C=O
C=O
AQL 0.65%
LTPD 20%, C=O
LTPD 15% C=2
Critical Defect: LTPD 1.5% C=6
Major Defect: LTPD 1.5% C=6
Minor Defect: LTPD 1.5% C=6
n:4,C=0
n:5,C=0
Critical Defect: LTPD 0.15%
Major Defect: LTPD 1.0%
Minor Defect: LTPD 1.5%
n:5,C=0
32
QUALITY and RELIABILITY
MOLDING COMPOUND INCOMING INSPECTION
(THERMAL ANALYSER, DUPONT 9900)
(Continued)
Material
Inspection Item
Visual Inspection
Dimension Inspection
Electro-Static Inspection
Hardness Test
Acceptable Quality Level
Packing Tube
& Pin
1)
2)
3)
4)
Solder
1) Visual Inspection
2) Weight Inspection
3) Chemical Composition Analysis
LTPD 20% C=O
LTPD 20% C=O
LTPD 20% C=O
Flux
1) Acidity Test
2) Specific Gravity Test
3) Chemical Composition Analysis
LTPD 20% C=O
LTPD 20% C=O
LTPD 20% C=O
Solder Preform
1) Visual Inspection
2) Work Test
3) Chemical Composition Analysis
AQL 2.5%
AQL 2.5%
AQL 2.5%
Coating Resin
1) Visual Inspection
2) Work Test
3) Chemical Composition Analysis
AQL 1.0%
AQL 1.0%
AQL 1.0%
1) Work Test
2) Mark Permanency Test
Critical Defect: 0.15%
Major Defect: 1.0%
Minor Defect: 1.5%
n: 5, C=O
Chip Carrier
1)
2)
3)
4)
Visual Inspection
Dimension Inspection
Electro-Static Inspection
Hardness Test
LTPD 15% C=2
LTPD 15% C=O
n: 5, C=O
n: 5, C=O
Vinyl Pack
1) Visual Inspection
2) Work Test
3) Electro-Static Inspection
LTPD 20% C=O
LTPD 20% C=O
LTPD 15% C=O
Ag Epoxy
1) Work Test
2) Chemical Composition Analysis
AQL2.5%
AQL2.5%
Letter Marking
1) Visual Inspection
2) Work Test
100% Inspection C=O
Spare Parts
& Others
1) Dimension Inspection
2) Visual Inspection
AQL 0.65%
LTPD 20%
Marking Ink
c8SAMSUNG
LTPD 15%, C=2
n:10,C=0
n:10,C=0
n: 10, C=O
33
QUALITY and RELIABILITY
3. In·Process Quality Inspection
A. Assembly Lot Acceptance Inspection
(1) Acceptance quality level for wire bond gate inspection
Defect Class
Critical Defect
Major Defect
Minor Defect
Inspection Level
AQL 0.65%
AQL 1.0%
AQL 1.5%
Type of Defect
-
Missing Metal
Chip Crack
No Probe
Epoxy on Die
Mixed Device
Wrong Bond
Missing Bond
-
Diffusion Defect
Ink Die
Exposed Contact
Bond Short
Die Lift
Broken Wire
-
Metal Missing
Metal Adhesion
Pad Metal Discolored
Tilted Die
Die Orientation
Partial Bond
-
Oxide Defect
Probe Damage
Metal Corrosion
Incomplete Wetting
Weakened Wire
-
Adjacent Die
Passivation Glass
Die Attach Defect
Wire Loop Height
Extra Wire
-
Contamination
Ball Size
Wire Clearance
Bond Deformation
(2) Acceptance quality level for MoldlTrim gate inspection
Defect Class
Inspection Level
Critical Defect
AQL 0.10%
-
Incomplete Mold
Void, Broken Package
Misalignment
-
Deformation
No Plating
Broken Lead
Major Defect
AQL 0.4%
-
Ejector Pin Defect
Package Burr
Flash on Lead
-
Crack, Lead Burr
Rough Surface
Squashed Lead
Lead Contamination
Poor Plating
Package Contamination
Bent Lead
AQL 0.65%
-
-
Minor Defect
Kind of Defect
B. In-process monitor inspection
~------Inspection- ----._----
.Die Shear Test
• Bond Strength Test
• Solderability Test
• Mark Permanency Test
• Lead Integrity Test
• In-Process Monitor
Inspection for Product
• X-Ray Monitor
Inspection for Molding
• Monitor Inspection
for Production Equipment
• Compound Thermal Analysis
c8SAMSUNG
-----ErequencY------- c------ -------Beference---
--~--
Each Lot
Each Lot
Weekly
1 Time/EquipmentlDay
Weekly
4 Times/Shift/Each Process
MIL·STD-883C, 2019·2
MIL-STD-883C, 2011-4
MIL·STD-883C, 2003-3
MIL-STD-883C, 2015·4
MIL-5TD-883C, 2004-4
Identify for Each Control Limit
2 Times/Shift/Mold Press
Identify for Each Control Limit
2 Times/Shift/Each Unit of
Equipment
3 Equipment/ShifUDay
Identify for Each Control Limit
Identify for Each Control Limit
34
QUALITY and RELIABILITY
II
4. Outgoing quality inspection plan (LTPD)
Defect Class
Critical Defect
electrical
visual
Major
Minor
Discrete
LSI
Kind of Defect
1%
2%
Open, short
Wrong configuration, no marking
Defect
electrical
visual
1.5%
3%
Items which affect reliability most strongly
Defect
electrical
visual
2%
5%
Items which minimally or do
not affect reliability at all
(cosmetic, appearance, etc.)
c8SAMSUNG
35
QUALITY and RELIABILITY
Figure 10. General Assembly Flow
Process Flow
Process Step
Major Control Item
Wafer
Wafer Incoming
Inspection
Q.C. Wafer Incoming Inspection AQL 4.0%
Tape Mount
Sawing Q.C. Monitor
Q.C. Monitoring:
- Chip·out
- Crack
- Sawing·speed
- 0.1. Purity
-
Visual Inspection
100% Screen:
- FAB Defect
- EDS Test Defect
- Sawing & Scratch Defect
Q.C. Gate
1st AQL 1.0%
Reinspection AQL: 0.65%
Scratch
Sawing Discoloration
Cut Count
CO2 Bubble Purity
Lead Frame (UF)
Lead Frame Incoming
R>
~.-----
Die Attach (D/A)
Q.C. Monitor
1--- -----.--I-----~---~~---~--
Yl
c8SAMSUNG
*Q.C.UF Incoming Inspection
1. Acceptance Quality Level
- Dimension LTPD 20%, C=O
- Visual & Mechanical: LTPD 10%, C=2
- Functional Work Test: LTPD 20%, C=O
*Q.C.D/A Monitor Inspection
1. Bond force
2. Frequency: 4 Times/Station/Shift
3. Sample: 24 ea Time
4. Acceptance Criteria
~
-
1--
~-
--~------~--
-----
--
--------
~------------
Defect
Acceptance
Critical
0
1
Major
1
2
---
Reject
Cure
36
QUALITY and RELIABILITY
Figure 10. General Assembly Flow (Continued)
Process Flow
Process Step
O.C. Monitor
I
<>
Major Control Item
"O.C. Cure Monitor Inspection
1. Control Item
- Temperature
- In/out Time
2. Frequency
- 1 Time/Shift
Au Wire
Bonding Wire
Incoming Inspection
r
"O.C Au Wire Incoming Inspection
1. Visual Inspection: N 5, C 0
2. Bond Pull Test Strength Test: N
3. Bondability Test
- Critical Defect: AOL 0.65%
- Major Defect: AOL 1.0%
- Minor Defect: AOL 1.5%
=
=
=13, C =0
Wire Bonding (W/B)
100% Visual
Inspection
O.C. Monitor
O.C. Gate
"O.C. W/B Monitor Inspection
1. Frequency: 4 Times/Mach/Shift
1. O.C. Acceptance Ouality Level
- Critical Defect: AOL 0.65%
- Major Defect: AOL 1.0%
- Minor Defect: AOL 1.5%
Mold Compound
Incoming Inspection
Mold
"Moldability Test
- Critical Defect: AOL 0.15%
- Major Defect: AOL 1.0%
- Minor Defect: AQL 1.5%
Mold
O.C. Monitor
c8SAMSUNG
"O.C. Mold Monitor Inspection
1. In-Process Monitor Insp~ction
- Frequncy: 4 Times/Station/Shift
- Sample: 200 UnitslTime
2. Acceptance Ouality Level
- Critical Defect: AOL 0.25%
- Major Defect: AOL 0.4%
37
QUALITY and RELIABILITY
Figure 10. General Assembly Flow (Continued)
Process Flow
Process Step
n
Major Control Item
Cure
a.c. Monitor
~6
-a.c. Cure Monitor Inspection
1. Control Item
- Temperature
- In/out Time
2. Frequency
- 1 Time/shift
Deflash
a.c. Monitor
-a.c. Deflash Monitor Inspection
1. Control Item
- Pressure
- Belt Speed
- Visual/Mechanical Inspection
2. Frequency: 4 Times/Mach/Shift
3. Identify each Defect Control Limit
I
TRIM/BEND
~.
)--
=?
-
=8SAMSUNG
a.c. Monitor
-a.c. Trim/Bend Monitor Inspection
1. Visual Inspection
2. Frequency: 4 Times/Station/Shift
Solder
100% Visual Inspection
a.c. Monitor
-a.c. Solder Monitor Inspection
1. Frequency: 4 Times/Mach/Shift
2. Criteria
- Critical Defect: AaL 0.25%
- Major Defect: AaL 0.4%
a.c. Gate
-a.c. Mold Gate
- Acceptance Criteria
Critical Defect: AaL 0.10%
-----
----
--
-----
----
._.
Ma:jorDefecf:AaL...()AO/~"
- ---
-
Minor Defect: AaL 0.65%
Test
100% Electrical Test
a.c. Monitor
Correlation Sample Reading for Initial
Device Test
Mark
100% Visual Inspection
38
QUALITY and RELIABILITY
Figure 10. General Assembly Flow (Continued)
Process Flow
<>
0
Process Step
Major Control Item
PRT Monitoring
(Product Reliability
Monitor)
1. PRT
- HOPL, PCT
- Other (when applicable)
2. Acceptance Criteria: LTPD 10%
Q.C. Monitor
'Q.C. Marking Monitor Inspection
- Frequency: 4 Times/Station/Shift.
- Sample: 24 UnitslTime
- Identify for Each C.L.
- Acceptance Criteria
Defect
Acceptance
I
Critical
0
1
I
Major
1
2
I
I
<>
Q.C. Gate
'Q.C. Final Acceptance Level
- Critical Defectg: AQL 0.10%
- Major Defect: AQL 0.4%
- Minor Defect: AQL 0.65%
Q.A. Gate
'Q.A. Incoming Inspection
1. Critical Defect:
- Electrical Test: LTPD
- Visual Test:
LTPD
2. Major Defect:
- Electrical Test: LTPD
- Visual Test:
LTPD
3. Minor Defect:
- Electrical Test: LTPD
- Visual Test:
LTPD
Reject
2% (N = 116, C = 0)
2% (N=116, C=O)
3% (N=116, C=1)
3% (N=116, C=1)
5% (N = 116, C = 2)
5% (N=116, C=2)
Stock
'Age Control
Q.A. Gate
'Q.A. OutgOing Inspection
1. Quantity
2. Customer
3. Packing
4. Sampling Inspection (when applicable)
- Sampling plan is same as incoming
Inspection
Shipment
c8SAMSUNG
39
NOTES
_Ii
;
.l~
- - - - _ .. _ - - -
PRODUCT GUIDE
1. FUNCTION GUIDE
A. CMOS LCD Watch ICs
.
. .
f/)
g)
u::
f/)
~
C
.....
~
'tI
'tI
:::J
LL
=
.~
CD
I(
CD
CD
c
::!!
c
.....
KS5112
6
-
1
-
*
KS5198
3.5
KS5199A 3.5
- -
KS5184
7
*
*
*
-
6
4
KS5190
6
7
KS5194
4
- 4
- -
tKS5114
3.5
4
Q.
Q.
:::J
'C
-
• * • -
"'
0
.....
0
0
:§I
c
>-
~haracteristic
c
c
Device
Electrical
Additional Features
Function
Display
CD
0.
. . ..... E.
It)
f/)
III
I!I0
.....>>C
CD
0
CD
e :cE
0
0
li
~
j::
>
c
c
E
- - - - - * • • - * - - -
* * .* * Flag
- - - - - * •
• Flag - • *
• - - * * - - - -
Remark
c
oJ:
c
z:
0
C
II)
Ci
>
.5
z:
0.
f!
g)
C
-
Ii
..c
.....>- ::!!
1.5 0.8 1.5
1.5 0.8 1.5
Intemal
Capacitor
1.5 0.8 1.5
1.5 1.0 2.0
Chrono (11100
1.5 1.0 2.0
sec, 24HR)
1.5 1.0 2.0
1.5 0.8 1.5
Intemal
Capacitor
B. CMOS Analog LCD Watch
Electrical Characteristic
Display
KS5113
100
Function
Device
Hand
Segment
LCD duty
3
120
116
Voo (V)
3
1.5
!!.tA)
Typ
Max
1.5
2.5
Remark
Intemal Capacitor
C. CMOS Analog Watch
Electrical Characteristic
Function
Device
,
tKS5243
1.5
3 Hand Analog Watch
(nA)
Typ
Max
Osc.
(Hz)
170
300
32768
100
Voo (V)
Remark
Extemal Trimmer Capacitor
D. CMOS Analog Clock ICs
Electrical Characteristic
Device
KS5206
KS5207
KS5209
KS521 0
KS5211
Feature
A: 0.5Hz Square Wave
Pulse Output
E: 0.5Hz 46.9ms
Duration Pulse Output
F: 0.5Hz 31.2ms
Duration Pulse Output
c8SAMSUNG
100
Voo (V)
!!.tA)
Typ
Max
Osc.
(Hz)
Package
Remark
2048Hz Alarm
1.5
1.5
2.5
32,768
8 DIP or Chip
1.5
1.5
2.5
32,768
8 DIP or Chip
1 HR Function
1.5
1.0
2.0
32,768
8 DIP or Chip
2048Hz Alarm
1.5
0.7
2.0
32,768
8 DIP or Chip
2048Hz Alarm
1.5
0.7
2.0
32,768
8 DIP or Chip
No Trimmer
43
II
PRODUCT GUIDE
E Calculator ICs
Device
Calculator
Function
Additional Function
100
Voo(V)
(JlA)
Typ
Max
Package
Remark
KS6025
Basic
Auto Power Off
1.5
6
9
48 FQP
Solar Cell
KS6026
Basic
Auto Power Off
1.5
5.6
9
48 FQP
Solar Cell
KS6027A
Desk Top
-
1.5
7.0
15
Bare Chip
Solar Cell
tKS6027B
-
-
1.5
7.0
15
60 FQP
Solar Cell
tKS6027C
Basic
-
3.0
7.0
15
60 FQP
-
tKS6028
Basic
1.5
1.3
3
48 FQP
Solar Cell
tKS6029
KS6041
Auto Power Off
Basic
Auto Power Off
1.5
1.5
3
48 FQP
Solar Cell
Scientific
Auto Power Off
3.0
70
120
48 FQP
-
F. Voice Synthesizer ICs
Device
Synthesis Method
Voo(V)
Maximum Memory
Package
LPC
5
64K Bytes
60 FQP
KS5901A
Remark
KS5902
LPC
5
48K Bits
24 DIP
Internal ROM
KS5911
ADM
5
256K DRAMx4
48 FOP
External DRAM
KS5912
ADM
5
64K Bits
16 DIP
Internal ROM
ttKS5915
ADM
5
1M DRAM x4
60 FQP
External DRAM
--
G. Melody ICs
Device
Time Base
Title
(Hz)
Voo
(V)
KS5310
Series
KS5310A
Oh! Susanna
32,768
1.5
Minuet (BACH)
Cuckoo's Waltz
Oh! Susanna
Home Sweet Home
Big Ben
For Elise
33,000
1.5
KS5313
Series
KS5313N
KS·5313P
KS5313R
KS5313Q
KS5313S
KS5313T
KS5814
Sky· Lark's or
Cricket's Sound
KS5814
----
KS5401
ttKS5401A
210,000
-
--
8 Sound effect
1.5
---
-
125,000
Package
Remark
Bare Chip
1 Melody
Bare Chip
(At Watch)
Stand-By
0.1·0.3
Operating
20·30
KS5313:
16 DIPI
8 DIP
KS5313
Speaker or
Piezo Drive
Stand· By
0.1·0.3
Operating
250~400 _
14 DIP
Stand·By
0.4·1.5
Operating
300-600
18 DIP
loo(JlA)
3
-
--
Speaker
-
-- ---
I
I
Speaker
H. Miscellaneous
Device
Function
Voo (V)
100
lilA)
Typ
Max
Package
KS5815
3.5 Digits Clinical Ther!T'0meter
1.5
-
100
Bare Chip
KS5116
6 Digit UplDown Counter
1.5
9
18
Bare Chip
t New Product
Remark
"tt Under Develop
c8SAMSUNG
44
-
PRODUCT GUIDE
2. CROSS REFERENCE GUIDE
Application
SAMSUNG
OKI
SEIKO
TOSHIBA
KS5184
LCD Watch
LC5641
KS5198
MSM5001N
KS5199A
MSM5001N
KS5189
MSM5066
KS5190
MSM5066
KS5194
MSM5004
--
KS5112
tKS5114
Analog LCD
Watch
Analog Watch
KS5113
Others
JT6649A·CS
MSM5001N
e1331
STP55721
MSM5008
e1208
tKS5243
KS5205
KS5206
Analog Clock
UM3262
KS5209
KS5210
e1444
KS5211
RCA92461
KS5310A
SVM7952
KS5313
SVM7920
Melody
CIC3821
CIC3822
KS5814
MN6223
ttKS5401A
HT·88
KS6025
Ll3128
KS6026
Calculator
t KS6027 AlBIC
UM3135
T6899
---
tKS6028
tKS6029
KS6041
Voice
Synthesizer
Miscellaneous
Ll3135
SC6992
KS5901A
T6721
KS5902
T6803
SP0255, LC8100
KS5911
T6668
UM5101
KS5912
T6667
CIC560
KS5915
TC8831F
CIC5500
KS5815
JT6690·AS
KS5116
t New Product
tt Under Development
c8SAMSUNG
45
II
PRODUCT GUIDE
3. ORDERING INFORMATION
KSV
3100A
r__
N
C
A+
~
BURN-IN (OPTIONAL)
(SEE BURN-IN PROGRAM)
PACKAGE TYPE
' - - - - - - - - - - - TEMPERATURE RANGE
'---_ _ _ _ _ _ _ _ _ _ _ _ DEVICE NUMBER AND SUFFIX (OPTIONAL)
A: IMPROVED VERSION
' - - - - - - - - - - - - - - - - - - - - D E V I C E FAMILY
TEMPERATURE RANGE
BLANK
PACKAGE TYPE
CODE
SEE INDIVIDUAL SPEC
C
COMMERCIAL 0 _ + 70°C
I
INDUSTRIAL -25-+85°C
-40-+85°C
M
MILITARY - 55 - + 125°C
D
J
N
S
0
E
B
P
INTEGRATED CIRCUIT
KA
LINEAR IC
KS
CMOS IC
-KT-LM
Tl:tECO~IC--
W
U
L
PL
---
NATIONAL
MC-
MOTOROLA
NE
SIGNETICS
KSV
AID-D/A CONVERTER
KAD
AID CONVERTER
KDA
D/A CONVERTER
c8SAMSUNG
--
M
H
Z
V
A
T
X
G
PKG. TYPE
SOIC
CERAMIC DIP
PLASTIC DIP (300/600 mil)
SIP
FOP
SD (400 mil)
SSD (Skinny Shrink DIP)
(400 mil. Small Pitch)
SHD (Shrink DIP)
(300 mil. Small Pitch)
ZIP
PGA
LCC
PLCC
TO-3
TO-3P
TO-92
TO-92L
TO-126
TO-220
TO-247
BARE CHIP
46
4
! \
I
1 CMOS LCD ",Itch ICs
2. CMOS Analod Clock ICs
3. CMOS Analog Watch lOs
i
CMOS LCD Watch ICs
Device
KS5112
KS5113
KS5114
KS5184
KS5190
KS5194
KS5199A
Function
Package
5 Functions 6 Digits Watch for Triplexed LCD
3 Hands LCD Analog Watch
5 Functions 3.5 Digits Watch for Duplexed LCD
6 Functions 6 Digits Alarm Watch with Chime
for Duplexed LCD
6 Functions 6 Digits Alarm Watch with Chronograph
and Chime for Duplexed LCD
5 Functions 4 Digits Alarm Watch with Chime for
Duplexed LCD
5 Functions 3.5 Digits Watch for Duplexed LCD
Bare
Bare
Bare
Bare
Page
Chip
Chip
Chip
Chip
49
56
64
70
Bare Chip
74
Bare Chip
80
Bare Chip
84
CMOS Analog Clock ICs
Device
KS5206
KS5207
KS5209
KS5210
KS5211
Function
Bipolar
Bipolar
Bipolar
Bipolar
Bipolar
Stepping
Stepping
Stepping
Stepping
Stepping
Motor
Motor
Motor
Motor
Motor
Drive
Drive
Drive
Drive
Drive
Analog
Analog
Analog
Analog
Analog
Package
Clock
Clock
Clock
Clock
Clock
8
8
8
8
8
DIP
DIP
DIP
DIP
DIP
or
or
or
or
or
Chip
Chip
Chip
Chip
Chip
Page
90
95
100
104
109
CMOS Analog Watch IC
Device
KS5243
Function
3 Hands Analog Watch
Package
Bare Chip
Page
113
CMOS DIGITAL INTEGRATED CIRCUIT
KS5112
5-FUNCfION 6-DIGIT WATCH CIRCUIT FOR
TRIPLEXED LCD.
The KS5112 is a CMOS LSI which contains all logic necessary to im·
plement of a five function six digits liquid crystal display watch. The
circuit contains an oscillator amplifier with an internal feedback resis·
tor for the use of 32,768Hz quartz crystals. The circuit operates from
a single 1.5 volt battery and contains internal voltage doubler. Only 2
switches are required to control all-functions: These switch inputs have
pull down resistor and be debounced by internal circuitry.
FUNCfIONS
•
•
•
•
•
•
•
5 functions: Month, Date, Hour, Minute and Second
12 hour format.
Selectable display Hour, Minute, Second I Month, Date.
One touch correction of time error within ± 30 seconds.
2 switch sequential operation.
4 year calendar.
LCD test
FEATURES
•
•
•
•
•
•
•
•
•
One chip C-MOS con~ruction.
Drives 6 digits trlplexed LCD.
Colon and PM display.
Low power consumption.
32,768Hz crystal oscillator.
Single 1.SV battery operation.
Built-in voltage doubler circuit.
Built-in crystal oscillator input capaCitor.
Trimmer capaCitor Included
ABSOLUTE MAXIMUM RATINGS (Ta =25°C)
Characteristics
Supply Voltage (VOD1 - Vss)
Supply Voltage (VOD2 - Vss)
Operating Temperature
Storage Temperature
Symbol
Vos,
VDS2
Top,
Tstg
Value
-0.3 - +2.0
-0.3 - +4.0
-20 -+75
-55 -+125
Unit
V
V
°C
°C
* Voltage greater than above may damage the circuit.
c8SAMSUNG
49
CMOS DIGITAL INTEGRATED CIRCUIT
KS5112
ELECTRICAL CHARACTERISTICS
Characteristic
Operating Voltage
Symbol
(Ta = 25°C, Voo = 1.5V, Vss = OV; unless otherwise specified)
Test Condition
Min
Typ
Max
Unit
V
V OO1
1.2
1.5
1.8
V OO2
2.4
3.0
3.6
V
0.8
1.5
fJ-A
Without Load
Supply Current
100
Input High Voltage
V,H
Voo - 0.3
Voo
V
V'L
Vss
Vss + 0.3
V
0.1
3
fJ-A
1.45
V
Input Low Voltage
Switch Activation Current
Isw
Vi,=V OO
Oscillator Start Voltage
Vose
Within 5 Sec
Oscillator Stop Voltage
VosP
Oscillator Frequency
Fose
DC-DC Conversion Frequency
FeoN
LCD Frequency
Oscillator Capacitor
Switch Debouncing Time
c8SAMSUNG
0.5
1.15
32,768
V
Hz
1,024
Hz
Fd
43
Hz
Gin
20
pF
Cout
20
pF
Tdeb
C1 = C2 = 0.1fJ-F
31.25
mSEC
50
KS5112
CMOS DIGITAL INTEGRATED CIRCUIT
FUNCTIONAL DESCRIPTION
Two switchs (D and S) are required to control all display and setting of function.
A) Display Control
Hours, minutes and seconds are displayed, colon remains stationary in normal mode.
Month and date are displayed by depressing O-switch.
If D-switch is not depressed continuously, the display will return to normal mode (Hours, minutes and seconds)
after 2 seconds.
B) Setting Control
1. Second
Depressing S·switch in normal mode will cause second correction mode. Second display will flash at a 2Hz rate
in this mode. D-switch is used to correct second within ± 30 seconds. After seconds correction, the display
will return to normal mode (Hours, minutes and seconds).
2. Hour
Depressing S-switch in second correction mode will cause "Hour set" mode and hour display will flash at a
2Hz rate. D-switch is used to advance contents of selected state. If O-switch is depressed continuously, contents will be advanced at a 4Hz rate.
3. Minute
The next depressing of S-switch will select "Minute set" mode and minute display will flash at a 2Hz rate. Minute
can be advanced as above.
4. Month
The next depressing of S-switch will select "Month set" mode and month display will flash at a 2Hz rate.
5. Date
The next depressing of S-switch will select "Date set" mode and date display will flash at a 2Hz rate.
6. Return
The next depressing of S-switch will return to normal display mode.
c8SAMSUNG
51
II
CMOS DIGITAL INTEGRATED CIRCUIT
KS5112
OPERATIONAL DIAGRAM
I
1
2 seconds
(Auto return)
o
Normal display mode
#
HH: MM 55
s
Month/date display mode
MOOT
o
o
(Second correction within ±30 seconds)
..
"Second correction"
#; Colon is not flashing
and remains stationary.
HH: MM 55
* *; Digits flash at a 2Hz rate.
S
..
'Hour set" mode
o (Advance)
HH: MM 55
I
S
..
"Minute set" mode
o (Advance)
HH: MM 55
I
S
..
"Month set" mode
-----
--
D-(Advance)
Mcfbr--
I
I
S
"Date set" mode
.*
o (Advance)
MOOT
S
c8SAMSUNG
I
52
CMOS DIGITAL INTEGRATED CIRCUIT
KS5112
APPLICATION
• The voltage doubler circuit is formed by connecting O.OS"F to O.1~ capacitor from 'CAP' PAD to '1KO' PAD and from ·VDD2'
PAD to 'VSS' PAD.
• Oscillator circuit is formed by connecting crystal from '01' PAD to '00' PAD.
• The circuit substrate is electrically connected to Vss, the most negative voltage. The preferred assembly method
is to connect die area to Vss using a conductive die attach.
• The watch can operate with 1.SV silver oxide battery and user should connect 'VDD' PAD to 1.SV, VSS to OV.
TESTING
• T1, T2 and T3 PAD are provided for testing. In normal operation they should be kept open.
• Three test inputs and two switches are pulled down by internal resistors.
LCD FORMAT
...J
0
i
0
(J
~
!!i!
u
III
c8SAMSUNG
B
'w~"
~
~
~III
;Z
0
ill
~
~
III
~
~
ill
~
~
53
CMOS DIGITAL INTEGRATED CIRCUIT
KS5112
APPLICATION CIRCUIT
LCD
COM1
COM2 COM3
vss
00
x-laiD
C2:
01
O.1~F
VDD2
KS5112
1KO
C1:
S
O.1~F
CAP
D
VDDl
VSf
+
1.SV
* Quartz Crystal Parameter
---,----."--------------
Fp = 32,768Hz
CL = 10pF
C1 = 4pF
Co
2.5pF
Rs
35KO
=
= 35;000---------
_ _ _ _ _ _ _ . __________
---_0-------
_______________ . _______
~
__
~
______________________ _
~---Q--~-
c8SAMSUNG
54
CMOS DIGITAL INTEGRATED CIRCUIT
KS5112
PAD DIAGRAM
(2340, 1560)
00GJ00000~G0~
G
GJ
KS5112 PAD DIAGRAM
Chip Size : 2340 x1560
PAD Size : 98x98
Unit
: I'm
GJ
@]
G
G
~
~
y
~ ~
(0,0)
~
@]
~ ~ ~
0
-x
COORDINATES OF PAD
Pad No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Name of Pad
COM1
BC, /BiCOL
F2/EiD2
A 2/G 2/C 2
AD:JF:JEa
FJB:JGa
AJGJD.
BJCJE5
ADsfF5/G5
PM/BsfC5
AelFelE6
BelGelD6
CelEJCa
COM2
c8SAMSUNG
(Unit I'm)
Coordinates
X
V
129
230
390
550
710
870
1030
1190
1350
1510
1670
1830
1990
2211
789
1431
1431
1431
1431
1431
1431
1431
1431
1431
1431
1431
1431
1431
Pad No.
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Name of Pad
COM3
Vss
VOO2
S
D
V OOl
T3
T2
Tl
Vss
CAP
lKO
01
00
Coordinates
1---X
2211
2211
2211
2211
2501
1874
1711
1494
1137
449
289
129
129
129
---
V
1261
526
366
206
129
129
129
129
129
129
129
285
457
629
55
KS5113
CMOS DIGITAL INTEGRATED CIRCUIT
3 HAND LCD ANALOG WATCH
The KS5113 is a silicon-gate CMOS LSI for 3-HAND analog LCD display
watch. It provides three functions (HOUR, MINUTE, SECOND).
It connects the analog LCD panel with 120 segments type.
The KS5113 has 20 segment outputs and 6 common outputs for direct
drive of 1/6 duty multiplexing LCD.
It operates on single 1.5V battery and the circuit time base is a 32,768Hz
crystal oscillator.
FUNCTIONS
o
3 Function: HOUR, MINUTE, SECOND.
o Time setting: Minute up setting.
o
1 switch operation.
FEATURES
One chip CMOS construction.
1/6 duty multiplex LCD drive.
o Single 1.5V battery operation.
o Voltage doubler, voltage tripler.
o Lower power consumption.
o 32,768Hz Crystal frequency.
o Built-in voltage doubler, voltage tripler circuits.
o Trimmer capacitor included.
o
o
c8SAMSUNG
56
CMOS DIGITAL INTEGRATED CIRCUIT
KS5113
ABSOLUTE MAXIMUM RATINGS (Ta = 25°C)
Characteristic
Supply Voltage (VOD1 - Vss)
Supply Voltage (Voo, - VSS)
Supply Voltage (V003 - Vss)
Operating. Temperature
Storage Temperature
Symbol
Value
Unit
VOS1
Vos,
VOS3
-0.3 -+2.0
-0.3 -+4.0
-0.3 -+6.0
-20 -+ 75
-55 -+125
V
V
V
°C
°C
Topr
T'lg
• Voltage greater than above may damage the circuit
ELECTRICAL CHARACTERISTICS
Characteristic
Operating Voltage
Symbol
(Ta=25°C, Voo = 1.5V, Vss=oV; unless otherwise specified)
Test Condition
Min
Typ
Max
Unit
VOO1
1.2
1.5
1.8
V
V oo,
2.4
3.0
3.6
V
3.6
4.5
5.4
V
1.5
2.5
p.A
V
VOO3
Supply Current
100
Without Load
Input High Voltage
V ,H
Voo -0.3
Voo
Input Low Voltage
V'L
Vss
Vss + 0.3
V
Switch Activation Current
Isw
V in = Voo
3
p.A
Vose
Within 5 Sec
1.45
V
1.15
V
Oscillator Start Voltage
Oscillator Stop Voltage
Fose
DC-DC Conversion Frequency
FeoN
Osci lIator Capacitor
Switch Debouncing Time
c8SAMSUNG
0.5
Vosp
Oscillator Frequency
LCD Frequency
0.1
32,768
Hz
1,024
Hz
Fd
43
Hz
Cin
20
pF
Cout
20
Tdeb
C12 = CD2 = CD3 = 0.1p.F
pF
31.25
mSEC
57
CMOS DIGITAL INTEGRATED CIRCUIT
KS5113
FUNCTIONAL DESCRIPTION
1. Voltage Tripier
The battery voltage (1.5V) can be doubted and tripled by connecting external capacitor C02, C03 and C12 to the
on-ohip voltage doubler and tripler as shown in Fig. 1.
1.5V
VOD1
vss
C2
C1
VOD3
VOD2
r
C12
Vss=OV
V001 =1.5V
V002=3.0V
roo
VDD3=4.5V
CD3=CD2=C12=O.1,F
vss
VOD1
Fig. 1. Voltage Tripier
2. Chattering Prevention
The on chip chatter killer network provided for switch prevent possible error caused by chatter as shown in Fig. 2.
nUnUnIU
_____1
I
I
~
InUnUnc.....
U
L____
Tet
I
f---Tst~
I
let
Tct:s33.3 msec (maxmum switch
chattering time.)
Tst:s60msec(minimumstabletime)
t--
Fig. 2. Chattering
3. Initial Set
Initial state is shown in Fig. 3.
--
-- Initial State-
Base Watch Mode
- -
---
----
Time--
(AM) 00:00 00
--
--
- - - Display-
-
----
QJ
Fig. 3.
c8SAMSUNG
58
CMOS DIGITAL INTEGRATED CIRCUIT
KS5113
TEST FUNCTIONS
T1
T2
T3
AC
o
0
0
0
sw
f-------+------+----.-f---.-~~
Clock
..- -~-------- ..
0
f-------f-------f--------f-------f-
Clock
.
o
__. _ - - _ . -
-~------
Function
Normal
I-----------~---------
Test 256Hz drive
..-.~-------~------
Test 8Hz drive
._--------
Clock
0
Clock
Minute display & TEST
f-------+------f------f--------f------.----f-----------------.
Clock
0
Clock
Hour display & TEST
f - - - - - - - + - - - - - - f - - - - - - . f - - - - - - - - - ---------.--- f---~--.~---------1
Initial SET
f - - - - - - - - + - - - - - - - + - - - - - - - - - j - - - - - - - - - . - - - . - - . - - - - - - - 1 - - - - - - - - - -..- - - - - 1
LAMP TEST
o
Switch Operation
1) Normal mode.
The normal mode will be displayed with three HANDS (HOUR, MINUTE, SECOND). Second is advanced at 1Hz
rate, minute is advanced at 60 second rate, and hour is advanced at 6, 18, 30, 42, 54 minute.
2) Time setting.
When switch SW is depressed less than 1 second, the minute HAND advances + 1 step with the second HAND
returning to "0".
If switch SW is depressed over 1-2 second, the minute HAND advances at 8Hz rate with the second HAND remaining "0" and the hour HAND advances according to the minute HAND.
A) Depressing switch SW less than 1 second.
Minute HAND will be advanced + 1.
Second HAND will be returned to "0".
B) Depressing switch SW over 1·2 second.
Minute HAND will be advanced at 8Hz rate.
Second HAND stays "0".
C) Switch SW released.
c
~
: Second hand
I :Minute hand
I : Hour hand
Fig. 4. Switch operation.
c8SAMSUNG
59
CMOS DIGITAL INTEGRATED CIRCUIT
KS5113
APPLICATION CIRCUIT
ED
A
y--
TI
Segment out
(Sl-S20)
X-tal
C12
~
00
L_
t
COMou1
(COM1-COMS)
VOD3
01
VDD2
C2
KS5113
HO.
HO~
vss
15v_l
C1
VOD1
SW
~o-
C12=CD2=CD3=0_1JLf
Fig. 5. Application Circuit
Quartz Crystal Parameter
32~768Hz --CL
10pF
C1 = 4pF .
Co = 2.0pF
Rs = 35KO
Q = 35,000
- rp =
=
c8SAMSUNG
60
KS5113
CMOS DIGITAL INTEGRATED CIRCUIT
LCD FORMAT
I
r - - - I-
Fig. 6. COMMON SIDE
c8SAMSUNG
61
CMOS DIGITAL INTEGRATED CIRCUIT
KS5113
LCD .FORMAT
(Continued)
fig>] SEGMENT SlOE-
c8SAMSUNG
62
CMOS DIGITAL INTEGRATED CIRCUIT
KS5113
PAD LAYOUT
(1940,2050)
~
~
0
~
~0
0
~
G
0
~
~
EJ
KS5113 PAD DIAGRAM
Chip Size : 1940x2050
PAD Size : 98x98
Unit
: I'm
0
G
G
0
G
y
~
EJ
EJ
~
~
EJ
~
~
G
(0,.0)
II
0
0
0
0
@] ~ ~ @J ~
0
~
@J
---x
KS5113 PAD LOCATION
Pad
No.
Coordinates
Pad Coordinates Pad
Name
No.
y
X
X
y
Pad
No.
00
1447
1921
11
S6
129 1409
2
01
1273
1921
12
S16
3
C2
1090
1921
13
S15
4
C1
930
1921
14
5
S19
710
1921
15
6
S9
504
1921
7
S8
298
8
S18
129
9
10
1
Pad
Name
(Unit: I'm)
Pad Coordinates Pad
Name
No.
y
X
Pad
Name
Coordinates
y
X
1811
21
SW
466
129
31
COM5
129 1249
22
VOOl
639
129
32
COM4
1811
700
129
1089
AC
799
129
929
T1
972
129
129
33
34
COM3
COM2
1811
1811
860
S5
23
24
1020
S4
129
769
25
T2
1145
129
35
COM1
1811
1180
16
S14
129
609
26
T3
1318
129
36
S1
1811
1340
1921
17
S13
129
449
27
Vss
1491
129
37
S11
1811
1500
1921
18
S3
129
289
28
V OO2
1651
129
38
S10
1811
1660
S17
129 1729
19
S2
129
129
29
VOO3
1811
220
39
S20
1811
1820
S7
129 1569
20
S12
306
129
30
COM6
1811
380
-
-
-
-
=8SAMSUNG
540
63
KS5114
CMOS DIGITAL INTEGRATED CIRCUIT
FUNCTIONS 3.5 DIGITS WATCH CIRCUIT
FOR DUPLEXED LCD.
The KS5114 is low threshold voltage, ion implanted metal gate CMOS
integrated circuit which provides all signals to drive a duplexed 3,5
digits liquid crystal display with colon (Fig. 1).
32.768Hz frequency from crystal controlled oscillator is divided
to provide SECOND,.MINUTE, HOUR, DATE and MONTH information.
Phase controlled segment outputs and two Phase controlled back piane
outputs are provided for direct drive of the duplexed LCD.
The KS5114 contains inverter/amplifier, output attenuating resis·
tor, capacitor and feed back resistor to drive the crystal.
The frequency of oscillator is divided to provide 512Hz outPut pulse
used as signal for the voltage doubler.
FUNCTIONS
5 functions: Month, Date, Hour, Minute and Second.
Selective altemation of TIME·DATE display mode.
o One touch correction of time error within ± 30 seconds.
o 4 years calendar.
o 2 switches sequential operating.
o LCD test.
o
o
FEATURES
Single chip CMOS construction.
Drives 3.5 digits duplexed LCD.
o Low power dissipation (100: Typ. O.8pA. Max. 1.5pA ;1.55V
operation).
o Colon display.
o 32.768Hz crystal controlled operation.
o Single 1.5V battery operation.
• On-chip capacitive voltage doubler.
o Debounce circuitly on switch inputs.
o Protection against static discharge.
o Built-in crystal oscillator 1l'-network input capaCitor.
o Trimmer capaCitor is user selectable. (bonding option)
o
o
ABSOLUTE MAXIMUM RATINGS (Ta = 25°C)
Characteristic
Supply Voltage (VDD - Vss)
Supply Voltage (VDD - VEE)
Operating Temperature
Storage Temperature
Symbol
Value
Unit
VDS
VDE
-0.3 - +2.0
-0.3- +4.0
-20 - + 75
-55-+125
V
V
·C
·C
Topr
Tstg
• Voltage greater than above in oamage the circuit.
c8SAMSUNG
64
CMOS DIGITAL INTEGRATED CIRCUIT
KS5114
ELECTRICAL CHARACTERISTICS
Characteristic
Operating Voltage
Symbol
(T.=25°C, Voo= OV, Vss= -1.5V; unless otherwise specified)
Test Condition
Min
Typ
Max
Unit
IVssl
1.2
1.5
1.8
V
IVEEI
2.4
3.0
3.6
V
Without Load
SlJPply Current
100
1.5
p.A
IhPut High Voltage
VIH
Voo-0.3
Voo
V
Input Low Voltage
VIL
Vss
Vss +0.3
V
Switch Activation Current
Isw
VI. = Voo
3
p.A
Oscillator Start Voltage
IVasel
Within 5 Sec
1.45
V
Oscillator Stop Voltage
IVospl
Oscillator Frequency
Fosc
DC-DC Conversion Frequency
FCON
LCD Frequency
Oscillator Capacitor
0.8
0.1
0.5
1.15
V
32,768
Hz
512
Hz
Fd
32
Hz
CI•
25
pF
COUI
25
pF
Time Stability
Tstb
Switch Debouncing Time
Tdeb
C1 =C2=0.1p.F
l:.Voo= 0.5V
(C""t=25pF)
1
ppm
62.5
mSEC
FUNCTIONAL DESCRIPTION
DISPLAY CONTROL
• Standard Display
Normal KS5114 displays HOUR In digit 1,2 and MINUTE in digit 3 and 4. In this state colon flashes at 1Hz rate.
Depression of 0 switch on normal display state will cause MONTH to be displayed in digit 1 and 2, DATE in
digit 3 and 4 with colon off. MONTH and DATE will continue to be displayed for 2 secnds after the D switch is
released. Then HOUR and MINUTE are displayed again.
Two momentary depressions of D switch within 2 seconds on normal display state will cause SECOND to be
displayed in digit 3, 4 and the digit 1 and 2 blanked with colon non-flashing continuously. Depressing S in this
state resets and holds the SECOND counter until switch S is released and MINUTE counter is either advanced
or remained unchanged depending upon whether the SECOND counter is greater or less than 30 seconds.
Depressing D in this state returns the display to HR : MIN display state.
• Alternating display
This mode is selected by activating the set switch (S) in normal display mode. In this mode HR : MIN is
automatically displayed alternately with MONTH DATE. Each is displayed for two seconds.
The S input must be activated five times to return to normal display mode and depressing D switch in this
alternating mode will cause the SECOND display mode.
c8SAMSUNG
65
CMOS DIGITAL INTEGRATED CIRCUIT
KS5114
3.5 DIGITS LCD FORMAT
'"
:;;
0
()
e
u
OJ
ill
~
f£«'"
~OJ
~
9
0
()
ill
~
COLON
~
'"
«
~
OJ
Ui
~
u.
.
(!l
~
«
<3
~
OJ
:E"
0
()
[JQD(] D~(l
o D ~ D ~
®
®
o C) (,l IJ (.l
D~\J D~t::J
Fig. 1
SETTING PROCEDURE
(fig. 2)
Time/calendar setting is accomplished by using S switch to enter and return from setting state. The D switch
is used to advance the function at 2Hz rate.
The function to be set is displayed the only one while setting state.
The detailed setting procedure is as follows.
a. Alternating display state
Depressing S switch in normal display state causes the alternating display mode. (Alternating HR : MIN and
MONTH DATE)
b. Month
Depressing S switch in normal display state calls MONTH set state and the display shows MONTH in digit 1
and 2. The MONTH counter can be advanced at 2Hz rate by depressing D switch.
c. Date
The next-deJjressin of S ~witctrwill selecrEJA-TE-set state ana-ttTe-display shows-DA1"Ein- digit3-ano4.The
DATE can be advanced as fig. 2.
d. Hour
The next depression of S switch will select HOUR set state and the display shows HOUR in digit 1 and 2 and
A (AM)/P (PM) in digit 4.
The colon flashes at 1Hz rate. The HOUR can be advanced a.s fig. 2.
e. Minute
The next depression of S switch will select MINUTE set state and the display shows MINUTE in digit 3 and 4
and the colon flashes at 1Hz rate. Depressing D switch advance the MINUTE at 2Hz flashing and the watch
suspends time-keeping.
c8SAMSUNG
66
CMOS DIGITAL INTEGRATED CIRCUIT
KS5114
f. Hold mode
Then watch enters the HOLD state with the next depression of S switch. In this state the display shows HOUR in digit 1
and 2, MINUTE in digit 3 and 4 and non-flashing colon. (Normal display state)
NOTE
If MINUTE were not changed in MINUTE set state, the watch will not enter the HOLD state but will automatically revert to
normal display state.
The carry signal from any preceeding counter during operation is not accepted except for second reset.
SETTING AND DISPLAY SEQUENCE
Second reset
(±30 sec correction)
o
Advance:
+1 for each depression and advance at 2Hz
rate with continuous depression.
- : Colon flashes at 1Hz rate.
--: Normally colon flashes at 1Hz rate,colon stops
flashing if minute is set.
II: Colon is not flashing and remains stationary.
If mInute IS nOfset
second re'et, to zem and hold
Fig. 2
=8SAMSUNG
67
KS5114
CMOS DIGITAL INTEGRATED CIRCUIT
APPLICATION CIRCUIT
1) External Trimmer Capacitor Type
COM2
SEGMENTS
COM1
vss 1-----.
S
o
1.5V
KS5114
r---l01
X·taiD
t--~ 00
1------0
Voo
CAP
512Hz
VEE
C2:
0.1~F
2) Internal Trimmer Capacitor Type
s
COM2
SEGMENTS
• Quartz Crystal Parameter
Fp
32,768Hz
12.5pF
CL
C1
4pF
Co = 2.5pF
Rs
35K{l
Q = 35,000
=
=
=
=
COM1
vss 1-----.
1.5V
x-tal
, - - - - J 01
D
'----I
00'
VOD
CAP
=8SAMSUNG
512Hz
t-----;.
VEE
68
KS5114
CMOS DIGITAL INTEGRATED CIRCUIT
PAD DIAGRAM
(2280, 1370)
DDDDDDDDDDDD
COM2
BC1/D2
F2/E2
A2/G2
COUD4
B2/C2
F3/E3
AD3/G3
B3/C3
F4/E4
A4/G4
001
B4/C4
COM1D
~OO'
0
KS5114
00 .
CHIP SIZE: 2280 X 1370"m
PAD SIZE; 110 X 110"m
Ovoo
vooD
y
0
512
CAP
T1
T2
T3
DDDD
vssD
(O,O) _ _ _ _~x
KS5114 PAD LOCATION
Unit: I"m
Coordinates
Pad Name
Coordinates
Pad Name
X
y
COM2
135
1235
F4/E4
1735
1235
BC11D2
315
1235
A4/G4
1935
1235
F2/E2
495
1235
B4/C4
2115
A2/G2
675
1235
COM1
B2/C2
855
1235
1035
1235
X
Coordinates
Pad Name
X
Y
T3
785
135
T2
505
135
1235
T1
325
2145
1045
CAP
135
135
D
2145
865
512
135
315
VEE
2145
685
Voo
135
510
690
Y
135
-~
COUD4
F3/E3
1215
1235
Voo
2145
505
00'
135
AD3/G3
1395
1235
S
2145
325
00
135
860
B3/C3
1575
1235
Vss
2145
145
01
135
1050
c8SAMSUNG
69
KS5184
CMOS DIGITAL INTEGRATED CIRCUIT
6 FUNCTION 6 DIGIT ALARM WATCH WITH
CHIME FOR DUPLEXED LCD
The KS5184 is a CMOS 6 function watch circuit with alarm function and
Chime, which is designed for with 6 Digit duplexed liquid crystal display with 7 day mark, date mark, alarm mark, AM/PM mark and colon_
FUNCTIONS
•
•
•
•
•
•
•
•
•
6 Function: Month, Date, Day-of-week, Hour, Minute, Second
Alarm, Snooze
Alarm output for melody IC (KS5310 Series)
User selectable 12 hour/24 hour format
4 year calendar
One touch correction of time error within ±30 seconds_
Chime on every hour
3 Switch sequential operation
LCD test
FEATURES
• Single chip CMOS construction
• Drives 6 digit duplexed LCD with 7 day mark, AM/PM mark, date
mark and alarm mark
• Colon display
• Direct drive of piezoelectric transducer at 3 volt peak to peak
• Fast advance for time and alarm set
• 32,768Hz crystal frequency
• On-chip oscillator and resistors
• On-chip voltage doubler
• Single 1.5V battery operation
• Low power dissipation
• Debounce circuitry on switch Inputs
• Protection against static discharge
ABSOLUTE MAXIMUM RATINGS (Ta = 25°C)
Characteristic
Supply Voltage (Voo-Vss)
_____ ~ __ ~ ____ r_~UPp5yoltage (VOsr VE)
Operating Temperature
Storage Temeprature
Symbol
Vos
value
V
-0.3- +2.0
___ ~ _____ 'y~_~ ______ ~~ _______ . =-0_3,., +4.Jl____ __
Top.
Tstg
Unit
~
____ '1..._____ _
-20-+75
-55-+125
• Voltage greater than above may damage the circuit.
c8SAMSUNG
70
C-MOS DIGITAL INTEGRATED CIRCUIT
KS5184
ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Operating Voltage
(Ta=25°C, VOD=OV, Vss= -1.5V; unless otherwise specified)
Test Condition
Min
Typ
Max
Unit
IVss11
1.2
1.5
1.8
V
IV.., I
2.4
3.0
3.6
V
~-.
Supply Current
100
2.0
p.A
Input High Voltage
V,H
VOD - 0.3
Voo
V
Input Low Voltage
V,L
Vss
Vss + 0.3
V
Switch Activation Current
Isw
V'n = Voo
3
p.A
Oscillator Start Voltage
IVosel
Within 5 Sec
1.45
V
Oscillator Stop Voltage
IVosp l
1.15
V
Alarm Drive Current
Without Load
1.0
0.1
lala
V,., =0.5V
(Both Direction)
0.5
lalb
V,.t = 0.5V
10
0.5
2.0
mA
20
p.A
32,768
Hz
2,048
Hz
Fd
32
Hz
Oscillator Input Capacitor
Gin
25
pF
Time Stability
Tstb
Switch Debouncing Time
Tdeb
Oscillator Frequency
Fose
DC~DC
FeoN
Conversion Frequency
LCD Frequency
C1 =C2=0.1p.F
f'"VDO = 0.5V
(Cout = 25pF)
1
ppm
62.5
mSEC
LCD FORMAT
COM2
PM/AM
ADEG1/SUM
C1/B1
A2/MON
COLON/TUE A3/WED
A4/THU
As/FRI
A6/SAT
DATE/AL
COM1
AM~~
PM~
8
~
~
Q
~
F2/E2
G2/D2
Fs/Es
Gs/Ds
Bs/Cs
F6/E6
G6/D6 B6/C6
Fig. 1
c8SAMSUNG
71
CMOS DIGITAL INTEGRATED CIRCUIT
KS5184
SEITING SEQUENCE AND SWITCH OPERATION
Alarm Minute Set
AL'
HR: MIN' AlP (12 hr)
HR: MIN' H (24 hr)
When S or 0 was used in alarm time setting
mode, depressing M will force to normal
*Flastiing at 2Hz rate.
AL means ,Alarm-mark
Advance
OM means date-mark
*12 HR mode or 24
HR mode is selected alternately on
everyone day
D cycle.
' -_ _ _..,..._':"---J
Display Alarm Time &
Disactivate Alarm
Output
HR: MIN AlP (12 hr)
HR: MIN H (24 hr)
Calendar Display
Day-ol-Week
MO DATE DM
SID
Display Alarm Time &
Alarm Enable/Disable
Alarm Demonstrate
M
Display Alarm Time &:
Chime Enable/Disable
Day-ol-Week
HR: MIN AlP (12 hr)
HR: MIN H (24 hr)
• Alarm-mark appears in any modes when the alarm is enable.
, All the day-ot-week mark appear when the chime is enabled
by switch operation.
Fig. 2
ALARM OUTPUT WAVEFORMS
r-
4,096Hz (50% duty)
.
I"'~
__
ALA1 and ALA2
rm rm ~~~~~l
matching
-'IIUII~
I
1_~ec --=:1...
r0.5 sec
ALA1 and ALA2
Chime Signal
s~c-=---==---=t--
Ir- - - - - - - - - - - - - - - - - - - - - - - - ,
--'
I.
-.JTlllTfL
-l
1_
I
m
60
4,096Hz (50% duty)
ALB
Alarm matching
L::::al
I
60 sec
L O.5 secJ
I
I
ALB
Chime
Signal
Fig. 3
c8SAMSUNG
72
KS5184
CMOS DIGITAL INTEGRATED CIRCUIT
APPLICATION CIRCUIT
Voo
C2:
0.1~F
Electrocoll
VEE
MTI---~ALB
OSC
Transducer
Roc= 1201l
CAP
u.
00
;:
ci
KS5184
01
0'
2KO
M
S
Vss ALA,
0
ALA2
• Quartz Crystal Parameter
Fp = 32,768Hz
CL = 12.5pF
Electrocoil
TranSducer
C1
4pF
Re and Ce are necessary only when employing envelope circuit with KS5310 Series. CO = 2.5pF
Rs
35KO
Otherwise, ENV pad must be connected to Vss.
Q = 35,000
Fig. 4
=
PAD DIAGRAM
...g
180
0
G2/0 2
0
'"8 8 8 8~e 'G
IRILIRI~~8
COLON
0
®
®
E2
~
C
0
E4
~
~
C4
~
Fig. 1
c8SAMSUNG
81
KS5194
CMOS DIGITAL INTEGRATED CIRCUIT
SETTING SEQUENCE AND SWITCH OPERATION
o
o
1
2
3
110 switch
Alarm
Chime
OFF
ON
ON
OFF
OFF
OFF
ON
ON
is pressed in the
alarm time
setting mode
II the MIN is not
adjusted
• Flashing at a 2 Hz rate
"Colon normally flashes at 1Hz rate and when MIN
is adjusted the colon stops and second counter is reset.
Adv·ance: + 1 for each depression and advances
at 2Hz rate with a continuous depression. When Alarm and chime functions are enabled, their marks appear
except in month/date and second display state.
01------,
Fig. 2
APPLICATION CIRCUIT
VSS3
• Quartz Crystal Parameter
Fp
32,768Hz
CL
12.5pF
C1
4pF
CO = 2.5pF
=
=
D
VDD
=
Rs
Q
=
35KO
= 35,000
Fig. 3
c8SAMSUNG
82
KS5194
CMOS DIGITAL INTEGRATED CIRCUIT
ALARM OUTPUT WAVEFORM
4096Hz (50% Duty)
ALI and AL2
Alarm Matching
Signal
~-'----"----- 0.125Sec
_
--lSec------t
r-------3OSec.--
4096Hz (50% Duty)
~L.
~
I
I
H
_ _ __
ALlandAL2
0.25Sec
Chime Signal
Fig. 4
PAD DIAGRAM
=DDDDDDDDDDDD·DDDD
Iii
I'l Ii!
:ii
::;;
~
!!;
0
::;;
()
1920
1720
1520
1320
a.
On
001
On
Doo
1120
DVDD
920
D'KO
720
DCAP
w
0
!!;
0
~
0
.
~
W
"
~
(!)
.
~
()
z
90
~
;rJ
~
(!)
~
'"
()
0
,.w
~
~
(!)
~
2520
::;;
[[
...J
ifi
::;;
0
()
ALI 0
2220
AL20
2020
DO
1470
vss'O
1030
~
()
KS5194 PAD DIAGRAM
Chip Size: 2660x3770
Ped Size : 12Ox120
Unit
: I'm
VDD
NC
520
320
Ds
Dr.
0
VEE
140
140
0
830
830
0
VSS30
430
VEED
230
140
3630
320
Fig. 5
c8SAMSUNG
83
KS5199A
CMOS DIGITAL INTEGRATED CIRCUIT
FUNCTIONS 3.5 DIGITS WATCH CIRCUIT
FOR DUPLEXED LCD.
The KS5199A is low threshold voltage, ion implanted metal gate CMOS
integrated circuit which provides all signals to drive a duplexed 3.5 digits
liquid crystal display with colon (Fig. 1).
32.768Hz frequency from crystal controlled oscillator is divided to provide SECOND, MINUTE, HOUR, DATE and MONTH information.
Phase controlled segment outputs and two Phase controlled back plane
outputs are provided for direct drive of the duplexeq LCD.
The KS5199A contains inverter/amplifier, output attenuating resistor,
capacitor and feed back resistor to drive the crystal.
The frequency of oscillator is divided to provide 512Hz output pulse used
as signal for the voltage doubler.
FUNCTIONS
o
o
o
o
o
o
5 Function: Month, Date, Hour, Minute and Second.
Selective alternation of TIME-DATE display mode.
One touch correction of time error within ± 30 seconds.
4 year calendar
2 switches sequential operating
LCD test
FEATURES
o
o
o
o
o
o
o
o
o
o
o
Single chip CMOS construction
Drives 3.5 digits duplexed LCD
Low power dissipation (IDD: Typ. O.BI'A, Max, 1.5I'A; 1.55V
operation).
Colon display
32,76BHz crystal controlled operation
Single 1.5V battery operation
On-chip capacitive voltage doubler
Debounce circuitly on switch inputs
Protection against static discharge
Built-in crystal oscillator 1f-network input capacitor
Trimmer capacitor is user selectable (bonding option)
ABSOLUTE MAXIMUM RATINGS (Ta = 25°C)
Characteristic
Symbol
Supply Voltage (Voo - Vss)
Supply Voltage (Voo - VEE)
Operating Temperature
Storage Temperature
Vos
VOE
Topr
TS '9
Value
-0.3 -0.3 -20 - 55 -
+2.0
+4.0
+ 75
+ 125
Unit
V
V
°C
°C
* Voltage greater than above may damage the circuit.
c8SAMSUNG
84
KS5199A
CMOS DIGITAL INTEGRATED CIRCUIT
ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Operating Voltage
--_.._..
Input Low Voltage
~
.
Operating Voltage
Supply Cu rrent
(Ta=25°C, Vss= -1.5V, VDD=OV; unless otherwise specified)
Test Conditions
IVssl _ _. _ _
_c_~.
.~
Switch Activation Current
Osc. Input Capacitor
1.2
1.5
1.7
V
3.0
3.4
V
0.8
1.5
/LA
-
Input High Voltage
Oscillator Stop Voltage
Unit
2.4
Vss+0.3
Vss
V
V,H
-0.3
0
V
-------
10
/LA
Within 5 sec
IVosci
- _ _._-_.- ---_. __
1.45
V
pl
IVos
_
_
...
1.15
V
Isw
.- _ . - - -
_..
.-
--
V,L
_._--_._--- -
Oscillator Start Voltage
Max
Without load
IDD
-_._-
Typ
--
IVEE I
_.
Min
0.1
V,N=VDD
- - -----_.
1.0
--
•..
..
-
-_.
CI
-------- _ .
Oscillator Frequency
Fosc
CI=25pF, CO=20pF
DC-DC Conversion Freq.
VCON
C1=C2=0.1~
LCD Frequency
FD
SW Debouncing Time
TD
.-"~
1----
25
pF
32,768
Hz
512
Hz
32
-- . _ - - _._--- _ .
62.5
Hz
ms
FUNCTIONAL DESCRIPTION
DISPLAY CONTROL
• Standard Display
Normal KS5199A displays HOUR in digit 1, 2 and MINUTE in digit 3 and 4, In this state colon flashes at 1Hz rate.
Depression of D switch on normal display state will cause MONTH to be displayed in digit 1 and 2, DATE in
digit 3 and 4 with colon off. MONTH and DATE are continuously displayed for 2 secnds after the D switch is released.
Then HOUR and MINUTE are displayed again.
Two momentary depressions of D switch within 2 seconds in normal display state causes SECOND to be dis·
played in digit 3, 4 and the digit and 2 blanked with colon non-flashing continuously. Depressing S in this state
resets and holds the SECOND counter until switch S is released and MINUTE counter either advanced or remains
unchanged depending upon whether the SECOND counter is greater or less than 30 seconds.
Depressing D in this state retums the display to HR : MIN display state.
• Alternating display
This mode is selected by activating the set switch (S) in normal display mode. In this mode HR : MIN is
automatically displayed alternately with MONTH DATE. Each is displayed for two seconds.
The S input must be activated five times to return to normal display mode and depressing D switch in this
alternating mode will cause the SECOND display mode.
c8SAMSUNG
85
KS5198
CMOS DIGITAL INTEGRATED CIRCUIT
3.5 DIGITS LCD FORMAT
* BC11D2 must be connected to B1/C1 pad for 12-hour application.
Fig. 1
4 DIGITS LCD FORMAT
v
0
N
e
'"
::;;
0
0
~
w
0
'"
Z
N
e
U
CD
N
w
~
~
N
~
\i:
CD
9
0
0
~
~
~COLON
~
0
'"
~
~
v
Q
w
~
u.
;f
~
CD
:!
0
0
~
- -rJ----- 8 8.--~
o~-8 8---8fJ
r::i b1 fJ
®
®
®
®
(J
(J 0
(J
D~lJ l)~lJ
D~lJ [)~\J
Fig. 2
c8SAMSUNG
86
KS5199A
CMOS DIGITAL INTEGRATED CIRCUIT
f. Hold mode
Then watch enters the HOLD state with the next depression of S switch. In this state the display shows HOUR in digit 1
and 2, MINUTE in digit 3 and 4 and non-flashing colon. (Normal display state)
NOTE
It MINUTE is not changed in MINUTE set state, the watch does not enter the HOLD state but automatically reverts
to normal display state.
The carry Signal from any preceeding counter during operation is not accepted except for second reset.
SETTING AND DISPLAY SEQUENCE
Second reset
(t30 sec correctIon)
a
Advance: + 1 for each depression and advance at 2Hz
rate with a continuous depression.
Colon flashes at 1Hz rate.
Normally colon flashes at 1Hz rate,colon stops
flashing if minute is set.
If minute is nOi"set
#: Colon does non-flashing and remains stationary.
second reset to zero and hold
Fig. 2
c8SAMSUNG
87
CMOS DIGITAL INTEGRATED CIRCUIT
KS5199A
APPLICATION CIRCUIT
1) External Trimmer Capacitor Type
vssl---~
D
1.5V
KS5199A
..L
01
DX·tal
vool---.....
00
5- 35P
2) Internal Trimmer Capacitor Type
• Quartz Crystal Parameter
Fp = 32,768Hz
CL
12.5pF
C1
4pF
CO = 2.5pF
Rs = 35Kn
Q
35,000
=
=
=
Vss
D
1.5V
KS5199A
01
OX·tal
Voo
00'
CAP
512Hz
VEE
C2: O.l"F
C,: O.l"F
c8SAMSUNG
88
KS5199A
CMOS DIGITAL INTEGRATED CIRCUIT
PAD DIAGRAM
~
~
1890
0
N
DO
0
V>
V>
0
>
1464
1890
>=
Os
CAPO
D
VODO
000
00'0
0
512Hz
1260
OVDD
992
OVEE
782
DO
KS5199A PAD DIAGRAM
Chip Size: 2330x2050
Pad Size : 120x120
Unit
: p'm
01
540
. . .
0.0
SAMSUNG
'"
'"
(!J
'"
.
0
::J
N
N
1251
1067
883
701
N
N
e
'" G'
[J
D0 D
D D D 0 D D D D
"
~
f-----
c8
1435
DCOM1
~
0>
0>
0>
""'
'"t-;; "' '"~
"'"
~
0>
""'"'
~
b2
C2
a3
0 G G
§'"
""''"
t-
0
125
M
'"
128
CMOS DIGITAL INTEGRATED CIRCUIT
KS6026
BASIC FUNCTION 8 DIGITS LCD
CALCULATOR WITH INTERNAL
VOLTAGE REGULATOR
48 FQP
The KS6026 is a single chip CMOS LSI with 8 digits
ariJhmetic operation, single memory, extraction-ofsquare-root, percentage calculation and auto power off
functions, designed for FEM LCD operation with 1.5V
power supply.
FUNCTIONS
II
• Four standard functions (+, -, x, .,.).
• Auto constant calculations (constant: multiplicand,
divisor, addend and subtrahend).
• Square and reciprocal calculations.
• Make-up and make-down calculations.
• Extraction of square root.
• Percentage calculations.
FEATURES
•
•
•
•
•
•
•
•
•
•
•
Single chip CMOS construction.
Chain multiplication and division.
Power calculations.
Rough estimate calculations.
Rollover capability.
Floating decimal.
LCD direct drive.
Overflow indicacion: "E".
Accumulating memory: M + , M - , RM, CM, RM/CM.
On chip supply voltage limiter by bonding option.
48 FOP and bare chip available.
ABSOLUTE MAXIMUM RATINGS
\
Characteristic
Terminal Voltage
Solar Supply Vol\age
Symbol
Rating
Unit
VGG
-0.3-2.1
V
V'N
-0.3 - VGG + 0.3
V
1.7 -3
V
2
1.2 -1.8
V
3
VSb
VGG(lim)
1.1-1.7
V
560±5%
KO
Topr
0- +50
·C
Tstg
-55-+150
·C
Battery Supply VolIage
VGG
Resistance for CG
R,
Operating Temperature
Storage Temperature
Note 1.
2.
3.
4.
..
""
Note
1
4
Maximum voltage on any pin is in with respect to GND.
VSb is solar supply voltage
VGG (lim) is limited voltage
Resistor value for CG varies according to the floating capacitance on a PWB
OCSAMSUNG
129
CMOS DIGITAL INTEGRATED CIRCUIT
KS6026
ELECTRICAL CHARACTERISTICS
(Ta= 25 C C, VGG = 1.5V, unless otherwise specified)
Characteristic
Symbol
Test Condition
Min
V,H,
Input Voltage 1
Input Current 1
Output Voltage 1
Output Voltage 2
Typ
Max
Unit
V
VGG·0.4
V,L,
0.4
V
1
/LA
3
/LA
I,H'
V ,N = VGG
I'L'
VOH ,
V,N=OV
VOl2
lout = 15/LA
VOA
without load
2.80
2.95
VOB
without load
1.30
1.50
1.70
V
Voe
without load
0
0.20
V
0.3
without load
1
V
VGG·0.15
0.15
V
Note
5
6
7
V
8
Display Frequency
Fd
VGG = 1.3V while display'
is on, R, = 560Kohm
10ff
display is off
0.8
/LA
9
Dissipation
Idls
VGG = 1.3V, while display is on
4.2
6
/LA
10
lop
VGG = 1.2V, while operation
5.6
9
/LA
11
55
67
Hz
8
Note 5.
6.
7.
8.
9.
10.
Applies to pin K2, K6.
Applies to pin K2, and K6.
Applies to P1, P2, A2 and A5.
Applies to H1, H3, a1, a8, b1, b8, c1 and c8.
Measured by the below test circuit after power supply automatically turns off.
Measured by the below test circuit while "0" is being displayed after auto-clear operation and while
key is not being depressed.
11. Measured by the below test circuit while operation is being made by AC key and while key is free from
depression.
OUTPUT WAVEFORM 1
- VOA
- VOB
- Voe
,-------\32
J~-1~C2
OUTPUT WAVEFORM 2
:
KS6026
35
36
l~
c8SAMSUNG
- VOA
37
- Voe
130
KS6026
CMOS DIGITAL INTEGRATED CIRCUIT
FUNCTIONAL DESCRIPTION
• Decimal point system
Complete floating decimal pOint system.
• Integral number: 8 digits leading zero suppression. Zero shift.
• Symbols: -: negative number display.
E : error display.
M : memory display.
• Negative number indication
Antilogarithm:
Minus
+
II
Error detections
System errors occur when:
1) The integral part of any calculation result exceeds 8 digits.
2) The integral part of any memory calculation result exceeds 8 digits.
In addition, the integral part of any addend or subtrahend to memory exceeds 8 digits.
3) The integral part of a make-up and make-down calculation result exceeds 8 digits.
4) The division by zero.
5) The extraction of square root of a negative number.
• Rough estimate calculation error
The integral part of the result of anyone of standard for functions, percentage, square, reciprocal, and power
calculations exceeds 8 digits and is equal to 16 digits or less.
Error indication
System error
"0" is indicated in the 1 digit position and "E" in the sign-digit position.
Rough estimate calculation error
The high-order 8 digits of a calculation result is indicated together with "E".
The decimal point is indicated in the position corresponding to a calculation result time 10- 8 , and no zero shift
is performed.
Error release
System error
A system error can be release by the AC or ON/C, CE key.
Rough estimate calculation error
A rough estimate calculation error can be released by the AC or ON/C, CE key.
A calculation result is not cleared by ON/C, CE key but is retained.
• Number entry
Numericals can be entered up to 8 digits. Numerical enteries equal to 9 digits or more are ignored .
.".
C:C"SAMSUNG
131
KS6026
CMOS DIGITAL INTEGRATED CIRCUIT
• Memory protection
In any error detection, the memory counters present before the error detection are protected.
• Memory indication
If the memory counters are a number other then zero, "M" is indicated in the sign-digit position.
• Doubler key depression
The order of the priority when two keys are being depressed simultaneously, is regarded as follows:
e
When the OFF and AC key are depressed simultaneously, the OFF key is given priority.
• Key bounce protection
Front edge
Down to 1 word and up to about 3 words.
Trailling edge
9 words.
1 word 3.3ms when display frequency fd
=100Hz.
DISPLAY FONTS
• Numericals font
1- I
-I
• Sign font
M
Memory
:CJ SAMSUNG
""
E
Error
Minus
132
KS6026
CMOS DIGITAL INTEGRATED CIRCUIT
• LCD connector
M
1- II _I _I
_I -I _11H2 H3 c8 b8
as
c7 b7 a7
c6 b6
a6
c5 b5
a5 c4 b4 a4 c3 b3 a3 c2
E
b2 82 c1
b1
a1
H1
AUTO POWER OFF
Power automatically turns off a after 9-11 minutes pass from the last key
pre~sure.
• AC key
All operation including memory contents are cleared by AC key.
• Make-up and make-down calculation
Make-up and make-down calculation are performed as followes.
ENTRY
A
+
B
%
DISPLAY
A
x
B
%
+OR-
A
A
B
A+AM/100
=
A
A
B
AM/100
AM/100
A + AM/100 OR A - AM/100
• AM: AMOUNT
c8SAMSUNG
133
KS6026
CMOS DIGITAL INTEGRATED CIRCUIT
PIN ASSIGNMENT
Pin No.
1
2
Signal
110
Signal
110
Description
V'b
I
Solar Battery
VOP
I
Option Pin
25
b7
0
Display Output
26
c7
0
Display Output
Power Supply
27
a8
0
Display Output
28
b8
0
Display Output
Description
Pin No.
3
VGG
4
H1
0
Display Output
5
a1
0
Display Output
29
c8
0
Display Output
6
b1
0
Display Output
30
H2
0
7
GND
31
H3
0
Display Output ._Display Output
8
c1
0
Display Output
32
GND
--
--
a2
9
0
Display Output
33
VC
---
0
Capacitor
Terminal for
Voltage Set·up
-------
10
b2
0
Display Output
34
VA
0
Capacitor
Terminal for
Voltage Set·up
11
c2
0
Display Output
35
VB
0
Capacitor
Terminal for
Voltage Set·up
12
a3
0
Display Output
36
CG Out
0
Resistor
Terminal for CG
13
b3
0
Display Output
37
CG In
I
Resistor
Terminal for CG
14
c3
0
Display Output
38
K3
I
Key Input
15
a4
0
Display Output
39
K2
I
Key Input
16
b4
0
Display Output
40
A2
0
Strobe Output
17
c4
0
Display Output
41
A3
0
Strobe Output
18
a5
0
Display Output
42
A4
0
Strobe Output
19
b5
0
Display Output
43
A5
0
Strobe Output
20
c5
0
Display Output
44
P2
0
Strobe Output
21
a6
0
Display Output
45
P1
0
Strobe Output
__ gE) _...
.._9-
.. Display Outpl!L
23
c6
0
Display Output
47
K6
I
Key Input
24
a7
0
Display Output
48
K4
I
Key Input
22
--
qSSAMSUNG
____ 4!L.
-
.----
. K!L_ ..
_J ._- _. J<.e.}'.I.!lJl!J.i_ .
----
134
KS6026
CMOS DIGITAL INTEGRATED CIRCUIT
APPLICATION CIRCUIT
(for use with a solar cell)
II
b7
25
12
a3
c7
26
11
c2
as
27
10
b2
bS
2S
9
a2
cS
29
S
c1
H2 30
KS6026
7 GND
H3 31
6
GN 32
D
5
a1
VC 33
4
H1
VA 34
3 VGG
V8 35
2
b1
TP
OUT
Rt
58: Solar battery
TP: Test pad
....
//
/
OCSAMSUNG/
/
/
/
135
KS6026
CMOS DIGITAL INTEGRATED CIRCUIT
APPLICATION
c8SAMSUNG
136
KS6026
CMOS DIGITAL INTEGRATED CIRCUIT
INTERNAL VOLTAGE LIMITER BONDING OPTION METHOD
OPTION 1
II
(Configuration using internal voltage limiter)
OPTION 2
(Configuration using external voltage limiter)
c8SAMSUNG:
137
CMOS DIGITAL INTEGRATED CIRCUIT
KS6026
PAD DIAGRAM
(2440 x 2300)
~--~----
------2440
<0
<0
<0
~
2175
'"'"
'"
~ ~ ~
VA
CG OUT VB
2015
1B55
;!
0>
0>
0>
~
VC
GND
III
'"
~
G
H3
0
'";":
~
'!2
~
~
H2
cB
0
;!
<0
0
~
G G
bB
aB
0
is
'"
~
c7
GCGln
~K3
-;-]
G
b7
a7~
1969.5
C6~iJ
1810
b6G
1649.5
a6~
1490
C58
1329.5
b5~
1170
a58
1009.5
C4G
850
b4G]
689.5
a4B
530
C3~
369.5
b3~
202
~K2
~A2
1375
0
0
'"'"
I
~A3
1215
~A4
1055
~A5
KS6026 PAD DIAGRAM
Chip Size: 2440 x 2300
Pad Size : 86 x 86
Unit
: I'm
I
B95
~P2
G~P1
575
415
~K5
1_~K6
~K4
Vsb
c:;]
VOP
VGG
0
[2]
H1
c1
a1
a2
b2
[2J ~ ~
0 G
c2
a3
8 B
125
-,--(0,0)
0
<0
'"
=8SAMSUNG
0
0;
'"
'"'"
'"
0>
"-
'"
<0
0>
<0
~
'""'"
<0
N
'";":
~
'!2
on
N
<0
'"
§'"
<0
f::!
0
'"
138
KS6027 AlBIC
CMOS DIGITAL INTEGRATED CIRCUIT
10/12 Digits Multi Type Calculator
KS6027 is distributed to multi type calculator by the user's bonding
option. KS6027 can drive the liquid crystal display (LCD) with single
power supply. Single power supply operation, wide operating voltage
range and low power consumption make it suitable for 1.5V solar battery
or 1.5V battery or 3V battery operated calculator.
1. KS6027A-10/12 digits selectable desk top/basic calculator (Bare Chip)
2. KS6027B-10 digits basic calculator (60 FOP)
3. KS6027C-10/12 digits basic selectable calculator (60 FOP)
12 digits desk top calculator (60 FOP)
II
FEATURES
• Complementary output buffer lor direct driving 01 liquid crystal
display
• Oscillator/clock generator intemal to chip
• Key board encoding Internal to chip
• Key board debouncing Internal to chip
• Wide supply voltage range (1.2V - 2.DV)
• Very lower power conllumptlon (7p.W TYP)
c8SAMSUNG
139
KS6027AlBIC
CMOS DIGITAL INTEGRATED CIRCUIT
ELECTRICAL CHARACTERISTICS
(1) Absolute maximum ratings
Characteristic
Value
Symbol
Terminal Voltage
Unit
Voo
-0.3 - +2.0
V
VIN
-0.3- Voo-0.3
V
DC
DC
Operating Temperature
Topr
0- +40
Storage Temperature
Ts.g
-55-+125
(2) Electrical characteristics
(Voo= +1.5V (±0.2V), Vee= +3V (±O.4V), Vss=OV, Ta=25 D C)
Characteristic
Pin Name
-
Operating Voltage
-
Supply Current
-
OSC Frequency
Frame Frequency
High Input Voltage
Symbol
-
V
1.5
2.0
6.5
Voo= 1.5V Operating
7.0
15
FdiS
Voo= 1.5V Stand-by
5.4
9.0
12.6
Fopr
Voo = 1.5V Operating
28.8
48
67.2
93.8
lopr
p.A
KHz
-
F,
Voo = 1.5V Stand-by
56.3
K3-K10
VIH (1)
-
Voo -0.4
-
Voo
K11-K12
VIH (2)
-
Vee - 0.4
-.
Vee
-
Vss
-
0.4
V
-
Voo-0.2
-
Voo
V
Vss
-
0.2
V
0.5
1
1.5
10
17
28
145
170
195
0.6
1.2 - -1-.9
250
400
550
-
Vee
V
Voo
V
0.2
V
High Output Voltage
K1-K8
VOH
Low Output Voltage
K1-K8
VOL
KI
Rpd1
K1-K10
Rpd2
KI
Vou.= 0.3V
Rpu1
You. = 1.2V
K1-KlO ___
Rpu2
K11-K14
Rpu3
High Output Voltage
LCD, COM
VOH
-
Vee - 0.2
"M" Output Voltage
LCD, COM
YOM
-
Voo-0.2
Low Output Voltage
LCD, COM
VOL
-
Vss
c8SAMSUNG
Unit
4.4
VIL (2)
-------
Max
-
V IL (1)
_Key Pull_l.!!:> Bes.
Typ
1.2
Voo = 1.5V Stand-by
KI
Key Pull Down Res.
Min
Idis
K3-K12
Low Input Voltage
Condition
-----
-----
Vou.=2.7V
----------
131
Hz
V
KG
K,Q
140
KS6027 AlBIC
CMOS DIGITAL INTEGRATED CIRCUIT
WAVE FORMS FOR DISPLAY
----·vcc: +3 (V)
. . . . . . - - - - - - - ' ---------·Voo: +1.5 (V)
COM1_--'
II
L--.....II
COM3lL-_......
,----- --- ---- 'W,,",
L - .- - - _
-Vss:O(V)
.-------, - - - - - - ----------------+3(V)
L - - - - - , - - - - - - - - - - - - - - - - +1.5 (V)
a1·COM1
------ -------------------- ------------------- ----------------OM
L-----, ------------ -1.5 (V)
! - - - ----3(V)
--+---Oll---+I-onl-+-I- o l i
a1. COM2
l
.1
on-j
1-----------------+
L - . - - . . . . , i
'
-
-
-
-
-
-
'
1 .5 (V)
I ----1-:':00
--------OFF
f - .
c8SAMSUNG
141
CMOS DIGITAL INTEGRATED CIRCUIT
KS6027AlBIC
PAD DESCRIPTION
PAD No.
Name
1/0
Description
PAD No.
1
2
3
4
5
COM1
COM2
COM3
AO (K)
80 (K)
0
0
0
0
0
Common Signal 1
Common Signal 2
Common Signal 3
LCD
LCD
36
37
38
39
40
810
C10
A11
811
C11
0
0
0
0
0
LCD
LCD
LCD
LCD
LCD
6
7
8
9
10
CO
A1 (K)
81 (K)
FOOlS
C1 (K)
0
0
0
I
0
LCD
LCD
LCD
A12
812
VSS
VA
VB
0
0
LCD
LCD
Solar Cell (-)
LCD
41
42
43
44
45
11
12
13
14
15
A2 (K)
82 (K)
C2
A3
83
0
0
0
0
0
LCD
LCD
LCD
LCD
LCD
46
47
48
49
50
Vee
VDD
VDD
EXTNL
FOOlS
16
17
18
19
20
C3
84
C4
A5
0
0
0
0
0
LCD
LCD
LCD
LCD
LCD
51
52
53
54
55
KI
K1
K2
K3
K4
1/0
0
0
1/0
1/0
ON Key
Key Input
Key Input
Key Input
Key Input
1
2
3
4
21
22
23
24
25
85
C5
A6
86
C6
0
0
0
0
0
LCD
LCD
LCD
LCD
LCD
56
57
58
59
60
K5
K6
K7
K8
K9
1/0
1/0
1/0
1/0
I
Key
Key
Key
Key
Key
5
6
7
8
9
26
27
28
29
30
A7
87
C7
A8
88
0
0
0
0
0
LCD
LCD
LCD
LCD
LCD
61
62
63
64
65
K10
K11
K12
K13
K14
I
I
I
31
32
33
34
35
C8
A9
89
C9
A10
0
0
0
0
0
LCD
LCD
LCD
LCD
LCD
A4
.
I
I
Description
....
..
+ 1.5V Power
Solar Cell (+)
External Clock
Fosc Disable
Input
Input
Input
Input
Input
Key Input 10
Key Input 11
Key Input 12
No Connection
No Connection
• Frequency Doubler Disable
•• Capacitor Terminal for Voltage Doubling
-----
c8SAMSUNG
1/0
Name
---
--
----
-
142
KS6027A
CMOS DIGITAL INTEGRATED CIRCUIT
1. KS6027A
Desk Top 10 or 12 digits selectable LCD calculator. KS6027A is either
10 digits capacity 2-memory or 12 digits capacity 2-memory electronic
calculator on one chip CMOS/LSI.
KS6027A can drive the liquid crystal display (LCD) with single power
supply. Single power supply operation, wide operating voltage range
and low power consumption make it suitable for 1.5V solar battery operated calculator.
FUNCTION
II
• Display
12 digits or 10-digits (selectable with PCB option) of data, 2
digits of sign, error symbol, memory load symbol, constant
calculation mode symbol, operation symbol.
• Standard 4 functions
• Memory and grand total (GT) memory calculation
• Automatic percentage operation with add on, discount
• Square root
• Constant calculation
• Chain calculation
• Change sign
• Floating point or momentary mode (selectable with a switch)
• Fixed point ("0", "2", "3", "4")
• Adding pOint mode
• Registration overflow, indicating that too many digits are
entered (the most significant digits are protected).
• Result overflow, indicating during calculation (most function
key are locked as it happended).
• Rounding switches (rounding up, down and off)
• Leading zero suppression
• Trailing zero suppression
• Punctuation on display; Commas for thousand.
• Memory and GT memory contents indicator, turn on with nonzero in the memory and GT memory.
c8SAMSUNG
143
CMOS DIGITAL INTEGRATED CIRCUIT
KS6027A
BASIC SPECIFICATION
1. Fixed point calculations
1) Key
C
3
Display
o.
M+
MR
MC
MR
3.
3.
7.
0.429
4.
4.
4.5
4.51
4.51
2.
6.510
1.
1.
1.9
1.900
8.410
8.410
O.
3) Key
Display
+
7
4
5
1
+
2
M+
1
9
C
o.
3
3.
3.
3.1
3.1
6.
6.
6.4
19.
2.
2.
2.5
2.5
8.
---10.50
4.
2.
2.
7.
7.
7.3
14.6
x
6
4
2
5
+
8
4
..r
x
7
3
c8SAMSUNG
Fixed point place
2) Key
DP=3 (5/4)
C
9
..r
x
7
2
3
4
5
+
1
6
7
+
4
Fixed point place
DP=O (cuT)
Key
4
3
2
+
5
1
2
x
3
7
8
9
6
M+
4
DP=F
O.
9.
3.
3.
7.
7.
7.2
7.23
7.234
21.71
5.
5.
1.
1.
1.6
6.60
7.
7.
4.
2.
Fixed point place
DP=2 (UP)
DP=O
2. Adding point mode calculations
C
DP=2
Display
Display
O.
4
43
432
4.32
5.
4.37
1.
12.
12.
3.
3.
3.2-3.78
3.789
45.46
6.
0.06
4.
4.
Key
1
2
3
M+
MR
C
9
5
2
3
Display
4.1
4.12
4.123
4.12
4.18
O.
9.
95.
952.
9.52
3.
3.
-s
--3.~
7
3.67
5.85
4.
0.04
3.
3.
3.04
4
+
3
144
KS6027A
CMOS DIGITAL INTEGRATED CIRCUIT
3. Constant calculation
2) Division
1) Multiplication
Key
Display
k
x
x
a
k
k
k
a
k·a
b
k·b
b
Constant
kx
kx
kx
b
Display
Constant
k
k
k
a
a/k
b
b/k
+k
+k
+k
b
II
4) Subtraction
3) Addition
k
+
+
a
Key
k
+
+
a
k
k
k
a
a+k
b
b+k
k
a
+k
+k
+k
b
k
k
k
a
a-k
b
b-k
5) Percentage
6) Percentage
k
x
x
a
%
b
%
k
k
k
k
a
k·a/100
b
k·b/100
kx
kx
kx
a
%
b
%
k
k
k
a
100·a/k
100·b/k
-k
-k
-k
+k
+k
+k
4. Add·on, discount calculations
2) Discount
1) Add·on
Key
Display
Key
Display
a
x
b
%
+
a
a
b
a
x
b
%
a
a
b
a·b/100
a(1 + b/100)
c8SAMSUNG
a·b/100
a(1-b/100)
145
- - - - - - - - - - -
CMOS DIGITAL INTEGRATED CIRCUIT
KS6027A
TOUCH KEY CONSTITUTION AND OPERATION
O,0-0 :
Number
B
GD0c:J
: Change Sign
: Function
[]0G
EJB~
: Memory
GEl
G
00 :
: Shift
Clear
-
-
_ _ _ _ _ _ _ _ _ _n
_____
4iSAMSUNG
------F-ON-l
_-=_SyBtelIueseL _____ -
_n
_ _n
_____________
n
__ _
146
KS6027A
CMOS DIGITAL INTEGRATED CIRCUIT
KEY CONSTITUTION AND OPERATION
1. Key Board
Klo------/
II
K1 0 - - - - - - - - - - ,
K20-----~--,
K30------+-~--,
K4 o - - - - - - - - i
K5 o - - - - - - - - i
K6 o-----------{
K7 o - - - - - - + - - - - l
Kl
0-------;
K90------;
K100------;
2. Switch
B2
A2
C1
B1
A1
BO
AO
K12 o - - - - - - - - - i
K110-------+--+_-I
K11: Selectable with fixed point.
'" K12: Rounding switches for mode select.
c8SAMSUNG
147
KS6027A
CMOS DIGITAL INTEGRATED CIRCUIT
LCD CONNECTION
1. 10 Digits Desk Top
2. 12 Digits Desk Top
COM3
1) Segment
2) Common
COM1
COM2
c8SAMSUNG
2>
COM3
148
CMOS DIGITAL INTEGRATED CIRCUIT
KS6027A
APPLICATION CIRCUIT
1. Select of 10 Digits
r---
'"00
..:
II
e
'"
ij\
a.
:::>
..,
...
II
I-
:::>
0
-
IL
I I
I
~
~
;!
~
~
::
~
a>
'"
....
Iel
II
29 A8
K354
30 B8
K253
31 C8
K1 52
32 A9
-'
33 B9
a>
0
(:Ij
0
:(
l$l
0
0;
~
I
0
[)
:(
..,.... ..,.0
0;
1/l
.
[)
0
'"
:(
~
'"0;
~
'" <
..,>'" ...>
In
0
0
c
c
z
on
>
~
~)
0
~:
>
....
.~
i5 KI 51
c
c
>-
>
X
W
IL
e
on
. . . . .. .I
>
-
en
0
I
R ~~
z
~O
~
----c8SAMSUNG
149
on
CMOS DIGITAL INTEGRATED CIRCUIT
KS6027A
APPLICATION CIRCUIT
2. Self;lct of 12 Digits
ADD2
o
H-________________~~~~I
H---------------__~_r~~~~5/4
3
~----------------~--4_4_~_r~_r_+_+--~up
4
I
:e
I
~
I
;!
.., .., ..,
U
III
17 A4
~
« u'"
~
::
'" '"«
III
CXl,....«)IO'¢MN
~
'"
a m :{ 8
en
U
~
0
LI.
~
;
~
CUT
-
F
-
....
iNC
8 8 8
65-
r-
18 B4
r-
19 C4
K12 63 __
20 A5
K11 62 r-----
NC 64
21 B5
ci
~
AC
C
I I I I I I
K9 60
•
00
0
1
K8 59
+
-
x
+
K10 61
22 C5
..J
2
3
4
5
23 A6
24 B6
KS6027A
25 C6
(SELECT OF 12 DIGITS)
26 A7
..r
K7 58
K6 57
M+ M-
%
+1-
MR MC
27 B7
K556
6
K455
=
28 C7
7
89
GT
29A8
K3
30 B8
31 C8
K1 52 f--
32 A9
33 B9", ~
--
541--+------t-----'
K2531---
______ 0
« ai
;:1; ~
I
0
..,
<0
I I
~ !Q
0
u
'"
'" '" '" ...
U -!C---m....
Um<
."'''Xl
001«
000
001«
COM2
c8SAMSUNG
154
CMOS DIGITAL INTEGRATED CIRCUIT
KS6027B
APPLICATION CIRCUIT
L.C.D.
A9
31
15
C3
69
32
14
63
NC
33
13
A3
C9
34
12
C2
NC
35
11
62
A12
36
10
A2
612
37
9
C1
KS6027B
(10 DIGITS BASIC CALCULATOR)
Vss
38
8
NC
Va
39
7
OOIS
Vb
40
6
61
Vee 41
5
A1
Ca
Cb
Vdd' 42
Vdd
43
EXT
44
NL
FOO 45
IS
II
CO
3
60
2
AO
1 COM3
• POWER ON/OFF
c8SAMSUNG
155
KS6027C
CMOS DIGITAL INTEGRATED CIRCUIT
3. KS6027C
60 FOP
The KS6027C is 10/12 digits basic or 12 digits desk top (3V operation) calculator which have to use the only 3.0V power supply. However,
when you want to use bare chip, you can use 1.5V solar cell as well
as 1.5V battery.
Refer to application circuit.
FUNCTION
• Display
12 digits or 10-digits (selectable with PCB option) of data, 2 digits
of sign, error symbol, memory load symbol, constant calculation
mode symbol, operation symbol.
• Standard 4 functions
• Memory and grand total (GT) memory calculation
• Automatic percentage operation with add on, discount
• Square root
• Constant calculation
• Chain calculation
• Change sign
• Floating point or momentary mode (selectable with a switch):
Desk Top
• Fixed pOint ("0", "2", "3", "4"): Desk Top
• Adding point mode: Desk Top
• Registraction overflow, indicating that too many digits are entered
(the most significant digits are protected).
• Result overflow, indicating during calculation (most function key
are locked as it happended).
• Rounding switches (rounding up, down and off)
• Leading zero suppression
• Trailing zero suppression
• Punctuation on display; Commas for thousand.
• Memory and GT memory contents indicator, turn on with non-zero
in the memory and GT memory.
c8SAMSUNG
60 FOP
156
KS6027C
CMOS DIGITAL INTEGRATED CIRCUIT
BASIC SPECIFICATION
1. Constant calculation
1) Multiplication
Key
Display
k
x
x
a
k
k
k
a
k'a
b
k'b
b
2) Division
Constant
b
Display
Constant
k
k
k
k
a
a/k
b
b/k
..,.k
..,.k
..,.k
a
kx
kx
kx
3) Addition
k
+
+
a
Key
b
II
4) Subtraction
k
k
k
a
a+k
b
b+k
k
a
+k
+k
+k
b
k
k
k
a
a-k
b
b-k
5) Percentage
6) Percentage
k
x
x
a
%
b
%
k
k
k
k
a
k·a/100
b
k'b/100
~
kx
kx
kx
a
%
b
%
k
k
k
a
100'a/k
100'b/k
-k
-k
-k
..,.k
..,.k
..,.k
2. Add-on, discount calculations
1) Add·on
2) Discount
Key
Display
Key
Display
a
a
a
b
a'b/100
a(1 + bI100)
a
x
b
%
a
a
b
a·b/100
a(1 - b/100)
x
b
%
+
157
KS6027C
CMOS DIGITAL INTEGRATED CIRCUIT
TOUCH KEY CONSTITUTION AND OPERATION
G, 0 -0 :
Number
D
B :
Change Sign
c:J D [:] [J :
Function
800
EJB~
:Memo~
GEl
G :
80 :
Shift
Clear
__ I
c8
SAMSUNG
()N
~_
: System reset
158
KS6027C
CMOS DIGITAL INTEGRATED CIRCUIT
KEY CONSTITUTION AND OPERATION
1. Key Board
K10---------,
K2
KIO----~
o----____+_~
K3O-----+-+_--,
K40-------{
K5
o-------{
K6
o-------{
K7
o----____+_-I
II
K8 O - - - - - - - - i
K9 0-----------1
K10 0------------1
LCD CONNECTION
1. Segment
2. Common
COM2
c8SAMSUNG
COM3
159
CMOS DIGITAL INTEGRATED CIRCUIT
KS6027C
APPLICATION CIRCUIT
I
L.C.D.
,---
-
.-----
,---
,---
I csl
30
,--A9
-
r--'-- B9
r--C9
r---" - - - - A10
r--B10
f-C10
f-A11
f-Vss
f-B11
f-C11
l~
m
JJ
r---
0
z
~
Bsl Asl c71 B71 A71 c61 B61 A61 c51 B51 A51 c41 B41 A41
29
28
27
26
25
24
23
22 21
20
19
18
17
16
,--C3
f-14
B3
15
31
32
r---
34
35
11
13
1--10
3V
~
A2
8
C1
f-NC
39
7
~ODIS
40
6
9
12 DIGITS DESK TOP CALCULATOR)
38
-
I---
(10112 DIGITS BASIC SELECTABLE,
37
B2
I---
KS6027C
36
I
I---
A12 41
f-Vee 42
~ 111+1
-
A3 f-12
C2
33
B1
I---
A1
f-4
CO
f-3
BO
5
I--Vdd 43
f--
I
r--
2
§44
FOOlS 45
AO
r--
1 COM3
'----
46
47
I K1 I K21
48
49
50
51
52
53
54
55
56
57
58
K31 K41 K51 K6t K71 K81 K91 K101 K111 K121 NC
=
6
7
+ .
+
M-
I>
-
00
x
0
.;-
1
%
3
~~
GT
8
9
MR
-.r
MC
f
AC
C
59
60
I~ I~ I
,.--~~
l-
I l
~~
~O)(
II I I I
4
3
A602
2
4
5
=8SAMSUNG
/
160
KS6028
CMOS DIGITAL 'INTEGRATED CIRCUIT
BASIC FUNCTION LOW POWER
TYPE
8 DIGITS LCD CALCULATOR WITH
INTERNAL VOLTAGE REGULATOR
48 FOP
The KS6028 is a single chip CMOS LSI with 8 digits
arithmetic operation, single memory, extraction-ofsquare-root, percentage calculation and auto power off
functions, designed for FEM LCD operation with 1,5V
power supply,
FUNCTIONS
II
• Four standard functions ( +, -, x, +),
• Auto constant calculations (constant: multiplicand,
divisor, addend and subtrabend),
• Square and reciprocal calculations,
• Make-up and make-down calculations,
• Extraction of square root.
• Percentage calculations,
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
Single chip CMOS construction.
Chain multiplication and division.
Power calculations.
Rough estimate calculations.
Rollover capability.
Floating decimal.
LCD direct drive (3, 113).
Overflow Indication: "E"
Accumulating memory: M -, M -, RM, CM, RM/CM
On-chip oscililltor components
On-chlp supply voltage limiter by application option.
Very low power consumption.
ABSOLUTE MAXIMUM RATINGS
Characteristic
Terminal Voltage
Symbol
Rating
Unit
VGG
-0.3-2.1
V
Y,N
-0.3-VGG+0.3
V
V.b
Note
1
1.1-3
V
2
VGG (lim)
1.1-1.8
V
3
Battery Supply Voltage
VB
1.1-1.8
V
Operating Temperature
Topr
0- +50
·C
Storage Temperature
T.tg
-55-+150
·C
Solar Supply Voltage
. ..
Note'1. Maximum voltage on any pin with respect to GND.
2. VSb is solar supply voltage.
3. VGG (lim) is limited voltage.
c8SAMSUNG'
161
CMOS DIGITAL INTEGRATED CIRCUIT
KS6028
ELECTRICAL CHARACTERISTICS
(Ta=25°C, VGG= 1.5V, unless otherwise specified)
Characteristic
Input Voltage 1
Input Current 1
Output Voltage 1
Output Voltage 2
Display Frequency
Dissipation
Symbol
Test Condition
V,H1
Min
Typ
Max
V,L1
V,N=VGG
I'L1
V,N=OV
1
0.3
0.4
V
1
pA
3
p.A
without load
VOI.2
loul = 15p.A
VGG-O.15
VOA
without load
2.BO
2.95
Voe
without load
1.30
Voc
without load
35
50
VGG = 1.3V while display is on.
10ff
display is off
Idis
VGG = 1.3V, while display is on
lop
VGG=1.1V, while operation
4
5
V
VOH1
Fd
Note
V
VGG-0.4
I'H1
Unit
0.15
V
1.50
1.70
V
0
0.20
6
V
7
V
Hz
7
O.B
p.A
B
1.3
3
p.A
9
2.5
5.5
p.A
10
Note 4.
5.
6.
7.
B.
9.
Applies to pin K2, K6.
Applies to pin K2, and K6.
Applies to P1, P2, A2 and A5.
Applies to H1, H3, a1, aB, b1, bB, c1 and cB.
Measured by the test circuit below after power supply automatically turns off.
Measured by the test circuit below while "0" is being displayed after auto-clear operation and while
key is not being depressed.
10. Measured by the below test circuit wl1i1e operated AC key and while key is free from depression.
OUTPUT WAVEFORM 1
-Voe
r-----I32
33
34
KS6028
35
OUTPUT WAVEFORM 2
36
3
nA
37
-VOA
(TEST CIRCUln
-Voe
VGG
162
KS6028
CMOS DIGITAL INTEGRATED CIRCUIT
FUNCTIONAL DESCRIPTION
• Decimal point system
Complete floating decimal point system.
• Integral number: 8 digits leading zero suppression. Zero shift.
• Symbols: -: negative number display.
E : e~ror display.
M : memory display.
• Negative number indication
Antilogarithm: +
II
Minus
Error detections
System errors occur when:
1) The integral part of any calculation result exceeds 8 digits.
2) The Integral part of any memory calculation result exceeds 8 digits.
In addition, the integral part of any addend or subtrahend to memory exceeds 8 digits.
3) The integral part of a make-up and make-down calculation result exceeds 8 digits.
4) The division by zero.
5) The extraction of square root of a negative number.
• Rough estimate calculation error
The integral part of the result of anyone of standard for functions, percentage, square, reciprocal, and power
calculations exceeds 8 digits and is equal to 16 digits or less.
Error indication
System error
"0" is indicated in the 1 digit position and "E" in the sign-digit position.
Rough estimate calculation error
The high-order 8 digits of a calculation result is indicated together with "E".
The decimal point is indicated in the position corresponding to a calculation result time 10- 8 , and no zero shift
is performed.
Error release
System error
A system error can be release by the AC or ON/CCE key.
Rough estimate calculation error
A rough estimate calculation error can be released by the AC or ON/CCE, CE key.
A calculation result is not cleared by ON/CCE or CE key but is retained.
• Number entry
Numericals can be entered up to 8 digits. Numerical enteries equal to 9 digits or more are ignored.
c8SAMSUNG
163
KS6028
CMOS DIGITAL INTEGRATED CIRCUIT
• Memory protection
In any error detection, the memory counters present before the error detection are protected.
• Memory indication
If the memory counter is a number other then zero, "M" is indicated in the sign·digit position.
• Doubler key depression
The order of the priority when two keys are being depressed simultaneously, is as follows:
When the OFF and AC key are depressed simultaneously, the OFF key is given priority.
• Key bounce protection
Front edge
Down to 1 word and up to about 3 words.
Trailling edge
9 words.
1 word is 3.3ms when display frequency is fd =100Hz.
DISPLAY FONTS
• Numericals font
• Sign font
M
Memory
=8SAMSUNG
E
Error
Minus
164
KS6028
CMOS DIGITAL INTEGRATED CIRCUIT
• LCD connector
=1
M
11_ 1 _I
_11H2 H3 c8 b8 a8 c7
b7
a7
c6 b6
c3
_
I
a6
c5 b5
b3a3 c2
E
1
a5 c4 b4 a4 c3 b3
b2a2
c1
a3 c2
b2
a2 c1
b1
a1
H1
II
b1a1
AUTO POWER OFF/DISABLE
After 9-11 minute from the last key pressure power is off automatically. By connecting APODIS pin to GND or VGG ,
whether an auto power off function is available is determined.
APODIS
Auto-power-off state
GND
disable
VGG
enable
AC key
All operation including memory contents are cleared by AC key.
Make-tip and make·down calculation
Make-up and make-down calculation are performed as follows.
Entry
A
+
B
%
Display
A
x
B
%
+OR-
=
A
A
B
A + AM/100
A
A
B
AM/100
AM/100
A + AM/100 OR A - AM/100
• AM: Amount
c8SAMSUNG
165
KS6028
CMOS DIGITAL INTEGRATED CIRCUIT
PIN ASSIGNMENT
Pad No.
Pin No.
Signal
1/0
Descri ... ::v;:
Pad No.
Pin No.
Signal
I/O
Description
1
25
VSb
I
Solar Battery
25
1
b7
0
Display Output
2
26
VOP
I
Option Pin
26
2
c7
0
Display Output
3
27
VGG
Power Supply
27
3
a8
0
Display Output
4
28
APODIS
I
APO Disable
28
4
b8
0
Display Output
5
29
H1
0
Display Output
29
5
c8
0
Display Output
6
30
a1
0
Display Output
30
6
H2
0
Display Output
7
31
b1
0
Display Output
31
7
H3
0
Display Output
8
32
c1
0
Display Output
32
8
GND
9
33
a2
0
Display Output
33
9
VC
0
Capacitor
Terminal for
Voltage Set·up
10
34
b2
0
Display Output
34
10
VA
0
Capacitor
Terminal for
Voltage Set·up
11
35
c2
0
Display Output
35
11
WB
0
Capacitor
Terminal for
Voltage Set·up
12
36
a3
0
Display Output
36
12
EXTNL
I
External Clock
---
13
37
b3
0
Display Output
37
13
FDIS
I
FOSC and Freq.
Doubler Disable
14
38
c3
0
Display Output
38
14
K3
I
Key Input
15
39
a4
0
Display Output
39
15
K2
I
Key Input
16
40
b4
0
Display Output
40
16
A2
0
Strobe Output
17
41
c4
0
Display Output
41
17
A3
0
Strobe Output
18
42
a5
0
Display Output
42
18
A4
0
Strobe Output
19
43
b5
0
Display Output
43
19
A5
0
Strobe Output
20
44
c5
0
Display Output
44
20
P2
0
Strobe Output
21
45
a6
0
Display Output
45
21
P1
0
Strobe Output
22
46
b6
0
Display Output
46
22
K5
I
Key Input
23
47
c6
0
Display Qutput.
47
2~
K6_
1
. Key IIJp.ut
24
48
a7
0
Display Output
48
24
K4
I
Key Input
c8SAMSUNG
--- --
166
KS6028
CMOS DIGITAL INTEGRATED CIRCUIT
APPLICATION CIRCUIT
(for use with a solar cell)
II
b7
25
12
a3
c7 26
11
c2
a6
27
10
b2
b8
28
9
a2
c8
29
B c1
H2 30
H3
31
KS6028
7
b1
6
a1
5
H1
4 APO
3 VGG
c8SAMSUNG
2
Vop
1
Vsb
167
KS6028
CMOS DIGITAL INTEGRATED CIRCUIT
APPLICATION CIRCUIT
(for use with a battery)
b7 25
12
a3
c7
26
11
c2
as
27
10
b2
b8 28
9 a2
8
c8 29
c8SAMSUNG
c11-----'
7
b1 1 - - - - - - '
H3 31
GN 32
0
VC 33
6
a1 1 - - - - - - '
5
H1 1 - - - - - - - '
VA 34
3 VGGI----.------,
VB 35
2 Vop
EXTNL 36
1 Vsb
H2 30
KS6028
4 APO
168
KS6028
CMOS DIGITAL INTEGRATED CIRCUIT
INTERNAL VOLTAGE LIMITER BONDING OPTION METHOD
OPTION 1
II
(Configuration using internal voltage limiter)
OPTION 2
(Configuration using external voltage limiter)
c8SAMSUNG
169
KS6028
c8SAMSUNG
CMOS DIGITAL INTEGRATED CIRCUIT
170
CMOS DIGITAL INTEGRATED CIRCUIT
KS6029
BASIC FUNCTION 10 DIGITS LCD
CALCULATOR WITH INTERNAL
VOLTAGE REGULATOR
48 FOP
The KS6029 is a single chip CMOS LSI with 10 digits
arithmetic operation, single memory, extraction-ofsquare-root, percentage calculation and auto power off
functions, designed for FEM LCD operation with 1.5V
power supply.
FUNCTIONS
II
• Four standard functions (+, -, x, -;.).
• Auto constant calculations (constant: multiplicand,
divisor, addend and subtrabend).
• Square and reciprocal calculations.
• Make-up and make-down calculations.
• Extraction of square root.
• Percentage calculations.
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
Single chip CMOS construction.
Chain multiplication and division.
Power calculations.
Rough estimate calculations.
Rollover capability.
Floating decimal point.
LCD direct drive (4, 114).
Overflow indication: "E"
Accumulating memory: M1, M, RM, CM, RM/CM
On·chip supply voltage limiter by application option.
Very low power consumption_
On-chip oscillator components
ABSOLUTE MAXIMUM RATINGS
Characteristic
Terminal Voltage
Solar StJpply Voltage
Symbol
Rating
Unit
VGG
-0.3- 2.1
V
Y'N
- 0.3 - VGG + 0.3
V
VSb
1.1-3
V
2
3
VGG (lim)
1.1-1.8
V
Battery Supply Voltage
VB
1.1 -1.8
V
Operating Temperature
Topr
0- +50
'C
Storage Temperature
Tstg
-55- +150
'C
Note
1
Note 1. Maximum voltage on any pin with respect to GND.
2. VSb is solar supply voltage.
3. VGG (lim) is limited voltage.
c8
SAMSUNG
171
CMOS DIGITAL INTEGRATED CIRCUIT
KS6029
ELECTRICAL CHARACTERISTICS
(Ta = 25°C, VGG = 1.5V, unless otherwise specified)
Characteristic
Symbol
Test Condition
Min
VIH1
Input Voltage 1
Typ
VGG·O.4
Output Voltage 1
Output Voltage 2
Display Frequency
Dissipation
IIH1
VIN= VGG
IIL1
VIN=OV
VOH1
without load
VOL2
lout = 15p.A
0.3
1
0.4
V
1
p.A
p.A
3
V
VGG·0.15
0.15
VOA
without load
2.BO
2.95
VOB
without load
1.30
1.50
1.70
Voe
without load
0
0.20
35
50
Fd
VGG = 1.3V while display is on.
lott
display is off
Idis
VGG = 1.3V, while display is on
lop
VGG = 1.1V, while operation
Unit
V
VIL1
In put Cu rrent 1
Max
V
Note
4
5
6
V
O.B
1.5
3
3
5.5
V
7
V
Hz
7
p.A
p.A
p.A
B
9
10
Note 4.
5.
6.
7.
B.
Applies to pin K2, K6.
Applies to pin K2, and K6.
Applies to P1, P2, A2 and A5.
Applies to H1, H3, a1, aB, b1, bB, c1 and cB.
Measured by the test circuit below after power supply automatically turns off.
9. Measured by the test circuit below while "0" is being displayed after auto·clear operation and while
key is not being depressed.
10. Measured by the below test circuit while operated AC key and while key is free of depression.
OUTPUT WAVE FORM 1
-fl
~~VOA
~,=H'-=I--1-rr==~~ ---------~::
l
OUTPUT WAVE FORM 2
~
;h
32
C1
33
34
-cz
_KS6029
35
36
37
r-----.-------VOA
'-------'
c8SAMSUNG
Voe
172
KS6029
CMOS DIGITAL INTEGRATED CIRCUIT
FUNCTIONAL DESCRIPTION
• Decimal point system
Complete floating decimal point system.
• Integral number: 10 digits leading zero suppression. Zero shift.
• Symbols: -: negative number display.
E : error display.
M : memory display.
•
Neg~tive
number indication
Antilogarithm: +
Minus
II
Error detections
System errors occur when:
1) The integral part of any calculation result exceeds 10 digits.
2) The integral part of any memory calculation result exceeds 10 digits.
In addition, the integral part of any addend or subtrahend to memory exceeds 10 digits.
3) The integral part of a make-up and make-down calculation result exceeds 10 digits.
4} The division by zero.
5) The extraction of square root of a negative number.
Rough estimate calculation error
The integral part of the result of anyone of standard for functions, percentage, square, reciprocal and power calculations exceeds 10 digits and is equal to 20 digits or less.
Error indication
System error
"0" is indicated in the 1 digit position and "E" in the sign-digit position.
Rough estimate calculation error
The high-order 10 digits of a calculation result is indicated together with "E". The decimal point is indicated in
the position corresponding to a calculation result time 10- 1 and no zero shift is performed.
°,
Error release
System error
A system error can be release by the AC or ON/CCE key.
Rough estimate calculation error
A rough estimate calculation error can be released by the AC or ON/CCE, CE key. A calculation result is not cleared
by ON/CCE or CE key but is retained.
• Number entry
Numericals can be entered up to 10 digits. Numerical enteries equal to 11 digits or more are ignored.
ciS
SAMSUNG
173
KS6029
CMOS DIGITAL INTEGRATED CIRCUIT
• Memory protection
In any error detection, the memory counters present before the error detection are protected.
• Memory indication
If the memory contents are a number other then zero, "M" is indicated in the sign-digit position.
• Doubler key depression
The order of the priority when two keys are being depressed simultaneously, is regarded as follows:
When the OFF and AC key are depressed simultaneously, the OFF key is given priority.
• Key bounce protection
Front edge
Down to 1 word and up to about 3 words.
Trailling edge
9 words.
1 word 3.3ms when display frequency fd = 100Hz.
DISPLAY FONTS
• Numericals font
I-II 1- 1_
_11_1
I~ .1-1
11-1
-1-1 1-·1
11_1
• Sign font
M
Memory
c8SAMSUNG
E
Error
Minus
174
CMOS DIGITAL INTEGRATED CIRCUIT
KS6029
LCD connector
1-11- 1-11-1-111-IM
- '-III
11_1 _-I - I_'
__ E
H3 H4 bl0 al0 b9 a9 ba aa b7 a7 b6 a6 b6 a5 b4 a4 b3 83 b2 a2 bl al aO H2 Hl
II
~~&fj ¥~
b2
a2
bl
al
alO
AUTO POWER OFF/DISABLE
After 9·11 minute from the last key pressure power is off automatically. By connecting APODIS pin to GND or VGG •
whether an auto power off function is available is determined.
APODIS
Auto·power·off state
GND
disable
VGG
enable
AC key
All operation including memory contents are cleared by AC key.
Make·up and make·down calculation
Make·up and make·down calculation are performed as follows.
Entry
A
+
B
%
Display
A
x
B
%
+OR-
=
A
A
B
A+AM/100
A
A
B
AM/100
AM/100
A+AM/100 OR A-AMI100
• AM: Amount
c8SAMSUNG
175
KS6029
CMOS DIGITAL INTEGRATED CIRCUIT
PIN ASSIGNMENT
Pin No.
Signal
1/0
Description
Pin No.
Signal
I/O
Description
Display Output
1
VSb
I
Solar Battery
25
b8
0
2
VOP
I
Option Pin
26
a9
0
Display Output
3
VGG
Power Supply
27
b9
0
Display Output
4
APODIS
I
APO Disable
28
a10
0
Display Output
5
H1
0
Display Output
29
b10
0
Display Output
6
H2
0
Display Output
30
H4
0
Display Output
7
NC
31'
H3
0
Display Output
8
aO
0
Display Output
32
GND
9
a1
0
Display Output
33
VC
0
Capacitor
Terminal for
Voltage Set-up
10
b1
0
Display Output
34
VA
0
Capacitor
Terminal for
Voltage Set-up
11
NC
35
VB
0
Capacitor
Terminal for
Voltage Set-up
12
a2
0
Display Output
36
EXTNL
I
External Clock
13
b2
0
Display Output
37
FDIS
I
FOSC and Freq,
Doubler Disable
14
a3
0
Display Output
38
K3
I
Key Input
15
b3
0
Display Output
39
K2
I
Key Input
16
a4
0
Display Output
40
A2
0
Strobe Output
17
b4
0
Display Output
41
A3
0
Strobe Output
18
a5
0
Display Output
42
A4
0
Strobe Output
19
b5
0
Display Output
43
A5
0
Strobe Output
20
a6
0
Display Output
44
P2
0
Strobe Output
Strobe Output
21
b6
0
Display Output
45
P1
0
22
a7
0
Display Output
46
K5
I
Key Input
23
b7
0
Display Output
47
K6
I
Keylnpul
24
a8
0
Display Output
48
K4
I
Key Input
c8SAMSUNG
176
CMOS DIGITAL INTEGRATED CIRCUIT
KS6029
II
b8 25
12
89 26
11 NC
b9 27
10 b1
'--------1810 28
9 81
' - _ - - I b10 29
~------1 H4
c8SAMSUNG
30
8
KS8029
a2
ao
f-----'
7 NC
177
KS6029
CMOS DIGITAL INTEGRATED CIRCUIT
b8 25
12
a2
a9 26
11
NC
be 27
10
bl
al0 26
9 al
bl0 29
6
H4 30
7 NC
H3 31
c8SAMSUNG·
KS6029
ao
6 H2
178
KS6029
CMOS DIGITAL INTEGRATED CIRCUIT
INTERNAL VOLTAGE LIMITER BONDING OPTION METHOD
OPTION 1
II
(Configuration using internal voltage limiter)
OPTION 2
(Configuration using external voltage limiter)
c8SAMSUNG.
179
KS6029
CMOS DIGITAL INTEGRATED CIRCUIT
PAD DIAGRAM
(2460 x 2710)
2460
I
0
'"'"
...iil
0
'"'"
0
E key.
• Floating mode
10'0 s I x I s10'oo
: Exponent display.
10-99 s I x I s1O- 9
: Exponent display.
o and 1O-9 s I x I s10'o: Floating display.
• Engineering mode
and 1O-99 S I x I s10'oo (all ranges); Exponent display.
F-E key also convert the display format of a displayed numerical value simultaneously with the display format
setting.
At the same time, number of digits below the decimal point of the above modes follows the display format assigned
by 2ndF and F-E keys.
Further, in the same manner as F-E key, the conversion is also taken place simultaneously with the display format
setting.
'
When the number of digits is specified, the displayed last digit is a rounded number, and when there is no specification of the number of digits, the displayed last digit is a cut number.
o
Example:~
[J
0 [J
0.285714285
TAB
I
I I
12ndF
I
F+->EI
0
0.286
2.857-01
F+->E
TAB
12ndF
I
I
F+->E
I
D
2.8571428-01
c. Negative numbers are not displayed with the minus symbol ,~, but are displayed in hexadecimal, octal, and binary
two's complement.
d. Display style and special display
• Display st1'le.
• Special display
c8SAMSUNG
184
KS6041
CMOS DIGITAL INTEGRATED CIRCUIT
e. Examples of display
• Floating of -6000 1/x; TAB=7
I-I 1-' I-I I-I
1_10 I_I LI I_I
I- I- 1-'
I , I , I
• Same as above, engineering display
I I- I- I- I- I- I 1-'
-I I_I I
10 I I I I I I I I I-
I-I
I_I I-I
II
• Error display
DEG
I-I
1_10
E
(6) Protection
a. Memory overflow protection
If the overflow occures in the memory calculation, the data before calculation is retained.
b. Statistical overflow protection
If the overflow occures in the statistical calculation, the data before calculation is retained.
(7) The number of digits of the internal retained data.
The number of digits of the mantissa of displayed data is maximum 10 digits, but the available data for successive
calculation is the internal retained data.
The number of digits of the mantissa of internal retained data is as follows.
a.
b.
c.
d.
e.
f.
g.
Data input
Arithmetic
Engineering function
Statistical function
Complex number function
Memory calculation
Number of random
Maximum
Maximum
10 digits.
10 digits.
Maximum
3 digits
(8) Auto clear
When the power supply is suddenly turned on, auto clear routine is executed to initialize as DEC mode, no TAB, floating
and DEG mode.
(9) Power off function.
a. Auto power off
In about 7.5 minutes, after operation ended or pressing key, the power supply is turned off.
b. OFF
Pressing tlie key shall stop the oscillator. (Memory safe guard)
c. ON
Pressing this key shall wake the oscillator and initialize.
c8SAMSUNG
185
KS6041
CMOS DIGITAL INTEGRATED CIRCUIT
OPERATION MODE
(1) Operation mode
~
DEC
BIN
OCT
HEX
STAT
CPLX
0
0
0
0
0
0
0
X
X
X
0
X
Parenthesis ( )
0
0
0
0
X
X
Constant calculation
0
0
0
0
0
X,
Percentage calculation
0
X
X
X
0
Statistical calculation
X
X
X
X
0
X
CPLX calculation
X
X
X
X
X
0
Input a, b
0
X
X
X
X
0
Numberic input 0, 1
0
0
0
0
0
0
Numeric input (2-7)
0
X
0
0
0
0
0
Operation
4 Operation +, -, x, "'",
Power yx,
6
Operation
STAT
CPLX
DATA
setting
x.JY
=
-
X
- - 1----------
Numeric input 8, 9
0
X
X
0
0
Hex input A-F
X
X
X
0
X
X
., Exp
0
X
X
X
0
0
+/-
0
0
0
0
0
0
Shift key
0
0
0
0
0
0
0
0
0
0
0
0
CE
Memory
Memory calculation
0
0
0
0
0
0
Display
conversion
P<-~E,
0
X
X
X
X
X
P-R
conversion
P->R
R->P
0
X
X
X
X
Random
RND
0
X
X
X
0
0
Function
1 variable function
0
X
X
X
0
0
Augular
conversion
DRG
0
X
X
X
0
0
TAB
DRG~
c8SAMSUNG
I
0
-- - - - -
186
KS6041
CMOS DIGITAL INTEGRATED CIRCUIT
(2) The calculation is always shifted to a specified mode by mode keys.
A Mode ~ B Mode
'iZ
DEC
BIN
ocr
HEX
STAT
CPLX
DEC
NOP
DEC
Conversion
DEC
Conversion
DEC
Conversion
DEC
Conversion
State clear
DEC
Conversion
State clear
BIN
BIN
Conversion
NOP
BIN
Conversion
BIN
Conversion
BIN
Conversion
State clear
BIN
Conversion
State clear
OCT
OCT
Conversion
OCT
Conversion
NOP
OCT
Conversion
OCT
Conversion
State clear
OCT
Conversion
State clear
HEX
HEX
Conversion
HEX
Conversion
HEX
Conversion
NOP
HEX
Conversion
State clear
HEX
Conversion
State clear
STAT
Display
Clear
Display
Clear
Display
Clear
Display
Clear
NOP
Display
Clear
CPLX
Display
Clear
Display
Clear
Display
Clear
Display
Clear
Display
Clear
State clear
NOP
NOP: No operation.
KEY DEFINITIONS.
(1) 2ndF
This is the key for specifying the second function.
When this key is pressed, the special display "2ndF" lights. When this key is pressed twice continuously, the second
function mode is released.
(2) DRG DRG~
a. Pressing this key shall change the mode of angle sequencially
C DEG ~ RAD ~ GRA~ and displayed it.
b. Pressing this key after 2ndF key shall change the mode of angle and shall convert the displayed data
DEG ~ RAD
7r
RAD=DEGx180
RAD .... GRAD GRAD=RADx 200
DEG=GRADxO~
GRAD .... DEG
(3) 0-9
a. In setting data in the mantissa section, it is set at the right margin, and data in more than 11 digits cannot be input.
b. At the data input against the exponent, last two number are efficient.
(4)a.
b.
c.
RND
The position first pressed has preferenced, and no input is made to data set in the exponent section.
When pressed as the first set number, it is regarded as 0 and - keys are pressed.
Random as a 2ndF
Pressing this key shall display the random numbers.
The range of random numbers is 0.000-0.999.
(5) +/-
a. In setting data in the mantissa section, this key reverses code in the mantissa section.
Similarly, for exponent section, it reverses code in the exponent section.
b. For the operation "result, this key reverses codes in the mantissa section"
c8SAMSUNG
187
II
CMOS DIGITAL INTEGRATED CIRCUIT
KS6041
(6)
+ - x -;-
= (
)
a. When the key operations are performed by these keys according to a numerical expression, a result of operation
is obtained according to mathematical priorities. Priorities discriminated are;
1) 1 Variable function
2) Expression in ( ); (The most inner expression has priority in case of multiple parentheses)
"'-fY
3) y',
4) x,-;5) +,-
b. Whenever the key is operated, the calculator discrimiuates the above priorities and holds the data and operation
keys pending as required.
This pending action is possible up to 6 times and 7 or more pending become error.
c. (Key is accepted only immediately after CE, +, -, x, -;-, y3" '-J\j, =, ( keys and not accepted in all other cases.
When this key is accepted, the displayed data is cleared to O.
When ( key is first accepted, the special display "( )" illuminates.
When a parenthesis expression is completed) and = keys or when it is cleared by ONtC key, etc, or when errors are
generated, the special display "( )" goes out.
d. If it is within the allowable range of pending, ( can be input into any place in an expression as many times as desired.
However, if the key is pressed continuously 16 times or more, it be comes error.
e. From a viewpoint of numerical expression, even when the corresponding C key is not pressed, the operation is not
executed if ) key is pressed. On the other hand, when ( key is pressed and = key is pressed without pressing the
corresponding ) key, the operation' is also completed according to the priority.
(7) Memory calculation (x .... M, RM, M+)
a. Memory register "M" used by these keys is the completely independent single memory.
b. Display data is added to "M" (memory register) by M+ key.
If data overflows at this time, the proceeding data is held.
c. Display data is stored in "M" by x-->M key.
d. Contents of "M" is displayed by MR key.
e. When data except for 0 is stored in "M", the special display "M" illuminates.
(8)
"Ii"
a. This key displays a rounded value (3.141592654) of a 12 digit value (3.14159265359) according to the set display format.
b. A value that is used in a subsequent operation is the above 12 digit value.
c. The display is cleared by the following 1st numeric key and a new data is set.
(9) % Calculation
a. When any arithmetic functions or constant mode has not been set, the displayed number is converted from a
percentage to a decimal.
Example) 61.5%
Display
6 1 . 5 % 0.615
b. When = key is pressed after % with any arithmetic function
• Add-on
axb
• y', '.fi.
R+b
--> a+ 100
a y' b
%
• Discount
axb
a-b
%
--> a- 100
a '.JY b
%
• Percentage
axb
%
axb
-->100
a-;-b
%
-->~ x100
b
(10) Trigonometric and arctrigonometric function (1 Variable)
(sin cos tan sino, COSo, tan-')
These functions are calculated according to respective defined areas and accuracy show in (6), and displayed result
of operation can become operators.
(11) Hyperbolic and archyperbolic function.
(hyp --> sin cos tan, archyp --> sin cos tan)
Same as trigonometric function.
c8SAMSUNG
188
KS6041
CMOS DIGITAL INTEGRATED CIRCUIT
(12) Exponential and logarithmic function.
(eX 10X In log)
Same as tigonometric function.
(13) Reciprocal, square, square root and cube root.
(1/x x2 ";-3";-)
Same as trigonometric function.
(14) Factorial function (n!)
n!=nx(n-1)x(n-2)x ...... x2x1.
Same as trigonometric function.
(15) .... OEG .... OMS
a. These keys convert degree, minutes and second into decimal degree and decimal degree into degree minutes and
second, respectively.
b. On the OMS format, the integer part of display data is regarded as degree, 2 digits below the decimal point as minute
and 3rd digit and below as second.
-OMS
1.999999999
59
minute
degree
5999
second
.... xy)
(16) Coordinate conversion (a b .... rO
a. These keys convert the rectangular coordinates into the polar coordinates and the polar coordinates into the
rectangular coordinates, respectively. The angle unit that have been set by ORG key is followed.
b. Respective defined areas and accruacy are as shown in (6), however, the range of 0 obtained by R .... P in degree
is as follows.
1st
2nd
3rd
4th
Quadrant
Quadrant
Quadrant
Quadrant
0° s 0 s
90° s 0 s
-1800s0s
-90° s 0 s
90°
180°
-90°
0°
c. Input of 2 variables is performed oy setting
x or r by pressing a key and
y or 0 by preSSing b key.
d. The operation result of x or R is obtained in the display register or by preSSing a key and y or 0 by pressing b key.
Input Data
Result
a
b
a
b
R .... P
(Rectangular .... Polar)
x
y
r
0
P .... R
(Polar .... Rectangular)
r
0
x
y
( .... r, 0) r=--Jx2+y2, 0=tan-1 y/x
( .... x, y)x=rcosO, y=rsinO
e. (R .... P Conversion) (lx, y] .... Ir, 0])
Key operation
x
a
y
b
.... rO
b
c8.SAMSUNG
f.
(p .... R Conversion) (lr, 0] .... Ix, y])
Oisplay
o
x
b
x
y
a
y
r
o
o
o
r
.... xy
b
x
y
189
II
KS6041
CMOS DIGITAL INTEGRATED CIRCUIT
(17) Binary mode (2ndF, ~BIN, 0,1)
a. Data input and output are both binary integers in maximum 10 digits.
b. A negative number is expressed in binary number of two's complement.
c. The range of internal operation is as shown below and if the result of operation exceed the range, it becomes error
(overflow)
Binary Number
Outside the operation range
Binary
Positive
Integer
Binary
Positive
Integer
(Complement)
Decimal Number
-
512:s; DATA
1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 0
1 1 1 1 1 1 1 o 1
511
510
509
1 1 1 1
1 1 1 1
1 1 1 1
:
:
1 000
1 o0 0
1 1 1 1
1 1 1 1
1 1 1 0
:
:
0 0 0 0
0 0 0 0
Outside the operation range
:
:
:
10
1
0
:
2
1
0
1
0
1
-1
-2
-3
:
0 1
0 0
:
-511
-512
-512;;,; DATA
(18) Octal mode (2ndF, ~OCT, 0 - 7)
a. Data input and output are both octal integers in maximum 10 digits.
b. A negative number is expressed in octal number display of two's complement.
c. The range of internal operation is as shown below and if the result of operation exceed the range, it becomes error
(overflow)
Octal Number
-
Outside the operation range
Binary
Positive
-Integer
Octal
Negative
Integer
(Complement)
Outside the operation range
c8SAMSUNG
5 3 6 8 709 1 2 :s; DATA
3 777 7 777 7 7
3 777 7 7 7 7 7 6
:
:
-11
0
7 7 7 7
7 7 7 7
1 1 1 1
:
:
4 0 0 0
4 0 0 0
7 7 7 7
7 7 7 7
1 1 1 0
:
:
0 0 0 0
0 0 0 0
Decimal Number
7
6
1
0 1
0 0
5 3 6 8 709 1 1
5 368 709 1 0
:
:1
0
-1
-2
:
-5 3 6 8 7 0 9 1 1
-5 3 6 8 7 0 9 1 2
-5 3 6 8 7 0 9 1 3
2:
DATA
190
CMOS DIGITAL INTEGRATED CIRCUIT
KS6041
(19) Hexadecimal Mode (2ndF, -+HEX, 0 - 9, A-F)
a. Data input and output are both hexadecimal integers in maximum 10 digits.
b. A negative number is expressed in hexadecimal number of two's complement.
c. The range of internal operation is as snown below and if the result of operation exceed the range, it becomes error
(overflow)
Hexadecimal Number
Decimal Number
-
1x10 ' Os DATA
Outside the operation range
254 0 B E 3 F F
2 5 4 0 B E 3 F E
:
Hexadecimal
Positive
Integer
9 9 9 9 9 9 9 9 9 9
9 9 999 9 999 8
Hexadecimal
Negative
Integer
(Complement)
II
:
:
:
1
0
1
0
FFFFFFFFFF
F F F F F F F F F E
-1
-2
:
:
:
:
FDABF4 1 CO2
FDABF4 1 CO 1
-9 9 9 9 9 9 9 9 9 8
-9 9 9 9 9 9 9 9 9 9
Outside the operation range
-1x10'°2: DATA
(20) Complex number mode (2ndF, CPLX)
a. Pressing these keys shall set the complex number mode.
b. Input of 2 parts is performed by setting the real part (X; pressing a key) and the imaginary part (Y; pressing b key)
c. The operation result of the real part is obtained by pressing = or a key and the imaginary part by pressing b key.
Input Data 2
Input Data 1
Item
Real
Imaginary
Imaginary
Result
Function
Real
a
b
a
b
X2
Y2
X1+X2
Y1+Y2
a
b
Addition
X1
Y1
+
Subtraction
X1
Y1
-
X2
Y2
Multiplication
X1
Y1
x
X2
Y2
Division
X1
Y1
X2
Y2
Real
X1-X2
X1X2-Y1Y2
X1X2+Y1Y2
X22 +Y22
Imaginary
Y1-Y2
Y1X2+X1Y2
Y1X2-X1Y2
X22 +Y22
(21) Static calculation mode (2ndF, STAT)
a. Pressing these keys shall set the statistic calculation mode.
b. Available number of data is the positive integer, such as 0 s n s 9999999999, and when the number of data exceeds
this integer, it becomes error.
e. The input range of the data are as follows Os I data Is 1x1050
This data exceeds the ranges, it becomes error.
d. n Ex Ex2
These keys display the number of data (sample), each sum total of x and sum total 01 x 2
n
Ex;
• Average; x
=~
n
c8SAMSUNG
Ex
n
191
CMOS DIGITAL INTEGRATED CIRCUIT
KS6041
• The standard deviation of the sample
s=
,.,;: (xi-x)"
The standard devitation of the population
f; (xi-x)2
Ex 2-(Ex)2/n
0=
Ex2-(Ex)2/n
i=1
n
n
ERROR CONDITIONS
(1) The result of operation in exponent parts exceed +99
(2) Entering more than the calculation range (6) of each function.
(3) Dividing by zero.
(4) In statistical calculation.
a. x, s, (J when n=O
b. s when n=l
(5) The number of pending operations exceeds 3
(6) The number of the parenthesis in the one level exceed 15
OPERATION RANGE AND ACCURACY.
Function
sin x
cos x
tan x
_.
sin-' x
cos-' x
lan-' x
Angle
Unit
Operation Range
Under Flow Area
DEG
Os I x I s4.499999999xl0'o
Os Ix I s5.729577951xlO- 98
RAD
Os I x I s7853981633
GRAD
Os Ix I s4.999999999xl0'o
DEG
Os I x I s4.500000008xl0 1O
-
-
-
RAD·
Os I x I s7853981649
GARD
Os Ix I s5.000000009xl0'o
DEG
Same as sin x
Os Ix I s6.36619m3xl0- 98
Same as sin x
RAD
Same as sinx
Same as sin x
GARD
Same as sin x
Same as sin x
DEG
Oslxlsl
Os Ix I sl.570796326xl0-"
RAD
Os I x I sl
GARD
Os Ix I sl
DEG
Same as sin-'x
RAD
Same as sin-' x
Os Ix I sl.570796326xlO-"
-
Os I x I s9.999999999xl099
RAD
os I x I s 9.999999999 x 1099
GARD
Os I x I s9.999999999 X 10"
log x
Osx
eX
- 9.999999999 x 1099 S
230.2585092
c8SAMSUNG
--
-
Same as sin-' x
DEG
Osx
10 digits
±1
-
GARD
In x
Normal
Accuracy
Same as sin-' x
Same as sin-' x
X S
-9.999999999xl099 s
-227.9559243
X
s
192
CMOS DIGITAL INTEGRATED CIRCUIT
KS6041
OPERATION RANGE AND ACCURACY.
Function
(Continued)
Operation Range
10X
- 9.999999999 x 1099 S
99.99999999
x!
Os x s69 (integer)
X
s
Under Flow Area
-9.999999999 x 1099 s x s
- 99.00000001
-
1 X 10-··s I x Is 9.999999999 X 10.9
1.000000001 X 10·9 s I x Is
9.999999999 x 1099
x'
Os I x I s9.999999999 X 104•
Os I x I s3.162277660x 10- 50
-..Ix
Os I x I s9.999999999 X 10··
W
Os I x I s 9.999999999 X 1099
-
DMS .... DEG
Os I x I s9.999999999 X 10·
-
DEG .... DMS
Os I x I s9.999999999 X 10·
1
X
Os I x I s230.2585092
-
cosh x
Os I x I s.230.2585092
-
tanh x
Os I x I ~9.999999999 X 10··
-
sinh- 1 x
Os I x I s4.999999999 X 10··
-
cosh- 1 X
1 s x s 4.999999999 x 10··
tanh- 1 x
Os I x I s9.9999999999 X 10- 1
II
Os I x I s 2.777777777 x 10-··
)C
sinh
Normal
Accuracy
R .... P
(x,y) (r, 8)
Ixl. Iyl s 9.999999999 x 104•
(X2 + y2) s 9.999999999 x 10··
correspond to the under flow area
oftan x
P .... R
(r, II) (x,y)
Os rs9.999999999 x 1099
8 correspond to the operation range
of sin x, cos x
8 correspond to the under flow area
of sin x, cos x
Os I x I s5.729577951
DEG .... RAD
Os I x I s9.999999999 x 1099
RAD .... GARD
Os I x I s 1.570796326x 10.8
GARD .... DEG
Os I x I s9.999999999 x 10··
Oslxls1.111111111 x10- 99
- 9.999999999 X 10··sx. In Iyl
s230.2585092
- 9.999999999 x 10·· s x. In Iyl
s -227.9559243
X
10 digits
±1
1098
-
---
yx
i) y> 0; The above - mentioned operation range
ii) y < 0; x (integer) or 1/x (x = odd, x = 0)
The above - mentioned operation range
iii) y=O; x>O
- 9.999999999 x 10 s..!. In Iyl s
230.2585092
x.
x..JY
- 9.999999999 x 10 s..!. In Iyl s
_ 227.9559243
x.
i) y>O; The above - mentioned operation range.
ii) yO
.... DEC
The following operation range after the conversion .
Os Ix I s 9999999999
-
.... SIN
The following operation range after the conversion .
1000000000s x s 1111111111, Os x s 1111111111
-
c8SAMSUNG
193
KS6041
CMOS DIGITAL INTEGRATED CIRCUIT
OPERATION RANGE AND ACCURACY.
Function
-->OCT
(Continued)
Operation Range
Under Flow Area
The following operation range after the conversion.
4000000000::;; x ::;;777777777, 0::;; x ::;;3777777777
Normal
Accuracy
-
-
-->HEX
Complex number
calculation
Statistical
calculation
The following operation range after the conversion.
FDABF41C01::;; x ::;;FFFFFFFFFF, 0::;; x ::;;2540BE3FF
(X1+Y1i) +, -, x, .;. (X2+Y2i)
i) Addition and subtraction
IX1+X21 ::;;9.9999999999x1099
IY1 + Y21 :5 9.9999999999 x 1099
ii) Multiplication
IX1X2-Y1Y2I :5 9.9999999999x1099
IY1X2-X1Y21:5 9.9999999999x1099
IX1X21. 1Y1,Y21.1Y1X21. IX1Y21 ::;; 9.9999999999 x 1099
iii) Division
/X1X2+Y1Y2/
r1X2-X1Y2/ :5 9.999999999x1099
X2 2+Y22
,
X22 +Y22
IX2 2+Y2 2I , IX2 21.1Y221. IX1X2+Y1Y21.1Y1X2-X1Y21
IX1X21, 1Y1Y21, 1Y1X21, IX1Y21:5 9.9999999999x10 99
i)
ii)
iii)
iv)
v)
Data; Ixl:59.9999999999x10
lI:xl ::;; 9.9999999999 x 10
lI:x 21:59.9999999999x10
x; n=O
s; n=1 n=O
0:5
-
10 digits
±1
--
10 digits
±1
I:x2 - (I:x)2/n
:5 9.9999999999x10
n- 1
vi) 0"; n=O
0:5
c8SAMSUNG
I:x 2 _ (I:x)2/n
:5 9.9999999999 x 10
n
194
KS6041
CMOS DIGITAL INTEGRATED CIRCUIT
LCD CONNECTION
a. Segment
45
44
41
40
39
38
37
36
35
34
33
32
29
28
27
28
25
24
23
22
21
20
",,,,,,II
b. Common
15 COM4
L-_--=C.::.-OM:.::,3=__ 48
COM1
141-----.J
L -_ _----=C.=.OM:.:;;2=-47
WOVEFORM OF COM
I
iI
I
I
I t---'Z>I
I
r--VDD (3V)
1-_......._ _-;1 I - - w
I
I
I
iI
iI
COM1-'1--~
GND
II
II
II
I
r---+-_-;I I
I
I
COM2 1 I
II
:1-1_ _+_.......
I
I
COM3 1 I
II
Ir-I--.:......--;
I
COM4 1 1
II
II
1t-i1r----160Hz(6.25ms)----f
II
II
O.034ms
II
c8SAMSUNG
195
KS6041
CMOS DIGITAL INTEGRATED CIRCUIT
EXTERTAL CONNECTION
(1) Pin description
Pin
No.
Signal
1/0
Description
Pad
No.
Pin
No.
Signal
1/0
Description
Pad
No.
0
0
LCD (Key output)
16
LCD (Key output)
17
0
0
0
LCD (Key output)
18
LCD (Key output)
19
LCD (Key output)
20
1
KI8
I
Key input 8
40
25
b4 (KO)
2
FODIS
I
Fosc disable
41
26
a5 (KO)
3
EXTNL
I
External clock
42
27
b5 (KO)
4
KITEN
I
Key in test enable
43
28
a6 (KO)
29
b6 (KO)
Vss Power (G N D)
44
30
Vss
Vss Power (GND)
21
31
VDD
VDD Power (+ 3V)
22
32
a7
23
b7
0
0
0
0
LCD
33
LCD
24
0
0
0
0
0
LCD
27
LCD
28
LCD
31
0
0
0
0
LCD
32
No Connection
33
5
NC
6
Vss
7
NC
8
VDD
9
NC
10
TST
I/O
11
DEN
VDD Power (+ 3V)
45
Test
1
34
a8
I
Dump Enable
2
35
b8
12
KI1
I
Key Input 1
3
36
a9
13
KI2
I
Key Input 2
4
37
b9
14
COM1
5
38
a10
COM4
Common Signal 4
6
39
b10
16
aO (KO)
0
0
0
Common Signal 1
15
LCD (Key Output)
7
40
a11
17
bO (KO)
0
0
0
0
0
0
0
0
LCD (Key Output)
8
41
b11
18
a1 (KO)
19
b1 (KO)
20
a2 (KO)
21
b2 (KO)
22
a3 (KO)
23
b3 (KO)
24
a4 (KO)
c8SAMSUNG
LCD (Key Output)
9
42
a12
LCD (Key Output)
10
43
b12
LCD (Key Output)
11
44
a13
LCD (Key Output)
12
45
b13
LCD (Key Output)
13
46
COM3
LCD (Key Output)
14
47
LCD (Key Output)
15
48
LCD
25
LCD
26
LCD
29
LCD
30
No Connection
34
LCD
35
LCD
36
Common Signal 3
37
COM2
0
0
0
Common Signal 2
38
KI4
I
Key Input 4
39
196
KS6041
CMOS DIGITAL INTEGRATED CIRCUIT
APPLICATION CIRCUIT
(1) LCD connection
I
I
I
I
LCD
I
Ir=r=- -r~
2l1~ ~I~I~I~ ~I~ ~I~
II
I
C)
'"
36
b9
~
L--
34
33
32 31
30
29
28
27
26
25
37
24
r---810
r----
-
35
....c
bl0
23
38
39
22
all
40
21
bll
41
20
a12
42
19
b12
43
C----
-
-
KS6041
18
a13
44
17
b13
45
16
-
-
83
-
b2
-
a2
bl
al
bO
aO
t---
KI4
15 COM4
t--14 COMI
f---48
1
2
3
4
5
6
7
8
9
~1~1~lffilul
~Iu ~eluz
u. w ><
~Oxt:z>z
10
11
~Iz0w
13 KI2
121'"""'----
CJ)
;;<
b2
a2
~
~J!~
(2) Key connection
NOTE:
b3
t---
r-----
a5
-
t---
COM3 46
I--------COM2 47
b6
-
-
-
84
-
a5
b5
~
b4
a4
b3
a3
bl
al
aO
bO
1.IF
~ 2ndFH
c8SAMSUNG
197
KS6041
CMOS DIGITAL INTEGRATED CIRCUIT
KEY CONNECTION
K\~
2nd F
1st F
16 -
0
17 -
=
18 --
1
19 -
20 -
X~M
RM
~48
HEX
STAT
%
r
I 1:: x
I
I
1:><"
I
I
n
X
-
22 231 24I -
M+
-
G
I
CD
S
~
t--
+
~DEC
(
,
1st F
HEX
:-
I
l_--III.-_l_--I'8!
HEX
OFF
f-----
CE
nl
r---
~
CPLX
r---
I
:t--
2nd F
112
ON/C
-
I
I
I
DATA:
STAT
or 31
t--
I--
F-E
TAB
r---
~ll:'(
r-----
+
~BIN
f---
b
f--
x
~OCT
f---
x'
1/x
r-----
-
6
f---
a
~re
c--
r--
9
f---
tan
tan-1
r-----
'--
2
f---
"
f---
cos
cos-1
log
10><
F
r-----
In
e'
E
r-----
..J
~HEX
3
.
2nd F
I
I
I
2nd F
r--
I
I
21
1st F
KI1
'1~3
RND
~
C
r-----
25, -
1
I--
5
26; -
4
r--
8
27' -
7
r--
Y'
~
B
._-
281 -
+1-
r--
EXP
T
A
f-----
sin
sin- 1
r-----
291 -
~DEG
r--
hyp
archyp
,--
DRG
DRG~
r-
~DMS
0
~
r-----
r---~-·-l
NOTE: :
:
lI _____ --'-I
c8SAMSUNG
= STATISTIC MODE KEYS
198
KS6041
CMOS DIGITAL INTEGRATED CIRCUIT
PAD DIAGRAM
~ ~ @] ~ @] ~ @] §J @] @] @J ~
a9
b8
a8
b7
a7
VDD
Vss
b6(KO) a6(KO) b5(KO) a5(KO) b4(KO)
@Jb9
a4(KO)~
~a10
b3(KO)
~b10
a3(KO)~
~a11
b2(KO)
~b11
a2(KO)G
~a12
~b12
~a13
B
II
~
b1(KO)~
KS6041 PAD DIAGRAM
Chip Size: 4820 x 5950
Pad Size : 86 x 86
Unit
: I'm
a1(KO)0
bO(KO)0
~b13
AOIKO)
~
COM3
COM40
~
COM2
COM1IT]
~K14
[2J
K12G
K11Q]
K18
c8SAMSUNG
FODIS EXTNL KIT EN
Vss
VDD
TST
~~~~~
~
[1J IT]
DEN
199
NOTES
Voice Synthesizer res
Function
Device
KS5901
KS5901A
KS5902XX
KS5911
KS5912XX
**KS5915
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
** Under Development
1 Chip
1 Chip
1 Chip
1 Chip
1 Chip
1 Chip
Voice
Voice
Voice
Voice
Voice
Voice
Synthesizer (External EPROM)
Synthesizer (External EPROM)
Synthesizer (Internal ROM)
Recorder & Reproducer (External DRAM)
& Sound Generator (Internal ROM)
& Sound Generator (External DRAM)
Package
64
60
24
48
16
60
SDIP
FOP
DIP
FOP
DIP
FOP
Page
.
213
234
248
260
.
VOICE SYNTHESIZER APPLICATION GUIDE
1. CLASSIFICATION OF VOICE LSI
.----Voice Synthesizer
--c
1
Direct wave coding-PCM, ADPCM, DM, ADM
Analysis & Synthesis
.
LPC:
KS5901A
KS5902
PARCOR
FORMANT
I----Voice Recording
& Reproducing
~ :~~CM
C
ADM:
Natural Sound
Generation
II
DM
Voice LSI
-E
KS5911
""KS5915
ADPCM
PCM
DM
ADM:
KS5912
Voice Recognition
PCM
ADPCM
DM
ADM
LPC
PARCOR
:
:
:
:
:
:
Pulse Code Modulation.
Adaptive Differential Pulse Code Modulation.
Delta Modulation.
Adaptive Delta Modulation.
Linear Predictive Coding.
Partial Auto-Correlation.
NOTE: ""Under Development
c8SAMSUNG
203
VOICE SYNTHESIZER APPLICATION GUIDE
2. VOICE SYNTH ESIZER
2·1. External ROM Type: KS5901/KS5901A
A. FEATURES
•
•
•
•
•
•
•
•
•
•
•
Voice synthesis method: LPC
640 KHz X·tal oscillation
8 KHz sampling frequency
Control mode: CPU/manual mode
Various synthesis speed: 0.7 - 1.55 times of normal speed
Direct access to the external ROM (x 8 Bit)
Maximum memory size: 64 KBytes (KS5901A), 512KBytes (KS5901)
Easy interface with CPU
On chip 9 Bits R·2R D/A converter
Single 5V power supply
PKG: KS5901: 64 SDIP
KS5901A: 60 FOP
B. BLOCK DIAGRAM
PROM/MASK ROM
DATA
ADDRESS
CPU
CPU
I/F
KS52000
c8SAMSUNG
KS5901A
204
VOICE SYNTHESIZER APPLICATION GUIDE
2·2. Intemal ROM Type: KS5902
A. FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
Speech synthesis method: LPC
2.56 MHz X·tal oscillation
8 KHz sampling frequency
Control mode: CPU/manual mode
Various synthesis speed: 0.7 -1.55 times of normal speed
Various speech synthesis conditions
48 KBlts on chip data ROM
Easy interface with CPU
On chip 9 Bits R·2R D/A converter
Single 5V power supply
Low power consumption by C'MOS structure
PKG: 24 Dip
B. BLOCK DIAGRAM
I/O
CPU
I/F
KS52000
c8SAMSUNG
KS5902
205
VOICE SYNTHESIZER APPLICATION GUIDE
3. VOICE RECORDING & REPRODUCTION LSI: KS5911
A. FEATURES
•
•
•
•
•
•
•
•
•
•
•
Speech analysis & synthesis method: ADM
RC oscillator: 640 KHz
Selectable bit rate: 8K, 11 K, 16K, 32Kbps
Control mode: Talking back mode/manual control mode
Data memory: 64K or 256K DRAM up to 4pcs
Auto silence detection (Talking back mode)
Recording/Reproducing of max. 16 phrases (Manual control mode)
Built·in DRAM refresh counter
Built·in microphone amplifier & 10 Bits D/A converter
Single 5V power supply
Low power consumption by C2 MOS structure
• PKG: 48 FQP
B. BLOCK DIAGRAM
rI
1
~
RAMx4 pes
256K or 64K
r
RAM INTERFACE
I
DIA
LOW PASS
CONVERTER
FILTER
I
MIC
~
--
AID
CONVERTER
AMP
f--
ANALYZER
L-
SYNTHESIZER
-C(]
SPEAKER
KS5911
c8SAMSUNG
206
VOICE SYNTHESIZER APPLICATION GUIDE
4. VOICE & SOUND GENERATOR: KS5912
A.
•
•
•
•
•
•
•
•
•
•
•
•
FEATURES
Sound synthesis method: ADM
On·chip 64KBits mask ROM
RC oscillator: 640 KHz
Control mode: Manual control
Variable bit rate (Mask option): 32K, 16K, 11 K, 8Kbps
Repeat function: 3 times/8 times
Phrase selectable: 4 phrase
Maximum generation time: 8 sec. (8 KHz sampling)
On·chip 10 Bit D/A converter
Single 5V power supply
Low power consumption by C2 MOS logic
PKG: 16 Dip
II
B. BLOCK DIAGRAM
'--___;-+---l'--___
....J
-
G> --oJ """"
KS5912
c8
SAMSUNG
207
VOICE SYNTHESIZER APPLICATION GUIDE
5. VOICE RECORDING & REPRODUCING LSI: KS5915
A. FEATURE
•
•
•
•
•
•
•
•
•
•
•
•
Speech analysis & synthesis method: ADM
Resonator oscillator: 640 KHz
Selected bit rate: 11 K, 16K, 24K, 32Kbps
Control mode: CPU/manual
Data memory: 256K or 1M DRAM up to 4pcs
Recording/reproducing of max. 16 phrases
Built-in DRAM refresh counter
Built·in microphone amplifier & 10 bits D/A converter
Built·in band pass filter
Voice trigger in recording (Option)
Normal mode/256K fixed mode
PKG: 60 FOP
B. BLOCK DIAGRAM
DRAM
ADM
DfA
IfF
ANAfSYN
CONVERTER
!
MIC
---
MICROPHONE
AID
BAND PASS
AMP
CONVERTER
FILTER
I
I
AMP
SPEAKER
c8SAMSUNG
208
VOICE SYNTHESIZER APPLICATION GUIDE
6. SYNTHESIS LSI FUNCTIONS TABLE
KS5901/KS5901 A
KS5902XX
KS5911
KS5912XX
KS5915
Synthesis Method
LPC
LPC
ADM
ADM
ADM
Operating Voltage
5V
5V
5V
5V
5V
640 KHz
(X-TaIOSC)
2.56 MHz
(X-TaIOSC)
640 KHz
(RC OSC)
640 KHz
(RC as C)
640 KHz
(X-TaIOSC)
8 KHz
8 KHz
8-32 KHz
8-32 KHz
16-32 KHz
Features
Oscillation Frequency
Sampling Frequency
Bit Rate
2.4-9.6 Kbps
2.4-9.6 Kbps
8-32 Kbps
8-32 Kbps
16-32 Kbps
Control Mode
CPU/Manual
CPU/Manual
/Auto
Talk-Back/
Manual
Manual
CPU/Manual
Data Memory
External ROM
512KBytes/64KBytes
Internal ROM
48Kbits
External RAM
64K/256K x4
Internal ROM
64KBits
External RAM
256K/1M x4
Speech Time
Max.
10 Min.l4 Min.
Max.
20 Sec.
Max.
2 Min.
Max.
8 Sec.
Max.
8 Min.
D/A Converter
9 bits
9 bits
10 bits
10 bits
10 bits
64 SDIP/60 FOP
24 DIP
48 FOP
16 DIP
60 FOP
HA
A/M
Toy
Simple
Sound
Information
Message
Phone
A/M
Toy
Message
Phone
A/M
PKG
Applications
c8SAMSUNG
209
II
VOICE SYNTHESIZER APPLICATION GUIDE
7. VOICE SYNTHESIS LSls DEVELOPMENT FLOW
USER
SAMSUNG ACTION
NO
3 DAY
LPC: 14 DAY
per 10 SEC.
ADM: 7 DAY
per 4 SEC.
NO
7 DAY
30 DAY
10 DAY
RELIABI LlTY
APPLICATION
NO
1 MONTH
OUTGOING
c8SAMSUNG
210
db
~
KS5901A APPLICATION CIRCUIT (CPU
<
0
MODE)
(;
m
3:
CJ)
tA
A
c:
z
c;)
-<
Z
-I
::I:
m
1K!l
r----~I P12
XT1
Voo Vee
tA
1N4148 2K!l
I~
I
1
--
6V
"'tJ
"'tJ
1N4148
I
3300
~
..
A
+
~
PO.zE~
---L
10IIII
1N4148
POWER SAVING CIRCUIT
Voo
+..
m"
Vss
All
8)
DAOI
+
n
SOK!l
50K!l
;.1-.....
t"......
.to"'
...
i
~
0
A
SWITCH
10"F
Other
r0
z
C)
+
C
10"F
C
1-
m
50K!l
~·'V
..'V/¥-~-~--
A
/
AO-A12
00-07
PROM (KM2865A)
Voo
DE
Vss
CE
8!l
LOW PASS FILTER
~
-'
II
AUDIO
db
KS5902XX APPLICATION CIRCUIT (KEY MODE)
~
om
ic
en
~
~
Z
~
::J:
Vee (6V)
m
1N4148
N
m
::D
»
""C
KSA733
""C
r-
PS3
o
~
oz
PS2
PS1
PSO
KS5902
~
47pF
x2
VOICE SYNTHESIZER
~
-m
C
l
rh
I\)
RESET
t t~ t~
C)
c
8n
LOW PASS FILTER
AUDIO
KS5901A
CMOS DIGITAL INTEGRATED CIRCUIT
CMOS 1·CHIP SPEECH SINTHESIZER
The KS5901A is a CMOS speech synthesizer which is developed by
Samsung Semiconductor and Telecommunications Co., Ltd. (SST).
SST has undertaken a research & development program on an encoded
reproduction algorithm called linear predictive coding (LPC). Speech is
synthesized by processing an externally provided variable bit stream of
LPC encoded speech data, and converting the results to the audible
output with an on-chip 9 bits D/A converter.
The speech syntheSiS system using KS5901A is composed of the
following three chips;
KS5901A: CMOS speech syntheSizer
PROM : Commercial non-volatile memory (x8 bit)
Micomlwprocessor: 4/8 bits system controller (CPU mode)
eo FOP
With a considerable memory expansion and controller interfacing
capacity, the KS5901A performs speech synthesiS operation required
for various applications. As the KS5901 A is a CMOS LSI, the power
consumption is small enough to satisfy the power speCification.
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
Speech synthesis method; LPC (Linear Predictive Coding)
640 KHz crystal OSCillation
8 KHz sampling frequency
Control mode; CPU control/manual control
Various synthesis speed; 0.7-1.55 times of normal speed.
Various speech synthesis conditions;
· Excitation source
Voiced speech; impulseltriangular pulse
Unvoiced speech; white Gaussian noise
Bit allocationiframe
48 bits/frame; nonlinear transformation
96 bitslframe; linear transformation
Frame length; 10/20msec per frame
· Repefi,tion of the speech parameter set is possible.
· Loss faator of the synthesis filter is controllable.
• Variable stage of the digital filter; 8110 stage.
Direct access to the external ROM (x8 bit)
Maximum memory size; 64K bytes
Easy interface with CPU
• 4 Dits interface bus line
• 12-kinds of command
· Monitoring the 4 kinds of status flags
· BUSY, EOS (End of speech) output
· External ROM data dump mode
· Less CPU overhead
On chip 9 bits R-2R D/A converter
Low power consumption due to the 2-phase CMOS structure
Single +5V power supply
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"KS5901A
CMOS DIGITAL INTEGRATED CIRCUIT
BLOCK DIAGRAM
Interpolator
K-stack
External
Excitation
Generator
ROM
Booth
Re-encoder
Manual
switches
Pipeline Multiplier
WE
4J8bllS
CPU
RE
Parallel Adder
CPU
Interface
Block
Digital
Filter
Loss & Delay Stack
BE
BuSY
Multiplexer
I I II I
...1
EOS
Timing
Control
CX1
CX2
X·tal
D
640 KHz
.) LPF: LOW PASS FILTER
Fig. 1 KS5901A functional block diagram
PIN CONFIGURATION
30
29
26
25
-KS5901k
(Speech synthesizer)
24
2.
en
21
20
,.
18
11
UI2
0t1I
or.
""
DT8
017
Fig. 2 Pin configuration (60 FOP top view)
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KS5901A
CMOS DIGITAL INTEGRATED CIRCUIT
PIN DESCRIPTION
Name
Pin (No.)
A'5-Ao
(58-60,1-5,7,9-15)
Address output
Used for external PROM Interface
(16 bits address line)
Output
. _ - - - - - - - --- - - - - - - - - f------
--
DT7-DTc
(16-23)
Input
Data input
-------------- - - - - - - -
MODE (24)
Mode switch
-------
SR(25)
System reset
~-----
-- -------
-
M-START (26)
Manual start
1-------------- --_.-
.-
Input/Output
Input
----
-_ ..
--_.-
-
._- - - - - - -.. _.. _-----
EXC(29)
Excitation
source
Input
H: Triangular pulse
L: Impulse
REP (30)
Parameter
repetition
Input
H: Without repetition
L: With repetition
NOFS (31)
Number of
filter stages
Input
H: 8-stages
L: 10 stages
NOBA(32)
Number of bit
allocation
Input
H: 96 bits/frame
L: 48 bits/frame
FRL(33)
Frame length
Input
H: 10 msec/frame
L: 20 msec/frame
LODF(40)
Loss of digital
filter
Input
H: With Loss
L: Without Loss
Input
Output
f---
Pins for connecting crystal oscillator
- - r--
----
(In the manual control mode, these pins must be selected
to "H" or ''I.:' according to the synthesis conditions.
- - - - - - -_.
-----
._ ..
-------
Input
Pins for LSI Test (normally ground)
Output
Pins for LSI test
(these pins should be open.)
------
Test
---.---
----------~---------
Oscillator
TDFe(43)
TDFO(45)
---------
In the manual control mode, M-START signal initiates
reading of external ROM data, starting the syntheSiS
operation.
-------------
Test
-----
--~---
System reset. Clears internal registers. (active low)
CX1 (27)
CX2(28)
TEXC(34)
TDAe(41)
TINI(42)
TDAI(44)
------~-----.
Selects CPU or manual control mode
H: CPU control L: manual control
Input
-._.- c------- ----
... _ - - - - - _ .
Used for speech data input from external PROM
(8 bit data line)
- - -- - - - - - - - - - 1------
1--------- -
_._._--
Function
Input/Output
....
~~------
-------------
1
-_ ..
---
se3 -seC
(39,37-35)
Speed select
Input
In the manual control mode, the synthesis speed follows
the "H"/"L:' combination of SCO-SC3. Synthesis speed
is varied from 0.7 to 1.55.
DAO(46)
D/A output
Output
9 bits R-2R D/A converter output
APD (47)
Audio power down
Output
Controls the power of external audio circuit
< I >< I
D3
121
X3: X2
XO
DO
D3
DO
Address in address counter
IX2
><
Xol
Ala· . A16
A15
.
A12
All
AS
A7
A4
A3
AO
Fig. 7. ROM start address
• After loading the start address, the STRT command initiates the KS5901A to read the external ROM data and start the
synthesis operation.
• The address counter continues to increase during synthesis operation until ENDI code of the ROM data is detected.
• When ENDI code is detected address counting is stopped and the KS5901A returns to the stand·by state.
• In stand·by state, the synthesis operation of the phrase currently addressed can be activated by STRT command
• If END2 code is detected, the start address previously specified by LDADR command is fed to the address counter, and
the synthesis operation is repeated. The repetition is continued until the external control, such as STOP/ODIS command
or system reset, is given.
S. Indirect addressing
In this mode, some part of speech data ROM iSlused to the index area. The label must be given to each phrase to be
synthesized. The contents stored at the label address are used as the real start address. Address loading sequence of Indirect
addressing mode is as follows.
• UsingLDADR command, CPU loads~the label address of the phrase to be synthesized to the address counter.
• Using DDMP command, CPU reads the start address data (3 bytes), i.e., the contents in the memory location pointed to
by the label address and the next two addresses. And save then at the temporary area in the controller.
• Using LDADR command, CPU loads the real start address to the address counter of the KS5901A.
• The real start address must be stored in the format shown in Fig. a & 9. The LSS (bO) atthe label address should be excluded
in storing the start address. As the KS5901A has the addressing range of AO·AI5, the last byte only contains one bit address
data of A15 at the LSS (bO) and the other bits (b7 - bl) become dummy data. (see appendix)
• The control procedures are explained as follows. (refer Fig. a & 9)
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KS5901A
CMOS DIGITAL INTEGRATED CIRCUIT
LDADR
L
Real address (A6-AO)
Label address
-------------~
Real address (A14-A7)
--------------Real address (A15)
I
Memory
DDMP
l
I
---Voice data
Real start address (A15-AO)
CPU
External ROM (x 8)
Fig. 8 Setting the label address
II
l
I
I
Real address (A6·AO)
I
-~~
I
Label address
---------
Real address (A14·A7)
-------------Real address (A15)
I
Memory
I
CPU
LDADR
Voice data
Real start address (A15-AO)
:
External ROM (x8)
Fig. 9 Setting the real start address.
5. BUSY output
BUSY is generated in the follows:
A. During the execution time of the DDMP command and it's successive RE.
BUSY is enabled during from the rising edge of the WE or RE to the rising edge after the 9th falling of 2. (10 T max.)
B. I:)uring the execution time of the other command or RE for status read.
BUSY is enabled during from the rising edge of the WE or RE to the rising edge after the 2nd falling of 2. (3 T max.) See
fig. 10.
C. During power-on transient state.
Power switch ON or OENA command causes the KS5901A to be in power-on transient state, of which duration is fixed by
the external capacitor connected to SR pin. In transient state, normally 40msec, KS5901A is initialized in it's internal state,
and outputs BUSY signal. The BUSY signal due to OENA command become active at the falling edge of WE signal, while
it is normally active at the rising edge. See Fig. 11.
* BUSY signal is available only when CE is low (Fig. 10), therefore you must hold CE to low whenever you wish to check it.
* While Internal BUSY (lBUSY) signal is active, KS5901A can not accept the WE or RE signal.
* If the WE or RE signal is given during IBUSY signal, the internal status of the KS5901A may be uncertain. Besides, the
"command error" of the status flag is set.
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KS5901A
CMOS DIGITAL INTEGRATED CIRCUIT
4>2 _ _ _--'
WEor~------~L--J
Internal
I
BUSY _ _ _ _ _ _ _ _J--t1-~f__-t2----1
• BUSY=CE • Internal BUSY
• T=6.25I'sec typo
Fig. 10. Timing diagrams of -BUSY signal
WE
forOENA
IBUSY
---"""U
-----II
11.....--__
---+"'r::=:
Fig. 11. Timing diagram of power-on transient state
6_ Stop and restart operation
Speech synthesizing process is controlled by 2 kinds of code such as END1, END2.
A. Stop operation by END1 code
END1 code inserted atthe last part olthe speech parameter of a certain phrase controls the KS5901A to haltthe increment
of address counter, and issues EOS signal during 1 frame, remaining all it's internal condition values. At the same time status
flag of DO (End of speech) is set to high level. Figure 12 shows the~timingdiagram of EOS and EOS11ag.
B. Restart operation by END2 code
END2 code inserted at the last part of the speech parameter of a certain phrase generates IBUSY during about 2.5ms
and resets the address counter to the pre-loaded value by LDADER command, restarting synthesis operation from that address.
You can stop synthesis operation by loading STOP command in, it repeat operation without STAT command.
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KS5901A
CMOS DIGITAL INTEGRATED CIRCUIT
end 01 speech
Status flag _ _ _ _ _ _ _ _ _ _ _..1
olEOS
~---lkame~
Fig. 12. Timing diagram of -EOS signal
7. Notes on the CPU control mode.
A. MODE pin must be set to ''I.:' level.
B. BUSY pin issues the output of NAND logic of the internal busy and CE signal, therefore BUSY· is not issued when CE
is high level.
C. RE or WE signal is not detected during internal busy sin gal.
D. The APD signal set to "H" by the ODIS command is not changed by the OENA command (Le., remains "H" level).
Therefore, if APD is used to control the power of external audio circuit, the AENA command must be beforehand with
the START command.
E. In the CPU controlled mode the default values of conditions after reset operation are such as;
APD
: High
Speed code : cf>H (normal speed)
COND1 code: cf>H (48 bit, 20msec, with repetition, 10 stages)
COND2 code: cf>H (impulse, without loss)
F. The internal status of the KS5901A is usually read by RE signal. If you want to dump the speech ROM data, DDMP mode
must be set previously.
G. In the DDMP mode the 100,..sec of time interval is needed at least between each read operation to dump ROM data
H. While the synthesis operation is executed by the KS5901A, such commands as DDMP, START, 2 & 6 nibble one are
forbidden.
I. After the ODIS command, the time interval of about 40msec is needed so as to execute the OENA command.
225
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-------------------
II
CMOS DIGITAL INTEGRATED CIRCUIT
KS5901A
Manual control mode
When MODE pin is set to "t.:', the KS5901A is turned into the manual control mode. In this mode, all the synthesis operation
and conditions can be controlled by the external switches.
ReselS/w
DAD
Synthesis
condition
OT7-DTO
pins
KS5901A
(Speech synthesizer)
External
PROM
64Kbytes
A15-AO
o
Vff
-l0
M-START
S/W
Fig. 13. System configuration the in manual control mode
1. Operation method
A.
B.
C.
D.
E.
F.
G.
H.
MODE pin must be set to "t.:' level.
Reset the KS5901A by means of depressing SR switch.
Through 10 synthesis condition pins, the synthesis conditions of the phrase to be synthesized must be specified.
The synthesis operation is started by means of depressing M-START switch.
The synthesis operation is halted by END 1 code.
The synthesis operation is repeated by END2 code.
When speech is halted by ENOl code you may do the steps of C & D to perform the synthesis operation of the next phrase.
If you want the first phrase, you must operate the steps of B, C, D.
2. RESET operation
When Reset switch connected to SR pin is depressed or the power switch is on, the KS5901A remains the initialized state
during about 40msec due to the charging time of the external capacitor attached to SR pin. M-START input is not received
during that period.
3. START operation
In manual control mode, the chattering-preventing circuit is inserted to deb ounce the chatterings of the M-START pin. So,
M-START input should be continued about min. 20msec (refer to Fig. 14)
1-----1 1 frame
M-START
strobe
M-START
I
UUl'--------~s
-l11J1.J
Internal
I
-I'
r-S- - -
,-----,
M-START_-_ _ _ _ _ _ _
'L------------4S5-i- - - - -
'~
EOS
~ start speech
~stopspeeCh
Fig. 14. Timing diagram of debouncing of the M-START signal
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KS5901A
CMOS DIGITAL INTEGRATED CIRCUIT
4. Synthesis conditions and speed.
In manual control mode, synthesis conditions are determined according to "HIt:' combination of synthesis condition pins
as shown bellow and synthesis speed follows the "HIt:' combination of SCO-SC3 as shown in Tab. 9
Pin No.
Pin Name
Level
29
EXC
L
H
Impulse
Triangular pulse
40
LODF
L
H
With loss effect
Without loss effect
31
NOFS
L
H
Filter stages: 10 stages
8 stages
32
NOBA
L
H
48 bit/frame
96 bit/frame
33
FRL
L
H
20 mseclframe
10 mseclframe
30
REP
L
H
Parameter: repetition
no repetition
Synthesis Condition
Tab. 8 Synthesis conditions in the manual control mode
39
L
L
L
L
L
L
L
L
Pin number
37
36
35
L
L
L
L
H
H
H
H
L
H
L
H
L
H
L
H
L
L
H
H
L
L
H
H
Speed
1.0'
0.7
0.8
0.9
1.0
1.1
1.2
1.3
39
Pin number
37
36
35
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
H
L
H
L
H
L
H
L
L
H
H
L
L
H
H
Speed
1.4
1.5
1.55
1.0
1.0
1.0
1.0
1.0
'Original speed = 1.0
Tab. 9 Speed table in the manual control mode
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KS5901A
CMOS DIGITAL INTEGRATED CIRCUIT
LPC-PARAMETER EXTRACTION FLOW
InVAx-7ao
System
dissatisfy
Data Encoding &
PROM Programming
Parameter
Evaluation
System
dissatisfy
Fig. 15 LPC-parameter extraction flow
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KS5901A
CMOS DIGITAL INTEGRATED CIRCUIT
SYSTEM CONFIGURATION
1. CPU control mode
circuit
50
KS5901A
(Speech synthesizer)
To
CPU
55
Fromexlemal
ROMdaia
(07·00)
57
56
* C1=33pF
• G2=O.47pF
* NC: No Connection
• Crystal oseillator: 640 KHz
Fig. 16 System configuration in the CPU control mode
2. Manual control mode
Voo or GND according to
GND
r
45
ito-
Taau
circu
44
43
synthesIs conditions
~I~
NC
42
41
40
39
CJl
38
36
35
I
34
33
32
46
29_
-48
28
-49
27
-
Manual
R1
25
tI
--'-
26
(KS5901A)
-52
r--------,
'~1l1
"- t "
(Speech synthesizer)
-53
-54
22 -
AI
21r---
55
1-
>--jDf--
30-
-47
NC
:
::C1
31
56
20
r-
From external
57
lP
f-
~~:c;~
56
18r--17f16f-
59
60
2
1
3
4
5
6
7
8
I
To external ROM
address (A1S-AO)
-~
,
9
GNO
9
10
11
12
13
14
15
,
~Ae_s
~" 'h
J
• Rl=100n
• Cl=33pF
• C2=O.47pF
• NC: NaCo nnection
• Crystal oscillator: 640 KHz
FLg 17 System configuration in the manual control mode
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KS5901A
CMOS DIGITAL INTEGRATED CIRCUIT
AUDIO CIRCUIT
INPUTO-
1
VR
(47KIl)
SPEAKER
ABSOLUTE MAXIMUM RATINGS
Symbol
I
VDD
-f------
Unit
I
-----=~4-~ ::~o+ 0:3----\
::::~:~::~
+V---
-- ------------------------ - - - - - - - - - - - - - - - - - - ----------- -
Storage temperature
TST
1----
Specifications
Description
I
V,N
(Ta=25°C)
-40 - +125
°C
- - - - - - - - - - - - - - - - - - - - - -- - f - - - - - - - - - - - - - - - - - - - - - - - - - - -
-Top
Operation temperature
I
-10 - +55
I
°C
Tab_ 10 Absolute maximum ratings
ELECTRICAL CHARACTERISTICS
Symbol
Conditions
Characteristics
- --- ---- tCD
Chip enable setup time
tw
Write enable pulse width
tCH
Chip enable hold time
tws
tWH
Min.
Max.
Typ.
=-1-------------------1---------VDD =5V
200
VDD =5V
500
VDD =5V
200
Data setting time
VDD =5V
500
Data hold time
VDD =5V
300
---------- - -- ---- ----------------------
-1
Unit
nsec
nsec
- - - f----------+--------,
nsec
f---------------+- ----'--------------- ------- -----+--------+---- -------+--------
----'--'----+-----=---------------------f-----------+-~~-
'-::
- - - --------------- - ----
tAcc
nsec
---- -
_~::f~~:-u:-e-\\fid-t-h-~~'----~::~:~ r---~----- 1----=- :_~o-o---I----:-:~~
+ __
..
-----------------------
tRH
nsec
~-- -~------
---------
-
Data hold time
VDD =5V
ROM data access time
VDD =5V
---------------- ----------
-
-
500
nsec
1.5
I'sec
- -
Tab. 11 AC Characteristics
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CMOS DIGITAL INTEGRATED CIRCUIT
KS5901A
90%
Address
10%
tAce
90%
Data
10%
A. External ROM Interface
-tcH-----i
D3-DO
Internal BUSY
(IBUSY)
-------+'
1--------tBSY--+----
B. Write operation
----tcH---
iiE----L
D3-DO
-----+-{I
100/,
tRS
tAH
Internal BUSY _ _ _
(IBUSY)
---tJ1;{
f.1
_ _ _ _ _ _ _
ILl"
tBSy • _ _ _~-
BUSY------------------~
10%
c: Read operation
*) t BSY: 3T or 10T max.
H) BUSY=CE*IBUSY (see page127)
---!---!---tBS
Fig. 18 A.C. Characteristics
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CMOS DIGITAL INTEGRATED CIRCUIT
KS5901A
Symbol
Characteristics
Specific Pin
Condition
Min.
Typ.
Max.
Unit
VDD
Power supply voltage
VDD
3.5
5
6
V
IDDA
Operating current
VDD
VDD =5V
-
1.1
1.5
mA
mA
IDDB
Stand-by current
VDD
VDD =5V
-
0.8
1.0
IDDc
Osc. disable current
VDD
VDD =5V
-
1.0
5.0
pA
fq,
System clock frequency
q,2
VDD =5V
155
160
165
kHz
fosc
Oscillator frequency
CX2
VDD =5V
622
640
659
kHz
V,H
"H" input voltage
Except SR
VDD =5V
VDD-0.8
-
VDD
V
V,L
"t:' input voltage
Except SR
VDD =5V
0
-
0.8
V
VOH
"H" output voltage
Except SR, DAO, CX2
No load
VDD-004
-
VDD
V
V
f-------
~-
VOL
"t:' output voltage
Except SR, DAO, CX2
No load
0
-
004
VOUT
DAO output voltage
DAO
No load
0
-
VDD
V
R'NH
Pull up resistor
CE, WE, RE
190
380
570
kO
R'NL
Pull down resistor
M-START
70
140
210
kO
10
15
20
kO
ROUT
DAO output impedance
DAO
1--
---
IOHA
"H" output current
AO-A15
Vout = V DD-004
004
-
-
mA
IOHB
"H" output current
00-03
Vout= VDD-004
0.2
-
-
mA
IOHc
"H" output current
EOS, BUSY
Vout=V DD/2
1.0
-
-
mA
IOHD
"H" output current
Others
Vout=VDD-0.4
0.1
-
-
mA
lOLA
"t:' output current
AO-A15
Vout=Oo4V
0.2
-
-
mA
IOLB
"t:' output current
00-03
Vout=Oo4V
1.3
-
-
mA
IOLe
"t:' output current
Vout=Oo4V
1.0
-
-
mA
IOLD
"t:' output current
Others
Vout=Oo4V
0.6
-
-
mA
I'H
"H" input current
Except M-START
Vin=VDD
-
1
pA
"t:' input current
Except M CE
WE,RE
Vin=GND
-
-
1
pA
I'L
EOS, BUSY
--
--
Tab. 12 D.C. characteristics
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KS5901A
CMOS DIGITAL INTEGRATED CIRCUIT
APPENDIX
KSS901A is originally designed to have 64 pins. KSS901A is the another version to replace the 64 pin package type, named
KSS901. Therefore, the KSS901A is equal to the KSS901 except that it's S pins are excluded.
KSS901 has 19 address lines which enable it to access upto O.S Mbytes of external PROM/EPROM. It's internal address
counter is also 19 bits wide, and you must load 1 dummy nibble to set the start address when using the KSS901A. (see page 10)
KSS901 has two more signal named PD, TINT. PD represents the status of the internal oscillator which is the same as status
flag of D1. TINT is for test only.
The differences between the two chips are summarized as follows.
Device
KS5901A
Item
Pin count
60
----~-----------~--~-
~---~~--
Package type
- - - --.
KS5901
----------~
64
~.-------
OFP
DIP/OFP
16
19
64 Khytes
O.S Mbytes
II
~-------------t--
No. of address pin
~-----------------------
Addressing range
~~---
--------------
Maximum synthesizing time
DTB 0DTs
DT4
DT3
DT2
DTl
DTo
MODE 0-SA
TINT
M·START
eXl
eX2
Exe
REP 0-NOFS
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18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
---------------~------ --t------------~
4-S min.
40 min.
64
63
-0 A14
--0
A15
~---O
AlB
A17
AlB
62
61
60
WE
KS5901
(Speech synthesizer)
CE
56 ---0 BUSY
EOS
55
-000
54
53
01
02
52
03
51
50
PO
49
~2
233
KS5902XX
CMOS DIGITAL INTEGRATED CIRCUIT
CMOS 1·CHIP SPEECH SYNTHESIZER
The KS5902XX is a CMOS one-chip speech synthesizer which pro·
duces a good quality of human voice using LPC (Linear Predictive
Coding) algorithm. It can be easily used everywhere required to pro·
duce synthesized speech with it's simplified I/O design. The
KS5902XX has three operating modes. The CPU mode makes it easy
to interface with 4/8 bits microprocessor or microcontroller. In the
KEY mode it is operated by some keys attached to. In the auto mode,
it can synthesize speech automatically according to the simple opera·
tion of externally connected switches.
The KS5902XX has 48K bits mask programmable ROM which can
produce speech during about 20 sec. continuously. It can be
separated to 15 phrases. The KS5902XX also has a built-in 9 bits R·2R
D/A converter. (KS5902XX is noted to KS5902 hereinafter, as the 'XX'
is 2 character assigned according to the mask option)
24 DIP
FEATURES
1) General Feature
•
•
•
•
•
•
•
•
•
Speech synthesis method; LPC
Oscillator frequency; 2.56MHz
Sampling frequency; 8KHz
Operating modes; CPU/KEY/AUTO
On-Chip mask ROM; 48 Kbits
Built·in interpolator
Built·in pipelined multiplier
Easy interface with microprocessor or microcontroller.
Low power consumption due to power·down at the stand·
by state
• Built·in 9 bits R·2R D/A converter
• Clocked CMOS
• Single =+- 5V power supply
2) Synthesizer Feature
• Synthesizing speed ; variable from 0.7 - 1.55 times of nor·
mal speech.
• Excitation source
; voiced: impulseltriangular pulse
unvoiced: white noise
• Bit allocation
; 48/96 bits/frame
• Frame length
; 10/20 msec/frame
• Parameter repetition; with repeat/without repeat
• Loss factor
; with consideration/without
consideration
• Digital filter stage ; 8/10 stages
• Repetition of Phrase; END1/END2 code.
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CMOS DIGITAL INTEGRATED CIRCUIT
KS5902XX
BLOCK DIAGRAM
DATA ROM
(24 x 2 K bits)
MODE 1
MODE 2
PS3
-PSO
START
BUSY
ROM
IIF
Block
1/0
IIF
Block
SA
Digital
Filter
Pipelined Multiplier
Parallel Adder
Loss and Delay Stack
DIA
Converter
Multiplexer
DAO
.) LPF: Low Pass Filter
.. ) AMP: Audio Amplifier
Fig. 1 Functional block diagram
PIN CONFIGURATION
VDD
START
MODE1
MODE2
PS3
TROM2
PS1
PSO
APE
KS5902XX
SA
DAO
TINI
TDAC
CX1
TDFO
TDAI
TDFC
CX2
~2
Vss
TEXC
Fig. 2 KS5902 pin assignment
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235
KS5902XX
CMOS DIGITAL INTEGRATED CIRCUIT
PIN DESCRIPTION
Pin No.
Name
110
Description
1
BUSY
0
BUSY Signal Output
2
START
I
Start Signal Input (internally pull·up)
3
PS3
I
4
PS2
I
5
PS1
I
Phrase Select Input
(internally pull·down)
6
PSO
I
7
TINT
110
8
TINI
I
For Test Only (normally ground)
9
TDAC
I
For Test Only (normally ground)
For Test Only
10
CX1
I
Crystal Oscillator Input
11
CX2
0
Crystal Oscillator Output
12
Vss
POWER
13
TEXC
I
For Test Only (normally ground)
14
!li2
0
System Clock Output (160KHz)
15
TDFC
0
For Test Only
16
TDAI
I
For Test Only (normally ground)
17
TDFO
0
For Test Only
18
DAO
0
D/A Converter Output
Ground
19
SR
I
System Reset (low active)
20
APE
0
Audio Power Enable (low active)
21
TROM2
0
For Test Only
I
Mode Select Input 1
I
Mode Select Input 2
-
22
MODE 2
23
MODE 1
24
Voo
POWER
+5 Volt
Tab. 1 KS5902XX pin description
OPERATING PRINCIPLES
Mode Selection
The KS5902XX can be used in three operating modes according to the combinations of MODE 1/MODE 2 pins.
MODE 1
MODE2
Operating Mode
CPU Mode
H"
H
H
L""
KEY Mode
L
H
AUTO Mode
L
L
Not Used
" H"; +5V, L""; OV
Tab. 2 Mode selection
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236
CMOS DIGITAL INTEGRATED CIRCUIT
KS5902XX
CPU Mode
CPU mode makes it easy to interface with microprocessor or microcontroller. It is controlled only by PS3 - PSO
& START, also can be monitored it's status through BUSY and APE.
Voo
1-----ISl1
MODE 1
PS3
CPU
1-------
MODE 2
I
PSO
controller
1 - - - - - 1 START
1------1 BUSY
DAO
,....--..,
1----11--1
I-----?--I APE
KS5902
II
Fig. 3 System configuration in CPU mode
KEY Mode
KEY mode, which is the same as in it's operational principle, is characterized by its manual operation with the
switches connected to it. Also, the input debouncing circu'it is inserted internally to the START pin to prevent
malfunction caused by using the KEYs.
Reset switch
--L-
~
Voo
~~------4
MODE 1
PS3
Manual
MODE 2
DAO
controller
,I
- - - - -
- -
-
---,
I
PSO
1 - - - - - 1 START
1----'-<-1
APE
KS5902
Fig. 4 System configuration in KEY mode
AUTO Model
In this mode, KS5902XX starts its oscillator circuit when anyone of PS3- PSO is connected to the "H" level,
and after 500 msec from that time the KS5902XX fetches phrase selection (PS3 - PSO) data to initiate it s synthesis
operation. KS5902XX repeats to be selected phrase as long as not all the phrase select (PS3 - PSO) lines connected to
the "L" level. If it is selected another phrase during one phrase is activated, it completes current phrase and then
initiates new phrase.
237
c8SAMSUNG
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CMOS DIGITAL INTEGRATED CIRCUIT
KS5902XX
.--____..,R~8~I---t-----M----1
PS3
CPU/Manual
MODE 2
pso
r----------...,
I
I
I
I
DAO 1_---'1--1
controller
I
I
I
L ____ _
1-------.----1 APE
KS5902XX
Fig. 5 System configuration in AUTO mode
Phrase Selection
According to the conbinations of 4 phrase selection lines (PS3 - PSO) total 15 phrases of speech are available.
Before starting the synthesis operation, phrase selection must be specified in 4 bit code. Possible combinations
of phrase selects are as follows, and can be selected at random.
PS3
PS2
PS1
PSO
Selected Phrase
L
L
L
H
#1 Phrase
L
L
H
L
#2 Phrase
L
L
H
H
#3 Phrase
H
H
H
H
#15 Phrase
Tab. 3 Phrase selection by PS3 - PSO
If the KS5902XX receives START signal when all phrase select lines are set to "L" level in CPU, KEY mode, it
stops synthesis operation within 1 frame (10/20 msec). In AUTO mode, if all PS3 - PSO are set to "L" level, it stops
synthesis operation within 0.5 frame.
Start Operation
48 Kbits on-chip mask ROM is composed of 24 bit x 2K words. Initial 15 addresses are index area which contain
synthesis conditions and start address of each phrase, the other addresses are data area which contain speech
parameter (refer fig. 6).
The start operation of KS5902XX is as follows. First, phrase is selected by P.S. Second, START signal is given
by CPU or manual operation. Third, as its first internal cycle, start address and condition data of the specified phrase
in the index area are fed to the address counter and condition latch respectively. Then, after the first internal cycle
the desired speech is synthesized with the speech parameter from data area pOinted by address counter.
c8SAMSUNG
238
CMOS DIGITAL INTEGRATED CIRCUIT
KS5902XX
condition
not used
start address
~/,_ _~A~_ _~v~
I
0001
b23-b21
I
b20--------b11
1
_ _~A~_ _ _~\
b10 _________ bO
I
#2 phrase data
0010
I
I
···
·
I
0011
I
Index
Area
Up to 15
10000
Speech parameter for #1 phrase
··
·
10001
Data
Area
·
Up to 2K
Fig. 6 KS5902XX memory map
Conditions
The 10 bits of b20 - b11 of each index address represent condition data. The conditions, described in tab. 4 are
determined when original speech is analyzed by LPC algorithm. They can affect the quality of synthesized speech
and the total data size, therefore any customer who want to use KS5902XX must determine them through
discussions with SST.
The followings are the details of the conditions, but they are not user accessable once mask programed.
I
b20 : b19 : b18 : b17
b16: b15
: b14 : b13 : b12 : b11
I
I
ll=::.
LOSS
L------------EXC
' - - - - - - - - - - - - - - - - - - NOFS
L----------------FRL
L-_____________________________ SPEED
code
Fig. 7 The descriptions of condition code
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CMOS DIGITAL INTEGRATED CIRCUIT
KS5902XX
Item
Description
Level
Condition
H
Without Repetition
L
With Repetition
REP
Parameter Repetition
NOBA
Number of Bit
Allocation
H
96 Bit/frame
L
48 Bit/frame
LOSS
Loss Factor of
Digital Filter
H
With Consideration
EXC
NOFS
FRL
Speed
Excitation Source
Number of Digital
filter Stage
Frame Length
Speed Rate
L
Without Consideration
H
Triangular Pulse
L
Impulse
H
8 Stages
L
10 Stages
H
10 mseclframe
L
20 mseclframe
LLLH
:
HLLH
HLHL
Others
XO.7
:
X1.5
X1.55
X1.0 (normal speed)
Tab. 4 The descriptions of condition code
Cautions
(1) The internal status of KS5902XX, after power-on transient time or synthesizing operation is under "system reset,"
are denoted by "stand-by status" which means the oscillator is disabled.
(2) Any access is prohibitted during BUSY Signal is "H".
(3) On the power-on reset, it needs 10 msec of transient time, and during this time any access to KS5902XX is
prohibited.
(4) The unused input terminals such as TINI, TDAC, TDAI, TEXC must be connected to "L" level.
(5) The low level of the APE terminal represents that KS5902XX is under synthesis operation. This signal may be
used to control the audio power so that the low level of the APE enables audio power, otherwise disables to
save power consumption.
OPERATING METHOD
CPU Mode
(1) Mode selection; Connect the mode select (MODE 1, MODE 2) terminals to "H" level.
(2) Phrase selection; Select anyone of the 15 phrases by the combinations of 4 phrase select terminals. (PS3- PSO)
(3) Start; If CPU forces START signal under phrase selected, then KS5902 starts the synthesis operation holding
low level of APE. (refer Fig. 8)
(4) Stop; If CPU selects all phrase selects (PS3- PSO) to "L" level and forces START signal, synthesizing operation
is halted within 1 frame (10/20 msec). (refer Fig. 9)
Otherwise, speech synthesis process is stopped automatically by END 1 code located in the last of each phrase
data. In each case KS5902XX outputs the APE terminal to it's "H" level then returns to the stand-by state. If
END 2 code is contained to the specified phrase, the phrase is repeated until the proces is halted. (refer Fig. 10)
(5) Status signal
a. BUSY; BUSY signal is generated during 60 msec typically from falling edge of the START Signal. During this
time any attempt to access is blocked.
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240
CMOS DIGITAL INTEGRATED CIRCUIT
KS5902XX
b.
AJ5'E"; APE signal is generated during the system is under synthesis
terminal represents this status.
r--
PS3-PSO
operatio~.
The low level of the APE
data letch time
----~(~~~)~-------------I
ItoH I
tos
BUSY
tBSY'
'tBSy=tW+tA1
Fig. 8 Timing of start operation In CPU mode
Symbol
Description
Min
Typ
Max
Unit
tos
tOH
tw
tBSY
tA1
tA2
tA3
Data Settling Time
Data Holding Time
Start Signal Width
Busy Signal Duration
APE Signal Delay 1
APE Signal Delay 2
APE Signal Delay 3
500
-
20
-
nsec
nsec
I'sec
msec
msec
msec
msec
300
1.0
-
-
60
60
-
40
Tab. 5 AC characteristics of CPU mode
~Tfr'-i
Internal
signal
Fl
PS3-PSO
__~rl
Il~
____--«
anULU
__~
)>------------tA2
BUSY
") Tlr, Frame length (10 to 20 msec according to condition)
Fig. 9 Timing of forced stop in CPU mode
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241
CMOS DIGITAL INTEGRATED CIRCUIT
KS5902XX
~Tfr~
Internal
signal
Fl
-Fl__. . . .n
n . . __. . n
. . . __. . nL...
. __
Internal
signal END 2 - - - - - - - -....
_____.....1
_
End of speech
IL--_____________
tA3
If - - - - - - - - ' - " ' - -
--i
~
Restart
Fig. 10 Repetition of speech by END 2 code
KEY Mode
(1) Mode selection; Connect MODE 1 terminal to "H" level, and MODE 2 terminal to "L" level.
(2) Phrase selection; Select anyone of the 15 phrases by combinations of 4 phrase select terminals (PS3 - PSO).
(3) Start; Synthesizing operation is started by pressing start key which is externally connected to START terminal.
Built·in debouncing circuit requires 40 msec or more to prevent the chatterings of START terminal.
(4) Stop; Synthesizing operation car be stopped by one of the three case.
a. Press SR switch connected to SR terminal.
b. Select all phrase selects to "L" level, Then press start switch
c. Otherwise speech synthesis operation is stopped automatically by END 1 code located on the last of each
phrase speech data.
f--PS3-PSO
data fetch time
-------(~rrr-«-----:..I~»)~
I
I toH
tos
_ __
I
~--------------~I~II
I
tos
itolyl
BUSY
* tgSY
= 2.5msec + tAl
Fig. 11 Timingof start operation in KEY mode
Symbol
tos
toH
tos
tolY
tsSY
tAl
Description
Min
Typ
Max
Unit
Data Settling Time
Data Hold Time
Input Debounce Time
Data Fetch Delay Time
Busy Signal Duration
APE Signal Delay
500
300
40
-
-
-
20
42.5
40
nsec
nsec
msec
msec
msec
msec
-
-
Tab. 6 AC characteristics of Key mode
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CMOS DIGITAL INTEGRATED CIRCUIT
KS5902XX
AUTO Mode
(1) Mode selection; Select MODE 1 terminal to "L" and MODE 2 terminal to "H" level.
(2) Phrase select; Select anyone of the 15 phrases by combinations of 4 phrase select terminals. (PS3 - PSO)
(3) Start; If anyone of the phrase select is set to "H" level, then internal oscillator circuit starts to oscillate and
after 500 msec KS5902XX fetches the phrase select data to begin synthesis operation. Therefore the phrase select
terminals must be settled within 500 msec. Synthesis operation is continued unless all phrase selects are set
to "L" level. The interval repeated phrases is 560 msec. If the levels of. phrase selects are changed under synthesis
operation, the new selected phrase is synthesized after the current speech is terminated.
(4) Stop; If all the phrase select lines are set to "L" level, current speech is stopped within 1 fame (10/20 msec).
r---
data fetch time
IIIIII I
PS3-PSO
tos
~ l__t~:~'--------I~-
BUSY
*tBSY = 2.5msec + tA1
Fig. 12 Timing of start operation in AUTO mode
DeSCription
Min
Typ
Max
Unit
Data Settling Time
Busy Signal Duration
APE Signal Delay 1
APE Signal Delay 2
-
500
42.5
40
40
-
msec
msec
msec
msec
Symbol
tos
tBSY
tAl
tA2
-
Tab. 7 AC characteristics of AUTO mode
Internal
signal Ft'
I
I
I
n IL...._____________________________
Internal
signal ENO,----l
I
--i
Restart~
End of speech
'Fl: The frequency of Internal signal F' Is 20 msec. (Initial frame length)
Fig. 13 Repetition of speech in AUTO mode
Internal
Signal Ft
_----In. . ._----'n. . _-'
PS3- PSO
all""L""
III
~
stop speech
Fig. 14 Stop operation In AUTO mode
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243
KS5902XX
CMOS DIGITAL INTEGRATED CIRCUIT
SYSTEM CONFIGURATION
+5V
c
(1) BUSY
mAT
(2)
Voo (24)
r--
MODE 1 (23)
MODE 2 (22)
r---
r-J~
(3) PS3
CPU
SF! (19)
(4) PS2
-
(5) PSI
(6) PSO
KS5902XX
12 (14) -NC
(2O)AJ5E
DAO (18)
NC- (7) TINT
TROM 2 (21)
TDFO (17)
(6)TINI
.--+-
TDAI(16)
=;:C2
t- NC
t- NC
r--
!10)CX1
TDFC(15) t-NC
(11) CX2
TEXC (13)
TDAC(9) t - - -
To audio circuli
r----
(12) Vss
X'ial
~O~
:,:: =r
C1
J
(a) CPU Mode
+5V
+5V
§
(3) PS3
Voo (24)
(4) PS2
MODE 1 (23)
(5) PSI
MODE 2(22)
(6) PSO
(2)START
Resel swllch
NC
NC
(1) BUSY
KS5902XX
(7) TINT
APE (20)
(8)TINI
DAO(18)
To audio
circuli
TROM 2 (21)
NC
(10)CX1
TDFO (17)
TDAI (16)
NC
(11)CX2
TDFC (15)
NC
(12) Vss
TEXC(13)
(9)TDAC
Cl
12 (14)
Rl
(b) KEY Mode
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244
CMOS DIGITAL INTEGRATED CIRCUIT
KS5902XX
+5V
r-----------,
NC
I
I NC
:
I
(1) BUSY
Voo (24)
(2)S'TAIfT
MODE 1 (23)
I
I
I
(3) PS3
MODE 2 (22)
I
I
(4) PS2
I
I
I
(5) PSI
I
I
(6) PSO
im(19)
I
I
~2
KS5902XX
I
I
IL _ _ _ _ _ _ _ _ _ _ JI
CPU/manual controller
(14)
APE (20)
DAO (18) I----f---+--
NC
TAOM 2 (21)
TDFO (17)
(7) TINT
(8) TINI
(9) TDAC
TDAI (16)
(10)CXl
TDFC (15)
(11) CX2
TEXC (13)
To audio circuit
AI
NC
II
(12) Vss
Cl
·Al =100 0
·C1 =47 pF ·C2=0.01 ~F
• NC: No Connection
·Crystal oscillator = 2.56 MHz
(C) AUTO Mode
Fig. 15 Application circuit examples
APPLICATION CIRCUIT (KEY MODE)
Vee (6V)
lN4148
,-----------i
A643G
KS5902XX
u.
1000
u.
u.
l~ l~ l~
~AESET
1
245
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-------------
-------_.
KS5902XX
CMOS DIGITAL INTEGRATED CIRCUIT
ELECTRICAL CHARACTERISTICS
(1) Absolute maximum ratings
Description
Power Supply
Unit
Symbol
Specifications
Voo
-0.3-7.0
V
Input Voltage
V,N
- 0.3 -Voo+ 0.3
V
Operation Temperature
Topr
-10-55
°C
Storage Temperature
Ts.g
- 55 -120
°C
(2) D.C. characteristics
Characteristics
(Voo = 5V, Ta= 25°C)
Symbol
Specific Pin
Condition
Min
Typ
Max
Unit
mA
Operating Current
looA
Voo
-
1.0
1.5
Stand·by Current
looB
Voo
-
1.0
5.0
J.tA
System Clock Frequency
Fa
2
155
160
165
KHz
Oscillator Frequency
Fosc
CX2
2.48
2.56
2.63
MHz
V
"H" Input Voltage
V,H
Except SR
Voo=5V
Voo - 0.8
-
Voo
"L" Input Voltage
V,L
Except SR
Voo =5V
0
0.8
V
"H" Output Voltage
VOH
Except DAO
No Load
Voo-0.4
Voo
V
"L" Output Voltage
VOL
Except DAO
No Load
0
0.4
V
DAO Output Voltage
VOUT
DAO
No Load
0
-
Pull Up Resistor
R'NH
START, MODE 1/2
-
800
Pull Down Resistor
R'NL
PS3 -PSO
-
DAO Output Impedance
ROUT
DAO
10
"H" Output Current
10H
BUSY, APE,
2
Va". = Voo - 0.4
-0.3
"L" Output Current
10L
BUSY, APE,
2
Va". = O.4V
0.8
c8SAMSUNG
Voo
V
-
KO
300
-
KO
15
20
KO
-
-
mA
mA
246
CMOS DIGITAL INTEGRATED CIRCUIT
KS5902XX
SPEECH PARAMETER ENCODING
KS5902XX is a speech synthesizer based on LPC (Linear Predictive Coding) algorithm. LPC is a coding techni·
que in which speech signal is converted to frequency domain and, extracting it's characteristic parameters. This
method can save memory size over 20 times compared with time domain analysis method, therefore it can store
more speech data on limitted memory area. KS5902XX performs speech synthesizing operation with LPC coded
speech parameter.
To synthesize speech using KS5902XX, at first it requires the analysis process of recorded voice signal, LPC
analysis extracts 12 parameters for each defined interval (frame). The extracted parameters, which represent the
characteristics of each frame, have speCial distribution characteristics. The extracted data can be shrinked more
compactly in the quantization process to store them on memory using this distribution characteristics. Several
factors are considered to encode them such as frame length, bit allocation, repetition of parameters, etc. Such
factors can have influence on the amount of memory size, and on the quality of synthesized speech by causing
distortions in extracted parameters. There is a trade-off between memory size and quality of synthesized speech.
To synthesize speech using KS5902XX, as described above, speech parameters must be acquired by analyzing
original speech and encoding them. Then SST produces a piece of mask which contains speech parameters of
the acquired data. And KS5902XX is fabricated with this new mask plus remaining masks through a series of
processes. Thus the customized KS5902XX which contains the desired speech data is aquired. SST have set up
the KS5902XX development system for such processes to prepare speech parameters.
Any customer who wants to build speech synthesizing system using KS5902XX must determine the conditions
for speech analysis through discussions on the memory size and the quality of the synthesized speech. SST
then prepare the speech data using the development system. The speech data are evaluated on the KS5902XX
evaluation Kit, and if they are not satisfied to the customer's demand the analysis-evaluation procedure is repeated
until they. meet the customer's need. The flow of speech parameter encoding is shown below.
Request
~
LPC Analysis
from customer
c---
Data Encoding
I--
Evaluation
Yes
I
J
No
Producing
Customized
Test
-
Fabrication
mask
KS5902
-
Fig. 16 Speech parameter coding flow
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KS5911
CMOS DIGITAL INTEGRATED CIRCUIT
VOICE RECORDING & REPRODUCING LSI
KS5911 is a CMOS LSI for voice (sound) recording & reproducing LSI, using the ADM (Adaptive Delta Modulation) algorithm.
KS5911 cn be used two kinds of modes, that is, manual mode
and auto mode with the way of recording/reproducing.
It can be used 64K or 256K DRAM, until maximum 4pcs.
In the manual mode, using 4 input pin, the sound recording/
reproducing of maximum 16 phrases can be performed and
start/stop input is activated by external key.
In the auto mode, input voice signal is automatically recorded
and recording stop with silence detection and recorded voice signal is reproduced automatically.
KS5911 can be used 4 kinds of bits rate (8K, 11 K, 16K, 32K BPS).
48 FQP
FEATURES
o
o
o
o
o
o
o
o
o
o
o
o
o
o
Voice recording & reproducing LSI using ADM algorithm_
Auto-talking back function with auto mode.
64K DRAM or 256K DRAM can be used selectively 1 pcs-4 pcs.
Capable of recording & reproducing of max. 16 phrases_
Selective 4 kinds of bits rate (8K, 11 K, 16K, 32K bps).
Built-in in DRAM refresh circuit.
Built-In microphone amplifier.
Built-in 10 bits D/A converter.
Buill-in voltage follower for D/A converter buffering.
Buill-in RC oscillator (640 KHz-1 MHz).
+ 5V single power.
Clocked CMOS for low power consumption.
48 pin QFP package.
In case of long time recording/reproducing without phrase selection,
using EXT/RIPPLE pin, memory extension is possible.
c8SAMSUNG
248
CMOS DIGITAL INTEGRATED CIRCUIT
KS5911
FUNCTIONAL BLOCK DIAGRAM
ADI
MICaUT
C2
C1
A
~
-CAS1 -CAS4
-WE
256K
M1
M2
DIN
DOUT
-
VSSA
VSSB
~
Voo
Y
RATOR
I
AO·A8
-
L
~
-RAS
DAO
II
ADM
ANAL YSIS/SYNTH ESIS
START
STOP
--
SYSTEM
CONTROL
DRAM
-ACL
BPSO BPS1
INTERFACE
PHRO - PHR
RIPPLE
I
MODE SELECTION
SYSTEM
-.
CLOCK
GENERATION
EXT
AUTO
ROUT
I
I I !
REC
-
TEST
- CLOCK
Figure 1. KS5911 Functional Block Diagram
c8SAMSUNG
249
CMOS DIGITAL INTEGRATED CIRCUIT
KS5911
PIN DESCRIPTION
Pin Name
Pin No.
-ACL
1
1/0
Pull
UplDown
I
UP
REC
2
I
DOWN
M1
3
I
-
M2
4
I
-
Function
Reset Input Pin. Use CAP. (11-'F)
At manual mode.
H; Recording mode
Pin
No.
7
L; Reproducing mode.
Programming terminal for the number of outer DRAMs.
M1
M2
Pin
M1
No.
M2
1pcs
L
L
3pcs
H
L
2pcs
L
H
4pcs
H
H
N.C.
PHRO
5
I
DOWN
PHR1
6
I
DOWN
PHR2
8
I
DOWN
PHR3
9
I
DOWN
BPSO
10
I
DOWN
BPS1
11
I
DOWN
Programming terminal for the phrase selection.
Phrase No.
PHRO
PHR1
PHR2
PHR3
0
1
L
L
L
L
L
L
L
H
15
H
H
..H
H
Programming terminal for bit rate selection.
Bit Rate
BPSO BPS1
Bit Rate
BPSO BPS1
8KBits/sec
L
L
16KBits/sec
H
L
11 KBits/sec
L
H
32KBits/sec
H
H
D'N
12
I
UP
Data input pin. Connect this pin to data output
pins of DRAMs.
RIPPLE
13
0
-
At EXT = H, when maximum address overflow occurs,
this pin generates a ripple clock.
-CAS1
-CAS2
-CAS3
-CAS4
14
15
16
17
0
0
0
0
-
-
Column address strobe output.
Used from CAS1 to that required corresponding
to the number of external DRAMs.
(to be continued)
c8SAMSUNG
250
KS5911
CMOS DIGITAL INTEGRATED CIRCUIT
PIN DESCRIPTION
(Continued)
Pull
Up/Down
Function
Pin Name
Pin No.
I/O
-CLOCK
18
0
-
Only test.
DouT
19
0
-
Data output pin. Connect this to data input pins
of external DRAMs.
A8
A7
A6
A5
0
0
0
0
0
0
0
0
0
-
A3
A2
A1
AO
20
21
22
23
24
25
26
27
28
Voo
29
Power
A4
-
-
Address output pin to DRAMs
A8 is not needed when 64K bit DRAMs are used.
-
+ 5V (Typ.)
ADI
30
I
-
Voice (or Signal) input pin.
The center of input signal level must be 1/2 Voo
DAO
31
0
-
Synthesized voice output pin.
The center of output level is 1/2 Voo
VSSB
32
Power
-
System ground.
MICouT
33
0
-
Output pin of built-in AMP (1).
The center of output level is 1/2 Voo
C2
34
I
-
Input pin of built-in AMP (2).
C1
35
0
-
Output pin of built-in AM P (2).
The center of output level is 1/2 Voo
MICIN
36
I
-
Input pin of built-in AMP (1).
Connect to microphone through capacitor.
VREF
37
I/O
-
For connecting capacitor which stabilized the
reference voltage for the built-in AMP.
VssA 38
Power
-
Ground
OV.
STOP
39
I
DOWN
Manual stop input pin.
TEST
40
I
DOWN
Only test.
START
41
I
DOWN
EXT
42
I
-
--
Manual start input pin.
=
=
At EXT H: When address overflow occurs, RI PPLE
pin generates a ripple clock.
At EXT L: KS5911 is manual mode.
(to be continued)
=8SAMSUNG·
251
CMOS DIGITAL INTEGRATED CIRCUIT
KS5911
PIN DESCRIPTION
(Continued)
Pin No.
I/O
Pull
Up/Down
-RAS
45
0
-
Low address strobe output.
Connect this to-RAS pins of outer DRAMs.
256K
46
I
-
Input for the selection of the types of external
DRAMs.
256K = H: 256K DRAM type. 256K = L: 64K DRAM type.
ROUT
47
0
-
R'N
48
I
-
Pin Name
Function
Pins for RC oscillator
Attach variable resistor between ROUT and R'N
Generating clock frequency: 640KHz·1MHz.
'L' =V SSB
'H'=Voo
Table 1. KS5911 pin description
MIC'N
C1
C2 MICoUT
36
35
34
33
VSSB
32
DAO
ADI
VOD
AO
A1
A2
A3
31
30
29
28
27
26
25
VREF
37
24
A4
VSSA
38
23
A5
STOP
39
22
A6
TEST
40
21
A7
START
41
20
A8
EXT
42
19
DOUT
43
18
-CLOCK
-WE
44
17
-CAS4
-RAS
45
16
-CAS3
256K -
46
15
-CAS2
ROUT - -
47
14
-CAS1
13
RIPPLE
AUTO
R'N
~-.
KS5911
0
48
10
-ACL
M1
M2
PHRO
PHR1
PHR2
11
PHR3 BPSO BPS1
12
DIN
Figure 2. KS5911 Pin configuration (48 QFP, Top view)
c8SAMSUNG
252
KS5911
CMOS DIGITAL INTEGRATED CIRCUIT
FUNCTIONAL DESCRIPTION
Manual Mode (EXT
='L', TEST ='L')
Phrase Selection
Using 4 input terminals of PHRO - PHR3, the sound recording/reproducing of maximum 16 phrases can be
performed.
Before starting the sound recording/reproducing, phrases must be specified and can be selected at random.
Pin
PHRO
PHR1
PHR2
PHR3
No.O
L
L
L
·L
No.1
L
L
L
H
No. 14
H
H
H
L
No. 15
H
H
H
H
Phrase No.
II
Table 2. Selection of phrases
Selection of bit rate
KS5911 can use 4 kinds of bits rate as shown in Table 4. (8K, 11K, 16K, 32K) which are selected by BPSO and
BPS1 since a bit rate is independently specified for sound recording/reproducing, it is possible to change reproduced
voice slow/fast to speak.
Pin
BPSO
BPS1
Bit Rate
Using time
Using time
(64K)
(256K)
8KBPS
L
L
about 8 sec.
about 32 sec.
11KBPS
L
H
about 6 sec.
about 24 sec.
16KBPS
H
L
about 4 sec.
about 16 sec.
32KBPS
H
H
about 2 sec.
abo'ut 8 sec.
"In case of fx = 640 KHz.
"Initial 1Kbits are used index area.
Table 3. Selection of bit rate
c8SAMSUNG
253
KS5911
CMOS DIGITAL INTEGRATED CIRCUIT
Recording procedure
(1) Before recording, KS5911 must be reset by-ACL pin_
(2) REC pin must be H state_
(3) Select bit-rate, phrase number.
(4) When START pin is activated, the contents of address counter are added successively and recording is started_
(5) Then STOP pin is activated or the contents of address counter are reached the maximum address of memory,
the recording is stopped.
(6) Repeat from 2), then another phrases are recorded.
(7) Changes of bit-rate and phrase number during recording are ignored.
Reproducing procedure
(1) REC pin must be set to L.
(2) Select bit-rate and phrase number.
(3) If START pin is activated, the start and stop address are readed from index area of memory and reproduced
from start address to stop address.
(4) If current address is equal to stop address, reproducing is stopped.
(5) Repeat from 2), then another phrases are reproduced.
(6) Changes of bit-rate and phrase number during reproducing are ignored.
Auto mode
- If AUTO pin is set to "H", KS5911 is auto-tolking back mode.
- Auto mode is independent of REC pin state.
- In the auto mode, KS5911 is automatically recording mode and internal system reset signal is created. Therefore, recording is started.
- In the auto mode, sound information is accumulated to DRAM like manual operation mode.
- When sound stops, namely, silence is detected internally, KS5911 stops automatically recording and reproduces
sound stored at the memory.
- If ADI input signal swings within 2.5 ± 0.3125V about 0.5sec, KS5911 set to the reproducing mode automatically.
Reset function
The status during reset operation
Low level to - ACL pin causes the reset to KS5911 and almost internal operations such as recording/reproducing stop, but the refresh counter doesn't stop so that the data stored in DRAM are protected.
The status after reset operation
- Internal address counter is preset to 00400 (H).
- In the recording mode, if recorded address reaches to the maximum address, start input is not given in order
to protect DRAM data. The function of RAM-data protection is released by reset so that KS5911 can record newly.
Precautions
-
During recording/reproducing operation, pins of M1, M2 and 256K must not be changed.
System reset doesn't stop the oscillation for the reason of keeping the data in DRAMs.
The conditions of phrase, bit-rate and recording/reproducing mode settled before start signal is inputed to KS5911
and in the middle of recording/reproducing, conditions of phrase or bit rate must not be changed.
- During recording, start input is not accepted.
- Resistor for RC oscillator must be attached closet to R'N, ROUT pin.
- Output clock (fx) from ROUT is 640 KHz.
If resistor value is small, the frequency is high and resistor value is large the frequency is low.
- If frequency (fx) is high, output voice quality is good because of high bitrate, but frequency is low, output voice
quality is bad because of low bitrate.
- At recording mode, built-in mute circuit operates in order to protect bowling effect.
c8SAMSUNG
254
KS5911
CMOS DIGITAL INTEGRATED CIRCUIT
APPLICATION CIRCUIT
Manual Operation Mode Auto Mode
Auto Mode
9: +5V
~: ov
II
1.F ~;:
MIC
~~I
I
35 34
33
32
0 '"
0
::>
0
0-
m
-W±i
I
36
z
6
'iii
0.1.F
+
I I
0
'iii
"'
>"'
31
0
..:
0
AU
A1
A2
A3
I
I
30
29 28
27 26 25
15
"
>"
:;: ..:
'" ..:
'"
..:
0
..:
I
I
-f
t-II-
37 VREF
A4 24
~
38 VSSA
A5 23
0<>""0- 39
~
STOP
A6 22
40 TEST
A721
0<>"""0- 41
f---
A8 20
START
42 EXT
DOUT 19
KS5911
-CLOCK 18 -NC
NC- 43 AUTO
-
44 -WE
- CAS4 17
45 - RAS
-CAS3 16
- CAS2 15
0- 46 256K
-CAS1 14
47 ROUT
~[ 48
~
-
RIPPLE 13 -NC
R'N
...J
0
..:
I
1
0
0
w
a:
2
a:
i
'"
;:;;
II:
J:
11.
11.
3
4
5
6
'"
J:
7
II:
J:
11.
II:
J:
11.
'"
0
CI)
11.
III
C
8
9
10 11
12
11.
III
Ui
i~?1 j j ??? y?? ~ ?????n????r
7
Z
A4
A5
A6
VSS
AO
A1
A2
A3
A4
A5
A6
Vss
AO
A1
A2
A3
A4
A5
A6
Vss
AO
A1
A2
A3
-A4
-A5
A6
V.s
'""'
0>
"
"''"
0>
"
'"g:
"
"''"
0>
"
Vee
A7
A8
DIN
DOUT
RAS
- WE
CAS
Vee
A7
A8
DIN
DOUT
RAS
f-f---
-
~
CAS Vee
A7 A8 DIN
DOUT
RAS
WE
CAS
Vee
A7 fA8 f-.
DIN
DOUT
RAS
WE
CAS [
I
6
'At this diagram, if AUTO (N.C.) set to H, KS5911 is auto-mode.
Figure 3. Application circuit in the manual operation mode
c8SAMSUNG
255
KS5911
CMOS DIGITAL INTEGRATED CIRCUIT
Auto Mode
9: +5V
v:
ov
50KO
50KO
50KI)
1"F';:=
~-
+
MIC
1"F
1"F
OIP-=H~ r~
I I
36
z
(5
U
~
0.1"F
H~-
35
I
34
33
32
0'"
....
::>
iil
00 >'"
I
I
31
30
29
28
0
is
..:
c
c
0
..:
Q
>
..:
27
I
26
r
I
25
:;: ..:'" ..:..,
i
~
I
L
37 VREF
A4 24
38 VSSA
A5 23 1 - - -
NC- 39 STOP
A6 22
NC- 40 TEST
A7 21
NC- 41 START
A8 2 0 1 - - -
42 EXT
0-,----
DOUT 19
KS5911
43 AUTO
i
I
AO
Vee
' - A1
A7
r---'
~
44 -WE
A3
'"'"
DIN
I--
0>
-CAS4 17 I-NC
, - - 45 -RAS
A8 f - -
' - - A2
-CLOCK 18 I-NC
r---
~
A4
"
DOUT
I--
-CAS3 16 I-NC
0-
46 256K
-CAS2 15 f-NC
~[
47 ROUT
-CAS1 14
r---
RIPPLE 13 I- NC
48 R'N
0..: 0UJ
..J
I
a:
i
'"
::;;
1
2
3
4
~z i,z
0
a:
Q.
Q.
5
6
a:
:z:
:z:
0
Q.
Q.
Q.
Q.
III
III
t5
8
9
10
11
12
!J)
(ij
,
A5
RAS I--
A6
WE
VSS
-
z
0z 0 0 0 0 J J I
CAS
Ii
~ Iii I
zzz~
._.
L·
7
..,
'" a:
II:
:z: :z:
~
!
._-----
~
"The type and number of memory are used 64K DRAM or 256K DRAM and used maximum 4pcs.
Figure 4. Application circuit in the auto mode
c8SAMSUNG
256
KS5911
CMOS DIGITAL INTEGRATED CIRCUIT
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Symbol
Specifications
Unit
Power Supply
Voo
-0.3-6.0
V
Input Voltage
V,N
-0.3-Voo +0.3
V
Storage Temperature
TST
-30 -90
C
Description
Table 4. Absolute maximum ratings
Recommended Operation Conditions
Description
Symbol
Specifications
Unit
Power Supply
Voo
4.5-5.5
V
Input Voltage
V,N
o -Voo
V
Operating Temperature
Top
Oscillation Frequency
Fx (Ix)
-10 - 50
II
°C
640 -1000
KHz
Table 5. Recommended operation conditions
DC Characteristics (Voo= 5V, Ta=25°C, fx=640 KHz)
Description
Symbol
Specific Pin
Condition
'H' Input Current
I'H
- REC, STOP, START
AUTO, TEST, BPSO
BPS1, PHRO-PHR3
V,N = Voo
'L' Input Current 1
Min
Typ
Max
Unit
12
18
p.A
I'L1
DIN
V,N = VSSB
90
150
p.A
'L' Input Current 2
1'L2
-ACL
V,N = VSSB
800
1100
p.A
'H' Input Voltage 1
V,H1
EXT, D,N
'H' Input Voltage 2
V,H2
All input pin
except EXT, D,N
'L' Input Voltage 1
V ,L1
-
3
V
4.3
V
---~
'L' Input Voltage 2
V,L2
D,~
-
0.5
V
All input pin
except EXT, D,N
-
0.3
V
EXT,
---------~-
'H' Output Current
10H
Output pin
VOUT = 2.4V
1.5
3.3
mA
'L' Output Current
10L
Output pin
VOUT = 0.8V
1.0
2.2
mA
VSSA
oWithout the
external loads at
all out pins.
oNo signal is
input
Stand·by Current
Iss
1
1.5
mA
Table 6. DC characteristics
c8SAMSUNG
257
KS5911
CMOS DIGITAL INTEGRATED CIRCUIT
AC CHARACTERISTIC
In the Case of Recording
Description
Symbol
Min
Low Address Set-up Time
TAsR
150
-
-
Low Address Holding Time
TRAH
-
-
-
Typ
Max
Unit
ns
- RAS Pulse Width
TRAs
-
4.58
Column Address Set-up Time
TAsc
150
Column Address Holding Time
TCAH
500
-
- CAS Pulse Width
TcAs
-
3.05
-
P.s
- WE Pulse Width
TwEP
-
3.05
-
P.s
Data Output Set-up Time
Tows
500
-
-
Data Output Holding Time
TowH
500
-
-
P.s
ns
-
ns
Table 7. AC characteristics (1)
---tRAS
RAS
I(
teAs--
CAS1-CAS4
I
I
AD-A8
WE
-·tASR- -tRAHROW ADDRESS
\I
J\
--{
-tASC- f--tCAH-
V
J\
COLUMN ADDRESS
___________-'X
1\
t WEP - - - - )_ _ _ _ _ _ __
_ _ _ _ _ _ _ _"""" r t o w s - : j
DOUT
\V
- - t o w H - - - I l _ _ _ __
r-I
VALID
~
Figure 8. AC Timming Diagrams (1)
c8SAMSUNG
258
KS5911
CMOS DIGITAL INTEGRATED CIRCUIT
In the Case of Reproducing
Description
Symbol
Min
Typ
Max
Data Input Set-up Time
tocs
500
-
-
Data Input Holding Time
tOCH
0
-
-
Unit
ns
RAS
II
CAS1-CAS4 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _""\,
AO-AB
______________________________
~~~
::_:I~D~~~_~--~~-t-OC-H----
_______
Figure 7, AC Timing Diagrams (2)
Analog Characteristics
Description
Input Voltage Range
Voltage Gain
Output Resistance
Symbol
Min
Condition
V'N'
MIC'N
AMP (1)+AMP (2)
V'N2
MIC'N
AMP (1)
125
V'N3
C2
AMP (2)
250
VG,
MIC'N"MICoUT
VG2
MIC'N"C1
Typ
Max
Specific Pin
Unit
12.5
mV p.p
46
V,N=6mV p•p
fin = 100 Hz -10 KHz
26
VG3
C2-MICouT
20
RouT1
C1
1.2
ROUT2
MICouT
-
Input Voltage Range
V'N.
ADI
-
Output Resistance
ROUT3
DAO
-
db
Kfl
1.2
3.75
1.25
0.9
V
Kfl
Table 9. Analog characteristics
c8SAMSUNG
259
KS5912XX
CMOS DIGITAL INTEGRATED CIRCUIT
CMOS 1·CHIP SPEECH SYNTHESIZER
16 DIP
KS5912XX is a one chip voice/sound reproducing LSI using CVSD
(Continuously Variable Slope Delta modulation) algorithm.
This LSI is capable of reproducing voice/sound up to 8 seconds,
seperating 4 phrases.
KS5912XX consists of voice reproducing logic, 64 Kbits ROM to
contain encoding data, 10 bits D/A converter, control logic, RC oscillator
for cost effect.
This LSI can be used for various applications required for voice and
sound reproducing (especially, TOY industry), having simple control
method and external circuit.
Voice and sound encoding data that have been edited by ADM tooling
system are programmed into internal ROM by changing one mask during
the device fabrication.
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
Single chip voice & sound generation LSI by ADM method
On·chip 64 Kbits mask ROM
Simple manual control
Repetition function: 3 times/8 times/infinite
Selectable phrase: 4 phrase
Maximum generation time: 8 sec (8 KHz sampling)
Variable bit rate (make option): 32kbps/16kbps/11kbps/8kbpsss
660 KHz RC Oscillation
On·chip 10 bits D/A converter
Single 5V power supply
Low power consumption by CMOS logic
16 DIP type
ELECTRICAL CHARACTERISTICS
1) Absolute Rating
Description
Symbol
Specifications
Unit
Power Supply
Input -Voltage
Storage Temperature
Operation Temperature
Voo
-0.3-6.0
-0.3- Voo + 0.3
-55-120
-10-55
V
V
c8SAMSUNG
Y,N
TST
Top
260
KS5912XX
CMOS DIGITAL INTEGRATED CIRCUIT
2) DC Characteristics
Characteristics
Symbol
Test Conditions
Power Supply Voltage
Voo
Operation Current
looA
Voo=5V
Stand-by Current
loDe
Oscillation Frequency
Typ
Min
Unit
Max
3.5
5
5.5
V
-
600
900
p.A
Voo=5V
100
150
p.A
fosc
Voo=5V
R=240KO
660
DAO Output Voltage
VOUT
NO load
Pull Up Resistor
R'NH
MODE1,2
300
KO
Pull Down Resistor
PSO, 1
START
300
KO
R'NL
-ACL
17
KO
kHz
-
1.25
3.75
V
II
INTERNAL BLOCK DIAGRAM
MODE 1
f---
LSB DECODER
-
MODE
r
f---
~
32K BITS
r--PHR
1
ASE
~
-
PS 1 -
'7"
I
"
iii
0
16
?
1
'1
5
PSO
()
~
SEL
-
...
32K EITS
MODE2
r---
r-
,------r---
I
1
14
ADDRESS
COUNTER
12
SEL
,---
12
'--'-
-
1
ADM
r--f--OSCOUT
f--
TIMM
ING
rI
'---
START
_._-
2
I
CONDITION
LATCH
--
2
10
1-
CONTROLLER
3_
DAO
261
c8SAMSUNG
--------- ______
~
______ -_0_.__--- __ . __
~
____
~~
__
KS5912XX
CMOS DIGITAL INTEGRATED CIRCUIT
FUNCTIONAL DESCRIPTION
PHRASE SELECTION
Before starting the sound reproducing, phrase must be specified by selection of PSO and PS1
PS1
PSO
Selected Phrase
L
L
#1 Phrase
L
H
#2 Phrase
H
L
#3 Phrase
H
H
#4 Phrase
Operating Mode Selection
KS5912XX can be performed 3 kinds of mode by using 2 input terminals of mode 1 & mode 2
H: +5V
L:
OV
Mode 2
Mode 1
H
H
Normal Mode
L
H
REP3 Mode (3 times repetition mode)
H
L
REP8 Mode (8 times repetition mode)
L
L
Not Used
Operating Mode
Normal Mode
(1)
(2)
(3)
(4)
Normal mode shall be specified by using 2 input terminals of mode 1 and mode 2 (M1:H, M2:H)
The phrase shall be selected by PSO and PS1 switch.
Sound reproduces by start input ("H" state).
When the ACL terminal becomes "L" level under reproducing, the internal state of KS5912 is initialized and
is become stand-by mode.
c8SAMSUNG
262,
KS5912XX
PHRASE
SELECTION
CMOS DIGITAL INTEGRATED CIRCUIT
~~~-----------15.6ms
START
INTERNAL
DISABLE
OSCILLATION _ _ _oJ
DISABLE
DAO
2.5V
Figure 1. Timming Diagram at Normal Mode
REP3/REP8 Mode
1)
2)
3)
4)
5)
REP3/REP8 model shall be specified by using 2 input terminal of mode 1 and mode 2 (M1:H, M2:LlM1:L, M2:H).
The phrase shall be selected by PSO and PS1 switch.
The sound of selected phrase repeats 3 times or 8 times by mode selection.
Change of phrase or start input is ignored under reproducing.
Reproducing can be stopped by ACL input ("L").
PHRASE
SELECTION
~------------------115.6msC=
START
_ _--'I
:
I
:
*'
11......-_ _ _ _ _ _ _ _ _ _ __
\V
IJ\.............: _________E_N_A_BL_E_ _ _ _ _ _ _ _ _ _-.J'r'
INTERNAL
OSCILLATION _ _
DI_SA_B_L_E__
:1
DISABLE
I
I
REPRODUCING
DAO
--1
2.5V
816ms f . - - - -
Figure 2. Timming Diagram at REP3 Mode
c8SAMSUNG
263
II
KS5912XX
CMOS DIGITAL INTEGRATED CIRCUIT
Infinite Mode
When start signal keeps "H" state continuously, the sound reproduces continuously irrespective of mode (normal,
REP3/REP8).
-V
PHRASE
SELECTION...J\....._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
START
--J
I
I
I
INTERNAL~~-----------------------------------
OSCILLATI~.....- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - I
:~~"" 1-t=oo",,:W~,g--g
15.6ms
15.6ms
REP3
DAO
15.6ms
15.6ms
15.6ms
15.6ms
II$;J----0'/$;}-v11II!/A---10f""""1"'"1""WJ;....,...,...,..~
-+EPRODUCINGH!
~
816ms
~-
=i
816ms
~ ~
C =i
15.6ms
816ms
15.6ms
F
Figure 3. Timming Diagram at Infinite Mode
Start Operation
KS5912XX mask ROM is consist of 16 bits x 4K and index area is stored start address and bit rate for phrase
1, 2, 3 and 4.
KS5912XX stops internal oscillation for power dissipation at stand-bY.
After selection of phrase and start signal, it starts internal oscillation and reproduces sound by information of
index area.
Start signal debouncing time for protection of chattering by SW., etc. is 15.6ms. When start signal activates "H",
sound reproducing is repeated continuously.
c8SAMSUNG
264
KS5912XX
CMOS DIGITAL INTEGRATED CIRCUIT
PIN CONFIGURATIONS
1) Pin Assignments
KS5912XX
II
(KS5912XX Pin Assignments)
2) Pin Descriptions
Pin No.
Name
1/0
Descriptions
1
PS1
I
2
PSO
I
Phrase selection pins
(pull·down)
3
RDUMP
0
Internal status output pin for test
4
MODE2
I
MODE selection pin 2 (pull·up)
5
MODE1
I
MODE selection pin 1 (pull·up)
6
OSCOUT
0
660 KHz, RC oscillator OUTPUT pin
7
OSCIN
I
660 KHz, RC oscillator INPUT pin
8
Vss
-
GROUND
9
DAO
0
10 bit DIA converter output
10
-ACL
I
System reset pin (Low Active)
11
START
I
12
DAR9
1/0
13
SYSCLK
0
System clock output pin (128 KHz)
14
TEST1
1/0
TEST pin (Normally Ground)
15
TEST2
1/0
TEST pin (Normally Ground)
16
VDD
-
+5 Volt
c8SAMSUNG
Start signal input pin (pull·down)
TEST pin Normally N.C.
265
CMOS DIGITAL INTEGRATED CIRCUIT
KS5912XX
TYPICAL APPLICATION CIRCUIT
NORMAL MODE
+5V
+5V
t:
PS',
NC
l~:
Voo
PSO
TEST2
RDUMP
TESn
MODE2
SYSCLK.
NC
DAR9
NC
KS5912XX
MODEl
OSCOUT
START
-L
SW
R
240K
50KIl
50KO
OSCIN
ACl
Vss
DAO
C
r
SW
50KIl
+ ~-~~-,~~~~~~----~
c8SAMSUNG
266
~
MELODY/MISCELLANEOUS ICs
6
Melody ICs
Function
Device
KS5310
KS5313
KS5381
KS5814
Simple Melody with Watch
Simple Melody IC
Multi Melody Ie
Sky-lark's or Cricker's Sound IC
Package
Page
Bare Chip
8/16 DIP
16/20 DIP
14 DIP
269
273
277
286
Package
Page
Bare Chip
289
60 FOP
295
Miscellaneous ICs
Device
KS5116
KS5815
Function
Functions 6 Digits UPIDOWN Counter Circuit
for Triplexed LCD
CentigradelFatirenhert Clinical Thermometer
KS531 0
CMOS DIGITAL INTEGRATED CIRCUIT
SIMPLE MELODY WITH WATCH
The KS5310 series is a CMOS LSI chip which electronically plays a prearranged melody.
FUNCTIONS
•
•
•
•
•
Tempo: 16 kinds (presto-largo)
Sound range: 2.5 octave
High start input
Melody stop input
Selection of automatic stop or repeat of the melody
FEATURES
•
•
•
•
•
•
•
One chip CMOS construction
Plays a melody consisting of 64 notes
Starts from the head of melody
Very low stand-by current
Designed to use with CMOS digital watch circuit
32,768Hz operating frequency
1.5V operation
II
BLOCK DIAGRAM
OSC
ENV
RPT
OUTPUT
MT
Enable
Fig. 1
QSAMSUNG
."
269
KS531 0
CMOS DIGITAL INTEGRATED CIRCUIT
ABSOLUTE MAXIMUM RATINGS
(Ta=25°C)
Characteristic
Supply Voltage
In put Voltage
Operating Temperature
Storage Temperature
Symbol
Value
Unit
Vss
Y'N
+0.3- -2.0
Vss+0.3-Voo-0.7
-20-+70
-55-+125
V
V
°C
°C
Topr
T"9
ELECTRICAL CHARACTERISTICS
(Ta=25°C, Vss =-1.5V, Voo=OV unless otherwise specified)
Characteristic
I
Symbol
Test Conditions
Min
1.2
IVssl
Operating Voltage
Typ
1.5
Max
Unit
2
V
-
Stand-by Current
1ST
Without Load
Operating Current
lop
Without Load
--
0.3
pA
20
30
/LA
Input Low Voltage
V,L
Vss
Vss
Vss +0.1
V
Input High Voltage
V,H
Voo -0.1
Voo
Voo
V
Input Low Current
I,L
V,L=VSS
0.05
pA
I'H
V,H=V OO
1.5
15
/LA
10H
Vss= -1.2V
VoH= -0.7V
30
Input High Current
Output High Current
(Output Terminal)
I
0.1
pA
Output Low Voltage
VOL
Without Load
Vss
Vss
Vss+0.1
Output High Voltage
VOH
Without Load
Voo-0.1
Voo
Voo
V
--
V
OUTPUT TIMING
1) RPT=Vss (OPEN)
MT~
2) RPT=VDD
!-----------
Melody~~-----f_i---------'-I
t-
atune
;-1
voo
....._ _ vss
voo
I
LVOO
MT---.J
vss
:::=:::1
r
- voo
I
Melody Output
vss
I
-------1""1--.....
"".
~
stop
atune
vss
atune
~
Length of a tune=20·30 sec
Fig. 2
c8SAMSUNG
270
KS5310
CMOS DIGITAL INTEGRATED CIRCUIT
APPLICATION CIRCUIT
32,768Hz
vss
ElectrocOil
Transducer
ROC =1200
D
J
r---
OSC
MT
1·5K
I
1.5V
I
-~
__ .JI
KS5310 Series
RPT
OUT
,.A
VDO
from Switches of
Watch Circuit
MS
'Currently available types
KS5310A: Oh! Susanna
II
Fig. 3
PAD DIAGRAM
2270
140
1330
D
D D D D D
OSC
1820
1550
T2
T1
1760
2000
Voo
TC
2210
(2550, 2430)
2290
NC
D
D
NC
1/60
NC
KS5310 Series PAD DIAGRAM
Chip Size: 2550x2430
Pad Size : 120x120
Unit
: I'm
NC
D
D
MS
vss
RPT
OUT
NC
150
D
D
D
D
D
(0.0)
140
360
610
1830
2100
2410
MT
350
150
Fig. 4
c8SAMSUNG
271
KS531 0
CMOS DIGITAL INTEGRATED CIRCUIT
CUSTOM ORDER
Changing the contents of melody ICs are possible by reprogramming the maskable ROM. Please free to contact us for
more information including ORDER spec.
CUSTOM ORDER SPEC
1. Request Date:
2. Development Term:
3. Melody
a. Song name:
b. Melody Time:
c. Tempo:
d. Octave Range:
e. Repeated Syllable: (Yes/No)
4. Function
• a. Melody Start Input (Active High/Active Floating)
b. Melody Start Signal (Level Hold/One Shot)
c. Repeat Input(RPT)
d. Repeat Interval
e. Melody Stop Input:
f. Output Pad:
g. Application Set
5. Others.
c8SAMSUNG
272
KS5313
CMOS DIGITAL INTEGRATED CIRCUIT
SIMPLE MELODY IC
8 DIP
The KS5313 series is a CMOS LSI chip which electronically plays a prearranged melody.
FUNCTIONS
• Tempo: 16 kinds
• Sound range: 2.5 octave
• Selection of melody start switch (Active high swi.tch or active floating
switch)
• Selection of melody start signal (Level hold or one shot trigger)
• Selection of automatic stop or repeat of the melody
• Melody stop input
• Level Hold mode/one shot mode user option: 16 Dip
• Level Hold mode only: 8 Dip.
18 DIP
FEATURES
•
•
•
•
One chip CMOS construction
Plays a melody consisting of 64 notes
Starts from the head of melody
Very low stand-by current
• 33KHz operating frequency
• 1.5V operation
II
BLOCK DIAGRAM
OSC1
OSC2
MS
MT1
MT2
SWITCH
CONTROL
CIRCUIT
OS
OUTPUT
RPT
Enable
Fig. 1
c8SAMSUNG
273
KS5313
CMOS DIGITAL INTEGRATED CIRCUIT
ABSOLUTE MAXIMUM RATINGS (Ta =25°C)
Characteristic
Supply Voltage
Input Voltage
Operating Temperature
Storage Temperature
Symbol
Value
Unit
Voo
Y,N
0.3--2.0
Vss+0.3-Voo-0.7
-20-+70
-55- +125
V
V
°C
°C
Topr
Tstg
ELECTRICAL CHARACTERISTICS
(Ta =25°C, Vss = -1.5V, Voo =OV unless otherwise specified)
Characteristic
Test Conditions
Symbol
Min
IVssl
Operating Voltage
Typ
1.2
Max
1.5
Unit
2
V
------------
-~
Input High Voltage
I
------
V'H
- -------- 1----
~
Input Low Voltage
---------
.. _--- - - - - - - - - - - f - - - - - - - - - - - - - - -
Strand-by Current
Voo -0.1
Voo
Vss
Vss +0.1
1ST
Without Load
lop
Without Load
I'H
r---------
--
Operating Current
0.1
20
- - - --- f - - - - - - - - - - - - - - - - - -
Input High Current
----------
I,L
- - - ------ ---
Output 0 Current
f------------
V,L=VSS
I-------------------~
100
.. _-----
--
Output 3, 4 Current
1----
Vss=-1.2V, VoH =-0.7V,
ENV=VSS
-~-
10 (3.4)
-----'"'----
-----
1.5
V,H=V OO
0.3
p.A
30
p.A
15
p.A
0.05
p.A
Voo=IOV, Vss=-1.5V
-----
--
p.A
15
- - --
------------
V
-- - - - -
---------1 - - - - - - - - - - - - - - - - - - -------"
-----------------"---
Input Low Current
V
--------.--~-
V,L
---
± 1.8
mA
Output Low Voltage
VOL
Without Load
Vss
Vss +0.1
V
Output High Voltage
VOH
Without Load
Voo-O.l
V DO
V
36
KHz
f-----------------
Operating Frequency
Fosc
30
33
TEST CIRCUIT
1) OUT 3 AND OUT 4 DRIVE CURRENT
TEST CIRCUIT
2) OUT 0 CURRENT TEST CIRCUIT
OSCl
OUT3
p.G
'"
OUTO
-c-
KS5313 Series
i'0::
.....-: ~:,
J:
0
>
OUT4
p.G: Pulse Generator (1020Hz)
c8SAMSUNG
f---~
V
vss
Fig. 2
Fig. 3
"
r
//
274
KS5313
CMOS DIGITAL INTEGRATED CIRCUIT
TIMING
1) MELODY START INPUT
2) MELODY START SIGNAL
a) Level Hold Mode
a) MT1 (Active High Input)
,...------VDD
MTl
-----.-.;..-----VSS
floating'
------+1------I
MT2
Floating
One Shot
VSS
VDD
Floating
MT1--~""
" " " ' - - - - VSS
or
MT2 _ _ _....
I
VSS
.-----VDD
Floating
I
Melody Start
SF-atun:H
Melody Output
----iII.mmmmnl~llmnnlllllllrr-_!_"!-!- - - VDD
Vss
b) MT2 (Active Floating Input)
b) One Shot Mode
Floating
vss
MTl
VDD
One Shot
VDD
MT2
Floating
n
Vss
MTl
Melody Start
VDD
vss
jOP
Melody Output - -__
I I I I I!I !I!I I I~I I I I!1 !I I I I I I I I-___
~I I I~Ij--___ -___ -____- VVDD
Stjart
3) REPEAT INPUT
a) Normal Mode
a ture
SS
Floating
R~------~----
vss
4) MELODY STOP
VDD
VDD
MTl _ _
Flo_atin..;.g....
vss
or
MT2 _ _ _....
VDD
Floating
Melody Output
vss
MS
vss
Melody Time
VDD
I1111111111111111111111111111111111
Vss
VDD
1IIIIIIIIIIIImllllllmlllllllllllllllili
I
Vss
Melody Stop
b) Repeat Mode
p~--------------------- VDD
VDD
Floating
MT1-------'
or
MT2 _ _ _ _ _ _- - ,
vss
VDD
I" " " " - - - - - - - V s s
Floating
~a l u n e - t - a tune-----i
"11111II111111111""IIII""IIIIIIIII"IIII"I"IIIIIIII~::
c8SAMSUNG
275
II
KS5313
CMOS DIGITAL INTEGRATED CIRCUIT
-APPLICATION CIRCUIT
1) ONE SHOT & LEVEL HOLD MODE
1.5V
Electrocoil
Transducer
• Currently available types
KS5313N: MINUET (BACH)
KS5313Q: Home Sweet Home
KS5313S: Big Ben
KS5313T: For Elise
KS5313P: Cuchoo's Waltz
KS5313R: Oh! Susanna
KS5313 Series
T2
OSC2
OSC1
MT,
os
MT2
MS
2) LEVEL HOLD MODE
1.5V
Voo
OUT~
ENV
Vss
·C1 and R1 are
necessary only when employ
ENVELOPE circuit.
Otherwise, ENVELOPE terminal
must be connected to Vss.
KS5313 Series
MTI
c8SAMSUNG
RPT
276
KS5381
CMOS DIGITAL IC
MULTI MELODY IC
The KS5381 is a CMOS melody IC, the circuit is composed of 512 word ROM, address counter, tempo &
rhythm generator, address control circuit, envelope signal geAerator, switch control circuit, RC oscillator and
tone generator_ Since the KS5381 includes envelope circuit, it can generate good melody sound without any
external component for envelope circuit
The KS5381 can select 8 melodies in serial select
mode and 7 pieces of melody in binary select mode.
The KS5381 can easily connect with the SST standard
watch.
16 DIP
20 sOP
FUNCTION
•
•
•
•
•
•
•
Tempo: 16 kinds
Sound Range: 3 octave (G4-G7)
Play one melody, auto stop
Play all melodies serially
Melody stop function
Serial/binary select mode: bare chip, 20 DIP
Serial select mode: 16 DIP
II
FEATURES
•
•
•
•
•
•
•
One chip CMOS construction
Max. 8 melodies, 512 word ROM
Internal envelope circuit
Piezo direct drive
Very low stand·by current
33 KHz operating frequency
1.5V or 3.0V operation
BLOCK DIAGRAM
-
E
C
OSC R
OSCILL
OSC IN
Ml,
MS
MTIN
T,
E
E
SWITCH
DIVIDER
GENERATOR
OUTPUT &
ENVELOPE
CIRCUIT
CONTROL
CIRCUIT
I
E
~
B
~
P
TONE
'--GENERATOR
ADDRESS
Voo,
VDD1
Vss
T
MT,
TEMPO & RHYTHM
r--
ATOR
OSC C
FREQUENCY
P
MO,
P
MO,
r-ROM
ADDRESS
I--
CONTROL
P
-
R
CIRCUIT
10 bil x512 nolo=5120 bil
COUNTER
r--::;:J
a 1-:]
T
1-=:1
I-:J
'--
Fig. 1.
c8SAMSUNG
277
KS5381
CMOS DIGITAL IC
ABSOLUTE MAXIMUM RATINGS (Ta=25°C)
Characteristics
Symbol
Value
Supply Voltage 1
Vss ~ VOOl
-0.3-4.0
Supply Voltage 1
Vss ~V002
-0.3-4.0
Input Voltage 1
V1N1
Vss - 0.3 - VOOl + 0.3
Input Voltage 2
V,N2
Vss - 0.3 - V002 + 0.3
Output Voltage 1
VOUTl
Vss - 0.3 - VOOl + 0.3
Output Voltage 2
VOUT2
Vss-0.3 -Vo02+0.3
Storage Temperature
Tstg
-55 - + 125
°C
Operation Temperature
Topr
-20-+70
°C
Unit
V
V
V
ELECTRICAL CHARACTERISTICS
1.5V Battery Operation
(Ta=25°C, Vss=OV, V001 , Vo02=1.55V)
Characteristics
Operation Voltage
Switch Input Current
Test Input Current
Symbol
Condition
Value
Min
Typ
Max
VOOl
1.25
1.55
3.3
V002
1.25
1.55
3.3
0.2
1
10
I'Hl
V'N= 1.55V
I,u
V,N=OV
I'H2
V'N= 1.55V
1'L2
V,N=OV
V,H
0.05
2
10
0.3
V'L
Output Current M02, M02
*1 Output Resistor of MO,
Switch Chartering Time
V
p.A
p.A
1.25
Input Voltage
Standby Current
100
0.05
Unit
0.1
100
Without load
10Hl
VOH=1.0V
200
lOll
VoL =0.5V
200
0.5
V
p.A
p.A
RO,
VOH = 0.7V t1
17
R02
VOH = O.7V t2
30
R03
VOH = O.7V t3
50
RO.
VOH =O.7V t4
75
ROs
VOH =O.7V t5
110
ROs
VOH=0.7V t6
170
R0 7
VOH =O.7V t7
260
ROa
VOH =0.7V tS
10L2
VoL =0.5V
TCH
F=3276S Hz
K!l
450
p.A
2
62.5
mS
t1. See Fig. 4 (t1 - tS)
c8SAMSUNG
278
KS5381
BATTERY OPERATION
Characteristics
Operation Voltage
Switch Input Current
Test Input Current
Input Voltage
CMOS DIGITAL IC
(Ta=25°C, Vss=ov, VOD1 = 1.5V, V002 = 3.0V)
Symbol
Condition
Value
Min
Typ
VOO1
1.25
1.5
2.4
VOO2
2.4
3.0
3.3
1
6
I'H1
V'N=3.0V
I'L1
V,N=OV
I'H2
V'N=3.0V
1'L2
V,N=OV
V,H
Output Current M02, M0 2
Output Resistor of MO,
Switch Chartering Time
c8SAMSUNG
60
0.1
5
60
300
0.1
Unit
V
p.A
p.A
2.4
V
0.3
V,L
Standby Current
Max
100
Without load
IOH1
VOH=2.5V
400
0.2
10L1
VOL = 0.5V
400
RO,
VOH=2.1V t1
17
VOH=2.1V t2
30
R03
VOH=2.1V t3
50
RO.
VOH = 2.1V t4
75
ROs
VOH=2.1V t5
110
ROB
VOH=2.1V t6
170
R0 7
VOH=2.1V t7
260
ROB
VOH=2.1VtB
VOL=0.5V
TCH
F=3276B Hz
p.A
p.A
R02
10L2
1
II
KO
450
p.A
2
62.5
mS
279
KS5381
CMOS DIGITAL IC
MELODY SELECT
1. Binary Select Mode
The KS5381 can repeat a melody which select from 7 melodies.
(see Table 1 and Fig. 2)
2. Serial Select Mode
While AS 3, AS2, AS, pins are low level or open, that is, melody select counter is reset, the first melody start
by pushing the switches (MT" MT2) at the same time. The next simultaneous pushing of the switches (MT" MT:0
will change the melody to the next one. If the switch MT, and MT2 are pushed continuously, the 8 melodies
will repeat by itself.
The total number of melody can be selected at will within 8 by mask option.
Fig. 2. The Sequence of Melody
Usage
Melody
AS 3
AS.
AS,
Serial Selection
No. 1·No. 8
L
L
L
No.2
L
L
H
No.3
L
H
L
No.4
L
H
H
No.5
H
L
L
No.6
H
L
H
No.7
H
H
L
No.8
H
H
H
Binary Selection
1 * Advanced by serial select mode
2* Selected by mask option
3* Selected by binary select mode
KS5381A SONG LIST
#
#
#
#
#
#
#
1.
2.
3.
4.
5.
6.
7.
Home Sweet Home
Oh! Susanna
Whispering Hope
Dreaming of Home and Mother
Oh! My darling Clementine
Beautiful Dreamer
Red River Valley
Table 1. Serial and Binary Selection (H: VDD , L: Vss (open»
c8SAMSUNG
280
KS5381
CMOS DIGITAL IC
MELODY OPERATING
There are two method to start the melody. One is pushing the MT, and MT2 at the same time. The other'is to
supply DC or watch alarm signal at "MTIN" pin.
1. Switch Operation
When the switch MT, and MT2 are pushed at the same time, the melody start. The switch MT" MT2, MS is used
for melody stop. Continuous and simultaneous pushing of switch MT, and MT2 will repeat the same melody in binary select mode and change the 8 melodies serially in serial select mode. Fig. 2 shows operation of these switches.
The melody keep on sounding until the switch MS is on. While MT, and MT2 switches are on, the melody is off
as long as MS switch is on. The same melody will restart (binary select opt.) or the next melody will start (serial
selection opt.) in 0.75 sec after the MS switch returns to off.
II
MT,
/
MELoDyr------+--------------------------+---------------~STOPBYMT2
START
MT,. MT2: ON
MT, or MT2: ON
MT,. MT2: OFF
Fig. 3.
2. Alarm Signal Operation
• On-Hour and Switch Conformation Ct.ime
The KS5381 has a 0.75 sec timer circuit to prevent the melody from starting by DC or AC signal. The melody
does not start by chime sound of the KS5910 or signal below 0.75 sec.
• Melody Start
The signals to start melody are the DC or AC signal which is over 0.75 sec. The signals under 0.75 sec will make
the KS5381 melody stand-by mode.
• Melody Stop
The melody does not stop until it plays the end of the melody even if alarm signal stopped. Though the alarm
signal is longer than the melody Signal, the melody does not repeat. If the melody is needed to be stopped in the
midway, it can be done using either switch MT, or MT2.
• Melody Sound
The output frequency of the melody is 400-1500 Hz (musical interval) with signal of 50% duty.
c8SAMSUNG
281
CMOS DIGITAL IC
KS5381
ENVELOPE FUNCTION
The KS5381 has an envelope circuit for high tone quality without any external component. The envelope circuit
make the melody output decrease exponencially. (as shown in Fig. 4.) The transistor for amplification would be
NPN type and has proper hie in order to keep this waveform.
CURRENT
0.61
0.37
r----+----,
----
----t-----,
0.22
Hi t-----''-----I----------...J....-_-_-_-_-.!.-~_~_~_.::-_.::!.L..-_=-_.: =_- _~i. .J. . =_- _-~_~_~1.J.·_·_
."---'1--_ _ _ _ _ TIME
t1
t2
t3
t4
t5
t6
t7
t8
~------------·--------------o
--.-----~
Fig. 4
RC OSCILLATOR
The KS5381 oscillator is composed of 3 inverters, a resistor and a capacitor. The frequency of the oscillator is
determined by a external capacitor and a resistor. The frequency of the oscillator vary by applying voltage and
temperature, therefore it is right to use trimmer resistor for getting precise 32768 Hz.
c8SAMSUNG
282
KS5381
CMOS DIGITAL IC
PAD DIAGRAM
1814
1538
215
450
1449
1684
1919
~
0
0
0
~
@]
KS5381
Chip Size: 2330 x 2000
PAD Size: 90 x 90
Unit
:/Lm
(2330, 2000)
0
1642
[2J
1407
0
950
831
@]
~
742
617
@]
@l
625
382
~
G
510
166
(0,0)
~
[!!]
@]
~
~
~
~
~
226
461
696
931
1166
1572
1758
2165
165
Fig. 5
PAD DESCRIPTION
No.
Pin Name
Description
No.
Pin Name
Description
1
M02
Di rect Piezo Driver
13
MT2
Start & Stop Input
2
M02
Di rect Piezo Driver
14
MS
Melody Stop
3
AS,
Melody Selection
15
MTIN
4
AS2
Melody Selection
16
T2
Test Input
5
ASa
Melody Selection
17
T,
Test Input
6
OSC R
Oscillation
18
RDa
Test Terminal
7
OSCIN
Oscillation & Ext. Input
19
RD.
Test Terminal
8
OSCC
Oscillation
20
RD2
Test Terminal
9
Voo,
1.5V·3.0V Power Supply
21
RD,
Test Terminal
10
Voo" VOD2
VOD2
1.5V-3.0V Power Supply
22
Vss
OV Power Supply
11
1.5V-3.0V Power Supply
23
MO,
ENV. Melody Output
12
MT,
Start & Stop Input
24
Trigger Signal Input
• Pull-down resistor is incorporated into MT" MT2, MS, MTIN, T, and T2.
c8SAMSUNG
283
KS5381
CMOS DIGITAL IC
APPLICATION CIRCUIT
1. Combination with Watch
1) AgO Battery (1.55V)
L.C.D.
PIEZO
MTIN 1-----+----------1 ALB
OOC~
00
MO,
01
KS5381
Series
O.•• F
KS5190
1--<.......---+--_+----1 VOO
Vss
Vss
D
S
._______--' * X·tal: 32768 Hz
# 5·35pF
2) Lithium Battery (3.0V)
P.I ~'O
L.C.D.
PIEZO
DI~
.~~
~
M02
M02
ALB
MTIN
OSCIN
;~ ~
#
KSC 16230)- MO,
L
KS5381
Series
Voo,
I
VOO2
>--
vss
C'+
MT2
MT,
l
~
sw,~
~
SEGMENTS
00
01
Voo,
.l3.0~
WATCH
LSI
VOO2
vsa
SIN,
sw
( SW2
* X·tal: 32768 Hz
# 5·35pF
C,(Cap): O.1,..F
c8SAMSUNG
284
KS5381
CMOS DIGITAL IC
2. PACKAGJ: APPLICATION CIRCUIT
1) 16 DIP type
AD,
Vss
MO,
M02
M02
OSCA
OSCIN
MS
MT
=
• Rose 320Kn
at 3.0V operati ng
OSCC
KS5381 Series
AD2
AD,
ADs
T2
II
J, Vee <1.5V)
2) 20 DIP type
Vee
KS.El564Y
Rose:;;;;
270KO
Vss
AS2
AS3
OSCA
STOP
STAAT
47pF
OSCIN
OSCC
KS5381 Series
Vee <1.5V)
c8SAMSUNG
285
KS5814
CMOS DIGITAL INTEGRATED CIRCUIT
SKY-lARK'S OR CRICKET'S SOUND IC
14 DIP
The KS5814 is a CMOS LSI chip which generates either Sky-lark's sound
or Cricket's sound.
The RC oscillator frequency is used to generate acolIstic pulses for the
sounds.
The sound is initiated by AL-IN, and continued as long as AL-IN is
connected to Vss.
If the AL·IN switch is open, the oscillater will be stopped, thus all
operation will be stopped.
FUNCTIONS
• Selectable either Sky-lark's sound or Cricket's sound by SLCT input
I
I
AL-IN
SOUND
SLCT
SKY-LARK'S SOUND
CRICKET'S SOUND
No operation
FEATURES
•
•
•
•
•
•
Single Chip CMOS construction.
RC oscillator.
Speaker drive by using a PNP transistor.
Single battery (1.5V) operation.
Low power dissipation.
14 pins dual-in-line plastic package.
BLOCK DIAGRAM
r10
I
11
I
OSC2
OSC3
12
I
SLCT
2
~1
- - - - -- ------ - -
I
I
OSC1
AL·IN
-
--
rr
Vdd
Vss
-----------~
I
SOUND
OSCILLATOR
I
SELECT MODE
,
I
j
I
1
I
I
9 I
I
I
I
I
I
I
I
I
FREQUENCY
GENERATOR
ROM
I
4
- r-
GENERATOR
c8
,02
5,..,,03
I
6,..,,04
I
1
PRESET DATA
4
I
I
PRESETFUL
DOWNCOIJNTER
- -
,I
OUT
CIRCUIT
7
OUT
I
I
I
L
,01
I
8 I
TC
3,..,
I
I
I
T1
I
I
__________________________
SAMSUNG
,
-l
286
KS5814
CMOS DIGITAL INTEGRATED CIRCUIT
ABSOLUTE MAXIMUM RATINGS (Ta=2S0C)
Characteristics
Symbol
Supply Voltage
Input Voltage
Operating Temperature
Storage Temperature
value
VDD
V,N
Topr
Tstg
-0.3
Vss -0.3
-10
-55
-
Unit
V
V
°C
°C
+3.0
VDD +0.3
+55
+ 125
'Value grater than this may result in damage to the circuit.
ELECTRICAL CHARACTERISTICS
(Vss =ov, VDD =1.5V, Ta =25°C; unless otherwise specified)
Characteristics
Symbol
Operating Voltage
VDD
Stanby-by Current
1ST
Operating Current
lop
Test Conditions
Min
1.2
- - - - - - _ . _ . _ - - - - - - - - - -_._--- -----
----------------
--
._-_._- - - - - - - - - - .
Input Low Voltage
V'L
Input High Voltage
V,H
Switch Input Current
Isw
- - - - - - - - - - - - - - -: - - - - - ._--
Alarm Sink Current
Oscillation Frequency
Without Load
-----~
los
---
_.
-
100
Typ
Max
Unit
1.5
1.8
V
0.1
0.3
250
400
p.A
0.2
V
VDD-OA
-----~-------.
Vin=Vss
f----------.------
60
100
---_.-1 - - -1-------
0.7
- - _ . r---- - _ . -
210
200
Fosc
V
------------
0.4
Rm=lKO, VDD=1.2V
p.A
-- - - -
220
_".A_
mA
---.--~
KHz
APPLICATION CIRCUIT
OSC3
KS5814
OSC2
OSC1
43KIl
30KIl
'Notes: 01; 02, 03, 04, T1 and
TC are pins for test
purpose only.
c8SAMSUNG
287
II
CMOS DIGITAL INTEGRATED CIRCUIT
KS5814
PAD DIAGRAM
G
G
KS5814 PAD DIAGRAM
Chip Size : 1800x1570
PAD Size : 98x98
Unit
: I'm
~
G
10
(O,O)--X
1-1---------I
1800 - - - - - - - - - - - 1
COORDINATES OF PAD
(Unit/Lm)
Pad No.
1
2
3
4
5
6
7
Name of Pad
SLCT
AL-IN
01
02
03
04
OUT
c8SAMSUNG
Coordinates
---
~-,-,--
X
Y
1671
1446
1043
522
334
129
129
800
1441
1441
1441
1441
1307
830
Coordinates
Pad No.
8
9
10
11
12
13
14
Name of Pad
X
T,
Tc
OSC,
OSC 2
OSCa
Vss
V DD
129
129
464
1029
1379
1671
1671
y
642
129
129
129
129
523
720
288
KS5116
CMOS DIGITAL INTEGRATED CIRCUIT
FUNCTIONS 6 DIGITS UP/DOWN COUNTER
CIRCUIT FOR TRIPLEXED LCD
The KS5116 is a silicon-gate CMOS LSI for 6 digits LCD display up/down
counter.
It operates on single 1.5V battery and the circuit time base is a 16KHz
internal RC oscillator.
FUNCTIONS
•
•
•
•
•
•
Count up, from zero to any setting number
Count down, from any setting number to zero
User selectable up/down mode
Alarm function
Output pulse for any external mechanism
LCD, alarm test
FEATURES
•
•
•
•
•
•
•
II
Single chip CMOS construction.
Built·in RC oscillator
Built·in voltage doubler
6 digits triplexed LCD drive
4 Switch operation
Low power consumption
Single 1.5V battery operation.
ABSOLUTE MAXIMUM RATINGS (Ta = 25°C)
Characteristic
Supply Voltage (VOD1 - Vss)
Supply Voltage (V002 - VSS)
Operating Temperature
Storage Temperature
Symbol
Value
Unit
VOS1
VDS2
-0.3 -+2.0
-0.3 - +4.0
-20-+60
-30-+125
V
V
·C
·C
Tapr
Tstg
* Voltage greater than above may result in damage to the circuit.
289
c8SAMSUNG
------------~---------
CMOS DIGITAL INTEGRATED CIRCUIT
KS5116
ELECTRICAL CHARACTERISTICS
Characteristic
Operating Voltage
Symbol
(T.=25°C,
voo = 1.5V, Vss=OV; unless otherwise specified)
Test Condition
Voo1
Voo2
Min
Typ
Max
Unit
1.2
1.5
1.8
V
2.4
3.0
3.6
V
9
18
p.A
V
Supply Current
100
Input High Voltage
V,H
Voo - 0.3
Voo
Input Low Voltage
V'L
Vss
Vss + 0.3
V
Switch Activation Current
Isw
5
p.A
Alarm Drive Current
Without Load
Yin
=Voo
lapu
V,a' =0.5V
laou
Vea, =0.5V
Oscillator Frequency
Fosc
DC· DC Conversion Frequency
FcON
C1 =C2=0.1p.F
0.1
1.5
0.5
2
mA
50
p.A
--'----
25
32
40
KHz
Hz
800
1,024
1,250
LCD Frequency
Fd
33
43
53
Switch Debounce Time
t,
25
mSEC
Switch Periode Time
t2
35
mSEC
Hz
FUNCTIONAL DESCRIPTION
1. LOCK MODE
When power is on or AC switch is depressed, the state is in lock mode. Where D switch is blocked and S switch
is enable. The depression of S switch in the lock mode will select setting mode.
2. SETTING MODE
If S switch is depressed in the lock mode, the state becomes setting mode. The D switch is used to advance
the function. The flag is off.
• Digit 5,6 flashing mode
Digit 5,6 will flash at a 1Hz rate when S switch is depressed in the lock mode. If D switch is depressed, the counter
of digit 5,6 will advance. Whenever D switch is depressed, the counter of digit 5,6 will advance.
• Digit 3,4 flashing mode
The next depression of S switch will select digit 3,4 flashing mode. In digit 3,4 flashing mode, digit 3,4 flashes
at a 1Hz rate. The operation by using 0 switch is same as digit 5,6 flashing mode.
• Digit 1,2 flashing mode
The next depression of S switch will select digit 1,2 flashing mode. In digit 1,2 flashing mode, digit 1,2 flashes
at a 1Hz rate. The operation by using D switch is same as digit 5,6 flashing mode.
3. ALL FLASHING MODE
The next depression of S switch will select all flashing mode. All digit flashes at a 1Hz rate with flag up or down.
User can select up or down mode
4. NORMAL MODE
The next depression of S switch will select normal mode. If user selects up mode in the all flashing mode, all
of digits display 000000. If user selects down mode the digits display setting number in the Setting mode. The
next depression of S switch will select digit 5, 6 flashing mode. If D switch is depressed. The counter is counted
up or down by state of flag being up or down.
c8SAMSUNG
.290
CMOS DIGITAL INTEGRATED CIRCUIT
KS5116
5. COUNTING MODE
The depression of 0 switch in normal mode will enter counting mode. It counter is matched to setting number
in up mode or down mode, alarm sound and outputs pulse output.
6. ALL CLEAR OPERATION
The depression of AC switch will select lock mode in every mode.
7. LAMP TEST
The deprEl8sion of S, 0 and AC switch at a same time will display all digit segment and cause 'alarm sound
with flag (up or down).
, 8. ALARM MODE
The depression of 0 and S switch is blocked in alarm mode. After the counter is matched to setting number
in up mode or down mode .
• Switch can recognize minimum 30 times per second
I
I
I
t"~-I
=
II
t1 25m sec
t2 = 35m sec
LCD FORMAT
:iii
0
0
c
'"
:!!
0
0
:s
0
w
c5
Ii:'
<"
31
30
Pad No.
33
32
COM1
U
03
F1
COM2
0
02
G1
01
E1
COM3
c8SAMSUNG
0
8
8
rE
~
~
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