1989_Signetics_Microcontrollers_Users_Guide 1989 Signetics Microcontrollers Users Guide

User Manual: 1989_Signetics_Microcontrollers_Users_Guide

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INTEGRATED

CIRCUITS

Signetics
Microcontroller
Users'
Guide

PHILIPS

INDEX

Pl.D 1

40 Vee

P1.1~

39 PO. alA DO
38 PO.t/ADt

:::!~

~ PO.2/AD2

PtA 5

~ PO.3/AD3

P1.5 6

35 POA/AD4

Pl.B 7

34 PO.5/AD5

Pt.? 8

33 PO.S/AD6

RST~

32 PO.l/AD?

RxD/P3.0~

DIP

31 EA

,~~~;:~:: ~

30 ALE

M1/P3.313
TO/P3.4 14

29 PSEN

P2.7/A15

27 P2.S/A14

Tl/P3.515

26 P2.5JA13

~/P3.6~

25 P2.4/A12

R~~~:*

24 P2.3/Al1
23 P2.2/Al0

XTAl119

22 P2.1/A9
21 P2.0/A8

Vss 20

"ToPViEW
INDEX
CORNER

r~J

"""tj
7

Pin
1
2
3
4
5
6
7

9
10
11
12

13
14
15
16
17
18
19
20
21

P1.6
Pt.?

RST
RxD/P3.0
NC

IxD/P3.1

mro/P3.2
INTt IP3.3
TO/P3.4
Tl/P3.5
WR/P3.6
AD/P3.?
41
XTAL2
42
XTAL1
43
44
V"

P2.t/A9

PSEN

ALE
NC

PO.l/AD?
PO.B/ADS
PO.S/ADS
POA/AD4
PO.3/AD3

PO.2IAD2
PO.t/ADt
PO.D/ADO

Vee

Function
NC

Function
NC
P2.0/A8
P2.lIA9
P2.2/Al0
P2.3/Al1
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15

Pin
23
24
25
26
27
28
29
30

PloD

P1.1
Pl.2
P1.3
Pl.4

Pl.5
P1.6
Pl.?
RST

31
32

RxD/P3.0
NC
TxD/P3.1

iiii'i"i/P3.3
TOJP3.4

T1/P3.S
WR/P3.6

1m!?3.?
XTAL2
XTALl
1

Pin
1
2
3
4
5
6
7

9
10
11
12
13
14
15
16
17
18
19
20
21

18 P1.S/INTO
17 P1A

~~ ~
Vss 12
28 P2.7IA1S
27 P2.6/A14
INDEX

CORNER

24 P2.3/A11

XTAL2 18

23 P2.2/Al0

PO.7/AD?

XTAL1 19

22 P2.1/A9

PO.6/ADe

Vss 20

21 P2.0/A8
TOP VIEW

POAIAD4

PO.l/AD'

Vee

INDEX

00"") ,:
17

28
18
TOP VIEW
Function
Pin Function
NC
23
V"
P2.D/A8
PloD
24
P2.1/A9
Pl.1
25
P2.2/Al0
P1.2
26
P2.3/Al1
Pl.3
27
P2.4/A12
Pl.4
28
P2.5/A13
P1.5
29
P2.6/A14
Pl.6
30
P2.7/A15
Pl.?
31
RST
~
32
ALE
RxD/P3.0
33
NC
NC
34
~
TxD/P3.1
35
PO.7/AD?
ilimi/P3.2
36
PO.s/ADe
INn/P3.3
37
PO.5/AD5
TO/P3.4
38
T1/P3.S
PO.4/AD4
39
PO.3/AD3
WR/P3.6
40
PO.2/AD2
M/P3.?
41
PO.l/ADl
XTAL2
42
PO.a/ADO
XTALl
43
Vee
44
V"

SC80C31B/SC80C51B

:r
29

TOP VIEW
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1S
17
18

FUnction
NC
Pl.0
Pl.l
P1.2
Pl.3
P1A
Pl.5
Pl.6
Pl.?
RST
RxD/P3.0
NC
TxD/P3.1
iNIo/P3.2
mfi/P3.3
TO/P3A
T1/P3.S
WF'l/P3.6

1'IT5/P3.7

20
21
22

XTAL2
XTAL1
Vss

Pin
23
24
25
26
27
28
29
30
31

Function
NC
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/Al1
P2A/Al2
P2.5/A13
P2.6/A14
P2.7IA15
~
ALE/i'i1WG
NC

33
34
35
36

13 P1.0

2. 25

PLCC
11

19
12

TOP VIEW
PI"
1
2
3
4
5

,•
7

14 Pl.1

TOP VIEW

PO.5/AD5

PO.C/ADO

15 P1.3
15 P1.2

RST , ;
DIP

25 P2.4/A12

PO.3/AD3
PD.2/AD2

~ P1.6/INTl

DIP

PO.O/SCL 8

26 P2.5/A13

21 P3.7

PO.l/SDA 7

RD/P3.7 17

PSEN

20 P1.7/TO

Tl/P3.5 15

'cr
V"

22 P3.6

:~:~+

WR/P3.6 16

ALE
NC

33
34
35
36
37
38
39
40
41
42
43
44

mT6/P3.2

Function
NC
P2.0/A8

P2.2/Al0
P2.3/Al1
P2A/A12
P2.5/A13
P2.6/A14
P2.7/A15

23 P3.5

P3.2~

PO.2 6

QF?

28
TOP VIEW
PI"
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

24 Vee

P3.3~

Function
NC
P1.0
Plot
P1.2
Pl.3
Pl.4
P1.S

P3A 1

39 PO.O/ADO

28
18
TOP VIEW

PI"
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

40 Vee

Lec

PLee

S83C751

SC87C51

SC80C31B/SC80C51B

SCN8031 AH/SCN8051 AH

9
10

12
13
14

Function
P3.4
P3.3
P3.2
P3.1
N.C.
P3.0
PO.2
PO.1/SDA
PO.O/SCL
N.C.
RST
X2
Xl

Pin
15
1.
17
18
19
20
21
22
23
24
25
26
27
28

Function
Pl.0
Pl.l
Pl.2
Pl.3
P1.4_
Pl.S/INTO
N.C.
N.C.
Pl.6/INTl
P1.7/TO
P3.7
P3.6
P3.5

Vee

S87C752

~lVpp

PO.7/AD7

PO.6/AD6

38
39
40
41
42
43
44

PO.5/ADS
POAfAD4
PO.3/AD3

PO.2/AD2
PO.lIADl
PO.O/ADO
Vee

S87C751
P3AIA4 1
P3.3/A3 2

P3.2/;~b 3
P1.0 1

40 Vee

Pl,' 2

~ PO.a/ADO

Pl.2 3

38 PO.l/ADl

Pl.3 4

37 PO.2/AD2

P1.4 5

36 PO.3/AD3

P1.5 6

35 POA/AD4

PO.21Vpp 6
PO.l/SDAI
OE-PGM 7

P1.6 7

~ PO.5/AD5

Po.O/!~~L 8

Pl.7 8

33 PO.6/ADS

RST 9

32 PO.71AD7

RxD/P3.0 10

DIP

TxD/P3.1 11

P3.1/A~~ 4
P3.0/A~£ S
TOP VIEW
INDEX

eORNER
1 G26
4 25

PLCC

31 EA

INTO/P3.2 12

~~~~N

iNTI/P3.3 13

28 P2.7/A1S

TO/P3.4 14

27 P2.6/A14

Tl/P3.S 1S

26 P2.S/A13

INDEX

WR/P3.6 16

CORNE,R

M/P3.7 17

2S P2A/A12
24 P2.3/Al1

XTAL2 18

23 P2.2/Al0

XT:~: t¥o

22 P2.1/A9

TOP VIEW

2. 25

G5
PLCC

21 P2.0/A8

Pin Function
1 P3.4/A4
2 P3.3/A3
3 P3.2/A2fAl0
4 P3.1/Al/AS
5 P3.0/AO/A8
6 PO.21Vpp
7 PO.1/SDA/
OE-PGM

8 po.o/seLl

TOP VIEW

See inside of back cover for additional pins.

12
18
TOP VIEW

Pin
1
2
3
4
5
6
7
8

10
11
12
13
14

Function
P3.4/A4
P3.3/A3
P3.2/A2/A10
P3.1/Al/A9
N.C.
P3.0/AO/A8
PO.21Vpp
PO.l/SDAI
DE-PGM
PO.O/SCLI
ASEL
N.C.
RST
X2
Xl
Vss

Pin
15
16
17
18
19
20
21
22
23
24
25
26
27
28

Function
Pl.D/oO
P1.1/Dl
Pl.2/D2

Pl.3/D3
Pl.4/D4
Pl.siiNf'O/DS
N.C.
N.C.
P1.6/INT1/D6
Pl.7/TO/D7
P3.7/A7
P3.6/A6
P3.S/AS

Vee

ASEL
9 RST
10 X2
11 Xl
12 Vss
13 P1.0/ADCO/DO
14

Pin
15
16
17
18
19
20
21
22
23
24

Function
Pl.2/ADC2/D2
Pl.3/ ADC3/o3
Pl.4/ADC4/D4
AVss
AVee_
Pl.5/INTO/D5
Pl.6/INT1/D6
Pl.7/TO/D7

PO.3
PO.4/PWM
OUT

25
26
27
28

P3.7/A7
P3.6/A6
P3.5/AS
Vee

P1.1/ADC1!D1

NOTE:
AO-A10 and 00-07 available for EPROM
verify only.

Signefics

Microprocessor Products

Microcontroller
Users' Guide

Signetics reserves the right to make changes, without notice, in the products, including
circuits, standard cells, and/orsoftware, described or contained herein in order to improve
design andlor performance. Signetics assumes no responsibility or liability for the use of
any of these products, conveys no license or title under any patent, copyright, or mask
work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise
specified. Applications that are described herein for any of these products are for illustrative purposes only. Signetics makes no representation or warranty that such applications
will be suitable for the specified use without further testing or modification. Portions of this
users' guide are printed under a license from Intel Corporation.
LIFE SUPPORT APPLICATIONS
Signetics Products are not designed for use in life support appliances, devices, or systems
where malfunction of a Signetics Productcan reasonably be expected to result in a personal injury. Signetics customers using or selling Signetics' Products for use in such applications do so at their own risk and agree to fully indemnify Signetics for any damages resulting from such improper use or sale.

Signetics registers eligible circuits under
the Semiconductor Chip Protection Act.

Signefics

Contents

Microprocessor Products

Section 1 - 8051 Family
Family Overview. .. . . .. . ........................................................................ 1-1
Arch itectu re . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-4
Hardware Description ............................................................................ 1-20
Programmers' Guide and Instruction Set ............................................................. 1-4B
EPROM Products .............................................................................. 1-111
SCNB031 AH/SCNB051AH Data Sheet .............................................................. 1-115
SCBOC31 B/SCBOC51 B Data Sheet ................................................................ 1-123
SCB7C51 Data Sheet ........................................................................... 1-133
Section 2 - 8051 Family Derivatives
B032/B052 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-1
SCNB032AH/SCNB052AH Data Sheet ................................................ . . . . . . . . . .. 2-11
BXC451 Overview ............................................................................... 2-1B
SCBOC451/SC83C451 Data Sheet .............................................................. 2-21
SCB7C451 Data Sheet ....................................................................... 2-35
BXC552 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-53
SB3C552/SBOC552 Data Sheet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-112
BXC652 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-123
SB3C652/SBOC652 Data Sheet ................................................................ 2-127
BXC751 Overview .............................................................................. 2-137
S83C751 Data Sheet ........................................................................ 2-144
SB7C751 Data Sheet ........................................................................ 2-151
8XC752 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-162
S87C752 Data Sheet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-16B
Section 3 - Application Notes
AN408 SCBOC451 Operation of Port 6 ............................................................... 3-1
AN417 256K Centronics Printer Buffer - Using the SC87C451 Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-12
AN418 CounterlTimer 2 of the 83C552 ............................................................. 3-26
AN420 Using up to 5 External Interrupts on 8051 Family Microcontrollers .................................. 3-33
Section 4 -Inter-Integrated (FC) Circuit Bus
12C Bus Specification ............................................................................. 4-1
12C Peripheral Selection Guide. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .. . . . . . . . . . . . . .
. ................ 4-13
Section 5 - Development Support Tools
Development Support Tools ........................................................................ 5-1
In-Circuit Emulator for 8051 or 8052 Microcontroller ..................................................... 5-2
In-Circuit Emulator for 80C451 Microcontroller ......................................................... 5-4
In-Circuit Emulator for 83C451 Microcontroller ......................................................... 5-6
In-Circuit Emulator for 80C552 Microcontroller ......................................................... 5-8
In-Circuit Emulator for 80C652 Microcontroller ........................................................ 5-10
In-Circuit Emulator for B3C751 Microcontroller ........................................................ 5-12
ASM51 8051 Macro Cross Assembler ............................................................... 5-14
SPGM-100 EPROM Microcontroller and Standard EPROM Programmer ................... , ................ 5-16
Section 6 - Additional Microcontroller Data Sheets
BX305 Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-3
8X401 Microcontroller ............................................................................ 6-2B
SCNB049 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-4B
Section 7 - Sales Offices, Representatives & Distributors ................................................. 7-3

April 1989

Signetics

Section 1
8051 Family

Microprocessor Products

INDEX

1-1
1-1
1-1
1-1
1-1
1-1

Family Overview ..........................................
8051 ..................................................
8051AH ................................................
80C51 BH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
8052AH ................................................
83C451 ................................................
~C~ ...............................................
83C652 ................................................
83C751 ................................................
83C752 ................................................

1-3
1-3
1-3

Architecture . . . . . . . . . . . .
......................
Members of the Family ....................................
8051 ................................................
8051AH ..............................................
80C51 BH ............................................

1-4
1-4
1-4
1-4
1-4

8051 Family Devices Memory Organization .................... 1-4
Program Memory ........................................ 1-4
Data Memory ............................................ 1-6
8051 Family Instruction Set ................................. 1-8
Program Status Word ..................................... 1-8
Addressing Modes ....................................... 1-8
Direct Addressing ........................................ 1-8
Indirect Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-8
Register Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-8
Register-Specific Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-8
Immediate Constants ..................................... 1-9
Indexed Addressing ...................................... 1-9
Arithmetic Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-9
Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-10
Data Transfers ......................................... 1-11
Internal RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-11
External RAM . ....................................... 1-12
LookupTables ........................................ 1-12
Boolean Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-13
Relative Offset ....................................... 1-14
Jump Instructions ..................................... 1-14
CPU Timing ............................................ 1-15
Machine Cycles ......................................... 1-15
Interrupt Structure ....................................... 1-16
Interrupt Enables ..................................... 1-16
Interrupt Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-16
Simulating a 3rd Priority Level in Software .................. 1-18
Hardware Description
Special Function Registers ................................
Accumulator .........................................
B Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Program Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Stack Pointer ........................................
Data Pointer .........................................
Ports 0 to 3 ..........................................
Serial Data Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Timer Registers Basic to 8051 ...........................
Control Registers for the 8051 ...........................

1-21
1-21
1-21
1-21
1-21
1-21
1-21
1-22
1-22
1-22

Microcontroller Users' Guide

INDEX (Continued)
Port Structures and Operation ...................................
I/O Configurations ..........................................
Writing to a Port ............................................
Port Loading and Interfacing ..................................
Read-Modify-Write Feature ...................................
Accessing External Memory .....................................
Timer/Counters ...............................................
Timer 0 and Timer 1 .........................................
Mode 0 ...................................................
Mode 1 ...................................................
Mode2 ...................................................
Mode 3 ...................................................
Standard Serial Interface .......................................
Multiprocessor Communications ...............................
Serial Port Control Register ...................................
Baud Rates ................................................
Using Timer 1 to Generate Baud Rates ..........................
More About Mode 0 .........................................
More About Mode 1 .........................................
More About Modes 2 and 3 ...................................
Interrupts ....................................................
Priority Level Structure .......................................
How Interrupts are Handled ...................................
Externallnterrupts ..........................................
Response Time ............................................
Single-Step Operation .........................................
Reset ......................................................
Power-On Reset .............................................
Power-Saving Modes of Operation ...............................
CHMOS Power Reduction Mode ...............................
Idle Mode .................................................
Power-Down Mode .........................................
On-Chip Oscillators ...........................................
HMOS Versions ............................................
CHMOS Versions ...........................................
Internal Timing ...............................................
Pin Descriptions ..............................................

1-22
1-22
1-24
1-25
1-25
1-25
1-26
1-26
1-27
1-27
1-27
1-27
1-27
1-29
1-29
1-30
1-30
1-30
1-31
1-34
1-34
1-37
1-38
1-38
1-39
1-39
1-39
1-40
1-40
1-40
1-41
1-41
1-42
1-42
1-43
1-43
1-43

8051 Programmers' Guide and Instruction Set ......................
Memory Organization ..........................................
Program Memory .............................................
Direct and Indirect Address Area .................................
Interrupts ....................................................
Timer Set-Ups ...............................................

1-48
1-48
1-48
1-48
1-52
1-55

8051 Family Instruction Set ...................................... 1-59
EPROM Products .............................................
Programming the 87C51 , 87C451, 87C552 ........................
Programming Verification ... , ..................................
EPROM Erasure ..... " ......................................
Programming the 87C751, 87C752 ..............................
SCN8031 AH/SCN8051 AH Data Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SC80C31 B/SC80C51 B Data Sheet ..............................
SC87C51 Data Sheet ........................................

1-111
1-111
1-112
1-113
1-113
1-115
1-123
1-133

Section 1
8051 FAMILY OVERVIEW
The Signetics 8051 family of products is based on the
industry standard for 8-bit high performance microcontrollers. The architecture for the family has been
optimized for sequential real time control applications.
The 8051 family of products are used in a wide range of
applications from those that are relatively simple to
applications in medical instrumentation and automobile
control systems. All of the devices included in the family
are available in versions that have either internal ROM,
EPROM, or CPU only. With the exception of the
83C751 and 752 (which are limited to on-board memory)
all of the devices in the family c an address up to 64k
bytes of both program and data memory.

8OC5lBH
The 80C51BH is the CHMOS version of the 805l.
Functionally it is fully compatible with the 8051, but
being CMOS it draws less current than its HMOS counterpart.
The ROMIess version of the 80C51BH is the 80C31BH.
The EPROM version is the 87C5l.

8052AH
The 8052AR is an enhanced version of the 805l. It is
fabricated with HMOS II technology, and is upwards
compatible with the 805l. Its enhancements over the
8051 include:

The 8051 family of microcontrollers includes the devices
listed in Table 1. The basic architecture of these devices
is shown in Figure l.

•
•
•
•
•

8051
The 8051 is the original member of the family. Among
the features of the 8051 are:
• 8-bit CPU optimized for control applications
• Extensive Boolean processing (single bit logic) capabilities
• 32 bi-directional and individual addressable I/O lines
• 128 bytes of on-chip data RAM
• Two 16-bit timer/counters
• Full duplex UART
• 5-source interrupt structure with 2 priority levels
• On-chip clock oscillator
• 4K bytes of on-chip program memory
• 64K bytes program memory address space
• 64K bytes data memory address space
• 40-pin DIP and 44-pin PLCC packages
The 8031 is a CPU only version of the 8051 and only
differs from the 8051 in that it does not have on-chip
ROM. The 8031 fetches all instructions from external
memory.

805lAH
The 8051AH is identical to the 8051, but is fabricated
with HMOS II technology. It is pin-for-pin compatible
with the 805l. The ROMless version of the 8051AH is
the 8031AH.

256 bytes of on-chip data RAM
Three counter/timers
A 6-source interrupt structure
8K bytes of on-chip program memory
40-pin DIP and 44-pin PLCC packages

The ROMIess version of the 8052AH is the 8032AR.

83C4S1
The 83C451 is an extended I/O version of the 80C51
with the following features:
• Seven 8-bit quasi-bidirectional I/O ports (PLCC version).
• Six 8-bit and one 4-bit quasi-bidirectional I/O
ports (DIP version).
• Mailbox port (port 6) features:
tI Operation as normal quasi-bidirectional I/O port
tI 4 handshake control pins
tI Control status register
tI Input and output buffer registers making port 6
suitable for:
• direct MPU interface
• parallel printer interface
• 64-pin DIP and 68-pin packages.
All other aspects of the 83C451 are identical to the
80C5l. The 87C451 is the EPROM version of this device.

Table 1. 8051 Family of Microcontrollers
Device
Name
8051
8051AH
80C51BH
8052AH
83C451
83C552
83C652
83C751
83C752

February 1989

ROM less
Version
8031
8031AH
80C31BH
8032AH
80C451
80C552
80C652

EPROM
Version

87C51BH

87C451
87C552
87C652
87C751
87C752

ROM
Bytes
4K
4K
4K
8K
4K
8K
8K
2K
2K

1-1

RAM
Bytes
128
128
128
256
128
256
256
64
64

16-Blt
Timers
2
2
2
3
2
3
2
1
1

Circuit
Type
HMOS
HMOS
CHMOS
HMOS
CHMOS
CHMOS
CHMOS
CHMOS
CHMOS

(J)

I:\I)

(l)

EXTERNAL

INTERRUPTS

1
1
1

"II

-L

-TiiiER2 .....
CAPTURE/
COMPARE
ARRAY

8K ROM
IN 8052
83C652
83C552

1
1_

2K ROM
IN 83C751
83C752 I

~
o

(83C552)

(8052)

> <

iil

i%
s::
0"

o
u
en

COUNTER

INPUTS

o
C.

80C552

128

(~C5E)-,

TlMER~

ri'ii1En-_

256 RAM
IN 8052
8OC652

Ie
::l

84 RAM
IN 83C751
83C752

~
(l)

...
-:
01

I\)

~
ED

I/O

4 I/O PORTS

PORT

WATCHDOG
TIMER
(63C552)
FIXED RATEj
TIMER
(83C751/2)

SCL

,PO

P2,

•
ADDRESS/DATA

SDA

TXD

12 C
SERIAL
PORT

RXD

P~P5-P8

NOTES:
Po-P3 FOR 8051. 8052. 83C852
Po-P5 FOR 83C552
PO-P6 FOR 83C451
PART OF PO. AND Pl. P3 FOR 83C75l AND 83C752

-L

2
CD
<
~.

~enG)

a:CD

User's Guide

Signetics Microprocessor Products

8051 Family Overview

Section 1
83C552
The 83C552 is an extended function 80C51 with the
following features:
•
•
•
•
•
•
•
•
•
•

8k bytes of ROM
256 bytes of RAM
lO-bit 8 channel AID
Counter/timer array with high speed outputs and capture inputs
4 counter/timers (including a watchdog timer)
2 PWM outputs
2 serial ports
6 8-bit I/O ports
I2C serial port
68-pin PLCC package

The 83C552 is 100% code compatible with the 80C5l.
The ROMless version of the 83C552 is the 80C552 and
the EPROM version is the 87C552.

83C652
The 83C652 is an 80C51 with the following additions: an
8k ROM, 256 bytes RAM and I2C serial port.
The 83C652 is pin-for-pin compatible with the 80C51
except for minor DC specifications on the l2C serial
port pins.
The ROMless version of the 83C652 is the 80C652.

83C751
The 83C751 is a 24-pin version of the 80C51, where
small size and cost are of· prime consideration. The
83C751 is packaged in a 24-pin "skinnydip" (.300 wide)
and in a 28-pin PLCC package.
The following differences exist between the 83C751 and
the 80C5l. The 83C751 has:
• 2K bytes ROM
• 64 bytes RAM
• I2C serial port (no UART)

•
•
•
•

19 I/O lines
Single level interrupt structure
One counter/timer with 16-bit autoload
No external memory expand ability (data memory can
be expanded using the I2C serial port and I2C compatible memory devices).

Note that since there is no external expandability, the
external memory addressing signals: WR, RD, PSEN,
EA, and ALE are not present. Because of. these differences, instructions UMP, LCALL, and MOVX have no
meaning.
For all other instructions the 83C751 is 100% code
compatible with the 80CS1 and operates at full 80CS1
speed.
The EPROM version of the 83C751 is the 87C75l.

83C752
The 83C752 is a derivative version of the 80C51 that is
intended for use in automotive, electro-mechanical, and
consumer applications. The emphasis of the device is on
high integration and small packaging. The 83C752 contains most of the features of the 80C51 with the following
exceptions:
•
•
•
•
•
•
•
•
•

2K bytes ROM
64 bytes RAM
Single level interrupt structure
One 16-bit counter/timer. (mode 2 only) with 16-bit
autoload
Two 8-bit and one 5-bit bidirectional I/O ports
I2C serial interface
One PWM with timer, including overflow interrupt
capability
5 channels of 8-bit AID
28-pin packages, .both DIP and SMD

The 83C752 does not have external memory expandability. The EPROM versions of the 83C752 is the
87C752.

Table 2. 80C51 Derivative Comparisons
Device

AID

Ports

PWM

Timers

UART

80C51
83C451

4
7

Standard
Standard

83C552

8 channel/
10 bit

Two standard
Two standard
Two standard,
timer 2,
watchdog
(4 total)

Standard, 12C

Two standard

Standard, 12C

One standard,
extended to
16-bit autoload
One standard,
extended to
16-bit autoload

12C

83C652

83C751

2-3/8

83C752

5 channel/
8 bit

2-5/8

February 1989

1-3

12C

User's Guide

Signetics Microprocessor Products

8051 Family Architecture

Section 1
8051 ARCHITECTURE
MEMBERS OF THE FAMILY
The basic architecture of the 8051 devices is as follows:

8051
The 8051 is the original member of the family (see
Figure 2). Among the features of the 8051 are:
• 8-bit CPU optimized for control applications
• Extensive Boolean processing (single-bit logic)
capabilities
• 32 bi-directional and individually addressable I/O lines
• 128 bytes of on-chip data RAM
• Two 16-bit timer/counters
• Full duplex UART
• 5 source interrupt structure with 2 priority levels
• On-chip clock oscillator
• 4K bytes of on-chip program memory
• 64K program memory address space
• 64K data memory address space
The 8031 differs from the 8051 in not having the on-chip
program ROM. Instead, the 8031 fetches all instructions
from external memory.

8051AH
The 8051AH is identical to the 8051, but is fabricated
with HMOS II technology. It is pin-for-pin compatible
with the 8051. The ROMless version of the 8051AH is
the 8031AH.

8OC51BH
The 80C5IBH is the CHMOS version of the 8051.
Functionally, it is fully compatible with the 8051, but
being CMOS it draws less current than the HMOS
counterpart. To further exploit the power savings available in CMOS circuitry, two reduced power modes are
added:
1.

Software-invoked idle mode, during which the CPU
is turned off while the RAM and other on-chip peripherals continue operating. In this mode, current
draw is reduced to about 15% of the current drawn
when the device is fully active.
2. Software-invoked power down mode, during which all
on-chip activities are suspended. The on-chip RAM
continues to hold its data. In this mode the device
typically draws less than 1O~.
Although the 80C51BH is functionally compatible with its
HMOS counterpart, specific differences between the two
types of devices must be considered in the design of an
application circuit if one wishes to ensure complete
interchangeability between the HMOS and CHMOS devices. The ROMless version of the 80C51BH is the
80C3IBH. The EPROM version is the 87C51.

February 1989

8051 FAMILY DEVICES
MEMORY ORGANIZATION
All 8051 devices have separate address spaces for program and data memory, as shown in Figure 3. The
logical separation of program and data memory allows
the data memory to be accessed by 8-bit addresses,
which can be more quickly stored and manipulated by an
8-bit CPU. Nevertheless, 16-bit data memory addresses
can also be generated through the DPTR register.
Program memory can only be read, not written to.
There can be up to 64K bytes of program memory. In
the 8051, 8051AH, 80C51BH, and their EPROM versions, the lowest 4K bytes of program memory are onchip. In the ROMless versions (8031, 8031AH,
80C31BH) all program memory is external. The read
strobe for external program memory is the !'SEN (program store enable).
Data Memory occupies a separate address space from
Program Memory. Up to 64K bytes of external RAM can
be addressed in the external Data Memory space.. The
CPU generates read and write signals, RD and WR, as
needed during external Data Memory accesses.
External Program Memory and external Data Memory
may be combined if desired by applying the RD and
PSEN signals to the inputs of an AND gate and using
the output of the gate as the read strobe to the external
Program/Data memory.

PROGRAM MEMORY
Figure 4 shows a map of the lower part of the Program
Memory. After reset, the CPU begins execution from
location OOOOH. As shown in Figure 4, each interrupt is
assigned a fixed location in Program Memory. The interrupt causes the CPU to jump to that location, where it
commences execution of the service routine. External
Interrupt 0, for example, is assigned to location 0003H.
If External Interrupt 0 is going to be used, its service
routine must begin at location 0003H. If the interrupt is
not going to be used, its service location is available as
general purpose Program Memory.
The interrupt service locations are spaced at 8-byte
intervals: 0003H for External Interrupt 0, OOOBH for
Timer 0, 0013H for External Interrupt 1, 00IBH for
Timer 1, etc. If an interrupt service routine is short
enough (as is often the case in control applications), it
can reside entirely within that 8-byte interval. Longer
service routines can use a jump instruction to skip over
subsequent interrupt locations, if other interrupts are in
use.
The lowest 4K bytes of Program Memory can either be
in the on-chip ROM or in an external ROM. This
selection is made by strapping the EA (External Access)
pin to either Vee, or Vss.

1-4

Signetics Microprocessor Products

User's Guide

Section 1

8051 Family Architecture

EXTERNAL
INTERRUPTS

128
RAM

COUNTER
INPUTS

TXD

,!O

P2,

RXD

ADDRESS/DATA

Figure 2. 8051 Block Diagram
PROGRAM MEMORY
(READ ONLY)

.-----------------------•
FFFFH: , . . - - -...

_________

DATA MEMORY

J!~2~~~~~

FFFFH:

________ _
r----,

EXTERNAL

INTERNAL

FFH:~------I""'"'';;'''--'

EA=O
EXTERNAL

••
••

EA=!
INTERNAL

00 _ _ __
....."'T'.....I~OOOO -+11-.._.....1

OOOO""~-r"

._------------------Figure 3. 8051 Memory Structure

February 1989

1-5

User's Guide

Signetics Microprocessor Products

8051 Family Architecture

Section 1
In the 8051, if the EA pin is strapped to Vcc, then the
program fetches to addresses OOOOH through OFFFH are
directed to the internal ROM. Program fetches to addresses 1000H through FFFFH are directed to external
ROM.

002BH

If the EA pin is strapped to Vss, then all program
fetches are directed to external ROM. The ROMless
parts (8031, 80C31, etc .. ) must have this pin externally
strapped to Vss to enable them to execute from external
Program Memory.

0023H

INTERRUPT
LOCATIONS

00lBH]
0013H

The read strobe to external ROM, PSEN, is used for all
external program fetches. PSEN is not activated for
internal program fetches.

8 BYTES

OOOBH

...... .......

The hardware configuration for external program execution is shown in Figure 5. Note that 16 I/O lines (Ports
o and 2) are dedicated to bus functions during external
Program Memory fetches. Port 0 (PO in Figure 5) serves
as a multiplexed address/data bus. It emits the low byte
of the Program Counter (PCL) as an address, and then
goes into a float state awaiting the arrival of the code
byte from the Program Memory. During the time that
the low byte of the Program Counter is valid on Port 0,
the signal ALE (Address Latch Enable) clocks this byte
into an address latch. Meanwhile, Port 2 (P2 in Figure
5) emits the high byte of the Program Counter (PCH).
Then PSEN strobes the EPROM and the code byte is
read into the microcontroller.

0003H
OOOOH

Figure 4. 8051 Program Memory

8051

EPROM

LATCH

Program Memory addresses are always 16 bits wide,
even though the actual amount of Program Memory used
may be less than 64K bytes. External program execution
sacrifices two of the8-bit ports, PO and P2, to the
function of addressing the Program Memory.

P21======~

DATA MEMORY

Figure 5. Executing from External
Program Memory

The right half of Figure 3 shows the internal and external Data Memory spaces available to the 8051 user.
Figure 6 shows a hardware configuration for accessing
up to 2K bytes of external RAM. The CPU in this case
is executing from internal ROM. Port 0 serves as a
multiplexed address/data bus to the RAM, and 3 lines of
Port 2 are being used to page the RAM. The CPU
generates RD and WR signals as needed during external
RAM accesses. There can be up to 64K bytes of external Data Memory. External Data Memory addresses can
be either 1 or 2 bytes wide. One-byte addresses are
often used in conjunction with one or more other I/O
lines to page the RAM, as shown in Figure 6.
Two-byte addresses can also be used, in which case the
high address byte is emitted at Port 2.
Internal Data Memory is mapped in Figure 7. The
memory space is shown divided into three blocks, which
are generally referred to as the Lower 128, the Upper
128, and SFR space.

February 1989

Figure 6. Accessing External Data Memory.
If the Program Memory is Internal, the other

Bits of P2 are Available as 110

1-6

Signetics Microprocessor Products

User's Guide

Section 1

8051 Family Architecture

7rH
rrH

·--------r----, rrH

: ACCESSIBLE
UPPER ,BY INDIRECT
128
'ADDRESSING
BOH:
ONLY
7rH
LOWER
12B

ACCESSIBLE
BY DIRECT
AND INDIRECT
ADDRESSING

0'--_ _--'

ACCESSIBLE
BY DIRECT
ADDRESSING

BANK
SELECT
BITS IN

2rH
T-ADDRESSABLE SPACE
} BI
{B IT ADDRESSES 0-7r)

PSW~

BOH

20H

{ 18H
10 {
10H
01 {
OBH
11

" ' - SPECIAL } PORTS
rUNCTION STATUS AND
REGISTERS CONTROL BITS
TIMER
REGISTERS
STACK POINTER
ACCUMULATOR
(ETC.)

Figure 7. Internal Data Memory

17H
OrH
07H

BANKS or
REGISTERS
O-R7
RESET VALUE or
STACK POINTER

Figure 8. Lower 128 Bytes of Internal RAM

Internal Data Memory addresses are always one byte
wide, which implies an address space of only 256 bytes.
However, the addressing modes for internal RAM can in
fact accommodate 384 bytes, using a simple trick. Direct addresses higher than 7FH access one memory
space, and indirect addresses higher than 7FH access a
different memory space. Thus Figure 7 shows the Upper
128 and SFR space occupying the same block of addresses, 80H through FFH, although they are physically
separate entities.

rrH

NO BIT-ADDRESSABLE
SPACES

The Lower 128 bytes of RAM are present in all 8051
devices as mapped in Figure 8. The lowest 32 bytes are
grouped into 4 banks of 8 registers. Program instructions
call out these registers as RO through R7. Two bits in
the Program Status Word (PSW) select which register
bank is in use. This allows more efficient use of code
space, since register instructions are shorter than instructions that use direct addressing.

BOH

Figure 9. Upper 128 Bytes of Internal RAM

The next 16 bytes above the register banks form a block
of bit-addressable memory space. The 8051 instruction
set includes a wide selection of single-bit instructions,
and the 128 bits in this area can be directly addressed
by these instructions. The bit addresses in this area are
OOH through 7FH.

rrH
EOH

All of the bytes in the Lower 128 can be accessed by
either direct or indirect addressing. The Upper 128
(Figure 9) can only be accessed by indirect addressing.

BOH

Figure 10 gives a brief look at the Special Function
Register (SFR) space. SFRs include the Port latches,
timers, peripherals controls, etc. These registers can
only be accessed by direct addressing. Sixteen addresses
in SFR space are both byte- and bit-addressable. The
bit-addressable SFRs are those whose address ends in
OH or 8H.
The bit addresses in this area are 80H
through FFH.

February 1989

lrH

ACC

··

PORT 3

AOH

PORT 2

90H

PORT 1

BOH

PORT 0

-PORT PINS
-ACCUMULATOR
-PSW

{ETC.}

Figure 10. SFR Space

1-7

User's Guide

Signetics Microprocessor Products

8051 Family Architecture

Section 1
8051 FAMILY INSTRUCTION SET

ADDRESSING MODES

The 8051 instruction set is optimized for 8-bit control
applications. It provides a variety of fast addressing
modes for accessing the internal RAM to facilitate byte
operations on small data structures. The instruction set
provides extensive support for one-bit variables as a
separate data type, allowing direct bit manipulation in
control and logic systems that require Boolean processing.

The addressing modes in the 8051 instruction set are as
follows:

PROGRAM STATUS WORD

INDIRECT ADDRESSING

The Program Status Word (PSW) contains several status
bits that reflect the current state of the CPU. The PSW,
shown in Figure 11, resides in SFR space. It contains
the Carry bit, the Auxiliary Carry (for BCD operations),
the two register bank select bits, the Overflow flag, a
Parity bit, and two user-definable status flags.

In indirect addressing the instruction specifies a register
which contains the address of the operand. Both internal
and external RAM can be indirectly addressed.

DIRECT ADDRESSING
In direct addressing the operand is specified by an 8-bit
address field in the instruction. Only internal Data RAM
and SFRs can be directly addressed.

The address register for 8-bit addresses can be RO or
R1 of the selected bank, or the Stack Pointer. The
address register for 16-bit addresses can only be the 16bit "data pointer" register, DPTR.

The Carry bit, other than serving the function of a Carry
bit in arithmetic operations, also serves as the "Accumulator" for a number of Boolean operations.

REGISTER INSTRUCTIONS
The register ·banks, containing registers RO through R7,
can be accessed by certain instructions which carry a 3bit register specification within the opcode of the instruction. Instructions that access the registers this way
are code efficient, since this mode eliminates an address
byte. When the instruction is executed, one of the eight
registers in the selected bank is accessed. One of four
banks is selected at execution time by the two bank
select bits in the PSW.

The bits RSO and RS1 are used to select one of the four
register banks shown in Figure 8. A number of instructions refer to these RAM locations as RO through R7.
The selection of which of the four is being referred to is
made on the basis of the RSO and RS1 at execution
time.
The Parity bit reflects the number of 1s in the Accumulator: P = 1 if the Accumulator contains an odd number
of 1s, and P = 0 if the Accumulator contains an even
number of 1s. Thus the number of 1s in the Accumulator
plus P is always even. Two bits in the PSW are uncommitted and may be used as general purpose status
flags.

I
PSW 7
CARRY fLAG RECEIVES CARRY OUT
fROW BIT 7 Of AlU OPERANDS

REGISTER-SPECIFIC INSTRUCTIONS
Some instructions are specific to a certain register. For
example, some instructions always operate on the Accumulator, or Data Pointer, etc., so no address byte is
needed to point to it. The opcode itself does that.
Instructions that refer to the Accumulator as A assemble
as accumulator specific opcodes.

I RS,j Rsol

PSW 0
PARITY Of ACCUWULATOR SET
BY HARDWARE TO 1 If IT CONTAINS
AN ODD NUWBER Of 1S. OTHERWISE
IT IS RESET TO 0

' - - - PSW 1

PSW 6
AUXilIARY CARRY fLAG RECEIVES
CARRY OUT fROW BIT 3 Of
ADDITION OPERANOS

USER DEfiNABLE fLAG

PSW 5
GENERAL PURPOSE STATUS fLAG

PSW 2
OVERflOW fLAG SET BY
ARITHWETIC OPERATIONS

PSW 4
REGISTER BANK SELECT BIT 1

PSW 3
REGISTER BANK SELECT BIT 0

Figure 11. PSW (program Status Word) Register in 8051 Devices

February 1989

1-8

Signetics Microprocessor Products

User's Guide

Section 1

8051 Family Architecture

IMMEDIATE CONSTANTS

ARITHMETIC INSTRUCTIONS

The value of a constant can follow the ope ode in Program Memory. For example,

The menu of arithmetic instructions is listed in Table J.
The table indicates the addressing modes that can be
used with each instruction to access the operand. For example, the ADD A, instruction can
be written as:

MOV A, #100
loads the Accumulator with the decimal number 100.
TIle same number could be specified in hex digits as
64H.

ADD
ADD
ADD
ADD

INDEXED ADDRESSING

A,
A,
A,
A,

7FH (direct addressing)
@RO (indirect addressing)
R7 (register addressing)
#127 (immediate constant)

Only program Memory can be accessed with indexed
addressing, and it can only be read. TIlis addressing
mode is intended for reading look-up tables in Program
Memory. A 16-bit base register (either DPTR or the
Program Counter) points to the base of the table, and
the Accumulator is set up with the table entry number.
The address of the table entry in Program Memory is
formed by adding the Accumulator data to the base
pointer.

Note that any byte in the interual Data Memory space
can be incremented without going through the Accumulator.

Another type of indexed addressing is used in the "case
jump" instruction. In this case the destination address of
a jump instruction is computed as the sum of the base
pointer and the Accumulator data.

One of the INC instructions operates on the 16-bit Data
Pointer. The Data Pointer is used to generate 16-bit
addresses for external memory, so being able to increment it in one 16-bit operation is a useful feature.

The execution times
clock frequency. All
cute in If15 except
takes 2f15, and the
which take 4f15.

listed in Table J assume a 12MHz
of the arithmetic instructions exethe INC DPTR instruction, which
Multiply and Divide instructions,

Table 3. 8051 Arithmetic Instructions

Mnemonic

Addressing Modes

Operation
Dir

ADD

Ind

Reg

Imm

Execution
Time (ILS)

A = A +

ADDC A,

A = A + + C

SUBB A,

A = A - - C

INC

A=A+1

INC

= + 1

INC

DPTR

DPTR = DPTR + /1

DEC

A=A-1

DEC

= - 1

MUL

B:A = BxA

ACC and B only

DIV

A = Int [AlB]
B = Mod [AlB)

ACC and B only

Decimal Adjust

Accumulator only

February 1989

Accumulator only
X

1-9

1
1

Data Pointer only

Accumulator only

1
4
4

User's Guide

Signetics Microprocessor Products

8051 Family Architecture

Section 1

ANL A,

The MUL AB instruction multiplies the Accumulator by
the data in the B register and puts the l6-bit product
into the concatenated B and Accumulator registers.

will leave the Accumulator holding OOOlOOOlB.
The addressing modes that can be used to access the
operand are listed in Table 4.

The DIV AB instruction divides the Accumulator by the
data in the B register and leaves the 8-bit quotient in the
Accumulator, and the 8-bit remainder in the B register.

The ANL A, instruction may take any of the
forms:

Oddly enough, DIV AB finds less use in arithmetic
"divide" routines than in radix conversions and programmable shift operations. An example of the use of DIV
AB in a radix conversion will be given later. In shift
operations, dividing a number by 2n shifts its n bits to
the right. Using DIV AB to perform the division completes the shift in 4j.1S and leaves the B register holding
the bits that were shifted out. The DA A instruction is
for BCD arithmetic operations.
In BCD arithmetic,
ADD and ADDC instructions should always be followed
by a DA A operation, to ensure that the result is also in
BCD. Note that DA A will not convert a binary number
to BCD. The DA A operation produces a meaningful
result only as the second step in the addition of two BCD
bytes.

ANL
ANL
ANL
ANL

A,7FH (direct addressing)
A,@Rl (indirect addressing)
A,R6 (register addressing)
A,#53H (immediate constant)

All of the logical instructions that are Accumulatorspecific execute in lj.lS (using a 12MHz clock). The
others take 2j.1S.
Note that Boolean operations can be performed on any
byte in the internal Data Memory space without going
through the Accumulator. The XRL , #data instruction, for example, offers a quick and easy way to
invert port bits, as in XRL PI, #OFFH.

LOGICAL INSTRUCTIONS

If the operation is in response to an interrupt, not using
the Accumulator saves the time and effort to stack it in
the service routine.

Table 4 shows the list of 8051 logical instructions. The
instructions that perform Boolean operations (AND, OR,
Exclusive OR, NOT) on bytes perform the operation on a
bit-by-bit basis. That is, if the Accumulator contains
OOllOlOlB and byte contains OlO]OOl1B, then:

The Rotate instructions (RL A, RLC A, etc.) shift the
Accumulator 1 bit to the left or right. For a left
rotation, the MSB rolls into the LSB position. For a
right rotation, the LSB rolls into the MSB position.

Table 4. 8051 Logical Instructions

Mnemonic

Operation
Dlr

ANL

A = A .AND.

ANL

= .AND.A

Addressing Modes
Reg
Imm
Ind
X

Execution
Time (p.s)

1
1

ANL

, # data

= .AND. #data

ORL

A = A .OR.

ORL

= .OR.A

ORL

,#data

= .OR. #data

XRL

A = A .XOR.

XRL

= .XOR.A

X
X

2
1
1
1
1
1

XRL

< byte> , # data

= .XOR.#data

CRL

A = OOH

Accumulator only

CPL

A = .NOT.A

Accumulator only

Rotate ACC Left 1 bit

Accumulator only

RLC

Rotate Left through Carry

Accumulator only

Rotate ACC Right 1 bit

Accumulator only

RRC

Rotate Right through Carry

Accumulator only

Swap Nibbles in A

Accumulator only

SWAP A

February 1989

1-10

User's Guide

Signetics Microprocessor Products

8051 Family Architecture

Section 1
The SWAP A instruction interchanges the high and low
nibbles within the Accumulator. This is a useful operation in BCD manipulations. For example, if the Accumulator contains a binary number which is known to be
less than 100, it can be quickly converted to BCD by the
following code:
MOV
DIV
SWAP
ADD

TIle Upper 128 are not implemented in the 8051,
8051AH, or 80C51BH, nor in their ROMless or EPROM
counterparts. With these devices, if the SP points to the
Upper 128, PUSHed bytes are lost, and POPed bytes
are indeterminate.
The Data Transfer instructions include a 16-bit MOV
that can be used to initialize the Data Pointer (DPTR)
for look-up tables in Program Memory, or for 16-bit
external Data Memory accesses.

B,#lO
AB
A
A,B

Dividing the number by 10 leaves the tens digit in
low nibble of the Accumulator, and the ones digit in
B register. TIle SWAP and ADD instructions move
tens digit to the high nibble of the Accumulator, and
ones digit to the low nibble.

the
the
the
the

DATA TRANSFERS
INTERNAL RAM
Table 5 shows the menn of instructions that are available for moving data around within the internal memory
spaces, and the addressing modes that can be used with
each one. With a 12MHz clock, all of these instructions
execute in either 1 or 2)lS.
The MOV , instruction allows data to be
transferred between any two internal RAM or SFR locations without going through the Accumulator. Remember
the Upper 128 byes of data RAM can be accessed only
by indirect addressing, and SFR space only by direct
addressing.
Note that in all 8051 devices, the stack resides in onchip RAM, and grows upwards. The PUSH instruction
first increments the Stack Pointer (SP), then copies the
byte into the stack. PUSH and POP use only direct addressing to identify the byte being saved or restored, but
the stack itself is accessed by indirect addressing using
the SP register. TIlis means the stack can go into the
Upper 128, if they are implemented, but not into SFR
space.

The XCH A, instruction causes the Accumulator and addressed byte to exchange data. The XCHD A,
@Ri instruction is similar, but only the low nibbles are
involved in the exchange.
To see how XCH and XCHD can be used to facilitate
data manipulations, consider first the problem of shifting
an 8-digit BCD number two digits to the right. Figure
12 shows how this can be done using direct MOVs, and
for comparison how it can be done using XCH instructions. To aid in understanding how the code works, the
contents of the registers that are holding the BCD
number and the content of the Accumulator are shown
alongside each instruction to indicate their status after
the instruction has been executed.
After the routine has been executed, the Accumulator
contains the two digits that were shifted out on the right.
Doing the routine ,vith direct MOVs uses 14 code bytes
and 9)lS of execution time (assuming a 12MHz clock).
The same operation with XCHs uses less code and executes almost twice as fast.
To right-shift by an odd number of digits, a one-digit
shift must be executed.
Figure 13 shows a sample of code that will right-shift a
BCD number one digit, using the XCHD instruction.
Again, the contents of the registers holding the number
and of the Accumulator are shown alongside each instruction.

Table 5. Data Transfer Instructions that Access Internal Data Memory Space

Mnemonic

Addressing Modes

Operation

Dir

Ind

Reg

Imm

MOV

DPTR,#data16

DPTR = 16-bit immediate constant.

MOV

PUSH

INC SP: MOV "@SP",

POP

MOV , "@SP" : DEC SP

XCH

ACC and < byte> exchange data

XCHD A,@Ri

February 1989

ACC and @Ri exchange low nibbles

1-11

Execution
Time (/-Ls)

1
1

2
2

2
X
X

1
1

Signetics Microprocessor Products

User's Guide

Section 1

8051 Family Architecture
EXTERNAL RAM

2A
MOV A,2EH
00
MOV 2EH,20H
00
MOV 20H,2CH 00
MOV 2CH,2BH
00
MOV 2BH,#0
00
(a) Using direct MOVs: 14

2B 2C
12
34
12
34
12
34
12
12
12
00
bytes, 9 /Ls

2A
2B
CLR
A
00
12
XCH
A,2BH
00
00
XCH
A,2CH
00
00
XCH
A,20H
00
00
XCH
A,2EH
00
00
(b) Using XCHs: 9 bytes, 5 "'S

2C
34
34
12
12
12

20
56
56
34
34
34
20
56
56
56
34
34

2E
78
56
56
56
56
2E
78
78
78
78
56

ACC
78
78
78
78
78
ACC
00
12
34
56
78

Table 6 shows a list of the Data Transfer instructions
that access external Data Memory. Only indirect addressing can be used. The choice is whether to use a
one-byte address, @Ri, where Ri can be either RO or
Rl of the selected register bank, or a two-byte address,
@DPTR. The disadvantage to using 16-bit addresses if
only a few K bytes of external RAM are involved is that
16-bit addresses use all 8 bits of Port 2 as address bus.
On the other hand, 8-bit addresses allow one to address
a few bytes of RAM, as shown in Figure 6, without having to sacrifice all of Port 2. All of these instructions
execute in 2iJS, with a 12MHz clock.
Table 6. 8051 Data Transfer Instructions that
Access External Data Memory Space
Address
Width

Figure 12. Shifting a BCD Number
Two Digits to the Right

MOV
MOV

Rl,#2EH
RO,#2DH

loop for R1
LOOP: MOV
XCHD
SWAP
MOV
DEC
DEC
CJNE

CLR
XCH

00
00
00
00
00
00

12
12
12
12
12
12

34
34
34
34
34
34

56
58
58
58
58
58

78 78
78 76
78 67
67 67
67 67
67 67

Iggl ~~I~~I:~I~~I ~~

A
A,2AH

108101 1231451671 00
00 01 23 45 67 08

:~~~:~~=~ : 2BH:
~g~;
loop for R1

08 01 23 45 67

Figure 13. Shifting a BCD Number
One Digit to the Right

Execution
Time (",s)

8 bits

MOVXA,@Ri

Read external
RAM@Ri

8 bits

MOVX@Ri,A

Write external
RAM@Ri

16 bits

MOVXA,@OPTR

Read external
RAM@DPTR

16 bits

MOVX @DPTR,A

Write external
RAM@DPTR

The read and write strobes to external RAM are activated only during the execution of a MOVX instruction.
Normally these signals are inactive, and in fact if
they're not going to be used at all, their pins are available as extra I/O lines. More about that later.
LOOKUP TABLES
Table 7 shows the two instructions that are available for
reading lookup tables in Program Memory. Since these
instructions access only Program Memory, the lookup
tables can only be read, not updated.
If the table access is to external Program Memory, then
the read strobe is PSEN.

First, pointers Rl and RO are set up to point to the two
bytes containing the last four BCD digits. 'Then a loop is
executed which leaves the last byte, location 2EH, holding the last two digits of the shifted number. The pointers are decremented, and the loop is repeated for location 2DH. The CJNE instruction (Compare and Jump if
Not Equal) is a loop control that will be described later.
The loop executed from LOOP to CJNE for Rl = 2EH,
2DH, 2CH and 2BH. At that point the digit that was
originally shifted out on the right has propagated to location 2AH. Since that location should be left with Os,
the lost digit is moved to the Accumulator.

February 1989

Operation

Note that in all external Data RAM accesses, the Accumulator is always either the destination or source of
the data.

2EH:

A,@Rl
A,@RO
A
@R1,A
R1
RO
R1,#2AH,LOOP

MnemoniC

Table 7. 8051 Lookup Table Read Instructions
Mnemonic

Operation

MOVC A,@A+DPTR

Read Pgm Memory
at (A+DPTR)
Read Pgm Memory
at (A+PC)

MOVC A,@A+PC

1-12

Execution
Time (/La)
2
2

User's Guide

Signetics Microprocessor Products

8051 Family Architecture

Section 1

Table 8. 8051 Boolean Instructions

TIle mnemonic is MOVC for "move constant". 11,e first
MOVC instruction in Table 7 can accommodate a table
of up to 256 entries numbered 0 through 255. 11,e
number of the desired entry is loaded into the Accumulator, and the Data Pointer is set up to point to beginning of the table. Then:
MOVC

Mnemonic

A,@A+DPTR

copies the desired table entry into the Accumulator.
The other MOVC instruction works the same way, except the Program Counter (PC) is used as the table
base, and the table is accessed through a subroutine.
First the number of the desired entry is loaded into the
Accumnlator, and the subroutine is called:
MOV
CALL

The subroutine "TABLE" would look like this:
TABLE: MOVC
RET

A,@A+PC

The table itself immediately follows the RET (return)
instruction in Program Memory. This type of table can
have up to 255 entries, numbered 1 through 255.
Number 0 cannot be used, because at the time the
MOVC instruction is executed, the PC contains the address of the RET instruction. An entry numbered 0
would be the RET ope ode itself.

C,bit

C,Ibit C = C .AND .. NOT. bit

ORL

C,bit

ORL

C,Ibit C = C .OR. .NOT. bit

Execution
Time (f£8)

= C .AND. bit

ANL
ANL

MOV

C,bit

C = bit

MOV

bit,C

bit = C

2
2
2
1
2

CLR

C=O

CLR

bit

C = C.OR.bit

C-l

SETB C

A, ENTRY NUMBER
TABLE

Operation

SETB bit

bit = 1

CPL

C = .NOT.C

= .NOT. bit

CPL

bit

rei

Jump if C = 1

JNC

rei

JumpifC = 0

bit,rel

Jump if bit

JNB

bit, rei

Jump if bit

JBC

bit,rel

Jump if bit

=1
=0
= 1; CLR bit

2
2
2
2

The Carry bit in the PSW is used as the single-bit
Accnmnlator of the Boolean processor. Bit instructions
that refer to the Carry bit as C assemble as Carryspecific instructions (CLR C, etc). The Carry bit also
has a direct address, since it resides in the PSW register, which is bit-addressable.

BOOLEAN INSTRUCTIONS
8051 devices contain a complete Boolean (single-bit)
processor. The internal RAM contains 128 addressable
bits, and the SFR space can support up to 128 other addressable bits. All of the port lines are bit-addressable,
and each one can be treated as a separate single-bit
port. The instructions that access these bits are not just
conditional branches, but a complete menu of move, set,
clear, complement, OR, and AND instructions. These
kinds of bit operations are not easily obtained in other
architectures with any amount of byte-oriented software.
The instruction set for the Boolean processor is shown in
Table 8. All bit accesses are by direct addressing.
Bit addresses OOH throngh 7FH are in the Lower 128,
and bit addresses 80H throngh FFH are in SFR space.
Note how easily an internal flag can be moved to a port
pin:
MOV
MOV

C,FLAG
Pl.O,C

In this example, FLAG is the name of any addressable
bit in the Lower 128 or SFR space. An I/O line (the
LSB of Port 1, in this case) is set or cleared depending
on whether the flag bit is 1 or O.

February 1989

Note that the Boolean instruction set includes ANL and
ORL operations, but not the XRL (Exclusive OR) operation. An XRL operation is simple to implement in software. Suppose, for example, it is required to form the
Exclusive OR of two bits:
C

bill .XRL. bit2

The software to do that could be as follows:

OVER:

MOV
JNB
CPL
(continue)

C,bill
bit2,OVER
C

First, bill is moved to the Carry. If bit2 = 0, then C
now contains the correct result. That is, bill .XRL. bit2
= bill if bit2 = O. On the other hand, if bit2 = 1, C now
contains the complement of the correct result. It need
only be inverted (CPL C) to complete the operation.
This code uses the JNB instruction, one of a series of
bit-test instructions which execute a jump if the addressed bit is set (JC, ID, mC) or if the addressed bit
is not set (JNC, JNB). In the above case, bit2 is being
tested, and if bit2 = 0 the CPL C instruction is jumped
over.

1-13

User's Guide

Signetics Microprocessor Products

8051 Family Architecture

Section 1
mc

executes the jump if the addressed bit is set, and
also clears the bit. Thus a flag can be tested and
cleared in one operation.

All the PSW bits are directly addressable, so the Parity
bit, or the general purpose flags, for example, are also
available to the bit-test instructions.

an 11-bit constant. The instruction is 2 bytes long, consisting of the opcode, which itself contains 3 of the 11
address bits, followed by another byte containing the low
8 bits of the destination address. When the instruction is
executed, these 11 bits are simply substituted for the low
11 bits in the Pc. The high 5 bits stay the same. Hence
the destination has to be within the same 2K block as
the instruction following the NMP.

RELATIVE OFFSET
The destination address for these jumps is specified to
the assembler by a label or by an actual address in Program memory. However, the destination address assembles to a relative offset byte. This is a signed (two's
complement) offset byte which is added to the PC in
two's complement arithmetic if the jump is executed.
The range of the jump is therefore -128 to + 127 Program Memory bytes relative to the first byte following
the instruction.

JUMP INSTRUCTIONS
Table 9 shows the list of unconditional jumps with execution time for a 12MHz clock.
Table 9. Unconditional Jumps in 8051 Devices
Mnemonic
JMP
JMP

addr
@A+DPTR

Operation

In all cases the programmer specifies the destination
address to the assembler in the same way: as a label or
as a 16-bit constant. The assembler will put the destination address into the correct format for the given instruction. If the format required by the instruction will not
support the distance to the specified destination address,
a "Destination out of range" message is written into the
List file.
The JMP @A+DPTR instruction supports case jumps.
The destination address is computed at execution time as
the sum of the 16-bit DPTR register and the Accumulator. Typically, DPTR is set up with the address of a
jump table, and the Accumulator is given an index to the
table. In a 5-way branch, for example, an integer 0
through 4 is loaded into the Accumulator. The code to
be executed might be as follows:

MOV
MOV
RL
JMP

Execution
Time (I£S)

Jump to addr

Jump to A + DPTR

CALL addr

Call subroutine at addr

RET

Return from subroutine

RETI

Return from interrupt

NOP

No operation

The Table lists a single "JMP addr" instruction, but in
fact there are three SJMP, LJMP and NMP, which differ in the format of the destination address. JMP is a
generic mnemonic which can be used if the programmer
does not care which way the jump is encoded.
The SJMP instruction encodes the destination address as
a relative offset, as described above. The instruction is 2
bytes long, consisting of the opcode and the relative offset byte. The jump distance is limited to a range of -128
to +127 bytes relative to the instruction following the
SJMP.

DPTR,#JUMP TABLE
A,INDEx..NUMBER
A
@A+DPTR

The RL A instruction converts the index number (0
through 4) to an even number on the range 0 through 8,
because each entry in the jump table is 2 bytes long:
JUMP TABLE:
NMP
AJMP
AJMP
AJMP
AJMP

CASE
CASE
CASE
CASE
CASE

0
1
2
3
4

Table 9 shows a single "CALL addr" instruction, but
there are two of them, LCALL and ACALL, which differ
in the format in which the subroutine address is given to
the CPU. CALL is a generic mnemonic which can be
used if the programmer does not care which way the address is encoded.
The LCALL instruction uses the 16-bit address format,
and the subroutine can be anywhere in the 64K Program
Memory space. The ACALL instruction uses the ll-bit
format, and the subroutine must be in the same 2K block
as the instruction following the ACALL.

The LJMP instruction encodes the destination address as
a 16-bit constant. The instruction is 3 bytes long, consisting of the opcode and two address bytes. The destination address can be anywhere in the 64K Program Memory space.

In any case the programmer specifies the subroutine address to the assembler in the same way: as a label or as
a 16-bit constant. The assembler will put the address into the correct format for the given instructions.

The NMP instruction encodes the destination address as

Subroutines should end with a RET instruction, which returns execution to the instruction following the CALL.

February 1989

1-14

User's Guide

Signetics Microprocessor Products

8051 Family Architecture

Section 1

CPU TIMING

RETI is used to return from an interrupt service routine.
The only difference between RET and RETI is that
RETI tells the interrupt control system that the interrupt
in progress is done. If there is no interrupt in progress
at the time RETI is executed, then the RETI is functionally identical to RET.

All 8051 microcontrollers have an on-chip oscillator
which can be used if desired as the clock source for the
CPU. To use the on-chip oscillator, connect a crystal or
ceramic resonator between the XTALI and XTAL2 pins
of the microcontroller, and capacitors to ground as
shown in Figure 14.

Table 10 shows the list of conditional jumps available to
the 8051 user. All of these jumps specify the destination
address by the relative offset method, and so are limited
to a jump distance of -128 to + 127 bytes from the instruction following the conditional jump instruction. Important to note, however, the user specifies to the assembler the actual destination address the same way as
the other jumps: as a label or a 16-bit constant.

HMOS
OR CHWOS

,........--IXTA'2

OUAR~ ~~~~~~~~-==
RESONA.TOR

There is no Zero bit in the PSW. The JZ and JNZ instructions test the Accumulator data for that condition.

~""-l-lXT'"
vss

The DJNZ instruction (Decrement and Jump if Not Zero) is for loop control. To execute a loop N times, load
a counter byte with N and terminate the loop with a
DJNZ to the beginning of the loop, as shown below for N
~ 10:

LOOP:

Fignre 14. Using the On-Chip Oscillator
Examples of how to drive the clock with an external oscillator are shown in Figure 15. Note that in the HMOS
devices (8051, etc.) the signal at the XTAL2 pin actually
drives the internal clock generator. In the CHMOS devices (80C51BH, etc.), the signal at the XTALI pin
drives the internal clock generator. The internal clock
generator defines the sequence of states that make up
the 8051 machine cycle.

MOV
COUNTER,#10
(begin loop)

•

•
•

(end loop)
DJNZ
COUNTER,LOOP
(continue)

MACIDNE CYCLES
The CJNE instruction (Compare and Jump if Not Equal)
can also be used for loop control as in Figure 13. Two
bytes are specified in the operand field of the instruction. The jump is executed only if the two bytes are not
equal. In the example of Figure 13, the two bytes were
data in R1 and the constant 2AH. The initial data in R1
was 2EH. Every time the loop was executed, R1 was
decremented, and the looping was to continue until the
Rl data reached 2AH.

A machine cycle consists of a sequence of 6 states,
numbered SI through S6. Each state time lasts for two
oscillator periods. Thus a machine cycle takes 12 oscillator periods or IJ.1S if the oscillator frequency is
12MHz.
Each state is divided into a Phase 1 half and a Phase 2
half. Figure 16 shows that fetch/execute sequences in
states and phases for various kinds of instructions. Normally two program fetches are generated during each
machine cycle, even if the instruction being executed
doesn't require it. If the instruction being executed
doesn't need more code bytes, the CPU simply ignores
the extra fetch, and the Program Counter is not
incremented.

Another application of this instruction is in "greater
than, less than" comparisons. The two bytes in the operand field are taken as unsigned integers. If the first is
less than the second, then the Carry bit is set (1). If the
first is greater than or equal to the second, then the
Carry bit is cleared.

Table 10. Conditional Jumps in 8051 Devices

MnemoniC
JZ
JNZ

rei
rei

DJNZ ,rei
CJNE A, < byte> ,rei
CJNE < byte> ,# data, rei

February 1989

Operation

Dlr

Jump if A = 0
Jump if A*"O
Decrement and jump if not zero
Jump if A *"
Jump if *" #data

1-15

Addressing Modes
Reg
Imm
Ind
Accumulator only
Accumulator only

X
X

Execution
Time (,...s)

2
2
2
2
2

User's Guide

Signetics Microprocessor Products

8051 Family Architecture

Section 1

HWOS
OR eMMOS
XT4L.2

txTtRN4L

CLOCK

XTAl.l

SIGHAL

vss

A. HMOS or CHMOS
HIrotOS
ONLY

ontRMAL

CLOCK
SIGN..L

)O'4LI

vss

='"---B. HMOS Only
CHWO$

ONL'I'

(JoIC)

[XTER ... AL
CLOCK

SIQiAI.

XTALl

When the CPU is executing from internal Program
Memory, PSEN is not activated, and program addresses
are not emitted. However, ALE continues to he activated
twice per machine cycle and so it is available as a clock
output signal. Note, however, that one ALE is skipped
during the execution of the MOVX instruction.

INTERRUPT STRUCTURE
The 8051, 8051AH, 80C5IBH, 83C451, and their
ROMless and EPROM versions, provide 5 interrupt
sources: 2 external interrupts, 2 timer interrupts, and the
serial port interrupt.
What follows is an overview of the interrupt structure for
these devices. More detailed information for specific
members of the 8051 family is provided in later chapters
of this handbook.

INTERRUPT ENABLES
XTALI

vss

='"---C. CHMOS Only

Figure 15. Using an External Clock
Execution of a one-cycle instruction (Figure 16A and B)
begins during State 1 of the machine cycle, when the
opcode is latched into the Instruction Register. A second
fetch occurs during S4 of the same machine cycle. Execution is complete at the end of State 6 of this machine
cycle.
The MOVX instructions take two machine cycles to execute. No program fetch is generated during the second
cycle of a MOVX instruction. This is the only time program fetches are skipped. The fetch/execute sequence
for MOVX instructions is shown in Figure 16D.
The fetch/execute sequences are the same whether the
Program Memory is internal or external to the chip. Execution times do not depend on whether the Program
Memory is internal or external.
Figure 17 shows the signals and timing involved in program fetches when the Program Memory is external. If
Program Memory is external, then the Program Memory
read strobe PSEN is normally activated twice per machine cycle, as shown in Figure 17(A).
If an access to external Data Memory occurs, as shown
in Figure 17(B), two PSENs are skipped, because the
address and data bus are being used for the Data Memory access.

Note that a Data Memory bus cycle takes twice as much
time as a Program Memory bus cycle. Figure 17 shows
the relative timing of the addresses being emitted at

February 1989

Ports 0 and 2, and of ALE and PSEN. ALE is used to
latch the low address byte from PO into the address
latch.

Each of the interrupt sources can be individually enabled
or disabled by setting or clearing a bit in the SFR
named IE (Interrupt Enable). This register also contains
a global disable bit, which can be cleared to disable all
interrupts at once. Figure 18 shows the IE register for
the 8051 devices.

INTERRUPT PRIORITIES
Each interrupt source can also be individually programmed to one of two priority levels by setting or
clearing a bit in the SFR named IP Interrupt Priority).
Figure 19 shows the IP register in the 8051.
A low-priority interrupt can be interrupted by a highpriority interrupt, but not by another low-priority interrupt. A high-priority interrupt can't be interrupted by any
other interrupt source.
If two interrupt requests of different priority levels are
received simultaneously, the request of higher priority
level is serviced. If interrupt requests of the same priority level are received simultaneously, an internal polling
sequence determines which request is serviced. Thus
within each priority level there is a second priority structure determined by the polling sequence.

Figure 20 shows, for the 8051, how the IE and IP registers and the polling sequence work to determine which if
any interrupt will be serviced.
In operation, all the interrupt flags are latched into the
interrupt control system during State 5 of every machine
cycle. The samples are polled during the following machine cycle. If the flag for an enabled interrupt is found
to be set (1), the interrupt system generates an LCALL
to the appropriate location in Program Memory, unless
some other condition blocks the interrupt. Several con1-16

User's Guide

Signetics Microprocessor Products

8051 Family Architecture

Section 1

52 1 53

54 I 55

1 III

1 51

I 54

55 1 56 1

~~~~~~~~~~~~~~~~~~~~~~~~~~

05C.

(XTAL2)

ALE

_R:~O NEXT OPCOOE AGAIN.

------~~--_r--~Lo--_r~

(All.byte, l-cycle I n l _ , •.g., INC A.

I
I

READ OPCODE.

I
:

_ f _ R : NEXT OPCODE.

- - - - - - - - r-''--T---'-:-:-T-:':-t-=:-r-::-1
(BI2-byIe, l-cycle Inlltuc:llon, •.g., ADD A, .da..

READOPCODE
(MOVX).

I
I

------~~--_r--~Lo--_r--~~~~--,_~r_~--~

DATA
(01 MOVX (l-by1e, 2-cyc1e)

ACCESS EXTERNAL MEMORY

Figure 16. State Sequence in 8051 Family devices

ditions can block an interrupt, among them that an interrupt of equal or higher priority level is already in
progress.
The hardware-generated LCAlL causes the contents of
the Program Counter to be pushed into the stack, and
reloads the PC with the beginning address of the service
routine. As previously noted (Figure 4), the service routine for each interrupt begins at a fixed location.
Only the Program Counter is automatically pushed onto

February 1989

the stack, not the PSW or any other register. Having
only the PC be automatically saved allows the programmer to decide how much time to spend saving which
other registers. This enhances the interrupt response
time, albeit at the expense of increasing the programmer's burden of responsibility. As a result, many interrupt functions that are typical in control applications
toggling a port pin for example, or reloading a timer, or
unloading a serial buffer can often be completed in less
time than it takes other architectures to complete.

1-17

User's Guide

Signetics Microprocessor Products

8051 Family Architecture

Section 1

, O N E MACHINE CYCLE-r--0NE MACHINE CYCLEi

1~1~1"1~1"IUI~~~I"I~I"IUI
ALE

PsEN
AD --------+-----------~-----------+------------T_----------~:----I
I

p~......-P..:.C-'H-O-U-T~X'-+_'PC..:....H:...;O:...;U-T--JX

,
I

tPCLOUT
VAllO

tPCLOUT
VALID

PCH OUT

X'-~-PC-H-O-U-T~~

tpCLOUT
VALID

t.PCLOUT
VALID

(A)

WITHOUT A
MOVX.

ALE
PSEN

liD

(B)

--,---;-----~'----

WITH A
MOVX.

t.PCLOUT
VALID

lADDIIOUT
VALID

Figure 17. Bus Cycles iu 8051 Family Devices Executing from External Program Memory

SIMULATING A THIRD PRIORITY LEVEL
IN SOFTWARE
Some applications require more than two priority levels
that are provided by on-chip hardware in 8051 devices.
In these cases, relatively simple software can be written
to produce the same effect as a third priority level. First
interrupts that are to have higher priority than 1 are assigned to priority 1 in the Interrupt Priority (IP) register. The service routines for priority 1 interrupts that
are supposed to be interruptable by "priority 2" interrupts are written to include the following code:
PUSH
MOV
CALL

As soon as any priority interrupt is acknowledged, the
Interrupt Enable (IE) register is redefined so as to disable all but "priority 2" interrupts. Then a CALL to LABEL executes the RETI instruction, which clears the
priority 1 interrupt-in-progress flip-flop. At this point
any priority 1 interrupt that is enabled can be serviced,
but only "priority 2" interrupts are enabled.

POPing IE restores the original enable byte. Then a
normal RET (rather than another RETI) is used to terminate the service routine. The additional software adds
1OJ.lS (at 12MHz) to priority 1 interrupts.

IE
IE,#MASK
LABEL

**********

(execute service routine)
**********
POP
IE
RET
LABEL: RETI

February 1989

1-18

Signetics Microprocessor Products

User's Guide

Section 1

8051 Family Architecture

(MSB)

(LSB)

I EA Ix I x IES IET1 IEXI IETO I EXO I
Symbol

Poaltlon
IE.7

ETI

1E.6

reserved.

1E.5

reserved.

lEA

enables or disables the Sarial Port
interrupt If ES = 0, the Serial Port
interrupt is disabled.

IE.3

(MSB)

Function
disables all interrupts. If EA = 0, no
interrupt will be acknowledged. If EA = 1,
each interrupt source is individually
enabled or disabled by setting or claaring
"s enable bit.

Symbol

(LSB)

Ix I X IPS IPTI IPXl IPTO I pxo I

P081110n
IP.7
IP.6
IP.5

Function
reserved
reserved
reserved

IP.4

defines the Serial Port interrupt priority
level. PS '"' 1 programs it to the higher
priority level.

PTI

IP.3

defines the Timer 1 interrupt priority
level. PT1 - 1 programs it to the higher
priority level.

enables or disables the Timer 1 Overflow
interrupt. If ETI = 0, the Timer 1 interrupt
is disabled.

PXl

IP.2

defines the External Interrupt 1 priority
level. PX1 '"' 1 programs it to the higher
priority level.

PTO

IP.l

defines the Timer 0 interrupt priority
level. PTO '"' 1 programs It to the higher
priority level.

PXO

IP.O

defines the External interrupt 0 priority
level. PXQ - 1 programs it to the higher
priority level.

EXI

IE.2

enables or disables External Interrupt 1. If
EXI = 0, External Interrupt 1 is disabled.

ETO

IE.l

enables or disables the Timer 0 Overflow
interrupt. If ETO = 0, the Timer 0 interrupt
is disabled.

EXO

IE.O

enables or disables External Interrupt O. If
EXO = 0, Externallnterrupl 0 Is disabled.

Figure 18. Interrupt Enable (IE) Register

Figure 19. Interrupt Priority (lP) Register

IE REGISTER

IP REGISTER

HIGH PRIORITY
INTERRUPT

~~--~~~--~~~~
I

I
I

TFO------.t--<:~ ~>-t-IO-~~~I-.I

INTERRUPT
POLLING
SEQUENCE

I
I

TF1----------------~~~~(>-t---~r<~~-l-----J~
I

I
I

RI
TI

TF2
EXF2

r----~~~~_t~~_4~
(8052 ONLY)
INDIVIDUAL
ENABLES

GLOBAL
DISABtE

Figure 20. Interrupt Control System

February 1989

1-19

LOW PRIORITY
INTERRUPT

User's Guide

Signetics Microprocessor Products

Section 1

8051 Family Hardware Description

HARDWARE DESCRIPTION
This chapter provides a detailed description of the 8051
microcontrollers (see Figure 21). Included in this description are:

• The port drivers and how they function both as ports
and, for Ports 0 and 2, in bus operations
• The Timers/Counters
• The Serial Interface
• The Interrupt System
• Reset
• The Reduced Power Modes in CHMOS devices
• The EPROM version of the 80C51BH

r
I

::EI'
I

Li~-----------

February 1989

1-20

Signetics Microprocessor Products

User's Guide

Section 1

8051 Family Hardware Description

SPECIAL FUNCTION REGISTERS

PROGRAM STATUS WORD

A Map of the on-chip memory area called Special Function Register (SFR) space is shown in Figure 22.

The PSW register contains program status information as
detailed in Figure 23.

Note that in the SFRs not all of the addresses are occupied. Unoccupied addresses are not implemented on the
chip. Read accesses to these addresses will in general
return random data, and write accesses will have no effect.

STACK POINTER
The Stack Pointer register is 8 bits wide. It is incremented before data is stored during PUSH and CALL
executions. While the stack may reside anywhere in onchip RAM, the Stack Pointer is initialized to 07H after
a reset. This causes the stack to begin at locations 08H.

User software should not write Is to these unimplemented locations, since they may be used in other 8051
Family products to invoke new features. The function of
the SFRs are described in the text that follows.

DATA POINTER
The Data Pointer (DPTR) consists of a high byte (DPH)
and a low byte (DPL). Its intended function is to hold a
16-bit address. It may be manipulated as a 16-bit register or as two independent 8-bit registers.

ACCUMULATOR
ACC is the Accumulator register. The mnemonics for
Accumulator-Specific instructions, however, refer to the
Accumulator simply as A.

PORTS 0 TO 3
PO, PI, P2 and P3 are the SFR latches of Ports 0, I, 2,
and 3 respectively.

B REGISTER
The B register is used during multiply and divide operations. For other instructions it can be treated as another
scratch pad register.

8 BYTES

F'8
F'O
E8
EO

F'F'
F'7
EF'
E7
OF'

a
ACC

PSW

CF'
C7
BF'
B7
AF
A7

C8
CO

B8
BO

98
90

SCON

TCON

TMOD

TLO

TL1

DPL

DPH

SBUF

THO

TH1

alT

ADDRESSABLE
Figure 22. 80S1 SFR Memory Map

February 1989

1-21

PCON

9F
97
8F
87

User's Guide

Signetics Microprocessor Products

8051 Family Hardware Description

Section 1

(MSB)

(LSB)

AC
Symbol

PoeIllon

CY
AC

PSW.7
PSW.S

PSW.S

RSl
RSO

PSW.4
PSW.3

RSl

Name and Slgnlflcllnca

Carry flag.
Auxiliary Carry flag.
(For BCD operations.)
Flag 0
(Available to the user for general
purposes.)
Register bank select control bits 1 &
O. Set/cl_ed by software to
determine working register benk (_
Note).

RSO

Symbol

Poeltlon

PSW.2
PSW.l
PSW.O

Name and SlpnlflCance

Overflow Ilag.
User definable flag.
Parilyflag.
Set/cleared by hardware each
ins1ruction cycle to Indicate an oddl
even number Of "one" bits in the
Accumulator. i.e•• even parity.

NOTE:
The contents Of (RS1. RSO) aneble the working register banks as
follows:
(OOH-07H)
(O.O)-Bank 0
(O.l)-Bank 1 (OBH-OFH)
(1.0)-8ank 2 (10H-17H)
(l.l)-Bank 3 (18H-1FH)

Figure 23. Program Status Word (pSW) Register
SERIAL DATA BUFFER

The Serial Buffer is actually two separate registers, a
transmit buffer and a receive buffer register. When data
is moved to SBUF, it goes to the transmit buffer is held
for serial transmission. (Moving a byte to SBUF is what
initiates the transmission.) When data is moved from
SBUF, it comes from the receive buffer.
TIMER REGISTERS BASIC TO 8051

Register pairs (TIm, TID), and (ml, 11..1) are the
16-bit Counting registers for Timer/Counters 0, and 1
respectively.
CONTROL REGISTERS FOR THE 8051

Special Function Registers IP, IE, TMOO, TCON,
SCON, and PCON contain control and status bits for the
interrupt system, the Timer/Counters, and the serial
port. They are described in later sections.

PORT STRUCTURES AND
OPERATION
All four ports in the 8051 are bidirectional. Each consists of a latch (Special Function Registers PO through
P3), an output driver, and an input buffer.
The output drivers of Ports 0 and 2, and the input buffers
of Port 0, are used in accesses to external memory. In
this application, Port 0 outputs the low byte of the external memory address, time-multiplexed with the byte
being written or read.
Port 2 outputs the high byte of the external memory address when the address is 16 bits wide. Otherwise, the
Port 2 pins continue to emit the P2 SFR content.

February 1989

All the Port 3 pins are multifunctional. They are not only
port pins, but also serve the functions of various special
features as listed below:
Port
Pin
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7

Alternate Function
RxD (serial input port)
TxD (serial output port)
INTO (external interrupt)
INTI (external interrupt)
TO (Timer/Counter 0 external input)
Tl (Timer/Counter 1 external input)
WR (external Data Memory write strobe)
RD (external Data Memory read strobe)

The alternate functions can only be activated if the corresponding bit latch in the port SFR contains a 1. Otherwise the port pin remains at O.
I/O CONFIGURATIONS

Figure 24 shows a functional diagram ofa typical bit
latch and I/O buffer in each of the four ports. The bit
latch (one bit in the port's SFR) is represented as a
Type D flip-flop, which will clock in a value from the internal bus in response to a "write to latch" signal from
the CPU. The Q output of the flip-flop is placed on the
internal bus in response to a "read latch" signal from the
CPU. The level of the port pin itself is placed on the internal bus in response to a "read pin" signal from the
CPU. Some instructions that read a port activate the
"read latch" signal, and others activate the "read pin"
signal.
As shown in Figure 24, the output drivers of Port 0 and
2 are switchable to an internal ADDR and ADDRI DATA bus by an internal CONTROL signal for use in exter-

1-22

Signetics Microprocessor Products

User's Guide

8051 Family Hardware Description

Section 1

REAO
LATCH

Vcc

WRITE

LATCH

TO
LATCH

READ
PIN

B. Port·1 Bit

A. PortO Bit

ALTERNATE
OUTPUT
FUNCTION

AOOR
VCC

READ
LATCH

tNT. BUS
INT. BUS

WRITE

WRITE
TO
LATCH

LATCH

ALTERNATE

INPUT
FUNCTION

c. Port 2 Bit

D. Port 3 B,t

Figure 24. 8051 Port Bit Latches and 110 Buffers
*See Figure 25 for details of the internal pullup.
nal memory accesses. During external memory accesses,
the P2 SFR remains unchanged, but the PO SFR gets 1s
written to it.
Also shown in Figure 24, is that if a P3 bit latch contains a 1, then the output level is controlled by the signal
labeled "alternate output function". The actual P3.X pin
level is always available to the pin's alternate input function, if any.
Ports 1, 2, and 3 have internal pullups. Port 0 has open
drain outputs. Each I/O line can be independently used
as an input or an output. (Port 0 and 2 may not be used
as general purpose I/O when being used as the ADDRI
DATA BUS). To be used as an input, the port bit latch
must contain a 1, which turns off the output driver FET.
Then, for Ports 1, 2, and 3, the pin is pulled high by the
internal pullup, but can be pulled low by an external
source.

FET in the PO output driver (see Figure 24) is used only
when the port is emitting 1s during external memory accesses. Otherwise the pullup FET is off. Consequently PO
lines that are being used as output port lines are open
drain. Writing a 1 to the bit latch leaves both output
FETs off, so the pin floats. In that condition it can be
used a high-impedance input.
Because Ports 1, 2, and 3 have fixed internal pullups
they are sometimes called "quasi-bidirectional" ports.
When configured as inputs they pull high and will source
current (hL, in the data sheets) when externally pulled
low. Port 0, on the other hand, is considered "true"
bidirectional, because when configured as an input it
floats.
All the port latches in the 8051 have 1s written to them
by the reset function. If a 0 is subsequently written to a
port latch, it can be reconfigured as an input by writing
a 1 to it.

Port 0 differs in not having internal pullups. The pullup

February 1989

1-23

User's Guide

Signetics Microprocessor Products

8051 Family Hardware Description

Section 1

VCC
ENHANCEMENT MODE FET

6D......... . . - - - - - - - -

A. HMOS Configuration. The enhancement mode transistor
Is turned on for 2 08C. perlod8 after Q make8 a 1-to-O tran8ltlon.

FROM PORT
LATCH
INPUT
DATA

CI---C

I-~-<

READ
PORT PIN

B. CHMOS Configuration. pFET 1 18 turned on for 2 08C. periods after Q
makes a 1-to-0 tran8ltlon. During this time, pFET 1 also turns on pFET 3
through the Inverter to form a latch which holds the 1. pFET 21s also on.
Figure 25. Ports 1 and 3 HMOS and CHMOS Internal Pullup Configurations
Port 2 is similar except that it holds the strong pullup on while emitting
is that are address bits. (See Accessing External Memory).
WRITING TO A PORT

In the execution of an instruction that changes the value
in a port latch, the new value arrives at the latch during
S6P2 of the final cycle of the instruction. However, port
latches are in fact sampled by their outpnt buffers only
during Phase 1 of any clock period. (During Phase 2 the
output buffer holds the value it saw during the previous
Phase 1). Consequently, the new value in the port latch
won't actually appear at the output pin until the next
Phase 1, which will be at SlP1 of the next machine cycle.
If the change requires a 0-to-1 transition in Port 1, 2,

or 3, an additional pullup is turned on during SlP1 and
SlP2 of the cycle in which the transition occurs. This is
done to increase the transition speed. The extra pullup
can source about 100 times the current that the normal
pullup can. It should be noted that the internal pullups

February 1989

are field-effect transistors, not linear resistors. The
pullup arrangements are shown in Figure 25.
In HMOS versions of the 8051, the fixed part of the
pullup is a depletion mode transistor with the gate wired
to the source. This transistor will allow the pin to source
about 0.25mA when shorted to ground. In parallel with
the fixed pullup is an enhancement mode transistor,
which is activated during Sl whenever the port bit does
a 0-to-1 transition. During this interval, if the port pin
is shorted to ground, this extra transistor will allow the
pin to source an additional 30mA.
In the CHMOS versions, the pullup consists of three
pFETs. It should be noted that an n-channel FET
(nFET) is turned on when a logical 1 is applied to its
gate, and is turned off when a logical 0 is applied to its
gate. A p-channel FET (PFET is the opposite: it is on
when its gate sees a 0, and off when its gate sees a 1.

1-24

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Si 9 netics M icroprocesso r Prod ucts

8051 Family Hardware Description

Section 1
pFET1 in Figure 25 is the transistor that is turned on
for 2 oscillator periods after a 0-to-1 transition in the
port latch. While it's on, it turns on pFET3 (a weak
pullup), through the inverter. TIlis inverter and pPET
form a latch which hold the 1.
Note that if the pin is emitting a 1, a negative glitch on
the pin from some external source can turn off pFET3,
causing the pin to go into a float state. pFET is a very
weak pullup which is on whenever the nFET is off, in
traditional CMOS style. It's only about 1/10 the strength
of pFET3. Its function is to restore a 1 to the pin in the
event the pin had a 1 and lost it to a glitch.

PORT LOADING AND INTERFACING
TIle output buffers of Ports 1, 2, and 3 can each drive 4
LS 1TL inputs. These ports on HMOS versions can be
driven in a normal malller by any TTL or NMOS circuit. Both HMOS and CHMOS pins can be driven by
open-collector and open-drain outputs, but note that 0to-1 transitions will not be fast.
In the HMOS device, if the pin is driven by an opencollector output, a 0-to-1 transition will have to be driven by the relatively weak depletion mode FET in Figure
25(A).
In the CHMOS device, an input 0 turns off
pullup pFET3, leaving only the very weak pullup pFET2
to drive the transition.
Port 0 output buffers can each drive 8 LS TTL inputs.
TI,ey do, however, require external pullups to drive
NMOS inputs, except when being used as the ADDRESS/DATA bus.

READ-MODIFY-WRITE FEATURE
Some instructions that read a port read the latch and
others read the pin. Which ones do which? The instructions that read the latch rather than the pin are the ones
that read a value, possibly change it, and then rewrite it
to the latch. These are called "read-modify-write" instructions. The instructions listed below are read-modify'Write instructions. \\Thon the destination operand is a

port, or a port bit, these instructions read the latch
rather than the pin:
ANL
ORL
XRL
JBC
CPL
INC
DEC
DJNZ
MOV,PX.Y,C
CLR PX.Y
SET PX.Y

February 1989

(logical AND, e.g. ANL P1,A)
(logical OR, e.g. ORL P2,A)
(logical EX-OR, e.g. XRL
P3,A)
(jump if bit = 1 and clear
bit, e.g. JBC P1.1,LABEL)
(complement bit, e.g.
CPL P3.0)
(increment, e.g. INC P2)
(decrement, e.g. DEC P2)
(decrement and jump if not
zero, e.g. DJNZ P3,LABEL)
(move carry bit to bit Y of
Port X)
(clear bit Y of Port X)
(set bit Y of Port X)

It is not obvious that the last three instructions in this
list are read-modifY-write instructions, but they are.
They read the port byte, all 8 bits, modify the addressed
bit, then write the new byte back to the latch.

The reason that read-modifY-write instructions are directed to the latch rather than the pin is to avoid a possible misinterpretation of the voltage level at the pin.
For example, a port bit might be used to drive the base
of a transistor. Vllhen a 1 is written to the bit, the transistor is turned on. If the CPU then reads the same port
bit at the pin rather than the latch, it will read the base
voltage of the transistor and interpret it as a O. Reading
the latch rather than the pin will return the correct value of 1.

ACCESSING EXTERNAL
MEMORY
Accesses to external memory are of two types: accesses
to external Program Memory and accesses to external
Data Memory. Accesses to external Program Memory
use signal PSEN (program store enable) as the read
strobe. Accesses to external Data Memory use RD or
WR (alternate functions of P3.7 and P3.6) to strobe the
memory. Fetches from external Program Memory always
use a 16-bit address. Accesses to external Data Memory
can use either a 16-bit address (MOVX @ DPTR) or an
8-bit address (MOVX @Ri).
Whenever a 16-bit address is used, the high byte of the
address comes out on Port 2, where it is held for the
duration of the read or write cycle. Note that the Port 2
drivers use the strong pull ups during the entire time that
they are emitting address bits that are 1s. This is during
the execution of a MOVX @DPTR instruction. During
this time the Port 2 latch (the Special Function Register) does not have to contain 1s, and the contents of the
Port 2 SFR are not modified. If the external memory
cycle is not immediately followed by another external
memory cycle, the undisturbed contents of the Port 2
SFR will reappear in the next cycle.
If an 8-bit address is being used (MOVX @Ri), the con-

tents of the Port 2 SFR remain at the Port 2 pins
throughout the external memory cycle. This will facilitate paging.
In any case, the low byte of the address is timemultiplexed with the data byte on Port O. The ADDRI
DATA signals drives both FETs in the Port 0 output
buffers. Thus, in this application the Port 0 pins are not
open-drain outputs, and do not require external pull ups.
ALE (Address Latch Enable) should be used to capture
the address byte into an external latch. The address byte
is valid at the negative transition of ALE. Then, in a
write cycle, the data byte to be written appears on Port
o just before WR is activated, and remains there until
after WR is deactivated. In a read cycle, the incoming
byte is accepted at Port 0 just before the read strobe is
deactivated.

1-25

User's Guide

Signetics Microprocessor Products

8051 Family Hardware Description

Section 1
During any access to external memory, the CPU writes
OFFH to the Port 0 latch (the Special Function Register), thus obliterating whatever information the Port 0
SFR may have been holding.

In the "Counter" function, the register is incremented in
response to a I-to-O transition at its corresponding external input pin, TO or Tl. In this function, the external
input is sampled during SSP2 of every machine cycle.

External Program Memory is accessed under two conditions: Whenever signal EA is active; or whenever the
program counter (PC) contains a number that is larger
than OFFFH (in the 8051).

When the samples show a high in one cycle and a low in
the next cycle, the count is incremented. The new count
value appears in the register during S3Pl of the cycle
following the one in which the transition was detected.
Since it takes 2 machine cycles (24 oscillator periods)
to recognize a I-to-O transition, the maximum count rate
is 1124 of the oscillator frequency. There are no restrictions on the duty cycle of the external input signal, but
to ensure that a given level is sampled at least once before it changes, it should be held for at least one full
cycle. In addition to the "Timer" or "Counter" selection,
Timer 0 and Timer 1 have four operating modes from
which to select.

This requires that the ROMless versions have EA wired
low to enable the lower 4K program bytes to be fetched
from external memory.
When the CPU is executing out of external Program
Memory, all 8 bits of Port 2 are dedicated to an output
function and may not be used for general purpose I/O.
During external program fetches they output the high
byte of the Pc. During this time the Port 2 drivers use
the strong pullups to emit PC bits that are Is.

TIMER 0 AND TIMER 1

TIMER/COUNTERS

The "Timer" or "Counter" function is selected by control
bits CIT in the Special Function Register TMOD. These
two Timer/Counters have four operating modes, which
are selected by bit-pairs (Ml, MO) in TMOD. Modes 0,
1, and 2 are the same for both Timers/Counters. Mode 3
is different. The four operating modes are described in
the following text.

The 8051 has two 16-bit Timer/Counter registers: Timer
o and Timer 1. Both can be configured to operate either
as timers or event counters (see Figure 26).
In the "Timer" function, the register is incremented every machine cycle. Thus, one can think of it as counting
machine cycles. Since a machine cycle consists of 12
oscillator periods, the count rate is 1112 of the oscillator
frequency.

(MSB)

GATE

CIT

GATE

CIT

Gating control when set. Timer/Counter "x" is enabled
only while "INTx" pin is high and "TAx" control pin is
set. When cleared Timer 'Ix" is enabled whenever
"TAx" control bit is set.

(lSB)

•

Timer 1
GATE

CIT

Timer 0
Ml

o
o

Timer or Counter Selector cleared for Timer operation
(input from internal system clock). Set for Counter
operation (input from "Tx" input pin).

Operating Mode
8048 Timer "TLx" se,:,ves as 5--blt prescaler.

16-bit Timer/Counter "THx" and "Tlx" are
cascaded; there is no prescaler.

8-bit auto-reload Timer/Counter "THx" holds a
value which is to be reloaded into "Tlx" each
time it overflows.
(Timer 0) TlO is an 8-bit TImer/Counter
controlled by the standard TImer 0 control bits.
THO is an 8-bit timer only controlled by Timer 1
control bits.
(Timer 1) Timer/Counter 1 stopped.

Figure 26_ Tlmer/Connter Mode Control (TMOD) Register

February 1989

1-26

User's Guide

Signetics Microprocessor Products

8051 Family Hardware Description

Section 1
MODE 0

Mode 2 operation is the same for Timer/Counter O.

Putting either Timer into Mode 0 makes it look like an
8048 Timer, which is an 8-bit Counter with a divide-by32 prescaler. Figure 27 shows the Mode 0 operation as
it applies to Timer 1.

MODE 3

In this mode, the Timer register is configured as a 13bit register. As the count rolls over from all Is to all
Os, it sets the Timer interrupt flag TF1. The counted input is enabled to the Timer when IR1 = 1 and either
GATE = 0 or INfl = 1. (Setting GATE = 1 allows the
Timer to be controlled by external input INf1, to facilitate pulse width measurements). IR1 is a control bit in
the Special Function Register TCON (Figure 28).
GATE is in TMOD.
The 13-Bit register consists of all 8 bits of 11f1 and the
lower 5 bits of 1L1. The upper 3 bits of 1L1 are indeterminate and should be ignored. Setting the run flag
(IR1) does not clear the registers.
Mode 0 operation is the same for the Timer 0 as for
Timer 1. Substitute IRO, TFO and INfO for the corresponding Timer 1 signals in Figure 27. There are two
different GATE bits, one for Timer 1 (TMOD.7) and
one for Timer 0 (TMOD.3).
MODE 1
Mode 1 is the same as Mode 0, except that the Timer
register is being run with all 16 bits.
MODE 2
Mode 2 configures the Timer register as an 8-bit
Counter (1L1) with automatic reload, as shown in Figure 29. Overflow from 1L1 not only sets TF1, but also
reloads 1L1 with the contents of 11f1, which is preset by
software. The reload leaves 11f1 unchanged.

Timer 1 in Mode 3 simply holds its count. The effect is
the same as setting IR1 = O.
Timer 0 in Mode 3 establishes 1LO and 11f0 as two
separate counters. The logic for Mode 3 on Timer 0 is
shown in Figure 30. 1LO uses the Timer 0 control bits:
CIT, GATE, IRO, INTO, and TFO. 11f0 is locked into a
timer function (counting machine cycles) and takes over
the use of IR1 and TF1 from Timer 1. Thus, 11f0 now
controls the "Timer 1" interrupt.
Mode 3 is provided for applications reqUlrmg an extra
8-bit timer on the counte~. With Timer 0 in Mode 3, an
8051 can look like it has three Timer/Counters. When
Timer 0 is in Mode 3, Timer 1 can be turned on and off
by switching it out of and into its own Mode 3, or can
still be used by the serial port as a baud rate generator,
or in fact, in any application not requiring an interrupt.

STANDARD SERIAL INTERFACE
The serial port is full duplex, meaning it can transmit
and receive simultaneously. It is also receive-buffered,
meaning it can commence reception of a second byte
before a previously received byte has been read from the
register. (However, if the first byte still hasn't been read
by the time reception of the second byte is complete,
one of the bytes will be lost). The serial port receive
and transmit registers are both accessed at Special
Function Register SBUF. Writing to SBUF loads the
transmit register, and reading SBUF accesses a physically separate receive register.
The serial port can operate in 4 modes:

CIT. 0

T1 PIN

______-'1 elf·

INTERRUPT
1

Figure 27. Timer/Counter 1 Mode 0: 13-Bit Counter

February 1989

1-27

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Section 1

8051 Family Hardware Description

(MSB)

TFI

TFjO

lEI

ITI

lEO

ITO

Name and Slgnlllcance

Name and SignifICance

Symbol
lEI

PoaIlion
TCON.3

TCON.6

Timer I Run control bit. Set/cleared
by software to turn Timer/Counter on/
011.

TCON.2

TCON.5

Timer 0 overflow Flag. Set by
hardware on Timer/Counter overflow.
Cleared by hardware when processor
vectors to interrupt routine.

Interrupt I Type control bH. Set!
cleared by software to specify failing
edge/low level triggensd external
Interrupts.

lEO

TCON.I

Interrupt 0 Edga flag. Set by hardware
when external interrupt edge
detected. Cleared when interrupt
processed.

ITO

TCON.O

Interrupt 0 Type control bit. Set/
cleared by software to specify falling
edge/low level triggered external
Interrupts.

Poallton
TCON.7

TRI

TFO

TRO

TFO

Timer I overflow Flag. Set by
hardware on Timer/Counter overflow.
Cleared by hardware when processor
vectors to interrupt routine.

TFI

Symbol

(LSB)

TAl

TCON.4

Interrupt I Edge flag. Set by hardware
when external Interrupt edge
detected. Cleansd when Interrupt
processed.

Timer 0 Run control bH. Set/cleared
by software to turn Timer/Counter on/

011.

Figure 28. Timer/Counter Control (TCON) Register

INTERRUPT

Figure 29. Timer/Counter 1 Mode 2: 8-Bit Auto-Load

February 1989

1-28

Signetics Microprocessor Products

User's Guide

Section 1

8051 Family Hardware Description

B--B1112 lose

1' 1210SC

-------,
INTERRUPT

PIN------~

CONTROL

GATE

1'1210SC-----------1~f-!

.~INTERRUPT

~TROL

TR1 ____________

Figure 30. Timer/Counter 0 Mode 3: Two 8-Bit Counters
Mode 0:
Serial data enters and exits through RxD.
TxD outputs the shift clock. 8 bits are transmitted/received (LSB first). The baud is fixed at 1112 the oscillator frequency.
Mode 1: 10 bits are transmitted (through TxD) or received (through Rx D): a start bit (0), 8 data bits (LSB
first), and a stop bit (1). On receive, the stop bit goes
into RB8 in Special Function Register SCaN. The baud
rate is variable.
Mode 2: 11 bits are transmitted (through TxD) or received (through RxD): start bit (0), 8 data bits (LSB
first), a programmable 9th data bit, and a stop bit (1).
On Transmit, the 9th data bit (TB8 in SCaN) can be
assigned the value of 0 or 1. Or, for example, the parity
bit (P, in the PSW) could be moved into TB8. On receive, the 9th data bit goes into RB8 in Special Function Register SCaN, while the stop bit is ignored. The
baud rate is programmable to either 1/32 or 1/62 the
oscillator frequency.
Mode 3: 11 bits are transmitted (through TxD) or received (through RxD): a start bit (0), 8 data bits (LSB
first), a programmable 9th data bit and a stop bit (1).
In fact, Mode 3 is the same as Mode 2 in all respects
except baud rate. The baud ·rate in Mode 3 is variable.
In all four modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is initiated in Mode 0 by the condition RI = 0
and REN = 1. Reception is initiated in the other modes
by the incoming start bit if REN = 1.

February 1989

MULTIPROCESSOR COMMUNICATIONS
Modes 2 and 3 have a special provision for multiprocessor communications. In these modes, 9 data bits are received. The 9th one goes into RB8. Then comes a stop
bit. The port can be programmed such that when the
stop bit is received, the serial port interrupt will be activated only if REB = 1. This feature is enabled by setting bit SM2 in SCaN. A way to use this feature in
multiprocessor systems is as follows:
When the master processor wants to transmit a block of
data to one of several slaves, it first sends out an address byte which identifies the target slave. An address
byte differs from a data byte in that the 9th bit is 1 in
an address byte and 0 in a data byte. With SM2 = 1, no
slave will be interrupted by a data byte. An address byte,
however, will interrupt all slaves, so that each slave can
examine the received byte and see if it is being addressed. The addressed slave will clear its SM2 bit and
prepare to receive the data bytes that will be coming.
The slaves that weren't being addressed leave their
SM2s set and go on about their business, ignoring the
coming data bytes.
SM2 has no effect in Mode 0, and in Mode 1 can be
used to check the validity of the stop bit. In a Mode 1
reception, if SM2 = 1, the receive interrupt will not be
activated unless a valid stop bit is received.
SERIAL PORT CONTROL REGISTER
The serial port control and statu~ register is the Special
Function Register SCaN, shown in Figure 31. This register contains not only the mode selection bits, but also
the 9th data bit for transmit and receive (TBB and RBS),
and the serial port interrupt bits (Tl and Rl).

1-29

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Section 1

8051 Family Hardware Description

(MSB)
SMO

(LSB)
SM'

SM2

AEN

TB8

Where SMO, SM' specify the serial port mode, as follows:

SMO

SMI

0
0

0
1
0

•

SM2

Mode
0
2

or
fosc/32
9-bit UAAT variable

•

TB8

.
.

Baud Rat.

Description
shift register
II-bitUART
9-bitUAAT

AB8

losc/ 12
variable

lose/54

REN

is the 9th data bit that will be
transmitted in Modes 2 and 3. Set or
clear by software as desired.
in Modes 2 and 3, is the 9th data bit
that was received. In Mode I, if SM2
= 0, AB8 is the stop bij that was
received. In Mode 0, RB8 is not used.

is transm~ interrupt flag. Set by
hardware at the end of the 8th M time
in Mode 0, or at the beginning of the
stop bit in the other modes, in any

communication feature in Modes

•

RBe

enables the multiprocessor
2 and 3. In Mode 2 or 3, if SM2 is
set to 1 then RI will not be
activated if the received 9th data
M (AB8) is O. In Mode I, if SM2
= 1 then RI will not be activated
if a valid stop bit was not
received. In Mode 0, SM2 should
beO.

serial transmission. Must be cleared
by software.
•

enables serial reception. Set by
software to enable reception.
Clear by software to disable
reception.

is receive interrupt flag. Set by
hardware at the end of the 8th bit time
in Mode 0, or halfway through tha stop
bit time in the other modes, in any
serial reception (except see SM2).
Must be cleared by software.

Figure 31- Serial Port Control (SCON) Register

BAUD RATES
The baud rate in Mode 0 is fixed: Mode 0 Baud Rate =
Oscillator Frequency / 12. The baud rate in Mode 2 depends on the value of bit SMOD in Special Function
Register peON. If SMOD = 0 (which is the value on reset), the baud rate is 1164 the oscillator frequency. If
SMOD = 1, the baud rate is 1132 the oscillator frequency.

The Timer 1 interrupt should be disabled in this application. The Timer itself can be configured for either "timer" or "counter" operation, and in any of its 3 running
modes. In the most typical applications, it is configured
for "timer" operation, in the auto-reload mode (high
nibble of TMOD = 001OB). In that case the baud rate is
given by the formula:
Mode 1, 3 Baud Rate =

Mode 2 Baud Rate =

2SMOD
Oscillator Frequency
-3-2- x 12 X [256 - (TIll)]

2 SMOD
~ x (Oscillator Frequency)

In the 8051, the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate.
USING TIMER 1 TO GENERATE BAUD RATES
When Timer 1 is used as the baud rate generator, the
baud rates in Modes 1 and 3 are determined by the
Timer 1 overflow rate and the value of SMOD as follows:
Mode 1, 3 Baud Rate =

2SMOD

----n-- x (Timer 1 Overflow Rate)
February 1989

One can achieve very low baud rates with Timer 1 by
leaving the Timer 1 interrupt enabled, and configuring
the Timer to run as a 16-bit timer (high nibble of
TMOD = 0001B), and using the Timer 1 interrupt to do
a 16-bit software reload. Figure 32 lists various commonly used baud rates and how they can be obtained
from Timer 1.
MORE ABOUT MODE 0
Serial data enters and exists through RxD. TxD outputs
the shift clock. 8 bits are transmitted/received: 8 data
bits (LSB first). The baud rate is fixed at 1112 the oscillator frequency.
Figure 33 shows a simplified functional diagram of the
serial port in Mode 0, and associated timing.

1-30

User's Guide

Signetics Microprocessor Products

8051 Family Hardware Description

Section 1

Baud Rate

fose

SMOD

Mode 0 Max: 1 MHZ
Mode 2 Max: 375K
Modes 1, 3: 62.5K
19.2K
9.6K
4.8K
2.4K
1.2K
137.5
110
110

12 MHZ
12MHZ
12MHZ
11.059 MHZ
11.059 MHZ
11.059 MHZ
11.059 MHZ
11.059 MHZ
11.986 MHZ
6MHZ
12MHZ

X
1
1
1
0
0
0
0
0
0
0

Timer 1
CIT Mode Reload
Value
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0

2
2
2
2
2
2
2
2
1

FFH
FDH
FDH
FAH
F4H
E8H
1DH72H
FEEBH

Figure 32. Timer 1 Generated Commonly Used Baud Rates

Transmission is initiated by any instruction that uses
SBUF as a destination register. The "write to SBUF"
signal at S6P2 also loads a 1 into the 9th position of the
transmit shift register and tells the TX Control block to
commence a transmission. The internal timing is such

that one full machine cycle will elapse between "write to
SBUF", and activation of SEND.
SEND enables the output of the shift register to the alternate output function line of P3.0 and also enables
SHIFT CLOCK to the alternate output function line of
P3.I. SHIFT CLOCK is low during S3, S4, and S5 of
every machine cycle, and high during S6, Sl and S2. At
S6P2 of every machine cycle in which SEND is active,
the contents of the transmit shift are shifted to the right
one position.
As data bits shift out to the right, zeros come in from
the left. When the MSB of the data byte is at the output
position of the shift register, then the 1 that was initially
loaded into the 9th position, is just to the left of the
MSB, and all positions to the left of that contain zeros.
This condition flags the TX Control block to do one last
shift and then deactivate SEND and set TL Both of
these actions occur at SlP1 of the 10th machine cycle
after "write to SBUF".
Reception is initiated by the condition REN = 1 and R1
O. At S6P2 of the next machine cycle, the RX Control
unit writes the bits 11111110 to the receive shift register, and in the next clock phase activates RECEIVE.
=

RECEIVE enables SHIFT CLOCK to the alternate output function line of P3.L SHIFT CLOCK makes transitions at S3P1 and S6P1 of every machine cycle. At
S6P2 of every machine cycle in which RECEIVE is active, the contents of the receive shift register are shifted
to the left one position. The value that comes in from

February 1989

the right is the value that was sampled at the P3.0 pin
at S5P2 of the same machine cycle.
As data bits come in from the right, Is shift out to the
left. When the 0 that was initially loaded into the rightmost position arrives at the leftmost position in the shift
register, it flags the RX Control block to do one last
shift and load SBUF. At SlP1 of the 10th machine cycle
after the write to SCaN that cleared RI, RECEIVE is
cleared as RI is set.
MORE ABOUT MODE 1

Ten bits are transmitted (through TxD), or received
(through RxD): a start bit (0), 8 data bits (LSB first),
and a stop bit (1). On receive, the stop bit goes into
RE8 in SCaN. In the 8051 the baud rate is determined
by the Timer 1 overflow rate.
Figure 34 shows a simplified functional diagram of the
serial port in Mode 1, and associated timings for transmit receive.
Transmission is initiated by any instruction that uses
SBUF as a destination register. The "write to SBUF"
signal also loads a 1 into the 9th bit position of the
transmit shift register and flags the TX Control unit that
a transmission is requested. Transmission actually commences at S1P1 of the machine cycle following the next
rollover in the divide-by-16 counter. (Thus, the bit times
are synchronized to the divide-by-16 counter, not to the
"write to SBUF" signal).
The transmission begins with activation of SEND which
puts the start bit at TxD. One bit time later, DATA is
activated, which enables the output bit of the transmit
shift register to TxD. The first shift pulse occurs one bit
time after that.

1-31

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8051 Family Hardware Description

Section 1

WRITE
TO
SBUF

---li-:~t;i:j=~--jJ~--~~------~r-'\

Rxe
P3.0ALT
OUTPUT
FUNCTION

sa --..-------~
Txe
P3.1 ALT
OUTPUT
FUNCTION
' - - - - - . I RX CLOCK

RX CONTROL

REON

I----~

SHIFT

START

r.L-IU-...L..L-IU-I-..1____

Rxe

P3.0 ALT
INPUT
FUNCTION

REAO
SBUF

ALE
---JtWRITE TO saUF
SEND S8P2

SHIFT
TRANSMIT

RXD (DATA OUT) \
TXD (SHIFT CLOCK)
TI

-.l1 WRITE TO SCON (CLEAR RI)

L-~AII~~====Jr====================================================~r----

~CEIVE

SHIFT

RXD (DATA IN)-~-[J!!l!:::--Ql=!.!....--{}~---{}!!!--~L--{)!i!!""--oe!.---{}2!~
TXD (SHIFT CLOCK)

Figure 33. Serial Port Mode 0

February 1989

1-32

RECEIVE

Signetics Microprocessor Products

User's Guide

Section 1

8051 Family Hardware Description
TIMER1
OVERFLOW

WRITE

--~r--:==:{~~~--~~:----'----~~ ~r-...

SBUF
TO

TXD

Figure 34. Serial Port Mode 1
As data bits shift out to the right, zeros are clocked iu
from the left. When the MSB of the data byte is at the
output position of the shift register, then the 1 that was
initially loaded into the 9th position is just to the left of
the MSB, and all positions to the left of that contain zeros. This condition flags the TX Control unit to do one
last shift and then deactivate SEND and set TI. This
occurs at the 10th divide-by-16 rollover after "write to
SBUF".

February 1989

Reception is initiated by a detected I-to-O transition at
RxD. For this purpose RxD is sampled at a rate of 16
times whatever baud rate has been established. When a
transition is detected, the divide-by-16 counter is immediately reset, and IFFH is written into the input shift
register. Resetting the divide·by-16 counter aligns its
rollovers with the boundaries of the incoming bit times.

1-33

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8051 Family Hardware Description

Section 1
The 16 states of the counter divide each bit time into
16ths. At the 7th, 8th, and 9th counter states of each bit
time, the bit detector samples the value of RxD. The
value accepted is the value that was seen in at least 2 of
the 3 samples. This is done for noise rejection. If the
value accepted during the first bit time is not 0, the receive circuits are reset and the uD.itgoes back to looking
for another 1-to-O transition. This is to provide rejection
of false start bits. If the start bit proves valid, it is shifted into the input shift register, and reception of the rest
of the frame will proceed.

As data bits come in from the right, 1s shift out to the
left. When the start bit arrives at the leftmost position in
the shift register, (which in mode 1 is a 9-bit register),
it flags the RX Control block to do one last shift, load
SBUF and RB8, and set RI. The signal to load SBUF
and RB8, and to set RI, will generated if, and only if,
the following conditions are met at the time the final
shift pulse is generated.
1. R1 = 0, and
2. Either SM2 = 0, or the received stop bit

If either of these two conditions is not met, the received
frame is irretrievably lost. If both conditions are met,
the stop bit goes into RB8, the 8 data bits go into SBUF,
and RI is activated. At this time, whether the above conditions are met or not, the unit goes back to looking for
a 1-to-0 transition in RxD.

into the 9th bit position of the shift register. Thereafter,
only zeros are clocked in. Thus, as data bits shift out to
the right, zeros are clocked in from the left. When TB8
is at the output position of the shift register, then the
stop bit is just to the left of TB8, and all positions to the
left of that contain zeros. This condition flags the TX
Control unit to do one last shift and then deactivate
SEND and set TI. This occurs at the 11th divide-by-16
rollover after "write to SUBF".
Reception is initiated by a detected 1-to-0 transition at
RxD. For this purpose RxD is sampled at a rate of 16
times whatever baud rate has been established. When a
transition is detected, the divide-by-16 counter is immediately reset, and 1FFH is written to the input shift register.
At the 7th, 8th and 9th counter states of each bit time,
the bit detector samples the value of R-D. The value accepted is the value that was seen in at least 2 of the 3
samples. If the value accepted during the first bit time is
not 0, the receive circuits are reset and the unit goes
back to looking for another 1-to-O transition. If the start
bit proves valid, it is shifted into the input shift register,
and reception of the rest of the frame will proceed.

As data bits come in from the right, 1s shift out to the
left. When the start bit arrives at the leftmost position in
the shift register (which in Modes 2 and 3 is a 9-bit register), it flags the RX Control block to do one last shift,
load SBUF and RB8, and set RI.

MORE ABOUT MODES 2 AND 3
Eleven bits are transmitted (through TxD), or received
(through RxD): a start bit (0), 8 data bits (LSB first), a
programmable 9th data bit, and a stop bit (1). On
transmit, the 9th data bit (TB8) can be assigned the value of
or 1. On receive, the 9th data bit goes into RB8
in SCON. The baud rate is programmable to either 1132
or 1/64 the oscillator frequency in Mode 2. Mode 3 may
have a variable baud rate generated from Timer 1.

Figures 35 and 36 show a functional diagram of the serial port in Modes 2 and 3. The receive portion is exactly the same as in Mode 1. The transmit portion differs from Mode 1 only in the 9th bit of the transmit shift
register.

The signal to load SBUF and RB8, and to set RI, will be
generated if, and only if, the following conditions are
met at the time the final shift pulse is generated.
1. RI = 0, and
2. Either SM2

or the received 9th data bit

If either of these conditions is not met, the received
frame is irretrievably lost, and RI is not set. If both
conditions are met, the received 9th data bit goes into
RB8, and the first 8 data bits go into SBUF. One bit
time later, whether the above conditions were met or
not, the unit goes back to looking for a 1-to-O transition
at the RxD input.

INTERRUPTS
Transmission is initiated by any instruction that uses
SBUF as a destination register. The "write to SBUF"
signal also loads TB8 into the 9th bit position of the
transmit shift register and flags the TX Control unit that
a transmission is requested. Transmission commences
at SlP1 of the machine cycle following the next roll-over
in the divide-by-16 counter (thus, the bit times are synchronized to the divide-by-16 counter, not to the "write
toSBUF" signal).
The transmission begins with activation of SEND, which
puts the start bit at TxD. One bit time later, DATA is
activated, which enables the output bit of the transmit
shift register to TxD. The first shift pulse occurs one bit
time after that. The first shift clocks a 1 (the stop bit)

February 1989

The 8051 provides 5 interrupt sources. These are shown
in Figure 37. The External Interrupts INTO and INT1
can each be either level-activated or transition-activated,
depending on bits ITO and ITl in Register TCON. The
flags that actually generate. these interrupts are bits lEO
and IE1 in TCON. When an external interrupt is generated, the flag that generated it is cleared by the hardware when the service routine is vectored to only if the
interrupt was transition-activated. If the interrupt was
level activated, then the external requesting source is
what controls the request flag, rather than the on-chip
hardware.

1-34

User's Guide

Signetics Microprocessor Products

8051 Family Hardware Description

Section 1

WRITE

SBUF
TO

---~--~~~~~~--~~~--~--~r-~___~~~

TXD

PHASE 2 CLOCK
(lh fosc)

MODE2

(SMOD IS PCON.?)

L.......-------+l
LOAD
SBUF

RXD

TRANSMIT

~--------------------------------------------~,---

Figure 35. Serial Port Mode 2

February 1989

1-35

User's Guide

Signetics Microprocessor Products

8051 Family Hardware Description

Section 1

TIMER1
OVERFLOW

WRITE

--~---:==:Tr~~~~--~=----'~--~~l_

SBUF
TO

..~

TXD

BIT
DETECTOR

RXD

~
---t WRIT;:;E"T;:;O_S:.B..U"F;--.......-....JL----"L--..JL--Jl--JL--.JL--IL-..JL--.JIL---

-----. miiD
L

SIPl I
TRANSMIT
STOP BIT

RECEIVE

~
RXD BIT DETECTORl sr•• T.OT I
I
D6
L~STOP
BIT
SAMPLE TIMES
~ __~L-_
_"l_ _~~_ _JL_ _'L_~l___~L_ _JL_ _L__ _ _
SHIFT
_________________________________________________________1r____
~RI~

Figure 36. Serial Port Mode 3

February 1989

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Section 1

8051 Family Hardware Description

(MSS)

(LSS)

I EA Ix I x IES IET1 IEX' IETa I EXO I
Symbol

Position
IE.?

EA
~o--------------------~.

1E.6
INTERRUPT
SOURCES

1E.5

~,------------------~.

~2~

EXF2~ --(805~

Figure 37, 8051 Family Interrupt Sources

IE.4

enables or disables the Serial Port
interrupt. If ES = 0, the Serial Port
interrupt is disabled.

ETI

IE.3

enables or disables the Timer 1 Overflow
interrupt. If ETI = 0, the Timer 1 interrupt
is disabled.

EXI

IE.2

enables or disables External Interrupt 1. If
EXI = 0, External Interrupt 1 is disabled.

ETO

IE.l

enables or disables the Timer 0 Overflow
interrupt. If ETO = 0, the Timer 0 interrupt
is disabled.

EXO

IE.O

enables or disables External Interrupt O. If
EXO = 0, External Interrupt 0 is disabled.

Figure 38, Interrupt Enable Register (IE)

(MSS)

IP.6

All of the bits that generate interrupts can be set or
cleared by software, with the same result as though it
had been set or cleared by hardware. That is, interrupts
can be generated or pending interrupts can be canceled
in software.
Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special
Function Register IE (Figure 38). IE also contains a
global disable bit, EA, which disables all interrupts at
once.

(LSS)

IX I X IPS IPT1 IPXl IPTO I PXO I

Symbol Position
IP.?

The Serial Port Interrupt is generated by the logical OR
of RI and TI. Neither of theses flags is cleared by hardware when the service routine is vectored to. In fact, the
service routine will normally have to determine whether
it was RI or TI that generated the interrupt, and the bit
will have to be cleared in software.

Function
reserved
reserved

IP.5

reserved

IP.4

defines the Serial Port Interrupt priority
level. PS-l programs It to the higher
priority level.

PTI

IP.3

defines the Timer 1 Interrupt priority
level. PT1-1 programs It to the higher
priority level.

PXl

IP.2

defines the External Interrupt 1 priority
level. PX1-1 programs It to the higher
priority level.

PTO

IP.l

defines the Timer 0 Interrupt priority
level. PTO-l programs It to the higher
priority level.

PXO

IP.O

defines the External Interrupt 0 priority
level. PXO-l programs It to the higher
priority level.

Figure 39, Interrupt Priority Register (lP)

PRIORITY LEVEL STRUCTURE

February 1989

reserved
reserved

The Timer 0 and Timer 1 Interrupts are generated by
1FO and 1Fl, which are set by a rollover in their respective Timer/Counter registers (except see Timer 0 in
Mode 3). When a timer interrupt is generated, the flag
that generated it is cleared by the on-chip hardware
\\hen the service routine is vectored to.

Each interrupt source can also be individually programmed to one of two priority levels by setting or
clearing a bit in Special Function Register IP (Figure
39). A low-priority interrupt can itself be interrupted by
a high-priority interrupt, but not by another low-priority
interrupt. A high-priority interrupt can't be interrupted
by any other interrupt source.

Function
disables all interrupts. If EA = 0, no
interrupt will be acknowledged. If EA = 1,
each interrupt source is individually
enabled or disabled by setting or clearing
its enable bit.

If two requests of different priority levels are received
simultaneously, the request of higher priority level is
serviced. If requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. Thus within each priority level there is a second priority structure determined
by the polling sequence as follows:

1-37

User's Guide

Signetics Microprocessor Products

8051 Family Hardware Description

Section 1
1.
2.
3.
4.
5.

Source
IEO
TFO
IEI
TFI
RI+TI

Priority Within Level
(highest)

(lowest)

Note that the "priority within level" structure is only used
to resolve simultaneous requests of the same priority level.
The IP register contains a number of unimplemented
bits. IP.?, IP.6 and IP.S are reserved in the 80S1s. User
software should not write Is to these positions, since they
may be used in other 8051 Family products.

Thus the processor acknowledges an interrupt request by
executing a hardware generated LCALL to the appropriate servicing routine. In some cases it also clears the
flag that generated the interrupt, and in other cases it
doesn't. It never clears the Serial Port or Timer 2 flags.
This has to be done in the user's software. It clears an
external interrupt flag (lEO or lEI) only if it was transition-activated. The hardware-generated LCALL pushes
the contents of the Program Counter on to the stack (but
it does not save the PSW) and reloads the PC with an
address that depends on the source of the interrupt being
vectored to, as shown below:
Source
IEO
TFO
IEI
TFI
RI+TI

HOW INTERRUPTS ARE HANDLED
The interrupt flags are sampled at SSP2 of every machine cycle. The samples are polled during the following
machine cycle. If one of the flags was in a set condition
at S5P2 of the preceding cycle, the polling cycle will
find it and the interrupt system will generate an LCALL
to the appropriate service routine, provided this
hardware-generated LCALL is not blocked by any of the
following conditions:

1. An interrupt of equal or higher priority level is already in progress.
2. The current (polling) cycle is not the final cycle in
the execution of the instruction in progress.
3. The instruction in progress is RETI or any write to
the IE or IP registers.
Any of these three conditions will block the generation of
the LCALL to the interrupt service routine. Condition 2
ensures that the instruction in progress will be completed
before vectoring to any service routine. Condition 3 ensures that if the instruction in progress is RETI or any
access to IE or IP, then at least one more instruction
will be executed before any interrupt is vectored to.
The polling cycle is repeated with each machine cycle,
and the values polled are the values that were present at
SSP2 of the previous machine cycle. Note than that if an
interrupt flag is active but not being responded to for
one of the above conditions, if the flag is not still active
when the blocking condition is removed, the denied interrupt will not be serviced. In other words, the fact that
the interrupt flag was once active but not serviced is not
remembered. Every polling cycle is new.
The polling cycle/LCALL sequence is illustrated in Figure 40.
Note that if an interrupt of higher priority level goes active prior to SSP2 of the machine cycle labeled C3 in
Figure 40, then in accordance with the above rules it
will be vectored to during CS and C6, without any instruction of the lower priority routine having been executed.

February 1989

Vector Address
0003H
OOOBH
0013H
OOlEH
0023H

Execution proceeds from that location until the RETI instruction is encountered. The RETI instruction informs
the processor that this interrupt routine is no longer in
progress, then pops the top two bytes from the stack and
reloads the Program Counter. Execution of the interrupted program continues from where it left off.
Note that a simple RET instruction would also have returned execution to the interrupted program, but it would
have left the interrupt control system thinking an interrupt was still in progress.
EXTERNAL INTERRUPTS
The external sources can be programmed to be levelactivated or transition-activated by setting or clearing bit
ITI or ITO in Register TCON. If ITx = 0, external interrupt x is triggered by a detected low at the INTx pin.
If ITx = 1, external interrupt x is edge triggered. In this
mode if successive samples of the INTx pin show a high
in one cycle and a low in the next cycle, interrupt request flag lEx in TCON is set. Flag bit lEx then requests the interrupt.
Since the external interrupt pins are sampled once each
machine cycle, an input high or low should hold for at
least 12 oscillator periods to ensure sampling. If the external interrupt is transition-activated, the external
source has to hold the request pin high for at least one
cycle, and then hold it low for at least one cycle. This is
done to ensure that the transition is seen so that interrupt request flag lEx will be set. lEx will be automatically cleared by the CPU when the service routine is
called.
If the external interrupt is level-activated, the external
source has to hold the request active until the requested
interrupt is actually generated. Then it has to deactivate
the request before the interrupt service routine is completed, or else another interrupt will be generated.

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Section 1

--c.--..

••· .... ·---C1-_.-II_.
_ _ _ C2 _ _••- t I _ - - C 3 - -.......
1 ••
I S5P2 I

..,I....
---C5--·····

·······lJL_n..fL_-\,~_-'-___''\u,_---''--_''\l~_---'-_ __

fYt

INTERRUPT
GOES
ACTIVE

INTERRUPT
LATCHED

INTERRUPTS
ARE POLLED

LONG CALL TO
INTERRUPT
VECTOR ADDRESS

INTERRUPT ROUTINE

This is the fastest possible response when C2 is the final cycle of an instruction other than RETI or an access to IE or IP.

Figure 40. Interrupt Response Timing Diagram

RESPONSE TIME
The INfO and INT1 levels are inverted and latched into
lEO and IE1 at S5P2 of every machine cycle. The values
are not actually polled by the circuitry until the next
machine cycle. If a request is active and conditions are
right for it to be acknowledged, a hardware subroutine
call to the requested service routine will be the next instruction to be executed. The call itself takes two cycles.
Thus, a minimum of three complete machine cycles
elapse between activation of an external interrupt request
and .the beginning of execution of the first instruction of
the service routine. Figure 40 shows interrupt response
timings.
A longer response time. would result if the request is
blocked by one of the 3 previously listed conditions. If an
interrupt of equal or higher priority level is already in
progress, the additional wait time obviously depends on
the nature of the other interrupt's service routine. If the
instruction in progress is not in its final cycle, the additional wait time cannot be more the 3 cycles, since the
longest instructions (MUL and DIY) are only 4 cycles
long, and if the instruction in progress is RETI or an
access to IE or IP, the additional wait time cannot be
more than 5 cycles (a maximum of one more cycle to
complete the instruction in progress, plus 4 cycles to
complete the next instruction if the instruction is MUL
or DIV).
Thus, in a single-interrupt system, the response time is
always more than 3 cycles and less than 9 cycles.

SINGLE-STEP OPERATION
The 8051 interrupt structure allows single-step execution
with very little software overhead. As previously noted, an
interrupt request will not be responded to while an interrupt of equal priority level is still in progress, nor will it
be responded to after RETI until at least one other instruction has been executed. Thus, once an interrupt routine has been entered, it cannot be re-entered until at
least one instruction of the interrupted program is exe-

February 1989

cuted. One way to use this feature for single-step operation is to program one of the external interrupts (e.g.
INfO) to be level-activated. The service routine for the
interrupt will terminate with the following code:
JNB

m
RETI

P3.2,$
P3.2,$

;Wait Till INfO Goes High
;Wait Till INfO Goes Low
;Go Back and Execute One Instruction

Now if the INfO pin, which is also the P3.2 pin, is held
normally low, the CPU will go right into the External
Interrupt 0 routine and stay there until INTO is pulsed
(from low to high to low). Then it will execute RETI, go
back to the task program, execute one instruction, and
immediately re-enter the External Interrupt 0 routine to
await the next pulsing of P3.2. One step of the task program is executed each time P3.2 is pulsed.
.

RESET
The reset input is the RST pin, which is the input to a
Schmitt Trigger. A reset is accomplished by holding the
RST pin high for at least two machine cycles (24 oscillator periods), while the oscillator is running. The CPU
responds by generating an internal reset, with the timing
shown in Figure 41.
The external reset signal is asynchronous to the internal
clock. The RST pin is sampled during State 5 Phase 2
of every machine cycle. The port pins will maintain their
current activities for 19 oscillator periods after a logic 1
has been sampled at the RST pin; that is, for 19 to 31
oscillator periods after the external reset signal has been
applied to the RST pin.
The internal reset algorithm writes Os to all the SFRs
except the port latches, the Stack Pointer, and SBUF.
The port latches are initialized to FFH, the Stack Pointer to 07H, and SBUF is indeterminate. Table 11 lists the
SFR reset values. The internal RAM is not affected by
reset. On power up the RAM content is indeterminate.

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Section 1

r--- 12 OSC. PERIODS ----1
I 55 I 56 I 51 I 52 I S3 I 54 I S5 I S6 I S 1 I S2 I S3 I S4 I S5 I 56 I S 1 I 52 I S3 I S4 I
RST:

~/ 1111111117~

SAMPLE RST

CINTERNAL RESET SIGNAL
-

SAMPLE RST

ALE:

PSEN:

po:
I

- 1 1 OSC. PERIODS -'"',,>--------19 OSC. PERIODS - - - - - -

Figure 41. Reset Timing
Table 11. 8051 SFR Reset Values
Register

PC
ACC
B

PSW
SP
DPTR
PO-P3
IP
IE
TMOD
TCON
THO
TLO
TH1
TL1
SCON
SBUF
PCON (HMOS)
PCON (CHMOS)

Reset Value

OOOOH
OOH
OOH
OOH
07H
OOOOH
FFH
XXXOOOOOB
OXXOOOOOB
OOH
OOH
OOH
OOH
OOH
OOH
OOH
Indeterminate
OXXXXXXXB
OXXXOOOOB

POWER-ON RESET
An automatic reset can be obtained when Vee is turned
on by connecting the RST pin to Vee through a 1O,.u
capacitor and to Vss through an 8.2K resistor, providing
the Vee rise time does not exceed a millisecond and the
oscillator start-up time does not exceed 10 milliseconds.
This power-on reset circuit is shown in Figure 42. The
CHMOS devices do not require the 8.2K pulldown resistor, although its presence does no harm.

When power is turned on, the circuit holds the RST pin
high for an amount of time that depends on the value of
the capacitor and the rate at which it charges. To ensure
a good reset, the RST pin must be high long enough to
allow the oscillator time to start-up (normally a few
msec) plus two machine cycles.

February 1989

Note that the port pins ,viii be in a random state until
the oscillator has started and the internal reset algorithm
has written Is to them.
With this circuit, reducing Vee quickly to 0 causes the
RST pin voltage to momentarily fall below OV. However,
this voltage is internally limited, and will not harm the
device.

POWER-SAVING MODES OF OPERATION
For applications where power consumption is critical the
CHMOSversion provides power reduced modes of operation as a standard feature. The power down mode in
HMOS devices is no longer a standard feature.
CHMOS POWER REDUCTION MODE

CHMOS versions have two power reducing modes, Idle
and Power Down. The input through which backup power
is supplied during these operations is Vee. Figure 43
shows the internal circuitry which implements these features. In the Idle modes (IDL = 1), the oscillator continues to run and the Interrupt, Serial Port, and Timer
blocks continue to be clocked, but the clock signal is
gated off to the CPU. In Power Down (PD = 1), the oscillator is frozen. The Idle and Power Down Modes are
activated by setting bits in Special Function Register
PCON. The address of this register is 87H. Figure 44
details its contents.
In the HMOS devices the PCON register only contains
SMOD. The other four bits are implemented only in the
CHMOS devices. User software should never write Is to
unimplemented bits, since they may be used in other
8051 Family products.

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8051 Family Hardware Description
(MSB)
SMOO

vee

(lSB)

I I I

IOl

POlltlon

Name and Function

SMOD

PCON.7

Double Baud rata bit. When set to a 1
and Timer 1 is used to generate baud
rate, and the Serial Port is used in
modes 1, 2, or 3.

PCON.S

(Reserved)

PCON.S

(Reserved)

PCON.4

(Reserved)

vee t-8051

8.2K!!

GFO

Symbol

10u'_r-

RST

GF1

GFl

PCON.3

General-purpose flag bit.

GFO

PCON.2

General-purpose flag bit.

PCON.l

Power Down bit. Setting this bit

activates power down operation.
IDL

VSS

PCON.O

Idle mode bit. Setting this bit activates
idle mode operation.

If 1 s are written to PO and IDL at the same time, PO takes
precedence. The reset value of PCON Is (OXXXOOOO).

-l=-

In the H MaS devices the PCON register only contains
SMOD. The other four bits are Implemented only in the
CHMOS devices. User software should never write 1s to
unimplemented bits, since they may be used in future

Figure 42. Power On Reset Circuit

products.

Figure 44. Power Control (PCON) Register
There are two ways to terminate the Idle. Activation of
any enabled interrupt will cause PCON.O to be cleared
by hardware, terminating the Idle mode. The interrupt
will be serviced, and following RETI, the next instruction
to be executed will be the one following the instruction
that put the device into Idle.

XTAl 2

XTAL 1

INTERRUPT.

f-......-<>SERIAL PORT,
TIMER BLOCKS

CPU

Figure 43. Idle and Power Down Hardware

IDLE MODE
An instruction that sets PCON.O causes that to be the
last instruction executed before going into the Idle
mode, the internal clock signal is gated off to the CPU
but not to the Interrupt, Timer and Serial Port functions.
The CPU status is preserved in its entirety; the Stack
Pointer, Program Counter, Program Status Word, Accumulator, and all other registers maintain their data during Idle. The port pins hold the logical states they had at
the time Idle was activated. ALE and PSEN hold at logic high levels.

February 1989

The flag bits GFO and GF1 can be used to give an indication if an interrupt occurred during normal operation
or during an Idle. For example, an instruction that activates Idle can also set one or both flag bits. When Idle
is terminated by an interrupt, the interrupt service routine can examine the flag bits. The other way of terminating the Idle mode is with a hardware reset. Since the
clock oscillator is still running, the hardware reset needs
to be held active for only two machine cycles (24 oscillator periods) to complete the reset.
The signal at the RST pin clears the IDL bit directly
and asynchronously. At this time the CPU resumes program execution from where it left off; that is, at the instruction following the one that invoked the Idle Mode.
A, shown in Figure 41, two or three machine cycles of
program execution may take place before the internal
reset algorithm takes control. On-chip hardware inhibits
access to the internal RAM during this time, but access
to the port pins is not inhibited. To eliminate the possibility of unexpected outputs at the port pins, the instruction following the one that invokes Idle should not be one
that writes to a port pin or to external Data RAM.

POWER DOWN MODE
An instruction that sets PCON.1 causes that to be the
last instruction executed before going into the Power
Down mode. In the Power Down mode, the on-chip oscillator is stopped. With the clock frozen, all functions
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Section 1

Vee is restored to its normal operating level, and must
be held active long enough to allow the oscillator to restart and stabilize (normally less than lOmsec).

are stopped, the contents of the on-chip RAM and Special Function Registers are maintained. The port pins
output the values held by their respective SFRs. The
ALE and PSEN output are held low.

THE ON-CHIP OSCILLATORS
The only exit from Power Down is a hardware reset.
Reset redefines all the SFRs, but does not change the
on-chip RAM.

HMOS Versions
The on-chip oscillator circuitry for the HMOS (-I and
-II) members of the 8051 family is a single stage linear
inverter (Figure 45), intended for use as a crystalcontrolled, positive reactance oscillator (Figure 46). In
this application the crystal is operated in its fundamental
response mode as an inductive reactance in parallel
resonance with capacitance external to the crystal.

In the Power Down mode of operation, Vee can be reduced to as low as 2V. Care must be taken, however, to
ensure that Vee is not reduced before the Power Down
mode is invoked, and that Vee is restored to its normal
operating level, before the Power Down mode is terminated. The reset that terminates Power Down also frees
the oscillator. The reset should not be activated before

Vee

TO INTERNAL

nMlNGCKTS
XTAL2
XTAL1

SUBST.

Figure 45. On-Chip Oscillator In the HMOS Version of the 8051 Family

TO INTERNAL
nMINGCKTS

Vu
Il0l1

XTAU-----_ _-r---QUARTZ CRYSTAL
OR CERAMIC RESONATOR

Figure 46. Using the HMOS On-Chip Oscillator

February 1989

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8051 Family Hardware Description

The crystal specifications and capacitance values (C1
and C2 in Figure 46) are not critical. 30pF can be used
in these positions at any frequency with good quality crystals. A ceramic resonator can be used in place of the
crystal in cost-sensitive applications. When a ceramic
resonator is used, C1 and C2 are normally selected to
be of somewhat higher values, typically, 47pF. The manufacturer of the ceramic resonator should be consulted for
recommendation on the values of these capacitors.
To drive the HMOS parts with an external clock source,
apply the external clock signal to XTAL2, and ground
XTAL1, as shown in Figure 47. A pullup resistor may be
used (to increase noise margin), but is optional if VOH
of the driving gate exceeds the VIH minimum specification of XTAL.

when a ceramic resonator is used.
To drive the CHMOS parts with an external clock
source, apply the external clock signal to XTAL1, and
leave XTAL2 float, as shown in Figure 50.
The reason for this change from the way the HMOS part
is driven can be seen by comparing Figures 46 and 48.
In the HMOS devices the internal timing circuits are
driven by the signal at XTZL2. In the CHMOS devices
the internal timing circuits are driven by the signal at
XTALL

INTERNAL TIMING
Figures 51 through 54 show when the various strobe and
port signals are clocked internally. The figures do not
show rise and fall times of the signals, nor do they show
propagation delays between the XTAL2 signal and events
at other pins.
Rise and fall times are dependent on the external
loading that each pin must drive. They are often taken to
be something in the neighborhood of 10nsec, measured
between 0.8V and 2.0V.

Vee
1011

:>0-.....--4 XTALI
XTAU

Propagation delays are different for different pins.
given pin they vary with pin loading, temperature,
and manufacturing lot. If the XTAL2 waveform is
as the timing reference, prop delays may vary from
125nsec.

For a
Vee,
taken
25 to

TTL
GATE

Vss

wmt

TOTIIIoPOLE
OUTPUT

Figure 47. Driving the HMOS 80S1 Family
Parts with an External Clock

CHMOS VERSIONS
The on-chip oscillator circuitry for the 8OC51BH, shown
in Figure 48, consists of a single stage linear inverter
intended for use as a. crystal-controlled, positive reactance oscillator in the same manner as the HMOS parts.
However, there are some important differences.
One difference is that the SOC51BH is able to turn off
its oscillator under software control (by writing a 1 to
the PD bit in PCON). Another difference is that, in the
8OC51BH, the internal clocking circuitry is driven by the
signal at XTAL1, whereas in the HMOS versions it is by
the signal at XTAL2.
The ~eedback resistor Rf in Figure 48 consists of paralleled n-and p-channel PETs controlled by the PD bit,
such that Rf is opened when PD - 1. The diodes D1 and
D2, which act as clamps to Vee and Vss, are parasitic
to the Rf FETs. The oscillator can be used with the
same external components as the HMOS versions, as
shown in Figure 49. Typically, C1 = C2 - 30pF when
the feedback element is a quartz, and C1 - C2 - 47pF
February 1989

The AC Timings section of the data sheets do not reference any timing to the XTAL2 waveform. Rather, they
relate the critical edges of control and input signals to
each other. The timings published in the data sheets include the effects of propagation delays under the specified test conditions.

8051 PIN DESCRIPTIONS
ALEIPROG: Address Latch Enable output pulse for
latching the low byte of the address during accesses to
external memory. ALE is emitted at a constant rate of
116 of the oscillator frequency, for external timing or
clocking purposes, even when there are no accesses to
external memory. (However, one ALE pulse is skipped
during each access to external Data Memory.) This pin
is also the program pulse (PROG during EPROM programming).
PSEN: Program Store Enable is the read strobe to external Program Memory. When the device is executing
out of external Program Memory, PSEN is activated
twice each machine cycle (except that two PSEN activations are skipped during accesses to external Data
Memory). PSEN is not activated when the device is executing out of internal Program Memory.

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Section 1

VCC

TO INTERNAL
nMING CKTS

Figure 48. On-Chip Oscillator Circuitry in the CHMOS Versions of the 8051 Family
VCC
TO INTERNAL
nMINGCKTS

Vss
XTAL2·-----

1OC51

_..-,..--QUARTZ CRYSTAL
OR CERAMIC
RESONATOR

Figure 49. Using the CHMOS On-Chip Oscillator

XTALI

EAlVpp: When EA is held high the CPU executes out of
internal Program Memory (unless the Program Counter
exceeds OFFFH in the 8051 or 80CS1). Holding EA low
forces the CPU to execute out of external memory regardlessof the Program Counter value. In the 8031AH,
EA must be externally wired low. In the EPROM de~
vices, this pin also receives the programming supply
voltage (Vpp) during EPROM programming.

VSS

XTAL1: Input to the inverting oscillator amplifier.

8OC51

XTAL2

EXTERNAL
OSCILLATOR
SIGNAL

CMOS GATE

....

XTAL2: Output from the inverting oscillator amplifier .

Figure 50. Driving the CHMOS Family
Parts with an External Clock Source

February 1989

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Section 1

Port 3: Port 3 is an 8-bit bidirectional 110 port with internal pultups. It also serves the functions of various
special features of the 8051 Family as follows:

Port 0: Port 0 is an 8-bit open drain bidirectional port.
As an open drain output port, it can sink eight LS TIL
loads. Port 0 pins that have 1s written to them float, and
in that state will function as high impedance inputs. Port
o is also the multiplexed low-order address and data bus
during accesses to external memory. In this application
it uses strong internal pullups when emitting 1s. Port 0
also emits code bytes during program verification. In
that application, external pullups are required.

Port Pin
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7

Port 1: Port 1 is an 8-bit bi-directional 110 port with internal pullups. Port 1 pins that have Is written to them
are pulled high by the internal pullups, and in that state
can be used as inputs. As inputs, port 1 pins that are
externally being pulled low will source current because
of the internal pultups.

Alternate Function
RxD (serial input port)
TxD (serial output port)
INTO (external interrupt 0)
INT1 (external interrupt 1)
TO (timer 0 external input)
Tl (timer 1 external input)
WR (external data memory write strobe)
RD (external data memory read strobe)

V cc: Supply voltage
V ss: Circuit ground potential

Port 2: Port 2 is an 8-bit bidirectional 1/0 port with internal pullups. Port 2 emits the high-order address byte
during accesses to external memory that use 16-bit addresses. In this application, it uses the strong internal
pullups when emitting 1s.

STATE 1 STATE

~I~

21 STATE

~I~

41 STATE 'ISTATE 'ISTATE 1 STATE
~I~ ~I~ ~I~ ~I~ ~I~

STATE

XTAU:

ALI:

PCHOUT

Figure 51. External Program Memory Fetches

February 1989

1-45

PCHOUT

Signetics Microprocessor Products

User's Guide

8051 Family Hardware Description

Section 1

STATt:

41 STATt: 51 STATt: 61 STATt:

~1P2

STATE

21 STATE 31 STATE 41 STATE 51

~1P2

~1P2 ~1P2

~1P2

XTAL2:

ALE:

iii:

PO:

P2:

PCHOR

PCH OR

DPH OR P2 SFR OUT

P2SFR

Figure 52. External Data Memory Read Cycle

I~1P241 ~1P251 ~1P261 ~1P2'I ~1P221 ~1P231 ~1P241 ~1P251
STATE

STATE

It.ATE

STATE

XTAL2:

ALE:

WA:

FOut ~
PCL OUT IF

IS EXTERNAL

DPL OR AI
OUT

PO:

PCH OR
P2SFR

DATA OUT

OPH OR P2 SFR OUT

PCH OR
P2SFR

Figure 53. External Data Memory Write Cycle

February 1989

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Signetics Microprocessor Products

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Section 1

8051 Family Hardware Description

I~1P2

STATE 41STATE

SI STATE II/STATE 1 ISTATE 2/STATE 3/STATE 41 STATE 51

~1P2 ~1P2 ~1P2 ~1P2 ~1P2 ~1P2 ~1P2

XTALI:

'P1

INPUTS SAMPLeD:

PO,P1~

P2,

P2, P3, RST

MaY PORT, IRC:

OLD DATA

P3, R8T=::rl.-

NEW DATA

81I11ALPORT

IHIFTCLOCK
(MODE 0)

~ RXD PIN SAMPLED

Figure 54. Port Operation

February 1989

1-47

RXD SAMPLED --l

f--

User's Guide

Signetics Microprocessor Products

Section 1

8051 Family Programmer's Guide and Instruction Set
1.

PROGRAMMER'S GUIDE AND
INSTRUCTION SET
MEMORY ORGANIZATION
PROGRAM MEMORY
The 8051 has separate address spaces for program and
data memory. The Program memory can be up to 64K
bytes long. The lower 4K can reside on-chip. Figure 55
shows a map of the 8051 program memory.
The 8051 can address up to 64K bytes of data memory
to the chip. The MOVX instruction is used to access the
external data memory.
The 8051 has 128 bytes of on-chip RAM, plus a number
of Special Function Registers (SFRs). The lower 128
bytes of RAM can be accessed either by direct addressing (MOY data addr) or by indirect addressing (MOY
@Ri). Figure 56 shows the Data Memory organization.
DIRECT AND INDIRECT ADDRESS AREA
The 128 bytes of RAM which can be accessed by both
direct and indirect addressing can be divided into three
segments as listed below and shown in Figure 57.

Register Banks 0-3: Locations 0 through IFH (32
bytes). The device after reset defaults to register
bank O. To use the other register banks, the user
must select them in software. Each register bank
contains eight I-byte registers 0 through 7. Reset initializes the stack pointer to location 07H and it is
incremented once to start from location 08H which
is the first register (RO) of the second register bank.
Thus in order to use more than one register bank,
the SP should be initialized to a different location of
the RAM where it is not used for data storage. (i.e.
the higher part of the RAM).
2. Bit Addressable Area: 16 bytes have been assigned
for this segment, 20H-2FH. Each one of the 128
bits of this segment can be directly addressed
(0-7FH). The bits can be referred to in two ways
both of which are acceptable by most assemblers.
One way is to refer to their address (i.e. 0-7FH).
The other way is with reference to bytes 20H to
2FH. Thus, bits 0-7 can also be referred to as bits
20.0-20.7, and bits 8-FH are the same as
21.0-21.7, and so on. Each of the 16 bytes in this
segment can also be addressed as a byte.
3. Scratch Pad Area: 30H through 7FH are available to
the user as data RAM. However, if the data pointer
has been initialized to this area, enough bytes should
be left aside to prevent SP data destruction.
Figure 56 shows the different segments of the on-chip
RAM.

~r-----------------,

FFFFr-------------------~

&OK
BYTES

EXTERNAL
14K
BYTES

---OR---~~

EXTERNAL
1~~

__________________~

AND

~ooooFl________
_

4K
__
BYTES
__________
INTERNAL

~
oooo~------

Figure 55. 8051 Program Memory

February 1989

1-48

____________

User's Guide

Signetics Microprocessor Products

8051 Family Programmer's Guide and Instruction Set

Section 1

~~----------------~

INTERNAL

FF,..-----------------,
SFR.

14K
BYTES

DIRECT
ADDRESSING
ONLY

EXTERNAL

7Fr-----------------~

---AND--'"

DIRECT.
INDIRECT
ADORESBING

~L-----------------J

~~-------~

Figure 56. 8051 Data Memory

1, .......
.--------

ellyln

------I~~II
7F

..
..
70

IF
IT

SCRATCH

PAD
17

AREA

•
40

••• 7F

BIT

ADDRESBABLE
20

0 ...

BEGMENT

IANIC8

Figure 57. 128 Bytes of RAM Direct and Indirect Addressable
February 1989

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8051 Family Programmer's Guide and Instruction Set

Section 1

Table 13. Contents of SFRs Arter a Reset

Table 12. 8051, 80CSI Special Funcdon Registers
Symbol
*ACC
·B
·PSW
SP
DPTR
DPL
DPH

·PO
·P1
*P2
*P3

•

Name
Accumulator
B Register
Program Status Word
Stack Pointer
Data Pointer 2 Bytes
Low Byte
High Byte
Port 0
Port 1
Port 2
Port 3
Interrupt Priority Control
Interrupt Enable Control
Timer/counter Mode Control
Timer/counter Control
Timer/counter 0 High Byte
Timer/counter 0 Low Byte
Timer/counter 1 High Byte
Timer/counter 1 Low Byte
Serial Control
Serial Data Buffer
Power Control

*IP
*IE
TMOD
*TCON
THO
TLO
TH1
TLI
·SCON
SBUF
PCON
= Bit addressable

Value In Binary

Address
OEOH
OFOH
ODOH
81H
82H
83H
80H
90H
OAOH
OBOH
OB8H
OA8H
89H
88H
8CH
8AH
8DH
8BH
98H
99H
87H

x• =

OOOOOOOO
OOOOOOOO
00000000
00000111
OOOOOOOO
00000000
11111111
11111111
11111111
11111111
xxxOOOOO
OXXOOOOO
00000000
00000000
00000000
00000000
OOOOOOOO
OOOOOOOO
OOOOOOOO
Indeterminate
HMOSOxxxxxxx
CHMOS OXXXOOOO

Undefined
Bit addressable

I BY1U

FF
F7

EO
DB
DO
CB
CO
88
BO
A8

AO
98

90
88
80

ACC

PSW

D7
CF

C7
BF

IP
P3
IE
P2
SCON
P1
TCON
PO

AF
A7
9F

SBUF

97
TMOD

TLo

TL1

SIt

DPL

DPH

THO

POON

T
m..ABLE
Figure 58. 8051 SFR Memory Map

February 1989

TH1

1-50

User's Guide

Signetics Microprocessor Products

8051 Family Programmer's Guide and Instruction Set

Section 1

Those SFRs that have their bits assigned for various functions are listed in this section. A brief description of each bit
is provided for quick reference. For more detailed information refer to the Architecture Chapter of this book.

PSW: PROGRAM STATUS WORD. BIT ADDRESSABLE.
CY

CY
AC
Fa
RSI
RSa
OV

PSW.7
PSW.6
PSW.5
PSW.4
PSW.3
PSW.2
PSW.I
psw.a

RS1

Rsa

Carry Flag.
Auxiliary Carry Flag.
Flag a available to the user for general purpose.
Register Bank selector bit I (SEE NOTE I).
Register Bank selector bit a (SEE NOTE I).
Overflow Flag.
Usable as a general purpose flag.
Parity flag. Set/cleared by hardware each instruction cycle to indicate an odd/even number of
'I' bits in the accumulator.

NOTE:
1.

The value presented by

RSO

and

RS1

selects the corresponding register bank.

RS1

RSO

Address

a
a
1
1

a
1
a
1

a
1
2
3

OOH-07H
OBH-OFH
10H-17H
1BH-1FH

PCON: POWER CONTROL REGISTER. NOT BIT ADDRESSABLE.
SMOD

GF1

GFO

IDL

SMOD Double baud rate bit. If Timer I is used to generate baud rate and SMOD
when the Serial Port is used in modes I, 2, or 3.
Not implemented, reserved for future use.'
Not implemented, reserved for future use.'
Not implemented, reserved for future use.'
GF I
General purpose flag bit.
GFa
General purpose flag bit.

I, the baud rate is doubled

Power Down bit. Setting this bit activates Power Down operation in the 8aC5IBH. (Available only in
CHMOS).

IDL

Idle Mode bit. Setting this bit activates Idle Mode operation in the 8aC51BH. (Available only in CHMOS).

If Is are written to PD and IDL at the same time, PD takes precedence.

·User software should not write 1s to reserved bits. These bits may be used in future 8051 products to invoke new
features.

February 1989

1-51

User's Guide

Signetics Microprocessor Products

8051 Family Programmer's Guide and Instruction Set

Section 1
INTERRUPTS:

In order to use any of the interrupts in the 8051 Family, the following three steps must be taken.

1. Set the EA (enable all) bit in the IE register to 1.
2. Set the corresponding individual interrupt enable bit in the IE register to 1.
3. Begin the interrupt service routine at the corresponding Vector Address of that interrupt. See
Table below.

Interrupt
Source

Vector
Address

lEO
TFO
IE1
TF1
RI & TI

0OO3H
OOOSH
0013H
001SH
0023H

In addition, for external interrupts, pins INTO and INTI (P3.2 and P3.3) must be set to I, and depending on whether
the interrupt is to be level or transition activated, bits ITO or ITI in the TCON register may need to be set to 1.
ITx

= 0 level activated

ITx

1 transition activated

IE: INTERRUPT ENABLE REGISTER. BIT ADDRESSABLE.
If the bit is 0, the corresponding interrupt is disabled. If the bit is I, the corresponding interrupt is enabled.
EA
EA

IE.7
IE.6
IE.S

ES
ETI
EXI
ETO
EXO

IE.4
IE.3
IE.2
IE. I

lE.O

ET1

ETO

EX1

EXO

Disables all interrupts. If EA = 0, no interrupt will be acknowledged. If EA = 1, each interrupt
source is individually enabled or disabled by setting or clearing its enable bit.
Not implemented, reserved for future use.'
Not implemented, reserved for future use.'
Enable or disable the serial port interrupt.
Enable or disable the Timer I overflow interrupt.
Enable or disable External Interrupt 1.
Enable or disable the Timer 0 overflow interrupt.
Enable or disable External Interrupt O.

.User software should not write Is to reserved bits. These bits may be used in future 8051 products
to invoke new features.

February 1989

1-52

User's Guide

Signetics Microprocessor Products

Section 1

8051 Family Programmer's Guide and Instruction Set

ASSIGNING HIGHER PRIORITY TO ONE OR MORE INTERRUPTS:

In order to assign higher priority to an interrupt the corresponding bit in the IP register must be set to L

I··,

Remember that while an interrupt service is in progress, it cannot be interrupted by a lower or same level interrupt.

PRIORITY WITHIN LEVEL:
Priority within level is only to resolve simultaneous requests of the same priority level
From high to low, interrupt sources are listed below:

lEO
TFO
lEI

TFI
RI or TI

IP: INTERRUPT PRIORITY REGISTER. BIT ADDRESSABLE.
If the bit is 0, the corresponding interrupt has a lower priority and if the bit is 1 the corresponding interrupt has a
higher priority.

1- I

PT1

PX1

PTO

PXO

IP.7 Not implemented, reserved for future use,·
IP. 6 Not implemented, reserved for future use.·
IP.5 Not implemented, reserved for future use.·
PS
PT I
PX I
PTO
PXO

IP. 4
IP. 3
IP. 2
IP. I
IP. 0

Dermes the Serial Port interrupt priority level.
Defines the Timer I interrupt priority level.
Defines External Interrupt I priority level.
Defines the Timer 0 interrupt priority level.
Defines the External Interrupt 0 priority level.

·User software should not write Is to reserved bits. These bits may be used in future 8051 products to invoke
new features.

February 1989

1-53

User's Guide

Signetics Microprocessor Products

8051 Family Programmer's Guide and Instruction Set

Section 1

TCON: TIMER/COUNTER· CONTROL REGISTER. BIT ADDRESSABLE.
[

TF1

TFI
TRI
TFO
TRO
lEI
ITt
lEO

ITO

TFO

TR1

TRO

IE1

lEO

IT1

ITO

TCON. 7 Timer 1 overflow flag. Set by hardware when the Timer/Counter 1 overflows. Cleared by hardware as processor vectors to the interrupt service routine.
TCON. 6 Timer 1 run control bit. Set/cleared by software to turn Timer/Counter ION/OFF.
TCON. 5 Timer 0 overflow flag. Set by hardware when the Timer/Counter 0 overflows. Cleared by hardware as processor vectors to the service routine.
TCON. 4 Timer 0 run control bit. Set/cleared by software to tum Timer/Counter 0 ON/OFF.
TCON.3 External Interrupt 1 edge flag. Set by hardware when External Interrupt edge is detected.
Cleared by hardware when interrupt is processed.
TCON. 2 Interrupt 1 type control bit. Set/cleared by software to specify falling edge/low level triggered
External Interrupt.
TCON. 1 External Interrupt 0 edge flag. Set by hardware when External Interrupt edge detected. Cleared
by hardware when interrupt is processed.
TCON. 0 Interrupt 0 type control bit. Set/cleared by software to specify falling edge/low level triggered
External Interrupt.

TMOD: TIMER/COUNTER MODE CONTROL REGISTER. NOT BIT
ADDRESSABLE.

I\0 GATE
GATE

CIT
Ml
MO

CIT

GATE

CIT

)\:

MO
)

TIMER 1
TIMER 0
When TRx (in TCON) is set and GATE = 1, TIMER/COUNTERx will run only while INTx pin is high
(hardware control). When GATE = 0, TIMER/COUNTERx will run only while TRx = 1 (software
control).
Timer or Counter selector. Cleared for Timer operation (input from internal system clock). Set for Counter operation (input from Tx input pin).
Mode selector bit. (NOTE 1)
Mode selector bit. (NOTE 1)

NOTE 1:

o
o

February 1989

o
1

Operating Mode
13-bit Timer (8048 compatible)
1
16-bit Timer/Counter
2
8-bit Auto-Reload Timer/Counter
3
(Timer 0) TLO is an 8-bit Timer/Counter controlled by the standard Timer 0
control bits, THO is an 8-bit Timer and is controlled by Timer 1 control bits.
3
(Timer 1) Timer/Counter 1 stopped.

1-54

User's Guide

Signetics Microprocessor Products

Section 1

8051 Family Programmer's Guide and Instruction Set

TIMER SET-UP
Tables 14 through 17 give some values for TMOD which can be used to set up Timer 0 in different modes.

,-i

It is assumed that only one timer is being used at a time. If it is desired to run Timers 0 and I simultaneously, in any
mode, the value in TMOD for Timer 0 must be ORed with the value shown for Timer 1 (Table 16 and 17).
For example, if it is desired to run Timer 0 in mode I GATE (external control), and Timer I in mode 2 COUNTER,
then the value that must be loaded into TMOD is 69H (09H from Table 14 ORed with 60H from Table 17).
Moreover, it is assumed that the user, at this point, is not ready to tum the timers on and will do that at a different
point in the program by setting bit TRx (in TCON) to 1.

TIMER/COUNTER 0

AsaTlmer:

Table 14

TMOD
MODE

TIMER 0
FUNCTION

INTERNAL
CONTROL
(NOTE 1)

EXTERNAL
CONTROL
(NOTE 2)

0
1
2
3

13-bit Timer
1S-bitTimer .
8-bit Auto-Reload
two 8-bit Timers

OOH
01H
02H
03H

08H
09H
OAH
OSH

As a Counter:
Table 15

TMOD
MODE

0
1
2

COUNTER 0
FUNCTION

INTERNAL
CONTROL
(NOTE 1)

EXTERNAL
CONTROL
(NOTE 2)

13-bit Timer
1S-bit Timer
8-bit Auto-Reload
one 8-bit Counter

04H
05H
OSH
07H

OCH
OOH
OEH
OFH

NOTES:
1. The Timer is turned ON/OFF by setting/clearing bit TAO in the software.
2. The Timer is turned ON/OFF by the 1 to 0 transition on iN'i'O (P3.2) when TAO = 1
(hardware control).

February 1989

1-55

Signetics Microprocessor Products

Section 1

User's Guide

8051 Family Programmer's Guide and Instruction Set

TIMER/COUNTER 1

As a Timer:

Table 16

TMOD
MODE

TIMER 1
FUNCTION

INTERNAL
CONTROL
(NOTE 1)

EXTERNAL
CONTROL
(NOTE 2)

0
1
2
3

13-blt Timer
16-bit Timer
8-bit Auto-Reload
does not run

OOH
10H
20H
30H

80H
90H
AOH
BOH

As a Counter:
Table 17

TMOD
MODE

COUNTER 1
FUNCTION

INTERNAL
CONTROL
(NOTE 1)

EXTERNAL
CONTROL
(NOTE 2)

0
1
2
3

13-bit Timer
16-bitTimer
8-bit Auto-Reload
not available

40H
50H
60H

COH
DOH
EOH

NOTES:
1. The Timer Is tumed ON/OFF by setting/clearing bit TR1 In the software.
2. The Timer Is tumed ON/OFF by the 1 to 0 transition on INTI (p3.3) when TRI = 1
(herdware control).

February 1989

1-56

Signetics Microprocessor Products

Section 1

User's Guide

8051 Family Programmer's Guide and Instruction Set

SCON: (SOCON IN THE 83C652 AND 83C552) SERIAL PORT CONTROL REGISTER.
BIT ADDRESSABLE

I.
SM1

SMO

SM2

REN

RB8

TB8

SMO

SCON.7 Serial Port mode specifier. (NOTE 1).

SMI

SCON.6 Serial Port mode specifier. (NOTE 1).

SM2

SCON.5 Enables the multiprocessor communication feature in modes 2 & 3. In mode 2 or 3, ifSM2 is set
to 1 then RI will not be activated if the received 9th data bit (RB8) is O. In mode I, if SM2 = 1
then RI will not be activated if a valid stop bit was not received. In mode 0, SM2 should be O.
(See Table 18).

REN

SCON. 4 Set/Cleared by software to EnablelDisable reception.

TB8

SCON.3 The 9th bit that will be transmitted in modes 2 & 3. Set/Cleared by software.

RB8

SCON. 2 In modes 2 & 3, is the 9th data bit that was received. In mode I, if SM2 = 0, RB8 is the stop bit
that was received. In mode 0, RB8 is not used.

SCON. I Transmit interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or at the
beginning of the stop bit in the other modes. Mnst be cleared by software.

SCON.O Receive interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or halfway
through the stop bit time in the other modes (except see SM2). Must be cleared by software.

NOTE 1:

SMO

SM1

Mode

Description

Baud Rate

o
o

0
1
0

0
1
2

SHIFT REGISTER
8-Bit UART
9-Bit UART

9-BitUART

Fosc.l12
Variable
Fosc.l64OR
Fosc.l32
Variable

SERIAL PORT SET-UP:
Table 18
MODE

SCON

SM2 VARIATION

0
1
2
3

10H
SOH
90H
DOH

Single Processor
Environment
(SM2 = 0)

0
1
2
3

NA
70H
BOH
FOH

Multiprocessor
Environment
(SM2 = 1)

GENERATING BAUD RATES
Serial Port in Mode 0:
Mode 0 has a fixed baud rate which is 1/12 of the oscillator frequency. To run the serial port in this mode none of
the Timer/Counters need to be set up. Only the SCON register needs to be defined.
Baud Rate

Osc Freq
12

Serial Port in Mode 1:
Mode 1 has a variable baud rate. The baud rate is generated by Timer 1.
February 1989

1-57

Signetics. Microprocessor Products

Section 1

User's Guide

8051 Family Programmer's Guide and Instruction Set

USING TIMER/COUNTER 1 TO GENERATE BAUD RATES:
For this purpose, Timer 1 is used in mode 2 (Auto-Reload). Refer to Timer Setup section of this chapter.
B
R
K x Oscillator Freq.
aud ate = 32 x 12 x [256 - (TH1))

If SMOD
If SMOD

=
=

0, then K
I, then K

=
=

1.
2. (SMOD is the PCON register).

Most of the time the user knows the baud rate and needs to know the reload value for TH 1.
Therefore, the equation to calculate THI can be written as:
TH1 = 256

KxOsc Freq.
384 x baud rate

TH 1 must be an integer value. Rounding off TH 1 to the nearest integer may not produce the desired baud rate. In
this case, the user may have to choose another crystal frequency.
Since the PCON register is not bit addressable, one way to set the bit is logical ORing the PCON register. (ie, ORL
PCON,#80H). The address of PCON is 87H.

SERIAL PORT IN MODE 2:
The baud rate is fixed in this mode and is
bit in the PCON register.

1/,2 or Y•• of the oscillator frequency depending on the value of the SMOD

In this mode none of the TimerS are used and the clock comes from the internal phase 2 clock.
SMOD

I, Baud Rate

= 1/,2 Osc Freq.

SMOD

0, Baud Rate

= II•• Osc Freq.

To set the SMOD bit: ORL

PCON, # SOH. The address of PCON is S7H.

SERIAL PORT IN MODE 3:
The baud rate in mode 3 is variable and sets up exactly the same as in mode 1.

February 1989

1-58

User's Guide

Signetics Microprocessor Products

Section 1

8051 Family Programmer's Guide and Instruction Set

8051 FAMILY INSTRUCTION SET
Table 19. 8051 Instruction Set Summary
r---------------------------~

Interrupt Response Time: Refer to Hardware Description Chapter.
Instructions that Affect Flag Settlngs(1)

Instruction
ADD
ADDC
SUBB
MUl
DIV
DA
RRC
RlC
SETBC

Flag
Instruction
C OV AC
X X X ClRC
X X X CPlC
X X X ANlC,bit
ANl C,Ibit
0 X
ORlC,bit
0 X
X
ORl C,Ibit
X
MOVC,bit
X
CJNE

Flag

C OV AC
0
X
X
X
X
X
X
X

(I}Note that operations on SFR byte address 208 or
bit addresses 209-215 (i.e., the PSW or bits in the
PSW) will also affect flag settings.
Note on instruction set and addressing modes:
Rn
- Register R 7 - RO of the currently selected Register Baok.
direct
- 8-bit internal data location's address.
This could be ao Internal Data RAM
location (0-127) or a SFR [i.e., I/O
port, control register, status register,
etc. (128-255)].
@Ri
- 8-bit intemai data RAM location (0255) addressed indirectly through register Rl or RO.
# data
- 8-bit constant included in instruction.
# data 16 - 16-bit constant included in instruction.
addr 16 - 16-bit destination address. Used by
LCALL & UMP. A branch can be
anywhere within the 64K-byte Program Memory address space.
addr 11 - ll-bit destination address. Used by
ACALL & AJMP. The branch will be
within the same 2K-byte page of program memory as the first byte of the
following instruction.
rei
- Signed (two's complement) 8-bit offset
byte. Used by SJMP aod all conditional jumps. Range is -128 to + 127
bytes relative to first byte of the following instruction.
bit
- Direct Addressed bit in Internal Data
RAM or Special Function Register.

February 1989

1-59

.-----------------------------,
Oscillator
Mnemonic

Description

Byte

Period
ARITHMETIC OPERATIONS
A,Rn
ADD
Add register to
12
Accumulator
ADD
A,direct Add direct byte to
2
12
Accumulator
A,@Ri
ADD
Add indirect RAM
12
to Accumulator
ADD
A,#data Add immediate
2
12
data to
Accumulator
ADDC A,Rn
Add register to
12
Accumulator
with Carry
ADDC A,direct Add direct byte to
2
12
Accumulator
with Carry
ADDC A,@Ri
Add indirect
12
RAM to
Accumulator
with Carry
ADDC A,#data Add immediate
2
12
data to Acc
with Carry
SUBB A,Rn
Subtract Register
12
from Acc with
borrow
SUBB A,direct Subtract direct
2
12
byte from Acc
with borrow
SUBB A,@Ri
Subtract indirect
12
RAM from ACC
with borrow
SUBB A,#data Subtract
2
12
immediate data
from Acc with
borrow
INC
A
Increment
12
Accumulator
INC
Rn
Increment register
1
12
INC
direct
Increment direct
2
12
byte
@Ri
Increment indirect
INC
12
RAM
DEC
A
Decrement
12
Accumulator
DEC
Rn
Decrement
12
Register
direct
Decrement direct
DEC
2
12
byte
@Ri
DEC
Decrement
12
indirect RAM
All mnemonics copyrighted @ Intel Corporation 1980

User's Guide

Signetics Microprocessor Products

Section 1

8051 Family Programmer's Guide and Instruction Set
Table 19, 8051 Instruction Set Snmmary (Continned)

Mnemonic

Description

Byte

ARITHMETIC OPERATIONS (Continued)
INC DPTR
Increment Data
Pointer
Multiply A & B
MUL AB
DIV AB
DivideAbyB
DA
A
Decimal Adjust
Accumulator
LOGICAL OPERATIONS
AND Register to
ANL A,Rn
Accumulator
ANL A,direct
AN D direct byte
2
to Accumulator
AND indirect
ANL A,@Ri
RAM 10
Accumulator
AND immediate
ANL A,#data
2
data to
Accumulator
ANL direct,A
AND Accumulator
2
to direct byte
ANL direct, # data AND immediate
3
data to direct byte
ORL A,Rn
OR register to
Accumulator
ORL A,direct
OR direct byte to
2
Accumulator
OR indirect RAM
ORL A,@Ri
to Accumulator
ORL A,#data
OR immediate
2
data to
Accumulator
ORL direct,A
OR Accumulator
2
to direct byte
ORL direct, # data OR immediate
3
data to direct byte
XRL A,Rn
Exclusive-OR
register to
Accumulator
XRL A,direct
Exclusive-OR
2
direct byte to
Accumulator
Exclusive-OR
XRL A,@Ri
indirect RAM to
Accumulator
Exclusive-OR
2
XRL A,#data
immediate data to
Accumulator
XRL direct,A
Exclusive-OR
2
Accumulator to
direct byte
XRL direct, # data Exclusive-OR
3
immediate data
to direct byte
CLR A
Clear
Accumulator
CPL A
Complement
Accumulator

February

1989

Oscillator
Period

24
48
48
12
12
12
12
12
12
24
12
12
12
12
12
24
12
12
12
12
12
24
12
12

Mnemonic

Description

LOGICAL OPERATIONS (Continued)
Rotate
RL
A
Accumulator Left
RLC
A
Rotate
Accumulator Left
through the Carry
Rotate
RR
A
Accumulator
Right
RRC
A
Rotate
Accumulator
Right through
the Carry
SWAP A
Swap nibbles
within the
Accumulator
DATA TRANSFER
Move
MOV A,Rn
register to
Accumulator
MOV A,direct
Move direct
byte to
Accumulator
MOV A,@Ri
Move indirect
RAM to
Accumulator
MOV A,#data
Move
immediate
data to
Accumulator
MOV Rn,A
Move
Accumulator
to register
Move direct
MOV Rn,direct
byte to
register
MOV Rn,#data
Move
immediate data
to register
Move
MOV direct,A
Accumulator
to direct byte
MOV direct,Rn
Move register
to direct byte
MOV direct,direct Move direct
byte to direct
Move indirect
MOV direct,@Ri
RAM to
direct byte
MOV direct, # data Move
immediate data
to direct byte
Move
MOV @Ri,A
Accumulator to
indirect RAM

Byte

12
12
12
12

12
2

12
12

12
2

All mnemonics copyrighted ® Inlel Corporation

1-60

Oscillator
Period

1980

User's Guide

Si g netics Microprocessor Products

Section 1

8051 Family Programmer's Guide and Instruction Set
Table 19. 8051 Instruction Set Summary (Continued)

Mnemonic

Description

DATA TRANSFER (Continued)
@Ri,direct
Move direct
MOV
byte to
indirect RAM
@Ri,#data
Move
MOV
immediate
data to
indirect RAM
MOV DPTR, #datal6 Load Data
Pointer with a
16-bit constant
MOVC A,@A+DPTR
Move Code
byte relative to
DPTRto Acc
MOVC A,@A+PC
Move Code
byte relative to
PC to Acc
MOVX A,@Ri
Move
External
RAM (B-bit
addr) to Acc
MOVX A,@DPTR
Move
External
RAM (16-bit
addr) to Acc
MOVX @Ri,A
Move Acc to
External RAM
(B-bit addr)
MOVX @DPTR,A
Move Acc to
External RAM
(16-bit addr)
PUSH direct
Push direct
byte onto
stack
POP
direct
Pop direct
byte from
stack
XCH
A,Rn
Exchange
register with
Accumulator
XCH
A,direct
Exchange
direct byte
with
Accumulator
A,@Ri
XCH
Exchange
indirect RAM
with
Accumulator
XCHD A,@Ri
Exchange loworder Digit
indirect RAM
with Acc

February

1989

Byte

Oscillator
Period

Mnemonic

Oscillator
Period
1-

Byte

BOOLEAN VARIABLE MANIPULATION
Clear Carry
1
CLR
C
bit
Clear direct bit
2
CLR
SETB
Set Carry
C
Set direct bit
2
SETB
bit
Complement
CPL
C
Carry
bit
Complement
2
CPL
direct bit
C,bit
AND direct bit
2
ANL
to CARRY
ANL
C,/bit
AND complement
2
of direct bit
to Carry
C,bit
OR direct bit
2
ORL
to Carry
C,/bit
OR complement
2
ORL
of direct bit
to Carry
Move direct bit
2
C,bit
MOV
to Carry
2
Move Carry to
MOV
bit,C
direct bit
rei
Jump if Carry
2
JC
is set
2
rei
Jump if Carry
JNC
not set
3
bit,rel
Jump if direct
JB
Bit is set
bit,rel
Jump if direct
3
JNB
Bit is Not set
3
bit,rel
Jump if direct
JBC
Bit is set &
clear bit
PROGRAM BRANCHING
2
ACALL addrll Absolute
Subroutine
Call
3
LCALL addr16 Long
Subroutine
Call
Return from
RET
Subroutine
RETI
Return from
interrupt
2
AJMP
addrll Absolute
Jump
3
WMP
addr16 Long Jump
Short Jump
2
SJMP
rei
(relative addr)

Description

12
12
12
12
12
"12
24
24

24
24

12
24
24
24
24
24
24

24
24
24
24
24

All mnemonics copyrighted © Intel Corporation 19BO

1-61

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Section 1

8051 Family Programmer's Guide and Instruction Set
Table 19. 8051 Instruction Set Summary (Continued)

r---------------------------~

Mnemonic

Description

PROGRAM BRANCHING (Continued)
@A+DPTA Jump indirect
JMP
relative to the
DPTA
rei
Jump if
JZ
Accumulator
is Zero
rei
JNZ
Jump if
Accumulator
is Not Zero
Compare
CJNE A,direct,rel
direct byte to
Acc and Jump
if Not Equal
CJNE A, '" data,rel Compare
immediate to
AccandJump
if Not Equal

Byte

Oaclllator
Period
24

r---------------------------~

Mnemonic

Deacrlptlon

PROGRAM BRANCHING (Continued)
Compare
CJNE An,"'data,rel
immediate to
register and
Jump if Not
Equal
CJNE @Ai,"'data,rel Compare
immediate to
indirect and
Jump if Not
Equal
Decrement
DJNZ An,rel
register and
Jump if Not
Zero
DJNZ direct, rei
Decrement
direct byte
and Jump if
Not Zero
No Operation
NOP

Byte

Oscillator
Period

All mnemonics copyrighted © Intel Corporation 1980

February 1989

1-62

User's Guide

Signetics Microprocessor Products

Section 1

8051 Family Programmer's Guide and Instruction Set

INSTRUCTION DEFINITIONS
ACALL addr11
Function:

Absolute Call

Description:

ACALL unconditionally calls a subroutine located at the indicated address. The instruction
increments the PC twice to obtain the address of the following instruction, then pushes the
16-bit result onto the stack (low-order byte first) and increments the Stack Pointer twice. The
destination address is obtained by successively concatenating the five high-order bits of the
incremented PC, opcode bits 7-5, and the second byte of the instruction. The subroutine called
must therefore start within the same 2K block of the program memory as the first byte of the
instruction following ACALL. No flags are affected.

Example:

Initially SP equals 07H. The label "SUBRTN" is at program memory location 0345 H. After
executing the instruction,
ACALL

SUBRTN

at location Ol23H, SP will contain 09H, internal RAM locations OSH and 09H will contain
25H and OIH, respectively, and the PC will contain 0345H.

Bytes:

Cycles:

Encoding:
Operation:

February 1989

I a10 a9 a8

0 0 0 1

I a7 a6 a5 a4

ACALL
(PC) +- (PC) + 2
(SP) +- (SP) + 1
«SP» +- (PC7-O)
(SP) +- (SP) + I
«SP) +- (PCIS-S)
(PCIO-O) +- page address

1-63

a3 a2 a1 aO

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Section 1

User's Guide

8051 Family Programmer's Guide and Instruction Set

ADD A, <.rc-byte >
Function:
De.crlptlon:

Add

ADD adds the byte variable indicated to the Accumulator, leaving the result in the Accumulator. The carry and auxiliary-carry flags are set, respectively, if there is a carry-out from bit 7 or
bit 3, and cleared otherwise. When adding unsigned integers, the carry flag indicates an
overflow occured.
OV is set if there is a carry-out of bit 6 but not out of bit 7, or a carry-out of bit 7 but not bit 6;
otherwise OV is cleared. When adding signed integers, OV indicates a negative number produced as the sum of two positive operands, or a positive sum from two negative operands.
Four source operand addressing modes are allowed: register, direct, register-indirect, or immediate.

Example:

The Accumulator holds OC3H (llOOOOllB) and register 0 holds OAAH (10 10 10 lOB). The
instruction,

ADD A,RO
will leave 6DH (01 101 IOIB) in the Accumulator with the AC flag cleared and both the carry
flag and OV set to 1.

ADD A,Rn
Byte.:
Cycle.:
Encoding:
Operation:

ADD

0 0 1 0

ADD
(A) ..- (A)

1 r r r

(Rn)

A,dlrect
Byte.:

Cycle.:
Encoding:
Operation:

February 1989

ADD
(A) ..- (A)

o1
+

0 1

direct address

(direct)

1-64

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Signetics Microprocessor Products

8051 Family Programmer's Guide and Instruction Set

Section 1
A,@Ri

ADD

Bytes:
Cycles:
Encoding:
Operation:

00 1 0

ADD
(A) -

(A)

011

«Rj))

A, # data

ADD

Bytes:

Cycles:
Encoding:
Operation:

I 00

1 0

ADD
(A) -(A)

o1
+

0 0

immediate data

# data

A, < src-byte >

ADDC

Function:
Description:

Add with Carry
ADDC simultaneously adds the byte variable indicated, the carry flag and the Accumulator
contents, leaving the result in the Accumulator. The carry and auxiliary-carry flags are set,
respectively, if there is a carry-out from bit 7 or bit 3, and cleared otherwise. When adding
unsigned integers, the carry flag indicates an overflow occured.
OV is set if there is a carry-out of bit 6 but not out of bit 7, or a carry-out of bit 7 but not out of
bit 6; otherwise OV is cleared. When adding signed integers, OV indicates a negative number
produced as the sum of two positive operands or a positive sum from two negative operands.

Four source operand addressing modes are allowed: register, direct, register-indirect, or immediate.
Example:

The Accumulator holds OC3H (llOOOOllB) and register 0 holds OAAH (lOlOJOlOB) with the
carry flag set. The instruction,
ADDC

A,RO

will leave 6EH (01 1011 lOB) in the Accumulator with AC cleared and both the Carry flag and
OV set to I.

February 1989

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8051 Family Programmer's Guide and Instruction Set

Section 1
ADDC

A,Rn
Bytes:
Cycles:

Encoding:
Operation:

ADDC

_0_0_1_,--l_r_r_r-l1

1-1

ADDC
(A) - (A)

(C)

+ (R,J

A,dlrect
Bytes:

Cycles:
Encoding:
Operation:

_0_0_1_,--0_1_0_1--,

1-1

ADDC
(A) - (A)

(C)

direct address

(direct)

ADDC A,@RI
Bytes:
Cycles:
Encoding:
Operation:

ADDC

_O_O_l_-,-O_l_l_i--,1

1-1

ADDC
(A) - (A)

(C)

+ «Rv)

A,#data
Bytes:

Cycles:
Encoding:
Operation:

February 1989

_0_0_1_-,--0_1_0_0-,

1-1

ADDC
(A) - (A)

(C)

immediate data

#data

1-66

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Section 1

User's Guide

8051 Family Programmer's Guide and Instruction Set

AJMP addr11
Function:
Description:

Example:

Absolute Jump
AJMP transfers program execution to the indicated address, which is formed at run-time by
concatenating the high-order five bits of the PC (after incrementing the PC twice), opcode bits
7-5, and the second byte ofthe instruction. The destination must therefore be within the same
2K block of program memory as the first byte of the instruction following AJMP.
The label "JMPADR" is at program memory location 0123H. The instruction,
AJMP

JMPADR

is at location 0345H and will load the PC with 0123H.

Bytes:

Cycles:

Encoding:
Operation:

ANL

I a10 a9 a8 0

0 0 0 1

a7 a6 a5 a4

a3 a2 a1 aO

AJMP
(PC) +- (PC) + 2
(PCw.o) +- page address

,
Function:

Description:

Logical-AND for byte variables
ANL performs the bitwise logical-AND operation between the variables indicated and stores
the results in the destination variable. No flags are affected.
The two operands allow six addressing mode combinations. When the destination is the Accumulator, the source can use register, direct, register-indirect, or immediate addressing; when
the destination is a direct address, the source can be the Accumulator or immediate data.

Note: When this instruction is used to modify an output port, the value used as the original
port data will be read from the output data latch, not the input pins.
Example:

If the Accumulator holds OC3H (1IOOOOIIB) and register 0 holds 55H (OlOI010IB) then the
instruction,
ANL

A,RO

will leave 4lH (OIOOOOOIB) in the Accumulator.
When the destination is a directly addressed byte, this instruction will clear combinations of
bits in any RAM location or hardware register. The mask byte determining the pattemofbits
to be cleared would either be a constant contained in the instruction or a value computed in
the Accumulator at run-time. The instruction,
ANL

PI, #OIIIOOIIB

will clear bits 7, 3, and 2 of output port 1.

February 1989

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Section 1· .

User's Guide

8051 Family Programmer's Guide and Instruction Set

ANL A,Rn
Bytes:
Cycl..:
Encoding:

1 0 1 01 1 1 r r r

Operation:

ANL
(A) -

(A) A (Rn)

ANL A,dlrect
Byte.:

Cycles:
Encoding:

1 0101 1 0 1 0 1

Operation:

ANL
(A) -

1 direct address 1

(A) A (direct)

ANL A,@RI
Byte.:
Cycle.:
Encoding:

101011 011i

Operation:

ANL
(A) -

(A) A

«Ri»

ANL A,#data
Byte.:

Cycle.:
Encoding:

1 0101 1 01 001

Operation:

ANL
(A) -

immediate data 1

(A) A #data

ANL dlrect,A
Bytes:

Cycle.:
encoding:

1 010 1 1 001 0 1

Operation:

ANL
(direct) -

February 1989

I direcl address 1

(direct) A (A)

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Section 1

User's Guide

8051 Family Programmer's Guide and Instruction Set

ANL direct, # data
Bytes:

Cycles:

Encoding:
Operation:

I0 1 0 1

0 0 1 1

direct address

immediate data

ANL
(direct) +- (direct) /\ # data

ANL C,
Function:
Description:

Example:

Logical-AND for bit variables
If the Boolean value of the source bit is a logical 0 then clear the carry flag; otherwise leave the
carry flag in its current state. A slash (hI") preceding the operand in the assembly language
indicates that the logical complement of the addressed bit is used as the source value. but the
source bit itself is not affected. No other flags are affected.
Only direct addressing is allowed for the source operand.
Set the carry flag if. and only if. P1.0 = 1. ACC. 7 = 1. and OV = 0:
MOV

C,Pl.O

;LOAD CARRY WITH INPUT PIN STATE

ANL

C.ACC.7

;AND CARRY WITH ACCUM. BIT 7

ANL

C,/OV

;AND WITH INVERSE OF OVERFLOW FLAG

ANL C,blt
Bytes:

Cycles:

Encoding:

11 000

Operation:

ANL
(C) +- (C) /\ (bit)

00 1 0

bit address

ANL C,/blt
Bytes:

Cycles:

Encoding:

Operation:

ANL
(C) +- (C) /\ --, (bit)

February 1989

0000

bit address

1-69

Signetics Microprocessor Products

Section 1
CJNE

User's Guide

8051 Family Programmer's Guide and Instruction Set

< dest-byte > , < src-byte > , rei
Function:

Description:

Compare and Jump if Not Equal.
CINE compares the magnitudes of the first two operands, and branches if their values are not
equal. The branch destination is computed by adding the signed relative-displacement in the
last instruction byte to the PC, after incrementing the PC to the start of the next instruction.
The carry flag is set if the unsigned integer value of is less than the unsigned
integer value of < src-byte > ; otherwise, the carry is cleared. Neither operand is affected.
The first two operands allow four addressing mode combinations, the Accumulator may be
compared with any directly addressed byte or immediate data, and any indirect RAM location
or working register can be compared with an immediate constant.

Example:

The Accumulator contains 34H. Register 7 contains 56H. The first instruction in the sequence,
CINE R7,#60H, NOT_EQ
R7 = 6OH.

NOT.-EQ:

REQJOW

IFR7 < 6OH.
R7> 6OH.

sets the carry. flag and branches to the instruction at label NOT_EQ. By testing the carry flag,
this instruction determines whether R 7 is greater or less than 60H.
If the data being presented to Port I is also 34H, then the instruction,
WAIT: CINE A,PI,WAIT

clears the carry flag and continues with the next instruction in sequence, since the Accumulator does equal the data read from PI. (If some other value was being input on PI, the program
will loop at this point until the PI data changes to 34H.)
CJNE

A,direct,rel
Bytes:

Cycles:

Encoding:

110110101

Operation:

(PC) - (PC) + 3
IF (A) < > (direct)
THEN
(PC) - (PC)

direct address

relative offset

IF (A) < (direct)
THEN
(C)-I
ELSE
(C)-O

February 1989

1-70

rei. address

Signetics Microprocessor Products

Section 1
CJNE

User's Guide

8051 Family Programmer's Guide and Instruction Set

A, # data,rel
Bytes:

Cycles:

Encoding:

110110100

Operation:

(PC) - (PC) + 3
IF (A) < > data

THEN
(PC) -

(PC)

immediate data

rei. address

relative offset

IF (A) < data

THEN
(C)-l

ELSE
(C)-O

CJNE

Rn,#data,rel
Bytes:

Cycles:

Encoding:

I1 0 1 1

Operation:

(PC) - (PC) + 3
IF (Rn) < > data

immediate data

1 r r r

THEN
(PC) -

(PC)

reI. address

relative offset

IF (Rn) < data

THEN
(C)-l

ELSE
(C)-O

CJNE

@RI,#data,rel
Bytes:

Cycles:

Encoding:

11011011

Operation:

(PC) IF

«Ri»

(PC)

immediate data

< > data

THEN

(PC) -

«Ri»

(PC)

relative offset

< data

THEN

(C)-l

ELSE
(C)-O

February 1989

1-71

reI. address

User's Guide

Signetics Microprocessor Products

8051 Family Programmer's Guide and Instruction Set

Section 1
CLR

A
Function:

Description:
Example:

Clear Accumulator
The Accumulator is cleared (all bits reset to zero). No flags are affected.
The Accumulator contains 5CH (01011100B). The instruction,
CLR A
will leave the Accumulator set to OOH (OOOOOOOOB).

Bytes:
Cycles:
Encoding:
Operation:

1 1

0 1 0 0

CLR
(A)-O

CLR

bit
Function:

Description:
Example:

Clear bit
The indicated bit is cleared (reset to zero). No other flags are affected. CLR can operate on the
carry flag or any directly addressable bit.
Port 1 has previously been written with 5DH (01011 IOIB). The instruction,
CLR PI.2
will leave the port set to 59H (OIOII00IB).

CLR

C
Bytes:
Cycles:
Encoding:
Operation:

CLR

0 0

0 0 1 1

CLR
(C)-O

bit
Bytes:

Cycles:
Encoding:
Operation:

February 1989

I1
CLR
(bit) -

0 0

0 0 1 0

bit address

1-72

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8051 Family Programmer's Guide and Instruction Set

Section 1
CPL

A
Function:

Description:
Example:

Complement Accumulator
Each bit of the Accumulator is logically complemented (one's complement). Bits which previously contained a one are changed to a zero and vice-versa. No flags are affected.
The Accumulator contains 5CH (OlOlllOOB). The instruction,
CPL A
will leave the Accumulator set to OA3H (lOlOOOIIB).

Bytes:
Cycles:
Encoding:

11110100

Operation:

CPL
(A) - - , (A)

CPL bit
Function:
Description:

Complement bit
The bit variable specified is complemented. A bit which had been a one is changed to zero and
vice-versa. No other flags are affected. CLR can operate on the carry or any directly addressable bit.

Note: When this instruction is used to modify an output pin, the value used as the original data
will be read from the output data latch, not the input pin.
Example:

Port I has previously been written with 5BH (OlOlllOlB). The instruction sequence,
CPL Pl.l
CPL

P1.2

will leave the port set to 5BH (0101 101 IB).
CPL C
Bytes:
Cycles:
Encoding:

1_1_0_1_....>-_0_0_1_1-1
....

Operation:

CPL
(C) - - , (C)

February 1989

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8051 Family Programmer's Guide and Instruction Set

Section 1
CPL bit
Bytes:

Cycles:
Encoding:
Operation:

_1_0_1_-,-_0_0_1_0-,

1-1

bit address

CPL
(bit) +- -, (bit)

DA A
Function:
Description:

Decimal-adjust Accumulator for Addition
DA A adjusts the eight-bit value in the Accumulator resulting from the earlier addition of two
variables (each in packed-BCD format), producing two four-bit digits. Any ADD or ADDC
instruction may have been used to perform the addition.
If Accumulator bits 3-0 are·greater than nine (xxxxlOlO-xxxxllll), or if the AC flag is one,
six is added to the Accumulator producing the proper BCD digit in the low-order nibble. TIlls
internal addition would set the carry flag if a carry-out of the low-order four-bit field propagated through all high-order bits, but it would not clear the carry flag otherwise.
If the carry flag is now set, or if the four high-order bits now exceed nine (1010xxxx-lllxxxx),
these high-order bits are incremented by six, producing the proper BCD digit in the high-order
nibble. Again, this would set the carry flag if there was a carry-out of the high-order bits, but
wouldn't clear the carry. The carry flag thus indicates if the sum of the original two BCD
variables is greater than 100, allowing multiple precision decimal addition. OV is not affected.
All of this occurs during the one instruction cycle. Essentially, this instruction performs the
decimal conversion by adding OOH, 06H, 6OH, or 66H to the Accumulator, depending on
initial Accumulator and PSW conditions.

Note: DA A cannot simply convert a hexadecimal number in the Accumulator to BCD notation, nor does DA A apply to decimal subtraction.

February 1989

1-74

Signetics Microprocessor Products

Section 1

Example:

User's Guide

8051 Family Programmer's Guide and Instruction Set

The Accumulator holds the value 56H (01010110B) representing the packed BCD digits of the
decimal number 56. Register 3 contains the value 67H (OII00IIIB) representing the packed
BCD digits of the decimal number 67. The carry flag is set. The instruction sequence.
ADDC A,R3
DA
A
will first perform a standard twos-complement binary addition, resulting in the value OBEH
(10111110) in the Accumulator. The carry and auxiliary carry flags will be cleared.
The Decimal Adjust instruction will then alter the Accumulator to the value 24H
(OOI00I00B), indicating the packed BCD digits of the decimal number 24, the low-order two
digits ofthe decimal sum of 56, 67, and the carry-in. The carry flag will be set by the Decimal
Adjust instruction, indicating that a decimal overflow occurred. The true sum 56, 67, and 1 is
124.
BCD variables can be incremented or decremented by adding 01H or 99H. If the Accumulator
initially holds 30H (representing the digits of 30 decimal), then the instruction sequence,
ADD

A,#99H

will leave the carry set and 29H in the Accumulator, since 30
byte of the sum can be interpreted to mean 30 - 1 = 29.

Bytes:
Cycles:
EnCOding:
Operation:

I1 1 0 1

DA
-contents of Accumulator are BCD
IF
[[(A3-O) > 9) V [(AC) = 111
THEN(A3-O) +- (A3-O) + 6
AND
IF

February 1989

0 1 0 0

[[(A74) > 9) V [(C) =
THEN (A7-4) +- (A74)

111
+6

1-75

99 = 129. The low-order

User's Guide

Signetics Microprocessor Products

8051

Section 1
DEC

F~mily

Programmer's Guide and Instruction Set

byte
Function:

Description:

Decrement
The variable indicated is decremented by I. An original value of OOH will underflow to OFFH.
No flags are affected. Four operand addressing modes are allowed: accumulator, register,
direct, or register-indirect.

Note: When this instruction is used to modify an output port, the value used as the original
port data will be read from the output data latch, not the input pins.
£xample:

Register 0 contains 7FH (OlllllllB). Internal RAM locations 7EH and 7FH contain OOH
and 4OH, respectively. The instruction sequence,
DEC

@RO

DEC RO
DEC

@RO

will leave register 0 set to 7EH and internal RAM locations 7EH and 7FH set to OFFH and
3FH.
DEC A
Bytes:
Cycles:

DEC

Encoding:

100010100

Operation:

DEC
(A) -

(A) - 1

Rn
Bytes:
Cycles:
Encoding:

10001

Operation:

DEC
(Rn) -

February 1989

1rrr

(Rn) - 1

1-76

Signetics Microprocessor Products

Section 1
DEC

User's Guide

8051 Family Programmer's Guide and Instruction Set

direct
Bytes:

Cycles:
Encoding:
Operation:

DEC

_0_0_0_-,--0_1_0_1-,

,-I

direct address

DEC
(direct) +- (direct) -

@RI
Bytes:
Cycles:
Encoding:
Operation:

DIV

°°° °

DEC

«Ri»

1 1

«Ri» - I

AB
Function:
Description:

Divide
DIV AB divides the unsigned eight-bit integer in the Accumulator by the unsigned eight-bit
integer in register B. The Accumulator receives the integer part of the quotient; register B
receives the integer remainder. The carry and OV flags will be cleared.

Exception: if B had originally contained OOH, the values returned in the Accumulator and Bregister will be undefined and the overflow flag will be set. The carry flag is cleared in any
case.
Example:

The Accumulator contains 251 (OFBH or lIIIIOIIB) and B contains 18 (12H or 000100 lOB).
The instruction,
DIV

will leave 13 in the Accumulator (ODH or OOOOllOIB) and the value 17 (llH or OOOIOOOIB)
in B, since 251 = (13 X 18) + 17. Carry and OV will both be cleared.
Bytes:
Cycles:
Encoding:
Operation:

°°° ° °°
1

DIV
(A)15-8 +- (A)/(B)

(Bh-o

February 1989

1-77

User's Guide

Signetics Microprocessor Products

8051 Family Programmer's Guide and Instruction Set

Section 1
DJNZ

< byte> , < rel-addr >
Function:

Description:

Decrement and Jump if Not Zero
DJNZ decrements the location indicated by I, and branches tothe address indicated by the
second operand if the resulting value is not zero. An original value of OOH will underflow to
OFFH. No flags are affected. The branch destination would be computed by adding the signed
relative-displacement value in the last instruction byte to the PC, after incrementing the PC to
the first byte of the following instruction.
The location decremented may be a register or directly addressed byte.
Note: When this instruction is used to modify an output port, the value used as the original
port data will be read from the output data latch, not the input pins.

Example:

Internal RAM locations 40H, 50H, and 60H contain the values OIH, ?OH, and 15H, respectively. The instruction sequence,
DJNZ 40H,LABEL_l
DJNZ 50H,LABEL_2
DJNZ 60H,LABEL_3
will cause a jump to the instruction at label LABEL_2 with the values OOH, 6FH, and 15H in
the three RAM locations. The first jump was not taken because the result was zero.
This instruction provides a simple way of executing a program loop a given number of times,
or for adding a moderate time delay (from 2 to 512 machine cycles) with a single instruction.
The instruction sequence,
TOGGLE:

MOV
CPL
DJNZ

R2,#8
Pl.?
R2,TOGGLE

will toggle Pl.? eight times, causing four output pulses to appear at bit 7 of output Port I.
Each pulse will last three machine cycles; two for DJNZ and one to alter the pin.
DJNZ Rn,rel
Bytes:

Cycles:

reI. address

Encoding:

L.1_1_1_0_1......L_1_ r_r_ r ..J

Operation:

DJNZ
(PC) - (PC) + 2
(Rn) - (Rn) - I
IF (Rn) > 0 or (Rn) < 0
THEN
(PC) - (PC) + rel

February 1989

1-78

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Section 1

User's Guide

8051 Family Programmer's Guide and Instruction Set

DJNZ dlrect,rel
Bytes:

Cycles:

Encoding:
Operation:

I1 1 0 1

0 1 0 1

direct address

reI. address

DJNZ
(PC) +- (PC) + 2
(direct) +- (direct) IF (direct) > 0 or (direct) < 0
THEN
(PC) +- (PC) + reI

INC

Function:
Description:

Increment
INC increments the indicated variable by I. An original value of OFFH will overflow to OOH.
No flags are affected. Three addressing modes are allowed: register, direct, or register-indirect.

Note: When this instruction is used to modify an output port, the value used as the original
port data will be read from the output data latch, not the input pins.
Example:

Register 0 contains 7EH (011 II II lOB). Internal RAM locations 7EH and 7FH contain OFFH
and 4OH, respectively. The instruction sequence,
INC
INC
INC

@RO
RO
@RO

will leave register 0 set to 7FH and internal RAM locations 7EH and 7FH holding (respectively) OOH and 4tH.

INC

A
Bytes:
Cycles:
Encoding:
Operation:

10000
INC
(A) +- (A)

February 1989

I0 1 0 0
+

1-79

Signetics Microprocessor Products

8051 Family Programmer's Guide and Instruction Set

Section 1
INC

User's Guide

Rn
Bytes:
Cycles:
Encoding:
Operation:

I 0000 I 1 r r r
INC
(Rn)- (Rn)

INC

direct
Bytes:

Cycles:
Encoding:
Operation:

INC

I 000 0 I 0 1 0 1 I
INC
(direct) -

direct address

(direct)

@RI
Bytes:
Cycles:
Encoding:
Operation:

INC

I 0000 I 011
INC
((Ri» -

((Ri»

DPTR
Function:

Description:

Increment Data Pointer
Increment the 16-bit data pointer by I. A 16-bit increment (modulo 2 16) is performed; an
overflow of the low-order byte of the data pointer (DPL) from OFFH to OOH will increment
the high-order byte (DPH). No flags are affected.
This is the only 16-bit register which can be incremented.

Example:

Registers DPH and DPL contain 12H and OFEH. respectively. The instruction sequence.
INC DPTR
INC DPTR
INC DPTR
will change DPH and DPL to I3H and OlH.

Bytes:
Cycles:
Encoding:
Operation:

February 1989

I1 0 1 0
INC
(DPTR) -

0 0 1 1
(DPTR)

1-80

Signetics Microprocessor Products

Section 1
JB

User's Guide

8051 Family Programmer's Guide and Instruction Set

blt,rel
Function:

Jump if Bit set

Description:

If the indicated bit is a one, jump to the address indicated; otherwise proceed with the next
instruction. The branch destination is computed by adding the signed relative-displacement in
the third instruction byte to the PC, after incrementing the PC to the first byte of the next
instruction. The bit tested is not modified. No flags are affected.

Example:

The data present at input port I is I 100 10 lOB. The Accumulator holds 56 (010101 lOB). The
instruction sequence,
JB

P1.2,LABELl

ACC.2,LABEL2

will cause program execution to branch to the instruction at label LABEL2.
Bytes:

Cycles:

Encoding:

I0 0

Operation:

1 0

0 0 0 0

(PC) +- (PC)

reI. address

IF (bit) = I
THEN
(PC) +- (PC)

JBC

bit address

rei

bit,rel
Function:

Description:

Jump if Bit is set and Clear bit
If the indicated bit is one, branch to the address indicated; otherwise proceed with the next
instruction. The bit will not be cleared if it is already a zero. The branch destination is computed by adding the signed relative-displacement in the third instruction byte to the PC, after
incrementing the PC to the first byte of the next instruction. No flags are affected.
Note: When this instruction is used to test an output pin, the value used as the original data
will be read from the output data latch, not the input pin.

Example:

The Accumulator holds 56H (01010ll0B). The instruction sequence,
JBC ACC.3,LABELl
JBC ACC.2,LABEL2
will cause program execution to continue at the instruction identified by the label LABEL2,
with the Accumulator modified to 52H (0 101 00 lOB).

February 1989

1-81

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Section 1

User's Guide

8051 Family Programmer's Guide and Instruction Set

Bytes:

Cycles:

Encoding:

1..._0_0_0_-,-0_0_0_0-,

Operation:

JBC
(PC) +- (PC) + 3
IF (bit) = 1
THEN
(bit) +- 0
(PC) +- (PC)

bit address

reI. address

+ rei

rei
Function:
Description:

Example:

Jump if Carry is set
If the carry flag is set, branch to the address indicated; otherwise proceed with the next
instruction. The branch destination is computed by adding the signed relative-displacement in
the second instruction byte to the PC, after incrementing the PC twice. No flags are affected.

The carry flag is cleared. The instruction sequence,
JC
CPL
JC

LABELl
C
LABEL 2

will set the carry and cause program execution to continue at the instruction identified by the
label LABEL2.
Bytes:

Cycles:

Encoding:
Operation:

February 1989

I ° 1 0 0 I °0 0 0 I
JC
(PC) +- (PC) + 2
IF (C) = 1
THEN
(PC) +- (PC)

reI. address

reI

1-82

Signetics Microprocessor Products

Section 1

User's Guide

8051 Family Programmer's Guide and Instruction Set

JMP @A+DPTR
Function:

Jump indirect

Description:

Add the eight-bit unsigned contents of the Accumulator with the sixteen-bit data pointer, and
load the resulting sum to the program counter. This will be the address for subsequent instruction fetches. Sixteen-bit addition is performed (modulo 2 16): a carry-out from the low-order
eight bits propagates through the higher-order bits. Neither the Accumulator nor the Data
Pointer is altered. No flags are affected.

Example:

An even number from 0 to 6 is in the Accumulator. The following sequence of instructions will
branch to one of four AJMP instructions in a jump table starting at JMP_ TBL:
MOV
JMP
AJMP
AJMP
AJMP
AJMP

DPTR,#JMP_TBL
@A+DPTR
LABELO
LABELl
LABEL2
LABEL3

If the Accumulator equals 04H when starting this sequence, execution will jump to label
LABEL2. Remember that AJMP is a two-byte instruction, so the jump instructions start at
every other address.

Bytes:
Cycles:

Encoding:

101110011

Operation:

JMP
(PC) -

February 1989

(A)

(DPTR)

1-83

User's Guide

Signetics Microprocessor Products

8051 Family Programmer's Guide and Instruction Set

Section 1
JNB

blt,rel
Function:

Jump if Bit Not set

Description:

If the indicated bit is a zero, branch to the indicated address; otherwise proceed with the next
instruction. The branch destination is computed by adding the signed relative-displacement in
the third instruction byte to the PC, after incrementing the PC to the first byte of the next
instruction. The bit tested is not modified. No flags are affected.

Example:

The data present at input port 1 is llOOlOlOB. The Accumulator holds 56H (010101 lOB). The
instruction sequence,
JNB P1.3,LABELl
JNB ACC.3,LABEL2
will cause program execution to continue at the instruction at label LABEL2.

Bytes:

Cycles:

Encoding:
Operation:

JNC

10 0 1 1

0 0 0 0

JNB
(PC) +- (PC) + 3
IF (bit) = 0
THEN (PC) +- (PC)

bit address

reI. address

reI.

rei
Function:

Description:

Example:

Jump if Carry not set
If the carry flag is a zero, branch to the address indicated; otherwise proceed with the next
instruction. The branch destination is computed by adding the signed relative-displacement in
the second instruction byte to the PC, after incrementing the PC twice to point to the next
instruction. The carry flag is not modified.
The carry flag is set. The instruction sequence,
INC LABELl
CPL C
JNC LABEL2
will clear the carry and cause program execution to continue at the instruction identified by
the label LABEL2.

Bytes:

Cycles:

Encoding:

101010000

Operation:

JNC
(PC) +- (PC) + 2
IF (C) = 0
THEN (PC) +- (PC) + reI

February 1989

reI. address

1-84

Signetics Microprocessor Products

Section 1
JNZ

User's Guide

8051 Family Programmer's Guide and Instruction Set

rei
Function:

Description:

Jump if Accumulator Not Zero
If any bit of the Accumulator is a one, branch to the indicated address; otherwise proceed with

the next instruction. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC, after incrementing the PC twice. The
Accumulator is not modified. No flags are affected.
Example:

The Accumulator originally holds DOH. The instruction sequence,
JNZ LABELl
INC A
JNZ LABEL2
will set the Accumulator to OIH and continue at label LABEL2.

Bytes:

Cycles:

Encoding:

LI_0__1_1--1._0_0_0_0-,

Operation:

JNZ
(PC) - (PC) + 2
IF
(A) =F
THEN (PC) -

reI. address

(PC) + rei

rei
Function:
Description:

Example:

Jump if Accumulator Zero
If all bits of the Accumulator are zero, branch to the address indicated; otherwise proceed with
the next instruction. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC, after incrementing the PC twice. The
Accumulator is not modified. No flags are affected.
The Accumulator originally contains OIH. The instruction sequence,
JZ LABELl
DEC A
JZ LABEL2
will change the Accumulator to DOH and cause program execution to continue at the instruction identified by the label LABEL2.

Bytes:

Cycles:

Encoding:

Operation:

JZ
(PC) - (PC) + 2
IF
(A) =
THEN (PC) -

° 1 1 ° ° °° 0

February 1989

(PC)

reI. address

+ rei

1-85

User's Guide

Signetics Microprocessor Products

8051 Family Programmer's Guide and Instruction Set

Section 1
LCALL

addr16

Function:

(Not implemented in 8xC751 and 8xC752)

Long call

Description:

LCALL calls a subroutine located at the indicated address. The instruction adds three to the
program counter to generate the address of the next instruction and then pushes the 16-bit
result onto the stack (low byte first), incrementing the Stack Pointer by two. The high-order
and low-order bytes of the PC are then loaded, respectively, with the second and third bytes of
the LCALL instruction. Program execution continues with the instruction at this address. The
subroutine may therefore begin anywhere in the full 64K-byte program memory address space.
No flags are affected.

Example:

Initially the Stack Pointer equals 07H. The label "SUBRTN" is assigned to program memory
location 1234H. After executing the instruction,
LCALL SUBRTN
at location 0123H, the Stack Pointer will contain 09H, internal RAM locations OSH and 09H
will contain 26H and 01H, and the PC will contain 1235H.

Bytes:

Cycles:

Encoding:
Operation:

LJMP

_0_0_0_....l.-0_0_1_0...J

addr1S-addrB

addr7-addrO

LCALL
(PC) +- (PC) + 3
(SP) +- (SP) + 1
«SP» +- (PC7-O)
(SP) +- (SP) + I
«SP» +- (PCIS-S)
(PC) +- addf!5.0

addr16 (Implemented in 87C751 and 87C752, for use in in-circuit emulation).
Function:

Long Jump

Description:

UMP causes an unconditional branch to the indicated address, by loading the high-order and
low-order bytes of the PC (respectively) with the second and third instruction bytes. The
destination may therefore be anywhere in the full 64K program memory address space. No
flags are affected.

Example:

The label "JMPADR" is assigned to the instruction at program memory location 1234H. The
instruction,
UMP JMPADR
at location 0123H will load the program counter with 1234H.

Bytes:

Cycles:

Encoding:

1000010010

Operation:

UMP
(PC) +- addrl5-O

February 1989

addr1S-addrB

1-86

addr7 -addrO

Signetics Microprocessor Products

User's Guide

8051 Family Programmer's Guide and Instruction Set

Section 1

< dest-byte > , < src-byte >

MOV

Function:
Description:

Move byte variable
The byte variable indicated by the second operand is copied into the location specified by the
first operand. The source byte is not affected. No other register or flag is affected.
This is by far the most flexible operation. Fifteen combinations of source and destination
addressing modes are allowed.

Example:

Internal RAM location 30H holds 4OH. The value of RAM location 40H is 10H. The data
present at input port I is llOOlOlOB (OCAH).
MOV
MOV
MOV
MOV
MOV
MOV

RO,#30H ;RO <= 30H
A,@RO
;A <= 40H
Rl,A
;Rl < = 40H
R,@Rl
;B <= IOH
@Rl,Pl
;RAM (40H) < = OCAH
P2,Pl
;P2 #OCAH

leaves the value 30H in register 0, 40H in both the Accumulator and register 1, IOH in register
B, and OCAH (11001010B) both in RAM location 40H and output on port 2.

MOV A,Rn
Bytes:
Cycles:
Encoding:

11 1 1 0

Operation:

MOV
(A) -(Rn)

1r r r

"MOV A,dlrect
Bytes:

Cycles:
Encoding:

11 1 1 0

Operation:

MOV
(A) - (direct)

01 0 1

direct address

"MOV A,ACC Is not a valid Instruction.

February 1989

1-87

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Section 1

User's Guide

8051 Family Programmer's Guide and Instruction Set

MOV A,@RI
Bytes:
Cycles:
Encoding:

11 1 1 0

Operation:

MOV
(A) -

«Ri»

MOV A,#data
Bytes:

Cycles:
Encoding:

10 1 1 1

Operation:

MOV
(A)- #data

o1 0

immediate data

MOV Rn,A
Bytes:
Cycles:
Encoding:

I1 11 1

Operation:

MOV
(Rn) -

1 r r r

(A)

MOV Rn,dlrect
Bytes:

Cycles:

Encoding:

11 010

Operation:

MOV
(Rn) -

1 r r r

direct addr.

(direct)

MOV Rn,#data
Bytes:

Cycles:
Encoding:
Operation:

February 1989

01 1 1

MOV
(Rn) -

1 r r r

immediate data

#data

1-88

Si 9 netics M icrop rocessor Prod ucts

Section 1

User's Guide

8051 Family Programmer's Guide and Instruction Set

MOV dlrect,A
Bytes:

Cycles:
Encoding:

I 1111

Operation:

10 1

direct address

MOY
(direct) -

(A)

MOV dlrect,Rn
Bytes:

Cycles:

Encoding:
Operation:

000

direct address

1 r r r

MOY
(direct) -

(Rn)

MOV dlrect,dlrect
Bytes:

Cycles:

Encoding:
Operation:

11 000 o 1 0 1

dir. addr. (src)

dir. addr. (dest)

MOY
(direct) -

(direct)

MOV dlrect,@RI
Bytes:

Cycles:

Encoding:

11 000 o 1

Operation:

MOY
(direct) -

direct addr.

«Ri»

MOV direct, # data
Bytes:

Cycles:

2
1 1

Encoding:

101

Operation:

MOY
(direct) -

February 1989

o10

direct address

#data

1-89

immediate data 1

Signetlcs Microprocessor Products

Section 1

User's Guide

8051 Family Programmer's Guide and Instruction Set

MOV @RI,A
Bytes:
Cycles:

MOV

Encoding:

1 1 1 1 1

Operation:

MOV
«Ri» -

(A)

@RI,dlrect
Bytes:

Cycles:

Encoding:

11 0 1 0

Operation:

MOV
«Ri» -

direct addr.

(direct)

@RI,#data
Bytes:

Cycles:

MOV

Encoding:

101 11

Operation:

MOV
«RJ» -

o 1 ·1

immediate data

#data

,
Function:

Move bit data

Deacrlptlon:

The Boolean variable indicated by the second operand is copied into the location specified by
thef1I'St operand. One of the operands must be the carry flag; the other may be any directly
addressable bit. No other register or flag is affected.

Example:

The carry flag is originally set. The data present at input Port 3 is llOOOHilB. The data
previously written to output Port 1 is 35H (OOllOlOlB).
MOV P1.3,C
MOV C,P3.3
MOV P1.2,C

will leave the carry cleared and change Port 1 to 39H (OOlllOOlB).

February 1989

1-.90

Signetics Microprocessor Products

Section 1

User's Guide

8051 Family Programmer's Guide and Instruction Set

MOY C,blt
Bytes:

Cycles:

Encoding:

Operation:

MOY
(C) +- (bit)

001 0

bit address

001 0

bit address

MOY blt,C
Bytes:

Cycles:

Encoding:

11 0 0 1

Operation:

MOY
(bit) +- (C)

MOY DPTR,#data16
Function:
Description:

Load Data Pointer with a 16-bit constant
The Data Pointer is loaded with the 16-bit constant indicated. The 16-bit constant is loaded
into the second and third bytes of the instruction. The second byte (DPH) is the high-order
byte, while the third byte (DPL) holds the low-order byte. No flags are affected.
This is the only instruction which moves 16 bits of data at once.

Example:

The instruction,
MOY DPTR,#1234H
will load the value 1234H into the Data Pointer: DPH will hold 12H and DPL will hold 34H.

Bytes:

Cycles:

EncodIng:

110010000

OperatIon:

MOY
(DPTR) +- #datalS"()
DPH 0 DPL +- #datalS_S 0 #data7"()

February 1989

immed. data15-8

1-91

immed. data7-0

Signetics Microprocessor Products

Section 1

User's Guide

8051 Family Programmer's Guide and Instruction Set

MOVC A,@A+
Function:

Move Code byte

Description:

The MOVC instructions load the Accumulator with a code byte, or constant from program
memory. The address of the byte fetched is the sum of the original unsigned eight-bit Accumulator contents and the contents of a sixteen-bit base register, which may be either the Data
Pointer or the PC. In the latter case, the PC is incremented to the address of the following
instruction before being added with the Accumulator; otherwise the base register is not altered. Sixteen-bit addition is performed so a carry-out from the low-order eight bits may
propagate through higher-order bits. No flags are affected.

Example:

A value between 0 and 3 is in the Accumulator. The following instructions will translate the
value in the Accumulator to one of four values defined by the DB (define byte) directive.
RELJC:

INC

MOVC A,@A+PC
RET
DB

66H

77H

88H

99H

If the subroutine is called with the Accumulator equal to OIH, it will return with 77H in the
Accumulator. The INC A before the MOVC instruction is needed to "get around" the RET
instruction above the table. If several bytes of code separated the MOVC from the table, the
corresponding number would be added to the Accumulator instead.

MOVC A,@A+DPTR
Bytes:

Cycles:

Encoding:

11 0 0 1

Operation:

MOVC
(A) +- «A) + (DPTR))

0 0 1 1

MOVC A,@A + PC
Bytes:
Cycles:

Encoding:

11000

Operation:

MOVC
(PC) +- (PC) + I
(A) +- «A) + (PC))

February 1989

0011

1-92

Si gnetics Microprocessor Prod ucts

Section 1
MOVX

8051 Family Programmer's Guide and Instruction Set

,
Function:

Description:

User's Guide

(Not implemented in 8xC751 and 8xC752)

Move External
The MOVX instructions transfer data between the Accumulator and a byte of external data
memory, hence the "X" appended to MOV. There are two types of instructions, differing in
whether they provide an eight-bit or sixteen-bit indirect address to the external data RAM.
In the first type, the contents of RO or R I in the current register bank provide an eight-bit
address multiplexed with data on PO. Eight bits are sufficient for external I/O expansion
decoding or for a relatively small RAM array. For somewhat larger arrays, any output port
pins can be used to output higher-order address bits. These pins would be controlled by an
output instruction preceding the MOVX.
In the second type of MOVX instruction, the Data Pointer generates a sixteen-bit address. P2
outputs the high-order eight address bits (the contents of DPH) while PO multiplexes the loworder eight bits (DPL) with data. The P2 Special Function Register retains its previous contents while the P2 output buffers are emitting the contents of DPH. This form is faster and
more efficient when accessing very large data arrays (up to 64K bytes), since no additional
instructions are needed to set up -.!he output ports.
It is possible in some situations to mix the two MOVX types. A large RAM array with its

high-order address lines driven by P2 can be addressed via the Data Pointer, or with code to
output high-order address bits to P2 followed by a MOVX instruction using RO or R I.
Example:

An external 256 byte RAM using multiplexed addressldata lines is connected to
the 8051 Port O. Port 3 provides control lines for the external RAM. Ports 1
and 2 are used for normal 1/0. Registers 0 and 1 contain 12H and 34H. Location 34H of the external RAM holds the value 56H. The instruction sequence,

MOVX

A,@RI

MOVX

@RO,A

copies the value 56H into both the Accumulator and external RAM location 12H.

February 1989

1-93

Signetics Microprocessor Products

Section 1
MOVX

User's Guide

8051 Family Programmer's Guide and Instruction Set

A,@Ri
Bytes:
Cycles:

Encoding:

11 1 1 0

Operation:

1 i

MOVX

(A) MOVX

«Ri»

A,@DPTR
Bytes:
Cycles:

Encoding:
Operation:

11 1 1 0
MOVX

(A) MOVX

0000

«DPTR»

@RI,A
Bytes:
Cycles:

Encoding:
Operation:

11 1 1 1
MOVX

«Ri» MOVX

001

(A)

@DPTR,A
Bytes:
Cycles:

Encoding:
Operation:

11 1 1 1

0 0 0 0

MOVX

(DPTR)-(A)

February 1989

1-94

Signetics Microprocessor Products

Section 1

User's Guide

8051 Family Programmer's Guide and Instruction Set

NOP
Function:

No Operation

Description:

Execution continues at the following instruction. Other than the PC, no registers or flags are
affected.

Example:

It is desired to produce a low-going output pulse on bit 7 of Port 2 lasting exactly 5 cycles. A
simple SETB/CLR sequence would generate a one-cycle pulse, so four additional cycles must
be inserted. This may be done (assuming no interrupts are enabled) with the instruction
sequence,

CLR
NOP
NOP
NOP
NOP
SETB

P2.7

Bytes:
Cycles:
Encoding:
Operation:

I0 0 0 0 I 0 0 0 0
NOP
(PC) +- (PC)

MUL AB
Function:

Multiply

Description:

MUL AB multiplies the unsigned eight-bit integers in the Accumulator and register B. The
low-order byte of the sixteen-bit product is left in the Accumulator, and the high-order byte in
B. If the product is greater than 255 (OFFH) the overflow flag is set; otehrwise it is cleared.
The carry flag is always cleared.

Example:

Originally the Accumulator holds the value 80 (SOH). Register B holds the value 160 (OAOH).
The instruction,
MUL

will give the product 12,800 (32ooH), so B is changed to 32H (oollooIOB) and the Accumulator is cleared. The overflow flag is set, carry is cleared.
Bytes:
Cycles:

Encoding:

Operation:

February 1989

1 0 1 0

0 1 0 0

MUL
(Ah_o +- (A) X (B)
(Bhs.8

1-95

User's Guide

Signetics Microprocessor Products

8051 Family Programmer's Guide and Instruction Set

Section 1
ORL

Function:

Description:

Logical-OR for byte variables
ORL performs the bitwise logical-OR operation between the indicated variables, storing the
results in the destination byte. No flags are affected.
The two operands allow six addressing mode combinations. When the destination is the Accumulator, the source can use register, direct, register-indirect, or immediate addressing; when
the destination is a direct address, the source can be the Accumulator or immediate data.

Note: When this instruction is used to modify an output port, the value used as the original
port data will be read from the output data latch, not the input pins.
Example:

If the Accumulator holds OC3H (! lOOOOIIB) and RO holds 55H (OIOIOIOIB) then the instruction,
ORL A,RO
will leave the Accumulator holding the value OD7H (lIOIOIIIB).
When the destination is a directly addressed byte, the instruction can set combinations of bits
in any RAM location or hardware register. The pattern of bits to be set is determined by a
mask byte, which may be either a constant data value in the instruction or a variable computed
in the Accumulator at run-time. The instruction,
ORL Pl,#OOIlOOIOB
will set bits 5, 4, and 1 of output Port 1.

ORL A,Rn
Bytes:
Cycles:
Encoding:
Operation:

February 1989

I0 1 0 0
ORL
(A) -

1 r r r

(A) V (Rn)

1-96

Signetics Microprocessor Products

Section 1

ORL

User's Guide

8051 Family Programmer's Guide and Instruction Set

A,direct
Bytes:

Cycles:

I0 10 1 I

Encoding:

10100

Operation:

ORL
(A) +- (A) V (direct)

direct address

ORL A,@Ri
Bytes:
Cycles:

Encoding:

101

Operation:

ORL
(A) +- (A) V «Ri))

ORL A,#data
Bytes:

Cycles:
Encoding:

I 0 1 0 0 I 0 1 oOl

Operation:

ORL
(A) +- (A) V # data

immediate data

ORL direct,A
Bytes:

Cycles:

ORL

Encoding:

10100 I 0 0 1 0 I

Operation:

ORL
(direct) +- (direct) V (A)

direct address

direct, # data
Bytes:

Cycles:

Encoding:

101

Operation:

ORL
(direct) +- (direct) V # data

February 1989

001 1

direct addr.

1-97

immediate data

User's Guide

Signetics Microprocessor Products

8051 Family Programmer's Guide and Instruction Set

Section 1
ORL C, < src-blt >
Function:
Description:

Example:

Logical-OR for bit variables
Set the carry flag if the Boolean value is a logical I; leave the carry in its current state
otherwise. A slash ("I") preceding the operand in the assembly language indicates that the
logical complement of the. addressed bit is used as the source value, but the source bit itself is
not affected. No other flags are affected.

Set the carry flag if and only if Pl.O

= I, ACC. 7 =

= 0:

MOV C,Pl.O

;LOAD CARRY WITH INPUT PIN PIO

ORL C,ACC.7

;OR CARRY WITH THE ACC. BIT 7

ORL C,IOV

;OR CARRY WITH THE INVERSE OF OV.

ORL C,blt
Bytes:

Cycles:

Encoding:

1 01 1 1

Operation:

ORL
(C) -

001 0

bitaddress

ORL C,/blt
Bytes:

Cycles:

Encoding:

11 0 1 0 1 0000

Operation:

ORL
(C) -

February 1989

I, or OV

1-98

Si 9 netics Microprocessor Prod ucts

Section 1
POP

User's Guide

8051 Family Programmer's Guide and Instruction Set

direct
Function:

Pop from stack.

Description:

The contents of the internal RAM location addressed by the Stack Pointer is read, and the
Stack Pointer is decremented by one. The value read is then transferred to the directly addressed byte indicated. No flags are affected.

Example:

The Stack Pointer originally contains the value 32H, and internal RAM locations 30H
through 32H contain the values 20H, 23H, and OIH, respectively. The instruction sequence,
POP

DPH

POP

DPL

will leave the Stack Pointer equal to the value 30H and the Data Pointer set to 0123H. At this
point the instruction,
POP

will leave the Stack Pointer set to 20H. Note that in this special case the Stack Pointer was
decremented to 2FH before being loaded with the value popped (20H).
Bytes:

Cycles:

Encoding:
Operation:

PUSH

_1__0_1-,-_0_0_0_0-,

direct addr~

POP
(direct) - «SP))
(SP) - (SP) - I

direct
Function:

Push onto stack

Description:

The Stack Pointer is incremented by one. The contents of the indicated variable is then copied
into the internal RAM location addressed by the Stack Pointer. Otherwise no flags are affected.

Example:

On entering an interrupt routine the Stack Pointer contains 09H. The Data Pointer holds the
value 0123H. The instruction sequence,
PUSH

DPL

PUSH

DPH

will leave the Stack Pointer set to OBH and store 23H and OIH in internal RAM locations
OAH and OBH, respectively.
Bytes:

Cycles:

Encoding:
Operation:

February 1989

1 1

° ° ° °°
0

direct address

PUSH
(SP) - (SP) + I
«SP)) - (direct)

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Section 1

User's Guide

8051 Family Programmer's Guide and Instruction Set

RET
Function:

Return from subroutine

Description:

RET pops the high- and low-order bytes of the PC successively from the stack, decrementing
the Stack Pointer by two. Program execution continues at the resulting address, generally the
instruction immediately following an ACALL or LCALL. No flags are affected.

Example:

The Stack Pointer originally contains the value OBH. Internal RAM locations OAH and OBH
contain the values 23H and OlH, respectively. The instruction,
RET
will leave the Stack Pointer equal to the value 09H. Program execution will continue at
location 0123H.

Bytes:
Cycles:

Encoding:

100100010

Operation:

RET
(PCIS-S) +- «SP»
(SP) +- (SP) - 1
(PC7-O) +- «SP»
(SP) +- (SP) - 1

RETI
Function:

Return from interrupt

Description:

RETI pops the high- and low-order bytes of the PC successively from the stack, and restores
the interrupt logic to accept additional interrupts at the same priority level as the one just
processed. The Stack Pointer is left decremented by two. No other registers are affected; the
PSW is not automatically restored to its pre-interrupt status. Program execution continues at
the resulting address, which is generally the instruction immediately after the point at which
the interrupt request was detected. If a lower- or same-level interrupt had been pending when
the RETI instruction is executed, that one instruction will be executed before the pending
interrupt is processed.

Example:

The Stack Pointer originally contains the value OBH. An interrupt was detected during the
instruction ending at location 0122H. Internal RAM locations OAH and OBH contain the
values 23H and OlH, respectively. The instruction,
RETI
will leave the Stack Pointer equal to 09H and return program execution to location 0123H.

Bytes:
Cycles:

Encoding:

1_0_0
.... _ _-'-0_0_1_0--,

Operation:

RETI
(PCIS-S) +- «SP»
(SP)- (SP) - 1
(PC7-O) +- «SP»
(SP) +- (SP) - 1

February 1989

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Signetics Microprocessor Products

Section 1
RL

User's Guide

8051 Family Programmer's Guide and Instruction Set

Function:
Description:
Example:

Rotate Accumulator Left
The eight bits in the Accumulator are rotated one bit to the left. Bit 7 is rotated into the bit 0
position. No flags are affected.
The Accumulator holds the value OC5H (llOOOIOIB). The instruction.
RL

leaves the Accumulator holding the value 8BH (lOOOIOIIB) with the carry unaffected.

Bytes:
Cycles:
Encoding:
Operation:

0 0 1 0

0 0 1 1

CAn+l)_CAn). n
CAO)-CA7)

RLC

0 - 6

Function:

Rotate Accumulator Left through the Carry flag

Description:

The eight bits in the Accumulator and the carry flag are together rotated one bit to the left. Bit
7 moves into the carry flag; the original state of the carry flag moves into the bit 0 position. No
other flags are affected.

Example:

The Accumulator holds the value OC5H (lIOOOIOIB). and the carry is zero. The instruction.
RLC

leaves the Accumulator holding the value 8BH (IOOOIOIOB) with the carry set.

Bytes:
Cycles:
Encoding:
Operation:

_0_0_1_-,-_0_0_1_1-.1

1-1

RLC
CAn+l)~(An). n - 0 - 6

CAO)-CC)
CC)-CA7)

February 1989

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Section 1

8051 Family Programmer's Guide and Instruction Set

RR A

Function:
Description:
Example:

Rotate Accumulator Right
The eight bits in the Accumulator are rotated one bit to the right. Bit 0 is rotated into the bit 7
position. No flags are affected.
The Accumulator holds the value OCSH (I 1000 101 B). The instruction.
RR

leaves the Accumulator holding the value OE2H (llIOOOIOB) with the carry unaffected.

Bytes:
Cycles:
Encoding:

1000010011

Operation:

RR
(An) _(An+l). n
(A7)-(AO)

0 - 6

RRC A

Function:
Description:

Example:

Rotate Accumulator Right through Carry flag
The eight bits in the Accumulator and the carry flag are together rotated one bit to the right.
Bit 0 moves into the carry flag; the original value of the carry flag moves into the bit 7
position. No other flags are affected.
The Accumulator holds the value OCSH (1 100010 1B). the carry is zero. The instruction.
RRC

leaves the Accumulator holding the value 62 (0 llOOO lOB) with the carry set.

Bytes:
Cycles:
Encoding:

100010011

Operation:

RRC
(An) - (An+l). n - 0 - 6
(A7) - (C)
(C)- (AO)

February 1989

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Signetics Microprocessor Products

Section 1

8051 Family Programmer's Guide and Instruction Set

SETB

Function:

Set Bit

Description:

SETB sets the indicated bit to one. SETB can operate on the carry flag or any directly
addressable bit. No other flags are affected.

Example:

The carry flag is cleared. Output Port 1 has been written with the value 34H (001 101OOB). The
instructions,
SETB C
SETB Pl.O
will leave the carry flag set to 1 and change the data output on Port 1 to 35H (001lO101B).

SETB

C
Bytes:
Cycles:
Encoding:

Operation:

I1 10 1

001 1

SETB
(C)-l

SETB

bit
Bytes:

Cycles:
Encoding:

11 1 0 1

Operation:

SETB
(bit) -

February 1989

001 0

bit address

1-103

Signetics Microprocessor Products

Section 1
SJMP

User's Guide

8051 Family Programmer's Guide and Instruction Set

rei
Function:

Short Jump

Description:

Program control branches unconditionally to the address indicated. The branch destination is
computed by adding the signed displacement in the second instruction byte to the PC, after
incrementing the PC twice. Therefore, the range of destinations allowed is from 128 bytes
preceding this instruction to 127 bytes following it.

Example:

The label "RELADR" is assigned to an instruction at program memory location 0123H. The
instruction,
SJMP RELADR
will assemble into location OIOOH. After the instruction is executed, the PC will contain the
value 0123H.
(Note: Under the above conditions the instruction following SJMP will be at 102H. Therefore,
the displacement byte of the instruction will be the relative offset (0123H-0102H) = 21H. Put
another way, an SJMP with a displacement of OFEH would be a one-instruction infinite loop.)

Bytes:

Cycles:

Encoding:
Operation:

February 1989

I10 0 0

0 0 0 0

SJMP
(PC) +- (PC)
(PC) +- (PC)

+
+

I reI. address

2
rei

1-104

Signetics Microprocessor Products

Section 1
SUBB

User's Guide

8051 Family Programmer's Guide and Instruction Set

A,
Function:

Description:

Subtract with borrow
SUBB subtracts the indicated variable and the carry flag together from the Accumulator,
leaving the result in the Accumulator. SUBB sets the carry (borrow) flag if a borrow is needed
for bit 7, and clears C otherwise. (If C was set before executing a SUBB instruction, this
indicates that a borrow was needed for the previous step in a multiple precision subtraction, so
the carry is subtracted from the Accumulator along with the source operand.) AC is set if a
borrow is needed for bit 3, and cleared otherwise. OV is set if a borrow is needed into bit 6, but
not into bit 7, or into bit 7, but not bit 6.
When subtracting signed integers OV indicates a negative number produced when a negative
value is subtracted from a positive value, or a positive result when a positive number is
subtracted from a negative number.
The source operand allows four addressing modes: register, direct, register-indirect, or immediate.

Example:

The Accumulator holds OC9H (llOOIOOlB), register 2 holds 54H (OIOlOlOOB), and the carry
flag is set. The instruction,
SUBB

A.R2

will leave the value 74H (01 110100B) in the accumulator, with the carry flag and AC cleared
but OV set.
Notice that OC9H minus 54H is 75H. The difference between this and the above result is due
to the carry (borrow) flag being set before the operation. If the state of the carry is not known
before starting a single or multiple-precision subtraction, it should be explicitly cleared by a'
CLR C instruction.
.

SUBB A,Rn
Bytes:
Cycles:
Encoding:
Operation:

February 1989

1 r r r
SUBB
(A) -- (A) - (C) - (Rn)

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Section 1

User's Guide

8051 Family Programmer's Guide and Instruction Set

SUBB A,dlrect
Bytes:

C'ycles:
Encoding:

,. 1 0 0 1

Operation:

SUBB
(A) . - (A) - (C) - (direct)

SUBB

0 1 0 1

direct address

A,@RI
Bytes:
Cycles:
Encoding:

I1 0 0 1

Operation:

SUBB

0 1 1

(A) . - (A) - (C) -

«Ri»

SUBB A,#data
Bytes:

Cycles:
Encoding:
Operation:

I10 0 1

0 1 0 0

immediate data

SUBB
(A) . - (A) - (C) - #data

SWAP A
Function:
Description:

Example:

Swap nibbles within the Accumulator
SWAP A interchanges the low- and high-order nibbles (four-bit fields) of the Accumulator
(bits 3-0 and bits 7-4). The operation can also be thought of as a four-bit rotate instruction. No
flags are affected.
The Accumulator holds the value OC5H (lIOOOIOIB). The instruction,
SWAP A
leaves the Accumulator holding the value 5CH (0101 I IOOB).

Bytes:
Cycles:
Encoding:

I1 10 0

Operation:

SWAP

0 1 0 0

(A3-0) -;:: (A7-4)

February 1989

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Signetics Microprocessor Products

Section 1

User's Guide

8051 Family Programmer's Guide and Instruction Set

XCH A,
Function:

Exchange Accumulator with byte variable

Description:

XCH loads the Accumulator with the contents of the indicated variable, at the same time
writing the original Accumulator contents to the indicated variable. The source/destination
operand can use register, direct, or register-indirect addressing.

Example:

RO contains the address 20H. The Accumulator holds the value 3FH (OOllllllB). Internal
RAM location 20H holds the value TSH (01110101B). The instruction,
XCH A,@RO

will leave RAM location 20H holding the values 3FH (OOI11111B) and 75H (0111010lB) in
the accumulator.
XCH

A,Rn
Byte.:
Cycle.:
Encoding:

11 100

Operation:

XCH
(A) ~ (Rn)

r r r

XCH A,dlrect
Byte.:

Cycle.:

Encoding:

11 100

Operation:

XCH
(A) ~ (direct)

0 1

direct address

XCH A,@RI
Byte.:
Cycle.:
Encoding:

11 100

Operation:

XCH
(A) ~

February 1989

1 i

«Ri»

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Signetics Microprocessor Products

8051 Family Programmer's Guide and Instruction Set

Section 1
XCHD

A,@RI

Function:

Exchange Digit

DescriptIon:

XCHD exchanges the low-order nibble of the Accumulator (bits 3-0), generally representing a
hexadecimal or BCD digit, with that of the internal RAM location indirectly addressed by the
specified register. The high-order nibbles (bits 7-4) of each register are not affected. No flags
are affected.

Example:

RO contains the address 2OH. The Accumulator holds the value 36H (00 11 0 110B). Internal
RAM location 20H holds the value 75H (OIIIOIOIB). The instruction,
XCHD

A,@RO

will leave RAM location 20H holding the value 76H (011101 lOB) and 35H (00110101B) in the
Accumulator.

Bytes:
Cycles:

XRL

EncodIng:

11101011

OperatIon:

XCHD
(A3-O) -;.

«Ri3-O»

< dest-byte >,
FunctIon:

DescrIptIon:

Logical Exclusive-OR for byte variables
XRL performs the bitwise logical Exclusive-OR operation between the indicated variables,
storing the results in the destination. No flags are affected.
The two operands allow six addressing mode combinations. When the destination is the Accumulator, the source can use register, direct, register-indirect, or immediate addressing; when
the destination is a direct address, the source can be the Accumulator or immediate data.

(Note: When this instruction is used to modify an output port, the value used as the original
port data will be read from the output data latch, not the input pins.)

Example:

If the Accumulator holds OC3H (11000011B) and register 0 holds OAAH (10101OIOB) then
the instruction,
XRL

A,RO

will leave the Accumulator holding the value 69H (01101001B).
When the destination is a directly addressed byte, this instruction can complement combinations of bits in any RAM location or hardware register. The pattern of bits to be complemented is then determined by a mask byte, either a constant contained in the instruction or a
variable computed in the Accumulator at run-time. The instruction,
XRL

Pl,#00110001B

will complement bits 5, 4, and 0 of output Port 1.

February 1989

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8051 Family Programmer's Guide and Instruction Set

XRL A,Rn
Bytes:
Cycles:
Encoding:
Operation:

I0 1 1 0

1 r r r

XRL
(A) +- (A) ¥ (Rn)

XRL A,direct
Bytes:

Cycles:
Encoding:
Operation:

I0 1 1 0

0 1

direct address

XRL
(A) +- (A) ¥ (direct)

XRL A,@RI
Bytes:
Cycles:
Encoding:
Operation:

01 1 0

XRL
(A) +- (A) ¥

1 i

«Ri»

XRL A,#data
Bytes:

Cycles:
Encoding:
Operation:

01 1 0

o10

immediate data

XRL
(A) +- (A) ¥ #data

XRL dlrect,A
Bytes:

Cycles:
Encoding:
Operation:

01 1 0

001 0

direct address

XRL
(direct) +- (direct) ¥ (A)

February 1989

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User's Guide

Signetics Microprocessor Products

Section 1

8051 Family Programmer's Guide and Instruction Set

XRL dlrect,#dMa

Bytes:

Cycles:

Encoding:
Operation:

I 0 1 1 0 I 0 0 1 1 I I direct address I I immediate data I
XRL

(direct) +- (direct) ¥ #data

February 1989

1-110

Signetics Microprocessor Products

User's Guide

Section 1

8051 Family EPROM Products

EPROM PRODUCTS
All 80C51 derivative products offered by Signetics are
supported with an EPROM version. Currently available
EPROM parts are the 87C51, 87C451, and the 87C751.
EPROM versions of the 83C552, 83C652, and 83C752
are now in development.
All EPROM products are available in both windowed
DIP and OTP package configurations. The windowed
DIP package allows the EPROM to be erased under a
strong UV light source making program development
easier and faster. The OTP (One Time Programmable)
version cannot be erased because there is no window
through which the die could be exposed to UV light.
While the EPROM can only be programmed once in the
OTP package, the part costs less than in windowed DIP
and therefore offers an advantage for those not desiring
to use the masked ROM version of the part.
The EPROM products are fully supported on the industry
standard EPROM programmers.

PROGRAMMING THE 87C51, 87C451 AND 87C552
The setup for programming the microcontroller is shown
in Figure 59. Note that the part is running with a 4 to 6
MHz oscillator. The clock must be running because the
device is executing internal address and program data
transfers during the programming.

To program the SC87C51, SC87C451, or SC87C552, the
address of the EPROM location to be programmed is
applied to ports 1 and 2 as shown in Figure 59. The
code byte to be programmed into this location is applied
to port O. RST, PSEN and the pins of ports 2 and 3
specified in Table 20 are held at the "Program Code
Data" levels specified in the table. The ALE/PROG is
then pulsed low 25 times to program the addressed location.

ENCRYPTION TABLE
The encryption table is a feature of the SC87C51, and
its derivatives, that protects the code from being easily
read by anyone other than the programmer. The encryption table is 16 bytes of code that are exclusive NORed
with the program code data as it is read out. The first
byte is XNORed with the first location read, the second
with the second read, etc. through the sixteenth byte
read. The seventeenth byte is XNORed with the first byte
of the encryption table, the eighteenth with the second,
etc. and on in sixteen byte groups.
After the Encryption table has been programmed the user has to know its contents in order to correctly decode
the program code data. The encryption table itself cannot be read out.
The encryption table is programmed in the same manner
as the program memory, but using the "Pgm Encryption
Table" levels specified in Table 20. After the encryption
table is programmed verification cycles will produce only
encrypted information.

+5V

Vee

IA
A 0-A7

4-6MHz

RST

EA/vpp

P3.6

ALE/P"ROO

P3.7

SC87C51

XTAL2

PGM DATA
+12.75V
25 100us PULSES
TO GROUND

PsEN
P2.7

=~
P2.6

P2.0
-P2.3 I ~

XTAL1
~ Vss

,--

Figure 59. Programming Configuration

February 1989

1-111

A8-A11

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Signetics Microprocessor Products

User's Guide

8051 Family EPROM Products

Section 1
Table 20. EPROM Programming Modes

RST

PSEN

ALE/PROG

EA/Vpp

P2.7

P2.6

P3.7

P3.6

Read signature

MODE

Program code data

O·

Vpp

Verify code data
Pgm encryption table

1
1

0
0

O·

Vpp

0
1

0
0

1
1

1
0

Pgm lock bit 1

O·

Vpp

Pgm lock bit 2

o·

Vpp

NOTES:
1. "0" = valid low for that pin, "1" = valid high for that pin.
12.7SV ±O.2SV.
2. Vpp
3. Vee = 5V ±10% during programming and verification.
"ALE/PROG receives 25 programming pulses while Vpp is held at 12.75V. Each programming pulse is low for lOOI1S
(±101lS) and high for a minimum of lOllS.

LOCK BIT

PROGRAM VERIFICATION

There are two lock bits on the SC87C51 that, when set,
prevent the program data memory from being read out
or programmed further. To program the lock bits repeat
the programming sequence using the "Pgm Lock Bit"
levels specified in Table 20.

If lock bit 2 has not been programmed the on-chip program memory can be read out for program verification.
To verify the contents of the program memory, the address of the location to be read is applied to ports 1 and
2 as shown in Figure 60. The other pins are held at the
"Verify Code Data" levels indicated in Table 20. The
contents of the addressed location will appear on port O.
For this operation external pull-ups are required on port
o as shown in figure 60. Note that if the encryption table
has been programmed the data presented at port 0 will
be the exclusive NOR of the program byte with a byte
from the encryption table.

After the first lock bit is programmed, further programming of the code memory or the encryption table is disabled. The other lock bit can of course still be programmed. With only lock bit one programmed, the
memory can still be read out for program verification.
After the second lock bit is programmed, it is no longer
possible to read out (verify) the program memory.

+5V

Vee

P0l-_~'; PGM DATA

AO-A7 - - - - , I I Pl

----oI

RST

- _ _--oj P3.6
_ _ _........ P3.7

EA/vpp I t - - - ALE/PROG I t - - - -

SC87C51

r--_._--I XTAL2

PSEN 1"----

P2.7 10----- 0

(ENABLE)

P2.6 I t - - - - 0

P2.0 11'---- AS-All
-P2.3,v----

'---......-+-1 XTAL 1
Vss

Figure 60. Program Verification

February 1989

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User's Guide

Signetics Microprocessor Products

8051 Family EPROM Products

Section 1
SIGNATURE BYTES
The SC87C51 contains two signature bytes that can be
read and used by an EPROM programming system to
identifY the device. The signature bytes identifY the device as an SC87C51 manufactured by Signetics .
The signature bytes are read by the same procedure as a
normal verification of locations 030H and 031H, except
that P3.6 and P3.7 need to be pulled to a logic low. The
values are:
(030H)
(031H)

=
=

ISH indicates the part made by Signetics
90H 87C451
94H 87C552
9lH 87C751
95H 87C752
92H 87C51
96H 87C550
93H 87C652
97H 87C52

EPROM ERASURE
Erasure of the EPROM occurs when the chip is exposed
to light with wavelengths shorter than 4000 angstroms.
Sunlight and fluorescent lighting have wavelengths in this
range, so exposure to these light sources over an extended period of time (about I week in sunlight, or 3
years in room level fluorescent lighting) could cause inadvertent erasure. It is recommended, for this reason,
that an opaque label be placed over the window. If the
part is Subject to elevated temperatures or an environment
where solvents are used, Kapton tape (Fluorglas part number
2345-5 or its equivalent) can be used.
The recommended erasure procedure is to expose the
chip to ultraviolet light (at 2537 angstroms) to an integrated dose of at least 15W-sec/cm2. Exposing the
EPROM to an ultraviolet lamp of 12,OOOJ.LW/cm2 rating
for 20 to 40 minutes, at a distance of I inch, is adequate.
PROGRAMMING THE 87C751 AND 87C752
The 87C751 and 87C752 are programmed using a Quickpulse programming algorithm that is similar to that used
for the 87C51. It differs from the 87CSl in that a serial
data stream is used to place the 87C751 in the programming mode.
Figure 61 shows a block diagram of the programming
configuration for the 87C751. Port pin PO.2 is used for
the programming voltage supply input (Vpp signal). Port
pin PO.I is used for the program (PGM) signal.
Port 3 accepts the address input for the EPROM location to be programmed. Both the high and low components of the eleven bit address are presented to the part
through port 3. Multiplexing of the address components
is performed using ASEL (PO.O).
Port 1 is used as a bidirectional data bus during programming and verifY operations. During the programming mode, it accepts the byte to be programmed. In
the verifY mode, it returns the contents of the specified
address location.

February 1989

The Xl pin is the oscillator input and receives the master system clock. This clock should be between 1.2 and
6MHz.
The RESET pin is used to accept the serial data stream
that places the 87C75l into various programming modes.
This pattern consists of a 10-bit code with the LSB sent
first. Each bit is synchronized to the clock input Xl.
To program the 87C7Sl the part must be put into the
programming mode by presenting the proper serial code
(see Table 21) to the RESET pin. To do this RESET
should be held high for at least two machine cycles. Port
pins PO.l and PO.2 will be at VOH as a result of this,
but they must be driven high prior to sending the serial
data stream on the RESET pin. The serial data bits can
now be transmitted over the RESET pin placing the
87C75l into one of the programming modes. Following
the transmission of the last data bit the reset pin should
be held low.
Next the address information for the location to be programmed is placed on Port 3 and ASEL is used to perform the address mUltiplexing. ASEL should be driven
high and then Port 3 driven with the high order address
bits. ASEL is then driven low latching the high order
bits internally. Port 3 can now be driven with the low 8
bits of the address, completing the addressing of the location to be programmed.
A high voltage Vpp level is now applied to the Vpp input. This sets Port 1 as an input port. The data to be
programmed to the EPROM array should be placed on
Port 1. A series of 25 programming pulses is now applied to the PGM pin (PO.l) to program the addressed
EPROM location.
PROGRAM VERIFICATION
The EPROM array can be verified by placing the part in
the programming mode as described above and forcing
the Vpp pin to the VOH level. Four machine cycles after
addressing a location the contents of the addressed location will appear on Port 1.
87C751 AND 87C752 SIGNATURE BYTES
The signature bytes for the 87C75l and 87C752 are read
differently and are in different locations than those on
the 87C51. Due to its reduced pin count, the part has to
be put into "Signature Byte Read Mode" by placing a 10bit serial data stream on the Reset pin. The proper code
and the conditions of PO.l and PO.2, for this mode, are
shown in Table 21.
Once the part has been placed into the Signature Byte
Read Mode, the signature bytes can be read by the same
procedure as a normal verification of locations OlEH
and OlFH. The values are:
OlEH = ISH indicates the part was made by Signetics
OlFH = 9lH - 87C751
01FH = 95H - 87C752

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8051 Family EPROM Products

Section 1
PROGRAMMING FEATURES
The 87C7S1 has all of the special programming features
incorporated within its EPROM array that the 87CSI
has. It has an encryption key table and two security bits
(lock bits). These function exactly as they do in the
87CS1. They are programmed or verified by sending the
proper code over the RESET pin (see table 21) and then
following the 87C7S1 programming procedure as described previously.
ERASURE CHARACTERISTICS

The erasure procedure is exactly the same as that described for the 87CS1.
Table 21. Implementing ProgramlVerify Modes
Operation
Program user EPROM
Verify user EPROM
Program key EPROM
Verify key EPROM
Program security bit 1
Program security bit 2
Verify security bits
Read siJl;nature bytes

Serial Code
296H
296H
292H
292H
29AH
298H
29AH
19CH

PO.l (pGMI)

PO.2 (Vpp)

Vpp
VIH
Vpp
VIH
Vpp
Vpp
VIH
VIH

VIH

-.-.

VIH
VIH
VIH

NOTE.

*Pulsed from V IH to V 1L and returned to VIII'

87C751
Vee _ + l I V

AO-A7/AB-AIO

PJ.O-PJ.7

ADDRESS S11IOBE

PO.O/ASEL

Vss

PI.D-Pl.7
PROGRAMMING
PULSES

PO.I

Vpp/VIH ~~
CLK SOURCE

PO.2

RESET
CONTROL
LOGIC

XTALI

I
I

RESET

Figure 61. Programming Configuration

February 1989

1-114

DATA BUS

Signetics

SCN8031 AH/SCN8051 AH
Single-Chip 8-Bit Microcontroller
Product Specification

Microprocessor Division

DESCRIPTION
The Signetics SCN8031AH/SCN8051AH
is a high-performance microcontroller
fabricated using the Signetics highly reliable +5V, depletion-load, N-channel, sillcon-gate, N500 MOS process technology. It provides the hardware features,
architectural enhancements and instructions that are necessary to make it a
powerful and cost-effective controller for
applications requiring up to 64K bytes of
program memory and/or up to 64K bytes
of data storage.
The SCN8051AH contains a 4K X 8
read-only program memory, a 128 X 8
read/write data memory, 32 I/O lines,
two 16-bit timer/counters, a five-50urce
two-priority-level nested interrupt structure, a serial I/O port for either multiprocessor communications, I/O expansion, or full-duplex UART, and on-chip
oscillator and clock circuits. The SCN8031 AH is identical, except that it lacks
the program memory. For systems that
require extra capability, the SCN8051AH
can be expanded using standard TTL
compatible memories and byte oriented
peripheral controllers.

FEATURES
• Reduced supply current
• 4K X 8 ROM (SCN8051AH)
.128 X 8 RAM
• Four 8-bit ports, 32 I/O lines
• Two 16-bit timerlevent
counters
• High-performance full-duplex
serial channel
• External memory expandable to
128K
• Boolean processor
• Industry standard 8051
architecture:
Non-paged jumps
- Direct addressing
- Four 8-register banks
- Stack depth up to U8-bytes
- Multiply, divide, subtract,
compare
• Most instructions execute
in 1!lS
• 4!lS multiply and divide

40 Vee

P1.0 ~
P1.1

~ PO.O/ADO

P1.2~

~ PO.1/AD1

P1.3~

~ PO.2/AD2

P1.4~

~ PO.3/AD3

P1.5~

P1. 6

~ PO.5/AD5

.r.

P1.7 ~
RST 9

PO.4/AD4

~ PO.6/AD6

~ ~7/AD7

RXD/P3.0~

DIP

~P3.1~

~ EA
30 ALE

~PSEN

~/P3.2~

~ P2.7/A15

INT1/P3.3~

TO/P3.4~

~ P2.6/A14

g P2.5/A13

.!!./P3.5~

~/P3.6~
RD/P3.7jolJ

~ P2.4/A12
~

P2.3/A11

XTAL2~

g P2.2/A10

XTAL1~

P2.1/A9

Vss.gfl

P2.0/A8

TOP VIEW

LOGIC SYMBOL

INDEX
CORNER

The SCN8051AH microcontroller, like its
SCN8048 predecessor, is efficient both
as a controller and as an arithmetic
processor. It has extensive facilities for
binary and BCD arithmetic and excels in
bit-handling capabilities. Efficient use of
program memory results from an instruction set consisting of 44% one-byte,
41 % two-byte, and 15% three-byte instructions. With a 12MHz crystal, 58%
of the instructions execute in 1JIS, 40%
in 2j1S and multiply and divide require only 4j1S.

February 1989

PIN CONFIGURATION

PLCC

28
18
TOP VIEW

Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

1-115

Pin
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
T1/P3.5
39
WR/P3.6 40
RD/P3.7
41
XTAL2
42
XTAL1
43
Vss
44

Function
NC
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
RxD/P3.0
NC
TxD/P3.1
1m'ii/P3.2
iiili'i/P3.3
TO/P3.4

Function
NC
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15

i>sEN
ALE
NC

PO.7/AD7
PO.6/AD6
PO.5/AD5
PO.4/AD4
PO.3/AD3
PO.2/AD2
PO.1/AD1
PO.O/ADO
Vee

853-0096 85292H

Product Specification

Signetics Microprocessor Products

SCN8031 AH /SCN8051 AH

Single-Chip 8-Bit Microcontroller
ORDERING INFORMATION

ROM~R:~]e:)HCJCJCJCJ1CJ :I:X:

ROMless
ROM Pattern No.

ROM

SCN8031 HACN40 SCNS051 HACN40

Temperature and
Package

Frequency

-40 to +S5°C plastic DIP

3.5 to 12MHz

3.5 to 12MHz
o to +70°C plastic DIP
Applies to masked ROM versions SCNS031 HCCN40 SCN8051 HCCN40
only. Number will be assigned by
3.5 to 15MHz
o to +70 0 C plastic DIP
Signetics. Contact Signetics sales SCNS031 HCFN40 SCNS051 HCFN40
office for ROM pattern submission SCN8031 HAFN40 SCNS051 HAFN40
3.5 to 15MHz
-40 to +S5°C plastic DIP
requirements.
SCNS031 HCCA44 SCNS051 HCCA44 o to + 70°C plastic PLCC
3.5 to 12MHz
Pins
40 = 40-pin
SCNS031 HACA44 SCN8051 HACA44 -40 to +S5°C plastic PLCC 3.5 to 12MHz
44 - 44-pin
SCNS031 HCFA44 SCNS051 HCFA44
3.5 to 15MHz
o to + 70°C plastic PLCC
Package
A - Plastic LCC
SCNS031 HAFA44 SCN8051 HAFA44 -40 to +S5°C plastic PLCC 3.5 to 15MHz
I - Ceramic DIP
N - Plastic DIP

31 - Extl12S
51 - 4K/12S

Power

Consumption

PART NUMBER SELECTION

-P~~~~c:~

Speed
C - 3.5 to 12MHz
F - 3.5 to 15MHz
Operating Temperature Range
A - -40°C to +S5°C
C = OOC to +70 0 C

BLOCK DIAGRAM
PO.o-PO.7

P2.D-P2.7

--------1

- - - - - - - - - - ~:-S':l""

peON

SCON TMOD

TCON

THO

TLO

THI

SBUF

TLI

PsEN
ALE

RST

)
Pl.0-Pl.7

February 1989

P3.o-PJ.7

1-116

Product Specification

Signetics Microprocessor Products

SCN8031AH/SCN8051AH

Single-Chip 8-Bit Microcontroller
PIN DESCRIPTION

PIN NO.
MNEMONIC f--~---1 TYPE
NAME AND FUNCTION
DIP
LCC
I
Ground:
OV
reference.
20
22
Vss
I
Power Supply: This is the power supply voltage for normal, idle, and power-down op40
44
Vee
eration.
I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have Is written
PO.O-PO'? 39-32 43-36
to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed
low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pullups when emitting Is.
I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that
1-8
2-9
Pl.0-Pl.?
have Is written to them are pulled high by the internal pull ups and can be used as
inputs. As inputs, port 1 pins that are externally pulled low will source current because
of the internal pUll-Ups. (See DC Electrical Characteristics: lid·
I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pUll-Ups. Port 2 pins that
P2.0-P2.? 21-28 24-31
have 1s written to them are pulled high by the internal pullups and can be used as
inputs. As inputs, port 2 pins that are externally being pulled low will source current
because of the internal pullups. (See DC Electrical Characteristics: lid. Port 2 emits the
high-order address byte during fetches from external program memory and during
accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this
application, it uses strong internal pull-ups when emitting Is. During accesses to
exter- nal data memory that use 8-bit addresses (MOVX @Ri), port 2 emits the
contents of the P2 special function register.
I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pullups. Port 3 pins that
10-17
11,
P3.0-P3.7
have 1s written to them are pulled high by the internal pullups and can be used as
13-19
inputs. As inputs, port 3 pins that are externally being pulled low will source current
because of the pUll-Ups. (See DC Electrical Characteristics: lid. Port 3 is also used for
the special features listed below:
I
RxD (P3.0): Serial input port
10
11
o TxD (P3.1): Serial output port
11
13
I
INTO (P3.2): External interrupt
12
14
I
INT1 (P3.3): External interrupt
13
15
I
TO (P3.4): Timer 0 external input
14
16
I
I!JP3.5): Timer 1 external input
15
17
o WR (P3.6): External data memory write strobe
16
18
o RD (P3. 7): External data memory read strobe
17
19
I
Reset: A high on this pin for two machine cycles while the oscillator is running, resets
RST
9
10
the device. An internal diffused resistor to Vss permits a power-on reset using only an
external capacitor to Vee.
I/O Address Latch Enable: Output pulse for latching the low byte of the address during an
ALE
30
33
access to external memory. In normal operation, ALE is emitted at a constant rate of
1/6 the oscillator frequency, and can be used for external timing or clocking. Note that
one ALE pulse is skipped_during each access to external data memory.
o Program Store Enable: The read strobe to external program memory. When the device
32
29
is executing code from externl!L..!2!2gram memory, PSEN is activated twice each
machine cycle, except that two PSEN activations are skipped during each access to
external data memory. PSEN is not activated during fetches from internal program
memory.
I
External Access Enable: EA must be externally held low to enable the device to fetch
31
35
code from external program memory locations OOOOH and OFFFH. If EA is held high, the
device executes from internal program memory unless the program counter contains an
address greater than OFFFH.
Crystal 1: Input to the inverting oscillator amplifier.
I
XTALI
19
21
o Crystal 2: Output from the inverting oscillator amplifier and input to the internal clock
18
XTAL2
20
generator circuits.

February 1989

1-117

Product Specification

Signetics Microprocessor Products

SCN8031 AH/SCN8051 AH

Single-Chip 8-Bit Microcontroller
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an Inverting amplifier. The pins can be configured for use
as an on-chip oscillator, as shown in the
logic symbol, page 1.

To drive the device from an external
clock source, XTAL2 should be driven
while XTAL1 is left unconnected. There
are no requirements on the duty cycle of
the external clock signal, because the
input to the internal clock circuitry is
through a divide.oy-two flip-flop. However, minimum and maximum high and
low times specified in the data sheet
must be observed.

DESIGN CONSIDERATIONS
At powero{)n, the voltage on Vec and
RST should come up at the same time
for a proper start-up.

ABSOLUTE MAXIMUM RATINGS1, 2, 3
RATING

UNIT

Storage temperature range

-65 to +150

°C

All voltages with respect to ground

-0.5 to +7.0

1.0

PARAMETER

Power dissipation

DC ELECTRICAL CHARACTERISTICS TA - O°C to +70°C, Vec - 4.5 to S.5V, Vss - OV4, 5
Parameter

Symbol

Test Conditions

Limits
Min

Max

Unit

VIL

Input low voltage

-0.5

0.8

VIH

Input high voltage, except RST and XTAL2

Vcc+0.5

VIHl

Input high voltage to RST for reset, XTAL2

2.5

Vcc+0.5

0.45

XTAL1 to Vss
IOL - 1.6mA

VOL

Output low voltage, ports 1, 2, 36

VOLl

Output low voltage, port 0, ALE, PSEN6

IOL - 3.2mA

VOH

Output high voltage, ports 1, 2, 3

IOH - -80IJA

2.4

VOHl

Output high voltage port 0, ALE, PSEN)3

IOH - -400IJA

2.4

IlL

Logical 0 Input current, ports 1, 2, 3

IIHl

Input high curent to RST for reset

ILl

VIN - 0.45V

-500
500

IJA

I nput leakage current, port 0, EA

< Vcc - 1.5V
0.45 < VIN < Vcc

±10

VIN

IJA

IIL2

Logical 0 input current for XTAL2

XTAL1 - Vss, VIN - 0.4SV

-3.2

IJA
mA

Icc

Power supply current:

All outputs disconnected
and EA - Vcc

125

CIO

Pin capacitance

Vcc+O•S

175

= -40"C to +85"C -

Extended temperature range - SCN8051HAC only

VIH

Input high voltage, except RST and XTAL2

VIHl

Input high voltage to RST for reset, XTAL2

Icc

Power supply current:

2.2
XTAL1 to Vss
All outputs disconnected
and EA - Vcc

2.7

NOTES:

1.
2
3.
4.
5.
6.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied.
For operating at elevated temperatures, the device must be derated based on +l50o C maximum junction temperature.
This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it Is suggested that conventional precautions be taken to avoid applying voltages greater than the rated maxima.
Parameters are valid over operating temperature range unless otherwise specified.
All voltage measurements are referenced to ground. For testing, all Input signals swing between O.45V and 2.4V with a transition time of
20ns maximum. All time measurements ·are referenced at Input voltages of O.BV and 2.0V and at output voltages of O.BV and 2.0V as
appropriate.
VOL is degraded when the device rapidly discharges external capaCitance. This AC noise is most pronounced during emission of address
data. When using external memory, locate the latch or buffer as close to the device as possible.
Emitting
Degraded
Datum
Ports
VO Lines
VOL (Peak Max)
Address
P2, PO
Pl, P3
O.BV
Write Data
PO
Pl, P3, ALE
O.BV
CL - 100pF for port 0, ALE and J5Sm outputs; CL - BOpF for all other ports.

February 1989

1-118

Product Specification

Signetics Microprocessor Products

SCN8031AH/SCN8051AH

Single-Chip 8-Bit Microcontroller

AC ELECTRICAL CHARACTERISTICS TA - O°C to +70°C or -40°C to +85°C, VCC - 5V ±20%, Vss - OV1, 2
12MHz CLOCK

PARAMETER

SYMBOL FIGURE

Min

Program Memol'll
Oscillator frequency: Speed Versions
1
1/tCLCL
SCN8051
C
SCN8051
F
1
ALE pulse width
tLHLL
Address valid to ALE low
1
tAVLL
Address hold after ALE low
1
tLLAX
ALE low to valid instruction in
1
tLLlV
tLLPL
tp PH
tpLiV
tpXIX
IpXIZ
tAVIV

1
1
1
1
1
1

1
tpLAZ
1
tpXAV
Data Memory
2, 3
tRLRH
2,3
tWLWH
2, 3
tRLDV

12
15

233

4tCLCL 100

ns
ns

tCLCL -25
3tCLCL-35
125

3tCLcL -125

ns
ns

tCLCL -20
5tCLCL-115
20

ns
ns
ns

0
63
302
20

400
400

6tCLCL-100

tovwx

2, 3
2, 3
2, 3

6tCLcL -100
252

5tcLcL-165
0

97
517
585
200
203

Data vaid to WR high
Data hold after WR

300

2tCLCL -70
8tCLCL-150
9tCLCL-165
3!cLCl. -50
4tCLCL-130

23
433

tCLCL-60
7tCI CL -150

tCLCL-8

RD low to address float
RD or WR high to ALE high

High time
Low time
Rise time
Fall time

20
123

20
20

+50

tCLCL-40

ns
tCLCL+40

ns
ns

20
20

ns
ns
ns
ns

10tCLCL-133

ns
ns
ns
ns

).IS

teFfENture
range unless otherwise specified.
S
- 100pF. load capacitance for all other outputs = 80pF.

P- PSEN
Q - Output data

R - RD signal
t - Time
V-Valid
W - WRsignal
X - No longer a valid logic level
Z - Float
Examples: tAVLL = Time for address valid to ALE low.
tLLPL - Time for ALE low to J5SEN low.

1-119

12tCLCL
10tCLCL-133
2tCLCL-117
0
700

ns
ns
ns
ns
ns
ns
ns
ns

20
20

1.0
700
50
0

Output data setup to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid

r.1

20
20

Serial port clock cycle time

3lel

NOTES:
1. Parameters are valid over operating
2. Lead capacitance for port 0, ALE, and

February 1989

MHz
MHz
ns
ns
ns
ns

RD pulse width
WR pulse width
RD low to valid data in

ALE low to RD or WR low
Address valid to WR low or RD low
Data valid to WR transition

4
4
4
4

3.5
3.5

I UNIT

2, 3
2, 3

tOVXH
tXHOX
tXHDX
tXHDV

Max

tCLCL-8

tLLWL
tAvw

2,3
2, 3
tWHLH
External Clock
5
tCHCX
5
tCLCX
5
tCLCH
5
tCHCL
Shift Register
4
tXLXL

Min

Data hold after RD
Data float after RD
ALE low to valid data in
Address to valid data in

tRLAZ

VARIABLE CLOCK

2tCLCL 40
tCLCL-40
tCLCL -35

58
215

PSEN low to address float
PSEN to address valid

2, 3
2,3
2, 3
2, 3

tOIlll'lH
tWHOX

127
43
48

ALE low to PSEN low
PSEN pulse width
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in

tRHDZ
tLLDV
tAVDV

tRHDX

Max

Product Specification

Signetics Microprocessor Products

SCN8031 AH /SCN8051 AH

Single-Chip 8-Bit Microcontroller

ALE

PSEiii

_ _ _J

PORTO _ _ _J

PORT 2 _ _ _ _J

Figure 1. External Program Memory Read Cycle

ALE

1 0 - - - - - tllDV - - - . - I
--~~---tRlRH-----.-I

PORT 0

AO-A? FROM PCl
~----------tAVDV-----~

PORT 2

--~

P2.0-P2.? OR A8-A15 FROM DPH

Figure 2. External Data Memory Read Cycle

February 1989

1-120

A8-A15 FROM PCH

Product Specification

Signetics Microprocessor Products

SCN8031 AH/SCN8051 AH

Single-Chip 8-Bit Microcontroller

ALE

----~-----tWlWHI------~

1o--l---tOVWH-----ooI

1.----.;""'...---.1.

PORT 0

PORT 2

AO-A? FROM PCl

DATA OUT

A8-A15 FROM PCH

P2.0-P2.? OR A8-A15 FROM DPH

Figure 3. External Data Memory Write Cycle

INSTRUCTION

ALE

tOVXH
OUTPUT DATA

H r-

t XHOX

\\-_---1 '--_--' \-_---1 " - _ - ' \-_---1 '--_--' \-_---1

1...-_-'

WRITE TO SBUF
I INPUT DATA I ____________J'.

"I'

f
CLEAR RI

t
SET RI

Figure 4. Shift Register Mode Timing

February 1989

1-121

Product Specification

Signetics Microprocessor Products

SCN8031 AH/SCN8051 AH

Single-Chip 8-Bit Microcontroller

O.45V

t o - - - - - - t cLCL

-----of

Figure 5. External Clock Drive

Vcc-O.5
O.45V

O.2Vcc+O.9

Timing
Reference

_,-O;";';;,2V,;.;c;.,;c,;.;-.;;.O;.,;.1_ __

AC inputs during testing are driven at Vcc-0.5
for a logic "1" and 0.45V for a logic "0".
Timing measurements are made at VIH min for
a logic "1" and V IL max for a logic "0".

For timing purposes, a port is no longer floating
when a 100mV change from load voltage occurs,
and begins to float when a 100mV change from
the 10adedVOHIVOL level occurs.IOHIlOL~±20mA.

Figure 6. AC Testing Input/Output

Figure 7. Float Waveform

Vee
. -_ _ _ _....lcC
VCC

Vce

Vee

PO
RST

(NC)

CLOCK
SIGNAL

Ei':

XTALl
XTAL2

Vss

Figure 8. Icc Test Condition, Active Mode
All other pins are disconnected

0.45V

~------tCLCL-----~

Figure 9. Clock Signal Waveform for Icc Tests in Active and Idle Modes
tClCH
tCHCL = 5ns

February 1989

Points

1-122

Signetics

SC80C31B/SC80C51B
CMOS Single-Chip 8-Bit
Microcontroller
Product Specification

Microprocessor Division
DESCRIPTION
The Signetics SC80C31 B/SC80C51 B is a
high-performance microcontroller fabricated with Signetics high-density CMOS
technology. The CMOS SC80C31B/
SC80C51 B is functionally compatible
with the NMOS SCN8031/SCN8051 microcontrollers. The Signetics CMOS
technology combines the high speed and
density characteristics of HMOS with
the low power attributes of CMOS.
Signetics' epitaxial substrate minimizes
latch-up sensitivity.
The SC80C31 B/SC80C51 B contains a
4K x 8 ROM, a 128 x 8 RAM, 32 I/O
lines, two 16-bit counter/timers, a fivesource, two priority level nested interrupt
structure, a serial I/O port for either
multi-processor communications, I/O expansion or full duplex UART, and on-chip
oscillator and clock circuits.
In addition, the SC80C31 B/SC80C51 B
has two software selectable modes of
power reduction - idle mode and powerdown mode. The idle mode freezes the
CPU while allowing the RAM, timers, serial port, and interrupt system to continue functioning. The power-down mode
saves the RAM contents but freezes the
oscillator, causing all other chip functions to be inoperative.

LOGIC SYMBOL

FEATURES
• SCN8031/SCN80S1/SC80CS1
compatible
- 4K x 8 ROM
- 128 x 8 RAM
- Two 16-bit counter/timers
- Full duplex serial channel
- Boolean processor
• Memory addressing capability
- 64K ROM and 64K RAM
• Power control modes:
- Idle mode
- Power-down mode
• CMOS and TTL compatible
• Three speed ranges at Vee =
SV ±20%
- 3.S to 12MHz
- 3.S to 16MHz
- O.S to 12MHz
• Three package styles
PIN CONFIGURATION

I:ro Vee
~ PO.O/ADO

P1.0 :::;:
P1.1 ~
P1.2.l

~ PO.1/AD1

P1.3~

~ PO.2/AD2

P1.4~

~ PO.3/AD3

P1.514

~ PO.4/AD4

P1.6~

~ PO.5/AD5

P1.7~

~ PO.6/AD6

RST 9

~:~;:::~ ~
INTO/P3.2

DIP

February 1989

P2.6/A14

~ P2.5/A13

WR/P3.6 ~

~ P2.4/A12

RD/P3.7 ~

~ P2.3/A11

XTAL2 ~

~ P2.2/A10

XTAL1 ~
Vss &Q

t£1. P2.01 A8

~ P2.1/A9

1-123

Lee

18
28
TOP VIEW

Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

Function
NC
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
RxD/P3.0
NC
TxD/P3.1
1l\JTO/P3.2
I1\i'I'i/P3.3
TO/P3.4
T1/P3.5
iNrl/P3.6
lTI)/P3.7
XTAL2
XTAL1
Vss

Function
NC
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15

23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44

PSrN
ALE
NC

PO.7/AD7
PO.6/AD6
PO.5/AD5
PO.4/AD4
PO.3/AD3
PO.2/AD2
PO.1/AD1
PO.O/ADO
Vee
40

'8'"
QFP

to ALE
tePSEN

..:!2!P3.5 ~

TOP VIEW

oo·"tJ
INDEX

~ ~7/AD7
31 EA

~ P2.7/A15

g
TO/P3.4 14

INT1/P3.3

PIN CONFIGURATION (Cont)

18
28
TOP VIEW

Pin
1
2
3
4

5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

Function
NC
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
RxD/P3.0
NC
TxD/P3.1
TmQ/P3.2
iNTi IP3.3
TO/P3,4
T1/P3.5
WR/P3.6
RD/P3.7
XTAL2
XTAL1
Vss

Pin
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44

Function
Vss
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15

J5SrFJ
ALE
NC

l:A

PO.7/AD7
PO.6/AD6
PO.5/AD5
PO,4/AD4
PO.3/AD3
PO.2/AD2
PO.1/AD1
PO.O/ADO
Vee

Product Specification

Signetics Microprocessor Products

CMOS Single-Chip 8-Bit Microcontroller

SC80C31 B/SC80C51 B

ORDERING INFORMATION

ROM~:;;r~BcCCC1C
3 - ROMless
5 _ ROM

ROM
:uIX: ROM Pattern No.
Applies to masked ROM versions
only. Number will be assigned by
Signetics. Contact Signetics sales
office for ROM pattern submission
requirements.

PART NUMBER SELECTION
ROM

less

Temperature and
Package

Frequency

8C80C31 BCCN40 8C80C51 BCCN40

o to +70°C plastic DIP

3.5 to 12MHz

8C80C31 BCGN40 8C80C51 BCGN40

o to +70°C plastic DIP

3.5 to 16MHz

8C80C31 BCBN40 8C80C51 BCBN40

o to + 70°C plastic DIP

0.5 to 12MHz

8C80C31 BCCA44 8C80C51 BCCA44

o to + 70°C plastic LCC

3.5 to 12MHz
3.5 to 16MHz

Pins
40 - 40-pin
44 - 44-pin

8C80C31 BCGA44 8C80C51 BCGA44

o to + 70°C plastic Lee

8C80C31 BCBA44 8C80C51 BCBA44

o to +70 0 C plastic LCC

Package
A - Plastic LCC
N - Plastic DIP
B - Plastic OFP

8C80C31 BACN40 8C80C51 BACN40 -40 to +85°C plastic DIP

3.5 to 12MHz

8C80C31 BAGN40 8C80C51 BAGN40 -40 to +85 0 C plastic DIP

3.5 to 16MHz

Speed
B - 0.5 to 12MHz
C - 3.5 to 12MHz
G - 3.5 to 16MHz
Operating Temperature Range
A - -40°C to +85°C
C - OOC to +70 0 C

0.5 to 12MHz

8C80C31 BACA44 8C80C51 BACA44 -40 to +85°C plastic LCC 3.5 to 12MHz
8C80C31 BAGA44 8C80C51 BAGA44 -40 to +85°C plastic LCC 3.5 to 16MHz
8C80C31 BCCB44 8C80C51 BCCB44

o to +70°C plastic OFP

3.5 to 12MHz

8C80C31 BCGB44 8C80C51 BCGB44

o to + 70°C plastic OFP

3.5 to 16MHz

BLOCK DIAGRAM
PO.D-PIl.7

P2.O-P2.7

--------l

- - - - - - - - - - P--!~""

PCON

SOON TMOD

THO

SBUF

TooN

THI
IP

PSDi ~_.r--_r_::1
ALE

RST

PJ.o-PJ.7

February 1989

1-124

Signetics Microprocessor Products

Product Specification

CMOS Single-Chip 8-Bit Microcontroller

SC80C31 B/SC80C51 B

PIN DESCRIPTION
PIN NO.
MNEMONIC

DIP

Vss

Vee

PO.O-PO.?

LCC!
QFP

TYPE

22
23
44

I
I
I

39-32 43-36

P1.0-P1.7

1-8

2-9

P2.0-P2.7

21-28 24-31

P3.0-P3.7

10-17

11,
13-19

RST

10
11
12
13
14
15
16
17
9

11
13
14
15
16
17
18
19
10

ALE

PSEN

XTAL1

XTAL2

February 1989

NAME AND FUNCTION

Ground: OV reference.
Ground: OV reference. (QFP only)
Power Supply: This is the power supply voltage for normal, idle, and power-down operation.
I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written
to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed
low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pullups when emitting 1s. Port 0 also
outputs the code bytes during program verification in the SC80C31 B/SC80C51 B. External pull-ups are required during program verification.
I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pullups. Port 1 pins that
have 1s written to them are pulled high by the internal pullups and can be used as
inputs. As inputs, port 1 pins that are externally pulled low will source current because
of the internal pullups. (See DC Electrical Characteristics: IILl. Port 1 also receives the
low-order address byte during program memory verification.
I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pullups. Port 2 pins that
have 1s written to them are pulled high by the internal pullups and can be used as
inputs. As inputs, port 2 pins that are externally being pulled low will source current
because of the internal pullups. (See DC Electrical Characteristics: IILl. Port 2 emits the
high-order address byte during fetches from external program memory and during
accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this
application, it uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the
P2 special function register.
I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pullups. Port 3 pins that
have 1s written to them are pulled high by the internal pullups and can be used as
inputs. As inputs, port 3 pins that are externally being pulled low will source current
because of the pUll-Ups. (See DC Electrical Characteristics: IILl. Port 3 also serves the
special features of the SC80C51 family, as listed below:
I
RxD (P3.0): Serial input port
0
TxD (P3.1): Serial output port
I
INTO (P3.2): External interrupt
I
INn (P3.3): External interrupt
I
TO (P3.4): Timer 0 external input
I
I1JP3.5): Timer 1 external input
0
WR (P3.5): External data memory write strobe
0
RD (P3.7): External data memory read strobe
I
Reset: A high on this pin for two machine cycles while the oscillator is running, resets
the device. An internal diffused resistor to Vss permits a power-on reset using only an
external capacitor to Vee.
I/O Address Latch Enable: Output pulse for latching the low byte of the address during an
access to external memory. In normal operation, ALE is emitted at a constant rate of
1/6 the oscillator frequency, and can be used for external timing or clocking. Note that
one ALE pulse is skipped during each access to external data memory.
0
Program Store Enable: The read strobe to external program memory. When the SC80C31 B/SC80C51 B is executing code from external program memory, PSEN is activated
twice each machine cycle, except that two PSEN activations are skipped during each
access to external data memory. PSEN is not activated during fetches from internal
program memory.
I
External Access Enable: EA must be externally held low to enable.!b..e device to fetch
code from external program memory locations OOOOH and OFFFH. If EA is held high, the
device executes from internal program memory unless the program counter contains an
address greater than OFFFH.
I
Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits.

Crystal 2: Output from the inverting oscillator amplifier.

1-125

Product Specification

Signetics Microprocessor Products

SC80C31 B/SC80C51 B

CMOS Single-Chip 8-Bit Microcontroller
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier. The pins can be configured for use
as an on-chip oscillator, as shown in the
logic symbol, page 1.
To drive the device from an external
clock source, XTAL1 should be driven
while XTAL2 is left unconnected. There
are no requirements on the duty cycle of
the external clock signal, because the
input to the internal clock circuitry is
through a divide-by-two flip-flop. However, minimum and maximum high and
low times specified in the data sheet
must be observed.

RESET
A reset is accomplished by holding the
RST pin high for at least two machine
cycles (24 oscillator periods), while the
oscillator is running. To insure a good
power-on reset, the RST pin must be
high long enough to allow the oscillator
time to start up (normally a few milliseconds) plus two machine cycles. At
power-on, the voltage on Vee and RST
must come up at the same time for a
proper start-up.
IDLE MODE
In the idle mode, the CPU puts itself to
sleep while all of the on-chip peripherals
stay active. The instruction to invoke the
idle mode is the last instruction executed
in the normal operating mode before the

idle mode is activated. The CPU contents, the on-chip RAM, and all of the
special function registers remain intact
during this mode. The idle mode can be
terminated either by any enabled interrupt (at which time the process is picked
up at the interrupt service routine and
continued), or by a hardware reset
which starts the processor in the same
manner as a power-on reset.
POWER-DOWN MODE
In the power- 100pF), the noise pulse on the ALE pin may exceed O.BV. In such cases, it may be desirable to

3.
4.

qualify ALE with a Schmitt Trigger. or use an address latch with a Schmitt Trigger STROBE input.
Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9VCC specification when the
address bits are stabilizing.
Pins of ports 1, 2, and 3 source a transition current when they are being externally driven from 1 to O. The transition current reaches its
maximum value when VIN is approximately 2V.

ICC MAX at other frequencies is given by:
Active mode: ICCMAX - 0.94 X FREO + 13.71
Idle mode:
ICCMAX - 0.14 X FREO + 2.31

See Figures 9 through 12 for ICC test conditions.

where FREQ is the external oscillator frequency in MHz. ICCMAX is given in mA. See Figure B.

February 1989

1-127

Product Specification

Signetics Microprocessor Products

SC80C31 B/SC80C51 B

CMOS Single-Chip 8-Bit Microcontroller

AC ELECTRICAL CHARACTERISTICS TA - O°C to +70°C or TA - -40°C to +B5°C, VCC - 5V ±20%, VSS - OV1, 2
SYMBOL FIGURE

12MHz CLOCK

PARAMETER

Program Memory
Oscillator frequency:
1
l/tClCl
SCBOC31B/SCBOC51B
SCBOC31B/SCBOC51B
SCBOC31B/SCBOC51B

Min

Max

Speed Versions
B
C

VARIABLE CLOCK
Min

Max

0.5
3.5
3.5

12
12
16

UNIT

MHz
MHz
MHz

tlHll

ALE pulse width

127

2tClCl -40

tAVlL

Address valid to ALE low

t0101-55

tllAX

Address hold after ALE low

tClCl -35

tlLIV

ALE low to valid instruction in

tllPl

ALE low to PSEN low

tClCl -40

tp PH

PSEN pulse width

205

3tClCl -45

tpLiV

PSEN low to valid instruction in

tpXIX

Input instruction hold after PSEN

tpXIZ

Input instruction float after PSEN

tAVIV

Address to valid instruction in

1
tplAZ
Data Memory
2, 3
tRlRH

234

145
0

PSEN low to address float

ns
4tClCL -100

ns
ns
ns

3tclCl -105
0

ns
ns

tClCl -25

312

5tClCl -105
10

RD pulse width

400

6tClCl -100

tWlWH

2, 3

WR pulse width

400

6tClCl -100

tRIDV

2, 3

RD low to valid data in

tRHDX

2, 3

Data hold after RD

252
0

ns
ns
ns

5tcLCL -165
0

ns
ns

tRHDZ

2, 3

Data float after RD

2tClCL -70

tllDV

2, 3

ALE low to valid data in

517

BtClCl -150

9tCLCl -165

3tClCl +50

tAVDV

2, 3

Address to valid data in

tllWl

2,3

ALE low to RD or WR low

200

tAVWL

2, 3

Address valid to WR low or RD low

203

4tOLCI -130

tQVWX

2, 3

Data valid to WR transition

tCLCl-60

tWHOX

2, 3

Data hold after WR

tCLCL-50

IRlAZ

2,3

RD low 10 address float

2, 3
tWHlH
External Clock
5
tCHCX
5
tClCX
5
tClCH
5
tCHCl
Shift Re ister
4
IXlXl
4
tOVXH
4
tXHOX
4
tXHDX
4
tXHDV
NOTES:

5B5
300

3tClCl -50

RD or WR high to ALE high

High time
Low time
Rise time
Fall time

20
20

123

tClCL -40

tClCl+40

20
20

ns
ns
ns
ns

1OtClCl -133

ns
ns
ns
ns

20
20
20
20

Serial port clock cycle time
Output data setup to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid

ns
0

1.0
700
50
0

12tClCl
10tClCl-133
2tClCl -117
0
700

f1S

1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port O. ALE, and PSEN ~ 100pF. load capacitance for all other outputs ~ 80pF.

EXPLANATION OF THE AC SYMBOLS
Each timing symbol has five characters. The first character is
always 'I' (- time). The other characters, depending on their
positions, indicate the name of a signal or the logical stalus of
that Signal. The designations are:
A - Address
C - Clock
D - I nput data
H - Logic level high
I - I nstruction (program memory contents)
L - Logic level low, or ALE

February 1989

P- PSEN
Q - OUIPuI dala
R - RD signal
t - Time
V - Valid
W - WR signal
X - No longer a valid logic level
Z - Float
Examples: tAVll - Time for address valid to ALE low.
IllPl - Time for ALE low to PSEN low.

1-128

Product Specification

Signetics Microprocessor Products

SC80C31 B/SC80C51 B

CMOS Single-Chip 8-Bit Microcontroller

ALE

PSEN _ _ _J

PORTO _ _ _J

1o-----tAVIV----oI
PORT 2

AB-A15

A8-A15

Figure 1. External Program Memory Read Cycle

ALE

10------- tllDV - - - - o j

--..----I

RlRH

----.I

PORTO

PORT 2

AO-A7 FROM PCl

---

~-----IAVDV--------~

P2.0-P2.7 OR A8-A15 FROM DPH

Figure 2. External Data Memory Read Cycle

February 1989

1-129

A8-A15 FROM PCH

Product Specification

Signetics Microprocessor Products

SC80C31 B/SC80C51 B

CMOS Single-Chip 8-Bit Microcontroller

ALE

- - - - - - - WlWHI-----I

PORTO

DATA OUT

PORT 2

P2.0-P2.? OR A8-A15 FROM DPH

AO-A? FROM PCl

A8-A15 FROM PCH

Figure 3. External Data Memory Write Cycle

INSTRUCTION

ALE

tOVXH

OUTPUT DATA

t XHOX

\,-_~ , " - _ - J ' - _ - - ' ' - - _....... ' - _ - - ' ' - - _ - J ' - _ - - ' '--_..J

WRITE TO SBUF
I INPUT DATAl _ _ _ _ _--'

CLEAR RI

SET RI

Figure 4. Shift Register Mode Timing

February 1989

1-130

Product Specification

Signetics Microprocessor Products

SC80C31 B/SC80C51 B

CMOS Single-Chip 8-Bit Microcontroller

O.45V

t CHCL
~---------tCLCL--------~

Figure 5. External Clock Drive

Vcc-O.5
0.45V

O.2Vcc+O.9

Timing
Reference
Points

_:..;O::;.;;.2V;,;c;;;;c;,..-.;:.O.;.:.1_ __

AC inputs during testing are driven at Vcc-O.S
for a logic "1" and O.4SV for a logic "0".
Timing measurements are made at VIH min for
a logic "1" and V IL max for a logic "0".

For timing purposes, a port is no longer floating
when a 100mV change from load voltage occurs,
and begins to float when a 100mV change from
the loaded VOHIVOL level occurs.IOH/1oL ~± 20mA.

Figure 6. AC Testing Input/Output

Figure 7. Float Waveform

MAX
ACTIVE MODE
25

0
~

5 ~---+~~+----4----4MAX
IDLE MODE
TVP(1)

~~:±====:t::==1:==~IDLEMODE
4MHz BMHz 12MHz 16MHz

FREQ AT XTAL1

Figure 8. Icc vs. FREQ
Valid only within frequency specifications of the device under test

February 1989

1-131

Signetics Microprocessor Products

Product Specification

CMOS Single-Chip 8-Bit Microcontroller

SC80C31 B/SC80C51 B

Vee
. -_ _ _ _-il,ee

Vee

l
Vee

RST
RST

CLOCK
SIGNAL

(NC)

XTAL2
XTAL1

CLOCK (NC)
SIGNAL

Vss

XTAL2
XTAL1
Vss

Figure 10. Icc Test Condition, Idle Mode
All other pins are disconnected

Figure 9. Icc Test Condition, Active Mode
All other pins are disconnected

0.45V

1-----tcLcL------.I

Figure 11. Clock Signal Waveform for Icc Tests in Active and Idle Modes
tCLCH
tCHCL
5ns

Vee

,-____-ilee
Vee

l
Vee

RST

(NC)

XTAL2
XTAL1
Vss

Figure 12. Icc Test Conditions, Power Down Mode
All other pins are disconnected. VCC = 2V to 5.5V

February 1989

1-132

Signefics

SC87C51
CMOS Single-Chip 8-Bit EPROM
Microcontroller
Product Specification

Microprocessor Division

DESCRIPTION
The Signetics SC8lCSl is a high-performa nee microcontroller fabricated with
Signetics high- 100pF), the noise pulse on the ALE pin may exceed O.SV. In such cases, it may be desirable to

3,
4.
5.

qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input.
Capacitive loading on ports
and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0,9VCC specification when the

address bits are stabilizing.
Pins of ports 1, 2, and 3 source a transition current when they are being externally driven from 1 to 0.. The transition current reaches its
maximum value when VIN is approximately 2V.
ICCMAX at other frequencies is given by:

Active mode: ICCMAX - 0,94 X FREO + 13.71
Idle mode:
ICC MAX - 0,14 X FREQ + 2,31
6.
7.

where FREQ is the external oscillator frequency in MHz. ICCMAX is given in mA. See Figure 8.
See Figures 9 through 12 for ICC test conditions.
These values apply only to TA -= OOC to +70 o C. For TA ""' -40°C to +85°C, see table on page 4.

February 1989

1-137

Product Specification

Signetics Microprocessor Products

SC87C51

CMOS Single-Chip 8-Bit EPROM Microcontroller
AC ELECTRICAL CHARACTERISTICS TA - O°C to +70°C or -40°C to +85°C, VCC - 5V ±10%, Vss - OV1, 2
12MHz CLOCK

PARAMETER

SYMBOL FIGURE

Min

Max

Program Memory
Oscillator frequency: Speed Versions
1
1/tClCl
SC87C51
B
SC87C51
C
SC87C51
G

VARIABLE CLOCK
Min

Max

0,5
3,5
3,5

12
12
16

UNIT

MHz
MHz
MHz

tlHll

ALE pulse width

127

2tClCl -40

tAVL

Address valid to ALE low

tClCl-55

tllAX

Address hold after ALE low

tClCl-35

tLLJV

ALE low to valid instruction in

tllPl

ALE low to PSEN low

tpLPH

PSEN pulse width

tpLiV

PSEN low to valid instruction in

tPXIX

Input instruction hold after PSEN

tpXIZ

Input instruction float after PSEN

tClCl-25

Address to valid instruction in

312

5tClCL -105
10

1
tAYIV
1
tplAZ
Data Memory_
2, 3
tRlRH

234
43

tClCl -40

205

3tClCl -45
145

ns
3tClCl-105

RD pulse width

400

6tCccL -100

tWlWH

2, 3

WR pulse width

400

6tClCl-100

tRlDV

2, 3

RD low to valid data in

tRHDX

2, 3

Data hold after RD

252

ns
ns

ns
ns
ns

5tco[-165

ns
ns

PSEN low to address float

ns
4tclcl -100

tRH[)7

2, 3

Data float after RD

2tClCl -70

'llDV
tAVD\i

2, 3

ALE low to valid data in

517

8tClCl -150

2, 3

Address to valid data in

585

9tcLCL -165

tllWl

2, 3

ALE low to RD or WR low

200

3tClCl+50

tAVWL

2, 3

Address valid to WR low or RD low

203

4tol 01 -130

tOVWX

2, 3

Data valid to WR transition

tClCl -60

tWHOX

2, 3

Data hold after WR

tRlAZ

2, 3

RD low to address float

2, 3
tWHLH
External Clock
5
tCHCX
5
tClCX
5
tClCH
5
tCHCl
Shift Re ister
4
tXlXl
4
tOVXH
4
tXHOX
4
tXHDX
4
tXHDV

300

3tClCl-50

RD or WR high to ALE high

High time
Low time
Rise time
Fall time

20
20

Serial port clock cycle time
Output data setup to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid

1.0
700
50
0

t0101-50
0
123

tCLCL-40

tCLCL+40

20
20

ns
ns
ns
ns

1OtClCl -133

J.lS
ns
ns
ns
ns

20
20
20
20
12tClCl
1OtClCl -133
2tClCl -117
0
700

NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN - 100pF, load capacitance for all other outputs - 80pF.

February 1989

P- PSEN
Q - Output data
R - RD signal
t - Time
V - Valid
W - WR signal
X - No longer a valid logic level
Z - Float
Examples: tAVll - Time for address valid to ALE low.
tllPl - Time for ALE low to PSEN low.

1-138

Product Specification

Signetics Microprocessor Products

CMOS Single-Chip 8-Bit EPROM Microcontroller

SC87C51

ALE

PORTO

PORT 2

----'

-----'
Figure 1. External Program Memory Read Cycle

ALE

Je----- tLLDV - - - - I
t LLWL

--1---- tRLRH ------I

tRLDV
tRHDX
PORTO

PORT 2

P2.0-P2.7 OR A8-A15 FROM DPH

Figure 2. External Data Memory Read Cycle

February 1989

1-139

A8-A15 FROM PCH

Product Specification

Signetics Microprocessor Products

SC87C51

CMOS Single-Chip 8-Bit EPROM Microcontroller

ALE

I--

t WLWH

t LLWL

r-.
t AVLL

PORT 0

I-----<

I-

i-tLLAX-o

np,
~ • Hl()MAg;~~
t

tWHLH

......

tOVWX

t WHOX

DATA OUT

AO-A? FROM PCL

INSTR IN

AVWL

PORT 2

A8-A15 FROM PCH

P2.0-P2.? OR A8-A15 FROM DPH

Figure 3. External Data Memory Write Cycle

INSTRUCTION

ALE

tOVXH
OUTPUT DATA

t XHOX

' ' -_ _-' '-_ _-' '-_ _-' '-_ _-' '-_ _-' '-_ _oJ '-_ _oJ

1..._--'

WRITE TO SBUF
,'NPUT DATA, _ _ _ _ _....1

CLEAR RI

SET RI

Figure 4. Shift Register Mode Timing

February 1989

1-140

Signetics Microprocessor Products

Product Specification

CMOS Single-Chip 8-Bit EPROM Microcontroller

SC87C51

0.45V

~----------tCLCL--------~

Figure 5. External Clock Drive

VCC-O.5=>C O.2Vcc+O.9
0.45V

Timing
Reference
Points

_-.::;O.;,:;2..:.V,:;.cc:;.-..,;O:,;..;.1_ __

AC inputs during testing are driven at Vcc-0.5
for a logic "1" and 0.45V for a logic "0".
Timing measurements are made at VIH min for
a logic" 1" and V IL max for a logic "0".

For timing purposes, a port is no longer floating
when a 100mV change from load voltage occurs,
and begins to float when a 100mV change from
the loaded VOHIVOL level occurs.IOH /1 0L2± 20mA.

Figure 6. AC Testing Input/Output

EPROM CHARACTERISTICS
The SC87C51 is programmed by using a
modified Quick-Pulse Programming" algorithm. It differs from older methods in
the value used for Vpp (programming
supply voltage) and in the width and
number of the ALE/PROG pulses.
The SC87C51 contains two signature
bytes that can be read and used by an
EPROM programming system to identify
the device. The signature bytes identify
the device as an SC87C51 manufactured
by Signetics Corporation.
Table 2 shows the logic levels for
reading the signature byte, and for programming the program memory, the encryption table, and the lock bits. The
circuit configuration and waveforms for
quick-pulse programming are shown in
Figures 13 and 14. Figure 15 shows the
circuit configuration for normal program
memory verification.
QUICK-PULSE PROGRAMMING
The setup for microcontroller quick-pulse
programming is shown in Figure 13. Note
that the SC87C51 is running with a 4 to
6MHz oscillator. The reason the oscillator needs to be running is that the device is executing internal address and
program data transfers.
The address of the EPROM location to
be programmed is applied to ports 1 and
2, as shown in Figure 13. The code byte
to be programmed into that location is

February 1989

Figure 7. Float Waveform

applied to port O. RST, PSEN and pins
of ports 2 and 3 specified in Table 2 are
held at the "Program Code Data" levels
indicated in Table 2. The ALE/PROG is
pulsed low 25 times as shown in Figure
14.

shown in Figure 15. The other pins are
held at the "Verify Code Data" levels indicated in Table 2. The contents of the
address location will be emitted on port
O. External pull-ups are required on port
a for this operation.

To program the encryption table, repeat
the 25 pulse programming sequence for
addresses a through 1 FH, using the
"Pgm Encryption Table" levels. Do not
forget that after the encryption table is
programmed, verification cycles will produce only encrypted data.

If the encryption table has been programmed, the data presented at port a
will be the exclusive NOR of the gram
byte with one of the encryption bytes.
The user will have to know the encryption table contents in order to correctly
decode the verification data. The encryption table itself cannot be read out.

To program the lock bits, repeat the 25
pulse programming sequence using the
"Pgm Lock Bit" levels. After one lock bit
is programmed, further programming of
the code memory and encryption table is
disabled. However, the other lock bit
can still be programmed.
Note that the EA/vpp pin must not be allowed to go above the maximum specified Vpp level for any amount of time.
Even a narrow glitch above that voltage
can cause permanent damage to the device. The Vpp source should be well regulated and free of glitches and overshoot.
Program Verification
If lock bit 2 has not been programmed,
the on-chip program memory can be
read out for program verification. The
address of the program memory locations
to be read is applied to ports 1 and 2 as

1-141

Reading the Signature Bytes
The signature bytes are read by the
same procedure as a normal verification
of locations 030H and 031 H, except that
P3.6 and P3.7 need to be pulled to a
logic low. The values are:
(030H) - 15H indicates manufactured by
Signetics
(031 H) - 92H indicates SC87C51
ProgramNerify Algorithms
Any algorithm in agreement with the
conditions listed in Table 2, and which
satisfies the timing specifications, is suitable.

'"Trademark phrase of Intel Corp.

Product Specification

Signetics Microprocessor Products

SC87C51

CMOS Single-Chip 8-Bit EPROM Microcontroller
Erasure Characteristics
Erasure of the EPROM begins to occur
when the chip is exposed to light with
wavelengths shorter than approximately
4,000 angstroms. Since sunlight and fluorescent lighting have wavelengths in
this range, exposure to these light
sources over an extended time (about 1
week in sunlight, or 3 years in room level
fluorescent lighting) could cause inadvertent erasure. For this and secondary effects, it is recommended that an
opaque label be placed over the window. For elevated temperature or solvent environments, use Kapton tape
Fluorglas part number 2345-5 or equivalent.

The recommended erasure procedure is
exposure to ultraviolet light (at 2537
angstroms) to an integrated dose of at
least
15W-sec/cm2.
Exposing
the
EPROM to an ultraviolet lamp of
12,00011W/cm2 rating for 20 to 39 minutes, at a. distance of about 1 inch,
should be sufficient.
Erasure leaves the array in an all IS
state.

Table 2. EPROM Programming Modes
RST

PSEN

ALE/PROG

EA/vpp

P2.7

P2.6

P3.7

P3.6

Read signature

MODE

Program code data

Vpp

Verify code data

Pgm encryption table

Vpp

Pgm lock bit 1

O·

Vpp

Pgm lock bit 2

Vpp

NOTES:
1. "0" - valid low for that pin, "1" - valid high for that pin.
2. Vpp = 12.75V ±O.25V.
3. Vee - 5V ±1 0% during programming and verification.
'ALE/PROG receives 25 programming pulses while Vpp is held at 12.75V. Each programming pulse is low for IOOILS (±IOILS) and
high for a minimum of lOlLS.

30
MAX
ACTIVE MODE

..:

TYP(1)
ACTIVE MODE

2
10

f--++-I--+--I MAX

IDLE MODE

TYP(1)

~~==b::::J:::::1====~IDLEMODE
4MHz 8MHz 12MHz 16MHz
FREQ AT XTAL1

Figure 8. Icc vs. FREQ
Valid only within frequency specifications of the device under test

February 1989

1-142

Product Specification

Signetics Microprocessor Products

SC87C51

CMOS Single-Chip 8-Bit EPROM Microcontroller

Vee

r-____-;Iee
Vee

Vee

~
Vee

RST
RST

(NC)
CLOCK
SIGNAL

XTAL2
XTAl1

CLOCK
SIGNAL

Vss

(NC)

XTAl2
XTAl1
Vss

Figure 10. Icc Test Condition, Idle Mode
All other pins are disconnected

Figure 9. Icc Test Condition, Active Mode
All other pins are disconnected

O.45V

t CHCl

t ClCH

tClCX

~-----tClCl--------~

Figure 11. Clock Signal Waveform for Icc Tests in Active and Idle Modes
tCLCH
tCHCL
5ns

Vee

r-____-;Iee
Vee

!
Vee

RST

(NC)

XTAl2
XTAl1
Vss

Figure 12. Icc Test Conditions, Power Down Mode
All other pins are disconnected. VCC = 2V to 5.5V

February 1989

1-143

Product Specification

Signetics Microprocessor Products

SC87C51

CMOS Single-Chip 8-Bit EPROM Microcontroller

+5V

AO-A? --_011 P1

----01 RST
----tlP3.6
----tlP3.?

1\.----

PGM DATA

EA/vpp 1 0 - - - - +12.75V
ALE/P'ROG

SC87C51

...--_--1 XTAL2

10---- ¥~ ~~~Su~~LSES

Ps"EN 10---P2.71o---P2.61O---P2.0 IJL--- A8-A11
-P2.3 I \ r - - - -

L--....-J.-I XTAL 1
Vss

Figure 13. Programming Configuration

1110.---------25 PULSES.----------o!

ALE/PROG:

~-----------,

i-----

1"-.

10).lSMIN

--I1---100).lS±10~

----.:....,
OL-I________~n
ALE/PROG:

Figure 14. PROG Waveform

February 1989

1-144

___

Product Specification

Signetics Microprocessor Products

SC87C51

CMOS Single-Chip 8-Bit EPROM Microcontroller

+5V

10K

Vee

_ _ _-ojRST
----tlP3.6
- - - - t l P3 .7

PO 1-_"':"''; PGM DATA

AO-A7 _ _-,/1 P1

EA/Vpp i t - - - ALE/PROG i t - - - SC87C51

,---.....---1 XTAL2

PSENIo---P2.71o---- 0

(ENABLE)

P2.6it---P2.0 11'---- AS-A11
-P2.3 I \ r - - - -

-I--I XTAL 1

L - _......

Vss

Figure 15. Program Verification

EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS TA - 21°C to +27°C, VCC - 5V±1 0%, VSS - OV (see Figure 16)
PARAMETER

SYMBOL
Vpp

Programming supply voltage

Ipp

Programming supply current

1/tCLCL

Oscillator frequency

tAVGL

Address setup to PROG low

MIN

MAX

12.5

13.0

MHz

UNIT

48tCLCL

tGHAX

Address hold after PROG

48tCLCL

tDVGL

Data setup to PROG low

48tCLCL

tGHDX

Data hold after PROG

48tCLCL

tEHSH

P2.7 (ENABLE) high to Vpp

48tCLCL

tSHGL

Vpp setup to PROG low

).IS

tGHSL

Vpp hold after PROG

).IS

tGLGH

PROG width

tAVQV

Address to data valid

).IS

48tCLCL

tELQV

ENABLE low to data valid

tEHQZ

Data float after ENABLE

tGHGL

PROG high to PROG low

February 1989

110

48tCLCL

1-145

48tCLCL
).IS

Signetics Microprocessor Products

Product Specification

CMOS Single-Chip 8-Bit EPROM Microcontroller

PROGRAMMING"

Pl.0-Pl.7
P2.0-P2.3

VERIFICATIOW

ADDRESS

I-- I AVOV

I-

I AVGL

I-- , 25 PULSES "

ALE/PROG

IGLGH-t
I SHGL

EAlVpp

DATA OUT

DATA IN
I DVGL

~
- -

I-

Q:-:'

-4

10-

I-

I GHDX
I GHAX

I GHGL

f----t
V

\.
/

ADDRESS

-4

PORTO

SC87C51

I GHSL

LOGIC 1

LOGIC 0

-- - - - - - - - - - - -

- - - - - - - - -

I EHSH

P2.7

EANBLE

IELOr

-./

"FOR PROGRAMMING VERIFICATION SEE FIGURE 13.
FOR VERIFICATION CONDITIONS SEE FIGURE 15.

Figure 16. EPROM Programming and Verification

February 1989

1-146

I-

I EHOZ

Signetics

Section 2
8051 Family Derivatives

Microprocessor Products

INDEX
8032/8052 Overview. . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-1
Differences from the 8051 ..................................
Program Memory ........................................
Special Function Registers '" . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Timer/Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Serial Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Special Function Registers Table ............................
Timer/Counter 2 Set-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Port Structures ..........................................
SCN8032AH/SCN8052AH Data Sheet ........................
8XC451 Overview ........................................
Differences from the 8051 .................................
Special Function Registers . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . ..
I/O Port Structure .......................................
Processor Bus Interface ..................................
Standard Quasi-BidirectionalliO Port .......................
Parallel Printer Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Special Function Registers Table ...........................

2-1
2-1
2-1
2-1
2-2
2-5
2-8
2-8
2-9
2-11
2-1 8
2-18
2-18
2-18
2-19
2-19
2-19
2-20

SC80C451/SC83C451 Data Sheet ............................ 2-21
SC87C451 Data Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-35
8XC552 Overview ........................................ 2-53
Differences from the 8051 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-53
Program Memory ....................................... 2-53
Data Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-53
Special Function Registers ........ . . . . . . . . . . . . . . . . . . . . . . .. 2-53
Timer T2 .............................................. 2-53
Special Function Registers Table ........................... 2-55
Timer T3. the Watchdog Timer ... . . . . . . . . . . . . . . . . . . . . . . . . .. 2-59
Serial I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .............. 2-61
Reset Circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-95
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-96
1/0 Port Structure ....................................... 2-98
Port 1 Operation ........................................ 2-99
Port 5 Operation ....................................... 2-100
Pulse Width Modulated Outputs .. " ....................... 2-100
Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-101
Power Reduction Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-105
Memory Organization ................................... 2-106
S83C552/S80C552 Data Sheet ............................. 2-112
8XC652 Overview .......................................
Differences from the 80C51 ..............................
Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Special Function Registers Table ...... " ..................
12C Serial Communications - SI01 .........................
Idle and Power-Down Operation ..........................
Interrupt System .......................................

2-123
2-123
2-123
2-124
2-124
2-124
2-125

Microcontroller Users' Guide

INDEX (Continued)

S83C6521S80C652 Data Sheet ................................... 2-127
8XC751 OVerview ............................................. 2-137
Differences from the 80C51 .................................... 2-137
Memory organization ......................................... 2-137
Special Function Registers ..................................... 2-137
Data Pointer (DPTR) .......................................... 2-138
I/O Port Latches (PO, P1, P3) ................................... 2-138
I/O Port Structure ............................................ 2-138
Special Function Registers Table ................................ 2-139
Timer/Counter ........................... ' ................... 2-139
12C Serial Interface ........................................... 2-140
S83C751 Data Sheet ........................................... 2-144
587C751 Data Sheet ........................................... 2-151
8XC752 Overview ............................................. 2-162
Idle Mode .................................................. 2-162
Power-Down Mode .......................................... 2-162
Memory Organization ......................................... 2-162
I/O Ports ................................................... 2-162
Special Function Registers Table ................................ 2-163
PWM Outputs ............................................... 2-163
AID Converter ............................................... 2-164
Countermmer ............................................... 2-165
12C Serial 110 .................................... , ......... , . 2-165
Interrupts ................................................... 2-165
Power-Down and Idle Modes ................................... 2-166
Instruction Set ............................................... 2-166
Special Function Registers ..................................... 2-167
Data Pointer ................................................ 2-167
Ports 0, 1, 2 ................................................ 2-167
87C752 Data Sheet ............................................ 2-168

Section 2
8051 FAMILY DERIVATIVES
The data memory organization is identical to the 8051
except that the 8052 has an additional 128 bytes of RAM
overlapped with the special function register space. This
additional RAM is addressed using indirect addressing
only and is available as stack space. The 8052 data
memory space is shown in Figure 2.

8032/8052 OVERVIEW
The 8052/8032 are identical to the 805118031 respectively except for added features. The 8052/8032 has:
8K ROM (8052 only)
256 bytes RAM
Counter/timer 2

SPECIAL FUNCTION REGISTERS
The special function register space is the same as the
8051 except that the 8052 contains the additional special
function registers TICON, RCAP2L, RCAP2H, TL2 and
1H2. Since the standard 8051 on-chip functions are
identical in the 8052, the SFR locations, bit locations
and operation are likewise identical. The only exceptions
are in the interrupt mode and interrupt priority SFR's
(see Table 1).

As a result, there are some additions to the interrupt
structure, I/O pin alternate functions, and baud rate
generation for the serial channel.
Since the similarity is so close, only the additional features of the 8052/8032 are described. Where necessary,
some repetition of 8051 information will be made for the
sake of clarity. The 8052 is pin for pin and fully code
compatible with the 8051.

TIMER/COUNTERS

DIFFERENCES FROM THE 8051

In addition to timer/counters 0 and 1 of the 8051 the
8052 contains timer/counter 2. Like timers 0 and l,'timer 2 can operate as either an event timer or as an event
counter. This is selected by bit C/TI in the special function register TICON (see Figure 3). It has three operating modes:capture, auto-load, and baud rate generator,
which are selected by bits in the TICON as shown in
Table 2.

PROGRAM MEMORY
The data and program memory are organized virtually
identically to the 8051. The 8052 ~sesses 8K bytes of
on-chip program memory. When EA is high, the 8052
fetches instructions from the internal ROM unless the
address exceeds 1FFFH. Locations 2000H to FFFFH are
fetched from external program memory. When EA is
held low all instruction fetches are from external memory. The program memory space is shown in Figure 1.

In the Capture Mode there are two options which are selected by bit EXEN2 in TICON. If EXEN2 = 0, then
Timer 2 is a 16-bit timer or counter which upon over-

FFFF , . . . . - - - - - - - - - -

FFFF , . . - - - - - - - - - - .

11K
BYTES
EXTERNAL
14K

--OR-_....

EXTERNAL

~-------~
AND

:::1~_______~__

8YTE8_NA
__L______

GOOD

Figure 1. 8052 Program Memory

February 1989

BYTES

2-1

_ _ _ _ _ _ _.....J

User's Guide

Signetics Microprocessor Products

8032/8052

Section 2 - 8051 Derivatives

FFFF
INTERNAL

r-----------,

INDIRECT
ADDRESSING ONLY

8OHTOFFH

FF/
FFr-~--------~

SFRa

14K
BYTES
EXTERNAL

DIRECT
ADDRESSING
ONLY

--AND~

7F~------------------~
DIRECT ..
INDIRECT
ADDRESSING

oo~------------~

oooo~---------------~

Figure 2. 8052 Data Memory
flowing sets bit TF2, the Timer 2 overflow bit, which can
be used to generate an interrupt. If EXEN2 = 1, then
Timer 2 still does the above, but with the added feature
that a 1-to-O transition at external input TIEX causes
the current value iu the Timer 2 registers, 1L2 and TH2
to be captured into registers RCAP2L and RCAP2H, respectively. (RCAP2L and RCAP2H are new Special
Function Registers in the 8052.) In addition, the transition at TIEX causes bit EXF2 in TICON to be set, and
EXF2 like TF2, can generate an interrupt. The Capture
Mode is illustrated in Figure 4.
In the auto-reload mode there are again two options,
which are selected by bit EXEN2 in TICON. If EXEN2
= 0, then when Timer 2 rolls over it not only sets TF2
but also causes the Timer 2 registers to be reloaded with
the 16-bit value in registers RCAP2L and RCAP2H,
which are preset by software. If EXEN2 = 1, then Timer
2 still does the above, but with the added feature that a
1-to-0 transition at external input TIEX will also trigger
the 16-bit reload and set EXF2. The auto-reload mode
is illustrated in Figure 5.
The baud rate generation mode is selected by RCLK = 1
and/or TCLK = 1. It will be described in conjunction
with the serial port.

Figure 3). Note that the baud rate for transmit and receive can be simultaneously different. Setting RCLK
and/or TCLK puts Timer 2 into its baud rate generator
mode, as shown in Figure 6.
The baud rate generator mode is similar to the autoreload mode, in that a rollover in TH2 causes the Timer
2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software.
Now, the baud rates in Modes 1 and 3 are determined by
Timer 2's overflow rate as follows:
Timer 2 Overflow Rate
Modes 1, 3 Baud Rate

= ---------

16
The Timer can be configured for either "timer" or
"counter" operation. In the most typical applications, it
is configured for "timer" operation (C/TI = 0). "Timer"
operation is a little different for Timer 2 when it's being
used as a baud rate generator. Normally, as a timer it
would increment every machine cycle (thus at 1112 the
oscillator frequency). As a baud rate generator, however,
it increments every state time (thus at 112 the oscillator
frequency). In that case the baud rate is given by the
formula

SERIAL PORT
The serial port of the 8052/8032 is identical to that of
the 8051 except that counter/timer 2 can be used to
generate baud rates.

Modes 1,3
Baud Rate

In the 8052, Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in TICON (see

where (RCAP2H, RCAP2L) is the content of RCAP2H
and RCAP2L taken as a 16-bit unsigned integer.

February 1989

Oscillator Frequency
= -------------

32x [65536 - (RCAP2H, RCA2L)]

2-2

User's Guide

Signetics Microprocessor Products

8032/8052

Section 2 - 8051 Derivatives
(LSB)

(MSB)
TF2

EXF2

RCLK

TCLK

EXEN2

TR2

c/f2

cMu:2

Symbol

Poalllon

TF2

T2CON.7

TImer 2 overflow flag set by a TImer 2 overflow and must be cleared by software.
TF2 will not be set when efther RCLK = 1 or TCLK = 1.

EXF2

T2CON.6

TImer 2 external flag set when either a capture or reload is caused by a negative
transition on T2EX and EXEN2 = 1. When TImer 2 interrupt is enabled. EXF2 = 1
will cause the CPU to vector to the TImer 2 Interrupt routine. EXF2 must be
cleared by software.

RCLK

T2CON.5

Receive clock flag. When set, causes the serial port to use Timer 2 overflow
pulses for Its receive clock in Modes 1 and 3. RCLK = 0 causes Timer 1 overflow
to be used for the receive clock.

TCLK

T2CON.4

Transm" clock flag. When set, causes the serial port to use Timer 2 overflow
pulses for its transmit clock in modes 1 and 3. TCLK = 0 causes Timer 1
overflows to be used for the transmit clock.

EXEN2

T2CON.3

Timer 2 external enable flag. When set, allows a capture or reload to occur as a
result of a negative transition on T2EX if TImer 2 Is not being used to clock the
serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.

Name and SlgnllfC8nce

TR2

T2CON.2

Startlstop control for TImer 2. A logic 1 starts the timer.

c/f2

T2CON.l

Timer or counter select. (Timer 2)
o = Internal timer (OSC/12)
1 = External event counter (faUing edge triggered).

CP/m

T2CON.O

Capture/Reload flag. When set, captures will occur on negative transitions at
T2EX if EXEN2 = 1. When cleared, auto-reloads will occur either with Timer 2
overflows or negative transitions at T2EX when EXEN2 = 1. When either RCLK
= 1 or TCLK = I, this bit is Ignored and the timer is forced to auto-reload on
Timer 2 overflow.

Figure 3. Timer/Counter 2 (T2CON) Control Register

nMER2
INTERRUPT

EXEN2

Figure 4. Timer 2 in Capture Mode

February 1989

2-3

User's Guide

Signetics Microprocessor Products

8032/8052

Section 2 - 8051 Derivatives

TIMER 2
INTERRUPT

EXEN2

Figure 5. Timer 2 in Auto-Reload Mode

nMER1
OVEIIFUlW

RX CLOCK

TX CLOCK

.x....
L NOTa AYAUlUUTY OF ADDI110NAL IX11!RNAL INTEARUPT
Figure 6. Timer 2 in Baud Rate Generator MOde

February 1989

2-4

User's Guide

Signetics Microprocessor Products

8032/8052

Section 2 - 8051 Derivatives
Table 1. Special Function Registers
Description

Symbol

Direct
Address
EOH
FOH

Bit Address, Symbol or Alternative Port Function
MSB
LSB
E4
E3
E2
EO
E7
E5
E1
E6
FO
F5
F4
F3
F2
F1
F7
F6

ACC'
B*
DPTR:
DPH
DPL

Accumulator
B register
Data pointer (2 bytes)
Data pointer high
Data pointer low

IE'

Interrupt enable

A8H

AF
EA
BF

IP'

Interrupt priority

B8H

PO'

Port 0

80H

87
AD7

Pl'

Port 1

90H

P2'

Port 2

AOH

P3'

Port 3

BOH

PC ON

Power control

87H

PSW*

SBUF

Program status word
Capture high
Capture low
Serial data buffer

DOH
CBH
CAR
99H

SCON'
SP

Serial controller
Stack pointer

98H
81H

TCON*

Timer control

88H

OOH
OOH
OOH
OOH

83H
82H
AE
I

I -

A8
AD
AC
AB
AA
A9
I ET2 I ES I ETl I EXI I ETO I EXO OxOOOOOOB
B8
BD
BC
BB
BA
B9
I PT2 I PS I PTl I PX1 I PTO I PXO xxOOOOOOB

I AD6 I AD5 LAD4 J

96
I

95
I

94
I

83
AD3

93
I

82
AD2
92

RD IWR
SMODI -

B5
ITO
I

D7
CY

D6
AC

D5
FO

9F
SMO

9E
SM1

9D
SM2

B4
I Tl
I D4
RS1

FFH

91
IT2EXI

90
T2

FFH

AO
I A8

FFH

I INTil INTO I TxD I RxD
I GF1 I GFO I PD I IDL

D3
RSO

D2
OV

I -

I REN I

9B
TB8

9A
RB8

1 AD1 LADO

A7
A6
A5
A4
A3
A2
Al
A15 I A14 I A13 I A12 I All I AlO I A9
B7

RCAP2H#
RCAP2L#

Reset Value

8F
8E
8D
8C
8B
8A
TF1 I TR1 I TFO I TRO I lEI I ITl

99
TI

DO
P

98
RI

89
88
I lEO I ITO

FFH
OxxxxxxxB

OOH
OOH
OOH
xxxxxxxxB
OOH
07H
OOH

CF
CE
CD
CB
CC
CA
C9
C8
Timer 2 control
C8H
TF2 I EXF21RCLK ITCLK I E)CEN2 1 TR2 I C/T21 CP/RL2 OOH
Timer high 0
8CH
OOH
Timer high 1
8DH
OOH
Timer high 2
CDH
OOH
Timer low 0
8AH
OOH
Timer low 1
8BH
OOH
Timer low 2
CCH
OOH
Timer mode
89H
GATE I CIT I M1 I MO IGATE I CIT I M1 I MO OOH
* ~ BIt addressable
# ~ SFRs are modified from or added to the 80C51
Timer 2 as a baud rate generator is shown in Figure 6.
This Figure is valid only if RCLK + TCLK ~ 1 in
SFRs.
TICON. Note that a rollover in TH2 does not set TF2,
Table 2. Timer 2 Operating Modes
and will not generate an interrupt. Therefore, the Timer
2 interrupt does not have to be disabled when Timer 2 is
RCLK + TCLK CP/RL2 TR2
Mode
in the baud rate generator mode. Note too, that if
EXEN2 is set, a 1-to-0 transition in TIEX will set EXF2
0
0
1
16-bit Auto-reload
0
1
1
16-bit Capture
but will not cause a reload from (RCAP2H, RCAP2L) to
1
X
1
Baud rate generator
(TH2, TL2). Thus when Timer 2 is in use as a baud rate
X
X
0
(off)
generator, TIEX can be used as an extra external interrupt, if desired.
T2CON*#
THO
TH1
TH2#
TLO
TLl
TL2#
TMOD

February 1989

2-5

User's Guide

Signetics Microprocessor Products

8032/8052

Section 2 8051 - Derivatives
It should be noted that when Timer 2 is running (1m =

not be written to, because a write might overlap a reload
and cause write and/or reload errors. Turn the Timer off
(clear 1m) before accessing the Timer 2 or RCAP registers, in this case.

1) in "timer" function in the baud rate generator mode,
one should not try to read or· write 1H2 or 1L2. Under
these conditions the Timer is being incremented every
state time, and the results of a read or write may not be
accurate. The RCAP registers may be read, but should

The serial port in Modes 1 and 3 with the timer 2 baud
rate interface is shown in Figures 7 and 8.

TIMER2
OVERFLOW

WRITE

--~r--=~~~~~~--~~~--~----r-~ ~r-~

SBUF
TO

Txe

Rxe

TRANSMIT

716 RESET

R;~ux:

RECEIVE

!l!TAAT IITI

181

.T DETECTOR SAMPlE TIMEI

STOP81T

~SH~I~FT~________~L_ _ _ _JL-__- L__~____~__-L___ .~
~R~I

Jr----

______________________________________________________

Figure 7. Serial Port Mode 1 in the 8052

February 1989

2-6

User's Guide

Signetics Microprocessor Products

8032/8052

Section 2 8051 - Derivatives

TIMER 1
OVERFLOW

TIMER 2
OVERFLOW

WRITE

~-,~-::::£~~;r~--~=-----~---r~L- ~~

TO
SBUF

TXO

TCLKTI

TX
FLOCK!
R
• WRITE TO SBUF
- - - - , ftiiI!j
DATA C S1P1 I
SHIFT
fij)\STA.T .tTi
TI

L--JIL--__-"-__- - '____A-__...Jl.__.-.JL-__-'-___
I
I

00'

L-L-J

L-n

Ll!i::X::Q.L1 D3 ~~ru;;;;::;,:::S:T:::O:::P:::B;IT;==
I

DO
RXD BIT DETECTORI orA.T on I
SAMPLE TIMES
SHIFT
--L-__~~__JL____IL___~____~__~L____L____L____A_____
__________________________________________________________r____
~

RECEIVE

Figure 8. Serial Port Mode 3 in the 8052

February 1989

TRANSMIT

2-7

Signetics Microprocessor Products

User's Guide

8032/8052

Section 2 - 8051 Derivatives
TIMER/COUNTER 2 SET-UP
Except for the baud rate generator mode, the values given for 1'2CON do not include the setting of the TR2 bit.
Therefore, bit TR2 must be set, separately, to turn the
Timer on. See table 3 for set-up of timer 2 as a timer.
See table 4 for set-up of timer 2 as a counter.
Table 3. Timer 2 as a Timer
Mode

16-bit Auto-Reload
16-bit Capture
Baud rate generator receive and
transmit same baud rate
Receive only
Transmit only

T2CON
Internal External
Control
Control
(Note 1) (Note 2)
OOH
08H
01H
09H
34H
24H
14H

wo------__________

INTERRUPT

36H
26H
16H

SOUACEI

",------------------

Table 4. Timer 2 as a Couuter
Mode
16-bit
Auto-Reload

TMOD
Iuternal Control External Control
(Note 1)
(Note 2)
02H
OAH
03H
OBH

NOTES:
1. Capture/reload occurs only on timer/counter overflow.
2. Capture/reload occurs on timer/counter overflow and
a 1 to 0 transition on 1'2EX (PI. 1) pin except when
timer 2 is used in the baud rate generator mode.
USING TIMER/COUNTER 2
TO GENERATE BAUD RATES
For this purpose, Timer 2 must be used in the baud rate
generating mode. If Timer 2 is being clocked through
pin 1'2 (P1.0) the baud rate is:
Timer 2 Overflow Rate
Baud Rate

= ---------

16
And if it is being clocked internally the baud rate is:
Osc Freq
Baud Rate

32 x [65536 - (RCAP2H, RCAP2L)]
To obtain the reload value for RCAP2H and RCAP2L
the above equation can be rewritten as:
RCAP2H, RCAP2L

Osc Freq
65536 - - - - - 32 x Baud Rate

INTERRUPTS
The 8052 has 6 interrupt sources as shown in Figure 9.
All except TF2 and EXF2 are identical sources to those
in the 8051.

February 1989

Figure 9. 805218032 Interrupt Sources
The Interrupt Enable Register and the Interrupt Priority
Register are modified to include the additional 8052 interrupt sources. The operation of these registers is identical to the 8051. The registers are detailed in Figures
10, 11 and 12.
In the 8052, the Timer 2 Interrupt is generated by the
logical OR of TF2 and EXF2. Neither of these flags is
cleared by hardware when the service routine is vectored
to. In fact, the service routine may have to determine
whether it was TF2 or EXF2 that generated the interrupt, and the bit will have to be cleared in software.
All of the bits that generate interrupts can be set or
cleared by software, with the same result as though it
had been set or cleared by hardware. That is, interrupts
can be generated or pending interrupts can be canceled
in software.
The interrupt vector addresses and the interrupt priority
for requests in the same priority level are given in the
following:

2-8

Signetics Microprocessor Products

User's Guide

8032/8052

Section 2

IP REGISTER

HIGH PRIORITY
INTERRUPT

~~--~~4---~
I
I
I

TFO,-------~~~

~c>f~~---I....j
I
I
I

INTERRUPT
POLLING
SEQUENCE

~
II >J~H---++I
I
I

TFl-------+t--o'

~I ~-ro-~-4+I
I
I
I

>----...--j---r-~....J---I-~

RI
TI

TF2
EXF2

INDIVIDUAL
ENABLES

GLOBAL
DISABLE

Figure 10. 8052 Intermpt Control System
Source

Vector Address

1. IEO
2. TFO
3. IEI

0003H
OOOBH
0013H

4. TFI
5. RI + TI
6. TF2 + EXF2

OOlBH
0023H
002BH

Priority WithIn
Level
(highest)

(lowest)

Note that they are identical to those in the 8051 except
for the addition of the Timer 2 (TF1 and EXF2) interrupt at 002BH and at the lowest priority within a level.

PORT STRUCTURES
The port structures are identical in both parts, except
that on the 8052/8032 ports P1.0 and P1.1 include the
Timer 2 alternate functions as follows:
PLO
Pl.l

T2 (Timer/counter 2 external input)
T2EX (Timer/counter 2 capture/reload trigger)

As with the 8051, these alternate functions can only be
activated if the corresponding bit latch in the port SFR
contains a 1.

February 1989

2-9

LOW PRIORITY
INTERRUPT

User's Guide

Signetics Microprocessor Products

8032/8052

Section 2 - 8051 Derivatives

(MSB)

I EA
Symbol

(LSB)
IxlmIEsIET1IEXlIETOIEXO

Po8ItIon
IE.7

(MSB)

Function
disablaa all Interrupts. If EA = 0, no
Inlerrupt will be acknowledged. If EA - 1,
each Interrupt source is Individually
enabled or dI8abIad by setting or clearing
Its enable bit.

Symbol

(LSB)
IxlPT2lpslpT1lpXllPTOI PXO

PGlllllon

IP.7

Function
reserved

IP.6

reserved

PT2

IP.5

defines the Timer 2 interrupt priority
lavel. PT2 = 1 programs rt to the
higher priority laval.

IE.6

reserved.

ET2

IE.S

enables or disables the TImer 2 Overftow
or capture interrupt. If ET2 = 0, the TImer
2 Interrupt Is cfosabled.

IP.4

defines the Serial Port interrupt priority
laval. PS = 1 programs It to the
higher priority laval.

IE.4

enables or disables the SerIal Port
Interrupt. If ES = 0, the Serial Port
Interrupt Is disabled.

PT1

IP.3

defines the Timer 1 interrupt priority
laval. PT1 = 1 programs It to the
higher priority laval.

ETl

IE.3

enables or disables the Timer 1 Overflow
i$rrupt. If ETl = 0, the TImer 1 Interrupt
is disabled.

PXl

IP.2

EXl

IE.2

defines the Extarnallnterrupt 1 priority
level. PXl = 1 programs It to the
higher priority laval.

enables or disables External Interrupt 1. If
EXl = 0, Extarnallnterrupt 1 Is disabled.

PTO

IP.l

ETO

IE.l

enables or disables the nner 0 Overflow
Interrupt. If ETO = 0, the TImer 0 Interrupt
isdiaablad.

defines the TImer 0 interrupt priority
laval. PTO = 1 programs It to the
higher priority lavel.

PXO

IP.O

EXO

IE.O

enables or disables Extamallnterrupt O. If
EXQ = 0, ExternaIlntarrupt 0 18 disabled.

defines the Extarnallnterrupt 0 priority
level. PXO = 1 programs It to the
higher priority level.

•

Figure 11. 8052 Interrupt Enable (IE) Register

February 1989

Figure 12. 8052 Interrupt Priority (IP) Register

2-10

Signetics

SCN8032AH/SCN8052AH
Single-Chip 8-Bit Microcontroller
Product Specification

Microprocessor Division

DESCRIPTION
The Signetics SCNB032AH/SCNB052AH
is a high-performance microcontroller
fabricated using the Signetics highly reliable +5V, depletion-load, N -channel, silicon-gate, N500 MOS process technology. It provides the hardware features,
architectural enhancements and instructions that are necessary to make it a
powerful and cost-€ffective controller for
applications requiring up to 64K bytes of
programming memory and up to 64K
bytes of data storage.
The SCNB032AH contains 256 bytes of
read/write data memory, 32 I/O lines
configured as four B-bit ports, three 16bit timer/counters, a six-$ource twopriority-level nested interrupt structure, a
programmable serial I/O port and an onchip oscillator and clock circuitry. The
SCNB052AH has all of these features
plus BK bytes of non-volatile read-only
program memory. Both microcontrollers
ha ve memory expansion capabilities of
up to 64K bytes of data storage and 64K
bytes of program memory that may be
realized with standard TTL compatible
memories.
Because of its extensive BCD/binary
arithmetic and bit-handling facilities, the
SCNB032AH/SCNB052AH microcontroller is efficient at both computational and
control-oriented tasks. Efficient use of
program memory is also achieved by using the familiar compact instruction set
of the B031/B051. Forty-four percent of
the instructions are one-byte, 41 % twobyte, and 15% three-byte instructions.
With a 12MHz crystal, the majority of
the instructions execute in just 1.0j.lS.
The longest instructions, multiply and divide, require only 4j.1S at 12MHz.

FEATURES
• SCN8032AH - control-oriented
CPU with RAM and I/O
• SCN8052AH - an SCN8032AH
with factory mask-programmable ROM
• 8K X 8 ROM (SCN8052AH only)
.256 X 8 RAM
• 32 I/O lines (four 8-bit ports)
• Three 16-bit timer/counters
• Programmable full-duplex serial
channel
- Variable transmit/receive
baud rate capability
• Timer 2 capture capability
• External memory addressing
- 64K ROM and 64K RAM
• Boolean processor
• 128 user bit-addressable
locations
• Upward compatible with
SCN8031 AH/SCN8051 AH

40 Vee
~ PO.O/ADO

T2/P1.0'1
T2EX/P1.1

P1.2~

38 PO.1/AD1

P1.3~

P1.4~

~ PO.3/AD3

:~::~

~ :~::~~~:
~ PO.6/AD6

RST

~ PO.7/AD7

f2.

RxD/P3.0~

DIP

~/P3.1 ~
~/P3.2~
INT1/P3.3~

TO/P3.4~

~ P2.6/A14
~ P2.5/A13

~/P3.6~

~ P2.4/A12

RD/P3.7g

~ P2.3/A11

XTAL2~

~ P2.2/A10

XTAL1 ~

~ P2.1/A9
~ P2.0/ A8

TOP VIEW
INDEX
CORNER

rr-

~=
~
~-l:!

t~.
]~li

~t~~ '~-~

-T2

u..1RI'l-t;;:
~

TO-~

<~-

!!
8R!l-

....
en

2-11

PLCC

....
-:5

8'"

PSEN
ALE

31 EA

~ ALE
~ PSEN
~ P2.7/A15

..!!./P3.5~

LOGIC SYMBOL

PO.2/AD2

P1.7~

Vss.gg

::>mrn- ..,

February 1989

PIN CONFIGURATION

TOP VIEW
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

Function
NC
T2/P1.0
T2EX/P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
RxD/P3.0
NC
TxD/P3.1
iFlTO/P3.2
mTT/P3.3
TO/P3.4
T1/P3.5
WI1/P3.6
R[)/P3.7
XTAL2
XTAL1
Vss

Pin
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44

Function
NC
P2.0/AS
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15

!5Srn

ALE
NC
~
PO.7/AD7
PO.6/AD6
PO.5/AD5
PO.4/AD4
PO.3/AD3
PO.2/AD2
PO.1/AD1
PO.O/ADO
Vee

Product Specification

Signetics Microprocessor Products

SCN8032AH/SCN8052AH

Single-Chip 8-Bit Microcontroller
ORDERING INFORMATION

ROM~R:a==5ce:)HCCCICC ::L::

32 - Extl256
52 - 8K/256

Power
Consumption
H

-P~:~~c:~

PART NUMBER SELECTION
Temperature and
ROM
Package

ROM less
ROM Pattern No,

Applies to masked ROM versions
only. Number will be assigned by
Signetics. Contact Signetics sales
office for ROM pattern submission
requirements.

Pins
40 - 40-pin
44 - 44-pin

SCNS032HCCA44 SCN8052HCCA44

o to +70·C, plastiC DIP
o to + 70·C, plastic LCC

SCNS032HACN40 SCN8052HACN40

-40 to +85·C, plastic DIP

3.5 to 12MHz

SCNS032HACA44 SCNS052HACA44 -40 to +S5·C, plastiC LCC 3.5 to 12MHz

o to +70·C, plastic DIP
o to + 70·C, plastic PLCC

3.5 to 15MHz

SCNS032HCFA44 SCN8052HCFA44
SCNS032HAFN40 SCNS052HAFN40

-40 to +85·C, plastic DIP

3.5 to 15MHz

SCN8032HCFN40 SCNS052HCFN40

Package
A - Plastic LCC
I - Ceramic DIP
N - Plastic DIP

Frequency
3.5 to 12MHz

SCN8032HCCN40 SCN8052HCCN40

3.5 to 15MHz

SCN8032HAFA44 SCN8052HAFA44 -40 to +85·C, plastic PLCC 3.5 to 15MHz

Speed

C - 3.5 to 12MHz
F - 3.5 to 15MHz
Operating Temperature Range
A - -40·C to +85·C
C - O·C to +70·C

BLOCK DIAGRAM

--------l

PCON

scaN TIoIOD

T2CON THO TLO
TL,
TH2 TL2
RCIIP2l SBUF IE

iiSEN ~_.r--"""-::;"I
ALE

RST

PUH".7

February 1989

2-12

TCON

THI
RCIIP2H
IP

Signetics Microprocessor Products

Product Specification

Single-Chip 8-Bit Microcontroller

SCN8032AH/SCN8052AH

PIN DESCRIPTION
PIN NO.

MNEMONIC

TYPE

NAME AND FUNCTION

DIP

LCC

Vss

Ground: OV reference.

Vee

Power Supply: This is the power supply voltage for normal operation.

PO.0-PO.7

39-32 43-36

P1.0-P1.7

1-8

2-9

1
2

1/0

Port 0: Port 0 is an open-drain, bidirectional 1/0 port. Port 0 is also the multiplexed
low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pullups when emitting 1s. Port 0 also
outputs the code bytes during program verification.

1/0

Port 1: Port 1 is an 8-bit bidirectional 1/0 port with internal pull-ups. Pins P1.0 and
P1.1 also correspond to the special functions T2, timer 2 counter trigger input, and
T2EX, external input to timer 2. The output latch on these two special functions must
be programmed to one for that function to operate. Port 1 also receives the low-order
address byte during program verification.

T2 (P1.0): Timerlcounter 2 trigger input.
T2EX (P1.1): Timerlcounter 2 external count input.

P2.0-P2.7

21-28 24-31

1/0

Port 2: Port 2 is an 8-bit bidirectional 1/0 port with internal pUll-ups. Port 2 emits the
high-order address byte during fetches from external program memory and during
accesses to external data memory that use 16-bit addresses (MOVX @DPTR). During
accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 emits
the contents of the P2 special function register.

P3.0-P3.7

10-17

11,
13-19

1/0

Port 3: Port 3 is an 8-bit bidirectional 1/0 port with internal pull ups. Port 3 is also used
for the special features listed below:
.

10
11
12
13
14
15
16
17

11
13
14
15
16
17
18
19

o
o

RST

Reset: A high on this pin for two machine cycles while the oscillator is running, resets
the device. A small external pull-down resistor (= 8.2KQ) from RST to Vss permits
power-on reset when a capacitor (= 10!d) is also connected from this pin to Vee.

ALE

1/0

Address Latch Enable: Output pulse for latching the low byte of the address during an
access to external memory. In normal operation, ALE is emitted at a constant rate of
1/6 the oscillator frequency, and can be used for external timing or clocking. Note that
one ALE pulse is skipped during each access to external data memory.

Program Store Enable: The read strobe to external program memory. When the device
is executing code from externa.L.EJ:Qgram memory, PSEN is activated twice each
machine cycle, except that two PSEN activations are skipped during each access to
external data memory. PSEN Is not activated during fetches from internal program
memory.

External Access Enable: EA must be externally held low to enable..!l!.e device to fetch
code from external program memory locations OOOOH and 1 FFFH. If EA is held high, the
device executes from internal program memory unless the program counter contains an
address greater than 1 FFFH.

XTAL1

Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock
generator circuits.

XTAL2

Crystal 2: Output from the inverting oscillator amplifier.

February 1989

o
I
I
I
I

RxD (P3.0): Serial input port
TxD (P3.1): Serial output port
INTO (P3.2): External interrupt
INT1 (P3.3): External interrupt
TO (p3.4): Timer 0 external input
!!JP3.5): Timer 1 external input
WR (P3.8): External data memory write strobe
RD (P3.7): External data memory read strobe

2-13

Product Specification

Signetics Microprocessor Products

SCN8032AH/SCN8052AH

Single-Chip 8-Bit Microcontroller
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier. The pins can be configured for use
as an on-chip oscillator, as shown in the
logic symbol, page 1.

To drive the device from an external
clock source, XTAL2 should be driven
while XTAL1 should be grounded. There
are no requirements on the duty cycle of
the external clock signal, because the
input to the internal clock circuitry is
through a divide-by-two flip-flop. However, minimum and maximum high and
low times specified in the data sheet
must be observed.

RESET
A reset is accomplished by holding the
RST pin high for at least two machine
cycles (24 oscillator periods), while the
oscillator is running.

ABSOLUTE MAXIMUM RATINGS1. 2. 3
RATING

UNIT

Storage temperature range

-65 to +150

°C

All voltages with respect to ground

-0.5 to +7.0

2.0

PARAMETER

Power dissipation

DC ELECTRICAL CHARACTERISTICS TA - O°C to +70°C , Vee - 5V ±10%, Vss - OV4, 5
Parameter

Symbol
VIL

Input low voltage

VIH

Input high voltage, except RST and XTAL2

VIH1

Input high voltage to RST for reset, XTAL2

VOL

Output low voltage, ports 1, 2, 3 6

Test Conditions

Limits
Min

Max

Unit

-0.5

O.S

Vee+0.5

2.5

Vee+0.5

IOL - 1.6mA

0.45

XTAL1 to Vss

VOLl

Output low voltage, port 0, ALE, PSEN6

IOL - 3.2mA

VOH

Output high voltage, ports 1, 2, 3

IOH - -SOj.lA

2.4

VOH1

Output high voltage port 0 in external bus
mode, ALE, PSEN)3

IOH - -400j.lA

2.4

VIN - 0.45V

-SOO

j.lA

VIN - Vee - 1.5V

500

j.lA

IlL

Logical 0 input current, ports 1, 2, 3

IIH1

Input high curent to RST for reset

III

Input leakage current, port 0, EA

0.45 < VIN < Vee

±10

j.lA

IIL2

Logical 0 input current for XTAL2

XTAL1 - Vss, VIN - 0.45V

-3.2

rnA

lee

Power supply current

All outputs disconnected
and EA - Vee

175

rnA

fe - 1MHz, TA - 25°C

CIO
TA

Pin capacitance

=-40°C to +85°C -

Extended temperature range - SCNS052HAC only

VIH

Input high voltage, except RST and XTAL2

VIHl

Input high voltage to RST for reset, XTAL2

lee

Power supply current

2.2
XTAL1 to VSS
All outputs disconnected
and EA - Vee

Vee+0.5

V
V

2.7
175

rnA

NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
2
3.
4.

functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied.
For operating at elevated temperatures, the device must be derated based on +150 0 C maximum junction temperature.
This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying voltages greater than the ratee! maxima.
Parameters are valid over operating temperature range unless otherwise specified.

All voltage measurements are referenced to ground. For testing, all input signals swing between 0.45V and 2.4V with a transition time of
20ns maximum. All time measurements are referenced at input voltages of 0.8V and 2.0V and at output voltages of 0.8V and 2.0V as
appropriate.

VOL is degraded when the device rapidly discharges external capacitance. This AC noise is most pronounced during emission of address
data. When using external memory, locate the latch or buffer as close to the device as possible.

Emitting
Degraded
Datum
Ports
I/O Lines
P2. PO
Pl, P3
Address
Write Data
PO
P1, P3, ALE
7. eL - 100pF for port 0, ALE and PSEN outputs; eL - 80pF for all other ports.

February 1989

2-14

VOL (Peak Max)
0.8V
0.8V

Product Specification

Signetics Microprocessor Products

SCN8032AH/SCN8052AH

Single-Chip 8-Bit Microcontroller

AC ELECTRICAL CHARACTERISTICS TA - O°C to +70°C or -40°C to +85°C, VCC - 5V ±10%, Vss - OV1, 2

Pro!lram Memo
l/tCLCL

12MHz CLOCK

PARAMETER

SYMBOL FIGURE

Min

Max

VARIABLE CLOCK
Min

Max

3.5
3.5

12
15

tLHLL
tAvLL
tLLAX
tLLlV

1
1
1
1

Oscillator frequency: Speed Versions
SCN8052
C
SCN8052
F
ALE pulse width
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in

tLLPL

ALE low to PSEN low

tel CI -25

tpLPH
tpLiV

PSEN pulse width

215

3tCLCL-35

PSEN low to valid instruction in

tpXIX

Input instruction hold after PSEN

tPXIZ
tAVIV

1
1

Input instruction float after PSEN
Address to valid instruction in

tpIA7

PSEN low to address float

1
tpXAV
Data Memory
2
tRLRH

2tCLCL 40
tCLCL 40
tCLCL-35

127
43
48
233

4tCLCL -100

125

MHz
MHz
ns
ns
ns
ns
ns
ns

3tCLCL -125

tCLCL -20

302

5tCLCL -115

PSEN to address valid

UNIT

tCLCL-8

ns
ns

RD pulse width

400

6tCLCL -100

tWLWH

WR pulse width

400

6tCLCL-100

tRLDV

RD low to valid data in

tRHDX

Data hold after R 0

tRHD7
tLLDV
tAVDV

2
2
2

Data float after RD
ALE low to valid data in
Address to valid data in

tLLWL

2, 3

ALE low to RD or WR low

200

tAVWL

2, 3

Address valid to WR low or RD low

203

252
0

ns
5tCLCL -165

97
517
585
300

2tci CI -70
8tCLCL-150
9tCLCL -165
3tCLCL-50

ns
ns

3tCLCL+50

ns
ns
ns
ns

4tcLCL -130

tOVWX

Data valid to WR transition

tCLCL-60

t()VW~

Data vaid to WR high

433

7tCLCL-150

tWHOX

Data hold after WR

tCLCL-8

tRLAZ

RD low to address float

tWHLH
External
tCHCX

2, 3
lock
5

5
tCLCX
5
tCLCH
5
tCHCL
Shift Register
4
tXLxL
tOVXH
tXHOX
tXHDX
tXHDV

4
4
4
4

RD or WR high to ALE high

123

tCLCL-40

High time

Lr.w time
Rise time
Fall time

Serial port clock cycle time

1.0

Output data setup to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid

700
50
0

ns
20

tCLCL+40

ns
ns

20
20

ns
ns
ns

10tCLCL-133

ns
ns
ns
ns

12tCLCL
10tCLCL-133
2tCLCL-117
0
700

f.LS

NOTES.
1. Parameters are valid over operating temperature range unless otherwise specified.

2. Load capacitance for port 0, ALE, and PSEN - 100pF, load capacitance for all other outputs - 80pF.
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has five characters. The first character is
always '1' (- time). The other characters, depending on their
positions, indicate the name of a signal or the logical status of
that Signal. The designations are:
A - Address
C - Clock
o - I nput data
H - Logic level high
I - I nstruction (program memory contents)
L - Logic level low, or ALE
February 1989

P- PSEN
Q - Output data

R - RD signal
t - Time
V - Valid
W -WR signal
X - No longer a valid logic level
Z - Float
Examples: tAvLL - Time for address valid to ALE low.
tLLPL - Time for ALE low to PSEN low.

2-15

Product Specification

Signetics Microprocessor Products

SCN8032AH/SCN8052AH

Single-Chip 8-Bit Microcontroller

ALE

~ _ _ _J

PORTO _ _ _ _
~
1o---tAVIV-----.I

PORT 2

A8-A15

Figure 1. External Program Memory Read Cycle

ALE

J.--

WHLH

PsE"N
tLLDV

I---

t LLWL

"t AVLL

PORTO

tRLRH

I---t foo- tLLAX-o

~ . _''')"

io--tRLDv--o

II--

AO-A?

/
tRHDX .....
tRLAZ
DATA IN

'" n" np, 1'1

tRHDZ

»>K

AO-A? FROM PCL

INSTR IN

tAVWL
t AvDV
PORT 2

P2.0-P2.? OR A8-A 15 FROM DPH

A8-A15 FROM PCH

Figure 2. External Data Memory Read Cycle

ALE

/
0-----0

tWHLH

ffiN

I---- t LLWL

"'
I--

WR
tAVLL

i----<

I--tLLAX ""

t WLWH

Io--t

tOVWX

t WHOX

tOVWH

PORTO~ . Fom ~g~~~

no,

DATA OUT

AO-A? FROM PCL

tAVWL -

PORT 2

P2.0-P2.? OR A8-A15 FROM DPH

Figure 3. External Data Memory Write Cycle

February 1989

2-16

A8-A15 FROM PCH

INSTR IN

Product Specification

Signetics Microprocessor Products

SCN8032AH/SCN8052AH

Single-Chip 8-Bit Microcontroller

INSTRUCTION

ALE

tOVXH

,'----,J

OUTPUT DATA

t XHOX

'---".J '-_---J ' - - - - ' '-_---J ' - - _ - ' '-_---J

~_.J

WRITE TO SBUF
I INPUT DATAl _ _ _ _ _ _..1

CLEAR RI

SET RI

Figure 4. Shift Register Mode Timing

Vee-O.5·--------

O.7Vce

0.45V

~---------tcLCL-----~

Figure 6. External Clock Drive

Vee-O.5
O.45V

O.2Vcc+O.9

Timing

Reference
Points

_..O_.2_V;.;;e.;;.e-...:O;,;.;.1~_ _

AC inputs during testing are driven at Vcc-O.S
for a logic H1 Hand O.4SV for a logic HOH.
Timing measurements are made at VIH min for
a logic H1 H and V IL max for a logic ·0·.

For timing purposes, a port Is no longer floating
when a 100mV change from load voltage occurs,
and begins to float when a 100mV change from
the 10adedVOHlVOL level occurs.IOH/IOL~±20mA.

Figure 6. AC Testing Input/Output

February 1989

Figure 7. Float Waveform

2-17

User's Guide

Signetics Microprocessor Products

8XC451

Section 2 - 8051 Derivatives
8XC451 OVERVIEW

DIFFERENCES FROM THE 8051

The SC80C4S1, the SC83C4S1, and the SC87C4S1
(hereafter referred to collectively as the 83C4S1) are
I/O expanded versions of the 80CSl. Three I/O ports
have been added to the basic 80CS1 architecture for a
total of 7 on-chip I/O ports. The LCC version has a total
of 68 pins. The DIP version has 64 pins. Port 6 has 4
control lines to facilitate high-speed asynchronous I/O
functions.

SPECIAL FUNCTION REGISTERS

The 83C451187C4S1 includes a 4K X 8 ROM/EPROM, a
128 X 8 RAM, 56 (LCC) or 52 (DIP) I/O lines, two 16bit timer/counters, a five source, two priority, level nested interrupt structure, a serial I/O port for either full
duplex UART, I/O expansion, or multiprocessor communications, and an on-chip oscillator and clock circuits.
The 8OC4S1 includes all of the 83C4S1 features except
the on-board 4K X 8 ROM.
The 83C4S1 has two software selectable modes of reduced activity for further power reduction: idle mode and
power-down mode. Idle mode freezes the CPU while allowing the RAM, timers, serial port, and interrupt system to continue functioning. Power-down mode freezes
the oscillator, causing all other chip functions to be inoperative while maintaining the RAM contents.

The SFRs are identical to those of the standard 80CS1
with the exception of four registers that have been added
to allow control of the three additional I/O ports P4 PS
and P6. The additional registers are P4, PS, P6,~ and
CSR. Registers P4, PS, and P6 function as port latches
for ports 4, 5, and 6 respectively. These registers operate identically to those for ports 0 through 3 of the
80CSl.
The Control Status Register (CSR) is used to control the
mode of operation of port 6 and indicates the current
status of port 6. All control status register bits can be
read and written by the CPU except bits 0 and 1, which
are read only. A Reset writes ones to bits 2-7 and zeros
to bits 0 and 1. See Table 5 for the specific function of
each bit in the Control Status register.
The SFR addresses for the 83C451 are identical to those
in the 80CS1 except for the additional registers P4, P5,
P6, and CSR. Table 6 lists the SFR addresses bit
names and addresses (where applicable), and reset'values for the 83C4S1. Table 7 is a detailed expansion of
the special function registers.
110 PORT STRUCTURE

The 83C4S1 features include:

The 8XC4S1 has a total of seven parallel I/O ports. The
first four ports, PO through P3, are identical in function
to those present on the 80CS1 family. The added ports 4
and 5 are identical in function to port 1, that is, they are
standard quasi-bidirectional ports with no alternate functions and the standard output drive characteristics. Note
th~t on the 68-pin LCC packages, port 4 is an 8-bit port,
while on the 64-pin DIP packages, only the lower four
bits of port 4 are available. Port 6 is a specialized 8-bit
bidirectional I/O port with internal pull ups. This special
port can sink/source three LS TTL inputs and drive
CMOS inputs without external pullups. The flexibility of
this port facilitates high-speed parallel data communications. Port 6 operating modes are controlled by the port

• 80C51 based architecture
• 68-pin LCC and 64-pin DIP packages
• Seven 8-bit I/O ports (LCC Version)
• Six 8-bit ports and one 4-bit port (DIP version)
• 4K X 8 ROM or EPROM
.128 X 8 RAM
• Two 16-bit counter/timers
• Two external interrupts
• External memory addressing capability
- 64K ROM and 64K RAM
• Low power consumption
- Idle Mode
- Power-down mode

Table S. Control Status Register (CSR)
Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

MB1

MBO

MA1

MAO

OBFC

IOSM

OBF

ISF

Output Buffer
Flag Clear
Mode

Input Data
Strobe Mode

Output Buffer
Full-Flag

Input Buffer
Full Flag

0- Output
data buffer
empty

0- Input
data buffer
empty

BFLAG Mode Select
0/0 - Logic 0 output"
011 - Logic 1 output"
110 - IBF output
1/1 - PE input
(0 - Select)
(1 - Disable I/O)

AFLAG Mode Select
0/0
0/1
1/0
1/1

- Logic 0 output
- Logic 1 output
- OBF output"
- SEL input
(0 - Data)
(1 - Control/status)

Positive
0
N~veO
edge of ODS
edge of IDS
1
Positive 1 =_bpw level
of IDS
edge of ODS

Bit 0

1 - Output
1 - Input .
data buffer full data buffer full

NOTE:
"Output-always mode: MB1 - 0, MA1 - 1, and MAO - O. In this mode, port 6 is always enabled for output ODS only clears
th.e OBF flag.
.

February 1989

2-18

User's Guide

Signetics Microprocessor Products

8XC451

Section 2 - 8051 Derivatives
Table 6. Special Function Register Addresses
REGISTER ADDRESS
Name
Port
Port
Port
Port

4
5
6 data
6 control status

BIT ADDRESS

Symbol

Address

P4
P5
P6
CSR

CO
C8
D8
E8

MSB
C7
CF
DF
EF

6 Control Status Register (CSR). Port 6 and 111e CSR
are addressed at 111e Special Function Addresses shown
in Table 6. Port 6 can be used as a standard I/O port,
or in strobed modes of operation in conjunction wi111 111e
four port 6 control lines listed below:
ODS
IDS
BF1.AG

AF1.AG

Output data strobe (active low)
Input data strobe (active low)
Bidirectional I/O pin. Can be programmed
to output 111e Input Buffer Full flag (IBF),
input an active low Port Enable (PE) signal, or output a high or low logic level.
Bidirectional I/O pin. Can be programmed
to output 111e Output Buffer Full (OBF)
flag, input a register select signal (SEL),
or output a high or low logic level.

Port 6 can be used in a number of different ways to facilitate data communication. It can be used as a processor bus interface, as a standard quasi -bidirectional I/O
port, or as a parallel printer port (ei111er polled or interrupt driven).
PROCESSOR BUS INTERFACE
Port 6 allows 111e use of an 83C451 as an element on a
microprocessor type bus. The host processor could be a
general purpose MPU or 111e data bus of a microcontroller like 111e 83C451 itself. Setting up 111e 83C451 as a
processor bus interface allows single or multiple
microcontrollers to be used on a bus as flexible peripheral processing elements. Applications can include:
keyboard scanners, serial I/O controllers, servo controllers, etc.

C5
CD
DD
ED

C4
CC
DC
EC

C3
CB
DB
EB

C2
CA
DA
EA

C1
C9
D9
E9

CO
C8
D8
E8

STANDARD QUASI-BIDIRECTIONAL 110 PORT
To use port 6 as a common I/O port, all of 111e control
pins should be tied to ground. On hardware reset, bits
2-7 of 111e CSR are set to one. Wi111 111e control pins
grounded, 111e Port's operation and electrical characteristics will be identical to port 1 on 111e 80C51. No fur111er
software initialization is required.
PARALLEL PRINTER PORT
The 83C451 has 111e capacity to permit all of 111e intelligent features of a common printer to be handled by a
single chip. The features of Port 6 allow a parallel port
to be designed wi111 only line driving and receiving chips
required as additional hardware. The onboard UART allows RS232 interfacing wi111 only level shifting chips added. The 8-bit parallel ports 0 to 6 are ample to drive
onboard control functions, even when ports are used for
external memory access, interrupts, and o111er functions.
The RAM addressing ability of ports 0 to 2 can be used
to address up to 64K bytes of a hardware buffer/spooler.
In addition, ei111er end of a parallel interface can be implemented using port 6, and 111e interfaces can be interrupt driven or polled in ei111er case. For more detailed
information on port 6 usage, refer to 111e application
notes contained in Section 3, entitled "80C451 Operation
of Port 6" and "256K Centronics Printer Buffer Using
111e SC87C451 Microcontroller".

On reset, Port 6 is programmed correctly (111at is Special Function registers CSR and P6) for use as a bus interface. This prevents 111e interface from disrupting data
on 111e bus of a host processor during power-up.

February 1989

LSB
C6
CE
DE
EE

2-19

User's Guide

Signetics Microprocessor Products

8XC451

Section 2 - 8051 Derivatives
Table 7. 8X4S 1 Special Function Registers
Symbol
ACC*
B*

Description

Direct
Address

Bit Names and Addresses
LSB

MSB

Accumulator
B register

EOH
FOH

E7
F7
EF
MB1

E6
F6
EE

E5
F5
ED

E4
F4
EC

E3
F3
EB

E2
F2
EA

El
F1
E9

I MBO I MAl I MAO IOBFC IIDSM I OBF

EO
FO
E8

CSR*#

Port 6 command/status

E8H

DPTR:
DPH
DPL

Data pointer (2 bytes):
High byte
Low byte

83H
82H

IP*

Interrupt priority

B8H

IE*

Interrupt enable

A8H

PO·
P1*
P2*
P3*
P4*#
P5*#
P6*#

Port
Port
Port
Port
Port
Port
Port

80H
90H
AOH
BOH
COH
C8H
D8H

PCON

Power control

87H

SMOni

PSW*

Program status word

DOH

SBUF

Serial data buffer

99H

SCON*

Serial port control

98H

Stack pointer

81H

TCON*

Timer/counter control

88H

TF1 I TRI I TFO I TRO I lEI I ITl I lEO I ITO
GATE I CIT I MI I MO IGATEI CIT I MI I MO

I -

89H
8CH
8DH
8AH
8BH

0
1
0
I

high byte
high byte
low byte
low byte

I PS
AC

AC I FO

I PT1 I PX1 I PTO I PXO xxxOOOOOB
AB

OxxOOOOOB
FFH
FFH
FFH
FFH
FFH
FFH
FFH

I GF1 I GFO I PD I IDL OxxxOOOOB
D3

I RS1 I RSO I OV I

DO
I

SMO I SM1 I SM2 I REN I TB8 I RB8 I TI

I RI

OOH

OOH
07H

88
OOH
OOH
OOH
OOH
OOH
OOH

*SFRs are bit addressable.
#SFRs are modified from or added to the 80C5I SFRs.

February 1989

xxxxxxxxB

Timer/counter mode

Timer
Timer
Timer
Timer

I IBF FCH

EA I - I - I ES I ETl I EX1 I ETO I EXO
87
B6
85
84
83
82
81
80
93
92
91
90
96
97
95
94
A7
A6
AS
A4
A3
A2
A1
AO
B7
B6
B5
B4
B3
B1
B2
BO
C7
C6
C5
C4
C3
C2
C1
CO
CF
CE
CD
CC
CB
CA
C9
C8
DF
DE
DD
DC
D9
D8
DB
DA

TMOD

THO
TH1
TLO
TLl

OOH
OOH

OOH
OOH
BF

0
1
2
3
4
5
6

Reset Value

2-20

Signetics

SC80C451/SC83C451
CMOS Single-Chip 8-Bit
Microcontroller
Product Specification

Microprocessor Division
DESCRIPTION
The Signetics SCBOC451/SCB3C451 is
an I/O expanded, single-chip microcontroller fabricated with Signetics highdensity CMOS technology. Signetics
epitaxial
substrate minimizes latch-up
sensitivity.
The SCBOC451/SCB3C451 is a functional
extension of the SCBOC51 microcontroller with three additional I/O ports and
four I/O control lines. The LCC version
has a total of 6B pins. Four control lines
associated with port 6 facilitate high
speed asynchronous I/O functions.
The SCB3C451 includes a 4K X B ROM,
a 12B X B RAM, 56 (LCC) or 52 (DIP)
I/O lines, two 16-bit timer/counters, a
five source, two priority level, nested interrupt structure, a serial I/O port for either a full duplex UART, I/O expansion,
or multiprocessor communications, and
an on-chip oscillator and clock circuits.
The SCBOC451 includes all the SCB3C451 features except the on-board 4K
X B ROM.
The SC80C451/SCB3C451 has two software selectable modes of reduced activity for further power reduction: idle mode
and power-down mode. Idle mode freezes the CPU while allowing the RAM, timers, serial port, and interrupt system to
continue functioning. Power-down mode
freezes the oscillator, causing all other
chip functions to be inoperative while
maintaining the RAM contents.

PIN CONFIGURATIONS

FEATURES
• User programmable microcontrolier
• SC80C51 based architecture
• 88-pin LCC and 84-pin DIP
packages:
- Seven 80bit I/O ports (LCC
version)
- Six 80bit ports and one 40bit
port (DIP version)
• Port 8 features:
- 8 data pins
- 4 control pins
- Direct MPU bus interface
- Parallel printer interface
• On the microcontrolier
- 4K X 8 ROM (SC83C451 only)
- 128 X 8 RAM
- Two 180bit counter/timers
- Two external interrupts
• External memory addressing
capability
- 84K ROM and 84K RAM
• Low power consumption:
- Normal operation: less than
24mA at 5V, 12MHz
- Idle mode
- Power-down mode

LOGIC SYMBOL

'64 ALE
~ PSEN

EA"

P2.0/AB
P2.1/A9 ~
P2.21 A10
P2.3/A11 ~
P2.4/A12 ~
P2.5/A13 ~

~ P6.7

~
~

§I
~

P2.6/A14~

P2.7/A15 ~
PO.7/AD7 ~
PO.61 AD6 ~

~
~

~ ~AG

PO.5/AD5tl¥
P0.41 AD4 1

~ ~

PO.3/AD3~

ODS
50 Vss
~ XTAL1

PO.21 AD2 ~

PO.1/AD1

PO.O/ADO ~

DIP

Vee ~

¢.g XTAL2
J!Y P5.7

P4.3~

~ P5.6

P4.2~

~ P5.5

P4.1 ~
P4.0

~4 P5.4
t!,3 P5.3

P1.og

~2 P5.2
~ P5.1
jiG P5.0 _

P1.1~
P1.2~

I
I

P6.6
P6.5
P6.4
P6.3
P6.2
P6.1
P6.0
AFLAG

F!l

P1.3~
P1.4g
P1.5 ~
P1.6 ~

P3.7/~

~ P3.6/WR

~ P3.5/T1
36 P3.4/TO

P1.7~

P3.3/1NT1

~ P3.2/INTO

RST 31
P3.0/RxD

P3.1/TxD

TOP VIEW

INDEX

'"""~M
26CJ44
27
43
TOP VIEW

See next page for LCC pin functions

F ebrua ry 1989

2-21

Product Specification

Signetics Microprocessor Products

SC80C451/SC83C451

CMOS Single-Chip 8-Bit Microcontroller
ORDERING INFORMATION

::c
1

1
ROM::.:r:: CCCC C

ROMless
3 - ROM

PART NUMBER SELECTION
ROMlesa
SC80C451CCN64
SC80C451CGN64
SC80C451CBN64
SC80C451 CCA68
SC80C451 CGA68
SC80C451 CBA68
SC80C451 ACN64
SC80C451AGN64
SC80C451 ACA68
SC80C451 AGA68

ROM Pattern No.

Applies to masked ROM versions
only. Number will be assigned by
Sig netics. Contact Sig netics sales
office for ROM pattern submission
requirements.

Pins
64 - 64-pin DIP
68 - 68-pln PLCC
Package
A - Plastic PLCC
N - Plastic DIP
Speed
B - 0.5 to 12MHz
C - 3.5 to 12MHz
G - 3.5 to 16MHz

ROM

Temp8rature and Package

SC83C451CCN64
SC83C451CGN64

o to +7000 plastic DIP
o to +7000 plastic DIP
o to +7000 plastic DIP
o to +70°C plastic LGC
o to +70°C plastic LCC
o to +7000 plastic LCC

SC83C451CBN64
SC83C451 CCA68
SC83C451 CGA68
SC83C451CBA68
SC83C451ACN64
SC83C451AGN64
SC83C451 ACA68
SC83C451 AGA68

Operating Temperature Range
A - _40°C to +85 0 C
C - OOC to +70 0 C

LCC PIN FUNCTIONS

INDEX

~tj
10

LCC

44
27
43
TOP VIEW

Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

17
18
19
20
21
22
23

February 1989

Function
EA
P2.0/A8
P2.1/A9
P2.2/Al0
P2.3/All
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
PO.7/AD7
PO.6/AD6
PO.5/AD5
PO.4/AD4
PO.3/AD3
PO.2/AD2
PO.l/ADl
PO.O/ADO
Vcc
P4.7
P4.6
P4.5
P4.4
P4.3

Pin
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46

Function
P4.2
P4.1
P4.0
Pl.0
Pl.l
Pl.2
Pl.3
Pl.4
Pl.5
Pl.6
Pl.7
RST
P3.0/RxD
P3.1/TxD
P3.2/iFffii
P3.3/iNi'i
P3.4/TO
P3.5/Tl
P3.6/iNIi
P3.7/im
P5.0
P5.1
P5.2

2-22

Pin
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68

Function
P5.3
P5.4
P5.5
P5.6
P5.7
XTAL2
XTALI

BFLAG
AFLAG
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
P6.7

PSEN
ALE

-40 to +85°C plastic DIP
-40 to +8500 plastic DIP
-40 to +85°C plastic LCC
-40 to +8500 plastic LCC

~
2

-<~

co
00

)0
Q

i------Ttf[-F-'ieTiF------.~--:

cO"
;

g.fh

en~
_

en §

11
"0

"0
00

III
;::+

o·

a
(")

SBUF IE

~:i:::1
n= li~~II!f
RST~
CONIROL

I
I

I~=~I

11:-".:,.. ':
U 11

~
~

1T
IT

I~....-----.
~
~
DPTR

_____ J

::J

I~
en

o00
o
oJ::o.

....

o00
w
oJ::o.

""5l

en !l8.c:

....

=
0"
~

:::l

Signetics Microprocessor Products

Product Specification

CMOS Single-Chip 8-Bit Microcontroller

SC80C451/SC83C451

PIN DESCRIPTION
PIN NO.
MNEMONIC DIP PLCC TYPE
Vss
50
54
I
Vee
18
18
I
PO.0-PO.7 17-1017-10 I/O

P1.0-P1.7 23-3027-34 I/O

P2.0-P2.7

2-9

I/O

P3.0-P3.7 32-39 36-43 I/O

32
36
I
33
37
0
34
I
38
35
39
I
36
40
I
37
41
I
38
42
0
39
43
0
P4.0-P4.3 22-19
I/O
P4.0-P4.7
26-19 I/O
P5.0-P5.7 40-47 44-51 flO
P6.0-P6.7 55-62 59-66 I/O

ODS
IDS
BFLAG
AFLAG
RST

51
52
53
54
31

55
56
57
58
35

I
I
I/O
I/O
I

ALE

PSEN

XTAL1

XTAL2

February 1989

NAME AND FUNCTION
Ground: OV reference.
Power Supply: This is the power supply voltage for normal, idle, and power-<:town operation.
pon 0: Port 0 is an 8-blt open-<:train, bidirectional I/O port. Port 0 is also the multiplexed data
and low-order address bus during accesses to external memory. External pullups are required
during program verification. Port 0 can sink/source eight LS TIL inputs.
pon 1: Port 1 is an 8-bit bidirectional I/O port with internal pullups. Port 1 receives the loworder address bytes during program memory verification. Port 1 can sink/source three LS TTL
inputs, and drive CMOS inputs without external pullups.
pon 2: Port 2 is an 8-bit bidirectional I/O port with internal pullups. Port 2 emits the hlgh-order
address bytes during access to external memory and receives the high-order address bits and
control signals during program verification. Port 2 can sink/source three LS TTL inputs and
drive CMOS inputs without external pullups.
pon 3: Port 3 is an 8-bit bidirectional I/O port with internal pullups. Port 2 can sink/source
three LS TTL inputs and drive CMOS inputs without external pullups. Port 3 also serves the
special functions listed below:
RxO (P3.0): Serial input port
TxO (P3.1): Serial output port
INTO (P3.2): External interrupt 0
INT1 (P3.3): External interrupt 1
TO (P3.4): Timer 0 external input
!!.{P3.5): Timer 1 external input
WR (P3.6): External data memory write strobe
RO (P3.7): External data memory read strobe
pon 4: Port 4 is a 4/8-bit (DIP/LCC) bidirectional I/O port with internal pullups. Port 4 can
sink/source three LS TIL inputs and drive CMOS inputs without external pullups.
pon 5: Port 5 is an 8-bit bidirectional I/O port with internal pullups. Port 5 can sink/source
three LS TIL inputs and drive CMOS inputs without external pullups.
pon 6: Port 6 is a specialized S-bit bidirectional I/O port with internal pullups. This special
port can sink/source three LS TTL inputs and drive CMOS inputs without external pull ups.
Port 6 can be used in a strobed or non-strobed mode of operation. Port 6 works in conjunction with four control pins that serve the functions listed below:
pon 6 Control Lines:
ODS: Output data strobe
IDS: Input data strobe
BFLAG: Bidirectional I/O pin with internal pullups
AFLAG: Bidirectional I/O pin with internal pullups
Reset: A high on this pin, for two machine cycles while the oscillator is running, resets the
device. An internal pull-<:town resistor permits a power-on reset using only a capacitor connected to Vee.
Address Latch Enable: Output pulse for latching the low byte of the address during accesses
to external memory. ALE is activated at a constant rate of 1/6 the oscillator frequency except
during an external data memory access, at which time one ALE is skipped. ALE can
sink/source eight LS TTL inputs and drive CMOS Inputs without an external pullup.
Program Store Enable: The read strobe to external program memory. PSEN is activated twice
each machine cycle during fetches from external program memory. However, when executing
out of external program...!!!Jilllory, two activations of PSEN are skipped during each access to
~al data memory. PSEN is not activated during fetches from internal program memory.
PSEN can sink/source eight LS TTL inputs and drive CMOS inputs without an external pullup.
Instruction Execution Control: When EA is held high, the CPU executes out of internal program
memory, unless the program cou~r exceeds OFFFH. When EA is held low, the CPU executes
out of external program memory. EA must never be allowed to float.
Crystal 1: Input to the inverting amplifier that forms the oscillator. This input receives the external oscillator when an external oscillator is used.
Crystal 2: An output of the inverting amplifier that forms the oscillator. This pin should be
floated when an external oscillator is used.

2-24

Product Specification

Signetics Microprocessor Products

SC80C451/SC83C451

CMOS Single-Chip 8-Bit Microcontroller
PORTS 4 AND 5
Ports 4 and 5 are bidirectional 1/0 ports
with internal pullups. Port 4 is an 8-bit
port (LCC version) or a 4-bit port (01 P
version). Port 4 and port 5 pins with
ones written to them, are pulled high by
the internal pullups, and in that state can
be used as inputs. Port 4 and 5 are addressed at the special function register
addresses shown in Table 1.

ODS - Output data strobe input for port
6. ODS can be programmed to control
the port 6 output drivers and the output
buffer full flag (OBF), or to clear only
the OBF flag bit in the CSR (outputalways mode). ODS is active low for
output driver control. The OBF flag can
be programmed to be cleared on the
negative or positive edge of ODS.
IDS- Input data strobe for port 6. IDS is
used to control the port 6 input latch and
input buffer full flag (IBF) bit in the CSR.
The input data latch can be programmed
to be transparent when IDS is low and
latched on the positive transition of IDS,
or to latch only on the positive transition
of IDS. Correspondingly, the IBF flag is
set on the negative or positive transition
of IDS.

PORT 6
Port 6 is a special 8-bit bidirectional 1/0
port with internal pullups (see Figure 1).
This port can be used as a standard 1/0
port, or in strobed modes of operation in
conjunction with four special control
lines: ODS, IDS, AFLAG, and BFLAG.
Port 6 operating modes are controlled by
the port 6 control status register (CSR).
Port 6 and the CSR are addressed at the
special
function
register
addresses
shown in Table 1. The following four
control pins are used in conjunction with
port 6:

AFLAG - AFLAG is a bidirectional 1/0
pin which can be programmed to be an
output set high or low under program

control, or to output the state of the
output buffer full flag. AFLAG can also
be programmed to be an input which selects whether the contents of the output
buffer, or the contents of the port 6 control status register will be output on port
6. This feature grants complete port 6
status to external devices.

BFLAG - BFLAG is a bidirectional 1/0
pin which can be programmed to be an
output, set high or low under program
control, or to output the state of the input buffer full flag. BFLAG can also be
programmed to input an enable signal for
port 6. When BFLAG is used as an enable input, port 6 output drivers are in
the high-impedance state, and the input
latch does not respond to the IDS strobe
when BFLAG is high. Both features are
enabled when BFLAG is low. This feature facilitates the use of the SC80C451 1
SC83C451
in
bused
multiprocessor
systems.

Table 1. Special Function Register Addresses
REGISTER ADDRESS
Name
Port
Port
Port
Port

4
5
6 data
6 control status

BIT ADDRESS

Symbol

Address

MSB

P4
P5
P6
CSR

CO
C8
08
E8

C7
CF
OF
EF

LSB
C6
CE
DE
EE

AFLAG

Figure 1. Port 6 Block Diagram
February 1989

2-25

C5 C4 C3 C2
CD CC CB CA
DO DC DB DA
ED EC EB EA

C1
C9
09
E9

CO
C8
08
E8

Product Specification

Signetlcs Microprocessor Products

SC80C451/SC83C451

CMOS Single-Chip 8-Bit Microcontroller
CONTROL STATUS REGISTER
The control status register (CSR) establishes the mode of operation for port 6
and indicates the current status of port 6
i/O registers. All control status register
bits can be read and written by the CPU,
except bits 0 and 1, which are read onIy. Reset writes ones to bits 2 through 7,
and writes zeros to bits 0 and 1 (see Table 2).
CSR.O Input Buffar Full Flag (IBF) (Raad
Only) - The I BF bit is set to a logic 1
when port 6 data is loaded into the input
buffer under control of IDS. This can occur on the negative or positive edge of
IDS, as determined by CSR.2. IBF is
cleared when the CPU reads the input
buffer register.
CSR.1 Output Buffar Full Flag (OBF)
(Read Only) - The OBF flag is set to a
logic 1 when the CPU writes to the port
6 output data buffer. OBF is cleared by
the positive or negative edge of ODS, as
determined by CSR.3.
CSR.2 IDS Mode Salect (IDSM) - When
CSR.2 - 0, a low-to-high tranSition on
the ~ pin sets the IBF flag. The port 6

input buffer is loaded on the IDS positive
edge. When CSR.2 - 1, a high-to-low
transition on the ~ pin sets the I BF
flag. When port 6 Input buffer is transparent when jjjS" is low, and latched
when jjjS" is high.
CSR.3 Output Buffer Full Flag Clear
Mode (OBFC) - When CSR.3 - 1, the
positive edge of the ODS input clears
the OBF flag. When CSR.3 - 0, the
negative edge of the ODS input clears
the OBF flag.
CSR.4, CSR.5 AFLAG Mode Sal act (MAO,
MA1) - Bits 4 and 5 select the mode of
operation for the AFLAG pin, as follows:
MA1 MAO

o
o

0
1
0
1

1
1

AFLAG Function
Logic 0 output
Logic 1 output
OBF flag output (CSR.1)
Select (SEL) Input mode

The select (SEL) input mode is used to
determine whether the port 6 data register or the control status register is output
on port 6. When the select feature is
enabled, the AFLAG input controls the

source of port 6 output data. A logic 0
on AFLAG input selects the port 6 data
register, and a logic 1 on AFLAG input
selects the control status register.
CSR.6, CSR.7 BFLAG Moda Salact (MBO,
MB1) - Bits 6 and 7 select the mode
operation as follows:
MB1 MBO

1
1

1
0
1

AFLAG Function
Logic 0 output
Logic 1 output
IBF flag output (CSR.O)
Port enable (PE)

In the port enable mode, IDS and ODS
inputs are disabled when BFLAG input is
high. When the BFLAG input is low, the
port is enabled for i/O.
SPECIAL FUNCTION REGISTER
ADDRESSES
Special function register addresses for
the SC80C451/SC83C451 are identical
to those of the SC80C51, except for the
additional registers listed in Table 1.

Tabla 2. Control Status Ragister (CSR)
Bit 7
MB1

Bit 6

MBO

BFLAG Mode Select
0/0 - Logic 0 output"
0/1 - Logic 1 output"
110 - IBF output
111 - PE Input
(0 - Select)
(1 - Disable 1/0)

Bit 0
MA1

-rI

Bit 2
IDSM

Bit 1
OBF

IBF

Output Buffer
Flag Clear
Mode

Input Data
Strobe Mode

Output Buffer
Full Flag

Input Buffer
Full Flag

0- Output
data buffer
empty

0- Input
data buffer
empty

MAO

AFLAG Mode Select
- Logic 0 output
- Logic 1 output
- OBF output"
- SEL Input
(0 - Data)
(1 - Control/status)

0/0
0/1
110
111

Bit 3
OBFC

Bit 4

0
N~veO Positive
edge of ODS
edge of IDS
1 - Positive 1 - Low level
edge of ODS
of IDS

Bit 0

1 - Output
1 - Input
data buffer full data buffer full

NOTE.
"Output-always mode: MB1 - 0, MA1 - 1, and MAO - O. In this mode, port 6 is always enabled for output. ODS only clears
the OBF flag.

February 1989

2-26

Product Specification

Signetics Microprocessor Products

SC80C451/SC83C451

CMOS Single-Chip 8-Bit Microcontroller
ABSOLUTE MAXIMUM RATINGS1. 2. 3
PARAMETER
Operating temperature under bias
Storage temperature range
Voltage on any other pin to VSS
Power dissipation (based on package heat transfer
limitations, not device power consumption)

RATING

UNIT

o to +70
-40 to +85
65 to +150

°C

-0.5 to + 6.5

°C
V

1.5

NOleS:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied.
2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying voltages greater than the rated maxima.
3.
Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to Vss unless otherwise

noted.
DC ELECTRICAL CHARACTERISTICS TA - O°C to +70°C or TA - -40°C to +85°C, Vcc - 5V ±20%, VSS - OV
Parameter

Symbol
VIL

Input low voltage, except EA

VIL1

Input low voltage to EA

VIH

Input high voltage, except XT AL1, RST

Test Conditions

Limits
Min

Typical 1

Max

Unit
V

-0.5

0.2Vcc-0.1

0. 2Vcc-0.3

0. 2Vcc+· 9

Vcc+0.5

0. 7Vcc

VIH1

Input high voltage, XTAL1, RST

Vcc+0.5

VOL

Output low voltage, ports 1, 2, 3

IOL - 1.6mA2

0.45

VOL1

Output low voltage, port 0, ALE, PSEN

IOL - 3.2mA2

0.45

VOH

Output high voltage, ports 1, 2, 3

IOH - -601JA
IOH - -251JA
IOH - -1 01JA

2.4
0. 75Vcc
0. 9Vcc

V
V
V

VOH1

Output high voltage (port 0 in external bus
mode, ALE, PSEN)3

IOH - -8001JA
IOH - -3001JA
IOH - -801JA

2.4
0. 75Vcc
0. 9Vcc

V
V
V

IlL

Logical 0 Input current, ports 1, 2, 3

VIN - 0.45V

-50

ITL

LogicaI1-to-0 transition current, ports 1, 2, 3

See note 4

-650

VIN - VIL or VIH

±10

III

Input leakage current, port 0

Icc

Power supply current:
Active mode @ 12MHz5
Idle mode @ 12MHz5
Power down mode

RRST

Internal reset pulldown resistor

CIO

Pin capacltance7 - DIP package
- PLCC package

IJA
IJA
IJA

See note 6
11.5
1.3
3
50

25
4
50

rnA
rnA

IJA

300

k.Q

15
10

pF
pF

NOleS:
1. Typical ratings are based on a limited number of samples taken from early manufacturing lots and are not guaranteed. The values listed are
at room temperature, 5V.
'

Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and ports 1 and 3. The noise is due
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1·to-0 transitions during bus operations. In

3.
4.

the worst cases (capacitive loading> 100pF), the noise pulse on the ALE pin may exceed O.SV. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input.
Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9VCC specification when the
address bits are stabilizing.

Pins of ports 1, 2, and 3 source a transition current when they are being externally driven from 1 to O. The transition current reaches its
maximum value when VIN is approximately 2V.
leeMAX at other frequencies is given by:

6.
7.

Active mode: ICCMAX - 0,94 X FREQ + 13.71
Idle mode:
ICCMAX - 0.14 X FREQ + 2.31
where FREQ is the external oscillator frequency in MHz. ICCMAX is given in rnA. See Figure 13.
See Figures 14 through 17 for ICC test conditions.
CIO applies to Ports 1,2,3,4,5,6, AFLAG, BFLAG, XTAL1, XTAL2.

February 1989

2-27

Product Specification

Signetics Microprocessor Products

SC80C451/SC83C451

CMOS Single-Chip 8-Bit Microcontroller

AC ELECTRICAL CHARACTERISTICS TA - O°C to +70°C or TA - -40°C to +85°C, VCC - 5V ±20%, Vss - OV1, 2
12MHz CLOCK
PARAMETER

SYMBOL FIGURE

Min

Max

VARIABLE CLOCK
Min

Max

0.5
3.5
3.5

12
12
16

UNIT

Program Memory
l/tCLCL

Oscillator frequency:
SC80C451/SC83C451
SC80C451/SC83C451
SC80C451/SC83C451

Speed Versions

B
C

MHz
MHz
MHz

tLHLL

ALE pulse width

127

2tCLCL -40

tAVLL

Address valid to ALE low

tCLCL -55

tLLAX

Address hold after ALE low

tCLCL -35

tLLlV

ALE low to valid instruction in

tLLPL

ALE low to PSEN low

tpLPH

PSEN pulse width

tpLiV

PSEN low to valid instruction in

tpXIX

Input instruction hold after PSEN

tpXIZ

Input instruction float after PSEN

tAVIV

Address to valid instruction in

PSEN low to address float

tpLAZ

234
43

ns
4tCLCL -100

tCLCL -40

205

3tCLCL -45
145

3tCLCL-l05

tCLCL-25

312

5tcLCL -105

Data Memory
tRLRH

3,4

RD pulse width

400

6tCLCL -100

tWLWH

3, 4

WR pulse width

400

6tCLCL -100

tRLDV

3,4

RD low to valid data in

tRHDX

3, 4

Data hold after R 0

tRHDZ

3, 4

Data float after RD

2tCLCL -70

tLLDV

3, 4

ALE low to valid data in

517

8tCLCL -150

tAvDV

3, 4

Address to valid data in

tLLWL

3,4

ALE low to RD or WR low

200

tAVWL

3, 4

Address valid to WR low or RD low

203

4tCLCL -130

tOVWX

3, 4

Data valid to WR transition

tCLCL-60

tWHOX

3, 4

Data hold after WR

tCLCL-50

tRLAZ

3, 4

RD low to address float

tWHLH

3, 4

RD or WR high to ALE high

252

ns
5tCLCL -165

585
300

3tCLCL -50

0
43

123

tCLCL-40

ns
ns

9tCLCL -165

3tCLCL+50

ns
ns

tCLCL+40

Shift Register
tXLXL

Serial port clock cycle time

1.0

12tCLCL

J.1S

tOVXH

Output data setup to clock rising edge

700

1OtCLCL -133

tXHOX

Output data hold after clock rising edge

2tCLCL -117

tXHDX

Input data hold after clock rising edge

tXHDV

Clock rising edge to input data valid

700

NOTES.
1. Parameters are valid over operating temperature range unless otherwise specified.

2. Load capacitance for port 0, ALE, and PSEN - 100pF, load capacitance for all other outputs - 80pF.

February 1989

2-28

1OtCLCL -133

Product Specification

Signetics Microprocessor Products

SC80C451/SC83C451

CMOS Single-Chip 8-Bit Microcontroller
AC ELECTRICAL CHARACTERISTICS (Continued)
SYMBOL FIGURE

12MHz CLOCK

PARAMETER

Port 6 Input (input rise and fall times

Min

Max

VARIABLE CLOCK
Min

Max

UNIT

=5ns)

tFLFH

PE width

270

3tCLCL +20

tlLlH

IDS width

270

3tCLCL +20

tDVIH

Data setup to IDS high or PE high

tlHDX

Data hold after IDS high or PE high

tlVFV

IDS to BFLAG (IBF) delay

130

Port 6 Output
tOLOH

ODS width

tFVDV

SEL to data out delay

tOLDV

ODS to data out delay

tOHDZ

ODS to data float delay

270

3tCLCL+20
85

tOVFV

ODS to AFLAG (OBF) delay

100

tFLDV

PE to data out delay

120

tOHFH

ODS high to AFLAG (SEL) delay

100

External Clock
tCHCX

High time

tCLCX

Low time

tCLCH

Rise time

tCHCL

Fall time

EXPLANATION OF THE AC SYMBOLS
Each timing symbol has five characters. The first character is
always 't' (- time). The other characters, depending on their
positions, indicate the name of a signal or the logical status of
that signal. The designations are:
A - Address
C - Clock
0- Input data
F - PE, SEL, or IBF
H - Logic level high
I - Instruction (program memory contents), or input data strobe
L - Logic level low, or ALE
Output data strobe
P- PSEN
Q - Output data
R - RD signal
t - Time
V - Valid
W - WR signal
X - No longer a valid logic level
Z - Float

Examples: tAVLL - Time for address valid to ALE low.
tLLPL - Time for ALE low to PSEN 10w.L - Logic I

February 1989

2-29

Product Specification

Signetics Microprocessor Products

SC80C451/SC83C451

CMOS Single-Chip 8-Bit Microcontroller

ALE

PORTO _ _ _ _/

PORT 2 _ _ _ _J

A8-A15

Figure 2. External Program Memory Read Cycle

ALE

10----- 'lLDV ----001
-~~----'RlRH------~

'RHDX
PORTO

PORT 2

AO-A? FROM PCl

---

Io----------'AVDV~----~
P2.0-P2.? OR AS-A15 FROM DPH

Figure 3. External Data Memory Read Cycle

February 1989

2-30

A8-A15 FROM PCH

Product Specification

Signetics Microprocessor Products

SC80C451/SC83C451

CMOS Single-Chip 8-Bit Microcontroller

ALE

....---WLWH----01

tOVWX

DATA OUT

PORTO

PORT 2

A8-A15 FROM PCH

P2.0-P2.7 OR A8-A15 FROM DPH

---'

Figure 4. External Data Memory Write Cycle

INSTRUCTION

ALE

tOVXH

OUTPUT DATA

f
WRITE TO SBUF
I

INPUT DATA I

t XHOX

' ' - _ - J "--_-' ' - _ - J ' - - _ . . J ' - _ - J ' - - _ - ' ' - _ - J '--_....J

_ _ _ _ _ _ _ _ _ _ _ _,~--'~---I'~~··?

f
CLEAR RI

SET RI

Figure 5. Shift Register Mode Timing

February 1989

2-31

Product Specification

Signetics Microprocessor Products

SC80C451/SC83C451

CMOS Single-Chip 8-Bit Microcontroller

OBF (AFLAG)

1----0
~

PE(BFlAG)

-' I.-

k::

~ tOVFV

tOVFV

...., t<-

~
t OLOH

~ Ir-

-: £.

I--

tOLDV

tOHDZ

PORT 6

10--

tFLDV -

Figure 6. Port 6 Output

...., ~

I------

I----PORT 6

:; I'-

SEL (AFLAG)

DATA

t FvDV

"to--

tOHFH

~ I'-

t FVDV
DATA

CSR

Figure 7. Port 6 Select Mode

I
PE (BFLAG)

tFLFH

tlllH

7 I't Dv1H

tlHDX

PORTS

Figure 8. Port 6 Input

"'~:) ~~~~~~~~~~~~~~~-t!--.Lj.-:I-VF-v---------i+_IV_FV

_ _ _ __

Figure 9. ISF Flag Output

February 1989

2-32

Signetics Microprocessor Products

Product Specification

CMOS Single-Chip 8-Bit Microcontroller

SC80C451/SC83C451

0.45V

~----------tCLCL----------~

Figure 10. External Clock Drive

Vcc-o.s

.45V

O.2Vcc+O.9

Timing
Reference
Points

_,-O.;.;..;;.2V.;,.C;,.;c.;..-,.;;.O;,.;., _ _.....

AC inputs during testing are driven at Vcc-o.s
for a logic "1" and O.4SV for a logic "0".
Timing measurements are made at VIH min for
a logic "1" and V IL max for a logic "0".

For timing purposes, a port is no longer floating
when a 100mV change from load voltage occurs,
and begins to float when a 100mV change from
the loaded VOHIVOL level occurs.IOH/lOL~± 20mA.

Figure 11. AC Testing Input/Output

Figure 12. Float Waveform

MAX
ACTIVE MODE

()

!:!
10

5 ~---+~~+----4----~MAX
IDLE MODE

L:::d=:::::±==:t:==:J

TYP(1)
IDLE MODE

4MHz 8MHz 12MHz 16MHz
FREQ AT XTAL1

Figure 13. Icc vs. FREQ
Valid only within frequency specifications of the device under test
TYP(1) - See DC Electrical Characteristics

February 1989

2-33

Product Specification

Signetics Microprocessor Products

SC80C451/SC83C451

CMOS Single-Chip 8-Bit Microcontroller

Vee

RST
RST

CLOCK
SIGNAL

(NC)

XTAL2
XTAL1
Vss

CLOCK

(NC)

SIGNAL

Figure 14. Icc Test Condition, Active Mode
All other pins are disconnected

XTAL2
XTAL1
Vss

Figure 15. Icc Test Condition, Idle Mode
All other pins are disconnected

0.45V

~--------tCLCL----------~

Figure 16. Clock Signal Waveform for Icc Tests in Active and Idle Modes
tCLCH
tCHCL 5ns

RST

(NC)

XTAL2
XTAL1
Vss

Vee

Figure 17. Icc Test Conditions, Power Down Mode
All other pins are disconnected. VCC = 2V to 5.5V

February 1989

Vee

2-34

Signetics

SC87C451
CMOS Single-Chip 8-Bit EPROM
Microcontroller
Product Specification

Microprocessor Division
DESCRIPTION
The Signetics SC87C451 is an I/O expanded, single-chip microcontroller fabricated with Signetics high-density CMOS
technology. Signetics epitaxial substrate
minimizes latch-up sensitivity.
The SC87C451 has 4K of EPROM onchip as program memory and is otherwise identical to the SC83C451.
The SC87C451 is a functional extension
of the SC87C51 microcontroller with
three additional I/O ports and four I/O
control lines. The LCC version has a total
of 68 pins. Four control lines associated
with port 6 facilitate high speed asynchronous I/O functions.
The SC87C451 includes a 4K X 8
EPROM, a 128 X 8 RAM, 58 (LCC) or 54
(DIP) I/O lines, two 16-blt timer/counters, a five source, two priority level,
nested interrupt structure, a serial I/O
port for either a full duplex UART, I/O
expansion, or multiprocessor communications, and an on-chip oscillator and clock
circuits.

PIN CONFIGURATIONS

FEATURES
• User programmable microcontroller
• SC80C51 based architecture
• 681'in LCC and 641'in DIP
packages:
- Seven 8-bit I/O ports (LCC
version)
- Six 6-bit ports and one 4-bit
port (DIP version)
• Port 6 features:
- 8 data pins
- 4 control pins
- Direct MPU bus interface
- Parallel printer interface
• On the microcontroller
- 4KX 8 EPROM
- 128X 8 RAM
- Two 16-bit counter/timers
- Two external interrupts
• External memory addressing
capability
- 64K ROM and 64K RAM
• Low power consumption:
- Normal operation: less than
24mA at 5V, 12MHz
- Idle mode
- Power-down mode

LOGIC SYMBOL

The SC87C451 has two software selectable modes of reduced activity for further power reduction: Idle mode and
power-down mode. Idle mode freezes
the CPU while allowing the RAM, timers,
serial port, and interrupt system to continue functioning. Power-down mode
freezes the OSCillator, causing all other
chip functions to be inoperative while
maintaining the RAM contents.

~ ~ROG

EA/vPP
P2.0/A8 ~
P2.1/A9 3

~ PSEN

S2 PS.7

P2.2/Al0
P2.3/All ,l
P2.4/A12 ~
P2.5/A13 ~
P2.6/A14.!
P2.7/A15
PO.7/AD7

~
~
~

il2

P6.S
PS.5
P6.4
PS.3
PS.2
PS.l
P6.0

PO.S/ADS~

~ AFLAG

PO.5/AD5~

~ ~AG

PO.4/AD4~

~ ~

PO.3/AD3~

~ ODS

PO.2/AD2~

PO.l/ADl

50 Vss

PO.O/ADO~
VCC~

~
DIP

XTALl

~ XTAL2
~ P5.7

P4.3~

P4.2~

~ P5.5

P4.1 ~
~
P4.0~
~
Pl.0~
~
Pl.l ~
~
Pl.2~
~
Pl.3~
~
Pl.4~
~
Pl.5 ~
~
Pl.S ~
~
Pl.7~
~
RST ~
~
P3.0/RxD ~,-_ _~1=_33_

ps.s
P5.4
P5.3
P5.2
P5.1
P5.0_
P3.7/~
P3.S/WR
P3.5/Tl
P3.4/~
P3.3~
P3.2/INTO
P3.1 /TxD

TOP VIEW
INDEX

CORNE1~9
:
61 so
LCC
26

44
27
43
TOP VIEW

See next page for LCC pin functions

February 1989

2-35

ECN 94521

Signetlcs Microprocessor Products

Product Specification

CMOS Single-Chip 8-Bit EPROM Microcontroller

SC87C451

ORDERING INFORMATION
PART NUMBER SELECTION

SC87C451 cC!:!:',!:!

Pan No.

OPERATING
TEMPERATURE RANGE A - -40°C to +85 0 C
C - oOC to +70OC
SPEEDB - 0.5 to 12MHz
C - 3.5 to 12MHz
G - 3.5 to 16MHz

~64

=
pin DIP
=64
68 pin lCC

'---PACKAGE
A - Plastic LCC
I - Ceramic DIP
L - Ceramic LCC
N - Plastic DIP

SC87C451 CCI64
SC87C451CGI64
SC87C451CBI64
SC87C451 CCl68
SC87C451 CGl68
SC87C451CBL68
SC87C451 CCN64
SC87C451 CGN64
SC87C451CBN64
SC87C451 CCA68
SC87C451CGA68
SC87C451CBA68

Speed
Temperature and Package
3.5 to 12MHz o to +70 "C ceramic 01 P
3.5 to 16MHz o to +70·Cceramic DIp·
0.5 to 12MHz o to +70"Cceramic DIP
3.5 to 12MHz o to +70·Cceramic LCC
3.5 to 16MHz o to +70"Cceramic LCC·
0.5 to 12MHz o to +70·Cceramic LCC
3.5 to 12MHz o to +70"Cplastic DIP
3.5 to 16MHz o to +70 "C plastic 01 p.
0.5 to 12MHz o to +70"C plastic DiP
3.5 to 12MHz o to +70"C plastic LCC
3.5 to 16MHz o to +70"C plastic LCC·
0.5 to 12MHz o to +70"C plastic LCC

'PRELIMINARY SPECIFICATION

lCC PIN FUNCTIONS
INDEX

~"n
10

LCC

44
27
43
TOP VIEW

Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23

February 1989

Function
EAIVPP
P2.0/A8
P2.1/A9
P2.2/Al0
P2.3/All
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
PO.7IAD7
PO.6/AD6
PO.5/AD5
PO.4/AD4
PO.3/AD3
PO.2/AD2
PO.l/ADl
PO.O/ADO
Vee

P4.7
P4.6
P4.5
P4.4
P4.3

Pin
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46

Function

P4.2
P4.1
P4.0
Pl.0
Pl.l
Pl.2
Pl.3
Pl.4
Pl.5
Pl.6
Pl.7
RST
P3.0/RxD
P3.1/TxD
P3.2/iliiTli
P3.3/iN'i'i
P3.4/TO
P3.5/Tl
P3.6/ioWi
P3.7/RD
P5.0
P5.1
P5.2

2-36

Pin
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68

Function

P5.3
P5.4
P5.5
P5.6
P5.7
XTAL2
XTALl
Vss

ODS

BFLAG
AFLAG
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6

~~'~N
ALE/PROO

.,.,
CD

r
0
0

-<"
I»

"i>c

'"
'"
00

PO.D-PO.7

P2.CI-P2.7

P4.o-P4.7

P5.o-P5.7

---------1

(

(f)

<5.

n·

s::

CJ)
CJ)
::::l

....0.

a
c

(f)

-a
CD

()

o·~

::J

Product Specification

Signetics Microprocessor Products

CMOS Single-Chip 8-Bit EPROM Microcontroller

SC87C451

PIN DESCRIPTION
PIN NO.
TYPE
NAME AND FUNCTION
DIP LCC
50
54
I
Ground: OV reference.
Vss
Power Supply: This is the power supply voltage for normal, idle, and power-down operation.
I
18
18
Vee
PO.0-PO.7 17-10 17-10 I/O Port 0: Port 0 is an 8-bit open-drain, bidirectional I/O port. Port 0 is also the multiplexed data
and low- 100pF), the noise pulse on the ALE pin may exceed O.SV. In such cases, it may be desirable to qualify

3.
4.

ALE with a Schmitt Trigger, or use an address latch with a Schmit! Trigger STROBE input.
Capacitive loading on ports 0 and 2 may cause the YOH on ALE and PSEN to momentarily fall below the 0.9YCC specification when the
address bits are stabilizing.
Pins of ports 1, 2, and 3 source a transition current when they are being externally driven from 1 to-'O. The transition current reaches its
maximum value when VIN is approximately 2V.

ICCMAX at other frequencies is given by:
Active mode: ICC MAX - 0.94 X FREQ + 13.71
Idle mode:
ICCMAX - 0.14 X FREQ + 2.31

See Figures 14 through 17 for ICC test conditions.
CIO applies to Ports 1, 2, 3, 4, 5, 6, AFLAG, BFLAG, XTAL1, XTAL2.

where FREQ is the external oscillator frequency in MHz. ICCMAX is given in rnA. See Figure 13.

February 1989

2-41

Product Specification

Signetics Microprocessor Products

SC87C451

CMOS Single-Chip 8-Bit EPROM Microcontroller

AC ELECTRICAL CHARACTERISTICS TA - DoC to +70°C or TA - -40°C to +85°C, VCC - 5V ±10%, Vss - OV1, 2
12MHz CLOCK
PARAMETER

SYMBOL FIGURE

Min

Max

VARIABLE CLOCK
Min

Max

0.5
3.5
3.5

12
12
16

UNIT

Program Memory
Oscillator frequency: Speed Versions
8
SC87C451
SC87C451
C
SC87C451
G

l/tCLCL

tLHLL

ALE pulse width

127

2tCLCL-40

tAVLL

Address valid to ALE low

tCLCL-55

tLLAX

Address hold after ALE low

tLLlV

ALE low to valid instruction in

ALE low to PSEN low

tLLPL
tpLPH

PSEN pulse width

tpLiV

PSEN low to valid instruction in

tpXIX

Input instruction hold after PSEN

tpXIZ

Input instruction float after PSEN

tAVIV

Address to valid instruction in

tpLAZ

PSEN low to address float

tCLcL -35
234

43
205

MHz
MHz
MHz

4tCLCL -100

tCLCL-40

3tCLCL -45

ns
3tCLCL -105

tCLCL-25

312

5tCLCL -105

145
0

Data Memory
tRLRH

3, 4

RD pulse width

400
400

6tCLCL -100

tWLWH

3, 4

WR pulse width

tRLDV

3, 4

RD low to valid data in

tRHDX

3, 4

Data hold after RD

tRHDZ

3, 4

Data float after RD

tLLDV

3, 4

ALE low to valid data in

tAvDV

3, 4

Address to valid data in

tLLWL

3, 4

ALE low to RD or WR low

tAVWL

3,4

Address valid to WR low or RD low

203

4tCLCL-130

tOVWX

3,4

Data valid to WR transition

tCLCL-60

tWHOX

3, 4

Data hold after WR

tCLCL -50

tRLAZ

3, 4

RD low to address float

tWHLH

3,4

RD or WR high to ALE high

6tCLCL-100
252

5tCLCL-165

2tCLCL-70

517

8tCLCL-150

585

9tCLCL-165

0
97

200

300

3tCLCL-50

0
43

123

tCLCL-40

3tCLCL+50

ns
0

tCLCL+40

Shift Register
tXLXL

Serial port clock cycle time

1.0

12tCLCL

!IS

1OtCLCL -133

ns
ns

tOVXH

Output data setup to clock rising edge

700

tXHOX

Output data hold after clock rising edge

2tCLCL-117

tXHDX

Input data hold after clock rising edge

tXHDV

Clock rising edge to input data valid

700

NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.

2. Load capacitance for port 0, ALE, and PSEN - 100pF. load capacitance for all other outputs - 80pF.

February 1989

2-42

ns
10tCLCL-133

Product Specification

Signetics Microprocessor Products

SC87C451

CMOS Single-Chip 8-Bit EPROM Microcontroller
AC ELECTRICAL CHARACTERISTICS (Continued)
12MHz CLOCK
PARAMETER

SYMBOL FIGURE

Port 6 Input (input rise and fall times

Min

Max

VARIABLE CLOCK
Min

Max

UNIT

= 5ns)
ns

tFLFH

PE width

270

3tCLCL+20

tlLlH

IDS width

270

3tCLCL +20

tDVIH

Data setup to IDS high or PE high

tlHDX

Data hold after IDS high or PE high

tlVFV

IDS to BFLAG (lBF) delay

130

Port 6 Output
270

tOLOH

ODS width

tFVDV

SEL to data out delay

tOLDV

ODS to data out delay

tOHDZ

ODS to data float delay

tOVFV

ODS to AFLAG (OBF) delay

100

tFLDV

PE to data out delay

120

tOHFH

ODS high to AFLAG (SEL) delay

3tCLCL +20

100

External Clock
tCHCX

High time

tCLCX

Low time

tCLCH

Rise time

tCHCL

Fall time

EXPLANATION OF THE AC SYMBOLS
Each timing symbol has five characters. The first character is
always 't' (- time). The other characters, depending on their
positions, indicate the name of a signal or the logical status of
that signal. The designations are:
A - Address
C - Clock
o - I nput data
F - PE, SEL, or IBF
H - LogiC level high
I - I nstruction (program memory contents), or input data strobe
L - Logic level low, or ALE
Output data strobe
P- PSEN
Q - Output data
R - RD signal
t - Time
V - Valid
W - WR signal
X - No longer a valid logic level
Z - Float

Examples: tAVLL - Time for address valid to ALE low.
tLLPL - Time for ALE low to PSEN 10w.L - Logic I

February 1989

2-43

Product Specification

Signetics Microprocessor Products

SC87C451

CMOS Single-Chip 8-Bit EPROM Microcontroller

ALE

~ _ _ _J

PORTO _ _ _J

PORT 2

_ _ _ _J

Figure 2. External Program Memory Read Cycle

ALE

---M.------IRlRH------~

AO-A7 FROM

PORTO

PCl

1o----IAVWl
Io-------IAVDV------~

PORT 2

----'

P2.0-P2.7 OR AS-A 15 FROM DPH

Figure 3. External Data Memory Read Cycle

February 1989

2-44

AS-A15 FROM PCH

Product Specification

Signetics Microprocessor Products

SC87C451

CMOS Single-Chip 8-Bit EPROM Microcontroller

ALE

/
I--

I---

t AVLL

PORT 0

~ . ",,,,,.A~

nDI

/
tOVWX

.....

t wHoX

DATA OUT

AD-A7 FROM PCL

INSTR I N

tAVWL

PORT 2

t WLWH

t LLWL

..-tLLAX .....

tWHLH

A8-A15 FROM PCH

P2.0-P2.7 OR A8-A15 FROM DPH

Figure 4. External Data Memory Write Cycle

INSTRUCTION

ALE

tOVXH H I ' X H Q X

OUTPUT DATA

\ ...._ - - ' '--_...J \.._--'

I - - _ . . J ...._ - - '

'--_..J ...._----1 \..o-_..J

WRITE TO SBUF
I INPUT DATA I __________- J

CLEAR RI

SET RI

Figure 5. Shift Register Mode Timing

February 1989

2-45

Product Specification

Signetics Microprocessor Products

SC87C451

CMOS Single-Chip 8-Bit EPROM Microcontroller

OBF (AFLAG)

I----t
..J

PE(BFLAG)

to---

tOVFV

"7 IL

.., IL

t OLOH

..::~

I--t

tOLDV

tOHDZ

PORTe

I--

tFLDV

---

Figure 6. Port 6 Output

"7 l£-

I-SEL (AFLAG)

I---

I-----

"7 l£t FVDV

eSR

DATA

PORTe

t FVDV

tOHFH

DATA

Figure 7. Port 6 Select Mode

I
PE (BFLAG)

tFLFH

-:: IL

tlLlH

.., F-

t DV1H

tlHDX

PORTe

Figure 8. Port 6 Input

IBF (BFLAG)

IDS

;,~

Figure 9. ISF Flag Output

February 1989

2-46

iJ_
1VFV

Signetics Microprocessor Products

Product Specification

CMOS Single-Chip 8-Bit EPROM Microcontroller

SC87C451

0.45V

~---------tCLCL--------~

Figure 10. External Clock Drive

Vcc-O.5
O.45V

O.2Vcc+O.9

Timing
Reference
Points

_...O;;,;.,:;;2V.:.,c,;;.c,;;.-..,;O.:...,:......___

AC inputs during testing are driven at Vcc-0.5
for a logic "1" and 0.45V for a logic "0".
Timing measurements are made at VIH min for
a logic" 1" and V IL max for a logic "0".

For timing purposes, a port is no longer floating
when a 100mV change from load voltage occurs,
and begins to float when a 100mV change from
the loaded VOHIVOL level occurs.IOH/lOL~± 20mA.

Figure 11. AC Testing Input/Output
EPROM CHARACTERISTICS
The SC87C451 is programmed by using a
modified Quick-Pulse Programming" algorithm. It differs from older methods in
the value used for Vpp (programming
supply voltage) and in the width and
number of the ALE/PROG pulses.
The SC87C451 contains two signature
bytes that can be read and used by an
EPROM programming system to identify
the device. The signature bytes identify
the device as an SC87C451 manufactured by Signetics Corporation.
Table 3 shows the logic levels for reading the signature byte, and for programming the program memory, the encryption table, and the lock bits. The circuit
configuration and waveforms for quickpulse programming are shown in Figures
18 and 19. Figure 20 shows the circuit
configuration for normal program memory
verification.
QUICK-PULSE PROGRAMMING
The setup for microcontroller quick-pulse
programming is shown in Figure 18. Note
that the SC87C451 is running with a 4 to
6MHz oscillator. The reason the oscillator needs to be (unning is that the device is executing internal address and
program data transfers.
The address of the EPROM location to
be programmed is applied to ports 1 and
2, as shown in Figure 18. The code byte
to be programmed into that location is
February 1989

Figure 12. Float Waveform

applied to port O. RST, PSEN and pins
of ports 2 and 3 specified in Table 2 are
held at the "Program Code Data" levels
indicated in Table 3. The ALE/PROG is
pulsed low 25 times as shown in Figure
19.

shown in Figure 20. The other pins are
held at the "Verify Code Data" levels indicated in Table 3. The contents of the
address location will be emitted on port
O. External pull-ups are required on port
o for this operation.

To program the encryption table, repeat
the 25 pulse programming sequence for
addresses 0 through 1 FH, using the
"Pgm Encryption Table" levels. Do not
forget that after the encryption table is
programmed, verification cycles will produce only encrypted data.

If the encryption table has been programmed, the data presented at port 0
will be the exclusive NOR of the program byte with one of the encryption
bytes. The user will have to know the
encryption table contents in order to correctly decode the verification data. The
encryption table itself cannot be read
out.

To program the lock bits, repeat the 25
pulse programming sequence using the
"Pgm Lock Bit" levels. After one lock bit
is programmed, further programming of
the code memory and encryption table is
disabled. However, the other lock bit
can still be programmed.
Note that the EAIVpp pin must not be allowed to go above the maximum specified Vpp level for any amount of time.
Even a narrow glitch above that voltage
can cause permanent damage to the device. The Vpp source should be well regulated and free of glitches and overshoot.
Program Verification
If lock bit 2 has not been programmed,
the on-chip program memory can be
read out for program verification. The
address of the program memory locations
to be read is applied to ports 1 and 2 as

2-47

Reading the Signature Bytes
The signature bytes are read by the
same procedure as a normal verification
of locations 030H and 031 H, except that
P3.6 and P3.7 need to be pulled to a
logic low. The values are:
(030H) - 15H indicates manufactured by
Signetics
(031 H) - 90H indicates SC87C451
ProgramlVerify Algorithms
Any algorithm in agreement with the
conditions listed in Table 3, and which
satisfies the timing specifications, is suitable.

"Trademark phrase of Intel Corp.

Product Specification

Signetics Microprocessor Products

SC87C451

CMOS Single-Chip 8-Bit EPROM Microcontroller
E rasure Characteristics
Erasure of the EPROM begins to occur
when the chip is exposed to light with
wa velengths shorter than approximately
4,000 angstroms. Since sunlight and fluorescent lighting have wavelengths in
this range, exposure to these light
sources over an extended time (about 1
week in sunlight, or 3 years in room level
fluorescent lighting) could cause inadvertent erasure. For this and secondary effects, it is recommended that an
opaque label be placed over the window. For elevated temperature or solvent environment, use Kapton tape
Fluorglas part number 2345-5 or equivalent.

The recommended erasure procedure is
exposure to ultraviolet light (at 2537
angstroms) to an integrated dose of at
least
15W-sec/cm2.
Exposing
the
EPROM to an ultraviolet lamp of
12,OOOIlW/cm2 rating for 20 to 39 minutes, at a distance of about 1 inch,
should be sufficient.
Erasure leaves the array in an all 1s
state.

Table 3, EPROM Programming Modes
RST

PSEN

ALE/PROG

EANpp

P2.7

P2.B

P3.7

P3.B

Read signature

Program code data

Vpp

Verify code data

Pgm encryption table

Vpp

Pgm lock bit 1

Vpp

Pgm lock bit 2

Vpp

MODE

NOTES:
1. '0' - valid low for that pin, '1" - valid high for that pin.
2, Vpp = 12.75V ±O.25V.
3. Vee - 5V ±10% during programming and verification.
'ALE/i5"R1X3 receives 25 programming pulses while Vpp Is held at 12.75V. Each programming pulse is low for 100/lS (±10/lS) and
high for a minimum of 10/lS.

MAX
ACTIVE MODE

~
10

f---+r---,f---+---:f MAX

IDLE MODE

L:::'d:=::±==t:=:J

TYP(1)
IDLE MODE

4MHz 8MHz 12MHz 16MHz
FREQ AT XTAL 1

Figure 13. ICC VB. FREQ
Valid only within frequency specifications of the device under test
TYP(1) - See DC Electrical Characteristics
February 1989

2-48

Signetics Microprocessor Products

Product Specification

SC87C451

CMOS Single-Chip 8-Bit EPROM Microcontroller

Vee

RST
RST

CLOCK
SIGNAL

(NC)

XTAL2
XTAL1

CLOCK

(NC)

SIGNAL

Voo

Figure 14. Icc Test Condition, Active Mode
All other pins are disconnected

XTAL2
XTAL1

Figure 15. Icc Test Condition, Idle Mode
All other pins are disconnected

0.45V

1-----tcLcL------"I

Figure 16. Clock Signal Waveform for IcC Tests in Active and Idle Modes
tCLCH
tCHCL
5ns

Vee

RST

(NC)

XTAL2
XTAL1

Vee

Voo

Figure 17. Icc Test Conditions, Power Down Mode
All other pins are disconnected. VCC = 2V to 5.SV

February 1989

Vee

Voo

2-49

Signetics Microprocessor Products

Product Specification

CMOS Single-Chip 8-Bit EPROM Microcontroller

SC87C451

+5V

Vee
P1

A 0-A7

4-SMHz

RST

EAlVpp

P3.S

ALE/PRciG

P3.7

PGM DATA

SC87C451

XTAL2

25 100us PULSES
TO GROUND

PsEN
P2.7

=*=~

P2.S
A

=i=

+12.75V

P2.0
-P2.3 •

XTAL1

A8-A11

.-- Vss
L-

Figure 18. Programming Configuration

J,....--------:25 PULSES----------01

ALE/PROG:

-:LJLJlJUl.:::.------------

i-----

L-...,--J

1'-

ALE/PROG:

10/iSMIN

----o~I_______

-01 r---

__In

Figure 19. PROG Waveform

February 1989

2-50

100/iS±10-----1

n. . __

Product Specification

Signetics Microprocessor Products

SC87C451

CMOS Single-Chip 8-Bit EPROM Microcontroller

+5V

Vee
PO I--""'-,{ PGM DATA

AO-A7 -----,{I P1
_ _ _-IjRST

EAlVpp ......- - -

----IjP3.6
----IjP3.7

ALE/PROO ......- - SC87C461

PSEN i t - - - - - 0
P2.7 i t - - - - - 0

...--......---1 XTAL2

(ENABLE)

P2.6 10---- 0
P2.0 1/'---- AS-A11
-P2.31\r----

-+-I XTAL1

L - _......

Voo

Figure 20. Programming Verification
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS TA - 21°C to +27°C, VCC - 5V±10%, VSS - OV (see Figure 21)
SYMBOL

PARAMETER

Vpp

Programming supply voltage

Ipp

Programming supply current

1/tCLCL

Oscillator frequency

MIN

MAX

12.5

13.0

rnA

MHz

tAVGL

Address setup to PROG low

tGHAX

Address hold after PROG

48tcLCL

tDVGL

Data setup to PROG low

48tCLCL

tGHDX

Data hold after PROG

48tCLCL

tEHsH

P2.7 (ENABLE) high to Vpp

48tCLCL

tSHGL

Vpp setup to PROG low

tGHSL

Vpp hold after PROG

tGLGH

PROG width

tAVQV

Address to data valid

tELQV

ENABLE low to data valid

tEHQZ

Data float after ENABLE

tGHGL

PROG high to PROG low

February 1989

UNIT

!IS
110

48tCLCL
48tCLCL

2-51

. 48tCLCL
~

Signetics Microprocessor Products

Product Specification

CMOS Single-Chip 8-Bit EPROM Microcontroller

PROGRAMMING'
P1.0-P1.7
P2.0-P2.3

VERIFICATION'

ADDRESS

io-

tAVOV

DATA IN

PORTO
t DVGL

1-0

t AVGL

j.o---o

ALE/PROG
tGLGH-o
t SHGL

I-

DATA OUT
-0

25 PULSES

D=-:

I-

tGHDX

~ tGHAX

10-

t GHGL

1--0

t GHSL

'\.
/

ADDRESS

-0

EANpp

SC87C451

LOGIC 1

LOGIC 0

- - -- - - - - - - - - - - -

- - - - --

t EHSH
P2.7
EANBlE

tELOr

---./
'FOR PROGRAMMING VERIFICATION SEE FIGURE 18.
FOR VERIFICATION CONDITIONS SEE FIGURE 20.

Figure 21. EPROM Programming and Verification

February 1989

2-52

I-

t EHOZ

User's Guide

Signetics Microprocessor Products

8XC552

Section 2 - 8051 Derivatives
8XC552 OVERVIEW

DATA MEMORY

The 83C552 is a stand-alone high-performance microcontroller designed for use in real-time applications such
as instrumentation, industrial control, and automotive
control applications such as engine management and
transmission control. The device provides, in addition to
the 80C51 standard functions, a number of dedicated
hardware functions for these applications.
The 83C552 single-chip 8-bit microcontroller is manufactured in an advanced CMOS process and is a derivative of the 80C51 microcontroller family. The 83C552
uses the powerful instruction set of the 80C51. Additional
special function registers are incorporated to control the
on-chip peripherals. Three versions of the derivative exist although the generic term "83C552" is used to refer
to family members:
83C552: 8K bytes mask-programmable ROM, 256 bytes
RAM
87C552: 8K bytes EPROM, 256 bytes RAM
80C552: ROMless version of the 83C552
The 83C552 contains a non-volatile 8K x 8 read-only
program memory, a volatile 256 x 8 read/write data
memory, six 8-bit 110 ports, two 16-bit timer/event
counters (identical to the timers of the 80C51), an additional 16-b~t timer coupled to capture and compare
latches, a fifteen-source, two-priority-level, nested interrupt structure, an 8-input ADC, a dual DAC pulse width
modulated interface, two serial interfaces (UART and
I2C bus), a 'watchdog' timer and on-chip oscillator and
timing circuits. For systems that require extra capability,
the 83C552 can be expanded using standard TIL compatible memories and logic.
The 83C552 has two software selectable modes of reduced activity for further power reduction - Idle and
Power-down. The Idle mode freezes the CPU and resets
Timer T2 and the ADC and PWM circuitry but allows
the other timers, RAM, serial ports and interrupt system
to continue functioning. The Power-down mode saves the
RAM contents but freezes the oscillator causing all other
chip functions to become inoperative.

DIFFERENCES FROM THE 8051
PROGRAM MEMORY
The 83C552 contains 8K-bytes of on-chip program memory which can be extended to 64K-bytes with external
memories (see Figure 13). When the EA pin is held
high, the 83C552 fetches instructions from internal ROM
unless the address exceeds 1FFFH. Locations 2000H to
FFFFH are fetched from external program memory.
When the EA pin is held low, all instructions fetches are
from external memory. ROM locations 0003H to 0073H
are used by interrupt service routines.

February 1989

The internal data memory is divided into 3 sections: the
lower 128 bytes of RAM, the upper 128 bytes of RAM
and the 128-byte special function register areas. The
lower 128 bytes of RAM are directly and indirectly addressable. While RAM locations 128 to 255 and the special function register area share the same address space,
they are accessed through different addressing modes.
RAM locations 128 to 255 are only indirectly addressable and the special function registers are only directly
addressable. All other aspects of the internal RAM are
identical to the 8051.
The stack may be located anywhere in the internal RAM
by loading the eight bit stack pointer. Stack depth is 256
bytes maximum.
SPECIAL FUNCTION REGISTERS
The special function registers (directly addressable only)
contain all of the 83C552 registers except the program
counter and the four register banks. Most of the 56 special function registers are used to control the on-chip
peripheral hardware. Other registers include arithmetic
registers (ACC, B, PSW), stack pointer (SP) and data
pointer registers (DHP, DPL). Sixteen of the SFR's
contain 128 directly addressable bit locations. Table 8
lists the 83C552's special function registers.
The standard 80C51 SFR's are present and function
identically in the 83C552 except where noted in the following sections.
TIMER T2
Timer T2 is a 16-bit timer consisting of two registers
TMH2 (HIGH byte) and TML2 (LOW byte). The 16-bit
timer/counter can be switched off or clocked via a
prescaler from one of two sources: fosc/12 or an external signal. When Timer T2 is configured as a counter,
the prescaler is clocked by an external signal on T2
(P1.4). A rising edge on T2 increments the prescaler
and the maximum repetition rate is one count per machine cycle (lMHz with a 12MHz oscillator).
The maximum repetition rate for Timer T2 is twice the
maximum repetition rate for Timer 0 and Timer 1. T2
(P1.4) is sampled at S2P1 and again at S5P1 (i.e., twice
per machine oycle). A rising edge is detected when T2
is LOW during one sample and HIGH during the next
sample. To ensure that a rising edge is detected, the input signal must be LOW for at least 1/2 cycle and then
HIGH for at least 112 cycle. If a rising edge is detected
before the end of S2P1, the timer will be incremented
during the following cycle; otherwise it will be incremented one cycle later. The prescaler has a programmable division factor of 1, 2, 4 or 8 and is cleared if its
division factor or input source is changed, or if the timer/counter is reset.

2-53

User's Guide

Signetics Microprocessor Products

Section 2 - 8051 Derivatives

8XC552

(FF FFHI 64 K
(FFFFHI 64K ...-------,

EXTERNAL

(20 OOHI 8192
(1 FFFHI

8191

(

INTERNAL
(EA. 11

(FFHI 255

EXTERNAL
(EA·OI

...-----<,

(7FHI 127
(OOOOHI 0

INTERNAL
DATA RAM

(OOH) 0

(OOOOHI 0 '--_ _ _.....

~------~y~--------~

~'--------~y~--------~

PROGRAM MEMORY

INTERNAL
DATA MEMORY

~
EXTERNAL
DATA MEMORY

Figure 13. Memory Map
Timer 1'2 may be read "on the fly", but possesses no
extra read latches and software precautions may have to
be taken to avoid misinterpretation in the event of an
overflow from least to most significant byte while Timer
1'2 is being read.· Timer 1'2 is not load able and is reset
by the RST signal or by a rising edge on ~e inp~t signal
R1'2, if enabled. R1'2 is enabled by setting bIt 1'2ER
(TM2CON.5).

lEN (E8H)

lenlECM2IECMIIECMOIEcr3IECT2IEcnlecrol
MSB

When the least significant byte of the timer overflows or
\\hen a 16-bit overflow occurs, an interrupt request may
be generated. Either or both of these overflows can be
programmed to request an interrupt. In both cases, the
interrupt vector will be the same. When the lower byte
(TML2) overflows, flag 1'2BO (TM2CON) is set and flag
1'20V (TM2IR) is set when TMH2 overflows. These flags
are set one cycle after an overflow occurs. Note that
\\hen T20V is set, T2BO will also be set. To enable the
byte overflow interrupt, bits ET2 (IENl. 7, enable overflow interrupt, see Figure 14) and 1'2lS0 (TM2CON.6,
byte overflow interrupt select) must be set. Bit T2BO
(TM2CON.4) is the Timer T2 byte overflow flag.

February 1989

LSB

BIT

Symbol

Function

lEN 1.7
lENl.6
IENl.5
IENl.4
lEN 1.3
IENl.2
IENl.l
IENl.O

ET2

Enable Timer T2 overflow interrupt( s)
Enable T2 Comparator 2 interrupt
Enable T2 Comparator I interrupt
Enable T2 Comparator 0 interrupt
Enable T2 Capture register 3 interrupt
Enable T2 Capture register 2 interrupt
Enable T2 Capture register I interrupt
Enable T2 Capture register 0 interrupt

ECM2
ECMI
ECMO
ECf3

ECT2
ECfI

Ecro

Figure 14. Timer T2 Interrupt Enable Register (lEN1)

2-54

User's Guide

Signetics Microprocessor Products

8XC552

Section 2 - 8051 Derivatives
Table 8. 8XC552 Special Function Registers
Symbol

Description

Accumulator
ACC*
ADCH# A/D converter high
ADCON# Adc control
B*
B register
CTCON# Capture control
CTH3#
Capture high 3
CTH2#
Capture high 2
CTHl#
Capture high 1
CTHO#
Capture high 0
CMH2# Compare high 2
Compare
high 1
CMH1#
CMHO# Compare high 0
CTL3#
Capture low 3
CTL2#
Capture low 2
CTL1#
Capture low 1
Capture low 0
CTLO#
CML2# Compare low 2
CML1# Compare low 1
CMLO# Compare low 0
DPTR:
Data pointer (2 bytes)
DPH
Data pointer high
DPL
Data pointer low

Direct
Address
EOH
C6H

CSH
FOH
EBH
CFH
CEH
CDH
CCH
CBH
CAR
C9H
AFH
AEH
ADH
ACH
ABH
AAH
A9H

Bit Address, Symbol or Alternative Port Function
Reset Value
LSB
MSB
EO OOH
E7
E6
ES
E4
E3
E2
E1
xxxxxxxxB
iADc.lIADc.0IADEX1ADCljADC~AADR2jAADR!lAAD~ xxOOOOOOB

F6
FS
F4
F3
F2
Fl
FO OOH
F7
CTN31 CTP3 I CTN21 CTPZ ICTNll CTP ICTNO I CTPO OOH
xxxxxxxxB
xxxxxxxxB
xxxxxxxxB
xxxxxxxxB

OOH
OOH
OOH
xxxxxxxxB
xxxxxxxxB
xxxxxxxxB

xxxxxxxxB
OOH
OOH
OOH

83H
82H

IENO*

Interrupt enable 0

A8H

IENl*#

Interrupt enable 1

E8H

IPO*

Interrupt priority 0

B8H

IP1*#

PS#

Interrupt priority 1
Port S

F8H
C4H

P4*#

Port 4

COH

P3*

Port 3

BOH

PZ*

Port 2

AOH

Pl*

Port 1

90H

PO*
PCON

Port 0
Power control

80H
87H

OOH
OOH
AF
AE
AD
AC
AB
A8
AA
A9
EA I EAD I ESlj ESO j ETlj EXlj ETO 1 ETl OOH
EF
EE
ED
EC
EB
EA
E9
E8
ET2 IECM21 ECMllECMO IECT31 ECTZI ECTl I ECTO OOH
BF
BE
BD
BB
BC
BA
B9
B8
- I PAD I PSl I PSO I PTl I PXl I PTO I PXO xOOOOOOOB
FF
FE
FD
FC
FB
FA
F9
F8
PT2 1PCM21 PCMl LPCMol PCT3J PCTZ I PCTl I PCTO OOH
ADC71ADC61ADCsIADC41ADC31ADC21ADCliADCO xxxxxxxxB
C7
C6
CS
C4
C3
C2
CO
Cl
CMTlI CMTOlcMSRSlcMSR4IcMSR3lcMSR2lcMSRllcMSRO FFH
B7
B6
BS
B4
B3
B2
B1
BO
RD I WR I Tl I TO IINTlI INTO I TXD I RXD FFH
A7
A6
AS
A4
A3
A2
Al
AO
AlS I Al4 I A13 1 Al2 I All I AlO I A9 I A8 FFH
97
96
9S
94
93
92
91
90
SDA I SCL I RT2j T2 j CT3Ij CTZlj CTlIj CTOI FFH
87
86
8S
84
83
82
80
81
AD7 I AD6 I ADS I AD4 I AD3 I AD2 I ADl I ADO FFH
SMODI I I WLE I GFI I GFO I PD I IDL OOxxOOOOOB
D7
D6
DS
D4
D3
D2
Dl
DO
CY I Ac.1 FO.1 RSlj RSOj OV L Fl 1 P
OOH
OOH
OOH
OOH
TP47 jTP46 I RP4Sj RP44 JRP431 RP42 IRP4l I RP40 OOH
07H
xxxxxxxxB

PSW·
Program status word
DOH
PWMP# PWM prescaler
FEH
PWMl# PWM register 1
FDH
PWMO# PWM register 0
FCH
RTE#
Reset/toggle enable
EFH
SP
Stack pointer
8lH
SOBUF
Serial 0 data buffer
99H
* = SFRs are bit addressable.
# = SFRs are modified from or added to the 80CSl SFRs.

February 1989

2-55

User's Guide

Signetics Microprocessor Products

8XC552

Section 2 - 8051 Derivatives
Table 8. 8XC552 Special Function Registers (Continued)
Description

Symbol
0
I
I
I

Direct
Address

SOCON*
SIADR#
SIDAT#
SISTA#

Serial
Serial
Serial
Serial

control
address
data
status

98H
DBH
DAH
D9H

SICON#*
STE#

Serial I control
Set enable

D8H
EEH

THI
THO
TLl
TLO
TMH2#
TML2#
TMOD

Timer
Timer
Timer
Timer
Timer

8DH
8CH
8BH
8AH
EDH
ECH
89H

high I
high 0
low I
low 0
high 2

Timer low 2
Timer mode

TCON*
Timer control
TM2CON# Timer 2 control

88H
EAH

TM2IR#
T3#
• = SFRs
# = SFRs

C8H
FFH

Timer 2 int flag reg
Timer 3

Bit Address, Symbol or Alternative Port Function
Reset Value
LSB
MSB
9F
9E
9D
9C
9B
9A
99
98
REN
TB8
RB8
TI
R1
OOH
SMO I SMI
SM2
GC OOH
SLAVE ADDRESS
OOH
SC4j SC3 I SC2 I SCI 1 sco I 0 l 0 1 0
F8H
DF
DE
DD
DC
DB
DA
D9
D8
CRI
CRO xOOOOOOOB
SI
AA
- -.l ENSI STA STO
TG47-.l TG46 I SP45 I SP44 I SP43 I SP42 L SP411 SP40 COH

GATE I CIT
8F
8E
TFI J TRI
T2ISIJ TSISO
CF
CE
nov1 CMI2

OOH
OOH
OOH
OOH
OOH
OOH
OOH

I MI I MO I GATE I
8D
8C
I TFO I TRO I
I T2ER I T2BO I
CD
CC
I CMIl I CMIO I

CIT I MI I MO
8B
8A
89
88
IEI I IT! I lEO I ITO OOH
T2PI I T2PO IT2MSII T2MSO OOH
CB
CA
C9
C8
CTI3 I CTI2 j CTIll CTIO OOH
OOH

are bit addressable.
are modified from or added to the 80C51 SFRs.

To enable the 16-bit overflow interrupt, bits ET2 (IE1.7,
enable overflow interrupt) and T2ISI (TM2CON.7, 16-bit
overflow interrupt select) must be set. Bit T20V
(TM2IR.7) is the Timer T2 16-bit overflow flag. All interrupt flags must be reset by software. To enable both
byte and 16-bit overflow, T2ISO and T2ISI must be set
and two interrupt service routines are required. A test on
the overflow flags indicates which routine must be executed. For each routine, only the corresponding overflow
flag must be cleared.

OVINT: PUSH
PUSH
INC

MOV
JNZ

INC
Timer T2 may be reset by a nsmg edge on RT2 (Pl.5)
if the Timer T2 external reset enable bit (T2ER) in
T2CON is set. This reset also clears the prescaler. In
the Idle mode, the timer/counter and prescaler are reset
and halted. Timer T2 is controlled by the TM2CON special function register (see Figure 15).

MOV
JNZ

INC

Timer T2 Extension

INTEX: CLR
When a 12MHz oscillator is used, a 16-bit overflow on
Timer T2 occurs every 65.5, 131, 262 or 524ms depending on the prescaler division ratio i.e. the maximum
cycle time is approximately 0.5 seconds. In applications
where cycle times are greater than 0.5 seconds, it is
necessary to extend Timer T2. This is achieved by selecting foscl12 as the clock source (set T2MSO, reset
T2MSl), setting the prescaler division ratio to 118 (set
T2PO, set T2Pl), disabling the byte overflow interrupt
(reset T2ISO) and enabling the 16-bit overflow interrupt
(set T2ISl). The following software routine is written for
a three-byte extension which gives a maximum cycle
time of approximately 2400 hours.

February 1989

POP
POP
RETI

ACC
PSW
TIMEXI

;save accumulator
;save status
;increment first
; byte (low order)
;of extended timer

A,TIMEXI
INTEX
; jump to INTEX if
;there is no
; overflow
TIMEX2 ; increment second
; byte
A,TIMEX2
INTEX
; jump to INTEX i f
; there is no
; overflow
TIMEX3 ;increment third
; byte (high order)
T20V
;reset interrupt
; flag
PSW
; restore status
ACC
;restore accumulator
; return from
; interrupt

Timer T2, Capture and Compare Logic
Timer T2 is connected to four 16-bit capture registers
and three 16-bit compare registers. A capture register
may be used to capture the contents of Timer T2 when a
transition occurs on its corresponding input pin. A compare register may be used to set, reset or toggle Port 4
output pins at certain pre-programmable time intervals.

2-56

User's Guide

Signetics Microprocessor Products

8XC552

Section 2 - 8051 Derivatives

6
TM2CON
(EAH)

I I

11'21S1 1'2150 11'2ER 1'280 1'2PI I T2I'IlI 1'2MSII 1'2M5O I

MSB

Bit

LSB

Symbol

TM2CON.7
TM2CON.6
TM2CON.5

TM2CON.4
TM2CON.3
TM2CON.2

Functioa

1'2ISI Timer 1'2 l6-bitoverflow intenuptselect
1'21S0 Timer 1'2 byte overflow intenupl select
1'2ER Timer 1'2 external reset enable. When this
bit is set. Timer 1'2 may be reset by a rising
edge on R1'2 (PI.5).
1'280 Timer 1'2 byte overflow interrupt flag

:g~

}

Timer 1'2 prescaler select

T2P1
0
0
I
I
TM2CON.I

1'2MSI

TM2CON.0

1'2MSO

1'21'0
0
I
0
I

o
o
I
I

o
I
o
I

When a recurring external event is represented in the
form of rising or falling edges on one of the four capture
pins, the time between two events can be measured using
Timer 1'2 and a capture register. When an event occurs,
the contents of Timer 1'2 are copied into the relevant
capture register and an interrupt request is generated.
The interrupt service routine may then compute the interval time if it knows the previous contents of Timer 1'2
when the last event occurred. With a 12MHz oscillator,
Timer 1'2 can be programmed to overflow every S24ms.
When event interval times are shorter than this, computing the interval time is simple and the interrupt service
routine is short. For longer interval times, the Timer 1'2
extension routine may be used.
Compare Logic

Mode selected
Timer 1'2 halted (oft)
1'2 clock source f..J12
Test mode; do not use
1'2 clock source pin 1'2

=
=

Figure 15. T2 Control Register (TM2CON)

The combination of Timer 1'2 and the capture and compare logic is very powerful in applications involving rotating machinery, automotive injection systems, etc. Timer
1'2 and the capture and compare logic are shown in Figure 16.
Capture Logic

The four 16-bit capture registers that Timer 1'2 is connected to are: cro, crl, CI'2 and Cf3. These registers
are loaded with the contents of Timer 1'2 and an interrupt is requested upon receipt of the input signals croI,
crll, CI'2I or CI'3I. These input signals are shared with
Port 1. The four interrupt flags are in the Timer 1'2 interrupt register (TM2IR special function register). If the
capture facility is not required, these inputs can be regarded as additional external interrupt inputs.
Using the capture control register crCON (see Figure
17), these inputs may capture on a rising edge, a falling
edge or on either a rising or falling edge. The inputs are
February 1989

Measuring Time Intervals using Capture Registers

Timer 1'2 clock
clock source
clock source/2
clock source,l4
clock sourcet8

} Tuner 1'2 mode select

1'2MSI T2MSO

sampled during SIP! of each cycle. When a selected
edge is detected, the contents of Timer 1'2 are captured
at the end of the cycle.

Each time Timer 1'2 is incremented, the contents of the
three 16-bit compare registers CMO, CMl and CM2 are
compared with the new counter value of Timer 1'2. When
a match is found, the corresponding interrupt flag in
TM2IR is set at the end of the following cycle. When a
match with CMO occurs, the controller sets bits 0-5 of
Port 4 if the corresponding bits of the set enable register
STE are at logic 1. When a match with CMl occurs, the
controller resets bits 0-5 of Port 4 if the corresponding
bits of the reset/toggle enable register RTE are at logic
1 (see Figure 18 for RTE register function). If RTE is
'0', then P4.n is not affect by a match between CMl or
CM2 and Timer 2. When a match with CM2 occurs, the
controller 'toggles' bits 6 and 7 of Port 4 if the corresponding bits of the RTE are at logic 1. The port latches of bits 6 and 7 are not toggled. Two additional flipflops store the last operation and it is these flip-flops
that are toggled. Thus, if the current operation is 'set',
the next operation will be 'reset' even if the port latch is
reset by software before the 'reset' operation occurs. The
first 'toggle' after a chip RESET will set the port latch.
The contents of these two flip flops can be read at
STE.6 and STE.7 (corresponding to P4.6 and P4.7 respectively). Bits STE.6 and STE.7 are read only (see
Figure 19 for STE register function). A logic 1 indicates
that the next toggle will set the port latch; a logic 0 indicates that the next toggle will reset the port latch.
CMO, CMl and CM2 are reset by the RST signal.
The. modified port latch information appears at the port
pin during SSP 1 of the cycle following the cycle in which
a match occurred. If the port is modified by software,
the outputs change during S1Pl of the following cycle.
Each port 4 bit can be set or reset by software at any
time. A hardware modification resulting from a
comparator match takes precedence over a software
modification in the same cycle. When the comparator
results require a 'set' and a 'reset' at the same time, the
port latch will be reset.
.

2-57

User's Guide

Signetics Microprocessor Products

8XC552

Section 2 - 8051 Derivatives

~r I~ I

IT 1+11

eTO

eTl

I~:I ~r I~'I

eT2

eT3

off

8 - bit overflow

interrupt

fose

I&-bit overflow

interrupt

RT2
T2ER

external reset
enable

P4.0

P4.1

P4.2

INT

I/O port 4

P4.3~

P4.4

P4.S

P4.&

P4.7

STE

RTE

'\r--V
5 •

T2 SFR address, TML2· lower 8 bits
TMH2· higher 8 bits

SIll

R • reset

T • toggle
TG • toggle status

Figure 16. Block Diagram of Timer 2
7

7643210

~~H)ICIl3~1 erNj eml erN I CiPI C"3 aw I
MSB

Rn (mf)

11?4711P* 1aN'l __ RP431 aN21 aNI
MSB

LSB

S,mIIoI , Capture/lDterruptan:

BIT

Symbol Functloa

CTCON.7

CTN3

RTE.7

11'47

CTCON:6

CI'P3

RTE.6

11'46

CTCON.S

CTN2

CTCON.4

CTP2,

CTCON.3

CTNI

CTCON.2

CI1'I

CTCON.I

CTNO

RTE.5

ItP45

RTE.4

RP44

RTE.3

RP43

RTE.2

RP42

RTE.I

RP41

RTE.O

RP40

edge 01\ CTOI

CTCON.O

CTPO

Capture Register 0 lrigered by a risi",
edge 011 CTOI

Figure 17. Capture Control Register (CTCON)

February 1989

RP40
LSB

Bit

CapIUIe Register 3lriggeRd by a falling
edge on CT31
Capture Register 3 lriggeRd by a rising
edge 011 CT31
,.
Capture Register 2lriggeRd by a falling
edge 011 CT21
Capture Register 2lriggeRd by a rising
edgeOllCT21
Capture Register IlriggeRd by a falli",
edge 011 CTII
Capture Register 11riggeRd by a rising
edge on CTII
CapIUIe Register 0 IriggeRd by a fallin.

I I

if 'I' then P4.7 toggles 01\ a march between
CM2111d Tuner 1'2
if 'I' then P4.6 toggles 011 • march between
CM21J1d Tuner 1'2
if 'I' then P4.5 is reset an a march between
CMIIJId Timer1'2
if 'I' then P4.4 is reset 0111 march between
CMIIJId Tuner 1'2
if 'I' then P4.3 is reset 011 1 mlk:b between
CMIIJId Timer 1'2
if 'I' then P4.2 is reset 011 1 march between
CMIIJId Timer 1'2
if 'I' then N.I is reset 011 1 march between
CMIIIId Timer 1'2
if 'I'lbea P4.0 is rae! 011 anwch between
CMI IJId Tuner 1'2

Figure 18, ReseVfoggle Enable Register (RTE)

2-58

Signetics Microprocessor Products

User's Guide

Section 2 - 8051 Derivatives

8XC552
able period of time. An analogy is the "dead man's handle" in railway locomotives. When enabled, the watchdog
circuitry will generate a system reset if the user program
fails to reload the watchdog timer within a specified
length of time known as the 'watchdog interval'.

765
432
1
0
STE (EEH) ITG471TG461SP451SP441SP431sP42jSP411sP40
LSB
MSB
Bit
Symbol
STE.7 TG47
STE.6 TG46
STE.5 SP45
STE.4

SP44

STE.3

SP43

STE.2

SP42

STE.1

SP41

STE.O

SP40

Function
Toggle flip-flops
Toggle flip-flops
If '1' then P4.5 is set on a
tween CMO and timer T2
If '1' then P4.4 is set on a
tween CMO and timer T2
If '1' then P4.3 is set on a
tween CMO and timer T2
If '1' then P4.2 is set on a
tween CMO and timer T2
If '1' then P4.1 is set on a
tween CMO and timer T2
If '1' then P4.0 is set on a
tween CMO and timer T2

match be-

match bematch bematch bematch be-

Figure 19. Set Enable Register (STE)

Eight of the nine Timer T2 interrupt flags are located in
special function register 1M2IR (see Figure 20). The
ninth flag is 1M2CON.4.
The CTOI and CTlI flags are set during S4 of the cycle
in which the contents of Timer T2 are captured. CTOI is
scanned by the interrupt logic during S2 and CTlI is
scanned during S3. CTII and CT3I are set during S6
and are sc anned during S4 and S5. The associated interrupt requests are recognized during the following cycle.
If these flags are polled, a transition at CTOI or CTlI
will be recognized one cycle before a transition on CTII
or CT3I since registers are read during S5. The CMIO,
CMIl and CMI2 flags are set during S6 of the cycle following a match. CMIO is scanned by the interrupt logic
during S2; CMIl and CMI2 are scanned during S3 and
S4. A match will be recognized by the interrupt logic (or
by polling the flags) two cycles after the match takes
place.

Special function register IP1 (Figure 20) is used to determine the Timer T2 interrupt priority. Setting a bit
high gives that function a high priority, and setting a bit
low gives the function a low priority. The functions controlled by the various bits of the IP1 register are shown
in Figure 20.
TIMER T3, THE WATCHDOG TIMER
In addition to Timer T2 and the standard timers, a
watchdog timer is also incorporated on the 83C552. The
purpose of a watchdog timer is to reset the microcontroller if it enters erroneous processor states (possibly caused by electrical noise or RFI) within a reason-

February 1989

Interrupt Flag Register (TM2IR)

Timer T2 Interrupt Flag Register TM2IR

The 16-bit overflow flag (T20V) and the byte overflow
flag (T2BO) are set during S6 of the cycle in which the
overflow occurs. These flags are recognized by the interrupt logic during the next cycle.

M21R (C8H)IT20VICMI2ICMI1ICMIOI CTl31 CTI21 CTI1 I CTIO
MSB
LSB
Bit
Symbol
Function
TM2IR.7
T20V
Timer T2 16-bit overflow interrupt flag
TM2IR.6
CMI2
CM2 interrupt flag
TM2IR.5
CMI1
CM 1 interrupt flag
TM2IR.4
CMIO
CMO interrupt flag
TM2IR.3
CTI3
CT3 interrupt flag
TM2IR.2
CTI2
CT2 interrupt flag
TM2IR.1
CTI1
CT1 interrupt flag
TM2IR.O
CTIO
CTO interrupt flag

match be-

7
4
6
5
2
3
1
0
IP1 (F8H) I PT2 IPCM21pCM11pCMOI PCT31 PCT21 PCT1I PCTO
MSB
LSB
Bit
Symbol
Function
IP1.7
PT2
Timer T2 overlfow interrupt(s) priority
level
IP1.6
PCM2 Timer T2 comparator 2 interrupt priority
level
IP1.5
PCM1 Timer T2 comparator 1 interrupt priority
level
IP1.4
PCMO Timer T2 comparator 0 interrupt priority
level
IP1.3
Timer T2 capture register 3 interrupt
PCT3
priority level
IP1.2
PCT2
Timer T2 capture register 2 interrupt
priority level
IP1.1
PCT1
Timer T2 capture register 1 interrupt
priority level
IP1.0
PCTO
Timer T2 capture register 0 interrupt
priority level

Timer 2 Interrupt Priority Register (IPi)
Figure 20. Interrupt Flag Register (TM2IR)
and Timer T2 Interrupt Priority Register (IPl)
Watchdog Circuit Description
The watchdog timer (Timer T3) consists of an 8-bit timer with an ll-bit prescaler as shown in Figure 21. The
prescaler is fed with a signal whose frequency is 1/12
the oscillator frequency (1MHz with a 12 MHz oscillator). The 8-bit timer is incremented every 't' seconds
where:
t

2-59

12 x 2048 x lIfosc (= 2ms at fosc = 12MHz)

User's Guide

Signetics Microprocessor Products

8XC552

Section 2 - 8051 Derivatives

PRESCALER
11- BIT

TIMER TJIB·BIT!
LOAD LOADEN

,.....

internal

writ~

-----c;:]

-~t----l

_-_-~~~_-_-_-__I -- '~f::'''

I -......- - - - - - - - " ' -_ _ _ _ _ _ _..

EWI

.....

INTERNAL BUS

Figure 21. Watchdog Timer
If the 8-bit timer overflows, a short internal reset pulse
is generated which will reset the 83CSS2. A short output
reset pulse is also generated at the RST pin. This short
output pulse (3 machine cycles) may be destroyed if the
RST pin is connected to a capacitor. This would not,
however, affect the internal reset operation.

Watchdog operation is activated when external pin EW is
tied low. When EW is tied low, it is impossible to disable watchdog operation by software.
How to Operate the Watchdog Timer
The watchdog timer has to be reloaded within periods
that are shorter than the programmed watchdog interval;
otherwise the watchdog timer will overflow and a system
reset will be generated. The user program must therefore continually execute sections of code which reload
the watchdog timer. The period of time elapsed between
execution of these sections of code must never exceed
the watchdog interval. When using a 12MHz oscillator,
the watchdog interval is programmable between 2ms and
S1Oms.
In order to prepare software for watchdog operation, a
programmer should first determine how long his system
can sustain an erroneous processor state. The result will
be the maximum watchdog interval. As the maximum
watchdog interval becomes shorter, it becomes more difficult for the programmer to ensure that the user program always reloads the watchdog timer within the

February 1989

watchdog interval and thus it becomes more difficult to
implement watchdog operation.
The programmer must now partition the software in such
a way that reloading of the watchdog is carried out in
accordance with the above requirements. The programmer must determine the execution times of all software
modules. The effect of possible conditional branches,
subroutines, external and internal interrupts must all be
taken into account. Since it may be very difficult to
evaluate the execution times of some sections of code,
the programmer should use worst case estimations. In
any event, the programmer must make sure that the
watchdog is not activated during normal operation.
The watchdog timer is reloaded in two stages in order to
prevent erroneous software from reloading the watchdog.
First, PCON.4 (WLE) must be set. Then T3 may be
loaded. When T3 is loaded, PCON.4 (WLE) is automatically reset. T3 can not be loaded if PCON.4 (WLE)
is reset. Reload code may be put in a subroutine as it is
called frequently. Since Timer T3 is an up-counter, a
reload value of OOH gives the maximum watchdog interval (S1Oms with a 12MHz oscillator) and a reload value
of OFFH gives the minimum watchdog interval (2ms with
a 12MHz oscillator).
In the Idle mode, the watchdog circuitry remains active.
When watchdog operation is implemented, the Powerdown mode cannot be used since both states are contradictory. Thus, when watchdog operation is enabled by ty-

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8XC552

ing external pin EW low, it is impossible to enter the
Power-down mode and an attempt to set the Power-down
bit (PCON.l) will have no effect. PCON.l will remain at
logic O.

- Multimaster bus (no central master)
- Arbitration between simultaneously transmitting masters
without corruption of serial data on the bus
- Serial clock synchronization allows devices with different bit rates to communicate via one serial bus
- Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer
- The 12C bus may be used for test and diagnostic purposes

During the early stages of software development/debugging, the watchdog may be disabled by tying the EW pin
high. At a later stage, EW may be tied low to complete
the debugging process.
Watchdog Software Example

The output latches of P1.6 and Pl.7 must be set to logic
1 in order to enable SIal.

The following example shows how watchdog operation
might be handled in a user program.

The 83C552 on-chip 12C logic provides a serial interface
that meets the 12C bus specification and supports all
transfer modes (other than the low speed mode) from
and to the I2C bus. The SIal logic handles bytes transfer autonomously. It also keeps track of serial transfers,
and a status register SlSTA) reflects the status of SIal
and the 12C bus.

;at the program start:
T3

EQU OFFH ;address of
;watchdog timer T3
PCON
EQU 087H ;address of PCON SFR
WATCH-INTV EQU 156 ;watchdog interval
;(e.g.2xlOOms)
ito be inserted at each watchdog reload
;location within the user program:
LCALL WATCHDOG
;watchdog service routine:
WATCHDOG: ORL

PCON,tlOH

;set condition
; flag (PCON. 4)
MOV T3,WATCH-INV ;load T3 with
; watchdog
; interval
RET

If it is possible for this subroutine to be called in an erroneous state, then the condition flag WLE should be set

at different parts of the main program.
SERIAL 110
The 83C552 is equipped with two independent serial
ports: SIOO and SIal. SIOO is a full duplex UART port
and is identical to the 80C5l serial port. SIal accommodates the l2C bus.
SIOO
SIOO is a full duplex serial I/O port identical to that on
the 80C51. Its operation is identical including the use of
timer 1 as a baud rate generator.
S101, Pc Serial 1/0
The 12C bus uses two wires (SDA and SCL) to transfer
information between devices connected to the bus. The
main features of the bus are:
- Bidirectional data transfer between masters and slaves

February 1989

The CPU interfaces to the I2C logic via the following
four special function registers: SlCON (SIal control
register), SlSTA (SIOI status register), SlDAT (SIOI
data register) and SlADR (SIal slave address register).
The Sial logic interfaces to the external 12C bus via
two Port 1 pins: P1.6/SCL (serial clock line) and Pl.71
SDA (serial data line).
A typic al 12C bus configuration is shown in Figure 22
and Figure 23 shows how a data transfer is accomplished
on the bus. Depending on the state of the direction bit
(R/W), two types of data transfers are possible on the
12C bus:
1. Data transfer from a master transmitter to a slave
receiver. The first byte transmitted by the master is
the slave address. Next follows a number of data
bytes. The slave returns an acknowledge bit after each
received byte.
2. Data transfer from a slave transmitter to a master
receiver. The first byte (the slave address) is transmitted by the master. The slave then returns an acknowledge bit. Next follows a number of data bytes transmitted by the slave to the master. The master returns
an acknowledge bit after all received bytes other than
the last byte. At the end of the last received byte, a
'not acknowledge' is returned.
The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer is
ended with a STOP condition or with a repeated START
condition. Since a repeated START condition is also the
beginning of the next serial transfer, the I2C bus will not
be released.
Modes of Operation
The on-chip SIal logic may operate in the following
four modes:

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Section 2 - 8051 Derivatives

VOD

) Rp

] Rp

SDA
SCL

Pl.7/SDA

Pl.6/SCL

83C552

OTHER DEVICE
WITH 12C
INTERFACE

OTHER DEVICE
WITH ,2C
'NTERFACE

Figure 22. Typical Pc Bus Configuration

r-l

SOA~_-

I
I

I
I
I
I
I
I
I

i \.J

I
I

STOP COndition

__ J~-J~~_ _~

SCl~

MSB

.,... odd,. .

r\
\.J 2 L __

r\
t

L..!.J
START
CONDiTION

Figure 23. Data Transfer on the 12C Bus
1. Master Transmitter Mode:

2. Master Receiver Mode:

Serial data output through P1.7/SDA while P1.6/SCL
outputs the serial clock. The first byte transmitted contains the slave address of the receiving device (7 bits)
and the data direction bit. In this case the data direction
bit (RJW) will be logic 0 and we say that a 'W' is
transmitted. Thus the first byte transmitted is SLA+W.
Serial data is transmitted 8 bits at a time. After each
byte is transmitted, an acknowledge bit is received.
START and STOP conditions are output to indicate the
beginning and the end of a serial transfer.

The first byte transmitted contains the slave address of
the transmitting device (7 bits) and the data direction
bit. In this case the data direction bit (RJW) will be logic 1 and we say that an 'R' is transmitted. Thus the first
byte transmitted is SLA+R. Serial data is received via
P1.7/SDA while P1.6/SCL outputs the serial clock. Serial data is received eight bits at a time. After each byte
is received, an acknowledge bit is transmitted. START
and STOP conditions are output to indicate the beginning
and end of a serial transfer.

February 1989

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3. Slave Receiver Mode:

Comparator

Serial data and the serial clock are received through
P1.7/SDA and P1.6/SCL. After each byte is received, an
acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end of a serial
transfer. Address recognition is performed by hardware
after reception of the slave address and direction bit.

The comparator compares the received 7-bit slave address with its own slave address (7 most significant bits
in SlADR). It also compares the first received 8-bit
byte with the general call address (OOH). If an equality
is found, the appropriate status bits are set and an interrupt is requested.

4. Slave Transmitter Mode:

Shift Register, SlDAT

The first byte is received and handled as in the slave receiver mode. However, in this mode, the direction bit
will indicate that the transfer direction is reversed. Serial data is transmitted via P1.7/SDA while the serial
clock is input through P1.6/SCL. START and STOP
conditions are recognized as the beginning and end of a
serial transfer.

This 8-bit special function register contains a byte of serial data to be transmitted or a byte which has just been
received. Data in SlDAT is always shifted from right to
left; the first bit to be transmitted is the MSB (bit 7)
and, after a byte has been received, the first bit of received data is located at the MSB of SlDAT. While data
is being shifted out, data on the bus is simultaneously
being shifted in; SlDAT always contains the last byte
present on the bus. Thus, in the event of lost arbitration,
the transition from master transmitter to slave receiver
is made with the correct data in SlDAT.

In a given application, SIal may operate as a master
and as a slave. In the slave mode, the SIal hardware
looks for its own slave address and the general call address. If one of these addresses is detected, an interrupt
is requested. When the microcontroller wishes to become
the bus master, the hardware waits until the bus is free
before the master mode is entered so that a possible
slave action is not interrupted. If bus arbitration is lost
in the master mode, SIal switches to the slave mode
immediately and can detect its own slave address in the
same serial transfer.
SI01 Implementation and Operation
Figure 24 shows how the on-chip 12C bus interface is
implemented and the following text describes the individual blocks.
Input Filters and Output Stages
The input filters have 12C compatible input levels. If the
input voltage is less than 1.5V, the input logic level is
interpreted as 0; if the input voltage is greater than 3.0
V, the input logic level is interpreted as 1. Input signals
are synchronized with the internal clock (fosc/4) and
spikes shorter than three oscillator periods are filtered
out.
The output stages consist of open drain transistors that
can sink 3mA at VOUT < O.4V. These open drain outputs do not have clamping diodes to VDD. Thus, if the
device is connected to the 12C bus and VDD is switched
off, the 12C bus is not affected.
Address Register, SlADR
This 8-bit special function register may be loaded with
the 7-bit slave address (7 most significant bits) to which
SIal will respond when programmed as a slave transmitter or receiver. The LSB (aC) is used to enable general
call address (DOH) recognition.

February 1989

Arbitration and Synchronization Logic
In the master transmitter mode, the arbitration logic
checks that every transmitted logic 1 actually appears as
a logic 1 on the 12C bus. If another device on the bus
overrules a logic 1 and pulls the SDA line low, arbitration is lost and SIal immediately changes from master
transmitter to slave receiver. SIal will continue to output clock pulses (on SCL) until transmission of the current serial byte is complete.
Arbitration may also be lost in the master receiver
mode. Loss of arbitration in this mode can only occur
while SIal is returning a 'not acknowledge' (logic 1) to
the bus. Arbitration is lost when another device on the
bus pulls this signal LOW. Since this can occur only at
the end of a serial byte, SIal generates no further clock
pulses. Figure 25 shows the arbitration procedure.
The synchronization logic will synchronize the serial
clock generator with the clock pulses on the SCL line
from another device. If two or more master devices generate clock pulses, the 'mark' duration is determined by
the device that generates the shortest 'marks' and the
'space' duration is determined by the device that generates the longest 'spaces'. Figure 26 shows the synchronization procedure.
A slave may stretch the space duration to slow down the
bus master. The space duration may also be stretched
for handshaking purposes. This can be done after each
bit or after a complete byte transfer. SIal will stretch
the SCL space duration after a byte has been transmitted
or received and the acknowledge bit has been transferred. The serial interrupt flag (SI) is set and the
stretching continues until the serial interrupt flag is
cleared.

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8XC552

r---,

r
I

--I'- ___
PI.7
:
....

I
I

I
P1.8/SCL
OUTPUT
STAGE

'"...

INPUT
FILTER

-<
z

.
a::
w

P1.1/SDA

I
I

I
L

OUTPUT
STAGE

r---,

TIMER 1
OVERFLOW

-+IL.. _Pl.8
I
_ _ ..J

STATUS {
BITS

SlSTA

Figure 24. Block Diagram of the 12C Bus Serial Interface

February 1989

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8XC552

SDA

l . . ____

..J

·1

,--_!_ll_1.....JrL-.-_-_l_'~_-=I====='f..== _ ____JX\___C
(3)

--~

SCL

ACK

I. Another device transmits identical serial data
2. Another device overrules a logic I (dotted line) transmitted by SIOI (master) by pulling the SDA line LOW.
Arbitration is lost and SID 1 enters the slave receiver mode
3. SIOI is in the slave receiver mode but still generates clock pulses until the current byte has been transmitted.
SID I will not generate clock pulses for the next byte. Data on SDA originates from the new master once it has won
arbitration.

Figure 25. Arbitration Procedure

SDA

________~x~___________x==

SCL

I. Another sevice pulls the the SCL line low before the SIOI 'mark' duration is complete. The serial clock generator
is immediately reset and commences with the 'space' duration by pulling SCL LOW.
2. Another device stills pulls the SCL line LOW after SID I releases SCL. The serial clock generator is forced into the
~
wait state until the SCL line is released.
3. The SCL line is released and the serial clock generator commences with the mark duration.

Figure 26. Serial Clock Synchronization

February 1989

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8XC552

Serial Clock Generator
This programmable clock pulse generator provides the
SCL clock pulses when SIOI is in the master transmitter
or master receiver mode. It is switched off when SIOI is
in a slave mode. The programmable output clock frequencies are: fosc/120, fosc/9600 and the Timer 1 overflow rate divided by eight. The output clock pulses have
a 50% duty cycle unless the clock generator is synchronized with other seL clock sources as described above.
Timing and Control
The timing and control logic generates the timing and
control signals for serial byte handling. This logic block
provides the shift pulses for SlDAT, enables the
comparator, generates and detects start and stop conditions, receives and transmits acknowledge bits, controls
the master and slave modes, contains interrupt request
logic and monitors the 12C bus status.
Control Register, SlCON
This 7-bit special function register is used by the microcontroller to control the following SIOI functions: start
and restart of a serial transfer, termination of a serial
transfer, bit rate, address recognition and acknowledgment.
Status Decoder and Status Register
The status decoder takes all of the internal status bits
and compresses them into a 5-bit code. This code is
unique for each 12C bus status. The 5-bit code may be
used to generate vector addresses for fast processing of
the various servic.e routines. Each service routine processes a particular bus status. There are 26 possible bus
states if all four modes of SIOI are used. The 5-bit status code is latched into the five most significant bits of
the status register when the serial interrupt flag is set
(by hardware) and remains stable until the interrupt flag
is cleared by software. The three least significant bits of
the status register are always zero. If the status code is
used as a vector to service routines, then the routines
are displaced by eight address locations. Eight bytes of
code is sufficient for most of the service routines (see
the software example in this section).
More Information on SI01 Operating Modes
The four operating modes are:
- Master Transmitter
- Master Receiver
Slave Receiver
- Slave Transmitter
Data transfers in each mode of operation are shown in
Figures 27-30. These figures contain the following abbreviations:

February 1989

Abbreviation
S
SLA
R
W
A

A
DATA
p

Explanation
Start condition
7-bit slave address
Read bit (high level at SDA)
Write bit (low level at SDA)
Acknowledge bit (low level at SDA)
Not acknowledge bit (high level at SDA)
S-bi t data byte
Stop condition

In Figure 27-30, circles are used to indicate when the
serial interrupt flag is set. The numbers in the circles
show the status code held in the SlSTA register. At
these points, a service routine must be executed to continue or complete the serial transfer. These service routines are not critical since the serial transfer is suspended until the serial interrupt flag is cleared by
software.
When a serial interrupt routine is entered, the status
code in SlSTA is used to branch to the appropriate service routine. For each status code, the required software
action and details of the following serial transfer are
given in Tables 9-12.
Master Transmitter Mode
In the master transmitter mode, a number of data bytes
are transmitted to a slave receiver (see Figure 27). Before the master transmitter mode can be entered,
SleON must be initialized as follows:
7

SlCON (DSH)

CRO and CRI define the serial bit rate. ENSI must be
set to logic 1 to enable SIOL If the AA bit is reset,
SIOI will not acknowledge its own slave address or the
general call address in the event of another device becoming master of the bus. In other words, if AA is reset,
SIOO can not enter a slave mode. STA, STO and SI
must be reset.
The master transmitter mode may now be entered by setting the STA bit using the SETB instruction. The SIOI
logic will now test the 12C bus and generate a start condition as soon as the bus becomes free. When a START
condition is transmitted, the serial interrupt flag (S1) is
set and the status code in the status register (SlSTA)
will be OSH. This status code must be used to vector to
an interrupt service routine that loads SlDAT with the
slave address and the data direction bit (SLA+W). The
S1 bit in Sl CON must then be reset before the serial
transfer can continue.

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8XC552

SUCCESSFUL TRANSMISSION
TO A SLAVE RECEIVER

NEXT TRANSFER STARTEO WITH
A REPEATEO START CONDITION

NOT ACKNOWLEDGE RECEIVED
AFTER THE SLAVE ADDRESS

TO MST/REC MODE
ENTRY. MR
NOT ACKNOWLEDGE RECEIVED
AFTER A DATA BYTE

ARBITRATION LOST IN SLAVE
ADDRESS OR DATA BYTE

ARBITRATION LOST AND
ADDRESSED AS SLAVE

TO CORRESPONDING STATES
IN SLAVE MODE

FROM MASTER TO SLAVE

FROM SLAVE TO MASTER

ANY NUMBER OF DATA BYTES
AND THEIR ASSOCIATED ACKNOWLEDGE BITS

THIS NUMBER (CONTAINED IN SlSTAI CORRESPONDS TO A
DEFINED STATE OF THE 12C·bus; See Table 9.

Figure 27. Format and States in the Master Transmitter Mode

February 1989

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8XC552

SUCCESSFUL RECEPTION
FROM A SLAve
TRANSMITTER

NEXT TRANSFER STARTED WITH
A REPEATED START CONDITION

NOT ACKNOWLEDGE RECEIVED
AFTER THE SLAVE ADDRESS

TO MST ITRX MODE
ENTRY -MT
ARBITRATION LOST IN SLAVE
ADDRESS OR ACKNOWLEDGE BIT

OTHER MST
CONTINUES

ARBITRATION LOST AND
ADDRESSED AS SLAVE

TO CORRESPONDING STATES
IN SLAVE MODE

FROM MASTER TO SLAVE

FROM SLAVE TO MASTER

r-;:;:~

ANY NUMBER OF DATA BYTES

L.::.:,,~ AND THEIR ASSOCIATED ACKNOWLEDGE BITS

THIS NUMBER (CONTAINED IN SISTAI CORRESPONDS TO A
DEFINED STATE OF THE 12C-bus; See Tabla 10.

Figure 28. Format and States in the Master Receiver Mode

February 1989

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RECEPTION OF THE OWN SLAVE
ADDRESS AND ONE OR MORE DATA
BYTES. ALL ARE ACKNOWLEDGED

LAST DATA BYTE RECEIVEO
IS NOT ACKNOWLEDGED

ARBITRATION LOST AS MST
AND ADDRESSED AS SLAVE

RECI:PTION OF THE GENERAL
CALL ADDRESS AND ONE OR
MORE DATA BYTES

LAST DATA BYTE IS NOT ACKNOWLEDGED

ARBITRATION LOST AS MST AND
ADDRESSED AS SLAVE BY GENERAL CALL

FROMMASTERTOSLAVE

FROM SLAVE TO MASTER

~~
8

[]
c§

ANY NUMBER OF DATA BYTES
AND THEIR ASSOCIATED ACKNOWLEDGE BITS

THIS NUMBER ICONTAINED IN SlSTAI CORRESPONDS TO A
DEFINED STATE OF THE 12C·bus; See Table 11.

Figure 29. Format and States in the Slave Receiver Mode

February 1989

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RECEPTION OF THE OWN
SLAVE ADDRESS AND TRANSMISSION
OF ONE OR MORE DATA BYTES

ARBITRATION LOST AS MST
AND ADDRESSED AS SLAVE
FROM MASTER TO SLAVE

FROMSLAVETOMASTER

~~
~~

LAST DATA BYTE TRANSMIITEO.
SWITCHED TO NOT ADDRESSED
SLAVE (AA BIT IN SICON 0'0'1

ANY NUMBER OF DATA BYTES
AND THEIR ASSOCIATED ACKNOWLEDGE BITS

THIS NUMBER (CONTAINED IN SISTAI CORRESPONDS TO A
DEFINED STATE OF THE 12C·bus; See Table 12.

Figure 30. Format and States of the Slave Transmitter Mode

When the slave address and the direction bit have been
transmitted and an acknowledgment bit has been received, the serial interrupt flag (SI) is set again and a
number of status codes in SlSTA are possible. There
are 18H, 20H or 38H for the master mode and also
68H, 78H, or BOH if the slave mode was enabled (AA =
logic 1). The appropriate action to be taken for each of
these status codes is detailed in Table 9. ENS1, CR1
and CRO are not affected by the serial transfer and are
not referred to in Table 9. After a repeated start condition (state lOH). SIal may switch to the master receiver
mode by loading SlDAT with SLA+R.

logic 1). The appropriate action to be taken for each of
these status codes is detailed in Table 10. ENS1, CR1
and CRO are not affected by the serial transfer and are
not referred to in Table 10. After a repeated start condition (state 10H), SIal may switch to the master transmitter mode by loading SlDAT with SLA+W.
Slave Receiver Mode
In the slave receiver mode, a number of data bytes are
received from a master transmitter (see Figure 29). To
initiate the slave receiver mode. SlADR and SlCON
must be loaded as follows:

Master Receiver Mode
In the master receiver mode, a number of data bytes are
received from a slave transmitter (see Figure 28). The
transfer is initialized as in the master transmitter mode.
When the start condition has been transmitted, the interrupt service routine must load SlDAT with the 7-bit
slave address and the data direction bit (SLA+R). The
SI bit in SlCON must then be cleared before the serial
transfer can continue.
When the slave address and the data direction bit have
been transmitted and an acknowledgment bit has been
received, the serial interrupt flag (SI) is set again and a
number of status codes in SlSTA are possible. These
are 40H, 48H or 38H for the master mode and also
68H, 78H, or BOH if the slave mode was enabled (AA =

February 1989

765
SlADR (DBH)

!Xlxlxlxlxlxlx!ocl
- - - own slave address - - -

The upper 7 bits are the address to which SIal will respond when addressed by a master. If the LSB (GC) is
set, SIal will respond to the general call address (OOR);
other wise it ignores the general call address.

SlCON (D8H)

2-70

210

Signetics Microprocessor Products

User's Guide

Section 2 - 8051 Derivatives

8XC552

Table 9. Master Transmitter Mode

Status
Status of the
Code
PC bus and
(SISTA) SIO 1 Hardware

Application Software Response
ToSICON

Next Action Taken by SIOI Hardware

To/From SlOAT
STA STO SI AA
08H

A START condition Load SLA+W
has been transmitted

SLA+W will be transmitted;
ACK bit will be received

10H

A repeated START
condition has been
transmitted

Load SLA+W or
Load SLA+R

X
X

0
0

X
X

As above
SLA+R will be transmitted;
SIOI will be switched to MST/REC
mode

18H

SLA+W has been
transmitted; ACK
has been received

Load data byte or

no SIDAT action or
no S I DAT action or

I
0

0
I

0
0

X
X

no SIDAT action

Data byte will be transmitted;
ACK bit will be received
Repeated START will be transmitted;
STOP condition will be transmitted;
STO nag will be reset
STOP condition followed by a
START condition will be transmitted;
STO flag will be reset

Load data byte or

no SIDAT action or
no SIDATaction or

I
0

0
I

0
0

X
X

no SIDAT action

Load data byte or

no SIDAT action or
no SIDAT action or

0
I

0
0

X
X

no SIDAT action

Load data byte or

no SIDAT action or
no SIDAT action or

I
0

0
1

0
0

X
X

no S I DA Taction

No S 1DA T action or

no SIDAT action

20H

28H

30H

38H

SLA+W has been
transmitted; NOT
ACK has been
received

Data byte in
SI DAT has been
transmitted; ACK
has been received

Data byte in
SIDAT has been
transmitted; NOT
ACK has been
received

Arbitration lost in
SLA+R/Wor
Data bytes

February 1989

2-71

Data byte will be transmitted;
ACK bit will be received
Repeated START will be transmitted;
STOP condition will be transmitted;
STO flag will be reset
STOP condition followed by a
START condition will be transmitted;
STO flag will be reset
Data byte will be transmitted;
ACK bit will be received
Repeated START will be transmitted;
STOP condition will be transmitted;
STO flag will be reset
STOP condition followed by a
START condition will be transmitted;
STO flag will be reset
Data byte will be transmitted;
ACK bit will be received
Repeated START will be transmitted;
STOP condition will be transmitted;
STO flag will be reset
STOP condition followed by a
START condition will be transmitted;
STO flag will be reset
PC bus will be released;
not addressed slave will be entered
A START condition will be
transmitted when the bus becomes free

Signetics Microprocessor Products

User's Guide

Section 2 - 8051 Derivatives

8XC552

Table 10. Master Receiver Mode

Status
Status of the
Code
PC bus and
(SISTA) SlOl Hardware

Application Software Response
ToSlCON

Next Action Taken by SlOl Hardware

To/From SlOAT
STA STO SI AA
08H

A START condition Load SLA+R
has been transmitted

SLA+R will be transmitted;
ACK bit will be received

IOH

A repeated START
condition has been
transmitted

Load SLA+R or
Load SLA+W

X
X

0
0

X
X

As above
SLA+W will be transmitted;
Sial will be switched to MST/TRX
mode

38H

Arbitration lost in
NOT ACK bit

No Sl DAT action or

no SlDAT action

FC bus will be released;
SI01 will enter a slave mode
A START will be transmitted when
the bus becomes free

No SlDAT action or

no Sl DAT action

No S 1DA T action or

no S 1DA T action or

no SI DA Taction

Data byte has been
received; ACK has
been returned

Read data byte or

read data byte

Data byte has been
received; NOT ACK
has been returned

Read data byte or

read data byte or

read data byte

40H

48H

50H

58B

SLA+R has been
transmitted; ACK
has been received
SLA+R has been
transmitted; NOT
ACK has been
received.

February 1989

2-72

Data byte will be received;
NOT ACK bit will be returned
Data byte will be received;
ACK bit will be returned
Repeated START condition will be
transmitted
STOP condition will be transmitted;
STO flag will be reset
STOP condition followed by a
START condition will be transmitted;
STO flag will be reset
Data byte will be received;
NOT ACK bit will be returned
Data byte will be received;
ACK bit will be returned
Repeated START condition will be
transmitted
STOP condition will be transmitted;
STO flag will be reset
STOP condition followed by a
START condition will be transmitted;
STO flag will be reset

Signetics Microprocessor Products

User's Guide

Section 2 - 8051 Derivatives

8XC552

Table 11. Slave Receiver Mode
Statu. of the I'C bus
Status
and 510 I Hudware
Code
(SISTA)

Application Softwue IlelPOnle
Next Action Taken by SI01 Hudwue

ToSICON
To/From SIDAT
STA STO SI AA

60H

Own SLA+W has been
received; ACK has been
returned

No SIDATaction or
no S I DATaction

X
X

0
0

0
I

Data byte will be received and NOT ACK will be returned
Data byte will be received and ACK will be returned

68H

Arbitration lost in SLA+RtW No SIDAT action or
as master; Own SLA+W has no SIDAT action
been received, ACK returned

X
X

0
0

0
I

Data byte will be received and NOT ACK will be returned
Data byte will be received and ACK will be returned

70H

General call address (OOH)
has been received; ACK has
been returned

No S I DA T action or
no SIDATaction

X
X

0
0

0
I

Data byte will be received and NOT ACK will be returned
Data byte will be received and ACK will be returned

78H

Arbitration lost in SLA+R/W No SIDAT action or
as master; General call
no SIDAT action
address has been received;
ACK has been returned

X
X

0
0

0
I

Data byte will be received and NOT ACK will be returned
Data byte will be received and ACK will be returned

80H

Previously addressed with
own SLY address; DATA
has been received; ACK has
been returned

Read data byte or
read data byte

X
X

0
0

0
I

Data byte will be received and NOT ACK will be returned
Data byte will be received and ACK will be returned

88H

Previously addressed with
own SLA; DATA byte has
been received; NOT ACK
has been returned

Read data byte or

Switched to not addressed SLV mode; no recognition
of own SLA or General call address
Switched to not addressed SLV mode; Own SLA will
be recognized; General call address will be recognized
if SIADR. 0 =logic I
Switched to not addressed SLV mode; no recognition
of own SLA or General call address. A START
condition will be transmitted when the bus becomes free.
Switched to not addressed SLV mode; Own SLA will
be recognized; General call address will be recognized
if SIADR. 0 =logic 1. A START condition will be
transmitted when the bus becomes free.

read data byte or

read data byte

Read data byte or
read data byte

X
X

0
0

0
I

Data byte will be received and NOT ACK will be returned
Data byte will be received and ACK will be returned

Switched to not addressed SLY mode; no recognition
of own SLA or General call address
Switched to not addressed SLY mode; Own SLA will
be recognized; General call address will be recognized
if SIADR. 0 =logic I
Switched to not addressed SLV mode; no recognition
of own SLA or General call address. A START
condition will be transmitted when the bus becomes free.
Switched to not addressed SLV mode; Own SLA will
be recognized; General call address will be recognized
if SIADR. 0 =logic 1. A START condition will be
transmitted when the bus becomes free.

90H

Previously addressed with
General Call; DATA byte
has been received; ACK has
been returned

98H

Previously addressed with
Read data byte or
General Call; DATA byte
has been received; NOT ACK read data byte or
has been returned

AOH

A STOP condition or
repeated START condition
has been received while still
addressed as SLV/REC or
SLV/TRX

February 1989

read data byte or

read data byte

Read data byte or

read data byte or

read data byte

2-73

Switched to not addressed SLY mode; no recognition
of own SLA or General call address
Switched to not addressed SLY mode; Own SLA will
be recognized; General call address will be recognized
if SIADR. 0 =logic I
Switched to not addressed SLV mode; no recognition
of own SLA or General call address. A START
condition will be transmitted when the bus becomes free.
Switched to not addressed SLY mode; Own SLA will
be recognized; General call address will be recognized
if SIADR. 0 =logic 1. A START condition will be
transmitted when the bus becomes free.

User's Guide

Signetlcs Microprocessor Products

8XC552

Section 2 - 8051 Derivatives
Table 12. Slave Transmitter Mode
Statu.
Statu. of the PC bu.
Code
and SIOI Hudwue
(SISTA)

Application Software ReapOOIle
ToSICON

Next Action Taken by SIOI Hudwue

To/prom SIDAT
STA STO SI AA
ASH

DOH

Own SLA+R has been

Load data byte or

received; ACK bas been
returned

load data byte

Arbitration lost in SLA+R/W Load data byte or
as master; own SLA+R has
been received; ACK has been load data byte
returned

Last data byte will be transmitted and
ACK bit will be received
Data byte will be transmitted; ACK bit will be received
Last data byte will be transmitted and
ACK bit will be received
Data byte will be transmitted; ACK bit will be received

B8H

Data byte in SlOAT has
been transmitted; ACK has
been received

Load data byte or
load data byte

X
X

0
0

0
I

Last data byte will be transmitted and ACJ\ bi .. will be
received Data byt~ will be tr.nsmilt~d: ACJ\ bit will be
received

COH

Data byte in SlOAT bas
been transmitted; NOT
ACK has been received

No SIDAT aetion or

no SIOATaetion or

no S I OAT action or

no S I OAT action

Switched to not addressed SLY mode; no recognition
of own SLA or General call address
Switched to not addressed SL V mode; Own SLA will
be recognized; General call address will be recognized
if SIADR. 0 =logic I
Switched to not addressed SLY mode; no recognition
of own SLA or General call address. A START
condition will be transmitted when the bus becomes free.
Switched to not addressed SLV mode; Own SLA will
be recognized; General call address will be recognized
if SIADR. 0 =logic I. A START condition will be
transmitted when the bus becomes free.

No SIDAT action or

no SlOAT action or

no S IDAT action or

no SlOAT action

CSH

Last data byte in SlDAT
hal been transmitted
(AA =0); ACK has been
received

CRO and CR1 do not affect SI01 in the slave mode.
ENS1 must be set to logic 1 to enable SIOl. The AA bit
must be set to enable SI01 to acknowledge its own slave
address or the general call address. STA, sm and SI
must be reset.

Switched to not addressed SLV mode; no recognition
of own SLA or General call address
Switched to not addressed SLV mode; Own SLA will
be recognized; General call address will be recolnized
if SIADR. 0 =logic I
Switched to not addressed SLV mode; no recognition
of own SLA or General call address. A START
condition will be transmitted when the bus becomes free.
Switched to not addressed SLV mode; Own SLA will
be recognized; General can address will be recolnized
If SIADR. 0 -lope I. A START condition will be
transmitted when the bUI becomes free.

However, the I2C bus is still monitored and address recognition may be resumed at any time by setting AA. This
means that the AA bit may be used to temporarily isolate SI01 from the I2C bus.
Slave Transmitter Mode

When SlADR anq SlCON have been initialized, SI01
waits until it is addressed by its own slave address followed by the data direction bit which must be '0' (W) for
SI01 to operate in the slave receiver 'mode. After its
own slave address and the W bit have been received, the
serial interrupt flag (I) is set and a valid status code can
be read fromS1STA. This status code is used to vector
to an interrupt service routine and the appropriate action
to be taken for each of these status codes is detailed in
Table 11. The slave, receiver mode may also be entered
if arbitration is lost while SI01 is in the master mode
(see status 68H and 78H);
If the AA bit is reset during a transfer ,SI01 will return
a not acknowledge (logic 1) to SDA after the next received data byte. While AA is reset, SI01 does not respond to its own slave address or a general call address.

February 1989

In the slave transmitter mode, a number of data bytes
are transmitted to a master receiver (see Figure 30).
Data transfer is initialized as in the slave receiver mode.
When SlADR and SlCON have been initialized, SI01
waits until it is addressed by its own slave address followed by the data direction bit which must be '1' (R) for
SI01 to operate in the slave transmitter mode. After its
own slave address and the R bit have been received, the
serial interrupt flag (SI) is set and a valid status code
can be read from SlSTA. This status code is used to
vector to an interrupt service routine and the appropriate
action to be taken for each of these status codes is detailed in Table 12. The slave transmitter mode may also
be entered if arbitration is lost while SI01 is in the master mode (see state BOH).

2-74

User's Guide

Signetics Microprocessor Products

8XC552

Section 2 - 8051 Derivatives
If the AA bit is reset during a transfer, SIal will transmit the last byte of the transfer and enter state COH or
C8H. SIal is switched to the not addressed slave mode
and will ignore the master receiver if it continues the
transfer. Thus the master receiver receives all 1s as serial data. While AA is reset, SIal does not respond to
its own slave address or a general call address. However, the 12C bus is still monitored and address recognition may be resumed at any time by setting AA. This
means that the AA bit may be used to temporarily isolate SIal from the I2C bus.

set. To recover from a bus error, the STO flag must be
set and SI must be cleared. This causes SIal to enter
the 'not addressed' slave mode (a defined state) and to
clear the STO flag (no other bits in SlCON are affected). The SDA and SCL lines are released (a STOP
condition is not transmitted).
The Four SI01 Special Function Registers
The microcontroller interfaces to SIal via four special
function registers. These four SFR's (SlADR, SlDAT,
SlCON and SlSTA) are described individually in the following sections.

Miscellaneous States

The Address Register, S1ADR

There are two SlSTA codes that do not correspond to a
defined SIal hardware state (see Table 13). These are
discussed below.

The CPU can read from and write to this 8-bit, directly
addressable SFR. SlADR is not affected by the SIal
hardware. The contents of this register are irrelevant
\Wen SIal is in a master mode. In the slave modes, the
seven most significant bits must be loaded with the
microcontroller's own slave address and, if the least significant bit is set, the general call address (OOH) is recognized; otherwise it is ignored.

SlSTA - F8H:
This status code indicates that no relevant information is
available because the serial interrupt flag, SI is not yet
set. This occurs between other states and when SIal is
not involved in a serial transfer.

SlSTA - OOH:
SlADR (DBH)
This status code indicates that a bus error has occurred
during an SIal serial transfer. A bus error is caused
\Wen a START or STOP condition occurs at an illegal
position in the format frame. Examples of such illegal
positions are during the serial transfer of an address
byte, a data byte or an acknowledge bit. A bus error may
also be caused when external interference disturbs the
internal SIal signals. When a bus error occurs, SI is

321

Ixlxlxlxlxlxlxlocl
- - - own slave address - - -

The most significant bit corresponds to the first bit received from the 12C bus after a start condition. A logic
1 in SlADR corresponds to a high level on the I2C bus
and a logic 0 corresponds to a low level on the bus.

Table 13. Miscellaneous States

Status
Status of the
Code
PC bus and
(SISTA) SIOI Hardware

Application Software Response
ToSICON

Next Action Taken by SlOt Hardware

To/From SlOAT
STA STO SI AA

F8H

No relevant state
information
available; Sl = 0

No SIDAT action

OOH

Bus error during
MST or selected
slave modes, due to
an illegal START or
STOP condition.
State DOH can also
occur when
interf"rence causes
SI01 to enter an
undefined state.

No SIDAT action

February 1989

No SICON action

2-75

Wait or proceed current transfer.

Only the internal hardware is affected
in the MST or addressed SL V modes.
In all cases, the bus is released and
SIOI is switched to the not addressed
SLY mode. STO is reset.

User's Guide

Signetics Microprocessor Products

8XC552

Section 2 - 8051 Derivatives
The Data RegIster, SIDAT
SIDAT contains a byte of serial data to be transmitted
or a byte which has just been received. The CPU can
read from and write to this 8-bit, directly addressable
SFR while it is not in the process of shifting a byte. This
occurs when SIOI is in a defined state and the serial interrupt flag is set. Data in SlDAT remains stable as
long as SI is set. Data in SlDAT is always shifted from
right to left: the first bit to be transmitted is the MSB
(bit 7) and, after a byte has been received, the first bit
of received data is located at the MSB of SlDAT. While
data is being shifted out, data on the bus is simultaneously being shifted in; SlDAT always contains the last
data byte present on the bus. Thus, in the event of lost
arbitration, the transition from master transmitter to
slave receiver is made with the correct data in SlDAT.
7

654

210

SlDAT (DAH) ISD7ISD6ISD5ISD4ISDJISDZISDlISDOI
~--- shift direction - - - - -

Serial data is shifted out from SlDAT via a buffer
(BSD7) on the falling edges of clock pulses on the SCL
line.
When the CPU writes to SlDAT, BSD7 is loaded with
the content of SlDAT.7 which is the first bit to be
transmitted to the SDA line (see Figure 32). After nine
serial clock pulses, the eight bits in SlDAT will have
been transmitted to the SDA line and the acknowledge
bit will be present in ACK. Note that the eight transmitted bits are shifted back into SlDAT.
The Control RegIster, SICON
The CPU can read from and write to this 8-bit, directly
addressable SFR. The most significant bit is not used
and a logic 1 will be returned if SlCON.7 is read. Two
bits are affected by the SIOI hardware: the SI bit is set
\ 100pF). the noise pulse on the ALE pin may exceed o.av. In such cases, it may be desirable to

3.
4.
5.

qualify ALE with a Schmitt Trigger. or use an address latch with a Schmitt Trigger STROBE input.
Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the O.9VCC specification when the
address bits are stabilizing.
Pins of ports 1 (except P1.6, P1.7), 2,3 and 4 source a transition current when they are being externally driven from 1 to O. The transition
current reaches its maximum value when VIN is approximately 2V.
See Figures 8 throug h 11 for ICC test conditions.

The input threshold voltage of P1.6 and P1.7 (SI01) meets the 12C specification. so an input voltage below 1.5V will be recognized as a log-

7.
8.

The following condition must not be exceeded: VCC - 0.2V < AVcc < VCC + 0.2V.
Conditions: AVREF- - OV; AVCC - 5.0V. AVREF+ - 5.12V. ADC is monotonic with no missing codes.

This should be considered when both analog and digital sig nals are simultaneously input to port 5.

ic 0 while an input voltage above 3.0V will be recognized as a logic 1.

February 1989

2-117

Product Specification

Signetics Microprocessor Products

S83C552/S80C552

Single-Chip 8-Bit Microcontroller

AC ELECTRICAL CHARACTERISTICS TA - O°C to +70°C, VCC. AVcc - 5V ±1 0%. Vss. AVss - OV
SYMBOL

VARIABLE CLOCK

12MHz CLOCK

PARAMETER

FIGURE

Min

Max

Min

Max

1.2

UNIT

Program Memory
MHz

l/tCLCL

Oscillator frequency

tLHLL

ALE pulse width

127

2tci CI -40

tAVLL

Address valid to ALE low

tCLCL -55

tLLAX

Address hold after ALE low

tLLlV

ALE low to valid instruction in

tLLPL

ALE low to PSEN low

tpLPH

PSEN pulse width

tp IV

PSEN low to valid instruction in

tpXIX

Input instruction hold after PSEN

tpxIZ

Input instruction float after PSEN

tAVIV

Address to valid instruction in

PSEN low to address float

tp.AZ
Data Memory

tr.1 C -35
234

4tCLCL -100

tr.1 r.1 -40

205

3tCLCL -45

ns
3tci CI -105

145

ns
ns

0
59

tr.lr.I-25

312

5tCLCL-l05
10

tAvLL

2, 3

Address valid to ALE low

tCLCL -40

tRLRH

2,3

RD pulse width

400

6tCLCL -100

tWLWH

2, 3

WR pulse width

400

6tci cr-1OO

tRLDV

2, 3

RD low to valid data in

tRHDX

2, 3

Data hold after RD

tRHDZ
t .DV

2, 3

Data float after RD

2. 3

ALE low to valid data in

tAVDV

2, 3

Address to valid data in

t LWL

2. 3

ALE low to RD or WR low

200

tAVWL

2. 3

Address valid to WR low or RD low

203

4tCLCL -130

tOVWX

2. 3

Data valid to WR transition

tWHOX

2, 3

Data hold after WR

"'" r.1 -60
tCLCL -50

tRiAZ

2. 3

RD low to address float

2, 3
tWHLH
External Clock
5
tCHCX

ns
ns

517

2tCLCL-70
8tr.1 r.1 -150

585

9tCLCL -165

3tr.1 r.1 +50

300

3tr.1 r.1 -50

12
43

RD or WR high to ALE high

ns
5tCLCL-165

252

123

tCLCL -40

ns
12

tCLCL+40

High time 3

tCLCX

Low time 3

tCLCH

Rise time3

Fall time 3

tXLXL

Serial port clock cycle time 3

1.0

12tCLCL

tOVXH

Output data setup to clock rising edge 3

700

1OtCLCL-133

tXHQX

Output data hold after clock rising edge 3

2tCLCL -117

tXHDX

Input data hold after clock rising edge 3

tXHDV

Clock rising edge to input data valid 3

tCHCL
Shift Register

0
700

NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.

2. Load capacitance for port 0, ALE, and PSEN - 100pF. load capacitance for all other outputs - 80pF.
3. These values are characterized but not 100% production tested.

February 1989

2-118

fLS

ns
1OtCLCL -133

Product Specification

Signetics Microprocessor Products

S83C552/S80C552

Single-Chip 8-Sit Microcontroller
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has five characters. The first character is
always 't' (- time). The other characters, depending on their
positions, indicate the name of a signal or the logical status of
that signal. The designations are:
A - Address
C - Clock
o - I nput data
H - Logic level high
I - Instruction (program memory contents)
L - Logic level low, or ALE

P- PSEN
Q - Output data

R - RD signal
t - Time
V - Valid
W - WR signal
X - No longer a valid logic level
Z - Float
Examples: tAVLL - Time for address valid to ALE low.
tLLPL - Time for ALE low to PSEN low.

ALE

PORTO

PORT 2 _ _ _ _oJ'

Figure 1. External Program Memory Read Cycle

ALE

PORTO

PORT 2 _ _ _./

I'-------------------J
Figure 2. External Data Memory Read Cycle

February 1989

2-119

Product Specification

Signetics Microprocessor Products

S83C552/S80C552

Single-Chip 8-Bit Microcontroller

ALE

--~~-----IWlWH'------~

'OVWX
PORTO

DATA OUT

PORT 2

P2.0-P2.? OR A8-A15 FROM DPH

AD-A? FROM PCl

A8-A15 FROM PCH

Figure 3. External Data Memory Write Cycle

INSTRUCTION

ALE

'OVXH
OUTPUT DATA

'XHOX

\'--_~ '-_~ '--_~ '-_---' '--_..J ' - _ - - I '--_..J '-_--.J

WRITE TO SBUF
I INPUT DATAl _ _ _ _ _ _ _J

CLEAR RI

SET RI

Figure 4. Shift Register Mode Timing

February 1989

2-120

Signetics Microprocessor Products

Product Specification

Single-Chip 8-Bit Microcontroller

S83C552/S80C552

O.45V

~---------tCLCL--------~

Figure 5. External Clock Drive

Vcc-O.5
0.45V

O.2Vcc+O.9

Timing
Reference
Points

_,-O",.",2V.;.,c",c,--..;.O",.1_ __

AC inputs during testing are driven at Vcc-0.5
for a logic "1" and 0.45V for a logic '0".
Timing measurements are made at VIH min for
a logic "1" and V IL max for a logic "0".

For timing purposes, a port is no longer floating
when a 100mV change from load voltage occurs,
and begins to float when a 100mV change from
the 10adedVoHIVOL level occurs.IOH/lOL~±20mA.

Figure 6. AC Testing Input/Output

Figure 7. Float Waveform

()

Q
15

MAX ACTIVE MODE

/
/
VV

TYP ACTIVE MODE

:::::::. ~ I---I - -

MAX IDLE MODE
TYP IDLE MODE

4MHz 8MHz 12MHz 16MHz

FREQ AT XTAL1

Figure 8. Icc vs. FREQ
Valid only within frequency specifications of the device under test.
Maximum values taken at Vcc = 5.5V and worst case temperature.
Typical Values taken at Vcc = 5.0V and 25°C.

February 1989

2-121

Signetics Microprocessor Products

Product Specification

S83C552/S80C552

Single-Chip 8-Bit Microcontroller

Vee
...-_ _ _ _-;Iee

Vee

!
Vee

RST
RST

(NC)
CLOCK
SIGNAL

XTAL2
XTALI
Vss

CLOCK (NC)
SIGNAL

XTAL2
XTAL1
Vss

Figure 10. Icc Test Condition, Idle Mode
All other pins are disconnected

Figure 9. Icc Test Condition, Active Mode
All other pins are disconnected

0.45V

~--------tCLCL----------~

Figure 11. Clock Signal Waveform for Icc Tests in Active and Idle Modes
tCLCH
tCHCL
5ns

Vee
...-_ _ _ _-;Iee
Vee

1
Vee

RST

(NC)

XTAL2
XTAL1
Vss

Figure 12. Icc Test Conditions, Power Down Mode
All other pins are disconnected. VCC = 2V to 5.5V

February 1989

2-122

User's Guide

Signetics Microprocessor Products

Section 2 - 8051 Derivatives

8XC652

8XC652 OVERVIEW
The SXC652 is a derivative of the 80C51 8-bit CMOS
microcontroller. The 8XC652 contains all of the features
of the 80C51 (that is the standard counter/timers TO and
Tl, the standard serial I/O (UART) , and four 8-bit 110
ports). In addition, the 8XC652 has the following:

The organization of the data memory is similar to the
80C51 except that the SXC652 has an additional 128
bytes of RAM overlapped with the special function register space. This additional RAM is addressed using indirect addressing only and is available as stack space.
(This memory addition is the same as in the S052 and
83C552. See Figure 59 for a memory map.)
Special Function Registers

• 8K bytes of ROM
• 256 bytes of RAM
• I2C bus serial 110
The 8XC652 is pin-for-pin compatible and fully code
compatible with the SOC5l. There are some differences
in the Pl.6 and Pl.7 pin functions that are described in
detail" later in this section. All of the 80C5l functions
are present including the external 64K program and data
memory expansion, Boolean processing, and two reduced
power modes.
Differences from the 80C51
The data and program memory are organized similar to
the SOC51. The 8XC652 program memory differs in that
it has 8K bytes of on-chip ROM. When EA is high the
8XC652 fetches instructions from the internal ROM unless the address exceeds 1FFFH. Locations 2000H to
FFFFH~re fetched from external program memory.
When EA is held low, all instruction fetches are from
external memory.

The 8XC6S2 special function register space is the same
as that on the 80C5l except that it contains four additional SFRs. The added registers are: SlCON, S1STA,
S1DAT, and SlADR. In addition to these the standard
UART special function registers, SCaN and SBUF have
been renamed SOCON and SOBUF for clarity.
Since the standard 80CSl on-chip functions are the same
on the 8XC652, the SFR locations, bit locations, and operation are unchanged. The only exception is in the interrupt enable and interrupt priority SFRs. These have
been changed to include the interrupt from the I2C serial port. Table 19 shows the special function registers,
their direct address, the bit addresses, and the value in
the register after a reset.

64K
64K .....- - - - ,

EXTERNAL

8192

819 1

t
8191

INTERNAL

EXTERNAL

lEA-II

IEA-OI

255

r----..::.,

127

-----INTERNAL
DATA RAM

PROGRAM MEMORY

INTERNAL
DATA MEMORY

FIgure 59. Memory Map

February 1989

0'------'

'---v-----'

2-123

EXTERNAL
DATA
MEMORY

Signetics Microprocessor Products

User's Guide

Section 2 - 8051 Derivatives

8XC652

Table 19. 8XC652 Special Function Registers
Symbol

Description

Direct
Address
EOH
FOH

ACC·
B'
DPTR:
DPH
DPL

Accumulator
B register
Data pointer (2 bytes):
Data pointer high
Data pointer low

IE'

Interrupt enable

A8H

Ip·

Interrupt priority

B8H

PO'

Port 0

80H

PI •

Port 1

90H

P2'

Port 2

AOH

P3'
PCON

Port 3
Power control

BOH
87H

83H
82H

SOCON*# Serial 0 port control
SOBUF# Serial 0 data buffer

98H
99H

PSW'
SlDAT#
SP
SIADR#

Program status word
Serial 1 data
Stack pointer
Serial 1 address

DOH
DAH
81H
DBH

SISTA#

Serial 1 status

D9H

SICON*# Serial 1 control

Bit Address, Symbol or Alternative Port Function
Reset Value
MSB
LSB
E7
E6
ES
E4
E3
E2
El
EO OOH
F7
F6
FS
F4
F3
F2
Fl
FO OOH

D8H

OOH
OOH
AC
AB
AA
A9
A8
ESO I ETl I EXI I ETO I ETl OXOOOOOOB
BD
BC
BB
BA
B9
B8
I PSI I PSO I PTl I PXl I PTO I PXO xxOOOOOOB
85
84
82
81
80
83
I ADS I AD4 I AD3 I AD2 I ADI I ADO FFH
95
94
92
91
90
93
I
FFH
I
I
I
I
I
AS
A4
A3
A2
Al
AO
I A13 I A12 I All I AlO I A9 I A8 FFH
BS
B4
B3
B2
Bl
BO
I Tl I TO I INTlI INTO I TXD I RXD FFH
I I GFI I GFOI PD I IDL OxxxOOOOB
I 9D
9C
9B
9A
99
98
I SM2 I REN I TBB I RBB I TI I RI OOH
xxxxxxxxB
D6
DS
D4
D3
D2
Dl
DO
AC I FO I RSI I RSO I OV I FI I P
OOH
OOH
07H
SLAVE ADDRESS
I GC OOH

AF
AE
EAl
BF
BE
- I
87
86
AD7 I AD6
97
96
SDAj SCL
A7
A6
AlSj A14
B7
B6
RD I WR
SMODl 9F
9E
SMO I SMI
D7
CY

SC4l SC3 I
DF
DE
- lENSll
8F
8E
TFI I TRI I

TCON*
Timer control
88H
THI
Timer high 1
8DH
THO
Timer high 0
8CH
TLl
Timer low 1
8BH
TLO
Timer low 0
8AH
TMOD
Timer mode
89H
GATEJ CIT
* = SFRs are bit addressable
# = SFRs are modified from or added to the 80CSI SFRs.
I2C Serial Communication - SIOI
The I2C Serial port is identical to the I2C serial port on
the 83C552. The operation of this subsystem is described
in detail in the 83C5S2 section of this manual.
Note that in both the 8XC6S2 and the 83CS52 the I2C
pins are alternate functions to port pins PI.6 and PI.7.
Because of this PI.6 and PI. 7 on these parts do not have
a pull-up structure as found on the 80CSI. Therefore
PI.6 and PI.7 have open drain outputs on the 8XC652.
Idle and Power-down Operation
Idle mode operation permits the interrupt, serial ports,

February 1989

I ESI I

SC2 I SCI I SCO I 0 I 0 I 0
F8H
DD
DC
D9
DB
DA
D8
STA I STO I SI I AA I CRI I CRO xOOOOOOOB
8D
8C
8B
8A
89
88
TFO I TRO I IEl I ITl I IEO I ITO OOH
OOH
OOH
OOH
OOH
Ml I MO IGATE I CIT I Ml I MO OOH

and timer blocks to continue to function while the CPU
is halted. The following functions remain active during
idle mode. These functions may generate an interrupt or
reset and thus end the idle mode:
- Timer O. Timer 1
- SIoO. SIOl
- External interrupt
In idle mode. port pins PI.6 and PI.7 function as SCL
and SDA respectively if the I2C serial port is enabled.
The power-down operation freezes the oscillator. TIle
power-down mode can only be activated by setting the
PD bit in the PCON register. The power-down mode in
the 8XC6S2 operates exactly the same as in the 80CSl.

2-124

Signetics Microprocessor Products

User's Guide

Section 2 - 8051 Derivatives

8XC652

Interrupt System
The interrupt system is the same as in the 80C51 except
that the 8XC652 acknowledges interrupt requests from
six sources as follows:

Both external interrupts can be programmed to be levelactivated or transition-activated; an active LOW level allows "Wire-ORing" of several input sources to the input
pin.
Each interrupt source can be set for either high priority
or low priority. If two separate interrupts are requested
simultaneously the processor will branch to the vector
associated with the interrupt that has the higher priority.
If there are simultaneous requests from sources that
have the same priority, then the interrupts will be serviced in the following order:

INTO external interrupt 0
INTI external interrupt I
Timer 0 overflow
Timer I overflow
I2C serial I/O interrupt
- UART serial I/O interrupt
-

See Figure 60 for a function diagram of the 8XC652 interrupt structure. Each interrupt vectors to a separate
location in program memory for its service program.
Each source can be individually enabled or disabled by a
corresponding bit in the IE register, moreover each interrupt may be programmed to a high or low priority
level using a corresponding bit in the IP register. Also
all enabled sources can be globally disabled or enabled.

I
2
3
4
5
6

INTO external interrupt 0
12C serial I/O interrupt
Timer 0 overflow
INTI external interrupt I
Timer I overflow
UART serial 1/0 interrupt

interrupt enable register
interrupt

sources

~
5101
INT

EXTERNAL
INTERRUPT
REQUEST 0
12C
SERIAL PORT

INTERNAL
TIMER
0

5100

iNT

source enable

global enable

interrupt priority
register
0-

f--

......n.

"""'0- f--

.......

"""'0- f--

f--

r--

""0- t--

EXTERNAL
INTERRUPT
REQUEST 1

.......

""'0- r-

INTERNAL
TIMER
1

.......

""'0- t--

.......

..........

INTERNAL iT
SERIAL
>PORT
:R

~o-

rr-t--

Figure 60. Interrupt System

February 1989

2-125

User's Guide

Signetics Microprocessor Products

Section 2 - 8051 Derivatives

8XC652

A low priority interrupt routine can be interrupted by an
interrupt having a higher priority. A high priority interrupt can not be interrupted. All of the features of the
SXC6S2 that have not been discussed in this section are
the same as those on the SOCSl.

Interrupt Priority Register

Interrupt Enable Register

Bit
IP.7
IP.6
IP.S
IP.4
IP.3
IP.2
IP.1
IP.O

7
IE (ASH)
Bit
1E.7

1E.6
IE.S
1E.4
1E.3
1E.2
IE.I
IE.O

lEAl Symbol
EA

ES1
ESO
ETl
EXI

ETO
EXO

February 1989

IESIIESOIETlIEX11ETOIEXOI

Fnnction
General enable/disable control
o = No interrupt enabled
I = Any individually enabled
interrupt will be accepted
Unused
Enable SI01 (I2C) interrupt
Enable SIOO (UART) interrupt
Enable timer I interrupt
Enable external 1 interrupt
Enable timer 0 interrupt
Enable external 0 interrupt
o = interrupt disabled
1 = interrupt enabled

IP (BSH)
Symbol

PSI
PSO
PTl
PXI
PTO
PXO

I -

IpS11pSOlpTllpX11PTOlpXOI

Function
Unused
Unused
SI01 (DC) interrupt priority level
SIOO (UART interrupt priority level
Timer 1 interrupt priority level
Enable interrupt I priority level
Timer 0 interrupt priority level
External interrupt 0 priority level
o = Low priority
1 = High priority

The following vectors indicate the ROM location where
the appropriate interrupt service routine starts.
Source
External 0 (XO)
Timer 0 overflow (TO)
External I (Xl)
Timer I overflow (Tl)
Serial I/O 0 (UART) (SO)
Serial I/O I (I2C) (Sl)

2-126

Vector
0003H
OOOBH
0013H
OOlBH
0023H
002BH

Signetics

S83C652/S80C652
CMOS Single-Chip 8-Bit
Microco ntro lIer
Product Specification

Microprocessor Division

DESCRIPTION
The SB3C652/SBOC652 Single-Chip B-Bit
Microcontroller is manufactured in an
advanced CMOS process and is a derivative of the SCBOC51 microcontroller
family. The SB3C652/SBOC652 has the
same instruction set as the BOC51. Two
versions of the derivative exist:
o SB3C652 - BK bytes mask programmable ROM, 256 bytes RAM
o SBOC652 - ROM less version of the
SB3C652
This device provides architectural enhancements that make it applicable in a
variety of applications for general control
systems. The SB3C652 contains a nonvolatile BK x B read-only program memory, a volatile 256 x B read/write data
memory, four B-bit I/O ports, two 16-bit
timer/event counters (identical to the
timers of the S80C51), a multi-source,
two-priority-level, nested interrupt structure, an 12C interface, UART and on-chip
oscillator and timing circuits. For systems
that
require
extra
capability,
the
SB3C652 can be expanded using standard TIL compatible memories and logic.
The device also functions as an arithmetic processor having facilities for both
binary and BCD arithmetic plus bit-handling capabilities. The instruction set
consists of over 100 instructions: 49 onebyte, 45 two-byte and 17 three-byte.
With a 12MHz crystal, 5B% of the instructions are executed in 1J.1S and 40%
in 2J.1S. Multiply and divide instructions
require 4J.1S.

FEATURES
• SC80C51 central processing
unit
• 8K x 8 ROM, expandable
externally to 64K bytes
.256 x 8 RAM, expandable
externally to 64K bytes
• Two standard 16-bit timerl
counters
• Four 8-bit I/O ports
• 12C-bus serial I/O port with
byte oriented master and slave
functions
• Full-duplex UART facilities

P1.0;:!;

'40 Vee

P1.1~

~PO.O/ADO

P1.2 3

38 PO.1 / AD1

P1.3~

~7 PO.2/AD2

P1.4~

~ PO.3/AD3

P1.5 B

35 P0.4/AD4

SCL/P1.B~

~ PO.5/AD5

SDA/P1.7~

~ PO.B/ADB

RST 9

32 PO.7/AD7

RXD/DATA/P3.0~
TxD/CL~P3.1~
I~P3.2.g
INT1/P3.3~
TO/P3.4 ~

DIP

' ; EA

~ALE
~ Ps"EN

I¥s P2.7/A15

~ P2.6/A14

22.!P3.5 ~

~ P2.5/ A 13

~/P3.6~

~P2.4/A12

RD/P3.7 ~

~4 P2.3/A11

XTAL2~

~ P2.2/A10

XTAL1~

gP2.1/A9

Vss~

~ P2.0/AS
L-_--J-

TOP VIEW
INDEX

,o"~ ,,:' ~r"
29

LOGIC SYM BOL

TOP VIEW

V.Vee RST

)0:::~~-)e~~
~~

_SCL

_SDA

RXD/DATA
D/CLOCK

Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

17
18
19
20
21
22

February 1989

PIN CONFIGURATION

2-127

Function
NC
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
SCL/P1.6
SDA/P1.7
RST
RxD/DAT AlP3.0
NC
TxDIICLOCK/P3.1
rnTO/P3.2
iNTi/P3.3
TO/P3.4
T1/P3.5
Wl\/P3.6
lm/P3.7
XTAL2
XTAL1
Vss

Pin
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44

Function
NC
P2.0/AS
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
~
ALE
NC

PO.7/AD7
PO.B/AD6
PO.5/AD5
PO.4/AD4
PO.3/AD3
PO.2/AD2
PO.1/AD1
PO.O/ADO
Vee

95544

Product Specification

Signetics Microprocessor Products

S83C652/S80C652

CMOS Single-Chip 8-Bit Microcontroller
S8

C852-

1
C CC

PART NUMBER SELECTION

Custom ROM Pattern No.
Applies to masked ROM versions
only. Number will be assigned by
Signetics. Contact Signetics
sales office for ROM pattern submission requirements.

Temperature and Package

Frequency

S80C652-1 N40

S83C652-1 N40

1.2 to 12MHz

S80C652-1 A44

S83C652-1A44

o to +70 0 C plastic DIP
o to +70 0 C plastic LCC

1.2 to 12MHz

S80C652-2N40

S83C652-2N40

-40 to +85 0 C plastic DIP

1.2 to 12MHz

Package and Pins

S80C652-2A44

S83C652-2A44

-40 to +85°C plastic LCC

1.2 to 12MHz

A44 - 44-Pin Plastic LCC
N40 - 40-Pin Plastic DIP

S80C652-4N40

S83C652-4N40

1.2 to 16MHz

S80C652-4A44

S83C652-4A44

o to +70°C plastic DIP'
o to +70°C plastic LCC'

S80C652-5N40

S83C652-5N40

-40 to +85°C plastic DIP'

1.2 to 16MHz

S80C652-5A44

S83C652-5A44

-40 to +85 0 C plastic LCC' 1.2 to 16MHz

S80C652-6N40

S83C652-6N40

-40 to +11 OOC plastic DIP

S80C652-6A44

S83C652-6A44

-40 to +110 0 C plastic LCC 1.2 to 12MHz

Speed and Temperature Range
1
2
4
5
6

ROM Version

ROMle.s

0 to +70 0 C, 1.2 to 12MHz
-40 to +85 0 C, 1.2 to 12MHz
0 to +70 0 C, 1.2 to 16MHz
-40 to +85°C, 1.2 to 16MHz
-40 to +110 0 C, 1.2 to 12MHz

ROMlesa/ROM

1.2 to 16MHz

1.2 to 12MHz

·Preliminary specification

0- ROMless
3 - ROM

BLOCK DIAGRAM
FREQUENCY
REFERENCE
I

XTAL2

XTAL1

COUNTERS

•

i
TO

PROGRAM
MEMORY
(8K x 8 ROM)

DATA
MEMORY
(258 x 8 RAM)

SDA} SHARED
WITH
SCL PORT 1

INTERNAL
INTERRUPTS

EXTERNAL INTERRUPTS

February 1989

J
PARALLEL PORTS,
ADDRESS/DATA BUS
AND I/O PINS

2-128

I SERIAL IN

SERIAL OUT.
i

SHARED WITH
PORT 3

Product Specification

Signetics Microprocessor Products

S83C652/S80C652

CMOS Single-Chip 8-Bit Microcontroller
PIN DESCRIPTION
MNEMONIC
PO.7-PO.0

PIN NO.

1----,-----1 TYPE
DIP

39-32 43-46

Pl.O-Pl.7

Pl.6
Pl.7

NAME AND FUNCTION

LCC

I/O

Port 0: 8-bit open-drain bidirectional I/O port. It is also the multiplexed low-order address and data bus during accesses to external memory (during these accesses it activates internal pullups). Port 0 can sink/source 8 LS TTL inputs.
Port 1: 8-bit quasi-bidirectional I/O port. Port 1 can sink/source one TTL (- 4 LS TTL)
input. It can drive CMOS inputs without external pullups, except Pl.6 and Pl.7 which
have open drain outputs. Alternate functions include:
SCL: 12C-bus serial port clock line.
SDA: 12C-bus serial port data line.

1-8

2-9

I/O

7
8

8
9

I/O
I/O

P2.0-P2.7

21-28 24-31

P3.0-P3.7

10-17

I/O

Port 2: 8-bit quasi-bidirectional I/O port with internal pull ups. During access to
external memories (RAM/ROM) that use 16-bit addresses (MOVX @DPTR), port 2 emits
the high-order address byte. When external RAM is accessed with an 8-bit address
(MOVX @Ri), port 2 emits the contents of the P2 function register. Port 2 can sink/
source one TTL (-4 LS TTL) input. It can drive CMOS inputs without external pull ups.
I/O Port 3: 8-bit quasi-bidirectional I/O port with internal pull ups. It also serves the following alternative functions:
I
RxD/DATA: Serial port receiver data input (asynchronous) or data input/output (synchronous).
o TxD/CLOCK: Serial port transmitter data output (asynchronous) or clock output (synchronous).
I
INTO: External interrupt 0 or gate control input for timer/event counter O.
I
INT1: External interrupt 1 or gate control input for timer/event counter 1.
I
TO: External input for timer/event counter O.
I
T1: External input for timer/event counter 1.
o WR: External data memory write strobe.
ORO: External data memory read strobe.
The generation or use of a port pin as an alternative function Is carried out automatically by the S83C652, provided the associated special function register bit Is set
high. Port 3 can sink/source one TTL (-4 LS TTL) input. It can drive CMOS Inputs without external pullups.

P3.0

ii,
13-19
11

P3.1

P3.2
P3.3
P3.4
P3.5
P3.6
P3.7

12
13
14
15
16
17

14
15
16
17
18
19

RST

XTAL1

Vss
PSEN

20
29

22
32

Program Store Enable: Read strobe to the external program memory via port 0 and 2. It
is activated twice each machine cycle during fetches from external..J2!.Q9!am memory.
When executing out of external program memory, two activations of PSEN are skipped
during each access to external data memory. PSEN is not activated (remains high)
during fetches from external program memory. PSEN can sink/source 8 LS TTL inputs.
It can drive CMOS inputs without an external pull up.

ALE

Address Latch Enable: Latches the low byte of the address during accesses to external
memory in normal operation. It is activated every six oscillator periods except during an
external data memory access. ALE can sink/source 8 LS TTL inputs. It can drive CMOS
inputs without an external pull up.

External Access: When EA is held at a TTL high level, the CPU executes out QLthe
internal program ROM, provided the program counter is less than 8192. When EA is
held at a T1l..low level, the CPU executes out of external program memory via port 0
and port 2. EA is not allowed to float.

Vee

Reset: A high level on this pin for two machine cycles, while the oscillator is running,
resets the device. An internal pull-down resistor permits power-on reset using only a
capacitor to Vee.
Crystal Input 1: Input to the inverting amplifier that forms the oscillator. Left opencircuit when an external oscillator clock is used.
Ground: Circuit ground potential.

Power Supply: +5V power supply pin during normal operation, idle mode and powerdown mode.

NOTE:
To avoid a 'latch-up' effect at power-on, the voltage on any pin at any time must not be higher or lower than Vee + 0.5V or
VSS - 0.4V respectively.

February 1989

2-129

Product Specification

Signetics Microprocessor Products

S83C652/S80C652

CMOS Single-Chip 8-Bit Microcontroller
OSCILLATOR CHARACTERISTICS
XTAU and XTAL2 are the input and output, respectively, of an inverting amplifier. The pins can be configured for use
as an on-chip oscillator, as shown in the
logic symbol, page 1.
To drive the device from an external
clock source, XTAU should be driven
while XTAL2 is left unconnected. There
are no requirements on the duty cycle of
the external clock signal, because the
input to the internal clock circuitry is
through a divide-by-two flip-flop. However, minimum and maximum high and
low times specified in the data sheet
must be observed.

idle mode is activated. -The CPU contents, the on-chip RAM, and all of the
special function registers remain intact
during this mode. The idle mode can be
terminated either by any enabled interrupt (at which time the process is picked
up at the interrupt service routine and
continued), or by a hardware reset
which starts the processor in the same
manner as a power-on reset.
POWER-DOWN MODE
In the power- 100pF), the noise pulse on the ALE pin may exceed O.BV. In such cases, it may be desirable to

qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input.
3.
4.
5.

Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the O.9VCC specification when the
address bits are stabilizing.
Pins of ports 1, 2, and 3 source a transition current when they are being externally driven from 1 to O. The transition current reaches its
maximum value when VIN is approximately 2V.
See Figures 7 through 10 for ICC test conditions.

The input threshold voltage of Pl.6 and Pl.? (Sial) meets the 12C specification, so an input voltage below 1.5V will be recognized as a logic 0 while an input voltage above 3.0V will be recognized as a logic 1.

AC ELECTRICAL CHARACTERISTICS TA - O°C to +70°C, or TA - -40°C to +85°C/l10°C, VCC - 5V ±10%, VSS - OV1, 2
SYMBOL

FIGURE

12MHz CLOCK

PARAMETER

Min

Max

VARIABLE CLOCK
Min

Max

1.2

UNIT

Program Memory
l/tCLCL

Oscillator frequency

tLHLL

ALE pulse width

127

2tCLCL -40

tAVLL

Address valid to ALE low

tCLCL-55

tLLAX

Address hold after ALE low

tCLCL-35

tLLlV

ALE low to valid instruction in

tLLPL

ALE low to PSEN low

tCLCL -40

tpLPH

PSEN pulse width

205

3tCLCL -45

tPLIV

PSEN low to valid instruction in

tPXIX

Input instruction hold after PSEN

tpXIZ

Input instruction float after PSEN

tAVIV

Address to valid instruction in

PSEN low to address float

tpLAZ
Data Memory

234

4tCLCL -100

145

MHz

ns
ns
ns

3tCLCL -105
0

ns
ns

tCLCL-25

312

5tCLCL -105

tAVLL

2, 3

Address valid to ALE low

tCLCL-40

tRLRH

2, 3

RD pulse width

400

6tCLCL -100

tWLWH

2,3

WR pulse width

400

6tCLCL -100

tRLDV

2, 3

RD low to valid data in

tRHDX

2, 3

Data hold after RD

tRHDZ

2, 3

Data float after R D

252
0

5tCLCL -165

2tCLCL -70

0
97

tLLDV

2, 3

ALE low to valid data in

517

8tCLCL -150

tAVDV

2, 3

Address to valid data in

585

9tCLCL -165

tLLWL

2, 3

ALE low to RD or WR low

200

tAVWL

2, 3

Address valid to WR low or RD low

203

4tCLCL -130

tOVWX

2, 3

Data valid to WR transition

tCLCL -60

tWHOX

2, 3

Data hold after WR

tCLCL-50

tRLAZ

2, 3

RD low to address float

tWHLH

2, 3

RD or WR high to ALE high

February 1989

300

3tCLCL -50

12
43

2-132

123

tCLCL -40

3tCLCL+50

ns
12

tCLCL+40

Product Specification

Signetics Microprocessor Products

S83C652/S80C652

CMOS Single-Chip 8-Bit Microcontroller
AC ELECTRICAL CHARACTERISTICS (Continued)
SYMBOL

12MHz CLOCK

PARAMETER

FIGURE

Min

VARIABLE CLOCK

Max

Min

Max

UNIT

External Clock
tCHCX

High time 3

tCLCX

Low time 3

tCLCH

Rise time 3

Fall time 3

tCHCL
Shift Register

ns
ns

tXLXL

Serial port clock cycle time 3

1.0

12tCLCL

tOVXH

Output data setup to clock rising edge 3

700

1OtCLCL -133

tXHOX

Output data hold after clock rising edge 3

2tCLCL -117

tXHDX

Input data hold after clock rising edge 3

tXHDV

Clock rising edge to input data valid 3

lIS

0
700

ns
1OtCLCL -133

NOTES:
1. Parameters are valid over operating tei!!2erature range unless otherwise specified.

2. Load capacitance for port 0, ALE, and PSEN - 100pF, load capacitance for all other outputs - BOpF.
3. These values are characterized but not 100% production tested.

P- PSEN
Q - Output data

R - RD signal
t - Time
V - Valid
W - WR signal
X - No longer a valid logic level
Z - Float
Examples: tAVLL - Time for address valid to ALE low.
tLLPL - Time for ALE low to PSEN low.

ALE

I"SE'N

---"

PORTO _ _ _J

PORT 2

Figure 1. External Program Memory Read Cycle

February 1989

2-133

Product Specification

Signetics Microprocessor Products

CMOS Single-Chip 8-Bit Microcontroller

S83C652/S80C652

ALE

t-----tLLDV ---.....,
---*~-----tRLRH------.....,

PORTO

~----------~VDV-----~
PORT 2

P2.0-P2.7 OR AB-AI5 FROM DPH

A8-A15 FROM PCH

Figure 2. External Data Memory Read Cycle

ALE

---to----WLWH----o!

PORTO

DATA OUT

PORT 2

P2.0-P2.7 OR A8-A15 FROM DPH

Figure 3. External Data Memory Write Cycle

February 1989

2-134

AO-A7 FROM PCL

AB-AI5 FROM PCH

Product Specification

Signetics Microprocessor Products

S83C652/S80C652

CMOS Single-Chip 8-Bit Microcontroller

Vee-O,S .-------,,-- - - O.4SV

~---------tCLCL-----~

Figure 4. External Clock Drive

INSTRUCTION

ALE

tOVXH

OUTPUT DATA

f
WRITE TO SBUF

I INPUT DATAl ____________

t XHOX

X~--JX~--JX~--JX'-_...JX'-_...JX'-_...J

J, __J~~-'~=7'

1~-'··7'

I~-"·~'

I~·-"~'

I':-"?,.

I'''-''~''

CLEAR RI

SET RI

Figure 5. Shift Register Mode Timing

Vee-O.S
O.4SV

O.2Vee+O.9

Timing

Reference
Points

_,-,O""2""V""e,,,e-...;O;;,;','-'-_.....

AC inputs during testing are driven at Vcc-O.S

for a logic "1" and 0.4SV for a logic '0'.
Timing measurements are made at VIH min for
a logic '1' and V IL max for a logic '0'.

For timing purposes, a port is no longer floating
when a 100mV change from load voltage occurs,
and begins to float when a 100mV change from
the loaded VOHIVOL level occurs.IOH/lOL~± 20mA.

Figure 6. AC Testing Input/Output

Figure 7. Float Waveform

February 1989

2-135

Signetics Microprocessor Products

Product Specification

S83C652/S80C652

CMOS Single-Chip 8-Bit Microcontroller

Vee
....._ _ _--ilee
Vee

l Vee

Vee
RST
RST

CLOCK (NC)
SIGNAL

XTAL2
XTALl
Vss

CLOCK (NC)
SIGNAL

XTAL2
XTALI
Vss

Figure 9. Icc Test Condition, Idle Mode
All other pins are disconnected

Figure 8. Icc Test Condition, Active Mode
All other pins are disconnected

0.45V

~---------tCLCL----------~

Figure 10. Clock Signal Waveform for Icc Tests in Active and Idle Modes
tCLCH
tCHCL
5ns

Vee

....._ _ _--il,ee
Vee

l
Vee

RST

(NC)

XTAL2
XTALI
Vss

Figure 11. Icc Test Conditions, Power Down Mode
All other pins are disconnected. VCC
2V to 5.5V

February 1989

2-136

Signetics Microprocessor Products

User's Guide

Section 2 - 8051 Derivatives

8XC751

8XC751 OVERVIEW

This part is well suited for logic replacement in consumer and industrial applications.

The Signetics 83C751/87C751 offers the advantages of
the SC80C51 architecture in a small package and at a
low cost. This microcontroller is fabricated with
Signetics high-density CMOS technology. Signetic~. e.ritaxial substrate minimizes CMOS lach-up senSItiVIty.
The 83C751187C751 (hereafter referred to collectively as
the 83C751) contains a 2K x 8 ROM/EPROM, a 64 x 8
RAM 19 I/O lines a 16-bit auto-reload counter/timer,
a fix~d rate timer,' a five source fixed priority interrupt
structure, a bidirectional Inter-Integrated Circuit (12C)
serial bus interface, and an on-chip oscillator. The onboard inter-integrated circuit (12C) bus interface allows
the 83C751 to operate as a master or slave device on
the 12C small area network. This capability facilitates
I/O and RAM expansion, access to EPROM, processor
to processor communication, and efficient interface to a
wide variety of dedicated 12C peripherals. The 83C751
has the following features:
•
•
•
•
•
•

•
•

•
•
•
•
•

SC80C51 based architecture
Boolean processor
Inter-integrated Circuit (12C) serial bus interface
Fixed-rate timer
16-bit auto reload able counterltimer
Small package sizes
- 24 pin DIP (300 mil "skinny DIP")
- 28 pin PLCC
2K x 8 ROM/EPROM
Available in erasable quartz lid (87C751), one-time
programmable (87C751), or mask programmable
versions (83C751)
Wide oscillator frequency range
Low power consumption:
- Normal operation: less than llmA @ 5V, 12MHz
Idle mode
Power-down mode
CMOS and TIL compatible

DIFFERENCES FROM THE 80C5l
Memory Organization

The central processing unit (CPU) manipulates operands
in 2 address spaces as shown in Figure 61. The part's
internal memory space consists of 2K bytes of program
memory, and 64 bytes of data RAM overlapped with the
128 byte special function register area. The differences
from the 80C5l are in RAM size (64 bytes vs 128 bytes),
in external RAM access (not available on the 83C751),
in internal ROM size (2K bytes vs 4k bytes), and in external program memory expansion (not available on the
83C751). The 128 byte special function register (SFR)
space is accessed as on the 80C51 with some of the registers having been changed to reflect changes in the
83C751 peripheral functions. The stack may be located
anywhere in internal RAM by loading the 8-bit stack
pointer (SP). It should be noted that stack depth is limited to 64 bytes, the amount of available RAM. A reset
loads the stack pointer with 07F (which is pre-incremented on a PUSH instruction).
Special Fnnction Registers

The 83C751 contains many of the Special Function Registers (SFR) that are found on the 80C51. Due to the
different peripheral features on the 83C751, there are
several additional SFRs and several that have been
changed. There is no port 2 on the 83C751 so the P2
SFR isn't used. The standard UART found on the 80C51
has been replaced by the 12C serial interface, so the
UART SFRs, SCON and SBUF, have been replaced by
12CON and 12DAT, and two additional 12C registers
have been added (12STA and 12CFG).

(FFH) 255
SPECIAL
FUNCTION
REGISTERS

(80H) 128

(3FH) 63
INTERNAL
DATA RAM

(OOH) 0

Figure 61. Memory Map

February 1989

2-137

Signetics Microprocessor Products

User's Guide

Section 2 - 8051 Derivatives

8XC751

Because the interrupt structure is single level on the
83C751 there is no need for the IP SFR, so it is not
used. The counter/timer has only one mode of operation
so the TMOD SFR is not used. There is also only one
counter/timer so there is no need for the TLI and THI
SFRs found on the 80C51. These have been replaced on
the 83C751 by RTL and RTH the counter/timer reload
registers. Table 20 shows the special function registers,
their locations, and reset values.
Data Pointer (DPTR)
The Data Pointer (DP1R) consists of a high byte (DPH)
and a low byte (DPL). In the 80C51 this register allows
the access of external data memory using the MOVX instruction. Since the 83C751 does not support MOVX or
external me'mory accesses this register is generally used
as a 16-bit offset pointer of the accumulator in a MOVC
instruction. DP1R may also be manipulated as two independent 8-bit registers.
110 Port Latches (pO, PI, P3)

110 Port Structure
The 8XC751 has 2 eight-bit ports (ports I and 3) and I
three-bit port (port 0). All three ports on the 8XC751
are bi-directional. Each consists of a latch (special function register PO, PI, P3), an output driver, and an input
buffer. Three Port 1 pins and two Port 0 pins are multifunctional. In addition to' being port pins, these pins
serve the function of special features' as follows:
Port Pin
PO.O
PO.I
P1.5
P1.6
P1.7

Alternate Function
I2C clock (SCL)
I2C data (SDA)
INTO (external interrupt 0 input)
INTI (external interrupt I input)
TO (timer 0 external input)

Ports I and 3 are identical in structure to the same
ports on the 80C51. The structure of Port 0 on the
8XC751 is similar to that of the 80C51 but does not include address/data input and output circuitry. As on the
80C51, ports 1 and 3 are quasi-bidirectional while port 0
is bi-directional with no internal pullups.

The port latches function the same as those on the
80C51. Since there is no Port 2 on the 83C751 the P2
latch is not used. Port 0 on the 83C751 has only 3 bits,
so only 3 bits of the PO SFR have a useful function.

B
TO PIN

112

·1

~
r

RTL

RTH

C/T=1

TR
GATE
INTO PIN

Figure 62. 83C7S1 Counterrflmer Block Diagram

February 1989

2-138

INT

Signetics Microprocessor Products

User's Guide

Section 2 - 8051 Derivatives

8XC751

Table 20. 8XC751 Special Function Registers
Description

Symbol
ACC*
B*
DPTR:
DPH
DPL

Accumulator
B register
Data pointer (2 bytes):
High byte
Low byte

Direct
Address
EOH
FOH

Bit Address. Symbol or Alternative Port Function
MSB
LSB
E7
E6
E4
E5
E3
E2
EI
EO
F7
F6
F5
F4
F3
F2
FI
FO

Reset Value

DOH
DOH
DOH
DOH

83H
82H
DF

12CFG*# 12C configuration

DD
DC
D8H/RD SLAVE~STRCl[ 0 tIIRUN!
WR SLAVENlMASTRQlCLRTHIIR UN!

I2CON*# I2C control

9E
9D
9F
9C
9B
9A
99
98
98H/RD RDA'"Q ATN lDRDYI ARL I STR I STP IMASTER!
8lH
WR CXAl IDLE~ CDR ICARLI CSTR I CSTP I XSTR I XSTP

I2DAT#

I2C data

DB
-

DA
I
I

D9
D8
I CTl I CTO OOOOxxOOB
I CTl I CTO

99H/RD RDATI
WR XDATI
FF

I2STA*# I2C control

F8H

IE*#

Interrupt enable

A8H

PO*#
PI *
P3*

Port 0
Port 1
Port 3

80H
90H
BOH

PC ON

Power control

87H

PSW*

Program status word

DOH

Stack pointer

81H

TCON*# Timer/counter control

88H

0
X

I
I

0
X

0
X
FB

0
X

0
X ~

0
X

A9
ETO

A8
EXO

81
91
Bl

80
90
BO

xxxxxl1lB
FFH
FFH

IDL

xxxxxxDOB

DO
P

DOH

AC
AB
AA
I EI2 I ETI I EX1

97
B7

96
B6

95
B5

94
B4

93
B3

- 1
D6

I
D5

82
92
B2

1 AC 1 FO I RSI I RSO I

Dl
I

DOH

07H
8F
8E
GATEl CIT

1 TF

8C
8B
I TR I lEO

8A
I ITO

89
lEI

88
ITl

Timer/Counter

DOH
DOH
DOH
DOH
DOH

TL#
Timer low byte
8AH
TH#
Timer high byte
8CH
RTL#
Timer low reload
8BH
RTH#
Timer high reload
8DH
* = SFRs are bit addressable.
# = SFRs are modified from or added to the 80C51 SFRs.
TCON Register

The 8XC751 has two timers: a 16-bit Timer/Counter and
a lO-bit fixed rate timer. The 16-bit Timer/Counter's
operation is similar to Mode 2 operation on the 80C51.
but is extended to 16 bits. The Timer/Counter is clocked
by either 1/12 the oscillator frequency or by transitions
on the TO pin. The CIT pin in special function register
TCON selects between these two modes. When the
TCON TR bit is set, the timer/counter is enabled. Register pair TH and TL are incremented by the clock
source. When the register pair overflows, the register
pair is reloaded with the values in registers RTH and
RTL. The value in the reload registers is left unchanged.
See the 83C751 counter/timer block diagram in Figure
62. The TF bit in special function register TCON is set
on counter overflow and, if the interrupt is enabled, will
generate an interrupt.

February 1989

80H

1 IDLE lXDATAIXACTVIMAKSTRIMAKSTPI XSTR I XSTP xOl00000B

AF
AE
EAJ

D7
CY

IGATEI CIT I TF
MSB

432
TR
lEO
ITO

0
lEI I ITI I
LSB

GATE 1 - Timer/counter is enabled only when INTO
pin is high, and TR is 1.
o - Timer/counter is enabled when TR is 1.
CIT
1 - Counter/timer operation from TO pin.
o - Timer operation from internal clock.
TF
I - Set on overflow of TH.
o - Cleared when processor vectors to interrupt
routine and by reset.
TR
1 - Timer/counter enabled.
o - Timer/counter disabled.
lEO
1 - Edge detected in INTO.

2-139

User's Guide

Signetics Microprocessor Products

8XC751

Section 2 - 8051 Derivatives
ITO
lEI
IT1

- INTO
INTO
1 - Edge
1 - INTI
o - INTI

The MINIMUM SDA LOW TO SCL LOW time in a
start condition.
The MAXIMUM SCL CHANGE time while an 12C
frame is in progress. A frame is in progress between
a Start condition and the following Stop condition.
This time span serves to detect a lack of software response on this 8XC751 as well as external l2C problems. SCL "stuck low" indicates a faulty Master or
Slave. SCL "stuck high" may mean a faulty device, or
that noise induced onto the 12C caused all Masters to
withdraw from 12C arbitration.

is edge triggered.
is level sensitive.
detected on INTI.
is edge triggered.
is level sensitive.

These flags are functionally identical to the corresponding 80C51 flags, except that there is only one timer on the 83C751 and the flags are therefore combined
into one register.
The 12C watchdog timer, timer I, is also available as a
general purpose fixed rate timer when the 12C interface
is not being used. A clock rate of 1/12 the oscillator
frequency forms the input to a prescaler. This prescaler
c an be programmed for 1 of 4 values to give a range of
timeout periods (see more discussion in 12C section).
Timer I has a timeout interval of 1024 machine cycles.
An external reset on this timer is initiated by a transition on the SCL(PO.O) pin.
12C Serial Interface
The 12C bus uses two wires (SDA and SCL) to transfer
information between devices connected to the bus. The
main technical features of the bus are:
-

Bidirectional data transfer between masters and slaves
Serial addressing of slaves
Acknowledgment after each transferred byte
Multimaster bus
Arbitration between simultaneously transmitting masters without corruption of serial data on bus

A large family of 12C compatible ICs is available. See
the 12C section of this manual for more details on the
bus and available ICs.
The 83C751 12C subsystem includes hardware to simplify
the software required to drive the 12C bus. The hardware
is a single bit interface which in addition to including
the necessary arbitration and framing error checks, includes clock stretching and a bus timeout timer. The interface is synchronized to software either through polled
loops or interrupts. Six time spans are important in 12C
operation and are insured by Timer I:
The MINIMUM HIGH time for SCL when this device is the master.
- The MINIMUM LOW time for SCL when this device
is a master. This is not very important for a single-bit
hardware interface like this one, because the SCL
low time is stretched until the software responds to
the 12C flags. The software response time normally
meets or exceeds the MIN La time. In cases where
the software responds within (MIN HI + MIN La)
time, Timer I will insure that the minimum time is
met.
- The MINIMUM SCL HIGH TO SDA HIGH time in
a stop condition.
- The MINIMUM SDA HIGH TO SDA LOW time between 12C stop and start conditions. (4.7jlS see spec.)

The first 5 of these times are 4.7jlS (see 12C specification) and are covered by the low order 3 bits of Timer 1.
Timer I is clocked by the 8XC751 oscillator which can
vary in frequency from 0.5 to 16MHz. A prescaler with
one of 4 divisor values allows Timer I values to be optimized for different oscillator frequencies. At lower frequencies, software response time is increased and will
degrade maximum performance of the 12C bus. For
100Khz bus performance, the oscillator rate should be
limited to the 8-16MHz range which is the range that
the Timer I prescaler was designed for. See special
function register 12CFG description for prescale values
(CTO, CTl).
The MAXIMUM SCL CHANGE time is important but
its exact span is not critical. The complete 10 bits of
Timer I are used to count out the maximum time. When
12C operation is enabled, this counter is cleared by transitions on the SCL pin. The timer does not run between
12C frames (i.e. whenever Reset or Stop occurred more
recently than the last Start). When this counter is running, it will carry out after 1024 machine cycles have
elapsed since a change on SCL. A carry out causes a
hardware reset of the 83C751 12C interface and generates an interrupt if the Timer I interrupt is enabled. In
cases where the bus hangup is due to a lack of software
response by this 83C751, the reset releases SCL and allows 12C operation among other devices to continue.
I2C Register 12CON
7

Read
Write

February 1989

Reading 12CON
RDAT

2-140

The data from SDA is captured into "Receive
DATa" whenever a rising edge occurs on
SCL. RDAT is also available (with 7 loworder zeros) in the 12DAT register. The difference between reading it here and there is
that reading 12DAT clears DRDY, allowing
the 12C to proceed on to another bit. Typically, the first 7 bits of a received byte are
read from 12DAT, while the 8th is read here.
Then, 12DAT can be written to send the Ack
bit and clear DRDY.

Signetics Microprocessor Products

User's Guide

Section 2 - 8051 Derivatives
Am

DRDY

8XC751

"ATteNtion" is 1 when one or more of DRDY,
ARL, STR, or STP is 1. Thus, Am comprises a single bit that can be tested to release the I2C service routine from a "wait
loop".
"Data ReaDY" (and thus Am) is set when a
rising edge occurs on SCL, except at idle
Slave. DRDY is cleared by writing CDR ~ 1,
or by writing or reading the 12DAT register.
The following low period on SCL is stretched
until the program responds by clearing
DRDY.

Checking Am and DRDY
When a program detects Am ~ 1, it should next check
DRDY. If DRDY ~ 1, then if it receives the last bit it
should capture the data from RDAT (in 12DAT or
I2CON). Next, if the next bit is to be sent it should be
written to I2DAT. One way or another it should clear
DRDY and then return to monitoring Am. Note that if
any of ARL, STR, or STP is set, clearing DRDY will
not release SCL to high, so that the 12C will not go on
to the next bit. If a program detects Am ~ 1, and
DRDY ~ 0, it should go on to examine ARL, STR, and
STP.
ARL

"Arbitration Loss" is 1 when transmit Active
was set, but this 83C751 lost arbitration to
another transmitter. Transmit Active is
cleared when ARL is 1. There are 4 separate
cases in which ARL is set.
1. If the program sent a 1 or repeated start,
but another device sent a 0, or a stop, so that
SDA is 0 at the rising edge of SCL. (If the
other device sent a Stop, the setting of ARL
will be followed shortly by STP being sent.)
2. If the program sent a 1, but another device
sent a repeated start, and it drove SDA low
before the 83C751 could drive SCL low. (This
type of ARL is always accompanied by STR ~

MASTER

Writing I2CON
Typically, for each bit in an I2C message, a service routine waits for Am ~ 1. Based on DRDY, ARL, STR,
and STP, and on the current bit position in the message,
it may then write I2CON with one or more of the following bits, or it may read or write the I2DAT register.
CXA

STR

STP

February 1989

Writing a 1 to "Clear Xmit Active" clears the
Transmit Active state. (Reading the I2DAT
register also does this.)

Regarding Transmit Active
Transmit Active is an internal state in the I2C interface
and is not directly testable. Transmit Active is set by
writing the I2DAT register, or by writing I2CON with
XSTR ~ 1 or XSTP ~ 1. The I2C interface will only
drive the SDA line low when Transmit Active is set, and
the ARL bit will only be set to 1 when Transmit Active
is set. Transmit Active is cleared by reading the I2DAT
register, or by writing I2CON with CXA ~ 1. Transmit
Active is automatically cleared when ARL is 1.
IDLE

CDR

1.)
3. In Master mode, if the program sent a repeated Start, but another device sent a 1, and
it drove SCL low before this 83C751 could
drive SDA low.
4. In Master mode, if the program sent Stop,
but it could not be sent because another device sent a O.
"STaRt" is set to a 1 when an I2C Start condition is detected at a non-idle Slave or at a
Master. (STR is not set when an idle Slave
becomes active due to a Start bit; the Slave
has nothing useful to do until the rising edge
of SCL sets DRDY.)
"SToP" is set to 1 when an I2C Stop condition is detected at a non-idle Slave or at a
Master. (STP is not set for a Stop condition
at an idle Slave.)

"MASTER" is 1 if this 83C751 is currently a Master on the nc. MASTER
is set when MASTRQ is 1 and the bus
is not busy (i.e., if a start bit hasn't
been received since Reset or a "Timer
I" time-out, or if a Stop has been received since the last Start). MASTER
is cleared when ARL is set, or after the
software writes MASTRQ ~ 0 and then
XSTP ~ 1.

CARL
CSTR
CSTP

2-141

Writing 1 to "IDLE" causes a Slave's I2C hardware to ignore the I2C until the next Start
condition (but if MASTRQ is 1 then a Stop
condition will make the 83C751 into a Master).
Writing a 1 to "Clear Data Ready" clears
DRDY. (Reading or writing the I2DAT register also does this.)
Writing a 1 to "Clear Arbitration Loss" clears
the ARL bit.
Writing a 1 to "Clear STaRt" clears the STR
bit.
Writing a
to "Clear SToP" clears the STP
bit. Note that if one or more of DRDY, ARL,
STR, or STP is 1, the low time of SCL is
stretched until the service routine responds by
clearing them.

Signetics Microprocessor Products

User's Guide

Section 2 - 8051 Derivatives
XSTR

XSTP

8XC751

Writing 1's to "Xmit repeated STaRt" and CDR
tells the I2C hardware to send a Repeated
Start condition. This should only be at a Master. Note that XSTR need not and should not
be used to send an "initial" (non-repeated)
Start; it is sent automatically by the I2C hardware. Writing XSTR = 1 includes the effect of
writing I2DAT with XDAT = 1; it sets Transmit Active and releases SDA to high during
the SCL low time. After SCL goes high, the
I2C hardware waits for the suitable minimum
time and then drives SDA low to make the
Start condition.
Writing 1's to "Xmit SToP" and CDR tells the
I2C hardware to send a Stop condition. This
should only be done at a Master. If there are
no more messages to initiate, the service routine should clear the MASTRQ bit in I2CFG to
o before writing XSTP with 1. Writing XSTP =
1 includes the effect of writing I2DAT with
XDAT - 0; it sets Transmit Active and drives
SDA low during the SCL low time. After SCL
goes high, the I2C hardware waits for the suitable minimum time and then releases SDA to
high to make the Stop condition.

RDAT
XDAT

I:~~ ~ I

____

SLAVEN

MASTRQ

5
0
X

4
0
X

3
0
X

2
0
X

1
0
X

0
0
X

IIIIII

"Receive DATa" is captured from SDA every
rising edge of SCL. Reading I2DAT also
clears DRDY and the Transmit Active state.
"Xmit Data" sets the data for the next bit.
Writing I2DAT also clears DRDY and sets
the Transmit Active state.

TIRUN

en,o

Regarding Software Response Time
Because the 83C751 can run at 16MHz, and because the
I2C interface is optimized for high-speed operation, it is
quite likely that an I2C service routine will sometimes
respond to DRDY (which is set at a rising edge of SCL)
and write I2DAT before SCL has gone low again. If
XDAT were applied directly to SDA, this situation would
produce an I2C protocol violation. The programmer need
not worry about this possibility because XDAT is applied
to SDA only when SCL is low.
Conversely, a program that includes an I2C service routine may take a long time to respond to DRDY. Typically, an I2C routine operates on a flag-polling basis
during a message, with interrupts from other peripheral
functions enabled. If an interrupt occurs it will delay the
response of the 12C service routine. The programmer
need not worry about this very much either, because the
12C hardware stretches the SCL low time until the service routine responds. The only constraint on the response
is that it must not exceed the Timer I time-out, which is
at least 768 microseconds.

February 1989

Read
Write

CLRTI

I2C Register I2DAT

Read
Write

12C Register 12CFG

____

_ _- L_ _

o
~~

Writing a 1 to "SLAVe ENable" enables
the Slave functions of the I2C subsystem. If
SLAVEN and MASTRQ are 0, the I2C
hardware is disabled. This bit is cleared to
o by reset and by an I2C time-out.
Writing a 1 to "MASTRQ" requests mastership of the I2C. If a frame from another
Master is in progress when this bit is
changed from 0 to 1, action is delayed until a stop condition is detected. Then, or
immediately if a frame is not in progress,
a start condition is sent and DRDY is set
(thus making ATN 1 and generating an I2C
interrupt). When a Master wishes to release mastership status of the I2C, it writes
a 1 to XSTP in I2CON. MASTRQ is
cleared by Reset and by an I2C time-out.
Writing a 1 to this bit clears the Timer I
interrupt flag. This bit position always
reads as a O.
Writing a 1 to this bit lets Timer I run; a
zero stops and clears it. Together with
SLAVEN, MASTRQ, and MASTER, this
bit determines operational modes as shown
in Table 21.
These two bits are programmed as a function of the OSC rate, to optimize the MIN
HI and LO time of SCL when this 83C751
is a master on the I2C. The time value determined by these bits controls both of
these parameters, and also the timing for
Stop and Start conditions. These bits are
cleared to 00 by reset.

The value that should be programmed in these bits is
given in Table 22, for integer-MHz crystal values. For
other values, the controlling factor is that the MIN
TIME must be greater than or equal to 4.7I1Sec. (MIN
TIME is a range because 12C events are not synchronized to osc/12.)
The maximum oscillator frequency (MHz) for a given
en, 0 value is given by:
(oscl12 count - 0.42) *12
fosc max =
4.7
The 4.7 in the denominator is the minimum LOW time
for 12C in microseconds.

2-142

Signetics Microprocessor Products

User's Guide

Section 2 - 8051 Derivatives

8XC751

Table 21. Interaction of TIRUN with SLAVEN, MASTRQ, and MASTER
SLAVEN,
MASTRQ,
MASTER

TIRUN

Operating Mode

All 0

The 12C interface is disabled. Timer I is cleared and does not run. This is the state assumed after
a reset. If an I2C application wants to ignore the I2C at certain times, it should write SLAVEN,

All 0

Any or all 1

The I2C interface is disabled. Timer I operates as a free-running time base. Use this mode only in
non - 12C applications.
The 12C interface is enabled. The 3 low-order bits of Timer I run for min-time generation. but
the hi-order bits do not, so that there is no checking for I2C being 'hung'. This configuration can
be used for very slow 12C operation.
The 12C interface is enabled. Timer I runs during frames on the I2C, and is cleared by transitions on SCL, and by Start and Stop conditions. This is the normal state for I2C operation.

MASTRQ, and TIRUN all to zero.

Table 22. CT1, CTO Values
CT1, CTO Values

Oscll2 Count

10
01
00

7
6
5
4

Program Memory
Address
000
003
OOB
013
OlB
023

Event
Reset
INTO
Counter/Timer 0
INTI
Timer I
12C

I2C Register I2STA

Priority

Higr

Lowest

76543210
Read I - I IDLEIXDATAIXACTVIMAKSTRI MAKSTPIXSTRIXSTPI
MSB

LSB

This register is read only and reflects the internal status
of the 12C hardware. IDLE, XSTR, and XSTP reflect
the status of the like named bits in the 12CON register.
XDATA
XACfV
MAKSTR
MAKSTP
XSTR
XSTP

The content of the transmitter buffer.
Transmitter active.
This bit is high while the hardware
effecting a Start condition.
This bit is high while the hardware
effecting a Stop condition.
This bit is active while the hardware
effecting a repeated Start Condition.
This bit is active while the hardware
effecting a repeated Stop Condition.

The interrupt enable register (IE) is used to individually
enable or disable the 5 sources. Bit EA in the interrupt
enable register can be used to globally enable or disable
all interrupt sources. The interrupt enable register is described below. All other interrupt details are based on
the SOC51 interrupt architecture.
Interrupt Enable Register IE

Symbol
EA

Position

IE.7

EI2

IE.6
IE.5
IE.4

ETl

IE.3

EX1

IE.2

ETO

IE.1

EXO

IE.O

Instruction Set
The instruction set of the S3C751 is identical to the
SOC51 except for the instructions: MOVX, LCALL, and
UUMP which are not implemented.
Interrupts
The SXC751 has 5 interrupt sources with fixed priority
levels. Interrupt sources common to the SOC51 are the
external interrupts (INTO, INTI) and the timer/counter
interrupt (ETO). The 12C interrupt (EI2) and Timer I interrupt (ETI) are the other two interrupt sources.
Upon interrupt or reset the program counter is loaded
with specific values for the appropriate interrupt service
routine in program memory. These values are:

February 1989

I EI2 I ETl IEX1 I ETO IEXO I

2-143

Fnnction
Disables all interrupts. If EA = 0,.1!Q
interrupt will be acknowledged. If EA
= 1, each interrupt source is individually enabled or disabled by setting
or clearing its enable bit.
Reserved
Reserved
Enables or disables the 12C interrupt.
If ES = 0, the 12C interrupt is disabled.
Enables or disables the Timer I overflow interrupt. IF ETl = 0, the Timer
I interrupt is disabled.
Enables or disables external interrupt
1. If EX1 = 0, external interrupt 1 is
disabled.
Enables or disables the Timer 0
overflow interrupt. If ETO = 0, the
Timer 0 interrupt is disabled.
Enables or disables external interrupt
O. If EXO = 0, external interrupt 0 is
disabled.

Signetics

S83C751
CMOS Single-Chip 8-Bit
Microcontroller
Product Specification

Microprocessor Division

DESCRIPTION
The Signetics S83C751 offers many of
the advantages of the SC80C51 architecture in a small package and at low
cost.
The S83C751 Microcontroller is fabricated with Signetics high-density CMOS
technology. Signetics' epitaxial substrate
minimizes CMOS latch-up sensitivity.
The S83C751 contains a 2K x 8 ROM, a
64 x 8 RAM, 19 110 lines, a 16-bit
counter/timer, a fixed-rate timer, a fivesource fixed-priority interrupt structure, a
bidirectional Inter-Integrated Circuit (12C)
serial bus interface, and an on-chip
oscillator.
The onboard inter-integrated circuit (12C)
bus interface allows the S83C751 to operate as a master or slave device on the
12C small area network. This capability
facilitates I/O and RAM expansion, access to EEPROM, processor-to-processor communication, and efficient interface to a wide variety of dedicated 12C
peripherals.

FEATURES
• SC80C51 based architecture
• Inter-Integrated Circuit (12C)
serial bus interface
• Small package sizes
- 24-pin DIP (300 mil
"skinny DIP")
- 28-pin PLCC
• Wide power supply voltage
range
• Wide oscillator frequency range
• Low power consumption:
- Normal operation: less
than 24mA @ 5V, 12MHz
- Idle mode
- Power-down mode
• 2K x 8 ROM, 64 x 8 RAM
• 16-bit counter/timer
• Fixed-rate timer
• Boolean processor
• CMOS and TTL compatible
• Well suited for logic replacement, consumer and industrial
applications

PIN CONFIGURATION

Vss 12

INDEX

CORNEa:
4
~ 26 25
PLCC

LOGIC SYMBOL

19
12

TOP VIEW

-j_1m'lI
Ii: -11m
~

February 1989

2-144

_TO

Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14

Function

P3.4
P3.3
P3.2
P3.1
N.C.
P3.0
PO.2
PO.l/SDA
PO.O/SCL
N.C.
RST
X2
Xl

15
16
17
18
19
20
21
22
23
24
25
26
27
28

Vss

Function

P1.0
P1.1
P1.2
P1.3
P1.4
P1.5iiNi'O
N.C.
N.C.
P 1.6/ iN'i'i
P1.7ITO
P3.7
P3.6
P3.5
Vee

853-0599 95088

Signetlcs Microprocessor Products

Product Specification

CMOS Single-Chip 8-Bit Microcontroller

S83C751

ORDERING INFORMATION
S83C751- ee (CVxxxx)

--r-

Custom ROM Pattern No.
Applies to masked ROM versions
only. Number will be assigned by
Signetics. Contact Signetics
sales office for ROM pattern sub-

mission requirements.
Package Codes:
N24 - Plastic DIP
A28 - Plastic PLCC
Speed and Temperature Range:

12345-

3.5
3.5
0.5
3.5
3.5

to
to
to
to
to

12MHz.
12MHz.
12MHz.
16MHz.
16MHz.

OoC to +70 0 C
-40°C to +85 °c
OOC to +70° C
OOC to +70 0 C
-40°C to +85 °c

PART NUMBER SELECTION
Speed
Temperature and Package
3.5 to 12MHz
o to +70°C, Plastic DIP
S83C751-2N24 3.5 to 12MHz
-40 to +85°C, Plastic DIP
Part Number
S83C751-1 N24

S83C751-3N24

0.5 to 12MHz

S83C751-4N24

3.5 to 16MHz

S83C751-5N24

3.5 to 16MHz

S83C751-1A28

3.5 to 12MHz

S83C751-2A28

3.5 to 12MHz

S83C751-3A28

0.5 to 12MHz

S83C751-4A28

3.5 to 16MHz

S83C751-5A28

3.5 to 16MHz

o to +70°C,
o to +70°C,

Plastic DIP
Plastic DIP

-40 to +85°C, Plastic DIP

o to +70°C,

Plastic LCC

-40 to +85°C, Plastic LCC

o to + 70°C,
o to +70°C,

Plastic LCC
Plastic LCC

-40 to +85°C, Plastic LCC

BLOCK DIAGRAM

~------------l

lIlT

L
P1.o-P1.7

February 1989

2-145

Signetics Microprocessor Products

Product Specification

CMOS Single-Chip 8-Bit Microcontroller

S83C751

PIN DESCRIPTION
PIN NO.
MNEMONIC I - - - , - - - i TYPE
DIP
PlCC

NAME AND FUNCTION

Vss

Circuit ground potential.

Vee

Supply voltage during normal, idle, and power-down operation.

8-6

9-7

I/O

PO.0-PO.2

Port 0: Port 0 is a 3-bit open-drain bidirectional port. Port 0 pins that have ones written to
them float, and in that state can be used as high-impedance inputs. Port 0 also serves as
the serial 12C interface as shown in the pinout diagram. When this feature is activated by
software, SCL and SDA are driven low in accordance with the 12C protocol. These pins are
driven low if the port register bit is written with a 0 or if the 12C subsystem presents a O.
The state of the pin can always be read from the port register by the program.
To comply with the 12C specification, PO.O and PO.l are open-drain bidirectional I/O pins
with the electrical characteristics listed in the tables that follow. While these differ from
'standard TTL' characteristics, they are close enough for the pins to still be used as
general-purpose 1/0 in non-12C applications.

I/O

SDA (PO.l) 12C data.

110

SCl (PO.O) 12C clock.

1/0

Port 1: Port 1 is an 8-bit bidirectional 110 port with internal pullups. Port 1 pins that have
ones written to them are pulled high by the internal pullups and can be used as inputs. As
inputs, port 1 pins that are externally pulled low will source current because of the internal
pullups. (See DC electrical characteristics: IILl. Port 1 also serves the special function
features of the SCBOC51 family as listed below:

Pl.0-Pl.7 13-20 15-20,
23, 24

INT1 CP1.6): External interrupt

TO CP1.7): Timer 0 external input

5-1
23-21

4-1,
6,
27-25

RST

Reset: A high on this pin for two machine cycles while the oscillator is running, resets the
device. An internal diffused resistor to Vss permits a power-on RESET using only an
external capacitor to Vee.

Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator
circuits.

P3.0-P3.7

INTO CP1.5): External interrupt

I/O

Port 3: Port 3 is an 8-bit bidirectional 1/0 port with internal pull ups. Port 3 pins that have
ones written to them are pulled high by the internal pullups and can be used as inputs. As
inputs, port 3 pins that are externally being pulled low will source current because of the
pullups (See DC electrical characteristics: IILl.

Crystal 2: Output from the inverting oscillator amplifier.

OSCilLATOR CHARACTERISTICS
Xl and X2 are the input and output, respectively, of an inverting amplifier
which can be configured for use as an
on-<:hip oscillator, as shown in the logic
symbol.

high long. enough to allow the oscillator
time to start up (normally a few milliseconds) plus two machine cycles. At
power-on, the voltage on Vee and RST
must come up at the same time for a
proper start-up.

To drive the device from an external
clock source, Xl should be driven while
X2 is left unconnected. There are no requirements on the duty cycle of the externa clock signal, because the input to
the internal clock circuitry is through a
divide-by-two flip-flop. However, minimum and maximum high and low times
specified in the data sheet must be
observed.

IDLE MODE
In the idle mode, the CPU puts itself to
sleep while all of the on-<:hip peripherals
stay active. The instruction to invoke the
idle mode is the last instruction executed
in the normal operating mode before the
idle mode is activated. The CPU contents, the on-<:hip RAM, and all of the
special ·function registers remain intact
during this mode. The idle mode can be
terminated either by any enabled interrupt (at which time the process is picked
up at the interrupt service routine and
continued), or by a hardware reset
which starts the processor in the same
manner as a power-on reset.

February 1989

2-146

POWER-DOWN MODE
In the power-<1own mode, the oscillator
is stopped and the instruction to invoke
power-<1own is the last instruction executed. Only the contents of the on-<:hip
RAM are preserved. A hardware reset is
the only way to terminate the powerdown mode. The control bits for the reduced power modes are in the special
function register PCON.

Table 1. External Pin Status During
Idle and Power-Down Modes
Mode
Idle
Power-down

Port 0

Port1

Port 2

Data
Data

Product Specification

Signetics Microprocessor Products

S83C751

CMOS Single-Chip 8-Bit Microcontroller
DIFFERENCES BETWEEN THE
S83C751 AND THE SC80C51
Program Memory
On the S83C751, program memory is
2048 bytes long and is not externally
expandable. Program memory can contain S83C751 instructions and constant
data. The only fixed allocations in program memory are the addresses at which
execution is taken up in response to reset and to interrupts, which are as
follows:
Program Memory
Address
Event
000
Reset
003
External INTO
OOB
Counter/timer 0
External I NT1
013
01B
Timer I
12C serial
023
Counter/Timer Subsystem
The S83C751 has one counter/timer
called timer/counter o. Its operation is
similar to mode 2 operation on the
SC80C51, but is extended to 16 bits with
16 bits of autoload. The controls for this
counter are centralized in a single register called TCON.

A watchdog timer, called Timer I, is for
use with the 12C subsystem. In 12C applications, this timer is dedicated to timegeneration and bus monitoring of the
12C. In non-12C applications, it is available for use as a fixed timebase.
Interrupt Subsystem - Fixed Priority
The I P register and the 2-level interrupt
system of the SC80C51 are eliminated.
Simultaneous interrupt conditions are resolved by a single-level, fixed priority as
follows:
Pin INTO
Counter/timer flag 0
Pin INT1
Timer I
Serial1 2C

Highest priority:

Lowest priority:

Serial Communications
The S83C751 contains an 12C serial communications port instead of the SC80C51
UART. The 12C serial port is a single bit
hardware interface with all of the hardware necessary to support multimaster
and slave operations. Also included are
receiver digital filters and timer (timer I)
for communication watch- to data valid

tGHGL

PO.1 (PROG-) high to PO.l (PROG-) low

tSYNL

PO.O (sync pulse) low

10
4tCLCL

tSYNH

PO.O (sync pulse) high

8tCLCL

tMASEL

ASEL high time

13tCLCL

tMAHLD

Address hold time

2tCLCL

tHASET

Address setup to ASEL

13tCLCL

tADsTA

Low adress to address stable

13tCLCL

NOTES:
°Address should be valid at least 24tCLCL before the rising edge of PO.2 (Vpp).
oOFor a pure verify mode, i.e., no program mode in between, tAVQV is 14tCLCL maximum.

February 1989

110

).LS

48tCLCL

2-159

).LS

Product Specification

Signetics Microprocessor Products

S87C751

CMOS Single-Chip 8-Bit Microcontroller

117C7II!
AO-A7/A&-A!O

P3.O-P;J.7

ADDAESS STROBE

PO.OIASEL

Vee 10--- +5V
Vss

Pl.CI-P!.7

PROGRAMIIING
PULSES

vpp /VIH

VOLTAGE
501J1CE

cue

50URCE

DATA BUS

PD.!
P0.2

XTALI
RESET

COHIROL
LOGIC

I
I

RESET

Figura 4. Programming Configuration

lCTAL 1
~ 2 MACHINE
...---CYClES _I_
TEN BIT SERIAL CODE
-I
RESET~
,
~1~B~rr~O~~B~rr~I~~B~IT~2~~B~IT~3~I~B~IT~4~I~B~IT~5~1~B~rr_8~~B~IT_7~~B~IT~8~-2BI~T~9~1______

PO.2 UNDEFINED I
PO.! UNDEFINED I

Figura 5. Entry Into ProgramNerify Modes

February 1989

2-160

-n

(/)

I»

()

cC·

III

s::

:::l

(J)

::J

co
CD
I

12.75V
5V

PO.2 (Vpp)

- - - - - - ".....::.;5V:...-_ _ _ _ _ _ __

H tSHGL

P~LSES

r-tMASELl

'tI
I
0)
~

Po.o (ASEL)

:::7

'tI

aa.

iii

s::

o·
0

98u5 MIN

'I'

1Qus MIN

... ,

VERIFY MODE

.-+
~

____~L~O~W~A~D~D~R~ES~S~_______________________________________________________________

HtADSTA

INVALID DATA

::J

CD
PORT 1

tHAHLD

;>C HIGHADDRESS:><:~

PORT 3

(")

,'-______________________________

tHASETj'

fJn

::::r

;::;:

H tGLGH H tGHGL

(>
Q)

.8ill

()

H tGHSL

I\)

o·

CX)

L ___ JLJL~=rur-------

PO.1 (PGM)

...
VALID

tGHDxj'

H t DVGL

DAT~

'I'

Ir--------------.:-....:.
DATA TO BE PROGRAMMED

... I

PROGRAM MODE

---.I
I VALID DATA
INVALID DATA
t AvaV

.. , , - - - - -

VERIFY MODE---i

'tI

a
c:

(J)

CX)

(/)

-...I
()
-...I
01
-L

"i
::;;
o·
e
g"
(>

User's Guide

Signetics Microprocessor Products

8XC752

Section 2 - 8051 Derivatives
Memory Organization

8XC752 OVERVIEW
The Signetics 83C752/87C752 is a single-chip control
oriented microcontroller fabricated with Signetics highdensity CMOS technology minimizing CMOS latch-up
sensitivity. Being a member of the 80C51 family, the
83C752 has a powerful instruction set, and has the same
basic architecture as the 80C5l. The 83C752 is essentially the popular industry-standard 83C751 with the inclusion of a 5-channel multiplexed 8-bit ADC and a
PWM output.
The 83C752 contains a 2K X 8 masked ROM, 64 bytes
of RAM, 21 110 lines, a 16-bit auto-reload timer/counter, a fixed rate timer, a seven source fixed priority interrupt structure, a bi-directional Inter-Integrated Circuit (I2C) serial bus interface, and an on-chip oscillator.
This device also includes a 5-channel multiplexed 8-bit
AiD converter and an 8-bit PWM output.
The on-board 12C bus interface allows the 83C752 to operate as a Master or Slave device on the 12C small area
network. This capability facilitates 110 and RAM expansion, access to EEPROM, processor-to-processor communications, and efficient interface to a wide variety of
dedicated 12C peripherals.
The EPROM version of this device, the 87C752, is also
available in both quartz-lid erasable and plastic one-time
programmable (OTP) packages. Once the array has been
programmed, it is functionally equivalent to the masked
ROM 83C752. Thus, unless explicitly stated otherwise,
all references made to the 83C752 apply equally to the
87C752.
The 83C752 supports two power reduction modes of operation referred to as the idle mode and the power-down
mode.
Idle Mode
In the idle mode, the CPU puts .itself to sleep while all
of the on-chip peripherals stay active, except for the
AiD converter and the PWM output. The instruction
which places the 83C752 into the idle mode is the last
instruction executed in normal operation before the idle
mode is activated. The CPU contents, the on-chip RAM,
and all of the SFRs remain intact during this mode. The
idle mode can be terminated by any enabled interrupt or
by a hardware reset. An interrupt will cause processing
to begin with the interrupt service routine.
Power-Down Mode
In the power-down mode, the oscillator is stopped and
the instruction to invoke power-down is the last instruction executed. Only the contents of the on-chip RAM is
preserved. A hardware reset is the only way to terminate
the power-down mode. The control bits for the reduced
power modes are in the PCON register.

February 1989

The 83C752 manipulates operands in three memory address spaces. The first is the program memory space
which contains program instructions as well as constants
such as look-up tables. The program memory space contains 2Kbytes in the 83C752.
The second memory space is the data memory array
which has a logical address space of 128 bytes. However,
only the first 64 bytes (0 to 3FH) are implemented in
the 83C752.
The third memory space is the special function register
array having a 128 byte address space (80H to FFH).
Only selected locations in this memory space are used
(see Table 23). Note that the architecture of these
memory spaces (internal program memory, internal data
memory, and special function registers) is identical to
the 80C51 and the 83C752 varies only in the amount of
memory physically implemented.
The 83C752 does not directly address any external data
or program memory spaces. For this reason, the MOVX
instructions in the 80C51 instruction set are not implemented in the 83C752, nor are the alternate I/O pin
functions RD and WR.
110 Ports
The I/O pins provided by the 83752 consists of port 0,
port 1, and port 3.
Port 0
Port 0 is as-bit bi-directional I/O port and includes alternate functions on some pins of this port. Pins PO.3
and PO.4 are provided with internal pullups while the
remain.ing pins (PO.O, PO.1 and PO.2) have open drain
output structures. The alternate functions for port 0 are:
PO.O SCL - the 12C bus clock
PO.1 SDA - the 12C bus data
PO.4 PWM - the PWM output
If the alternate functions, 12C and PWM, are not being
used then these pins may be used as I/O ports.
Port 1
Port 1 is an 8-bit bi-directional 110 port whose structure
is identical to the 80C51, but also includes alternate input functions on all pins. The alternate pin functions for
port 1 are:
Pl.0-Pl.4 - ADCO-ADC4 - AiD converter analog inputs
Pl.5 INTO - external interrupt 0 input
Pl.6 INT1 - external interrupt 1 input
Pl.7 - TO - timer 0 external input

2-162

User's Guide

Signetics Microprocessor Products

8XC752

Section 2 - 8051 Derivatives
Table 23. 8XC752 Special Fuuction Registers
Description

Symbol

Accumulator
ACC'
ADAT#
AID result
ADCON# AID control
B Register
B"
DPTR:
Data pointer (2 bytes):
Data pointer low
DPL
DPH
Data pointer high

12CFG'#

12C configuration

Bit Address, Symbol or Alternative Port Function
Direct
LSB
Address MSB
E7
E5
E4
E3
E2
EI
EO
EOH
E6
84H
ENADC ADCI I ADCS LAADR21 AADRI AADRO
AOH
I FOH
FI
FO
F7
F5
F4
F3
F2
F6

OOH
OOH

82H
83H
DF
DE
D8H/RD SLAVEN MASTRQ

12C control

98H/RD

12DAT*#

Pc data

WR
99H/RD

12STA"#

I2C status

RDAT

ATN

CXA
RDAT
WR XDAT
FF
F8H

IDLE
0
X
FE

IE"#
PooH
PI*#
P3"#
PCON#

Interrupt enable

Port 0
Port 1
Port 3
Power control

A8H
80H
90H
BOH
87H

PSW*
PWCM#
PWENA#
PWMP#
RTL#
RTH#
SP
TL#

Program status word
PWM compare
PWM enable
PWM prescaler
Timer low reload
Timer high reload
Stack pointer
Timer low

DOH
8EH
FEH
8FH
8BH
8DH
81H
8AH

TH#
TCON"#

Timer high
Timer control

8CH
88H

TIRUN

CTl

CTO

CTl

~ CTO

DRDY

ARL

STR

STP

MASTER

CSTR
0
X
FB

CSTP
0
X
FA

XSTR
0
X
F9

AD
ETI

96
B6

95
B5

D6
AC

D5
FO

8F
GATE

8E
CIT

XSTR

XDATA XACTVJMAKSTRjMAKSTP

AE
EAD

CDR CARL
0
0
X
X
FD
FC

IDLE

CLRTI~T1RUN~

WR SLAVEN MASTRQ
9F
9E
I2CON"#

Reset Value
OOH
OOH
COH
OOH

I -

8D
TF

AC
ES
84
94
B4

AB
I EPWM
83
93
B3

I -

D4
RSI

I -

8C
TR

D3
RSO

D2
OV

8B
lEO

8A
ITO

89
IEI

98
-

81H

XSTP
0
80H
X
F8
XSTP xOlOOOOOB

A9
A8
ETO I EXO
81
80
91
90
BI
BO
PD ~ IDL
DI
DO
P
-

AA
EXI
82
92
B2

OOOOxxOOB

OOH
xxxlllllB
FFH
FFH
xxxxOOOOB

OOH
xxxxxxxxB
PWE FEH
OOH
OOH
DOH
07H
DOH

88
ITI

OOH
OOH
OOH

• = SFRs are bIt addressable.
# = SFRs are modified from or added to the 80C51 SFRs.
If the alternate functions INTO, INTI, or TO are not
being used, these pins may be used as standard I/O
ports. If the ND converter is not enabled, pins
Pl.O- Pl.4 can be used as standard I/O pins.

Port 3
Port 3 is an 8-bit bi-directional I/O port whose structure
is identical to the 80C5l. Note that the alternate functions associated with port 3 of the 80C51 have been
moved to port I of the 83C752 (as applicable). See Figure 63 for port bit configurations.
PWM Outputs

The single PWM output is an alternate function assigned
to PO.4, and can be used to output pulses of programmable length and interval. The repetition frequency is
defined by an 8-bit prescaler which generates the clock
for the counter. This prescaler is contained in the
PWMP register.

February 1989

The 8-bit counter counts from 0 to 254 inclusive. The
value of the 8-bit counter is compared to the contents of
the compare register, PWM. When the content's value
matches that of the PWM register, the PWM output is
set high. When the counter reaches zero, the PWM output is set low. The pulse width ratio (duty cycle) is defined by the contents of the compare register and is in
the range of 0 to I programmed in increments of 11255.
The PWM output can be set continuously high by loading
the compare register with OOH and continuously low by
loading the compare register with FFH. The PWM output is enabled by setting the PWE bit in the PWM enable register, PWENA. When enabled, the output is
driven with a fully active strong pullup. When disabled,
the pin behaves as a normal bi-directional I/O pin.
When disabled, the counter remains active. The PWM
function is disabled by a reset condition. The PWM output is high during power-down and idle modes and the
counter is disabled.

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Signetics Microprocessor Products

8XC752

Section 2 - 8051 Derivatives
AID Converter
ALTERNATE
OUTPUT

READ
LATCH

The 83C752 contains a 5-channel multiplexed 8-bit ND
converter. The conversion requires 40 machine cycles
(40).lS at 12MHz oscillator frequency).

VDD

-I

INTERNAL
PULL·UP

The ND converter is controlled by the ND control register, AD CON. Input channels are selected by the analog
multiplexer by bits ADCON.O through ADCON.2. TI,e
ADCON register is not bit addressable.

INT BUS

WRITE TO
LATCH

ADCON Register

Lsn

MSB

READ PIN
ALTERNATE
INPUT
FUNCTION

ADCI

ADCS

Operation

ADC busy, start of a new conversion is
blocked.
Conversion completed, start of a new conversion is blocked.
Not possible.

o
ALTERNATE
OUTPUT
FUNCTION

READ
LATCH

Input Channel Selection

INT BUS

WRITE TO
LATCH

ADDR2

ADDRI

ADDRa

Input Pin

0
0
0
0
1

0
0
I
I
0

0
I
0
I
a

PI.O
Pl.l
PI.2
PI.3
PI.4

Position
ADCON.5
ADCON.4

READ PIN
ALTERNATE
INPUT
FUNCTION

ADCON.3

Figure 63. Port Bit Latches and 1/0 Buffers

The repetition frequency is given by:
ADCON.2
ADCON.l
ADCON.O

fose
fpWM

--------

2 x (1 + PWMP) 255
An oscillator frequency of 12MHz results in a repetition
range of 92Hz to 23.5KHz.

The low/high ratio of the PWM output is PWM / (255
PWM) for PWM values except 255. A PWM value of
255 results in the low PWM output.
If enabled, a PWM interrupt will occur when the PWM
counter overflows.

In order for the PWM output to be used as a standard
I/O pin, the PWM function needs to be disabled. The
PWM counter can still be used as an internal timer by
enabling the PWM interrupt.

February 1989

ADC not busy, a conversion can be started.

Symbol

Function

ENADC Enable AID function when ENADC - L
Disable AID function when ENADC - a.
Reset forces ENADC - O.
ADCI ADC interrupt flag. This flag is set when
an ADC conversion is complete. If IE.6 >=
1, an interrupt is requested when ADCI 1. The ADCI flag is cleared when conversion data is read. This nag is read only.
ADCS ADC start and status. Setting this bit starts
an ND conversion. Once set, ADCS
remains high throughout the conversion
cycle. On completion of the conversion, it
is reset at the same time the ADCI
interrupt flag is set. ADCS cannot be reset
by software.
AADR2 Analog input select.
AADRI Analog input select.
AADRO Analog input select. This binary coded
address selects one of the five analog
input port pins of PI to be input to the
converter. It can only be changed when
ADCI and ADCS are both low. AADR2 is
the most significant bit.

The completion of the 8-bit ADC conversion is flagged
by ADCI in the ADCON register and the result is stored
in the special function register ADAT.
An ADC conversion in progress is unaffected by an ADC
start. "D,e result of a completed conversion remains unaffected provided ADCI remains at a logic 1. While
ADCS is a logic 1 or ADCI is a logic 1, a new ADC
START will be blocked and consequently lost. An ADC

2-164

User's Guide

Signetics Microprocessor Products

8XC752

Section 2 - 8051 Derivatives
conversion in progress is aborted when the Idle or
Power-down mode is entered. The result of a completed
conversion (ADCI ~ logic 1) remains unaffected when
entering the Idle mode. See Figure 64 for an ND input
equivalent circuit.
The analog input pins ADCO-ADC4 may be used as digital inputs and outputs when the A/D converter is disabled by a 0 in the ENADC bit in ADCON. When the
ND is enabled, the analog input channel that is selected
by the ADDR2-ADDRO bits in ADCON cannot be used
as a digital input. Reading the selected ND channel as
a digital input will always return a 1. The unselected
ND inputs may always be used as digital inputs.
CounterlTimer
The 8XC752 counter/timer is designated Timer 0 and is
separate from Timer I of the 12C serial port and from
the PWM. Its operation is similar to mode 2 of the
80C51 counterltimer, extended to 16 bits. When Timer
o is used in the external counter mode, the TO input
(P1.7) is sampled every S4Pl. The counter/timer function is controlled using the timer control register
(TCON)
TCON Register
MSB
IGATEI CIT I TF

lEO

ITO

1E1

12C Serial 110
The I2C bus uses two wires (SDA and SCL) to transfer
information between devices connected to the bus. The
main technical features of the bus are:
•
•
•
•
•

A large family of 12C compatible ICs is available. See
the 12C section for more details on the bus and available
ICs.
The 83C752 I2C subsystem includes hardware to simplifY
the software required to drive the I2C bus. This circuitry
is the same as that on the 83C751. (See the 83C751 section for a detailed discussion of this subsystem).

LSB
IT1

Position Symbol
Function
TCON.7 GATE 1 - Timer 0 is enabled only when INTO pin is
high and TR is 1
o - Timer 0 is enabled only when TR is 1
TCON.6 CIT 1 - Counter operation from TO pin
o - Timer operation from internal clock
TCON.5 TF
1 - Set on overflow of TO
o - Cleared when processor vectors to interrupt routine and by reset
TCON.4 TR
1 - Enable timer 0
o - Disable timer 0
TCON.3 lEO 1 - Edge detected on INTO
TCON.2 ITO 1 - INTO is edge triggered
o - INTO is level sensitive
TCON.l lEi 1 - Edge detected on INTi
TCON.O ITl
1 - INTl is edge triggered
o - INTi is level sensitive

Interrupts
The interrupt structure is a seven source, one level interrupt system similar to the 8XC751. The interrupt
sources are listed below in their order of polling sequence priority (highest to lowest):
Priority
Highest

These flags are functionally identical to the corresponding 80C51 flags except that there is only one of the
80C51 style timers and the flags are combined into one
register.
A communications watchdog timer Timer I, is described
in the 12C section. In I2C applications, this timer is dedicated to time generation and bus monitoring for the
12C. In non-I2C applications, it is available for use as a
fixed time base.
The 16-bit timer/counter's operation is similar to mode
2 operation on the 80C51, but is extended to 16 bits.
The timer/counter is clocked by either 1/12 the oscillator frequency or by transitions on the TO pin. The CIT
pin in special function register TCON selects between
these two modes. When the TCON TR bit is set, the

February 1989

timer/counter is enabled. Register pair TH and TL are
incremented by the clock source. When the register pair
overflows, the register pair is reloaded with the values in
registers RTH and RTL. The value in the reload registers is left unchanged. The TF bit in special function
register TCON is set on counter overflow and, if the interrupt is enabled, will generate an interrupt (see Figure
65).

Lowest

Source
INTO
TFO
INTl
PWM
TI
SIO
ADC

Function
External interrupt 0
Timer flag 0
External interrupt 1
PWM counter overflow
l2C timer overflow
Serial port interrupt
A/D conversion complete

The vector addresses are as follows:
Vector
Source
Address
INTO
0003H
TFO
OOOBH
INTl
0013H
TIMER I
00lBH
SIO
0023H
ADC
002BH
PWM
0033H
Interrupt Control Registers
The 80C51 interrupt enable register is modified to take
into account the different interrupt sources of the
8XC752.

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Signetics Microprocessor Products

User's Guide

Section 2 - 8051 Derivatives

8XC752

.--

•
••

·-----·----~-------·1

S;~, R~~,

I~,

-j---1"-

Sm.

--U'V\,'\r"-~-t

Rm.
TO COMPARATOR

WV\r-+--I-------------MULTIPLEXER

c.
~NAlOGINPUT

Rm - O.S-3Kohms
Cs + Cc - 1SpF maximum
Rs - Recommended < 9.6Kohms for 1 LSB @ 12MHz
NOTE:
Because the analog to digital converter has a sampled-data comparator, the input looks capacitive to a source. When a
conversion is initiated, switch Sm closes for 8tcy (8JlS @ 12MHz crystal frequency) during which time capacitance Cs + Cc
is charged. It should be noted that the sampling causes the analog input to present a varying load to an analog source.

Figure 64. Am Input: Equivalent Circuit
Interrupt Enable Register
MSB

LSB

I EA IEAD I ETI I ES IEPWM I EXI I ETO I EXO I
Position Symbol
EA

1E.7
1E.6
IE.S
1E.4
1E.3
1E2
IE.I
IE.O

EAD
ETI
ES
EPWM
EXI
ETO
EXO

Function
Global interrupt disable when EA = 0
ND conversion complete
Timer I
12C serial port
PWM counter overflow
External interrupt I
Timer 0 overflow
External interrupt 0

Power-Down and Idle Modes

ing Timer I, the counter portion of the PWM, and the
interrupts. Upon powering-up the circuit, or exitiug from
idle mode, sufficient time must be allowed for stabilization of the internal analog reference voltages before an
ND conversion is started.
Instruction Set
The instruction set of the 83C7S2 is identical to the
80CSI except that:
MOVX, LCALL and UUMP are not implemented.
these instructions are executed, the appropriate
number of instruction cycles will take place along with
external fetches, however, no operation will take place.
The UMP may not respond to all program address bits.
If

The 8XC752 includes the 80C51 power-down and idle
mode features. The functions that continue to run while
in the idle mode are Timer 0, the 12C interface includFebruary

1989

2-166

Signetics Microprocessor Products

User's Guide

Section 2 - 8051 Derivatives

osc

8XC752

112

TO PIN - - - - - - - - - - - '
TR

GATE
INTO PIN

RTL

RTH

Figure 65. 83C752 CounterrI'imer Block Diagram
Special Function Registers
The special function registers (directly addressable only)
contain all of the 8XC751 registers except the program
counter and the four register banks. Most of the 21 special function registers are used to control the on-chip
peripheral hardware. Other registers include arithmetic
registers (ACC, E, PSW), stack pointer (SP) and data
pointer registers (DPH, DPL). Nine of the SFRs are bit
addressable.
Data Pointer
The Data Pointer DPTR) consists of a high byte (DPH)
and a low byte (D PL). In the 80C51, this register allows
the access of external data memory using the MOVX
instruction.

Ports 0, 1, 2
PO, P1, P2 are the latches of Ports 0, 1, and 2, respectively. P1 and P2 are each 8 bits wide while PO has only
five valid bits since it represents a 5-bit port.

February 1989

2-167

INT

Signetics

S87C752
CMOS Single-Chip 8-Bit
Microcontroller

Microprocessor Division

DESCRIPTION
The Signetics S87C752 offers many of
the advantages of the SC80C51 architecture in a small package and at low
cost.
The S87C752 Microcontroller is fabricated with Signetics high-density CMOS
technology. Signetics epitaxial substrate
minimizes CMOS latch-up sensitivity.
The S87C752 contains a 2K x 8 EPROM, a 64 x 8 RAM, 21 I/O lines, a
16-bit auto-reload counter/timer, a fixedrate timer, a seven-5ource fixed-priority
interrupt structure, a bidirectional InterIntegrated Circuit (12C) serial bus interface, an on-chip oscillator, a five channel multiplexed 8-bit A/D converter, and
an 8-bit PWM output.
The onboard inter-integrated circuit (12C)
bus interface allows the S87C752 to operate as a master or slave device on the
12C small area network. This capability
facilitates I/O and RAM expansion, access to EEPROM, processor-to-processor communication, and efficient interface to a wide variety of dedicated 12C
peripherals.

Preliminary Specification

FEATURES
• EPROM version of S83C752
• Available in erasable quartz lid
or One-Time Programmable
plastic packages
• SC80C51 based architecture
• Inter-Integrated Circuit (12C)
serial bus interface
• Small package sizes
- 28-pin DIP
- 28-pin PlCC
• Wide oscillator frequency range
• low power consumption:
- Normal operation: less
than 11mA @ 5V, 12MHz
- Idle mode
- Power-down mode
• 2K x 8 EPROM, 64 x 8 RAM
• 16-bit auto reloadable counter!
timer
• 5 channel 8-bit AID converter
• 8-bit PWM output/timer
• Fixed-rate timer
• Boolean processor
• CMOS and TTL compatible
• Well suited for logic replacement, consumer and industrial
applications

PIN CONFIGURATION

P3.4/A4 1

TOP VIEW
INDEX

,om! ,,~ ~['"

lOGIC SYMBOL

19
12
18
TOP VIEW

Pin
1
2
3
4
5
6
7

10
11

12
13
14

Function
P3.4/A4
P3.3/A3
P3.2/A2/A10
P3.1/A1/A9
P3.01 AOI A8
PO.2iVpp
PO.1/SDAI
OE-PGM
PO.O/SCLI
ASEL
RST
X2
X1
Vss
P1.0/ADCO/DO
P1.1/ADC1/D1

Pin
15
16
17
18
19
20

21
22
23
24
25
26
27
28

Function
P1.21 ADC2/D2
P1.31 ADC3/D3
P1.41 ADC4/D4
AVss
AVec
P1.5iiNi'ii/D5
p1.6iiFJ'fi ID6
P1.7/TO/D7
PO.3
PO.4/PWM
OUT
P3.7/A7
P3.6/A6
P3.5/A5
Vee

NOTE:

AO-Al0 and 00-07 available for EPROM
verify only.

February 1989

2-168

Preliminary Specification

Signetics Microprocessor Products

S87C752

CMOS Single-Chip 8-Bit Microcontroller
ORDERING INFORMATION
S87C752-

L,~.".~."

A28 - Plastic PLCC (OTP)
F28 - Ceramic DIP
N28 - Plastic DIP (OTP)

Speed and Temperature Range:

12345-

3.5
3.5
0.5
3.5
3.5

to
to
to
to
to

12MHz,
12MHz,
12MHz,
16MHz,
16MHz,

OoC to +70°C
_40°C to +85 °c
OOC to +70° C
OOC to +70° C
-40°C to +85 °c

Part Number

PART NUMBER SELECTION
Speed
Temperature and Package

S87C752-1 N28

3.5 to 12MHz

o to +70°C, Ceramic DIP
o to +70°C, Ceramic DIP
o to +70°C, Ceramic DIP
o to +70°C, Plastic DIP

S87C752-2N28

3.5 to 12MHz

. -40 to +85°C, Plastic DIP

S87C752-3N28

0.5 to 12MHz

S87C752-4N28

3.5 to 16MHz

S87C752-5N28

3.5 to 16MHz

S87C752 1F28

3.5 to 12MHz

S87C752-3F28

0.5 to 12MHz

S87C752-4F28

3.5 to 16MHz

S87C752 1A28

3.5 to 12MHz

S87C752-2A28

3.5 to 12MHz

S87C752-3A28

0.5 to 12MHz

S87C752-4A28

3.5 to 16MHz

S87C752 5A28

3.5 to 16MHz

o to +70°C,
o to +70°C,

Plastic DIP
Plastic DIP

-40 to +85°C, Plastic DIP

o to +70°C,

Plastic LCC

-40 to +85°C, Plastic LCC

o to +70°C,
o to +70°C,

Plastic LCC
Plastic LCC

-40 to +85°C, Plastic LCC

BLOCK DIAGRAM

----------~~

_____ J

February 1989

----------l

2-169

Signetics Microprocessor Products

Preliminary Specification

CMOS Single-Chip 8-Bit Microcontroller

S87C752

PIN CONFIGURATION (DIP and PLCC)
MNEMONIC PIN NO. TYPE
Vss
Vee
PO.0-PO.4

12
28
8-6,
23, 24

110

NAME AND FUNCTION
Circuit ground potential.
Supply voltage during normal, idle, and power-down operation.
Port 0: Port 0 is a 5-bit bidirectional port. Port 0.0 - PO.2 are open drain. Port 0.0 - PO.2 pins
that have ones written to them float, and in that state can be used as high-impedance inputs.
PO.3-P004 are bi-directional 110 port pins with internal pullups. Port 0 also serves as the serial
12C interface as shown in the pinout diagram. When this feature is activated by software, SCL and
SDA are driven low in accordance with the 12C protocol. These pins are driven low if the port
register bit is written with a 0 or if the 12C subsystem presents a O. The state of the pin can
always be read from the port register by the program. Port 0.3 and 004 have internal pull-ups that
function identically to port 3. Pins that have ones written to them are pulled high by the internal
pull-ups and can be used as inputs.
To comply with the 12Cspecification, PO.O and PO.1 are open drain bidirectional 110 pins with the
electrical characteristics listed in the tables that follow. While these differ from 'standard TTL'
characteristics, they are close enough for the pins to still be used as general-purpose 110 in
non-12C applications.

P1.0-P1.7

110

SDA (PO.1) 12C data.

8
24

110
0

6
7

I
I

SCl (PO.O) 12C clock.
PWM OUT (PO.4) - This pin also functions as the pulse width modulated output. When the PWM
is enabled, the output (PO A) has a strong active pull-up and cannot be used as an input. (see DC
Electrical Characteristics).
Port 0 also provides alternate functions for programming the EPROM memory as follows:
Vpp (PO.2) - Programming voltage input.
OE/PGM (PO. 1) - Input, OE/PGM, which specifies verify mode (output enable) or the prrogram
mode.
OE/PGM - 1 output enabled (verify mode)
OE/PGM - 0 program mode.
ASEl (PO,O) - input which indicates which bits of the EPROM address are applied to port 3.
ASEL - 0 low address byte available on port 3.

13-17,
20-22

110

20
21
22
13-17

P3.0-P3.7

ASEL - 1 high address byte is available on port 3 (only the three least significant bits are used).
Port 1: Port 1 is an 8-bit bidirectional 110 port with internal pullups. Port 1 pins that have ones
written to them are pulled high by the internal pull ups and can be used as inputs. PO.3-P004 pins
are bi-directional 110 port pins with internal pull ups. As inputs, port 1 pins that are externally
pulled low will source current because of the internal pullups. (See DC electrical characteristics:
. IILl· Port 1 also serves the special function features of the SC80C51 family as listed below:
INTO (Pl.5): External interrupt
INTl (Pl.6): External interrupt
TO (Pl.7): Timer 0 external input
ADCO (Pl.0) - ADC4 (Pl.4) - Port 1 also functions as the inputs to the five channel multiplexed
AID converter. These pins can be used as outputs only if the AID function has been disabled.
These pins may be used as inputs while the AID converter is enabled.
Port 1 serves to output the addressed EPROM contents in the verify mode and accepts as inputs
the value to program into the selected address during the program mode.
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pullups. Port 3 pins that have ones
written to them are pulled high by the internal pullups and can be used as inputs. As inputs, port
3 pins that are externally being pulled low will source current because of the pull ups (See DC
electrical characteristics: IILl. Port 3 also functions as the address input for the EPROM memory
location to be programmed (or verified). The 11-bit address is multiplexed into this port as specified by PO.O/ASEL.

5-1
27-25

110

RST

Reset: A high on this pin for two machine cycles while the oscillator is running resets the device.
An internal diffused resistor to VSS permits a power-on RESET using only an external capacitor
to Vee. After the device is reset, a 10-bit serial sequence., sent LSB first, applied to RESET,
places the device in the programming state allowing programming address, data and Vpp to be
applied for programming or verification purposes. The RESET serial sequence must be synchronized with the X1 input.

X2
AVcc
AVss

10
19
18

Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator
circuits. X1 also serves as the clock to strobe in a serial bit stream into RESET to place the device in the programming state.
Crystal 2: Output from the inverting oscillator amplifier.
Analog supply voltage and reference input.
Analog supply and reference ground.

February 1989

I
I

2-170

Preliminary Specification

Signetics Microprocessor Products

CMOS Single-Chip 8-Bit Microcontroller
OSCILLATOR CHARACTERISTICS
X1 and X2 are the input and output, respectively, of an inverting amplifier
which can be configured for use as an
on-<:hip oscillator.
To drive the device from an external
clock source, X1 should be driven while
X2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, because the input to
the internal clock circuitry is through a
divide-by-two flip-flop. However, minimum and maximum high and low times
specified in the data sheet must be
observed.
IDLE MODE
In the idle mode, the CPU puts itself to
sleep while all of the on-<:hip peripherals
stay active, except for the A/D converter and the PWM output. The instruction to invoke the idle mode is the last
instruction executed in the normal operating mode before the idle mode is activated. The CPU contents, the on-<:hip
RAM, and all of the special function registers remain intact during this mode. The
idle mode can be terminated either by
any enabled interrupt (at which time the
process is picked up at the interrupt
service routine and continued), or by a
hardware reset which starts the processor in the same manner as a power-on
reset.
POWER-DOWN MODE
In the power-J.7

ADDRESS STROBE

PO.O/ASEL

Vss

Pl.0-f>1.7

PROCRAMMING
PULSES

PO.l

Vpp /VIH VOLTAGE
SOURCE

PO.2

Cll< SOURCE

DATA BUS

XTALI
RESET
CONTROL
LOGIC

1
I

RESET

Figure 4. Programming Configuration

XTALI
MIN 2 MACHINE
jo--CYCLES

RESET~

PO.2

UNDEFINED I

PO. 1

UNDEFINED I

.1.
TEN BIT SERIAL COOE
-I
~1~B~IT~0~~B~IT~1-L~B~IT~2-L~B~IT~J~I~B~IT~4~I~B~rr~5~I~B~IT~8~~B~IT_7~~B~IT~8~~BI~T~9~1______

Figure 5. Entry Into ProgramNerify Modes

February 1989

2-178

"Tl

Cl>
0-

-<'"

(j)

<0
0>
<0

(j)

PO.2 (Vpp)

s:
(;'
(3
'0

::J

()
\I)

0
:::r

8.c:

"g.

\I)

(l)

12.75V

(j)
CO
-....,J

o-...,J
<.T1

I\.)

'0
\I)

()

:::;;

(;'

o·~

Section 3
Application Notes

Signetics

Microprocessor Products

INDEX
AN408
AN417
AN418
AN420

SC80C451 Operation of Port 6 ..................... 3-1
256K Centronics Printer BufferUsing the SC87C451 Microcontroller . . . . . . . . . . . . . . .. 3-12
CounterfTimer 2 of the 83C552 . . . . . . . . . . . . . . . . . . .. 3-26
Using up to 5 External Interrupts on 8051 Family
Microcontrollers .............................. " 3-33

Signetics

AN408
SC80C451 Operation of
Port 6
Application Note

Microprocessor Division

INTRODUCTION

OPERATION

The features of the 80C451 are shared
with the 80C51 or are conventional except for the operation of port 6. The
flexibility of this port facilitates highspeed parallel data communications. This
application note discusses the use of
port 6 and is divided into the following
sections:
1. Port 6 as a processor bus interface.
2. Using port 6 as a standard pseudo bidirectional I/O port.
3. Implementation of parallel printer
ports.
This information applies to all versions of
the part: 80C451, 83C451 and the 87C-

451.
PORT 6 AS A PROCESSOR
BUS INTERFACE
Port 6 allows use of the 80C451 as an
element on a microprocessor type bus.
The host processor could be a general
purpose MPU or the data bus of a
microcontroller like the 80C451 itself.
This feature allows single or multiple
80C451 controllers to be used on a bus
as flexible peripheral processing elements. Applications could include keyboard scanners, serial I/O controllers,
servo controllers, etc.

use as a bus interfaca (see Figure 2). This
prevents the interfaca from disrupting data on
the bus of the host processor during powerup. Software initialization of the CSR (Control
Status Register) is not required. A dummy
read of port 6 may be required to clear the
IBF (Input Buffer Full) flag since it could be
set by tum on transients on the bus of the
host processor. On reset the CSR of the
63C451 is programmed to allow the following:
1. AFLAG is an input controlling the port
select function. If AFLAG is high. the
contents of the CSR is output on port 6
when the port is read by the host. If
AFLAG is low. then the contents of the
output latCh is output when port 6 is read
by the host.
2. BFLAG is an input controlling· the port
enable function. In this mode when
BFLAG is high. the input latCh and the
output drivers are disabled and the flags
are not affected by the ~ (Input Data
Strobe) or ~ (Output Data Strobe)
signals. When BFLAG is low. the port is
enabled for reading and writing under the
control of ~ and DDS pins.

HOST
PROCESSOR

Ill!
WI!

Figure 1 shows one possible example of an
80C451 on a memory bus. This arrangement
allows the main processor to query port 6 for
flag status without interrupting the 80C451. If
the address decoder. shown in Figure 1.
enables port 6 on the 80C451 when the
address is 6000H or B001 H. and the address
line AO controls the port select feature. then
the host processor can read and write to port
6 using address BOOOH. Since the port select
function Is being controlled by the address
Mne AO. the CSR contents can be read by the
host processor at address 6001 H.

On reset. port 6 is programmed correctly for

By testing the CSR contents in this way. the
host processor can tell if new data has been
wriIIento the port 6 output latch Since it last
read the port or if the 80C451 has read the
last byte that the host wrote to the port.
Conversely the BOC451 can poll the flags in
its CSR to see if the host processor has
written to or read from port 6 since the last
lime It serviced the port.
If desired. an interrupt sourca for the B0C451
can be derived easily from the port enable
sourca as shown by the dashed line in Figure

•

r--

r---

-~
WI!

,
Ill!

(AFLAII)

ill!

LA1tlH

811.

e0C451

ADDRESS

ADO-AlJ7

ALE

D!
o...._

AI-/IA

iliL
II

(BF1.AO)

Figure 1. An 83C451 on

-'"
j,.

February 1989

II!

ADDRESS

,A- ~
,

"'"---

Microprocessor Memory Bus

3-1

i"f--

sa IIlIIIlIIIPI

DO-D7

-- -

74HCT373

r--

IIIT6

t __ Jt

Application Note

Signetics Microprocessor Products

SC80C451

Operation of Port 6
SOFTWARE EXAMPLES
To write to port 6 on the bus shown in Figure
I, the host processor first reads the CSR
contents at address 8001 H, and tests the

Input buffer luliliag (CSR bit 0). lIthe flag is
clear the host writes a byte to address
8000H. This loads the input buffer latch of
port 6 and sets the input buffer full flag.

Conversely tha 80C451 polls the ISF flag and
reads a byte from port 6 when ~ finds the flag
set. The flag is automatically reset when this
internal read 0CCUfS.

80C451 ROUTINE TO READ ONE BYTE FROM HOST VIA PORT 6
RCVR:

JNS CSR.O,RCVR
MOV A,P6
RET

;TEST ISF FLAG
;WHEN FLAG IS SET READ BYTE

8OC51 ROUTINE TO WRITE ONE BYTE TO THE 83C451 PORT 6
If the host processor is an 8OC51 the loIlowing routine will write a byte of date to the 80C451. The date involved is passed to the routine through
register 1.
XMIT:
TEST:

MOV OPTR,8001 H
MOVX A,@OPTR
JS ACC.O,TEST
MOV OPTR,8000H
MOV A,Rl
MOVX @DPTR,A
RET

;REAO THE CSR
;TEST ISF FLAG

;WRITE DATA TO THE 451

80C451 ROUTINE TO WRITE ONE BYTE TO HOST VIA PORT 6
Routines for date transfer in tha opposite direction
XMIT:

JS CSR.l,XMIT
MOV P6,A
RET

are

similar to the above two. The 80C451 version is given below.

;TEST OBF FLAG
;WRITE DATA

CSR 7

CSR 6

CSR5

CSR 4

CSR 3

CSR 2

CSR 1

CSRO

MBI

MBO

MAl

MAO

OBFC

IOSM

OBF

IBF

FIgure 2. CSR Programmed to Allow Port 6 a. a Bua Interface

February 1989

3-2

Signetics Microprocessor Products

Application Note

Operation of Port 6

SC80C451

USING PORT 6 AS A
STANDARD QUASI·
BIDIRECTIONAL 1/0 PORT
To use port 6 as a common II 0 port, all 01 the
control pins are tied to ground (see Figure 3).
On hardware reset, bits 2 - 7 in the CSR are
set to one. Port operation and electrical
characteristics become identical to port 1 on
the aOCSl and the 80C451 ports I, 4, and 5.
No software initialization is required.
" desired, AFLAG and BFLAG can be used
as outputs while port 6 is operating as a
standard quasi-bidirectional 110 port (see Figure 4). In this case, only iDS and ODS are tied
to ground and the CSR is initialized to allow
operation 01 AFLAG and BFLAG as simple
outputs (see Figure 5).

IMPLEMENTATION OF
PARALLEL PRINTER PORTS
USING PORT 6

Figure 4. Standard 110 Port on Reset
with AFLAG and BFLAG as Outputs

Figure 3_ Standard I/O Port on Reset
common printer to be handled by a single
chip:
1. The features 01 port 6 allow a parallel
printer port to be designed with only line
driving and receiving chips required as
additional hardware.
2. The onboard UART allows RS232 interfacing with only level shifting chips add-

ed.

The 80C451 is an excellent choice lor a
printer controller. The 80C451 has the lacilities to permit all 01 the intelligent leatures 01 a

The B-bit parallel ports 0 to 6 are ample
to drive onboard control functions, even
when ports are used for external memory
access, interrupts and other functions.

The RAM addressing ability 01 ports 0
and 2 can be used to address up to 64K
bytes 01 a hardware buffer/spooler. AFLAG and BFLAG as simple outputs (see
Figure 5).
The 64K byte ROM addressing capability
allows space for the most sophisticated
software.

In addition, either end 01 a parallel interface
can be implemented using port 6, and the
interfaces can be interrupt driven or polled in
either case.

eSR 7

eSR 6

CSR 5

CSR 4

CSR 3

CSR 2

CSR 1

CSR 0

MBI

MBO

MAl

MAO

OBFC

IOSM

OBF

IBF

Figure 5_ CSR Programmed to Allow AFLAG and BFLAG to Operate as Outputs and Port 6 as a Standard 110 Port

DATA TRANSFER SIGNAL PINS

TYPICAL AUXILIARY PIN FUNCTIONS

Pin No.

Ground Return
Pin No.

Signal

Pin No_

PAPER OUT

Signal

DATA 1

AuTO LlN~

DATA 2

LOGIC GROUND

DATA 3

CHASSIS GND

DATA 4

GROUND RETURN

DATA 5

~~SEi l5~iNTER

DATA 6

DATA 7

GROUND RETURN

DATA a

ACKNLG

BUSY

Figure 6. Parallel Prtnter Interface Pin Functions

February 1989

"EED

3-3

Signetics Microprocessor Products

Application Note

Operation of Port 6

SC80C451

>r_

TAANSMmER GENERATED SIGNALS

DATA_
STROBE _ _

P~~t~~=V-,,::O;::;;'I~-l-+------------

RECEIVER GeNERATED SIGNALS
HANDSHAKE TYPE 1

: -----J/----------t-,..--~-f-=-yHANDSHAKE TYPE 2

BUSY

,r --- - - - - -~- - -

"'C ~~

----1===vWF'"""
Figure 7. Parallel Printer Interface Signals

THE INTERFACE
Data transfer on a parallel printer interface
occurs across eleven signal lines. The other
conductors on the standard plug are used as
ground returns or for auxiliary functions (see
Figure 6). Only the data transfer signals will
be considered.

printers using generic parallel interfaces. This
fact influences the design of both port hardware and software. A good transmitter should
be able to drive devices with all three styles
of handshakes and a good receiver should
generate the handshake most likely compatible with any transmitter.

The Data Transfer Format

The Variations

The parallel printer interfaces are far more
standardized in features than their serial
counterpart. However at least three signifieant variations exist in handshake style in

Type 1 - Figure 7 shows a common style of
handshake and is the style that will be implemented in the receiver examples. A busy
signal and an acknowledge strobe pulse are
generated for every byte received.

February 1989

3-4

Type 2 - Another style of handshake generates a busy signal only when the printer will
not be aple to accept more data for a
relatively long time. Acknowledge pulses are
created after every byte received. When the
busy signal is generated after a byte is
received, the associated acknowledge pulse
does. not occur until after the busy signal
returns to logic zero. (see Figure 7).
Type 3 - A third handshake style does not
generate acknowledge pulses. but a busy
signal is produced after every byte is received.

Application Note

Signetics Microprocessor Products

SC80C451

Operation of Port 6
PARALLEL PRINTER
INTERFACES USING POLLING
Transmitter Operation
This application illustrates the flexibility of the
port 6 logic in solving an applications problem. We need to be able to handle all types of
acknowledge signals that might be received
by the transmitter. We will use the ODS pin
and output buffer full flag logic to record the
receipt of the acknowledge pulse (see Figure
8), but not all parallel receivers generate
acknowledge pulses. We could poll the busy
signal line, but not all receivers generate busy
signals for each byte received; so lack of a
busy signal does not imply that we can send
another byte. We can, however, expect an
acknowledge pulse very shortly after the end
of a busy signal if one is going to arrive at all.
So we can send a new data byte after having
received either a positive transition on the
acknowledge line, or shortly after receiving a
negative edge on the busy line.

The GSR is programmed to the output only
mode. In this mode the ODS pin does not
control the output drivers but only the output
buffer full flag. The flag serves to record the
positive transition of the acknowledge signal.
The input latch is not used, but the IDS pin is
used to set the input buffer full flag. This is
used to record the negative transition at the
end of the busy signal. Dummy reads by the
80C451 of port 6 will be used to clear the flag.
In this example, the AFLAG mode is set only
to place the port in the output only mode. The
AFLAG pin is not actually used (see Figure
10).
The transmitter's GSR (control status register) is programmed to the following mode
(see Figure 9):

GSR bit 6 controls the BFLAG output and
therefore the strobe line.

The OBF (output buffer full) flag controls
the AFLAG output.

BUS

DRIVER

RECEIVER

The OBF is cleared on the positive edge
of the ODS input.

The IBF flag is cleared on the negative
edge of the lOS strobe.

NOTE:
With this combination of modes set, port 6 is
in the output only mode.

Receiver Operation
In receiver operation, the IDS input is used to
latch in the data transmitted on receipt of the
strobe pulse. The receiver's GSR is programmed to allow the following:
1. The input buffer full flag is output through
the BFLAG pin and is used as the busy
signal to the transmitter.
2. The IBF flag is set and data is latched on
the positive edge of IDS.
3.

Writing to the GSR bit 4 controls the
AFLAG output and therefore the acknowledge line.

AFLAG

RECEIVER

TRANSMITTER

Figure 8. Interconnection for a Parallel Interface Using Polling

CSR 7

CSR 6

CSR 5

CSR 4

CSR 3

CSR 2

CSR 1

CSR 0

MBI

MBO

MAl

MAO

OBFC

IOSM

OBF

IBF

Figure 9. CSR Programmed for Polled Transmitter Operation

February 1989

3-5

Application Note

Signetics Microprocessor Products

SC80C451

Operation of Port 6

Figure 10. Flow Chart of Polled Parallel Transmitter Operation

CSR 7

CSR 6

CSR 5

CSR 4

CSR 3

CSR 2

CSR 1

CSR 0

MBI

MBO

MAl

MAO

OBFe

IOSM

OBF

IBF

Figure 11. CSR Programmed for Polled Parallel Receiver Operation

February 1989

3-6

Application Note

Signetics Microprocessor Products

SC80C451

Operation of Port 6

Figure 12. Flow Chart of Polled Parallel Receiver Operation

SOFTWARE EXAMPLES
This polled parallel transmit routine outputs one byte passed to it in the accumulator.

WAIT:

MOV CSR,#OS4H
JB P5.0
MOV PS,ACC
MOV R1,PS
MOV R1,#02H
CLEAR CSR.S
DJNZ R1,$
SETB CSR.S
JNB CSR.1.0UT
JNB CSR.O.WAIT
RET

;INITIALIZE PORT S OPERATING MODE
;WAIT IF BUSY SIGNAL IS HIGH
;OUTPUT DATA
;DUMMY READ TO CLEAR IBF FLAG
;INITIALIZE DELAY COUNTER
;START STROBE PULSE
;TIME S MICROSECOND STROBE PULSE
;END STROBE PULSE
;EXIT IF ACKNOWLEDGE RCV'D
;EXIT IF NEGATIVE BUSY EDGE RCV'D

This polled parallel receive routine places one byte in the accumulator each time it is called.
P INIT:
PIN:

MOV CSR,#09CH
MOV R7,PS
JNB CSR.O
CLR CSR.4
MOV R7,#02H
DJNZ R7,$
MOV A,PS
MOV R7,#02H
DJNZ R7,$
SETB CSR.4

;INITIALIZE PORT S OPERATING MODE
;DUMMY READ TO CLEAR IBF FLAG
;INPUT BUFFER LATCH FULL?
;BEGIN ACKNOWLEDGE PULSE
;INITIALIZE DELAY COUNTER
;TIME ACKNOWLEDGE PULSE
;READ BYTE - CLEAR BUSY SIGNAL
;INITIALIZE DELAY COUNTER
;TIME ACKNOWLEDGE PULSE
;END ACKNOWLEDGE PULSE

RET

February 1989

3-7

Application Note

Signetics Microprocessor Products

SC80C451

Operation of Port 6
INTERRUPT DRIVEN PARALLEL
PRINTER INTERFACE
Transmitter Operation
The transmitter's CSR (control status register) is programmed to the following mode
(see Figure t4):
1. CSR bit 6 controls the BFLAG output and
therefore the strobe line.
2.

The OBF (output buffer full) flag controls
the AFLAG output.

The OBF is cleared on the positive edge
of the ODS (output data strobe) input.

Tha IBF flag is set on the negative edge
of the IDS (input data strobe) pin.

NOTE:
With this combination of AFLAG and BFLAG
modes set, port 6 is in the output only mode.
The output drivers are always enabled and
the 008 input is only used to clear the OBF
flag.
INTO is programmed to be negative edge
sensitive and is connected to the OBF flag
through the AFLAG pin. The OBF is cleared
on the positive edge of 008. The net result is
that INTO is triggered on the end of the ACK
pulse (a positive edge). This signals the

transmitter that another byte may be transmitted. The transmitting 83C451 is free to do
other tasks prior to this interrupt.
In this routine, Figure 15, the main program
establishes a buffer in data memory ended by
an ASCII end of text character. To begin
outputting the buffer the routine PSEND is
called. The rest of the buffer is emptied by the
interrupt vectors to PSENDI.
For printers which generate acknowledge
pulses, output rates of 25k transfers per
second are achieved. Timer generated inter·
rupts are used to periodically return program
execution to the routine to service non-acknowledging printers and to provide a timeout
feature. Non acknowledging printers are serviced at a rate of about 2.5k transfers per
second. This maximum rate may be varied by
adjusting the timer reload value. As written,
the time out procedure attempts to retransmit
a byte when the printer has not acknowledged for an excessively long time.

Receiver Operation
In receiver operation, the iDS input is used to
latch in the data transmitted on receipt of the
strobe pulse. The receiver's CSR is programmed to allow the following (see Figure
16):

The input buffer full flag is output through
the BFLAG pin and is used as the busy
signal to the transmitter. The IBF flag is
set and data is latched on the positive
edge of IDS.

Writing to the eSR bit 4 controls the
AFLAG output and therefore the ac·
knowledge line.

The receiver is interrupted on the negative
edge of the data strobe. Data is latched in on
the positive edge of the strobe pulse (see
Figure 17). Since the strobe pulse is normally
very short there is little time lost between
receiving the interrupt and having valid data in
the input latch. The receiver is free to do
other tasks prior to receiving the INTO inter·
rupt.

SOFTWARE EXAMPLES
The software for the interrupt driven parallel
receiver is similar to the polled receiver example. However, after an interrupt is received,
this routine checks to confirm that data has
been latched by the positive edge of the
strobe pulse before proceeding with the routine.

lm 1.---+-=-=-+-.... :>-.... ~

BFLAG

iIiTli
Ifm
~

t-t-

I\)
(]l
(j)

cr
....
c
~

....

DB25

'"
co

P4,J

fINT1~

87C451~.1
PLCC

18U~?

2J
UJ

C>
U2

PS.5
PM

~g]

P6.1

p------.----------,

~ SLCT
fERROR
::m
i oPE
BUSY
0
0

IODS~

,I),

4...he
-

PRINTER
OUTPUT
PORT

i!::

.-+

.....
0

:
:

::J
0
(J)

"U
:::::!,

OEa OEb

8 J
1. 12L14

AFLAG 58

08
05

og~

741.S244

PS.o 55

~~CK

A
()

(J)

ri'

a
~Cl
~

a
c
0

::J

1.-----------------'
0

:::l

ri'

::J

(J)

iD'

.-+

.....

-+>
-+>

eli'

.....

e::

;

~
(f)

v.>

n
::r

.I>

3
2l.

....
I

!L
Q

14Q
-:}:

51C258 OR 4125S

Voo

n'
0

iii'

'!lIl>

U10

U11

U12

kT..L EACH

Vss 18

0.11£

DRAM

INPUT
PORT

(J)
~

()

ex>

-....j

~ri'
~

()

~
(]l

:::l

......

;

Application Note

Signetics Microprocessor Products

256K Centronics Printer Buffer

SC87C451

Figure 2. Flowchart of Transmit Operation

February 1989

3-15

Signetics Microprocessor Products

Application Note

SC87C451

256K Centronics Printer Buffer

REPEATED
64 TIMES

Figure 2. (Cont) Flowchart of Receive and Refresh Operation

February 1989

3-16

Signetics Microprocessor Products

Application Note

256K Centronics Printer Buffer

SC87C451

j*******************************************************i

256K PRINTER BUFFER PROGRAM USING THE 8xC451
FOR CENTRONICS PARALLEL PRINTER PORTS
SIGNETICS CORPORATION
October, 1988
i*******************************************************i

$Mod451
$Title(8XC451 Printer Buffer)
$Date(lO/28/88)
PORT USAGE:
PO

Not used (reserved for data/address bus when external
program memory is used).
Lower S bits of DRAM address (AO - A7).
Not used (reserved for high-order address bus when external
program memory is used).

PI
P2
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7

(/INTO)
(/INT1)

(/WR)
(/RD)

(Reserved for serial port.)
(Reserved for serial port.)
Input port strobe input (interrupt).
Output port acknowledge input (interrupt).
Input port acknowledge output.
DRAM write enable output.
DRAM row address select output.
DRAM column address select output.

P4.0
P4.1
P4.2
P4.3
P4.4-P4.7

Upper bit of DRAM address (AS).
Reserved as an extra address line for I Megabit DRAMS.
Not used.
Output port busy input (OBUSY).
Unused (not available on 64-pin DIP package).

DRAM output data.

P6
BFLAG

Parallel output port.
Input port strobe input (ISTB).
Input port busy output (IBUSY).

AFLAG
/ODS

Output port strobe output (OSTB).
Port 6 output enable, tied low.

/IDS

Internal Register/RAM Usage:
REFCNT

EQU

020h

Low order refresh byte.

The following refer to the circular FIFO buffer
implemented in the DRAM array.
INLOW
INMID
INHI
OUT LOW
OUTMID
OUTHI

EQU
EQU
EQU
EQU
EQU
EQU

February 1989

22h
23h
24h
25h
26h
27h

Incoming
Incoming
Incoming
Outgoing
Outgoing
Outgoing

address
address
address
address
address
address
3-17

low byte.
mid byte.
high byte.
low byte.
mid byte.
high byte.

Application Note

Signetics Microprocessor Products

256K Centronics Printer Buffer
OACK
FOACK

EQU
BIT

28h
OACK.O

SC87C451

Holds flag for output port acknowledge.
Bit-address of output port acknowledge flag.

; Miscellaneous Equates:
TIME
TIMEHI
TIMELO
RAS

CAS
DRAMWR

IACK
ISTB
OBUSY
OSTB

EQU
EQU
EQU
BIT
BIT
BIT
BIT
BIT
BIT
BIT

-1000
HIGH TIME
LOW TIME
P3.6
P3.7
P3.5
P3.4
P3.2
P4.3
MAO

Value for 1000 timer clocks
1 millisecond.
High byte of timer value.
Low byte of timer value.
DRAM column address select.
DRAM row address select.
DRAM write control line.
Input port ACK output.
Input port strobe line (INTO).
Output port BUSY input.
Output port strobe (MAO bit in port 6 CSR).

i***************************************************** ***********************

Reset and Interrupt Jump Table
ORG
AJMP

OOh
START

ORG
AJMP

03h
INDATA

INT O.
Data at input port.

ORG
AJMP

OBh
REFRESH

Timer O.
Refresh DRAM array.

ORG
AJMP

13h
OPACK

INT 1.
Output port acknowledge.

;

Power-on reset.

i***************************************************** ***********************

Power up reset routine:
Set up refresh timer, enable timer interrupt and
external interrupt, initialize circular buffer pointers.
START:

ORG
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV

February 1989

18h
SP,#40h
A,#OO
REFCNT,A
INLOW, A
INMID,A
INHI,A
OUTLOW,A
OUTMID,A
OUTHI,A

Initialize stack pointer.
Initialize refresh counter.
Initialize FIFO pointers.

3-18

Signetics Microprocessor Products

Application Note

256K Centronics Printer Buffer

SC87C451

;Initialize interrupt priority register so that DRAM refresh
(TFO) gets high priority, input port service (lEO) and output
port acknowledge service get lower priority.
All other
interrupts set to lower priority level.
MOV
MOV
MOV
MOV
MOV
MOV

IE,#OOOOOlllb
IP,#OOOOOOlOb
TLO,#TlMELO
THO,#TlMEHI
TMOD,#OOOOOOOlb
TCON,#OOOlOlOlb

TimerO, INTO, and INTI enabled.
TimerO high priority.
Operate TimerO in mode 1.
TimerO run, 10 and II ~ edge.

Initialize Port 6 Control and Status Register.
- 'BFLAG' mode set to output value of IBF
(input port BUSY signal: IBUSY)
'AFLAG' set as logic 1 output
(output port strobe signal : OSTB)
'IDS' active on negative level
(input port strobe signal : ISTB)
MOV
MOV
SETB

CSR, #lOOlllOOb
A,P6
EA

Dummy read of P6 to clear IBF (IBUSY).
Enable interrupts.

i***************************************************** ***********************

Main Routine:
Executes while not performing DRAM refresh or servicing
input port interrupt.
Check if buffer is not empty by comparing input and output
pointers. If not empty, go to NOTMT to output a byte.
MAINLP:

MOV
CJNE
MOV
CJNE
MOV
CJNE
SJMP

A, INLOW
A,OUTLOW,NOTMT
A,INMID
A, OUTMID,NOTMT
A,INHI
A,OUTHI,NOTMT
MAINLP

Compare pointers.

Buffer is not empty: compute row & column addresses for
a read cycle from DRAM.
NOTMT:

MOV
MOV
MOV
RRC
MOV
MOV
RRC
MOV

R4,OUTLOW
RS,OUTMID
A,OUTHI
A
R7,A
A,OUTMID
A
R6,A

Save low byte of row.
Save upper bit of row.
Shift to align correctly.
Save upper column bit.
Get low byte of column.
Shift in bit from OUTHI.
Save.

Now do actual DRAM access to get the data byte at computed
address. Disable interrupts so we don't lose what we put
out on the ports.

February 1989

3-19

Signetics Microprocessor Products

Application Note

SC87C451

256K Centronics Printer Buffer
CLR
MOV
MOV

ORL
MOV
CLR
MOV
MOV
ORL
MOV
CLR
MOV

PLOOPI:

EA
Pl,R4
A,RS
A,#OFEh
P4,A

Disable interrupts.
Low byte row address.
Get high byte row address.
Make sure OBUSY stays high.

RAS

lRAS low.

PI,R6
A,R7
A,#OFEh
P4,A
CAS
R4,PS

Low byte column address.
High byte column address.
Make sure OBUSY stays high.

CAS

ICAS low.
Get the data byte

SETB
SETB
CLR
SETB

RAS

ICAS high.
lRAS high.

FOACK
EA

Clear acknowledge flag.
Re-enable interrupts.

OBUSY,PLOOPI

Loop if printer busy.

CLR
MOV
CLR
NOP
NOP
NOP
SETB
SETB

EA
P6,R4
MAO

Disable interrupts.
Move byte to output port.
Assert output port strobe.
Kill some time.

MAO

De-assert output port strobe.
Re-enable interrupts.

Following waits for lACK to occur on output port. Loops on
acknowledge flag which is set by INTI service routine when
lACK occurs.
PLOOP2: JNB
INC
MOV
CJNE
INC
MOV
CJNE
MOV
INC
ANL
MOV

FOACK,PLOOP2

Wait till lACK occurs.

OUTLOW
A,OUTLOW
A,#OO,PDONE
OUTMID
A,OUTMID
A,#OO,PDONE
A,OUTHI
A
A,#03h
OUTHI,A

Increment output buffer pointer.

Eliminate unused address bits
and save.

Check if input port busy flag was left asserted, indicating that
the buffer was full after last input. If so, acknowledge input
port and de-assert input busy signal.
PDONE:

JNB
CLR
CLR
NOP
NOP
NOP
NOP
NOP

February 1989

IBF,MAINLP
EA

lACK

Not busy, return to main loop.
Disable interrupts.
Assert IlACK.
Wait 7 microseconds.

3-20

Signetics Microprocessor Products

Application Note

256K Centronics Printer Buffer
NOP
NOP
MOV
NOP
NOP
NOP
NOP
NOP
SETB
SETB
AJMP

SC87C451

A,P6

Dummy read of P6 clears IBF (IBUSY).
Wait 5 microseconds.

lACK
EA
MAINLP

De-assert IIACK.
Re-enable interrupts.
Return to main loop.

;****************************************************************************

Interrupt 1 Service Routine:
- Called when output port asserts lACK.
- Sets FOACK flag and returns.
OPACK:

SETB
RETI

FOACK

i***************************************************** ***********************

DRAM Refresh (TimerO) Interrupt Service:
- Called once every millisecond by timer interrupt.
- Refreshes 64 rows and then returns.
- Therefore refreshes all rows every 4 milliseconds.
(Note that 41256/5lC256 DRAM only requires a 256 row refresh.)
REFRESH: PUSH
MOV
MOV
MOV
MOVX
INC
MOVX
INC
MOVX
INC
MOVX
INC
MOVX
INC
MOVX
INC
MOVX
INC
MOVX
INC
MOVX
INC
MOVX
INC
MOVX
INC
MOVX
INC

February 1989

PSW
THO,#TlMEHI
TLO,#TlMELO
PI,REFCNT
@RO,A
PI
@RO,A
Pl
@RO,A
Pl
@RO,A
Pl
@RO,A
Pl
@RO,A
PI
@RO,A
PI
@RO,A
Pl
@RO,A
Pl
@RO,A
Pl
@RO,A
Pl
@RO,A
PI

Reload timer registers.

Get next row to refresh.
Pulse lRAS (/WR).
I
2
3
4

5
6
7
8
9

10
11

3-21

Application Note

Signetics Microprocessor Products

SC87C451

256K Centronics Printer Buffer
MOVX
INC
MOVX
INC
MOVX
INC
MOVX
INC
MOVX
INC
MOVX
INC
MOVX
INC
MOVX
INC
MOVX
INC
MOVX
INC
MOVX
INC
MOVX
INC
MOVX
INC
MOVX
INC
MOVX
INC
MOVX
INC
MOVX
INC
MOVX
INC
MOVX
INC
MOVX
INC
MOVX
INC
MOVX
INC
MOVX
INC
MOVX
INC
MOVX
INC
MOVX
INC
MOVX
INC
MOVX
INC
MOVX
INC
MOVX
INC

February 1989

@Ro,A

PI
@RO,A

PI
3-22

Application Note

Signetics Microprocessor Products

@Ro,A
Pl
@RO,A
Pl
@RO,A
Pl
@RO,A
Pl
@RO,A
Pl
@RO,A
Pl
@RO,A
Pl
@RO,A
Pl
@RO,A
Pl
@RO,A
Pl
@RO,A
Pl
@RO,A
Pl
@RO,A
Pl
@RO,A
Pl
@R0,A
Pl
@RO,A
Pl
@RO,A
PI
@R0,A
Pl
@RO,A
PI
@RO,A
Pl
@RO,A
Pl
@RO,A

INC
MOV
POP
RETI

Pl
REFCNT,PI
PSW

SC87C451

42
43
44
45
46
47
48
49
50
5l
52
53
54
55
56
57
58
59
60
6l
62
63
Adjust for next time
and save.

i***************************************************** ***********************

Data at Input Port:
This routine is called via interrupt INTO whenever data
is strobed into the input port. It saves the data into the
DRAM array and increments the input pointer. If the output
pointer is now equal to the input pointer, then the buffer
is full, and we leave the busy flag set so that no more
data can be input until some is output and the buffer is
no longer full.

February 1989

3-23

Application Note

Signetics Microprocessor Products

SC87C451

256K Centronics Printer Buffer

INDATA: PUSH
PUSH
MOV
MOV
MOV
RRC
MOV
MOV
RRC
MOV

STBLP:

PSW
ACC
RI,INLOW
R2,INMID
A, INRI
A
RO,A
A,INMID
A
R3,A

Lower 8 bits of row to RI.
Upper bit of row to R2.
Get upper 2 bits.
LSB to carry.
Shift bit into MSB.
Save.

CLR
MOV
MOV
ORL
MOV
JNB
CLR
CLR
MOV
MOV
ORL
MOV
MOVX
SETB
SETB
SETB

EA
PI,RI
A,R2
A,#OFEh
P4,A
ISTB,STBLP
RAS
DRAMWR
PI,R3
A,RO
A,#OFEh
P4,A
A,@RO
RAS
DRAMWR
EA

Disable interrupts.
LSB row address.
MSB row address.
Make sure OBUSY stays high.
MSB row address.
Check for end of strobe before DRAM write.
/RAS low.
/WR low.
LSB column address.
MSB column address.
Make sure OBUSY stays high.
MSB column address.
Pulse /CAS low.
/RAS high.
/WR high.
Re-enable interrupts.

INC
MOV
CJNE
INC
MOV
CJNE
MOV
INC
ANL
MOV

INLOW
A, INLOW
A,#OO,CKFULL
INMID
A, INMID
A,#OO,CKFULL
A,INHI
A
A,#03h
INHI,A

Increment input buffer pointer.

Eliminate unused address bits.

Compare input pointer to output pointer to see if the buffer is full.
CKFULL:

MOV
CJNE
MOV
CJNE
MOV
CJNE

A, INLOW
A,OUTLOW,INCLR
A,INMID
A,OUTMID,INCLR
A, INRI
A, OUTHI, INCLR

If we get here, the buffer is full, so skip the acknowledge pulse.
SJMP

INDONE

Send acknowledge pulse on /IACK line for 7 microseconds,
de-assert input BUSY signal halfway through.
INCLR:

CLR
CLR

February 1989

lACK

Disable interrupts.
Assert /IACK.

3-24

Application Note

Signetics Microprocessor Products

SC87C451

256K Centronics Printer Buffer

lNDONE:

NOP
NOP
NOP
NOP
NOP
NOP
NOP
MOV
NOP
POP
pOP
SETB
SETB
RETl

wait 7 microseconds.

A,P6
ACC
psw
lACK
EA

Dummy read of P6 clears lBF (IBUSY).
Wait 5 microseconds before clearing flACK.

De-assert flACK.
Re-enable interrupts.

END

February 1989

3-25

Signefics

AN418
Counter/Timer 2
of the 83C552
Application Note

Microprocessor Division
Introduction to the 83C552

16-Bit Counter Timer

The 83C552 is an 80C51 derivative with
several extended features: 8k RO M, 256
bytes RAM, 10-bit A/D converter, two
PWM channels, two serial I/O channels,
six 8-bit I/O ports, and four counter timers. The architecture of the 83C552 is
identical to that of the 80C51 making the
two devices fully code compatible. The
additional peripheral functions are added
to the 80C51 Special Function Register
space and the interrupt structure is modified accordingly. This information is detailed in other references on the 83C552.
The focus of this application note is on
one of the timers of the 83C552, Counter
TImer 2.

The description of Counter Timer 2 in the
following paragraphs is intended to be a
general overview. Details on architecture, address locations, interrupt
structure and timer operation are given
in the 83C552 Users Manual. This users
manual may be useful to complement the
material presented in this application
note. References to registers, bits, I/O
ports and on-chip hardware will relate
directly to 83C552 Users Manual nomenclature. This application note will focus
on the use of Counter Timer 2 as a powerful input capture and high speed output facilitator through some specific examples and not on the detailed coding.

This counter timer includes capture,
compare and high speed output capabilities which facilitate many control oriented tasks. The objective of this note is to
make users of the 83C552 aware of this
counter timer subsystem and assist the
use of this subsystem by a detailed explanation of its operation supported by
actual application examples.

The counter timer consists of a 16-bit
counter which is readable by software
through special function registers TM2L
and TM2H. The timer itself has two
overflow flags, one after the entire 16-bit
counter and one attached to the eighth
stage. This latter flag reflects an overflow from the first byte of the counter.
These two flags are present in register
TM21R and are labeled T2BO for the
overflow from the first byte and T20V for
the overflow from the entire 16-bits.
These flags may be used to generate an
interrupt.

Timer 2 of the 83C552
Timer 2 of the 83C552 is in fact a timing
controller and has an associated programmable array. The Timer 2 subsystem
consists of three parts:
1. the time base consists of a 16-bit
timer with a 3-bit prescalar. The
master clock for the subsystem can
be derived from the on-chip oscillator
(fose) or an external input, T2. It has
an external reset, RT2, by which a
signal applied to this input can reset
the timer if the external reset is
enabled.
2. a capture system consisting of four
capture registers and four capture
inputs which can be used for a wide
variety of time measurements on external signals.
3. a compare system consisting of three
compare registers and eight associated high-speed outputs which can
be activated upon a match between
the 16-blt timer and one of the compare registers.
For reference a complete block diagram
of the 83C552 Counter Timer 2 subsystem is shown in Figure 1.

February 1989

The counter timer is controlled directly
through the special function register
TM2CON, the timer 2 control register.
This register also contains certain status
flags.
The prescaler divides the input clock by
a progammable ratio. The prescaler divide value is progammable to divide by
1, 2, 4, or 8 as controlled by T2PO and
T2P1 in TM2CON.
The input clock to the prescalar is either
fosc / 12 or the external input, T2. The
clock input to the prescaler may also be
shut off. This clock input selection is
controlled by bits T2MSO and T2MS1 in
TM2CON.
If T2 is used as the input clock to the
timer 2 subsystem, the hardware logic
samples this input and looks for a low to
high transition. If the logic detects a logic 0 at the T2 input in state S2P1 of the
microcontroller and a logic 1 in state
S5P1, then this is recognized as a low to

3-26

high transition and the prescaler is incremented. The prescaler is incremented
in the second cycle after the cycle in
which the transition was detected. If the
transition is detected before S2P1 is finished, the prescalar is incremented in the
next cycle. This timing is shown in Figure 2. Note that this sampling rate is
twice that of the normal 80C51 timers,
TO and T1, therefore T2 has twice the
maximum external counting rate as compared to the standard timers.
Any programming of the clock source or
the prescalar divide ratio results in a
reset of the prescaler. This allows the
state of the timer subsystem to be in a
known state upon programming. The
main 16-bit timer can not be reset by
software but it is reset by activating the
reset pin or using the external reset,
RT2. The external reset, RT2 can be enabled or disabled by bit T2ER in
TM2CON. These resets reset the prescalar as well as the 16-bit counter.
Only one interrupt is available from the
16-bit counter timer. Two bits in
TM2CON control whether TM2L, TM2H,
or both flags will be used to generate the
interrupt. A selection for no interrupt is
also possible.

Capture System
The capture system is a powerful tool to
measure the width of pulses or repetition rates. There are four independent
inputs for the signals to be analyzed,
CTIO through CTI3. These inputs are alternate functions to Port 1. Each input is
connected to a dedicated capture register. A transition at any of these inputs
will cause the content of the 16-bit
counter timer to be loaded into the respective capture register. The capture
can occur upon various conditions of the
input signal as specified by certain bits in
the capture control register, CTCON.
Each input can be set to cause a capture on a low to high tranSition, a high to
low transition, or on both transitions. Upon a capture taking place, each input
causes an interrupt flag to be set in the
Timer 2 Interrupt Flag Register, TM21R.
If enabled an interrupt will be generated.

Signetics Microprocessor Products

Application Note

Counter Timer 2

S83C552

off

~I PRESCALER
T2
RT2

------
T-start
<----->1 . . . . Jnj.~9:H?n•.•

Cyl 2
Cyl 3
Cyl 4

Shaded areas indicate injectors are on.
Figure 5. Four Cylinder Injection Timing

February 1989

3-30

Application Note

Signetics Microprocessor Products

S83C552

Counter Timer 2
STE.1 is programmed to a 1 and STE. 0
is programmed to a O. Similarly, the next
interrupt for CM1 is treated in the same
way and the sequence of events rotates
around through all cylinders in turn. The
flag bits associated with this operation
keep track of the injector sequencing.
While this example shows the injection
stop time of one cylinder overlapping into the injector on time of the subsequent
cylinder, close examination of the operations described above reveal that the
start and stop events are independent
and can overlap or not as required. In
this way all injectors may be driven independently and have overlapping on
times.
Given that this is an example applicable
to general usage, it is possible that interrupt service routine could be relatively
long as it would be in an actual injector
application. Since the service routine
has other interrupts disabled, the length
may cause real time conflicts. To eliminate this potential problem, the interrupt
service routines are divided into two
parts. I n the first part, all other interrupts
are disabled and the essential register
loading is done to prepare for the next
interrupt. After this is completed, all interrupts are enabled and the ancillary
service routine functions are performed
prior to a return to the main routine.

Reference
I

As an example consider the interrupt
service routine for CMO. Upon entering
the routine, all interrupts are disabled.
the
following
actions
are
Then
performed:
- set bit in STE to start next injector
- clear bit in STE for injector just started
- load CMO with start time for next
injector
- clear CMIO interrupt flag in TM21R
Now that the essential set up is made for
the next interrupt, all interrupts are now
enabled. However the return to the main
program is not invoked until the following
ancillary processing is completed:
- calculate the next absolute start time
for the next injector (the next load
value for CMO)
-

increment the flag so that the next
entry to this interrupt service routine
will be able to identify the next injector to start.

The process performing these calculations can be interrupted to service real
time functions.

Application Example Timed Ignition
In electronic ignition systems, multiple
ignition coils may be used and each coil
is fired by electronic means rather than
with the old stile mechanical breakers.
In a four cylinder engine, there may be
two ingnition coils, one coil providing
spark for a pair of cylinders. Both plugs
fire at the same time. For one cylinder,
the spark occurs at the appropriate time
while for the other cylinder, the spark
occurs at the end of the exhaust stroke
and has no effect. With timing references to crankshaft top dead center provided by an external sensor, the ignition
timing for the engine may be generated
in the 83C552 and applied to the electronic drivers for the ignition coils.
To illustrate the toggle high speed outputs of the 83C552 Counter Timer 2
subsystem, the following example will
discuss the ignition timing in a four cylinder engine employing the two coil approach with one coil for a pair of cylinders. The coil timing is illustrated in Figure 6. A reference time is used which is
a given interval prior to top dead center
so that the times used in the illustration
can be always after the reference.
There are two times of interest for each
coil: the load time and the ignition point.

TDC
II

Coil 1
-----~.-

Coil 2

Figure 6. Four Cylinder, Two Coil Ignition Timing

February 1989

3-31

Signetics Microprocessor Products

Application Note

Counter Timer 2
Ignition advance is usually given in degrees crankshaft angle prior to top dead
center. As with injection, this angle is
assumed to be derived from other calculations and is a given value for this illustration. This angle must be converted into a time with respect to the reference
point. The load time (the time at which
the coil has to be switched on to reach
the current that will give sufficient energy for an adequate spark) must be
subtracted from the desired ignition
point. At the ignition time, the coil will be
switched off and the spark will be
generated.
The coil driver electronics are connected
to port bits P4.6 and P4.7. Ignition Coil
1 is connected to P4.6 and ignition Coil
2 is connected to P4.7. These outputs
are the toggle high speed outputs controlled by the 16-bit compare register,
CM2. The program simply needs to set
up the compare and control registers to
turn the coils on and off at the appropriate times. It is assumed in this example
that the ignition and load times are given
quantities and have been determined
previously.
Consider now the sequence of events in
two rotations of the engine crankshaft
and refer to Figure 6. Assume that the
engine is running, that all relevant parameters are available and that it has
been determined that the processor is
responding to the interrupt associated
with a compare to CM2. The top dead
center time and crankshaft rotation
speed have been already determined
through the top dead center capture,
CTOI. This is the same as in the injector
example. The interrupt for CTOI is enabled. From the top dead center time, the
times to turn on and turn off the coil
drivers are computed and made available
in data storage locations in the microcontroller. It is also convenient to have
flags to identify the step in the complete
ignition cycle. The flags are cleared in
the interrupt service routine for top dead
center of cylinder 1.

February 1989

S83C552
Upon entering the interrupt service routine, other interrupts are disabled. Examination of the flags reveals that the state
of the ignition sequence is that Coil 1
has been turned on to begin the current
build up (load time). The next event will
therefore be turning off Coil 2 to cause
ignition. The interrupt service routine
then performs the following actions: The
time to turn off Coil 2 is moved into
compare register 2, CM2. Bit 6 of RTE
is cleared; this disconnects the output of
CM2 from the toggle flip flop of P4.6
(Coil 1). Bit 7 of RTE is set; this connects the output of CM2 to the toggle
flip flop of P4.7 (Coil 2). The flags are
incremented to indicate that the next interrupt will be a result of Coil 2 turning
off and causing ignition. The other interrupts can be enabled and a return to the
main program can be executed. After
the other interrupts are enabled and before a return is made to the main program, it may be convenient to do any
necessary calculations to determine the
time value to be loaded into CM2 in the
next CM2 interrupt.
Since the flip flops are toggled, it is likely that upon power up of the microcontroller, the toggle flip flops will not be
in the desired state. To get the toggle
flip flops in the correct state in the ignition cycle, the flip flops must be toggled
if they are in the wrong state. To determine if this is necessary, the state of
the toggle flip flops can be read from the
STE register. The state of the P4.6 flip
flop is present in STE bit 6 and the state
of the P4.7 flip flop is present in STE bit
7. Comparing the actual state to the required state determines which if any or
both of the flip flops must be toggled. If
a toggle is necessary to put one or both
of the flip flops in the correct state, the
corresponding bits in RTE would be set
for those flip flops requiring the toggle
and CM2 would be loaded with a value
that is slightly larger than the present
contents of Timer 2. If desired for reliability purposes, the state of the flip flops
could be checked periodically against
the ignition cycle flags to determine if a
correction is necessary.

3-32

Conclusion
This application note has examined one
aspect of the 83C552 CMOS 80C51 derivative microcontroller. The Counter
Timer 2 Subsystem has been applied to
a complex timing task of gasoline engine
injector valve and ignition coil timing
control. While this is a specific application to the automotive interests, the result are applicable to a wide variety of
time measurement and control applications. The 83C552 would be ideal for
many electromechanical systems such as
copy machines, fax machines, industrial
process control equipment, automatic
transmission control, and anti-5kid and
anti-lock braking control.
These application areas are those which
can successfully employ the 83C552
Counter Timer 2, however the other features should not be overlooked. When
combined with the 10-bit A to 0 Converter, the Pulse Width Modulator, the
12C serial bus and peripheral device family, the 83C552 provides minimum component count solutions for cellular radio
systems, professional audio systems, and
medical instrumentation products such as
bed side patient monitors and analyzers
for home care and sports use.

Signetics

AN420
Using up to 5 External
Interrupts on 8051 Family
Microcontrollers
Application Note

Microprocessor Division
8051 family microcontrollers are equipped with up to two inputs which may be
used as general-purpose interrupts. A
typical device provides a total of 5 interrupt sources. Timer a and Timer 1 generate vectored interrupts, as does the Serial Port. Applications that require more
than two externally signaled vectored interrupts, and do not use one or more of
the counters or the serial port, can be
configured to use these facilities for additional external interrupt inputs.
This note describes a method to configure the timer/counters and the serial port
for use as interrupt inputs. Minimum response time is a goal for this configuration.
Another popular method to implement
extra interrupt inputs is to poll under
software control a port pin configured as
an input. This method is necessary when
the on-<:hip peripherals are in use. Applications where this approach is recommended are ones in which the processor
spends more than half of the time executing a "wait loop", or a short code
sequence which jumps or branches back
on itself without performing any functions. I n this case, the instructions that
will check the state of input used as an
interrupt source are inserted into this sequence. Consequently, this input is ignored when other routines are being executed. This input may have to be
latched externally, or the processor may
miss the signal while executing other
routines.

In TMOD:
GATE - a

In TCON:
TRi - 1

CIT - 1
M1
MO

In IE:
ETi - 1
EA - 1

SERIAL PORT CONFIGURATION

- 1
- a

Where "i" is the timer number being used
as the external interrupt. The TMOD value would be 66 hexadecimal if both timer are being used as external interrupt
sources, x6 hex for timer 0, and 6x hex
for timer 1. The interrupt priority may
also be set in the IP register.
A falling edge on the corresponding
TimerO or Timer1 input (TO or T1) will
cause the counter to overflow and generate a timer interrupt. The counter will
be automatically loaded with another F F
from the reload register, so the interrupt
can occur again as soon as the interrupt
service routine completes. Counter/Timer
operation is described in detail in elsewhere in this manual.

The serial port can be placed in mode 2,
which is a 9-bit UART with the baud rate
derived from the oscillator. The external
interrupt is signaled through this port on
the RXD receive data pin. Reception is
initiated by a detected 1-to.{) transition
at RxD. The signal must stay at a for at
least five-eighths of a bit period for this
level to be recognized. Refer to the description of baud rates to determine the
length of a bit period at the oscillator
frequency selected for the application.
The input signal should remain low for at
least one bit period and for not more
than 9 bit periods.
To prepare the serial port for use as an
external interrupt, the following bits must
be set up:
In SCON:
SMa - 1
SM1 - a
SM2 - a
REN - 1

80eS1

Port 0
X2
Port 1
RESET
Port 2

Dedicated interrupt inputs that vector
the processor to individual service routines (as the two general purpose interrupt inputs work) do not have the drawbacks of the method described above.

INTO (P3.2l

P3.l

INTl (P3.3l

P3.6

COUNTERfTlMER CONFIGURATION

(P3.4l

P3.7

Ext. Interrupt

(P3.Sl

Ext. Interrupt

RXD (P3.0l

Timers a and 1 are placed in Mode 2,
which configures the timer register as an
8-bit counter with automatic reload. The
counter and reload register are loaded
with FF hexadecimal which is stored in
TH 1 and TL 1 or THO and TLO.
To prepare one of the timers for this kind
of operation, a number of control bits
have to be set up. The following is a list
of these bits and their values:

February 1989

Figure 1. SOC51 Five Interrupt Configuration

3-33

Application Note

Signetics Microprocessor Products

8051 Family

Using up to 5 External Interrupts
The Serial Port I nterrupt is then used as
a general purpose interrupt. The contents of receive buffer should be ignored, and will subsequently be overwritten during the next interrupt.

Note that the response time for this input
will be slower than for the Counter/Timer
inputs. This is due to the fact that the RI
is generated after the eighth serial data
bit time after the falling edge on RxD.

; Demonstration program for five external interrupts.
$MOD5l
$TITLE (Five vectored External Interrupts)
Interrupt Jump Table
ORG
OH
AJMP
setup

;Reset

ORG
RETI

;External interrupt O.
;(not implemented in this demo)

ORG
AJMP

OBH
TimO

;Timer a interrupt.

ORG
RETI

l3H

;External interrupt 1.
;(not implemented in this demo)

ORG
AJMP

lBH
Timl

;Timer 1 interrupt.

ORG
AJMP

23H
Serial

;Serial port interrupt.

Begin setup code
Setup MOV
SP,#7FH

;Initialize the stack pointer.

Configure both timers
MOV
TMOD,#66H
MOV
A,#OFFH
TLO,A
MOV
MOV
THO,A
MOV
TLl,A
MOV
THl,A
SETB
ETa
SETB
ETI
SETB
TRO
SETB
TRI

; Enable
;Enable
; Enable
; Enable

Configure the serial port
SETB
ES
MOV
SCON,#90H
SETB
EA

;Enable serial port interrupt.
;Put the serial port in mode 2.
;Enable interrupt system.

Wait:

NOP
JMP

Serial:NOP
CLR
RETI

;Put both counters into mode 2.
;Load FF hex into both counters

Timer
Timer
Timer
Timer

a interrupt.
1 interrupt.

a to run.
1 to run.

;Wait for an interrupt.
Wait
RI

;Serial interrupt service routine.
;Clear receiver interrupt flag.

TimO:

NOP
RETI

;Timer a interrupt service routine.

Timl:

NOP
RETI

;Timer a interrupt service routine.

END

February 1989

3-34

Signefics

Section 4
Inter-Integrated (12C)
Circuit Bus

Microprocessor Products

INDEX
12C Bus Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-1
12C Peripheral Selection Guide ............................... 4-13

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Signetics

12C Bus
Specification

Linear Products

INTRODUCTION
For 8-bit applications, such as those requiring
single-chip microcomputers, certain design
criteria can be established:
• A complete system usually consists
of at least one microcomputer and
other peripheral devices, such as
memories and 1/0 expanders.
• The cost of connecting the various
devices within the system must be
kept to a minimum,
• Such a system usually performs a
control function and does not require
high-speed data transfer.
• Overall efficiency depends on the
devices chosen and the
interconnecting bus structure.
In order to produce a system to satisfy these
criteria, a serial bus structure is needed.
Although serial buses don't have the throughput capability of parallel buses, they do require less wiring and fewer connecting pins.
However, a bus is not merely an interconnecting wire, it embodies all the formats and
procedures for communication within the system.
Devices communicating with each other on a
serial bus must have some form of protocol
which avoids all possibilities of confusion,
data loss and blockage of information. Fast
devices must be able to communicate with
slow devices. The system must not be dependent on the devices connected to it, otherwise modifications or improvements would be
impossible. A procedure has also to be resolved to decide which device will be in
control of the bus and when. And if different
devices with different clock speeds are connected to the bus, the bus clock source must
be defined.

a receiver, while a memory can both receive
and transmit data. In addition to transmitters
and receivers, devices can also be considered as masters or slaves when performing
data transfers (see Table 1). A master is the
device which initiates a data transfer on the
bus and generates the clock signals to permit
that transfer. At that time, any device addressed is considered a slave.
The 12 C bus is a multi-master bus. This means
that more than one device capable of controlling the bus can be connected to it. As
masters are usually microcomputers, let's
consider the case of a data transfer between
two microcomputers connected to the 12C
bus (Figure 1). This highlights the masterslave and receiver-transmitter relationships to
be found on the 12 C bus. It should be noted
that these relationships are not permanent,
but only depend on the direction of data
transfer at that time. The transfer of data
would follow in this way:
1) Suppose microcomputer A wants to send
information to microcomputer B
- microcomputer
microcomputer
- microcomputer
sends data to
receiver)

A (master) addresses
B (slave)
A (master transmitter)
microcomputer B (slave

- microcomputer A terminates the
transfer.
2) If microcomputer A wants to receive information from microcomputer B

- microcomputer A (master) addresses
microcomputer B (slave)
- microcomputer A (master receiver)
receives data from microcomputer B
(slave transmitter)
- microcomputer A terminates the
transfer.
Even in this case, the master (microcomputer
A) generates the timing and terminates the
transfer.
The possibility of more than one microcomputer being connected to the 12 C bus means
that more than one master could try to initiate
a data transfer at the same time. To avoid the
chaos that might ensue from such an event,
an arbitration procedure has been developed.
This procedure relies on the wired-AND connection of all devices to the 12C bus.
If two or more masters try to put information
on to the bus, the first to produce a one when
the other produces a zero will lose the
arbitration. The clock signals during arbitration are a synchronized combination of the
clocks generated by the masters using the
wired-AND connection to the SCL line (for
more detailed information concerning arbitration see Arbitration and Clock Generation).
Generation of clock Signals on the 12C bus is
always the responsibility of master devices;
each master generates its own clock signals
when transferring data on the bus. Bus clock
signals from a master can only be altered
when they are stretched by a slow slave

All these criteria are involved in the specification of the 12C bus.

THE 12C BUS CONCEPT
Any manufacturing process (NMOS, CMOS,
12L) can be supported by the 12C bus. Two
wires (SDA - serial data, SCL - serial clock)
carry information between the devices connected to the bus. Each device is recognized
by a unique address - whether it is a microcomputer, LCD driver, memory or keyboard
interface - and can operate as either a transmitter or receiver, depending on the function
of the device. Obviously an LCD driver is only
December 1988

Figure 1. Typical 12C Bus Configuration

4-1

Signetics Linear Products

12C Bus Specification

Table 1. Definition of 12C Bus Terminology
TERM

device holding down the clock line or by
another master when arbitration takes place.

DESCRIPTION

Transmitter

The device which sends data to the bus

Receiver

The device which receives data from the bus

Master

The device which initiates a transfer, generates clock
signals and terminates a transfer

Slave

The device addressed by a master

Multi·master

More than one master can attempt to control the
bus at the same time without corrupting the message

Arbitration

Procedure to ensure that if more than one master
simultaneously tries to control the bus, only one is
allowed to do so and the message is not corrupted

Synchronization

Procedure to synchronize the clock signals of two or
more devices

GENERAL CHARACTERISTICS
Both SDA and SCL are bidirectional lines,
connected to a positive supply voltage via a
pull·up resistor (see Figure 2). When the bus
is free, both lines are High. The output stages
of devices connected to the bus must have
an open-drain or open·collector in order to
perform the wired-AND function. Data on the
12C bus can be transferred at a rate up to
1OOkbitls.The number of devices connected
to the bus is solely dependent on the limiting
bus capacitance of 400pF.

BIT TRANSFER
-.,....-1~--- +VDD

SOA

(SERIAL DATA LINE)
(SERIAL CLDCK LINE)

~L~---~~----i---+----~----;---

r------

j------

: SCLK2-.J

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lOUT

~LK1_l

lOUT
I

-I
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1________________ ...J

IL _______________ ...JI

DEVICE 1

DEVICE 2

I
:

~LK

DATA
IN

I
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SCLK
IN

DATA
IN

Due to the variety of different technology
devices (CMOS, NMOS, 12L) which can be
connected to the 12C bus, the levels of the
logical 0 (Low) and 1 (High) are not fixed and
depend on the appropriate levi'll of VDD (see'
Electrical Specifications). One clock pulse is
generated for each data bit transferred.

Data Validity
The data on the SDA line must be stable
during the High period of the clock. The High
or Low state of the data line can only change
when the clock signal on the SCL line is Low
(Figure 3).

Start and Stop Conditions
Within the procedure of the 12 C bus, unique
situations arise which are defined as start and
stop conditions (see Figure 4).

Figure 2. Connection of Devices to the 12C Bus

A High·to-Low transition of the SDA line while
SCL is High is one such unique case. This
situation indicates a start condition.
A Low·to·High transition of the SDA line while
SCL is High defines a stop condition.
Start and stop conditions are always generat·
ed by the master. The bus is considered to be
busy after the start condition. The bus is
considered to be free again a certain time
after the stop condition. This bus free situa·
tion will be described later in detail.
Figure 3. Bit Transfer on thel 2 C Bus

SDA

f\l
I

ill
I

-t:1'rt~
rr-t- ~L
L~J '--I
'--I L~J
START CONDITION

STOP CONDITION

TRANSFERRING DATA
Byte Format
Every byte put on the SDA line must be 8 bits
long. The number of bytes that can be
transmitted per transfer is unrestricted. Each
byte must be followed by an acknowledge bit.

Figure 4. Start and Stop Conditions

December 1988

SDA

Detection of start and stop conditions by
devices connected to the bus is easy if they
possess the necessary interfacing hardware.
However, microcomputers with no such inter·
face have to sample the SDA line at least
twice per clock period in order to sense the
transition.

4-2

Signetics Linear Products

12C Bus Specification

r--,

ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER

CLOCK UNE HELDLQWWHILE
INTERRUPTS ARE SERVICED

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~V~K'\..../
'i' rt-t
I I
-8

L_...l
SlOP

CONDITION

Figure 5. Data Transfer on the 12C Bus

DATA OUTPUT
BYTRANSMrlTER

II \j1_
I ........
/ ___J
I

>C~

"'_ _ _.....

" -_ __

sc~~~ I I
Is I
L..::J
srART

CONDlnoN

Figure 6. Acknowledge on the 12C Bus

Data is transferred with the most significant
bit (MSB) first (Figure 5). " a receiving device
cannot receive another complete byte of data
until it has performed some other function, for
example, to service an internal interrupt, it
can hold the clock line SCL Low to force the
transmitter into a wait state. Data transfer
then continues when the receiver is ready for
another byte of data and releases the clock
line SCL.
In some cases, it is permitted to use a
different format from the 12C bus format, such
as CBUS compatible devices. A message
which starts with such an address can be
terminated by the generation of a stop condition, even during the transmission of a byte.
In this case, no acknowledge is generated.

Acknowledge
Data transfer with acknowledge is obligatory.
The acknowledge-related clock pulse is generated by the master. The transmitting device
releases the SDA line (High) during the acknowledge clock pulse.

December 1988

The receiving device has to pull down the
SDA line during the acknowledge clock pulse
so that the SDA line is stable Low during the
high period of this clock pulse (Figure 6). Of
course, setup and hold times must also be
taken into account and these will be described in the Timing section.
Usually, a receiver which has been addressed
is obliged to generate an acknowledge after
each byte has been received (except when
the message starts with a CBUS address.
When a slave receiver does not acknowledge
on the slave address, for example, because it
is unable to receive while it is performing
some real-time function, the data line must be
left High by the slave. The master can then
generate a STOP condition to abort the
transfer.
If a slave receiver does acknowledge the
slave address, but some time later in the
transfer cannot receive any more data bytes,
the master must again abort the transfer. This
is indicated by the slave not generating the
acknowledge on the first byte following. The

4-3

slave leaves the data line High and the
master generates the STOP condition.
In the case of a master receiver involved in a
transfer, it must signal an end of data to the
slave transmitter by not generating an acknowledge on the last byte that was clocked
out of the slave. The slave transmitter must
release the data line to allow the master to
generate the STOP condition.

ARBITRATION AND CLOCK
GENERATION
Synchronization
All masters generate their own clock on the
SCL line to transfer messages on the 12C bus.
Data is only valid during the clock High period
on the SCL line; therefore, a defined clock is
needed if the bit-by-bit arbitration procedure
is to take place.
Clock synchronization is performed using the
wired-AND connection of devices to the SCL
LINE. This means that a High-to-Low transi-

Signetics Linear Products

,2C Bus Specification

1_
I

START COUNTING
WAIT -I-..!I!!HPERIOD

STATE

--""'\

ClK
1 ____-+_~

ClK
2 ____

_______ J _____________+~------,~---

+-__

-+~,~~

______________

_J'~~-----,--~-

SCl

Figure 7. Clock Synchronization During the Arbitration Procedure

TRANSMITTER 1 LOSES ARBrrRATlON
DATAl + SDA
DATA

DATA

2~.'--'~~

__~__'~____-+__~ ______~~__--f

SDA

SCl

A master which loses the arbitration can
generate clock pulses until the end of the
byte in which it loses the arbitration.
If a master does lose arbitration during the
addressing stage, it is possible that the winning master is trying to address it. Therefore,
the losing master must switch over immediately to its slave receiver mode.
Figure 6 shows the arbitration procedure for
two masters. Of course more may be involved, depending on how many masters are
connected to the bus. The moment there is a
difference between the internal data level of
the master generating DATA 1 and the actual
level on the SDA line, its data output is
switched off, which means that a High output
level is then connected to the bus. This will
not affect the data transfer initiated by the
winning master. As control of the 12 C bus is
decided solely on the address and data sent
by competing masters, there is no central
master, nor any order of priority on the bus.

Use of the Clock Synchronizing
Mechanism as a Handshake
Figure 8. Arbitration Procedure of Two Masters

tion on the SCL line will affect the devices
concerned, causing them to start counting off
their Low period. Once a device clock has
gone Low it will hold the SCL line in that state
until the clock High state is reached (Figure
7). However, the Low-to-High change in this
device clock may not change the state of the
SCL line if another device
clock is still within its Low period. Therefore,
SCL will be held Low by the device with the
longest Low period. Devices with shorter Low
periods enter a High wait state during this
time.
When all devices concerned have counted off
their Low period, the clock line will be ie:
leased and go High. There will' then be no
difference between the device clocks and the

December 1966

Arbitration can carry on through many bits.
The first stage of arbitration is the comparison
of the address bits. If the masters are each
trying to address the same device, arbitration
continues into a comparison of the data.
Because address and data information is
used on the 12C bus for the arbitration, no
information is lost during this process.

state of the SCL line and all of them will start
counting their High periods. The first device
to complete its High period will again pull the
SCL line Low.
In this way, a synchronized SCL clock is
generated for which the Low period is determined by the device with the longest clock
Low period while the High period on SCL is
determined by the device with the shortest
clock High period.

Arbitration
Arbitration takes place on the SDA line in
such a way that the master which transmits a
High level, while another master transmits a
Low level, will switch off its DATA output
stage since the level on the bus does not
correspond to its own level.

4-4

In addition to being used during the arbitration
procedure, the clock synchronization mechanism can be used to enable receiving devices
to cope with fast data transfers, either on a
byte or bit level.
On the byte level, a device may be able to
receive bytes of data at a fast rate, but needs
more time to store a received byte or prepare
another byte to be transmitted. Slave devices
can then hold the SCL line Low, after reception and acknowledge of a byte, to force the
master into a wait state until the slave is
ready for the next byte transfer in a type of
handshake procedure.
On the bit level, a device such as a microcomputer without a hardware 12C interface
on-chip can slow down the bus clock by
extending each clock Low period. In this way,
the speed of any master is adapted to the
internal operating rate of this device.

Signetlcs Linear Products

12C Bus Specification

FORMATS
Data transfers follow the format shown in
Figure 9. After the start condition, a slave
address is sent. This address is 7 bits long;
the eighth bit is a data direction bit (R/W). A
zero indicates a transmission (WRITE); a one
indicates a request for data (READ). A data
transfer is always terminated by a stop condition generated by the master. However, if a

master still wishes to communicate on the
bus, it can generate another start condition,
and address another slave without first generating a stop condition. Various combinations
of read/write formats are then possible within
such a transfer.
At the moment of the first acknowledge, the
master transmitter becomes a master receiv-

er and the slave receiver becomes a slave
transmitter. This acknowledge is still generated by the slave.
The stop condition is generated by the master.
During a change of direction within a transfer,
the start condition and the slave address are
both repeated, but with the R/W bit reversed.

SDAl'\L.r~~OOCAV!
I I
I I

SCLW~~-vvvtt
L
L
j

L - - - J L-.-J L---.J

START
ADDRESS
CONDITION

R/W

ACK

L---.J

DATA

ACK

DATA

L-.-J
ACK

--l

SlOP
CONDITION

Figure 9. A Complete Data Transfer

Possible Data Transfer Formats are:
a) Master transmitter transmits to slave
receiver. Direction is not changed.

SLAVE ADDRESS

RtW

'O'(WRITE)

S ~ START

DATA

DATA TRANSFERRED
(n BYTES + ACKNOWLEDGE)

P~sTOP

b) Master reads slave immediately after
first byte.

DATA

A ~ ACKNOWLEDGE

SLAVE ADDRESS

R/W

DATA

II
~'(READ)

c) Combined formats.

DATA TRANSFERRED
(n BYTES + ACKNOWLEDGE)

I s I SLAVEADDRESS I R/W I A I DATA I A I s I SLAVE ADDRESS I RtW I A I DATA I A I P I

READ OR
WRITE

Lr~

J lL.r~

(n BYTES

+ ACKNOWLEDGE)

READ OR
WRITE

DIRECTION OF
TRANSFER MAY
CHANGE AT
THIS POINT

NOTES:
1. Combined formats can be used, for example, to control a serial memory. During the first data byte, the internal memory location has to be written. After the start condition is repeated,

data can then be transferred.
2. All decisions on auto-increment or decrement of previously accessed memory locations, etc., are taken by the deSigner of the device.
3. Each byte is followed by an acknowledge as indicated by the A blocks in the sequence.
4. 12C devices have to reset their bus logiC on receipt of a start condition so that they all antiCipate the sending of a slave address.

December 1988

4-5

Signetics Linear Products

12 C Bus Specification

ADDRESSING
The first byte after the start condition determines which slave will be selected by the
master. Usually, this first byte follows that
start procedure. The exception is the general
call address which can address all devices.
When this address is used, all devices
should, in theory, respond with an acknowledge, although devices can be made to
ignore this address. The second byte of the
general call address then defines the action
to be taken.

Definition of Bits in the First
Byte
The first seven bits of this byte make up the
slave address (Figure 10). The eighth bit
(LSB - least significant bit) determines the
direction of the message. A zero on the least
significant position of the first byte means that
the master will write information to a selected
slave; a one in this position means that the
master will read information from the slave.
LSB
-SLAYEADDRESS-

LSB

o
RRSTBYTE

Figure 12. Sequence of a Programming Master
bilities in group 1111 will also only be used for
extension purposes but are not yet allocated.
The combination OOOOXXX has been defined
as a special group. The following addresses
have been allocated:
FIRST BYTE
Slave
Address

0000
0000

001
010

X
X

0000
0000
0000
0000
0000

all

X
X
X
X
X

100
101
110
111

edge this address and behave as a slave
receiver. The second and following bytes will
be acknowledged by every slave receiver
capable of handling this data. A slave which
cannot process one of these bytes must
ignore it by not acknowledging.
The meaning of the general call address is
always specified in the second byte (Figure
11).

R/W

When an address is sent, each device in a
system compares the first 7 bits after the start
condition with its own address. If there is a
match, the device will consider itself addressed by the master as a slave receiver or
slave transmitter, depending on the R/W bit.

December 1988

SECOND BYTE

I H'OO' I AI H'02' I AI ABCDOOO I X I A I ABCDOQ1 I X I AI ABCD010 I X I A I p I

The address 1111111 is reserved as the
extension address. This means that the addressing procedure will be continued in the
next byte(s). Devices that do not use the
extended addressing do not react at the
reception of this byte. The seven other possi-

H'06'

000
000

The bit combination llllXXX of the slave
address is reserved for future extension purposes.

Figure 11. General Call Address Format

0000
0000

The 12C bus committee is available to coordinate allocation of 12C addresses.

(GENERAl. CALL ADDRESS)

Figure 10. The First Byte After the
Start Procedure

The slave address can be made up of a fixed
and a programmable part. Since it is expected
that identical ICs will be used more than once
in a system, the programmable part of the
slave address enables the maximum possible
number of such devices to be connected to
the 12 C bus. The number of programmable
address bits of a device depends on the
number of pins available. For example, if a
device has 4 fixed and 3 programmable
address bits, a total of eight identical devices
can be connected to the same bus.

OIAxxxxlx

General call address
Start byte

There are two cases to consider:
1. When the least significant bit B is a zero.
2. When the least significant bit B is a one.

CBUS apdress
Address reserved for
different bus format

When B is a zero, the second byte has the
following definition:

}o",

"'moO

No device is allowed to acknowledge at the
reception of the start byte.
The CBUS address has been reserved to
enable the intermixing of CBUS and 12C
devices in one system. 12C bus devices are
not allowed to respond at the reception of this
address.
The address reserved for a different bus
format is included to enable the mixing of 12 C
and other protocols. Only 12C devices that are
able to work with such formats and protocols
are allowed to respond to this address.
General Call Address
The general call address should be used to
address every device connected to the 12C
bus. However, if a device does not need any
of the data supplied within the general call
structure, it can ignore this address by not
acknowledging. " a device does require data
from a general call address, it will acknowl-

4-6

00000110 (H'06') Reset and write the programmable part of slave
address by software and
hardware. On receiving this
two-byte sequence, all devices (designed to respond
to the general call address)
will reset and take in the
programmable part of their
address.
Precautions must be taken
to ensure that a device is
not pulling down the SDA
or SCL line after applying
the supply voltage, since
these low levels would
block the bus.
00000010 (H'02') Write slave address by
software only. All devices
which obtain the programmable part of their address
by software (and which
have been designed to respond to the general call
address) will enter a mode
in which they can be programmed. The device will
not reset.

Signetics Linear Products

12C Bus Specification

An example of a data transfer of a programming master is shown in Figure t 2 (ABCD
represents the fixed part of the address).

(B)

00000100 (H'04') Write slave address by

hardware only. All devices
which define the programmable part of their address
by hardware (and which respond to the general call
address) will latch this programmable part at the reception of this two-byte sequence. The device will not
reset.

oooooooo

SLAVEADDRHIWMASTER

RIW

(n BYTES

+ ACKNOWLEDGE)

DUMPADDRFORHIWMASTER

IP I

a. Configuring master sends dump address to hardware master

DUMP ADDR FROM H IW MASTER

The remaining codes have not been fixed and
devices must ignore these codes.

RIW

WRITE

When B is a one, the two-byte sequence is a
hardware general call. This means that the
sequence is transmitted by a hardware master device, such as a keyboard scanner,
which cannot be programmed to transmit a
desired slave address. Since a hardware
master does not know in advance to which
device the message must be transferred, it
can only generate this hardware general call
and its own address, thereby identifying itself
to the system (Figure 13).

December 1988

WRITE

Sequences of programming procedure are
published in the appropriate device data
sheets.

Start Byte
Microcomputers can be connected to the 12 C
bus in two ways. If an on-chip hardware 12 C
bus interface is present, the microcomputer
can be programmed to be interrupted only by
requests from the bus. When the device
possesses no such interface, it must constantly monitor the bus via software. Obvious-

DATA

Figure 13. Data Transfer From Hardware Master Transmitter

be used as the second
byte.

In some systems an alternative could be that
the hardware master transmitter is brought in
the slave receiver mode after the system
reset. In this way, a system configuring master can tell the hardware master transmitter
(which is now in slave receiver mode) to
which address data must be sent (Figure 14).
After this programming procedure, the hardware master remains in the master transmitter mode.

SECOND
BYTE

GENERAL
CALL ADDRESS

00000000 (H'OO') This code is not allowed to

The seven bits remaining in the second byte
contain the device address of the hardware
master. This address is recognized by an
intelligent device, such as a microcomputer,
connected to the bus which will then direct
the information coming from the hardware
master. If the hardware master can also act
as a slave, the slave address is identical to
the master address.

MASTER ADDRESS

(n BYTES

+ ACKNOWLEDGE)

b. Hardware master dumps data to selected slave device
Figure 14. Data Transfer of Hardware Master Transmitter Capable of Dumping
Data Directly to Slave Devices

II
SDA?

~UMMY
I
(
ACKNOWLEDGE
I
I

I \.. I
I

SCL

(HIGH)

--r---f\
f0.
r;\ J;\ r,;\ HI _I \..Jr,\
. \..J - "-t~ , \..J - \..J ACK\..J I _ i
L~

!----START BYTE

00000001----1

Figure 15. Start Byte Procedure
Iy, the more times the microcomputer monitors, or polls, the bus, the less time it can
spend carrying out its intended function.
Therefore, there is a difference in speed
between fast hardware devices and the relatively slow microcomputer which relies on
software polling.
In this case, data transfer can be preceded by
a start procedure which is much longer than
normal (Figure 15). The start procedure consists of:
a)
b)
c)
d)

A start condition, (S)
A start byte 00000001
An acknowledge clock pulse
A repeated start condition, (Sr)

After the start condition (S) has been transmitted by a master requiring bus access, the

4-7

start byte (00000001) is transmitted. Another
microcomputer can therefore sample the
SDA line on a low sampling rate until one of
the seven zeros in the start byte is detected.
After detection of this Low level on the SDA
line, the microcomputer is then able to switch
to a higher sampling rate in order to find the
second start condition (Sr) which is then used
for synchronization.
A hardware receiver will reset at the reception
of the second start condition (Sr) and will
therefore ignore the start byte.
After the start byte, an acknowledge-related
clock pulse is generated. This is present only
to conform with the byte handling format used
on the bus. No device is allowed to acknowledge the start byte.

Signetics Linear Products

12C Bus Specification

r-,
I

"I___________J

SDA

SCL

DLEN

~----------------~
'---_ _ _ _ _ _ _ _-'IL.JL.J

CO~~I~ON

Ag~~:ss

L -_ _ _ _ _ _ _ _ _ _ _ _--'I

~ I

L-J

n DATA BITS

ACK
RELATED
CLOCK PULSE

Figure 16. Data Format of Transmissions With CBUS Receiver/Transmitter
CBUS Compatibility
Existing CBLiS receivers can be connected to
the 12 C bus. In this case, a third line called
DLEN has to be connected and the acknowledge bit omitted. Normally, 12 C transmissions
are multiples of 8-bit bytes; however, CBLiS
devices have different formats.

V 0D1 _4 =5V:t:10%

In a mixed bus structure, 12C devices are not
allowed to respond on the CBLiS message.
For this reason, a special CBLiS address
(0000001 X) has been reserved. No 12 C device will respond to this address. After the
transmission of the CBLiS address, the DLEN
line can be made active and transmission,
according to the CBLiS format, can be performed (Figure 16).

SM--~-t--~~~--~-+----~~----~+
SCL----~~----~------4_------4_------+_

Figure 17. Fixed Input Level Devices Connected to the 12C Bus

VoD =e.g.3V

After the stop condition, all devices are again
ready to accept data.
Master transmitters are allowed to generate
CBLiS formats after having sent the CBLiS
address. Such a transmission is terminated
by a stop condition, recognized by all devices.
In the low speed mode, full 8-bit bytes must
always be transmitted and the timing of the
DLEN signal adapted.
If the CBLiS configuration is known and no
expansion with CBLiS devices is foreseen,
the user is allowed to adapt the hold time to
the specific requirements of device(s) used.

ELECTRICAL SPECIFICATIONS
OF INPUTS AND OUTPUTS OF
12C DEVICES
The 12 C bus allows communication between
devices made in different technologies which
might also use different supply voltages.
For devices with fixed input levels, operating
on a supply voltage of + 5V ± 10%, the following levels have been defined:
Vilmax

1.5V (maximum input Low
voltage)

December 1988

SM--~~~--~~----~+-----~+-----~+
SCL----~~----~------~------~------~

Figure 18. Devices With a Wide Ra9ge of Supply Voltages Connected
to the I C Bus
VIHmin

3V (minimum input High
voltage)

Devices operating on a fixed supply voltage
different from + 5V (e.g. 12L), must also have
these input levels of 1.5V and 3V for Vil and
VIH, respectively.
For devices operating over a wide range of
supply voltages (e.g. CMOS), the following
levels have been defined:
Vilmax

VIHmin

0.3VDD (maximum input Low
voltage)
0.7VDD (minimum input High
voltage)

For both groups of devices, the maximum
output Low value has been defined:
VOl max

O.4V (max. output voltage Low)
at 3mA sink current

4-8

The maximum low-level input current at
VOl max of both the SDA pin and the SCL pin
of an 12 C device is -10pA, including the
leakage current of a possible output stage.
The maximum high-level input current at
0.9VDD of both the SDA pin and SCL pin of an
12 C device is 10pA, including the leakage
current of a possible output stage.
The maximum capacitance of both the SDA
pin and the SCL pin of an 12 C device is 10pF.
Devices with fixed input levels can each have
their own power supply of +5V ± 10%. Pullup resistors can be connected to any supply
(see Figure 17).
However, the devices with input levels related
to VDD must have one common supply line to
which the pull-up resistor is also connected
(see Figure 18).

Signetics Linear Products

12C Bus Specification

When devices with fixed input levels are
mixed with devices with VDD-related levels,
the latter devices have to be connected to
one common supply line of + 5V ± 10% along
with the pull-up resistors (Figure 19).

V DD1 =5V±100f0

V0D2 =5V±10%

V OD3 =5V±1O%

Input levels are defined in such a way that:
1. The noise margin on the Low level is 0.1
VDD·
2. The noise margin on the High level is 0.2
VDD·
3. Series resistors (Rs) up to 300n can be
used for flash-over protection against high
voltage spikes on the SDA and SCL line
(due to flash-over of a TV picture tube, for
example) (Figure 20).

SOA--~-1----+-;-----+-;-----~+---~~rSCL.-----4------~-----4

Figure 19. Devices With Voo Related LeveJs Mixed With Fixed Input Level
Devices on the I C Bus

TIMING

SOA

The clock on the 12C bus has a minimum Low
period of 4.711S and a minimum High period of
411S. Masters in this mode can generate a bus
clock with a frequency from 0 to 100kHz.

SCL

Figure 21 shows the timing requirements in
detail. A description of the abbreviations used
is shown in Table 2. All timing references are

voo

The maximum bus capacitance per wire is
400pF. This includes the capacitance of the
wire itself and the capacitance of the pins
connected to it.

All devices connected to the bus must be
able to follow transfers with frequencies up to
100kHz, either by being able to transmit or
receive at that speed or by applying the clock
synchronization procedure which will force
the master into a wait state and stretch the
Low periods. In the latter case the frequency
is reduced.

______~------~

I'C
OEVICE

JI
Rs

O:'CE

LD05650S

Figure 20. Serial Resistors (Rs) for Protection Against High Voltage

LOW-SPEED MODE

Data Format and Timing

As explained previously, there is a difference
in speed on the 12 C bus between fast hardware devices and the relatively slow microcomputer which relies on software polling.
For this reason a low speed mode is available
on the 12C bus to allow these microcomputers
to poll the bus less often.

The bus clock in this mode has a Low period
of 130l1s ± 2511S and a High period of
390l1s ± 2511S, resulting in a clock frequency
of approx. 2kHz. The duty cycle of the clock
has this Low-to-High ratio to allow for more
efficient use of microcomputers without an
on-chip hardware 12C bus interface. In this
mode also, data transfer with acknowledge is
obligatory. The maximum number of bytes
transferred is not limited (Figure 22).

Start and Stop Conditions
In the low-speed mode, data transfer is preceded by the start procedure.

at V1Lmax and VILmln.

SDA

SCL

Figure 21. Timing Requirements for the 12 C Bus

December 1988

4-9

Signetics Linear Products

12C Bus Specification

Table 2. Timing Requirement for the 12 C Bus
LIMITS
SYMBOL

PARAMETER

UNIT
Min

Max

100

fscL

SCL clock frequency

tsuF

Time the bus must be free before a new transmission can start

tHO; STA

Hold time start condition. After this period the first clock pulse is generated

tLOW

The Low period of the clock

4.7

I1s

tHIGH

The High period of the clock

I1s

tsu; STA

Setup time for start condition (Only relevant for a repeated start condition)

4.7

I1s

tHO; OAT

Hold
for
for

5
O·

I1s
I1S

time DATA
CBUS compatible masters
12 C devices

tsu; OAT

Setup time DATA

Rise time of both SDA and SCL lines

kHz

4.7

I1s

250

Fall time of both SDA and SCL lines

tsu; STO

Setup time for stop condition

I1s
ns

300
4.7

I1S

NOTES:
All values referenced to VIH and VIL levels.
* Note that a transmitter must internally provide, a hold time to bridge the undefined region (300ns max.) of the falling edge of SCL.

~...,

SDA

"1\:

I \jol----~(.(_J
I I

C~~
I

SCL~~~-~
I s I
I I
I I
Sr

1....---'

IL---..J

CO~~ON

START BYTE

L.....J

IL---JI

ACK~~~~~DGE R~e::rED
(HIGH)

ADDRESS

ACK

CONDITIDN

Figure 22. Data Transfer Low-Speed Mode

SDA

SCL

l----tHIGH----~1

Figure 23. Timing Low-Speed Mode

December 1988

4-10

IL---J

DATA n BYTES

ACK

L-......J

CO~:'DN

Signetics Linear Products

12C Bus Specification

LOW SPEED MODE
CLOCK
DUTY CYCLE

START BYTE
MAX. NO. OF BYTES
PREMATURE TERMINATION OF TRANSFER
ACKNOWLEDGE CLOCK BIT
ACKNOWLEDGEMENT OF SLAVES

tLOW - t 30l'S ± 251's
tHIGH - 390l's ± 251's
1:3 Low-to-High (Duty cycle of
clock generator)
0000 0001
UNRESTRICTED
NOT ALLOWED
ALWAYS PROVIDED
OBLIGATORY

In this mode, a transfer cannot be terminated
during the transmission of a byte.
The bus is considered busy after the first start
condition. It is considered free again one
minimum clock Low period, 1051's, after the
detection of the stop condition. Figure 23
shows the timing requirements in detail, Table
3 explains the abbreviations.

Table 3. Timing Low Speed Mode
LIMITS
SYMBOL

PARAMETER

UNIT
Min

Max

tBUF

Time the bus must be free before a new transmission can start

105

I's

tHO; STA

Hold time start condition. After this period the first clock pulse is generated

365

p.s

tHO; STA

Hold time (repeated start condition only)

210

tLOW

The Low period of the clock

105

155

I'S

p.s

tHIGH

The High period of the clock

365

415

I'S

tsu; STA

Setup time for start condition (Only relevant for a repeated start condition)

105

155

p.s

tHO; tOAT

Hold time DATA
for CBUS compatible masters
for 12 C devices

5
O'

tsu; OAT

Setup time DATA

250

Rise time of both SDA and SCL lines

Fall time of both SDA and SCL lines

tsu; STO

Setup time for stop condition

I'S
p.s
ns
1

105

300

155

p.s

NOTES:
All values referenced to V 1H and V 1L levels .

• Note that a transmitter must internally provide a hold time to bridge the undefined region (300ns max.) of the falling edge of

December 1988

4-11

I'S

seL.

Signetics Linear Products

12C Bus Specification

APPENDIX A
Maximum and minimum values of the pull-up
resistors Rp and series resistors Rs (See
Figure 20).
In a 12C bus system these values depend on
the following parameters:
- Supply voltage
- Bus capacitance
- Number of devices (input current + leakage current)
1) The supply voltage limits the minimum value of the Rp resistor due
to the specified 3mA as minimum
sink current of the output stages,
at O.4V as maximum low voltage.
In Graph 1, VDD against Rpmin is
shown.

In Graph 2, RSmax against Rp is shown.
2) The bus capacitance is the total capacitance of wire, connections, and
pins. This capacitance limits the maximum value of Rp because of the
specified rise time of 1MS.

In Graph 3, the bus capacitance - RPmax
relationship is shown.
3) The maximum high-level input current
of each input! output connection has a
specified value of 10j.iA max. Due to
the desired noise margin of 0.2 VDD
for the high level, this input current
limits the maximum value of Rp. This
limit is dependent on VDD.
In Graph 4 the total high-level input current - RPmax relationship is shown.
20

<;.
0:
w

__-L____L-__- L__
400

800

1200

1600

MAXIMUM VAWE Rs (2)

::Ii
:::>
:I!

:I!

Graph 2

oL-__ __-L__
o
40
80
~

lii"
O~

__-L____L-__-L__

.t
w
3

Graph 1
The desired noise margin of 0.1 VDD for the
low level limits the maximum value of Rs.

MAX.R~~

@VOO=j
o
o

100

200

.......:::::
300

BUS CAPACITANCE (PF)

Graph 3

December 1988

200

12C LICENSE

/Rs=O

::Ii
:::>
::Ii

L-~

180

Graph 4

os.

____

120

TOTAL HIGH LEVEL INPUT CURRENT (jA)

4-12

-=
400

Purchase of Signetics or Philips 12C components conveys a license under the Philips 12C
patent rights to use these components in an
12C system, provided that the system conforms to the 12 C standard specification as
defined by Philips.

Signetics

12C PERIPHERAL
SELECTION GUIDE

General Purpose ICs

Application-Oriented ICs

68000-Based CMOS IlProcessor

LCD Drivers

Video/Radio/Audio

SCC68070:

PCF8566:

PCF8200:

PCF8576:
PCF8517/A:
PCF8578i79:

96-segment LCD driver
1:1 -1:4 Mux
160-segment LCD driver
1:1 -1:4Mux
64-segment LCD driver
1:1 -1:2Mux
Row/column LCD dotmatrix driver; 1 :S - 1 :32 Mux

SAA3028:
SAB3035/36/37:
TDA8440:
TDA8443/A:
TEA6000/61 00:

I/O Expandors
PCF85741A:
.".

-'>

PCF8584:

c.u

SAA1064:
SAA1300:

S-bit remote I/O port WC
bus to parallel converter)
S-bit parallel to 12 C
converter·
4-digit LED driver
5-bit high-current driver

TEA6300:

TEA6310T:

TSA5510:

Data Converters
PCF8591:
TDA8442:
TDA8444:

4-channel, S-bit Mux
ADC + one DAC
Quad 6-bit DAC
Octal 6-bit DAC

Memory
PCF8570/C:
PCF8571:
PCF8581:
PCF8582A:
PCF8583:

256-byte static RAM
12S-byte static RAM
12S-byte EEPROM·
256-byte EEPROM
256-byte RAM/clockl
calendar

Clock/Calendars
PCF8573:
PCF8583:

TSA6057:

Telecom
NE5750/51:
PCD3311/12:
PCD3341:

PCD3343:
PCD3348:
UMA1000T:

Clocklcalendar
Clocklcalendar/256-byte
RAM

Voice synthesizer (malel
female speech)
Transcoder (RC-5) for IR
remote control
Digital tuning circuits for
computer-controlled TV
Video/audio switch
YUV/RGB matrix switch
FMlIF and digital tuning IC
for computer-controlled
radio
Sound fader control and
preamplifier/source
selector for car radio
Sound fader control with
tone and volume control for
car radio
PLL frequency synthesizer
for radio
PLL frequency synthesizer
for radio

UMA1010T:

. 80C51-Based CMOS IlControllers·
S80C552:

ROM-less version of
S83C552
S80C652:
ROM-less version of
S83C652
S83C552:
256-byte RAMISk RaMI
ADC/UART
S83C652:
256-byte RAMISkI ROM
S83C751 :
64-byte RAM/2k ROM
S87C552:
EPROM version of
SS3C552·
S87C652:
EPROM version of
S83C652*
S87C751:
EPROM version of
S83C751
+al50 available with extended lemperature ranges

8048 Instruction-Set Based CMOS
IlControllers
PCF84COO:

Audio processor pair'"
Tone generator (DTMF/
modem/musical)
Advanced 10 to 11 O-number
repertory dialer with LCD
control
Microcontroller with 224byte RAMl3k ROM
Microcontrolier with 256byte RAMISk ROM
Data processor for mobile
telephones·
1GHz frequency
synthesizer for mobile
telephones·

68000 CPU/MMU/UARTI
DMNtimer

PCF84C21:
PCF84C41 :
PCF84C81:
PCF84C85:
PCF84C430:

• Future Device

256-byte RAM/bond-out
version for prototype
development
64-byte RAM/2k ROM
128-byte RAMl4k ROM
256-byte RAMISk ROM
256-byte RAMISk ROM/
Extended 1/0
12S-byte RAMl4k RaMI
96-segment LCD driver·

Signetics

Section 5
Development Support
Tools

Microprocessor Products

INDEX
Development Support Tools .................................. 5-1
In-Circu~ Emulator for 8051 or 8052 Microcontroller ............... 5-2
In-Circuit Emulator for 80C451 Microcontroller. . . . . . . . . . . . . . . . . . .. 5-4
In-Circuit Emulator for 83C451 Microcontroller. . . . . . . . . . . . . . . . . . .. 5-6
In-Circu~ Emulator for 80C552 Microcontroller . . . . . . . . . . . . . . . . . . .. 5-8
In-Circuit Emulatorfor 80C652 Microcontroller ................... 5-10
In-Circuit Emulatorfor 83C751 Microcontroller. . . . . . . . . . . . . . . . . .. 5-12
ASM51 8051 Macro Cross Assembler ......................... 5-14
SPGM-100 EPROM Microcontroller and Standard EPROM
Programmer ............................................. 5-16

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DEVELOPMENT SUPPORT TOOLS
Signetics stocks development support tools to help simplify
your design activities. These include:
c In-circuit emulation development systems
c Cross-assemblers
Low-cost EPROM programming equipment

In addition, Signetics works closely with many 'third-party'
vendors who provide support tools for our wide variety of
80C51-based microcontroller derivatives.
DEVELOPMENT SYSTEMS
In most cases, our development systems are available in
two versions for ROM and ROMless applications. The
ROM emulation products are capable of supporting all
versions of a given device type including EPROM, ROM,
and ROMless devices. For example, the SMI-83C451 emulator can support designs based on either the 87C451,
83C451, or 8OC451. In contrast, a ROMless emulator can
only support applications designed for a ROMless microcontroller. For example, the SMI-80C451 emulator can
only support applications using the 8OC451.
These development systems are designed to connect to the
serial port of an IBM-PC or compatible personal computer. The development system package includes the emu-

lator hardware, host emulation software, cross-assembler,
user's manuals, cables, and power supply. Note that these
emulators do not include provisions for programming
('burning') the EPROM in EPROM-based microcontrollers.
CROSS-ASSEMBLER
The cross-assembler provided with the development system
package is also available separately. This assembler supports macros and conditional assembly operations and is
designed to run on an IBM-PC or compatible processor.
This assembler uses an external text file to define the
architecture of specific microcontrollers. Support for new
microcontroller types can be added by creating a simple
text file to define the new micro-controller, thereby allowing the assembler to support a variety of prodact derivatives now and in future applications.
EPROM PROGRAMMING SUPPORT
Signetics works closely with. major suppliers of EPROM
programming equipment to support our family of EPROM
micro-controllers. As a result, EPROM programming support is available within the programming facilities of many
major distributors and customers.
Your local Signetics sales office or representative can
provide a list of manufacturers of EPROM programming
equipment that offer programming support products for
Signetics EPROM microcontrollers.

SIGNETICS MICROCONTROLLER DEVELOPMENT SYSTEMS

The emulator package includes emulator hardware, power supplies, Interface cables, host software and cross-assembler.
This package requires the use of an IBM-PC or 100% compatibles with 640k RAM, PC DOS version 2.0 or later and an
RS232 port.
EPROM MICROCONTROLLER PROGRAMMING SYSTEM

Mltl~@J.i~§t#n tki&YMlt@rWWm%ltW#jjtMird;a;dm!~ltltml_m"~~$.tl@mN
Part No.
SAM 751SD
SAM 751ASD
SAM 51SD
SAM 51ASD
SAM-451SD
SAM 451ASD
SAM-752SD
SAM 752ASD

Adapter Sockets for SPGM-100SD
Microcontroller
87C751
87C751
87C51
87C51
87C451
87C451
87C752
87C752

DIP
24-Pin

5-1

LCC
28-Pin

40-Pin
44-Pin
64-Pin
68-Pin
28-Pin

SHIPMENTS THROUGH SIGNETICS DISTRIBUTORS ONLY

February 1989

H!@tr . .·. . . . . . . . I.)n'td

28-Pin

System Overview
Signetics-8052
In-Cirquit Emulator
for 8051 or 8052
Microcontroller

• Serially linked to IBM PC or 100%
compatible hosts

• Over 128,000 Break Triggers and 64,000
Trace Triggers

• Advanced menu driven human interface

• Emulation Memory:
Standard
16K
~ Program
~ External Data
16K

• Real time and transparent emulation up to
16 MHz
• Disassembler and Single Line Assembler

Optional
64K
64K

• Full Symbolic Debug Capability

• Examine/Modify Memory capabilities

• High Level Language Support

• 16 Break and Trace Trigger Conditions

• Up to 64K Pass Counts
• Separate Program and Data Memory Mapping
in 16 byte blocks

• Supports both modes:
Microcontroller
Microprocessor

• Experiment Editor/Compiler

• 9 Probe Clips
7 External Events
1 External Trigger Input
1 External Trigger Output

• Trace with 2K frames
• Opcode Class Editor

PHILIPS
98-8270-010

5-2

1029-OOO/688IIM

Functional Description

Support

The Signetics-8052 is an in-circuit emulator which is designed for use in
developing, testing and debugging designs based on 8051 or 8052 single
chip microcontrollers. The Signetics-8052 allows the development of
hardware and software designs to occur simultaneously.
The Signetics-8052 emulator assists in the following design phases:
• Software Development
• Manufacturing
• Integration of target software and system hardware
• Field Service

The Signetics-8052 emulator not only assists the designer in developing, testing
and debugging 8051 or 8052 microcontroller designs, but is also backed by
Signetics with an extensive service and support policy that includes:
• Updates to the Signetics User's Manual and Signetics host Operating System
software that are provided at no charge for a ninety (90) day period.
• Toll free phone number (l-800-A-HLP-4-51) to resolve system hardware
and/or software concerns.
• A 72-hour repair on disabled systems under warranty.

Features Description
Emulator Functions
• Microcontrollers supported:
S031 SOC31 S032
SOSI SOCSI S052
S7C51
• Perfonnance
Real-time 3.5 to 16 MHz
• Transparency:
Operational and electrical
• Examine and modify:
Program
Internal data
External data

User Interface
• Advanced menu driven operating system
• 11 functional capabilities:
OS-Escape
Load
Help
Upload
Configure
Download
Restore
Store
Interrogate
Exit
Macro

Mode
• Allows user to emulate all the operating modes
of;
Full operation with external address/data bus
Single-chip operation with NO external
address/data bus

Interrogation
• Allows the user to:
Run experiments
Examine the system status
Set break and trace triggers
Examine/modify data
• 16 functional capabilities:
Run
Single-step
Reset
OS-Escape
Set pass count
Set simple break and trace triggers
Set repetition counter
Set phantom break and trace triggers
Set trace triggers (start, end & center)
Tum trace trigger ON/OFF
View up to 2K of trace buffer
Examine/modify:
Special Function Registers
Internal data memory
External data memory
Program memory
Emulator experiments

Experiment

High Level Language

• Used to specify complex break and trace
triggers
• Uses the if-then construct
• Allowable trigger conditions are:
PC address
PC address range
Opcode value
apcode class
Special function registers
Direct byte address
Direct byte address range
Direct bit address
Direct bit address range
Immediate operand value
Read/write to bit or direct addresses
External data address
External data address range
Logical AND or OR of any of the above
Pass count overflow
External input
• Over; 12S,OOO break triggers
64,000 trace triggers
• Experiment Editor allows user to create or
modify experiments by:
Edit
Delete
Store
Compile
Load
Specify Opcode Class
• apcode class is collection of various 8051
instructions that make up a set.
Set is user defined
Opcode class editor allows user to create,
delete or edit ape ode classes

Examine/Modify Memory
• Program memory operations:
Disassemble
Single line assemble
Examine/modify raw data
Mapping
• Microcontroller internal and external data
memory operations:
Dump
Scan and modify
Fill
Move
Search
Compare
Mapping
Examine/modify addressable bits

Macro
• Repetitive routine
• User created, edited and
callable at any time

MetaLink is a Irademark of MetaLink. Corporation.
pc-OOS, PC. PC XT and PC AT are trademarks of IBM.
IBM is a registered trademark of IBM Corporation.
Intel is a registered trademark of Intel Corporation.
©METALINK CORPORATION 1988

•
•
•
•

'C' and PLM support
Variables and Line number break/trace triggers
Variables Accessible
Step - Proceed and Step - Trace of Line
numbers

SymbOlic Debug
• User and Pre-Defined Symbols
• Supports MetaLink., Enertec, lAR, Archimedes,
Signetics, Microtec Research or Intel aMF files
• Use a name not address to alter content of:
bits, bytes, code

Electrical Specification
Input Power (typical):
1.5 amps @ + 5 volts DC

+/ -

Mechanical Specification
Emulator dimensions:
1.0" x 7.0" x 5.5"
2.5cm x 17.Scm x 14.0cm
Target system cable length:
14.0"
35.6cm
Emulator and target system cable weight:
2.01bs.
0.9 kg
Emulator probe head:
Compatible with 600 mil wide 40 pin DIP on
100 mil centers

Host Specification
An IBM PC, PC XT, PC AT or 100%
compatible system with 640K bytes of RAM.
PC-DOS 2.0 or later.
Two (2) floppy disk drives.
One (I) RS232C interface card for the PC and
cable.

warranty
Ninety (90) days limited warranty, parts and
labor.

Signetics
a division 01 North American Philips Corporation
Signellcs Company
811 E. Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088-3409
Telephone 408/991-2000

System Overview
Signetics-80C451
In-Circuit Emulator for
80C451 Microcontroller

• Serially linked to IBM PC or 100%
compatible hosts

• Opcode Class Editor
• Over 128,000 Break and Trace Triggers

• Advanced menu driven human interface
• Real time and transparent emulation up to
12 MHz

• Emulation Memory:
- 64K Program
- 64K External Data

• Disassembler and Single Line Assembler
• Examine/Modify Memory capabilities
• 16 Break and Trace Trigger Conditions

• Full Symbolic Debug Capability

• Supports 80C451
• 9 Probe Clips
7 External Events
1 External Trigger Input
1 External Trigger Output

PHILIPS

• Up to 64K Pass Counts
• Separate Program and Data Memory Mapping
in 16 byte blocks
• Experiment Editor/Compiler
• Trace with 4K frames

PHILIPS
98-8270-070
1034-0001988/IM

Functional Description

Support

The Signetics-80C451 is an in-circuit emulator which is designed for
use in developing, testing and debugging designs based on an 80C451
single chip microcontroller. The Signetics-80C451 allows the development of hardware and software designs to occur simultaneously.
The Signetics-80C451 emulator assists in the following design phases:
• Software Development
_ Integration of target software and
• Manufacturing
system hardware
• Field Service

The Signetics-80C451 emulator not only assists the designer in developing, testing and debugging 80C451 microcontroller designs, but is
also backed by Signetics with an extensive service and support policy
that includes:
• Updates to the Signetics User's Manual and Signetics host Operating System software that are provided at no charge for a ninety
(90) day period .
• Toll free phone number (l-800-A-HLP-4-51) to resolve system
hardware and software concerns.
• A 72-hour repair on disabled systems under warranty.

Features Description
Emulator Functions
• Microcontrollers supported:
80C45 I
• Performance
Real-time .5 MHz to 12 MHz
• Transparency:
Operational and electrical
• Examine and modify:
Program
Internal data
External data

User Interface
• Advanced menu driven operating system
• 11 functional capabilities:
Load
OS-Escape
Upload
Help
Download
Configure
Store
Restore
Interrogate
Exit
Macro

Interrogation
• Allows the user to:
Run experiments
Examine the system status
Set break and trace triggers
Examine/modify data
• 15 functional capabilities:
Run
Single-step
Reset
OS-Escape
Set pass count
Set simple break and trace triggers
Set repetition counter
Set phantom break and trace triggers
Set trace triggers (start, end & center)
View up to 4K of trace buffer
Examine/modify:
Special Function Registers
Internal data memory
External data memory
Program memory
Emulator experiments

Experiment

Macro

• Used to specify break and trace triggers
• Uses the if-then construct
• Allowable trigger conditions are:
PC address
PC address range
Ope ode value
Ope ode class
Special function registers
Direct byte address
Direct byte address range
Direct bit address
Direct bit address range
Immediate operand value
Read/write to bit or direct addresses
External data address
External data address range
Logical AND or OR of any of the above
Pass count overflow
External input
• Over 128,000 break and trace triggers
• Experiment Editor allows user to create or
modify experiments by:
Edit
Delete
Store
Compile
Load
Specify Opcode Class
• Opcode class is collection of 80C45 1
instructions that make up a set.
Set is user defined
Opcade class editor allows user to create,
delete or edit Opcode classes

Move
Search
Compare
Mapping
Examine/modify addressable bits

Symbolic Debug
• User and Pre-Defined Symbols
• Supports MetaLink, Enertec, I AR, Archimedes,
Signetics, Microtec Research or Intel OMF files
• Use a name not address to alter content of:
bits, bytes, code

Optional Products
• MetaWARE Converter compatible with 900
mil wide 64 pin DIP on 100 mil centers.
TN

Electrical Specification
Input Power (typical):
1 amp @ +25 volts DC +/ -5%

Mechanical Specification
Emulator dimensions:
2.0" X 11.0" X 7.62"
5.1 em X 27.9 cm X 19.3 em
Target system cable length:
14.0"
35.6 em
Emulator and target system cable weight:
5.01bs.
2.2 kg
Emulator probe head:
Compatible with 68 lead PLCC (J-Bend) on
50 mil centers

Host Specification
An [BM PC, PC XT, PC AT or 100%
compatible system with 640K bytes of RAM.
PC-DOS 2.0 or later.
Two (2) floppy disk drives.
One (I) RS232C interface card for the PC and
cable

Warranty
Ninety (90) days limited warranty, parts and
labor.

Signefics

Ordering Information

a division of North American Philips Corporation

Order Code: SMI-80C451SD
MelaLink is a trademark of MetaLink Corporation.
PC-DOS, PC, PC XT and PC AT are trademarks of IBM
IBM is a registered trademark of IBM Corporation.
Intel is a registered trademark of Intel Corporation.
©METALINK CORPORATION 1988

• Repetitive routine
• User created, edited and callable at any time

5--5

Signetics Company
811 E. Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088-3409
Telephone 408/991-2000

System Overview
Signetics-83C451
In-Circuit Emulator for
83C451 Microcontroller

• Serially linked to IBM PC or 100%
compatible hosts

• Opcode Class Editor
• Over 128,000 Break and Trace Triggers

• Advanced menu driven human interface
• Real time and transparent emulation up to
12 MHz

• Emulation Memory:
- 64K Program
- 64K External Data

• Disassembler and Single Line Assembler

• Full symbolic Debug Capability

• Examine/Modify Memory capabilities

• Up to 64K Pass Counts
• Separate Program and Data Memory Mapping
in 16 byte blocks

• 16 Break and Trace Trigger Conditions
• Supports both modes:
80C45l with External Addresses
83C45l Single Chip

• Experiment Editor/Compiler
• Trace with 4K frames

• 9 Probe Clips
7 External Events
1 External Trigger Input
1 External Trigger Output

PHILIPS
98-8270-030

5--6

1027-OOO/6SSIIM

Functional Description

Support

The Signetics-83C451 is an in-circuit emulator which is designed for
use in developing, testing and debugging designs based on an 83C451
single chip microcontroller. The Signetics-83C45I allows the
development of hardware and software designs to occur simultaneously.
The Signetics-83C451 emulator assists in the following design phases:
• Software Development
• Manufacturing
• Integration of target software and system hardware
• Field Service

The Signetics-83C45I emulator not only assists the designer in developing, testing
and debugging 83C45 I microcontroller designs. but is also backed by Signetics
with an extensive service and support policy that includes:
• Updates to the Signetics User's Manual and Signetics host Operating System
software that are provided at no charge for a ninety (90) day period.
• Toll free phone number (l-800-A-HLP-4-51) to resolve system hardware and
software concerns.
• A 72-hour repair on disabled systems under warranty.

Features Description
Emulator Functions
• Microcontrollers supported;
83C45 1 80C45 1 87C45 1
• Perfonnance
Real-time .5 MHz to 12 MHz
• Transparency;
Operational and electrical
• Examine and modify:
Program
Internal data
External data

User Interface
• Advanced menu driven operating system
• 11 functional capabilities:
Load
OS-Escape
Upload
Help
Download
Configure
Store
Restore
Interrogate
Exit
Macro

Mode
• Allows user to emulate all the operating modes
of the 83C45 1:
Full 8OC451 operation with external address bus
Single-chip 83C451 with NO external address
bus and 4K of on-chip code memory

Experiment

Symbolic Debug

• Used to specify break and trace triggers
• Uses the if-then construct
• Allowable trigger conditions are:
PC address
PC address range
Opcode value
Opcode class
Special function registers
Direct byte address
Direct byte address range
Direct bit address
Direct bit address range
Immediate operand value
Read/write to bit or direct addresses
External data address
External data address range
Logical AND or OR of any of the above
Pass count overflow
External input
• Over 128,000 break and trace triggers
• Experiment Editor allows user to create or
modify experiments by:
Edit
Delete
Compile
Store
Load
Specify Opcode Class
• Opcode class is collection of 83C45 I
instructions that make up a set.
Set is user defined
Opcode class editor allows user to create,
delete or edit Opcode classes

• User and Pre-Defined Symbols
• Supports MetaLink, Enertec, JAR, Signetics,
Archimedes, Microtec Research or Intel OMF
files
• Use a name not address to alter content of:
bits, bytes, code

Optional Products
• Converter compatible with 900 mil wide 64 pin
DIP on 100 mil centers.

Electrical Specification
Input Power (typical):
1 amp @ + 23 volts DC

+/-

Mechanical Specification
Emulator dimensions:
2.0" x 11.0"x 7.62"
5.1cm x 27,9cm x 19.3cm
Target system cable length:
14.0"
35.6cm
Emulator and target system cable weight:
5.0Ibs.
2.2 kg
Emulator probe head:
Compatible with 68 lead plastic leaded chip
carrier (J-bend) on 50 mil centers

Host Specification
An IBM PC, PC XT, PC AT or 100%
compatible system with 640K bytes of RAM.
PC-DOS 2.0 or later.
Two (2) floppy disk drives.
One (I) RS232C interface card for the PC
and cable.

Warranty
Ninety (90) days limited warranty, parts and
labor.

Macro
• Repetitive routine
• User created, edited and callable
at any time

Signetics
a division of North American Philips Corporation

MetaLink is a trademark of MetaLink Corporation
pc-OOS. pc. PC XT and PC AT are trademarks of IBM.
IBM is a registered trademark of IBM Corporation.
Intel is a registered trademark of Intel Corporation
©METALlNK CORPORATION 1988

5--7

Signetics Company
811 E. Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088-3409
Telephone 408/991-2000

System Overview
Signetics-80C552
In-Circuit Emulator for
80C552 Microcontroller

• Serially linked to IBM PC or 100%
compatible hosts

• Opcode Class Editor
• Over 128,000 Break and Trace Triggers

• Advanced menu driven human interface
• Real time and transparent emulation up to
12 MHz

• Emulation Memory:
- 64K Program
- 64K External Data

• Disassembler and Single Line Assembler

• Full symbolic Debug Capability

• Examine/Modify Memory capabilities

• Up to 64K Pass Counts
• Separate Program and Data Memory Mapping
in 16 byte blocks

• 16 Break and Trace Trigger Conditions
• Supports 80C552

• Experiment Editor/Compiler

• 9 Probe Clips
7 External Events
I External Trigger Input
1 External Trigger Output

• Trace with 4K frames

PHILIPS
5--8

98-8270-060
103Q{lOO!688IIM

Functional Description

Support

The Signetics-80C552 is an in-circuit emulator which is designed for
use in developing, testing and debugging designs based on an 80C552
single chip microcontroller. The Signetics-80C552 allows the
development of hardware and software designs to occur simultaneously.
The Signetics-80C552 emulator assists in the following design phases:
• Software Development
• Manufacturing
• Integration of target software and system hardware
• Field Service

The Signetics-80CSS2 emulator not only assists the designer in developing, testing
and debugging 80C552 microcontroller designs, but is also backed by Signetics
with an extensive service and support policy that includes:
• Updates to the Signetics User's Manual and Signetics host Operating System
software that arc provided at no charge fur a ninety (90) day period.
• Toll free phone number (l-800-A-HLP-4-51) to resolve :'!ystem hardware and
software concerns.
• A 72-hour repair on disabled systemr, under warranty.

Features Description
Emulator Functions
• Microcontrollers supported:
8OC552
• Perfonnance
Real-time 3.5 MHz to 12 MHz
• Transparency:
Operational and electrical
• Examine and modify:
Program
Internal data
External data

User Interface
• Advanced menu driven operating system
• 11 functional capabilities:
Load
OS-Escape
Upload
Help
Download
Configure
Store
Restore
Interrogate
Exit
Macro

Interrogation
• Allows the user to:
Run experiments
Examine the system status
Set break and trace triggers
Examine/modify data
• 16 functional capabilities:
Run
Single-step
Reset
OS-Escape
Set pass count
Set simple break and trace triggers
Set repetition counter
Set phantom break and trace triggers
Set trace triggers (start, end & center)
View up to 4K of trace buffer
Examine ND data
Examine/modify:
Special Function Registers
Internal data memory
External data memory
Program memory
Emulator experiments

Experiment

Symbolic Debug

• Used to specify break and trace triggers
• Uses the if-then construct
• Allowable trigger conditions are:
PC address
PC address range
Opcode value
Opcode class
Special function registers
Direct byte address
Direct byte address range
Direct bit address
Direct bit address range
Immediate operand value
Read/write to bit or direct addresses
External data address
External data address range
Logical AND or OR of any of the above
Pass count overflow
External input
• Over 128,000 break and trace triggers
• Experiment Editor allows user to create or
modify experiments by:
Edit
Delete
Compile
Store
Load
Specify Opcode CIass
• Opcode class is collection of 80C552
instructions that make up a set.
Set is user defined
Opcode class editor allows user to create,
delete or edit Opcode classes

• User and Pre-Defined Symbols
• Supports MetaLink, Enertec, IAR, Signetics,
Archimedes, Microtec Research or Intel OMF
files
• Use a name not address to alter content of:
bits, bytes, code

Optional Products
• Converter

Electrical Specification
Input Power (typical);
I amp @ + 23 volts DC

+/-

Mechanical Specification
Emulator dimensions:
2.0" x 11.0" x 7.62"
5.lcm x 27.9cm x 19.3cm
Target system cable length:
14.0"
35.6cm
Emulator and target system cable weight:
5.0Ibs.
2.2 kg
Emulator probe head:
Compatible with 68 lead plastic leaded chip
carrier (J-bend) on 50 mil centers

Host Specification
An IBM PC, PC XT, PC AT or 100%
compatible system with 640K bytes of RAM.
PC-DOS 2.0 or later.
Two (2) floppy disk drives.
One (I) RS232C interface card for the PC
and cable.

warranty
Ninety (90) days limited warranty, parts and
labor.

Macro
• Repetitive routine
• User created, edited and
callable at any time

Signefics
a division of North Americon Philips Corporotion

MetaLink is a trademark of MetaLink Corporation.
PC-OOS, PC, PC XT and PC AT are trademarks of IBM,
IBM is a registered trademark of IBM Corporation.
Intel is a registered trademark of Intel Corporation.
cMETALINK CORPORATION 1988

5-9

Signetics Company
811 E. Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088-3409
Telephone 408/991-2000

System Overview
Signetics-80C652
In-Circuit Emulator for
80C652 Microcontroller

• Serially linked to IBM PC or 100%
compatible hosts

• Opcode Class Editor
• Over 128,000 Break and Trace Triggers

• Advanced menu driven human interface
• Real time and transparent emulation up to
12 MHz

• Emulation Memory:
- 64K Program
- 64K External Data

• Disassembler and Single Line Assembler

• Full symbolic Debug Capability

• Examine/Modify Memory capabilities

• Up to 64K Pass Counts
• Separate Program and Data Memory Mapping
in 16 byte blocks

• 16 Break and Trace Trigger Conditions
• Supports 80C652
• 9 Probe Clips
7 External Events
1 External Trigger Input
1 External Trigger Output

• Experiment Editor/Compiler
• Trace with 4K frames

PHILIPS
98-8270-020
5-10

1031-o00I688/IM

Functional Description

Support

The Signetics-80C652 is an in-circuit emulator which is designed for
use in developing. testirig and debugging designs based on an 8OC652
single chip microcontroller. The Signetlcs-80C652 allows the
development of hardware and software designs to occur simultaneously.
The Signetics-8OC652 emulator assists in the following design phases:
• Software Development

The Signetics-80C652 emulator not only assists the designer in developing, testing
and debugging 80C652 microcontroller designs, but is also backed by Signetics
with an ex.tensive service and support policy that includes:
• Updates to the Signetics User's Manual and Signetics host Operating System
software that are provided at no charge for a ninety (90) day period.
• Toll free phone number (1-8oo-A-HLP-4-51) to resolve system hardware and
software concerns,
• A 72-hour repair on disabled systems under warranty.

• Manufacturing
• Integration of target software and system hardware
• Field Service

Features Description
Emulator Functions
• Microcontrollers supported:
80C652
• Perfonnance
Real-time 3.5 MHz to 12 MHz

• Transparency:
Operational and electrical
• Examine and modify:
Program
Internal data
External data

User Interface
• Advanced menu driven operating system
• II functional capabilities:
Load
OS-Escape
Upload
Help
Download
Configure
Store
Restore

Interrogate
Macro

Exit

Interrogation
• Allows the user to:

Run experiments
Examine the system status
Set break and trace triggers
Examine/modify data
• 15 functional capabilities:
Run
Single-step

Reset
OS-Escape
Set pass count
Set simple break and trace triggers
Set repetition counter
Set phantom break and trace triggers
Set trace triggers (start, end & center)
View up to 4K of trace buffer

Examine/modify:
Special Function Registers
Internal data memory
External data memory
Program memory

Emulator experiments

Macro

Experiment
• Used to specify break and trace triggers
• Uses the if-then construct
• Allowable trigger conditions are:
PC address
PC address range
Opcode value
Opcode class
Special function registers
Direct byte address
Direct byte address range
Direct bit address
Direct bit address range
Immediate operand value
Read/write to ·bit or direct addresses
External data address
Externlll data address range
Logical AND or OR of 'my of the above
Pass coUnt overflow
External input
• Over 128,000 break and trace triggers
• Experiment Editor allows user to create or
modify experiments by:
Edit
Delete
Store
Compile
Load
Specify Opcode Class
• Opcode class is collection of SOC6S2
instructions that make up a set.
Set is user defined
Opcode class editor allows user to create,
delete or edit Opcode classes

• Repetitive routine
• User created, edited and callable at any time

Symbolic Debug
• User and Pre-Defined Symbols
• SuPPOrts MeiaLink, Enertec, JAR, Signetics,
Archimedes, Microtec Research or Intel OMF
files
• Use a name not address to alter content of:
bits, bytes, code

Electrical Specification
Input Power (typical):
I amp@ + 23 volts DC

+/-

Mechanical Specification
Emulator dimensions:
2.0" X 11.0" X 7.62"
S.lcm x 27.9cm x 19.3cm
Target system cable length:
14.0"
35.6cm
Emulator and target system cable weight:
5.0lbs.
2.2 kg
Emulator probe head:
Compatible with 40 lead DIP on 100 mil
centers

Host Specification
An IBM pc, PC XT, pc AT or 100%
compatible system with 640K bytes of RAM.
PC-DOS 2.0 or later.
Two (2) floppy disk drives.
One (1) RS232C interface card for the PC
and cable.

Warranty
Ninety (90) days limited warranty, parts and
labor.

Signetics
a division of North American Philips Corporation
MetaLink is a trademark of MetaLink Corporation.
PC-DOS, PC, PC XT and pC AT are trademarks of IBM.
mM is a registered trademark of IBM Corporation.
Intel is a registered trademark of Intel Corporation.
oMETALINK CORPORATION 1988

5-11

Signeties Company
811 E. Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088-3409
Telephone 408/991-2000

System Overview
Signetics-83C751
In-Circuit Emulator for
83C751 Microcontroller

• Serially linked toIBM PC or 100%
compatible hosts

• Opcode Class Editor

• Advanced menu driven human interface

• Emulation Memory:
- 2K Program

• Real time and transparent emulation up to
16 MHz
• Disassembler and Single Line Assembler

• Break and Trace Triggers

• Fuil symbolic Debug Capability

• Examine/Modify Memory capabilities

• Up to 64K Pass Counts
• Program Mapping in 16 byte blocks

• 14 Break and Trace Trigger Conditions

• Experiment Editor/Compiler

• Supports 83C751

• Trace with 4K 4ames

• 9 Probe Clips
7 External Events
1 External Trigger Input
1 External Trigger Output

PHILIPS
5-12

98-8270-040
1028-000J688/1M

Functional Description

Support

The Signetics-83C751 is an in-circuit emulator which is designed for
use in developing, testing and debugging designs based on an 83C751

The Signetics-83C751 emulator not only assists the designer in developing, testing
and debugging 83C751 microcontroller designs, but is also backed by Signetics
with an extensive service and support policy that includes:
• Updates to the Signetics User's Manual and Signetics host Operating System
software that are provided at no charge for a ninety (90) day period.
• Toll free phone number (l-800-A-HLP-4-51) to resolve system hardware and
software concerns.
• A 72-hour repair on disabled systems under warranty.

single chip microcontroller. The Signetics-83C75I allows the
development of hardware and software designs to occur simultaneously.
The Signetics-83C75I emulator assists in the following design phases:
• Software Development
• Manufacturing
• Integration of target software and system hardware
• Field Service

Features Description
Emulator Functions
• Microcontrollers supported:
83C751, 87C751
• Performance
Real-time 3.5 MHz to 16 MHz
• Transparency:
Operational and electrical
• Examine and modify:
Program
Internal data

User Interface
• Advanced menu driven operating system
• 11 functional capabilities:
Load
OS-Escape
Upload
Help
Download
Configure
Store
Restore
Interrogate
Exit
Macro

Interrogation
• Allows the user to:
Run experiments
Examine the system status
Set break and trace triggers
Examine/modify data
• 14 functional capabilities:
Run
Single-step
Reset
OS-Escape
Set pass count
Set simple break and trace triggers
Set repetition counter
Set phantom break and trace triggers
Set trace triggers (start, end & center)
View up to 4K of trace buffer
Examine/modify:
Special Function Registers
Internal data memory
Program memory
Emulator experiments

Experiment

Macro

• Used to specify break and trace triggers
• Uses the if-then construct
• Allowable trigger conditions are:
PC address
PC address range
Opcode value
Opcode class
Special function registers
Direct byte address
Direct byte address range
Direct bit address
Direct bit address range
Immediate operand value
Read/write to bit or direct addresses
Logical AND or OR of any of the above
Pass count overflow
External input
• Break and trace triggers
• Experiment Editor allows user to create or
modify experiments by:
Edit
Delete
Compile
Store
Load
Specify Ope ode Class
• Opcode class is collection of 83C751
instructions that make up a set.
Set is user defined
Opcode class editor allows user to create,
delete or edit Opcode classes

Examine/Modify Memory
• Program memory operations:
Disassemble
Single line assemble
Examine/modify raw data
Mapping
• Microcontroller internal memory operations:
Dump
Scan and modify
Fill
Move
Search
Compare
Examine/modify addressable bits

• Repetitive routine
• User created, edited and callable at any time

Symbolic Debug
• User and Pre-Defined Symbols
• Supports MetaLink, Enertec, IAR, Signetics,
Archimedes, Microtec Research or Intel OMF
files
• Use a name not address to alter content of:
bits, bytes, code

Electrical Specification
Input Power (typical):
I amp @ + 23 volts DC

+/-

Host Specification
An IBM PC, PC XT, PC AT or 100%
compatible system with 640K bytes of RAM.
PC-DOS 2.0 or later.
Two (2) floppy disk drives.
One (I) RS232C interface card for the PC
and cable,

warranty
Ninety (90) days limited warranty, parts and
labor.

Signetics
a division of North American Philips Corporation
MClaLink is a trademark of MctaLink Corporation.
PC-DOS, PC, PC XT and PC AT are trademarks of IBM.
IBM is a registered trademark of IBM Corporation
Intel is a registered trademark of Intel Corporation
fJMETALINK CORPORATION 1988

5--13

Signetics Company
811 E. Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088-3409
Telephone 408/991-2000

System Overview
Signetics-ASM51
8051 Macro
Cross Assembler

• IBM PC or 100% Compatible Host
• Supports All Members of the MCS-Sl Family

• Symbolic Access to Predefined Hardware
Registers

• Supports All S Memory Spaces
• Uses Standard Mnemonics and Syntax

• Fast Assembler Execution Time
• Full Range of Assembly Time Operators,
Complete Listing and Output Controls and
choice of Radix

• Generates Intel HEX and MetaLink or
Signetics Debug Format for use with
Signetics emulators

• INCLUDE Statement Allows Development of
Code In Modules

• Conditional Assembly and Full Macro
Capability including Nesting

PHILIPS
98-8270-050

5-14

l032-o00!688flM

Functional Description
The Signetics-ASM5! Macro Cross Assembler takes an assembly language source file created with a text editor and translates it into a machine language object
file. This translation process is done in two passes over the source file. The Signetics-ASM51 Macro Cross Assembler is supported on IBM PCs and as such
has faster assembly times than traditional methods. The Signetics-ASMS t Macro Cross Assembler supports modular code development or will assemble
previously developed code modules through the use of the INCLUDE capability that brings together these code modules at assembly time.

Features Description
Products Supported
8052
8032

8051
8031

83C75 I
87C75 I

80C45 I
83C451
87C451

80C552
83C552
87C552

80C51
80C31
87C51

80C652
83C652
87C652

Instructions Supported

Conditional Assembly

• Standard mnemonics plus generic CALL/IMP.

Assembly Time Operators
• Operations supported are: +, -, HIGH, LOW,
MOD, /, *, SHR, SHL, NOT. AND, OR,
XOR, =, <, >, <>, <=, >=.
• Operations are done in 16-bit 2's complement
arithmetic.

Listing Controls
Symbols
• Symbols can be up to 255 characters long, with
the first 32 being significant
• Symbols character set include:
? and _
(underline)
A ... Z

a ...

0 ... 9

Numbers
• Numbers can be entered in decimal (default),
binary, hexadecimal or octal.

Predefined Addresses
• All MCS-51 architecturally defined Special
Function Registers (SFR) are symbolically
defined in the Signetics-ASM51 Macro Cross
Assembler.

• IF-THEN-ELSE conditional capability, nested
up to 255 levels.

Macro Capability
• Full macro capability exists with up to nine (9)
levels of nesting.
• Up to 16 parameters can be specified in a
macro.

Assembler Type

• Controls supported: Title, Date, List, Nobst,
Paging, Nopaging, Eject, Pagelength and
Pagewidth.

• Two (2) pass, absolute assembler.

Minimum System Requirements
An IBM PC, PC XT, PC AT or 100%
compatible system with 96K bytes of RAM.
PC-DOS 2.0 or later.
One (I) ftoppydisk drive.

Output Controls
• Controls supported: Object, Noobject, Print,
Noprint, Symbols, Nosymbols and Debug.

Object File Format

Warranty

• Standard Intel Hexadecimal Object Code
Format.
• MetaLink or Signetics Debug Format for use
with Signetics emulators.

Ninety (90) days free update service.

Include Capability
• Any number of files can be included in the
source file, nested up to eight (8) levels deep.

Memory Spaces Supported
• Code, Data, Bit, External and Indirect.

Signetics
a division of North American Philips Corporation
MetaLink is a trademark of MetaLink Corporation
PC-DOS, PC, PC XT and PC AT are trademarks of IBM.
IBM is a registered trademark of IBM Corporation.
Intel is a registered Irademark of Intel Corporation.
©METALINK CORPORATION 1988

!'>-15

Signetics Company
811 E. Arques Avenue
P.O. Box 3409
Sunnyvale, Califomia 94088-3409
Telephone 408/991-2000

Universal EPROM Programmer
SPGM-100 EPROM Microcontroller
and Standard EPROM Programmer
FEATURES
o Supports standard EPROMs
o Modules Available for Microcontroller Support
lEt 87C751
lEt 87C752
lEt Others to follow
o Connects to IBM PC or 100%
Compatibles

o Uses standard, intelligent and
quick pulse programming algorithms
o 8K x 8 Data Buffer Standard
(32K, 64K Optional)
o Supports Intel Hex Format
o System Includes Power Supply,
RS-232 Cable, System Software,
Documentation and Programmer

PROGRAMMING
SITE

SPGM-100

SPGM-100 System Block Diagram

OPERATIONS
o
o
o
o
o
o
o
o
o

Select EPROM Type
Blank Check
Program EPROM array
Display!Alter Data Buffer
Fill Buffer with Constant
Copy EPROM to Buffer
Verify EPROM Versus Buffer
Error Display (Program/Verify)
Help

5-16

Signetics

Microprocessor Products

Section 6
Additional
Microcontroller
Data Sheets

INDEX
8X305
Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-3
8X401 Microcontroller
SCN8049 Series.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-28
........................................ 6-48

Signetics

8X305
Microcontroller
Product Specification

Microprocessor Products

FEATURES
• Fetch, Decode, and Execute a
16-bit instruction in a minimum
of 200 ns (one machine cycle)
• Bit-oriented instruction set
(addressable single-or-multiple bit
subfields)
• Separate buses for Instruction,
Instruction Address and ThreeState I/O
• Thirteen 8-bit general-purpose
working registers
• Source/destination architecture
• Bipolar low-power Schottky
technology/TTL inputs and
outputs
• On-chip oscillator and timing
generation
• Single + 5V supply
• 0.9-in. 50-pin DIP
• 68-Pin PLCC

PRODUCT DESCRIPTION
The Signetics 8X305 Microcontroller
(Figure 1) is a high-speed bipolar microprocessor implemented with low-power
Schottky technology. In a single chip,
the 8X305 combines speed, flexibility,
and a bit-oriented instruction set. These
features and other basic characteristics
of the chip combine to provide costeffective solutions for a broad range of
applications. The 8X305 is particularly
useful in systems that require highspeed bit manipulations - sophisticated
controllers, data communications, very
fast interface control, and other applications of a similar nature.
The 8X305 can fetch, decode, and execute a 16-bit instruction word in a mini-

mum of 200ns. Within one instruction
cycle, the 8-bit data-processing path can
be programmed to rotate, mask, shift,
and/or merge single or multiple bit subfields and, in addition, perform an ALU
operation. In the same instruction, an
external data field can be input, processed, and output to a specified destination -likewise, single or multiple bit
data fields can be internally moved from
a given source to a given destination. To
summarize, fixed or variable-length data
fields can be fetched, processed, operated on by the ALU, and moved to a
different location - all in a timeframe of
200ns. To interface with I/O and program memory, the 8X305 uses a 13-bit
instruction address bus, a 16-bit instruction bus, an 8-bit bidirectional multiplexed I/O data/address bus and a 5-bit
I/O control bus.

PIN CONFIGURATION
N, I PACKAGES

A wide selection of I/O devices, interface chips, and special-purpose parts
are available for systems use. In most
applications, the more powerful 8X305 is
functionally interchangeable with its predecessor-the 8X300.

ASSOCIATED DOCUMENTATION
Other documents directly relating to design and applications use of the 8X305
Microcontroller are:
• Product Capabilities Manual
• 8X305 Users Manual
These documents and other current literature (Data Sheets, Product Bulletins,
Applications Notes, etc.) are available at
all Signetics Sales and Service Offices - see rear cover of this data sheet
for the office in your locality.

TOP

view

ORDERING INFORMATION
DESCRIPTION

ORDER CODE
N8X305N

50-Pin plastic DIP
50-Pin ceramic DIP

N8X3051

68-Pin PLCC

N8X305A

December 17, 1986

6-3

853-0925 086958

s:
o·
a
0

CD
CD

-""
CD
CD
0>

PROGRAM COUNTER

...

leyend:
•

DATA REGISTERS -

DATA

o_
~ -. :::~:~g~:g= ~~~TROL

...

~~~:~~EXTERNAL

G!(N:::3i!

~Vcc

Not. . 11t1

G G

~~~~~: AND ADDRESS

I(N~::2)!
.n
(Nole 3)

~~[i~

'l:J-(:t.L-J.

----I

JV1
M

iV'3

~Jrt±~
38

•

IV.

jliM

.w
sc
we

' '=H
,"

r(/

2'-

'12

......

:[:lK

'"
'n

"AU

.ESET

NOTES:
1. Registers R1-R6, All and A14-R16 are general-purpose working registers.
2. In any instruction where R7 (IVL) or Rll (IVA) is specified as the destination, the a-bit value is output on the IV bus as an IV device enable address (SC "" High) - R7 = left bank and Rll = right bank; the results are also stored into the
specified internal register and may later be accessed as source data.
3. R12 and R13 are general-purpose working registers for all operations except transmit (XMIT).
4. The feast significant bit of register R10 (OVF) is used to reflect the carryout status resulting from the most recent ADD operation.
5. Auxiliary register RO # 1 is a general-purpose working register that holds the implied operand for Arithmetic and Logical operations; the content of this register is repeated in AUX # 2 (shown dotted). The duplicate register is physically
part of the ALU and is shown separate only for layout convenience.
6. Internal working registers cannot be operated on by the MASK logic.
7. During NZT instructions the ALU tests for all bits equal to "0" (Transfer if A 0) -refer to BASIC OPERATIONS that follow.

Figure 1. Architecture and· Pin Designations for 8X305 Microcontroller
Pin Numbers Shown are for DIP Packaging

-u

8.c
Q.

~o
3;

S.(5::J

Signetics Microprocessor Products

Product Specification

8X305

M icrocontroller

VCRQ

~VR

.. ~
.. [!

~"'10

.. [1

~ ..

~Al1

A3~

~Al1

~HALT

A2[!

Al~

INDEX
CORNER

RESET

~MCLK

.. [!

~iYO
~iV1
~iV2
~iVa

12@

~iV4

X1§
X2~
GND@

PLCC

~vcc

11~

la§

~iVs

I.~
15~

~iVi

26
27

!!lUi

I.~
,,~

~wc

111~

!!1h4

TOP VIEW

~RB

11~

COOO68PS

~sc

hO~

~115

112~

~113
CD09<0
<0(,)

LEFT BANK

(,)

RIGHT BANK

1-0F·258

I/'.'---::---I~ ADDRESSABLE
LOCA110NS

Figure 3. Typical 8X305 System Hookup

December 17, 1986

6-7

Signetics Microprocessor Products

Product Specification

8X305

Microcontroller

BASIC OPERATIONS OF 8X305
Refer to a later discussion of "Instruction Fields" for a detailed examination of ali operand fields and subdivisions thereof - "S" (So, S1), "0"
(Do, 0 1), "R", "L", "J", and "A".

MOVE OPERATIONS
I---------------REGISTER-TO-REGISTER-------------SOURCE

DATA PROCESSING
(PRE-ALU)

RD-R 1? as specified by _
"8" field of instruction.

Right rotate as specified
by "R" field of
instruction.

ALU

DATA PROCESSING
(POST-ALU)

DESTINATION

No operation.

RD-R?, R11-R17 as
specified by "0" field of
instruction.

1 - - - - - - - - - - - - - - - - REGISTER-TO·W
SOURCE

DATA PROCESSING
(PRE-ALU)

RD-R17 as specified by _
"8" field of instruction.

No operation.

BUS - - - - - - - - - - - - - - - DATA PROCESSING
(POST-ALU)

ALU
_

No operation.

Shift and merge as

DESTINATION

specified by "Do" and
"L" fields of instruction.

Variable length field of iV
bus - Left Bank (03) or
Right Bank (RB) as
specified by "Do" and
"01" fields of instruction.

I - - - - - - - - - - - - - - - I V BUS-TO-REGISTER - - - - - - - - - - - - - - SOURCE
Variable length field of iV
bus - Left Bank (03) or
Right Bank (RB) as
specified by "S,' and
"SO" fields of instruction.

DATA PROCESSING
(PRE-ALU)

ALU

DATA PROCESSING
(POST-ALU)

Right rotate and mask ,..
as specified by "So" and

No operation.

ilL" fields of instruction.

DESTINATION

RD-R?, R11-R17 as
specified by "0" field of
instruction.

1---------------- IV BUS-TO-IV BUS
SOURCE
Variable length field of iV
bus - Left Bank (03) or
Right Bank (RB) as
specified by "S,' and
"So" fields of instruction.

December 17, 1986

DATA PROCESSING
(PRE-ALU)

Right rotate and mask
as specified by ,r So " and
ilL" fields of instruction.

ALU

No operation.

DATA PROCESSING
(POST-ALU)
Shift and merge as

specified by "Do" and
"L" fields of instruction.

DESTINATION

....

Variable length field of iV
bus - Left Bank (03) or
Right Bank (RB) as
specified by "Do" and
"0 1" fields of instruction.

6-8

Signetics Microprocessor Products

Product Specification

8X305

Microcontroller

ADD OPERATIONS
REGISTER-to-REGISTER

-..ISOURCEI-..lpRE-ALUf--1

-"ISOURCEI-"lpRE-ALU~_1

IV BUS-to-REGISTER

-"ISOURCEI-"lpRE-ALU~_1

IV BUS-to-IV BUS

-..ISOURCEI-..lpRE-ALUf--1

Same as MOVE operations, except source
data is ADDed to contents of AUXiliary
Register RO via the ALU; if appropriate,
Overflow Register RIO (OVF) is also set.

I~POST-ALUI-"1

DEST

1-..1

DEST

I~POST-ALUI-"1

DEST

I~POST-ALUI-"1

DEST

1-..1

DEST

l~ POST-ALU 1-..1

DEST

l~ POST-ALU

AND OPERATIONS
REGISTER-to-REGISTER

l~ POST-ALU

-..ISOURCEI-..lpRE-ALUf--1
Same as MOVE operations, except source
data is ANDed with contents of AUXiliary
Register RO via the ALU.

-..ISOURCEI-..lpRE-ALUf--1

IV BUS-to-REGISTER

-..ISOURCEI-..lpRE-ALUf--1

I~POST-ALUI-"1

DEST

IV BUS-to-IV BUS

-..ISOURCEI-..lpRE-ALUf--1

l~ POST-ALU

1-..1

DEST

I~POST-ALUI-"1

DEST

EXCLUSIVE OR (XOR) OPERATIONS
REGISTER-to-REGISTER

-..ISOURCEI-..lpRE-ALUf--1

I~POST-ALUI-"1

DEST

IV BUS-to-REGISTER

-..ISOURCEI-..lpRE-ALUf--1

I~POST-ALUI-"1

DEST

IV Bus-to-IV BUS

-..ISOURCEI-..lpRE-ALUf--1

I~POST-ALUI-"1

DEST

Same as MOVE operations, except source
data is Exclusively ORed with contents of
AUXiliary Register RO via the ALU.

EXECUTE (XEC) OPERATIONS
XEC, REGISTER
SOURCE
RO - R17 as specified by
"S" field of instruction.

DATA PROCESSING
(PRE-ALU)
No operation.

ALU

Add source data to 8-bit
field specified by
instruction literal

(0 < J < 377.).

DATA PROCESSING
(POST-ALU)
No operation.

DESTINATION

Replace 8 LSB of
Address Register

with

8-bit sum from ALU.
• PG M eTR unchanged.

XEC,
SOURCE
Left or Right Bank of 117
bus as specified by "S"
field of instruction.

December 17, 1986

DATA PROCESSING
(PRE-ALU)
Rotate and mask as
specified by "So" and
"L" fields of instruction.

IV BUS

ALU
Add masked field of
source data to 5-bit
literal specified by "J"
field of instruction
(0 .

No operation.

ALU

DATA PROCESSING
(POST-ALUl

No operation.

DATA PROCESSING
(PRE-ALUl

0 .. J .. 3778 - value
specified by "J" field of
instruction.

No operation.

o .. J .. 378 - value
specified by "J" field of
instruction.

December 17, 1986

ALU

DATA PROCESSING
(PRE-ALUl

No operation,

RO-R7, R11, R14-R1·7.
Load a-bit integer

DESTINATION

DATA PROCESSING
(POST-ALUl
No operation.

XMIT VARIABLE-BIT FIELD IMMEDIATE
SOURCE

BUS

ALU

No operation.

specified by "J" field
into register specified by
"0" field.

XMIT 8-BIT IMMEDIATE,
SOURCE

DESTINATION

No operation.

6-10

Left (R12) or Right (R13)
Bank of iV bus as
specified by "0" field of
instruction.

BUS

DATA PROCESSING
(POST-ALUl
Shift and merge source
data as specified by
"00" and "L" fields of
instruction.

DESTINATION

Left or Right Bank of iV
bus as specified by "0"
field of instruction.

Signetics Microprocessor Products

Product Specification

8X305

Microcontroller

Table 1.
LB

FUNCTION

tion, anyone or all of the functions (Rotate/
Mask/Shift/Merge) can operate on 8 bits of
data in a single instruction cycle. For a
summary of all data-processing capabilities,
refer to BASIC OPERATIONS OF THE 8X305
described earlier in this data sheet.

Low

This state is not generated by the 8X305.

Low

High

Enable left bank devices.

High

Low

Enable right bank devices.

Instruction Cycle

High

Disable all devices; IV bus is 3-State.

Each operation of the 8X305 is executed in a
single instruction cycle. The instruction cycle
is internally divided into four equal partseach part being as short as 50ns. Figure 4
shows the general functions that occur during
each quarter cycle; specifics regarding minimum/maximum timing and other critical values are described later in this data sheet.
During the first quarter cycle, a new instruction from program storage is input via 10 - 115
and decoded. If an I/O operation is indicated,
new data is fetched from a specified internal
register or via the TV bus. At the end of the
first quarter cycle, the new instruction is
latched into the instruction register.

Table 2.
LB/RB

High

Low

The IV bus is 3-State and not looking for
input data.

FUNCTION

The IV bus is reading input data.

Low

High

Data is being output.

Low

High

Low

Address is being output.

High

This condition is never generated.

Program Storage Interface
As shown in Figure 3, program storage is
connected to output address lines Ao through
A12 (A 12 = LSB) and input instruction lines 10
through 115. An address output on Aol A12
identifies one 16-bit instruction word in program storage. The instruction word is subsequently input on 10/115 and defines the MicroController operation which is to follow - one
instruction word equals one completed operation. Any TIL-compatible memory can be
used for program storage provided the worstcase access time is compatible with the
instruction cycle time used for the application - see timing section for appropriate calculations.

I/O Interface and Control
An 8-bit bidirectional I/O bus, referred to as
the Interface Vector (TV) bus, provides a
communication link between the Microcontroller and the two banks of I/O devices. The
LB (Left Bank) and RB (Right Bank) control
signals identify which bank is enabled; when

December 17, 1986

both LB and RB are high (inactive), neither
bank is enabled and the TV bus is inactive
(three-state). A functional analysis of the Left
and Right Bank signals is shown in Table 1.
Both data and I/O address information are
multiplexed on the TV bus. The SC (Select
Command) and WC (Write Command) signals
distinguish between data and I/O address
information as shown in Table 2.

Data Processing
Basically, the data processing path of the
8X305 consists of the Rotate/Mask logic, the
Arithmetic Logic Unit (ALU), the Shift/Merge
functions, on-chip memory (sixteen 8-bit registers), and the bidirectional TV bus interface
with its associated driver circuits and internal
latches. The on-board memory and the TV bus
are connected to both inputs and outputs of
the ALU via internal 8-bit data paths - see
Figure 1. Inputs to the ALU are preceded by
right-rotate and data-mask functions; the ALU
output is followed by the left-shift and merge
operations. Depending on the desired opera-

6-11'

In the second quarter cycle, the I/O input
data stabilizes and preliminary processing is
completed. At the end of this quarter, the TV
latches close and final processing can be
accomplished, thus completing the input
phase of the instruction cycle. During the third
quarter cycle, the address for the next instruction is output to the instruction address
bus, TV control signals are generated, and
both data and destination are setup for the
remainder of the output phase. During the
fourth quarter cycle, a master clock signal
(MCLK) generated by the 8X305 is used to
latch either the I/O-enabling address or the
I/O data into peripheral devices connected to
the TV bus. MCLK can also be used to
synchronize any external logic with timing
circuits of the 8X305. To summarize the
action, the first half of the instruction cycle
deals primarily with input functions and the
second half is mostly concerned with output
functions.

Signetics Microprocessor Products

Product Specification

M icrocontroller

8X305

"II-

r--INPUTPHASE

----.r

~I_ _--'

.J
I

101

2nd

INSTRUCTION SET
General Format and Operating
Principles

OUTPUTPHASE~

31d

The 16-bit instruction word (10 through 115)
from program storage is input to the instruction register (Figure 1) and is subsequently
decoded to implement the events to occur
during the current instruction cycle.

41h

j-4-QUARTER--f--QUARTER~QUARTER~QUARTER~

sons

SOnl

SOna

SOns

INPUT
INSTRUCTION,
DECODE
INSTRUCTION
AND, IF
REQUIRED,
FETCH NEW
DATA

LATCH AND
PROCESS
INPUT DATA

NEXT
INSTRUCTION
ADDRESS,
GENERATE
CONTROL
SIGNALS, AND
SETUP 1/0
DATA FOR
OUTPUT

LATCH I/O
ENABLING
ADDRESS OR
110 DATA INTO
SELECTED
PERIPHERAL.

~~-------------~If-

The general format for each instruction word
is shown in Table 3.
The 3-bit operation code (OPCODE) define
anyone of eight classes of instructions;
variations within each class are specified by
the remaining thirteen operand bits. The eight
instruction classes can be separated into two
control areas - data and program; general
functions within these areas are as shown in
Table 4.

IICLK
(ACTIVE--I
STATE)

NOTES:
1. New instruction must be accepted and latched at end of first quarter cycle.
2. The 1/0 data latches are open for the first two quarter cycles, that is, for 1DOns.
3. The address changes during third quarter cycle.
4. iV bus drivers are active (turned on) during third and fourth quarter cycles.

Instruction Fields

Figure 4. Instruction Cycle and MCLK with: Crystal = 10MHz and
Cycle Time = 200ns.

Table 3.

MSB

BIT POSITIONS -->

LSB

678

OPERAND(S)

Table 4.
• Data ControlADD
AND
Arithmetic and Logic Operations
XOR

1
1

MOVE
Movement of Data and Constants
XMIT
• Program ControlXEC
NZT
JMP

Branch or Test

December 17, 1986

6-12

!
15

As shown in Table 5, each instruction word
consists of an operation code (OPCODE)
field and from one to three operand fields.
The possible operand fields are: Source (S),
Destination (D), Rotate/Length (R/L), Literal
(J), and Address (A). The OPCODE and
operand fields are described in the paragraphs that follow the table.

Product Specification

Signetics Microprocessor Products

8X305

Microcontroller

Table 5. Functional Description of Instruction Set
STATE OF CONTROL SIGNAL
DURING INSTRUCTION CYCLE
SEE FIGURE 4

INSTRUCTION WORD

CLASS

= MOVE

OPCODE

DESCRIPTION

OPERATION

= (5)

Reglster-ta-Register

~!c:o~:

1 3141 : 1617181:

5-00.-17. D-00.-07., 11.-17.

IopeODE I

I
I

5-00.-17. D-20.-37.

IV Bus-ta-Reglster (Note)
1 0 1'12131415161718191'01"1'21'31'41'51
5
L
D
opeODE

I
I

5,
So
5=20.-37. D=00.-07., 11.-17.

IV Bus-ta-IV Bus (Note)
101'12131415161718191'01"1'21'31'41'51
5
L
D
10PCODE

I
I

5,
So
5 - 20.-37. D-20.-37.

CLASS = ADD OPCODE

I
L D,

OPERATION

CLASS

= AND

OPCODE

OPERATION

= XOR

OPCODE

OPERATiON

= XEC

OPCODE

OPERATION

~!e~~: 1 3141 :

= (5) Ell (AUX)

--+

H if D-07., 17.

--+

L if D-07.

L if D-17.
L

we
LB

L if D-20.-27. LifD-20.-27.

liB

L il D-30.-37. L if D-30.-37.

Ui
"FiB

Lit 5-20.-27.

LHD-07.

L H 5-30.-37.

L H D-17.

Ui
"1m

H H D=07., 17.

L if 5 = 20.-27. L H D-20.-27.
L H 5-30.-37. L H D - 30.-37.

Same as MOVE instruction class

0
Same as MOVE instruction class

Same as MOVE instruction class except that
contents of AUX (RO) register are Exclusively
ORed with source data.

= Refer

OUTPUT PHASE

Same as MOVE instruction class except that
contents of AUX (RO) register are ANDed
with source data.

Same as MOVE instruction class

to Description

Move right-rotated iV bus (source) data
specified by the 5-fietd to the 110 latches.
Before outputting on 1i7 bus, shift data as
specified by the D-field; then merge source
end latched 110 data as specified by the L
(length) field.

= (5) /\ (AUX)

Same as MOVE instruction class

CLASS

Move right-rotated iV bus (source) data
specified by the 5-field to internal register
specified by \he D-field. The L-field specHies
the length of source data starting from the
L5B-position and, if less than B bits, the
remaining bits are filled w:ith zeros.

Same as MOVE instruction class except that
contents of AUX (RO) register are ADDed to
the source data. If there is a "carry" from
MSB, then RIO (OVF) = 1 (overflow),
otherwise OVF = O.

Same as MOVE instruction class

CLASS

Move contents of internal register specified by
the 5-field to the iV bus. Before outputting on
iV bus, data is shifted as spec~ied by the least
significant octal dign of the D-field and the bits
specified by the L-field are merged with the
latched 110 data.

= (S) + (AUX)

Same as MOVE instruction class

INPUT PHASE

D
Move content of internal register specified by
5-field to internal register specified by D-field.
Prior to the "MOVE" operation, right-rotate
contents of internal source register by octal
value (0 through 7) defined by the R-field.

1,01"1'21~HI5!

CONTROL
SIGNAL

1617IBI9110111!'21'3HI5!

S - 00.-17. J-000.-377.

Execute instruction at current page address
oIIset by J (literal) + (5). Return to normal
instruction flow unless a branch is
encountered.
Execute instruction at an address determined
by replacing the low-order B bits of the
Address Register with the following derived
sum:
Value of Ineral (J-field) plus contents of
internal register specified by S-field
The PC is not incremented and the overflow
status (OVF) is not changed.

IV Bus Immediate (Note)
1 0 1'12131415161718191'01"1'21'31'41'51
5
L
J
OPCODE

I
I s,

5=20.-37. J-00.-37.

December 17, 1986

I
I

Execute instruction at an address determined
by replacing the low-order 5 bits of Address
Register with the following derived sum:
5-b~ value of literal (J-field) plus value of
rotated source data specified by S-field.
The L-field specifies the length of source
data starting from the LSB position and, if
less than B bits, the remaining bits are filled
with zeros; the Program Counter is not
incremented and the overflow status (OVF)
is not changed.

6-13

L if 5- 203-27.

L if 5-30.-37.

Product Specification

Signetics Microprocessor Products

8X305

M icrocontroller

Table 5. Functional Description of Instruction Set (Continued)
STATE OF CONTROL SIGNAL
DURING INSTRUCTION CYCLE
SEE FIGURE 4

INSTRUCTION WORD

CLASS = NZT OPCODE

DESCRIPTION

OPERATION

= Refer

~le~l:

161718191101ll~12113H151

data specified by the 8-field is not equal to

zero, jump to current page address offset by

value of

J~field;

otherwise, increment the

Program Counter.

J ~ ODD. - 377.

S~00.-17.

INPUT PHASE

OUTPUT PHASE

to Description

CONTROL
SIGNAL

If contents of internal register specified by S-

field is non-zero, transfer to address
determined by replacing the low-order 8 bits
of Address Register and Program Counter
with "J", otherwise, increment PC.

Bus Immediate (Note)

D 11

OPCODE

5,
5 ~ 20.-37, J ~

If right-rotated and masked IV bus is nan-

81 9 110 11112113114115

31 4 1 5 1 6 1 7
5

zero, transfer to address determined by
replacing low-order 5 bits of Address
Register and Program Counter with "J",
otherwise, increment PC. (The L-field
specifies the length of source liD data
starting from the LSB-position and, if less
than 8 bits, the remaining bits are filled with

50
00, - 37.

L if S=208-278

L if

5~30,-37,

zeros.)

= XMIT

CLASS

OPCODE

OPERATION

XMIT, Register
1

~le~l:

1 3141

D~00,-06,.

XMIT,

oj 1"[2
OPCODE

~ 161718191101ll~12113H15i

D
Store a-bit value specified by "J" into
register specified by "D".

11,. 14.-16. J ~ ODD. - 377.

Bus Address

31 4 1 5 6 J7
D

J 9 LlO

11112]13114]15
J

Enable 110 device on the bank specified by
"0". whose address is the 6-bit integer
specified by "J". Address "J" is stored in
register "0".

D = 078. 178 J ~ 000,-377.

XMIT 8 Bits Immediate,

o 11

OPCODE

31 4 1 5 1 6 1 7
D

D~12.-13.

Bus (Note)

819110 111121131141151
J

or RB) specified by "0". Contents of R12 or
R 13 remain unchanged.

J ~ ODD. - 377,

XMIT Variable Bit Field Immediate,
011 12
OPCODE

Store value of a-bit integer in the previously
enabled 110 port, at the bank destination ([8

31 4 1 5 1 6 1 7
D

Bus (Note)

8 19110 11112113114115
L

Transmit Least SignificE!!:!.t "L" bits of "J"

field to "L-bit" field of IV bus specified by
"0"; if "L" is greater than 5 bits, the M8B
bits of destination field is filled with zeros.

D,
Do
D - 20.-37. J-00.-37.
CLASS

= JMP

OPCODE

OPERATION

= Refer

Address Immediate
1 0 11 1213141s1617161elfOlni12113H1Si
OPCODE
A
A

Jump to address in program storage

specified by A-field; this address is loaded
into the Address Register and the Program
Counter.

the L8B of rotated input data field
the bank of iV bus from which source data will be input
bit position in 1/0 device with which L8B of processed data will be aligned, and
the bank of iV bus which will be the destination.

December 17, 1986

L
L

L if

D~07,

L if

D~17.

LifD~12.

L if

D~13,

L if

D~20,-27.

L if D-20.-27.

L if

D~30,-37.

L if D-30,-37.

to Description

00000, - 17777.

NOTE:
So specifies
81 specifies
00 specifies
0 1 specifies

5e
we

6-14

L
L

Signetics Microprocessor Products

Product Specification

Microcontroller

8X305

Table 6. Octal Addresses and Source/Destination Fields for 8X305 Registers
ADDRESS

SOURCE

DESTI·
NATION

ADDRESS

SOURCE

DESTI·
NATION

008

RO (AUX) - General
purpose register

108

R10 (OVF-Overflow
register)

01 8

R1-General purpose
register

118

R11 - General purpose
register

02 8

R2-General purpose
register

128

R12-General purpose
register (Note)

03 8

R3-General purpose
register

13 8

R 13 - General purpose
register (Note)

048

R4-General purpose
register

148

R 14 - General purpose
register

05 8

R5-General purpose
register

158

R15 - General purpose
register

068

R6-General purpose
register

168

R16 - General purpose
register

07 8

R7 - Special purpose
register (refer to next
paragraph)

17a

R17 - Special purpose
register (refer to next
paragraph)

NOTE:
R12 and R13 function as general purpose working registers for all operations except transmit (XMIT). During a transmit instruction where R12 or R13 is the
destination, the a-bit "J" field is immediately transferred to the TV bus; for this operation, the contents of the designated register remain unchanged.

Operations Code Field. The 3-bit OPCODE
field specifies one of eight classes of 8X305
instructions; octal designations for this field
and operands for each instruction class are
shown in Table 5.

DESIGNATES LEFT

Source (S) and Destination (D) Fields. The
5·bit "S" and "D" fields specify the source
and destination, respectively, for whatever
operation is defined by the OPeration CODE.
The "S" andlor "D" fields can specify an
internal 8X305 register or any one-to-eight bit
field within an 1/0 device; octal values and
sourcel destination field assignments for all
internal registers are shown in Table 6.
In instructions where R7a (IVL) or R17a (IVR)
is specified as the destination, the 8-bit value
is output on the iV bus as an 110 device
address or memory location; register R7 selects the Left Bank and register R 17 selects
the Right Bank. The results are also stored
into the specified internal register (R78 or
R178) and may later be accessed as source
data. When the iV bus is specified as a
source and lor destination, the "S" and "D"
fields are split into two parts, that is,
• Source (S) = S1, So and Destination
(D) = D1, Do where,
So specifies the LSB of rotated input
data field
S1 specifies the bank of iV bus from
which source data will be input
Do specifies bit position in 1/0 device
with which LSB of processed data will
be aligned and
D1 specifies the bank of iV bus which
will be the destination.
December 17, 1986

DESIGNATES LSB OF

(2) OROF
RIGHT
(3)~ ~1I0
DATA-REFER
BANK
ill BUS
TO TEXT
DESCRIPTIONS

S,
OR

10111213141518171

ttl

20a

21.
22a
23e
24a
25a
280

278

NOTES:
1. The field length of O-to-8 bits is specified by the "L" field.
2. For the Right Bank, 308 - 378 perform equivalent 110 functions.

RIGHT·ROTATE FUNCTION
2

567

Rotate (R) and Length (L) Field. The 3-bit
R/L field performs one of two functions,
specifying either the field length (L) for I/O
operations or a right-rotate (R) for internal
operations. For a given instruction, the speci·
fied funr.tion depends upon the contents of
the Source (S) and Destination (D) fields.
When an internal register is specified by both
the source and destination fields, the "R"
field is invoked and it specifies a right-rotate

6-"\.5

of the data specified in the "S" field (see
accompanying diagram.) The source-register
data (up to 8 bits) is right-rotated during the
"input phase" of the instruction cycle (Figure
4). This function is always performed prior to
any ALU operation. (Note: The right-rotate
function is implemented on the bus and not in
the source register.)
When either or both of the source and destination fields specify a variable·length I/O

Signetics Microprocessor Products

Product Specification

8X305

Microcontroller

data field, the" L" field specifies the length of
the I/O data field (see following diagram). If
the source field specifies an IV address
(20e - 37 e) and the destination field specifies
an internal register (00e-07e, 11a-17a), the
"L" field specifies the length of source data;
the source data is formed by right-rotating the
IV bus data according to the source address
and then masking result as specified by the
"L" field. If length is less than 8 bits, all
remaining bits are set to zero prior to processing data in the ALU. If the source field
specifies an internal register (OOa - 17a) and
the destination field specifies IV bus data
(20e - 37e), the" L" field specifies the length
of the destination data. To form the destination data, the ALU output is left-shifted according to the destination address and then
masked to the required length (see IV DATA
LENGTH SPECIFICATION). The destination
data is merged with data in the I/O latches to
finalize the IV bus data. Hence, a one-to-eight
bit destination data field can be inserted into
the existing 8-bit I/O port without modifying
surrounding bits. If both the source and destination fields specify IV bus data (20e - 37 a),
the "L" field specifies the length of both the
source and destination data.
To form the source data, the IV bus input data
is right-rotated according to the source address and then masked to the required
length-see IV DATA LENGTH SPECIFICATION. If length is less than 8 bits, all remaining bits are set to zero before processing in
the ALU. To form the destination data, the
ALU output is left-shifted according to the
destination address and masked to the required length specification. The destination
data is then merged into the IV bus data that
was used to obtain the source; thus, if the
source and destination addresses are on the
same bank, the IV bus data written to the
destination I/O Port appears unmodified, except for bits changed during the shift-andmask operations. If the source and destination addresses refer to different banks, the
destination I/O Port is changed to contain the
contents of the source 110 Port in those bit
positions not affected by the destination data.
J Field. The 5-bit or 8-bit "J" field is used to

01234567

IIIIIIII
I
I
I
I
I
I

I
I
I
I
I
I

I
I
I
I
I

I
I
I
I

I I I
I I I<
I I<
I(

~1<------L=1

L=3
L=4

L=5

L=6

I I<

L=7

L=O

IV DATA LENGTH SPECIFICATION
(No Rotate Function Specified)
A Field. The 13-bit "A" field is an address
field which allows the 8X305 to directly
branch to any of the 8192 locations in Program Storage memory.

Formation of Instruction
Address
The Address Register and Program Counter
are used to generate addresses for acceSSing
an instruction from program storage. The
instruction address is formed in one of the
following ways:
• For all except the JMP, XEC, and a
"satisfied" NZT instruction, the Program
Counter is incremented by one and
placed in the Address Register.
• For the JMP instruction, the 13-bit "A"
field contained in the JMP instruction
word replaces the contents of both the
Address Register and the Program
Counter.
• For the XEC instruction, the Address
Register is loaded with bits from the
Program Counter modified as follows:
XEC using IV Bus Data - low-order 5
bits of ALU output replaces counterpart
bits in Address Register.
XEC using Data from Internal Registerlow-order 8 bits of ALU output replaces
counterpart bits in Address Register.

load a literal value (coritained in the instruction) into a register, into a variable I/O data
field, or to modify the low-order bits of the
Program Counter. The bit length of the" J"
field is implied by the "S" and "L" fields in
the XEC, NZT, and XMIT instructions, based
on the following conditions:
• When the Source (S) field specifies an
internal register, the literal value of the
"J" field is an 8-bit binary number.

The Program Counter is not modified for
either of the above conditions.

• When the Source (S) field specifies a
variable I/O data field, the literal value
of the "J" field is a 5-bit binary
number.

The source and/or destination addresses of
the data to be operated upon are specified as
part of the instruction word. As shown earlier,

December 17, 1986

L=2

• For a "satisfied" NZT instruction, the
low-order 5 bits (NZT source is IV bus
data) or low-order 8 bits (NZT source is
an internal register) of both the Address
Register and Program Counter are
loaded with the literal value specified by
the "J" field of instruction word.

Data Addressing

6-16

source/destination addresses are specified
using a 5-bit code (OOa - 37 8), When the most
significant octal digit is a "0" or "1", the
source and/or destination address is an internal register; if the most significant digit is a 2
or 3, an IV bus operation is indicated - 2
specifying a Left-Bank (LB) operation and 3
specifying a Right-Bank (RB) operation. The
least significant octal digit (0 through 7)
indicates either a specific internal register
address or positioning information for the
least significant bit when specifying IV bus
data. Referring to Table 5, AUXiliary register
RO (008) is the implied source of the second
argument for the ADD, AND, and XOR operations. IVL register R7 and IVR register R 17
(destination addresses 078 and 17a, respectively) provide a means of routing enabling
address information to I/O peripherals. With
IVL or IVR specified as the destination address, data is placed on the IV bus during the
output phase of the instruction cycle; simultaneously, a Select Command (SC) is generated to inform all I/O devices that information
on the IV bus is to be considered as an I/O
address. Since the contents of IVL and IVR
are preserved, either register may later be
accessed as a source of data.
Control outputs LB and RB are used to
partition I/O bus devices into two fields of
256 addresses. With LB in the active-low
state and a source address of 20a - 27 a, the
left bank of I/O devices are enabled during
the input phase of the instruction cycle. With
RB in the active-low state and a source
address of 30 a - 37 a, the right bank of devices are enabled. During the output phase,
LB is low if the destination address is 07 a or
20a - 27 a, whereas RB is low if the destination address is 17a or 30 a - 37 a. Each address field (LB and RB) can have a different
I/O device selected, that is, data can be
transferred from a device in one bank to a
device in the other in one instruction cycle.

Signetics Microprocessor Products

Product Specification

8X305

Microcontroller

PARAMETER

aX30S

1I'F. V_CR

:r:-::-.

CONDtTIONS

LIMITS

> 50

hie

VCE:2V;
100mA <

VB EON

VCE=5V; Ie = 500mA < 1V

VCESAT

IC=500mA; IB=50mA < O.SV

< SOOmA

BVCEO

> 15V

> 30MHz

NOTE:
Typical approved parts - 2N5320, 2N5337

Voltage Regulator

DESIGN PARAMETERS

VOLTAGE REGULATOR

Hardware design of an 8X305-based system
largely consists of the following operations:
• Selecting and interfacing a Program
Storage device - ROM, PROM, etc.

All internal logic of the 8X305 is powered by
an on-Chip voltage regulator that requires an
external series-pass transistor. Electrical
specifications for the off-chip power transistor
and a typical hook-up are shown in the
accompanying diagram. To minimize lead
inductance, the transistor should be as close
as possible to the 8X305 package and the
emitter should be AC-grounded via a 0.1 Ilf
ceramic capacitor.

• Selecting and interfacing input! output
devices - RAM, Ports, and other B-bit
addressable I/O devices.
• Choosing and implementing System
Clock - Capacitor-Controlled, CrystalControlled, or Externally-Driven.
• Selection of an off-chip series-pass
transistor.

All information required for easy implementation of these design requirements is provided
under the following captions:
• Ordering Information
• Voltage Regulator
• DC Characteristics
• AC Characteristics
• Timing Considerations
• Clock Considerations
• HALT/RESET Logic

December 17, 1986

6-17

Signetics Microprocessor Products

Product Specification

8X305

Microcontroller

ABSOLUTE MAXIMUM RATINGS Storage Temperature (TsTG) rating are from -65°C to +150 o G
SYMBOL

Vee

DESCRIPTION

RATING

UNIT

+7.0

Vee

Supply voltage

X1, X2

Crystal input voltage

2.0

All other pins

logic input voltage

5.5

DC ELECTRICAL CHARACTERISTICS (Commercial Part) 4.75V';;; Vee';;; 5.25V, OOG';;; TA';;; 70 G
0

LIMITS
SYMBOL

Vee

PARAMETER

TEST CONDITIONS

Supply voltage

UNIT
Typ

Max

4.75

5.25

2
5.5

X1 and X2
All other pins

0.5
0.8

X1 and X2
All other pins

0.9
2

V ,H

High-level input voltage

V,L

Low-level input voltage

VOH

High-level output voltage

Vee =min; IOH = -3mA

VOL

Low-level output voltage

Vee = min; 10L = 6mA
Vee = min; 10L = 16mA

VeR

Regulator voltage

Vie

Input clamp voltage

Vee = min; liN =-10mA

I'H

High-level input current

Vec = max

I,L

Low-level input current

los

Short circuit output current

Ice

Supply current

Vce= max

IREG

Regulator control

Vee = 5.0V

leR

Regulator current

Vce= max

2.4

V
0.55
0.55

Ao through A12
All other outputs

TA = OOG
TA = 70 0 G

-1.5

Grystal inputs X1 and X2
do not have internal
clamp diodes

4
50

mA
p.A

X1 and X2
All other pins

X1 and X2
IVO-IV7
10-115
HALT and RESET

-140

All output pins

180
195

TA = 70 0 G
TA = OOG

-25

Max available base drive
for series-pass transistor

200
230

TA = 70 0 G
TA = OOG

3.1
2.9

Vee = 5V

V,H = 0.9V
V,H = 4.5V

-3
-0.2
-1.6
-0.4

Vee = max; V,L = O.4V

Vee = max; (Note: At any
time, no more than
one output should be
connected to ground.)

-30

-10

NOTES:
1. Operating temperature ranges are guaranteed after thermal equilibrium has been reached.
2. All voltages measured with respect to ground terminal.

December 17, 1986

6-18

COMMENTS

Min

Signetics Microprocessor Products

Product Specification

8X305

Microcontroller

AC ELECTRICAL CHARACTERISTICS

SYMBOL

PARAMETER (NOTE 1)

(Commercial Part) Conditions: 4.75V~Vcc~5.25V; O°C~TA~70°C
Loading: (See test circuits)
LIMITS (INSTRUCTION
CYCLE TIME = 200ns)

LIMITS (INSTRUCTION
CYCLE TIME> 200ns)

Min

Typ

Max

Typ

UNITS

COMMENTS

Max

tpc

Processor cycle time

200

tcp

X1 clock period

100

tCH

X1 clock high time

tCl

X1 clock low time

tMCl

MCLK low delay

MCLK pulse width

T 40 -15

too

Input data to output data

105

tMHS

MCLK falling edge to HALT
falling edge

tMHH

HALT hold time
(MCLK falling edge)

tACC

Program storage access time

t,O

I/O ~ output en~ble time
(LR/RB to val ide IV data input)

tMAS

MCLK falling edge to address
stable

140

t'A

Instruction to address

140

t,VA

Input data to address

tMIS

MCLK falling edge to instruction
stable

TlQ - 25

tMIH

Instruction hold time
(MCLK falling edge)

tMWH

MCLK falling edge to SC/WC
rising edge

105

125

T,o+
T 20 + 5

tMWl

MCLK falling edge to SC/WC
falling edge

tMIBS

MCLK falling edge to LB/RB
(Input phase)

tllBS

Instruction to LB/RB
(Input phase)

tMOBS

MCLK falling edge to LB/RB
(Output phase)

TlQ +
T20 + 15

TlQ +
T20 + 45

Note 2

tMIOS

MCLK falling edge to input data
stable

TlQ +
T 20 - 45

Note 2

tMIDH

Input data hold time
(MCLK falling edge)

115

Note 2

tMOOH

Output data hold time
(MCLK falling edge)

tMooS

Output data stable
(MCLK falling edge)

123

TlQ +
T 20 + 23

toOSM

Output data stable
(MCLK rising edge)

ns
40
T 40

TlQ - 20

Note 2

TlQ +
+ 40

Notes 2, 3, & 4

+ 90

Notes 2, 3 & 5

Notes 3 & 6

Notes 2 & 7

Notes 2 & 8

Note 2

T20

T,o+5

115

145
55

TlQ +
+ 25

T 20

TlQ +
T 20+15

150

t30- 4O

Note 2

T 20

105

TlQ + 15

ns
TlQ +
T 20 + 50

Note 2

NOTES:
1.
2.
3.
4.
5.
6.
7.

X1 and X2 inputs are driven by an external pulse generator with an amplitude of 1.5 volts; all timing parameters are measured at this voltage level.
Respectively, T 1Q, T 20, T30. and T 4Q represent time intervals for the first, second, third, and fourth quarter cycles.
Capacitive loading for the address bus is 150 picofarads.
TMAS is obtained by forcing a valid instruction and an 1/0 bus input to occur earlier than the specified minimum set up time.
TIA is obtained by forcing a valid instruction input to occur earlier than the minimum set up time.
TlvA is obtained by forcing a valid 1/0 bus input to meet the minimum set up time.
TMIS represents the setup time required by internal latches of the 8X305. In system applications, the instruction input may have to be valid before the worst·case
set up time in order for the system to respond with a valid 1/0 bus input that meets the 1/0 bus input set up time (T lDs and T MIDS).
8. TMIH represents the hold time required by internal latches of the 8X305. To generate proper IS/RB signals, the instruction must be held valid until the address
bus changes.

December 17, 1986

6-19

Product Specification

Signetics Microprocessor Procucts

Microcontroller

8X305

AC TEST CIRCUITS
5V

237n

787H
OUTPUT
UNDER TEST

OUTPUT
UNDER TEST

150pF

374U

300pF

169!l

NOTE:
Load capacitance includes Test Jig and Probe Capacitance

TIMING CONSIDERATIONS
(Commercial Part)
As shown in the AC CHARACTERISTICS
table for the commercial part, the minimum
instruction cycle time is 200ns; whereas, the
maximum is determined by the on-chip oscillator frequency and can be any value the user
chooses. With an instruction cycle time of
200ns, the part can be characterized in terms
of absolute values; these are shown in the
first" LIMITS" column of the table. When the
instruction cycle time is greater than 200ns,
certain parameters are cycle-time dependent;
thus, these parameters are specified in terms
of the four quarter cycles (T 10, T2Q, T3Q, and
T4Q) that make up one instruction cyclesee 8X305 TIMING DIAGRAM. As the time
interval for each instruction cycle increases
(becomes greater than 200ns), the delay for

all parameters that are cycle-time dependent
is likewise increased. In some cases, these
delays have a significant impact on timing
relationships and other areas of systems
design; subsequent paragraphs describe
these timing parameters and reliable methods
of calculation.

Condition 1 -

Instruction or MCLK to LB/RB
(input phase) plus I/O port access time (TIO) < fV data setup time (Figure 5a).

Condition 2 -

Program storage access time
(TACC) plus instruction to LS/
RS (input phase) plus I/O port
access time (TIO) plus fV data
(input phase) to address < instruction cycle time (Figure
5b).

Condition 3 -

Program storage access time
plus instruction to address
< instruction cycle time (Figure 5c).

Timing parameters for the 8X305 are normally measured with reference to MCLK.
System determinants for the instruction cycle
time are:
• Propagation delays within the 8X305
• Access time of Program Storage
• Enable time of the I/O port
Normally, the instruction cycle time is constrained by one or more of the following
conditions:

,"
,
,
~
I"'II

,----v.

-a:c'

MClK-.i

SC,WC,lB
orRB

IVO-1V7

I~@:~

'E='"
I
I

I
I

MCLK

I
I

:-0-fi
I
I

AO-A12~!
I

:
151

10-1

LB,RBI

~
\ - i (Ii

1VO- 1V7 r",~
I
I
I
"

NOTES:
CD MCLK to IS/AB (input phase) or instruction to
[BlAB (input phase).
® I/O port access (TIO).
® TV data setup time (referenced to MCLK).

------+--r

10-115

~L-..j

MCLK ----Jj
~'

l~-::'
I~
I
II

::~:

~
:
'

i ! ~i

f-T-CD---I.j

H
!: H
~~

AO-A12

I
I

"~"
I
~
I
I
I::

I
:
I

:INSTRUCTlON:
ITO ADDRESS I

I
I

Program s~a~ access time.
MCLK to LB/RS (input phase) or instruction to

03/R8 (input phase).

!fO port access (TIO).

@ iV data (input phase to address.)

a_ Condition # 1

b_ Condition # 2
Figure 5_ Constraints of 8X305 Instruction Cycle Time

December 17, 1986

6-20

l::

PROGRAM
STORAGE
ACCESS

NOTES:

c. Condition #3

Product Specification

Signetics Microprocesscr Products

8X305

Microcontroller

8X305 TIMING DIAGRAM

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ALU
SOURCE
MUX

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Signetics Microprocessor Products

Product Specification

Microcontroller

8X401

PIN DESCRIPTION
PIN NO.

FUNCTION

IDENTIFIER

1, 17, 47

GND

2-14

A12-AO

NMI

Non-Maskable Interrupt: The falling edge of this active-low input pin generates a nonmaskable interrupt.

INT

Interrupt: This active-low input pin is tested during the fourth quarter of each instruction cycle.
If an interrupt is indicated and if interrupts are enabled, the address of the next instruction that
was to be executed is stored onto the program counter stack before the interrupt is serviced.

18-37

119-10

Bank A: When low, devices connected to bank A are accessed. (Note: Typically, the A signal
is tied to the ME input pin of 1/0 peripherals.)

Bank B: When low, devices connected to bank B are accessed. (Note: Typically, the B signal
is tied to the ME input pin of 1/0 peripherals.)

Bank C: When low, devices connected to bank C are accessed. (Note: Typically, the C signal
is tied to the ME input pin of 1/0 peripherals.)

Select Control: When high, an address is being output on pins DA7 through DAO.

43-46
48-51

DA7-DAO

52,64

Vcc

Ground.
Program Address Lines: These active-high outputs permit direct addressing of up to 8192
locations of program storage; AO is LSB.

Instruction Lines: These active-high input lines receive 20-bit instructions from program
storage; 10 is LSB.

Write Control: When high, data is being output on pins DA7 through DAO.
Data Address Bus: These active-low, bidirectional, three-state lines are used for 1/0; DAO is
LSB.

+ 5V power supply.

MCLK

Master Clock: This active-high output signal is used to strobe data into data peripherals for
clocking 110 devices andlor synchronization of external logic. MCLK is active-high in the fourth
quarter cycle.

RWC

Read/Write Clock: This active-high output signal is used for synchronization of external logic
and is active-high during the third and fourth quarter cycles.

RESET

Reset: The RESET input pin is used to initialize the 8X401.

HALT

Halt: The HALT input is sampled during the first quarter cycle of each instruction cycle. When
the HALT input is low, the instruction cycle is not executed.

SCR

Slow Clock Request: This active-low control input is sampled during the first quarter cycle of
each instruction. When SCR is asserted, it will cause the current instruction to be executed at
half of the normal clock rate. This control input is necessary to accommodate 1/0 devices that
cannot operate at the 8X401's full speed, without having to continuously run ihe 8X401 at half
speed.

Clock Pulse: Each 8X401 quarter cycle will correspond to one full cycle of the clock pulse.

Status Input: The value of the SI pin during the fourth quarter cycle is transferred to SI bit in
the status register.

Programmable Status: The programmable status pin is controlled entirely by the user program.

Non-Zero: The NZ bit of the status register is reflected on this pin.

Interrupt Receivable: The IR pin indicates whether an interrupt applied at any point in time
will be serviced. Interrupts are receivable when the interrupt mask (status register, bit 0) is
clear and the stack is not full (1M = 0 and SF = 0).

Carry: Carry bit from R10 is output on this pin.

December 17, 1986

6-30

Signetics Microprocessor Products

Product Specification

Microcontroller

SMALL SYSTEM
CONFIGURATION
The system hookup shown on the next page,
although of the simplest form, provides a
fundamental example of the 8X401 Microcontroller and compatible peripheral relationships. As shown, the 8X401 can directly
address up to 8K locations of program storage.
Each of the three bank pins (A, B, or C) are
capable of uniquely addressing 256 input!
output locations via the Data Address bus
(DA7-DAO).
The addressable locations for each bank can
be used in a variety of ways. The hookup
shown below is just one method of implementation.
When a particular bank signal is asserted,
that bank is enabled and anyone of 256
locations on that bank can be accessed for
input! output operations.

PROGRAM STORAGE
INTERFACE
As shown in the 8X401 small system hookup,
program memory is connected to output address lines A12 through AO (AO = LS8) and
input instruction lines 119 through 10
(10 = LS8). An address output on AI2-AO
identifies one 20-bit instruction word in program memory. The program memory outputs
an instruction word on 119 -10 which defines
the microcontroller operation which is to follow. One instruction word equals one com-

December 17, 1986

8X401

pleted operation. Any TTL-compatible memory can be used for program storage, provided
the worst-case access time is compatible with
the instruction cycle time used for the application. See timing section for appropriate
calculations.

110 INTERFACE AND CONTROL
The Data Address (DA) bus is an 8-bit bidirectional I/O bus which provides a communication link between the 8X401 and the three
banks of the I/O devices. The A (A bank), B
(8 bank), and C (C bank) control signals
identify which bank is enabled. When all three
banks go high (inactive), neither bank is
enabled and the DA bus is inactive (threestate). A functional analysis of the three bank
signals is shown below:

Low

FUNCTION

This state is not
generated by the
8X401.

Low

High High

Enable A bank
devices.

High

Low High

Enable 8 bank
devices.

High High Low

Enable C bank
devices.

High High High

Disable all devices;
DA bus is threestate

6-31

80th data and I/O address information are
multiplexed on the DA bus. The SC (Select
Command) and WC (Write Command) signals
distinguish between data and I/O address
information as shown in the table below.
Although the table shows bank A only, the
same conditions apply to banks 8 and C.
BANK
A

FUNCTION

High

Low

DA bus is threestate and not
looking for input
data.

Low

The DA bus is
reading input data.

Low

Low High

Data is being
output.

Low

High Low

Address is being
output.

High High

This condition is
never generated.

r
I

Signetics Microprocessor Products

Product Specification

Microcontroller

8X401

SUPPLEMENTARY TIMING SIGNAL

258 ADDIIEIlSAa.E
LOCATlONII

INSTRUCTION ADDRESS

~ INSTRUC110N IMTA

133

DATA. - . AND CONTROL

8X401 Small System Hookup

December 17. 1986

6-32

Signetics Microprocessor Products

Product Specification

Microcontroller

8X401

tion to being general purpose. A summary of
the registers is listed below:
• RO (Auxiliary Register) - Register 0 is
also used as the implied second
operand for two operand instructions
(ADD, ADD with CARRY, XOR, AND).
The primary operand is specified in the
source field of the instruction word and
the AUX register is the implied second
operand. Prior to performing arithmetic
or logical operations (other than the
IMMEDIATE operation), it is assumed
that RO contains the appropriate data.
In order to reduce the possibility of
erroneous results and to minimize the
number of instructions required to
transfer a right-justified second operand

DATA PROCESSING
The data processing section of the BX401
consists of a number of logical subsections.
In order of processing, the data sees the right
rotator, the ALU, the left rotator, and the
merge circuits. Data sources and destinations
can be various on-chip registers, the bidirectional DA bus, or immediate subfields. The
data processing paths are shown below.

DATA REGISTERS

General-Purpose Storage
There are 13 source/destination general-purpose registers available on the BX401. Three
of these registers, specifically Registers 0, B,
and F, have other special functions in addi-

into the AUX, the left-rotate and merge
functions are inhibited when specifying
the AUX as a destination address. This
allows subfields from any internal
register or I/O bank to be transferred
to the AUX with the subfield LSB rightjustified and unspecified bits set to zero.
• R1 through RA - These 10 addresses
specify general-purpose, on-chip storage
registers.
• RB - Register B is also used as the
implied source for the XEC instruction.
• RF - Register F is also used as the
implied destination for the XOR
IMMEDIATE and AND IMMEDIATE
instruction classes.

I Itt 1
I!!Pi

iI!W

GENERAL PURPOSE fIOoR8, RF

ADDRESS REGS RC-RE
CARRY R10

t-~S~TA=IVS~~R~17~----------------~

ALU
SOURCE

MUX

I/O INTERFACE

December 17, 19B6

6-33

Signetics Microprocessor Products

Product Specification

Microcontroller

Enabled 1/0 Addresses
These three registers (RC RD, and RE) always contain the address of the most recently enabled 110 device for each of the three 1/
banks. When register C, 0, or E is the
specified destination address, the destination
data is sent to both the on-chip register and
the corresponding bank on the DA bus. The
relationship between the register addresses
and I/O banks is shown below:

BANK

When these registers are specified as a
destination address, the L field must be set to
o (full 8-bit operation). Also, note that registers C, 0, and E may not be used with the
XMIT 5 or ADD IMMEDIATE 5 instructions.

Carry
Register 10 contains the Carry bit. Bit position
is the Carry bit, and positions one
through seven are always zero. The Carry bit
is updated each time an ADD, ADD IMMEDIATE, or ADD WITH CARRY instruction is
performed. When specifying address 10 as a
destination, only bit 0 (the Carry bit) will be
written to. Data written to the Carry bit will be
the LSB of the right-rotated data after any
specified operation.

o (LSB)

When the Carry register is the explicit destination of any ADD instruction, it will contain
the carry resulting from the add operation
rather than the LSB of the sum. Carry can
also be affected via the Return and Set Carry
or Return and Clear Carry instructions.

Status Register
This address specifies the current condition
of the 8X401 system. The status register may
be either a source or destination; however,
certain bits in the status register are readonly. Four status outputs are available on
8X401 pins. They are NZ (Not Equal to Zero),
PS (Programmable Status), IR (Interrupts Receivable), and Carry (Rl0, bit 0). The IR pin
goes high when the interrupt mask is clear
and the stack is not full. The IR output is
updated during the 4th quarter cycle. The
following descriptions define the bits within
the status register.
Bit 0: (1M) - This bit represents the Interrupt
Mask control. When 1M is set, the interrupt is
inhibited. This bit is set automatically by a
response from a standard or non-niaskable
interrupt, or RESET. 1M can also be set or
cleared by a write to the status register.
Bit 1: (HZ) - This bit is set whenever the
ALU output data is not equal to zero after any
of the following instructions: MOVE, ADD,
AND, XOR, ADD IMMEDIATE, AND IMMEDIATE, XOR IMMEDIATE, or ADD WITH CARDecember 17, 1986

8X401

RY. NZ can also be written to directly when
specified in the destination field. This operation will negate and take priority over the
normal setting by the ALU output. NZ is not
affected after an XMIT instruction, or after a
write to R17.

pressed. This allows byte rotate operations to
be performed. The left-rotate is also suppressed when the destination is register O.
This is the AUX register and is used as the
implied second operand in· certain instructions.

Bit 2: (PS) - This is the Programmable Status bit. The contents are reflected on the PS
output pin. This status is controlled entirely by
the user program.

It should also be noted that subfields are
defined at the ends of a register; for example,
bit positions 1, 0, 7, and 6 constitute a
contiguous 4-bit subfield.

Bits 3 and 4: (UFO, UF1) - These two bits
represent user flags and have no assigned
functions. They can be used as l-bit internal
flags and are entirely under control of the
user program.

Data Field - The data field holds data that
can be processed directly from the instruction
word.

Bit 5: (51) - This bit reflects the state of the
status input pin. This read-only bit is updated
during the 4th quarter cycle.
Bits 6 and 7: (SE, SF) - These read-only bits
indicate Stack Empty and Stack Full, respectively. The bits are updated during the 3rd
quarter cycle within the instruction thaI. alters
the stack status.

INSTRUCTION WORD (See
Table 3)
Operations Code Field - The 4-bit opcode
specifies one of 16 classes of instructions.
Some instructions require two additional subopcode fields, X and XS. Variations and
interpretations are displayed in Table 2.
Source (5) and Destination (D) FieldsThe 5-bit "S" and "D" fields specify the
source and destination, respectively, for the
operation that is defined by the opcode. The
"S"· and/or "D" fields specify an internal
8X401 register or a variable length field from
an 110 device. Hexadecimal values and
source/destination field assignments for all
internal registers are shown in Table 1.
When RC-RE (banks A, B, or C, respectively)
are specified as the destination, the data is
output onto the DA bus using the specified
bank. The data is also stored in the specified
register and may be later accessed as source
data.
Rotate (R) and Length (L) Fields - The R
field is used in conjunction with the L field to
define the desired data within a register or 1/
device. The source data is right-rotated
prior to ALU operations, such that the bit
specified by the R field is right-justified. The L
field specifies the number of bits of data to be
used for the operation. After the ALU operation, the data is left-rotated back to the
original position prior to merging the data in
the destination register.

When the L field specification is 0 Ondicating
a full 8-bit operation), the left-rotate. is sup-

6-34

LEFT-ROTATE OVERRIDE
BLOCK
Register addresses 18-1 F are destination
only and are used to independently control
left rotation of data prior to storage in the
destination. Specifying 18-1 F as a destination
causes the data to be returned to the source
address.
In order to move a processed subfield within
the same register but in different bit positions
(the LSB of the contiguous subfield can vary),
it is necessary to independently specify the
LSB for both the source and destination. The
order of operation is as follows:
• Register or I/O source data is rightrotated as specified by the "R" field.
Along with the "L" field, the subfield
data is defined.
• Subfield data is processed via the ALU.
• Data is left-rotated 0 - 7 bits, depending
on the corresponding register addresses
18-1 F as specified in the destination
field rather than using the "R" field.
• After left-rotation the specified subfield
is merged into those bits of the original
source data. The unspecified bits of the
original source data remain unchanged.
• Result is stored in the register address
specified by the source field.
Note that the left-rotate is always inhibited if
the "L" field is zero. Also, addresses 18-1 F
may not be used in the destination field for
the XMIT or ADD IMMEDIATE instructions.
The destination addresses and corresponding left-rotate values are shown in Table 2.

DA BUS CONTROL BLOCK
Register addresses 11 - 16 are used by the
8X401 to access I/O devices for either a
source or destination specified within the
instruction. Register addresses 13, 15, and
16 specify banks A, B, and C, respectively,
whereas addresses 11, 12, and 14 specify
bank pairs AB, CA, and BC, respectively
(Table 4). One bank of each pair is known as
the preferred bank. The preferred banks for

Signetics Microprocessor Products

Product Specification

Microcontroller

8X401

pairs AB, CA, and BC are banks A, C, and B,
respectively. The first letter from each bank
pair can serve as a mnemonic aid as to which
bank is the preferred bank. Having a preferred bank is simply a method of determining
which bank to read when an instruction would
otherwise indicate that two banks should be
read at once.
When used as a source, the appropriate If a
bank is enabled and data is read from the
activated If device on that bank. The If
device may have been activated by a previous address select instruction where registers C-E were the specified destination. If a
bank pair (addresses 11, 12, or 14) is specified as a source, only data from the preferred
bank of that pair will be read in.

PROGRAM COUNTER STACK

OPCODE

ADD I

S
R1

When addresses 11 - 16 are specified as the
destination and the "L" field is not zero, the
following statements apply: If the source is a
register and the destination is a single bank,
the bank will be read (or the preferred bank of
a bank pair will be read) to obtain the data
required to perform the merge operation. The
result is that processed data from the specified subfield of the source register is returned
to that selected field of the destination bank
and any bits outside of the specified subfield
will be loaded with unprocessed data from the
If device just read. If the destination is a
bank pair, the data from the procedure just
described is sent to both banks. Below is an
example of the outcome of an ADD instruction with Length = 4, Rotate = 2,
Source = R1, and Destination = R11 (bank
pair AB).

R11
Bank Pair

AB
2

R1 I a I

c I

Ie
Specified
Subfield

When addresses 11 - 16 are specified as the
destination address, the destination data is
sent to the DA bus. The Write Control (WC)
signal goes high, indicating data (as opposed
to an address) is on the DA bus and is to be
written to the activated If device on the
selected bank(s).

Example 1:

Source register R1. Note specified

subfield from L ~ 4 and R ~ 2.
R1+ RO I a' I b' I c' I d' I e' I f' I g' I h' I
Add R1 with RO (AUX). Result after
left~rotate.

Bank A I i i i Ikl1lmlnlolp I
Read preferred bank A of AB.

Bank A
Bank B
Result after merge. Data put out

on both banks A and B.
If, however, the specified source is a bank or
bank pair, any unspecified bits will contain
unprocessed data from the source If device. Below is an example of the outcome
with Source = R14 (bank pair BC) and Destination = R13 (bank A).

ADD

R14

Bank B I a I b I c I die I

2
f

I h I

Specified
Subfield
Read Preferred bank B of Be. Note
specified subfield from L = 4 and

R ~2.

Bank B + RO I a' I b' I c' I d' I e' I f' I g' I h' I
Add bank B data with RO (AUX).
Result after left-rotate.

Bank A I a I b I c' I d' I e' I f' I g I h I
Result after merge. Unspecified
bits contain original source data.

December 17, 1986

6-35

Program flow is transferred to address 2 for
the start of the service routine (Figure 2). This
is accomplished by inserting a dummy instruction cycle after the interrupt is accepted.

The Interrupts Receivable (IR) pin indicates
whether an interrupt applied at any point in
time will be serviced. Interrupts are receivable
when the interrupt mask is clear and the
stack is not full (1M = 0 and SF = 0).

BC
7

Interrupt (INT)
The interrupt input is tested once each instruction cycle, during the fourth quarter cycle
(see Figure 1). When the interrupt input is
taken low and is enabled, the address of the
next instruction is pushed onto the program
counter stack.

R13
Bank A

Bank Pair

INTERRUPTS

The interrupt mask bit (R17, bit 0) is set
automatically as part of the interrupt response.

Example 2:
OPCODE

The 8X401 stack is capable of saving up to
four return addresses for subroutines and
interrupts. Addresses are pushed onto the
stack as a result of a call or a maskable or
non-maskable interrupt. Addresses are
popped from the stack as a result of an
unconditional RETURN, a satisfied conditional RETURN, or a Pop Stack and Jump
instruction. The status of the stack (whether
empty, full, or neither) is available from the SE
and SF flags in the status register and the
Interrupts Receivable (IR) output pin.

Non-Maskable Interrupt (NMI)
The function of the non-maskable interrupt is
similar to the standard interrupt, except that
the interrupt receivable status has no effect
on its operation and the address jumped to is
1 rather than 2 (Figure 2). Address 1 should
contain an unconditional JUMP to the start of
the NMI service routine. An NMI is triggered
by a falling edge on the NMI input. The
interrupt mask is set to prevent normal interrupts from interfering with the NMI service
routine. Note that it may not always be
possible to recover from an NMI, since the
condition of the interrupt mask prior to the
NMI is not known, and the NMI response may
overflow the stack.

SLOW CLOCK REQUEST (SCR)
This control input is sampled during the first
quarter cycle of each instruction along with
the instruction data. If the input is low, it will
cause the current instruciion to be executed
at half of the normal clock rate. The purpose
of this function is to facilitate accesses to I/O
devices that cannot operate at the 8X401's

Signetics Microprocessor Products

Product Specification

Microcontroller

full speed, without the need to run the 8X401
continuously at half speed.

8X401

HALT operation. Like MCLK, RWC continues
to operate during a HALT operation.

HALT

RESET LOGIC

The HALT input is sampled during the first
quarter cycle of each instruction. If the HALT
input is low, the instruction cycle is not
executed. The MCLK continues to operate
normally (high every fourth quarter cycle),
even though program execution has ceased.
When the HALT input goes high, program
execution will resume at the next falling edge
of MCLK. The DA bus is also inactive during a

The RESET pin is used to initialize the 8X401.
When RESET is low, the address outputs
(A 12 - AO) are high impedance, the stack
pointer is set to the top of the stack (empty),
MCLK is inhibited, RWC is low, and the
interrupt mask (bit 0, register 17) is se\.
When RESET is released, the address outputs all go low (program address 0). A dummy
instruction cycle occurs to allow time to fetch

the first instruction from program storage at
address O. Only MCLK, RWC, and the address bus are in operation during the dummy
cycle. The first active instruction cycle will
begin following the first MCLK after RESET is
released. The instruction at address 0 should
be an unconditional jump to the beginning of
the main program (which may be proceeded
by a power-up sequence to initialize the
system (Figure 2).
If RESET is applied during program execution, its effect is immediate. That is, if MCLK is
high, it may be prematurely terminated by
RESET.

Table 1_ Hexadecimal Addresses and Source/Destination Specification
S

ADDRESS

RO (AUX) - General Purpose 1

R10 -Carry6

R1 - General Purpose

R11 - Bank Access Command (Bank Pair AB)

R2 - General Purpose

R12 - Bank Access Command (Bank Pair CAl

R3-General Purpose

R13 - Bank Access Command (Bank A)

R4-General Purpose

R14 - Bank Access Command (Bank Pair BC)

R5-General Purpose

R15 -

Bank Access Command (Bank B)

R6-General Purpose

R16 - Bank Access Command (Bank C)

R7-General Purpose

Rl? - Status4

R8-General Purpose

R18 - Suppress Left-Rotate5

R9-General Purpose

R19 - Left-Rotate 1 Place 5

RA - General Purpose

R1A - Left-Rotate 2 Places 5

RB - General Purpose2

R 1B - Left-Rotate 3 Places 5

ADDRESS

DESIGNATION

DESTINATION

RC - Address Reg (Bank A)

R1C - Left-Rotate 4 Places5

RD-Address Reg (Bank B)

R1 0 -

Left-Rotate 5 Places 5

RE - Address Reg (Bank C)

R 1E -

Left-Rotate 6 Places5

RF - General Purpose 3

R 1F -

Left-Rotate 7 Places5

NOTES:
1. Also used as implied second operand for two operand instructions.
2. Also used as implied source for XEC instructions.

3. Also used as implied destination for XOR IMMEDIATE and AND IMMEDIATE instructions.
4. Certain bits in the status register are read-only. (See Status Register within text.)
5. The result is returned to the register address specified by the source field.
6. Carry register, bit 0 is the carry bit. Bits 1 - 7 are always set to zero.

December 17, 1986

6-36

Product Specification

Signetics Microprocessor Products

Microcontroller

8X401

Table 2. Various of Instruction Types
INSTRUCTION
TYPE

VARIATION

OPCODE

DESCRIPTION

MOVE

MOV

0000

ADD

ADD
ADC
AD8
AD5

0001
0101
1000
1001

AND

AND
AN8
AN5

0010
1010
1011

XOR

XOR
XR8
XR5

0011
1100
1101

XEC

0100

EXECUTE

XMIT

XT8
XT5

0110
0111

Transmit IMMEDIATE 8
Transmit IMMEDIATE 5

RETURN

RIF NS
RIF S
RIF NC
RIF C
RIF Z
RIF NZ
PSJ
RTN
RCC
RSC

1110
1110
1110
1110
1110
1110
1110
1110
1110
1110

000
001
010
011
100
101
110
111
111
111

JIF NS
JIF S
JIF NC
JIF C
JIF Z
JIF NZ
JSR
JMP

1111
1111
1111
1111
1111
1111
1111
1111

000
001
010
011
100
101
110
111

JUMP

December 17, 1986

ADD
ADD with CARRY
ADD IMMEDIATE 8
ADD IMMEDIATE 5

AND
AND IMMEDIATE 8
AND IMMEDIATE 5

Exclusive-OR
Exclusive-OR IMMEDIATE 8
Exclusive-OR IMMEDIATE 5

00
10
11

RETURN IF SI = 0
RETURN IF SI = 1
RETURN IF CARRY = 0
RETURN IF CARRY = 1
RETURN IF ALU = 0
RETURN IF ALU 0
POP STACK and JUMP
RETURN
RETURN and CLEAR CARRY
RETURN and SET CARRY

JUMP
JUMP
JUMP
JUMP
JUMP
JUMP
JUMP
JUMP

IF
IF
IF
IF
IF
IF
to

SI =0
SI = 1
CARRY = 0
CARRY = 1
ALU = 0
ALU 0
SUBROUTINE

6-37

Instruction Set Overview: The 8X401 instruction set is summarized in Table 2. Subsets of each instruction type are grouped
together showing the variations of each instruction type. The hardware and software
descriptions can be found in the data operations section.

!....

Signetics Microprocessor Products

Product Specification

Microcontroller

8X401

Table 3. 8X401 Instruction Formats

Table 4. I/O Acess Register

1. Format for the MOVE, ADD, XOR, and ADD with Carry Instructions:
I I I I
I OPCODE

I I I I
SOURCE

INPUT
BANK

OUTPUT
BANK

11
12
13
14
15
16

A
C
A
B
B
C

A&B
C&A
A
B&C
B
C

IDESTINATION
I I I I I

2. Format for the XMIT 8 and ADD Immediate 8 Instruction:
I I I
I I I
I I
I I I I
DATA8
?PCODE
L
DESTINATION

3. Format for the XMIT 5 and ADD Immediate 5 Instruction:
I I I I
I OPCODE

IDESTINATION
I I I I I

I I I
DATA5

4. Format for the AND Immediate 8, and XOR Immediate 8 Instruction:
I I I I
I I I
I I
I ?PCODE
I I I I
DATA8
L
SOURCE
5. Format for the AND Immediate 5 and XOR Immediate 5 Instruction:
I I
I I I I
I I
I I I I
I I I
OPCODE
L
SOURCE
R
DATA5

6. Format for the JUMP, Subroutine Jump, Conditional Jump, and Conditional
Return Instruction:
I I I I
I I I I I I
I OPCODE
X
ADDRESS
7. Format for the Unconditional Return, Return and Set Carry, and Return and Clear
Carry Instruction:
I I I
I I I
I I
OPCODE
X
(UNUSED

8. Format for the XEC Instruction:
I I I I
I OPCODE

I I I I
ADDRESS

I----INPUT PHASE---+---OUTPUT P H A S E - j

I
tst
I
2nd
I
3rd
I
4th-l
I-- QUARTER -I-- QUARTER -I--- QUARTER -I--- QUARTER
INPUT INSTRUCTION, DECODE
INSTRUCTION,
AND IF
REQUIRED,

FETCH NEW
DATA.

GENERATE NEW
ADDRESS FOR
NEXT INSTRUCTION, LATCH AND
PROCESS INPUT
DATA.

PROCESS DATA
THRU ALU, GENERATE SIGNALS,
AND SETUP 110
DATA FOR OUT·
PUT. STACK
OPERATION
(EITHER PUSH,
POP, OR NOP).

LATCI:t 110 ENA·
BLlNG ADDRESS
OR VO DATA IN10

saECTED
PERIPHERALS.
PC UPDATED.

Figure 1. Instruction Cycle and MCLK with: Clock Input = 26.67MHz and Cycle Time

December 17, 1986

6-38

= 150ns

Signetics Microprocessor Products

Product Specification

Microcontroller

8X401

DATA OPERATIONS OF THE 8X401

(See Tables 2 and 3)

MOVE, ADD, AND, XOR, ADD with CARRY
SOURCE
AO

A 17 as specified by

"5" field of instruction.

PRE-ALU

Right rotate as specified
by "R" field of instruction.

POST-ALU

ALU
Perform appropriate ALU
operation. (Note 1)

Left-rotate and mask as
specified by the "R" and
"L" fields of instruction.

DESTINATION
RO - R 17 as specified by
the "Destination" field of
instruction. (Notes 2 & 3)

MOVE, ADD, AND, XOR, ADD with CARRY (Using left-rotate override R18 - R1 F)

,---------,

PRE-ALU

SOURCE
RO - R17 as specified by
"S" field of instruction.

Right-rotate as specified
by "R" field of instruction.

ALU
Perform appropriate ALU
operation. (Note 1)

POST-ALU

DESTINATION
When R18-R1F are
specified in the "D" field,
data is returned to the
address specified in the
"Source" field.

Left-rotate and mask as
specified by the "D" and
"L" fields of instruction.
(Note 4)

XMIT 8 (XT8), ADD IMMMEDIATE 8 (AD8), AND IMMEDIATE 8 (AN8), XOR IMMEDIATE 8 (XR8,..:-)_ _ _ _ _--,
SOURCE
One to eight bit constants
from data field of
instruction and register!
address specified by either
the source or destination
field.

PRE-ALU

NOP.

ALU

POST-ALU

Perform appropriate ALU
operation. (Note 5)

Mask as specified by the
"L" field.

DESTINATION
XT8, AD8: Results are
sent to register! address,
starting from LSB,
specified by the destination
field of the instruction
word.
AN8, XR8: Results are sent
to RF, starting from LSB.

XMIT 5 (XT5), ADD IMMMEDIATE 5 (AD5), AND IMMEDIATE 5 (AN5), XOR IMMEDIATE 5 (XR5)
SOURCE
One to five bit constants
from data field of
instruction and register!
address specified by either
the source or destination.

PRE-ALU
Right-rotate as specified
by "R" field, the data
defined in either the
source or destination field.

ALU
Perform appropriate ALU
operation. (Note 6)

,----------,
DESTINATION

POST-ALU
Left·rotate and mask as
specified by the "R" and
"L" fields.

XT5, AD5: Subfield is
merged into register!
address specified by
destination field. LSB of
data field is sent to bit
position of destination
defined by "A" field.
AN5, XR5: Subfield is
merged into register!
address specified by
source field. The "A" field
specifies the LSB position
of source and RF. Results
are returned to RF.

ALL CONDITIONAL AND UNCONDITIONAL RETURNS
ADDRESS REGISTER (AR)

PROGRAM COUNTER (PC)

STACK

Conditional Returns: If condition is true.
AR = address from top of stack, else load address from
instruction word.
Unconditional Returns: AR = address from top of
stack.

PC~AR.

Conditional Returns: If condition is true.
POP stack, else NOP.
Unconditional Returns: POP stack.

ALL CONDITIONAL JUMPS, POP STACK AND JUMP (PSJ), and JUMP (JMP)
ADDRESS REGISTER
Conditional Jumps: If condition is true.
AR = instruction word address, else AR = PC + 1.
PSJ and JMP: AR = instruction word address.

December 17, 1986

PROGRAM COUNTER
PC=AR.

STACK
Conditional Jumps: NOP.
PSJ: POP stack.
JMP, NOP.

6-39

Signetics Microprocessor Products

Product Specification

Microcontroller

8X401

DATA OPERATIONS OF THE 8X401 (Continued)
CALL (JSR), INTERRUPT (INT), NON-MASKABLE INTERRUPT (NMI)
STACK

ADDRESS REGISTER
JSR: AA .. instruction address.
INT: AR = address 2.
NMI: AR '" address 1.

PUSH PC

+ 1.

(Note 6)

PROGRAM COUNTER
PC~AR.

XEC
ADDRESS REGISTER

PROGRAM COUNTER

STACK

Right-most L bits of RS merged into corresponding bits
in instruction address

PC not updated.

NOP.

NOTES:
1. ALU Descriptions:
MOVE:
• No operation
• Source data ADDed to contents of auxiliary register (RD - AUX). Carry bit set if carry is generated at MSB of selected data field.
ADD:
NZ status bit set jf specified bits are not zero after ALU add.
• Source data ANDed to contents of AUX register. NZ status bit updated accordingly.
AND:
• Source data Exclusive-ORed with contents of AUX register. NZ status bit set accordingly.
XOR:
ADD with CARRY: • Sum is formed from source data. AUX register, and carry bit (register 10, bit 0). Carry and NZ status bits are set when
appropriate.
2. Left-rotate is suppressed when destination is AO (AUX).
3. When address registers Re, AD and RE are specified in the destination, source data will also go out on banks A, B, C, respectively. The L-field
should be zero (a full a-bit operation) to ensure duplication of the two outputs.
4. A left-rotate of 0 - 7 bits will correspond to R18 - R1F as specified in the "Destination" field of instruction word.
5. ALU Descriptions:
XMIT:
• Input constants from the instruction word to specified destination. NZ flag is not updated when an XMIT is performed: however,
NZ can be written to by an XMIT if R17 bit 1 is within the destination field.
ADO IMMEDIATE: • Instruction word data is ADDed to data specified by destination tied. The carry bit is set if a carry is generated at the MSB of
the selected data field. NZ status bit is updated to reflect the value of "L" bits of data atter the addition.
AND IMMEDIATE: • Instruction word data is ANDed to data specified by source field. Returning the destination data to RF allows the operation to
be performed without destroying the original data field. This will facilitate testing of data for certain pre~defined values while still
preserving the original data for other uses. NZ status bit updated accordingly. Unspecified bits in RF remain unchanged.
XOR IMMEDIATE: • Sarne as AND IMMEDIATE, except the logical operation performed is Exclusive-OR.
6. Note that the stack operation IS show before the PC in the CALL and INTERRUPT formats. This is because the stack is actually in operation in
cycle 3, and the PC is updated in cycle 4 (see Figure 1). In fact, for the Call (JSR) instruction and interrupt servicing, cycle order is important for
the user to understand the current status of the PC. The other instructions are in reverse order for visual simplicity in keeping with block diagram
flow, and cycle order is irrelevant.

RESET VECTOR

•

The RESET VECTOR. LOCATED AT ADDRESS 0, WILL BE
AN UNCONDmONAL JUUP TO THE BEGINNING OF THE
UAlN PROGRAU.

•

THE NON-UASKABLE INTERRUPT (NUI~ VECTOR,
LOCATED AT ADORESS 1, IS A JUUP TO THE NUl SERV.
SERVICE ROUTINE.

•

LOCATED AT ADDRESS 2 IS THE ROUTINE THAT
SERVICES INTERRUPT (INT) CALLS.

NUl VECTOR
INTERRUPT
SERVICE ROUTINE

NIII SERVICE
ROUTlN~

MAIN

PIIOGIIAII

Figure 2. Typical 8X401 System Memory Map

December 17, 1986

6-40

Product Specification

Signetics Microprocessor Products

8X401

Microcontroller

Thermal Junction Temperature
vs Airflow

31
30

The ceramic package used for the 8X401 has
no heat sink and a 8ia rating of 30.5°C/W in
still air. Currently, to ensure operation at
150ns, the junction temperature of the devices must be kept below 115°C. The maximum power dissipation at that junction temperature will be 2.4W so that airflow will be
required for full commercial range operation.
The 0ja versus Airflow curve is drawn here:

29
28
27
26
25

'10

2.
23
22
21
20
19
18

100

200

300

400

500

600

700

800

AIRFLOW (UNEAR FEET PER MINUTE)

DC ELECTRICAL CHARACTERISTICS

Commercial Part 4.75V';;; Vcc';;; 5.25V, O°C';;; TA ,;;; 70°C'
LIMITS

PARAMETER

SYMBOL
Vee

Supply voltage

VIH

High-level input voltage

Vil

Low-level input voltage

VOH

High-level output voltage

VOL

TEST CONDITIONS

UNIT
Min

Typ

Max

4.75

5.25

0.8

COMMENTS

Vee = Min, 10H = -3mA

2.4

DAO through DA7, MCLK,
SC, WC, AB, BB, CB

Vee = Min, 10H = -4OOI1A

2.4

All others

Vee = Min, 10l = 16mA

0.5

DAO through DA7, MCLK,
RWC, SC, WC, A, S, C

Vee = Min, 10l = 8mA

0.5

AO through A 12, PS, NZ,
CY,IR

Low-level output voltage

Vie

Input clamp voltage

Vee = Min, liN = -10mA

-1.5

IIH

High-level input current

Vee = Max, VI = 2.7

I1A

III

Low-level input current

Vee = Max, VI = O.4V

-400

I.lA

10ZH

Off-state output current,
high-level voltage applied

Vee = Max, Vo = 2.7V

I1A

DAO through DA7

10Zl

Off-state output current
low-level voltage applied

Vee = Max, Vo = O.4V

-400

I1A

DAO through DA7

los

Short circuit output current 2

Vee = Max, Vo = OV

-140

500

TA = O°C; Cold start 3

Icc

Supply Current

430

TJ=115°C

Vee = Max

-30

NOTES:

1. 64-pin CDIP, airflow required for commercial operation. (The plastic 64-pin DIP with internal heatsink does not have this requirement.)
See above for thermal characteristics.

2. Not more than one output should be tested at a time.
3. Guaranteed by operation to Icc measured at 25°C.

December 17, 1986

6-41

Signetics Microprocessor Products

Product Specification

M icrocontroller

AC ELECTRICAL CHARACTERISTICS

8X401

(Vcc=5V +5%, 0°C";;TA ";;70°C)1

> 150n5

150n5 CYCLE
SYMBOL

CYCLE

PARAMETER

UNIT
Min

Typ

Max

Min

Typ

tpc

Processor cycle time

150

tcp

Clock pulse period

37.5

tCH

Clock pulse high time

tCl

Clock pulse low time

tMCl

CPl to MCLK low

tMCH

CP4 to MCLK high

MCLK pulse width

tRWCl

CPl to RWC low

tRWCH

CP3 to RWC high

T40 -12

T40

tRWCW

RWC pulse width

tAS

CP2 to address stable

tMAS

MCLK to address stable

tiS

Instruction setup to CPl

tMIS

Instruction setup to MCLK

tlH

Instruction hold from CP2

tMIH

Instruction hold from MLCK

tSCH

CP3 to SC rising edge

tMscH

MCLK to SC rising edge

tWCH

CP3 to WC rising edge

tMWCH

MCLK to WC rising edge

105

See Note 2

ns
ns

T30 +T40
-10

T30 + T40
+5

ns
ns

Tl0 + 24

ns
See Note 3

ns
ns

Tl0-12

ns
Tl0 + T20
+20

ns
ns

Tl0 +T20
+20

ns
ns

tWl

CPl to SC/WC falling edge

tMWl

MCLK to SC/WC falling edge

tlBSl

CPl to input phase bank signal
falling edge

tMIBSl

MCLK to input phase bank signal
falling edge

tlBSH

CP3 to input phase bank signal
rising edge

tMIBSH

MCLK to input phase bank signal
rising edge

tOBSl

CP3 to output phase bank signal
falling edge

tMOBSl

MCLK to output phase bank signal
falling edge

105

tOBSH

CPl to output phase bank signal
rising edge

tMOBSH

MCLK to output phase bank signal
rising edge

tlDS

Input data setup to CP3

ns
Tl0+ T20
+ 20

ns
ns

Tl0 +T20
+30

-3

ns
25 - T10
-T20

tMIDS

Input data setup to MCLK

-50

tlDH

Input data hold from CP3

tMIDH

Input data hold from MCLK

toDH

Output data hold from CPl

tMODH

Output data hold from MCLK

December 17, 1986

See Note 2

40
65

COMMENTS

Max

ns
ns

T10 +T20
+3

6-42

See Note 4

Signetics Microprocessor Products

Product Specification

Microcontroller

8X401
I
[

I
!

AC ELECTRICAL CHARACTERISTICS (Continued)

> 150ns

150ns CYCLE
SYMBOL

PARAMETER
Min

taos

Typ

CP3 to output data stable

Max

Min

1CYCLE

Typ

UNIT

COMMENTS

Max

ns
T1Q+T2Q
+45

tMOOS

MCLK to output data stable

120

tOI

SC/WC rising edge to output driver
turn on

tHS

Halt setup to CP2

tMHS

Halt setup to MCLK

-10

tHH

Halt hold from CP2

tMHH

Halt hold from MCLK

tSIS

Status input setup to CP1

ns
T1Q + 22

ns
ns

tMSIS

Status input setup to MCLK

tglH

Status input hold from CP1

tMSIH

Status input hold from MCLK

tscRS

SCR setup to CP1

tMSCRS

SCR setup to MCLK

tSCRH

SCR hold from CP2 (Slow CP2)

See Diagram
for CP2

Slow T1Q

tMSCRH

SCR hold from MCLK

tiNTS

INT setup to CP1

ST1Q-12

tMINTS

INT setup to MCLK

tlNTH

INT hold from CP1

tMINTH

INT hold from MCLK

leyU

CP4 to CY update

tMCYU

MCLK to CY update

tNZU

CP4 to NZ update

tMNZU

MCLK to NZ update

-5

tlRU

CP4 to IR update

tMIRU

MCLK to IR update

tpsu

CP4 to PS update

tMPSU

MCLK to PS update

tACC

Program memory access time
(address stable to valid instruction)

tlO

I/O port output enable time
(bank signal to valid data on bus)

tRW

Reset pulse width

150

tNMIW

NMI pulse width

tNMIS

NMI setup to CP2

See Note 5

tMNMIS

NMI setup to MCLK

See Note 5

-10

ns
60

-10

28-T4Q

ns
ns

33-T4Q

58-T4Q

-10

28-T4Q

T2Q+T3Q
+ T4Q-52

ns
T1Q+T2Q
-51

24
tpc

ns
ns
ns

NOTES:

1. Inputs swing between OV and 3V. All outputs are measured at 1.5V with loading as specified in the test circuits.
2. CP1, CP2, CP3, and CP4 refer to the clock pulse that causes the first. second, third, and fourth 8X401 quarter cycles, respectively. Parameters
referenced to MCLI<, CP1, CP2, CP3, and CP4 are measured to the falling edge of those signals. Tl Q, T2Q, T3Q, and T4Q represent time intervals
for the first, second, third, and fourth 8X401 quarter cycles. respectively. Duty cycle can be from 40% to 80%.
3. Instructions must be setup before CPl.
4. tWL represents IscL and tWCL' iMWL represents tMSCL and tMWCL·
5. This guarantees NMI is serviced in the current cycle.

December 17, 1986

6-43

Signetics Microprocessor Products

Product Specification

Microcontroller

8X401

TEST CIRCUIT
VL=2.1V

VL=2.3

OUTPUT
UNDER
TEST

2260
OUTPUT
UNDER
TEST

'000

~'OOPF

~50PF
TC11240S

MAIN TIMING DIAGRAM
CP1

CP2

CP3

CP4

CP1

CPa

CP4

CP1

CPa

CP3

CP4

CP1

CPa

IICLK

---+J

AWe
I

I
ADDRESS
(A12-AO) _ _ _ _ _ _ _ _

1ou.s-l

'--------...JI'----o:----.~-

'-__.....____

INSTRUCTION

(119-10) " "........... . ,

--------+-~--~
tMWCL

~~ --------~-~----<'_~_A_~_~_J

,
ii

THE 3 CYCLES REPRESENT THE FOUOWING INSTRUCTIONS:

- - . r IIIIIEDIATE ADDRESS 10 BANK B (SELECT A PORT ON BANK B)
-IIOI/E BANK A DATA 10 BANK B
- ADD _ T E DATA 10 BANK A

""",,'"

December 17, 1986

6-44

Signetics Microprocessor Products

Product Specification

Microcontroller

8X401

TIMING SUPPLEMENT: STATUS
CP3

CP2

CP4

CP1

CP2

CP3

CP1

CP2

CP4

CP3

CP2

CP1

MCLK

~~§

~IsH ~"'~H

I-t"su-

I - typsu

}

I - tyNZU :

! - - tNZU -

1-~~1 I-- tllC~
CY

I-~RUj ~""RU
IR

TIMING SUPPLEMENT: RESET
CP1

MCLK
RESET
ASSERTED

AWC

---1

CP2

CP3

CP4

" '---'

RESET

ADDRESS

CP1

1_~1

_'\1

c.-----

tRW

)
CP1

CP2

CP3

CP4

CP1

CP2

CP3

CP4

CP1

f-:~~=~TRUCTION-I
MCLK
RESET
RELEASED

AWC

RESET

ADDRESS

December 17, 1986

"--\

'---

ADDRESS

6-45

)(

Signetics Microprocessor Products

Product Specification

Microcontroller

8X401

TIMING SUPPLEMENT: HALT
CPl

CP2

CP3

CP4

CPl

CP2

CPl

CP4

CP3

CP2

CP3

CPl

CP4

MCLK

I I

RWC--i

tHS-j

HALT

SCORWC

~tMHH~

'--

\..-

I-tHH

r---------""\

DA BUS

A.B.ORC

~~HS

-l

"--

(

)(

TIMING SUPPLEMENT: INT
CP2

CP3

CP4

CPl

CP2

CP3

CP4

CPl

CP2

CP3

CP4

CPl

MCLK

________~__-L______________________________________________________________

ADDRESS

ADDRESS OF INSTRUCTION NOT
EXECUTED DUE TO INTERRUPT.

December 17. 1986

ADDRESS =

0002,.

\~--------------------------------------

6-46

Product Specification

Signetics Microprocessor Products

8X401

M icrocontroller

,..

TIMING SUPPLEMENT: NMI

CPl

CP2

CP3

CP4

CPl

CP3

CP4

CPl

CP2

CP3

CP4

CPl

ADDRESS =

0001,.

UCLK

NMi

t,.1IIW--j
* E S S OF INSTRUCTION

ADORESS

l1TED DUE TO NUl.

H!li)(

TIMING SUPPLEMENT: seR
CPl

CP2

CP3

CP4

CPl

CP2

CP3

CP4

CPl

i:.Jrl,..1--;.:_______--J,r-------.'I--_ _ _" " - - -

UCLK _ _ _

~I ~+---...JI

fMC.!
5

:
l_ _
I~RS
11+-!seR:
!seRS 'I
IUSCR"
_ _ _ _ _ _ .'1
,;__

-_-_-_--_-_-_-J-r---TC-_-_-_-_-J-,-------

X~________~X~_________x=

ADDRESS

SCORWC---,

DABUS

A.B.ORC~

December 17. 1986

\~-------------------

(

(~-----)~-------------

)
I

_________JI

6-47

SCN8049 Series

Signetics

SCN8049, SCN8050, SCN8039,
SCN8040 Single-Chip 8-Bit
M icrocontroller
Microprocessor Products

Product Specification

DESCRIPTION

FEATURES

The Signetics SCN8049 Series microcontrollers are self-contained, 8-bit processors which contain the system timing, control logic, RAM data memory,
ROM program memory (8048/49/50
only), and 1/0 lines necessary to implement dedicated control functions. All
SCN8049 Series devices are pin and
program compatible, differing only in the
size of the on-board program ROM and
data RAM, as follows:

• a-bit CPU, ROM, RAM, 1/0 in a
40-pin package
• 24 quasi bidirectional 1/0 lines
• Two test inputs
• Internal counterltimer
• Single-level vectored Interrupts:
external, counterltimer
• Over 90 instructions, 70% single
byte
• 1.3611S or 2.5!lS instruction cycle,
all instructions one or two cycles
• Expandable memory and 1/0
• Low voltage standby
• TTL compatible inputs and
outputs

TYPE

SCN8049
SCN8050
SCN8039
SCN8040

RAM SIZE

128
256
128
256

X
X
X
X

8
8
8
8

ROM SIZE

2K x 8
4K X 8

Program memory can be expanded externally up to a maximum total of 4K
bytes without paging. Data memory can
also be expanded externally. 110 capabilities can be expanded using standard
devices or the 8243 1/0 expander.
The SCN8049 Series processors are
designed to be efficient control processors as well as arithmetic processors.
They provide an instruction set which
allows the user to directly set and reset
individual lines within its 110 ports as
well as test individual bits within the
accumulator. A large variety of branch
and table look-up instructions make
these processors very efficient in implementing standard logic functions. Also,
special attention has been given to code
efficiency. Over 70% of the instructions
are a single byte long and all others are
only 2 bytes long.

PIN CONFIGURATIONS

P25
P24
P17

P16
P15
P14
P13

DBO

P12

DB2

Pl0

P11

DB3

LOGIC SYMBOL

XTAL

Tl
P27

• Single + 5V power supply

DB4

PROG

DBS

P23

DB6

P22

DB7

P21

Vss

P20

PORT

INDEX
CORNER

PORT

RESET ........

SINGLE
STEP EXTERNAL
MEM-

TEST

PLCC

29
18

28
TOP VIEW

INTERRUPT ........

CD0044PS

PI"
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

BUS

An on-chip 8-bit counter is provided
which can count, under program control,
either internal clock pulses (with a divide
by 32 prescaler) or external events. The
counter can be programmed to cause an
interrupt on terminal count.

August 26, 1986

XTAL1

6-48

Function
NC
TO
XTALl
XTAL2
RESET

INT
EA

l'iil
j5SEfii

WI!
NC
ALE
DBO
081
DB2
083
084
085
086
087

Vss

PI"
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44

Function
NC
P20
P21
P22
P23
PRoo
VDD
Pl0
P11
P12
P13
NC
P14
P15
P16
P17
P24
P25
P26
P27
Tl
Vee

853-0095 85292

Signetics Microprocessor Products

Product Specification

SCN8049, SCN8050, SCN8039, SCN8040
Single-Chip 8-Bit Microcontroller
ORDERING INFORMATION

SCN8049 Series

J 1[

SCN8000 HoODOO (CPxxxx)

ROM/RAM (bytes)
35 = EXT /64
48 = 1K/64
39 = EXT/128
49 = 2K/128
40 = EXT /256
50 = 4K/256

CUSTOM RO" PAnE'N NUMBER

OPERATING TEMPERATURE RANGE
A = -40°C to + 85°C
C = O°C to +70°C
SPEED - - - - - '

B = 11MHz clock
6 = 6MHz clock

40
44

Applies to masked ROM versions only.
Number will be assigned by Signetics.
Contact Signetics sales office for ROM
pattern submission requirements.

= Pin
= Pin

DIP
LCC

' - - - - - - PACKAGE
N = Plastic 01 P
I = Ceramic DIP
A = Plastic lCC

PIN DESCRIPTION
PIN NO.
TYPE

MNEMONIC

NAME AND FUNCTION

DIP

PLCC

Vss

VDD

low power standby.

Vee

Main Power Supply: + 5V during operation.

PROG

Circuit ground potential.

Output strobe for 8243 I/O expander.

P10 - P17

27 -34 30 - 33,
35-38

I/O

Port 1: 8·bit quasi·bidirectional port.

P20 - P27

21-24, 24 - 27,
35-38 39-42

I/O

Port 2: 8·bit quasi·bidirectional port. P20·23 contain the four high·order program counter bits
during an ex1ernal program memory fetch and serve as a 4·bit I/O expander bus for 8243.

DBO-DB7

12 -19 14- 21

I/O

Data Bus: True bidirectional port which can be written or read synchronously using the RD,
WR strobes. The port can also be statically latched. Contains the eight low·order program
counter bits during an ex1ernal program memory fetch and receives the addressed instruction
under the control of PSEN. Also contains the address and data during an external RAM data
store instruction, under control of ALE, RD and WR.

Input pin testable using the conditional transfer instructions JTO and JNTO. TO and be
designated as a clock output using the ENTO ClK instruction.

Input pin testable using the JT1 and JNT1 instructions. Can be designated the timer/counter
input using the STRT CNT instruction.

XTAl1

Crystal 1: One side of the crystal input for internal oscillator. Also input for external source
(non-TTL VIH).

XTAl2

Crystal 2: Other side of crystal input.

INT

Interrupt: Initiates an interrupt if interrupt is enabled. Interrupt is disabled aiter a reset. Also
testable with conditional jump instruction. Interrupt must remain low for at least three machine
cycles for proper operation.

RESET

Reset: Used to initialize the microcomputer. Active low. Internal pullup -75Kr!. During
program verification the address is latched by a "0" to "1" transition on RESET and the
data at the addressed location is output on BUS.

Read: Output strobe activated during a bus read. Can be used to enable data onto the bus
from an ex1ernal device. Used as a read strobe to ex1ernal data memory.

Write: Output strobe during a bus write. Used as write strobe to ex1ernal data memory.

ALE

Address Latch Enable: Occurs once during each cycle and is useful as a clock output. The
negative edge of ALE strobes address into ex1ernal data and program memory.

PSEN

Single Step: Can be used in conjunction with ALE to "single step" the processor through
each instruction.

External Access: Forces all program memory fetches to reference ex1ernal memory. Useful
for emulation and debug, and essential for testing and program verification.

Program Store Enable: Output occurs only during a fetch to ex1ernal program memory.

NOTE:
Each pin on these ports can be assigned, under program control, to be an input or an output. A pin is deSignated as an input by writing a logic" 1" to the pin. RESET
sets all pins to the input mode. Each pin has an internal pullup of approximately SOkn.
August 26, 1986

6-49

Signetics Microprocessor Products

Product Specification

SCN8049, SCN8050, SCN8039, SCN8040
Single-Chip 8-Bit Microcontroller

SCN8049 Series

FUNCTIONAL DESCRIPTION
The following is a general functional description of the SCNB049 Series microcomputers. Refer to the block diagram below.

BLOCK DIAGRAM

P!"

RESIDENT

ROM
(8048149150 ONLy)

PQRTl
8US

r--------,~----~__----~~----~~----~~----------~--~ B~:~R
LATCH

AEGISTEA2
REGISTER 3
REGISTER ..

B
DD

- . RAM SUPPLY

POWER
SUPPLY

v~ +5V MAIN SUPPLY

!!..OND

(VARIABLE LENGTH)
OPTIONAL SECOND
REGISTER BANK

DATA STORE

RESIDENT

RAM ARRAY
TIMING
OUTPUT

INTERRUPT

INITIALIZE

EXPANDER
STROBE

CPU
OSCILLATOR
PROGRAM SINGLE READlWRITE
MEMORY
XTAL
MEMORY
STEP
STROBES
ENABLE
SEPARATE
ADDRESS

LATCH
ENABLE

August 26, 19B6

P,O

Signetics Microprocessor Products

Product Specification

SCN8049, SCN8050, SCN8039, SCN8040
Single-Chip 8-Bit Microcontroller
PROGRAM MEMORY
Resident program memory consists of up to
4K bytes of ROM. The program memory is
divided into pages of 256 bytes each. As
shown in the memory map, Figure 1, program
memory is also divided into two 2046-byte
banks, MBO and MB1. A total of 4096 bytes
can be addressed directly. If more memory is
required, an I/O port can be used to address
locations over 4095.
There are three locations in program memory
of special importance. These locations contain the first instruction to be executed upon
the occurrence of one of three events.
LOCATION

EVENT

Activation then deactivation
of the "FfEm line.
Activation of the liiIf line
when the external interrupt
is enabled.
An overflow of the timer/
counter if the T /C interrupt
is enabled.

DATA MEMORY
Resident data. memory, as shown in Figure 2,
consists of up to 256 bytes of RAM. All

locations are indirectly addressable by either
of two RAM pointer registers at locations 0
and 1. The first eight locations of RAM (0-7)
are designated as working registers and are
directly addressable by several instructions.
By selecting register bank 1, RAM locations
24-31 become the working registers, replacing those in register bank 0 (0-7).
RAM locations 6-23 are designated as the
stack. Two locations (bytes) are used per
CALL, allowing nesting of up to eight subroutines.
If additional RAM is required, up to 256 bytes
may be added and addressed directly using
the MOVX instructions. If more RAM is required an I/O port can be used to select one
(256-byte) bank of external memory at a time.

PROGRAM COUNTER AND
STACK
The Program Counter (PC) is a 12-bit counter/register that points to the location from
which the next instruction is to be fetched.
The 6046 and 6049 will automatically address
external memory when the boundary of their
internal memory is exceeded. All processors
access external memory if EA is high.

-D

128
127

64
63

SELMBO

32
31

'-B

1023

:;:

~
0

i
z

I--

LOCATION 7 - TIMER
INTERRUPT VECTORS
PROGRAM HERE

I--

LOCATION 3- EXTERNAL
INTERRUPT VECTORS
PROGRAM HERE

'--

8
7
6
5

:;:
1./
z

'--

24
23

:;:
9

3
2
1
,-0

716151413121110 _

The end of a subroutine, which is Signalled by
a return instruction (RET or RETR), causes
the stack pointer to be decremented and the
contents of the resulting register pair to be
transferred to the program counter.

8040/8050
USER RAM
128)(8
8039/8049
USER RAM
64K8
8035/8046
USER RAM
32)(8
BANK 1
WORKING
REGISTERS
&x8
f----ii1:----

f----iio:---8 LEVEL STACK
'OR
USER RAM
16)(8

BANKO
WORKING
REGISTERS"
&x8

___ !!1 ___
1--------

~:~~TR~~C~~=~

ADDRESS

p""""",
Figure 1. Program Memory Map

August 26, 1966

An interrupt or CALL to a subroutine causes
the contents of the program counter to be
stored in one of the 6 register pairs of the
program counter stack. The pair to be used is
determined by a 3-bit stack pointer which is
part of the Program Status Word (PSW). Data
RAM locations 6 through 23 are available as
stack registers and are used to store the
program counter and 4 bits of PSW. The
stack pointer, when initialized to 000, points
to RAM locations 6 and 9. The first subroutine
jump or interrupt results in the program counter contents being transferred to locations 6
and 9 of the RAM array. The stack pointer is
then incremented by one to point to locations
10 and 11 in anticipation of another CALL.
Nesting of subroutines within subroutines can
continue up to eight times without overflowing
the stack. If overflow does occur the deepest
address stored (location 6 and 9) will be
overwritten and lost since the stack pointer
overflows from 111 to 000. It also underflows
from 000 to 111.

255

-B'~-

r---2047

SCN8049 Series

~
DIRECTLY
ADDRESSABLE
WHEN BANK 1
IS SELECTED

ADDRESSED
INDIRECT LY
THROUG H
R1 OR RO
(RO' OR R1')

~
DIRECTLY
ADDRESSABLE
WHEN BANKO
ISSELErTED

PFOO'' '
Figure 2. Data Memory Map

6-51

Signetics Microprocessor Products

Product Specification

SCN8049, SCN8050, SCN8039, SCN8040
Single-Chip 8-Bit Microcontroller

SCN8049 Series

OSCILLATOR AND CLOCK
The processor contains its own internal oscillator and clock driver. A crystal, inductor, or
external pulse generator may be used to
determine the oscillator frequency (see Figure 3). The output of the oscillator is divided
by three and can be output on the TO pin by
executing the ENTO ClK instruction. This
ClK signal is divided by 5 to define a machine
(instruction) cycle. It is available on Pin 11 as
ALE.

+5V

INTERNAL
BUs-+--t D
D
FLIP
FLOP

...-.......=:'1XTALI
CLK

XTAL2
c= 15-25pF
(INCLUDES SOCKET,
STRAY)

SERIES RESONANT, AT CUT CRYSTAL
IN

DRIVING
FROM EXTERNAL
SOURCE

Figure 4_ "Quasi Bidirectional" Port

+5V

470'l
Jo-. For testing, all input signals swing between 0.4V and 2.4V with a transition time of 20ns maximum. All
time measurements are referenced at input voltages of 0.8V and 2.0V and output voltages 0.8V and 2.0V as appropriate.
6. Typical values are at + 25·C, typical ssupply voltages and typical processing parameters.
7. Control outputs: CL - 80pF
Bus outputs: CL = 150pF
Icv = 1.36jlS for 11 MHz versions
lev = 2.5jlS for 6 MHz versions
S. Where no specification is shown, the commercial temperature range specification applies.

1.2
u

1.1

+
0
.g 1.0

"'-

III
N

:J
c 0.9
lIE
a:
0

"'- ~

o.a
0.7

-25

100

TEMPERATURE, ·C

VI.

NORMALIZED TOTAL
SUPPLY CURRENT
TEMPERATURE (TYPICAL)

August 26, 1986

6-55

Signetlcs Microprocessor Products

Product Specification

SCN8049, SCN8050, SCN8039, SCN8040
Single-Chip 8-Bit Microcontroller

SCN8049 Series

TIMING DIAGRAMS

-------t
I-tLL-!

cv- - - - - - .I

ALE

Figure 7. Instruction Fetch From External Program Memory

ALE

BUS

\'------

FLOATING

Figure 8. Read From External Data Memory

ALE

BUS

\'-------

FLOATING

Figure 9. Write to External Data Memory

August 26, 1986

6-56

Signetics Microprocessor Products

Product Specification

SCN8049, SCN8050, SCN8039, SCN8040
Single-Chip 8-Bit Microcontroller

SCN8049 Series

TIMING DIAGRAMS (Continued)

ALE

~ ~ICA
rIDP-H-IPD

,..----""\.

EXPANDER
PORT
OUTPUT

PCH

EXPANDER
PORT
INPUT

PCH

OUTPUT DATA

Ipp

I
-1
_____r-

1......-. _ _

PROG

Figure 10. Port 2 Timing

ICy

I
J

INPUT
INST.

DECODE

OUTPUT ADDRESS

EXECUTION

INC. PC

INPUT

OUTPUT ADDRESS

Figure 11. Instruction Cycle

CLOCK OUT
ON TO
ALE

_1-_-+__-1--'

RD--I---+---I---~--+-.,
WR

L-~--4--~

PROG

Figure 12. Instruction Cycle Timing

August 26, 1986

6-57

Signetics Microprocessor Products

Product Specification

SCN8049, SCN8050, SCN8039, SCN8040
Single-Chip 8-Bit Microcontroller

SCN8049 Series

Table 1 Instruction Set
INSTRUCTION CODE
MNEMONIC

FUNCTION

CYCLES

DESCRIPTION

FLAGS
BYTES

D-,DsDsD.D3 DID1 DO

Accumulator

ADD A,

data

ADD A, Rr
ADD A,

ADDC A,

data

ANL A,

data

ANL A, Rr

ANL A,

(A)
for
(A)
for

<- (A) + (Rr)
r=0-7
<- (A) + «Rr))
r=O-1

(A) <- (A) + (C) + data
(A) <- (A) + (C) + (Rr)
for r=0-7

ADDC A, Rr

ADDC A,

(A) <- (A) + data

(A) <- (A) + (C) + «Rr))
for r=O-1
(A) <- (A) AND data
(A) <- (A) AND (Rr)
for r-0-7

CPL A

(A) <- (A) AND «Rr))
for r=O-1
(A) <- NOT (A)

CLR A

(A) <- 0

DA A
(A) <- (A)-1

DEC A

(A) <- (A) + 1

INC A
ORL A,

data

ORL A, Rr
ORL A,

RL A

RLC A

RR A

RRC A

&NAPA
XRL A,

# data

(A) <- (A) OR data
(A) <- (A) OR (Rr)
forr-0-7
(A) <- (A) OR «Rr))
for r-O-l
(An + 1) <- (An)
(Ao) <- (A7)
forN-0<-6
(An + 1) <- (An);
n-0-6
(Ao) <- (C)
(C) <- (A7)
(An) <- (An + 1);
n-0-6
(A7) <- (Ao)
(An) <- (An + 1);
n-0-6
(A7) <- (C)
(C) <- (Ao)
(~7) <- (Ao - 3)
(A) <- (A) XOR data

XRL A, Rr

(A) <- (A) XOR (Rr)
for r-0-7

XRL A, @ Rr

(A) <- (A) XOR «Rr))
for r-O-l

August 26, 1986

Add immadiate the specified data
to the accumulator.
Add contenta of designated
register to the accumulator.
Add indirect the contenta the data
memory location to the
accumulator.
Add immediate with carry the
specified data to the accumulator.
Add with carry the oontents of the
designated register to the
accumulator.
Add indirect with carry the
oontenta of data memory location
to the accumulator.
Logical AND specifiad immediate
data with accumulator.
Logical AND oontenta of
designated register with
accumulator.
Logical AND indirect the oontents
of data memory with accumulator.
Complement the oontenta of the
accumulator.
Clear the oontenta of the
accumulator.
Decimal adjust the oontenta of the
accumulator.
Decrement the accumulator's
contenta by 1.
Increment the accumulato~s
oontenta by 1.
Logical OR specified Immadiate
data with accumulator.
Logical OR oontenta of designated
register with accumulator.
Logical OR indirect the oontenta of
data memory location with
accumulator.
Rotate accumulator left by l-bR
withOut carry.

0 0 0 0 0 0 1 1

0 0 0 1 0 0 1 1
d7 de ds d. da d2 d1 do
0 1 1 1 1 r r r

0 1 1 1 0 0 0

IIrdsds~dad2d1

0 1 1 0 1 r

0 1 1 0 0 0 0

0 1 0 1 0 0 1 1
d7 de ds d. da d2 d1 do
0 1 0 1 1 r r r

0 1 0 1 0 0 0

0 0 1 1 0 1 1 1

0 0 1 0 0 1 1 1

0 1 0 1 0 1 1 1

0 0 0 0 0 1 1 1

0 0 0 1 0 1 1 1

0 1 0 0 0 0 1 1
d7 de de d. da d2 d1 do
0 1 0 0 1 r r r

0 1 0 0 0 0 0

1 1 1 0 0 1 1 1

Rotate accumulator left by l-bR
through carry.

1 1 1 1 0 1 1 1

Rotate accumulator right by l-bR
withOut carry.

0 1 1 1 0 1 1 1

Rotate accumulator right by I-bit
through carry.

0 1 1 0 0 1 1 1

Swap the 2 4-bit nibbles in the
accumulator.
Logical XOR specifiad immediate
data with accumulator.
logical XOR Contenta of
designated register with
accumulator.
Logical XOR indirect the oontenta
of date memory location with
accumulator.

0 1 0 0 01

6-68

1 1

1 1 0 1 0 0 1 1

d7dsde~dad2d1

1 1 0 1 1

1 1 0 1 0 0 0

··
· ·
··
· ·
· ·
··

··

·
·

Product Specification

Signetics Microprocessor Products

SCN8049, SCN8050, SCN8039, SCN8040
Single-Chip 8-Bit Microcontroller

SCN8049 Series

Table 1. Instruction Set (Continued)
INSTRUCTION CODE
FUNCTION

MNEMONIC

FLAGS

CYCLES

DESCRIPTION

07 0. Os D. 03 O2 0,

BYTES

Branch
DJNZ Rr, addr

JBb addr

(Rr) +- (Rr)-I; r~0-7
if (Rr) *0:
(PC 0 - 7) +- addr
(PC 0-7) <- addr if
Bb~ 1
(PC) +- (PC) + 2 if Bb

1 1 1 0

1 1 1 0 0 1 1 0
"7as aS . . . . 82 81 as

1 0 0 0 0 1 1 0
a7 as a5 .. "3 a2 ", as

Jump to specified address if test 0 0 0 1 0 0 1 1 0
is low.
a7 as 8S 8.4 a3 82 81 ao

Jump to specified address if test 1 0

Decrement the specified register
and test contents.

87 a6 8S 84 83 82 81

Jump to specified address if

b2b,bol

accumulator bit is set.

87 86 85 84 83 82 81

0 0

1 0

JC addr

(PC 0 - 7) +- addr if
Jump to specified address if carry
1
flag is set.
(PC) <- (PC) + 2 if C ~ 0
(PC 0 - 7) +- addr if
Jump to specified address if flag
FO~ 1
FO is set.
(PC) <- (PC) + 2 if

JFO addr

1 1 1 1 0

1 1 0

a7asa5~a3

82 81

1 0 1 1 0

1 1 0

87 86 8 58.483 82 81

as
"0

FO~O

JFl addr

JMP addr

JMPP @ A
JNC addr

(PC 0 - 7) +- addr if
Fl ~ 1
(PC) +- (PC) + 2 if
Fl ~ 0
(PC 8 -10) .... addr
8-10
(PC 0-7) +- addr 0-7
(PC 11) .... (DBF)
(PC 0 - 7) .... «A»
(PC 0 - 7) +- addr if
C~O

JNI

JNTO addr

(PC) .... (PC)+2 if C~1
(PC 0 - 7) +- addr if
iNi=O
(PC) .... (PC) + 2 if
INT~ 1
(PC 0 - 7) +- addr if
TO~O

JNTI addr

JNZ addr

(PC) .... (PC) + 2 if
TO ~ 1
(PC 0-7) .... addr if
T1 -0
(PC) .... (PC) + 2 if
T1 ~ 1
(PC 0 - 7) .... addr if
A~O

JTF addr

(PC) .... (PC) +2 if A~O
(PC 0 - 7) .... oddr if
TF~ 1
(PC) .... (PC) + 2 if

Jump to specified address if flag
Fl is set.

Direct jump to specified address

within the 2K address block.

Jump indirect to specified address
within address page.
Jump to specified address if carry
flag is low.
Jump to specified address if INT

input is low.

0 1 1 1 0 1 1 0

85 84 83 82 81

81089 88 0 0 1 0
87
8S .. "3 82 81

1 0

1 1 0 0 1

1 0 0 0 1

1 0

is low.

Jump to specified address if
accumulator is non~zero.

1 0 0 1 0 1 1 0
"7 as os .... 02 0, as

Jump to specified address if timer
flag is set to 1.

0 0 0 1 0 1 1 0
a7 as as .... a2 a, as

1 1 0 1 1 0
as B4 83 82 81 as

Jump to specified address if test 1 0 1 0 1 0 1 1 0
is a 1.
87 as 85 B4 83 82 81 as

Jump to specified address if
accumulator is O.

1 1 0 0 0 1 1 0
"7 as as .. a3 a2 a, as

Enable the external (INn intemupt.
Disable the external (INn interrupt.
Select bank 0 (locations 0 - 7) of
data memory.

0 0 0 0 0
0 0 0 1 0
1 1 0 0 0

1
1
1

83 82 81

TF~O

JTO addr

JTl addr

JZ addr

(PC 0-7) .... addr if
TO~ 1
(PC) .... (PC) + 2 if
TO-O
(PC 0-7) .... addr if
Tl ~ 1
(PC) .... (PC) + 2 if
Tl =0
(PC 0 - 7) .... addr if
A~O

Jump to specified address if test 0 0 0

is a 1.

(PC) +- (PC) +2 if A*O

Control

EN I
DIS I
SEL RBO

August 26, 1986

(BS) .... 0

6-59

1 0
1 0
1 0

1
1
1

Signatics Microprocessor Products

Product Specification

SCN8049. SCN8050. SCN8039. SCN8040
Single-Chip 8-Bit Microcontroller

SCN8049 Series

Table 1. Instruction Set (Continued)
INSTRUCTION CODE
MNEMONIC

FUNCTION

FLAGS

DESCRIPTION

CYCLES

D-rDeD.D.D3 D2 D,

BYTES

Control (Cont.)
SEL RBI

(BS) +- 1

SEL MBO

(DBF) +- 0

SEL MBI

(DBF) +- 1

ENTO CLK

Select bank 1 (locations 24 - 31)
of data memory.
Select program memory bank 0,
addresses 0 - 2047.
Select program memory bank I,
addresses 2048 - 4095
Enable clock output on TO pin.

1 1 0 1 0 1 0 1

1 1 1 0 0 1 0 1

1 1 0 1 0 1

0 1 1 1 0 1 0 1

Move immediate the specified data 0 0 1 0 0 0 1 1
into the accumulator.
d7 d6 d5 do da d2 d, do
Move the contents of the
1 1 1 1 1 r r r
designated register into the

1 1 1

1 0 1 1 1 r r r
d7 d6 d5 d. da d2 d, do
1 0 1 0 1 r r r

1 1

Data moves
MOV A,

data

(A) +- data
(A) ...... (Rr); r=0-7

MOV A, Rr

MOV PSW, A

(PSW) ...... (A)

MOVP A, @ A

(A) ...... «A))

MOVP3 A, @ A
MOVX A, @ Rr

(A) ...... «A))
in page 3
(A) +- «Rr)); r=O-1

MOVX @ Rr, A

«Rr)) ...... (A); r=O-1

XCH A, Rr

(A) " (Rr); r-0-7

XCH A, @ Rr

(A)"«Rr)); r-O-l

XCHD A, @ Rr

(A 0-3)~(Rr)(0-3)
r-O-l

accumulator.
Move indirect the contents of data
memory location into the
accumulator.
Move contents of the program
status word into the accumulator.
Move immediate the specijied data
into the designated register.
Move accumulator contents into
the designated register.
Move indirect accumulator contents
into data memory location.
Move indirect the specified data
into data memory.
Move contents of accumulator into
the program status word.
Move data in the current page into
the accumulator.
Move data in page 3 into the
accumulator.
Move indirect the contents of
external memory location into the
accumulator.
Move indirect the contents of the
accumulator into external memory.
Exchange the accumulator and
designated register's contents.
Exchange indirect contents of
accumulator and location in data
memory.
Exchange indirect 4·b~ contents of
accumulator and data memory.

Complement content of carry btt.
Complement content of flag FO.
Complement content of flag Fl.
Clear content of carry bit to O.
Clear content of flag 0 to O.
Clear content of flag 1 to O.

1
1
1
1
1
1

(BUS) +- (BUS) AND
data
(Pp) ...... (Pp) AND data
p= 1-2
(Pp) +- (PP) AND (A
0-3)
p=4-7

Logical AND immediate specified
data with BUS.
Logical AND immediate specified
data with deSignated pori (lor 2).
Logical AND contents of
accumulator wtth deSignated pori
(4-7).

1 0 0 1 1 0
d7 do d5 do da d2
1 0 0 1 1 0
d7 de d5 do da d2
1 0 0 1 1 1

MOV A, @ Rr

(A) ...... «Rr)); r=O-1

MOV A, PSW

(A) ...... (PSW)

MOV Rr,

data

(Rr) ...... data; r=0-7

MOV Rr, A

(Rr) ...... (A); r=0-7

MOV @ Rr, A

«Rr)) ...... (A); r - 0 - 1

MOV @ Rr,

data

«Rr)) +- data; r = 0 - 1

1 1 1 1 0 0 0

1 1 0 0 0

1 0 1 1 0 0 0 r
d7 de d5 do da d2 d, do
1 1 0 1 0 1 1 1

1 1

1 1 1 0 0 0 1 1

1 0 0 0 0 0 0

1 0

0 1 0 0 0

0 0

1 0 1

0 0

1 0 0 0 0

0 0

1 1 0 0 0

1
1
1
1
1
1

1
1
1
1
1

0 0
d, do

P P

1 0

1 0 0 0 0

1 0 0 0

·.· ·

Flags
CPL
CPL
CPL
CLR
CLR
CLR

C
FO
Fl
C
FO
Fl

0 1
0 0
0 1
0 0
0 0
0 1

0
1
1
1
0
0

0
0
0
0
0
0

1
1
1
1
1
1

1
0
0
1
0
0

Input/output
ANL BUS,

data

ANL Pp,

data

ANLD Pp, A

August 26, 1986

6-60

P P

· ·.
· ·
·

Signetics Microprocessor Products

Product Specification

SCN8049, SCN8050, SCN8039, SCN8040
Single-Chip 8-Bit Microcontroller

SCN8049 Series

Table 1. Instruction Set (Continued)

INSTRUCTION CODE
MNEMONIC

FUNCTION

FLAGS

DESCRIPTION

CYCLES

BYTES
C

D7 D6 D. D. D3 D2 D, Do

Input/output (Cant.)
IN A, Pp

(A) ..... (Pp); p = 1 - 2

INS A, BUS

(A) ..... (BUS)

MOVO A, Pp

(A 0-3) ..... (Pp);
p=4-7
(A4-7) ..... 0

MOVO Pp, A

(Pp) ..... A 0-3; p=4-7 Move contents of accumulator to
designated port (4 - 7).
(Pp) ..... (Pp) OA (A
logical OA contents of
0-3)
accumulator with designated port
p =4-7
(4-7).
(BUS) .... (BUS) OA data logical OA immediate specified
data with BUS.
(Pp) ..... (Pp) OA data
logical OA immediate specified
data with designated port (1 - 2).
P = 1-2
(BUS) ..... (A)
Output contents of accumulator
onto BUS.
(Pp) .... (A); p = 1-2
Output contents of accumulator to
designated port (1 - 2).

OAlO Pp, A

ORl BUS,

# data

OAl Pp,

# data

OUTl BUS, A
OUTl Pp, A

Input data from designated port
(1 - 2) into accumulator.
Input strobed BUS data into
accumulator.
Move contents of designated port
(4 - 7) into accumulator.

a a a a

a a a

0 1 1 P P

1 1 P P

1 P P

1 a a a 1 a a a
d7 ds ds d4 do d2 d, do
1 a a a 1 a p p
d7 ds ds d4 do d2 d, do
0 a a a a a 1 a

a a a
a a
1

1 1

a a a

1 1 1

p p

a a

a a a

1 1

a a a

1 0

a a

a a
ao

p p

Registers
DEC Ar

(Ar) ..... (Ar)-l; r=0-7

INC Ar

(Ar) ..... (Ar) + 1; r=0-7

INC @ Ar

«Ar» ..... «Ar» + 1;
r=O-l

Decrement contents of designated
register by 1.
Increment contents of designated
register by 1.
Increment indirect the contents of

1 1

data memory location by 1.

Subroutine
CAll addr

AET
AETR

«SP» ..... (PC), (PSW
4-7)
(SP) ..... (SP) + 1
(PC 6-10) ..... addr
6-10
(PC 0-7) ..... addr 0-7
(PC 11) ..... OBF
(SP) ..... (SP) - 1
(PC) ..... «SP»
(SP) ..... (SP) - 1
(PC) ..... «SP»
(PSW 4 - 7) ..... «SP»

Call designated subroutine.

Return from subroutine without
restoring program status word.
Return from subroutine restoring
program status word.

a'Oa9 .. 1

a a a a a

1 1

a a

1 1

a a 1 a a 1 a 1
a a 1 1 a 1 a 1
a 1 a a a a 1 a

1
1
1

8S 84 a3 82 81

a a

TimerI counter

EN TCNTI
DIS TCNTI
MOV A, T

(A) ..... (T)

Move contents of timer/counter
into accumulator.

MOV T, A

(T) ..... (A)

Move contents of accumulator into
timer/counter.

1 1

a a a

Stop count for event counter or
timer.

1 1

a a

Start count for event counter.
Start count for timer.

a
a

1
1

1 0 1
1 a 1

1
1

No operation performed

a a a a a a a a

STOP TCNT
STRT CNT
STRT T

Enable timer/counter interrupt.
Disable timer/counter interrupt.

a a a
a 1 a

Miscellaneous
NOP

NOTES:
1. Instruction code designations rand p form the binary representation of the registers and ports involved.
2. The dot under the appropriate flag bit indicates that its content is subject to change by the instruction in which it appears.
3. Numerical subscripts appearing in the FUNCTION column reference the specific bits affected.

August 26, 1986

6-61

Signetics Microprocessor Products

Product Specification

SCN8049, SCN8050, SCN8039, SCN8040
Single-Chip 8-Bit Microcontroller

SCN8049 Series

SYMBOL DEFINITIONS
SYMBOL
A
AC
addr

The accumulator

"In-Page" operation designator
Port designator (p = 1, 2 or 4 - 7)

PSW

The auxiliary carry flag

Program status word

Program memory address (11 bits)

Stack pointer

Bit designator (b

The bank switch

P
Pp

DESCRIPTION

°-

T
TF

Carry flag

TO, Tl

Timer
Timer flag
Testable inputs 0, 1

ClK

Clock signal

CNT

Event counter

Prefix for immediate data

Nibble designator (4 bits)

Prefix for indirect address

0
DBF

Program memory bank flip-flop

data

Number or expression (8 bits)

Fa, Fl
I

-....
$

Flags 0, 1

Program counter's current value
Replaced by
Exchanged with

Interrupt

INT

External interrupt

Table 2. Instruction Timing""
CYCLE 1
INSTRUCTION

CYCLE 2

IN A,P

Fetch
Instruction

Increment

Timer

Fetch
Instruction

Increment
Timer

Output
To Port

Read Port

OUTL P,A
ANL P, # data

Fetch
Instruction

Increment
Program Counter

Increment

Program Counter

Increment
Program Counter

Increment

Instruction

OUTl BUS, A

Fetch
Instruction

Increment
Program Counter

Increment
Timer

Output
To Port

ANL BUS, #: data

Fetch
Instruction

Increment
Program Counter

Increment
Timer

Read Port

Fetch
Immediate Data

ORl BUS, # data

Fetch
Instruction

Increment
Program Counter

Increment
Timer

Read Port

Fetch
Immediate Data

Output
Data to
RAM

ORL P,

'* data

INS A, BUS

Fetch
Instruction

Fetch

Increment

·
·
·
·

Program Counter
Increment
Program Counter

Increment

Timer
Increment
Timer

Read Port

Fetch
Immediate Data

Read Port

Fetch
Immediate Data

Timer

Read Port

MOVX @R,A

Fetch
Instruction

Increment
Program Counter

Output RAM
Address

Increment
Timer

MOVX A,@R

Fetch
Instruction

Increment
program Counter

Output RAM
Address

Increment
Timer

Read Data

MOVD A, Pi

Fetch
Instruction

Increment
Program Counter

Output
Opcodel Address

Increment
Timer

Read
P2 lower

MOVO Pj, A

Fetch
Instruction

Increment
Program Counter

Output
Opcodel Address

Increment
Timer

Output Data
TO P2
Lower

ANlD P, A

Fetch
Instruction

Increment
Program Counter

Output
Opcodel Address

Increment
Timer

Output
Data

CRlO P, A

Fetch
Instruction

Increment
Program Counter

Output
Opcodel Address

Increment
Timer

Output
Data

J (CONDITIONAL)

Fetch
Instruction

Increment
Program Counter

Sample
Condition

Increment
Timer

Fetch
Immediate Data

9TART CNT ISTAT T

Fetch
Instruction

Increment
Program Counter

Fetch
Instruction

Start
Counter

STOP TCNT
EN I

Fetch
Instruction

Enable
Interrupt

DIS I

Fetch
Instruction

ENTO ClK

Fetch
Instruction

·
·
·
·
·
·

Increment
Program Counter
Increment
Program Counter
Increment
Program Counter
Increment
Program Counter

Stop
Counter

Disable
Interrupt

Enable

Clock

NOTES:

'Valid instruction address are output at this time if extemal program memory is being accessed,
.. See figures 11 and 12 for instruction cycle and cycle timing,

August 26, 1986

6-62

·
·
·
·
·
·
·
·
·
·
·
·
·
·
·

Increment
Program Counter

Output
To Port

Increment
Program Counter

Output
To Port

Increment
Program Counter

Output
To Port

Increment
Program Counter

Output
To Port

Update
Program Counter

Signetics

Microprocessor Products

Section 7
Sales Offices,
Representatives &
Distributors

I
I

,-.

Sales Offices,
Representatives &
Distributors

Signetics

SIGNETICS
HEADQUARTERS

811 East Arques Avenue
P.O. Box 3409
Sunnyvale, CA 94088-3409
Phone: (408) 991-2000
ALABAMA
Huntsville
Phone: (205) 830-4001

ARIZONA
Phoenix
Phone: (602) 968-5777

CALIFORNIA

NEW JERSEY

FLORIDA

NEW YORK

Parsippany
Phone: (201) 334-4405

Clearwater
Sigma Technical Assoc.
Phone: (813) 791-{)271

Ithaca
Bob Dean, Inc.
Phone: (607) 257-1111

NEW YORK
Hauppauge
Phone: (516) 348-7877
Wa~pingera

Falla
hone:(914) 297-4074

Ft. Lauderdale
Sigma Technical Assoc.
Phone: (305) 731-5995

ILLINOIS

Raleigh
Phone: (919) 781-1900

Hoffman Estates
Micro-Tex, Inc.
Phone: (312) 382...,'3001

OHIO

INDIANA

NORTH CAROLINA

Columbus
Phone: (614) 888-7143

Calabasas
Phone: (818) 880-6304

Da~ton

Irvine
Phone: (714) 833--8980
(714) 752-2780

OREGON

Los Angeles
Phone: (213) 670-1101

hone: (513) 294-7340

Indianapolis
Mohrfield Marketing, Inc.
Phone: (317) 54EH;969

IOWA

PENNSYLVANIA

MARYLAND

PENNSYLVANIA

Plymouth Meeting
Phone: (215) 825-4404
Greeneville
Phone: (615) 639-{)251

COLORADO

Columbia
Third Wave Solutions, Inc.
Phone: (301) 290-5990

MASSACHUSETTS

TEXAS

Needham Heights
Kanan Associates
Phone: (617) 449-7400

Aurora
Phone: (303) 751-5011

Austin
Phone: (512) 339-9944

MICHIGAN

FLORIDA

Houston
Phone: (713)668-1989

Bloomfield Hills
Enco Marketing
Phone: (313) 338-8600

Richardson
Phone: (214) 644...,'3500

MINNESOTA

CANADA
SIGNETICS CANADA,
LTD.

MISSOURI

ILLINOIS
Itasca
Phone: (312) 25Q-{)050

INDIANA
Kokomo
Phone: (317) 459-5355

KANSAS
Overland Park
Phone: (913) 469-4005

MASSACHUSETTS
Westford
Phone: (508) 692-6211

MICHIGAN
Farmington Hills
Phone: (313) 553-6070

MINNESOTA
Edina
Phone: (612)835-7455

April 1989

OREGON

Beaverton
Phone: (503) 627-{)110

Sunnyvale
Phone: (408) 991...,'3737

Atlanta
Phone: (404) 594-1392

OKLAHOMA
Tulsa
Jerry Robison
and Associates
Phone: (918) 665-3562
Beaverton
Western Technical Sales
Phone: (503) 644-8860

TENNESSEE

GEORGIA

Richfield
Bear Marketing, Inc.
Phone: (216) 659...,'3131

Cedar Rapids
J.R. Sales
Phone: (319) 393-2232

San Diego
Phone: (619) 56Q-{)242

Ft. Lauderdale
Phone: (305) 48EH;300

OHIO
Centerville
Bear Marketini;' Inc.
Phone: (513) 36-2061

Etobicoke, Ontario
Phone:(416)626-6676
Ne~ean, Ontario

hone: (613) 225-5467

Eden Prairie
High Technolo," Sales
Phone: (612)9 4-7274
Bridgeton
Centech, Inc.
Phone: (314) 291-4230

REPRESENTATIVES

Raytown
Centech, Inc.
Phone: (816) 358-8100

ARIZONA

NEW HAMPSHIRE

Scottsdale
Thorn Luke Sales, Inc.
Phone: (602)941-1901

Hookset
Kanan Associates
Phone: (603) 645-{)209

CALIFORNIA

NEW JERSEY

Orangevale
Webster Associates
Phone: (916) 989-{)843

East Hanover
Emtec Sales, Inc.
Phone: (201) 428-{)600

CONNECTICUT

NEW MEXICO

Fairfield
NRG, Limited
Phone: (203) 384-1112

Albu~uerque

F.. Sales
Phone: (505) 345-5553

7...,'3

Pittsbur~h

Bear arketing, Inc.
Phone: (412) 531-2002

Hatboro
Delta Technical
Sales, Inc.
Phone: (215) 975-{)600

UTAH
Salt Lake City
Electrodyne
Phone: (801) 264-8050

WASHINGTON
Bellevue
Western Technical Sales
Phone: (206) 641-3900
Spokane
Western Technical Sales
Phone: (509)922-7600

WISCONSIN
Waukesha
Micro-Tex, Inc.
Phone: (414) 542-5352

CANADA
Burnaby, B.C.
Tech-Trek, Ltd.
Phone: (604) 439-1373
Misslssauga, Ontario
Tech-Trek, Ltd.
Phone: (416) 238-{)366
Ne~ean, Ontario

ech-Trek, Ltd.
Phone: (613) 225-5161

Ville SI. Laurent, Quebec
Tech-Trek, Ltd.
Phone: (514) 337-7540

Signetics

Sales Offices, Representatives & Distributors

DISTRIBUTORS
Contact one of our
local distributors:
Anthem Electronics
Avnet Electronics
Aztech Electronics
Hamilton/Avnet Electronics
Marshall Industries
Schweber Electronics
Wyle/LEMG
Zentronics, Ltd.
FOR SIGNETICS
PRODUCTS
WORLDWIDE:
ARGENTINA
Philips Argentina S.A.
Buenos Aires
Phone: 54-1-541-7141

DENMARK
Philips Components AIS
Copenhagen S
Phone: 45-1-54-11-33

KOREA
Philips Industries, Ltd.
Seoul
Phone: 82-2-794-5011
1213/4/5

Co~resa

FRANCE
R.T.C. Compelec
Issy-ies-Moulineaux
Cedex
Phone: 33-1-40-93-80-00

MALAYSIA
Philips Malaysia SON
Bernhsd
Pulau Penang
Phone: 60-4-870-055

SWEDEN
Philips Components A.B.
Stockholm
Phone: 46-8--782-10-00

GERMANY
Valvo
Hamburg
Phone: 49-40-3-296-0

MEXICO
Panamtek
Guadalajara. Jal
Phone: 52-36-30-30-29

GREECE
Philips S.A. Hellenique
Athens
Phone: 30-1-4894-339

Mexico. D.F.
Phone: 52-5-586-84-43

HONG KONG
Philips Hong Kong, Ltd.
Kwai Chung. Kowloon
Phone: 852-0-245-121

AUSTRIA
Osterrichische Philips
Wien
Phone: 43-222-60-1 01
-820

INDIA
Peico Electronics
& Elect. Ltd.
Bombay
Phone: 91-22-493-0311

BELGIUM
S.A. MBLE Components
Brussels
Phone: 32-2-525-61-11

INDONESIA
P.T. Phlllcs-Raiin
Electron cs
Jakarta Selatan
Phone: 62-21-512-572

CHILE
Philips Chilena S.A.
Santiago
Phone: 56-02-077-3816
CHINA,
PEOPLES REPUBLIC OF
Philips Hong Kong, Ltd.
Kwai Chung, Kowloon
Phone: 852-0-424-5121
COLUMBIA
Iprelenso, Ltda.
Bogota
Phone: 57-1-2497624

April 1989

SOUTH AFRICA
SA Philigs (PTY), Ltd.
Rand urg
Phone: 27-11-889-3911

FINLAND
OyPhilipsAb
Espoo
Phone: 358-0-502-61

AUSTRALIA
Philips Electronic
Components & Mat'I Ltd.
Artarmon. N.SW.
Phone: 61-2-439-3322

BRAZIL
Philips Do Brasil, Ltda.
Sao Paulo
Phone: 55-11-211-2600

Philips Components Japan
Tokyo
Phone: 81-3-280-2620

NETHERLANDS
Philips Nederland
Eindhoven
Phone: 31-40-444-755

IRELAND
Philips Electrical Ltd.
Dublin
Phone: 353-1-69-33-55
ISRAEL
Ra~ac Electronics, Ltd.
elAviv
Phone: 972-3-477115

NEW ZEALAND
Philips N_ Zealand Ltd.
Auckland
Phone: 64-9-605-914
NORWAY
Norsk AlS Philips
Oslo
Phone: 47-2-68-02-00
PERU
Cadesa
San Isidro
Phone: 51-14-707-080
PHILIPPINES
Philips Industrial Dev., Inc.
Makati Metro Manila
Phone: 63-2-810-01-61
PORTUGAL
Philips Portuguesa SA
Lisbon
Phone:351-1-68-31-21

ITALY
Philips S.p.A.
Milano
Phone: 38-2-67-52-1'
JAPAN
Philips Components Japan
Osaka-Shi
Phone: 81-6-389-7722

7-4

SINGAPORE
Philips Project Dev.
Pte., Ltd.
Singapore
Phone: 65-350-2000

SPAIN
S.A.
arcelona
Phone:34-3-301-63-12

SWITZERLAND
Philips Components A.G.
Zuerich
Phone:41-1-488-2211
TAIWAN
Philips Taiwan, Ltd.
Taipei
Phone: 886-2-712-0500
THAILAND
Philips Electrical Co.
of Thailand Ltd.
Bangkok
Phone: 66-2-223-6330/9
TURKEY
Turk Philips
Ticaret A.S.
Istanbul
Phone: 90-1-179-27-70
UNITED KINGDOM
Philips Components
London
Phone: 44-1-580-6633
UNITED STATES
Signetics International
co~.
unnyvale, California
Phone: (408) 991-2000
URUGUAY
Luzllectron SA
Montevideo
Phone: 598-91-56-411
42/43/44
VENEZUELA
Magnetica S.A.
aracas
Phone: 58-2-241-7509

INDEX

"~'t:l
43

TOP VIEW

Pin
1
2
3
4
5
6
7

9
10
11
12
13
14

16
17
1A
1,1

"
21

22
23

Function

:~::;~~!~

59 P6.4
58 P6.3

P2.6/Al4 8

~ P6.2

:~..;::~~~

56 P6.1

P5.0/ADCO

Function
XTALl

VoD

V"
V"

:~::;~~:~

P2.0/A08
P2.1/A09

PO.4/AD413
PO.3/AD3 14

37
38
PwMo
PWMT
39
40
f"W
P4,O/CMSr~O 41
P4.1/CMSfll 42
P4,?/CM:;f12 43
r4.:1/CM:;\\J 44

STADG

P4,4fCM::!!4

P2.2/Al0
P2.3/Al1

PI (J!C1UI
1'1,
1 II

lie

l'I.:.'IC1;>1
1'1,:l/C1:11
1'1,4/1;>
Pl.f)/fH2

pl.S/sel
P1.71SDA
P3.0/RXO

P3.1/TXD
P3.2/INTO
P3.3/TN'i'T

ALE

P3.4/TO
P3.5/Tl
P3.6/~

P3.7iRD
NC
NC

XTAl2

P4.2 20
P4.1 21

i'A

PO.7/AD?

50
51
52
63
54
55
56
57
66
59
60
61
62
63
64
65
66
67
6'

DIP

Vee 18
P4.319

PO.S/ADS

PO.2/AD2
PO.1/AD'
PO.D/ADO

AVrefAVref+

P2.6/Al 4 8
P2.7/Al
PO.7/AD
PO.6/AD61fi
PO.5/AD 512
PO.4/AD 413
PO.3/AD
PO.2/AD
POol/AD 1 16
PO.O/AD 017
Ye e 18
P4.
P4.
P4. 121
P4. 022
P1. 023
P1.
P1.
P1. 326
P1. 427
P1. 528

~ P5.4
43 P5.3
42 PS.2

~ :::~/Ro
38 P3.6/WR
37 P3.5/T1

Pl.629
Pl.7 30

~ :::;;~:T1

P3.0/::~~

34 P3.2/"'iNTO

P1.
P1.

33 P3.1/TxD

"~d
10

40 Vee

PI,1 2

39 PO.D/ADO

I'l" 3
1'1 :1 4

38PO.l/AOl

1'1 4 5

36 PO.3/A03
35 PO.4/AD4

:;CI./I'1.6 I

34 PO.5/AD5

SDAfrl:~~~

~PO.6/AD6

RxD/DA1A/P:1.O 10
TxD/ClOCK/P3.1 11
IN-rOIP3.2 12

¥.~.7/AD7
31 EA
30ALE
29 PSEN
28 P2.7/A1S

DIP

IN~~;:::! H

gP2.6/A14
26 P2.5/A13

Tl/P3.515
WR/P3.616

25 P2.4/A12

RD/P3.7
XTAl218

~P2.3/A11

gP2.2/Al0
22 P2.l/A9
21 P2.0/A8

XTALl 19
Vss 20

'ToPViEW
INDEX
CORNER

EJ
PlCC

TOP VIEW

Pin
1
2
3
4
5
6
7
8
9
10
11
12

Function

23
24

PLO
PI.1
P1.2
PI.3
P1A
Pl.!>
SCLlI'l.t;
SDA/f'l.1

mTill'.1 I
10!f':1·'

11/I'::!.!;

RxD/DA 1 A/P3.0
NC
Tx[)IICII)CK/P3.1

14
15
16
17

TNTr\/I':l;.1

20
21
22

29
30
31
32
33
34
35
36
37
38

RST

16
19

25
26
27

~/P:1.r,

1'10/P3.7
XTAI.;>
XTAl.l

41
42

P2.0/A8
P2.1/A9
P2.2/Al0
P2.3/Al1
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A1S

rnN
ALE

PO.7/AD7
PO.6/AD6
PO.5/AD5
PO.4/AD4
PO.3/AD3
PO.2/AD2
PO.l/AD1
PO.D/ADO

Vco

INDEX
CORNER

Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23

Function
EAJVPP
P2.0/A8
P2.1/A9
P2.2/Al0
P2.3/All
P2.4/AI2
P2.5/A13
P2.6/A14
P2.7/A15
PO.7/AD7
PO.6/AD6
PO.5/ADS
PO.4/AD4
PO.3/AD3
PO.2/AD2
PO.l/AD1
PO.O/ADO

Pin
24
25
26
27
28
29

30
31
32
33
34
35
36
37
38

Vee

39
40
41

P4.7
P4.6
P4.5
P4.4
P4.3

42
43
44
45
46

Function
P4.2
P4.l
P4.0
Pl.0
Pl.1
Pl.2
Pl.3
Pl.4
P1.S
Pl.6
Pl.?

Pin
47
48
49
50
51
52
53
54
55
56
67
RST
58
P3.0/RxD 59
P3.l/TxD 60
P3.2/ii\l'i'O 61
P3.3/INTl 62
P3.4/TO
63
64
65
P3.7/RD
66
PS.O
67
PS.1
68

~~:~~W

P5.?

P3.2/1NTo
P3.l/TxD

27
43
TOP VIEW

TOP VIEW
Function
PS.3
PS.4
P5.5
P5.6
P5.7
XTAl2
XTAL1

ODS

iDS
BFLAG
AFLAG
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6

~~'~N
ALE/Pi"fc5G

PI,
1
2
3
4

,
6
7

,
9
10
11
12

13
14
15
16
17

Function

i'A
P2.0/A8
P2.1/A9
P2.2/Al0
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
PO.7/AD7
PO.6/AD6
PO.5/AD5
POA/AD4
PO.3/AD3
PO.2/AD2
PO.I/AD1
PO.D/ADO

Vee

P4.7
P4.6
P4.5
P4.4
P4.3

20
21

22
23

22 P2.1/A9
21 P2.0/A8

Pin
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43

44
45
46

Function
P4.2
P4.1
P4.0
Pl.0
Pl.1
Pl.2
Pl.3
P1.4
P1.5
Pl.6
Pt.7

Pin
47
48
49
50
51
52
63
54
55
56
57
RST
66
P3.0/RxD 59
P3.1/!21L 60
P3.21ltllQ 61
P3.3/1NTl 62
P3.4/TO
63
P3.5/Tl
64
P3.6/!tZB
65
P3.7/RD
66
P5.0
67
P5.l
66
P5.2

Function
P5.3
P5.4
P5.S
P5.6
P5.7
XTAL2
XTALl

ODs

iDS

BFLAG
AFLAG
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6

~~JN

ALE

P3.7IRo
P3.6/WR
37 P3.5/T1
36 P3.4/TO
35 P3.3/TNfi

LCC

24 P2.3/Al1
23 P2.2/Al0

TOP VIEW

'8'

P2.6/A14
26 P2.5/A13
25 P2.4/A12

XTAL1 ~
Vss 20

40 PS.O

~
33

29 PSEN
28 P2.7/A15

XTAL2~

~
36

~¥o

PO.6/AD6
32 PO.7/AD7
31 EA
30 ALE

WR/P3.6 16
RoJP3.7 17

INDEX
CORNER

42 P5.2
41 P5.1

TOP VIEW

LCC

37 PO.2/A02

I' 1 .~, (}

45 PS.5
44 P5.4
43 PS.3

RS T31

INDEX

PI,O 1

46 P5.6

TOP VIEW

S83C652/S80C652

XTAL2
4'47 PS.7

P3.0/RxD 32

DIP

RxD/P3.0 10
TxD/P3.1 11
INTO/P3.2 12
TO/P3.4 14
T1/P3.5 15

~¥S

41 P5.1

34 PO. 51 ADS
~

INT1/P3.3~

ODs

50 V"
XTALl

!¥o

36 PO.3/AD3
35 PO.4/AD4

:~~~

~I DS
DIP

38 PO.l/AD1
37 PO.2/AD2

P1.6~

54 AfLAG
BFLAG
51

~ PO.O/ADO

P1.3 4
P1.4 5
P1.5 6

ODS
Vss
XTALl
XTAL2
P5.7
PS.6

P6.6

58 P6.3
P6.2
56 P6.1
55 P6.0

:~::~

AVSS
AVOD

P5.7/AOC7
P5.6/ADC6
P5.5/ADC5
P5.4/ADC4
P5.3/ADC3
PS.2/ADC2
P5.1/ADCl

'F1,

40 Vee

T2JP1.0~

T2EX/Pl.1 ~
Pl.2 3

60 P6.5
59 P6.4

~ff

45 P5.5

P4.0 22
Pl.0 23
Pl.! 24
P1.225
P1.326

PO.5/AD5
PC.4/AD4
PO.3/AD3

51
50
49
48
47
46

~
61

P2.2/Al o 4
P2.3/Al
P2.4/Al
P2.5/Al

~iOs

:~:~;~~~~

P2.6/A14
P2.71A1S
PSEN

P2.0/A
P2.l/A 9 3

55 P6.0
54 AFLAG
53 BFLAG

PO.2/AD2~

P2.4/A12
P2.S/A13

1'4 !)/C:M~;H5 46
f'4 n/c'Mll1
47
i'4.fICMll
4'
H~; !
49

27
28
29
30
31
32
33
34

P2.3/All ~

61 P6.6
60 P6.5

PI,
35

64 ALE
63 PSEN
P6.?

64 AlE/PFiOG

t¥ P6.7

P2.2/Al0~

SCN8032AH/SCN8052AH

~PS""EN

P2.0/A8 2
P2.1/A9 3

EAIVPP 1

PLCC

SC80C4511SC83C451

SC87C451

S83C552/S80C552

PlCC

28
18
TOP VIEW

Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21

Function
NC

Pin
23

T2/Pl.0
24
T2EX/Pl.1 25
Pl.2
26
P1.3
27
Pl.4
28
P1.5
29
P1.6
30
P1.7
31
RST
32
RxD/P3.0 33
NC
34
TxD/P3.1 35
rFrrO"/P3.2 36
mTi/P3.3 37
TO/P3.4
36
Tl/P3.5
39
V'i7!=l/P3.6 40
Ri5/P3.7
41
XTAL2
42
XTAL1
43
44
V"

Function
NC

P2.0/A8
P2.1/A9
P2.2/Al0
P2.3/Al1
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A1S

rsEN
ALE
NC

EA
PO.7/AD7
PO.6/AD6
PO.5/AD5
PO.4/AD4
PO.3/AD3
PO.2/AD2
PO.1/AD1
PO.O/ADO

Vee

Signetics
a division of North American Philips Corporation
Signetics Company
81 1 E. Arq ues Avenue

P. O. Box 3409
Sunnyvale, Cali forn ia 94088-3409

Telephone 4081991-2000

98 -8000 -000

Printed in U.SA.

9167M fGT Ef70Mf FPf0589

Signetics
Philips Components

PHILIPS

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1989_Signetics_Microcontrollers_Users_Guide 1989 Signetics Microcontrollers Users Guide

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