1989_Silicon_Systems_Microperipheral_Products 1989 Silicon Systems Microperipheral Products
User Manual: 1989_Silicon_Systems_Microperipheral_Products
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MICROPERIPHERAL
PRODUCTS
INTEGRATED CIRCUITS
1989
·
0
A
T
A
BOO
K
Silicon Systems, Inc.
Silicon Systems, Inc. specializes in the marketing, design, and manufacturing of Application
Specific Integrated Circuits (ASICS). It offers a sophisticated line of custom and standard ICs primarily
aimed at the microperipheral, communications and industrial marketplace.
The Company was founded in 1972 and is headquartered in Tustin, California, 30 miles south of
Los Angeles. At first it offered only design services, but in the mid-70s began to subcontract the
manufacturing of finished products. In 1981, through initial public funding (SLCN/NASDAQ), the
Company launched its own wafer manufacturing capability, which was completed and put into
production in 1982. A fully integrated assembly and test operation in Singapore-was implemented
in 1985. In August, 1988, Silicon Systems announced the acquisition of its second wafer fabrication
facility and opened its fourth design center in Santa Cruz, California.
Present industry projections show the worldwide semiconductor market growing to $40 billion in
1990, a compound annual growth rate of more than 15 percent. Within that marketplace, the ASIC
segment is expected to grow in excess of 30 percent annually; whereas general purpose products
growth rates are forecasted at 13 percent. Silicon Systems has positioned its capabilities to
participate in the communications, computer and industrial ASIC market segments. The Company
achieved an $81.7 million sales level in 1987 and is expected to reach $110-120 million in 1988. In
recognition of its first $100 million year, the Company announced in August, 1988, its listing on the
New York Stock Exchange (SIUNYSE).
Silicon Systems possesses all the capabilities necessary to design, produce, market and deliver
ASICs to its growing worldwide customer base. This includes its waferfabs in Tustin and Santa Cruz,
California; assembly and test facilities in Singapore; and Design Engineering capabilities in Tustin,
Santa Cruz and Grass Valley, California, as well as Singapore.
©1988 Silicon Systems, Inc.
Table of
Contents
Product Index
Page #
Customer Reply Card
Table of Contents ....................................................................................................................................................1
Product Index ..................................................................................................................................................... 11
Numerical Index ....................................................................................................................................................IV
Product Selector Guide .........................................................................................................................................V
Section 1.
fNi@WII
fNi@WII
fNi@WII
fNi@WII
fNi@WII
fNi@WII
32R104C, 104CL, 104CM, 104CLM, 32R108, 108M, 122, 4-Channel ReadIWrite Device ................... 1-1
32R114, 4-Channel Thin Film Read/Write Device ................................................................................. 1-9
32R115, 2, 4, 5-Channel Read/Write Device ....................................................................................... 1-17
32R117/117R, 2, 4, 6-Channel Read/Write Device ............................................................................. 1-25
32R117Al117 AR, 2, 4, 6-Channel ReadIWrite Device ........................................................................ 1-35
32R188, 4-Channel ReadlWrite Device ............................................................................................... 1-45
32R501/501 R, 4, 6, 8-Channel Read/Write Device ............................................................................. 1-55
32R51 OAl51 OAR, 2, 4, 6-Channel ReadlWrite Device ........................................................................ 1-67
32R511/511 R, 4,6, 8-Channel Ferrite Read/Write Device .................................................................. 1-77
32R5121512R, 8, 9-Channel Thin Film Read/Write Device ................................................................. 1-89
32R514/514R, 2, 4, 6-Channel Read/Write Device ............................................................................. 1-99
32R515/515R, 9, 10-Channel Ferrite ReadlWrite Device .................................................................. 1-111
32R520/520R, 4-Channel Thin Film Read/Write Device ................................................................... 1-121
32R521/521R, 6-Channel Thin Film Read/Write Device ................................................................... 1-129
32R522/522R,4, 6-Channel Thin Film ReadIWrite Device ............................................................... 1-137
32R524R, 8-Channel Thin Film Read/Write Device .......................................................................... 1-145
32R525R, 4-Channel Thin Film Read/Write Device .......................................................................... 1-153
Section 2.
fNi@WII
fNi@WII
Read
Read
Read
Read
Data Processor ..............................................................................................................2-1
Data Processor ............................................................................................................ 2-15
Data Processor and Servo Demodulator ..................................................................... 2-25
Data Processor with Pulse Slimming ........................................................................... 2-45
HDD DATA RECOVERY
32D531, Data SeparatorlWrite Precompensation ................................................................................. 3-1
32D5321, Data Synchronizer/2, 7 RLL ENDEC ..................................................................................3·13
32D534, Data SynchronizerlMFM ENDEC ..........................................................................................3-41
320535, Data Synchronizer/2, 7 RLL ENDECIWrite Precompensation .............................................. 3-57
32D536, Data Separator/1, 7 RLL Encoding .......................................................................................3-85
Section 4.
fNi@WII
fNi@WII
HDD PULSE DETECTION
32P540,
32P541,
32P544,
32P546,
Section 3.
fNi@WII
fNi@WII
HDD READIWRITE AMPLIFIERS
HDD HEAD POSITIONING
32H101A, Differential AmpUfier ..............................................................................................................4-1
32H116. Differential Amplifier ................................................................................................................4-5
32H523R. Servo Read/Write. Thin Film ...............................................................................................4-9
32H566R. Servo ReadIWrite, Ferrite ...................................................................................................4-17
32H567, Servo Demodulator ...............................................................................................................4-27
32H568. Servo Controller ....................................................................................................................4-43
32H569. Servo Motor Driver ................................................................................................................4-67
II
Product Index (Continued)
Section 5.
fNJ@W!!
32M590-Series, Two-Phase 5-1/4" Winchester Motor Speed Controller .............................................. 5-1
32M591, Three-Phase 5-1/4" Winchester Motor Speed Controller ..... ...................... ............................ 5-7
32M593, Three-Phase Delta 5-1/4" Winchester Motor Speed Controller ............................................ 5-15
32M594, Three-Phase Delta Motor Speed Controller ......................................................................... 5-27
Section 6.
fNJ@W!!
fNJ@W!!
HDD SPINDLE MOTOR CONTROL
HDD CONTROLLER/INTERFACE
328450A, SCSI Controller .....................................................................................................................6-1
328451, SCSI Controller .....................................................................................................................6-37
32C452, Storage Controller ................................................................................................................. 6-53
32C452A, Storage Controller ................... ............................................................................................ 6-85
32C453, Dual-Port 8uffer Controller .................................................................................................. 6-121
328545, Winchester Disk Drive Support Logic .................................................................................. 6-145
Section 7.
FLOPPY DISK DRIVE CIRCUITS
34D441,
34P570,
34R575,
348580,
Section 8.
Data Synchronizer & Write Precompensator Device .............................................................. 7-1
2-Channel Floppy Disk Read/Write Device ............. .............................................................. 7-15
2, 4-Channel Floppy Disk Read/Write Device ....................................................................... 7-25
Port Expander Floppy Disk Drive .......................................................................................... 7-33
TAPE DRIVE CIRCUITS
35P550, 4-Channel Magnetic Tape Read Device ................................................................................. 8-1
Section 9.
CUSTOM/SEMI CUSTOM CAPABILITIES ............................................................................... 9-0
Section 10.
QUALITY ASSURANCE AND RELIABILITY ........................................................................ 10-0
Section 11.
PACKAGING/ORDERING INFORMATION
fNJ@W!!
fNJ@W!!
Packaging Index .................................................................................................................................. 11-0
Packaging Matrix ................................................................................................................................. 11-1
Package Types .................................................................................................................................... 11-2
Marketing Number Definition ............................................................................................................... 11-4
Plastic DIP 8 and 14 Pins .................................................................................................................... 11-5
Plastic DIP 16 and 18 Pins .................................................................................................................. 11-6
Plastic DI P 20, 22 and 24S Pins ........ .................................................................................................. 11-7
Plastic DIP 24 and 28 Pins .................................................................................................................. 11-8
Plastic DIP 32 and 40 Pins .................................................................................................................. 11-9
Cerdip 8 and 16 Pins ........................................... '" ........................................................................... 11-10
Cerdip 18 and 22 Pins ....................................................................................................................... 11-11
Cerdip 24 and 28 Pins. '" .......................................................................,........................................... 11-12
Surface Mounted Device (PLCC) 28 and 44 Leads ........................................................................... 11-13
Surface Mounted Device (PLCC) 52 and 68 Leads ........................................................................... 11-14
SON 8,14 and 16 Leads ................................................................................................................... 11-15
SOL 16 and 18 Leads ........................................................................................................................ 11-16
SOL 20 and 24 Leads ........................................................................................................................ 11-17
SOL 28 and 34 Leads ........................................................................................................................ 11-18
SOW 32 Leads .................................................................................................................................. 11-18
Flat Package Dimensional Diagrams and Chart, 10,24,28 and 32 Leads ....................................... 11-19
Section 12.
SALES OFFICES/DISTRIBUTORS ....................................................................................... 12-1
III
Numerical Index
SSi Device Numbers
Page #
SSi Device Numbers
Page #
328450A ................................................. 6-1
32P546 .................................................. 2-45
328451 .................................................. 6-37
32R104C, Cl, CM, ClM ......................... 1-1
328545 ................................................ 6-145
32R108, 108M ........................................ 1-1
32C452 ................................................. 6-53
32R114 ................................................... 1-9
32C452A ............................................... 6-85
32R115 ................................................. 1-17
32C453 ............................................... 6-121
32R117/117R ........................................ 1-25
320531 ................................................... 3-1
32R117A1117AR ................................... 1-35
3205321 ............................................... 3-13
32R122 ................................................... 1-1
320534 ................................................. 3-41
32R188 ................................................. 1-45
320535 ................................................. 3-57
32R501/501R ........................................ 1-55
320536 ................................................. 3-85
32R51 OAl51 OAR ................................... 1-67
32H1 01 A ................................................. 4-1
32R511/511 R ........................................ 1-77
32H116 ................................................... 4-5
32R512/512R ........................................ 1-89
32H523R ................................................. 4-9
32R514/514R ........................................ 1-99
32H566R ............................................... 4-17
32R515/515R ...................................... 1-111
32H567 ................................................. 4-27
32R520/520R .......... ......................... 1-121
32H568 ................................................. 4-43
32R521 1521 R ...................................... 1-129
32H569 ................................................. 4-67
32R522/522R ...................................... 1-137
32M590, 5901,5902 ............................... 5-1
32R524R ............................................. 1-145
32M591 ................................................... 5-7
32R525R ............................................. 1-153
32M593 ................................................. 5-19
348580 .................................................. 7-33
32M594 ................................................. 5-27
340441 ................................................... 7-1
32P540 .................................................... 2-1
34P570 .................................................. 7-15
32P541 .................................................. 2-15
34R575 ................................................. 7-25
32P544 .................................................. 2-25
35P550 .................................................... 8-1
IV
Microperipheral Products
Selector Guide
SSi Device
Number
H. .d
Type
.of
Channe..
Max
Input
Nol. .
nVNHz
Max
Input
CspecHance
(pF)
Reed
Gain
(typ)
Wrtte
Current
Rang.
R. .dIWrlte
Oats Port(s)
Power
Suppllee
(mA)
HOD READIWRITE AMPLIFIERS
SSI32R104C
SSI32R104CLN
SSI32R114
SSI32R115
SSI32R117
SSI32R117A
SS132R188
SS132R501
SS132R51OA
SSI32R511
SSI32R512
SSI32R514
SSI32R515
SSI32R520
SSI32R521
SSI32R522
SSI32R524R
SSI32R525
Ferrite
Ferrite
Thin Film
Ferrite
Ferrite
Ferrite
Ferrite
Ferrite
Ferrite
Ferrite
Thin Film
Ferrite
Ferrite
Thin Film
Thin Film
Thin Film
Thin Film
Thin Film
SSi Device
4
4
4
2,4,5
2,4,6
2,4,6
4
4,6,8
2,4,6
4,6,8
8,9
2,4,6
9,10
4
6
4,6
8
4
2.4
1.7
1.1
1.8
2.1
1.7
2.4
1.5
1.5
1.5
0.9
1.5
1.5
0.9
0.9
1.0
0.8
0.8
23
23
35
35
65
123
40
100
100
20
23
20
18
23
20
20
32
20
20
65
43
100
100
100
150
150
100
123
100
100
100
150
65
32
56
35
1510 45
1510 45
55 to 110
301050
101050
101050
3510 70
101050
101040
101040
101040
101040
101050
301075
201070
6 to 35
201060
251040
+6V,-4V
+6V,-4V
:l!N
:l5V
+5V,+12V
+5V,+12V
+6V,..sV
+5V,+12V
+5V,+12V
+5V,+12V
+5V,+12V
+5V,+12V
+5V, +12V
:l5V
+5V,+12V
+5V,+12V
+5V, +12V
+5V,..sV
Differential, Bi-directional
Differential, Bi...cJirectional
DifferentiailDifferentiai
Differential, Bi-directional
DifferentiaifTTL
DifferentiaifTTL
Differential, Bi-directional
DifferentiaifTTL
DifferentiaifTTL
DifferentiaifTTL
DifferentiaifTTL
DifferentiaifTTL
DifferentialfTTL
DifferentialIDifferentiai
DifferentiaifTTL
DifferentiaifTTL
DifferentiailDifferentiai
DifferentialIDifferentiai
Features
Circuit Function
Number
HDD PULSE DETECTION
SSI32P540
SS132P541
SSI32P544
SSI32P546
Read Data Processor
Read Data Processor
Pulse Detector
Pulse Detector
Time Domain Filter
AGC, Amplitude & Time Pulse Qualification, RLL Compatible
32P541-typa pulse detector with embedded servo electronics
32P541-type pulse detector with pulse slimming compatibility
HOD DATA RECOVERY
SSI320531
SSI3205321
SSI320534
SSI320535
SS132D536
Data Synchronizer
Dala
Dala
Dala
Dala
Separalor
Separalor
Separalor
Separalor
Data SynchronizerIWrite Precompensation
Data Synchronizer/2, 7 RLL ENDEC
Dala Synchronizer/MFM ENDEClWrite Precompensation
Dala Synchronizer/2, 7 RLL ENDEClWrite Precompansation
Data Synchronizer/1, 7 RLL ENDEClWrite Precompensation
HOD HEAD POSITIONING
SSI32H101A
SSI32H116
Preamplifier-Ferrite Head
Preamplifier-Thin Film Head
SSI32H523R
SS132H566
SS132H567
SS132H568
SS132H569
Servo ReadIWrit9
Servo ReadIWrite
Servo Demodulator
Servo Controller
Servo Motor Driver
AV = 93, BW = 10MHZ, en = 7.0 nW..'Hz
AV = 250, BW = 20MHz, en = 0.94 nW..'Hz
Single-channel thin-film readlwrite device
Single-channel ferrite readlwrite device
Di-bit Quadrature Servo Pattern: PLL Synchronization
Track & Seek Mode Operation; Microprocessor Interface
Head Parking, Spindle Molor Braking
HOD SPINDLE MOTOR CONTROL
SS132M590
SSI32M591
SS132M593
SSI32M594
2-Phase Motor Spead Control
3-Phase Motor Speed Control
3-Phase Motor Spead Control
Motor Speed Control
±a.035% Spead Accuracy; Unipolar Operation
±a.05% Speed Accuracy; Unipolar Operation
±a.037% Spead Accuracy; Bipolar Operation, 5-1/4" Drives
±a.037% Spead Accuracy; Bipolar Operation, 3-112", 5-114" Drives
HOD CONTROLLER/INTERFACE
SSI328450A
SS1328451
SS132C452
SS132C452A
SS132C453
SS1329545
SCSI Controller
SCSI Controller
Slorage Controller
Slorage Controller
Buffer Controller
Support Logic
Async transfer 10 2 MBPS; InitiatelTarget Modes; Internal Drivers; CMOS
Async transfer 10 1.5 MBPS; Internal Drivers; AIC 500L compatible
2OMbitsisec; CMOS; Programmable; AIC-D10 Compatible
15Mbitslsec; CMOS; Programmable; AIC-D10F Compatible
Non-mux addressing 10 16K; CMOS: AIC-300 Compatible
Includes ST506 Bus DriverslReceivers
FLOPPY DISK DRIVES
SSI340441
SSI34P570
SSI34R575
SSI349580
Data Seperalor
Read Data Path
ReadiWrite
Support Logic
High Performance Analog Data Separator, NEC 765 Compatible
2 Channel Read! Write With Read Data Path
2, 4 Channel ReadiWrite Circuit
Port Expander, Includes SA400 Interface Drivers/Receivers
TAPE DRIVER CIRCUITS
Read Data Path
4 Channel ReadlWrite With Read Data Path
v
SSI 32R104C, 32R104CL,
32R104CM, 32R104CLM,
32R108,32R122
4-Channel Thin Film
Read/Write Device
INNOVATORS IN INT E.G RATION
-----------------------------------------------------August, 1988
DESCRIPTION
The "M" version is functionally identical to the standard
SOL device, except that the pinout is the mirror image
to simplify mUlti-chip layouts.
The SSI 32R104 is a monolithic bipolar integrated
circuit for use in high performance disk drive systems
where it is desirable to locate the control circuitry
directly on the data arm. Each circuit controls four
heads and has three modes of operation: Read, Write
and Idle.
FEATURES
•
IBM 3350 compatible performance
IBM compatible power supply voltages and logic
levels
The SSI 32R104L is a low-noise version of the
SSI 32R1 04 with all other parameters identical. Both
are available in 24-pin flatpack, and 24-pin small outline (SOL) packages.
•
Four readlwrite channels
•
Safety circuits
The SSI32R108 and SSI32R122 are identical in performance to the SSI32R1 04. The SSI32R1 08 is packaged in a 24-pin DIP package, while the SSI32R122 is
packaged in a 22-pin DIP.
PIN DIAGRAM
BLOCK DIAGRAM
US
CE [
UNSAFE
CIRCUIT
WS
VEE
GNO
HS'
WS
vee
H2'
US
H22
WC
HO'
NlC
POST
READ
AMPLIFIER
Dx
Dy
NlC
HS2
C;
e
HEAD
SELECT
H32
DIFFERENTIAL
READ
AMPLIFIERS
AND
WRITE
CURRENT
SWITCHES
"-, H'2
H2'
HS2
CE
(4-CHANNELS)
_H22
VEE
GNO
H"
~
'HEAD2
HS'
H02
H3'
~
H3'
H32
OX
H"
OY
H'2
• MUST NOT CONNECT
32R104, 32R10B Pinout
CAUTION: Use handling procedures necessary
for a static sensitive component.
WC
0888
1-1
551 32R1 04C, 32R1 04CL,
32R104CM,32R104CLM,
32R108,32R122
4-Channel Thin Film Read/Write Device
CIRCUIT OPERATION
WRITE MODE
In the write mode, the circuit functions as a current
gate. Externally supplied write current is gated by the
state of the head select and data inputs to one side of
one head. Head voltage swings are monitored by the
head transition detect circuit. Absence of proper head
voltage swings,indicating an open or short on either
side of the head or absence of write current, will cause
a fault current to flow into the unsafe pin.
differentially read from one of four heads and an open
collector differential signal is put across the Data X and
Data Y pins. If a fault condition exists such that write
current is applied to the chip when the chip is in read
mode, the write current will be drawn from the unsafe
pin and the fault will be detected.
HEAD SELECT TABLE
HEAD SELECTED
HS.2
HS1
0
1
1
READ MODE
In the read mode, the circuit functions as a low noise
differential amplifier. The state of the head select
inputs determines which amplifier is active. Data is
1
1
0
2
0
1
3
0
0
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, 5.7 S VCC S 6.7, -4.2 S VEE S -3.8, 0° S Tj, S 110°C.
ABSOLUTE MAXIMUM RATINGS
Operation above absolute maximum ratings may permanently damage the device.
PARAMETER
Positive Supply Voltage VCC
Negative Supply Voltage, VEE
RATING
UNIT
7.0
V
-5.5
V
-65 to 150
°C
Head Select (HS)
VEE -0.3 to + 0.3
V
Unsafe (US)
-0.3 to VCC +0.5
V
Storage Temperature
Input Voltages
Write Current (We)
VEE -2 to + 0.3
V
VEE -0.3 to + 0.3
V
Chip Enable (CE)
VEE -0.3 to VCC +0.5
V
Write Select (WS)
-0.3 to VCC + 0.3
V
Data (Ox, Dy)
1-2
0886
551 32R104C, 32R104CL,
32R104CM, 32R104CLM,
32R108,32R122
4-Channel Thin Film Read/Write Device
POWER SUPPLY
PARAMETER
CONDITIONS
MIN
11.5
Positive Supply Current (ICC)
Read/Write
Positive Supply Current (ICC)
Idle
Negative Supply Current (lEE)
Negative Supply Current (lEE)
NOM
MAX
UNIT
23
rnA
75 + ICE
rnA
Read/Write
70
rnA
Idle
52
rnA
LOGIC SIGNALS
PARAMETER
CONDITIONS
MIN
MAX
UNIT
Chip Enable Low voltage (VLCE)
Read/Write
0.0
0.7
V
Chip Enable High Voltage (VHCE)
Idle
VCC -1.0
VCC +0.3
V
Chip Enable Low Current (ILCE)
VCE= O.OV
-1.45
-0.47
rnA
Chip Enable High Current (IHCE1)
VCE = VCC - 1 .0
-350
Chip Enable High Current (IHCE2)
VCE = VCC + .3V
Write Select High Voltage (VHWS)
Write/ldle
Write Select Low Voltage (VLWS)
Read/Idle
Write Select High Current (IHWS)
Write/Idle, VWS = 3.8V
-100
~
+100
~
3.2
3.8
V
-0.1
0.1
V
Transition unsafe current off
0.6
3.2
rnA
Transition unsafe on
0.6
4.2
rnA
0.1
rnA
Head Select High Voltage (VHHS)
-1.12
-0.72
V
Head Select Low Voltage (VLHS)
-2.38
-1.51
V
240
~
60
~
Write, VCT = 3.5V
3.7
rnA
Read, VCT = O.OV
0.16
rnA
Idle
1.25
rnA
Write Select Low Current (ILWS)
Read/Idle, VWS = 3.8V
Head Select High Current (IHHS)
Head Select Low Current (ILHS)
Total Head Input Current
0888
NOM
Surn of all head input currents
with IWC= 0
1-3
SSI 32R104C, 32R104CL,
32R104CM, 32R104CLM,
32R108, 32R122
4-Channel Thin Film Read/Write Device
READ MODE
PARAMETER
CONDITIONS
Differential Gain
Yin = ImV p-p, OVDC,
f = 300 KHz
MIN
MAX
UNIT
Tj=22°C
28
43
VN
Tj=O°C
28
46
VN
22.2
43
VN
Tj = 110°C
Common Mode Rejection Ratio
NOM
Yin = 100 mVpp, OVDC,
5 MHz
45
dB
Power Supply Rejection Ratio
Yin = OV, f ~ 5 MHz t>.VCC or
t>.VEE = 100 mVpp
45
dB
Bandwidth
lin = on, Yin = 1 mVPP,
f midband = 300 KHz
30
MHz
Input Noise
Yin = OV, lin = on,
Power Bandwidth = 15 MHz
9.3
IlVRMS
Input Noise (SSI 32R1 04L)
Yin = OV, lin = on,
Power Bandwidth = 15 MHz
6.6
IlVRMS
Input Current
Yin = OV
26
flA
Differential Input Capacitance
Yin = OV
23.5
pF
Differential Input Resistance
Yin = OV
915
f~
Tj=22°C
585
Tj=O°C
565
915
Tj=110°C
585
1070
n
n
n
120
mV
-0.78
-0.32
V
0.1
mA
Output Offset Voltage
lin=O
Common Mode Output VoHage
Vin=O
Unsafe Current
Write Current = 0 mA
Write Current = -45 mA
40
DynamiC Range
DC input voHage where AC
gain falls to 90% of OVDC
input value. Measured with
0.5 mVpp AC input, Tj = 30°C
2.0
mVp
Channel Separation
Yin = 1 mVpp, OVDC,
f = 5 MHz 3 channels driven
40
dB
1-4
45
mA
0888
SSI 32R104C, 32R104CL,
32R104CM, 32R104CLM,
32R108,32R122
4-Channel Thin Film Read/Write Device
WRITE MODE
PARAMETER
CONDITIONS
MIN
Differential Input Voltage
0.175
Single Ended Input voltage
-0.68
Write Current
NOM
MAX
UNIT
V
-0.45
V
rnA
-45
Current Gain
IWC =-45 rnA
0.95
1.0
Write Current Voltage
IWC =-45 rnA
VEE+O.2!
VEE+1.0V
V
Unsafe Voltage
IUS= +45 rnA
V
4
VCC+.3
Head Center Tap Voltage
3.2
3.8
V
Differential Head Voltage
IWC = -45 rnA, Lh = 10 IlH
5.7
7.2
Vp
Single Ended Head Voltage
IWC = -45 rnA, unselected
heads at 3.5V Selected Side
of Selected Head
Current =0 rnA
0.0
0.9
V
=90mA
1.4+vee
3.7+vee
V
1.0
rnA
Unsafe Current
IWC = -30 rnA, f = 2 MHz:
Lh = 9 IlH, VUS = 5.0V - 6.3V,
15
45
rnA
Lh = 0, IWC = 45 rnA,
Rh = 00 one side of head only
15
45
rnA
2.0
mAp
2.0
rnA
MAX
UNIT
Idle to Read/write Transition Time
0.5
IlS
Read/Write to Idle Transition Time
0.5
Ils
Read to Write Transition Time
0.5
Ils
Write To Read Transition Time
0.5
IlS
50.0
ns
15
ns
15
ns
2
ns
1
IlS
5.1
IlS
Unselected Head Current
IWC = -45 rnA, f = 2 MHz,
Lh = 9.51lH
DX DY Input Current
-2.0
SWITCHING CHARACTERISTICS
PARAMETER
CONDITIONS
MIN
Head Select Switching Delay
= -45 rnA, Lh = 0, f = 5 MHz
Head Current Transition Time
Iwe
Head Current Switching Delay Time
IWC = -45 rnA, Lh
Head Current Switching Hysteresis
= 0, f = 5 MHz
Iwe = -45 rnA, Lh = 0, f = 5 MHz
Data rise and fall time :s 1 nSec
Unsafe Switching Delay Time
Delay Time
IWC = -30 rnA, f = 2 MHz;
Lh=9IlH
0.8
Lh=OIlH
0888
1-5
NOM
SSI 32R104C, 32R104CL,
32R104CM, 32R104CLM,
32R108, 32R122
4-Channel Thin Film Read/Write Device
55
~
WS.--J
OX-OY
55
we
HS1&2
==><
x=
Z
eEl
us
'\
/
55
HEAD OPEN
Z
NORMAL WRITE
/
I
L
FIGURE 1: Write Mode Timing System
PACKAGE PIN DESIGNATIONS
(TOP VIEW)
VEE
GND
HS1
GNO
VEE
WS
WS
HS1
VEE
GNO
VCC
H21
H21
vee
HS1
WS
us
H22
H22
US
vee
H21
WC
H01
H01
WC
us
H22
N/C
H02
H02
N!C
WC
H01
H31
H31
OX
H02
H32
H32
NtC
H31
NtC
OX
H11
H11
OX
OY
OY
H12
H12
OY
HS2
HS2
CE
CE
HS2
VEE
H12
VEE
GNO
GNO
VEE
GNO
CE
• MUST NOT CONNECT
32R104,32R108
24·Pln
• MUST NOT CONNECT
32R104M
24-Pln SOL
1-6
H32
H11
• MUST NOT CONNECT
32R122
22·Pln PDIP
0888
551 32R104C, 32R104CL,
32R104CM, 32R104CLM,
32R108,32R122
4-Channel Thin Film Read/Write Device
THERMAL CHARACTERISTICS: (2) ja
22-Lead
PDIP
65°C/W
24-Lead
PDIP
115°CIW
24-Lead
SOL
80°C/W
24-Lead
Flatpack
105°C/W
ORDERING INFORMATION
PART DESCRIPTION
I
ORDERING NUMBER
I
PACKAGE MARK
SSI 32R104C ReadIWrite IC
24-Lead Flatpack
24-Lead SOL
I
I
SS132R104C-F
I
SSI32R104CL-F
I
SSI32R104CL-F
I
SSI 32R1 04CM-CL
I
SSI 32R1 04CM-CL
I
SS132R108C-P
1
SS132R108C-P
I
SSI 32R122B-P
I
SSI 32R122B-P
SSI32R104C-CL
I
I
SS132R104C-F
SSI32R104C-CL
SSI32R104CL Low Noise Read/Write IC
24-Lead Flatpack
SSI 32R1 04CM Mirror Image Read/Write IC
24-Lead SOL
SSI 32R1 08 Read/Write IC
24-Lead PDIP
SSI 32R122 ReadIWrite IC
22-Lead PDIP
No responsibility is assumed by SSi for use of this product nor for any infringements of patents and trademarks or other rights of third parties
resulting from its use. No lioense is granted under any patents, patent rights or trademarks of SSi. SSi reserves the right to make changes
in specifications at any time without notice.
Silicon Systems, Inc., 14351 Myford Road, Tustin,
CA 92680 (714) 731-7110, TWX 910-595-2809
©1988 Silicon Systems, Inc.
0888
1-7
NOTES:
SSI32R114
4-Channel Thin Film
Read/Write Device
INNOVATORS IN INTEGRATION
...
------------------------~
DESCRIPTION
FEATURES
The SSI 32R114 is an integrated readlwrite circuit designed for use with non-center tapped thin fi 1m heads
in disk drive systems. Each chip controls four heads
and has three modes of operation: read, write, and idle.
The circuit contains four channels of read amplifiers
and write drivers and also has an internal write current
source.
•
Thin film head compatible perfonnance
•
Four ReadIWrlte channels
•
TTL - compatible logic levels
•
Operates on standard +5V, -5V power supplies
A current monitor (IMF) output is provided that allows
a multichip enable fault to be detected. An enabled
chip's output will produce one unit of current. An open
collector output, write select verify (WSV), will go low if
the write current source transistor is forward biased.
The circuit operates on +5 volt, and -5 von power and
is available in a 24-pin flatpack.
PIN DIAGRAM
BLOCK DIAGRAM
IMF
us
GND
VEE
vwc
cr
RiW
WSV
HS1
HS2
DIFFERENTIAL
READ
AMPLIFIERS
AND
WRITE
CURRENT
SWITCHES
WRITE
BUFFER
HEAD
SELECT
4
21
20
HOX
HOY
Wll"
H2X
WD
H2Y
US
H1X
IMF
H1Y
VCC
H3X
RD
H3Y
Ali
GND
(4-CHANNELS)
H3X
WRITE
CURRENT
SOURCE
VEE
GND
VCC
CAUTION: Use handHng procedures necessary
for a static sensitive component.
0888
1-9
551 32R114
4-Channel Thin Film
Read/Write Device
FUNCTIONAL DESCRIPTION
READ MODE
WRITE MODE
In the Read Mode, (RIW high and CE low), the circuit
functions as a differential amplifier. The amplifier input
terminals are determined by the Head Select inputs.
In the write mode (RIW and CE low) the circuit
functions as a differential current switch. The Head
Select Inputs (HS1 and HS2) determine the selected
head. The Write Data Inputs (WD, WD) determine the
polarity of the head current. The write current magnitude is adjustable by an external 1% resistor, Rx from
VWC to VCC, where:
Iw
Kw
=
HEAD SELECT TABLE
HEAD SELECTED
HS2
HS1
0
0
0
0
-0.7mA
Rx ( 1 + Rh + Rh )
Ad 1k
1
1
2
0
1
3
1
1
Where Kw = Current Gain Factor = 130 Amp-Ohms
Rh = Head plus External Wire Resistance
Rd = Damping Resistance
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, 4.75
$;
VCC
$;
5.25, -5.5
$;
VEE
$;
-4.95V, 25° $; T (junction)
$;
125°C.
ABSOLUTE MAXIMUM RATINGS
RATING
UNIT
Positive Supply Voltage, Vcc
6
V
Negative Supply Voltage, VEE
-6
V
PARAMETER
Operating Junction Temperature
25 to 125
°C
Storage Temperature
-65 to 150
°C
260
°C
-0.4 to Vee + 0.3
V
-0.4 to Vcc+ 0.3
V
-O.4Vor -2 mA to Vee + 0.3
V
Lead Temperature (Soldering, 10 sec)
Input Voltages
Head Select (HS)
Chip Enable (CE)
Read Select (RIW)
VEE to 0.3
V
-0.6 to +0.4
V
Read Data (RD, RD)
0.5 to Vcc + 0.3
V
Write Unsafe (WUS)
-0.4 to Vee + 0.3 and 20 mA
V
Write Select Verify (WSV)
-0.4 to Vee + 0.3 and 20 mA
V
Write Data (WD, WD)
Head Inputs (Read Mode)
Outputs
1-10
0888
SSI32R114
4-Channel Thin Film
Read/Write Device
ABSOLUTE MAXIMUM RATINGS (Continued)
I
I PARAMETER
I
RATING
UNIT
Outputs (Continued)
-0.4 to Vee + 0.3
V
VEE to Vee + 0.3 and 8 mA
V
Iw max = 150
mA
Current Monitor (IMF)
Current Reference (VWC)
Head Outputs (Write Mode)
POWER SUPPLY
PARAMETER
CONDITIONS
Power Dissipation
MAX
UNIT
All modes, 25 :;; Tj :;; 100
612+6.7Iw
mW
1000
563+6.7Iw
mW
:;;
MIN
NOM
Tj:;; 125 °C
Positive Supply Current
(ICC)
Idle Mode
10+ Iw/19
mA
Positive Supply Current
(ICC)
Read Mode
40+ Iw/19
mA
Positive Supply Current
(ICC)
Write Mode
38+ Iw/19
mA
Negative Supply Current
(lEE)
Idle Mode
-12-1w/19
mA
Negative Supply Current
(lEE)
Read Mode
-66-1w/19
mA
Negative Supply Current
(lEE)
Write Mode
-75-1.16Iw
mA
LOGIC SIGNALS
0888
PARAMETER
CONDITIONS
Chip Enable Low Voltage
(VLCE)
Read or Write Mode
Chip Enable High Voltage
(VHCE)
Idle Mode
2.0
V
Chip Enable Low Current
(ILCE)
VLCE= OV
-1.60
rnA
Chip Enable High Current
(IHCE)
VHCE= 2.0V
Read Select High Voltage
(VHR/W)
Read or Idle Mode
Read Select Low Voltage
(VLR/W)
Write or Idle Mode
Read Select High Current
(IHR/w)
VHR/w= 2.0V
1-11
MIN
NOM
MAX
UNIT
0.8
V
-0.3
mA
V
2.0
0.8
V
0.015
rnA
SSI32R114
4-Channel Thin Film
Read/Write Device
LOGIC SIGNALS (Continued)
PARAMETER
CONDITIONS
Read Select Low Current
(ILR/W)
VLRlW=OV
MIN
Head Select HighVoltage
(VHHS)
NOM
MAX
UNIT
-0.015
mA
2.0
V
Head Select Low Voltage
(VLHS)
0.8
V
0.25
mA
0.25
mA
Head Select High Current
(IHHS)
VHHS= VCC
Head Select Low Current
(ILHS)
VLHS= OV
WUS, WSV Low Level Voltage
ILUS=8 mA
(denotes safe condition)
0.5
V
WUS, WSV High Level Current
VHUS= 5.0V
(denotes unsafe condition)
100
J.1A
3.70
mA
0.02
mA
VCC+O.3
V
-0.1
IMF on Current
2.20
IMF off Current
IMF Voltage Range
0
READ MODE
Tests performed with 100n load resistors from RD and RD through series isolation diodes to VCC.
PARAMETER
CONDITIONS
Differential Voltage Gain
Yin = 1m Vpp, f = 300 KHz
75
Voltage Bandwidth (-3d B)
Zs < 5n, Yin = 1m Vpp
f midband = 300 KHz
45
Input Noise Voltage
Zs = on , Yin = OV,
Power Bandwidth = 15 MHz
1.1
nV"Hz
Differential Input Capacitance
Yin = OV, f = 5 MHz
65
pF
MIN
45
NOM
MAX
UNIT
170
VN
MHz
Differential Input Resistance
Vin= OV, f = 5 MHz
Input Bias Current (per side)
Yin = OV
Dynamic Range
DC input voltage where AC
gain falls to 90% of the gain
with .5m Vpp input signal
CMRR
Yin = 100m Vpp, OV DC
1 MHz ~ f ~a 10 MHz
54
dB
10 MHz ~f ~ 20 MHz
48
dB
VCC or VEE = 100m Vpp
1 MHz ~ f ~ 10 MHz
54
dB
10 MHz ~f ~ 20 MHz
36
dB
Power Supply Rejection Ratio
1-12
-3.0
96
n
0.17
mA
3.0
mV
0888
551 32R114
4-Channel Thin Film
Read/Write Device
READ MODE (Continued)
PARAMETER
CONDITIONS
Channel Separation
The three unselected
channels are driven with
Vin = 100m Vpp
1 MHz s f s 10 MHz
43
dB
10 MHz Sf s 20 MHz
37
dB
Output Offset Voltage
Output Leakage Current
MIN
NOM
-360
Idle Mode
Output Common Mode Voltage
VCC-l.l
Single Ended Output Resistance
MAX
UNIT
360
mV
0.01
mA
VCC-0.3
V
KO
10
Single Ended Output Capacitance
10
pF
MAX
UNIT
55
110
mA
-8
+8
%
0.24
1.30
WRITE MODE
PARAMETER
CONDITIONS
Current Range (Iw)
Current Tolerance
Current set to nominal value
by Rx, Rh= 70 ± 10%,
Tj = 50 oC, Rd = 590
(Iw) (Rh) Product
Differential Head Voltage Swing
Iw = 100 rnA, Lh = 0.2 JlH
Rh = 100
Unselected Head
Transient Current
Iw = 100 rnA, Lh = 0.2 JlH,
Rh = 100, Non adjacent
heads tested to minimize
external coupling effects
Head Differential Load
Resistance, Rd
MIN
3.8
48
Head Differential Load
Capacitance
0888
Differential Data Voltage,
(WD-WD)
0.20
Data Input Voltage Range
-1.87
Data Input Current (per side)
Data Input Capacitance
NOM
V
Vpp
2
mAp
97
0
30
pF
V
+0.1
V
Chip Enabled
150
JlA
Per side to GND
10
pF
1-13
SSI32R114
4-Channel Thin Film
ReadlWrite Device
SWITCHING CHARACTERISTICS
PARAMETER
CONDITIONS
MIN
Idle to ReadlWrite Transition Time
ReadlWrite to Idle Transition Time
NOM
MAX
UNIT
1.0
IlS
1.0
IlS
Read to Write Transition Time
VLCE=0.8V,
Delay to 90% of Iw
0.6
IlS
Write to Read Transition Time
VLCE = 0.8V, Delay to 90% of
20 MHz Read Signal
envelope, Iw decay to 10%
1.0
IJ.S
Head Select Switching Delay
Read or Write Mode
0.40
IJ.S
Shorted Head Current Transition
Time
Iw = 100 rnA, Lh = < O.OS IlH,
Rh=O
13
ns
Shorted Head Current Switching
Delay Time
Iw = 100 mA, Lh < O.OSIlH,
Rh = 0, measured from SO%
of input to SO% of current
change
18
ns
Head Current Switching Time
Symmetry
Iw 100 rnA, Lh = 0.2 IlH,
Rh 10n, WD & WD
transitions 2 ns, switching time
symmetry 0.2 ns
1.S
ns
WSV Transition Time
Delay from SO% of write
select swing to 90% of final
WSV voltage,
Load = 2Kn /I 20 pF
1.0
IJ.S
Unsafe to Safe Delay After
Write Data Begins (WUS)
f(data) = 10 MHz
1.0
IJ.S
Safe to Unsafe Delay, (WUS)
Non-switching write data, no
write current, or shorted head
close to chip
3.6
IJ.S
Safe to Unsafe Delay, (WUS)
Head open or head select
input open
0.6
Ils
IMF Switching Time
Delay from SO% of CE to 90010
of finallMF current
1.0
IJ.S
=
=
,
1-14
0.6
OBBB
SSI32R114
4-Channel Thin Film
Read/Write Device
PACKAGE PIN DESIGNATIONS
THERMAL CHARACTERISTICS: 0 ja
(TOP VIEW)
24-Pin Flatpack
144°CIW (Still Air)
30°CIW
GND
C:=======;--;:J
VEE
vwe
C:=====:;-J
eE
24
2
23 2 2
Ri:n
4
21
HOX
HS2
5
20
HOY
6
19
H2X
WD
7
18
H2Y
us
8
17
H1X
IMF
9
16
H1Y
WSV
3
HS1
vee
H3X
RD
c:=====:J
H3Y
Ri5
c=======:J
GND
24-Pin Flatpack
ORDERING INFORMATION
PART DESCRIPTION
ORDERING NUMBER
PACKAGE MARK
SSI32R114
24-Pin Flatpack
SSI 32R114-F
SS132R114-F
No responsibility is assumed by SSi for use of this product nor for any infringements of patents and trademarks or other rights 01 third parties
resulting from its use. No license is granted under any patents, palent rights or trademarks 01 SSi. SSi reserves the right to make changes
in specifications at any time without notice.
Silicon Systems, Inc., 14351 Myford Road, Tustin,
0888
CA 92680 (714) 731-7110, 1WX 910-595-2809
©1988 Silicon Systems, Inc.
1-15
NOTES:
SSI32R115
2, 4, 5-Channel
Read/Write Device
INNOVATORS IN INTEGRATION
---------------------------------------------August, 1988
DESCRIPTION
FEATURES
The 881 32R115 is a monolithic bipolar integrated
circuit designed for use with 8-inch and 5-1/4-inch
Winchester disk drive magnetic recording heads. The
circuit interfaces with up to five magnetic recording
heads providing the required readlwrite electronic
functions as well as various control and data protect
functions. The circuit operates on +5 volt and -5 volt (or
-5.2 volt) power and is available in a variety of packages.
•
Electrically compatible with 8-inch and 5-1/4-inch
Winchester disk drive magnetic recording heads
•
Supports up to five recording heads per circuit
•
Detects and indicates unsafe write conditions
•
On-chip current diverter eliminates the need for
external write current switching
•
Control signals are TTL compatible
•
Operates on standard +5 volt and -5 volt (or -5.2
volt) power sources
BLOCK DIAGRAM
PIN DIAGRAM
us
VCT
US
HOl
CE
H02
H11
H12
ws
H2l
H22
H3l
H32
HOl
H02
DIFFERENTIAL
READ
AMPLIFIERS
AND
WRITE
CURRENT
SWITCHES
Ox
Dy
H4l
H42
Hll
H12
DY
VEE
H2l
H22
(5-CHANNELS)
HSl
HS2
H3l
H32
HS3
H4l
H42
CAUTION: Use handling procedures necessary
for a static sensitive ccmponent.
wc
0888
1-17
5S132R115
2, 4, 5-Channel
Read/Write Device
CIRCUIT OPERATION
WRITE MODE
With both the chip enable and write select signals
activated, SSI 32R115 is switched to the write mode
and the circuit operates as a differential current switch.
The center tap head voltage (VCT) is turned on, the
unsafe circuit detector is activated, and the current
diverter is disabled. The head select signals (HS1,
HS2, HS3) select one of five differential current
switches. The selected current switch senses the
polarity of the data input signal (Dx-Dy) and gates write
current to the corresponding side of the head (HN1 or
HN2). Head overshoot voHages that occur during
normal write operation are sensed to determine safe or
unsafe head circuit conditions. The detector senses
the following unsafe conditions: no data transitions,
head open, or no write current.
tor is deactivated, and the write current diverter is enabled. The differential head input signal (HN1-HN2),
selected by the head select signals, is amplified by a
differential read amplifier and appears as a differential
output signal on the data lines (Dx, Dy).
During the read and idle modes, the on-chip current
divertercircuit prevents write current from flowing in the
head circuits. Therefore, external gating of the write
current source is not required.
TABLE 1: Head Select
READ MODE
With chip enable active and write select disabled, the
SSI 32R115 is switched to the read mode and the
circuit operates as a differential amplifier. The center
tap head voltage is turned off, the unsafe circuit detec-
HEAD
HS3
HS2
HS1
0
1
2
3
4
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
Note: Invalid Head Select input codes (5, 6 and 7) have
the effect of not selecting any heads.
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Operation above absolute maximum ratings may permanently damage the device.
PARAMETER
RATING
UNIT
V
Positive Supply Voltage, VCC
6
Negative Supply Voltage, VEE
-6
V
Write Current (IWC)
70
mA
Operating Junction Temperature
25 to 135
°C
Storage Temperature
-65 to 150
°C
260
°C
Lead Temperature (Soldering, 10 SEC)
INPUT VOLTAGES
Head Select (HS)
-0.4 to VCC +0.3
V
Unsafe lUS) (IHUS ~ 15 mAl
-0.3 to VCC +0.3
V
VEE -0.3 to 0.3
V
Write Current (WC) Voltage in read idle modes.
(Write mode must be current limited to -70 mAl
1-18
0888
'
SSI32R115
2, 4, 5-Channel
Read/Write Device
ABSOLUTE MAXIMUM RATINGS (Continued)
RATING
UNIT
VEE to 0.3
V
Chip Enable (CE)
-0.4 to VCC +0.3
V
Write Select (WS)
-0.4 to VCC +0.3
V
PARAMETER
INPUT VOLTAGES (Continued)
Data (Dx, Dy)
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MIN
NOM
MAX
UNIT
V
DC Supply Voltage
VCC
4.75
5
5.25
DC Supply Voltage
VEE
-5.5
-5
-4.75
V
Write Current (O-pk)
IWC
-30
-45
-50
mA
Head Inductance
Junction Temperature Range
LH
10
Tj
25
I!H
135
°C
MAX
UNIT
700
mW
35+ Iwe
mA
10
mA
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, recommended operating conditions apply
POWER SUPPLY
PARAMETER
CONDITIONS
Total Power Dissipation (PD)
Write Mode, IWC
Tj ~ 125 °C
Positive Supply Current (ICC)
ReadlWrite Mode
Positive Supply Current (ICC)
Idle Mode
MIN
~
NOM
45 mA,
Negative Supply Current (lEE)
ReadlWrite Mode
-65
mA
Negative Supply Current (lEE)
Idle Mode
-10
mA
LOGIC SIGNALS
0888
PARAMETER
CONDITIONS
MIN
Chip Enable Low voltage (VLCE)
Read or Write Mode
-0.3
NOM
MAX
UNIT
0.8
V
Chip Enable Low Current (ILCE)
VLCE= OV
-2.4
Chip Enable High Current (IHCE)
Idle Mode
-250
Write Select Low Voltage (VLWS)
Write or Idle Mode
-0.3
Write Select Low Current (ILWS)
VLWS=OV
-3.2
mA
Write Select High Current (IHWS)
Read or Idle Mode
-250
I!A
1-19
mA
I!A
0.8
V
551 32R115
2, 4, 5-Channel
Read/Write Device
LOGIC SIGNALS (Continued)
PARAMETER
MIN
CONDITIONS
Head Select High Level Current
(IHHS)
NOM
2.0
Head Select High Level Voltage
(VHHS)
VHHS= VCC
-0.3
Head Select Low Level Voltage
(VLHS)
MAX
UNIT
vcc
V
100
~
0.8
V
rnA
-0.6
Head Select Low Level Current
(ILHS)
VLHS= OV
Unsafe Low Level Voltage
(VLUS)·
ILUS=8 rnA
(Denotes Unsafe Condition)
0.5
V
Unsafe High Level Current
(IHUS)·
VHUS=5.0V
(Denotes Safe Condition)
100
~
'Note: Unsafe is an open collector output.
READ MODE (Tests performed with 50 load resistors from Dx and Dy to ground.)
PARAMETER
CONDITIONS
MIN
Input Common Mode Range
MAX
UNIT
-0.6
0.1
V
60
52
~
VN
Total Input Bias Current
-0.6V ~ Vin ~ 0.1V
Differential Voltage Gain
Vin = 1 mVpp, f = 300 KHz
26
Voltage Bandwidth (-3dB)
Zs ~ 100, Vin = 1 mVpp,
f midband = 300 KHz
30
Input Noise Voltage
Zs = 0, Vin = OV,
Power Bandwidth = 15 MHz
Differential Input Capacitance
Vin = 0, f = 5 MHz
Differential Input Resistance
(Internal Damping Resistor)
Vin =0, f = 300 KHz
560
Output Offset Voltage
Differential Head Current
IWC = 45 rnA, LH = 10 IlH,
f = 2 MHz
Output Common Mode Voltage
Single Ended Output Resistance
-0.4
f = 300 KHz
MHz
7
~Vrms
20
pF
1070
0
120
mV
2
mAp
-.125
V
10
Single Ended Output Capacitance
Dynamic Range
NOM
KO
10
DC input voltage where the AC gain
pF
2
mVp
50
dB
lalls to 90% 01 its OVDC input value
(Measured with 0.5 mVpp AC input
voltage)
Common Mode Rejection Ratio
Yin = 100 mVpp, OVDC, 1 = 5 MHz
1-20
0888
SSI32R115
2, 4, 5-Channel
Read/Write Device
READ MODE (Continued)
I
PARAMETER
I
I
CONDITIONS
MIN
I
NOM
I
MAX
I
UNIT
Power Supply Rejection Ratio
t.VCC or t.VEE. 100 mVpp.
t = 5 MHz
45
dB
Channel Seperation
The lour un selected channels are
45
dB
driven with Yin = 100mVpp, 1= 5MHz
Write Current Voltage
IWC=45mA
Total Head Input Current
IWC=O
-2.7
-0.5
V
200
~
MAX
UNIT
WRITE MODE
PARAMETER
CONDITIONS
MIN
Current Gain (IH/IWC)
IWC = 45 rnA. IH~
Head Current
0.95
1.0
Write Current Pin Voltage
IWC-45mA
-3.7
-1.5
Center Tap Head Voltage (VCT)
IWC =45 rnA
3.0
vee -0.5
V
Differential Head Voltage Swing
3.0 ~ VCT ~ VCC -0.5V
IWC = 45 rnA, LH = 10 ~H
5.7
7.7
V
NOM
Differential Data Voltage
(Dx- Dy)
.175
Single Ended Data Input Voltage
(Dx.Dy)
-0.9
0.1
-10
100
Data Input Current
-0.9 ~ VOx. VDy
Data Input Differential Resistance
t = 300 KHz
~
0.1
V
IWC = 45 rnA. LH = 10 ~H.
t = 2 MHz
Write Current Range
Total Head Input Current
V
~
KO
5
Data Input Capacitance
Unselected Ditt. Head Current
V
30
IWC=O
10
pF
2
mAp
50
rnA
500
~
MAX
UNIT
2
mAp
500
~
IDLE MODE
0888
PARAMETER
CONDITIONS
MIN
Write Current Pin Voltage
IWC=45mA
VEE
Differential Head Current
IWC = 45 rnA. LH = 10 ~H.
t = 2 MHz
Total Head Input Current
IWC=O
1-21
NOM
V
SSI32R115
2, 4, 5-Channel
Read/Write Device
SWITCHING CHARACTERISTICS
PARAMETER
MAX
UNIT
Idle to ReadlWrite Transition Time
CONDITIONS
MIN
NOM
0.6
~s
Read/Write to Idle Transition Time
0.6
~
Read to Write Transition Time
o S; VLCE S; O.SV
(Circuit Enabled)
0.6
~
Write to Read Transition Time
Os; VLCE S; O.SV
(Circuit Enabled)
0.6
~s
0.25
~s
Head Current Transition Time
(10% to 90% points)
IWC = 45 mA, LH = OH,
RH=On
15
ns
Head Current Switching
Delay Time (TD1 - TD2)
IWC = 45 mA, LH = OH,
RH = on, f = 5 MHz
(See Figure 1)
19
ns
Head Current Switching
Hysteresis TH = (TD1 - TD2)
IWC = 45 mA, LH = OH,
RH = on, f = 5 MHz,
(VOx - VDy) Rise Time = 2ns
(See Figure 1)
3
ns
Unsafe to Safe Delay After Write
Data Begins (TD3)
IWC=30mA,
LH = 10 ~H, f = 2 MHz
(See Figure 2A)
1.0
~s
S.O
~s
Head Select Switching Delay Time
Safe to Unsafe Delay (TD4)
LH=10~H,
1.6
f = 2 MHz, Iwe = 45 mA
(See Figure 2B)
1-22
0888
551 32R115
2, 4, 5-Channel
Read/Write Device
VDx - VDy
~~oo_~___________
7Lo%
'-"
,,
,
~TD1~
,
o mA
Differential Head Current
·L..-TD2~.
··,
.,,
o mA
FIGURE 1: Head Current Timing
50%
VDx-VDy
DATA
yo'
~TD3~
_ _ _ _ _ _ _ _----'
_VUS
.
:
,--________________ Load Capacitance = 20 pF
Pull Up Resistor = 1 K.Q
2.0V
FIGURE 2A: Unsafe to Safe Timing
Head Overshoot
Voltage (VH1. VH2)
.
;....---TD4-----~.:
VUS ---------------~
O.7~-Load Capacitance = 20 pF
~ Pull Up Resistor = 1 Kn
y
FIGURE 28: Safe to Unsafe Timing
0888
1-23
I
551 32R115
2, 4, 5-Channel
Read/Write Device
PACKAGE PIN DESIGNATIONS
(TOP VIEW)
HS1
US
US
H01
H01
H02
H02
H11
GND
CE
H12
H12
H21
H21
H22
H22
H31
H31
H32
H32
H41
NC
VEE
H42
DY
VEE
us
HS1
4321282726
H01
H02
VCT
H11
32R115-S
H12
5 CHANNELS
NC
NC
DY
12
13
14
15
16
17
18
18-Pln PDIP
22-Pln PDIP
28-Pln PLCC
24-Pin PDIP,
Flatpack, SOL
0ja
THERMAL CHARACTERISTICS'
PDIP
PDIP
PLCC
lB-lead
22-lead
2B-lead
l40·CIW
65·CIW
65·CIW
24-lead
24-lead
PDIP
24-lead
SOL
Flatpack
l15·CIW
105·CIW
BO·CIW
ORDERING INFORMATION
PART DESCRIPTION
ORDERING NUMBER
PACKAGE MARK
SSI32R115
2-Channel PDIP
SS132R115-2P
SS132R115-2P
4-Channel PDlP
SSI 32R115-4CP
SS132R115-4CP
5-Channel PDIP
SS132R115-5P
SS132R115-5P
5-Channel SOL
SS132R115-5CL
SSI 32R115-5CL
5-Channel Flatpack
SS132R115-5F
SS132R115-5F
5-Channel PLCC
SSI 32R115-5CH
SSI 32R115-5CH
No responsibility is assumed by SSi for use of this product nor for any infringements of patents and trademarks or other rights of third parties
resulting from its use. No license is granted under any patents, patent rights or trademarks of SSi. SSi reserves the right to make changes
in specifications at any time without notice.
Silicon Systems, Inc., 14351 Myford Road, Tustin,
©1988 Silicon Systems, Inc.
CA 92680 (714) 731-7110, TWX 910-595-2809
0888
SS132R117/117R
2, 4, 6 Channel
Read/Write Circuit
INTEGRATION
July, 1988
DESCRIPTION
FEATURES
The SSI 32R 117 devices are bipolar monolithic integrated circuits designed for use with center-tapped
ferrite recording heads. They provide a low noise read
path, write current control, and data protection circuitry
for as many as six channels. The SSI32R117 requires
+5V and + 12V power supplies and is available in 2, 4
or 6 channel versions with a variety of packages.
•
+5V, +12V power supplies
•
Single or multi-platter Winchester drives
•
Designed for center-tapped ferrite heads
The SSI 32R117R differs from the SSI 32R117 by
having internal damping resistors.
•
Programmable write current source
•
Available In 2, 4 or 6 channels
•
Easily multiplexed for larger systems
•
Includes write unsafe detection
•
TTL compatible control signals
BLOCK DIAGRAM
VDDl
vee
GND
WUS
VDD2
PIN DIAGRAM
veT
HOX
HOY
HSl
RiW
HS2
H1X
es
WDI
HW
VDDl
H2X
VCT
VDD2
RDX
RDY
H5X
H2Y
H2X
H5Y
H4X
H3X
WDI
RflJ
H4Y
NC
H3Y
H3X
H3Y
H4X
RDX
WUS
RDY
vec
H4Y
HSO
HSl
H5X
HS2
H5Y
we
0788
1-25
CAUTION: Use handling procedures necessary
for a static sensitive component.
SSI32R117/117R
2, 4, 6-Channel
Read/Write Circuit
CIRCUIT OPERATION
The SSI32R117functions as a write driver or as a read
amplifier for the selected head. Head selection and
mode control are described in Tables 1 & 2. Both RIW
and CS have internal pull-up resistors to prevent an accidental write condition.
WRITE MODE
The Write mode configures the SSI 32R117 as a
current switch and activates the Write Unsafe Detector. Head current is toggled between the X- and Y-side
of the recording head on the falling edgesofWDI, Write
.D~!a . Input. Note that a preceding read operation
Initializes the Write Data Flip-Flop, WDFF, to pass
current through the X-side ofthe head. The magnitude
of the write current, given by
Iw = K/Rwc, where K = Write Current Constant
is set by the external resistor, Rwc, connected from pin
WCto GND.
READ MODE
In the Read mode the SSI 32R117 is configured as a
low noise differential amplifier, the write current source
and the write unsafe detector are deactivated, and the
write data flip-flop is set. The RDX and ROY outputs
are driven by emitterfollowers and are in phase with the
"X" and "Y" head ports. They should be AC coupled to
the load.
Note that the internal write current source is deactivated for both the Read and the Chip Deselect mode.
This eliminates the need for external gating of the write
current source.
IDLE MODE
Taking CS high selects the idle mode which
switches the RDX, ROY outputs into a high impedance state and deactivates the internal write current
source. This facilitates multi-device installations by
allowing the read outputs to be wire OR'ed.
TABLE 1 : MODE SELECT
Any of the following conditions will be indicated as a
high level on the Write Unsafe, WUS, open collector
output.
cs
R/W
MODE
0
0
Write
0
1
Read
1
x
Idle
Head open
Head center tap open
WDI frequency too low
Device in Read mode
TABLE 2: HEAD SELECT
Device not selected
No write current
After the fault condition is removed, two negative
transitions on WDI are required to clear WUS.
Power dissipation in write mode may be reduced by
placing a resistor (RCT) between VDD1 & VDD2. The
optimum resistor value is 1300 x 50/1w (Iw in mA). At
low write currents «15 mA) read mode dissipation is
higher than write mode and RCT, though recommended, may not be considered necessary. In this
case VDD2 is connected directly to VDD1.
0
HS2
HS1
HSO
HEAD
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
x
None
= Low level
1-26
1 = High level
x = Don't care
0788
SSI32R117/117R
2, 4, 6-Channel
Read/Write Circuit
PIN DESCRIPTIONS
NAME
I/O
HSO-HS2
DESCRIPTION
I
Head Select: selects up to six heads
CS
I
Chip Select: a low level enables device
R/W
I
ReadlWrite: a high level selects read mode
WUS
O'
WDI
I
Write Unsafe: a high level indicates an unsafe writing condition (open collector)
Write Data In: negative transition toggles the direction of the head current
HOX-H5X
HOY-H5Y
I/O
X,Y head connections
RDX,RDY
O'
X, Y Read Data: differential read signal out
VDD1
-
VDD2
-
Positive power supply for the center tap voltage source
GND
-
Ground
WC
VCT
VCC
Write Current: used to set the magnitude of the write current
Voltage Center Tap: voltage source for head center tap
+5V
+12V
'When more than one R/W device is used, these signals can be wire OR'ed.
ABSOLUTE MAXIMUM RATINGS (Operation above absolute maximum ratings may permanently
damage the device. All voltages referenced to GND.)
PARAMETER
0788
VALUE
UNITS
VDD1
DC Supply Voltage
-0.3 to +14
VDC
VDD2
DC Supply Voltage
-0.3 to +14
VDC
VCC
DC Supply Voltage
-0.3 to +6
VDC
VIN
Digital Input Voltage Range
-0.3 to VCC + 0.3
VDC
VH
Head Port Voltage Range
-0.3 to VDD + 0.3
VDC
Vwus
WUS Port Voltage Range
-0.3 to +14
VDC
Iw
Write Current
60
mA
10
RDX, RDY Output Current
-10
mA
IveT
VCT Output Current
-60
mA
+12
mA
-65 to +150
°C
Lead Temperature, PDIP, Flatpack (10 sec soldering)
260
°C
Package Temperature, PLCC, SOL (20 sec reflow)
215
°C
Iwus
WUS Output Current
Tstg
Storage Temperature Range
1-27
551 32R117/117R
2, 4, 6-Channel
Read/Write Circuit
RECOMMENDED OPERATION CONDITIONS
PARAMETER
CONDITIONS
DC Supply Voltage
VDD1
DC Supply Voltage
VCC
Head Inductance
Lh
Damping Resistor
RD
32R117 only
MIN
NOM
MAX
UNITS
10.8
12.0
13.2
VDC
4.5
5.0
5.5
VDC
5
15
flH
500
2000
Q
125.0
RCT Resistor
RCT
135.0
Q
Write Current
Iw
25
130
50
rnA
Junction Temperature Range
Tj
25
125
°C
MAX
UNITS
Readlldle Mode
25
rnA
Write Mode
30
rnA
Idle Mode
25
rnA
Read Mode
50
rnA
Write Mode
DC CHARACTERISTICS
(Unless otherwise specified, recommended operating conditions apply.)
PARAMETER
CONDITIONS
VCC Supply Current
VDD Supply Current
Power Dissipation (Tj = + 125°C)
MIN
NOM
30+lw
rnA
Idle Mode
400
mW
Read Mode
600
mW
Write Mode, Iw = 50 rnA,
RCT= 130n
700
mW
Write Mode, Iw = 50 rnA,
RCT= on
1050
mW
Digital Inputs
Input Low Voltage
VIL
-0.3
0.8
VDC
Input High Voltage
VIH
2.0
VCC+0.3
VDC
Input Low Current
ilL
VIL = 0.8V
Input High Current
-0.4
rnA
IIH
VIH = 2.0V
100
flA
WUS Output
VOL
IOL=8mA
0.5
VDC
WUS Output
IOH
VOH =5.0V
100
Center Tap Voltage
VCT
Write Mode
6.0
VDC
Read Mode
4.0
VDC
1-28
flA
0788
SS132R117/117R
2, 4, 6-Channel
Read/Write Circuit
WRITE CHARACTERISTICS (Unless otherwise specified: recommended operating conditions apply,
IW = 45 mA, Lh = 10 IlH, Rd = 750a (32R117 only), f(Data) = 5 MHz, CL(RDX, RDY) s; 20 pF)
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNITS
Write Current Range
10
50
mA
Write Current Constant "K"
133
147
V
Differential Head Voltage Swing
8.0
V(pk)
Unselected Head Transient Current
2
mA(pk)
Differential Output Capacitance
15
pF
32R117
10K
32R117R
562
WDI Transition Frequency
WUS = low
250
Iwc to Head Current Gain
Iw/lwc
Unselected Head Leakage Current
Sum of X & Y side
leakage current
Differential Output Resistance
a
938
a
kHz
20
mNmA
85
JlA
READ CHARACTERISTICS
(Unless otherwise specified: recommended operating conditions apply, IW = 45 mA, Lh = 10 IlH,
Rd = 750a (32R117 only), f(Data) = 5 MHz, CL(RDX, RDY) s; 20 pF, Yin is referenced to VCT)
PARAMETER
CONDITIONS
Differential Voltage Gain
Yin = 1 mVpp @ 300 KHz
RL(RDX), RL(RDY) = 1 Ka
Dynamic Range
MIN
MAX
UNITS
80
120
VN
DC Input Voltage, Vi,
Where Gain Falls by 10%,
Yin = Vi + 0.5 mVpp
@300KHz
-3
+3
mV
Bandwidth (-3d B)
IZsl < 5a, Yin = 1 mVpp
30
Input Noise Voltage
BW= 15 MHz,
Lh = 0, Rh = 0
2.1
nV/.JHz
Differential Input Capacitance
f = 5 MHz
20
pF
Differential Input Resistance
32R117, f = 5 MHz
2K
32R117R, f = 5 MHz
390
Input Bias Current (per side)
Common Mode Rejection Ratio
0788
Vcm = VCT + 100 mVpp
@5MHz
1-29
50
NOM
MHz
a
810
a
45
JlA
dB
SS132R117/117R
2, 4, 6-Channel
Read/Write Circuit
READ CHARACTERISTICS (Continued)
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNITS
Power Supply Rejection Ratio
100 mVpp@ 5 MHz on
VDD1, VDD2 or VCC
45
dB
Channel Separation
Unselected Channels:
Vin=100 mVpp@ 5 MHz;
Selected Channel:
Yin =0 mVpp
45
dB
Output Offset Voltage
Common Mode Output Voltage
Read Mode
-480
+480
mV
5
7
V
Single Ended Output Resistance
f = 5 MHz
Leakage Current, RDX, ROY
RDX, ROY = 6V
Write/Idle Mode
Output Current
AC Coupled Load,
RDXto ROY
V
4.3
Writelldle Mode
-100
30
0
+100
IJ.A
2
rnA
SWITCHING CHARACTERISTICS (Unless otherwise specified: recommended operating conditions
apply, IW = 45 rnA, Lh = 10 J.1H, Rd = 7500 (32R117) only, f(Data) = 5 MHz)
PARAMETER
CONDITIONS
R/WTo Write
MIN
MAX
UNITS
Delay to 90% of
write current
1.0
J.1S
R/Wto Read
Delay to 90% of 100 mV
10 MHz read signal
envelope or to 90 %
decay of write current
1.0
J.1S
CS to Select
Delay to 90% of write
current or to 90% of
100mV 10MHz read
signal envelope
1.0
J.1s
CS to Unselect
Delay to 90% decay
of write current
1.0
J.1S
1-30
NOM
078.8
SS132R117/117R
2, 4, 6-Channel
Read/Write Circuit
SWITCHING CHARACTERISTICS (Continued)
PARAMETER
CONDITIONS
HSO - HS2 to any head
Delay to 90% of 100 mV
10 MHz read signal
envelope
WUS - Safe to Unsafe - TD1
Iw = 50 rnA
WUS - Unsafe to Safe - TD2
= 20 rnA
Head Current (Lh
= 0 ~H.
Rh
Iw
MIN
NOM
1.6
UNITS
1.0
~s
8.0
~s
1.0
~s
= On)
Prop. Delay - TD3
From 50% points
25
ns
Asymmetry
WDI has 50% duty cycle
and 1ns riselfall time
2
ns
Rise/Fall Time
10% - 90% pOints
20
ns
WDI
f--TD2 - .
+--TD1--'
wus
4
.-TD3
HEAD
CURRENT
( Ix - Iy)
FIGURE 1: Write Mode Timing Diagram
0788
MAX
1-31
SS132R117/117R
2, 4, 6-Channel
Read/Write Circuit
+12V
+5V
see Nole2
see Nole4
DRIVE
INTERFACE
SSI32B545
LOGIC
SUPPORT
L---,,-----.J---1 ~
H1Y
H2X
{
~~~CT
WRITE
DATA
SSI32P540
READ DATA PROCESSOR
SSI32Rl17
~
f-+-+------l.ff)o------+-------i
HSl
H2Y
H3X
H3Y
~+-+----~Tx~------~----~H~
H4X
>-----------1---------1 WDI
H4Y
H5X
RDX
READ
DATA
H5Y
ROY
RWC
see Nole6
NOTES
1. An external resistor, RCT, given by,
RCT = 130(55/Iw)Q, where Iw is in rnA,
can be used to limit internal power dissipation. Otherwise connect VDD2 to VDD1.
2. A ferrite bead (Ferroxcube 5659065/4A6) can be used to suppress write current overshoot and ringing
induced by flex cable parasitics.
3. Limit DC current from RDX and RDY to 100 IJ.A and load capacitance to 20 pF.
4. Damping resistors not required on 32R117R version.
5. The power bypassing capacitor must be located close to the 32R117 with its ground returned directly to
device ground with as short a path as possible.
6. To reduce ringing due to stray capacitance this resistor should be located close to the 32R117. Where this
is not desirable a series resistor can be used to buffer a long WC line.
FIGURE 2: Applications Information
1-32
0788
SSI32R117/117R
2, 4, 6-Channel
Read/Write Circuit
PACKAGE PIN DESIGNATIONS
(TOP VIEW)
cs
HSO
HS1
HS2
VDD1
WDI
WDI
VDD2
VDD1
VDD1
veT
VDD2
VDD2
veT
veT
H1Y
H1X
H1Y
H3X
H5X
WUS
H3Y
H5Y
WUS
H4X
vee
18-lead PDIP
x
c
:r
C)
I~
4
3
2
z
0
HOY 5
H1X
H1Y
H2X
H2Y
6
7
8
9
!il :r
Cii
:r
we
vee
RlW
H4Y
RDX
RDY
we
H3X
i)J 0
:r
1 28 27 26
25 VDD1
24 VDD2
23 VCT
22 H5X
21 H5Y
RiW 10
12 13 14 15 16 17 18
x
c c>0:
z
RDY
VCC
28-lead PDIP,
Flatpack, SOL
0:
0
0
>
rn
:::>
THERMAL CHARACTERISTICS
~ x
'"
3: :r :r
PACKAGE
28-lead PLCC
HSO
GND
HSl
HOX
WDI
4
H1X
H1Y
21
VDDl
2D
VDD2
H2X
H3X
H2Y
H3Y
9
16
we
NC
WUS
vee
ROY
140°CIW
22-lead POIP
65°CIW
24-lead Flatpack
110°CIW
SOL
NO
24-lead Flatpack, SOL
1-33
0ja
1S-lead POIP
28-lead POIP
VCT
32R117·4
32Rl17R-4
ROX
88
WUS
H4X
19 H4Y
Cll
RIW
RDX
20
0
HOY
H3Y
NC
22-lead PDIP
3:
32R117-6
32R117R-6
WC 11
HS1
HSO
WDI
SO°CIW
55°CIW
Flatpack
100°c!W
PLCC
65°C/W
SOL
70°CIW
SS132R117/117R
2, 4, 6.. Channel
Read/Write Circuit
ORDERING INFORMATION
PART DESCRIPTION
ORDER NO.
PKG.MARK
2-Channel PDIP
SS132R117-2P
32R117-2P
4-Channel PDIP
SSI32R117-4CP
32R117-4CP
4-Channel SOL
SS132R117-4CL
32R117-4CL
4-Channel Flatpack
SS132R117-4F
32R117-4F
6-Channel PDIP
SS132R117-6CP
32R117-6CP
6-Channel SOL
SS132R117-6CL
32R117-6CL
6-Channel Flatpack
SS132R117-6F
32R117-6F
6-Channel PLCC
SS132R117-6CH
32R117-6CH
SS132R117
SSI32R117R wHh Internal Damping Resistor
2-Channel PDIP
SSI 32R117R-2P
32R117R-2P
4-Channel PDIP
SS132R117R-4CP
32R117R-4CP
4-Channel SOL
SSI 32R 117R-4CL
32R117R-4CL
4-Channel Flatpack
SSI 32R117R-4F
32R117R-4F
6-Channel PDIP
SS132R117R-6CP
32R117R-6CP
6-Channel SOL
SSI 32R117R-6CL
32R117R-6CL
6-Channel Flatpack
S81 32R117R-6F
32R117R-6F
6-Channel PLCC
881 32R117R-6CH
32R 117R-6CH
No responsibility is assumed by SSi for use of this product nor for any infringements of patents and trademarks or other rights of third parties
resulting from its use. No license is granted under any patents, patent rights or trademarks of SSi. SSi reserves the right to make changes
in specifications at any time without notice.
14351 Myford Road, Tustin, CA 92680
©1988 Silicon Systems, Inc.
(714) 731-7110, TWX 910-595-2809
0788
SS132R117A/117AR
2, 4, 6 Channel
Read/Write Circuit
INTEGRATION
August, 1988
DESCRIPTION
FEATURES
The SSI32R117A devices are bipolar monolithic integrated circuits designed for use with center-tapped
ferrite recording heads. They provide a low noise read
path, write current control, and data protection circuitry
for as many as six channels. The SSI 32R117A
requi res +5V and + 12V power supplies and is available
in 2, 4 or 6 channel versions with a variety of packages.
•
+5V, +12V power supplies
•
Single or multi-platter Winchester drives
•
Designed for center-tapped ferrite heads
•
Programmable write current source
•
Available In 2, 4 or 6 channels
•
Easily multiplexed for larger systems
The SSI32R117AR differs from the SSI32R117A by
having internal damping resistors.
•
Includes write unsafe detection
•
TTL compatible control signals
PIN DIAGRAM
BLOCK DIAGRAM
VDD1
hTI d
VCC
,"7
GND
CS
VCT
VDD2
~
«
iii
RlW
WUS
1,
WRITE
UNSAFE
DETECTOR
i)
CENTER
TAP
DRIVER
HOX
HOY
HS1
l,c
HS2
MODE
SELECT
H1X
RDX
L
ROY
L
VDD2
VCT
H2X
ii .
H2Y
T
)
HS2
H5X
H5Y
H4X
RiW
S Q
In
WDI
H1Y
H2X
MULTIPLEXER
• .• • i
i
HS1
VDD1
H1Y
I
HSO
WDI
'-r
"0
H3X
~rlJ
H3Y
H3X
NC
H3Y
ROX
wus
ROY
WRITE
CURRENT
SOURCE
H4X
«
H4Y
l
'T /
li
H5X
H5Y
I
Hi
<
I
wc
888
1-35
CAUTION:
Use handling procedures necessary
for a static sensitive component.
SS132R117A/117AR
2, 4, 6-Channel
Read/Write Circuit
CIRCUIT OPERATION
The SSI 32R117A functions as a write driver or as a
read amplifier for the selected head. Head selection
and mode control are described in Tables 1 & 2. Both
R/W and CS have internal pull-up resistors to prevent
an accidental write condition.
WRITE MODE
The Write mode configures the SSI 32R117A as a
current switch and activates the Write Unsafe Detector. Head current is toggled between the X- and Y-side
ofthe recording head on the falling edges of WDI, Write
Data Input. Note that a preceding read operation
initializes the Write Data Flip-Flop, WDFF, to pass
current through the X-side of the head. The magnitude
of the write current, given by
Iw
= KlRwc, where K = Write Current Constant
is set by the external resistor, Rwc, connected from pin
WCto GND.
READ MODE
In the Read mode the SSI32R117A is configured as a
low noise differential amplifier, the write current source
and the write unsafe detector are deactivated, and the
write data flip-flop is set. The RDX and ROY outputs
are driven by emitterfollowers and are in phase with the
"X" and ''Y'' head ports. They should be ACcoupled to
the load.
Note that the internal write current source is deactivated for both the Read and the Chip Deselect mode.
This eliminates the need for external gating of the write
current source.
IDLE MODE
Taking CS high selects the idle mode which
switches the RDX, ROY outputs into a high impedance state and deactivates the internal write current
source. This facilitates multi-device installations by
allowing the read outputs to be wire OR'ed.
TABLE 1: MODE SELECT
Any of the following conditions will be indicated as a
high level on the Write Unsafe, WUS, open collector
output.
cg
R/W
MODE
0
0
Write
Head open
0
1
Read
Head center tap open
1
x
Idle
WDI frequency too low
Device in Read mode
TABLE 2: HEAD SELECT
Device not selected
HS2
HS1
HSO
HEAD
0
0
0
0
After the fault condition is removed, two negative
transitions on WDI are required to clear WUS.
0
0
1
1
0
1
0
2
Power dissipation in write mode may be reduced by
placing a resistor (RCT) between VDD1 & VDD2. The
optimum resistor value is 1300 x 50/1w (Iw in mA). At
low write currents «15 mA) read mode dissipation is
higher than write mode and RCT, though recommended, may not be considered necessary. In this
case VDD2 is connected directly to VDD1.
0
1
1
3
1
0
0
4
1
0
1
5
1
1
x
None
No write current
0
= Low level
1-36
1 = High level
x = Don't care
08881
SSI32R117A/117AR
2, 4, 6-Channel
Read/Write Circuit
PIN DESCRIPTIONS
NAME
1/0
DESCRIPTION
HSO-HS2
I
Head Select: selects up to six heads
CS
I
Chip Select: a low level enables device
R/W
I
WUS
O·
WDI
I
ReadIWrite: a high level selects read mode
Write Unsafe: a high level indicates an unsafe writing condition (open collector)
Write Data In: negative transition toggles the direction of the head current
HOX-H5X
HOY-H5Y
1/0
X,Y head connections
RDX,RDY
O·
X, Y Read Data:
diff~rential
read signal out
Write Current: used to set the magnitude of the write current
VDD1
-
VDD2
-
Positive power supply for the center tap voltage source
GND
-
Ground
WC
VCT
VCC
Voltage Center Tap: voltage source for head center tap
+5V
+12V
·When more than one RIW device is used, these signals can be wire OR'ed.
ABSOLUTE MAXIMUM RATINGS (Operation above absolute maximum ratings may permanently
damage the device. All voltages referenced to GND.)
PARAMETER
l88
VALUE
UNITS
VDC
VDD1
DC Supply Voltage
-0.3 to +14
VDD2
DC Supply Voltage
-0.3 to +14
VOC
VCC
DC Supply Voltage
-0.3 to +6
VDC
VIN
Digital Input Voltage Range
-0.3 to VCC + 0.3
VOC
VH
Head Port Voltage Range
-0.3 to VDO + 0.3
VDC
Vwus
WUS Port Voltage Range
-0.3 to +14
VDC
Iw
Write Current
60
rnA
10
RDX, RDY Output Current
-10
rnA
IVCT
VCT Output Current
-60
rnA
Iwus
WUS Output Current
+12
rnA
Tstg
Storage Temperature Range
-65 to +150
°c
Lead Temperature PDIP, Flatpack (10 sec soldering)
260
°C
Package Temperature PlCC, SOL (20 sec reflow)
215
°C
1-37
SS132R117A1117AR
2, 4, 6-Channel
Read/Write Circuit
RECOMMENDED OPERATION CONDITIONS
PARAMETER
CONDITIONS
DC Supply VoHage
VDD1
DC Supply Voltage
VCC
Head Inductance
Lh
Damping Resistor
RD
32R117A only
MIN
NOM
MAX
UNITS
10.8
12.0
13.2
VDC
4.5
5.0
5.5
VDC
5
15
500
2000
~
0
125.0
RCT Resistor
RCT
135.0
0
Write Current
Iw
25
130
50
mA
Junction Temperature Range
Tj
25
125
°C
MAX
UNITS
DC CHARACTERISTICS
(Unless otherwise specified, recommended operating conditions apply.)
PARAMETER
CONDITIONS
VCC Supply Current
Read/Idle Mode
25
rnA
Write Mode
30
mA
Idle Mode
25
rnA
Read Mode
50
rnA
Write Mode
30+1w
mA
400
mW
VDD Supply Current
Power Dissipation (Tj = + 125°C)
MIN
NOM
Idle Mode
Read Mode
600
mW
Write Mode, Iw = 50 rnA,
RCT= 1300
700
mW
Write Mode, Iw = 50 mA,
RCT=OO
1050
mW
"
Digital Inputs
Input Low Voltage
VIL
-0.3
0.8
VDC
Input High Voltage
VIH
2.0
VCC+0.3
VDC
Input Low Current
ilL
VIL=0.8V
Input High Current
IIH
VIH =2.0V
100
~
WUS Output
VOL
IOL=8mA
0.5
VDC
WUS Output
IOH
VOH=5.0V
100
~
Center Tap Voltage
VCT
Write Mode
6.0
VDC
Read Mode
4.0
VDC
-0.4
1-38
mA
0888
SS132R117A/117AR
2, 4, 6-Channel
Read/Write Circu it
WRITE CHARACTERISTICS (Unless otherwise specified: recommended operating conditions apply,
IW = 45 mA, Lh = 10 IlH, Rd = 7500 (32R117A only), f(Data) = 5 MHz, CL(RDX, ROY) ~ 20 pF)
PARAMETER
CONDITIONS
MAX
UNITS
10
50
mA
Write Current Constant "K"
133
147
V
Differential Head Voltage Swing
8.0
Write Current Range
MIN
NOM
V(pk)
Unselected Head Transient Current
2
mA(pk)
Differential Output Capacitance
15
pF
Differential Output Resistance
32R117A
10K
32R117AR
638
WDI Transition Frequency
WUS= low
250
Iwc to Head Current Gain
Iwllwc
Unselected Head Leakage Current
Sum of X & Y side
leakage current
0
863
0
kHz
20
mA/mA
85
JlA
READ CH.ARACTERISTICS
(Unless otherwise specified: recommended operating conditions apply, IW = 45 mA, Lh = 10 IlH,
Rd = 7500 (32R117A only), f(Data) = 5 MHz, CL(RDX, ROY) ~ 20 pF, Vin is referenced to VCT)
PARAMETER
CONDITIONS
Differential Voltage Gain
Vin = 1 mVpp @ 300 KHz
RL(RDX), RL(RDY) = 1 KO
Dynamic Range
MIN
MAX
UNITS
90
110
VN
DC Input Voltage, Vi,
Where Gain Falls by 10%,
Vin = Vi + 0.5 mVpp
@300KHz
-3
+3
mV
Bandwidth (-3d8)
IZsl < 50, Vin = 1 mVpp
30
Input Noise Voltage
BW= 15 MHz,
Lh = 0, Rh = 0
1.7
nV/-#iZ
Differential Input Capacitance
f = 5 MHz
20
pF
Differential Input Resistance
32R117A, f = 5 MHz
2K
32R117AR, f = 5 MHz
450
Input Bias Current (per side)
Common Mode Rejection Ratio
388
Vcm = VCT + 100 mVpp
@5MHz
1-39
50
NOM
MHz
0
750
0
45
JlA
db
SS132R117A/117AR
2,4,6-Channel
Read/Write Circuit
READ CHARACTERISTICS (Continued)
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNITS
Power Supply Rejection Ratio
100 mVpp@ 5 MHz on
VDD1, VDD2 or VCC
45
dB
Channel Separation
Unselected Channels:
Vin=100 mVpp @ 5 MHz;
Selected Channel:
Vin=OmVpp
45
dB
Output Offset Voltage
Common Mode Output VoHage
-440
Read Mode
5
Write/Idle Mode
Single Ended Output Resistance
f = 5 MHz
Leakage Current, RDX, ROY
RDX, RDY=6V
Write/Idle Mode
Output Current
. AC Coupled Load,
RDXto ROY
+440
mV
7
V
4.3
-100
V
30
0
+100
~
2
mA
SWITCHING CHARACTERISTICS (Unless otherwise specified: recommended operating conditions
apply, IW = 45 mA, Lh = 10 ~H, Rd = 7500 (32R117A only), f(Data) = 5 MHz)
PARAMETER
CONDITIONS
RIWTo Write
MIN
NOM
MAX
UNITS
Delay to 90% of
write current
1.0
~
R/Wto Read
Delay to 90% of 100 mV
10 MHz read signal
envelope or to 90 %
decay of write current
1.0
~
CS to Select
Delay to 90% of write
current or to 90% of
100mV 10MHz read
signal envelope
1.0
~
CS to Unselect
Delay to 90% decay
of write current
1.0
~
08881
SS132R117A1117AR
2, 4, 6-Channel
Read/Write Circuit
SWITCHING CHARACTERISTICS
I
PARAMETER
,
CONDITIONS
,
,
MIN
'NOM
MAX
UNITS
1.0
f.J.s
8.0
f.J.S
HSO - HS2 to any head
Delay to 90% of 100 mV
10 MHz read signal
envelope
WUS - Safe to Unsafe - TD1
Iw = 50 rnA
WUS - Unsafe to Safe - TD2
Iw = 20 rnA
1.0
f.J.s
Prop. Delay - TD3
From 50% points
25
ns
Asymmetry
WDI has 50% duty cycle
and 1ns riselfall time
2
ns
Rise/Fall Time
10% - 90% points
20
ns
1.6
Head Current (Lh = 0 f.J.H, Rh = On)
WDI
TDl~
wus
...-TD3
HEAD
CURRENT
(Ix ·ry)
FIGURE 1: Write Mode Timing Diagram
1-41
I
551 32R117A/117AR
2, 4, 6-Channel
Read/Write Circuit
+5V
+12V
see Note 2
see Note 4
DRIVE
INTERFACE
SS1328545
LOGIC
SUPPORT
~~~~------1~
SSI32P540
READ DATA PROCESSOR
551 32R117A
HEAD
{
SELECT
WRITE
DATA
:~- - - I . L T > o - - - + - - - l H S O
:
f-:-:,:
=:=:=======:=~:~=:===========:=========:
HS2
HS1
> - - - - - - - - - - - t - - - - - - j WDI
RDX
READ
DATA
ROY
WC
GND
RWC
see Note 6
NOTES
1. An external resistor, RCT, given by,
RCT = 130(50/lw)Q, where Iw is in mA,
can be used to limit internal power dissipation. Otherwise connect VDD2 to VDD1.
2. A ferrite bead (Ferroxcube 5659065/4A6) can be used to suppress write current overshoot and ringing
induced by flex cable parasitics.
3. Limit DC current from RDX and RDY to 100 ~ and load capacitance to 20 pF.
4. Damping resistors not required on 32R117AR version.
5. The power bypassing capacitor must be located close to the 32R117A with its ground returned directly to
device ground with as short a path as possible.
6. To reduce ringing due to stray capacitance this resistor should be located close to the 32R117A. Where
this is not desirable a series resistor can be used to buffer a long WC line.
FIGURE 2: Applications Information
1-42
0888
SS132R117/117R
2, 4, 6-Channel
Read/Write Circuit
PACKAGE PIN DESIGNATIONS
(TOP VIEW)
CS
HSO
HSO
HSO
GNO
WOI
HS1
CS
VDD1
WDI
VOD2
VOO1
VCT
VDD2
VDD2
H1X
VCT
veT
H1Y
H3X
H5X
WUS
H3Y
H5Y
VCC
WUS
HOY
18-lead
CS
PDIP
x z
(!)
0
0
::t:
HOY
4
5
3
I~
2
VDD1
H4X
RNJ
H4Y
ROX
ROY
WC
H3X
NC
H3Y
ROX
WUS
ROY
vec
25
PDIP
VDD1
PDIP,
SOL
H1X
6
24
VDD2
28-lead
H1Y
7
23
veT
Flatpack,
H2X
8
22
H5X
H2Y
9
21
H5Y
RNJ
10
20
H4X
we
11
19
H4Y
32R117-6
32R117R-6
12 13 14 15 16 17 18
0
z
x 0>0
II:
II:
0
0
rJ)
:::>
> 3:
28-lead
THERMAL CHARACTERISTICS
>- x
'" ::t:'"
::t:
PACKAGE
PLCC
ell
HSO
GND
HSl
HOX
WDI
HOY
VDDl
H1X
VDD2
H1Y
VCT
H2X
H3X
H2Y
H3Y
FWl
NC
WC
RDY
140°C/W
22-lead
PDIP
65°C/W
28-lead
VCC
24-lead Flatpack,
PDIP
SQL
WUS
SOL
1-43
"ja
18-lead
24-lead Flatpaek
NC
RDX
788
HOX
vee
22-lead
28 27 26
HS2
WDI
we
Dl::t: iii
Vi Ci
::t: ::t: 3:
1
HS1
2
110°C/W
80°C/W
PDIP
55°C/W
Flatpaek
100 o e/W
PLCC
65°C/W
SOL
70°C/W
SSI32R117A/117AR
2, 4, 6-Channel
Read/Write Circuit
ORDERING INFORMATION
PART DESCRIPTION
ORDER NO.
PKG.MARK
2-Channel PDIP
SSI32R117A-2P
32R117A-2P
4-Channel PDIP
SSI32R117A-4CP
32R117A-4CP
4-Channel SOL
SS132R117A-4CL
32R117A-4CL
4~Channel
SSI32R117A
SS132R117A-4F
32R117A-4F
6-Channel PDIP
SS132R117A-6CP
32R117A-6CP
6-Channel SOL
SS132R117A-6CL
32R117A-6CL
6-Channel Flatpack
SS132R117A-6F
32R117A-6F
6-Channel PLCC
SS132R117A-6CH
32R117A-6CH
Flatpack
SSI 32R117 AR with Internal Damping Resistor
2-Channel PDIP
SS132R117AR-2P
32R117AR-2P
4-Channel PDIP
SSI32R117AR-4CP
32R117AR-4CP
4-Channel SOL
SSI32R117AR-4CL
32R117AR-4CL
4-Channel Flatpack
SSI32R117AR-4F
32R117AR-4F
6-Channel PDIP
SSI32R117AR-6CP
32R117AR-6CP
6-Channel SOL
SSI32R117AR-6CL
32R117AR-6CL
6-Channel Flatpack
SSI32R117AR-6F
32R117AR-6F
6-Channel PLCC
SSI 32R117AR-6CH
32R117AR-6CH
No responsibility is assumed by SSi for use of this product nor for any infringements 01 patents and trademarks or other rights of third parties
resulting from its use. No license is granted under any patents, patent rights or trademarks of SSi. SSi reserves the right to make changes
in specifications at any time without notice.
(714) 731-7110, TWX 910-595-2809
©1968 Silicon Systems, Inc.
0888
SSI32R188
4-Channel
Read/Write Circuit
INNOVATORS IN INTEGRATION
---------------------------------------------July, 1988
DESCRIPTION
FEATURES
The SSI 32R188 is a high-performance, bipolar
integrated read/write circuit for use with center
tapped, ferrite heads. It provides a low noise read
path, write control circuitry and data protection circuitry for 4-channels. The SSI 32R188 requires
+6.SV and -S.2V power supplies. It is available in a
24-pin flat pack.
•
•
TTL compatible control signals
•
Four head capacity
•
•
Designed for center-tapped ferrite heads
•
Easily multiplexed
Fast switching characteristics
Includes write unsafe detection
BLOCK DIAGRAM
PIN DIAGRAM
VCT
we
UNSAFE
CONDITION
DETECTOR
GNO
C::===,=JllUlJ::c~==:::J VCT
H2X
VEE
HS1
WIJS
HEAD
SELECT
HSO
HS'
21
H2Y
20
HOX
HSO
HOY
~
H3X
WRITE
WC
CURRENT
QlVERTER
RIW
MODE
CONTROL
GND
4
CENTER TAP
RIW
,7
H3Y
NlC
'6
H'X
DRIVER
READ CURRENT
SOURCE
DIFFERENTIAL
OX
READ
AMPUAERS
AND
OY
WRITE
DRIVERS
(4 CHANNELS)
HOX
VEE
H'Y
L.:::======:::::J
GNO
HOY
H1X
OX
H1Y
DY
H2X
H2Y
H3X
H3Y
CAUTION: Use handling procedures necessary for
a static sensitive component.
)788
1-45
SSI32R188
4-Channel
Read/Write Circuit
FUNCTIONAL DESCRIPTION
The SSI32R 188 has three selectable modes of operation as illustrated in Table 1. The RIW and es inputs
which determine these modes have internal resistor
pullups to prevent an accidental write condition. Depending on the mode selected, the chip performs as a
write gate or read amplifierforthe selected head. Table
2 shows proper head addressing. In the Idle mode all
inputs and outputs are in a high-impedance state,
except the we pin which is diverted to GND.
with a gain dependent on external resistors tied from
each pin to ground. The nominal values listed in this
data sheet were obtained with 500 resistors and can
be doubled by using1000 resistors. Polarity is such
that the OX output is more positive when the "X" side of
the head is mpre positive. External gating of the write
current source is not necessary because an on-chip
diverter Circuit prevents the write current from flowing
in the head circuits during the read and idle modes.
WRITE MODE
TABLE 1: Mode Select
In this mode, externally supplied write current is gated
to the "X" side of the chosen head when the OX input
is low and to the "Y" side when DY is low. The write
unsafe detector is activated when the SSI 32R188 is in
the write mode. A low on the WUS pin indicates one of
the following unsafe conditions:
cs
R/W
MODE
0
0
Write
0
1
Read
1
X
Idle
HS1
HSO
HEAD
0
0
0
• Head open or shorted
• No write current
• No write data transitions
During a normal write cycle the pin is initially low and
then goes high after the differential input makes two
transitions. Two tranSitions are also needed to clear
WUS after a fault condition.
TABLE 2: Head Select
READ MODE
The SSI 32R188 amplifies the differential signal on the
addressed head when in the read mode. The amplified
signal is output on the open-collector OX and DY pins,
1-46
0
1
1
1
0
2
1
1
3
0788
SSI32R188
4-Channel
Read/Write Circuit
PIN DESCRIPTION
I
NAME
I
TYPE
I
DESCRIPTION
HSO - HS1
I
Head Select: selects up to four heads
CS
I
Chip Select: a low level enables device
R/W
I
ReadIWrite: a high level selects Read mode
WUS
0
Write Unsafe: open collector output, low indicates unsafe condition
HOX-H3X
HOY-H3Y
I/O
X, Y head connections
DX,DY
I/O
X, Y ReadiWrite Data: differential read data inlwrite data out signal
WC
-
Write Current: extemal write current generator connected to this pin
VCT
-
Voltage Center Tap: voltage source for head center tap
VCC
-
+6.5V
VEE
GND
-5.2V
Ground
ABSOLUTE MAXIMUM RATINGS (Operation above absolute maximum ratings may permanently damage the device.)
PARAMETER
DC Supply Voltages
RATING
UNIT
VCC
7.5
VDC
VEE
-6.0
VDC
-0.3 to VCC + 0.3
VDC
Digital Input Voltage Range
Head Input (Read Mode)
-0.6 to 0.4
VDC
Head Select (HSO, HS1)
-0.4 (or -2 rnA) to VCC + 0.3
VDC
WUS Port Voltage Range
-0.4 to VCC + 0.3
VDC
-80
rnA
VCT
-80
rnA
WUS
10
rnA
-0.1 to + 0.3
VDC
6.5
-65 to + 150
VDC
°c
260
°C
Write Current (Jw)
Output Current
DX, DY Voltage
ves
Differential Voltage, IVR/W I
Storage Temperature Range (Tstg)
Lead Temperature (10 sec soldering)
0788
1-47
SSI32R188
4-Channel
Read/Write Circuit
RECOMMENDED OPERATION CONDITIONS
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNITS
DC Supply Voltage
VCC
6.2
6.5
6.8
VDC
DC Supply Voltage
VEE
-5.5
-5.2
-4.9
VDC
Head Inductance
Lh
1.5
15
I1H
Write Current
Iw
35
70
rnA
Junction Temperature Range
Tj
25
125
°C
MAX
UNITS
DC CHARACTERISTICS
(Unless otherwise specified, VCC = 6.5 ± 5%, VEE = -5.2 ± 5%, +25°C < Tj < +125°C.)
MIN
NOM
PARAMETER
CONDITIONS
VCC Supply Current
Idle Mode
35
mA
Read Mode
80
mA
Write Mbde
40+lw
mA
VEE Supply Current
Idle Mode
-20
mA
Read Mode
-75
mA
Write Mode
-30
mA
HSO, HS1, RIW, ~
Digital Inputs
Input Low Voltage
VIL
Input High Voltage
VIH
,
0.8
VDC
VDC
2.0
Head Select
Input Low Current
ilL
VIL=0.8V
-0.1
0.2
mA
Input High Current
IIH
VIH =2.0V
-0.1
0.2
mA
Input Low Current
ilL
VIL=0.8V
-1.6
-0.1
mA
Input High Current
IIH
VIH =2.0V
-1.4
-0.1
mA
WUS Output
VOL
IOL=8mA
0.5
VDC
WUS Output
IOH
VOH=5.0V
100
J1A
Center Tap Voltage
VCT
Read Mode
0.0
VDC
Write Mode
4.2
VDC
Chip Select & ReadlWrite
-100
1-48
0788
SSI32R188
4-Channel
Read/Write Circuit
WRITE CHARACTERISTICS (Unless otherwise specified: VCC = 6.5 ± 5%, VEE = -5.2
Iw = 70 mA, Lh = 1.8 ~H, Rd = 230Q)
PARAMETER
CONDITIONS
Write Current Range
Current Gain
Head CurrenVlwc
± 5%,
MAX
UNITS
35
70
mA
0.95
1.01
-
MIN
NOM
V(pk)
10.5
Differential Head Voltage Swing
3
mA(pk)
10
pF
5
KQ
WC Voltage
-4.5
-0.5
·V
Differential Data Input Voltage
300
Data Input Voltage Range
-0.8
Unselected Diff. Head Current
Data Input Capacitance
Per side to GND
Data Input Resistance
Data Input Current
mV
Per side
+0.1
V
100
JlA
READ CHARACTERISTICS
(Unless otherwise specified: VCC = 6.5 ± 5%, VEE = -5.2 ± 5%, Lh = 1.8 ~H, Rd = 230Q,
f(Data) = 5 MHz, RL(DX, DY) = 50Q to GND, Vin is referenced to VCT)
0788
PARAMETER
CONDITIONS
MAX
UNITS
Differential Voltage Gain
Yin =1 mVpp @ 300 KHz
25
60
VN
Dynamic Range
DC Input Voltage, Vi,
Where Gain Falls by 10%,
Yin = Vi + 0.5 mVpp
@300KHz
-2
+2
mV
Bandwidth (-3dB)
IZsl < 5Q, Yin = 1 mVpp
48
Input Noise Voltage
BW = 15 MHz, Yin = 0.0 VDC
Lh = 0, Rh = 0
2.4
nV/-YHZ
Lh = 0, Rh = 115Q per side
3.3
nV/-YHZ
Differential Input Capacitance
Yin = O.OVDC
18
pF
Differential Input Resistance
V= O.OVDC
Input Bias Current (per side)
Vin= 0.0 VDC
Common Mode Rejection Ratio
Vcm = 100 mVpp@ 12 MHz
Power Supply Rejection Ratio
100 mVpp on
MIN
NOM
MHz
KQ
1.5
100
vee or VEE
1-49
JlA
45
dB
45
dB
SSI32R188
4"Channel
Read/Write Circuit
READ CHARACTERISTICS (Continued)
CONDITIONS
PARAMETER
Unselected Channels:
Vin=100 mVpp @ 12 MHz;
Selected Channel:
Vin=OmVpp
Channel Separation
MIN
NOM
MAX
34
UNITS
dB
Input Offset Voltage
-10
+10
mV
Common Mode Output Voltage
-1.3
-0.2
V
Single Ended Output Resistance
KO
5
Single Ended Output Capacitance
WC Voltage
Total Head Input Current
IVCT
10
pF
IWC=70mA
-3.2
-0.4
VDC
IWC=O
-500
+500
IlA
SWITCHING CHARACTERISTICS (Unless otherwise specified: VCC = 6.5 ± 5%, VEE = -5.2V ± 5%,
Tj = 25°C, Iw = 70 mA, Lh = 1.8 ~H, Rd = 2300, f(Data) = 5 MHz)
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNITS
RlWToWrite
Delay to 90% of write current
0.6
~
RlWto Read
Delay to 90% of 100 mV 10 MHz read
signal envelope or to 90 % decay of
write current
0.6
~
CS to Select
De.lay to 90% of write current or to 90%
of 100mV 10MHz read signal envelope
0.6
~
CS to Unselect
Delay to 90% decay of write current
0.6
~
HSO - HS2 to any head
Delay to 90% of 100 mV 10 MHz read
signal envelope
0.25
~
WUS - Safe to Unsafe
TD1,Iw = 70mA
4.0
~
WUS - Unsafe to Safe
TD2, Iw = 35 mA
1.0
~
Head Current
Lh = 0 ~H, Rh = 250 per side
0.4
Prop. Delay
TD3, From 50% points
19
ns
Asymmetry
2 ns max input switching
2
ns
Rise/Fall Time
10% - 90% pOints
15
ns
1-50
0788
SSI32R188
4-Channel
Read/Write Circuit
Head Overshoot
Voltage (VH1. VH2)
I
I
I
I
I
I
I
I
I
I
I
I
...1111---- TD1----I~~1
_ _ _ _ _ _ _ _ _ _I_ _ _ _ _ _ _ _
I
~
Oo7V
~ Load Capacitance = 20 pF
Pull Up Resistor = 1 Kn
FIGURE 1: safe to Unsafe Timing
50%
~D_X_-~DY~__~I
I
I
I
Data
Load Capacitance = 20 pF
I+-- TD2 - + ' J t ' r - - - - - - - - -
r
!
Pull Up Resistor ~ 1 Kn
200V
FIGURE 2: Unsafe to Safe Timing
Dx-Dy
~O%
I
-------~
~50%
1'-------
0
I
I
I
!+-TD3-.!
I
Differential Head Current
I
I
OmA
II
I
I
I
I+-TD~
I
•
!
I
FIGURE 3: Head Current Timing
)788
1-51
OmA
SSI32R188
4-Channel
Read/Write Circuit
TEMPERATURE MONITORING
Two sets of series diodes are included on the chip for
junction temperature monitoring. Between both the
HSO and HS1 pads to GNO, two diodes are connected in series as shown in Figure 4.
To calibrate the diodes remove power from the
SSI 32R188, pull down on the HSO or HS1 pin with a
constant current and measure the diode forward bias
voltage as the temperature is varied. To monitor
temperature measure the diode forward bias voltage
in either read or write mode and compare to the
previously determined calibration curve.
HEAD
SELECT
HSI
0------_----1
FIGURE 4
APPLICATIONS
The circuits shown in Rgures 5, 6, and 7 are suggested for interfacing the differential OX and OY lines and
either Eel or TTL data.
Ox
Eel
Write
Data
Am
or
500
FIGURES
1-52
0766
SSI32R188
4-Channel
Read/Write Circuit
APPLICATIONS (Continued)
son
~------,
.-+----------+-------~
(3/5) CA 3127E
ECL
WIlle
Data
son
L...-+-________--*_______
~~V'II'V_--
FIGURE 6
500
(112) I SN 75110
~~----~----Dx
TTL
Write Data
~~--.---- Dy
l _______________________ _
FIGURE 7
0783
1-53
Dr
VCT
SSI32R188
4-Channel
Read/Write Circuit
PACKAGE PIN DESIGNATIONS
(TOP VIEW)
wc
VCC
VCT
GNO
2
24
23 22
H2X
VEE
3
WUS'
4
21
H2Y
HS1
5
20
HOX
HSO
6
19
HOY
cs
7
18
H3X
RHI
8
17
H3Y
N/C
9
16
H1X
OX
1011
H1Y
OY
VCC
VEE
GNO
0ja = 105°CIW
24-Pin Flatpack
ORDERING INFORMATION
PART DESCRIPTION
ORDER NO.
PKG.MARK
SSI32R188 24-Pin Flatpack
SS132R188-4F
32R188-4F
No responsibility is assumed by SSi for use of this product nor for any infringements of patents and trademarks or other rights of third parties
resulting from its use. No license is granted under any patents, patent rights or trademarks of SSi. SSi reserves the right to make changes
in specifications at any time without notice.
Silicon Systems, Inc., 14351 Myford Road, Tustin,
©1988 Silicon Systems, Inc.
CA 92680, (714) 731-7110, TWX 910-595-2809
0788
SSI 32R501 /501 R
4, 6, 8-Channel Ferrite
Read/Write Circuit
INNOVATORS IN INTEGRATION
----------------------------------------------August, 1988
DESCRIPTION
FEATURES
The SSI32R501 is a bipolar monolithic integratedcircuit designed for use with a center-tapped ferrite recording head. It provides a low noise read path, write
current control, and data protection ciruitryfor as many
as 8 channels. The SSI 32R501 requires +5V and
+ 12V power supplies and is available in a variety of
packages.
•
Single or multi-platter Winchester drives
•
Designed for center-tapped ferrite heads
•
Programmable write current source
•
Easily multiplexed for larger systems
The SSI 32R501 R performs the same function as the
SSI32R501 with the addition of internal damping resistors.
•
Includes write unsafe detection
•
TTL compatible control signals
•
1.5 nV/-YHz maximum Input noise voltage
•
+5V, + 12V power supplies
BLOCK DIAGRAM
VDD1
VCC
GND
,<::
VDD2
WUS
~
~
.~
PIN DIAGRAM
veT
.r
X
WRITE
UNSAFE
DETECTOR
ii
>.:......
1<
(
CENTER
TAP
DRIVER
RDX
Ii
RDY
>;0
WDI
i
HSO
;IiI«
WC
T iII
tn
I>
:7
"
MULTIPLEXER
H1Y
?<
)?
H2X
H2Y
"'J>"
H3Y
HSO
H3X
%~
H3Y
tt
H4X
H4Y
}
i
<• • ny<{
ii}/ ' : « /
HS1
HS2
,T
//
i
H1X
< i<
I~~~v'
HOX
HOY
::
o~~DE
[
I
:':<"
:::
H5X
C~:~~
«
SOURCE
H5Y
:<
J
i<
<
i
II
>
i
Ii
WI
HGX
HGY
W H7X
R'0
>1
J
32-LEAD SOW
H7Y
CAUTION: Use handling procedures necessary
for a static sensitive component.
0888
1-55
551 32R501 /501 R
4, 6, 8-Channel Ferrite
Read/Write Circuit
CIRCUIT OPERATION
The SSI32R501 gives the userthe abilityto address up
to eight center-tapped ferrite heads and provide write
drive or read amplification. Head selection and mode
control is accomplished using the HSn, cg and RIW
inputs as shown in Tables 1 & 2. Internal pullups are
provided for the CS & RIW inputs to force the device
into a non-writing condition if either control line is
opened accidentally.
TABLE 1: Mode Select
cg
R/W
0
0
1
0
1
X
MODE
Write
Read
Idle
TABLE 2: Head Select
• Head open
• Head center tap open
• WDI frequency too low • Device in read mode
• Device not selected
• No write current
Two negative transitions on_ WDI, after the fault is
corrected, will clear the WUS flag.
Power dissipation in write mode may be reduced by
placing a resistor (RCT) between VDD1 & VDD2. The
optimum resistor value is 1200 x 50/lw (Iw in mAl. At
low write currents «15 mAl read mode disSipation is
higher than write mode and RCT, though recommended, may not be considered necessary. In this
case VDD2 is connected directly to VDD1.
READ MODE
HS2
HS1
HSO
HEAD
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
3
4
5
0
1
6
7
o= Low level
The Write Unsafe detection circuitry monitors voltage
transitions at the selected head connections and flags
any of the following conditions as a high level on the
Write Unsafe open collector output:
1 = High level
WRITE MODE
Taking both CS and RlW low selects write mode which
configures the SSI32R501 as a current switch and activates the Write Unsafe (WUS) detector circuitry.
Write current is toggled between the X and Y side of the
selected head on each high to low transition of the
Write Data Input (WDI). Note that a preceding read
mode selection initializes the Write Data Flip-Flop,
WDFF, to pass write current through the "X" side of the
head. The zero-peak write current magnitude is programmed by an external resistor Rwc from pin WC to
GND and is given by:
Taking cg low and R/W high selects read mode which
configures the SSI 32R501 as a low noise differential
amplifier for the selected head. The RDX and ROY
outputs are driven by emitter followers and are in phase
with the "X" and "Y" head ports. These outputs should
be AC coupled to the load. The internal write current
source is gated off in read mode eliminating the need
for any external gating.
Read mode selection also initializes the Write Data
Flip-Flop (WDFF) to pass write current through the "X"
side of the head at a subsequent write mode selection.
IDLE MODE
Taking CS high selects the idle mode which switches
the RDX, ROY outputs into a high impedance state and
deactivates the internal write current source. This
facilitates multi-device installations by allowing the
read outputs to be wire OR'ed.
Iw = KlRwc, where K = Write Current Constant
1-56
0888
SSI 32R501/501 R
4, 6, a-Channel Ferrite
ReadlWrite Circuit
PIN DESCRIPTIONS
NAME
DESCRIPTION
1/0
HSO-HS2
I
Head Select
CS
I
Chip Select: a low level enables device
RIW
I
WUS
O'
WDI
Read/Write: a high level selects read mode
Write Unsafe: a high level indicates an unsafe writing condition
I
HOX-H7X
HOY-H7Y
1/0
RDX, RDY
O'
Write Data In: negative transition toggles direction of head current
X,Y head connections
X, Y Read Data: differential read signal out
WC
Write Current: used to set the magnitude of the write current
VCT
Voltage Center Tap: voltage source for head center tap
VCC
+5V
VDD1
+12V
VDD2
Positive power supply for the center tap voltage source
GND
Ground
• When more than one R/w device is used these signals can be wire OR'ed.
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS (All voltages referenced to GND. Currents into device are positive.)
PARAMETER
UNITS
DC Supply Voltage
VDD1
-0.3 to +14
VDC
DC Supply Voltage
VDD2
-0.3 to +14
VDC
DC Supply Voltage
VCC
-0.3 to +6
VDC
VIN
-0.3 to VCC + 0.3
VDC
VH
-0.3 to VDD1 + 0.3
VDC
-0.3 to +14
VDC
Digital Input Voltage Range
Head Port Voltage Range
WUS Pin Voltage Range
Vwus
Write Current Zero Peak
0888
VALUE
Iw
60
mA
Output Current
RDX, RDY 10
-10
mA
Output Current
IVCT
-60
mA
Output Current
Iwus
+12
mA
Storage Temperature Range
Tstg
-65 to 150
°C
Lead Temp. PDIP, Flatpack (10 sec Soldering)
260
°C
Package Temperature PLCC, SO (20 sec Reflow)
215
°C
1-57
551 32R501 /501 R
4, 6, a-Channel Ferrite
Read/Write Circuit
RECOMMENDED OPERATION CONDITIONS
PARAMETER
CONDITIONS
DC Supply Voltage
VDD1
DC Supply Voltage
VCC
Head Inductance
Lh
Damping Resistor
RD
MIN
NOM
MAX
UNITS
10.8
12.0
13.2
VDC
4.5
5.0
5.5
VDC
5
15
~H
32R5010nly
500
2000
n
Iw=50mA
114
126
n
120
RCT Resistor
RCT*
Write Current
Iw
22
50
mA
Junction Temperature Range
Tj
+25
+135
°C
*For Iw = 50 mAo At other Iw levels refer to Applications Information that follows this specification.
DC CHARACTERISTICS
Unless otherwise specified, recommended operating conditions apply.
POWER SUPPLY
PARAMETER
CONDITIONS
VCC Supply Current
VDD Supply Current
(sum of VDD1 and VDD2)
Power Dissipation (Tj = + 135°C)
MIN
MAX
UNITS
Read/Idle Mode
25
mA
Write Mode
30
mA
Idle Mode
25
mA
Read Mode
50
mA
Write Mode
30 + Iw
mA
Idle Mode
400
mW
Read Mode
600
mW
Write Mode, Iw = 50 mA,
RCT= on
1050
mW
Write Mode, Iw =50 mA
RCT = 120n
750
mW
1-58
NOM
0888
SSI 32R501 /501 R
4, 6, a-Channel Ferrite
Read/Write Circuit
DC CHARACTERISTICS (Continued)
DIGITAL 1/0
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNITS
VIL
Input Low Voltage
-0.3
0.8
VOC
VIH
Input High Voltage
2.0
VCC
+0.3
VOC
ilL
Input Low Current
VIL = 0.8V
-0.4
mA
IIH
Input High Current
VIH = 2.0V
85
VOL
WUS Output Low Voltage
IOL= 8 mA
0.5
~
VOC
IOH
WUS Output High Current
VOH = 5.0V
100
~
MAX
UNITS
WRITE MODE
PARAMETER
Center Tap Voltage
CONDITIONS
VCT
MIN
Write Mode
Write Current Range
Write Current Constant uK"
NOM
6.0
VOC
10
50
129
151
Iwe to Head Current Gain
mNmA
20
Unselected Head Leakage Current
ROX, ROY Common Mode
Output Voltage
Writelldle Mode
ROX, ROY Leakage
RD 3.0 < RDX, RDY < 8.0V
Write/Idle Mode
-50
PARAMETER
CONDITIONS
MIN
Center Tap Voltage
Read Mode
mA
85
~
VOC
+50
~
MAX
UNITS
4.3
READ MODE
4.0
VOC
Output Offset Voltage
Read Mode
-480
+480
~
mV
Common Mode Output Voltage
Read Mode
5
7
VOC
Input Bias Current (differential)
0888
NOM
100
1-59
551 32R501 /501 R
4, 6, a-Channel Ferrite
Read/Write Circuit
DYNAMIC CHARACTERISTICS AND TIMING
Unless otherwise specified, recommended operating conditions apply and Iw = 45 mA, Lh = 10 JlH, Rd = 7500
32R501 only, f(WDI) = 5 MHz, CL(RDX, RDY) ~ 20 pF.)
WRITE MODE
PARAMETER
CONDITIONS
Differential Head Voltage Swing
Unselected Head Transient Current
MIN
NOM
32R501
10K
32R501R
600
WUS= low
250
PARAMETER
CONDITIONS
MIN
Differential Voltage Gain
Vin = 1 mVpp @ 300 kHz,
RL(RDX), RL(RDY)
= 1 KO
Dynamic Range
WDI Transition Frequency
UNITS
2
mA(pk)
15
pF
7.5
V(pk)
5 JlH ~ Lh ~ 9.5 JlH
Differential Output Capacitance
Differential Output Resistance
MAX
0
960
0
KHz
READ MODE
MAX
UNITS
80
120
VN
DC Input Voltage, Vi,
Where Gain Falls
by 10%. Vin = Vi +
0.5 mVpp @ 300 kHz
-3
+3
mV
Bandwidth (-3d B)
IZsl < 50, Vin = 1 mVpp
30
Input Noise Voltage
BW= 15 MHz,
Lh = 0, Rh = 0
NOM
MHz
1.5
nV/..JHZ
23
pF
860
0
Differential Input Capacitance
f = 5 MHz
Differential Input Resistance
32R501, f = 5 MHz
2K
Differential Input Resistance
32R501 R, f = 5 MHz
460
Common Mode Rejection Ratio
Vcm = VCT + 100 mVpp
@5MHz
50
dB
Power Supply Rejection Ratio
100 mVpp@ 5 MHz on
VDD1, VDD2 or VCC
45
dB
Channel Separation
Unselected Channels:
Vin=100 mVpp@ 5 MHz;
Selected Channel:
Vin = 0 mVpp
45
dB
Single Ended Output Resistance
f = 5 MHz
0
30
1-60
0
0888
SSI 32R501 1501 R
4, 6, a-Channel Ferrite
Read/Write Circuit
READ MODE (Continued)
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNITS
Output Current
AC Coupled Load,
ROXto ROY
2.0
mA
External Resistance Load
AC coupled to output
per side to GNO
100
n
Center tap output impedance
o ~f~ 5 MHz
150
n
MAX
UNITS
SWITCHING CHARACTERISTICS
MIN
NOM
PARAMETER
CONDITIONS
R/WTo Write
Delay to 90% of
Write Current
600
ns
R/Wto Read
Delay to 90% of
100 mV, 10 MHz Read
Signal Envelope or
to 90% decay of
Write Current
600
ns
CS to Select
Delay to 90% of Write
Current or to 90% of
100 mV, 10 MHz Read
Signal Envelope
600
ns
CS to Unselect
Delay to 90% Decay
of Write Current
600
ns
HSO - HS2 to any head
Delay to 90% of 100 mV,
10 MHz Read Signal
Envelope
600
ns
WUS-Safe to Unsafe - TD1
Iw = 50 mA
8.0
).LS
WUS-Unsafe to Safe - TD2
Iw= 20 mA
1.0
).LS
1.6
Head Current (Lh = 0 ).LH, Rh = On)
0888
Prop. Delay - TD3
From 50% POints
30
ns
Asymmetry
WDI has 50% Duty Cycle
and 1ns Rise/Fall Time
2
ns
Rise/Fall Time
10% - 90% Points
20
ns
1-61
SSI 32R501 /501 R
4, 6, a-Channel Ferrite
Read/Write Circuit
WDI
4-TD1-+
1.-----
wus
_
TD3
HEAD
CURRENT
(Ix -Iy)
FIGURE 1: Write Mode Timing Diagram
+12V
see Note 4
see Note 2
READ
DATA
-------------------------------------------------.~I
HSn
NOTES
1.
2.
3.
An external resistor, RCT, given by; RCT. 120 (5OIIw) where Iw is the zero-peak write current in rnA. can be used
to limit internal power dissipation. Otherwise connect VOD2 to VDD1.
Damping resistors not required on 32R501 R versions.
Limit DC current from RDX and ROY to 100 vA and load capacitance to 20 pF. In muhi-chip application these
outputs can be wire-OR'ed,
4.
The power bypassing capacitor must be located close to the 32R501 with its ground returned directly to device
5.
ground, with as short a path as possible.
To reduce ringing due to stray capacitance this resistor should be located close to the 32R501. Where this is nOl:
desirable a series resistor can be used to buffer a tong we line.
Rwe
see NoteS
FIGURE 2: Applications Information
1-62
0888
SSI 32R501/501 R
4, 6, 8-Channel Ferrite
Read/Write Circuit
PACKAGE PIN DESIGNATIONS
(TOP VIEW)
GND
N/C
24
2
23
N/C'
HOX
cs
HOY
NlC'
H'X
~
RiW
HOX
3
22
HOY
4
21
WC
H1X
S
20
RDY
RfiN
H2X
WC
H2Y
ROY
H3X
ROX
RDX
H3Y
HSO
7
HSO
H4X
HS'
8
17
HS1
6
H2X
H2Y
H3X
9
16
VCC
H3Y
10
1S
WDI
VDD2
H'Y
32RS01-41
19
32RS01R-4
4
Channels 18
H1Y
VCT
GNO
11
14
13
12
WUS
VDD1
, Must remain open
H4Y
HS2
H5X
vcc
H5Y
WOI
H6X
WUS
H6Y
VOO'
H7X
VDD2
H7Y
VCT
-Must ramaln open
24-Lead SOL
32-Lead Flatpack, SOW
GNO
HoX
HOX
28
GND
NlC
HOY
2
27
N/C'
H1X
3
26
CS
N/C
NiC
1:S
H'X
H1Y
4
25
RiW
H2X
5
24
WC
H2Y
6
23
RDY
H3X
7
H3Y
8
H4X
32RS01-61 22
32RS01R-6
6
21
Channels
9
20
HS2
HSX
11
18
VCC
HSY
12
17
WDI
VCT
13
16
WUS
VDD1
'Must remain open
RDX
HaY
HSO
H4X
HS'
H4Y
HS2
H5X
vee
H5Y
WDI
H6X
wus
H6Y
NIC
NlC
NlC
NIC
VDD'
H7X
VDD2
fl7Y
VCT
*MJst remain open
28-Lead PDIP, SOL, Flatpack
0888
H3X
HS1
19
15
RDY
HSO
10
14
WC
RDX
H4Y
VDD2
RfiN
H'Y
40-Lead PDIP
1-63
SSI 32R501 /501 R
4, 6, 8-Channel Ferrite
Read/Write Circuit
PACKAGE PIN DESIGNATIONS
(TOP VIEW)
0
0
i5
;;:
Cl
>
~
>-
>
2iCl
....
;;:
18
17
16
15
14
13
12
>
Ci
UJ
~
'"J:
HS2
19
11
H5X
HS1
20
10
H4Y
9
H4X
8
H3Y
7
H3X
6
H2Y
5
H2X
HSO
21
RDX
22
RDY
23
WC
24
R1N
25
32R501-6132R501 R-6
6 Channel.
0
26
27
28
~
~
Z
Cl
Cl
2
><
0
J:
>-
~
3
4
><
>-
i
i
*Must remain open
28-Lead PLCC
~ ~ ~ Z ~
U
28
27
26
25
24
0 C'" I- >c c U "> > > J:
23
22
21
20
X
J:
"-
~
19
18
WUS
WOI
29
17
30
16
NlC
H6Y
VCC
31
15
H6X
HS2
32
14
H5Y
HSl
33
13
HSO
ROX
ROY
34
H5X
H4Y
35
11
36
10
WC
37
RiW
38
N/C
39
32R501-8132R501 R-8
12
8 Channels
H4X
H3Y
H3X
H2Y
0
40
41
42
43
~ Z fc1
~
u
44
1
H2X
3
c
4
X
>a
z £
J: ~ ~
(!)
X
>-
:r: :r:
"Must remain open
44-Lead PLCC
1-64
0888
551 32R501/501 R
4, 6, 8-Channel Ferrite
Read/Write Circuit
Oja
THERMAL CHARACTERISTICS:
24-lead
28-lead
SOL
PDIP
PLCC
SOL
Flatpack
32-lead
80°Cm
ssocm
ssocm
70°cm
100°Cm
40-lead
44-lead
FLATPACK
SOW
PDIP
PLCC
9soCm
ssocm
4soCm
so°cm
ORDERING INFORMATION
PART DESCRIPTION
SSI32RS01
4-Channel SOL
S-Channel Flatpack
S-Channel PLCC
S-Channel SOL
S-Channel PDIP
8-Channel Flatpack
8-Channel SOW
8-Channel PDIP
a-Channel PLCC
SSI32RS01R
4-Channel SOL
S-Channel Flatpack
S-Channel PLCC
S-Channel SOL
S-Channel PDIP
8-Channel Flatpack
8-Channel SOW
8-Channel PDIP
8-Channel PLCC
I
ORDER NO.
PKG.MARK
SSI 32RS01-4CL
SSI 32RS01-SF
SSI 32RS01-SCH
SSI 32RS01-SCL
SSI 32RS01-SCP
SSI 32RS01-8F
SSI 32RS01-8CW
SSI 32RS01-8CP
SSI 32RS01-8CH
32RS01-4CL
32RS01-SF
32RS01-SCH
32RS01-SCL
32RS01-SCP
32RS01-8F
32RS01-8CW
32RS01-8CP
32RS01-8CH
SSI32RS01 R-4CL
SSI 32RS01 R-SF
SSI 32RS01 R-SCH
SSI 32RS01 R-SCL
SSI 32RS01 R-SCP
SSI 32RS01 R-8F
SSI 32RS01 R-8CW
SSI 32RS01 R-8CP
SSI32RS01 R-8CH
32RS01 R-4CL
32RS01R-SF
32RS01 R-SCH
32RS01 R-SeL
32RS01 R-SCP
32RS01R-8F
32RS01 R-8CW
32RS01 R-8CP
32RS01 R-8CH
No responsibility is assumed by SSi for use of this product nor for any infringements of patents and trademarks or other rights of third parties
resulting from its use. No license is granted under any patents, patent rights or trademarks of SSi. SSi reserves the right to make changes
in specifications at any time without notice.
Silicon Systems, Inc., 14351 Myford Road, Tustin
0888
CA 92680, (714) 731-7110, TWX 910-595-2809
©1988 Silicon Systems, Inc.
1-65
NOTES:
SSI32R510Al510AR
2, 4, 6-Channel
Read/Write Device
INNOVATORSIN
I~N~T=EG~RA~J~IO~N~
________________________
July, 1988
DESCRIPTION
FEATURES
The SSI 32R510A is a bipolar monolithic integrated
circuit designed for use with a center-tapped ferrite
recording head. It provides a low noise read path, write
current control, and data protection circuitry for as
many as 6 channels. The SSI 32R51 OA requires +5V
and + 12V power supplies and is available in a variety
of packages.
• High performance:
- Read mode gain 100 VN
-Input noise 1.5 nV/..JHz max.
- Input capacitance 20 pF max.
- Write current range 10 rnA to 40 rnA
The SSI32R51 OAR performs the same function as the
SSI32R51 OA with the addition of internal 750n damping resistors.
=
•
•
•
•
•
•
•
•
=
=
=
Enhanced system write to read recovery time
Power supply fault protection
Plug compatible to the SSI32R117
Designed for center-tapped ferrite heads
Programmable write current source
Write unsafe detection
TTL compatible control signals
+5V. +12V power supplies
PIN DIAGRAM
BLOCK DIAGRAM
(6-Channel)
VDD1
VCC
,."..,.,n,~
I. i"<
/i i
GND
..,[]
WUS
,..,
WRITE
UNSAFE
DETECTOR
VDD2
VeT
~
CENTER
TAP
DRIVER
HSl
HS2
RiW
RDX
RDY
;?~
MODE
SELECT
9
.~
,
MULTI·
PLEXER
'
••••••.••• •.••••••..•.• ••••.••••
··rI' ''.'i.. /
... ...
WDI
.-
C
II:
0
0
Ul
::l
> 3:
>-
X
::t:
HSI
HOX
WDI
HOY
21
VOOI
HS1
HIX
20
VOD2
HS2
VCT
WOI
H3X
VOO1
21
2D
H4X
H2X
19 H4Y
H2Y
8
17
H3Y
VOO2
RFlI
9
16
NC
VCT
18
::t:
GNO
H5X
H5Y
22
17
HSO
'" '"
28-lead PLCC
H1Y
32R510A-4
32R510AR-4
we
NC
ROX
wus
ROY
vcc
24-lead Flatpack, SOL
THERMAL CHARACTERISTICS
PACKAGE
0ja
PACKAGE
0ja
18-lead
PDIP
140
28-lead
100
20-lead
SOL
95
PLCC
65
22-lead
PDIP
65
PDIP
55
105
SOL
70
24-lead
)788
I Flatpack
I SOL
Flatpaek
80
1-75
H5X
H2X
H5Y
H4X
RiW
H4Y
WC
H3X
NC
H3Y
ROX
WUS
ROY
vcc
28-lead PDIP,
Flatpack, SOL
SSI 32R51 OA/51 OAR
2, 4, 6-Channel
Read/Write Device
ORDERING INFORMATION
ORDER NO.
PKG.MARK
2-Channel PDIP
SSI 32R51 OA-2P
32R510A-2P
2-Channel SOL
SSI 32R51 OA-2L
32R510A-2L
4-Channel SOL
SS132R510A-4CL
32R510A-4CL
4-Channel Flatpack
SS132R510A-4F
32R510A-4F
4-Channel PDIP
SS132R510A-4CP
32R510A-4CP
6-Channel PDIP
SSI 32R51 OA-6CP
32R510A-6CP
6-Channel SOL
SS132R510A-6CL
32R510A-6CL
6-Channel Flatpack
SSI 32R51 OA-6F
32R510A-6F
6-Channel PLCC
SSI 32R51 OA-6CH
32R510A-6CH
PART DESCRIPTION
SSI32R510A
SSI32R510AR with Internal Damping Resistor
2-Channel PDIP
SS132R510AR-2P
32R510AR-2P
2-Channel SOL
SS132R510AR-2L
32R510AR-2L
4-Channel SOL
SSI32R510AR-4CL
32R510AR-4CL
4-Channel Flatpack
SSI 32R510AR-4F
32R510AR-4F
4-Channel PDIP
SSI32R510AR-4CP
32R510AR-4CP
6-Channel PDIP
SSI32R510AR-6CP
32R510AR-6CP
6-Channel SOL
SSI32R510AR-6CL
32R510AR-6CL
6-Channel Flatpack
SSI 32R510AR-6F
32R510AR-6F
6-Channel PLCC
SSI32R510AR-6CH
32R510AR-6CH
No responsibility is assumed by SSi for use of this product nor for any infringements of patents and trademarks or other rights of third parties
resulting from its use. No license is granted under any patents, patent rights or trademarks of SSi. SSi reserves the right to make changes
in specifications at any time without notice.
14351 Myford Road, Tustin, CA 92680
©1988 Silicon Systems, Inc.
(714) 731-7110, TWX 910-595-2809
0788
1-76
SS132R511/511R
4, 6, 8-Channel Ferrite
Read/Write Device
INNOVATORS IN INTEGRATION
DESCRIPTION
FEATURES
The SSI32R511 is a bipolar monolithic integrated circuit designed for use with a center-tapped ferrite recording head. The SSI32R511 offers the performance
upgrades of the SSI32R51 OA, along with the improved
pin arrangement of the SSI 32R501. It provides a low
noise read path, write current control, and data protection ciruitry for as many as 8 channels. The SSI32R511
requires +5V and + 12V powersupplies and is available
in a variety of packages.
•
The SSI 32R511 R performs the same function as the
SSI32R511 with the addition of internal 750ildamping
resistors. The SSI 32R511 M and SSI32R511 RM are
functionally equivalent to the SSI 32R511 and SSI
32R511 R however, they have the mirror image pin arrangement to simplify layout when using multiple devices.
August, 1988
•
High performance
Read mode gain 100 VIV
Input noise = 1.5 nV"IHz maximum
Input capacitance = 20 pF
Write current range = 10 mA to 40 mA
Enhanced system write to read recovery time
•
Power supply fault protection
•
Pin compatible with the SSI 32R501 /501 R
•
Designed for center-tapped ferrite heads
=
•
Programmable write current source·
•
Easily multiplexed for larger systems
•
Includes write unsafe detection
•
TTL compatible control signals
•
+5V, +12V power supplies
•
Mirror Image pin arrangements
BLOCK DIAGRAM
VOOl
vee
GNO
WUS
V002
PIN DIAGRAM
VCT
HOX
FWl
HOY
we
H1X
ROY
H1Y
ROX
H2X
H2Y
H3Y
HSO
HSl
H3X
HS2
H3Y
vee
H4X
WOI
H4Y
WUS
HSX
VDOl
HSY
VD02
H6X
VCT
HaY
H7X
H7Y
0888
32-LEADSOW
CAUTION: Use handling procedures necessary
for a static sensitive component.
1-77
SSI 32R511/511 R
4, 6, 8-Channel Ferrite
Read/Write Device
CIRCUIT OPERATION
The SSI32R511 gives the userthe ability to address up
to 8 center-tapped ferrite heads and provide write drive
or read amplification. Head selection and mode control
is accomplished using the HSn, CS and R/W inputs as
shown in tables 1 & 2. Internal pullups are provided for
the CS & R/W inputs to force the device into a nonwriting condition if either control line is opened accidentally.
TABLE 1: MODE SELECT
cs
R/W
MODE
0
0
0
1
1
X
Write
Read
Idle
The Write Unsafe detection circuitry monitors voltage
transitions at the selected head connections and flags
any of the following conditions as a high level on the
Write Unsafe open collector output:
• Head open
• Head center tap open
• WDI frequency too low· Device in read mode
• Device not selected
• No write current
Two negative transitions on WDI, after the fault is
corrected, will clear the WUS flag.
To further assure data security a voltage fault detection
circuit prevents application of write current during
power loss or power sequencing.
To enhance write to read recovery time the change in
RDX, ROY common mode voltage is minimized by
biasing these outputs to a level within the read mode
range when in write mode.
TABLE 2: HEAD SELECT
Power dissipation in write mode may be reduced by
placing a resistor (RCT) between VDD1 & VDD2. The
optimum resistor value is 1200 x 40 Ilw (Iw in rnA). At
low write currents «15 rnA) read mode dissipation is
higher than write mode and RCT, though recommended, may not be considered necessary. In this
case VDD2 is connected directly to VDD1.
HS2
HS1
HSO
HEAD
0
0
0
0
0
1
1
1
0
1
1
2
3
0
0
4
READ MODE
0
1
1
1
0
1
5
Taking CS low and R/W high selects read mode which
configures the S51 32R511 as a low noise differential
amplifier for the selected head. The RDX and ROY
outputs are driven by emitter followers and are in phase
with the "X" and "Y" head ports. These outputs should
be AC coupled to the load. The internal write current
source is gated off in read mode eliminating the need
for any external gating.
0
0
0
1
1
1
1
o = Low level
1
6
7
= High level
WRITE MODE
Taking both CS and R/W low selects write mode wh ich
configures the SSI32R511 as a current switch and activates the Write Unsafe (WUS) detector circuitry.
Write current is toggled between the X and Y side of the
selected head on each high to low transition of the
Write Data Input (WDI). Note that a preceding read
mode selection initializes the Write Data Flip-Flop,
WDFF, to pass write current through the "X" side of the
head. The zero-peak write current magnitude is programmed by an external resistor Rwc from pin WC to
GND and is given by:
Iw = KlRwc, where K = Write Current Constant
Read mode selection also initializes the Write Data
Flip-Flop (WDFF) to pass write current through the "X"
side of the head at a subsequent write mode selection.
IDLE MODE
Taking CS high selects the idle mode which switches
the RDX, ROY outputs into a high impedance state and
deactivates the internal write current source. This
facilitates multi-device installations by allowing the
read outputs to be wire OR'ed and the write current
programming resistor to be common to all devices.
1-78
0888
551 32R511/511 R
4, 6, 8-Channel Ferrite
Read/Write Device
PIN DESCRIPTIONS
I NAME
I
1/0
I DESCRIPTION
HSO-HS2
I
Head Select
CS
I
Chip Select: a low level enables device
R/W
I
WUS
O·
WDI
I
HOX-H7X
HOY-H7Y
1/0
RDX,RDY
O·
WC
.
ReadIWrite: a high level selects read mode
Write Unsafe: a high level indicates an unsafe writing condition
Write Data In: negative transition toggles direction of head current
X,Y head connections
X, Y Read Data: differential read signal out
Write Current: used to set the magnitude of the write current
+5V
VDD1
-
VDD2
-
Positive power supply for the center tap voltage source
GND
-
Ground
VCT
VCC
Voltage Center Tap: voltage source for head center tap
+12V
·When more than one R/W device is used, these signals can be wire OR'ed.
ABSOLUTE MAXIMUM RATINGS (All voltages referenced to GND. Currents into device are positive.)
PARAMETER
UNITS
VDC
DC Supply Voltage
VDD1
-0.3 to +14
DC Supply Voltage
VDD2
-0.3 to +14
VDC
DC Supply Voltage
VCC
-0.3 to +6
VDC
VIN
-0.3 to VCC + 0.3
VDC
VH
-0.3 to VDD1 + 0.3
VDC
-0.3 to +14
VDC
Digital Input Voltage Range
Head Port Voltage Range
WUS Pin Voltage Range
Vwus
Write Current Zero Peak
IW
60
mA
10
-10
mA
RDX, RDy Output Current
0888
VALUE
VCT Output Current
IveT
-60
mA
WUS Output Current
Iwus
+12
mA
Storage Temperature Range
Tstg
-65 to 150
°C
Lead Temperature PDIP, Flat Pack
(10 sec Soldering)
260
°C
Package Temperature PLCC, SO
(20 sec Reflow)
215
°C
1-79
SSI 32R511/511 R
4,6, a-Channel Ferrite
Read/Write Device
RECOMMENDED OPERATION CONDITIONS
PARAMETER
MIN
NOM
MAX
UNITS
10.8
12.0
13.2
VDC
4.5
5.0
5.5
VDC
5
15
IJ.H
32R511 only
500
2000
0
1w=40mA
114
126
0
CONDITIONS
DC Supply Voltage
VDD1
DC Supply Voltage
VCC
Head Inductance
Lh
Damping Resistor
RD
RCT Resistor
RCT-
Write Current
IW
10
40
rnA
Tj
+25
+135
°C
Junction Temperature Range
120
-For Iw = 40 rnA. At other Iw levels refer to Applications Information that follows this specification.
DC CHARACTERISTICS
(Unless otherwise specified, recommended operating conditions apply.)
POWER SUPPLY
PARAMETER
CONDITIONS
VCC Supply Current
MAX
UNITS
Read/Idle Mode
35
rnA
Write Mode
30
rnA
VDD Supply Current
Idle Mode
20
rnA
(sum of VDD1 and VDD2)
Read Mode
35
rnA
Write Mode
20 + Iw
rnA
Idle Mode
400
mW
Read Mode
600
mW
Write Mode, IW = 40 rnA,
RCT=OO
800
mW
Write Mode, IW = 40 rnA,
RCT= 1200
610
mW
Power Dissipation (Tj = + 125°C)
1-80
MIN
NOM
0888
I
551 32R511/511 R
4, 6, a-Channel Ferrite
Read/Write Device
DC CHARACTERISTICS (continued)
DIGITAL 1/0
PARAMETER
VIL
Input Low Voltage
VIH
Input High Voltage
CONDITIONS
MIN
NOM
2.0
MAX
UNITS
0.8
VDC
VCC
+0.3
VDC
ilL
Input Low Current
VIL= 0.8V
IIH
Input High Current
VIH=2.OV
-0.4
100
J.LA
VOL
WUS Output Low Voltage
IOL=8mA
0.5
VDC
IOH
WUS Output High Current
VOH =5.0V
100
J.LA
mA
WRITE MODE
Center Tap Voltage
VCT
Head Current (per side)
Write Mode
Write Mode,
~ VCC ~ 3.7V,
~ VDD1 ~ 8.7V
o
o
Write Current Range
Write Current Constant "1<"
6.0
-200
VDC
200
J.LA
10
40
mA
2.375
2.625
Iwe to Head Current Gain
mA/mA
0.99
Unselected Head Leakage Current
RDX, RDY Output Offset Voltage
Write/ldle Mode
RDX, RDY Common Mode
Output Voltage
Write/ldle Mode
RDX, RDY Leakage
RDX, RDY=6V
Write/ldle Mode
-20
85
J.LA
+20
mV
5.3
-100
VDC
100
J.LA
READ MODE
Center Tap Voltage
Read Mode
Head Current (per side)
Read or Idle Mode
O:s; VCC ~5.5V
~ VDD1 ~ 13.2V
4.0
VDC
-200
200
J.LA
mV
VDC
o
Input Offset Voltage
Read Mode
-4
45
+4
Common Mode Output Voltage
Read Mode
4.5
6.5
Input Bias Current (per side)
)888
1-81
J.LA
551 32R511/511 R
4, 6, a-Channel Ferrite
Read/Write Device
DYNAMIC CHARACTERISTICS AND TIMING
(Unless otherwise specified, recommended operating conditions apply and IW = 35 rnA, Lh = 10 IlH,
Rd = 750Q 32R511 only, f(WDI) = 5 MHz, CL(RDX, RDY) ~ 20 pF.)
WRITE MODE
PARAMETER
CONDITIONS
Differential Head Voltage Swing
MIN
NOM
MAX
7.0
UNITS
V(pk)
Unselected Head Transient Current
2
mA(pk)
Differential Output Capacitance
15
pF
Differential Output Resistance
Q
32R511
10K
32R511R
600
WUS = low
250
Differential Voltage Gain
Vin = 1 mVpp @ 300 kHz,
RL(RDX), RL(RDY)
= 1 KQ
85
115
VN
Dynamic Range
DC Input Voltage, Vi,
Where Gain Falls
by 10%. Vin = Vi +
0.5 mVpp @ 300 kHz
-3
+3
mV
Bandwidth (-3d B)
IZsl < 5Q, Vin = 1 mVpp
30
Input Noise Voltage
BW= 15 MHz,
Lh = 0, Rh = 0
1.5
nV/-vHz
20
pF
WDI Transition Frequency
960
Q
KHz
READ MODE
MHz
Differential Input Capacitance
f = 5 MHz
Differential Input Resistance
32R511, f = 5 MHz
2K
Differential Input Resistance
32R511R, f = 5 MHz
460
Common Mode Rejection Ratio
Vcm = VCT + 100 mVpp
@5MHz
50
dB
Power Supply Rejection Ratio
100 mVpp@ 5 MHz on
VDD1, VDD2 or VCC
45
dB
Channel Separation
Unselected Channels:
Vin=100 mVpp@ 5 MHz;
Selected Channel:
Vin= OmVpp
45
dB
Single Ended Output Resistance
f = 5 MHz
Output Current
AC Coupled Load,
RDXto RDY
Q
860
30
1-82
±2.1
Q
Q
rnA
0888
SSI 32R511/511 R
4, 6, a-Channel Ferrite
Read/Write Device
DYNAMIC CHARACTERISTICS AND TIMING (continued)
SWITCHING CHARACTERISTICS
MAX
UNITS
1.0
IlS
1.0
IlS
Delay to 90% of Write
Current or to 90% of
100 mY, 10 MHz Read
Signal Envelope
1.0
IlS
CS to Unselect
Delay to 90% Decay
of Write Current
1.0
Ils
HSO - HS2 to any head
Delay to 90% of 100 mV,
10 MHz Read Signal
Envelope
1.0
Ils
WUS, Safe to Unsafe - TD1
Iw = 35 rnA
8.0
IlS
WUS, Unsafe to Safe - TD2
1w=35mA
1.0
IlS
Prop. Delay - TD3
From 50% Points
25
ns
Asymmetry
WDI has 50% Duty Cycle
and 1ns Rise/Fall Time
2
ns
Rise/Fall Time
10% - 90% Points
20
ns
PARAMETER
CONDITIONS
R/WTo Write
Delay to 90% of
Write Current
R/Wto Read
Delay to 90% of
100 mY, 10 MHz Read
Signal Envelope or
to 90% decay of
Write Current
CS to Select
MIN
NOM
.
1.6
Head Current (Lh = 0 IlH, Rh = On)
WDI
wus
_ _ TD3
HEAD
CURRENT
(Ix -Iy)
FIGURE 1: WRITE MODE TIMING DIAGRAM
0888
1-83
SSI 32R511/511 R
4, 6, a-Channel Ferrite
Read/Write Device
+5V
+12V
see Note 4
~--
;;:
c
>
c'"
>
18
17
16
15
14
rn
;;:
>
C
>
on
I-
g
J:
13
12
19
32R511-6132R511 R-6
6 Channals
8
H3Y
7
H3X
WC
24
6
H2Y
Am
25
5
H2X
26
27
28
~
z
C5
Gl
Z
C
J:
0
><
2
3
J:
x
Q
4
J:
GNO
HOX
GNO
NIC
HOY
NIC
NIC
HOY
NlC
~
J:
::<
H1X
~
~
H1X
HOX
RiW
H1Y
RiW
RiW
H1Y
HOY
WC
H2X
we
we
H2X
H1X
ROY
H2Y
ROY
ROY
H2Y
H1Y
ROX
H3X
ROX
ROX
H3X
H2X
HSO
H3Y
HSO
HSO
H3Y
H2Y
HSl
H4X
HSl
HSl
H4X
H3X
vee
WDI
H4Y
HS2
HS2
H4Y
H3Y
H5X
vee
vee
H5X
VCT
WUS
H5Y
WOI
WOI
H5Y
VOO2
VOOl
Hex
WUS
WUS
Hex
H6Y
VOOl
VODl
H6Y
H7X
VDD2
VDD2
H7X
H7Y
VCT
VCT
H7Y
1-85
H4X
23
GNO
OBBB
9
22
HOX
32-LeadSOW
Mirror Image
10
RDY
28-Lead SOL
Mirror Image
32-Lead Flatpack, SOW
H5X
H4Y
ROX
28-Lead PLCC
28-Lead SOL
11
24-Lead SOL
SSI32R511/511R
4, 6, 8-Channel Ferrite
ReadlWrite Device
PACKAGE PIN DESIGNATIONS (Continued)
HOX
GNO
NIC
~ ~ ~ ~ ~
NIC
28
NIC
Zl
28
25
24
0
N
0
> >
0
0
>
:I:
~ ~
:I:
~
23
22
21
20
19
18
b
29
17
30
16
RIW
WUS
WOI
VCC
31
15
we
HS2
32
14
ROY
HS1
33
H3X
ROX
34
H3Y
HSO
35
11
38
10
39
~
H4Y
HS2
HSX
vee
HSO
ROX
ROY
WC
RIll
HSY
WOI
NIC
H6X
WUS
H6Y
NIC
HSI
NIC
NIC
VOOI
H7X
VOD2
H7Y
veT
12
8 Channels
37
39
41
43
44
~ ~ ~ ~
CI
40
NIC
13
32R511-8132R511 R-8
42
0
Z
1
2
~ ~
:I:
:I:
3
4
5
NlC
H6Y
HaX
H5Y
H5X
H4Y
H4X
H3Y
H3X
H2Y
H2X
6
x >-
~ ~ i: i:
44-Lead PLCC
4D-Lead PDIP
THERMAL CHARACTERISTICS;
0ja
24-lead
SOL
SO°C/W
2S-lead
PLCC
65°C/W
SOL
70°C/W
FLATPACK
95°C/W
SOW
55°C/W
40-lead
PDIP
45°C/W
44-lead
PLCC
60°C/W
32-lead
1-86
0888
SSI 32R511/511 R
4, 6, a-Channel Ferrite
ReadlWrite Device
ORDERING INFORMATION
I
PART DESCRIPTION
I PKG.MARK
ORDER NO.
I
SSI32R511
4-Channel SOL
SS132R511-4CL
32R511-4CL
6-Channel PLCC
SS132R511-6CH
32R511-6CH
6-Channel SOL
S5132R511-6CL
32R511-6CL
8-Channel Flat Pack
5S1 32R511-8F
32R511-SF
8-Channel SOW
5S1 32R511-SCW
32R511-SCW
S-Channel PDIP
551 32R511-SCP
32R511-SCP
8-Channel PLCC
5S132R511-SCH
32R511-SCH
4-Channel SOL
5S132R511 R-4CL
32R511 R-4CL
6-Channel PLCC
SSI 32R511 R-6CH
32R511 R-6CH
SSI32R511R
6-Channel 50L
S51 32R511R-6CL
32R511 R-6CL
S-Channel Flat Pack
551 32R511 R-SF
32R511R-SF
S-Channel SOW
5S1 32R511 R-SCW
32R511 R-SCW
S-Channel PDIP
551 32R511 R-SCP
32R511 R-SCP
a-Channel PLCC
S51 32R511 R-8CH
32R511 R-SCH
6-Channel 50L
5S1 32R511 M-6CL
32R511 M-6CL
8-Channel SOW
S51 32R511 M-SCW
32R511M-SCW
6-Channel SOL
SSI 32R511 RM-6CL
32R511 RM6CL
S-Channel SOW
SSI 32R511 RM-SCW
32R511 RM-SCW
SSI32R511M
SSI 32R511 RM
No responsibility is assumed by SSi for use of this product nor for any infringements of patents and trademarks or other rights of third parties
resulting from its use. No license is granted under any patents, patent rights or trademarks of SSi. SSi reserves the right to make changes
in specifications at any time without notice.
Silicon Systems, Inc., 14351 Myford Road, Tustin
0888
CA 92680, (714) 731-7110, TWX 910-595-2809
©1988 Silicon systems, Inc.
1-87
NOTES:
Jifkon Jz rJkmJ~
INNOVATORSIN
SSI 32R512/512R
8 & 9-Channel Thin Film
ReadlWrite Device
I~N~T~6G~RA~~~IO~N~
______________________
August 1988
DESCRIPTION
FEATURES
The SSI32R512/512R ReadlWrite devices are bipolar
monolithic integrated circuits designed for use with
two terminal thin film recording heads. They provide a
low noise read amplifier, write current control and data
protection circuitry for eight or nine channels. Power
supply fault protection is provided by disabling the write
current generator during power sequencing. System
write to read recovery time is significantly improved by
controlling the read channel common mode output
voltage shift in the write mode. They require +5V and
+12V power supplies and are available in a variety of
package configurations. A mirror image pinout option
is available to simplify flex circuit layout in multiple R/W
device applications. The SSI32R512R option provides internal 10000 damping resistors.
• High performance:
Read mode gain 150 VN
Input noise = 0.85 nV/..JHz max.
Input capacitance 40 pF max.
Write current range 10 mA to 40 mA
Head voltage swing 7 vpp
Write current rise time 9 nsec
• Enhanced system write to read recovery time
=
=
=
=
=
• Power supply fault protection
• Plug compatible to the SSI 32R501 & SSI 32R511
• Compatible with two & three terminal thin film heads
• Write unsafe detection
• +5V, +12V power supplies
• Mirror Image pinout option
PIN DIAGRAM
BLOCK DIAGRAM
VDD1
vee
GND
r
wus
VDD2
~
ROX
ROY
wo,
l~
==R
OJ
MULTIPLEXER
"""""""""""""',x
.....
H50
H51 (
H52
H3X
""""""',"""""""x
.....
HaY
l84&8l:)
HeX
II
we
:
""""""""""""""a.....
v"""""""""""',x
......
1+8&8'):0
tl
HeY
H5X
==1-..1
IT
GNO
HOY
NIC
HOY
H1X
US
H1X
GNO
HOX
H1Y
RIW
RIW
H1Y
H2X
we
we
H2X
H2Y
ROY
ROY
H2Y
H3X
ROX
ROX
H3X
H3Y
HSO
HSO
H3Y
H4X
HS1
HS1
H4X
H4Y
HS2
HS2
H4Y
H5X
vee
vee
H5X
HSY
WDI
WOI
H5Y
H6X
13
20
WUS
WUS
Hey
14
19
VDD1
VDD1
14
19
H6Y
H7X
15
18
VDD2
VDD2
15
18
H7X
Nle L16
17
-____
H7Y
H7Y " -____
16
17
~
NIC
H6X
~
HOY
H5X
HOY
il
H#B8D:O
HOX
32·LEAD SOW,
FLATPACK
32·LEADSOW
MIRROR
H7X
H7Y
CAUTION: Use handling procedures necessary
far a sialic sensitive component.
0888
1-89
SSI 32R5121512R
8 & 9-Channel Thin Film
ReadlWrite Device
CIRCUIT OPERATION
The SSI 32R512 addresses up to nine two-terminal
thin film heads providing write drive or read amplification. Head selection and mode control is accomplished
with pins HSn, es and RIW, as shown in Tables 1 & 2.
Internal resistor pullups, provided on pins CS and RIW
will force the device into a non-writing condition if either
control line is opened accidentally.
WRITE MODE
The write mode configures the SSI 32R512 as a
current switch and activates the Write Unsafe (WUS)
detection circuitry. Write current is toggled between
the X and Y direction of the selected head on each high
to low transition on pin WDI, Write Data Input.
A preceding read operation initializes the Write Data
Flip Flop (WDFF) to pass write current in the Xdirection of the head.
The magnitude of the write current (O-pk) given by:
Iw=Vwc
Rwe
where Vwc (We pin voltage) = 1.65V ± 5%, is programmed by an external resistor RWe, connected
from pin we to ground. In multiple device applications,
a single RWe resistor may be made common to all
devices. The actual head current lx, y is given by:
Ix,y=
resistor value should be chosen such that Iw Rw ~ 3.0V
for an accompanying reduction of (lw)2 Rw in power
dissipation. If a resistor is not used, VDD2 should be
connected to VDD1. Note that Rw will also provide
current limiting in the-event of a head short.
READ MODE
The read mode configures the SSI 32R512 as a low
noise differential amplifier and deactivates the write
current generator and write unsafe detection circuitry.
The RDX and RDY outputs are emitter followers and
are in phase with the "X" and "Y· head ports. These
outputs should be Ae coupled to the load. The RDX,
RDY common mode voltage is maintained in the write
mode, minimizing the transient between write mode
and read mode, substantially reducing the write to read
recovery time in the subsequent Pulse Detection circuitry.
IDLE MODE
The idle mode deactivates the internal write current
generator, the write unsafe detector and switches the
RDX, RDY outputs into a high impedance state. This
facilitates multiple device applications by enabling the
read outputs to be wire OR'ed and the write current
programming resistor to be common to all devices.
TABLE 1: MODE SELECT
Iw
1+RtvRd
"CS"
RIW
0
0
1
1
0
1
0
1
where:
Rh = head resistance + external wire resistance, and
Rd = damping resistance.
Power supply fault protection improves data security
by disabling the write current generator during a voltage fault or powersupply sequencing. Additionally, the
write unsafe detection circuitry will flag any of the
conditions listed below as a high level on the open
collector output pin, WUS. Two negative transitions on
pin WDI, after the fault is corrected, are required to
clear the WUS flag.
• WDI frequency too low
• Device not selected
TABLE 2: HEAD SELECT
HS3
HS2
HS1
HSO
HEAD
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0
1
2
3
4
5
6
7
8
• Device in read mode
• No write current
Power dissipation in Write Mode may be reduced by
placing a resistor, Rw, between VDD1 and VDD2.The
MODE
Write
Read
Idle
Idle
0_ Low level
1-90
1 _ High level
0888
SSI 32R512/512R
8 & 9-Channel Thin Film
Read/Write Device
PIN DESCRIPTIONS
NAME
TYPE
DESCRIPTION
HSO - HS3
I
Head Select
CS
I
Chip Select: a low level enables the device
R/W
I
ReadIWrite: a high level selects Read mode
WUS
O·
Write Unsafe: Open collector output, a high level indicates an unsafe writing
condition
WDI
I
Write Data In: a negative transition toggles the direction of the head current
HOX - H8X
HOY - H8Y
I/O
X, Y Head Connections: Current in the X-direction flows into the X-port
RDX,RDY
O·
X, Y Read Data: differential read data output
WC
VCC
VDD1
VDD2
GND
.
-
Write Current: used to set the magnitude of the write current
+5V Logic Circuit Supply
+12V
Positive Power Supply for Write current drivers
Ground
·When more than one RIW device is used, these signals can be wire OR'ed.
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
VALUE
UNITS
DC Supply Voltage
VDD1,2
-0.3 to +14
VDC
VCC
-0.3 to +7
VDC
Write Current
Iw
100
rnA
Digital Input Voltage
Yin
-0.3 to VCC +0.3
VDC
Head Port Voltage
VH
-0.3 to VDD2 +0.3
VDC
Vwus
-0.3 to +14
VDC
10
-10
rnA
Iwus
+12
rnA
Tstg
-65 to +150
°C
WUS Pin Voltage Range
Output Current
RDX,RDY
WUS
Storage Temperature
0888
1-91
SSI 32R512/512R
8 & 9-Channel Thin Film
Read/Write Device
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
VALUE
UNITS
VDD1
12± 10%
VDD1 - 3.0 to VDD1
VDC
DC Supply Voltage
VDD2
VCC
Tj
Operating Temperature
5± 10%
VDC
VDC
+25 to +135
°C
DC CHARACTERISTICS
Unless otherwise specified, recommended operating conditions apply.
PARAMETER
VDD1 Supply Current
CONDITIONS
Read Mode
Write Mode
Idle Mode
VDD2 Supply Current
VCC Supply Current
Read Mode
Write Mode
Idle Mode
Read Mode
Write Mode
Idle Mode
Power Dissipation (Tj = + 135°C)
Read Mode
Write Mode: Iw = 20 rnA,
VDD2 =VDD1
Write Mode: Iw = 40 rnA,
VDD1 - VDD2 = 3.0V
Idle Mode
Input Low Voltage (VIL)
Input High Voltage (VIH)
Input Low Current (ilL)
Input High Current (IHL)
VIL = 0.8v
WUS Output Low Voltage (VOL)
VDD Fault VoHage
lol=8mA
NOM
MAX
UNITS
-
34
rnA
38
14
rnA
rnA
200
IW+O.4
~
rnA
200
75
~
rnA
56
60
rnA
rnA
-
-
800
1000
mW
mW
-
-
1140
mW
-
-
500
-
-
0.8
mW
VDC
2.0
-0.4
-
VDC
100
0.5
10.0
~
VDC
VDC
4.2
VDC
-200
-
+200
~
-200
-
+200
~
-
VIH = 2.0v
8.5
VCC Fault VoHage
Head Current (HnX, HnY)
MIN
3.5
Write Mode, O~VCC ~3.5V
0~VDD1 ~.5V
Read/ldle Mode
0~VCC~.5V
rnA
0~VDD1 ~13.2V
1-92
0888
SSI 32R512/512R
8 & 9-Channel Thin Film
Read/Write Device
WRITE CHARACTERISTICS
Unless otherwise specified, recommended operating conditions apply, Iw = 20 mA, Lh = 1.0 IlH, Rh = 30Q
and f(WDI) = 5 MHz.
PARAMETER
CONDITIONS
MIN.
NOM
MAX
WC Pin Voltage (Vwc)
-
1.65±5%
-
V
Differential Head Voltage Swing
7
-
Vpp
Unselected Head Current
Differential Output Capacitance
-
-
1
25
1000
1350
mA(pk)
pF
Q
-
-
Q
-
MHz
mA
Differential Output Resistance
32R512R
WDI Transition Frequency
Write Current Range
32R512
800
4K
WUS = low
1.7
10
40
UNITS
READ CHARACTERISTICS
Unless otherwise specified, recommended operating conditions apply CL (RDX, RDY) < 20pF and
RL (RDX,RDY) = 1KQ.
PARAMETER
Differential Voltage Gain
I -1dB
Bandwidth
1-3dB
Input Noise Voltage
Differential Input Capacitance
Differential Input
I
Resistance
Dynamic Range
I
32R512R
32R512
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Channel Separation
CONDITIONS
MIN
Vin=1mVpp@ 300 kHz
125
IZsl<5Q, Vin=1 mVpp @ 300 kHz
25
IZsl<5Q, Vin=1 mVpp @ 300 kHz
BW= 15 MHz, Lh = 0, Rh = 0
45
Vin = 1 mVpp, f = 5 MHz
Vin = 1 mVpp, f = 5 MHz
Vin = 1 mVpp, f =5 MHz
DC input voltage where gain
falls to 90% of its 0 VDC value,
Vin = VDC +0.5 mVpp, f = 5 MHz
Vin = 0 VDC+ 100 mVpp @ 5 MHz
100 mVpp@ 5 MHz on VDD1
100 mVpp@ 5 MHz on VCC
Unselected channels driven
with 100 mVpp @ 5 MHz,
Vin = 0 mVpp
Output Offset Voltage
RDX, RDY Common Mode
0888
Read Mode
Output Voltage
Write Mode
Single Ended Output Resistance
f = 5 MHz
Output Current
AC Coupled Load, RDX to RDY
1-93
NOM MAX
UNITS
-
175
VN
-
MHz
-
0.62
0.85
40
390
640
-
-3
-
MHz
nV/.,fHz
-
pF
Q
Q
3
mV
54
-
-
-
dB
54
45
-
-
dB
-360
2.2
-
+360
mV
2.9
3.6
VDC
2.9
-
-
30
VDC
Q
-
mA
3.2
dB
551 32R5121512R
8 & 9-Channel Thin Film
Read/Write Device
SWITCHING CHARACTERISTICS (See Figure 1)
Unless otherwise specified, recommended operating conditions apply, Iw ='20 rnA, Lh = 1.0 IlH, Rh = 300
and f(WDI) = 5 MHz.
PARAMETER
MIN
MAX
UNITS
Delay to 90% of write current
Delay to 90% of 100mV 10MHz
Read signal envelope or to 90%
decay of write current
-
0.6
0.6
J.1S
Delay to 90% of write current or to
90% of 100mV 10MHz Read
signal envelope
Delay to 90% of write current
-
0.6
J.1S
-
0.6
IlS
Delay to 90 % of 100mV 10MHz
Read signal envelope
-
0.4
J.1S
0.6
3.6
1
J.1S
J.1S
-
32
1
ns
ns
-
9
ns
CONDITIONS
RJW
R/W to Write Mode
R/W to Read Mode
Il s
CS
CSto Select
CS to Unselect
HSn
HSO, 1, 2 to any Head
WUS
Safe to Unsafe - TD1
Unsafe to Safe - TD2
Head Current
Prop. Delay - TD3
Asymmetry
-
From 50 % points, Lh=Ollh, Rh=OO
WDI has 50 % duty cycle and
1ns riselfall time, Lh=Ollh, Rh=OO
10% - 90% pOints, Lh=Ollh, Rh=OO
Rise/Fall Time
WDI
~TD1~
Ir----
WUS
_
TD3
HEAD
CURRENT
(lx-Iy)
FIGURE 1: WRITE MODE TIMING DIAGRAM
1-94
0888
551 32R512/512R
8 & 9-Channel Thin Film
Read/Write Device
APPLICATIONS INFORMATION
The specifications, provided in the data section, account for the worst case values of each parameter taken
individually. In actual operation, the effects of worst case conditions on many parameters correlate. Tables 3 &
4 demonstrate this for several key parameters. Notice that under the conditions of worst case input noise, the
higher read back signal resulting from the higher input impedance can compensate for the higher input noise.
Accounting for this correlation in your analysis will be more representative of actual performance.
TABLE 3: KEY PARAMETERS UNDER WORST CASE INPUT NOISE CONDITIONS
PARAMETER
= 25°C
Tj
Input Noise Voltage (Max.)
Differential Input Resistance (Min.)
Tj
0.70
UNITS
0.85
nV/¥Z
539
595
1200
1500
n
n
34
36
pF
32R512R
32R512
= 135°C
Differential Input Capacitance (Max.)
TABLE 4: KEY PARAMETERS UNDER WORST CASE INPUT IMPEDANCE CONDITIONS
= 135°C
UNITS
0.58
0.71
nV/>'Hz
32R512R
391
458
32R512
643
846
n
n
38
40
pF
PARAMETER
Tj
Input Noise Voltage (Max.)
Differential Input Resistance (Min.)
Differential Input Capacitance (Max.)
0888
1-95
= 25°C
Tj
I
551 32R512/512R
8 & 9-Channel Thin Film
Read/Write Device
PACKAGE PIN DESIGNATIONS (Top View)
HOX
GND
GNO
HOY
NJC
NlC
HOY
H1X
~
CS
H1X
HOX
H1Y
ANi
ANi
H1Y
H2X
we
WC
H2X
H2Y
RDY
ROY
H2Y
H3X
ROX
ROX
H3X
H3Y
HSO
HSO
H3Y
H4X
HS1
HS1
H4X
H4Y
HS2
HS2
H4Y
HSX
VCC
vee
HSX
HSY
WDI
WOI
HSY
H6X
WUS
WUS
H6X
H6Y
VDD1
VOO1
H6Y
H7X
VD02
VOO2
H7X
H7Y
NlC
NlC
H7Y
8-Channel
32-Lead SOW
8-Channel
32-LeadSOW
Mirror
HOX
GND
GND
HOY
HS3
HS3
HOY
H1X
'OS"
'OS"
H1X
H1Y
AIW
AIW
H1Y
H2X
we
we
H2X
H2Y
RDY
ROY
H2Y
H3X
RDX
ROX
H3X
H3Y
HSO
HSO
H3Y
H4X
HS1
HS1
H4X
H4Y
HS2
HS2
H4Y
H5X
vee
vee
H5X
H5Y
WDI
WOI
H5Y
H6X
wus
WUS
H6X
H6Y
VDD1
VOO1
H6Y
H7X
VDD2
VOD2
H7X
H7Y
H6Y
HBY
H7Y
Nle
HBX
HBX
NIC
9-Channel
34-Lead SOL
HOX
9-Channel
34-Lead SOL
Mirror
1-96
0888
SSI 32R512/512R
8 & 9-Channel Thin Film
Read/Write Device
I
THERMAL CHARACTERISTICS: "ja
32-Lead SOW
34-Lead SOL
ORDERING INFORMATION
ORDER NO.
PKG.MARK
B-Channel SOW
SSI32R512-BCW
32R512-BCW
9-Channel SOL
SSI 32R512-9CL
32R512-9CL
B-Channel SOW
SS132R512R-8CW
32R512R-8CW
9-Channel SOL
SS132R512R-9CL
32R512R-9CL
B-Channel SOW
SSI32R512M-BCW
32R512M-8CW
9-Channel SOL
SS132R512M-9CL
32R512M-9CL
8-Channel SOW
SSI32R512RM-BCW
32R512RM-8CW
9-Channel SOL
SSI32R512RM-9CL
32R512RM-9CL
PART DESCRIPTION
SSI32R512 Read/write IC
SSI32R512R with Internal Damping Resistor
SSI 32R512M Mirror Image
SSI 32R512RM Mirror Image with Damping Resistor
No responsibility is assumed by SSi for use of this product nor for any infringements of patents and trademarks or other rights of third parties
resulting from its use. No license is granted under any patents, patent rights or trademarks of SSi. SSi reserves the right to make changes
;",~fi_.m~Y~.M~JIicon
Jz ~kmr
Silicon Systems, Inc., 14351 Myford Road, Tustin
CA 92680, (714) 731-7110, TWX 910-595-2809
©1988 Silicon Systems, Inc.
0888
1-97
NOTES:
SS132R514/514R
2, 4, 6-Channel
Read/Write Device
I
INNOVATORS IN _IN_T_E_G_RA_T_IO
__
N__________________________
August, 1988
DESCRIPTION
FEATURES
The SSI32R514/514R ReadlWrite devices are bipolar
monolithic integrated circuits designed for use with
center-tapped ferrite recording heads. They provide a
low noise read amplifier, write current control and data
protection circuitry for as many as six channels. The
SSI32R514R option provides internal 750n damping
resistors. Power supply fault protection is provided by
disabling the write current generator during power
sequencing. System write to read recovery time is
significantly improved by controlling the read channel
common mode output voltage shift in the write mode.
The SSI 32R514 is available in a variety of package
and channel configurations.
• High performance:
- Read mode gain 150 VN
-Input noise 1.5 nV/.JHz max.
- Input capacitance 20 pF max.
- Write current range 10 mA to 40 mA
=
•
•
•
•
•
•
•
•
=
=
=
Enhanced system write to read recovery time
Power supply fault protection
Plug compatible to the SSI32R117 & SSI32R510A
Designed for center-tapped ferrite heads
Programmable write current source
Write unsafe detection
TTL compatible control signals
+5V, +12V power supplies
BLOCK DIAGRAM
VDD1
VCC
GND
WUS
VDD2
WRITE
UNSAFE
DelECTOR
R.W~
VCT
CENTER
TAP
DRIVER
HOX
HOY
MODE
~C
H1X
RDX
H1Y
MlI.TIPLEXER
ROY
H2X
WDI
Sa
H2Y
0
H3X
H3Y
VOLTAGE
FAULT
IU~'~v'
C~R~~~
H4X
SOURCE
H4Y
HSO
H5X
HS1
H5Y
HS2
WC
CAUTION: Use handling procedures necessary
for a slatic sensitive component.
0888
1-99
SSI 32R514/514R
2, 4, 6-Channel
Read/Write Device
CIRCUIT OPERATION
The SSI 32R514 addresses up to six center-tapped
ferrite heads providing write drive or read amplification.
Head selection and mode control is accomplished with
pins HSn, CS, and RIW, as shown in Tables 1 & 2.
Internal resistor pullups, provided on pins CS and RIW,
will force the device into a non-writing condition if either
control line is opened accidentally.
TABLE 1: MODE SELECT
cs
R!W
MODE
0
0
1
0
1
X
Write
Read
Idle
TABLE 2: HEAD SELECT
HS2
HS1
HSO
HEAD
0
0
0
0
1
1
0
1
0
1
0
0
1
0
1
X
0
1
2
3
4
5
None
0
0
1
1
1
o= Low level
1 = High level
X=Don't care
WRITE MODE
The write mode configures the SSI 32R514 as a
current switch and activates the Write Unsafe (WUS)
detection circuitry. Write current is toggled between
the X and Y side of the selected head on each high to
low transition of the Write Data Input (WDI).
The magnitude of the write current (O-pk) is programmed by an external resistor RWC, connected
from pin WC to ground and is given by:
Iw= _K_
RWC
Power supply fault protection improves data security
by disabling the write current generator during a voltage fault or power supply sequencing. Additionally, the
write unsafe detection circuitry monitors voHage transitions at the selected head connections and flags any
of the conditions listed below as a high level on the
open collector output pin, WUS. Two negative transitions on pin WDI, after the fault is corrected, are
required to clear the WUS flag.
• Head open
• WDI frequency too low
• Device not selected
• Head center tap open
• Device in read mode
• No write current
To reduce internal power dissipation, an optional
external resistor, RCT, given by RCT s 130n x 40llw
(Iw in rnA), is connected between pins VDD1 and
VDD2. Otherwise connect pin VDD1 to VDD2.
To initialize the Write Data Flip Flop (WDFF) to pass
current through the X-sideofthe head, pinWDI must be
low when the previous read mode was commanded.
READ MODE
The read mode configures the SSI 32R514 as a low
noise differential amplifier and deactivates the write
current generator and write unsafe circuitry. The RDX
and RDYoutputs are emitterfollowers and are in phase
with the "X" and "Y" head ports. These outputs should
be AC coupled to the load. The RDX, RDY common
mode voltage is maintained in the write mode, minimizing the transient between write mode and read mode,
substantially reducing the write to read recovery time in
the subsequent pulse detection circuitry.
IDLE MODE
The idle mode deactivates the internal write current
generator, the write unsafe detector, and switches the
RDX, RDYoutputs into a high impedance state. This
facilitates multiple device applications by enabling the
read outputs to be wire OR'ed and the write current
programming resistor to be common to all devices.
where K is the Write Current Constant. In multiple
device applications, a single RWC resistor may be
made common to all devices.
1-100
551 32R514/514R
2, 4, 6-Channel
ReadlWrite Device
PIN DESCRIPTIONS
I
NAME
I
1/0
I
DESCRIPTION
HSO-HS2
I
Head Select
CS
I
Chip Select: a low level enables device
RIW
I
WUS
O·
WDI
I
HOX-H5X
HOY-H5Y
1/0
RDX,RDY
O·
ReadlWrite: a high level selects Read mode
Write Unsafe: a high level indicates an unsafe writing condition
Write Data In: negative transition toggles direction of head current
X,Y head connections
WC
.
Write Current: used to set the magnitude of the write current
VCT
-
Voltage Center Tap: voltage source for head center tap
VCC
-
+5V
VDD1
-
+12V
VDD2
-
Ground
GND
X, Y Read Data: differential read signal output
Positive power supply for the center-tap voltage source
·When more than one RIW device is used, these signals can be wire OR'ed.
ABSOLUTE MAXIMUM RATINGS
(All voltages referenced to GND. Currents into device are positive.)
PARAMETER
UNITS
DC Supply Voltage
VDD1
-0.3 to +14
VDC
DC Supply Voltage
VDD2
-0.3 to +14
VDC
DC Supply Voltage
VCC
-0.3 to +6
VDC
Digital Input Voltage Range
VIN
-0.3 to VCC + 0.3
VDC
Head Port Voltage Range
VH
-0.3 to VDD1 + 0.3
VDC
WUS Pin Voltage Range
Write Current (O-pk)
Vwus
-0.3 to +14
VDC
Iw
60
mA
10
-10
mA
VCT Output Current
IVCT
-60
mA
WUS Output Current
Iwus
+12
mA
Storage Temperature Range
Tstg
-65 to 150
°C
Lead Temperature PDIP,
(10 sec Soldering)
260
°C
Package Temperature PLCC,
SO (20 sec Reffow)
215
°C
RDX, RDY Output Current
0888
VALUE
1-101
I
551 32R514/514R
2, 4, 6-Channel
Read/Write Device
RECOMMENDED OPERATING CONDITIONS
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNITS
VDD1
DC Supply Voltage
10.8
12.0
13.2
VDC
VCC
DC Supply VoHage
4.5
5.0
5.5
VDC
Lh
Head Inductance
5
15
!J.H
RD
Damping Resistor
32R514 only
500
2000
n
RCT*
RCT Resistor
1w=40mA
123
137
n
Iw
Write Current (O-pk)
10
40
mA
Tj
Junction Temperature Range
+25
+135
°C
130
*For Iw = 40 mAo At other Iw levels refer to Applications Information that follows this specification.
DC CHARACTERISTICS
(Recommended operating conditions apply unless otherwise specified.)
POWER SUPPLV
PARAMETER
CONDITIONS
VCC Supply Current
MIN
MAX
UNITS
Readlldle Mode
35
mA
Write Mode
30
mA
VDD Supply Current
Idle Mode
20
mA
(sum of VDD1 and VDD2)
Read Mode
35
mA
Write Mode
20 + Iw
mA
Idle Mode
400
mW
Read Mode
600
mW
Write Mode, Iw = 40 mA,
RCT= on
800
mW
Write Mode, Iw = 40 mA,
RCT= 130n
600
mW
Power Dissipation (Tj = + 135°C)
1-102
NOM
0888
SSI 32R514/514R
2, 4, 6-Channel
Read/Write Device
I
DC CHARACTERISTICS (continued)
DIGITAL I/O
PARAMETER
CONDITIONS
VIL
Input Low Voltage
VIH
Input High Voltage
ilL
Input Low Current
VIL = 0.8V
IIH
Input High Current
VIH = 2.0V
VOL
WUS Output Low Voltage
IOH
WUS Output High Current
MIN
NOM
MAX
UNITS
0.8
VDC
2.0
VDC
-0.4
rnA
100
~
IOL=8 rnA
0.5
VDC
VOH =5.0V
100
~
WRITE MODE
VCT
Center Tap Voltage
Head Current (per side)
Write Mode
6.7
Write Mode,
o~ VCC ~ 3.7V,
o~ VDD1 ~ 8.7V
Write Current Range
Write Current Constant uK"
VDC
-200
200
~
10
40
rnA
2.375
2.625
Iwc to Head Current Gain
rnA/rnA
0.99
Unselected Head Leakage Current
85
RDX, RDY Output Offset Voltage
Write/Idle Mode
RDX, RDY Common Mode
Output Voltage
Write/Idle Mode
RDX, RDY Leakage
RDX, RDY = 6V
Write/Idle Mode
-20
+20
mV
VDC
5.3
100
-100
~
~
READ MODE
VCT
Center Tap Voltage
Head Current (per side)
4.0
Read Mode
Read or Idle Mode
-200
VDC
200
~
45
~
0~VCC~5.5V
o~ VDD1
~
13.2V
Input Bias Current (per side)
0888
Output Offset Voltage
Read Mode
-615
+615
mV
Common Mode Output Voltage
Read Mode
4.5
6.5
VDC
1-103
SSI 32R514/514R
2, 4, 6-Channel
Read/Write Device
DYNAMIC CHARACTERISTICS AND TIMING
Iw = 35 mA, Lh = 10 J,lH, Rd = 750 0 32R514 only, f(WDI) = 5 MHz, CL(RDX, RDY) ~ 20 pF. Recommended operating conditions apply unless otherwise specified.
WRITE MODE
PARAMETER
MIN
CONDITIONS
NOM
MAX
V(pk)
7.0
Differential Head VoHage Swing
UNITS
Unselected Head Transient Current
2
mA(pk)
Differential Output Capacitance
15
pF
Differential Output Resistance
WDI Transition Frequency
32R514
10K
32R514R
600
0
960
0
KHz
WUS = low
250
Differential Voltage Gain
Vin = 1 mVpp @ 300 kHz
ZL(RDX), ZL(RDY) = 1 KO
125
175
VN
Dynamic Range
DC Input VoHage, Vi,
Where Gain Falls by 10%
Vin = Vi + 0.5 mVpp
@300KHz
-2
+2
mV
Bandwidth (-3dB)
IZsl < 50, Vin = 1 mVpp
30
Input Noise Voltage
BW= 15 MHz,
Lh = 0, Rh = 0
1.5
nV/¥Z
Differential Input Capacitance
f = 5 MHz
20
pF
Differential Input Resistance
32R514, f = 5 MHz
3.2K
32R514R, f = 5 MHz
500
READ MODE
MHz
0
1000
0
Common Mode Rejection Ratio
Vcm = VCT + 100 mVpp
@5MHz
50
dB
Power Supply Rejection Ratio
100 mVpp@ 5 MHz on
VDD1, VDD2 or vce
45
dB
Channel Separation
Unselected Channels:
Vin=100 mVpp@ 5 MHz;
Selected Channel:
Vin =0 mVpp
45
dB
Single Ended Output Resistance
f = 5 MHz
Output Current
AC Coupled Load,
RDXto RDY
30
1-104
±2.1
0
rnA
OS8S
551 32R514/514R
2, 4, 6-Channel
Read/Write Device
DYNAMIC CHARACTERISTICS AND TIMING (continued)
SWITCHING CHARACTERISTICS
MAX
UNITS
Delay to 90% of
Write Current
1.0
J.LS
RJW to Read Mode
Delay to 90% of
100 mV, 10 MHz Read
Signal Envelope or
to 90% decay of
Write Current
1.0
J.LS
CSto Select
Delay to 90% of Write
Current or to 90% of
100 mV, 10 MHz Read
Signal Envelope
1.0
I1S
CS to Unselect
Delay to 90% Decay
of Write Current
1.0
I1S
HSO - HS2 to any head
Delay to 90% of 100mV
10 MHz Read Signal
Envelope
1.0
J.LS
WUS, Safe to Unsafe - TD1
Iw =35 rnA, see Figure 1
8.0
J.LS
WUS, Unsafe to Safe - TD2
Iw =35 rnA, see Figure 1
1.0
J.LS
Prop. Delay - TD3
From 50% Points
25
ns
Asymmetry
WDI has 50% Duty Cycle
and 1ns Rise/Fall Time
2
ns
Rise/Fall Time
10% - 90% Points
20
ns
PARAMETER
CONDITIONS
RJW To Write Mode
Head Current
(Lh = 0 I1H, Rh
888
MIN
1.6
NOM
= on, see Rgure 1)
1-105
551 32R514/514R
2, 4, 6-Channel
Read/Write Device
WDI
4--TD1~
WUS
~
-4-TD3
HEAD
CURRENT
(Ix-Iy)
FIGURE 1: WRITE MODE TIMING DIAGRAM
APPLICATIONS INFORMATION
The specifications, provided in the data section, account for the worst case values of each parameter taken
individually. In actual operation, the effects of worst case conditions on many parameters correlate. Tables
3 & 4 demonstrate this for several key parameters. Notice that under the conditions of worst case input nOise,
the higher read back signal resulting from the higher input impedance can compensate for the higher input
noise. Accounting for this correlation in your analysis will be more representative of actual performance.
TABLE 3: KEY PARAMETERS UNDER WORST CASE INPUT NOISE CONDITIONS
PARAMETER
Tj=25°C
Tj=135°C
UNITS
1.1
1.S
nV/*iZ
32RS14R
8S0
1000
32RS14
1S.4
29.4
n
Kn
11.6
10.8
pF
Inputs Noise Voltage (max.)
Differential Input Resistance (min.)
Differential Input Capacitance (max.)
TABLE 4: KEY PARAMETERS UNDER WORST CASE INPUT IMPEDANCE CONDITIONS
PARAMETER
Tj=25°C
Tj=135°C
UNITS
0.92
1.2
nV/*iZ
32RS14R
SOO
620
32RS14
3.2
6.1
n
Kn
fO.1
10.3
pF
Inputs Noise Voltage (max.)
Differential Input Resistance (min.)
Differential Input Capacitance (max.)
1-106
0888
SSI 32R514/514R
2, 4, 6-Channel
Read/Write Device
APPLICATIONS INFORMATION (continued)
+5V
+12V
see Note 4
see Note 2
READ
DATA
SSI32P541 READ DATA PROCESSOR
H5X
---------------------------------------------.~I
HSn
-------------------------------------------......
~I
WDI
we
GND
Rwe
soo Note 5
NOTES
1. An external resistor, RCT, given by; RCT S; 130 (40/1w) where Iw is the zero-peak write current in mA, can
be used to limit internal power dissipation. Otherwise connect VDD2 to VDD1.
2. Damping resistors not required on 32R514R versions.
3. Limit DC current from RDX and RDY to 100).1A and load capacitance to 20 pF. In multi-chip application
these outputs can be wire OR'ed.
4. The power bypassing capacitor must be located close to the device with its ground returned directly to
device ground, with as short a path as possible.
5. To reduce ringing due to stray capacitance this resistor should be located close to the device. Where this
is not desirable a series resistor can be used to buffer a long WC line. In multi-chip applications a Single
resistor common to all chips may be used.
FIGURE 2: TYPICAL APPLICATION DIAGRAM
0888
1-107
SSI 32R514/514R
2, 4, 6-Channel
ReadlWrite Device
PACKAGE PIN DESIGNATIONS (TOP VIEW)
CS
HSO
cs
HSO
HSO
HS1
cs
HS2
GNO
HOX
WDI
VD01
GND
NC
WDI
VOO1
GNO
HOX
HS1
WDI
HOX
HOY
VOO2
VCT
HOY
VOD1
HOY
VDD2
H1X
H1Y
H1X
H1Y
VDD2
R/W
WC
RDX
VCT
H1X
H1Y
VCT
H5X
WUS
H2Y
H2X
H5Y
RDY
VCC
R/W
WC
H2X
18-LEAD SOL
H3X
H3Y
NC
ROX
ROY
H2Y
H4X
NC
WUS
R/W
H4Y
WC
H3X
vcc
NC
RDX
H3Y
WUS
ROY
vcc
24-LEADSOL
x0 0z
:r:
Cl
4 3
R/W
WC
2
1 28 27 26
25
24
23
32R514-6
22
32R514R-6
21
20
19
13 14 15 16 17 18
0
z
28-LEADSOL
0
en
Cii en
'" :;:is
~ :r: :r: :r:
0
~ ~ 0
a: a: >
x
en
::> ~ M
:;: :r: :r:
VDD1
VDD2
VCT
H5X
H5Y
H4X
H4Y
THERMAL CHARACTERISTICS
PACKAGE
9ja
18-Lead
SOL
100°C/W
24-Lead
SOL
SO°C/W
2S-Lead
SOL
70°C/W
2S-Lead
PLCC
65°C/W
28-LEAD PLCC
1-108
0888
551 32R514/514R
2, 4, 6-Channel
Read/Write Device
ORDERING INFORMATION
ORDER NO.
PKG.MARK
SS132R514-2CL
32R514-2CL
PART DESCRIPTION
SSI32R514 ReadIWrite IC
2-Channel SOL
4-Channel SOL
SS132R514-4CL
32R514-4CL
6-Channel SOL
SS132R514-6CL
32R514-6CL
6-Channel PLCC
SS132R514-6CH
32R514-6CH
SSI 32R514R Read/Write IC-with internal damping resistors
2-Channel SOL
SS132R514R-2CL
32R514R-2CL
4-Channel SOL
SS132R514R-4CL
32R514R-4CL
6-Channel SOL
SS132R514R-6CL
32R514R-6CL
6-Channel PLCC
SS132R514R-6CH
32R514R-6CH
No responsibility is assumed by SSi for use of this product nor for any infringements of patents and trademarks or other rights of third parties
resulting from its use. No license is granted under any patents, patent rights or trademarks of SSi. SSi reserves the right to make changes
in specifications at any time without notice.
Silicon Systems, Inc., 14351 Myford Road, Tustin,
0888
CA 92680, (714) 731-7110, TWX 910-595-2809
©1988 Silicon Systems, Inc.
1-109
NOTES:
SSI32R515/515R
9, 10-Channel Ferrite
Read/Write Device
INTEGRATION
August 1988
DESCRIPTION
FEATURES
The SSI32R515 is a bipolar monolithic integrated circuit designed for use with a center-tapped ferrite recording head. It provides a low noise read path, write
current control, and data protection ciruitry for as many
as 10 channels. The SSI 32R515 requires +5V and
+ 12V power supplies and is available in a variety of
packages.
•
The SSI32R515R performs the same function as the
SSI32R515 with the addition of internal damping resistors. The SSI 32R515M and SSI 32R515RM are
functionally equivalent to the SSI 32R515 and
SSI 32R515R however, they have the mirror image pin
arrangement to simplify layout when using muHiple devices.
High Performance
Read Mode Gain = 100VN
Input Noise = 1.5 nV/..JHi. max.
Input Capacitance
•
Write Current Range = 10 mA to 50 mA
Enhanced system write to read recovery time
•
Power supply fault protection
•
Designed for center-tapped ferrite heads
•
Programmable write current source
•
Includes write unsafe detection
•
TTL compatible control signals
•
+5V, +12V power supplies
•
Mirror Image package option
BLOCK DIAGRAM
VOD1
vee
GND
wus
VDD2
=20 pF
PIN DIAGRAM
VCT
HOX
HOV
H1X
H1Y
ROX
o;;.+'±'+'±'~~+-''If+~ f+f~t%~~~44$4q
H2X
H2Y
ROY 0+""-'"'~~""-'"'h4",,-,","""" FF+~' h++""F+~
H3X
H3Y
H4X
H4Y
HSX
HSY
H6X
H1X
H1Y
we
Hax
34-LEADSOL
HBY
H9X
I.:lSi1.3±ill2S2222Sl222232231221i.Li2s2=zz:;;;:JBi.ZZl
0888
1-111
H9Y
CAUTION: Use handling procedures necessary
for a static sensitive component.
551 32R515/515R
9, 10-Channel Ferrite
Read/Write Device
CIRCUIT OPERATION
The SSI32R515 gives the userthe ability to address up
to 10 center-tapped ferrite heads and provide write
drive or read amplification. Head selection and mode
control is accomplished using the HSn, CS and RJW
inputs as shown in tables 1 & 2. Internal pullups are
provided for the CS & RIW inputs to force the device
into a non-writing condition if either control line is
opened accidentally.
TABLE 1: Mode Select
cs
1
HS2
0
0
0
0
1
1
1
1
0
0
o = Low level
HS1
0
0
1
1
0
0
1
1
0
0
HSO
0
1
0
1
0
1
0
1
0
1
Two negative transitions on WDI, after the fault is
corrected, will clear the WUS flag.
To enhance write to read recovery time the change in
RDX, RDY common mode voltage is minimized by
biasing these outputs to a level within the read mode
range when in write mode.
TABLE 2: Head Select
HS3
0
0
0
0
0
0
0
0
1
1
• Head open
• Head center tap open
• WDI frequency too low • Device in read mode
• Device not selected
• No write current
To further assure data security a voltage fault detection
circuit prevents application of write current during
power loss or power sequencing.
MODE
Write
Read
Idle
R/W
0
1
X
0
0
The Write Unsafe detection circuitry monitors voltage
transitions at the selected head connections and flags
any of the following conditions as a high level on the
Write Unsafe open collector output:
HEAD
0
1
2
3
4
5
6
7
8
9
1 = High level
WRITE MODE
Taking both CS and R/W low selects write mode which
configures the SSI32R515 as a current switch and activates the Write Unsafe (WUS) detector circuitry.
Write current is toggled between the X and Y side ofthe
selected head on each high to low transition of the
Write Data Input (WDI). Note that a preceding read
mode selection initializes the Write Data Flip-Flop,
WDFF, to pass write current through the "X" side of the
head. The zero-peak write current magnitude is programmed by an external resistor Rwc from pin WC to
GND and is given by:
Iw = KlRwc, where K = Write Current Constant
Power dissipation in write mode may be reduced by
placing a resistor (RCT) between VDD1 & VDD2. The
optimum resistor value is 96Qx 50/lw (Iw in rnA). At low
write currents «15 rnA) read mode dissipation is
higher than write mode and RCT, though recommended, may not be considered necessary. In this
case VDD2 is connected directly to VDD1.
READ MODE
Taking CS low and R/W high selects read mode which
configures the SSI 32R515 as a low noise differential
amplifier for the selected head. The RDX and RDY
outputs are driven by emitterfollowers and are in phase
with the "X" and ''Y'' head ports. These outputs should
be AC coupled to the load. The internal write current
source is gated off in read mode eliminating the need
for any external gating.
Read mode selection also initializes the Write Data
Flip-Flop (WDFF) to pass write current through the "X"
side of the head at a subsequent write mode selection.
IDLE MODE
Taking CS high selects the idle mode which switches
the RDX. RDY outputs into a high impedance state and
deactivates the internal write current source. This
facilitates multi-device installations by allowing the
read outputs to be wire OR'ed and the write current
programming resistor to be common to all devices.
1-112
0888
SSI 32R515/515R
9, 10-Channel Ferrite
Read/Write Device
PIN DESCRIPTIONS
NAME
I/O
DESCRIPTION
HSO-HS3
I
Head Select
CS
I
Chip Select: a low level enables device
R/W
I
WUS
O·
WDI
I
HOX-H9X
HOY-H9Y
I/O
RDX, RDY
O·
WC
ReadIWrite: a high level selects read mode
Write Unsafe: a high level indicates an unsafe writing condition
Write Data In: negative transition toggles direction of head current
X,Y head connections
.
X, Y Read Data: differential read signal out
Write Current: used to set the magnitude of the write current
VDD1
-
VDD2
-
Positive power supply for the center tap voltage source
GND
-
Ground
VCT
VCC
Voltage Center Tap: voltage source for head center tap
+5V
+12V
• When more than one Read/Write device is used, these signals can be wire OR'ed.
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS (All voHages referenced to GND. Currents into device are positive.)
PARAMETER
VALUE
UNITS
DC Supply VoHage
VDD1
-0.3 to +14
VDC
DC Supply VoHage
VDD2
-0.3 to +14
VDC
DC Supply VoHage
VCC
-0.3 to +6
VDC
Digital Input VoHage Range
Head Port Voltage Range
VIN
-0.3 to VCC + 0.3
VDC
VH
-0.3 to VDD1 + 0.3
VDC
WUS Pin Voltage Range
Vwus
-0.3 to +14
VDC
Write Current Zero Peak
Iw
60
mA
Output Current
RDX, RDlo
-10
mA
Output Current
IveT
-60
mA
mA
Output Current
Iwus
+12
Storage Temperature Range
Tstg
-65 to 150
°C
215
°C.
Package Temperature PLCC, SO
(20 sec Reflow)
0888
1-113
551 32R515/515R
9, 10-Channel Ferrite
Read/Write Device
RECOMMENDED OPERATION CONDITIONS
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNITS
DC Supply VoHage
VDD1
10.8
12.0
13.2
VDC
DC Supply Voltage
VCC
4.5
5.0
5.5
VDC
3
15
!lH
32R515 only
500
2000
0
Iw = 50 rnA
91
101
0
Head Inductance
Lh
Damping Resistor
RD
RCT Resistor
RCT<
Write Current
IW
10
80
rnA
Tj
+25
+135
°C
Junction Temperature Range
96
>
>
:I:
:I:
:I:
23
22
21
20
19
,.
C
C
0
~
X
'"
~
17
.,
..
.
H7Y
15
H7X
,.
,.
32
32R515132R515R
10 Channels
35
H8X
,.
H6Y
H6X
12
H5Y
11
H5X
10
H4Y
WC
37
H4X
RfN
38
H3Y
NlC
30
40
.,
42
~ ~ ~
..
'"
CIl
:I:
cz
Cl
H3X
1
~ ~
x
>- 1::i ~
:I: :I:
:i: :i:
44-Lead PLCC
HOX
GND
GND
HOX
HOY
HS3
HS3
HOY
H1X
t:s"
H1X
H1Y
FWI
H1Y
H2X
WC
H2Y
ROY
ROY
H2Y
H3X
RDX
RDX
H3X
H3Y
HSO
HSO
H3Y
H2X
H4X
HS1
HS1
H4X
H4Y
HS2
HS2
H4Y
H5X
vee
vee
H5X
H5Y
WDI
WDI
H5Y
H6X
WUS
WUS
H6X
H6Y
VOO1
.VOD1
H6Y
H7X
VOO2
VDD2
H7X
H7Y
VCT
VCT
H7Y
HeX
HaY
HaY
H6X
34-Lead SOL
)888
34-Lead SOL
Mirror Image
1-119
551 32R515/515R
9, 10-Channel Ferrite
ReadlWrite Device
THERMAL CHARACTERISTICS: 0 ja
34-Lead
SOL
50°C/W
44-Lead
PLCC
60°C/W
ORDERING INFORMATION
ORDER NO.
PKG.MARK
9-Channel SOL
SS132R515-9CL
32R515-9CL
10-Channel PLCC
SS132R515-10CH
32R515-10CH
9-Channel SOL
SS132R515R-9CL
32R515R-9CL
10-Channel PLCC
SSI32R515R-1OCH
32R515R-1OCH
SS132R515M-9CL
32R515M-9CL
SSI32R515RM-9CL
32R515RM-9CL
PART DESCRIPTION
SSI32R515
SSI32R515R
SSI32R515M
9-Channel SOL
SSI32R515RM
9-Channel SOL
No responsibility is assumed by SSi for use of this product nor for any infringements of patents and trademarks or other rights of third parties
resulting from its use. No license is granted under any patents, patent rights qr trademarks of SSi. SSi reserves the right to make changes
in specifications at any time without notice.
Silicon Systems, Inc., 14351. Myford Road, Tustin
©1988 Silicon Systems, Inc.
CA 92680, (714) 731-7110, TWX 910-595-2809
08881
I
1-120
SSI 32R520/520R
4-Channel Thin Film
ReadlWrite Device
INTEGRATION
August, 1988
FEATURES
DESCRIPTION
•
The SSI 32R520 is an integrated read/write circuit
designed for use with non-center tapped thin film
heads in disk drive systems. Each chip controls four
heads and has three modes of operation: read, write,
and idle. The circuit contains four channels of read
amplifiers and write drivers and also has an internal
write current source.
High performance
= 120V/v
Read mode gain
Input noise = 0.9nV/-fI=lZ
Input capacitance = 65 pF
Write current range = 30 rnA to 75 rnA
= 3.8 Vpp
Write current risetime = 13 nsec
Head voltage swing
A current monitor (IMF) output is provided that allows
a multi-chip enable fault to be detected. An enabled
chip's output will produce one unit of current. An open
collector output, write select verify (WSV) , will go low if
the write current source transistor is forward biased.
The circuit operates on +5 volt, and -5 volt power and
is available in a 24-pin flatpack. The SSI 32R520R
differs from the SSI 32R520 by having internal 200Q
damping resistors.
•
Write unsafe detection
•
TTL - compatible logic levels
•
Operates on standard +5 volt and -5 volt power
supplies
PIN DIAGRAM
BLOCK DIAGRAM
IMF
US
.,n."""",n
~
I
CHIP
SELECT
FUNCTION
VERIFY
WS
ITI
WSV
~
lID ~
WD
WIT
HS1
O"H"
.. R.E!E
RD
~
~
HS1 [
HS2 [
VWC [
POST
READ
AMPLIFIER
WRITE
BUFFER
VEE
a;
II
10
DIFFERENTIAL
READ
AMPLIFIERS
AND
WRITE
CURRENT
SWITCHES
HEAD
SELECT
HOX
HOY
I
H1X
H1Y
~
H2X
H2Y
II.··.····
HEAD 3
..···.···.··.··.'
H3X
HSY
21
HOX
20
HOY
WI)
19
H2X
WD
18
H2Y
US
17
H1X
IMF
16
H1Y
vee
I·.·.·.··.·.·
. ·.··.···.
1•. t1~D.!
4
HS2
H3X
RD
H3Y
lID
GND
(4-CHANNELS)
WRITE
CURRENT
SOURCE
HI
CAUTION:
0888
RfW
WSV
HEAD
TRANSITION
DETECTOR
WRITE
SELECT
[
GND
vwc
1-121
Use handling procedures necessary
for a static sensitive component.
SSI 32R520/520R
4-Channel Thin Film
ReadlWrite Device
CIRCUIT DESCRIPTION
READ MODE
WRITE MODE
In the Read Mode, (R/W high and CD low), the circuit
functions as a differential amplifier. The amplifier input
terminals are determined by the Head Select inputs.
In the write mode (R/W and CE low) the circuit functions
as a differential current switch. The Head Select inputs
(HS1 and HS2) determine the selected head. The
Write Data Inputs (WD, WD) determine the polarity of
the head current. The write current magnitude is
adjustable by an extemal1 % resistor, Rwc, from VWC
to VEE, where:
HEAD SELECT TABLE
HEAD SELECTED
HS2
HS1
0
0
0
Iw
Vwc
Rwc(1 +Rh)
Rd
Where:Vwc = Write Current Pin Voltage = 1.65 ± 5%
Rh
=
1
0
1
2
1
0
3
1
1
Head Plus External Wire Resistance
Rd = Damping Resistance
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, 4.75:5 Vee:5 5.25, -5.5:5 VEE:5 -4.95V, 25°:5 T (junction):5 125°C.
ABSOLUTE MAXIMUM RATINGS
Operation above absolute maximum ratings may permanently damage the device.
PARAMETER
Positive Supply Voltage, Vcc
Negative Supply Voltage, VEE
RATING
UNIT
6
V
-6
V
Operating Junction Temperature
25 to 125
°C
Storage Temperature
-65 to 150
°C
260
°C
Head Select (HS)
-0.4 to Vee +0.3
V
Chip Enable (CE)
-0.4 to Vcc +0.3
V
Read Select (RIW)
Lead Temperature (Soldering, 10 sec)
Input Voltages
-0.4 or -2 rnA to Vcc +0.3
V
Write Data (WD, WD)
VEE to + 0.3
V
Head Inputs (Read Mode)
-0.6 to + 0.4
V
1-122
0888
SSI 32R520/520R
4-Channel Thin Film
Read/Write Device
ABSOLUTE MAXIMUM RATINGS (Continued)
RATING
UNIT
Read Data (RD, RD)
0.5 to Vee +0.3
V
Write Unsafe (WUS)
-0.4 to Vee +0.3
and 20 rnA
V
PARAMETER
Outputs
Write Select Verify (WSV)
-O.4V to Vee +0.3V and 20
rnA
Current Monitor (IMF)
-0.4 to Vee +0.3
V
Current Reference (VWC)
VEE to Vee +0.3
andS rnA
V
Iw rnax = 150
rnA
Head Outputs (Write Mode)
POWER SUPPLY
PARAMETER
CONDITIONS
MAX
UNIT
Power Dissipation
All modes, 25 s; Tj s; 100
612+6.71w
rnW
1000 s; Tj s; 125 °C
MIN
NOM
563+6.71w
rnW
Idle Mode
10+lw/19
rnA
Positive Supply Current (ICC)
Read Mode
40+lw/19
rnA
Positive Supply Current (ICC)
Write Mode
38+lw/19
rnA
Negative Supply Current (lEE)
Idle Mode
-12-lw/19
rnA
Negative Supply Current (lEE)
Read Mode
-66-1w/19
rnA
Negative Supply Current (lEE)
Write Mode
·75-1.16Iw
rnA
Positive Supply Current (ICC)
LOGIC SIGNALS
PARAMETER
CONDITIONS
Chip Enable Low Voltage (VLCE)
Read or Write Mode
Chip Enable High Voltage (VHCE)
Idle Mode
2.0
Chip Enable Low Current (ILCE)
VLCE=OV
-1.60
Chip Enable High Current (IHCE)
VHCE=2.0V
Read Select High Voltage (VHRIW)
Read or Idle Mode
Read Select Low Voltage (VLRIW)
Write or Idle Mode
Read Select High Current (IHRIW)
VHR/W= 2.0V
Read Select Low Current (ILRIW)
VLRIW=OV
Head Select High Voltage (VHHS)
Head Select Low Voltage (VLHS)
Head Select High Current (IHHS)
0888
MIN
VHHS= VCC
1-123
NOM
MAX
O.S
UNIT
V
V
rnA
-0.3
rnA
V
2.0
O.S
V
0.015
rnA
-0.15
rnA
2.0
V
O.S
V
0.25
rnA
5S1 32R520/520R
4-Channel Thin Film
Read/Write Device
LOGIC SIGNALS (Continued)
PARAMETER
CONDITIONS
MIN
Head Select low Current (ILHS)
VLHS=OV
-0.1
WUS, WSV Low Level Voltage
WUS, WSV High Level Current
MAX
UNIT
0.25
mA
ILUS= 8 mA
(denotes safe condition)
0.5
V
VHUS=5.OV
(denotes unsafe condition)
100
IlA
2.20
3.70
mA
0.02
mA
0
VCC+O.3
V
IMF ON Current
NOM
IMF OFF Current
IMF Voltage Range
READ MODE
Tests performed with 1000 load resistors from RD and RD through series isolation diodes to VCC.
PARAMETER
CONDITIONS
Differential Voltage Gain
Vin = 1 mVpp, f = 300 KHz;
25 °C:S; Tj:s; 125 °C
MIN
Tj = 70 °C
NOM
MAX
UNIT
75
170
VN
85
150
VN
Voltage Bandwidth (-3 dB)
Zs < 50, Vin = 1 mVpp
f midband = 300 KHz
Input Noise Voltage
Zs = 00, Vin = OV,
Power Bandwidth = 15 MHz
0.9
nV/-iHz
Differential Input Capacitance
Vin = 1 mVpp, f = 5 MHz
65
pF
Differential Input Resistance
Vin = 1 mVpp, f = 5 MHz
32R520
1K
32R520R
130
45
MHz
0
270
0
0.17
mA
3.0
mV
Input Bias Current (per side)
Vin =OV
Dynamic Range
DC input voltage where AC
gain falls to 90% of the gain
with .5 mVpp input signal
CMRR
Vin = 100 mVpp, OV DC
1 MHz s f s 10 MHz
54
dB
10 MHz:s;1 S 20 MHz
48
dB
VCC or VEE = 100 mVpp
1 MHz s f s 10 MHz
54
dB
10 MHz s f:s; 20 MHz
40
dB
Power Supply Rejection Ratio
Channel Separation
-3.0
The three unselected channels
are driven with Vin = 100 mVpp
1 MHz S f s 10 MHz
43
dB
10 MHz:s; f s 20 MHz
37
dB
1-124
0888
SSI 32R520/520R
4-Channel Thin Film
Read/Write Device
READ MODE (Continued)
I
PARAMETER
I
I
CONDITIONS
Output Offset Voltage
Output Leakage Current
Idle Mode
Output Common Mode VoHage
(Without series isolation diodes)
Single Ended Output Resistance
MIN
NOM
I
MAX
I
UNIT
-360
360
mV
0.01
rnA
VCC-l.l
VCC-O.13
V
10
KO
Single Ended Output Capacitance
10
pF
WRITE MODE
PARAMETER
MIN
CONDITIONS
Current Range (Iw)
Current Tolerance
Current set to nomial value
by Rx, Rh = 150± 10%,
Tj = 50°C, Rd = 2000
(Iw) (Rh) Product
Differential Head VoHage Swing
Unselected Head
Transient Current
= 40 rnA, Lh = 0.3 IlH,
Rh = 150
Iw = 40 rnA, Lh = 0.3 IlH,
Rh = 150 Non-adjacent
Iw
MAX
UNIT
30
NOM
75
rnA
-8
+8
%
0.24
1.30
V
Vpp
3.8
2
mAp
heads tested to minimize
external coupling effects
Head Differential Load
32R520
1K
Resistance, Rd
32R520R 25 °C ~ Tj ~ 125°C
130
270
0
120°C
140
260
0
= 70°C
150
250
0
30
pF
60 °C
~
Tj
~
Tj
Head Differential Load
Capacitance
0888
Differential Data Voltage,
(WD-WD)
0.20
Data Input Voltage Range
-1.87
0
V
+0.1
V
Data Input Current (per side)
Chip Enabled
150
IJ.A
Data Input Capacitance
Per side to GND
10
pF
1-125
I
SSI 32R520/520R
4-Channel Thin Film
Read/Write Device
SWITCHING CHARACTERISTICS
MAX
UNIT
Idle to Read/Write Transition Time
1.0
Read/Write to Idle Transition Time
1.0
PARAMETER
CONDITIONS
MIN
NOM
Read to Write Transition TIme
VLCE= 0.8V,
Delay to 90% of Iw
0.6
IlS
IlS
IlS
Write to Read Transition Time
VLCE = 0.8V, Delay to 90%
of 20 MHz Read Signal
envelope, Iw decay to 10%
0.6
JlS
0.40
JlS
13
ns
Head Select Switching Delay
Read or Write Mode
Shorted Head Current
Transition Time
Iw = 40 rnA, Lh < 0.05 IlH,
Shorted Head Current Switching
Delay Time
Iw = 40 mA, Lh < 0.05 ilK,
Rh = 0, measured from 50%
of input to 50% of current
change
18
ns
Head Current Switching
Time Symmetry
Iw = 40 rnA, Lh = 0.2 IlH,
1.0
ns
WSV Transition Time
Delay from 50% of write select
swing to 90% of final WSV
voHage, Load = 2 Kn /I 20 pF
1.0
IlS
Unsafe to Safe Delay After
Write Data Begins (WUS)
f(data) = 10 MHz
1.0
JlS
Safe to Unsafe Delay, (WUS)
Non-switching write data,
no write current
3.6
IlS
Safe to Unsafe Delay, (WUS)
Head open or head select
input open
0.6
JlS
IMF Switching Time
Delay from 50% of CE to
90% of finallMF current
1.0
JlS
Rh =0
Rh = 10n, WD & WD
transitions 2 ns, switching
time symmetry 0.2 ns
1-126
0.6
0888
551 32R520/520R
4-Channel Thin Film
Read/Write Device
PACKAGE PIN DESIGNATIONS
THERMAL CHARACTERISTICS: 0 ja
(TOP VIEW)
GND
C=:======:::;-;:I r;=======:::J
I
24-Lead
1Flatpack 11 OsoC/W
I
VEE
vwc
2
RiW
WSV
3
HS1
4
21
HOX
HS2
5
20
HOY
WD
6
19
H2X
WD
7
18
H2Y
US
8
17
H1X
IMF
9
16
H1Y
vee
H3X
L':::====:::::J
H3Y
L':::========:J
GND
RD
1'il5
24·Pln Flatpack
ORDERING INFORMATION
PART DESCRIPTION
I
I
PACKAGE MARK
SSI 32RS20-F
I
SSI 32RS20-F
SSI 32RS20R-F
I
SSI 32RS20R-F
ORDERING NUMBER
SSI 32RS20 ReadIWrite IC
24-Pin Flatpack
I
SSI 32RS20R ReadIWrite IC with Damping Resistors
24-Pin Flatpack
I
No responsibility is assumed by SSi for use of this product nor for any infringements of patents and trademarks or other rights of third parties
resulting from its use. No license is granted under any patents, patent rights or trademarks of SSi. SSi reserves the right to make changes
in specifications at any time without notice.
Silicon Systems, Inc., 14351 Myford Road, Tustin,
CA 92680 (714) 731-7110, TWX 910-595-2809
©1988 Silicon Systems, Inc.
0888
1·127
NOTES:
551 32R521 /521 R
Thin Film-6-Channel
ReadlWrite Device
INNOVATORS IN INTEGRATION
August, 1988
DESCRIPTION
FEATURES
The SSI 32R521 is a bipolar monolithic integrated circuit designed for use with non-center tapped thin film
recording heads. It provides a low noise read path,
write current control, and data protection circuitry for up
to six channels. The SSI 32R521 requires +5V and
+12V power supplies and is available in a variety of
packages.
The SSI 32R521 R differs from the
SSI 32R521 by having 2000 internal damping resistors.
•
Designed for thin film heads
•
+5'1, +12V power supplies
•
Ideal for multi-platter Winchester applications
•
Programmable write current source
•
Easily muHlplexed for larger systems
•
Includes write unsafe detection
PIN DIAGRAM
BLOCK DIAGRAM
VDD
~
c
RDX
ROY
VCC1
VCC2
:.
wus
GND
WRIlE
UNSAFE
{
HOX
DETECTOR
II
HOY
±lM0
Q
z
Q
3
2
"
5! ~ ~ ~
1
...
>
'i:
rzJ
H1X
H1X
HW
MULTIPLEXER
H2X
"l
II:
IIiI·.·.·III·.·.1
U
H2Y
H3X
H3Y
E:·.:::.:rr::::::.·:·.·:·,
..~~~-
WP
~
4
" E.
Sa
WDI
IMF
H4X
SOORCE
H4Y
HSO
12
13
14
15
16
17
18
~
~ ~ !l !l3
~
!
15
HSJ(
HS1
HS2
we
HSY
lit}.:}: .}'
I
28-LEAD PLCC
CAUTION: Use handling procedures necessary
for a static sensitive component.
0888
1-129
I
SS132R521/521 R
Thin Film-6-Channel
Read/Write Device
CIRCUIT OPERATION
when the device is selected. This allows a multi chip
enable fault to be detected.
The 881 32R521 functions as a write driver or as a read
amplifier for the selected head. Head selection and
mode control are described in Tables 1& 2. The inputs
R/W, C8 and WP have internal pull-up resistors to
prevent an accidental write condition.
NOTE: If it is deSirable to initialize the Write Data flipflop to pass current in the Y -direction of the head when
entering Write Mode, the WDI input must go low in
Read mode for 20 ns minimum.
WRITE MODE
READ MODE
The Write mode configures the 881 32R521 as a current switch and activates the Write Unsafe Detector.
Head current is toggled between the X- and Y-directions of the recording head on the falling edges of WDI,
Write Data Input. The magnitude of the write current,
given by:
In the Read mode, the 881 32R521 is configured as a
low noise differential amplifier, the write current source
and the write unsafe detector are deactivated, and the
write data flip-flop can be set. The RDX and RDY
outputs are driven by emitter followers. They should be
AC coupled to load. Note that the internal write current
source is deactivated for both the Read and chip
deselected modes.
Iw= Vwc
Rwc
IDLE MODE
is controlled by an external resistor, Rwc, connected
from pin WC to GND.
Haoo Current lx, y _
Iw
1+RtvRd
Any of the following conditions will be indicated as a
high level on the Write Unsafe, WU8, open collector
output.
The idle mode deactivates the internal write current
generator, the write unsafe detector and switches the
RDX, RDY outputs into a high impedance state. This
facilitates multiple device applications by enabling the
read outputs to be wire OR'ed and the write current
programming resistor to be common to all devices.
TABLE 1: MODE SELECT
WDI frequency too low
cs
RiW
MODE
Chip disabled
0
0
Write
No write current
0
1
Read
1
0
Idle
1
1
Idle
Device in Read mode
After fauh condition is removed, two negative
transitions on WDI are required to clear WU8. The
Current monitor output (IMF) sinks one unit of current
1-130
0888
SSI 32R521 /521 R
Thin Film-6-Channel
Read/Write Device
TABLE 2: HEAD SELECT
HS2
HS1
HSO
HEAD
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
none
1
1
1
none
PIN DESCRIPTIONS
NAME
I/O
DESCRIPTION
HSO - HS2
I
Head Select: selects one of six heads
CS
I
Chip Select: a high inhibits chip
R/W
I
ReadlWrite: a high selects Read mode
WP
I
Write Protect: a low enables the write current source
WUS
O·
Write Unsafe: a high indicates an unsafe writing condition
IMF
O·
Current Monitor Function: allows muHichip enable fault detection
WDI
I
Write Data In: changes the direction of the current in the recording head
HOX - H5X
HOY - H5Y
I/O
X, Y Head Connections: Current in the X-direction flows into the X-port
RDX,RDY
O·
WC
.
Write Current: used to set the magnitude of the write current
VCC1
-
+5V LogiC Circuit Supply
VCC2
-
+5V Write Current Supply
VDD
-
+12V
GND
-
Ground
X, Y Read Data: differential read data output
·When more than one device is used, these signals can be wire OR'ed.
0888
1-131
I
SSI 32R521 1521 R
Thin Film-6-Channel
Read/Write Device
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
VALUE
UNITS
VDD
-0.3 to +14
VDC
VCC
-0.3 to +7
VDC
Write Current
IW
100
rnA
Digital Input Voltage
Yin
-0.3 to VCC +0.3
VDC
Head Port Voltage
VH
-0.3 to VDD +0.3
VDC
10
-10
Iwus
+12
rnA
rnA
Tstg
-65 to +150
°C
SYMBOL
VALUE
UNITS
VDD
12 ± 5%
VDC
VCC1
5±5%
VDC
VCC2
5±5%
VDC
Tj
+25 to +135
°C
DC Supply Voltage
Output Current:
RDX, RDY
WUS
Storage Temperature
RECOMMENDED OPERATING CONDITIONS
PARAMETER
DC Supply Voltage
Operating Temperature
DC CHARACTERISTICS
Unless otherwise specified, recommended operating conditions apply.
PARAMETER
CONDITIONS
VDD Supply Current
VCC Supply Current
Power Dissipation (Tj = +135°C)
MAX
UNITS
Read Mode
34
rnA
Write Mode
38
rnA
Idle Mode
9
Idle Mode
49
Read Mode
62
rnA
rnA
rnA
Write Mode
49+IW
rnA
Idle Mode
400
mW
Read Mode
800
mW
990
mW
Write Mode, IW - 70
1-132
MIN
rnA
0888
SSI 32R521/521 R
Thin Film-6-Channel
Read/Write Device
DC CHARACTERISTICS (Continued)
PARAMETER
CONDITIONS
MIN
MAX
UNITS
Input Low Voltage (VIL)
-0.3
0.8
VDC
Input High Voltage (VIH)
2.0
VCC+0.3
VDC
Digital Inputs
Input Low Current
VIL = 0.8V
Input High Current
VIH = 2.0V
RDX, ROY Common
Mode Output Voltage
WUS Output
3
VOL
IMF Output
mA
-0.4
101=8 mA
CS=O
0.73
CS=1
100
j.tA
5
VDC
0.5
VDC
1.23
mA
0.02
mA
WRITE CHARACTERISTICS
Unless otherwise specified, recommended operating conditions apply, and IW = 40 mA, Lh = 200 nH,
Rh = 160, f(Data) = 5 MHz, CL(RDX, RDY) < 20 pF, RL(RDX,RDY) = 1 KO.
PARAMETER
CONDITIONS
MIN
Write Current Voltage Vwc
NOM
MAX
1.65±5%
Differential Head Voltage Swing
V
3.4
V(pk)
Unselected Head Current
Differential Output Capacitance
Differential Output Resistance
32R521R
WDI Transition Frequency
160
UNITS
200
2
mA(pk)
30
pF
240
0
32R521
2K
0
WUS=low
1.7
MHz
Write Current Range
20
70
mA
MIN
MAX
UNITS
125
VN
READ CHARACTERISTICS
Unless otherwise specified, recommended operating conditions apply.
PARAMETER
CONDITIONS
Differential Voltage Gain
Yin = 1 mVpp @ 300 KHz
RL(RDX), RL(RDY) = 1 KO
75
IZsl < 50, Yin = 1 mVpp
@300KHz
25
MHz
45
MHz
Voltage BW
-1dB
-3dB
0888
1-133
I
SSI 32R5211521 R
Thin Film-6-Channel
Read/Write Device
READ CHARACTERISTICS (Continued)
PARAMETER
CONDITIONS
Input Noise Voltage
BW = 15 MHz, Lh = 0, Rh = 0
f= 5 MHz
Differential Input Capacitance
Differential Input Resistance .
Input Bias Current
Dynamic Range
MIN
521R, f = 5 MHz
521, f= 5 MHz
UNITS
0.9
nV/..JHz
pF
n
n
200
600
-3
Common Mode Rejection Ratio
Vin=OVDC+100mVpp@5MHz
Power Supply Rejection Ratio
100 mVpp @ 5 MHz on VDD
54
54
Channel Separation
100 mVpp@ 5 MHz on VCC
Unselected channels driven
with 100 mVpp@ 5 MHz
Vin= OmVpp
Single Ended Output Resistance
Output Current
MAX
65
DC input voRage where gain
falls to 90% of its 0 VDC value
Vin=VDC+0.5mVpp, f=5MHz
Output Offset Voltage
NOM
170
mA
3
mV
dB
90
dB
49
45
dB
-360
360
f=5 MHz
30
AC Coupled Load, RDX to RDY
3.2
mV
n
mA
SWITCHING CHARACTERISTICS
Unless otherwise specified, recommended operating conditions apply, and IW = 40 mA, Lh = 200 nH,
Rh = 160, f(Data) = 5 MHz.
PARAMETER
R/W
CS
MIN
UNITS
JlS
JlS
To 90% of write current
0.6
R/Wto Read
To 90% of 100 mV, 10 MHz Read
signal envelope
To 90% of write current
0.6
To 90% of 100 mV, 10 MHz Read
signal envelope
To 90% of 100 mV, 10 MHz Read
signal envelope
1
JlS
JlS
0.4
JlS
CSto Select
HSO, 1, 2 to any Head
Safe to Unsafe TD1
Transition Time
Head Current
1
0.6
Unsafe to Safe TD2
IMF
MAX
R/WtoWrite
CS to Unselect
WUS
CONDITIONS
Delay from 50% point of CS
to 90%of IMF current
3.6
1
IlS
0.6
JlS
JlS
Lh = 0, Rh = 0
WDI to (Ix-Iy) TD3
From 50% points
32
ns
Asymmetry
WDI has 50% duty cycle
and 1ns riselfall time
1.0
ns
Rise/Fall Time
10% - 90% points
13
ns
1-134
0888
SSI 32R521 1521 R
Thin Film-6-Channel
ReadlWrite Device
WDI
4--TD2
-+1
~TD1~
WUS
_
4-TD3
HEAD
CURRENT
(Ix -Iy)
FIGURE 1: Write Mode Timing Diagram
APPLICATIONS INFORMATION
Read mode input port parameter limits, as given in the specifications, are over extremes of temperature, voltage
and process. The tabulation below shows parameter correlation as a function of base sheet resistance, a
processing parameter. Use of these limits, for worst case analysis, will be more representative of actual
performance.
EXAMPLE 1: Base Sheet Resistance
PARAMETER
Tj
Input Noise Voltage (Maximum)
Differential Input Resistance (Minimum)
= 25°C
= 135°C
UNITS
0.9
nV/¥Z
521R
146
150
521
1025
1240
n
n
43
47
pF
EXAMPLE 2: Base Sheet Resistance
= Minimum
= 135°C
UNITS
0.58
0.75
nV/,!Hz
521R
133
140
521
600
760
n
n
51
56
pF
PARAMETER
Tj
Input Noise Voltage (Maximum)
Differential Input Capacitance (Maximum)
0888
Tj
0.69
Differential Input Capacitance (Maximum)
Differential Input Resistance (Minimum)
= Maximum
1-135
= 25°C
Tj
SSI 32R521/521 R
Thin Film-6-Channel
Read/Write Device
PACKAGE PIN DESIGNATIONS
(Top View)
WC
HOY
VOO
HOX
GNO
H1Y
WOI
H1X
WP
H2Y
RIW
H2X
~
H3Y
HSO
H3X
HS1
H4Y
HS2
H4X
wus
H5Y
IMF
H5X
ROX
VCC2
ROY
VCC1
4321282726
WP
21
WUS
H3X
11
12
13
14
15
16
17
18
28-Lead PLCC
THERMAL CHARACTERISTICS: 0ja
28-Lead
28-Lead SOL,
Flatpack
SOL
75°C/W
PLCC
65°C/W
Flatpack
100°C/W
ORDERING INFORMATION
ORDER NO.
PKG.MARK
6 - Channel SOL
SSI 32R521-6L
32R521-6L
6 - Channel PLCC
SS132R521-6CH
32R521-6CH
6 - Channel Flatpack
SSI 32R521-6F
32R521-6F
6 - Channel SOL
SSI 32R521 R-6L
32R521R-6L
6 - Channel PLCC
SSI 32R521 R-6CH
32R521 R-6CH
6 - Channel Flatpack
SSI 32R521 R-6F
32R521R-6F
PART DESCRIPTION
SSI 32R521 - Read/Write IC
SSI 32R521 R - with Internal Damping Resistors
No responsibility is assumed by SSi for use of this product nor for any infringements of patents and trademarks or other rights of third parties
resulting from its use. No license is granted under any patents, patent rights or trademarks of SSi. SSi reserves the right to make changes
in specifications at any time without notice.
JiIuonJz rskmJ'"
Silicon Systems, Inc., 14351 Myford Road, Tustin
CA 92680, (714) 731-7110, TWX 910-595-2809
0888
©1988 Silicon Systems, Inc.
1-136
SSI 32R522/522R
4, 6-Channel Thin Film
Read/Write Device
INNOVATORS IN INTEGRATION
August, 1988
FEATURES
DESCRIPTION
Th~ SSI32R522/522R ReadlWrite devices are bipolar
monolithic integrated circuits designed for use with two
terminal thin film recording heads. They provide a low
noise read amplifier, write current control and data
protection circuitry for as many as six channels. They
require +5V and + 12V power supplies and are available in a variety of package and channel configurations. The 32R522R option provides internal1000n
damping resistors.
• High performance:
- Read mode gain 100 VN
-Input noise 1.0 nVNHz max.
- Input capacitance 32 pF max.
- Write current range 6 mA to 35 mA
• Compatible wHh two & three terminal thin film heads
=
=
=
=
• Programmable write current source
• Write unsafe detection
• TTL compatible control signals
• +5, +12V power supplies
BLOCK DIAGRAM
VOO
vee1 VCC2
wus
GNO
PIN DIAGRAM
IMF
WRITE
UNSAfe
HOX
DETECTOR
AAV~
MODE
~
"CS"
ROX
ROY
•
H1X
t H1Y
MULnpLEXER
~H2Y
9H3X
0
•••••
WP
HSO
I~~~
}I
HOY
HOX
GND
H1Y
WDI
H1X
HOY
~H2X
WDI
we
VDD
I:
H4Y
HS1
~H5X
HS2
~ !lI;y
we
WP
H2Y
RlW
H2X
~
H3Y
HSO
H3X
HSl
H4Y
HS2
H4X
WUS
H5Y
IMF
H5X
RDX
VCC2
ROY
VCCl
CAUTION: Use handling procedures necessary
for a static sensitive component.
0888
1-137
SSI 32R5221522R
4, 6-Channel Thin Film
ReadlWrite Device
CIRCUIT OPERATION
The SSI 32R522 addresses up to six two-terminal thin
film heads providing write current drive or read amplification. Head selection and mode control is acComplished with pins HSn, CS and RIW, as shown in
Tables 1 & 2. Internal resistor pullups, provided on
pins CS, R/W and WP will force the device into a nonwriting condition if either control line is opened accidentally.
A multiple device enable condition can be detected by
monitoring the voltage across a resistor connected
from VCC to the wire OR'ed IMF (Current Monitor
Function) pins. Pin IMF sinks one unit of current when
the device is enabled.
To initialize the Write Data Flip Flop (WDFF) to pass
current through the V-direction of the head, pin WDI
must be low when the previous read mode was commanded.
WRITE MODE
READ MODE
The write mode configures the SSI 32R522 as a
current switch and activates the Write Unsafe (WUS)
detection circuitry. Write current is toggled between
the X and V direction of the selected head on each high
to low transition on pin WDI, Write Data Input.
The read mode configures the SSI 32R522 as a low
noise differential amplifier and deactivates the write
current generator and write unsafe circuitry. The RDX
and RDVoutputs are emitterfollowers and are in phase
with the "X" and "Y" head ports. These outputs should
be AC coupled to the load.
The magnitude of the write current (O-pk) given by:
Iw = ..JI:JJ..sL
RWC
where Vwc (WC pin voltage) = 1.7V ± 5%, is programmed by an external. resistor RWC, connected
from pin WC to ground. In multiple device applications,
a single RWC resistor may be made common to all
devices. The actual head current lx, y is given by:
Ix,y=
IDLE MODE
The idle mode deactivates the internal write current
generator, the write unsafe detector and switches the
RDX, RDVoutputs into a high impedance state. This
facilitates multiple device applications by enabling the
read outputs to be wire OR'ed and the write current
programming resistor to be common to aU devices.
Iw
1 + Rh/Rd
TABLE 1: MODE SELECT
cs
where:
Rh = Head resistance + external wire resistance, and
Rd = Damping resistance.
The write unsafe detection circuitry will flag any of the
conditions listed below as a high level on the open
collector output pin, WUS. Two negative transitions on
pin WDI, after the fault is corrected, are required to
clear the WUS flag.
o
o
o
o
R/W
MODE
0
0
0
Write
1
Read
1
0
Idle
1
1
Idle
WDI frequency too low
Device in read mode
Device not selected
No write current
1-138
0888
SSI 32R5221522R
4, 6-Channel Thin Film
ReadlWrite Device
TABLE 2: HEAD SELECT
HS2
HS1
HSO
HEAD
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
X
none
o = Low level, 1 = High level, X = Don't care
PIN DESCRIPTIONS
NAME
I/O
DESCRIPTION
HSO - HS2
I
Head Select: selects one of six heads
CS
R/W
WP
WUS
IMF
I
I
Chip Select: a low level enables the device
ReadlWrite: a high level selects read mode
I
0*
0*
Write Protect: a low level enables the write current source
Write Unsafe: a high level indicates an unsafe writing condition
Current Monitor Function: allows multichip enable fault detection
WDI
I
Write Data In: a negative transition toggles the direction of the
head current
X, Y Head Connections: Current in the X-direction flows into the
X-port
X, Y Read Data: differential read data output
HOX- H5X
HOY-H5Y
RDX, RDY
WC
VCC1
VCC2
VDD
GND
I/O
0*
*
-
-
Write Current: used to set the magnitude of the write current
+5V Logic Circuit Supply
+5V Write Current Supply
+12V
Ground
*When more than one device is used, these signals can be wire OR'ed.
0888
1-139
SSI 32R522/522R
4, 6-Channel Thin Film
Read/Write Device
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
VALUE
VDD
-0.3 to +14
VDC
VCC1,2
Iw
-0.3to.+7
100
VDC
Yin
VH
-0.3 to VCC +0.3
-0.3 to VDD +0.3
VDC
VDC
DC Supply Voltage
Write Current
Digital Input Voltage
Head Port Voltage
Output Current
I
I
UNITS
mA
10
-10
Iwus
+12
mA
mA
Tstg
-65 to +150
°C
SYMBOL
VALUE
UNITS
RDX,RDY
WUS
Storage Temperature
RECOMMENDED OPERATING CONDITIONS
PARAMETER
DC Supply Voltage
VDD
12±5%
VDC
VCC1
VCC2
5±5%
5±5%
VDC
VDC
Tj
+25 to +135
°C
Operating Temperature
DC CHARACTERISTICS
Unless otherwise specified: recommended operating conditions apply.
PARAMETER
VDD Supply Current
CONDITIONS
Read Mode
Write Mode
Idle Mode
VCC Supply Current
Read Mode
Write Mode
Idle Mode
Power Dissipation (Tj=+135°C)
Read Mode
Write Mode, Iw = 35 mA
Idle Mode
Input Low Voltage (VIL)
MIN
MAX
-
34
mA
38
mA
9
62
mA
mA
49+IW
49
mA
mA
800
950
mW
mW
UNITS
400
mW
0.8
VDC
Input High Voltage (VIH)
Input Low Current (ilL)
VIL= 0.8V
2.0
-0.4
-
VDC
mA
Input High Current (IIH)
VIH = 2.0V
-
100
~
1-140
0888
SSI 32R522/522R
4, 6-Channel Thin Film
Read/Write Device
DC CHARACTERISTICS (continued)
I
I
PARAMETER
RDX, RDY Common Mode
Output Voltage
WUS Output Low Voltage (VOL)
IMF Output Current
CONDITIONS
MIN
Read Mode
3
101 =8 mA
CS=O
CS= 1
I
MAX
I
UNITS
5
VDC
-
0.5
VOC
0.73
1.23
mA
-
0.02
mA
WRITE CHARACTERISTICS
Unless otherwise specified: recommended operating conditions apply, Iw = 10 mA, Lh = 1.51lH,
Rh = 300 and f(Data) = 5 MHz.
PARAMETER
CONDITIONS
MIN
TYP
MAX
WC Pin Voltage (Vwc)
1.61
1.7
1.79
V
Differential Head Voltage Swing
Unselected Head Current
3.4
-
1
V(pk)
mA(pk)
30
1350
pF
0
Differential Output Capacitance
Differential Output Resistance
WDI Transition Frequency
Iw=50mA
-
-
UNITS
32R522R
800
1000
32R522
2400
1.7
-
-
0
MHz
6
-
35
mA
WUS=low
Write Current Range
READ CHARACTERISTICS
Unless otherwise specified: recommended operating conditions apply, CL(RDX, RDY) < 20 pF and
RL(ROX, RDY) = 1 KO.
PARAMETER
CONDITIONS
Differential Voltage Gain
Bandwidth
MAX
UNITS
Vin = 1 mVpp @ 300 KHz
75
125
1-1dB
IZsl<5n, Vin = 1 mVpp @ 300 KHz
25
-
VN
MHz
1-3dB
IZsl<50, Vin = 1 mVpp @ 300 KHz
BW = 15 MHz, Lh = 0, Rh = 0
45
MHz
1.0
nV/..JHz
Differential Input Capacitance
Vin = 1 mVpp, f - 5 MHz
-
-
Input Noise Voltage
32
pF
I 32R522R
Vin = 1 mVpp, f = 5 MHz
460
-
0
32R522
Vin = 1 mVpp, f = 5 MHz
770
-
0
3
mV
-
dB
Differential Input
Resistance
I
Dynamic Range
DC input voltage where gain
falls to 90% of its 0 VOC value,
Vin = VDC + 0.5 mVpp, f = 5 MHz
-3
Common Mode Rejection Ratio
Vin = OVDC + 100 mVpp@5MHz
100 mVpp@ 5 MHz on VDO
54
Power Supply Rejection Ratio
100 mVpp@ 5 MHz on VCC
0888
MIN
1-141
54
-
dB
I
SSI 32R5221522R
4, 6-Channel Thin Film
Read/Write Device
READ CHARACTERISTICS (continued)
PARAMETER
TEST CONDITIONS
Channel Separation
Unselected channels driven
with 100 mVpp @ 5 MHz,
Vin=OmVpp
Output Offset Voltage
Single Ended Output Resistance
f= 5 MHz
Output Current
AC Coupled Load, RDX to ROY
MIN.
MAX.
UNITS
45
-
dB
·300
+300
mV
-
30
n
3.2
-
mA
SWITCHING CHARACTERISTICS
Unless otherwise specified: recommended operating conditions apply, IW = 10 mA, Lh = 1.5 ~H,
Rh = 30n and f(Data) = 5 MHz. Reference Figure 1.
PARAMETER
CONDITIONS
RJW
MIN
MAX
UNITS
R/W to Write Mode
Delay to 90% of write current
.
0.6
~
RIW to Read Mode
Delay to 90% of 100 mV, 10 MHz
Read signal envelope or to 90%
decay of write current
-
0.6
~
CSto Select
Delay to 90% of write current or to
90% of 100 mV, 10 MHz Read
siena I enveloDe
Delay to 90% of write current
-
1
~
-
1
~
Delay to 90% of 100 mV, 10 MHz
Read signal envelope
-
0.4
~
Safe to Unsafe-TD1
0.6
3.6
~
Unsafe to Safe-TD2
-
1
~
Delay from 50% point of CS to
90% of IMF current
-
0.6
~
From 50% pOints, Lh=O!J.h, Rh=On
WDI has 50% duty cycle and
1ns riselfall time, Lh=O~h, Rh=On
-
Asymmetry
-
32
0.5
ns
ns
Rise/Fall Time
10% - 90% points, Lh=O~h, Rh=On
-
10
ns
~
CS to
Unselect
HSn
HSO, 1, 2 to any Head
WUS
IMF
Propagation Delay
Head Current
Prop. Delay-TD3
1-142
0888
SSI 32R522/522R
4, 6-Channel Thin Film
ReadlWrite Device
-4-- TD2
---"1
~TD1~
WUS
---..
~TD3
HEAD
CURRENT
(Ix -Iy)
FIGURE 1: WRITE MODE TIMING DIAGRAM
APPLICATIONS INFORMATION
The specifications, provided in the data section, account for the worst case values of each parameter taken
individually. In actual operation, the effects of worst case conditions on many parameters correlate. Tables 3 &
4 demonstrate this for several key parameters. Notice that under the conditions of worst case input noise, the
higher read back signal resulting from the higher input impedance can compensate for the higher input noise.
Accounting for this correlation in your analysis will be more representative of actual performance.
TABLE 3: KEY PARAMETERS UNDER WORST CASE INPUT NOISE CONDITIONS
PARAMETER
Tj
Input Noise Voltage (Max.)
Ditferentiallnput Resistance (Min.)
32R522R
32R522
Differential Input Capacitance (Max.)
= 25°C
Tj
= 135°C
UNITS
0.76
1.0
nV/'-'Hz
602
645
1245
1455
n.
n.
25
28
pF
TABLE 4: KEY PARAMETERS UNDER WORST CASE INPUT IMPEDANCE CONDITIONS
=135°C
UNITS
0.63
0.82
nV/.,fHz
32R522R
460
526
32R522
770
960
n.
n.
30
32
pF
PARAMETER
Tj
Input Noise Voltage (Max.)
Differential Input ReSistance (Min.)
Differential Input Capacitance (Max.)
0888
1-143
=25°C
Tj
SSI 32R522/522R
4 or 6-Channel Thin Film
Read/Write Device
PACKAGE PIN DESIGNATIONS
(TOP VIEW)
GNO
C=======:::;-;:J
VOO
WC
HOY
WDI
WC
VDD
HOX
WP
HOY
GND
H1Y
RlW
4
21
HOX
WDI
H1X
~
5
20
H1Y
WP
H2Y
AlW
H2X
cs
H3Y
~
HSO
19
H1X
HS1
18
H2Y
HSO
H3X
NC
17
H2X
HS1
H4Y
WUS
16
H3Y
IMF
HS2
H4X
WUS
H5Y
IMF
H5X
RDX
VCC2
RDY
VCC1
4321282726
21
12
13
14
15
16
17
H3X
18
H3X
ROX
VCC2
ROY
VCC1
24· LEAD FLATPACK
28 • LEAD PLCC
THERMAL CHARACTERISTICS: 9ja
24 - Lead FLAT PACK
28· LEAD SOL
28 - Lead SOL
28 - Lead PLCC
105°C/W
70°C/W
65°C/W
ORDERING INFORMATION
PART DESCRIPTION
ORDER NO.
PKG.MARK
SSI 32R522 - Read/Write IC
4 - Channel Flat Pack
6 - Channel SOL
6 - Channel PLCC
SSI 32R522 - 4F
SSI 32R522 - 6L
SSI 32R522 - 6CH
32R522 - 4F
32R522 - 6L
32R522 - 6CH
SSI 32R522R- w/lnternal Damping Resistors
4 - Channel Flat Pack
6 - Channel SOL
6 - Channel PLCC
SSI 32R522R - 4F
SSI 32R522R - 6L
SSI 32R522R - 6CH
32R522R - 4F
32R522R - 6L
32R522R - 6CH
No responsibility is assumed by SSi for use of this product nor for any infringements of patents and trademarks or other rights of third parties
resulting from its use. No license is granted under any patents, patent rights or trademarks of SSi. SSi reserves the right to make changes
in specifications at any time without notice.
CA 92680, (714) 731-7110, TWX 910-595-2809
Silicon Systems, Inc., 14351 Myford Road, Tustin
0888
©1988 Silicon Systems, Inc.
1-144
Jh Jl rJfonJ'"
INNOVATORSIN
I~N~T~EG~RA~T~IO~N~
SSI32R524R
8-Channel Thin Film
ReadlWrite Device
I
________________________
August, 1988
DESCRIPTION
FEATURES
The SSI 32R524R Read/Write device is a bipolar
monolithic integrated circuit designed for use with
two terminal thin film recording heads. It provides a low
noise read amplifier, write current control and data
protection circuitry for eight channels. Power supply
fault protection is provided by disabling the write current generator during power sequencing. System write
to read recovery time is significantly improved by
controlling the read channel common mode output
voltage shift in the write mode. It requires +5V and
+ 12V power supplies and is available in a variety of
package configurations. A mirror image pinout option
is available'to simplify flex circuit layout in multiple RIW
device applications. The SSI 32R524R provides internal7400 damping resistors.
•
•
High performance:
Read mode gain = 100VN
Input noise 0.75 nV/'I'HZ max.
Input capacitance 60 pF max.
WrHe current range = 20 to 60 mA
Head voltage swing = 7 Vpp
WrHe current rise time = 9 nsec
Enhanced system write to read recovery time
•
Power supply fault protection
=
=
•
Plug compatible to the SSI 32R501, SSI 32R511 &
SSI32R512
• Compatible with two & three terminal thin film heads
• WrHe unsafe detection
• +5V, +12V power supplies
•
Mirror Image pinout option
BLOCK DIAGRAM
VDDl
vee
GNO
WIJS
PIN DIAGRAM
VD02
HOX
GND
HOX
NlC
N/C
HOY
~
H,X
H1Y
rWJ
rWJ
H'Y
H2X
HOY
HOX
HOV
H1X
H2X
WC
WC
H'X
H2Y
ROY
ROY
H2Y
H'V
H3X
ROX
ROX
H3X
H3Y
H3Y
HSO
HSO
H4X
HSl
HSl
H4X
H4Y
HS2
HS2
H4Y
H5X
vee
VCC
H5X
H5Y
WOI
WDI
H5Y
H6X
WUS
WUS
H6X
H6Y
VOOl
VOOl
H6Y
HSX
H7X
VOO2
VD02
H7X
HSV
H7Y
N/C
N/C
H7Y
H2X
H2V
HaX
HaV
H4X
H4V
HOX
HOV
H7X
32·LEADSOW
32·LEADSOW
MIRROR
H7V
0888
CAUTION: Use handling procedures necessary
for a static sensitive component.
1-145
SSI32R524R
a-Channel Thin Film
Read/Write Device
CIRCUIT OPERATION
The SSI 32R524R addresses eight two-terminal thin
film heads providing write drive or read amplification.
Head selection and mode control is accomplished with
pins HSn, CS and R/W, as shown in Tables 1 & 2.
Internal resistor pullups, provided on pins CS and RIW
will force the device into a non-writing condition if either
control line is opened accidentally.
WRITE MODE
The write mode configures the SSI 32R524R as a
differential current switch and activates the Write Unsafe (WUS) detection circuitry. Write current is toggled
between the X and V directions olthe selected head on
each high to low transition on pin WDI, Write Data
Input
A preceding read operation initializes the Write Data
Flip Flop (WDFF) to pass write current in the Xdirection of the head, which is defined as entering from
the V-side and flowing to the X-side.
The magnitude of the write current (O-pk) given by:
Iw=~
RWC
where K (Write Current Constant) = 70 ± 5%, is programmed by an external resistor RWC, connected
from pin WC to ground. The actual head current lx, y
is given by:
Power dissipation in Write Mode may be reduced by
placing a resistor, Rw, between VDD1 and VDD2. The
resistor value should be chosen such that Iw Rw S 3. OV
for an accompanying power dissipation reduction of
(lw)2Rw. If a resistor is not used, VDD2 should be connected to VDD1. Note that Rw will also provide current
limiting in the event of a head short.
READ MODE
The read mode configures the SSI 32R524R as a low
noise differential amplifier and deactivates the write
current generator and write unsafe detection circuitry.
The RDX and RDV outputs are emitter followers and
are in phase with the "X" and "V" head ports. These
outputs should be AC coupled to the load. The RDX,
RDV common mode voHage is maintained in the write
mode, minimizing the transient between write mode
and read mode, substantially reducing the write to read
recovery time in the subsequent Pulse Detection circuitry.
IDLE MODE
The idle mode deactivates the internal write current
generator, the write unsafe detector, and switches the
RDX, RDV outputs into a high impedance state. This
facilitates multiple device applications by enabling the
read outputs to be wire OR'ed.
TABLE 1: MODE SELECT
Iw y
Iw
,
1 +RhlRd
where:
Rh = head resistance + external wire resistance, and
Rd = damping resistance.
Power supply fault protection improves data security
by disabling the write current generator during a voltage fault or power supply sequencing. Additionally, the
write unsafe detection circuitry will flag any of the
conditions listed below as a high level on the open
collector output pin, WUS. Two negative transitions on
pin WDI, after the fault is corrected, are required to
clear the WUS flag.
• Open head
• WDI frequency too low
• Device not selected
~
RfR
MODE
0
0
Write
0
1
Read
1
0
Idle
1
1
Idle
TABLE 2: HEAD SELECT
• Device in read mode
• No write current
HS2
HS1
HSO
HEAD
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
7
0= Low level, 1 = High level
1-146
0888
SSI32R524R
8-Channel Thin Film
Read/Write Device
I
PIN DESCRIPTIONS
NAME
TYPE
DESCRIPTION
HSO - HS2
I
Head Select: selects one of eight heads
CS
I
Chip Select: a low level enables the device
R/W
I
WUS
0*
WDI
I
HOX - H7X
HOY - H7Y
1/0
RDX, ROY
0*
Read/Write: a high level selects Read Mode
Write Unsafe: Open collector output, a high level indicates an unsafe
writing condition
Write Data In: a negative transition toggles the direction of the
head current
X, Y Head Connections: Current in the X-direction flows into the
X-port
X, Y Read Data: differential read data output
Write Current: used to set the magnitude of the write current
VDD2
-
GND
-
Ground
WC
VCC
VDD1
+5V Logic Circuit Supply
+12V
Positive Power Supply for Write current drivers
* When more than one R/W device is used, these signals can be wire OR'ed.
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
VALUE
UNITS
DC Supply Voltage
VDD1,2
-0.3 to +14
VDC
VCC
-0.3 to +7
VDC
Write Current
Iw
100
rnA
Digital Input Voltage
Vin
-0.3 to VCC +0.3
VDC
Head Port Voltage
WUS Pin Voltage Range
Output Current
Storage Temperature
0888
I
I
RDX,RDY
WUS
VH
-0.3 to VDD2 +0.3
VDC
Vwus
-0.3 to +14
VDC
10
-10
Iwus
+12
rnA
rnA
Tstg
-65 to +150
°c
1-147
SSI 32R524R
8-Channel Thin Film
Read/Write Device
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
DC Supply Voltage
VDD1
VDD2
VALUE
UNITS
12± 10%
VDC
~VDD1
-3.0V
VCC
5± 10%
VDC
VDC
Tj
+25 to +135
°C
Junction Temperature
DC CHARACTERISTICS
Unless otherwise specified, recommended operating conditions apply.
PARAMETER
VDD1 Supply Current
CONDITIONS
MIN
NOM
MAX
UNITS
-
-
50
mA
45
25
mA
mA
Write Mode Iw = 60mA,
VDD1 - VDD2 = 3.0V
-
Idle Mode
Read Mode
Write Mode
Idle Mode
VDD2 Supply Current
Read Mode
Write Mode
Idle Mode
VCC Supply Current
Power Dissipation (Tj = +135°C)
Read Mode
Write Mode
Idle Mode
Read Mode
Write Mode Iw = 40mA,
VDD2 =VDD1
Input Low VoHage (VIL)
Input High Voltage (VI H)
Input Low Current (ilL)
Input High Current (IHL)
VIL= 0.8v
VIH = 2.0v
WUS Output Low Voltage (VOL)
VDD Fault VoHage
101 = 8mA
VCC Fault Voltage
Head Current (HnX, HnY)
60
mA
50
mA
mA
45
-
1425
mW
-
-
500
mW
-
0.8
2.0
-
-
VDC
VDC
100
J.LA
0.5
10.0
4.2
VDC
VDC
VDC
-
+200
J.LA
-
+200
J.LA
8.5
3.5
-200
0~VDD1 ~.5V
Readlldle Mode
0~VCC~.5V
0~VDD1 ~13.2V
1-148
J.LA
mW
O~VCC ~.5V
J.LA
mA
900
1300
-0.8
Write Mode,
200
Iw+O.4
200
-200
mW
mA
0888
SSI32R524R
8-Channel Thin Film
Read/Write Device
WRITE CHARACTERISTICS
Unless otherwise specified, recommended operating conditions apply, Iw = 40mA, Lh = 500nH, Rh = 300
and f(WDI) = 5MHz.
MIN.
NOM
MAX
Write Current Constant "K"
Differential Head Voltage Swing
66.5
73.5
V
-
Vpp
Unselected Head Current
Differential Output Capacitance
-
-
1
mA(pk)
-
35
1000
pF
CONDITIONS
PARAMETER
Differential Output Resistance
WDI Transition Frequency
7
WUS= low
400
1.0
740
-
20
Write Current Range
UNITS
-
0
MHz
60
rnA
READ CHARACTERISTICS
Unless otherwise specified, recommended operating conditions apply, CL (RDX, ROY) < 20pF and
RL (RDX,RDY) = 1Kn.
PARAMETER
Differential Voltage Gain
Bandwidth
CONDITIONS
Vin=1 mVpp @ 300 kHz
1-1dB
IZsl<50, Vin=1 mVpp @ 300 kHz
1-3dB
Input Noise Voltage
IZsl<50, Vin=1 mVpp @ 300 kHz
BW = 15 MHz, Lh = 0, Rh = 0
Differential Input Capacitance
Differential Input Resistance
Yin = 1 mVpp, f = 5 MHz
Yin = 1 mVpp, f = 5 MHz
Dynamic Range
DC input voltage where gain
falls to 90% of its 0 VDC value,
Yin = VDC +0.5 mVpp, f = 5 MHz
Yin = 0 VDC+100 mVpp@ 5 MHz
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Channel Separation
80
25
NOM MAX
UNITS
100
120
45
-
-
VN
MHz
-
0.55
0.75
-
-
60
220
-
pF
0
-3
-
3
mV
54
MHz
nV/¥Z
54
-
-
100 mVpp@ 5 MHz on VDD1
100 mVpp @ 5 MHz on VCC
-
dB
dB
Unselected channels driven
with 100 mVpp @ 5 MHz,
Vin= 0 mVpp
45
-
-
dB
+360
3.6
VDC
VDC
-360
-
Read Mode
2.2
2.9
Output Voltage
Write Mode
-
f = 5 MHz
-
2.9
Single Ended Output Resistance
30
0
Output Current
AC Coupled Load, RDX to ROY
-
-
rnA
Output Offset Voltage
RDX, ROY Common Mode
0888
MIN
1-149
3.2
mV
551 32R524R
a-Channel Thin Film
Read/Write Device
SWITCHING CHARACTERISTICS (See Figure 1)
Unless otherwise specified, recommended operating conditions apply, Iw = 40mA, Lh = SOOnH, Rh = 30n
and f(WDI) = SMHz.
CONDITIONS
PARAMETER
MIN
MAX
UNITS
-
0.6
J.Ls
0.6
J.LS
R/W
R/W to Write Mode
Delay to 90% of write current
R/W to Read Mode
Delay to 90% of 100mV 10MHz
Read signal envelope or to 90%
decay of write current
CS to Select
Delay to 90% of write current or to
90% of 100mV 10MHz Read
signal envelope
-
0.6
J.LS
CS to Unselect
Delay to 10% of write current
-
0.6
J.Ls
Delay to 90% of 100mV 10MHz
Read signal envelope
-
0.4
J.Ls
Safe to Unsafe - TD1
0.6
S.O
J.LS
Unsafe to Safe - TD2
-
1
J.LS
-
32
ns
1
ns
CS
HSn
HSO, 1, 2 to any Head
WUS
Head Current
ProD. Delay - TD3
From SO% ooints Lh=Ouh Rh=On
Asymmetry
WDI has SO% duty cycle and
1ns riselfall time, Lh=0J.Lh, Rh=On
Rise/Fall Time
10%-90% points, Lh=OJ.Lh, Rh=On
-
9
ns
Rise/Fall TIme
10%-90% points,
R(HnX, HnY)=10n
-
10
ns
WDI
TD1~
1,.----
WUS
TOO
HEAD
CURRENT
(Ix ·Iy)
FIGURE 1: WRITE MODE TIMING DIAGRAM
1-150
0888
SSI 32R524R
a-Channel Thin Film
Read/Write Device
APPLICATIONS INFORMATION
The specifications, provided in the data section, account for the worst case values of each parameter taken
individually. In actual operation, the effects of worst case conditions on many parameters correlate. Tables 3 &
4 demonstrate this for several key parameters. Notice that under the conditions of worst case input noise, the
higher read back signal resulting from the higher input impedance can compensate for the higher input noise.
Accounting for this correlation in your analysis will be more representative of actual performance.
TABLE 3: KEY PARAMETERS UNDER WORST CASE INPUT NOISE CONDITIONS
PARAMETER
Tj
Input Noise Voltage (Max.)
Differential Input Resistance (Min.)
Differential Input Capacitance (Max.)
= 135°C
UNITS
0.5
292
0.75
nV/'iHZ
318
n
43
4s
pF
= 25°C
Tj
TABLE 4: KEY PARAMETERS UNDER WORST CASE INPUT IMPEDANCE CONDITIONS
PARAMETER
Tj
0888
= 25°C
0.45
220
55
Input Noise Voltage (Max.)
Differential Input Resistance (Min.)
Differential Input Capacitance (Max.)
1-151
Tj
= 135°C
0.6
260
60
UNITS
nV"/Hz
n
pF
551 32R524R
8-Channel Thin Film
Read/Write Device
PACKAGE PIN DESIGNATIONS
(TOP VIEW)
GND
HOX
HOX
GND
GND
HOX
N/C
HOY
HOY
N/c
N/c
HOY
(%
H1X
H1X
N/c
N/C
H1X
RiiJ
H1Y
H1Y
(;S
(;S
H1Y
WC
H2X
H2X
RiiJ
RiiJ
H2X
RDY
RDY
H2Y
H2Y
WC
we
H2Y
H3X
RDX
RDX
H3X
H3X
RDY
RDY
H3X
H3Y
HSO
HSO
H3Y
H3Y
RDX
RDX
HaY
H4X
HS1
HS1
H4X
H4X
HSO
HSO
H4X
H4Y
HS2
HS2
H4Y
H4Y
HS1
HS1
H4Y
H5X
vce
vec
H5X
H5X
HS2
HS2
H5X
H5Y
WDI
WDI
H5Y
H5Y
vee
vce
H5Y
H6X
WUS
WUS
H6X
H6X
WDI
WDI
H6X
H6Y
VDD1
VDD1
H6Y
H6Y
WUS
WUS
H6Y
H7X
VDD2
VDD2
H7X
H7X
N/c
N/c
H7X
H7Y
N/C
N/e
H7Y
HOX
GND
HOY
N/C
H1X
(%
H1Y
RiiJ
H2X
WC
H2Y
32·LEADSOW
32·LEADSOW
MIRROR
H7Y
VDD1
VDD1
H7Y
N/c
VDD2
VDD2
N/c
34·LEADSOL
THERMAL CHARACTERISTICS: Gja
32-LeadSOW
55°C/W
34-Lead SOL
50°C/W
34·LEADSOL
MIRROR
ORDERING INFORMATION
PART DESCRIPTION
SSI32R524R
SSI 32R524RM
· .
ORDER NO.
PKG.MARK
8-Channel SOW
SSI 32R524R-8W
32R524R-8W
8-Channel SOL
SSI 32R524R-8L
32R524R-8L
8-Channel SOW
SSI 32R524RM-8W
32R524RM-8W
8-Channel SOL
SSI 32R524RM-8L
32R524RM-8L
No responsibility is assumed by SSi for use of this product nor for any infringements of patents and trademarks or other rights of third parties
resulting from its use. No license is granted under any patents, patent rights or trademarks of ~i. SSi reserves the right to make changes
.-~~ ~, '-';~:rifuon
en
CA 92680, (714) 731-7110, TWX 910-595-2809
Silicon Systems, Inc., 14351 Myford Road, Tustin
0888
©1988 Silicon Systems, Inc.
1-152
SSI32R525R
4-Channel Thin Film
Read/Write Device
INNOVATORS IN INTEGRATION
~~~~~~-----------------------------------------------------August, 1988
DESCRIPTION
FEATURES
The SSI 32R525 is an integrated reacl/write circuit
designed for use with non-center tapped thin film
heads in disk drive systems. Each chip controls four
heads and has three modes of operation: read, write,
and idle. The circuit contains four channels of read amplifiers and write drivers and also has an internal write
current source.
•
A current monitor (IMF) output is provided that allows
a multichip enable fault to be detected. An enabled
chip's output will produce one unit of current. An open
collector output, write select verify (WSV) , will go low if
the write current source transistor is forward biased.
The circuit operates on +5 volt, and -5 voH power and
is available in 24-pin flatpack and SOL packages.
High performance
Read Mode Gain = 150 VN
Input Noise = 0.8 nV/v'Hz max
Input Capacitance = 35 pF
WrHe Current Range = 25 mA to 40 mA
WrHe Current Rise Time =10 nsec
Head Voltage Swing
•
Write unsafe detection
•
·5V, +5V power supplies
PIN DIAGRAM
BLOCK DIAGRAM
IMF
= 3.8 Vpp min
us
GND
VEE
we
~
2
RIW
WSV
3
HS1
4
21
HOX
HS2
5
20
HOY
WI)"
19
H2X
WD
7
18
H2Y
HOX
HOY
us
8
17
H1X
IMF
9
16
H1Y
H1X
H1Y
vee
RD
H3Y
H2X
H2Y
1m
GND
H3X
H3X
H3Y
VEE
GND
vee
CAUTION: Use handling procedures necessary
for a static sensiti ..... component.
0888
1-153
SSI32R525R
4-Channel Thin Film
Read/Write Device
FUNCTIONAL DESCRIPTION
WRITE MODE
In write mode (R/W and CE low) the circuitfunctions as
a differential current switch. The Head Select Inputs
(HS1 and HS2) determine the selected head. The
Write Data Inputs (WD, WD) determine the polarity of
the head current. The write current magnitude is adjustable by an external 1% resistor, RX from WC to
VCC, where:
Iw = 80 Adc
Rx
IDLE MODE
Taking CS high selects the idle mode which switches
the RD and RD outputs into a high impedance state
and deactivates the internal write current source. This
facilitates multi-device installations by allowing the
read outputs to be wire OR'ed and the write current programming resistor to be common to all devices.
HEAD SELECT TABLE
HEAD SELECTED
HS2
HS1
0
0
0
READ MODE
In the Read Mode, (R/W high and CE low), the circuit
functions as a differential amplifier. The amplifier input
terminals are determined by the Head Select inputs.
1
0
1
2
1
0
3
1
1
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, 4.75:5 VCC:5 5.25, -5.35:5 VEE:5 -4.75V, 0°:5 T Ounction):5 100°C.
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Positive Supply Voltage, Vcc
Negative Supply Voltage, VEE
Operating Junction Temperature
Storage Temperature
RATING
UNIT
6
V
-6
V
125
°C
-65 to 150
°C
260
°C
Head Select (HS)
-0.4 to Vcc + 0.3
V
Chip Enable (CE)
-0.4 to Vcc+ 0.3
V
Lead Temperature (Soldering, 10 sec)
Input Voltages
Read Select (RIW)
-O.4V or -2 mA to Vee + 0.3
V
Write Data (WD, WD)
VEE to 0.3
V
Head Inputs (Read Mode)
-0.6 to 0.4
V
Outputs
Read Data (RD, RD)
0.5 to Vee + 0.3
V
Write Unsafe (WUS)
-O.4V to Vee + 0.3 and 20 mA
V
Write Select Verify (WSV)
-O.4V to Vee + 0.3 and 20 mA
V
1-154
0888
SSI32R525R
4-Channel Thin Film
Read/Write Device
ABSOLUTE MAXIMUM RATINGS (Continued)
PARAMETER
Outputs
RATING
UNIT
(Continued)
Current Monitor (IMF)
Current Reference (WC)
-0.4 to Vcc + 0.3
V
VEE to Vce + 0.3 and 8 rnA
V
Iw max = 150
rnA
Head Outputs (Write Mode)
POWER SUPPLY
PARAMETER
CONDITIONS
Power Dissipation
Write mode, Iw = 40 rnA
Positive Supply Current
(ICC)
MIN
NOM
MAX
UNIT
500
rnW
Idle Mode
10
rnA
Positive Supply Current
(ICC)
Read Mode
25
rnA
Positive Supply Current
(ICC)
Write Mode
12
rnA
Negative Supply Current
(lEE)
Idle Mode
8
rnA
Negative Supply Current
(lEE)
Read Mode
45
rnA
Negative Supply Current
(lEE)
Write Mode
40+lw
rnA
MAX
UNIT
0.8
V
LOGIC SIGNALS
0888
PARAMETER
CONDITIONS
Chip Enable Low Voltage
(VLCE)
Read or Write Mode
Chip Enable High Voltage
(VHCE)
Idle Mode
Chip Enable Low Current
(ILCE)
VLCE = OV
Chip Enable High Current
(IHCE)
VHCE= 2.0V
Read Select High Voltage
(VHR/w)
Read or Idle Mode
Read Select Low Voltage
(VLR/w)
Write or Idle Mode
MIN
NOM
2.0
1-155
V
-0040
rnA
20
IlA
2.0
V
0.8
V
SSI32R525R
4-Channel Thin Film
Read/Write Device
LOGIC SIGNALS (Continued)
PARAMETER
CONDITIONS
Read Select high Current
(IHRIW)
VHR/W= 2.0V
Read Select Low Current
(ILRIW)
VLRlW=OV
MIN
Head Select High Voltage
(VHHS)
NOM
MAX
UNIT
-0.40
mA
20
j.LA
V
2.0
Head Select Low Voltage
(VLHS)
0.8
V
0.25
mA
0.25
mA
Head Select High Current
(IHHS)
VHHS= VCC
Head Select Low Curren
(ILHS)
VLHS = OV
WUS, WSV Low Level VoHage
ILUS=8mA
(denotes safe condition)
0.5
V
WUS, WSV High Level Current
VHUS = 5.0V
(denotes unsafe condition)
100
j.LA
2.40
3.50
mA
0.02
mA
0
VCC+O.3
V
-0.1
IMF on Current
IMF off Current
IMF Voltage Range
READ MODE
Tests performed with 100n load resistors from RD and RD through series isolation diodes to VCC.
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNIT
Differential Voltage Gain
Yin = 1m Vpp, f = 300 KHz
100
150
VN
Voltage Bandwidth (-3d B)
Zs < 5z, Yin = 1m Vpp
f midband = 300 KHz
55
100
MHz
Input Noise Voltage
Zs = on , Yin = OV,
Power Bandwidth = 15 MHz
0.8
nVNz
Differential Input Capacitance
Yin = OV, f = 5 MHz
Differential Input Resistance
Yin = OV, f = 5 MHz
Input Bias Current (per side)
Yin = OV
Dynamic Range
DC input voltage where AC
gain falls to 90% of the gain
with .5m Vpp input signal
CMRR
Yin = 100m Vpp, OV DC
1 MHz ~ f ~a 10 MHz
54
dB
10 MHz ~f~ 20 MHz
48
dB
1-156
500
-3.0
35
pF
1800
n
0.17
mA
3.0
mV
OBBB
551 32R525R
4-Channel Thin Film
Read/Write Device
READ MODE (Continued)
MAX
UNIT
CONDITIONS
Power Supply Rejection Ratio
VCC or VEE = 100m Vpp
1 MHz s f s 10 MHz
54
dB
10 MHz s f s 20 MHz
Channel Separation
36
dB
The three unselected
channels are driven with
Vin = 100m Vpp
1 MHz s f s 10 MHz
43
dB
10 MHz Sf s 20 MHz
37
Output Offset Voltage
Output Leakage Current
MIN
NOM
PARAMETER
dB
-360
360
mV
0.01
rnA
VCC-l.l
VCC-O.3
V
Idle Mode
Output Common Mode Voltage
Kn
10
Single Ended Output Resistance
Single Ended Output Capacitance
10
pF
WRITE MODE
PARAMETER
CONDITIONS
Current Range (Iw)
Current Tolerance
Current set to nominal value
by Rx = 2K to 3.2K,
Tj=50°C
(Iw) (Rh) Product
Differential Head voltage Swing
Iw=40mA
Unselected Head
Transient Current
Iw = 40 rnA, Lh = 0.5 ~H,
MAX
UNIT
25
40
rnA
-8
+8
%
0.24
1.30
MIN
3.8
V
Vpp
2
mAp
2600
0
10
pF
Rh = 200, Non adjacent
heads tested to minimize
external coupling effects
Head DHferential Load
Resistance, Rd
1700
Head Differential Load
Capacitance
0888
NOM
Differential Data Voltage,
(WD-WD)
0.20
Data Input Voltage Range
-1.87
V
+0.1
V
~
pF
Data Input Current (per side)
Chip Enabled
150
Data Input Capacitance
per side to GND
10
1-157
551 32R525R
4-Channel Thin Film
Read/Write Device
SWITCHING CHARACTERISTICS
MAX
UNIT
Idle to Read/Write Transition Time
0.6
Il s
Read/Write to Idle Transition Time
0.3
JlS
PARAMETER
CONDITIONS
MIN
NOM
Read to Write Transition Time
VLCE = 0.8V,
Delay to 90% of Iw
0.6
JlS
Write to Read Transition Time
VLCE = 0.8V, Delay to 90% of
20 MHz Read Signal
envelope, Iw decay to 10%
0.3
IlS
Head Select Switching Delay
Read or Write Mode
0.3
JlS
Head Current Transition Time
10% to 90%
Iw = 40 rnA, Lh
Rh = 20n
= 0.151lH,
10
ns
Head Current Overshoot
Iw = 40 rnA, Lh = 0.151lH,
Rh = 20n, relative to total
current charge
25
%
Head Current Switching Time
Symmetry
Iw = 40 rnA, Lh = 0.151lH,
Rh = 20n, WD & WD
transitions 2nS, switching time
symmetry 0.2 nS
1.5
ns
WSV Transition Time
Delay from 50% of write
select swing to 90% of final
WSV voltage,
Load = 2Kn 1/ 20 pF
0.3
IlS
Unsafe to Safe Delay After
Write Data Begins (WUS)
f(data)
0.3
Il s
Safe to Unsafe Delay, (WUS)
Head open or shorted to GND,
no write current, head select
input open
0.3
IlS
Safe to Unsafe Delay, (WUS)
Non-switching write data
2.0
IMF Switching Time
Delay from 50% of CE to 90%
of final IMF current
Il s
IlS
= 5 MHz
1-158
0.5
0.3
0888
SSI32R525R
4-Channel Thin Film
ReadlWrite Device
THERMAL CHARACTERISTICS: 0
PACKAGE PIN DESIGNATIONS
(TOP VIEW)
24-Pin Flatpack
100°CIW
24-Pin SOL
ao°clW
GND
VEE
-rn:
we
VEE
~
2
wsv
3
HS1
4
21
HS2
5
20
WIl"
6
H2X
WD
7
H2Y
H,X
us
8
17
H1X
H'Y
IMF
9
16
H1Y
vee
H3X
vee
RD
H3Y
RD
H3Y
ml"
GND
"1m
GND
RiW
HOX
HS'
HOY
Ja
ANi
HOX
HOY
H2X
H2Y
H3X
24-Pln Flatpack
24-Pln SOL
ORDERING INFORMATION
PART DESCRIPTION
ORDERING NUMBER
PACKAGE MARK
S5132R525R
24-Pin Flatpack
551 32R525R-4F
551 32R525R-4F
24-Pin 50L
551 32R525R-4L
551 32R525R-4L
No responsibility is assumed by SSi for use of this product nor for any infringements of patents and trademarks or other rights of third parties
resulting from its use. No license is granted under any patents, patent rights or trademarks of SSi. SSi reserves the right to make changes
in specifications at any time without notice.
Silicon Systems, Inc., 14351 Myford Road, Tustin,
CA 92680 (714) 731-7110, TWX 910-595-2809
©1988 Silicon Systems, Inc.
0888
1-159
NOTES:
SSI 32P540-Series
Read Data Processor
INNOVATORS IN INTEGRATION
----------------------------------------------August, 1988
DESCRIPTION
FEATURES
The SSI 32P540 is a bipolar integrated circuit that
provides all data processing necessary for detection
and qualification of M FM read signals from rigid media.
ST506 compatible interfacing is provided for write data
signals, head select lines and recovered read data as
applicable.
In read mode the SSI32P540 provides amplification,
differentiation and time domain qualification of head
preamplifier outputs. The recovered data is available
at the output of a differential line driver that conforms to
the ST506 interface specification. In write mode the
SSI 32P540 provides a differential line receiver conforming with ST506 requirements. Schmitt Trigger
inputs on head select lines and an open collector
output for voltage fault indication are provided for
interface compatibility.
(Continued)
•
•
•
•
•
•
•
Differential Read and Write Ports
Schmitt Trigger Head Select Inputs for Higher
Noise Immunity
Programmable Gain
Time Domain Pulse Qualification Supports MFM
Encoded Data Retrieval
Supply Voltage Fault Detection
+12 Volt and +5 Volt Power Supplies
1/0 Meets ST506 Requirements
•
Dual-in-Line and Surface Mount Packages Available
•
Adjustable Time Domain Filter and Output Pulse
Width Settings
BLOCK DIAGRAM
Veo
GND1
Vee:
GND2 (32P54a2. 3)
~
VOLTAGE
FAULT
HSO
!I
!;l
HSOB
HSl
U
!;l
HS1B
I IS NOr AVAILABLE ON
0 !;I HS2B
HS2
WRTOUT [
·:i
.....
U
\
WRT.
WRT·
MODE
.I
!t ~E
SHOT
Q
CK
RrOPJ
Cex
O.lp.F
OBBB
g
2-1
!t~ ~
:,:""':'
Rpw
(
RD.
RD-
(NOT ~ 32P5403)
551 32P540-5eries
Read Data Processor
DESCRIPTION (Continued)
The SSI 32P5402 is a dual-ground version for use in
noisier environments. In order to provide this feature
the numberof head select lines is reduced to two. The
SSI32P5403 has dual grounds and an open-collector
RD output instead of a differential line-driver output.
When used with a read/write preamplifier (i.e.
SSI32R117 or SSI 32R501), the SSI 32P540 or
SSI 32P5402 and required external passive components perform all read/write signal processing necessary between the heads and the interface connector of
an ST506 compatible Winchester disk drive. A line
driver is required with the SSI 32P5403 .
The amplifier is followed by an active differentiator
whose external network serves to transform peaks in
the input signal into zero-crossings while maintaining
the time relationship of the original input peaks. Differentiator response is set by an external capacitor or
more complex series. LRC network between the DIF+
and DIF- pins. The transfer .function with such a
network is:
Av2
-1420 Cex s
LexCex s2 + (Rex +46) Cex s + 1
where Cex = external capacitor (50 pF to 250 pF)
Rex = external resistor
Lex = external inductor
CIRCUIT OPERATION
In both read and write modes, Schmitt Trigger inputs
are u sed to buffer the three head select lines providing
the increased noise immunity required of a ST506
interface. A power supply monitoring function, VFLTB,
is provided to flag a low voltage fault condition if either
supply is low. A low voltage fault condition results in a
low level output on the VFLTB pin.
READ MODE
In the read mode (MODE input high) the read signal is
detected, time domain qualified and made available at
RD+ and RD- as differential MFM encoded data, or at
the RD+ open collector output. This is accomplished
by the on-board Amplifier, Differentiator, Zero Crossing Detector, Time Domain Filter, Output One Shot and
Line Driver circuits.
The amplified and filtered read back signal, which
contains pulses corresponding to magnetic transitions
in the media is AC coupled into the input amplifier. A
resistor, Rg, connected between pins G+ and G- is
used to adjust the 1st stage amplifier gain according to
the following expression.
Av1 =~ Where Rx _ 94 x ( Rg +42)
17+Rx
230+Rg
s = js= j21tf
Total gain from IN+ and IN- to OUT+ and OUT- is:
Av = Av1 x Av2
To reduce pulse pairing (bit shift), it is essential that the
input to the zero-crossing detector be maximized to
reduce the effect of any comparator offset. This means
that the above gains should be chosen such that the
differential voltage at OUT+ and OUT-approaches
5 Vpp at max input and frequency.
The Differentiator output is AC coupled into a zerocrossing detector that provides an output level change
at each positive or negative zero transition on its input.
The zero-crossing detector output is coupled to a Time
Domain Filter that eliminates false triggering of the
output one-shot by spurious zero-crossings. The validity decision is based on a minimum duration between
zero crossings that can be set externally by an RC
network on the TO pin.
The output of the Time Domain Filter triggers a oneshot that defines the output pulsewidth based on an
external RC network on the PW pin. These output
pulses are fed into a line driver that provides a highcurrent differential output at RD+ and RD-, or are made
available as an open-collector output at RD+.
WRITE MODE
First Stage gain can be monitored atthe DIF+ and DIFpins.
In the write mode (MODE input low) the differential line
receiver is enabled. This receiver accepts the differential data from the ST506 interface and outputs a TIL
Signal for the write data input of an external R/W
2-2
0888 I
SSI 32P540-Series
Read Data Processor
analog signal lines as short as possible and balanced.
Analog test points should be provided with a probe
ground in the immediate vicinity. Do not run digital
signals under the chip or next to analog inputs. Use of
a ground plane is recommended along with supply
bypassing and separation of the SSI 32P540 ground
from other circuits on the disk drive PCB.
amplifier. A low on the MODE input also puts the read
outputs in a high impedance state, allowing several
SSI 32P540's to be multiplexed on a bus.
LAYOUT CONSIDERATIONS
The SSI 32P540 is a high gain wide bandwidth device
that requires care in layout. The designer should keep
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, 4.5V < Vee < 5.5V, 10.8V < Vdd < 13.2V, 25 °C < T(junction) < 135 °C.
ABSOLUTE MAXIMUM RATINGS
Operation above absolute maximum rating may permanently damage the device.
RATING
UNIT
5V Supply Voltage, Vee
6
V
12V Supply Voltage, Vdd
14
V
PARAMETER
Storage Temperature
-65 to +150
°C
Operating Temperature, Tj
+25 to +135
°C
Lead Temperature (soldering 10 sec)
260
°C
0.3 to Vdd + 0.3
V
-0.3 to Vee + 0.3 or 100 mA
V
-0.3 to Vcc + 0.3
V
Pin Voltages: IN+, IN-, G+, G-, DIF +, DIF-,
OUT +, OUT-, DIN + DIN RD +, RD - , WRTOUT, HSO, HS1, HS2, VFLTB
TO, PW, MODE, WRT +, WRT-, HSOB,
HS1B,HS2B
POWER SUPPLY
0888
PARAMETER
CONDITIONS
NOM
MAX
UNIT
lee - Vcc Supply Current
Read mode, no TIL or
RD± loads
35.0
46
mA
Write/Disable mode,
no TIL loads
36.5
43
mA
Idd - Vdd Supply Current
Read mode
33.5
48
mA
Write/Disable mode
34.5
Pd - Power Dissipation
Tj
= 135 °C Read/Write modes
2-3
MIN
50
mA
820
mW
SSt 32P540-Series
Read Data Processor
LOGIC SIGNALS - MODE
PARAMETER
MIN
CONDITIONS
-0.3
Input Low Voltage (VIL)
Input Low Current (IlL)
VIL = 0.4V
2.0
Input High Voltage (VIH)
Input High Current (IIH)
NOM
VIH =2.4V
MAX
UNIT
+0.8
V
-0.8
mA
V(X; + 0.3
V
100
I1A
LOGIC SIGNALS - HSnB
PARAMETER
CONDITIONS
MIN
MAX
UNIT
Threshold VoHage,
VT + Positive-Going
Vcc= 5.0V
1.4
NOM
2.0
V
Threshold Voltage,
VT - Negative-Going
Vee = 5.0V
0.6
1.15
V
Input Low Current (IlL)
VIL = 0.4V
-0.4
mA
Input High Current (IIH)
VIH =2.4V
100
I1A
MAX
UNIT
0.4
V
LOGIC SIGNALS - WRTOUT, HSn
PARAMETER
CONDITIONS
Output Low VoHage (VoL)
IOL= 1.6 ma
Output High Voltage (VOH)
IOH = -500 I1A
MIN
NOM
2.4
V
LOGIC SIGNALS - VFLTB & RD Open Collector Output
PARAMETER
CONDITIONS
Output Low Voltage (VoL)
IOL = 1.6 mA 4.5 < Vcc < 5.5
IOL = 0.5 mA,1.0 < Vee < 4.5V
(VFLTB Only)
MIN
NOM
Output High Current (IOH)
MAX
UNIT
0.4
V
25
I1A
MODE CONTROL
PARAMETER
MIN
MAX
UNIT
Read to Write Transition Time
CONDITIONS
1.0
I1s
Write to Read Transition Time
1.0
IJ.S
2-4
NOM
0888
SSI 32P540·Series
Read Data Processor
SUPPLY VOLTAGE FAULT DETECT
PARAMETER
CONDITIONS
MIN
MAX
UNIT
Vdd Fault Threshold
VFLTB transition from
high to low
9.5
10.8
V
Vcc Fault Threshold
VFLTB transition from
high to low
4.3
4.6
V
CONDITIONS
MIN
MAX
UNIT
NOM
WRITE MODE
PARAMETER
Differential Input Voltage
NOM
±0.4
Input Hysteresis
V
±40
Single Ended Input Resistance
4.0
Input Common Mode Voltage
Range
0.0
Input Pulse Width
mV
Kn
5.0
20
V
ns
Propagation Delay
(WRT + & WRT - TO WRTOUT)
V (WRT+ - WRT-) = 0 to
WRTOUT = 1.3V
See Note & Fig. 1 TPD
40
ns
Output Rise and Fall times
WRTOUT transition from 0.7
to 1.9V, See Note & Fig. 1
15
ns
Note: WRTOUT load is 30 pF to GND and 2.5 Kn to Vee
READ MODE
Unless otherwise specified RD+ and RD- are loaded with 1DOn differentially and 30 pF per side to GND, IN+
and IN - are AC coupled, G+ and G- are open. An 800n resistor is tied between the DIF+ and DIF - pins with
each pin loaded to GND with < 3 pF. The OUT+ and OUT- pins are loaded with < 3 pF in parallel with> 5 KQ
AC coupled (i.e. no DC current).
AMPLIFIER & ACTIVE DIFFERENTIATOR
PARAMETER
CONDITIONS
MIN
MAX
UNIT
Differential
RG
7.2
12.6
VN
Voltage Gain (IN± to OUH)
= co, Rex = 800n
RG = OQ, Rex = 200n
72
155
Bandwidth
-3 dB point
30
Common Mode Input
Impedance (IN±)
0888
Differential Input
Resistance (IN±)
V(IN+ - IN-) = 100 mVpp,
2.5 MHz, AC coupled
Differential Input
Capacitance (IN±)
V(IN+ - IN-) = 100 mVpp,
2.5 MHz, AC coupled
2-5
NOM
VN
MHz
3.5
Kn
6.0
Kn
8
pF
SSI 32P540·Series
Read Data Processor
AMPLIFIER & ACTIVE DIFFERENTIATOR (Continued)
PARAMETER
CONDITIONS
MAX
UNIT
Input Noise (IN±)
Inputs shorted together
RG = on, Rex = 200n
10
nV/-JHZ
V(DIF+ DIF-) Output Swing
Set by RG
3.2
Vpp
V(OUT+ -) Output Swing
Set by Rex, Lex,
Cex Impedance
5
Vpp
Dynamic Range
Common mode DC input
where gain falls to 90% of
O.OV DC common mode input.
10 mVpp AC input, RG = 00,
Rex = 1200n
+240
mV
MIN
NOM
-240
DIF+ to DIF- pin Current
±1.9
mA
OUT+ to OUT- pin Current
±3.8
mA
CMRR (input referred)
V(IN+) = V(IN-) = 100 mVpp,
5 MHz, RG = on, Rex = 200n
40
dB
PSRR (input referred)
Vdd or Vee = 100 mVpp,
5 Mhz, RG = on, Rex = 200n
40
dB
ZERO CROSSING DETECTOR
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNIT
Input Offset Voltage
5.0
mV
Input Signal Range
5.0
Vpp
Differential Input
Impedance (DIN±)
4.4
Kn
LINE DRIVE (SSI 32P540 & SSI 32P5402 only)
PARAMETER
CONDITIONS
Output Sink Current
VOL = 0.5V, V(MODE) = 2.0V
Output Source Current
VOH = 2.5V, V(MODE) = 2.0V
-2
Output Current
Vo=OV to Vcc, V(MODE) = OV
-50
50
JJA
Output Rise Time
Vo = 0.7V to 1.9V 100n
between RD+ and RD-,
30 pFto GND
2
30
ns
Output Fall Time
Vo = 1.9V to 0.7V 100n
between RD+ and RD-,
30 pFtoGND
2
30
ns
MIN
2-6
NOM
MAX
20
UNIT
mA
mA
0888
!
SSI 32P540-Series
Read Data Processor
TIME DOMAIN FILTER
PARAMETER
CONDITIONS
MIN
Delay Range
TTOl = 0.184 X RTD X CTo,
RTO = 1.5 Knto 3.1 Kn,
CTD = 50 pF to 200 pF,
V(DIN+ - DIN-) = 100 mVpp,
5 MHz, AC coupled square
wave. See Figure 2
13.8
Delay Range Accuracy
Vee = 5.0V, Tj
Propagation Delay
NOM
= 60°C
MAX
UNIT
114
ns
±15
ns
Variation with supply and
temperature
12
ns
Delay = T02 - TOl See Fig. 2
80
ns
MAX
UNIT
80
ns
5
ns
DATA PULSE
PARAMETER
CONDITIONS
Pulse Width
Tpw = 0.184 x Rpw x
Cpw, Rpw = 2 Kn,
Cpw = 150 pF. See Figure 2
Skew
V(DIN = - DIN -) = 100 mVpp,
5 MHz, AC coupled square
wave w/2 nsec rise & fall times
MIN
NOM
30
V (WRT + - WRT·)
,
~~'-l
----------------------r---l
1.9V WRTOUT 1.3V .- -------------------
O.7V .- ------------------
=l
TRISE
FIGURE 1: WrHe Mode Timing
0888
2-7
j:=
TFALl
IJ
SSI 32P540-Series
Read Data Processor
FIGURE 2: Read Mode Timing
APPLICATIONS INFORMATION
GAINSETIING
DESIGN EXAMPLE
So calculating for nominal gain:
Maximum gain from the amplifier occurs when RG = O.
As a design example a system using a 4-Channel
SSI32R117 ReadlWrite preamplifier will be used.
Rx=94x42 =17.17
230
Assumptions - coding scheme is MFM
AV1 =
- data rate is 5 Mbitslsecond
- Ferrite head output is 1 mVpp
min. and 2 mVpp max.
The output from the SSI 32R117 is 80 mVpp to
240 mVpp. Assuming a 6 dB loss through the extemal
low pass filter the input to the SSI 32P540 at IN+, INis:
628
_
19.9 nominal or
17+17.17
16.52 min. to 23.28 max.
The voltage swing at the DIF+, DIF- pins is:
120 mVpp x 22.25 =2.79 Vpp maximum.
40 mVpp x 17.55 = 0.661 Vpp minimum.
This is within the 3.2 Vpp maximum guaranteed by this
specification, so maximum gain will be used.
40 mVpp to 120 mVpp differential voltage.
Forthis analysis the ± 37"/0 tolerance on gain from IN+,
IN- to OUT+, OUT- will be equally divided between the
gain stage and the differentiator, so each will contribute
a ±17% variance from nominal values. The objective
is to get a 5 Vpp signal at OUT+, OUT-at max input and
maximum frequency. For MFM the 2f frequency in a
5 Mbits/s data rate is 2.5 MHz, 1f is 1.25 MHz.
2-8
0888
o
a>
&l
+~N
,,,,,optional
O.1JLF
GND
+12V
*
O.1p.F
'''''
I\)
I
to
:tJ
(I)
mC/)
CoC/)
RIW we wus t:!
1.1K
10pH
C-
mW
-I\)
FIGURE 3: Typical Application
m."
."Ul
""'I~
0
0
(')
I
(l)C/)
en
en
o
""'I
(I)
::::!.
(I)
en
551 32P540-5eries
Read Data Processor
DlFFERENTIATOR DESIGN
The differentiator can be as simple as a capacitor or as
complex as a series RLC network. In order not to
violate the 5 Vpp maximum specification at OUT+,
OUT- the maximum differential voltage gain is:
Check for current saturation using the following formula:
=
Ip
j Vp21tfCex
1+j21tfCex(R+46)
For Rex, Cex, and Lex networks, the following formulae are used:
~= 1.79 maximum gain
2.79
.
GainG _
which is nominally a gain of 1.53
For Cex only:
-j 142OCex21tf
1-LexCex (21tf)2+H Rex +46) Cex27tf
1420 Cex 21tf
Cex
1.53
-68pF
21trV( 1420)2_( 1.53x46)2
1[1- Lex Cex (21tf)2J2 +[( Rex +46) Cex 21tf] 2
_~_1an-1 [( Rex +46) (Cex 21tf)]
2
1-LexCex(21tf)2
check for current saturation:
J
Ic = Cex x Vp x 2m must be less than 1.9 rnA
For Cex, Rex network:
Center Fl"ElCJ.lency fn -
The following two formulas are used:
1.53_~~j~1_4ro~Ce~x~2~1tf~_
j( Rex +46) Cex 21tf+ 1
Rex +46
--=---:-~~~
1
21t"Lex Cex
OarJl)ing Facu ~= ( Rex +46) Cex
2
"LeXcex
__
CexA 21tfmaximum
where A is chosen for position of comer frequency
to reduce high frequency noise gain from the single
capacitor network. Graphically the method is as
follows:
Noise gain
IC(I)
reduction
--Cex
--~--
only
Cex, Rex series
This technique adds another pole to the differentiator
response to attenuate high frequency noise. The
center frequency damping ratio and group delay are
chosen to meet system requirements. Values for the
center frequency are usually from 2 to 10 fmax and the
damping factor may be from 0.3 to 1. Graphically the
method is as follows:
network
1,(1)
11
21
AI
2ltIVln(1)
11
2-10
21
In
2o:IVIn (I)
0888
SSI 32P540-Series
Read Data Processor
As with the previous Rex, Cex example, care must be
taken to insure a 90° phase shift at the frequencies of
interest (1f and 2f or 1.25 MHz and 2.5 MHz). This
requirement is modified by any need to compensate for
phase distortion caused by preceding signal processing.
EFFECT OF GAIN TOLERANCE
any distortion to this harmonic. For this reason, the
most common filter type used is a Bessel Filter which
has a constant group delay(dII» or linear phase shift.
df
Thus for a 5 Mbitls MFM waveform a Bessel Filterwith
constant group delay and a -3 dB point of 3.75 MHz is
required. This is the type of filter is used in the design
example.
At minimum gain the 1 mVpp input at 1.25 MHz frequency has the following effects:
Using the capacitor only results with Cex = 68 pF
Diflerential Gain -
1420Cex 27tf
'11 +(46Cex27tf)2
-0.758 nom.
Using ± 17% tolerance, min gain = 0.629
FIGURE 3: Outer Track Waveform
So with a 661 mVpp input the minimum voltage
@OUT+, OUT- is 416 mVpp.
-.-,-~-
Thus, with all tolerances considered, a 1 mVpp to
2 mVpp input to the SSI 32R117 will result in a 5 Vpp
to 416 mVpp input to the zero-crossing detector.
,
COMPARATOR
OUfPUT
ONE-SHOT CONSIDERATIONS
:---1
--1JI-...:
AI
:
The timing for both one shots conform to the same
equation:
:
,
l
iI
:
i
I
,
r-"--+-- .---1
t
t = 0.184 x C x R
Setting of the time domain one-shot reflects the expected base line shouldering effect at the 11 frequency
and is set accordingly. In this example the output pulse
width has been set at approximately 30 nsec and the
time domain filter at approximately 80 nsec.
EXTERNAL FILTER
The filter on the output of the readlwrite amplifier, limits
the bandwidth of the input to the SSI 32P540. This
reduces the noise input to the differentiator which can
produce spurious zero-crossings. The design of this
filter is not discussed here, but general aspects of its
transfer function will be diacussed.
On the outer tracks of an ST506 compatible drive using
a MFM coding technique, the output pulses return to
baseline or exhibit shouldering as shown in Figure 3.
This waveform has a high third harmonic content. In
order to preserve this waveform the filter must not add
0888
(RO.,RD-)
,
:
I:·
2-11
FIGURE 4:
Effect of Comparator Offset on Output Waveform
BIT SHIFT OR PULSE PAIRING
Theoretical consideration of this aspect of pulse replication relative solely to the SSI 32P540 indicates that
comparator offset is the major contributing parameter.
For sinusoidal inputs the offset produces a non-symmetric waveform as shown in Figure 4.
The RD+, RD-outputpulses have beenoffsetfromtrue
position (zero-crossing) by an amount £\t, that is dependent on Voffset and OUT+, OUT- amplitude.
This relationship is:
551 32P540-5eries
Read Data Processor
So, referring to previous resuHs:
when OUT+, OUT-
Using this technique and a sinusoidal input to DIN± of
varying amplitude at 1.25 MHz and 2.5 MHz, the
following resuHs were obtained.
5 Vpp @2.5 MHz
at
0.13 nsec
when OUT+, OUT-
DIN± Input
416 mVpp@1.25MHz
at
vp-p
3.1 nsec
1.25 MHz
2.5 MHz
0.6
1.0
3
0.6
0.8
1
0.6
0.0
.7
1.4
0.0
.3
1.6
0.5
.1
3.8
1.2
.07
5.6
2.4
.06
6.2
3.2
.05
7.0
3.5
.04
9.6
4.5
.03
11.8
6.0
5
As can be seen in Figure 4, the center pulse has been
shifted from its true position by 2 at. So forthis example
the Bit Shift contributed by the SSI 32P540 is:
0.26 nsec at maximum input and frequency
6.2 nsec at minimum input and frequency
In some literature this effect is called Pulse Pairing. If
the RD+, RD- waveform is displayed on an oscilloscope with the trigger holdoff adjusted to fire on succeeding pulses the following waveform is observed:
RD± Pulse JIHer (4at) nsec
Pulse Pairing
where t2 - t 1, = 4 at or 2 x (Bit Shift)
PACKAGE PIN DESIGNATIONS
CAUTION: Use handling procedures necessary
lor a static sensitive component.
(TOP VIEW)
DIF·
DIF·
MOllE
MOllE
MODE
OUT+
OUT+
OUT+
OUT·
OUT·
OUT·
HSD
HSD
HSO
DIN+
DIN+
DIN+
DIN-
DIN-
DIN·
HS1B
HSIa
HSia
HSI
HSi
HSI
OS1
VFLTB
OS1
WATOUT
AD.
VFLTB
OS1
WATOUT
WATOUT
0S2
AIJ..
OS2
HS2B
WAT+
AD.
WAr+
HS2
WAr·
NC
WAT·
32P540
28-Pin PDIP
DIF-
32P5402
28-Pln PDIP
2-12
AD.
0S2
HS2B
WAr+
HS2
WAr·
32P5403
28-Pln PDIP
0888
SSI 32P540-Series
Read Data Processor
THERMAL CHARACTERISTICS: 0
PACKAGE PIN DESIGNATIONS (Continued)
(TOP VIEW)
Is
28-Pin PDIP
28-Pin PLCC
+
"
4321282728
25
12
13
14
15
i ~ ! ~
16
i
17
iii
OUT·
G-
IN+
•
•
24
HSO
23
DIN+
IN-
22
DIN·
AGND
21
HS1B
DGND
20
HS1
VFLTB
10
19
OS1
V.
11
N
>
• •
to
I
is
oJ:
~
~ a
2
1
28
V
4321282726
28
7
•
•
18
12
I
~
32P540
28-Pln PLCC
,.
14
,. ,.
Ii
~
~
~
~
17
,.
~
§
DGND
G
VFLTB
10
V5
l'
~
32P5402
28-Pln PLCC
12
13
14
15
16
17
18
i;~ii!ll
32P5403
28-Pln PLCC
ORDERING INFORMATION
PART DESCRIPTION
ORDERING NUMBER
PACKAGE MARK
SSI 32P540 Read Data Processor
28-Pin PDIP
SSI 32P540-CP
SS132P540-CP
Dual GND PDIP
SS132P5402-CP
SSI 32P5402-CP
28-Pin PLCC
SSI 32P540-CH
SSI 32P540-CH
Dual GND PLCC
SSI 32P540-CH
SSI 32P540-CH
Dual GND/Open Collector PDIP
SS132P5403-CP
SSI 32P5403-CP
Dual GND/Open Collector PLCC
SSI 32P5403-CH
SSI 32P5403-CH
No responsibility is assumed by SSi for use of this product nor for any infringements of patents and trademarks or other rights of third parties
resulting from its use. No license is granted under any patents, patent rights or trademarks of SSi. SSi reserves the right to make changes
in specifications at any time without notice.
Silicon Systems, Inc., 14351 Myford Road, Tustin,
0888
CA 92680 (714) 731-7110, TWX 910-595-2809
©1988 Silicon Systems, Inc.
2-13
NOTES:
SSI32P541
Read Data Processor
INNOVATORS IN INTEGRATION
-----------------------------------------------------August, 1988
DESCRIPTION
FEATURES
The SSI 32P541 is a bipolar integrated circuit that
provides all data processing necessary for detection
and qualification of MFM or RLL encoded read signals.
The circuit will handle data rates up to 15 Mbits/sec.
•
In read mode the SSI 32P541 provides amplification
and qualification of head preamplifier outputs. Pulse
qualification is accomplished using level qualification
of differentiated input zero crossings. An AGC amplifier is used to compensate for variations in head
preamp output levels, presenting a constant input level
to the pulse qualification circuitry. The AGC loop can
be disabled so that a constant gain can be used for
embedded servo decoding or other processing needs.
Level qualification supports high resolution MFM
and RLL encoded data retrieval
•
•
•
•
Wide bandwidth AGC input amplifier
•
Write to read transient suppression
•
Fast and slow AGC attack regions for fast transient
Supports data rates up to 15 Mbits/sec
Standard 12V ± 10% and 5V ± 10% supplies
Supports embedded servo pattern decoding
recovery
Inwrite mode the circuitry is disabled and the AGC gain
stage input impedance is switched to a lower level to
allow fast setting of the input coupling capacitors during
a write to read transition. The SSI 32P541 requires
+5V and + 12V power supplies and is available in a
24-pin DIP and 28-pin PLCC.
BLOCK DIAGRAM
COUT
RD
LEVa.
0888
HYS
2-15
Door
os
I
SSI32P541
Read Data Processor
CIRCUIT OPERATION
READ MODE
In the read mode (RlWB input high or open) the input
read signal is amplified and qualified using an AGC
amplifier and pulse level qualification of the detected
signal peaks.
The amplified head signals are AC coupled to the IN +
and IN -pins ofthe AGC amplifier that isgain controlled
by full wave rectifying and amplifying the (DIN+ - DIN-)
voltage level and comparing itto a reference level atthe
AGC pin. A fast attack mode, which supplies a 1.7 rnA
charging current for the capacitor at the BYP pin, is
entered whenever the instantaneous DIN ± level is
more than 125% of set level. Between 100% and 125%
the slow attack mode is invoked, providing 0.18 rnA of
charging current. The two attack modes allow rapid
AGC recovery from a write to read transition while reducing zero crossing distortion once the amplifier is in
range.
The level at the AGC pin should be set such that the
differential voltage level at the DIN+, DIN- pins is 1.00
Vpp althe OUT+, OUT-pins which allows forupto 6 dB
loss in any external filter connected between the
OUT+, OUT- outputs and the DIN+, DIN-inputs.
setting the AGC slow attack and decay times slow
enough to minimize distortion of the clock path signal.
This '1eed-forward" technique, utilizing a fraction of the
rectified data path input available at the LEVEL pin as
the hysteresis threshold, is especially useful inthe slow
decay mode of the AGC loop. By using a short time
constant for the hysteresis level, the qualification
method can continue as the AGC amplifier gain is
slowly ramped up. This level will also shorten the write
to read transient recovery time without affecting data
timing as the circuit will be properly decoding before the
AGC gain has settled to its final value. The comparator
output is the "D" input of a D type flip-flop. The DOUT
pin provides a buffered test point for monitoring this
function.
The filtered clock path signal is differentiated to transform signal peaks to zero-crossings which clock an
edge-trigger circuit to provide output pulses at each
zero-crossing. The pulses are used to clock the D type
flip-flop. The COUT pin is a buffered test point for
monitoring this function.
The differentiatorfunction is set by an external network
between the DI F+, DIF- pins. The transfer function is:
AV=
Gain of the AGC section is nominally
Where: C = external capacitor (20 pF to 150 pF)
L = external inductor
Av2 =exp- Vl- V1
Av1
5.8+'11
Where: Av1 and Av2 are initial and final amplifier
gains. V1, V2 are initial and final voltages
on the BYP pin.
Vt = (K x T)/q = 26 mV at room temperature.
One filter for both data (DIN+, DIN- input) and clock
(CIN+, CIN- input) paths, or a separate filter for each
path may be used. If two filters are used, care must be
exercised to control time delays so that each path is
timed properly. A multi-pole Bessell filter is typically
used for its linear phase or constant group delay
characteristics.
The filtered data path signal is fed into a hysteresis
comparator that is set at a fraction of the input signal
level by using an external filter/network between the
LEVEL and HYS pins. Using this approach allows
-2000Cs
LCs2 +( R+92)CS+1
R = external resistor
s = jw = j211f
During normal operation the differentiatorcircuit clocks
the D flip-flop on every positive and negative peak of
the signal input to CIN+, CIN-. The D input to the
flip-flop only changes state when the signal applied to
the DIN+, DIN- inputs exceeds the hysteresis comparator threshold opposite in polarity to the previous
peak that exceeded the threshold.
The clocking path, then, determines signal timing and
the data path determines validity by blocking signal
peaks that do not exceed the hysteresis comparator
threshold.
The delays from CIN+, CIN- inputs to the flip-flop clock
input and from the DIN+, DIN- inputs to the flip-flop D
input are well matched.
2-16
0888
SSI32P541
Read Data Processor
WRITE (DISABLED) MODE
In the write or disabled mode (R/WB input low) the
digital circuitry is disabled and the AGC amplHier input
impedance is reduced. In addition the AGC amplHier,
gain is set to maximum so that the loop is in·its fast
attack mode when changing back to Read Mode. The
lowered input impedance facilitates more rapid settling
of the write to read transient by reducing the time
constant of the network between the SSI 32P541 and
read/write preamplifier, such as the SS132R510.
that requires care in layout. The designer should keep
analog signal lines as short as possible and well
balanced. Use of a ground plane is recommended
along with supply bypassing and separation of the
SSI32P541 and associated circuitry grounds from
other circuits on the disk drive PCB.
MODE
RWIB
HOLDB
1
1
READ - Read amp on, AGC active, Digital section active
1
0
HOLD - Read amp on, AGC
gain held constant Digital section active
0
X
WRITE - AGC gain switched to
maximum, Digital section inactive, common mode input resistance reduced
Internal SSI 32P541 timing is such that this settling is
accomplished before the AGC loop is activated when
going to read mode. Coupling capacitors should be
chosen with as Iowa value as possible, consistent with
bandwidth requirements, to allow more rapid settling.
LAYOUT CONSIDERATIONS
The SSI 32P541 is a high gain wide bandwidth device
PIN DESCRIPTION
NAME
TYPE
VCC
VDD
12 volt power supply
AGND, DGND
Analog and Digital ground pins
R/WB
I
TTL compatible read/write control pin
IN+,IN-
I
Analog signal input pins
OUT+,OUT-
0
AGC AmplHier output pins
HOLDB
I
TTL compatible pin that holds the AGC gain when pulled low
AGC
I
Reference input voltage level for the AGC circuit
DIN+, D1N-
I
Analog input to the hysteresis comparator
I
Hysteresis level setting input to the hysteresis comparator
BYP
HYS
The AGC timing capacitor is tied between this pin and AGND
LEVEL
0
Provides rectHied signal level for input to the hysteresis comparator
DOUT
0
Buffered test point for monitoring the flip-flop D input
CIN+, CIN-
I
Analog input to the differentiator
DIF+, DIFCOUT
Pins for extemal differentiating network
0
OS
RD
OBBB
DESCRIPTION
5 volt power supply
Buffered test point for monitoring the clock input to the flip-flop
Connection for read output pulse width setting capacitor
0
TTL compatible read output
2-17
I
SSI32P541
Read Data Processor
ELECTRICAL CHARACTERISTICS
Unless otherwise specified 4.5 ~ VCC ~ 5.5V, 1O.SV ~ VDD ~ 13.2V, 25 °C ~ Tj ~ 135°C.
ABSOLUTE MAXIMUM RATINGS
Operation above absolute maximum ratings may permanently damage the device.
PARAMETER
RATING
UNIT
5V Supply Voltage, VCC
6
V
12V Supply Voltage, VDD
14
V
Storage Temperature
-65 to 150
°C
260
°C
Lead Temperature
-0.3 to VCC + 0.3
V
-0.3V to VCC + 0.3V or +12
rnA
-0.3 to VDD + 0.3
V
R/WB, IN+, IN-, HOLD
RD
All others
POWER SUPPLY
PARAMETER
CONDITIONS
ICC - VCC Supply Current
IDD - VDD Supply Current
Pd - Power Dissipation
MIN
NOM
MAX
UNIT
Outputs unloaded
14
rnA
Outputs unloaded
70
rnA
Outputs unloaded, Tj = 135°C
730
mW
MAX
UNIT
O.S
V
LOGIC SIGNALS
PARAMETER
CONDITIONS
MIN
VIL - Input Low Voltage
-0.3
VIH - Input High Voltage
2.0
NOM
V
IlL - Input Low Current
VIL = O.4V
-0.4
rnA
IIH - Input High Current
VIH = 2.4V
100
J.tA
VOL - Output Low Voltage
IOL=4.0 rnA
0.4
V
VOH c Output High Voltage
IOH = -400 J.tA
2.4
CONDITIONS
MIN
0.0
V
MODE CONTROL
PARAMETER
Read to Write Transition Time
Write to Read Transition Time
AGC settling not included,
transition to high input
resistance
Read to Hold Transition Time
2-18
1.2
NOM
MAX
UNIT
1.0
~s
3.0
~
1.0
~s
0888
551 32P541
Read Data Processor
WRITE MODE
PARAMETER
CONDITIONS
Common Mode Input Impedance
(both sides)
RlWB pin = low
MIN
NOM
MAX
250
UNIT
0
READ MODE
Unless otherwise specified IN+ and IN- are AC coupled, OUT+, and OUT-are loaded differentially with> 6000
and each side is loaded with < 10 pF to GND, a 2000 pF capacitor is connected between BYP and GND, OUT+
is AC coupled to DIN+, OUT- is AC coupled to DIN-, AGC pin voltage is 2.2 VDC.
AGC AMPLIFIER
PARAMETER
CONDITIONS
Differential Input Resistance
V(IN+ -IN-)
@2.5MHz
= 100 mVpp
Differential Input Capacitance
V(IN+ -IN-)
@2.5MHz
= 100 mVpp
Common Mode Input Impedance
RlWB pin high
(both sides)
MIN
1.0 Vpp S V(OUT+ - OUT-)
S2.5 Vpp
Input Noise Voltage
Gain set to maximum
Bandwidth
Gain set to maximum
-3 dB point
Maximum Output Voltage Swing
Set by AGC pin voHage
OUT+ to OUT- Pin Current
No DC path to GND
Output Resistance
1.8
pF
KO
0.25
4.0
UNIT
0
10
KO
83
VN
30
nV/-JHz
30
MHz
3.0
Vpp
rnA
±3.2
13
32
15
pF
0.37
0.56
VppN
8
%
Output Capacitance
0888
MAX
5K
RlWBpin low
Minimum Gain Range
NOM
0
(DIN+ - DIN-) Input VoHage
Swing VS AGC Input Level
30 mVpp V(IN+ - IN-)
S 550 mVpp 0.5 Vpp
S V(DIN+ - DIN-) S 1.5 Vpp
(DIN+ - DIN-) Input VoHage
Swing Variation
30 mVpp V(IN+ - IN-)
S 550 mVpp AGC Fixed,
over supply & temperature
Gain Decay Time (Td)
Vin = 300 mVpp-> 150 mVpp
at 2.5 MHz, Vout to 90% of
final value Figure 1a
50
IJ.S
Gain Attack time (Ta)
From Write to Read transition
to Vout at 110% of final value
Vin = 400 mVpp @ 2.5 MHz.
Figure 1b
4
IJ.S
2-19
I
SSI32P541
Read Data Processor
AGC AMPLIFIER
(Continued)
PARAMETER
CONDITIONS
MIN
MAX
UNIT
Fast AGC Capacitor Charge
Current
V(DIN+ - DIN-) = 1.6V
V(AGC) = 2.2V
1.3
2.0
mA
Slow AGC Capacitor Charge
Current
V(DIN+ - DIN-) = 1.6V Vary
V(AGC) until slow discharge
0.14
0.22
mA
Fast to Slow Attack Switchover
Point
V(DIN+-DIN-)
V(DIN+-DIN-) Final
AGC Capacitor Discharge Current
V(DIN+ - DIN-)
NOM
1.25
= O.OV
~
4.5
Read Mode
CMRR (Input Referred)
V(IN+) = V(IN-) = 100 mVpp
@ 5 MHz,gain at max.
40
~
dB
PSRR (Input Referred)
l!VCC or l!VDD = 100 mVpp
@ 5 MHz, gain at max.
30
dB
Hold Mode
-0.2
+0.2
HYSTERESIS COMPARATOR
PARAMETER
CONDITIONS
MIN
NOM
Input Signal Range
Differential Input Resistance
V(DIN+ - DIN-)
@2.5MHz
= 100 mVpp
Differential Input Capacitance
V(DIN+- DIN-)
@2.5MHz
= 100 mVpp
Common Mode Input Impedance
(both sides)
Comparator Offset Voltage
HYS pin at GND, S; 1.5 KQ
across DIN+, DIN-
Peak Hysteresis Voltage vs HYS
pin voltage (input referred)
At DIN+, DIN- pins
1V < V (HYS) < 3V
HYS Pin Input Current
Level Pin Output
Voltage vs V(DIN+ - DIN-)
5
MAX
UNIT
1.5
Vpp
11
KQ
6.0
pF
KQ
2.0
10
mV
0.16
0.25
VN
1V < V (HYS) < 3V
0.0
-20
~
0.6 < I V (DIN+ - DIN-) I
<1.3 Vpp, 10 KQ from LEVEL
pinto GND
1.5
2.5
VNpp
LEVEL Pin Max Output Current
3.0
= 0.5 mA
mA
LEVEL Pin Output Resistance
I(LEVEL)
DOUT Pin Output Low Voltage
0.0 S; IOL S; 0.5 mA
VDD -4.0
VDD -2.B
V
DOUT Pin Output High Voltage
0.0 S; IOH S; 0.5 mA
VDD -2.5
VDD-1.B
V
2-20
Q
180
OB88
SSI32P541
Read Data Processor
ACTIVE DIFFERENTIATOR
PARAMETER
CONDITIONS
MIN
NOM
Input Signal Range
Differential Input Resistance
V(CIN+ - CIN-) = 100 mVpp
@2.5MHz
Differential Input Capacitance
V(CIN+ - CIN-) = 100 mVpp
@2.5MHz
Common mode Input Impedance
(both sides)
Voltage Gain From CIN± to DIF±
R(DIF+ to DIF-) = 2 Kg
DIF+ to DIF- Pin Current
Differentiator Impedance
must be set so as not to clip
signal at this current level
Comparator Offset Voltage
DIF+, DIF- are AC Coupled
5.8
MAX
UNIT
1.5
vpp
11.0
Kg
6.0
pF
Kg
2.0
1.7
2.2
±1.3
VN
mA
10.0
mV
COUT Pin Output Low Voltage
0.0 S 10H S 0.5 mA
VDD -3.0
V
COUT Pin Output Pulse voltage
V(high) - V(low)
0.0 S 10H S 0.5 mA
+004
V
COUT Pin Output Pulse Width
0.0 S 10H S 0.5 mA
30
ns
OUTPUT DATA CHARACTERISTICS (See Figure 2)
Unless otherwise specified V(CIN+ - CIN-) = V(DIN+ - DIN-) = 1.0 Vpp AC coupled since wave at 2.5 MHz
differentiating network between DIF+ and DIF- is 1OOnin series with 65 pF, V (Hys) = 1.8 DC, a 60 pF capacitor
is connected between OS and VCC, RD- is loaded with a 4 Kg resistor to VCC and a 10 pF capacitor to GND.
PARAMETER
CONDITIONS
D-Flip-Flop Set Up Time (Td1)
Min delay from V(DIN+ DIN-)
exceeding threshold to
V(DIF+ - DIF-) reaching
apeak
Propagation Delay (Td3)
Output Data Pulse Width
Variation
Td5 = 670 Cos,
50 pF S Cos S 200 pF
Logic Skew Td3 - Td4
0888
MIN
NOM
MAX
UNIT
ns
0
110
ns
±15
%
3
ns
Output Rise Time
VOH =2AV
14
ns
Output Fall Time
VOL = OAV
18
ns
2-21
551 32P541
Read Data Processor
(a)
FIGURE 1 (a), (b): AGe Timing Diagrams
+HYSTERESIS LEVEL
f-I----\----------.f--\--
-HYSTERESIS LEVEL I + - - - - ' , , . . . . - i - - - - - - -
V (COUT)
FLI P-FLOP CLOCK
FIGURE 2: Timing Diagram
2-22
0888
SSI32P541
Read Data Processor
TO SERVO CIRCUIT
[-
fl·,~ ;1-------="'--------'
iI
iI .00'""
I
I'
II
I
!
I
•
I
•
.
READ DATA
II
I
1.002
l""ll
I
I Rf~~~~J~E I ~
1
II
171-----1
I!
I
ANALOG
III
GROUND
l___! .----;'t----...-llJ-------{.r----l,,/------l.I--~}----5-0pI'-bU
..1--5V---J
V
1.54K
DIGITAL
GROUND
6.49K
L-~----------------------------~--------------------------------------ltsls system.
FIGURE 3: Typical Read/Wrlte Electronics Set Up
0888
2-23
SSI32P541
Read Data Processor
PACKAGE PIN DESIGNATIONS
(TOP VIEW)
DIF-
CIN+
DlF+
DIN+
AGC
0
g!
Z
J:
~
Ii.
'" '"
z+
(3
z+
c it0
4
3
2
1
28
Zl
26
CIN-
NC
DIN-
DIN-
OUT-
OUT-
OUT+
IN-
OUT+
AGND
HOLDB
21
AGND
BYP
BYP
VDD
DGND
VDD
DGND
COUT
DOUT
RlWB
12
13
14
15
16
17
~
~
0
g
ca:
0
RD-
os
VCC
z
z
18
':;
8
28-Lead PLCC
24·Lead PDIP, SOL
THERMAL CHARACTERISTICS: (2) Js
24-Lead PDIP
115·CIW
24-Lead SOL
SO·CIW
2S-Lead PLCC
65·elW
CAUTION: Use handling procedures necessary
for a s1atic sensitive component
ORDERING INFORMATION
PART DESCRIPTION
ORDERING NUMBER
PACKAGE MARK
SSI 32P541 Read Data Processor
24-Lead PDIP
SS132P541-P
SS132P541-P
28-Lead PLCC
SS132P541-CH
SS132P541-CH
24-LeadSOL
SSI 32P541-CL
SSI 32P541-CL
No resp0l;lsibility is assumed by SSi for use of this product nor for any infringements of patents and trademarks or other rights of third parties
resulting from its use_ No li08nse is granted under any patents. patent rights or trademarks of SSi. SSi reserves the right to make changes
in specifications at any time without notice.
Silicon Systems. Inc_. 14351 Myford Road. Tustin.
CA 92680 (714) 731-7110. 1WX 910-595-2809
@1988 SUicon Systems. Inc.
0888
2-24
SSI32P544
Read Data Processor
and Servo Demodulator
INNOVATORS IN INTEGRATION
August, 1988
DESCRIPTION
FEATURES
The SSI 32P544 Read Data Processor and Servo
Demodulator has a fully integrated bipolar circuit that
detects and validates amplitude peaks in the output
from a disk drive read amplifier, as well as detecting
embedded servo information to provide position error
signals used for read head positioning.
•
Wide bandwidth AGe Input amplifier
•
Level qualification supports MFM and RLL
encoded data retrieval
•
Fast and slow AGC attack and decay regions
for fast transient recovery
•
Embedded servo channel provides servo burst
capture and difference circuits
•
Local servo AGC provided based on servo
burst output amplitude sum
•
Standard ±10%, 12V and 5V supplies
•
Write to Read transient suppression
Time and amplitude qualification are used to provide a
TTL compatible output that accurately duplicates the
time position of input signal peaks. An AGe control
loop, using a dual rate charge pump, provides a constant imput amplitude for the level qualifier. Level
qualification can be implemented as a fixed threshold
or a constant percentage that tracks Signal amplitude
that enhances qualification during AGe loop transients.
(Continued)
BLOCK DIAGRAM
r==-::=J-------,
KEEP LEADS
RCS
l88
2-25
CIf.J)
SHO'"
SSI32P544
Read Data Processor
and Servo Demodulator
DESCRIPTION (Continued)
The Servo Demodulator consists of two peak detector
channels that capture rectified servo data peaks.
Buffered individual channel outputs are provided along
with a difference output. Servo channel gain can be
controlled by an AGC signal based on maintaining the
amplitude of the sum of both channels.
I(DIN+)-(DIN-) I is above 200 mVo-p a decay current,
controlled by a resistor from BYP1 to DECAY, is
switched in to decrease decay time. The amount of
charge pulled from the AGC timing capacitor on each
data pulse is:
QDECAY
= K1(Ton + Ts)/RDECAY
Where:
K1 = Constant defined in spec (4.0V, typ)
The circuit also provides a voltage fault flag that indicates a low voltage condition on either supply.
The SSI 32P544 requires standard +10% tolerance
+5V and +12V supplies and is available in a 44-pin
PLCC package.
CIRCUIT OPERATION
READ MODE
In Read Mode the SSI32P544 is used to process either
data or servo signals. In the Data Read Mode the input
signal is amplified and qualified using an AGC amplifier
and pulse level qualification of the detected signal
peaks. In the Servo Read Mode the input signal is
amplified and an error signal based on amplitude
comparison is made available.
Ton = Time in seconds that the data pulse at
DIN+/- is greater than 200 mVo-p
Ts = Switching time in seconds (4 ns, typ)
The AGC1 pin is internally biased so that the target
differential voltage input at DIN+/- is 1.0 Vp-p at nominal conditions. The AGC1 voltage can be modified by
tying a resistor between AGC1 and ground or VCC. A
resistor to ground decreases the voltage level while a
resistor to VCC increases it. The resultant AGC1
voltage level is:
Rx
5V
v
v
VAGe,
DATA READ MODE
= (5-V) Rirt
Rint + Ax
An amplified head output signal is AC coupled to the
IN+ and IN- pins of the AGC amplifier. Gain control is
accomplished by full wave rectifying and amplifying the
[(DIN+) - (DIN-)] voltage level and comparing it to a
reference voltage level at the AGC1 pin.
Where:
Two attack modes are entered depending on the
instantaneous level at DIN+/-. For DIN+/-Ievels above
125% of desired level a fast attack mode is invoked that
supplies 1.7 rnA charging current to the network on the
BYP1 pin. Between 125% and 100% of the desired
level the circuit enters a slow attack mode and supplies
0.18 rnA of charging current. This allows the AGC to
rapidly recover during a write to read transition but
reduces distortion once the AGC amplifier is in range.
The new DIN+/- input target level is nominally 0.48
Vp-pIVAGC1
Two decay modes are available that apply a discharge
current to the BYP1 pin network when DIN+/- falls
below the desired level. An internal decay current sink
will supply 4.5 J.IA of discharge current. Also, if
V = Voltage at AGC1 with pin open (2.2V, nom.)
Rint = AGC1 pin input impedance (6.7 Kil, typ.)
Rx = External resistor.
The AGC amplifier can swing 3.0 Vp-p at OUT+/- which
allows for up to 6 dB loss in any external filter between
OUT+/- and DIN+/-.
Gain of the AGC amplifier is nominally:
Av1/Av2 = e[6.9(V2.V1)]
Where:
Av1, Av2 are initial and final amplifier gains.
V1, V2 are initial and final voltages on the BYP1 pin.
2-26
0888
SSI32P544
Read Data Processor
and Servo Demodulator
The minimum output current from the AGC amplifier is
±3.2 mA. In cases where more current is required to
drive a low impedance load the current can be increased by connecting load resistors Ri from OUT+/- to
GNO, as shown below.
Out+
FILTER
Out-
Ri
lout min = ±3.2 mA + (6.S/Ri)
Where: Ri
~
2 Kn
One filter for both amplitude (OIN+/- input) and time
(CIN+/- input) channels, or a separate filter for each
may be used. If two filters are used, attention must be
paid to time delays so that each channel is timed
properly. A multi-pole Bessel filter is typically used for
its linear phase or constant group delay characteristics.
In the amplitude channel the signal is sent to a hysteresis comparator. The hysteresis threshold level is set
so that it will be tripped only by valid signal pulses and
not by baseband noise. It can be fixed level or a fraction
of the OIN+/- voltage level.
The latter approach is accomplished by using an external filter/network between the LEVEL and HYS pins.
This allows setting the AGC slow attack and decay
times slow enough to minimize time channel distortion
and setting a shorter time constant for the hysteresis
level. The LEVEL pin output is a rectified and amplified
version of OIN+/-, 1.0 Vp-pat OIN+/- results in 2.0 Vo-p
nominally, at the LEVEL pin. A voltage divider is used
from LEVEL to ground to set the Hysteresis threshold
at a percentage of the peak OIN+/- Voltage. For
example, if OIN+/- is 1.0 Vp-p, then using an equal
valued resistor dividerwill result in 1.0 Vo-p at the HYS
pin. This will result in a nominal ±0.21 OV threshold or
a 42% threshold of a ±0.500V OIN+/- input. The
capacitor is chosen to set an appropriate time constant.
This "feed forward" technique speeds up transient
recovery by allowing qualification of the input pulses
while the AGC is still settling. This helps in the two
critical areas of write to read and head change recovery. Some care in the selection of the hysteresis level
0888
time constant must be exercised so as to not miss
pattern (resolution) induced lower amplitude signals.
The output of the hysteresis comparator is the "0" input
of a 0 type flip-flop. The OOUT pin provides a buffered
TTL compatible comparator output signal for testing
purposes or for use in the servo circuit if required.
In the time channel the signal is differentiated to transform signal peaks to zero crossings which are detected
and used to trigger a bi-directional one-shot. The oneshot output pulses are used as the clock input of the 0
flip-flop. The COUT pin provides the one-shot output
for test purposes.
The differentiatorfunction is accomplished by an external network between the OIF+ and OIF- pins. The
transfer function from CIN+/- to the comparator input
(not OIF+/-) is:
Av
-1000(Abu~(Cs)
2LCs 2 + C(R + 92)s + 1
Where:
C, L, R are external passive components
20 pF < C < 150 pF
Abuf = Gain From CIN+/- to OIF+/-
s = Jro = J27tf
During normal operation, the time channel clocks the 0
flip-flop on every positive and negative peak of the
CIN+/- input. The 0 input to the flip-flop only changes
state when the DIN+/- input exceeds the hysteresis
comparator threshold opposite in polarity to the previous threshold exceeding peak.
The time channel, then, determines signal peak timing
and the amplitude channel determines validity by blocking signal peaks that do not exceed the hysteresis
comparator threshold. The delays in each of these
channels to the 0 flip-flop inputs are well matched.
The 0 flip-flop output triggers a one-shot that sets the
RO output pulse width. Width is controlled by an
external capacitor from the
pin to VCC.
as
SERVO READ MODE
A position error signal (PES) is generated based on the
relative amplitude of two servo Signals, A and B.
Several methods are made available for maintaining
channel gain during servo Signal processing.
2-27
I
SSI32P544
Read Data Processor
and Servo Demodulator
SERVO READ MODE (Continued)
Rectified servo signal peaks ate captured on hold
capacitors at the HOLDAIB pins. This is accomplished
by pulling LATCHA or LATCHB low for a sample
period. Addiitonally, a hold capacitor discharge current
of up to 3.5 mA can be turned on by pulling RSTA or
RSTB low. The discharge current is determined by a
resistor tied between CS and ground. Its magnitude is:
Ics = 2.6/(Rcs + 750) A, typo
Where: Rcs = resistor from CS to ground
Outputs BURSTAIB & PES are referenced to an external reference applied to the VREF pin.
As noted, several methods are used to determine
channel gain in Servo Read Mode. These methods
make use of the data read mode AGC loop, the servo
AGC loop and external or fixed AGC loop gain. Two
methods are used that control the channel gain based
on maintaining the sum of A & B channel amplitudes.
In one case (see Figure 1) the BYP2 pin is connected
to the GAIN pin and the servo channel gain is determined by the read channel gain as controlled by the
sum of the A and B amplitudes. In this case a current
is sourcedlsinked to/from the capacitor on the GAINI
BYP2 pin whenever the HOLD2 pin is pulled high. The
current magnitude and direction is determined by:
Ic = K4[(Ks • VAGC2) - Va(DIN)p-p - Vb(DIN)p-p]
Where:
VAGC2
=AGC2 pin voHage
K4 = 270 !lMIP-P
Ks = 0.41 V/V
Va/b(DIN)p-p = peak to peak A or B servo pattern
Signal voltages at DIN+IThe other case (see Figure 2) controls the channel by
fixing the Read Data channel gain by taking HOLD1
low and closing the loop about the Servo Channel AGC
(LOCOFF is held low for this mode).
HOLD2 is used to update the control voltage on the
AGC capaCitor at the BYP2 pin. This loop has a time
constant defined by:
Time Constant = K6 • CSYP2
Where: Ks = 1.8 to 7.5 KQ
CSYP2
=BYP2 pin capacitor value in farads
Another method (see Figure 5) uses either a fixed voltage atthe GAIN pin to determine channel gain or a gain
based on preamble data amplitude. In this case no
AGC methods are used that are based on servo signal
amplitudes. Gain, as determined by an external voltage has been covered above. In the preamble method
HOLD1 is taken low during a preamble and the channel
gain, determined by that necessary to maintain DIN+I
- as programmed by the AGC1 voltage, is held during
servo data processing.
WRITE MODE
In Write Mode the SSI 32P544 is disabled and preset
for the following Read Mode. The digital circuitry is
disabled, the input AGC amplifier gain is set to maximum and the AGC amplifier input impedance is reduced.
Resetting the AGC amplifier gain and input impedance
shortens system Write to Read recovery times. With
the AGC gain at maximum when returning to Read
mode the AGC loop is in fast attack mode.
The lowered input impedance improves settling time
by reducing the time constant of the network between
the SSI 32P544 and a read preamplifier such as the
SSI 32R510A. Write to read timing is controlled to
maintain the reduced impedance for 1.2 to 3.0 ~s
before the AGC circuitry is activated. Coupling capacitors should be chosen with as Iowa value as possible
consistent with adequate bandwidth to allow more
rapid settling.
POWER DOWN MODE
A power down mode is provided to reduce power
usage during the idle periods. Taking ENABLE pin low
selects this mode. Recovery from this state can be
slow due to the necessity of charging external capacitors.
LOW VOLTAGE FAULT DETECTION
A low voHage detection circuit monitors both supplies
and pulls an open collector TIL output low whenever
either supply drops below their trip point.
2-28
0888
SSI32P544
Read Data Processor
and Servo Demodulator
MODE CONTROL
Servo Read Mode II (See Figures 2 & 4)
The SSI 32P544 circuit mode is controlled by the
ENABLE, RIW, AGCMODE, HOLD1, HOLD2, and
LOCOFF pins as shown in Table 1.
Read amplifier AGC gain held fixed (HOLD1 low).
Servo AGC loop activated with HOLD2 toggled to
update or hold gain based on a constant servo signal
sum.
Data Read Mode
Servo Mode III (See Figure 5)
AGC active and controlled by data, Digital section
active
Read channel gain determined by voltage on GAIN pin.
Data Read Mode, Hold
WrHe
AGC gain held constant, Digital section active. Gain
will drift higher at rate determined by CBYPl and Hold
mode discharge current.
Read amplHier input impedance reduced. BYP1 pin
voltage pulled low to select maximum amplifier gain.
Digital section deactivated.
Servo Read Mode I (See Figures 1 & 3)
Power Down
The BYP2 and GAIN pins are tied together. Read
amplifier AGC control voltage developed from sum of
Servo signal levels. HOLD2 is toggled to update the
control voltage after each Servo frame.
Circuit switched to a low current disabled mode.
Note: When AGCMODE is switched to a low state the
voltage at the BYP1 pin will be held subject to Hold
mode discharge current induced drHt. So, when returning to Data Read Mode, the channel gain will be the
same as it was prior to AGCMODE switching or slightly
higher.
TABLE 1: SSI 32P544 Circuit Mode Control
0888
ENABLE
RIW
AGC
MODE
HOCD1
HOLD2
LOCOFF
1
1
1
1
-
Data Read Mode
Servo Read Mode I
READ PATH MODES
1
1
1
0
-
-
1
1
0
1
1
1
0
-
1
0
1
1
1
1
0
0
0
1
1
1
0
1
0
1
1
0
Servo Mode III
0
-
Write
0
-
-
-
-
1
-
-
-
Power Down
2-29
Data Read Mode Hold
Servo Read Modell
I
SSI32P544
Read Data Processor
and Servo Demodulator
~----------------~~
To ~~P2
i~p~
LOCOFF
_----D-------+----4
AGe,
BVP2
rw
I
FIGURE 1: Servo Read Mode I
~------------------_LJJm
;-----0
GAIN
~
BYP'
1
PES
SAMPLE
AND HOLD
+
--[:r-__---,
+5.V__
A-B
SUMMING
CIRCIUTRV
L-----A.-I""-'"
+5V
AGCO
AGC'
BYP2
1
FIGURE 2: Servo Read Mode II
2-30
0888
SSI32P544
Read Data Processor
and Servo Demodulator
+C.SV
1\
I \
/\
I \
\ I \
\/
\ 1/
+0.25 V
(DIN+) - (DIN-)
0V
-0.25 V
-0.5 V
VLATCHA
VRSTA
--+I
~
f-Tds1
BCHANNEL
DISCHARGE CURRENT
VREF + TBD V
VBURSTA
VREF V
\. J
I \
I
\ I)
I+- Tds2
l'-____--'
l
1
~.:;:j r j
A CHANNEL
DISCHARGE CURRENT
/ \
J
r""
1- J
,,_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
-------~/
BJJ
,,'--------
11111111111111
VBURSTB
VREF+TBD V
VREF V
VREF+TBD V
VPES
VREF V
1IIIIIIIJ:d:d 1111111
I~
!---TUd--!
______________________---'1
AGC AMP
GA~NVN I I I I I I I I I I I I I I I I I I
FIGURE 3: Servo Read Mode I Timing Diagram
0888
L
2-31
SSI32P544
Read Data Processor
and Servo Demodulator
+0.5 V
/ \
/ \
+D.25 V
(DIN+)-(DIN-)
OV
-0,25 V
-0.5 V
VIATCHA
VASTA
/ \
/
/
\
\
L '\
\
\
\.. /
I
\J
I)
-+ !+r-lL._______--'
-+I
Tds1
L
~
\. /
Tds2
lL-_ _---'
VIATCHB
VRSTB
A CHANNa
DISCHARGE CURRENT
J /
BCHANNa
DISCHARGE CURRENT
----------------------~~
VREF+TBD V
VBURSTA
VREF V
VBURSTB
VREF +TBD V
VREF V
VREF+ TBD V
VPES
VREF V
"-
,'-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
I 1:1:1 I I I I I I
I I I I I 1 I I 1:d:d
"''-----
1
1
-I
1
I I I
I~
FIGURE 4: SelVo Read Mode II Timing Diagram
2-32
0888
SSI32P544
Read Data Processor
and Servo Demodulator
~--------------u~
;
SAMPLE
A-8
AND HOW
+
SUMMING
CIRCIUTRY
A+ B
~PES
0
LOCOFF
rv
'-------I--U'FIllIlm
AGC.
AGC.
BYP2
FIGURE 5: Servo Read Mode III
PIN DESCRIPTIONS
POWER SUPPLY AND CONTROL
NAME
DESCRIPTION
VCC
5 voH power supply.
VDD
12 voH power supply.
AGND, DGND
Analog and digital ground pins.
RIW*
TTL compatible readlwrite control pin
ENABLE*
TTL compatible power up control pin. A low input selects a low power state.
VFLT
Open collector output that goes low when a low power supply fault is detected.
AGC GAIN STAGE
0888
IN+,IN-
Analog signal input pins.
OUT+,OUT-.
Read path AGC amplifier output pins.
AGC1
Reference input voltage level for the read path AGC loop.
AGCMODE*
TTL compatible pin that selects the AGC loop control input. A high selects BYP1, a low
GAIN.
BYP1
An AGC timing capacitor or network is tied between this pin and AGND.
GAIN
A voltage at this pin may be used to control AGC gain.
DECAY
A resistor to control the AGC loop decay time constant may be tied between this pin and
BYP1.
HOLD1*
TTL compatible control pin that holds the read path AGC loop gain constant when low.
2-33
I
SSI32P544
Read Data Processor
and Servo Demodulator
PIN DESCRIPTIONS (Continued)
DIGITAL PROCESSING STAGE
NAME
DESCRIPTION
DIN+, DIN-
Analog input to the hysteresis comparator.
CIN+, CIN
Analog input to the differentiator.
DIF+, DIF-
Pins for external differentiating network.
LEVEL
Output from full wave rectifier that may be used for input to the hysteresis-comparator.
HYS
Threshold setting input to the hysteresis-comparator.
DOUT
Buffered TTL output for monitoring the flip-flop D input. Provided for testing or servo use.
COUT
Test point for monitoring the flip-flop clock input.
OS
Connection for output pulse width setting capacitor.
RD
TTL compatible read output.
SERVO BURST CAPTURE STAGE
LATCHA,
LATCHB
TTL compatible inputs that switch channels A or B into peak acquisition mode when
low.
HOLDA,
HOLDB
Peak holding capacitors are tied from each of these pins to AGND.
RSTA,
RSTB
TTL compatible inputs that enable discharge of Channel A or B hold capacitors when
low.
CS
Hold capacitor discharge current magnitude is controlled by a resistor from this pin to
ground.
VREF
Reference voltage input for servo outputs.
AGC2
Reference input voltage level for the servo AGC loop.
BYP2
An AGC timing capacitor or network is tied between this pin and AGND.
HOLD2
TTL compatible control pin that holds the servo AGC loop gain constant when low.
BURSTA,
BURSTB
Buffered hold capacitor voltage outputs.
PES
Position error signal A minus B output.
LOCOFF"
TTL compatible input to select path for PES signal.
" These inputs have internal pull-ups, so an open connection is the same as a high input.
2-34
0888
SSI32P544
Read Data Processor
and Servo Demodulator
ELECTRICAL SPECIFICATION
ABSOLUTE MAXIMUM RATINGS
Operation outside these rating limits may cause permanent damage to this device.
RATING
UNIT
5V Supply Voltage, VCC
6.0
V
12V Supply Voltage, VDD
14.0
V
Pin Voltage
GAIN, BYP1/2, AGC1/2 LEVEL, HYS, HOLDNB, VREF
BURSTNB, PES, COUT, DIF+I-, OUT+I-
-0.3 to VDD + 0.3
V
Pin Voltage
IN +1-, AGCMODE, HOLD1/2, ENABLE, R/W, LATCHNB,
RSTNB, CS, LOCOFF, OS, CIN+I-, DIN+I-
-0.3 to VCC + 0.3
V
Pin Voltage
RD,DOUT,DECAY,VFLTB
-0.3 to VCC + 0.3
or +12 mA
V
65 to 150
°C
260
°C
PARAMETER
Storage Temperature
Lead Temperature (Soldering 10 sec.)
I
RECOMMENDED OPERATING CONDITIONS
Currents flowing into the chip are positive.
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNIT
VCC Supply Voltage
4.5
5.0
5.5
V
VDD Supply Voltage
10.8
12.0
13.2
V
145
°C
MAX
UNITS
Tj Junction Temperature
25
ELECTRICAL CHARACTERISTICS
POWER SUPPLY
Recommended conditions apply unless otherwise specified
PARAMETER
OBBB
CONDITIONS
MIN
NOM
ICC
vce Supply Current
Outputs unloaded,
ENABLE = high or open
16
mA
IDD
VDD Supply Current
Outputs unloaded,
ENABLE = high or open
90
mA
2-35
SSI32P544
Read Data Processor
and Servo Demodulator
POWER SUPPLY (Continued)
PARAMETER
Pd
Power description
MIN
CONDITIONS
Tj = 145°C, ENABLE
Outputs unloaded
= high,
ENABLE = low,
Outputs unloaded
NOM
MAX
UNITS
1.0
W
0.3
W
LOGIC SIGNALS
VIL
Input Low Voltage
-0.3
0.8
V
VIH
Input High Voltage.
2.0
VCC+0.3
V
ilL
Input Low Current
VIL = O.4V
0.0
-0.4
rnA
IIH
Input Low Current
VIH = 2.4V
100
~
VOL
Output Low Voltage
IOL=4.0 rnA
0.4
V
VOH
Output High Voltage
10H =400 ~
Output rise time
VOH = 2.4V·
9.0
ns
Output full time
VOL
= 0.4V·
9.0
ns
2.4
V
·Output load is a 4K resistor to 5V and a 10 pF capacitor to DGND
MODE CONTROL
Enable to/from Disable
Transition Time
Setting time of external
capacitors not included
ENABLE pin high to/from low
50
(.lS
Read to Write Transition Time
R/W pin high to low
1.0
(.lS
Write to Read
Transition Time
R/W pin low to high
AGC setting not included
3.0
p.s
AGC On to/from AGC Off
Transition Time
AGCMODE pin high
to/from low
2.0
p.s
HOLD1 On to/from
HOLD2 Off Transition Time
HOLD1 pin high to/from
low
1.0
(.lS
HOLD2 On to HOLD2 Off
Transition Time
HOLD2 pin high to/from
low
1.0
(.lS
2-36
1.2
0888
SSI32P544
Read Data Processor
and Servo Demodulator
WRITE MODE
PARAMETER
CONDITION
MIN
Common Mode Input
Impedance
R/Wpin = low
NOM
MAX
250
UNIT
n
READ MODE
READ PATH AGC AMPLIFIER
Unless otherwise specified, recommended operating conditions apply. Input signals are AC coupled to
IN+I-. OUT+1- are loaded differentially with >600n, and each side is loaded with < 10 pF to AGND, and AC
coupled to DIN+I-. A 2000 pF capacitor is connected between BYP1 and AGND. AGC1 pin is open. RIW
is high.
PARAMETER
Gain Range
CONDITION
MIN
1.0 Vp-p ~ (OUT+) - (OUT-)
3.0 Vp-p
NOM
MAX
UNIT
4
83
VN
+400
mV
~
Output Offset Voltage
Over entire gain range
-400
Maximum Output
Voltage Swing
Set by BYP1 pin
3.0
Differential Input Resistance
(IN+) - (IN-) = 100 mVp-p
@2.5MHz
Differential Input Capacitance
(IN+) - (IN-) = 100 mVp-p
@2.5MHz
10
pF
Common Mode Input
Impedance
R/W = high
1.8
Kn
R/W = Low
250
n
15
nV/'I'HZ
Input Noise Voltage
Gain set to maximum
Bandwidth
-3 dB bandwidth at
maximum gain
OUT+ to OUT- Pin Current
No DC path to AGND
5.0
MHz
±3.2
rnA
Output Capacitance
CMRR (Input Referred)
0888
(IN+) = (IN-)= 100 mVp-p
@ 5MHz, gain set to max
2-37
Kn
30
26
Output Resistance
Vp-p
40
64
n
TBD
pF
dB
I
SSI32P544
Read Data Processor
and Servo Demodulator
READ PATH AGC AMPLIFIER
(Continued)
PARAMETER
CONDITION
PSRR (Input Referred)
VDD or VCC = 100 mVp-p
@ 5 MHz, gain set to max
Externally controlled
Gain Constants
AV = K2 • e(K3' VGAIN) VN
K2, AGCMODE = Low
1.33
1.87
= Low
1.98
2.1
Gain pin parasitic
Input cu rre nt
AGCMODE & HOLD1
0.2
+0.2
~
(DIN+) - (DIN-) Input
Swing vs. AGC1 Input
30 mVp-p:,; (IN+) " (IN·)
:,; 550mVp-p
0.5 Vp-p :,; (DIN+) - (DiN-)
:,; 1.5 Vp-p, AGCMODE &
HOLD1 = high
0.37
0.56
Vp-p/V
(DIN+) - (DIN-) Input Voltage
Swing Variation
30 mVp-p :,; (IN+) - (IN-)
:,;550mVp-p
8.0
%
AGC1 Voltage
AGC10pen
K3, AGCMODE
MIN
= low
NOM
MAX
dB
30
TBD
AGC1 Pin Input Impedance
5.0
= high
Fast Decay Threshold
(DIN+) - (DIN-)
AGCMODE
Slow AGC Capacitor Discharge
Current
(DIN+) - (DIN-)
AGC Capacitor Leakage
Current
AGCMODE = high,
HOLD1 = low
Slow AGC Capacitor Charge
Current
(DIN+) - (DIN-) = 0.8 VDC,
vary AGC1 until slow charge
begins
Fast AGC Capacitor Charge
Current
(DIN+) - (DIN-)
VAGC1 = 3.0V
Fast to Slow Attack
Switchover Point
[(DIN+)-(DIN-)][(DIN+)-(DIN-)]FINAL
= OV
= 0.8 VDC,
2-38
UNIT
V
8.3
KQ
±0.2
V
4.5
~
-0.2
+0.2
rnA
-0.14
-0.22
rnA
-1.3
-2.0
rnA
0.25
V
0888
SSI32P544
Read Data Processor
and Servo Demodulator
READ PATH AGC AMPLIFIER
(Continued)
PARAMETER
CONDITION
MIN
NOM
MAX
UNIT
Gain Decay Time (Td)
(See Figure 6a)
(IN+) - (IN-) = 300 mVp-p to
150mVp-p@ 2.5 MHz
DECAY pin open,
(OUT +) - (OUT-) to 90% final
value.
50
~s
Gain Attack Time (Ta)
(See Figure 6b)
R/W = low to high
(IN+) - (IN-) = 400 mVp-p
@ 2.5 MHz, (OUT+) - (OUT-)
to 11 0% final value
4
~s
HYSTERESIS COMPARATOR
Unless otherwise specified, recommended operating conditions apply. Input (DIN+) - (DIN-) is an AC coupled,
1.0 Vp-p, 2.5 MHz sine wave. 1.8 VDC is applied to the HYS pin. ENABLE and RIW pins are high.
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNIT
1.5
Vp-p
16.5
Kn
4.0
pF
3.0
5.0
Kn
1.5
2.5
VNp-p
Input Signal Range
Differential Input Resistance
(DIN+) - (DIN-)
@2.5MHz
= 100 mVp-p
Differential Input Capacitance
(DIN+) - (DIN-)
@2.5MHz
= 100 mVp-p
Common Mode Input
Impedance (Both Sides)
Level Pin Output Voltage
vs. (DIN+) - (DIN-)
0.6 Vp-p < (DIN+) - (DIN-)
< 1.5 Vp-p, 10K between
LEVEL and AGND
Level Pin Output Impedance
ILEVEL = 0.5 rnA
Level pin Maximum
Output Current
180
rnA
3.0
Hysteresis Voltage at DIN+/vs. HYS Pin Voltage
1 V < HYS < 3V
0.16
0.25
VN
HYS Pin Current
1 V < HYS<3V
0.0
-20
~
10.0
mV
Comparator Offset Voltage
HYS pin at AGND
1.5 Kn across DIN +/-
$;
0888
10
2-39
SSI32P544
Read Data Processor
and Servo Demodulator
ACTIVE DIFFERENTIATOR
Unless otherwise specified, recommended operating conditions apply. Input (CIN+) - (CIN-) is an ACcoupled, 1.0 Vp-p, 2.5 MHz sine wave. 100n in series with 65 pF are tied from DIF+ to DIF-.
PARAMETER
MAX
UNIT
1.5
Vp-p
16.5
Kn
4.0
pF
3.0
5.0
Kn
1.7
2.2
VN
MIN
CONDITIONS
NOM
Input Signal Range
Differential Input Resistance
(CIN+) - (CIN-)
@2.5MHz
= 100 mVp-p
Differential Input Capacitance
(CIN+) - (CIN-)
@2.5MHz
= 100. mVp-p
Common Mode Input Impedance
Both sides
Voltage Gain From
CIN+/- to DIF+/-
(DIF+ to DIF-)
DIF+ to DIF- Pin Current
Differentiator impedance
must be set so as to not clip
the signal for this current
level
Comparator Offset Voltage
DIF+, DIF- are AC-coupled
COUT Pin Output Low Voltage
0:;; IOL:;; 0.5 mA
VDD-3.0
V
COUT pin Output Pulse
Voltage, VHIGH - VLOW
0:;; IOL:;; 0.5 mA
0.4
V
COUT pin Output Pulse Width
o:;; IOH :;; 0.5 mA
30
ns
= 2 Kn
10
±1.3
mA
10.0
mV
(a)
Figure 6: AGC Timing Diagram
2-40
0888
SSI32P544
Read Data Processor
and Servo Demodulator
OUTPUT DATA CHARACTERISITICS (See Figure 7)
Unless otherwise specified, recommended operating conditions apply. Inputs (CIN+) - (CIN-) and (DIN+) (DIN-) are in-place as a coupled, 1.0Vp-p, 2.5MHz sine wave. 1OOQ in series with 65 pF are tied from DIF+
to DIF-. 1.8V is applied to the HYS pin. A 60 pF capacitor is tied between OS and VCC. RD is loaded with
a 4 KQ resistor to VCC and a 10 pF capacitor to DGND. ENABLE and R/W pins are high.
PARAMETER
CONDITIONS
Td1
D Flip-Flop Set Up
Time
Td3
Propagation Delay
Td5
Output Pulse Width
Variation
MIN
Minimum allowable time
delay from (DIN+) - (DIN-)
exceeding hysterisis
point to (DIF+) - (DIF-)
hitting a peak value.
Td5 = 900(Cos) @ VRD
50 pF :s; Cos :s; 200 pF
NOM
= 1.4V
I+----'<:--------f--"'>-
V(CIN+) - (CIN-)
and
ovl+---\----f--~-f-----''r
V(DIN+) - (DIN-)
-HYSTERESIS LEVEL
1+---"'>--1'---------
V (DIN+-DIN-)
f--+-\----f--~-f----
DIFFERENTIATOR
COMPARATOR OUTPUT
RDOUTPUT
-I i+-
Td5
Figure 7: Read Mode Digital Section Timing Diagram
0888
2-41
UNIT
ns
0
trd3-Td41 Logic Skew
+HYSTERESIS LEVEL
MAX
110
ns
±15
%
1.5
ns
SSI32P544
Read Data Processor
and Servo Demodulator
SERVO SECTION (Unless otherwise specified, recommended operating conditions apply.)
PARAMETER
MIN
CONDITIONS
3.9
VREF Voltage Range
AGC2 Pin Voltage
MAX
UNIT
6.0
V
V
3.4
AGC2 Pin Open
8.3
5.0
AGC2 Pin Input Impedance
BURSTAIB pin Output
Voltage vs (DIN+) - (DIN-)
NOM
VNp-p
1.7
LATCHAIB - Low
KO
V\lLRSTAS - VR EF
(DIN+) - (DIN-)
BURSTAIB Output
Offset Voltage
VBURST - VREF
LATCHAIB = Low,
(DIN+) = (DIN-),
RCS = 38.3 KO
-50
+50
mV
BURSTA - BURSTB Output
Offset Match
LATCHAIB = low
(DIN+) = (DIN-)
-10
+10
mV
Maximum PES Pin Output
Voltage
Controlled by AGC2
5.0
Vp-p
PES Pin Output Offset Voltage
VPES - VREF, (DIN+)
LATCHAIB = Low
+10
mV
20
0
= (DIN-)
-10
Output Resistance, BURSTAIB &
PES pins
HOLDAIB Discharge
Current Tolerance
Load Resistance
BURSTAlB, PES pins
RSTAIB = low,
ICS = 2.6V/(RSC + 7500)
%
TBD
RSTAlB = high,
LATCHAIB = high
-0.5
Resistors to VREF
10.0
+0.5
I1A
KO
20
Load Capacitance
BURSTAlB, PES pins
pF
LATCHAIB pin set up time
(Tds1 in Figures 3 & 4)
150
ns
LATCHAIB pin Hold Time
(Tds2 in Figures 3 & 4)
150
ns
Channel AlB Discharge
Current Turn On time
(Tds3 in Figures 3 & 4)
2-42
.
150
ns
0888
SSI32P544
Read Data Processor
and Servo Demodulator
SERVO SECTION (Continued)
PARAMETER
CONDITIONS
Channel AlB discharge
Current Turn Off time
(Tds4 in Figures 3 & 4)
BYP2 Pin Parasitic Input Current
HOLD2 = Low
Ks loop parameter
BYP2 Pin Charge/Discharge
Current
Ic = K4[(Ks • VAGC2)VA(OIN)p-p - VB(OIN)p-p]
MAX
UNIT
150
lJ.S
-9.0
+9.0
JJ.A
Loop Time Constant =
Ks' CBYP2
LOCOFF= Low
(Local AGC Mode)
1.8
7.5
KQ
K4, HOLD2 = High
229
270
310
JJ.AlVp-p
Ks, HOLD2 = High
0.39
0.41
0.43
VN
*PES Pin Output Voltage
LOCOFF=Low
0.6
6.0
VNp-p
vs. VA(OIN)p-p - VB(OIN)p-p
LOCOFF=High
1.62
1.7
1.79
VNp-p
VPES p-p vs. VAGC2
VPES p-pNAGC2
1.31
1.38
1.45
Vp-pN
VPES p-pNAGC2
AGC2=Open
4.46
4.7
4.94
Vp-p
BURSTAIB Pin Output vs. VAGC2
MIN
NOM
(VA + VB - 2VREF)NAGC2
0.66
VN
VA + VB - 2VREF,
AGC2=Open
2.3
V
*Av = (VPES - VREF)/(VA(OIN)p-p - VB(OIN)p-p)
SUPPLY VOLTAGE FAULT DETECTION
PARAMETER
CONDITIONS
TYP
MAX
UNIT
VDD Fault Threshold
9.1
10.3
V
VCC Fault Threshold
4.1
4.4
V
4.5 < VCC < 5.5V,
IOL=1.6 rnA
0.4
V
1.0 < VCC < 4.5,
IOL=0.5 rnA
0.4
V
25
JJ.A
VOL Output Low
VoHage
IOH Output High Current
0888
MIN
2-43
SSI32P544
Read Data Processor
and Servo Demodulator
PACKAGE PIN DESIGNATIONS
CAUTION: Use handling procedures necessary
for a static sensitive compcnent.
(Top View)
g 5
0
0
6
5
z+
(3
~
+
0
4
3
2
~
.!:
c
~ ~ ~
~
C
44
41
40
43
42
J.
BYP1
39
HYS
38
LEVEL
37
DECAY
IN+
36
DOUT
IN-
35
HOLDA
VJU
34
HOLDB
VDD
33
CS
HOID2
32
DGND
ENABLE
31
rmRA
LOCOFF
30
lJ\1'CIm
29
"1m
FIOlD1
20
18
19
21
w
c
0
:::;
~ IIIg:'" a:~
~
III
:l
23
24
w
~ '"
a:
>
22
Do
:l
Ll-
w
25
26
27
28
N
0
I-
1Il
0
~
g
a
0
III
44-pin PLCC
ORDERING INFORMATION
PART DESCRIPTION
55) 32P544 - 44-pin PLCC
ORDER NO.
PKG.MARK
55) 32P544-CH
32P544-CH
No responsibility is assumed by SSi for use of this product nor for any infringements of patents and trademarks or other rights of third parties
resulting from its use. No license is granted under any patents, patent rights or trademarks of SSi. SSi reserves the right to make changes
in specifications at any time without notice.
Silicon Systems, Inc., 14351 MyfOrd Road, Tustin,
CA 92680, (714) 731-7110, TWX 910-595-2809
©1988 Silicon Systems, Inc.
0888
2-44
SSI32P546
Read Data Processor
with Pulse Slimming
INNOVATORS IN INTEGRATION
-----------------------------------------------------August, 1988
DESCRIPTION
FEATURES
The SSI 32P546 is a bipolar integrated circuit that
provides a" data processing necessary for detection
and qualification of MFM or RLL encoded read signals.
•
Level qualification supports high resolution MFM
and RLL encoded data retrieval
•
•
•
Wide bandwidth AGe input amplifier
•
Write to read transient suppression
•
Fast and slow AGe attack regions forfasttransient
recovery
•
Buffers and Amplifier to implement Pulse Slimming
In read mode the SSI 32P546 provides amplification
and qualification of head preamplifier outputs. Pulse
qualification is accomplished using level qualification
of differentiated input zero crossings. An AGe amplifier is used to compensate for variations in head
preamp output levels, presenting a constant input level
to the pulse qualification circuitry. Signal processing
can be further enhanced with pulse slimming techniques supported by on-chip emitter followers and
buffer amplifier. The AGe loop can be disabled so that
a constant gain can be used for embedded servo decoding or other processing needs.
Supports data rates up to 15 Mbits/sec
Standard 12V ±1 0% and 5V ±1 0% supplies
In write mode the circuitry is disabled and the AGe gain
stage input impedance is switched to a lower level to
allow fast setting of the input coupli ng capacitors during
a write to read transition. The SSI 32P546 requires
+5V and +12V power supplies and is available in a
32-pin DIP.
BLOCK DIAGRAM
our.
OUT-
EF1
EF2
EF3
Ef4
BIN-
BlN+
BOUT+
BOUT+
DIN-
DIN+
ClN-
CIN+
DlF-
DIF+
vee
VOD
COUT
BYP
U-~-+---,
AGND
=u-~-
0888
DIGITAL
ONO
AGe
LEVEL
HYS COOT
2-45
os
SSI32P546
Read Data Processor
with Pulse Slimming
CIRCUIT OPERATION
READ MODE
In the read mode (RIW input high or open) the input
read signal is amplified and qualified using an AGC
amplifier and pulse level qualification of the detected
signal peaks.
The amplified head signals are AC coupled to the IN+
and IN- pins of the AGC amplifier that is gain controlled
by full wave rectifying and amplifying the (DlN+ - DIN-)
voltage level andcomparing itto a reference level atthe
AGC pin. A fast attack mode, which supplies a 1.7 rnA
charging current for the capacitor at the BYP pin, is
entered whenever the instantaneous DIN ± level is
morethan 125% of set level. Between 100% and 125%
the slow attack mode is invoked, providing 0.18 rnA of
charging current. The two attack modes allow rapid
AGC recovery from a write to read transition while reducing zero crossing distortion once the amplifier is in
range.
The level at the AGC pin should be set such that the
differential voltage level at the DIN+, DIN- pins is
1.00 Vpp at nominal conditions. The circuit can swing
2.5 Vpp at the BOUT+, BOUT- pins which allows for up
to 6 dB loss i n any external filter connected between the
BOUT+, BOUT- outputs and the DIN+, DIN- inputs.
timed properly. A multi-pole Bessell filter is typically
used for its linear phase or constant group delay
characteristics.
The filtered data path signal is fed into a hysteresis
comparator that is set at a fraction of the input signal
level by using an external filter/network between the
LEVEL and HYS pins. Using this approach allows
setting the AGC slow attack and decay times slow
enough to minimize distortion of the clock path signal.
This "feed-forward" technique, utilizing a fraction ofthe
rectified data path input available at the LEVEL pin as
the hysteresis threshold, is especially useful inthe slow
decay mode of the AGC loop. By using a short time
constant for the hystereSiS level, the qualification
method can continue as the AGC amplifier gain is
slowly ramped up. This level will also shorten the write
to read transient recovery time without affecting data
timing as the circuit will be properly decoding before the
AGC gain has settled to its final value. The comparator
output is the "0" input of a 0 type flip-flop. The DOUT
pin provides a buffered test point for monitoring this
function.
The filtered clock path signal is differentiated to transform signal peaks to zero-crossings which clock an
edge-trigger circuit to provide output pulses at each
zero-crossing. The pulses are used to clock the 0 type
flip-flop. The COUT pin is a buffered test point for
monitoring this function.
Gain of the AGC section is nominally
Av2 =ex p _(V2-V1 )
Av1
5.8+Vt
The differentiatorfunction is set by an external network
between the DIF+, DIF- pins. The transfer function is:
AV
Where: Av1 and Av2 are initial and final amplifier
gains. V1, V2 are initial and final voltages
on the BYP pin.
Where: C = external capacitor (20 pF to 150 pF)
Vt = (K x T)/q = 26 mV at room temperature.
Manipulation of pulse characteristics can be accomplished using the emitter followers and buffer amplifier
(gain = 4) that follow the AGC amplifier. As illustrated
in the application section, pulse slimming requires an
external delay line and attenuator.
One filter for both data (DIN+, DIN- input) and clock
(CIN+, CIN- input) paths, or a separate filter for each
path may be used. If two filters are used, care must be
exercised to control time delays so that each path is
-2000Cs
LCs 2 + ( R + 92 ) Cs + 1
L = external inductor
R = external resistor
s = jw = j27tf
During normal operation the differentiator circuit clocks
the 0 flip-flop on every positive and negative peak of
the signal input to CIN+, CIN-. The 0 input to the
flip-flop only changes state when the signal applied to
the DIN+, DIN- inputs exceeds the hysteresis comparator threshold opposite in polarity to the previous
peak that exceeded the threshold.
2-46
0888
SSI32P546
Read Data Processor
with Pulse Slimming
The clocking path. then. determines signal timing and
the data path determines validity by blocking signal
peaks that do not exceed the hysteresis comparator
threshold.
The delays from CIN+. CIN- inputs to the flip-flop clock
input and from the DIN+. DIN- inputs to the flip-flop D
input are well matched.
LA YOUT CONSIDERATIONS
The SSI32P546 is a high gain wide bandwidth device
that requires care in layout. The designer should keep
analog signal lines as short as possible and well
balanced. Use of a ground plane is recommended
along with supply bypassing and separation of the
SSI 32P546 and associated Circuitry grounds from
other circuits on the disk drive PCB.
WRITE (DISABLED) MODE
In the write or disabled mode (R/W input low) the digital
circuitry is disabled and the AGC amplifier input impedance is reduced. In addition the AGC amplifier. gain is
set to maximum so that the loop is in its fast attack
mode when changing back to Read Mode. The lowered input impedance facilitates more rapid settling of
thewriteto read transient by reducing the time constant
of the network between the SSI32P546 and readlwrite
preamplifier. such as the SS132R510A.
MODE
R/W
HOLD
1
1
READ - Read amp on. AGC active. Digital section active
1
0
HOLD - Read amp on. AGC
gain held constant Digital section active
0
X
WRITE - AGC gain switched to
maximum. Digital section inactive. common mode input resistance reduced
Internal SSI 32P546 timing is such that this settling is
accomplished before the AGC loop is activated when
going to read mode. Coupling capacitors should be
chosen with as Iowa value as possible. consistent with
bandwidth requirements. to allow more rapid settling.
PIN DESCRIPTION
NAME
TYPE
VCC
DESCRIPTION
5 volt power supply
VDD
12 volt power supply
AGND.DGND
Analog and Digital ground pins
R/W
I
TTL compatible readlwrite control pin
IN+.IN-
I
Analog signal input pins
OUT+.OUT-
0
AGC Amplifier output pins
~
BYP
0888
The AGC timing capacitor is tied between this pin and AGND
HOLD
I
TTL compatible pin that holds the AGC gain when pulled low
AGC
I
Reference input voltage level for the AGC circuit
DIN+. DIN-
I
Analog input to the hysteresis comparator
HYS
I
Hysteresis level setting input to the hysteresis comparator
LEVEL
0
Provides rectified signal level for input to the hysteresis comparator
DOUT
0
Buffered test point for monitoring the flip-flop D input
2-47
SSI32P546
Read Data Processor
with Pulse Slimming
PIN DESCRIPTION
NAME
(Continued)
TYPE
CIN+, CIN-
I
DIF+, DIFCOUT
DESCRIPTION
Analog input to the differentiator
Pins for external differentiating network
0
OS
Buffered test point for monitoring the clock input to the flip-flop
Connection for read output pulse width setting capacitor
RD
0
TTL compatible read output
EF1
I
Emitter follower input
EF2,3,4
0
Emitter follower outputs
BIN+, BIN-
I
Analog input to buffer amplifier
BOUT+, BOUT-
0
Buffer amplifier output pins
ELECTRICAL CHARACTERISTICS
Unless otherwise specified 4.5 ~ vce
~
5.5V, 10.8V ~ VDD
~
13.2V, 25 °c
~
Tj
~
135°C.
ABSOLUTE MAXIMUM RATINGS
Operation above absolute maximum ratings may permanently damage the device.
PARAMETER
RATING
UNIT
5V Supply Voltage, VCC
6
V
12V Supply Voltage, VDD
14
V
-65 to 150
°C
260
°C
Storage Temperature
Lead Temperature
R/W, IN+, IN-, HOLD
RD
-0.3 to VCC + 0.3
V
-0.3 to VCC + 0.3 or +12 rnA
V
-0.3 to VDD + 0.3
V
All others
POWER SUPPLV
PARAMETER
CONDITIONS
ICC - VCC Supply Current
Outputs unloaded
IDD - VDD Supply Current
Outputs unloaded
Pd - Power Dissipation
Outputs unloaded, Tj = 135°C
MIN
2-48
NOM
MAX
UNIT
14
rnA
90
rnA
1000
mW
0888
SSI32P546
Read Data Processor
with Pulse Slimming
LOGIC SIGNALS
PARAMETER
CONDITIONS
MIN
VIL - Input Low Voltage
-0.3
VIH - Input High Voltage
2.0
NOM
MAX
UNIT
0.8
V
V
ilL - Input Low Current
VIL = O.4V
-0.4
rnA
IIH - Input High Current
VIH = 2.4V
100
I1A
VOL - Output Low Voltage
IOL =4.0 rnA
0.4
V
VOH - Output High Voltage
IOH = -400
0.0
I1A
2.4
CONDITIONS
MIN
V
MODE CONTROL
PARAMETER
NOM
Read to Write Transition Time
Write to Read Transition Time
AGC settling not included,
transition to high input
resistance
1.2
Read to Hold Transition Time
MAX
UNIT
1.0
I1s
3.0
I1s
1.0
I1S
MAX
UNIT
WRITE MODE
PARAMETER
CONDITIONS
Common Mode Input Impedance
(both sides)
R/Wpin = low
MIN
NOM
250
0
READ MODE
Unless otherwise specified IN+ and IN- are AC coupled, OUT+, and OUT- are loaded with 1500 to VDD, a
2000 pF capacitor is connected between BYP and GND, BOUT+ is AC coupled to DIN+, BOUT- isAC coupled
to DIN-, AGC pin voltage is 2.2 VDC.
AGC AMPLIFIER
0888
PARAMETER
CONDITIONS
Differential Input Resistance
V(IN+ - IN-) = 100 mVpp
@2.5MHz
Differential Input Capacitance
V(IN+-IN-) = 100 mVpp
@2.5MHz
MIN
NOM
MAX
UNIT
KO
5
10
pF
Common Mode Input Impedance
R/W pin high
1.8
KO
(both sides)
R/Wpin low
0.25
KO
Gain Range
VOUT+ = 0.75 Vpp
Input NOise Voltage
Gain set to maximum
Bandwidth
Gain set to maximum
-3 dB point
2-49
1.0
30
31
VN
30
nV/,!Hz
MHz
SSI32P546
Read Data Processor
with Pulse Slimming
AGC AMPLIFIER (Continued)
PARAMETER
CONDITIONS
MIN
Maximum Output Voltage Swing
Set by BYP pin voltage
Z (load) = 1500 to VDD
0.75
(DIN+ - DIN-) Input Voltage
Swing VS AGC Input Level
30 mVpp V(IN+ -IN-)
~ 550 mVpp, 0.5 Vpp
~ V(DIN+ - DIN-) ~ 1.5 Vpp
0.37
(DIN+ - DIN-) Input Voltage
Swing Variation
30 mVpp V(IN+ - IN-)
~ 550 mVpp AGC Fixed,
over supply & temperature
Gain Decay Time (Td)
Yin = 300 mVpp-> 150 mVpp
at 2.5 MHz, Vout to 90% of
final value Figure 1a
50
IJ.S
Gain Attack time (Ta)
From Write to Read transition
to Vout at 110% of final value
Yin = 400 mVpp @ 2.5 MHz.
Figure 1b
4
IJ.S
Fast AGC Capacitor Charge
Current
Slow AGC Capacitor Charge
Current
V(DIN+ - DIN-)
= 1.6V V(AGC) = 2.2V
V(DIN+ - DIN-) = 1.6V Vary
Fast to Slow Attack Switchover
Point
V(AGC) until slow discharge
V(DIN+-DIN-)
V(DIN+-DIN-) Final
AGC Capacitor Discharge Current
V(DIN+ - DIN-)
NOM
MAX
UNIT
Vpp
0.56
VppN
8
%
1.3
2.0
rnA
0.14
0.22
rnA
1.25
= O.OV
~
4.5
Read Mode
CMRR (Input Referred)
V(IN+) = V(IN-) = 100 mVpp
@ 5 MHz,gain at max.
40
~
dB
PSRR (Input Referred)
VCC or VDD = 100 mVpp
@ 5 MHz, gain at max.
30
dB
-0.2
Hold Mode
+0.2
UNITY GAIN BUFFERS: (EMITTER FOLLOWERS)
PARAMETER
CONDITIONS
MIN
Maximum Output Voltage Swing
Z(load diff.) = 1 KO
ACCoupled
1.0
Input Bias Current
EF1
Gain
NOM
1
30
Output Current
750
2-50
UNIT
VN
Vpp
50
Output Resistance
MAX
~
0
~
0888
SSI32P546
Read Data Processor
with Pulse Slimming
DIFFERENTIAL BUFFER AMPLIFIER
PARAMETER
CONDITIONS
Gain
(BOUT+- BOUT-)
(BIN+- BIN-)
Differential Gain
MIN
Input Noise
Input (BIN+, BIN-) Referred
NOM
MAX
UNIT
VN
4
100
nV/VHz
Bandwidth
-3 dB bandwidth
30
MHz
Maximum Output Voltage Swing
Z (load ditt.)
= 1 KQ
V (IN+ -IN-) = 100 mVpp,
3.0
Vpp
Differential Input ReSistance
KQ
20.0
2.5 MHz
Differential Input Capacitance
V (IN+ -IN-)
2.5 MHz
= 100 mVpp,
10.0
Common Mode Input Impedance
(Both Sides)
BOUT+ to BOUT- Pin Current
KQ
5.0
No DC path from
OUT+/- to GND
Output Resistance
pF
rnA
±2.4
43
17
Q
Common mode Rejection Ratio
(Input Referred)
V (BIN+) = V (BIN-)
= 100 mVpp, 5 MHz
40
dB
Power Supply Rejection Ratio
Input Referred
V (12) or V(5}
= 100 mVpp, 5MHz
30
dB
HYSTERESIS COMPARATOR
PARAMETER
CONDITIONS
MIN
NOM
Input Signal Range
0888
Differential Input Resistance
V (DIN+ - DIN-)
@2.5MHz
= 100 mVpp
Differential Input Capacitance
V (DlN+- DIN-)
@2.5MHz
= 100 mVpp
Common Mode Input Impedance
(both sides)
Comparator Offset Voltage
HYS pin at GND, :5 1.5 KQ
across DIN+, DIN-
Peak Hysteresis Voltage vs HYS
pin voltage (input referred)
At DIN+, DIN- pins
1V < V (HYS) < 3V
HYS Pin Input Current
Level Pin Output
Voltage vs V(DIN+ - DIN-)
5
MAX
UNIT
1.5
Vpp
11
KQ
6.0
pF
2.0
KQ
10
mV
0.16
0.25
VN
1V < V (HYS) < 3V
0.0
-20
IJ.A
0.6 < I V (DIN+ - DIN-) I
<1.3 Vpp 10 KQ from LEVEL
pinto GND
1.5
2.5
VNpp
2-51
SSI32P546
Read Data Processor
with Pulse Slimming
HYSTERESIS COMPARATOR (Continued)
PARAMETER
MIN
CONDITIONS
LEVEL Pin Max Output Current
NOM
MAX
UNIT
mA
3.0
180
0
LEVEL Pin Output Resistance
I(LEVEL) = 0.5 mA
DOUT Pin Output Low Voltage
0.0:s 10L:s 0.5 mA
VDD -4.0
VDD -2.8
V
DOUT Pin Output High Voltage
0.0:s 10H :s 0.5 mA
VDD -2.5
VDD -1.8
V
MAX
UNIT
1.5
Vpp
11.0
KO
6.0
pF
2.2
VN
ACTIVE DIFFERENTIATOR
PARAMETER
MIN
CONDITIONS
NOM
Input Signal Range
Differential Input Resistance
V(CIN+ - CIN-) = 100 mVpp
@2.5MHz
Differential Input Capacitance
V(CIN+ - CIN-) = 100 mVpp
@2.5MHz
Common mode Input Impedance
(both sides)
Voltage Gain From CIN± to DIF±
R(DIF+ to DIF-) = 2 KO
DIF+ to DIF- Pin Current
Differentiator Impedance
must be set so as not to clip
signal at this current level
5.8
2.0
1.7
KO
±1.3
mA
10.0
mV
Comparator Offset Voltage
DIF+, DIF = AC Coupled
COUT Pin Output Low Voltage
0.0:s 10H :s 0.5 mA
VDD-3.0
V
COUT Pin Output Pulse voltage
V(high) - V(low)
0.0:s 10H :s 0.5 mA
+0.4
V
COUT Pin Output Pulse Width
0.0:s 10H :s 0.5 mA
30
ns
OUTPUT DATA CHARACTERISTICS (See Figure 2)
Unless otherwise specified V(CIN+ - CIN-) = V(DIN+ - DIN-) = 1.0 Vpp AC coupled since wave at 2.5 MHz
differentiating networkbetweenDIF+and DIF-is 100mn series with 65pF, V (Hys) = 1.8 DC,a60pFcapacitor
is connected between OS and VCC, RD- is loaded with a 4 Kn resistor to VCC and a 10 pF capacitor to GND.
PARAMETER
CONDITIONS
D-Flip-Flop Set Up Time (Td1)
Min delay from V(DIN+ DIN-)
exceeding threshold to
V(DIF+ - DIF-) reaching
apeak
MIN
Propagation Delay (Td3)
Output Data Pulse Width
Variation
Td5 = 670 Cos,
50 pF :S Cos::;; 200 pF
Logic Skew Td3 - Td4
NOM
MAX
UNIT
ns
0
110
ns
±15
%
3
ns
Output Rise Time
VOH =2.4V
14
ns
Output Fall Time
VOL = 0.4V
18
ns
2-52
0888
SSI32P546
Read Data Processor
with Pulse Slimming
(a)
FIGURE 1(a), (b): AGe Timing Diagrams
+HYSTERESIS LEVEL
1+-+-------1-"""'\-
v (CIN+ -
CIN-)
and
I+--'t----t-~..._-t--~I<
V (OIN+ - OIN-)
-HYSTERESIS LEVEL
1+---'<-----,1-------
V (OIN+ - OIN-)
r---+-+---{--'I;---f----
V (COUT)
FLIP-FLOP CLOCK
FIGURE 2: Timing Diagram
0888
2-53
SSI32P546
Read Data Processor
with Pulse Slimming
PULSE SLIMMING
The "Cosine Equalization" technique used in the SSI 32P546 relies on an external delay line to affect pulse
slimming. This method is illustrated below:
10
OUT
+
BIN+
IOUT+(IO))
~
,...-- , _--..
BIN-
,,'
----_.-"";'
,/
~~
131 OUT + (1 0 + 2t)]
..._----
BOUT = 4 (BIN+ - BIN-)
BOUT
The PW50 reduction is dependent on the amplitude of't and the attenuation (13) between EF3 and BIN-.
2-54
0888
o
0>
~
o
•
o
WRITE UNSAFE
• HEAD SELECT
0-. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - _ + 1 1 1 WAITEDATA
o
II
.OCl1}1f
1K
~~g
;<
300
.OO1}1f
;<
8
~
I
I~~
400
.01 ""
CHIP DISABLE
: TO SERVO
1
• CIRCUIT
.01~
KEEP LEADS
SHOAT
TO ANALOG
GND PIN
COUT
I\)
I
0'1'
0'1
READ DATA
ANALOG
GND
m>J])"
::sif
-'Q)
;'0.
READlWAITE
CIRCUIT
--
"'CO
c::
Q)
(l)Q)cn
HVS
DOUT
cn ... _
CD"'Ccn
os
cosU'"
-
=0
KEEP lEADS
SHORT
READ,wRITEB
SERVO HOLD
FIGURE 3: Typical Application
--
3 (') W
N
3-'(1)
mU1"'C
:::s 0 oI:ao
cc ... en
SSI32P546
Read Data Processor
with Pulse Slimming
THERMAL CHARACTERISTICS: 0
PACKAGE PIN DESIGNATIONS
(TOP VIEW)
32-LeadSOW
Ja
55·eIW
EFI
EF2
EF3
EF4
CIN+
DIN+
CINDIN·
OUT·
OUT.
IN.
IN·
AGND
'RCCD
BYP
DaND
VDD
DooT
COUT
1'Iri
RIW
vec
OS
32·Lead SOW
CAUTION: Use handling procedures necessary
for a slatic sensitive component
ORDERING INFORMATION
PART DESCRIPTION
I
ORDERING NUMBER
I
PACKAGE MARK
I
551 32P546-CW
551 32P546 Read Data Processor
32-Lead50W
I
551 32P546-CW
No responsibility is assumed by SSi for use of this product nor for any infringements of patents and trademarks or other rights of third parties
resulting from its USB. No license is granted under any patents, patent rights or trademarks of SSi. SSi reserves the right to make changes
in specifications at any time without notice.
Silicon Systems, Inc., 14351 Myford Road, Tustin,
CA 92680 (714) 731-7110, TWX 910-595-2809
0888
©1988 Silicon Systems,lnc.
2-56
SSI32D531
Data Separator and Write
Precompensation Device
INNOVATORS IN INTEGRATION
-----------------------------------------------------August, 1988
DESCRIPTION
FEATURES
The SSI 32D531 Data Separator performs data synchronization and write precompensation of encoded
data. The interface of the SSI 32D531 is optimum for
use with Western Digital's WD1 01 OIWD201 0 controllerfamily.
•
MFM & RLL Data Synchronization.
•
Optimized for use with the WD1010IWD2010
controller family
•
Fast acquisition Phase Locked Loop
•
1F detection
•
Write precompensatlon
•
Write data resynchronlzed for reduced jitter
•
No external delay line or varactor diode required
•
Single +5V power supply
The SSI 32D531 contains a high performance Phase
Locked Loop for read data synchronization, a crystal
controlled reference oscillator for write data synchronization, and write precompensation circuitry. The SSI
32D531 employs an advanced bipolar technology
which affords precise bit cell control without the need
for external active components. The SSI 32D531
requires a single +5V power supply and is available in
24-pin DIP and 28-pin PLCC packages.
BLOCK DIAGRAM
Rac~
cac
t--
ENCODED
READ DATA
li
~
114
FDETECT
FETRlG-
.::--~
-
=
IF DETECT
PD OUT
D
....
7 ~
Y
R1F
F DET SET
;:ty
LCWn-TEA
\/Co IN
-
..
GiJCF
~ ~
CF>
Cf2
PHASE
Ya.TAGECON1"RCILLED
1ft
READ
DErECTOA
OSCl1ATOR
DIY
Cl.0CK
I : : :.'
\ICC
}::::~ ": "~::::,:~:>"::
ACLK
V
WD101~
':::':::':','
QND
MUX
CC»fTROLL.ER
CONTFlC1.
VJ
S'iNCH
LOGIC
8'I1lOO
SVNCHAONIZER
M'ERFACE
AEAD
cO
GATE
xrAL,
"-::!:;-
~
CAVSTAL,...
~
WAITE
~
RD
READ DATA
~
...
WCLK
xr....
~
~
=AWAITE
. .-SYNCH
~~~
~
"tJC
.,
m
CDn m
WD
~
VOLT
!AT(
!AT(
REF
PRECOMP
.RWC
°en
3CD
ENA1lLE
~ PRECOMP SET
-=- Rf'C Tepc
\/cC
""m
• comacIIdwhln pracompanulon II
COII'ICiIdd Will reciJced wrna anent.
CD
::::I .,
~
FIGURE 4: Typical System Connections
Application Information
In a typical application the 881 32D531 is used with a Western Digital WD1 01 0·05 Winchester Disk Controller as shown in Figure 4.
Interface to the disk drive consists of the Read data input signal from the drive and the Write data output signal from the 881 32D531. All
the other connections are with the WD1 01 0 and external components.
m
en
m=.~en
Omen
::::1::::1W
cc.
CD<~
l--------
NRZ ---..,
INPUT COUNTER
---1---------------+1-------------o
32
Notes: 1) Dashed lines "'present a high l"lledance output stat.
2) Rep.....ntationo of Int.rnal.lgnals
FIGURE 6: HARD SECTOR MODE TIMING DIAGRAM
3-22
0188
SSI3205321
Data Synchronizer/
2, 7 RLL ENOEC
31
INPUT COUNTER
ENCODED 2.7 DATA
I
32
I
\1\0\0\01\0\0\01\0\0\1\0\010\1\0\0\1\0\0\0\0\0\0\1\0\0\
DLYD DATA"
VCOOUT "
RRC
DECODED NRZ DATA
NRZ OUTPUT 2 '
1
\
1
---------------------+------~
Notes: *1) Representations of Internal signals
"2) In hard sector mode the NRZ output is inverted
FIGURE 7: HARD SECTOR MODE DECODE TIMING
-
INPU"b~t~
I
516 - - E 1 6 - - - - - - - - - - A 1 6 - - X 1 6 ' .. - - O A T A -
0
NAZ
ARC (WCLK)
, I I I I3,1 I I I, I I I, I I I I' I I I, I I I I I I I, I
ENCOOED2, 7
0
DATA
0
0
0
0
0
0
0
0
0
0
0
X16 can be anycorrbination. C16 (1100) was selected in this eXa.f1lJ1e
*2) Representations of Internal signals
*3) Deleted ouput pulse to encode Address Mark
Notes: *1)
FIGURE 8: WRITE ADDRESS MARK GENERATION
0188
3-23
0
0
0
0
0
0
0
SSI3205321
Data Synchronizer/
2, 7 RLL ENOEC
ABSOLUTE MAXIMUM RATINGS
PARAMETER
RATINGS
UNIT
Storage Temperature
-65 to +150
°C
oto +70
oto +130
°C
-0.5 to 7
Vdc
-0.5 to VCC +0.5
Vdc
950
mW
Ambient Operating Temperature, TA
Junction Operating Temperature
Supply Voltage, VCC
Voltage Applied to Logic inputs
Maximum Power Dissipation
°C
DC ELECTRICAL CHARACTERISTICS - unless otherwise specified, 4.75V < VCC
< 5.25V, TA = O°C to 70°C, 7.5MHz < 1/TORC < 15MHz , 15MHz < 1/TVCO < 30MHz
PARAMETER
CONDITIONS
MIN
VIH, High Level Input Voltage
NOM
MAX
UNIT
0.8
V
2.0
VIL, Low Level Input Voltage
V
IIH, High Level Input Current
VIH = 2.7V
20
J,JA
ilL, Low Level Input Current
VIL = O.4V
-0.36
rnA
VOH, High Level Output Voltage
IOH = -400J,JA
2.7
V
VOL, Low Level Output Voltage
IOL= 4mA
0.5
V
ICC, Power Supply Current
All outputs open
165
rnA
DYNAMIC CHARACTERISTICS AND TIMING
READ MODE (See figure 9)
TRD, Read Data Pulse Width
TORC-40
nS
TFRD, Read Data Fall Time
2.0V to 0.8V, CL:<:; 15 pF
15
nS
TRRC, Read Clock Rise Time
0.8V to 2.0V, CL:<:; 15pF
8
nS
TFRC, Read Clock Fall Time
2.0Vto 0.8V, CL:<:; 15pF
5
nS
20
TPNRZ, NRZ (out)
Propagation Delay
-15
15
nS
TPAMD,AMD
Propagation Delay
-15
15
nS
-4
+4
%
1/4 Cell + Retriggerable
One-Shot Detect Stability
3-24
0188
SSI32D5321
Data Synchronizer!
2, 7 RLL ENDEC
READ MODE (Cont.)
PARAMETER
CONDITIONS
1/4 Cell + Retriggerable
One-Shot Delay·
TD=6.14(RR +O.S)
+ 0.172Rd (Cd +11.S)
RR = Kil
Rd=KQ
Cd = 68pF to 100pF
Note: •
MIN
MAX
UNIT
0.89TD
1.11TD
nS
= Excludes External Capacitor and Resistor Tolerances
WRITE MODE (See figure 10)
TWO, Write Data Pulse Width
CL :S;1SpF
TFWD, Write Data Fall Time
2.0V to 0.8V, CL:S; 1SpF
TOWC
TRWC
TFWC
(TORO/2) -12 (TORO/2) + 12
Write Data Clock
Repetition Period
8
TORO -12
Write Data
Clock Rise Time
0.8Vto 2.0V
Write Data
Clock Fall Time
2.0Vto O.SV
TaRO +12
nS
nS
nS
10
nS
S
nS
TSNRZ, NRZ (in) Set Up Time
20
nS
THNRZ, NRZ (in) Hold Time
7
nS
DATA SYNCHRONIZATION
PARAMETER
CONDITIONS
TVCO VCO Center Frequency
Period
VCO IN = 2.7V
TO = 1.23E - 11 (RR +SOO)
VCC= S.OV
1.0V:S; VCO IN :S; VCC -0.6V
VCC= S.OV
VCO Frequency
Dynamic Range
KVCO VCO Control Gain
KD
Phase Detector Gain
= 21t1 TO
1.0V:S; VCO IN :S; VCC -0.6V
(00
KD = 0.309 1 (RR + SOO)
VCC= S.OV
MAX
UNIT
0.8TO
1.2TO
sec
±27
±40
%
0.14roo
0.20roo
MIN
ra.d.
sec-V
0.83KD
1.17 KD
KVCO x KD Product
Accuracy
-28
+28
0/0
VCO Phase Restart Error
-O.S
+O.S
rad
±(0.01
nS
Decode Window
Centering Accuracy
Alrad
TORe + 2)
Decode Window
0188
NOM
(TORC/2) ·2
3-25
nS
SSI3205321
Data Synchronizer!
2, 7 RLL ENOEC
DATA SYNCHRONIZATION (Cont.)
PARAMETER
TS1
CONDITIONS
NOM
MIN
MAX
UNIT
Decode Window Time
Shift Magnitude
TS1 = 0.015 TORC
0.85 TS1
1.15 TS1
sec
TS2
Decode Window Time
Shift Magnitude
TS2 = 0.06 TORC
0.90 TS2
1.1 TS2
sec
TS3
Decode Window Time
Shift Magnitude
TS3 = 0.075 TORC
0.90 TS3
1.1TS3
sec
TSA
Decode Window Time
Shift Magnitude
1.35TSA
sec
TSA=0.125TORC(1- 680+R) 0.65 TSA
1180 + R
with: R in ohms
CONTROL CHARACTERISTICS (See figure 11)
TSWS, WSO, WS1, WSD
Set Up Time
50
nS
THWS, WSO, WS1, WSD
Hold Time
0
nS
RG, WG, SOFT/HARD
Time Delay
100
nS
/
RD
RRC
NRZ(OUn
FIGURE 9: READ TIMING
3-26
0188
SSI3205321
Data Synchronizer!
2, 7 RLL ENOEC
REFERENCE
OSCILLATOR
WCLK
NRZ(IN)
FIGURE 10: WRITE TIMING
wso
WSf
WSD
-.-
-'--
\~~J
_TSWS
WSL
-II
•
_THWS
-f-
'----~/
FIGURE 11: CONTROL TIMING
0188
3-27
~I\)
0 U'J
"""!.~
:::oD)w
.(1)1\)
.'< 0
CJ1
m ::lnw
(
VPA
"'--r--r-r-"")~
Z::::r'1\)
0""1-'"
TO.,.P
mg
RR
0-'
N
IREF
CD
:::!.
SS132R510A
ANI
c.u
I
I\)
ex>
0.01,_
WOI
1
aoont
SSI32C452A
STORAGE
CONTROLLER
AGND
DGND
soo
TYPICAL 551 3205321 APPLICATION
~
&l
SSI3205321
Data Synchronizer/
2, 7 RLL ENOEC
APPLICATIONS INFORMATION
REFERENCE OSCILLATOR
An internal reference oscillator, operating at twice the data rate, generates the standby reference for the PLL. A
series resonant crystal between XTAL 1 and XTAL2, should be selected at twice the Data Rate. If a crystal
oscillator is not desired, then an external TTL compatible reference may be applied to XTAL 1, leaving XTAL2 open.
An R-C network is employed on the demonstration board for operation with the crystal oscillator. The purpose
of this network is to minimize the coupling of noise into the clock. The 3K.o resistor from XTAL2 to ground helps
to speed up the oscillator transitions, while the R-C network from XTAL 1 to ground lowers the impedance to reduce
capacitive coupling effects. In applications utilizing a TTL compatible reference Signal, this network should be
removed.
If it is desired to operate a crystal at a non-fundamental or harmonic frequency, then the following network is
suggested:
XTAL 1
XTAL2
~.~
~'"
CyL
The typical input impedance looking into XTAL 1 is approximately Rin = 250.0. It is recommended to design the
value of 00 at approximately 10 to 15. Therefore, a resonant frequency of Fo = 20M Hz would result in L== 0.16JlH
and C == 380pF.
0188
3-29
I
SSI32D5321
Data Synchronizer!
2, 7 RLL ENDEC
LOOP FILTER
The performance of the SSI 3205321 is directly related to the selection of the loop filter.
characteristics should be optimized for:
(A)
The loop filter
Fast Acquisition
The ability of the loop to quickly obtain lock when the input signal to the Phase Detector is switched
between the reference oscillator (crystal) and the Read Data (RD). Fast acquisition implies a large loop
bandwidth so that it can quickly respond to changes at the input.
(8)
Data Margin
The ability of the loop to ignore bit shifts (jitter) and maintain a well centered window about the data pulse
train. In general, it is not desirable to allow the loop to respond to a single shifted bit as this would cause
the subsequent bit to be poorly centered within its window and possibly cause an error. This requirement
implies a small loop bandwidth reducing the sensitivity to high frequency jitter.
(C)
Data Tracking
The ability to respond to instantaneous changes in phase and frequency of the data. This can be a result
of such phenomena as disk rotational speed variations which cause changes in the characteristics of the
incoming data stream. In general, this requirement is consistent with that of fast acquisition, however, this
depends upon the application.
AHhough the loop performance characteristics place conflicting requirements on the loop bandwidth, the
architecture of the SSI 3205321 significantly simplifies the design by minimizing the "step in phase" and "step in
frequency" encountered when switching the Phase Detector input reference signal. A zero phase restart
technique is employed to minimize the initial phase error while the standby reference oscillator keeps the veo
at the center frequency during non-read modes.
One approach in determining the initial loop filter selection is to consider the requirements imposed during
acquisition. This includes both acquiring lock to the crystal reference in non-read modes, as well as locking to the
preamble field prior to decoding data. The format of the sector will dictate which of these two criteria imposes the
tightest restriction on acquisition.
The requirements for acquiring lock to the crystal oscillator are application specific and usually depend upon the
length of the Write Splice gap. Therefore, the design approach employed in this analysis will be based upon the
requirements during acquisition to the preamble field. The length (in time) of the preamble field is set by the SSI
3205321 locking sequence. Knowing this length in time, and that our initial phase error is less than 0.5 radians,
we can determine an acceptable loop bandwidth (ron) and damping factor (~).
3-30
0188
SSI32D5321
Data Synchronizer!
2, 7 RLL ENDEC
One possible loop filter configuration is as follows:
I
The role of C1 is as an integrating element. The largerthis capacitance, the longerthe acquisition time; the smaller
the capacitance, the greater the ability to track high frequency jitter. The resistor R reduces the phase shift induced
by C1. The capacitor C2 will suppress high frequency transients and will have minimal effect on the loop response
if it is small relative to C1 (typically C2 = C1/10)
The loop filter transfer function is:
F (s) Vout
lin
If C2 «
1 +sRC 1
sC 1 ( 1 +sC 2 R +C 2 /C 1 1
C1, then:
F(s)= V~
lin
1 +sRC 1
sC 1
The overall block diagram for the phaselock loop can be described as:
r
I-- I
.
+
r;;;::;r
r-.:-=l
KVCO
9In(s)
____.EE>____.~----.~----.
t-
s
~------~~~------~
0188
3-31
90u!(s)
SSI32D5321
Data Synchronizer!
2, 7 RLL ENDEC
Where,
KO = Phase Oetector gain [Alrad]
F(s) = Loop filter impedance [VIA]
KVCO/s
= VCO control gain
[radlsec-V]
N = The ratio of the reference input frequency to the VCO output frequency
The closed loop transfer function is;
T (s)
Sout (s)
Sin (s)
G (s)
1 +G (s) H (s)
KOoKVCO[(1 +SRC1)/C~
by putting the characteristic equation (denominator) in the form of;
2
s +2s~ron+con
2
we can solve for ron and ~ to get;
2
con
=
s= N·KO·KVCO·R
NoKOoKVCO
C1
2ron
Now we can solve for R, C1 and C2:
C1
= N·KO·KVCO
2
ron
R
2~ron
N ·KO·KVCO
where: ron = loop bandwid1h
~ = loop damping factor
3-32
0188
SSI3205321
Data Synchronizer!
2, 7 RLL ENOEC
Because of the nature of Run Length Limited (RLL) codes, the Phase Detector will only be enabled during a data
pulse. This technique allows the veo to run at a center frequency with period, TVeO, equal to one encoded data
bit cell time.
Figure 12 represents the relationship between the veo output when locked to various Phase Detector input
signals.
--I
TVCO
I
f--
VCOOUTPUT
REFERENCE OSCILLATOR
INPUT
'3T'INPUT
'4T'INPUT
~
'8T'INPUT
~
n
IL
IL
FIGURE 12: RELATIONSHIP OF VCO OUTPUT TO PHASE DETECTOR INPUT
The average amplitude of the Phase Detector gain depends upon the Phase Detector input signal. When the PLL
is locked to the reference oscillator, the Phase Detector is continuously enabled and the gain is at its maximum.
When the PLL is tracking data and the input is an "8T" pattern, then the Phase Detector gain is at its minimum.
The following indicates the value of "N" for various input.conditions:
N
= 1.0
N = 0.33
N
= 0.25
N = 0.125
, for Gin
= reference oscillator
, for Gin = 3T (100) preamble field (maximum data frequency)
, for Gin
= 4T (1000) preamble field
,for Gin = 8T (minimum data frequency)
Throughoutthis analysis the PLL has been considered as a continuous time system. In actuality the characteristics
of the Phase Detector result in a sampled data system. By utilizing an integrating loop filter to average and smooth
the Phase Detector change pump output pulses, this analogy should be reasonable.
0188
3-33
SSI32D5321
Data Synchronizer/
2, 7 RLL ENDEC
LOOP FILTER - Example for a 10Mblt/sec Soft Sector Application
In the Soft Sector mode the PLL locking sequence allows the veo to be within a determined amount of error after
38 x '3T' (100) bit groups. At 10Mbitlsec each data bit cell time, TYeO, is equal to 50nS. This results in:
tmax
= (38)
(3) (50nS)
= 5.7~S
Therefore, the PLL has 5.7~S to settle to within an acceptable amount of error before tracking and decoding data.
Because the SSI32D5321 employs a zero phase restart technique, the initial phase error is less than 8% TORe
(O.5rad) or:
~ee
< (O.08)(100nS)
~ee
< 8nS
Determining an acceptable amount of phase error after locking to the preamble field depends upon the system
requirements. In addition, it may be necessary to consider the effects of frequency steps in applications where
motor speed control tolerances are significant. Generally, an acceptable amount of error is defined to be that
amount which when added to all other timing error contributors, results in the data being within its timing window
by the required margin.
3-34
0188
SSI32D5321
Data Synchronizer!
2, 7 RLL ENDEC
In general, it is desirable to have the loop damping factor "~" between 0.5 and 1.0 during acquisition. For a high
gain, second-order loop this results in minimal noise bandwidth. For this example we will let ~ = 0.7.
Figure 13 represents the phase errors response in time to a transient step in phase as a function of the loop
bandwidth and damping factor. Figure 14 indicates the response of the veo control voltage to compensate for
this step in phase.
I
1.0
0.9
0.8
~
0.7
a:
0
a:
a:
w
o.s
l\
1\
w
0.4
«
I
0.3
0
w
0.2
...J
0.1
::2:
a:
0
0
(/)
0..
!:::!
«
z
\
0.6
i\
~
~
-{ =Lls.o)
-0.3
rl~ = 2.0
T
~\
1\1\ I\~
-0.1
-0.2
.\
1\,1\ \ \
;'
~
1:::"1'7'
,..-fA ..:;>( bl,
,..- fo... V
:---
:--..
--V- I"'-
'"
-0.4
-o.s
0
2
4
3
~=
1.0
~= 0.7
~=
o.s
~=
0.3
s
6
7
8
ron!
FIGURE 13: TRANSIENT PHASE ERROR
0188
3-35
ge(i) DUE TO A STEP IN PHASE
~9
SSI32D5321
Data Synchronizer/
2, 7 RLL ENDEC
0.8
0.7
CI:
0
CI:
CI:
UJ
UJ
f-'
0.6
/
II. /
0.5
0.4
fj'
C/)
«
:t:
a.
Cl
UJ
N
0.3
0.2
::::;
0.1
:::E
CI:
0
z
-0.1
«
0
II
1;= 0.3
1;=0.5
1;=0.7
r--.< '\1\
II ....... r--.~
/ 1/
,
~
/v
V
I; -1.0
1;=2.0
1;=5.0
-0.2
<'
"~r\
......
JV
l-
r--.
......
V
.;.
\
1\
...y
-0.3
o
2
3
4
5
6
7
8
ronl
FIGURE 14: TRANSIENT PHASE ERROR ee(t) DUE TO A STEP IN FREQUENCY L\ro
3-36
0188
SSI32D5321
Data Synchronizer!
2, 7 RLL ENDEC
As shown in Figure 13, with C= 0.7, our initial transient phase error will be at most 22% of its original value at ront
= 2.3,7.5% at ront =4.0, etc. Forthis example we want the final phase error to be less than 1% of its original level.
This results in a ront between 5 and 6. To simplify the results, let ront = 5.7.
Now,
ront = 5.7
and
tmax = 5.7f.1S
:. ron = 1.0· 106 rad/sec
with
C= 0.7
Since we are evaluating the loop response during acquisition to the '3T' preamble, N = 0.33.
Now we have all the information required to calculate the loop filter component values.
RR = 3567Q
ron =
1.0· 106 rad/sec
c
= 0.7
KD(typ) = 0.309/(RR+500) = 7.6 • 10·s A/rad
KVCO(typ) = 0.17(00 = 0.17(21t)/T0 = 2.14.10 7 rad/sec-volt
N = 0.33
which results in:
R
C,
2Cron
=26Q8Q
N·KD·KVCO
N· KD· KVCO = 537pF
2
or,
PO OUT
O)---I--'---5-37-p-F-I--'---~O veo IN
1I
26080
0188
3-37
54 pF
SSI3205321
Data Synchronizer!
2, 7 RLL ENOEC
This loop filter configuration and its component values should be considered a starting point. The final value of
ron depends upon the system requirements and can certainly be optimized for a specific application. In the table
below, we have listed some suggested external component values for several common data rates.
EXTERNAL COMPONENT VALUES
BANDWIOTH
DATA RATE
(MbiVSEC)
DAMPING
FACTOR,
LOCK TIME
lmax(J.lS)
ron!
rol(:l
RR(KQ)
Cd (pF)
Rd(KQ)
R(KQ)
C1 (pF)
C2(pF)
7.5
0.7
7.5
5.0
6.67 x 105
4.92
100
11.0
3.0
687
69
10.0
0.7
5.7
5.7
1.0 x 106
3.57
82
10.0
2.7
510
51
15.0
0.7
3.8
5.7
1.5 x 106
2.21
100
6.22
1.8
510
51
LAYOUT CONSIDERATIONS
As with other high frequency analog devices the 881 32D5321 requires care in layout. The designer should keep
analog signal lines as short as possible and well balanced. Use of a ground plane is recommended, along with
supply bypassing to separate the 881 32D5321 , and aSSOCiated circuitry, from other circuits on the PCB.
3-38
0188
SSI32D5321
Data Synchronizer/
2, 7 RLL ENDEC
PACKAGE PIN DESIGNATIONS
(TOP VIEW)
~
~lil
~
~
1
28
27
28
SOFTiJUiRD
WG
VPA
WI)"
"SOO
VPO
1m
XTAl2
RG
SOS
EPO
XTALl
NC
VCOIN
PO OUT
AGNO
RS
RF
IREF
rf § ~
4
XTAl2
8
24
XTALl
7
23
DGND
NlC
8
22
RRC
VCOIN
9
21
WCLK
PDOUT
10
20
NRZ
19
AIm
5
DGNO
RRC
50S
EPD
WClK
~
WSl
WSD
2
25
RG
NRZ
3
AGND
WS1
W§i
11
12
13
14
15
~
if
II.
~
28-Pln DIP
~
18
;
17
18
~
...J
~
28-Pln PLCC
ORDERING INFORMATION
ORDER NO.
PKG.MARK
881 3205321 28 Pin PLCC
881 3205321 - C28H
3205321 -CH
881 3205321 28 Pin Plastic OIP
881 3205321 - C28P
3205321 -CP
PART DESCRIPTION
No responsibility is assumed by SSi for use of this product nor for any infringements of patents and trademarks or other rights of third parties
resulting from its use. No liosnse is granted under any patents, patent rights or trademarks of SSi. SSi reserves the right to make changes
in specifications at any time without notios.
CA 92680, (714) 731-7110, TWX 910-595-2809
Silicon Systems, Inc., 14351 Myford Road, Tustin
0188
©1988 Silicon Systems, Inc.
3-39
NOTES:
SSI320534
Data Synchronizer!
MFM EN DEC
INTEGRATION
July, 1988
DESCRIPTION
FEATURES
The SSI 320534 Data Synchronizer/MFM ENDEC is
intended to provide data recovery and data encoding in
storage systems which employ an MFM encoding
format. Data synchronization is performed with a fully
integrated high performance PLL and encoding is
performed in soft/hard sector formats with optional
write precompensation through the internal delay line.
The SSI 320534 has been optimized for operation as
a companion device to the SSI 32C452 and the AIC
010 family of controllers. The frequency setting elements are incorporated within the SSI 320534 for
enhanced performance and reduced board space.
Data rate, adjustable from 5 to 1OM bits/sec, is established with a single external programming resistor for
Direct Sync operation or with two external resistors for
Auto Sync operation.
•
•
•
•
•
•
•
•
•
The SSI 320534 utilizes an advanced bipolar process
technology that affords precise decode window control
without the requirement of an accurate 114 cell delay or
Data Synchronizer and MFM ENDEC
5 to 10 Mblts/sec operation programmed with a
single external resistor
Optimized for operation with the SSI 32C452
and AIC 010 family of controllers
Programmable decode window symmetry via a
~P port and/or analog pins
Programmable write precompensation
Fast acquisition phase locked loop - zero phase
restart technique
Fully Integrated data separator - no external
delay lines or active devices required
+5V operation
28 pin DIP and PLCC packages
(Continued)
BLOCK DIAGRAM
VPD
VPA
DONO
AGND
POOUT
VCOIN
PIN DIAGRAM
RF
RS
WSO
WSf
~
WSl
REFERENCE
CURRENT
GENERATOR
PCS
Wl5"
XTAL2
VPD
XTAL1
RRC
DGND
XTAl1
RRC
XTAl2
NRZ
NC
RG
WG
NC
WliM/AMi5
~
IREF
NRZ
NC
WSL
RF
WSD
me
wmrm.rJ
PCS
CAUTION: Use handling procedures necessary
1788
3-41
for a static sensitive component.
5S1320534
Data Synchronizer!
MFM ENDEC
DESCRIPTION (Continued)
external devices. To enhance disk drive testability,
decode window symmetry control is available through
a digital microprocessor port and/or two analog pins.
This feature can facilitate automatic calibration, sys-
tematic error cancellation, and window margin testing.
A zero phase restart technique is used to minimize PLL
acquisition time. The SSI 32D534 requires a single
+5V power supply and is available in 28-pin DIP and
PLCC packages.
PIN DESCRIPTION
INPUT PINS
NAME
DESCRIPTION
RD
READ DATA. MFM encoded Read Data from the disk drive read channel, active low.
RG
READ GATE. Selects the PLL reference input and initiates the PLL synchronization
sequence. A high level selects the RD input and enables the Read Mode/Address Mark
Detection sequences. A low level selects the crystal reference oscillator.
WG
WRITE GATE. Enables the write mode.
WSL
WINDOW SYMMETRY LATCH. Used to latch the input window symmetry control bits
WSD, WSO and WS1 into an internal DAC. An active high level latches the input bits.
WSD
WINDOW SYMMETRY DIRECTION. Controls the direction of the optional window
symmetry shift.
WSO
WINDOW SYMMETRY CONTROL BIT. A low level introduces a window shift of 1.5%
of TORC (Read Reference Clock Period) in the direction established by WSD.
WS1
WINDOW SYMMETRY CONTROL BIT. A low level introduces a window shift of 6% of
TORC (Read Reference Clock Period) in the direction established by WSD. A low level
at both WSO and WS1 will produce the sum of the two window shifts.
EWC/ASM
ENABLE WRITE PRECOMP/AUTO SYNC MODE. Selects the synchronization sequence required in order to enter Read Mode, a low level selects the Auto Sync Mode.
In the Write Mode, a high level enables write precompensation.
OUTPUT PINS
NAME
DESCRIPTION
WD
WRITE DATA. MFM encoded write data output, active low. Precompensation is enabled
with the EWC/ASM input pin.
RRC
READ/REFERENCE CLOCK. A multiplexed clock source used by the controller. In the
read mode, this clock is the VCO frequency divided by two (1ITORC) and in the write
mode it is the crystal reference frequency divided by two (1ITORO).
3-42
0788
551320534
Data Synchronizer!
MFM EN DEC
PIN DESCRIPTION (Continued)
BIDIRECTIONAL PINS
NAME
DESCRIPTION
NRZ
NRZ DATA PORT. Read data output when RG is high and write data input when WG
is high.
WAM/AMD
WRITE ADDRESS MARK/ADDRESS MARK DETECT. In the Write Mode, used to
delete clock/data pulses in the MFM encoded output stream, WD, active low. In the Read
Mode, a latched low level output indicates that an address mark has been detected.
ANALOG PINS
0788
NAME
DESCRIPTION
IREF
TIMING PROGRAM PIN. The VCO center frequency, 1/4 cell delay and the 1F Detect
Retriggerable One Shot timing is a function of the current sourced into pin IREF. The
current is set by an external resistor, RR, connected from IREF to VCC.
XTAL1, XTAL2
CRYSTAL OSCILLATOR CONNECTIONS. If a crystal oscillator is not desired, XTAL1
may be driven by a TTL signal with XTAL2 open. The frequency must be at twice the data
rate.
PDOUT
PHASE DETECTOR OUTPUT. Drives the Loop RHer input.
VCOIN
VCO CONTROL INPUT. Driven by the Loop FiHer output.
1FS
1 F DETECT SET. Used to program the 1F detect timing with an external resistor, RT,
connected from pin 1 FS to ground. The 1F Detect period is the sum ofthe 1/4 cell delay,
TOC, plus the Retriggerable One-Shot delay, TOS, and is normally set to 1 1/4 bit cell
times.
RF,RS
WINDOW SYMMETRY ADJUST PINS. Provides analog control over the decode
window symmetry; typically used to null out any window symmetry offset. A resistor
connected from either RF or RS to ground will provide magnitude and direction control.
They can be used in conjunction with the digital control port WSD, WSO, and WS1.
PCS
PRECOMP SET. Pin for R-C network to program write precompensation early and late
times. Connect the capacitor, CPC, to VPA and the resistor, RPC, to either ground.
VPD,VPA
DIGITAL AND ANALOG +5V.
DGND,AGND
DIGITAL AND ANALOG GROUND.
3-43
SSI32D534
Data Synchronizer!
MFMENDEC
FUNCTIONAL DESCRIPTION
The SSI 320534, a high performance data synchronizer and MFM ENDEC, performs data separation,
data encoding with optional write precompensation,
Preamble detection, and Write Address Mark!Address
Mark detection. The interface electronics and the
architecture of the SS132D534 has been optimized for
use as a companion device to the SSI 32C452 or AIC
010 type Storage Controllers. It includes a zero phase
restart PLL for fast acquisition, a crystal reference
OSCillator, the write precompensation delay line, a
multiplexed Read/Reference clock output, and a bidirectional NRZ data interface.
Data rate is programmed with a single 1% external
resistor, RR, connected from pin IREF to VCC, given
by:
RR=30.67 -0.5 (Kn)
DR
Where:
DR = Data Rate in Mbitslsec.
RR=Kn
Resistor RR establishes a reference current which
controls the VCO center frequency, the phase detector
gain, the 1/4 cell delay and, indirectly, the decode
window shift (RF, RS).
The internal crystal reference oscillator, operating at
twice the data rate, generates the standby reference
input to the PLL. ' This minimizes the frequency step
and the associated acquisition time encountered when
locking the PLL onto Encoded Read Data. Additionally, in non-Read modes the RRC (Read Reference
Clock) output is generated from the reference oscillator
divided by two. A series resonant, crystal at twice the
data rate should be used. If a crystal oscillator is not
desired, an external TTL compatible reference may be
applied to XTAL1 with XTAL2 open.
READ OPERATION
The Data Synchronizer utilizes a fully integrated fast
acquisition PLL to accurately develop the decode
window. Read Gate, RG, initiates the PLL locking
sequence and selects the PLL reference input, a nigh
level (Read Mode) selects the RD input and a low level
selects the crystal reference oscillator.
The SSI32D534 provides two sync modes for controlling the PLL locking sequence, Auto Sync and Direct
Sync. The Auto Sync mode provides preamble search
and address mark detection while the Direct Sync
mode provides direct control over the input to the PLL.
These modes extend the applicabilityofthe SSI320534
to a variety of controller and interface requirements.
The appropriate mode should be selected for the given
application, see Table 1.
TABLE 1: Mode Control
MODE
WG
RG
EWCI
ASM
Idle
0
0
X
Read (Auto Sync)
0
1
0
Read (Direct Sync)
0
1
1
Write (Disable Precomp)
1
0
0
Write (Enable Precomp)
1
0
1
Illegal
1
1
X
(X = Don't Care)
AUTO SYNC MODE
The Auto Sync mode, typically used for Soft Sector
formats, activates the preamble search and address
mark detection circuitry. As depicted in Figure 1, the
SSI 320534 requires16 continuous preamble bits before switching the reference input to the PLL, 64 preamble bits before switching the Read Reference Clock
to the VCO clock divided by two, and a detected address mark prior to an additional 64 input bits in order to
enter the Read Mode. This sequence repeats after 160
input bits until Read mode is successfully entered or
until RG is cancelled.
When RG transitions high, the following PLL locking
sequence begins:
a) PREAMBLE SEARCH: The SSI32D534 searches
for 16 continous preamble bits. The Preamble
fields consistofa stream of MFM encodedO's. The
sum of the delays from the Re-triggerable One
3-44
0788
SSI32D534
Data Synchronizer!
MFM ENDEC
GAP
MFM
READ DATA
PREAMBLE FIELD
16 X'4E'
ADDRESS RELD
13X'OO'
RG
1FDETECT2
'-----------,
PLl REF. XTAL
DLYDDATA
: __________ 1~_
:-
veo RESTART 2
L----------r------------
ARC SOURCE veo
-----------'''--
XTAL
l-------------J
l- -------------:
PLL LOCKING
,
SEQUENCE ENABLE 2 _ _ _....J
INPUT COUNTER
o
18
126
64
160
NOTE 1: Dashed lines represent conditions under which JiliI!j" does not occur.
NOTE 2: Representations of internal signals
FIGURE 1: Auto Sync Mode Waveform Diagram
Shot, TOS, and the 1/4 Cell Delay, Tac, is set to
1 1/4 bit cell times with the external programming
resistor, RT. The Preamble stream has a pulse
rate of 1 bit cell time (2F frequency) which continuously resets the one-shot while a 2 bit cell period
(1 F frequency) allows the one-shot to time out
producing a 1F detect pulse. The 1 F detect pulse
resets the Input counter and the search is started
over.
VCO clock divided by 2, and the Address Mark
Detection circuitry is enabled. If a 1F detect pulse
occurs before 64 preamble bits are detected, the
PLL is locked back to the crystal reference oscillator, the RRC output is switched to the crystal
reference oscillator divided by2, the Input Counter
is reset, and the sequence is restarted. No short
duration glitches will occur during this switching.
c)
b)
PLL ACQUISITION: When 16 continuous preamble '0' bits are detected, the reference input to
the PLL is switched from the crystal reference
oscillator to the DLYO DATA, the VCO is phase
reset to the next DLYO DATA pulse, PLL acquisition begins, and the VCO clock divider is reset.
When 64 '0' preamble bits are detected, the Read
Reference Clock output (RRC) is switched to the
3-45
\
ADDRESS MARK DETECTION: The circuit
searches for the occurrence of the Address Mark.
The 1F detect circuitry remains active so that,
during the search, once a 1F is detected, the
Address Mark must be found within the next five
counts of the Read Data input pulses. If an
Address Mark is detected, priorto the Input Counter
reaching count 128, the WAMlAMDoutputis latched
low, the PLL training sequence is terminated, and
I
SSI320534
Data Synchronizer!
MFM ENOEC
DLYD
DATA
~ ~
~
~
0
vco
ARC
DATA
CELLS
DECODED
DATA
0
I
0
I
0
I
I
0
I
0
I
x
I
0
I
ADDRESS MARK
BYTE
NRZ
NOTE: NRZ output data cells are clocked out on the falling edges of RRC.
They are delayed 1 data cell relative to the input data.
FIGURE 2: Address Mark Detection and NRZ Waveform Diagram
AUTO SYNC MODE (Continued)
the Read Mode is entered allowing the data field to
be read. If the input counter reaches count 128
before the Address Mark is detected, the PLL is
locked back to the crystal reference oscillator, the
RRC output is switched to the crystal reference
oscillator divided by 2, and the PLL training sequence is restarted when the Input Counter reaches
count 160. Figure 2 depicts the Address Mark
detection sequence.
DIRECT SYNC MODE
Direct Sync Mode disables the preamble search and
address mark detection circuitry. It allows the PLL to be
controlled directly by RG, for Hard Sectorformatoperation.
When RG transitions high, the reference input to the
PLL is switched from the crystal reference oscillator to
DLYD DATA, the VCO is phase reset to the next DLYD
DATA pulse, PLL acquisition begins, the VCO clock
divider is reset, and the RRC output is switched to the
VCO clock divided by 2.
Read Gate, RG, is an asynchronous input and may be
initiated or terminated at any position on the disk.
Terminating RG locks the PLL to the crystal reference
oscillator and switches the RRC output to the crystal
reference oscillator divided by 2.
In non-Read modes the PLL is locked to the crystal
reference oscillator. This forces the VCO to run at a
frequency that is very close to that required for tracking
actual data and thus minimizes the associated frequency step during acquisition. When the reference
input to the PLL is switched, the VCO is stopped
momentarily and then restarted in an accurate phase
alignment with the next PLL reference input pulse and
the VCO clock divider is reset. By minimizing the phase
misalignment in this manner (phase error ~ ± 0.5 rads),
the acquisition time is substantially reduced.
3-46
0788
SSI320534
Data Synchronizer/
MFM ENOEC
DATA
elTCELLS
c
I
D
C
I
D
I
c
c
D
I
c
D
I
D
OLVO
DATA
veo
RRC
(DECODE WINDOW)
PHASE DET
ENABLE
FIGURE 3: Data Synchronization Waveform Diagram
DIRECT SYNC MODE (Continued)
The S8132D534 employs a dual mode phase detector;
harmonic in Read mode and non-harmonic in Idlel
Write modes. The harmonic phase detector only
updates the PLL with each occurrence of a DLYD
DATA pulse. This allows the PLL to remain phase
locked to actual Read Data. The rising edge of DLYD
DATA enables the phase detector and the falling edge
is phase compared to the rising edge of the VCO. As
depicted in Figure 3, DLYD DATA is a 1/4 cell wide
(TVCO/2) pulse whose leading edge is defined by the
leading edge of RD. In IdlelWrite modes, both phase
and frequency lock (non-harmonic) to the crystal reference oscillator is accomplished by continuously enabling the phase detector. With both phase and frequency lock to the crystal reference oscillator and the
zero phase restart acquisition technique, false lock to
DLYD DATA is eliminated.
The phase detector incorporates a charge pump in
order to drive the loop filter directly. The polarity and
width of the output current pulses correspond to the
direction and magnitude of the phase error. Figure 4
depicts the average output current as a function of the
input phase error (relative to the VCO period).
AVERAGE
OUTPUT CURRENT
AVERAGE
OUTPUT CURRENT
-21<
"ERROR
I
"ERROR
-10
a) HARMONIC MODE
b) NON-HARMONIC MODE
NOTE 1: 10 is the magnitude of the charge pump current.
NOTE 2: Phase error is relative to the VCO period.
FIGURE 4: Phase Detector Transfer Function
0788
3-47
SSI32D534
Data Synchronizer!
MFM ENDEC
DATA
Ill!
I
I
I
~
DATA
Ill!
I
I
I
I
OATA
~
Ill!
DLYD
DATA
OlYD
OATA
OlYD
OAT'
vco
vco
vco
RRC
RRC
RRC
(DECODE
WINDOW)
(DeCODE
(DECODE
WINDOW)
WINDOW)
I
--u-u
(c)
(b)
(a)
I
FIGURE 5: Decode Window a) Early, b) Normal, c) Late
DIRECT SYNC MODE (Continued)
WSD, WSO, WS1) as described in Table 2.
An accurate and symmetrical decode window is developed from the VCOclock. The rising edges of the VCO
clock are phase locked to the falling edges of DLYO
DATA as shown in Figure 3. The decode window is
then generated from the falling edges olthe VCO clock.
By utilizing a fully integrated symmetrical VCO running
at twice the data rate, the decode window is ensured to
be accurate and centered symmetrically about the
falling edges of DLYO DATA. The accuracy of the 1/4
cell delay only affects the retrace angle of the phase
detector and does not influence the accuracy of the
decode window.
Window shifts in the range of ±1 .5% to ±7 .5% olTORC
are easily programmed by latching the appropriate
control word into the Window Shift Register with the
WSL pin. Shifts in the positive or negative directions
result in early or late decode windows respectively, as
depicted in Figure 5. For applications not utilizing this
feature, WSL should be tied to ground, while WSD,
WSO & WS1 should be left floating. Additionally, for
small systematic error cancellation a resistor, R, connected from either RS (Early) or RF (Late) to ground
will provide analog control over the decode window.
The magnitude of this shift, Tsa, is determined by :
Shifting the symmetry of the VCO clock effectively shifts the relative position of the DLYD DATA pulse within the decode window. This powerful capability easily
facilitates automatic calibration, window margin testing, error recovery, and systematic error cancellation.
For enhanced disk drive testability and error recovery,
decode window control is provided via a IlP port (WSL,
Tsa (O.25)TORC
R+O.7
Where:
R isin
Kn.
Pins RF and RS are intended to be used as a trim and
should be restricted to ± 1.5% window shifts. They can
be used in conjunction with the digital control port.
TABLE 2: Decode Window Symetry Control
Ts, NOMINAL WINDOW SHIFT
WSD
WS1
0
1
1
1
0
+TS3
0
0
0
0
0
0
0
0
1
1
1
+TS1
+TS2
WSO
1
-TS1
1
1
0
-TS2
1
-TS3
1
0
0
0
3-48
1
0788
551320534
Data Synchronizer/
MFM ENDEC
NRZ
CRYSTAL
OSCILLATOR
RRC
I
INPUT
DATA CELLS
OUTPUT
DATA CELLS
NOTE 1: NRZ and WAM inpu1s are clocked in on the rising edges of RRC (input data cell boundaries).
NOTE 2: WD output data cells are defined in terms of the falling edges of RRC. They are delayed 1 1/2 data cells relative to the
input data cells.
FIGURE 6: Write Address Mark IAddress Write Data Waveform Diagram
WRITE OPERATION
In the Write Mode, the SSI320534 converts NRZ data
(from the Controller) into MFM data, for storage onto
the disk. It performs write precompensation, if enabled, and inserts Address Marks as requested. Serial
NRZ data is clocked into the SSI 320534 and latched
on defined data cell boundaries. NRZ data must be
synchronous with the rising edges of the RRC clock
output. Ouring a Write Oata Operation, the SSI320534
processes data and ECC fields and in a Write Format
Operation, Address Marks, Preamble, ECC, Gaps,
and 10 fields are processed. Write Gate is an asynchronous input and may be initiated or terminated at
any position on the disk. MFM encoded output write
data, WO, is delayed from input NRZ data by 1.5 Oata
Cells. Forthe successful completion of a write operation, Write Gate, WG, should not be terminated priorto
the last output Write Oata pulse.
Address Marks can be inserted into the MFM encoded
data stream, WO, with the pin WAM (Write Address
Mark). When WAM is asserted, the datal clock pulse in
the corresponding bit cell of the MFM encoded data
0788
stream is deleted. This allows specially encoded sequences (illegal MFM patterns) to be encoded using
the SSI 320534. WAM is synchronous with the RRC
clock and is internally delayed by 0.5 data cells. To
generate the missing clock A1 Address Mark pattern,
WAM is asserted during the sixth data cell of the NRZ
A1 data pattern. Figure 6 depicts the Address Mark
generation sequence.
Write Precompensation reduces the effect of intersymbol interference caused by the proximity of magnetic
transitions on the disk media. The interference is
caused by specific data patterns where flux reversals
are positioned closely together. Compensation consists of shifting write data pulses in time to counteract
forthe shifting normally exhibited in the corresponding
Read Back signal. When Precompensation is enabled, see Table1, the SSI 320534 recognizes these
data patterns and appropriately shifts the write data
pulses. Table 3 describes the Precompensation Algorithm relative to the current data bit, n, to be written.
3-49
551320534
Data Synchronizer/
MFM ENOEC
WRITE OPERATION
TABLE 3: Write Precompensatlon Algorithm
(Continued)
The SSI 320534 utilizes an internal analog delay line
to time shift the encoded write data pulses. The magnitude of the time shift, TPC, is determined by the external RC network (RPC, CPC) at pin PCS (Precomp
Set) and is given by:
BIT
n-2
BIT
n-1
BIT
n
BIT
n+1
COMPENSATION
Bit n
X
0
1
1
LATE
X
1
1
0
EARLY
1
0
0
0
LATE
0
0
0
1
EARLY
TPC = 0.21 x RPC x (CPC + 2pF),
with RPC in Kn & CPC in pF
An Early/Late compensated bit resultsi n a pulse shifted
TPC seconds before/after the nominal unshifted pulse
position.
ABSOLUTE MAXIMUM RATINGS
Operation above absolute maximum ratings may permanently damage the device.
RATING
UNIT
-65 to +150
°C
Junction Operating Temperature
o to +130
°C
Supply Voltage, VCC
-0.5 to 7
Vdc
-0.5 to VCC + 0.5
Vdc
PARAMETER
Storage Temperature
Voltage Applied to Logic inputs
ELECTRICAL CHARACTERISTICS
Unless otherwise specified 4.75 ::;; VCC::;; 5.25V, O°C::;; TA::;; 70°C, 5MHz::;; 1ITORC::;; 10 MHz;
10 MHz::;; 1ITVCO::;; 20 MHz.
PARAMETER
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
IIH
High Level Input Current
ilL
VOH
CONDITIONS
MIN
MAX
UNIT
V
2.0
0.8
V
VIH = 2.7V
20
~
Low Level Input Current
VIL = O.4V
-0.36
mA
High level Output Voltage
IOH = -400~
2.7
V
V
VOL
Low Level Output Voltage
IOL= 4mA
0.5
ICC
Power Supply Current
All outputs open
180
mA
Power Dissipation
Tj = 130°C
850
mW
3-50
0788
551320534
Data Synchronizer/
MFM ENDEC
CONTROL CHARACTERISTICS (Refer to Figure 7)
PARAMETER
TSWS
MIN
CONDITIONS
MAX
ns
ns
ns
ns
ns
ns
15
WSO, WS1, WSD Set Up Time
THWS
WSO, WS1, WSD Hold Time
5
TSERG
Set up time EWC to RG
10
THERG
Hold time EWC from RG
0
TSEWG
Set up time EWC to WG
0
THEWG
Hold time Ewe from WG
0
THWS
!--~-=l~r__
WSL
~
\
EWC
---
RG
--
TSERG
,- ---- - -f--
THERG
TSEWG
WG
THEWG
~'-----
-----'y
FIGURE 7: Control Timing
TFRD
TRRC
TFRC
RRC
(READ CLOCK)
NRZ(OUT)
TPNRZ
-
TPAMD
FIGURE 8: Read Timing
0788
3-51
UNIT
SSI320534
Data Synchronizer!
MFM ENDEC
ENDEC CHARACTERISTICS
READ MODE (Refer to Figure S)
PARAMETERS
TAD
CONDITIONS
MIN
MAX
UNIT
20
TORC - 40
ns
ns
Read Data Pulse Width
TFRD
Read Data Fall Time
2.0 to O.SV
20
TARC
Read ClockRise Time
O.S to 2.0V; CL:O; 15pF
10
ns
TFRC
Read Clock Fall TIme
2.0V to O.SV; CL:O; 15pF
S
ns
TPNRZ
NRZ (out) Propagation Delay
-20
+10
ns
TPAMD
AMD Propagation Delay
TVCO
TVCO+15
ns
2
2
TOC
1/4 Cell Delay Accuracy
TOC = 0.25 TORO
O.STOC
1.2TOC
sec
TOS
Retriggerable One-shot
Delay Accuracy
TOS = RT (S.96E-12)
12K:o; RT:o; 36K
0.S4TOS
1.16TOS
sec
TORC
Read Clock Period
O.STORO
1.2TORO
ns
MAX
UNIT
WRITE MODE (Refer to Figure 9)
PARAMETERS
CONDITIONS
TWD
CL:O; 15pF
Write Data Pulse Width
MIN
TORO - 2TPC-10 TORO+10
TPC
PrecompensationTime
Shift Magnitude Accuracy
2K:o; RPC :o;6K
15pF:O; CPC:o; 36 pF
See Note
TFWD
Write Data Fall Time
TRRO
TFRO
TSNRZ
NRZ(in) Set Up Time
THNRZ
ns
2
2
O.STPC
1.2TPC
sec
2.0V to O.SV; C~15pF
S
ns
Reference Clock RiseTime
O.S to 2.0V; CL:O;15pF
S
ns
Reference Clock Fall Time
2.0V to O.SV; CL:O;15pF
S
ns
25
ns
NRZ(in) Hold Time
7
ns
TSWAM
WAM Set-up Time
25
ns
THWAM
WAM Hold Time
7
ns
Note: TPC=0.21 (RPC)(CPC+2pF)
3-52
0788
551320534
Data Synchronizer/
MFM ENOEC
NRZ(IN)
RRC
(REFERENCE
CLOCK)
FIGURE 9: Write Timing
DATA SYNCHRONIZATION CHARACTERISTICS
PARAMETERS
CONDITIONS
TVCO VCO Center Frequency
Period
VCOIN = 2.7V.
TO = 1.63E - 11 (RR+500)
VCC =5.0V.
2400 ~ RR ~ 6000n
VCO Frequency Dynamic
Range
KVCO VCO Control Gain
KD
Phase Detector Gain
KVCO x KD Product Accuracy
MIN
MAX
UNIT
0.78TO
1.22TO
sec
±27
±40
%
1V ~ VCOIN ~ VCC-0.6 V.
0)0 = 21t1T0
0.140)0
0.200)0
rad
sec-volls
KD = 0.308/(RR+500);
VCC =5.0 V.
2400 ~ RR ~ 6000n
0.83KD
1.17KD
..A..
VCC =5.0V.
1V~VCOIN ~
VCC-0.6V
2400 ~ RR ~ 6000n.
VCC= 5.0V
VCO Phase Restart Error
rad
-28
-0.5
Decode Window Centering
Accuracy
%
+0.5
rad
See Note
ns
ns
TORC_4
2
Decode Window
T51
Decode Window Time
Shift Magnitude
TS1 = 0.015TORC
0.85T51
1.15T51
sec
TS2
Decode Window Time
Shift Magnitude
TS2 = 0.06TORC
0.90TS2
1.10TS2
sec
TS3
Decode Window Time
Shift Magnitude
TS3 = 0.075TORC
0.90TS3
1.10TS3
sec
TSA
Decode Window Time
Shift Magnitude
0.65 TSA
TSA (025)TffiC; (R in Kn)
R+0.7
1.35TSA
sec
Note: ±(.015TORC+3)
0788
+28
3-53
551320534
Data Synchronizer!
MFM ENOEC
APPLICATION
lin
LOOP FILTER
The element in the phase lock loop which controls the
loop dynamics is known as the loop filter. Acquisition
time, data margin, and data tracking can be optimized
by the loop filter selection. One possible loop filter
configuration is shown in Figure 10, where the function
of C, is as an integrating element. The larger the
capacitance of C" the longerwill be the lock time. Ifthe
capacitance is too small, the loop will tend to track high
frequency jitter. The role of the resistor R is to reduce
the phase shift induced by C,. This is necessary since
the loop will oscillate at the frequency where the gain is
unity. The capacitor C2 will suppress high frequency
transients when switching occurs. This capacitor will
have a minimal effect of the loop response if it is small
compared to C, (typically, C 2 = C,t10).
FIGURE 10: Loop Filter
Therefore, the closed loop transfer function is now:
T(s) =0 out(s)
in(s)
o
lin
G(s)
1 + G(s)H(s)
KD x KVCO{ 1 + ~~C' )
s2+s(Nx KDx KVCOx R) +N x KDx KVCO
The loop filter transfer function is:
F(s) =V~ut
=
C,
1 +sRC,
now we can putthe characteristic equation (denominator) in the form:
SC,{ 1 +SC2R+g~)
S2 + 2s1jo n+ co n2
if C2 < C,
then,
:.COn2 NxKDxKVCO and ~ NxKDxKVCOx R
C,
F(s) V~ut
lin
2con
which results in:
The phase lock loop can be described as:
C, NxKDxKVCO
COn2
+
0",')~0""')
R
21jon
NxKDxKVCO
and C2= C,
10
For a ~ = 0.8, the relationship between con and lock time
is:
where,
KD = phase detector gain
F(s) = Filter impedance
[VIA)
KVfO =oscillator transfer function
[rad /volt - sec)
[Alrad)
N = ratio of reference inputfrequency vs. VCO output
frequency.
COn
4.5
lock time
Therefore, the loop filter components C" C2 , and R can
be evaluated for a required lock time and coding
scheme (N) frequency relationship to the VCO frequency.
With MFM coding:
N = 1, for 0in = reference oscillator
N = 0.5, for 0in = maximum data frequency
N =0.25 for 0in = minimum data frequency
3-54
0788
SSI320534
Data Synchronizer/
MFM ENOEC
VPA
SSI32R510A
RIW
ARC
AG
NRZ
.••..••••••••••••••••••..•.•••..• i ••••••.•••••• ·.•.••••·i
I mM~D
FIGU RE 11: Typical Application
Typical External Component Values for a 5 Mbit/Sec. MFM Application:
COMPONENT
CONDITIONS
X1
Series resonant crystal
VALUE
UNITS
10
MHz
RR
RT
RPC
5.62
KQ
24.8
KQ
2
KQ
CPC
15
pF
R
5.1
KQ
C1
270
pF
C2
33
pF
Loop Filter
0788
3-55
551320534
Data Synchronizer/
MFM ENOEC
PACKAGE PIN DESIGNATIONS
(TOP VIEW)
()
3:
w
~
4
3
<{
c-
>
~
2
CJl
()
c-
28
'"
~
...J
~
27
12
13
()
LL
a:
z
14
15
~ ~
16
17
18
0
...J
LL
~
~
pcs
VPA
WD
EWC
26
NC
WG
25
VPD
24
XTAL1
23
XTAL2
RD
VPD
RG
XTAL1
1FS
DGND
DGND
AGND
RRC
22
RRC
VCOIN
NRZ
21
NRZ
PDOUT
20
NC
19
WAJAlAMD"
NC
NC
w
g;
WAM/AMD
RS
IREF
NC
WSL
RF
WSD
WSO
WS1
28-pin PLCC
28-pln DIP
THERMAL CHARACTERISTICS: raja
28-pin PLCC
65°CIW
28-pin POIP
55°C/W
ORDERING INFORMATION
ORDER NO.
PKG.MARK
881320534 28-pin PLCC
881 320534-CH
320534-CH
881320534 28-pin POIP
881 320534-CP
320534-CP
PART DESCRIPTION
No responsibility is assumed by SSi for use of this product nor for any infringements of patents and trademarks or other rights of third parties
resulting from its use. No license is granted under any patents, patent rights or trademarks of SSi. SSi reserves the right to make changes
in specifications at any time without notice.
14351 Myford Road, Tustin, CA 92680
(714) 731-7110, TWX 910-595-2809
©1988 Silicon Systems, Inc.
0788
3-56
SSI320535
Data Synchronizer/
2, 7 RLL ENDEC with
Write Precompensation
INNOVATORS IN INTEGRATION
---------------------------------------January, 1988
DESCRIPTION
FEATURES
The SSI 320535 Data Separator provides data recovery, data encoding, and write precompensation for
storage systems which employ a 2, 7 RLL encoding
format. Data synchronization is performed with a fully
integrated high performance PLL. A zero phase
restart technique is used to minimize PLL acquisition
time. The SSI32D535 has been optimized for operation as a companion device to the SSI 32C452A and
the AIC 010 controllers. The VCO frequency setting
elements are incorporated within the SSI 320535 for
enhanced performance and reduced board space.
Data rate is established with a single external programming resistor. The SSI32D535 utilizes an advanced bipolar process technology which affords precise decode window control without the requirement of an
accurate 1/4 cell delay or external devices. To enhance disk drive testability, decode window symmetry
control is available through a digitalllP port and/or two
analog pins. This feature can facilitate defect mapping,
automatic calibration, systematic error cancellation,
window margin testing, and error recovery. The SSI
320535 requires a single +5V power supply and is
available in 32-pin DIP and SOW packages.
•
Data Synchronizer and 2, 7 RLL ENDEC
•
•
Write Precompensation
•
•
•
•
•
•
•
•
•
7.5 to 15 Mblts/sec Operation
Programmed with a Single External Resistor
Optimized for Operation with the SSI 32C452A
and AIC 010 Controllers
ESDI compatible
Programmable Decode Window Symmetry via a
IlP Port and/or Analog Pins
Fast Acquisition Phase Locked Loop
• Zero Phase Restart Technique
Fully Integrated Data Separator
• No External Delay Lines or Active Devices
Required
Crystal Controlled Reference Oscillator
Hard/Soft Sector Operation
+5V Operation
32·Pln DIP and SOW Packages
BLOCK DIAGRAM
DGND AGND
EPO
PO
OUT
PIN DIAGRAM
vco
tw1'
IN
WG
32
2
VPA
soo
RG
WG
,..,
SO
XTAL
,----------------------------r-
PLL REF2
DLYO DATA
ADDRESS
DETECT
veo
L_________________________________~
1--:
~
L__________________________________~
I-----------------------------------l-·... o.-o.·-o.··
a!"~~2
RESTART 2
RRCSOUACE 2
___-'n
veo
XTAL
AMD
NRZ
_o._.._J
__o....J
lXXXXXXXXXXXXXXXXl--o.o.·-o.-...
INPUT COUNTER 2
10
I
.8
80
Notes: 1) Dashed lines represent conditions where ~dld not occur
2) Representations of Internal signals
3) Dotted lines represent a high irr(Jedance output state
FIGURE 4: Soft Sector Mode Timing Diagram
0188
3-67
551320535
Data Synchronizer! 2, 7 RLL ENDEC
with Write Precompensation
RRC
DEgf.g.ED
IXXXXXXXXXXXXXX
I I I I I I I I
1
1
1
1
1
I
----.T..
I
I
0
0
o
I
·---+i.,
: - - - - A 1 S - I...- - - C 1 S1
+----------SYNCFIELD
NRZ
Notes: ·1) These four bits can be any combination.
e16
(1100) was selected in this example
·2) The SE,l of the SEAx'6 Address Mark is not read back
+3) Representations of internal signals
FIGURE 5: Address Mark Detection and NRZ Output Waveform
4T (1000) PREAMBLE FIELD
PLL REF2
XfAL
DLYDDATA
VCORESTART 2
RRC SOURCE 2
I
I.
.
-.-n'--__________________________
VCO _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
Xf~
NRZ
INPUT COUNTER
DATA FlELD
~
~
!XxxxxxxXX>!--------
---l
--t-------------------t---------------32
Notes: 1) Dashed lines represent a high
i~dance
output state
2) Representations of internal signals
FIGURE 6: Hard Sector Mode Timing Diagram
3-68
0188
551320535
Data Synchronizer/ 2, 7 RLL ENDEC
with Write Precompensation
INPUT COUNTER
31
32
I
I
ENCODED 2. 7 DATA
DLYD DATA l '
I
VCOOUT 1'
RRC
DECODED NRZ DATA
2
NRZOUTPUT •
1
I
-----------+------1
Notes: ·1) Representations of internal signals
·2) In hard sector mode the NRZ output is inverted
FIGURE 7: Hard Sector Mode Decode Timing
_ 5 16 - - E 1 e - - - - - - A 1 S - - X 1 6 1 * - - O A T A -
'1'1'1'101'101'101'1'101010101,1
NRZ
VCOOUT2""
RRC(WCLK)
ENCODED 2. 7
DATA
Notes: *1) XlI can be any coni>ination,
C16
(1100) was selected in this exarrple
·2) Representations of internal signals
·3) Deleted ouput pulse to encode Address Mark
FIGURE 8: Write Address Mark Generation
0188
3-69
SSI320535
Data Synchronizer! 2, 7 RLL ENDEC
with Write Precompensation
ABSOLUTE MAXIMUM RATINGS
PARAMETER
RATINGS
UNIT
Storage Temperature
-65 to +150
°C
°C
Junction Operating Temperature, Tj
oto +70
oto +130
°C
Supply VoHage, VCC
-0.5 to 7
Vdc
-0.5 to VCC +0.5
Vdc
950
mW
Ambient Operating Temperature, Ta
Voltage Applied to Logic inputs
Maximum Power Dissipation
DC ELECTRICAL CHARACTERISTICS - unless otherwise specified, 4.75V < VCC
< 5.25V, Ta = O°C to 70°C, 7.5 MHz < 1ITORC < 15 MHz, 15 MHz < 1/TVCO < 30 MHz
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNIT
TIL Inputs:
VIH, High Level Input Voltage
2.0
VIL, Low Level Input Voltage
V
0.8
V
IIH, High Level Input Current
VIH = 2.7V
20
~
ilL, Low Level Input Current
VIL = O.4V
-0.36
mA
TIL Outputs:
VOH, High Level Output Voltage
IOH = -400~
VOL, Low Level Output Voltage
IOL=4mA
2.7
V
0.5
V
Test Point Outputs: DRD, VCO CLK (See Figure 12)
VOH, High Level Ouput Voltage
RL= 1300 to VPD,
2000 to DGND
VOL, Low Level Output Voltage
RL= 1300 to VPD,
2000 to DGND
ICC, Power Supply Current
All outputs open
VPD-0.720
V
iVPO - 1.625
V
180
mA
TO RC-40
ns
DYNAMIC CHARACTERISTICS AND TIMING
READ MODE (See figure 9)
TRD, Read Data Pulse Width
20
TFRD, Read Data Fall Time
2.0V to 0.8V, CL ~ 15 pF
15
ns
TRRC, Read Clock Rise Time
0.8V to 2.0V, CL ~ 15pF
8
ns
TFRC, Read Clock Fall Time
2.0V to 0.8V, CL ~ 15pF
5
ns
3-70
0188
SSI320535
Data Synchronizer/ 2, 7 RLL ENDEC
with Write Precompensation
READ MODE (Cont.)
PARAMETER
MIN
CONDITIONS
NOM
MAX
UNIT
TPNRZ, NRZ (out)
Propagation Delay
-15
15
ns
TPAMD,AMD
Propagation Delay
-15
15
ns
-4
+4
0/0
0.89TD
U1TD
ns
1/4 Cell + Retriggerable
One-Shot Detect Stability
1/4 Cell + Retriggerable
One-Shot Delay'
Note: •
4.5V < VCC < 5.5V
TD = 6.14(RR +0.5)
+ 0.172Rd(Cd +11.5)
RR=KQ
Rd=KQ
Cd = 68 pF to 100 pF
= Excludes External Capacitor and Resistor Tolerances
WRITE MODE (See Figure 10)
PARAMETER
CONDITIONS
TWD, Write Data Pulse Width
CL~15
TFWD, Write Data Fall Time
2.0V to 0.8V, CL ~ 15 pF
TOWC
TRWC
TFWC
pF
Write Data Clock
Repetition Period
MIN
MAX
(TORO/2)-12
(TORO/2) +12
ns
8
ns
TaRO +12
ns
10
ns
8
ns
TORO-12
Write Data
Clock Rise Time
0.8Vto 2.0V
Write Data
Clock Fall Time
2.0Vto 0.8V
UNIT
TSNRZ, NRZ (in) Set Up Time
20
ns
THNRZ, NRZ (in) Hold Time
7
ns
(TORO/2)-2TC-12
ns
TWDC
Compensated Write
Data Pulse Width
CL~
TE,TL
Write Data
Compensation Accuracy
TC = 0.15(Rp)(Cp)
Cp = 15 pFto 36 pF
15 pF
0.8TC
1.2TC
ns
DATA SYNCHRONIZATION
PARAMETER
CONDITIONS
TVCO VCO Center Frequency
Period
VCO IN = 2.7V
TO = 1.23E - 11 (RR +500)
VCC=5.0V
VCO Frequency
Dynamic Range
0188
1.0V ~ VCO IN
VCC= 5.0V
MIN
~
NOM
MAX
UNIT
0.8TO
1.2TO
sec
±27
±40
%
VCC -0.6V
3-71
SSI320535
Data Synchronizer/ 2, 7 RLL ENDEC
with Write Precompensation
DATA SYNCHRONIZATION (Cont.)
PARAMETER
CONDITIONS
KVCO VCO Control Gain
000 = 2n/ TO
1.0V ~ VCO IN
KD
Phase Detector Gain
MIN
0.14c.oo
~
NOM
MAX
0.20000
rad
sec-V
VCC -0.6V
KD = 0.309 / (RR + 500)
VCC=5.0V
UNIT
0.83KD
1.17 KD
Alrad
KVCO x KD Product
Accuracy
-28
+28
%
VCO Phase Restart Error
-0.5
+0.5
rad
± (0.01
TORC + 2)
ns
Decode Window
Centering Accuracy
Decode Window
ns
(TORCI2) ·2
TS1
Decode Window Time
Shift Magnitude
TS1 = 0.015 TORC
0.85 TS1
1.15 TS1
sec
TS2
Decode Window Time
Shift Magnitude
TS2 = 0.06 TORC
0.90TS2
1.1 TS2
sec
Decode Window TIme
Shift Magnitude
TS3 = 0.075 TORC
0.90 TS3
1.1TS3
sec
1.35TSA
sec
TS3
TSA
Decode Window Time
0.65 TSA
TSA=0.125TORC(1- 680+R)
Shift Magnitude
1180 + R
with: R in ohms
CONTROL CHARACTERISTICS (See figure 11)
TSWS, WSO, WS1, WSD
Set Up TIme
50
ns
THWS, WSO, WS1 , WSD
Hold Time
0
ns
RG, WG, SOFT/HARD
TIme Delay
100
3-72
ns
0188
SSI32D535
Data Synchronizer! 2, 7 RLL ENDEC
with Write Precompensation
/
RD
I
RRC
NRZ (OUT)
AMD
FIGURE 9: Read Timing
REFERENCE
OSCILLATOR
WCLK
NRZ(IN)
FIGURE 10: Write Timing
0188
3-73
551320535
Data Synchronizer/ 2, 7 RLL ENDEC
with Write Precompensation
wso
WS1
WSD
-.-
-f--
I\'------+---,I
_
TSWS--------.+
_
_THWS
/
WSL
-'---
/
FIGURE 11: Control Timing
~'--~£
I+-
bit position
VCOCLK
Decode
Window
Edges
FIGURE 12: Test Point Timing
3-74
0188
o
CO
CO
SSI32RS10A
RIW
W
I
-....J
01
O.O,"F
WDI
300n
~
1.
SSI32C4S2A
c
aS»
STORAGE
CONTROLLER
en
'<
:E
-. ::::J
n
-:::r
:::r""'l
:lEg
AGND
EWl'
DGND
VPA
Cp
.i
""'I
_.
CD
(I)
-. N
"C:::!.
""'II\)
(I)
~
n ......
Rp
TYPICAL 551320535 APPLICATION
cn
°:Dcn
3._
i
·w
::::JmN
cnZ C
aCU1
-'m w
gOU1
551320535
Data Synchronizerl 2, 7 RLL ENDEC
with Write Precompensation
APPLICATIONS INFORMATION
REFERENCE OSCILLATOR
An internal reference oscillator, operating at twice the data rate, generates the standby reference for the PLL. A
series resonant crystal between XTAL1 and XTAL2, should be selected at twice the Data Rate. If a crystal
oscillator is not desired, then an external TTL compatible reference may be applied to XTAL 1, leaving XTAL2 open.
An R-C network is employed on the demonstration board for operation with the crystal oscillator. The purpose
of this network is to minimize the coupling of noise into the clock. The 3 KO resistor from XTAL2 to ground helps
to speed upthe oscillator transitions, while the R-C network from XTAL 1 to ground loWers the impedance to reduce
capacitive coupling effects. In applications utilizing a TTL compatible reference Signal, this network should be
removed.
If it is desired to operate a crystal at a non-fundamental or harmonic frequency, then the following network is
suggested:
XTAL1
XTAL2
~.~
~',F
C-yL
The typical input impedance looking into XTAL1 is approximately Rin = 2500. It is recommended to design the
value of 00 at approximately 10 to 15. Therefore, a resonant frequency of Fo = 20 MHz would result in L == 0.16
~H and C == 380 pF.
3-76
0188
551320535
Data Synchronizer! 2, 7 RLL ENDEC
with Write Precompensation
LOOP FILTER
The performance of the SSI 320535 is directly related to the selection of the loop filter.
characteristics should be optimized for:
(A)
The loop filter
Fast Acquisition
The ability of the loop to quickly obtain lock when the input signal to the Phase Detector is switched
between the reference oscillator (crystal) and the Read Data (RD). Fast acquisition implies a large loop
bandwidth so that it can quickly respond to changes at the input.
(8)
Data Margin
The ability of the loop to ignore bit shifts (jitter) and maintain a well centered window about the data pulse
train. In general, it is not desirable to allow the loop to respond to a single shifted bit as this would cause
the subsequent bit to be poorly centered within its window and possibly cause an error. This requirement
implies a small loop bandwidth reducing the sensitivity to high frequency jitter.
(e)
Data Tracking
The ability to respond to instantaneous changes in phase and frequency of the data. This can be a result
of such phenomena as disk rotational speed variations which cause changes in the characteristics of the
incoming data stream. In general, this requirement is consistent with that of fast acquisition, however, this
depends upon the application.
Although the loop performance characteristics place conflicting requirements on the loop bandwidth, the
architecture of the SSI 320535 significantly simplifies the design by minimizing the "step in phase" and "step in
frequency" encountered when switching the Phase Detector input reference signal. A zero phase restart
technique is employed to minimize the initial phase error while the standby reference oscillator keeps the veo
at the center frequency during non-read modes.
One approach in determining the initial loop filter selection is to consider the requirements imposed during
acquisition. This includes both acquiring lock to the crystal reference in non-read modes, as well as locking to the
preamble field prior to decoding data. The format of the sector will dictate which of these two criteria imposes the
tightest restriction on acquisition.
The requirements for acquiring lock to the crystal oscillator are application specific and usually depend upon the
length of the Write Splice gap. Therefore, the design approach employed in this analysis will be based upon the
requirements during acquisition to the preamble field. The length (in time) of the preamble field is set by the SSI
320535 locking sequence. Knowing this length in time, and that our initial phase error is less than 0.5 radians,
we can determine an acceptable loop bandwidth (ron) and damping factor (~).
0188
3-77
I
SSI320535
Data Synchronizer! 2, 7 RLL ENDEC
with Write Precompensation
One possible loop filter configuration is as follows:
The role of C1 is as an integrating element. The largerthis capacitance, the longer the acquisition time;the smaller
the capacitance, the greaterthe ability to track high frequency jitter. The resistor R reduces the phase shift induced
by C1. The capacitor C2 will suppress high frequency transients and will have minimal effect on the loop response
if it is small relative to C1 (typically C2 = C1/10)
The loop filter transfer function is:
F (s) Vout
1 +sRC 1
lin sC 1 ( 1 +sC 2 R +C 2 IC 1
j
If C2 « C1, then:
F (s) = V~
lin
1 +sRC 1
sC 1
The overall block diagram for the phaselock loop can be described as:
9in(s)
----t(f)~~-+~-+I Kv~olT
t
0~-----'-
3-78
90UI(S)
0188
SSI320535
Data Synchronizer! 2, 7 RLL ENDEC
with Write Precompensation
Where,
KO = Phase Detector gain rAiradl
F(s) = Loop filter impedance rV/A-
KVCO = VCOcontroi gain [racVsec-V
s
-
N = The ratio of the reference input frequency to the VCO output frequency
The closed loop transfer function is;
T (5) = Soul (5)
Sin (5)
G (5)
1 +G (5) H (5)
KO.KVCO[{1 +SRC1)/C~
by putting the characteristic equation (denominator) in the form of;
2
s +2s~ron+ron
we can solve for ron and
~
2
to get;
2
ron
N·KO·KVCO
C1
Now we can solve for R, C1 and C2:
C1
= N·KO·KVCO
2
ron
R
2~ron
N·KO·KVCO
where: ron = loop bandwidth
~ = loop damping factor
0188
3-79
I
551320535
Data Synchronizer! 2, 7 RLL ENDEC
with Write Precompensation
Because of the nature of Run Length Limited (RLL) codes, the Phase Detector will only be enabled during a data
pulse. This technique allows the VCO to run at a center frequency with period, TVCO, equal to one encoded data
bit cell time.
Figure 13 represents the relationship between the VCO output when locked to various Phase Detector input
signals.
--I
TVCOI--
VCOOUTPUT
REFERENCE OSCILLATOR
INPUT
'3T'INPUT
'4T'INPUT
'BT'INPUT
-.-n
-.-n
n
IL
IL
FIGURE 13: Relationship of VCO Output to Phase Detector Input
The average amplitude of the Phase Detector gain depends upon the Phase Detector input signal. When the PLL
is locked to the reference OSCillator, the Phase Detector is continuously enabled and the gain is at its maximum.
When the PLL is tracking data and the input is an "8T' pattern, then the Phase Detector gain is at its minimum.
The following indicates the value of "N" for various input conditions:
N = 0.33
= reference oscillator
, for Oin = 3T (100) preamble field (maximum data frequency)
N = 0.25
, for Oin = 4T (1000) preamble field
N = 0.125
,for Oin = 8T (minimum data frequency)
N
= 1.0
, for Oin
Throughoutthis analysis the PLL has been considered as acontinuous time system. In actuality the characteristics
of the Phase Detector result in a sampled data system. By utilizing an integrating loop filter to average and smooth
the Phase Detector change pump output pulses, this analogy should be reasonable.
LOOP FILTER - Example for a 10 Mblts/s Soft Sector Application
In the soft Sector mode the PLL locking sequence allows the VCO to be within a determined amount of error after
38 x '3T (100) bit groups. At 10 Mbitsls each data bit cell time, TVCO, is equal to 50 ns. This resuHs in:
tmax = (38)(3)(50ns) = 5.7 j.LS
3-80
0188
SSI32D535
Data Synchronizerl 2, 7 RLL ENDEC
with Write Precompensation
LOOP FILTER (Continued)
Therefore, the PLL has 5. 711S to settle to within an acceptable amount of error before tracking and decoding data.
Because the 551320535 employs a zero phase restart technique, the initial phase error is less than 8% TORC
(0.5rad) or:
.Me < (0.08)(100ns)
.1.ge < 8ns
Determining an acceptable amount of phase error after locking to the preamble field depends upon the system
requirements. In addition, it may be necessary to consider the effects of frequency steps in applications where
motor speed control tolerances are significant. Generally, an acceptable amount of error is defined to be that
amount which when added to all other timing error contributors, results in the data being within its timing window
by the required margin.
In general, it is desirable to have the loop damping factor "~.. between 0.5 and 1.0 during acquisition. For a high
gain, second-order loop this results in minimal noise bandwidth. For this example we will let ~ = 0.7.
Figure 14 represents the phase errors response in time to a transient step in phase as a function of the loop
bandwidth and damping factor. Figure 15 indicates the response of the VCO control voltage to compensate for
this step in phase.
1.0
0.9
0.8
~
0.7
II:
0.6
II:
II:
0.5
l\\
1\1\'
0
w
w
C/)
«
J:
0.3
o
w
0.2
-'
«
0.1
II:
0
D-
D!
:!:
0
z
11 \
0.4
\1\ \
1\ \
!\
,1\
\1\
-0.1
-0.2
1
-{
=~.o ~
11
=~.o 1
r--
~
",..-:~
r--
t''It-.
~
.... ~
I
-0.3
r--
1/'
"
-0.4
r--
,/
= 1.0
=0.7
=0.5
=0.3
-0.5
0
2
3
4
5
6
7
ron!
FIGURE 14: TRANSIENT PHASE ERROR ge(t) DUE TO A STEP IN PHASE .1.9
0188
3-81
8
I
551320535
Data Synchronizerl 2, 7 RLL ENDEC
with Write Precompensation
LOOP FILTER (Continued)
As shown in Figure 14, with ~ = 0.7, our initial transient phase error will be at most 22% of its original value at oont
= 2.3,7.5% at oont = 4.0, etc. Forthis example we want the final phase error to be less than 1% of its original level.
This results in a oont between 5 and 6. To simplify the results, let oont = 5.7.
Now,
oont = 5.7
and
tmax = 5.7~S
:. ron =
with
~=
1.0. 106 radlsec
0.7
Since we are evaluating the loop response during acquisition to the '3T' preamble, N = 0.33.
Now we have all the information required to calculate the loop filter component values.
RR= 356m
ron =
1.0· 106 radlsec
~= 0.7
KO(typ) = 0.309/(RR+500) = 7.6 • 10.5 A/rad
KVCO(typ) = 0.17000 = 0.17(27t)/T0 = 2.14 .107 radlsec-volt
N = 0.33
which results in:
R
2~CJ.)n
=26OOa
N·KO·KVCO
C 1 - ----,2:---N·KO·KVCO 537pF
or,
PO OUT Of---I.----53-7-p-F-I.---~O
i
2608Q
I
3-82
veo IN
54 pF
0188
SSI320535
Data Synchronizer! 2, 7 RLL ENDEC
with Write Precompensation
LOOP FILTER (Continued)
This loop filter configuration and its component values should be considered a starting point. The final value of
(On depends upon the system requirements and can certainly be optimized for a specific application. In the table
below, we have listed some suggested external component values for several common data rates.
DATA RATE DAMPING LOCK TIME ront
(Mbitls)
tmax ij.Ls)
FACTOR
BANDWIDTH
ron (rad)
sec
EXTERNAL COMPONENT VALUES
RR(KCl) Cd(pF) Rd(KCl)
R(Kn)
C1 (pF) C2(pF)
7.5
0.7
7.5
5.0
6.67 x 10 5
4.92
100
11.0
3.0
687
69
10.0
0.7
5.7
5.7
1.0 x 10 6
3.57
82
10.0
2.7
510
51
15.0
0.7
3.8
5.7
1.5 x 10 6
2.21
100
6.22
1.8
510
51
LA YOUT CONSIDERATIONS
As with other high frequency analog devices the SSI 32D535 requires care in layout. The designer should keep
analog signal lines as short as possible and well balanced. Use of a ground plane is recommended, along with
supply bypassing to separate the 551 32D535, and associated circuitry, from other circuits on the PCB.
0.8
0.7
II:
0
II:
II:
0.6
0.5
llJ
llJ
0.4
«
:::c
0.3
0
0.2
en
/
/,~
N
::J
0.1
a:
::2:
0
z
-0.1
«
0
"
~=0.3
K
I-r-. 1'-1-'\
~=
0.5
~=0.7
~k '\\
'I'
~r-. ...... ,,~
f
a.
llJ
I-
r
jr-7
V
V
~
,,~
- 1.0
\
~=2.0
1"\
~=5.0
-0.2
....) -
1\ .....
1
vV
f\.
-0.3
o
2
3
4
5
6
7
(Ont
FIGURE
0188
15:
TRANSIENT PHASE ERROR 8e(t) DUE TO A STEP IN FREQUENCY ~(O
3-83
8
I
SSI320535
Data Synchronizer! 2, 7 RLLENDEC
with Write Precompensation
PACKAGE PIN DESIGNATIONS
(TOP VIEW)
EWl'
SOFTIFiAR5
WG
PCS
VPA
WI5
soo
VPD
i'ID
NC
RG
XTAl2
SDS
XTAl1
EPD
DGND
RRC
VCOIN
PDOUT
WCLK
AGND
NRZ
RS
AMD
RF
WSL
IREF
WSD
wso
WS1
mm
VCOCLK
32 LEAD
sow, DIP
ORDERING INFORMATION
PART DESCRIPTION
ORDER NO.
SSI 320535 32 Pin Small Outline - Wide
SSI 320535 - CW
320535- CW
SSI 320535 32 Pin Plastic OIP
SSI 320535 - CP
320535 - CP
PKG.MARK
No responsibility is assumed by SSi for use of this product nor for any infringements of patents and trademarks or other rights of third parties
resulting from its use. No license is granted under any patents, patent rights or trademarks of SSi. SSi reserves the right to make changes
in specifications at any time without notice.
Silicon Systems, Inc., 14351 Myford Road, Tustin
©1988 Silicon Systems, Inc.
CA 92680, (714) 731-7110, TWX 910-595-2809
0188
3-84
SSI320536
Data Synchronization/
1, 7 RLL ENDEC
with Write Precompensation
INNOVATORS IN INTEGRATION
-----------------------------------------------------August, 1988
DESCRIPTION
FEATURES
The SSI 32D536 Data Synchronizer/1 ,7 RLL ENDEC
provides data recovery and data encoding for storage
systems which employ a 1,7 RLL encoding format.
Data synchronization is performed with a fully integrated high performance PLL. A zero phase restart
technique is used to minimize PLL acquisition time.
The SSI 32D536 has been optimized for operation as
a companion device to the SSI 32C452 and AIC 010
controllers. The VCO frequency setting elements are
incorporated within the SSI 32D536 for enhanced
performance and reduced board space. Data rate is
established with a single external programming resistor. The SSI 32D536 utilizes an advanced bipolar
process technology which affords precise decode
window control without the requirement of an accurate
1/3 cell delay or extemal devices. The SSI 32D536
requires a single +5V supply.
•
•
•
•
•
•
Data Synchronizer and 1,7 RLL ENDEC
7.5 to 15 Mbits/sec operation
-Data Rate programmed with a single external
resistor
Optimized for operation with the SSI 32C452 and
AIC 010 controllers.
Fast acquisition phase lock loop
- Zero phase restart technique
Fully integrated data separator
- No external delay lines or active devices requ ired
Programmable write precompensation
•
Hard and soft sector operation
•
•
Crystal controlled reference oscillator
+5V operation
•
28-pin PLCC & 28-pin DIP packages
BLOCK DIAGRAM
IEF
\'CO REF
0888
3-85
EPD
POOUT
\'CO" YCO QJ(
VAA1 VP0\2
I
SSI32D536
Data Synchronization/1, 7 RLL ENDEC
with Write Precompensation
OPERATION
The SSI 320536 is designed to perform data recovery
and data encoding in rotating memory systems which
utilize a 1,7 RLL encoding format. In the Read Mode
the SSI32D536 performs Data Synchronization, Sync
Field Search and Detect, Address Mark Detect, and
Data Decoding. In the Write Mode, the SSI 320536
converts NRZ data into the 1,7 RLL format described in
Table 1, performs Write Precompensation, generates
the Preamble Field, and inserts Address Marks as
requested. The interface electronics and architecture
of the SSI 320536 have been optimized for use as a
companion device to the SSI 32C452 or AIC 010
controllers.
The SSI 320536 can operate with data rates ranging
from 7.5 to 15 Mbits/sec. This data rate is established
by a single 1% external resistor, RR, connected from
pin IREF to VPA. This resistor establishes a reference
current which sets the VCO center frequency, the
phase detector gain, and the 1/3 cell delay. The value
of this resistor is given by:
The phase detector incorporates a charge pump in
order to drive the loop filter directly. The polarity and
width of the output current pulses correspond to the
direction and magnitude of the phase error.
The READ GATE (RG), and WRITE GATE (WG)
inputs control the device mode.
RG is an asynchronous input and may be initiated or
terminated at any position on the disk. WG is also an
asynchronous input, but should not be terminated prior
to the last output Write Data pulse.
READ OPERATION
The Data Synchronizer utilizes a fully integrated fast
acquisition PLL to accurately develop the decode
window. Read Gate, RG, initiates the PLL locking
sequence and selects the PLL reference input; a high
level (Read Mode) selects the RD input and a low level
selects the crystal reference oscillator.
An internal crystal reference oscUiator, operating at
three times the data rate, generates the standby reference for the PLL. A series resonant crystal between
XTAL 1 and XTAL2 should be selected at three times
the Data Rate. If a crystal oscillator is not desired, then
an external TTL compatible reference may be applied
to XTAL 1, leaving XTAL2 open.
In the Read Mode the falling edge of ORO enables the
Phase Detector while the rising edge is phase compared to the rising edge of the VCO/2. As depicted in
Figure 1, ORO is a 1/3 cell wide (TVCO) pulse whose
leading edge is defined by the leading edge of RD. An
accurate and symmetrical decode window is developed from the VCO/2 clock. By utilizing a fully integrated symmetrical VCO running at three times the
data rate, the decode window is insured to be accurate
and centered symmetrically about the rising edges of
ORO. The accuracyofthe 1/3cell delay only affects the
retrace angle of the phase detector and does not
influence the accuracy of the decode window.
The SSI32D536 employs a Dual Mode Phase Detector; Harmonic in the Read Mode and Non Harmonic in
Write and Idle Modes. In the Read Mode the Harmonic
Phase Detector updates the PLL with each occurrence
of a DYLD DATA pulse. In the Write and Idle modes the
Non-Harmonic Phase Detector is continuously enabled, thus maintaining both phase and frequency
lock. By acquiring both phase and frequency lock to the
crystal reference oscillator and utilizing a zero phase
restart technique, false lock to DLYD DATA is eliminated.
In Non-Read Modes, the PLL is locked to the crystal
reference oscillator. This forces the VCO to run at a
frequency which is very close to that required for
tracking actual data and thus minimizes the associated
frequency step during acquisition. When the reference
input to the PLL is switched, the VCO is stopped
momentarily, then restarted in an accurate phase
alignment with the next PLL reference input pulse, and
the VCO clock divider is reset. By minimizing the phase
alignment in this manner (phase error ~ 1 rads), the
acquisition time is substantially reduced.
RR=92.6-23(Kn)
DR
where: DR
= Data Rate in Mbits/sec.
3-86
0888
551320536
Data 5ynchronization/1, 7 RLL ENOEC
with Write Precompensation
SOFT SECTOR OPERATION
VCO LOCK & BIT SYNC ENABLE
Disk Operation Lock Sequence in Read Mode Soft
Sector Operation
When the internal counter counts 16 more "3T" or a
total of 19 negative transitions from RG enable, an
internal VCO lock signal enables. The VCO lock signal
activates the decoder bit synchronization circuitry to
define the proper decode boundaries. Also, at count
19, the RRC source switches from the reference oscillatorto VCO clock signal which is phase locked to DRD.
The VCO is assumed locked at this point. A maximum
of 2 RRC time periods may occur for the RRC transition, however, no short duration glitches will occur.
After the bit sync circuitry sets the proper decode
window (VCO in sync with RRC and RRC in sync with
data) NRZ is enabled and data is toggled in to be
decoded for the duration of the read gate.
.MCC
~
------
ADDRESS MARK DETECT
In Soft Sector Read Operation the SSI 32D536 must
first detect an address mark to be able to initiate the rest
of the read lock sequence. An address mark for the
SSI 32D536 consists of two (2) 7 "0" patterns followed
by two 11 "0" patterns. To begin the read lock sequence the Address Mark E{1able (AMENB) is asserted by the controller. The SSI 32D536 Address
Mark Detect (AMD) circuitry then initiates a search of
the read data (RD) for an address mark. Firstthe AMD
looks for a set of 6 "O's" within the 7 "0" patterns. Having
detected a 6 "0" the AMD then looks for a 9 "0" set within
the 11 "O's". If AMD does not detect 9 "O's" within 5 RD
bits after detecting 6 "O's" it will restart the Address
Mark Detect sequence and look for 6 "O's." When the
AMD has acquired a 6 "0," 9 "0" sequence the AMD
transitions low disabling AMENB after one "zero" time
period delay; one encoded clock time period later the
AMD tranSitions back high and the SSI 32D536 is
ready for a preamble search when the Read Gate is
asserted.
PREAMBLE SEARCH
After the Address Mark (AM) has been detected a
Read Gate (RG) can be asserted initiating the remainder of the read lock sequence. When RG is asserted
an internal counter counts negative transitions of the
incoming Read Data (RD) looking for (3) consecutive
3T preamble. Once the counter reaches count 3 (finds
(3) consecutive 3T preamble) the internal read gate
enables switching the phase detector from the reference oscillator to the delayed Read Data input (DRD);
at the same time a zero phase (internal) restart signal
restarts the VCO in phase with the read reference
clock. This prepares the VCO to be synchronized to
data when the bit sync circuitry is enabled after VCO
lock is established.
0888
HARD SECTOR OPERATION
Disk Operation Lock Sequence in Read Mode Hard
Sector Operation
~
I~I
1I1-3T"
vco
LOCK
J
I
BIT
SYNC
.DiECC
DATA -------
In hard sector operation the SSI 32D536's Address
Mark Detection circuitry is not enabled by a AMENB
signal and AMD remains inactive. A hard sector read
operation does not require an address mark search but
starts with a preamble search as with soft sector and
sequences identically. In all respects, with exception to
the address mark search sequence, hard sector read
operation is the same as soft sector read.
WRITE MODE
In the write mode the SSI 32D536 converts NRZ data
from the controller into 1,7 RLL formatted data for
storage on the disk. The SSI32D536 can operate with
a soft or hard sector hard drive.
In soft sector operation the device generates a '7, 11"
Address Mark, and a preamble pattern.
In the hard sector operation the device generates a
3 x "3T" preamble pattern but no preceding Address
Mark. Serial NRZ data is clocked into the SSI 32D536
and latched on defined cell boundaries. The NRZ input
data must be synchronous with the rising edges of the
3-87
I
SSI320536
Data Synchronization/1, 7 RLL ENOEC
with Write Precompensation
WCLK input. The WCLK input is a feature provided for
operation in an ESDI application to compensate for
large cable delays. In SCSI or ST5060peration, WCLK
is connected directly to the RRC output.
the VCO is locked to the reference crystal. After a delay
of 1 NRZ time period (min) from RG low, the Write Gate
(WG) can be enabled while WONRZ is maintained
(NRZ write data) low. The Address Mark Enable
(AMENB) is made active (high) a minimum of 1 NRZ
time period later. The Address Mark (consisting of
7 "O's," 7 "O's," 11 "O's, "11 "O's") and the 3 x "3T'
Preamble is then written by WOO. WONRZ goes
active at this point and after a delay of 5 NRZ time
periods begins to toggle out WOO encoded data.
Finally, at the end of the write cycle, 5 NRZ of blank
encoded time passes to insure the encoder is flushed
of data; WG then goes low.
Write precompensation circuitry is provided to compensate for media bit shift caused by intersymbol interference. The SSI 320536 recognizes specific write
data patterns and can add or subtract delays in the time
position of write data bits to counteract the read back bit
shift. The magnitude of the time shift, TC, is determined by an external R C network on the WCS pin
given by:
TPC = WP(0.053)(Rc)(Cc + Cs)
HARD SECTOR
When the write precompensation control latch, WCL is
low, the S51320536 performs write precompensation
according to the algorithm outlined in Table 3.
In hard sector operation, when read gate (RG) transitions low, VCO sou rce and RRC switch references and
VCO lock (internal) goes inactive as with soft sector but
the AMENB (address mark enable) is low.
SOFT SECTOR
In soft sector operation, when Read Gate (RG) transitions low, VCO source and RRC source switch from RO
and VCO/3, respectively, to the reference crystal. At
the same time the VCO (internal) lock goes inactive but
The 551 320536 then sequences from RG disable to
WG enable and WONRZ active as in soft sector operation.
1.7 RLL OATA
VCO
VCO/2 •
DECOOEWINDOW'
PHASEDET
ENABLE •
14---~--*+--'--~+-~~
II
I
------~
NRZBlTCELL
~----------
L
14-~--------I.~~I---------4I.1
NOTE: • Denotes Internal signal
FIGURE 1: Data Synchronization Waveform
3-88
0888
551320536
Data 5ynchronization/1, 7 RLL ENOEC
with Write Precompensation
,,
,
,
X 6 X 6
X XI X X ¥
D1
D2
X X
NRZDATA
D4
D3
PRESENT
Y3
Y1
Y2
Y3
,
Y1
1.7 CODE
I
,
I:
PREVIOUS :
CODEWORD'
LAST BIT :
NEXT
'CODEWORD
: FIRST BIT
1 WORD BIT
FIGURE 2: NRZ Data Word Comparlslon to 1,7 Code Word Bit (See Table 1, for Decode SCheme)
TABLE 1: 1,7 RLL Code Set
PREVIOUS
CODEWORD
LAST BIT
DATA BITS
PRESENT
NEXT
0
0
1
0
0
0
X
1
0
1
1
1
X
0
1
0
0
1
1
0
1
0
1
1
. .
0
0
1
0
0
0
0
0
0
X
0
0
1
0
0
0
0
1
X
0
0
0
0
1
0
X
0
0
1
0
0
1
1
X
0
0
0
1
0
0
0
X
0
1
1
0
0
1
X
0
0
1
0
1
0
1
0
0
0
1
0
0
0
0
03
04
Y1
Y2
Y3
1
0
1
Y3
01
02
.==
X
0
. .
Don't care
Not all zeros
0888
CODE BITS
3-89
551320536
Data 5ynchronization/1, 7 RLL ENOEC
with Write Precompensation
TABLE 2: Clock Frequency
WG
RG
VCOREF
RRC
DECCLK
ENCCLK
0
0
XTAU2
XTAU3
XTAU2
XTAU2
IDLE
0
1
RD
VCO/3
VCO/2
XTAU2
READ
1
0
XTAU2
XTAU3
XTAU2
XTAU2
WRITE
1
1
XTAU2
XTAU3
XTAU2
XTAU2
IDLE
MODE
Note 1: Until the VCO locks to the new source, the VCO/2 entries will
be XTAU2.
2: Until the VCO locks to the new source, the VCO/3 entries will
beXTAU3.
TABLE 3: Write Precompensatlon Algorithm
BIT
BIT
BIT
BIT
BIT
COMPENSATION
n-2
n-1
n
n+1
n+2
BITn
NONE
1
0
1
0
1
0
0
1
0
0
NONE
1
0
1
0
0
EARLY
0
0
1
0
1
LATE
LATE:
Bit n is time shHted (delayed) from its nominal
time position towards the bit n+1 time position.
EARLY: Bit n is time shifted (advanced) from its nominal
time position towards the bit n-1 time position.
TABLE 4: Write Precompensatlon Magnitude
Wei
WC()
MAGNITUDE.WP
0
0
3
0
1
2
1
0
1
1
1
0
The nominal magnitude,
(TPC = WP x 0.053 (Rc) (Cc+Cs), is externally
set with an R-C network on pin WCS.
3-90
0888
551320536
Data 5ynchronization/1, 7 RLL ENDEC
with Write Precompensation
PIN DESCRIPTION
INPUT PINS
NAME
TYPE
DESCRIPTION
RD
I
READ DATA: Encoded Read Data from the disk drive read channel, active
low.
RG
I
READ GATE: Selects the PLL reference input (REF), see Table 1. A change
in state on RG initiates the PLL synchronization sequence.
WG
I
WRITE GATE: Enables the write mode, see Table 2.
WCLK
I
WRITE CLOCK: Write Clock input. Must be synchronous with the NRZ
Write Data input. For small cable delays, WCLK may be connected directly
to pin RRC.
EPD
I
ENABLE PHASE DETECTOR: A low level (Coast Mode) disables the
phase detector. This opens the PLL and the VCO will run at the frequency
commanded by the voltage on pin VCO IN. Pin EPD has an internal resistor
pull up.
AMENB
I
ADDRESS MARK ENABLE: Used to enable the address mark detection
and address mark generation circuitry, active high.
WCD, WC1
I
WRITE PRECOMPENSATION CONTROL BITS: Pins WC1, and WCD
control the magnitude of the write precompensation, see Table 4. Internal
resistor pull ups are provided.
WCL
I
WRITE PRECOMPENSATION CONTROL LATCH: Used to latch the write
precompensation control bits WC1 and WCD into the internal DAC. An
active low level latches the input bits. Pin WCL has an internal resistor pull
up.
WDNRZ
I
NRZ WRITE DATA INPUT PIN: This pin can be connected to the NRZ pin
to form a bidirectional data port.
OUTPUT PINS
NAME
0888
TYPE
DESCRIPTION
WD
0
WRITE DATA: Encoded write data output, active low. The data is
automatically resynchronized (Independent of the delay between RRC and
WCLK) to one edge of the XTAL 1 input clock.
RRC
0
READ/REFERENCE CLOCK: A multiplexed clock source used by the controller, see Table 2. During a mode change, no glitches are generated and
no more than two lost clock pulses will occur. When RG goes high, RRC is
synchronized to the NRZ Read Data after 19 read data pulses.
AMD
0
ADDRESS MARK DETECT: Tristate output pin that is in its high impedance
state when WG is high or AM ENB is low. A latched low level output indicates
that an address mark has been detected. A low level on pin AMENB resets
pinAMD.
3-91
I
SSI320536
Data Synchronization/1, 7 RLL ENOEC
with Write Precompensation
OUTPUT PINS (Continued)
NAME
TYPE
DESCRIPTION
VCO REF
0
VCO REFERENCE: An open emitter ECl output test point. The VCO
reference input to the phase detector, the negative edges are phase locked
to DlYD DATA. The positive edges of this open emitter output signal
indicate the edges of the decode window. Two external resistors are
required to perform this test, they should be removed during normal
operation for reduced power dissipation.
VCOClK
0
VCO CLOCK: An open emitter ECl outputtest point. Two external resistors
are required to perform this test. They should be removed during normal
operation for reduced power dissipation.
ORO
0
DELAYED READ DATA: An open emitter ECl output test point. The
positive edges of this open emitter output signal indicates the data bit
position. The positive edges of the ORO and the VCO REF signals can be
used to estimate window centering. The time jitter of ORO's positive edge
is an indication of media bit shift. Two external resistors are required to
perform this test. They should be removed during normal operation for
reduced power dissipation.
NRZ
0
NRZ READ OATA OUTPUT: Tristate output pin that is enabled when read
gate is high. This pin can be connected to the WDNRZ pin to form a
bidirectional data port.
ANALOG PINS
NAME
TYPE
DESCRIPTION
IREF
I
TIMING PROGRAM PIN: The VCO center frequency and the 1/3 cell delay
are a function of the current sourced into pin IREF.
XTAL1,2
I
CRYSTAL OSCilLATOR CONNECTIONS: The pin frequency is at three
times the data rate. If the crystal oscillator is used, an AC coupled parallel
lC circuit must be connected from XTAl1 to ground. If the crystal oscillator
is not desired, XTAl1 may be driven by a TTL source with XTAl2 open. The
source duty cycle should be close to 50% as possible since its duty cycle will
affect the RRC clock duty cycle when XTAl is its source. The additional
RRC duty cycle error will be one third the source duty cycle error.
PO OUT
0
PHASE DETECTOR OUTPUT: Drives the loop filter input.
VCOIN
I
VCO CONTROL INPUT: Driven by the loop filter output.
WCS
I
WRITE PRECOMPENSATION SET: Pin for RC network to program write
precompensation magnitude value.
DGND,AGND
I
Digital and Analog Ground
VPA1, VPA2
I
Analog +5V Supplies
VPD
I
Digital +5V Supply
3-92
0888
SSI32D536
Data Synchronization/1, 7 RLL ENDEC
with Write Precompensation
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Operation above maximum ratings may damage the device.
PARAMETER
Storage Temperature
Junction Operating Temperature, Tj
UNIT
-65 to + 150
°C
+150
°C
-0.5 to 7
V
-0.5 to VPD + 0.5
V
1.1
W
RATING
UNIT
4.75 < VCC < 5.25
V
0< Tj < 135
°C
Supply Voltage, VPA 1, VPA2, VPD
Voltage Applied to Logic Inputs
RATING
Maximum Power Dissipation
I
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage, VPA1 = VPA2 = VPD = VCC
Junction Temperature, Tj
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, 4.75V< VCC <5.25V, 10 MHz< 1fTORC <15 MHz, 30 MHz< 1/TVCO <45 MHz,
o °C< Tj <135 °C.
PARAMETER
0888
VIH
High Level Input
Voltage
VIL
Low Level Input
Voltage
IIH
High Level Input
Current
ilL
CONDITIONS
MIN
NOM
MAX
UNIT
V
2.0
0.8
V
VIH = 2.7V
2.0
~
Low Level Input
Current
VIL = O.4V
-1.5
mA
VOH
High Level Output
Voltage
IOH =400~
VOL
Low Level Output
Voltage
IOL=4mA
0.5
V
ICC
Power Supply Current
All outputs open,
Tj = 135°C
240
mA
PWR
Power Dissipation
Tj = 135°C, test point
pins open
1.1
W
3-93
2.7
V
551320536
Data 5ynchronization/1, 7 RLL ENOEC
with Write Precompensation
ELECTRICAL CHARACTERISTICS (Continued)
CONDITIONS
MIN
VOHT
Test Point
Output High Level
ORO, VCO ClK,
VCOREF
2620 to VPD
4020toGND
VPD=5.0V
VOHT-VPD
-1.02
VOLT
Test Point
Output low level
ORO, VCO ClK,
VCOREF
2620 to VPD
4020 to GND
VPD=5.0V
VOlT- VPD
PARAMETER
NOM
MAX
UNIT
V
-1.625
V
MAX
UNIT
TORC-20
ns
DYNAMIC CHARACTERISTICS AND TIMING
READ MODE (See Figure 3)
PARAMETER
TRD
MIN
CONDITIONS
NOM
15
Read Data Pulse Width
TFRD
Read Data Fall Time
2.0V to 0.8V, C1
~
15 pF
15
ns
TRRC
Read Clock Rise Time
0.8V to 2.0V, C1
~
15 pF
8
ns
2.0Vto O.8V, C1
~
15 pF
5
ns
TFRC
Read Clock Fall Time
TPNRZ
NRZ (out) Set Up/Hold
Time
TPAMD
AMD Propogation
Delay
1/3 Cell Delay
TO = 5.05E -12 (RR+530)
.31
TORC
ns
10
ns
0.8TO
1.2TD
ns
WRITE MODE (See Figure 4)
PARAMETER
CONDITIONS
MIN
MAX
UNIT
TWD
C1
~15pF
2TOWC13
2TOWC/3
ns
-2TPC -5
-2TPC +15
Write Data Pulse Width
~
NOM
TFWD
Write Data Fall Time
2.0V to 0.8V, C1
8
ns
TRWC
Write Data Clock
Rise Time
0.8Vto 2.0V
10
ns
TFWC
Write Data Clock
Fall Time
2.0Vto 0.8V
8
ns
TSNRZ
WDNRZ Set up TIme
5
ns
THNRZ
WDNRZ Hold Time
5
ns
15 pF
3-94
0888
SSI320536
Data Synchronization/1, 7 RLL ENOEC
with Write Precompensation
WRITE MODE
(Continued)
PARAMETER
CONDITIONS
TPC
TPCO=.053 (Cc+Cs) (Rc)
Rc=1K to 2K
Cs=stray capacity
WCO = 1 WC1 = 1
Precompensation
Time Shift
Magnitude
Accuracy
MIN
MAX
UNIT
0
0
ns
WCO = 0 WC1 = 1
0.8TPCO-0.2
1.2TPCO+O.2
ns
WCO = 1 WC1 =0
0.8(2)TPCO
1.2(2)TPCO
ns
WCO =OWC1 =0
0.8(3)TPCO
1.2(3)TPCO
ns
DATA SYNCHRONIZATION
PARAMETER
CONDITIONS
MIN
MAX
UNIT
TYCO
VCO Center
Frequency Period
VCO IN = 2.7V
TO = 3.6E-12 (RR+2300)
VCC= 5.0V
RR = 3.5K to 5.7K
O.STO
1.2TO
ns
VCO Frequency
Dynamic Range
1V::;; VCO IN::;; VCC-0.6V
VCC =5.0
±25
±45
%
KVCO
VCO Control Gain
0>0 = 27tlTO
1V ::;; VCO IN ::;; VCC 0.6V
0.140>0
0.260>0
rad/
sec V
KD
Phase Detector
Gain
KD = 0.19/(RR+530)
VCC = 5.0V, PLL REF = RD
3T ("100") pattern
0.83KD
1.17KD
Alrad
-28
-28
%
-1
1
rad
±2
ns
KVCO • KD Product
Accuracy
VCO Phase
Restart Error
Referred to RRC
Decode Window
Centering Accuracy
Decode Window
ns
(2TORC/3) - 2
CONTROL CHARACTERISTICS (See Figure 5)
PARAMETER
0888
CONDITIONS
MIN
NOM
MAX
UNIT
TSWS
WCO WC1
SET UPTIME
50
ns
THWS
WCO, WC1
HOLD TIME
0
ns
3-95
I
SSI32D536
Data Synchronization/1, 7 RLL ENDEC
with Write Precompensation
1.SV
RRC
-+-..J
NRZ(OUT) _ _ _ _ _ _
~-------+-~
FIGURE 3: Read Timing
~
TOIIO--~
1PWC
t.BY
~----------~
FIGURE 4: Write Timing
1.5V .....
f\..
/'-
"----I--"
~TSWS---+
---+
4-- THWS
~".5V
'--------FIGURE 5: Control Timing
3-96
0888
;
..
lJ .:
u '~u
u
,,~
o
,,~
~
r-' ENCODED DATA
~r!',,~_T_IM_E_MAX
__DE_LA_Y_ _ _ _ _ _ _ _ _ __
AMENB
'ZERO'
T::~:
lIIm
~r--TR-~-ATE--------------
TRISTATE ><--
B~ABLE
6"0-
9"0-
DETECT
DETECT
CASE'
~ "O"&9"O~
DETECT'"
PATTERN
c
aS»
en
(,)
cO
'"
TRISTATE ><--
8"0-
B~ABLE
9"0"
TR~ATE
DETECT
DETECT
CASE 2
'<
:::J
8"0-
9"0"
CASE 3
DETECT
DETECT
~g.
_ . ""'I
H5 bill ofRD are _
-0
after8 "0" _found and bo_ 9"0- lhon .....~ and look for 6 "0."
lID
:::r:::J
:e_.-N'
- -.
EXAMPLE
""'IS»
CD 0
6'0'
Found
,
CT
CT
2
CT
3
CT
4
"'C~
.....
CT
5
""'I
CD"
~RESTART
n .....
o
3::Den
FIGURE 6: Address Mark Search
en
"C 1
(\)1_
:::Jmw
tnzl\)
ace
_. m (II
-
°ow
:::J
0')
,.
~~
I
~
..,.*----'
n'--__
31(.31"
z~
+++
ZERO_ *
n
AESl"ART
~.
vr--
A
----_~_~~I
~I
___
"""""""'---=-x-f!.4
n-..._~-x-~--x X~, ..._,~ x----------x ~ ~ x-xxx
-1P~r-1P~DSr-1~rtv
(,)
tb
IX)
*-------
IX XX
"HZ
1I/TSN~ACH
,--
DISABLE
Me.
\/coCLK··
REF esc
SOURCE
**
PHASE DETSOUACE:::
-- -----
--------'L__________
I~~~ -----------------:~-------------------------------------1.
..
* __
I
~IISCUCO
--TllltPont
FIGURE 7: Read Mode Locking Sequence (Soft and Hard Sector)
:seen
::;:Q)en
::r-Q)w
:eenN
... '< e
---.,UI
CDnw
,,=fe»
"'0
CD :::s
n
__
ON
3!.
"C --
CD O
:::s~
0
.....
Q)'"
=. .....
0::rJ
:::Sr-
rm
z
e
m
o
g
~
~~
~...
,__
r+-hN~~l'~-----
WG
(INTERNAL)'
"
,
- ---
TlMINGBElWEENAMENB&STARTOFWDNRZTlMING
MUST MEET TIME REOUIREMENTS OF WRITE DATA.
AMENB
W
I
CO
CO
W!lI:1
L
L
' - - - - -
vvv
VV
VVV--
-- ----
h h m m __
o
nL---_
VVV
-en
m
m
'<
VV
:::s
~g.
_.
r-
1__
L
mhh
-
WDNRZ
- I _
AM
ENe DATA
I
AM
I
ENe DATA
AM
I -
ENe DATA
-
r
AM
____--'-_ _
ENe DATA
~
-0
:::J":::s
:e_.-N'm
~
_.
CD 0
"t'I~
~
.....
FIGURE 8: Multiple Address Mark WrHe
CD
o .....
:Den
3 ren
"C r_
CD
n
:::smCa)
cnZN
moo
...
=mO'l
°OCa)
:::s
en
M
WG
WG
(INTERNAL)
H
~
'=~
--"NR2~
MIN
L
~VNR2
~
AMENS
'NRZMIN
~=~
-'-
-o:;rm
... 0
CD :::s
(")
_.
~
o
'1
-------~--_':_'~~~~----------------------------------------------~---------------------------------MAX OF 3 X 3T (1 ,7) DE'tJ 11~::~tAS~~~
5 NRZ PAD TO
FWSH ENCODER
II'lIRl
m
U)
I
......
~
VCOLOCK
(INTERNAll
14
ADDRESS MARK
~4
~ ENCODED DATA
PREAMBLE
('9x 3T PATTERN)
1 •
---"l
IL_V_CO_UX_~_&rr_V_CO_UX_K_S_~_~_WlL
__S_TA_Y_'__
NAC~~
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
~E
"RIS-*-~
~CE ~-*-~
R~ XXXI
Kl
U.
MAX 2
~ME PERIOOS
OF~
FIGURE 9: WrHe Data
I
°
e»
=
...
0:D
CD
:::s~
tn .....
:::Sr
r
WDNRZ
o
o
N
3!.
"C
_.
J
MIN OF(!'&~A=~ENDED
MAX
__
...
'< 01
C
CD(")W
I
_____. . r.~
::CCJ)
::;:e»CJ)
:::J'-e»W
=ECJ)I\)
z
C
m
o
SSI320536
Data Synchronization/1, 7 RLL ENOEC
with Write Precompensation
PACKAGE PIN DESIGNATIONS
CAUTION: Use handling procedures necessary
far a sialic sensitive ccmponent.
(TOP VIEW)
IIGND
'EPD"
OJ
z
IREF
VCOIN
PO OUT
VPAI
'DIm
VCOClK
VCOREF
RG
5
WClJ(
8
WDNRZ
7
wet
8
VPO
WCf
•
XTAL2
WCIf
10
XTALI
wcs
11
DGND
RRC
"iI:
W
:l! >~ Jf
0
Z
~
~
!!
4
3
2
1
28
~
28
12
13
14
15
1.
17
18
~
II!
z
i
~
a:
0
~ ~
IL
w
I.
28-Pln DIP
z
8
YPD
28-Pln PLCC
ORDERING INFORMATION
PART DESCRIPTION
J
ORDERING NUMBER
I
PACKAGE MARK
I
881 320536-CP
881320536
28-Pin DIP
28-Pin PLCC
I
I
881 320536-CP
581 320536-CH
I
851 320536-CH
No responsibility is assumed by SSi for use of this product nor for any infringements of patents and trademarks or other rights of third parties
resulting from its use. No Hcense is granlBd under any patents, patent rights or trademarks of SSi. SSi reserves the right to make changes
in specifications at any time without notice.
Silicon Systems, Inc., 14351 Myford Road, Tustin,
CA 92680 (714) 731-7110, TWX 910-595-2809
Cl988 Silicon Systems, Inc.
0888
3-101
NOTES:
551 32H101A
Differential Amplifier
INNOVATORS IN INTEGRATION
----------------------------------------------August, 1988
DESCRIPTION
FEATURES
The SSI32H101A is a two stage differential amplifier
applicable for use as a preamplifier for the magnetic
servo head circuit of Winchester technology disk
drives.
•
Very narrow gain range
•
30 MHz bandwidth
•
Electrically characterized at two power supply
voHages: IBM Model 3340 compatible (8.3V)
and standard OEM Industry compatible (10V)
•
Mechanically compatible with Model 3348 type
head arm assembly
•
SSI32H1012A available to operate with a 12V
power supply
•
Packages Include S-pln DIP or SON
CONNECTION DIAGRAM
RECOMMENDED LOAD CONDITIONS
1. Input must be AC coupled
Vee
ee
REO
~--~~--~~r-~~
ee
REO-=
~---2~~------~--~~
4
2.
Cc's are AC coupling capacitors
3.
RL'S are DC bias and termination resistors (recommended 130Q)
4.
REQ represents equivalent load resistance
5.
For gain calculations Rp= RL" RID
RL+RID
6.
Differential gain = 0.72 Rp (± 18%) (Rp in Q)
7.
Ceramic capacitors (0.1 ~F) are recommended for
good power supply noise filtering
CAUTION: Use handling procedures necessary
for a static sensitive component.
0888
4-1
SSI32H101A
Differential Amplifier
ELECTRICAL CHARACTERISTICS
TA = 25°C, (Vee-VEE) = 8.3 to 10V ±10% (12V ±10% for 101A-2)
ABSOLUTE MAXIMUM RATINGS
Operation above absolute maximum ratings may permanently damage the device.
PARAMETER
Power Supply Voltage (Vee - VEE)
SSI32H1012A
Differential Input Voltage
Storage Temperature Range
Operating Temperature Range
RATING
UNIT
12
V
14
V
±1
V
-65 to 150
°C
Oto 70
°C
DC ELECTRICAL CHARACTERISTICS
PARAMETER
CONDITIONS
MIN
NOM
MAX
110
Gain (differential)
Rp= 130Cl
77
93
Bandwidth (3dB)
Vi.2 mVpp
10
20
Input Resistance
750
Input Capacitance
MHz
1200
3
Input Dynamic Range (Differential)
RL = 130n
Power Supply Current
(Vee - VEE) - 9.15V
UNITS
n
pF
mVpp
3
26
35
mA
(Vee - VEE) = 11V
30
40
mA
(Vee - VEE) = 13.2V (32H101A-2)
35
45
mA
600
mV
14
~V
Output Offset ( Differential)
Rs = 0, RL = 130n
Equivalent Input Noise
Rs = 0, RL = 130n, BW = 4 MHz
PSRR, Input Referred
Rs = 0, f s 5 MHz
Gain Sensitivity (Supply)
A (Vee - VEE) = ±1 0%, RL = 130n
±1.3
%
Gain Sensitivity (Temp.)
TA - 25·C to 70 ·C, RL - 130Cl
-0.2
%/OC
CMRR, Input Referred
f s 5 MHz
55
70
dB
MIN
NOM
MAX
UNITS
7.45
8.3
9.15
V
9.0
10.0
11.0
V
10.8
12.0
13.2
8
50
dB
65
RECOMMENDED OPERATING CONDITIONS
PARAMETER
CONDITIONS
Supply Voltage (Vee - VEE)
32H1012Aonly
Input Signal Vi
Ambient Temp. TA
0
4-2
V
mVpp
2
70
C
0888
SSI32H101A
Differential Amplifier
PACKAGE PIN DESIGNATIONS
(TOP VIEW)
INPUT 1 (+)
1
INPUT 2 (-)
2
SEE NOTE
OUTPUT 2 (-)
'-------1 5
OUTPUT 1 (+)
a-Pin PDIP, SON
Note: Pin must be left open and not connected to
any circuit etch.
ORDERING INFORMATION
PART DESCRIPTION
l
ORDERING NUMBER
J
I
SSI32H101A-SP
I
PACKAGE MARK
SSI32H101A Differential Amplifier
S-Pin PDIP
S-Pin SON
32H101A-CP
l
SSI32H101A-SN
I
32H101A-SN
I
I
SS132H1012A-SP
I
I
32H1012A-SP
SSI 32H1 012A Differential Amplifier
S-Pin PDIP
S-Pin SON
SS132H1012A-SN
32H1012A-SN
No responsibility is assumed by SSi for use ofthis product nor for any infringements of patents and trademarks or other rights of third parties
resulting from its use. No license is granted under any patents, patent rights or trademarks of SSi. SSi reserves the right to make changes
in specifications at any time without notice.
Silicon Systems, Inc., 14351 Myford Road, Tustin,
0888
CA 92680 (714) 731-7110, TWX 910-595-2809
©1988 Silicon Systems, Inc.
4-3
NOTES:
SSI32H116
Differential Amplifier
INNOVATORS IN INTEGRATION
------------------------------------------------------August, 1988
DESCRIPTION
FEATURES
The SSI 32H116 is a high performance differential
amplifier applicable for use as a preamplifier for the
magnetic servo thin film head in Winchester disk
drives.
•
Narrow gain range
•
50 MHz bandwidth
•
IBM 3370/3380-compatlble performance
•
Operates on either IBM-compatible voltages
(8.3V) or OEM-compatible (10V)
•
Packages include 8-pln CERDIP, Plastic DIP or
SON and custom 10-pin flatpack
•
SSI 32H1162 available to operate with a 12V
power supply
CONNECTION DIAGRAM
RECOMMENDED LOAD CONDITIONS
Vee
1.
Input must be AC coupled
ee
REQ
2.
Cc's are AC coupling capacitors
3.
RL's are DC bias and termination resistors, 100n
recommended
4.
REO. represents equivalent load resistance
r-----~~----~~~--~~
REO
-=
' - - - - - - - - I A"ff------------4-----I~
5. Ceramic capacitors (0.1 IlF) are recommended for
good power supply noise filtering
CAUTION: Use handling procedures necessary
for a static sensitive component.
0888
4-5
I
SSI32H116
Differential Amplifier
ELECTRICAL CHARACTERISTICS
Tj = 15 °C to 125 °C, (Vee-VEE) = 7.9V to 10.5V (to 13.2V for 32H1162)
ABSOLUTE MAXIMUM RATINGS
RATING
UNIT
Power Supply Voltage (VCC-VEE)
12
V
SSI32H1162
14
V
Operating Power Supply Range
7.9 to 10.5
V
SSI32H1162
7.9 to 13.2
V
±1
V
-65 to 150
°C
15 to 60
°C
15 to 125
°C
VCC -2.0 to VCC +0.4
V
PARAMETER
Differential Input Voltage
Storage Temperature Range
Operating Ambient Temperature (TA)
Operating Junction Temperature (TJ)
Output Voltage
DC ELECTRICAL CHARACTERISTICS
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNIT
Gain (Differential)
Yin = 1mVpp,
TA = 25 °C, F = 1 MHz
200
250
310
mV/mV
Bandwidth (3dB)
Yin = 1mVpp, CL = 15 pF
20
50
Gain Sensitivity (Supply)
MHz
1.0
-0.16
%/V
Gain Sensitivity (Temp.)
15 °C < TA < 55 °C
Input Noise Voltage
Input Referred, Rs = 0
0.7
0.94
nVlfHz
Input Capacitance (Differential)
Yin = O,f = 5 MHz
40
60
pF
200
n
60
70
dB
46
52
Input Resistance (Differential)
Common Mode
Rejection Ratio Input Referred
Yin = 100 mVpp, f = 1 MHz
Input Signal Level
Common Mode
Power Supply
Rejection Ratio Input Referred
Vee + 100 mVpp, f -1 MHz
Input Dynamic
Range (Differential)
DC input voltage where AC
gain is 90% of gain with
0.2 mVpp input signal
Output Offset
Voltage (Differential)
Vin=O
Output Voltage (Common Mode)
Inputs shorted together and
Outputs shorted together
%/C
300
-600
Single Ended Output Resistance
Vcc-O.45
10
4-6
Vcc-O.6
mVpp
dB
±0.75
mV
600
mV
Vcc-1.0
V
n
OBBB
SSI32H116
Differential Amplifier
DC ELECTRICAL CHARACTERISTICS
PARAMETER
(Continued)
CONDITIONS
MIN
NOM
Single Ended Output Capacitance
Power Supply Current
28
Vee-VEE = 9.15V
MAX
UNIT
10
pF
40
rnA
Vee-VEE = 11V
29
42
Vee-VEE = 13.2V, 32H1162 only
39
50
Input DC Voltage
Common Mode
VEE +2.6
V
Input Resistance
Common Mode
80
Q
RECOMMENDED OPERATING CONDITIONS
PARAMETER
CONDITIONS
Supply Voltage (Vee-VEE)
SSI 32H1162 only
MIN
NOM
MAX
UNIT
7.45
8.3
9.15
V
9.0
10.0
11.0
V
10.8
12.0
13.2
V
Input Signal Vin
1
Ambient Temp TA
0888
15
4-7
mVpp
65
°C
I
SSI32H116
Differential Amplifier
PACKAGE PIN DESIGNATIONS
(TOP VIEW)
N/C
10
N/C
INPUT 1 (+)
2
9
SEE NOTE
INPUT 2 (-)
3
8
VCC
SEE NOTE 1
4
7
OUTPUT2(-)
VEE
5
6
OUTPUT 1 (+)
INPUT 1 (+)
1
B
SEE NOTE
SEE NOTE 1
3
6
OUTPUT 2 (-)
5
OUTPUT 1 (+)
B-Pln PDIP, SON
1a·Pln Flatpack
NOTE : Pin must be left open and not connected to any circuit etch.
ORDERING INFORMATION
PART DESCRIPTION
ORDERING NUMBER
PACKAGE MARK
551 32H116 Differential Amplifier
10-Pin Flatpack
551 32H116-CF
32H116-CF
8-Pin 50N
551 32H116-CN
32H116-CN
8-Pin PDIP
551 32H116-CP
32H116-CP
551 32H1162
10-Pin Flatpack
551 32H1162-CF
32H1162-CF
8-Pin50N
551 32H1162-CN
32H1162-CN
8-Pin PDIP
551 32H1162-CP
32H1162-CP
No responsibility is assumed by SSi for use of this product nor for any infringements of patents and trademarks or other rights of third parties
resulting from its use. No license is granted under any patents, patent rights or trademarks of SSi. SSi reserves the right to make changes
in specifications at any time without notice.
JifuonJz rJfemJ~
Silicon Systems, Inc., 14351 Myford Road, Tustin,
©1988 SRicon Systems, Inc.
CA 92680 (714) 731-7110, TWX 910-595-2809
0888
SSI32H523R
Jifuon Jl rsfonf
INNOVATORSIN
I~N~T~EG~R~A~T~IO~N
Thin Film Single Channel
Servo Read/Write Device
__________________________
August, 1988
DESCRIPTION
FEATURES
The SSI 32H523R Read/Write device is a bipolar
monolithic integrated circuit designed for use with a
two terminal thin film recording head. It provides a low
noise read amplifier and write current control. In its
servo application, the device will be used in write mode
once then switched permanently to read mode. Data
protection is provided in both write and read modes to
guarantee servo data security. Power supply fault
protection is effective in both write and read modes
while head short circuit protection is provided in write
mode. Further data security can be provided in read
mode by removing the write current source voltage. It
requires +5V and +12V power supplies and is available
in a 14-pin SON surface mount package. Internal
1ooon damping resistors are provided.
•
High performance:
Read mode gain = 250 V/V
Input noise = 1.0 nV/~ max.
Input capacitance = 45 pF max.
Write current range = 10 mA to 40 mA
Head voltage swing = 3.4 Vpp min.
Write current rise time = 13 nsec
• Highest level of data security provided
•
Power supply fault protection
•
Head to ground short circuit protection
• +5V. + 12V power supplies
BLOCK DIAGRAM
VDD
R/W
VCC1
GND
PIN DIAGRAM
VCC2
MODE
SELECT
ROX
RDX
HDX
ROY
HDY
WOM
VOO
ROY
2
13
HOX
RJW
3
12
HOY
GNO
4
11
NC
WOM
5
10
WC
wrn
6
9
WOI
7
WOI
WDI
VCC2
VCCl
14·PIN SON
CAUTION:
WC
0888
14
4-9
Use handling procedures necessary
for a static sensitive component.
I
SSI32H523R
Thin Film Single Channel
Servo Read/Write Device
CIRCUIT OPERATION
The SSI 32H523R provides write drive or read
amplification. Mode control is accomplished with pins
WDM, Write Data Mode, and RIW, as shown in Table
1. An internal resistor pullup on RIW will force the
device into a non-writing condition if the line is opened
aCCidentally.
Power supply fault protection improves data security
by disabling the write current generator during a
voltage fault or power supply sequencing. In addition
a head to ground short circuit protection circuit will shut
off the write driver and current to prevent excessive
current and power dissipation. Triggering of this
feature occurs when the DC voltage at either HDX or
HDY is less than 2.0V ± 15% in write mode
WRITE MODE
READ MODE
The write mode configures the SSI 32H523R as a
differential current switch. The WDM pin state
determines whether write current transitions are
controlled by a single-ended TTL input, WDI, or by
differential (ECl-like) inputs, WDI and WDI. With
WDM open, write current is toggled between the X and
Y direction ofthe head on each high to low transition on
pin WDI, Write Data Input. A preceding read operation
initializes the Write Data Flip-Flop (WDFF) to pass
write current in the X-direction of the head.
The read mode configures the SSI32H523R as a low
noise differential amplifier and deactivates the write
current generator. The RDX and RDY outputs are
open collectors and are in phase with the "X" and "Y"
head ports.
With WDM grounded the head current direction is
controlled by differential inputs WDI, WDI. For (WDIWDI) > 200mV the current is in the X-direction.
For maximum data security in read mode VCC2 is left
open or grounded. This eliminates the voltage source
for write current.
In read mode, the write data channel is powered down
to reduce power consumption. Note that inwrite mode,
the read amplifier is deactivated and will not pull any
current from the load resistor.
The magnitude of the write current (O-pk) given by:
Iw= Vwc
Rwc
TABLE 1: MODE SELECT
where Vwc (WC pin voltage) = 1.65V ± 5%, is
programmed by an external resistor Rwc, connected
~ro~ pin WC to ground. The actual head current lx, y
IS given by:
lx, y=
Iw
1 + Rh/Rd
WDM
R/W
MODE
GND
0
Write
DHferential input
OPEN
0
Write
Single-ended input
X
1
Read
where:
Rh = head resistance + external wire resistance, and
Rd = damping resistance.
4-10
0888
SSI32H523R
Thin Film Single Channel
Servo Read/Write Device
PIN DESCRIPTIONS
NAME
TYPE
DESCRIPTION
RIW
I
Read/Write: a high level selects Read mode
WDI,WDI
I
Write Data In: toggles the direction of the head current
HDX, HDY
1/0
X, Y Head Connections: current in the X-direction flows into the X-port
RDX,RDY
0
X, Y Read Data: differential read data output
WC
-
Write Current: used to set the magnitude of the write current
WDM
I
Write Data Mode: Ground this pin for direct differential input using both
WDI and WDI, leave open to select TTL input using WDI and the internal
Write Data Flip-Flop.
VCC1
+5V logic circuit supply
+ 12V supply for read
VCC2
-
GND
-
Ground
VDD
Note:
+5V power supply for write current drivers (see note)
To ensure maximum data integrity in write-once servo applications, this pin should be left open or
shorted to ground after writing servo information.
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Operation above absolute maximum ratings may permanently damage the device.
PARAMETER
SYMBOL
VALUE
UNITS
VDD
-0.3 to +14
VDC
VCC1,2
-0.3 to +7
VDC
Write Current
Iw
60
mA
Digital Input Voltage
Yin
-0.3 to VCC1 +0.3
VDC
Head Port Voltage
VH
-0.3 to VCC2 +0.3
VDC
10
-10
mA
Tstg
-65 to +150
°C
215
°C
DC Supply Voltage
RDX, RDY Output Current
Storage Temperature
Package Temperature (20 sec Reflow)
0888
4-11
I
SSI32H523R
Thin Film Single Channel
Servo Read/Write Device
RECOMMENDED OPERATING CONDITIONS
PARAMETER
DC Supply Voltage
SYMBOL
VALUE
UNITS
VDD
12+ 10%
VDC
VCC1
5±10%
VDC
Read Mode
VDD
12±5%
VDC
VCC1
5±5%
VDC
VCC2
5±5%
VDC
RL
100
Q
Write Mode
Output Pullup Resistors (to VCC1)
Ambient Temperature
Read Mode
TAR
0-70
°C
Write Mode
TAW
20 - 43
°C
Tj
oto +135
°C
Operating Junction Temperature
DC CHARACTERISTICS (Unless otherwise specified, recommended operating conditions apply.)
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNITS
26
mA
10
rnA
35
mA
Input Low Voltage (VIL)
Includes WOI wIWOM = open
-
VDD Fault Voltage
8.5
VCC1 Fault Voltage
3.5
-
Input High Voltage (VI H)
Includes WOI wIWOM = open
2.0
0~VDD~8.5V
-200
Write Mode
VCC2 = open or ground
-200
Read Mode
o~ VCC1 ~ 5.5V
o~ VDD ~ 13.2V
-200
VDD Supply Current
Read Mode
Write Mode
VCC1 Supply Current
Read Mode
Write Mode
VCC2 Supply Current
Read Mode, see Note 1
Write Mode
Power Dissipation (Tj = + 135°C)
Read Mode, VCC2 = 0
Write Mode: Iw = 40mA
Input Low Current (ilL)
VIL = 0.8v
-0.4
Input High Current (IHL)
VIH = 2.0v
-
Input Voltage (WDI, WDI)
WDM=GND
Differential Input Voltage (WDI, WDI)
WDM=GND
Head Current
(HDX, HDY)
Write Mode
3.0
200
o~ VCC1 ~ 3.5V
36
mA
2
mA
12+lw
mA
500
mW
500
mW
0.8
VDC
-
VDC
mA
100
!lA
VCC1
VDC
-
mVDC
10.0
VDC
4.1
VDC
-
+200
!lA
-
+200
!lA
!lA
+200
Note 1: If VCC2 is at ground or open this current is zero.
4-12
0888
SSI32H523R
Thin Film Single Channel
Servo Read/Write Device
WRITE CHARACTERISTICS
Unless otherwise specified, recommended operating conditions apply, Iw = 15mA, Lh = 1.51lH, Rh = 300
f(DATA) = 5MHz, and +20°C < Tj < + 135°C
MIN.
NOM
MAX
UNITS
-
1.65±5%
V
Differential Head Voltage Swing
3.4
-
-
Vpp
Differential Output Capacitance
-
-
25
pF
800
1000
1400
0
10
-
40
rnA
PARAMETER
CONDITIONS
WC Pin Voltage (Vwc)
Differential Output Resistance
Write Current Range
READ CHARACTERISTICS
Unless otherwise specified, recommended operating conditions apply, CL (RDX, RDY) < 20pF
PARAMETER
CONDITIONS
MIN
Differential Voltage Gain
Vin=1mVpp@1MHz, TA = 25°C
200
250
300
VN
Gain Sensitivity
15°C < TA < 55°C
-
-0.16
-
%rC
Bandwidth
-1dB
IZsl<50, Yin = 1 mVpp @ 300kHz
10
20
-3dB
IZsl<50, Yin = 1mVpp @ 300kHz
20
45
UNITS
MHz
MHz
0.7
1.0
nV/...JHz
45
pF
Input Noise Voltage
BW=15MHz, Lh=O IlH, R =00
-
Differential Input Capacitance
Yin = 1mVpp, f = 5MHz
-
40
Differential Input Resistance
Yin = 1mVpp, f = 5MHz
460
750
1.4K
0
Dynamic Range
AC input voltage where gain falls
to 90% of its small signal gain
value, f=5MHz
±2
-
-
mV
Common Mode Rejection Ratio
Yin = OVDC+100mVpp@ 5MHz
54
-
dB
Power Supply Rejection Ratio
100m Vpp@ 5MHz on VDD,
100m Vpp@ 5MHz on VCC1
54
-
-
dB
Output Offset Voltage
Yin = OV
+600
mV
Output Voltage (Common Mode)
Inputs shorted together, and
outputs shorted together
..
-600
·VCC1 - 0.42
··VCC1 - 1.0
0888
NOM MAX
4-13
~
-
.
VDC
SSI32H523R
Thin Film Single Channel
Servo Read/Write Device
SWITCHING CHARACTERISTICS (See Figure 1)
Unless otherwise specified, recommended operating conditions apply, Iw = 15mA, Lh = 0, Rh = 0,
f(DATA) = 5MHz, and +20°C < TA < +43°C
PARAMETER
CONDITIONS
MIN
MAX
UNITS
-
0.6
lls
0.6
llS
-
32
ns
1
ns
-
13
ns
R/W
R/W to Write Mode
Delay to 90% of write current
R/W to Read Mode
Delay to 90% of 100mV 10MHz
Read signal envelope or to 90%
decay of write current
Head Current
Prop. Delay - TD1
From 50 % points, Lh=Ollh, Rh=On
Asymmetry
Input has 50 % duty cycle and
1ns riselfall time, Lh=Ollh, Rh=On
Rise/Fall Time
10% - 90% pOints, Lh=Ollh, Rh=On
WDI
(WDM = Open)
HEAD
CURRENT
(Ix-Iy)
WDI
(WDM= GND)
FIGURE 1: WRITE MODE TIMING DIAGRAM
4-14
0888
SSI32H523R
Thin Film Single Channel
Servo ReadlWrite Device
JUMPER DURING
WRI]MOOE
+12V
.sV
VCC1
ROX
VOO
ROY
HDX
HOX
ROX
~
RJW
HOY
HOY
ROY
~
GNO
NC
WOI
WOM
WC
WOM
WN
VCC2
WOI
VCC1
SERVO HEAD
SSI32H523R
RiW
GNO
lEAVE OPEN AFTER
WRITING SERVO
FIGURE 3: PACKAGE PIN DESIGNATIONS
(TOP VIEW)
14·PIN SON
FIGURE 2: TYPICAL APPLICATION
ORDERING INFORMATION
PART DESCRIPTON
SSI32H523R ReadlWrite IC
ORDER NO.
PKG.MARK
SSI 32H523R-N
32H523R-N
No responsibility is assumed by SSi for use of this product nor for any infringements of patents and trademarks or other rights of third parties
resulting from its use. No license is granted under any patents, patent rights or trademarks of SSi. SSi reserves the right to make changes
in specifications at any time without notice.
Silicon Systems, Inc., 14351 Myford Road, Tustin,
CA 92680 (714) 731-7110, TWX 910-595-2809
©1988 Silicon Systems, Inc.
0888
4-15
NOTES:
SSI32H566R
Ferrite Single-Channel
Servo ReadlWrite Device
INNOVATORS IN
I~N~T=EG~R~A~T~IO~N~
_____________________
August, 1988
DESCRIPTION
FEATURES
The SSI 32H566R Read/Write device is a bipolar
monolithic integrated circuit designed for use with
center-tapped ferrite recording heads. It provides a low
noise read amplifier, write current control and data
The
protection circuitry for a single channel.
SSI 32H566R provides internal 750Q damping resistors. Power supply fault protection is provided by
disabling the write current generator during power
sequencing. System write to read recovery time is
significantly improved by controlling the read channel
common mode output voltage shift in the write mode.
•
High performance:
- Read mode gain = 150 VN
- Input noise = 1.5nV/--JHz max.
- Input capacitance = 20 pF max.
- Write current range = 10 mA to 40 mA
•
Enhanced system write to read recovery time
•
Power supply fault protection
•
Designed for center-tapped ferrite heads
•
Programmable write current source
•
TIL compatible control signals
•
+5V, +12V power supplies
•
Socket compatible with the SSI 32H523R
BLOCK DIAGRAM
VDDl VCC
GND
PIN DIAGRAM
VDD2 VCT
CENTER
TAP
DRIVER
RiW
MODE
SELECT
ROX
HDX
ROY
HOY
sQ
T
WOI
VOLTAGE
FAULT
DETECTOR
tl'
14
VOO
ROY
2
13
HOX
RNJ
3
12
HOY
GNO
4
11
VCT
N/C
5
10
WC
N/C
6
9
VOO2
WOI
7
8
VCC1
WRITE
CURRENT
SOURCE
CAUTION:
we
0888
ROX
4-17
Use handling procedures necessary for
a static sensitive component.
SSI32H566R
Ferrite Single-Channel
Servo Read/Write Device
To reduce internal power dissipation, an optional external resistor, RCT, given by RCT ~ 1300 x 40/lw (Iw in
mAl, is connected between pins VDD1 and VDD2.
Otherwise connect pin VDD1 to VDD2.
CIRCUIT OPERATION
The SSI 32H566R provides center-tapped ferrite head
write drive or read amplification. Mode control is accomplished with pin R/W. Internal resistor pullups,
provided on pin R/W, will force the device into a nonwriting condition if a control line is opened accidentally.
To initialize the Write Data Flip Flop (WDFF) to pass
currentthrough the X-side ofthe head, pin WDI must be
low when the previous read mode was commanded.
WRITE MODE
READ MODE
The write mode configures the SSI 32H566R as a
current switch. Write current is toggled between the X
and Y side of the selected head on each high to low
transition of the Write Data Input (WDI).
The read mode configures the SSI 32H566R as a low
noise differential amplifier and deactivates the write
current generator. The RDX and RDY outputs are
emitter followers and are in phase with the "X" and "Y"
head ports. These outputs should be AC coupled to the
load. The RDX, RDY common mode voltage is maintained in the write mode, minimizing the transient
between write mode and read mode, substantially
reducing the write to read recovery time in the subsequent pulse detection circuitry.
The magnitude of the write current (O-pk) is programmed by an external resistor RWC, connected
from pin WC to ground and is given by:
Iw =
----'S.RWC
where K is the Write Current Constant.
Power supply fault protection improves data security
by disabling the write current generator during a voltage fault or power supply sequencing.
PIN DESCRIPTIONS
NAME
R/W
WDI
TYPE
DESCRIPTION
I
ReadIWrite - A high level selects Read Mode
I
WRITE DATA IN - Negative transition toggles direction of head current
HDX, HDY
1/0
X,Y head connections
RDX,RDY
0
X, Y READ DATA - Differential read signal output
WC
I
WRITE CURRENT - Used to set the magnitude of the write current
VCT
0
VOLTAGE CENTER TAP - Voltage source for head center tap
VCC
-
+5V
VDD1
-
+12V
VDD2
GND
Positive power supply for the center-tap voltage source
GROUND
4-18
0888
SSI32H566R
Ferrite Single-Channel
Servo Read/Write Device
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
All voltages referenced to GND. Currents into device are positive. Maximum limits indicate when permanent device damage occurs. Continuous operation at these levels is not intended and should be limited
to those conditions specified in the DC Operating Characteristics.
PARAMETER
RATING
UNIT
VDD1
DC Supply Voltage
-0.3 to +14
VDC
VDD2
DC Supply Voltage
-0.3 to +14
VDC
VCC
DC Supply Voltage
VIN
Digital Input Voltage Range
-0.3 to +7
VDC
-0.3 to VCC + 0.3
VDC
VH
Head Port Voltage Range
-0.3 to VDD1 + 0.3
VDC
Iw
Write Current (O-pk)
60
mA
RDX, RDY (10) Output Current
-10
mA
VCT Output Current
-60
mA
Storage Temperature Range
-65 to 150
Lead Temperature PDIP,
Flat Pack (10 sec Soldering)
260
°c
°c
Package Temperature PLCC,
SO (20 sec Reflow)
215
°c
Tstg
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MIN
NOM
MAX
UNIT
DC Supply Voltage
10.8
12.0
13.2
VDC
VCC
DC Supply Voltage
4.5
5.0
5.5
VDC
Lh
Head Inductance
15
~H
VDD1
RCT'
RCT ReSistor
Iw
Write Current (O-pk)
Tj
Junction Temperature
Range
CONDITIONS
1w=40mA
137
n
10
40
mA
+25
+135
°c
123
130
'For Iw = 40 mA. At other Iw levels refer to Applications Information that follows this specification.
0888
4-19
SSI32H566R
Ferrite Single-Channel
Servo ReadIWrite Device
DC CHARACTERISTICS (Recommended operating conditions apply unless otherwise specified.)
POWER SUPPLY
PARAMETER
MIN
CONDITIONS
NOM
MAX
UNIT
VCC Supply Current
Read
Read Mode
13
mA
Write
Write Mode
25
mA
VDD Supply Current (sum of VDD1 and VDD2)
Read
Read Mode
33
mA
Write
Write Mode
10+lw
mA
Read
Read Mode
500
mW
Write
Write Mode, Iw = 40 mA,
RCT= on
700
mW
Write Mode, Iw = 40 mA,
RCT= 130n
500
mW
MAX
UNIT
0.8
VDC
Power Dissipation (Tj = + 135°C)
DIGITAL I/O
PARAMETER
CONDITIONS
VIL
Input Low Voltage
VIH
Input High Voltage
ilL
Input Low Current
VIL = 0.8V
IIH
Input High Current
VIH = 2.0V
MIN
NOM
2.0
VDC
-0.4
mA
100
J.IA
MAX
UNIT
WRITE MODE
PARAMETER
CONDITIONS
VCT
Write Mode
Center Tap Voltage
Head Current (per side)
MIN
6.7
Write Mode,
0:<> VCC:<> 3.7V,
0:<> VDD1 :<> 8.7V
Write Current Range
Write Current Constant uK"
VDC
-200
200
J.IA
10
40
mA
2.375
Iwc to Head Current Gain
RDX, RDY Output Offset Voltage
NOM
2.625
mA/mA
0.99
Write/Idle Mode
-20
4-20
+20
mV
0888
SSI32H566R
Ferrite Single-Channel
Servo ReadlWrite Device
WRITE MODE (Continued)
PARAMETER
CONDITIONS
MIN
RDX, RDY Common Mode
Output Voltage
Write/Idle Mode
RDX, RDY Leakage
RDX, RDY = 6V
Write/Idle Mode
-100
PARAMETER
CONDITIONS
MIN
VCT
Read Mode
NOM
MAX
UNIT
VDC
5.3
100
~
MAX
UNIT
READ MODE
Center Tap Voltage
NOM
VDC
4.0
Read or Idle Mode
0$ VCC $ 5.5V
0$ VDD1 $ 13.2V
-200
200
~
45
Output Offset Voltage
Read Mode
-615
+615
~
mV
Common Mode Output Voltage
Read Mode
4.5
6.5
VDC
Head Current (per side)
Input Bias Current (per side)
DYNAMIC CHARACTERISTICS AND TIMING
(Iw = 35 rnA, Lh = 10 J.lH, Rd = 7500, f(WDI) = 5 MHz, CL(RDX, RDY) $ 20 pF. Recommended operating
conditions apply unless otherwise specified.)
WRITE MODE
PARAMETER
CONDITIONS
Differential Head Voltage Swing
MIN
NOM
MAX
7.0
V(pk)
Differential Output Capacitance
Differential Output
Resistance
UNIT
600
15
pF
960
0
MAX
UNIT
175
VN
READ MODE
0888
PARAMETER
CONDITIONS
MIN
Differential Voltage Gain
Vin = 1 mVpp @ 300 KHz
ZL(RDX), ZL(RDY) = 1 KO
125
Dynamic Range
AC Input Voltage, Vi, @ 300 KHz
Where Gain Falls by 10%.
±2
4-21
NOM
mV
SSI32H566R
Ferrite Single-Channel
Servo Read/Write Device
READ MODE (Continued)
MIN
PARAMETER
CONDITIONS
Bandwidth (-3d B)
IZsl < 5n, Vin = 1 mVpp
NOM
MAX
UNIT
MHz
30
Input Noise Voltage
BW= 15 MHz,
Lh = 0, Rh = 0
1.5
nV/{Hz
Differential Input Capacitance
f = 5 MHz
20
pF
Differential Input
Resistance
f = 5 MHz
500
1000
n
Common Mode Rejection Ratio
Vcm = VCT + 100 mVpp
@5MHz
50
db
Power Supply Rejection Ratio
100 mVpp@ 5 MHz on
VDD1, VDD2 or VCC
45
db
Single Ended Output Resistance
f = 5 MHz
Output Current
AC Coupled Load,
RDXto RDY
±2.1
CONDITIONS
MIN
30
n
mA
SWITCHING CHARACTERISTICS
PARAMETER
NOM
MAX
UNIT
R/W
R/W To Write Mode
Delay to 90% of
Write Current
1.0
~s
R/W to Read Mode
Delay to 90% of
100 mV 10 MHz Read
Signal Envelope or
to 90% decay of
Write Current
1.0
~
Prop Delay - TD1
From 50% points
25
ns
Asymmetry
WDI has 50% duty cycle and
1 ns Rise/Fall Time
2
ns
Rise/Fall Time
10% - 90% points
20
ns
Head Current (Lh
= O~H. Rh =On)
4-22
0888
SSI32H566R
Ferrite Single-Channel
Servo ReadlWrite Device
WDI
HEAD
CURRENT
(Ix -Iy)
FIGURE 1: Write Mode Timing Diagram
APPLICATIONS INFORMATION
The specifications, provided in the data section, account for the worst case values of each parameter
taken individually. In actual operation, the effects of
worst case conditions on many parameters correlate.
Tables 3 & 4 demonstrate this for several key parame-
ters. Notice that under the conditions of worst case
input noise, the higher read back signal resulting from
the higher input impedance can compensate for the
higher input noise. Accounting for this correlation in
your analysis will be more representative of actual
performance.
TABLE 3: KEY PARAMETERS UNDER WORST CASE INPUT NOISE CONDITIONS
PARAMETER
Tj=25°C
Tj=125°C
UNIT
Inputs Noise Voltage (max.)
1.1
1.5
nV/VHz
Differential Input Resistance (min.)
850
1000
Q
Differential Input Capacitance (max.)
11.6
10.8
pF
TABLE 4: KEY PARAMETERS UNDER WORST CASE INPUT IMPEDANCE CONDITIONS
PARAMETER
0888
Tj=25°C
Tj=125°C
UNIT
Inputs Noise Voltage (max.)
0.92
1.2
nV/YHZ
Differential Input Resistance (min.)
500
620
Q
Differential Input Capacitance (max.)
10.1
10.3
pF
4-23
SSI32H566R
Ferrite Single-Channel
Servo Read/Write Device
SEE NOTE 3
+12V
SEE NOTE 1
SEE NOTE 3 ....- - - - ,
O.1~FI
vee VDD1 VDD2 veT
r----------~
ruw
HDX
1---,
HOY
1----"
SSI32H566R
RDX
ROY
READ
DATA
SSl32P541 READ DATA PROCESSOR
--------------------+1
WDI
we
GND
SEE NOTE 4
Rwe
NOTES
1. An external resistor, ReT, given by; ReT::;; 130 (40/1w) where Iw is the zero-peak write current in mA,
can be used to limit internal power dissipation. Otherwise connect VDD2 to VDD1.
2. Limit De current from RDX and RDY to 100 ~ and load capacitance to 20 pF.
3. The power bypassing capacitor must be located close to the device with its ground returned directly
to device ground, with as short a path as possible.
4. To reduce ringing due to stray capacitance this resistor should be located close to the device. Where
this is not desirable a series resistor can be used to buffer a long we line.
FIGURE 2: Typical Application
4-24
0888
SSI32H566R
Ferrite Single-Channel
Servo ReadlWrite Device
PACKAGE PIN DESIGNATIONS
(TOP VIEW)
RDX
14
VDD
RDY
2
13
HDX
R!W
3
12
HDY
GND
4
11
VCT
N/C
5
10
WC
N/C
6
9
VDD2
WDI
7
8
VCC1
14-Pln SON
THERMAL CHARACTERISTICS: 0ja
= 130 °C/W
ORDERING INFORMATION
PART DESCRIPTION
I
ORDER NO.
I
PKG.MARK
J
32H566R-N
SSI 32H566R Servo Ferrite Single Channel Read/Write Device
14-Pin SON
I
SSI 32H566R-N
No responsibility is assumed by SSi for use of this product nor for any infringements of patents and trademarks or other rights of third parties
resulting from its use. No license is granted under any patents, patent rights or trademarks of SSi. SSi reserves the right to make changes
in specifications at any time without notice.
CA. 92680 (714) 731-7110, TWX 910-595-2809
Silicon Systems, Inc., 14351 Myford Road, Tustin,
©1988 Silicon Sytems, Inc.
0888
4-25
NOTES:
SSI32H567
Servo Demodulator
INNOVATORS IN
~IN~T~EG~RA~T~I~O~N~
________________________
August, 1988
DESCRIPTION
sponse and sync separatorthreshold. Its high performance analog/digital circuitry is capable of supporting
servo frame rates of up to 500 KHz.
The SSI 32H567 Servo Demodulator is a bipolar device intended for use in Winchester disk drives with
dedicated surface head positioning systems. It processes a di-bit quadrature pattern read from the servo
surface by a preamplifier, such as the SSI 32H101 or
SS132H116, and generates normal and quadrature (N
and Q) position reference signals. These signals provide the servo controller with position error feedback. A
complete position control system can be realized with
the SSI 32H567 and its companion devices, the
SSI 32H568 Servo Controller and SSI 32H569 Servo
Motor Driver.
FEATURES
•
•
•
Servo signal demodulation for Winchester
disk drives with dedicated surface head positioning systems
suppons Industry standard di-bit quadrature
servo pattern with frame rates up to 500 KHz
N, Q outputs convey track crossing and position error Information
•
The SSI 32H567 incorporates an input amplifier with
automatic gain control and offset cancellation, a phase
locked loop and sync separator to recover timing information, and pulse area detectors to recover the position information embedded in a di-bit quadrature servo
pattern. In addition, a bandgap voltage generator provides an analog reference level for the entire servo
electronics path. External components are used to set
the operating characteristics of the SS132H567, such
as AGC response, VCO center frequency, PLL re-
Pulse area detection technique for superior
noise Immunity
PLL for timing recovery and synchronization
•
•
•
Adjustable sync separator threshold
Auto-zeroing AGC input amplifier
•
•
Precision bandgap voltage reference output
Advanced bipolar process dissipates less than
850 mW (5V, 12V)
Available in 28-pln PLCC or 28-pin DIP
•
BLOCK DIAGRAM
"GNP
0888
TW
THR
5A"i'A
SYNC
DGND
LF
BP1
4-27
VPA
BP2
vee
CLD
VREF (5.4\1)
LOCI<
C1
SSI32H567
Servo Demodulator
FUNCTIONAL DESCRIPTION
(Refer to block diagram, and typical application, Fig.2)
The SSI32H567 processes servo position information
which is read from a dedicated surface by a pre-amplifier. The servo information must conform to the 'di-bit
quadrature' pattern which is illustrated in Figure 3.
Servo frames, conSisting of data and sync pulses
followed by four information pulses (A, 8, C, D) are
prerecorded along each track of the servo surface. All
the servo frames on an individual track are identical,
but in the radial direction four different frame types are
encountered, with every fourth track being identical.
The N signal generated by the SSI 32H567 is proportional to the difference in sizes of pulses A and 8, while
the Q signal is proportional to the difference between
pulses C and D. When the read head is off traCk, the
read signal is effectively a linear interpolation between
the prerecorded information of two adjacent tracks,
making it possible to sense the head displacement
exactly.
The SSI32H567 has a differential input amplifier which
incorporates offset voltage cancellation and automatic
gain control. An external read preamplifier must provide a differential input signal of 23 to 400 mV peak to
peak from the servo read head. This signal is applied
to a pulse area detector whose output is proportional to
the area under the positive half of the input pulse. The
external capacitor CAD integrates the incoming pulses
while they are positive, and is discharged when they go
negative. This area detection technique provides improved noise immunity over voltage detection.
An AGC circuit adjusts the input gain so that the maximum pulse area detector output is 2V peak. The AGC
circuit incorporates a peak detector which stores the
maximum pulse area signal on the external capacitor
CPK. This signal is compared to an internal amplitude
reference and the input amplifier gain is adjusted until
they are equal. The capacitor CAGC determines the response time of the gain control circuit. An offset cancellation circuit, whose response is set with the external
capacitor CAZ, ensures that the average level at the differential amplifier output is zero.
All internal analog signals are referenced to a 5.4V
bandgap reference voltage. This level is available at
the VREF output, which is capable of supplying 10 mA
to the rest of the servo path electronics.
In a standard servo frame, the data and sync pulses are
. more closely spaced than the information pulses (A-D).
This allows the sync detect circuit to recover the SYNC
pulses. A threshold, which is defined as percentage of
the peak signal atthe output ofthe AGC amplifier, is set
externally with RTH. Pulses which exceed this threshold are defined as vaRd pulses (ie. potentially SYNC or
DATA). As illustrated in Figure 5, at the end of the
positive going half of a valid pulse, a window set by Rw
and Cw is opened. If a second valid pulse occurs within
this window, it is recognized as a SYNC pulse. This
pulse becomes the input signal to a phase locked loop
whose VCO clock frequency is 32 times the SYNC
frequency (servo frame rate). The DATA output pin is
low whenever a SYNC pulse is detected. The example
illustrated in Figure 5 includes the case of a missing
DATA pulse. The SYNC clock output, which marks the
start of a new servo frame, is derived from the VCO
output so that the clock continues to run when a data
pulse is missing. Absolute positioning information such
as track 0 and guardband flags may be encoded on the
servo surface by the omission of data pulses.
The phase detector compares the detected sync
pulses with the SYNC output. A current pulse proportional to the phase error is applied to an external loop
filter network connected to the LF pin, to generate the
VCO control voltage. If improved power supply rejection is required, bypassing may be provided at pins
8P1 and 8P2. The VCO center frequency is determined by the external components RVCD and CVCD.
A lock detect circuit measures the phase difference
between the detected sync pulses and the sync output.
When this difference exceeds half of a VCO clock
cycle, a pulse of discharge current is applied to CLD.
Otherwise a pulse of charging current is applied to
CLD.
A clamp circuit limits the swing of the CLD pin and also
insures that a small amount of hysteresis is present.
When the voltage on CLD falls below the upper clamp
level by more than the "lock margin," the LOCK output
transistor is turned on. Likewise, when the voltage on
CLD rises above the lower clamp level by more than the
"unlock margin," the LOCK output transistor is turned
off.
Internal timing windows are generated from the recovered SYNC pulse and VCO clock. These windows,
WA, W8, WC, and WD, in Figure 4, enable the integra-
4-28
0888
SSI32H567
Servo Demodulator
FUNCTIONAL DESCRIPTION (Continued)
after the D pulse has been detected. Nand Q should be
sampled by the servo controller on the next falling edge
of the SYNC output clock.
tion of the A, B, C, D pulses, respectively. Four peak
detectors at the output of the pulse area detector are
enabled in succession to capture the A, B, C and D
information pulses, and the Nand Q analog outputs are
formed by differencing adjacent pulses. These outputs
change during a servo frame and only become valid
An example of an entire servo path implemented with
the SSI 32H567 and its companion devices, the
SS132H568 and SSI32H569, is shown in Figure 7.
12V
AGND
CAGe
DGND
A
VPA
B
SV
VREF (S.'V)
I
VCC
12V
5V
(ANALOG) (DIGITAL)
CPK
AGC
GAIN
CONTROL
a
CAD
RVCO
RW
SAMPLE CLOCK }
SERVQDATA
TO SERVO CONTROLLER
FIGURE 2: TYPICAL APPLICATION
0888
4-29
SSI32H567
Servo Demodulator
PIN DESCRIPTION
POWER
NAME
TYPE
VREF
0
REFERENCE VOLTAGE - 5.4V output. All analog signals are referenced to this voltage.
AGND
-
ANALOG GROUND
VPA
VCC
DGND
DESCRIPTION
ANALOG SUPPLY - 12V power supply.
DIGITAL SUPPLY - 5V power supply.
DIGITAL GROUND
INPUT AMPLIFIER
NAME
TYPE
DESCRIPTION
CAZ
-
AUTOZERO CAPACITOR - A capacitor which sets the response of the
input amplifier offset cancellation circuit should be connected between
this pin and analog ground.
IN+
I
NON-INVERTING INPUT - AGC input amplifier connection. The noninverting output of the differential servo pre-amplifier should be AC
coupled to this pin.
IN -
I
INVERTING INPUT - AGC input amplifier connection. The inverting
output of the differential servo pre-amplifier should be AC coupled to this
pin.
CPK
-
PEAK HOLD CAPACITOR - A capacitor which is used by the peak
detector of the AGC circuitry must be connected between this pin and
analog ground.
CAGC
-
AGC CAPACITOR - A capacitor which sets the AGC attack and decay
times must be connected between this pin and analog ground.
TIMING RECOVERY
NAME
TYPE
DESCRIPTION
VCO
0
VCO OUTPUT - TTL compatible digital clock which is 32 times the sync
frequency (servo frame rate).
C2,C1
-
VCO CAPACITOR - Connection points for a capacitor which sets the
VCO center frequency in conjunction with an external resistor connected to RVCO.
BP1,BP2
-
PLL BYPASS - Bypass capacitors may be connected between these
pins and analog ground to provide additional power supply rejection in
the phase locked loop.
4-30
0888
SSI32H567
Servo Demodulator
TIMING RECOVERY (Continued)
NAME
TYPE
DESCRIPTION
LF
-
PHASE LOCKED LOOP FILTER - An external RC network which sets
the PLL loop characteristics must be connected between this pin and
analog ground.
RVCO
-
VCO RESISTOR - Connection for a resistor which sets the VCO center
frequency, in conjunction with the capaCitor between pins C1 and C2.
The resistor must be connectedbetween this pin and the VREF output.
SYNC
0
SYNC OUTPUT - TTL compatible digital clock whose falling edge
indicates the presence of valid analog signals on the Nand Q outputs.
There is one SYNC cycle per servo frame.
DATA
0
DATA OUTPUT - Active low TTL compatible digital output that indicates
the presence of a data pulse in the servo frame. This signal is updated
on the falling edge of the SYNC output.
TW
-
TIMING WINDOW - A resistor and capacitor must be connected in
parallel between this pin and analog ground to set a timing window
which is used in detecting SYNC pulses.
THR
-
PULSE THRESHOLD - A resistor which sets a threshold for SYNC and
DATA pulse detection must be connected between this pin and VCC
(digital5V supply).
CLD
-
LOCK DETECT CAPACITOR - The value of this capaCitor determines
how quickly the LOCK output responds.
LOCK
0
LOCK OUTPUT - An open collector output that indicates the lock status
of the PLL.
POSITION INFORMATION
NAME
TYPE
DESCRIPTION
CAD
-
AREA DETECTOR CAPACITOR - A capacitor, which forms an integrator to sense the pulse area of the servo position Signals, must be connected between this point and analog ground.
N
0
N OUTPUT - This sampled analog signal is the normal position
reference output. N is referenced to VREF and is periodic in radial displacement, with a period of 4 tracks.
Q
0
Q OUTPUT - This sampled analog signal is the quadrature position
reference output. Q is referenced to VREF and is periodic in radial displacement, with a period of 4 tracks. It is 90 degrees out of phase with
N.
No connects on PLCC package: 4, 7
0888
4-31
SSI32H567
Servo Demodulator
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
(Maximum limits indicates where permanent device damage occurs. Continuous operation at these limits is
not intended and should be limited to those conditions specified in the DC operating characteristics.)
PARAMETER
CONDITIONS
MIN
VCCvoltage
TYP
0
VPAvoltage
MAX
UNITS
8
V
0
16
V
Voltage on PLL inputs
-0.5
VCC+0.5
V
Voltage on other inputs
0
14
V
Storage Temp.
Solder Temp.
-45
10 sec. duration
160
°C
260
°C
RECOMMENDED OPERATION CONDITIONS (Unless otherwise noted, the following conditions are valid
throughout this document.)
PARAMETER
CONDITIONS
VPA, analog supply
Supply noise
MIN
TYP
MAX
UNITS
10.8
12
13.2
V
0.1
Vp-p
4.75
5
5.25
V
70
°C
MAX
UNITS
50
mA
52
mA
F<1 MHz
VCC, digital supply
Ta, ambient temperature
0
DC CHARACTERISTICS
PARAMETER
CONDITIONS
MIN
TYP
IPA, VPA current
ICC, VCC current
VOH, digital output high
IIOHI<40 J.LA
VOL, digital output low
IIOll<1.6 rnA
2.4
0.4
IREF, VREF
output current capacity
VREF output voltage
V
rnA
10
IIREFI<10 mA
5.1
4-32
V
5.4
5.7
V
0888
SSI32H567
Servo Demodulator
ELECTRICAL SPECIFICATIONS (Continued)
AC CHARACTERISTICS
PARAMETER
CONDITIONS
VREF output impedance
lOUT = 0-10 mA
1 JlF bypass to AGND
Frequency<15MHz
MIN
TYP
MAX
UNITS
7
n
100
n
N, Qoutputs
Output impedance
F = 1 MHz
Load resistance
To VREF
Kn
10
Load capacitance
Peak output voHage
Referenced to VREF
23-400 mVp-p differential
1.8
2
Offset voltage
50
pF
2.2
V
10
mV
Input amplifier
Input resistance
Kn
5
Input resistance mismatch
Input capacitance
Bandwidth
10
1
%
20
pF
20
MHz
30
nVI-vHz
Input referred noise
10 Hz.
I
U)
-....I
""'"
OOTPUT
~~
WA
WI!
we
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _---lI17 " "
..,
____________________
III
f::-,.--:.."--::",.--lL -_ _ _ _ _ _ _ _ _ _ _ __
~
fC
<
o
c
CD
en
3en
0c. W
eN
FIGURE 4: TIMING DIAGRAM
--
-:::E:
am
00)
......
SSI32H567
Servo Demodulator
VAUDPULSE
THRESHOLD ~ __ J
D
DATA
A
SYNC
B
C
D
SYNC
_
--+-4r,-~-1~~~.-~~r-~~~--------~-;~~-------f-;"r---
VALID PULSE
Rw, Cw TIMING WINDOW
I
INTERNAL SYNC
DETECTION
:
_______________~r__i
!
I
~i----------------~~
DATA OUTPUT
SYNC DETECT
(DERIVED FROM
VCOCLOCK)
N,aOUTPUTS
I
ri---
--11
:
I
~
STABLE
1_
II
:0lIl
SERVO FRAME
I
I
I
STABLE
1
II
~:
I
FIGURE 5: SYNC AND DATA PULSE DETECTION
4-38
0888
g
&l
AGND
Lt
CAGe
O.04j1F
CAGC
CPK I
I
A
DGND I
VPA
VREF (5.4V)
5V
12V
vee
I
12V
5V
(ANALOG) (DIGITAL)
AGe
CpK
lSOOpF
GAIN
CONTROl
A
N
>-o:;;;rl
O.lj1F ~
>-o:;;;rl
IN +
N-
FROM
SERVO
PREAMPLIFIER
Q
O.lj1F
CAD
,J:o.
II
CD
CAD _ 45 pF FOR 16 MHz
~
A
PHASE LOCKED LOOP
vco
vco
cll
I'
RVCO _llKO
4\g~~R
VREF
%TH
CLOCK
D-+ ~~~LER
021 RVCO
Cvco
..:!!...
720
fVCO
en
(D
o<
C
(Den
3en
0-
-100 _1 KnFOR 37%
}
TO SERVO CONTROLLER
SERVO DATA
CDn 127t .. 4600 Hz
z •.88
FIGURE 6: DESIGN EXAMPLE FOR 500 KHz FRAME RATE
Q,W
Cl\)
-:::t
!,UI
0(7)
""' ......
I
PO.O
I EN
80C51
VPD
Xl
~~z
0
Vcc~l-r-VPA
W
---t
1-1
~
A15
CS
RBIAS
RD
RD
AGND~
WR
WR
INT
INT
., I
1-------,1
PREAMPLIFIER
0.11' F
~
~
o
~F
SERVO
READ HEAD
l1
IDGND
::: I
IN+
H·BRIDGE
"
,
N
Q
VEL
RP4
FP4
,1
1-_--=-_ _
~I
OLITC~·-----------------~
CLOCK FP3
FV4
Cl
' - I_ - -
1 - 1- - . . . - ,
VEL·
VELOCITY
LOOP FILTER
CVCO
+ 12V
C2
VPA
C~
..---,----ll
RW
FV21 , • • M' ,
FV31
oJ'{If--'
CAD
BPl
B:
BYP
I
SOLIT
+5V
SSl32H!I68
ERR
RBRK
TW
SSl32H!I67
FVl
RIN
EOLIT 1
IN
RL2 CL3
1
SSl32H569
1 ERR·
TO SPINDLE MOTOR
BRAKING TRANSISTOR
BRK
LOOP COMPENSATION
r------il
VREF
SERVO
ERR+
VREF
Rcs
SERVO
IIOTOR DRIVER
CONTROLLER
CBYP
w
FIGURE 7:
COMPLETE EXAMPLE OF SERVO PATH ELECTRONICS USING
SSI32H567/568/569
I
MOTOR
DRIVER
SYNC ,I- - - - - I SYNC
IN·
I,
OLITA
Rp2
FP21
...
( +12V
<. + 12V
I
POSITION
LOOP FILTER
+5V
I
INS820
ADo.7
ADO-7
XO
LOWV
c
a
°...
.....
SSI32H567
Servo Demodulator
PACKAGE PIN DESIGNATIONS
CAUTION: Use handling procedures necessary
for a static sensitive component.
(TOP VIEW)
VREF
THR
AGND
TW
CAZ
LOCK
NlC
DATA
0
Z
~
0
0
u.
Cl
a:
>
I
;:
'"0
I--
9
1
28
27
26
z
<
SYNC
IN+
IN+
CLD
IN-
N/C
RVCO
CPK
LF
CAGC
CAD
SYNC
N/C
23
CLD
22
RVCO
N
C1
Q
C2
N
VCC
VCO
!lATA
24
CAD
DGND
25
0
8
CAGC
BP1
VPA
a:
I--
IN-
CPK
BP2
w
10
11
21
LF
20
BP2
19
BP1
12
13
14
15
16
17
0
<
">
0
0
0
0
>
Cl
'"0 u
28-Pln DIP
>
0
z
18
0
28-Pln PLCC
ORDERING INFORMATrON
PART DESCRIPTION
ORDER NO.
PKG.MARK
SS132H567, Servo Demodulator
28-Pin DIP
SSI 32H567-CP
32H567-CP
28-Pin PLCC
SS132H567-CH
32H567-CH
No responsibility is assumed by SSi for use of this product nor for any infringements of patents and trademarks or other rights of third parties
resulting from its use. No license is granted under any patents, patent rights or trademarks of SSi. SSi reserves the right to make changes
in specifications at any time without notice.
CA 92680, (714) 731-7110, TWX 910-595-2809
Silicon Systems, Inc., 14351 Myford Road, Tustin
©1988 Silicon Systems, Inc.
0888
4-41
I
NOTES:
SSI32H568
Servo Controller
INTEGRATION
August, 1988
DESCRIPTION
FEATURES
The SSI32H568 Servo Controller is a CMOS device intended for use in Winchester disk drive head positioning systems. When used in conjunction with a position
reference, such as the SSI 32H567 Servo Demodulator, and a motor driver, such as the SSI 32H569 Servo
Motor Driver, the device allows the construction of a
high performance, dedicated surface head positioning
system which operates under microprocessor control.
•
The SSI32H568 generates position and track crossing
information from standard di-bit quadrature position
signals, derived from a dedicated servo surface. In its
seek mode, the controller attempts to match the actual
head velocity to a programmed target value, while in its
track mode, it keeps the head centered on a track.
Internal status and control registers allow a microprocessor to select operating modes, monitor track information and establish velocity targets.
(Continued)
Servo control for Winchester disk drives with
dedicated surface head positioning systems
Accepts standard dl-blt quadrature position Information
500 KHz maximum servo frame rate
•
•
•
Microprocessor bus Interface compatible with
16 MHz 8051
•
•
•
•
•
•
Seek and track modes
Programmable velocity profile and loop gains
Internal offset cancellation capability
Track crossing Interrupt
Low power CMOS design
Available In 32-pln DIP or 44-pln PLCC packagIng
BLOCK DIAGRAM
FPl
...
FPO
FPO
Q
ECUT
VPD
YPA
1IESET
YREF
TiS"
liT
AGND
ALE
m
AS1AS
SELECT CORNEA
WI!
FREaJENCY(ND)
YDD
ACOIN
""
DGN)
AO~AD7
0888
~
FYI
FY3
...
FY2
4-43
SYNC
a..oa<
I
SSI32H568
Servo Controller
DESCRIPTION (Continued)
The microprocessor bus interface is optimized for use
with muHiplexed address/data bus microprocessors
such as Intel's 8051, operating at up t016 MHz.
The SS132H568 is a low power, CMOS device and is
available in 32-pin DIP and 44-pin PLCC packaging.
FUNCTIONAL DESCRIPTION
The SSI 32H568 receives position information from a
servo demodulator through the analog inputs Nand 0,
which are sampled on the falling edge of SYNC.
FSYNC, the maximum SYNC frequency (which is the
servo frame rate) is 500 KHz. The position processor
compares the analog N signal with both 0 and -0, to
generate the digital signals NO and NO. Since the N
and 0 signals have a period offourtracks, NO and NQ
provide additional information on which track the head
is positioned over. Figure 6 shows the behavior of
various position signals as radial displacement
changes. A track crossing signal (TRKCS) may be
programmed to provide an indication of each track
crOSSing, or alternate track crossings. Internal timing
hysteresis forces the NO and NO bits to remain constant for at least two servo frames. This prevents noise
at the Nand 0 inputs from causing multiple track
crossing indications at low head velocities.
The SS132H568 has two modes of operation, track and
seek, which are selected under microprocessor control. In the track mode, the control loop drives the
position error signal to zero. In the seek mode, the loop
attempts to match the head velocity to a velocity target
programmed through the microprocessor interface.
In track mode, the head position error signal is summed
with an 8-bit programmable offset signal which may be
used to null out circuit offsets orto permit reading of offtrack data. This adjusted position error signal is available on pin FP1. A Iowpass fiber with a comer frequency above 0.1 • FSYNC provides a small amount of
smoothing. A position loop filter may be constructed
from external RC components and amplifier A1, whose
output is switched to buffer amplifier A2 while track
mode is selected (control bit T/S=1). Switch S1, controlled by the DUMP bit, is used to keep the feedback
capacitor in the position loop fiHer discharged while the
controller is in seek mode. The output of A2 is the error
signal (EOUl) which should be connected to the servo
motor driver circuitry. The position error is also applied
to a window comparator with programmable limits that
provide a digital indication of whether the head is on
track or not, through the ONTRK bit in the status
register. In systems employing the SSI32H569, EOUT
should be connected to the SSI 32H569 ERR- pin
through an input resistor.
The SSI 32H568 has a calibration control which permits the cancellation of position error offsets. When the
control bit CAL is set, the inputs to the position processor are switched to VREF instead of N and O. A
comparator connected to the EOUT pin senses the
sign of the error signal (ERSGN), allowing the microprocessor to aHer the offset DAC input word until an
LSB change causes ERSGN to change state. At this
point internal offsets in the position error path have
been cancelled.
In seek mode, the position error is dHferentiated by a
switched capacitor differencer, to produce a velocity
estimate. The differencer does not sample the position
error immediately after the discontinuity that occurs
when a track boundary is crossed. This prevents the
discontinuity from disturbing the differentiator output.
The velocity estimate is applied to a velocity loop filter
consisting of external RC components and amplifier
A3. A signal proportional to motor current may also be
summed in at A3, to compensate for the fact that during
rapid acceleration the high pass fiHer does. not accurately model a differentiator. Switch S2, controlled by
the ACCIN bit, allows the motor current feedback to be
aHered under microprocessor control. A velocity error
term is computed as the difference between the velocity target and the actual head velocity. The velocity
target is generated by a DAC from the digital word
stored in the TARGET register. The output of the
velocity 100pfiHer (pin FV4) is proportionaltothe actual
head velocity and is scaled by a 4-bit programmable
velocity gain before being subtracted from the velocity
target. Also, a fill signal which is generated by muHiplying the position error by a 4-bit programmable fill gain
is subtracted from the velocity error. The fill signal
compensates for the 8-bit quantization of the velocity
target Signal, which becomes a factor as the head
velocity approaches zero. As the head nears the destination track at the end of a seek operation, the target
velocity is zero, so if a fill term which is proportional to
position error is subtracted from the velocity error term,
the velocity loop will calise the head to come to rest at
the center ofthe track. Withoutthis additional fill signal,
4-44
0888
SSI32H568
Servo Controller
the velocity loop would not necessarily center the head
in the destination track. In seek mode, the velocity error
signal is switched to buffer amplifier A2, which drives
the EOUT pin.
The actual velocity profile of the head is determined by
the values written to the target velocity DAC. Typically,
a new velocity target is written at each track crossing.
An automatic update feature (enabled when UP~
DATE=1) causes the next velocity target to be loaded
from a holding register when a track crossing occurs,
so that the microprocessor does not have to perform
this time-critical operation.
The SSI 32H568 has 8 registers, described in "Register Description", which are accessed through a microprocessor interface optimized for multiplexed address!
data bus processors. A 3-bit register address is latched
from the bus on the falling edge of ALE (address latch
enable) and a bus cycle occurs if CS (chip select) and
either RD (read strobe) or WR (write strobe) are asserted. An open drain interrupt line (INT) may be used
to cause a microprocessor interrupt when a track
crossing occurs.
--
ADDREI&'DATA BUS
2
SELECT CORIER
FREOLENCV (N»
LN:SFROM
YCO
'RON SERVO
DEMODU.ATOR
vaOCnYLOOPFLTER
FIGURE 2: SS132H568 TYPICAL APPLICATION
0888
4-45
SSI32H568
Servo Controller
PIN DESCRIPTION
POWER
NAME
32-pln
DIP
44-pln TYPE
DESCRIPTION
PLCC
RBIAS
11
16
I
BIAS INPUT - This input sets the intemal opamp bias currents. A
20 Kn 1% resistor should be connected between RBIAS and
AGND.
VREF
12
17
I
REFERENCE VOLTAGE -S.4V input which is used as the DC reference level for all analog signals. (This level is available as an
output from the SSI 32HS67).
AGND
13
19
ANALOG GROUND
DGND
18
27
DIGITAL GROUND
VDD
19
28
DIGITAL SV SUPPLY - 5 voit supply for the microprocessor
interface circuitry.
VPD
31
43
DIGITAL 12V SUPPLY - 12 volt supply for the switched capacitor
fiiter clocks.
VPA
32
44
ANALOG 12V SUPPLY - 12 volt supply for all analog circuitry.
POSITION REFERENCE INTERFACE
Q
9
14
I
QUADRATURE INPUT - Analog position signal from servo demodulator.
N
10
15
I
NORMAL INPUT - Analog position signal from servo demodulator
(90 degrees or 1 track out of phase with Q signal).
SYNC
29
40
I
SYNC INPUT - The falling edge of this clock causes the analog
information on the N, Q inputs to be sampled. There is one SYNC
pulse per servo frame and the maximum rate is 500 KHz. This
signal is generated by the SSI 32HS67.
CLOCK
30
41
I
CLOCK INPUT - This clock must be either 32 or 72 times the rate
of the SYNC clock (selected by the FRFMT bit in STATUS
register). It is usually supplied by the VCO output of the servo
demodulator (eg. SSI 32HS67).
MICROPROCESSOR INTERFACE
CS
14
21
I
CHIP SELECT - Active low signal enables device to respond to
microprocessor read or write.
ALE
15
22
I
ADDRESS LATCH ENABLE - Falling edge latches register address from pins ADO-AD2.
RD
16
23
I
READ STROBE - Active low signal causes the contents of the
addressed register to be placed on the address/data bus (ADO-7)
if CS is also active.
4-46
0888
SSI32H568
Servo Controller
MICROPROCESSOR INTERFACE (Continued)
NAME
32-pin
DIP
44-pin TYPE
PLCC
DESCRIPTION
WR
17
24
I
WRITE STROBE - Active low signal causes the data on the
addressldata bus to be written to the addressed register if CS is
also active.
INT
20
29
0
INTERRUPT - This active low open drain output is asserted when
a track crossing is detected. It is released when the intemal track
crossing status bit (TRKCS) is read by the microprocessor.
TIS
-
30
0
TRACK/SEEK - This output reflects the state of the TIS bit in the
STATUS register. It is high when the device is in track mode and
low when it is in seek mode (PLCC package only).
AD7
21-28
31-32
1/0
ADDRESSIDATA BUS - 8-bit bus which carries register address
-ADO
34-39
information and bi-directional data.
RESET
-
42
I
RESET - This active low input is used to force all the intemal
registers to their reset condition (PLCC package only).
OFFTRK
-
26
0
OFFTRACK - This open drain output is asserted whenever the
head position is outside the window specified by NW. It is always
asserted in seek mode (PLCC package only).
CONTROL LOOP
0888
FV4
1
1
0
VELOCITY FILTER OUTPUT - This is the output of amplifier A3
which forms part of the velocity loop filter. This signal is intemally
amplified and compared to the target velocity.
FV3
2
3
I
VELOCITY FILTER INPUT (SWITCHED) - This input is connectedtothe inverting input of amplifier A3 through a switch which
is closed when control bit ACCIN is set and open when ACCIN is
cleared.
FV2
3
5
I
VELOCITY FILTER INPUT - Direct connection to the inverting
input of amplifier A3.
FV1
4
7
0
ESTIMATED VELOCITY OUTPUT - Output of the position error
differentiating high pass filter.
EOUT
5
9
0
LOOP ERROR SIGNAL - Buffered output which is the position
error in track mode (TIS = 1) or the velocity error in seek mode
(TIS = 0). This signal should be connected to the servo motor
driver circuitry. In systems using the SSI 32H569 servo driver,
EOUT is connected to the SSI 32H569 pin ERR- through a
resistor.
FP4
*
11
0
POSITION FILTER CAPACITOR - The extemal position loop
filter feedback capacitor should be connected between this pin
and FP3. When the DUMP bit in register WINDOW is set, an
intemal switch (S1) shorts FP3 to FP4. This allows the extemal
capacitor to be kept discharged during seek mode.
4-47
SSI32H568
Servo Controller
CONTROL LOOP (Continued)
NAME
32-pin
DIP
44-pin TYPE
PLCC
DESCRIPTION
FP3
6
10
0
POSITION FILTER OUTPUT - Output of position loop filter
amplifier Ai. In track mode this signal is the position error and is
internally connected to buffer amplifier A2.
FP2
7
12
I
POSITION FILTER INPUT - Inverting input to opamp Ai.
8
13
0
POSITION ERROR OUTPUT - Offset-corrected output of the
position processing circuitry, which is proportional to the radial
displacement of the head from the center of the current track.
FP1
The actual transfer function from N, Q to FP1 is:
sin (roT /2)
3
H(z)=-2z-1
roT /2
where: T = 1 / FSVNC
z = esT
This transfer function exhibits a high frequency roll off with a.3d8 point at f = 0.11 FSYNC.
Unused pins on PLCC package: 2,4,6,8,18,20,25,33
• FP4 tied to FP2, Pin 7, internally on 32 pin DIP package.
REGISTER DESCRIPTION
The SSI 32H568 has 8 internal registers which contain status, control and loop parameter information. A three
bit register address is latched from inputs ADO-AD2 on the falling edge of ALE. The corresponding register is
accessed if CS is then asserted, with the direction of access being determined by RD or WR. The registers are
summarized in Figure 3.
REGISTER ADDRESS
ACCESS
D7
NEXT
2
VELCON
3
WINDOW
4
READI
WRITE
READI
WRITE
READI
WRITE
READI
WRITE
READI
WRITE
STATUS
5
AS NOTED
ERSGN
(READONlV)
OFFSET
6
READI
WRITE
SOS
RESET
7
WRITE ONLY
GAIN
0
TARGET
1
I
D6
I
D4
D5
D3
I
NFG
I
D2
Dl
I
DO
NVG
TARGET VELOCITY
NEXT TARGET VELOCITY
UNUSED
CAL
UNUSED
ACCIN
(REAOtWRITE)
ND
I
I
DUMP
TIS
CSMOD
(REAOIWRrTE)
FRFMT
(READNIRITE)
J UNUSED
I
ONmK
(READ ONL V)
UPDATE
NO
(READ ONLy)
I
I
ENA
NW
NQ
(READONLV)
I VELPOL
I
TAKes
(READONLV)
NOS
RESET (ANY VALUE)
FIGURE 3: SS132H568 REGISTER MAP
4-48
0888
SSI32H568
Servo Controller
REGISTER DESCRIPTION (Continued)
GAIN
Address 0
ReadIWrlte
GAIN SETTINGS - Used to set the velocity gain and fill gain. These settings are only significant in the
seek mode.
BIT
NAME
DESCRIPTION
0-3
NVGO-3
VELOCITY GAIN - 4-bit quantity which sets the gain applied to the velocity
signal at the output of opamp A3.
4-7
NFGO-3
FILL GAIN - 4-bit quantity which sets the gain applied to the position error
which is added to the velocity signal.
If NVG and NFG are represented as integers ranging from 0 to 15, then for a zero velocity target, the error
output in seek mode is given by:
EOUT - VREF = NVG ( FV4 - VREF) + NFG ( FP1 - VREF)
15
255
TARGET
Address 1
ReadIWrlte
CURRENT VELOCITY TARGET - This register selects the 8 bit velocity target which is subtracted from
the actual velocity to yield velocity error in seek mode. The sign of the velocity target is determined by the
VEL POL bit in register VELCON. If TARGET is represented as an integer from 0 to 255, then the voltage
at the output of the velocity target DAC, VT, is given by:
VT =VREF (1-
T~Er), VELPCl..=O
VREF (1 +
T~Er), VELPCl..=1
The SSI 32H568 has an update feature which allows this register to be loaded automatically with the
contents of the next target register when a track crossing occurs. The target register may also be written
to directly by the microprocessor to cause an immediate change in target velocity.
NEXT
Address 2
ReadIWrlte
NEXT TARGET VELOCITY - This register contains an 8-bit value that will be loaded automatically into
the velocity target registerwhen a track crossing occurs, ifthe UPDATE bit in VELCON is set. This register
is unused if UPDATE is cleared.
0888
4-49
SSI32H568
Servo Controller
REGISTER DESCRIPTION (Continued)
VELCON
Address 3
ReadlWrlte
BIT
NAME
DESCRIPTION
0
VELPOL
VELOCITY TARGET POLARITY - If this bit is set, the velocity target will
be positive (with respect to VREF) and if it is reset, the velocity target will
be negative.
1
ENA
ENABLE VELOCITY TARGET DAC -If ENA is set, the velocity target
DAC will be enabled and if it is cleared the output of the DAC will be
clamped to VREF.
2
UPDATE
UPDATE MODE SELECT - When this bit is set, the contents of the
NEXT register will be transferred to TARGET automatically when a track
crossing occurs. If it is cleared, new velocity targets must be written
directly to the TARGET register by the microprocessor.
3-4
NDO-ND1
DIFFERENTIATOR CHARACTERISTIC SELECT - These bits select the
characteristic of the differentiator high pass filter as follows:
H(s) = ~
1 + ':Ii
s
, W = ~ (1 + J:ill)
2T
1.75
G =14.3
rad/sec
Where T is the period of the SYNC clock input in seconds, s is the complex
frequency variable in radians/second and ND is an integer from 0 to 3. For
s«W the high pass filter H(s) acts like a differentiator. For a SYNC rate of
500 kHz, the corner frequency W will be:
.!iIlL1..N.QQ
':Ii.l"TJ,. (Istlz:)
00
01
10
11
39.8
62.5
85.3
108
The actual transfer function from N,
H (z)
a, to FV1
is:
-100(z-1)
sin( roT /2) where:T =1/FSYNC
z[7 (z -1) +(3.5+2 ND)]z
roT /2
z = esT
This transfers function is approximated throughout this data sheet with an
s domain approximation that is accurate for k .05 • FSYNC.
5-7
unused
4-50
0888
SSI32H568
Servo Controller
REGISTER DESCRIPTION (Continued)
WINDOW
Address 4
ReadIWrite
WINDOW CONTROL - This register is used to program the on-track window comparator and also
contains several control bits.
BIT
NAME
DESCRIPTION
0-2
NWO-NW2
WINDOW SELECT BITS - This 3 bit word selects the window comparator
threshold voltage. The on track indicator bit will be true as long as:
I FP1
- VREF I < VREF[(1 + NW)/32]
where NW is an integer from 0 to 7.
3
unused
4
T/S
TRACK/SEEK MODE SELECT - When this bit is set, track mode is selected
and when it is reset, seek mode is selected.
5
DUMP
POSITION LOOP FILTER DUMP CONTROL - When this bit is set, pins FP3
and FP4 are switched together internally by S1. This causes the external
position loop filter feedback capacitor to be discharged.
6
unused
7
CAL
STATUS
Address 5
CALIBRATION MODE - When this bit is reset, the N and Q inputs are
connected to the position processor and normal operation occurs. When
CAL is set, the processor inputs are connected to VREF, causing the FP1
output to reflect the offset voHage errors in the position sensing path.
ReadIWrlte access as noted
STATUS REGISTER - Contains track status information and several control bits.
0888
BIT
NAME
DESCRIPTION
0
TRKCS
TRACK CROSSING INDICATOR - The function of TRKCS is determined by
the CSMOD bit in this register. When CSMOD is set, TRKCSwill be set every
time NQ or NO change state (ie. on every track crossing). When CSMOD is
reset, TRKCS will be set every time NQ changes state (ie. on aHernate track
crOssings). TRKCS is reset every time STATUS is read by the microprocessor. The INT interrupt output is the inverse of TRKCS. (TRCKS is read only.)
1
NQ
TRACK QUADRANT - This bit is set when:
N-VREF > VREF-Q
and reset otherwise. (NO is read only)
2
NQ
TRACK QUADRANT - This bit is set when:
N-VREF > Q-VREF
and reset otherwise. (NQ is read only)
4-51
SSI32H568
Servo Controller
REGISTER DESCRIPTION (Continued)
BIT
NAME
DESCRIPTION
3
ONTRK
ON TRACK INDICATOR - This bit is set when the voltage on pin FP1 iswithin
the window selected by the WINDOW register. It is reset otherwise (ONTRK
is read only).
4
FRFMT
FRAME FORMAT - Used to indicate the relationship between CLOCK and
SYNC. If this bit is set, the VCO clock rate must be 32 times the SYNC clock
rate. If it is reset, the VCO clock rate must be 72 times the SYNC clock rate.
(FRFMT is read/Write).
5
CSMOD
CROSSING INDICATOR MODE - If this bit is reset, TRKCS will be set on
alternate track crossings. If it is set, TRKCS will be set on every track
crossing. JCSMOD is readlwrite).
6
ACCIN
ACCELERATION INPUT CONTROL - When this bit is set, the FV3 and FV2
inputs are connected internally. This allows motor current feedback to be
switched in and out of the velocity loop under microprocessor control.
JACCIN is read/write}.
7
ERSGN
ERROR VOLTAGE SIGN - This bit is set when:
EOUT-VREF < 0
and reset otherwise. It is used to determine the sign of the offset voltage
during calibration. (ERSGN is read only.)
OFFSET
Address 6
Read/Wrlte
OFFSET VOLTAGE REGISTER - The 8-bit value in this register drives the offset DAC which adds a
correcting voltage to the position error signal.
BIT
NAME
DESCRIPTION
0-6
NOSO-NOS6
OFFSET MAGNITUDE
7
SOS
OFFSET SIGN
The offset correction voltage, VOS, is given by:
VOS = - 0.89 (~ V , SOS=O
127
0.89 (~ V , SOS=1
127
RESET
Address 7
Write only
RESET REGISTER - When any value is written to this register, all writeable register bits inthe SSI 32H568
are reset.
4-52
0888
SSI32H568
Servo Controller
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
(Maximum limits indicate where permanent device damage occurs. Continous operation at these limits
is not intended and should be limited to those conditions specified in the DC operating characteristics.)
CONDITIONS
PARAMETER
MIN
TYP
MAX
UNITS
VPA
0
14
V
Voltage on any pin
0
VPA+O.1V
V
-45
Storage Temp.
Solder Temp.
10 sec duration
165
°C
260
°C
RECOMMENDED OPERATION CONDITIONS (Unless otherwise noted, the following conditions are valid
throughout this document.)
VPA,VPD
10.8
13.2
V
VDD
4.5
5.5
V
VREF
5.1
5.4
5.7
V
70
°C
22.6
22.9
KO
Operating temp.
0
RBIAS, bias resistor to AGND
22.3
DC CHARACTERISTICS
IVP
IDD
Total VPA and VPD current
VDD current
40
10
rnA
rnA
IREF
VREF current
3
rnA
DIGITAL I/O
Digital Inputs
VIH
IIIHI<10uA
VIL
IIILI<10uA
2
V
0.7
V
0.4
V
IIOLI<1.6mA
0.4
V
VOH=VPD
10
J1A
Digital Outputs (ADD-AD7, TIS)
VOH
IIOHI<40uA
VOL
IIOLI<1.6mA
Open Drain Digital OUtputs (iNf,
VOL
Off leakage
0888
2.4
V
OFFTRK)
4-53
SSI32H568
Servo Controller
MICROPROCESSOR INTERFACE TIMING (see figure 4(a) and figure 4(b)). (Timing measurements for
digital signals are measured at 1.3V. unless otherwise noted.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
45
UNITS
TLHLL
ALE pulse width
TAVLL
Address setup time
8
ns
TLLAX
Address hold time
20
ns
TRLVD
RD to data valid
TRHDX
data hold time after RD
TRLRH
RD pulse width
TLLWL
ALE to RD or WR
TRLCL
RD or WR to CS low
TRHCH
RD or WR to CS high
ns
0
145
ns
50
ns
200
ns
25
ns
20
ns
10
ns
TWLWH WR pulse width
100
ns
TQVWH data set up to WR high
70
ns
TWHQX data hold after WR high
10
ns
ANALOG I/O
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
N,Qlnputs
Input resistance
Offset voltage
Common mode range
KO
50
Input capacitance
-15
AboutVREF
25
pF
15
mV
4
V
N, Q Timing (see figure 5)
Fc
VCO input frequency
TSKW
TSYNC
Nc
4
16
SYNC skew
0
6
SYNC pulse width
40
MHz
ns
ns
VCO/SYNC
FRFMT=1
32
32
frequency ratio
FRFMT=O
72
72
TAOS
N or Q analog setup time
260
ns
TADH
N or Q analog hold time
180
ns
4-54
0888
SSI32H568
Servo Controller
tLHLL-o
4--
TLLWL-.
ALE
TAVLL
ADOAD7---<,
TLLAX
ADDRESS
DATA
~TRLVD----o
I--'
TRHDX
RD
I - - - TRLRH
----
TRLCL ~
~
TRHCH
CS
FIGURE 4(a): READ CYCLE TIMING
ALE
ADOAD?
DATA
--->+0----0/ TWHOX
.--<'i4----TWLWH
cs
--------~
FIGURE 4(b): WRITE CYCLE TIMING
VCO
SYNC
----'I
r-------------~/
TADS---to;O---->1TADH
N,Q
FIGURE 5: ANALOG TIMING
0888
4-55
SSI32H568
Servo Controller
ANALOG I/O (Continued)
PARAMETER
CONDITIONS
MIN
About VREF
100
TYP
MAX
UNITS
FP2, FV2, FV3 Inputs
Input resistance
Kn
Input capacitance
-15
Offset voltage
Switch resistance (81 , 82)
20
pF
15
mV
100
n
20
n
Kn
40
pF
Analog Outputs
Output impedance
IVo-VREFI<3V
Resistive loading
AboutVREF
5
Capacitive loading
Output swing (FP1, FV1)
AboutVREF
4
V
Output swing (FP3, FV4)
AboutVREF
3.5
V
Output swing (EOUT)
About VREF
3.7
V
Gain (FP1 from N or Q)
Gain (Amplifier A 1, A3)
9.45
Open loop DC gain
Gain (Amplifier A2)
9.55
9.65
66
dB
dB
-0.1
0.1
dB
Unity gain bandwidth
(Amplifier A 1, A3)
Open loop
1
MHz
Unity gain bandwidth
(Amplifier A2)
Open loop
0.5
MHz
PARAMETER
CONDITIONS
MIN
Threshold step size accuracy
Nominal=VREF/32
-30
PARAMETER
CONDITIONS
MIN
Maximum gain
NFG=15
WINDOW COMPARATOR
MAX
UNITS
30
%
TYP
MAX
UNITS
58
59
60
mV/v
3
4
5
mV/v
TYP
FILL GAIN
Gain step size
4-56
0888
SSI32H568
Servo Controller
VELOCITY GAIN
PARAMETER
CONDITIONS
MIN
Maximum gain
NVG=15
Gain step size
TYP
MAX
UNITS
.98
1
1.02
VN
48
67
82
mVN
TARGET VELOCITY DAC
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Full scaieNREF
VELPOL=1
1.72
1.75
1.78
VN
VELPOL=O
Step sizeNREF
Offset Match
.22
.25
.28
VN
1.9
2.9
3.7
mVN
20
mV
TARGET=O VELPOL=O,1
OFFSET CORRECTION DAC
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Full scaleNREF
NOS=127, SOS=1
.15
.16
.18
VN
NOS=127, SOS=O
-0.15
-0.16
-0.18
VN
.83
1.3
1.76
mVN
MIN
TYP
MAX
UNITS
13.7
14.3
14.9
VN
42.2
KHz
Step sizeNREF
DIFFERENTIATOR
PARAMETER
CONDITIONS
High pass gain
Corner frequency
0888
FSYNC = 500 KHz
ND=O
37.4
ND=1
57.3
66
KHz
ND=2
81.2
89.9
KHz
ND=3
102.7
113.8
KHz
4-57
SSI32H568
Servo Controller
APPLICATIONS INFORMATION
In the example shown in figure 7, the SSI 32H568 is
used with its companion devices, the SSI 32H567 and
SS132H569, as well as a microprocessor and some external components, to implement a complete head positioning system.
Position Reference
The position feedback signal for the servo loop is
generated by a servo demodulator from information
prerecorded on the disk drive's servo surface. The
SSI 32H567 provides quadrature position signals (N
and 0), recovered clocks (SYNC and VCO) and an
analog reference level (VREF) for the rest of the
system. The SSI 32H567 translates the radial displacement of the servo read head to a voltage with a
gain of 2 voltsltrack. The SSI 32H568 has a front end
gain of 3, so the gain from actual position error to the
voltage at pin FP1 (the input to the position loop filter)
is 6 volts/track.
In order to produce the position error signal illustrated
in figure 6, the position processor in the SSI 32H568
selects either N, 0 or an inverted signal, based on the
value of the digital signals NO and NQ. The resulting
error signal is zero (equal to VREF) when the head is
perfectly centered on a track. The error signal has a
maximum absolute value in the vicinity of a track
boundary (ie. when the head is displaced one halftrack
from a track center) and has a polarity that indicates
the direction of the position error.
INPUT FROM
SERVO DEMODULATOR (V)
TRACK N I TRACK N+ 1 I TRACK N+2 I TRACK N+3 I
I
VREF +3
I
I
I
POSITION
ERROR
SIGNAL
AT FPI(V)
VREF
VREF ·3
I
N:>Q
I
I
I
I
I
I~I
(NQ)L---J
I
L---J
I
N>.Q (NOliI
I
I
I
I
I
TRACK
CROSSINGI
(CSMOD=O),
I
I
I
I
I
I
I
I
n---:--
I
I
n L----.ln L----.ln L----.l L-..J
FALLING EDGE
CAUSED BY
REGISTER ACCESS
:
FIGURE 6: POSITION SIGNAL WAVEFORMS
4-58
0888
a
OJ
OJ
OJ
PO.O
r------------------------II
EN
LOWV
I
<+ 12V
80C51
Xl
J~z
D
I
ADO-7
XO
ALE
A15
RD
WR
VPA
I
(
INS820
+12V
vcci
E
,~,
., I
+ 12VTO
;~E RBIAS~
RD
SPINDLE
MOTOR
AGND
WR
A
-----qINT
FPl
SE3
RESET
0.1 ~ F
,l::.
0,
to
~l'
IN -
SERVO 0.1 ~ F
READ HEAD
Cl
"w;n
C vco
CBYP
. . .,. .
~
SYNC
VCO
I
I
I
H- BRIDGE
MOTOR
DRIVER
OUTA
FP2
I
OUTB
.,
N
a
If------+------------,
::~ I
----1>-,
t-I
I VDD
I DGND
PREAMPLIFIER
,
,
VCC
GND
>
I
ADO-7
INT
+5V
VPD
\f!
VEL
FP4
~I
SYNC
CLOCK FP3
OUTC
-~-~
-------------------~
t-.
1-1
VEL-
CLD
FV4
CAl.
t - I- - - . - - - - ,
CAGC
C2
CPK
~,
CAD
BPl
BP2
FV2
I , •
FV3
I
•
VWL -1,>----t--------,
SOUT
'f'f'{'---'
+5V
SSl32H568
ERR
RBRK
TW
RW~
T"WI
LF
FVl
EOUT
SSl32H567
RIN
I
CL3
SSI32H569
I ERR -
JW'
BRK
LOOP COMPENSATION
AGND
RVCO VREF
RL2
,-------1
VREF
TO SPINDLE MOTOR
BRAKING TRANSISTOR
ERR +
VREF
CJ)
(\)
ROS
SERVO
DEMODULATOR
SERVO
MOTOR DRIVER
SERVO
CONTROLLER
CBYP
9
<
OCJ)
OCJ)
0~W
-I\)
""I::J:
FIGURE 7: COMPLETE EXAMPLE OF SERVO PATH ELECTRONICS USING SSI 32H567/568/569 CHIP SET
2.U1
(\)en
""IClO
SSI32H568
Servo Controller
Servo Motor and Driver
For the purposes of illustration, the following simple
model for the servo motor in figure 7 is assumed.
J8 d ro
.
Im=-oKm dt
e=Kmoro
Definition of terms:
im
Armature current (A)
ro
Motor speed (rad/s)
J9
Rotor moment of inertia (kg· m2)
Km Torque constant (V • s)
e
Motor back EMF (V)
Lm Winding inductance (H)
Rm Winding resistance (Ohm)
Under the assumption that the electrical and mechanical poles ofthe motor above are widely separated (RmI
Lm » J9 • RmlKm2), the servo driver loop compensation components, RL2 and CL3, may be chosen to
cancel the effect of Lm, as follows:
CL3
68 Rs
, RL2
Lm
21tRF (Rm+Rs}BW
CL3( Rm+Rs)
where BW is the desired servo driver open loop bandwidth (Hz). This results in the following relationship
between motor current (im) and error voHage at the
servo controller output (EOUT).
_i_m_ (s)=
-RF
EO U T
----:-(~-s-..,..)
4 R in Rs 1 + - - 2ltBW
This simple first order approximation ofthe servo motor
behaviour neglects effects such as resonance due to
the motor inductance, Lm, or the pole due to servo
driver transconductance. However, it is sufficient to
illustrate the design goals for the velocity and position
loop filters that are required with the SSI 32H568. A
more detailed description of the SSI 32H569 may be
found in the SSI 32H569 data sheet.
TRACK MODE
Loop Compensation
Track mode is engaged when the head has reached its
destination and the current position must be maintained. The control objective is to drive the position
error signal at FP1 to zero and minimize excursions of
the head due to noise and other perturbations of the
system. The transfer function of the complete servo
loop in track mode is shown in figure 8(a), using the
servo motor model derived above. The gain G1 is the
combined effect of the SSI 32H567 and the front end
gain of the SSI 32H568, and has a nominal value of 6
volts/lrack. The gain G2 is a property of the head
transport system, and has units of tracks/radian for
rotary servo motors and tracks/meter for linear motors.
(The nomenclature chosen for the motor model is that
of rotary motors but the results are applicable to linear
motors as well, if appropriate units are substituted). To
ensure that the control loop has negative feedback,
positive motor current (as indicated in figure 7) must
resuH in negative motor acceleration. This inversion is
accomplished in the prerecorded servo pattern and is
accounted for in the transfer function by showing G2 to
be negative.
Since the servo driver/motor combination has a double
pole at the origin and an additional real pole at frequency BW (which is selectable with external components in the SSI 32H569), the position loop filter is
essential to ensure a stable system. The effect of the
position filter used in this example is to provide lag-lead
compensation. Systems of this type are usually designed by trial and error, but a further simplification of
the transfer function may be made to obtain an initial
solution. If the pole at BW is ignored, RP4 is removed
and RP2 made large (RP2 is necessary to provide a DC
path for leakage current at pin FP2) then the system
illustrated in figure 8(b) is obtained. The compensation
has been reduced to lead compensation only. If the
following quantities are defined:
PM = Desired closed loop phase margin (degrees)
FB = Desired open loop unity gain bandwidth (rad/s)
then appropriate values for the time constants of the
lead compensation circuit (T1, T2) may be chosen
using the following relationships, assuming 1fT2« FB
«1fT1 :
FB
=Gtot ° T 2( rad/s)
PM=90-arctan(FB oT 1
4-60
)
(degrees)
0888
SSI32H568
Servo Controller
The values for Tl and T2 thus chosen form a starting
point for the selection of appropriate values for the
more complex lag-lead compensator required by the
real system.
Position Loop Filter Initialization
Offset cancellation
The position error path in the servo loop is DC coupled
and can be affected by offset voHages internal to the
SSI 32H568, especially during a transition from seek
to track mode. The following procedure may be used to
cancel out any offsets in the position error path:
Switch S1, which is controlled by the DUMP bit in the
WINDOW, register, may be used to short out the
external feedback capacitor CP2, discharging it. S1 is
usually closed during seek a operation, so that when
the system is switched to track mode no sudden
transients occur due to charge stored on CP2. Disturbances to the position signal when the system is
switching to track mode can greatly extend the disk
drive's access time, since the system response is
much slower in this mode.
DESIRED
TRACK (= 0)
1) Set TIS. (Enter track mode).
Set both the CAL and DUMP bits. (This switches
the N and inputs to VREF and shorts out CP2).
3) Set NOS=O. (This sets the offset DAC magnitude
to zero).
4) Copy the ERSGN bit to SOS. (If the offset causes
EOUTto be negative, then it is necessary to make
the input of inverting amplifier A1 more negative,
and vice versa).
2)
POSITION LOOP FILTER
a
SSI 32H569 AND SERVO MOTOR
RF
1
-~.~
HEAD
POSITION
(TRACKS)
EOUT
(V)
FPl
(V)
ROTOR POSITION
WHERE:
Tl =Cp1 • Rpl
14------' T2 = Cp2 • Rp3
(rad)
a=l+RP2
HEAD TRANSPORT
MECHANICS
Rpl
b=1+Rp4
Rp3
FIGURE 8(a): SYSTEM JRANSFER FUNCTION IN TRACK MODE
FIGURE 8(b): SIMPLIFIED TRACK MODE TRANSFER FUNCTION
0888
4-61
SSI32H568
Servo Controller
5) Increase NOS in steps of one LSB until ERSGN
changes sign. At this point the position error offset
will have been cancelled to the greatest extent
possible.
6) Clear both DUMP and CAL to resume normal track
mode operation.
On Track Window
The on track window comparator may be used to
monitor the positioning accuracy of the head. The
position error voltage at pin FP1 is compared to a signal
selected by the bits NWO-2 in the WINDOW register.
The ONTRK bit in register STATUS is set if the position
error is within the specified limits and cleared if it is
outside the limits (in either the positive or the negative
direction). The programmable excursion limits (expressed as a percentage of a track) range from 2.8% to
22.5% in 8 equal steps. By monitoring the ONTRK bit,
the microprocessor can determine when the head has
settled sufficiently for read and write operations to
commence. The ONTRK bit may also be used to
decide when it is appropriate to switch from seek to
track mode at the end of a period of decceleration.
SEEK MODE
Velocity Profile
The velocity profile that results in the shortest seek
time, subject to motor current and head velocity limitations, is as follows:
1) Maximum acceleration (maximum motor current)
until the half-way point or maximum velocity is
reached.
2) Constant velocity motion until it is time to commence decceleration (if maximum velocity was
reached).
3) Maximum decceleration until head comes to rest
over the destination track. The decceleration period is of approximately the same duration as the
acceleration period.
The microprocessor computes a velocity profile according to the rules above, based on the current head
location and destination track. During the final approach to the destination track, updates to the velocity
DAC become more infrequent since the track crossing
rate is approaching zero. The fill signal which is derived
from the position error can be used to provide a smooth
target velocity profile between track crossing updates.
Figure 9 shows a set of typical waveforms as the head
approaches the destination track. The fill gain is adjusted at each track crossing so that the fill signal
interpolates smoothly between target DAC settings. In
the destination track, where the target DAC output is
zero, the fill signal is especially important, since it
becomes zero only when the head is centered on the
track. The velocity control loop thus causes the head to
come to rest at the center of the destination track.
Loop Compensation
The transfer function for the controller electronics of
figure 7 is shown in figure 10(a). This transfer function
may be simplified as shown in figure 1O(b), under the
following conditions: 2
IGG 1 G2 )(Km Rxl
ro > > .!.--_--I....l.-_....!..
J6 Rva
R
C
V4
_
J6 roRva
Vl-(GG 1 G2 j(K m Rx)
where Rx is RVl (ACCIN=O) or RV111Rv2 (ACCIN=1)
The value of ro, the corner frequency of the internal
position differentiator, is dependent on the sync rate,
but the above condition is generally satisfied by most
systems. The condition on RV4 and CV1 sets the
position of the zero due to the external components in
the velocity loop filter, whose function is described
below. The resulting system has two real poles, one
of which is at the origin, and is thus unconditionally
stable.
The position of the SSI 32H568 internal differentiator
pole is selectable under microprocessor control. It is
desireable to select as Iowa frequency as is consistent
with the required seek performance. This pole prevents the differentiatorfrom amplifiying high frequency
noise. In order to provide feedback ofa velocity signal
for frequencies above the differentiator pole, the external velocity loop filter is configured to act as an integrator which integrates the motor current sense output of
the SS132H569, SOUTo Since SOUT is proportional to
motor acceleration, this integration produces a signal
proportional to velocity. Thus, at low frequencies the
velocity feedback is generated by differentiating the
position error signal and at high frequencies, the velocityterm results from integrating motorcurrent.ltis more
accurate to estimate velocity from a direct observation
of head poSition, but at higher frequencies it is necessary to provide increased noise immunity. The system
described above balances these two considerations.
4-62
0888
SSI32H568
Servo Controller
HEAD ENTERS
(DESTINATION TRACK
VELOCITY
SIGNAL
,,
,VELOCITY
,
, TARGET DAC'
~'/
'
TARGET DAC
& FILL SIGNAL
/
VREF
TIME
,:~VELOCITY ESTIMATE (FVI)
POSITION
SIGNAL
FILL SIGNAL
"
/
VREF
" - POSITION ERROR (FPI)
FIGURE 9: TYPICAL WAVEFORMS DURING FINAL DECELERATION MODE
0888
4-63
SSI32H568
Servo Controller
SSI 32H569 AND MOTOR
VT
+:
EOUT
RF
1
-~. ~ f - - - - - - - - - - - - - - < p - + im
(VELOCITY
TARGET
VOLTAGE)
VELOCITY LOOP FILTER
Rw
RY3
MOTOR
DYNAMICS
DIFFERENTIATOR
-G
1 +sCY1 RY4
Rx = { RYl
RY1/1RV2
ACCIN = 0
ACCIN = 1
FIGURE 10(8): TRANSFER FUNCTION OF SSI 32H568 IN SEEK MODE
of:;
-
RF
4R in Rs
.
C V1
• Rx
1
1
1+
B"w
.S
FIGURE 10(b): SIMPLIFIED TRANSFER FUNCTION OF SS132H568IN SEEK MODE
2
CJ)
I1
(GG 1 G 2 K m R x)
> >.:--~---
J9
RV3
4-64
0888
SSI32H568
Servo Controller
(a) MAGNllUDE
(a) MAGNITUDE
I S10PEN I
LOOP
GAIN
(dB)
LOOP
GAIN
(dB)
Y
'(, :
S1 CLOSED
(DUMP-1)
OdB
OdB
FREQUENCY
(rad/s)
FREQUENCY
(b) PHASE
(b) PHASE
LOOP
PHASE
SHIFT
(DEGREES)
LOOP
PHASE
SHIFT
(DEGREES)
1
12
FB
FREQUENCY
(radls)
FREQUENCY
(radls)
S1 CLOSED
-90 •
1
.go'
_ _ _ _ _ _ _ L_
-180'
-180 •
S10PEN
FIGURE 11: BODE PLOT OF SIMPLIFIED TRACK
MODE TRANSFER FUNCTION
0888
4-65
FIGURE 12: BODE PLOT OF SIMPLIFIED SEEK
MODE TRANSFER FUNCTION
SSI32H568
Servo Controller
PACKAGE PIN DESIGNATIONS
CAUTION: Use handling procedures necessary
for a static sensitive component.
(TOP VIEW)
FV4
VPA
FV3
VPD
FV2
CLOCK
FV'
SYNC
EOUT
ADO
FP3
FV1
7
39
ADO
NiC
8
38
AD1
EOUT
9
37
A02
10
36
A03
AD4
AD'
AD2
FP2
FP3
FP'
A03
FP4
11
35
a
AD4
FP2
12
34
AD5
A05
FP1
13
33
NlC
RBIAS
A06
o
14
32
ADS
VREF
ADJ
N
15
31
A07
AGND
iNf
RBIAS
16
30
TiS
VREF
17
29
iff
Co
VDD
ALE
DGNO
Ali
ViR
32·Pin DIP
44-Pin PLCC
ORDERING INFORMATION
PART DESCRIPTION
ORDER NO.
PKG.MARK
SS132H568, Servo Controller
32-Pin DIP
SSI 32H568-CP
32H568-CP
44-Pin PLCC
SSI 32H568-CH
32H568-CH
No responsibility is assumed by SSi for use of this product nor for any infringements of patents and trademarks or other rights of third parties
resulting from its use. No license is granted under any patents, patent rights or trademarks of SSi. SSi reserves the right to make changes
in specifications at any time without notice.
Silicon Systems, Inc., 14351 Myford Road, Tustin
©1988 Silicon Systems, Inc.
CA 92680, (714) 731-7110, TWX 910-595-2809
0888
4-66
SSI32H569
Servo Motor Driver
INTEGRATION
August, 1988
DESCRIPTION
FEATURES
The SSI32H569 Servo Motor Driver is a bipolar device
intended for use in Winchester disk drive head positioning systems employing linear or rotary voice coil
motors. When used in conjunction with a position
controller, such as the SSI 32H568 Servo Controller,
and a position reference, such as the SSI 32H567
Servo Demodulator, the device allows the construction
of a high performance, dedicated surface head positioning system.
•
Predrlver for linear and rotary voice coli motors
•
Interfaces directly to MOSFET H-Brldge motor
driver
•
Class B linear mode and constant velocity
retract mode
•
Precision differential amplifier for motor current sensing
The SSI 32H569 serves as a transconductance amplifier by driving 4 MOSFETs in an H-bridge configuration, performs motor current sensing and limits motor
current and velocity. In its linear tracking mode, class
B operation is guaranteed by crossover protection circuitry, which ensures that only one MOSFET in each
leg of the H-bridge is active. The MOSFET drivers are
disabled when motor velocity or current exceed externally programmable limits. In addition, automatic head
retraction and spindle braking may be initiated by a low
voltage condition or upon external command.
•
•
•
•
Motor current and velocHy limiting clrcuHry
Automatic head retract and spindle braking
signal on power failure
External digital enable
Servo loop parameters programmed with external components
•
Advanced bipolar IC requires under 240 mW
from 12V supply
•
Available In 20-pln DIP or SO packaging
(Continued)
BLOCK DIAGRAM
SOOT
SE'
E'"
OUTU
E... ·
E....
Vl£F
OOTD
vt ..
OOTe
"'"
GND
0888
4-67
SSI32H569
Servo Motor Driver
DESCRIPTION (Continued)
The SSI32HS69 is implemented in an advanced bipolar process and dissipates less than 240 mW from a
12V supply. The IC is available in 20-pin DIP and
20-pin SO packaging.
FUNCTIONAL DESCRIPTION
(Refer to block diagram and typical application Fig.2)
The SSI 32HS69 has two modes of operation, linear
and retract. The retract mode is activated by a power
supply failure or when the control signal EN is false.
Otherwise the device operates in linear mode.
During linear operation, an acceleration signal from the
servo controller is applied through amplifier A1, whose
three connections are all available externally. RC
components may be used to provide loop compensation at this stage. The ERR signal drives two precision
amplifiers, each with a gain of 8.S. The first of these
amplifiers is inverting, and is formed from opamp A4,
an on-chip resistor divider and an off-chip complementary MOSFET pair. The second is non-inverting, and is
formed in a similar manner from opamp AS. Feedback
from the MOSFET drains, on sense inputs SE1 and
SE3, allows the amplifiers gains to be established
precisely. The voice coil motor and a series current
sense resistor are connected between SE1 and SE3.
Crossover protection circuitry between the outputs of
A4 and AS, and the external MOSFETs, ensures class
B operation by allowing only one MOSFET in each leg
of the H-bridge to be in conduction. The crossover
separation threshold, illustrated in Figure S, is the
maximum drive on any MOSFET gate when the motor
voltage changes sign. The crossover circuitry can also
disable all MOSFETS simultaneously (to limit motor
current or velocity) or apply a constant voltage across
the motor (to retract the heads at a constant velocity).
actual motor acceleration. If SOUT is integrated, using
opamp A3 and an external RC network, the resulting
signal, VEL, is proportional to the motor velocity.
Both SOUT and VEL are connected to window comparators, which are used to detect excessive motor
current or velocity. The comparator outputs disable the
MOSFET drivers until the motor comes within limits
again. The VLlM pin may be used to program the
voltage limits for the window comparators. The maximum voltage excursion allowed about VREF is (VREFVLlM). An on-Chip resistor divider sets a default value
for VLlM and if VLlM is connected to ground, the
windowing is effectively disabled.
The SSI 32HS69 has low voltage monitor circuitry that
will detect a loss of voltage on the VREF, VCC or
LOWV pins. The power supply pin, VCC, should be
connected to the disk drive's spindle motor so that its
stored rotational energy may be used to hold up VCC
briefly during a power failure. LOWV is used to detect
a system power supply failure. When a low voltage
condition is detected, the MOSFET drivers switch from
linear operation to retract mode. In this mode a constant voltage is applied across the motor which will
cause the heads to move at a constant speed. A
mechanical stop must be provided for the heads when
they reach a safe location. The current limiting circuitry
will disable the MOSFET drivers when motor current
increases due to loss of the velocity-induced back
EMF. An open collector output, BRK, which is active
while the device is in retract mode, is provided for
spindle motor braking. An external RC delay may be
used to defer braking until the heads are retracted. For
proper operation of the SSI 32HS69, a pullup resistor
on BRK is required even if the BRK output is not used.
An example of an entire servo path implemented with
the SSI 32HS69 and its companion devices, the
SSI 32HS67 and 32HS68, is shown in Figure10.
Motor current is sensed by a small resistor placed in
series with the motor. The voltage drop across this
resistor is amplified by a differential amplifier with a
gain of 4 (A2 and associated resistors), whose inputs
are SE1 and SE2. The resulting voltage, SOUT, is
proportional to motor current, and hence acceleration.
This signal is externally fed back to A1, so that the
signal ERR represents the difference between the
desired acceleration (from the servo controller) and the
4-68
0888
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Cv
VELOCITY!
CURRENT
UMIT
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4"
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DISABLE DRfVERS
VREF~
FORCED RETRACT
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TO SPINDLE MOTOR
BRAKNG TRANSISTOR
"BIlK
"V
vee
(TOMOTORD",VER)~
en
CD
TO SPINDLE MOTOR
~
1
o
==en
2.
en
0~
FIGURE 2: TYPICAL APPLICATION
W
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<01
CDol
--
~CD
SSI32H569
Servo Motor Driver
PIN DESCRIPTION
POWER
NAME
PIN
TYPE
DESCRIPTION
VCC
20
LOWV
19
I
LOW VOLTAGE - System 12V supply.lfthis input falls below 9V, a forced
head retraction occurs.
VREF
4
I
REFERENCE VOLTAGE - 5.4V input. All analog signals are referenced
to this voltage. If VREF falls below 4.3V, a forced head retraction occurs.
GND
10
POSITIVE SUPPLY -12V power supply. Usually taken from spindle motor
supply. Spindle motor stored energy permits head retraction during power
failure. If VCC falls below 9V, a forced head retraction occurs.
GROUND
CONTROL
NAME
PIN
TYPE
DESCRIPTION
ERR
1
0
POSITION ERROR- Loop compensation amplifier output. This signal is
amplified by the MOSFET drivers and applied to the motor by an extemal
MOSFET H-bridge, as follows:
ERR-
2
I
POSITION ERROR INVERTING INPUT - Inverting input to the loop
compensation amplifier.
ERR+
3
I
POSITION ERROR NON-INVERTING INPUT - Non-inverting input to the
loop compensation amplifier.
SOUT
5
0
MOTOR CURRENT SENSE OUTPUT - This output provides a voltage
proportional to the voltage drop across the external current sense resistor,
as follows:
SE3-SE1 = 17(ERR-VREF)
SOUT-VREF=4(SE2-SE1 )
VEL-
6
I
VELOCITY INVERTING INPUT -Inverting inputtothevelocity integrating
amplifier. The non-inverting input is connected intemally to VREF.
VEL
7
0
VELOCITY OUTPUT - Output of the velocity integration amplifier. This
signal is internally applied to a· window comparator whose output limits
motor drive current when the voltage at VEL exceeds a set limit.
BRK
8
0
BRAKE OUTPUT - Active high, open collector output which may be used
to enable an external spindle motor braking transistor upon power failure
or deassertion of EN.
VLlM
11
I
LIMITING VOLTAGE - The voltage at this pin sets motor current and
velocity limits. Limiting occurs when:
or
ISOUT-VREFI>VREF-VLlM
IVEL-VREFI>VREF-VLlM.
An internal resistor divider establishes a default value that may be
externally adjusted.
4-70
0888
SSI32H569
Servo Motor Driver
CONTROL (Continued)
NAME
PIN
TYPE
DESCRIPTION
SE2
14
I
MOTOR CURRENT SENSE INPUT - Non-inverting input to the current
sense differential amplifier. It should be connected to one side of an
external current sensing resistor in series with the motor. The inverting
input of the differential amplifier is connected internally to SE1.
EN
18
I
ENABLE - Active high TTL compatible input enables linear tracking mode.
A low level will initiate a forced head retract.
PIN
TYPE
9
I
MOTOR VOLTAGE SENSE IN PUT - This input provides feedback to the
non-inverting MOSFET driver amplifier. It is connected to one side of the
motor. The gain to this point is:
OUTC
12
0
P-FET DRIVE (NON-INVERTING) - Drive signal for a P channel MOSFET
connected between one side of the motor and VCC. This MOSFET drain
is connected to SE3.
OUTD
13
0
N-FET DRIVE (NON-INVERTING) - Drive signal for an N channel MOSFET
connected between one side of the motor and GND. This MOSFET drain
is connected to SE3. Crossover protection circuitry ensures thatthe P and
N channel devices driven by OUTC and OUTD are never enabled
simultaneously.
SE1
15
I
MOTOR VOLTAGE SENSE INPUT - This input provides feedback to the
inverting MOSFET driver amplifier. It is connected to the current sensing
resistor which is in series with the motor. The gain to this point is:
FET DRIVE
NAME
SE3
DESCRIPTION
SE3-VREF = 8.5(ERR-VREF)
SE1-VREF = -8.5(ERR-VREF)
This input is internally connected to the current sense differential amplifier
inverting input.
OUTB
16
0
N-FET DRIVE (INVERTING) - Drive signal for an N channel MOSFET
connected between the current sense resistor and GND. This MOSFET
drain is also connected to SE1.
OUTA
17
0
P-FET DRIVE (INVERTING) - Drive signal for a P channel MOSFET
connected between the current sense resistor and VCC. This MOSFET
drain is also connected to SE 1. Crossover protection circuitry ensu res that
the P and N channel devices driven by OUTC and OUTD are never
enabled simultaneously.
0888
4-71
SSI32H569
Servo Motor Driver
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
(Maximum limits indicates where permanent device damage occurs. Continuous operation at these limits
is not intended and should be limited to those conditions specified in the DC operating characteristics.)
PARAMETER
MIN
CONDITIONS
TYP
MAX
UNITS
VCC
0
16
V
VREF
0
10
V
All other pins
Storage temperature
Solder temperature
0
14
V
-45
165
°C
260
°C
10 sec duration
RECOMMENDED OPERATION CONDITIONS (Unless otherwise noted, the following conditions are valid
throughout this document.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VCC
Normal Mode
9
12
13.2
V
Retract Mode
3.5V
14
V
VREF
5
7
V
Operating temperature
0
70
°C
20
rnA
2
rnA
DC CHARACTERISTICS
ICC, VCC current
IREF, VREF current
A1, LOOP COMPENSATION AMPLIFIER
Input bias current
Input offset voHage
VoHage swing
500
nA
3
mV
AboutVREF
2
Common mode range
AboutVREF
±1
V
Load resistance
To VREF
4
Kn
Load capacitance
V
100
Gain
Unity gain bandwidth
pF
80
dB
1
MHz
CMRR
1<20 kHz
60
dB
PSRR
f<20 kHz
60
dB
4-72
0888
SSI32H569
Servo Motor Driver
A2, CURRENT SENSE AMPLIFIER
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Input impedance
SE1 to SE2
3.5
5
2
mV
VREF-4
VCC-1.2
V
0
VCC-O.2
Input offset voltage
Output voltage swing
Common mode range
Load Resistance
ToVREF
4
100
1<40 KHz
Gain (SOUT-VREF)/(SE1-SE2)
V
Kn
Load Capacitance
Output impedance
Kn
4
3.9
pF
20
n
4.1
VN
1
MHz
CMRR
1<20 KHz
52
dB
PSRR
f<20 KHz
60
dB
Unity gain banclwidth
A3, VELOCITY INTEGRATING AMPLIFIER
PARAMETER
CONDITIONS
MIN
TYP
Input bias current
Common mode range
Load resistance
ToVREF
UNITS
250
nA
2
mV
VREF-4
VCC-1.2
V
4.5
6
V
Input offset voltage
Voltage swing
MAX
Kn
10
Load capacitance
RB, internal feedback resistor
80
100
pF
150
Kn
MAX
UNITS
65
%
WINDOW COMPARATORS AND LIMITING
PARAMETER
CONDITIONS
MIN
Window comparator threshold
(SOUT-VREF or VEL-VREF)
VREF-VLlM
Threshold hysteresis
VLlM voltage
35
No extemal parts
VLlM input resistance
0888
TYP
VREF-l.8
50
4-73
50
V
VREF-2.2
V
Kn
I
SSI32H569
Servo Motor Driver
POWER SUPPLY MONITOR
PARAMETER
CONDITIONS
VCC fail threshold
LOWV fail threshold
IILowvl < 0.5 mA
VREF fail threshold
MIN
TYP
MAX
UNITS
8.5
9
9.8
V
8.5
9
9.8
V
4.3
4.8
3.9
V
Hysteresis (LOWV, VCC)
250
mV
Hysteresis (VREF)
110
mV
EN input low voltage
0.8
IIILI< 0.5mA
EN input high voHage
IIIHI <40uA
BRKvoHage
BRK leakage current
V
2
V
normal mode, IIOLI < 1 rnA
0.4
V
retract mode
10
J.1A
1
ms
MAX
UNITS
BRK delay (from power fail or
EN false to BRK floating)
MOSFET DRIVERS
PARAMETER
CONDITIONS
SE31nput impedance
ToVREF
MIN
TYP
10
25
KO
OUTA,OUTC
voHage swing 1101<1 rnA
0.7
VCC-1
V
OUTB,OUTO
voltage swing 1101<1 rnA
1
VCC-1
V
2
V
VTH,
Crossover separation threshold
Slew rate
(OUTA, OUTB, OUTC, OUTO)
CI<1000 pF
Crossover time
300 mV step at ERR
V/~
1.4
5
~
Output impedance (OUTA,B,C,O)
50
KO
Transconductance
I(OUTA,B,C,O)/(ERR-VREF)
8
mAN
Gain (-(SE1-VREF)/(ERR-VREF)
or (SE3-VREF)/(ERR-VREF) )
Offset current
8
8.5
Rs = 0.20, RF = RIN,
VIN=VREF
Retract motor voHage
(SE1-SE3)
0.7
4-74
1
9
VN
20
mA
1.3
V
0888
SSI32H569
Servo Motor Driver
APPLICATIONS INFORMATION
LOOP COMPENSATION
A typical SSI32H569 application is shown in Figure 2.
The selection criteria for the extemal components
shown are discussed below. Figure 3 shows the
equivalent circuit and equations forthe DC motor used
in the following derivations. While the nomenclature
chosen is for a rotating motor, the resuHs are equally
applicable to linear motors.
The transfer function of the SSI32H569 in the application of Figure 2 is shown in figure 4(a). If the zero due
to RL and CL in the loop compensation circuit is chosen
to cancel the pole due to the motor inductance, Lm,
then the transfer fu nction can be simplified as shown in
figure 4(b), underthe assumption that this pole and the
pole due to the motor mechanical response are widely
separated. CL may then be chosen to set the desired
open loop unity gain bandwidth.
MOTOR CURRENT SENSE AND LIMITING
where BW is the
unity gain open
loop bandwidth
The series resistor which senses motor current, Rs, is
chosen to be small compared to the resistance of the
motor, Rm. A value of Rs = 0.20 is typical in disk drive
applications. The window comparator threshold, programmed by VLlM, must be chosen to cause limiting
when the motor current reaches its maximum permissible value. If iMAX is the maximum motor current in
Amps, then this value may be chosen as follows:
VLlM = VREF -4· Rs· iMAX (V)
VLlM may be set with a resistor divider whose thevenin
resistance is substantially less than the output resistance of the VLlM pin (50 Kn). The window comparators have hysteresis (typically 50% of their threshold,
VREF-VLlM) to prevent muHiple triggerings of the
driver disable signal.
The closed loop response of the servo driver and motor
combination, using the component values and simplifying assumptions given above, is given by:
~(S)= __1_" __R_F_" ___________
Vln
Rin 4· Rs (1 +
s
)
2"1t"BW
(ThiS analysis neglects the pole due to the output
impedance of the MOSFET drivers and the MOSFET
gate capacitance, an effect that may be significant in
some systems).
VELOCITY LIMITING
The values of Rv and Cv in the velocity integrator are
chosen to produce a voHage excursion of VREF-VLlM,
when the motor speed is at its maximum permissible
value. Rv must be large enough to prevent overloading
of opamp A2. The following equation ignores the effect
of RB, the intemal resistor between VEL and VELwhich prevents saturation of A3 due to offsets. For the
motor in Figure 3, with maximum velocity ooMAX
(radls) these components may be chosen as follows:
Rvl/ RF > 4Kn
C v=
(A20u~utloadingres1riction)
4R s ·J9"ooMAX
(VREF-VLlM)" R v " Km (F)
RF is chosen to be sufficiently large to avoid overloading A2 (RF /I Rv > 4Kn). The input reSistor, RIN, sets the
conversion factor from servo controller output voHage
to servo motor current. RIN is chosen such that the
servo controller intemal voltages are scaled conveniently. The resistor Ros is optional and cancels out the
effect of the input bias current of Ai.
The extemal components Ro and Co have no effect on
the motor dynamics, but may be used to improve the
stability of the MOSFET drivers. The load represented
by the motor, ZM, is given by:
L
K
2
ZM=(Rs+Rm)(1+s--m-)(1+
m
)(0)
Rs+Rm
S "J9" (Rs+Rm)
0888
4-75
SSI32H569
Servo Motor Driver
At frequencies above (Rs+Rm)/(2 on Lm) Hz, this load
becomes entirely inductive, which is undesireable. Ro
and Co may be used to add some parallel resistive
loading at these frequencies.
0
H-BRIDGE MOSFETS
The MOSFETs chosen for the H-bridge should have
gate capacitances in the range of SOO-1000 pF. The
MOSFET input capacitance forms part of the compensationforthe MOSFETdrivers, so values belowSOO pF
may cause some driver instability. Excessive input
capacitance will degrade the slew mode performance
of the drivers.
When the motor voltage is changing polarity, the crossoverprotection circuits at outputs OUTA-OUTD ensure
that the maximum MOSFET gate drive is less than 2V
(the crossover separation threshold), as illustrated in
Figure S. The thresholds of the MOSFET devices chosen should be as large as possible to minimize conduction in this region. If the device thresholds are significantly less than the crossover separation threshold,
the Nand P channel devices in each leg of the H-bridge
will conduct simultaneously, causing unnecessary
power dissipation.
POWER FAILURE OPERATION
The power supply forthe SSI32HS69, VCC, should be
taken from the system 12V supply through a schottky
diode (maximum O.SV drop at If = 3A) and connected
to the disk drive spindle motor. If the system power
fails, the IC will continue to operate as the spindle mQtor
becomes a generator. The SSI 32HS69 will detect the
power failure and cause a forced head retract, continuing to operate with VCC as low as 3.SV. The power fail
mode will commence if eitherVCC orLOWVfalis below
9V, or VR EF falls below 4.3V, or EN is false. Hysteresis
on the low voltage thresholds prevents the device from
oscillating between operating modes when the power
supply is marginal.
The BRK output, which is pulled low during normal
operation, floats during a power failure. This allows an
external transistor to be enabled for spindle motor
braking. An external RC delay may be added to defer
braking until head retraction is complete, since the
spindle motor is required to generate the supply voltage during retraction.
im
:=
J9(1)
Km
im
Armature current (A)
(I)
Motor speed (radls)
J9
Moment of inertia of
rotor (Kg. M2 )
Km
Torque constant (V.S.)
e
Back E.M.F. (V)
Lm
Winding inductance (H)
Rm
Winding resistance ( Q
Nomenclature used is for rotary motor
FIGURE 3: EQUIVELANT CIRCUIT FOR FIXED FIELD DC MOTOR
4-76
0888
SSI32H569
Servo Motor Driver
WINDING IMPEDANCE
LOOP COMPENSATION
MECHANICAL RESPONSE
e
CURRENT SENSE
FIGURE 4(A): TRANSFER FUNCTION OF 551 32H569
IN TYPICAL APPLICATION WITH FIXED FIELD DC MOTOR
LOOP COMPENSATION
MECHANICAL RESPONSE
~ _~
/1
RIN
I
1
"'+
/)K-
'"
1
..
/
1+
SJ9
17
""
/
Km2
(As + Rml
SCL(R.+ Rm l
CURRENT SENSE
R.
RF
/'
4 -
J8Rm
-- «
Km 2
"
Rm
Lm
FIGURE 4(8): SIMPLIFIED TRANSFER FUNCTION OF 551 32H569
IN DC MOTOR APPLICATION
0888
4-77
"/
SSI32H569
Servo Motor Driver
M06FETGATE DRIVE
_____________ J ________
vee -
VCC-VTH
_
VTH
_
(CROSSOVER
~~~~
~
____ _
I
~o~
__
____________________~_____________________ _ +
ERR
(ERAORSIONAL INPUT)
(HORIZONTAL SCALE IS GREAn.v EXPANDED)
FIGURE 4(8): SIMPLIFIED TRANSFER FUNCTION OF 551 32H569
IN DC MOTOR APPLICATION
RVLIM
RVLlM
(n)
(0)
1 MEG +-.-T--'IrT-r--.--.-r-r-r--r--,--,-,.--,
-1- t- + -I -1- t- + -I -1- t-
'I
_1_ L .1 J _'- L.l J _1_ L
I I
I I
-1-1-'-1
500K
-,- r
-1- I-
I
1
-1-'
T -, -,
T.
+
-I -1-
~ -I
_1_ L .l J _1_ L
I
I
I
I
I
~I
Rs =.501
I
-I I~I_L
I
-'-I T -, -,- II -,
lOOK
-,- r
T -, -,-
r
-1- I- .... -I -1- I-
I
I
-I
I
200K
r
1- I-
.l J _1_ L
1
I
I
I
- ,- T -, -,- ,-
T -, -,-
+
+
I
.'-
-I -1-
T -, - , -
1-....
lOOK
r
-1- I-
-~~~~~~rTT
_1_ L .l J _1_ L .l J _1_ L.l J __
I
I
I
I
I
I
I
I
I
I
I
I
I
-I-I-I-t-t-t-r
I
-~~~~h
-~~
4
5
6
~~4~~-
"""1-1-1--;-1-
~+++~~~~~-
~~~+++444~~-
7
2
I MAX
(AMPS)
o
FIGURE 6: RVLlM TO GROUND
TYPICAL MOTOR CURRENT LIMIT
3
4
'MAX
(AMPS)
FIGURE 7: RVLlM TO VREF
TYPICAL MOTOR CURRENT LIMIT
4-78
0888
SSI32H569
Servo Motor Driver
------
ASSUMPTIONS:
-
-
1
-1- _ _ _ _ _ _ _
-1K
R. =0.20
RF = 10K
CL
(I1F)
RL
(0)
Rm=30
L m =6001'1i
1
-1- -
.100
-
-
-
-
--
-10
.010
1K
100
100K
10K
BANDWIDTH
(Hz)
FIGURE 8: TYPICAL MOTOR DRIVER COMPENSATION
1.7
- - I- I
-1- - -I 1
-
+- - -
I- -
-1
I
Ay
.10KO
Km
_.Slbs/amp
M... _ .00026 SLUG
I
I
: I tUff
I ....rr
I
1- 4~
_ VUM
'A,
I
.1
-100
I/RL
CL ' "
-
- I- - -1- - --I - -
I
+- - -
1- - -1- -
--I -
-
1
30
GO
100
FIGURE 9: TYPICAL MOTOR VELOCITY LIMIT
0888
4-79
EN
po.o
80C51
~
-L
Xl
M)O·7
r
~
'l
XO
ALE
A15
VCC
VPA
RBIAS
AGND
RD
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WR
WR
INT
INT
1
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+1
RW
N
Q
Q
IN+
SYNC
IN.
VCO
CLD
-
Cl
CAZ
CAGe
-
C2
CPK
:..~
VPA
CM)
=u
TW
BPI
SP2
LF
SERVO
OEMODULATOR
T
OUTB
::ERp4
~
VELOCITY
INTEGRATOR
f---1~
~~
~- ~ ~l~
III
VOICE COIL
~
~I
1m
f
VEL
~L~
FV2
_\':, r "~
FV3
SSl32H!1118
FVl
1f-cL2
III
:E RV3
f-
EOUT
RV2
RIN
::
SOUT
III
III
1
If-
RL2 CL3
All
III
I
+5V
RF
ERR
: j : RSRK
8813211568
ERR·
BRK
LOOP COMPENSATION
~'- ~~~~~~STh'foR
ERR+
VREF
VREF
RVCO VREF
VEL·
RV4::j: f C V1 R
III VI
f---1~
hJ~
>--
AGND
~
1
----0,11
R.
Rv=E
~~
::E ROS
1
SERVO
CONTROLLER
SERVO
MOTOR
DRIVER
-
CSVP
-W
FIGURE 10: COMPLETE EXAMPLE OF SERVO PATH ELECTRONICS USING THE SSI 32H567/568/569 CHIP SET
~
C
""l
H·BRIDGE
MOTOR
OUTC
VELOCITY
LOOP FILTER
FV4
0(J1
_0)
oeo
""l
Cv
T CP2
CLOCK FP3
3:%
+12VTO
SPINDLE
MOTOR
OUTO
SYNC
8813211587
cw
OUTA
FP2
FP4
~
SE2
E R P3
THR
N
CBYP
SEI
=E RP2
CP1
-----I1 FREF
Ro
°NOTE: Diode required lor regenerative braking. (three amp minimum rating)
FIGURE 2: Typical Application
0888
5-5
sec
SSI 32M590-Series
5-1/4 Inch
Motor Speed Control
PACKAGE PIN DESIGNATIONS
(TOP VIEW)
N/C
N/C
V12
OUTB
N/C
OUTA
SENSE
N/C
N/C
N/C
N/C
V12
OUTB
OUTA
SENSE
N/C
FREF
F R E F 0 8 V12
HALLOUT 2
7 OUTB
HALLIN 3
6 OUTA
5 SENSE
GND 4
SSI32M5901
8-Pin PDIP
SSI32M5902
14-Pln PDIP
N/C
HALLIN
N/C
GND
START
SSI32M5902
16-Pin SOL
ORDERING INFORMATION
PART DESCRIPTION
ORDERING NUMBER
PACKAGE MARK
SSI 32M590-Series
S-Pin PDIP
SSI 32M5901-CP
SS132M5901-CP
14-Pin PDIP
SSI 32M5902-CP
SSI 32M5902-CP
16-Pin SOL
SSI 32M5902-CL
SSI 32M5902-CL
No responsibility is assumed by SSi for use of this product nor for any infringements of patents and trademarks or other rights of third parties
resulting from its use. No license is granted under any patents, patent rights or trademarks of SSi. SSi reserves the right to make changes
in specifications at any time without notice.
CA 92680 (714) 731-7110, TWX 910-595-2809
Silicon Systems, Inc., 14351 Myford Road, Tustin,
©1988 Silicon Systems, Inc.
0888
5-6
SSI32M591
INNOVATORS IN INTEGRATION
Three-Phase 5-1/4 Inch
Winchester Motor
Speed Control
August, 1988
DESCRIPTION
FEATURES
The SSI 32M591 is a motor controller IC designed to
provide all timing and control functions necessary to
start, drive and brake a three-phase brushless DC
spindle motor. The IC requires three external power
transistors (such as Darlington power transistors), one
external power resistor, and an external frequency
reference. The three motor HALL sensors are directly driven and decoded by the device. The controller is
optimized for a 3600 rpm disk drive motor using a 2
Mega-Hertz clock. Motor protection features include
stuck rotor shutdown, supply and clock fault detection,
all of which are indicated by a FAULT signal, and coil
over-current detection and control. A LOCK signal is
provided to indicate that the motor is at speed. The
device's linear control loop controls the power drivers
using Pulse Amplitude Modulation.
• CMOS with TTL/LSTTL compatible control
functions
• Single +12 volt power supply
• All motor START, DRIVE, and STOP timing and
control
• Includes HALL-Effect sensor drive and Input pins
• Highly accurate speed regulation of ±.05 %
• Active braking function
• On-chip digital filtering requires no external
compensation of adjustments
• Provides protection against stuck rotor, motor
coli over-current, supply fault, or clock fault
• At speed Indication provided
PIN DIAGRAM
BLOCK DIAGRAM
VDD
SENSE
FAULT
OUTA
VDD
OUTB
OUTC
OUTA
HALl2
NlC
FREF
NlC
HALLOUT
LOCK
START
FAULT
HALL1
VSS
HALL3
OUTS
OUTC
SENSE
CAUTION: Use handling procedures necessary
for a static sensitive component.
0888
5-7
SSI32M591
Three-Phase 5-1/4 Inch
Winchester Motor Speed Control
CIRCUIT OPERATIONS
The device incorporates both analog and digital circuit
techniques to utilize the advantages of each. The
analog portion of the loop uses switched capacitor fiHer
technology to eliminate external components. The
control loop uses a Pulse Amplitude Modulation (PAM)
control scheme to avoid the switching transients and
torque ripple inherent in Pulse Width Modulation
(PWM) schemes.
PIN DESCRIPTION
SYMBOL
1/0
DESCRIPTION
I
+12V Power supply
VSS
I
Ground
FREF
I
FREQUENCY REFERENCE INPUT: A TTL compatible input used by the device to set
and maintain the desired motor speed and operate circuit blocks. This input level must
not exceed VDD at any time.
HALLOUT
0
HALL SENSOR BIAS OUTPUT: Provides a regulated bias voltage forthe Hall effect
sensors, inside the motor.
HALL1,
HALL2,
HALL3
I
HALL SENSOR INPUTS: The TTL open-collector type outputs of the motor's Hall
switches feed these inputs which have a resistor pullup to the HALLOUT bias voltage.
The HALL 1 input is used to index the control loop counter. Referto figure 1 for input
timing.
OUTA,
OUTB,
OUTC
0
DRIVER OUTPUTS: These three driver outputs drive the external power transistors,
such as TIP120 NPN Darlington power transistors shown in the typical application.
The power transistors control the motor current through the current setting resistor Re.
The motor current is V(sense)/Re. During normal operation, the driver output voHages
are adjusted as necessary to maintain the proper motor speed and drive current. Refer
to figure 1 for output timing.
I
COIL CURRENT SENSE INPUT: Senses the coil current and limits the sense voHage
to the thresholcl by limiting the drive to the extemal power transistors.
LOCK
0
AT SPEED INDICATOR OUTPUT: An open drain LSTTL compatible output that
indicates with an active low that the period of the motor is within the controller's linear
range. Because of the accuracy of the loop, the LOCK pin is a good "at speed"
indicator.
START
I
ACTIVE BRAKE CONTROL INPUT: The active brake is enabled by applying a logic
"0" to the START pin. During active braking the driver output's phasing is changed to
apply a reverse torque to the motor until the motor period drops below the reverse
shutdown speed at which time the drivers turn off the external powertransistors to deny
power to the motor. Active braking timing is shown in figure 1. Do not enable active
braking at motor speeds below 120 rpm.
FAULT
0
FAULT INDICATOR OUTPUT: Goes high when the motor is determined to be stalled,
VDD is low, or FREF clock is too slow.
NIC
-
NO CONNECTION: These pins must be left unconnected and floating.
VDD
SENSE
5-8
0888
SSI32M591
Three-Phase 5-1/4 Inch
Winchester Motor Speed Control
FUNCTIONAL DESCRIPTIONS
device will turn off all of the external power transistors
to prevent damage to the motor and the power devices.
The FAULT pin goes high in this condition.
A binary counter is preset once per motor revolution by
an index signal developed from the HALL1 input. On
the next index pulse, the remaining least significant bits
are loaded into the proportional O/A and accumulated
by a saturating accumulator. The most significant bits
are loaded into the integral O/A. The size of the accumulator and the bit locations determine the major
scaling (within a factor of two) for the gain and zero
location of the filter. To prevent overflow in the proportional O/A , the counter is decoded to detect overflow
and the proportional 01 A is saturated as needed. The
overflow also generates a boost signal used in the
summer. The range of the accumulator is larger than
the linear range ofthe proportional channel to help fiHer
small load disturbances that tend to saturate the proportional channel. The entire counter is also used to
provide a time-out feature to protect the motor and external circuitry.
Stalled Rotor Shutdown
If the delay from power onset to a positive index
transition or the time interval between successive
index transitions is greater than the prescribed time,
the device interprets this delay as a stalled rotor and
reduces the motor current to zero until such time as one
positive index transition is detected or until power is
removed and reapplied. The FAULT output goes high
when the motor is determined to be stalled.
Motor Coli Over-Current
Refer to SENSE input description. The voHage generated by motor coil current through Re is sensed as
shown in the typical application. The sense input
threshold limits the maximum coil current.
FREF Clock Fault
If the FREF frequency drops below the specified minimum frequency, the driver will shut down and the
FAULT pin will go high.
PROTECTION FEATURES
Low Voltage Detection
If the supply drops below the detect threshold, the
HALL SWITCH
FIRING ORDER
NORMAL OUTPUT
FIRING ORDER
G
ALL1
HALL2 =:t::~-"""!
HALL3
~~A
ACTIVE BRAKING
FIRING ORDER
,
I,
OUTB
OUTC
~~A
OUTB
OUTC
L
L
r
~
,,
,
--,
,
-J
,,
,
;
:1
..
360 0 ROTATION
,,,
.." ,
FIGURE 1: HALL Switch/Driver Timing Relationship
0888
5-9
I
SSI32M591
Three-Phase 5-1/4 Inch
Winchester Motor Speed Control
ELECTRICAL CHARACTERSTICS
ABSOLUTE MAXIMUM RATINGS
Maximum limits indicate where permanent device damage occurs. Continuous operation at these limits is not
intended and should be limited to those conditions specified in the DC operating characteristics.
PARAMETER
RATING
Positive Supply Voltage, VDD
14
V
-65 to + 125
°C
-0.3 to VDD +0.3
V
Storage Temperature
Pin Voltage (except FAULT and LOCK)
FAULT and LOCK Pin Voltage
UNIT
-0.3 to VDD +5.0
V
20
rnA
260
°C
HALLOUT Current
Lead Temperature (soldering, 10 sec)
RECOMMENDED OPERATION CONDITIONS
PARAMETER
CONDITIONS
DC Supply Voltage, VDD
Input Clock, FREF
Ambient Temperature, Ta
NOM
MAX
10.8
12.0
13.2
V
1.9998
2
2.0002
MHz
70
°C
.4
.408
Q
0.8
1.8
V
0
Emitter ReSistor, Re
.392
Power Darlington Vbe
Motor Parameters (1)
MIN
Motor Frequency (s ) _
Motor Current (s )
UNITS
KT
Js+KD
KT, Torque Constant Range
(0.15 Nt-m/A nom)
-10
+10
%
J, Inertia Range
(489x10-6 Nt-m-sec2 nom)
-33
+33
%
KD, Damping Factor Range
(31.8x10-6 Nt-rn/rad/sec nom)
-33
Winding resistance (2)
+33
2.0
Winding inductance
Back EMF (2)
%
Ohms
2.0
mH
0.0159
V/rad/sec
Notes:
(1 ) The motor parameters given are for a typical motor. The device will work for a range of motors near this
nominal motor.
(2)
The motor must have a back EMF less than 10 volts peak (measured from center tap to drive transistor
collector/drain) at speed to insure linear operation of drive transistors and a coil resistance small enough
to insure adequate start current.
5-10
0888
SSI32M591
Three-Phase 5-1/4 Inch
Winchester Motor Speed Control
DC ELECTRICAL CHARACTERISTICS.
Unless otherwise specified, 10.BV:::;VDD:::;13.2V: 0°C:::;TA:::;70°C; FREF
Motor Configuration is 4-pole 3-phase center-tap "Y".
PARAMETER
CONDITIONS
= 2.000MHz; Re = 0.4 Ohms;
MIN
NOM
MAX
UNITS
30
rnA
400
mW
9.0
V
Power Supply Current
ICC
Clock Active
1(HALLOUT) = 1SmA
1 Driver loaded to = S rnA
2 Drivers unloaded
Power Dissipation
Fault Detection
6.B
Low Voltage Detect
Threshold
Input Lagle Signals - 'FREF' and 'STARr Inputs
Vii, Input Low Voltage
iii, Input Low Current
O.OB
Vin=O
Vih, Input High Voltage
IiH, Input High Current
V
-SOO
~
2.0
V
Vin=S
100
~
Output Lagle Signals - 'LOCK' and 'FAULr Pins
Vol
Isink= 2mA
0.4
V
loh
Vout = VDD
10
~
HALL Sensor Interface
HALLOUT Bias Voltage
1= Oto -1SmA
HALL 1,2,3 Pullup Resistance
To HALLOUT pin
S.O
6.B
V
S
20
KQ
1.0
V
Input Low Voltage
Input High Voltage
4.0
V
rnA
Driver Outputs
Sink Capability
Vol = O.SV
1.0
Source Capability
Voh = 3.0V
-S.O
rnA
SO.O
Capacitive Load Drive
Capability
pF
Sense Input And Over-Current Control
Threshold Voltage
Input Current
0888
5-11
0.9
1.1
V
-100
100
~
I
SSI32M591
Three-Phase 5-1/4 Inch
Winchester Motor Speed Control
AC ELECTRICAL CHARACTERISTICS
Unless otherwise specified, 10.8V:S;; VDD:s;; 13.2V; O°C:s;; TA:s;; 70°C; FREF = 2.000 MHz; Re=O.4 Ohms.
PARAMETER
MIN
CONDITIONS
NOM
MAX
UNITS
0.900
sec
100
Hz
3615
Hz
Fault Detection
Stalled Rotor Shutdown Time
Power On to driver
0.850
Low FREF Shutdown
Threshold
Lock Indication
Lock Range
Motor Speed
3585
Control Loop Parameters*
Divider Ratio
FREF/Fmotor
33,336
Instantaneous Speed Error
Referenced to 60Hz
Index to Index Jitter
(16/FREF)
Total jitter
Loop Bandwidth
Nominal motor
Re = 0.400
Loop Zero
Ki/Kp
Maximum Running Current
Re
1.50
Minimum Running Current
= 0.400
Re = 0.400
Start Current
Re = 0.400
2.25
-0.035
0.01
0.015
%
8
j.ls
2
Hz
1.0
Hz
Amps
0
Amps
2.75
Amps
~
Input Logic Signals-'FREF' and 'START' Pins
Input Capacitance
..
25
pF
25
pF
25
pF
Hall Sensor Interface
Input Capacitance
Sense Input and Over-current Control
Input Capacitance
'Control Loop Notes:
Running current limits refer to capabilities during speed correction.
The motor control loop consists of counters, logic, and digital-to-analog converters that provide loop time
constants. The continuous time transfer function of the on chip control can be modeled as follows:
H(s) = Vc(s)
Fm(s)
=Ki + Kp
s
Vc(s) is the voHage applied to the extemal setting resistor Re by the modulator. By adjusting the value of Re
the gain the motor sees can be adjusted, as can the starting current.
5-12
0888
SSI32M591
Three-Phase 5-1/4 Inch
Winchester Motor Speed Control
+12V
CLOCK
FREF
Voo
101(0
HALLOUT
HALL 1
LOCK
HALl2
FAULT
HALL3
OUTA
START
OUTB
101(0
COILA
START
OUTC
VSS
SENSE
I
Re
0.40
Typical Application Diagram
0888
5-13
SSI32M591
Three-Phase 5-1/4 Inch
Winchester Motor Speed Control
"'Ja
PIN DIAGRAM
THERMAL CHARACTERISTICS:
(TOP VIEW)
16-Pin DIP
75°CIW
16-Pin SOL
105°CIW
VDD
SENSE
OUTB
OUTC
OUTA
HALL2
N/C
FREF
N/C
HALLOUT
LOCK
START
FAULT
HALL1
VSS
HALL3
16·Pln DIP
ORDERING INFORMATION
ORDER NO.
PKG.MARK
SSI32M591 16-Pin Plastic DIP
SSI 32M591-CP
32M591-CP
SSI 32M591 16-Pin SOL
SSI 32M591-CL
32M591-CL
PART DESCRIPTION
No responsibility is assumed by SSI for use of this product nor for any infringements of patents and trademarks or other rights of third parties
resulting from its use. No license is granted under any patents, patent rights or trademarks of SSI. SSI reserves the right to make changes
in specifications at any time without notice.
Silicon Systems, Inc., 14351 Myford Road, Tustin
CA 92680, (714) 731-7110, TWX 910-595-2809
©1988 Silicon systems, Inc.
0888
5-14
SSI32M593
Three-Phase Delta
Motor Speed Controller
INTEGRATION
June, 1988
FEATURES
DESCRIPTION
The SSI 32M593 is a motor speed controllC designed
to provide all timi ng and control functions necessary to
start, drive, and brake a 3-phase, 4 or 8 pole brushless
DC spindle motor. External Darlington powertransistors or external power FETs may be used by the
SSI 32M593 to drive the spindle motor.
The motor Hall sensors are directly driven and decoded by the device. The controller is optimized for a
3600 rpm motor using a2 MHz clock. Motorprotection
features include jammed platter shutdown, supply and
clock fault detection, all of which are indicated by a
FAULT signal, and coil over-current detection and
control. A LOCK signal is provided to indicate that the
motor is at speed. The device's linear control loop
controls the power drivers using Pulse Amplitude
Modulation.
The SSI32M593 requires a + 12V power supply, and is
available in 20-pin DIP or SO packages.
•
•
•
•
•
•
•
•
3-phase bipolar or unipolar operation
4 or a-pole operation
3600 rpm speed control using a 2 MHz clock
Highly accurate speed regulation of ±0.037%
On-chip digital filter
At speed indication provided
Active braking function
Output pre-driver for center tap or non-center
tap windings
•
Drives complementary Darlington power transistors or complementary power FETs
•
•
•
Power supply fault protection
Motor over-current protection
Multiple retry on jammed spindle
Single +12 volt power supply
•
BLOCK DIAGRAM
PIN DIAGRAM
'REF
LOCK
CI<
HALL3
START
FREF
HALLOUT
HALL1
FMOTOR
OUTUPC
FAULT
VDD
MODE
UENABLE
GND
OUTB
START
OUTA
OUTUPA
CK
OUTUPB
HALL2
SENSE
OUTC
2D-PIN DIP or SOL
YREF
CAUTION:
0688
5-15
Use handling procedures necessary
for a static sensitive component.
I
SSI32M593
Three-Phase Delta
Motor Speed Controller
FUNCTIONAL DESCRIPTION
The SSI 32M593 uses a mix of analog and digital
techniques to accomplish speed control. The control
signal is generated by analog conversion of a digital
speed error term developed by examining the contents
of a count-down counter once per motor revolution.
The sign and magnitude of the remainder controls the
amplitude of a correction signal applied to the motor.
Commutation timing, developed from motor generated
HALL signals, applies the correction in the proper
phase sequence.
The device uses a Pulse Amplitude Modulation (PAM)
scheme ratherthan Pulse Width Modulation (PWM) to
avoid the switching transients and torque ripple inherentin PWM.
In operation, the SSI 32M593 is installed in a closed
loop control system that maintains the ~peed of a
3-Phase Brushless DC motor. By monitoring the
HALL signal outputs of the motor, a control voltage is
developed using both digital and analog techniques.
The analog portion of the control loop uses switched
capacitor techniques to eliminate the need for any external passive components required for loop compensation. An operation description of the circuit follows.
CONTROL LOOP
Referring to the block diagram, the major sections of
the control loop are a 19-stage Counter, Integral and
Proportional channels, D/A's and a Summer.
The speed error is determined by examining the contents of the counter once per revolution. The counter
is preset once per revolution by an INDEX signal
developed from the HALL1 input, at the same time any
remainder resulting from a 500 KHz count-down rate is
loaded into a latch.
If the contents of the counter indicate that the speed is
outside tbe linear regulation range (±0.037"1o), this is
decoded as a "FAST" or "SLOW' condition. Under
these conditions the Proportional D/A output is driven
to either end of its range, as appropriate. Under a slow
condition, a fixed reference voltage is supplied to the
output drives.
The Summer then outputs a control voltage (VC) consisting of a bias voltage plus or minus the sum ofthe two
D/A outputs.
The Integral and Proportional channels perform several functions related to the operation of the control
loop. One function is to control loop stability by maintaining the loop zero at 1 Hz. In operation this translates to the Integral channel responding to major bias·
point changes while the Proportional channel takes
care of minor perturbations to the loop.
COMMUTATION
The summer output is channeled to the appropriate
OUTA, B, C output according to the timing shown in
Rgure 1. To reduce switching transients, the outputs
are slew rate controlled during each transition.
OUTUPA, B, C outputs cycle between approximately
VDD in the OFF state and GND in the ON state also
according to Figure 1. Again, rise and fall times are
controlled during transitions.
MOTOR COIL OVER-CURRENT
Refer to SENSE input description. Sense voltage is
generated by current through Re shown in the typical
application. The SENSE input threshold limits the
maximum coil current.
The lower LSB's of the latch, except for the LSB, are
used to drive the Proportional D/A while the entire
contents of the latch are accumulated to control the
Integral Channel. The MSB's of the accumulator drive
the Integral D/A.
5-16
0688
SSI32M593
Three-Phase Delta
Motor Speed Controller
HALL SIGNAL AND FMOTOR TIMING
HALLl
~
HALL2
HALL3
FMOTOR
~
j
,
FORWARD FIRING OIIDER
CUTUPA
CUTUPB
OUTUPC
OUTA
OUTB
OUTC
REVERSE FIRING ORDER
(ACTIVE BRAKING)
L
OUTUPA
OUTUPB
OUTUPC
OUTA
OUTB
OUTC
I~'~~~~'~~r-l~~~
r
I
360'
MECHANICAL
1
NOTE: Figure shows commutation of a 4-pole device. 8-pole devices apply same firing order twice per revolution.
FIGURE 1: COMMUTATION TIMING DIAGRAM
0688
5-17
SSI32M593
Three-Phase Delta
Motor Speed Controller
reduced to zero until such time as one positive
HALL index transition is detected, the START
pin is toggled, or power or FREF is removed and
re-applied. After the fourth try, FAULT goes
high. (See Figure 2.)
FUNCTIONAL DESCRIPTION (Continued)
FAULT CONDITIONS
Four conditions cause an active high on the FAULT
output pin, also disabling all drivers except as noted:
(1 )
Low power supply - VDD < Vlvdt
(2)
No FREF clock - FREF < Fmin
(3)
Stalled motor. If the delay from power onset to
a positive HALL index transition or the time
interval between successive HALL index transitions is greater than the specified time, the
device interprets this delay as a stalled motor,
reduces the motor current to zero and performs
three retry cycles. If the motor continues to be
stalled after three retries, then motor current is
(4)
Reverse shutdown speed. During active braking
(START=O) the HALL sensor's phasing is
changed to apply a reverse torque to the motor
until the motor speed drops below the reverse
shutdown speed at which time the drivers turn off
to deny power to the motor and FAULT goes
high. If UENABLE is high (non-center tapped
motor) the device will perform passive braking
after the motor speed drops below the reverse
shutdown speed by enabling the lower drivers,
OUTX, to dissipate any remaining coil energy.
The upper drivers OUTUPX are off.
(See Figure 3.)
/
OUTX.O::::---- ~ ~>---~0>-----<0
---------------------------~/
FAULT
FIGURE 2: JAMMED PLATTER SEQUENCE
5-18
0688
SSI32M593
Three-Phase Delta
Motor Speed Controller
START
"
ACTIVE BRAKING
PASSIVE BRAKING
~~---------------------+---------------OUTX
OUTUPX
FORWARD COMMUTATION
~_300
FMOTOR ______ __
o_rp_m____
LOCK
(ACTIVE LOW)
FAULT
REVERSE COMMUTATION
X~O
(UENABLE ~ ')
~jx(~_______28_'_r~__<_F<_~_OO__~______~~~_____F_<_~_'_r~_______
-------/
---------------------------------------~/
FIGURE 3: ACTIVE BRAKING SEQUENCE
0688
OUTX~'
OUTUP
5-19
SSI32M593
Three-Phase Delta
Motor Speed Controller
PIN DESCRIPTION
NAME
TYPE
DESCRIPTION
VDD
I
+12V Power Supply
GND
I
Ground
FREF
I
The reference clock input used to set motor speed and operate circuit
blocks.
START
I
Spin start is enabled by applying a logic "one" to the START pin. It may be
connected to VDD in systems that do not require active braking. Active
braking is enabled by applying a logic "zero" to the START pin. During active
braking the commutation is changed to apply a reverse torque to the motor
until the motor velocity drops below 281 rpm.
MODE
I
Mode Control. When tied high (to VDD) selects 8-pole operation where
HALL 1 signal is divided by fourto generate an index signal. When left open,
4-pole operation is selected and HALL 1 is divided by two.
UENABLE
I
Tying UENABLE to GND forces all upper outputs to their off state and
disables passive braking. UENABLE must be tied to GND for unipolar
center-tapped motors. Tied high or floating, UENABLE = 1 and drives
bipolar motors.
FAULT
0
FAULT goes active high indicating low Voo, no FREF, a stalled motor, or
motor velocity below the reverse shutdown speed.
LOCK
0
LOCK goes active low when the motor frequency is within a specified lock
range.
FMOTOR
0
FMOTOR frequency indicates the motor speed, nominally 3600 rpm.
FMOTOR is derived from HALL 1.
SENSE
I
Coil Current Sense Input. Senses the coil current and limits the sense
voltage to the specified threshold by limiting the voltage from the lower
drivers. (OUTX)
HALLOUT
0
Hall Sensor Bias Output. Provides a regulated bias voltage forthe hall effect
sensors.
HALL1, 2,3
I
Hall Sensor inputs that determine commutation. The TTL open-collector
type motor outputs drive these inputs, which have internal resistor
pullups referenced to the HALLOUT bias voltage.
OUTUPA,B,C
0
Upper motor CMOS level outputs that drive either Darlingtons or PFETs.
OUTA, B, C
0
Lower Driver Outputs. These three driver outputs drive external Bipolar
or NFET power transistors to control the motor current through the current
setting resistor Re. The motor current is V(sense)/Re. During normal
operation, the drive voltages are adjusted as necessary to maintain the
proper motor speed and drive current.
5-20
0688
SS.32M593
Three-Phase Delta
Motor Speed Controller
ABSOLUTE MAXIMUM RATINGS
PARAMETER
RATING
UNIT
VDD Supply Voltage
-0.5 to +14V
V
Storage Temperature
-65 to +150
°C
260
°C
215
°C
-0.3 to VDD +0.3
V
Lead Temperature, PDIP (10 sec. soldering)
Package Temperature, SO (20 sec. reflow)
Input, Output pins
Inputs and outputs are protected from static charge using built-in ESD and Latchup protection devices.
ELECTRICAL CHARACTERISTICS (Unless otherwise specified Vlvdt
"-_---'
5-27
SSI32M594
Three-Phase Delta
Motor Speed Controller
FUNCTIONAL DESCRIPTION
The SSI 32M594 uses a mix of analog and digital
techniques to accomplish speed control. The control
signal is generated by analog conversion of a digital
speed error term developed by examining the contents
of a count-down counter once per motor revolution.
The sign and magnitude of the remainder controls the
amplitude of a correction signal applied to the motor.
Commutation timing, developed from motor generated
HALL signals, applies the correction in the proper
phase sequence.
The device uses a Pulse Amplitude Modulation (PAM)
scheme rather than Pulse Width Modulation (PWM) to
avoid the switching transients and torque ripple inherent in PWM.
The SSI 32M594 generates a motor current voltage
which is related to the motor speed error. This is
implemented on the IC by digital/analog techniques,
converting a motor frequency error derived from a
reference clock and digital counter into a voltage using
switched capacitor D/A's. The voltage Vc translates
into a motor current across Re regulating motor speed.
In operation, the SSI 32M594 is installed in a closed
loop control system that maintains the speed of a
3-Phase Brushless DC motor. By monitoring the
HALL signal outputs of the motor, a control voltage is
developed using both digital and analog techniques.
The analog portion of the control loop uses switched
capaCitor techniques to eliminate the need for any external passive components required for loop compensation. An operation description of the circuit follows.
The lower LSB's of the latch, except for the LSB, are
used to drive the Proportional D/A while the entire
contents of the latch are accumulated to control the
Integral Channel. The MSB's of the accumulator drive
the Integral D/A.
If the contents of the counter indicate that the speed is
outside the linear regulation range (±0.037%), this is
decoded as a "FAST" or "SLOW' condition. Under
these conditions the Proportional D/A output is driven
to either end of its range, as appropriate. Under a slow
condition, a fixed reference voltage is supplied to the
output drives resulting in a start current of Vref/Re.
When LOCK is low, the control voltage, VDAC, from
the summer is used to generate the motor running
current. VDAC is a summation of integral channel
voltage which cancels out offsets in the loop and motor
losses, and a proportional channel voltage which tracks
speed variations from the counter. The two channel
voltages are then summed and weighted. The control
voltage applied is externally scaleable by resistors R1
and R2 at DACOUT and DACIN (see Typical Application diagram) to fit a wide range of motors including
those used in 3 1/2" drives. Note that Re affects start
current while R1 and R2 affect running current as
lrunning = VDAcIN/Re.
The Integral and Proportional channels perform several functions related to the operation of the control
loop. One function is to control loop stability by maintaining the loop zero at 1 Hz. In operation this translates to the Integral channel responding to major bias
point changes while the Proportional channel takes
care of minor perturbations to the loop.
CONTROL LOOP
COMMUTATION
Referring to the block diagram, the major sections of
the control loop are a 19-stage Counter, Integral and
Proportional channels, D/A's and a Summer.
The summer output is channeled to the appropriate
OUTA, B; C output according to the timing shown in
Figure 1. To reduce switching transients, the outputs
are slew rate controlled during each transition.
The speed error is determined by examining the contents of the counter once per revolution. The counter
is preset once per revolution by an INDEX signal
developed from the HALL 1 input, at the same time any
remainder resulting from a 500 KHz count-down rate is
loaded into a latch.
OUTUPA, B, C outputs cycle between approximately
VDD in the OFF state and GND in the ON state also
according to Figure 1. Again, rise and fall times are
controlled during transitions.
5-28
0888
SSI32M594
Three-Phase Delta
Motor Speed Controller
HALL SIGNAL TIM NG
HALL1
~
I
HALL2
I
HAL13
----:l
FORWARD FIRING ORDER
OUTUPA
OUTUPB
I
OUTUPC
~
I
W.
n
I
CUTA
n
r-
OUTB
CUTC
REVERSE FIRING ORDER
(ACTIVE BRAKING)
W
OUTUPA
U
I
L
CUTUPB
OUTUPC
OUTA
OUTB
CUTC
I
I
n
I
I'
I
h
I
I
I
360·
MECHANIG:AL
I
NOTE: Figure shows commutation of a 4-pole device. 8-pole devices apply same firing order twice per revolution.
FIGURE 1: Commutation Timing Diagram
0888
5-29
SSI32M594
Three-Phase Delta
Motor Speed Controller
interval between successive HALL index transitions is greater than the specified time, the
device interprets this delay as a stalled motor,
reduces the motor current to zero and performs
three retry cycles. If the motor continues to be
stalled after three retries, then motor current is
reduced to zero until such time as one positive
HALL index transition is detected, the START
pin is toggled, or power or FREF is removed and
re-applied. After the fourth try, FAULT goes
high. (See Figure 2)
FUNCTIONAL DESCRIPTION (Continued)
MOTOR COIL OVER-CURRENT
Refer to SENSE input description. Sense voltage is
generated by current through Re shown in the typical
application. The SENSE input threshold limits the
maximum coil current.
FAULT CONDITIONS
Four conditions cause an active high on the FAULT
output pin, also disabling all drivers except as noted :
(1)
Low power supply - VDD < Vlvdt
(2)
No FREF clock - FREF < Fmin
(3)
Stalled motor. If the delay from power onset to
a positive HALL index transition or the time
(4)
Reverse shutdown speed. During active braking
(START = 0) the HALL sensor's phasing is
changed to apply a reverse torque to the motor
until the motor speed drops below the reverse
shutdown speed at which time the drivers turn off
to deny power to the motor and FAULT goes
high. (See Figure 3)
START·----/
~ms~>----8>----.. .8>-----
OUTX.OUTUPX(------I
ON
ON
SOOms
FAULT·--------------------------.....,/
FIGURE 2: Jammed Platter Sequence
START - - - - - - - - . . " "
PASSIVE BRAKING
ACTIVE BRAKING
~------------~--------------OU~~~
REVERSE COMMUTATION
FORWARD COMMUTATION
(ACTIVE= _ _ _ _ _ _
OUTX=l
OUTUP X=O
(UENABLE = 1)
~/
FAULT _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _...../
FIGURE 3: Active Braking Sequence
5-30
0888
SSI32M594
Three-Phase Delta
Motor Speed Controller
PIN DESCRIPTION
NAME
0888
TYPE
DESCRIPTION
VDD
I
+12V Power Supply
GND
I
Ground
FREF
I
The reference clock input used to set motor speed and operate circuit
blocks.
START
I
Spin start is enabled by applying a logic "one" to the START pin. It may be
connected to VDD in systems that do not require active braking. Active
braking is enabled by applying a logic "zero"to the START pin. During active
braking the commutation is changed to apply a reverse torque to the motor
until the motor velocity drops below 281 rpm.
MODE
I
Mode Control. When tied high (to VDD) selects 8-pole operation where
HALL 1 signal is divided by fourto generate an index signal. When left open,
4-pole operation is selected and HALL 1 is divided by two.
FAULT
0
FAULT goes active high indicating low Voo, no FREF, a stalled motor, or
motor velocity below the reverse shutdown speed.
LOCK
0
LOCK, open drain active low, goes active low when the motor frequency is
within a specified lock range.
SENSE
I
Coil Current Sense Input. Senses the coil current and limits the sense
voltage to the specified threshold by limiting the voltage from the lower
drivers. (OUTX)
HALLOUT
0
Hall Sensor Bias Output. Provides a regulated bias voltage for the hall effect
sensors.
HALL1, 2, 3
I
Hall Sensor inputs that determine commutation. The TTL open-collector
type motor outputs drive these inputs, which have internal resistor
pullups referenced to the HALLOUT bias voltage.
OUTUPA, B,C
0
Upper motor CMOS level outputs that drive either Darlingtons or PFETs.
OUTA, B, C
0
Lower Driver Outputs. These three driver outputs drive external Bipolar
or NFET power transistors to control the motor current through the current
setting resistor Re. During normal operation, the drive voltages are adjusted
as necessary to maintain the proper motor speed and drive current.
DACIN
I
Reference voltage for motor current.
DACOUT
0
Summer Output (VDAC).
channel voltages.
5-31
The summation of integral and proportional
SSI32M594
Three-Phase Delta
Motor Speed Controller
ABSOLUTE MAXIMUM RATINGS
Maximum limits indicate where permanent device damage occurs. Continuous operation at these limits is not
intended and should be limited to those conditions specified in the DC Operating Characteristics.
RATING
PARAMETER
UNIT
VDD Supply Voltage
-0.5to+14V
V
Storage Temperature
-65 to +150
°C
Lead Temperature, PDIP (10 sec. soldering)
260
°C
Package Temperature, SO (20 sec. reflow)
215
°C
-0.3 to VDD +0.3
V
Input, Output pins
Inputs and outputs are protected from static charge using built-in ESD and Latchup protection devices.
ELECTRICAL CHARACTERISTICS (Unless otherwise specified Vlvdt Ci(, FAULT
VOL Output Low Voltage
IOL=2 rnA
Typical external pullup resistor
-
-
0.5
V
-
10
-
KQ
8.0
-
9.5
V
-
-
100
Hz
0.90
-
sec
rpm
FAULT Indication
Vlvdt, low voltage
Fmin, loss of FREF
Stuck motor, start pulses
drivers on, drivers off
Number of start pulses
Reverse shutdown speed
START = 0
4
281
-
[QCK Indication
Lock range
FREF= 2 MHz
3594
3607
rpm
Speed error
10.8 < VOO < 13.2
-0.037
+0.037
0/0
10.8 < VOO < 13.2,
lIoad = -5 rnA
5.0
6.8
V
10.8 < VOO < 13.2,
lIoad = -10 rnA
5.0
3600
HALL Sensor Interface
HALLOUT bias voltage
V
Driver Outputs (FHALLX 2: 100 Hz, Vlvdt < VOO S 13.2, CL S 500 pF unless otherwise specified.)
Slew rate
OUTX
OUTUPX
0888
All driver outputs
150
-
400
V/msec
VOH
lIoad = -7.5 rnA
3.75
lIoad = -100 1iA,
10.8 S Voo S 13.2
8.0
-
-
V
VOH
VOL off state
lIoad = 3.4rnA,
5.0 S VOO S 13.2
-
-
0.5
V
VOL
lIoad = 10 rnA
-
-
3.0
V
VOH off state
lIoad = -5 rnA
Voo-o.s
lIoad = -2 rnA,
5.0 S VOO S Vlvdt
Voo-o.s
-
V
VOH off state
-
5-33
V
V
SSI32M594
Three-Phase Delta
Motor Speed Controller
APPLICATION INFORMATION
PARAMETER
RECOMMENDED
MIN
NOM
MAX
UNIT
Power Darlington Vbe
Typical device: TIP 125,
TIP 120
0.8
-
1.8
V
Power FET Vth
Typical device: IRFT 001
2
6
V
0.4
0
30
-
-
V
0.02
0.2
1.0
20
50
200
Power Transistors
-
Power FET Rds (on)
Power FET BVds
R1,R2
R1/(R1 + R2)
R1 + R2
KO
I running =_R_1_x VDAC
R1+R2
Re
WhereVDAC=Kp*df+Ki* Jdf*dt
Kp = Proportional constant = .213 V/radlsec
Ki = Integral constant = 1.33 V/rad
df = Frequency error
Motor Parameters
The SSI32M594 MSC is optimized for use with a wide range of Winchester motors including 31/2" motors.
Torque Constant Range (KT) of 0.01 to 0.02 Nt - mtA and an Inertia Range (J) from 0.5 to 6.5 x 10 -4
Nt - m - sec 2. The choice of R1, R2 and Re will be affected by motor parameters, so some care in their
selection is recommended.
Control Loop Parameters
The motor control loop consists of counter, logic, and digital-to-analog converters that provide loop time
constants. The continuous time transfer function of the on-chip control can be modeled as follows:
H(s) = Vc(s) = Ki + Kp
Fm(s)
s
Vc(s) is the voltage applied to the external sense resistor (Re) by the modulator. By adjusting the value of Re,
the gain the motor sees can be adjusted as can the starting current.
5-34
0888
SSI32M594
Three-Phase Delta
Motor Speed Controller
Control Loop Parameters (Continued)
PARAMETER
RECOMMENDED
Loop Bandwidth
Nominal motor, Re = O.4n
Loop Zero
KilKp
MIN
NOM
MAX
UNIT
Hz
Hz
2
1.0
Kp, Proportional Channel Gain
0.198
0.213
0.227
V/rad/s
Ki, Integral Channel Gain
1.23
1.33
1.42
V/rad
Start current
1.0
2.0
3.0
Amps
Running current
0.1
0.2
0.3
Amps
.SV
I
V12
.SV
10K
CLOCK
START
NOTE:
C>--1f-++t--'--l
In cases where motor coil voltages are noisy with complex transients. stability can be improved by snubber (filter) circuits
on each coil. A series RC filter to ground is suggested with the following values: (R = 10Q, C = 4.7 I1F).
Typical Three-Phase, 4-Pole, Bipolar,
Non-Center Tapped Motor using a Power FET Module
0888
5-35
SSI32M594
Three-Phase Delta
Motor Speed Controller
Typical Three-Phase, a-Pole, Unipolar,
Center Tapped Motor using a Power Darlington.
5-36
0888
SSI32M594
Three-Phase Delta
Motor Speed Controller
PACKAGE PIN DESIGNATIONS
CAUTION: Use handling procedures necessary
for a static sensitive component.
(TOP VIEW)
LOCK
HALL3
2
20
OUTUPB
19
OUTUPC
FREF
3
18
FAULT
HALLOUT
4
17
VDD
HALL1
5
16
DACIN
MODE
6
15
DACOUT
GND
7
14
OUTB
START
8
13
OUTA
OUTUPA
9
12
SENSE
10
11
OUTC
HALL2
20-Pin PDIP or SOL
ORDERING INFORMATION
PART DESCRIPTION
I
PACKAGE MARK
ORDERING NUMBER
SSI 32M594 Three-Phase Delta Motor Speed Controller
20-Pin SOL
20-PIN PDIP
I
I
SSI 32M594-CL
SSI 32M594-CP
I
I
SSI 32M594-CL
SSI 32M594-CP
No responsibili1y is assumed by SSi for use of this product nor for any infringements of patents and trademarks or other rights of third parties
resulting from its use. No license is granted under any patents, patent rights or trademarks of SSi. SSi reserves the right to make changes
in specifications at any time without notice.
Silicon Systems, Inc., 14351 Myford Road, Tustin,
0888
CA 92680 (714) 731-7110, TWX 910-595-2809
©1988 Silicon Systems, Inc.
5-37
NOTES:
SSI328450A
SCSI Controller
INNOVATORSIN
I~N~TE~G~R~A~T~IO~N~
_________________________
August, 1988
DESCRIPTION
FEATURES
The SSI32B450A is a SCSI bus controllC that handles
all arbitration, (re)selection, and data transfer functions
for the SCSI bus interface portion of an intelligent
peripheral controller or host controller in accordance
with ANSI Standard X3.131-1986.
•
Single-chip SCSI bus control; no external
circuitry required for bus-Interface functions
•
Optimized for use with SSI 32C452 Storage
Controller IC and SSI 32C453 Dual-pon Buffer
Controller IC
•
•
Async SCSI data rate up to 4 Mbytes
The SSI 32B450A is optimized for use with the
SSI 32C452 Storage Controller, the SSI32C453 DualPort Buffer Controller, and an 8-bit multiplexed address/data bus microprocessor such as the 8051 to implement complete SCSI controller functions for high
performance data storage devices. Each IC in the set
is highly integrated and utilizes a bus oriented design
structure that implements high performance and requires minimal board space and software overhead.
Functionally, the SSI32B450A performs all SCSI bus
control and interface functions and the DMA handshake to work with the buffer controller to ensure
efficient data transfer. It supports both target and
initiator modes, and carries out SCSI arbitration,
(re)selection and data transfer functions without microprocessor intervention. It has eight programmable
interrupts which eliminate the need for polling from the
microprocessor to detect process completion or error
conditions.
•
•
•
•
•
•
Operation conforms to ANSI Standard
X3.131-1986
suppons both Target and Initiator modes
Software programmable SCSIID for all modes
High current drivers I receivers for direct SCSI
bus connection
Parity generation and check for SCSI data
High performance, low-power CMOS design;
single +5V power supply
Available In 52-pin surface mount PLCC
BLOCK DIAGRAM
"SmT
1!SV
"SEE
!!l
"REO"
Al:R"
ill
DB7·DBO
'"
~
BSYIN
BSYOUT
BREa
BACK
DBP
LO
1/"0
C/lr
lI1E
07-00
"fJSl!
J\TR
lJiIT
SCSIGND
~
"RO" WR ALE ADa·ADO
Vee GND CLK
ImT
CAUTION: Use handling procedures necessary
for a static sensitive component.
0888
6-1
SSI32B450A
SCSI Controller
FUNCTIONAL DESCRIPTION
The SSI 32B450A performs all the necessary tasks to
control communication with the SCSI bus in both target
and initiator roles, without assistance from the microprocessor, according to ANSI Standard X3.131-1986.
Because the SSI32B450A can operate in both the target and initiator roles it is suitable for use in both host
and peripheral designs. A basic understanding of the
physical and logical characteristics described in the
ANSI specification is helpful. For more information
refer to the Applications Information section at the end
of this data sheet.
When directed the SSI 32B450A will arbitrate for the
SCSI bus and (re)select another SCSI device automatically upon successful completion of arbitration. A
programmable interrupt signal flags operation completion, arbitration lost, or error conditions so the microprocessor does not have to poll the SCSI Controller.
The microprocessor can identify the cause of the
interrupt by reading the interrupt status registers. Once
a valid SCSI bus connection is made the SSI32B450A
works with the local DMA logic, such as the SSI
32C453 Buffer RAM Controller, without microprocessor intervention, to transfer data efficiently to and from
the SCSI bus. The microprocessor controls the operation and obtains status from the SSI 32B450A by
accessing the internal registers.
The functional sections of the SSI32B450A are shown
in the Block Diagram.
The SCSI register and control section executes the
SCSI bus interface operations in accordance with
ANSI Standard X3.131-1986. The arbitration and
(re)selection operations are initiated by writing to the
registers and the status is obtained by reading from
them. Once arbitration is initiated by setting the ARB bit
in the COMMAND register or asserting the BSYOUT
pin, the SSI32B450A executes the arbitration process
and upon winning the SCSI bus proceeds directly into
the (re)selection process. Whether it is the selection or
reselection process is determined by the state of the
ITAR bit in the TRGTI D register, which directs whether
the SSI32B450A operates as an initiator or target. The
SID2-SIDO (self ID) bits and TID2-TIDO (target ID) bits
are automatically converted from binary code as they
are written in the SELFID and TRGTID registers, and
the properdatabus (DB) signal(s) driven onto the SCSI
bus. During arbitration the SSI32B450Acompares the
self ID with the other ID's on the bus to discern whether
it has won the arbitration. The SSI32B45OA can be programmed to assert the INT (interrupt) line when the
processes are complete or an error occurs.
The BSYIN pin indicates to the buffer control logic that
the SCSI bus signal BSY is asserted and the bus is
currently in use.
Upon being directed to initiate the arbitration phase,
the SSI32B450A checks for bus-free phase (BSY and
SEL deasserted continuously for minimum of
bus-settle delay and bus-free delay), then asserts the
BSY signal and drives the SELFID onto the SCSI bus.
After waiting an arbitration delay, it examines the data
bus. If a higher SCSIID is present on the bus, the SSI
32B450A has lost the arbitration. The SSI 32B450A
releases the BSY and ID lines and waits for the busfree phase to reoccur, and then begins the arbitration
process again. The continuous arbitration retrying can
be stopped by resetting the ARB bit and negating the
BSYOUT signal. If arbitration Is lost and the LOSE bit
in the INTENO register is set, the INT line will be
asserted and the LOST bit in the INTSTSO register set.
If arbitration is won, the SSI 32B450A asserts SEL. If
the WIN bit in the INTENO register is set, upon winning
arbitration the INT signal will be asserted and the WON
bit in the INTSTSO register will be set.
After a bus-clear plus bus-settle delay time with both
BSY and SEL asserted, the arbitration phase is complete and the selection phase begins. The device
becomes the initiator by leaving I/O negated, and
driving both the self and target ID's onto the SCSI bus.
The SSI 32B450A waits two deskew delays, negates
BSY, then waits a bus-settle delay before looking for a
response from the target. If there are no problems the
target responds by asserting BSY within a bus-settle
delay. BSY must stay asserted for a minimum of 100
nanoseconds from the end of the bus-settle delay
waiting period to be recognized by the SSI 32B450A.
There are two waiting periods: selection-abort time and
timeout delay, which due to their long length are not
monitored by the SSI32B450A and are left to firmware
implementation.
The arbitration and reselection phases occur in the
same manner as arbitration and selection with the
exception that the device which arbitrated asserts the
110 at the end of arbitration indicating it is a target. The
winner (target) then asserts seH and target ID's on to
6-2
0888
SSI32B450A
SCSI Controller
the SCSI bus. When the SS1328450A is the target the
target 10 is located in the S102-S100 bits inthe SELFIO
register.
Once arbitration and (re)selection phases are complete the information transfer phases can be entered.
The microprocessor maintains the 1/0, C/O, and MSG
signals to control the interpretation of the commands
during the message, command and status phases.
These signals are asserted by setting and interrogated
by reading the 1/0, C/O, or MSG bits in the SCSI1
register. The SSI 32B450A monitors the state of these
signals on the SCSI bus and compares them with the
expected state from the contents of the SCSI registers
(which are controlled by the microprocessor) to check
for phase errors. If a difference is detected, a byte of
data transferred across the SCSI bus, and the PHERREN bit in the INTEN1 register is set, the INT line will
be asserted and the PHERRINT bit in the INTSTS1
register set to indicate that a phase error has occurred.
Ouring the message phase, when the SSI32B450A is
the initiator, the ATN signal can be asserted by setting
the ATN bit in the SCSI2 register to indicate to the
target that it has a message ready to transmit. Once
the data transfer phase is entered the SSI 32B450A
controls the SCSI bus signals necessary for data
transfer.
Selection of the SSI32B450A as a target by a host:
The SSI 32B450A will respond only if RESELN or
SELEN bits in CMO register are set. The SSI32B450A
determines that it is selected when SEL and its SCSI 10
is asserted and BSYand I/O are deasserted continuously for minimum of bus-settle delay. Once it determines that it is selected the SSI 32B450A will assert
BSY. If SLCTEN in INTENO register is set; the corresponding INT status bit will be set and INT line will be
driven low to indicate a successful selection ofthe chip
via the initiator.
Reselectlon of the SSI 32B450A as a host by a
target: The SSI32B450A will respond only if RESELN
bit in CMO register is set. The SSI 32B450A determines it is reselected when SEL, VO and SCSI 10 are
asserted and BSY is continuously free for minimum of
bus-settle delay. Once it determines that it is reselected, the SSI32B450Awili assert BSYand deasserts
BSY when it detects a de asserted SEL. If SLCTEN in
INTENO register is set, the corresponding interrupt
status bit will be set and INT line will be driven low to
indicate successful reselection of the chip via the
0888
6-3
target. Also, if parity is supported and bad parity is
found, or more than two lOs are on the bus, the
SSI 32B450A will disregard the reselect attempt by the
target.
The SS1328450A will assert the SRST signal on to the
SCSI bus when the SRST bit in the SCSI2 register is
set. The SRST signal is also received by the SSI450A
when it is asserted by another SCSI device on the bus.
When it is received by the SSI 328450A and the
SRSTEN bit in the INTEN1 register is set, the INT
signal will be asserted upon detection of SRSTtrue and
the SRSTINT bit in the INTSTS1 register set. This indicates that an SCSI reset was the cause of the
interrupt. The SSI 32B450A will not be affected in any
other way by assertion of SRST.
The data transfer Interface logic coordinates the
transfer of data between the data transfer logic and the
SCSI bus. Standard two-wire OMA handshaking is
supported by the BREa and BACK signals. This
section is organized to connect directly with the
SS132C453.
The SSI 328450A is easily connected to any OMA
controller such as 8237 through a single PLA such as
16L8 and LS245 bidirectional octal buffer. In such
case, the SSI 328450A will support both initiator and
target modes while the PLA and the octal buffer will
replace the SSI 32C453.
Before OMA controlled information transfer can begin,
a valid connection must exist to the SCSI bus with BSY
active and no phase error. The direction of information
flow is automatically determined by the SSI 32B450A
from the ITAR bit of the TRGTIO register and the 1/0
signal. There are four information flow states, initiator
in and out, and target in and out. Initiator or target refers
to the mode of the SSI32B450A, and in or out refers to
the direction of data flow with regard to the initiator.
Once a valid SCSI bus connection is established, the
transfer is initiated by the target and data transfer
control logic asserting REa and BREa.
In the target-in state, the data is being transferred from
the data transfer control logic to the initiator at the
initiation of the data transfer control logic and the
SSI32B450A. Once valid data is present on 07-00,
LO is asserted, latching data into the SSI 328450A.
The data transfer control logic asserts BREa, indicating to the SSI 32B450A that valid data is in the internal
SSI32B450A
SCSI Controller
latch ready to be transferred over the SCSI bus. The
SSI32B450A asserts REO and places the data on the
SCSI bus. The initiator asserts ACK indicating acceptance of the data and completion of the SCSI data
transfer cycle. The SSI32B450A asserts BACK to the
data transfer control logic indicating completion of that
cycle.
The handshaking of BREO, BACK and LO is automatically controlled via the SSI32C453. In non SS132C453
environment, it can be easily generated and controlled
by the PLA and generic OMA controller, i.e. 8237.
In the target-out state data is being transferred from the
initiator to the buffer at the initiation of the data transfer
control logic and the SSI 32B450A. The data transfer
control logic asserts BREO requesting transfer of a
byte of data from the initiator. The SSI 32B450A
asserts REO and the initiator responds by driving the
SCSI data bus and asserting ACK which latches data
into the SSI 32B450A. BACK is asserted indicating to
the data transfer control logic that the byte has been
transferred and is ready at the SSI32B450A. The data
transfer control logic then asserts BIE to enable output
of the data onto 0(7:0). When the data transfer control
logic has completed transferring the data it negates
BIE and BREO indicating to the SS1328450A that the
cycle is complete.
For an initiator-in transfer, data is moved to the
SSI 32B450A from the SCSI target selected by the
SSI 32B450A. The data is then moved from the SSI
32B450A to the data transfer control logic. The target'
initiates the transfer by asserting REO and driving the
SCSI data bus. The SS1328450A will not respond untjl
it has been alerted to the pending transfer by the assertion of BREO by the data transfer control logic. This
insures the data transfer control logic is available to
receive data and is not servicing a higher priority data
transfer function such as synchronous transfer from
the hard disk. The SSI 32B450A asserts ACK to latch
data into the internal latch and tell the target the SCSI
transfer is complete. The data transfer control logic
then asserts BI E to enable data to the 07-00 lines. The
SSI32B450A asserts BACK to indicate completion of
transfer from the SCSI bus.
An initiator-out transfer moves data from the data
transfer control logic, through the SSI 32B450A in the
initiator role to the target SCSI device. The transfer is
initiated by the target asserting REO, but the
SSI 32B450A must have already set upforthe impending transfer by the data transfer control logic. Valid data
must be present on 07-00, and is then latched into the
SSI328450~ by asserting LO, and asserting BREO to
begin the data transfer cycle. The SSI 328450A then
drives the SCSI data bus and waits for two deskew
delays and asserts ACK which the target uses to latch
the data from the SCSI bus. Upon negation of REO the
SSI 32B450A asserts BACK indicating to the data
transfer control logic that the transfer is complete.
A feature of the SSI 32B450A which allows for faster
data transfer is that BREO can be negated before the
SS132B450A asserts BACK, allowing the data transfer
control logic to begin preparing for another transfer
cycle without having to wait for the current one to
complete. BREO must have a minimum pulse width of
30 nanoseconds.· The SSI32B450Awili not recognize
more than one BREO assertion until it cycles BACK.
The SSI 32B450A controls the interface to the SCSI
bus so that it is transparent to the rest of the controller
allowing other processes to continue.
During the command, status and message phases the
ONEXFER bit in the SCSI2 register is provided for
transfer of commands to the microprocessor. When it
is set, a byte of data is transferred across the SCSI bus.
When the transfer is complete the bit is reset. The
direction of the data transfer is determined by the state
of VO and the ITAR bit in the TRGTIO register. For
outgoing transfers, the data transferred is that present
in the internal data latch.
Parity is always generated when there is a transfer of
data on the SCSI bus. Whether or not a parity error
causes an interrupt to occur is controlled by the PERREN bit in the INTEN1 register. The PERREN bit also
serves as a mask for the (re)selection process. If the
parity interrupt is enabled, and bad parity occurs during
the (re)selection procedure, the SSI 328450A will not
be (re)selected. If parity interrupt is disabled, the
SSI 32B450A will be (re)selected regardless of the
parity state. A phase error can be detected during a
data transfer phase. Phase error detection is enabled
by setting the PHERRENbit in the INTEN1 register,
and causes the INT signal to be asserted and the
PHERRINT bit in the INTSTS1 register to be set.
The control registers allow programmable control of
the prescaling factorforthe internal clock and soft reset
of the SSI 32B450A. The internal clock synchronizes
6-4
0888
SSI32B450A
SCSI Controller
internal functions such as SCSI bus control signals and
data transfer, and clocks the state machines which
control these functions. The prescaling factor allows
use of available clocks to create the necessary internal
clock rate of 3.34 to 5.0 MHz. For maximum speed of
operation of the SCSI bus, a 5.0 MHz clock is required.
A write to the RESET register causes the SSI32B45OA
to be reset as though the RST pin were asserted. The
details of the effects on the registers are described in
the Register Description section of this data sheet.
The Interrupt registers and control section controls
the INT output and allows the microprocessorto obtain
status once an interrupt has occurred. The INT signal
can be programmed to be asserted for any of eight
reasons by setting the appropriate bit in the INTENO or
INTEN1 registers. These are winning or losing arbitration, (re)selection complete and (re)selected com-
plete, loss of BSY (SCSI busy) true, a phase ~r parity
error, and/or assertion of SRST (SCSI reset) signal on
the SCSI bus. By not setting any of the bits the INT
signal may be masked out completely. Once the INT
signal has been asserted, the microprocessor can
determine the cause(s) of the interrupt by reading from
the INTSTSO and INTSTS1 registers.
The microprocessor Interface section decodes microprocessor read and write requests and provides
access to all the registers. Since both data and
address are carried on the multiplexed address/data
lines, AD3-ADO, address information is latched from
the bus on the falling edge of the ALE (address latch
enable) input. When CS (chip select) is asserted with
either RD (read) or WR (write), the register whose
address was previously latched is selected and data
moved as directed by the RD and WR signals.
PIN DESCRIPTION
NAME
NUMBER
TYPE
DESCRIPTION
GENERAL
VCC
23,44
GND
29,41
RST
39
I
RESET - This signal is active Iow.When asserted the
SSI 32B450A goes to an idle mode and the contents of
some registers are reset. In the idle mode no activity will
take place until further inputs are given. See Register
Description for exact details.
ClK
40
I
MASTER CLOCK - Synchronous internal functions are
controlled by this signal. It is prescaled by the value in the
ClKPRSC register.
POWER SUPPLY - +5 volts
GROUND - Device system ground.
SCSI BUS SIGNALS
All signals connecting to the SCSI bus are designed to have a controlled rise and fall time to minimize the
noise injected into the system.
0888
SGND
3,8,13,
9,49
DBO-DB7
1,2,4-7,
51,52
SCSI GROUND - These are the ground signals for the
SCSI bus interface. These pins should be connected to a
good system ground, capable of handling the large transient and static SCSI bus current levels.
I/O
SCSI DATA BUS - Buffered data bus signals to interface
to the SCSI bus. Schmidt trigger input and high current
open drain drivers allow direct connection to the SCSI bus.
6-5
SSI32B450A
SCSI Controller
SCSI BUS SIGNALS (Continued)
NAME
DESCRIPTION
NUMBER
TYPE
DBP
50
0
DATA BUS PARITY - Parity bit for the SCSI DATA BUS
signals. This signal has the same electrical attributes as
the DBO-DB7 signals. It is always generated when data is
transferred on the SCSI bus. It can be ignored on reception
of data from the SCSI bus by resetting the PERREN bit in
the INTEN1 register.
SRST
12
1/0
SCSI RESET - This signal can be asserted by any of the
SCSI devices on the bus. When it is an input, and the
SRSTEN bit in the INTEN 1 register is set, the INT signal will
be asserted upon detection of an asserted SRST signal on
the SCSI bus. ThiscausestheSRSTINTbitintheiNTSTS1
register to be set by the SSI 32B450A, indicating to the
microprocessor that the INT assertion was caused by the
SRST signal being asserted. As an output it is asserted by
setting the SRST bit in the SCSI1 register.
BSY
10
1/0
BUSY - An active low signal which indicates that the SCSI
bus is being used. It can be asserted by any of the devices
on the SCSI bus. As an output it can be asserted by setting
the BUSY bit in the SCSIO register, or in the course of
executing the SCSI bus control routines internal to the
SSI 32B450A.
SEL
15
110
SELECT - An active low signal which is asserted by the
SSI 32B45OA to (re)select a target (initiator).
REQ
17
110
REQUEST- An active low signal. When the SSI 32B450A
is the initiator it is an input which indicates that the target is
requesting transfer of a byte of data on the bus. When the
SSI 328450A is the target the signal is an output which
requests the initiator to transfer a byte of data overthe bus.
The status of REO can be read in REQ bit in SCSIO.
ACK
11
110
ACKNOWLEDGE - An active low signal. When the
SSI 32B450A is the initiator the signal is an output which is
asserted in response to the REQ input Signal, indicates that
there is valid data on the bus, and completes the handshaking for asynchronous data transfer. When the
SSI 32B450A is the target, this signal is an input from the
initiator in response to the SSI 328450A's REO, and indicates valid data on the SCSI bus. The status on ACK can
be read in ACK bit in SCSIO.
6-6
08BB
SSI328450A
SCSI Controller
SCSI BUS SIGNALS (Continued)
NAME
NUMBER
TYPE
1/5
18
1/0
INPUTIOUTPUT - This signal controls the direction of the
data transfer across the SCSI bus relative to the initiator.
When it is asserted it indicates that data is being input to the
initiator. When it is not asserted it indicates that data is
being output from the initiator. This signal is only driven
when the SSI32B450A is in the target role. During reselection of an initiator by the SSI32B45OA this line will be driven
low.
CID
16
1/0
CONTROLJDATA - This signal is driven when in the target
mode to indicate whether control or data information is on
the DBO - DB7, and DBP lines. When the signal is asserted,
control information is on the bus, and when it is inactive, it
indicates that data is on the bus.
MSG
14
I/O
MESSAGE - An active low signal. When the SSI32B450A
is in the target mode, it is asserted to indicate that the SCSI
communication is in the message portion of the information
transfer phase.
ATN
9
I/O
ATTENTION
An active low signal.
When the
SSI 32B450A is in the initiator mode, this signalis an output
which indicates that a message is ready to be transmitted.
BSYIN
34
0
BUSY IN - Reflects the state of the BSY signal from the
SCSI bus.
BSYOUT
35
I
BUSY OUT - When asserted this signal causes the
SSI 32B450A to initiate arbitration for the SCSI bus. Asserting this signal affects the SS1328450A in the same way
as setting the ARB bit in the COMMAND register. The ARB
bit will not be set by assertion of this signal.
DESCRIPTION
-
DATA TRANSFER INTERFACE
0888
BREQ
30
I
DATA TRANSFER REQUEST -When asserted, this signal
indicates that the peripheral device data transfer control
logic is requesting to transfer of a byte of data, and causes
the SSI 328450A to cycle for a transfer of data.
BACK
31
0
DATA TRANSFER ACKNOWLEDGE - When asserted
indicates that the transfer of data is complete.
LO
32
I
LATCH OUTPUT - Latches data into the SSI328450A. It
is named LATCH OUTPUT because it is latching data out
onto the SCSI bus. It is valid only when data is going out to
the SCSI bus, the target-in and initiator-out modes.
6-7
I
SSI328450A
SCSI Controller
DATA TRANSFER INTERFACE (Continued)
NAME
BIE
00-07
NUMBER
TYPE
33
I
BUS INPUT ENABLE - This signal is active low. It is a
strobe from the data transfer control logic which indicates
it is transferring data from the SCSI bus to the peripheral
device or local buffer. It enables the output drivers for 07DO of .the SSI 32B450A so that data present in the intemal
latch is output.
20-22
24-28
I/O
DATA BUS - Data bus for transfer of data on local (usually
peripheral controller and buffer) bus.
0
INTERRUPT - This is an open drain, active low signal.
When asserted it indicates that an interrupt condition has
occurred as defined in the INTOEN and INT1 EN registers.
The status of the interrupt can be read from the INTOSTS
and INT1 STS registers. The signal is negated when
interrupt status is read.
DESCRIPTION
INTERRUPT CONTROL
INT
36
MICROPROCESSOR INTERFACE
cs
37
I
CHIP SELECT - This is an active low signal. When
asserted it indicates that the microprocessor is selecting
the device and it is enabled to respond to the microprocessor.
RD
42
I
READ - This signalis active low. When asserted it indicates
thatthe microprocessorwants to readfromthedevice. The
ADO-AD3 signals become an output. This signal is gated
internally with CS.
WR
43
I
WRITE - This signal is active low. When asserted it indicates that the microprocessor wants to write to the device.
The ADO-AD3 signals are written to the register pointed to
by the address register. This signal is gated internally with
45-48
1/0
ADDRESS and DATA BUS - Bus which carries device
register address information and bi-directional data.
Whether it is carrying address or data is governed by the
state of ALE.
38
I
ADDRESS LATCH ENABLE - The falling edge of this
signal latches the register address form the ADO-AD3 pins
into the internal address latch.
cs.
ADO-AD3
ALE
6-8
0888
551 32B450A
SCSI Controller
REGISTER DESCRIPTIONS
The SSI32B450A has twelve four-bit registers which control the device and provide status forthe microprocessor.
They are broken into three functional groups; SCSI control, interrupt control, and general control. Register bits
which are Read only are unaffected during writing.
ADDRESS
03
02
01
DO
SELFID
OH
0
SID2
SID1
SIDO
RIW
TRGTID
1H
ITAR
TID2
TID1
TIDO
RIW
COMMAND
2H
RESELEN
SELEN
ARB
unused
RIW
INTENO
4H
WIN
LOSE
SLCTEN
ENDSLEN
RIW
INTSTSO
5H
WON
LOST
SELED
ENDSEL
R
INTEN1
6H
LSBSYEN
PHERREN
SRSTEN
PERREN
RIW
INTSTS1
7H
LSBSYINT
PHERRINT
SRSTINT
PERRINT
R
SCSIO
SH
REO
ACK
BSY
SEL
RIW
SCSI1
9H
SRST
I/O
C/O
MSG
RIW
SCSI2
AH
ONEXFER
reserved
ATNEN
ATN
RIW
CLKPRSC
EH
X
PRSC2
PRSC1
PRSCO
W
RESET
FH
X
X
X
REGISTER
SSI 32B450A REGISTER BIT MAP
0888
6-9
X
ACCESS
W
SSI32B450A
SCSI Controller
REGISTER DESCRIPTIONS
SCSI BUS CONTROL AND STATUS REGISTERS· BIT DESCRIPTION
SELFID
OH
READIWRITE
Self 10 number - Contains the binary equivalent of its own SCSI 10.
BIT
NAME
3
reserved
2-0
S102-S100
DESCRIPTION
Must always be written as reset, always reads as reset.
SELF 10 - Binary equivalent of device's SCSI 10. SI02 is the
most significant bit.
The SELFIO register is not affected by assertion of RST.
TRGTID
1H
READIWRITE
Target 10 number - Contains the binary equivalent of the connecting SCSI device's 10 in TI02-TIDO.
BIT
NAME
3
ITAR
INITIATORITARGET ROLE - When set indicates the device is
in the initiator role and will select the target defined by the TID
after arbitration has been won. When reset indicates the device
is in the target role and will reselect an initiator defined by TID.
This bit must be defined prior to beginning arbitration. When the
device is selected by another SCSI device this bit is cleared and
when reselected it is set.
2-0
T102-T100
TARGET 10 NUMBER - These bits are the binary equivalent of
the connecting device's SCSI 10. TID2 is the most significant
bit.
DESCRIPTION
The TRGTIO register is not affected by assertion of RST.
6-10
0888
SSI32B450A
SCSI Controller
SCSI BUS CONTROL AND STATUS REGISTERS· BIT DESCRIPTION (Continued)
COMMAND
2H
READIWRITE
Command - Controls whether the SSI 32B450A will respond to selection, reselection, and initiation of
arbitration.
BIT
NAME
3
RESELEN
RESELECT ENABLE - When set, the SSI 32B45OA will respond to a reselect or select request from another SCSI device.
2
SELEN
SELECT ENABLE - When set, the SSI 32B45OA will only
respond to a select request from another SCSI device.
1
ARB
ARBITRATE - When set, causes the SSI 32B450A to begin arbitration for the SCSI bus (re)select a target (initiator).
0
unused
DESCRIPTION
Read only, always set.
The COMMAND register is reset (except bit 0) on assertion of RST.
SCSIO
8H
READIWRITE
SCSI 0 - SCSI control and status register O.
BIT
NAME
3
REQ
REQUEST - This read only bit reflects the state of the REO pin.
2
ACK
ACKNOWLEDGE - This read only bit reflects the state of the
ACKpin.
1
BSY
BUSY - The EmY signal is asserted when this bit is set and
negated when it is reset. When this register is read, this bit
reflects the state of the BSY pin.
0
SEL
SELECT - This read only pin reflects the state of the SEL pin.
DESCRIPTION
The BSY bit of the SCSIO register is reset on assertion of RST. All other bits remain unaffected.
0888
6-11
SSI32B450A
SCSI Controller
SCSI BUS CONTROL AND STATUS REGISTERS· BIT DESCRIPTION (Continued)
SCSI1
9H
READIWRITE
SCSI 1 - SCSI control and status register 1.
BIT
NAME
DESCRIPTION
3
SRST
SCSI RESET - The SRST signal Is asserted when this bit is set
and negated when this bit is reset. When this register is read,
this bit reflects the state of the SRST pin.
2
lie
INPUT/OUTPUT - The lie signal is asserted when this bit is set,
the ITAR bit of the TRGTID register is reset, and the BSY signal
is asserted. It is negated when this bit is reset. when this
register is read, this bit reflects the state of the lie pin.
1
C/D
CONTROUDATA - The C/O signal is asserted when this bit is
set, the ITAR bit in the TRGTID register is reset, and the BSY
signal is asserted. It is negated when this bit is reset. When this
register is read, this bit reflects the state of the C/O pin.
0
MSG
MESSAGE - The ~ signal is asserted when this bit is set, the
ITAR bit in the TRGTID register is reset and the BSY signal is
asserted. It is negated when this bit is reset. When this register
is read, this bit reflects the state of the MSGpin.
The SCSI1 register is reset on assertion of RST.
SCSI2
AH
READIWRITE
SCSI 2 - SCSI control and status register 2.
BIT
NAME
DESCRIPTION
3
ONEXFER
2
reserved
Must always be written as reset, always reads as reset.
1
ATNEN
ATN ENABLE, R/W - When set it enables the ATN signal to be
ONE TRANSFER, R/W - When set a byte of information is
transferred from the internal data latch across the SCSI bus.
Upon completion of the transfer the bit will automatically be
reset, and therefore reflects the status of the data transfer.
asserted by the SSI 32B45OA at the end of arbitration plus the
bus settle and clear delay times when it Is reselecting the
initiator. The ATN bit (SCSI2 bit 0) is set when selecting a target
and ATNEN bit Is set.
0
ATN
ATIENTION - The ATN signal is asserted when this bit is set
and negated when it is reset. When this register is read it
reflects the state of the ATN pin.
The SCSI2 register is reset on assertion of the SRST.
6-12
0888
SSI32B450A
SCSI Controller
INTERRUPT CONTROL AND STATUS REGISTERS· BIT DESCRIPTION
INTENO
4H
READIWRITE
Interrupt Enable 0 - Controls interrupt mode enable.
BIT
NAME
DESCRIPTION
3
WIN
WIN ENABLE - When set enables the INT signal to be asserted
when SCSI arbitration is won.
2
LOSE
LOSE ENABLE - When set enables the INT signal to be
asserted when SCSI arbitration is lost.
1
SLCTEN
SELECTED ENABLE - When set enables the INT signal to be
asserted when the SSI 32B450A has been selected or reselected by another SCSI device.
0
ENDSLEN
END SELECT ENABLE - When set enables the INT signal to be
asserted at the end of the SSI 32B450A's selection process.
This indicates that the SCSI device being (re)selected has responded properly.
The INTENO register is reset on assertion of RST.
INTSTSO
5H
READ ONLY
Interrupt status 0 - Provides information on cause of assertion of INT signal.
BIT
NAME
DESCRIPTION
3
WON
WON ARBITRATION - The SSI 32B450A has won arbitration
and SEL is not active on the SCSI bus at the end of the
arbitration phase. Indicates that no higher priority SCSI device
was arbitrating for the SCSI bus.
2
LOST
LOST ARBITRATION - The SS132B450A has lost arbitration.
This means that a device with a higher I D is on the bus or that
SEL is (has become) active during arbitration time.
1
SELED
SELECTED - The SSI 32B450A has been (re)selected by
another SCSI device. The ID of the other device is in the
TRGTID register.
0
ENDSEL
END SELECT
The SSI32B450A has completed
(re)connection to the SCSI target (initiator) device with ID in the
TRGTID register.
-
The INTSTSO register is reset on assertion of RSTor on read of this register.
0888
6-13
SSI328450A
SCSI Controller
INTERRUPT CONTROL AND STATUS REGISTERS - BIT DESCRIPTION (Continued)
INTEN1
6H
READ/WRITE
Interrupt enable 1 - Controls interrupt mode enable.
BIT
NAME
3
LSBSYEN
LOST BUSY ENABLE - When set enables the INT signal to be
asserted when the BSY signal on the SCSI bus has been
negated.
2
PHERREN
PHASE ERROR ENABLE - When set enables the INT signal to
be asserted when a phase error has been detected by the
SSI 32B450A during an information or data transfer phase.
1
SRSTEN
SCSI RESET ENABLE - When set enables the INT signal to be
asserted when the SRST signal has been asserted on the SCSI
bus.
0
PERREN
PARITY ERROR ENABLE - When set enables the INT signal
to be asserted when a parity error is detected by the
SSI 32B450A parity check circuitry.
DESCRIPTION
The INTEN1 register is reset on assertion of RST.
INTSTS1
7H
READ ONLY
Interrupt Status 1 - Provides information on cause of assertion of INT signal.
BIT
NAME
3
LSBSYINT
LOST BUSY - The BSY signal on the SCSI bus is no longer
active.
2
PHERRINT
PHASE ERROR - A phase error was detected by the
SSI 32B450A during the information or data transfer phase.
1
SRSTINT
SCSI RESET - The SRST signal is active on the SCSI bus.
0
PERRINT
PARITY ERROR - A parity error occurred during information or
data transfer phase.
DESCRIPTION
The INTSTS1 register is reset on assertion of RST, or on Read of this register.
6-14
0888
SSI328450A
SCSI Controller
GENERAL CONTROL REGISTERS
CLKPRSC
EH
WRITE ONLY
CLOCK PRESCAlE - Value to prescale the internal clock from the ClK input.
BIT
NAME
DESCRIPTION
3
x
2
PRSC2
CLOCK PRESCAlE 2
1
PRSC1
CLOCK PRESCAlE 1
0
PRSCO
CLOCK PRESCAlE 0 - Clock input frequency is divided as
follows:
don't care
PRSC2
PRSC1
PRSCO
DIVISOR
0
0
0
1
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
1
1
0
5
6
1
1
1
7
The ClKPRSC register is not affected by RST.
RESET
FH
WRITE ONLY
RESET - Software reset for the device.
BIT
NAME
3-0
x
DESCRIPTION
Don't care - A write to this register of any value will cause a
software reset to occur in the same way as asserting the RST
pin.
Register locations 3H, BH, CH, and DH are reserved for future definition.
0888
6-15
SSI32B450A
SCSI Controller
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Ambient Temperature Under Bias
RATING
UNIT
Oto 70
°C
-65 to 150
°C
Voltage With Respect to Ground SCSI Bus Signals
-0.5 to 10.0
V
Voltage With Respect to Ground All Other Pins
-0.5 to 7.0
V
±20
rnA
Storage Temperature
Maximum Current Injection
Note: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress rating only and functional operation ofthedevice atthese or any other conditions above
those indicated in the operational section of this data sheet is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
PARAMETERS
CONDITIONS
VCC Supply Voltage
TA Operating Free Air Temperature
MIN
NOM
MAX
4.75
5.00
5.25
V
70
°C
0
UNIT
D.C. CHARACTERISTICS
TA = 0 °C to 70°C; VCC = +5V ±5% Recommended operating range unless otherwise specified.
SCSI BUS SIGNALS
PARAMETERS
CONDITIONS
MIN
NOM
MAX
UNIT
2.0
V
VIH
Input High Voltage
VIL
Input Low Voltage
0.8
1.3
V
IIH
Input High Current
VIN
=5.0V
-50
+50
~
ilL
Input Low Current
VIN
=0.5V
-50
+50
VOL
Output Low Voltage
IOL
=48.0 rnA
~
V
IOL
Output Low Current
VOL
=0.5V
H
Hysterisis
1.5
VCC=5.0V
Ta = 25°C
Power Dissipation
0.5
48.0
rnA
0.4
V
0.600
6-16
mW
0888
SSI32B450A
SCSI Controller
DATA BUS SIGNALS: 07 - DO
PARAMETERS
CONDITIONS
MIN
NOM
MAX
UNIT
VIH
Input High Voltage
1.5
2.0
V
VIL
Input Low Voltage
0.8
1.3
V
H
Hysterisis
IIH
Input High Current
Vin
= 2.4 V
-20
+20
ilL
Input Low Current
Vin
=0.5V
-20
+20
IlA
IlA
VOL
Output Low Voltage
IOL
=8.0rnA
IOL
Output Low Current
VOL
=0.5V
VOH
Output High Voltage
IOH
= -4.0 rnA
IOH
Output High Current
V
0.4
0.5
4.0
V
rnA
2.4
V
-4.0
rnA
ALL OTHER SIGNALS
PARAMETERS
0888
VIH
Input High Voltage
VIL
Input Low Voltage
CONDITIONS
MIN
NOM
MAX
UNIT
V
2.0
0.6
V
IIH
Input High Current
Vin
=2.4V
-20
+20
ilL
Input Low Current
Vin
=0.5V
-20
+20
IlA
IlA
VOL
Output Low Voltage
IOL
=2.0 rnA
0.5
V
IOL
Output Low Current
VOL
=0.5V
2.0
rnA
VOH
Output High Voltage
IOH
= -500 IlA
2.4
V
IOH
Output High Current
-500
6-17
IlA
I
SSI32B450A
SCSI Controller
ELECTRICAL SPECIFICATIONS (Continued)
CLOCK (ClK) TIMING (See Figure 1)
PARAMETERS
MIN
T IClK IClK width
TIClKl2 IClK half-cycle
NOM
MAX
UNIT
200
340
ns
100
170
ns
NOTE: IClK (internal clock) is the signal internal to the SSI 32B450A based on the ClK input. It will
have a 50% duty cycle if the prescale factor programmed in the ClKPRSC register is greater than one.
DATA TRANSFER INTERFACE TIMING • INITIATOR IN (See Figure 2)
MIN
PARAMETERS
NOM
MAX
ns
0
TARH ACK J, to REO i
UNIT
5
80
ns
T RAH REO ito ACK i
5
100
ns
T BRA BREO i to ACK J,
SS132D532
HRZ
DBo-DB7
~
:z:
~
c
!ii!
~
!iI
~
;
~
_1'11'
~ ~
~ ~
~.!
8OC51
'FlIT
1RTO
AL2
~
IE::f.'
XTAl1
vss
SCSI PERIPERAL CONTROLLER CHIP SET
en
o
en en
-en
0-
OW
::IN
-ID
... ~
2.01
-0
~l>
SSI32B450A
SCSI Controller
PACKAGE PIN DESIGNATIONS
(TOP VIEW)
7
6
5
4
3
2
1 52 51 50 49 46 47
SGND
8
48
AD2
l\TIQ'
9
45
AD3
BSY
10
44
Vee
lICK
11
43
WI'!
SRST 12
42
mr
0
SGND
13
MSG
14
40
eLK
"SEC
15
39
RST
em
16
38
ALE
11ECl
17
37
36
"CS
TNT
I/U
18
SGND
19
35
BSYOUT
DO
20
34
BSYIN
21 22 23 24 25 26 27 28 29 30 31 32 33
PLCC
ORDERING INFORMATION
ORDER NO.
PART DESCRIPTION
SSI 328450A SCSI Controller
52-Pin PLCC
SSI 328450A-CH
PKG.MARK
328450A-CH
No responsibility is assumed by SSi for use of this product nor for any infringements of patents and trademarks or other rights of third parties
resulting from its use. No license is granted under any patents, patent rights or trademarks of SSi. SSi reserves the right to make changes
in specifications at any time without notice.
Silicon Systems, Inc., 14351 My10rd Road, Tustin,
CA 92680 (714) 731-7110, TWX 910-595-2809
©1988 Silicon Systems, Inc.
0888
6-36
SSI328451
SCSI Controller
INNOVATORS IN INTEGRATION
August, 1988
DESCRIPTION
FEATURES
The SS1328451 SCSI bus interface device is designed
to adapt a peripheral controller (target) system to a
small computer system interface (SCSI) bus.
•
As a target adapter, the SSI 328451 contains circuitry
to complement the logic of the SSI 32C453 Dual Port
Buffer Controller for SCSI arbitration; SCSI REQ/ACK
handshake; and parity generation and checking. In its
role as a target SCSI adapter, the circuitry on the
device maximizes SCSI bus performance in all phases
and ensures conformance with the SCSI specification.
The SSI 328451 includes high current drivers and
Schmitt trigger receivers which allow for direct connection to the SCSI bus for the single ended interfacing
option. The SSI 328451 is intended for use in designs
based around the SSI 32C452 storage controller and
the SSI 32C453 Dual Port 8uffer Controller.
•
•
•
•
•
•
suppons asynchronous data transfer up to
1.5 Mbyteslsec
suppons target role In SCSI applications
Includes high current drivers and Schmitt trigger
receivers for direct connection to the SCSI bus
Full hardware compliance to ANSI X3T9.2 Rev.
17B speclflcatlon as a target peripheral adapter
Contains circuitry to suppon SCSI arbitration,
(re)selectlon and parity features
Complements the SSI 32C453 Buffer controller
Plug compatible with AIC 500L
•
•
Single +5V supply
•
Fabricated In 2 micron CMOS technology
Available In 44 pin PLCC
BLOCK DIAGRAM
0888
6-37
551328451
SCSI Controller
FUNCTIONAL DESCRIPTION
The purpose ofthe SSl32B451 is to fulfill a support role
within a hardware design. The device contains four
circuit functions which interact within the overall design. The partial schematic In Figure 10 Illustrates this
interaction. This section describes each of the functional circuits.
DATA TRANSFER INTERFACE
The data transfer interface logic coordinates the transfer of data between the data transfer logic and the SCSI
bus. Standard two-wire DMA handshaking is supported by the BREO and BACK signals. This section
is organized to connect directly with the SSI 32C453,
Dual Port Buffer Controller, but is easily connected to
any other data transfer control device. Before DMA
controlled information transfer can begin, a valid connection must exist to the SCSI bus with BSY active and
no phase error. The direction of information flow is
controlled by the 1/0 In signal from the storage controller or a latch.
The device complements the buffer controller handshake timing by latching the SCSI data before transferring into the controller buffer. This speeds the data
transfer across the bus by reducing the REQlACK
timing restraints for the SCSI bus transfers.
In the target-in state (read operation), the data is being
transferred from the peripheral controllerto the initiator
or the host. The buffer controller device controls when
the buffer is accessed to pass on to the device. Once
valid data is present on 00-07 of the buffer data, LO is
asserted, latching data into the device. The buffer
controller then asserts BREO, indicating to the device
that valid data is in the internal latch ready to be
transferred overthe SCSI bus. The device then places
data on the SCSI bus and then asserts REO. The data
setup time required by SCSI specification is dictated
primarily by the buffer controller. The host (initiator)
asserts ACK indicating acceptance of the SCSI data
transfer cycle. The device asserts BACK to the buffer
controller logic indicating completion of that cycle.
Refer to Read Operation timing diagram (Figure 4) for
an illustration of this handshake.
In the target-out state (write operation), the data is
being transferred from the initiator to the buffer upon
the control of the buffer controller. The buffer controller
asserts BREO requesting transfer of a byte of data
from the initiator. The device, in tum, asserts REO and
the initiator responds by driving the SCSI data bus and
asserting ACK which latches data into the device.
BACK is asserted by the device indicating that the byte
is latched inside the device and is available to be
transferred to the buffer RAM. The buffer controller
then asserts BIE to enable output of the data to the
RAM. When the buffer controller has completed transferring the data it negates BIE and BREO indicating to
the device that the cycle is complete. Refer to Write
Operation timing diagram (Figure 3) for an illustration
of this handshake.
ARBITRATION
The purpose of this block is to complement the logic in
the SSI 32C453, buffer controller device, for SCSI bus
arbitration during selection of the target controller or
reselection of the initiator phases. The device simply
passes along the SEL and BSY signals as SEL IN and
BSY IN, respectively. It also monitors the control line
BSYOUT received from the buffer controller chip for a
minimum of three clock periods and a maximum of four
clock periods (Bus-Free Delay) after which time it
outputs BSY.
Once the device has performed these functions it
leaves the actual arbitration activity to the local microcontroller and the buffer controller. Refer to the SSI
32C453 specification for details of this activity.
The SCSI signals SEL, SELOUT, BSY and BSYOUT
received from the buffer controller are internally inverted and become SELIN, SEL, BSYIN and BSY,
respectively. The actual monitoring of these lines for
SCSI timing specification is accomplished by the buffer
controller. The actual arbitration activity for the SCSI
bus is performed by the buffer controller device and the
local microcontroller. Refer to the SSI 32C453 specification for the timing of this activity.
PARITY GENERATION
Parity functions as 'Odd' parity only. For incoming
data, the SSI 32B451 checks parity or computes and
passes the computed bit to the buffer RAM depending
upon the condition of PARIRST line. For outgoing
data, the device always computes parity on the data
and presents to the SCSI bus.
6-38
0888
551328451
SCSI Controller
For the incoming SCSI data, the device generates
parity intemally and compares it against the parity bit
received ifthe PARIRST line is high. The resuH ofthis
comparison is latched at the PAR/ERR output signal.
An error is indicated by a high signal atthis output. To
clear the error condition, the PAR/RST line must be
driven to a low level.
AHematively, if PAR/RST is held low, the device computes parity on incoming SCSI data and presents this
parity bit at the PAR/ERR output. This value can be
stored in the buffer RAM for parity checking at a later
time.
For outgoing data, parity is always generated and
presented for the SCSI bus on the DBP line by the
device.
NOTE: Parity, as a function of SCSI, is optional.
However, the SSI32B451 ignores this and works parity
continuously. The surrounding design has responsibility of either monitoring parity or ignoring it.
SCSI INTERFACE
Drivers and receivers are provided intemallyto the SSI
32B451 for direct connection to the SCSI bus. The only
components necessary outside of the chip are the pullup and pull-down resistors forthe interface and receivers for SCSI Attention and Reset signals. The data and
parity signals received from the SCSI bus are passed
along to the Data Transfer Interface and parity circuits
described above. The data and parity bits to be sent
over to the SCSI bus are buffered by this circuit.
PIN DESCRIPTION
This section describes the names of pins, their symbols, their functions and their active states. The signals
are grouped in four categories according to their interface to other components on the board. The four
categories area:
SCSI Bus Interface
Buffer Controller/Buffer RAM Interface
Storage Controller Interface
Others
SCSI BUS INTERFACE
The following group of signals interface directly to the SCSI bus. All output and bi-directionallines have 48 mA
sinking current capability. All input buffers are Schmitt trigger inputs and all outputs have high current open
drain buffers to allow direct connection to the SCSI bus.
OBBB
NAME
PIN #
TYPE
I/O
DESCRIPTION
DBO-DB7
13-17
19-21
SCSI
I/O
Data Bus. Buffered data bus signals interface directly to
SCSI bus.
DBP
10
SCSI
I/O
Data Bus Parity. Parity bit for the SCSI data bus signals. It is
always generated when data is transferred on the SCSI bus. It
can be ignored on reception. Active low.
ACK
7
SCSI
I
Acknowledge. This signal is an input from the initiator in
response to the SSI 32B451 's REO, and indicates valid data on
the SCSI bus. Active low.
SEL
23
SCSI
I/O
Select. Active low signal used by an initiator (the host) to select
a target or by a target to reselect an initiator.
6-39
551328451
SCSI Controller
SCSI BUS INTERFACE (Continued)
PIN#
TYPE
1/0
DESCRIPTION
BSY
25
SCSI
1/0
Busy. Active low. An "OR-tied" signal that indicates the bus is
being used.
MSG
11
SCSI
0
Message. Open drain SCSI signal. Signal driven by the device
to indicate that the SCSI communication is in the message
phase. Active low.
C/O
27
SCSI
0
Command/Data. Open drain SCSI signal driven by the device
that indicates control or data information is on the data bus.
REO
22
SCSI
0
Request. Active low true signal driven to request data byte
transfers. Also, used to "Acknowledge" at completion of transfer.
i/O
26
SCSI
0
Input/Output SCSI signal that controls the direction of data
movement on the SCSI bus with respect to the initiator.
NAME
BUFFER CONTROLLER/BUFFER RAM INTERFACE
The following group of signals are associated with buffer data and control. All signals except the buffer data
signals interface to the SSI 32C453, Dual Port Buffer Controller.
NAME
PIN#
TYPE
1/0
BREa
35
TIL
I
Buffer Request. When asserted, this signal indicates that the
peripheral buffer controller is requesting to transfer a byte of
data. Active high input.
BACK
6
TIL
0
Buffer Acknowledge. When asserted this signal indicates
acceptance of data transfer. Active high output.
LO
38
TIL
I
Latch Out Latches data into the device to be presented to the
SCSI bus. Active high.
BIE
39
TIL
I
Bus In Enable. Active low. A strobe from the data transfer
control logic which indicates it is transferring data from the SCSI
bus to the local buffer.
BOE
5
TIL
I
Bus Out Enable~ Active low. A strobe from the data transfer
control logic which indicates it is transferring data from the local
buffer to the SCSI bus.
ET
8
TIL
I
Target Enable. Active low. A signal connected to the SSI
32C453. When this signaHs active it provides microcode and
hardware control to enable all drivers except Busy on the SCSI
bus.
DESCRIPTION
6-40
0888
551328451
SCSI Controller
BUFFER CONTROLLER/BUFFER RAM INTERFACE (Continued)
NAME
PIN'
TYPE
I/O
DESCRIPTION
SELIN
29
TTL
0
Select In. Active high. Used to pass the select line from the
SCSI bus to the buffer controller.
SELOUT
28
TTL
I
Select Out. Active high. Used as an input from the buffer
controller to indicate when to drive the select line on the SCSI
bus.
BSYIN
31
TTL
0
Busy In. Active high. Used to pass busy from the SCSI bus to
the buffer controller. Indicates other devices are actively
accessing the bus.
BSYOUT
32
TTL
I
Busy Out. Active high. Used as an input from the buffer
controller to indicate when to drive the busy line on the SCSI
bus.
2-4
40-44
TTL
I/O
00-07
Buffer Data. These lines connect to buffer RAM data pins.
STORAGE CONTROLLER INTERFACE
The following group of pins interface with the SSI 32C452, Storage Controller. These lines may also be
connected to an output port of a microcontroller or a latch.
NAME
PIN'
TYPE
I/O
MSGIN
9
TTL
I
Message In. Active high signal from the storage controller
drives the SCSI MSG signal low.
I/O IN
33
TTL
I
I/O In. A high signalfrom the storage controller drives the SCSI
i/O signal low.
C/D IN
30
TTL
I
C/D In. A high signal from the storage controller drives the SCSI
C/D signal low.
DESCRIPTION
OTHERS
The following group of lines are the miscellaneous signals.
NAME
0888
PIN'
TYPE
I/O
DESCRIPTION
CLK
34
TTL
I
Clock. Used for clock input between 2.5 MHz and 5 MHz. This
signal is used internally during the arbitration phase only.
PAR/ERR
37
TTL
0
Parity/Error. Logic 1 indicates a parity error detected on the
SCSI bus when PAR/RSTis held high. When the PARlRSTline
is held low, parity will be passed to the controller buffer by using
the PAR/ERR line as the parity bit for each byte.
6-41
I
•
SSI328451
SCSI Controller
OTHERS (Continued)
NAME
PIN#
TYPE
I/O
36
TIL
I
PAR/RST
GND
12,18,
24
VCC
1
DESCRIPTION
Parity/Reset. When held high, the device checks SCSI bus
parity error by setting logic 1 (high) onthe PARIERR pin. When
held low, parity is passed through the device to the controller
buffer with the PARIERR line being the parity bit.
Ground. Device system ground.
Power Supply. +5V input for power to the device.
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
(Maximum limits indicate where permanent device damage occurs. Continuous operation at these limits is
not intended and should be limited to those conditions specified in the DC Operating Characteristics.)
PARAMETER
VCC with respect to VSS (GND)
Max. voltage on any pin with respect to VSS
-
Operating temperature
Storage temperature
RATING
UNIT
+7
V
-0.5 to +7
V
Oto 70
°C
-55 to +125
°C
DC OPERATING CHARACTERISTICS
(Ta '" 0 to 70°C, VCC '" +5V ± 5%, VSS '" OV)
PARAMETER
CONDITION
MIN
MAX
UNITS
ilL
Input Leakage
(BREQ, LO, BOE, BIE, ET
SELOUT, BSYOUT, CDIN,
IIOIN, MSGIN, PARIRST,
CLK,ACK)
0< Vin< VCC
-10
+10
W\
10L
SCSI Output Leakage
(SEL, BSY, DBO-DB7,
DBP, MSG, C/D, 1/0)
0.5 < Vout < VCC
-50
+50
W\
10L
DO-D7
0.45 < Vout <
-10
+10
W\
VIL
Input Low Voltage
0
0.8
V
vec
6-42
0888
SSI328451
SCSI Controller
DC OPERATING CHARACTERISTICS (Continued)
PARAMETER
CONDITION
MIN
MAX
UNITS
2.0
V
2.4
V
VIH
Input High Voltage
VOH
Output High Voltage
IOH = -400 ~
VOL
SCSI Output Low Voltage
IOL = 48 mA
0.5
VOL
All others
IOL= 2 mA
0.4
V
500
mW
Power Dissipation
V
Vhsy
Hysteresis Voltage
(all SCSI signals)
mV
Ices
Standby Current
Ta = 70°C
600
~
Icc
Supply Current
Ta = 70°C
30
mA
Cin
Input Capacitance
15
pF
200
AC CHARACTERISTICS
The following sections list the timing characteristics necessary forthe proper operation of the device. Unless
otherwise specified, all timing parameters pertain to input clock frequency (2.5 MHz min. to 5.0 MHz max.).
Note: AC timing is measured at Voh = 2.0V, Vol = 0.8V, Cin = 50 pF. Timing characteristics are valid over
the entire operating temperature, 0 to 70°C, and voltage range, 4.75 to 5.25 volts.
CLOCK AND PARITY TIMING (See Figures 1 & 2)
SYMBOL
PARAMETER
MIN
MAX
UNITS
TICLK/2
Input Clock Half-Cycle
100
200
ns
TICLK
Input Clock Width
200
400
ns
DPV
Data Valid to Parity Detect
100
ns
PARlm'I'
~~_ _ _ _ _ __
_TI_~L_K ---IM4---- _TI_~L_K
1 4 - - - - - - TICLK - - - - - - . J
HIGH _ ODD PARITY
PAR/ERR
I4--DPV
FIGURE 1: Input Clock Timing
0888
FIGURE 2: SCSI Bus Parity Timing
6-43
I
551328451
SCSI Controller
WRITE OPERATION TIMING (See Figure 3)
SYMBOL
PARAMETER
t
MIN
to REO J,
TREO
BREO
TARO
ACK J, to REO
TACK
ACK J, to BACK
TBREO
BREO J, to BACK J,
TDH
BIE
TDV
SCSI Data Valid to ACK J,
TPER
BREO J, to Parity Error Valid
PAFV~
t
t
to Data Invalid
UNITS
21
ns
55
ns
50
ns
25
ns
40
ns
55
ns
45
ns
\~_ _ _ _ _ _ _ _~/
_____
\
SELIN
llllC5-~
t
MAX
VAllO
-------
X'-______
BACK
BREa
_
___
~~~-RE-a-----------4
J
},
PAFVERR - - - - - - - - - - - - - - - X r - - -H-1G-H .-0-0-0- - - - - X , . . . - - - - - - - - T - P - E ) j ( : G H . PARITY ERROR
0: ------------------------y-,>8E---"'---I-'x,~o >C
Note: Data from host - SCSI initiator - is transferred to buffer RAM.
FIGURE 3: Write Operation Timing
6-44
0888
551328451
SCSI Controller
READ OPERATION TIMING (See Figure 4)
MIN
MAX
UNITS
SYMBOL
PARAMETER
TBDS
Buffer Data Valid to LO ..!.
0
ns
TBDH
LO ..!. to Buffer Data Invalid
25
ns
TDBO
Buffer Data Valid to BREO i
90
ns
TRO
SCSI Bus Data Valid to REO ..!.
55
ns
TARO
ACK ..!.to REOi
55
ns
TACK
ACK ..!. to BACK i
55
ns
TARO
ACK ito REO..!.
55
ns
TBREO
BREO ..!. to BACK ..!.
25
ns
TOE
BCE to SCSI Data Valid
35
ns
~~
LO
DQ.D7
/
1I-f
I
\
/
X
VALID
X
lOBa
BREQ
"I:Im-¥ITt
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- J
VALID
VALID
__
BACK
-----m-RE-Q~~__________
Note: Data read from peripheral drive is transferred to the host - SCSI initiator
FIGURE 4: Read Operation Timing
0888
6-45
551328451
SCSI Controller
ARBITRATION AND CONTROL SIGNAL TIMING (See Figures 5 & 6)
MIN
SYMBOL
PARAMETER
TSELO
SELOUT t or J.. to SEL J.. or t
TBOT
BSYOUT t or J.. to BSY J.. or
TCNT
MSGIN, VOIN, COIN to MSG, Tlo, C/O
t
3xTICLK
MAX
UNITS
35
ns
ns
ns
4xTICLK +40
35
--J/
n~~____________________________________
~L:
__C1
~----------~/
~~_ _ _ _ _~~
\~--------------------------~;-
eLK
TlIOT
..."
~,~,--------------~/
FIGURE 5: Arbitration Signals Timing
r r \_______________
MSGIN.~~
~.ga
L"~
______
--9
FIGURE 6: SCSI Control Signal Timing
6-46
0888
551328451
SCSI Controller
APPLICATION NOTES
The SSI 32B451 supports the SSI 32C453 and the
local microprocessor in performing all the SCSI target
controller functions. For successful SCSI bus operation, the target controller must follow all the requirements of the SCSI protocol defined by ANSI specification X3T9.2 Rev. 17B. An overview of a typical SCSI
signal sequence is shown in Figure 7.
Before any SCSI operations can begin, the local microprocessor polls the BSY line through the SSI 32C453
(BSYIN signal). When this signal is asserted, the
microprocessor checks the arbitration 1.0. asserted by
the initiator.
Following the Arbitration phase, the SCSI bus enters
the Selection phase. SSI 32B451 assists the Arbitration and Selection phases by passing the two control
Signals, BSY and SEL, and the SCSI 1.0. to the SSI
32C453 and the local buffer, respectively. Otherphases
following Arbitration and Selection are command, data
in, data out, status, message in and message out.
Table 1 shows the various phases and their sources.
Table 2 shows the various control signal status during
different SCSI phases. Being a target device, the SSI
32B451 drives these control lines out on the SCSI bus.
The SSI 32B451 requires local microprocessor supervision for successful operation over the SCSI bus.
Firmware supportforthe local microprocessor consists
of various routines. Flow charts for these routines are
shown in Figures 8 and 9.
SCSI SPECIFIC INFORMATION
This information from the ANSI Standard forthe Small
Systems Computer Interface is provided to assist in
implementing a SCSI based controller with the SSI
32B451.
TABLE 1 : Bus Phase Signal Sources
SIGNALS
BUS PHASE
0888
BSY
SEC
aD,TIO,
ACKIATN
DB7-DBO
~REQ
Bus Free
None
None
None
None
None
Arbitration
All
Winner
None
None
SCSI 10
Selection
I&T
Initiator
None
Initiator
Initiator
Reselection
I&T
Target
Target
Initiator
Target
Command
Target
None
Target
Initiator
Initiator
Data In Target
Target
None
Target
Initiator
Target
Data Out
Target
None
Target
Initiator
Initiator
Status Target
Target
None
Target
Initiator
Target
Message In
Target
None
Target
Initiator
Target
Message
Target
None
Target
Initiator
Initiator
6-47
I
SSI328451
SCSI Controller
DEFINITIONS FOR TABLE 1
All:
I&T:
This signal is driven by the initiator, target or
both as specified in the selection or reselection phase.
The signal is driven by all SCSI devices
which are actively arbitrating.
SCSI 10: The SCSI 10 is a unique data bit (DB) for
each of the SCSI devices in the system and
is driven onto the SCSI bus by each device
that is actively arbitrating. The other seven
data bits shall not be driven by the SCSI
device. The parity bit may be asserted or
undriven during arbitration but can't be driven
false.
Initiator: Ifthis signal is driven it can be driven only by
the active initiator.
None:
The signal is released meaning it is not
driven by any SCSI device.
Winner:
The signal shall be driven by the one SCSI
device that wins arbitration.
Target:
If the signal is driven it can be driven only by
the active target.
TABLE 2: Signal Status, Information Transfer Phases
SIGNALS
PHASE NAME
DIRECTION OF TRANSFER
1
Data Out
Initiator to Target
1
0
Data In
Initiator from Target
1
0
1
Command
Initiator to Target
1
0
0
Status
Initiator from Target
0
1
1
#
0
1
0
#
0
0
1
Message Out
Initiator to Target
0
0
0
Message In
Initiator from Target
MSG
00,
Tlo
1
1
1
# = Reserved for future standardization
6-48
0888
o
en
en
en
Ir
Bus Free Delay
Bus Set Delay
Bus Clear Delay
Arbitration Delay
Bus Settle Delay
1
r
Bus Clear plus Bus Settle Delays
I
BSY
"SIT
+
Target
Asserts
Initiator
Asserts
~
~/O
m
I
va
co
MS.
/
tim
/ ' '-----7~
7iCK
V- ~ V-
OB7-0BO,
OBP
'
,& 7 /1'
r'-J
h
Arnjt~tinn
Bus Free]
Phase
Phase
~
"/
'"
"- /
/
Command
Phase
Phase
'\ ~
/ /'
~
~
-.J
r
,P'
/'
r
h
"Comm~
last
Command
Byte
~QI':tinn
"- "- -
~ -f----/ ~~ ~ c-f----/ ~ -f----/ ~ -
h
Arb Target and Initiator
First
10's
10's
Command
Byte
"~P'
// /'
M.
Data-In
Phase
FIGURE 7: SCSI Signal Sequence Example
Status
Phase
..
.g
In
Phase
e""
Free
Phase
en
oen
-en
oen
0::sW
am
-I\)
=~
(DUl
.........
SSI328451
SCSI Controller
oro
ASSERT
SELOUTIN
32C453 IFCON
REGISTER
T
SETUP
32C453
SAP AND RAP
REGISTERS
WRITE TO
32C453 HOSTL
TO INITIATE THE
TRANSFER
TO INFO OUT.
BUS FREE OR
INFO IN PHASE
TO
RES ELECTION
PHASE
TO INFO
TRANSFER
PHASE
Note: Info In phase includes
Message In. Status, and Data In
phases.
The code for the Info Out phase
is very similar to this description
of the Info In phase.
FIGURE 8: Flow Charts for Various SSI 328451 Routines
6-50
0888
SSI328451
SCSI Controller
READS SCSI INPUT
LINES
CHECKS FOR RESET
AND ERRORS
PHASE
ERROR?
YES
)----------------1
TO BUS FREE
STATE
FIGURE 9: SCSI Background Routines Using SSI 32B451
U1
LS240
NRZ
MSG1N
IIOIN
RG
ClOIN
WG
WAMIAMD
00-07
STORAGE
CONTROLLER
ClK
SCSI
SS132C452
INTERFACE
DEVICE
ROIRFCLK
AlWAMP
ENDECIDATA
SEPARATOR
WIlT
SSI3205321
WSO/GPIQO
WS1JGPI01
SSI328451
DUAL
BUFFER
SSI32C453
=
~
ADO-AD7, 110, WII, CS, ALE
MICROBUS
PAAlERR
PARiRST
U1
LS240
mrr------~/r----L
MICROCONTROLLER
________~
FIGURE 10: Partial Schematic for SCSI Implementation with Arbitration Support Using SSI 32B451
0888
6-51
SSI32R510
551328451
SCSI Controller
PACKAGE PIN DESIGNATIONS
(TOP VIEW)
CAUTION: Use handling procedures necessary
for a static sensitive component.
~ gw 8
III
6
5
15
~
g
2
4
In
8
15
C
44
43
42
....
~
c
41
40
llIE
0
lO
PARIERR
OOJS
PARiRST
BREQ
eLK
GND
mIO
33
1m1
IIOIN
BSYOUT
1m2
31
1m3
BSYIN
CIOIN
004
SEUN
19
c
z
CJ
20
I!! I!!
21
22
23
24
25
26
27
~ ~ ~ ~ ~ g 8
....
9w
'"
44-pln PLCC
ORDERING INFORMATION
PART DESCRIPTION
SSI 32B451 44-pin PLCC
ORDER NO.
PKG.MARK
SS132B451-CH
32B451-CH
No responsibility is assumed by SSi for use of this product nor for any infringements of patents and trademarks or other rights of third parties
resulting from its use. No license is granted under any patents, patent rights or trademarks of SSi. SSi reserves the right to make changes
in specifications at any time without notice.
Silicon Systems, Inc., 14351 Myford Road, Tustin,
CA 92680, (714) 731-7110, TWX 910-595-2809
0888
©1988 Silicon Systems, Inc.
6-52
SSI32C452
Storage Controller
INNOVATORS IN INTEGRATION
August, 1988
DESCRIPTION
FEATURES
The SSI32C452 Storage Controller is a CMOS device
that provides the basis for an intelligent Winchester
disk drive controller capable of non-interleaved data
transfers at rates up to 20Mbps. When combined with
a microprocessor, memory and a buffer management
device such asthe SS132C453, the SSI32C452 implements a powerful and cost-efficient peripheral controller solution. It also has the flexibility to be used in SCSI
systems.
•
suppons ST506/412, ST412HP, SA100, SMD,
ESDI and custom Interfaces
•
•
•
•
•
Operates with 16 MHz microprocessors
The SSI 32C452 includes a control sequencer with a
writeable control store, and configuration/status registers which can be programmed to support standard
and custom interface protocols for storage controllers.
Access to the control store and registers is accomplished through the microprocessor interface which is
optimized for 8 bit, multiplexed address/data bus processors such as the 8085. It also has the flexibility to
interface with most standard 8-bit microprocessors.
This organization allows the controller firmware to be
stored in an EPROM or the host and down-loaded to
the SSI 32C452 , and means wide flexibility of the
control functions performed by the device.
Internal RAM-based control sequencer
Internal user programmable ECC to 32 bits
Non-Interleaved data transfer to 20 Mbltsls
Hard or soft sector formats
•
Programmable sector lengths up to a full
track
•
High performance, low power CMOS device
•
Plug and software compatible with AIC-D10F
Storage Controller
•
•
Single 5 volt supply
Available In 44-pln PLCC or 4O-pln DIP
package
(Continued)
BLOCK DIAGRAM
RDIREFClJ(
NRZ
INDEX
-
SECTOR
RG
wo
SEOUENCER
AND
RAM
:' ::
cs
ALE
GPlOO
OPl01
GPl02
GPI03
INPUT
A!JO.AD7 ---r-~
OUTPUT
CAUTION: Use hendllng procedures necessary
for a static sensitive compcnents
0888
6-53
I
SSI32C452
Storage Controller
DESCRIPTION (Continued)
The SSI 32C452 performs all the controller functions
for the peripheral device, such as serialization/deserialization, ECC generation and checking on the data
stream. It also handles overhead information such as
address marks, gaps and sector 10 fields. If an ECC
error is detected during a read, the syndrome is saved
so that defects can be corrected. The ECC polynomial
and register length can be programmed or bypassed
entirely so that external ECC hardware can be used.
FUNCTIONAL DESCRIPTION
The major functional elements and data paths of the
SSI 32C452 are shown in the block diagram.
The SSI 32C452 performs the functions to interface a
serial data storage device such as a Winchester disk
drive, to a parallel bus interface for data processing on
a byte wide basis. The functions necessary to accurately make this conversion are serializationldeserialization, error detection and correction, and data path
control. The SSI 32C452 also has general purpose
interface lines to further facilitate control of the data
storage device or parallel interface. An eight byte stack
allows data to be saved and reviewed by the microprocessor for error handling purposes. The internal sequencer performs most of the operations in conjunction with the control and status registers. The sequencer program is contained in internal sequencer
RAM, which is easily (re)programmed providing almost
infinite flexibility in communcations protocols and
control features. A microprocessor effects both initialization and control of the SSI 32C452 by writing to and
reading from the intemal registers, sequencer RAM,
stack and general purpose I/O circuitry. The microprocessor interface block of the SS132C452 provides the
communication and control for the SS132C452 to the
microprocessor.
The buffer Interface includes a bidirectional data bus
that exchanges data bytes between an external buffer
memory and the serializer/deserializer. It generates
two clocks, ClKA and ClKB which control all accesses
to the buffer memory. All buffer memory cycles must be
synchronous with ClKA, which is derived from the RD/
REFClK input during data transfers and from SYSClK
otherwise. The internal register ClKCON contains
control bits which define the relationship between
these source clocks and ClKA. The ClKB signal is
asserted whenever a new data byte must be transferred (ie. when the serializer/deserializer is full during
a read operation or empty during a write operation).
The direction of the transfer is determined from the
state of the read gate (RG) and write gate (WG) lines.
A ClKB cycle is used to force the buffer control device
(eg. an SSI32C453) to reserve the next buffer memory
access for the SSI 32C452, since peripheral transfers
take precedence over the asynchronous host transfers. In orderto allow host transfers to keep up with peripheral transfers, the ClKA rate selected should be at
least twice the word transfer rate of the peripheral.
The microprocessor Interface decodes microprocessor read and write requests and provides access to
the appropriate register or internal memory location.
Since both data and address information are carried on
the muHiplexed bus lines ADO-AD7, address information is latched from the bus on the falling edge of the
microprocessor signal ALE (address latch enable).
=:e~~~:!s:d~~:o;~sw~:~~~~~~~~~:~~ ~~~
lected. The addresses and names of all the accessible
r~gisters are shown in the Register Address Map,
Figure 1. The. microprocessor should not read or write
the sequencer RAM while the sequencer is running,
since: there is no circuitry to resolve conflicting accesses and incorrect sequencer operation will resuH.
The status and control registers make status information available to the microprocessor and allow the
device to be configured for a wide variety of peripheral
control applications. The microprocessor can monitor
the status of transfers In progress and control the ECC
register operation, the ECC polynomial, the clock
generation hardware and the sequencer program
execution. The microprocessor also has access to the
sequencer's microprogram RAM so that it loads the
microcode for all controller operations.
The serlallzer/deserlallzer circuit interfaces the parallel buffer memory bus to the serial NRZ data stream
of the peripheral device. Byte synchronism is maintained with a bit ring, which is an 8 bit recirculating shift
register clocked by the peripheral bit clock. During a
sector write, the bit ring is initialized explicitly with a
sequencer instruction. The bit ring continues to
operate until the end of the field (ECC written or read)
and causes ClKB to be asserted once for each data
byte to be transferred. During write operations, the
6-54
0888
SSI32C452
Storage Controller
sequencer may cause address marks and sync patterns to be loaded into the serializer instead of data
bytes. These special patterns are contained in a
sequencer instruction and are transferred to the serializer over an internal byte wide data path. During read
operations, bytes of overhead information may be
routed to the stack or sequencer for comparison
againsttargetvalues. This process is controlled by the
control field (SEQCONF) in each sequencer instruction.
The eight byte recirculating stack may be used to
capture read data for later examination by the microprocessor. Data is pushed onto the stack under
sequencer control. The control bit STACKEN in the
sequencer instruction field SEQCONF directly controls
the stack. If more than 8 bytes are written to the stack,
only the last 8 will be saved. When a data byte is read
from the top of the stack by the microprocessor via the
STACK register, the data is recirculated to the bottom
of the stack, allowing the stack contents to be examined more than once without the use of temporary
storage in the microprocessor or buffer.
Serial peripheral data is passed through a variable
length shift register with programmable exclusive OR
feedback that performs ECC generation and check·
Ing. The feedback taps for the desired ECC polynomial are selected inthefourregisters POLYO - POLY24
and the polynomial length is determined by the LEN
bits in ECCCON. In addition, the ECC register may be
operated either under sequencer or microprocessor
control. During read operations, the contents of the
ECC register are compared to the actual ECC field
read from the peripheral. If there is a mismatch, the
error syndrome is available for error correction. The
ECC polynomial may be reversed to allow hardware
computation of the error location, relieving the microprocessor of the burden of this lengthy calculation.
During writes to the peripheral, the computed ECC
word can be appended to each data or address field.
The sequencer data type field (SEQDATF) indicates
when ECC bytes are to be written or checked during a
peripheral transfer.
The sequencer controls the time critical operations of
the SS132C452. It executes programs stored in the 28
LOWER ADDRESS NIBBLE
c
A
w
a! •
!!!
z
~
c
~
a:
~
Q.
::l
.
.
7
"""To
HOSTL
I!Il HOSTH !j.j INTCON ll'I DMACON~ BUFaIZE flI'M"""""II
!lRESCON
"""TI
"""TO
RAP\.
ln RAPH
WAPL ~
OLR
WAPH
GPL
GPH
o...... ! GPREGI
BUFACC
I
ECCCON
I
ECC11
I
ECC24
I
POLYO
I
POlVl
I
POLV1e
I
POLY24
I :~
8EOADDR
SEOBTAT
OPCON
SEOCONF(n)
A
SEOOONF(n)
c
SEOTYPF(n)
.SEODATF(n)
FIGURE 1: REGISTER ADDRESS MAP
0888
"""11
6-55
WAMCON
AMDCON
GPIOOON
GPIODAT
CLKCON
STACK
I
SSI32C452
Storage Controller
FUNCTIONAL DESCRIPTION (continued)
the sequencer is halted.
word by 32 bit sequencer RAM, and can be programmed to support hard and soft sectored read, write,
search and verify operations for a wide variety of
Winchester disk drives and other peripherals. The
sequencer RAM is loaded by writing to the sequencer
instruction registers as outlined in the Sequencer Instructions section of this data sheet. Each instruction
is comprised of four bytes. Each of the four bytes
represents a function of the sequencer operation.
They are address field, control field, data type field, and
data field. The organization of these fields is shown in
the Register Bit Map, Figure 2. The Sequencer Registers provide control from and status to the microprocessor and sequencer. They contain branch, next and
start addresses, and sequencer status information.
The SEQUENCER STATUS register provides informaton on the sequencer state such as whether an ECC
error occurred, a compare equal or low occurred, if the
branch condition or address mark is active, or whether
The general purpose 1/0 section has four general
purpose 1/0 lines GPIOO - GP103, and the INPUT pin
which are accessible through the internal general
purpose input/output registers. They are available for
user defined functions such as Winchester disk or host
interface control. The functionality of the GPIOO GPI03 pins is programmed in the GPIOCON and
GPIODAT registers. They can act as 110's asserted or
read through the GPIODAT register, or they can be
programmed to decode microprocessor access to
addresses 6EH and 6FH eliminating the need for
external decode. The INPUT signal can be programmed in the SEQADRF RAM (registers) to affect
sequencer operation and the state of the pin read from
the GPIODAT register. The other general purpose line,
OUTPUT is controlled directly by the sequencer to
synchronize it with external circuitry. The OUT bit ofthe
GPIODAT register reflects the state of the output pin.
PIN DESCRIPTION
GENERAL
NAME
DIP
PLCC
VCC
40
1
GND
20-21
22
RST
12
13
I
RESET - Active low signal halts the sequencer, sets
output pins RG, WG, WAM and NRZ low, forces the
GPIO pins into a high impedance state and resets a
number of the registers as described below.
SYSCLK
13
14
I
SYSTEM CLOCK - Clock input in the range of 1.5 MHz
to 16 MHz
TYPE
DESCRIPTION
POWER SUPPLY +5 volts
GROUND
MICROPROCESSOR INTERFACE
ALE
1
2
I
ADDRESS LATCH ENABLE - Falling edge latches register address from ADO-7 pins.
CS
29
33
I
CHIP SELECT- Active high signal enables device to
respond to microprocessor read or write.
6-56
0888
SSI32C452
Storage Controller
PIN DESCRIPTION (continued)
DESCRIPTION
NAME
DIP
PLCC
TYPE
WR
30
34
I
WRITE STROBE - Active low signal causes the data on
the addressJdata bus to be written to the addressed
register if CS is also active.
RD
31
35
I
READ STROBE - Active low signal causes the contents
of the addressed register to be placed on the addressJ
data bus if CS is also active.
39-32
43-36
I/O
ADDRESs/OATA BUS - 8 bit bus which carries register
address information and bi-directional data. These pins
are high impedance when not in use.
5-8
I/O
GENERAL PURPOSE I/O LINES - These lines can be
programmed as an inputs or outputs which are accessed
though the GPIODAT register. They may also be programmed to serve as active low outputs which decode
microprocessor accesses to the following locations:
ADO-AD7
GENERAL PURPOSE 110
GP100-3
4-7
JLQJln
GPIOO
GPI01
GPI02
GPI03
Ab~mat~
QUlgUI
d~cgg~
Write to 6EH
Read from 6EH
Write to 6FH
Read from 6FH
INPUT
8
9
I
INPUT PIN - This dedicated input line may be read
through the GPIODAT register or tested directly by the
control sequencer.
OUTPUT
9
10
0
OUTPUT PIN - Dedicated output line which is derived
directly from the control sequencer instruction field.
DISK DRIVE INTERFACE
0888
INDEX
10
11
I
INDEX PULSE - Active high disk drive index pulse input,
must be at least one byte time long.
SECTOR
11
12
I
SECTOR PULSE - Active high sector pulse input from
disk drives that are hard sectored, must be at least one
byte time long.
RG
14
15
0
READ GATE - Active high output from control sequencer
enables extemal phase-locked loop (PLL) to synchronize to read data stream from the storage device.
6-57
I
SSI32C452
Storage Controller
PIN DESCRIPTION (continued)
DISK DRIVE INTERFACE (continued)
NAME
DESCRIPTION
DIP
PLCC
TYPE
WG
15
16
0
WRITE GATE - Active high output from control sequencer indicates valid write data to the storage device.
RD/REFCLK
26
30
I
READ/REFERENCE CLOCK - This input must be
externally muHiplexed to provide the PLL clock when
read gate is active and the write oscillator clock at all
other times. This pin must always be driven with a clock
Signal, even when RST is active.
NRZ
27
31
I/O
NRZ DATA - This bi-directional pin provides write data
when WG is active, and must be driven with read data
when RG is active. Data must be in the NRZ format.
WAM/AMD
28
32
I/O
WRITE ADDRESS MARK/ADDRESS MARK DETECT This bi-directional pin is used to write and detect address
marks. When WG is active, a low level output of one bit
time on this pin indicates that an address mark must be
written. When RG is active, the peripheral must provide
an active low input to indicate the detection of an address
mark.
BUFFER INTERFACE
CLKA
2
3
0
CLOCK A - Clock signal which initiates host or controller
accesses to the buffer memory on its falling edge. When
either RG or WG is active, this output is derived from RD/
REFCLK. At all other times it is derived from SYSCLK.
The clock source is divided by 2 or 4 as programmed in
the CLKCON register.
CLKB
3
4
0
CLOCK B - This clock is used to reserve CLKA cycles for
SS132C452 data transfers. An active low pulse spanning
a falling edge of CLKA indicates that the next falling edge
on CLKA will be used by the SSI 32C452 to access the
buffer memory.
DO-D7
16-19
22-25
18-21
25-28
I/O
BUFFERDATABUS-Bi-directionaldatabusthatcarries
data to and from the buffer memory. Bus cycles are
controlled by CLKA and CLKB. Direction of the transfer
is determined by RG and WG. Note: refer to pin diagram
for exact ordering of the pins.
No connects on PLCC package: 17, 23, 24, 29, 44
0888
SSI32C452
Storage Controller
REGISTER
ADDRESS
07
06
D4
05
03
01
READ/
WRITE
DO
TESTO
49H
SEQUENCER NEXT ADDRESS FIELD
R
TESTl
4AH
SEQUENCER CONTROL FIELD
R
TEST2
4BH
SEQUENCER COUNT/DATA TYPE FIELD
R
TEST3
4CH
SEQUENCER DATA FIELD
R
DLR
4DH
DATA LATCH REGISTER
R
BUFACC
70H
BUFFER MEMORY BYTE
RIW
ECCCON
71H
LENl
LENO
RESET
SECTBR
CLRECC
FEEDINH
ECCSHIFT
ECCIN
RIW
ECC16
72H
ECC23
ECC22
ECC21
ECC20
ECC19
ECC18
ECC17
ECCO/16
R
ECC24
73H
ECC31
ECC30
ECC29
ECC28
ECC27
ECC26
ECC25
ECC24
R
POLYO
74H
F7
F6
F5
F4
F3
F2
Fl
FO
RIW
POLY8
75H
F15
F14
F13
F12
Fll
FlO
F9
F8
RIW
POLY16
76H
F23
F22
F21
F20
F19
F18
F17
F16
RIW
POLY24
77H
UNUSED
F30
F29
F28
F27
F26
F25
F24
RIW
SEQBR
78H
UNUSED
BRADR2
BRADRl
BRADRO
W
SEQNA
78H
TEST POINTS
NADR4
NADR3
NADR2
NADRl
NADRO
R
SEQADDR
79H
UNUSED
STADR4
STADR3
STADR2
STADRl
STADRO
W
BRACTIVE STOPPED
UNUSED
ECCERR
COMPLO
COMPEQ
R
TRANSINH
SYNDET
NRZDAT
SECTORP
INDEXP
RIW
SEQSTAT
79H
AMACTIVE
DATAlFIANS
OPCON
7AH
CARRYINH
UNUSED
BRADR4
SEARCHOP
BRADR3
WAMCON
7BH
AM7-AMO
RIW
AMDCON
7CH
AMD7-AMDO
RIW
GPIOCON
7DH
GPIODAT
7EH
CLKCON
7FH
STACK
7FH
SEQADDRF
80H
SEQCONF
WGFSEL
UNUSED
CLKF2
CLKFl
RGESEL
WGESEL
GPDIR3
GPDIR2
GPDIRl
GPDIRO
RIW
OUT
INP
GP3
GP2
GPl
GPO
RIW
UNUSED
CLKFO
CLKlNH
SYN2
SYNl
SYNO
W
R
TOP OF STACK
BRCON2
BRCONl
BRCONO
NEXT4
NEXT3
NEXT2
NEXTl
AOH -+SETWG
SETRG
RESWG
STACKEN
NRZINH
OUTPIN
COMPEN
DATEN
CNT6I
DTYPl
CNTS/
DTYPO
CNT4
CNT3
CNT2
CNTl
BBH
SEQTYPF
RGFSEL
NEXTO
9BH
COH
DBH
T
-+-
SEQDATF
CNT7/
DTYP2
DATA FIELD
-+
FIGURE 2: REGISTER BIT MAP
0888
02
6-59
CNTO
RIW
+
+
+
Y
RIW
RIW
RIW
SSI32C452
Storage Controller
REGISTER DESCRIPTION
shift registers, ECC16 and ECC24, while its output is
always bit 31, which is bit ECC31 of register ECC24.
The microprocessor which controls the system has
access to all the SSI 32C452 registers and sequencer
RAM through its external memory address space. The
SSI 32C452 and its companion device, the SSI
32C453 Dual Port Buffer Controller, are designed to
occupy a single 256 byte page. The 8 bit page address
is latched from pins ADO-AD7 on a falling edge of ALE
and remains valid until the next ALE falling edge.
The external registers described at the end of this
section are not implemented in either the SSI 32C452
or SSI32C453, and are assumed to be implemented in
external hardware. These external registers are not
required for use with the SS132C452, but are included
as applications information.
ECC REGISTERS
The core of the ECC circuit is a 32 bit shift register
whose effective length may be programmed to be 16,
24 or 32 bits. This is accomplished in hardware by
directing the input data to stage 16, 8 or 0 of the ECC
ECCCON
71H
The ECC polynomial to be implemented is programmed by the user into the ECC feedback registers,
POLYO, POLY8, POLY16 and POLY24. Each bit in
these registers enables or disables exlusive OR feedback to the output of the corresponding shift register
stage. The feedback signal is the exclusive OR of the
serial data stream with the output of shift register stage
31. An override bit in ECCCON forces normal shift
register operation, regardless of the settings of the
feedback control bits.
When WG or RG are active, the ECC shift register input
is the serial read or write data and the shift clock is RD!
REFCLK. When an ECC word is being written, feedback is disabled and the shift register output is substituted for the data stream. At other times the microprocessor may set the ECCIN bit explicitly and cause a
single shift register clocking to occur. For further
information on implementing an ECC polynomial see
the Applications Information Section at the end of this
data sheet.
ReadlWrlte
ECC CONTROL WORD
BIT
NAME
DESCRIPTION
0
ECCIN
ECC SERIAL INPUT - When both RG and WG are inactive, this bit becomes the
input bit for the ECC shift register. The RD!REFCLK must always be active for
correct operation of the device.
1
ECCSHIFT
ECC SHIFT CONTROL - When both RG and WG are inactive, a single shift ofthe
ECC register will occur when this bit is set. It is automatically cleared again when
the shift is complete.
2
FEEDINH
ECC FEEDBACK INHIBIT - When this bit is set all feedback is inhibited and the
ECC register functions as a simple shift register of the selected length.
3
CLRECC
CLEAR ECC - Ifthis bit is set when either RG or WG are active, the ECC syndrome
will be cleared at the end of the readlwrite operation. If both are inactive, the
syndrome will be cleared immediately.
4
SECTBR
ENABLE SECTOR BRANCH - If the sequencer "branch on index or sector"
instruction is executed and SECTBR is set, the sequencer will recognize the
branch condition as true if either the INDEX or the SECTOR pin is active. If
SECTBR is cleared, then the sequencer will only recognize the branch condition
if the INDEX pin is active.
6-60
0888
SSI32C452
Storage Controller
ECC REGISTERS (continued)
BIT
NAME
DESCRIPTION
5
RESET
CHIP RESET - When this bit is set, the SSI 32C452 will be held in its reset state.
This bit is set when RST is true.
6-7
LENO-LEN1
ECC REGISTER LENGTH - These two bits select the ECC register length as
follows:
LE..t:ll.
LENQ
0
0
1
1
0
1
0
1
16 bit register
24 bit register
illegal combination
32 bit register
Reset State: ECCCON= 20H (ie. RESET=1)
72H
ECC16
Read only
ECC DATA
BIT
NAME
DESCRIPTION
0
ECCO/16
ECC REGISTER LEADING BITS - This bit reflects the OR of all the ECC register
bits from the input stage through bit 16. For 16 bit operation, this is bit 16. For 24
bit operation this is bit 8 + bit 9 + .. + bit 16. For 32 bit operation, this is bit 0 + bit
1 + ... + bit 16.
1-7
ECC17-ECC23
ECC REGISTER BITS - These bits reflect the output of ECC shift register stages
17to 23.
Reset State: Unknown
ECC24
73H
Read only
ECC DATA
BIT
NAME
DESCRIPTION
0-7
ECC24-ECC31
ECC REGISTER BITS - These bits reflect the output of ECC shift register stages
24 to 31.
Reset State: Unknown
0888
6-61
SSI32C452
Storage Controller
ECC REGISTERS (continued)
74H
POLYO
Read/Wrlte
ECC POLYNOMIAL
BIT
NAME
DESCRIPTION
0-7
FO-F7
ECC POLYNOMIAL FEEDBACK - These bits enable or disable exclusive OR
feedback of both the shift register output (bit 31) and the serial input to the output
of shift register stages 0 to 7. These settings may be overriden by the FEEDINH
bit in ECCCON. For ECC register lengths of 16 or 24 bits, FO-F7 are irrelevant.
Reset State: POLYO=OOH
75H
POLY8
Read/Write
ECC POLYNOMIAL
BIT
NAME
DESCRIPTION
0-7
F8-F15
ECC POLYNOMIAL FEEDBACK - These bits enable or disable exclusive OR
feedback to the output of shift register stages 8 to 15. For register lengths of 16 bits,
F8-F15 are irrelevant.
Reset State: POLY8=00H
POLY16
76H
Read/Write
ECC POLYNOMIAL
BIT
NAME
DESCRIPTION
0-7
F16-F23
ECC POLYNOMIAL FEEDBACK - These bits enable or disable exclusive OR
feedback to the output of shift register stages 16 to 23.
Reset State: POLY16=00H
POLY24
77H
Read/Write
ECC POLYNOMIAL
BIT
NAME
DESCRIPTION
0-6
F24-F30
ECC POLYNOMIAL FEEDBACK - These bits enable or disable exclusive OR
feedback to the output of shift register stages 24 to 30.
7
unused
Reset State: POLY24=00H
6-62
0888
SSI32C452
Storage Controller
SEQUENCER STATUS AND CONTROL
REGISTERS
The sequencer controls all the time-critical interactions
with the peripheral storage device being controlled by
the SSI 32C452. The instructions directly control disk
drive interface lines, provide data for writing or comparison, determine the number of bytes handled and
control the sequence of instruction execution. It is
programmed by the user for maximum capability and
variability. There are 28 instructions which are 32 bits
wide. They are divided in to 4 byte wide fields. These
fields are sequencer address, control, data type and
data fields. These may be further divided into subfields as described in detail below. Examples are
shown in the Applications Information section at the
end of this data sheet.
The next address field of the sequencer instruction
contains address and branching information. Each
instruction is executed forthe duration ofthe number of
byte times specified in its count field. The specified
SEQBR
78H
count is loaded into a down counter which clocks every
8 bit times. When the counter underflows execution of
that instruction is terminated. A carry inhibit feature
allows the counter to wrap around to a full count for
fields which are more than 256 bytes long. Execution is
passed to the instruction at the specified next address,
unless a branch condition is specifed in the instruction
(eg. ECC error or successful data comparison). In that
case, execution passes to the address specified in the
SEQBR register. Sequencer operation may also be
conditionally stopped. The sequencer will always stop
if execution passes to address 1FH, which is outside of
the 28 word instruction control store.
The control field of the sequencer instruction is used to
specify the state of RG and WG, to move data to the
stack and to select data transfer or data comparison
operations. The count field sets the duration of each
instruction in byte times and is also used to select the
type of data written, such as address marks or ECC
bytes.
Write only
SEQUENCER BRANCH ADDRESS
BIT
NAME
DESCRIPTION
0-4
BRADRO
- BRADR4
BRANCH ADDRESS BITS - When a sequencer instruction with a branch
condition is finished (ie. the specified number of byte times have elapsed) and the
specified condition did occur, execution will resume at this 5 bit address.
5-7
unused
Reset State: Unknown
SEQNA
78H
Read only
SEQUENCER NEXT ADDRESS
BIT
NAME
DESCRIPTION
0-4
NADRO
- NADR4
NEXT ADDRESS BITS- This reflects the 5 bit next address field of the
sequencer instruction currently being executed. After the specified byte count,
execution will proceed at this address provided no branch conditions occur.
5-7
Internal test points
Reset State: Unknown
0888
6,-63
SSI32C452
Storage Controller
SEQUENCER STATUS AND CONTROL REGISTERS (continued)
SEQADDR
79H
Write only
SEQUENCER START ADDRESS
BIT
NAME
DESCRIPTION
0-4
STADRO
-STADR4
SEQUENCER START ADDRESS BITS -If the sequencer is currently haned,
writing this register with an address in the range OOH to 1BH will cause sequencer
execution to commence at that address. Hthis register is written with 1FH , the
sequencer will han.
5-7
unused
Reset State: OOH
SEQSTAT
79H
Read only
SEQUENCER STATUS
BIT
NAME
DESCRIPTION
0
COMPEQ
COMPARE EQUAL - When a sequencer instruction enables the comparison
operation, this bit reflects the resun of all the byte comparisons performed (ie. if it
is set then all bytes compared so far have been equal.) H RG is enabled, the
comparisons occur between the instruction's data field and the data bytes being
read (or buffer memory if the SEARCHOP bit in OPCON is true as well).
1
COMPLO
COMPARE LOW - Similar to COMPEQ, except that it indicates that in all
comparisons the data field was smaller than the compared byte.
2
ECCERR
ECC ERROR - This bit is set during RG active, upon reading the last ECC bit, if
there was an error in the data read. The error syndrome will be stored in the ECC
registers.
3
not used
4
STOPPED
SEQUENCER STOPPED - This bit is set when the sequencer is stopped and its
instruction address is 1FH.
5
BRACTIVE
BRANCH ACTIVE - This is set when the branch condition specified in the current
instruction has been satisfied. This means that the next address used will be taken
from the SEQBR register. This bit is reset when the microprocessor reads this
register.
6
DATATRANS
DATA TRANSFER - This bit is set when the current sequencer instruction is
causing data to be transferred between the buffer memory and the peripheral
device. This distinguishes the activity from a search or verification operation.
7
AMACTIVE
ADDRESS MARK ACTIVE - This bit is set when the controller reads or writes an
address mark or sync byte. It is reset after the ECC bytes are read or written, or
when the sequencer is haned.
Reset State: OOH
6..64
0888
SSI32C452
Storage Controller
SEQUENCER INSTRUCTION REGISTERS
The 4 fields of 8 bits comprising a single sequencer instruction are detailed below. They are presented as
arrays of 28 bytes each, corresponding to the 28 instructions at sequencer addresses 0 to 1BH.
SEQADRF(n)
80H-9BH
Read/Wrlte
SEQUENCER ADDRESS FIELD ARRAY
BIT
NAME
DESCRIPTION
0-4
NEXTO-NEXT4
NEXT ADDRESS FIELD - This 5 bit field specifies the address of the next
instruction to be executed when the current instruction has continued for the
specified number of bytes.
5-7
BRCONO
-BRCON2
BRANCH CONTROL FIELD - This 3 bit field specifies the branch condition
for the current instruction. When a branch condition is satisfied, execution of the
current instruction is not curtailed. It continues to execute for the full byte count
specifed, and then the sequencer proceeds with execution ofthe address specified
in SEQBR. The branch condition used depends on the state of RG and data type
field (see SEQTYPF). If RG is true and ECC bytes are being read, the following
branch conditions apply:
BRCON2I1/0=
No branch
000
001
Stop on ECC error
010
Stop on comparison error
011
Stop on ECC or comparison error
100
Branch on good ECC and comparison
101
Branch on ECC error
110
Branch on comparison error
111
Branch on ECC or comparison error
Otherwise, the branch conditions are:
BRCON2I1/0=
000
No branch
001
Stop if INPUT pin active
010
Stop if INDEX or SECTOR pin active (see SECTBR bit
of register ECCCON).
011
Stop if comparison error
100
Branch on carry (from byte counter).
101
Branch on ECC error
110
Branch if INDEX or SECTOR pin active (see SECTBR
111
Branch on comparison error
bit of register ECCCON).
Reset State: The contents of the sequencer RAM are unchanged.
0888
6-65
I
SSI32C452
Storage Controller
SEQUENCER INSTRUCTION REGISTERS (continued)
SEQCONF(n)
AOH-BBH
ReadIWrlte
SEQUENCER CONTROL FIELD ARRAY
BIT
NAME
DESCRIPTION
0
DATEN
DATA TRANSFER ENABLE - When this bit is set, the SSI32C452 will generate
ClKB requests to transfer data bytes to or from buffer memory, depending on
whether WG or RG is active.
1
COM PEN
COMPARE ENABLE - When this bit is set and RG is active, read data bytes from
the peripheral will be compared with the instruction data field (SEARCHOP reset
in the OPCON register) or the buffer memory data (SEARCHOP set). The results
of the comparisons are OR'ed together for the duration of the instruction and can
be used for a branch condition or tested by the microprocessor.
2
OUTPIN
OUPUT PIN CONTROL - This bit appears on the OUTPUT pin and may be used
to synchronize external circuitry to the sequencer.
3
NRZINH
NRZ DATA INHIBIT - When RG is active and this bit is set, the NRZdatainputwill
be ignored. This is useful while external data recovery circuits start up.
4
STACKEN
STACK WRITE ENABLE - While this bit is set, bytes of NRZ data are pushed onto
the recirculating stack.
5
RESWG
RESET WRITE GATE - This bit causes the WG line to go inactive 4 bit times after
the current instruction is finished (byte counter reaches 0).
6
SETRG
SET READ GATE - Provided WG is inactive, this bit sets RG, which will remain
active until the ECC information is read or the sequencer is halted.
7
SETWG
SET WRITE GATE - When this bit is set and an instruction executed, the WG line
will be activated after a delay of 4 bit times. WG wiIJ remain active until cleared by
the RESWG bit orthe sequencer is halted. WG will not be activated if RG is already
active.
Reset State: The contents of the sequencer RAM are unchanged.
SEQTVPF(n)
COH-DBH
ReadIWrlte
SEQUENCER DATA TYPE FIELD ARRAY
BIT
NAME
DESCRIPTION
0-4
CNTO-CNT4
COUNT FIELD - The current sequencer instruction is executed for the number of
byte times specified by the countfield. 1ft he DATEN bit is set, the count is specified
as an 8 bit quantity (CNTO-CNT7). If DATEN is reset, the count is specified as a
5 bit quantity (CNTO-CNT4), and the upper three bits of this instruction field are
interpreted as data type bits, described below.
6-66
0888
SSI32C452
Storage Controller
SEQUENCER INSTRUCTION REGISTERS (continued)
BIT
NAME
DESCRIPTION
5
CNT5/DTYPO
COUNT BIT 5 OR DATA TYPE 0 - When this bit is interpreted as a data type bit,
it is used to initialize the bit ring with a single 1. This will occur at the next ClKA
cycle. This starts ClKB so that write data bytes will be fetched from buffer memory.
The bit ring will be cleared after the ECC is written.
6
CNT6IDTYP1
COUNT BIT 6 OR DATA TYPE BIT 1 - When this bit is interpreted as a data type
bit, it indicates that ECC information is being read or written.
7
CNT7/DTYP2
COUNT BIT 7 OR DATA TYPE BIT 2 - When this bit is being interpreted as a data
type bit it indicates that an address mark is being written.
Note: When DATEN is reset, and CNT5/DTYPO, CNT6IDTYP1 and CNT7/DTYP2 are being interpreted as
data type select bits, the upper 3 bits of the byte counter are forced to 0 regardless of the settings of the data
type bits. When all 3 data type bits are 0, the data field is interpreted as normal binary data.
Reset State: The contents of the sequencer RAM are unchanged
SEQDATF
EOH-FBH
Read/Wrlte
SEQUENCER DATA FIELD ARRAY
BIT
NAME
DESCRIPTION
0-7
DATO-DAT7
DATA FIELD - When RG is active, the byte in this field is used for comparison
operations. If WG is active, DATATRANS is set and TRANSINH (Transfer Inhibit
bit in OPCON register) is set, the write data will come from this field. This allows
the sequencer to generate the necessary overhead bytes while writing a sector.
Reset State: The contents of the sequencer RAM are unchanged.
DISK DRIVE INTERFACE REGISTERS
The disk drive interface registers provide control and status forthe interface ofthe SSI32C452 to the disk drive
(peripheral device), and for data transfer to the buffer or host.
OPCON
7AH
Read/Wrlte
OPERATION CONTROL WORD
0888
BIT
NAME
DESCRIPTION
0
INDEXP
INDEX PULSE DETECTED - This bit is set when an index pulse is encountered
and reset each time the register is read. The bit will be reset even if the INDEX pin
is true during the access.
1
SECTORP
SECTOR PULSE DETECTED - This bit is set when a sector pulse is encountered
and cleared each time the register is read. The bit will be cleared even if the
SECTOR pin is true during the read access. This bit is only used with hard-sectored
disk drives.
6-67
I
SSI32C452
Storage Controller
DISK DRIVE INTERFACE REGISTERS (continued)
BIT
NAME
DESCRIPTION
2
NRZDAT
NRZ DATA IN - This bit is set when a rising edge is detected on the NRZ pin and
RG is active. It is reset when the register is read.
3
SYNDET
SERIAL DATA SYNCHRONIZATION DETECT - Indicates that the bit ring is
synchronized on byte boundaries, following detection of an address mark.
4
SEARCHOP
SEARCH OPERATION - Setting this bit will cause comparisons to occur between
the contents of the buffer memory and the read data bytes from the peripheral. If
SEARCHOP is reset, then read data bytes will be compared to the sequencer
instruction data field.
5
TRANSINH
DATA TRANSFER INHIBIT -If WG is active and this bit is set, then the write data
will come from the sequencer instruction data field instead of the buffer memory.
If RG is active and this bit is set, then the read data bytes are used for comparisons
only and are not written to buffer memory. Setting this bit will suppress ClKB so
that no buffer memory transfers occur.
6
Unused
7
CARRYINH
SEQUENCER COUNTER CARRY INHIBIT - When this bit is set, the sequencer
will not detect a carry (underflow) in its byte counter. This bit is reset when a carry
occurs.
Reset State: Unknown
WAMCON
7BH
ReadIWrlte
WRITE ADDRESS MARK CONTROL
BIT
NAME
DESCRIPTION
0-7
AMO-AM7
ADDRESS MARK BITS - When WG is active and the sequencer instruction
specifies that an address mark is to be written (DATATRANS is reset, DTYP2 is
set) the bits AMO-AM7 will be shifted out on the WAM/AMD pin. The pattern is
delayed by two bit times to compensate for the encoder delay.
Reset State: Unknown
AMDCON
7CH
ReadIWrlte
ADDRESS MARK DETECT CONTROL
BIT
NAME
DESCRIPTION
0-7
AMDO-AMD7
ADDRESS MARK DETECT CONTROL - When RG and the WAM/AMD input are
active, the NRZ data stream is compared to the contents of this register. Byte
synchronization is established when a match occurs. The number of bits used in
the comparison is determined in the ClKCON register.
Reset State: Unknown
6-68
0888
SSI32C452
Storage Controller
DISK DRIVE INTERFACE REGISTERS (continued)
ClKCON
7FH
Write only
CLOCK CONTROL
BIT
NAME
DESCRIPTION
0-2
SYNO-SYN2
SYNC COMPARE CONTROL - These 3 bits determine which bits in register
AMDCON are used when looking for the sync byte, as follows:
SYN2I1/0 =
000
Bit 7 used
001
Bits 7,6 used
010
Bits 7,6,5 used
011
Bits 7,6,5,4 used
100
Bits 7,6,5,4,3 used
101
Bits 7,6,5,4,3,2 used
110
Bits 7,6,5,4,3,2,1 used
111
All bits used
3
CLKINH
CLOCK INHIBIT - When this bit is set, CLKA and ClKS are forced to a high
impedance state.
4
CLKFO
CLOCK FREQUENCY SELECT - This bit sets the relationship between CLKA and
RD/REFCLK when data transfers are in progress. When it is set, CLKA will be
1/4 the RD/REFCLK frequency and when it is reset, CLKA will be 1/2 the RDI
REFCLK frequency.
5
Unused
6-7
CLKF1-CLKF2
CLOCK FREQUENCY SELECT - These bits determine the relationship between
the frequency of CLKA and SYSCLK when no data transfers are in progress, as
follows:
CLKF2/CLKF1 =
00
1/4 frequency
01
1/2 frequency
10
same frequency
11
illegal combination
Reset State: Unknown
STACK
7FH
Read only
TOP OF STACK
This register provides the microprocessor read access to the top of the 8 byte stack. Each read operation
causes the stack data to recirculate, with the top of the stack moving to the bottom. When the sequencerwrites
data to the stack, the byte on the bottom of the stack is lost.
0888
6-69
I
SSI32C452
Storage Controller
GENERAL PURPOSE INPUT/OUTPUT REGISTERS
GPIOCON
7DH
ReadIWrlte
GENERAL PURPOSE 1/0 CONTROL
BIT
NAME
DESCRIPTION
0-3
GPDIRO
-GPDIR3
GENERAL PURPOSE 1/0 LINE DIRECTION- These bits program the
direction of lines GPIOO to GP103. The direction bits are set for outputs and reset
for inputs.
4
W6ESEL
W6E SELECT - If this bit is set along with GPDIRO, the GPIOO pin becomes an
active low output signal decoding a microprocessor write to location 6EH.
5
R6ESEL
R6E SELECT - If this bit is set along with GPDIR1, the GPI01 pin becomes an
active low output signal decoding a microprocessor read from location 6EH.
6
W6FSEL
W6F SELECT - If this bit is set along with GPDIR2, the GPI02 pin becomes an
active low output signal decoding a microprocessor write to location 6FH.
7
R6FSEL
R6F SELECT - If this bit is set along with GPDIR3, the GPI03 pin becomes an
active low output signal decoding a microprocessor read from location 6FH.
Reset State: Unknown
GPIODAT
7EH
ReadIWrlte
GENERAL PURPOSE 1/0 DATA
BIT
NAME
DESCRIPTION
0-3
GPO-GP3
GENERAL PURPOSE 1/0 PIN STATUS - These bits represent the state or output
data forthe GPIOO to GPI03 pins, depending on the direction programmed in the
GPIOCON register.
4
INPUT
INPUT PIN STATUS - This bit reflects the data on the INPUT pin.
5
OUT
OUTPUT PIN STATUS - This bit reflects the data on the OUTPUT pin. The
OUTPUT pin is actually written to by the sequencer.
6-7
Unused
Note: The GPIOCON register must be initialized before GPIODAT is accessed.
Reset State: Unknown
6-70
0888
SSI32C452
Storage Controller
MICROPROCESSOR INTERFACE REGISTERS
DLR
4DH
Read only
DATA LATCH REGISTER
When a microprocessor read from location 70H is detected, the data on the buffer memory bus (DO-D7) is
latched by the SSI 32C452 into the DATA LATCH REGISTER. When the microprocessor accesses DLR this
data is placed on the address/data bus (ADO-AD7).
SPECIAL ADDRESS DECODES SOH-51 H
ReadlWrlte
Special decodes
Microprocessor accesses to these locations will cause the address/data bus (ADO-AD7) and the buffer data
bus (DO-D7) to be bridged together internally (see external register description).
BUFACC
70H
ReadlWrlte
BUFFER ACCESS
Microprocessor accesses to this location cause the address/data bus (ADO-AD7) and the buffer data bus (DOD7) to be bridged together internally. If a read cycle is performed, the data present will be latched into register
DLR as well.
TEST REGISTERS
These registers may not be accessed while the sequencer is running.
TESTO
49H
Read only
TEST REGISTER 0
Access to the Next Address field of the current sequencer instruction.
TEST1
4AH
Read only
TEST REGISTER 1
Access to the Control field of the current sequencer instruction.
TEST2
4BH
Read only
TEST REGISTER 2
Access to the Count/Data Type field of the current sequencer instruction.
TEST3
4CH
Read only
TEST REGISTER 3
Access to the Data field of the current sequencer instruction.
0888
6-71
I
SSI32C452
Storage Controller
EXTERNAL REGISTERS (for reference only)
HOSTL
50H
ReadIWrlte
HOST BUS (LOWER BYTE)
External hardware may be used to connect the lower byte of the host bus to the buffer memory when this
address is accessed.
HOSTH
51H
ReadIWrlte
HOST BUS (UPPER BYTE)
External hardware may be used to connect the upper byte of the host bus to the buffer memory when this
address is accessed.
GPREGO
6EH
ReadIWrlte
GENERAL PURPOSE REGISTER 0
Systems which need extra 1/0 on the microprocessor data bus may take advantage of the strobes available
on pins GPIOO (write) and GPI01 (read) to add an expansion port at this address.
GPREG1
6FH
ReadIWrlte
GENERAL PURPOSE REGISTER 1
Systems which need extra 1/0 on the microprocessor data bus may take advantage of the strobes available
on pins GPI02 (write) and GPI03 (read) to add an expansion port at this address.
6-72
0888
SSI32C452
Storage Controller
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETER
RATING
UNIT
Ambient Temperature Under Bias
Oto 70
°C
Storage Temperature
-65 to 150
°C
Voltage On Any Pin With Respect To Ground
GND -0.5 or VCC + 0.5
V
Power Supply Voltage
7.0
V
Max Current Injection
25
mA
NOTE: Stress above those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MAX
UNIT
4.75
5.25
V
0
70
°C
Input Low Voltage
0
0.4
V
Input High Voltage
2.4
VCC
V
MAX
UNIT
PARAMETER
VCC
Supply Voltage
TA
Operating Free Air Temp.
CONDITIONS
MIN
NOM
D. C. CHARACTERISTICS
TA = O°C to 70°C, VCC = 5V ± 5%, unless otherwise specified.
PARAMETER
CONDITIONS
MIN
NOM
VIL
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage
2.0
VCC+.5
V
VOL
Output Low Voltage
0.45
V
10L =4mA for
10L = 2mA all others
VOH
Output High Voltage
ICCS
Supply Current Standby
ICC
Supply Current
IOH=400mA
2.4
V
Inputs at GND or VCC
25
mA
85
mA
500
mW
Power Dissipation
0888
6-73
I
SSI32C452
Storage Controller
D. C. CHARACTERISTICS (continued)
PARAMETER
CONDITIONS
MIN
IL
Input Leakage
OV
c..>
c..>
2
4443 42 41
...J
< > z
GPI02
1
0
C
C c'" '"
c
< <
< <
0
AD5
INPUT
AD6
OUTPUT
AD7
40
39
AD4
38
AD5
37
AD6
OUTPUT
10
36
AD7
INDEX
11
35
I1D"
vm
INDEX
1m"
SECTOR
12
34
SECTOR
WFI"
~
13
33
cs
cs
1'!ST
SYSCLK
14
32
WAIl/Alim"
RG
15
31
NRZ
WG
16
30
RD/REFCLK
NC
17
18 19 20 21
29
NC
WAlNAIm
SYSCLK
RG
NRZ
WG
ROIREFCLK
01
DO
03
02
05
04
07
06
GNO
22
C c'" :g I:i cz
Cl
23 24 25 26 27 28
zc..>
c..>
Z
~
2i
~
8
GNO
DIP
PLCC
ORDERING INFORMATION
PART DESCRIPTION
SSI 32C452 Storage Controller
ORDER NO.
PKG.MARK
40 Pin DIP
SSI 32C452-CP
32C452-CP
44 Pin PLCC
SSI 32C452-CH
32C452-CH
No responsibility is assumed by SSi for use of this product nor for any infringements of patents and trademarks or other rights of third parties
resulting from its use. No license is granted under any patents. patent rights or trademarks of SSi. SSi reserves the right to make changes
in specifications at any time without notice.
CA 92680, (714) 731-7110, TWX 910-595-2809
Silicon Systems, Inc.,14351 Myford Road, Tustin
©1988 Silicon Systems, Inc.
6-84
0888
SSI32C452A
Storage Controller
INNOVATORS IN INTEGRATION
August, 1988
DESCRIPTION
FEATURES
The SSI 32C452A Storage Controller is a CMOS
device that provides the basis for an intelligent Winchester disk drive controller capable of non-interleaved
data transfers at rates up to 20 Mbps. When combined
with a microprocessor, memory and a buffer management device such as the SSI 32C453, the SSI
32C452A implements a powerful and cost-efficient
peripheral controller solution. It also has the flexibility to
be used in SCSI systems.
•
•
•
Operates with 16 MHz microprocessors
•
Internal user programmable ECC to 64 bits
•
•
•
•
Internal 16 bit CRC
The SSI 32C452A includes a control sequencer with a
writeable control store, and configuration/status registers which can be programmed to support standard
and custom interface protocols for storage controllers.
Access to the control store and registers is accomplished through the microprocessor interface which is
optimized for 8 bit, multiplexed address/data bus processors such as the 8085. It also has the flexibility to
interface with most standard 8-bit microprocessors.
This organization allows the controller firmware to be
stored in an EPROM or the host and down-loaded to
the SSI 32C452A, and means wide flexibility of the
control functions performed by the device.
Supports all serial data storage Interfaces
Internal RAM-based control sequencer
Non-Interleaved data transfer to 15 Mbps
Hard or soft sector formats
Programmable sector lengths up to a full
track
•
•
Functionally compatible with AIC-011
•
Single 5 volt supply
•
Available In 44-pln PLCC or 40-pln DIP
package
High performance, low power CMOS device
(Continued)
BLOCK DIAGRAM
I
BUFFER
:~~
RDlREFCLK
ECC&CRC
GENERATION AND
CHECKING
NRZ
INTERFACE
00· 07
/
S
"RIl"
INDEX
•
SECTOR
RG
WG
SEQUENCER
WAINAMl)
AND
SxSSTACK
RAM
WI!
CS
ALE
MICROPROCESSCR
INTERFACE
STATUS AND
CONTROL
ADO-AD7
0888
REGISTERS
/
GPIOO
GPI01
GPI02
GPI03
INPUT
OUTPUT
GENERAL
PURPOSE
va
"S
I I I I
vcc
GND
mT SVSClK
6-85
l
CAUTION: Use handling procedures necessary
for a static sensitive device.
I
SSI32C452A
Storage Controller
DESCRIPTION (Continued)
The SSI32C452A performs all the controller functions
for the peripheral device, such as serialization/deserialization, ECC generation and checking on the data
stream, and CRC generation and checking on the
header or data stream. It also handles overhead information such as address marks, gaps and sector 10
fields. If an ECC error is detected during a read, the
syndrome is saved so that defects can be corrected.
The ECC polynomial and register length can be programmed or bypassed entirely so that external ECC
hardware can be used.
FUNCTIONAL DESCRIPTION
The major functional elements and data paths of the
SSI 32C452A are shown in the block diagram.
The SSI 32C452A performs the functions to interface
a serial data storage device such as a Winchester disk
drive, to a parallel bus interface for data processing on
a byte wide basis. The functions necessary to accurately make this conversion are serialization/deserialization, error detection and correction for both the
header information and data stream, and data path
control. The SSI 32C452A also has general purpose
interface lines to further facilitate control of the data
storage device or parallel interface. An eight byte stack
allows data to be saved and reviewed by the microprocessor for error handling purposes. The internal sequencer performs most of the operations In conjunction with the control and status registers. The sequencer program is contained in internal sequencer
RAM, which is easily (re)programmed providing almost
infinite flexibility in communcations protocols and
control features. A microprocessor effects both initialization and control ofthe SSI32C452A by writing to and
reading from the internal registers, sequencer RAM,
stack and general purpose 1/0 circuitry. The microprocessor interface block of the SSI32C452A provides the
communication and control for the SSI32C452A interface to the microprocessor.
The buffer Interface includes a bidirectional data bus
that exchanges data bytes between an external buffer
memory and the serializer/deserializer. It generates
two clocks, ClKA and ClKB which control all accesses
to the buffer memory. All buffer memory cycles must be
synchronous with ClKA, which is derived from the RDI
REFClK input during data transfers and from SYSClK
otherwise. The internal register ClKCON contains
control bits which define the relationship between
these source clocks and ClKA. The ClKB signal is
asserted whenever a new data byte must be transferred (ie. when the serializer/deserializer is full during
a read operation or empty during a write operation).
The direction of the transfer is determined from the
state of the read gate (RG) and write gate (WG) lines.
A CD.
POLv..
POlva
ECCM
POL'"
POLv.
POLY18
RESCON
I
I
POLY56
POLY24
I
I
seoaR
SEONA
SEOADDA
SEQSTAT
n
RAPL
OPCO.
a
~
RAPH
WAPL
WAMCON
AMDCOH
D
K-~
GPtoCON
GPIODAT
CJ:r~ z
OUTPUT
NRZ
WG
~~
GPI02
WAlNAf.l!l"
SYSCLK
Cl
'"
0
III
0
....
0
29
22 23 24 25 26 27 28
0
z
Cl
()
()
z z 8
z;
N
0
RD/REFCLK
NC
8
GNO
DIP
PLCC
ORDERING INFORMATION
PART DESCRIPTION
SSI 32C452A Storage Controller
ORDER NO.
PKG.MARK
40 Pin DIP
SSI 32C452A-CP
32C452A-CP
44 Pin PLCC
SSI 32C452A-CH
32C452A-CH
No responsibility is assumed by SSi for use of this product nor for any infringements of patents and trademarks or other rights of third parties
resulting from its use. No license is granted under any patents, patent rights or trademarks of SSi. SSi reserves the right to make changes
in specifications at any time without notice.
Silicon Systems, Inc.,14351 Myford Road, Tustin
©1988 Silicon Systems, Inc.
6-120
CA 92680, (714) 731-7110, TWX 910-595-2809
0888
SS132.C453
Dual Port
Buffer Controller
INNOVATORS IN INTEGRATION
August, 1988
DESCRIPTION
FEATURES
TheSSI32C453 Dual Port Buffer Controller is a CMOS
device that allows low speed RAM to be configured as
a dual port circular FIFO buffer. It generates all the
buffer memory addressing required and manages two
ports: Port A, a synchronous peripheral device interface and Port B, an asynchronous host interface. The
SSI 32C453 has arbitration logic to support the SCSI
protOCOl, host DMA transfers and uninterruptible peripheral block transfers.
• Dual pon circular FIFO buffer controller
On-chip counters generate the addresses needed to
access the external RAM. In extended addressing
mode, 16 bits of address are multiplexed onto 8 lines
and the necessary strobes are provided. Direct addressing mode may be used for 10 bit addresses (DIP
package) or 14 bit addresses (PLCC package) without
multiplexing.
• SCSI bus arbitration control
• DMA handshake control
• Multiplexed mode buffer addressing up to
64 Kbytes
• Direct mode buffer addressing up to 1 Kbyte
(DIP) or 16 Kbytes (PLCC)
• High speed CMOS device has 16 MHz microprocessor Interface
• Compatible with SSI32C452 Storage Controller
• Plug and software compatible with Ale-SOD
buffer controller
• Single 5V supply
• Available in 44-pin PLCC or 40-pln DIP package
The SSI 32C453 is intended for use in intelligent controllers and includesa set of configuration/status registers which are accessed through the microprocessor
interface. It is optimized for 8 bit, multiplexed addresS!
BLOCK DIAGRAM
~:: -A13~
A12J1:lll1r
All
Al0
DP
A9I5
SHP
:: _
_ _
AG-A7 ....
CONTROLINFORMATON
BUFFER
INTERFACE
"
AD
WR:
MICRO-
ALE
BUFFER
ADDRESS
-I
ADDRESS
/
GENERATOR
PROCESSOR
INTERFACE
4
ADG-AD7
' f =~
.--
PORTB
INTERFACE
cs
vcc
AO
BREO
Al
BACK
A2
LO
A3
l!Ot:'
~
A4
~
l!Ot:'
AS
El
LO
BACK
BREQ
AS
"ET
A7
SELIN
ASlSHP
A915DP
8
SCSI
STATUS AND
ABRITRATION
LOGIC
REGISTERS
ttt t
I I I I
VCCGND
0888
Jmm
~
CONTROL
...
PORTA
INTERFACE
18
-
cs
PIN DIAGRAM
1mT
BSYOUT
BSYIN
SELOUT
SELIN
"ET
ET
ALE
1mT
AREa
m
1m
SELOUT
BSYIN
BSYOUT
~
'!!S
ADO
ADl
WAC
AD2
AD7
AD3
ADa
AD4
GND
ADS
tl[R'
6-121
CAUTION: Use handling procedures necessary
for a static sensitive component.
SSI32C453
Dual Port
Buffer Controller
DESCRIPTION (Continued)
data bus processors such as the 8085 or 8051, and will
also interface easily to most 8 bit microprocessors. The
registers allow the designer to select buffer RAM sizes,
manipulate the internal address pointers and sense
impending overruns of the buffer.
The SSI 453 provides a cost-effective buffer memory
and SCSI port control solution, and when used in
conju nction with an 8 bit microprocessor and a peripheral controller device, such as the SSI452, itforms the
basis for an intelligent, high performance Winchester
disk drive control system.
FUNCTIONAL DESCRIPTION
The major functional elements and data paths of the
SSI 453 are shown inthe block diagram. Data transfers
are requested through two ports, Port A and Port B. The
direction of and number of bytes to be transferred are
determined by the setting of the status and control
register. All buffer memory transfers are synchronous
with the ClK signal.
The pon A Interface communicates with the peripheral device controller. The AREQ signal is monitored
by the SSI 453 and when asserted begins the Port A
data transfer. The SSI 453 then generates the necessary address and control signal to coordinate data
transfer between buffer and peripheral device.
The pon B Interface communicates with the host bus.
It supports a two wire requesVacknowledge protocol
for transferring data asynchronously, and generates
the necessary strobes, lO and BOE, for controlling and
external latch and three-state drivers for host bus
access.
Since peripheral data transfers occur synchronously
and in blocks, Port A requests are alway honored over
Port B requests. If the speed of the data transfer from
the peripheral device allows, the SSI 453 has the
capability to alternate Port A and Port B data transfers
so that time is not lost waiting on the peripheral device.
The buffer Interface generates buffer memory read
and write cycles during data transfers and presents
either the Port A or Port B address to the memory. Its
memory address lines can be operated in one of two
user selectable modes, supporting buffer sizes from
256 bytes to 64 Kbytes.ln direct addressing mode, the
buffer address is available on either 10 lines (AO-A9) or
14 lines (AO-A13), depending on the chosen buffer
size. If larger buffer sizes are required, extended addressing mode supports up to 16 address lines multiplexed onto pins AO-A7. Two external 8 bit three-state
latches must be provided to hold the upper 8 bits of the
Port A and Port B addresses. The buffer interface
provides the signals SOP and SHP for clocking the
latches, and DOE and HOE for enabling the latch
outputs at the appropriate times.
The address generator contains two 16 bit pointers,
the read address pointer (RAP) and the write address
pointer (WAP), which indicate where in the external
buffer RAM data is to be read or written. During data
transfers, these pointers are automatically incremented as the RAM is accessed. The pointers wrap
around to 0 when the programmed buffer size is
exceeded. To prevent host overruns of the buffer
(caused by one of the pointers overtaking the other),
the address generator includes a 16 bit stop pointer
(SP). The microprocessor loads SP with the last address in buffer memory to be accessed during a host
DMA transfer. When the port B address (RAP during an
upload to the host or WAP during a download to the
peripheral) reaches the value in SP, the DMA transfer
is automatically suspended.
The SSI 453 includes the necessary Iogicto request a
SCSI arbitration phase. When the microprocessor
enables the SCSI logic, it will wait for a 'bus free'
condition and then request arbitration. The microprocessor must generate the device address and determine whether the arbitration was favorable or not. Two
output pins EI and ET, are provided to allowthe SSI453
to be identified as either a target or an initiator.
The microprocessor Interface decodes microprocessor read and write requests and provides access to
the appropriate status or control register location.
Since both data and address information are carried on
the bus lines ADO-AD7, the microprocessor signal ALE
(address latch enable) is used to indicate the presence
of a valid address on the bus.
The status and control registers contain operational
status for, and control information from, the microprocessor. They include data transfer and port status and
information such as transfer complete or current address. The control registers configure the SSI 453 with
parameters such as buffer size, read and write pointers
and stop pointer.
6-122
0888
SSI32C453
Dual Port
Buffer Controller
PIN DESCRIPTION
GENERAL
NAME
DIP
VCC
40
1
GND
20-21
22
RST
13
14
I
RESET - Active low signal sets reset bit in RESCON and resets all
other registers.
ClK
15
16
I
MASTER CLOCK - All buffer memory transfers occuron a falling edge
of ClK. There should be at least two ClK cycles per byte transferred
to allow the host and peripheral to remain in step.
PLCC TYPE
DESCRIPTION
POWER SUPPLY
+5 volts
GROUND
MICROPROCESSOR INTERFACE
CS
1
2
I
CHIP SELECT- Active high signal enables device to respond to
microprocessor read or write.
ALE
12
13
I
ADDRESS lATCH ENABLE - Falling edge latches register address
from ADO-AD7 pins.
RD
16
18
I
READ STROBE - Active low signal causes the contents of the
addressed register to be placed on the addressldatabus if CS is also
active.
WR
17
19
I
WRITE STROBE - Active low signal causes the data on the address/
data bus to be written to the addressed register if CS is also active.
18-19
21-26
20-21
23-28
I/O
ADDRESSIDATABUS - 8 bit bus which carries register address information and bi-directional data.
ADO-AD7
BUFFER MEMORY INTERFACE
0888
AO-A7
2-9
3-10
0
BUFFER ADDRESS BITS - In direct addressing mode, these are
buffer address bits 0 to 7. In extended addressing mode, these lines
are multiplexed between low and high order address bytes.
A8/SHP
10
11
0
A8/PORT B (HOST) ADDRESS STROBE - In direct addressing
mode, this pin is buffer address bit 8. In extended addressing mode,
this pin is an address strobe whose rising edge is used to clock the
contents of pins AO-7 into an external latch , for the upper address byte
for Port B transfers.
6-123
I
SSI32C453
Dual Port
Buffer Controller
PIN DESCRIPTION (Continued)
BUFFER MEMORY INTERFACE (Continued)
NAME
DIP
A9/SDP
11
PLCC TYPE
DESCRIPTION
12
0
A9/PORT A (DEVICE) ADDRESS STROBE - In direct addressing
mode, this pin is buffer address bit 9. In extended addressing
mode,this pin is an address strobe whose rising edge is used to clock
the contents of pins AO-7 into an external latch, containing the upper
address byte for Port A transfers.
17,29
0
Buffer address bits - They are valid in both addressing modes. (PlCC
version only)
A12/HOE
30
0
A121PORT B (HOST) ADDRESS ENABLE - In direct addressing
mode this pin is buffer address bit 12. In extended addressing mode
this pin is an active low signal used to enable an external three-state
latch which holds the upper address byte for Port B transfers. (PlCC
version only)
A13/DOE
31
0
A13/PORT A (DEVICE) ADDRESS ENABLE - In direct addressing
mode this pin is buffer address bit 13. In extended addressing mode
this pin is an active low signal used to enable an external three-state
latch which holds the upper address byte for Port A transfers. (PlCC
version only)
A10-11
MS
27
32
0
MEMORY SElECT- This active low output is used to enable the
buffer RAM for read or write access.
WE
28
33
0
WRITE ENABLE - This active low output enables a write to the buffer
RAM, in conjunction with MS. If MS is active while WE is inactive, the
buffer access will be a read operation.
15
I
PORT A REQU EST - This active low input is sampled on each falling
edge of ClK. If it is low, a Port A transfer will occur on the next falling
edge of ClK.
40
0
PORT B INPUT ENABLE - Active low signal used to enable output of
an external three-state driver which presents host bus data to the
buffer RAM. This line is asserted either under microprocessor control
or as a result of a Port B DMA transfer request (BREQ). Microprocessor control of this Une permits di rect host to microprocessor transfers.
PORT A INTERFACE
AREQ
14
PORT B INTERFACE
BIE
35
6-124
0888
SSI32C453
Dual Port
Buffer Controller
PIN DESCRIPTION (Continued)
PORT B INTERFACE (Continued)
NAME
DIP
PLCC TYPE
DESCRIPTION
BOE
36
41
0
PORT B OUTPUT ENABLE - Active low signal used to enable output
of an external three-state driver which holds buffer RAM output and
presents it to the host data bus. This line is asserted either under
microprocessor control or as a result of a Port B DMA transferrequest
(BREQ). Microprocessor control of this line permits direct microprocessor to host transfers.
LO
37
42
0
PORT B OUTPUT LATCH - Active high signal controls an external
latch which holds buffer RAM output during Port B read operations.
BACK
38
43
I
PORT B ACKNOWLEDGE - Active high input signal from the host
indicates that a Port B transfer request has been accepted andthatthe
host bus is available.
BREQ
39
44
0
PORT B REQUEST - Active high output that requests the host to
accept a Port B data transfer.
SCSI BUS ARBITRATION
0888
BSYOUT
29
34
0
BUSY OUT - Active high output that is set either by the microprocessor or the arbitration logic and indicates that the SSI 32C453 is
requesting control of the SCSI bus.
BSYIN
30
35
I
BUSY IN - Active high input which indicates that another device has
control of the bus.
SELOUT
31
36
0
SELECT OUT - Active high output under microprocessor control
which is asserted when bus access is granted to the peripheral
controller.
SELIN
32
37
I
SELECT IN - Active high input which indicates that another device has
been granted access to the bus.
ET
33
38
0
ENABLE TARGET MODE - Active low output which allows the
microprocessor to identify the peripheral controller as a SCSI Target
device.
EI
34
39
0
ENABLE INITIATOR MODE - Active low output which allows the
microprocessor to identify the peripheral controller as a SCSI Initiator
device.
6-125
I
SSI32C453
Dual Port
Buffer Controller
REGISTER DESCRIPTION
The external registers are described at the end of this
section. They are not implemented in either the
SSI32C453 or SSI 32C452, and are assumed to be
implemented in external hardware. They are included
as an applications suggestion for a 'standard' peripheral controller design.
The microprocessor which controls the system has
access to all the SSI 32C453 registers through its external memory address space. The SSI32C453 and its
companion device, the SSI32C452 storage controller,
are designed to occupy a single 256 byte page. The 8
bit page address is latched into the SSI 32C453 from
pins ADO-AD7 on a falling edge of ALE and remains
valid until the next ALE falling edge.
551 32C453 REGISTER BIT MAP
REGISTER
ADDRESS
D7
D6
D5
D4
D3
D2
D1
DO
ACCESS
IFCON
52H
BSYOUT
SELOUT
BSYIN
SELIN
BOE
BIE
unused
ARB
RIW
DMACON
53H
TARGET
INIT
DMADONE
ROPiWOP"
RDLATCH
WRLATCH
BACK
unused
RIW
BUFSIZE
54H
BUFFER SIZE
AMODCON
55H
reserved
AMOD
W
RESCON
59H
unused
RESET
W
RAPL
5AH
READ ADDRESS POINTER (0·7)
RIW
RAPH
5BH
READ ADDRESS POINTER (8-15)
RIW
WAPL
5CH
WRITE ADDRESS POINTER (0·7)
RIW
WAPH
5DH
WRITE ADDRESS POINTER (8·15)
RIW
SPL
5EH
STOP POINTER (0·7)
RIW
SPH
5FH
STOP POINTER (8-15)
RIW
6-126
RIW
0888
SSI32C453
Dual Port
Buffer Controller
INTERNAL REGISTER DESCRIPTION
IFCON 52H
READ/WRITE
INTERFACE CONTROL WORD - Controls and monitors host bus interface and SCSI bus arbitration.
BIT
NAME
DESCRIPTION
0
ARB
ARBITRATION - This bit controls the SCSI bus arbitration and returns its status. When
it is set, the SS132C453 will look for a 'bus free: condition (both SELIN and BSYIN false)
and then assert BSYOUT and BOE, so that the device address may be sent to the host.
When ARB is reset, the arbitration activity ceases. When the ARB bit is read it indicates
that a SCSI arbitration phase has been recognized if it is set, or not if it is reset.
1
-
unused
2
BIE
BUS INPUT ENABLE - While this bit is set, the BIE output pin will be asserted if the
microprocessor reads locations 50H or 51H (see external registers), enabling an
external driver to pass host data to the buffer memory. (Note thatthe BIE pin may also
be asserted automatically during DMA operations).
3
BCE
BUS OUTPUT ENABLE - While this bit is set, the BCE output pin will be asserted if the
microprocessor writes locations 50H or 51 H (see external registers), enabling an
external three-state latch to drive buffer data onto the host data bus. (Note that the BOE
pin may also be asserted automatically during DMA operations).
4
SELIN
SELECT IN - This bit reflects the status of the SELIN pin and is read only.
5
BSYIN
BUSY IN - This bit reflects the status of the BSYIN pin and is read only.
6
SELOUT
SELECT OUT - This bit directly controls the SELOUT pin.
7
BSYOUT
BUSY OUT - This bit directly controls the BSYOUT pin.
Reset State: IFCON= OOH
0888
6-127
I
SSI32C453
Dual Port
Buffer Controller
INTERNAL REGISTER DESCRIPTION
DMACON
53H
(Continued)
READ/WRITE
DMA CONTROL WORD - Used to initiate and control DMA transfers.
BIT
NAME
DESCRIPTION
0
-
unused
1
BACK
PORT B ACKNOWLEDGE - This read only bit reflects the status of the BACK pin,
which is set when the host acknowledges a Port B DMA transfer request from the
SS132C453.
2
WRLATCH
WRITE LATCH - When this bit is set, a host bus to buffer RAM DMA transfer will be
initiated. The transfer continues until the address pointer in WAPLIWAPH is equal to
the stop value in SPUSPH. The ROP/WOP bit in this register must be cleared. Until
WRLATCH is reset, transfers will resume each time the stop pointer is changed.
3
RDLATCH
READ LATCH - When this bit is set, a buffer RAM to host bus DMA transfer will be
initiated. The transfer continues until the address pointer in RAPURAPH is equalto the
stopvalueinSPUSPH. The ROPIWOPbit inthis register must be set. Until RDLATCH
is reset, transfers will resume each time the stop pointer is changed.
4
ROP/WOP
READIWRITE OPERATION SELECT- This bit determines the direction of DMA to
buffer transfer.
5
DMADONE
DMA DONE - This read only bitis set when a DMA transfer is completed (read or write
address pointer reaches stop pointer value) and both BREQ and BACK are inactive.
It is cleared when the stop pointer is updated.
6
INIT
ENABLE INITIATOR MODE - The value written to this bit is inverted and presented on
the EI output pin.
7
TARGET
ENABLE TARGET MODE - The value written to this bit is inverted and presented on
the ET output pin.
Reset State: DMACON=OOH
BUFSIZE
54 READ/WRITE
BUFFER SIZE CONTROL - Used to select buffer size ranging from 256 bytes to 64K bytes. This register
contains an 8 bit unsigned value which sets the buffer size as follows:
Buffer Size = 256.(BUFSIZE+1) bytes
In conjunction with the AMODCON register, this allows buffer sizes from 256 bytes to 64K bytes to be selected
in 256 byte increments.
Reset State: BUFSIZE=OOH
6-128
0888
SSI32C453
Dual Port
Buffer Controller
INTERNAL REGISTER DESCRIPTION (Continued)
AMODCON
55H
WRITE ONLY
ADDRESS MODE CONTROL - Used in direct addressing mode (non-multiplexed address lines) to select the
number of active address lines (10 or 14).
BIT
NAME
DESCRIPTION
0
AMOD
ADDRESSING MODE - In direct addressing mode, this bit determines the number of
address lines supported. If AMOD=1, then 14 lines are supported (AO-A13), and if
cleared then 10 lines are supported (AO-A9) .
1-7
-
reserved
The AMOD bit and the value chosen for buffer size (BUFSIZE) together determine the addressing mode used,
as follows:
Maximum
Eluffer Size
AMQ.O.
Addll!sSiOQ MQd~
ElUESIZE
1 Kb
Direct
0
0-3
(10 lines)
64Kb
4-255
Extended
0
(16 lines multiplexed)
1
0-63
Direct
16 Kb
(14 lines - PLCC version only)
1
64-255
Extended
64Kb
(16 lines multiplexed)
Reset State: AMODCON=OOH
RESCON
59H
WRITE ONLY
RESET CONTROL - Used to return all device registers to a known condition.
BIT
NAME
DESCRIPTION
0
RESET
RESET CONTROL - When this bit is set, all the registers are forced to their reset state.
It must be cleared by the microprocessor. It is set either by the microprocessor or by
hardware, when RST is asserted. When not set, a write to it will reset WAP, RAP and
SP.
1-7
-
unused
Reset State: RESCON=01H
0888
6-129
SSI32C453
Dual Port
Buffer Controller
INTERNAL REGISTER DESCRIPTION (Continued)
RAPL
5AH
READIWRITE
READ ADDRESS POINTER (LOW BYTE) - Lower 8 bits of address where next data byte will be read
from buffer memory during DMA operations. When ROPIWOP is set, peripheral data will be read from the
buffer RAM at this address and transferred to the host data bus, following a Port B DMA request (BREa).
When ROPIWOP is reset, host data will be read from the buffer RAM at this address and transferred to
the peripheral, following Port A transfer requests (AREa).
RAPH
5BH
READIWRITE
READ ADDRESS POINTER (HIGH BYTE) - Upper 8 bits of address where next data byte will be read
from buffer memory.
WAPL
5CH
READ/WRITE
WRITE ADDRESS POINTER (LOW BYTE) - Lower 8 bits of address where next data byte will be written
to buffer memory. When ROPIWOP is set, peripheral data will be written to the buffer RAM at this address, following a Port A transfer request (AREa). When ROPIWOP is reset, host data will be written to
the buffer RAM at this address, following a Port B DMA transfer request (BREa).
WAPH
5DH
READ/WRITE
WRITE ADDRESS POINTER (HIGH BYTE) - Upper 8 bits of address where next data byte will be written
to buffer memory.
SPL
5EH READIWRITE
STOP ADDRESS POINTER (LOW BYTE) - During DMA the stop pointer is compared to RAP, for a
peripheral to host transfer (ROP/WOP is set), or WAP, for a host to peripheral transfer (ROP/WOP is
reset). Whenever the two pointers are equal, DMA is halted. DMA only resumes when the stop pointer is
changed. SPL contains the lower byte of the 16 bit address.
SPH
5FH
READIWRITE
STOP ADDRESS POINTER (HIGH BYTE) - Upper 8 bits of the stop pointer.
0888
SSI32C453
Dual Port
Buffer Controller
EXTERNAL REGISTERS
HOSTL
50H
Read/Write
Special decode - Microprocessor reads from this location will cause the BIE signal to be asserted if the BIE
bit in INTCON is set. The BIE signal causes an external three-state driver to present host data to the buffer
RAM. Microprocessor writes to this location will cause LO and BOE to be asserted in succession, if the BOE
bit in INTCON is set. This allows buffer data to be latched and driven onto the host data bus.
HOSTH
51 H
Read/Write
Special decode - Same function as for external register HOSTL (50H). In systems with 16 bit hosts, external
hardware may be used to distinguish between accesses to locations 50H and 51 H, allowing separate access
to the lower and upper bytes of the host bus.
BUFACC
70H
ReadIWrite
BUFFER ACCESS - Microprocessor accesses to this location cause MS to be asserted. Ifthe access is a write
operation, WE will be asserted as well. This is intended to allow the microprocessor access to the currently
addressed buffer RAM location, without altering the pointer value.
0888
6-131
I
SSI32C453
Dual Port
Buffer Controller
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Ambient Temperature Under Bias
Storage Temperature
Voltage on any Pin with respect to Ground
Power Dissipation
Maximum Current Injection
RATING
UNIT
oto 70
°C
-65 to 150
°C
-0.5 to 7
V
0.475
W
±20
rnA
Note: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
PARAMETERS
CONDITIONS
MIN
NOM
MAX
UNIT
4.75
5.25
V
TA, Operating Free Air Temperature
0
70
°C
Input Low Voltage
0
0.4
V
Input High Voltage
2.4
VCC
V
VCC, Supply Voltage
D.C. CHARACTERISTICS (TA = O°C to 70° C, VCC = recommended range unless otherwise specified.)
PARAMETERS
CONDITIONS
MIN
NOM
MAX
UNIT
VIL
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage
2.0
VCC+0.5
V
VOL
Output Low Voltage
IOL= 2 mA
0.4
V
VOH
Output High Voltage
IOH = 400
ICC
Supply Current
IL
Input Leakage
OV-::1:
~o.
!::
Ol
a:
«
arbitration
delay
2200n5
r"-
r
ZLlJ
oen
-«
~1f
...J
LlJ
C/l
FIGURE 7: SSI 32C453 SCSI Arbitration logic Timing
0888
6-139
SSI32C453
Dual Port
Buffer Controller
APPLICATIONS INFORMATION
SINGLE BLOCK WRITE
EXTERNAL HARDWARE
The following steps must be taken to effect the transfer
of a single block of data from the hostto the peripheral:
As described previously, the SSI 32C4S3 provides a
number of strobe outputs to control extemal interface
hardware. Three different addressing configurations
are illustrated in figures 8 to 11. Because of pin limitations, the DIP version of the SSI 32C4S3 does not
provide either HOE or DOE. These signals may be
recreated with an extemal D flip-flop as shown in
Figure 11. In extended addressing mode, the external
Port A and Port B address latches must be initialized
with explicit writes to the RAPH and WAPH registers,
since only internal registers are initialized upon reset.
To avoid interfering with data transfers, these registers
should only be accessed when both ports are
inactive.The ROPIWOP bit must be set correctly before these registers are written to in extended addressing mode, since this control bit can change which
pointer is associated with which port. An example of
interfacing the SSI 32C4S3 to the SCSI bus is shown
in Figure 12.
1. Initialize SSI32C4S3 using RESET bit, and
select
desired buffer size and addressing mode. (This
will clear ROPIWOP.)
2. Clear RAPH, WAPH explicitly when in extended
addressing mode.
3. Set SP to be equal to the length of the data
block to be transferred.
4. Set the WRLATCH bit so that the DMA
request/acknowledge cycles commence.
5. Wait for DMADONE to be set. (Occurs when
WAP=SP).
6. Instruct peripheral controller to commence
peripheral read.
7. Wait for end of block. (Will be detected by
controller or by observing value of RAP, which
increments automatically).
MUTLIPLE BLOCK READ
A rule of thumb to use when selecting RAM for the
buffer is:
Buller cycle time 8 bitsbyte
3 * bit rate
SINGLE BLOCK READ
The following steps must be taken to effect the transfer
of a single block of data from the peripheral to the host:
1.
2.
3.
4.
5.
6.
7.
8.
Initialize SSI 32C4S3 using RESET bit, and select
desired buffer size and addressing mode.
Select read operation by setting ROPIWOP.
Clear RAPH, WAPH' explicitly when in extended
addressing mode.
Instruct peripheral controller to commence peripheral read.
Waitfor end of block. (Will be detected by controller
or by observing value of WAP, which increments
automatically) .
Load stop pointer (SP) with the value (WAP-1),
since WAP points tothe location afterthe last entry
in the FIFO buffer.
Set the RDLATCH bit so that the DMA request!
acknowledge cycles commence.
Wait for DMADONE to be set. (Occurs when
RAP=SP).
The initial steps in a multiple block read are similar to
those of a single block read. However, once the DMA
transfer of the first block to the host is underway, the
next peripheral block read can occur, provided that the
buffer is sufficiently large to accomodate the next block
of data. (The microprocessor can either check the
value of RAP, or maintain its own count of the number
of blocks currently stored in the buffer, in order to
prevent buffer overruns caused by the peripheral.)
When the next peripheral block transfer has been
initiated, the microprocessor waits for DMADONE to
be set. When the host is ready for a new DMA transfer,
the value of SP may be changed and a new transfer
started (provided there is sufficient data in the buffer to
prevent an overrun).
MULTIPLE BLOCK WRITE
As in the case of multiple block reads, the microprocessor starts by causing a single block of host data to be
transferred to the buffer memory. Thereafter, host and
peripheral transfers may be initiated simultaneously,
provided the microprocessor ensures that a buffer
overrun does not occur.
6-140
0888
SSI32C453
Dual Port
Buffer Controller
7436
LS373
.----------1 0
o
PERIPHERAL DEVICE DATA
D~----~----------------~----
E
HOST
DATA
BUS
LS240
Or--+--_8~--~--~
SS132C453
E
DBo-DB7
LO
~
!lIE"
AO-A7
AO-A7
IT
A6/SP
NJ/SP
AS
NJ
BREO
MS
BACK
rn<
1K
RAM
OE"
M
M
AIirn
mm
FROM PERIPHERAL DEVICE
I
FIGURE 8: Direct Address Mode Example - 10 Address Lines
[ 7438
0
-¥-
' LS373
II---Q
'--~
HOST
DATA
BUS
8/ PERIPHERAL DEVICE DATA
D
-"i'--
LS240
'-- I
8/
0
I
SSI32C453
E
"ErnEQ
BACK
I
LO
-<}
BOI:
M
U
/'1
I
"'-J
BREQ
.J'--.-
BACK
CD<
A8/SPH
A9/SPH
A10
A11
A12A'1OE
A1300E:
AO-A7
/;ffi
M
AS
,L...,.
8
A9
A10
A11
A12
CS 1
DBO-DB7
AO-A7
OE
WE
AREQ
I
CIJ8
l!l!V
BSYOUT
...III
fii
A91SOP
A11rn
=
0
=
=
a
t!
BSYIN
74>8
SELIN
1!E[
l:lJ(7i
SELOUT
~
<
FROM PERIPHERAL
DE VICE
FIGURE 11: Extended Mode Address Strobes
for DIP Package
FIGURE 12: SCSI Bus Interface Example
6-142
0888
g
~
SSI32C452
SSI32B450A
UU-IJf
DBP
DBO-DB7
1!SV
~
~
BSYIN
BSYOUT
lie[
"R!!l:i
ACR
---"To
~
GND
.j:o,.
c.>
16xB
RAM
A7=l
-----eREci
~
c.o
111
I
-
NAZ
WO
RG
RG
WG
AD
WG
A13-A8
I
~
SELOUT
mll"
1.0ATI'/
1m'
m
I
......
SS132C453
SS13205321
NAZ
AD/REFCLK
I
ARm
~
C[K
~
GPIOO
GPI01
INPUT
OUTPUT
SECTOR
INDEX
CS
ALE
RD
AD
WR
ADO-ADa
CK
WFI
I
II
PDOUT
RRC
woe
WSO
WS1
::;
cs
CS
Am
~
VCOlN
:c
~
jJ.
R
C
c
iii
;10;
c
~
m
~
m
::a
~
m
ADo.AD7
SYSCLK
RST
~ ~
on w
11! ;;i
~R~
OOC51
RST
~
XTAl2
l~
~
IlJ
c
'9'
;=...
VSS
°C
o
CIJ
CIJ
-
-
....
~CW
...0.,,0
_1-
FIGURE 13: SCSI Peripheral Controller Chip Set
...
Q)
=00l:I0
CD ...
CJ1
...
_W
SSI32C453
Dual Port
Buffer Controller
PACKAGE PIN DESIGNATIONS
(Top View)
cs
40
AD
39
BREQ
A1
38
BACK
A2
4
vcc
37
LO
A3
36
m:iE"
A4
35
AS
7
34
AS
8
33
mE'
"EI
'ET
A7
9
32
SELIN
A81SHP
10
31
SELOUT
A9ISDP
11
30
BSYIN
ALE
12
29
BSYOUT
lmT
13
28
WE"
ARm
14
27
J;l§
m
15
28
ADO
1m"
WI'!
16
25
AD1
17
24
AD2
AD7
18
23
AD3
ADS
19
22
AD4
GND
20
21
ADS
0:..:
o W0
~
~~-oU)oa:;ao
~
« 0 >
JUMPER
ACTIVITY LAMP
OUT1
DB7
mrT
lIEm7
DII6
ow
WII1mE
P22
RiW
P23
WRrnITr
DRSEl
SEEk COMPLE I E
l5II!II:TD
wus
P21
l'AtJ[T
INDEX
T1
DIRIN
1lIIflI
00. .'
~o-:..
T1
..-0
l!ES"ET
..
GND
10K
""""
JUMPER
tlDEX
REfHEAO
Vee
GROUND
1fmEX
~
ORSI:TD
DBS
"STEP"
ORS"E[
rnm
DB7
"MODE
DB4
WOS"
DB6
SC
TRKO
Vee
sEER COMPLETE
TR"KO
GROUND
.,
WCICARO
CAR1
so
STEP
R6JUMPER
IN1
'I!IIro
DB4
+vcc
"RESET
PHOTO 0
INDEX REFHEAD
tlDEX
OA7V
10K
WU!!
IMJS
MODE
0."
PHOTO 0
0888
T"'O
.11
Vee
CUT 1
0----
6-145
CAUTION: Use handling procedures necessary for
a static sensitive component.
I
SSI328545
Winchester Disk Drive
Support Logic
PIN DESCRIPTIONS
PIN NUMBER
I/O TYPE
PIN NAME
PIN NUMBER
40 PIN
DIP
44 PIN
40 PIN
DIP
44 PIN
PLCC
1
1
13
R3JUMPER
21
23
2
2
03
ACTIVITY LAMP
22
3
3
01
OUT1
23
4
4
11
IN1
5
5
11
P22
I/O TYPE
PIN NAME
INDEX REF HEAD
24
.
.
25
02
SC
24
26
02
WUS
25
27
26
29
PLCC~
PHOTOO
MODE
12
DIRIN
6
7
11
P23
7
8
02
DRSEL
27
30
12
STEP
WUS
28
31
04
DR SLTD
8
9
13
9
10
11
10
11
11
12
02
, 12
13
02
P21
29
32
04
READY
GROUND
30
33
04
INDEX
INDEX
31
34
T1
32
35
04
FAULT
TRKO
GROUND
13
14
02
DIRIN
33
36
04
14
15
11
DB5
34
37
04
SEEK
38
12
WRGATE
ci5~I5[ETE
15
16
12
DRSEL
35
16
18
11
DB7
36
40
01
RIW
17
19
11
DB4
37
41
01
CAR1
18
20
11
DB6
38
42
01
WC/CARO
19
21
02
TRKO
39
43
13
R6JUMPER
RESET
40
44
20
22
11
+VCC
z1 Pins 6,17,28, and 39 are not connected in the 44 Pin QUAD package
·COMPARATOR
6-146
0888
SSI328545
Winchester Disk Drive
Support Logic
ELECTRICAL CHARACTERISTICS
(Unless otherwise specified: 4.5 < Vee < 5.5; O°C < Ta < 70 °C.)
ABSOLUTE MAXIMUM RATINGS
(Operation above absolute maximum ratings may permanently damage the device.)
RATING
UNIT
VCC supply voltage
7
volts
Storage temperature
-65 to + 150
°C
Oto+70
°C
-0.5 to 7.0
VDC
260
°C
PARAMETER
Ambient operating temperature
Logic input voltage
Lead temperature (soldering 10 sec)
LOGIC OUTPUTS (Refer to Pin Descriptions for output type, pin number cross reference.)
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNIT
TYPE 01 (OPEN COLLECTOR) OUTPUTS
Output High Current
VOH =5.5V
250
J,LA
Output Low Voltage
IOL= 16 rnA
0.5
V
0.5
V
-100
mA
TYPE 02 (TOTEM POLE) OUTPUTS
Output High Voltage
10H = -400 J,LA
Output Low Voltage
IOL=8mA
V
2.5
Short Circuit Current
TYPE 03 (OPEN COLLECTOR) OUTPUTS
Output High Current
VOH= VCC
50
J,LA
Output Low Voltage
IOL=30 rnA
0.8
V
TYPE 04 (OPEN COLLECTOR) OUTPUTS
Output High Current
VOH =5.5V
250
J,LA
Output Low Voltage
10L=48 rnA
0.5
V
MAX
UNIT
LOGIC INPUTS
PARAMETER
CONDITIONS
MIN
NOM
TYPE 11 INPUTS
Input Low Voltaae
0888
V
2.0
Input Hiah Voltaae
Input Low Current
VIL-0.5V
Input High Current
VIH = 2.4V
6-147
0.8
V
-0.8
mA
400
J,LA
I
551328545
Winchester Disk Drive
Support Logic
ELECTRICAL CHARACTERISTICS (continued)
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNIT
TYPE 12 (SCHMIDT TRIGGER) INPUTS
Positive going, VCC = 5V
1.3
2.0
V
Negative going, VCC = 5V
0.6
1.1
V
Hysteresis
VCC =5V
0.4
Input High Current
VIH = 2.4V
40
I1A
Input Low Current
VIL = 0.5V
-0.8
mA
Threshold Voltage
V
TYPE 13 (INTERNAL PULLUP) INPUTS
2.0
Input High Voltage
V
Input Low Voltage
Input Low Current
VIL = 0.5V
0.8
V
-1.2
V
MAX
UNIT
580
mV
COMPARATOR INPUTS
PARAMETER
CONDITIONS
Threshold Voltage
Index Ref
MIN
Positive going
Negative going
Photo 0
370
mV
Positive going
Negative going
280
120
Hysteresis
Input Resistance
NOM
mV
mV
30
VCC = 5.0V, O n + 00 n2
if C2 < C 1
then,
NxKDxKVCO and ~=NxKDxKVCOxR
C1
2m n
:.OOn2
F(s) = Vout
lin
which results in:
The phase lock loop can be described as:
C1 NxKDxKVCO
OOn2
+
.""'~.""'"
KD = phase detector gain
F(s} = Filter impedance
[VIA]
KVCO = osci lIator transfer function
[radlvolt - sec]
[Nrad]
OOn-
N = ratio of reference input frequency vs. VCO output
frequency.
0888
NxKDxKVCO
and C2=C1
19
For a ~ = 0.8, the relationship between oon and lock time
is:
where,
s
21;o>n
R
7-11
4.5
lock time
Therefore, the loop filter components C1 ' C2 ' and R can
be evaluated for a required lock time and coding
scheme (N) frequency relationship to the VCO frequency.
SSI34D441
Data Synchronizer & Write
Precompensator Device
Table 3 lists suggested loop filter component values
for various data rates. These values represent only a
starting point for the design of the filter and they may
be changed to meet the performance requirements
of the system.
LOOP FILTER (Continued)
For data rates of 250 Kbits/s, the bit cell is 41J.S long. A
lock time of 3 bytes translates into:
lock time = 3 x 8 x 4 = 96 ~s
Therefore:
TABLE 3:
ron=~=47KracVs
96 us
Cl
R
15.9x 10-6 X 0.96 x 1d' 3500pF
2x (47 x 1cjl)2
2xO.8
9.8KQ
47x 103 x3.5x 10-9
Interruptto
Host CPU
DATA
RATE
LOCK
TIME
LOOP
FILTER
125 KHz
192 ~s
H = 10 Kil, C, = 6800 pF
C2 = 360 pF
250 KHz
96~s
R = 10 Kil, C, = 3300 pF
C2 = 180 pF
500 KHz
46~s
R = 11 Kil, C, = 1500 pF
C 2 =82 pF
1 MHz
24~s
R = 13 Kil, C, = 680 pF
C2 =39 pF
o
2'
17
VPO
oa
07
es
AD
WR
AD
INT
WCK
AOW
AD
OAa
WOA
PSO
PSl
eLK
vea
WE
18
21
22
23
-
OROD
VNO
PDGAIN
DRTA
WOO
VPA
,.MHz
J.LPD7265C1j.lPD765AC
OAeK
Te
AST
DO
01
02
D3
D.
OS
XTAL
21
19
20
,.
2S
2.
27
31
,.
22
"
2.
25
11
23
Read Data
write Data
+SV
See Note 2
S9134D441
'9""
30
DMARequest
to Host CPU
WCK
AOW
ADD
ORO
WOA
PSO
PSl
elK
IREF
LPFOUT
Rl
R2
SCLK
+5V
FRlSTP
LCTIDIR
RWISEEK
uso
USl
33
37
38
3.
2.
28
Note 1: Inputs A, B, C, D, and E may either be hardwired to
desired control states, or may be programmable if
controlled externally.
Note 2: A single voltage regulated +5V power supply should
be used forVPA and VPD with appropriate bypassing
capacitor.
FIGURE 5: Application Diagram
7-12
0888
SSI34D441
Data Synchronizer & Write
Precompensator Device
PACKAGE PIN DESIGNATIONS
0
c: '"a:
>
3
2
4
0-
...J
~
LU
>=
28
iii
0
en
0-
0-
27
26
TEST
12
~
>
13
c(
Z
>
14
15
u..
g;;
f:J
Z
u..
~
0-
LU
16
0
17
18
Z
()
(!J
>
en
u::
;;:
...J
0
0-
WE
XTAl
VPD
(Top View)
PSI
PSO
Rl
WDA
25
WOA
24
VNO
23
WOO
22
elK
21
WClK
DRQD
RDD
20
ROO
TEST
RDW
19
ROW
RDTA
VCOSYNC
VND
WDD
ClK
PCl
WClK
z
0
()
>
VPA
PDGAIN
VNA
lPFIN
IREF
lPFOUT
600-mil
28-pin DIP
28-lead PLCC
PLCC pinouts are the same as the 28-pin DIP
THERMAL CHARACTERISTICS: Gja
28-lead PLCC
55°C/W
28-pin POIP
65°C/W
ORDERING INFORMATION
ORDER NO.
PKG.MARK
SSI340441 28-pin POIP
SS1340441-CP
340441-CP
SSI340441 28-pin PLCC
SSI 340441-CH
340441-CH
PART DESCRIPTION
No responsibility is assumed by SSi for use of this product nor for any infringements of patents and trademarks or other rights of third parties
resulting from its use. No license is granted under any patents, patent rights or trademarks of SSi. SSi reserves the right to make changes
in specifications at any time without notice.
Silicon Systems, Inc., 14351 Myford Road. Tustin,
0888
CA
92680, (714) 731-7110,
TWX 910-595-2809
©1988 Silicon Systems, Inc.
7-13
NOTES:
SSI34P570
2-Channel Floppy Disk
Read/Write Circuit
INNOVATORS IN INTEGRATION
August, 1988
DESCRIPTION
FEATURES
The SSI34P570 is an integrated circuit which performs
the functions of generating write signals, amplifying
and processing read signals required for a doublesided floppy disk drive. The write data circuitry includes switching differential current drivers and the
erase head drive with programmable delay and hold
times. The read data circuitry includes low noise
amplifiers for each channel as well as a programmable
gain stage and necessary equalization and filtering
capability using external passive components. All logic
inputs and outputs are TTL compatible and all timing is
externally programmable for maximum design flexibility. The circuit operates on + 12 volt and +5 volt power
supplies and is available in 28-pin plastic DIP and
PLCC packages.
•
•
•
•
•
•
•
•
BLOCK DIAGRAM
Single-chip read/write amplifier and read data
processing function
Compatible with 8", 5 1/4" and 3 1/2" drives
Internal write and erase current sources, externally set
Control signals are TTL compatible
Schmitt trigger Inputs for higher nOise immunity on bussed control signals
TTL selectable write current boost
Operates on +12 volt and +5 volt power supplies
High gain, low noise, low peak shift (0.3%
typical) read processing circuits
PIN DIAGRAM
+HOO
vcc
-HOO
+Ao
+H01
-Ao
-H01
+IN
CB
-IN
G1
RECE
G2
RE
01
VOO
02
VCT
RfilJ
HSO/HS'f
ROP
WOI
PW
E1
TO
GNO
EO
CAUTION: Use handling procedures necessary
for a sta~c sensitive component.
0888
7-15
I
SSI34P570
2-Channel Floppy Disk
Read/Write Circuit
FUNCTIONAL DESCRIPTION
READ MODE CIRCUITRY
WRITE MODE CIRCUITRY
In the Read Mode (RIW high), the circuit performs the
functions of amplifying and detecting the selected head
output pulses which correspond to magnetic transitions in the media. The read circuitry consists of two
differential preamplifiers, a summing amplifier, a
postamplifier, an active differentiator, a zero-crossing
detector, a time domain filter, and an output one-shot.
In Write Mode (RIW low), the circuit provides controlled
write and erase currents to either of two magnetic
heads. The write-erase circuitry consists of two differential write current drivers, a center tap voltage reference, two eral;le current switches and control circuits
for head selection and erase timing.
Write current is toggled between opposing sides of the
head on each negative transition of the write data input
(WOI) and is set externally by a single resistor, Rw
connected between the Rwterminal and ground. Since
driver output impedance is large, proper damping
resistors must be provided across each head. A signal
at the CB terminal provides write current boost.
Erase current is also set externally through resistors
REC connected in series with each erase coil. Erase
can be activated by, but delayed from, selection of the
write mode, and is held active after mode deselection.
The turn-on delay is determined by the charging of CE
through RED, while the hold time is determined by the
discharge of CE through the series combinatiotl of RED
and REH(see connection diagram). The RECE node
may be driven directly by a logic gate, with external
resistors per Figure 4, if the erase period is to be
controlled separately from the write mode selection.
For applications where no delays are required, CE is
omitted.
The Center Tap Voltage Reference supplies both write
and erase currents. A power turn-on protection circuit
prevents undesired writing or erasure by holding the
voltage reference off until the supply voltages are
within their operating ranges.
The selected preamplifier drives the summing amplifier
whose outputs are AC coupled to the postamplifier
through an external filter network. The postamplifier
adjusts signal amplitudes prior to application of signals
to the active differentiator. PostarnplHier gain is set as
required by connecting a resistor across the gain
terminals, G1 and G2. If desired, an additional frequency/phase compensation network may also be
connected across these gain terminals.
The differentiator, driven by the postamplifier, provides
zero-crossing output voltages in response to input
signal peaks. Oifferentiator response characteristics
are set by an external capacitor or more complex series
network connected between the 01 and 02 terminals.
The zero-crossing detector provides a unipolar output
for each positive or negative zero-crossing of the
differentiator output. To enhance signal peak detection the time domain filter inhibits the detection of zerocrossings if they are not sufficiently separated in time.
The filter period is set by an external RC network
connected to the TO pin.
The time domain filter drives the output one-shot which
generates uniform output data pulses. The pulse width
is set by an external RC network connected to the PW
pin. The output one-shot is inhibited while in the write
mode.
7-16
0888
SSI34P570
2-Channel Floppy Disk
Read/Write Circuit
~Vcc ~.25 V; 11.4 V
0°CSTA::;;70°C; Rw = 4300; RED = 62 KO; CE= 0.012 J.l.F; REH = 62 KO; REC= 220 0
ELECTRICAL CHARACTERISTIC Unless otherwise specified, 4.75 V
~Vo~12.6;
ABSOLUTE MAXIMUM RATINGS (Operating above absolute maximum ratings may damage the device.)
PARAMETER
RATING
UNIT
5 V Supply Voltage,Vec
7
V
12 V Supply Voltage, Voo
14
V
65 to +130
°C
130
°C
-0.5 V to 7.0 V
dc
Lead Temperature (Soldering, 10 sec.)
260
°C
Power Dissipation
800
mW
Storage Temperature
Junction Operating Temperature
Logic Input Voltage
POWER SUPPLY CURRENTS
PARAMETER
CONDITIONS
Icc - 5 V Supply Current
100 -
12 V Supply Current
MIN
NOM
MAX
UNIT
Read Mode
35
rnA
Write Mode
38
rnA
Read Mode
26
rnA
Write Mode (excluding
Write & Erase currents)
24
rnA
MAX
UNIT
0.8
V
-0.4
rnA
LOGIC SIGNALS· READIWRITE (RIW), CURRENT BOOST (CB)
PARAMETER
CONDITIONS
MIN
Input Low Voltage (VIL)
Input Low Current (ilL)
VIL = 0.4 V
Input High Voltage (VIH)
Input High Current (IIH)
0888
NOM
2.0
VIH=2.4V
V
20
7-17
JJ.A
SSI34P570
2-Channel Floppy Disk
Read/Write Circuit
LOGIC SIGNALS - WRITE DATA INPUT (WDI), HEAD SELECT (HSO/HS1)
PARAMETER
MIN
CONDITIONS
NOM
MAX
UNIT
Threshold Voltage, VT +
Positive - going
1.4
1.9
V
Threshold Voltage, VT Negative - going
0.6
1.1
V
Hysteresis, VT + to VT-
0.4
V
Input High Current, IIH
VIH =2.4V
20
~
Input Low Current, ilL
VIL = 0.4V
-0.4
rnA
MAX
UNIT
VDD -.5
V
CENTER TAP VOLTAGE REFERENCE
PARAMETER
CONDITIONS
MIN
NOM
Output Voltage (VCT)
Iwc + IE = 3 rnA to 60 rnA
Vcc Turn-Off Threshold
(See Note 1)
4.0
V
VDD Turn-Off Threshold
(See Note 1)
9.6
V
VDD -1.5
VCT Disabled Voltage
1.0
V
NOTE1: Voltage below which center tap voltage reference is disabled.
ERASE OUTPUTS (E1,EO)
PARAMETER
CONDITIONS
MAX
UNIT
Unselected Head Leakage
VEO, VEl = 12.6 V
100
~
Output on Voltage (VEl, VEO)
IE = 50 rnA
0.5
V
MAX
UNIT
25
~
MIN
NOM
WRITE CURRENT
PARAMETER
CONDITIONS
Unselected Head Leakage
VEl, VEO = 12.6 V
Write Current Range
Rw = 820 n to 180 n
3
10
rnA
Current Reference Accuracy
Iwc= 2.3/Rw
Vcs(current boost) = 0.5 V
-5
+5
%
1.0
%
MIN
Write Current Unbalance
Iwc = 3 rnA to 10 rnA
Differential Head Voltage Swing
t.lwc~
Current Boost
Vcs= 2.4 V
5%
NOM
Vpk
12.8
1.251wc
7-18
1.351wc
0888
SSI34P570
2-Channel Floppy Disk
Read/Write Circuit
ERASE TIMING
PARAMETER
CONDITIONS
MIN
Erase Delay Range
RED = 39 KO to 82 KO
CE= 0.0015 IlF to 0.043 IlF
Erase Delay Accuracy
ATED x100 %
TED
Erase Hold Range
Erase Hold Accuracy
ATEH x100 %
TEH
NOM
MAX
UNIT
0.1
1.0
msec
TED = 0.69 RED CE
RED = 39 KO to 82 KO;
CE = 0.0015 IlF to 0.043 IlF
-15
+15
%
REH + RED =78 KO t0164 KO;
CE = 0.0015 IlF to 0.043 IlF
0.2
2.0
msec
TEH= 0.69 (REH + RED) CE
REH + RED = 78 KO to 164 KO;
CE= 0.0015 IlF to 0.043 IlF
-15
+15
%
ELECTRICAL CHARACTERISTICS (Unless otherwise specified: VIN (Preamplifier) = 10 mVp-p sine
wave, dc coupled to center tap. (See Figure 1.) Summing Amplifier Load = 2 KO line-line, ac coupled. VIN
(Postamplifier) = 0.2 Vp-p sine wave, ac coupled; RG = open; Data Pulse Load = 1 Kn to Vcc; CD = 240 pF;
Cm = 100 pF; Rm = 7.5 KO; CPW = 47 pF; Rpw= 7.5 KO.)
READ MODE
PREAMPLIFIER - SUMMING AMPLIFIER
PARAMETER
CONDITIONS
Differential Voltage Gain
Freq. = 250 KHz
MIN
Bandwidth (-3 dB)
0888
85
NOM
MAX
UNIT
115
VN
MHz
3
Gain Flatness
Freq. = dc to 1.5 MHz
Differential Input Impedance
Freq. = 250 KHz
20
KO
Max Differential Output
Voltage Swing
VIN = 250 KHz sine wave,
THDS5%
2.5
Vp-p
Small Signal Differential
Output Resistance
10 s 1.0 mAp-p
Common Mode Rejection Ratio
VIN = 300 mVp-p
@ 500 KHz Inputs Shorted
±1.0
75
dB
0
50
dB
Power Supply Rejection Ratio
A VDD = 300 mVp-p @500 KHz
Inputs shorted to VCT.
50
dB
Channel Isolation
Unselected Channel VIN
100mVp-p @ 500 KHz
Selected channel input
connected to VCT
40
dB
7-19
SSI34P570
2-Channel Floppy Disk
ReadlWrite Circuit
PREAMPLIFIER· SUMMING AMPLIFIER (confd.)
PARAMETER
CONDITIONS
Equivalent Input Noise
Power BW = 10KHz to 1 MHz
Inputs shorted to VCT.
MIN
Center Tap Voltage, VCT
NOM
MAX
UNIT
10
~Vrms
1.5
V
POSTAMPLIFIER· ACTIVE DIFFERENTIATOR
PARAMETER
CONDITIONS
MIN
Ao, Differential Voltage Gain
+ IN, -IN to D1, D2
Freq. = 250 KHz
(See Figure 2)
8.5
Bandwidth (-3 dB)
+ IN< -IN to D1, D2
Co = 0.1 ~F, Ro = 2.5 KO
Gain Flatness
+ IN, -IN to D1, D2
Freq. = dc to 1.5 MHz
CD = 0.1 ~F, Ro = 2.5 KO
Max Differential Output
Voltage Swing
VIN = 250 KHz sine wave,
ac coupled. ~ 5% THD in
voltage across CD.
(See Rgure 2)
5.0
Vp-p
Max Differential Input Voltage
VIN = 250 KHz sine wave,
ac coupled. ~ 5% THD in
voltage across CD.
RG = 1.5 KO
2.5
2.5
Differential Input Impedance
Gain Control Accuracy
MR X100 %
AR
Threshold Differential
Input Voltage. (See Note 2)
NOM
MAX
UNIT
11.5
VN
3
MHz
±1.0
dB
Vp-p
10
AR = AoRG/(8 x 1()3 + RG)
RG=2KO
-25
Min differential input voltage
at post amp that results in a
change of state at RDP
VIN = 250 KHz square wave,
CD = 0.1 ~F, Ro = 500 0, TR,
TF ~0.2 ~ec No overshoot;
Data Pulse from each VIN .
transition. (See Figure 3)
Peak Differentiator Network
Current
KO
+25
%
3.7
mVp-p
1.0
mA
NOTE 2: Threshold Differential Input Voltage can be related to peak shift by the following formula:
Peak Shift = 3.7mv x 100"10
7tVin
where Vin = peak to pe.ak input voltage at post amplifier. Note that this formula demonstrates an
inverse relationship between the input amplitude and the Peak Shift.
7-20
0888
SSI34P570
2-Channel Floppy Disk
ReadlWrite Circuit
TIME DOMAIN FILTER
PARAMETER
CONDITIONS
MIN
Delay Accuracy
TTD = 0.58 RTD x (CTD +
10.11 ) +50 nsec, RTD = 5 KO,
to 10 KO Cro ~ 56 pF.
VIN =50m Vpp @ 250 KHz
square wave, TR, TF ~ 20
nsec, ac coupled. Delay
measured from 50% input
amplitude t01.5 V Data
Pulse
MAX
UNIT
-15
+15
%
TTO = 0.58 RTO x (CTD +
10.11 ) + 50 nsec, RTD = 5 KO
to 10 KO, CTD = 56 pF to
240pF
240
2370
ns
PARAMETER
CONDITIONS
MIN
MAX
UNIT
Width Accuracy
Tpw = 0.58 Rpw x (Cpw +8
x 10.12) + 20 nsec.
Rpw=5 KOto 10 KO
-20
+20
%
dTTD X100 %
TTO
Delay Range
NOM
DATA PULSE
dTPW X100 %
TpW
NOM
Cpw=~36pF
width measured at 1.5V
amplitudes
Active Level Output VoHage
0888
IOH= 400
JJA
Inactive Level Output Leakage
IOL=4 rnA
Pulse Width
Tpw = 0.58 Rpw x (Cpw +8
x10-12) + 20 nsec.
Rpw= 5 KO to 10 KO
Cpw = 36 pF to 200 pF
7-21
V
2.7
145
0.5
V
1225
ns
I
SSI34P570
2-Channel Floppy Disk
Read/Write Circuit
TEST SCHEMATICS
~ ,.-,,~,~pp--~----~----~~
100
VCT
FIGURE 1: PREAMPLIFIER CHARACTERISTICS
Vln
Vin
1-250 KHz
1-250 KHz
Co
VOU!
FIGURE 2:
POSTAMPLIFIER DIFFERENTIAL OUTPUT
VOLTAGE SWING AND VOLTAGE GAIN
FIGURE 3:
POSTAMPLIFIER THRESHOLD DIFFERENTIAL
INPUT VOLTAGE
7-22
0888
SSI34P570
2-Channel Floppy Disk
Read/Write Circuit
Vee
N.C.
B
N.C.
MOS
Gat.
10K
SSI
34P571l
SSI
34P570
Output HI = Erase Coil Active
FIGURE 4 : EXTERNAL ERASE CONTROL CONNECTIONS
0888
7-23
I
SSI34P570
2-Channel Floppy Disk
Read/Write Circuit
PACKAGE PIN DESIGNATIONS
THERMAL CHARACTERISTICS: 0 ja
(TOP VIEW)
vcc
+HDO
-HDO
Ei
=t
28-Pin
DIP
55°C/W
28-Pin
PLCC
65°CIW
0
0
J:
0
+
=t
J:
3
2
0
0
+
:8
>
~
+
l'
28
27
26
0
+Ao
+HD1
-Ao
-HD1
+IN
4
CB
5
0
25
+IN
-IN
CB
-IN
RW
6
24
RW
G1
RECE
7
23
G1
RECE
G2
RE
8
22
G2
RE
D1
Voo
9
21
01
VDD
D2
VCT
10
20
02
VCT
RiW
HsolHSl
11
19
Rfil
HSO/Hm"
RDP
WDI
PW
E1
TD
GND
EO
12
13
14
15
16
17
18
~
W
'"Clz
0
~
"-
3:
"0
w
a:
28-Pln PLCC
28-Pin DIP
ORDERING INFORMATION
ORDER NO.
PKG.MARK
SSI 34P570 28-Pin DIP
SSI 34P570-CP
34P570-CP
SSI 34P570 28-Pin PLCC
SSI 34P570-CH
34P570-CH
PART DESCRIPTION
No responsibility is assumed by SSi for use of this product nor for any infringements of patents and trademarks or other rights of third parties
resulting from its use. No license is granted under any patents, patent rights or trademarks of SSi. SSi reserves the right to make changes
in specifications at any time without notice.
14351 Myford Road, Tustin, CA 92680
(714) 731-7110, TWX 910-595-2809
7-24
0888
SSI34R575
2 or 4-Channel Floppy Disk
Read/Write Circuit
INNOVATORS IN INTEGRATION
August, 1988
DESCRIPTION
FEATURES
The 551 34R575 device is a bipolar monolithic integrated circuit used in floppy disk systems for head
control and write, erase, and read selectfunctions. The
device has either two or four discrete read, write, and
erase channels. Channel select inputs are TTL compatible. The 551 34R575 device requires +5 V and
+12 V power supplies and is available in 18-pin
(2-channel version) or 24-pin (4-channel version) dual
inline packages.
•
Operates on +5 V, +12 V power supplies
•
Two or four channel capability
•
TTL compatible control Inputs
•
ReadIWrlte functions on one-chip
•
Internal center tap voltage source
•
suppons all disk sizes
•
Applicable to tape systems
PIN DIAGRAM
BLOCK DIAGRAM
WG
we
Voo
E2
EO
Voo
HOX
GNO
HOY
H1X
HSl
H1Y
H2X
H2Y
H3X
H3Y
Vee
veT
WD
we
CAUTION: Use handling procedures necessary
for a static sensitive component.
0888
7-25
SSI34R575
2 or 4-Channel Floppy
Disk ReadlWrite Circuit
FUNCTIONAL DESCRIPTION
The SSI 34R575 functions as a write and erase driver
or as a read amplifier for the selected head. Two TTL
compatible inputs are decoded to select the desired
readlwrite and erase heads. 'Head select logic is
indicated in Table 1. Both the erase gate (EG) and
write gate (WG) lines have internal pull up resistors to
prevent an accidental write or erase condition.
MODE SELECTION
The read or write mode is determined by the write gate
(WG) line. The input is open collector TTL compatible.
With the input low, the circuit is in the write mode. With
the input high (open), the circuit is in the read mode. In
the read mode, orwith the +5 V supply off, the circuit will
not pass write current.
ERASE
The erase operation is controlled by an open collector
TTL compatible input. With erase gate (EG) input high
(open) or the +5 V supply off, the circuit will not pass
erase current. With EG low, the selected open collector erase output will be low and current will be pulled
through the erase heads.
READ MODE
With the WG line high, the read mode is enabled. In the
read mode the circuit functions as a differential amplifier. The state of the head select input determines
which amplifier is active. When the mode or head is
switched, the read output will have a voltage level shift.
External reactive elements must be allowed to recover
before proper reading can commence. A current
diverting circuit prevents any possible write current
from appearing on a head line.
WRITE MODE
With the-wG line low, externally generated write current is mirrored to the selected head and is switched
between head windings by the state of the write data
(WD) signal.
PIN DESCRIPTION
NAME
TYPE
DESCRIPTION
Vcc
+5V
Voo
+12V
HOX-H3X
HOY-H3X
X, Y head connections
DX,DY
X, Y Read Data: Differential read signal out
WG
Write gate: sets write mode of operation
WC
Write current: current mirror used to drive floppy disk heads
WD
Write data line
EG
Erase gate: allows erasure by selected head
EO-E3
Erase head driver connections
HSO-HS1
Head select inputs
GND
Ground
VCT
Center Tap VoHage Source
7-26
0888
SSI34R575
2 or 4-Channel Floppy
Disk Read/Write Circuit
TABLE 1: HEAD SELECT LOGIC
4-CHANNELS
HS1
HSO
HEAD
0
0
0
0
1
1
1
0
2
1
1
3
2-CHANNELS
HS1
HEAD
0
0
1
1
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
(Operating above absolute maximum ratings may damage the device.)
PARAMETER
RATING
UNIT
Vcc
6.0
V
Vdd
14.0
V
10
rnA
18.0
V
-0.3 to + 10
V
-0.3 to Vee + 0.3
V
-5
rnA
-10
rnA
-65 to + 150
°C
Junction Temperature
125
°C
Lead Temperature (Soldering, 10 sec.)
260
°C
DC Supply Voltage:
Write Current
Head Port Voltage
Digital Input Voltages:
DX, DY, HSO, HS1, WD
EG,WG
DX, DY Output Current
VCT Output Current
Storage Temperature Range
0888
7-27
SSI34R575
2 or 4-Channel Floppy
Disk ReadlWrite Circuit
RECOMMENDED OPERATING CONDITIONS (0°C
.N>
·IN
+IN
G1
NOM
MAX
UNIT
ns
ns
ns
ns
700
200
ns
ns
1500
G2
01
TO
02
ns
PW
.HOo
WOI
WO'I4----\
·HD
.HO
Hso.fIl!i5"
891348570
DATA PATH
CHIP
Hso.fIl!i5"
14-----1
·HO
E1
HOST
EO
INTERFACE
RDP
BUS
Ssf 348570
110 PORT
EXPANDER
c::@::l
SPINDLE
MOTOR
....\ r v ' v - - - o .5V
STEPPER MOTOR
FIGURE 2: TYPICAL APPLICATION
0888
7-39
SSI348580
Port Expander
Floppy Disk Drive
PACKAGE PIN DESIGNATIONS
(TOP VIEW)
P23
VCC
2
Wll7iTrnI
28
P22
'Z1
P21
28
P20
MOT15!fOI'I
4
25
NOT USED
15fl'(
5
24
WI'Il'IIi5T
m
6
23
"RmlV
~
7
22
'TRAl:Kli"
PROG
8
21
WR PROT SENSOR
GND
9
20
~
TRACK 0 SENSOR
10
19
TFmEl(
INDEX SENSOR
11
18
RDbATAOUT
GND
12
17
RD DATA IN
RICO
13
16
T1
RlCW
14
Ii
4
3
0
~
gj
D..
2
rnFI
~
~
!l'
28
27
26
0
25
NOT USED
24
WRl'l'I(jT
"STEJS
23
l'IEAlW
0
m
PROG
22
~
WR PROT SENSOR
21
GND
TRACK 0 SENSOR
20
Wlro'E
19
1flljEj{
INDEX SENSOR
12
13
14
15
16
0
0
;=
~
~
>=
z
CI
~
17
18
;;
I
~
0
II:
rnTl'I
28-Pln DIP
28-Pln PLCC
ORDERING INFORMATION
PART DESCRIPTION
ORDER NO.
PKG.MARK
551348580
28-Pin DIP
551 348580-CP
348580-CP
551348580
28-Pin PLCC
551 348580-CH
348580-CH
No responsibility is assumed by SSi for use of this product nor for any infringements of patents and trademarks or other rights of third parties
resulting from its use. No license is granted under any patents, patent rights or trademarks of SSi. SSi reserves the right to make changes
in specifications at any time without notice.
14351 Myford Road, Tustin, CA 92680
(714) 731-7110, TWX 910-595-2809
0888
7-40
SSI35P550
4-Channel Magnetic
Tape Read Circuit
INNOVATORS IN INTEGRATION
August, 1988
DESCRIPTION
FEATURES
Silicon Systems' SSI35P550 combines magnetic tape
head read signal amplification and processing onto a
single integrated circuit. The device accepts up to 4
center-tapped magnetic read heads connected directly to the head inputs; head center tap voltage is
provided by an on-chip reference. The device architecture permits system design flexibility by providing the
external connections between the PreamplHier/MuHiplexer, PostamplHier, Signal Level Detector, and Data
Detector; this allows the implementation of many suitable fiHering combinations. Low noise amplHiers are
used throughout the device. The SSI35P550 operates
on +5 and +12 Volt supplies and has TTL compatible
control signals.
•
4-Channel Multiplexer with differential-Input
Preamplifiers
•
Postampllfler has component-adjustable and
programmable gain
•
On-chip Signal Level Detector with programmable threshold and adjustable delay
•
Data Detection Circuit Includes spurious signal rejection (adjustable time domain filter)
and provides an adjustable uniform Data Pulse
output
•
Available In 4D-pln DIP or 44-pln PLCC plastiC
packages
BLOCK DIAGRAM
DFF.
HETW"""
..v
>EADO
HEAD 1
,,
''
,,
'" ___________________________________ -.1
POST-AMP
r -- ----------------------------------,
,:,
HEAD'
>---+----J13
HEAD3
SIGNAl lEVEL
DETECTOR
I'I
:,,
,
________________J
so
.,
GO
61
G2
'-v-'
CHANNEL SElECT
..v
THRE8HC1D SELECT
GAIN SElECT
+12V
DELAY NETWORK
..v
Note: Shown with typical external circuitry.
Pin #s refer to PLCC pinout.
0888
8-1
CAUTION: Use handling procedures necessary for
a static sensitive component.
SIGNAL
DETECT
SSI35P550
4-Channel Magnetic
Tape Read Circuit
FUNCTIONAL DESCRIPTION
4-CHANNEL PREAMPLIFIER AND MULTIPLEXER
The device contains four low level differential-input
Preamplifiers. The differential output of a single Preamplifier is selectively connected to the Preamplifier
output terminals by means of two logical CHANNEL
SELECT signals, SO and S1. The selected Preamplifier number is the binary value of the logical SELECT
signals for active high voHage levels.
The Preamplifier inputs are intended for connection to
center-tapped magnetic read heads. An appropriate
Preamplifier input bias voltage level is obtained by
connecting the head center taps to the circuit C.T.
VOLT terminal.
The C.T. VOLT terminal is the output of a voHage
reference which has a value to center the Preamplifier
inputs within their operating range.
POSTAMPLIFIER
The Postamplifier is a differential-input, differentialoutput circuit which has two means of gain adjustment.
A continuously-variable gain adjustment is obtained by
use of an external resistor or potentiometer. Discrete
values of gain setting are additionally obtained by
applying combinations of logical signal levels to the
three GAIN SELECT terminals, GO, G1, and G2.
The Postamplifier receives the output signals of the
Preamplifier after frequency selection by an external
filter network. The input characteristics of the Postamplifier are such that the inputs may have DC coupling to
the Preamplifier output, or may be AC coupled with
proper bias of 3V nom.
A suitable coupling capacitor must be connected between the GAIN1, GAIN2terminais independent of the
use of a gain setting resistor.
SIGNAL LEVEL DETECT CIRCUITS
The Signal Level Detect circuits consist of detector
circuits which compare the amplitude of the signal
envelope of the Postamplifier output with a selectable
threshold and provide a logical output level which
indicates the presence of Postamplifier signal greater
than the threshold. AC coupling is required between
the Postamplifier output and the Signal Level Detect
Circuits input. The Signal Level Detect input has
internal bias connections so that no external bias
network is required.
The threshold to which the Postamplifier signals are
compared is selected by means of two THRESHOLD
SELECT logical inputs TO and T1. The result of the
comparison is delayed from appearing at the circuit
SIGNAL DETECT output terminal by means of a delay
circuit which is adjustable by means of external components. The delay associated with signal detection is set
by combinations of capacitor CDS and resistor RDS1.
The delay associated with signal loss is set by combinations of CDS and resistors RDS1 plus RDS2.
DATA DETECTION CIRCUITS
The Data Detection circuits are AC coupled to the
Postamplifier outputs through an (optional) external
filter network and provide logical output pulse signals in
response to positive and negative input signal amplitude peaks. This function is performed by differentiating input signals to obtain zero-crossing voltages at
points of inflection and detecting these crossings to
provide output signals.
To enhance the signal peak detection, spurious inflection points which occur in pairs between true signal
peaks are suppressed by means of the Time Domain
FiHer. The fiHer inhibits the propagation of detected
zero-crossings if they are not sufficiently separated in
time. This time period is set by external capaCitor CTD
and resistor RTD.
Uniform DATA PULSE output signals are provided by
the One-Shot Multivibrator which is triggered by outputs olthe Time Domain Filter. The time duration olthe
DATA PULSE signals is set by external capacitor COP
and RDP.
DC paths through the external fiHer network to the
Signal Level Detect circuits inputs are required to
properly bias the Data Detection circuits. The resistance of each path is not critical and may be as large as
10Kn.
8-2
0888
SSI35P550
4-Channel Magnetic
Tape Read Circuit
PIN DESCRIPTION
NAME
INO -
40-PIN
44-PIN
1
1
Channel 0 (-) input
INO+
2
2
Channel 0 (+) input
IN1 -
3
3
Channel 1 (-) input
IN1 +
4
4
Channel 1 (+) input
IN2 -
5
5
Channel 2 (-) input
6
No internal connection
IN2+
6
7
Channel 2 (+) input
IN3 -
7
8
Channel 3 (-) input
IN3+
8
9
CTVOLT
9
10
N/C
(+) input
Center tap voltage
VCC2
10
11
+ 12 Volt supply connection
AGND
11
12
Analog signal ground
DEL IN
12
13
Input to delay comparator
SIGNAL DETECT
13
14
Output of delay comparator
DPN
14
15
External RC for output pulse width
TDF
15
16
External RC for time-domain delay
17
No internal connection
N/C
DATA PULSE
16
18
Output of time-domain filter
DGND
17
19
Ground
VCC1
18
20
+5 Volt supply
TO
19
21
Threshold select signal (1 of 2)
T1
20
22
Threshold select signal (1 of 2)
CAP1
21
23
External differentiating capacitor
connection
CAP2
22
24
DIF -
23
25
DIF +
24
26
LEV OUT
25
27
28
No internal connection
LEV -
26
29
Inputs to level detector
LEV+
27
30
GO
28
31
N/C
0888
DESCRIPTION
Inputs to active differentiator
Output to level detector
Postamp gain select (1 of 3)
8-3
SSI35P550
4-Channel Magnetic
Tape Read Circuit
PIN DESCRIPTION (Continued)
NAME
DESCRIPTION
4D-PIN
44-PIN
PSTOUT-
29
32
PSTOUT+
30
33
G1
31
34
Postamp gain select (1 of 3)
GAIN 1
32
35
External Postamplifier gain
adjusting RC terminals
GAIN 2
33
36
PSTIN +
34
37
PSTIN -
35
38
N/C
39
Outputs of Postamplifier
Inputs to Postamplifier
No internal connection
G2
36
40
Postamp gain select (1 of 3)
PREOUT +
37
41
(+) Output of Preamplifier
PREOUT-
38
42
(-) Output of Preamplifier
SO
39
43
Input channel select (1 of 2)
S1
40
44
Input channel select (1 of 2)
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Operation above absolute maximum ratings may permanently damage the device.
PARAMETER
RATING
UNIT
-65 to +150
°C
oto 130
°C
Supply Voltage, VCC1
-0.5 to +6.0
VDC
Supply VoHage, VCC2
-0.5 to +14.0
VDC
VoHage Applied to Logic Inputs
-0.5 to VCC1 +0.5
VDC
VoHage Applied to OFF Logic Outputs
-0.5 to VCC1 +0.5
VDC
5.0
rnA
+260
°C
Storage Temperature
Junction Operating Temperature
Current Into ON Logic Outputs
Lead Temperature (soldering, 10 sec)
0888
SSI35P550
4-Channel Magnetic
Tape Read Circuit
DC CHARACTERISTICS
(Unless otherwise specified, VCC1 = 4.75V to 5.25V, VCC2 = 11.4V to 12.6V, Ta = 0 to 70 °C.)
CHARACTERISTICS
CONDITIONS
MAX
UNITS
Input Current
Logical Inputs HIGH
Vih = VCC1
100
IJ.A
Input Current
Logical Inputs LOW
ViI=OV
-400
IJ.A
Output Voltage
Delay Comparator OFF
loh = -400 IJ.A
Output Voltage
Delay Comparator ON
101=2.0 mA
Data Pulse Inactive
Level Output Voltage
loh = -400 IJ.A
Data Pulse Active
Level Output Voltage
101 =2.0 mA
0.5
V
VCC1 Power Supply Current
No Head Inputs
30
mA
VCC2 Power Supply Current
No Head Inputs
62
mA
MIN
NOM
2.4
V
0.5
2.4
V
V
NOTE: Characteristic applies to Inputs SO, 51, GO, G1, G2, TO, T1
PREAMPLIFIER AND MULTIPLEXER CHARACTERISTICS
Output Load = 2 Kn line-line, Channel Select Signals (SO,S1): VON = 2V Min., VOFF = O.SV Max.
0888
CHARACTERISTICS
CONDITIONS
Differential Voltage Gain
Vin = 4 mV p-p @ 100 KHz
ref. to CT VOLT
Gain Flatness
Vin = 4 mV p-p DC to 0.5 MHz
ref. to CT VOLT
Bandwidth, -1 dB
Vin = 4 mV p-p
1.5
MHz
Bandwidth, -3 dB
Vin = 4 mV p-p
3.0
MHz
Differential Input Impedance
Vin = 4 mV p-p@ 100 KHz
ref to CT VOLT
10
Kn
Common-Mode Rejection Ratio
Vin = 300 mV p-p @ 500 KHz
Inputs shorted to CT VOLT
50
dB
Power Supply Rejection Ratio
t:. VCC = 300 mV p-p @ 500
KHz Inputs shorted to CT VOLT
50
dB
Channel Isolation
Unselected Vin = 100 mV p-p
@ 2 MHz. Selected Channel
inputs connected to CT VOLT
60
dB
MIN
8-5
SO
±0.5
NOM
MAX
UNITS
120
VN
dB
SSI35P550
4-Channel Magnetic
Tape Read Circuit
PREAMPLIFIER AND MULTIPLEXER CHARACTERISTICS
(Continued)
MAX
UNITS
Yin = 0.5 to 6.0 mV
p-p@500KHz
2
%
Equivalent Input Noise
Power BW = 10 KHz to 1MHz
Inputs shorted to CT VOLT
10
~Vrms
Small Signal
Single-Ended Output Res.
10 = 1 mA p-p @ 100 KHz
35
il
Maximum Diff. Output Voltage
Freq = 100 KHz THD < 5%
Output Offset Voltage
Inputs shorted to CT VOLT
Volt Load = Open Circuit
Common-Mode Output Voltage
Inputs shorted to CT VOLT
Volt Load = Open Circuit
CHARACTERISTICS
CONDITIONS
Total Harmonic Distortion
MIN
NOM
Vp-p
3
2.68
±1.0
V
3.5
V
3.0
Center Tap Voltage, CT VOLT
V
DATA DETECTION CIRCUIT CHARACTERISTICS
Yin = 1.0V p-p diff. square wave, Tr, Tf < 20 nsec, dc-coupled (for biasing).
RD = 2.5 Kil; CD = 0.1 ~F; RTO = 7.8 Kil; CTD = 200 pF; RDP = 3.9 Kil;
CDP = 100 pF. Data Pulse load = 2.5 Kil to VCC1 plus 20 pF or less to PWR GND.
UNITS
CONDITIONS
MIN
Differentiator Maximum
Differential Input Voltage
Yin = 100 KHz sine wave,
dc-coupled. < 5% THD in
voltage across CD.
CD = 620 pF RD = 0
5.0
Vp-p
Differentiator Input Impedance
Yin = 4V p-p diff., 100 KHz
sine wave. CD = 620 pF
RD=O
10
Kil
Differentiator Threshold
Differential Input Voltage
Yin = 100 KHz square wave,
Tr, Tf , 0.4 ~ec, no overshoot.
Data Pulse from each
Yin transition.
Data Pulse Width Accuracy
TDP = .59 RDP X CDP,
.85TOP
RDP = .85 TOP 3.9 Kil t010 Kil,
CDP = 75 pF to 300 pF. Width
measured at 1.5V amplitude
8-6
NOM
MAX
CHARACTERISTICS
300
mVp-p
1.15TDP
sec
0888
551 35P550
4-Channel Magnetic
Tape Read Circuit
DATA DETECTION CIRCUIT CHARACTERISTICS
MIN
MAX
UNITS
1.15TTD
sec
Width measure from
1.5V amplitude
±5.0
%
Delay measured from 50%
Input amplitude to 1.5V
Data Pulse amplitude
±5.0
%
CHARACTERISTICS
CONDITIONS
Time Domain Filter
Delay Accuracy
TTD = 0.59 RTD X CTD
+ 50 nsec, RTD = 3.9Kn
to 10 Kn, CTD =100pF
to 750 pF Delay measured
from 50% input amplitude to
1.5V Data Pulse amplitude
Data Pulse Width
Drift from + 25°C value
Time Domain Filter
Delay Drift
from +25 °C value
NOM
.S5TTD
Note: Differentiating network impedance should be chosen such that 1 rnA peak current flows at maximum
signal level and frequency.
SIGNAL LEVEL DETECT CIRCUITS CHARACTERISTICS
Level Comparator Inputs connected in parallel with Differentiator Inputs. Yin (Level Comp) = 100 KHz
sine wave, ac-coupled. RDS1 = 5 Kn; RDS2, CDS = open
0888
CHARACTERISTICS
CONDITIONS
MIN
MAX
UNITS
Level Comparator Input
Thresholds, Single-Ended,
Each Input
TO
VTO = O.SV VT1 = O.SV
Vo pulse value < 0.5V
at MAX LIMIT, >VCC1 - 0.5V
at MIN LIMIT
30
70
mVpk
T1
VTO = 2.0V VT1 = O.SV
Vo pulse Value <0.5V
at MAX LIMIT, >VCC1 - 0.5V
at MIN LIMIT
97
153
mVpk
T2
VTO = O.SV VT1 = 2.0V
Vo pulse value <0.5V
at MAX LIMIT, >VCC1 - 0.5V
at MIN LIMIT
13S
202
mVpk
T3
VTO = 2.0V VT1 = 2.0V
Vo pulse value <0.5V
at MAX LIMIT, >VCC1 - 0.5V
at MIN LIMIT
210
290
mVpk
Level Comparator Diff.
Input Resistance
Yin = 5 VP-P@ 100 KHz
Level Comparator Off
Output Leakage
Vo=VCC1
NOM
Kn
5
25
8-7
I1A
SSI35P550
4-Channel Magnetic
Tape Read Circuit
SIGNAL LEVEL DETECT CIRCUITS CHARACTERISTICS (Continued)
CHARACTERISTICS
CONDITIONS
Level Comparator ON
Output Voltage
VTO = O.SV VT1 .. O.SV
Yin = ±140 mV diff. de 10 '" 2.0 rnA
Delay Comparator Upper
Threshold Voltage
Vo >2.4V
Delay Comparator Lower
Threshold Voltage
Vo <0.5V
Delay Comparator
Input Current
OV < Yin < VCC1
MIN
NOM
MAX
UNITS
0.25
V
.65VCC1
.75VCC1
V
.25VCC1
.35VCC1
V
25
~
POSTAMPLIFIER CHARACTERISTICS
Output Load = 2.5 Kn + 0.1 ILF line-line, Yin = 100 mV p-p, 100 KHz sine wave, de-coupled (to provide
proper biasing). CG = 0.1 ILF, RG .. O.
CHARACTERISTICS
CONDITIONS
Differential Voltage
Gain
AO VGO = O.SV VG1 '" O.SV VG2 .: O.SV
A1 VGO = 2.0V VG1 = O.SV VG2 = O.BV
A2 VGO = O.BV VG1 = 2.0V VG2 = O.SV
A3 VGO .. 2.0V VG1 = 2.0V VG2 = O.BV
A4 VGO '" O.SV VG1 = O.BV VG2 = 2.0V
AS VGO = 2.0V VG1 = O.BV VG2 = 2.0V
A6 VGO = O.SV VG1 = 2.0V VG2 =2.0V
A7 VGO = 2.0V VG1 = 2.0V VG2 = 2.0V
ARG VGO = 2.0V VG1 '" 2.0V
VG2 =2.0V when RG = 2.5 Kn
Differential Input
Impedance
VGO = 2.0V VG1 = 2.0V VG2 =2.0V
10
Kn
Bandwidth,1dB
VGO
.: 2.0V VG2 =2.0V
1.5
MHz
.. 2.0V VG2 '" 2.0V
3.0
MHz
5
Vp-p
MIN
MAX
UNITS
A7 -14.75
A7 -12.75
A7 -10.75
A7-S.75
A7- 6.75
A7- 4.75
A7 - 2.75
32
A7 -7.5
A7 -13.25
A7 -11.25
A7 - 9.25
A7 -7.25
A7 - 5.25
A7 -3.25
A7 -1.25
36
A7 -4.5
dB
dB
dB
dB
dB
dB
dB
dB
dB
Bandwidth,3dB
= 2.0V VG1
VGO = 2.0V VG1
MaximumDiff.
Output Voltage
VGO = O.SV VG1 - O.BV VG2 .. O.SV
VIN = 100 KHz sine wave THO < 5%
Small Signal
Single-Ended
Output Res
VGO = 2.0V VG1 '" 2.0V VG2 = 2.0V
VIN =OV 10 = 1 mA pop, 100 KHz
35
n
Input Bias Offset
Voltage Range
VGO = O.SV VG1 = O.BV VG2 = O.SV
THO < 2.0%
±1.0
V
Input Bias
Common-Mode
Voltage Range
VGO = O.BV VG1 = O.BV VG2 = O.SV
THO < 2.0%
3.5
V
8-8
2.68
0888
SSI35P550
4-Channel Magnetic
Tape Read Circuit
PACKAGE PIN DESIGNATIONS
(TOP VIEW)
45°C/W
60°C/W
S1
SO
PREOUT·
+
~
N
~
i:
e
5
4
PREOUT +
G2
i
c1
~
•
2
~
~
u; Iil
a:
o.
1
44
43
42
g
0
II!
o. S
41
40
NIC
PSTIN·
PSTlN·
PSTIN.
GAIN 2
PSTlN+
GAIN 1
GAIN2
G1
GAIN1
PSTDUT +
DEL IN
G1
PSTDUT·
SIGNAL DETECT
GO
DWP
LEY +
TDF
LEY·
DATA PULSE
PSTOUT·
LEY OUT
DONO
LEY+
DIF+
LEY·
DIF·
VCC1
TO
20
21
22
23
24
25
26
Z1
28
~ if II
8
f'!
1=
;;:
~
a1.
~
I-
\il
18
19
CAP 2
Tl
15
CAP 1
:::>
o.
~
~
0
;!'
a
~
C!
4O-Pln DIP
44-Pln PLCC
ORDERING INFORMATION
ORDER NO.
PKG.MARK
44-Pin PLCC
SSI 35P550-CH
35P550-CH
40-Pin DIP
SSI 35P550-CP
35P550-CP
PART DESCRIPTION
SSI35P550
No responsibility is assumed by SSi for use ofthis product nor for any infringements of patents and trademarks or other rights of third parties
resulting from its use. No license is granted under any patents, patent rights or trademarks of SSi. SSi reserves the right to make changes
in specifications at any time without notice.
(714) 731-7110, TWX 910-595-2809
14351 My/ord Road, Tustin, CA 92680
0688
8-9
NOTES:
Custom/Semicustom
Capabilities
INNOVATORS IN INTEGRATION
SILICON SYSTEMS LEADS THE WAY DEVELOPING MIXED-SIGNAL
CUSTOMISEMICUSTOM PRODUCTS
Silicon Systems is committed to leadership in the development of high-performance, mixed-signal
custom/semicustom application-specific integrated circuits (ASICs).
Silicon Systems offers innovative designs for digital, analog, and mixed analog/digital ICs; a
versatile range of CMOS and bipolar processes; quick-turn design methodologies supported by
advanced and integrated design automation tools; specialized manufacturing facilities; comprehensive test, quality assurance, and prototype assembly programs; and, of course, greater than
15 years of IC design experience. SSi's efforts payoff by dramatically reducing the time (and cost)
it takes to deliver the most optimized custom/semicustom ICs available.
Whether a customer's application falls in SSi's specialty areas of communications, microperipherals, automotive, or other areas, SSi's technical capabilities turn designs around faster and
minimize a product's time to market for the competitive advantage.
DESIGN
ENGINEERING
DISK DRIVES
"R~IWRITE ",'
',I
TELECOM
,
.... AUTOManVE
' '
"MODEMS"
HEAD pc?SITlONING ,
'
,,' ,
'
'PULSE
' TONESIGNAl.ING
' " CUSTOM
,
'-
,
DETECT()fiS : , ' >
DA1;A'AE;COYi:RY "
9-0
TeLEPHO~Y/,
DJG1!AL,TELECOM
""';
'
'; , SEMICU~TPM
Custom/Semicustom
Capabilities
BROAD RANGE OF ANALOG AND DIGITAL DESIGN EXPERIENCE
With a broad base of experience, systems knowledge, and applications expertise, SSi's designers
provide creative IC solutions in both CMOS and bipolar process technologies for analog, digital,
and mixed-signal applications.
In CMOS, SSi has designed digital products ranging from FIFOs to complex hard-disk drive
controllers. Combined analog/digital products range from cross-point switches to complete,
single-chip 2400 BPS modems.
In bipolar, SSi's design expertise focuses on applications requiring high-speed ECl logic
combined with high-performance analog circuitry. Bipolar products range from low-noise amps to
very sophisticated data separators that employ patented phase locked loops.
TECHNIQUE
APPLICATION
9-1
SSi-DESIGNED EXAMPLES
Custom/Semicustom
Capabilities
FULL ANALOG AND DIGITAL INTEGRATION ON THE SAME CHIP
Silicon Systems leads its competition in the design of complete systems on a chip which combine
complex analog and digital functions. The total system solution approach allows designers to
satisfy their application, cost, and performance objectives.
Custom mixed-signal
Bipolar low-noise
read/write Ie
Standard Bipolar mixedsignal, high-performance
data separator
Standard product singlechip 2400 BPS modem with
switched capacitor filters
and RISC DSP
"DESIGN-FOR-TESTABILITY" AND TEST SUPPORT
SSi employs design-for-testability methodologies, such as built-in test modes that allow direct
testing of internal subsystems. SSi uses highly specialized equipment, test programs and test
procedures for combined analog/digital designs to ensure delivery of high-quality product. To
determine product reliability under extreme conditions, products are tested in-house by a wide
variety of advanced analog or digital testers including:
•
LTX (TS88/DX90) testers
•
Eagle (LSI-4) testers
•
Sentry 7 and Sentry 20 digital test systems
These testers are supported by:
•
Automatic handlers (Trigon PLCC, Symtek SOIC, and MCT and Daymarc handlers)
•
Burn-in sockets, temperature chambers, Aehr burn-in ovens, and Highly Accelerated
Stress Test (HAST)
9-2
Custom/Semicustom
Capabilities
CMOS TECHNOLOGIES...
SSi's state-of-the-art CMOS processes have allowed the company to become the leading supplier
of systems-oriented, mixed analog/digital ASICs.
The "CH" process features a unique source/drain structure for higher voltage (12-volt) applications. Poly-poly capacitors support filtering and data conversion (AID and D/A) applications. An
epitaxial substrata provides latch-up protection for ASICs subject to adverse environments (such
as motor control applications). And special poly resistors allow continuous time filters (for antialiasing functions) to be combined with sampled data, switched-capacitor filters, increasing the
level of ASIC integration and lowering overall system manufacturing costs.
CH CMOS PROCESS TRANSISTOR
Nitrite
Passivation
Polysilicon
Thin
Oxide
Aluminum
Interconnect
Field
Oxide
':-;-;-;-::-;-;;-:-:-~~~_ DD D
Source/Drain
DDD
Source/Drain
SID Contacts
PWell
(for NFETs)
Substrate
(Low resistivity)
CMOS PROCESS CHART
PROCESS
TYPE/FEATURES
PRODUCTION
NEW
DESIGNS
. l1ighVoltageM<>t.>IGate .
9-3
GATE
SIZE
(microns)
DIGITAL
ANALOG
INTERCONNECT
LAYERS: PITCH
(microns)
APPLICATION
VOLTAGE
Custom/Semicustom
Capabilities
The "CG" process addresses 5-voltapplications and features 1.5-micron gates and two layers of
metal interconnect for high-performance digital circuitry, along with the dual poly layers required
for analog circuitry. In addition to full-custom standard and customer-proprietary designs, both the
"CH" and "CG" processes support a family of combined analog/digital CMOS arrays.
AND BIPOLAR TECHNOLOGIES
SSi's leading analog/digital bipolar technology is "BK," which supports the development of a wide
variety of high-performance, combined analog/digital ASICs. In addition to full-custom standard
and customer-proprietary designs, the "BK" process supports a family of advanced bipolar analog/
digital arrays.
"BK" features a high-performance NPN (3 GHz FT) with an operating capability of 12 BVCEO. This
process utilizes an advanced polysilicon emitter structure as well as base and collector plugs to
reduce parasitic resistances for high-performance applications. Other key features include metalnitride-poly capacitors, aluminum Schottky diodes, and improved lateral PNPs through the use of
lighter doped epi.
BK BIPOLAR PROCESS NPN TRANSISTOR
Advanced polysilicon emitter
structure for high-performance
NPNs
Up-junction isolation
Base plug for reduced
base resistance
Collector plug for reduced
collector resistance
Lighter doped epi for improved
lateral PNPs, higher NPN BVCEO
and lower junction capacitance '
Buried layer for reduced
collector resistance
BIPOLAR PROCESS CHART
Emitter
PROCESS
TYPE/FEATURES
SIZE
PRODUCTION
NEW
DESIGNS
(microns)
DIGITAL
ANALOG
NPNFT
INTERCONNECT
LAYERS: PITCH
(microns)
eVCEO
(voll$)
Be
"Standard" Cut Emitter Process
Ves
No
6.0
Ves
Ves
1 GHZ
Metal 1 (14.0)
Metal 2 (24.0)
12,,,:
BJ
High-Performance Polysilicon
Emitter Structure
Ves
Ves
3.0
Ves
Yes
3GHZ
Metal 1 (9.0)
Melal 2 (14.0)
9
BK
Base and CoHector Plugs,
Improved Lateral PNPs
Ves
Ves
2.5
Ves
Yes
3GHZ
Melall (90)
Metal 2 (14.0)
12
9-4
Custom/Semicustom
Capabilities
INTEGRATED DESIGN METHODOLOGY.-THE IDM"" ADVANTAGE
Silicon Systems has spent almost 10 years developing its Integrated Design Methodology (IDM'M).
10M consists of an interlocking set of design methods supported by a single Computer-Aided
Engineering (CAE) and Computer-Aided Design (CAD) system. As 10M supports analog and
digital designs in any of SSi's CMOS and bipolartechnologies, it offers the tremendous advantage
of flexibility.
COMPARE FULL-CUSTOM TO SEMICUSTOM DESIGN
10M is based on two major design approaches: full-custom and semicustom.
Full-custom design is a "handcrafted" approach used to produce the most compact, highperformance design possible. Two approaches for full-custom physical design are possible: either
composite or symbolic. In composite design, every process mask layer is drawn down to the
process minimums. This yields the densest, highest-performance designs but is the most timeconsuming approach. Symbolic design utilizes correct-by-construction, stick-like, process symbols, such as resistors, capacitors, and wires. Symbolic design is significantly more productive
than composite and supports a higher level of circuit verification for greater design accuracy.
Semicustom design is an "automated" approach used to produce the most timely and cost-efficient
designs possible. Two approaches are possible: either automatically placed-and-routed library
components, including standard cells, or prefabricated array components.
SSi's analog and digital standard cells are pre-characterized, library-maintained circuits that are
automatically placed and routed to generate a layout. The automatic place-and-route software
also utilizes macro cell assemblers to route full-custom circuitry. The standard cell approach
requires minimal layout effort, leading to lower development cost and a higher first article success
rate.
SSi's mixed-signal arrays are bipolar and CMOS families of integrated circuits which are ninety
percent prefabricated. The base arrays utilize a three-tile, three-segment structure each of which
is targeted for a specific design application, i.e., analog, digital, and reference. The three segments
forming the array core are separated by interconnect "highways" capable of handling both analog
and digital signal busses. The core, in turn, is enclosed by a periphery of predefined I/O functions.
Array customization is achieved by the definition and interconnection of metal and poly-Si layers.
SSi mixed-signal arrays provide a systems designer with fast prototype cycle times, lower
integration costs, and the ability to migrate to either standard cell or custom integration with a
minimum perturbation in design production.
9-5
Custom/Semicustom
Capabilities
CHOOSE THE OPTIMUM DESIGN APPROACH BASED ON TRADE-OFFS
Each 10M design approach offers unique cost, time, and performance tradeoffs.
CUSTOM/SEMICUSTOM TRADE· OFFS
NOTE: All comparisons are normalized to a composite·level design.
MIX FULL-CUSTOM AND SEMICUSTOM DESIGN ON A SINGLE CHIP
Due to the interlocking nature of SSi's design approaches, full-custom and semicustom design can
be mixed on the electrical and/or physical design of any given IC.
Electrical Design (CAE)
-----------------Physical Design (CAD)
CONVERT SEMI-CUSTOM DESIGN INTO FULL-CUSTOM DESIGN
With its unique integrated design automation system, SSi can easily convert a semicustom design
into full-custom circuitry. This capability allows SSi's customers to reduce production costs by
converting an area-inefficient semicustom design into a high-performance full-custom design.
9-6
Custom/Semicustom
Capabilities
SOPHISTICATED DESIGN AUTOMA TlON TOOLS
The IDMTM design automation system, with proprietary and SSi-enhanced vendor software,
addresses both the electrical and physical phases of design.
GhromaliC 'Gri.ph1Cs tiormlnaland
Ethernet
VAX computer design statiorl$
CPA: Circuit path analyzer
$WtTCAP; Switched-capacitor simulator
FILSYN: Filter circuit synthesizer
NETED/SYMED: Schematic editors
PHSPICE: HSPICE pre-processor
DOC: Document editor
TANCELL: Automatic placer and router
ANITA: Automated network intertrace algorithm
ECAD: Design rules checks and pattern generation
ALICE: Automated layout for Ie engineering
HSPICE; AID circuit
HSPLOT; HSPICE graphic plotter
SILOS: Logic and fault simulator
81M: Digital logic simulator
T8IM: Timing simulation preprocessor
ELECTRICAL DESIGN
Electrical design is done on Mentor Graphics/Apolioengineering workstations with SSi-enhanced
software that provides schematic capture, simulation, synthesis, and documentation tools. This
software is supported by libraries of pre-designed cells and components. Due to our integrated
CAE environment, there is no distinction between any schematic capture, simulation, or synthesis
capabilities for full- or semicustom design approaches.
ANALOG AND DIGITAL SIMULATION
Simulation ensures that we meet the customer's performance specification before converting the
design into silicon. Circuit simulation, an important key to SSi's design methodology, allows us to
accurately simulate the performance numbers of our technologies. For circuit simulation, we use
Meta-Software's HSPICpM with a proprietary analog CMOS model that accurately predicts output
impedance and other analog parameters over a wide range of operating conditions and device
sizes. The HSPICE environment includes a fully hierarchical netlister, a preprocessor called
PHSPICE, and a Meta-Software graphic plotter called HSPLOT'M. For the analog simulation of
switched capacitors, we use Columbia University's SWITCAp'M.
For digital simulation, we use a proprietary version of SimuCad's SILOS'M that performs gate and
switch-level, zero-delay, functional logic and fault simulation. To analyze delays with a timingbased logic simulation, we use a combination of TSIM'M (developed on Meta-Software's Circuit
Path FinderTM) and SILOS.
9-7
Custom/Semicustom
Capabi Iities
DEVICE MODELING AND CHARACTERIZATION LABORATORY
Highly-accurate circuit simulation models and parameters are developed in SSi's state-of-the-art
Device Modeling and Characterization (DMC) laboratory. With capabilities including precision AC
measurement, RS1 statistical analysis, and worst-case modeling, the DMC lab provides complete
device model data for our processes.
PHYSICAL DESIGN
Physical design is done on Chromatics Graphics terminallY AX computer design stations. Our
proprietary, VAX-based program called ALlCFM(Automated Layout for Integrated Circuit Engineering) with other SSi-enhanced vendor software is used for graphical editing, digitizing, design
rules checking (DRC), circuit tracing, and pattern generation (PG).
AUTOMATIC PLACE AND ROUTE SOFTWARE
SSi's cell-based automatic place-and-route capability, which is based on Tangent's T ANCELL'" ,
performs physical design far more rapidly than can be done by hand. Extensive proprietary
software, developed to complement TANCELL, supports hierarchical routing, parameter passing,
library creation and maintenance, and CMOS switched-capacitor analog macro generation directly
from full-custom design. A random-logic digital macro assembler is in develooment. This flexible
place-and-route environment supports floorplanning, automatic chip construction, and the mix and
match of custom cells, standard cells, and compiled cells-all of which are used to reduce design
development time.
AUTOMATIC CIRCUIT TRACE AND VERIFICATION SOFTWARE
Using a proprietary circuit-trace program called ANITA'M, we compare the completed IC layout
database automatically to the Mentor schematic database to ensure that the layout implementation
matches the schematic design exactly. When this trace program is applied to CMOS and bipolar
mixed analog/digital designs, it performs a more detailed trace than is available through commerciallayout-versus-schematic (LVS) packages. ANITA allows SSi to dramatically reduce design
errors and minimize the time to product introduction.
DESIGN AUTOMATION BENEFITS
The proprietary IDM Design Automation system gives Silicon Systems the flexibility to create
increasingly complex ASIC designs for our customers while dramatically reducing design schedules, costs, and errors.
9-8
Custom/Semicustom
Capabilities
MANUFACTURING SUPPORTS BOTH CMOS AND BIPOLAR
TECHNOLOGIES
Silicon Systems is known in the ASIC industry for its commitment to producing standard and
custom ASICs using a broad range of CMOS and bipolar process technologies.
SSi continually invests in quality and capacity improvements to ensure that the company's wafer
fabrication, test, and assembly capabilities meet the latest manufacturing requirements. For
special functional capabilities (i.e., increased speed, bandwidths, response times, etc.), SSi's 4inch wafer fabrication facilities use sophisticated process techniques such as:
•
Stepper and projection photolithography for high resolution.
•
Positive resist and dry plasma etch for smaller feature size and minimal undercutting.
•
And high-current ion implantation and automated sputtering, which are used to improve productivity.
SSi can also meet a wide spectrum of assembly and packaging needs. Quick-turn, low-volume
assembly for prototypes is done in SSi's Tustin facility. High-volume production of plastic
packages in any of DIP, PLCC, or SO configurations is done in Silicon Systems' Singapore
Technology Center.
I
9-9
Custom/Semicustom
Capabilities
COMPUTER-AIDED MANUFACTURING WITH PROMIS ™
FOR RAPID DELIVERY OF RELIABLE ICs
Committed to Computer-Aided Manufacturing (CAM), Silicon Systems has invested in extensive
computer resources. To handle the vast amounts of data required for manufacturing, monitoring,
and statistical process control, SSi uses the Process and Management Information System
(PROMIS'M). The PROMIS system:
manages inventory information,
•
tracks wafers in process,
•
monitors the clean room environment, and
•
performs statistical process control.
PROMIS provides computer-controlled (i.e., paperless) facilities, which reduces sources of
contamination in the wafer fab clean rooms. SSi's wafer fab is a class "50" environment with class
"10" work surfaces. Cleanliness is maintained through the service chase approach, which
channels a minimum of 5 air exchanges per minute.
PROMIS allows Silicon Systems to deliver reliable ICs rapidly, thus allowing customers to
introduce products to the marketplace on schedule and within budget.
9-10
Custom/Semicustom
Capabilities
SS; WORKS WITH CUSTOMERS TO CREATE THE BEST IC SOLUTION
SSi has three IC design centers located in Tustin, California; Grass Valley, California; and
Singapore. An additional center in Silicon Valley will open by late 1988. Any of these design
centers can accept a functional specification and complete the entire design task using e.ither a fullcustom or a cell-based approach.
CUSTOMER INTERFACE FOR FULL-CUSTOM AND CELL-BASED DESIGNS
CUSTOMER
551
Design
Specifications
and Requirements
"" ,,;',,",,'
'tesIPrQgrl;lrnGn;Jatiot1
Photomask
Waferfat,l
"Proto!ype(Assembly,
"" Test,Stiip)
9-11
Custom/Semicustom
Capabilities
Or, a customer can complete most ofthe design, using array technology, and utilize SSi's expertise
for physical layout.
CUSTOMER INTERFACE FOR ARRAY-BASED DESIGNS
CUSTOMER
SSI
IC and Test Specification 1-----,
I
I
I
I
I
I
I
---------1...._------- 1
'---------1~1
.-------:1
Review Cells,
as Required
I
1
~--------T---~----J
I
I
I
I
I
I
Final Design Review
Interactive
Physical Layout
Schematics
Database Tape
Special Layout Information
Test Specification
Automatic Circuit
Trace
Test Program Creation
Photomask
Wafer Fab
Prototype
(AssembIY,Test, Ship)
9-12
J~ffunJ'"
Quality Assurance
________
N_N_O_VA_~_ORSIN IN_T_EG_RA
__T_IO_N________________a_n_d
__R_e_l_ia_b_i_lity
__~
TABLE OF CONTENTS
Section 1 A Message from Silicon Systems
President and CEO
1.1
1.2
Introduction
Quality Assurance and Reliability
Section 2 Quality Assurance
2.1
2.2
2.3
2.4
Quality Program
Process Control
PPM Program
Computer Aided Manufacturing Control
Section 3 Reliability
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
Reliability Program
Qualifications
Production Monitors
Evaluations
Failure Analysis
Data Collection & Presentation for
Improvement Projects
Reliability Methods
Reliability Prediction Methodology
CARMELa J. SANTORO
Chairman, President & CE.O
Section 4 Electrostatic Discharge Program
4.1
ESD Prevention
our environment. But we do strive for "zero defects"
for "just in time service" and for "doing it right the
SECTION 1
A MESSAGE FROM SILICON SYSTEMS'
PRESIDENT AND CEO
Quality is the secret to long term success. It literally
overshadows the short term emphasis on price,
delivery, or any other measure of performance.
At Silicon Systems, we have based our quality
philosophy on the development of a "state of mind"
in each employee, related to job performance and
to its reflection in the overall level of quality and
reliability of our product.
You won't hear very many cliches about quality in
first time." We think constant reminders of tired
phrases can serve more as an irritant than a stimulant. Our quality ethic is based on setting examples
for others and by intuitive "high quality" job performance propagating the quality ethic throughout
the organization to each employee.
To be sure, we have programs related to quality and
reliability. They are the subject of this brochure. We
al e dedicated to process control, overall product
reliability and outstanding outgoing quality. Rapid
analysis of failures and returns providing responsive
service to our customers also generates quick solutions to our own problems. We believe that the high
levels which we achieve in quality, reliability and
FIGURE 1.1 ORGANIZATION CHART
Assembly/Test & Finish
Process Control
Quality Engineering
a.A Corporate
Specification Writingl
Word Processing
Audits
Water Fabrication
Process Control
Final Outgoing
Inspection
Silicon Systems Singapore
Process Control
10-0
Quality Assurance
and Reliability
service are directly attributable to belief in the basIc
tenets of quality within our corporate culture.
1.2.1 Organization Philosophy
To facilitate the close cooperation and coordination
required of the Quality and Reliability functions, a
combined organization has been established. This
organization must have access to and support from
the top of the organization The R. & QA organization is shown in Figure 1.1.
1.1 INTRODUCTION
This brochure presents the basic quality and
reliability philosophy used by Silicon Systems
Silicon Systems' management philosophy is the
manufacture of a quality product consistent with
company policy and customer requirements. It is
the goal of the Quality Assurance and Reliability
departments to ensure that these requirements
are met.
SECTION 2
2.1
Included in this brochure is Silicon Systems' ongoing program for controlling and improving the quality
of devices manufactured.
The data clearly illustrates that Silicon Systems
is working diligently to maintain its position as a
leader in the industry. The use of highly specialized
equipment, test programs and test procedures
allows us to determine product reliability under
extreme conditions.
Quality is built into Silicon Systems' parts from rigid
incoming inspection of piece parts and materials to
stringent outgoing quality verification. The assembly
process flow is encompassed by an elaborate system of test and inspection gates and in-line monitors.
These gates and monitors ensure a step-by-step
adherence to prescribed procedure.
In addition, Silicon Systems is also incorporating
statistical process control into our manufacturing
operations. This approach of studying and improving
the quality of processes, products and services by
the use of statistical problem solving techniques,
analytical controls and quantitative methods ensures
that Silicon Systems' products maintain a high level
of quality and reliability. Our quality organization is
committed to working closely with you to provide
continuously improved incoming quality levels.
1.2 QUALITY ASSURANCE AND RELIABILITY
The quality of a semiconductor device is defined by
its conformance to specification; the reliability of a
semiconductor device is defined by how well it continues to conform to specification over time while
under stress. This relationship between quality and
reliabiiity requires a program that encompasses
both. Included in this brochure are outlines of our
process control program and our PPM (parts-permillion) program. These programs assure conformance to specification throughout the manufacturing process.
10-1
QUALITY ASSURANCE
QUALITY PROGRAM
Quality Assurance has the ultimate responsiblity for
the reliable performance of our products. This is
accomplished through the administration of formal
systems which assure that our products meet the
requirements of customer purchase orders, and
specifications for design, from raw materials
through finished product.
Quality Assurance supports formal qualifications of
suppliers, materials, processes, and products;
administration of system and production monitors to
assure that our products do meet the desired specifications; and the liaison between Silicon Systems
and the customer for all product-related problems.
It is the practice of Silicon Systems to have the
Quality and Reliability Program encompass all of its
activities, starting with a strong commitment of support for the program from the corporate. level, and
continuing with customer support after the product
has been shipped.
Silicon Systems firmly believes that quality must be
"built into" all of its products by ensuring that
employees are trained in the quality philosophy of
the company. Some of the features built into Silicon
Systems' Quality Program include:
1. Structured training programs directed at Wafer
Fabrication, Test, and Process Control personnel.
2. Stringent in-process inspection gates and
monitors.
3. Total evaluation of designs, materials, and
processing procedures.
4.· Stringent electrical testing (100% and redundant
QA AQL testing).
5. Ongoing reliability monitors and process
verifications.
6. Real time use of statistical process control
methodology.
7. Corporate level audits of manufacturing,
subcontractors, and suppliers.
These structured quality methods result in products
which deliver superior performance in the field.
Quality Assurance
and Reliability
2.1.1 Lot Acceptance Testing
At Silicon Systems, all sampling for Lot Acceptance
Testing is based upon MIL-STD-105D.
1. Commercial Testing includes resistance to solvents, Solution A, plus external Visual Inspection
to strict SSi standards.
In addition to these established gates, Silicon Systems also has established monitors during various
stages in the manufacturing process. It is this builtin quality that ensures failure-free shipment of
Silicon Systems' products.
Quality control monitors have been placed throughout the manufacturing flow, so that data may be
collected and analyzed to verify the results of
intermediate manufacturing steps. This data is used
to determine quality trends or long term changes in
the quality of specific operations. A general description of the product flow and QC inspection points
are shown in Figure 2.1.
2. Industrial Testing includes hermetic-only
Destructive Physical Analysis (DPA),as well as
Resistance to Solvents, Solutions A and B, plus
Solderability, Electrical @ 25°C, and external
Visual Inspection to SSi standards.
3. Extended Reliability covers hermetic-only DPA
and Burn-in, as well as Resistance to Solvents,
Solutions A, B, and C, pius Solderability, Fine and
Gross Leak Hermeticity, Electrical @ 25°C, and
external Visual Inspection to SSi standards.
FIGURE 2.1
PROCESS CONTROL GATES AND MONITORS
Wafer Fab Final Lot Acceptance
4. High Reliability includes Destructive Physical
Analysis and Bum-in, as well as Resistance to
Solvents, Solutions A, B, C, and 0, plus Solderability, Fine and Gross Leak Hermeticity, Electrical @
max/min temperature limits as well as 25°C, and
external Visual Inspection to SSi standards.
2.2
Wafer Probe Monitor
PROCESS CONTROL
Assembly Gates & Monitors
Silicon Systems' process control program is
designed to provide continuous visibility of the performance of manufacturing processes and ensures
that corrective action is taken before problems
develop.
AQL Sample
D
The principal areas of process control which assess
the quality of processed product against quality
standards are incoming materials inspection and
process control monitoring.
2.2.1
6.
Incoming Inspections
Ship to Customer
Incoming inspection plays a very important role in
Silicon Systems' quality program. Small deviations
from material specifications can transverse the
entire production cycle before being detected by
outgoing quality control. By paying strict attention to
quality at this early stage, the possibility of failures
occurring further down the line is greatly minimized.
2.2.2
o
In-Process Inspections
Every major manufacturing step is followed by an
appropriate in-process quality control inspection
gate. Silicon Systems has established inspection
gates in areas such as Wafer Fabrication, Wafer
Probe, Assembly, and Final Test areas.
2.3
Manufacturing
Process Control Gates
Process Control Monitor
1\ Quality Assurance
V
Final Outgoing Inspection
PPM PROGRAM
The main purpose of employing a PPM program is
to eliminate defects. The action portion of this program is accomplished in three stages:
1. Identify all defects by failure mode.
2. Identify defect causes and initiate corrective
action.
3. Measure results and set improved goals.
The data generated from an established PPM program is statistically compiled as a ratio of units
rejected/tested. This ratio is then expressed in
terms of parts per million (PPM) with a confidence
10-2
Quality Assurance
and Reliability
3.3 PRODUCTION MONITORS
limit attached. The eventual reported PPM result
therefore allows proper significance to be attached
to every defect found. The final aim or goal is to
achieve and maintain zero defects.
Based on significantly large volumes of PPM data
and an established five-year strategic plan identifyIng industry-wide competitive PPM goals, Silicon
Systems has progressively achieved excellent quality standards and will continue to measure the
results and, therefore, improve on PPM standards
as set by the industry.
This program has been established to randomly
select from production a statistically significant sample and subject it to the maximum stress test levels
to determine useful life of the product in a field use
environment.
The following pages show reliability methods that are
in use at Silicon Systems. The importance of production monitors at Silicon Systems does, in effect,
assure continued reliability.
3.4 EVALUATIONS
2.4
COMPUTER AIDED
MANUFACTURING CONTROL
The evaluation program at Silicon Systems is an
ongoing program that will continue defining standards which cover the reliability assessment of the
circuit portion, process parameters, and packaging
of a new product. This program continuously provides
performance characteristics of the products that are
part of the improvement projects at Silicon Systems.
Computer Aided Manufacturing (CAM) requires the
identification, control, collection and dissemination
of vast amounts of data for logistics control. Silicon
Systems uses this type of computerized system for
statistical process control and manufacturing
monitoring.
3.5 FAILURE ANALYSIS
PROM IS (Process Management and Information
System) displays document control-released
recipes, processes, and procedures, tracks work-inprocess, contains accurate inventory information,
allows continuous recording of facilities data, contains performance analysis capabilities, and much
more. PROMIS allows for a paperless facility, which
assists in keeping contamination out of the wafer
fab clean room.
The configuration of PROMIS has been tailored to
meet the requirements of Silicon Systems.
SECTION 3
RELIABILITY
3.1 RELIABILITY PROGRAM
Silicon Systems has defined various programs that
will continuously characterize product reliability levels. These programs are categorically described as:
1. Oualifications
2. Production monitors
3. Evaluations
4. Failure analysis
5. Data collection and presentation for improvement projects
3.2 QUALIFICATIONS
The application of this program ensures that all new
product designs, processes, and packaging meet
the absolute maximum rated design and worst case
end use criteria. The large data base generated by
means of the accelerated stress testing results in a
maximum confidence for determining the final use in
the production environment.
The failure analysis program is an integral part of
the Reliability Department at Silicon Systems. Being
aware of the low defect density requirements in the
industry along with the needed competitive edge,
Silicon Systems has formed a highly technical and
sophisticated failure analysis laboratory. This laboratory provides visual analysis, electrical reject mode
analysis, and both destructive and non-destructive
data to aid the engineers in their corrective
action for improvement programs, and to help our
customers implement improved field use designs.
This may include metallurgical, optical, chemical,
electrical and SEM with X-ray dispersive analysis
as needed.
Conclusively, this in-house testing and analysis
allows Silicon Systems to monitor all aspects of
manufacturing to ensure that a product of highest
quality is shipped to our customers.
3.6 DATA COLLECTION & PRESENTATION
FOR IMPROVEMENT PROJECTS
Data is collected from each of the above programs
and summarized for ease of understanding among
all engineering disciplines in the company. This data
facilitates improvement and provides our
customers an opportunity to review our product
performance.
3.7 RELIABILITY METHODS
The Reliability Program utilizes various stress tests
that are presently being used to define performance
levels of our products. Many of these stress tests are
per MIL-STD. 883C as shown on following page.
10-3
Quality Assurance
and Reliability
TABLE 3.1 RELIABILITY STRESS TESTS
TEST
CONDITIONS
Biased temperature/humidity
85°C/85o % RH
SECTION 4
ELECTROSTATIC DISCHARGE
PROGRAM
PURPOSE OF EVALUATION
4.1
Resistance to high humidity
with bias
High temperature operating life
Mil 883C
Method 1005
Resistance to electrical and
thermal stress
Highly accelerated
stress test
SSi Method
Evaluates package integrity
Steam pressure
121°C/15PSI
Resistance to high humidity
Temperature
cycling
Mil 883C
Method 1010
Resistance to thermal
excursion (air)
Thermal shock
Mil 883C
Method 1011
Resistance to thermal
excursion (liquid)
Salt atmosphere
Mil 883C
Method 1009
environment
Constant
acceleration
Mil 883C
Method 2001
Resistance to constant
acceleration
Silicon Systems' quality program incorporates various protection measures for the control of ESD.
Some of these preventive measures include handling
of parts at static safe-guarded work stations; the
wearing of wrist straps during ali handling operations;
the use of conductive lab coats in ali test areas and
areas which handle parts; and the packaging of components in conductive and anti-static containers.
Resistance to corrosive
Mechanical shock
Mil 883C
Method 2002
Resistance to mechanical
shocks
Solderability
Mil 883C
Method 2003
Evaluates solderabil.ity of
Lead integrity.
Mil 883C
Method 2004
Evaluates lead integrity before
board assembly
Vibration,
variable frequency
Mil 883C
Method 2007
Resistance to vibration
leads
Thermal resistance
Method-SSi
Evaluates thermal dissipation
Electrostatic damage
Method 3015
Evaluates ESD susceptibility
Latch-Up
SSi Method
Evaluates latch-up
susceptibility
Seal fine and gross leak
Mil Std 883C
Method 1014
Evaluates hermeticity of
sealed packages
ESD PREVENTION
Silicon Systems recognizes that procedures for the
protection of Electrostatic Discharge (ESD) sensitive devices from damage by electrical transients
and static electricity must be incorporated throughout all operations which come in contact with
these devices.
3.8 RELIABILITY PREDICTION
METHODOLOGY
It has been known in reliability engineering principles
that the failure rate of a group of devices as a function of time will follow a life curve as shown below:
failure
rate
random
time
The bath tub curve above, implies that the useful life
of the product extends until some basic design limitation is experienced. At SSi the Arrhenius Model is
used to extrapolate a failure rate at an accelerated
temperature test condition to a normal use temperature condition.
The model basically statesR ~ A e -Ea/KT
where R ~ Reaction rate
A ~ Constant
Ea ~ Activation energy (eV)
K ~ Boltzmann's constant 8.63 x 10- 5 eV/oK
T ~ Absolute temperature (OK)
10-4
SSi Ordering
Information
INNOVATORS IN INTEGRATION
i
SSi PACKAGING INDEX
I
I
DUAL-IN-L1NE PACKAGE (DIP)
Plastic
Ceramic
SURFACE MOUNTED DEVICES (SMD)
PLCC (Quad)
Small Outline (SOIC)
Flatpack
*SON is a 150 mil width package.
**SOL is a 300 mil width package.
***SOW is a 400 mil width package.
11-0
PINS
PAGE NO.
8 & 14
11-5
16 & 18
11-6
20,22 & 24S
11-7
24&28
11-8
32&40
11-9
8 & 16
11-10
18 & 22
11-11
24&28
11-12
LEADS
PAGE NO.
28& 44
11-13
52 &68
11-14
8,14 & 16 SON*
11-15
16 & 18 SOL**
11-16
20 & 24 SOL
11-17
28 & 34 SOL
11-18
32 SOW***
11-18
10,24,28 & 32
11-19
SSi Ordering
Information
INNOVATORS IN INTEGRATION
SSi PACKAGING MATRIX
Package Type
8
10
14
16
18
20
X
X
X
X
22
34
40
28
32
X
X
X
X
X
X
X
X
X
X
X
24
44
52
68
X
X
Plastic DIP
300 mil
X
S
X
400 mil
600 mil
X
Cerdip
300 mil
X
X
X
X
X
X
400 mil
600 mil
Side Braze
300 mil
X
X
X
X
S
X
400 mil
X
600 mil
Small Outline
150 mil
X
X
X
X
300 mil
X
X
400 mil
Flatpack
Chip Carrier
X
X
X
X
X
X
X
X
X
Plastic Quad
X
X
Ceramic Quad
X
X
11-1
X
MICROPERIPHERAL PRODUCTS PACKAGE TYPES
PACKAGE TYPE
DEVICE TYPE
SSI328450A
SSI328451
SSI328545
SSI32C452
SSI32C452A
SSI32C453
SSI320531
SSI3205321
SSI320534
SSI320535
SSI320536
SSI32H101A11012A
SSI32H116/1162
SSI32H523R
SSI32H566R
SSI32H567
SSI32H568
SSI32H569
SSI32M5901
SSI32M5902
SSI32M591
SSI32M593
SSI32M594
SSI32P540
SSI32P541
SSI32P544
SSI32P546
SSI32R104C
SSI32R104CL
SSI32R104CM
SSI32R108
SSI32R114
SS132R115-2
SS132R115-4
SS132R115-5
SS132R117/117R-2
SS132R117/117R-4
SS132R117/117R-6
P
F
H
Plastic
Flatpack
PLCC
52
44
44
44
44
44
28
28
28
40
40
40
40
24
28
28
32
28
N
L W
Small
Outline
32W
28
8
8
8N
8N
10
14N
14N
28
44
28
32
20
8
14
16
20
20
28
24
20L
16L
16L
20L
20L
28
28
44
24L
32W
24
24
24L
24L
24
24
18
22
24
18
22
28
24
28
24L
28
24L
28L
24
28
(Continued)
11-2
MICROPERIPHERAL PRODUCTS PACKAGE TYPES
(Cont)
PACKAGE TYPE
DEVICE TYPE
P
F
H
Plastic
18
Flatpack
PLCC
SSI32R117A1117AR-6
22
28
24
28
28
28L
SSI32R122
22
24L
28L
SSI 32R117Al117AR-2
SSI32R117A1117AR-4
24L
24
SSI32R188
SSI 32R501 /501 R-4
SS132R501/501 R-6
SSI 32R501/501 R-8
SS132R510Al510AR-2
28
40
18
28
28
32
44
SSI 32R51 OAl51 OAR-4
22
24
SSI 32R51 OAl51 OAR-6
28
28
SSI32R511/511R-4
SSI 32R511 /511 R-6
SSI32R511/511R-8
L W
Small
Outline
N
40
32
32W
20L
28
24L
28L
28
24L
28L
44
SSI 32R511 M/511 RM-6
SSI 32R511 M/511 RM-8
32W
28L
32W
SSI32R512/512R-8
SSI32R512/512R-9
32W
34L
SSI 32R512M/512RM-8
32W
SSI32R512M/512RM-9
34L
18L
SSI32R514/514R-2
SSI32R514/514R-4
SSI32R514/514R-6
SSI32R515/515R-9
SSI32R515/515R-10
28
34L
44
SSI32R515M/515RM-9
SSI 32R520/520R
34L
24
SSI 32R521/521 R
SSI32R522/522R-4
28
SS1340441
SSI34P570
28
28L
24
SSI32R522/522R-6
SSI 32R524R/524RM
SSI32R525R
SSI348580
24L
28L
28
24
28
28
28
28
28
28
SSI 34R575-2
SSI 34R575-4
24
SSI35P550
40
18
44
11-3
28L
32W,34L
24L
STANDARD PRODUCT MARKETING NUMBER DEFINITION
(R) =REQUIRED
(0) =OP11ONAL
RELEASE LEVEL (0)
(REVISION)
ATHROUGHE
PRODUCT CATEGORY (R)
....
....
I
.j::o.
32B
32C
32D
32H
32M
32P
32R
34B
34D
34P
34R
35P
73D
73K
73M
75T
78P
78A
HOD INTERFACE
HOD CONTROLLER
HDD DATA RECOVERY
HOD HEAD POSITIONING
HDD MOTOR SPEED CONTROllER
HDD PULSE DETECTION
HDD READlWRITE AMP
FOD INTERFACE
FDD DATA RECOVERY
FDD PULSE DETECTION
FDD REAOIWRITE AMP
TAPE DRIVE PULSE DETECTION
MODEM DEVICE SET
K-SERIES MODEM
MODEMIMODEM SUPPORT
TONE SIGNAliNG
DIGITAl TELECOM
ANAlOG TELECOM
NUMBER
OF
CHANNELS
0:
MODIFIERS (0)
J
K
W
LN
LQ
LR
M
S
SL
R
RM
U
BURN -IN (168 HOURS)
BURN -IN (48 HOURS)
LOW NOISE BURN -IN (168 HOURS)
LOW POWER
LOW NOISE
LOW NOISE, RESISTOR. MIRROR IMAGE
LOW NOISE, RESISTOR
MIRROR IMAGE
SERiAl VERSION
LOW POWER SERIAl
DAMPING RESISTOR
RESISTOR, MIRROR IMAGE
ON - CHIP UART
CANNOT USE A THROUGH E IN LEFT POSITION
PACKAGE TYPE (R)
C
D
F
H
P
T
S
N
W
SIDE-BRAZED CERAMIC
CERAMIC DIP
FLAT PACK
PLCC
PLASTIC DIP
METAL CAN
PLASTIC, SKINNY DIP
SMAlL OUTliNE, NARROW
(150 MIL)
SMAll OUTliNE, LARGE
(300 MIL)
SMAlL OUTliNE, WIDE
(400 MIL)
:~f%
I
TEMPERATURE RANGE (0)
C
M
COMMERCIAl (0 'C 10 +70 'C)
INDUSTRIAL (-40 '0 to +85 'C)
MILITARY (-55 '0 to 125 'C)
en
-en
a-·
00
""3c..
""
(I)
-""
o· s·
Q)
::J(Q
INTEGRATION
PLASTIC DIP
8 Pins
~ri~NNT~' 1
-0
ffin
400 (10.160)
_.~
!45 (3.680)
.
-'::1166041
.240 (6.096)
~
1-
.350 19.9801
. 21515.4611
551 Packaging
Diagrams
I.
I
I
I
.050(1.2701
.02010.508)
+
~--t
150138101")'--125 (3 (75)
J~
!--.,00TYP.(2.540)
17.8741 ~
iI .310
285 (7.239)
0-15 0
.015 (0.381)
.023 (0.584)
PLASTIC DIP
14 Pins
_ _ _ .770 (19.5581
.745 (18.923)
.200 (5.080)
.140 (3.5561
-1-1=r-.=1"'=r-~~~~~....d
.15013.810)-)--.125 13.1751
'-~~
f--.,00TYP.(2.540)
.015 (0.381)
.023 (0.584)
11-5
~
.28517.239)
551 Packaging
Diagrams
INNOVATORS IN INTEGRATION
PLASTIC DIP
16 Pins
\
260 (6.604)
.240 (6.096)
I
~_
"T;i2.0'if-l0(~5.08~0)
.140 (3.556)
I
.770(19.558)
.745 (18.923) - -
~
.070(1.778)
.015(0.381)
\
t
.150 (3.810) - ) ._.
125 (3.175)
~~
--.j
f--.100 TYP. (2.540)
~l
285 (7 239)
.015 (0.381)
.023 (0.584)
0-15°
PLASTIC DIP
18 Pins
~~
-1
1--.100 TYP.
(2.540)
.015 (0.381)
.023 (0.584)
~
~~
.285 (1239)
_
11-6
0-15 0
55i Packaging
Diagrams
INTEGRATION
PLASTIC DIP
20 Pins
24 Pins"
PIN NO.1
IDENT.
-DCJ
* .140 13.556
.1203.048
16. 8581
.265 16.731)
.24016.096)
__
I
1_~~~_~1~.0~40~(2~6.t.41~6)
1.010125.654)
I
1-----"
1.195130.3531
1.175 (29.845)
I
.20015.080)-1-\----~~
.14013.556)
*.135 13.4291
-:::r
.070 (1.778)
.02010.508)
* .015 (0.381)
~
r-
~~-t
.15013.810)
.12513.175)J
--Jl
~i=- .100 TYP. (2.540)
.310 (7.874)
.285IH39)
\
\--0-15 0
.015 (0.381)
.023 (0.584)
PLASTIC DIP
22 Pins
=~,1 ::::::::::I
200 15.080)
.14013.556)
)
.36019.144)
.33018.382)
j
-1-tr"Ffr=1"F=rFr"""Ar-F=r-=---=--,:"--~..d
.16014.064)-1-.120.( 3.048)
J.~ -I
--- --
!--.100TYP.(2.540)
_
.410 (10.414) _
.38019.652)
.01510.381)
.023 (0.584)
~
0_15 0
11-7
SSi Packaging
Diagrams
INTE.GRATION
PLASTIC DIP
24 Pins
~f
.580114.732)
PIN NO. '_-;:r-rcn:-:Tll"TTT-,-r;...,-,...,.rr-r-r""T"""T""T"..,.J
'515,1(13'081)
IDENT.
.20015.588)
.165 (4.19c)
r----r-------------------------~
I
.065 11.651)
.015 10.381)
I
--'
-'--
.160 (4.064) j'
.125 13.175)
JL
-..j
~.100(2.540)
.610115.494)
.585 (14.859)
.01510.381)
.023 (0.584)
PLASTIC DIP
28 Pins
~l
.560 (14.224)
PIN NO.
IDENT.
'--~~L:rr_rr__rT"""rr"T"T_.,_.,.....,rr_TT-,-,--,-,-.,...,.-,-,........J
1.450 (36.830) " '-u-' '-u-' V
__
"'''''''II
.165 14.1901
1.380(35.052),
'-u-' '-u-'
13
.530]1
.462)
I
~
~10.381)
~o
.. " .."
------.-
.16014.064)
.12513.175)___
I
~~ --l
~.'00(2.540)
.015 (0.381)
.023 (0.584)
11-8
SSi Packaging
Diagrams
INNOVATORS IN INTEGRATION
PLASTIC DIP
32 Pins
~I
.560 (14.224)
.530 (13.462)
PIN NO.1
IDENT.
Ir-r-r--r-r-r-r~--,-,--,-JJ
I------~\i\r--
11.670(42.4181
1.625(41.275)
'u-' 'i.r Y
Y
Y
'u-'
I
~
5.588)t6~ ~ ~
~
.165 (4.191
.220
--r
::~~I~:~~:I
----I
.015 (0.381)
~~ .023
(0.584)
f..-.l00(2.540)
.610 (15.494)
.585 (14.859)
PLASTIC DIP
40 Pins
~l
.560 (14.224)
.530 (13.462)
PINNO.1
IDENT.
.220 (5.588)
.165 (4.191)
::~~ I~:~~:I
h-r--r-r-r-r--r~J
1~-------4\N--
I~~
JL
.015 (0.381)
.023 (0.584)
I
I
2.070 (52.578)
2.020 (51.308)
~
--r
.01510.381)
.06511.651)
~
~
~.'00(2.540)
11-9
_ _ .610 (15.494)
.585 (14.859)
SSi Packaging
Diagrams
INTEGRATION
",---=O,=.400~
CERDIP
8 Pins
0.355
®0®®
o
Ii
--- ~
0.070
0.030
MAX
,
~:::::;::;;:::;:;;::::::::==l
0.060
0.420
i
0.4'0
MAX
0.023
0.015
CERDIP
22 Pins
'0:4201
t----
iMAX
~
g:~~~m~~t
~
i 0.2'5
0T70
~~
-----,.100TVP.(2.540)
---I
,1.100 MAX
ttif.f25
0.200
-II--
~
0.070
0.023
0.030
0,015
11-11
II
---I
-II-
~b~~~'{]c=J
r-
1
Jifuon Jl rskmJ'"
SSi Packaging
Diagrams
INNOVATORS IN INTEGRATION
CERDIP
24 Pins
CERDIP
28 Pins
I·
·1
'1.480 MAX
0.180
0.140
L··
1- 0.550 MAX<_I
~
-=1 -I ~ oo~
~ ~~
1 ~ ~mmJ
I
0.060
jOTJ~
0,020
(2.540)
0.008
0.07;
:1~
0.030
0.015
11-12
~:~~~
0-15°
SSi Packaging
Diagrams
INTEGRATION
SURFACE MOUNTED
QUAD (PLCC)
28 Leads
1 - - - - .495 (12.573) _ _~
.485 (12.319)
~~.~
.065(1.651)]
:::i;::1~'
::~ g~;~~l
.456 (11650)
~~'FEFEf'ETEiFB"ETd(l""'"
--l
~l
I--
050 (1.270)
I
.045 (1.140)
.020 (0508)
.016 (0.4.Q§)
.020 (0.508)
.390 (9.906)
.430 (10.922) -
I
.450(11430)~
.456 (\1.650) --'
LJ
SURFACE MOUNTED
QUAD (PLCC)
44 Leads
f - - - - - - - ~:~ ~~;~~~l-------l
.~~~ g;~~~l
.656 (16662)
~::rEFEfE'f"t:FEl"'EfEr~lJ'"
f-------
.~ ~ !~~~~~l ----~.I
11-13
~
-j
f---.050 (1.270)
.016 (0.406)
.020 (0.508)
)00-----
~~g g:~~~l-----..I
.045 (1.140)
.020 (0.508
INNOVATORS IN INTEGRATION
SSi Packaging
Diagrams
SURFACE MOUNTED
QUAD (PLCC)
52 Leads
+------ ~~; !~~~~~l------t
.020 (0.508)
.045(1.140)
.785 (19.939)
.795(20.193)
750 (19 050)
~
cr
~---- .,"'.~>~
.756 (19.202)
SURFACE MOUNTED
QUAD (PLCC)
68 Leads
+------ ~~; !~;:g~~l------t
.020 (0.508)
.0'4510,1140)
.985 (25.019)
.995 (25.273)
11-14
SSi Packaging
Diagrams
INTEGRATION
SON
8 Leads
.20015.080)
-- .185 (4.699)--
J
.010 10.254)
.07011.778)0
.00310.07S)
.OSO(1.524)
~I~
---------r
I--
.050 TYP. (1.270)
SON
14 Leads
I
PIN NO.
'---..t;:;=::;:;::::;:;=;:;:::::;::;=;::;::;::;:;l
BEVEL
~U'i:::::::
.ISO 14.0S4)
.,5
1
13.8,0)
--.-l
.010 10.254)
.003 (0.07S)
I
t
rrA
I
.245 (S.223)
.230 (5.842)
~,"~~"r
.17014.318)
f--
SON
.050 TYP. (1.270)
16 Leads
I
PIN NO.
'---1r:r=:n=:::;:;::::n=::;:;::::;::;::::::;:;:::n!I
BEVEL
.ISO (4.0S4)
1
.,5° (3.810)
('O.'SO)~]
.400
.380 (9.S52)
.070 (1.778)
.OSOIl.524)
O
f
~l
~
.010 (0.254)
.0031O.07S)
I
---------r
11-15
1
~I
JhJl rsfonf
SSi Packaging
Diagrams
INTEGRATION
r-
~
SOL
16 Leads
.050 TYP. (1.270)
1
J""
.305 (7.747)
PIN NO.1
BEVEL
---!=;:r:;::;::.;;:;=:;:;:::;:;;:::;:;=:r:;:::;;;;l.
~~:,'I,~::~,:I
LJ
11 []H 111111 C1H~(0076)
o
I
.110 (2.794)
.092 (2.336)
j
.010 (0.254)
r=~=l
laF~"'" ~I
c.F-------r-
8--H -H--U---LI----U
.335 (8.509)
.320 (8.128)
--j
I
~
.050 TYP (1.270)
SOL
18 Leads
r-~=l
~~
110 (2 794)
092(2336)
.010(0254)
.003 (0076)
~~
~
----r
laF~"~'~1
If.,,,,,.,j
.320 (8.128)
11-16
JifuonJi rJkmJ'~
SSi Packaging
Diagrams
INNOVATORS IN ~IN~T~E~G~RA~J~I~O::N~_ _ _ _ _ _ _ _ _ _ __
r---
.050 TYP (1.270)
SOL
20 Leads
SOL
24 Leads
~
r.050 TYP (1.270)
~~~~I
335 18.5091
:32018.1281
11-17
===J
SSi Packaging
Diagrams
INTEGRATION
--j
r-
·.040 TYP. (1.025)
SOL
28 Leads
34 Leads·
r=~~
I
ut= -•. , =h I
l('~I'''LJ
.320 8.128)
~ .050 TYP. (1.270)
SOW
32 Leads
l
.405 (10.287)
PIN NO.1
BEVEL
.iTn;=:r r Tri~r ;:;: r;: : ;:; ; :~:; ; :; :; ;:; ; IJ~
1 - - - - - - - - :~~~~:~~~l------~
I~~g~~l
~~~~J.f
I~
435(110491
420(106681
11-18
__
Jilicon Jl rJfonJw
SSi Flat Packages
INNOVATORS IN INTEGRATION
II--..
-I
- - A
FLAT PACK
24 Leads
~ 1
a
~
T
Pkg.
Type
Lead
F
=~L~w~~J==+ ~o,~
A
B
C
D
E
F
L
Q
W
10
.900
.015
.019
.045
.055
.090
max
.200
typ
.004
.007
.250
.260
.074
typ
.250
.260
F
24
.900
.050
typ
max
.567
typ
28
1.150
.045
.055
max
.645
.655
.004
.007
.004
.007
.391
.405
.712
.728
.075
typ
F
.015
.019
.015
.019
.085
.078
.264
.276
.492
.508
F
32
1.150
.015
.019
.045
.055
max
.745
.755
.004
.007
.812
.828
.085
.078
.492
.508
Cnt.
.087
.092
.092
11-19
arid Wid
&
INTEGRATION
Field Sales Network
North American
Regional Offices & Sales Representatives
NORTHWEST
SSI REGIONAL
Jon Tammel, RM
Silicon Systems, Inc.
2100 Augustine Dr.
Suite 219
Santa Clara, CA 95054
Ph: 408/980-9771
TLX: 171-200
FAX: 408/748-9488
CALIFORNIA
Magna Sales
Santa Clara
Ph: 408/727-8753
TLX: 171-200
FAX: 408/727-8573
CANADA
Enerlec
Surrey, BC
Ph: 604/888-1667
TLX: 04-365-634
FAX: 604/888-3381
COLORADO
Lange Sales
Uttleton
Ph: 303/795-3600
TLX: 450-017
FAX: 3031795-0373
OREGON
Western Technical Sales
Beaverton
Ph: 503/644-8860
FAX: 503/644-8200
UTAH
Lange Sales
Salt Lake City
Ph: 801/487-0843
FAX: 801/484-5408
WASHINGTON
Western Technical Sales
Bellevue
Ph: 206/641-3900
FAX: 206/641-5829
CALIFORNIA
Hadden Associates
San Diego
Ph: 619/565-9444
FAX: 619/565-1802
Western Technical Sales
Spokane
Ph: 509/922-7600
FAX: 509/922-7603
SCCubed
Thousand Oaks
Ph: 805/496-7307
FAX: 805/495-3601
SCCubed
Tustin
Ph: 714/731-9206
FAX: 714/731-7801
SOUTHWEST
SSI REGIONAL
Silicon Systems, Inc.
14351 Myford Road
Tustin, CA 92680
Ph: 714/731-7110
TWX: 472-2133
FAX: 7141669-8814
7141731-5457
NEW MEXICO
Western High Tech
Marketing Inc.
Albuquerque
Ph: 505/884-2256
FAX: 505/884-2258
Mel Marchbanks, RM
Silicon Systems, Inc.
(L.A. District)
454 Carson Plaza Drive
Suite 209
Carson, CA 90745
Ph: 213/532-1524,3499
FAX: 213/532-4571
ARIZONA
Western High Tech
Marketing, Inc.
Scottsdale
Ph: 602/860-2702
FAX: 602/860-2712
CENTRAL
SSI REGIONAL
Silicon Systems, Inc.
Tom George, RM
2201 N. Central Expressway
Suite 132
Richardson, TX 75080
Ph: 214/669-3381
FAX: 214/669-3495
ILLINOIS
Please call Regional
Office
Ph: 214/669-3381
12-1
INDIANA
Technology Marketing
Corporation (TMC)
Carmel
Ph: 317/844-8462
FAX: 317/573-5472
Fort Wayne
Ph: 219/432-5553
FAX: 219/432-5555
KANSAS
B. C. Electronics
Kansas City
Ph: 913/342-1211
FAX: 314/524-8906
Wichita
Ph: 3161722-0104
KENTUCKY
Technology Marketing
Corporation (TMC)
Louisville
Ph: 502/893-1377
FAX: 502/896-6679
MICHIGAN
A.P. Associates
Brighton
Ph: 313/229-6550
TLX: 816/287-310
FAX: 313/229-9356
MINNESOTA
Com-Tek
Eden Prairie
Ph: 612/941-7181
TWX: 310/431-0122
FAX: 612/941-4322
(Continued)
North American
Regional Offices & Sales Representatives (Continued)
EAST
CENTRAL (Cant.)
MISSOURI
B.C. Electronics
- St. Louis
Ph: 314/521-6683
OHIO
Makin Associates
Cincinnati
Ph: 513/871-2424
FAX: 513/871-2524
Columbus
Ph: 614/481-8898
FAX: 513/871-2524
Solon
Ph: 216/248-7370
FAX: 513/871-2524
TEXAS
OM Assoc., Inc.
Austin
Ph: 512/388-1151
FAX: 5121244-9505
Richardson
Ph: 214/690-6746
TWX: 910-860-5368
FAX: 214/690-8721
Houston
Ph: 713/789-4426
TLX: 791-363
FAX: 713/789-4825
WISCONSIN
Please call Regional
Office
Ph: 214/669-3381
551
B!;GIQ~AL
Wayne Taylor, RM
Silicon Systems, Inc.
53 Stiles Road
Salem, NH 03079
Ph: 603/898-1444
603/898-6721
603/898-6722
FAX: 603/898-9538
CONNECTICUT
NRG, Ltd.
Fairfield
Ph: 203/384-1112
FAX: 203/335-2127
CANADA· Ontario
Har-Tech
Downsview
Ph: 416/665-7773
FAX: 416/665-7290
Nepean
Ph: 6131726-9410
FAX: 613/726-8834
CANADA· Quebec
Har-Tech
Pointe Claire
Ph: 514/694-6110
FAX: 514/694-8501
MASSACHUSETTS
Mill-Bern Associates
Woburn
Ph: 617/932-3311
TWX: 710-332-0077
FAX: 617/932-0511
NEW YORK
Electra Sales
Rochester
Ph: 716/427-7860
TLX: 82-1722
FAX: 716/427-0614
Syracuse
Ph: 315/463-1248
TLX: 82-1721
FAX: 315/437-8283
Technical Marketing
Group
Melville
Ph: 516/351-8833
FAX: 516/351-8667
PENNSYLVANIA
Omni Sales
Erdenheim
Ph: 215/233-4600
FAX: 215/233-4702
ALABAMA
Technology Marketing
Associates (TMA)
Huntsville
Ph: 205/883-7893
TWX: 510-600-4721
FAX: 205/882-6162
GEORGIA
Technology Marketing
Associates (TMA)
Atlanta
Ph: 404/446-3565
TWX: 510-600-4721
FAX: 404/843-8705
NEW JERSEY
Technical Marketing
Group
Teaneck
Ph: 201/692-0200
FAX: 201/692-8367
12-2
FLORIDA
Technology Marketing
Associates (TMA)
Orlando
Ph: 407/857-3760
TWX: 510-600-4721
FAX: 407/857-6412
Pompano Beach
Ph: 305/977-9006
TWX: 510-600-4721
FAX: 305/977-9044
Largo
Ph: 813/541-1591
TWX: 510-600-4721
FAX: 813/545-8617
Melbourne
Ph: 407/676-3776
TWX: 510-600-4721
FAX: 407/676-4231
MARYLAND
Burgin-Kreh Associates
Baltimore
Ph: 301/265-8500
FAX: 301/265-8536
NO. CAROLINA
Technology Marketing
Associates (TMA)
Raleigh
Ph: 919/870-1084
FAX: 919/870-1085
TWX: 510-600-4721
VIRGINIA
Burgin-Kreh Associates
Lynchburg
Ph: 804/239-2626
FAX: 804/239-1333
International
Sales Representatives / Distributors
EUROPE
SSI EUROPEAN HDO
Silicon Systems, Int'I
R. Sharman, Tech. Sales
Mgr.
Woodpeckers
The Common
West Chiltington
Pulborough RH20 2PL
England
Ph: (44) 7983-2331
TLX: 878411
FAX: 44/7983-2117
GERMANY
Atlantik Elektronik GMBH
Munich
Ph: (49) 89-857-2086
FAX: (49) 89-857-3702
TWX: 521-511
SPAIN
Diode
Madrid
Ph: (34) 1-455-3686
TLX: 42148
FAX: 34-1-456-7159
GREECE
Peter Caritato & Associates Ltd.
Athens
Ph: (30) 1-361-9379
(30) 1-362-3614
FAX: (30) 1-364-6210
TLX: (863) 216-723
SWEDEN
Bexab Technology AB
Taeby
Ph: (46) 8-732-8980
FAX: (46) 8-732-7058
TLX: 13888 BEXTE S
BELGIUM
D & D Electronics BVBA
Antwerp
Ph: (32) 3-827-7934
FAX: (32) 3-828-7254
TLX: 73121 DDELEC
ISRAEL
Rapac
Tel Aviv
Ph: (972) 3-477115
TLX: (922) 342173
FAX: (972) 349-3272
DENMARK
C-88
Kokkedal
Ph: (45) 2-244888
FAX: (45) 2-244889
TLX: (855) 41198
ITALY
Cefra S.p.A.
Milano
Ph: (39) 223-5264
FAX (39) 2236-0249
TLX: 314543
ENGLAND
Pronto Electronic Systems Ltd
liford, Essex
Ph: (44) 1-554-6222
FAX: (44) 1-518-3222
TLX: (851) 895-4213
NETHERLANDS
Alcorn ElectroniCS BV
2908 LJ Capelle AID
IJSSEL
Ph: (31) 10-451-9553
FAX: (31) 10-458-6482
TLX: 26160
FINLAND
KomdelOy
Espoo
Ph: (358) 0-885011
TLX: (857) 121926
FAX: (358) 0-885-327
NORWAY
Hans H. Schive
Nesbru
Ph: (47) 2-845160
TLX: (856) 19124
FAX: (47) 2-846020
FRANCE
Datadis, S. A.
Boulogne
Ph: (33) 1-46-05-60-00
FAX: (33) 1-69-20-49-00
TLX: (842) 201-905
SO. AFRICA
South Continental Devices
Pinegowrie
Ph: (27) 11-789-2400
TLX: (960) 4-24849
FAX: (27) 11-787-0831
SWITZERLAND
EllypticAG
Zurich
Ph: (41)1- 493-100
TWX: 822-542
FAX: 011-41-1-700-2071
FAR EAST
AUSTRALIA
R&D Electronics
Victoria
Ph: 61-3-288-8911
TLX: (790) 33288
FAX: (61) 3-288-9168
HONG KONG
CET LTD
Wanchai
Ph: (852)5-200922
FAX: (852) 5-285764
TLX: (780) 85148
INDIA
Gaekwar Enterprise
Bombay
Ph: (91) 22-494-2583
TLX: 11-2633
FAX: 91-22-494-3459
JAPAN
Internix
Tokyo
Ph: (81) 3-369-1101
TLX: (781) 26733
FAX: (81) 3-366-8566
12-3
KOREA
Hanaro Corporation
Seoul
Ph: 82-2-784-1144,
1145,1146
TLX: (787) 26878
FAX: 82-2-784-0157
SINGAPORE
Dynamar International
Ph: (65) 747-6188
TLX: (786) 26283
FAX: (65) 747-2648
TAIWAN
Taipei
New Dynamar International
Ph: (886) 2-777-5670
thru 5674
TLX: (785) 11064 DYNAMAR
FAX: (886) 2-777-5867
SOUTH AMERICA
ARGENTINA
Yel S.R.L.
Buenos Aires
Ph: (54) 1-46-211
TLX: (390) 18605
FAX: (54) 1-45-2551
BRAZIL
Hitech
Sao Paulo
Ph: 55 (11) 53H~355
TLX: (391) 11-53288
HTHB BR
FAX: 55-240-2650
MEXICO
Panamtek
Mexico City
Ph: (525) 754-0426
TLX: 1173470
FAX: 011-754-6480
Guadalajara
Ph: (52) 36-303029
FAX: 52-36-30-3115
North American
Authorized Distributor Offices
All locations are "Hallmark Electronics" except as noted.
UNITED STATES
ALABAMA
Huntsville
Ph: 205/837-8700
ARIZONA
Phoenix
Ph: 602/437-1200
CALIFORNIA
Orange County
Ph: 714/669-4100
Aved,lnc.
Orange County
Ph: 714/259-8258
San Fernando Valley
Ph: 8181716-7300
San Diego·
Ph: 619/268-1201
Los Angeles
Ph: 2131217-8400
Sacramento
Ph: 9161722-8600
San Jose
Ph: 408/432-0900
CONNECTICUT
Wallingford
Ph: 203/271-2844
MASSACHUSETTS
Boston
Ph: 617/935-9777
OKLAHOMA
Tulsa
Ph: 918/665-3200
FLORIDA
Clearwater
Ph: 813/530-4543
MINNESOTA
Minneapolis
Ph: 612/941-2600
TEXAS
Austin
Ph: 512/258-8848
Orlando
Ph: 305/855-4020
MISSOURI
St. Louis
Ph: 314/291-5350
Dallas
Ph: 214/553-4300
Ft. Lauderdale
Ph: 305/971-9280
GEORGIA
Atlanta
Ph: 404/447-8000
NEW JERSEY
Philadelphia
Ph: 609/235-1900
Fairfield
Ph: 201/575-4415
ILLINOIS
Chicago
Ph: 312/860-3800
NEW YORK
New York City
Ph: 5161737-0600
INDIANA
Indianapolis
Ph: 317/291-5350
Rochester
Ph: 7161244-9290
KANSAS
Kansas City
Ph: 913/888-4747
NORTH CAROLINA
Raleigh
Ph: 919/872-0712
MARYLAND
BaltirnoreIWashington DC
Ph: 301/988-9800
OHIO
Cincinnati
Ph: 513/563-5980
COLORADO
Englewood
Ph: 303/790-1662
Houston
Ph: 713/781-6100
UTAH
Salt Lake City
Ph: 801/268-3779
WISCONSIN
Milwaukee
Ph: 414n97-7844
CANADA
ONTARIO
Valtrie Marketing
Toronto
Ph: 4161851-0355
BRITISH COLUMBIA
Enerlec
Vancouver
Ph: 604/888-1667
Cleveland
Ph: 216/349-5632
Columbus
Ph: 614/888-3313
Silicon Systems, Inc., 14351 Myford Road, Tustin,
12-4
CA 92680, (714) 731-7110, TWX 910-595-2809
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